From e0ab7bf6c16953e5cf688b7e4bfffe99e937c072 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 11 Dec 2021 19:10:02 +1000
Subject: [PATCH 001/712] =?UTF-8?q?gowin:=20BUGFIX.=20Place=20the=20ALU=20?=
 =?UTF-8?q?head=20in=20sli=D1=81e=200=20only?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/pack.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index 2616a913f3..4c6e28ca55 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -89,6 +89,9 @@ static void pack_alus(Context *ctx)
         }
         std::unique_ptr<CellInfo> packed_head = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_HEAD_ALULC");
 
+		// Head is always SLICE0
+		packed_head->constr_z = 0;
+		packed_head->constr_abs_z = true;
         if (ctx->verbose) {
             log_info("packed ALU head into %s. CIN net is %s\n", ctx->nameOf(packed_head.get()),
                      ctx->nameOf(cin_netId));

From df061b1a9c844f9f2d14b658edbaba190b8b8fe1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 11 Dec 2021 19:07:30 +0000
Subject: [PATCH 002/712] mistral: Add 'tools' dir to include path

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/mistral_ci.yml | 2 +-
 gui/mistral/family.cmake         | 2 +-
 mistral/family.cmake             | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 969005435a..afbb2ffd96 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: ea9691a720cc5695eab2fc580172be5c9e592760
+        MISTRAL_REVISION: ecd413421b3b559fc63db13da30275fcd5cd3881
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/gui/mistral/family.cmake b/gui/mistral/family.cmake
index c78ff6c1e4..072fa5cdc3 100644
--- a/gui/mistral/family.cmake
+++ b/gui/mistral/family.cmake
@@ -1 +1 @@
-target_include_directories(gui_mistral PRIVATE ${MISTRAL_ROOT}/libmistral ${CMAKE_BINARY_DIR}/libmistral)
+target_include_directories(gui_mistral PRIVATE ${MISTRAL_ROOT}/libmistral ${CMAKE_BINARY_DIR}/libmistral ${CMAKE_BINARY_DIR}/tools)
diff --git a/mistral/family.cmake b/mistral/family.cmake
index d2da396ae9..dcbab4ff10 100644
--- a/mistral/family.cmake
+++ b/mistral/family.cmake
@@ -8,6 +8,6 @@ add_subdirectory(${MISTRAL_ROOT}/libmistral ${CMAKE_CURRENT_BINARY_DIR}/libmistr
 find_package(LibLZMA REQUIRED)
 
 foreach(family_target ${family_targets})
-    target_include_directories(${family_target} PRIVATE ${MISTRAL_ROOT}/libmistral ${CMAKE_CURRENT_BINARY_DIR}/libmistral ${LIBLZMA_INCLUDE_DIRS})
+    target_include_directories(${family_target} PRIVATE ${MISTRAL_ROOT}/libmistral ${CMAKE_CURRENT_BINARY_DIR}/tools ${CMAKE_CURRENT_BINARY_DIR}/libmistral ${LIBLZMA_INCLUDE_DIRS})
     target_link_libraries(${family_target} PRIVATE mistral ${LIBLZMA_LIBRARIES})
 endforeach()

From 3c8af04ca587aa8056bbc583e1ecd0fae49e6276 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 11 Dec 2021 19:25:59 +0000
Subject: [PATCH 003/712] router2: Error instead of hang in case of reservation
 conflicts

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/router2.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/router2.cc b/common/router2.cc
index b93e7b35bc..051aa7f8d4 100644
--- a/common/router2.cc
+++ b/common/router2.cc
@@ -464,6 +464,9 @@ struct Router2
                 if (ctx->debug)
                     log("      %s\n", ctx->nameOfWire(cursor));
                 did_something |= (wd.reserved_net != net->udata);
+                if (wd.reserved_net != -1 && wd.reserved_net != net->udata)
+                    log_error("attempting to reserve wire '%s' for nets '%s' and '%s'\n", ctx->nameOfWire(cursor),
+                              ctx->nameOf(nets_by_udata.at(wd.reserved_net)), ctx->nameOf(net));
                 wd.reserved_net = net->udata;
                 if (cursor == src)
                     break;

From 35feb7ebbaa23e159d1ea5ca15da61e78aadaf57 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 12 Dec 2021 13:02:39 +0000
Subject: [PATCH 004/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/main.cc |  3 ++-
 nexus/pack.cc | 26 +++++++++++---------------
 2 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/nexus/main.cc b/nexus/main.cc
index 667b6d80dd..9fec8d5e80 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -52,7 +52,8 @@ po::options_description NexusCommandHandler::getArchOptions()
     specific.add_options()("pdc", po::value<std::string>(), "physical constraints file");
     specific.add_options()("no-post-place-opt", "disable post-place repacking (debugging use only)");
     specific.add_options()("no-pack-lutff", "disable packing (clustering) LUTs and FFs together");
-    specific.add_options()("carry-lutff-ratio", po::value<float>(), "ratio of FFs to be added to carry-chain LUT clusters");
+    specific.add_options()("carry-lutff-ratio", po::value<float>(),
+                           "ratio of FFs to be added to carry-chain LUT clusters");
 
     return specific;
 }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 0c771e8250..c3d9cba286 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2304,7 +2304,8 @@ struct NexusPacker
         }
     }
 
-    FFControlSet gather_ff_settings(CellInfo* cell) {
+    FFControlSet gather_ff_settings(CellInfo *cell)
+    {
         NPNR_ASSERT(cell->type == id_OXIDE_FF);
 
         FFControlSet ctrlset;
@@ -2321,7 +2322,8 @@ struct NexusPacker
         return ctrlset;
     }
 
-    void pack_lutffs () {
+    void pack_lutffs()
+    {
         log_info("Inferring LUT+FF pairs...\n");
 
         float carry_ratio = 1.0f;
@@ -2336,7 +2338,7 @@ struct NexusPacker
         dict<IdString, FFControlSet> cluster_ffinfo;
 
         size_t num_comb = 0;
-        size_t num_ff   = 0;
+        size_t num_ff = 0;
         size_t num_pair = 0;
         size_t num_glue = 0;
 
@@ -2361,13 +2363,11 @@ struct NexusPacker
             }
 
             // Check if the driver is a LUT and the direct connection is from F
-            CellInfo* lut = di->driver.cell;
+            CellInfo *lut = di->driver.cell;
             if (lut->type != id_OXIDE_COMB) {
                 continue;
             }
-            if (di->driver.port != id_F  &&
-                di->driver.port != id_OFX)
-            {
+            if (di->driver.port != id_F && di->driver.port != id_OFX) {
                 continue;
             }
 
@@ -2422,7 +2422,7 @@ struct NexusPacker
 
                 // No order not to make too large carry clusters pack only the
                 // given fraction of FFs there.
-                if(str_or_default(lut->params, id_MODE, "LOGIC") == "CCU2") {
+                if (str_or_default(lut->params, id_MODE, "LOGIC") == "CCU2") {
                     float r = (float)(ctx->rng() % 1000) * 1e-3f;
                     if (r > carry_ratio) {
                         continue;
@@ -2430,7 +2430,7 @@ struct NexusPacker
                 }
 
                 // Get the cluster root
-                CellInfo* root = ctx->cells.at(lut->cluster).get();
+                CellInfo *root = ctx->cells.at(lut->cluster).get();
 
                 // Constrain the FF relative to the LUT
                 ff->cluster = root->cluster;
@@ -2462,12 +2462,8 @@ struct NexusPacker
         }
 
         // Print statistics
-        log_info("    Created %zu LUT+FF pairs and extended %zu clusters using total %zu FFs and %zu LUTs\n",
-            num_pair,
-            num_glue,
-            num_ff,
-            num_comb
-        );
+        log_info("    Created %zu LUT+FF pairs and extended %zu clusters using total %zu FFs and %zu LUTs\n", num_pair,
+                 num_glue, num_ff, num_comb);
     }
 
     explicit NexusPacker(Context *ctx) : ctx(ctx) {}

From 78905c3ecf0cc283a79f064bf7e50aa6cdab2743 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 11 Dec 2021 19:38:14 +0000
Subject: [PATCH 005/712] mistral: DATAIN and DATAOUT of GPIO have swapped

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/io.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mistral/io.cc b/mistral/io.cc
index 3a72b001df..dab3672e28 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -31,9 +31,9 @@ void Arch::create_gpio(int x, int y)
         BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
         // FIXME: is the port index of zero always correct?
-        add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+        add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
         add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
-        add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
+        add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
         bel_data(bel).block_index = z;
     }
 }

From 61597e14a7fe488fcfc223d3109da1d30a2ec71b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 12 Dec 2021 13:55:06 +0000
Subject: [PATCH 006/712] mistral: Bump CI version

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/mistral_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index afbb2ffd96..7cf71621aa 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: ecd413421b3b559fc63db13da30275fcd5cd3881
+        MISTRAL_REVISION: 0edeca112dda9bd463125feb869ddb7511d1acd9
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies

From 80dd442412982af1901dcdf707ddc68379c20e0c Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Fri, 10 Dec 2021 15:46:15 +0800
Subject: [PATCH 007/712] ecp5: Use a vector rather than dict

This improves router1 performance vs the default dict
Using it for wire2net, pip2net, wire_fanout
---
 ecp5/arch.cc    | 21 +++++++++++
 ecp5/arch.h     | 97 ++++++++++++++++++++++++++++++++++++++++++-------
 ecp5/archdefs.h |  2 +
 3 files changed, 106 insertions(+), 14 deletions(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 34bdfa1b7f..ec64fb8284 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -123,6 +123,27 @@ Arch::Arch(ArchArgs args) : args(args)
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
+
+    wire_tile_vecidx.resize(chip_info->num_tiles, -1);
+    int n_wires = 0;
+    for (auto e : getWires()) {
+        if (e.index == 0) {
+            wire_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_wires;
+        }
+        n_wires++;
+    }
+    wire2net.resize(n_wires, nullptr);
+    wire_fanout.resize(n_wires, 0);
+
+    pip_tile_vecidx.resize(chip_info->num_tiles, -1);
+    int n_pips = 0;
+    for (auto e : getPips()) {
+        if (e.index == 0) {
+            pip_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_pips;
+        }
+        n_pips++;
+    }
+    pip2net.resize(n_pips, nullptr);
 }
 
 // -----------------------------------------------------------------------
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 1648c96282..585ae01dd3 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -447,7 +447,17 @@ struct Arch : BaseArch<ArchRanges>
     mutable dict<IdStringList, PipId> pip_by_name;
 
     std::vector<CellInfo *> bel_to_cell;
-    dict<WireId, int> wire_fanout;
+
+    // faster replacements for base_pip2net, base_wire2net
+    // indexed by get_pip_vecidx()
+    std::vector<NetInfo*> pip2net;
+    // indexed by get_wire_vecidx()
+    std::vector<NetInfo*> wire2net;
+    std::vector<int> wire_fanout;
+    // We record the index=0 offset into pip2net for each tile, allowing us to
+    // calculate any PipId's offset from pip.index and pip.location
+    std::vector<int32_t> pip_tile_vecidx;
+    std::vector<int32_t> wire_tile_vecidx;
 
     // fast access to  X and Y IdStrings for building object names
     std::vector<IdString> x_ids, y_ids;
@@ -614,21 +624,46 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
 
+    uint32_t get_wire_vecidx(const WireId & e) const {
+        uint32_t tile = e.location.y * chip_info->width + e.location.x;
+        int32_t base = wire_tile_vecidx.at(tile);
+        NPNR_ASSERT(base != -1);
+        int32_t i = base + e.index;
+        return i;
+    }
+
+    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(wire != WireId());
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
+        NPNR_ASSERT(w2n_entry == nullptr);
+        net->wires[wire].pip = PipId();
+        net->wires[wire].strength = strength;
+        w2n_entry = net;
+        this->refreshUiWire(wire);
+    }
     void unbindWire(WireId wire) override
     {
         NPNR_ASSERT(wire != WireId());
-        NPNR_ASSERT(base_wire2net[wire] != nullptr);
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
+        NPNR_ASSERT(w2n_entry != nullptr);
 
-        auto &net_wires = base_wire2net[wire]->wires;
+        auto &net_wires = w2n_entry->wires;
         auto it = net_wires.find(wire);
         NPNR_ASSERT(it != net_wires.end());
+
         auto pip = it->second.pip;
-        // As well as the default rules; need to handle fanout counting
         if (pip != PipId()) {
-            wire_fanout[getPipSrcWire(pip)]--;
+            pip2net.at(get_pip_vecidx(pip)) = nullptr;
+            wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
         }
-        BaseArch::unbindWire(wire);
+
+        net_wires.erase(it);
+        w2n_entry = nullptr;
+        this->refreshUiWire(wire);
     }
+    virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
+    NetInfo *getBoundWireNet(WireId wire) const override { return wire2net.at(get_wire_vecidx(wire)); }
 
     DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
 
@@ -667,17 +702,54 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
 
+    uint32_t get_pip_vecidx(const PipId & e) const {
+        uint32_t tile = e.location.y * chip_info->width + e.location.x;
+        int32_t base = pip_tile_vecidx.at(tile);
+        NPNR_ASSERT(base != -1);
+        int32_t i = base + e.index;
+        return i;
+    }
+
     void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
     {
-        wire_fanout[getPipSrcWire(pip)]++;
-        BaseArch::bindPip(pip, net, strength);
+        NPNR_ASSERT(pip != PipId());
+        wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]++;
+
+        auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
+        NPNR_ASSERT(p2n_entry == nullptr);
+        p2n_entry = net;
+
+        WireId dst = this->getPipDstWire(pip);
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
+        NPNR_ASSERT(w2n_entry == nullptr);
+        w2n_entry = net;
+        net->wires[dst].pip = pip;
+        net->wires[dst].strength = strength;
     }
 
     void unbindPip(PipId pip) override
     {
-        wire_fanout[getPipSrcWire(pip)]--;
-        BaseArch::unbindPip(pip);
+        NPNR_ASSERT(pip != PipId());
+        wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
+
+        auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
+        NPNR_ASSERT(p2n_entry != nullptr);
+        WireId dst = this->getPipDstWire(pip);
+
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
+        NPNR_ASSERT(w2n_entry != nullptr);
+        w2n_entry = nullptr;
+
+        p2n_entry->wires.erase(dst);
+        p2n_entry = nullptr;
+    }
+    bool checkPipAvail(PipId pip) const override { return getBoundPipNet(pip) == nullptr; }
+    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    {
+        NetInfo *bound_net = getBoundPipNet(pip);
+        return bound_net == nullptr || bound_net == net;
     }
+    NetInfo *getBoundPipNet(PipId pip) const override { return pip2net.at(get_pip_vecidx(pip)); }
 
     AllPipRange getPips() const override
     {
@@ -713,10 +785,7 @@ struct Arch : BaseArch<ArchRanges>
     DelayQuad getPipDelay(PipId pip) const override
     {
         NPNR_ASSERT(pip != PipId());
-        int fanout = 0;
-        auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip));
-        if (fnd_fanout != wire_fanout.end())
-            fanout = fnd_fanout->second;
+        int fanout = wire_fanout[get_wire_vecidx(getPipSrcWire(pip))];
         delay_t min_dly =
                 speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_base_delay +
                 fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index 5921954463..80e7810c18 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -156,6 +156,8 @@ struct ArchNetInfo
 
 typedef IdString ClusterId;
 
+struct NetInfo;
+
 struct ArchCellInfo : BaseClusterInfo
 {
     struct

From fc5b34254f47ef76150ec9f9edc85cda20681656 Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Fri, 10 Dec 2021 22:10:33 +0800
Subject: [PATCH 008/712] ecp5: Keep "visited" local

Otherwise it keeps growing boundless and slows down small arcs
---
 common/router1.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/router1.cc b/common/router1.cc
index c8585b0b7c..0ff2bedd76 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -108,7 +108,6 @@ struct Router1
     dict<arc_key, pool<WireId>> arc_to_wires;
     pool<arc_key> queued_arcs;
 
-    dict<WireId, QueuedWire> visited;
     std::priority_queue<QueuedWire, std::vector<QueuedWire>, QueuedWire::Greater> queue;
 
     dict<WireId, int> wireScores;
@@ -503,7 +502,7 @@ struct Router1
             std::priority_queue<QueuedWire, std::vector<QueuedWire>, QueuedWire::Greater> new_queue;
             queue.swap(new_queue);
         }
-        visited.clear();
+        dict<WireId, QueuedWire> visited;
 
         // A* main loop
 

From 0dafcc44ffcbe747babdadbb33d4dc140b5ea87c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 12 Dec 2021 18:48:39 +0000
Subject: [PATCH 009/712] router2: Improve reservation debug logging

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/router2.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/common/router2.cc b/common/router2.cc
index 051aa7f8d4..d713cce288 100644
--- a/common/router2.cc
+++ b/common/router2.cc
@@ -453,12 +453,14 @@ struct Router2
     {
         bool did_something = false;
         WireId src = ctx->getNetinfoSourceWire(net);
-        for (auto sink : ctx->getNetinfoSinkWires(net, net->users.at(i))) {
+        auto &usr = net->users.at(i);
+        for (auto sink : ctx->getNetinfoSinkWires(net, usr)) {
             pool<WireId> rsv;
             WireId cursor = sink;
             bool done = false;
             if (ctx->debug)
-                log("reserving wires for arc %d of net %s\n", int(i), ctx->nameOf(net));
+                log("reserving wires for arc %d (%s.%s) of net %s\n", int(i), ctx->nameOf(usr.cell),
+                    ctx->nameOf(usr.port), ctx->nameOf(net));
             while (!done) {
                 auto &wd = wire_data(cursor);
                 if (ctx->debug)

From a933f82845e489af7f5e209d2d43ff79b4c521ca Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 12 Dec 2021 18:49:37 +0000
Subject: [PATCH 010/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.h   | 10 ++++++----
 gowin/pack.cc |  6 +++---
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/ecp5/arch.h b/ecp5/arch.h
index 585ae01dd3..a570637954 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -450,9 +450,9 @@ struct Arch : BaseArch<ArchRanges>
 
     // faster replacements for base_pip2net, base_wire2net
     // indexed by get_pip_vecidx()
-    std::vector<NetInfo*> pip2net;
+    std::vector<NetInfo *> pip2net;
     // indexed by get_wire_vecidx()
-    std::vector<NetInfo*> wire2net;
+    std::vector<NetInfo *> wire2net;
     std::vector<int> wire_fanout;
     // We record the index=0 offset into pip2net for each tile, allowing us to
     // calculate any PipId's offset from pip.index and pip.location
@@ -624,7 +624,8 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
 
-    uint32_t get_wire_vecidx(const WireId & e) const {
+    uint32_t get_wire_vecidx(const WireId &e) const
+    {
         uint32_t tile = e.location.y * chip_info->width + e.location.x;
         int32_t base = wire_tile_vecidx.at(tile);
         NPNR_ASSERT(base != -1);
@@ -702,7 +703,8 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
 
-    uint32_t get_pip_vecidx(const PipId & e) const {
+    uint32_t get_pip_vecidx(const PipId &e) const
+    {
         uint32_t tile = e.location.y * chip_info->width + e.location.x;
         int32_t base = pip_tile_vecidx.at(tile);
         NPNR_ASSERT(base != -1);
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 4c6e28ca55..cb63f1c95a 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -89,9 +89,9 @@ static void pack_alus(Context *ctx)
         }
         std::unique_ptr<CellInfo> packed_head = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_HEAD_ALULC");
 
-		// Head is always SLICE0
-		packed_head->constr_z = 0;
-		packed_head->constr_abs_z = true;
+        // Head is always SLICE0
+        packed_head->constr_z = 0;
+        packed_head->constr_abs_z = true;
         if (ctx->verbose) {
             log_info("packed ALU head into %s. CIN net is %s\n", ctx->nameOf(packed_head.get()),
                      ctx->nameOf(cin_netId));

From 90b0e90bbe2fb923154096a8be3660b5e3f4cbb0 Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Sun, 12 Dec 2021 16:52:01 +0800
Subject: [PATCH 011/712] ecp5: Reduce some chipdb fields sizes

This reduces the final binary size by ~7 MB for 85k
---
 ecp5/arch.h            | 11 +++++------
 ecp5/trellis_import.py | 18 ++++++++++--------
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/ecp5/arch.h b/ecp5/arch.h
index a570637954..e7bf64fe81 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -54,11 +54,10 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     LocationPOD rel_src_loc, rel_dst_loc;
-    int32_t src_idx, dst_idx;
-    int32_t timing_class;
-    int16_t tile_type;
+    int16_t src_idx, dst_idx;
+    int16_t timing_class;
+    int8_t tile_type;
     int8_t pip_type;
-    int8_t padding_0;
 });
 
 NPNR_PACKED_STRUCT(struct PipLocatorPOD {
@@ -68,8 +67,8 @@ NPNR_PACKED_STRUCT(struct PipLocatorPOD {
 
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
-    int32_t type;
-    int32_t tile_wire;
+    int16_t type;
+    int16_t tile_wire;
     RelSlice<PipLocatorPOD> pips_uphill, pips_downhill;
     RelSlice<BelPortPOD> bel_pins;
 });
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 945f6e9303..2e76fb7453 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -196,12 +196,15 @@ def s(self, s, comment):
         print("str |%s| %s" % (s, comment))
 
     def u8(self, v, comment):
+        assert -128 <= int(v) <= 127
         if comment is None:
             print("u8 %d" % (v,))
         else:
             print("u8 %d %s" % (v, comment))
 
     def u16(self, v, comment):
+        # is actually used as signed 16 bit
+        assert -32768 <= int(v) <= 32767
         if comment is None:
             print("u16 %d" % (v,))
         else:
@@ -413,17 +416,16 @@ def get_wire_name(arc_loctype, rel, idx):
             for arc in loctype.arcs:
                 write_loc(arc.srcWire.rel, "src")
                 write_loc(arc.sinkWire.rel, "dst")
-                bba.u32(arc.srcWire.id, "src_idx")
-                bba.u32(arc.sinkWire.id, "dst_idx")
+                bba.u16(arc.srcWire.id, "src_idx")
+                bba.u16(arc.sinkWire.id, "dst_idx")
                 src_name = get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id)
                 snk_name = get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)
-                bba.u32(get_pip_class(src_name, snk_name), "timing_class")
-                bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
+                bba.u16(get_pip_class(src_name, snk_name), "timing_class")
+                bba.u8(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
                 cls = arc.cls
                 if cls == 1 and "PCS" in snk_name or "DCU" in snk_name or "DCU" in src_name:
                    cls = 2
                 bba.u8(cls, "pip_type")
-                bba.u8(0, "padding")
         if len(loctype.wires) > 0:
             for wire_idx in range(len(loctype.wires)):
                 wire = loctype.wires[wire_idx]
@@ -447,11 +449,11 @@ def get_wire_name(arc_loctype, rel, idx):
             for wire_idx in range(len(loctype.wires)):
                 wire = loctype.wires[wire_idx]
                 bba.s(ddrg.to_str(wire.name), "name")
-                bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
+                bba.u16(constids[wire_type(ddrg.to_str(wire.name))], "type")
                 if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
-                    bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
+                    bba.u16(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
                 else:
-                    bba.u32(0, "tile_wire")
+                    bba.u16(0, "tile_wire")
                 bba.r_slice("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, len(wire.arcsUphill), "pips_uphill")
                 bba.r_slice("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, len(wire.arcsDownhill), "pips_downhill")
                 bba.r_slice("loc%d_wire%d_belpins" % (idx, wire_idx) if len(wire.belPins) > 0 else None, len(wire.belPins), "bel_pins")

From f36188f2e18783ea692f8b6132712a0d1da6b6b7 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 13 Dec 2021 16:04:45 +0000
Subject: [PATCH 012/712] ecp5: LUT permutation support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .cirrus/Dockerfile.ubuntu20.04 |  2 +-
 ecp5/arch.cc                   |  4 +++
 ecp5/arch.h                    | 50 +++++++++++++++++++++++++++--
 ecp5/archdefs.h                |  1 +
 ecp5/bitstream.cc              | 58 ++++++++++++++++++++++++++++++++--
 ecp5/main.cc                   |  3 ++
 ecp5/pack.cc                   |  4 ++-
 ecp5/trellis_import.py         |  4 ++-
 8 files changed, 118 insertions(+), 8 deletions(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index 2e39058d09..4f229d2d38 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -48,7 +48,7 @@ RUN set -e -x ;\
     cd /usr/local/src ;\
     git clone --recursive https://github.com/YosysHQ/prjtrellis.git ;\
     cd prjtrellis ;\
-    git reset --hard 210a0a72757d57b278ac7397ae6b14729f149b10 ;\
+    git reset --hard 7239331d5463321d4864164f320beef67310f1e5 ;\
     cd libtrellis ;\
     cmake . ;\
     make -j $(nproc) ;\
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index ec64fb8284..95a2768285 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -144,6 +144,8 @@ Arch::Arch(ArchArgs args) : args(args)
         n_pips++;
     }
     pip2net.resize(n_pips, nullptr);
+
+    lutperm_allowed.resize(chip_info->width * chip_info->height * 4);
 }
 
 // -----------------------------------------------------------------------
@@ -625,6 +627,8 @@ bool Arch::route()
 {
     std::string router = str_or_default(settings, id("router"), defaultRouter);
 
+    disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
+
     setup_wire_locations();
     route_ecp5_globals(getCtx());
     assignArchInfo();
diff --git a/ecp5/arch.h b/ecp5/arch.h
index e7bf64fe81..51a919bb41 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -58,8 +58,15 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
     int16_t timing_class;
     int8_t tile_type;
     int8_t pip_type;
+    int16_t lutperm_flags;
+    int16_t padding;
 });
 
+inline bool is_lutperm_pip(int16_t flags) { return flags & 0x4000; }
+inline uint8_t lutperm_lut(int16_t flags) { return (flags >> 4) & 0x7; }
+inline uint8_t lutperm_out(int16_t flags) { return (flags >> 2) & 0x3; }
+inline uint8_t lutperm_in(int16_t flags) { return flags & 0x3; }
+
 NPNR_PACKED_STRUCT(struct PipLocatorPOD {
     LocationPOD rel_loc;
     int32_t index;
@@ -446,6 +453,14 @@ struct Arch : BaseArch<ArchRanges>
     mutable dict<IdStringList, PipId> pip_by_name;
 
     std::vector<CellInfo *> bel_to_cell;
+    enum class LutPermRule
+    {
+        NONE,
+        CARRY,
+        ALL,
+    };
+    std::vector<LutPermRule> lutperm_allowed;
+    bool disable_router_lutperm = false;
 
     // faster replacements for base_pip2net, base_wire2net
     // indexed by get_pip_vecidx()
@@ -509,6 +524,12 @@ struct Arch : BaseArch<ArchRanges>
         return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
     }
 
+    int get_slice_index(int x, int y, int slice) const
+    {
+        NPNR_ASSERT(slice >= 0 && slice < 4);
+        return (y * chip_info->width + x) * 4 + slice;
+    }
+
     void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
     {
         NPNR_ASSERT(bel != BelId());
@@ -517,6 +538,11 @@ struct Arch : BaseArch<ArchRanges>
         bel_to_cell[idx] = cell;
         cell->bel = bel;
         cell->belStrength = strength;
+        if (getBelType(bel) == id_TRELLIS_SLICE) {
+            lutperm_allowed.at(get_slice_index(bel.location.x, bel.location.y, getBelLocation(bel).z)) =
+                    (cell->sliceInfo.is_memory ? LutPermRule::NONE
+                                               : (cell->sliceInfo.is_carry ? LutPermRule::CARRY : LutPermRule::ALL));
+        }
         refreshUiBel(bel);
     }
 
@@ -744,11 +770,31 @@ struct Arch : BaseArch<ArchRanges>
         p2n_entry->wires.erase(dst);
         p2n_entry = nullptr;
     }
-    bool checkPipAvail(PipId pip) const override { return getBoundPipNet(pip) == nullptr; }
+    bool is_pip_blocked(PipId pip) const
+    {
+        auto &pip_data = loc_info(pip)->pip_data[pip.index];
+        int lp = pip_data.lutperm_flags;
+        if (is_lutperm_pip(lp)) {
+            if (disable_router_lutperm)
+                return true;
+            auto rule = lutperm_allowed.at(get_slice_index(pip.location.x, pip.location.y, lutperm_lut(lp) / 2));
+            if (rule == LutPermRule::NONE) {
+                // Permutation not allowed
+                return true;
+            } else if (rule == LutPermRule::CARRY) {
+                // Can swap A/B and C/D only
+                int i = lutperm_out(lp), j = lutperm_in(lp);
+                if ((i / 2) != (j / 2))
+                    return true;
+            }
+        }
+        return false;
+    }
+    bool checkPipAvail(PipId pip) const override { return (getBoundPipNet(pip) == nullptr) && !is_pip_blocked(pip); }
     bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
     {
         NetInfo *bound_net = getBoundPipNet(pip);
-        return bound_net == nullptr || bound_net == net;
+        return (bound_net == nullptr || bound_net == net) && !is_pip_blocked(pip);
     }
     NetInfo *getBoundPipNet(PipId pip) const override { return pip2net.at(get_pip_vecidx(pip)); }
 
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index 80e7810c18..dd260a3e87 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -165,6 +165,7 @@ struct ArchCellInfo : BaseClusterInfo
         bool using_dff;
         bool has_l6mux;
         bool is_carry;
+        bool is_memory;
         IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
         int sd0, sd1;
     } sliceInfo;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 338c4f201a..de6c711ece 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -522,6 +522,55 @@ static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
     cc.tiles[tile].add_arc(sink, source);
 }
 
+static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, int k, unsigned orig_init)
+{
+    std::array<std::vector<unsigned>, 4> phys_to_log;
+    const std::array<IdString, 4> ports{k ? id_A1 : id_A0, k ? id_B1 : id_B0, k ? id_C1 : id_C0, k ? id_D1 : id_D0};
+    for (unsigned i = 0; i < 4; i++) {
+        WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
+        for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+            if (!ctx->getBoundPipNet(pip))
+                continue;
+            unsigned lp = ctx->loc_info(pip)->pip_data[pip.index].lutperm_flags;
+            if (!is_lutperm_pip(lp)) { // non-permuting
+                phys_to_log[i].push_back(i);
+            } else { // permuting
+                unsigned from_pin = lutperm_in(lp);
+                unsigned to_pin = lutperm_out(lp);
+                NPNR_ASSERT(to_pin == i);
+                phys_to_log[from_pin].push_back(i);
+            }
+        }
+    }
+    for (unsigned i = 0; i < 4; i++)
+        if (!phys_to_log.at(i).empty())
+            used_phys_pins.insert(ports.at(i));
+    if (cell->sliceInfo.is_carry) {
+        // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
+        for (unsigned i = 0; i < 4; i++) {
+            if (!phys_to_log.at(i).empty())
+                continue;
+            for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
+                if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
+                    phys_to_log.at(i).push_back(j);
+            }
+        }
+    }
+    unsigned permuted_init = 0;
+    for (unsigned i = 0; i < 16; i++) {
+        unsigned log_idx = 0;
+        for (unsigned j = 0; j < 4; j++) {
+            if ((i >> j) & 0x1) {
+                for (auto log_pin : phys_to_log[j])
+                    log_idx |= (1 << log_pin);
+            }
+        }
+        if ((orig_init >> log_idx) & 0x1)
+            permuted_init |= (1 << i);
+    }
+    return permuted_init;
+}
+
 static std::vector<bool> parse_config_str(const Property &p, int length)
 {
     std::vector<bool> word;
@@ -787,12 +836,15 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
         }
         BelId bel = ci->bel;
         if (ci->type == ctx->id("TRELLIS_SLICE")) {
+            pool<IdString> used_phys_pins;
             std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
             std::string slice = ctx->loc_info(bel)->bel_data[bel.index].name.get();
             int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
             int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
-            cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
-            cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
+            cc.tiles[tname].add_word(slice + ".K0.INIT",
+                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 0, lut0_init), 16));
+            cc.tiles[tname].add_word(slice + ".K1.INIT",
+                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 1, lut1_init), 16));
             cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
             cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
             cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
@@ -854,7 +906,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
             // Tie unused inputs high
             for (auto input : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1}) {
-                if (ci->ports.find(input) == ci->ports.end() || ci->ports.at(input).net == nullptr) {
+                if (!used_phys_pins.count(input)) {
                     cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + "MUX", "1");
                 }
             }
diff --git a/ecp5/main.cc b/ecp5/main.cc
index f3861149d4..1864548bac 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -85,6 +85,7 @@ po::options_description ECP5CommandHandler::getArchOptions()
     specific.add_options()(
             "out-of-context",
             "disable IO buffer insertion and global promotion/routing, for building pre-routed blocks (experimental)");
+    specific.add_options()("disable-router-lutperm", "don't allow the router to permute LUT inputs");
 
     return specific;
 }
@@ -255,6 +256,8 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext(dict<std::string, Pro
     ctx->settings[ctx->id("arch.speed")] = speedString(ctx->archArgs().speed);
     if (vm.count("out-of-context"))
         ctx->settings[ctx->id("arch.ooc")] = 1;
+    if (vm.count("disable-router-lutperm"))
+        ctx->settings[ctx->id("arch.disable_router_lutperm")] = 1;
     return ctx;
 }
 
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index cbf882a88a..85d92336c2 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -3253,7 +3253,9 @@ void Arch::assignArchInfo()
             ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
             ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
             ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-            ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2";
+            std::string mode = str_or_default(ci->params, id("MODE"), "LOGIC");
+            ci->sliceInfo.is_carry = (mode == "CCU2");
+            ci->sliceInfo.is_memory = (mode == "DPRAM" || mode == "RAMW");
             ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id("REG0_SD"), "0"));
             ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id("REG1_SD"), "0"));
             ci->sliceInfo.has_l6mux = false;
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 2e76fb7453..a586db7b90 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -426,6 +426,8 @@ def get_wire_name(arc_loctype, rel, idx):
                 if cls == 1 and "PCS" in snk_name or "DCU" in snk_name or "DCU" in src_name:
                    cls = 2
                 bba.u8(cls, "pip_type")
+                bba.u16(arc.lutperm_flags, "lutperm_flags")
+                bba.u16(0, "padding")
         if len(loctype.wires) > 0:
             for wire_idx in range(len(loctype.wires)):
                 wire = loctype.wires[wire_idx]
@@ -623,7 +625,7 @@ def main():
     # print("Initialising chip...")
     chip = pytrellis.Chip(dev_names[args.device])
     # print("Building routing graph...")
-    ddrg = pytrellis.make_dedup_chipdb(chip)
+    ddrg = pytrellis.make_dedup_chipdb(chip, include_lutperm_pips=True)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_timing_data()

From fdf26e698f751c92445a0323d7892869598ca9ce Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 14 Dec 2021 14:09:27 +1000
Subject: [PATCH 013/712] gowin: Fix spelling of messages

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 6641df72ff..99e0ce6115 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -705,7 +705,7 @@ Arch::Arch(ArchArgs args) : args(args)
         }
     }
     if (package_name == IdString()) {
-        log_error("Unsuported partnumber '%s'.\n", args.partnumber.c_str());
+        log_error("Unsupported partnumber '%s'.\n", args.partnumber.c_str());
     }
 
     // setup timing info
@@ -719,7 +719,7 @@ Arch::Arch(ArchArgs args) : args(args)
         }
     }
     if (speed == nullptr) {
-        log_error("Unsuported speed grade '%s'.\n", speed_id.c_str(this));
+        log_error("Unsupported speed grade '%s'.\n", speed_id.c_str(this));
     }
 
     const VariantPOD *variant = nullptr;
@@ -732,7 +732,7 @@ Arch::Arch(ArchArgs args) : args(args)
         }
     }
     if (variant == nullptr) {
-        log_error("Unsuported device grade '%s'.\n", device_id.c_str(this));
+        log_error("Unsupported device grade '%s'.\n", device_id.c_str(this));
     }
 
     package = nullptr;
@@ -750,7 +750,7 @@ Arch::Arch(ArchArgs args) : args(args)
     }
 
     if (package == nullptr) {
-        log_error("Unsuported package '%s'.\n", package_name.c_str(this));
+        log_error("Unsupported package '%s'.\n", package_name.c_str(this));
     }
 
     //

From a120ae1fa7be5bac98e77755a6220df59e443b16 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 14 Dec 2021 18:47:35 +0000
Subject: [PATCH 014/712] python: Bind getBelLocation/getPipLocation

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/arch_pybindings_shared.h | 4 ++++
 common/pybindings.cc            | 5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/arch_pybindings_shared.h b/common/arch_pybindings_shared.h
index f44aa70e60..b3dc0506d0 100644
--- a/common/arch_pybindings_shared.h
+++ b/common/arch_pybindings_shared.h
@@ -48,6 +48,8 @@ fn_wrapper_2a_v<Context, decltype(&Context::copyBelPorts), &Context::copyBelPort
 
 fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
               conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
+fn_wrapper_1a<Context, decltype(&Context::getBelLocation), &Context::getBelLocation, pass_through<Loc>,
+              conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelLocation");
 fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
               conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
 fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
@@ -92,6 +94,8 @@ fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_cont
                                                                                                             "getPips");
 fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
               conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
+fn_wrapper_1a<Context, decltype(&Context::getPipLocation), &Context::getPipLocation, pass_through<Loc>,
+              conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipLocation");
 fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>, addr_and_unwrap<NetInfo>,
                 pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
 fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
diff --git a/common/pybindings.cc b/common/pybindings.cc
index f9ee9eb76d..eef460ce11 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -83,6 +83,8 @@ template <> struct string_converter<Property>
 
 } // namespace PythonConversion
 
+std::string loc_repr_py(Loc loc) { return stringf("Loc(%d, %d, %d)", loc.x, loc.y, loc.z); }
+
 PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
 {
     py::register_exception_translator([](std::exception_ptr p) {
@@ -175,7 +177,8 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
                            .def(py::init<int, int, int>())
                            .def_readwrite("x", &Loc::x)
                            .def_readwrite("y", &Loc::y)
-                           .def_readwrite("z", &Loc::z);
+                           .def_readwrite("z", &Loc::z)
+                           .def("__repr__", loc_repr_py);
 
     auto ci_cls = py::class_<ContextualWrapper<CellInfo &>>(m, "CellInfo");
     readwrite_wrapper<CellInfo &, decltype(&CellInfo::name), &CellInfo::name, conv_to_str<IdString>,

From a946ed0206cda29ce1bfe7f5a09f1b5e3d21794d Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 14 Dec 2021 19:27:20 +0000
Subject: [PATCH 015/712] ice40: Pack LUT at start of carry chain if there is 1
 candidate

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/pack.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index 0db7899212..921e73e08e 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -203,6 +203,8 @@ static void pack_carries(Context *ctx)
             CellInfo *carry_lc = nullptr;
             if (carry_ci_lc && carry_lcs.find(carry_ci_lc->name) != carry_lcs.end()) {
                 carry_lc = carry_ci_lc;
+            } else if (ci_const && carry_lcs.size() == 1) {
+                carry_lc = ctx->cells.at(*(carry_lcs.begin())).get();
             } else {
                 // No LC to pack into matching I0/I1, insert a new one
                 std::unique_ptr<CellInfo> created_lc =

From 120ed0c42d0d7a70003667d4e8dcc7b9ac86afef Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 15 Dec 2021 07:56:34 +1000
Subject: [PATCH 016/712] gowin: Recognize models correctly

For example, clearly distinguish between
    GW1N-4
    GW1NR-4
    GW1NS-4
    GW1NSR-4
    GW1NSR-4

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/main.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index c6697ecc86..cbd62ed92c 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -65,7 +65,7 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     // GW1N and GW1NR variants share the same database.
     // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
     // However, it appears that the S series with embedded ARM core are unique silicon.
-    if (match[1].str() == "S") {
+    if (match[1].str().length() && match[1].str()[0] == 'S') {
         snprintf(buf, 36, "GW1NS-%s", match[3].str().c_str());
     } else {
         snprintf(buf, 36, "GW1N-%s", match[3].str().c_str());

From d2ac6dffbcd1bcb6dbf3cadd03f33794b2af5c80 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 29 Oct 2021 18:00:05 -0400
Subject: [PATCH 017/712] machxo2: Correct which PIO wires get adjusted when
 writing text bitstream. Add verbose logging for adjustments.

---
 machxo2/bitstream.cc | 35 ++++++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index ed67975a22..913d7b58a7 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -19,6 +19,7 @@
  */
 
 #include <fstream>
+#include <iostream>
 
 #include "bitstream.h"
 #include "config.h"
@@ -59,13 +60,20 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
 
     // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose
     // relative coords push them outside the bounds of the chip.
+    // Indents are based on wires proximity/purpose.
     auto is_pio_wire = [](std::string name) {
         return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
-                name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
-                name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
-                name.find("JCE") != std::string::npos || name.find("JCLK") != std::string::npos ||
-                name.find("JLSR") != std::string::npos || name.find("JONEG") != std::string::npos ||
-                name.find("JOPOS") != std::string::npos || name.find("JTS") != std::string::npos ||
+                    name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
+                    name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
+                // JCE0-3, JCLK0-3, JLSR0-3 connect to PIO wires named JCEA-D, JCLKA-D, JLSRA-D.
+                name.find("JCEA") != std::string::npos || name.find("JCEB") != std::string::npos ||
+                    name.find("JCEC") != std::string::npos || name.find("JCED") != std::string::npos ||
+                    name.find("JCLKA") != std::string::npos || name.find("JCLKB") != std::string::npos ||
+                    name.find("JCLKC") != std::string::npos || name.find("JCLKD") != std::string::npos ||
+                    name.find("JLSRA") != std::string::npos || name.find("JLSRB") != std::string::npos ||
+                    name.find("JLSRC") != std::string::npos || name.find("JLSRD") != std::string::npos ||
+                name.find("JONEG") != std::string::npos || name.find("JOPOS") != std::string::npos ||
+                    name.find("JTS") != std::string::npos ||
                 name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
                 // Connections to global mux
                 name.find("JINCK") != std::string::npos);
@@ -92,10 +100,19 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
     if (loc == wire.location) {
         // TODO: JINCK is not currently handled by this.
         if (is_pio_wire(basename)) {
-            if (wire.location.x == 0)
-                return "W1_" + basename;
-            else if (wire.location.x == max_col)
-                return "E1_" + basename;
+            if (wire.location.x == 0) {
+                std::string pio_name = "W1_" + basename;
+                if (ctx->verbose)
+                    log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", \
+                        ctx->nameOfWire(wire), pio_name.c_str());
+                return pio_name;
+            } else if (wire.location.x == max_col) {
+                std::string pio_name = "E1_" + basename;
+                if (ctx->verbose)
+                    log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", \
+                        ctx->nameOfWire(wire), pio_name.c_str());
+                return pio_name;
+            }
         }
         return basename;
     }

From 365a871908f3b945fb19cfefb642fbde87dbf584 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 3 Nov 2021 13:53:57 -0400
Subject: [PATCH 018/712] machxo2: Add packing logic to forbid designs lacking
 FACADE_IO top-level ports.

---
 machxo2/pack.cc | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 66d2d4110a..231cc99d58 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -229,6 +229,44 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 
 static bool is_facade_iob(const Context *ctx, const CellInfo *cell) { return cell->type == id_FACADE_IO; }
 
+static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, NetInfo *&top) {
+    NPNR_ASSERT(is_nextpnr_iob(ctx, iob));
+
+    if(iob->type == ctx->id("$nextpnr_ibuf")) {
+        NetInfo *o = iob->ports.at(id_O).net;
+        top = o;
+
+        CellInfo *fio = net_only_drives(ctx, o, is_facade_iob, id_PAD, true);
+        return fio != nullptr;
+    } else if(iob->type == ctx->id("$nextpnr_obuf")) {
+        NetInfo *i = iob->ports.at(id_I).net;
+        top = i;
+
+        // If connected to a FACADE_IO PAD, the net attached to an I port of an
+        // $nextpnr_obuf will not have a driver, only users; an inout port
+        // like PAD cannot be a driver in nextpnr. So net_driven_by won't
+        // return anything. We exclude the IOB as one of the two users because
+        // we already know that the net drives the $nextpnr_obuf.
+        CellInfo *fio = net_only_drives(ctx, i, is_facade_iob, id_PAD, true, iob);
+        return fio != nullptr;
+    } else if(iob->type == ctx->id("$nextpnr_iobuf")) {
+        NetInfo *o = iob->ports.at(id_O).net;
+        top = o;
+
+        // When split_io is enabled in a frontend (it is for JSON), the I and O
+        // ports of a $nextpnr_iobuf are split; the I port connects to the
+        // driver of the original net before IOB insertion, and the O port
+        // connects everything else. Because FACADE_IO PADs cannot be a driver
+        // in nextpnr, the we can safely ignore the I port of an $nextpnr_iobuf
+        // for any JSON input we're interested in accepting.
+        CellInfo *fio_o = net_only_drives(ctx, o, is_facade_iob, id_PAD, true);
+        return fio_o != nullptr;
+    }
+
+    // Unreachable!
+    NPNR_ASSERT(false);
+}
+
 // Pack IO buffers- Right now, all this does is remove $nextpnr_[io]buf cells.
 // User is expected to manually instantiate FACADE_IO with BEL/IO_TYPE
 // attributes.
@@ -241,6 +279,14 @@ static void pack_io(Context *ctx)
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (is_nextpnr_iob(ctx, ci)) {
+            NetInfo *top;
+
+            if(!nextpnr_iob_connects_only_facade_iob(ctx, ci, top))
+                log_error("Top level net '%s' is not connected to a FACADE_IO PAD port.\n", top->name.c_str(ctx));
+
+            if (ctx->verbose)
+                log_info("Removing top-level IOBUF '%s' of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
+
             for (auto &p : ci->ports)
                 disconnect_port(ctx, ci, p.first);
             packed_cells.insert(ci->name);

From be3788fa3004cfee1058293d5da6ba758f913e7e Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 5 Nov 2021 12:49:24 -0400
Subject: [PATCH 019/712] machxo2: Remove -noiopad option when generating
 miters for post-pnr verification.

---
 machxo2/examples/mitertest.sh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index cfae28b788..feafc0ddab 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -61,6 +61,7 @@ do_smt() {
                         miter -equiv -make_assert gold gate ${2}${1}_miter
                         hierarchy -top ${2}${1}_miter; proc;
                         opt_clean
+                        flatten t:*FACADE_IO*
                         write_verilog ${2}${1}_miter.v
                         write_smt2 ${2}${1}_miter.smt2"
 
@@ -71,7 +72,7 @@ do_smt() {
 set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
-                    synth_machxo2 -noiopad -json ${1}.json"
+                    synth_machxo2 -json ${1}.json"
 ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json

From 4d757922572e6009777c6d533d410cdb2257c363 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 5 Nov 2021 13:26:05 -0400
Subject: [PATCH 020/712] machxo2: Remove no-iobs option. It was always enabled
 and should remain an implementation detail.

---
 machxo2/examples/demo-vhdl.sh | 2 +-
 machxo2/examples/demo.sh      | 2 +-
 machxo2/examples/mitertest.sh | 2 +-
 machxo2/examples/simple.sh    | 2 +-
 machxo2/examples/simtest.sh   | 2 +-
 machxo2/main.cc               | 3 ---
 6 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/machxo2/examples/demo-vhdl.sh b/machxo2/examples/demo-vhdl.sh
index 4bdab54a8a..ed1f7d8044 100644
--- a/machxo2/examples/demo-vhdl.sh
+++ b/machxo2/examples/demo-vhdl.sh
@@ -19,6 +19,6 @@ set -ex
 ${YOSYS:-yosys} -p "ghdl --std=08 prims.vhd ${1}.vhd -e;
                     attrmap -tocase LOC
                     synth_machxo2 -json ${1}-vhdl.json"
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json $1-vhdl.json --textcfg $1-vhdl.txt
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --json $1-vhdl.json --textcfg $1-vhdl.txt
 ecppack --compress $DB_ARG $1-vhdl.txt $1-vhdl.bit
 tinyproga -b $1-vhdl.bit
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
index 00cb0cd0fd..634fbb4dfd 100644
--- a/machxo2/examples/demo.sh
+++ b/machxo2/examples/demo.sh
@@ -17,6 +17,6 @@ fi
 set -ex
 
 ${YOSYS:-yosys} -p "synth_machxo2 -json $1.json" $1.v
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json $1.json --textcfg $1.txt
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --json $1.json --textcfg $1.txt
 ecppack --compress $DB_ARG $1.txt $1.bit
 tinyproga -b $1.bit
diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index feafc0ddab..b7ec2695d0 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -73,7 +73,7 @@ set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 1da6093393..69706b9c3f 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -26,7 +26,7 @@ set -ex
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json
                     show -format png -prefix ${1}"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index 2c7f6f3003..0adf175163 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -30,7 +30,7 @@ set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
diff --git a/machxo2/main.cc b/machxo2/main.cc
index 53b765fbbd..e29e117b45 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -69,7 +69,6 @@ po::options_description MachXO2CommandHandler::getArchOptions()
 
     // specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
 
-    specific.add_options()("no-iobs", "disable automatic IO buffer insertion (unimplemented- always enabled)");
     return specific;
 }
 
@@ -108,8 +107,6 @@ std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string,
     }
 
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
-    if (vm.count("no-iobs"))
-        ctx->settings[ctx->id("disable_iobs")] = Property::State::S1;
     return ctx;
 }
 

From 78ce9971ff9c0c5ed1b38e5a3423f325c9a1d6e5 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 5 Nov 2021 13:29:01 -0400
Subject: [PATCH 021/712] README.md: Add machxo2 arch to list of (experimental)
 supported devices.

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index c1b28f15ac..14128b87ec 100644
--- a/README.md
+++ b/README.md
@@ -10,6 +10,7 @@ Currently nextpnr supports:
  * Lattice Nexus devices supported by [Project Oxide](https://github.com/gatecat/prjoxide)
  * Gowin LittleBee devices supported by [Project Apicula](https://github.com/YosysHQ/apicula)
  * *(experimental)* Cyclone V devices supported by [Mistral](https://github.com/Ravenslofty/mistral)
+ * *(experimental)* Lattice MachXO2 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
  * *(experimental)* a "generic" back-end for user-defined architectures
 
 There is some work in progress towards [support for Xilinx devices](https://github.com/gatecat/nextpnr-xilinx/) but it is not upstream and not intended for end users at the present time. We hope to see more FPGA families supported in the future. We would love your help in developing this awesome new project!

From 064b6d808e9b91c93258a53ac1a18b3b84431545 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Thu, 16 Dec 2021 17:09:29 -0500
Subject: [PATCH 022/712] clangformat.

---
 machxo2/bitstream.cc | 10 ++++++----
 machxo2/pack.cc      | 11 ++++++-----
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 913d7b58a7..f624d91b61 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -62,6 +62,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
     // relative coords push them outside the bounds of the chip.
     // Indents are based on wires proximity/purpose.
     auto is_pio_wire = [](std::string name) {
+        // clang-format off
         return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
                     name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
                     name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
@@ -77,6 +78,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
                 name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
                 // Connections to global mux
                 name.find("JINCK") != std::string::npos);
+        // clang-format on
     };
 
     if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
@@ -103,14 +105,14 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
             if (wire.location.x == 0) {
                 std::string pio_name = "W1_" + basename;
                 if (ctx->verbose)
-                    log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", \
-                        ctx->nameOfWire(wire), pio_name.c_str());
+                    log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
+                             pio_name.c_str());
                 return pio_name;
             } else if (wire.location.x == max_col) {
                 std::string pio_name = "E1_" + basename;
                 if (ctx->verbose)
-                    log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", \
-                        ctx->nameOfWire(wire), pio_name.c_str());
+                    log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
+                             pio_name.c_str());
                 return pio_name;
             }
         }
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 231cc99d58..c53229ba01 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -229,16 +229,17 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 
 static bool is_facade_iob(const Context *ctx, const CellInfo *cell) { return cell->type == id_FACADE_IO; }
 
-static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, NetInfo *&top) {
+static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, NetInfo *&top)
+{
     NPNR_ASSERT(is_nextpnr_iob(ctx, iob));
 
-    if(iob->type == ctx->id("$nextpnr_ibuf")) {
+    if (iob->type == ctx->id("$nextpnr_ibuf")) {
         NetInfo *o = iob->ports.at(id_O).net;
         top = o;
 
         CellInfo *fio = net_only_drives(ctx, o, is_facade_iob, id_PAD, true);
         return fio != nullptr;
-    } else if(iob->type == ctx->id("$nextpnr_obuf")) {
+    } else if (iob->type == ctx->id("$nextpnr_obuf")) {
         NetInfo *i = iob->ports.at(id_I).net;
         top = i;
 
@@ -249,7 +250,7 @@ static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, Ne
         // we already know that the net drives the $nextpnr_obuf.
         CellInfo *fio = net_only_drives(ctx, i, is_facade_iob, id_PAD, true, iob);
         return fio != nullptr;
-    } else if(iob->type == ctx->id("$nextpnr_iobuf")) {
+    } else if (iob->type == ctx->id("$nextpnr_iobuf")) {
         NetInfo *o = iob->ports.at(id_O).net;
         top = o;
 
@@ -281,7 +282,7 @@ static void pack_io(Context *ctx)
         if (is_nextpnr_iob(ctx, ci)) {
             NetInfo *top;
 
-            if(!nextpnr_iob_connects_only_facade_iob(ctx, ci, top))
+            if (!nextpnr_iob_connects_only_facade_iob(ctx, ci, top))
                 log_error("Top level net '%s' is not connected to a FACADE_IO PAD port.\n", top->name.c_str(ctx));
 
             if (ctx->verbose)

From 4451a562efaab259c46d0ce2308fc4f1f1963708 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Dec 2021 14:51:00 +0000
Subject: [PATCH 023/712] frontend: Consider net aliases when uniquifying name

Signed-off-by: gatecat <gatecat@ds0.me>
---
 frontend/frontend_base.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index 6d2ee6f627..ed9354b63f 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -229,7 +229,7 @@ template <typename FrontendType> struct GenericFrontend
             }
             name = ctx->id(comb);
             incr++;
-        } while (is_net ? ctx->nets.count(name) : ctx->cells.count(name));
+        } while (is_net ? (ctx->nets.count(name) || ctx->net_aliases.count(name)) : ctx->cells.count(name));
         return name;
     }
 

From a30686014456cfc665b2bd3243dbef956891860d Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Dec 2021 15:06:19 +0000
Subject: [PATCH 024/712] nexus: router1 speedup based on #867

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.cc |  3 +++
 nexus/arch.h  | 72 +++++++++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index ee7f6304c4..74a0647863 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -119,6 +119,9 @@ Arch::Arch(ArchArgs args) : args(args)
             ts.bels_by_z[bel.z].tile = i;
             ts.bels_by_z[bel.z].index = j;
         }
+        auto &ts = tileStatus.at(i);
+        ts.boundwires.resize(loc.wires.size());
+        ts.boundpips.resize(loc.pips.size());
     }
 
     for (int i = 0; i < chip_info->width; i++) {
diff --git a/nexus/arch.h b/nexus/arch.h
index 3e718e7809..edebec1ba0 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -911,6 +911,7 @@ struct Arch : BaseArch<ArchRanges>
     {
         std::vector<CellInfo *> boundcells;
         std::vector<BelId> bels_by_z;
+        std::vector<NetInfo *> boundwires, boundpips;
         LogicTileStatus *lts = nullptr;
         ~TileStatus() { delete lts; }
     };
@@ -1014,7 +1015,7 @@ struct Arch : BaseArch<ArchRanges>
             return false;
         if (is_pseudo_pip_disabled(pip))
             return false;
-        return BaseArch::checkPipAvail(pip);
+        return getBoundPipNet(pip) == nullptr;
     }
 
     bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
@@ -1023,7 +1024,8 @@ struct Arch : BaseArch<ArchRanges>
             return false;
         if (is_pseudo_pip_disabled(pip))
             return false;
-        return BaseArch::checkPipAvailForNet(pip, net);
+        NetInfo *bound = getBoundPipNet(pip);
+        return (bound == nullptr) || (bound == net);
     }
 
     CellInfo *getBoundBelCell(BelId bel) const override
@@ -1136,6 +1138,38 @@ struct Arch : BaseArch<ArchRanges>
         return range;
     }
 
+    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(wire != WireId());
+        auto &w2n_entry = tileStatus.at(wire.tile).boundwires.at(wire.index);
+        NPNR_ASSERT(w2n_entry == nullptr);
+        net->wires[wire].pip = PipId();
+        net->wires[wire].strength = strength;
+        w2n_entry = net;
+        this->refreshUiWire(wire);
+    }
+    void unbindWire(WireId wire) override
+    {
+        NPNR_ASSERT(wire != WireId());
+        auto &w2n_entry = tileStatus.at(wire.tile).boundwires.at(wire.index);
+        NPNR_ASSERT(w2n_entry != nullptr);
+
+        auto &net_wires = w2n_entry->wires;
+        auto it = net_wires.find(wire);
+        NPNR_ASSERT(it != net_wires.end());
+
+        auto pip = it->second.pip;
+        if (pip != PipId()) {
+            tileStatus.at(pip.tile).boundpips.at(pip.index) = nullptr;
+        }
+
+        net_wires.erase(it);
+        w2n_entry = nullptr;
+        this->refreshUiWire(wire);
+    }
+    virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
+    NetInfo *getBoundWireNet(WireId wire) const override { return tileStatus.at(wire.tile).boundwires.at(wire.index); }
+
     // -------------------------------------------------
 
     PipId getPipByName(IdStringList name) const override;
@@ -1220,6 +1254,40 @@ struct Arch : BaseArch<ArchRanges>
         return range;
     }
 
+    void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(pip != PipId());
+
+        auto &p2n_entry = tileStatus.at(pip.tile).boundpips.at(pip.index);
+        NPNR_ASSERT(p2n_entry == nullptr);
+        p2n_entry = net;
+
+        WireId dst = this->getPipDstWire(pip);
+        auto &w2n_entry = tileStatus.at(dst.tile).boundwires.at(dst.index);
+        NPNR_ASSERT(w2n_entry == nullptr);
+        w2n_entry = net;
+        net->wires[dst].pip = pip;
+        net->wires[dst].strength = strength;
+    }
+
+    void unbindPip(PipId pip) override
+    {
+        NPNR_ASSERT(pip != PipId());
+
+        auto &p2n_entry = tileStatus.at(pip.tile).boundpips.at(pip.index);
+        NPNR_ASSERT(p2n_entry != nullptr);
+        WireId dst = this->getPipDstWire(pip);
+
+        auto &w2n_entry = tileStatus.at(dst.tile).boundwires.at(dst.index);
+        NPNR_ASSERT(w2n_entry != nullptr);
+        w2n_entry = nullptr;
+
+        p2n_entry->wires.erase(dst);
+        p2n_entry = nullptr;
+    }
+
+    NetInfo *getBoundPipNet(PipId pip) const override { return tileStatus.at(pip.tile).boundpips.at(pip.index); }
+
     // -------------------------------------------------
 
     delay_t estimateDelay(WireId src, WireId dst) const override;

From 53ce8f3736e7e4535c4fb4b323c01cbea95314a9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 18 Sep 2021 10:00:05 +0100
Subject: [PATCH 025/712] router1: Improve timing heuristic

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/router1.cc | 38 +++++++++++++++++++++++++-------------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/common/router1.cc b/common/router1.cc
index 0ff2bedd76..6977a79927 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -117,14 +117,21 @@ struct Router1
     int arcs_without_ripup = 0;
     bool ripup_flag;
 
-    Router1(Context *ctx, const Router1Cfg &cfg) : ctx(ctx), cfg(cfg) {}
+    TimingAnalyser tmg;
+
+    Router1(Context *ctx, const Router1Cfg &cfg) : ctx(ctx), cfg(cfg), tmg(ctx)
+    {
+        tmg.setup();
+        tmg.run();
+    }
 
     void arc_queue_insert(const arc_key &arc, WireId src_wire, WireId dst_wire)
     {
         if (queued_arcs.count(arc))
             return;
 
-        delay_t pri = ctx->estimateDelay(src_wire, dst_wire) - arc.net_info->users[arc.user_idx].budget;
+        delay_t pri = ctx->estimateDelay(src_wire, dst_wire) *
+                      (100 * tmg.get_criticality(CellPortKey(arc.net_info->users.at(arc.user_idx))));
 
         arc_entry entry;
         entry.arc = arc;
@@ -459,6 +466,8 @@ struct Router1
         auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx], arc.phys_idx);
         ripup_flag = false;
 
+        float crit = tmg.get_criticality(CellPortKey(net_info->users.at(user_idx)));
+
         if (ctx->debug) {
             log("Routing arc %d on net %s (%d arcs total):\n", user_idx, ctx->nameOf(net_info),
                 int(net_info->users.size()));
@@ -536,6 +545,7 @@ struct Router1
                 delay_t next_delay = qw.delay + ctx->getPipDelay(pip).maxDelay();
                 delay_t next_penalty = qw.penalty;
                 delay_t next_bonus = qw.bonus;
+                delay_t penalty_delta = 0;
 
                 WireId next_wire = ctx->getPipDstWire(pip);
                 next_delay += ctx->getWireDelay(next_wire).maxDelay();
@@ -544,7 +554,7 @@ struct Router1
                 NetInfo *conflictWireNet = nullptr, *conflictPipNet = nullptr;
 
                 if (net_info->wires.count(next_wire) && net_info->wires.at(next_wire).pip == pip) {
-                    next_bonus += cfg.reuseBonus;
+                    next_bonus += cfg.reuseBonus * (1.0 - crit);
                 } else {
                     if (!ctx->checkWireAvail(next_wire)) {
                         if (!ripup)
@@ -609,34 +619,36 @@ struct Router1
                     if (conflictWireWire != WireId()) {
                         auto scores_it = wireScores.find(conflictWireWire);
                         if (scores_it != wireScores.end())
-                            next_penalty += scores_it->second * cfg.wireRipupPenalty;
-                        next_penalty += cfg.wireRipupPenalty;
+                            penalty_delta += scores_it->second * cfg.wireRipupPenalty;
+                        penalty_delta += cfg.wireRipupPenalty;
                     }
 
                     if (conflictPipWire != WireId()) {
                         auto scores_it = wireScores.find(conflictPipWire);
                         if (scores_it != wireScores.end())
-                            next_penalty += scores_it->second * cfg.wireRipupPenalty;
-                        next_penalty += cfg.wireRipupPenalty;
+                            penalty_delta += scores_it->second * cfg.wireRipupPenalty;
+                        penalty_delta += cfg.wireRipupPenalty;
                     }
 
                     if (conflictWireNet != nullptr) {
                         auto scores_it = netScores.find(conflictWireNet);
                         if (scores_it != netScores.end())
-                            next_penalty += scores_it->second * cfg.netRipupPenalty;
-                        next_penalty += cfg.netRipupPenalty;
-                        next_penalty += conflictWireNet->wires.size() * cfg.wireRipupPenalty;
+                            penalty_delta += scores_it->second * cfg.netRipupPenalty;
+                        penalty_delta += cfg.netRipupPenalty;
+                        penalty_delta += conflictWireNet->wires.size() * cfg.wireRipupPenalty;
                     }
 
                     if (conflictPipNet != nullptr) {
                         auto scores_it = netScores.find(conflictPipNet);
                         if (scores_it != netScores.end())
-                            next_penalty += scores_it->second * cfg.netRipupPenalty;
-                        next_penalty += cfg.netRipupPenalty;
-                        next_penalty += conflictPipNet->wires.size() * cfg.wireRipupPenalty;
+                            penalty_delta += scores_it->second * cfg.netRipupPenalty;
+                        penalty_delta += cfg.netRipupPenalty;
+                        penalty_delta += conflictPipNet->wires.size() * cfg.wireRipupPenalty;
                     }
                 }
 
+                next_penalty += penalty_delta * std::max(0.05, (1.0 - crit));
+
                 delay_t next_score = next_delay + next_penalty;
                 NPNR_ASSERT(next_score >= 0);
 

From 9b2d6c5a67f0774bc41f0bc6cdb6a71bbcc388e8 Mon Sep 17 00:00:00 2001
From: uis <uis9936@gmail.com>
Date: Sat, 18 Dec 2021 22:44:08 +0300
Subject: [PATCH 026/712] Clean gowin modification regex

---
 gowin/main.cc | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index cbd62ed92c..66de26aa34 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -54,7 +54,7 @@ po::options_description GowinCommandHandler::getArchOptions()
 
 std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Property> &values)
 {
-    std::regex devicere = std::regex("GW1N([A-Z]*)-(LV|UV|UX)([0-9])(C?).*");
+    std::regex devicere = std::regex("GW1N(S?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
     std::smatch match;
     std::string device = vm["device"].as<std::string>();
     if (!std::regex_match(device, match, devicere)) {
@@ -65,11 +65,7 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     // GW1N and GW1NR variants share the same database.
     // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
     // However, it appears that the S series with embedded ARM core are unique silicon.
-    if (match[1].str().length() && match[1].str()[0] == 'S') {
-        snprintf(buf, 36, "GW1NS-%s", match[3].str().c_str());
-    } else {
-        snprintf(buf, 36, "GW1N-%s", match[3].str().c_str());
-    }
+    snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
     chipArgs.family = buf;
     chipArgs.partnumber = match[0];
     return std::unique_ptr<Context>(new Context(chipArgs));

From f670de7b52027ace6eb9f382ee6025f79d84202d Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 18 Dec 2021 20:58:44 +0000
Subject: [PATCH 027/712] router1: Experimental timing-driven ripup support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/command.cc |  8 ++--
 common/router1.cc | 97 ++++++++++++++++++++++++++++++++++++++++++++++-
 common/router2.cc |  4 +-
 3 files changed, 103 insertions(+), 6 deletions(-)

diff --git a/common/command.cc b/common/command.cc
index 5a13fb55ce..d4279a581f 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -176,7 +176,9 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("router2-heatmap", po::value<std::string>(),
                           "prefix for router2 resource congestion heatmaps");
 
-    general.add_options()("router2-tmg-ripup", "enable experimental timing-driven ripup in router2");
+    general.add_options()("tmg-ripup", "enable experimental timing-driven ripup in router");
+    general.add_options()("router2-tmg-ripup",
+                          "enable experimental timing-driven ripup in router (deprecated; use --tmg-ripup instead)");
 
     general.add_options()("report", po::value<std::string>(),
                           "write timing and utilization report in JSON format to file");
@@ -298,8 +300,8 @@ void CommandHandler::setupContext(Context *ctx)
         ctx->settings[ctx->id("placerHeap/timingWeight")] = std::to_string(vm["placer-heap-timingweight"].as<int>());
     if (vm.count("router2-heatmap"))
         ctx->settings[ctx->id("router2/heatmap")] = vm["router2-heatmap"].as<std::string>();
-    if (vm.count("router2-tmg-ripup"))
-        ctx->settings[ctx->id("router2/tmg_ripup")] = true;
+    if (vm.count("tmg-ripup") || vm.count("router2-tmg-ripup"))
+        ctx->settings[ctx->id("router/tmg_ripup")] = true;
 
     // Setting default values
     if (ctx->settings.find(ctx->id("target_freq")) == ctx->settings.end())
diff --git a/common/router1.cc b/common/router1.cc
index 6977a79927..f387aee1c5 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -119,8 +119,11 @@ struct Router1
 
     TimingAnalyser tmg;
 
+    bool timing_driven = true;
+
     Router1(Context *ctx, const Router1Cfg &cfg) : ctx(ctx), cfg(cfg), tmg(ctx)
     {
+        timing_driven = ctx->setting<bool>("timing_driven");
         tmg.setup();
         tmg.run();
     }
@@ -647,7 +650,7 @@ struct Router1
                     }
                 }
 
-                next_penalty += penalty_delta * std::max(0.05, (1.0 - crit));
+                next_penalty += penalty_delta * (timing_driven ? std::max(0.05, (1.0 - crit)) : 1);
 
                 delay_t next_score = next_delay + next_penalty;
                 NPNR_ASSERT(next_score >= 0);
@@ -790,6 +793,53 @@ struct Router1
 
         return true;
     }
+
+    delay_t find_slack_thresh()
+    {
+        // If more than 5% of arcs have negative slack; use the 5% threshold as a ripup criteria
+        int arc_count = 0;
+        int failed_count = 0;
+        delay_t default_thresh = ctx->getDelayEpsilon();
+
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            if (skip_net(ni))
+                continue;
+            for (size_t i = 0; i < ni->users.size(); i++) {
+                auto &usr = ni->users.at(i);
+                ++arc_count;
+                delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
+                if (slack == std::numeric_limits<delay_t>::min())
+                    continue;
+                if (slack < default_thresh)
+                    ++failed_count;
+            }
+        }
+
+        if (arc_count < 50 || (failed_count < (0.05 * arc_count))) {
+            return default_thresh;
+        }
+
+        std::vector<delay_t> slacks;
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            if (skip_net(ni))
+                continue;
+            for (size_t i = 0; i < ni->users.size(); i++) {
+                auto &usr = ni->users.at(i);
+                delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
+                if (slack == std::numeric_limits<delay_t>::min())
+                    continue;
+                slacks.push_back(slack);
+            }
+        }
+        std::sort(slacks.begin(), slacks.end());
+        delay_t thresh = slacks.at(int(slacks.size() * 0.05));
+        log_warning("%.f%% of arcs have failing slack; using %.2fns as ripup threshold. Consider a reduced Fmax "
+                    "constraint.\n",
+                    (100.0 * failed_count) / arc_count, ctx->getDelayNS(thresh));
+        return thresh;
+    }
 };
 
 } // namespace
@@ -831,6 +881,9 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
         int iter_cnt = 0;
         int last_arcs_with_ripup = 0;
         int last_arcs_without_ripup = 0;
+        int timing_fail_count = 0;
+        bool timing_ripup = ctx->setting<bool>("router/tmg_ripup", false);
+        delay_t ripup_slack = 0;
 
         log_info("           |   (re-)routed arcs  |   delta    | remaining|       time spent     |\n");
         log_info("   IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|\n");
@@ -866,6 +919,48 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
 #endif
                 return false;
             }
+            // Timing driven ripup
+            if (timing_ripup && router.arc_queue.empty() && timing_fail_count < 50) {
+                ++timing_fail_count;
+                router.tmg.run();
+                delay_t wns = 0, tns = 0;
+                if (timing_fail_count == 1)
+                    ripup_slack = router.find_slack_thresh();
+                for (auto &net : ctx->nets) {
+                    NetInfo *ni = net.second.get();
+                    if (router.skip_net(ni))
+                        continue;
+                    bool is_locked = false;
+                    for (auto &wire : ni->wires) {
+                        if (wire.second.strength > STRENGTH_STRONG)
+                            is_locked = true;
+                    }
+                    if (is_locked)
+                        continue;
+                    for (size_t i = 0; i < ni->users.size(); i++) {
+                        auto &usr = ni->users.at(i);
+                        delay_t slack = router.tmg.get_setup_slack(CellPortKey(usr));
+                        if (slack == std::numeric_limits<delay_t>::min())
+                            continue;
+                        if (slack < 0) {
+                            wns = std::min(wns, slack);
+                            tns += slack;
+                        }
+                        if (slack <= ripup_slack) {
+                            for (WireId w : ctx->getNetinfoSinkWires(ni, usr)) {
+                                if (ctx->checkWireAvail(w))
+                                    continue;
+                                router.ripup_wire(w);
+                            }
+                        }
+                    }
+                }
+                log_info("    %d arcs ripped up due to negative slack WNS=%.02fns TNS=%.02fns.\n",
+                         int(router.arc_queue.size()), ctx->getDelayNS(wns), ctx->getDelayNS(tns));
+                iter_cnt = 0;
+                router.wireScores.clear();
+                router.netScores.clear();
+            }
         }
         auto rend = std::chrono::high_resolution_clock::now();
         log_info("%10d | %8d %10d | %4d %5d | %9d| %10.02f %10.02f|\n", iter_cnt, router.arcs_with_ripup,
diff --git a/common/router2.cc b/common/router2.cc
index d713cce288..c76e1f6153 100644
--- a/common/router2.cc
+++ b/common/router2.cc
@@ -1373,8 +1373,8 @@ struct Router2
             route_queue.push_back(i);
 
         timing_driven = ctx->setting<bool>("timing_driven");
-        if (ctx->settings.count(ctx->id("router2/tmg_ripup")))
-            timing_driven_ripup = timing_driven && ctx->setting<bool>("router2/tmg_ripup");
+        if (ctx->settings.count(ctx->id("router/tmg_ripup")))
+            timing_driven_ripup = timing_driven && ctx->setting<bool>("router/tmg_ripup");
         else
             timing_driven_ripup = false;
         log_info("Running main router loop...\n");

From ddb084e9a8a0cba10536951236cde824526e8071 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 19 Dec 2021 16:41:34 +0000
Subject: [PATCH 028/712] archapi: Use arbitrary rather than actual placement
 in predictDelay

This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/arch_api.h           |  2 +-
 common/context.cc           | 23 +++++++++++++++++++++--
 common/context.h            |  2 ++
 common/nextpnr_namespaces.h |  2 ++
 common/place_common.cc      |  2 +-
 common/placer1.cc           |  4 ++--
 common/timing.cc            |  2 +-
 common/timing_opt.cc        |  8 ++++----
 docs/archapi.md             |  2 +-
 docs/coding.md              |  2 +-
 ecp5/arch.cc                | 21 ++++++++-------------
 ecp5/arch.h                 |  2 +-
 fpga_interchange/arch.cc    |  8 +++++---
 fpga_interchange/arch.h     |  2 +-
 generic/arch.cc             |  9 +++++----
 generic/arch.h              |  2 +-
 gowin/arch.cc               |  9 +++++----
 gowin/arch.h                |  2 +-
 ice40/arch.h                |  2 +-
 ice40/delay.cc              | 10 +++++-----
 machxo2/arch.cc             | 13 +++++++------
 machxo2/arch.h              |  2 +-
 mistral/arch.h              |  2 +-
 mistral/delay.cc            | 12 +++++-------
 nexus/arch.cc               | 12 +++++-------
 nexus/arch.h                |  2 +-
 26 files changed, 89 insertions(+), 70 deletions(-)

diff --git a/common/arch_api.h b/common/arch_api.h
index e49d26c1a8..14a30652ad 100644
--- a/common/arch_api.h
+++ b/common/arch_api.h
@@ -110,7 +110,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual typename R::GroupPipsRangeT getGroupPips(GroupId group) const = 0;
     virtual typename R::GroupGroupsRangeT getGroupGroups(GroupId group) const = 0;
     // Delay Methods
-    virtual delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const = 0;
+    virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const = 0;
     virtual delay_t getDelayEpsilon() const = 0;
     virtual delay_t getRipupDelayPenalty() const = 0;
     virtual float getDelayNS(delay_t v) const = 0;
diff --git a/common/context.cc b/common/context.cc
index 6bba5cbe69..faddf82595 100644
--- a/common/context.cc
+++ b/common/context.cc
@@ -90,6 +90,25 @@ WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &sink,
     return WireId();
 }
 
+delay_t Context::predictArcDelay(const NetInfo *net_info, const PortRef &sink) const
+{
+    if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
+        return 0;
+    IdString driver_pin, sink_pin;
+    // Pick the first pin for a prediction; assume all will be similar enouhg
+    for (auto pin : getBelPinsForCellPin(net_info->driver.cell, net_info->driver.port)) {
+        driver_pin = pin;
+        break;
+    }
+    for (auto pin : getBelPinsForCellPin(sink.cell, sink.port)) {
+        sink_pin = pin;
+        break;
+    }
+    if (driver_pin == IdString() || sink_pin == IdString())
+        return 0;
+    return predictDelay(net_info->driver.cell->bel, driver_pin, sink.cell->bel, sink_pin);
+}
+
 delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
 {
 #ifdef ARCH_ECP5
@@ -98,7 +117,7 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
 #endif
 
     if (net_info->wires.empty())
-        return predictDelay(net_info, user_info);
+        return predictArcDelay(net_info, user_info);
 
     WireId src_wire = getNetinfoSourceWire(net_info);
     if (src_wire == WireId())
@@ -128,7 +147,7 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
         if (cursor == src_wire)
             max_delay = std::max(max_delay, delay + getWireDelay(src_wire).maxDelay()); // routed
         else
-            max_delay = std::max(max_delay, predictDelay(net_info, user_info)); // unrouted
+            max_delay = std::max(max_delay, predictArcDelay(net_info, user_info)); // unrouted
     }
     return max_delay;
 }
diff --git a/common/context.h b/common/context.h
index 6adbbdb54f..cb8fd25707 100644
--- a/common/context.h
+++ b/common/context.h
@@ -51,6 +51,8 @@ struct Context : Arch, DeterministicRNG
 
     // --------------------------------------------------------------
 
+    delay_t predictArcDelay(const NetInfo *net_info, const PortRef &sink) const;
+
     WireId getNetinfoSourceWire(const NetInfo *net_info) const;
     SSOArray<WireId, 2> getNetinfoSinkWires(const NetInfo *net_info, const PortRef &sink) const;
     size_t getNetinfoSinkWireCount(const NetInfo *net_info, const PortRef &sink) const;
diff --git a/common/nextpnr_namespaces.h b/common/nextpnr_namespaces.h
index 6fb0aa776d..b758d7c555 100644
--- a/common/nextpnr_namespaces.h
+++ b/common/nextpnr_namespaces.h
@@ -33,6 +33,8 @@
 #define USING_NEXTPNR_NAMESPACE
 #endif
 
+#define NPNR_UNUSED(x) ((void)x)
+
 #if defined(__GNUC__) || defined(__clang__)
 #define NPNR_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
 #define NPNR_NORETURN __attribute__((noreturn))
diff --git a/common/place_common.cc b/common/place_common.cc
index bcfa3633a4..e03fca553f 100644
--- a/common/place_common.cc
+++ b/common/place_common.cc
@@ -50,7 +50,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
         if (load_cell->bel == BelId())
             continue;
         if (timing_driven) {
-            delay_t net_delay = ctx->predictDelay(net, load);
+            delay_t net_delay = ctx->predictArcDelay(net, load);
             auto slack = load.budget - net_delay;
             if (slack < 0)
                 negative_slack += slack;
diff --git a/common/placer1.cc b/common/placer1.cc
index 4db1c9519d..6de035b444 100644
--- a/common/placer1.cc
+++ b/common/placer1.cc
@@ -866,11 +866,11 @@ class SAPlacer
         if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
             return 0;
         if (cfg.budgetBased) {
-            double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user)));
+            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
             return std::min(10.0, std::exp(delay - ctx->getDelayNS(net->users.at(user).budget) / 10));
         } else {
             float crit = tmg.get_criticality(CellPortKey(net->users.at(user)));
-            double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user)));
+            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
             return delay * std::pow(crit, crit_exp);
         }
     }
diff --git a/common/timing.cc b/common/timing.cc
index e305d82d1c..f30d4fc531 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -1378,7 +1378,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                         auto driver_wire = ctx->getNetinfoSourceWire(net);
                         auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
                         log_info("                 prediction: %f ns estimate: %f ns\n",
-                                 ctx->getDelayNS(ctx->predictDelay(net, sink_ref)),
+                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
                                  ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
                         auto cursor = sink_wire;
                         delay_t delay;
diff --git a/common/timing_opt.cc b/common/timing_opt.cc
index 6dd93d6783..a73a70cf0f 100644
--- a/common/timing_opt.cc
+++ b/common/timing_opt.cc
@@ -99,7 +99,7 @@ class TimingOptimiser
                     continue;
                 for (auto user : net->users) {
                     if (user.cell == cell && user.port == port.first) {
-                        if (ctx->predictDelay(net, user) >
+                        if (ctx->predictArcDelay(net, user) >
                             1.1 * max_net_delay.at(std::make_pair(cell->name, port.first)))
                             return false;
                     }
@@ -111,7 +111,7 @@ class TimingOptimiser
                     BelId dstBel = user.cell->bel;
                     if (dstBel == BelId())
                         continue;
-                    if (ctx->predictDelay(net, user) >
+                    if (ctx->predictArcDelay(net, user) >
                         1.1 * max_net_delay.at(std::make_pair(user.cell->name, user.port))) {
 
                         return false;
@@ -413,7 +413,7 @@ class TimingOptimiser
             for (size_t j = 0; j < pn->users.size(); j++) {
                 auto &usr = pn->users.at(j);
                 if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
-                    original_delay += ctx->predictDelay(pn, usr);
+                    original_delay += ctx->predictArcDelay(pn, usr);
                     break;
                 }
             }
@@ -497,7 +497,7 @@ class TimingOptimiser
                     for (size_t j = 0; j < pn->users.size(); j++) {
                         auto &usr = pn->users.at(j);
                         if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
-                            total_delay += ctx->predictDelay(pn, usr);
+                            total_delay += ctx->predictArcDelay(pn, usr);
                             break;
                         }
                     }
diff --git a/docs/archapi.md b/docs/archapi.md
index f2571f084b..5034d7d12f 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -517,7 +517,7 @@ result, and for that estimate it is considered more acceptable to return a
 slightly too high result and it is considered less acceptable to return a
 too low result (thus "low upper bound").
 
-### delay\_t predictDelay(const NetInfo \*net\_info, const PortRef &sink) const
+### delay\_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 
 Return a reasonably good estimate for the total `maxDelay()` delay for the
 given arc. This should return a low upper bound for the fastest route for that arc.
diff --git a/docs/coding.md b/docs/coding.md
index dc09bb3f18..db2ec079b6 100644
--- a/docs/coding.md
+++ b/docs/coding.md
@@ -80,7 +80,7 @@ As nextpnr allows arbitrary constraints on bels for more advanced packer-free fl
 There are several routes for timing information in the placer:
     - sink `PortRef`s have a `budget` value annotated by calling `assign_budget` which is an estimate of the maximum delay that an arc may have
     - sink ports can have a criticality (value between 0 and 1 where 1 is the critical path) associated with them by using `get_criticalities` and a `NetCriticalityMap`
-    - `predictDelay` returns an estimated delay for a sink port based on placement information
+    - `predictDelay` and its derivative `predictArcDelay` returns an estimated delay for a sink port based on placement information
 
 
 ### Bel Buckets
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 95a2768285..2e453f2a90 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -543,26 +543,21 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
     return bb;
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    const auto &driver = net_info->driver;
-    if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB)
+    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB)
         return 0;
-    auto driver_loc = getBelLocation(driver.cell->bel);
-    auto sink_loc = getBelLocation(sink.cell->bel);
+    auto driver_loc = getBelLocation(src_bel);
+    auto sink_loc = getBelLocation(dst_bel);
     // Encourage use of direct interconnect
     if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
-        if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) &&
-            (driver_loc.z == 2 || driver_loc.z == 3))
+        if ((dst_pin == id_A0 || dst_pin == id_A1) && (src_pin == id_F1) && (driver_loc.z == 2 || driver_loc.z == 3))
             return 0;
-        if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) &&
-            (driver_loc.z == 0 || driver_loc.z == 1))
+        if ((dst_pin == id_B0 || dst_pin == id_B1) && (src_pin == id_F1) && (driver_loc.z == 0 || driver_loc.z == 1))
             return 0;
-        if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) &&
-            (driver_loc.z == 2 || driver_loc.z == 3))
+        if ((dst_pin == id_C0 || dst_pin == id_C1) && (src_pin == id_F0) && (driver_loc.z == 2 || driver_loc.z == 3))
             return 0;
-        if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) &&
-            (driver_loc.z == 0 || driver_loc.z == 1))
+        if ((dst_pin == id_D0 || dst_pin == id_D1) && (src_pin == id_F0) && (driver_loc.z == 0 || driver_loc.z == 1))
             return 0;
     }
 
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 51a919bb41..c1bed2b361 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -913,7 +913,7 @@ struct Arch : BaseArch<ArchRanges>
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
     ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override;
     float getDelayNS(delay_t v) const override { return v * 0.001; }
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index a39f49e67e..917af85e92 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1000,14 +1000,16 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
 #endif
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
     // FIXME: Implement when adding timing-driven place and route.
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
     int src_x, src_y;
-    get_tile_x_y(net_info->driver.cell->bel.tile, &src_x, &src_y);
+    get_tile_x_y(src_bel.tile, &src_x, &src_y);
 
     int dst_x, dst_y;
-    get_tile_x_y(sink.cell->bel.tile, &dst_x, &dst_y);
+    get_tile_x_y(dst_bel.tile, &dst_x, &dst_y);
 
     delay_t base = 30 * std::min(std::abs(dst_x - src_x), 18) + 10 * std::max(std::abs(dst_x - src_x) - 18, 0) +
                    60 * std::min(std::abs(dst_y - src_y), 6) + 20 * std::max(std::abs(dst_y - src_y) - 6, 0) + 300;
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 482bf9117d..8bb2e2d149 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -700,7 +700,7 @@ struct Arch : ArchAPI<ArchRanges>
 
     // -------------------------------------------------
     delay_t estimateDelay(WireId src, WireId dst) const final;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const final;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
     ArcBounds getRouteBoundingBox(WireId src, WireId dst) const final;
     delay_t getDelayEpsilon() const final { return 20; }
     delay_t getRipupDelayPenalty() const final { return 120; }
diff --git a/generic/arch.cc b/generic/arch.cc
index ebc1ef2694..0695ec9880 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -509,11 +509,12 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     return (dx + dy) * args.delayScale + args.delayOffset;
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    const auto &driver = net_info->driver;
-    auto driver_loc = getBelLocation(driver.cell->bel);
-    auto sink_loc = getBelLocation(sink.cell->bel);
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
+    auto driver_loc = getBelLocation(src_bel);
+    auto sink_loc = getBelLocation(dst_bel);
 
     int dx = abs(sink_loc.x - driver_loc.x);
     int dy = abs(sink_loc.y - driver_loc.y);
diff --git a/generic/arch.h b/generic/arch.h
index 2344d8b2d1..7f574f31c5 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -287,7 +287,7 @@ struct Arch : ArchAPI<ArchRanges>
     const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 0.001; }
     delay_t getRipupDelayPenalty() const override { return 0.015; }
     float getDelayNS(delay_t v) const override { return v; }
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 99e0ce6115..801540cc42 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1171,11 +1171,12 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     return (dx + dy) * args.delayScale + args.delayOffset;
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    const auto &driver = net_info->driver;
-    auto driver_loc = getBelLocation(driver.cell->bel);
-    auto sink_loc = getBelLocation(sink.cell->bel);
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
+    auto driver_loc = getBelLocation(src_bel);
+    auto sink_loc = getBelLocation(dst_bel);
 
     int dx = abs(sink_loc.x - driver_loc.x);
     int dy = abs(sink_loc.y - driver_loc.y);
diff --git a/gowin/arch.h b/gowin/arch.h
index aa751a4fe9..931a0aa1e5 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -419,7 +419,7 @@ struct Arch : BaseArch<ArchRanges>
     const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 0.01; }
     delay_t getRipupDelayPenalty() const override { return 0.4; }
     float getDelayNS(delay_t v) const override { return v; }
diff --git a/ice40/arch.h b/ice40/arch.h
index 5162285c36..3563baad2a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -784,7 +784,7 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override { return 200; }
     float getDelayNS(delay_t v) const override { return v * 0.001; }
diff --git a/ice40/delay.cc b/ice40/delay.cc
index 740057f1a9..a00cc2596c 100644
--- a/ice40/delay.cc
+++ b/ice40/delay.cc
@@ -188,13 +188,13 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     return v;
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    const auto &driver = net_info->driver;
-    auto driver_loc = getBelLocation(driver.cell->bel);
-    auto sink_loc = getBelLocation(sink.cell->bel);
+    NPNR_UNUSED(dst_pin);
+    auto driver_loc = getBelLocation(src_bel);
+    auto sink_loc = getBelLocation(dst_bel);
 
-    if (driver.port == id_COUT) {
+    if (src_pin == id_COUT) {
         if (driver_loc.y == sink_loc.y)
             return 0;
         return 250;
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index a201adf1af..6c0e48ced5 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -387,16 +387,17 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    BelId src = net_info->driver.cell->bel;
-    BelId dst = sink.cell->bel;
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
 
-    NPNR_ASSERT(src != BelId());
-    NPNR_ASSERT(dst != BelId());
+    NPNR_ASSERT(src_bel != BelId());
+    NPNR_ASSERT(dst_bel != BelId());
 
     // TODO: Same deal applies here as with estimateDelay.
-    return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
+    return (abs(dst_bel.location.x - src_bel.location.x) + abs(dst_bel.location.y - src_bel.location.y)) *
+           (0.01 + 0.01);
 }
 
 ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
diff --git a/machxo2/arch.h b/machxo2/arch.h
index f5ccb4f618..29d8c3ffcc 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -626,7 +626,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // Delay
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 0.001; }
     delay_t getRipupDelayPenalty() const override { return 0.015; }
     float getDelayNS(delay_t v) const override { return v; }
diff --git a/mistral/arch.h b/mistral/arch.h
index 34e5584638..471b5251ee 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -418,7 +418,7 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 10; };
     delay_t getRipupDelayPenalty() const override { return 100; };
     float getDelayNS(delay_t v) const override { return float(v) / 1000.0f; };
diff --git a/mistral/delay.cc b/mistral/delay.cc
index bfaeb06589..98ef1be62a 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -239,14 +239,12 @@ DelayQuad Arch::getPipDelay(PipId pip) const
     return DelayQuad{308};
 }
 
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId())
-        return 100;
-    if (sink.cell->bel == BelId())
-        return 100;
-    Loc src_loc = getBelLocation(net_info->driver.cell->bel);
-    Loc dst_loc = getBelLocation(sink.cell->bel);
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
+    Loc src_loc = getBelLocation(src_bel);
+    Loc dst_loc = getBelLocation(dst_bel);
     return std::abs(dst_loc.y - src_loc.y) * 100 + std::abs(dst_loc.x - src_loc.x) * 100 + 100;
 }
 
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 74a0647863..a7751425e3 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -603,16 +603,14 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     int dist_y = std::abs(src_y - dst_y);
     return 75 * dist_x + 75 * dist_y + 250;
 }
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
+    NPNR_UNUSED(src_pin);
+    if (dst_pin == id_FCI)
         return 0;
-    if (sink.port == id_FCI)
-        return 0;
-    int src_x = net_info->driver.cell->bel.tile % chip_info->width,
-        src_y = net_info->driver.cell->bel.tile / chip_info->width;
+    int src_x = src_bel.tile % chip_info->width, src_y = src_bel.tile / chip_info->width;
 
-    int dst_x = sink.cell->bel.tile % chip_info->width, dst_y = sink.cell->bel.tile / chip_info->width;
+    int dst_x = dst_bel.tile % chip_info->width, dst_y = dst_bel.tile / chip_info->width;
     int dist_x = std::abs(src_x - dst_x);
     int dist_y = std::abs(src_y - dst_y);
     return 100 * dist_x + 100 * dist_y + 250;
diff --git a/nexus/arch.h b/nexus/arch.h
index edebec1ba0..0bd1b62cd7 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1291,7 +1291,7 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override;
     delay_t getWireRipupDelayPenalty(WireId wire) const;

From 5a76b3cb4d506c4920fc3d6b9aff935cbaa2987e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 20 Dec 2021 15:48:38 +1000
Subject: [PATCH 029/712] gowin: Add simplified IO cells processing

Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input.  This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.

For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).

The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 33 +++++++++++++++++++++++++++++++++
 gowin/cells.cc     | 12 ++++++++++--
 gowin/constids.inc | 13 +++++++++++++
 gowin/pack.cc      | 23 +++++++++++++++++++++--
 4 files changed, 77 insertions(+), 4 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 801540cc42..2f61685a33 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -870,6 +870,39 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OEN, id(buf));
                 break;
+                // Simplified IO
+            case ID_IOBJS:
+                z++; /* fall-through*/
+            case ID_IOBIS:
+                z++; /* fall-through*/
+            case ID_IOBHS:
+                z++; /* fall-through*/
+            case ID_IOBGS:
+                z++; /* fall-through*/
+            case ID_IOBFS:
+                z++; /* fall-through*/
+            case ID_IOBES:
+                z++; /* fall-through*/
+            case ID_IOBDS:
+                z++; /* fall-through*/
+            case ID_IOBCS:
+                z++; /* fall-through*/
+            case ID_IOBBS:
+                z++; /* fall-through*/
+            case ID_IOBAS:
+                snprintf(buf, 32, "R%dC%d_IOB%c", row + 1, col + 1, 'A' + z);
+                belname = id(buf);
+                addBel(belname, id_IOBS, Loc(col, row, z), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_O)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_O, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_I)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_I, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OE)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_OEN, id(buf));
+                break;
 
             default:
                 break;
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 57f3ab9cc2..dce3f45654 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -64,14 +64,14 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         add_port(ctx, new_cell.get(), id_I1, PORT_IN);
         add_port(ctx, new_cell.get(), id_SEL, PORT_IN);
         add_port(ctx, new_cell.get(), id_OF, PORT_OUT);
-    } else if (type == id_IOB) {
+    } else if (type == id_IOB || type == id_IOBS) {
         new_cell->params[id_INPUT_USED] = 0;
         new_cell->params[id_OUTPUT_USED] = 0;
         new_cell->params[id_ENABLE_USED] = 0;
 
         add_port(ctx, new_cell.get(), id_PAD, PORT_INOUT);
         add_port(ctx, new_cell.get(), id_I, PORT_IN);
-        add_port(ctx, new_cell.get(), id_EN, PORT_IN);
+        add_port(ctx, new_cell.get(), id_OEN, PORT_IN);
         add_port(ctx, new_cell.get(), id_O, PORT_OUT);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
@@ -140,9 +140,17 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells)
 {
     if (nxio->type == id_IBUF) {
+        if (iob->type == id_IOBS) {
+            // VCC -> OEN
+            connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), iob, id_OEN);
+        }
         iob->params[id_INPUT_USED] = 1;
         replace_port(nxio, id_O, iob, id_O);
     } else if (nxio->type == id_OBUF) {
+        if (iob->type == id_IOBS) {
+            // VSS -> OEN
+            connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), iob, id_OEN);
+        }
         iob->params[id_OUTPUT_USED] = 1;
         replace_port(nxio, id_I, iob, id_I);
     } else if (nxio->type == id_TBUF) {
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 7de754fcc5..6a730d5d5e 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -358,6 +358,19 @@ X(IOBH)
 X(IOBI)
 X(IOBJ)
 
+// simplified iobs
+X(IOBS)
+X(IOBAS)
+X(IOBBS)
+X(IOBCS)
+X(IOBDS)
+X(IOBES)
+X(IOBFS)
+X(IOBGS)
+X(IOBHS)
+X(IOBIS)
+X(IOBJS)
+
 // Wide LUTs
 X(MUX2_LUT5)
 X(MUX2_LUT6)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index cb63f1c95a..553eeb4e53 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -629,7 +629,7 @@ static void pack_constants(Context *ctx)
 
     std::vector<IdString> dead_nets;
 
-    bool gnd_used = false;
+    bool gnd_used = true; // XXX May be needed for simplified IO
 
     for (auto &net : ctx->nets) {
         NetInfo *ni = net.second.get();
@@ -718,8 +718,27 @@ static void pack_io(Context *ctx)
                 }
                 packed_cells.insert(iob->name);
             }
+            // what type to create
+            IdString new_cell_type = id_IOB;
+            std::string constr_bel_name = std::string("");
+            // check whether the given IO is limited to simplified IO cells
+            auto constr_bel = ci->attrs.find(id_BEL);
+            if (constr_bel != ci->attrs.end()) {
+                constr_bel_name = constr_bel->second.as_string();
+            }
+            constr_bel = iob->attrs.find(id_BEL);
+            if (constr_bel != iob->attrs.end()) {
+                constr_bel_name = constr_bel->second.as_string();
+            }
+            if (!constr_bel_name.empty()) {
+                BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
+                if (constr_bel != BelId()) {
+                    new_cell_type = ctx->bels[constr_bel].type;
+                }
+            }
+
             // Create a IOB buffer
-            std::unique_ptr<CellInfo> ice_cell = create_generic_cell(ctx, id_IOB, ci->name.str(ctx) + "$iob");
+            std::unique_ptr<CellInfo> ice_cell = create_generic_cell(ctx, new_cell_type, ci->name.str(ctx) + "$iob");
             gwio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
             new_cells.push_back(std::move(ice_cell));
             auto gwiob = new_cells.back().get();

From 500fa6f4423ac016559f6140c8141da376d2833b Mon Sep 17 00:00:00 2001
From: Karol Gugala <kgugala@antmicro.com>
Date: Mon, 20 Dec 2021 14:33:29 +0100
Subject: [PATCH 030/712] nexus: handle SLEWRATE in pdc

---
 nexus/constids.inc | 1 +
 nexus/fasm.cc      | 4 ++--
 nexus/pdc.cc       | 7 +++++++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/nexus/constids.inc b/nexus/constids.inc
index 48b0ca2b2f..ca6bed5a23 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -109,6 +109,7 @@ X(CIB_T)
 X(CIB_LR)
 
 X(IO_TYPE)
+X(SLEWRATE)
 
 
 X(OSCA)
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index bb0a794173..4aaecdf47d 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -433,7 +433,7 @@ struct NexusFasmWriter
         write_bit(stringf("BASE_TYPE.%s_%s", iodir, str_or_default(cell->attrs, id_IO_TYPE, "LVCMOS33").c_str()));
         write_ioattr(cell, "PULLMODE", "NONE");
         write_ioattr(cell, "GLITCHFILTER", "OFF");
-        write_ioattr(cell, "SLEWRATE", "MED");
+        write_ioattr(cell, "SLEWRATE", str_or_default(cell->attrs, id_SLEWRATE, "MED").c_str());
         write_cell_muxes(cell);
         pop();
     }
@@ -458,7 +458,7 @@ struct NexusFasmWriter
         const char *iodir = is_input ? "INPUT" : (is_output ? "OUTPUT" : "BIDIR");
         write_bit(stringf("BASE_TYPE.%s_%s", iodir, str_or_default(cell->attrs, id_IO_TYPE, "LVCMOS18H").c_str()));
         write_ioattr(cell, "PULLMODE", "NONE");
-        write_ioattr(cell, "SLEWRATE", "MED");
+        write_ioattr(cell, "SLEWRATE", str_or_default(cell->attrs, id_SLEWRATE, "MED").c_str());
         pop();
         write_cell_muxes(cell);
         pop();
diff --git a/nexus/pdc.cc b/nexus/pdc.cc
index 67bab3c9ec..af62215829 100644
--- a/nexus/pdc.cc
+++ b/nexus/pdc.cc
@@ -21,6 +21,7 @@
 #include "log.h"
 #include "nextpnr.h"
 
+#include <algorithm>
 #include <iterator>
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -423,6 +424,12 @@ struct PDCParser
                         if (eqp == std::string::npos)
                             log_error("expected key-value pair separated by '=' (line %d)", lineno);
                         std::string k = kv.substr(0, eqp), v = kv.substr(eqp + 1);
+                        if (k == "SLEWRATE") {
+                            std::vector<std::string> slewrate_allowed = {"SLOW", "MED", "FAST", "NA"};
+                            if (std::find(std::begin(slewrate_allowed), std::end(slewrate_allowed), v) ==
+                                std::end(slewrate_allowed))
+                                log_error("unexpected SLEWRATE configuration %s (line %d)\n", v.c_str(), lineno);
+                        }
                         args[ctx->id(k)] = v;
                     }
                 } else {

From 2c43ac992f841eb57ac3003acc2f3a5736ce4591 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 22 Dec 2021 13:17:55 +0000
Subject: [PATCH 031/712] mistral: Update to latest enum name

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/mistral_ci.yml | 2 +-
 mistral/bitstream.cc             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 7cf71621aa..64300d78f4 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: 0edeca112dda9bd463125feb869ddb7511d1acd9
+        MISTRAL_REVISION: e039b595529ab573d9cb01c64ef927f9d81d63ce
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index e8c4dba7ae..eed508b38b 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -123,7 +123,7 @@ struct MistralBitgen
                 break;
             };
             case CycloneV::FPLL: {
-                if (pt == CycloneV::EXTSWITCH || (pt == CycloneV::CLKEN && pi < 2))
+                if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
                     cv->inv_set(pn2r.second, true);
                 break;
             };

From b53a921e426efdfbc6e0d13c19bcb94439431a70 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 17 Dec 2021 12:34:21 +0100
Subject: [PATCH 032/712] Add support for GW1NS-4 series devices

---
 gowin/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/CMakeLists.txt b/gowin/CMakeLists.txt
index a356a84b5f..5ec321288c 100644
--- a/gowin/CMakeLists.txt
+++ b/gowin/CMakeLists.txt
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-gowin NONE)
 
-set(ALL_GOWIN_DEVICES GW1N-1 GW1N-4 GW1N-9 GW1NS-2)
+set(ALL_GOWIN_DEVICES GW1N-1 GW1N-4 GW1N-9 GW1NS-2 GW1NS-4)
 set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
 message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")

From fa1ef15e47f7ee0b36a77f94ea26f92e2a8a689d Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 17 Dec 2021 12:35:37 +0100
Subject: [PATCH 033/712] build on release of apycula with gw1ns-4 support

---
 .cirrus/Dockerfile.ubuntu20.04 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index 4f229d2d38..bf81a4a663 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -65,4 +65,4 @@ RUN set -e -x ;\
     PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
 
 RUN set -e -x ;\
-    pip3 install apycula==0.0.1a12
+    pip3 install apycula==0.2a1

From e6b787954216ec220698bf7a6264f19bb6102d73 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 26 Dec 2021 12:05:35 +1000
Subject: [PATCH 034/712] gowin: Initializing the grid dimensions

gridDimX and gridDimY are not initialized explicitly, which leads to
effects when the design is reloaded, say, from the GUI.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/arch.h b/gowin/arch.h
index 931a0aa1e5..9f969f54f0 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -298,7 +298,7 @@ struct Arch : BaseArch<ArchRanges>
 
     dict<DecalId, std::vector<GraphicElement>> decal_graphics;
 
-    int gridDimX, gridDimY;
+    int gridDimX = 0, gridDimY = 0;
     std::vector<std::vector<int>> tileBelDimZ;
     std::vector<std::vector<int>> tilePipDimZ;
 

From 5b6961edd0ff3ad79aa659696105f93c3a246ca0 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sun, 26 Dec 2021 17:52:00 +0100
Subject: [PATCH 035/712] update release that actually includes GW1NS-4 chipdb

---
 .cirrus/Dockerfile.ubuntu20.04 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index bf81a4a663..934bbbcbe0 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -65,4 +65,4 @@ RUN set -e -x ;\
     PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
 
 RUN set -e -x ;\
-    pip3 install apycula==0.2a1
+    pip3 install apycula==0.2a2

From c272d28e575bde2675a6ae7090a0d5f0f4c9c88f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 29 Dec 2021 21:43:33 +0000
Subject: [PATCH 036/712] docs: Fix typo

Signed-off-by: gatecat <gatecat@ds0.me>
---
 docs/archapi.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/archapi.md b/docs/archapi.md
index 5034d7d12f..f798254fad 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -280,7 +280,7 @@ Return a (preferably unique) number that represents this wire. This is used in d
 
 ### void bindWire(WireId wire, NetInfo \*net, PlaceStrength strength)
 
-Bind a wire to a net. This method must be used when binding a wire that is driven by a bel pin. Use `binPip()`
+Bind a wire to a net. This method must be used when binding a wire that is driven by a bel pin. Use `bindPip()`
 when binding a wire that is driven by a pip.
 
 This method must also update `net->wires`.

From 59874188a6800fbaa03ec21e3578160e963c2eb5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 30 Dec 2021 09:08:02 +0000
Subject: [PATCH 037/712] generic: Refactor for faster performance

This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/pywrappers.h            |  17 +-
 docs/generic.md                |  35 +++--
 generic/arch.cc                | 274 ++++++++++++++++-----------------
 generic/arch.h                 |  78 ++++++----
 generic/arch_pybindings.cc     |  64 ++++----
 generic/arch_pybindings.h      |  67 ++++++++
 generic/archdefs.h             |  39 ++++-
 generic/examples/write_fasm.py |   2 +-
 8 files changed, 348 insertions(+), 228 deletions(-)

diff --git a/common/pywrappers.h b/common/pywrappers.h
index 66dec6fb11..60ef65be7c 100644
--- a/common/pywrappers.h
+++ b/common/pywrappers.h
@@ -257,7 +257,7 @@ template <typename Class, typename FuncT, FuncT fn, typename arg1_conv> struct f
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1));
+        (base.*fn)(arg1_conv()(ctx, arg1));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
@@ -280,7 +280,7 @@ template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2));
+        (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
@@ -304,7 +304,7 @@ struct fn_wrapper_3a_v
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3));
+        (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
@@ -331,8 +331,7 @@ struct fn_wrapper_4a_v
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3),
-                          arg4_conv()(ctx, arg4));
+        (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), arg4_conv()(ctx, arg4));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
@@ -360,8 +359,8 @@ struct fn_wrapper_5a_v
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3),
-                          arg4_conv()(ctx, arg4), arg5_conv()(ctx, arg5));
+        (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), arg4_conv()(ctx, arg4),
+                   arg5_conv()(ctx, arg5));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
@@ -390,8 +389,8 @@ struct fn_wrapper_6a_v
     {
         Context *ctx = get_ctx<Class>(cls);
         Class &base = get_base<Class>(cls);
-        return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3),
-                          arg4_conv()(ctx, arg4), arg5_conv()(ctx, arg5), arg6_conv()(ctx, arg6));
+        (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), arg4_conv()(ctx, arg4),
+                   arg5_conv()(ctx, arg5), arg6_conv()(ctx, arg6));
     }
 
     template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); }
diff --git a/docs/generic.md b/docs/generic.md
index 0562bed314..96db872e84 100644
--- a/docs/generic.md
+++ b/docs/generic.md
@@ -12,35 +12,42 @@ will be worked on in the future.
 
 ## Python API
 
-All identifiers (`IdString`) are automatically converted to
-and from a Python string, so no manual conversion is required.
+All identifiers (`IdString`, `IdStringList`, `WireId`, `PipId`, and `BelId`) are
+automatically converted to and from a Python string, so no manual conversion is
+required.
+
+`IdStringList`s will be most efficient if strings can be split according to a
+separator (currently fixed to `/`), as only the components need be stored 
+in-memory. For example; instead of needing to store an entire pip name
+`X33/Y45/V4A_TO_A6` which scales badly for large numbers of pips; the strings
+`X33`, `Y45` and `V4A_TO_A6` are stored.
 
 Argument names are included in the Python bindings,
 so named arguments may be used.
 
-### void addWire(IdString name, IdString type, int x, int y);
+### void addWire(IdStringList name, IdString type, int x, int y);
 
 Adds a wire with a name, type (for user purposes only, ignored by all nextpnr code other than the UI) to the FPGA description. x and y give a nominal location of the wire for delay estimation purposes. Delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is not of importance.
 
-### addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, float delay, Loc loc);
+### addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, float delay, Loc loc);
 
 Adds a pip (programmable connection between two named wires). Pip delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance.
 
 Loc is constructed using `Loc(x, y, z)`. 'z' for pips is only important if region constraints (e.g. for partial reconfiguration regions) are used.
 
-### void addBel(IdString name, IdString type, Loc loc, bool gb, bool hidden);
+### void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
 
 Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique. If `hidden` is true, then the bel will not be included in utilisation reports (e.g. for routing/internal use bels).
 
-### void addBelInput(IdString bel, IdString name, IdString wire);
-### void addBelOutput(IdString bel, IdString name, IdString wire);
-### void addBelInout(IdString bel, IdString name, IdString wire);
+### void addBelInput(BelId bel, IdString name, WireId wire);
+### void addBelOutput(BelId bel, IdString name, WireId wire);
+### void addBelInout(BelId bel, IdString name, WireId wire);
 
 Adds an input, output or inout pin to a bel, with an associated wire. Note that both `bel` and `wire` must have been created before calling this function.
 
-### void addGroupBel(IdString group, IdString bel);
-### void addGroupWire(IdString group, IdString wire);
-### void addGroupPip(IdString group, IdString pip);
+### void addGroupBel(IdString group, BelId bel);
+### void addGroupWire(IdString group, WireId wire);
+### void addGroupPip(IdString group, PipId pip);
 ### void addGroupGroup(IdString group, IdString grp);
 
 Add a bel, wire, pip or subgroup to a group, which will be created if it doesn't already exist. Groups are purely for visual presentation purposes in the user interface and are not used by any place-and-route algorithms.
@@ -56,9 +63,9 @@ Add a graphic element to a _decal_, a reusable drawing that may be used to repre
 
 Sets the decal ID and offset for a wire, bel, pip or group in the UI.
 
-### void setWireAttr(IdString wire, IdString key, const std::string &value);
-### void setPipAttr(IdString pip, IdString key, const std::string &value);
-### void setBelAttr(IdString bel, IdString key, const std::string &value);
+### void setWireAttr(WireId wire, IdString key, const std::string &value);
+### void setPipAttr(PipId pip, IdString key, const std::string &value);
+### void setBelAttr(BelId bel, IdString key, const std::string &value);
 
 Sets an attribute on a wire, pip or bel. Attributes are displayed in the tree view in the UI, but have no bearing on place-and-route itself.
 
diff --git a/generic/arch.cc b/generic/arch.cc
index 0695ec9880..d899bd0b68 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -28,46 +28,27 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-WireInfo &Arch::wire_info(IdStringList wire)
+WireId Arch::addWire(IdStringList name, IdString type, int x, int y)
 {
-    auto w = wires.find(wire);
-    if (w == wires.end())
-        NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(getCtx()));
-    return w->second;
-}
-
-PipInfo &Arch::pip_info(IdStringList pip)
-{
-    auto p = pips.find(pip);
-    if (p == pips.end())
-        NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(getCtx()));
-    return p->second;
-}
-
-BelInfo &Arch::bel_info(IdStringList bel)
-{
-    auto b = bels.find(bel);
-    if (b == bels.end())
-        NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(getCtx()));
-    return b->second;
-}
-
-void Arch::addWire(IdStringList name, IdString type, int x, int y)
-{
-    NPNR_ASSERT(wires.count(name) == 0);
-    WireInfo &wi = wires[name];
+    NPNR_ASSERT(wire_by_name.count(name) == 0);
+    WireId wire(wires.size());
+    wire_by_name[name] = wire;
+    wires.emplace_back();
+    WireInfo &wi = wires.back();
     wi.name = name;
     wi.type = type;
     wi.x = x;
     wi.y = y;
-
-    wire_ids.push_back(name);
+    return wire;
 }
 
-void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc)
+PipId Arch::addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc)
 {
-    NPNR_ASSERT(pips.count(name) == 0);
-    PipInfo &pi = pips[name];
+    NPNR_ASSERT(pip_by_name.count(name) == 0);
+    PipId pip(pips.size());
+    pip_by_name[name] = pip;
+    pips.emplace_back();
+    PipInfo &pi = pips.back();
     pi.name = name;
     pi.type = type;
     pi.srcWire = srcWire;
@@ -75,9 +56,8 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
     pi.delay = delay;
     pi.loc = loc;
 
-    wire_info(srcWire).downhill.push_back(name);
-    wire_info(dstWire).uphill.push_back(name);
-    pip_ids.push_back(name);
+    wire_info(srcWire).downhill.push_back(pip);
+    wire_info(dstWire).uphill.push_back(pip);
 
     if (int(tilePipDimZ.size()) <= loc.x)
         tilePipDimZ.resize(loc.x + 1);
@@ -88,13 +68,17 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
     gridDimX = std::max(gridDimX, loc.x + 1);
     gridDimY = std::max(gridDimY, loc.x + 1);
     tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
+    return pip;
 }
 
-void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
+BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
 {
-    NPNR_ASSERT(bels.count(name) == 0);
+    NPNR_ASSERT(bel_by_name.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
-    BelInfo &bi = bels[name];
+    BelId bel(bels.size());
+    bel_by_name[name] = bel;
+    bels.emplace_back();
+    BelInfo &bi = bels.back();
     bi.name = name;
     bi.type = type;
     bi.x = loc.x;
@@ -103,8 +87,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
     bi.gb = gb;
     bi.hidden = hidden;
 
-    bel_ids.push_back(name);
-    bel_by_loc[loc] = name;
+    bel_by_loc[loc] = bel;
 
     if (int(bels_by_tile.size()) <= loc.x)
         bels_by_tile.resize(loc.x + 1);
@@ -112,7 +95,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
     if (int(bels_by_tile[loc.x].size()) <= loc.y)
         bels_by_tile[loc.x].resize(loc.y + 1);
 
-    bels_by_tile[loc.x][loc.y].push_back(name);
+    bels_by_tile[loc.x][loc.y].push_back(bel);
 
     if (int(tileBelDimZ.size()) <= loc.x)
         tileBelDimZ.resize(loc.x + 1);
@@ -123,49 +106,50 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
     gridDimX = std::max(gridDimX, loc.x + 1);
     gridDimY = std::max(gridDimY, loc.x + 1);
     tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
+    return bel;
 }
 
-void Arch::addBelInput(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelInput(BelId bel, IdString name, WireId wire)
 {
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
+    auto &bi = bel_info(bel);
+    NPNR_ASSERT(bi.pins.count(name) == 0);
+    PinInfo &pi = bi.pins[name];
     pi.name = name;
     pi.wire = wire;
     pi.type = PORT_IN;
 
-    wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addBelOutput(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
 {
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
+    auto &bi = bel_info(bel);
+    NPNR_ASSERT(bi.pins.count(name) == 0);
+    PinInfo &pi = bi.pins[name];
     pi.name = name;
     pi.wire = wire;
     pi.type = PORT_OUT;
 
-    wire_info(wire).uphill_bel_pin = BelPin{bel, name};
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addBelInout(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelInout(BelId bel, IdString name, WireId wire)
 {
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
+    auto &bi = bel_info(bel);
+    NPNR_ASSERT(bi.pins.count(name) == 0);
+    PinInfo &pi = bi.pins[name];
     pi.name = name;
     pi.wire = wire;
     pi.type = PORT_INOUT;
 
-    wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
     wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
-void Arch::addGroupBel(IdStringList group, IdStringList bel) { groups[group].bels.push_back(bel); }
+void Arch::addGroupBel(IdStringList group, BelId bel) { groups[group].bels.push_back(bel); }
 
-void Arch::addGroupWire(IdStringList group, IdStringList wire) { groups[group].wires.push_back(wire); }
+void Arch::addGroupWire(IdStringList group, WireId wire) { groups[group].wires.push_back(wire); }
 
-void Arch::addGroupPip(IdStringList group, IdStringList pip) { groups[group].pips.push_back(pip); }
+void Arch::addGroupPip(IdStringList group, PipId pip) { groups[group].pips.push_back(pip); }
 
 void Arch::addGroupGroup(IdStringList group, IdStringList grp) { groups[group].groups.push_back(grp); }
 
@@ -177,19 +161,19 @@ void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
 
 void Arch::setWireDecal(WireId wire, DecalXY decalxy)
 {
-    wire_info(wire).decalxy = decalxy;
+    wires.at(wire.index).decalxy = decalxy;
     refreshUiWire(wire);
 }
 
 void Arch::setPipDecal(PipId pip, DecalXY decalxy)
 {
-    pip_info(pip).decalxy = decalxy;
+    pips.at(pip.index).decalxy = decalxy;
     refreshUiPip(pip);
 }
 
 void Arch::setBelDecal(BelId bel, DecalXY decalxy)
 {
-    bel_info(bel).decalxy = decalxy;
+    bels.at(bel.index).decalxy = decalxy;
     refreshUiBel(bel);
 }
 
@@ -199,14 +183,11 @@ void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
     refreshUiGroup(group);
 }
 
-void Arch::setWireAttr(IdStringList wire, IdString key, const std::string &value)
-{
-    wire_info(wire).attrs[key] = value;
-}
+void Arch::setWireAttr(WireId wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
 
-void Arch::setPipAttr(IdStringList pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
+void Arch::setPipAttr(PipId pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
 
-void Arch::setBelAttr(IdStringList bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
+void Arch::setBelAttr(BelId bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
 
 void Arch::setLutK(int K) { args.K = K; }
 
@@ -268,16 +249,19 @@ void IdString::initialize_arch(const BaseCtx *ctx) {}
 
 BelId Arch::getBelByName(IdStringList name) const
 {
-    if (bels.count(name))
-        return name;
-    return BelId();
+    if (name.size() == 0)
+        return BelId();
+    auto fnd = bel_by_name.find(name);
+    if (fnd == bel_by_name.end())
+        NPNR_ASSERT_FALSE_STR("no bel named " + name.str(getCtx()));
+    return fnd->second;
 }
 
-IdStringList Arch::getBelName(BelId bel) const { return bel; }
+IdStringList Arch::getBelName(BelId bel) const { return bel_info(bel).name; }
 
 Loc Arch::getBelLocation(BelId bel) const
 {
-    auto &info = bels.at(bel);
+    auto &info = bel_info(bel);
     return Loc(info.x, info.y, info.z);
 }
 
@@ -291,7 +275,7 @@ BelId Arch::getBelByLocation(Loc loc) const
 
 const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_by_tile.at(x).at(y); }
 
-bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
+bool Arch::getBelGlobalBuf(BelId bel) const { return bel_info(bel).gb; }
 
 uint32_t Arch::getBelChecksum(BelId bel) const
 {
@@ -301,7 +285,7 @@ uint32_t Arch::getBelChecksum(BelId bel) const
 
 void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
 {
-    bels.at(bel).bound_cell = cell;
+    bel_info(bel).bound_cell = cell;
     cell->bel = bel;
     cell->belStrength = strength;
     refreshUiBel(bel);
@@ -309,40 +293,41 @@ void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
 
 void Arch::unbindBel(BelId bel)
 {
-    bels.at(bel).bound_cell->bel = BelId();
-    bels.at(bel).bound_cell->belStrength = STRENGTH_NONE;
-    bels.at(bel).bound_cell = nullptr;
+    auto &bi = bel_info(bel);
+    bi.bound_cell->bel = BelId();
+    bi.bound_cell->belStrength = STRENGTH_NONE;
+    bi.bound_cell = nullptr;
     refreshUiBel(bel);
 }
 
-bool Arch::checkBelAvail(BelId bel) const { return bels.at(bel).bound_cell == nullptr; }
+bool Arch::checkBelAvail(BelId bel) const { return bel_info(bel).bound_cell == nullptr; }
 
-CellInfo *Arch::getBoundBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
+CellInfo *Arch::getBoundBelCell(BelId bel) const { return bel_info(bel).bound_cell; }
 
-CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
+CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bel_info(bel).bound_cell; }
 
-const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
+linear_range<BelId> Arch::getBels() const { return linear_range<BelId>(bels.size()); }
 
-IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
+IdString Arch::getBelType(BelId bel) const { return bel_info(bel).type; }
 
-bool Arch::getBelHidden(BelId bel) const { return bels.at(bel).hidden; }
+bool Arch::getBelHidden(BelId bel) const { return bel_info(bel).hidden; }
 
-const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
+const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bel_info(bel).attrs; }
 
 WireId Arch::getBelPinWire(BelId bel, IdString pin) const
 {
-    const auto &bdata = bels.at(bel);
+    const auto &bdata = bel_info(bel);
     if (!bdata.pins.count(pin))
         log_error("bel '%s' has no pin '%s'\n", getCtx()->nameOfBel(bel), pin.c_str(this));
     return bdata.pins.at(pin).wire;
 }
 
-PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).type; }
+PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bel_info(bel).pins.at(pin).type; }
 
 std::vector<IdString> Arch::getBelPins(BelId bel) const
 {
     std::vector<IdString> ret;
-    for (auto &it : bels.at(bel).pins)
+    for (auto &it : bel_info(bel).pins)
         ret.push_back(it.first);
     return ret;
 }
@@ -356,26 +341,25 @@ const std::vector<IdString> &Arch::getBelPinsForCellPin(const CellInfo *cell_inf
 
 WireId Arch::getWireByName(IdStringList name) const
 {
-    if (wires.count(name))
-        return name;
-    return WireId();
+    if (name.size() == 0)
+        return WireId();
+    auto fnd = wire_by_name.find(name);
+    if (fnd == wire_by_name.end())
+        NPNR_ASSERT_FALSE_STR("no wire named " + name.str(getCtx()));
+    return fnd->second;
 }
 
-IdStringList Arch::getWireName(WireId wire) const { return wire; }
+IdStringList Arch::getWireName(WireId wire) const { return wire_info(wire).name; }
 
-IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
+IdString Arch::getWireType(WireId wire) const { return wire_info(wire).type; }
 
-const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wires.at(wire).attrs; }
+const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wire_info(wire).attrs; }
 
-uint32_t Arch::getWireChecksum(WireId wire) const
-{
-    // FIXME
-    return 0;
-}
+uint32_t Arch::getWireChecksum(WireId wire) const { return wire.index; }
 
 void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
 {
-    wires.at(wire).bound_net = net;
+    wire_info(wire).bound_net = net;
     net->wires[wire].pip = PipId();
     net->wires[wire].strength = strength;
     refreshUiWire(wire);
@@ -383,55 +367,54 @@ void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
 
 void Arch::unbindWire(WireId wire)
 {
-    auto &net_wires = wires.at(wire).bound_net->wires;
+    auto &net_wires = wire_info(wire).bound_net->wires;
 
     auto pip = net_wires.at(wire).pip;
     if (pip != PipId()) {
-        pips.at(pip).bound_net = nullptr;
+        pip_info(pip).bound_net = nullptr;
         refreshUiPip(pip);
     }
 
     net_wires.erase(wire);
-    wires.at(wire).bound_net = nullptr;
+    wire_info(wire).bound_net = nullptr;
     refreshUiWire(wire);
 }
 
-bool Arch::checkWireAvail(WireId wire) const { return wires.at(wire).bound_net == nullptr; }
+bool Arch::checkWireAvail(WireId wire) const { return wire_info(wire).bound_net == nullptr; }
 
-NetInfo *Arch::getBoundWireNet(WireId wire) const { return wires.at(wire).bound_net; }
+NetInfo *Arch::getBoundWireNet(WireId wire) const { return wire_info(wire).bound_net; }
 
-NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wires.at(wire).bound_net; }
+NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wire_info(wire).bound_net; }
 
-const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wires.at(wire).bel_pins; }
+const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wire_info(wire).bel_pins; }
 
-const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
+linear_range<WireId> Arch::getWires() const { return linear_range<WireId>(wires.size()); }
 
 // ---------------------------------------------------------------
 
 PipId Arch::getPipByName(IdStringList name) const
 {
-    if (pips.count(name))
-        return name;
-    return PipId();
+    if (name.size() == 0)
+        return PipId();
+    auto fnd = pip_by_name.find(name);
+    if (fnd == pip_by_name.end())
+        NPNR_ASSERT_FALSE_STR("no pip named " + name.str(getCtx()));
+    return fnd->second;
 }
 
-IdStringList Arch::getPipName(PipId pip) const { return pip; }
+IdStringList Arch::getPipName(PipId pip) const { return pip_info(pip).name; }
 
-IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
+IdString Arch::getPipType(PipId pip) const { return pip_info(pip).type; }
 
-const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
+const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pip_info(pip).attrs; }
 
-uint32_t Arch::getPipChecksum(PipId wire) const
-{
-    // FIXME
-    return 0;
-}
+uint32_t Arch::getPipChecksum(PipId pip) const { return pip.index; }
 
 void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
 {
-    WireId wire = pips.at(pip).dstWire;
-    pips.at(pip).bound_net = net;
-    wires.at(wire).bound_net = net;
+    WireId wire = pip_info(pip).dstWire;
+    pip_info(pip).bound_net = net;
+    wire_info(wire).bound_net = net;
     net->wires[wire].pip = pip;
     net->wires[wire].strength = strength;
     refreshUiPip(pip);
@@ -440,41 +423,44 @@ void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
 
 void Arch::unbindPip(PipId pip)
 {
-    WireId wire = pips.at(pip).dstWire;
-    wires.at(wire).bound_net->wires.erase(wire);
-    pips.at(pip).bound_net = nullptr;
-    wires.at(wire).bound_net = nullptr;
+    WireId wire = pip_info(pip).dstWire;
+    wire_info(wire).bound_net->wires.erase(wire);
+    pip_info(pip).bound_net = nullptr;
+    wire_info(wire).bound_net = nullptr;
     refreshUiPip(pip);
     refreshUiWire(wire);
 }
 
-bool Arch::checkPipAvail(PipId pip) const { return pips.at(pip).bound_net == nullptr; }
+bool Arch::checkPipAvail(PipId pip) const { return pip_info(pip).bound_net == nullptr; }
 
 bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
 {
-    NetInfo *bound_net = pips.at(pip).bound_net;
+    NetInfo *bound_net = pip_info(pip).bound_net;
     return bound_net == nullptr || bound_net == net;
 }
 
-NetInfo *Arch::getBoundPipNet(PipId pip) const { return pips.at(pip).bound_net; }
+NetInfo *Arch::getBoundPipNet(PipId pip) const { return pip_info(pip).bound_net; }
 
-NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pips.at(pip).bound_net; }
+NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pip_info(pip).bound_net; }
 
-WireId Arch::getConflictingPipWire(PipId pip) const { return pips.at(pip).bound_net ? pips.at(pip).dstWire : WireId(); }
+WireId Arch::getConflictingPipWire(PipId pip) const
+{
+    return pip_info(pip).bound_net ? pip_info(pip).dstWire : WireId();
+}
 
-const std::vector<PipId> &Arch::getPips() const { return pip_ids; }
+linear_range<PipId> Arch::getPips() const { return linear_range<PipId>(pips.size()); }
 
-Loc Arch::getPipLocation(PipId pip) const { return pips.at(pip).loc; }
+Loc Arch::getPipLocation(PipId pip) const { return pip_info(pip).loc; }
 
-WireId Arch::getPipSrcWire(PipId pip) const { return pips.at(pip).srcWire; }
+WireId Arch::getPipSrcWire(PipId pip) const { return pip_info(pip).srcWire; }
 
-WireId Arch::getPipDstWire(PipId pip) const { return pips.at(pip).dstWire; }
+WireId Arch::getPipDstWire(PipId pip) const { return pip_info(pip).dstWire; }
 
-DelayQuad Arch::getPipDelay(PipId pip) const { return DelayQuad(pips.at(pip).delay); }
+DelayQuad Arch::getPipDelay(PipId pip) const { return DelayQuad(pip_info(pip).delay); }
 
-const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wires.at(wire).downhill; }
+const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wire_info(wire).downhill; }
 
-const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.at(wire).uphill; }
+const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wire_info(wire).uphill; }
 
 // ---------------------------------------------------------------
 
@@ -502,8 +488,8 @@ const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return g
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
-    const WireInfo &s = wires.at(src);
-    const WireInfo &d = wires.at(dst);
+    const WireInfo &s = wire_info(src);
+    const WireInfo &d = wire_info(dst);
     int dx = abs(s.x - d.x);
     int dy = abs(s.y - d.y);
     return (dx + dy) * args.delayScale + args.delayOffset;
@@ -527,10 +513,10 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     ArcBounds bb;
 
-    int src_x = wires.at(src).x;
-    int src_y = wires.at(src).y;
-    int dst_x = wires.at(dst).x;
-    int dst_y = wires.at(dst).y;
+    int src_x = wire_info(src).x;
+    int src_y = wire_info(src).y;
+    int dst_x = wire_info(dst).x;
+    int dst_y = wire_info(dst).y;
 
     bb.x0 = src_x;
     bb.y0 = src_y;
@@ -611,11 +597,11 @@ const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
     return decal_graphics.at(decal);
 }
 
-DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; }
+DecalXY Arch::getBelDecal(BelId bel) const { return bel_info(bel).decalxy; }
 
-DecalXY Arch::getWireDecal(WireId wire) const { return wires.at(wire).decalxy; }
+DecalXY Arch::getWireDecal(WireId wire) const { return wire_info(wire).decalxy; }
 
-DecalXY Arch::getPipDecal(PipId pip) const { return pips.at(pip).decalxy; }
+DecalXY Arch::getPipDecal(PipId pip) const { return pip_info(pip).decalxy; }
 
 DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
 
diff --git a/generic/arch.h b/generic/arch.h
index 7f574f31c5..885089ca9d 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -60,8 +60,6 @@ struct WireInfo
     std::map<IdString, std::string> attrs;
     NetInfo *bound_net;
     std::vector<PipId> downhill, uphill;
-    BelPin uphill_bel_pin;
-    std::vector<BelPin> downhill_bel_pins;
     std::vector<BelPin> bel_pins;
     DecalXY decalxy;
     int x, y;
@@ -111,23 +109,40 @@ struct CellTiming
     dict<IdString, std::vector<TimingClockingInfo>> clockingInfo;
 };
 
+template <typename TId> struct linear_range
+{
+    struct iterator
+    {
+        explicit iterator(int32_t index) : index(index){};
+        int32_t index;
+        bool operator==(const iterator &other) const { return index == other.index; }
+        bool operator!=(const iterator &other) const { return index != other.index; }
+        void operator++() { ++index; }
+        TId operator*() const { return TId(index); }
+    };
+    explicit linear_range(int32_t size) : size(size){};
+    int32_t size;
+    iterator begin() const { return iterator(0); }
+    iterator end() const { return iterator(size); }
+};
+
 struct ArchRanges
 {
     using ArchArgsT = ArchArgs;
     // Bels
-    using AllBelsRangeT = const std::vector<BelId> &;
+    using AllBelsRangeT = linear_range<BelId>;
     using TileBelsRangeT = const std::vector<BelId> &;
     using BelAttrsRangeT = const std::map<IdString, std::string> &;
     using BelPinsRangeT = std::vector<IdString>;
     using CellBelPinRangeT = const std::vector<IdString> &;
     // Wires
-    using AllWiresRangeT = const std::vector<WireId> &;
+    using AllWiresRangeT = linear_range<WireId>;
     using DownhillPipRangeT = const std::vector<PipId> &;
     using UphillPipRangeT = const std::vector<PipId> &;
     using WireBelPinRangeT = const std::vector<BelPin> &;
     using WireAttrsRangeT = const std::map<IdString, std::string> &;
     // Pips
-    using AllPipsRangeT = const std::vector<PipId> &;
+    using AllPipsRangeT = linear_range<PipId>;
     using PipAttrsRangeT = const std::map<IdString, std::string> &;
     // Groups
     using AllGroupsRangeT = std::vector<GroupId>;
@@ -147,17 +162,22 @@ struct Arch : ArchAPI<ArchRanges>
 {
     std::string chipName;
 
-    dict<IdStringList, WireInfo> wires;
-    dict<IdStringList, PipInfo> pips;
-    dict<IdStringList, BelInfo> bels;
+    std::vector<WireInfo> wires;
+    std::vector<PipInfo> pips;
+    std::vector<BelInfo> bels;
     dict<GroupId, GroupInfo> groups;
 
-    // These functions include useful errors if not found
-    WireInfo &wire_info(IdStringList wire);
-    PipInfo &pip_info(IdStringList wire);
-    BelInfo &bel_info(IdStringList wire);
+    WireInfo &wire_info(WireId wire) { return wires.at(wire.index); }
+    PipInfo &pip_info(PipId pip) { return pips.at(pip.index); }
+    BelInfo &bel_info(BelId bel) { return bels.at(bel.index); }
+
+    const WireInfo &wire_info(WireId wire) const { return wires.at(wire.index); }
+    const PipInfo &pip_info(PipId pip) const { return pips.at(pip.index); }
+    const BelInfo &bel_info(BelId bel) const { return bels.at(bel.index); }
 
-    std::vector<IdStringList> bel_ids, wire_ids, pip_ids;
+    dict<IdStringList, WireId> wire_by_name;
+    dict<IdStringList, PipId> pip_by_name;
+    dict<IdStringList, BelId> bel_by_name;
 
     dict<Loc, BelId> bel_by_loc;
     std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
@@ -170,17 +190,17 @@ struct Arch : ArchAPI<ArchRanges>
 
     dict<IdString, CellTiming> cellTiming;
 
-    void addWire(IdStringList name, IdString type, int x, int y);
-    void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc);
+    WireId addWire(IdStringList name, IdString type, int x, int y);
+    PipId addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc);
 
-    void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
-    void addBelInput(IdStringList bel, IdString name, IdStringList wire);
-    void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
-    void addBelInout(IdStringList bel, IdString name, IdStringList wire);
+    BelId addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
+    void addBelInput(BelId bel, IdString name, WireId wire);
+    void addBelOutput(BelId bel, IdString name, WireId wire);
+    void addBelInout(BelId bel, IdString name, WireId wire);
 
-    void addGroupBel(IdStringList group, IdStringList bel);
-    void addGroupWire(IdStringList group, IdStringList wire);
-    void addGroupPip(IdStringList group, IdStringList pip);
+    void addGroupBel(IdStringList group, BelId bel);
+    void addGroupWire(IdStringList group, WireId wire);
+    void addGroupPip(IdStringList group, PipId pip);
     void addGroupGroup(IdStringList group, IdStringList grp);
 
     void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
@@ -189,9 +209,9 @@ struct Arch : ArchAPI<ArchRanges>
     void setBelDecal(BelId bel, DecalXY decalxy);
     void setGroupDecal(GroupId group, DecalXY decalxy);
 
-    void setWireAttr(IdStringList wire, IdString key, const std::string &value);
-    void setPipAttr(IdStringList pip, IdString key, const std::string &value);
-    void setBelAttr(IdStringList bel, IdString key, const std::string &value);
+    void setWireAttr(WireId wire, IdString key, const std::string &value);
+    void setPipAttr(PipId pip, IdString key, const std::string &value);
+    void setBelAttr(BelId bel, IdString key, const std::string &value);
 
     void setLutK(int K);
     void setDelayScaling(double scale, double offset);
@@ -234,7 +254,7 @@ struct Arch : ArchAPI<ArchRanges>
     bool checkBelAvail(BelId bel) const override;
     CellInfo *getBoundBelCell(BelId bel) const override;
     CellInfo *getConflictingBelCell(BelId bel) const override;
-    const std::vector<BelId> &getBels() const override;
+    linear_range<BelId> getBels() const override;
     IdString getBelType(BelId bel) const override;
     bool getBelHidden(BelId bel) const override;
     const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
@@ -255,7 +275,7 @@ struct Arch : ArchAPI<ArchRanges>
     WireId getConflictingWireWire(WireId wire) const override { return wire; }
     NetInfo *getConflictingWireNet(WireId wire) const override;
     DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
-    const std::vector<WireId> &getWires() const override;
+    linear_range<WireId> getWires() const override;
     const std::vector<BelPin> &getWireBelPins(WireId wire) const override;
 
     PipId getPipByName(IdStringList name) const override;
@@ -270,7 +290,7 @@ struct Arch : ArchAPI<ArchRanges>
     NetInfo *getBoundPipNet(PipId pip) const override;
     WireId getConflictingPipWire(PipId pip) const override;
     NetInfo *getConflictingPipNet(PipId pip) const override;
-    const std::vector<PipId> &getPips() const override;
+    linear_range<PipId> getPips() const override;
     Loc getPipLocation(PipId pip) const override;
     WireId getPipSrcWire(PipId pip) const override;
     WireId getPipDstWire(PipId pip) const override;
@@ -307,7 +327,7 @@ struct Arch : ArchAPI<ArchRanges>
     {
         pool<IdString> cell_types;
         for (auto bel : bels) {
-            cell_types.insert(bel.second.type);
+            cell_types.insert(bel.type);
         }
 
         return std::vector<IdString>{cell_types.begin(), cell_types.end()};
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index df59b4fe76..92c782529b 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -42,6 +42,10 @@ void arch_wrap_python(py::module &m)
 {
     using namespace PythonConversion;
 
+    typedef linear_range<BelId> BelRange;
+    typedef linear_range<WireId> WireRange;
+    typedef linear_range<PipId> AllPipRange;
+
     auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
 
     auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
@@ -74,8 +78,8 @@ void arch_wrap_python(py::module &m)
                   conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
     fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
                   deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
-    fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
-                  wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
+    fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
+                                                                                                             "getBels");
 
     fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
                   conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
@@ -96,11 +100,11 @@ void arch_wrap_python(py::module &m)
     fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
                   deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
 
-    fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
-                  wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
+    fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap(
+            ctx_cls, "getWires");
 
-    fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
-                  wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
+    fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap(
+            ctx_cls, "getPips");
     fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
                   conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
     fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
@@ -156,50 +160,50 @@ void arch_wrap_python(py::module &m)
                                                                                              "name"_a, "type"_a, "x"_a,
                                                                                              "y"_a);
     fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdStringList>, conv_from_str<IdStringList>,
-                    pass_through<delay_t>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
-                                                                        "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
+                    conv_from_str<IdString>, conv_from_str<WireId>, conv_from_str<WireId>, pass_through<delay_t>,
+                    pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
+                                                 "delay"_a, "loc"_a);
 
     fn_wrapper_5a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
                     conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>,
                     pass_through<bool>>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a, "hidden"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
-                                                                                    "name"_a, "wire"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
-                                                                                    "name"_a, "wire"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
-                                                                                    "name"_a, "wire"_a);
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<BelId>,
+                    conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInput", "bel"_a, "name"_a,
+                                                                              "wire"_a);
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<BelId>,
+                    conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
+                                                                              "name"_a, "wire"_a);
+    fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>,
+                    conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a,
+                                                                              "wire"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
-                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
+                    conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdStringList>,
-                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
+                    conv_from_str<WireId>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdStringList>,
-                    conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdStringList>,
+                    conv_from_str<PipId>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
+    fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupGroup, conv_from_str<IdStringList>,
                     conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
                     pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic"));
-    fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>,
+    fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<WireId>,
                     unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", "wire"_a, "decalxy"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>,
+    fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<PipId>,
                     unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", "pip"_a, "decalxy"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>,
+    fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<BelId>,
                     unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", "bel"_a, "decalxy"_a);
     fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
                     unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", "group"_a, "decalxy"_a);
 
-    fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
+    fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<WireId>,
                     conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", "wire"_a,
                                                                                   "key"_a, "value"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
+    fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<BelId>,
                     conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", "bel"_a,
                                                                                   "key"_a, "value"_a);
-    fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
+    fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<PipId>,
                     conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", "pip"_a,
                                                                                   "key"_a, "value"_a);
 
@@ -254,6 +258,10 @@ void arch_wrap_python(py::module &m)
                   pass_through<bool>, conv_from_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls,
                                                                                                "isValidBelForCellType");
 
+    WRAP_RANGE(m, Bel, conv_to_str<BelId>);
+    WRAP_RANGE(m, Wire, conv_to_str<WireId>);
+    WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
+
     WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
     WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
     WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
diff --git a/generic/arch_pybindings.h b/generic/arch_pybindings.h
index 9a5735408c..72d688dc61 100644
--- a/generic/arch_pybindings.h
+++ b/generic/arch_pybindings.h
@@ -26,6 +26,73 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+namespace PythonConversion {
+
+template <> struct string_converter<BelId>
+{
+    BelId from_str(Context *ctx, std::string name) { return ctx->getBelByNameStr(name); }
+
+    std::string to_str(Context *ctx, BelId id)
+    {
+        if (id == BelId())
+            throw bad_wrap();
+        return ctx->getBelName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<WireId>
+{
+    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByNameStr(name); }
+
+    std::string to_str(Context *ctx, WireId id)
+    {
+        if (id == WireId())
+            throw bad_wrap();
+        return ctx->getWireName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<const WireId>
+{
+    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByNameStr(name); }
+
+    std::string to_str(Context *ctx, WireId id)
+    {
+        if (id == WireId())
+            throw bad_wrap();
+        return ctx->getWireName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<PipId>
+{
+    PipId from_str(Context *ctx, std::string name) { return ctx->getPipByNameStr(name); }
+
+    std::string to_str(Context *ctx, PipId id)
+    {
+        if (id == PipId())
+            throw bad_wrap();
+        return ctx->getPipName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<BelPin>
+{
+    BelPin from_str(Context *ctx, std::string name)
+    {
+        NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
+    }
+
+    std::string to_str(Context *ctx, BelPin pin)
+    {
+        if (pin.bel == BelId())
+            throw bad_wrap();
+        return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
+    }
+};
+
+} // namespace PythonConversion
+
 NEXTPNR_NAMESPACE_END
 #endif
 #endif
diff --git a/generic/archdefs.h b/generic/archdefs.h
index c46fba93c0..2d46c0a2d1 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -27,9 +27,42 @@ NEXTPNR_NAMESPACE_BEGIN
 
 typedef float delay_t;
 
-typedef IdStringList BelId;
-typedef IdStringList WireId;
-typedef IdStringList PipId;
+struct BelId
+{
+    BelId() : index(-1){};
+    explicit BelId(int32_t index) : index(index){};
+    int32_t index = -1;
+
+    bool operator==(const BelId &other) const { return index == other.index; }
+    bool operator!=(const BelId &other) const { return index != other.index; }
+    bool operator<(const BelId &other) const { return index < other.index; }
+    unsigned int hash() const { return index; }
+};
+
+struct WireId
+{
+    WireId() : index(-1){};
+    explicit WireId(int32_t index) : index(index){};
+    int32_t index = -1;
+
+    bool operator==(const WireId &other) const { return index == other.index; }
+    bool operator!=(const WireId &other) const { return index != other.index; }
+    bool operator<(const WireId &other) const { return index < other.index; }
+    unsigned int hash() const { return index; }
+};
+
+struct PipId
+{
+    PipId() : index(-1){};
+    explicit PipId(int32_t index) : index(index){};
+    int32_t index = -1;
+
+    bool operator==(const PipId &other) const { return index == other.index; }
+    bool operator!=(const PipId &other) const { return index != other.index; }
+    bool operator<(const PipId &other) const { return index < other.index; }
+    unsigned int hash() const { return index; }
+};
+
 typedef IdStringList GroupId;
 typedef IdStringList DecalId;
 typedef IdString BelBucketId;
diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py
index ede8f16b51..057e779cad 100644
--- a/generic/examples/write_fasm.py
+++ b/generic/examples/write_fasm.py
@@ -29,7 +29,7 @@ def write_fasm(ctx, paramCfg, f):
 	for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
 		print("# Net %s" % nname, file=f)
 		for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
-			if pip.pip != "":
+			if pip.pip is not None:
 				print("%s" % pip.pip, file=f)
 		print("", file=f)
 	for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):

From 69a4e3e544f3b0cff296a01c51d325d23e265fb1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 30 Dec 2021 21:32:04 +0000
Subject: [PATCH 038/712] SSOArray: Implement move and assignment operators

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/sso_array.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/common/sso_array.h b/common/sso_array.h
index 1fae6c57be..80e7d1c1fd 100644
--- a/common/sso_array.h
+++ b/common/sso_array.h
@@ -70,6 +70,26 @@ template <typename T, std::size_t N> class SSOArray
         std::copy(other.begin(), other.end(), begin());
     }
 
+    SSOArray(SSOArray &&other) : m_size(other.size())
+    {
+        if (is_heap())
+            data_heap = other.data_heap;
+        else
+            std::copy(other.begin(), other.end(), begin());
+        other.m_size = 0;
+    }
+    SSOArray &operator=(const SSOArray &other)
+    {
+        if (&other == this)
+            return *this;
+        if (is_heap())
+            delete[] data_heap;
+        m_size = other.m_size;
+        alloc();
+        std::copy(other.begin(), other.end(), begin());
+        return *this;
+    }
+
     template <typename Tother> SSOArray(const Tother &other) : m_size(other.size())
     {
         alloc();

From 045ce3f148a90ae4dc8751f856d39a985384d0cc Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 3 Jan 2022 17:48:31 +1000
Subject: [PATCH 039/712] gowin: Fix last MUX8

In fact, there is also an input/output column.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 2f61685a33..8c654b2eb9 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -612,7 +612,7 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
         int gcol = col + 1;
 
         // no MUX2_LUT8 in the last column
-        if (j == 7 && col == getGridDimX() - 1) {
+        if (j == 7 && col == getGridDimX() - 2) {
             continue;
         }
 

From e88bd34c02272ecdad6295123941d9040fa4f043 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 30 Dec 2021 13:18:34 +0000
Subject: [PATCH 040/712] Viaduct API for a hybrid between generic and
 full-custom arch

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.cc                               |  60 +++-
 generic/arch.h                                |  33 +-
 generic/archdefs.h                            |   5 +-
 generic/family.cmake                          |   7 +
 generic/main.cc                               |  15 +-
 generic/pack.cc                               |  14 +-
 generic/viaduct/example/.gitignore            |   1 +
 generic/viaduct/example/constids.inc          |  14 +
 generic/viaduct/example/example.cc            | 306 ++++++++++++++++++
 generic/viaduct/example/example_map.v         |  12 +
 generic/viaduct/example/example_prims.v       |  35 ++
 .../viaduct/example/synth_viaduct_example.tcl |  24 ++
 generic/viaduct/example/viaduct_example.sh    |   6 +
 generic/viaduct_api.cc                        | 118 +++++++
 generic/viaduct_api.h                         | 114 +++++++
 generic/viaduct_constids.h                    |  74 +++++
 generic/viaduct_helpers.cc                    | 163 ++++++++++
 generic/viaduct_helpers.h                     |  82 +++++
 18 files changed, 1055 insertions(+), 28 deletions(-)
 create mode 100644 generic/viaduct/example/.gitignore
 create mode 100644 generic/viaduct/example/constids.inc
 create mode 100644 generic/viaduct/example/example.cc
 create mode 100644 generic/viaduct/example/example_map.v
 create mode 100644 generic/viaduct/example/example_prims.v
 create mode 100644 generic/viaduct/example/synth_viaduct_example.tcl
 create mode 100755 generic/viaduct/example/viaduct_example.sh
 create mode 100644 generic/viaduct_api.cc
 create mode 100644 generic/viaduct_api.h
 create mode 100644 generic/viaduct_constids.h
 create mode 100644 generic/viaduct_helpers.cc
 create mode 100644 generic/viaduct_helpers.h

diff --git a/generic/arch.cc b/generic/arch.cc
index d899bd0b68..ad054efd6d 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -25,6 +25,7 @@
 #include "router1.h"
 #include "router2.h"
 #include "util.h"
+#include "viaduct_api.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -285,6 +286,8 @@ uint32_t Arch::getBelChecksum(BelId bel) const
 
 void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
 {
+    if (uarch)
+        uarch->notifyBelChange(bel, cell);
     bel_info(bel).bound_cell = cell;
     cell->bel = bel;
     cell->belStrength = strength;
@@ -293,6 +296,8 @@ void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
 
 void Arch::unbindBel(BelId bel)
 {
+    if (uarch)
+        uarch->notifyBelChange(bel, nullptr);
     auto &bi = bel_info(bel);
     bi.bound_cell->bel = BelId();
     bi.bound_cell->belStrength = STRENGTH_NONE;
@@ -300,7 +305,10 @@ void Arch::unbindBel(BelId bel)
     refreshUiBel(bel);
 }
 
-bool Arch::checkBelAvail(BelId bel) const { return bel_info(bel).bound_cell == nullptr; }
+bool Arch::checkBelAvail(BelId bel) const
+{
+    return (!uarch || uarch->checkBelAvail(bel)) && (bel_info(bel).bound_cell == nullptr);
+}
 
 CellInfo *Arch::getBoundBelCell(BelId bel) const { return bel_info(bel).bound_cell; }
 
@@ -359,6 +367,8 @@ uint32_t Arch::getWireChecksum(WireId wire) const { return wire.index; }
 
 void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
 {
+    if (uarch)
+        uarch->notifyWireChange(wire, net);
     wire_info(wire).bound_net = net;
     net->wires[wire].pip = PipId();
     net->wires[wire].strength = strength;
@@ -371,16 +381,22 @@ void Arch::unbindWire(WireId wire)
 
     auto pip = net_wires.at(wire).pip;
     if (pip != PipId()) {
+        if (uarch)
+            uarch->notifyPipChange(pip, nullptr);
         pip_info(pip).bound_net = nullptr;
         refreshUiPip(pip);
     }
 
+    uarch->notifyWireChange(wire, nullptr);
     net_wires.erase(wire);
     wire_info(wire).bound_net = nullptr;
     refreshUiWire(wire);
 }
 
-bool Arch::checkWireAvail(WireId wire) const { return wire_info(wire).bound_net == nullptr; }
+bool Arch::checkWireAvail(WireId wire) const
+{
+    return (!uarch || uarch->checkWireAvail(wire)) && (wire_info(wire).bound_net == nullptr);
+}
 
 NetInfo *Arch::getBoundWireNet(WireId wire) const { return wire_info(wire).bound_net; }
 
@@ -413,6 +429,10 @@ uint32_t Arch::getPipChecksum(PipId pip) const { return pip.index; }
 void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
 {
     WireId wire = pip_info(pip).dstWire;
+    if (uarch) {
+        uarch->notifyPipChange(pip, net);
+        uarch->notifyWireChange(wire, net);
+    }
     pip_info(pip).bound_net = net;
     wire_info(wire).bound_net = net;
     net->wires[wire].pip = pip;
@@ -424,6 +444,10 @@ void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
 void Arch::unbindPip(PipId pip)
 {
     WireId wire = pip_info(pip).dstWire;
+    if (uarch) {
+        uarch->notifyPipChange(pip, nullptr);
+        uarch->notifyWireChange(wire, nullptr);
+    }
     wire_info(wire).bound_net->wires.erase(wire);
     pip_info(pip).bound_net = nullptr;
     wire_info(wire).bound_net = nullptr;
@@ -431,10 +455,15 @@ void Arch::unbindPip(PipId pip)
     refreshUiWire(wire);
 }
 
-bool Arch::checkPipAvail(PipId pip) const { return pip_info(pip).bound_net == nullptr; }
+bool Arch::checkPipAvail(PipId pip) const
+{
+    return (!uarch || uarch->checkPipAvail(pip)) && (pip_info(pip).bound_net == nullptr);
+}
 
 bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
 {
+    if (uarch && !uarch->checkPipAvailForNet(pip, net))
+        return false;
     NetInfo *bound_net = pip_info(pip).bound_net;
     return bound_net == nullptr || bound_net == net;
 }
@@ -488,6 +517,8 @@ const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return g
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
+    if (uarch)
+        return uarch->estimateDelay(src, dst);
     const WireInfo &s = wire_info(src);
     const WireInfo &d = wire_info(dst);
     int dx = abs(s.x - d.x);
@@ -497,8 +528,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
 
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    NPNR_UNUSED(src_pin);
-    NPNR_UNUSED(dst_pin);
+    if (uarch)
+        return uarch->predictDelay(src_bel, src_pin, dst_bel, dst_pin);
     auto driver_loc = getBelLocation(src_bel);
     auto sink_loc = getBelLocation(dst_bel);
 
@@ -511,6 +542,8 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
 
 ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
+    if (uarch)
+        return uarch->getRouteBoundingBox(src, dst);
     ArcBounds bb;
 
     int src_x = wire_info(src).x;
@@ -537,6 +570,8 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
+    if (uarch)
+        uarch->prePlace();
     std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
     if (placer == "heap") {
         bool have_iobuf_or_constr = false;
@@ -548,7 +583,7 @@ bool Arch::place()
             }
         }
         bool retVal;
-        if (!have_iobuf_or_constr) {
+        if (!have_iobuf_or_constr && !uarch) {
             log_warning("Unable to use HeAP due to a lack of IO buffers or constrained cells as anchors; reverting to "
                         "SA.\n");
             retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
@@ -557,11 +592,15 @@ bool Arch::place()
             cfg.ioBufTypes.insert(id("GENERIC_IOB"));
             retVal = placer_heap(getCtx(), cfg);
         }
+        if (uarch)
+            uarch->postPlace();
         getCtx()->settings[getCtx()->id("place")] = 1;
         archInfoToAttributes();
         return retVal;
     } else if (placer == "sa") {
         bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
+        if (uarch)
+            uarch->postPlace();
         getCtx()->settings[getCtx()->id("place")] = 1;
         archInfoToAttributes();
         return retVal;
@@ -572,6 +611,8 @@ bool Arch::place()
 
 bool Arch::route()
 {
+    if (uarch)
+        uarch->preRoute();
     std::string router = str_or_default(settings, id("router"), defaultRouter);
     bool result;
     if (router == "router1") {
@@ -582,6 +623,8 @@ bool Arch::route()
     } else {
         log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
     }
+    if (uarch)
+        uarch->postRoute();
     getCtx()->settings[getCtx()->id("route")] = 1;
     archInfoToAttributes();
     return result;
@@ -644,6 +687,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
 
 bool Arch::isBelLocationValid(BelId bel) const
 {
+    if (uarch)
+        return uarch->isBelLocationValid(bel);
     std::vector<const CellInfo *> cells;
     Loc loc = getBelLocation(bel);
     for (auto tbel : getBelsByTile(loc.x, loc.y)) {
@@ -671,6 +716,7 @@ const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
 void Arch::assignArchInfo()
 {
+    int index = 0;
     for (auto &cell : getCtx()->cells) {
         CellInfo *ci = cell.second.get();
         if (ci->type == id("GENERIC_SLICE")) {
@@ -684,6 +730,8 @@ void Arch::assignArchInfo()
         for (auto &p : ci->ports)
             if (!ci->bel_pins.count(p.first))
                 ci->bel_pins.emplace(p.first, std::vector<IdString>{p.first});
+        ci->flat_index = index;
+        ++index;
     }
 }
 
diff --git a/generic/arch.h b/generic/arch.h
index 885089ca9d..e96853f1de 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -23,10 +23,12 @@
 #include <map>
 
 #include "arch_api.h"
+#include "base_arch.h"
 #include "idstring.h"
 #include "idstringlist.h"
 #include "nextpnr_namespaces.h"
 #include "nextpnr_types.h"
+#include "viaduct_api.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -126,7 +128,7 @@ template <typename TId> struct linear_range
     iterator end() const { return iterator(size); }
 };
 
-struct ArchRanges
+struct ArchRanges : BaseArchRanges
 {
     using ArchArgsT = ArchArgs;
     // Bels
@@ -158,9 +160,10 @@ struct ArchRanges
     using BucketBelRangeT = std::vector<BelId>;
 };
 
-struct Arch : ArchAPI<ArchRanges>
+struct Arch : BaseArch<ArchRanges>
 {
     std::string chipName;
+    std::unique_ptr<ViaductAPI> uarch{};
 
     std::vector<WireInfo> wires;
     std::vector<PipInfo> pips;
@@ -325,6 +328,8 @@ struct Arch : ArchAPI<ArchRanges>
 
     std::vector<IdString> getCellTypes() const override
     {
+        if (uarch)
+            return uarch->getCellTypes();
         pool<IdString> cell_types;
         for (auto bel : bels) {
             cell_types.insert(bel.type);
@@ -339,9 +344,15 @@ struct Arch : ArchAPI<ArchRanges>
 
     BelBucketId getBelBucketByName(IdString bucket) const override { return bucket; }
 
-    BelBucketId getBelBucketForBel(BelId bel) const override { return getBelType(bel); }
+    BelBucketId getBelBucketForBel(BelId bel) const override
+    {
+        return uarch ? uarch->getBelBucketForBel(bel) : getBelType(bel);
+    }
 
-    BelBucketId getBelBucketForCellType(IdString cell_type) const override { return cell_type; }
+    BelBucketId getBelBucketForCellType(IdString cell_type) const override
+    {
+        return uarch ? uarch->getBelBucketForCellType(cell_type) : cell_type;
+    }
 
     std::vector<BelId> getBelsInBucket(BelBucketId bucket) const override
     {
@@ -366,19 +377,11 @@ struct Arch : ArchAPI<ArchRanges>
     // Get the TimingClockingInfo of a port
     TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
 
-    bool isValidBelForCellType(IdString cell_type, BelId bel) const override { return cell_type == getBelType(bel); }
-    bool isBelLocationValid(BelId bel) const override;
-
-    // TODO
-    CellInfo *getClusterRootCell(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
-    ArcBounds getClusterBounds(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
-    Loc getClusterOffset(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
-    bool isClusterStrict(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
-    bool getClusterPlacement(ClusterId cluster, BelId root_bel,
-                             std::vector<std::pair<CellInfo *, BelId>> &placement) const override
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
     {
-        NPNR_ASSERT_FALSE("unimplemented");
+        return uarch ? uarch->isValidBelForCellType(cell_type, bel) : cell_type == getBelType(bel);
     }
+    bool isBelLocationValid(BelId bel) const override;
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
diff --git a/generic/archdefs.h b/generic/archdefs.h
index 2d46c0a2d1..4e91ffd3ab 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -20,6 +20,7 @@
 #ifndef GENERIC_ARCHDEFS_H
 #define GENERIC_ARCHDEFS_H
 
+#include "base_clusterinfo.h"
 #include "hashlib.h"
 #include "idstringlist.h"
 
@@ -74,7 +75,7 @@ struct ArchNetInfo
 
 struct NetInfo;
 
-struct ArchCellInfo
+struct ArchCellInfo : BaseClusterInfo
 {
     // Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
     // value may share a tile (-1 = don't care, default if not set)
@@ -83,6 +84,8 @@ struct ArchCellInfo
     bool is_slice;
     // Only packing rule for slice type primitives is a single clock per tile
     const NetInfo *slice_clk;
+    // A flat index for cells; so viaduct uarches can have their own fast flat arrays of per-cell validity-related data
+    int flat_index;
     // Cell to bel pin mapping
     dict<IdString, std::vector<IdString>> bel_pins;
 };
diff --git a/generic/family.cmake b/generic/family.cmake
index e69de29bb2..cd4e3801e4 100644
--- a/generic/family.cmake
+++ b/generic/family.cmake
@@ -0,0 +1,7 @@
+set(VIADUCT_UARCHES "example")
+foreach(uarch ${VIADUCT_UARCHES})
+    aux_source_directory(${family}/viaduct/${uarch} UARCH_FILES)
+    foreach(target ${family_targets})
+        target_sources(${target} PRIVATE ${UARCH_FILES})
+    endforeach()
+endforeach(uarch)
diff --git a/generic/main.cc b/generic/main.cc
index 387df6c6ed..d08ae3819a 100644
--- a/generic/main.cc
+++ b/generic/main.cc
@@ -44,8 +44,10 @@ GenericCommandHandler::GenericCommandHandler(int argc, char **argv) : CommandHan
 
 po::options_description GenericCommandHandler::getArchOptions()
 {
+    std::string all_uarches = ViaductArch::list();
+    std::string uarch_help = stringf("viaduct micro-arch to use (available: %s)", all_uarches.c_str());
     po::options_description specific("Architecture specific options");
-    specific.add_options()("generic", "set device type to generic");
+    specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
     specific.add_options()("no-iobs", "disable automatic IO buffer insertion");
     return specific;
 }
@@ -63,6 +65,17 @@ std::unique_ptr<Context> GenericCommandHandler::createContext(dict<std::string,
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     if (vm.count("no-iobs"))
         ctx->settings[ctx->id("disable_iobs")] = Property::State::S1;
+    if (vm.count("uarch")) {
+        std::string uarch_name = vm["uarch"].as<std::string>();
+        dict<std::string, std::string> args; // TODO
+        auto uarch = ViaductArch::create(uarch_name, args);
+        if (!uarch) {
+            std::string all_uarches = ViaductArch::list();
+            log_error("Unknown viaduct uarch '%s'; available options: '%s'\n", uarch_name.c_str(), all_uarches.c_str());
+        }
+        ctx->uarch = std::move(uarch);
+        ctx->uarch->init(ctx.get());
+    }
     return ctx;
 }
 
diff --git a/generic/pack.cc b/generic/pack.cc
index 32dae5538a..291a528dae 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -276,12 +276,16 @@ bool Arch::pack()
     Context *ctx = getCtx();
     try {
         log_break();
-        pack_constants(ctx);
-        pack_io(ctx);
-        pack_lut_lutffs(ctx);
-        pack_nonlut_ffs(ctx);
-        ctx->settings[ctx->id("pack")] = 1;
+        if (uarch) {
+            uarch->pack();
+        } else {
+            pack_constants(ctx);
+            pack_io(ctx);
+            pack_lut_lutffs(ctx);
+            pack_nonlut_ffs(ctx);
+        }
         ctx->assignArchInfo();
+        ctx->settings[ctx->id("pack")] = 1;
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;
     } catch (log_execution_error_exception) {
diff --git a/generic/viaduct/example/.gitignore b/generic/viaduct/example/.gitignore
new file mode 100644
index 0000000000..a6c57f5fb2
--- /dev/null
+++ b/generic/viaduct/example/.gitignore
@@ -0,0 +1 @@
+*.json
diff --git a/generic/viaduct/example/constids.inc b/generic/viaduct/example/constids.inc
new file mode 100644
index 0000000000..b40d5be8a0
--- /dev/null
+++ b/generic/viaduct/example/constids.inc
@@ -0,0 +1,14 @@
+X(LUT4)
+X(DFF)
+X(CLK)
+X(D)
+X(F)
+X(Q)
+X(INBUF)
+X(OUTBUF)
+X(I)
+X(EN)
+X(O)
+X(IOB)
+X(PAD)
+X(INIT)
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
new file mode 100644
index 0000000000..3d1c201cbf
--- /dev/null
+++ b/generic/viaduct/example/example.cc
@@ -0,0 +1,306 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+#include "viaduct_api.h"
+#include "viaduct_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define VIADUCT_CONSTIDS "viaduct/example/constids.inc"
+#include "viaduct_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct ExampleImpl : ViaductAPI
+{
+    ~ExampleImpl(){};
+    void init(Context *ctx) override
+    {
+        init_uarch_constids(ctx);
+        ViaductAPI::init(ctx);
+        h.init(ctx);
+        init_wires();
+        init_bels();
+        init_pips();
+    }
+
+    void pack() override
+    {
+        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_INBUF, id_PAD),
+                CellTypePort(id_OUTBUF, id_PAD),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+        // Replace constants with LUTs
+        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
+        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
+        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+        // Constrain directly connected LUTs and FFs together to use dedicated resources
+        int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        log_info("Constrained %d LUTFF pairs.\n", lutffs);
+    }
+
+    void prePlace() override { assign_cell_info(); }
+
+    bool isBelLocationValid(BelId bel) const override
+    {
+        Loc l = ctx->getBelLocation(bel);
+        if (is_io(l.x, l.y)) {
+            return true;
+        } else {
+            return slice_valid(l.x, l.y, l.z / 2);
+        }
+    }
+
+  private:
+    ViaductHelpers h;
+    // Configuration
+    // Grid size including IOBs at edges
+    const int X = 32, Y = 32;
+    // SLICEs per tile
+    const int N = 8;
+    // LUT input count
+    const int K = 4;
+    // Number of local wires
+    const int Wl = N * (K + 1) + 8;
+    // 1/Fc for bel input wire pips; local wire pips and neighbour pips
+    const int Si = 4, Sq = 4, Sl = 8;
+
+    // For fast wire lookups
+    struct TileWires
+    {
+        std::vector<WireId> clk, q, f, d, i;
+        std::vector<WireId> l;
+        std::vector<WireId> pad;
+    };
+
+    std::vector<std::vector<TileWires>> wires_by_tile;
+
+    // Create wires to attach to bels and pips
+    void init_wires()
+    {
+        log_info("Creating wires...\n");
+        wires_by_tile.resize(Y);
+        for (int y = 0; y < Y; y++) {
+            auto &row_wires = wires_by_tile.at(y);
+            row_wires.resize(X);
+            for (int x = 0; x < X; x++) {
+                auto &w = row_wires.at(x);
+                for (int z = 0; z < N; z++) {
+                    // Clock input
+                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y));
+                    // FF input
+                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y));
+                    // FF and LUT outputs
+                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y));
+                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y));
+                    // LUT inputs
+                    for (int i = 0; i < K; i++)
+                        w.i.push_back(
+                                ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y));
+                }
+                // Local wires
+                for (int l = 0; l < Wl; l++)
+                    w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("LOCAL%d", l))), ctx->id("LOCAL"), x, y));
+                // Pad wires for IO
+                if (is_io(x, y) && x != y)
+                    for (int z = 0; z < 2; z++)
+                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y));
+            }
+        }
+    }
+    bool is_io(int x, int y) const
+    {
+        // IO are on the edges of the device
+        return (x == 0) || (x == (X - 1)) || (y == 0) || (y == (Y - 1));
+    }
+    // Create IO bels in an IO tile
+    void add_io_bels(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        for (int z = 0; z < 2; z++) {
+            BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false);
+            ctx->addBelInout(b, id_PAD, w.pad.at(z));
+            ctx->addBelInput(b, id_I, w.i.at(z * K + 0));
+            ctx->addBelInput(b, id_EN, w.i.at(z * K + 1));
+            ctx->addBelOutput(b, id_O, w.q.at(z));
+        }
+    }
+    PipId add_pip(Loc loc, WireId src, WireId dst, delay_t delay = 0.05)
+    {
+        IdStringList name = IdStringList::concat(ctx->getWireName(dst), ctx->getWireName(src));
+        return ctx->addPip(name, ctx->id("PIP"), src, dst, delay, loc);
+    }
+    // Create LUT and FF bels in a logic tile
+    void add_slice_bels(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        for (int z = 0; z < N; z++) {
+            // Create LUT bel
+            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false,
+                                    false);
+            for (int k = 0; k < K; k++)
+                ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.i.at(z * K + k));
+            ctx->addBelOutput(lut, id_F, w.f.at(z));
+            // FF data can come from LUT output or LUT I3
+            add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
+            add_pip(Loc(x, y, 0), w.i.at(z * K + (K - 1)), w.d.at(z));
+            // Create DFF bel
+            BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1),
+                                    false, false);
+            ctx->addBelInput(dff, id_CLK, w.clk.at(z));
+            ctx->addBelInput(dff, id_D, w.d.at(z));
+            ctx->addBelOutput(dff, id_Q, w.q.at(z));
+        }
+    }
+    // Create bels according to tile type
+    void init_bels()
+    {
+        log_info("Creating bels...\n");
+        for (int y = 0; y < Y; y++) {
+            for (int x = 0; x < X; x++) {
+                if (is_io(x, y)) {
+                    if (x == y)
+                        continue; // don't put IO in corners
+                    add_io_bels(x, y);
+                } else {
+                    add_slice_bels(x, y);
+                }
+            }
+        }
+    }
+
+    // Create PIPs inside a tile; following an example synthetic routing pattern
+    void add_tile_pips(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        Loc loc(x, y, 0);
+        auto create_input_pips = [&](WireId dst, int offset, int skip) {
+            for (int i = (offset % skip); i < Wl; i += skip)
+                add_pip(loc, w.l.at(i), dst, 0.05);
+        };
+        for (int z = 0; z < N; z++) {
+            create_input_pips(w.clk.at(z), 0, Si);
+            for (int k = 0; k < K; k++)
+                create_input_pips(w.i.at(z * K + k), k, Si);
+        }
+        auto create_output_pips = [&](WireId dst, int offset, int skip) {
+            for (int z = (offset % skip); z < N; z += skip) {
+                add_pip(loc, w.f.at(z), dst, 0.05);
+                add_pip(loc, w.q.at(z), dst, 0.05);
+            }
+        };
+        auto create_neighbour_pips = [&](WireId dst, int nx, int ny, int offset, int skip) {
+            if (nx < 0 || nx >= X)
+                return;
+            if (ny < 0 || ny >= Y)
+                return;
+            auto &nw = wires_by_tile.at(ny).at(nx);
+            for (int i = (offset % skip); i < Wl; i += skip)
+                add_pip(loc, dst, nw.l.at(i), 0.1);
+        };
+        for (int i = 0; i < Wl; i++) {
+            WireId dst = w.l.at(i);
+            create_output_pips(dst, i % Sq, Sq);
+            create_neighbour_pips(dst, x - 1, y - 1, (i + 1) % Sl, Sl);
+            create_neighbour_pips(dst, x - 1, y, (i + 2) % Sl, Sl);
+            create_neighbour_pips(dst, x - 1, y + 1, (i + 3) % Sl, Sl);
+            create_neighbour_pips(dst, x, y - 1, (i + 4) % Sl, Sl);
+            create_neighbour_pips(dst, x, y + 1, (i + 5) % Sl, Sl);
+            create_neighbour_pips(dst, x + 1, y - 1, (i + 6) % Sl, Sl);
+            create_neighbour_pips(dst, x + 1, y, (i + 7) % Sl, Sl);
+            create_neighbour_pips(dst, x + 1, y + 1, (i + 8) % Sl, Sl);
+        }
+    }
+    void init_pips()
+    {
+        log_info("Creating pips...\n");
+        for (int y = 0; y < Y; y++)
+            for (int x = 0; x < X; x++)
+                add_tile_pips(x, y);
+    }
+    // Validity checking
+    struct ExampleCellInfo
+    {
+        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+        bool lut_i3_used = false;
+    };
+    std::vector<ExampleCellInfo> fast_cell_info;
+    void assign_cell_info()
+    {
+        fast_cell_info.resize(ctx->cells.size());
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto &fc = fast_cell_info.at(ci->flat_index);
+            if (ci->type == id_LUT4) {
+                fc.lut_f = get_net_or_empty(ci, id_F);
+                fc.lut_i3_used = (get_net_or_empty(ci, ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+            } else if (ci->type == id_DFF) {
+                fc.ff_d = get_net_or_empty(ci, id_D);
+            }
+        }
+    }
+    bool slice_valid(int x, int y, int z) const
+    {
+        const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+        const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+        if (!lut || !ff)
+            return true; // always valid if only LUT or FF used
+        const auto &lut_data = fast_cell_info.at(lut->flat_index);
+        const auto &ff_data = fast_cell_info.at(ff->flat_index);
+        // In our example arch; the FF D can either be driven from LUT F or LUT I3
+        // so either; FF D must equal LUT F or LUT I3 must be unused
+        if (ff_data.ff_d == lut_data.lut_f)
+            return true;
+        if (lut_data.lut_i3_used)
+            return false;
+        return true;
+    }
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override
+    {
+        if (cell_type.in(id_INBUF, id_OUTBUF))
+            return id_IOB;
+        return cell_type;
+    }
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        IdString bel_type = ctx->getBelType(bel);
+        if (bel_type == id_IOB)
+            return cell_type.in(id_INBUF, id_OUTBUF);
+        else
+            return (bel_type == cell_type);
+    }
+};
+
+struct ExampleArch : ViaductArch
+{
+    ExampleArch() : ViaductArch("example"){};
+    std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<ExampleImpl>();
+    }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/example/example_map.v b/generic/viaduct/example/example_map.v
new file mode 100644
index 0000000000..f701f0ed7a
--- /dev/null
+++ b/generic/viaduct/example/example_map.v
@@ -0,0 +1,12 @@
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+	input [WIDTH-1:0] A;
+	output Y;
+
+	localparam rep = 1<<(4-WIDTH);
+
+	LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .F(Y));
+endmodule
+
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
diff --git a/generic/viaduct/example/example_prims.v b/generic/viaduct/example/example_prims.v
new file mode 100644
index 0000000000..d2813129b4
--- /dev/null
+++ b/generic/viaduct/example/example_prims.v
@@ -0,0 +1,35 @@
+module LUT4 #(
+    parameter [15:0] INIT = 0
+) (
+    input [3:0] I,
+    output F
+);
+    wire [7:0] s3 = I[3] ?     INIT[15:8] :     INIT[7:0];
+    wire [3:0] s2 = I[2] ?       s3[ 7:4] :       s3[3:0];
+    wire [1:0] s1 = I[1] ?       s2[ 3:2] :       s2[1:0];
+    assign F = I[0] ? s1[1] : s1[0];
+endmodule
+
+module DFF (
+    input CLK, D,
+    output reg Q
+);
+    initial Q = 1'b0;
+    always @(posedge CLK)
+        Q <= D;
+endmodule
+
+module INBUF (
+    input PAD,
+    output O,
+);
+    assign O = PAD;
+endmodule
+
+module OUTBUF (
+    output PAD,
+    input I,
+);
+    assign PAD = I;
+endmodule
+
diff --git a/generic/viaduct/example/synth_viaduct_example.tcl b/generic/viaduct/example/synth_viaduct_example.tcl
new file mode 100644
index 0000000000..a9d18f5612
--- /dev/null
+++ b/generic/viaduct/example/synth_viaduct_example.tcl
@@ -0,0 +1,24 @@
+# Usage
+# tcl synth_viaduct_example.tcl {out.json}
+
+yosys read_verilog -lib [file dirname [file normalize $argv0]]/example_prims.v
+yosys hierarchy -check
+yosys proc
+yosys flatten
+yosys tribuf -logic
+yosys deminout
+yosys synth -run coarse
+yosys memory_map
+yosys opt -full
+yosys iopadmap -bits -inpad INBUF O:PAD -outpad OUTBUF I:PAD
+yosys techmap -map +/techmap.v
+yosys opt -fast
+yosys dfflegalize -cell \$_DFF_P_ 0
+yosys abc -lut 4 -dress
+yosys clean
+yosys techmap -map [file dirname [file normalize $argv0]]/example_map.v
+yosys clean
+yosys hierarchy -check
+yosys stat
+
+if {$argc > 0} { yosys write_json [lindex $argv 0] }
diff --git a/generic/viaduct/example/viaduct_example.sh b/generic/viaduct/example/viaduct_example.sh
new file mode 100755
index 0000000000..0842df200b
--- /dev/null
+++ b/generic/viaduct/example/viaduct_example.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -ex
+# Run synthesis
+yosys -p "tcl synth_viaduct_example.tcl blinky.json" ../../examples/blinky.v
+# Run PnR
+${NEXTPNR:-../../../build/nextpnr-generic} --uarch example --json blinky.json
diff --git a/generic/viaduct_api.cc b/generic/viaduct_api.cc
new file mode 100644
index 0000000000..8a7b631395
--- /dev/null
+++ b/generic/viaduct_api.cc
@@ -0,0 +1,118 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "viaduct_api.h"
+#include "nextpnr.h"
+
+// Default implementations for Viaduct API hooks
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void ViaductAPI::init(Context *ctx) { this->ctx = ctx; }
+
+std::vector<IdString> ViaductAPI::getCellTypes() const
+{
+    pool<IdString> cell_types;
+    for (auto bel : ctx->bels) {
+        cell_types.insert(bel.type);
+    }
+
+    return std::vector<IdString>{cell_types.begin(), cell_types.end()};
+}
+BelBucketId ViaductAPI::getBelBucketForBel(BelId bel) const { return ctx->getBelType(bel); }
+BelBucketId ViaductAPI::getBelBucketForCellType(IdString cell_type) const { return cell_type; }
+bool ViaductAPI::isValidBelForCellType(IdString cell_type, BelId bel) const
+{
+    return ctx->getBelType(bel) == cell_type;
+}
+
+delay_t ViaductAPI::estimateDelay(WireId src, WireId dst) const
+{
+    const WireInfo &s = ctx->wire_info(src);
+    const WireInfo &d = ctx->wire_info(dst);
+    int dx = abs(s.x - d.x);
+    int dy = abs(s.y - d.y);
+    return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
+}
+delay_t ViaductAPI::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
+{
+    NPNR_UNUSED(src_pin);
+    NPNR_UNUSED(dst_pin);
+    auto driver_loc = ctx->getBelLocation(src_bel);
+    auto sink_loc = ctx->getBelLocation(dst_bel);
+
+    int dx = abs(sink_loc.x - driver_loc.x);
+    int dy = abs(sink_loc.y - driver_loc.y);
+    return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
+}
+ArcBounds ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
+{
+    ArcBounds bb;
+    int src_x = ctx->wire_info(src).x;
+    int src_y = ctx->wire_info(src).y;
+    int dst_x = ctx->wire_info(dst).x;
+    int dst_y = ctx->wire_info(dst).y;
+
+    bb.x0 = src_x;
+    bb.y0 = src_y;
+    bb.x1 = src_x;
+    bb.y1 = src_y;
+
+    auto extend = [&](int x, int y) {
+        bb.x0 = std::min(bb.x0, x);
+        bb.x1 = std::max(bb.x1, x);
+        bb.y0 = std::min(bb.y0, y);
+        bb.y1 = std::max(bb.y1, y);
+    };
+    extend(dst_x, dst_y);
+    return bb;
+}
+
+ViaductArch *ViaductArch::list_head;
+ViaductArch::ViaductArch(const std::string &name) : name(name)
+{
+    list_next = ViaductArch::list_head;
+    ViaductArch::list_head = this;
+}
+std::string ViaductArch::list()
+{
+    std::string result;
+    ViaductArch *cursor = ViaductArch::list_head;
+    while (cursor) {
+        if (!result.empty())
+            result += ", ";
+        result += cursor->name;
+        cursor = cursor->list_next;
+    }
+    return result;
+}
+std::unique_ptr<ViaductAPI> ViaductArch::create(const std::string &name, const dict<std::string, std::string> &args)
+{
+    ViaductArch *cursor = ViaductArch::list_head;
+    while (cursor) {
+        if (cursor->name != name) {
+            cursor = cursor->list_next;
+            continue;
+        }
+        return cursor->create(args);
+    }
+    return {};
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
new file mode 100644
index 0000000000..bc9b4311ce
--- /dev/null
+++ b/generic/viaduct_api.h
@@ -0,0 +1,114 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_API_H
+#define VIADUCT_API_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Viaduct -- a series of small arches
+
+Viaduct is a framework that provides an 'inbetween' step between nextpnr-generic
+using Python bindings and a full-custom arch.
+
+It allows an arch to programmatically build a set of bels (placement locations)
+and a routing graph in-memory at startup; and then hook into nextpnr's flow
+and validity checking rules at runtime with custom C++ code.
+
+To create a Viaduct 'uarch', the following are required:
+ - an implementation of ViaductAPI. At a minimum; you will need to use ctx->addBel, ctx->addWire and ctx->addPip to
+create the graph of placement and routing resources in-memory. Also implement any placement validity checking required -
+like rules for how LUTs and FFs can be placed together in a SLICE.
+ - an instance of a struct deriving from ViaductArch - this is how the uarch is discovered. Override create(args) to
+create an instance of your ViaductAPI implementation.
+ - these should be within C++ files in a new subfolder of 'viaduct'. Add the name of this subfolder to the list of
+VIADUCT_UARCHES in family.cmake if building in-tree.
+
+For an example of how these pieces fit together; see 'viaduct/example' which implements a small synthetic architecture
+using this framework.
+
+*/
+
+struct Context;
+
+struct ViaductAPI
+{
+    virtual void init(Context *ctx);
+    Context *ctx;
+
+    // --- Bel functions ---
+    // Called when a bel is placed/unplaced (with cell=nullptr for a unbind)
+    virtual void notifyBelChange(BelId bel, CellInfo *cell) {}
+    // This only needs to return false if a bel is disabled for a microarch-specific reason and not just because it's
+    // bound (which the base generic will deal with)
+    virtual bool checkBelAvail(BelId bel) const { return true; }
+    // Mirror the ArchAPI functions - see archapi.md
+    virtual std::vector<IdString> getCellTypes() const;
+    virtual BelBucketId getBelBucketForBel(BelId bel) const;
+    virtual BelBucketId getBelBucketForCellType(IdString cell_type) const;
+    virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const;
+    virtual bool isBelLocationValid(BelId bel) const { return true; }
+
+    // --- Wire and pip functions ---
+    // Called when a wire/pip is placed/unplaced (with net=nullptr for a unbind)
+    virtual void notifyWireChange(WireId wire, NetInfo *net) {}
+    virtual void notifyPipChange(PipId pip, NetInfo *net) {}
+    // These only need to return false if a wire/pip is disabled for a microarch-specific reason and not just because
+    // it's bound (which the base arch will deal with)
+    virtual bool checkWireAvail(WireId wire) const { return true; }
+    virtual bool checkPipAvail(PipId pip) const { return true; }
+    virtual bool checkPipAvailForNet(PipId pip, NetInfo *net) const { return checkPipAvail(pip); };
+
+    // --- Route lookahead ---
+    virtual delay_t estimateDelay(WireId src, WireId dst) const;
+    virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const;
+    virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
+
+    // --- Flow hooks ---
+    virtual void pack(){}; // replaces the pack function
+    // Called before and after main placement and routing
+    virtual void prePlace(){};
+    virtual void postPlace(){};
+    virtual void preRoute(){};
+    virtual void postRoute(){};
+
+    virtual ~ViaductAPI(){};
+};
+
+struct ViaductArch
+{
+    static ViaductArch *list_head;
+    ViaductArch *list_next = nullptr;
+
+    std::string name;
+    ViaductArch(const std::string &name);
+    ~ViaductArch(){};
+    virtual std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args) = 0;
+
+    static std::string list();
+    static std::unique_ptr<ViaductAPI> create(const std::string &name, const dict<std::string, std::string> &args);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct_constids.h b/generic/viaduct_constids.h
new file mode 100644
index 0000000000..82180953c5
--- /dev/null
+++ b/generic/viaduct_constids.h
@@ -0,0 +1,74 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_CONSTIDS_H
+#define VIADUCT_CONSTIDS_H
+
+/*
+This enables use of 'constids' similar to a 'true' nextpnr arch in a viaduct uarch.
+To use:
+    - create a 'constids.inc' file in your uarch folder containing one ID per line; inside X( )
+    - set the VIADUCT_CONSTIDS macro to the path to this file relative to the generic arch base
+    - in your main file; also define GEN_INIT_CONSTIDS to create init_uarch_constids(Context*) which you should call in
+init
+    - include this file
+*/
+
+#include "nextpnr_namespaces.h"
+
+#ifdef VIADUCT_MAIN
+#include "idstring.h"
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+#ifndef Q_MOC_RUN
+enum ConstIds
+{
+    ID_NONE
+#define X(t) , ID_##t
+#include VIADUCT_CONSTIDS
+#undef X
+    ,
+};
+
+#define X(t) static constexpr auto id_##t = IdString(ID_##t);
+#include VIADUCT_CONSTIDS
+#undef X
+#endif
+
+#ifdef GEN_INIT_CONSTIDS
+
+void init_uarch_constids(Context *ctx)
+{
+#define X(t) IdString::initialize_add(ctx, #t, ID_##t);
+
+#include VIADUCT_CONSTIDS
+
+#undef X
+}
+
+#endif
+
+} // namespace
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
new file mode 100644
index 0000000000..36bdd6bec1
--- /dev/null
+++ b/generic/viaduct_helpers.cc
@@ -0,0 +1,163 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "viaduct_helpers.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void ViaductHelpers::resize_ids(int x, int y)
+{
+    NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000);
+    while (int(x_ids.size()) <= x) {
+        IdString next = ctx->id(stringf("X%d", int(x_ids.size())));
+        x_ids.push_back(next);
+    }
+    while (int(y_ids.size()) <= y) {
+        IdString next = ctx->id(stringf("Y%d", int(y_ids.size())));
+        y_ids.push_back(next);
+    }
+}
+
+IdStringList ViaductHelpers::xy_id(int x, int y, IdString base)
+{
+    resize_ids(x, y);
+    std::array<IdString, 3> result{x_ids.at(x), y_ids.at(y), base};
+    return IdStringList(result);
+}
+
+IdStringList ViaductHelpers::xy_id(int x, int y, IdStringList base)
+{
+    resize_ids(x, y);
+    std::array<IdString, 2> prefix{x_ids.at(x), y_ids.at(y)};
+    return IdStringList::concat(IdStringList(prefix), base);
+}
+
+void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
+{
+    std::vector<IdString> to_remove;
+    for (auto &cell : ctx->cells) {
+        auto &ci = *cell.second;
+        if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
+            continue;
+        NetInfo *i = get_net_or_empty(&ci, ctx->id("I"));
+        if (i && i->driver.cell) {
+            if (!top_ports.count(CellTypePort(i->driver)))
+                log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
+                          ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+        }
+        NetInfo *o = get_net_or_empty(&ci, ctx->id("O"));
+        if (o) {
+            for (auto &usr : o->users) {
+                if (!top_ports.count(CellTypePort(usr)))
+                    log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
+                              ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
+            }
+        }
+        disconnect_port(ctx, &ci, ctx->id("I"));
+        disconnect_port(ctx, &ci, ctx->id("O"));
+        to_remove.push_back(ci.name);
+    }
+    for (IdString cell_name : to_remove)
+        ctx->cells.erase(cell_name);
+}
+
+int ViaductHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports,
+                                         int delta_z)
+{
+    int constrained = 0;
+    for (auto &cell : ctx->cells) {
+        auto &ci = *cell.second;
+        if (ci.cluster != ClusterId())
+            continue; // don't constrain already-constrained cells
+        bool done = false;
+        for (auto &port : ci.ports) {
+            // look for starting source ports
+            if (port.second.type != PORT_OUT || !port.second.net)
+                continue;
+            if (!src_ports.count(CellTypePort(ci.type, port.first)))
+                continue;
+            for (auto &usr : port.second.net->users) {
+                if (!sink_ports.count(CellTypePort(usr)))
+                    continue;
+                if (usr.cell->cluster != ClusterId())
+                    continue;
+                // Add the constraint
+                ci.cluster = ci.name;
+                ci.constr_abs_z = false;
+                ci.constr_children.push_back(usr.cell);
+                usr.cell->cluster = ci.name;
+                usr.cell->constr_x = 0;
+                usr.cell->constr_y = 0;
+                usr.cell->constr_z = delta_z;
+                usr.cell->constr_abs_z = false;
+                ++constrained;
+                done = true;
+                break;
+            }
+            if (done)
+                break;
+        }
+    }
+    return constrained;
+}
+
+void ViaductHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+                                       const dict<IdString, Property> &vcc_params,
+                                       const dict<IdString, Property> &gnd_params)
+{
+    CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), vcc_driver.cell_type);
+    vcc_drv->addOutput(vcc_driver.port);
+    for (auto &p : vcc_params)
+        vcc_drv->params[p.first] = p.second;
+
+    CellInfo *gnd_drv = ctx->createCell(ctx->id("$PACKER_GND_DRV"), gnd_driver.cell_type);
+    gnd_drv->addOutput(gnd_driver.port);
+    for (auto &p : gnd_params)
+        gnd_drv->params[p.first] = p.second;
+
+    NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC"));
+    NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND"));
+
+    std::vector<IdString> trim_cells;
+    std::vector<IdString> trim_nets;
+    for (auto &net : ctx->nets) {
+        auto &ni = *net.second;
+        if (!ni.driver.cell)
+            continue;
+        if (ni.driver.cell->type != ctx->id("GND") && ni.driver.cell->type != ctx->id("VCC"))
+            continue;
+        NetInfo *replace = (ni.driver.cell->type == ctx->id("VCC")) ? vcc_net : gnd_net;
+        for (auto &usr : ni.users) {
+            usr.cell->ports.at(usr.port).net = replace;
+            replace->users.push_back(usr);
+        }
+        trim_cells.push_back(ni.driver.cell->name);
+        trim_nets.push_back(ni.name);
+    }
+    for (IdString cell_name : trim_cells)
+        ctx->cells.erase(cell_name);
+    for (IdString net_name : trim_nets)
+        ctx->nets.erase(net_name);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct_helpers.h b/generic/viaduct_helpers.h
new file mode 100644
index 0000000000..8cba84115e
--- /dev/null
+++ b/generic/viaduct_helpers.h
@@ -0,0 +1,82 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_HELPERS_H
+#define VIADUCT_HELPERS_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Viaduct -- a series of small arches
+
+See viaduct_api.h for more background.
+
+viaduct_helpers provides some features for building up arches using the viaduct API
+*/
+
+// Used to configure various generic pack functions
+struct CellTypePort
+{
+    CellTypePort() : cell_type(), port(){};
+    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port){};
+    explicit CellTypePort(const PortRef &net_port)
+            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port){};
+    inline bool operator==(const CellTypePort &other) const
+    {
+        return cell_type == other.cell_type && port == other.port;
+    }
+    inline bool operator!=(const CellTypePort &other) const
+    {
+        return cell_type != other.cell_type || port != other.port;
+    }
+    inline unsigned hash() const { return mkhash(cell_type.hash(), port.hash()); }
+    IdString cell_type, port;
+};
+
+struct ViaductHelpers
+{
+    ViaductHelpers(){};
+    Context *ctx;
+    void init(Context *ctx) { this->ctx = ctx; }
+    // IdStringList components for x and y locations
+    std::vector<IdString> x_ids, y_ids;
+    void resize_ids(int x, int y);
+    // Get an IdStringList for a hierarchical ID
+    // Because this uses an IdStringList with seperate X and Y components; this will be much more efficient than
+    // creating unique strings for each object in each X and Y position
+    IdStringList xy_id(int x, int y, IdString base);
+    IdStringList xy_id(int x, int y, IdStringList base);
+    // Common packing functions
+    // Remove nextpnr-inserted IO buffers; where IO buffer insertion is done in synthesis
+    // expects a set of top-level port types
+    void remove_nextpnr_iobs(const pool<CellTypePort> &top_ports);
+    // Constrain cells with certain port connection patterns together with a fixed z-offset
+    int constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports, int delta_z);
+    // Replace constants with given driving cells
+    void replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+                           const dict<IdString, Property> &vcc_params = {},
+                           const dict<IdString, Property> &gnd_params = {});
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif

From ae7c2261befd961a06a7422b8ae79b54c89e03bc Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 11 Jan 2022 15:28:13 +0100
Subject: [PATCH 041/712] Switched integer pair hashing function from DJB2 to
 Cantor

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 common/hashlib.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/common/hashlib.h b/common/hashlib.h
index b71f012984..70de8c919e 100644
--- a/common/hashlib.h
+++ b/common/hashlib.h
@@ -26,8 +26,11 @@ NEXTPNR_NAMESPACE_BEGIN
 const int hashtable_size_trigger = 2;
 const int hashtable_size_factor = 3;
 
-// The XOR version of DJB2
-inline unsigned int mkhash(unsigned int a, unsigned int b) { return ((a << 5) + a) ^ b; }
+// Cantor pairing function for two non-negative integers
+// https://en.wikipedia.org/wiki/Pairing_function
+inline unsigned int mkhash(unsigned int a, unsigned int b) {
+    return (a*a + 3*a + 2*a*b + b + b*b) / 2;
+}
 
 // traditionally 5381 is used as starting value for the djb2 hash
 const unsigned int mkhash_init = 5381;

From b5fc788153bd011a4476946af5ccebde05fd2ad2 Mon Sep 17 00:00:00 2001
From: Olivier Galibert <galibert@pobox.com>
Date: Tue, 18 Jan 2022 15:12:45 +0100
Subject: [PATCH 042/712] Sync with the current state of mistral

---
 .github/workflows/mistral_ci.yml |   2 +-
 mistral/arch.h                   |   1 -
 mistral/base_bitstream.cc        | 100 ------------------------------
 mistral/bitstream.cc             | 103 ++-----------------------------
 4 files changed, 5 insertions(+), 201 deletions(-)
 delete mode 100644 mistral/base_bitstream.cc

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 64300d78f4..0da633e68d 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: e039b595529ab573d9cb01c64ef927f9d81d63ce
+        MISTRAL_REVISION: db29e403bede4d514fcf83948db9d4c05df07e96
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/arch.h b/mistral/arch.h
index 471b5251ee..9c38d5d2c3 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -562,7 +562,6 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
 
-    void init_base_bitstream(); // base_bitstream.cc
     void build_bitstream();     // bitstream.cc
 };
 
diff --git a/mistral/base_bitstream.cc b/mistral/base_bitstream.cc
deleted file mode 100644
index 9fa74fb92b..0000000000
--- a/mistral/base_bitstream.cc
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace {
-// Device-specific default config for the sx120f die
-void default_sx120f(CycloneV *cv)
-{
-    // Default PMA config?
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::TRISTATE);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::TRISTATE);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::DOWN);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::UP);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
-    cv->bmux_b_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FPLL_DRV_EN, 0, 0);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::HCLK_TOP_OUT_DRIVER, 0, CycloneV::TRISTATE);
-    // Default PLL config
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0_PRECOMP, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1_PRECOMP, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_BG_KICKSTART, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_VBGMON_POWERDOWN, 0, 1);
-    // Default TERM config
-    cv->bmux_b_set(CycloneV::TERM, CycloneV::xy2pos(89, 34), CycloneV::INTOSC_2_EN, 0, 0);
-
-    // TODO: what if these pins are used? where do these come from
-    for (int z = 0; z < 4; z++) {
-        cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 43), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
-        cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 66), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
-    }
-    for (int y : {38, 44, 51, 58, 65, 73, 79}) {
-        // TODO: Why only these upper DQS? is there a pattern?
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_2X_CLK_DQS_INV, 0, 1);
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_ACLR_LFIFO_EN, 0, 1);
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_LFIFO_BYPASS, 0, 0);
-    }
-
-    // Discover these mux values using
-    //   grep 'i [_A-Z0-9.]* 1' empty.bt
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 12), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 13), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 34), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 35), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 37), 31), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 40), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 46), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 47), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 53), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 54), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 73), 68), true);
-
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 18), 66), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 20), 8), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 27), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 28), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 59), 66), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 61), 8), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 68), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 69), 43), true);
-
-    for (int z = 10; z <= 45; z++)
-        cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(51, 80), z), true);
-}
-} // namespace
-
-void Arch::init_base_bitstream()
-{
-    switch (cyclonev->current_model()->variant.die.type) {
-    case CycloneV::SX120F:
-        default_sx120f(cyclonev);
-        break;
-    default:
-        log_error("FIXME: die type %s currently unsupported for bitgen.\n",
-                  cyclonev->current_model()->variant.die.name);
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index eed508b38b..b432be037d 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -29,108 +29,13 @@ struct MistralBitgen
     Context *ctx;
     CycloneV *cv;
 
-    void init()
+    void options()
     {
-        ctx->init_base_bitstream();
-        // Default options
-        cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
-        if (!ctx->setting<bool>("compress_rbf", false))
+        if (!ctx->setting<bool>("compress_rbf", false)) {
             cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
-        cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
-        cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
-        cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
-        cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
-        cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
-        cv->opt_b_set(CycloneV::NCEO_DIS, true);
-        cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
-        cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
-        if (!ctx->setting<bool>("compress_rbf", false))
             cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
-        else
+        } else
             cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
-        cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
-        cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
-        cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
-        // Default inversion
-        write_default_inv();
-    }
-
-    void write_default_inv()
-    {
-        // Some PNODEs are inverted by default. Set them up here.
-        for (const auto &pn2r : cv->get_all_p2r()) {
-            const auto &pn = pn2r.first;
-            auto pt = CycloneV::pn2pt(pn);
-            auto pi = CycloneV::pn2pi(pn);
-
-            switch (CycloneV::pn2bt(pn)) {
-            case CycloneV::HMC: {
-                // HMC OE are inverted to set OE=0, i.e. unused pins floating
-                // TODO: handle the case when we are using the HMC or HMC bypass
-                std::string name(CycloneV::port_type_names[pt]);
-                if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
-                    continue;
-                cv->inv_set(pn2r.second, true);
-                break;
-            };
-            // HPS IO - TODO: what about when we actually support the HPS primitives?
-            case CycloneV::HPS_BOOT: {
-                switch (pt) {
-                case CycloneV::CSEL_EN:
-                case CycloneV::BSEL_EN:
-                case CycloneV::BOOT_FROM_FPGA_READY:
-                case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
-                    cv->inv_set(pn2r.second, true);
-                    break;
-                case CycloneV::CSEL:
-                    if (pi < 2)
-                        cv->inv_set(pn2r.second, true);
-                    break;
-                case CycloneV::BSEL:
-                    if (pi < 3)
-                        cv->inv_set(pn2r.second, true);
-                    break;
-                default:
-                    break;
-                };
-                break;
-            };
-            case CycloneV::HPS_CROSS_TRIGGER: {
-                if (pt == CycloneV::CLK_EN)
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::HPS_TEST: {
-                if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::GPIO: {
-                // Ignore GPIO used by the design
-                BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
-                                                  CycloneV::pn2bi(pn));
-                if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
-                    continue;
-                // Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
-                // Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
-                // GND, presumably for power/EMI reasons
-                bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
-                if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
-                    continue;
-                if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
-                    continue;
-                cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::FPLL: {
-                if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            default:
-                break;
-            }
-        }
     }
 
     void write_dqs()
@@ -392,7 +297,7 @@ struct MistralBitgen
     void run()
     {
         cv->clear();
-        init();
+        options();
         write_routing();
         write_dqs();
         write_cells();

From 91a0eb93672e9c764f03fd1b0a7d22595a61c516 Mon Sep 17 00:00:00 2001
From: Olivier Galibert <galibert@pobox.com>
Date: Tue, 18 Jan 2022 22:37:35 +0100
Subject: [PATCH 043/712] Mistral: fix gpio OE, add hmc bypass support

---
 .github/workflows/mistral_ci.yml |  2 +-
 mistral/arch.h                   | 34 +++++++++++++++++-
 mistral/bitstream.cc             | 62 +++++++++++++++++++-------------
 mistral/io.cc                    | 10 +++---
 4 files changed, 78 insertions(+), 30 deletions(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 0da633e68d..a02026cfff 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: db29e403bede4d514fcf83948db9d4c05df07e96
+        MISTRAL_REVISION: 0c2ab2b2c6af33fea1c20349be2e0068366ed615 
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/arch.h b/mistral/arch.h
index 9c38d5d2c3..98340d4e9a 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -461,9 +461,41 @@ struct Arch : BaseArch<ArchRanges>
 
     void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
 
+    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const
+    {
+        auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
+        auto rn1 = cyclonev->pnode_to_rnode(pn1);
+        if(rn1)
+            return rn1;
+
+        if(bt == CycloneV::GPIO) {
+            auto pn2 = cyclonev->p2p_to(pn1);
+            if(!pn2) {
+                auto pnv = cyclonev->p2p_from(pn1);
+                if(!pnv.empty())
+                    pn2 = pnv[0];
+            }
+            auto pn3 = cyclonev->hmc_get_bypass(pn2);
+            auto rn2 = cyclonev->pnode_to_rnode(pn3);
+            return rn2;
+        }
+
+        return 0;
+    }
+
     WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
     {
-        return WireId(cyclonev->pnode_to_rnode(CycloneV::pnode(bt, x, y, port, bi, pi)));
+        auto rn = find_rnode(bt, x, y, port, bi, pi);
+        if(rn)
+            return WireId(rn);
+
+        fprintf(stderr, "Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
+        exit(1);
+    }
+
+    bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
+    {
+        return find_rnode(bt, x, y, port, bi, pi) != 0;
     }
 
     void create_lab(int x, int y, bool is_mlab);       // lab.cc
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index b432be037d..3307972781 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -29,6 +29,34 @@ struct MistralBitgen
     Context *ctx;
     CycloneV *cv;
 
+    using rnode_t = CycloneV::rnode_t;
+    using pnode_t = CycloneV::pnode_t;
+    using pos_t = CycloneV::pos_t;
+    using block_type_t = CycloneV::block_type_t;
+    using port_type_t = CycloneV::port_type_t;
+
+    rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
+    {
+        auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
+        auto rn1 = cv->pnode_to_rnode(pn1);
+        if(rn1)
+            return rn1;
+
+        if(bt == CycloneV::GPIO) {
+            auto pn2 = cv->p2p_to(pn1);
+            if(!pn2) {
+                auto pnv = cv->p2p_from(pn1);
+                if(!pnv.empty())
+                    pn2 = pnv[0];
+            }
+            auto pn3 = cv->hmc_get_bypass(pn2);
+            auto rn2 = cv->pnode_to_rnode(pn3);
+            return rn2;
+        }
+
+        return 0;
+    }
+
     void options()
     {
         if (!ctx->setting<bool>("compress_rbf", false)) {
@@ -38,27 +66,6 @@ struct MistralBitgen
             cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
     }
 
-    void write_dqs()
-    {
-        for (auto pos : cv->dqs16_get_pos()) {
-            int x = CycloneV::pos2x(pos), y = CycloneV::pos2y(pos);
-            // DQS bypass for used output pins
-            for (int z = 0; z < 16; z++) {
-                int ioy = y + (z / 4) - 2;
-                if (ioy < 0 || ioy >= int(cv->get_tile_sy()))
-                    continue;
-                BelId bel = ctx->bel_by_block_idx(x, ioy, id_MISTRAL_IO, z % 4);
-                if (bel == BelId())
-                    continue;
-                CellInfo *ci = ctx->getBoundBelCell(bel);
-                if (ci == nullptr || (ci->type != id_MISTRAL_IO && ci->type != id_MISTRAL_OB))
-                    continue; // not an output
-                cv->bmux_m_set(CycloneV::DQS16, pos, CycloneV::INPUT_REG4_SEL, z, CycloneV::SEL_LOCKED_DPA);
-                cv->bmux_r_set(CycloneV::DQS16, pos, CycloneV::RB_T9_SEL_EREG_CFF_DELAY, z, 0x1f);
-            }
-        }
-    }
-
     void write_routing()
     {
         for (auto &net : ctx->nets) {
@@ -87,12 +94,20 @@ struct MistralBitgen
         if (is_output) {
             cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::DRIVE_STRENGTH, bi, CycloneV::V3P3_LVTTL_16MA_LVCMOS_2MA);
             cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::IOCSR_STD, bi, CycloneV::DIS);
+
+            // Output gpios must also bypass things in the associated dqs
+            auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
+            printf("%s -> %s\n", CycloneV::pn2s(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1)).c_str(), CycloneV::pn2s(dqs).c_str());
+            if(dqs) {
+                cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
+                cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);
+            }
         }
         // There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
         // prevent a single bitflip from turning inputs to outputs and messing up other devices on the boards, notably
         // ECP5 does similar. OEIN.0 inverted for outputs; OEIN.1 for inputs
-        cv->inv_set(cv->pnode_to_rnode(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, is_output ? 0 : 1)),
-                    true);
+        cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 0), is_output);
+        cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 1), !is_output);
     }
 
     void write_clkbuf_cell(CellInfo *ci, int x, int y, int bi)
@@ -299,7 +314,6 @@ struct MistralBitgen
         cv->clear();
         options();
         write_routing();
-        write_dqs();
         write_cells();
         write_labs();
     }
diff --git a/mistral/io.cc b/mistral/io.cc
index dab3672e28..a0a01af38a 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -30,10 +30,12 @@ void Arch::create_gpio(int x, int y)
         WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
         BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
-        // FIXME: is the port index of zero always correct?
-        add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
-        add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
-        add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+        if(has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
+            // FIXME: is the port index of zero always correct?
+            add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
+            add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
+            add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+        }
         bel_data(bel).block_index = z;
     }
 }

From 27d38de612ce4109723704f863ac82a6cbddf10c Mon Sep 17 00:00:00 2001
From: Olivier Galibert <galibert@pobox.com>
Date: Wed, 19 Jan 2022 08:42:29 +0100
Subject: [PATCH 044/712] Mistral: Use log_error, remove leftover debugging
 printf.

---
 mistral/arch.cc      | 36 ++++++++++++++++++++++++++++++++++++
 mistral/arch.h       | 39 +++------------------------------------
 mistral/bitstream.cc |  1 -
 3 files changed, 39 insertions(+), 37 deletions(-)

diff --git a/mistral/arch.cc b/mistral/arch.cc
index 034ecb980a..f61d07abe0 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -43,6 +43,42 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 #undef X
 }
 
+CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, int pi) const
+{
+    auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
+    auto rn1 = cyclonev->pnode_to_rnode(pn1);
+    if(rn1)
+        return rn1;
+
+    if(bt == CycloneV::GPIO) {
+        auto pn2 = cyclonev->p2p_to(pn1);
+        if(!pn2) {
+            auto pnv = cyclonev->p2p_from(pn1);
+            if(!pnv.empty())
+                pn2 = pnv[0];
+        }
+        auto pn3 = cyclonev->hmc_get_bypass(pn2);
+        auto rn2 = cyclonev->pnode_to_rnode(pn3);
+        return rn2;
+    }
+
+    return 0;
+}
+
+WireId Arch::get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
+{
+    auto rn = find_rnode(bt, x, y, port, bi, pi);
+    if(rn)
+        return WireId(rn);
+    
+    log_error("Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
+}
+
+bool Arch::has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
+{
+    return find_rnode(bt, x, y, port, bi, pi) != 0;
+}
+
 Arch::Arch(ArchArgs args)
 {
     this->args = args;
diff --git a/mistral/arch.h b/mistral/arch.h
index 98340d4e9a..e931df2d08 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -461,42 +461,9 @@ struct Arch : BaseArch<ArchRanges>
 
     void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
 
-    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const
-    {
-        auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
-        auto rn1 = cyclonev->pnode_to_rnode(pn1);
-        if(rn1)
-            return rn1;
-
-        if(bt == CycloneV::GPIO) {
-            auto pn2 = cyclonev->p2p_to(pn1);
-            if(!pn2) {
-                auto pnv = cyclonev->p2p_from(pn1);
-                if(!pnv.empty())
-                    pn2 = pnv[0];
-            }
-            auto pn3 = cyclonev->hmc_get_bypass(pn2);
-            auto rn2 = cyclonev->pnode_to_rnode(pn3);
-            return rn2;
-        }
-
-        return 0;
-    }
-
-    WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
-    {
-        auto rn = find_rnode(bt, x, y, port, bi, pi);
-        if(rn)
-            return WireId(rn);
-
-        fprintf(stderr, "Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
-        exit(1);
-    }
-
-    bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
-    {
-        return find_rnode(bt, x, y, port, bi, pi) != 0;
-    }
+    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const;
+    WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
+    bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
 
     void create_lab(int x, int y, bool is_mlab);       // lab.cc
     void create_gpio(int x, int y);                    // io.cc
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 3307972781..340f4b9642 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -97,7 +97,6 @@ struct MistralBitgen
 
             // Output gpios must also bypass things in the associated dqs
             auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
-            printf("%s -> %s\n", CycloneV::pn2s(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1)).c_str(), CycloneV::pn2s(dqs).c_str());
             if(dqs) {
                 cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
                 cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);

From 18f71ace8c0cd08478ec7ab1e05cc7036ba18c6a Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 25 Jan 2022 12:08:52 +0100
Subject: [PATCH 045/712] Removed the need for MULT36_CORE bel for implementing
 the MULTADDSUB9X9WIDE macro

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index c3d9cba286..e89dc9c00d 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1784,7 +1784,7 @@ struct NexusPacker
                     copy_port(ctx, ci, mt.has_addsub ? id_SIGNED : id_SIGNEDA, mult9[i], id_ASIGNED);
             }
 
-            bool mult36_used = (mt.a_width >= 36) && (mt.b_width >= 36);
+            bool mult36_used = (mt.a_width >= 36) && (mt.b_width >= 36) && !(mt.wide > 0);
             // Configure mult18x36s
             for (int i = 0; i < mt.N18x36; i++) {
                 mult18x36[i]->params[id_MULT36] = mult36_used ? std::string("ENABLED") : std::string("DISABLED");

From e51e82d6a93d2d46ab11601769e736dd5029d70d Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Fri, 28 Jan 2022 13:51:10 +0100
Subject: [PATCH 046/712] Added honoring OSCA output frequency tolerance during
 constraints generation

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/pack.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index e89dc9c00d..41f9d80664 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1987,8 +1987,9 @@ struct NexusPacker
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
                 } else if (ci->type == id_OSC_CORE) {
                     int div = int_or_default(ci->params, ctx->id("HF_CLK_DIV"), 128);
-                    set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1)));
-                    set_period(ci, id_LFCLKOUT, delay_t((1.0e3 / 10)));
+                    const float tol = 1.15f; // OSCA has +/-15% frequency tolerance, assume the worst case.
+                    set_period(ci, id_HFCLKOUT, delay_t(tol * (1.0e6 / 450) * (div + 1)));
+                    set_period(ci, id_LFCLKOUT, delay_t(tol * (1.0e3 / 10)));
                 } else if (ci->type == id_PLL_CORE) {
                     static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
                     static const std::array<IdString, 6> output{id_CLKOP,  id_CLKOS,  id_CLKOS2,

From 22e4081c73ab7eec3c9f0841fcb1f247a85b5265 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 29 Jan 2022 14:45:17 +1000
Subject: [PATCH 047/712] gowin: Add GUI.

* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.

For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.

Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/nextpnr_base_types.h      |    2 +
 common/svg.cc                    |    2 +
 gowin/arch.cc                    |  232 +-
 gowin/arch.h                     |   29 +-
 gowin/constids.inc               |  342 +++
 gowin/cst.cc                     |   40 +
 gowin/cst.h                      |   34 +
 gowin/gfx.cc                     |  932 ++++++
 gowin/gfx.h                      | 4935 ++++++++++++++++++++++++++++++
 gowin/main.cc                    |    1 +
 gui/designwidget.cc              |    6 +
 gui/fpgaviewwidget.cc            |   83 +-
 gui/gowin/mainwindow.cc          |   60 +-
 gui/gowin/mainwindow.h           |   12 +
 gui/gowin/nextpnr.qrc            |    3 +
 gui/gowin/resources/open_cst.png |  Bin 0 -> 9399 bytes
 16 files changed, 6656 insertions(+), 57 deletions(-)
 create mode 100644 gowin/cst.cc
 create mode 100644 gowin/cst.h
 create mode 100644 gowin/gfx.cc
 create mode 100644 gowin/gfx.h
 create mode 100644 gui/gowin/resources/open_cst.png

diff --git a/common/nextpnr_base_types.h b/common/nextpnr_base_types.h
index 2f114bf8f9..944bf0b8b5 100644
--- a/common/nextpnr_base_types.h
+++ b/common/nextpnr_base_types.h
@@ -46,6 +46,8 @@ struct GraphicElement
         TYPE_BOX,
         TYPE_CIRCLE,
         TYPE_LABEL,
+        TYPE_LOCAL_ARROW, // Located entirely within the cell boundaries, coordinates in the range [0., 1.]
+        TYPE_LOCAL_LINE,
 
         TYPE_MAX
     } type = TYPE_NONE;
diff --git a/common/svg.cc b/common/svg.cc
index d20508431b..c5e2ea36c9 100644
--- a/common/svg.cc
+++ b/common/svg.cc
@@ -57,6 +57,8 @@ struct SVGWriter
             switch (el.type) {
             case GraphicElement::TYPE_LINE:
             case GraphicElement::TYPE_ARROW:
+            case GraphicElement::TYPE_LOCAL_LINE:
+            case GraphicElement::TYPE_LOCAL_ARROW:
                 out << stringf("<line x1=\"%f\" y1=\"%f\" x2=\"%f\" y2=\"%f\" stroke=\"%s\"/>", (el.x1 + dxy.x) * scale,
                                (el.y1 + dxy.y) * scale, (el.x2 + dxy.x) * scale, (el.y2 + dxy.y) * scale,
                                get_stroke_colour(el.style))
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8c654b2eb9..c55d4a7147 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -23,6 +23,7 @@
 #include <math.h>
 #include <regex>
 #include "embed.h"
+#include "gfx.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
@@ -32,6 +33,148 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+// GUI
+void Arch::fixClockSpineDecals(void)
+{
+    for (auto sp : clockSpinesCache) {
+        // row: (#of spine cells, wire_id)
+        dict<int, std::pair<int, IdString>> rows;
+        IdString min_x, max_x;
+        min_x = max_x = *sp.second.begin();
+        for (auto wire : sp.second) {
+            WireInfo &wi = wire_info(wire);
+            std::pair<int, IdString> &row = rows[wi.y];
+            ++row.first;
+            row.second = wire;
+            if (wi.x < wire_info(min_x).x) {
+                min_x = wire;
+            } else {
+                if (wi.x > wire_info(max_x).x) {
+                    max_x = wire;
+                }
+            }
+        }
+        // central mux row owns the global decal
+        int mux_row = -1;
+        for (auto row : rows) {
+            if (row.second.first == 1) {
+                mux_row = row.first;
+                break;
+            }
+        }
+        // if there is no separate central mux than all decals are the same
+        if (mux_row == -1) {
+            mux_row = rows.begin()->first;
+            WireInfo &wi = wire_info(rows.at(mux_row).second);
+            GraphicElement &el_active = decal_graphics.at(wi.decalxy_active.decal).at(0);
+            GraphicElement &el_inactive = decal_graphics.at(wi.decalxy_inactive.decal).at(0);
+            el_active.y1 -= wi.y;
+            el_active.y2 -= wi.y;
+            el_inactive.y1 -= wi.y;
+            el_inactive.y2 -= wi.y;
+            el_active.x1 += wire_info(min_x).x;
+            el_active.x2 += wire_info(max_x).x;
+            el_inactive.x1 += wire_info(min_x).x;
+            el_inactive.x2 += wire_info(max_x).x;
+        } else {
+            // change the global decal
+            WireInfo &wi = wire_info(rows.at(mux_row).second);
+            // clear spine decals
+            float y = 0.;
+            for (auto wire : sp.second) {
+                if (wire == wi.name) {
+                    continue;
+                }
+                wire_info(wire).decalxy_active = DecalXY();
+                wire_info(wire).decalxy_inactive = DecalXY();
+                y = wire_info(wire).y;
+            }
+            GraphicElement &el_active = decal_graphics.at(wi.decalxy_active.decal).at(0);
+            GraphicElement &el_inactive = decal_graphics.at(wi.decalxy_inactive.decal).at(0);
+            el_active.y1 -= y;
+            el_active.y2 -= y;
+            el_inactive.y1 -= y;
+            el_inactive.y2 -= y;
+            el_active.x1 += wire_info(min_x).x;
+            el_active.x2 += wire_info(max_x).x;
+            el_inactive.x1 += wire_info(min_x).x;
+            el_inactive.x2 += wire_info(max_x).x;
+        }
+        refreshUi();
+    }
+}
+
+void Arch::updateClockSpinesCache(IdString spine_id, IdString wire_id)
+{
+    std::vector<IdString> &sp = clockSpinesCache[spine_id];
+    if (std::find(sp.begin(), sp.end(), wire_id) == sp.end()) {
+        sp.push_back(wire_id);
+    }
+}
+
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+    CellInfo *ci = getBoundBelCell(bel);
+    if (ci == nullptr) {
+        return bels.at(bel).decalxy_inactive;
+    } else {
+        // LUT + used/unused DFF
+        if (bels.at(bel).type == id_SLICE) {
+            DecalXY decalxy = bels.at(bel).decalxy_active;
+            if (!ci->params.at(id_FF_USED).as_bool()) {
+                decalxy.decal = id_DECAL_LUT_UNUSED_DFF_ACTIVE;
+                if (ci->params.count(id_ALU_MODE) != 0) {
+                    decalxy.decal = id_DECAL_ALU_ACTIVE;
+                }
+            }
+            return decalxy;
+        }
+    }
+    return bels.at(bel).decalxy_active;
+}
+
+DecalXY Arch::getGroupDecal(GroupId grp) const { return groups.at(grp).decalxy; }
+
+DecalXY Arch::getPipDecal(PipId pip) const
+{
+    if (getBoundPipNet(pip) == nullptr) {
+        return pips.at(pip).decalxy_inactive;
+    }
+    return pips.at(pip).decalxy_active;
+}
+
+DecalXY Arch::getWireDecal(WireId wire) const
+{
+    static std::vector<IdString> clk_wires = {id_GB00, id_GB10, id_GB20, id_GB30, id_GB40, id_GB50, id_GB60, id_GB70};
+    static std::vector<IdString> pip_dst = {id_CLK0, id_CLK1, id_CLK2, id_EW10, id_EW20, id_SN10, id_SN20};
+    if (getBoundWireNet(wire) == nullptr) {
+        if (std::find(clk_wires.begin(), clk_wires.end(), wires.at(wire).type) != clk_wires.end()) {
+            for (auto dst : pip_dst) {
+                // check if pip is used
+                char pip_name[20];
+                snprintf(pip_name, sizeof(pip_name), "%s_%s", wire.c_str(this), dst.c_str(this));
+                if (pips.count(id(pip_name)) != 0) {
+                    if (getBoundPipNet(id(pip_name)) != nullptr) {
+                        return wires.at(wire).decalxy_active;
+                    }
+                }
+            }
+        } else {
+            // spines
+            if (clockSpinesCache.count(wires.at(wire).type) != 0) {
+                std::vector<IdString> const &sp = clockSpinesCache.at(wires.at(wire).type);
+                for (auto w : sp) {
+                    if (getBoundWireNet(w) != nullptr) {
+                        return wires.at(wire).decalxy_active;
+                    }
+                }
+            }
+        }
+        return wires.at(wire).decalxy_inactive;
+    }
+    return wires.at(wire).decalxy_active;
+}
+
 WireInfo &Arch::wire_info(IdString wire)
 {
     auto w = wires.find(wire);
@@ -58,7 +201,6 @@ BelInfo &Arch::bel_info(IdString bel)
 
 void Arch::addWire(IdString name, IdString type, int x, int y)
 {
-    // std::cout << name.str(this) << std::endl;
     NPNR_ASSERT(wires.count(name) == 0);
     WireInfo &wi = wires[name];
     wi.name = name;
@@ -105,6 +247,13 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi
     tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
 }
 
+void Arch::addGroup(IdString name)
+{
+    NPNR_ASSERT(groups.count(name) == 0);
+    GroupInfo &gi = groups[name];
+    gi.name = name;
+}
+
 void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
 {
     NPNR_ASSERT(bels.count(name) == 0);
@@ -189,24 +338,41 @@ void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
     refreshUi();
 }
 
-void Arch::setWireDecal(WireId wire, DecalXY decalxy)
+void Arch::setWireDecal(WireId wire, DecalXY active, DecalXY inactive)
 {
-    wire_info(wire).decalxy = decalxy;
+    wire_info(wire).decalxy_active = active;
+    wire_info(wire).decalxy_inactive = inactive;
     refreshUiWire(wire);
 }
 
-void Arch::setPipDecal(PipId pip, DecalXY decalxy)
+void Arch::setPipDecal(PipId pip, DecalXY active, DecalXY inactive)
 {
-    pip_info(pip).decalxy = decalxy;
+    pip_info(pip).decalxy_active = active;
+    pip_info(pip).decalxy_inactive = inactive;
     refreshUiPip(pip);
 }
 
-void Arch::setBelDecal(BelId bel, DecalXY decalxy)
+void Arch::setBelDecal(BelId bel, DecalXY active, DecalXY inactive)
 {
-    bel_info(bel).decalxy = decalxy;
+    bel_info(bel).decalxy_active = active;
+    bel_info(bel).decalxy_inactive = inactive;
     refreshUiBel(bel);
 }
 
+void Arch::setDefaultDecals(void)
+{
+    for (BelId bel : getBels()) {
+        gfxSetBelDefaultDecal(this, bel_info(bel));
+    }
+    for (PipId pip : getPips()) {
+        gfxSetPipDefaultDecal(this, pip_info(pip));
+    }
+    for (WireId wire : getWires()) {
+        gfxSetWireDefaultDecal(this, wire_info(wire));
+    }
+    fixClockSpineDecals();
+}
+
 void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
 {
     groups[group].decalxy = decalxy;
@@ -519,6 +685,7 @@ void Arch::read_cst(std::istream &in)
         insloc
     } cst_type;
 
+    settings.erase(id("cst"));
     while (!in.eof()) {
         std::getline(in, line);
         cst_type = ioloc;
@@ -584,6 +751,7 @@ void Arch::read_cst(std::istream &in)
         }
         }
     }
+    settings[id("cst")] = 1;
 }
 
 // Add all MUXes for the cell
@@ -689,6 +857,14 @@ Arch::Arch(ArchArgs args) : args(args)
         IdString::initialize_add(this, db->id_strs[i].get(), uint32_t(i) + db->num_constids);
     }
 
+    // Empty decal
+    addDecalGraphic(IdString(), GraphicElement());
+
+    if (args.gui) {
+        // decals
+        gfxCreateBelDecals(this);
+    }
+
     // setup package
     IdString package_name;
     IdString device_id;
@@ -762,9 +938,17 @@ Arch::Arch(ArchArgs args) : args(args)
     // The reverse order of the enumeration simplifies the creation
     // of MUX2_LUT8s: they need the existence of the wire on the right.
     for (int i = db->rows * db->cols - 1; i >= 0; --i) {
+        IdString grpname;
         int row = i / db->cols;
         int col = i % db->cols;
         const TilePOD *tile = db->grid[i].get();
+        if (args.gui) {
+            // CRU decal
+            snprintf(buf, 32, "R%dC%d_CRU", row + 1, col + 1);
+            grpname = id(buf);
+            addGroup(grpname);
+            setGroupDecal(grpname, gfxGetCruGroupDecalXY(col, row));
+        }
         // setup wires
         const PairPOD *pips[2] = {tile->pips.get(), tile->clock_pips.get()};
         unsigned int num_pips[2] = {tile->num_pips, tile->num_clock_pips};
@@ -837,6 +1021,14 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (z == 0) {
                     addMuxBels(db, row, col);
                 }
+                if (z % 2 == 0) {
+                    snprintf(buf, 32, "R%dC%d_LUT_GRP%d", row + 1, col + 1, z);
+                    grpname = id(buf);
+                    if (args.gui) {
+                        addGroup(grpname);
+                        setGroupDecal(grpname, gfxGetLutGroupDecalXY(col, row, z >> 1));
+                    }
+                }
                 break;
             case ID_IOBJ:
                 z++; /* fall-through*/
@@ -933,7 +1125,6 @@ Arch::Arch(ArchArgs args) : args(args)
                 DelayQuad delay = getWireTypeDelay(destid);
                 // local alias
                 auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, srcid.index);
-                // std::cout << "srcid " << srcid.str(this) << std::endl;
                 if (local_alias != nullptr) {
                     srcid = IdString(local_alias->src_id);
                     gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
@@ -950,12 +1141,14 @@ Arch::Arch(ArchArgs args) : args(args)
                     srcrow = alias_src->src_row;
                     srcid = IdString(alias_src->src_id);
                     gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
-                    // std::cout << buf << std::endl;
                 }
                 addPip(pipname, destid, gsrcname, gdestname, delay, Loc(col, row, j));
             }
         }
     }
+    if (args.gui) {
+        setDefaultDecals();
+    }
 
     // Permissible combinations of modes in a single slice
     dff_comp_mode[id_DFF] = id_DFF;
@@ -1015,6 +1208,17 @@ BelId Arch::getBelByLocation(Loc loc) const
 
 const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_by_tile.at(x).at(y); }
 
+bool Arch::haveBelType(int x, int y, IdString bel_type)
+{
+    for (auto bel : getBelsByTile(x, y)) {
+        BelInfo bi = bel_info(bel);
+        if (bi.type == bel_type) {
+            return true;
+        }
+    }
+    return false;
+}
+
 bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
 
 void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
@@ -1303,6 +1507,16 @@ bool Arch::route()
     return result;
 }
 
+// ---------------------------------------------------------------
+std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
+{
+    if (!decal_graphics.count(decal)) {
+        // XXX
+        return std::vector<GraphicElement>();
+    }
+    return decal_graphics.at(decal);
+}
+
 // ---------------------------------------------------------------
 
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
diff --git a/gowin/arch.h b/gowin/arch.h
index 9f969f54f0..9ce3bd1c29 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -176,6 +176,7 @@ struct ArchArgs
     // y = mx + c relationship between distance and delay for interconnect
     // delay estimates
     double delayScale = 0.4, delayOffset = 0.4;
+    bool gui;
 };
 
 struct WireInfo;
@@ -187,7 +188,7 @@ struct PipInfo
     NetInfo *bound_net;
     WireId srcWire, dstWire;
     DelayQuad delay;
-    DecalXY decalxy;
+    DecalXY decalxy_active, decalxy_inactive;
     Loc loc;
 };
 
@@ -200,7 +201,7 @@ struct WireInfo
     BelPin uphill_bel_pin;
     std::vector<BelPin> downhill_bel_pins;
     std::vector<BelPin> bel_pins;
-    DecalXY decalxy;
+    DecalXY decalxy_active, decalxy_inactive;
     int x, y;
 };
 
@@ -217,7 +218,7 @@ struct BelInfo
     std::map<IdString, std::string> attrs;
     CellInfo *bound_cell;
     dict<IdString, PinInfo> pins;
-    DecalXY decalxy;
+    DecalXY decalxy_active, decalxy_inactive;
     int x, y, z;
     bool gb;
 };
@@ -270,8 +271,6 @@ struct ArchRanges : BaseArchRanges
     using GroupWiresRangeT = const std::vector<WireId> &;
     using GroupPipsRangeT = const std::vector<PipId> &;
     using GroupGroupsRangeT = const std::vector<GroupId> &;
-    // Decals
-    using DecalGfxRangeT = const std::vector<GraphicElement> &;
 };
 
 struct Arch : BaseArch<ArchRanges>
@@ -312,16 +311,23 @@ struct Arch : BaseArch<ArchRanges>
     void addBelOutput(IdString bel, IdString name, IdString wire);
     void addBelInout(IdString bel, IdString name, IdString wire);
 
+    void addGroup(IdString name);
     void addGroupBel(IdString group, IdString bel);
     void addGroupWire(IdString group, IdString wire);
     void addGroupPip(IdString group, IdString pip);
     void addGroupGroup(IdString group, IdString grp);
 
     void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
-    void setWireDecal(WireId wire, DecalXY decalxy);
-    void setPipDecal(PipId pip, DecalXY decalxy);
-    void setBelDecal(BelId bel, DecalXY decalxy);
+    void setWireDecal(WireId wire, DecalXY active, DecalXY inactive);
+    void setPipDecal(PipId pip, DecalXY active, DecalXY inactive);
+    void setBelDecal(BelId bel, DecalXY active, DecalXY inactive);
+    void setDefaultDecals(void);
     void setGroupDecal(GroupId group, DecalXY decalxy);
+    std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
+    DecalXY getBelDecal(BelId bel) const override;
+    DecalXY getGroupDecal(GroupId grp) const override;
+    DecalXY getPipDecal(PipId pip) const override;
+    DecalXY getWireDecal(WireId pip) const override;
 
     void setWireAttr(IdString wire, IdString key, const std::string &value);
     void setPipAttr(IdString pip, IdString key, const std::string &value);
@@ -452,6 +458,7 @@ struct Arch : BaseArch<ArchRanges>
     // Internal usage
     void assignArchInfo() override;
     bool cellsCompatible(const CellInfo **cells, int count) const;
+    bool haveBelType(int x, int y, IdString bel_type);
     // start Z for the MUX2LUT5 bels
     int const mux_0_z = 10;
     // chip db version
@@ -459,6 +466,12 @@ struct Arch : BaseArch<ArchRanges>
 
     std::vector<IdString> cell_types;
 
+    // clock spines cache
+    // spine_id : [wire_id, wire_id, ...]
+    dict<IdString, std::vector<IdString>> clockSpinesCache;
+    void updateClockSpinesCache(IdString spine_id, IdString wire_id);
+    void fixClockSpineDecals(void);
+
     // Permissible combinations of modes in a single slice
     std::map<const IdString, IdString> dff_comp_mode;
 };
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 6a730d5d5e..82d0bb11df 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -313,6 +313,312 @@ X(COUT2)
 X(COUT3)
 X(COUT4)
 X(COUT5)
+
+// wires
+// SN
+X(S10)
+X(S10_loop0)
+X(S13)
+X(S13_loop0)
+X(N10)
+X(N10_loop0)
+X(N13)
+X(N13_loop0)
+X(SN10_loop_n)
+X(SN10_loop_s)
+X(SN20_loop_n)
+X(SN20_loop_s)
+X(S20)
+X(S20_loop0)
+X(S20_loop1)
+X(S21)
+X(S21_loop0)
+X(S21_loop1)
+X(S22)
+X(S22_loop0)
+X(S22_loop1)
+X(S23)
+X(S23_loop0)
+X(S23_loop1)
+X(S24)
+X(S24_loop0)
+X(S24_loop1)
+X(S25)
+X(S25_loop0)
+X(S25_loop1)
+X(S26)
+X(S26_loop0)
+X(S26_loop1)
+X(S27)
+X(S27_loop0)
+X(S27_loop1)
+X(N20)
+X(N20_loop0)
+X(N20_loop1)
+X(N21)
+X(N21_loop0)
+X(N21_loop1)
+X(N22)
+X(N22_loop0)
+X(N22_loop1)
+X(N23)
+X(N23_loop0)
+X(N23_loop1)
+X(N24)
+X(N24_loop0)
+X(N24_loop1)
+X(N25)
+X(N25_loop0)
+X(N25_loop1)
+X(N26)
+X(N26_loop0)
+X(N26_loop1)
+X(N27)
+X(N27_loop0)
+X(N27_loop1)
+X(S80)
+X(S80_loop0)
+X(S80_loop1)
+X(S80_loop2)
+X(S80_loop3)
+X(S80_loop4)
+X(S80_loop5)
+X(S80_loop6)
+X(S80_loop7)
+X(N80)
+X(N80_loop0)
+X(N80_loop1)
+X(N80_loop2)
+X(N80_loop3)
+X(N80_loop4)
+X(N80_loop5)
+X(N80_loop6)
+X(N80_loop7)
+X(S81)
+X(S81_loop0)
+X(S81_loop1)
+X(S81_loop2)
+X(S81_loop3)
+X(S81_loop4)
+X(S81_loop5)
+X(S81_loop6)
+X(S81_loop7)
+X(N81)
+X(N81_loop0)
+X(N81_loop1)
+X(N81_loop2)
+X(N81_loop3)
+X(N81_loop4)
+X(N81_loop5)
+X(N81_loop6)
+X(N81_loop7)
+X(S82)
+X(S82_loop0)
+X(S82_loop1)
+X(S82_loop2)
+X(S82_loop3)
+X(S82_loop4)
+X(S82_loop5)
+X(S82_loop6)
+X(S82_loop7)
+X(N82)
+X(N82_loop0)
+X(N82_loop1)
+X(N82_loop2)
+X(N82_loop3)
+X(N82_loop4)
+X(N82_loop5)
+X(N82_loop6)
+X(N82_loop7)
+X(S83)
+X(S83_loop0)
+X(S83_loop1)
+X(S83_loop2)
+X(S83_loop3)
+X(S83_loop4)
+X(S83_loop5)
+X(S83_loop6)
+X(S83_loop7)
+X(N83)
+X(N83_loop0)
+X(N83_loop1)
+X(N83_loop2)
+X(N83_loop3)
+X(N83_loop4)
+X(N83_loop5)
+X(N83_loop6)
+X(N83_loop7)
+
+// WE
+X(E10)
+X(E10_loop0)
+X(E13)
+X(E13_loop0)
+X(W10)
+X(W10_loop0)
+X(W13)
+X(W13_loop0)
+X(EW10_loop_w)
+X(EW10_loop_e)
+X(EW20_loop_w)
+X(EW20_loop_e)
+// 
+X(E20)
+X(E20_loop0)
+X(E20_loop1)
+X(E21)
+X(E21_loop0)
+X(E21_loop1)
+X(E22)
+X(E22_loop0)
+X(E22_loop1)
+X(E23)
+X(E23_loop0)
+X(E23_loop1)
+X(E24)
+X(E24_loop0)
+X(E24_loop1)
+X(E25)
+X(E25_loop0)
+X(E25_loop1)
+X(E26)
+X(E26_loop0)
+X(E26_loop1)
+X(E27)
+X(E27_loop0)
+X(E27_loop1)
+X(W20)
+X(W20_loop0)
+X(W20_loop1)
+X(W21)
+X(W21_loop0)
+X(W21_loop1)
+X(W22)
+X(W22_loop0)
+X(W22_loop1)
+X(W23)
+X(W23_loop0)
+X(W23_loop1)
+X(W24)
+X(W24_loop0)
+X(W24_loop1)
+X(W25)
+X(W25_loop0)
+X(W25_loop1)
+X(W26)
+X(W26_loop0)
+X(W26_loop1)
+X(W27)
+X(W27_loop0)
+X(W27_loop1)
+//
+X(E80)
+X(E80_loop0)
+X(E80_loop1)
+X(E80_loop2)
+X(E80_loop3)
+X(E80_loop4)
+X(E80_loop5)
+X(E80_loop6)
+X(E80_loop7)
+X(W80)
+X(W80_loop0)
+X(W80_loop1)
+X(W80_loop2)
+X(W80_loop3)
+X(W80_loop4)
+X(W80_loop5)
+X(W80_loop6)
+X(W80_loop7)
+X(E81)
+X(E81_loop0)
+X(E81_loop1)
+X(E81_loop2)
+X(E81_loop3)
+X(E81_loop4)
+X(E81_loop5)
+X(E81_loop6)
+X(E81_loop7)
+X(W81)
+X(W81_loop0)
+X(W81_loop1)
+X(W81_loop2)
+X(W81_loop3)
+X(W81_loop4)
+X(W81_loop5)
+X(W81_loop6)
+X(W81_loop7)
+X(E82)
+X(E82_loop0)
+X(E82_loop1)
+X(E82_loop2)
+X(E82_loop3)
+X(E82_loop4)
+X(E82_loop5)
+X(E82_loop6)
+X(E82_loop7)
+X(W82)
+X(W82_loop0)
+X(W82_loop1)
+X(W82_loop2)
+X(W82_loop3)
+X(W82_loop4)
+X(W82_loop5)
+X(W82_loop6)
+X(W82_loop7)
+X(E83)
+X(E83_loop0)
+X(E83_loop1)
+X(E83_loop2)
+X(E83_loop3)
+X(E83_loop4)
+X(E83_loop5)
+X(E83_loop6)
+X(E83_loop7)
+X(W83)
+X(W83_loop0)
+X(W83_loop1)
+X(W83_loop2)
+X(W83_loop3)
+X(W83_loop4)
+X(W83_loop5)
+X(W83_loop6)
+X(W83_loop7)
+
+// spines
+X(SPINE0)
+X(SPINE1)
+X(SPINE2)
+X(SPINE3)
+X(SPINE4)
+X(SPINE5)
+X(SPINE6)
+X(SPINE7)
+X(SPINE8)
+X(SPINE9)
+X(SPINE10)
+X(SPINE11)
+X(SPINE12)
+X(SPINE13)
+X(SPINE14)
+X(SPINE15)
+X(SPINE16)
+X(SPINE17)
+X(SPINE18)
+X(SPINE19)
+X(SPINE20)
+X(SPINE21)
+X(SPINE22)
+X(SPINE23)
+X(SPINE24)
+X(SPINE25)
+X(SPINE26)
+X(SPINE27)
+X(SPINE28)
+X(SPINE29)
+X(SPINE30)
+X(SPINE31)
+
 // slice items
 X(SLICE)
 X(CLK)
@@ -380,6 +686,22 @@ X(GW_MUX2_LUT5)
 X(GW_MUX2_LUT6)
 X(GW_MUX2_LUT7)
 X(GW_MUX2_LUT8)
+X(I0MUX0)
+X(I1MUX0)
+X(I0MUX1)
+X(I1MUX1)
+X(I0MUX2)
+X(I1MUX2)
+X(I0MUX3)
+X(I1MUX3)
+X(I0MUX4)
+X(I1MUX4)
+X(I0MUX5)
+X(I1MUX5)
+X(I0MUX6)
+X(I1MUX6)
+X(I0MUX7)
+X(I1MUX7)
 
 // ALU
 X(ALU)
@@ -464,3 +786,23 @@ X(d_f)
 X(fx_ofx1)
 X(I01)
 
+// GUI
+X(DECAL_LUT_ACTIVE)
+X(DECAL_LUT_INACTIVE)
+X(DECAL_LUTDFF_ACTIVE)
+X(DECAL_LUTDFF_INACTIVE)
+X(DECAL_LUT_UNUSED_DFF_ACTIVE)
+X(DECAL_GRP_LUT)
+X(DECAL_CRU)
+X(DECAL_MUXUPPER_INACTIVE)
+X(DECAL_MUXUPPER_ACTIVE)
+X(DECAL_MUXLOWER_INACTIVE)
+X(DECAL_MUXLOWER_ACTIVE)
+X(DECAL_IOB_INACTIVE)
+X(DECAL_IOB_ACTIVE)
+X(DECAL_IOBS_INACTIVE)
+X(DECAL_IOBS_ACTIVE)
+X(DECAL_ALU_ACTIVE)
+
+
+
diff --git a/gowin/cst.cc b/gowin/cst.cc
new file mode 100644
index 0000000000..7ed74c6c7f
--- /dev/null
+++ b/gowin/cst.cc
@@ -0,0 +1,40 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "cst.h"
+#include <regex>
+#include <sstream>
+#include "arch.h"
+#include "log.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool read_cst(Context *ctx, std::istream &in)
+{
+    try {
+        ctx->read_cst(in);
+        return true;
+    } catch (log_execution_error_exception) {
+        return false;
+    }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gowin/cst.h b/gowin/cst.h
new file mode 100644
index 0000000000..3fcfd66385
--- /dev/null
+++ b/gowin/cst.h
@@ -0,0 +1,34 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CST_H
+#define CST_H
+
+#include <iostream>
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// Read the constraints file
+bool read_cst(Context *ctx, std::istream &in);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/gowin/gfx.cc b/gowin/gfx.cc
new file mode 100644
index 0000000000..ad2c7eadef
--- /dev/null
+++ b/gowin/gfx.cc
@@ -0,0 +1,932 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <iostream>
+
+#include "gfx.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const int PIP_SRC_DST_LEN = 20;
+
+static void get_pip_xy(CruSide side, float &off, float &x, float &y)
+{
+    switch (side) {
+    case Top:
+        x = off;
+        y = cru_y + cru_h;
+        break;
+    case Bottom:
+        x = off;
+        y = cru_y;
+        break;
+    case Left:
+        x = cru_x;
+        y = off;
+        break;
+    case Right:
+        x = cru_x + cru_w;
+        y = off;
+        break;
+    case Center:
+        x = cru_x + cru_w / 2.f;
+        y = off;
+        break;
+    }
+}
+
+void gfxSetPipDefaultDecal(Arch *arch, PipInfo &pip)
+{
+    DecalXY active, inactive;
+    std::vector<std::string> split_res;
+    IdString src_loc_id, dst_loc_id;
+    char buf[PIP_SRC_DST_LEN];
+
+    active.x = inactive.x = pip.loc.x;
+    active.y = inactive.y = arch->gridDimY - 1. - pip.loc.y;
+    boost::split(split_res, pip.name.str(arch), [](char c) { return c == '_'; });
+    src_loc_id = arch->id(split_res.at(1));
+    dst_loc_id = arch->id(split_res.at(2));
+    snprintf(buf, PIP_SRC_DST_LEN, "%s_%s_active", src_loc_id.c_str(arch), dst_loc_id.c_str(arch));
+    IdString active_id = arch->id(buf);
+    active.decal = active_id;
+    snprintf(buf, PIP_SRC_DST_LEN, "%s_%s_inactive", src_loc_id.c_str(arch), dst_loc_id.c_str(arch));
+    IdString inactive_id = arch->id(buf);
+    inactive.decal = inactive_id;
+    // create if absent
+    if (arch->decal_graphics.count(active_id) == 0) {
+        // clock?
+        if (dst_loc_id == id_GT00 || dst_loc_id == id_GT10) {
+            WireInfo &wi = arch->wire_info(pip.srcWire);
+            if (wi.type.str(arch).substr(0, 3) != "UNK") {
+                // create pip
+                GraphicElement el;
+                el.type = GraphicElement::TYPE_LOCAL_LINE;
+                el.style = GraphicElement::STYLE_ACTIVE;
+                if (dst_loc_id == id_GT00) {
+                    el.x1 = WIRE_X(CLK_GT00_X);
+                } else {
+                    el.x1 = WIRE_X(CLK_GT10_X);
+                }
+                el.x2 = el.x1 + spine_pip_off;
+                el.y2 = spineY.at(arch->wire_info(pip.srcWire).type);
+                el.y1 = el.y2 - spine_pip_off;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+        } else {
+            // XXX
+            if (pipPoint.count(src_loc_id) == 0 || pipPoint.count(dst_loc_id) == 0) {
+                // std::cout << "*R" << pip.loc.y + 1 << "C" << pip.loc.x + 1 << " no " << pip.name.str(arch) << " " <<
+                // buf << std::endl;
+            } else {
+                GraphicElement el;
+                el.type = GraphicElement::TYPE_LOCAL_ARROW;
+                el.style = GraphicElement::STYLE_ACTIVE;
+                CruSide srcSide = pipPoint.at(src_loc_id).first;
+                float srcOff = pipPoint.at(src_loc_id).second;
+                CruSide dstSide = pipPoint.at(dst_loc_id).first;
+                float dstOff = pipPoint.at(dst_loc_id).second;
+                if (srcSide != dstSide) {
+                    get_pip_xy(srcSide, srcOff, el.x1, el.y1);
+                    get_pip_xy(dstSide, dstOff, el.x2, el.y2);
+                    arch->addDecalGraphic(active_id, el);
+                    el.style = GraphicElement::STYLE_HIDDEN;
+                    arch->addDecalGraphic(inactive_id, el);
+                } else {
+                    get_pip_xy(srcSide, srcOff, el.x1, el.y1);
+                    float dst_x = 0, dst_y = 0, m_x = 0, m_y = 0;
+                    get_pip_xy(dstSide, dstOff, dst_x, dst_y);
+                    switch (dstSide) {
+                    case Top:
+                        m_x = el.x1 + (dst_x - el.x1) / 2.f;
+                        m_y = dst_y - std::max(cru_h * 0.1f, std::min(cru_h * 0.4f, std::abs(el.x1 - dst_x)));
+                        break;
+                    case Bottom:
+                        m_x = el.x1 + (dst_x - el.x1) / 2.f;
+                        m_y = dst_y + std::max(cru_h * 0.1f, std::min(cru_h * 0.4f, std::abs(el.x1 - dst_x)));
+                        break;
+                    case Right:
+                        m_x = dst_x - std::max(cru_w * 0.1f, std::min(cru_w * 0.4f, std::abs(el.y1 - dst_y)));
+                        m_y = el.y1 + (dst_y - el.y1) / 2.f;
+                        break;
+                    case Left:
+                        m_x = dst_x + std::max(cru_w * 0.1f, std::min(cru_w * 0.4f, std::abs(el.y1 - dst_y)));
+                        m_y = el.y1 + (dst_y - el.y1) / 2.f;
+                        break;
+                    default: // unreachable
+                        break;
+                    }
+                    el.x2 = m_x;
+                    el.y2 = m_y;
+                    arch->addDecalGraphic(active_id, el);
+                    el.style = GraphicElement::STYLE_HIDDEN;
+                    arch->addDecalGraphic(inactive_id, el);
+                    el.style = GraphicElement::STYLE_ACTIVE;
+                    el.x1 = m_x;
+                    el.y1 = m_y;
+                    el.x2 = dst_x;
+                    el.y2 = dst_y;
+                    arch->addDecalGraphic(active_id, el);
+                    el.style = GraphicElement::STYLE_HIDDEN;
+                    arch->addDecalGraphic(inactive_id, el);
+                }
+            }
+        }
+    }
+    arch->setPipDecal(pip.name, active, inactive);
+}
+
+const int WIRE_ID_LEN = 30;
+
+void gfxSetWireDefaultDecal(Arch *arch, WireInfo &wire)
+{
+    DecalXY active, inactive;
+    IdString active_id, inactive_id;
+    GraphicElement el;
+    std::vector<std::string> split_res;
+    char buf[WIRE_ID_LEN];
+
+    if (std::find(decalless_wires.begin(), decalless_wires.end(), wire.name) != decalless_wires.end()) {
+        arch->setWireDecal(wire.type, DecalXY(), DecalXY());
+        return;
+    }
+    // local to cell
+    if (arch->haveBelType(wire.x, wire.y, id_SLICE) && sliceLocalWires.count(wire.type) != 0) {
+        snprintf(buf, sizeof(buf), "%s_active", wire.type.c_str(arch));
+        active_id = arch->id(buf);
+        active.decal = active_id;
+        snprintf(buf, sizeof(buf), "%s_inactive", wire.type.c_str(arch));
+        inactive_id = arch->id(buf);
+        inactive.decal = inactive_id;
+        active.x = inactive.x = wire.x;
+        active.y = inactive.y = arch->gridDimY - 1. - wire.y;
+
+        // create if absent
+        if (arch->decal_graphics.count(active_id) == 0) {
+            el.type = GraphicElement::TYPE_LOCAL_LINE;
+            for (auto seg : sliceLocalWires.at(wire.type)) {
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = std::get<0>(seg);
+                el.y1 = std::get<1>(seg);
+                el.x2 = std::get<2>(seg);
+                el.y2 = std::get<3>(seg);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+        }
+        arch->setWireDecal(wire.name, active, inactive);
+        return;
+    }
+    // spines
+    if (spineY.count(wire.type) != 0) {
+        snprintf(buf, sizeof(buf), "%s_active", wire.type.c_str(arch));
+        active_id = arch->id(buf);
+        active.decal = active_id;
+        snprintf(buf, sizeof(buf), "%s_inactive", wire.type.c_str(arch));
+        inactive_id = arch->id(buf);
+        inactive.decal = inactive_id;
+        active.x = inactive.x = 0.;
+        active.y = inactive.y = 0.;
+
+        // update clock spines cache
+        arch->updateClockSpinesCache(wire.type, wire.name);
+
+        if (arch->decal_graphics.count(active_id) == 0) {
+            el.type = GraphicElement::TYPE_LINE;
+            el.style = GraphicElement::STYLE_ACTIVE;
+            el.x1 = 0.2;                                        // cell's x will be added later in fixClockSpineDecals
+            el.x2 = 0.7;                                        // cell's x will be added later in fixClockSpineDecals
+            el.y1 = spineY.at(wire.type) + arch->gridDimY - 1.; // cell's y will be added later in fixClockSpineDecals
+            el.y2 = el.y1;
+            arch->addDecalGraphic(active_id, el);
+            el.style = GraphicElement::STYLE_HIDDEN;
+            arch->addDecalGraphic(inactive_id, el);
+        }
+        arch->setWireDecal(wire.name, active, inactive);
+        return;
+    }
+
+    // global simple wires like IMUX
+    if (globalSimpleWires.count(wire.type) != 0) {
+        snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
+        active_id = arch->id(buf);
+        active.decal = active_id;
+        snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+        inactive_id = arch->id(buf);
+        inactive.decal = inactive_id;
+        active.x = inactive.x = 0;
+        active.y = inactive.y = 0;
+
+        // create if absent
+        if (arch->decal_graphics.count(active_id) == 0) {
+            el.type = GraphicElement::TYPE_LINE;
+            for (auto seg : globalSimpleWires.at(wire.type)) {
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = std::get<0>(seg) + wire.x;
+                el.y1 = std::get<1>(seg) + arch->gridDimY - 1. - wire.y;
+                el.x2 = std::get<2>(seg) + wire.x;
+                el.y2 = std::get<3>(seg) + arch->gridDimY - 1. - wire.y;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+        }
+        arch->setWireDecal(wire.name, active, inactive);
+        return;
+    }
+
+    // global
+    boost::split(split_res, wire.name.str(arch), [](char c) { return c == '_'; });
+    if (split_res.size() >= 2) {
+        IdString wire_id = arch->id(split_res.at(1));
+        // wrap
+        if ((wire.y == (arch->gridDimY - 1) && split_res.at(1).at(0) == 'S') ||
+            (wire.y == 0 && split_res.at(1).at(0) == 'N')) {
+            wire_id = arch->id(split_res.at(1) + "_loop0");
+        }
+        if ((wire.x == (arch->gridDimX - 1) && split_res.at(1).at(0) == 'E') ||
+            (wire.x == 0 && split_res.at(1).at(0) == 'W')) {
+            wire_id = arch->id(split_res.at(1) + "_loop0");
+        }
+        // SN wires
+        if (split_res.at(1).substr(0, 2) == "SN") {
+            if (wire.y == 0) {
+                wire_id = arch->id(split_res.at(1) + "_loop_n");
+            } else {
+                if (wire.y == (arch->gridDimY - 1)) {
+                    wire_id = arch->id(split_res.at(1) + "_loop_s");
+                }
+            }
+        } else {
+            // wrap 2 hop
+            if ((wire.y == (arch->gridDimY - 2) && split_res.at(1).substr(0, 2) == "S2") ||
+                (wire.y == 1 && split_res.at(1).substr(0, 2) == "N2")) {
+                wire_id = arch->id(split_res.at(1) + "_loop1");
+            }
+            // wrap 4 hop
+            if (split_res.at(1).substr(0, 2) == "S8" || split_res.at(1).substr(0, 2) == "N8") {
+                char loop_buf[5 + 2];
+                if (split_res.at(1).substr(0, 2) == "N8") {
+                    if (wire.y < 8) {
+                        snprintf(loop_buf, sizeof(loop_buf), "_loop%1u", wire.y);
+                        wire_id = arch->id(split_res.at(1) + loop_buf);
+                    }
+                } else {
+                    if (arch->gridDimY - 1 - wire.y < 8) {
+                        snprintf(loop_buf, sizeof(loop_buf), "_loop%1u", arch->gridDimY - 1 - wire.y);
+                        wire_id = arch->id(split_res.at(1) + loop_buf);
+                    }
+                }
+            }
+        }
+        // EW wires
+        if (split_res.at(1).substr(0, 2) == "EW") {
+            if (wire.x == 0) {
+                wire_id = arch->id(split_res.at(1) + "_loop_w");
+            } else {
+                if (wire.x == (arch->gridDimX - 1)) {
+                    wire_id = arch->id(split_res.at(1) + "_loop_e");
+                }
+            }
+        } else {
+            // wrap 2 hop
+            if ((wire.x == (arch->gridDimX - 2) && split_res.at(1).substr(0, 2) == "E2") ||
+                (wire.x == 1 && split_res.at(1).substr(0, 2) == "W2")) {
+                wire_id = arch->id(split_res.at(1) + "_loop1");
+            }
+            // wrap 4 hop
+            if (split_res.at(1).substr(0, 2) == "E8" || split_res.at(1).substr(0, 2) == "W8") {
+                char loop_buf[5 + 2];
+                if (split_res.at(1).substr(0, 2) == "W8") {
+                    if (wire.x < 8) {
+                        snprintf(loop_buf, sizeof(loop_buf), "_loop%1u", wire.x);
+                        wire_id = arch->id(split_res.at(1) + loop_buf);
+                    }
+                } else {
+                    if (arch->gridDimX - 1 - wire.x < 8) {
+                        snprintf(loop_buf, sizeof(loop_buf), "_loop%1u", arch->gridDimX - 1 - wire.x);
+                        wire_id = arch->id(split_res.at(1) + loop_buf);
+                    }
+                }
+            }
+        }
+        // really create decal
+        if (globalWires.count(wire_id) != 0) {
+            snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
+            active_id = arch->id(buf);
+            active.decal = active_id;
+            snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+            inactive_id = arch->id(buf);
+            inactive.decal = inactive_id;
+            active.x = inactive.x = 0;
+            active.y = inactive.y = 0;
+
+            // create if absent
+            if (arch->decal_graphics.count(active_id) == 0) {
+                el.type = GraphicElement::TYPE_LINE;
+                for (auto seg : globalWires.at(wire_id)) {
+                    el.style = GraphicElement::STYLE_ACTIVE;
+                    el.x1 = std::get<0>(seg) + wire.x;
+                    el.y1 = std::get<1>(seg) + arch->gridDimY - 1. - wire.y;
+                    el.x2 = std::get<2>(seg) + wire.x;
+                    el.y2 = std::get<3>(seg) + arch->gridDimY - 1. - wire.y;
+                    arch->addDecalGraphic(active_id, el);
+                    el.style = GraphicElement::STYLE_INACTIVE;
+                    arch->addDecalGraphic(inactive_id, el);
+                }
+            }
+            arch->setWireDecal(wire.name, active, inactive);
+            return;
+        }
+        // clock branches
+        // # of rows is unknown so generate wire ids at runtime
+        if (split_res.at(1).substr(0, 3) == "GBO") {
+            snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
+            active_id = arch->id(buf);
+            active.decal = active_id;
+            inactive_id = IdString();
+            inactive.decal = inactive_id;
+            active.x = inactive.x = 0;
+            active.y = inactive.y = 0;
+
+            float pip_x = PIP_X(id_GBO0);
+            float line_y = WIRE_Y(CLK_GBO0_Y) + arch->gridDimY - 1. - wire.y;
+            float line_0 = WIRE_Y(0) + arch->gridDimY - 1. - wire.y;
+            if (split_res.at(1).at(3) == '1') {
+                pip_x = PIP_X(id_GBO1);
+                line_y = WIRE_Y(CLK_GBO1_Y) + arch->gridDimY - 1. - wire.y;
+            }
+
+            // create if absent
+            if (arch->decal_graphics.count(active_id) == 0) {
+                el.type = GraphicElement::TYPE_LINE;
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = wire.x + pip_x;
+                el.y1 = line_y;
+                el.x2 = el.x1;
+                el.y2 = line_0;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_HIDDEN;
+                arch->addDecalGraphic(inactive_id, el);
+
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = pip_x;
+                el.y1 = line_y;
+                el.x2 = pip_x + arch->gridDimX - 1.;
+                el.y2 = el.y1;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_HIDDEN;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+            arch->setWireDecal(wire.name, active, inactive);
+            return;
+        } else {
+            if (split_res.at(1).substr(0, 2) == "GT") {
+                snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
+                active_id = arch->id(buf);
+                active.decal = active_id;
+                // snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+                // inactive_id = arch->id(buf);
+                inactive_id = IdString();
+                inactive.decal = inactive_id;
+                active.x = inactive.x = 0;
+                active.y = inactive.y = 0;
+
+                float pip_y = PIP_Y(id_GT00);
+                float line_x = WIRE_X(CLK_GT00_X) + wire.x;
+                float line_0 = WIRE_X(0) + wire.x;
+                if (split_res.at(1).at(2) == '1') {
+                    pip_y = PIP_Y(id_GT10);
+                    line_x = WIRE_X(CLK_GT10_X) + wire.x;
+                }
+
+                // create if absent
+                if (arch->decal_graphics.count(active_id) == 0) {
+                    el.type = GraphicElement::TYPE_LINE;
+                    el.style = GraphicElement::STYLE_ACTIVE;
+                    el.x1 = line_x;
+                    el.y1 = pip_y + arch->gridDimY - 1.;
+                    el.x2 = el.x1;
+                    el.y2 = pip_y;
+                    arch->addDecalGraphic(active_id, el);
+                    el.style = GraphicElement::STYLE_HIDDEN;
+                    arch->addDecalGraphic(inactive_id, el);
+
+                    for (int i = 0; i <= arch->gridDimY - 1; ++i) {
+                        el.style = GraphicElement::STYLE_ACTIVE;
+                        el.x1 = line_x;
+                        el.y1 = pip_y + arch->gridDimY - 1. - i;
+                        el.x2 = line_0;
+                        el.y2 = el.y1;
+                        arch->addDecalGraphic(active_id, el);
+                        el.style = GraphicElement::STYLE_HIDDEN;
+                        arch->addDecalGraphic(inactive_id, el);
+                    }
+                }
+                arch->setWireDecal(wire.name, active, inactive);
+                return;
+            } else {
+                if (split_res.at(1).substr(0, 2) == "GB") {
+                    snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
+                    active_id = arch->id(buf);
+                    active.decal = active_id;
+                    snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+                    inactive_id = arch->id(buf);
+                    inactive.decal = inactive_id;
+                    active.x = inactive.x = 0;
+                    active.y = inactive.y = 0;
+
+                    float line_y = WIRE_Y(CLK_GBO0_Y) + arch->gridDimY - 1. - wire.y;
+                    float line_0 = WIRE_Y(0) + arch->gridDimY - 1. - wire.y;
+                    float pip_x = PIP_X(arch->id(split_res.at(1)));
+                    if (split_res.at(1).at(2) >= '4') {
+                        line_y = WIRE_Y(CLK_GBO1_Y) + arch->gridDimY - 1. - wire.y;
+                    }
+
+                    // create if absent
+                    if (arch->decal_graphics.count(active_id) == 0) {
+                        el.type = GraphicElement::TYPE_LINE;
+                        el.style = GraphicElement::STYLE_ACTIVE;
+                        el.x1 = wire.x + pip_x;
+                        el.y1 = line_y;
+                        el.x2 = el.x1;
+                        el.y2 = line_0;
+                        arch->addDecalGraphic(active_id, el);
+                        el.style = GraphicElement::STYLE_INACTIVE;
+                        arch->addDecalGraphic(inactive_id, el);
+                    }
+                    arch->setWireDecal(wire.name, active, inactive);
+                    return;
+                }
+            }
+        }
+    }
+    // std::cout << wire.name.str(arch) << ":" << wire.type.str(arch) << " R" << wire.y + 1 << "C" << wire.x + 1 <<
+    // std::endl;
+}
+
+void gfxCreateBelDecals(Arch *arch)
+{
+    GraphicElement el;
+    // LUTs
+    el.type = GraphicElement::TYPE_BOX;
+    el.style = GraphicElement::STYLE_ACTIVE;
+    el.x1 = lut_x;
+    el.x2 = el.x1 + lut_w;
+    el.y1 = 0.;
+    el.y2 = el.y1 + lut_h;
+    arch->addDecalGraphic(id_DECAL_LUT_ACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_LUTDFF_ACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_LUT_UNUSED_DFF_ACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_ALU_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    arch->addDecalGraphic(id_DECAL_LUT_INACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_LUTDFF_INACTIVE, el);
+    el.x1 = dff_x;
+    el.x2 = el.x1 + dff_w;
+    el.y1 = 0.;
+    el.y2 = el.y1 + lut_h;
+    arch->addDecalGraphic(id_DECAL_LUTDFF_INACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_LUT_UNUSED_DFF_ACTIVE, el);
+    arch->addDecalGraphic(id_DECAL_ALU_ACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_LUTDFF_ACTIVE, el);
+    el.type = GraphicElement::TYPE_LOCAL_LINE;
+    el.x1 = lut_x + 0.33f * lut_w;
+    el.x2 = el.x1 + 0.33f * lut_w;
+    el.y1 = 0.66f * lut_h;
+    el.y2 = el.y1;
+    arch->addDecalGraphic(id_DECAL_ALU_ACTIVE, el);
+    el.y1 = 0.3f * lut_h;
+    el.y2 = el.y1;
+    arch->addDecalGraphic(id_DECAL_ALU_ACTIVE, el);
+    el.x1 = lut_x + 0.5f * lut_w;
+    el.x2 = el.x1;
+    el.y1 = 0.5f * lut_h;
+    el.y2 = el.y1 + 0.33f * lut_h;
+    arch->addDecalGraphic(id_DECAL_ALU_ACTIVE, el);
+
+    // LUT group
+    el.type = GraphicElement::TYPE_BOX;
+    el.style = GraphicElement::STYLE_FRAME;
+    el.x1 = grp_lut_x;
+    el.x2 = el.x1 + grp_lut_w;
+    el.y1 = 0.;
+    el.y2 = el.y1 + grp_lut_h;
+    arch->addDecalGraphic(id_DECAL_GRP_LUT, el);
+
+    // CRU group
+    el.type = GraphicElement::TYPE_BOX;
+    el.style = GraphicElement::STYLE_FRAME;
+    el.x1 = cru_x;
+    el.x2 = el.x1 + cru_w;
+    el.y1 = cru_y;
+    el.y2 = el.y1 + cru_h;
+    arch->addDecalGraphic(id_DECAL_CRU, el);
+
+    // Mux with upper 1 input
+    el.type = GraphicElement::TYPE_LINE;
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.x2 = mux_w;
+    el.y1 = 0.;
+    el.y2 = mux_f;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y1 = el.y2;
+    el.y2 = mux_h - mux_f;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = 0.;
+    el.y1 = el.y2;
+    el.y2 = mux_h;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y1 = mux_h;
+    el.y2 = 0.;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    // 1
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.0038;
+    el.x2 = 0.0118;
+    el.y1 = el.y2 = 0.0598;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = (el.x1 + el.x2) / 2.;
+    el.x2 = el.x1;
+    el.y2 = 0.0808;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = 0.0038;
+    el.y1 = el.y2;
+    el.y2 = 0.0797;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXUPPER_ACTIVE, el);
+
+    // Mux with lower 1 input
+    el.type = GraphicElement::TYPE_LINE;
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.x2 = mux_w;
+    el.y1 = 0.;
+    el.y2 = mux_f;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y1 = el.y2;
+    el.y2 = mux_h - mux_f;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = 0.;
+    el.y1 = el.y2;
+    el.y2 = mux_h;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y1 = mux_h;
+    el.y2 = 0.;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    // 1
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.0038;
+    el.x2 = 0.0118;
+    el.y1 = el.y2 = 0.0140;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = (el.x1 + el.x2) / 2.;
+    el.x2 = el.x1;
+    el.y2 = 0.0352;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = 0.0038;
+    el.y1 = el.y2;
+    el.y2 = 0.0341;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_MUXLOWER_ACTIVE, el);
+
+    // IOB
+    el.type = GraphicElement::TYPE_LINE;
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.x2 = io_w;
+    el.y1 = 0.;
+    el.y2 = el.y1;
+    arch->addDecalGraphic(id_DECAL_IOB_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOB_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y2 = io_h;
+    arch->addDecalGraphic(id_DECAL_IOB_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOB_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.y1 = el.y2;
+    arch->addDecalGraphic(id_DECAL_IOB_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOB_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = el.x1;
+    el.y2 = 0.;
+    arch->addDecalGraphic(id_DECAL_IOB_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOB_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = io_w;
+    el.x2 = io_w * 1.3f;
+    el.y2 = el.y1 = io_h / 2.f;
+    arch->addDecalGraphic(id_DECAL_IOB_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOB_ACTIVE, el);
+
+    // IOBS
+    el.type = GraphicElement::TYPE_LINE;
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.x2 = ios_w;
+    el.y1 = 0.;
+    el.y2 = el.y1;
+    arch->addDecalGraphic(id_DECAL_IOBS_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOBS_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = el.x2;
+    el.y2 = ios_h;
+    arch->addDecalGraphic(id_DECAL_IOBS_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOBS_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = 0.;
+    el.y1 = el.y2;
+    arch->addDecalGraphic(id_DECAL_IOBS_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOBS_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x2 = el.x1;
+    el.y2 = 0.;
+    arch->addDecalGraphic(id_DECAL_IOBS_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOBS_ACTIVE, el);
+    el.style = GraphicElement::STYLE_INACTIVE;
+    el.x1 = ios_w;
+    el.x2 = ios_w * 1.3f;
+    el.y2 = el.y1 = ios_h / 2.f;
+    arch->addDecalGraphic(id_DECAL_IOBS_INACTIVE, el);
+    el.style = GraphicElement::STYLE_ACTIVE;
+    arch->addDecalGraphic(id_DECAL_IOBS_ACTIVE, el);
+}
+
+void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel)
+{
+    DecalXY active, inactive;
+    switch (bel.type.hash()) {
+    case ID_SLICE:
+        active.x = inactive.x = bel.x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + lut_y[bel.z];
+        if (bel.z < 6) {
+            active.decal = id_DECAL_LUTDFF_ACTIVE;
+            inactive.decal = id_DECAL_LUTDFF_INACTIVE;
+        } else {
+            active.decal = id_DECAL_LUT_ACTIVE;
+            inactive.decal = id_DECAL_LUT_INACTIVE;
+        }
+        arch->setBelDecal(bel.name, active, inactive);
+        break;
+    case ID_GW_MUX2_LUT5:
+        active.x = inactive.x = bel.x + mux2lut5_x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - arch->mux_0_z) >> 1];
+        active.decal = id_DECAL_MUXUPPER_ACTIVE;
+        inactive.decal = id_DECAL_MUXUPPER_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        break;
+    case ID_GW_MUX2_LUT6:
+        active.x = inactive.x = bel.x + mux2lut6_x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - arch->mux_0_z) / 5];
+        active.decal = id_DECAL_MUXLOWER_ACTIVE;
+        inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        break;
+    case ID_GW_MUX2_LUT7:
+        active.x = inactive.x = bel.x + mux2lut7_x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut7_y;
+        active.decal = id_DECAL_MUXLOWER_ACTIVE;
+        inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        break;
+    case ID_GW_MUX2_LUT8:
+        active.x = inactive.x = bel.x + mux2lut8_x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut8_y;
+        active.decal = id_DECAL_MUXUPPER_ACTIVE;
+        inactive.decal = id_DECAL_MUXUPPER_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        break;
+    case ID_IOB:
+        active.x = inactive.x = bel.x + io_x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + io_y + bel.z * (2 * io_gap + io_h);
+        active.decal = id_DECAL_IOB_ACTIVE;
+        inactive.decal = id_DECAL_IOB_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        gfxSetIOBWireDecals(arch, bel);
+        break;
+    case ID_IOBS:
+        active.x = inactive.x = bel.x + ios_x + (ios_w + ios_gap_x) * (bel.z % 3);
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + ios_y + (ios_h + ios_gap_y) * (bel.z / 3);
+        active.decal = id_DECAL_IOBS_ACTIVE;
+        inactive.decal = id_DECAL_IOBS_INACTIVE;
+        arch->setBelDecal(bel.name, active, inactive);
+        gfxSetIOBSWireDecals(arch, bel);
+        break;
+    default:
+        break;
+    }
+}
+
+void gfxSetIOBWireDecals(Arch *arch, BelInfo &bel)
+{
+    DecalXY active, inactive;
+    GraphicElement el;
+    char buf[20];
+
+    // set decals for I, O and OE input wires
+    for (auto pi : bel.pins) {
+        WireInfo &wi = arch->wire_info(pi.second.wire);
+        // decal name: wire_port_z_active|inactive
+        snprintf(buf, sizeof(buf), "%s_%s_%u_active", wi.type.c_str(arch), pi.first.c_str(arch), bel.z);
+        IdString active_id = arch->id(buf);
+        active.decal = active_id;
+        snprintf(buf, sizeof(buf), "%s_%s_%u_inactive", wi.type.c_str(arch), pi.first.c_str(arch), bel.z);
+        IdString inactive_id = arch->id(buf);
+        inactive.decal = inactive_id;
+        active.x = inactive.x = bel.x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y;
+        if (arch->decal_graphics.count(active_id) == 0) {
+            el.type = GraphicElement::TYPE_LOCAL_LINE;
+            el.style = GraphicElement::STYLE_ACTIVE;
+            el.x1 = cru_x + cru_w;
+            el.y1 = pipPoint.at(wi.type).second;
+            el.x2 = io_x;
+            el.y2 = portPoint.at(pi.first) + io_y + bel.z * (2 * io_gap + io_h);
+            arch->addDecalGraphic(active_id, el);
+            el.style = GraphicElement::STYLE_INACTIVE;
+            arch->addDecalGraphic(inactive_id, el);
+            for (auto seg : portSign.at(pi.first)) {
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = std::get<0>(seg) + io_x;
+                el.y1 = std::get<1>(seg) + io_y + bel.z * (2 * io_gap + io_h);
+                el.x2 = std::get<2>(seg) + io_x;
+                el.y2 = std::get<3>(seg) + io_y + bel.z * (2 * io_gap + io_h);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+        }
+        arch->setWireDecal(wi.name, active, inactive);
+    }
+}
+
+void gfxSetIOBSWireDecals(Arch *arch, BelInfo &bel)
+{
+    DecalXY active, inactive;
+    GraphicElement el;
+    char buf[20];
+
+    // set decals for I, O and OE input wires
+    for (auto pi : bel.pins) {
+        WireInfo &wi = arch->wire_info(pi.second.wire);
+        // decal name: ios_wire_port_z_active|inactive
+        snprintf(buf, sizeof(buf), "ios_%s_%s_%u_active", wi.type.c_str(arch), pi.first.c_str(arch), bel.z);
+        IdString active_id = arch->id(buf);
+        active.decal = active_id;
+        snprintf(buf, sizeof(buf), "ios_%s_%s_%u_inactive", wi.type.c_str(arch), pi.first.c_str(arch), bel.z);
+        IdString inactive_id = arch->id(buf);
+        inactive.decal = inactive_id;
+        active.x = inactive.x = bel.x;
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y;
+        if (arch->decal_graphics.count(active_id) == 0) {
+            // leftmost wires
+            el.type = GraphicElement::TYPE_LOCAL_LINE;
+            if (bel.z % 3 == 0) {
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = cru_x + cru_w;
+                el.y1 = pipPoint.at(wi.type).second;
+                el.x2 = ios_x;
+                el.y2 = ios_scl * portPoint.at(pi.first) + ios_y + (ios_h + ios_gap_y) * (bel.z / 3);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            } else {
+                float col = (bel.z % 3) - 1;
+                float rel_port = portPoint.at(pi.first) / io_h;
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = cru_x + cru_w;
+                el.y1 = pipPoint.at(wi.type).second;
+                el.x2 = ios_x * (0.97 - 0.02 * col);
+                el.y2 = (rel_port + col) * 0.5 * ios_gap_y + ios_y + ios_h + (ios_h + ios_gap_y) * (bel.z / 3);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = ios_x + (ios_w + ios_gap_x) * (col + 1) - ios_gap_x + ios_w * 0.3 +
+                        rel_port * (ios_gap_x - 0.3 * ios_w);
+                el.y1 = el.y2;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x2 = el.x1;
+                el.y2 = ios_scl * portPoint.at(pi.first) + ios_y + (ios_h + ios_gap_y) * (bel.z / 3);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = ios_x + (ios_w + ios_gap_x) * (col + 1);
+                el.y1 = el.y2;
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+                el.style = GraphicElement::STYLE_ACTIVE;
+            }
+            // signs
+            for (auto seg : portSign.at(pi.first)) {
+                el.style = GraphicElement::STYLE_ACTIVE;
+                el.x1 = ios_scl * std::get<0>(seg) + ios_x + (ios_w + ios_gap_x) * (bel.z % 3);
+                el.y1 = ios_scl * std::get<1>(seg) + ios_y + (ios_h + ios_gap_y) * (bel.z / 3);
+                el.x2 = ios_scl * std::get<2>(seg) + ios_x + (ios_w + ios_gap_x) * (bel.z % 3);
+                el.y2 = ios_scl * std::get<3>(seg) + ios_y + (ios_h + ios_gap_y) * (bel.z / 3);
+                arch->addDecalGraphic(active_id, el);
+                el.style = GraphicElement::STYLE_INACTIVE;
+                arch->addDecalGraphic(inactive_id, el);
+            }
+        }
+        arch->setWireDecal(wi.name, active, inactive);
+    }
+}
+
+DecalXY gfxGetLutGroupDecalXY(int x, int y, int z)
+{
+    DecalXY decalxy;
+    decalxy.decal = id_DECAL_GRP_LUT;
+    decalxy.x = x;
+    decalxy.y = y + grp_lut_y[z];
+    return decalxy;
+}
+
+DecalXY gfxGetCruGroupDecalXY(int x, int y)
+{
+    DecalXY decalxy;
+    decalxy.decal = id_DECAL_CRU;
+    decalxy.x = x;
+    decalxy.y = y;
+    return decalxy;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gowin/gfx.h b/gowin/gfx.h
new file mode 100644
index 0000000000..574d73106a
--- /dev/null
+++ b/gowin/gfx.h
@@ -0,0 +1,4935 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef GFX_H
+#define GFX_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// LUTs
+const float lut_w = 0.6732 - 0.6386;
+const float lut_h = 0.9392 - 0.9074;
+const float lut_x = 0.6386;
+const float lut_y[] = {1. - 0.9392, 1. - 0.8870, 1. - 0.7864, 1. - 0.7321,
+                       1. - 0.6399, 1. - 0.5847, 1. - 0.5068, 1. - 0.4503};
+const float dff_w = 0.0580;
+const float dff_x = 0.6821;
+const float grp_lut_w = 0.1399;
+const float grp_lut_h = 0.0954;
+const float grp_lut_x = 0.6284;
+const float grp_lut_y[] = {1. - 0.9440, 1. - 0.7915, 1. - 0.6442, 1. - 0.5101};
+
+// mux
+const float mux_w = 0.8134 - 0.7899;
+const float mux_f = 0.9450 - 0.9358;
+const float mux_h = grp_lut_h;
+
+const float mux2lut5_x = 0.7900;
+const float mux2lut5_y[] = {grp_lut_y[0], grp_lut_y[1], grp_lut_y[2], grp_lut_y[3]};
+const float mux2lut6_x = 0.8378;
+const float mux2lut6_y[] = {1. - 0.9261, 1. - 0.6205};
+const float mux2lut7_x = 0.8859;
+const float mux2lut7_y = 1. - 0.7870;
+const float mux2lut8_x = 0.9337;
+const float mux2lut8_y = 1. - 0.8098;
+
+// pip
+enum CruSide
+{
+    Top,
+    Bottom,
+    Left,
+    Right,
+    Center
+};
+const float cru_x = 0.2568;
+const float cru_y = 1. - 0.9783;
+const float cru_w = 0.6010 - cru_x;
+const float cru_h = 1. - cru_y - 0.3742;
+
+const float lut_A_off = 1. - 0.9107 - lut_y[0];
+const float lut_D_off = lut_h - lut_A_off;
+const float lut_B_off = lut_A_off - (lut_h - lut_D_off) / 3.;
+const float lut_C_off = lut_D_off + (lut_h - lut_D_off) / 3.;
+
+const float right_wire_dist = (grp_lut_y[1] - grp_lut_y[0] - grp_lut_h) / 11.;
+const float left_wire_dist = cru_h / 100.;
+const float top_wire_dist = cru_w / 100.;
+const float clk_ce_set_vdist = (lut_y[1] - lut_y[0] - lut_h) / 4.;
+
+const float sn_dist = cru_x / 125.;
+const float ew_dist = (1. - cru_y - cru_h) / 130.;
+const float wrap_len = 0.02f;
+const float spine_pip_off = 0.11f;
+
+const float io_x = cru_x + cru_w + 0.1;
+const float io_w = (1. - io_x) / 3.;
+const float io_gap = 0.03;
+const float io_h = (cru_h - 4. * io_gap) / 2.;
+const float io_y = cru_y + io_gap;
+
+const float ios_scl = 0.5;
+const float ios_h = ios_scl * io_h;
+const float ios_w = ios_scl * io_w;
+const float ios_gap_y = io_gap;
+const float ios_gap_x = io_gap * 1.4;
+const float ios_x = io_x;
+const float ios_y = ios_scl * io_y;
+
+const dict<IdString, float> portPoint = {
+        {id_O, 3. * io_h / 4.},
+        {id_I, 2. * io_h / 4.},
+        {id_OEN, 1. * io_h / 4.},
+};
+
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> portSign = {
+        {id_O,
+         {{io_h / 14. * 1.33, portPoint.at(id_O) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14., io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 2.,
+           portPoint.at(id_O) - io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14.},
+          {io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.,
+           portPoint.at(id_O) + io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 1.33,
+           portPoint.at(id_O) + io_h / 14.}}},
+        {id_I,
+         {{io_h / 14., portPoint.at(id_I) + io_h / 14., 2. * io_h / 14., portPoint.at(id_I) + io_h / 14.},
+          {io_h / 14. * 1.5, portPoint.at(id_I) + io_h / 14., 1. * io_h / 14. * 1.5, portPoint.at(id_I) - io_h / 14.},
+          {io_h / 14., portPoint.at(id_I) - io_h / 14., 2. * io_h / 14., portPoint.at(id_I) - io_h / 14.}}},
+        {id_OEN,
+         {{io_h / 14. * 1.33, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.,
+           portPoint.at(id_OEN) + io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 2.,
+           portPoint.at(id_OEN) - io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.66,
+           portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.,
+           portPoint.at(id_OEN) - io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.,
+           portPoint.at(id_OEN) + io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 1.33,
+           portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + 0., io_h / 14. * 3.2, portPoint.at(id_OEN) + 0.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14.}}},
+};
+
+const dict<IdString, float> spineY = {
+        {id_SPINE0, 1. - 1. * ew_dist},  {id_SPINE1, 1. - 2. * ew_dist},  {id_SPINE2, 1. - 3. * ew_dist},
+        {id_SPINE3, 1. - 4. * ew_dist},  {id_SPINE4, 1. - 5. * ew_dist},  {id_SPINE5, 1. - 6. * ew_dist},
+        {id_SPINE6, 1. - 7. * ew_dist},  {id_SPINE7, 1. - 8. * ew_dist},  {id_SPINE8, 1. - 1. * ew_dist},
+        {id_SPINE9, 1. - 2. * ew_dist},  {id_SPINE10, 1. - 3. * ew_dist}, {id_SPINE11, 1. - 4. * ew_dist},
+        {id_SPINE12, 1. - 5. * ew_dist}, {id_SPINE13, 1. - 6. * ew_dist}, {id_SPINE14, 1. - 7. * ew_dist},
+        {id_SPINE15, 1. - 8. * ew_dist}, {id_SPINE16, 1. - 1. * ew_dist}, {id_SPINE17, 1. - 2. * ew_dist},
+        {id_SPINE18, 1. - 3. * ew_dist}, {id_SPINE19, 1. - 4. * ew_dist}, {id_SPINE20, 1. - 5. * ew_dist},
+        {id_SPINE21, 1. - 6. * ew_dist}, {id_SPINE22, 1. - 7. * ew_dist}, {id_SPINE23, 1. - 8. * ew_dist},
+        {id_SPINE24, 1. - 1. * ew_dist}, {id_SPINE25, 1. - 2. * ew_dist}, {id_SPINE26, 1. - 3. * ew_dist},
+        {id_SPINE27, 1. - 4. * ew_dist}, {id_SPINE28, 1. - 5. * ew_dist}, {id_SPINE29, 1. - 6. * ew_dist},
+        {id_SPINE30, 1. - 7. * ew_dist}, {id_SPINE31, 1. - 8. * ew_dist},
+};
+
+const dict<IdString, std::pair<CruSide, float>> pipPoint = {
+        {id_X01, {Center, cru_y + 1. * cru_h / 9.}},
+        {id_X02, {Center, cru_y + 2. * cru_h / 9.}},
+        {id_X03, {Center, cru_y + 3. * cru_h / 9.}},
+        {id_X04, {Center, cru_y + 4. * cru_h / 9.}},
+        {id_X05, {Center, cru_y + 5. * cru_h / 9.}},
+        {id_X06, {Center, cru_y + 6. * cru_h / 9.}},
+        {id_X07, {Center, cru_y + 7. * cru_h / 9.}},
+        {id_X08, {Center, cru_y + 8. * cru_h / 9.}},
+        // LUT inputs
+        {id_A0, {Right, lut_y[0] + lut_A_off}},
+        {id_B0, {Right, lut_y[0] + lut_B_off}},
+        {id_C0, {Right, lut_y[0] + lut_C_off}},
+        {id_D0, {Right, lut_y[0] + lut_D_off}},
+        {id_A1, {Right, lut_y[1] + lut_A_off}},
+        {id_B1, {Right, lut_y[1] + lut_B_off}},
+        {id_C1, {Right, lut_y[1] + lut_C_off}},
+        {id_D1, {Right, lut_y[1] + lut_D_off}},
+        {id_A2, {Right, lut_y[2] + lut_A_off}},
+        {id_B2, {Right, lut_y[2] + lut_B_off}},
+        {id_C2, {Right, lut_y[2] + lut_C_off}},
+        {id_D2, {Right, lut_y[2] + lut_D_off}},
+        {id_A3, {Right, lut_y[3] + lut_A_off}},
+        {id_B3, {Right, lut_y[3] + lut_B_off}},
+        {id_C3, {Right, lut_y[3] + lut_C_off}},
+        {id_D3, {Right, lut_y[3] + lut_D_off}},
+        {id_A4, {Right, lut_y[4] + lut_A_off}},
+        {id_B4, {Right, lut_y[4] + lut_B_off}},
+        {id_C4, {Right, lut_y[4] + lut_C_off}},
+        {id_D4, {Right, lut_y[4] + lut_D_off}},
+        {id_A5, {Right, lut_y[5] + lut_A_off}},
+        {id_B5, {Right, lut_y[5] + lut_B_off}},
+        {id_C5, {Right, lut_y[5] + lut_C_off}},
+        {id_D5, {Right, lut_y[5] + lut_D_off}},
+        {id_A6, {Right, lut_y[6] + lut_A_off}},
+        {id_B6, {Right, lut_y[6] + lut_B_off}},
+        {id_C6, {Right, lut_y[6] + lut_C_off}},
+        {id_D6, {Right, lut_y[6] + lut_D_off}},
+        {id_A7, {Right, lut_y[7] + lut_A_off}},
+        {id_B7, {Right, lut_y[7] + lut_B_off}},
+        {id_C7, {Right, lut_y[7] + lut_C_off}},
+        {id_D7, {Right, lut_y[7] + lut_D_off}},
+        // wires below LUT0
+        {id_Q0, {Right, grp_lut_y[0] - right_wire_dist}},
+        {id_F0, {Right, grp_lut_y[0] - 2. * right_wire_dist}},
+        {id_OF3, {Right, grp_lut_y[0] - 3. * right_wire_dist}},
+        // wires between LUT1 and LUT2
+        {id_Q2, {Right, grp_lut_y[1] - right_wire_dist}},
+        {id_F2, {Right, grp_lut_y[1] - 2. * right_wire_dist}},
+        {id_OF2, {Right, grp_lut_y[1] - 3. * right_wire_dist}},
+        {id_OF1, {Right, grp_lut_y[1] - 4. * right_wire_dist}},
+        {id_OF0, {Right, grp_lut_y[1] - 5. * right_wire_dist}},
+        {id_SEL1, {Right, grp_lut_y[1] - 6. * right_wire_dist}},
+        {id_OF7, {Right, grp_lut_y[1] - 7. * right_wire_dist}},
+        {id_SEL0, {Right, grp_lut_y[1] - 8. * right_wire_dist}},
+        {id_F1, {Right, grp_lut_y[1] - 9. * right_wire_dist}},
+        {id_Q1, {Right, grp_lut_y[1] - 10. * right_wire_dist}},
+        // wires between LUT3 and LUT4
+        {id_Q4, {Right, grp_lut_y[2] - right_wire_dist}},
+        {id_F4, {Right, grp_lut_y[2] - 2. * right_wire_dist}},
+        {id_OF4, {Right, grp_lut_y[2] - 3. * right_wire_dist}},
+        {id_OF5, {Right, grp_lut_y[2] - 4. * right_wire_dist}},
+        {id_SEL7, {Right, grp_lut_y[2] - 5. * right_wire_dist}},
+        {id_SEL3, {Right, grp_lut_y[2] - 6. * right_wire_dist}},
+        {id_SEL2, {Right, grp_lut_y[2] - 7. * right_wire_dist}},
+        {id_F3, {Right, grp_lut_y[2] - 8. * right_wire_dist}},
+        {id_Q3, {Right, grp_lut_y[2] - 9. * right_wire_dist}},
+        // wires between LUT5 and LUT6
+        {id_F6, {Right, grp_lut_y[3] - right_wire_dist}},
+        {id_SEL5, {Right, grp_lut_y[3] - 2. * right_wire_dist}},
+        {id_SEL4, {Right, grp_lut_y[3] - 4. * right_wire_dist}},
+        {id_F5, {Right, grp_lut_y[3] - 5. * right_wire_dist}},
+        {id_Q5, {Right, grp_lut_y[3] - 6. * right_wire_dist}},
+        // Q6, Q7 --- IOB
+        {id_Q6, {Right, grp_lut_y[3] + grp_lut_h * 0.33}},
+        {id_Q7, {Right, grp_lut_y[3] + grp_lut_h * 0.66}},
+        // wires above LUT7
+        {id_F7, {Right, grp_lut_y[3] + grp_lut_h + right_wire_dist}},
+        {id_SEL6, {Right, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist}},
+        {id_OF6, {Right, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist}},
+        // DI0-5
+        {id_DI5, {Right, cru_y + cru_h - 0.5 * right_wire_dist}},
+        {id_DI4, {Right, cru_y + cru_h - 1. * right_wire_dist}},
+        {id_DI3, {Right, cru_y + cru_h - 1.5 * right_wire_dist}},
+        {id_DI2, {Right, cru_y + cru_h - 2. * right_wire_dist}},
+        {id_DI1, {Right, cru_y + cru_h - 2.5 * right_wire_dist}},
+        {id_DI0, {Right, cru_y + cru_h - 3. * right_wire_dist}},
+        // Q6
+        // CLK, CE, SET-RESET
+        {id_CLK0, {Right, lut_y[1] - clk_ce_set_vdist}},
+        {id_CE0, {Right, lut_y[1] - 2. * clk_ce_set_vdist}},
+        {id_LSR0, {Right, lut_y[1] - 3. * clk_ce_set_vdist}},
+        {id_CLK1, {Right, lut_y[3] - clk_ce_set_vdist}},
+        {id_CE1, {Right, lut_y[3] - 2. * clk_ce_set_vdist}},
+        {id_LSR1, {Right, lut_y[3] - 3. * clk_ce_set_vdist}},
+        {id_CLK2, {Right, lut_y[5] - clk_ce_set_vdist}},
+        {id_CE2, {Right, lut_y[5] - 2. * clk_ce_set_vdist}},
+        {id_LSR2, {Right, lut_y[5] - 3. * clk_ce_set_vdist}},
+        // SN
+        // 1 hop
+        {id_S100, {Left, cru_y + 1. * left_wire_dist}},
+        {id_S101, {Left, cru_y + 2. * left_wire_dist}},
+        {id_S130, {Left, cru_y + 3. * left_wire_dist}},
+        {id_S131, {Left, cru_y + 4. * left_wire_dist}},
+        {id_N101, {Left, cru_y + 5. * left_wire_dist}},
+        {id_N100, {Left, cru_y + 6. * left_wire_dist}},
+        {id_N131, {Left, cru_y + 7. * left_wire_dist}},
+        {id_N130, {Left, cru_y + 8. * left_wire_dist}},
+        // 1 hop SN
+        {id_N111, {Left, cru_y + 9. * left_wire_dist}},
+        {id_SN10, {Left, cru_y + 10. * left_wire_dist}},
+        {id_S111, {Left, cru_y + 11. * left_wire_dist}},
+        {id_N121, {Left, cru_y + 12. * left_wire_dist}},
+        {id_SN20, {Left, cru_y + 13. * left_wire_dist}},
+        {id_S121, {Left, cru_y + 14. * left_wire_dist}},
+        // 2 hop
+        {id_S200, {Left, cru_y + 15. * left_wire_dist}},
+        {id_S201, {Left, cru_y + 16. * left_wire_dist}},
+        {id_N202, {Left, cru_y + 17. * left_wire_dist}},
+        {id_S202, {Left, cru_y + 18. * left_wire_dist}},
+        {id_N201, {Left, cru_y + 19. * left_wire_dist}},
+        {id_N200, {Left, cru_y + 20. * left_wire_dist}},
+
+        {id_S210, {Left, cru_y + 21. * left_wire_dist}},
+        {id_S211, {Left, cru_y + 22. * left_wire_dist}},
+        {id_N212, {Left, cru_y + 23. * left_wire_dist}},
+        {id_S212, {Left, cru_y + 24. * left_wire_dist}},
+        {id_N211, {Left, cru_y + 25. * left_wire_dist}},
+        {id_N210, {Left, cru_y + 26. * left_wire_dist}},
+
+        {id_S220, {Left, cru_y + 27. * left_wire_dist}},
+        {id_S221, {Left, cru_y + 28. * left_wire_dist}},
+        {id_N222, {Left, cru_y + 29. * left_wire_dist}},
+        {id_S222, {Left, cru_y + 30. * left_wire_dist}},
+        {id_N221, {Left, cru_y + 31. * left_wire_dist}},
+        {id_N220, {Left, cru_y + 32. * left_wire_dist}},
+
+        {id_S230, {Left, cru_y + 33. * left_wire_dist}},
+        {id_S231, {Left, cru_y + 34. * left_wire_dist}},
+        {id_N232, {Left, cru_y + 35. * left_wire_dist}},
+        {id_S232, {Left, cru_y + 36. * left_wire_dist}},
+        {id_N231, {Left, cru_y + 37. * left_wire_dist}},
+        {id_N230, {Left, cru_y + 38. * left_wire_dist}},
+
+        {id_S240, {Left, cru_y + 39. * left_wire_dist}},
+        {id_S241, {Left, cru_y + 40. * left_wire_dist}},
+        {id_N242, {Left, cru_y + 41. * left_wire_dist}},
+        {id_S242, {Left, cru_y + 42. * left_wire_dist}},
+        {id_N241, {Left, cru_y + 43. * left_wire_dist}},
+        {id_N240, {Left, cru_y + 44. * left_wire_dist}},
+
+        {id_S250, {Left, cru_y + 45. * left_wire_dist}},
+        {id_S251, {Left, cru_y + 46. * left_wire_dist}},
+        {id_N252, {Left, cru_y + 47. * left_wire_dist}},
+        {id_S252, {Left, cru_y + 48. * left_wire_dist}},
+        {id_N251, {Left, cru_y + 49. * left_wire_dist}},
+        {id_N250, {Left, cru_y + 50. * left_wire_dist}},
+
+        {id_S260, {Left, cru_y + 51. * left_wire_dist}},
+        {id_S261, {Left, cru_y + 52. * left_wire_dist}},
+        {id_N262, {Left, cru_y + 53. * left_wire_dist}},
+        {id_S262, {Left, cru_y + 54. * left_wire_dist}},
+        {id_N261, {Left, cru_y + 55. * left_wire_dist}},
+        {id_N260, {Left, cru_y + 56. * left_wire_dist}},
+
+        {id_S270, {Left, cru_y + 57. * left_wire_dist}},
+        {id_S271, {Left, cru_y + 58. * left_wire_dist}},
+        {id_N272, {Left, cru_y + 59. * left_wire_dist}},
+        {id_S272, {Left, cru_y + 60. * left_wire_dist}},
+        {id_N271, {Left, cru_y + 61. * left_wire_dist}},
+        {id_N270, {Left, cru_y + 62. * left_wire_dist}},
+
+        // Clocks
+        {id_GT10, {Left, cru_y + 63. * left_wire_dist}},
+        {id_GT00, {Left, cru_y + 68. * left_wire_dist}},
+
+        // 4 hop
+        {id_N808, {Left, cru_y + 73. * left_wire_dist}},
+        {id_S800, {Left, cru_y + 74. * left_wire_dist}},
+        {id_S804, {Left, cru_y + 75. * left_wire_dist}},
+        {id_N804, {Left, cru_y + 76. * left_wire_dist}},
+        {id_N800, {Left, cru_y + 77. * left_wire_dist}},
+        {id_S808, {Left, cru_y + 78. * left_wire_dist}},
+
+        {id_N818, {Left, cru_y + 79. * left_wire_dist}},
+        {id_S810, {Left, cru_y + 80. * left_wire_dist}},
+        {id_S814, {Left, cru_y + 81. * left_wire_dist}},
+        {id_N814, {Left, cru_y + 82. * left_wire_dist}},
+        {id_N810, {Left, cru_y + 83. * left_wire_dist}},
+        {id_S818, {Left, cru_y + 84. * left_wire_dist}},
+
+        {id_N828, {Left, cru_y + 85. * left_wire_dist}},
+        {id_S820, {Left, cru_y + 86. * left_wire_dist}},
+        {id_S824, {Left, cru_y + 87. * left_wire_dist}},
+        {id_N824, {Left, cru_y + 88. * left_wire_dist}},
+        {id_N820, {Left, cru_y + 89. * left_wire_dist}},
+        {id_S828, {Left, cru_y + 90. * left_wire_dist}},
+
+        {id_N838, {Left, cru_y + 91. * left_wire_dist}},
+        {id_S830, {Left, cru_y + 92. * left_wire_dist}},
+        {id_S834, {Left, cru_y + 93. * left_wire_dist}},
+        {id_N834, {Left, cru_y + 94. * left_wire_dist}},
+        {id_N830, {Left, cru_y + 95. * left_wire_dist}},
+        {id_S838, {Left, cru_y + 96. * left_wire_dist}},
+
+        // EW
+        // 1 hop
+        {id_E101, {Top, cru_x + 1. * top_wire_dist}},
+        {id_E100, {Top, cru_x + 2. * top_wire_dist}},
+        {id_E131, {Top, cru_x + 3. * top_wire_dist}},
+        {id_E130, {Top, cru_x + 4. * top_wire_dist}},
+        {id_W100, {Top, cru_x + 5. * top_wire_dist}},
+        {id_W101, {Top, cru_x + 6. * top_wire_dist}},
+        {id_W130, {Top, cru_x + 7. * top_wire_dist}},
+        {id_W131, {Top, cru_x + 8. * top_wire_dist}},
+        // 1 hop EW
+        {id_E111, {Top, cru_x + 9. * top_wire_dist}},
+        {id_EW10, {Top, cru_x + 10. * top_wire_dist}},
+        {id_W111, {Top, cru_x + 11. * top_wire_dist}},
+        {id_E121, {Top, cru_x + 12. * top_wire_dist}},
+        {id_EW20, {Top, cru_x + 13. * top_wire_dist}},
+        {id_W121, {Top, cru_x + 14. * top_wire_dist}},
+        // 2 hop
+        {id_E202, {Top, cru_x + 15. * top_wire_dist}},
+        {id_E201, {Top, cru_x + 16. * top_wire_dist}},
+        {id_W200, {Top, cru_x + 17. * top_wire_dist}},
+        {id_E200, {Top, cru_x + 18. * top_wire_dist}},
+        {id_W201, {Top, cru_x + 19. * top_wire_dist}},
+        {id_W202, {Top, cru_x + 20. * top_wire_dist}},
+
+        {id_E212, {Top, cru_x + 21. * top_wire_dist}},
+        {id_E211, {Top, cru_x + 22. * top_wire_dist}},
+        {id_W210, {Top, cru_x + 23. * top_wire_dist}},
+        {id_E210, {Top, cru_x + 24. * top_wire_dist}},
+        {id_W211, {Top, cru_x + 25. * top_wire_dist}},
+        {id_W212, {Top, cru_x + 26. * top_wire_dist}},
+
+        {id_E222, {Top, cru_x + 27. * top_wire_dist}},
+        {id_E221, {Top, cru_x + 28. * top_wire_dist}},
+        {id_W220, {Top, cru_x + 29. * top_wire_dist}},
+        {id_E220, {Top, cru_x + 30. * top_wire_dist}},
+        {id_W221, {Top, cru_x + 31. * top_wire_dist}},
+        {id_W222, {Top, cru_x + 32. * top_wire_dist}},
+
+        {id_E232, {Top, cru_x + 33. * top_wire_dist}},
+        {id_E231, {Top, cru_x + 34. * top_wire_dist}},
+        {id_W230, {Top, cru_x + 35. * top_wire_dist}},
+        {id_E230, {Top, cru_x + 36. * top_wire_dist}},
+        {id_W231, {Top, cru_x + 37. * top_wire_dist}},
+        {id_W232, {Top, cru_x + 38. * top_wire_dist}},
+
+        {id_E242, {Top, cru_x + 39. * top_wire_dist}},
+        {id_E241, {Top, cru_x + 40. * top_wire_dist}},
+        {id_W240, {Top, cru_x + 41. * top_wire_dist}},
+        {id_E240, {Top, cru_x + 42. * top_wire_dist}},
+        {id_W241, {Top, cru_x + 43. * top_wire_dist}},
+        {id_W242, {Top, cru_x + 44. * top_wire_dist}},
+
+        {id_E252, {Top, cru_x + 45. * top_wire_dist}},
+        {id_E251, {Top, cru_x + 46. * top_wire_dist}},
+        {id_W250, {Top, cru_x + 47. * top_wire_dist}},
+        {id_E250, {Top, cru_x + 48. * top_wire_dist}},
+        {id_W251, {Top, cru_x + 49. * top_wire_dist}},
+        {id_W252, {Top, cru_x + 50. * top_wire_dist}},
+
+        {id_E262, {Top, cru_x + 51. * top_wire_dist}},
+        {id_E261, {Top, cru_x + 52. * top_wire_dist}},
+        {id_W260, {Top, cru_x + 53. * top_wire_dist}},
+        {id_E260, {Top, cru_x + 54. * top_wire_dist}},
+        {id_W261, {Top, cru_x + 55. * top_wire_dist}},
+        {id_W262, {Top, cru_x + 56. * top_wire_dist}},
+
+        {id_E272, {Top, cru_x + 57. * top_wire_dist}},
+        {id_E271, {Top, cru_x + 58. * top_wire_dist}},
+        {id_W270, {Top, cru_x + 59. * top_wire_dist}},
+        {id_E270, {Top, cru_x + 60. * top_wire_dist}},
+        {id_W271, {Top, cru_x + 61. * top_wire_dist}},
+        {id_W272, {Top, cru_x + 62. * top_wire_dist}},
+
+        // Global taps -> bracnhes
+        {id_GBO0, {Top, cru_x + 63. * top_wire_dist}},
+        {id_GB00, {Top, cru_x + 64. * top_wire_dist}},
+        {id_GB10, {Top, cru_x + 65. * top_wire_dist}},
+        {id_GB20, {Top, cru_x + 66. * top_wire_dist}},
+        {id_GB30, {Top, cru_x + 67. * top_wire_dist}},
+        {id_GBO1, {Top, cru_x + 68. * top_wire_dist}},
+        {id_GB40, {Top, cru_x + 68. * top_wire_dist}},
+        {id_GB50, {Top, cru_x + 69. * top_wire_dist}},
+        {id_GB60, {Top, cru_x + 70. * top_wire_dist}},
+        {id_GB70, {Top, cru_x + 71. * top_wire_dist}},
+
+        // 4 hop
+        {id_E808, {Top, cru_x + 72. * top_wire_dist}},
+        {id_W800, {Top, cru_x + 73. * top_wire_dist}},
+        {id_W804, {Top, cru_x + 74. * top_wire_dist}},
+        {id_E804, {Top, cru_x + 75. * top_wire_dist}},
+        {id_E800, {Top, cru_x + 76. * top_wire_dist}},
+        {id_W808, {Top, cru_x + 77. * top_wire_dist}},
+
+        {id_E818, {Top, cru_x + 78. * top_wire_dist}},
+        {id_W810, {Top, cru_x + 79. * top_wire_dist}},
+        {id_W814, {Top, cru_x + 80. * top_wire_dist}},
+        {id_E814, {Top, cru_x + 81. * top_wire_dist}},
+        {id_E810, {Top, cru_x + 82. * top_wire_dist}},
+        {id_W818, {Top, cru_x + 83. * top_wire_dist}},
+
+        {id_E828, {Top, cru_x + 84. * top_wire_dist}},
+        {id_W820, {Top, cru_x + 85. * top_wire_dist}},
+        {id_W824, {Top, cru_x + 86. * top_wire_dist}},
+        {id_E824, {Top, cru_x + 87. * top_wire_dist}},
+        {id_E820, {Top, cru_x + 88. * top_wire_dist}},
+        {id_W828, {Top, cru_x + 89. * top_wire_dist}},
+
+        {id_E838, {Top, cru_x + 90. * top_wire_dist}},
+        {id_W830, {Top, cru_x + 91. * top_wire_dist}},
+        {id_W834, {Top, cru_x + 92. * top_wire_dist}},
+        {id_E834, {Top, cru_x + 93. * top_wire_dist}},
+        {id_E830, {Top, cru_x + 94. * top_wire_dist}},
+        {id_W838, {Top, cru_x + 95. * top_wire_dist}},
+
+};
+
+// wire
+const std::vector<IdString> decalless_wires = {id_X01, id_X02, id_X03, id_X04, id_X05, id_X06, id_X07};
+
+const float clk_ce_set_hdist = dff_w / 4.;
+const float dff_f_x = (grp_lut_x + grp_lut_w + dff_x + dff_w) / 2.;
+const float mux5i_x = (grp_lut_x + grp_lut_w + mux2lut5_x) / 2.;
+
+// id, {x1, y1, x2, y2}
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> sliceLocalWires = {
+        // dff
+        {id_CLK0,
+         {{cru_x + cru_w, pipPoint.at(id_CLK0).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK0).second},
+          {dff_x + clk_ce_set_hdist, lut_y[1], dff_x + clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_CE0,
+         {{cru_x + cru_w, pipPoint.at(id_CE0).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE0).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[1], dff_x + 2. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_LSR0,
+         {{cru_x + cru_w, pipPoint.at(id_LSR0).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR0).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[1], dff_x + 3. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_CLK1,
+         {{cru_x + cru_w, pipPoint.at(id_CLK1).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK1).second},
+          {dff_x + clk_ce_set_hdist, lut_y[3], dff_x + clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_CE1,
+         {{cru_x + cru_w, pipPoint.at(id_CE1).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE1).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[3], dff_x + 2. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_LSR1,
+         {{cru_x + cru_w, pipPoint.at(id_LSR1).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR1).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[3], dff_x + 3. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_CLK2,
+         {{cru_x + cru_w, pipPoint.at(id_CLK2).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK2).second},
+          {dff_x + clk_ce_set_hdist, lut_y[5], dff_x + clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        {id_CE2,
+         {{cru_x + cru_w, pipPoint.at(id_CE2).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE2).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[5], dff_x + 2. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        {id_LSR2,
+         {{cru_x + cru_w, pipPoint.at(id_LSR2).second, dff_x + 3 * clk_ce_set_hdist, pipPoint.at(id_LSR2).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[5], dff_x + 3. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        // lut
+        {id_A0, {{cru_x + cru_w, lut_y[0] + lut_A_off, lut_x, lut_y[0] + lut_A_off}}},
+        {id_B0, {{cru_x + cru_w, lut_y[0] + lut_B_off, lut_x, lut_y[0] + lut_B_off}}},
+        {id_C0, {{cru_x + cru_w, lut_y[0] + lut_C_off, lut_x, lut_y[0] + lut_C_off}}},
+        {id_D0, {{cru_x + cru_w, lut_y[0] + lut_D_off, lut_x, lut_y[0] + lut_D_off}}},
+        {id_A1, {{cru_x + cru_w, lut_y[1] + lut_A_off, lut_x, lut_y[1] + lut_A_off}}},
+        {id_B1, {{cru_x + cru_w, lut_y[1] + lut_B_off, lut_x, lut_y[1] + lut_B_off}}},
+        {id_C1, {{cru_x + cru_w, lut_y[1] + lut_C_off, lut_x, lut_y[1] + lut_C_off}}},
+        {id_D1, {{cru_x + cru_w, lut_y[1] + lut_D_off, lut_x, lut_y[1] + lut_D_off}}},
+        {id_A2, {{cru_x + cru_w, lut_y[2] + lut_A_off, lut_x, lut_y[2] + lut_A_off}}},
+        {id_B2, {{cru_x + cru_w, lut_y[2] + lut_B_off, lut_x, lut_y[2] + lut_B_off}}},
+        {id_C2, {{cru_x + cru_w, lut_y[2] + lut_C_off, lut_x, lut_y[2] + lut_C_off}}},
+        {id_D2, {{cru_x + cru_w, lut_y[2] + lut_D_off, lut_x, lut_y[2] + lut_D_off}}},
+        {id_A3, {{cru_x + cru_w, lut_y[3] + lut_A_off, lut_x, lut_y[3] + lut_A_off}}},
+        {id_B3, {{cru_x + cru_w, lut_y[3] + lut_B_off, lut_x, lut_y[3] + lut_B_off}}},
+        {id_C3, {{cru_x + cru_w, lut_y[3] + lut_C_off, lut_x, lut_y[3] + lut_C_off}}},
+        {id_D3, {{cru_x + cru_w, lut_y[3] + lut_D_off, lut_x, lut_y[3] + lut_D_off}}},
+        {id_A4, {{cru_x + cru_w, lut_y[4] + lut_A_off, lut_x, lut_y[4] + lut_A_off}}},
+        {id_B4, {{cru_x + cru_w, lut_y[4] + lut_B_off, lut_x, lut_y[4] + lut_B_off}}},
+        {id_C4, {{cru_x + cru_w, lut_y[4] + lut_C_off, lut_x, lut_y[4] + lut_C_off}}},
+        {id_D4, {{cru_x + cru_w, lut_y[4] + lut_D_off, lut_x, lut_y[4] + lut_D_off}}},
+        {id_A5, {{cru_x + cru_w, lut_y[5] + lut_A_off, lut_x, lut_y[5] + lut_A_off}}},
+        {id_B5, {{cru_x + cru_w, lut_y[5] + lut_B_off, lut_x, lut_y[5] + lut_B_off}}},
+        {id_C5, {{cru_x + cru_w, lut_y[5] + lut_C_off, lut_x, lut_y[5] + lut_C_off}}},
+        {id_D5, {{cru_x + cru_w, lut_y[5] + lut_D_off, lut_x, lut_y[5] + lut_D_off}}},
+        {id_A6, {{cru_x + cru_w, lut_y[6] + lut_A_off, lut_x, lut_y[6] + lut_A_off}}},
+        {id_B6, {{cru_x + cru_w, lut_y[6] + lut_B_off, lut_x, lut_y[6] + lut_B_off}}},
+        {id_C6, {{cru_x + cru_w, lut_y[6] + lut_C_off, lut_x, lut_y[6] + lut_C_off}}},
+        {id_D6, {{cru_x + cru_w, lut_y[6] + lut_D_off, lut_x, lut_y[6] + lut_D_off}}},
+        {id_A7, {{cru_x + cru_w, lut_y[7] + lut_A_off, lut_x, lut_y[7] + lut_A_off}}},
+        {id_B7, {{cru_x + cru_w, lut_y[7] + lut_B_off, lut_x, lut_y[7] + lut_B_off}}},
+        {id_C7, {{cru_x + cru_w, lut_y[7] + lut_C_off, lut_x, lut_y[7] + lut_C_off}}},
+        {id_D7, {{cru_x + cru_w, lut_y[7] + lut_D_off, lut_x, lut_y[7] + lut_D_off}}},
+        // wires below LUT0
+        {id_Q0,
+         {{cru_x + cru_w, grp_lut_y[0] - right_wire_dist, dff_f_x, grp_lut_y[0] - right_wire_dist},
+          {dff_f_x, grp_lut_y[0] - right_wire_dist, dff_f_x, lut_y[0] + lut_h / 2.},
+          {dff_f_x, lut_y[0] + lut_h / 2., dff_x + dff_w, lut_y[0] + lut_h / 2.}}},
+        {id_F0,
+         {{cru_x + cru_w, grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[0] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[0] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[0] + lut_h / 2., dff_x, lut_y[0] + lut_h / 2.}}},
+        {id_I0MUX0,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[0] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[0] - 2. * right_wire_dist, mux5i_x, lut_y[0] + lut_h / 2.},
+          {mux5i_x, lut_y[0] + lut_h / 2., mux2lut5_x, lut_y[0] + lut_h / 2.}}},
+        {id_OF3,
+         {{cru_x + cru_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
+           grp_lut_y[0] - 3. * right_wire_dist},
+          {mux2lut7_x + 4. / 3. * mux_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h / 2.},
+          {mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut7_x + mux_w, mux2lut7_y + mux_h / 2.}}},
+        {id_I1MUX7, {{mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut8_x, mux2lut7_y + mux_h / 2.}}},
+        // wires between LUT1 and LUT2
+        {id_Q1,
+         {{cru_x + cru_w, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, grp_lut_y[1] - 10. * right_wire_dist},
+          {dff_f_x, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, lut_y[1] + lut_h / 2.},
+          {dff_f_x, lut_y[1] + lut_h / 2., dff_x + dff_w, lut_y[1] + lut_h / 2.}}},
+        {id_F1,
+         {{cru_x + cru_w, grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[1] - 9. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[1] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[1] + lut_h / 2., dff_x, lut_y[1] + lut_h / 2.}}},
+        {id_I1MUX0,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, mux5i_x,
+           grp_lut_y[1] - 9. * right_wire_dist},
+          {mux5i_x, grp_lut_y[1] - 9. * right_wire_dist, mux5i_x, lut_y[1] + lut_h / 2.},
+          {mux5i_x, lut_y[1] + lut_h / 2., mux2lut5_x, lut_y[1] + lut_h / 2.}}},
+        {id_SEL0,
+         {{cru_x + cru_w, grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[1] - 8. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[0] + mux_h - mux_f / 2.}}},
+        {id_OF7,
+         {{cru_x + cru_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 7. * right_wire_dist},
+          {mux2lut8_x + 4. / 3. * mux_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
+           mux2lut8_y + mux_h / 2.},
+          {mux2lut8_x + 4. / 3. * mux_w, mux2lut8_y + mux_h / 2., mux2lut8_x + mux_w, mux2lut8_y + mux_h / 2.}}},
+        {id_SEL1,
+         {{cru_x + cru_w, grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           grp_lut_y[1] - 6. * right_wire_dist},
+          {mux2lut6_x + mux_w / 2., grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           mux2lut6_y[0] + mux_h - mux_f / 2.}}},
+        {id_OF0,
+         {{cru_x + cru_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 5. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[0] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[0] + mux_h / 2.}}},
+        {id_I1MUX1,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut6_x, mux2lut5_y[0] + mux_h / 2.}}},
+        {id_OF1,
+         {{cru_x + cru_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 4. * right_wire_dist},
+          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut6_y[0] + mux_h / 2.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[0] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[0] + mux_h / 2.}}},
+        {id_I1MUX3,
+         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h * 1. / 4.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 1. / 4., mux2lut7_x, mux2lut7_y + mux_h * 1. / 4.}}},
+        {id_OF2,
+         {{cru_x + cru_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           grp_lut_y[1] - 3. * right_wire_dist},
+          {mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           mux2lut5_y[1] + mux_h / 2.},
+          {mux2lut5_x + 5. / 3. * mux_w, mux2lut5_y[1] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[1] + mux_h / 2.}}},
+        {id_I0MUX1,
+         {{mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           mux2lut6_y[0] + mux_h * 3. / 4.},
+          {mux2lut5_x + 5. / 3. * mux_w, mux2lut6_y[0] + mux_h * 3. / 4., mux2lut6_x,
+           mux2lut6_y[0] + mux_h * 3. / 4.}}},
+        {id_F2,
+         {{cru_x + cru_w, grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[1] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[2] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[2] + lut_h / 2., dff_x, lut_y[2] + lut_h / 2.}}},
+        {id_I0MUX2,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[1] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[1] - 2. * right_wire_dist, mux5i_x, lut_y[2] + lut_h / 2.},
+          {mux5i_x, lut_y[2] + lut_h / 2., mux2lut5_x, lut_y[2] + lut_h / 2.}}},
+        {id_Q2,
+         {{cru_x + cru_w, grp_lut_y[1] - right_wire_dist, dff_f_x, grp_lut_y[1] - right_wire_dist},
+          {dff_f_x, grp_lut_y[1] - right_wire_dist, dff_f_x, lut_y[2] + lut_h / 2.},
+          {dff_f_x, lut_y[2] + lut_h / 2., dff_x + dff_w, lut_y[2] + lut_h / 2.}}},
+        // wires between LUT3 and LUT4
+        {id_Q3,
+         {{cru_x + cru_w, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, grp_lut_y[2] - 9. * right_wire_dist},
+          {dff_f_x, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, lut_y[3] + lut_h / 2.},
+          {dff_f_x, lut_y[3] + lut_h / 2., dff_x + dff_w, lut_y[3] + lut_h / 2.}}},
+        {id_F3,
+         {{cru_x + cru_w, grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[2] - 8. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[3] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[3] + lut_h / 2., dff_x, lut_y[3] + lut_h / 2.}}},
+        {id_I1MUX2,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, mux5i_x,
+           grp_lut_y[2] - 8. * right_wire_dist},
+          {mux5i_x, grp_lut_y[2] - 8. * right_wire_dist, mux5i_x, lut_y[3] + lut_h / 2.},
+          {mux5i_x, lut_y[3] + lut_h / 2., mux2lut5_x, lut_y[3] + lut_h / 2.}}},
+        {id_SEL2,
+         {{cru_x + cru_w, grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[2] - 7. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[1] + mux_h - mux_f / 2.}}},
+        {id_SEL3,
+         {{cru_x + cru_w, grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
+           grp_lut_y[2] - 6. * right_wire_dist},
+          {mux2lut7_x + mux_w / 2., grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
+           mux2lut7_y + mux_h - mux_f / 2.}}},
+        {id_SEL7,
+         {{cru_x + cru_w, grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
+           grp_lut_y[2] - 5. * right_wire_dist},
+          {mux2lut8_x + mux_w / 2., grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
+           mux2lut8_y + mux_h - mux_f / 2.}}},
+        {id_OF5,
+         {{cru_x + cru_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           grp_lut_y[2] - 4. * right_wire_dist},
+          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut6_y[1] + mux_h / 2.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[1] + mux_h / 2.}}},
+        {id_I0MUX3,
+         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h * 3. / 4.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 3. / 4., mux2lut7_x, mux2lut7_y + mux_h * 3. / 4.}}},
+        {id_OF4,
+         {{cru_x + cru_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[2] - 3. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[2] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[2] + mux_h / 2.}}},
+        {id_I1MUX5,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut6_x, mux2lut5_y[2] + mux_h / 2.}}},
+        {id_F4,
+         {{cru_x + cru_w, grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[2] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[4] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[4] + lut_h / 2., dff_x, lut_y[4] + lut_h / 2.}}},
+        {id_I0MUX4,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[2] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[2] - 2. * right_wire_dist, mux5i_x, lut_y[4] + lut_h / 2.},
+          {mux5i_x, lut_y[4] + lut_h / 2., mux2lut5_x, lut_y[4] + lut_h / 2.}}},
+        {id_Q4,
+         {{cru_x + cru_w, grp_lut_y[2] - right_wire_dist, dff_f_x, grp_lut_y[2] - right_wire_dist},
+          {dff_f_x, grp_lut_y[2] - right_wire_dist, dff_f_x, lut_y[4] + lut_h / 2.},
+          {dff_f_x, lut_y[4] + lut_h / 2., dff_x + dff_w, lut_y[4] + lut_h / 2.}}},
+        // wires between LUT5 and LUT6
+        {id_Q5,
+         {{cru_x + cru_w, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, grp_lut_y[3] - 6. * right_wire_dist},
+          {dff_f_x, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, lut_y[5] + lut_h / 2.},
+          {dff_f_x, lut_y[5] + lut_h / 2., dff_x + dff_w, lut_y[5] + lut_h / 2.}}},
+        {id_F5,
+         {{cru_x + cru_w, grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[3] - 5. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[5] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[5] + lut_h / 2., dff_x, lut_y[5] + lut_h / 2.}}},
+        {id_I1MUX4,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, mux5i_x,
+           grp_lut_y[3] - 5. * right_wire_dist},
+          {mux5i_x, grp_lut_y[3] - 5. * right_wire_dist, mux5i_x, lut_y[5] + lut_h / 2.},
+          {mux5i_x, lut_y[5] + lut_h / 2., mux2lut5_x, lut_y[5] + lut_h / 2.}}},
+        {id_SEL4,
+         {{cru_x + cru_w, grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[3] - 4. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[2] + mux_h - mux_f / 2.}}},
+        {id_SEL5,
+         {{cru_x + cru_w, grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           grp_lut_y[3] - 2. * right_wire_dist},
+          {mux2lut6_x + mux_w / 2., grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           mux2lut6_y[1] + mux_h - mux_f / 2.}}},
+        {id_F6,
+         {{cru_x + cru_w, grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[6] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[6] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2.}}},
+        {id_I0MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2., mux2lut5_x, lut_y[6] + lut_h / 2.}}},
+        // wires above LUT7
+        {id_F7,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[3] + grp_lut_h + right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[7] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[7] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2.}}},
+        {id_I1MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2., mux2lut5_x, lut_y[7] + lut_h / 2.}}},
+        {id_SEL6,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[3] + mux_h - mux_f / 2.}}},
+        {id_OF6,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[3] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[3] + mux_h / 2.}}},
+        {id_I0MUX5,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut6_y[1] + mux_h * 3. / 4.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h * 3. / 4., mux2lut6_x,
+           mux2lut6_y[1] + mux_h * 3. / 4.}}},
+};
+
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> globalSimpleWires = {
+        {id_I0MUX7,
+         {{mux2lut8_x, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4.},
+          {mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w,
+           cru_y - 2. * right_wire_dist},
+          {mux2lut8_x - 1. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
+           cru_y - 2. * right_wire_dist},
+          {1. + mux2lut7_x + 4. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
+           grp_lut_y[0] - 3. * right_wire_dist}}},
+};
+
+dict<IdString, std::vector<std::tuple<float, float, float, float>>> const globalWires = {
+#define PIP_Y(pip_id) (pipPoint.at(pip_id).second)
+#define WIRE_X(offset) (cru_x - ((float)offset) * sn_dist)
+        // 1 hop
+        {id_S10,
+         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
+          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. + PIP_Y(id_S101)},
+          {WIRE_X(1), -1. + PIP_Y(id_S101), WIRE_X(0), -1. + PIP_Y(id_S101)}}},
+        {id_N10,
+         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
+          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + PIP_Y(id_N101)},
+          {WIRE_X(2), 1. + PIP_Y(id_N101), WIRE_X(0), 1. + PIP_Y(id_N101)}}},
+        {id_S10_loop0,
+         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
+          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. * wrap_len},
+          {WIRE_X(1), -1. * wrap_len, WIRE_X(2), -1. * wrap_len},
+          {WIRE_X(2), -1. * wrap_len, WIRE_X(2), PIP_Y(id_N101)},
+          {WIRE_X(2), PIP_Y(id_N101), WIRE_X(0), PIP_Y(id_N101)}}},
+        {id_N10_loop0,
+         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
+          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + 1. * wrap_len},
+          {WIRE_X(2), 1. + 1. * wrap_len, WIRE_X(1), 1. + 1. * wrap_len},
+          {WIRE_X(1), 1. + 1. * wrap_len, WIRE_X(1), PIP_Y(id_S101)},
+          {WIRE_X(1), PIP_Y(id_S101), WIRE_X(0), PIP_Y(id_S101)}}},
+        {id_S13,
+         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
+          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. + PIP_Y(id_S131)},
+          {WIRE_X(3), -1. + PIP_Y(id_S131), WIRE_X(0), -1. + PIP_Y(id_S131)}}},
+        {id_N13,
+         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
+          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + PIP_Y(id_N131)},
+          {WIRE_X(4), 1. + PIP_Y(id_N131), WIRE_X(0), 1. + PIP_Y(id_N131)}}},
+        {id_S13_loop0,
+         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
+          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. * wrap_len},
+          {WIRE_X(3), -1. * wrap_len, WIRE_X(4), -1. * wrap_len},
+          {WIRE_X(4), -1. * wrap_len, WIRE_X(4), PIP_Y(id_N131)},
+          {WIRE_X(4), PIP_Y(id_N131), WIRE_X(0), PIP_Y(id_N131)}}},
+        {id_N13_loop0,
+         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
+          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + 1. * wrap_len},
+          {WIRE_X(4), 1. + 1. * wrap_len, WIRE_X(3), 1. + 1. * wrap_len},
+          {WIRE_X(3), 1. + 1. * wrap_len, WIRE_X(3), PIP_Y(id_S131)},
+          {WIRE_X(3), PIP_Y(id_S131), WIRE_X(0), PIP_Y(id_S131)}}},
+        // 1 hop SN
+        {id_SN10,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
+          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
+          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
+        {id_SN10_loop_n,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + 1. * wrap_len},
+          {WIRE_X(6), 1. + 1. * wrap_len, WIRE_X(5), 1. + 1. * wrap_len},
+          {WIRE_X(5), 1. + 1. * wrap_len, WIRE_X(5), PIP_Y(id_SN10)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
+          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
+        {id_SN10_loop_s,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
+          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. * wrap_len},
+          {WIRE_X(5), -1. * wrap_len, WIRE_X(6), -1. * wrap_len},
+          {WIRE_X(6), -1. * wrap_len, WIRE_X(6), PIP_Y(id_N111)},
+          {WIRE_X(6), PIP_Y(id_N111), WIRE_X(0), PIP_Y(id_N111)}}},
+        {id_SN20,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
+          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
+          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
+        {id_SN20_loop_n,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + 1. * wrap_len},
+          {WIRE_X(8), 1. + 1. * wrap_len, WIRE_X(7), 1. + 1. * wrap_len},
+          {WIRE_X(7), 1. + 1. * wrap_len, WIRE_X(7), PIP_Y(id_SN10)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
+          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
+        {id_SN20_loop_s,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
+          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. * wrap_len},
+          {WIRE_X(7), -1. * wrap_len, WIRE_X(8), -1. * wrap_len},
+          {WIRE_X(8), -1. * wrap_len, WIRE_X(8), PIP_Y(id_N121)},
+          {WIRE_X(8), PIP_Y(id_N121), WIRE_X(0), PIP_Y(id_N121)}}},
+        // 2 hop
+        {id_S20,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
+          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
+          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -2. + PIP_Y(id_S202)},
+          {WIRE_X(9), -2. + PIP_Y(id_S202), WIRE_X(0), -2. + PIP_Y(id_S202)}}},
+        {id_N20,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
+          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
+          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + PIP_Y(id_N202)},
+          {WIRE_X(10), 2. + PIP_Y(id_N202), WIRE_X(0), 2. + PIP_Y(id_N202)}}},
+        {id_S20_loop0,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. * wrap_len},
+          {WIRE_X(11), -1. * wrap_len, WIRE_X(12), -1. * wrap_len},
+          {WIRE_X(12), -1. * wrap_len, WIRE_X(12), PIP_Y(id_N201)},
+          {WIRE_X(12), PIP_Y(id_N201), WIRE_X(0), PIP_Y(id_N201)},
+          {WIRE_X(10), PIP_Y(id_N201), WIRE_X(10), 1. + PIP_Y(id_N202)},
+          {WIRE_X(10), 1. + PIP_Y(id_N202), WIRE_X(0), 1. + PIP_Y(id_N202)}}},
+        {id_N20_loop0,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + 1. * wrap_len},
+          {WIRE_X(12), 1. + 1. * wrap_len, WIRE_X(11), 1. + 1. * wrap_len},
+          {WIRE_X(11), 1. + 1. * wrap_len, WIRE_X(11), PIP_Y(id_S201)},
+          {WIRE_X(11), PIP_Y(id_S201), WIRE_X(0), PIP_Y(id_S201)},
+          {WIRE_X(9), PIP_Y(id_S201), WIRE_X(9), -1. + PIP_Y(id_S202)},
+          {WIRE_X(9), -1. + PIP_Y(id_S202), WIRE_X(0), -1. + PIP_Y(id_S202)}}},
+        {id_S20_loop1,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
+          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
+          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -1. + -1. * wrap_len},
+          {WIRE_X(9), -1. + -1. * wrap_len, WIRE_X(10), -1. + -1. * wrap_len},
+          {WIRE_X(10), -1. + -1. * wrap_len, WIRE_X(10), -1. + PIP_Y(id_N202)},
+          {WIRE_X(10), -1. + PIP_Y(id_N202), WIRE_X(0), -1. + PIP_Y(id_N202)}}},
+        {id_N20_loop1,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
+          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
+          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + 1. * wrap_len},
+          {WIRE_X(10), 2. + 1. * wrap_len, WIRE_X(9), 2. + 1. * wrap_len},
+          {WIRE_X(9), 2. + 1. * wrap_len, WIRE_X(9), 1. + PIP_Y(id_S202)},
+          {WIRE_X(9), 1. + PIP_Y(id_S202), WIRE_X(0), 1. + PIP_Y(id_S202)}}},
+        {id_S21,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
+          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
+          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -2. + PIP_Y(id_S212)},
+          {WIRE_X(13), -2. + PIP_Y(id_S212), WIRE_X(0), -2. + PIP_Y(id_S212)}}},
+        {id_N21,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
+          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
+          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + PIP_Y(id_N212)},
+          {WIRE_X(14), 2. + PIP_Y(id_N212), WIRE_X(0), 2. + PIP_Y(id_N212)}}},
+        {id_S21_loop0,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. * wrap_len},
+          {WIRE_X(15), -1. * wrap_len, WIRE_X(16), -1. * wrap_len},
+          {WIRE_X(16), -1. * wrap_len, WIRE_X(16), PIP_Y(id_N211)},
+          {WIRE_X(16), PIP_Y(id_N211), WIRE_X(0), PIP_Y(id_N211)},
+          {WIRE_X(14), PIP_Y(id_N211), WIRE_X(14), 1. + PIP_Y(id_N212)},
+          {WIRE_X(14), 1. + PIP_Y(id_N212), WIRE_X(0), 1. + PIP_Y(id_N212)}}},
+        {id_N21_loop0,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + 1. * wrap_len},
+          {WIRE_X(16), 1. + 1. * wrap_len, WIRE_X(15), 1. + 1. * wrap_len},
+          {WIRE_X(15), 1. + 1. * wrap_len, WIRE_X(15), PIP_Y(id_S211)},
+          {WIRE_X(15), PIP_Y(id_S211), WIRE_X(0), PIP_Y(id_S211)},
+          {WIRE_X(13), PIP_Y(id_S211), WIRE_X(13), -1. + PIP_Y(id_S212)},
+          {WIRE_X(13), -1. + PIP_Y(id_S212), WIRE_X(0), -1. + PIP_Y(id_S212)}}},
+        {id_S21_loop1,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
+          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
+          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -1. + -1. * wrap_len},
+          {WIRE_X(13), -1. + -1. * wrap_len, WIRE_X(14), -1. + -1. * wrap_len},
+          {WIRE_X(14), -1. + -1. * wrap_len, WIRE_X(14), -1. + PIP_Y(id_N212)},
+          {WIRE_X(14), -1. + PIP_Y(id_N212), WIRE_X(0), -1. + PIP_Y(id_N212)}}},
+        {id_N21_loop1,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
+          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
+          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + 1. * wrap_len},
+          {WIRE_X(14), 2. + 1. * wrap_len, WIRE_X(13), 2. + 1. * wrap_len},
+          {WIRE_X(13), 2. + 1. * wrap_len, WIRE_X(13), 1. + PIP_Y(id_S212)},
+          {WIRE_X(13), 1. + PIP_Y(id_S212), WIRE_X(0), 1. + PIP_Y(id_S212)}}},
+        {id_S22,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
+          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
+          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -2. + PIP_Y(id_S222)},
+          {WIRE_X(17), -2. + PIP_Y(id_S222), WIRE_X(0), -2. + PIP_Y(id_S222)}}},
+        {id_N22,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
+          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
+          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + PIP_Y(id_N222)},
+          {WIRE_X(18), 2. + PIP_Y(id_N222), WIRE_X(0), 2. + PIP_Y(id_N222)}}},
+        {id_S22_loop0,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. * wrap_len},
+          {WIRE_X(19), -1. * wrap_len, WIRE_X(20), -1. * wrap_len},
+          {WIRE_X(20), -1. * wrap_len, WIRE_X(20), PIP_Y(id_N221)},
+          {WIRE_X(20), PIP_Y(id_N221), WIRE_X(0), PIP_Y(id_N221)},
+          {WIRE_X(18), PIP_Y(id_N221), WIRE_X(18), 1. + PIP_Y(id_N222)},
+          {WIRE_X(18), 1. + PIP_Y(id_N222), WIRE_X(0), 1. + PIP_Y(id_N222)}}},
+        {id_N22_loop0,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + 1. * wrap_len},
+          {WIRE_X(20), 1. + 1. * wrap_len, WIRE_X(19), 1. + 1. * wrap_len},
+          {WIRE_X(19), 1. + 1. * wrap_len, WIRE_X(19), PIP_Y(id_S221)},
+          {WIRE_X(19), PIP_Y(id_S221), WIRE_X(0), PIP_Y(id_S221)},
+          {WIRE_X(17), PIP_Y(id_S221), WIRE_X(17), -1. + PIP_Y(id_S222)},
+          {WIRE_X(17), -1. + PIP_Y(id_S222), WIRE_X(0), -1. + PIP_Y(id_S222)}}},
+        {id_S22_loop1,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
+          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
+          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -1. + -1. * wrap_len},
+          {WIRE_X(17), -1. + -1. * wrap_len, WIRE_X(18), -1. + -1. * wrap_len},
+          {WIRE_X(18), -1. + -1. * wrap_len, WIRE_X(18), -1. + PIP_Y(id_N222)},
+          {WIRE_X(18), -1. + PIP_Y(id_N222), WIRE_X(0), -1. + PIP_Y(id_N222)}}},
+        {id_N22_loop1,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
+          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
+          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + 1. * wrap_len},
+          {WIRE_X(18), 2. + 1. * wrap_len, WIRE_X(17), 2. + 1. * wrap_len},
+          {WIRE_X(17), 2. + 1. * wrap_len, WIRE_X(17), 1. + PIP_Y(id_S222)},
+          {WIRE_X(17), 1. + PIP_Y(id_S222), WIRE_X(0), 1. + PIP_Y(id_S222)}}},
+        {id_S23,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
+          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
+          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -2. + PIP_Y(id_S232)},
+          {WIRE_X(21), -2. + PIP_Y(id_S232), WIRE_X(0), -2. + PIP_Y(id_S232)}}},
+        {id_N23,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
+          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
+          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + PIP_Y(id_N232)},
+          {WIRE_X(22), 2. + PIP_Y(id_N232), WIRE_X(0), 2. + PIP_Y(id_N232)}}},
+        {id_S23_loop0,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. * wrap_len},
+          {WIRE_X(23), -1. * wrap_len, WIRE_X(24), -1. * wrap_len},
+          {WIRE_X(24), -1. * wrap_len, WIRE_X(24), PIP_Y(id_N231)},
+          {WIRE_X(24), PIP_Y(id_N231), WIRE_X(0), PIP_Y(id_N231)},
+          {WIRE_X(22), PIP_Y(id_N231), WIRE_X(22), 1. + PIP_Y(id_N232)},
+          {WIRE_X(22), 1. + PIP_Y(id_N232), WIRE_X(0), 1. + PIP_Y(id_N232)}}},
+        {id_N23_loop0,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + 1. * wrap_len},
+          {WIRE_X(24), 1. + 1. * wrap_len, WIRE_X(23), 1. + 1. * wrap_len},
+          {WIRE_X(23), 1. + 1. * wrap_len, WIRE_X(23), PIP_Y(id_S231)},
+          {WIRE_X(23), PIP_Y(id_S231), WIRE_X(0), PIP_Y(id_S231)},
+          {WIRE_X(21), PIP_Y(id_S231), WIRE_X(21), -1. + PIP_Y(id_S232)},
+          {WIRE_X(21), -1. + PIP_Y(id_S232), WIRE_X(0), -1. + PIP_Y(id_S232)}}},
+        {id_S23_loop1,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
+          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
+          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -1. + -1. * wrap_len},
+          {WIRE_X(21), -1. + -1. * wrap_len, WIRE_X(22), -1. + -1. * wrap_len},
+          {WIRE_X(22), -1. + -1. * wrap_len, WIRE_X(22), -1. + PIP_Y(id_N232)},
+          {WIRE_X(22), -1. + PIP_Y(id_N232), WIRE_X(0), -1. + PIP_Y(id_N232)}}},
+        {id_N23_loop1,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
+          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
+          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + 1. * wrap_len},
+          {WIRE_X(22), 2. + 1. * wrap_len, WIRE_X(21), 2. + 1. * wrap_len},
+          {WIRE_X(21), 2. + 1. * wrap_len, WIRE_X(21), 1. + PIP_Y(id_S232)},
+          {WIRE_X(21), 1. + PIP_Y(id_S232), WIRE_X(0), 1. + PIP_Y(id_S232)}}},
+        {id_S24,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
+          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
+          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -2. + PIP_Y(id_S242)},
+          {WIRE_X(25), -2. + PIP_Y(id_S242), WIRE_X(0), -2. + PIP_Y(id_S242)}}},
+        {id_N24,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
+          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
+          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + PIP_Y(id_N242)},
+          {WIRE_X(26), 2. + PIP_Y(id_N242), WIRE_X(0), 2. + PIP_Y(id_N242)}}},
+        {id_S24_loop0,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. * wrap_len},
+          {WIRE_X(27), -1. * wrap_len, WIRE_X(28), -1. * wrap_len},
+          {WIRE_X(28), -1. * wrap_len, WIRE_X(28), PIP_Y(id_N241)},
+          {WIRE_X(28), PIP_Y(id_N241), WIRE_X(0), PIP_Y(id_N241)},
+          {WIRE_X(26), PIP_Y(id_N241), WIRE_X(26), 1. + PIP_Y(id_N242)},
+          {WIRE_X(26), 1. + PIP_Y(id_N242), WIRE_X(0), 1. + PIP_Y(id_N242)}}},
+        {id_N24_loop0,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + 1. * wrap_len},
+          {WIRE_X(28), 1. + 1. * wrap_len, WIRE_X(27), 1. + 1. * wrap_len},
+          {WIRE_X(27), 1. + 1. * wrap_len, WIRE_X(27), PIP_Y(id_S241)},
+          {WIRE_X(27), PIP_Y(id_S241), WIRE_X(0), PIP_Y(id_S241)},
+          {WIRE_X(25), PIP_Y(id_S241), WIRE_X(25), -1. + PIP_Y(id_S242)},
+          {WIRE_X(25), -1. + PIP_Y(id_S242), WIRE_X(0), -1. + PIP_Y(id_S242)}}},
+        {id_S24_loop1,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
+          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
+          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -1. + -1. * wrap_len},
+          {WIRE_X(25), -1. + -1. * wrap_len, WIRE_X(26), -1. + -1. * wrap_len},
+          {WIRE_X(26), -1. + -1. * wrap_len, WIRE_X(26), -1. + PIP_Y(id_N242)},
+          {WIRE_X(26), -1. + PIP_Y(id_N242), WIRE_X(0), -1. + PIP_Y(id_N242)}}},
+        {id_N24_loop1,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
+          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
+          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + 1. * wrap_len},
+          {WIRE_X(26), 2. + 1. * wrap_len, WIRE_X(25), 2. + 1. * wrap_len},
+          {WIRE_X(25), 2. + 1. * wrap_len, WIRE_X(25), 1. + PIP_Y(id_S242)},
+          {WIRE_X(25), 1. + PIP_Y(id_S242), WIRE_X(0), 1. + PIP_Y(id_S242)}}},
+        {id_S25,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
+          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
+          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -2. + PIP_Y(id_S252)},
+          {WIRE_X(29), -2. + PIP_Y(id_S252), WIRE_X(0), -2. + PIP_Y(id_S252)}}},
+        {id_N25,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
+          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
+          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + PIP_Y(id_N252)},
+          {WIRE_X(30), 2. + PIP_Y(id_N252), WIRE_X(0), 2. + PIP_Y(id_N252)}}},
+        {id_S25_loop0,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. * wrap_len},
+          {WIRE_X(31), -1. * wrap_len, WIRE_X(32), -1. * wrap_len},
+          {WIRE_X(32), -1. * wrap_len, WIRE_X(32), PIP_Y(id_N251)},
+          {WIRE_X(32), PIP_Y(id_N251), WIRE_X(0), PIP_Y(id_N251)},
+          {WIRE_X(30), PIP_Y(id_N251), WIRE_X(30), 1. + PIP_Y(id_N252)},
+          {WIRE_X(30), 1. + PIP_Y(id_N252), WIRE_X(0), 1. + PIP_Y(id_N252)}}},
+        {id_N25_loop0,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + 1. * wrap_len},
+          {WIRE_X(32), 1. + 1. * wrap_len, WIRE_X(31), 1. + 1. * wrap_len},
+          {WIRE_X(31), 1. + 1. * wrap_len, WIRE_X(31), PIP_Y(id_S251)},
+          {WIRE_X(31), PIP_Y(id_S251), WIRE_X(0), PIP_Y(id_S251)},
+          {WIRE_X(29), PIP_Y(id_S251), WIRE_X(29), -1. + PIP_Y(id_S252)},
+          {WIRE_X(29), -1. + PIP_Y(id_S252), WIRE_X(0), -1. + PIP_Y(id_S252)}}},
+        {id_S25_loop1,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
+          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
+          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -1. + -1. * wrap_len},
+          {WIRE_X(29), -1. + -1. * wrap_len, WIRE_X(30), -1. + -1. * wrap_len},
+          {WIRE_X(30), -1. + -1. * wrap_len, WIRE_X(30), -1. + PIP_Y(id_N252)},
+          {WIRE_X(30), -1. + PIP_Y(id_N252), WIRE_X(0), -1. + PIP_Y(id_N252)}}},
+        {id_N25_loop1,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
+          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
+          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + 1. * wrap_len},
+          {WIRE_X(30), 2. + 1. * wrap_len, WIRE_X(29), 2. + 1. * wrap_len},
+          {WIRE_X(29), 2. + 1. * wrap_len, WIRE_X(29), 1. + PIP_Y(id_S252)},
+          {WIRE_X(29), 1. + PIP_Y(id_S252), WIRE_X(0), 1. + PIP_Y(id_S252)}}},
+        {id_S26,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
+          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
+          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -2. + PIP_Y(id_S262)},
+          {WIRE_X(33), -2. + PIP_Y(id_S262), WIRE_X(0), -2. + PIP_Y(id_S262)}}},
+        {id_N26,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
+          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
+          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + PIP_Y(id_N262)},
+          {WIRE_X(34), 2. + PIP_Y(id_N262), WIRE_X(0), 2. + PIP_Y(id_N262)}}},
+        {id_S26_loop0,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. * wrap_len},
+          {WIRE_X(35), -1. * wrap_len, WIRE_X(36), -1. * wrap_len},
+          {WIRE_X(36), -1. * wrap_len, WIRE_X(36), PIP_Y(id_N261)},
+          {WIRE_X(36), PIP_Y(id_N261), WIRE_X(0), PIP_Y(id_N261)},
+          {WIRE_X(34), PIP_Y(id_N261), WIRE_X(34), 1. + PIP_Y(id_N262)},
+          {WIRE_X(34), 1. + PIP_Y(id_N262), WIRE_X(0), 1. + PIP_Y(id_N262)}}},
+        {id_N26_loop0,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + 1. * wrap_len},
+          {WIRE_X(36), 1. + 1. * wrap_len, WIRE_X(35), 1. + 1. * wrap_len},
+          {WIRE_X(35), 1. + 1. * wrap_len, WIRE_X(35), PIP_Y(id_S261)},
+          {WIRE_X(35), PIP_Y(id_S261), WIRE_X(0), PIP_Y(id_S261)},
+          {WIRE_X(33), PIP_Y(id_S261), WIRE_X(33), -1. + PIP_Y(id_S262)},
+          {WIRE_X(33), -1. + PIP_Y(id_S262), WIRE_X(0), -1. + PIP_Y(id_S262)}}},
+        {id_S26_loop1,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
+          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
+          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -1. + -1. * wrap_len},
+          {WIRE_X(33), -1. + -1. * wrap_len, WIRE_X(34), -1. + -1. * wrap_len},
+          {WIRE_X(34), -1. + -1. * wrap_len, WIRE_X(34), -1. + PIP_Y(id_N262)},
+          {WIRE_X(34), -1. + PIP_Y(id_N262), WIRE_X(0), -1. + PIP_Y(id_N262)}}},
+        {id_N26_loop1,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
+          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
+          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + 1. * wrap_len},
+          {WIRE_X(34), 2. + 1. * wrap_len, WIRE_X(33), 2. + 1. * wrap_len},
+          {WIRE_X(33), 2. + 1. * wrap_len, WIRE_X(33), 1. + PIP_Y(id_S262)},
+          {WIRE_X(33), 1. + PIP_Y(id_S262), WIRE_X(0), 1. + PIP_Y(id_S262)}}},
+        {id_S27,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
+          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
+          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -2. + PIP_Y(id_S272)},
+          {WIRE_X(37), -2. + PIP_Y(id_S272), WIRE_X(0), -2. + PIP_Y(id_S272)}}},
+        {id_N27,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
+          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
+          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + PIP_Y(id_N272)},
+          {WIRE_X(38), 2. + PIP_Y(id_N272), WIRE_X(0), 2. + PIP_Y(id_N272)}}},
+        {id_S27_loop0,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. * wrap_len},
+          {WIRE_X(39), -1. * wrap_len, WIRE_X(40), -1. * wrap_len},
+          {WIRE_X(40), -1. * wrap_len, WIRE_X(40), PIP_Y(id_N271)},
+          {WIRE_X(40), PIP_Y(id_N271), WIRE_X(0), PIP_Y(id_N271)},
+          {WIRE_X(38), PIP_Y(id_N271), WIRE_X(38), 1. + PIP_Y(id_N272)},
+          {WIRE_X(38), 1. + PIP_Y(id_N272), WIRE_X(0), 1. + PIP_Y(id_N272)}}},
+        {id_N27_loop0,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + 1. * wrap_len},
+          {WIRE_X(40), 1. + 1. * wrap_len, WIRE_X(39), 1. + 1. * wrap_len},
+          {WIRE_X(39), 1. + 1. * wrap_len, WIRE_X(39), PIP_Y(id_S271)},
+          {WIRE_X(39), PIP_Y(id_S271), WIRE_X(0), PIP_Y(id_S271)},
+          {WIRE_X(37), PIP_Y(id_S271), WIRE_X(37), -1. + PIP_Y(id_S272)},
+          {WIRE_X(37), -1. + PIP_Y(id_S272), WIRE_X(0), -1. + PIP_Y(id_S272)}}},
+        {id_S27_loop1,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
+          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
+          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -1. + -1. * wrap_len},
+          {WIRE_X(37), -1. + -1. * wrap_len, WIRE_X(38), -1. + -1. * wrap_len},
+          {WIRE_X(38), -1. + -1. * wrap_len, WIRE_X(38), -1. + PIP_Y(id_N272)},
+          {WIRE_X(38), -1. + PIP_Y(id_N272), WIRE_X(0), -1. + PIP_Y(id_N272)}}},
+        {id_N27_loop1,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
+          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
+          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + 1. * wrap_len},
+          {WIRE_X(38), 2. + 1. * wrap_len, WIRE_X(37), 2. + 1. * wrap_len},
+          {WIRE_X(37), 2. + 1. * wrap_len, WIRE_X(37), 1. + PIP_Y(id_S272)},
+          {WIRE_X(37), 1. + PIP_Y(id_S272), WIRE_X(0), 1. + PIP_Y(id_S272)}}},
+// clock taps
+#define CLK_GT00_X 41.f
+#define CLK_GT10_X 46.f
+// 4 hop
+#define HOP4X_START (CLK_GT00_X + 10.f)
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START)
+        {id_S80,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
+          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S808) - 8.},
+          {HOP4X(0), PIP_Y(id_S808) - 8., WIRE_X(0), PIP_Y(id_S808) - 8.}}},
+        {id_N80,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
+          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N808) + 8.},
+          {HOP4X(1), PIP_Y(id_N808) + 8., WIRE_X(0), PIP_Y(id_N808) + 8.}}},
+        {id_S80_loop0,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N800) - 0.},
+          {HOP4X(15), PIP_Y(id_N800) - 0., HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N800) + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N800) + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N800) + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N804) + 3., WIRE_X(0), PIP_Y(id_N804) + 3.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N800) + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N800) + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N800) + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N808) + 7.},
+          {HOP4X(1), PIP_Y(id_N808) + 7., WIRE_X(0), PIP_Y(id_N808) + 7.}}},
+        {id_S80_loop1,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N800) - 1.},
+          {HOP4X(13), PIP_Y(id_N800) - 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N800) - 0.},
+          {HOP4X(11), PIP_Y(id_N800) - 0., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N800) + 1.},
+          {HOP4X(9), PIP_Y(id_N800) + 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N804) + 1., WIRE_X(0), PIP_Y(id_N804) + 1.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N800) + 2.},
+          {HOP4X(7), PIP_Y(id_N800) + 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N800) + 3.},
+          {HOP4X(5), PIP_Y(id_N800) + 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N800) + 4.},
+          {HOP4X(3), PIP_Y(id_N800) + 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N808) + 5.},
+          {HOP4X(1), PIP_Y(id_N808) + 5., WIRE_X(0), PIP_Y(id_N808) + 5.}}},
+        {id_S80_loop2,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N800) - 2.},
+          {HOP4X(11), PIP_Y(id_N800) - 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N800) - 1.},
+          {HOP4X(9), PIP_Y(id_N800) - 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N804) - 1., WIRE_X(0), PIP_Y(id_N804) - 1.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N800) - 0.},
+          {HOP4X(7), PIP_Y(id_N800) - 0., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N800) + 1.},
+          {HOP4X(5), PIP_Y(id_N800) + 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N800) + 2.},
+          {HOP4X(3), PIP_Y(id_N800) + 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N808) + 3.},
+          {HOP4X(1), PIP_Y(id_N808) + 3., WIRE_X(0), PIP_Y(id_N808) + 3.}}},
+        {id_S80_loop3,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N800) - 3.},
+          {HOP4X(9), PIP_Y(id_N804) - 3., WIRE_X(0), PIP_Y(id_N804) - 3.},
+          {HOP4X(9), PIP_Y(id_N800) - 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N800) - 2.},
+          {HOP4X(7), PIP_Y(id_N800) - 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N800) - 1.},
+          {HOP4X(5), PIP_Y(id_N800) - 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N800) - 0.},
+          {HOP4X(3), PIP_Y(id_N800) - 0., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N808) + 1.},
+          {HOP4X(1), PIP_Y(id_N808) + 1., WIRE_X(0), PIP_Y(id_N808) + 1.}}},
+        {id_S80_loop4,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N800) - 4.},
+          {HOP4X(7), PIP_Y(id_N800) - 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N800) - 3.},
+          {HOP4X(5), PIP_Y(id_N800) - 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N800) - 2.},
+          {HOP4X(3), PIP_Y(id_N800) - 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N808) - 1.},
+          {HOP4X(1), PIP_Y(id_N808) - 1., WIRE_X(0), PIP_Y(id_N808) - 1.}}},
+        {id_S80_loop5,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N800) - 5.},
+          {HOP4X(5), PIP_Y(id_N800) - 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N800) - 4.},
+          {HOP4X(3), PIP_Y(id_N800) - 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N808) - 3.},
+          {HOP4X(1), PIP_Y(id_N808) - 3., WIRE_X(0), PIP_Y(id_N808) - 3.}}},
+        {id_S80_loop6,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N800) - 6.},
+          {HOP4X(3), PIP_Y(id_N800) - 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N808) - 5.},
+          {HOP4X(1), PIP_Y(id_N808) - 5., WIRE_X(0), PIP_Y(id_N808) - 5.}}},
+        {id_S80_loop7,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
+          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N808) - 7.},
+          {HOP4X(1), PIP_Y(id_N808) - 7., WIRE_X(0), PIP_Y(id_N808) - 7.}}},
+        {id_N80_loop0,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N808) + 0.},
+          {HOP4X(14), PIP_Y(id_N808) + 0., HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N808) - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N808) - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N808) - 3.},
+          {HOP4X(8), PIP_Y(id_S804) - 3., WIRE_X(0), PIP_Y(id_S804) - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N808) - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N808) - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N808) - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S808) - 7.},
+          {HOP4X(0), PIP_Y(id_S808) - 7., WIRE_X(0), PIP_Y(id_S808) - 7.}}},
+        {id_N80_loop1,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N808) + 1.},
+          {HOP4X(12), PIP_Y(id_N808) + 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N808) + 0.},
+          {HOP4X(10), PIP_Y(id_N808) + 0., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N808) - 1.},
+          {HOP4X(8), PIP_Y(id_S804) - 1., WIRE_X(0), PIP_Y(id_S804) - 1.},
+          {HOP4X(8), PIP_Y(id_N808) - 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N808) - 2.},
+          {HOP4X(6), PIP_Y(id_N808) - 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N808) - 3.},
+          {HOP4X(4), PIP_Y(id_N808) - 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N808) - 4.},
+          {HOP4X(2), PIP_Y(id_N808) - 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S808) - 5.},
+          {HOP4X(0), PIP_Y(id_S808) - 5., WIRE_X(0), PIP_Y(id_S808) - 5.}}},
+        {id_N80_loop2,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N808) + 2.},
+          {HOP4X(10), PIP_Y(id_N808) + 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N808) + 1.},
+          {HOP4X(8), PIP_Y(id_S804) + 1., WIRE_X(0), PIP_Y(id_S804) + 1.},
+          {HOP4X(8), PIP_Y(id_N808) + 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N808) + 0.},
+          {HOP4X(6), PIP_Y(id_N808) + 0., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N808) - 1.},
+          {HOP4X(4), PIP_Y(id_N808) - 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N808) - 2.},
+          {HOP4X(2), PIP_Y(id_N808) - 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S808) - 3.},
+          {HOP4X(0), PIP_Y(id_S808) - 3., WIRE_X(0), PIP_Y(id_S808) - 3.}}},
+        {id_N80_loop3,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N808) + 3.},
+          {HOP4X(8), PIP_Y(id_S804) + 3., WIRE_X(0), PIP_Y(id_S804) + 3.},
+          {HOP4X(8), PIP_Y(id_N808) + 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N808) + 2.},
+          {HOP4X(6), PIP_Y(id_N808) + 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N808) + 1.},
+          {HOP4X(4), PIP_Y(id_N808) + 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N808) + 0.},
+          {HOP4X(2), PIP_Y(id_N808) + 0., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S808) - 1.},
+          {HOP4X(0), PIP_Y(id_S808) - 1., WIRE_X(0), PIP_Y(id_S808) - 1.}}},
+        {id_N80_loop4,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N808) + 4.},
+          {HOP4X(6), PIP_Y(id_N808) + 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N808) + 3.},
+          {HOP4X(4), PIP_Y(id_N808) + 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N808) + 2.},
+          {HOP4X(2), PIP_Y(id_N808) + 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S808) + 1.},
+          {HOP4X(0), PIP_Y(id_S808) + 1., WIRE_X(0), PIP_Y(id_S808) + 1.}}},
+        {id_N80_loop5,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N808) + 5.},
+          {HOP4X(4), PIP_Y(id_N808) + 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N808) + 4.},
+          {HOP4X(2), PIP_Y(id_N808) + 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S808) + 3.},
+          {HOP4X(0), PIP_Y(id_S808) + 3., WIRE_X(0), PIP_Y(id_S808) + 3.}}},
+        {id_N80_loop6,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N808) + 6.},
+          {HOP4X(2), PIP_Y(id_N808) + 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S808) + 5.},
+          {HOP4X(0), PIP_Y(id_S808) + 5., WIRE_X(0), PIP_Y(id_S808) + 5.}}},
+        {id_N80_loop7,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
+          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S808) + 7.},
+          {HOP4X(0), PIP_Y(id_S808) + 7., WIRE_X(0), PIP_Y(id_S808) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f)
+        {id_S81,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
+          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S818) - 8.},
+          {HOP4X(0), PIP_Y(id_S818) - 8., WIRE_X(0), PIP_Y(id_S818) - 8.}}},
+        {id_N81,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
+          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N818) + 8.},
+          {HOP4X(1), PIP_Y(id_N818) + 8., WIRE_X(0), PIP_Y(id_N818) + 8.}}},
+        {id_S81_loop0,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N810) - 0.},
+          {HOP4X(15), PIP_Y(id_N810) - 0., HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N810) + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N810) + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N810) + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N814) + 3., WIRE_X(0), PIP_Y(id_N814) + 3.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N810) + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N810) + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N810) + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N818) + 7.},
+          {HOP4X(1), PIP_Y(id_N818) + 7., WIRE_X(0), PIP_Y(id_N818) + 7.}}},
+        {id_S81_loop1,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N810) - 1.},
+          {HOP4X(13), PIP_Y(id_N810) - 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N810) - 0.},
+          {HOP4X(11), PIP_Y(id_N810) - 0., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N810) + 1.},
+          {HOP4X(9), PIP_Y(id_N810) + 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N814) + 1., WIRE_X(0), PIP_Y(id_N814) + 1.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N810) + 2.},
+          {HOP4X(7), PIP_Y(id_N810) + 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N810) + 3.},
+          {HOP4X(5), PIP_Y(id_N810) + 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N810) + 4.},
+          {HOP4X(3), PIP_Y(id_N810) + 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N818) + 5.},
+          {HOP4X(1), PIP_Y(id_N818) + 5., WIRE_X(0), PIP_Y(id_N818) + 5.}}},
+        {id_S81_loop2,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N810) - 2.},
+          {HOP4X(11), PIP_Y(id_N810) - 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N810) - 1.},
+          {HOP4X(9), PIP_Y(id_N810) - 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N814) - 1., WIRE_X(0), PIP_Y(id_N814) - 1.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N810) - 0.},
+          {HOP4X(7), PIP_Y(id_N810) - 0., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N810) + 1.},
+          {HOP4X(5), PIP_Y(id_N810) + 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N810) + 2.},
+          {HOP4X(3), PIP_Y(id_N810) + 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N818) + 3.},
+          {HOP4X(1), PIP_Y(id_N818) + 3., WIRE_X(0), PIP_Y(id_N818) + 3.}}},
+        {id_S81_loop3,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N810) - 3.},
+          {HOP4X(9), PIP_Y(id_N814) - 3., WIRE_X(0), PIP_Y(id_N814) - 3.},
+          {HOP4X(9), PIP_Y(id_N810) - 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N810) - 2.},
+          {HOP4X(7), PIP_Y(id_N810) - 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N810) - 1.},
+          {HOP4X(5), PIP_Y(id_N810) - 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N810) - 0.},
+          {HOP4X(3), PIP_Y(id_N810) - 0., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N818) + 1.},
+          {HOP4X(1), PIP_Y(id_N818) + 1., WIRE_X(0), PIP_Y(id_N818) + 1.}}},
+        {id_S81_loop4,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N810) - 4.},
+          {HOP4X(7), PIP_Y(id_N810) - 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N810) - 3.},
+          {HOP4X(5), PIP_Y(id_N810) - 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N810) - 2.},
+          {HOP4X(3), PIP_Y(id_N810) - 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N818) - 1.},
+          {HOP4X(1), PIP_Y(id_N818) - 1., WIRE_X(0), PIP_Y(id_N818) - 1.}}},
+        {id_S81_loop5,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N810) - 5.},
+          {HOP4X(5), PIP_Y(id_N810) - 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N810) - 4.},
+          {HOP4X(3), PIP_Y(id_N810) - 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N818) - 3.},
+          {HOP4X(1), PIP_Y(id_N818) - 3., WIRE_X(0), PIP_Y(id_N818) - 3.}}},
+        {id_S81_loop6,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N810) - 6.},
+          {HOP4X(3), PIP_Y(id_N810) - 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N818) - 5.},
+          {HOP4X(1), PIP_Y(id_N818) - 5., WIRE_X(0), PIP_Y(id_N818) - 5.}}},
+        {id_S81_loop7,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
+          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N818) - 7.},
+          {HOP4X(1), PIP_Y(id_N818) - 7., WIRE_X(0), PIP_Y(id_N818) - 7.}}},
+        {id_N81_loop0,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N818) + 0.},
+          {HOP4X(14), PIP_Y(id_N818) + 0., HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N818) - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N818) - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N818) - 3.},
+          {HOP4X(8), PIP_Y(id_S814) - 3., WIRE_X(0), PIP_Y(id_S814) - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N818) - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N818) - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N818) - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S818) - 7.},
+          {HOP4X(0), PIP_Y(id_S818) - 7., WIRE_X(0), PIP_Y(id_S818) - 7.}}},
+        {id_N81_loop1,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N818) + 1.},
+          {HOP4X(12), PIP_Y(id_N818) + 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N818) + 0.},
+          {HOP4X(10), PIP_Y(id_N818) + 0., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N818) - 1.},
+          {HOP4X(8), PIP_Y(id_S814) - 1., WIRE_X(0), PIP_Y(id_S814) - 1.},
+          {HOP4X(8), PIP_Y(id_N818) - 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N818) - 2.},
+          {HOP4X(6), PIP_Y(id_N818) - 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N818) - 3.},
+          {HOP4X(4), PIP_Y(id_N818) - 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N818) - 4.},
+          {HOP4X(2), PIP_Y(id_N818) - 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S818) - 5.},
+          {HOP4X(0), PIP_Y(id_S818) - 5., WIRE_X(0), PIP_Y(id_S818) - 5.}}},
+        {id_N81_loop2,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N818) + 2.},
+          {HOP4X(10), PIP_Y(id_N818) + 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N818) + 1.},
+          {HOP4X(8), PIP_Y(id_S814) + 1., WIRE_X(0), PIP_Y(id_S814) + 1.},
+          {HOP4X(8), PIP_Y(id_N818) + 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N818) + 0.},
+          {HOP4X(6), PIP_Y(id_N818) + 0., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N818) - 1.},
+          {HOP4X(4), PIP_Y(id_N818) - 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N818) - 2.},
+          {HOP4X(2), PIP_Y(id_N818) - 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S818) - 3.},
+          {HOP4X(0), PIP_Y(id_S818) - 3., WIRE_X(0), PIP_Y(id_S818) - 3.}}},
+        {id_N81_loop3,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N818) + 3.},
+          {HOP4X(8), PIP_Y(id_S814) + 3., WIRE_X(0), PIP_Y(id_S814) + 3.},
+          {HOP4X(8), PIP_Y(id_N818) + 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N818) + 2.},
+          {HOP4X(6), PIP_Y(id_N818) + 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N818) + 1.},
+          {HOP4X(4), PIP_Y(id_N818) + 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N818) + 0.},
+          {HOP4X(2), PIP_Y(id_N818) + 0., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S818) - 1.},
+          {HOP4X(0), PIP_Y(id_S818) - 1., WIRE_X(0), PIP_Y(id_S818) - 1.}}},
+        {id_N81_loop4,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N818) + 4.},
+          {HOP4X(6), PIP_Y(id_N818) + 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N818) + 3.},
+          {HOP4X(4), PIP_Y(id_N818) + 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N818) + 2.},
+          {HOP4X(2), PIP_Y(id_N818) + 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S818) + 1.},
+          {HOP4X(0), PIP_Y(id_S818) + 1., WIRE_X(0), PIP_Y(id_S818) + 1.}}},
+        {id_N81_loop5,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N818) + 5.},
+          {HOP4X(4), PIP_Y(id_N818) + 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N818) + 4.},
+          {HOP4X(2), PIP_Y(id_N818) + 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S818) + 3.},
+          {HOP4X(0), PIP_Y(id_S818) + 3., WIRE_X(0), PIP_Y(id_S818) + 3.}}},
+        {id_N81_loop6,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N818) + 6.},
+          {HOP4X(2), PIP_Y(id_N818) + 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S818) + 5.},
+          {HOP4X(0), PIP_Y(id_S818) + 5., WIRE_X(0), PIP_Y(id_S818) + 5.}}},
+        {id_N81_loop7,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
+          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S818) + 7.},
+          {HOP4X(0), PIP_Y(id_S818) + 7., WIRE_X(0), PIP_Y(id_S818) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f)
+        {id_S82,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
+          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S828) - 8.},
+          {HOP4X(0), PIP_Y(id_S828) - 8., WIRE_X(0), PIP_Y(id_S828) - 8.}}},
+        {id_N82,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
+          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N828) + 8.},
+          {HOP4X(1), PIP_Y(id_N828) + 8., WIRE_X(0), PIP_Y(id_N828) + 8.}}},
+        {id_S82_loop0,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N820) - 0.},
+          {HOP4X(15), PIP_Y(id_N820) - 0., HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N820) + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N820) + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N820) + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N824) + 3., WIRE_X(0), PIP_Y(id_N824) + 3.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N820) + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N820) + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N820) + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N828) + 7.},
+          {HOP4X(1), PIP_Y(id_N828) + 7., WIRE_X(0), PIP_Y(id_N828) + 7.}}},
+        {id_S82_loop1,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N820) - 1.},
+          {HOP4X(13), PIP_Y(id_N820) - 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N820) - 0.},
+          {HOP4X(11), PIP_Y(id_N820) - 0., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N820) + 1.},
+          {HOP4X(9), PIP_Y(id_N820) + 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N824) + 1., WIRE_X(0), PIP_Y(id_N824) + 1.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N820) + 2.},
+          {HOP4X(7), PIP_Y(id_N820) + 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N820) + 3.},
+          {HOP4X(5), PIP_Y(id_N820) + 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N820) + 4.},
+          {HOP4X(3), PIP_Y(id_N820) + 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N828) + 5.},
+          {HOP4X(1), PIP_Y(id_N828) + 5., WIRE_X(0), PIP_Y(id_N828) + 5.}}},
+        {id_S82_loop2,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N820) - 2.},
+          {HOP4X(11), PIP_Y(id_N820) - 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N820) - 1.},
+          {HOP4X(9), PIP_Y(id_N820) - 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N824) - 1., WIRE_X(0), PIP_Y(id_N824) - 1.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N820) - 0.},
+          {HOP4X(7), PIP_Y(id_N820) - 0., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N820) + 1.},
+          {HOP4X(5), PIP_Y(id_N820) + 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N820) + 2.},
+          {HOP4X(3), PIP_Y(id_N820) + 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N828) + 3.},
+          {HOP4X(1), PIP_Y(id_N828) + 3., WIRE_X(0), PIP_Y(id_N828) + 3.}}},
+        {id_S82_loop3,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N820) - 3.},
+          {HOP4X(9), PIP_Y(id_N824) - 3., WIRE_X(0), PIP_Y(id_N824) - 3.},
+          {HOP4X(9), PIP_Y(id_N820) - 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N820) - 2.},
+          {HOP4X(7), PIP_Y(id_N820) - 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N820) - 1.},
+          {HOP4X(5), PIP_Y(id_N820) - 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N820) - 0.},
+          {HOP4X(3), PIP_Y(id_N820) - 0., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N828) + 1.},
+          {HOP4X(1), PIP_Y(id_N828) + 1., WIRE_X(0), PIP_Y(id_N828) + 1.}}},
+        {id_S82_loop4,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N820) - 4.},
+          {HOP4X(7), PIP_Y(id_N820) - 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N820) - 3.},
+          {HOP4X(5), PIP_Y(id_N820) - 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N820) - 2.},
+          {HOP4X(3), PIP_Y(id_N820) - 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N828) - 1.},
+          {HOP4X(1), PIP_Y(id_N828) - 1., WIRE_X(0), PIP_Y(id_N828) - 1.}}},
+        {id_S82_loop5,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N820) - 5.},
+          {HOP4X(5), PIP_Y(id_N820) - 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N820) - 4.},
+          {HOP4X(3), PIP_Y(id_N820) - 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N828) - 3.},
+          {HOP4X(1), PIP_Y(id_N828) - 3., WIRE_X(0), PIP_Y(id_N828) - 3.}}},
+        {id_S82_loop6,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N820) - 6.},
+          {HOP4X(3), PIP_Y(id_N820) - 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N828) - 5.},
+          {HOP4X(1), PIP_Y(id_N828) - 5., WIRE_X(0), PIP_Y(id_N828) - 5.}}},
+        {id_S82_loop7,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
+          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N828) - 7.},
+          {HOP4X(1), PIP_Y(id_N828) - 7., WIRE_X(0), PIP_Y(id_N828) - 7.}}},
+        {id_N82_loop0,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N828) + 0.},
+          {HOP4X(14), PIP_Y(id_N828) + 0., HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N828) - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N828) - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N828) - 3.},
+          {HOP4X(8), PIP_Y(id_S824) - 3., WIRE_X(0), PIP_Y(id_S824) - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N828) - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N828) - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N828) - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S828) - 7.},
+          {HOP4X(0), PIP_Y(id_S828) - 7., WIRE_X(0), PIP_Y(id_S828) - 7.}}},
+        {id_N82_loop1,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N828) + 1.},
+          {HOP4X(12), PIP_Y(id_N828) + 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N828) + 0.},
+          {HOP4X(10), PIP_Y(id_N828) + 0., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N828) - 1.},
+          {HOP4X(8), PIP_Y(id_S824) - 1., WIRE_X(0), PIP_Y(id_S824) - 1.},
+          {HOP4X(8), PIP_Y(id_N828) - 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N828) - 2.},
+          {HOP4X(6), PIP_Y(id_N828) - 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N828) - 3.},
+          {HOP4X(4), PIP_Y(id_N828) - 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N828) - 4.},
+          {HOP4X(2), PIP_Y(id_N828) - 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S828) - 5.},
+          {HOP4X(0), PIP_Y(id_S828) - 5., WIRE_X(0), PIP_Y(id_S828) - 5.}}},
+        {id_N82_loop2,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N828) + 2.},
+          {HOP4X(10), PIP_Y(id_N828) + 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N828) + 1.},
+          {HOP4X(8), PIP_Y(id_S824) + 1., WIRE_X(0), PIP_Y(id_S824) + 1.},
+          {HOP4X(8), PIP_Y(id_N828) + 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N828) + 0.},
+          {HOP4X(6), PIP_Y(id_N828) + 0., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N828) - 1.},
+          {HOP4X(4), PIP_Y(id_N828) - 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N828) - 2.},
+          {HOP4X(2), PIP_Y(id_N828) - 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S828) - 3.},
+          {HOP4X(0), PIP_Y(id_S828) - 3., WIRE_X(0), PIP_Y(id_S828) - 3.}}},
+        {id_N82_loop3,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N828) + 3.},
+          {HOP4X(8), PIP_Y(id_S824) + 3., WIRE_X(0), PIP_Y(id_S824) + 3.},
+          {HOP4X(8), PIP_Y(id_N828) + 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N828) + 2.},
+          {HOP4X(6), PIP_Y(id_N828) + 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N828) + 1.},
+          {HOP4X(4), PIP_Y(id_N828) + 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N828) + 0.},
+          {HOP4X(2), PIP_Y(id_N828) + 0., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S828) - 1.},
+          {HOP4X(0), PIP_Y(id_S828) - 1., WIRE_X(0), PIP_Y(id_S828) - 1.}}},
+        {id_N82_loop4,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N828) + 4.},
+          {HOP4X(6), PIP_Y(id_N828) + 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N828) + 3.},
+          {HOP4X(4), PIP_Y(id_N828) + 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N828) + 2.},
+          {HOP4X(2), PIP_Y(id_N828) + 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S828) + 1.},
+          {HOP4X(0), PIP_Y(id_S828) + 1., WIRE_X(0), PIP_Y(id_S828) + 1.}}},
+        {id_N82_loop5,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N828) + 5.},
+          {HOP4X(4), PIP_Y(id_N828) + 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N828) + 4.},
+          {HOP4X(2), PIP_Y(id_N828) + 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S828) + 3.},
+          {HOP4X(0), PIP_Y(id_S828) + 3., WIRE_X(0), PIP_Y(id_S828) + 3.}}},
+        {id_N82_loop6,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N828) + 6.},
+          {HOP4X(2), PIP_Y(id_N828) + 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S828) + 5.},
+          {HOP4X(0), PIP_Y(id_S828) + 5., WIRE_X(0), PIP_Y(id_S828) + 5.}}},
+        {id_N82_loop7,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
+          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S828) + 7.},
+          {HOP4X(0), PIP_Y(id_S828) + 7., WIRE_X(0), PIP_Y(id_S828) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f + 18.f)
+        {id_S83,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
+          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S838) - 8.},
+          {HOP4X(0), PIP_Y(id_S838) - 8., WIRE_X(0), PIP_Y(id_S838) - 8.}}},
+        {id_N83,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
+          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N838) + 8.},
+          {HOP4X(1), PIP_Y(id_N838) + 8., WIRE_X(0), PIP_Y(id_N838) + 8.}}},
+        {id_S83_loop0,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N830) - 0.},
+          {HOP4X(15), PIP_Y(id_N830) - 0., HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N830) + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N830) + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N830) + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N834) + 3., WIRE_X(0), PIP_Y(id_N834) + 3.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N830) + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N830) + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N830) + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N838) + 7.},
+          {HOP4X(1), PIP_Y(id_N838) + 7., WIRE_X(0), PIP_Y(id_N838) + 7.}}},
+        {id_S83_loop1,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N830) - 1.},
+          {HOP4X(13), PIP_Y(id_N830) - 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N830) - 0.},
+          {HOP4X(11), PIP_Y(id_N830) - 0., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N830) + 1.},
+          {HOP4X(9), PIP_Y(id_N830) + 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N834) + 1., WIRE_X(0), PIP_Y(id_N834) + 1.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N830) + 2.},
+          {HOP4X(7), PIP_Y(id_N830) + 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N830) + 3.},
+          {HOP4X(5), PIP_Y(id_N830) + 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N830) + 4.},
+          {HOP4X(3), PIP_Y(id_N830) + 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N838) + 5.},
+          {HOP4X(1), PIP_Y(id_N838) + 5., WIRE_X(0), PIP_Y(id_N838) + 5.}}},
+        {id_S83_loop2,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N830) - 2.},
+          {HOP4X(11), PIP_Y(id_N830) - 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N830) - 1.},
+          {HOP4X(9), PIP_Y(id_N830) - 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N834) - 1., WIRE_X(0), PIP_Y(id_N834) - 1.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N830) - 0.},
+          {HOP4X(7), PIP_Y(id_N830) - 0., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N830) + 1.},
+          {HOP4X(5), PIP_Y(id_N830) + 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N830) + 2.},
+          {HOP4X(3), PIP_Y(id_N830) + 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N838) + 3.},
+          {HOP4X(1), PIP_Y(id_N838) + 3., WIRE_X(0), PIP_Y(id_N838) + 3.}}},
+        {id_S83_loop3,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N830) - 3.},
+          {HOP4X(9), PIP_Y(id_N834) - 3., WIRE_X(0), PIP_Y(id_N834) - 3.},
+          {HOP4X(9), PIP_Y(id_N830) - 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N830) - 2.},
+          {HOP4X(7), PIP_Y(id_N830) - 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N830) - 1.},
+          {HOP4X(5), PIP_Y(id_N830) - 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N830) - 0.},
+          {HOP4X(3), PIP_Y(id_N830) - 0., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N838) + 1.},
+          {HOP4X(1), PIP_Y(id_N838) + 1., WIRE_X(0), PIP_Y(id_N838) + 1.}}},
+        {id_S83_loop4,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N830) - 4.},
+          {HOP4X(7), PIP_Y(id_N830) - 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N830) - 3.},
+          {HOP4X(5), PIP_Y(id_N830) - 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N830) - 2.},
+          {HOP4X(3), PIP_Y(id_N830) - 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N838) - 1.},
+          {HOP4X(1), PIP_Y(id_N838) - 1., WIRE_X(0), PIP_Y(id_N838) - 1.}}},
+        {id_S83_loop5,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N830) - 5.},
+          {HOP4X(5), PIP_Y(id_N830) - 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N830) - 4.},
+          {HOP4X(3), PIP_Y(id_N830) - 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N838) - 3.},
+          {HOP4X(1), PIP_Y(id_N838) - 3., WIRE_X(0), PIP_Y(id_N838) - 3.}}},
+        {id_S83_loop6,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N830) - 6.},
+          {HOP4X(3), PIP_Y(id_N830) - 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N838) - 5.},
+          {HOP4X(1), PIP_Y(id_N838) - 5., WIRE_X(0), PIP_Y(id_N838) - 5.}}},
+        {id_S83_loop7,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
+          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N838) - 7.},
+          {HOP4X(1), PIP_Y(id_N838) - 7., WIRE_X(0), PIP_Y(id_N838) - 7.}}},
+        {id_N83_loop0,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N838) + 0.},
+          {HOP4X(14), PIP_Y(id_N838) + 0., HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N838) - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N838) - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N838) - 3.},
+          {HOP4X(8), PIP_Y(id_S834) - 3., WIRE_X(0), PIP_Y(id_S834) - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N838) - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N838) - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N838) - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S838) - 7.},
+          {HOP4X(0), PIP_Y(id_S838) - 7., WIRE_X(0), PIP_Y(id_S838) - 7.}}},
+        {id_N83_loop1,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N838) + 1.},
+          {HOP4X(12), PIP_Y(id_N838) + 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N838) + 0.},
+          {HOP4X(10), PIP_Y(id_N838) + 0., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N838) - 1.},
+          {HOP4X(8), PIP_Y(id_S834) - 1., WIRE_X(0), PIP_Y(id_S834) - 1.},
+          {HOP4X(8), PIP_Y(id_N838) - 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N838) - 2.},
+          {HOP4X(6), PIP_Y(id_N838) - 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N838) - 3.},
+          {HOP4X(4), PIP_Y(id_N838) - 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N838) - 4.},
+          {HOP4X(2), PIP_Y(id_N838) - 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S838) - 5.},
+          {HOP4X(0), PIP_Y(id_S838) - 5., WIRE_X(0), PIP_Y(id_S838) - 5.}}},
+        {id_N83_loop2,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N838) + 2.},
+          {HOP4X(10), PIP_Y(id_N838) + 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N838) + 1.},
+          {HOP4X(8), PIP_Y(id_S834) + 1., WIRE_X(0), PIP_Y(id_S834) + 1.},
+          {HOP4X(8), PIP_Y(id_N838) + 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N838) + 0.},
+          {HOP4X(6), PIP_Y(id_N838) + 0., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N838) - 1.},
+          {HOP4X(4), PIP_Y(id_N838) - 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N838) - 2.},
+          {HOP4X(2), PIP_Y(id_N838) - 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S838) - 3.},
+          {HOP4X(0), PIP_Y(id_S838) - 3., WIRE_X(0), PIP_Y(id_S838) - 3.}}},
+        {id_N83_loop3,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N838) + 3.},
+          {HOP4X(8), PIP_Y(id_S834) + 3., WIRE_X(0), PIP_Y(id_S834) + 3.},
+          {HOP4X(8), PIP_Y(id_N838) + 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N838) + 2.},
+          {HOP4X(6), PIP_Y(id_N838) + 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N838) + 1.},
+          {HOP4X(4), PIP_Y(id_N838) + 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N838) + 0.},
+          {HOP4X(2), PIP_Y(id_N838) + 0., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S838) - 1.},
+          {HOP4X(0), PIP_Y(id_S838) - 1., WIRE_X(0), PIP_Y(id_S838) - 1.}}},
+        {id_N83_loop4,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N838) + 4.},
+          {HOP4X(6), PIP_Y(id_N838) + 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N838) + 3.},
+          {HOP4X(4), PIP_Y(id_N838) + 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N838) + 2.},
+          {HOP4X(2), PIP_Y(id_N838) + 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S838) + 1.},
+          {HOP4X(0), PIP_Y(id_S838) + 1., WIRE_X(0), PIP_Y(id_S838) + 1.}}},
+        {id_N83_loop5,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N838) + 5.},
+          {HOP4X(4), PIP_Y(id_N838) + 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N838) + 4.},
+          {HOP4X(2), PIP_Y(id_N838) + 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S838) + 3.},
+          {HOP4X(0), PIP_Y(id_S838) + 3., WIRE_X(0), PIP_Y(id_S838) + 3.}}},
+        {id_N83_loop6,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N838) + 6.},
+          {HOP4X(2), PIP_Y(id_N838) + 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S838) + 5.},
+          {HOP4X(0), PIP_Y(id_S838) + 5., WIRE_X(0), PIP_Y(id_S838) + 5.}}},
+        {id_N83_loop7,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
+          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S838) + 7.},
+          {HOP4X(0), PIP_Y(id_S838) + 7., WIRE_X(0), PIP_Y(id_S838) + 7.}}},
+
+#define PIP_X(pip_id) (pipPoint.at(pip_id).second)
+#define WIRE_Y(offset) (cru_y + cru_h + ((float)offset) * ew_dist)
+        // 1 hop
+        {id_E10,
+         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
+          {PIP_X(id_E100), WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(1)},
+          {PIP_X(id_E101) + 1., WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(0)}}},
+        {id_W10,
+         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
+          {PIP_X(id_W100), WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(2)},
+          {PIP_X(id_W101) - 1., WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(0)}}},
+        {id_E10_loop0,
+         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
+          {PIP_X(id_E100), WIRE_Y(1), 1. + wrap_len, WIRE_Y(1)},
+          {1. + wrap_len, WIRE_Y(1), 1. + wrap_len, WIRE_Y(2)},
+          {1. + wrap_len, WIRE_Y(2), PIP_X(id_W101), WIRE_Y(2)},
+          {PIP_X(id_W101), WIRE_Y(2), PIP_X(id_W101), WIRE_Y(0)}}},
+        {id_W10_loop0,
+         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
+          {PIP_X(id_W100), WIRE_Y(2), -1. * wrap_len, WIRE_Y(2)},
+          {-1. * wrap_len, WIRE_Y(2), -1. * wrap_len, WIRE_Y(1)},
+          {-1. * wrap_len, WIRE_Y(1), PIP_X(id_E101), WIRE_Y(1)},
+          {PIP_X(id_E101), WIRE_Y(1), PIP_X(id_E101), WIRE_Y(0)}}},
+        {id_E13,
+         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
+          {PIP_X(id_E130), WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(3)},
+          {PIP_X(id_E131) + 1., WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(0)}}},
+        {id_W13,
+         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
+          {PIP_X(id_W130), WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(4)},
+          {PIP_X(id_W131) - 1., WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(0)}}},
+        {id_E13_loop0,
+         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
+          {PIP_X(id_E130), WIRE_Y(3), 1. + wrap_len, WIRE_Y(3)},
+          {1. + wrap_len, WIRE_Y(3), 1. + wrap_len, WIRE_Y(4)},
+          {1. + wrap_len, WIRE_Y(4), PIP_X(id_W131), WIRE_Y(4)},
+          {PIP_X(id_W131), WIRE_Y(4), PIP_X(id_W131), WIRE_Y(0)}}},
+        {id_W13_loop0,
+         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
+          {PIP_X(id_W130), WIRE_Y(4), -1. * wrap_len, WIRE_Y(4)},
+          {-1. * wrap_len, WIRE_Y(4), -1. * wrap_len, WIRE_Y(3)},
+          {-1. * wrap_len, WIRE_Y(3), PIP_X(id_E131), WIRE_Y(3)},
+          {PIP_X(id_E131), WIRE_Y(3), PIP_X(id_E131), WIRE_Y(0)}}},
+        // 1 hop EW
+        {id_EW10,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
+          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
+          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
+        {id_EW10_loop_e,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), wrap_len + 1., WIRE_Y(6)},
+          {wrap_len + 1., WIRE_Y(6), wrap_len + 1., WIRE_Y(5)},
+          {wrap_len + 1., WIRE_Y(5), PIP_X(id_W111), WIRE_Y(5)},
+          {PIP_X(id_W111), WIRE_Y(5), PIP_X(id_W111), WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
+          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
+        {id_EW10_loop_w,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
+          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), -wrap_len, WIRE_Y(5)},
+          {-wrap_len, WIRE_Y(5), -wrap_len, WIRE_Y(6)},
+          {-wrap_len, WIRE_Y(6), PIP_X(id_E111), WIRE_Y(6)},
+          {PIP_X(id_E111), WIRE_Y(6), PIP_X(id_E111), WIRE_Y(0)}}},
+        {id_EW20,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
+          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
+          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
+        {id_EW20_loop_e,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), wrap_len + 1., WIRE_Y(8)},
+          {wrap_len + 1., WIRE_Y(8), wrap_len + 1., WIRE_Y(7)},
+          {wrap_len + 1., WIRE_Y(7), PIP_X(id_W121), WIRE_Y(7)},
+          {PIP_X(id_W121), WIRE_Y(7), PIP_X(id_W121), WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
+          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
+        {id_EW20_loop_w,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
+          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), -wrap_len, WIRE_Y(7)},
+          {-wrap_len, WIRE_Y(7), -wrap_len, WIRE_Y(8)},
+          {-wrap_len, WIRE_Y(8), PIP_X(id_E121), WIRE_Y(8)},
+          {PIP_X(id_E121), WIRE_Y(8), PIP_X(id_E121), WIRE_Y(0)}}},
+// 2 hop
+#define HOP2Y(offset) WIRE_Y(offset + 9)
+        {id_E20,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
+          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
+          {PIP_X(id_E201) + 1., HOP2Y(0), PIP_X(id_E202) + 2., HOP2Y(0)},
+          {PIP_X(id_E202) + 2., HOP2Y(0), PIP_X(id_E202) + 2., WIRE_Y(0)}}},
+        {id_W20,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
+          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
+          {PIP_X(id_W201) - 1., HOP2Y(1), PIP_X(id_W202) - 2., HOP2Y(1)},
+          {PIP_X(id_W202) - 2., HOP2Y(1), PIP_X(id_W202) - 2., WIRE_Y(0)}}},
+        {id_E20_loop0,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W201), HOP2Y(3)},
+          {PIP_X(id_W201), HOP2Y(3), PIP_X(id_W201), WIRE_Y(0)},
+          {PIP_X(id_W201), HOP2Y(1), PIP_X(id_W202) - 1., HOP2Y(1)},
+          {PIP_X(id_W202) - 1., HOP2Y(1), PIP_X(id_W202) - 1., WIRE_Y(0)}}},
+        {id_W20_loop0,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E201), HOP2Y(2)},
+          {PIP_X(id_E201), HOP2Y(2), PIP_X(id_E201), WIRE_Y(0)},
+          {PIP_X(id_E201), HOP2Y(0), PIP_X(id_E202) + 1., HOP2Y(0)},
+          {PIP_X(id_E202) + 1., HOP2Y(0), PIP_X(id_E202) + 1., WIRE_Y(0)}}},
+        {id_E20_loop1,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
+          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
+          {PIP_X(id_E201) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W202) + 1., HOP2Y(1)},
+          {PIP_X(id_W202) + 1., HOP2Y(1), PIP_X(id_W202) + 1., WIRE_Y(0)}}},
+        {id_W20_loop1,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
+          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
+          {PIP_X(id_W201) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E202) - 1., HOP2Y(0)},
+          {PIP_X(id_E202) - 1., HOP2Y(0), PIP_X(id_E202) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 1)
+        {id_E21,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
+          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
+          {PIP_X(id_E211) + 1., HOP2Y(0), PIP_X(id_E212) + 2., HOP2Y(0)},
+          {PIP_X(id_E212) + 2., HOP2Y(0), PIP_X(id_E212) + 2., WIRE_Y(0)}}},
+        {id_W21,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
+          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
+          {PIP_X(id_W211) - 1., HOP2Y(1), PIP_X(id_W212) - 2., HOP2Y(1)},
+          {PIP_X(id_W212) - 2., HOP2Y(1), PIP_X(id_W212) - 2., WIRE_Y(0)}}},
+        {id_E21_loop0,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W211), HOP2Y(3)},
+          {PIP_X(id_W211), HOP2Y(3), PIP_X(id_W211), WIRE_Y(0)},
+          {PIP_X(id_W211), HOP2Y(1), PIP_X(id_W212) - 1., HOP2Y(1)},
+          {PIP_X(id_W212) - 1., HOP2Y(1), PIP_X(id_W212) - 1., WIRE_Y(0)}}},
+        {id_W21_loop0,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E211), HOP2Y(2)},
+          {PIP_X(id_E211), HOP2Y(2), PIP_X(id_E211), WIRE_Y(0)},
+          {PIP_X(id_E211), HOP2Y(0), PIP_X(id_E212) + 1., HOP2Y(0)},
+          {PIP_X(id_E212) + 1., HOP2Y(0), PIP_X(id_E212) + 1., WIRE_Y(0)}}},
+        {id_E21_loop1,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
+          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
+          {PIP_X(id_E211) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W212) + 1., HOP2Y(1)},
+          {PIP_X(id_W212) + 1., HOP2Y(1), PIP_X(id_W212) + 1., WIRE_Y(0)}}},
+        {id_W21_loop1,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
+          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
+          {PIP_X(id_W211) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E212) - 1., HOP2Y(0)},
+          {PIP_X(id_E212) - 1., HOP2Y(0), PIP_X(id_E212) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 2)
+        {id_E22,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
+          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
+          {PIP_X(id_E221) + 1., HOP2Y(0), PIP_X(id_E222) + 2., HOP2Y(0)},
+          {PIP_X(id_E222) + 2., HOP2Y(0), PIP_X(id_E222) + 2., WIRE_Y(0)}}},
+        {id_W22,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
+          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
+          {PIP_X(id_W221) - 1., HOP2Y(1), PIP_X(id_W222) - 2., HOP2Y(1)},
+          {PIP_X(id_W222) - 2., HOP2Y(1), PIP_X(id_W222) - 2., WIRE_Y(0)}}},
+        {id_E22_loop0,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W221), HOP2Y(3)},
+          {PIP_X(id_W221), HOP2Y(3), PIP_X(id_W221), WIRE_Y(0)},
+          {PIP_X(id_W221), HOP2Y(1), PIP_X(id_W222) - 1., HOP2Y(1)},
+          {PIP_X(id_W222) - 1., HOP2Y(1), PIP_X(id_W222) - 1., WIRE_Y(0)}}},
+        {id_W22_loop0,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E221), HOP2Y(2)},
+          {PIP_X(id_E221), HOP2Y(2), PIP_X(id_E221), WIRE_Y(0)},
+          {PIP_X(id_E221), HOP2Y(0), PIP_X(id_E222) + 1., HOP2Y(0)},
+          {PIP_X(id_E222) + 1., HOP2Y(0), PIP_X(id_E222) + 1., WIRE_Y(0)}}},
+        {id_E22_loop1,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
+          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
+          {PIP_X(id_E221) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W222) + 1., HOP2Y(1)},
+          {PIP_X(id_W222) + 1., HOP2Y(1), PIP_X(id_W222) + 1., WIRE_Y(0)}}},
+        {id_W22_loop1,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
+          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
+          {PIP_X(id_W221) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E222) - 1., HOP2Y(0)},
+          {PIP_X(id_E222) - 1., HOP2Y(0), PIP_X(id_E222) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 3)
+        {id_E23,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
+          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
+          {PIP_X(id_E231) + 1., HOP2Y(0), PIP_X(id_E232) + 2., HOP2Y(0)},
+          {PIP_X(id_E232) + 2., HOP2Y(0), PIP_X(id_E232) + 2., WIRE_Y(0)}}},
+        {id_W23,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
+          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
+          {PIP_X(id_W231) - 1., HOP2Y(1), PIP_X(id_W232) - 2., HOP2Y(1)},
+          {PIP_X(id_W232) - 2., HOP2Y(1), PIP_X(id_W232) - 2., WIRE_Y(0)}}},
+        {id_E23_loop0,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W231), HOP2Y(3)},
+          {PIP_X(id_W231), HOP2Y(3), PIP_X(id_W231), WIRE_Y(0)},
+          {PIP_X(id_W231), HOP2Y(1), PIP_X(id_W232) - 1., HOP2Y(1)},
+          {PIP_X(id_W232) - 1., HOP2Y(1), PIP_X(id_W232) - 1., WIRE_Y(0)}}},
+        {id_W23_loop0,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E231), HOP2Y(2)},
+          {PIP_X(id_E231), HOP2Y(2), PIP_X(id_E231), WIRE_Y(0)},
+          {PIP_X(id_E231), HOP2Y(0), PIP_X(id_E232) + 1., HOP2Y(0)},
+          {PIP_X(id_E232) + 1., HOP2Y(0), PIP_X(id_E232) + 1., WIRE_Y(0)}}},
+        {id_E23_loop1,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
+          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
+          {PIP_X(id_E231) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W232) + 1., HOP2Y(1)},
+          {PIP_X(id_W232) + 1., HOP2Y(1), PIP_X(id_W232) + 1., WIRE_Y(0)}}},
+        {id_W23_loop1,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
+          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
+          {PIP_X(id_W231) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E232) - 1., HOP2Y(0)},
+          {PIP_X(id_E232) - 1., HOP2Y(0), PIP_X(id_E232) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 4)
+        {id_E24,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
+          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
+          {PIP_X(id_E241) + 1., HOP2Y(0), PIP_X(id_E242) + 2., HOP2Y(0)},
+          {PIP_X(id_E242) + 2., HOP2Y(0), PIP_X(id_E242) + 2., WIRE_Y(0)}}},
+        {id_W24,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
+          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
+          {PIP_X(id_W241) - 1., HOP2Y(1), PIP_X(id_W242) - 2., HOP2Y(1)},
+          {PIP_X(id_W242) - 2., HOP2Y(1), PIP_X(id_W242) - 2., WIRE_Y(0)}}},
+        {id_E24_loop0,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W241), HOP2Y(3)},
+          {PIP_X(id_W241), HOP2Y(3), PIP_X(id_W241), WIRE_Y(0)},
+          {PIP_X(id_W241), HOP2Y(1), PIP_X(id_W242) - 1., HOP2Y(1)},
+          {PIP_X(id_W242) - 1., HOP2Y(1), PIP_X(id_W242) - 1., WIRE_Y(0)}}},
+        {id_W24_loop0,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E241), HOP2Y(2)},
+          {PIP_X(id_E241), HOP2Y(2), PIP_X(id_E241), WIRE_Y(0)},
+          {PIP_X(id_E241), HOP2Y(0), PIP_X(id_E242) + 1., HOP2Y(0)},
+          {PIP_X(id_E242) + 1., HOP2Y(0), PIP_X(id_E242) + 1., WIRE_Y(0)}}},
+        {id_E24_loop1,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
+          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
+          {PIP_X(id_E241) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W242) + 1., HOP2Y(1)},
+          {PIP_X(id_W242) + 1., HOP2Y(1), PIP_X(id_W242) + 1., WIRE_Y(0)}}},
+        {id_W24_loop1,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
+          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
+          {PIP_X(id_W241) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E242) - 1., HOP2Y(0)},
+          {PIP_X(id_E242) - 1., HOP2Y(0), PIP_X(id_E242) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 5)
+        {id_E25,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
+          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
+          {PIP_X(id_E251) + 1., HOP2Y(0), PIP_X(id_E252) + 2., HOP2Y(0)},
+          {PIP_X(id_E252) + 2., HOP2Y(0), PIP_X(id_E252) + 2., WIRE_Y(0)}}},
+        {id_W25,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
+          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
+          {PIP_X(id_W251) - 1., HOP2Y(1), PIP_X(id_W252) - 2., HOP2Y(1)},
+          {PIP_X(id_W252) - 2., HOP2Y(1), PIP_X(id_W252) - 2., WIRE_Y(0)}}},
+        {id_E25_loop0,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W251), HOP2Y(3)},
+          {PIP_X(id_W251), HOP2Y(3), PIP_X(id_W251), WIRE_Y(0)},
+          {PIP_X(id_W251), HOP2Y(1), PIP_X(id_W252) - 1., HOP2Y(1)},
+          {PIP_X(id_W252) - 1., HOP2Y(1), PIP_X(id_W252) - 1., WIRE_Y(0)}}},
+        {id_W25_loop0,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E251), HOP2Y(2)},
+          {PIP_X(id_E251), HOP2Y(2), PIP_X(id_E251), WIRE_Y(0)},
+          {PIP_X(id_E251), HOP2Y(0), PIP_X(id_E252) + 1., HOP2Y(0)},
+          {PIP_X(id_E252) + 1., HOP2Y(0), PIP_X(id_E252) + 1., WIRE_Y(0)}}},
+        {id_E25_loop1,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
+          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
+          {PIP_X(id_E251) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W252) + 1., HOP2Y(1)},
+          {PIP_X(id_W252) + 1., HOP2Y(1), PIP_X(id_W252) + 1., WIRE_Y(0)}}},
+        {id_W25_loop1,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
+          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
+          {PIP_X(id_W251) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E252) - 1., HOP2Y(0)},
+          {PIP_X(id_E252) - 1., HOP2Y(0), PIP_X(id_E252) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 6)
+        {id_E26,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
+          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
+          {PIP_X(id_E261) + 1., HOP2Y(0), PIP_X(id_E262) + 2., HOP2Y(0)},
+          {PIP_X(id_E262) + 2., HOP2Y(0), PIP_X(id_E262) + 2., WIRE_Y(0)}}},
+        {id_W26,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
+          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
+          {PIP_X(id_W261) - 1., HOP2Y(1), PIP_X(id_W262) - 2., HOP2Y(1)},
+          {PIP_X(id_W262) - 2., HOP2Y(1), PIP_X(id_W262) - 2., WIRE_Y(0)}}},
+        {id_E26_loop0,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W261), HOP2Y(3)},
+          {PIP_X(id_W261), HOP2Y(3), PIP_X(id_W261), WIRE_Y(0)},
+          {PIP_X(id_W261), HOP2Y(1), PIP_X(id_W262) - 1., HOP2Y(1)},
+          {PIP_X(id_W262) - 1., HOP2Y(1), PIP_X(id_W262) - 1., WIRE_Y(0)}}},
+        {id_W26_loop0,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E261), HOP2Y(2)},
+          {PIP_X(id_E261), HOP2Y(2), PIP_X(id_E261), WIRE_Y(0)},
+          {PIP_X(id_E261), HOP2Y(0), PIP_X(id_E262) + 1., HOP2Y(0)},
+          {PIP_X(id_E262) + 1., HOP2Y(0), PIP_X(id_E262) + 1., WIRE_Y(0)}}},
+        {id_E26_loop1,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
+          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
+          {PIP_X(id_E261) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W262) + 1., HOP2Y(1)},
+          {PIP_X(id_W262) + 1., HOP2Y(1), PIP_X(id_W262) + 1., WIRE_Y(0)}}},
+        {id_W26_loop1,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
+          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
+          {PIP_X(id_W261) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E262) - 1., HOP2Y(0)},
+          {PIP_X(id_E262) - 1., HOP2Y(0), PIP_X(id_E262) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 7)
+        {id_E27,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
+          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
+          {PIP_X(id_E271) + 1., HOP2Y(0), PIP_X(id_E272) + 2., HOP2Y(0)},
+          {PIP_X(id_E272) + 2., HOP2Y(0), PIP_X(id_E272) + 2., WIRE_Y(0)}}},
+        {id_W27,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
+          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
+          {PIP_X(id_W271) - 1., HOP2Y(1), PIP_X(id_W272) - 2., HOP2Y(1)},
+          {PIP_X(id_W272) - 2., HOP2Y(1), PIP_X(id_W272) - 2., WIRE_Y(0)}}},
+        {id_E27_loop0,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W271), HOP2Y(3)},
+          {PIP_X(id_W271), HOP2Y(3), PIP_X(id_W271), WIRE_Y(0)},
+          {PIP_X(id_W271), HOP2Y(1), PIP_X(id_W272) - 1., HOP2Y(1)},
+          {PIP_X(id_W272) - 1., HOP2Y(1), PIP_X(id_W272) - 1., WIRE_Y(0)}}},
+        {id_W27_loop0,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E271), HOP2Y(2)},
+          {PIP_X(id_E271), HOP2Y(2), PIP_X(id_E271), WIRE_Y(0)},
+          {PIP_X(id_E271), HOP2Y(0), PIP_X(id_E272) + 1., HOP2Y(0)},
+          {PIP_X(id_E272) + 1., HOP2Y(0), PIP_X(id_E272) + 1., WIRE_Y(0)}}},
+        {id_E27_loop1,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
+          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
+          {PIP_X(id_E271) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W272) + 1., HOP2Y(1)},
+          {PIP_X(id_W272) + 1., HOP2Y(1), PIP_X(id_W272) + 1., WIRE_Y(0)}}},
+        {id_W27_loop1,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
+          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
+          {PIP_X(id_W271) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E272) - 1., HOP2Y(0)},
+          {PIP_X(id_E272) - 1., HOP2Y(0), PIP_X(id_E272) - 1., WIRE_Y(0)}}},
+
+// clock branches
+#define CLK_GBO0_Y 41.f
+#define CLK_GBO1_Y 46.f
+// 4 hop
+#define HOP4Y_START (CLK_GBO0_Y + 10.f)
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START)
+        {id_E80,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
+          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E808) + 8., HOP4Y(0)},
+          {PIP_X(id_E808) + 8, HOP4Y(0), PIP_X(id_E808) + 8., WIRE_Y(0)}}},
+        {id_W80,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
+          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W808) - 8., HOP4Y(1)},
+          {PIP_X(id_W808) - 8, HOP4Y(1), PIP_X(id_W808) - 8., WIRE_Y(0)}}},
+        {id_E80_loop0,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W800) - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - 0., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W800) - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W800) - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W800) - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W804) - 3., HOP4Y(9), PIP_X(id_W804) - 3., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W800) - 4., HOP4Y(7)},
+          {PIP_X(id_W800) - 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W800) - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W800) - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W808) - 7., HOP4Y(1)},
+          {PIP_X(id_W808) - 7, HOP4Y(1), PIP_X(id_W808) - 7., WIRE_Y(0)}}},
+        {id_E80_loop1,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W800) + 1., HOP4Y(13)},
+          {PIP_X(id_W800) + 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W800) - 0., HOP4Y(11)},
+          {PIP_X(id_W800) - 0., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W800) - 1., HOP4Y(9)},
+          {PIP_X(id_W804) - 1., HOP4Y(9), PIP_X(id_W804) - 1., WIRE_Y(0)},
+          {PIP_X(id_W800) - 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W800) - 2., HOP4Y(7)},
+          {PIP_X(id_W800) - 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W800) - 3., HOP4Y(5)},
+          {PIP_X(id_W800) - 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W800) - 4., HOP4Y(3)},
+          {PIP_X(id_W800) - 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W808) - 5., HOP4Y(1)},
+          {PIP_X(id_W808) - 5., HOP4Y(1), PIP_X(id_W808) - 5., WIRE_Y(0)}}},
+        {id_E80_loop2,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W800) + 2., HOP4Y(11)},
+          {PIP_X(id_W800) + 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W800) + 1., HOP4Y(9)},
+          {PIP_X(id_W804) + 1., HOP4Y(9), PIP_X(id_W804) + 1., WIRE_Y(0)},
+          {PIP_X(id_W800) + 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W800) + 0., HOP4Y(7)},
+          {PIP_X(id_W800) + 0., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W800) - 1., HOP4Y(5)},
+          {PIP_X(id_W800) - 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W800) - 2., HOP4Y(3)},
+          {PIP_X(id_W800) - 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W808) - 3., HOP4Y(1)},
+          {PIP_X(id_W808) - 3., HOP4Y(1), PIP_X(id_W808) - 3., WIRE_Y(0)}}},
+        {id_E80_loop3,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W800) + 3., HOP4Y(9)},
+          {PIP_X(id_W804) + 3., HOP4Y(9), PIP_X(id_W804) + 3., WIRE_Y(0)},
+          {PIP_X(id_W800) + 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W800) + 2., HOP4Y(7)},
+          {PIP_X(id_W800) + 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W800) + 1., HOP4Y(5)},
+          {PIP_X(id_W800) + 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W800) - 0., HOP4Y(3)},
+          {PIP_X(id_W800) - 0., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W808) - 1., HOP4Y(1)},
+          {PIP_X(id_W808) - 1., HOP4Y(1), PIP_X(id_W808) - 1., WIRE_Y(0)}}},
+        {id_E80_loop4,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W800) + 4., HOP4Y(7)},
+          {PIP_X(id_W800) + 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W800) + 3., HOP4Y(5)},
+          {PIP_X(id_W800) + 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W800) + 2., HOP4Y(3)},
+          {PIP_X(id_W800) + 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W808) + 1., HOP4Y(1)},
+          {PIP_X(id_W808) + 1., HOP4Y(1), PIP_X(id_W808) + 1., WIRE_Y(0)}}},
+        {id_E80_loop5,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W800) + 5., HOP4Y(5)},
+          {PIP_X(id_W800) + 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W800) + 4., HOP4Y(3)},
+          {PIP_X(id_W800) + 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W808) + 3., HOP4Y(1)},
+          {PIP_X(id_W808) + 3., HOP4Y(1), PIP_X(id_W808) + 3., WIRE_Y(0)}}},
+        {id_E80_loop6,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W800) + 6., HOP4Y(3)},
+          {PIP_X(id_W800) + 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W808) + 5., HOP4Y(1)},
+          {PIP_X(id_W808) + 5., HOP4Y(1), PIP_X(id_W808) + 5., WIRE_Y(0)}}},
+        {id_E80_loop7,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
+          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W808) + 7., HOP4Y(1)},
+          {PIP_X(id_W808) + 7., HOP4Y(1), PIP_X(id_W808) + 7., WIRE_Y(0)}}},
+        {id_W80_loop0,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W808) + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + 0., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W808) + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W808) + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W808) + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E804) + 3., HOP4Y(8), PIP_X(id_E804) + 3., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W808) + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W808) + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W808) + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E808) + 7., HOP4Y(0)},
+          {PIP_X(id_E808) + 7., HOP4Y(0), PIP_X(id_E808) + 7., WIRE_Y(0)}}},
+        {id_W80_loop1,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W808) - 1., HOP4Y(12)},
+          {PIP_X(id_W808) - 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W808) + 0., HOP4Y(10)},
+          {PIP_X(id_W808) + 0., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W808) + 1., HOP4Y(8)},
+          {PIP_X(id_W808) + 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E804) + 1., HOP4Y(8), PIP_X(id_E804) + 1., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W808) + 2., HOP4Y(6)},
+          {PIP_X(id_W808) + 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W808) + 3., HOP4Y(4)},
+          {PIP_X(id_W808) + 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W808) + 4., HOP4Y(2)},
+          {PIP_X(id_W808) + 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E808) + 5., HOP4Y(0)},
+          {PIP_X(id_E808) + 5., HOP4Y(0), PIP_X(id_E808) + 5., WIRE_Y(0)}}},
+        {id_W80_loop2,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W808) - 2., HOP4Y(10)},
+          {PIP_X(id_W808) - 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W808) - 1., HOP4Y(8)},
+          {PIP_X(id_W808) - 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E804) - 1., HOP4Y(8), PIP_X(id_E804) - 1., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W808) + 0., HOP4Y(6)},
+          {PIP_X(id_W808) + 0., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W808) + 1., HOP4Y(4)},
+          {PIP_X(id_W808) + 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W808) + 2., HOP4Y(2)},
+          {PIP_X(id_W808) + 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E808) + 3., HOP4Y(0)},
+          {PIP_X(id_E808) + 3., HOP4Y(0), PIP_X(id_E808) + 3., WIRE_Y(0)}}},
+        {id_W80_loop3,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W808) - 3., HOP4Y(8)},
+          {PIP_X(id_W808) - 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E804) - 3., HOP4Y(8), PIP_X(id_E804) - 3., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W808) - 2., HOP4Y(6)},
+          {PIP_X(id_W808) - 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W808) - 1., HOP4Y(4)},
+          {PIP_X(id_W808) - 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W808) + 0., HOP4Y(2)},
+          {PIP_X(id_W808) + 0., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E808) + 1., HOP4Y(0)},
+          {PIP_X(id_E808) + 1., HOP4Y(0), PIP_X(id_E808) + 1., WIRE_Y(0)}}},
+        {id_W80_loop4,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W804) - 4., HOP4Y(6), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W808) - 4., HOP4Y(6)},
+          {PIP_X(id_W808) - 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W808) - 3., HOP4Y(4)},
+          {PIP_X(id_W808) - 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W808) - 2., HOP4Y(2)},
+          {PIP_X(id_W808) - 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E808) - 1., HOP4Y(0)},
+          {PIP_X(id_E808) - 1., HOP4Y(0), PIP_X(id_E808) - 1., WIRE_Y(0)}}},
+        {id_W80_loop5,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W808) - 5., HOP4Y(4)},
+          {PIP_X(id_W808) - 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W808) - 4., HOP4Y(2)},
+          {PIP_X(id_W808) - 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E808) - 3., HOP4Y(0)},
+          {PIP_X(id_E808) - 3., HOP4Y(0), PIP_X(id_E808) - 3., WIRE_Y(0)}}},
+        {id_W80_loop6,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W808) - 6., HOP4Y(2)},
+          {PIP_X(id_W808) - 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E808) - 5., HOP4Y(0)},
+          {PIP_X(id_E808) - 5., HOP4Y(0), PIP_X(id_E808) - 5., WIRE_Y(0)}}},
+        {id_W80_loop7,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
+          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E808) - 7., HOP4Y(0)},
+          {PIP_X(id_E808) - 7., HOP4Y(0), PIP_X(id_E808) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f)
+        {id_E81,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
+          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E818) + 8., HOP4Y(0)},
+          {PIP_X(id_E818) + 8, HOP4Y(0), PIP_X(id_E818) + 8., WIRE_Y(0)}}},
+        {id_W81,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
+          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W818) - 8., HOP4Y(1)},
+          {PIP_X(id_W818) - 8, HOP4Y(1), PIP_X(id_W818) - 8., WIRE_Y(0)}}},
+        {id_E81_loop0,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W810) - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - 0., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W810) - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W810) - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W810) - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W814) - 3., HOP4Y(9), PIP_X(id_W814) - 3., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W810) - 4., HOP4Y(7)},
+          {PIP_X(id_W810) - 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W810) - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W810) - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W818) - 7., HOP4Y(1)},
+          {PIP_X(id_W818) - 7, HOP4Y(1), PIP_X(id_W818) - 7., WIRE_Y(0)}}},
+        {id_E81_loop1,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W810) + 1., HOP4Y(13)},
+          {PIP_X(id_W810) + 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W810) - 0., HOP4Y(11)},
+          {PIP_X(id_W810) - 0., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W810) - 1., HOP4Y(9)},
+          {PIP_X(id_W814) - 1., HOP4Y(9), PIP_X(id_W814) - 1., WIRE_Y(0)},
+          {PIP_X(id_W810) - 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W810) - 2., HOP4Y(7)},
+          {PIP_X(id_W810) - 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W810) - 3., HOP4Y(5)},
+          {PIP_X(id_W810) - 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W810) - 4., HOP4Y(3)},
+          {PIP_X(id_W810) - 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W818) - 5., HOP4Y(1)},
+          {PIP_X(id_W818) - 5., HOP4Y(1), PIP_X(id_W818) - 5., WIRE_Y(0)}}},
+        {id_E81_loop2,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W810) + 2., HOP4Y(11)},
+          {PIP_X(id_W810) + 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W810) + 1., HOP4Y(9)},
+          {PIP_X(id_W814) + 1., HOP4Y(9), PIP_X(id_W814) + 1., WIRE_Y(0)},
+          {PIP_X(id_W810) + 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W810) + 0., HOP4Y(7)},
+          {PIP_X(id_W810) + 0., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W810) - 1., HOP4Y(5)},
+          {PIP_X(id_W810) - 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W810) - 2., HOP4Y(3)},
+          {PIP_X(id_W810) - 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W818) - 3., HOP4Y(1)},
+          {PIP_X(id_W818) - 3., HOP4Y(1), PIP_X(id_W818) - 3., WIRE_Y(0)}}},
+        {id_E81_loop3,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W810) + 3., HOP4Y(9)},
+          {PIP_X(id_W814) + 3., HOP4Y(9), PIP_X(id_W814) + 3., WIRE_Y(0)},
+          {PIP_X(id_W810) + 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W810) + 2., HOP4Y(7)},
+          {PIP_X(id_W810) + 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W810) + 1., HOP4Y(5)},
+          {PIP_X(id_W810) + 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W810) - 0., HOP4Y(3)},
+          {PIP_X(id_W810) - 0., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W818) - 1., HOP4Y(1)},
+          {PIP_X(id_W818) - 1., HOP4Y(1), PIP_X(id_W818) - 1., WIRE_Y(0)}}},
+        {id_E81_loop4,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W810) + 4., HOP4Y(7)},
+          {PIP_X(id_W810) + 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W810) + 3., HOP4Y(5)},
+          {PIP_X(id_W810) + 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W810) + 2., HOP4Y(3)},
+          {PIP_X(id_W810) + 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W818) + 1., HOP4Y(1)},
+          {PIP_X(id_W818) + 1., HOP4Y(1), PIP_X(id_W818) + 1., WIRE_Y(0)}}},
+        {id_E81_loop5,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W810) + 5., HOP4Y(5)},
+          {PIP_X(id_W810) + 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W810) + 4., HOP4Y(3)},
+          {PIP_X(id_W810) + 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W818) + 3., HOP4Y(1)},
+          {PIP_X(id_W818) + 3., HOP4Y(1), PIP_X(id_W818) + 3., WIRE_Y(0)}}},
+        {id_E81_loop6,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W810) + 6., HOP4Y(3)},
+          {PIP_X(id_W810) + 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W818) + 5., HOP4Y(1)},
+          {PIP_X(id_W818) + 5., HOP4Y(1), PIP_X(id_W818) + 5., WIRE_Y(0)}}},
+        {id_E81_loop7,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
+          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W818) + 7., HOP4Y(1)},
+          {PIP_X(id_W818) + 7., HOP4Y(1), PIP_X(id_W818) + 7., WIRE_Y(0)}}},
+        {id_W81_loop0,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W818) + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + 0., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W818) + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W818) + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W818) + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E814) + 3., HOP4Y(8), PIP_X(id_E814) + 3., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W818) + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W818) + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W818) + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E818) + 7., HOP4Y(0)},
+          {PIP_X(id_E818) + 7., HOP4Y(0), PIP_X(id_E818) + 7., WIRE_Y(0)}}},
+        {id_W81_loop1,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W818) - 1., HOP4Y(12)},
+          {PIP_X(id_W818) - 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W818) + 0., HOP4Y(10)},
+          {PIP_X(id_W818) + 0., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W818) + 1., HOP4Y(8)},
+          {PIP_X(id_W818) + 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E814) + 1., HOP4Y(8), PIP_X(id_E814) + 1., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W818) + 2., HOP4Y(6)},
+          {PIP_X(id_W818) + 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W818) + 3., HOP4Y(4)},
+          {PIP_X(id_W818) + 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W818) + 4., HOP4Y(2)},
+          {PIP_X(id_W818) + 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E818) + 5., HOP4Y(0)},
+          {PIP_X(id_E818) + 5., HOP4Y(0), PIP_X(id_E818) + 5., WIRE_Y(0)}}},
+        {id_W81_loop2,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W818) - 2., HOP4Y(10)},
+          {PIP_X(id_W818) - 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W818) - 1., HOP4Y(8)},
+          {PIP_X(id_W818) - 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E814) - 1., HOP4Y(8), PIP_X(id_E814) - 1., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W818) + 0., HOP4Y(6)},
+          {PIP_X(id_W818) + 0., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W818) + 1., HOP4Y(4)},
+          {PIP_X(id_W818) + 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W818) + 2., HOP4Y(2)},
+          {PIP_X(id_W818) + 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E818) + 3., HOP4Y(0)},
+          {PIP_X(id_E818) + 3., HOP4Y(0), PIP_X(id_E818) + 3., WIRE_Y(0)}}},
+        {id_W81_loop3,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W818) - 3., HOP4Y(8)},
+          {PIP_X(id_W818) - 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E814) - 3., HOP4Y(8), PIP_X(id_E814) - 3., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W818) - 2., HOP4Y(6)},
+          {PIP_X(id_W818) - 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W818) - 1., HOP4Y(4)},
+          {PIP_X(id_W818) - 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W818) + 0., HOP4Y(2)},
+          {PIP_X(id_W818) + 0., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E818) + 1., HOP4Y(0)},
+          {PIP_X(id_E818) + 1., HOP4Y(0), PIP_X(id_E818) + 1., WIRE_Y(0)}}},
+        {id_W81_loop4,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W814) - 4., HOP4Y(6), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W818) - 4., HOP4Y(6)},
+          {PIP_X(id_W818) - 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W818) - 3., HOP4Y(4)},
+          {PIP_X(id_W818) - 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W818) - 2., HOP4Y(2)},
+          {PIP_X(id_W818) - 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E818) - 1., HOP4Y(0)},
+          {PIP_X(id_E818) - 1., HOP4Y(0), PIP_X(id_E818) - 1., WIRE_Y(0)}}},
+        {id_W81_loop5,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W818) - 5., HOP4Y(4)},
+          {PIP_X(id_W818) - 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W818) - 4., HOP4Y(2)},
+          {PIP_X(id_W818) - 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E818) - 3., HOP4Y(0)},
+          {PIP_X(id_E818) - 3., HOP4Y(0), PIP_X(id_E818) - 3., WIRE_Y(0)}}},
+        {id_W81_loop6,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W818) - 6., HOP4Y(2)},
+          {PIP_X(id_W818) - 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E818) - 5., HOP4Y(0)},
+          {PIP_X(id_E818) - 5., HOP4Y(0), PIP_X(id_E818) - 5., WIRE_Y(0)}}},
+        {id_W81_loop7,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
+          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E818) - 7., HOP4Y(0)},
+          {PIP_X(id_E818) - 7., HOP4Y(0), PIP_X(id_E818) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f)
+        {id_E82,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
+          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E828) + 8., HOP4Y(0)},
+          {PIP_X(id_E828) + 8, HOP4Y(0), PIP_X(id_E828) + 8., WIRE_Y(0)}}},
+        {id_W82,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
+          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W828) - 8., HOP4Y(1)},
+          {PIP_X(id_W828) - 8, HOP4Y(1), PIP_X(id_W828) - 8., WIRE_Y(0)}}},
+        {id_E82_loop0,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W820) - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - 0., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W820) - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W820) - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W820) - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W824) - 3., HOP4Y(9), PIP_X(id_W824) - 3., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W820) - 4., HOP4Y(7)},
+          {PIP_X(id_W820) - 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W820) - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W820) - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W828) - 7., HOP4Y(1)},
+          {PIP_X(id_W828) - 7, HOP4Y(1), PIP_X(id_W828) - 7., WIRE_Y(0)}}},
+        {id_E82_loop1,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W820) + 1., HOP4Y(13)},
+          {PIP_X(id_W820) + 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W820) - 0., HOP4Y(11)},
+          {PIP_X(id_W820) - 0., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W820) - 1., HOP4Y(9)},
+          {PIP_X(id_W824) - 1., HOP4Y(9), PIP_X(id_W824) - 1., WIRE_Y(0)},
+          {PIP_X(id_W820) - 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W820) - 2., HOP4Y(7)},
+          {PIP_X(id_W820) - 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W820) - 3., HOP4Y(5)},
+          {PIP_X(id_W820) - 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W820) - 4., HOP4Y(3)},
+          {PIP_X(id_W820) - 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W828) - 5., HOP4Y(1)},
+          {PIP_X(id_W828) - 5., HOP4Y(1), PIP_X(id_W828) - 5., WIRE_Y(0)}}},
+        {id_E82_loop2,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W820) + 2., HOP4Y(11)},
+          {PIP_X(id_W820) + 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W820) + 1., HOP4Y(9)},
+          {PIP_X(id_W824) + 1., HOP4Y(9), PIP_X(id_W824) + 1., WIRE_Y(0)},
+          {PIP_X(id_W820) + 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W820) + 0., HOP4Y(7)},
+          {PIP_X(id_W820) + 0., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W820) - 1., HOP4Y(5)},
+          {PIP_X(id_W820) - 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W820) - 2., HOP4Y(3)},
+          {PIP_X(id_W820) - 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W828) - 3., HOP4Y(1)},
+          {PIP_X(id_W828) - 3., HOP4Y(1), PIP_X(id_W828) - 3., WIRE_Y(0)}}},
+        {id_E82_loop3,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W820) + 3., HOP4Y(9)},
+          {PIP_X(id_W824) + 3., HOP4Y(9), PIP_X(id_W824) + 3., WIRE_Y(0)},
+          {PIP_X(id_W820) + 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W820) + 2., HOP4Y(7)},
+          {PIP_X(id_W820) + 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W820) + 1., HOP4Y(5)},
+          {PIP_X(id_W820) + 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W820) - 0., HOP4Y(3)},
+          {PIP_X(id_W820) - 0., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W828) - 1., HOP4Y(1)},
+          {PIP_X(id_W828) - 1., HOP4Y(1), PIP_X(id_W828) - 1., WIRE_Y(0)}}},
+        {id_E82_loop4,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W820) + 4., HOP4Y(7)},
+          {PIP_X(id_W820) + 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W820) + 3., HOP4Y(5)},
+          {PIP_X(id_W820) + 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W820) + 2., HOP4Y(3)},
+          {PIP_X(id_W820) + 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W828) + 1., HOP4Y(1)},
+          {PIP_X(id_W828) + 1., HOP4Y(1), PIP_X(id_W828) + 1., WIRE_Y(0)}}},
+        {id_E82_loop5,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W820) + 5., HOP4Y(5)},
+          {PIP_X(id_W820) + 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W820) + 4., HOP4Y(3)},
+          {PIP_X(id_W820) + 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W828) + 3., HOP4Y(1)},
+          {PIP_X(id_W828) + 3., HOP4Y(1), PIP_X(id_W828) + 3., WIRE_Y(0)}}},
+        {id_E82_loop6,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W820) + 6., HOP4Y(3)},
+          {PIP_X(id_W820) + 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W828) + 5., HOP4Y(1)},
+          {PIP_X(id_W828) + 5., HOP4Y(1), PIP_X(id_W828) + 5., WIRE_Y(0)}}},
+        {id_E82_loop7,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
+          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W828) + 7., HOP4Y(1)},
+          {PIP_X(id_W828) + 7., HOP4Y(1), PIP_X(id_W828) + 7., WIRE_Y(0)}}},
+        {id_W82_loop0,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W828) + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + 0., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W828) + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W828) + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W828) + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E824) + 3., HOP4Y(8), PIP_X(id_E824) + 3., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W828) + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W828) + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W828) + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E828) + 7., HOP4Y(0)},
+          {PIP_X(id_E828) + 7., HOP4Y(0), PIP_X(id_E828) + 7., WIRE_Y(0)}}},
+        {id_W82_loop1,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W828) - 1., HOP4Y(12)},
+          {PIP_X(id_W828) - 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W828) + 0., HOP4Y(10)},
+          {PIP_X(id_W828) + 0., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W828) + 1., HOP4Y(8)},
+          {PIP_X(id_W828) + 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E824) + 1., HOP4Y(8), PIP_X(id_E824) + 1., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W828) + 2., HOP4Y(6)},
+          {PIP_X(id_W828) + 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W828) + 3., HOP4Y(4)},
+          {PIP_X(id_W828) + 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W828) + 4., HOP4Y(2)},
+          {PIP_X(id_W828) + 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E828) + 5., HOP4Y(0)},
+          {PIP_X(id_E828) + 5., HOP4Y(0), PIP_X(id_E828) + 5., WIRE_Y(0)}}},
+        {id_W82_loop2,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W828) - 2., HOP4Y(10)},
+          {PIP_X(id_W828) - 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W828) - 1., HOP4Y(8)},
+          {PIP_X(id_W828) - 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E824) - 1., HOP4Y(8), PIP_X(id_E824) - 1., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W828) + 0., HOP4Y(6)},
+          {PIP_X(id_W828) + 0., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W828) + 1., HOP4Y(4)},
+          {PIP_X(id_W828) + 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W828) + 2., HOP4Y(2)},
+          {PIP_X(id_W828) + 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E828) + 3., HOP4Y(0)},
+          {PIP_X(id_E828) + 3., HOP4Y(0), PIP_X(id_E828) + 3., WIRE_Y(0)}}},
+        {id_W82_loop3,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W828) - 3., HOP4Y(8)},
+          {PIP_X(id_W828) - 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E824) - 3., HOP4Y(8), PIP_X(id_E824) - 3., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W828) - 2., HOP4Y(6)},
+          {PIP_X(id_W828) - 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W828) - 1., HOP4Y(4)},
+          {PIP_X(id_W828) - 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W828) + 0., HOP4Y(2)},
+          {PIP_X(id_W828) + 0., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E828) + 1., HOP4Y(0)},
+          {PIP_X(id_E828) + 1., HOP4Y(0), PIP_X(id_E828) + 1., WIRE_Y(0)}}},
+        {id_W82_loop4,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W824) - 4., HOP4Y(6), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W828) - 4., HOP4Y(6)},
+          {PIP_X(id_W828) - 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W828) - 3., HOP4Y(4)},
+          {PIP_X(id_W828) - 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W828) - 2., HOP4Y(2)},
+          {PIP_X(id_W828) - 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E828) - 1., HOP4Y(0)},
+          {PIP_X(id_E828) - 1., HOP4Y(0), PIP_X(id_E828) - 1., WIRE_Y(0)}}},
+        {id_W82_loop5,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W828) - 5., HOP4Y(4)},
+          {PIP_X(id_W828) - 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W828) - 4., HOP4Y(2)},
+          {PIP_X(id_W828) - 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E828) - 3., HOP4Y(0)},
+          {PIP_X(id_E828) - 3., HOP4Y(0), PIP_X(id_E828) - 3., WIRE_Y(0)}}},
+        {id_W82_loop6,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W828) - 6., HOP4Y(2)},
+          {PIP_X(id_W828) - 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E828) - 5., HOP4Y(0)},
+          {PIP_X(id_E828) - 5., HOP4Y(0), PIP_X(id_E828) - 5., WIRE_Y(0)}}},
+        {id_W82_loop7,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
+          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E828) - 7., HOP4Y(0)},
+          {PIP_X(id_E828) - 7., HOP4Y(0), PIP_X(id_E828) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f + 18.f)
+        {id_E83,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
+          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E838) + 8., HOP4Y(0)},
+          {PIP_X(id_E838) + 8, HOP4Y(0), PIP_X(id_E838) + 8., WIRE_Y(0)}}},
+        {id_W83,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
+          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W838) - 8., HOP4Y(1)},
+          {PIP_X(id_W838) - 8, HOP4Y(1), PIP_X(id_W838) - 8., WIRE_Y(0)}}},
+        {id_E83_loop0,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W830) - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - 0., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W830) - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W830) - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W830) - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W834) - 3., HOP4Y(9), PIP_X(id_W834) - 3., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W830) - 4., HOP4Y(7)},
+          {PIP_X(id_W830) - 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W830) - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W830) - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W838) - 7., HOP4Y(1)},
+          {PIP_X(id_W838) - 7, HOP4Y(1), PIP_X(id_W838) - 7., WIRE_Y(0)}}},
+        {id_E83_loop1,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W830) + 1., HOP4Y(13)},
+          {PIP_X(id_W830) + 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W830) - 0., HOP4Y(11)},
+          {PIP_X(id_W830) - 0., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W830) - 1., HOP4Y(9)},
+          {PIP_X(id_W834) - 1., HOP4Y(9), PIP_X(id_W834) - 1., WIRE_Y(0)},
+          {PIP_X(id_W830) - 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W830) - 2., HOP4Y(7)},
+          {PIP_X(id_W830) - 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W830) - 3., HOP4Y(5)},
+          {PIP_X(id_W830) - 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W830) - 4., HOP4Y(3)},
+          {PIP_X(id_W830) - 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W838) - 5., HOP4Y(1)},
+          {PIP_X(id_W838) - 5., HOP4Y(1), PIP_X(id_W838) - 5., WIRE_Y(0)}}},
+        {id_E83_loop2,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W830) + 2., HOP4Y(11)},
+          {PIP_X(id_W830) + 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W830) + 1., HOP4Y(9)},
+          {PIP_X(id_W834) + 1., HOP4Y(9), PIP_X(id_W834) + 1., WIRE_Y(0)},
+          {PIP_X(id_W830) + 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W830) + 0., HOP4Y(7)},
+          {PIP_X(id_W830) + 0., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W830) - 1., HOP4Y(5)},
+          {PIP_X(id_W830) - 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W830) - 2., HOP4Y(3)},
+          {PIP_X(id_W830) - 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W838) - 3., HOP4Y(1)},
+          {PIP_X(id_W838) - 3., HOP4Y(1), PIP_X(id_W838) - 3., WIRE_Y(0)}}},
+        {id_E83_loop3,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W830) + 3., HOP4Y(9)},
+          {PIP_X(id_W834) + 3., HOP4Y(9), PIP_X(id_W834) + 3., WIRE_Y(0)},
+          {PIP_X(id_W830) + 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W830) + 2., HOP4Y(7)},
+          {PIP_X(id_W830) + 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W830) + 1., HOP4Y(5)},
+          {PIP_X(id_W830) + 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W830) - 0., HOP4Y(3)},
+          {PIP_X(id_W830) - 0., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W838) - 1., HOP4Y(1)},
+          {PIP_X(id_W838) - 1., HOP4Y(1), PIP_X(id_W838) - 1., WIRE_Y(0)}}},
+        {id_E83_loop4,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W830) + 4., HOP4Y(7)},
+          {PIP_X(id_W830) + 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W830) + 3., HOP4Y(5)},
+          {PIP_X(id_W830) + 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W830) + 2., HOP4Y(3)},
+          {PIP_X(id_W830) + 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W838) + 1., HOP4Y(1)},
+          {PIP_X(id_W838) + 1., HOP4Y(1), PIP_X(id_W838) + 1., WIRE_Y(0)}}},
+        {id_E83_loop5,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W830) + 5., HOP4Y(5)},
+          {PIP_X(id_W830) + 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W830) + 4., HOP4Y(3)},
+          {PIP_X(id_W830) + 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W838) + 3., HOP4Y(1)},
+          {PIP_X(id_W838) + 3., HOP4Y(1), PIP_X(id_W838) + 3., WIRE_Y(0)}}},
+        {id_E83_loop6,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W830) + 6., HOP4Y(3)},
+          {PIP_X(id_W830) + 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W838) + 5., HOP4Y(1)},
+          {PIP_X(id_W838) + 5., HOP4Y(1), PIP_X(id_W838) + 5., WIRE_Y(0)}}},
+        {id_E83_loop7,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
+          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W838) + 7., HOP4Y(1)},
+          {PIP_X(id_W838) + 7., HOP4Y(1), PIP_X(id_W838) + 7., WIRE_Y(0)}}},
+        {id_W83_loop0,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W838) + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + 0., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W838) + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W838) + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W838) + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E834) + 3., HOP4Y(8), PIP_X(id_E834) + 3., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W838) + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W838) + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W838) + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E838) + 7., HOP4Y(0)},
+          {PIP_X(id_E838) + 7., HOP4Y(0), PIP_X(id_E838) + 7., WIRE_Y(0)}}},
+        {id_W83_loop1,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W838) - 1., HOP4Y(12)},
+          {PIP_X(id_W838) - 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W838) + 0., HOP4Y(10)},
+          {PIP_X(id_W838) + 0., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W838) + 1., HOP4Y(8)},
+          {PIP_X(id_W838) + 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E834) + 1., HOP4Y(8), PIP_X(id_E834) + 1., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W838) + 2., HOP4Y(6)},
+          {PIP_X(id_W838) + 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W838) + 3., HOP4Y(4)},
+          {PIP_X(id_W838) + 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W838) + 4., HOP4Y(2)},
+          {PIP_X(id_W838) + 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E838) + 5., HOP4Y(0)},
+          {PIP_X(id_E838) + 5., HOP4Y(0), PIP_X(id_E838) + 5., WIRE_Y(0)}}},
+        {id_W83_loop2,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W838) - 2., HOP4Y(10)},
+          {PIP_X(id_W838) - 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W838) - 1., HOP4Y(8)},
+          {PIP_X(id_W838) - 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E834) - 1., HOP4Y(8), PIP_X(id_E834) - 1., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W838) + 0., HOP4Y(6)},
+          {PIP_X(id_W838) + 0., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W838) + 1., HOP4Y(4)},
+          {PIP_X(id_W838) + 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W838) + 2., HOP4Y(2)},
+          {PIP_X(id_W838) + 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E838) + 3., HOP4Y(0)},
+          {PIP_X(id_E838) + 3., HOP4Y(0), PIP_X(id_E838) + 3., WIRE_Y(0)}}},
+        {id_W83_loop3,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W838) - 3., HOP4Y(8)},
+          {PIP_X(id_W838) - 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E834) - 3., HOP4Y(8), PIP_X(id_E834) - 3., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W838) - 2., HOP4Y(6)},
+          {PIP_X(id_W838) - 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W838) - 1., HOP4Y(4)},
+          {PIP_X(id_W838) - 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W838) + 0., HOP4Y(2)},
+          {PIP_X(id_W838) + 0., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E838) + 1., HOP4Y(0)},
+          {PIP_X(id_E838) + 1., HOP4Y(0), PIP_X(id_E838) + 1., WIRE_Y(0)}}},
+        {id_W83_loop4,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W834) - 4., HOP4Y(6), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W838) - 4., HOP4Y(6)},
+          {PIP_X(id_W838) - 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W838) - 3., HOP4Y(4)},
+          {PIP_X(id_W838) - 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W838) - 2., HOP4Y(2)},
+          {PIP_X(id_W838) - 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E838) - 1., HOP4Y(0)},
+          {PIP_X(id_E838) - 1., HOP4Y(0), PIP_X(id_E838) - 1., WIRE_Y(0)}}},
+        {id_W83_loop5,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W838) - 5., HOP4Y(4)},
+          {PIP_X(id_W838) - 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W838) - 4., HOP4Y(2)},
+          {PIP_X(id_W838) - 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E838) - 3., HOP4Y(0)},
+          {PIP_X(id_E838) - 3., HOP4Y(0), PIP_X(id_E838) - 3., WIRE_Y(0)}}},
+        {id_W83_loop6,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W838) - 6., HOP4Y(2)},
+          {PIP_X(id_W838) - 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E838) - 5., HOP4Y(0)},
+          {PIP_X(id_E838) - 5., HOP4Y(0), PIP_X(id_E838) - 5., WIRE_Y(0)}}},
+        {id_W83_loop7,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
+          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E838) - 7., HOP4Y(0)},
+          {PIP_X(id_E838) - 7., HOP4Y(0), PIP_X(id_E838) - 7., WIRE_Y(0)}}},
+};
+
+void gfxCreateBelDecals(Arch *arch);
+void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel);
+void gfxSetIOBWireDecals(Arch *arch, BelInfo &bel);
+void gfxSetIOBSWireDecals(Arch *arch, BelInfo &bel);
+void gfxSetPipDefaultDecal(Arch *arch, PipInfo &pip);
+void gfxSetWireDefaultDecal(Arch *arch, WireInfo &wire);
+DecalXY gfxGetLutGroupDecalXY(int x, int y, int z);
+DecalXY gfxGetCruGroupDecalXY(int x, int y);
+
+NEXTPNR_NAMESPACE_END
+
+#endif // GFX_H
diff --git a/gowin/main.cc b/gowin/main.cc
index 66de26aa34..fb9df48d20 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -61,6 +61,7 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
         log_error("Invalid device %s\n", device.c_str());
     }
     ArchArgs chipArgs;
+    chipArgs.gui = vm.count("gui") != 0;
     char buf[36];
     // GW1N and GW1NR variants share the same database.
     // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index 749c25a61d..bd2578de66 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -317,6 +317,12 @@ void DesignWidget::newContext(Context *ctx)
             for (const auto &wire : ctx->getWires()) {
                 wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
             }
+#endif
+#ifdef ARCH_GOWIN
+            for (const auto &wire : ctx->getWires()) {
+                WireInfo wi = ctx->wire_info(wire);
+                wireMap[std::pair<int, int>(wi.x, wi.y)].push_back(wire);
+            }
 #endif
             auto wireGetter = [](Context *ctx, WireId id) { return ctx->getWireName(id); };
             getTreeByElementType(ElementType::WIRE)
diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index b99c2bfc49..692eb27beb 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -129,40 +129,47 @@ float FPGAViewWidget::PickedElement::distance(Context *ctx, float wx, float wy)
 
     // Go over its' GraphicElements, and calculate the distance to them.
     std::vector<float> distances;
-    std::transform(graphics.begin(), graphics.end(), std::back_inserter(distances),
-                   [&](const GraphicElement &ge) -> float {
-                       switch (ge.type) {
-                       case GraphicElement::TYPE_BOX: {
-                           // If outside the box, return unit distance to closest border.
-                           float outside_x = -1, outside_y = -1;
-                           if (dx < ge.x1 || dx > ge.x2) {
-                               outside_x = std::min(std::abs(dx - ge.x1), std::abs(dx - ge.x2));
-                           }
-                           if (dy < ge.y1 || dy > ge.y2) {
-                               outside_y = std::min(std::abs(dy - ge.y1), std::abs(dy - ge.y2));
-                           }
-                           if (outside_x != -1 && outside_y != -1)
-                               return std::min(outside_x, outside_y);
-
-                           // If in box, return 0.
-                           return 0;
-                       }
-                       case GraphicElement::TYPE_LINE:
-                       case GraphicElement::TYPE_ARROW: {
-                           // Return somewhat primitively calculated distance to segment.
-                           // TODO(q3k): consider coming up with a better algorithm
-                           QVector2D w(wx, wy);
-                           QVector2D a(ge.x1, ge.y1);
-                           QVector2D b(ge.x2, ge.y2);
-                           float dw = a.distanceToPoint(w) + b.distanceToPoint(w);
-                           float dab = a.distanceToPoint(b);
-                           return std::abs(dw - dab) / dab;
-                       }
-                       default:
-                           // Not close to anything.
-                           return -1;
-                       }
-                   });
+    std::transform(
+            graphics.begin(), graphics.end(), std::back_inserter(distances), [&](const GraphicElement &ge) -> float {
+                switch (ge.type) {
+                case GraphicElement::TYPE_BOX: {
+                    // If outside the box, return unit distance to closest border.
+                    float outside_x = -1, outside_y = -1;
+                    if (dx < ge.x1 || dx > ge.x2) {
+                        outside_x = std::min(std::abs(dx - ge.x1), std::abs(dx - ge.x2));
+                    }
+                    if (dy < ge.y1 || dy > ge.y2) {
+                        outside_y = std::min(std::abs(dy - ge.y1), std::abs(dy - ge.y2));
+                    }
+                    if (outside_x != -1 && outside_y != -1)
+                        return std::min(outside_x, outside_y);
+
+                    // If in box, return 0.
+                    return 0;
+                }
+                case GraphicElement::TYPE_LOCAL_LINE:
+                case GraphicElement::TYPE_LOCAL_ARROW:
+                case GraphicElement::TYPE_LINE:
+                case GraphicElement::TYPE_ARROW: {
+                    // Return somewhat primitively calculated distance to segment.
+                    // TODO(q3k): consider coming up with a better algorithm
+                    QVector2D w;
+                    if (ge.type == GraphicElement::TYPE_LOCAL_LINE || ge.type == GraphicElement::TYPE_LOCAL_ARROW) {
+                        w = QVector2D(dx, dy);
+                    } else {
+                        w = QVector2D(wx, wy);
+                    }
+                    QVector2D a(ge.x1, ge.y1);
+                    QVector2D b(ge.x2, ge.y2);
+                    float dw = a.distanceToPoint(w) + b.distanceToPoint(w);
+                    float dab = a.distanceToPoint(b);
+                    return std::abs(dw - dab) / dab;
+                }
+                default:
+                    // Not close to anything.
+                    return -1;
+                }
+            });
 
     // Find smallest non -1 distance.
     // Find closest element.
@@ -193,7 +200,8 @@ void FPGAViewWidget::renderGraphicElement(LineShaderData &out, PickQuadTree::Bou
         return;
     }
 
-    if (el.type == GraphicElement::TYPE_LINE || el.type == GraphicElement::TYPE_ARROW) {
+    if (el.type == GraphicElement::TYPE_LINE || el.type == GraphicElement::TYPE_ARROW ||
+        el.type == GraphicElement::TYPE_LOCAL_LINE || el.type == GraphicElement::TYPE_LOCAL_ARROW) {
         PolyLine(x + el.x1, y + el.y1, x + el.x2, y + el.y2).build(out);
         bb.setX0(std::min(bb.x0(), x + el.x1));
         bb.setY0(std::min(bb.y0(), y + el.y1));
@@ -251,7 +259,8 @@ void FPGAViewWidget::populateQuadTree(RendererData *data, const DecalXY &decal,
             res = data->qt->insert(PickQuadTree::BoundingBox(x + el.x1, y + el.y1, x + el.x2, y + el.y2), element);
         }
 
-        if (el.type == GraphicElement::TYPE_LINE || el.type == GraphicElement::TYPE_ARROW) {
+        if (el.type == GraphicElement::TYPE_LINE || el.type == GraphicElement::TYPE_ARROW ||
+            el.type == GraphicElement::TYPE_LOCAL_LINE || el.type == GraphicElement::TYPE_LOCAL_ARROW) {
             // Lines are bounded by their AABB slightly enlarged.
             float x0 = x + el.x1;
             float y0 = y + el.y1;
@@ -540,7 +549,7 @@ void FPGAViewWidget::renderLines(void)
             QMutexLocker lock(&rendererDataLock_);
 
             // If we're not re-rendering any highlights/selections, let's
-            // copy them over from teh current object.
+            // copy them over from the current object.
             data->gfxGrid = rendererData_->gfxGrid;
             if (!highlightedOrSelectedChanged) {
                 data->gfxSelected = rendererData_->gfxSelected;
diff --git a/gui/gowin/mainwindow.cc b/gui/gowin/mainwindow.cc
index 9dafcef5fa..c7ba44ab60 100644
--- a/gui/gowin/mainwindow.cc
+++ b/gui/gowin/mainwindow.cc
@@ -19,9 +19,12 @@
 
 #include "mainwindow.h"
 
+#include <QFileDialog>
 #include <QMessageBox>
 #include <cstdlib>
 
+#include "cst.h"
+
 static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -30,8 +33,10 @@ MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler
         : BaseMainWindow(std::move(context), handler, parent)
 {
     initMainResource();
-    QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-gowin");
-    std::exit(1);
+    std::string title = "nextpnr-gowin - [EMPTY]";
+    setWindowTitle(title.c_str());
+    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
+    createMenu();
 }
 
 MainWindow::~MainWindow() {}
@@ -42,8 +47,57 @@ void MainWindow::newContext(Context *ctx)
     setWindowTitle(title.c_str());
 }
 
-void MainWindow::createMenu() {}
+void MainWindow::load_cst(std::string filename)
+{
+    disableActions();
+    std::ifstream f(filename);
+    if (read_cst(ctx.get(), f)) {
+        log("Loading CST successful.\n");
+        actionPack->setEnabled(true);
+    } else {
+        actionLoadCST->setEnabled(true);
+        log("Loading CST failed.\n");
+    }
+}
+
+void MainWindow::createMenu()
+{
+    actionLoadCST = new QAction("Open CST", this);
+    actionLoadCST->setIcon(QIcon(":/icons/resources/open_cst.png"));
+    actionLoadCST->setStatusTip("Open CST file");
+    actionLoadCST->setEnabled(false);
+    connect(actionLoadCST, &QAction::triggered, this, &MainWindow::open_cst);
+
+    // Add actions in menus
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionLoadCST);
+
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionLoadCST);
+}
 
 void MainWindow::new_proj() {}
 
+void MainWindow::open_cst()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open CST"), QString(), QString("*.cst"));
+    if (!fileName.isEmpty()) {
+        load_cst(fileName.toStdString());
+    }
+}
+
+void MainWindow::onDisableActions() { actionLoadCST->setEnabled(false); }
+
+void MainWindow::onUpdateActions()
+{
+    if (ctx->settings.find(ctx->id("synth")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(true);
+    }
+    if (ctx->settings.find(ctx->id("cst")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(false);
+    }
+    if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(false);
+    }
+}
 NEXTPNR_NAMESPACE_END
diff --git a/gui/gowin/mainwindow.h b/gui/gowin/mainwindow.h
index 1e39b63f63..0d65ed1c01 100644
--- a/gui/gowin/mainwindow.h
+++ b/gui/gowin/mainwindow.h
@@ -35,9 +35,21 @@ class MainWindow : public BaseMainWindow
   public:
     void createMenu();
 
+  protected:
+    void onDisableActions() override;
+    void onUpdateActions() override;
+
+    void load_cst(std::string filename);
+
   protected Q_SLOTS:
     void new_proj() override;
+
+    void open_cst();
+
     void newContext(Context *ctx);
+
+  private:
+    QAction *actionLoadCST;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/gui/gowin/nextpnr.qrc b/gui/gowin/nextpnr.qrc
index 03585ec030..921cfdd194 100644
--- a/gui/gowin/nextpnr.qrc
+++ b/gui/gowin/nextpnr.qrc
@@ -1,2 +1,5 @@
 <RCC>
+    <qresource prefix="/icons">
+        <file>resources/open_cst.png</file>
+    </qresource>
 </RCC>
diff --git a/gui/gowin/resources/open_cst.png b/gui/gowin/resources/open_cst.png
new file mode 100644
index 0000000000000000000000000000000000000000..23fe9cf88c151c0f8a4492be8e2de554715b1eb9
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literal 0
HcmV?d00001


From 676e56e5d44e09f3ff816c5efbb85e2b2ac1086b Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Tue, 25 Jan 2022 17:46:54 +0100
Subject: [PATCH 048/712] nexus: add option to modify the mult factor of the
 estimate delay

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 nexus/arch.cc | 7 ++++++-
 nexus/arch.h  | 1 +
 nexus/main.cc | 4 ++++
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index a7751425e3..06a901cdf3 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -601,7 +601,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;
     int dist_x = std::abs(src_x - dst_x);
     int dist_y = std::abs(src_y - dst_y);
-    return 75 * dist_x + 75 * dist_y + 250;
+
+    return estimate_delay_mult * (dist_x + dist_y) + 250;
 }
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
@@ -655,6 +656,10 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
+    estimate_delay_mult = 75;
+    if (getCtx()->settings.count(getCtx()->id("estimate-delay-mult")))
+        estimate_delay_mult = getCtx()->setting<int>("estimate-delay-mult");
+
     std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
 
     if (placer == "heap") {
diff --git a/nexus/arch.h b/nexus/arch.h
index 0bd1b62cd7..ea4e9f5bbe 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1290,6 +1290,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
 
+    int32_t estimate_delay_mult;
     delay_t estimateDelay(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 20; }
diff --git a/nexus/main.cc b/nexus/main.cc
index 9fec8d5e80..b02dfa998c 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -54,6 +54,8 @@ po::options_description NexusCommandHandler::getArchOptions()
     specific.add_options()("no-pack-lutff", "disable packing (clustering) LUTs and FFs together");
     specific.add_options()("carry-lutff-ratio", po::value<float>(),
                            "ratio of FFs to be added to carry-chain LUT clusters");
+    specific.add_options()("estimate-delay-mult", po::value<int>(),
+                           "multiplier for the estimate delay");
 
     return specific;
 }
@@ -88,6 +90,8 @@ std::unique_ptr<Context> NexusCommandHandler::createContext(dict<std::string, Pr
         }
         ctx->settings[ctx->id("carry_lutff_ratio")] = ratio;
     }
+    if (vm.count("estimate-delay-mult"))
+        ctx->settings[ctx->id("estimate-delay-mult")] = vm["estimate-delay-mult"].as<int>();
     return ctx;
 }
 

From 3042f9e792985cd204e1239d727541e566ddfcef Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Wed, 2 Feb 2022 09:24:28 +0100
Subject: [PATCH 049/712] Fixed correction of Nexus OSCA frequency constraints

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/pack.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 41f9d80664..5e9da3042f 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1988,8 +1988,8 @@ struct NexusPacker
                 } else if (ci->type == id_OSC_CORE) {
                     int div = int_or_default(ci->params, ctx->id("HF_CLK_DIV"), 128);
                     const float tol = 1.15f; // OSCA has +/-15% frequency tolerance, assume the worst case.
-                    set_period(ci, id_HFCLKOUT, delay_t(tol * (1.0e6 / 450) * (div + 1)));
-                    set_period(ci, id_LFCLKOUT, delay_t(tol * (1.0e3 / 10)));
+                    set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
+                    set_period(ci, id_LFCLKOUT, delay_t((1.0e3 / 10) / tol));
                 } else if (ci->type == id_PLL_CORE) {
                     static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
                     static const std::array<IdString, 6> output{id_CLKOP,  id_CLKOS,  id_CLKOS2,

From 368299d1437e4476e1ee41450194869e1ac6cf6b Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 3 Feb 2022 06:24:40 +1000
Subject: [PATCH 050/712] gowin: Rearrange the GUI constants

All internal constants for describing the graphics have been moved
to the .cc file.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/gfx.cc | 4896 ++++++++++++++++++++++++++++++++++++++++++++++++++
 gowin/gfx.h  | 4896 --------------------------------------------------
 2 files changed, 4896 insertions(+), 4896 deletions(-)

diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index ad2c7eadef..a851f53a69 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -24,6 +24,4902 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+// LUTs
+const float lut_w = 0.6732 - 0.6386;
+const float lut_h = 0.9392 - 0.9074;
+const float lut_x = 0.6386;
+const float lut_y[] = {1. - 0.9392, 1. - 0.8870, 1. - 0.7864, 1. - 0.7321,
+                       1. - 0.6399, 1. - 0.5847, 1. - 0.5068, 1. - 0.4503};
+const float dff_w = 0.0580;
+const float dff_x = 0.6821;
+const float grp_lut_w = 0.1399;
+const float grp_lut_h = 0.0954;
+const float grp_lut_x = 0.6284;
+const float grp_lut_y[] = {1. - 0.9440, 1. - 0.7915, 1. - 0.6442, 1. - 0.5101};
+
+// mux
+const float mux_w = 0.8134 - 0.7899;
+const float mux_f = 0.9450 - 0.9358;
+const float mux_h = grp_lut_h;
+
+const float mux2lut5_x = 0.7900;
+const float mux2lut5_y[] = {grp_lut_y[0], grp_lut_y[1], grp_lut_y[2], grp_lut_y[3]};
+const float mux2lut6_x = 0.8378;
+const float mux2lut6_y[] = {1. - 0.9261, 1. - 0.6205};
+const float mux2lut7_x = 0.8859;
+const float mux2lut7_y = 1. - 0.7870;
+const float mux2lut8_x = 0.9337;
+const float mux2lut8_y = 1. - 0.8098;
+
+// pip
+enum CruSide
+{
+    Top,
+    Bottom,
+    Left,
+    Right,
+    Center
+};
+const float cru_x = 0.2568;
+const float cru_y = 1. - 0.9783;
+const float cru_w = 0.6010 - cru_x;
+const float cru_h = 1. - cru_y - 0.3742;
+
+const float lut_A_off = 1. - 0.9107 - lut_y[0];
+const float lut_D_off = lut_h - lut_A_off;
+const float lut_B_off = lut_A_off - (lut_h - lut_D_off) / 3.;
+const float lut_C_off = lut_D_off + (lut_h - lut_D_off) / 3.;
+
+const float right_wire_dist = (grp_lut_y[1] - grp_lut_y[0] - grp_lut_h) / 11.;
+const float left_wire_dist = cru_h / 100.;
+const float top_wire_dist = cru_w / 100.;
+const float clk_ce_set_vdist = (lut_y[1] - lut_y[0] - lut_h) / 4.;
+
+const float sn_dist = cru_x / 125.;
+const float ew_dist = (1. - cru_y - cru_h) / 130.;
+const float wrap_len = 0.02f;
+const float spine_pip_off = 0.11f;
+
+const float io_x = cru_x + cru_w + 0.1;
+const float io_w = (1. - io_x) / 3.;
+const float io_gap = 0.03;
+const float io_h = (cru_h - 4. * io_gap) / 2.;
+const float io_y = cru_y + io_gap;
+
+const float ios_scl = 0.5;
+const float ios_h = ios_scl * io_h;
+const float ios_w = ios_scl * io_w;
+const float ios_gap_y = io_gap;
+const float ios_gap_x = io_gap * 1.4;
+const float ios_x = io_x;
+const float ios_y = ios_scl * io_y;
+
+const dict<IdString, float> portPoint = {
+        {id_O, 3. * io_h / 4.},
+        {id_I, 2. * io_h / 4.},
+        {id_OEN, 1. * io_h / 4.},
+};
+
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> portSign = {
+        {id_O,
+         {{io_h / 14. * 1.33, portPoint.at(id_O) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14., io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 2.,
+           portPoint.at(id_O) - io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14.},
+          {io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.,
+           portPoint.at(id_O) + io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 1.33,
+           portPoint.at(id_O) + io_h / 14.}}},
+        {id_I,
+         {{io_h / 14., portPoint.at(id_I) + io_h / 14., 2. * io_h / 14., portPoint.at(id_I) + io_h / 14.},
+          {io_h / 14. * 1.5, portPoint.at(id_I) + io_h / 14., 1. * io_h / 14. * 1.5, portPoint.at(id_I) - io_h / 14.},
+          {io_h / 14., portPoint.at(id_I) - io_h / 14., 2. * io_h / 14., portPoint.at(id_I) - io_h / 14.}}},
+        {id_OEN,
+         {{io_h / 14. * 1.33, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.,
+           portPoint.at(id_OEN) + io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 2.,
+           portPoint.at(id_OEN) - io_h / 14. * 0.6},
+          {io_h / 14. * 2., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.66,
+           portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 1.66, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.,
+           portPoint.at(id_OEN) - io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.,
+           portPoint.at(id_OEN) + io_h / 14. * 0.6},
+          {io_h / 14. * 1., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 1.33,
+           portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) + io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + 0., io_h / 14. * 3.2, portPoint.at(id_OEN) + 0.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) - io_h / 14.},
+          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14.}}},
+};
+
+const dict<IdString, float> spineY = {
+        {id_SPINE0, 1. - 1. * ew_dist},  {id_SPINE1, 1. - 2. * ew_dist},  {id_SPINE2, 1. - 3. * ew_dist},
+        {id_SPINE3, 1. - 4. * ew_dist},  {id_SPINE4, 1. - 5. * ew_dist},  {id_SPINE5, 1. - 6. * ew_dist},
+        {id_SPINE6, 1. - 7. * ew_dist},  {id_SPINE7, 1. - 8. * ew_dist},  {id_SPINE8, 1. - 1. * ew_dist},
+        {id_SPINE9, 1. - 2. * ew_dist},  {id_SPINE10, 1. - 3. * ew_dist}, {id_SPINE11, 1. - 4. * ew_dist},
+        {id_SPINE12, 1. - 5. * ew_dist}, {id_SPINE13, 1. - 6. * ew_dist}, {id_SPINE14, 1. - 7. * ew_dist},
+        {id_SPINE15, 1. - 8. * ew_dist}, {id_SPINE16, 1. - 1. * ew_dist}, {id_SPINE17, 1. - 2. * ew_dist},
+        {id_SPINE18, 1. - 3. * ew_dist}, {id_SPINE19, 1. - 4. * ew_dist}, {id_SPINE20, 1. - 5. * ew_dist},
+        {id_SPINE21, 1. - 6. * ew_dist}, {id_SPINE22, 1. - 7. * ew_dist}, {id_SPINE23, 1. - 8. * ew_dist},
+        {id_SPINE24, 1. - 1. * ew_dist}, {id_SPINE25, 1. - 2. * ew_dist}, {id_SPINE26, 1. - 3. * ew_dist},
+        {id_SPINE27, 1. - 4. * ew_dist}, {id_SPINE28, 1. - 5. * ew_dist}, {id_SPINE29, 1. - 6. * ew_dist},
+        {id_SPINE30, 1. - 7. * ew_dist}, {id_SPINE31, 1. - 8. * ew_dist},
+};
+
+const dict<IdString, std::pair<CruSide, float>> pipPoint = {
+        {id_X01, {Center, cru_y + 1. * cru_h / 9.}},
+        {id_X02, {Center, cru_y + 2. * cru_h / 9.}},
+        {id_X03, {Center, cru_y + 3. * cru_h / 9.}},
+        {id_X04, {Center, cru_y + 4. * cru_h / 9.}},
+        {id_X05, {Center, cru_y + 5. * cru_h / 9.}},
+        {id_X06, {Center, cru_y + 6. * cru_h / 9.}},
+        {id_X07, {Center, cru_y + 7. * cru_h / 9.}},
+        {id_X08, {Center, cru_y + 8. * cru_h / 9.}},
+        // LUT inputs
+        {id_A0, {Right, lut_y[0] + lut_A_off}},
+        {id_B0, {Right, lut_y[0] + lut_B_off}},
+        {id_C0, {Right, lut_y[0] + lut_C_off}},
+        {id_D0, {Right, lut_y[0] + lut_D_off}},
+        {id_A1, {Right, lut_y[1] + lut_A_off}},
+        {id_B1, {Right, lut_y[1] + lut_B_off}},
+        {id_C1, {Right, lut_y[1] + lut_C_off}},
+        {id_D1, {Right, lut_y[1] + lut_D_off}},
+        {id_A2, {Right, lut_y[2] + lut_A_off}},
+        {id_B2, {Right, lut_y[2] + lut_B_off}},
+        {id_C2, {Right, lut_y[2] + lut_C_off}},
+        {id_D2, {Right, lut_y[2] + lut_D_off}},
+        {id_A3, {Right, lut_y[3] + lut_A_off}},
+        {id_B3, {Right, lut_y[3] + lut_B_off}},
+        {id_C3, {Right, lut_y[3] + lut_C_off}},
+        {id_D3, {Right, lut_y[3] + lut_D_off}},
+        {id_A4, {Right, lut_y[4] + lut_A_off}},
+        {id_B4, {Right, lut_y[4] + lut_B_off}},
+        {id_C4, {Right, lut_y[4] + lut_C_off}},
+        {id_D4, {Right, lut_y[4] + lut_D_off}},
+        {id_A5, {Right, lut_y[5] + lut_A_off}},
+        {id_B5, {Right, lut_y[5] + lut_B_off}},
+        {id_C5, {Right, lut_y[5] + lut_C_off}},
+        {id_D5, {Right, lut_y[5] + lut_D_off}},
+        {id_A6, {Right, lut_y[6] + lut_A_off}},
+        {id_B6, {Right, lut_y[6] + lut_B_off}},
+        {id_C6, {Right, lut_y[6] + lut_C_off}},
+        {id_D6, {Right, lut_y[6] + lut_D_off}},
+        {id_A7, {Right, lut_y[7] + lut_A_off}},
+        {id_B7, {Right, lut_y[7] + lut_B_off}},
+        {id_C7, {Right, lut_y[7] + lut_C_off}},
+        {id_D7, {Right, lut_y[7] + lut_D_off}},
+        // wires below LUT0
+        {id_Q0, {Right, grp_lut_y[0] - right_wire_dist}},
+        {id_F0, {Right, grp_lut_y[0] - 2. * right_wire_dist}},
+        {id_OF3, {Right, grp_lut_y[0] - 3. * right_wire_dist}},
+        // wires between LUT1 and LUT2
+        {id_Q2, {Right, grp_lut_y[1] - right_wire_dist}},
+        {id_F2, {Right, grp_lut_y[1] - 2. * right_wire_dist}},
+        {id_OF2, {Right, grp_lut_y[1] - 3. * right_wire_dist}},
+        {id_OF1, {Right, grp_lut_y[1] - 4. * right_wire_dist}},
+        {id_OF0, {Right, grp_lut_y[1] - 5. * right_wire_dist}},
+        {id_SEL1, {Right, grp_lut_y[1] - 6. * right_wire_dist}},
+        {id_OF7, {Right, grp_lut_y[1] - 7. * right_wire_dist}},
+        {id_SEL0, {Right, grp_lut_y[1] - 8. * right_wire_dist}},
+        {id_F1, {Right, grp_lut_y[1] - 9. * right_wire_dist}},
+        {id_Q1, {Right, grp_lut_y[1] - 10. * right_wire_dist}},
+        // wires between LUT3 and LUT4
+        {id_Q4, {Right, grp_lut_y[2] - right_wire_dist}},
+        {id_F4, {Right, grp_lut_y[2] - 2. * right_wire_dist}},
+        {id_OF4, {Right, grp_lut_y[2] - 3. * right_wire_dist}},
+        {id_OF5, {Right, grp_lut_y[2] - 4. * right_wire_dist}},
+        {id_SEL7, {Right, grp_lut_y[2] - 5. * right_wire_dist}},
+        {id_SEL3, {Right, grp_lut_y[2] - 6. * right_wire_dist}},
+        {id_SEL2, {Right, grp_lut_y[2] - 7. * right_wire_dist}},
+        {id_F3, {Right, grp_lut_y[2] - 8. * right_wire_dist}},
+        {id_Q3, {Right, grp_lut_y[2] - 9. * right_wire_dist}},
+        // wires between LUT5 and LUT6
+        {id_F6, {Right, grp_lut_y[3] - right_wire_dist}},
+        {id_SEL5, {Right, grp_lut_y[3] - 2. * right_wire_dist}},
+        {id_SEL4, {Right, grp_lut_y[3] - 4. * right_wire_dist}},
+        {id_F5, {Right, grp_lut_y[3] - 5. * right_wire_dist}},
+        {id_Q5, {Right, grp_lut_y[3] - 6. * right_wire_dist}},
+        // Q6, Q7 --- IOB
+        {id_Q6, {Right, grp_lut_y[3] + grp_lut_h * 0.33}},
+        {id_Q7, {Right, grp_lut_y[3] + grp_lut_h * 0.66}},
+        // wires above LUT7
+        {id_F7, {Right, grp_lut_y[3] + grp_lut_h + right_wire_dist}},
+        {id_SEL6, {Right, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist}},
+        {id_OF6, {Right, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist}},
+        // DI0-5
+        {id_DI5, {Right, cru_y + cru_h - 0.5 * right_wire_dist}},
+        {id_DI4, {Right, cru_y + cru_h - 1. * right_wire_dist}},
+        {id_DI3, {Right, cru_y + cru_h - 1.5 * right_wire_dist}},
+        {id_DI2, {Right, cru_y + cru_h - 2. * right_wire_dist}},
+        {id_DI1, {Right, cru_y + cru_h - 2.5 * right_wire_dist}},
+        {id_DI0, {Right, cru_y + cru_h - 3. * right_wire_dist}},
+        // Q6
+        // CLK, CE, SET-RESET
+        {id_CLK0, {Right, lut_y[1] - clk_ce_set_vdist}},
+        {id_CE0, {Right, lut_y[1] - 2. * clk_ce_set_vdist}},
+        {id_LSR0, {Right, lut_y[1] - 3. * clk_ce_set_vdist}},
+        {id_CLK1, {Right, lut_y[3] - clk_ce_set_vdist}},
+        {id_CE1, {Right, lut_y[3] - 2. * clk_ce_set_vdist}},
+        {id_LSR1, {Right, lut_y[3] - 3. * clk_ce_set_vdist}},
+        {id_CLK2, {Right, lut_y[5] - clk_ce_set_vdist}},
+        {id_CE2, {Right, lut_y[5] - 2. * clk_ce_set_vdist}},
+        {id_LSR2, {Right, lut_y[5] - 3. * clk_ce_set_vdist}},
+        // SN
+        // 1 hop
+        {id_S100, {Left, cru_y + 1. * left_wire_dist}},
+        {id_S101, {Left, cru_y + 2. * left_wire_dist}},
+        {id_S130, {Left, cru_y + 3. * left_wire_dist}},
+        {id_S131, {Left, cru_y + 4. * left_wire_dist}},
+        {id_N101, {Left, cru_y + 5. * left_wire_dist}},
+        {id_N100, {Left, cru_y + 6. * left_wire_dist}},
+        {id_N131, {Left, cru_y + 7. * left_wire_dist}},
+        {id_N130, {Left, cru_y + 8. * left_wire_dist}},
+        // 1 hop SN
+        {id_N111, {Left, cru_y + 9. * left_wire_dist}},
+        {id_SN10, {Left, cru_y + 10. * left_wire_dist}},
+        {id_S111, {Left, cru_y + 11. * left_wire_dist}},
+        {id_N121, {Left, cru_y + 12. * left_wire_dist}},
+        {id_SN20, {Left, cru_y + 13. * left_wire_dist}},
+        {id_S121, {Left, cru_y + 14. * left_wire_dist}},
+        // 2 hop
+        {id_S200, {Left, cru_y + 15. * left_wire_dist}},
+        {id_S201, {Left, cru_y + 16. * left_wire_dist}},
+        {id_N202, {Left, cru_y + 17. * left_wire_dist}},
+        {id_S202, {Left, cru_y + 18. * left_wire_dist}},
+        {id_N201, {Left, cru_y + 19. * left_wire_dist}},
+        {id_N200, {Left, cru_y + 20. * left_wire_dist}},
+
+        {id_S210, {Left, cru_y + 21. * left_wire_dist}},
+        {id_S211, {Left, cru_y + 22. * left_wire_dist}},
+        {id_N212, {Left, cru_y + 23. * left_wire_dist}},
+        {id_S212, {Left, cru_y + 24. * left_wire_dist}},
+        {id_N211, {Left, cru_y + 25. * left_wire_dist}},
+        {id_N210, {Left, cru_y + 26. * left_wire_dist}},
+
+        {id_S220, {Left, cru_y + 27. * left_wire_dist}},
+        {id_S221, {Left, cru_y + 28. * left_wire_dist}},
+        {id_N222, {Left, cru_y + 29. * left_wire_dist}},
+        {id_S222, {Left, cru_y + 30. * left_wire_dist}},
+        {id_N221, {Left, cru_y + 31. * left_wire_dist}},
+        {id_N220, {Left, cru_y + 32. * left_wire_dist}},
+
+        {id_S230, {Left, cru_y + 33. * left_wire_dist}},
+        {id_S231, {Left, cru_y + 34. * left_wire_dist}},
+        {id_N232, {Left, cru_y + 35. * left_wire_dist}},
+        {id_S232, {Left, cru_y + 36. * left_wire_dist}},
+        {id_N231, {Left, cru_y + 37. * left_wire_dist}},
+        {id_N230, {Left, cru_y + 38. * left_wire_dist}},
+
+        {id_S240, {Left, cru_y + 39. * left_wire_dist}},
+        {id_S241, {Left, cru_y + 40. * left_wire_dist}},
+        {id_N242, {Left, cru_y + 41. * left_wire_dist}},
+        {id_S242, {Left, cru_y + 42. * left_wire_dist}},
+        {id_N241, {Left, cru_y + 43. * left_wire_dist}},
+        {id_N240, {Left, cru_y + 44. * left_wire_dist}},
+
+        {id_S250, {Left, cru_y + 45. * left_wire_dist}},
+        {id_S251, {Left, cru_y + 46. * left_wire_dist}},
+        {id_N252, {Left, cru_y + 47. * left_wire_dist}},
+        {id_S252, {Left, cru_y + 48. * left_wire_dist}},
+        {id_N251, {Left, cru_y + 49. * left_wire_dist}},
+        {id_N250, {Left, cru_y + 50. * left_wire_dist}},
+
+        {id_S260, {Left, cru_y + 51. * left_wire_dist}},
+        {id_S261, {Left, cru_y + 52. * left_wire_dist}},
+        {id_N262, {Left, cru_y + 53. * left_wire_dist}},
+        {id_S262, {Left, cru_y + 54. * left_wire_dist}},
+        {id_N261, {Left, cru_y + 55. * left_wire_dist}},
+        {id_N260, {Left, cru_y + 56. * left_wire_dist}},
+
+        {id_S270, {Left, cru_y + 57. * left_wire_dist}},
+        {id_S271, {Left, cru_y + 58. * left_wire_dist}},
+        {id_N272, {Left, cru_y + 59. * left_wire_dist}},
+        {id_S272, {Left, cru_y + 60. * left_wire_dist}},
+        {id_N271, {Left, cru_y + 61. * left_wire_dist}},
+        {id_N270, {Left, cru_y + 62. * left_wire_dist}},
+
+        // Clocks
+        {id_GT10, {Left, cru_y + 63. * left_wire_dist}},
+        {id_GT00, {Left, cru_y + 68. * left_wire_dist}},
+
+        // 4 hop
+        {id_N808, {Left, cru_y + 73. * left_wire_dist}},
+        {id_S800, {Left, cru_y + 74. * left_wire_dist}},
+        {id_S804, {Left, cru_y + 75. * left_wire_dist}},
+        {id_N804, {Left, cru_y + 76. * left_wire_dist}},
+        {id_N800, {Left, cru_y + 77. * left_wire_dist}},
+        {id_S808, {Left, cru_y + 78. * left_wire_dist}},
+
+        {id_N818, {Left, cru_y + 79. * left_wire_dist}},
+        {id_S810, {Left, cru_y + 80. * left_wire_dist}},
+        {id_S814, {Left, cru_y + 81. * left_wire_dist}},
+        {id_N814, {Left, cru_y + 82. * left_wire_dist}},
+        {id_N810, {Left, cru_y + 83. * left_wire_dist}},
+        {id_S818, {Left, cru_y + 84. * left_wire_dist}},
+
+        {id_N828, {Left, cru_y + 85. * left_wire_dist}},
+        {id_S820, {Left, cru_y + 86. * left_wire_dist}},
+        {id_S824, {Left, cru_y + 87. * left_wire_dist}},
+        {id_N824, {Left, cru_y + 88. * left_wire_dist}},
+        {id_N820, {Left, cru_y + 89. * left_wire_dist}},
+        {id_S828, {Left, cru_y + 90. * left_wire_dist}},
+
+        {id_N838, {Left, cru_y + 91. * left_wire_dist}},
+        {id_S830, {Left, cru_y + 92. * left_wire_dist}},
+        {id_S834, {Left, cru_y + 93. * left_wire_dist}},
+        {id_N834, {Left, cru_y + 94. * left_wire_dist}},
+        {id_N830, {Left, cru_y + 95. * left_wire_dist}},
+        {id_S838, {Left, cru_y + 96. * left_wire_dist}},
+
+        // EW
+        // 1 hop
+        {id_E101, {Top, cru_x + 1. * top_wire_dist}},
+        {id_E100, {Top, cru_x + 2. * top_wire_dist}},
+        {id_E131, {Top, cru_x + 3. * top_wire_dist}},
+        {id_E130, {Top, cru_x + 4. * top_wire_dist}},
+        {id_W100, {Top, cru_x + 5. * top_wire_dist}},
+        {id_W101, {Top, cru_x + 6. * top_wire_dist}},
+        {id_W130, {Top, cru_x + 7. * top_wire_dist}},
+        {id_W131, {Top, cru_x + 8. * top_wire_dist}},
+        // 1 hop EW
+        {id_E111, {Top, cru_x + 9. * top_wire_dist}},
+        {id_EW10, {Top, cru_x + 10. * top_wire_dist}},
+        {id_W111, {Top, cru_x + 11. * top_wire_dist}},
+        {id_E121, {Top, cru_x + 12. * top_wire_dist}},
+        {id_EW20, {Top, cru_x + 13. * top_wire_dist}},
+        {id_W121, {Top, cru_x + 14. * top_wire_dist}},
+        // 2 hop
+        {id_E202, {Top, cru_x + 15. * top_wire_dist}},
+        {id_E201, {Top, cru_x + 16. * top_wire_dist}},
+        {id_W200, {Top, cru_x + 17. * top_wire_dist}},
+        {id_E200, {Top, cru_x + 18. * top_wire_dist}},
+        {id_W201, {Top, cru_x + 19. * top_wire_dist}},
+        {id_W202, {Top, cru_x + 20. * top_wire_dist}},
+
+        {id_E212, {Top, cru_x + 21. * top_wire_dist}},
+        {id_E211, {Top, cru_x + 22. * top_wire_dist}},
+        {id_W210, {Top, cru_x + 23. * top_wire_dist}},
+        {id_E210, {Top, cru_x + 24. * top_wire_dist}},
+        {id_W211, {Top, cru_x + 25. * top_wire_dist}},
+        {id_W212, {Top, cru_x + 26. * top_wire_dist}},
+
+        {id_E222, {Top, cru_x + 27. * top_wire_dist}},
+        {id_E221, {Top, cru_x + 28. * top_wire_dist}},
+        {id_W220, {Top, cru_x + 29. * top_wire_dist}},
+        {id_E220, {Top, cru_x + 30. * top_wire_dist}},
+        {id_W221, {Top, cru_x + 31. * top_wire_dist}},
+        {id_W222, {Top, cru_x + 32. * top_wire_dist}},
+
+        {id_E232, {Top, cru_x + 33. * top_wire_dist}},
+        {id_E231, {Top, cru_x + 34. * top_wire_dist}},
+        {id_W230, {Top, cru_x + 35. * top_wire_dist}},
+        {id_E230, {Top, cru_x + 36. * top_wire_dist}},
+        {id_W231, {Top, cru_x + 37. * top_wire_dist}},
+        {id_W232, {Top, cru_x + 38. * top_wire_dist}},
+
+        {id_E242, {Top, cru_x + 39. * top_wire_dist}},
+        {id_E241, {Top, cru_x + 40. * top_wire_dist}},
+        {id_W240, {Top, cru_x + 41. * top_wire_dist}},
+        {id_E240, {Top, cru_x + 42. * top_wire_dist}},
+        {id_W241, {Top, cru_x + 43. * top_wire_dist}},
+        {id_W242, {Top, cru_x + 44. * top_wire_dist}},
+
+        {id_E252, {Top, cru_x + 45. * top_wire_dist}},
+        {id_E251, {Top, cru_x + 46. * top_wire_dist}},
+        {id_W250, {Top, cru_x + 47. * top_wire_dist}},
+        {id_E250, {Top, cru_x + 48. * top_wire_dist}},
+        {id_W251, {Top, cru_x + 49. * top_wire_dist}},
+        {id_W252, {Top, cru_x + 50. * top_wire_dist}},
+
+        {id_E262, {Top, cru_x + 51. * top_wire_dist}},
+        {id_E261, {Top, cru_x + 52. * top_wire_dist}},
+        {id_W260, {Top, cru_x + 53. * top_wire_dist}},
+        {id_E260, {Top, cru_x + 54. * top_wire_dist}},
+        {id_W261, {Top, cru_x + 55. * top_wire_dist}},
+        {id_W262, {Top, cru_x + 56. * top_wire_dist}},
+
+        {id_E272, {Top, cru_x + 57. * top_wire_dist}},
+        {id_E271, {Top, cru_x + 58. * top_wire_dist}},
+        {id_W270, {Top, cru_x + 59. * top_wire_dist}},
+        {id_E270, {Top, cru_x + 60. * top_wire_dist}},
+        {id_W271, {Top, cru_x + 61. * top_wire_dist}},
+        {id_W272, {Top, cru_x + 62. * top_wire_dist}},
+
+        // Global taps -> bracnhes
+        {id_GBO0, {Top, cru_x + 63. * top_wire_dist}},
+        {id_GB00, {Top, cru_x + 64. * top_wire_dist}},
+        {id_GB10, {Top, cru_x + 65. * top_wire_dist}},
+        {id_GB20, {Top, cru_x + 66. * top_wire_dist}},
+        {id_GB30, {Top, cru_x + 67. * top_wire_dist}},
+        {id_GBO1, {Top, cru_x + 68. * top_wire_dist}},
+        {id_GB40, {Top, cru_x + 68. * top_wire_dist}},
+        {id_GB50, {Top, cru_x + 69. * top_wire_dist}},
+        {id_GB60, {Top, cru_x + 70. * top_wire_dist}},
+        {id_GB70, {Top, cru_x + 71. * top_wire_dist}},
+
+        // 4 hop
+        {id_E808, {Top, cru_x + 72. * top_wire_dist}},
+        {id_W800, {Top, cru_x + 73. * top_wire_dist}},
+        {id_W804, {Top, cru_x + 74. * top_wire_dist}},
+        {id_E804, {Top, cru_x + 75. * top_wire_dist}},
+        {id_E800, {Top, cru_x + 76. * top_wire_dist}},
+        {id_W808, {Top, cru_x + 77. * top_wire_dist}},
+
+        {id_E818, {Top, cru_x + 78. * top_wire_dist}},
+        {id_W810, {Top, cru_x + 79. * top_wire_dist}},
+        {id_W814, {Top, cru_x + 80. * top_wire_dist}},
+        {id_E814, {Top, cru_x + 81. * top_wire_dist}},
+        {id_E810, {Top, cru_x + 82. * top_wire_dist}},
+        {id_W818, {Top, cru_x + 83. * top_wire_dist}},
+
+        {id_E828, {Top, cru_x + 84. * top_wire_dist}},
+        {id_W820, {Top, cru_x + 85. * top_wire_dist}},
+        {id_W824, {Top, cru_x + 86. * top_wire_dist}},
+        {id_E824, {Top, cru_x + 87. * top_wire_dist}},
+        {id_E820, {Top, cru_x + 88. * top_wire_dist}},
+        {id_W828, {Top, cru_x + 89. * top_wire_dist}},
+
+        {id_E838, {Top, cru_x + 90. * top_wire_dist}},
+        {id_W830, {Top, cru_x + 91. * top_wire_dist}},
+        {id_W834, {Top, cru_x + 92. * top_wire_dist}},
+        {id_E834, {Top, cru_x + 93. * top_wire_dist}},
+        {id_E830, {Top, cru_x + 94. * top_wire_dist}},
+        {id_W838, {Top, cru_x + 95. * top_wire_dist}},
+
+};
+
+// wire
+const std::vector<IdString> decalless_wires = {id_X01, id_X02, id_X03, id_X04, id_X05, id_X06, id_X07};
+
+const float clk_ce_set_hdist = dff_w / 4.;
+const float dff_f_x = (grp_lut_x + grp_lut_w + dff_x + dff_w) / 2.;
+const float mux5i_x = (grp_lut_x + grp_lut_w + mux2lut5_x) / 2.;
+
+// id, {x1, y1, x2, y2}
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> sliceLocalWires = {
+        // dff
+        {id_CLK0,
+         {{cru_x + cru_w, pipPoint.at(id_CLK0).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK0).second},
+          {dff_x + clk_ce_set_hdist, lut_y[1], dff_x + clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_CE0,
+         {{cru_x + cru_w, pipPoint.at(id_CE0).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE0).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[1], dff_x + 2. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_LSR0,
+         {{cru_x + cru_w, pipPoint.at(id_LSR0).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR0).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[1], dff_x + 3. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
+        {id_CLK1,
+         {{cru_x + cru_w, pipPoint.at(id_CLK1).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK1).second},
+          {dff_x + clk_ce_set_hdist, lut_y[3], dff_x + clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_CE1,
+         {{cru_x + cru_w, pipPoint.at(id_CE1).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE1).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[3], dff_x + 2. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_LSR1,
+         {{cru_x + cru_w, pipPoint.at(id_LSR1).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR1).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[3], dff_x + 3. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
+        {id_CLK2,
+         {{cru_x + cru_w, pipPoint.at(id_CLK2).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK2).second},
+          {dff_x + clk_ce_set_hdist, lut_y[5], dff_x + clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        {id_CE2,
+         {{cru_x + cru_w, pipPoint.at(id_CE2).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE2).second},
+          {dff_x + 2 * clk_ce_set_hdist, lut_y[5], dff_x + 2. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        {id_LSR2,
+         {{cru_x + cru_w, pipPoint.at(id_LSR2).second, dff_x + 3 * clk_ce_set_hdist, pipPoint.at(id_LSR2).second},
+          {dff_x + 3 * clk_ce_set_hdist, lut_y[5], dff_x + 3. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
+        // lut
+        {id_A0, {{cru_x + cru_w, lut_y[0] + lut_A_off, lut_x, lut_y[0] + lut_A_off}}},
+        {id_B0, {{cru_x + cru_w, lut_y[0] + lut_B_off, lut_x, lut_y[0] + lut_B_off}}},
+        {id_C0, {{cru_x + cru_w, lut_y[0] + lut_C_off, lut_x, lut_y[0] + lut_C_off}}},
+        {id_D0, {{cru_x + cru_w, lut_y[0] + lut_D_off, lut_x, lut_y[0] + lut_D_off}}},
+        {id_A1, {{cru_x + cru_w, lut_y[1] + lut_A_off, lut_x, lut_y[1] + lut_A_off}}},
+        {id_B1, {{cru_x + cru_w, lut_y[1] + lut_B_off, lut_x, lut_y[1] + lut_B_off}}},
+        {id_C1, {{cru_x + cru_w, lut_y[1] + lut_C_off, lut_x, lut_y[1] + lut_C_off}}},
+        {id_D1, {{cru_x + cru_w, lut_y[1] + lut_D_off, lut_x, lut_y[1] + lut_D_off}}},
+        {id_A2, {{cru_x + cru_w, lut_y[2] + lut_A_off, lut_x, lut_y[2] + lut_A_off}}},
+        {id_B2, {{cru_x + cru_w, lut_y[2] + lut_B_off, lut_x, lut_y[2] + lut_B_off}}},
+        {id_C2, {{cru_x + cru_w, lut_y[2] + lut_C_off, lut_x, lut_y[2] + lut_C_off}}},
+        {id_D2, {{cru_x + cru_w, lut_y[2] + lut_D_off, lut_x, lut_y[2] + lut_D_off}}},
+        {id_A3, {{cru_x + cru_w, lut_y[3] + lut_A_off, lut_x, lut_y[3] + lut_A_off}}},
+        {id_B3, {{cru_x + cru_w, lut_y[3] + lut_B_off, lut_x, lut_y[3] + lut_B_off}}},
+        {id_C3, {{cru_x + cru_w, lut_y[3] + lut_C_off, lut_x, lut_y[3] + lut_C_off}}},
+        {id_D3, {{cru_x + cru_w, lut_y[3] + lut_D_off, lut_x, lut_y[3] + lut_D_off}}},
+        {id_A4, {{cru_x + cru_w, lut_y[4] + lut_A_off, lut_x, lut_y[4] + lut_A_off}}},
+        {id_B4, {{cru_x + cru_w, lut_y[4] + lut_B_off, lut_x, lut_y[4] + lut_B_off}}},
+        {id_C4, {{cru_x + cru_w, lut_y[4] + lut_C_off, lut_x, lut_y[4] + lut_C_off}}},
+        {id_D4, {{cru_x + cru_w, lut_y[4] + lut_D_off, lut_x, lut_y[4] + lut_D_off}}},
+        {id_A5, {{cru_x + cru_w, lut_y[5] + lut_A_off, lut_x, lut_y[5] + lut_A_off}}},
+        {id_B5, {{cru_x + cru_w, lut_y[5] + lut_B_off, lut_x, lut_y[5] + lut_B_off}}},
+        {id_C5, {{cru_x + cru_w, lut_y[5] + lut_C_off, lut_x, lut_y[5] + lut_C_off}}},
+        {id_D5, {{cru_x + cru_w, lut_y[5] + lut_D_off, lut_x, lut_y[5] + lut_D_off}}},
+        {id_A6, {{cru_x + cru_w, lut_y[6] + lut_A_off, lut_x, lut_y[6] + lut_A_off}}},
+        {id_B6, {{cru_x + cru_w, lut_y[6] + lut_B_off, lut_x, lut_y[6] + lut_B_off}}},
+        {id_C6, {{cru_x + cru_w, lut_y[6] + lut_C_off, lut_x, lut_y[6] + lut_C_off}}},
+        {id_D6, {{cru_x + cru_w, lut_y[6] + lut_D_off, lut_x, lut_y[6] + lut_D_off}}},
+        {id_A7, {{cru_x + cru_w, lut_y[7] + lut_A_off, lut_x, lut_y[7] + lut_A_off}}},
+        {id_B7, {{cru_x + cru_w, lut_y[7] + lut_B_off, lut_x, lut_y[7] + lut_B_off}}},
+        {id_C7, {{cru_x + cru_w, lut_y[7] + lut_C_off, lut_x, lut_y[7] + lut_C_off}}},
+        {id_D7, {{cru_x + cru_w, lut_y[7] + lut_D_off, lut_x, lut_y[7] + lut_D_off}}},
+        // wires below LUT0
+        {id_Q0,
+         {{cru_x + cru_w, grp_lut_y[0] - right_wire_dist, dff_f_x, grp_lut_y[0] - right_wire_dist},
+          {dff_f_x, grp_lut_y[0] - right_wire_dist, dff_f_x, lut_y[0] + lut_h / 2.},
+          {dff_f_x, lut_y[0] + lut_h / 2., dff_x + dff_w, lut_y[0] + lut_h / 2.}}},
+        {id_F0,
+         {{cru_x + cru_w, grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[0] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[0] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[0] + lut_h / 2., dff_x, lut_y[0] + lut_h / 2.}}},
+        {id_I0MUX0,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[0] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[0] - 2. * right_wire_dist, mux5i_x, lut_y[0] + lut_h / 2.},
+          {mux5i_x, lut_y[0] + lut_h / 2., mux2lut5_x, lut_y[0] + lut_h / 2.}}},
+        {id_OF3,
+         {{cru_x + cru_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
+           grp_lut_y[0] - 3. * right_wire_dist},
+          {mux2lut7_x + 4. / 3. * mux_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h / 2.},
+          {mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut7_x + mux_w, mux2lut7_y + mux_h / 2.}}},
+        {id_I1MUX7, {{mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut8_x, mux2lut7_y + mux_h / 2.}}},
+        // wires between LUT1 and LUT2
+        {id_Q1,
+         {{cru_x + cru_w, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, grp_lut_y[1] - 10. * right_wire_dist},
+          {dff_f_x, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, lut_y[1] + lut_h / 2.},
+          {dff_f_x, lut_y[1] + lut_h / 2., dff_x + dff_w, lut_y[1] + lut_h / 2.}}},
+        {id_F1,
+         {{cru_x + cru_w, grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[1] - 9. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[1] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[1] + lut_h / 2., dff_x, lut_y[1] + lut_h / 2.}}},
+        {id_I1MUX0,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, mux5i_x,
+           grp_lut_y[1] - 9. * right_wire_dist},
+          {mux5i_x, grp_lut_y[1] - 9. * right_wire_dist, mux5i_x, lut_y[1] + lut_h / 2.},
+          {mux5i_x, lut_y[1] + lut_h / 2., mux2lut5_x, lut_y[1] + lut_h / 2.}}},
+        {id_SEL0,
+         {{cru_x + cru_w, grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[1] - 8. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[0] + mux_h - mux_f / 2.}}},
+        {id_OF7,
+         {{cru_x + cru_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 7. * right_wire_dist},
+          {mux2lut8_x + 4. / 3. * mux_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
+           mux2lut8_y + mux_h / 2.},
+          {mux2lut8_x + 4. / 3. * mux_w, mux2lut8_y + mux_h / 2., mux2lut8_x + mux_w, mux2lut8_y + mux_h / 2.}}},
+        {id_SEL1,
+         {{cru_x + cru_w, grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           grp_lut_y[1] - 6. * right_wire_dist},
+          {mux2lut6_x + mux_w / 2., grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           mux2lut6_y[0] + mux_h - mux_f / 2.}}},
+        {id_OF0,
+         {{cru_x + cru_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 5. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[0] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[0] + mux_h / 2.}}},
+        {id_I1MUX1,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut6_x, mux2lut5_y[0] + mux_h / 2.}}},
+        {id_OF1,
+         {{cru_x + cru_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           grp_lut_y[1] - 4. * right_wire_dist},
+          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut6_y[0] + mux_h / 2.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[0] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[0] + mux_h / 2.}}},
+        {id_I1MUX3,
+         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h * 1. / 4.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 1. / 4., mux2lut7_x, mux2lut7_y + mux_h * 1. / 4.}}},
+        {id_OF2,
+         {{cru_x + cru_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           grp_lut_y[1] - 3. * right_wire_dist},
+          {mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           mux2lut5_y[1] + mux_h / 2.},
+          {mux2lut5_x + 5. / 3. * mux_w, mux2lut5_y[1] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[1] + mux_h / 2.}}},
+        {id_I0MUX1,
+         {{mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
+           mux2lut6_y[0] + mux_h * 3. / 4.},
+          {mux2lut5_x + 5. / 3. * mux_w, mux2lut6_y[0] + mux_h * 3. / 4., mux2lut6_x,
+           mux2lut6_y[0] + mux_h * 3. / 4.}}},
+        {id_F2,
+         {{cru_x + cru_w, grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[1] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[2] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[2] + lut_h / 2., dff_x, lut_y[2] + lut_h / 2.}}},
+        {id_I0MUX2,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[1] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[1] - 2. * right_wire_dist, mux5i_x, lut_y[2] + lut_h / 2.},
+          {mux5i_x, lut_y[2] + lut_h / 2., mux2lut5_x, lut_y[2] + lut_h / 2.}}},
+        {id_Q2,
+         {{cru_x + cru_w, grp_lut_y[1] - right_wire_dist, dff_f_x, grp_lut_y[1] - right_wire_dist},
+          {dff_f_x, grp_lut_y[1] - right_wire_dist, dff_f_x, lut_y[2] + lut_h / 2.},
+          {dff_f_x, lut_y[2] + lut_h / 2., dff_x + dff_w, lut_y[2] + lut_h / 2.}}},
+        // wires between LUT3 and LUT4
+        {id_Q3,
+         {{cru_x + cru_w, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, grp_lut_y[2] - 9. * right_wire_dist},
+          {dff_f_x, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, lut_y[3] + lut_h / 2.},
+          {dff_f_x, lut_y[3] + lut_h / 2., dff_x + dff_w, lut_y[3] + lut_h / 2.}}},
+        {id_F3,
+         {{cru_x + cru_w, grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[2] - 8. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[3] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[3] + lut_h / 2., dff_x, lut_y[3] + lut_h / 2.}}},
+        {id_I1MUX2,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, mux5i_x,
+           grp_lut_y[2] - 8. * right_wire_dist},
+          {mux5i_x, grp_lut_y[2] - 8. * right_wire_dist, mux5i_x, lut_y[3] + lut_h / 2.},
+          {mux5i_x, lut_y[3] + lut_h / 2., mux2lut5_x, lut_y[3] + lut_h / 2.}}},
+        {id_SEL2,
+         {{cru_x + cru_w, grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[2] - 7. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[1] + mux_h - mux_f / 2.}}},
+        {id_SEL3,
+         {{cru_x + cru_w, grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
+           grp_lut_y[2] - 6. * right_wire_dist},
+          {mux2lut7_x + mux_w / 2., grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
+           mux2lut7_y + mux_h - mux_f / 2.}}},
+        {id_SEL7,
+         {{cru_x + cru_w, grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
+           grp_lut_y[2] - 5. * right_wire_dist},
+          {mux2lut8_x + mux_w / 2., grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
+           mux2lut8_y + mux_h - mux_f / 2.}}},
+        {id_OF5,
+         {{cru_x + cru_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           grp_lut_y[2] - 4. * right_wire_dist},
+          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut6_y[1] + mux_h / 2.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[1] + mux_h / 2.}}},
+        {id_I0MUX3,
+         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
+           mux2lut7_y + mux_h * 3. / 4.},
+          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 3. / 4., mux2lut7_x, mux2lut7_y + mux_h * 3. / 4.}}},
+        {id_OF4,
+         {{cru_x + cru_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[2] - 3. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[2] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[2] + mux_h / 2.}}},
+        {id_I1MUX5,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut6_x, mux2lut5_y[2] + mux_h / 2.}}},
+        {id_F4,
+         {{cru_x + cru_w, grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[2] - 2. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[4] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[4] + lut_h / 2., dff_x, lut_y[4] + lut_h / 2.}}},
+        {id_I0MUX4,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, mux5i_x,
+           grp_lut_y[2] - 2. * right_wire_dist},
+          {mux5i_x, grp_lut_y[2] - 2. * right_wire_dist, mux5i_x, lut_y[4] + lut_h / 2.},
+          {mux5i_x, lut_y[4] + lut_h / 2., mux2lut5_x, lut_y[4] + lut_h / 2.}}},
+        {id_Q4,
+         {{cru_x + cru_w, grp_lut_y[2] - right_wire_dist, dff_f_x, grp_lut_y[2] - right_wire_dist},
+          {dff_f_x, grp_lut_y[2] - right_wire_dist, dff_f_x, lut_y[4] + lut_h / 2.},
+          {dff_f_x, lut_y[4] + lut_h / 2., dff_x + dff_w, lut_y[4] + lut_h / 2.}}},
+        // wires between LUT5 and LUT6
+        {id_Q5,
+         {{cru_x + cru_w, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, grp_lut_y[3] - 6. * right_wire_dist},
+          {dff_f_x, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, lut_y[5] + lut_h / 2.},
+          {dff_f_x, lut_y[5] + lut_h / 2., dff_x + dff_w, lut_y[5] + lut_h / 2.}}},
+        {id_F5,
+         {{cru_x + cru_w, grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[3] - 5. * right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[5] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[5] + lut_h / 2., dff_x, lut_y[5] + lut_h / 2.}}},
+        {id_I1MUX4,
+         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, mux5i_x,
+           grp_lut_y[3] - 5. * right_wire_dist},
+          {mux5i_x, grp_lut_y[3] - 5. * right_wire_dist, mux5i_x, lut_y[5] + lut_h / 2.},
+          {mux5i_x, lut_y[5] + lut_h / 2., mux2lut5_x, lut_y[5] + lut_h / 2.}}},
+        {id_SEL4,
+         {{cru_x + cru_w, grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[3] - 4. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[2] + mux_h - mux_f / 2.}}},
+        {id_SEL5,
+         {{cru_x + cru_w, grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           grp_lut_y[3] - 2. * right_wire_dist},
+          {mux2lut6_x + mux_w / 2., grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
+           mux2lut6_y[1] + mux_h - mux_f / 2.}}},
+        {id_F6,
+         {{cru_x + cru_w, grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[6] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[6] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2.}}},
+        {id_I0MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2., mux2lut5_x, lut_y[6] + lut_h / 2.}}},
+        // wires above LUT7
+        {id_F7,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           grp_lut_y[3] + grp_lut_h + right_wire_dist},
+          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
+           lut_y[7] + lut_h / 2.},
+          {lut_x + lut_w, lut_y[7] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2.}}},
+        {id_I1MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2., mux2lut5_x, lut_y[7] + lut_h / 2.}}},
+        {id_SEL6,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist},
+          {mux2lut5_x + mux_w / 2., grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
+           mux2lut5_y[3] + mux_h - mux_f / 2.}}},
+        {id_OF6,
+         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist},
+          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut5_y[3] + mux_h / 2.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[3] + mux_h / 2.}}},
+        {id_I0MUX5,
+         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + 4. / 3. * mux_w,
+           mux2lut6_y[1] + mux_h * 3. / 4.},
+          {mux2lut5_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h * 3. / 4., mux2lut6_x,
+           mux2lut6_y[1] + mux_h * 3. / 4.}}},
+};
+
+const dict<IdString, std::vector<std::tuple<float, float, float, float>>> globalSimpleWires = {
+        {id_I0MUX7,
+         {{mux2lut8_x, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4.},
+          {mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w,
+           cru_y - 2. * right_wire_dist},
+          {mux2lut8_x - 1. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
+           cru_y - 2. * right_wire_dist},
+          {1. + mux2lut7_x + 4. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
+           grp_lut_y[0] - 3. * right_wire_dist}}},
+};
+
+dict<IdString, std::vector<std::tuple<float, float, float, float>>> const globalWires = {
+#define PIP_Y(pip_id) (pipPoint.at(pip_id).second)
+#define WIRE_X(offset) (cru_x - ((float)offset) * sn_dist)
+        // 1 hop
+        {id_S10,
+         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
+          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. + PIP_Y(id_S101)},
+          {WIRE_X(1), -1. + PIP_Y(id_S101), WIRE_X(0), -1. + PIP_Y(id_S101)}}},
+        {id_N10,
+         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
+          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + PIP_Y(id_N101)},
+          {WIRE_X(2), 1. + PIP_Y(id_N101), WIRE_X(0), 1. + PIP_Y(id_N101)}}},
+        {id_S10_loop0,
+         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
+          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. * wrap_len},
+          {WIRE_X(1), -1. * wrap_len, WIRE_X(2), -1. * wrap_len},
+          {WIRE_X(2), -1. * wrap_len, WIRE_X(2), PIP_Y(id_N101)},
+          {WIRE_X(2), PIP_Y(id_N101), WIRE_X(0), PIP_Y(id_N101)}}},
+        {id_N10_loop0,
+         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
+          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + 1. * wrap_len},
+          {WIRE_X(2), 1. + 1. * wrap_len, WIRE_X(1), 1. + 1. * wrap_len},
+          {WIRE_X(1), 1. + 1. * wrap_len, WIRE_X(1), PIP_Y(id_S101)},
+          {WIRE_X(1), PIP_Y(id_S101), WIRE_X(0), PIP_Y(id_S101)}}},
+        {id_S13,
+         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
+          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. + PIP_Y(id_S131)},
+          {WIRE_X(3), -1. + PIP_Y(id_S131), WIRE_X(0), -1. + PIP_Y(id_S131)}}},
+        {id_N13,
+         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
+          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + PIP_Y(id_N131)},
+          {WIRE_X(4), 1. + PIP_Y(id_N131), WIRE_X(0), 1. + PIP_Y(id_N131)}}},
+        {id_S13_loop0,
+         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
+          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. * wrap_len},
+          {WIRE_X(3), -1. * wrap_len, WIRE_X(4), -1. * wrap_len},
+          {WIRE_X(4), -1. * wrap_len, WIRE_X(4), PIP_Y(id_N131)},
+          {WIRE_X(4), PIP_Y(id_N131), WIRE_X(0), PIP_Y(id_N131)}}},
+        {id_N13_loop0,
+         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
+          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + 1. * wrap_len},
+          {WIRE_X(4), 1. + 1. * wrap_len, WIRE_X(3), 1. + 1. * wrap_len},
+          {WIRE_X(3), 1. + 1. * wrap_len, WIRE_X(3), PIP_Y(id_S131)},
+          {WIRE_X(3), PIP_Y(id_S131), WIRE_X(0), PIP_Y(id_S131)}}},
+        // 1 hop SN
+        {id_SN10,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
+          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
+          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
+        {id_SN10_loop_n,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + 1. * wrap_len},
+          {WIRE_X(6), 1. + 1. * wrap_len, WIRE_X(5), 1. + 1. * wrap_len},
+          {WIRE_X(5), 1. + 1. * wrap_len, WIRE_X(5), PIP_Y(id_SN10)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
+          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
+        {id_SN10_loop_s,
+         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
+          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
+          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
+          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. * wrap_len},
+          {WIRE_X(5), -1. * wrap_len, WIRE_X(6), -1. * wrap_len},
+          {WIRE_X(6), -1. * wrap_len, WIRE_X(6), PIP_Y(id_N111)},
+          {WIRE_X(6), PIP_Y(id_N111), WIRE_X(0), PIP_Y(id_N111)}}},
+        {id_SN20,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
+          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
+          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
+        {id_SN20_loop_n,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + 1. * wrap_len},
+          {WIRE_X(8), 1. + 1. * wrap_len, WIRE_X(7), 1. + 1. * wrap_len},
+          {WIRE_X(7), 1. + 1. * wrap_len, WIRE_X(7), PIP_Y(id_SN10)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
+          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
+        {id_SN20_loop_s,
+         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
+          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
+          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
+          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. * wrap_len},
+          {WIRE_X(7), -1. * wrap_len, WIRE_X(8), -1. * wrap_len},
+          {WIRE_X(8), -1. * wrap_len, WIRE_X(8), PIP_Y(id_N121)},
+          {WIRE_X(8), PIP_Y(id_N121), WIRE_X(0), PIP_Y(id_N121)}}},
+        // 2 hop
+        {id_S20,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
+          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
+          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -2. + PIP_Y(id_S202)},
+          {WIRE_X(9), -2. + PIP_Y(id_S202), WIRE_X(0), -2. + PIP_Y(id_S202)}}},
+        {id_N20,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
+          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
+          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + PIP_Y(id_N202)},
+          {WIRE_X(10), 2. + PIP_Y(id_N202), WIRE_X(0), 2. + PIP_Y(id_N202)}}},
+        {id_S20_loop0,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. * wrap_len},
+          {WIRE_X(11), -1. * wrap_len, WIRE_X(12), -1. * wrap_len},
+          {WIRE_X(12), -1. * wrap_len, WIRE_X(12), PIP_Y(id_N201)},
+          {WIRE_X(12), PIP_Y(id_N201), WIRE_X(0), PIP_Y(id_N201)},
+          {WIRE_X(10), PIP_Y(id_N201), WIRE_X(10), 1. + PIP_Y(id_N202)},
+          {WIRE_X(10), 1. + PIP_Y(id_N202), WIRE_X(0), 1. + PIP_Y(id_N202)}}},
+        {id_N20_loop0,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + 1. * wrap_len},
+          {WIRE_X(12), 1. + 1. * wrap_len, WIRE_X(11), 1. + 1. * wrap_len},
+          {WIRE_X(11), 1. + 1. * wrap_len, WIRE_X(11), PIP_Y(id_S201)},
+          {WIRE_X(11), PIP_Y(id_S201), WIRE_X(0), PIP_Y(id_S201)},
+          {WIRE_X(9), PIP_Y(id_S201), WIRE_X(9), -1. + PIP_Y(id_S202)},
+          {WIRE_X(9), -1. + PIP_Y(id_S202), WIRE_X(0), -1. + PIP_Y(id_S202)}}},
+        {id_S20_loop1,
+         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
+          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
+          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
+          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -1. + -1. * wrap_len},
+          {WIRE_X(9), -1. + -1. * wrap_len, WIRE_X(10), -1. + -1. * wrap_len},
+          {WIRE_X(10), -1. + -1. * wrap_len, WIRE_X(10), -1. + PIP_Y(id_N202)},
+          {WIRE_X(10), -1. + PIP_Y(id_N202), WIRE_X(0), -1. + PIP_Y(id_N202)}}},
+        {id_N20_loop1,
+         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
+          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
+          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
+          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + 1. * wrap_len},
+          {WIRE_X(10), 2. + 1. * wrap_len, WIRE_X(9), 2. + 1. * wrap_len},
+          {WIRE_X(9), 2. + 1. * wrap_len, WIRE_X(9), 1. + PIP_Y(id_S202)},
+          {WIRE_X(9), 1. + PIP_Y(id_S202), WIRE_X(0), 1. + PIP_Y(id_S202)}}},
+        {id_S21,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
+          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
+          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -2. + PIP_Y(id_S212)},
+          {WIRE_X(13), -2. + PIP_Y(id_S212), WIRE_X(0), -2. + PIP_Y(id_S212)}}},
+        {id_N21,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
+          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
+          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + PIP_Y(id_N212)},
+          {WIRE_X(14), 2. + PIP_Y(id_N212), WIRE_X(0), 2. + PIP_Y(id_N212)}}},
+        {id_S21_loop0,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. * wrap_len},
+          {WIRE_X(15), -1. * wrap_len, WIRE_X(16), -1. * wrap_len},
+          {WIRE_X(16), -1. * wrap_len, WIRE_X(16), PIP_Y(id_N211)},
+          {WIRE_X(16), PIP_Y(id_N211), WIRE_X(0), PIP_Y(id_N211)},
+          {WIRE_X(14), PIP_Y(id_N211), WIRE_X(14), 1. + PIP_Y(id_N212)},
+          {WIRE_X(14), 1. + PIP_Y(id_N212), WIRE_X(0), 1. + PIP_Y(id_N212)}}},
+        {id_N21_loop0,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + 1. * wrap_len},
+          {WIRE_X(16), 1. + 1. * wrap_len, WIRE_X(15), 1. + 1. * wrap_len},
+          {WIRE_X(15), 1. + 1. * wrap_len, WIRE_X(15), PIP_Y(id_S211)},
+          {WIRE_X(15), PIP_Y(id_S211), WIRE_X(0), PIP_Y(id_S211)},
+          {WIRE_X(13), PIP_Y(id_S211), WIRE_X(13), -1. + PIP_Y(id_S212)},
+          {WIRE_X(13), -1. + PIP_Y(id_S212), WIRE_X(0), -1. + PIP_Y(id_S212)}}},
+        {id_S21_loop1,
+         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
+          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
+          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
+          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -1. + -1. * wrap_len},
+          {WIRE_X(13), -1. + -1. * wrap_len, WIRE_X(14), -1. + -1. * wrap_len},
+          {WIRE_X(14), -1. + -1. * wrap_len, WIRE_X(14), -1. + PIP_Y(id_N212)},
+          {WIRE_X(14), -1. + PIP_Y(id_N212), WIRE_X(0), -1. + PIP_Y(id_N212)}}},
+        {id_N21_loop1,
+         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
+          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
+          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
+          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + 1. * wrap_len},
+          {WIRE_X(14), 2. + 1. * wrap_len, WIRE_X(13), 2. + 1. * wrap_len},
+          {WIRE_X(13), 2. + 1. * wrap_len, WIRE_X(13), 1. + PIP_Y(id_S212)},
+          {WIRE_X(13), 1. + PIP_Y(id_S212), WIRE_X(0), 1. + PIP_Y(id_S212)}}},
+        {id_S22,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
+          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
+          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -2. + PIP_Y(id_S222)},
+          {WIRE_X(17), -2. + PIP_Y(id_S222), WIRE_X(0), -2. + PIP_Y(id_S222)}}},
+        {id_N22,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
+          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
+          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + PIP_Y(id_N222)},
+          {WIRE_X(18), 2. + PIP_Y(id_N222), WIRE_X(0), 2. + PIP_Y(id_N222)}}},
+        {id_S22_loop0,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. * wrap_len},
+          {WIRE_X(19), -1. * wrap_len, WIRE_X(20), -1. * wrap_len},
+          {WIRE_X(20), -1. * wrap_len, WIRE_X(20), PIP_Y(id_N221)},
+          {WIRE_X(20), PIP_Y(id_N221), WIRE_X(0), PIP_Y(id_N221)},
+          {WIRE_X(18), PIP_Y(id_N221), WIRE_X(18), 1. + PIP_Y(id_N222)},
+          {WIRE_X(18), 1. + PIP_Y(id_N222), WIRE_X(0), 1. + PIP_Y(id_N222)}}},
+        {id_N22_loop0,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + 1. * wrap_len},
+          {WIRE_X(20), 1. + 1. * wrap_len, WIRE_X(19), 1. + 1. * wrap_len},
+          {WIRE_X(19), 1. + 1. * wrap_len, WIRE_X(19), PIP_Y(id_S221)},
+          {WIRE_X(19), PIP_Y(id_S221), WIRE_X(0), PIP_Y(id_S221)},
+          {WIRE_X(17), PIP_Y(id_S221), WIRE_X(17), -1. + PIP_Y(id_S222)},
+          {WIRE_X(17), -1. + PIP_Y(id_S222), WIRE_X(0), -1. + PIP_Y(id_S222)}}},
+        {id_S22_loop1,
+         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
+          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
+          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
+          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -1. + -1. * wrap_len},
+          {WIRE_X(17), -1. + -1. * wrap_len, WIRE_X(18), -1. + -1. * wrap_len},
+          {WIRE_X(18), -1. + -1. * wrap_len, WIRE_X(18), -1. + PIP_Y(id_N222)},
+          {WIRE_X(18), -1. + PIP_Y(id_N222), WIRE_X(0), -1. + PIP_Y(id_N222)}}},
+        {id_N22_loop1,
+         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
+          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
+          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
+          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + 1. * wrap_len},
+          {WIRE_X(18), 2. + 1. * wrap_len, WIRE_X(17), 2. + 1. * wrap_len},
+          {WIRE_X(17), 2. + 1. * wrap_len, WIRE_X(17), 1. + PIP_Y(id_S222)},
+          {WIRE_X(17), 1. + PIP_Y(id_S222), WIRE_X(0), 1. + PIP_Y(id_S222)}}},
+        {id_S23,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
+          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
+          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -2. + PIP_Y(id_S232)},
+          {WIRE_X(21), -2. + PIP_Y(id_S232), WIRE_X(0), -2. + PIP_Y(id_S232)}}},
+        {id_N23,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
+          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
+          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + PIP_Y(id_N232)},
+          {WIRE_X(22), 2. + PIP_Y(id_N232), WIRE_X(0), 2. + PIP_Y(id_N232)}}},
+        {id_S23_loop0,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. * wrap_len},
+          {WIRE_X(23), -1. * wrap_len, WIRE_X(24), -1. * wrap_len},
+          {WIRE_X(24), -1. * wrap_len, WIRE_X(24), PIP_Y(id_N231)},
+          {WIRE_X(24), PIP_Y(id_N231), WIRE_X(0), PIP_Y(id_N231)},
+          {WIRE_X(22), PIP_Y(id_N231), WIRE_X(22), 1. + PIP_Y(id_N232)},
+          {WIRE_X(22), 1. + PIP_Y(id_N232), WIRE_X(0), 1. + PIP_Y(id_N232)}}},
+        {id_N23_loop0,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + 1. * wrap_len},
+          {WIRE_X(24), 1. + 1. * wrap_len, WIRE_X(23), 1. + 1. * wrap_len},
+          {WIRE_X(23), 1. + 1. * wrap_len, WIRE_X(23), PIP_Y(id_S231)},
+          {WIRE_X(23), PIP_Y(id_S231), WIRE_X(0), PIP_Y(id_S231)},
+          {WIRE_X(21), PIP_Y(id_S231), WIRE_X(21), -1. + PIP_Y(id_S232)},
+          {WIRE_X(21), -1. + PIP_Y(id_S232), WIRE_X(0), -1. + PIP_Y(id_S232)}}},
+        {id_S23_loop1,
+         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
+          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
+          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
+          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -1. + -1. * wrap_len},
+          {WIRE_X(21), -1. + -1. * wrap_len, WIRE_X(22), -1. + -1. * wrap_len},
+          {WIRE_X(22), -1. + -1. * wrap_len, WIRE_X(22), -1. + PIP_Y(id_N232)},
+          {WIRE_X(22), -1. + PIP_Y(id_N232), WIRE_X(0), -1. + PIP_Y(id_N232)}}},
+        {id_N23_loop1,
+         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
+          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
+          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
+          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + 1. * wrap_len},
+          {WIRE_X(22), 2. + 1. * wrap_len, WIRE_X(21), 2. + 1. * wrap_len},
+          {WIRE_X(21), 2. + 1. * wrap_len, WIRE_X(21), 1. + PIP_Y(id_S232)},
+          {WIRE_X(21), 1. + PIP_Y(id_S232), WIRE_X(0), 1. + PIP_Y(id_S232)}}},
+        {id_S24,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
+          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
+          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -2. + PIP_Y(id_S242)},
+          {WIRE_X(25), -2. + PIP_Y(id_S242), WIRE_X(0), -2. + PIP_Y(id_S242)}}},
+        {id_N24,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
+          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
+          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + PIP_Y(id_N242)},
+          {WIRE_X(26), 2. + PIP_Y(id_N242), WIRE_X(0), 2. + PIP_Y(id_N242)}}},
+        {id_S24_loop0,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. * wrap_len},
+          {WIRE_X(27), -1. * wrap_len, WIRE_X(28), -1. * wrap_len},
+          {WIRE_X(28), -1. * wrap_len, WIRE_X(28), PIP_Y(id_N241)},
+          {WIRE_X(28), PIP_Y(id_N241), WIRE_X(0), PIP_Y(id_N241)},
+          {WIRE_X(26), PIP_Y(id_N241), WIRE_X(26), 1. + PIP_Y(id_N242)},
+          {WIRE_X(26), 1. + PIP_Y(id_N242), WIRE_X(0), 1. + PIP_Y(id_N242)}}},
+        {id_N24_loop0,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + 1. * wrap_len},
+          {WIRE_X(28), 1. + 1. * wrap_len, WIRE_X(27), 1. + 1. * wrap_len},
+          {WIRE_X(27), 1. + 1. * wrap_len, WIRE_X(27), PIP_Y(id_S241)},
+          {WIRE_X(27), PIP_Y(id_S241), WIRE_X(0), PIP_Y(id_S241)},
+          {WIRE_X(25), PIP_Y(id_S241), WIRE_X(25), -1. + PIP_Y(id_S242)},
+          {WIRE_X(25), -1. + PIP_Y(id_S242), WIRE_X(0), -1. + PIP_Y(id_S242)}}},
+        {id_S24_loop1,
+         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
+          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
+          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
+          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -1. + -1. * wrap_len},
+          {WIRE_X(25), -1. + -1. * wrap_len, WIRE_X(26), -1. + -1. * wrap_len},
+          {WIRE_X(26), -1. + -1. * wrap_len, WIRE_X(26), -1. + PIP_Y(id_N242)},
+          {WIRE_X(26), -1. + PIP_Y(id_N242), WIRE_X(0), -1. + PIP_Y(id_N242)}}},
+        {id_N24_loop1,
+         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
+          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
+          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
+          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + 1. * wrap_len},
+          {WIRE_X(26), 2. + 1. * wrap_len, WIRE_X(25), 2. + 1. * wrap_len},
+          {WIRE_X(25), 2. + 1. * wrap_len, WIRE_X(25), 1. + PIP_Y(id_S242)},
+          {WIRE_X(25), 1. + PIP_Y(id_S242), WIRE_X(0), 1. + PIP_Y(id_S242)}}},
+        {id_S25,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
+          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
+          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -2. + PIP_Y(id_S252)},
+          {WIRE_X(29), -2. + PIP_Y(id_S252), WIRE_X(0), -2. + PIP_Y(id_S252)}}},
+        {id_N25,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
+          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
+          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + PIP_Y(id_N252)},
+          {WIRE_X(30), 2. + PIP_Y(id_N252), WIRE_X(0), 2. + PIP_Y(id_N252)}}},
+        {id_S25_loop0,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. * wrap_len},
+          {WIRE_X(31), -1. * wrap_len, WIRE_X(32), -1. * wrap_len},
+          {WIRE_X(32), -1. * wrap_len, WIRE_X(32), PIP_Y(id_N251)},
+          {WIRE_X(32), PIP_Y(id_N251), WIRE_X(0), PIP_Y(id_N251)},
+          {WIRE_X(30), PIP_Y(id_N251), WIRE_X(30), 1. + PIP_Y(id_N252)},
+          {WIRE_X(30), 1. + PIP_Y(id_N252), WIRE_X(0), 1. + PIP_Y(id_N252)}}},
+        {id_N25_loop0,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + 1. * wrap_len},
+          {WIRE_X(32), 1. + 1. * wrap_len, WIRE_X(31), 1. + 1. * wrap_len},
+          {WIRE_X(31), 1. + 1. * wrap_len, WIRE_X(31), PIP_Y(id_S251)},
+          {WIRE_X(31), PIP_Y(id_S251), WIRE_X(0), PIP_Y(id_S251)},
+          {WIRE_X(29), PIP_Y(id_S251), WIRE_X(29), -1. + PIP_Y(id_S252)},
+          {WIRE_X(29), -1. + PIP_Y(id_S252), WIRE_X(0), -1. + PIP_Y(id_S252)}}},
+        {id_S25_loop1,
+         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
+          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
+          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
+          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -1. + -1. * wrap_len},
+          {WIRE_X(29), -1. + -1. * wrap_len, WIRE_X(30), -1. + -1. * wrap_len},
+          {WIRE_X(30), -1. + -1. * wrap_len, WIRE_X(30), -1. + PIP_Y(id_N252)},
+          {WIRE_X(30), -1. + PIP_Y(id_N252), WIRE_X(0), -1. + PIP_Y(id_N252)}}},
+        {id_N25_loop1,
+         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
+          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
+          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
+          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + 1. * wrap_len},
+          {WIRE_X(30), 2. + 1. * wrap_len, WIRE_X(29), 2. + 1. * wrap_len},
+          {WIRE_X(29), 2. + 1. * wrap_len, WIRE_X(29), 1. + PIP_Y(id_S252)},
+          {WIRE_X(29), 1. + PIP_Y(id_S252), WIRE_X(0), 1. + PIP_Y(id_S252)}}},
+        {id_S26,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
+          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
+          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -2. + PIP_Y(id_S262)},
+          {WIRE_X(33), -2. + PIP_Y(id_S262), WIRE_X(0), -2. + PIP_Y(id_S262)}}},
+        {id_N26,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
+          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
+          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + PIP_Y(id_N262)},
+          {WIRE_X(34), 2. + PIP_Y(id_N262), WIRE_X(0), 2. + PIP_Y(id_N262)}}},
+        {id_S26_loop0,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. * wrap_len},
+          {WIRE_X(35), -1. * wrap_len, WIRE_X(36), -1. * wrap_len},
+          {WIRE_X(36), -1. * wrap_len, WIRE_X(36), PIP_Y(id_N261)},
+          {WIRE_X(36), PIP_Y(id_N261), WIRE_X(0), PIP_Y(id_N261)},
+          {WIRE_X(34), PIP_Y(id_N261), WIRE_X(34), 1. + PIP_Y(id_N262)},
+          {WIRE_X(34), 1. + PIP_Y(id_N262), WIRE_X(0), 1. + PIP_Y(id_N262)}}},
+        {id_N26_loop0,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + 1. * wrap_len},
+          {WIRE_X(36), 1. + 1. * wrap_len, WIRE_X(35), 1. + 1. * wrap_len},
+          {WIRE_X(35), 1. + 1. * wrap_len, WIRE_X(35), PIP_Y(id_S261)},
+          {WIRE_X(35), PIP_Y(id_S261), WIRE_X(0), PIP_Y(id_S261)},
+          {WIRE_X(33), PIP_Y(id_S261), WIRE_X(33), -1. + PIP_Y(id_S262)},
+          {WIRE_X(33), -1. + PIP_Y(id_S262), WIRE_X(0), -1. + PIP_Y(id_S262)}}},
+        {id_S26_loop1,
+         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
+          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
+          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
+          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -1. + -1. * wrap_len},
+          {WIRE_X(33), -1. + -1. * wrap_len, WIRE_X(34), -1. + -1. * wrap_len},
+          {WIRE_X(34), -1. + -1. * wrap_len, WIRE_X(34), -1. + PIP_Y(id_N262)},
+          {WIRE_X(34), -1. + PIP_Y(id_N262), WIRE_X(0), -1. + PIP_Y(id_N262)}}},
+        {id_N26_loop1,
+         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
+          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
+          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
+          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + 1. * wrap_len},
+          {WIRE_X(34), 2. + 1. * wrap_len, WIRE_X(33), 2. + 1. * wrap_len},
+          {WIRE_X(33), 2. + 1. * wrap_len, WIRE_X(33), 1. + PIP_Y(id_S262)},
+          {WIRE_X(33), 1. + PIP_Y(id_S262), WIRE_X(0), 1. + PIP_Y(id_S262)}}},
+        {id_S27,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
+          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
+          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -2. + PIP_Y(id_S272)},
+          {WIRE_X(37), -2. + PIP_Y(id_S272), WIRE_X(0), -2. + PIP_Y(id_S272)}}},
+        {id_N27,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
+          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
+          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + PIP_Y(id_N272)},
+          {WIRE_X(38), 2. + PIP_Y(id_N272), WIRE_X(0), 2. + PIP_Y(id_N272)}}},
+        {id_S27_loop0,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. * wrap_len},
+          {WIRE_X(39), -1. * wrap_len, WIRE_X(40), -1. * wrap_len},
+          {WIRE_X(40), -1. * wrap_len, WIRE_X(40), PIP_Y(id_N271)},
+          {WIRE_X(40), PIP_Y(id_N271), WIRE_X(0), PIP_Y(id_N271)},
+          {WIRE_X(38), PIP_Y(id_N271), WIRE_X(38), 1. + PIP_Y(id_N272)},
+          {WIRE_X(38), 1. + PIP_Y(id_N272), WIRE_X(0), 1. + PIP_Y(id_N272)}}},
+        {id_N27_loop0,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + 1. * wrap_len},
+          {WIRE_X(40), 1. + 1. * wrap_len, WIRE_X(39), 1. + 1. * wrap_len},
+          {WIRE_X(39), 1. + 1. * wrap_len, WIRE_X(39), PIP_Y(id_S271)},
+          {WIRE_X(39), PIP_Y(id_S271), WIRE_X(0), PIP_Y(id_S271)},
+          {WIRE_X(37), PIP_Y(id_S271), WIRE_X(37), -1. + PIP_Y(id_S272)},
+          {WIRE_X(37), -1. + PIP_Y(id_S272), WIRE_X(0), -1. + PIP_Y(id_S272)}}},
+        {id_S27_loop1,
+         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
+          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
+          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
+          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -1. + -1. * wrap_len},
+          {WIRE_X(37), -1. + -1. * wrap_len, WIRE_X(38), -1. + -1. * wrap_len},
+          {WIRE_X(38), -1. + -1. * wrap_len, WIRE_X(38), -1. + PIP_Y(id_N272)},
+          {WIRE_X(38), -1. + PIP_Y(id_N272), WIRE_X(0), -1. + PIP_Y(id_N272)}}},
+        {id_N27_loop1,
+         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
+          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
+          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
+          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + 1. * wrap_len},
+          {WIRE_X(38), 2. + 1. * wrap_len, WIRE_X(37), 2. + 1. * wrap_len},
+          {WIRE_X(37), 2. + 1. * wrap_len, WIRE_X(37), 1. + PIP_Y(id_S272)},
+          {WIRE_X(37), 1. + PIP_Y(id_S272), WIRE_X(0), 1. + PIP_Y(id_S272)}}},
+// clock taps
+#define CLK_GT00_X 41.f
+#define CLK_GT10_X 46.f
+// 4 hop
+#define HOP4X_START (CLK_GT00_X + 10.f)
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START)
+        {id_S80,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
+          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S808) - 8.},
+          {HOP4X(0), PIP_Y(id_S808) - 8., WIRE_X(0), PIP_Y(id_S808) - 8.}}},
+        {id_N80,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
+          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N808) + 8.},
+          {HOP4X(1), PIP_Y(id_N808) + 8., WIRE_X(0), PIP_Y(id_N808) + 8.}}},
+        {id_S80_loop0,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N800) - 0.},
+          {HOP4X(15), PIP_Y(id_N800) - 0., HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N800) + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N800) + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N800) + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N804) + 3., WIRE_X(0), PIP_Y(id_N804) + 3.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N800) + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N800) + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N800) + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N808) + 7.},
+          {HOP4X(1), PIP_Y(id_N808) + 7., WIRE_X(0), PIP_Y(id_N808) + 7.}}},
+        {id_S80_loop1,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N800) - 1.},
+          {HOP4X(13), PIP_Y(id_N800) - 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N800) - 0.},
+          {HOP4X(11), PIP_Y(id_N800) - 0., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N800) + 1.},
+          {HOP4X(9), PIP_Y(id_N800) + 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N804) + 1., WIRE_X(0), PIP_Y(id_N804) + 1.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N800) + 2.},
+          {HOP4X(7), PIP_Y(id_N800) + 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N800) + 3.},
+          {HOP4X(5), PIP_Y(id_N800) + 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N800) + 4.},
+          {HOP4X(3), PIP_Y(id_N800) + 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N808) + 5.},
+          {HOP4X(1), PIP_Y(id_N808) + 5., WIRE_X(0), PIP_Y(id_N808) + 5.}}},
+        {id_S80_loop2,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N800) - 2.},
+          {HOP4X(11), PIP_Y(id_N800) - 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N800) - 1.},
+          {HOP4X(9), PIP_Y(id_N800) - 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N804) - 1., WIRE_X(0), PIP_Y(id_N804) - 1.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N800) - 0.},
+          {HOP4X(7), PIP_Y(id_N800) - 0., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N800) + 1.},
+          {HOP4X(5), PIP_Y(id_N800) + 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N800) + 2.},
+          {HOP4X(3), PIP_Y(id_N800) + 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N808) + 3.},
+          {HOP4X(1), PIP_Y(id_N808) + 3., WIRE_X(0), PIP_Y(id_N808) + 3.}}},
+        {id_S80_loop3,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N800) - 3.},
+          {HOP4X(9), PIP_Y(id_N804) - 3., WIRE_X(0), PIP_Y(id_N804) - 3.},
+          {HOP4X(9), PIP_Y(id_N800) - 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N800) - 2.},
+          {HOP4X(7), PIP_Y(id_N800) - 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N800) - 1.},
+          {HOP4X(5), PIP_Y(id_N800) - 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N800) - 0.},
+          {HOP4X(3), PIP_Y(id_N800) - 0., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N808) + 1.},
+          {HOP4X(1), PIP_Y(id_N808) + 1., WIRE_X(0), PIP_Y(id_N808) + 1.}}},
+        {id_S80_loop4,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N800) - 4.},
+          {HOP4X(7), PIP_Y(id_N800) - 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N800) - 3.},
+          {HOP4X(5), PIP_Y(id_N800) - 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N800) - 2.},
+          {HOP4X(3), PIP_Y(id_N800) - 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N808) - 1.},
+          {HOP4X(1), PIP_Y(id_N808) - 1., WIRE_X(0), PIP_Y(id_N808) - 1.}}},
+        {id_S80_loop5,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N800) - 5.},
+          {HOP4X(5), PIP_Y(id_N800) - 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N800) - 4.},
+          {HOP4X(3), PIP_Y(id_N800) - 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N808) - 3.},
+          {HOP4X(1), PIP_Y(id_N808) - 3., WIRE_X(0), PIP_Y(id_N808) - 3.}}},
+        {id_S80_loop6,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N800) - 6.},
+          {HOP4X(3), PIP_Y(id_N800) - 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N808) - 5.},
+          {HOP4X(1), PIP_Y(id_N808) - 5., WIRE_X(0), PIP_Y(id_N808) - 5.}}},
+        {id_S80_loop7,
+         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
+          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
+          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
+          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
+          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
+          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
+          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
+          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
+          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
+          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
+          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N808) - 7.},
+          {HOP4X(1), PIP_Y(id_N808) - 7., WIRE_X(0), PIP_Y(id_N808) - 7.}}},
+        {id_N80_loop0,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N808) + 0.},
+          {HOP4X(14), PIP_Y(id_N808) + 0., HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N808) - 1.},
+          {HOP4X(12), PIP_Y(id_N808) - 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N808) - 2.},
+          {HOP4X(10), PIP_Y(id_N808) - 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N808) - 3.},
+          {HOP4X(8), PIP_Y(id_S804) - 3., WIRE_X(0), PIP_Y(id_S804) - 3.},
+          {HOP4X(8), PIP_Y(id_N808) - 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N808) - 4.},
+          {HOP4X(6), PIP_Y(id_N808) - 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N808) - 5.},
+          {HOP4X(4), PIP_Y(id_N808) - 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N808) - 6.},
+          {HOP4X(2), PIP_Y(id_N808) - 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S808) - 7.},
+          {HOP4X(0), PIP_Y(id_S808) - 7., WIRE_X(0), PIP_Y(id_S808) - 7.}}},
+        {id_N80_loop1,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N808) + 1.},
+          {HOP4X(12), PIP_Y(id_N808) + 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N808) + 0.},
+          {HOP4X(10), PIP_Y(id_N808) + 0., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N808) - 1.},
+          {HOP4X(8), PIP_Y(id_S804) - 1., WIRE_X(0), PIP_Y(id_S804) - 1.},
+          {HOP4X(8), PIP_Y(id_N808) - 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N808) - 2.},
+          {HOP4X(6), PIP_Y(id_N808) - 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N808) - 3.},
+          {HOP4X(4), PIP_Y(id_N808) - 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N808) - 4.},
+          {HOP4X(2), PIP_Y(id_N808) - 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S808) - 5.},
+          {HOP4X(0), PIP_Y(id_S808) - 5., WIRE_X(0), PIP_Y(id_S808) - 5.}}},
+        {id_N80_loop2,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N808) + 2.},
+          {HOP4X(10), PIP_Y(id_N808) + 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N808) + 1.},
+          {HOP4X(8), PIP_Y(id_S804) + 1., WIRE_X(0), PIP_Y(id_S804) + 1.},
+          {HOP4X(8), PIP_Y(id_N808) + 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N808) + 0.},
+          {HOP4X(6), PIP_Y(id_N808) + 0., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N808) - 1.},
+          {HOP4X(4), PIP_Y(id_N808) - 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N808) - 2.},
+          {HOP4X(2), PIP_Y(id_N808) - 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S808) - 3.},
+          {HOP4X(0), PIP_Y(id_S808) - 3., WIRE_X(0), PIP_Y(id_S808) - 3.}}},
+        {id_N80_loop3,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N808) + 3.},
+          {HOP4X(8), PIP_Y(id_S804) + 3., WIRE_X(0), PIP_Y(id_S804) + 3.},
+          {HOP4X(8), PIP_Y(id_N808) + 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N808) + 2.},
+          {HOP4X(6), PIP_Y(id_N808) + 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N808) + 1.},
+          {HOP4X(4), PIP_Y(id_N808) + 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N808) + 0.},
+          {HOP4X(2), PIP_Y(id_N808) + 0., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S808) - 1.},
+          {HOP4X(0), PIP_Y(id_S808) - 1., WIRE_X(0), PIP_Y(id_S808) - 1.}}},
+        {id_N80_loop4,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N808) + 4.},
+          {HOP4X(6), PIP_Y(id_N808) + 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N808) + 3.},
+          {HOP4X(4), PIP_Y(id_N808) + 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N808) + 2.},
+          {HOP4X(2), PIP_Y(id_N808) + 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S808) + 1.},
+          {HOP4X(0), PIP_Y(id_S808) + 1., WIRE_X(0), PIP_Y(id_S808) + 1.}}},
+        {id_N80_loop5,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N808) + 5.},
+          {HOP4X(4), PIP_Y(id_N808) + 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N808) + 4.},
+          {HOP4X(2), PIP_Y(id_N808) + 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S808) + 3.},
+          {HOP4X(0), PIP_Y(id_S808) + 3., WIRE_X(0), PIP_Y(id_S808) + 3.}}},
+        {id_N80_loop6,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N808) + 6.},
+          {HOP4X(2), PIP_Y(id_N808) + 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S808) + 5.},
+          {HOP4X(0), PIP_Y(id_S808) + 5., WIRE_X(0), PIP_Y(id_S808) + 5.}}},
+        {id_N80_loop7,
+         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
+          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
+          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
+          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
+          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
+          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
+          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
+          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
+          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
+          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S808) + 7.},
+          {HOP4X(0), PIP_Y(id_S808) + 7., WIRE_X(0), PIP_Y(id_S808) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f)
+        {id_S81,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
+          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S818) - 8.},
+          {HOP4X(0), PIP_Y(id_S818) - 8., WIRE_X(0), PIP_Y(id_S818) - 8.}}},
+        {id_N81,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
+          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N818) + 8.},
+          {HOP4X(1), PIP_Y(id_N818) + 8., WIRE_X(0), PIP_Y(id_N818) + 8.}}},
+        {id_S81_loop0,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N810) - 0.},
+          {HOP4X(15), PIP_Y(id_N810) - 0., HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N810) + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N810) + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N810) + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N814) + 3., WIRE_X(0), PIP_Y(id_N814) + 3.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N810) + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N810) + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N810) + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N818) + 7.},
+          {HOP4X(1), PIP_Y(id_N818) + 7., WIRE_X(0), PIP_Y(id_N818) + 7.}}},
+        {id_S81_loop1,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N810) - 1.},
+          {HOP4X(13), PIP_Y(id_N810) - 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N810) - 0.},
+          {HOP4X(11), PIP_Y(id_N810) - 0., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N810) + 1.},
+          {HOP4X(9), PIP_Y(id_N810) + 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N814) + 1., WIRE_X(0), PIP_Y(id_N814) + 1.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N810) + 2.},
+          {HOP4X(7), PIP_Y(id_N810) + 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N810) + 3.},
+          {HOP4X(5), PIP_Y(id_N810) + 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N810) + 4.},
+          {HOP4X(3), PIP_Y(id_N810) + 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N818) + 5.},
+          {HOP4X(1), PIP_Y(id_N818) + 5., WIRE_X(0), PIP_Y(id_N818) + 5.}}},
+        {id_S81_loop2,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N810) - 2.},
+          {HOP4X(11), PIP_Y(id_N810) - 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N810) - 1.},
+          {HOP4X(9), PIP_Y(id_N810) - 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N814) - 1., WIRE_X(0), PIP_Y(id_N814) - 1.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N810) - 0.},
+          {HOP4X(7), PIP_Y(id_N810) - 0., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N810) + 1.},
+          {HOP4X(5), PIP_Y(id_N810) + 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N810) + 2.},
+          {HOP4X(3), PIP_Y(id_N810) + 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N818) + 3.},
+          {HOP4X(1), PIP_Y(id_N818) + 3., WIRE_X(0), PIP_Y(id_N818) + 3.}}},
+        {id_S81_loop3,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N810) - 3.},
+          {HOP4X(9), PIP_Y(id_N814) - 3., WIRE_X(0), PIP_Y(id_N814) - 3.},
+          {HOP4X(9), PIP_Y(id_N810) - 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N810) - 2.},
+          {HOP4X(7), PIP_Y(id_N810) - 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N810) - 1.},
+          {HOP4X(5), PIP_Y(id_N810) - 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N810) - 0.},
+          {HOP4X(3), PIP_Y(id_N810) - 0., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N818) + 1.},
+          {HOP4X(1), PIP_Y(id_N818) + 1., WIRE_X(0), PIP_Y(id_N818) + 1.}}},
+        {id_S81_loop4,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N810) - 4.},
+          {HOP4X(7), PIP_Y(id_N810) - 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N810) - 3.},
+          {HOP4X(5), PIP_Y(id_N810) - 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N810) - 2.},
+          {HOP4X(3), PIP_Y(id_N810) - 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N818) - 1.},
+          {HOP4X(1), PIP_Y(id_N818) - 1., WIRE_X(0), PIP_Y(id_N818) - 1.}}},
+        {id_S81_loop5,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N810) - 5.},
+          {HOP4X(5), PIP_Y(id_N810) - 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N810) - 4.},
+          {HOP4X(3), PIP_Y(id_N810) - 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N818) - 3.},
+          {HOP4X(1), PIP_Y(id_N818) - 3., WIRE_X(0), PIP_Y(id_N818) - 3.}}},
+        {id_S81_loop6,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N810) - 6.},
+          {HOP4X(3), PIP_Y(id_N810) - 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N818) - 5.},
+          {HOP4X(1), PIP_Y(id_N818) - 5., WIRE_X(0), PIP_Y(id_N818) - 5.}}},
+        {id_S81_loop7,
+         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
+          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
+          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
+          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
+          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
+          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
+          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
+          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
+          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
+          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
+          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N818) - 7.},
+          {HOP4X(1), PIP_Y(id_N818) - 7., WIRE_X(0), PIP_Y(id_N818) - 7.}}},
+        {id_N81_loop0,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N818) + 0.},
+          {HOP4X(14), PIP_Y(id_N818) + 0., HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N818) - 1.},
+          {HOP4X(12), PIP_Y(id_N818) - 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N818) - 2.},
+          {HOP4X(10), PIP_Y(id_N818) - 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N818) - 3.},
+          {HOP4X(8), PIP_Y(id_S814) - 3., WIRE_X(0), PIP_Y(id_S814) - 3.},
+          {HOP4X(8), PIP_Y(id_N818) - 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N818) - 4.},
+          {HOP4X(6), PIP_Y(id_N818) - 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N818) - 5.},
+          {HOP4X(4), PIP_Y(id_N818) - 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N818) - 6.},
+          {HOP4X(2), PIP_Y(id_N818) - 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S818) - 7.},
+          {HOP4X(0), PIP_Y(id_S818) - 7., WIRE_X(0), PIP_Y(id_S818) - 7.}}},
+        {id_N81_loop1,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N818) + 1.},
+          {HOP4X(12), PIP_Y(id_N818) + 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N818) + 0.},
+          {HOP4X(10), PIP_Y(id_N818) + 0., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N818) - 1.},
+          {HOP4X(8), PIP_Y(id_S814) - 1., WIRE_X(0), PIP_Y(id_S814) - 1.},
+          {HOP4X(8), PIP_Y(id_N818) - 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N818) - 2.},
+          {HOP4X(6), PIP_Y(id_N818) - 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N818) - 3.},
+          {HOP4X(4), PIP_Y(id_N818) - 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N818) - 4.},
+          {HOP4X(2), PIP_Y(id_N818) - 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S818) - 5.},
+          {HOP4X(0), PIP_Y(id_S818) - 5., WIRE_X(0), PIP_Y(id_S818) - 5.}}},
+        {id_N81_loop2,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N818) + 2.},
+          {HOP4X(10), PIP_Y(id_N818) + 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N818) + 1.},
+          {HOP4X(8), PIP_Y(id_S814) + 1., WIRE_X(0), PIP_Y(id_S814) + 1.},
+          {HOP4X(8), PIP_Y(id_N818) + 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N818) + 0.},
+          {HOP4X(6), PIP_Y(id_N818) + 0., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N818) - 1.},
+          {HOP4X(4), PIP_Y(id_N818) - 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N818) - 2.},
+          {HOP4X(2), PIP_Y(id_N818) - 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S818) - 3.},
+          {HOP4X(0), PIP_Y(id_S818) - 3., WIRE_X(0), PIP_Y(id_S818) - 3.}}},
+        {id_N81_loop3,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N818) + 3.},
+          {HOP4X(8), PIP_Y(id_S814) + 3., WIRE_X(0), PIP_Y(id_S814) + 3.},
+          {HOP4X(8), PIP_Y(id_N818) + 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N818) + 2.},
+          {HOP4X(6), PIP_Y(id_N818) + 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N818) + 1.},
+          {HOP4X(4), PIP_Y(id_N818) + 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N818) + 0.},
+          {HOP4X(2), PIP_Y(id_N818) + 0., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S818) - 1.},
+          {HOP4X(0), PIP_Y(id_S818) - 1., WIRE_X(0), PIP_Y(id_S818) - 1.}}},
+        {id_N81_loop4,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N818) + 4.},
+          {HOP4X(6), PIP_Y(id_N818) + 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N818) + 3.},
+          {HOP4X(4), PIP_Y(id_N818) + 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N818) + 2.},
+          {HOP4X(2), PIP_Y(id_N818) + 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S818) + 1.},
+          {HOP4X(0), PIP_Y(id_S818) + 1., WIRE_X(0), PIP_Y(id_S818) + 1.}}},
+        {id_N81_loop5,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N818) + 5.},
+          {HOP4X(4), PIP_Y(id_N818) + 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N818) + 4.},
+          {HOP4X(2), PIP_Y(id_N818) + 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S818) + 3.},
+          {HOP4X(0), PIP_Y(id_S818) + 3., WIRE_X(0), PIP_Y(id_S818) + 3.}}},
+        {id_N81_loop6,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N818) + 6.},
+          {HOP4X(2), PIP_Y(id_N818) + 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S818) + 5.},
+          {HOP4X(0), PIP_Y(id_S818) + 5., WIRE_X(0), PIP_Y(id_S818) + 5.}}},
+        {id_N81_loop7,
+         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
+          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
+          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
+          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
+          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
+          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
+          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
+          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
+          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
+          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S818) + 7.},
+          {HOP4X(0), PIP_Y(id_S818) + 7., WIRE_X(0), PIP_Y(id_S818) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f)
+        {id_S82,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
+          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S828) - 8.},
+          {HOP4X(0), PIP_Y(id_S828) - 8., WIRE_X(0), PIP_Y(id_S828) - 8.}}},
+        {id_N82,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
+          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N828) + 8.},
+          {HOP4X(1), PIP_Y(id_N828) + 8., WIRE_X(0), PIP_Y(id_N828) + 8.}}},
+        {id_S82_loop0,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N820) - 0.},
+          {HOP4X(15), PIP_Y(id_N820) - 0., HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N820) + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N820) + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N820) + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N824) + 3., WIRE_X(0), PIP_Y(id_N824) + 3.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N820) + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N820) + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N820) + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N828) + 7.},
+          {HOP4X(1), PIP_Y(id_N828) + 7., WIRE_X(0), PIP_Y(id_N828) + 7.}}},
+        {id_S82_loop1,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N820) - 1.},
+          {HOP4X(13), PIP_Y(id_N820) - 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N820) - 0.},
+          {HOP4X(11), PIP_Y(id_N820) - 0., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N820) + 1.},
+          {HOP4X(9), PIP_Y(id_N820) + 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N824) + 1., WIRE_X(0), PIP_Y(id_N824) + 1.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N820) + 2.},
+          {HOP4X(7), PIP_Y(id_N820) + 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N820) + 3.},
+          {HOP4X(5), PIP_Y(id_N820) + 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N820) + 4.},
+          {HOP4X(3), PIP_Y(id_N820) + 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N828) + 5.},
+          {HOP4X(1), PIP_Y(id_N828) + 5., WIRE_X(0), PIP_Y(id_N828) + 5.}}},
+        {id_S82_loop2,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N820) - 2.},
+          {HOP4X(11), PIP_Y(id_N820) - 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N820) - 1.},
+          {HOP4X(9), PIP_Y(id_N820) - 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N824) - 1., WIRE_X(0), PIP_Y(id_N824) - 1.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N820) - 0.},
+          {HOP4X(7), PIP_Y(id_N820) - 0., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N820) + 1.},
+          {HOP4X(5), PIP_Y(id_N820) + 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N820) + 2.},
+          {HOP4X(3), PIP_Y(id_N820) + 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N828) + 3.},
+          {HOP4X(1), PIP_Y(id_N828) + 3., WIRE_X(0), PIP_Y(id_N828) + 3.}}},
+        {id_S82_loop3,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N820) - 3.},
+          {HOP4X(9), PIP_Y(id_N824) - 3., WIRE_X(0), PIP_Y(id_N824) - 3.},
+          {HOP4X(9), PIP_Y(id_N820) - 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N820) - 2.},
+          {HOP4X(7), PIP_Y(id_N820) - 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N820) - 1.},
+          {HOP4X(5), PIP_Y(id_N820) - 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N820) - 0.},
+          {HOP4X(3), PIP_Y(id_N820) - 0., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N828) + 1.},
+          {HOP4X(1), PIP_Y(id_N828) + 1., WIRE_X(0), PIP_Y(id_N828) + 1.}}},
+        {id_S82_loop4,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N820) - 4.},
+          {HOP4X(7), PIP_Y(id_N820) - 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N820) - 3.},
+          {HOP4X(5), PIP_Y(id_N820) - 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N820) - 2.},
+          {HOP4X(3), PIP_Y(id_N820) - 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N828) - 1.},
+          {HOP4X(1), PIP_Y(id_N828) - 1., WIRE_X(0), PIP_Y(id_N828) - 1.}}},
+        {id_S82_loop5,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N820) - 5.},
+          {HOP4X(5), PIP_Y(id_N820) - 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N820) - 4.},
+          {HOP4X(3), PIP_Y(id_N820) - 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N828) - 3.},
+          {HOP4X(1), PIP_Y(id_N828) - 3., WIRE_X(0), PIP_Y(id_N828) - 3.}}},
+        {id_S82_loop6,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N820) - 6.},
+          {HOP4X(3), PIP_Y(id_N820) - 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N828) - 5.},
+          {HOP4X(1), PIP_Y(id_N828) - 5., WIRE_X(0), PIP_Y(id_N828) - 5.}}},
+        {id_S82_loop7,
+         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
+          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
+          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
+          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
+          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
+          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
+          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
+          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
+          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
+          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
+          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N828) - 7.},
+          {HOP4X(1), PIP_Y(id_N828) - 7., WIRE_X(0), PIP_Y(id_N828) - 7.}}},
+        {id_N82_loop0,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N828) + 0.},
+          {HOP4X(14), PIP_Y(id_N828) + 0., HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N828) - 1.},
+          {HOP4X(12), PIP_Y(id_N828) - 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N828) - 2.},
+          {HOP4X(10), PIP_Y(id_N828) - 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N828) - 3.},
+          {HOP4X(8), PIP_Y(id_S824) - 3., WIRE_X(0), PIP_Y(id_S824) - 3.},
+          {HOP4X(8), PIP_Y(id_N828) - 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N828) - 4.},
+          {HOP4X(6), PIP_Y(id_N828) - 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N828) - 5.},
+          {HOP4X(4), PIP_Y(id_N828) - 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N828) - 6.},
+          {HOP4X(2), PIP_Y(id_N828) - 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S828) - 7.},
+          {HOP4X(0), PIP_Y(id_S828) - 7., WIRE_X(0), PIP_Y(id_S828) - 7.}}},
+        {id_N82_loop1,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N828) + 1.},
+          {HOP4X(12), PIP_Y(id_N828) + 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N828) + 0.},
+          {HOP4X(10), PIP_Y(id_N828) + 0., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N828) - 1.},
+          {HOP4X(8), PIP_Y(id_S824) - 1., WIRE_X(0), PIP_Y(id_S824) - 1.},
+          {HOP4X(8), PIP_Y(id_N828) - 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N828) - 2.},
+          {HOP4X(6), PIP_Y(id_N828) - 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N828) - 3.},
+          {HOP4X(4), PIP_Y(id_N828) - 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N828) - 4.},
+          {HOP4X(2), PIP_Y(id_N828) - 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S828) - 5.},
+          {HOP4X(0), PIP_Y(id_S828) - 5., WIRE_X(0), PIP_Y(id_S828) - 5.}}},
+        {id_N82_loop2,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N828) + 2.},
+          {HOP4X(10), PIP_Y(id_N828) + 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N828) + 1.},
+          {HOP4X(8), PIP_Y(id_S824) + 1., WIRE_X(0), PIP_Y(id_S824) + 1.},
+          {HOP4X(8), PIP_Y(id_N828) + 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N828) + 0.},
+          {HOP4X(6), PIP_Y(id_N828) + 0., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N828) - 1.},
+          {HOP4X(4), PIP_Y(id_N828) - 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N828) - 2.},
+          {HOP4X(2), PIP_Y(id_N828) - 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S828) - 3.},
+          {HOP4X(0), PIP_Y(id_S828) - 3., WIRE_X(0), PIP_Y(id_S828) - 3.}}},
+        {id_N82_loop3,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N828) + 3.},
+          {HOP4X(8), PIP_Y(id_S824) + 3., WIRE_X(0), PIP_Y(id_S824) + 3.},
+          {HOP4X(8), PIP_Y(id_N828) + 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N828) + 2.},
+          {HOP4X(6), PIP_Y(id_N828) + 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N828) + 1.},
+          {HOP4X(4), PIP_Y(id_N828) + 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N828) + 0.},
+          {HOP4X(2), PIP_Y(id_N828) + 0., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S828) - 1.},
+          {HOP4X(0), PIP_Y(id_S828) - 1., WIRE_X(0), PIP_Y(id_S828) - 1.}}},
+        {id_N82_loop4,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N828) + 4.},
+          {HOP4X(6), PIP_Y(id_N828) + 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N828) + 3.},
+          {HOP4X(4), PIP_Y(id_N828) + 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N828) + 2.},
+          {HOP4X(2), PIP_Y(id_N828) + 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S828) + 1.},
+          {HOP4X(0), PIP_Y(id_S828) + 1., WIRE_X(0), PIP_Y(id_S828) + 1.}}},
+        {id_N82_loop5,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N828) + 5.},
+          {HOP4X(4), PIP_Y(id_N828) + 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N828) + 4.},
+          {HOP4X(2), PIP_Y(id_N828) + 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S828) + 3.},
+          {HOP4X(0), PIP_Y(id_S828) + 3., WIRE_X(0), PIP_Y(id_S828) + 3.}}},
+        {id_N82_loop6,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N828) + 6.},
+          {HOP4X(2), PIP_Y(id_N828) + 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S828) + 5.},
+          {HOP4X(0), PIP_Y(id_S828) + 5., WIRE_X(0), PIP_Y(id_S828) + 5.}}},
+        {id_N82_loop7,
+         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
+          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
+          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
+          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
+          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
+          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
+          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
+          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
+          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
+          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S828) + 7.},
+          {HOP4X(0), PIP_Y(id_S828) + 7., WIRE_X(0), PIP_Y(id_S828) + 7.}}},
+
+#undef HOP4X
+#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f + 18.f)
+        {id_S83,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
+          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S838) - 8.},
+          {HOP4X(0), PIP_Y(id_S838) - 8., WIRE_X(0), PIP_Y(id_S838) - 8.}}},
+        {id_N83,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
+          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N838) + 8.},
+          {HOP4X(1), PIP_Y(id_N838) + 8., WIRE_X(0), PIP_Y(id_N838) + 8.}}},
+        {id_S83_loop0,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
+          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
+          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N830) - 0.},
+          {HOP4X(15), PIP_Y(id_N830) - 0., HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N830) + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N830) + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N830) + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N834) + 3., WIRE_X(0), PIP_Y(id_N834) + 3.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N830) + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N830) + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N830) + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N838) + 7.},
+          {HOP4X(1), PIP_Y(id_N838) + 7., WIRE_X(0), PIP_Y(id_N838) + 7.}}},
+        {id_S83_loop1,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
+          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
+          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N830) - 1.},
+          {HOP4X(13), PIP_Y(id_N830) - 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N830) - 0.},
+          {HOP4X(11), PIP_Y(id_N830) - 0., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N830) + 1.},
+          {HOP4X(9), PIP_Y(id_N830) + 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(9), PIP_Y(id_N834) + 1., WIRE_X(0), PIP_Y(id_N834) + 1.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N830) + 2.},
+          {HOP4X(7), PIP_Y(id_N830) + 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N830) + 3.},
+          {HOP4X(5), PIP_Y(id_N830) + 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N830) + 4.},
+          {HOP4X(3), PIP_Y(id_N830) + 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N838) + 5.},
+          {HOP4X(1), PIP_Y(id_N838) + 5., WIRE_X(0), PIP_Y(id_N838) + 5.}}},
+        {id_S83_loop2,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
+          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
+          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N830) - 2.},
+          {HOP4X(11), PIP_Y(id_N830) - 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N830) - 1.},
+          {HOP4X(9), PIP_Y(id_N830) - 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(9), PIP_Y(id_N834) - 1., WIRE_X(0), PIP_Y(id_N834) - 1.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N830) - 0.},
+          {HOP4X(7), PIP_Y(id_N830) - 0., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N830) + 1.},
+          {HOP4X(5), PIP_Y(id_N830) + 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N830) + 2.},
+          {HOP4X(3), PIP_Y(id_N830) + 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N838) + 3.},
+          {HOP4X(1), PIP_Y(id_N838) + 3., WIRE_X(0), PIP_Y(id_N838) + 3.}}},
+        {id_S83_loop3,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
+          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
+          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N830) - 3.},
+          {HOP4X(9), PIP_Y(id_N834) - 3., WIRE_X(0), PIP_Y(id_N834) - 3.},
+          {HOP4X(9), PIP_Y(id_N830) - 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N830) - 2.},
+          {HOP4X(7), PIP_Y(id_N830) - 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N830) - 1.},
+          {HOP4X(5), PIP_Y(id_N830) - 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N830) - 0.},
+          {HOP4X(3), PIP_Y(id_N830) - 0., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N838) + 1.},
+          {HOP4X(1), PIP_Y(id_N838) + 1., WIRE_X(0), PIP_Y(id_N838) + 1.}}},
+        {id_S83_loop4,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
+          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
+          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N830) - 4.},
+          {HOP4X(7), PIP_Y(id_N830) - 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N830) - 3.},
+          {HOP4X(5), PIP_Y(id_N830) - 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N830) - 2.},
+          {HOP4X(3), PIP_Y(id_N830) - 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N838) - 1.},
+          {HOP4X(1), PIP_Y(id_N838) - 1., WIRE_X(0), PIP_Y(id_N838) - 1.}}},
+        {id_S83_loop5,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
+          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
+          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N830) - 5.},
+          {HOP4X(5), PIP_Y(id_N830) - 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N830) - 4.},
+          {HOP4X(3), PIP_Y(id_N830) - 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N838) - 3.},
+          {HOP4X(1), PIP_Y(id_N838) - 3., WIRE_X(0), PIP_Y(id_N838) - 3.}}},
+        {id_S83_loop6,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
+          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
+          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N830) - 6.},
+          {HOP4X(3), PIP_Y(id_N830) - 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N838) - 5.},
+          {HOP4X(1), PIP_Y(id_N838) - 5., WIRE_X(0), PIP_Y(id_N838) - 5.}}},
+        {id_S83_loop7,
+         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
+          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
+          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
+          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
+          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
+          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
+          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
+          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
+          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
+          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
+          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
+          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
+          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
+          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N838) - 7.},
+          {HOP4X(1), PIP_Y(id_N838) - 7., WIRE_X(0), PIP_Y(id_N838) - 7.}}},
+        {id_N83_loop0,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
+          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
+          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N838) + 0.},
+          {HOP4X(14), PIP_Y(id_N838) + 0., HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N838) - 1.},
+          {HOP4X(12), PIP_Y(id_N838) - 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N838) - 2.},
+          {HOP4X(10), PIP_Y(id_N838) - 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N838) - 3.},
+          {HOP4X(8), PIP_Y(id_S834) - 3., WIRE_X(0), PIP_Y(id_S834) - 3.},
+          {HOP4X(8), PIP_Y(id_N838) - 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N838) - 4.},
+          {HOP4X(6), PIP_Y(id_N838) - 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N838) - 5.},
+          {HOP4X(4), PIP_Y(id_N838) - 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N838) - 6.},
+          {HOP4X(2), PIP_Y(id_N838) - 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S838) - 7.},
+          {HOP4X(0), PIP_Y(id_S838) - 7., WIRE_X(0), PIP_Y(id_S838) - 7.}}},
+        {id_N83_loop1,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
+          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
+          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N838) + 1.},
+          {HOP4X(12), PIP_Y(id_N838) + 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N838) + 0.},
+          {HOP4X(10), PIP_Y(id_N838) + 0., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N838) - 1.},
+          {HOP4X(8), PIP_Y(id_S834) - 1., WIRE_X(0), PIP_Y(id_S834) - 1.},
+          {HOP4X(8), PIP_Y(id_N838) - 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N838) - 2.},
+          {HOP4X(6), PIP_Y(id_N838) - 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N838) - 3.},
+          {HOP4X(4), PIP_Y(id_N838) - 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N838) - 4.},
+          {HOP4X(2), PIP_Y(id_N838) - 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S838) - 5.},
+          {HOP4X(0), PIP_Y(id_S838) - 5., WIRE_X(0), PIP_Y(id_S838) - 5.}}},
+        {id_N83_loop2,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
+          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
+          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N838) + 2.},
+          {HOP4X(10), PIP_Y(id_N838) + 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N838) + 1.},
+          {HOP4X(8), PIP_Y(id_S834) + 1., WIRE_X(0), PIP_Y(id_S834) + 1.},
+          {HOP4X(8), PIP_Y(id_N838) + 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N838) + 0.},
+          {HOP4X(6), PIP_Y(id_N838) + 0., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N838) - 1.},
+          {HOP4X(4), PIP_Y(id_N838) - 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N838) - 2.},
+          {HOP4X(2), PIP_Y(id_N838) - 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S838) - 3.},
+          {HOP4X(0), PIP_Y(id_S838) - 3., WIRE_X(0), PIP_Y(id_S838) - 3.}}},
+        {id_N83_loop3,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
+          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
+          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N838) + 3.},
+          {HOP4X(8), PIP_Y(id_S834) + 3., WIRE_X(0), PIP_Y(id_S834) + 3.},
+          {HOP4X(8), PIP_Y(id_N838) + 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3.},
+          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N838) + 2.},
+          {HOP4X(6), PIP_Y(id_N838) + 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N838) + 1.},
+          {HOP4X(4), PIP_Y(id_N838) + 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N838) + 0.},
+          {HOP4X(2), PIP_Y(id_N838) + 0., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S838) - 1.},
+          {HOP4X(0), PIP_Y(id_S838) - 1., WIRE_X(0), PIP_Y(id_S838) - 1.}}},
+        {id_N83_loop4,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
+          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
+          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N838) + 4.},
+          {HOP4X(6), PIP_Y(id_N838) + 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4.},
+          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N838) + 3.},
+          {HOP4X(4), PIP_Y(id_N838) + 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N838) + 2.},
+          {HOP4X(2), PIP_Y(id_N838) + 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S838) + 1.},
+          {HOP4X(0), PIP_Y(id_S838) + 1., WIRE_X(0), PIP_Y(id_S838) + 1.}}},
+        {id_N83_loop5,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
+          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
+          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N838) + 5.},
+          {HOP4X(4), PIP_Y(id_N838) + 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5.},
+          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N838) + 4.},
+          {HOP4X(2), PIP_Y(id_N838) + 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S838) + 3.},
+          {HOP4X(0), PIP_Y(id_S838) + 3., WIRE_X(0), PIP_Y(id_S838) + 3.}}},
+        {id_N83_loop6,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
+          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
+          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N838) + 6.},
+          {HOP4X(2), PIP_Y(id_N838) + 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6.},
+          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S838) + 5.},
+          {HOP4X(0), PIP_Y(id_S838) + 5., WIRE_X(0), PIP_Y(id_S838) + 5.}}},
+        {id_N83_loop7,
+         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
+          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
+          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
+          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
+          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
+          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
+          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
+          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
+          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
+          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
+          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
+          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
+          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
+          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
+          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
+          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
+          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
+          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
+          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
+          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S838) + 7.},
+          {HOP4X(0), PIP_Y(id_S838) + 7., WIRE_X(0), PIP_Y(id_S838) + 7.}}},
+
+#define PIP_X(pip_id) (pipPoint.at(pip_id).second)
+#define WIRE_Y(offset) (cru_y + cru_h + ((float)offset) * ew_dist)
+        // 1 hop
+        {id_E10,
+         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
+          {PIP_X(id_E100), WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(1)},
+          {PIP_X(id_E101) + 1., WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(0)}}},
+        {id_W10,
+         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
+          {PIP_X(id_W100), WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(2)},
+          {PIP_X(id_W101) - 1., WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(0)}}},
+        {id_E10_loop0,
+         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
+          {PIP_X(id_E100), WIRE_Y(1), 1. + wrap_len, WIRE_Y(1)},
+          {1. + wrap_len, WIRE_Y(1), 1. + wrap_len, WIRE_Y(2)},
+          {1. + wrap_len, WIRE_Y(2), PIP_X(id_W101), WIRE_Y(2)},
+          {PIP_X(id_W101), WIRE_Y(2), PIP_X(id_W101), WIRE_Y(0)}}},
+        {id_W10_loop0,
+         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
+          {PIP_X(id_W100), WIRE_Y(2), -1. * wrap_len, WIRE_Y(2)},
+          {-1. * wrap_len, WIRE_Y(2), -1. * wrap_len, WIRE_Y(1)},
+          {-1. * wrap_len, WIRE_Y(1), PIP_X(id_E101), WIRE_Y(1)},
+          {PIP_X(id_E101), WIRE_Y(1), PIP_X(id_E101), WIRE_Y(0)}}},
+        {id_E13,
+         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
+          {PIP_X(id_E130), WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(3)},
+          {PIP_X(id_E131) + 1., WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(0)}}},
+        {id_W13,
+         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
+          {PIP_X(id_W130), WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(4)},
+          {PIP_X(id_W131) - 1., WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(0)}}},
+        {id_E13_loop0,
+         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
+          {PIP_X(id_E130), WIRE_Y(3), 1. + wrap_len, WIRE_Y(3)},
+          {1. + wrap_len, WIRE_Y(3), 1. + wrap_len, WIRE_Y(4)},
+          {1. + wrap_len, WIRE_Y(4), PIP_X(id_W131), WIRE_Y(4)},
+          {PIP_X(id_W131), WIRE_Y(4), PIP_X(id_W131), WIRE_Y(0)}}},
+        {id_W13_loop0,
+         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
+          {PIP_X(id_W130), WIRE_Y(4), -1. * wrap_len, WIRE_Y(4)},
+          {-1. * wrap_len, WIRE_Y(4), -1. * wrap_len, WIRE_Y(3)},
+          {-1. * wrap_len, WIRE_Y(3), PIP_X(id_E131), WIRE_Y(3)},
+          {PIP_X(id_E131), WIRE_Y(3), PIP_X(id_E131), WIRE_Y(0)}}},
+        // 1 hop EW
+        {id_EW10,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
+          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
+          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
+        {id_EW10_loop_e,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), wrap_len + 1., WIRE_Y(6)},
+          {wrap_len + 1., WIRE_Y(6), wrap_len + 1., WIRE_Y(5)},
+          {wrap_len + 1., WIRE_Y(5), PIP_X(id_W111), WIRE_Y(5)},
+          {PIP_X(id_W111), WIRE_Y(5), PIP_X(id_W111), WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
+          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
+        {id_EW10_loop_w,
+         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
+          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
+          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW10), WIRE_Y(5), -wrap_len, WIRE_Y(5)},
+          {-wrap_len, WIRE_Y(5), -wrap_len, WIRE_Y(6)},
+          {-wrap_len, WIRE_Y(6), PIP_X(id_E111), WIRE_Y(6)},
+          {PIP_X(id_E111), WIRE_Y(6), PIP_X(id_E111), WIRE_Y(0)}}},
+        {id_EW20,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
+          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
+          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
+        {id_EW20_loop_e,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), wrap_len + 1., WIRE_Y(8)},
+          {wrap_len + 1., WIRE_Y(8), wrap_len + 1., WIRE_Y(7)},
+          {wrap_len + 1., WIRE_Y(7), PIP_X(id_W121), WIRE_Y(7)},
+          {PIP_X(id_W121), WIRE_Y(7), PIP_X(id_W121), WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
+          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
+        {id_EW20_loop_w,
+         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
+          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
+          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
+          {PIP_X(id_EW20), WIRE_Y(7), -wrap_len, WIRE_Y(7)},
+          {-wrap_len, WIRE_Y(7), -wrap_len, WIRE_Y(8)},
+          {-wrap_len, WIRE_Y(8), PIP_X(id_E121), WIRE_Y(8)},
+          {PIP_X(id_E121), WIRE_Y(8), PIP_X(id_E121), WIRE_Y(0)}}},
+// 2 hop
+#define HOP2Y(offset) WIRE_Y(offset + 9)
+        {id_E20,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
+          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
+          {PIP_X(id_E201) + 1., HOP2Y(0), PIP_X(id_E202) + 2., HOP2Y(0)},
+          {PIP_X(id_E202) + 2., HOP2Y(0), PIP_X(id_E202) + 2., WIRE_Y(0)}}},
+        {id_W20,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
+          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
+          {PIP_X(id_W201) - 1., HOP2Y(1), PIP_X(id_W202) - 2., HOP2Y(1)},
+          {PIP_X(id_W202) - 2., HOP2Y(1), PIP_X(id_W202) - 2., WIRE_Y(0)}}},
+        {id_E20_loop0,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W201), HOP2Y(3)},
+          {PIP_X(id_W201), HOP2Y(3), PIP_X(id_W201), WIRE_Y(0)},
+          {PIP_X(id_W201), HOP2Y(1), PIP_X(id_W202) - 1., HOP2Y(1)},
+          {PIP_X(id_W202) - 1., HOP2Y(1), PIP_X(id_W202) - 1., WIRE_Y(0)}}},
+        {id_W20_loop0,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E201), HOP2Y(2)},
+          {PIP_X(id_E201), HOP2Y(2), PIP_X(id_E201), WIRE_Y(0)},
+          {PIP_X(id_E201), HOP2Y(0), PIP_X(id_E202) + 1., HOP2Y(0)},
+          {PIP_X(id_E202) + 1., HOP2Y(0), PIP_X(id_E202) + 1., WIRE_Y(0)}}},
+        {id_E20_loop1,
+         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
+          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
+          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
+          {PIP_X(id_E201) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W202) + 1., HOP2Y(1)},
+          {PIP_X(id_W202) + 1., HOP2Y(1), PIP_X(id_W202) + 1., WIRE_Y(0)}}},
+        {id_W20_loop1,
+         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
+          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
+          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
+          {PIP_X(id_W201) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E202) - 1., HOP2Y(0)},
+          {PIP_X(id_E202) - 1., HOP2Y(0), PIP_X(id_E202) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 1)
+        {id_E21,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
+          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
+          {PIP_X(id_E211) + 1., HOP2Y(0), PIP_X(id_E212) + 2., HOP2Y(0)},
+          {PIP_X(id_E212) + 2., HOP2Y(0), PIP_X(id_E212) + 2., WIRE_Y(0)}}},
+        {id_W21,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
+          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
+          {PIP_X(id_W211) - 1., HOP2Y(1), PIP_X(id_W212) - 2., HOP2Y(1)},
+          {PIP_X(id_W212) - 2., HOP2Y(1), PIP_X(id_W212) - 2., WIRE_Y(0)}}},
+        {id_E21_loop0,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W211), HOP2Y(3)},
+          {PIP_X(id_W211), HOP2Y(3), PIP_X(id_W211), WIRE_Y(0)},
+          {PIP_X(id_W211), HOP2Y(1), PIP_X(id_W212) - 1., HOP2Y(1)},
+          {PIP_X(id_W212) - 1., HOP2Y(1), PIP_X(id_W212) - 1., WIRE_Y(0)}}},
+        {id_W21_loop0,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E211), HOP2Y(2)},
+          {PIP_X(id_E211), HOP2Y(2), PIP_X(id_E211), WIRE_Y(0)},
+          {PIP_X(id_E211), HOP2Y(0), PIP_X(id_E212) + 1., HOP2Y(0)},
+          {PIP_X(id_E212) + 1., HOP2Y(0), PIP_X(id_E212) + 1., WIRE_Y(0)}}},
+        {id_E21_loop1,
+         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
+          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
+          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
+          {PIP_X(id_E211) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W212) + 1., HOP2Y(1)},
+          {PIP_X(id_W212) + 1., HOP2Y(1), PIP_X(id_W212) + 1., WIRE_Y(0)}}},
+        {id_W21_loop1,
+         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
+          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
+          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
+          {PIP_X(id_W211) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E212) - 1., HOP2Y(0)},
+          {PIP_X(id_E212) - 1., HOP2Y(0), PIP_X(id_E212) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 2)
+        {id_E22,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
+          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
+          {PIP_X(id_E221) + 1., HOP2Y(0), PIP_X(id_E222) + 2., HOP2Y(0)},
+          {PIP_X(id_E222) + 2., HOP2Y(0), PIP_X(id_E222) + 2., WIRE_Y(0)}}},
+        {id_W22,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
+          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
+          {PIP_X(id_W221) - 1., HOP2Y(1), PIP_X(id_W222) - 2., HOP2Y(1)},
+          {PIP_X(id_W222) - 2., HOP2Y(1), PIP_X(id_W222) - 2., WIRE_Y(0)}}},
+        {id_E22_loop0,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W221), HOP2Y(3)},
+          {PIP_X(id_W221), HOP2Y(3), PIP_X(id_W221), WIRE_Y(0)},
+          {PIP_X(id_W221), HOP2Y(1), PIP_X(id_W222) - 1., HOP2Y(1)},
+          {PIP_X(id_W222) - 1., HOP2Y(1), PIP_X(id_W222) - 1., WIRE_Y(0)}}},
+        {id_W22_loop0,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E221), HOP2Y(2)},
+          {PIP_X(id_E221), HOP2Y(2), PIP_X(id_E221), WIRE_Y(0)},
+          {PIP_X(id_E221), HOP2Y(0), PIP_X(id_E222) + 1., HOP2Y(0)},
+          {PIP_X(id_E222) + 1., HOP2Y(0), PIP_X(id_E222) + 1., WIRE_Y(0)}}},
+        {id_E22_loop1,
+         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
+          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
+          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
+          {PIP_X(id_E221) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W222) + 1., HOP2Y(1)},
+          {PIP_X(id_W222) + 1., HOP2Y(1), PIP_X(id_W222) + 1., WIRE_Y(0)}}},
+        {id_W22_loop1,
+         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
+          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
+          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
+          {PIP_X(id_W221) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E222) - 1., HOP2Y(0)},
+          {PIP_X(id_E222) - 1., HOP2Y(0), PIP_X(id_E222) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 3)
+        {id_E23,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
+          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
+          {PIP_X(id_E231) + 1., HOP2Y(0), PIP_X(id_E232) + 2., HOP2Y(0)},
+          {PIP_X(id_E232) + 2., HOP2Y(0), PIP_X(id_E232) + 2., WIRE_Y(0)}}},
+        {id_W23,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
+          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
+          {PIP_X(id_W231) - 1., HOP2Y(1), PIP_X(id_W232) - 2., HOP2Y(1)},
+          {PIP_X(id_W232) - 2., HOP2Y(1), PIP_X(id_W232) - 2., WIRE_Y(0)}}},
+        {id_E23_loop0,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W231), HOP2Y(3)},
+          {PIP_X(id_W231), HOP2Y(3), PIP_X(id_W231), WIRE_Y(0)},
+          {PIP_X(id_W231), HOP2Y(1), PIP_X(id_W232) - 1., HOP2Y(1)},
+          {PIP_X(id_W232) - 1., HOP2Y(1), PIP_X(id_W232) - 1., WIRE_Y(0)}}},
+        {id_W23_loop0,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E231), HOP2Y(2)},
+          {PIP_X(id_E231), HOP2Y(2), PIP_X(id_E231), WIRE_Y(0)},
+          {PIP_X(id_E231), HOP2Y(0), PIP_X(id_E232) + 1., HOP2Y(0)},
+          {PIP_X(id_E232) + 1., HOP2Y(0), PIP_X(id_E232) + 1., WIRE_Y(0)}}},
+        {id_E23_loop1,
+         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
+          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
+          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
+          {PIP_X(id_E231) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W232) + 1., HOP2Y(1)},
+          {PIP_X(id_W232) + 1., HOP2Y(1), PIP_X(id_W232) + 1., WIRE_Y(0)}}},
+        {id_W23_loop1,
+         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
+          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
+          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
+          {PIP_X(id_W231) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E232) - 1., HOP2Y(0)},
+          {PIP_X(id_E232) - 1., HOP2Y(0), PIP_X(id_E232) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 4)
+        {id_E24,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
+          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
+          {PIP_X(id_E241) + 1., HOP2Y(0), PIP_X(id_E242) + 2., HOP2Y(0)},
+          {PIP_X(id_E242) + 2., HOP2Y(0), PIP_X(id_E242) + 2., WIRE_Y(0)}}},
+        {id_W24,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
+          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
+          {PIP_X(id_W241) - 1., HOP2Y(1), PIP_X(id_W242) - 2., HOP2Y(1)},
+          {PIP_X(id_W242) - 2., HOP2Y(1), PIP_X(id_W242) - 2., WIRE_Y(0)}}},
+        {id_E24_loop0,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W241), HOP2Y(3)},
+          {PIP_X(id_W241), HOP2Y(3), PIP_X(id_W241), WIRE_Y(0)},
+          {PIP_X(id_W241), HOP2Y(1), PIP_X(id_W242) - 1., HOP2Y(1)},
+          {PIP_X(id_W242) - 1., HOP2Y(1), PIP_X(id_W242) - 1., WIRE_Y(0)}}},
+        {id_W24_loop0,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E241), HOP2Y(2)},
+          {PIP_X(id_E241), HOP2Y(2), PIP_X(id_E241), WIRE_Y(0)},
+          {PIP_X(id_E241), HOP2Y(0), PIP_X(id_E242) + 1., HOP2Y(0)},
+          {PIP_X(id_E242) + 1., HOP2Y(0), PIP_X(id_E242) + 1., WIRE_Y(0)}}},
+        {id_E24_loop1,
+         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
+          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
+          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
+          {PIP_X(id_E241) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W242) + 1., HOP2Y(1)},
+          {PIP_X(id_W242) + 1., HOP2Y(1), PIP_X(id_W242) + 1., WIRE_Y(0)}}},
+        {id_W24_loop1,
+         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
+          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
+          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
+          {PIP_X(id_W241) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E242) - 1., HOP2Y(0)},
+          {PIP_X(id_E242) - 1., HOP2Y(0), PIP_X(id_E242) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 5)
+        {id_E25,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
+          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
+          {PIP_X(id_E251) + 1., HOP2Y(0), PIP_X(id_E252) + 2., HOP2Y(0)},
+          {PIP_X(id_E252) + 2., HOP2Y(0), PIP_X(id_E252) + 2., WIRE_Y(0)}}},
+        {id_W25,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
+          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
+          {PIP_X(id_W251) - 1., HOP2Y(1), PIP_X(id_W252) - 2., HOP2Y(1)},
+          {PIP_X(id_W252) - 2., HOP2Y(1), PIP_X(id_W252) - 2., WIRE_Y(0)}}},
+        {id_E25_loop0,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W251), HOP2Y(3)},
+          {PIP_X(id_W251), HOP2Y(3), PIP_X(id_W251), WIRE_Y(0)},
+          {PIP_X(id_W251), HOP2Y(1), PIP_X(id_W252) - 1., HOP2Y(1)},
+          {PIP_X(id_W252) - 1., HOP2Y(1), PIP_X(id_W252) - 1., WIRE_Y(0)}}},
+        {id_W25_loop0,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E251), HOP2Y(2)},
+          {PIP_X(id_E251), HOP2Y(2), PIP_X(id_E251), WIRE_Y(0)},
+          {PIP_X(id_E251), HOP2Y(0), PIP_X(id_E252) + 1., HOP2Y(0)},
+          {PIP_X(id_E252) + 1., HOP2Y(0), PIP_X(id_E252) + 1., WIRE_Y(0)}}},
+        {id_E25_loop1,
+         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
+          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
+          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
+          {PIP_X(id_E251) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W252) + 1., HOP2Y(1)},
+          {PIP_X(id_W252) + 1., HOP2Y(1), PIP_X(id_W252) + 1., WIRE_Y(0)}}},
+        {id_W25_loop1,
+         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
+          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
+          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
+          {PIP_X(id_W251) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E252) - 1., HOP2Y(0)},
+          {PIP_X(id_E252) - 1., HOP2Y(0), PIP_X(id_E252) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 6)
+        {id_E26,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
+          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
+          {PIP_X(id_E261) + 1., HOP2Y(0), PIP_X(id_E262) + 2., HOP2Y(0)},
+          {PIP_X(id_E262) + 2., HOP2Y(0), PIP_X(id_E262) + 2., WIRE_Y(0)}}},
+        {id_W26,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
+          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
+          {PIP_X(id_W261) - 1., HOP2Y(1), PIP_X(id_W262) - 2., HOP2Y(1)},
+          {PIP_X(id_W262) - 2., HOP2Y(1), PIP_X(id_W262) - 2., WIRE_Y(0)}}},
+        {id_E26_loop0,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W261), HOP2Y(3)},
+          {PIP_X(id_W261), HOP2Y(3), PIP_X(id_W261), WIRE_Y(0)},
+          {PIP_X(id_W261), HOP2Y(1), PIP_X(id_W262) - 1., HOP2Y(1)},
+          {PIP_X(id_W262) - 1., HOP2Y(1), PIP_X(id_W262) - 1., WIRE_Y(0)}}},
+        {id_W26_loop0,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E261), HOP2Y(2)},
+          {PIP_X(id_E261), HOP2Y(2), PIP_X(id_E261), WIRE_Y(0)},
+          {PIP_X(id_E261), HOP2Y(0), PIP_X(id_E262) + 1., HOP2Y(0)},
+          {PIP_X(id_E262) + 1., HOP2Y(0), PIP_X(id_E262) + 1., WIRE_Y(0)}}},
+        {id_E26_loop1,
+         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
+          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
+          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
+          {PIP_X(id_E261) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W262) + 1., HOP2Y(1)},
+          {PIP_X(id_W262) + 1., HOP2Y(1), PIP_X(id_W262) + 1., WIRE_Y(0)}}},
+        {id_W26_loop1,
+         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
+          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
+          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
+          {PIP_X(id_W261) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E262) - 1., HOP2Y(0)},
+          {PIP_X(id_E262) - 1., HOP2Y(0), PIP_X(id_E262) - 1., WIRE_Y(0)}}},
+
+#undef HOP2Y
+#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 7)
+        {id_E27,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
+          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
+          {PIP_X(id_E271) + 1., HOP2Y(0), PIP_X(id_E272) + 2., HOP2Y(0)},
+          {PIP_X(id_E272) + 2., HOP2Y(0), PIP_X(id_E272) + 2., WIRE_Y(0)}}},
+        {id_W27,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
+          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
+          {PIP_X(id_W271) - 1., HOP2Y(1), PIP_X(id_W272) - 2., HOP2Y(1)},
+          {PIP_X(id_W272) - 2., HOP2Y(1), PIP_X(id_W272) - 2., WIRE_Y(0)}}},
+        {id_E27_loop0,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
+          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
+          {wrap_len + 1., HOP2Y(3), PIP_X(id_W271), HOP2Y(3)},
+          {PIP_X(id_W271), HOP2Y(3), PIP_X(id_W271), WIRE_Y(0)},
+          {PIP_X(id_W271), HOP2Y(1), PIP_X(id_W272) - 1., HOP2Y(1)},
+          {PIP_X(id_W272) - 1., HOP2Y(1), PIP_X(id_W272) - 1., WIRE_Y(0)}}},
+        {id_W27_loop0,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), -wrap_len, HOP2Y(3)},
+          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
+          {-wrap_len, HOP2Y(2), PIP_X(id_E271), HOP2Y(2)},
+          {PIP_X(id_E271), HOP2Y(2), PIP_X(id_E271), WIRE_Y(0)},
+          {PIP_X(id_E271), HOP2Y(0), PIP_X(id_E272) + 1., HOP2Y(0)},
+          {PIP_X(id_E272) + 1., HOP2Y(0), PIP_X(id_E272) + 1., WIRE_Y(0)}}},
+        {id_E27_loop1,
+         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
+          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
+          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
+          {PIP_X(id_E271) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
+          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
+          {wrap_len + 2., HOP2Y(1), PIP_X(id_W272) + 1., HOP2Y(1)},
+          {PIP_X(id_W272) + 1., HOP2Y(1), PIP_X(id_W272) + 1., WIRE_Y(0)}}},
+        {id_W27_loop1,
+         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
+          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
+          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
+          {PIP_X(id_W271) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
+          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
+          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E272) - 1., HOP2Y(0)},
+          {PIP_X(id_E272) - 1., HOP2Y(0), PIP_X(id_E272) - 1., WIRE_Y(0)}}},
+
+// clock branches
+#define CLK_GBO0_Y 41.f
+#define CLK_GBO1_Y 46.f
+// 4 hop
+#define HOP4Y_START (CLK_GBO0_Y + 10.f)
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START)
+        {id_E80,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
+          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E808) + 8., HOP4Y(0)},
+          {PIP_X(id_E808) + 8, HOP4Y(0), PIP_X(id_E808) + 8., WIRE_Y(0)}}},
+        {id_W80,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
+          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W808) - 8., HOP4Y(1)},
+          {PIP_X(id_W808) - 8, HOP4Y(1), PIP_X(id_W808) - 8., WIRE_Y(0)}}},
+        {id_E80_loop0,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W800) - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - 0., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W800) - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W800) - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W800) - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W804) - 3., HOP4Y(9), PIP_X(id_W804) - 3., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W800) - 4., HOP4Y(7)},
+          {PIP_X(id_W800) - 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W800) - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W800) - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W808) - 7., HOP4Y(1)},
+          {PIP_X(id_W808) - 7, HOP4Y(1), PIP_X(id_W808) - 7., WIRE_Y(0)}}},
+        {id_E80_loop1,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W800) + 1., HOP4Y(13)},
+          {PIP_X(id_W800) + 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W800) - 0., HOP4Y(11)},
+          {PIP_X(id_W800) - 0., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W800) - 1., HOP4Y(9)},
+          {PIP_X(id_W804) - 1., HOP4Y(9), PIP_X(id_W804) - 1., WIRE_Y(0)},
+          {PIP_X(id_W800) - 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W800) - 2., HOP4Y(7)},
+          {PIP_X(id_W800) - 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W800) - 3., HOP4Y(5)},
+          {PIP_X(id_W800) - 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W800) - 4., HOP4Y(3)},
+          {PIP_X(id_W800) - 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W808) - 5., HOP4Y(1)},
+          {PIP_X(id_W808) - 5., HOP4Y(1), PIP_X(id_W808) - 5., WIRE_Y(0)}}},
+        {id_E80_loop2,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W800) + 2., HOP4Y(11)},
+          {PIP_X(id_W800) + 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W800) + 1., HOP4Y(9)},
+          {PIP_X(id_W804) + 1., HOP4Y(9), PIP_X(id_W804) + 1., WIRE_Y(0)},
+          {PIP_X(id_W800) + 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W800) + 0., HOP4Y(7)},
+          {PIP_X(id_W800) + 0., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W800) - 1., HOP4Y(5)},
+          {PIP_X(id_W800) - 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W800) - 2., HOP4Y(3)},
+          {PIP_X(id_W800) - 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W808) - 3., HOP4Y(1)},
+          {PIP_X(id_W808) - 3., HOP4Y(1), PIP_X(id_W808) - 3., WIRE_Y(0)}}},
+        {id_E80_loop3,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W800) + 3., HOP4Y(9)},
+          {PIP_X(id_W804) + 3., HOP4Y(9), PIP_X(id_W804) + 3., WIRE_Y(0)},
+          {PIP_X(id_W800) + 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W800) + 2., HOP4Y(7)},
+          {PIP_X(id_W800) + 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W800) + 1., HOP4Y(5)},
+          {PIP_X(id_W800) + 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W800) - 0., HOP4Y(3)},
+          {PIP_X(id_W800) - 0., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W808) - 1., HOP4Y(1)},
+          {PIP_X(id_W808) - 1., HOP4Y(1), PIP_X(id_W808) - 1., WIRE_Y(0)}}},
+        {id_E80_loop4,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W800) + 4., HOP4Y(7)},
+          {PIP_X(id_W800) + 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W800) + 3., HOP4Y(5)},
+          {PIP_X(id_W800) + 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W800) + 2., HOP4Y(3)},
+          {PIP_X(id_W800) + 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W808) + 1., HOP4Y(1)},
+          {PIP_X(id_W808) + 1., HOP4Y(1), PIP_X(id_W808) + 1., WIRE_Y(0)}}},
+        {id_E80_loop5,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W800) + 5., HOP4Y(5)},
+          {PIP_X(id_W800) + 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W800) + 4., HOP4Y(3)},
+          {PIP_X(id_W800) + 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W808) + 3., HOP4Y(1)},
+          {PIP_X(id_W808) + 3., HOP4Y(1), PIP_X(id_W808) + 3., WIRE_Y(0)}}},
+        {id_E80_loop6,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W800) + 6., HOP4Y(3)},
+          {PIP_X(id_W800) + 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W808) + 5., HOP4Y(1)},
+          {PIP_X(id_W808) + 5., HOP4Y(1), PIP_X(id_W808) + 5., WIRE_Y(0)}}},
+        {id_E80_loop7,
+         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
+          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
+          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
+          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
+          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
+          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
+          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
+          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
+          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
+          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W808) + 7., HOP4Y(1)},
+          {PIP_X(id_W808) + 7., HOP4Y(1), PIP_X(id_W808) + 7., WIRE_Y(0)}}},
+        {id_W80_loop0,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W808) + 0., HOP4Y(14)},
+          {PIP_X(id_W808) + 0., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W808) + 1., HOP4Y(12)},
+          {PIP_X(id_W808) + 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W808) + 2., HOP4Y(10)},
+          {PIP_X(id_W808) + 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W808) + 3., HOP4Y(8)},
+          {PIP_X(id_W808) + 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E804) + 3., HOP4Y(8), PIP_X(id_E804) + 3., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W808) + 4., HOP4Y(6)},
+          {PIP_X(id_W808) + 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W808) + 5., HOP4Y(4)},
+          {PIP_X(id_W808) + 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W808) + 6., HOP4Y(2)},
+          {PIP_X(id_W808) + 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E808) + 7., HOP4Y(0)},
+          {PIP_X(id_E808) + 7., HOP4Y(0), PIP_X(id_E808) + 7., WIRE_Y(0)}}},
+        {id_W80_loop1,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W808) - 1., HOP4Y(12)},
+          {PIP_X(id_W808) - 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W808) + 0., HOP4Y(10)},
+          {PIP_X(id_W808) + 0., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W808) + 1., HOP4Y(8)},
+          {PIP_X(id_W808) + 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E804) + 1., HOP4Y(8), PIP_X(id_E804) + 1., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W808) + 2., HOP4Y(6)},
+          {PIP_X(id_W808) + 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W808) + 3., HOP4Y(4)},
+          {PIP_X(id_W808) + 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W808) + 4., HOP4Y(2)},
+          {PIP_X(id_W808) + 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E808) + 5., HOP4Y(0)},
+          {PIP_X(id_E808) + 5., HOP4Y(0), PIP_X(id_E808) + 5., WIRE_Y(0)}}},
+        {id_W80_loop2,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W808) - 2., HOP4Y(10)},
+          {PIP_X(id_W808) - 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W808) - 1., HOP4Y(8)},
+          {PIP_X(id_W808) - 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E804) - 1., HOP4Y(8), PIP_X(id_E804) - 1., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W808) + 0., HOP4Y(6)},
+          {PIP_X(id_W808) + 0., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W808) + 1., HOP4Y(4)},
+          {PIP_X(id_W808) + 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W808) + 2., HOP4Y(2)},
+          {PIP_X(id_W808) + 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E808) + 3., HOP4Y(0)},
+          {PIP_X(id_E808) + 3., HOP4Y(0), PIP_X(id_E808) + 3., WIRE_Y(0)}}},
+        {id_W80_loop3,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W808) - 3., HOP4Y(8)},
+          {PIP_X(id_W808) - 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E804) - 3., HOP4Y(8), PIP_X(id_E804) - 3., WIRE_Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W808) - 2., HOP4Y(6)},
+          {PIP_X(id_W808) - 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W808) - 1., HOP4Y(4)},
+          {PIP_X(id_W808) - 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W808) + 0., HOP4Y(2)},
+          {PIP_X(id_W808) + 0., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E808) + 1., HOP4Y(0)},
+          {PIP_X(id_E808) + 1., HOP4Y(0), PIP_X(id_E808) + 1., WIRE_Y(0)}}},
+        {id_W80_loop4,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W804) - 4., HOP4Y(6), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W808) - 4., HOP4Y(6)},
+          {PIP_X(id_W808) - 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W808) - 3., HOP4Y(4)},
+          {PIP_X(id_W808) - 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W808) - 2., HOP4Y(2)},
+          {PIP_X(id_W808) - 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E808) - 1., HOP4Y(0)},
+          {PIP_X(id_E808) - 1., HOP4Y(0), PIP_X(id_E808) - 1., WIRE_Y(0)}}},
+        {id_W80_loop5,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W808) - 5., HOP4Y(4)},
+          {PIP_X(id_W808) - 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W808) - 4., HOP4Y(2)},
+          {PIP_X(id_W808) - 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E808) - 3., HOP4Y(0)},
+          {PIP_X(id_E808) - 3., HOP4Y(0), PIP_X(id_E808) - 3., WIRE_Y(0)}}},
+        {id_W80_loop6,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W808) - 6., HOP4Y(2)},
+          {PIP_X(id_W808) - 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E808) - 5., HOP4Y(0)},
+          {PIP_X(id_E808) - 5., HOP4Y(0), PIP_X(id_E808) - 5., WIRE_Y(0)}}},
+        {id_W80_loop7,
+         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
+          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
+          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
+          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
+          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
+          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
+          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
+          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
+          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
+          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E808) - 7., HOP4Y(0)},
+          {PIP_X(id_E808) - 7., HOP4Y(0), PIP_X(id_E808) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f)
+        {id_E81,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
+          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E818) + 8., HOP4Y(0)},
+          {PIP_X(id_E818) + 8, HOP4Y(0), PIP_X(id_E818) + 8., WIRE_Y(0)}}},
+        {id_W81,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
+          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W818) - 8., HOP4Y(1)},
+          {PIP_X(id_W818) - 8, HOP4Y(1), PIP_X(id_W818) - 8., WIRE_Y(0)}}},
+        {id_E81_loop0,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W810) - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - 0., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W810) - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W810) - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W810) - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W814) - 3., HOP4Y(9), PIP_X(id_W814) - 3., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W810) - 4., HOP4Y(7)},
+          {PIP_X(id_W810) - 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W810) - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W810) - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W818) - 7., HOP4Y(1)},
+          {PIP_X(id_W818) - 7, HOP4Y(1), PIP_X(id_W818) - 7., WIRE_Y(0)}}},
+        {id_E81_loop1,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W810) + 1., HOP4Y(13)},
+          {PIP_X(id_W810) + 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W810) - 0., HOP4Y(11)},
+          {PIP_X(id_W810) - 0., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W810) - 1., HOP4Y(9)},
+          {PIP_X(id_W814) - 1., HOP4Y(9), PIP_X(id_W814) - 1., WIRE_Y(0)},
+          {PIP_X(id_W810) - 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W810) - 2., HOP4Y(7)},
+          {PIP_X(id_W810) - 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W810) - 3., HOP4Y(5)},
+          {PIP_X(id_W810) - 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W810) - 4., HOP4Y(3)},
+          {PIP_X(id_W810) - 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W818) - 5., HOP4Y(1)},
+          {PIP_X(id_W818) - 5., HOP4Y(1), PIP_X(id_W818) - 5., WIRE_Y(0)}}},
+        {id_E81_loop2,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W810) + 2., HOP4Y(11)},
+          {PIP_X(id_W810) + 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W810) + 1., HOP4Y(9)},
+          {PIP_X(id_W814) + 1., HOP4Y(9), PIP_X(id_W814) + 1., WIRE_Y(0)},
+          {PIP_X(id_W810) + 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W810) + 0., HOP4Y(7)},
+          {PIP_X(id_W810) + 0., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W810) - 1., HOP4Y(5)},
+          {PIP_X(id_W810) - 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W810) - 2., HOP4Y(3)},
+          {PIP_X(id_W810) - 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W818) - 3., HOP4Y(1)},
+          {PIP_X(id_W818) - 3., HOP4Y(1), PIP_X(id_W818) - 3., WIRE_Y(0)}}},
+        {id_E81_loop3,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W810) + 3., HOP4Y(9)},
+          {PIP_X(id_W814) + 3., HOP4Y(9), PIP_X(id_W814) + 3., WIRE_Y(0)},
+          {PIP_X(id_W810) + 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W810) + 2., HOP4Y(7)},
+          {PIP_X(id_W810) + 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W810) + 1., HOP4Y(5)},
+          {PIP_X(id_W810) + 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W810) - 0., HOP4Y(3)},
+          {PIP_X(id_W810) - 0., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W818) - 1., HOP4Y(1)},
+          {PIP_X(id_W818) - 1., HOP4Y(1), PIP_X(id_W818) - 1., WIRE_Y(0)}}},
+        {id_E81_loop4,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W810) + 4., HOP4Y(7)},
+          {PIP_X(id_W810) + 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W810) + 3., HOP4Y(5)},
+          {PIP_X(id_W810) + 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W810) + 2., HOP4Y(3)},
+          {PIP_X(id_W810) + 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W818) + 1., HOP4Y(1)},
+          {PIP_X(id_W818) + 1., HOP4Y(1), PIP_X(id_W818) + 1., WIRE_Y(0)}}},
+        {id_E81_loop5,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W810) + 5., HOP4Y(5)},
+          {PIP_X(id_W810) + 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W810) + 4., HOP4Y(3)},
+          {PIP_X(id_W810) + 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W818) + 3., HOP4Y(1)},
+          {PIP_X(id_W818) + 3., HOP4Y(1), PIP_X(id_W818) + 3., WIRE_Y(0)}}},
+        {id_E81_loop6,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W810) + 6., HOP4Y(3)},
+          {PIP_X(id_W810) + 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W818) + 5., HOP4Y(1)},
+          {PIP_X(id_W818) + 5., HOP4Y(1), PIP_X(id_W818) + 5., WIRE_Y(0)}}},
+        {id_E81_loop7,
+         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
+          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
+          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
+          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
+          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
+          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
+          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
+          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
+          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
+          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W818) + 7., HOP4Y(1)},
+          {PIP_X(id_W818) + 7., HOP4Y(1), PIP_X(id_W818) + 7., WIRE_Y(0)}}},
+        {id_W81_loop0,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W818) + 0., HOP4Y(14)},
+          {PIP_X(id_W818) + 0., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W818) + 1., HOP4Y(12)},
+          {PIP_X(id_W818) + 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W818) + 2., HOP4Y(10)},
+          {PIP_X(id_W818) + 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W818) + 3., HOP4Y(8)},
+          {PIP_X(id_W818) + 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E814) + 3., HOP4Y(8), PIP_X(id_E814) + 3., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W818) + 4., HOP4Y(6)},
+          {PIP_X(id_W818) + 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W818) + 5., HOP4Y(4)},
+          {PIP_X(id_W818) + 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W818) + 6., HOP4Y(2)},
+          {PIP_X(id_W818) + 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E818) + 7., HOP4Y(0)},
+          {PIP_X(id_E818) + 7., HOP4Y(0), PIP_X(id_E818) + 7., WIRE_Y(0)}}},
+        {id_W81_loop1,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W818) - 1., HOP4Y(12)},
+          {PIP_X(id_W818) - 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W818) + 0., HOP4Y(10)},
+          {PIP_X(id_W818) + 0., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W818) + 1., HOP4Y(8)},
+          {PIP_X(id_W818) + 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E814) + 1., HOP4Y(8), PIP_X(id_E814) + 1., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W818) + 2., HOP4Y(6)},
+          {PIP_X(id_W818) + 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W818) + 3., HOP4Y(4)},
+          {PIP_X(id_W818) + 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W818) + 4., HOP4Y(2)},
+          {PIP_X(id_W818) + 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E818) + 5., HOP4Y(0)},
+          {PIP_X(id_E818) + 5., HOP4Y(0), PIP_X(id_E818) + 5., WIRE_Y(0)}}},
+        {id_W81_loop2,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W818) - 2., HOP4Y(10)},
+          {PIP_X(id_W818) - 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W818) - 1., HOP4Y(8)},
+          {PIP_X(id_W818) - 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E814) - 1., HOP4Y(8), PIP_X(id_E814) - 1., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W818) + 0., HOP4Y(6)},
+          {PIP_X(id_W818) + 0., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W818) + 1., HOP4Y(4)},
+          {PIP_X(id_W818) + 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W818) + 2., HOP4Y(2)},
+          {PIP_X(id_W818) + 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E818) + 3., HOP4Y(0)},
+          {PIP_X(id_E818) + 3., HOP4Y(0), PIP_X(id_E818) + 3., WIRE_Y(0)}}},
+        {id_W81_loop3,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W818) - 3., HOP4Y(8)},
+          {PIP_X(id_W818) - 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E814) - 3., HOP4Y(8), PIP_X(id_E814) - 3., WIRE_Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W818) - 2., HOP4Y(6)},
+          {PIP_X(id_W818) - 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W818) - 1., HOP4Y(4)},
+          {PIP_X(id_W818) - 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W818) + 0., HOP4Y(2)},
+          {PIP_X(id_W818) + 0., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E818) + 1., HOP4Y(0)},
+          {PIP_X(id_E818) + 1., HOP4Y(0), PIP_X(id_E818) + 1., WIRE_Y(0)}}},
+        {id_W81_loop4,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W814) - 4., HOP4Y(6), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W818) - 4., HOP4Y(6)},
+          {PIP_X(id_W818) - 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W818) - 3., HOP4Y(4)},
+          {PIP_X(id_W818) - 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W818) - 2., HOP4Y(2)},
+          {PIP_X(id_W818) - 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E818) - 1., HOP4Y(0)},
+          {PIP_X(id_E818) - 1., HOP4Y(0), PIP_X(id_E818) - 1., WIRE_Y(0)}}},
+        {id_W81_loop5,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W818) - 5., HOP4Y(4)},
+          {PIP_X(id_W818) - 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W818) - 4., HOP4Y(2)},
+          {PIP_X(id_W818) - 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E818) - 3., HOP4Y(0)},
+          {PIP_X(id_E818) - 3., HOP4Y(0), PIP_X(id_E818) - 3., WIRE_Y(0)}}},
+        {id_W81_loop6,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W818) - 6., HOP4Y(2)},
+          {PIP_X(id_W818) - 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E818) - 5., HOP4Y(0)},
+          {PIP_X(id_E818) - 5., HOP4Y(0), PIP_X(id_E818) - 5., WIRE_Y(0)}}},
+        {id_W81_loop7,
+         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
+          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
+          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
+          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
+          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
+          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
+          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
+          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
+          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
+          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E818) - 7., HOP4Y(0)},
+          {PIP_X(id_E818) - 7., HOP4Y(0), PIP_X(id_E818) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f)
+        {id_E82,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
+          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E828) + 8., HOP4Y(0)},
+          {PIP_X(id_E828) + 8, HOP4Y(0), PIP_X(id_E828) + 8., WIRE_Y(0)}}},
+        {id_W82,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
+          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W828) - 8., HOP4Y(1)},
+          {PIP_X(id_W828) - 8, HOP4Y(1), PIP_X(id_W828) - 8., WIRE_Y(0)}}},
+        {id_E82_loop0,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W820) - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - 0., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W820) - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W820) - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W820) - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W824) - 3., HOP4Y(9), PIP_X(id_W824) - 3., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W820) - 4., HOP4Y(7)},
+          {PIP_X(id_W820) - 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W820) - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W820) - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W828) - 7., HOP4Y(1)},
+          {PIP_X(id_W828) - 7, HOP4Y(1), PIP_X(id_W828) - 7., WIRE_Y(0)}}},
+        {id_E82_loop1,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W820) + 1., HOP4Y(13)},
+          {PIP_X(id_W820) + 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W820) - 0., HOP4Y(11)},
+          {PIP_X(id_W820) - 0., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W820) - 1., HOP4Y(9)},
+          {PIP_X(id_W824) - 1., HOP4Y(9), PIP_X(id_W824) - 1., WIRE_Y(0)},
+          {PIP_X(id_W820) - 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W820) - 2., HOP4Y(7)},
+          {PIP_X(id_W820) - 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W820) - 3., HOP4Y(5)},
+          {PIP_X(id_W820) - 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W820) - 4., HOP4Y(3)},
+          {PIP_X(id_W820) - 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W828) - 5., HOP4Y(1)},
+          {PIP_X(id_W828) - 5., HOP4Y(1), PIP_X(id_W828) - 5., WIRE_Y(0)}}},
+        {id_E82_loop2,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W820) + 2., HOP4Y(11)},
+          {PIP_X(id_W820) + 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W820) + 1., HOP4Y(9)},
+          {PIP_X(id_W824) + 1., HOP4Y(9), PIP_X(id_W824) + 1., WIRE_Y(0)},
+          {PIP_X(id_W820) + 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W820) + 0., HOP4Y(7)},
+          {PIP_X(id_W820) + 0., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W820) - 1., HOP4Y(5)},
+          {PIP_X(id_W820) - 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W820) - 2., HOP4Y(3)},
+          {PIP_X(id_W820) - 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W828) - 3., HOP4Y(1)},
+          {PIP_X(id_W828) - 3., HOP4Y(1), PIP_X(id_W828) - 3., WIRE_Y(0)}}},
+        {id_E82_loop3,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W820) + 3., HOP4Y(9)},
+          {PIP_X(id_W824) + 3., HOP4Y(9), PIP_X(id_W824) + 3., WIRE_Y(0)},
+          {PIP_X(id_W820) + 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W820) + 2., HOP4Y(7)},
+          {PIP_X(id_W820) + 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W820) + 1., HOP4Y(5)},
+          {PIP_X(id_W820) + 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W820) - 0., HOP4Y(3)},
+          {PIP_X(id_W820) - 0., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W828) - 1., HOP4Y(1)},
+          {PIP_X(id_W828) - 1., HOP4Y(1), PIP_X(id_W828) - 1., WIRE_Y(0)}}},
+        {id_E82_loop4,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W820) + 4., HOP4Y(7)},
+          {PIP_X(id_W820) + 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W820) + 3., HOP4Y(5)},
+          {PIP_X(id_W820) + 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W820) + 2., HOP4Y(3)},
+          {PIP_X(id_W820) + 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W828) + 1., HOP4Y(1)},
+          {PIP_X(id_W828) + 1., HOP4Y(1), PIP_X(id_W828) + 1., WIRE_Y(0)}}},
+        {id_E82_loop5,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W820) + 5., HOP4Y(5)},
+          {PIP_X(id_W820) + 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W820) + 4., HOP4Y(3)},
+          {PIP_X(id_W820) + 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W828) + 3., HOP4Y(1)},
+          {PIP_X(id_W828) + 3., HOP4Y(1), PIP_X(id_W828) + 3., WIRE_Y(0)}}},
+        {id_E82_loop6,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W820) + 6., HOP4Y(3)},
+          {PIP_X(id_W820) + 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W828) + 5., HOP4Y(1)},
+          {PIP_X(id_W828) + 5., HOP4Y(1), PIP_X(id_W828) + 5., WIRE_Y(0)}}},
+        {id_E82_loop7,
+         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
+          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
+          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
+          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
+          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
+          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
+          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
+          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
+          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
+          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W828) + 7., HOP4Y(1)},
+          {PIP_X(id_W828) + 7., HOP4Y(1), PIP_X(id_W828) + 7., WIRE_Y(0)}}},
+        {id_W82_loop0,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W828) + 0., HOP4Y(14)},
+          {PIP_X(id_W828) + 0., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W828) + 1., HOP4Y(12)},
+          {PIP_X(id_W828) + 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W828) + 2., HOP4Y(10)},
+          {PIP_X(id_W828) + 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W828) + 3., HOP4Y(8)},
+          {PIP_X(id_W828) + 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E824) + 3., HOP4Y(8), PIP_X(id_E824) + 3., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W828) + 4., HOP4Y(6)},
+          {PIP_X(id_W828) + 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W828) + 5., HOP4Y(4)},
+          {PIP_X(id_W828) + 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W828) + 6., HOP4Y(2)},
+          {PIP_X(id_W828) + 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E828) + 7., HOP4Y(0)},
+          {PIP_X(id_E828) + 7., HOP4Y(0), PIP_X(id_E828) + 7., WIRE_Y(0)}}},
+        {id_W82_loop1,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W828) - 1., HOP4Y(12)},
+          {PIP_X(id_W828) - 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W828) + 0., HOP4Y(10)},
+          {PIP_X(id_W828) + 0., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W828) + 1., HOP4Y(8)},
+          {PIP_X(id_W828) + 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E824) + 1., HOP4Y(8), PIP_X(id_E824) + 1., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W828) + 2., HOP4Y(6)},
+          {PIP_X(id_W828) + 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W828) + 3., HOP4Y(4)},
+          {PIP_X(id_W828) + 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W828) + 4., HOP4Y(2)},
+          {PIP_X(id_W828) + 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E828) + 5., HOP4Y(0)},
+          {PIP_X(id_E828) + 5., HOP4Y(0), PIP_X(id_E828) + 5., WIRE_Y(0)}}},
+        {id_W82_loop2,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W828) - 2., HOP4Y(10)},
+          {PIP_X(id_W828) - 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W828) - 1., HOP4Y(8)},
+          {PIP_X(id_W828) - 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E824) - 1., HOP4Y(8), PIP_X(id_E824) - 1., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W828) + 0., HOP4Y(6)},
+          {PIP_X(id_W828) + 0., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W828) + 1., HOP4Y(4)},
+          {PIP_X(id_W828) + 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W828) + 2., HOP4Y(2)},
+          {PIP_X(id_W828) + 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E828) + 3., HOP4Y(0)},
+          {PIP_X(id_E828) + 3., HOP4Y(0), PIP_X(id_E828) + 3., WIRE_Y(0)}}},
+        {id_W82_loop3,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W828) - 3., HOP4Y(8)},
+          {PIP_X(id_W828) - 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E824) - 3., HOP4Y(8), PIP_X(id_E824) - 3., WIRE_Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W828) - 2., HOP4Y(6)},
+          {PIP_X(id_W828) - 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W828) - 1., HOP4Y(4)},
+          {PIP_X(id_W828) - 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W828) + 0., HOP4Y(2)},
+          {PIP_X(id_W828) + 0., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E828) + 1., HOP4Y(0)},
+          {PIP_X(id_E828) + 1., HOP4Y(0), PIP_X(id_E828) + 1., WIRE_Y(0)}}},
+        {id_W82_loop4,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W824) - 4., HOP4Y(6), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W828) - 4., HOP4Y(6)},
+          {PIP_X(id_W828) - 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W828) - 3., HOP4Y(4)},
+          {PIP_X(id_W828) - 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W828) - 2., HOP4Y(2)},
+          {PIP_X(id_W828) - 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E828) - 1., HOP4Y(0)},
+          {PIP_X(id_E828) - 1., HOP4Y(0), PIP_X(id_E828) - 1., WIRE_Y(0)}}},
+        {id_W82_loop5,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W828) - 5., HOP4Y(4)},
+          {PIP_X(id_W828) - 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W828) - 4., HOP4Y(2)},
+          {PIP_X(id_W828) - 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E828) - 3., HOP4Y(0)},
+          {PIP_X(id_E828) - 3., HOP4Y(0), PIP_X(id_E828) - 3., WIRE_Y(0)}}},
+        {id_W82_loop6,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W828) - 6., HOP4Y(2)},
+          {PIP_X(id_W828) - 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E828) - 5., HOP4Y(0)},
+          {PIP_X(id_E828) - 5., HOP4Y(0), PIP_X(id_E828) - 5., WIRE_Y(0)}}},
+        {id_W82_loop7,
+         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
+          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
+          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
+          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
+          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
+          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
+          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
+          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
+          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
+          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E828) - 7., HOP4Y(0)},
+          {PIP_X(id_E828) - 7., HOP4Y(0), PIP_X(id_E828) - 7., WIRE_Y(0)}}},
+
+#undef HOP4Y
+#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f + 18.f)
+        {id_E83,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
+          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E838) + 8., HOP4Y(0)},
+          {PIP_X(id_E838) + 8, HOP4Y(0), PIP_X(id_E838) + 8., WIRE_Y(0)}}},
+        {id_W83,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
+          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W838) - 8., HOP4Y(1)},
+          {PIP_X(id_W838) - 8, HOP4Y(1), PIP_X(id_W838) - 8., WIRE_Y(0)}}},
+        {id_E83_loop0,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
+          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
+          {wrap_len + 1., HOP4Y(15), PIP_X(id_W830) - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - 0., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W830) - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W830) - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W830) - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7)},
+          {PIP_X(id_W834) - 3., HOP4Y(9), PIP_X(id_W834) - 3., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W830) - 4., HOP4Y(7)},
+          {PIP_X(id_W830) - 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W830) - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W830) - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W838) - 7., HOP4Y(1)},
+          {PIP_X(id_W838) - 7, HOP4Y(1), PIP_X(id_W838) - 7., WIRE_Y(0)}}},
+        {id_E83_loop1,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
+          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
+          {wrap_len + 2., HOP4Y(13), PIP_X(id_W830) + 1., HOP4Y(13)},
+          {PIP_X(id_W830) + 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W830) - 0., HOP4Y(11)},
+          {PIP_X(id_W830) - 0., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W830) - 1., HOP4Y(9)},
+          {PIP_X(id_W834) - 1., HOP4Y(9), PIP_X(id_W834) - 1., WIRE_Y(0)},
+          {PIP_X(id_W830) - 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W830) - 2., HOP4Y(7)},
+          {PIP_X(id_W830) - 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W830) - 3., HOP4Y(5)},
+          {PIP_X(id_W830) - 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W830) - 4., HOP4Y(3)},
+          {PIP_X(id_W830) - 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W838) - 5., HOP4Y(1)},
+          {PIP_X(id_W838) - 5., HOP4Y(1), PIP_X(id_W838) - 5., WIRE_Y(0)}}},
+        {id_E83_loop2,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
+          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
+          {wrap_len + 3., HOP4Y(11), PIP_X(id_W830) + 2., HOP4Y(11)},
+          {PIP_X(id_W830) + 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W830) + 1., HOP4Y(9)},
+          {PIP_X(id_W834) + 1., HOP4Y(9), PIP_X(id_W834) + 1., WIRE_Y(0)},
+          {PIP_X(id_W830) + 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W830) + 0., HOP4Y(7)},
+          {PIP_X(id_W830) + 0., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W830) - 1., HOP4Y(5)},
+          {PIP_X(id_W830) - 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W830) - 2., HOP4Y(3)},
+          {PIP_X(id_W830) - 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W838) - 3., HOP4Y(1)},
+          {PIP_X(id_W838) - 3., HOP4Y(1), PIP_X(id_W838) - 3., WIRE_Y(0)}}},
+        {id_E83_loop3,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
+          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
+          {wrap_len + 4., HOP4Y(9), PIP_X(id_W830) + 3., HOP4Y(9)},
+          {PIP_X(id_W834) + 3., HOP4Y(9), PIP_X(id_W834) + 3., WIRE_Y(0)},
+          {PIP_X(id_W830) + 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W830) + 2., HOP4Y(7)},
+          {PIP_X(id_W830) + 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W830) + 1., HOP4Y(5)},
+          {PIP_X(id_W830) + 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W830) - 0., HOP4Y(3)},
+          {PIP_X(id_W830) - 0., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W838) - 1., HOP4Y(1)},
+          {PIP_X(id_W838) - 1., HOP4Y(1), PIP_X(id_W838) - 1., WIRE_Y(0)}}},
+        {id_E83_loop4,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
+          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
+          {wrap_len + 5., HOP4Y(7), PIP_X(id_W830) + 4., HOP4Y(7)},
+          {PIP_X(id_W830) + 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W830) + 3., HOP4Y(5)},
+          {PIP_X(id_W830) + 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W830) + 2., HOP4Y(3)},
+          {PIP_X(id_W830) + 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W838) + 1., HOP4Y(1)},
+          {PIP_X(id_W838) + 1., HOP4Y(1), PIP_X(id_W838) + 1., WIRE_Y(0)}}},
+        {id_E83_loop5,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
+          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
+          {wrap_len + 6., HOP4Y(5), PIP_X(id_W830) + 5., HOP4Y(5)},
+          {PIP_X(id_W830) + 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W830) + 4., HOP4Y(3)},
+          {PIP_X(id_W830) + 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W838) + 3., HOP4Y(1)},
+          {PIP_X(id_W838) + 3., HOP4Y(1), PIP_X(id_W838) + 3., WIRE_Y(0)}}},
+        {id_E83_loop6,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
+          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
+          {wrap_len + 7., HOP4Y(3), PIP_X(id_W830) + 6., HOP4Y(3)},
+          {PIP_X(id_W830) + 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W838) + 5., HOP4Y(1)},
+          {PIP_X(id_W838) + 5., HOP4Y(1), PIP_X(id_W838) + 5., WIRE_Y(0)}}},
+        {id_E83_loop7,
+         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
+          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
+          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
+          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
+          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
+          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
+          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
+          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
+          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
+          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
+          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
+          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
+          {wrap_len + 8., HOP4Y(1), PIP_X(id_W838) + 7., HOP4Y(1)},
+          {PIP_X(id_W838) + 7., HOP4Y(1), PIP_X(id_W838) + 7., WIRE_Y(0)}}},
+        {id_W83_loop0,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
+          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
+          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W838) + 0., HOP4Y(14)},
+          {PIP_X(id_W838) + 0., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W838) + 1., HOP4Y(12)},
+          {PIP_X(id_W838) + 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W838) + 2., HOP4Y(10)},
+          {PIP_X(id_W838) + 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W838) + 3., HOP4Y(8)},
+          {PIP_X(id_W838) + 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6)},
+          {PIP_X(id_E834) + 3., HOP4Y(8), PIP_X(id_E834) + 3., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W838) + 4., HOP4Y(6)},
+          {PIP_X(id_W838) + 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W838) + 5., HOP4Y(4)},
+          {PIP_X(id_W838) + 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W838) + 6., HOP4Y(2)},
+          {PIP_X(id_W838) + 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E838) + 7., HOP4Y(0)},
+          {PIP_X(id_E838) + 7., HOP4Y(0), PIP_X(id_E838) + 7., WIRE_Y(0)}}},
+        {id_W83_loop1,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
+          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
+          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W838) - 1., HOP4Y(12)},
+          {PIP_X(id_W838) - 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W838) + 0., HOP4Y(10)},
+          {PIP_X(id_W838) + 0., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W838) + 1., HOP4Y(8)},
+          {PIP_X(id_W838) + 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6)},
+          {PIP_X(id_E834) + 1., HOP4Y(8), PIP_X(id_E834) + 1., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W838) + 2., HOP4Y(6)},
+          {PIP_X(id_W838) + 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W838) + 3., HOP4Y(4)},
+          {PIP_X(id_W838) + 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W838) + 4., HOP4Y(2)},
+          {PIP_X(id_W838) + 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E838) + 5., HOP4Y(0)},
+          {PIP_X(id_E838) + 5., HOP4Y(0), PIP_X(id_E838) + 5., WIRE_Y(0)}}},
+        {id_W83_loop2,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
+          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
+          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W838) - 2., HOP4Y(10)},
+          {PIP_X(id_W838) - 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W838) - 1., HOP4Y(8)},
+          {PIP_X(id_W838) - 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6)},
+          {PIP_X(id_E834) - 1., HOP4Y(8), PIP_X(id_E834) - 1., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W838) + 0., HOP4Y(6)},
+          {PIP_X(id_W838) + 0., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W838) + 1., HOP4Y(4)},
+          {PIP_X(id_W838) + 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W838) + 2., HOP4Y(2)},
+          {PIP_X(id_W838) + 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E838) + 3., HOP4Y(0)},
+          {PIP_X(id_E838) + 3., HOP4Y(0), PIP_X(id_E838) + 3., WIRE_Y(0)}}},
+        {id_W83_loop3,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
+          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
+          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W838) - 3., HOP4Y(8)},
+          {PIP_X(id_W838) - 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6)},
+          {PIP_X(id_E834) - 3., HOP4Y(8), PIP_X(id_E834) - 3., WIRE_Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W838) - 2., HOP4Y(6)},
+          {PIP_X(id_W838) - 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W838) - 1., HOP4Y(4)},
+          {PIP_X(id_W838) - 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W838) + 0., HOP4Y(2)},
+          {PIP_X(id_W838) + 0., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E838) + 1., HOP4Y(0)},
+          {PIP_X(id_E838) + 1., HOP4Y(0), PIP_X(id_E838) + 1., WIRE_Y(0)}}},
+        {id_W83_loop4,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
+          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
+          {PIP_X(id_W834) - 4., HOP4Y(6), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W838) - 4., HOP4Y(6)},
+          {PIP_X(id_W838) - 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4)},
+          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W838) - 3., HOP4Y(4)},
+          {PIP_X(id_W838) - 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W838) - 2., HOP4Y(2)},
+          {PIP_X(id_W838) - 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E838) - 1., HOP4Y(0)},
+          {PIP_X(id_E838) - 1., HOP4Y(0), PIP_X(id_E838) - 1., WIRE_Y(0)}}},
+        {id_W83_loop5,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
+          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
+          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W838) - 5., HOP4Y(4)},
+          {PIP_X(id_W838) - 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2)},
+          {PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W838) - 4., HOP4Y(2)},
+          {PIP_X(id_W838) - 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E838) - 3., HOP4Y(0)},
+          {PIP_X(id_E838) - 3., HOP4Y(0), PIP_X(id_E838) - 3., WIRE_Y(0)}}},
+        {id_W83_loop6,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
+          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
+          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W838) - 6., HOP4Y(2)},
+          {PIP_X(id_W838) - 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0)},
+          {PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E838) - 5., HOP4Y(0)},
+          {PIP_X(id_E838) - 5., HOP4Y(0), PIP_X(id_E838) - 5., WIRE_Y(0)}}},
+        {id_W83_loop7,
+         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
+          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
+          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
+          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
+          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
+          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
+          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
+          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
+          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
+          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
+          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
+          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
+          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
+          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
+          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
+          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
+          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
+          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
+          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
+          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E838) - 7., HOP4Y(0)},
+          {PIP_X(id_E838) - 7., HOP4Y(0), PIP_X(id_E838) - 7., WIRE_Y(0)}}},
+};
 const int PIP_SRC_DST_LEN = 20;
 
 static void get_pip_xy(CruSide side, float &off, float &x, float &y)
diff --git a/gowin/gfx.h b/gowin/gfx.h
index 574d73106a..b5ea4678ac 100644
--- a/gowin/gfx.h
+++ b/gowin/gfx.h
@@ -24,4902 +24,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-// LUTs
-const float lut_w = 0.6732 - 0.6386;
-const float lut_h = 0.9392 - 0.9074;
-const float lut_x = 0.6386;
-const float lut_y[] = {1. - 0.9392, 1. - 0.8870, 1. - 0.7864, 1. - 0.7321,
-                       1. - 0.6399, 1. - 0.5847, 1. - 0.5068, 1. - 0.4503};
-const float dff_w = 0.0580;
-const float dff_x = 0.6821;
-const float grp_lut_w = 0.1399;
-const float grp_lut_h = 0.0954;
-const float grp_lut_x = 0.6284;
-const float grp_lut_y[] = {1. - 0.9440, 1. - 0.7915, 1. - 0.6442, 1. - 0.5101};
-
-// mux
-const float mux_w = 0.8134 - 0.7899;
-const float mux_f = 0.9450 - 0.9358;
-const float mux_h = grp_lut_h;
-
-const float mux2lut5_x = 0.7900;
-const float mux2lut5_y[] = {grp_lut_y[0], grp_lut_y[1], grp_lut_y[2], grp_lut_y[3]};
-const float mux2lut6_x = 0.8378;
-const float mux2lut6_y[] = {1. - 0.9261, 1. - 0.6205};
-const float mux2lut7_x = 0.8859;
-const float mux2lut7_y = 1. - 0.7870;
-const float mux2lut8_x = 0.9337;
-const float mux2lut8_y = 1. - 0.8098;
-
-// pip
-enum CruSide
-{
-    Top,
-    Bottom,
-    Left,
-    Right,
-    Center
-};
-const float cru_x = 0.2568;
-const float cru_y = 1. - 0.9783;
-const float cru_w = 0.6010 - cru_x;
-const float cru_h = 1. - cru_y - 0.3742;
-
-const float lut_A_off = 1. - 0.9107 - lut_y[0];
-const float lut_D_off = lut_h - lut_A_off;
-const float lut_B_off = lut_A_off - (lut_h - lut_D_off) / 3.;
-const float lut_C_off = lut_D_off + (lut_h - lut_D_off) / 3.;
-
-const float right_wire_dist = (grp_lut_y[1] - grp_lut_y[0] - grp_lut_h) / 11.;
-const float left_wire_dist = cru_h / 100.;
-const float top_wire_dist = cru_w / 100.;
-const float clk_ce_set_vdist = (lut_y[1] - lut_y[0] - lut_h) / 4.;
-
-const float sn_dist = cru_x / 125.;
-const float ew_dist = (1. - cru_y - cru_h) / 130.;
-const float wrap_len = 0.02f;
-const float spine_pip_off = 0.11f;
-
-const float io_x = cru_x + cru_w + 0.1;
-const float io_w = (1. - io_x) / 3.;
-const float io_gap = 0.03;
-const float io_h = (cru_h - 4. * io_gap) / 2.;
-const float io_y = cru_y + io_gap;
-
-const float ios_scl = 0.5;
-const float ios_h = ios_scl * io_h;
-const float ios_w = ios_scl * io_w;
-const float ios_gap_y = io_gap;
-const float ios_gap_x = io_gap * 1.4;
-const float ios_x = io_x;
-const float ios_y = ios_scl * io_y;
-
-const dict<IdString, float> portPoint = {
-        {id_O, 3. * io_h / 4.},
-        {id_I, 2. * io_h / 4.},
-        {id_OEN, 1. * io_h / 4.},
-};
-
-const dict<IdString, std::vector<std::tuple<float, float, float, float>>> portSign = {
-        {id_O,
-         {{io_h / 14. * 1.33, portPoint.at(id_O) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14.},
-          {io_h / 14. * 1.66, portPoint.at(id_O) + io_h / 14., io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6},
-          {io_h / 14. * 2., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 2.,
-           portPoint.at(id_O) - io_h / 14. * 0.6},
-          {io_h / 14. * 2., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14.},
-          {io_h / 14. * 1.66, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14.},
-          {io_h / 14. * 1.33, portPoint.at(id_O) - io_h / 14., io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6},
-          {io_h / 14. * 1., portPoint.at(id_O) - io_h / 14. * 0.6, io_h / 14. * 1.,
-           portPoint.at(id_O) + io_h / 14. * 0.6},
-          {io_h / 14. * 1., portPoint.at(id_O) + io_h / 14. * 0.6, io_h / 14. * 1.33,
-           portPoint.at(id_O) + io_h / 14.}}},
-        {id_I,
-         {{io_h / 14., portPoint.at(id_I) + io_h / 14., 2. * io_h / 14., portPoint.at(id_I) + io_h / 14.},
-          {io_h / 14. * 1.5, portPoint.at(id_I) + io_h / 14., 1. * io_h / 14. * 1.5, portPoint.at(id_I) - io_h / 14.},
-          {io_h / 14., portPoint.at(id_I) - io_h / 14., 2. * io_h / 14., portPoint.at(id_I) - io_h / 14.}}},
-        {id_OEN,
-         {{io_h / 14. * 1.33, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14.},
-          {io_h / 14. * 1.66, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.,
-           portPoint.at(id_OEN) + io_h / 14. * 0.6},
-          {io_h / 14. * 2., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 2.,
-           portPoint.at(id_OEN) - io_h / 14. * 0.6},
-          {io_h / 14. * 2., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.66,
-           portPoint.at(id_OEN) - io_h / 14.},
-          {io_h / 14. * 1.66, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14.},
-          {io_h / 14. * 1.33, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 1.,
-           portPoint.at(id_OEN) - io_h / 14. * 0.6},
-          {io_h / 14. * 1., portPoint.at(id_OEN) - io_h / 14. * 0.6, io_h / 14. * 1.,
-           portPoint.at(id_OEN) + io_h / 14. * 0.6},
-          {io_h / 14. * 1., portPoint.at(id_OEN) + io_h / 14. * 0.6, io_h / 14. * 1.33,
-           portPoint.at(id_OEN) + io_h / 14.},
-          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) + io_h / 14.},
-          {io_h / 14. * 2.2, portPoint.at(id_OEN) + 0., io_h / 14. * 3.2, portPoint.at(id_OEN) + 0.},
-          {io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14., io_h / 14. * 3.2, portPoint.at(id_OEN) - io_h / 14.},
-          {io_h / 14. * 2.2, portPoint.at(id_OEN) + io_h / 14., io_h / 14. * 2.2, portPoint.at(id_OEN) - io_h / 14.}}},
-};
-
-const dict<IdString, float> spineY = {
-        {id_SPINE0, 1. - 1. * ew_dist},  {id_SPINE1, 1. - 2. * ew_dist},  {id_SPINE2, 1. - 3. * ew_dist},
-        {id_SPINE3, 1. - 4. * ew_dist},  {id_SPINE4, 1. - 5. * ew_dist},  {id_SPINE5, 1. - 6. * ew_dist},
-        {id_SPINE6, 1. - 7. * ew_dist},  {id_SPINE7, 1. - 8. * ew_dist},  {id_SPINE8, 1. - 1. * ew_dist},
-        {id_SPINE9, 1. - 2. * ew_dist},  {id_SPINE10, 1. - 3. * ew_dist}, {id_SPINE11, 1. - 4. * ew_dist},
-        {id_SPINE12, 1. - 5. * ew_dist}, {id_SPINE13, 1. - 6. * ew_dist}, {id_SPINE14, 1. - 7. * ew_dist},
-        {id_SPINE15, 1. - 8. * ew_dist}, {id_SPINE16, 1. - 1. * ew_dist}, {id_SPINE17, 1. - 2. * ew_dist},
-        {id_SPINE18, 1. - 3. * ew_dist}, {id_SPINE19, 1. - 4. * ew_dist}, {id_SPINE20, 1. - 5. * ew_dist},
-        {id_SPINE21, 1. - 6. * ew_dist}, {id_SPINE22, 1. - 7. * ew_dist}, {id_SPINE23, 1. - 8. * ew_dist},
-        {id_SPINE24, 1. - 1. * ew_dist}, {id_SPINE25, 1. - 2. * ew_dist}, {id_SPINE26, 1. - 3. * ew_dist},
-        {id_SPINE27, 1. - 4. * ew_dist}, {id_SPINE28, 1. - 5. * ew_dist}, {id_SPINE29, 1. - 6. * ew_dist},
-        {id_SPINE30, 1. - 7. * ew_dist}, {id_SPINE31, 1. - 8. * ew_dist},
-};
-
-const dict<IdString, std::pair<CruSide, float>> pipPoint = {
-        {id_X01, {Center, cru_y + 1. * cru_h / 9.}},
-        {id_X02, {Center, cru_y + 2. * cru_h / 9.}},
-        {id_X03, {Center, cru_y + 3. * cru_h / 9.}},
-        {id_X04, {Center, cru_y + 4. * cru_h / 9.}},
-        {id_X05, {Center, cru_y + 5. * cru_h / 9.}},
-        {id_X06, {Center, cru_y + 6. * cru_h / 9.}},
-        {id_X07, {Center, cru_y + 7. * cru_h / 9.}},
-        {id_X08, {Center, cru_y + 8. * cru_h / 9.}},
-        // LUT inputs
-        {id_A0, {Right, lut_y[0] + lut_A_off}},
-        {id_B0, {Right, lut_y[0] + lut_B_off}},
-        {id_C0, {Right, lut_y[0] + lut_C_off}},
-        {id_D0, {Right, lut_y[0] + lut_D_off}},
-        {id_A1, {Right, lut_y[1] + lut_A_off}},
-        {id_B1, {Right, lut_y[1] + lut_B_off}},
-        {id_C1, {Right, lut_y[1] + lut_C_off}},
-        {id_D1, {Right, lut_y[1] + lut_D_off}},
-        {id_A2, {Right, lut_y[2] + lut_A_off}},
-        {id_B2, {Right, lut_y[2] + lut_B_off}},
-        {id_C2, {Right, lut_y[2] + lut_C_off}},
-        {id_D2, {Right, lut_y[2] + lut_D_off}},
-        {id_A3, {Right, lut_y[3] + lut_A_off}},
-        {id_B3, {Right, lut_y[3] + lut_B_off}},
-        {id_C3, {Right, lut_y[3] + lut_C_off}},
-        {id_D3, {Right, lut_y[3] + lut_D_off}},
-        {id_A4, {Right, lut_y[4] + lut_A_off}},
-        {id_B4, {Right, lut_y[4] + lut_B_off}},
-        {id_C4, {Right, lut_y[4] + lut_C_off}},
-        {id_D4, {Right, lut_y[4] + lut_D_off}},
-        {id_A5, {Right, lut_y[5] + lut_A_off}},
-        {id_B5, {Right, lut_y[5] + lut_B_off}},
-        {id_C5, {Right, lut_y[5] + lut_C_off}},
-        {id_D5, {Right, lut_y[5] + lut_D_off}},
-        {id_A6, {Right, lut_y[6] + lut_A_off}},
-        {id_B6, {Right, lut_y[6] + lut_B_off}},
-        {id_C6, {Right, lut_y[6] + lut_C_off}},
-        {id_D6, {Right, lut_y[6] + lut_D_off}},
-        {id_A7, {Right, lut_y[7] + lut_A_off}},
-        {id_B7, {Right, lut_y[7] + lut_B_off}},
-        {id_C7, {Right, lut_y[7] + lut_C_off}},
-        {id_D7, {Right, lut_y[7] + lut_D_off}},
-        // wires below LUT0
-        {id_Q0, {Right, grp_lut_y[0] - right_wire_dist}},
-        {id_F0, {Right, grp_lut_y[0] - 2. * right_wire_dist}},
-        {id_OF3, {Right, grp_lut_y[0] - 3. * right_wire_dist}},
-        // wires between LUT1 and LUT2
-        {id_Q2, {Right, grp_lut_y[1] - right_wire_dist}},
-        {id_F2, {Right, grp_lut_y[1] - 2. * right_wire_dist}},
-        {id_OF2, {Right, grp_lut_y[1] - 3. * right_wire_dist}},
-        {id_OF1, {Right, grp_lut_y[1] - 4. * right_wire_dist}},
-        {id_OF0, {Right, grp_lut_y[1] - 5. * right_wire_dist}},
-        {id_SEL1, {Right, grp_lut_y[1] - 6. * right_wire_dist}},
-        {id_OF7, {Right, grp_lut_y[1] - 7. * right_wire_dist}},
-        {id_SEL0, {Right, grp_lut_y[1] - 8. * right_wire_dist}},
-        {id_F1, {Right, grp_lut_y[1] - 9. * right_wire_dist}},
-        {id_Q1, {Right, grp_lut_y[1] - 10. * right_wire_dist}},
-        // wires between LUT3 and LUT4
-        {id_Q4, {Right, grp_lut_y[2] - right_wire_dist}},
-        {id_F4, {Right, grp_lut_y[2] - 2. * right_wire_dist}},
-        {id_OF4, {Right, grp_lut_y[2] - 3. * right_wire_dist}},
-        {id_OF5, {Right, grp_lut_y[2] - 4. * right_wire_dist}},
-        {id_SEL7, {Right, grp_lut_y[2] - 5. * right_wire_dist}},
-        {id_SEL3, {Right, grp_lut_y[2] - 6. * right_wire_dist}},
-        {id_SEL2, {Right, grp_lut_y[2] - 7. * right_wire_dist}},
-        {id_F3, {Right, grp_lut_y[2] - 8. * right_wire_dist}},
-        {id_Q3, {Right, grp_lut_y[2] - 9. * right_wire_dist}},
-        // wires between LUT5 and LUT6
-        {id_F6, {Right, grp_lut_y[3] - right_wire_dist}},
-        {id_SEL5, {Right, grp_lut_y[3] - 2. * right_wire_dist}},
-        {id_SEL4, {Right, grp_lut_y[3] - 4. * right_wire_dist}},
-        {id_F5, {Right, grp_lut_y[3] - 5. * right_wire_dist}},
-        {id_Q5, {Right, grp_lut_y[3] - 6. * right_wire_dist}},
-        // Q6, Q7 --- IOB
-        {id_Q6, {Right, grp_lut_y[3] + grp_lut_h * 0.33}},
-        {id_Q7, {Right, grp_lut_y[3] + grp_lut_h * 0.66}},
-        // wires above LUT7
-        {id_F7, {Right, grp_lut_y[3] + grp_lut_h + right_wire_dist}},
-        {id_SEL6, {Right, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist}},
-        {id_OF6, {Right, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist}},
-        // DI0-5
-        {id_DI5, {Right, cru_y + cru_h - 0.5 * right_wire_dist}},
-        {id_DI4, {Right, cru_y + cru_h - 1. * right_wire_dist}},
-        {id_DI3, {Right, cru_y + cru_h - 1.5 * right_wire_dist}},
-        {id_DI2, {Right, cru_y + cru_h - 2. * right_wire_dist}},
-        {id_DI1, {Right, cru_y + cru_h - 2.5 * right_wire_dist}},
-        {id_DI0, {Right, cru_y + cru_h - 3. * right_wire_dist}},
-        // Q6
-        // CLK, CE, SET-RESET
-        {id_CLK0, {Right, lut_y[1] - clk_ce_set_vdist}},
-        {id_CE0, {Right, lut_y[1] - 2. * clk_ce_set_vdist}},
-        {id_LSR0, {Right, lut_y[1] - 3. * clk_ce_set_vdist}},
-        {id_CLK1, {Right, lut_y[3] - clk_ce_set_vdist}},
-        {id_CE1, {Right, lut_y[3] - 2. * clk_ce_set_vdist}},
-        {id_LSR1, {Right, lut_y[3] - 3. * clk_ce_set_vdist}},
-        {id_CLK2, {Right, lut_y[5] - clk_ce_set_vdist}},
-        {id_CE2, {Right, lut_y[5] - 2. * clk_ce_set_vdist}},
-        {id_LSR2, {Right, lut_y[5] - 3. * clk_ce_set_vdist}},
-        // SN
-        // 1 hop
-        {id_S100, {Left, cru_y + 1. * left_wire_dist}},
-        {id_S101, {Left, cru_y + 2. * left_wire_dist}},
-        {id_S130, {Left, cru_y + 3. * left_wire_dist}},
-        {id_S131, {Left, cru_y + 4. * left_wire_dist}},
-        {id_N101, {Left, cru_y + 5. * left_wire_dist}},
-        {id_N100, {Left, cru_y + 6. * left_wire_dist}},
-        {id_N131, {Left, cru_y + 7. * left_wire_dist}},
-        {id_N130, {Left, cru_y + 8. * left_wire_dist}},
-        // 1 hop SN
-        {id_N111, {Left, cru_y + 9. * left_wire_dist}},
-        {id_SN10, {Left, cru_y + 10. * left_wire_dist}},
-        {id_S111, {Left, cru_y + 11. * left_wire_dist}},
-        {id_N121, {Left, cru_y + 12. * left_wire_dist}},
-        {id_SN20, {Left, cru_y + 13. * left_wire_dist}},
-        {id_S121, {Left, cru_y + 14. * left_wire_dist}},
-        // 2 hop
-        {id_S200, {Left, cru_y + 15. * left_wire_dist}},
-        {id_S201, {Left, cru_y + 16. * left_wire_dist}},
-        {id_N202, {Left, cru_y + 17. * left_wire_dist}},
-        {id_S202, {Left, cru_y + 18. * left_wire_dist}},
-        {id_N201, {Left, cru_y + 19. * left_wire_dist}},
-        {id_N200, {Left, cru_y + 20. * left_wire_dist}},
-
-        {id_S210, {Left, cru_y + 21. * left_wire_dist}},
-        {id_S211, {Left, cru_y + 22. * left_wire_dist}},
-        {id_N212, {Left, cru_y + 23. * left_wire_dist}},
-        {id_S212, {Left, cru_y + 24. * left_wire_dist}},
-        {id_N211, {Left, cru_y + 25. * left_wire_dist}},
-        {id_N210, {Left, cru_y + 26. * left_wire_dist}},
-
-        {id_S220, {Left, cru_y + 27. * left_wire_dist}},
-        {id_S221, {Left, cru_y + 28. * left_wire_dist}},
-        {id_N222, {Left, cru_y + 29. * left_wire_dist}},
-        {id_S222, {Left, cru_y + 30. * left_wire_dist}},
-        {id_N221, {Left, cru_y + 31. * left_wire_dist}},
-        {id_N220, {Left, cru_y + 32. * left_wire_dist}},
-
-        {id_S230, {Left, cru_y + 33. * left_wire_dist}},
-        {id_S231, {Left, cru_y + 34. * left_wire_dist}},
-        {id_N232, {Left, cru_y + 35. * left_wire_dist}},
-        {id_S232, {Left, cru_y + 36. * left_wire_dist}},
-        {id_N231, {Left, cru_y + 37. * left_wire_dist}},
-        {id_N230, {Left, cru_y + 38. * left_wire_dist}},
-
-        {id_S240, {Left, cru_y + 39. * left_wire_dist}},
-        {id_S241, {Left, cru_y + 40. * left_wire_dist}},
-        {id_N242, {Left, cru_y + 41. * left_wire_dist}},
-        {id_S242, {Left, cru_y + 42. * left_wire_dist}},
-        {id_N241, {Left, cru_y + 43. * left_wire_dist}},
-        {id_N240, {Left, cru_y + 44. * left_wire_dist}},
-
-        {id_S250, {Left, cru_y + 45. * left_wire_dist}},
-        {id_S251, {Left, cru_y + 46. * left_wire_dist}},
-        {id_N252, {Left, cru_y + 47. * left_wire_dist}},
-        {id_S252, {Left, cru_y + 48. * left_wire_dist}},
-        {id_N251, {Left, cru_y + 49. * left_wire_dist}},
-        {id_N250, {Left, cru_y + 50. * left_wire_dist}},
-
-        {id_S260, {Left, cru_y + 51. * left_wire_dist}},
-        {id_S261, {Left, cru_y + 52. * left_wire_dist}},
-        {id_N262, {Left, cru_y + 53. * left_wire_dist}},
-        {id_S262, {Left, cru_y + 54. * left_wire_dist}},
-        {id_N261, {Left, cru_y + 55. * left_wire_dist}},
-        {id_N260, {Left, cru_y + 56. * left_wire_dist}},
-
-        {id_S270, {Left, cru_y + 57. * left_wire_dist}},
-        {id_S271, {Left, cru_y + 58. * left_wire_dist}},
-        {id_N272, {Left, cru_y + 59. * left_wire_dist}},
-        {id_S272, {Left, cru_y + 60. * left_wire_dist}},
-        {id_N271, {Left, cru_y + 61. * left_wire_dist}},
-        {id_N270, {Left, cru_y + 62. * left_wire_dist}},
-
-        // Clocks
-        {id_GT10, {Left, cru_y + 63. * left_wire_dist}},
-        {id_GT00, {Left, cru_y + 68. * left_wire_dist}},
-
-        // 4 hop
-        {id_N808, {Left, cru_y + 73. * left_wire_dist}},
-        {id_S800, {Left, cru_y + 74. * left_wire_dist}},
-        {id_S804, {Left, cru_y + 75. * left_wire_dist}},
-        {id_N804, {Left, cru_y + 76. * left_wire_dist}},
-        {id_N800, {Left, cru_y + 77. * left_wire_dist}},
-        {id_S808, {Left, cru_y + 78. * left_wire_dist}},
-
-        {id_N818, {Left, cru_y + 79. * left_wire_dist}},
-        {id_S810, {Left, cru_y + 80. * left_wire_dist}},
-        {id_S814, {Left, cru_y + 81. * left_wire_dist}},
-        {id_N814, {Left, cru_y + 82. * left_wire_dist}},
-        {id_N810, {Left, cru_y + 83. * left_wire_dist}},
-        {id_S818, {Left, cru_y + 84. * left_wire_dist}},
-
-        {id_N828, {Left, cru_y + 85. * left_wire_dist}},
-        {id_S820, {Left, cru_y + 86. * left_wire_dist}},
-        {id_S824, {Left, cru_y + 87. * left_wire_dist}},
-        {id_N824, {Left, cru_y + 88. * left_wire_dist}},
-        {id_N820, {Left, cru_y + 89. * left_wire_dist}},
-        {id_S828, {Left, cru_y + 90. * left_wire_dist}},
-
-        {id_N838, {Left, cru_y + 91. * left_wire_dist}},
-        {id_S830, {Left, cru_y + 92. * left_wire_dist}},
-        {id_S834, {Left, cru_y + 93. * left_wire_dist}},
-        {id_N834, {Left, cru_y + 94. * left_wire_dist}},
-        {id_N830, {Left, cru_y + 95. * left_wire_dist}},
-        {id_S838, {Left, cru_y + 96. * left_wire_dist}},
-
-        // EW
-        // 1 hop
-        {id_E101, {Top, cru_x + 1. * top_wire_dist}},
-        {id_E100, {Top, cru_x + 2. * top_wire_dist}},
-        {id_E131, {Top, cru_x + 3. * top_wire_dist}},
-        {id_E130, {Top, cru_x + 4. * top_wire_dist}},
-        {id_W100, {Top, cru_x + 5. * top_wire_dist}},
-        {id_W101, {Top, cru_x + 6. * top_wire_dist}},
-        {id_W130, {Top, cru_x + 7. * top_wire_dist}},
-        {id_W131, {Top, cru_x + 8. * top_wire_dist}},
-        // 1 hop EW
-        {id_E111, {Top, cru_x + 9. * top_wire_dist}},
-        {id_EW10, {Top, cru_x + 10. * top_wire_dist}},
-        {id_W111, {Top, cru_x + 11. * top_wire_dist}},
-        {id_E121, {Top, cru_x + 12. * top_wire_dist}},
-        {id_EW20, {Top, cru_x + 13. * top_wire_dist}},
-        {id_W121, {Top, cru_x + 14. * top_wire_dist}},
-        // 2 hop
-        {id_E202, {Top, cru_x + 15. * top_wire_dist}},
-        {id_E201, {Top, cru_x + 16. * top_wire_dist}},
-        {id_W200, {Top, cru_x + 17. * top_wire_dist}},
-        {id_E200, {Top, cru_x + 18. * top_wire_dist}},
-        {id_W201, {Top, cru_x + 19. * top_wire_dist}},
-        {id_W202, {Top, cru_x + 20. * top_wire_dist}},
-
-        {id_E212, {Top, cru_x + 21. * top_wire_dist}},
-        {id_E211, {Top, cru_x + 22. * top_wire_dist}},
-        {id_W210, {Top, cru_x + 23. * top_wire_dist}},
-        {id_E210, {Top, cru_x + 24. * top_wire_dist}},
-        {id_W211, {Top, cru_x + 25. * top_wire_dist}},
-        {id_W212, {Top, cru_x + 26. * top_wire_dist}},
-
-        {id_E222, {Top, cru_x + 27. * top_wire_dist}},
-        {id_E221, {Top, cru_x + 28. * top_wire_dist}},
-        {id_W220, {Top, cru_x + 29. * top_wire_dist}},
-        {id_E220, {Top, cru_x + 30. * top_wire_dist}},
-        {id_W221, {Top, cru_x + 31. * top_wire_dist}},
-        {id_W222, {Top, cru_x + 32. * top_wire_dist}},
-
-        {id_E232, {Top, cru_x + 33. * top_wire_dist}},
-        {id_E231, {Top, cru_x + 34. * top_wire_dist}},
-        {id_W230, {Top, cru_x + 35. * top_wire_dist}},
-        {id_E230, {Top, cru_x + 36. * top_wire_dist}},
-        {id_W231, {Top, cru_x + 37. * top_wire_dist}},
-        {id_W232, {Top, cru_x + 38. * top_wire_dist}},
-
-        {id_E242, {Top, cru_x + 39. * top_wire_dist}},
-        {id_E241, {Top, cru_x + 40. * top_wire_dist}},
-        {id_W240, {Top, cru_x + 41. * top_wire_dist}},
-        {id_E240, {Top, cru_x + 42. * top_wire_dist}},
-        {id_W241, {Top, cru_x + 43. * top_wire_dist}},
-        {id_W242, {Top, cru_x + 44. * top_wire_dist}},
-
-        {id_E252, {Top, cru_x + 45. * top_wire_dist}},
-        {id_E251, {Top, cru_x + 46. * top_wire_dist}},
-        {id_W250, {Top, cru_x + 47. * top_wire_dist}},
-        {id_E250, {Top, cru_x + 48. * top_wire_dist}},
-        {id_W251, {Top, cru_x + 49. * top_wire_dist}},
-        {id_W252, {Top, cru_x + 50. * top_wire_dist}},
-
-        {id_E262, {Top, cru_x + 51. * top_wire_dist}},
-        {id_E261, {Top, cru_x + 52. * top_wire_dist}},
-        {id_W260, {Top, cru_x + 53. * top_wire_dist}},
-        {id_E260, {Top, cru_x + 54. * top_wire_dist}},
-        {id_W261, {Top, cru_x + 55. * top_wire_dist}},
-        {id_W262, {Top, cru_x + 56. * top_wire_dist}},
-
-        {id_E272, {Top, cru_x + 57. * top_wire_dist}},
-        {id_E271, {Top, cru_x + 58. * top_wire_dist}},
-        {id_W270, {Top, cru_x + 59. * top_wire_dist}},
-        {id_E270, {Top, cru_x + 60. * top_wire_dist}},
-        {id_W271, {Top, cru_x + 61. * top_wire_dist}},
-        {id_W272, {Top, cru_x + 62. * top_wire_dist}},
-
-        // Global taps -> bracnhes
-        {id_GBO0, {Top, cru_x + 63. * top_wire_dist}},
-        {id_GB00, {Top, cru_x + 64. * top_wire_dist}},
-        {id_GB10, {Top, cru_x + 65. * top_wire_dist}},
-        {id_GB20, {Top, cru_x + 66. * top_wire_dist}},
-        {id_GB30, {Top, cru_x + 67. * top_wire_dist}},
-        {id_GBO1, {Top, cru_x + 68. * top_wire_dist}},
-        {id_GB40, {Top, cru_x + 68. * top_wire_dist}},
-        {id_GB50, {Top, cru_x + 69. * top_wire_dist}},
-        {id_GB60, {Top, cru_x + 70. * top_wire_dist}},
-        {id_GB70, {Top, cru_x + 71. * top_wire_dist}},
-
-        // 4 hop
-        {id_E808, {Top, cru_x + 72. * top_wire_dist}},
-        {id_W800, {Top, cru_x + 73. * top_wire_dist}},
-        {id_W804, {Top, cru_x + 74. * top_wire_dist}},
-        {id_E804, {Top, cru_x + 75. * top_wire_dist}},
-        {id_E800, {Top, cru_x + 76. * top_wire_dist}},
-        {id_W808, {Top, cru_x + 77. * top_wire_dist}},
-
-        {id_E818, {Top, cru_x + 78. * top_wire_dist}},
-        {id_W810, {Top, cru_x + 79. * top_wire_dist}},
-        {id_W814, {Top, cru_x + 80. * top_wire_dist}},
-        {id_E814, {Top, cru_x + 81. * top_wire_dist}},
-        {id_E810, {Top, cru_x + 82. * top_wire_dist}},
-        {id_W818, {Top, cru_x + 83. * top_wire_dist}},
-
-        {id_E828, {Top, cru_x + 84. * top_wire_dist}},
-        {id_W820, {Top, cru_x + 85. * top_wire_dist}},
-        {id_W824, {Top, cru_x + 86. * top_wire_dist}},
-        {id_E824, {Top, cru_x + 87. * top_wire_dist}},
-        {id_E820, {Top, cru_x + 88. * top_wire_dist}},
-        {id_W828, {Top, cru_x + 89. * top_wire_dist}},
-
-        {id_E838, {Top, cru_x + 90. * top_wire_dist}},
-        {id_W830, {Top, cru_x + 91. * top_wire_dist}},
-        {id_W834, {Top, cru_x + 92. * top_wire_dist}},
-        {id_E834, {Top, cru_x + 93. * top_wire_dist}},
-        {id_E830, {Top, cru_x + 94. * top_wire_dist}},
-        {id_W838, {Top, cru_x + 95. * top_wire_dist}},
-
-};
-
-// wire
-const std::vector<IdString> decalless_wires = {id_X01, id_X02, id_X03, id_X04, id_X05, id_X06, id_X07};
-
-const float clk_ce_set_hdist = dff_w / 4.;
-const float dff_f_x = (grp_lut_x + grp_lut_w + dff_x + dff_w) / 2.;
-const float mux5i_x = (grp_lut_x + grp_lut_w + mux2lut5_x) / 2.;
-
-// id, {x1, y1, x2, y2}
-const dict<IdString, std::vector<std::tuple<float, float, float, float>>> sliceLocalWires = {
-        // dff
-        {id_CLK0,
-         {{cru_x + cru_w, pipPoint.at(id_CLK0).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK0).second},
-          {dff_x + clk_ce_set_hdist, lut_y[1], dff_x + clk_ce_set_hdist, lut_y[0] + lut_h}}},
-        {id_CE0,
-         {{cru_x + cru_w, pipPoint.at(id_CE0).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE0).second},
-          {dff_x + 2 * clk_ce_set_hdist, lut_y[1], dff_x + 2. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
-        {id_LSR0,
-         {{cru_x + cru_w, pipPoint.at(id_LSR0).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR0).second},
-          {dff_x + 3 * clk_ce_set_hdist, lut_y[1], dff_x + 3. * clk_ce_set_hdist, lut_y[0] + lut_h}}},
-        {id_CLK1,
-         {{cru_x + cru_w, pipPoint.at(id_CLK1).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK1).second},
-          {dff_x + clk_ce_set_hdist, lut_y[3], dff_x + clk_ce_set_hdist, lut_y[2] + lut_h}}},
-        {id_CE1,
-         {{cru_x + cru_w, pipPoint.at(id_CE1).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE1).second},
-          {dff_x + 2 * clk_ce_set_hdist, lut_y[3], dff_x + 2. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
-        {id_LSR1,
-         {{cru_x + cru_w, pipPoint.at(id_LSR1).second, dff_x + 3. * clk_ce_set_hdist, pipPoint.at(id_LSR1).second},
-          {dff_x + 3 * clk_ce_set_hdist, lut_y[3], dff_x + 3. * clk_ce_set_hdist, lut_y[2] + lut_h}}},
-        {id_CLK2,
-         {{cru_x + cru_w, pipPoint.at(id_CLK2).second, dff_x + clk_ce_set_hdist, pipPoint.at(id_CLK2).second},
-          {dff_x + clk_ce_set_hdist, lut_y[5], dff_x + clk_ce_set_hdist, lut_y[4] + lut_h}}},
-        {id_CE2,
-         {{cru_x + cru_w, pipPoint.at(id_CE2).second, dff_x + 2. * clk_ce_set_hdist, pipPoint.at(id_CE2).second},
-          {dff_x + 2 * clk_ce_set_hdist, lut_y[5], dff_x + 2. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
-        {id_LSR2,
-         {{cru_x + cru_w, pipPoint.at(id_LSR2).second, dff_x + 3 * clk_ce_set_hdist, pipPoint.at(id_LSR2).second},
-          {dff_x + 3 * clk_ce_set_hdist, lut_y[5], dff_x + 3. * clk_ce_set_hdist, lut_y[4] + lut_h}}},
-        // lut
-        {id_A0, {{cru_x + cru_w, lut_y[0] + lut_A_off, lut_x, lut_y[0] + lut_A_off}}},
-        {id_B0, {{cru_x + cru_w, lut_y[0] + lut_B_off, lut_x, lut_y[0] + lut_B_off}}},
-        {id_C0, {{cru_x + cru_w, lut_y[0] + lut_C_off, lut_x, lut_y[0] + lut_C_off}}},
-        {id_D0, {{cru_x + cru_w, lut_y[0] + lut_D_off, lut_x, lut_y[0] + lut_D_off}}},
-        {id_A1, {{cru_x + cru_w, lut_y[1] + lut_A_off, lut_x, lut_y[1] + lut_A_off}}},
-        {id_B1, {{cru_x + cru_w, lut_y[1] + lut_B_off, lut_x, lut_y[1] + lut_B_off}}},
-        {id_C1, {{cru_x + cru_w, lut_y[1] + lut_C_off, lut_x, lut_y[1] + lut_C_off}}},
-        {id_D1, {{cru_x + cru_w, lut_y[1] + lut_D_off, lut_x, lut_y[1] + lut_D_off}}},
-        {id_A2, {{cru_x + cru_w, lut_y[2] + lut_A_off, lut_x, lut_y[2] + lut_A_off}}},
-        {id_B2, {{cru_x + cru_w, lut_y[2] + lut_B_off, lut_x, lut_y[2] + lut_B_off}}},
-        {id_C2, {{cru_x + cru_w, lut_y[2] + lut_C_off, lut_x, lut_y[2] + lut_C_off}}},
-        {id_D2, {{cru_x + cru_w, lut_y[2] + lut_D_off, lut_x, lut_y[2] + lut_D_off}}},
-        {id_A3, {{cru_x + cru_w, lut_y[3] + lut_A_off, lut_x, lut_y[3] + lut_A_off}}},
-        {id_B3, {{cru_x + cru_w, lut_y[3] + lut_B_off, lut_x, lut_y[3] + lut_B_off}}},
-        {id_C3, {{cru_x + cru_w, lut_y[3] + lut_C_off, lut_x, lut_y[3] + lut_C_off}}},
-        {id_D3, {{cru_x + cru_w, lut_y[3] + lut_D_off, lut_x, lut_y[3] + lut_D_off}}},
-        {id_A4, {{cru_x + cru_w, lut_y[4] + lut_A_off, lut_x, lut_y[4] + lut_A_off}}},
-        {id_B4, {{cru_x + cru_w, lut_y[4] + lut_B_off, lut_x, lut_y[4] + lut_B_off}}},
-        {id_C4, {{cru_x + cru_w, lut_y[4] + lut_C_off, lut_x, lut_y[4] + lut_C_off}}},
-        {id_D4, {{cru_x + cru_w, lut_y[4] + lut_D_off, lut_x, lut_y[4] + lut_D_off}}},
-        {id_A5, {{cru_x + cru_w, lut_y[5] + lut_A_off, lut_x, lut_y[5] + lut_A_off}}},
-        {id_B5, {{cru_x + cru_w, lut_y[5] + lut_B_off, lut_x, lut_y[5] + lut_B_off}}},
-        {id_C5, {{cru_x + cru_w, lut_y[5] + lut_C_off, lut_x, lut_y[5] + lut_C_off}}},
-        {id_D5, {{cru_x + cru_w, lut_y[5] + lut_D_off, lut_x, lut_y[5] + lut_D_off}}},
-        {id_A6, {{cru_x + cru_w, lut_y[6] + lut_A_off, lut_x, lut_y[6] + lut_A_off}}},
-        {id_B6, {{cru_x + cru_w, lut_y[6] + lut_B_off, lut_x, lut_y[6] + lut_B_off}}},
-        {id_C6, {{cru_x + cru_w, lut_y[6] + lut_C_off, lut_x, lut_y[6] + lut_C_off}}},
-        {id_D6, {{cru_x + cru_w, lut_y[6] + lut_D_off, lut_x, lut_y[6] + lut_D_off}}},
-        {id_A7, {{cru_x + cru_w, lut_y[7] + lut_A_off, lut_x, lut_y[7] + lut_A_off}}},
-        {id_B7, {{cru_x + cru_w, lut_y[7] + lut_B_off, lut_x, lut_y[7] + lut_B_off}}},
-        {id_C7, {{cru_x + cru_w, lut_y[7] + lut_C_off, lut_x, lut_y[7] + lut_C_off}}},
-        {id_D7, {{cru_x + cru_w, lut_y[7] + lut_D_off, lut_x, lut_y[7] + lut_D_off}}},
-        // wires below LUT0
-        {id_Q0,
-         {{cru_x + cru_w, grp_lut_y[0] - right_wire_dist, dff_f_x, grp_lut_y[0] - right_wire_dist},
-          {dff_f_x, grp_lut_y[0] - right_wire_dist, dff_f_x, lut_y[0] + lut_h / 2.},
-          {dff_f_x, lut_y[0] + lut_h / 2., dff_x + dff_w, lut_y[0] + lut_h / 2.}}},
-        {id_F0,
-         {{cru_x + cru_w, grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[0] - 2. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[0] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[0] + lut_h / 2., dff_x, lut_y[0] + lut_h / 2.}}},
-        {id_I0MUX0,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[0] - 2. * right_wire_dist, mux5i_x,
-           grp_lut_y[0] - 2. * right_wire_dist},
-          {mux5i_x, grp_lut_y[0] - 2. * right_wire_dist, mux5i_x, lut_y[0] + lut_h / 2.},
-          {mux5i_x, lut_y[0] + lut_h / 2., mux2lut5_x, lut_y[0] + lut_h / 2.}}},
-        {id_OF3,
-         {{cru_x + cru_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
-           grp_lut_y[0] - 3. * right_wire_dist},
-          {mux2lut7_x + 4. / 3. * mux_w, grp_lut_y[0] - 3. * right_wire_dist, mux2lut7_x + 4. / 3. * mux_w,
-           mux2lut7_y + mux_h / 2.},
-          {mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut7_x + mux_w, mux2lut7_y + mux_h / 2.}}},
-        {id_I1MUX7, {{mux2lut7_x + 4. / 3. * mux_w, mux2lut7_y + mux_h / 2., mux2lut8_x, mux2lut7_y + mux_h / 2.}}},
-        // wires between LUT1 and LUT2
-        {id_Q1,
-         {{cru_x + cru_w, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, grp_lut_y[1] - 10. * right_wire_dist},
-          {dff_f_x, grp_lut_y[1] - 10. * right_wire_dist, dff_f_x, lut_y[1] + lut_h / 2.},
-          {dff_f_x, lut_y[1] + lut_h / 2., dff_x + dff_w, lut_y[1] + lut_h / 2.}}},
-        {id_F1,
-         {{cru_x + cru_w, grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[1] - 9. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[1] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[1] + lut_h / 2., dff_x, lut_y[1] + lut_h / 2.}}},
-        {id_I1MUX0,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 9. * right_wire_dist, mux5i_x,
-           grp_lut_y[1] - 9. * right_wire_dist},
-          {mux5i_x, grp_lut_y[1] - 9. * right_wire_dist, mux5i_x, lut_y[1] + lut_h / 2.},
-          {mux5i_x, lut_y[1] + lut_h / 2., mux2lut5_x, lut_y[1] + lut_h / 2.}}},
-        {id_SEL0,
-         {{cru_x + cru_w, grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           grp_lut_y[1] - 8. * right_wire_dist},
-          {mux2lut5_x + mux_w / 2., grp_lut_y[1] - 8. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           mux2lut5_y[0] + mux_h - mux_f / 2.}}},
-        {id_OF7,
-         {{cru_x + cru_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
-           grp_lut_y[1] - 7. * right_wire_dist},
-          {mux2lut8_x + 4. / 3. * mux_w, grp_lut_y[1] - 7. * right_wire_dist, mux2lut8_x + 4. / 3. * mux_w,
-           mux2lut8_y + mux_h / 2.},
-          {mux2lut8_x + 4. / 3. * mux_w, mux2lut8_y + mux_h / 2., mux2lut8_x + mux_w, mux2lut8_y + mux_h / 2.}}},
-        {id_SEL1,
-         {{cru_x + cru_w, grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
-           grp_lut_y[1] - 6. * right_wire_dist},
-          {mux2lut6_x + mux_w / 2., grp_lut_y[1] - 6. * right_wire_dist, mux2lut6_x + mux_w / 2.,
-           mux2lut6_y[0] + mux_h - mux_f / 2.}}},
-        {id_OF0,
-         {{cru_x + cru_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           grp_lut_y[1] - 5. * right_wire_dist},
-          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[1] - 5. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           mux2lut5_y[0] + mux_h / 2.},
-          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[0] + mux_h / 2.}}},
-        {id_I1MUX1,
-         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[0] + mux_h / 2., mux2lut6_x, mux2lut5_y[0] + mux_h / 2.}}},
-        {id_OF1,
-         {{cru_x + cru_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           grp_lut_y[1] - 4. * right_wire_dist},
-          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           mux2lut6_y[0] + mux_h / 2.},
-          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[0] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[0] + mux_h / 2.}}},
-        {id_I1MUX3,
-         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[1] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           mux2lut7_y + mux_h * 1. / 4.},
-          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 1. / 4., mux2lut7_x, mux2lut7_y + mux_h * 1. / 4.}}},
-        {id_OF2,
-         {{cru_x + cru_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
-           grp_lut_y[1] - 3. * right_wire_dist},
-          {mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
-           mux2lut5_y[1] + mux_h / 2.},
-          {mux2lut5_x + 5. / 3. * mux_w, mux2lut5_y[1] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[1] + mux_h / 2.}}},
-        {id_I0MUX1,
-         {{mux2lut5_x + 5. / 3. * mux_w, grp_lut_y[1] - 3. * right_wire_dist, mux2lut5_x + 5. / 3. * mux_w,
-           mux2lut6_y[0] + mux_h * 3. / 4.},
-          {mux2lut5_x + 5. / 3. * mux_w, mux2lut6_y[0] + mux_h * 3. / 4., mux2lut6_x,
-           mux2lut6_y[0] + mux_h * 3. / 4.}}},
-        {id_F2,
-         {{cru_x + cru_w, grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[1] - 2. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[2] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[2] + lut_h / 2., dff_x, lut_y[2] + lut_h / 2.}}},
-        {id_I0MUX2,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[1] - 2. * right_wire_dist, mux5i_x,
-           grp_lut_y[1] - 2. * right_wire_dist},
-          {mux5i_x, grp_lut_y[1] - 2. * right_wire_dist, mux5i_x, lut_y[2] + lut_h / 2.},
-          {mux5i_x, lut_y[2] + lut_h / 2., mux2lut5_x, lut_y[2] + lut_h / 2.}}},
-        {id_Q2,
-         {{cru_x + cru_w, grp_lut_y[1] - right_wire_dist, dff_f_x, grp_lut_y[1] - right_wire_dist},
-          {dff_f_x, grp_lut_y[1] - right_wire_dist, dff_f_x, lut_y[2] + lut_h / 2.},
-          {dff_f_x, lut_y[2] + lut_h / 2., dff_x + dff_w, lut_y[2] + lut_h / 2.}}},
-        // wires between LUT3 and LUT4
-        {id_Q3,
-         {{cru_x + cru_w, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, grp_lut_y[2] - 9. * right_wire_dist},
-          {dff_f_x, grp_lut_y[2] - 9. * right_wire_dist, dff_f_x, lut_y[3] + lut_h / 2.},
-          {dff_f_x, lut_y[3] + lut_h / 2., dff_x + dff_w, lut_y[3] + lut_h / 2.}}},
-        {id_F3,
-         {{cru_x + cru_w, grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[2] - 8. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[3] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[3] + lut_h / 2., dff_x, lut_y[3] + lut_h / 2.}}},
-        {id_I1MUX2,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 8. * right_wire_dist, mux5i_x,
-           grp_lut_y[2] - 8. * right_wire_dist},
-          {mux5i_x, grp_lut_y[2] - 8. * right_wire_dist, mux5i_x, lut_y[3] + lut_h / 2.},
-          {mux5i_x, lut_y[3] + lut_h / 2., mux2lut5_x, lut_y[3] + lut_h / 2.}}},
-        {id_SEL2,
-         {{cru_x + cru_w, grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           grp_lut_y[2] - 7. * right_wire_dist},
-          {mux2lut5_x + mux_w / 2., grp_lut_y[2] - 7. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           mux2lut5_y[1] + mux_h - mux_f / 2.}}},
-        {id_SEL3,
-         {{cru_x + cru_w, grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
-           grp_lut_y[2] - 6. * right_wire_dist},
-          {mux2lut7_x + mux_w / 2., grp_lut_y[2] - 6. * right_wire_dist, mux2lut7_x + mux_w / 2.,
-           mux2lut7_y + mux_h - mux_f / 2.}}},
-        {id_SEL7,
-         {{cru_x + cru_w, grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
-           grp_lut_y[2] - 5. * right_wire_dist},
-          {mux2lut8_x + mux_w / 2., grp_lut_y[2] - 5. * right_wire_dist, mux2lut8_x + mux_w / 2.,
-           mux2lut8_y + mux_h - mux_f / 2.}}},
-        {id_OF5,
-         {{cru_x + cru_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           grp_lut_y[2] - 4. * right_wire_dist},
-          {mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           mux2lut6_y[1] + mux_h / 2.},
-          {mux2lut6_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h / 2., mux2lut6_x + mux_w, mux2lut6_y[1] + mux_h / 2.}}},
-        {id_I0MUX3,
-         {{mux2lut6_x + 4. / 3. * mux_w, grp_lut_y[2] - 4. * right_wire_dist, mux2lut6_x + 4. / 3. * mux_w,
-           mux2lut7_y + mux_h * 3. / 4.},
-          {mux2lut6_x + 4. / 3. * mux_w, mux2lut7_y + mux_h * 3. / 4., mux2lut7_x, mux2lut7_y + mux_h * 3. / 4.}}},
-        {id_OF4,
-         {{cru_x + cru_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           grp_lut_y[2] - 3. * right_wire_dist},
-          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[2] - 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           mux2lut5_y[2] + mux_h / 2.},
-          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[2] + mux_h / 2.}}},
-        {id_I1MUX5,
-         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[2] + mux_h / 2., mux2lut6_x, mux2lut5_y[2] + mux_h / 2.}}},
-        {id_F4,
-         {{cru_x + cru_w, grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[2] - 2. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[4] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[4] + lut_h / 2., dff_x, lut_y[4] + lut_h / 2.}}},
-        {id_I0MUX4,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[2] - 2. * right_wire_dist, mux5i_x,
-           grp_lut_y[2] - 2. * right_wire_dist},
-          {mux5i_x, grp_lut_y[2] - 2. * right_wire_dist, mux5i_x, lut_y[4] + lut_h / 2.},
-          {mux5i_x, lut_y[4] + lut_h / 2., mux2lut5_x, lut_y[4] + lut_h / 2.}}},
-        {id_Q4,
-         {{cru_x + cru_w, grp_lut_y[2] - right_wire_dist, dff_f_x, grp_lut_y[2] - right_wire_dist},
-          {dff_f_x, grp_lut_y[2] - right_wire_dist, dff_f_x, lut_y[4] + lut_h / 2.},
-          {dff_f_x, lut_y[4] + lut_h / 2., dff_x + dff_w, lut_y[4] + lut_h / 2.}}},
-        // wires between LUT5 and LUT6
-        {id_Q5,
-         {{cru_x + cru_w, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, grp_lut_y[3] - 6. * right_wire_dist},
-          {dff_f_x, grp_lut_y[3] - 6. * right_wire_dist, dff_f_x, lut_y[5] + lut_h / 2.},
-          {dff_f_x, lut_y[5] + lut_h / 2., dff_x + dff_w, lut_y[5] + lut_h / 2.}}},
-        {id_F5,
-         {{cru_x + cru_w, grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[3] - 5. * right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[5] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[5] + lut_h / 2., dff_x, lut_y[5] + lut_h / 2.}}},
-        {id_I1MUX4,
-         {{(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - 5. * right_wire_dist, mux5i_x,
-           grp_lut_y[3] - 5. * right_wire_dist},
-          {mux5i_x, grp_lut_y[3] - 5. * right_wire_dist, mux5i_x, lut_y[5] + lut_h / 2.},
-          {mux5i_x, lut_y[5] + lut_h / 2., mux2lut5_x, lut_y[5] + lut_h / 2.}}},
-        {id_SEL4,
-         {{cru_x + cru_w, grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           grp_lut_y[3] - 4. * right_wire_dist},
-          {mux2lut5_x + mux_w / 2., grp_lut_y[3] - 4. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           mux2lut5_y[2] + mux_h - mux_f / 2.}}},
-        {id_SEL5,
-         {{cru_x + cru_w, grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
-           grp_lut_y[3] - 2. * right_wire_dist},
-          {mux2lut6_x + mux_w / 2., grp_lut_y[3] - 2. * right_wire_dist, mux2lut6_x + mux_w / 2.,
-           mux2lut6_y[1] + mux_h - mux_f / 2.}}},
-        {id_F6,
-         {{cru_x + cru_w, grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] - right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[6] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[6] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2.}}},
-        {id_I0MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[6] + lut_h / 2., mux2lut5_x, lut_y[6] + lut_h / 2.}}},
-        // wires above LUT7
-        {id_F7,
-         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           grp_lut_y[3] + grp_lut_h + right_wire_dist},
-          {(lut_x + lut_w + dff_x) / 2., grp_lut_y[3] + grp_lut_h + right_wire_dist, (lut_x + lut_w + dff_x) / 2.,
-           lut_y[7] + lut_h / 2.},
-          {lut_x + lut_w, lut_y[7] + lut_h / 2., (lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2.}}},
-        {id_I1MUX6, {{(lut_x + lut_w + dff_x) / 2., lut_y[7] + lut_h / 2., mux2lut5_x, lut_y[7] + lut_h / 2.}}},
-        {id_SEL6,
-         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist},
-          {mux2lut5_x + mux_w / 2., grp_lut_y[3] + grp_lut_h + 2. * right_wire_dist, mux2lut5_x + mux_w / 2.,
-           mux2lut5_y[3] + mux_h - mux_f / 2.}}},
-        {id_OF6,
-         {{cru_x + cru_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist},
-          {mux2lut5_x + 4. / 3. * mux_w, grp_lut_y[3] + grp_lut_h + 3. * right_wire_dist, mux2lut5_x + 4. / 3. * mux_w,
-           mux2lut5_y[3] + mux_h / 2.},
-          {mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + mux_w, mux2lut5_y[3] + mux_h / 2.}}},
-        {id_I0MUX5,
-         {{mux2lut5_x + 4. / 3. * mux_w, mux2lut5_y[3] + mux_h / 2., mux2lut5_x + 4. / 3. * mux_w,
-           mux2lut6_y[1] + mux_h * 3. / 4.},
-          {mux2lut5_x + 4. / 3. * mux_w, mux2lut6_y[1] + mux_h * 3. / 4., mux2lut6_x,
-           mux2lut6_y[1] + mux_h * 3. / 4.}}},
-};
-
-const dict<IdString, std::vector<std::tuple<float, float, float, float>>> globalSimpleWires = {
-        {id_I0MUX7,
-         {{mux2lut8_x, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4.},
-          {mux2lut8_x - 1. / 3. * mux_w, mux2lut8_y + mux_h / 4., mux2lut8_x - 1. / 3. * mux_w,
-           cru_y - 2. * right_wire_dist},
-          {mux2lut8_x - 1. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
-           cru_y - 2. * right_wire_dist},
-          {1. + mux2lut7_x + 4. / 3. * mux_w, cru_y - 2. * right_wire_dist, 1. + mux2lut7_x + 4. / 3. * mux_w,
-           grp_lut_y[0] - 3. * right_wire_dist}}},
-};
-
-dict<IdString, std::vector<std::tuple<float, float, float, float>>> const globalWires = {
-#define PIP_Y(pip_id) (pipPoint.at(pip_id).second)
-#define WIRE_X(offset) (cru_x - ((float)offset) * sn_dist)
-        // 1 hop
-        {id_S10,
-         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
-          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. + PIP_Y(id_S101)},
-          {WIRE_X(1), -1. + PIP_Y(id_S101), WIRE_X(0), -1. + PIP_Y(id_S101)}}},
-        {id_N10,
-         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
-          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + PIP_Y(id_N101)},
-          {WIRE_X(2), 1. + PIP_Y(id_N101), WIRE_X(0), 1. + PIP_Y(id_N101)}}},
-        {id_S10_loop0,
-         {{WIRE_X(0), PIP_Y(id_S100), WIRE_X(1), PIP_Y(id_S100)},
-          {WIRE_X(1), PIP_Y(id_S100), WIRE_X(1), -1. * wrap_len},
-          {WIRE_X(1), -1. * wrap_len, WIRE_X(2), -1. * wrap_len},
-          {WIRE_X(2), -1. * wrap_len, WIRE_X(2), PIP_Y(id_N101)},
-          {WIRE_X(2), PIP_Y(id_N101), WIRE_X(0), PIP_Y(id_N101)}}},
-        {id_N10_loop0,
-         {{WIRE_X(0), PIP_Y(id_N100), WIRE_X(2), PIP_Y(id_N100)},
-          {WIRE_X(2), PIP_Y(id_N100), WIRE_X(2), 1. + 1. * wrap_len},
-          {WIRE_X(2), 1. + 1. * wrap_len, WIRE_X(1), 1. + 1. * wrap_len},
-          {WIRE_X(1), 1. + 1. * wrap_len, WIRE_X(1), PIP_Y(id_S101)},
-          {WIRE_X(1), PIP_Y(id_S101), WIRE_X(0), PIP_Y(id_S101)}}},
-        {id_S13,
-         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
-          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. + PIP_Y(id_S131)},
-          {WIRE_X(3), -1. + PIP_Y(id_S131), WIRE_X(0), -1. + PIP_Y(id_S131)}}},
-        {id_N13,
-         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
-          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + PIP_Y(id_N131)},
-          {WIRE_X(4), 1. + PIP_Y(id_N131), WIRE_X(0), 1. + PIP_Y(id_N131)}}},
-        {id_S13_loop0,
-         {{WIRE_X(0), PIP_Y(id_S130), WIRE_X(3), PIP_Y(id_S130)},
-          {WIRE_X(3), PIP_Y(id_S130), WIRE_X(3), -1. * wrap_len},
-          {WIRE_X(3), -1. * wrap_len, WIRE_X(4), -1. * wrap_len},
-          {WIRE_X(4), -1. * wrap_len, WIRE_X(4), PIP_Y(id_N131)},
-          {WIRE_X(4), PIP_Y(id_N131), WIRE_X(0), PIP_Y(id_N131)}}},
-        {id_N13_loop0,
-         {{WIRE_X(0), PIP_Y(id_N130), WIRE_X(4), PIP_Y(id_N130)},
-          {WIRE_X(4), PIP_Y(id_N130), WIRE_X(4), 1. + 1. * wrap_len},
-          {WIRE_X(4), 1. + 1. * wrap_len, WIRE_X(3), 1. + 1. * wrap_len},
-          {WIRE_X(3), 1. + 1. * wrap_len, WIRE_X(3), PIP_Y(id_S131)},
-          {WIRE_X(3), PIP_Y(id_S131), WIRE_X(0), PIP_Y(id_S131)}}},
-        // 1 hop SN
-        {id_SN10,
-         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
-          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
-          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
-          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
-          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
-        {id_SN10_loop_n,
-         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
-          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + 1. * wrap_len},
-          {WIRE_X(6), 1. + 1. * wrap_len, WIRE_X(5), 1. + 1. * wrap_len},
-          {WIRE_X(5), 1. + 1. * wrap_len, WIRE_X(5), PIP_Y(id_SN10)},
-          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. + PIP_Y(id_S111)},
-          {WIRE_X(5), -1. + PIP_Y(id_S111), WIRE_X(0), -1. + PIP_Y(id_S111)}}},
-        {id_SN10_loop_s,
-         {{WIRE_X(0), PIP_Y(id_SN10), WIRE_X(6), PIP_Y(id_SN10)},
-          {WIRE_X(6), PIP_Y(id_SN10), WIRE_X(6), 1. + PIP_Y(id_N111)},
-          {WIRE_X(6), 1. + PIP_Y(id_N111), WIRE_X(0), 1. + PIP_Y(id_N111)},
-          {WIRE_X(5), PIP_Y(id_SN10), WIRE_X(5), -1. * wrap_len},
-          {WIRE_X(5), -1. * wrap_len, WIRE_X(6), -1. * wrap_len},
-          {WIRE_X(6), -1. * wrap_len, WIRE_X(6), PIP_Y(id_N111)},
-          {WIRE_X(6), PIP_Y(id_N111), WIRE_X(0), PIP_Y(id_N111)}}},
-        {id_SN20,
-         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
-          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
-          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
-          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
-          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
-        {id_SN20_loop_n,
-         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
-          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + 1. * wrap_len},
-          {WIRE_X(8), 1. + 1. * wrap_len, WIRE_X(7), 1. + 1. * wrap_len},
-          {WIRE_X(7), 1. + 1. * wrap_len, WIRE_X(7), PIP_Y(id_SN10)},
-          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. + PIP_Y(id_S121)},
-          {WIRE_X(7), -1. + PIP_Y(id_S121), WIRE_X(0), -1. + PIP_Y(id_S121)}}},
-        {id_SN20_loop_s,
-         {{WIRE_X(0), PIP_Y(id_SN20), WIRE_X(8), PIP_Y(id_SN20)},
-          {WIRE_X(8), PIP_Y(id_SN20), WIRE_X(8), 1. + PIP_Y(id_N121)},
-          {WIRE_X(8), 1. + PIP_Y(id_N121), WIRE_X(0), 1. + PIP_Y(id_N121)},
-          {WIRE_X(7), PIP_Y(id_SN20), WIRE_X(7), -1. * wrap_len},
-          {WIRE_X(7), -1. * wrap_len, WIRE_X(8), -1. * wrap_len},
-          {WIRE_X(8), -1. * wrap_len, WIRE_X(8), PIP_Y(id_N121)},
-          {WIRE_X(8), PIP_Y(id_N121), WIRE_X(0), PIP_Y(id_N121)}}},
-        // 2 hop
-        {id_S20,
-         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
-          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
-          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
-          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -2. + PIP_Y(id_S202)},
-          {WIRE_X(9), -2. + PIP_Y(id_S202), WIRE_X(0), -2. + PIP_Y(id_S202)}}},
-        {id_N20,
-         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
-          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
-          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
-          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + PIP_Y(id_N202)},
-          {WIRE_X(10), 2. + PIP_Y(id_N202), WIRE_X(0), 2. + PIP_Y(id_N202)}}},
-        {id_S20_loop0,
-         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
-          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. * wrap_len},
-          {WIRE_X(11), -1. * wrap_len, WIRE_X(12), -1. * wrap_len},
-          {WIRE_X(12), -1. * wrap_len, WIRE_X(12), PIP_Y(id_N201)},
-          {WIRE_X(12), PIP_Y(id_N201), WIRE_X(0), PIP_Y(id_N201)},
-          {WIRE_X(10), PIP_Y(id_N201), WIRE_X(10), 1. + PIP_Y(id_N202)},
-          {WIRE_X(10), 1. + PIP_Y(id_N202), WIRE_X(0), 1. + PIP_Y(id_N202)}}},
-        {id_N20_loop0,
-         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
-          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + 1. * wrap_len},
-          {WIRE_X(12), 1. + 1. * wrap_len, WIRE_X(11), 1. + 1. * wrap_len},
-          {WIRE_X(11), 1. + 1. * wrap_len, WIRE_X(11), PIP_Y(id_S201)},
-          {WIRE_X(11), PIP_Y(id_S201), WIRE_X(0), PIP_Y(id_S201)},
-          {WIRE_X(9), PIP_Y(id_S201), WIRE_X(9), -1. + PIP_Y(id_S202)},
-          {WIRE_X(9), -1. + PIP_Y(id_S202), WIRE_X(0), -1. + PIP_Y(id_S202)}}},
-        {id_S20_loop1,
-         {{WIRE_X(0), PIP_Y(id_S200), WIRE_X(11), PIP_Y(id_S200)},
-          {WIRE_X(11), PIP_Y(id_S200), WIRE_X(11), -1. + PIP_Y(id_S201)},
-          {WIRE_X(11), -1. + PIP_Y(id_S201), WIRE_X(0), -1. + PIP_Y(id_S201)},
-          {WIRE_X(9), -1. + PIP_Y(id_S201), WIRE_X(9), -1. + -1. * wrap_len},
-          {WIRE_X(9), -1. + -1. * wrap_len, WIRE_X(10), -1. + -1. * wrap_len},
-          {WIRE_X(10), -1. + -1. * wrap_len, WIRE_X(10), -1. + PIP_Y(id_N202)},
-          {WIRE_X(10), -1. + PIP_Y(id_N202), WIRE_X(0), -1. + PIP_Y(id_N202)}}},
-        {id_N20_loop1,
-         {{WIRE_X(0), PIP_Y(id_N200), WIRE_X(12), PIP_Y(id_N200)},
-          {WIRE_X(12), PIP_Y(id_N200), WIRE_X(12), 1. + PIP_Y(id_N201)},
-          {WIRE_X(12), 1. + PIP_Y(id_N201), WIRE_X(0), 1. + PIP_Y(id_N201)},
-          {WIRE_X(10), 1. + PIP_Y(id_N201), WIRE_X(10), 2. + 1. * wrap_len},
-          {WIRE_X(10), 2. + 1. * wrap_len, WIRE_X(9), 2. + 1. * wrap_len},
-          {WIRE_X(9), 2. + 1. * wrap_len, WIRE_X(9), 1. + PIP_Y(id_S202)},
-          {WIRE_X(9), 1. + PIP_Y(id_S202), WIRE_X(0), 1. + PIP_Y(id_S202)}}},
-        {id_S21,
-         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
-          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
-          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
-          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -2. + PIP_Y(id_S212)},
-          {WIRE_X(13), -2. + PIP_Y(id_S212), WIRE_X(0), -2. + PIP_Y(id_S212)}}},
-        {id_N21,
-         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
-          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
-          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
-          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + PIP_Y(id_N212)},
-          {WIRE_X(14), 2. + PIP_Y(id_N212), WIRE_X(0), 2. + PIP_Y(id_N212)}}},
-        {id_S21_loop0,
-         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
-          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. * wrap_len},
-          {WIRE_X(15), -1. * wrap_len, WIRE_X(16), -1. * wrap_len},
-          {WIRE_X(16), -1. * wrap_len, WIRE_X(16), PIP_Y(id_N211)},
-          {WIRE_X(16), PIP_Y(id_N211), WIRE_X(0), PIP_Y(id_N211)},
-          {WIRE_X(14), PIP_Y(id_N211), WIRE_X(14), 1. + PIP_Y(id_N212)},
-          {WIRE_X(14), 1. + PIP_Y(id_N212), WIRE_X(0), 1. + PIP_Y(id_N212)}}},
-        {id_N21_loop0,
-         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
-          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + 1. * wrap_len},
-          {WIRE_X(16), 1. + 1. * wrap_len, WIRE_X(15), 1. + 1. * wrap_len},
-          {WIRE_X(15), 1. + 1. * wrap_len, WIRE_X(15), PIP_Y(id_S211)},
-          {WIRE_X(15), PIP_Y(id_S211), WIRE_X(0), PIP_Y(id_S211)},
-          {WIRE_X(13), PIP_Y(id_S211), WIRE_X(13), -1. + PIP_Y(id_S212)},
-          {WIRE_X(13), -1. + PIP_Y(id_S212), WIRE_X(0), -1. + PIP_Y(id_S212)}}},
-        {id_S21_loop1,
-         {{WIRE_X(0), PIP_Y(id_S210), WIRE_X(15), PIP_Y(id_S210)},
-          {WIRE_X(15), PIP_Y(id_S210), WIRE_X(15), -1. + PIP_Y(id_S211)},
-          {WIRE_X(15), -1. + PIP_Y(id_S211), WIRE_X(0), -1. + PIP_Y(id_S211)},
-          {WIRE_X(13), -1. + PIP_Y(id_S211), WIRE_X(13), -1. + -1. * wrap_len},
-          {WIRE_X(13), -1. + -1. * wrap_len, WIRE_X(14), -1. + -1. * wrap_len},
-          {WIRE_X(14), -1. + -1. * wrap_len, WIRE_X(14), -1. + PIP_Y(id_N212)},
-          {WIRE_X(14), -1. + PIP_Y(id_N212), WIRE_X(0), -1. + PIP_Y(id_N212)}}},
-        {id_N21_loop1,
-         {{WIRE_X(0), PIP_Y(id_N210), WIRE_X(16), PIP_Y(id_N210)},
-          {WIRE_X(16), PIP_Y(id_N210), WIRE_X(16), 1. + PIP_Y(id_N211)},
-          {WIRE_X(16), 1. + PIP_Y(id_N211), WIRE_X(0), 1. + PIP_Y(id_N211)},
-          {WIRE_X(14), 1. + PIP_Y(id_N211), WIRE_X(14), 2. + 1. * wrap_len},
-          {WIRE_X(14), 2. + 1. * wrap_len, WIRE_X(13), 2. + 1. * wrap_len},
-          {WIRE_X(13), 2. + 1. * wrap_len, WIRE_X(13), 1. + PIP_Y(id_S212)},
-          {WIRE_X(13), 1. + PIP_Y(id_S212), WIRE_X(0), 1. + PIP_Y(id_S212)}}},
-        {id_S22,
-         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
-          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
-          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
-          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -2. + PIP_Y(id_S222)},
-          {WIRE_X(17), -2. + PIP_Y(id_S222), WIRE_X(0), -2. + PIP_Y(id_S222)}}},
-        {id_N22,
-         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
-          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
-          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
-          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + PIP_Y(id_N222)},
-          {WIRE_X(18), 2. + PIP_Y(id_N222), WIRE_X(0), 2. + PIP_Y(id_N222)}}},
-        {id_S22_loop0,
-         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
-          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. * wrap_len},
-          {WIRE_X(19), -1. * wrap_len, WIRE_X(20), -1. * wrap_len},
-          {WIRE_X(20), -1. * wrap_len, WIRE_X(20), PIP_Y(id_N221)},
-          {WIRE_X(20), PIP_Y(id_N221), WIRE_X(0), PIP_Y(id_N221)},
-          {WIRE_X(18), PIP_Y(id_N221), WIRE_X(18), 1. + PIP_Y(id_N222)},
-          {WIRE_X(18), 1. + PIP_Y(id_N222), WIRE_X(0), 1. + PIP_Y(id_N222)}}},
-        {id_N22_loop0,
-         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
-          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + 1. * wrap_len},
-          {WIRE_X(20), 1. + 1. * wrap_len, WIRE_X(19), 1. + 1. * wrap_len},
-          {WIRE_X(19), 1. + 1. * wrap_len, WIRE_X(19), PIP_Y(id_S221)},
-          {WIRE_X(19), PIP_Y(id_S221), WIRE_X(0), PIP_Y(id_S221)},
-          {WIRE_X(17), PIP_Y(id_S221), WIRE_X(17), -1. + PIP_Y(id_S222)},
-          {WIRE_X(17), -1. + PIP_Y(id_S222), WIRE_X(0), -1. + PIP_Y(id_S222)}}},
-        {id_S22_loop1,
-         {{WIRE_X(0), PIP_Y(id_S220), WIRE_X(19), PIP_Y(id_S220)},
-          {WIRE_X(19), PIP_Y(id_S220), WIRE_X(19), -1. + PIP_Y(id_S221)},
-          {WIRE_X(19), -1. + PIP_Y(id_S221), WIRE_X(0), -1. + PIP_Y(id_S221)},
-          {WIRE_X(17), -1. + PIP_Y(id_S221), WIRE_X(17), -1. + -1. * wrap_len},
-          {WIRE_X(17), -1. + -1. * wrap_len, WIRE_X(18), -1. + -1. * wrap_len},
-          {WIRE_X(18), -1. + -1. * wrap_len, WIRE_X(18), -1. + PIP_Y(id_N222)},
-          {WIRE_X(18), -1. + PIP_Y(id_N222), WIRE_X(0), -1. + PIP_Y(id_N222)}}},
-        {id_N22_loop1,
-         {{WIRE_X(0), PIP_Y(id_N220), WIRE_X(20), PIP_Y(id_N220)},
-          {WIRE_X(20), PIP_Y(id_N220), WIRE_X(20), 1. + PIP_Y(id_N221)},
-          {WIRE_X(20), 1. + PIP_Y(id_N221), WIRE_X(0), 1. + PIP_Y(id_N221)},
-          {WIRE_X(18), 1. + PIP_Y(id_N221), WIRE_X(18), 2. + 1. * wrap_len},
-          {WIRE_X(18), 2. + 1. * wrap_len, WIRE_X(17), 2. + 1. * wrap_len},
-          {WIRE_X(17), 2. + 1. * wrap_len, WIRE_X(17), 1. + PIP_Y(id_S222)},
-          {WIRE_X(17), 1. + PIP_Y(id_S222), WIRE_X(0), 1. + PIP_Y(id_S222)}}},
-        {id_S23,
-         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
-          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
-          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
-          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -2. + PIP_Y(id_S232)},
-          {WIRE_X(21), -2. + PIP_Y(id_S232), WIRE_X(0), -2. + PIP_Y(id_S232)}}},
-        {id_N23,
-         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
-          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
-          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
-          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + PIP_Y(id_N232)},
-          {WIRE_X(22), 2. + PIP_Y(id_N232), WIRE_X(0), 2. + PIP_Y(id_N232)}}},
-        {id_S23_loop0,
-         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
-          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. * wrap_len},
-          {WIRE_X(23), -1. * wrap_len, WIRE_X(24), -1. * wrap_len},
-          {WIRE_X(24), -1. * wrap_len, WIRE_X(24), PIP_Y(id_N231)},
-          {WIRE_X(24), PIP_Y(id_N231), WIRE_X(0), PIP_Y(id_N231)},
-          {WIRE_X(22), PIP_Y(id_N231), WIRE_X(22), 1. + PIP_Y(id_N232)},
-          {WIRE_X(22), 1. + PIP_Y(id_N232), WIRE_X(0), 1. + PIP_Y(id_N232)}}},
-        {id_N23_loop0,
-         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
-          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + 1. * wrap_len},
-          {WIRE_X(24), 1. + 1. * wrap_len, WIRE_X(23), 1. + 1. * wrap_len},
-          {WIRE_X(23), 1. + 1. * wrap_len, WIRE_X(23), PIP_Y(id_S231)},
-          {WIRE_X(23), PIP_Y(id_S231), WIRE_X(0), PIP_Y(id_S231)},
-          {WIRE_X(21), PIP_Y(id_S231), WIRE_X(21), -1. + PIP_Y(id_S232)},
-          {WIRE_X(21), -1. + PIP_Y(id_S232), WIRE_X(0), -1. + PIP_Y(id_S232)}}},
-        {id_S23_loop1,
-         {{WIRE_X(0), PIP_Y(id_S230), WIRE_X(23), PIP_Y(id_S230)},
-          {WIRE_X(23), PIP_Y(id_S230), WIRE_X(23), -1. + PIP_Y(id_S231)},
-          {WIRE_X(23), -1. + PIP_Y(id_S231), WIRE_X(0), -1. + PIP_Y(id_S231)},
-          {WIRE_X(21), -1. + PIP_Y(id_S231), WIRE_X(21), -1. + -1. * wrap_len},
-          {WIRE_X(21), -1. + -1. * wrap_len, WIRE_X(22), -1. + -1. * wrap_len},
-          {WIRE_X(22), -1. + -1. * wrap_len, WIRE_X(22), -1. + PIP_Y(id_N232)},
-          {WIRE_X(22), -1. + PIP_Y(id_N232), WIRE_X(0), -1. + PIP_Y(id_N232)}}},
-        {id_N23_loop1,
-         {{WIRE_X(0), PIP_Y(id_N230), WIRE_X(24), PIP_Y(id_N230)},
-          {WIRE_X(24), PIP_Y(id_N230), WIRE_X(24), 1. + PIP_Y(id_N231)},
-          {WIRE_X(24), 1. + PIP_Y(id_N231), WIRE_X(0), 1. + PIP_Y(id_N231)},
-          {WIRE_X(22), 1. + PIP_Y(id_N231), WIRE_X(22), 2. + 1. * wrap_len},
-          {WIRE_X(22), 2. + 1. * wrap_len, WIRE_X(21), 2. + 1. * wrap_len},
-          {WIRE_X(21), 2. + 1. * wrap_len, WIRE_X(21), 1. + PIP_Y(id_S232)},
-          {WIRE_X(21), 1. + PIP_Y(id_S232), WIRE_X(0), 1. + PIP_Y(id_S232)}}},
-        {id_S24,
-         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
-          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
-          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
-          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -2. + PIP_Y(id_S242)},
-          {WIRE_X(25), -2. + PIP_Y(id_S242), WIRE_X(0), -2. + PIP_Y(id_S242)}}},
-        {id_N24,
-         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
-          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
-          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
-          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + PIP_Y(id_N242)},
-          {WIRE_X(26), 2. + PIP_Y(id_N242), WIRE_X(0), 2. + PIP_Y(id_N242)}}},
-        {id_S24_loop0,
-         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
-          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. * wrap_len},
-          {WIRE_X(27), -1. * wrap_len, WIRE_X(28), -1. * wrap_len},
-          {WIRE_X(28), -1. * wrap_len, WIRE_X(28), PIP_Y(id_N241)},
-          {WIRE_X(28), PIP_Y(id_N241), WIRE_X(0), PIP_Y(id_N241)},
-          {WIRE_X(26), PIP_Y(id_N241), WIRE_X(26), 1. + PIP_Y(id_N242)},
-          {WIRE_X(26), 1. + PIP_Y(id_N242), WIRE_X(0), 1. + PIP_Y(id_N242)}}},
-        {id_N24_loop0,
-         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
-          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + 1. * wrap_len},
-          {WIRE_X(28), 1. + 1. * wrap_len, WIRE_X(27), 1. + 1. * wrap_len},
-          {WIRE_X(27), 1. + 1. * wrap_len, WIRE_X(27), PIP_Y(id_S241)},
-          {WIRE_X(27), PIP_Y(id_S241), WIRE_X(0), PIP_Y(id_S241)},
-          {WIRE_X(25), PIP_Y(id_S241), WIRE_X(25), -1. + PIP_Y(id_S242)},
-          {WIRE_X(25), -1. + PIP_Y(id_S242), WIRE_X(0), -1. + PIP_Y(id_S242)}}},
-        {id_S24_loop1,
-         {{WIRE_X(0), PIP_Y(id_S240), WIRE_X(27), PIP_Y(id_S240)},
-          {WIRE_X(27), PIP_Y(id_S240), WIRE_X(27), -1. + PIP_Y(id_S241)},
-          {WIRE_X(27), -1. + PIP_Y(id_S241), WIRE_X(0), -1. + PIP_Y(id_S241)},
-          {WIRE_X(25), -1. + PIP_Y(id_S241), WIRE_X(25), -1. + -1. * wrap_len},
-          {WIRE_X(25), -1. + -1. * wrap_len, WIRE_X(26), -1. + -1. * wrap_len},
-          {WIRE_X(26), -1. + -1. * wrap_len, WIRE_X(26), -1. + PIP_Y(id_N242)},
-          {WIRE_X(26), -1. + PIP_Y(id_N242), WIRE_X(0), -1. + PIP_Y(id_N242)}}},
-        {id_N24_loop1,
-         {{WIRE_X(0), PIP_Y(id_N240), WIRE_X(28), PIP_Y(id_N240)},
-          {WIRE_X(28), PIP_Y(id_N240), WIRE_X(28), 1. + PIP_Y(id_N241)},
-          {WIRE_X(28), 1. + PIP_Y(id_N241), WIRE_X(0), 1. + PIP_Y(id_N241)},
-          {WIRE_X(26), 1. + PIP_Y(id_N241), WIRE_X(26), 2. + 1. * wrap_len},
-          {WIRE_X(26), 2. + 1. * wrap_len, WIRE_X(25), 2. + 1. * wrap_len},
-          {WIRE_X(25), 2. + 1. * wrap_len, WIRE_X(25), 1. + PIP_Y(id_S242)},
-          {WIRE_X(25), 1. + PIP_Y(id_S242), WIRE_X(0), 1. + PIP_Y(id_S242)}}},
-        {id_S25,
-         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
-          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
-          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
-          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -2. + PIP_Y(id_S252)},
-          {WIRE_X(29), -2. + PIP_Y(id_S252), WIRE_X(0), -2. + PIP_Y(id_S252)}}},
-        {id_N25,
-         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
-          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
-          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
-          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + PIP_Y(id_N252)},
-          {WIRE_X(30), 2. + PIP_Y(id_N252), WIRE_X(0), 2. + PIP_Y(id_N252)}}},
-        {id_S25_loop0,
-         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
-          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. * wrap_len},
-          {WIRE_X(31), -1. * wrap_len, WIRE_X(32), -1. * wrap_len},
-          {WIRE_X(32), -1. * wrap_len, WIRE_X(32), PIP_Y(id_N251)},
-          {WIRE_X(32), PIP_Y(id_N251), WIRE_X(0), PIP_Y(id_N251)},
-          {WIRE_X(30), PIP_Y(id_N251), WIRE_X(30), 1. + PIP_Y(id_N252)},
-          {WIRE_X(30), 1. + PIP_Y(id_N252), WIRE_X(0), 1. + PIP_Y(id_N252)}}},
-        {id_N25_loop0,
-         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
-          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + 1. * wrap_len},
-          {WIRE_X(32), 1. + 1. * wrap_len, WIRE_X(31), 1. + 1. * wrap_len},
-          {WIRE_X(31), 1. + 1. * wrap_len, WIRE_X(31), PIP_Y(id_S251)},
-          {WIRE_X(31), PIP_Y(id_S251), WIRE_X(0), PIP_Y(id_S251)},
-          {WIRE_X(29), PIP_Y(id_S251), WIRE_X(29), -1. + PIP_Y(id_S252)},
-          {WIRE_X(29), -1. + PIP_Y(id_S252), WIRE_X(0), -1. + PIP_Y(id_S252)}}},
-        {id_S25_loop1,
-         {{WIRE_X(0), PIP_Y(id_S250), WIRE_X(31), PIP_Y(id_S250)},
-          {WIRE_X(31), PIP_Y(id_S250), WIRE_X(31), -1. + PIP_Y(id_S251)},
-          {WIRE_X(31), -1. + PIP_Y(id_S251), WIRE_X(0), -1. + PIP_Y(id_S251)},
-          {WIRE_X(29), -1. + PIP_Y(id_S251), WIRE_X(29), -1. + -1. * wrap_len},
-          {WIRE_X(29), -1. + -1. * wrap_len, WIRE_X(30), -1. + -1. * wrap_len},
-          {WIRE_X(30), -1. + -1. * wrap_len, WIRE_X(30), -1. + PIP_Y(id_N252)},
-          {WIRE_X(30), -1. + PIP_Y(id_N252), WIRE_X(0), -1. + PIP_Y(id_N252)}}},
-        {id_N25_loop1,
-         {{WIRE_X(0), PIP_Y(id_N250), WIRE_X(32), PIP_Y(id_N250)},
-          {WIRE_X(32), PIP_Y(id_N250), WIRE_X(32), 1. + PIP_Y(id_N251)},
-          {WIRE_X(32), 1. + PIP_Y(id_N251), WIRE_X(0), 1. + PIP_Y(id_N251)},
-          {WIRE_X(30), 1. + PIP_Y(id_N251), WIRE_X(30), 2. + 1. * wrap_len},
-          {WIRE_X(30), 2. + 1. * wrap_len, WIRE_X(29), 2. + 1. * wrap_len},
-          {WIRE_X(29), 2. + 1. * wrap_len, WIRE_X(29), 1. + PIP_Y(id_S252)},
-          {WIRE_X(29), 1. + PIP_Y(id_S252), WIRE_X(0), 1. + PIP_Y(id_S252)}}},
-        {id_S26,
-         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
-          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
-          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
-          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -2. + PIP_Y(id_S262)},
-          {WIRE_X(33), -2. + PIP_Y(id_S262), WIRE_X(0), -2. + PIP_Y(id_S262)}}},
-        {id_N26,
-         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
-          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
-          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
-          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + PIP_Y(id_N262)},
-          {WIRE_X(34), 2. + PIP_Y(id_N262), WIRE_X(0), 2. + PIP_Y(id_N262)}}},
-        {id_S26_loop0,
-         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
-          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. * wrap_len},
-          {WIRE_X(35), -1. * wrap_len, WIRE_X(36), -1. * wrap_len},
-          {WIRE_X(36), -1. * wrap_len, WIRE_X(36), PIP_Y(id_N261)},
-          {WIRE_X(36), PIP_Y(id_N261), WIRE_X(0), PIP_Y(id_N261)},
-          {WIRE_X(34), PIP_Y(id_N261), WIRE_X(34), 1. + PIP_Y(id_N262)},
-          {WIRE_X(34), 1. + PIP_Y(id_N262), WIRE_X(0), 1. + PIP_Y(id_N262)}}},
-        {id_N26_loop0,
-         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
-          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + 1. * wrap_len},
-          {WIRE_X(36), 1. + 1. * wrap_len, WIRE_X(35), 1. + 1. * wrap_len},
-          {WIRE_X(35), 1. + 1. * wrap_len, WIRE_X(35), PIP_Y(id_S261)},
-          {WIRE_X(35), PIP_Y(id_S261), WIRE_X(0), PIP_Y(id_S261)},
-          {WIRE_X(33), PIP_Y(id_S261), WIRE_X(33), -1. + PIP_Y(id_S262)},
-          {WIRE_X(33), -1. + PIP_Y(id_S262), WIRE_X(0), -1. + PIP_Y(id_S262)}}},
-        {id_S26_loop1,
-         {{WIRE_X(0), PIP_Y(id_S260), WIRE_X(35), PIP_Y(id_S260)},
-          {WIRE_X(35), PIP_Y(id_S260), WIRE_X(35), -1. + PIP_Y(id_S261)},
-          {WIRE_X(35), -1. + PIP_Y(id_S261), WIRE_X(0), -1. + PIP_Y(id_S261)},
-          {WIRE_X(33), -1. + PIP_Y(id_S261), WIRE_X(33), -1. + -1. * wrap_len},
-          {WIRE_X(33), -1. + -1. * wrap_len, WIRE_X(34), -1. + -1. * wrap_len},
-          {WIRE_X(34), -1. + -1. * wrap_len, WIRE_X(34), -1. + PIP_Y(id_N262)},
-          {WIRE_X(34), -1. + PIP_Y(id_N262), WIRE_X(0), -1. + PIP_Y(id_N262)}}},
-        {id_N26_loop1,
-         {{WIRE_X(0), PIP_Y(id_N260), WIRE_X(36), PIP_Y(id_N260)},
-          {WIRE_X(36), PIP_Y(id_N260), WIRE_X(36), 1. + PIP_Y(id_N261)},
-          {WIRE_X(36), 1. + PIP_Y(id_N261), WIRE_X(0), 1. + PIP_Y(id_N261)},
-          {WIRE_X(34), 1. + PIP_Y(id_N261), WIRE_X(34), 2. + 1. * wrap_len},
-          {WIRE_X(34), 2. + 1. * wrap_len, WIRE_X(33), 2. + 1. * wrap_len},
-          {WIRE_X(33), 2. + 1. * wrap_len, WIRE_X(33), 1. + PIP_Y(id_S262)},
-          {WIRE_X(33), 1. + PIP_Y(id_S262), WIRE_X(0), 1. + PIP_Y(id_S262)}}},
-        {id_S27,
-         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
-          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
-          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
-          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -2. + PIP_Y(id_S272)},
-          {WIRE_X(37), -2. + PIP_Y(id_S272), WIRE_X(0), -2. + PIP_Y(id_S272)}}},
-        {id_N27,
-         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
-          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
-          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
-          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + PIP_Y(id_N272)},
-          {WIRE_X(38), 2. + PIP_Y(id_N272), WIRE_X(0), 2. + PIP_Y(id_N272)}}},
-        {id_S27_loop0,
-         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
-          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. * wrap_len},
-          {WIRE_X(39), -1. * wrap_len, WIRE_X(40), -1. * wrap_len},
-          {WIRE_X(40), -1. * wrap_len, WIRE_X(40), PIP_Y(id_N271)},
-          {WIRE_X(40), PIP_Y(id_N271), WIRE_X(0), PIP_Y(id_N271)},
-          {WIRE_X(38), PIP_Y(id_N271), WIRE_X(38), 1. + PIP_Y(id_N272)},
-          {WIRE_X(38), 1. + PIP_Y(id_N272), WIRE_X(0), 1. + PIP_Y(id_N272)}}},
-        {id_N27_loop0,
-         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
-          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + 1. * wrap_len},
-          {WIRE_X(40), 1. + 1. * wrap_len, WIRE_X(39), 1. + 1. * wrap_len},
-          {WIRE_X(39), 1. + 1. * wrap_len, WIRE_X(39), PIP_Y(id_S271)},
-          {WIRE_X(39), PIP_Y(id_S271), WIRE_X(0), PIP_Y(id_S271)},
-          {WIRE_X(37), PIP_Y(id_S271), WIRE_X(37), -1. + PIP_Y(id_S272)},
-          {WIRE_X(37), -1. + PIP_Y(id_S272), WIRE_X(0), -1. + PIP_Y(id_S272)}}},
-        {id_S27_loop1,
-         {{WIRE_X(0), PIP_Y(id_S270), WIRE_X(39), PIP_Y(id_S270)},
-          {WIRE_X(39), PIP_Y(id_S270), WIRE_X(39), -1. + PIP_Y(id_S271)},
-          {WIRE_X(39), -1. + PIP_Y(id_S271), WIRE_X(0), -1. + PIP_Y(id_S271)},
-          {WIRE_X(37), -1. + PIP_Y(id_S271), WIRE_X(37), -1. + -1. * wrap_len},
-          {WIRE_X(37), -1. + -1. * wrap_len, WIRE_X(38), -1. + -1. * wrap_len},
-          {WIRE_X(38), -1. + -1. * wrap_len, WIRE_X(38), -1. + PIP_Y(id_N272)},
-          {WIRE_X(38), -1. + PIP_Y(id_N272), WIRE_X(0), -1. + PIP_Y(id_N272)}}},
-        {id_N27_loop1,
-         {{WIRE_X(0), PIP_Y(id_N270), WIRE_X(40), PIP_Y(id_N270)},
-          {WIRE_X(40), PIP_Y(id_N270), WIRE_X(40), 1. + PIP_Y(id_N271)},
-          {WIRE_X(40), 1. + PIP_Y(id_N271), WIRE_X(0), 1. + PIP_Y(id_N271)},
-          {WIRE_X(38), 1. + PIP_Y(id_N271), WIRE_X(38), 2. + 1. * wrap_len},
-          {WIRE_X(38), 2. + 1. * wrap_len, WIRE_X(37), 2. + 1. * wrap_len},
-          {WIRE_X(37), 2. + 1. * wrap_len, WIRE_X(37), 1. + PIP_Y(id_S272)},
-          {WIRE_X(37), 1. + PIP_Y(id_S272), WIRE_X(0), 1. + PIP_Y(id_S272)}}},
-// clock taps
-#define CLK_GT00_X 41.f
-#define CLK_GT10_X 46.f
-// 4 hop
-#define HOP4X_START (CLK_GT00_X + 10.f)
-#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START)
-        {id_S80,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
-          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
-          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
-          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
-          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
-          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S808) - 8.},
-          {HOP4X(0), PIP_Y(id_S808) - 8., WIRE_X(0), PIP_Y(id_S808) - 8.}}},
-        {id_N80,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
-          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
-          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
-          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
-          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
-          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N808) + 8.},
-          {HOP4X(1), PIP_Y(id_N808) + 8., WIRE_X(0), PIP_Y(id_N808) + 8.}}},
-        {id_S80_loop0,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
-          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
-          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N800) - 0.},
-          {HOP4X(15), PIP_Y(id_N800) - 0., HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N800) + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N800) + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N800) + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N804) + 3., WIRE_X(0), PIP_Y(id_N804) + 3.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N800) + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N800) + 5.},
-          {HOP4X(5), PIP_Y(id_N800) + 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N800) + 6.},
-          {HOP4X(3), PIP_Y(id_N800) + 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N808) + 7.},
-          {HOP4X(1), PIP_Y(id_N808) + 7., WIRE_X(0), PIP_Y(id_N808) + 7.}}},
-        {id_S80_loop1,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
-          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
-          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N800) - 1.},
-          {HOP4X(13), PIP_Y(id_N800) - 1., HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N800) - 0.},
-          {HOP4X(11), PIP_Y(id_N800) - 0., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N800) + 1.},
-          {HOP4X(9), PIP_Y(id_N800) + 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(9), PIP_Y(id_N804) + 1., WIRE_X(0), PIP_Y(id_N804) + 1.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N800) + 2.},
-          {HOP4X(7), PIP_Y(id_N800) + 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N800) + 3.},
-          {HOP4X(5), PIP_Y(id_N800) + 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N800) + 4.},
-          {HOP4X(3), PIP_Y(id_N800) + 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N808) + 5.},
-          {HOP4X(1), PIP_Y(id_N808) + 5., WIRE_X(0), PIP_Y(id_N808) + 5.}}},
-        {id_S80_loop2,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
-          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
-          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N800) - 2.},
-          {HOP4X(11), PIP_Y(id_N800) - 2., HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N800) - 1.},
-          {HOP4X(9), PIP_Y(id_N800) - 1., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1.},
-          {HOP4X(9), PIP_Y(id_N804) - 1., WIRE_X(0), PIP_Y(id_N804) - 1.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N800) - 0.},
-          {HOP4X(7), PIP_Y(id_N800) - 0., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N800) + 1.},
-          {HOP4X(5), PIP_Y(id_N800) + 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N800) + 2.},
-          {HOP4X(3), PIP_Y(id_N800) + 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N808) + 3.},
-          {HOP4X(1), PIP_Y(id_N808) + 3., WIRE_X(0), PIP_Y(id_N808) + 3.}}},
-        {id_S80_loop3,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
-          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
-          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N800) - 3.},
-          {HOP4X(9), PIP_Y(id_N804) - 3., WIRE_X(0), PIP_Y(id_N804) - 3.},
-          {HOP4X(9), PIP_Y(id_N800) - 3., HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N800) - 2.},
-          {HOP4X(7), PIP_Y(id_N800) - 2., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N800) - 1.},
-          {HOP4X(5), PIP_Y(id_N800) - 1., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N800) - 0.},
-          {HOP4X(3), PIP_Y(id_N800) - 0., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N808) + 1.},
-          {HOP4X(1), PIP_Y(id_N808) + 1., WIRE_X(0), PIP_Y(id_N808) + 1.}}},
-        {id_S80_loop4,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
-          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
-          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
-          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
-          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N800) - 4.},
-          {HOP4X(7), PIP_Y(id_N800) - 4., HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N800) - 3.},
-          {HOP4X(5), PIP_Y(id_N800) - 3., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N800) - 2.},
-          {HOP4X(3), PIP_Y(id_N800) - 2., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N808) - 1.},
-          {HOP4X(1), PIP_Y(id_N808) - 1., WIRE_X(0), PIP_Y(id_N808) - 1.}}},
-        {id_S80_loop5,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
-          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
-          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
-          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
-          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
-          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N800) - 5.},
-          {HOP4X(5), PIP_Y(id_N800) - 5., HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N800) - 4.},
-          {HOP4X(3), PIP_Y(id_N800) - 4., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N808) - 3.},
-          {HOP4X(1), PIP_Y(id_N808) - 3., WIRE_X(0), PIP_Y(id_N808) - 3.}}},
-        {id_S80_loop6,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
-          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
-          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
-          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
-          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
-          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
-          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N800) - 6.},
-          {HOP4X(3), PIP_Y(id_N800) - 6., HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N808) - 5.},
-          {HOP4X(1), PIP_Y(id_N808) - 5., WIRE_X(0), PIP_Y(id_N808) - 5.}}},
-        {id_S80_loop7,
-         {{WIRE_X(0), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_S800)},
-          {HOP4X(16), PIP_Y(id_S800), HOP4X(16), PIP_Y(id_N808)},
-          {HOP4X(16), PIP_Y(id_N808) - 0., HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N808) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N808) - 1.},
-          {HOP4X(14), PIP_Y(id_N808) - 1., HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N808) - 2.},
-          {HOP4X(12), PIP_Y(id_N808) - 2., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N808) - 3.},
-          {HOP4X(10), PIP_Y(id_N808) - 3., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N808) - 4.},
-          {HOP4X(8), PIP_Y(id_S804) - 4., WIRE_X(0), PIP_Y(id_S804) - 4.},
-          {HOP4X(8), PIP_Y(id_N808) - 4., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N808) - 5.},
-          {HOP4X(6), PIP_Y(id_N808) - 5., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N808) - 6.},
-          {HOP4X(4), PIP_Y(id_N808) - 6., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N808) - 7.},
-          {HOP4X(2), PIP_Y(id_N808) - 7., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
-          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
-          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N808) - 7.},
-          {HOP4X(1), PIP_Y(id_N808) - 7., WIRE_X(0), PIP_Y(id_N808) - 7.}}},
-        {id_N80_loop0,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
-          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
-          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N808) + 0.},
-          {HOP4X(14), PIP_Y(id_N808) + 0., HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0.},
-          {HOP4X(12), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N808) - 1.},
-          {HOP4X(12), PIP_Y(id_N808) - 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N808) - 2.},
-          {HOP4X(10), PIP_Y(id_N808) - 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N808) - 3.},
-          {HOP4X(8), PIP_Y(id_S804) - 3., WIRE_X(0), PIP_Y(id_S804) - 3.},
-          {HOP4X(8), PIP_Y(id_N808) - 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N808) - 4.},
-          {HOP4X(6), PIP_Y(id_N808) - 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N808) - 5.},
-          {HOP4X(4), PIP_Y(id_N808) - 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N808) - 6.},
-          {HOP4X(2), PIP_Y(id_N808) - 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S808) - 7.},
-          {HOP4X(0), PIP_Y(id_S808) - 7., WIRE_X(0), PIP_Y(id_S808) - 7.}}},
-        {id_N80_loop1,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
-          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
-          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N808) + 1.},
-          {HOP4X(12), PIP_Y(id_N808) + 1., HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1.},
-          {HOP4X(10), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N808) + 0.},
-          {HOP4X(10), PIP_Y(id_N808) + 0., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N808) - 1.},
-          {HOP4X(8), PIP_Y(id_S804) - 1., WIRE_X(0), PIP_Y(id_S804) - 1.},
-          {HOP4X(8), PIP_Y(id_N808) - 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N808) - 2.},
-          {HOP4X(6), PIP_Y(id_N808) - 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N808) - 3.},
-          {HOP4X(4), PIP_Y(id_N808) - 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N808) - 4.},
-          {HOP4X(2), PIP_Y(id_N808) - 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S808) - 5.},
-          {HOP4X(0), PIP_Y(id_S808) - 5., WIRE_X(0), PIP_Y(id_S808) - 5.}}},
-        {id_N80_loop2,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
-          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
-          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N808) + 2.},
-          {HOP4X(10), PIP_Y(id_N808) + 2., HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2.},
-          {HOP4X(8), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N808) + 1.},
-          {HOP4X(8), PIP_Y(id_S804) + 1., WIRE_X(0), PIP_Y(id_S804) + 1.},
-          {HOP4X(8), PIP_Y(id_N808) + 1., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N808) + 0.},
-          {HOP4X(6), PIP_Y(id_N808) + 0., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N808) - 1.},
-          {HOP4X(4), PIP_Y(id_N808) - 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N808) - 2.},
-          {HOP4X(2), PIP_Y(id_N808) - 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S808) - 3.},
-          {HOP4X(0), PIP_Y(id_S808) - 3., WIRE_X(0), PIP_Y(id_S808) - 3.}}},
-        {id_N80_loop3,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
-          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
-          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N808) + 3.},
-          {HOP4X(8), PIP_Y(id_S804) + 3., WIRE_X(0), PIP_Y(id_S804) + 3.},
-          {HOP4X(8), PIP_Y(id_N808) + 3., HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3.},
-          {HOP4X(6), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N808) + 2.},
-          {HOP4X(6), PIP_Y(id_N808) + 2., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N808) + 1.},
-          {HOP4X(4), PIP_Y(id_N808) + 1., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N808) + 0.},
-          {HOP4X(2), PIP_Y(id_N808) + 0., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S808) - 1.},
-          {HOP4X(0), PIP_Y(id_S808) - 1., WIRE_X(0), PIP_Y(id_S808) - 1.}}},
-        {id_N80_loop4,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
-          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
-          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
-          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
-          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N808) + 4.},
-          {HOP4X(6), PIP_Y(id_N808) + 4., HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4.},
-          {HOP4X(4), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N808) + 3.},
-          {HOP4X(4), PIP_Y(id_N808) + 3., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N808) + 2.},
-          {HOP4X(2), PIP_Y(id_N808) + 2., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S808) + 1.},
-          {HOP4X(0), PIP_Y(id_S808) + 1., WIRE_X(0), PIP_Y(id_S808) + 1.}}},
-        {id_N80_loop5,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
-          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
-          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
-          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
-          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
-          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N808) + 5.},
-          {HOP4X(4), PIP_Y(id_N808) + 5., HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5.},
-          {HOP4X(2), PIP_Y(id_N808) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N808) + 4.},
-          {HOP4X(2), PIP_Y(id_N808) + 4., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S808) + 3.},
-          {HOP4X(0), PIP_Y(id_S808) + 3., WIRE_X(0), PIP_Y(id_S808) + 3.}}},
-        {id_N80_loop6,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
-          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
-          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
-          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
-          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
-          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
-          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N808) + 6.},
-          {HOP4X(2), PIP_Y(id_N808) + 6., HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6.},
-          {HOP4X(0), PIP_Y(id_N808) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S808) + 5.},
-          {HOP4X(0), PIP_Y(id_S808) + 5., WIRE_X(0), PIP_Y(id_S808) + 5.}}},
-        {id_N80_loop7,
-         {{WIRE_X(0), PIP_Y(id_N800), HOP4X(17), PIP_Y(id_N800)},
-          {HOP4X(17), PIP_Y(id_N800) + 0., HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N800) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N800) + 1.},
-          {HOP4X(15), PIP_Y(id_N800) + 1., HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N800) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N800) + 2.},
-          {HOP4X(13), PIP_Y(id_N800) + 2., HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N800) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N800) + 3.},
-          {HOP4X(11), PIP_Y(id_N800) + 3., HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N800) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N800) + 4.},
-          {HOP4X(9), PIP_Y(id_N804) + 4., WIRE_X(0), PIP_Y(id_N804) + 4.},
-          {HOP4X(9), PIP_Y(id_N800) + 4., HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N800) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N800) + 5.},
-          {HOP4X(7), PIP_Y(id_N800) + 5., HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N800) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N800) + 6.},
-          {HOP4X(5), PIP_Y(id_N800) + 6., HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N800) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N800) + 7.},
-          {HOP4X(3), PIP_Y(id_N800) + 7., HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N800) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
-          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
-          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S808) + 7.},
-          {HOP4X(0), PIP_Y(id_S808) + 7., WIRE_X(0), PIP_Y(id_S808) + 7.}}},
-
-#undef HOP4X
-#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f)
-        {id_S81,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
-          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
-          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
-          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
-          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
-          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S818) - 8.},
-          {HOP4X(0), PIP_Y(id_S818) - 8., WIRE_X(0), PIP_Y(id_S818) - 8.}}},
-        {id_N81,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
-          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
-          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
-          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
-          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
-          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N818) + 8.},
-          {HOP4X(1), PIP_Y(id_N818) + 8., WIRE_X(0), PIP_Y(id_N818) + 8.}}},
-        {id_S81_loop0,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
-          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
-          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N810) - 0.},
-          {HOP4X(15), PIP_Y(id_N810) - 0., HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N810) + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N810) + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N810) + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N814) + 3., WIRE_X(0), PIP_Y(id_N814) + 3.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N810) + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N810) + 5.},
-          {HOP4X(5), PIP_Y(id_N810) + 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N810) + 6.},
-          {HOP4X(3), PIP_Y(id_N810) + 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N818) + 7.},
-          {HOP4X(1), PIP_Y(id_N818) + 7., WIRE_X(0), PIP_Y(id_N818) + 7.}}},
-        {id_S81_loop1,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
-          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
-          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N810) - 1.},
-          {HOP4X(13), PIP_Y(id_N810) - 1., HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N810) - 0.},
-          {HOP4X(11), PIP_Y(id_N810) - 0., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N810) + 1.},
-          {HOP4X(9), PIP_Y(id_N810) + 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(9), PIP_Y(id_N814) + 1., WIRE_X(0), PIP_Y(id_N814) + 1.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N810) + 2.},
-          {HOP4X(7), PIP_Y(id_N810) + 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N810) + 3.},
-          {HOP4X(5), PIP_Y(id_N810) + 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N810) + 4.},
-          {HOP4X(3), PIP_Y(id_N810) + 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N818) + 5.},
-          {HOP4X(1), PIP_Y(id_N818) + 5., WIRE_X(0), PIP_Y(id_N818) + 5.}}},
-        {id_S81_loop2,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
-          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
-          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N810) - 2.},
-          {HOP4X(11), PIP_Y(id_N810) - 2., HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N810) - 1.},
-          {HOP4X(9), PIP_Y(id_N810) - 1., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1.},
-          {HOP4X(9), PIP_Y(id_N814) - 1., WIRE_X(0), PIP_Y(id_N814) - 1.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N810) - 0.},
-          {HOP4X(7), PIP_Y(id_N810) - 0., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N810) + 1.},
-          {HOP4X(5), PIP_Y(id_N810) + 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N810) + 2.},
-          {HOP4X(3), PIP_Y(id_N810) + 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N818) + 3.},
-          {HOP4X(1), PIP_Y(id_N818) + 3., WIRE_X(0), PIP_Y(id_N818) + 3.}}},
-        {id_S81_loop3,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
-          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
-          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N810) - 3.},
-          {HOP4X(9), PIP_Y(id_N814) - 3., WIRE_X(0), PIP_Y(id_N814) - 3.},
-          {HOP4X(9), PIP_Y(id_N810) - 3., HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N810) - 2.},
-          {HOP4X(7), PIP_Y(id_N810) - 2., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N810) - 1.},
-          {HOP4X(5), PIP_Y(id_N810) - 1., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N810) - 0.},
-          {HOP4X(3), PIP_Y(id_N810) - 0., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N818) + 1.},
-          {HOP4X(1), PIP_Y(id_N818) + 1., WIRE_X(0), PIP_Y(id_N818) + 1.}}},
-        {id_S81_loop4,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
-          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
-          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
-          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
-          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N810) - 4.},
-          {HOP4X(7), PIP_Y(id_N810) - 4., HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N810) - 3.},
-          {HOP4X(5), PIP_Y(id_N810) - 3., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N810) - 2.},
-          {HOP4X(3), PIP_Y(id_N810) - 2., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N818) - 1.},
-          {HOP4X(1), PIP_Y(id_N818) - 1., WIRE_X(0), PIP_Y(id_N818) - 1.}}},
-        {id_S81_loop5,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
-          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
-          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
-          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
-          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
-          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N810) - 5.},
-          {HOP4X(5), PIP_Y(id_N810) - 5., HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N810) - 4.},
-          {HOP4X(3), PIP_Y(id_N810) - 4., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N818) - 3.},
-          {HOP4X(1), PIP_Y(id_N818) - 3., WIRE_X(0), PIP_Y(id_N818) - 3.}}},
-        {id_S81_loop6,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
-          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
-          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
-          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
-          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
-          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
-          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N810) - 6.},
-          {HOP4X(3), PIP_Y(id_N810) - 6., HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N818) - 5.},
-          {HOP4X(1), PIP_Y(id_N818) - 5., WIRE_X(0), PIP_Y(id_N818) - 5.}}},
-        {id_S81_loop7,
-         {{WIRE_X(0), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_S810)},
-          {HOP4X(16), PIP_Y(id_S810), HOP4X(16), PIP_Y(id_N818)},
-          {HOP4X(16), PIP_Y(id_N818) - 0., HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N818) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N818) - 1.},
-          {HOP4X(14), PIP_Y(id_N818) - 1., HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N818) - 2.},
-          {HOP4X(12), PIP_Y(id_N818) - 2., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N818) - 3.},
-          {HOP4X(10), PIP_Y(id_N818) - 3., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N818) - 4.},
-          {HOP4X(8), PIP_Y(id_S814) - 4., WIRE_X(0), PIP_Y(id_S814) - 4.},
-          {HOP4X(8), PIP_Y(id_N818) - 4., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N818) - 5.},
-          {HOP4X(6), PIP_Y(id_N818) - 5., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N818) - 6.},
-          {HOP4X(4), PIP_Y(id_N818) - 6., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N818) - 7.},
-          {HOP4X(2), PIP_Y(id_N818) - 7., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
-          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
-          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N818) - 7.},
-          {HOP4X(1), PIP_Y(id_N818) - 7., WIRE_X(0), PIP_Y(id_N818) - 7.}}},
-        {id_N81_loop0,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
-          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
-          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N818) + 0.},
-          {HOP4X(14), PIP_Y(id_N818) + 0., HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0.},
-          {HOP4X(12), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N818) - 1.},
-          {HOP4X(12), PIP_Y(id_N818) - 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N818) - 2.},
-          {HOP4X(10), PIP_Y(id_N818) - 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N818) - 3.},
-          {HOP4X(8), PIP_Y(id_S814) - 3., WIRE_X(0), PIP_Y(id_S814) - 3.},
-          {HOP4X(8), PIP_Y(id_N818) - 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N818) - 4.},
-          {HOP4X(6), PIP_Y(id_N818) - 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N818) - 5.},
-          {HOP4X(4), PIP_Y(id_N818) - 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N818) - 6.},
-          {HOP4X(2), PIP_Y(id_N818) - 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S818) - 7.},
-          {HOP4X(0), PIP_Y(id_S818) - 7., WIRE_X(0), PIP_Y(id_S818) - 7.}}},
-        {id_N81_loop1,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
-          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
-          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N818) + 1.},
-          {HOP4X(12), PIP_Y(id_N818) + 1., HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1.},
-          {HOP4X(10), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N818) + 0.},
-          {HOP4X(10), PIP_Y(id_N818) + 0., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N818) - 1.},
-          {HOP4X(8), PIP_Y(id_S814) - 1., WIRE_X(0), PIP_Y(id_S814) - 1.},
-          {HOP4X(8), PIP_Y(id_N818) - 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N818) - 2.},
-          {HOP4X(6), PIP_Y(id_N818) - 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N818) - 3.},
-          {HOP4X(4), PIP_Y(id_N818) - 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N818) - 4.},
-          {HOP4X(2), PIP_Y(id_N818) - 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S818) - 5.},
-          {HOP4X(0), PIP_Y(id_S818) - 5., WIRE_X(0), PIP_Y(id_S818) - 5.}}},
-        {id_N81_loop2,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
-          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
-          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N818) + 2.},
-          {HOP4X(10), PIP_Y(id_N818) + 2., HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2.},
-          {HOP4X(8), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N818) + 1.},
-          {HOP4X(8), PIP_Y(id_S814) + 1., WIRE_X(0), PIP_Y(id_S814) + 1.},
-          {HOP4X(8), PIP_Y(id_N818) + 1., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N818) + 0.},
-          {HOP4X(6), PIP_Y(id_N818) + 0., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N818) - 1.},
-          {HOP4X(4), PIP_Y(id_N818) - 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N818) - 2.},
-          {HOP4X(2), PIP_Y(id_N818) - 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S818) - 3.},
-          {HOP4X(0), PIP_Y(id_S818) - 3., WIRE_X(0), PIP_Y(id_S818) - 3.}}},
-        {id_N81_loop3,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
-          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
-          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N818) + 3.},
-          {HOP4X(8), PIP_Y(id_S814) + 3., WIRE_X(0), PIP_Y(id_S814) + 3.},
-          {HOP4X(8), PIP_Y(id_N818) + 3., HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3.},
-          {HOP4X(6), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N818) + 2.},
-          {HOP4X(6), PIP_Y(id_N818) + 2., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N818) + 1.},
-          {HOP4X(4), PIP_Y(id_N818) + 1., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N818) + 0.},
-          {HOP4X(2), PIP_Y(id_N818) + 0., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S818) - 1.},
-          {HOP4X(0), PIP_Y(id_S818) - 1., WIRE_X(0), PIP_Y(id_S818) - 1.}}},
-        {id_N81_loop4,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
-          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
-          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
-          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
-          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N818) + 4.},
-          {HOP4X(6), PIP_Y(id_N818) + 4., HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4.},
-          {HOP4X(4), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N818) + 3.},
-          {HOP4X(4), PIP_Y(id_N818) + 3., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N818) + 2.},
-          {HOP4X(2), PIP_Y(id_N818) + 2., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S818) + 1.},
-          {HOP4X(0), PIP_Y(id_S818) + 1., WIRE_X(0), PIP_Y(id_S818) + 1.}}},
-        {id_N81_loop5,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
-          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
-          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
-          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
-          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
-          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N818) + 5.},
-          {HOP4X(4), PIP_Y(id_N818) + 5., HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5.},
-          {HOP4X(2), PIP_Y(id_N818) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N818) + 4.},
-          {HOP4X(2), PIP_Y(id_N818) + 4., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S818) + 3.},
-          {HOP4X(0), PIP_Y(id_S818) + 3., WIRE_X(0), PIP_Y(id_S818) + 3.}}},
-        {id_N81_loop6,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
-          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
-          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
-          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
-          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
-          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
-          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N818) + 6.},
-          {HOP4X(2), PIP_Y(id_N818) + 6., HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6.},
-          {HOP4X(0), PIP_Y(id_N818) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S818) + 5.},
-          {HOP4X(0), PIP_Y(id_S818) + 5., WIRE_X(0), PIP_Y(id_S818) + 5.}}},
-        {id_N81_loop7,
-         {{WIRE_X(0), PIP_Y(id_N810), HOP4X(17), PIP_Y(id_N810)},
-          {HOP4X(17), PIP_Y(id_N810) + 0., HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N810) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N810) + 1.},
-          {HOP4X(15), PIP_Y(id_N810) + 1., HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N810) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N810) + 2.},
-          {HOP4X(13), PIP_Y(id_N810) + 2., HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N810) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N810) + 3.},
-          {HOP4X(11), PIP_Y(id_N810) + 3., HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N810) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N810) + 4.},
-          {HOP4X(9), PIP_Y(id_N814) + 4., WIRE_X(0), PIP_Y(id_N814) + 4.},
-          {HOP4X(9), PIP_Y(id_N810) + 4., HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N810) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N810) + 5.},
-          {HOP4X(7), PIP_Y(id_N810) + 5., HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N810) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N810) + 6.},
-          {HOP4X(5), PIP_Y(id_N810) + 6., HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N810) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N810) + 7.},
-          {HOP4X(3), PIP_Y(id_N810) + 7., HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N810) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
-          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
-          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S818) + 7.},
-          {HOP4X(0), PIP_Y(id_S818) + 7., WIRE_X(0), PIP_Y(id_S818) + 7.}}},
-
-#undef HOP4X
-#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f)
-        {id_S82,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
-          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
-          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
-          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
-          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
-          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S828) - 8.},
-          {HOP4X(0), PIP_Y(id_S828) - 8., WIRE_X(0), PIP_Y(id_S828) - 8.}}},
-        {id_N82,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
-          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
-          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
-          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
-          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
-          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N828) + 8.},
-          {HOP4X(1), PIP_Y(id_N828) + 8., WIRE_X(0), PIP_Y(id_N828) + 8.}}},
-        {id_S82_loop0,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
-          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
-          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N820) - 0.},
-          {HOP4X(15), PIP_Y(id_N820) - 0., HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N820) + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N820) + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N820) + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N824) + 3., WIRE_X(0), PIP_Y(id_N824) + 3.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N820) + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N820) + 5.},
-          {HOP4X(5), PIP_Y(id_N820) + 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N820) + 6.},
-          {HOP4X(3), PIP_Y(id_N820) + 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N828) + 7.},
-          {HOP4X(1), PIP_Y(id_N828) + 7., WIRE_X(0), PIP_Y(id_N828) + 7.}}},
-        {id_S82_loop1,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
-          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
-          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N820) - 1.},
-          {HOP4X(13), PIP_Y(id_N820) - 1., HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N820) - 0.},
-          {HOP4X(11), PIP_Y(id_N820) - 0., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N820) + 1.},
-          {HOP4X(9), PIP_Y(id_N820) + 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(9), PIP_Y(id_N824) + 1., WIRE_X(0), PIP_Y(id_N824) + 1.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N820) + 2.},
-          {HOP4X(7), PIP_Y(id_N820) + 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N820) + 3.},
-          {HOP4X(5), PIP_Y(id_N820) + 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N820) + 4.},
-          {HOP4X(3), PIP_Y(id_N820) + 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N828) + 5.},
-          {HOP4X(1), PIP_Y(id_N828) + 5., WIRE_X(0), PIP_Y(id_N828) + 5.}}},
-        {id_S82_loop2,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
-          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
-          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N820) - 2.},
-          {HOP4X(11), PIP_Y(id_N820) - 2., HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N820) - 1.},
-          {HOP4X(9), PIP_Y(id_N820) - 1., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1.},
-          {HOP4X(9), PIP_Y(id_N824) - 1., WIRE_X(0), PIP_Y(id_N824) - 1.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N820) - 0.},
-          {HOP4X(7), PIP_Y(id_N820) - 0., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N820) + 1.},
-          {HOP4X(5), PIP_Y(id_N820) + 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N820) + 2.},
-          {HOP4X(3), PIP_Y(id_N820) + 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N828) + 3.},
-          {HOP4X(1), PIP_Y(id_N828) + 3., WIRE_X(0), PIP_Y(id_N828) + 3.}}},
-        {id_S82_loop3,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
-          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
-          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N820) - 3.},
-          {HOP4X(9), PIP_Y(id_N824) - 3., WIRE_X(0), PIP_Y(id_N824) - 3.},
-          {HOP4X(9), PIP_Y(id_N820) - 3., HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N820) - 2.},
-          {HOP4X(7), PIP_Y(id_N820) - 2., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N820) - 1.},
-          {HOP4X(5), PIP_Y(id_N820) - 1., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N820) - 0.},
-          {HOP4X(3), PIP_Y(id_N820) - 0., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N828) + 1.},
-          {HOP4X(1), PIP_Y(id_N828) + 1., WIRE_X(0), PIP_Y(id_N828) + 1.}}},
-        {id_S82_loop4,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
-          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
-          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
-          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
-          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N820) - 4.},
-          {HOP4X(7), PIP_Y(id_N820) - 4., HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N820) - 3.},
-          {HOP4X(5), PIP_Y(id_N820) - 3., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N820) - 2.},
-          {HOP4X(3), PIP_Y(id_N820) - 2., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N828) - 1.},
-          {HOP4X(1), PIP_Y(id_N828) - 1., WIRE_X(0), PIP_Y(id_N828) - 1.}}},
-        {id_S82_loop5,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
-          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
-          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
-          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
-          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
-          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N820) - 5.},
-          {HOP4X(5), PIP_Y(id_N820) - 5., HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N820) - 4.},
-          {HOP4X(3), PIP_Y(id_N820) - 4., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N828) - 3.},
-          {HOP4X(1), PIP_Y(id_N828) - 3., WIRE_X(0), PIP_Y(id_N828) - 3.}}},
-        {id_S82_loop6,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
-          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
-          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
-          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
-          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
-          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
-          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N820) - 6.},
-          {HOP4X(3), PIP_Y(id_N820) - 6., HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N828) - 5.},
-          {HOP4X(1), PIP_Y(id_N828) - 5., WIRE_X(0), PIP_Y(id_N828) - 5.}}},
-        {id_S82_loop7,
-         {{WIRE_X(0), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_S820)},
-          {HOP4X(16), PIP_Y(id_S820), HOP4X(16), PIP_Y(id_N828)},
-          {HOP4X(16), PIP_Y(id_N828) - 0., HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N828) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N828) - 1.},
-          {HOP4X(14), PIP_Y(id_N828) - 1., HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N828) - 2.},
-          {HOP4X(12), PIP_Y(id_N828) - 2., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N828) - 3.},
-          {HOP4X(10), PIP_Y(id_N828) - 3., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N828) - 4.},
-          {HOP4X(8), PIP_Y(id_S824) - 4., WIRE_X(0), PIP_Y(id_S824) - 4.},
-          {HOP4X(8), PIP_Y(id_N828) - 4., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N828) - 5.},
-          {HOP4X(6), PIP_Y(id_N828) - 5., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N828) - 6.},
-          {HOP4X(4), PIP_Y(id_N828) - 6., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N828) - 7.},
-          {HOP4X(2), PIP_Y(id_N828) - 7., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
-          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
-          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N828) - 7.},
-          {HOP4X(1), PIP_Y(id_N828) - 7., WIRE_X(0), PIP_Y(id_N828) - 7.}}},
-        {id_N82_loop0,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
-          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
-          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N828) + 0.},
-          {HOP4X(14), PIP_Y(id_N828) + 0., HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0.},
-          {HOP4X(12), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N828) - 1.},
-          {HOP4X(12), PIP_Y(id_N828) - 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N828) - 2.},
-          {HOP4X(10), PIP_Y(id_N828) - 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N828) - 3.},
-          {HOP4X(8), PIP_Y(id_S824) - 3., WIRE_X(0), PIP_Y(id_S824) - 3.},
-          {HOP4X(8), PIP_Y(id_N828) - 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N828) - 4.},
-          {HOP4X(6), PIP_Y(id_N828) - 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N828) - 5.},
-          {HOP4X(4), PIP_Y(id_N828) - 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N828) - 6.},
-          {HOP4X(2), PIP_Y(id_N828) - 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S828) - 7.},
-          {HOP4X(0), PIP_Y(id_S828) - 7., WIRE_X(0), PIP_Y(id_S828) - 7.}}},
-        {id_N82_loop1,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
-          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
-          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N828) + 1.},
-          {HOP4X(12), PIP_Y(id_N828) + 1., HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1.},
-          {HOP4X(10), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N828) + 0.},
-          {HOP4X(10), PIP_Y(id_N828) + 0., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N828) - 1.},
-          {HOP4X(8), PIP_Y(id_S824) - 1., WIRE_X(0), PIP_Y(id_S824) - 1.},
-          {HOP4X(8), PIP_Y(id_N828) - 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N828) - 2.},
-          {HOP4X(6), PIP_Y(id_N828) - 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N828) - 3.},
-          {HOP4X(4), PIP_Y(id_N828) - 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N828) - 4.},
-          {HOP4X(2), PIP_Y(id_N828) - 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S828) - 5.},
-          {HOP4X(0), PIP_Y(id_S828) - 5., WIRE_X(0), PIP_Y(id_S828) - 5.}}},
-        {id_N82_loop2,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
-          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
-          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N828) + 2.},
-          {HOP4X(10), PIP_Y(id_N828) + 2., HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2.},
-          {HOP4X(8), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N828) + 1.},
-          {HOP4X(8), PIP_Y(id_S824) + 1., WIRE_X(0), PIP_Y(id_S824) + 1.},
-          {HOP4X(8), PIP_Y(id_N828) + 1., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N828) + 0.},
-          {HOP4X(6), PIP_Y(id_N828) + 0., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N828) - 1.},
-          {HOP4X(4), PIP_Y(id_N828) - 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N828) - 2.},
-          {HOP4X(2), PIP_Y(id_N828) - 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S828) - 3.},
-          {HOP4X(0), PIP_Y(id_S828) - 3., WIRE_X(0), PIP_Y(id_S828) - 3.}}},
-        {id_N82_loop3,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
-          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
-          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N828) + 3.},
-          {HOP4X(8), PIP_Y(id_S824) + 3., WIRE_X(0), PIP_Y(id_S824) + 3.},
-          {HOP4X(8), PIP_Y(id_N828) + 3., HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3.},
-          {HOP4X(6), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N828) + 2.},
-          {HOP4X(6), PIP_Y(id_N828) + 2., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N828) + 1.},
-          {HOP4X(4), PIP_Y(id_N828) + 1., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N828) + 0.},
-          {HOP4X(2), PIP_Y(id_N828) + 0., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S828) - 1.},
-          {HOP4X(0), PIP_Y(id_S828) - 1., WIRE_X(0), PIP_Y(id_S828) - 1.}}},
-        {id_N82_loop4,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
-          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
-          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
-          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
-          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N828) + 4.},
-          {HOP4X(6), PIP_Y(id_N828) + 4., HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4.},
-          {HOP4X(4), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N828) + 3.},
-          {HOP4X(4), PIP_Y(id_N828) + 3., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N828) + 2.},
-          {HOP4X(2), PIP_Y(id_N828) + 2., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S828) + 1.},
-          {HOP4X(0), PIP_Y(id_S828) + 1., WIRE_X(0), PIP_Y(id_S828) + 1.}}},
-        {id_N82_loop5,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
-          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
-          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
-          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
-          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
-          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N828) + 5.},
-          {HOP4X(4), PIP_Y(id_N828) + 5., HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5.},
-          {HOP4X(2), PIP_Y(id_N828) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N828) + 4.},
-          {HOP4X(2), PIP_Y(id_N828) + 4., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S828) + 3.},
-          {HOP4X(0), PIP_Y(id_S828) + 3., WIRE_X(0), PIP_Y(id_S828) + 3.}}},
-        {id_N82_loop6,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
-          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
-          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
-          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
-          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
-          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
-          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N828) + 6.},
-          {HOP4X(2), PIP_Y(id_N828) + 6., HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6.},
-          {HOP4X(0), PIP_Y(id_N828) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S828) + 5.},
-          {HOP4X(0), PIP_Y(id_S828) + 5., WIRE_X(0), PIP_Y(id_S828) + 5.}}},
-        {id_N82_loop7,
-         {{WIRE_X(0), PIP_Y(id_N820), HOP4X(17), PIP_Y(id_N820)},
-          {HOP4X(17), PIP_Y(id_N820) + 0., HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N820) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N820) + 1.},
-          {HOP4X(15), PIP_Y(id_N820) + 1., HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N820) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N820) + 2.},
-          {HOP4X(13), PIP_Y(id_N820) + 2., HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N820) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N820) + 3.},
-          {HOP4X(11), PIP_Y(id_N820) + 3., HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N820) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N820) + 4.},
-          {HOP4X(9), PIP_Y(id_N824) + 4., WIRE_X(0), PIP_Y(id_N824) + 4.},
-          {HOP4X(9), PIP_Y(id_N820) + 4., HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N820) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N820) + 5.},
-          {HOP4X(7), PIP_Y(id_N820) + 5., HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N820) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N820) + 6.},
-          {HOP4X(5), PIP_Y(id_N820) + 6., HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N820) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N820) + 7.},
-          {HOP4X(3), PIP_Y(id_N820) + 7., HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N820) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
-          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
-          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S828) + 7.},
-          {HOP4X(0), PIP_Y(id_S828) + 7., WIRE_X(0), PIP_Y(id_S828) + 7.}}},
-
-#undef HOP4X
-#define HOP4X(offset) WIRE_X((float)offset + HOP4X_START + 18.f + 18.f + 18.f)
-        {id_S83,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
-          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
-          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
-          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
-          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
-          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), PIP_Y(id_S838) - 8.},
-          {HOP4X(0), PIP_Y(id_S838) - 8., WIRE_X(0), PIP_Y(id_S838) - 8.}}},
-        {id_N83,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
-          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
-          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
-          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
-          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
-          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), PIP_Y(id_N838) + 8.},
-          {HOP4X(1), PIP_Y(id_N838) + 8., WIRE_X(0), PIP_Y(id_N838) + 8.}}},
-        {id_S83_loop0,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), -wrap_len - 0.},
-          {HOP4X(14), -wrap_len - 0., HOP4X(15), -wrap_len - 0.},
-          {HOP4X(15), -wrap_len - 0., HOP4X(15), PIP_Y(id_N830) - 0.},
-          {HOP4X(15), PIP_Y(id_N830) - 0., HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(13), PIP_Y(id_N830) + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(11), PIP_Y(id_N830) + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(9), PIP_Y(id_N830) + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N834) + 3., WIRE_X(0), PIP_Y(id_N834) + 3.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(7), PIP_Y(id_N830) + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(5), PIP_Y(id_N830) + 5.},
-          {HOP4X(5), PIP_Y(id_N830) + 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(3), PIP_Y(id_N830) + 6.},
-          {HOP4X(3), PIP_Y(id_N830) + 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(1), PIP_Y(id_N838) + 7.},
-          {HOP4X(1), PIP_Y(id_N838) + 7., WIRE_X(0), PIP_Y(id_N838) + 7.}}},
-        {id_S83_loop1,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), -wrap_len - 1.},
-          {HOP4X(12), -wrap_len - 1., HOP4X(13), -wrap_len - 1.},
-          {HOP4X(13), -wrap_len - 1., HOP4X(13), PIP_Y(id_N830) - 1.},
-          {HOP4X(13), PIP_Y(id_N830) - 1., HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(11), PIP_Y(id_N830) - 0.},
-          {HOP4X(11), PIP_Y(id_N830) - 0., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(9), PIP_Y(id_N830) + 1.},
-          {HOP4X(9), PIP_Y(id_N830) + 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(9), PIP_Y(id_N834) + 1., WIRE_X(0), PIP_Y(id_N834) + 1.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(7), PIP_Y(id_N830) + 2.},
-          {HOP4X(7), PIP_Y(id_N830) + 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(5), PIP_Y(id_N830) + 3.},
-          {HOP4X(5), PIP_Y(id_N830) + 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(3), PIP_Y(id_N830) + 4.},
-          {HOP4X(3), PIP_Y(id_N830) + 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(1), PIP_Y(id_N838) + 5.},
-          {HOP4X(1), PIP_Y(id_N838) + 5., WIRE_X(0), PIP_Y(id_N838) + 5.}}},
-        {id_S83_loop2,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), -wrap_len - 2.},
-          {HOP4X(10), -wrap_len - 2., HOP4X(11), -wrap_len - 2.},
-          {HOP4X(11), -wrap_len - 2., HOP4X(11), PIP_Y(id_N830) - 2.},
-          {HOP4X(11), PIP_Y(id_N830) - 2., HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(9), PIP_Y(id_N830) - 1.},
-          {HOP4X(9), PIP_Y(id_N830) - 1., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1.},
-          {HOP4X(9), PIP_Y(id_N834) - 1., WIRE_X(0), PIP_Y(id_N834) - 1.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(7), PIP_Y(id_N830) - 0.},
-          {HOP4X(7), PIP_Y(id_N830) - 0., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(5), PIP_Y(id_N830) + 1.},
-          {HOP4X(5), PIP_Y(id_N830) + 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(3), PIP_Y(id_N830) + 2.},
-          {HOP4X(3), PIP_Y(id_N830) + 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(1), PIP_Y(id_N838) + 3.},
-          {HOP4X(1), PIP_Y(id_N838) + 3., WIRE_X(0), PIP_Y(id_N838) + 3.}}},
-        {id_S83_loop3,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), -wrap_len - 3.},
-          {HOP4X(8), -wrap_len - 3., HOP4X(9), -wrap_len - 3.},
-          {HOP4X(9), -wrap_len - 3., HOP4X(9), PIP_Y(id_N830) - 3.},
-          {HOP4X(9), PIP_Y(id_N834) - 3., WIRE_X(0), PIP_Y(id_N834) - 3.},
-          {HOP4X(9), PIP_Y(id_N830) - 3., HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(7), PIP_Y(id_N830) - 2.},
-          {HOP4X(7), PIP_Y(id_N830) - 2., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(5), PIP_Y(id_N830) - 1.},
-          {HOP4X(5), PIP_Y(id_N830) - 1., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 1., HOP4X(3), PIP_Y(id_N830) - 0.},
-          {HOP4X(3), PIP_Y(id_N830) - 0., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 0., HOP4X(1), PIP_Y(id_N838) + 1.},
-          {HOP4X(1), PIP_Y(id_N838) + 1., WIRE_X(0), PIP_Y(id_N838) + 1.}}},
-        {id_S83_loop4,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
-          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
-          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), -wrap_len - 4.},
-          {HOP4X(6), -wrap_len - 4., HOP4X(7), -wrap_len - 4.},
-          {HOP4X(7), -wrap_len - 4., HOP4X(7), PIP_Y(id_N830) - 4.},
-          {HOP4X(7), PIP_Y(id_N830) - 4., HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(5), PIP_Y(id_N830) - 3.},
-          {HOP4X(5), PIP_Y(id_N830) - 3., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 3., HOP4X(3), PIP_Y(id_N830) - 2.},
-          {HOP4X(3), PIP_Y(id_N830) - 2., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 2., HOP4X(1), PIP_Y(id_N838) - 1.},
-          {HOP4X(1), PIP_Y(id_N838) - 1., WIRE_X(0), PIP_Y(id_N838) - 1.}}},
-        {id_S83_loop5,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
-          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
-          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
-          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), -wrap_len - 5.},
-          {HOP4X(4), -wrap_len - 5., HOP4X(5), -wrap_len - 5.},
-          {HOP4X(5), -wrap_len - 5., HOP4X(5), PIP_Y(id_N830) - 5.},
-          {HOP4X(5), PIP_Y(id_N830) - 5., HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist - 5., HOP4X(3), PIP_Y(id_N830) - 4.},
-          {HOP4X(3), PIP_Y(id_N830) - 4., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 4., HOP4X(1), PIP_Y(id_N838) - 3.},
-          {HOP4X(1), PIP_Y(id_N838) - 3., WIRE_X(0), PIP_Y(id_N838) - 3.}}},
-        {id_S83_loop6,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
-          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
-          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
-          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
-          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), -wrap_len - 6.},
-          {HOP4X(2), -wrap_len - 6., HOP4X(3), -wrap_len - 6.},
-          {HOP4X(3), -wrap_len - 6., HOP4X(3), PIP_Y(id_N830) - 6.},
-          {HOP4X(3), PIP_Y(id_N830) - 6., HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist - 6., HOP4X(1), PIP_Y(id_N838) - 5.},
-          {HOP4X(1), PIP_Y(id_N838) - 5., WIRE_X(0), PIP_Y(id_N838) - 5.}}},
-        {id_S83_loop7,
-         {{WIRE_X(0), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_S830)},
-          {HOP4X(16), PIP_Y(id_S830), HOP4X(16), PIP_Y(id_N838)},
-          {HOP4X(16), PIP_Y(id_N838) - 0., HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0.},
-          {HOP4X(14), PIP_Y(id_N838) - left_wire_dist - 0., HOP4X(14), PIP_Y(id_N838) - 1.},
-          {HOP4X(14), PIP_Y(id_N838) - 1., HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(12), PIP_Y(id_N838) - 2.},
-          {HOP4X(12), PIP_Y(id_N838) - 2., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(10), PIP_Y(id_N838) - 3.},
-          {HOP4X(10), PIP_Y(id_N838) - 3., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(8), PIP_Y(id_N838) - 4.},
-          {HOP4X(8), PIP_Y(id_S834) - 4., WIRE_X(0), PIP_Y(id_S834) - 4.},
-          {HOP4X(8), PIP_Y(id_N838) - 4., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(6), PIP_Y(id_N838) - 5.},
-          {HOP4X(6), PIP_Y(id_N838) - 5., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(4), PIP_Y(id_N838) - 6.},
-          {HOP4X(4), PIP_Y(id_N838) - 6., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(2), PIP_Y(id_N838) - 7.},
-          {HOP4X(2), PIP_Y(id_N838) - 7., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 7., HOP4X(0), -wrap_len - 7.},
-          {HOP4X(0), -wrap_len - 7., HOP4X(1), -wrap_len - 7.},
-          {HOP4X(1), -wrap_len - 7., HOP4X(1), PIP_Y(id_N838) - 7.},
-          {HOP4X(1), PIP_Y(id_N838) - 7., WIRE_X(0), PIP_Y(id_N838) - 7.}}},
-        {id_N83_loop0,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), wrap_len + 1.},
-          {HOP4X(15), wrap_len + 1., HOP4X(14), wrap_len + 1.},
-          {HOP4X(14), wrap_len + 1., HOP4X(14), PIP_Y(id_N838) + 0.},
-          {HOP4X(14), PIP_Y(id_N838) + 0., HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0.},
-          {HOP4X(12), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(12), PIP_Y(id_N838) - 1.},
-          {HOP4X(12), PIP_Y(id_N838) - 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(10), PIP_Y(id_N838) - 2.},
-          {HOP4X(10), PIP_Y(id_N838) - 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(8), PIP_Y(id_N838) - 3.},
-          {HOP4X(8), PIP_Y(id_S834) - 3., WIRE_X(0), PIP_Y(id_S834) - 3.},
-          {HOP4X(8), PIP_Y(id_N838) - 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(6), PIP_Y(id_N838) - 4.},
-          {HOP4X(6), PIP_Y(id_N838) - 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(4), PIP_Y(id_N838) - 5.},
-          {HOP4X(4), PIP_Y(id_N838) - 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 5., HOP4X(2), PIP_Y(id_N838) - 6.},
-          {HOP4X(2), PIP_Y(id_N838) - 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 6., HOP4X(0), PIP_Y(id_S838) - 7.},
-          {HOP4X(0), PIP_Y(id_S838) - 7., WIRE_X(0), PIP_Y(id_S838) - 7.}}},
-        {id_N83_loop1,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), wrap_len + 2.},
-          {HOP4X(13), wrap_len + 2., HOP4X(12), wrap_len + 2.},
-          {HOP4X(12), wrap_len + 2., HOP4X(12), PIP_Y(id_N838) + 1.},
-          {HOP4X(12), PIP_Y(id_N838) + 1., HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1.},
-          {HOP4X(10), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(10), PIP_Y(id_N838) + 0.},
-          {HOP4X(10), PIP_Y(id_N838) + 0., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(8), PIP_Y(id_N838) - 1.},
-          {HOP4X(8), PIP_Y(id_S834) - 1., WIRE_X(0), PIP_Y(id_S834) - 1.},
-          {HOP4X(8), PIP_Y(id_N838) - 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(6), PIP_Y(id_N838) - 2.},
-          {HOP4X(6), PIP_Y(id_N838) - 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(4), PIP_Y(id_N838) - 3.},
-          {HOP4X(4), PIP_Y(id_N838) - 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 3., HOP4X(2), PIP_Y(id_N838) - 4.},
-          {HOP4X(2), PIP_Y(id_N838) - 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 4., HOP4X(0), PIP_Y(id_S838) - 5.},
-          {HOP4X(0), PIP_Y(id_S838) - 5., WIRE_X(0), PIP_Y(id_S838) - 5.}}},
-        {id_N83_loop2,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), wrap_len + 3.},
-          {HOP4X(11), wrap_len + 3., HOP4X(10), wrap_len + 3.},
-          {HOP4X(10), wrap_len + 3., HOP4X(10), PIP_Y(id_N838) + 2.},
-          {HOP4X(10), PIP_Y(id_N838) + 2., HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2.},
-          {HOP4X(8), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(8), PIP_Y(id_N838) + 1.},
-          {HOP4X(8), PIP_Y(id_S834) + 1., WIRE_X(0), PIP_Y(id_S834) + 1.},
-          {HOP4X(8), PIP_Y(id_N838) + 1., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(6), PIP_Y(id_N838) + 0.},
-          {HOP4X(6), PIP_Y(id_N838) + 0., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(4), PIP_Y(id_N838) - 1.},
-          {HOP4X(4), PIP_Y(id_N838) - 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist - 1., HOP4X(2), PIP_Y(id_N838) - 2.},
-          {HOP4X(2), PIP_Y(id_N838) - 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist - 2., HOP4X(0), PIP_Y(id_S838) - 3.},
-          {HOP4X(0), PIP_Y(id_S838) - 3., WIRE_X(0), PIP_Y(id_S838) - 3.}}},
-        {id_N83_loop3,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), wrap_len + 4.},
-          {HOP4X(9), wrap_len + 4., HOP4X(8), wrap_len + 4.},
-          {HOP4X(8), wrap_len + 4., HOP4X(8), PIP_Y(id_N838) + 3.},
-          {HOP4X(8), PIP_Y(id_S834) + 3., WIRE_X(0), PIP_Y(id_S834) + 3.},
-          {HOP4X(8), PIP_Y(id_N838) + 3., HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3.},
-          {HOP4X(6), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(6), PIP_Y(id_N838) + 2.},
-          {HOP4X(6), PIP_Y(id_N838) + 2., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(4), PIP_Y(id_N838) + 1.},
-          {HOP4X(4), PIP_Y(id_N838) + 1., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 1., HOP4X(2), PIP_Y(id_N838) + 0.},
-          {HOP4X(2), PIP_Y(id_N838) + 0., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 0., HOP4X(0), PIP_Y(id_S838) - 1.},
-          {HOP4X(0), PIP_Y(id_S838) - 1., WIRE_X(0), PIP_Y(id_S838) - 1.}}},
-        {id_N83_loop4,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
-          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
-          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), wrap_len + 5.},
-          {HOP4X(7), wrap_len + 5., HOP4X(6), wrap_len + 5.},
-          {HOP4X(6), wrap_len + 5., HOP4X(6), PIP_Y(id_N838) + 4.},
-          {HOP4X(6), PIP_Y(id_N838) + 4., HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4.},
-          {HOP4X(4), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(4), PIP_Y(id_N838) + 3.},
-          {HOP4X(4), PIP_Y(id_N838) + 3., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 3., HOP4X(2), PIP_Y(id_N838) + 2.},
-          {HOP4X(2), PIP_Y(id_N838) + 2., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 2., HOP4X(0), PIP_Y(id_S838) + 1.},
-          {HOP4X(0), PIP_Y(id_S838) + 1., WIRE_X(0), PIP_Y(id_S838) + 1.}}},
-        {id_N83_loop5,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
-          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
-          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
-          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), wrap_len + 6.},
-          {HOP4X(5), wrap_len + 6., HOP4X(4), wrap_len + 6.},
-          {HOP4X(4), wrap_len + 6., HOP4X(4), PIP_Y(id_N838) + 5.},
-          {HOP4X(4), PIP_Y(id_N838) + 5., HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5.},
-          {HOP4X(2), PIP_Y(id_N838) - left_wire_dist + 5., HOP4X(2), PIP_Y(id_N838) + 4.},
-          {HOP4X(2), PIP_Y(id_N838) + 4., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 4., HOP4X(0), PIP_Y(id_S838) + 3.},
-          {HOP4X(0), PIP_Y(id_S838) + 3., WIRE_X(0), PIP_Y(id_S838) + 3.}}},
-        {id_N83_loop6,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
-          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
-          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
-          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
-          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), wrap_len + 7.},
-          {HOP4X(3), wrap_len + 7., HOP4X(2), wrap_len + 7.},
-          {HOP4X(2), wrap_len + 7., HOP4X(2), PIP_Y(id_N838) + 6.},
-          {HOP4X(2), PIP_Y(id_N838) + 6., HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6.},
-          {HOP4X(0), PIP_Y(id_N838) - left_wire_dist + 6., HOP4X(0), PIP_Y(id_S838) + 5.},
-          {HOP4X(0), PIP_Y(id_S838) + 5., WIRE_X(0), PIP_Y(id_S838) + 5.}}},
-        {id_N83_loop7,
-         {{WIRE_X(0), PIP_Y(id_N830), HOP4X(17), PIP_Y(id_N830)},
-          {HOP4X(17), PIP_Y(id_N830) + 0., HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0.},
-          {HOP4X(15), PIP_Y(id_N830) + left_wire_dist + 0., HOP4X(15), PIP_Y(id_N830) + 1.},
-          {HOP4X(15), PIP_Y(id_N830) + 1., HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1.},
-          {HOP4X(13), PIP_Y(id_N830) + left_wire_dist + 1., HOP4X(13), PIP_Y(id_N830) + 2.},
-          {HOP4X(13), PIP_Y(id_N830) + 2., HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2.},
-          {HOP4X(11), PIP_Y(id_N830) + left_wire_dist + 2., HOP4X(11), PIP_Y(id_N830) + 3.},
-          {HOP4X(11), PIP_Y(id_N830) + 3., HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3.},
-          {HOP4X(9), PIP_Y(id_N830) + left_wire_dist + 3., HOP4X(9), PIP_Y(id_N830) + 4.},
-          {HOP4X(9), PIP_Y(id_N834) + 4., WIRE_X(0), PIP_Y(id_N834) + 4.},
-          {HOP4X(9), PIP_Y(id_N830) + 4., HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4.},
-          {HOP4X(7), PIP_Y(id_N830) + left_wire_dist + 4., HOP4X(7), PIP_Y(id_N830) + 5.},
-          {HOP4X(7), PIP_Y(id_N830) + 5., HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5.},
-          {HOP4X(5), PIP_Y(id_N830) + left_wire_dist + 5., HOP4X(5), PIP_Y(id_N830) + 6.},
-          {HOP4X(5), PIP_Y(id_N830) + 6., HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6.},
-          {HOP4X(3), PIP_Y(id_N830) + left_wire_dist + 6., HOP4X(3), PIP_Y(id_N830) + 7.},
-          {HOP4X(3), PIP_Y(id_N830) + 7., HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7.},
-          {HOP4X(1), PIP_Y(id_N830) + left_wire_dist + 7., HOP4X(1), wrap_len + 8.},
-          {HOP4X(1), wrap_len + 8., HOP4X(0), wrap_len + 8.},
-          {HOP4X(0), wrap_len + 8., HOP4X(0), PIP_Y(id_S838) + 7.},
-          {HOP4X(0), PIP_Y(id_S838) + 7., WIRE_X(0), PIP_Y(id_S838) + 7.}}},
-
-#define PIP_X(pip_id) (pipPoint.at(pip_id).second)
-#define WIRE_Y(offset) (cru_y + cru_h + ((float)offset) * ew_dist)
-        // 1 hop
-        {id_E10,
-         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
-          {PIP_X(id_E100), WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(1)},
-          {PIP_X(id_E101) + 1., WIRE_Y(1), PIP_X(id_E101) + 1., WIRE_Y(0)}}},
-        {id_W10,
-         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
-          {PIP_X(id_W100), WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(2)},
-          {PIP_X(id_W101) - 1., WIRE_Y(2), PIP_X(id_W101) - 1., WIRE_Y(0)}}},
-        {id_E10_loop0,
-         {{PIP_X(id_E100), WIRE_Y(0), PIP_X(id_E100), WIRE_Y(1)},
-          {PIP_X(id_E100), WIRE_Y(1), 1. + wrap_len, WIRE_Y(1)},
-          {1. + wrap_len, WIRE_Y(1), 1. + wrap_len, WIRE_Y(2)},
-          {1. + wrap_len, WIRE_Y(2), PIP_X(id_W101), WIRE_Y(2)},
-          {PIP_X(id_W101), WIRE_Y(2), PIP_X(id_W101), WIRE_Y(0)}}},
-        {id_W10_loop0,
-         {{PIP_X(id_W100), WIRE_Y(0), PIP_X(id_W100), WIRE_Y(2)},
-          {PIP_X(id_W100), WIRE_Y(2), -1. * wrap_len, WIRE_Y(2)},
-          {-1. * wrap_len, WIRE_Y(2), -1. * wrap_len, WIRE_Y(1)},
-          {-1. * wrap_len, WIRE_Y(1), PIP_X(id_E101), WIRE_Y(1)},
-          {PIP_X(id_E101), WIRE_Y(1), PIP_X(id_E101), WIRE_Y(0)}}},
-        {id_E13,
-         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
-          {PIP_X(id_E130), WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(3)},
-          {PIP_X(id_E131) + 1., WIRE_Y(3), PIP_X(id_E131) + 1., WIRE_Y(0)}}},
-        {id_W13,
-         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
-          {PIP_X(id_W130), WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(4)},
-          {PIP_X(id_W131) - 1., WIRE_Y(4), PIP_X(id_W131) - 1., WIRE_Y(0)}}},
-        {id_E13_loop0,
-         {{PIP_X(id_E130), WIRE_Y(0), PIP_X(id_E130), WIRE_Y(3)},
-          {PIP_X(id_E130), WIRE_Y(3), 1. + wrap_len, WIRE_Y(3)},
-          {1. + wrap_len, WIRE_Y(3), 1. + wrap_len, WIRE_Y(4)},
-          {1. + wrap_len, WIRE_Y(4), PIP_X(id_W131), WIRE_Y(4)},
-          {PIP_X(id_W131), WIRE_Y(4), PIP_X(id_W131), WIRE_Y(0)}}},
-        {id_W13_loop0,
-         {{PIP_X(id_W130), WIRE_Y(0), PIP_X(id_W130), WIRE_Y(4)},
-          {PIP_X(id_W130), WIRE_Y(4), -1. * wrap_len, WIRE_Y(4)},
-          {-1. * wrap_len, WIRE_Y(4), -1. * wrap_len, WIRE_Y(3)},
-          {-1. * wrap_len, WIRE_Y(3), PIP_X(id_E131), WIRE_Y(3)},
-          {PIP_X(id_E131), WIRE_Y(3), PIP_X(id_E131), WIRE_Y(0)}}},
-        // 1 hop EW
-        {id_EW10,
-         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
-          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
-          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
-          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
-          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
-        {id_EW10_loop_e,
-         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
-          {PIP_X(id_EW10), WIRE_Y(6), wrap_len + 1., WIRE_Y(6)},
-          {wrap_len + 1., WIRE_Y(6), wrap_len + 1., WIRE_Y(5)},
-          {wrap_len + 1., WIRE_Y(5), PIP_X(id_W111), WIRE_Y(5)},
-          {PIP_X(id_W111), WIRE_Y(5), PIP_X(id_W111), WIRE_Y(0)},
-          {PIP_X(id_EW10), WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(5)},
-          {PIP_X(id_W111) - 1., WIRE_Y(5), PIP_X(id_W111) - 1., WIRE_Y(0)}}},
-        {id_EW10_loop_w,
-         {{PIP_X(id_EW10), WIRE_Y(0), PIP_X(id_EW10), WIRE_Y(6)},
-          {PIP_X(id_EW10), WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(6)},
-          {PIP_X(id_E111) + 1., WIRE_Y(6), PIP_X(id_E111) + 1., WIRE_Y(0)},
-          {PIP_X(id_EW10), WIRE_Y(5), -wrap_len, WIRE_Y(5)},
-          {-wrap_len, WIRE_Y(5), -wrap_len, WIRE_Y(6)},
-          {-wrap_len, WIRE_Y(6), PIP_X(id_E111), WIRE_Y(6)},
-          {PIP_X(id_E111), WIRE_Y(6), PIP_X(id_E111), WIRE_Y(0)}}},
-        {id_EW20,
-         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
-          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
-          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
-          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
-          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
-        {id_EW20_loop_e,
-         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
-          {PIP_X(id_EW20), WIRE_Y(8), wrap_len + 1., WIRE_Y(8)},
-          {wrap_len + 1., WIRE_Y(8), wrap_len + 1., WIRE_Y(7)},
-          {wrap_len + 1., WIRE_Y(7), PIP_X(id_W121), WIRE_Y(7)},
-          {PIP_X(id_W121), WIRE_Y(7), PIP_X(id_W121), WIRE_Y(0)},
-          {PIP_X(id_EW20), WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(7)},
-          {PIP_X(id_W121) - 1., WIRE_Y(7), PIP_X(id_W121) - 1., WIRE_Y(0)}}},
-        {id_EW20_loop_w,
-         {{PIP_X(id_EW20), WIRE_Y(0), PIP_X(id_EW20), WIRE_Y(8)},
-          {PIP_X(id_EW20), WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(8)},
-          {PIP_X(id_E121) + 1., WIRE_Y(8), PIP_X(id_E121) + 1., WIRE_Y(0)},
-          {PIP_X(id_EW20), WIRE_Y(7), -wrap_len, WIRE_Y(7)},
-          {-wrap_len, WIRE_Y(7), -wrap_len, WIRE_Y(8)},
-          {-wrap_len, WIRE_Y(8), PIP_X(id_E121), WIRE_Y(8)},
-          {PIP_X(id_E121), WIRE_Y(8), PIP_X(id_E121), WIRE_Y(0)}}},
-// 2 hop
-#define HOP2Y(offset) WIRE_Y(offset + 9)
-        {id_E20,
-         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
-          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
-          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
-          {PIP_X(id_E201) + 1., HOP2Y(0), PIP_X(id_E202) + 2., HOP2Y(0)},
-          {PIP_X(id_E202) + 2., HOP2Y(0), PIP_X(id_E202) + 2., WIRE_Y(0)}}},
-        {id_W20,
-         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
-          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
-          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
-          {PIP_X(id_W201) - 1., HOP2Y(1), PIP_X(id_W202) - 2., HOP2Y(1)},
-          {PIP_X(id_W202) - 2., HOP2Y(1), PIP_X(id_W202) - 2., WIRE_Y(0)}}},
-        {id_E20_loop0,
-         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
-          {PIP_X(id_E200), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W201), HOP2Y(3)},
-          {PIP_X(id_W201), HOP2Y(3), PIP_X(id_W201), WIRE_Y(0)},
-          {PIP_X(id_W201), HOP2Y(1), PIP_X(id_W202) - 1., HOP2Y(1)},
-          {PIP_X(id_W202) - 1., HOP2Y(1), PIP_X(id_W202) - 1., WIRE_Y(0)}}},
-        {id_W20_loop0,
-         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
-          {PIP_X(id_W200), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E201), HOP2Y(2)},
-          {PIP_X(id_E201), HOP2Y(2), PIP_X(id_E201), WIRE_Y(0)},
-          {PIP_X(id_E201), HOP2Y(0), PIP_X(id_E202) + 1., HOP2Y(0)},
-          {PIP_X(id_E202) + 1., HOP2Y(0), PIP_X(id_E202) + 1., WIRE_Y(0)}}},
-        {id_E20_loop1,
-         {{PIP_X(id_E200), WIRE_Y(0), PIP_X(id_E200), HOP2Y(2)},
-          {PIP_X(id_E200), HOP2Y(2), PIP_X(id_E201) + 1., HOP2Y(2)},
-          {PIP_X(id_E201) + 1., HOP2Y(2), PIP_X(id_E201) + 1., WIRE_Y(0)},
-          {PIP_X(id_E201) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W202) + 1., HOP2Y(1)},
-          {PIP_X(id_W202) + 1., HOP2Y(1), PIP_X(id_W202) + 1., WIRE_Y(0)}}},
-        {id_W20_loop1,
-         {{PIP_X(id_W200), WIRE_Y(0), PIP_X(id_W200), HOP2Y(3)},
-          {PIP_X(id_W200), HOP2Y(3), PIP_X(id_W201) - 1., HOP2Y(3)},
-          {PIP_X(id_W201) - 1., HOP2Y(3), PIP_X(id_W201) - 1., WIRE_Y(0)},
-          {PIP_X(id_W201) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E202) - 1., HOP2Y(0)},
-          {PIP_X(id_E202) - 1., HOP2Y(0), PIP_X(id_E202) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 1)
-        {id_E21,
-         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
-          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
-          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
-          {PIP_X(id_E211) + 1., HOP2Y(0), PIP_X(id_E212) + 2., HOP2Y(0)},
-          {PIP_X(id_E212) + 2., HOP2Y(0), PIP_X(id_E212) + 2., WIRE_Y(0)}}},
-        {id_W21,
-         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
-          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
-          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
-          {PIP_X(id_W211) - 1., HOP2Y(1), PIP_X(id_W212) - 2., HOP2Y(1)},
-          {PIP_X(id_W212) - 2., HOP2Y(1), PIP_X(id_W212) - 2., WIRE_Y(0)}}},
-        {id_E21_loop0,
-         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
-          {PIP_X(id_E210), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W211), HOP2Y(3)},
-          {PIP_X(id_W211), HOP2Y(3), PIP_X(id_W211), WIRE_Y(0)},
-          {PIP_X(id_W211), HOP2Y(1), PIP_X(id_W212) - 1., HOP2Y(1)},
-          {PIP_X(id_W212) - 1., HOP2Y(1), PIP_X(id_W212) - 1., WIRE_Y(0)}}},
-        {id_W21_loop0,
-         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
-          {PIP_X(id_W210), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E211), HOP2Y(2)},
-          {PIP_X(id_E211), HOP2Y(2), PIP_X(id_E211), WIRE_Y(0)},
-          {PIP_X(id_E211), HOP2Y(0), PIP_X(id_E212) + 1., HOP2Y(0)},
-          {PIP_X(id_E212) + 1., HOP2Y(0), PIP_X(id_E212) + 1., WIRE_Y(0)}}},
-        {id_E21_loop1,
-         {{PIP_X(id_E210), WIRE_Y(0), PIP_X(id_E210), HOP2Y(2)},
-          {PIP_X(id_E210), HOP2Y(2), PIP_X(id_E211) + 1., HOP2Y(2)},
-          {PIP_X(id_E211) + 1., HOP2Y(2), PIP_X(id_E211) + 1., WIRE_Y(0)},
-          {PIP_X(id_E211) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W212) + 1., HOP2Y(1)},
-          {PIP_X(id_W212) + 1., HOP2Y(1), PIP_X(id_W212) + 1., WIRE_Y(0)}}},
-        {id_W21_loop1,
-         {{PIP_X(id_W210), WIRE_Y(0), PIP_X(id_W210), HOP2Y(3)},
-          {PIP_X(id_W210), HOP2Y(3), PIP_X(id_W211) - 1., HOP2Y(3)},
-          {PIP_X(id_W211) - 1., HOP2Y(3), PIP_X(id_W211) - 1., WIRE_Y(0)},
-          {PIP_X(id_W211) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E212) - 1., HOP2Y(0)},
-          {PIP_X(id_E212) - 1., HOP2Y(0), PIP_X(id_E212) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 2)
-        {id_E22,
-         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
-          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
-          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
-          {PIP_X(id_E221) + 1., HOP2Y(0), PIP_X(id_E222) + 2., HOP2Y(0)},
-          {PIP_X(id_E222) + 2., HOP2Y(0), PIP_X(id_E222) + 2., WIRE_Y(0)}}},
-        {id_W22,
-         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
-          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
-          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
-          {PIP_X(id_W221) - 1., HOP2Y(1), PIP_X(id_W222) - 2., HOP2Y(1)},
-          {PIP_X(id_W222) - 2., HOP2Y(1), PIP_X(id_W222) - 2., WIRE_Y(0)}}},
-        {id_E22_loop0,
-         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
-          {PIP_X(id_E220), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W221), HOP2Y(3)},
-          {PIP_X(id_W221), HOP2Y(3), PIP_X(id_W221), WIRE_Y(0)},
-          {PIP_X(id_W221), HOP2Y(1), PIP_X(id_W222) - 1., HOP2Y(1)},
-          {PIP_X(id_W222) - 1., HOP2Y(1), PIP_X(id_W222) - 1., WIRE_Y(0)}}},
-        {id_W22_loop0,
-         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
-          {PIP_X(id_W220), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E221), HOP2Y(2)},
-          {PIP_X(id_E221), HOP2Y(2), PIP_X(id_E221), WIRE_Y(0)},
-          {PIP_X(id_E221), HOP2Y(0), PIP_X(id_E222) + 1., HOP2Y(0)},
-          {PIP_X(id_E222) + 1., HOP2Y(0), PIP_X(id_E222) + 1., WIRE_Y(0)}}},
-        {id_E22_loop1,
-         {{PIP_X(id_E220), WIRE_Y(0), PIP_X(id_E220), HOP2Y(2)},
-          {PIP_X(id_E220), HOP2Y(2), PIP_X(id_E221) + 1., HOP2Y(2)},
-          {PIP_X(id_E221) + 1., HOP2Y(2), PIP_X(id_E221) + 1., WIRE_Y(0)},
-          {PIP_X(id_E221) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W222) + 1., HOP2Y(1)},
-          {PIP_X(id_W222) + 1., HOP2Y(1), PIP_X(id_W222) + 1., WIRE_Y(0)}}},
-        {id_W22_loop1,
-         {{PIP_X(id_W220), WIRE_Y(0), PIP_X(id_W220), HOP2Y(3)},
-          {PIP_X(id_W220), HOP2Y(3), PIP_X(id_W221) - 1., HOP2Y(3)},
-          {PIP_X(id_W221) - 1., HOP2Y(3), PIP_X(id_W221) - 1., WIRE_Y(0)},
-          {PIP_X(id_W221) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E222) - 1., HOP2Y(0)},
-          {PIP_X(id_E222) - 1., HOP2Y(0), PIP_X(id_E222) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 3)
-        {id_E23,
-         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
-          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
-          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
-          {PIP_X(id_E231) + 1., HOP2Y(0), PIP_X(id_E232) + 2., HOP2Y(0)},
-          {PIP_X(id_E232) + 2., HOP2Y(0), PIP_X(id_E232) + 2., WIRE_Y(0)}}},
-        {id_W23,
-         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
-          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
-          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
-          {PIP_X(id_W231) - 1., HOP2Y(1), PIP_X(id_W232) - 2., HOP2Y(1)},
-          {PIP_X(id_W232) - 2., HOP2Y(1), PIP_X(id_W232) - 2., WIRE_Y(0)}}},
-        {id_E23_loop0,
-         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
-          {PIP_X(id_E230), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W231), HOP2Y(3)},
-          {PIP_X(id_W231), HOP2Y(3), PIP_X(id_W231), WIRE_Y(0)},
-          {PIP_X(id_W231), HOP2Y(1), PIP_X(id_W232) - 1., HOP2Y(1)},
-          {PIP_X(id_W232) - 1., HOP2Y(1), PIP_X(id_W232) - 1., WIRE_Y(0)}}},
-        {id_W23_loop0,
-         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
-          {PIP_X(id_W230), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E231), HOP2Y(2)},
-          {PIP_X(id_E231), HOP2Y(2), PIP_X(id_E231), WIRE_Y(0)},
-          {PIP_X(id_E231), HOP2Y(0), PIP_X(id_E232) + 1., HOP2Y(0)},
-          {PIP_X(id_E232) + 1., HOP2Y(0), PIP_X(id_E232) + 1., WIRE_Y(0)}}},
-        {id_E23_loop1,
-         {{PIP_X(id_E230), WIRE_Y(0), PIP_X(id_E230), HOP2Y(2)},
-          {PIP_X(id_E230), HOP2Y(2), PIP_X(id_E231) + 1., HOP2Y(2)},
-          {PIP_X(id_E231) + 1., HOP2Y(2), PIP_X(id_E231) + 1., WIRE_Y(0)},
-          {PIP_X(id_E231) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W232) + 1., HOP2Y(1)},
-          {PIP_X(id_W232) + 1., HOP2Y(1), PIP_X(id_W232) + 1., WIRE_Y(0)}}},
-        {id_W23_loop1,
-         {{PIP_X(id_W230), WIRE_Y(0), PIP_X(id_W230), HOP2Y(3)},
-          {PIP_X(id_W230), HOP2Y(3), PIP_X(id_W231) - 1., HOP2Y(3)},
-          {PIP_X(id_W231) - 1., HOP2Y(3), PIP_X(id_W231) - 1., WIRE_Y(0)},
-          {PIP_X(id_W231) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E232) - 1., HOP2Y(0)},
-          {PIP_X(id_E232) - 1., HOP2Y(0), PIP_X(id_E232) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 4)
-        {id_E24,
-         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
-          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
-          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
-          {PIP_X(id_E241) + 1., HOP2Y(0), PIP_X(id_E242) + 2., HOP2Y(0)},
-          {PIP_X(id_E242) + 2., HOP2Y(0), PIP_X(id_E242) + 2., WIRE_Y(0)}}},
-        {id_W24,
-         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
-          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
-          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
-          {PIP_X(id_W241) - 1., HOP2Y(1), PIP_X(id_W242) - 2., HOP2Y(1)},
-          {PIP_X(id_W242) - 2., HOP2Y(1), PIP_X(id_W242) - 2., WIRE_Y(0)}}},
-        {id_E24_loop0,
-         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
-          {PIP_X(id_E240), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W241), HOP2Y(3)},
-          {PIP_X(id_W241), HOP2Y(3), PIP_X(id_W241), WIRE_Y(0)},
-          {PIP_X(id_W241), HOP2Y(1), PIP_X(id_W242) - 1., HOP2Y(1)},
-          {PIP_X(id_W242) - 1., HOP2Y(1), PIP_X(id_W242) - 1., WIRE_Y(0)}}},
-        {id_W24_loop0,
-         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
-          {PIP_X(id_W240), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E241), HOP2Y(2)},
-          {PIP_X(id_E241), HOP2Y(2), PIP_X(id_E241), WIRE_Y(0)},
-          {PIP_X(id_E241), HOP2Y(0), PIP_X(id_E242) + 1., HOP2Y(0)},
-          {PIP_X(id_E242) + 1., HOP2Y(0), PIP_X(id_E242) + 1., WIRE_Y(0)}}},
-        {id_E24_loop1,
-         {{PIP_X(id_E240), WIRE_Y(0), PIP_X(id_E240), HOP2Y(2)},
-          {PIP_X(id_E240), HOP2Y(2), PIP_X(id_E241) + 1., HOP2Y(2)},
-          {PIP_X(id_E241) + 1., HOP2Y(2), PIP_X(id_E241) + 1., WIRE_Y(0)},
-          {PIP_X(id_E241) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W242) + 1., HOP2Y(1)},
-          {PIP_X(id_W242) + 1., HOP2Y(1), PIP_X(id_W242) + 1., WIRE_Y(0)}}},
-        {id_W24_loop1,
-         {{PIP_X(id_W240), WIRE_Y(0), PIP_X(id_W240), HOP2Y(3)},
-          {PIP_X(id_W240), HOP2Y(3), PIP_X(id_W241) - 1., HOP2Y(3)},
-          {PIP_X(id_W241) - 1., HOP2Y(3), PIP_X(id_W241) - 1., WIRE_Y(0)},
-          {PIP_X(id_W241) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E242) - 1., HOP2Y(0)},
-          {PIP_X(id_E242) - 1., HOP2Y(0), PIP_X(id_E242) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 5)
-        {id_E25,
-         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
-          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
-          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
-          {PIP_X(id_E251) + 1., HOP2Y(0), PIP_X(id_E252) + 2., HOP2Y(0)},
-          {PIP_X(id_E252) + 2., HOP2Y(0), PIP_X(id_E252) + 2., WIRE_Y(0)}}},
-        {id_W25,
-         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
-          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
-          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
-          {PIP_X(id_W251) - 1., HOP2Y(1), PIP_X(id_W252) - 2., HOP2Y(1)},
-          {PIP_X(id_W252) - 2., HOP2Y(1), PIP_X(id_W252) - 2., WIRE_Y(0)}}},
-        {id_E25_loop0,
-         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
-          {PIP_X(id_E250), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W251), HOP2Y(3)},
-          {PIP_X(id_W251), HOP2Y(3), PIP_X(id_W251), WIRE_Y(0)},
-          {PIP_X(id_W251), HOP2Y(1), PIP_X(id_W252) - 1., HOP2Y(1)},
-          {PIP_X(id_W252) - 1., HOP2Y(1), PIP_X(id_W252) - 1., WIRE_Y(0)}}},
-        {id_W25_loop0,
-         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
-          {PIP_X(id_W250), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E251), HOP2Y(2)},
-          {PIP_X(id_E251), HOP2Y(2), PIP_X(id_E251), WIRE_Y(0)},
-          {PIP_X(id_E251), HOP2Y(0), PIP_X(id_E252) + 1., HOP2Y(0)},
-          {PIP_X(id_E252) + 1., HOP2Y(0), PIP_X(id_E252) + 1., WIRE_Y(0)}}},
-        {id_E25_loop1,
-         {{PIP_X(id_E250), WIRE_Y(0), PIP_X(id_E250), HOP2Y(2)},
-          {PIP_X(id_E250), HOP2Y(2), PIP_X(id_E251) + 1., HOP2Y(2)},
-          {PIP_X(id_E251) + 1., HOP2Y(2), PIP_X(id_E251) + 1., WIRE_Y(0)},
-          {PIP_X(id_E251) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W252) + 1., HOP2Y(1)},
-          {PIP_X(id_W252) + 1., HOP2Y(1), PIP_X(id_W252) + 1., WIRE_Y(0)}}},
-        {id_W25_loop1,
-         {{PIP_X(id_W250), WIRE_Y(0), PIP_X(id_W250), HOP2Y(3)},
-          {PIP_X(id_W250), HOP2Y(3), PIP_X(id_W251) - 1., HOP2Y(3)},
-          {PIP_X(id_W251) - 1., HOP2Y(3), PIP_X(id_W251) - 1., WIRE_Y(0)},
-          {PIP_X(id_W251) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E252) - 1., HOP2Y(0)},
-          {PIP_X(id_E252) - 1., HOP2Y(0), PIP_X(id_E252) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 6)
-        {id_E26,
-         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
-          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
-          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
-          {PIP_X(id_E261) + 1., HOP2Y(0), PIP_X(id_E262) + 2., HOP2Y(0)},
-          {PIP_X(id_E262) + 2., HOP2Y(0), PIP_X(id_E262) + 2., WIRE_Y(0)}}},
-        {id_W26,
-         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
-          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
-          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
-          {PIP_X(id_W261) - 1., HOP2Y(1), PIP_X(id_W262) - 2., HOP2Y(1)},
-          {PIP_X(id_W262) - 2., HOP2Y(1), PIP_X(id_W262) - 2., WIRE_Y(0)}}},
-        {id_E26_loop0,
-         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
-          {PIP_X(id_E260), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W261), HOP2Y(3)},
-          {PIP_X(id_W261), HOP2Y(3), PIP_X(id_W261), WIRE_Y(0)},
-          {PIP_X(id_W261), HOP2Y(1), PIP_X(id_W262) - 1., HOP2Y(1)},
-          {PIP_X(id_W262) - 1., HOP2Y(1), PIP_X(id_W262) - 1., WIRE_Y(0)}}},
-        {id_W26_loop0,
-         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
-          {PIP_X(id_W260), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E261), HOP2Y(2)},
-          {PIP_X(id_E261), HOP2Y(2), PIP_X(id_E261), WIRE_Y(0)},
-          {PIP_X(id_E261), HOP2Y(0), PIP_X(id_E262) + 1., HOP2Y(0)},
-          {PIP_X(id_E262) + 1., HOP2Y(0), PIP_X(id_E262) + 1., WIRE_Y(0)}}},
-        {id_E26_loop1,
-         {{PIP_X(id_E260), WIRE_Y(0), PIP_X(id_E260), HOP2Y(2)},
-          {PIP_X(id_E260), HOP2Y(2), PIP_X(id_E261) + 1., HOP2Y(2)},
-          {PIP_X(id_E261) + 1., HOP2Y(2), PIP_X(id_E261) + 1., WIRE_Y(0)},
-          {PIP_X(id_E261) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W262) + 1., HOP2Y(1)},
-          {PIP_X(id_W262) + 1., HOP2Y(1), PIP_X(id_W262) + 1., WIRE_Y(0)}}},
-        {id_W26_loop1,
-         {{PIP_X(id_W260), WIRE_Y(0), PIP_X(id_W260), HOP2Y(3)},
-          {PIP_X(id_W260), HOP2Y(3), PIP_X(id_W261) - 1., HOP2Y(3)},
-          {PIP_X(id_W261) - 1., HOP2Y(3), PIP_X(id_W261) - 1., WIRE_Y(0)},
-          {PIP_X(id_W261) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E262) - 1., HOP2Y(0)},
-          {PIP_X(id_E262) - 1., HOP2Y(0), PIP_X(id_E262) - 1., WIRE_Y(0)}}},
-
-#undef HOP2Y
-#define HOP2Y(offset) WIRE_Y(offset + 9 + 4 * 7)
-        {id_E27,
-         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
-          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
-          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
-          {PIP_X(id_E271) + 1., HOP2Y(0), PIP_X(id_E272) + 2., HOP2Y(0)},
-          {PIP_X(id_E272) + 2., HOP2Y(0), PIP_X(id_E272) + 2., WIRE_Y(0)}}},
-        {id_W27,
-         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
-          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
-          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
-          {PIP_X(id_W271) - 1., HOP2Y(1), PIP_X(id_W272) - 2., HOP2Y(1)},
-          {PIP_X(id_W272) - 2., HOP2Y(1), PIP_X(id_W272) - 2., WIRE_Y(0)}}},
-        {id_E27_loop0,
-         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
-          {PIP_X(id_E270), HOP2Y(2), wrap_len + 1., HOP2Y(2)},
-          {wrap_len + 1., HOP2Y(2), wrap_len + 1., HOP2Y(3)},
-          {wrap_len + 1., HOP2Y(3), PIP_X(id_W271), HOP2Y(3)},
-          {PIP_X(id_W271), HOP2Y(3), PIP_X(id_W271), WIRE_Y(0)},
-          {PIP_X(id_W271), HOP2Y(1), PIP_X(id_W272) - 1., HOP2Y(1)},
-          {PIP_X(id_W272) - 1., HOP2Y(1), PIP_X(id_W272) - 1., WIRE_Y(0)}}},
-        {id_W27_loop0,
-         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
-          {PIP_X(id_W270), HOP2Y(3), -wrap_len, HOP2Y(3)},
-          {-wrap_len, HOP2Y(3), -wrap_len, HOP2Y(2)},
-          {-wrap_len, HOP2Y(2), PIP_X(id_E271), HOP2Y(2)},
-          {PIP_X(id_E271), HOP2Y(2), PIP_X(id_E271), WIRE_Y(0)},
-          {PIP_X(id_E271), HOP2Y(0), PIP_X(id_E272) + 1., HOP2Y(0)},
-          {PIP_X(id_E272) + 1., HOP2Y(0), PIP_X(id_E272) + 1., WIRE_Y(0)}}},
-        {id_E27_loop1,
-         {{PIP_X(id_E270), WIRE_Y(0), PIP_X(id_E270), HOP2Y(2)},
-          {PIP_X(id_E270), HOP2Y(2), PIP_X(id_E271) + 1., HOP2Y(2)},
-          {PIP_X(id_E271) + 1., HOP2Y(2), PIP_X(id_E271) + 1., WIRE_Y(0)},
-          {PIP_X(id_E271) + 1., HOP2Y(0), wrap_len + 2., HOP2Y(0)},
-          {wrap_len + 2., HOP2Y(0), wrap_len + 2., HOP2Y(1)},
-          {wrap_len + 2., HOP2Y(1), PIP_X(id_W272) + 1., HOP2Y(1)},
-          {PIP_X(id_W272) + 1., HOP2Y(1), PIP_X(id_W272) + 1., WIRE_Y(0)}}},
-        {id_W27_loop1,
-         {{PIP_X(id_W270), WIRE_Y(0), PIP_X(id_W270), HOP2Y(3)},
-          {PIP_X(id_W270), HOP2Y(3), PIP_X(id_W271) - 1., HOP2Y(3)},
-          {PIP_X(id_W271) - 1., HOP2Y(3), PIP_X(id_W271) - 1., WIRE_Y(0)},
-          {PIP_X(id_W271) - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(1)},
-          {-wrap_len - 1., HOP2Y(1), -wrap_len - 1., HOP2Y(0)},
-          {-wrap_len - 1., HOP2Y(0), PIP_X(id_E272) - 1., HOP2Y(0)},
-          {PIP_X(id_E272) - 1., HOP2Y(0), PIP_X(id_E272) - 1., WIRE_Y(0)}}},
-
-// clock branches
-#define CLK_GBO0_Y 41.f
-#define CLK_GBO1_Y 46.f
-// 4 hop
-#define HOP4Y_START (CLK_GBO0_Y + 10.f)
-#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START)
-        {id_E80,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
-          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
-          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
-          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
-          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E808) + 8., HOP4Y(0)},
-          {PIP_X(id_E808) + 8, HOP4Y(0), PIP_X(id_E808) + 8., WIRE_Y(0)}}},
-        {id_W80,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
-          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
-          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
-          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
-          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W808) - 8., HOP4Y(1)},
-          {PIP_X(id_W808) - 8, HOP4Y(1), PIP_X(id_W808) - 8., WIRE_Y(0)}}},
-        {id_E80_loop0,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
-          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
-          {wrap_len + 1., HOP4Y(15), PIP_X(id_W800) - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - 0., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W800) - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W800) - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W800) - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7)},
-          {PIP_X(id_W804) - 3., HOP4Y(9), PIP_X(id_W804) - 3., WIRE_Y(0)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W800) - 4., HOP4Y(7)},
-          {PIP_X(id_W800) - 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W800) - 5., HOP4Y(5)},
-          {PIP_X(id_W800) - 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W800) - 6., HOP4Y(3)},
-          {PIP_X(id_W800) - 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W808) - 7., HOP4Y(1)},
-          {PIP_X(id_W808) - 7, HOP4Y(1), PIP_X(id_W808) - 7., WIRE_Y(0)}}},
-        {id_E80_loop1,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
-          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
-          {wrap_len + 2., HOP4Y(13), PIP_X(id_W800) + 1., HOP4Y(13)},
-          {PIP_X(id_W800) + 1., HOP4Y(13), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W800) - 0., HOP4Y(11)},
-          {PIP_X(id_W800) - 0., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W800) - 1., HOP4Y(9)},
-          {PIP_X(id_W804) - 1., HOP4Y(9), PIP_X(id_W804) - 1., WIRE_Y(0)},
-          {PIP_X(id_W800) - 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W800) - 2., HOP4Y(7)},
-          {PIP_X(id_W800) - 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W800) - 3., HOP4Y(5)},
-          {PIP_X(id_W800) - 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W800) - 4., HOP4Y(3)},
-          {PIP_X(id_W800) - 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W808) - 5., HOP4Y(1)},
-          {PIP_X(id_W808) - 5., HOP4Y(1), PIP_X(id_W808) - 5., WIRE_Y(0)}}},
-        {id_E80_loop2,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
-          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
-          {wrap_len + 3., HOP4Y(11), PIP_X(id_W800) + 2., HOP4Y(11)},
-          {PIP_X(id_W800) + 2., HOP4Y(11), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W800) + 1., HOP4Y(9)},
-          {PIP_X(id_W804) + 1., HOP4Y(9), PIP_X(id_W804) + 1., WIRE_Y(0)},
-          {PIP_X(id_W800) + 1., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7)},
-          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W800) + 0., HOP4Y(7)},
-          {PIP_X(id_W800) + 0., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W800) - 1., HOP4Y(5)},
-          {PIP_X(id_W800) - 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W800) - 2., HOP4Y(3)},
-          {PIP_X(id_W800) - 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W808) - 3., HOP4Y(1)},
-          {PIP_X(id_W808) - 3., HOP4Y(1), PIP_X(id_W808) - 3., WIRE_Y(0)}}},
-        {id_E80_loop3,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
-          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
-          {wrap_len + 4., HOP4Y(9), PIP_X(id_W800) + 3., HOP4Y(9)},
-          {PIP_X(id_W804) + 3., HOP4Y(9), PIP_X(id_W804) + 3., WIRE_Y(0)},
-          {PIP_X(id_W800) + 3., HOP4Y(9), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7)},
-          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W800) + 2., HOP4Y(7)},
-          {PIP_X(id_W800) + 2., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W800) + 1., HOP4Y(5)},
-          {PIP_X(id_W800) + 1., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W800) - 0., HOP4Y(3)},
-          {PIP_X(id_W800) - 0., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W808) - 1., HOP4Y(1)},
-          {PIP_X(id_W808) - 1., HOP4Y(1), PIP_X(id_W808) - 1., WIRE_Y(0)}}},
-        {id_E80_loop4,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
-          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
-          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
-          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
-          {wrap_len + 5., HOP4Y(7), PIP_X(id_W800) + 4., HOP4Y(7)},
-          {PIP_X(id_W800) + 4., HOP4Y(7), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W800) + 3., HOP4Y(5)},
-          {PIP_X(id_W800) + 3., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W800) + 2., HOP4Y(3)},
-          {PIP_X(id_W800) + 2., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W808) + 1., HOP4Y(1)},
-          {PIP_X(id_W808) + 1., HOP4Y(1), PIP_X(id_W808) + 1., WIRE_Y(0)}}},
-        {id_E80_loop5,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
-          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
-          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
-          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
-          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
-          {wrap_len + 6., HOP4Y(5), PIP_X(id_W800) + 5., HOP4Y(5)},
-          {PIP_X(id_W800) + 5., HOP4Y(5), PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W800) + 4., HOP4Y(3)},
-          {PIP_X(id_W800) + 4., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W808) + 3., HOP4Y(1)},
-          {PIP_X(id_W808) + 3., HOP4Y(1), PIP_X(id_W808) + 3., WIRE_Y(0)}}},
-        {id_E80_loop6,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
-          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
-          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
-          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
-          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
-          {wrap_len + 7., HOP4Y(3), PIP_X(id_W800) + 6., HOP4Y(3)},
-          {PIP_X(id_W800) + 6., HOP4Y(3), PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W808) + 5., HOP4Y(1)},
-          {PIP_X(id_W808) + 5., HOP4Y(1), PIP_X(id_W808) + 5., WIRE_Y(0)}}},
-        {id_E80_loop7,
-         {{PIP_X(id_E800), WIRE_Y(0), PIP_X(id_E800), HOP4Y(16)},
-          {PIP_X(id_E800), HOP4Y(16), PIP_X(id_W808), HOP4Y(16)},
-          {PIP_X(id_W808) + 0., HOP4Y(16), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W808) + 1., HOP4Y(14)},
-          {PIP_X(id_W808) + 1., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W808) + 2., HOP4Y(12)},
-          {PIP_X(id_W808) + 2., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W808) + 3., HOP4Y(10)},
-          {PIP_X(id_W808) + 3., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W808) + 4., HOP4Y(8)},
-          {PIP_X(id_W808) + 4., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E804) + 4., HOP4Y(8), PIP_X(id_E804) + 4., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W808) + 5., HOP4Y(6)},
-          {PIP_X(id_W808) + 5., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W808) + 6., HOP4Y(4)},
-          {PIP_X(id_W808) + 6., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W808) + 7., HOP4Y(2)},
-          {PIP_X(id_W808) + 7., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
-          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
-          {wrap_len + 8., HOP4Y(1), PIP_X(id_W808) + 7., HOP4Y(1)},
-          {PIP_X(id_W808) + 7., HOP4Y(1), PIP_X(id_W808) + 7., WIRE_Y(0)}}},
-        {id_W80_loop0,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
-          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
-          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W808) + 0., HOP4Y(14)},
-          {PIP_X(id_W808) + 0., HOP4Y(14), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W808) + 1., HOP4Y(12)},
-          {PIP_X(id_W808) + 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W808) + 2., HOP4Y(10)},
-          {PIP_X(id_W808) + 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W808) + 3., HOP4Y(8)},
-          {PIP_X(id_W808) + 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6)},
-          {PIP_X(id_E804) + 3., HOP4Y(8), PIP_X(id_E804) + 3., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W808) + 4., HOP4Y(6)},
-          {PIP_X(id_W808) + 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W808) + 5., HOP4Y(4)},
-          {PIP_X(id_W808) + 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W808) + 6., HOP4Y(2)},
-          {PIP_X(id_W808) + 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E808) + 7., HOP4Y(0)},
-          {PIP_X(id_E808) + 7., HOP4Y(0), PIP_X(id_E808) + 7., WIRE_Y(0)}}},
-        {id_W80_loop1,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
-          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
-          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W808) - 1., HOP4Y(12)},
-          {PIP_X(id_W808) - 1., HOP4Y(12), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10)},
-          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W808) + 0., HOP4Y(10)},
-          {PIP_X(id_W808) + 0., HOP4Y(10), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W808) + 1., HOP4Y(8)},
-          {PIP_X(id_W808) + 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6)},
-          {PIP_X(id_E804) + 1., HOP4Y(8), PIP_X(id_E804) + 1., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W808) + 2., HOP4Y(6)},
-          {PIP_X(id_W808) + 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W808) + 3., HOP4Y(4)},
-          {PIP_X(id_W808) + 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W808) + 4., HOP4Y(2)},
-          {PIP_X(id_W808) + 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E808) + 5., HOP4Y(0)},
-          {PIP_X(id_E808) + 5., HOP4Y(0), PIP_X(id_E808) + 5., WIRE_Y(0)}}},
-        {id_W80_loop2,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
-          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
-          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W808) - 2., HOP4Y(10)},
-          {PIP_X(id_W808) - 2., HOP4Y(10), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8)},
-          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W808) - 1., HOP4Y(8)},
-          {PIP_X(id_W808) - 1., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6)},
-          {PIP_X(id_E804) - 1., HOP4Y(8), PIP_X(id_E804) - 1., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W808) + 0., HOP4Y(6)},
-          {PIP_X(id_W808) + 0., HOP4Y(6), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W808) + 1., HOP4Y(4)},
-          {PIP_X(id_W808) + 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W808) + 2., HOP4Y(2)},
-          {PIP_X(id_W808) + 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E808) + 3., HOP4Y(0)},
-          {PIP_X(id_E808) + 3., HOP4Y(0), PIP_X(id_E808) + 3., WIRE_Y(0)}}},
-        {id_W80_loop3,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
-          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
-          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W808) - 3., HOP4Y(8)},
-          {PIP_X(id_W808) - 3., HOP4Y(8), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6)},
-          {PIP_X(id_E804) - 3., HOP4Y(8), PIP_X(id_E804) - 3., WIRE_Y(0)},
-          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W808) - 2., HOP4Y(6)},
-          {PIP_X(id_W808) - 2., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W808) - 1., HOP4Y(4)},
-          {PIP_X(id_W808) - 1., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W808) + 0., HOP4Y(2)},
-          {PIP_X(id_W808) + 0., HOP4Y(2), PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E808) + 1., HOP4Y(0)},
-          {PIP_X(id_E808) + 1., HOP4Y(0), PIP_X(id_E808) + 1., WIRE_Y(0)}}},
-        {id_W80_loop4,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
-          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
-          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
-          {PIP_X(id_W804) - 4., HOP4Y(6), PIP_X(id_W804) - 4., WIRE_Y(0)},
-          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W808) - 4., HOP4Y(6)},
-          {PIP_X(id_W808) - 4., HOP4Y(6), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4)},
-          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W808) - 3., HOP4Y(4)},
-          {PIP_X(id_W808) - 3., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W808) - 2., HOP4Y(2)},
-          {PIP_X(id_W808) - 2., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E808) - 1., HOP4Y(0)},
-          {PIP_X(id_E808) - 1., HOP4Y(0), PIP_X(id_E808) - 1., WIRE_Y(0)}}},
-        {id_W80_loop5,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
-          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
-          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
-          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
-          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W808) - 5., HOP4Y(4)},
-          {PIP_X(id_W808) - 5., HOP4Y(4), PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2)},
-          {PIP_X(id_W808) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W808) - 4., HOP4Y(2)},
-          {PIP_X(id_W808) - 4., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E808) - 3., HOP4Y(0)},
-          {PIP_X(id_E808) - 3., HOP4Y(0), PIP_X(id_E808) - 3., WIRE_Y(0)}}},
-        {id_W80_loop6,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
-          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
-          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
-          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
-          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
-          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W808) - 6., HOP4Y(2)},
-          {PIP_X(id_W808) - 6., HOP4Y(2), PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0)},
-          {PIP_X(id_W808) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E808) - 5., HOP4Y(0)},
-          {PIP_X(id_E808) - 5., HOP4Y(0), PIP_X(id_E808) - 5., WIRE_Y(0)}}},
-        {id_W80_loop7,
-         {{PIP_X(id_W800), WIRE_Y(0), PIP_X(id_W800), HOP4Y(17)},
-          {PIP_X(id_W800) - 0., HOP4Y(17), PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W800) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W800) - 1., HOP4Y(15)},
-          {PIP_X(id_W800) - 1., HOP4Y(15), PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W800) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W800) - 2., HOP4Y(13)},
-          {PIP_X(id_W800) - 2., HOP4Y(13), PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W800) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W800) - 3., HOP4Y(11)},
-          {PIP_X(id_W800) - 3., HOP4Y(11), PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W800) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W800) - 4., HOP4Y(9)},
-          {PIP_X(id_W800) - 4., HOP4Y(9), PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W804) - 4., HOP4Y(9), PIP_X(id_W804) - 4., WIRE_Y(0)},
-          {PIP_X(id_W800) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W800) - 5., HOP4Y(7)},
-          {PIP_X(id_W800) - 5., HOP4Y(7), PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W800) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W800) - 6., HOP4Y(5)},
-          {PIP_X(id_W800) - 6., HOP4Y(5), PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W800) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W800) - 7., HOP4Y(3)},
-          {PIP_X(id_W800) - 7., HOP4Y(3), PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W800) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
-          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
-          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E808) - 7., HOP4Y(0)},
-          {PIP_X(id_E808) - 7., HOP4Y(0), PIP_X(id_E808) - 7., WIRE_Y(0)}}},
-
-#undef HOP4Y
-#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f)
-        {id_E81,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
-          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
-          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
-          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
-          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E818) + 8., HOP4Y(0)},
-          {PIP_X(id_E818) + 8, HOP4Y(0), PIP_X(id_E818) + 8., WIRE_Y(0)}}},
-        {id_W81,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
-          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
-          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
-          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
-          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W818) - 8., HOP4Y(1)},
-          {PIP_X(id_W818) - 8, HOP4Y(1), PIP_X(id_W818) - 8., WIRE_Y(0)}}},
-        {id_E81_loop0,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
-          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
-          {wrap_len + 1., HOP4Y(15), PIP_X(id_W810) - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - 0., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W810) - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W810) - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W810) - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7)},
-          {PIP_X(id_W814) - 3., HOP4Y(9), PIP_X(id_W814) - 3., WIRE_Y(0)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W810) - 4., HOP4Y(7)},
-          {PIP_X(id_W810) - 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W810) - 5., HOP4Y(5)},
-          {PIP_X(id_W810) - 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W810) - 6., HOP4Y(3)},
-          {PIP_X(id_W810) - 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W818) - 7., HOP4Y(1)},
-          {PIP_X(id_W818) - 7, HOP4Y(1), PIP_X(id_W818) - 7., WIRE_Y(0)}}},
-        {id_E81_loop1,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
-          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
-          {wrap_len + 2., HOP4Y(13), PIP_X(id_W810) + 1., HOP4Y(13)},
-          {PIP_X(id_W810) + 1., HOP4Y(13), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W810) - 0., HOP4Y(11)},
-          {PIP_X(id_W810) - 0., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W810) - 1., HOP4Y(9)},
-          {PIP_X(id_W814) - 1., HOP4Y(9), PIP_X(id_W814) - 1., WIRE_Y(0)},
-          {PIP_X(id_W810) - 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W810) - 2., HOP4Y(7)},
-          {PIP_X(id_W810) - 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W810) - 3., HOP4Y(5)},
-          {PIP_X(id_W810) - 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W810) - 4., HOP4Y(3)},
-          {PIP_X(id_W810) - 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W818) - 5., HOP4Y(1)},
-          {PIP_X(id_W818) - 5., HOP4Y(1), PIP_X(id_W818) - 5., WIRE_Y(0)}}},
-        {id_E81_loop2,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
-          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
-          {wrap_len + 3., HOP4Y(11), PIP_X(id_W810) + 2., HOP4Y(11)},
-          {PIP_X(id_W810) + 2., HOP4Y(11), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W810) + 1., HOP4Y(9)},
-          {PIP_X(id_W814) + 1., HOP4Y(9), PIP_X(id_W814) + 1., WIRE_Y(0)},
-          {PIP_X(id_W810) + 1., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7)},
-          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W810) + 0., HOP4Y(7)},
-          {PIP_X(id_W810) + 0., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W810) - 1., HOP4Y(5)},
-          {PIP_X(id_W810) - 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W810) - 2., HOP4Y(3)},
-          {PIP_X(id_W810) - 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W818) - 3., HOP4Y(1)},
-          {PIP_X(id_W818) - 3., HOP4Y(1), PIP_X(id_W818) - 3., WIRE_Y(0)}}},
-        {id_E81_loop3,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
-          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
-          {wrap_len + 4., HOP4Y(9), PIP_X(id_W810) + 3., HOP4Y(9)},
-          {PIP_X(id_W814) + 3., HOP4Y(9), PIP_X(id_W814) + 3., WIRE_Y(0)},
-          {PIP_X(id_W810) + 3., HOP4Y(9), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7)},
-          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W810) + 2., HOP4Y(7)},
-          {PIP_X(id_W810) + 2., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W810) + 1., HOP4Y(5)},
-          {PIP_X(id_W810) + 1., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W810) - 0., HOP4Y(3)},
-          {PIP_X(id_W810) - 0., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W818) - 1., HOP4Y(1)},
-          {PIP_X(id_W818) - 1., HOP4Y(1), PIP_X(id_W818) - 1., WIRE_Y(0)}}},
-        {id_E81_loop4,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
-          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
-          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
-          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
-          {wrap_len + 5., HOP4Y(7), PIP_X(id_W810) + 4., HOP4Y(7)},
-          {PIP_X(id_W810) + 4., HOP4Y(7), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W810) + 3., HOP4Y(5)},
-          {PIP_X(id_W810) + 3., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W810) + 2., HOP4Y(3)},
-          {PIP_X(id_W810) + 2., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W818) + 1., HOP4Y(1)},
-          {PIP_X(id_W818) + 1., HOP4Y(1), PIP_X(id_W818) + 1., WIRE_Y(0)}}},
-        {id_E81_loop5,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
-          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
-          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
-          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
-          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
-          {wrap_len + 6., HOP4Y(5), PIP_X(id_W810) + 5., HOP4Y(5)},
-          {PIP_X(id_W810) + 5., HOP4Y(5), PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W810) + 4., HOP4Y(3)},
-          {PIP_X(id_W810) + 4., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W818) + 3., HOP4Y(1)},
-          {PIP_X(id_W818) + 3., HOP4Y(1), PIP_X(id_W818) + 3., WIRE_Y(0)}}},
-        {id_E81_loop6,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
-          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
-          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
-          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
-          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
-          {wrap_len + 7., HOP4Y(3), PIP_X(id_W810) + 6., HOP4Y(3)},
-          {PIP_X(id_W810) + 6., HOP4Y(3), PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W818) + 5., HOP4Y(1)},
-          {PIP_X(id_W818) + 5., HOP4Y(1), PIP_X(id_W818) + 5., WIRE_Y(0)}}},
-        {id_E81_loop7,
-         {{PIP_X(id_E810), WIRE_Y(0), PIP_X(id_E810), HOP4Y(16)},
-          {PIP_X(id_E810), HOP4Y(16), PIP_X(id_W818), HOP4Y(16)},
-          {PIP_X(id_W818) + 0., HOP4Y(16), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W818) + 1., HOP4Y(14)},
-          {PIP_X(id_W818) + 1., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W818) + 2., HOP4Y(12)},
-          {PIP_X(id_W818) + 2., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W818) + 3., HOP4Y(10)},
-          {PIP_X(id_W818) + 3., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W818) + 4., HOP4Y(8)},
-          {PIP_X(id_W818) + 4., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E814) + 4., HOP4Y(8), PIP_X(id_E814) + 4., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W818) + 5., HOP4Y(6)},
-          {PIP_X(id_W818) + 5., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W818) + 6., HOP4Y(4)},
-          {PIP_X(id_W818) + 6., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W818) + 7., HOP4Y(2)},
-          {PIP_X(id_W818) + 7., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
-          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
-          {wrap_len + 8., HOP4Y(1), PIP_X(id_W818) + 7., HOP4Y(1)},
-          {PIP_X(id_W818) + 7., HOP4Y(1), PIP_X(id_W818) + 7., WIRE_Y(0)}}},
-        {id_W81_loop0,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
-          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
-          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W818) + 0., HOP4Y(14)},
-          {PIP_X(id_W818) + 0., HOP4Y(14), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W818) + 1., HOP4Y(12)},
-          {PIP_X(id_W818) + 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W818) + 2., HOP4Y(10)},
-          {PIP_X(id_W818) + 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W818) + 3., HOP4Y(8)},
-          {PIP_X(id_W818) + 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6)},
-          {PIP_X(id_E814) + 3., HOP4Y(8), PIP_X(id_E814) + 3., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W818) + 4., HOP4Y(6)},
-          {PIP_X(id_W818) + 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W818) + 5., HOP4Y(4)},
-          {PIP_X(id_W818) + 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W818) + 6., HOP4Y(2)},
-          {PIP_X(id_W818) + 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E818) + 7., HOP4Y(0)},
-          {PIP_X(id_E818) + 7., HOP4Y(0), PIP_X(id_E818) + 7., WIRE_Y(0)}}},
-        {id_W81_loop1,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
-          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
-          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W818) - 1., HOP4Y(12)},
-          {PIP_X(id_W818) - 1., HOP4Y(12), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10)},
-          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W818) + 0., HOP4Y(10)},
-          {PIP_X(id_W818) + 0., HOP4Y(10), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W818) + 1., HOP4Y(8)},
-          {PIP_X(id_W818) + 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6)},
-          {PIP_X(id_E814) + 1., HOP4Y(8), PIP_X(id_E814) + 1., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W818) + 2., HOP4Y(6)},
-          {PIP_X(id_W818) + 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W818) + 3., HOP4Y(4)},
-          {PIP_X(id_W818) + 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W818) + 4., HOP4Y(2)},
-          {PIP_X(id_W818) + 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E818) + 5., HOP4Y(0)},
-          {PIP_X(id_E818) + 5., HOP4Y(0), PIP_X(id_E818) + 5., WIRE_Y(0)}}},
-        {id_W81_loop2,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
-          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
-          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W818) - 2., HOP4Y(10)},
-          {PIP_X(id_W818) - 2., HOP4Y(10), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8)},
-          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W818) - 1., HOP4Y(8)},
-          {PIP_X(id_W818) - 1., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6)},
-          {PIP_X(id_E814) - 1., HOP4Y(8), PIP_X(id_E814) - 1., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W818) + 0., HOP4Y(6)},
-          {PIP_X(id_W818) + 0., HOP4Y(6), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W818) + 1., HOP4Y(4)},
-          {PIP_X(id_W818) + 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W818) + 2., HOP4Y(2)},
-          {PIP_X(id_W818) + 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E818) + 3., HOP4Y(0)},
-          {PIP_X(id_E818) + 3., HOP4Y(0), PIP_X(id_E818) + 3., WIRE_Y(0)}}},
-        {id_W81_loop3,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
-          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
-          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W818) - 3., HOP4Y(8)},
-          {PIP_X(id_W818) - 3., HOP4Y(8), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6)},
-          {PIP_X(id_E814) - 3., HOP4Y(8), PIP_X(id_E814) - 3., WIRE_Y(0)},
-          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W818) - 2., HOP4Y(6)},
-          {PIP_X(id_W818) - 2., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W818) - 1., HOP4Y(4)},
-          {PIP_X(id_W818) - 1., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W818) + 0., HOP4Y(2)},
-          {PIP_X(id_W818) + 0., HOP4Y(2), PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E818) + 1., HOP4Y(0)},
-          {PIP_X(id_E818) + 1., HOP4Y(0), PIP_X(id_E818) + 1., WIRE_Y(0)}}},
-        {id_W81_loop4,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
-          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
-          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
-          {PIP_X(id_W814) - 4., HOP4Y(6), PIP_X(id_W814) - 4., WIRE_Y(0)},
-          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W818) - 4., HOP4Y(6)},
-          {PIP_X(id_W818) - 4., HOP4Y(6), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4)},
-          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W818) - 3., HOP4Y(4)},
-          {PIP_X(id_W818) - 3., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W818) - 2., HOP4Y(2)},
-          {PIP_X(id_W818) - 2., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E818) - 1., HOP4Y(0)},
-          {PIP_X(id_E818) - 1., HOP4Y(0), PIP_X(id_E818) - 1., WIRE_Y(0)}}},
-        {id_W81_loop5,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
-          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
-          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
-          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
-          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W818) - 5., HOP4Y(4)},
-          {PIP_X(id_W818) - 5., HOP4Y(4), PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2)},
-          {PIP_X(id_W818) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W818) - 4., HOP4Y(2)},
-          {PIP_X(id_W818) - 4., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E818) - 3., HOP4Y(0)},
-          {PIP_X(id_E818) - 3., HOP4Y(0), PIP_X(id_E818) - 3., WIRE_Y(0)}}},
-        {id_W81_loop6,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
-          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
-          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
-          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
-          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
-          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W818) - 6., HOP4Y(2)},
-          {PIP_X(id_W818) - 6., HOP4Y(2), PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0)},
-          {PIP_X(id_W818) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E818) - 5., HOP4Y(0)},
-          {PIP_X(id_E818) - 5., HOP4Y(0), PIP_X(id_E818) - 5., WIRE_Y(0)}}},
-        {id_W81_loop7,
-         {{PIP_X(id_W810), WIRE_Y(0), PIP_X(id_W810), HOP4Y(17)},
-          {PIP_X(id_W810) - 0., HOP4Y(17), PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W810) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W810) - 1., HOP4Y(15)},
-          {PIP_X(id_W810) - 1., HOP4Y(15), PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W810) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W810) - 2., HOP4Y(13)},
-          {PIP_X(id_W810) - 2., HOP4Y(13), PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W810) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W810) - 3., HOP4Y(11)},
-          {PIP_X(id_W810) - 3., HOP4Y(11), PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W810) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W810) - 4., HOP4Y(9)},
-          {PIP_X(id_W810) - 4., HOP4Y(9), PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W814) - 4., HOP4Y(9), PIP_X(id_W814) - 4., WIRE_Y(0)},
-          {PIP_X(id_W810) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W810) - 5., HOP4Y(7)},
-          {PIP_X(id_W810) - 5., HOP4Y(7), PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W810) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W810) - 6., HOP4Y(5)},
-          {PIP_X(id_W810) - 6., HOP4Y(5), PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W810) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W810) - 7., HOP4Y(3)},
-          {PIP_X(id_W810) - 7., HOP4Y(3), PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W810) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
-          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
-          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E818) - 7., HOP4Y(0)},
-          {PIP_X(id_E818) - 7., HOP4Y(0), PIP_X(id_E818) - 7., WIRE_Y(0)}}},
-
-#undef HOP4Y
-#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f)
-        {id_E82,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
-          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
-          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
-          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
-          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E828) + 8., HOP4Y(0)},
-          {PIP_X(id_E828) + 8, HOP4Y(0), PIP_X(id_E828) + 8., WIRE_Y(0)}}},
-        {id_W82,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
-          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
-          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
-          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
-          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W828) - 8., HOP4Y(1)},
-          {PIP_X(id_W828) - 8, HOP4Y(1), PIP_X(id_W828) - 8., WIRE_Y(0)}}},
-        {id_E82_loop0,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
-          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
-          {wrap_len + 1., HOP4Y(15), PIP_X(id_W820) - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - 0., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W820) - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W820) - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W820) - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7)},
-          {PIP_X(id_W824) - 3., HOP4Y(9), PIP_X(id_W824) - 3., WIRE_Y(0)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W820) - 4., HOP4Y(7)},
-          {PIP_X(id_W820) - 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W820) - 5., HOP4Y(5)},
-          {PIP_X(id_W820) - 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W820) - 6., HOP4Y(3)},
-          {PIP_X(id_W820) - 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W828) - 7., HOP4Y(1)},
-          {PIP_X(id_W828) - 7, HOP4Y(1), PIP_X(id_W828) - 7., WIRE_Y(0)}}},
-        {id_E82_loop1,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
-          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
-          {wrap_len + 2., HOP4Y(13), PIP_X(id_W820) + 1., HOP4Y(13)},
-          {PIP_X(id_W820) + 1., HOP4Y(13), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W820) - 0., HOP4Y(11)},
-          {PIP_X(id_W820) - 0., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W820) - 1., HOP4Y(9)},
-          {PIP_X(id_W824) - 1., HOP4Y(9), PIP_X(id_W824) - 1., WIRE_Y(0)},
-          {PIP_X(id_W820) - 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W820) - 2., HOP4Y(7)},
-          {PIP_X(id_W820) - 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W820) - 3., HOP4Y(5)},
-          {PIP_X(id_W820) - 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W820) - 4., HOP4Y(3)},
-          {PIP_X(id_W820) - 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W828) - 5., HOP4Y(1)},
-          {PIP_X(id_W828) - 5., HOP4Y(1), PIP_X(id_W828) - 5., WIRE_Y(0)}}},
-        {id_E82_loop2,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
-          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
-          {wrap_len + 3., HOP4Y(11), PIP_X(id_W820) + 2., HOP4Y(11)},
-          {PIP_X(id_W820) + 2., HOP4Y(11), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W820) + 1., HOP4Y(9)},
-          {PIP_X(id_W824) + 1., HOP4Y(9), PIP_X(id_W824) + 1., WIRE_Y(0)},
-          {PIP_X(id_W820) + 1., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7)},
-          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W820) + 0., HOP4Y(7)},
-          {PIP_X(id_W820) + 0., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W820) - 1., HOP4Y(5)},
-          {PIP_X(id_W820) - 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W820) - 2., HOP4Y(3)},
-          {PIP_X(id_W820) - 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W828) - 3., HOP4Y(1)},
-          {PIP_X(id_W828) - 3., HOP4Y(1), PIP_X(id_W828) - 3., WIRE_Y(0)}}},
-        {id_E82_loop3,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
-          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
-          {wrap_len + 4., HOP4Y(9), PIP_X(id_W820) + 3., HOP4Y(9)},
-          {PIP_X(id_W824) + 3., HOP4Y(9), PIP_X(id_W824) + 3., WIRE_Y(0)},
-          {PIP_X(id_W820) + 3., HOP4Y(9), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7)},
-          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W820) + 2., HOP4Y(7)},
-          {PIP_X(id_W820) + 2., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W820) + 1., HOP4Y(5)},
-          {PIP_X(id_W820) + 1., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W820) - 0., HOP4Y(3)},
-          {PIP_X(id_W820) - 0., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W828) - 1., HOP4Y(1)},
-          {PIP_X(id_W828) - 1., HOP4Y(1), PIP_X(id_W828) - 1., WIRE_Y(0)}}},
-        {id_E82_loop4,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
-          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
-          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
-          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
-          {wrap_len + 5., HOP4Y(7), PIP_X(id_W820) + 4., HOP4Y(7)},
-          {PIP_X(id_W820) + 4., HOP4Y(7), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W820) + 3., HOP4Y(5)},
-          {PIP_X(id_W820) + 3., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W820) + 2., HOP4Y(3)},
-          {PIP_X(id_W820) + 2., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W828) + 1., HOP4Y(1)},
-          {PIP_X(id_W828) + 1., HOP4Y(1), PIP_X(id_W828) + 1., WIRE_Y(0)}}},
-        {id_E82_loop5,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
-          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
-          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
-          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
-          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
-          {wrap_len + 6., HOP4Y(5), PIP_X(id_W820) + 5., HOP4Y(5)},
-          {PIP_X(id_W820) + 5., HOP4Y(5), PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W820) + 4., HOP4Y(3)},
-          {PIP_X(id_W820) + 4., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W828) + 3., HOP4Y(1)},
-          {PIP_X(id_W828) + 3., HOP4Y(1), PIP_X(id_W828) + 3., WIRE_Y(0)}}},
-        {id_E82_loop6,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
-          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
-          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
-          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
-          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
-          {wrap_len + 7., HOP4Y(3), PIP_X(id_W820) + 6., HOP4Y(3)},
-          {PIP_X(id_W820) + 6., HOP4Y(3), PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W828) + 5., HOP4Y(1)},
-          {PIP_X(id_W828) + 5., HOP4Y(1), PIP_X(id_W828) + 5., WIRE_Y(0)}}},
-        {id_E82_loop7,
-         {{PIP_X(id_E820), WIRE_Y(0), PIP_X(id_E820), HOP4Y(16)},
-          {PIP_X(id_E820), HOP4Y(16), PIP_X(id_W828), HOP4Y(16)},
-          {PIP_X(id_W828) + 0., HOP4Y(16), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W828) + 1., HOP4Y(14)},
-          {PIP_X(id_W828) + 1., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W828) + 2., HOP4Y(12)},
-          {PIP_X(id_W828) + 2., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W828) + 3., HOP4Y(10)},
-          {PIP_X(id_W828) + 3., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W828) + 4., HOP4Y(8)},
-          {PIP_X(id_W828) + 4., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E824) + 4., HOP4Y(8), PIP_X(id_E824) + 4., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W828) + 5., HOP4Y(6)},
-          {PIP_X(id_W828) + 5., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W828) + 6., HOP4Y(4)},
-          {PIP_X(id_W828) + 6., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W828) + 7., HOP4Y(2)},
-          {PIP_X(id_W828) + 7., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
-          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
-          {wrap_len + 8., HOP4Y(1), PIP_X(id_W828) + 7., HOP4Y(1)},
-          {PIP_X(id_W828) + 7., HOP4Y(1), PIP_X(id_W828) + 7., WIRE_Y(0)}}},
-        {id_W82_loop0,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
-          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
-          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W828) + 0., HOP4Y(14)},
-          {PIP_X(id_W828) + 0., HOP4Y(14), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W828) + 1., HOP4Y(12)},
-          {PIP_X(id_W828) + 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W828) + 2., HOP4Y(10)},
-          {PIP_X(id_W828) + 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W828) + 3., HOP4Y(8)},
-          {PIP_X(id_W828) + 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6)},
-          {PIP_X(id_E824) + 3., HOP4Y(8), PIP_X(id_E824) + 3., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W828) + 4., HOP4Y(6)},
-          {PIP_X(id_W828) + 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W828) + 5., HOP4Y(4)},
-          {PIP_X(id_W828) + 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W828) + 6., HOP4Y(2)},
-          {PIP_X(id_W828) + 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E828) + 7., HOP4Y(0)},
-          {PIP_X(id_E828) + 7., HOP4Y(0), PIP_X(id_E828) + 7., WIRE_Y(0)}}},
-        {id_W82_loop1,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
-          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
-          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W828) - 1., HOP4Y(12)},
-          {PIP_X(id_W828) - 1., HOP4Y(12), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10)},
-          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W828) + 0., HOP4Y(10)},
-          {PIP_X(id_W828) + 0., HOP4Y(10), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W828) + 1., HOP4Y(8)},
-          {PIP_X(id_W828) + 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6)},
-          {PIP_X(id_E824) + 1., HOP4Y(8), PIP_X(id_E824) + 1., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W828) + 2., HOP4Y(6)},
-          {PIP_X(id_W828) + 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W828) + 3., HOP4Y(4)},
-          {PIP_X(id_W828) + 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W828) + 4., HOP4Y(2)},
-          {PIP_X(id_W828) + 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E828) + 5., HOP4Y(0)},
-          {PIP_X(id_E828) + 5., HOP4Y(0), PIP_X(id_E828) + 5., WIRE_Y(0)}}},
-        {id_W82_loop2,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
-          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
-          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W828) - 2., HOP4Y(10)},
-          {PIP_X(id_W828) - 2., HOP4Y(10), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8)},
-          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W828) - 1., HOP4Y(8)},
-          {PIP_X(id_W828) - 1., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6)},
-          {PIP_X(id_E824) - 1., HOP4Y(8), PIP_X(id_E824) - 1., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W828) + 0., HOP4Y(6)},
-          {PIP_X(id_W828) + 0., HOP4Y(6), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W828) + 1., HOP4Y(4)},
-          {PIP_X(id_W828) + 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W828) + 2., HOP4Y(2)},
-          {PIP_X(id_W828) + 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E828) + 3., HOP4Y(0)},
-          {PIP_X(id_E828) + 3., HOP4Y(0), PIP_X(id_E828) + 3., WIRE_Y(0)}}},
-        {id_W82_loop3,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
-          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
-          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W828) - 3., HOP4Y(8)},
-          {PIP_X(id_W828) - 3., HOP4Y(8), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6)},
-          {PIP_X(id_E824) - 3., HOP4Y(8), PIP_X(id_E824) - 3., WIRE_Y(0)},
-          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W828) - 2., HOP4Y(6)},
-          {PIP_X(id_W828) - 2., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W828) - 1., HOP4Y(4)},
-          {PIP_X(id_W828) - 1., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W828) + 0., HOP4Y(2)},
-          {PIP_X(id_W828) + 0., HOP4Y(2), PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E828) + 1., HOP4Y(0)},
-          {PIP_X(id_E828) + 1., HOP4Y(0), PIP_X(id_E828) + 1., WIRE_Y(0)}}},
-        {id_W82_loop4,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
-          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
-          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
-          {PIP_X(id_W824) - 4., HOP4Y(6), PIP_X(id_W824) - 4., WIRE_Y(0)},
-          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W828) - 4., HOP4Y(6)},
-          {PIP_X(id_W828) - 4., HOP4Y(6), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4)},
-          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W828) - 3., HOP4Y(4)},
-          {PIP_X(id_W828) - 3., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W828) - 2., HOP4Y(2)},
-          {PIP_X(id_W828) - 2., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E828) - 1., HOP4Y(0)},
-          {PIP_X(id_E828) - 1., HOP4Y(0), PIP_X(id_E828) - 1., WIRE_Y(0)}}},
-        {id_W82_loop5,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
-          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
-          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
-          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
-          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W828) - 5., HOP4Y(4)},
-          {PIP_X(id_W828) - 5., HOP4Y(4), PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2)},
-          {PIP_X(id_W828) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W828) - 4., HOP4Y(2)},
-          {PIP_X(id_W828) - 4., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E828) - 3., HOP4Y(0)},
-          {PIP_X(id_E828) - 3., HOP4Y(0), PIP_X(id_E828) - 3., WIRE_Y(0)}}},
-        {id_W82_loop6,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
-          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
-          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
-          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
-          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
-          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W828) - 6., HOP4Y(2)},
-          {PIP_X(id_W828) - 6., HOP4Y(2), PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0)},
-          {PIP_X(id_W828) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E828) - 5., HOP4Y(0)},
-          {PIP_X(id_E828) - 5., HOP4Y(0), PIP_X(id_E828) - 5., WIRE_Y(0)}}},
-        {id_W82_loop7,
-         {{PIP_X(id_W820), WIRE_Y(0), PIP_X(id_W820), HOP4Y(17)},
-          {PIP_X(id_W820) - 0., HOP4Y(17), PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W820) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W820) - 1., HOP4Y(15)},
-          {PIP_X(id_W820) - 1., HOP4Y(15), PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W820) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W820) - 2., HOP4Y(13)},
-          {PIP_X(id_W820) - 2., HOP4Y(13), PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W820) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W820) - 3., HOP4Y(11)},
-          {PIP_X(id_W820) - 3., HOP4Y(11), PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W820) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W820) - 4., HOP4Y(9)},
-          {PIP_X(id_W820) - 4., HOP4Y(9), PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W824) - 4., HOP4Y(9), PIP_X(id_W824) - 4., WIRE_Y(0)},
-          {PIP_X(id_W820) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W820) - 5., HOP4Y(7)},
-          {PIP_X(id_W820) - 5., HOP4Y(7), PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W820) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W820) - 6., HOP4Y(5)},
-          {PIP_X(id_W820) - 6., HOP4Y(5), PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W820) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W820) - 7., HOP4Y(3)},
-          {PIP_X(id_W820) - 7., HOP4Y(3), PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W820) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
-          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
-          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E828) - 7., HOP4Y(0)},
-          {PIP_X(id_E828) - 7., HOP4Y(0), PIP_X(id_E828) - 7., WIRE_Y(0)}}},
-
-#undef HOP4Y
-#define HOP4Y(offset) WIRE_Y((float)offset + HOP4Y_START + 18.f + 18.f + 18.f)
-        {id_E83,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
-          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
-          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
-          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
-          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), PIP_X(id_E838) + 8., HOP4Y(0)},
-          {PIP_X(id_E838) + 8, HOP4Y(0), PIP_X(id_E838) + 8., WIRE_Y(0)}}},
-        {id_W83,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
-          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
-          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
-          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
-          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), PIP_X(id_W838) - 8., HOP4Y(1)},
-          {PIP_X(id_W838) - 8, HOP4Y(1), PIP_X(id_W838) - 8., WIRE_Y(0)}}},
-        {id_E83_loop0,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), wrap_len + 1., HOP4Y(14)},
-          {wrap_len + 1., HOP4Y(14), wrap_len + 1., HOP4Y(15)},
-          {wrap_len + 1., HOP4Y(15), PIP_X(id_W830) - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - 0., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(13), PIP_X(id_W830) - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(11), PIP_X(id_W830) - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(9), PIP_X(id_W830) - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7)},
-          {PIP_X(id_W834) - 3., HOP4Y(9), PIP_X(id_W834) - 3., WIRE_Y(0)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(7), PIP_X(id_W830) - 4., HOP4Y(7)},
-          {PIP_X(id_W830) - 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(5), PIP_X(id_W830) - 5., HOP4Y(5)},
-          {PIP_X(id_W830) - 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(3), PIP_X(id_W830) - 6., HOP4Y(3)},
-          {PIP_X(id_W830) - 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(1), PIP_X(id_W838) - 7., HOP4Y(1)},
-          {PIP_X(id_W838) - 7, HOP4Y(1), PIP_X(id_W838) - 7., WIRE_Y(0)}}},
-        {id_E83_loop1,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), wrap_len + 2., HOP4Y(12)},
-          {wrap_len + 2., HOP4Y(12), wrap_len + 2., HOP4Y(13)},
-          {wrap_len + 2., HOP4Y(13), PIP_X(id_W830) + 1., HOP4Y(13)},
-          {PIP_X(id_W830) + 1., HOP4Y(13), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(11), PIP_X(id_W830) - 0., HOP4Y(11)},
-          {PIP_X(id_W830) - 0., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(9), PIP_X(id_W830) - 1., HOP4Y(9)},
-          {PIP_X(id_W834) - 1., HOP4Y(9), PIP_X(id_W834) - 1., WIRE_Y(0)},
-          {PIP_X(id_W830) - 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(7), PIP_X(id_W830) - 2., HOP4Y(7)},
-          {PIP_X(id_W830) - 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(5), PIP_X(id_W830) - 3., HOP4Y(5)},
-          {PIP_X(id_W830) - 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(3), PIP_X(id_W830) - 4., HOP4Y(3)},
-          {PIP_X(id_W830) - 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(1), PIP_X(id_W838) - 5., HOP4Y(1)},
-          {PIP_X(id_W838) - 5., HOP4Y(1), PIP_X(id_W838) - 5., WIRE_Y(0)}}},
-        {id_E83_loop2,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), wrap_len + 3., HOP4Y(10)},
-          {wrap_len + 3., HOP4Y(10), wrap_len + 3., HOP4Y(11)},
-          {wrap_len + 3., HOP4Y(11), PIP_X(id_W830) + 2., HOP4Y(11)},
-          {PIP_X(id_W830) + 2., HOP4Y(11), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(9), PIP_X(id_W830) + 1., HOP4Y(9)},
-          {PIP_X(id_W834) + 1., HOP4Y(9), PIP_X(id_W834) + 1., WIRE_Y(0)},
-          {PIP_X(id_W830) + 1., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7)},
-          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(7), PIP_X(id_W830) + 0., HOP4Y(7)},
-          {PIP_X(id_W830) + 0., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(5), PIP_X(id_W830) - 1., HOP4Y(5)},
-          {PIP_X(id_W830) - 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(3), PIP_X(id_W830) - 2., HOP4Y(3)},
-          {PIP_X(id_W830) - 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(1), PIP_X(id_W838) - 3., HOP4Y(1)},
-          {PIP_X(id_W838) - 3., HOP4Y(1), PIP_X(id_W838) - 3., WIRE_Y(0)}}},
-        {id_E83_loop3,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), wrap_len + 4., HOP4Y(8)},
-          {wrap_len + 4., HOP4Y(8), wrap_len + 4., HOP4Y(9)},
-          {wrap_len + 4., HOP4Y(9), PIP_X(id_W830) + 3., HOP4Y(9)},
-          {PIP_X(id_W834) + 3., HOP4Y(9), PIP_X(id_W834) + 3., WIRE_Y(0)},
-          {PIP_X(id_W830) + 3., HOP4Y(9), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7)},
-          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(7), PIP_X(id_W830) + 2., HOP4Y(7)},
-          {PIP_X(id_W830) + 2., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(5), PIP_X(id_W830) + 1., HOP4Y(5)},
-          {PIP_X(id_W830) + 1., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist + 1., HOP4Y(3), PIP_X(id_W830) - 0., HOP4Y(3)},
-          {PIP_X(id_W830) - 0., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(1), PIP_X(id_W838) - 1., HOP4Y(1)},
-          {PIP_X(id_W838) - 1., HOP4Y(1), PIP_X(id_W838) - 1., WIRE_Y(0)}}},
-        {id_E83_loop4,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
-          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
-          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), wrap_len + 5., HOP4Y(6)},
-          {wrap_len + 5., HOP4Y(6), wrap_len + 5., HOP4Y(7)},
-          {wrap_len + 5., HOP4Y(7), PIP_X(id_W830) + 4., HOP4Y(7)},
-          {PIP_X(id_W830) + 4., HOP4Y(7), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(5), PIP_X(id_W830) + 3., HOP4Y(5)},
-          {PIP_X(id_W830) + 3., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist + 3., HOP4Y(3), PIP_X(id_W830) + 2., HOP4Y(3)},
-          {PIP_X(id_W830) + 2., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist + 2., HOP4Y(1), PIP_X(id_W838) + 1., HOP4Y(1)},
-          {PIP_X(id_W838) + 1., HOP4Y(1), PIP_X(id_W838) + 1., WIRE_Y(0)}}},
-        {id_E83_loop5,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
-          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
-          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
-          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), wrap_len + 6., HOP4Y(4)},
-          {wrap_len + 6., HOP4Y(4), wrap_len + 6., HOP4Y(5)},
-          {wrap_len + 6., HOP4Y(5), PIP_X(id_W830) + 5., HOP4Y(5)},
-          {PIP_X(id_W830) + 5., HOP4Y(5), PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist + 5., HOP4Y(3), PIP_X(id_W830) + 4., HOP4Y(3)},
-          {PIP_X(id_W830) + 4., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist + 4., HOP4Y(1), PIP_X(id_W838) + 3., HOP4Y(1)},
-          {PIP_X(id_W838) + 3., HOP4Y(1), PIP_X(id_W838) + 3., WIRE_Y(0)}}},
-        {id_E83_loop6,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
-          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
-          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
-          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), wrap_len + 7., HOP4Y(2)},
-          {wrap_len + 7., HOP4Y(2), wrap_len + 7., HOP4Y(3)},
-          {wrap_len + 7., HOP4Y(3), PIP_X(id_W830) + 6., HOP4Y(3)},
-          {PIP_X(id_W830) + 6., HOP4Y(3), PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist + 6., HOP4Y(1), PIP_X(id_W838) + 5., HOP4Y(1)},
-          {PIP_X(id_W838) + 5., HOP4Y(1), PIP_X(id_W838) + 5., WIRE_Y(0)}}},
-        {id_E83_loop7,
-         {{PIP_X(id_E830), WIRE_Y(0), PIP_X(id_E830), HOP4Y(16)},
-          {PIP_X(id_E830), HOP4Y(16), PIP_X(id_W838), HOP4Y(16)},
-          {PIP_X(id_W838) + 0., HOP4Y(16), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(14), PIP_X(id_W838) + 1., HOP4Y(14)},
-          {PIP_X(id_W838) + 1., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(12), PIP_X(id_W838) + 2., HOP4Y(12)},
-          {PIP_X(id_W838) + 2., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(10), PIP_X(id_W838) + 3., HOP4Y(10)},
-          {PIP_X(id_W838) + 3., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(8), PIP_X(id_W838) + 4., HOP4Y(8)},
-          {PIP_X(id_W838) + 4., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6)},
-          {PIP_X(id_E834) + 4., HOP4Y(8), PIP_X(id_E834) + 4., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(6), PIP_X(id_W838) + 5., HOP4Y(6)},
-          {PIP_X(id_W838) + 5., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(4), PIP_X(id_W838) + 6., HOP4Y(4)},
-          {PIP_X(id_W838) + 6., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(2), PIP_X(id_W838) + 7., HOP4Y(2)},
-          {PIP_X(id_W838) + 7., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 7., HOP4Y(0), wrap_len + 8., HOP4Y(0)},
-          {wrap_len + 8., HOP4Y(0), wrap_len + 8., HOP4Y(1)},
-          {wrap_len + 8., HOP4Y(1), PIP_X(id_W838) + 7., HOP4Y(1)},
-          {PIP_X(id_W838) + 7., HOP4Y(1), PIP_X(id_W838) + 7., WIRE_Y(0)}}},
-        {id_W83_loop0,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(15)},
-          {-wrap_len - 0., HOP4Y(15), -wrap_len - 0., HOP4Y(14)},
-          {-wrap_len - 0., HOP4Y(14), PIP_X(id_W838) + 0., HOP4Y(14)},
-          {PIP_X(id_W838) + 0., HOP4Y(14), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(12), PIP_X(id_W838) + 1., HOP4Y(12)},
-          {PIP_X(id_W838) + 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(10), PIP_X(id_W838) + 2., HOP4Y(10)},
-          {PIP_X(id_W838) + 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(8), PIP_X(id_W838) + 3., HOP4Y(8)},
-          {PIP_X(id_W838) + 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6)},
-          {PIP_X(id_E834) + 3., HOP4Y(8), PIP_X(id_E834) + 3., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(6), PIP_X(id_W838) + 4., HOP4Y(6)},
-          {PIP_X(id_W838) + 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(4), PIP_X(id_W838) + 5., HOP4Y(4)},
-          {PIP_X(id_W838) + 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 5., HOP4Y(2), PIP_X(id_W838) + 6., HOP4Y(2)},
-          {PIP_X(id_W838) + 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 6., HOP4Y(0), PIP_X(id_E838) + 7., HOP4Y(0)},
-          {PIP_X(id_E838) + 7., HOP4Y(0), PIP_X(id_E838) + 7., WIRE_Y(0)}}},
-        {id_W83_loop1,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(13)},
-          {-wrap_len - 1., HOP4Y(13), -wrap_len - 1., HOP4Y(12)},
-          {-wrap_len - 1., HOP4Y(12), PIP_X(id_W838) - 1., HOP4Y(12)},
-          {PIP_X(id_W838) - 1., HOP4Y(12), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10)},
-          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(10), PIP_X(id_W838) + 0., HOP4Y(10)},
-          {PIP_X(id_W838) + 0., HOP4Y(10), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(8), PIP_X(id_W838) + 1., HOP4Y(8)},
-          {PIP_X(id_W838) + 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6)},
-          {PIP_X(id_E834) + 1., HOP4Y(8), PIP_X(id_E834) + 1., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(6), PIP_X(id_W838) + 2., HOP4Y(6)},
-          {PIP_X(id_W838) + 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(4), PIP_X(id_W838) + 3., HOP4Y(4)},
-          {PIP_X(id_W838) + 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 3., HOP4Y(2), PIP_X(id_W838) + 4., HOP4Y(2)},
-          {PIP_X(id_W838) + 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 4., HOP4Y(0), PIP_X(id_E838) + 5., HOP4Y(0)},
-          {PIP_X(id_E838) + 5., HOP4Y(0), PIP_X(id_E838) + 5., WIRE_Y(0)}}},
-        {id_W83_loop2,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(11)},
-          {-wrap_len - 2., HOP4Y(11), -wrap_len - 2., HOP4Y(10)},
-          {-wrap_len - 2., HOP4Y(10), PIP_X(id_W838) - 2., HOP4Y(10)},
-          {PIP_X(id_W838) - 2., HOP4Y(10), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8)},
-          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(8), PIP_X(id_W838) - 1., HOP4Y(8)},
-          {PIP_X(id_W838) - 1., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6)},
-          {PIP_X(id_E834) - 1., HOP4Y(8), PIP_X(id_E834) - 1., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(6), PIP_X(id_W838) + 0., HOP4Y(6)},
-          {PIP_X(id_W838) + 0., HOP4Y(6), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(4), PIP_X(id_W838) + 1., HOP4Y(4)},
-          {PIP_X(id_W838) + 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist + 1., HOP4Y(2), PIP_X(id_W838) + 2., HOP4Y(2)},
-          {PIP_X(id_W838) + 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 2., HOP4Y(0), PIP_X(id_E838) + 3., HOP4Y(0)},
-          {PIP_X(id_E838) + 3., HOP4Y(0), PIP_X(id_E838) + 3., WIRE_Y(0)}}},
-        {id_W83_loop3,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(9)},
-          {-wrap_len - 3., HOP4Y(9), -wrap_len - 3., HOP4Y(8)},
-          {-wrap_len - 3., HOP4Y(8), PIP_X(id_W838) - 3., HOP4Y(8)},
-          {PIP_X(id_W838) - 3., HOP4Y(8), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6)},
-          {PIP_X(id_E834) - 3., HOP4Y(8), PIP_X(id_E834) - 3., WIRE_Y(0)},
-          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(6), PIP_X(id_W838) - 2., HOP4Y(6)},
-          {PIP_X(id_W838) - 2., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(4), PIP_X(id_W838) - 1., HOP4Y(4)},
-          {PIP_X(id_W838) - 1., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist - 1., HOP4Y(2), PIP_X(id_W838) + 0., HOP4Y(2)},
-          {PIP_X(id_W838) + 0., HOP4Y(2), PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist + 0., HOP4Y(0), PIP_X(id_E838) + 1., HOP4Y(0)},
-          {PIP_X(id_E838) + 1., HOP4Y(0), PIP_X(id_E838) + 1., WIRE_Y(0)}}},
-        {id_W83_loop4,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
-          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(7)},
-          {-wrap_len - 4., HOP4Y(7), -wrap_len - 4., HOP4Y(6)},
-          {PIP_X(id_W834) - 4., HOP4Y(6), PIP_X(id_W834) - 4., WIRE_Y(0)},
-          {-wrap_len - 4., HOP4Y(6), PIP_X(id_W838) - 4., HOP4Y(6)},
-          {PIP_X(id_W838) - 4., HOP4Y(6), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4)},
-          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(4), PIP_X(id_W838) - 3., HOP4Y(4)},
-          {PIP_X(id_W838) - 3., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist - 3., HOP4Y(2), PIP_X(id_W838) - 2., HOP4Y(2)},
-          {PIP_X(id_W838) - 2., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist - 2., HOP4Y(0), PIP_X(id_E838) - 1., HOP4Y(0)},
-          {PIP_X(id_E838) - 1., HOP4Y(0), PIP_X(id_E838) - 1., WIRE_Y(0)}}},
-        {id_W83_loop5,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
-          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
-          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(5)},
-          {-wrap_len - 5., HOP4Y(5), -wrap_len - 5., HOP4Y(4)},
-          {-wrap_len - 5., HOP4Y(4), PIP_X(id_W838) - 5., HOP4Y(4)},
-          {PIP_X(id_W838) - 5., HOP4Y(4), PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2)},
-          {PIP_X(id_W838) + top_wire_dist - 5., HOP4Y(2), PIP_X(id_W838) - 4., HOP4Y(2)},
-          {PIP_X(id_W838) - 4., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist - 4., HOP4Y(0), PIP_X(id_E838) - 3., HOP4Y(0)},
-          {PIP_X(id_E838) - 3., HOP4Y(0), PIP_X(id_E838) - 3., WIRE_Y(0)}}},
-        {id_W83_loop6,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
-          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
-          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
-          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(3)},
-          {-wrap_len - 6., HOP4Y(3), -wrap_len - 6., HOP4Y(2)},
-          {-wrap_len - 6., HOP4Y(2), PIP_X(id_W838) - 6., HOP4Y(2)},
-          {PIP_X(id_W838) - 6., HOP4Y(2), PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0)},
-          {PIP_X(id_W838) + top_wire_dist - 6., HOP4Y(0), PIP_X(id_E838) - 5., HOP4Y(0)},
-          {PIP_X(id_E838) - 5., HOP4Y(0), PIP_X(id_E838) - 5., WIRE_Y(0)}}},
-        {id_W83_loop7,
-         {{PIP_X(id_W830), WIRE_Y(0), PIP_X(id_W830), HOP4Y(17)},
-          {PIP_X(id_W830) - 0., HOP4Y(17), PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15)},
-          {PIP_X(id_W830) - top_wire_dist - 0., HOP4Y(15), PIP_X(id_W830) - 1., HOP4Y(15)},
-          {PIP_X(id_W830) - 1., HOP4Y(15), PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13)},
-          {PIP_X(id_W830) - top_wire_dist - 1., HOP4Y(13), PIP_X(id_W830) - 2., HOP4Y(13)},
-          {PIP_X(id_W830) - 2., HOP4Y(13), PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11)},
-          {PIP_X(id_W830) - top_wire_dist - 2., HOP4Y(11), PIP_X(id_W830) - 3., HOP4Y(11)},
-          {PIP_X(id_W830) - 3., HOP4Y(11), PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9)},
-          {PIP_X(id_W830) - top_wire_dist - 3., HOP4Y(9), PIP_X(id_W830) - 4., HOP4Y(9)},
-          {PIP_X(id_W830) - 4., HOP4Y(9), PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7)},
-          {PIP_X(id_W834) - 4., HOP4Y(9), PIP_X(id_W834) - 4., WIRE_Y(0)},
-          {PIP_X(id_W830) - top_wire_dist - 4., HOP4Y(7), PIP_X(id_W830) - 5., HOP4Y(7)},
-          {PIP_X(id_W830) - 5., HOP4Y(7), PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5)},
-          {PIP_X(id_W830) - top_wire_dist - 5., HOP4Y(5), PIP_X(id_W830) - 6., HOP4Y(5)},
-          {PIP_X(id_W830) - 6., HOP4Y(5), PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3)},
-          {PIP_X(id_W830) - top_wire_dist - 6., HOP4Y(3), PIP_X(id_W830) - 7., HOP4Y(3)},
-          {PIP_X(id_W830) - 7., HOP4Y(3), PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1)},
-          {PIP_X(id_W830) - top_wire_dist - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(1)},
-          {-wrap_len - 7., HOP4Y(1), -wrap_len - 7., HOP4Y(0)},
-          {-wrap_len - 7., HOP4Y(0), PIP_X(id_E838) - 7., HOP4Y(0)},
-          {PIP_X(id_E838) - 7., HOP4Y(0), PIP_X(id_E838) - 7., WIRE_Y(0)}}},
-};
 
 void gfxCreateBelDecals(Arch *arch);
 void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel);

From 604260a0d7344627cea82198512384319c705105 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 3 Feb 2022 11:26:45 +1000
Subject: [PATCH 051/712] gowin: Add a DS location recognition

For differential signals it is necessary to set the position of two pins
at once: P and N.
This commit adds that capability and also adds another style of location
setting --- with the pin letter in square brackets used in vendor tools.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8c654b2eb9..1c401a43ce 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -505,10 +505,13 @@ static Loc getLoc(std::smatch match, int maxX, int maxY)
 
 void Arch::read_cst(std::istream &in)
 {
-    std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+) *;.*");
+    // If two locations are specified separated by commas (for differential I/O buffers),
+    // only the first location is actually recognized and used.
+    // And pin A will be Positive and pin B will be Negative in any case.
+    std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ,;]+)(, *[^ ;]+)? *;.*");
     std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*");
     std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
-    std::regex iobelre = std::regex("IO([TRBL])([0-9]+)([A-Z])");
+    std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
     std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
     std::smatch match, match_attr, match_pinloc;
     std::string line, pinline;
@@ -551,17 +554,20 @@ void Arch::read_cst(std::istream &in)
             if (belname != nullptr) {
                 std::string bel = IdString(belname->src_id).str(this);
                 it->second->setAttr(IdString(ID_BEL), bel);
-            } else if (std::regex_match(pinline, match_pinloc, iobelre)) {
-                // may be it's IOx#[AB] style?
-                Loc loc = getLoc(match_pinloc, getGridDimX(), getGridDimY());
-                BelId bel = getBelByLocation(loc);
-                if (bel == BelId()) {
-                    log_error("Pin %s not found\n", pinline.c_str());
-                }
-                std::string belname = getCtx()->nameOfBel(bel);
-                it->second->setAttr(IdString(ID_BEL), belname);
             } else {
-                log_error("Pin %s not found\n", pinname.c_str(this));
+                if (std::regex_match(pinline, match_pinloc, iobelre)) {
+                    // may be it's IOx#[AB] style?
+                    Loc loc = getLoc(match_pinloc, getGridDimX(), getGridDimY());
+                    BelId bel = getBelByLocation(loc);
+                    if (bel == BelId()) {
+                        log_error("Pin %s not found (TRBL style). \n", pinline.c_str());
+                    }
+                    std::string belname = getCtx()->nameOfBel(bel);
+                    it->second->setAttr(IdString(ID_BEL), belname);
+                } else {
+                    std::cout << "plain error:[" << pinline << "]" << std::endl;
+                    log_error("Pin %s not found (pin# style)\n", pinname.c_str(this));
+                }
             }
         } break;
         case insloc: { // INS_LOC

From d446a299871e7cf30631721f20818f7cce9ea3c0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 3 Feb 2022 14:59:25 +0000
Subject: [PATCH 052/712] nexus: Hotfix to disable unimplemented DCS routethru

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index 06a901cdf3..d553200fe0 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -185,7 +185,12 @@ Arch::Arch(ArchArgs args) : args(args)
             for (auto pip : getPipsUphill(w))
                 disabled_pips.insert(pip);
         }
-        NPNR_ASSERT(disabled_pips.size() == 4);
+        // TODO: find a better solution to disable these
+        WireId dcs_out = getWireByName(
+                IdStringList(std::array<IdString, 3>{x_ids.at(37), y_ids.at(10), id("JDCSOUT_DCS_DCSIP")}));
+        for (auto dcs_pip : getPipsUphill(dcs_out))
+            disabled_pips.insert(dcs_pip);
+        NPNR_ASSERT(disabled_pips.size() == 6);
     }
 }
 

From 84399caebe3c3eb0eba5275b7e2d5479404ba1a7 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 3 Feb 2022 15:28:46 +0000
Subject: [PATCH 053/712] run clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/hashlib.h     |  4 +---
 gowin/gfx.h          |  1 -
 mistral/arch.cc      | 15 ++++++++-------
 mistral/arch.h       |  5 +++--
 mistral/bitstream.cc | 16 +++++++++-------
 mistral/io.cc        |  2 +-
 nexus/main.cc        |  3 +--
 7 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/common/hashlib.h b/common/hashlib.h
index 70de8c919e..2f7357e25c 100644
--- a/common/hashlib.h
+++ b/common/hashlib.h
@@ -28,9 +28,7 @@ const int hashtable_size_factor = 3;
 
 // Cantor pairing function for two non-negative integers
 // https://en.wikipedia.org/wiki/Pairing_function
-inline unsigned int mkhash(unsigned int a, unsigned int b) {
-    return (a*a + 3*a + 2*a*b + b + b*b) / 2;
-}
+inline unsigned int mkhash(unsigned int a, unsigned int b) { return (a * a + 3 * a + 2 * a * b + b + b * b) / 2; }
 
 // traditionally 5381 is used as starting value for the djb2 hash
 const unsigned int mkhash_init = 5381;
diff --git a/gowin/gfx.h b/gowin/gfx.h
index b5ea4678ac..623b9fb20e 100644
--- a/gowin/gfx.h
+++ b/gowin/gfx.h
@@ -24,7 +24,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-
 void gfxCreateBelDecals(Arch *arch);
 void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel);
 void gfxSetIOBWireDecals(Arch *arch, BelInfo &bel);
diff --git a/mistral/arch.cc b/mistral/arch.cc
index f61d07abe0..c50e30f49b 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -43,18 +43,19 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 #undef X
 }
 
-CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, int pi) const
+CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi,
+                                   int pi) const
 {
     auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
     auto rn1 = cyclonev->pnode_to_rnode(pn1);
-    if(rn1)
+    if (rn1)
         return rn1;
 
-    if(bt == CycloneV::GPIO) {
+    if (bt == CycloneV::GPIO) {
         auto pn2 = cyclonev->p2p_to(pn1);
-        if(!pn2) {
+        if (!pn2) {
             auto pnv = cyclonev->p2p_from(pn1);
-            if(!pnv.empty())
+            if (!pnv.empty())
                 pn2 = pnv[0];
         }
         auto pn3 = cyclonev->hmc_get_bypass(pn2);
@@ -68,9 +69,9 @@ CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, Cycl
 WireId Arch::get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
 {
     auto rn = find_rnode(bt, x, y, port, bi, pi);
-    if(rn)
+    if (rn)
         return WireId(rn);
-    
+
     log_error("Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
 }
 
diff --git a/mistral/arch.h b/mistral/arch.h
index e931df2d08..e17be33125 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -461,7 +461,8 @@ struct Arch : BaseArch<ArchRanges>
 
     void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
 
-    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const;
+    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1,
+                                 int pi = -1) const;
     WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
     bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
 
@@ -561,7 +562,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
 
-    void build_bitstream();     // bitstream.cc
+    void build_bitstream(); // bitstream.cc
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 340f4b9642..e18d141346 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -39,14 +39,14 @@ struct MistralBitgen
     {
         auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
         auto rn1 = cv->pnode_to_rnode(pn1);
-        if(rn1)
+        if (rn1)
             return rn1;
 
-        if(bt == CycloneV::GPIO) {
+        if (bt == CycloneV::GPIO) {
             auto pn2 = cv->p2p_to(pn1);
-            if(!pn2) {
+            if (!pn2) {
                 auto pnv = cv->p2p_from(pn1);
-                if(!pnv.empty())
+                if (!pnv.empty())
                     pn2 = pnv[0];
             }
             auto pn3 = cv->hmc_get_bypass(pn2);
@@ -97,9 +97,11 @@ struct MistralBitgen
 
             // Output gpios must also bypass things in the associated dqs
             auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
-            if(dqs) {
-                cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
-                cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);
+            if (dqs) {
+                cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs),
+                               CycloneV::SEL_LOCKED_DPA);
+                cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY,
+                               CycloneV::pn2bi(dqs), 0x1f);
             }
         }
         // There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
diff --git a/mistral/io.cc b/mistral/io.cc
index a0a01af38a..c8d0238dcf 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -30,7 +30,7 @@ void Arch::create_gpio(int x, int y)
         WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
         BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
-        if(has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
+        if (has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
             // FIXME: is the port index of zero always correct?
             add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
             add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
diff --git a/nexus/main.cc b/nexus/main.cc
index b02dfa998c..88dddfe598 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -54,8 +54,7 @@ po::options_description NexusCommandHandler::getArchOptions()
     specific.add_options()("no-pack-lutff", "disable packing (clustering) LUTs and FFs together");
     specific.add_options()("carry-lutff-ratio", po::value<float>(),
                            "ratio of FFs to be added to carry-chain LUT clusters");
-    specific.add_options()("estimate-delay-mult", po::value<int>(),
-                           "multiplier for the estimate delay");
+    specific.add_options()("estimate-delay-mult", po::value<int>(), "multiplier for the estimate delay");
 
     return specific;
 }

From 1152c9f2f816c3d996b76dcf8c9333fb931ca8a8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 4 Feb 2022 09:18:08 +1000
Subject: [PATCH 054/712] gowin: Remove leftover debugging

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 886d811d8a..0793832601 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -732,7 +732,6 @@ void Arch::read_cst(std::istream &in)
                     std::string belname = getCtx()->nameOfBel(bel);
                     it->second->setAttr(IdString(ID_BEL), belname);
                 } else {
-                    std::cout << "plain error:[" << pinline << "]" << std::endl;
                     log_error("Pin %s not found (pin# style)\n", pinname.c_str(this));
                 }
             }

From 0675b98437df77f38a5d3f6278df7463d60cb3a3 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 4 Feb 2022 14:24:22 +1000
Subject: [PATCH 055/712] gowin: Speed up the GUI

By mistake, an empty decal gets filled with graphical elements.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/gfx.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index a851f53a69..daae5c71c3 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -5260,7 +5260,8 @@ void gfxSetWireDefaultDecal(Arch *arch, WireInfo &wire)
             snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
             active_id = arch->id(buf);
             active.decal = active_id;
-            inactive_id = IdString();
+            snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+            inactive_id = arch->id(buf);
             inactive.decal = inactive_id;
             active.x = inactive.x = 0;
             active.y = inactive.y = 0;
@@ -5301,9 +5302,8 @@ void gfxSetWireDefaultDecal(Arch *arch, WireInfo &wire)
                 snprintf(buf, sizeof(buf), "%s_active", wire.name.c_str(arch));
                 active_id = arch->id(buf);
                 active.decal = active_id;
-                // snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
-                // inactive_id = arch->id(buf);
-                inactive_id = IdString();
+                snprintf(buf, sizeof(buf), "%s_inactive", wire.name.c_str(arch));
+                inactive_id = arch->id(buf);
                 inactive.decal = inactive_id;
                 active.x = inactive.x = 0;
                 active.y = inactive.y = 0;

From 5ef5c33e9e964a176040c829adc965ec46331d77 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 4 Feb 2022 15:54:41 +0000
Subject: [PATCH 056/712] generic: Add missing Pip vector binding

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch_pybindings.cc |  1 +
 generic/arch_pybindings.h  | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 92c782529b..6d3d981c53 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -266,6 +266,7 @@ void arch_wrap_python(py::module &m)
     WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
     WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
     WRAP_VECTOR(m, const std::vector<IdString>, conv_to_str<IdString>);
+    WRAP_VECTOR(m, const std::vector<PipId>, conv_to_str<PipId>);
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/generic/arch_pybindings.h b/generic/arch_pybindings.h
index 72d688dc61..f0daccbc4e 100644
--- a/generic/arch_pybindings.h
+++ b/generic/arch_pybindings.h
@@ -76,6 +76,18 @@ template <> struct string_converter<PipId>
     }
 };
 
+template <> struct string_converter<const PipId &>
+{
+    PipId from_str(Context *ctx, std::string name) { return ctx->getPipByNameStr(name); }
+
+    std::string to_str(Context *ctx, const PipId &id)
+    {
+        if (id == PipId())
+            throw bad_wrap();
+        return ctx->getPipName(id).str(ctx);
+    }
+};
+
 template <> struct string_converter<BelPin>
 {
     BelPin from_str(Context *ctx, std::string name)

From e5bfff6e9fbbbc743c504365ab41e4112aefb6d6 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 4 Feb 2022 20:49:32 +0000
Subject: [PATCH 057/712] viaduct: Allow constraining only cascades without
 fanout

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct_helpers.cc | 4 +++-
 generic/viaduct_helpers.h  | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index 36bdd6bec1..e9f7fa60e6 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -82,7 +82,7 @@ void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
 }
 
 int ViaductHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports,
-                                         int delta_z)
+                                         int delta_z, bool allow_fanout)
 {
     int constrained = 0;
     for (auto &cell : ctx->cells) {
@@ -96,6 +96,8 @@ int ViaductHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, co
                 continue;
             if (!src_ports.count(CellTypePort(ci.type, port.first)))
                 continue;
+            if (!allow_fanout && port.second.net->users.size() > 1)
+                continue;
             for (auto &usr : port.second.net->users) {
                 if (!sink_ports.count(CellTypePort(usr)))
                     continue;
diff --git a/generic/viaduct_helpers.h b/generic/viaduct_helpers.h
index 8cba84115e..cac2230421 100644
--- a/generic/viaduct_helpers.h
+++ b/generic/viaduct_helpers.h
@@ -70,7 +70,8 @@ struct ViaductHelpers
     // expects a set of top-level port types
     void remove_nextpnr_iobs(const pool<CellTypePort> &top_ports);
     // Constrain cells with certain port connection patterns together with a fixed z-offset
-    int constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports, int delta_z);
+    int constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports, int delta_z,
+                             bool allow_fanout = true);
     // Replace constants with given driving cells
     void replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
                            const dict<IdString, Property> &vcc_params = {},

From 230de1e68afb0f7c57f64bd1b35850e529395d92 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Mon, 24 Jan 2022 23:54:09 +0800
Subject: [PATCH 058/712] gowin: add an option to manually specify family

In the vendor IDE, there's a device family named GW1N-9C (which seems to
mean C revision of GW1N-9), in which the model numbers are all the same
with GW1N-9.

Add an option to nextpnr-gowin to allow manually specified family for
this situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 gowin/main.cc | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index fb9df48d20..343d922b5c 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -48,6 +48,7 @@ po::options_description GowinCommandHandler::getArchOptions()
 {
     po::options_description specific("Architecture specific options");
     specific.add_options()("device", po::value<std::string>(), "device name");
+    specific.add_options()("family", po::value<std::string>(), "family name");
     specific.add_options()("cst", po::value<std::string>(), "physical constraints file");
     return specific;
 }
@@ -62,12 +63,16 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     }
     ArchArgs chipArgs;
     chipArgs.gui = vm.count("gui") != 0;
-    char buf[36];
-    // GW1N and GW1NR variants share the same database.
-    // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
-    // However, it appears that the S series with embedded ARM core are unique silicon.
-    snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
-    chipArgs.family = buf;
+    if (vm.count("family")) {
+	    chipArgs.family = vm["family"].as<std::string>();
+    } else {
+	    char buf[36];
+	    // GW1N and GW1NR variants share the same database.
+	    // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
+	    // However, it appears that the S series with embedded ARM core are unique silicon.
+	    snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
+	    chipArgs.family = buf;
+    }
     chipArgs.partnumber = match[0];
     return std::unique_ptr<Context>(new Context(chipArgs));
 }

From cd97ef6536eccc73554b5f418945c4e001db9606 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sun, 6 Feb 2022 11:56:09 +0100
Subject: [PATCH 059/712] add GW1N-9C db

---
 .cirrus/Dockerfile.ubuntu20.04 | 2 +-
 gowin/CMakeLists.txt           | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index 934bbbcbe0..a4233f3d51 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -65,4 +65,4 @@ RUN set -e -x ;\
     PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
 
 RUN set -e -x ;\
-    pip3 install apycula==0.2a2
+    pip3 install apycula==0.2a3
diff --git a/gowin/CMakeLists.txt b/gowin/CMakeLists.txt
index 5ec321288c..34af9dc6d5 100644
--- a/gowin/CMakeLists.txt
+++ b/gowin/CMakeLists.txt
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-gowin NONE)
 
-set(ALL_GOWIN_DEVICES GW1N-1 GW1N-4 GW1N-9 GW1NS-2 GW1NS-4)
+set(ALL_GOWIN_DEVICES GW1N-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-2 GW1NS-4)
 set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
 message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")

From 5c300933609b5213322e271a4e745e2d4a101b31 Mon Sep 17 00:00:00 2001
From: Dan Callaghan <dcallagh@google.com>
Date: Thu, 10 Feb 2022 15:48:06 +1100
Subject: [PATCH 060/712] nexus: reduce OSCA worst case to 7%
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):

https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780

Older documents listed a wider frequency range but ±7% is the range for
production parts.
---
 nexus/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 5e9da3042f..81a729b187 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1987,7 +1987,7 @@ struct NexusPacker
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
                 } else if (ci->type == id_OSC_CORE) {
                     int div = int_or_default(ci->params, ctx->id("HF_CLK_DIV"), 128);
-                    const float tol = 1.15f; // OSCA has +/-15% frequency tolerance, assume the worst case.
+                    const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
                     set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
                     set_period(ci, id_LFCLKOUT, delay_t((1.0e3 / 10) / tol));
                 } else if (ci->type == id_PLL_CORE) {

From e90f5b72f7047e3813ce0817eeba82393919b13e Mon Sep 17 00:00:00 2001
From: Verneri Hirvonen <verneri.hirvonen.2@gmail.com>
Date: Tue, 15 Feb 2022 14:12:16 +0200
Subject: [PATCH 061/712] gowin: Add GW1NZ-1

---
 gowin/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/CMakeLists.txt b/gowin/CMakeLists.txt
index 34af9dc6d5..ab6f4ee42e 100644
--- a/gowin/CMakeLists.txt
+++ b/gowin/CMakeLists.txt
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-gowin NONE)
 
-set(ALL_GOWIN_DEVICES GW1N-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-2 GW1NS-4)
+set(ALL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-2 GW1NS-4)
 set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
 message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")

From 05c41ae2246f7a5da5247906f73d88d8526ebe6d Mon Sep 17 00:00:00 2001
From: Ezra Thomas <46074998+ept221@users.noreply.github.com>
Date: Tue, 15 Feb 2022 22:29:39 -0500
Subject: [PATCH 062/712] Fixed formatting typo in archapi.md

---
 docs/archapi.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/archapi.md b/docs/archapi.md
index f798254fad..3fc30cdb5b 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -569,7 +569,7 @@ run the router.
 Graphics Methods
 ----------------
 
-###DecalGfxRangeT getDecalGraphics(DecalId decal) const
+### DecalGfxRangeT getDecalGraphics(DecalId decal) const
 
 Return the graphic elements that make up a decal.
 

From bdea5a1f6f5633ddc84fcbe1f13325b655bae1e9 Mon Sep 17 00:00:00 2001
From: Verneri Hirvonen <verneri.hirvonen.2@gmail.com>
Date: Wed, 16 Feb 2022 10:25:18 +0200
Subject: [PATCH 063/712] gowin: bump apycula version

---
 .cirrus/Dockerfile.ubuntu20.04 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index a4233f3d51..d1e7b47bf9 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -65,4 +65,4 @@ RUN set -e -x ;\
     PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
 
 RUN set -e -x ;\
-    pip3 install apycula==0.2a3
+    pip3 install apycula==0.2a4

From f3ee0d51a9546afe77a31d2a1e98a0bbee4659fa Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Feb 2022 13:32:53 +0000
Subject: [PATCH 064/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 gowin/main.cc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index 343d922b5c..38a67fcd18 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -64,14 +64,14 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     ArchArgs chipArgs;
     chipArgs.gui = vm.count("gui") != 0;
     if (vm.count("family")) {
-	    chipArgs.family = vm["family"].as<std::string>();
+        chipArgs.family = vm["family"].as<std::string>();
     } else {
-	    char buf[36];
-	    // GW1N and GW1NR variants share the same database.
-	    // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
-	    // However, it appears that the S series with embedded ARM core are unique silicon.
-	    snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
-	    chipArgs.family = buf;
+        char buf[36];
+        // GW1N and GW1NR variants share the same database.
+        // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
+        // However, it appears that the S series with embedded ARM core are unique silicon.
+        snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
+        chipArgs.family = buf;
     }
     chipArgs.partnumber = match[0];
     return std::unique_ptr<Context>(new Context(chipArgs));

From 02e6d2dbca0433e6f873c6af635cee701e84f5f5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Feb 2022 13:39:57 +0000
Subject: [PATCH 065/712] mistral: Fix 'not handled in switch' compiler warning

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/delay.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/mistral/delay.cc b/mistral/delay.cc
index 98ef1be62a..4d123249e8 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -235,8 +235,9 @@ DelayQuad Arch::getPipDelay(PipId pip) const
         return DelayQuad{123};
     case CycloneV::rnode_type_t::TCLK:
         return DelayQuad{46};
+    default:
+        return DelayQuad{308};
     }
-    return DelayQuad{308};
 }
 
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const

From 30fd86ce69fa65e89dec119e23b5bccb54de70a3 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Feb 2022 13:53:47 +0000
Subject: [PATCH 066/712] refactor: New NetInfo and CellInfo constructors

---
 common/basectx.cc                    |  7 +---
 common/design_utils.cc               |  8 +---
 common/nextpnr_types.h               |  6 +++
 ecp5/cells.cc                        | 18 ++++-----
 ecp5/globals.cc                      | 23 +++++------
 ecp5/pack.cc                         | 58 +++++++++-------------------
 fpga_interchange/pseudo_pip_model.cc |  6 +--
 fpga_interchange/site_arch.cc        |  4 +-
 generic/cells.cc                     | 10 ++---
 generic/pack.cc                      |  6 +--
 gowin/cells.cc                       | 10 ++---
 gowin/pack.cc                        |  6 +--
 ice40/bitstream.cc                   |  4 +-
 ice40/cells.cc                       | 20 ++++------
 ice40/chains.cc                      | 32 +++++----------
 ice40/pack.cc                        | 22 ++++-------
 machxo2/cells.cc                     | 10 ++---
 machxo2/pack.cc                      | 15 +++----
 18 files changed, 95 insertions(+), 170 deletions(-)

diff --git a/common/basectx.cc b/common/basectx.cc
index b9036ed6ec..b55cd072ab 100644
--- a/common/basectx.cc
+++ b/common/basectx.cc
@@ -211,8 +211,7 @@ NetInfo *BaseCtx::createNet(IdString name)
 {
     NPNR_ASSERT(!nets.count(name));
     NPNR_ASSERT(!net_aliases.count(name));
-    std::unique_ptr<NetInfo> net{new NetInfo};
-    net->name = name;
+    auto net = std::make_unique<NetInfo>(name);
     net_aliases[name] = name;
     NetInfo *ptr = net.get();
     nets[name] = std::move(net);
@@ -252,9 +251,7 @@ void BaseCtx::lockNetRouting(IdString name)
 CellInfo *BaseCtx::createCell(IdString name, IdString type)
 {
     NPNR_ASSERT(!cells.count(name));
-    std::unique_ptr<CellInfo> cell{new CellInfo};
-    cell->name = name;
-    cell->type = type;
+    auto cell = std::make_unique<CellInfo>(getCtx(), name, type);
     CellInfo *ptr = cell.get();
     cells[name] = std::move(cell);
     refreshUi();
diff --git a/common/design_utils.cc b/common/design_utils.cc
index da5decf9c4..9432b6cd71 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -129,12 +129,8 @@ void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo
     PortInfo &port1 = cell1->ports.at(port1_name);
     if (port1.net == nullptr) {
         // No net on port1; need to create one
-        std::unique_ptr<NetInfo> p1net(new NetInfo());
-        p1net->name = ctx->id(cell1->name.str(ctx) + "$conn$" + port1_name.str(ctx));
-        connect_port(ctx, p1net.get(), cell1, port1_name);
-        IdString p1name = p1net->name;
-        NPNR_ASSERT(!ctx->cells.count(p1name));
-        ctx->nets[p1name] = std::move(p1net);
+        NetInfo *p1net = ctx->createNet(ctx->id(cell1->name.str(ctx) + "$conn$" + port1_name.str(ctx)));
+        connect_port(ctx, p1net, cell1, port1_name);
     }
     connect_port(ctx, port1.net, cell2, port2_name);
 }
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index 6b594d643d..6debd2b8df 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -124,6 +124,7 @@ struct ClockConstraint;
 
 struct NetInfo : ArchNetInfo
 {
+    explicit NetInfo(IdString name) : name(name){};
     IdString name, hierpath;
     int32_t udata = 0;
 
@@ -155,8 +156,13 @@ struct PortInfo
     PortType type;
 };
 
+struct Context;
+
 struct CellInfo : ArchCellInfo
 {
+    CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type){};
+    Context *ctx = nullptr;
+
     IdString name, type, hierpath;
     int32_t udata;
 
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index b0ae2065f8..e5ab4d4b7d 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -34,13 +34,9 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
 std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
-    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
-    if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
-    } else {
-        new_cell->name = ctx->id(name);
-    }
-    new_cell->type = type;
+    IdString name_id =
+            name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+    std::unique_ptr<CellInfo> new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
 
     auto copy_bel_ports = [&]() {
         // First find a Bel of the target type
@@ -465,11 +461,11 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
     if (ctx->ports.count(nxio->name)) {
         IdString tn_netname = nxio->name;
         NPNR_ASSERT(!ctx->nets.count(tn_netname));
-        std::unique_ptr<NetInfo> toplevel_net{new NetInfo};
+        ctx->net_aliases.erase(tn_netname);
+        NetInfo *toplevel_net = ctx->createNet(tn_netname);
         toplevel_net->name = tn_netname;
-        connect_port(ctx, toplevel_net.get(), trio, ctx->id("B"));
-        ctx->ports[nxio->name].net = toplevel_net.get();
-        ctx->nets[tn_netname] = std::move(toplevel_net);
+        connect_port(ctx, toplevel_net, trio, ctx->id("B"));
+        ctx->ports[nxio->name].net = toplevel_net;
     }
 
     CellInfo *tbuf = net_driven_by(
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 8ee49c0293..cc2208e00a 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -456,11 +456,10 @@ class Ecp5GlobalRouter
             dccptr = net->driver.cell;
         } else {
             auto dcc = create_ecp5_cell(ctx, id_DCCA, "$gbuf$" + net->name.str(ctx));
-            std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo);
-            glbnet->name = ctx->id("$glbnet$" + net->name.str(ctx));
-            glbnet->driver.cell = dcc.get();
-            glbnet->driver.port = id_CLKO;
-            dcc->ports[id_CLKO].net = glbnet.get();
+            glbptr = ctx->createNet(ctx->id("$glbnet$" + net->name.str(ctx)));
+            glbptr->driver.cell = dcc.get();
+            glbptr->driver.port = id_CLKO;
+            dcc->ports[id_CLKO].net = glbptr;
             std::vector<PortRef> keep_users;
             for (auto user : net->users) {
                 if (dcs_cell != nullptr && user.cell != dcs_cell) {
@@ -473,8 +472,8 @@ class Ecp5GlobalRouter
                 } else if (is_logic_port(user)) {
                     keep_users.push_back(user);
                 } else {
-                    glbnet->users.push_back(user);
-                    user.cell->ports.at(user.port).net = glbnet.get();
+                    glbptr->users.push_back(user);
+                    user.cell->ports.at(user.port).net = glbptr;
                 }
             }
             net->users = keep_users;
@@ -485,13 +484,11 @@ class Ecp5GlobalRouter
             clki_pr.cell = dcc.get();
             net->users.push_back(clki_pr);
             if (net->clkconstr) {
-                glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-                glbnet->clkconstr->low = net->clkconstr->low;
-                glbnet->clkconstr->high = net->clkconstr->high;
-                glbnet->clkconstr->period = net->clkconstr->period;
+                glbptr->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+                glbptr->clkconstr->low = net->clkconstr->low;
+                glbptr->clkconstr->high = net->clkconstr->high;
+                glbptr->clkconstr->period = net->clkconstr->period;
             }
-            glbptr = glbnet.get();
-            ctx->nets[glbnet->name] = std::move(glbnet);
             dccptr = dcc.get();
             ctx->cells[dcc->name] = std::move(dcc);
         }
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 85d92336c2..79644d1331 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -761,17 +761,14 @@ class Ecp5Packer
                            carry->users.end());
         connect_port(ctx, carry, feedin.get(), id_A0);
 
-        std::unique_ptr<NetInfo> new_carry(new NetInfo());
-        new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
-        connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
+        NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
+        connect_port(ctx, new_carry, feedin.get(), ctx->id("COUT"));
         chain_in.cell->ports[chain_in.port].net = nullptr;
-        connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
+        connect_port(ctx, new_carry, chain_in.cell, chain_in.port);
 
         CellInfo *feedin_ptr = feedin.get();
         IdString feedin_name = feedin->name;
         ctx->cells[feedin_name] = std::move(feedin);
-        IdString new_carry_name = new_carry->name;
-        ctx->nets[new_carry_name] = std::move(new_carry);
         return feedin_ptr;
     }
 
@@ -789,11 +786,10 @@ class Ecp5Packer
         carry->driver.cell = nullptr;
         connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
 
-        std::unique_ptr<NetInfo> new_cin(new NetInfo());
-        new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
+        NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
         new_cin->driver = carry_drv;
-        carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
-        connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
+        carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
+        connect_port(ctx, new_cin, feedout.get(), ctx->id("CIN"));
 
         if (chain_next) {
             // Loop back into LUT4_1 for feedthrough
@@ -805,24 +801,17 @@ class Ecp5Packer
                                               }),
                                carry->users.end());
 
-            std::unique_ptr<NetInfo> new_cout(new NetInfo());
-            new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
-            connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
+            NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
+            connect_port(ctx, new_cout, feedout.get(), ctx->id("COUT"));
 
             chain_next->cell->ports[chain_next->port].net = nullptr;
-            connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
-
-            IdString new_cout_name = new_cout->name;
-            ctx->nets[new_cout_name] = std::move(new_cout);
+            connect_port(ctx, new_cout, chain_next->cell, chain_next->port);
         }
 
         CellInfo *feedout_ptr = feedout.get();
         IdString feedout_name = feedout->name;
         ctx->cells[feedout_name] = std::move(feedout);
 
-        IdString new_cin_name = new_cin->name;
-        ctx->nets[new_cin_name] = std::move(new_cin);
-
         return feedout_ptr;
     }
 
@@ -1384,16 +1373,14 @@ class Ecp5Packer
 
         std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
         gnd_cell->params[ctx->id("INIT")] = Property(0, 16);
-        std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
-        gnd_net->name = ctx->id("$PACKER_GND_NET");
+        auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
         gnd_net->driver.cell = gnd_cell.get();
         gnd_net->driver.port = ctx->id("Z");
         gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
 
         std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
         vcc_cell->params[ctx->id("INIT")] = Property(65535, 16);
-        std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
-        vcc_net->name = ctx->id("$PACKER_VCC_NET");
+        auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
         vcc_net->driver.cell = vcc_cell.get();
         vcc_net->driver.port = ctx->id("Z");
         vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
@@ -1967,12 +1954,9 @@ class Ecp5Packer
                 IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
                                            std::to_string(free_eclk));
 
-                std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
-                promoted_ecknet->name = eckname;
+                NetInfo *promoted_ecknet = ctx->createNet(eckname);
                 promoted_ecknet->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1; // Prevents router etc touching this special net
-                eclk.buf = promoted_ecknet.get();
-                NPNR_ASSERT(!ctx->nets.count(eckname));
-                ctx->nets[eckname] = std::move(promoted_ecknet);
+                eclk.buf = promoted_ecknet;
 
                 // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
                 std::unique_ptr<CellInfo> eclkbuf =
@@ -2052,17 +2036,13 @@ class Ecp5Packer
             ci->ports[port].name = port;
             ci->ports[port].type = PORT_IN;
         }
-
-        std::unique_ptr<CellInfo> zero_cell{new CellInfo};
-        std::unique_ptr<NetInfo> zero_net{new NetInfo};
         IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
-        zero_cell->type = ctx->id("GND");
-        zero_cell->name = name;
-        zero_net->name = name;
-        zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
-        connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
-        connect_port(ctx, zero_net.get(), ci, port);
-        ctx->nets[name] = std::move(zero_net);
+
+        auto zero_cell = std::make_unique<CellInfo>(ctx, name, ctx->id("GND"));
+        NetInfo *zero_net = ctx->createNet(name);
+        zero_cell->addOutput(ctx->id("GND"));
+        connect_port(ctx, zero_net, zero_cell.get(), ctx->id("GND"));
+        connect_port(ctx, zero_net, ci, port);
         new_cells.push_back(std::move(zero_cell));
     }
 
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc
index 39718c651b..7f2427c4f4 100644
--- a/fpga_interchange/pseudo_pip_model.cc
+++ b/fpga_interchange/pseudo_pip_model.cc
@@ -355,12 +355,11 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
 
         NPNR_ASSERT(bel_data.lut_element != -1);
 
-        lut_thru_cells.emplace_back();
+        lut_thru_cells.emplace_back(nullptr, IdString(), IdString(ctx->wire_lut->cell));
         CellInfo &cell = lut_thru_cells.back();
 
         cell.bel = bel;
 
-        cell.type = IdString(ctx->wire_lut->cell);
         NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
         cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));
 
@@ -384,7 +383,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
             continue;
         }
 
-        lut_cells.emplace_back();
+        lut_cells.emplace_back(nullptr, IdString(), ctx->wire_lut ? IdString(ctx->wire_lut->cell) : IdString());
         CellInfo &cell = lut_cells.back();
 
         cell.bel.tile = tile;
@@ -393,7 +392,6 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site)
         if (ctx->wire_lut == nullptr)
             continue;
 
-        cell.type = IdString(ctx->wire_lut->cell);
         NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
         cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));
 
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
index ac64446521..f78e8af44f 100644
--- a/fpga_interchange/site_arch.cc
+++ b/fpga_interchange/site_arch.cc
@@ -103,7 +103,8 @@ void SiteArch::archcheck()
     }
 }
 
-SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site_info(site_info)
+SiteArch::SiteArch(const SiteInformation *site_info)
+        : ctx(site_info->ctx), site_info(site_info), blocking_net(site_info->ctx->id("$nextpnr_blocked_net"))
 {
     // Build list of input and output site ports
     //
@@ -275,7 +276,6 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
         }
     }
 
-    blocking_net.name = ctx->id("$nextpnr_blocked_net");
     blocking_site_net.net = &blocking_net;
 }
 
diff --git a/generic/cells.cc b/generic/cells.cc
index 44b99050f2..967afb23ca 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -34,13 +34,9 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
 std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
-    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
-    if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
-    } else {
-        new_cell->name = ctx->id(name);
-    }
-    new_cell->type = type;
+    IdString name_id =
+            name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+    auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
     if (type == ctx->id("GENERIC_SLICE")) {
         new_cell->params[ctx->id("K")] = ctx->args.K;
         new_cell->params[ctx->id("INIT")] = 0;
diff --git a/generic/pack.cc b/generic/pack.cc
index 291a528dae..8bdbbed07c 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -140,8 +140,7 @@ static void pack_constants(Context *ctx)
 
     std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND");
     gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << ctx->args.K);
-    std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
-    gnd_net->name = ctx->id("$PACKER_GND_NET");
+    std::unique_ptr<NetInfo> gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
     gnd_net->driver.port = ctx->id("F");
     gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
@@ -149,8 +148,7 @@ static void pack_constants(Context *ctx)
     std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC");
     // Fill with 1s
     vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << ctx->args.K), Property::S1);
-    std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
-    vcc_net->name = ctx->id("$PACKER_VCC_NET");
+    std::unique_ptr<NetInfo> vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
     vcc_net->driver.port = ctx->id("F");
     vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
diff --git a/gowin/cells.cc b/gowin/cells.cc
index dce3f45654..67a81f39f9 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -35,13 +35,9 @@ void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
 std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
-    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
-    if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
-    } else {
-        new_cell->name = ctx->id(name);
-    }
-    new_cell->type = type;
+    IdString name_id =
+            name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+    auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
     if (type == id_SLICE) {
         new_cell->params[id_INIT] = 0;
         new_cell->params[id_FF_USED] = 0;
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 553eeb4e53..3d33f2d8a4 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -612,8 +612,7 @@ static void pack_constants(Context *ctx)
 
     std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_GND");
     gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << 4);
-    std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
-    gnd_net->name = ctx->id("$PACKER_GND_NET");
+    auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
     gnd_net->driver.port = ctx->id("F");
     gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
@@ -621,8 +620,7 @@ static void pack_constants(Context *ctx)
     std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_VCC");
     // Fill with 1s
     vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
-    std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
-    vcc_net->name = ctx->id("$PACKER_VCC_NET");
+    auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
     vcc_net->driver.port = ctx->id("F");
     vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 3c7e74151c..8caa9dc698 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -979,9 +979,7 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config)
                 IdString netName = ctx->id(name);
 
                 if (ctx->nets.find(netName) == ctx->nets.end()) {
-                    std::unique_ptr<NetInfo> created_net = std::unique_ptr<NetInfo>(new NetInfo);
-                    created_net->name = netName;
-                    ctx->nets[netName] = std::move(created_net);
+                    ctx->createNet(netName);
                 }
 
                 WireId wire;
diff --git a/ice40/cells.cc b/ice40/cells.cc
index a7e5b0670c..9a75118f53 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -36,13 +36,10 @@ void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir
 std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
-    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
-    if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
-    } else {
-        new_cell->name = ctx->id(name);
-    }
-    new_cell->type = type;
+    IdString name_id =
+            name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+    auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
+
     if (type == ctx->id("ICESTORM_LC")) {
         new_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
         new_cell->params[ctx->id("NEG_CLK")] = Property::State::S0;
@@ -459,11 +456,10 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
     if (ctx->ports.count(nxio->name)) {
         IdString tn_netname = nxio->name;
         NPNR_ASSERT(!ctx->nets.count(tn_netname));
-        std::unique_ptr<NetInfo> toplevel_net{new NetInfo};
-        toplevel_net->name = tn_netname;
-        connect_port(ctx, toplevel_net.get(), sbio, ctx->id("PACKAGE_PIN"));
-        ctx->ports[nxio->name].net = toplevel_net.get();
-        ctx->nets[tn_netname] = std::move(toplevel_net);
+        ctx->net_aliases.erase(tn_netname);
+        NetInfo *toplevel_net = ctx->createNet(tn_netname);
+        connect_port(ctx, toplevel_net, sbio, ctx->id("PACKAGE_PIN"));
+        ctx->ports[nxio->name].net = toplevel_net;
     }
 
     CellInfo *tbuf = net_driven_by(
diff --git a/ice40/chains.cc b/ice40/chains.cc
index d0d8b043fc..fa4ce413cf 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -114,8 +114,7 @@ class ChainConstrainer
         lc->params[ctx->id("LUT_INIT")] = Property(65280, 16); // 0xff00: O = I3
         lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
         lc->ports.at(id_O).net = cout_port.net;
-        std::unique_ptr<NetInfo> co_i3_net(new NetInfo());
-        co_i3_net->name = ctx->id(lc->name.str(ctx) + "$I3");
+        NetInfo *co_i3_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$I3"));
         co_i3_net->driver = cout_port.net->driver;
         PortRef i3_r;
         i3_r.port = id_I3;
@@ -125,17 +124,12 @@ class ChainConstrainer
         o_r.port = id_O;
         o_r.cell = lc.get();
         cout_port.net->driver = o_r;
-        lc->ports.at(id_I3).net = co_i3_net.get();
-        cout_port.net = co_i3_net.get();
-
-        IdString co_i3_name = co_i3_net->name;
-        NPNR_ASSERT(ctx->nets.find(co_i3_name) == ctx->nets.end());
-        ctx->nets[co_i3_name] = std::move(co_i3_net);
+        lc->ports.at(id_I3).net = co_i3_net;
+        cout_port.net = co_i3_net;
 
         // If COUT also connects to a CIN; preserve the carry chain
         if (cin_cell) {
-            std::unique_ptr<NetInfo> co_cin_net(new NetInfo());
-            co_cin_net->name = ctx->id(lc->name.str(ctx) + "$COUT");
+            NetInfo *co_cin_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$COUT"));
 
             // Connect I1 to 1 to preserve carry chain
             NetInfo *vcc = ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get();
@@ -150,7 +144,7 @@ class ChainConstrainer
             co_r.port = id_COUT;
             co_r.cell = lc.get();
             co_cin_net->driver = co_r;
-            lc->ports.at(id_COUT).net = co_cin_net.get();
+            lc->ports.at(id_COUT).net = co_cin_net;
 
             // Find the user corresponding to the next CIN
             int replaced_ports = 0;
@@ -166,14 +160,11 @@ class ChainConstrainer
                 if (fnd_user != usr.end()) {
                     co_cin_net->users.push_back(*fnd_user);
                     usr.erase(fnd_user);
-                    cin_cell->ports.at(port).net = co_cin_net.get();
+                    cin_cell->ports.at(port).net = co_cin_net;
                     ++replaced_ports;
                 }
             }
             NPNR_ASSERT(replaced_ports > 0);
-            IdString co_cin_name = co_cin_net->name;
-            NPNR_ASSERT(ctx->nets.find(co_cin_name) == ctx->nets.end());
-            ctx->nets[co_cin_name] = std::move(co_cin_net);
         }
 
         IdString name = lc->name;
@@ -201,24 +192,19 @@ class ChainConstrainer
         i1_ref.port = ctx->id("I1");
         lc->ports.at(ctx->id("I1")).net->users.push_back(i1_ref);
 
-        std::unique_ptr<NetInfo> out_net(new NetInfo());
-        out_net->name = ctx->id(lc->name.str(ctx) + "$O");
+        NetInfo *out_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$O"));
 
         PortRef drv_ref;
         drv_ref.port = ctx->id("COUT");
         drv_ref.cell = lc.get();
         out_net->driver = drv_ref;
-        lc->ports.at(ctx->id("COUT")).net = out_net.get();
+        lc->ports.at(ctx->id("COUT")).net = out_net;
 
         PortRef usr_ref;
         usr_ref.port = cin_port.name;
         usr_ref.cell = cin_cell;
         out_net->users.push_back(usr_ref);
-        cin_cell->ports.at(cin_port.name).net = out_net.get();
-
-        IdString out_net_name = out_net->name;
-        NPNR_ASSERT(ctx->nets.find(out_net_name) == ctx->nets.end());
-        ctx->nets[out_net_name] = std::move(out_net);
+        cin_cell->ports.at(cin_port.name).net = out_net;
 
         IdString name = lc->name;
         ctx->assignCellInfo(lc.get());
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 921e73e08e..fcbdf2bdad 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -354,8 +354,7 @@ static void pack_constants(Context *ctx)
 
     std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
     gnd_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
-    std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
-    gnd_net->name = ctx->id("$PACKER_GND_NET");
+    auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
     gnd_net->driver.port = ctx->id("O");
     gnd_cell->ports.at(ctx->id("O")).net = gnd_net.get();
@@ -367,8 +366,7 @@ static void pack_constants(Context *ctx)
 
     std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
     vcc_cell->params[ctx->id("LUT_INIT")] = Property(1, 16);
-    std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
-    vcc_net->name = ctx->id("$PACKER_VCC_NET");
+    auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
     vcc_net->driver.port = ctx->id("O");
     vcc_cell->ports.at(ctx->id("O")).net = vcc_net.get();
@@ -606,15 +604,14 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
 
     pr.cell = gb.get();
     pr.port = ctx->id("GLOBAL_BUFFER_OUTPUT");
-    std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo());
-    glbnet->name = ctx->id(glb_name);
+    NetInfo *glbnet = ctx->createNet(ctx->id(glb_name));
     glbnet->driver = pr;
-    gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet.get();
+    gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet;
     std::vector<PortRef> keep_users;
     for (auto user : net->users) {
         if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) ||
             (is_cen && is_enable_port(ctx, user)) || (is_logic && is_logic_port(ctx, user))) {
-            user.cell->ports[user.port].net = glbnet.get();
+            user.cell->ports[user.port].net = glbnet;
             glbnet->users.push_back(user);
         } else {
             keep_users.push_back(user);
@@ -629,7 +626,6 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
         glbnet->clkconstr->period = net->clkconstr->period;
     }
 
-    ctx->nets[glbnet->name] = std::move(glbnet);
     ctx->cells[gb->name] = std::move(gb);
 }
 
@@ -1026,11 +1022,10 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     pt->params[ctx->id("LUT_INIT")] = Property(65280, 16); // output is always I3
 
     // Create LUT output net.
-    std::unique_ptr<NetInfo> out_net = std::unique_ptr<NetInfo>(new NetInfo);
-    out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net");
+    NetInfo *out_net = ctx->createNet(ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net"));
     out_net->driver.cell = pt.get();
     out_net->driver.port = ctx->id("O");
-    pt->ports.at(ctx->id("O")).net = out_net.get();
+    pt->ports.at(ctx->id("O")).net = out_net;
 
     // New users of the original cell's port
     std::vector<PortRef> new_users;
@@ -1040,7 +1035,7 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
             continue;
         }
         // Rewrite pointer into net in user.
-        user.cell->ports[user.port].net = out_net.get();
+        user.cell->ports[user.port].net = out_net;
         // Add user to net.
         PortRef pr;
         pr.cell = user.cell;
@@ -1058,7 +1053,6 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     // Replace users of the original net.
     port.net->users = new_users;
 
-    ctx->nets[out_net->name] = std::move(out_net);
     return pt;
 }
 
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index 7334234d62..534d8e3cc9 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -41,13 +41,9 @@ void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
 std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
-    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
-    if (name.empty()) {
-        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
-    } else {
-        new_cell->name = ctx->id(name);
-    }
-    new_cell->type = type;
+    IdString name_id =
+            name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+    auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
 
     if (type == id_FACADE_SLICE) {
         new_cell->params[id_MODE] = std::string("LOGIC");
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index c53229ba01..0c2c945922 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -183,17 +183,16 @@ static void pack_constants(Context *ctx)
     const_cell->params[id_LUT0_INITVAL] = Property(0, 16);
     const_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
 
-    std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
-    gnd_net->name = ctx->id("$PACKER_GND_NET");
+    NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = const_cell.get();
     gnd_net->driver.port = id_F0;
-    const_cell->ports.at(id_F0).net = gnd_net.get();
+    const_cell->ports.at(id_F0).net = gnd_net;
 
-    std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
+    NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
     vcc_net->name = ctx->id("$PACKER_VCC_NET");
     vcc_net->driver.cell = const_cell.get();
     vcc_net->driver.port = id_F1;
-    const_cell->ports.at(id_F1).net = vcc_net.get();
+    const_cell->ports.at(id_F1).net = vcc_net;
 
     std::vector<IdString> dead_nets;
 
@@ -201,20 +200,18 @@ static void pack_constants(Context *ctx)
         NetInfo *ni = net.second.get();
         if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
             IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, gnd_net.get(), false);
+            set_net_constant(ctx, ni, gnd_net, false);
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
         } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
             IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, vcc_net.get(), true);
+            set_net_constant(ctx, ni, vcc_net, true);
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
         }
     }
 
     ctx->cells[const_cell->name] = std::move(const_cell);
-    ctx->nets[gnd_net->name] = std::move(gnd_net);
-    ctx->nets[vcc_net->name] = std::move(vcc_net);
 
     for (auto dn : dead_nets) {
         ctx->nets.erase(dn);

From 9ef0bc3d3ad667d937ed803eba7b216a604d5624 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Feb 2022 16:45:45 +0000
Subject: [PATCH 067/712] refactor: Use cell member functions to add ports

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/cells.cc    | 164 +++++++++++------------
 generic/cells.cc |  23 ++--
 gowin/cells.cc   |  34 ++---
 ice40/cells.cc   | 331 +++++++++++++++++++++++------------------------
 machxo2/cells.cc | 131 +++++++++----------
 5 files changed, 322 insertions(+), 361 deletions(-)

diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index e5ab4d4b7d..18d9107f51 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -25,12 +25,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
-{
-    IdString id = ctx->id(name);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
 std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
@@ -49,7 +43,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         }
         NPNR_ASSERT(tgt != BelId());
         for (auto port : ctx->getBelPins(tgt)) {
-            add_port(ctx, new_cell.get(), port.str(ctx), ctx->getBelPinType(tgt, port));
+            new_cell->ports[port] = PortInfo{port, nullptr, ctx->getBelPinType(tgt, port)};
         }
     };
 
@@ -70,104 +64,104 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         new_cell->params[ctx->id("CCU2_INJECT1_1")] = std::string("NO");
         new_cell->params[ctx->id("WREMUX")] = std::string("WRE");
 
-        add_port(ctx, new_cell.get(), "A0", PORT_IN);
-        add_port(ctx, new_cell.get(), "B0", PORT_IN);
-        add_port(ctx, new_cell.get(), "C0", PORT_IN);
-        add_port(ctx, new_cell.get(), "D0", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "A1", PORT_IN);
-        add_port(ctx, new_cell.get(), "B1", PORT_IN);
-        add_port(ctx, new_cell.get(), "C1", PORT_IN);
-        add_port(ctx, new_cell.get(), "D1", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "M0", PORT_IN);
-        add_port(ctx, new_cell.get(), "M1", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "FCI", PORT_IN);
-        add_port(ctx, new_cell.get(), "FXA", PORT_IN);
-        add_port(ctx, new_cell.get(), "FXB", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "CLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "LSR", PORT_IN);
-        add_port(ctx, new_cell.get(), "CE", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "DI0", PORT_IN);
-        add_port(ctx, new_cell.get(), "DI1", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "WD0", PORT_IN);
-        add_port(ctx, new_cell.get(), "WD1", PORT_IN);
-        add_port(ctx, new_cell.get(), "WAD0", PORT_IN);
-        add_port(ctx, new_cell.get(), "WAD1", PORT_IN);
-        add_port(ctx, new_cell.get(), "WAD2", PORT_IN);
-        add_port(ctx, new_cell.get(), "WAD3", PORT_IN);
-        add_port(ctx, new_cell.get(), "WRE", PORT_IN);
-        add_port(ctx, new_cell.get(), "WCK", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "F0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "Q0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "F1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "Q1", PORT_OUT);
-
-        add_port(ctx, new_cell.get(), "FCO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "OFX0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "OFX1", PORT_OUT);
-
-        add_port(ctx, new_cell.get(), "WDO0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WDO1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WDO2", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WDO3", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WADO0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WADO1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WADO2", PORT_OUT);
-        add_port(ctx, new_cell.get(), "WADO3", PORT_OUT);
+        new_cell->addInput(ctx->id("A0"));
+        new_cell->addInput(ctx->id("B0"));
+        new_cell->addInput(ctx->id("C0"));
+        new_cell->addInput(ctx->id("D0"));
+
+        new_cell->addInput(ctx->id("A1"));
+        new_cell->addInput(ctx->id("B1"));
+        new_cell->addInput(ctx->id("C1"));
+        new_cell->addInput(ctx->id("D1"));
+
+        new_cell->addInput(ctx->id("M0"));
+        new_cell->addInput(ctx->id("M1"));
+
+        new_cell->addInput(ctx->id("FCI"));
+        new_cell->addInput(ctx->id("FXA"));
+        new_cell->addInput(ctx->id("FXB"));
+
+        new_cell->addInput(ctx->id("CLK"));
+        new_cell->addInput(ctx->id("LSR"));
+        new_cell->addInput(ctx->id("CE"));
+
+        new_cell->addInput(ctx->id("DI0"));
+        new_cell->addInput(ctx->id("DI1"));
+
+        new_cell->addInput(ctx->id("WD0"));
+        new_cell->addInput(ctx->id("WD1"));
+        new_cell->addInput(ctx->id("WAD0"));
+        new_cell->addInput(ctx->id("WAD1"));
+        new_cell->addInput(ctx->id("WAD2"));
+        new_cell->addInput(ctx->id("WAD3"));
+        new_cell->addInput(ctx->id("WRE"));
+        new_cell->addInput(ctx->id("WCK"));
+
+        new_cell->addOutput(ctx->id("F0"));
+        new_cell->addOutput(ctx->id("Q0"));
+        new_cell->addOutput(ctx->id("F1"));
+        new_cell->addOutput(ctx->id("Q1"));
+
+        new_cell->addOutput(ctx->id("FCO"));
+        new_cell->addOutput(ctx->id("OFX0"));
+        new_cell->addOutput(ctx->id("OFX1"));
+
+        new_cell->addOutput(ctx->id("WDO0"));
+        new_cell->addOutput(ctx->id("WDO1"));
+        new_cell->addOutput(ctx->id("WDO2"));
+        new_cell->addOutput(ctx->id("WDO3"));
+        new_cell->addOutput(ctx->id("WADO0"));
+        new_cell->addOutput(ctx->id("WADO1"));
+        new_cell->addOutput(ctx->id("WADO2"));
+        new_cell->addOutput(ctx->id("WADO3"));
     } else if (type == ctx->id("TRELLIS_IO")) {
         new_cell->params[ctx->id("DIR")] = std::string("INPUT");
         new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
         new_cell->params[ctx->id("DATAMUX_ODDR")] = std::string("PADDO");
         new_cell->params[ctx->id("DATAMUX_MDDR")] = std::string("PADDO");
 
-        add_port(ctx, new_cell.get(), "B", PORT_INOUT);
-        add_port(ctx, new_cell.get(), "I", PORT_IN);
-        add_port(ctx, new_cell.get(), "T", PORT_IN);
-        add_port(ctx, new_cell.get(), "O", PORT_OUT);
+        new_cell->addInout(ctx->id("B"));
+        new_cell->addInput(ctx->id("I"));
+        new_cell->addInput(ctx->id("T"));
+        new_cell->addOutput(ctx->id("O"));
 
-        add_port(ctx, new_cell.get(), "IOLDO", PORT_IN);
-        add_port(ctx, new_cell.get(), "IOLTO", PORT_IN);
+        new_cell->addInput(ctx->id("IOLDO"));
+        new_cell->addInput(ctx->id("IOLTO"));
 
     } else if (type == ctx->id("LUT4")) {
         new_cell->params[ctx->id("INIT")] = Property(0, 16);
 
-        add_port(ctx, new_cell.get(), "A", PORT_IN);
-        add_port(ctx, new_cell.get(), "B", PORT_IN);
-        add_port(ctx, new_cell.get(), "C", PORT_IN);
-        add_port(ctx, new_cell.get(), "D", PORT_IN);
-        add_port(ctx, new_cell.get(), "Z", PORT_OUT);
+        new_cell->addInput(ctx->id("A"));
+        new_cell->addInput(ctx->id("B"));
+        new_cell->addInput(ctx->id("C"));
+        new_cell->addInput(ctx->id("D"));
+        new_cell->addOutput(ctx->id("Z"));
     } else if (type == ctx->id("CCU2C")) {
         new_cell->params[ctx->id("INIT0")] = Property(0, 16);
         new_cell->params[ctx->id("INIT1")] = Property(0, 16);
         new_cell->params[ctx->id("INJECT1_0")] = std::string("YES");
         new_cell->params[ctx->id("INJECT1_1")] = std::string("YES");
 
-        add_port(ctx, new_cell.get(), "CIN", PORT_IN);
+        new_cell->addInput(ctx->id("CIN"));
 
-        add_port(ctx, new_cell.get(), "A0", PORT_IN);
-        add_port(ctx, new_cell.get(), "B0", PORT_IN);
-        add_port(ctx, new_cell.get(), "C0", PORT_IN);
-        add_port(ctx, new_cell.get(), "D0", PORT_IN);
+        new_cell->addInput(ctx->id("A0"));
+        new_cell->addInput(ctx->id("B0"));
+        new_cell->addInput(ctx->id("C0"));
+        new_cell->addInput(ctx->id("D0"));
 
-        add_port(ctx, new_cell.get(), "A1", PORT_IN);
-        add_port(ctx, new_cell.get(), "B1", PORT_IN);
-        add_port(ctx, new_cell.get(), "C1", PORT_IN);
-        add_port(ctx, new_cell.get(), "D1", PORT_IN);
+        new_cell->addInput(ctx->id("A1"));
+        new_cell->addInput(ctx->id("B1"));
+        new_cell->addInput(ctx->id("C1"));
+        new_cell->addInput(ctx->id("D1"));
 
-        add_port(ctx, new_cell.get(), "S0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "S1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
+        new_cell->addOutput(ctx->id("S0"));
+        new_cell->addOutput(ctx->id("S1"));
+        new_cell->addOutput(ctx->id("COUT"));
 
     } else if (type == ctx->id("DCCA")) {
-        add_port(ctx, new_cell.get(), "CLKI", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLKO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "CE", PORT_IN);
+        new_cell->addInput(ctx->id("CLKI"));
+        new_cell->addOutput(ctx->id("CLKO"));
+        new_cell->addInput(ctx->id("CE"));
     } else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
         new_cell->params[ctx->id("MODE")] = std::string("NONE");
         new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
@@ -198,8 +192,8 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         // Just copy ports from the Bel
         copy_bel_ports();
     } else if (type == id_TRELLIS_ECLKBUF) {
-        add_port(ctx, new_cell.get(), "ECLKI", PORT_IN);
-        add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT);
+        new_cell->addInput(ctx->id("ECLKI"));
+        new_cell->addOutput(ctx->id("ECLKO"));
     } else {
         log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
     }
diff --git a/generic/cells.cc b/generic/cells.cc
index 967afb23ca..c14ddf7306 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -24,13 +24,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
-{
-    IdString id = ctx->id(name);
-    NPNR_ASSERT(cell->ports.count(id) == 0);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
 std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
@@ -43,21 +36,21 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->params[ctx->id("FF_USED")] = 0;
 
         for (int i = 0; i < ctx->args.K; i++)
-            add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
+            new_cell->addInput(ctx->id("I[" + std::to_string(i) + "]"));
 
-        add_port(ctx, new_cell.get(), "CLK", PORT_IN);
+        new_cell->addInput(ctx->id("CLK"));
 
-        add_port(ctx, new_cell.get(), "F", PORT_OUT);
-        add_port(ctx, new_cell.get(), "Q", PORT_OUT);
+        new_cell->addOutput(ctx->id("F"));
+        new_cell->addOutput(ctx->id("Q"));
     } else if (type == ctx->id("GENERIC_IOB")) {
         new_cell->params[ctx->id("INPUT_USED")] = 0;
         new_cell->params[ctx->id("OUTPUT_USED")] = 0;
         new_cell->params[ctx->id("ENABLE_USED")] = 0;
 
-        add_port(ctx, new_cell.get(), "PAD", PORT_INOUT);
-        add_port(ctx, new_cell.get(), "I", PORT_IN);
-        add_port(ctx, new_cell.get(), "EN", PORT_IN);
-        add_port(ctx, new_cell.get(), "O", PORT_OUT);
+        new_cell->addInout(ctx->id("PAD"));
+        new_cell->addInput(ctx->id("I"));
+        new_cell->addInput(ctx->id("EN"));
+        new_cell->addOutput(ctx->id("O"));
     } else {
         log_error("unable to create generic cell of type %s", type.c_str(ctx));
     }
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 67a81f39f9..aef34f535a 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -26,12 +26,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
-{
-    NPNR_ASSERT(cell->ports.count(id) == 0);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
 std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
@@ -45,30 +39,30 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
 
         IdString names[4] = {id_A, id_B, id_C, id_D};
         for (int i = 0; i < 4; i++) {
-            add_port(ctx, new_cell.get(), names[i], PORT_IN);
+            new_cell->addInput(names[i]);
         }
 
-        add_port(ctx, new_cell.get(), id_CLK, PORT_IN);
+        new_cell->addInput(id_CLK);
 
-        add_port(ctx, new_cell.get(), id_F, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_Q, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_CE, PORT_IN);
-        add_port(ctx, new_cell.get(), id_LSR, PORT_IN);
+        new_cell->addOutput(id_F);
+        new_cell->addOutput(id_Q);
+        new_cell->addInput(id_CE);
+        new_cell->addInput(id_LSR);
     } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
                type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
-        add_port(ctx, new_cell.get(), id_I0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_I1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_SEL, PORT_IN);
-        add_port(ctx, new_cell.get(), id_OF, PORT_OUT);
+        new_cell->addInput(id_I0);
+        new_cell->addInput(id_I1);
+        new_cell->addInput(id_SEL);
+        new_cell->addOutput(id_OF);
     } else if (type == id_IOB || type == id_IOBS) {
         new_cell->params[id_INPUT_USED] = 0;
         new_cell->params[id_OUTPUT_USED] = 0;
         new_cell->params[id_ENABLE_USED] = 0;
 
-        add_port(ctx, new_cell.get(), id_PAD, PORT_INOUT);
-        add_port(ctx, new_cell.get(), id_I, PORT_IN);
-        add_port(ctx, new_cell.get(), id_OEN, PORT_IN);
-        add_port(ctx, new_cell.get(), id_O, PORT_OUT);
+        new_cell->addInout(id_PAD);
+        new_cell->addInput(id_I);
+        new_cell->addInput(id_OEN);
+        new_cell->addOutput(id_O);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 9a75118f53..b97131a62e 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -26,13 +26,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
-{
-    IdString id = ctx->id(name);
-    NPNR_ASSERT(cell->ports.count(id) == 0);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
 std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
@@ -50,97 +43,97 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         new_cell->params[ctx->id("CIN_CONST")] = Property::State::S0;
         new_cell->params[ctx->id("CIN_SET")] = Property::State::S0;
 
-        add_port(ctx, new_cell.get(), "I0", PORT_IN);
-        add_port(ctx, new_cell.get(), "I1", PORT_IN);
-        add_port(ctx, new_cell.get(), "I2", PORT_IN);
-        add_port(ctx, new_cell.get(), "I3", PORT_IN);
-        add_port(ctx, new_cell.get(), "CIN", PORT_IN);
+        new_cell->addInput(ctx->id("I0"));
+        new_cell->addInput(ctx->id("I1"));
+        new_cell->addInput(ctx->id("I2"));
+        new_cell->addInput(ctx->id("I3"));
+        new_cell->addInput(ctx->id("CIN"));
 
-        add_port(ctx, new_cell.get(), "CLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "CEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "SR", PORT_IN);
+        new_cell->addInput(ctx->id("CLK"));
+        new_cell->addInput(ctx->id("CEN"));
+        new_cell->addInput(ctx->id("SR"));
 
-        add_port(ctx, new_cell.get(), "LO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "O", PORT_OUT);
-        add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
+        new_cell->addOutput(ctx->id("LO"));
+        new_cell->addOutput(ctx->id("O"));
+        new_cell->addOutput(ctx->id("COUT"));
     } else if (type == ctx->id("SB_IO")) {
         new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6);
         new_cell->params[ctx->id("PULLUP")] = Property::State::S0;
         new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
         new_cell->params[ctx->id("IO_STANDARD")] = Property("SB_LVCMOS");
 
-        add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT);
+        new_cell->addInout(ctx->id("PACKAGE_PIN"));
 
-        add_port(ctx, new_cell.get(), "LATCH_INPUT_VALUE", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLOCK_ENABLE", PORT_IN);
-        add_port(ctx, new_cell.get(), "INPUT_CLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "OUTPUT_CLK", PORT_IN);
+        new_cell->addInput(ctx->id("LATCH_INPUT_VALUE"));
+        new_cell->addInput(ctx->id("CLOCK_ENABLE"));
+        new_cell->addInput(ctx->id("INPUT_CLK"));
+        new_cell->addInput(ctx->id("OUTPUT_CLK"));
 
-        add_port(ctx, new_cell.get(), "OUTPUT_ENABLE", PORT_IN);
-        add_port(ctx, new_cell.get(), "D_OUT_0", PORT_IN);
-        add_port(ctx, new_cell.get(), "D_OUT_1", PORT_IN);
+        new_cell->addInput(ctx->id("OUTPUT_ENABLE"));
+        new_cell->addInput(ctx->id("D_OUT_0"));
+        new_cell->addInput(ctx->id("D_OUT_1"));
 
-        add_port(ctx, new_cell.get(), "D_IN_0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "D_IN_1", PORT_OUT);
+        new_cell->addOutput(ctx->id("D_IN_0"));
+        new_cell->addOutput(ctx->id("D_IN_1"));
     } else if (type == ctx->id("ICESTORM_RAM")) {
         new_cell->params[ctx->id("NEG_CLK_W")] = Property::State::S0;
         new_cell->params[ctx->id("NEG_CLK_R")] = Property::State::S0;
         new_cell->params[ctx->id("WRITE_MODE")] = Property::State::S0;
         new_cell->params[ctx->id("READ_MODE")] = Property::State::S0;
 
-        add_port(ctx, new_cell.get(), "RCLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "RCLKE", PORT_IN);
-        add_port(ctx, new_cell.get(), "RE", PORT_IN);
+        new_cell->addInput(ctx->id("RCLK"));
+        new_cell->addInput(ctx->id("RCLKE"));
+        new_cell->addInput(ctx->id("RE"));
 
-        add_port(ctx, new_cell.get(), "WCLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "WCLKE", PORT_IN);
-        add_port(ctx, new_cell.get(), "WE", PORT_IN);
+        new_cell->addInput(ctx->id("WCLK"));
+        new_cell->addInput(ctx->id("WCLKE"));
+        new_cell->addInput(ctx->id("WE"));
 
         for (int i = 0; i < 16; i++) {
-            add_port(ctx, new_cell.get(), "WDATA_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "MASK_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "RDATA_" + std::to_string(i), PORT_OUT);
+            new_cell->addInput(ctx->id("WDATA_" + std::to_string(i)));
+            new_cell->addInput(ctx->id("MASK_" + std::to_string(i)));
+            new_cell->addOutput(ctx->id("RDATA_" + std::to_string(i)));
         }
 
         for (int i = 0; i < 11; i++) {
-            add_port(ctx, new_cell.get(), "RADDR_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "WADDR_" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("RADDR_" + std::to_string(i)));
+            new_cell->addInput(ctx->id("WADDR_" + std::to_string(i)));
         }
     } else if (type == ctx->id("ICESTORM_LFOSC")) {
-        add_port(ctx, new_cell.get(), "CLKLFEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLKLFPU", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLKLF", PORT_OUT);
-        add_port(ctx, new_cell.get(), "CLKLF_FABRIC", PORT_OUT);
+        new_cell->addInput(ctx->id("CLKLFEN"));
+        new_cell->addInput(ctx->id("CLKLFPU"));
+        new_cell->addOutput(ctx->id("CLKLF"));
+        new_cell->addOutput(ctx->id("CLKLF_FABRIC"));
     } else if (type == ctx->id("ICESTORM_HFOSC")) {
         new_cell->params[ctx->id("CLKHF_DIV")] = Property("0b00");
         new_cell->params[ctx->id("TRIM_EN")] = Property("0b0");
 
-        add_port(ctx, new_cell.get(), "CLKHFEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLKHFPU", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLKHF", PORT_OUT);
-        add_port(ctx, new_cell.get(), "CLKHF_FABRIC", PORT_OUT);
+        new_cell->addInput(ctx->id("CLKHFEN"));
+        new_cell->addInput(ctx->id("CLKHFPU"));
+        new_cell->addOutput(ctx->id("CLKHF"));
+        new_cell->addOutput(ctx->id("CLKHF_FABRIC"));
         for (int i = 0; i < 10; i++)
-            add_port(ctx, new_cell.get(), "TRIM" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("TRIM" + std::to_string(i)));
     } else if (type == ctx->id("SB_GB")) {
-        add_port(ctx, new_cell.get(), "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN);
-        add_port(ctx, new_cell.get(), "GLOBAL_BUFFER_OUTPUT", PORT_OUT);
+        new_cell->addInput(ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER"));
+        new_cell->addOutput(ctx->id("GLOBAL_BUFFER_OUTPUT"));
     } else if (type == ctx->id("ICESTORM_SPRAM")) {
-        add_port(ctx, new_cell.get(), "WREN", PORT_IN);
-        add_port(ctx, new_cell.get(), "CHIPSELECT", PORT_IN);
-        add_port(ctx, new_cell.get(), "CLOCK", PORT_IN);
-        add_port(ctx, new_cell.get(), "STANDBY", PORT_IN);
-        add_port(ctx, new_cell.get(), "SLEEP", PORT_IN);
-        add_port(ctx, new_cell.get(), "POWEROFF", PORT_IN);
+        new_cell->addInput(ctx->id("WREN"));
+        new_cell->addInput(ctx->id("CHIPSELECT"));
+        new_cell->addInput(ctx->id("CLOCK"));
+        new_cell->addInput(ctx->id("STANDBY"));
+        new_cell->addInput(ctx->id("SLEEP"));
+        new_cell->addInput(ctx->id("POWEROFF"));
 
         for (int i = 0; i < 16; i++) {
-            add_port(ctx, new_cell.get(), "DATAIN_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "DATAOUT_" + std::to_string(i), PORT_OUT);
+            new_cell->addInput(ctx->id("DATAIN_" + std::to_string(i)));
+            new_cell->addOutput(ctx->id("DATAOUT_" + std::to_string(i)));
         }
         for (int i = 0; i < 14; i++) {
-            add_port(ctx, new_cell.get(), "ADDRESS_" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("ADDRESS_" + std::to_string(i)));
         }
         for (int i = 0; i < 4; i++) {
-            add_port(ctx, new_cell.get(), "MASKWREN_" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("MASKWREN_" + std::to_string(i)));
         }
     } else if (type == ctx->id("ICESTORM_DSP")) {
         new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
@@ -168,44 +161,44 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         new_cell->params[ctx->id("A_SIGNED")] = Property::State::S0;
         new_cell->params[ctx->id("B_SIGNED")] = Property::State::S0;
 
-        add_port(ctx, new_cell.get(), "CLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "CE", PORT_IN);
+        new_cell->addInput(ctx->id("CLK"));
+        new_cell->addInput(ctx->id("CE"));
         for (int i = 0; i < 16; i++) {
-            add_port(ctx, new_cell.get(), "C_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "A_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "B_" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "D_" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("C_" + std::to_string(i)));
+            new_cell->addInput(ctx->id("A_" + std::to_string(i)));
+            new_cell->addInput(ctx->id("B_" + std::to_string(i)));
+            new_cell->addInput(ctx->id("D_" + std::to_string(i)));
         }
-        add_port(ctx, new_cell.get(), "AHOLD", PORT_IN);
-        add_port(ctx, new_cell.get(), "BHOLD", PORT_IN);
-        add_port(ctx, new_cell.get(), "CHOLD", PORT_IN);
-        add_port(ctx, new_cell.get(), "DHOLD", PORT_IN);
+        new_cell->addInput(ctx->id("AHOLD"));
+        new_cell->addInput(ctx->id("BHOLD"));
+        new_cell->addInput(ctx->id("CHOLD"));
+        new_cell->addInput(ctx->id("DHOLD"));
 
-        add_port(ctx, new_cell.get(), "IRSTTOP", PORT_IN);
-        add_port(ctx, new_cell.get(), "IRSTBOT", PORT_IN);
-        add_port(ctx, new_cell.get(), "ORSTTOP", PORT_IN);
-        add_port(ctx, new_cell.get(), "ORSTBOT", PORT_IN);
+        new_cell->addInput(ctx->id("IRSTTOP"));
+        new_cell->addInput(ctx->id("IRSTBOT"));
+        new_cell->addInput(ctx->id("ORSTTOP"));
+        new_cell->addInput(ctx->id("ORSTBOT"));
 
-        add_port(ctx, new_cell.get(), "OLOADTOP", PORT_IN);
-        add_port(ctx, new_cell.get(), "OLOADBOT", PORT_IN);
+        new_cell->addInput(ctx->id("OLOADTOP"));
+        new_cell->addInput(ctx->id("OLOADBOT"));
 
-        add_port(ctx, new_cell.get(), "ADDSUBTOP", PORT_IN);
-        add_port(ctx, new_cell.get(), "ADDSUBBOT", PORT_IN);
+        new_cell->addInput(ctx->id("ADDSUBTOP"));
+        new_cell->addInput(ctx->id("ADDSUBBOT"));
 
-        add_port(ctx, new_cell.get(), "OHOLDTOP", PORT_IN);
-        add_port(ctx, new_cell.get(), "OHOLDBOT", PORT_IN);
+        new_cell->addInput(ctx->id("OHOLDTOP"));
+        new_cell->addInput(ctx->id("OHOLDBOT"));
 
-        add_port(ctx, new_cell.get(), "CI", PORT_IN);
-        add_port(ctx, new_cell.get(), "ACCUMCI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SIGNEXTIN", PORT_IN);
+        new_cell->addInput(ctx->id("CI"));
+        new_cell->addInput(ctx->id("ACCUMCI"));
+        new_cell->addInput(ctx->id("SIGNEXTIN"));
 
         for (int i = 0; i < 32; i++) {
-            add_port(ctx, new_cell.get(), "O_" + std::to_string(i), PORT_OUT);
+            new_cell->addOutput(ctx->id("O_" + std::to_string(i)));
         }
 
-        add_port(ctx, new_cell.get(), "CO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "ACCUMCO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SIGNEXTOUT", PORT_OUT);
+        new_cell->addOutput(ctx->id("CO"));
+        new_cell->addOutput(ctx->id("ACCUMCO"));
+        new_cell->addOutput(ctx->id("SIGNEXTOUT"));
 
     } else if (type == ctx->id("ICESTORM_PLL")) {
         new_cell->params[ctx->id("DELAY_ADJMODE_FB")] = Property::State::S0;
@@ -227,114 +220,114 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         new_cell->params[ctx->id("SHIFTREG_DIVMODE")] = Property::State::S0;
         new_cell->params[ctx->id("TEST_MODE")] = Property::State::S0;
 
-        add_port(ctx, new_cell.get(), "BYPASS", PORT_IN);
+        new_cell->addInput(ctx->id("BYPASS"));
         for (int i = 0; i < 8; i++)
-            add_port(ctx, new_cell.get(), "DYNAMICDELAY_" + std::to_string(i), PORT_IN);
-        add_port(ctx, new_cell.get(), "EXTFEEDBACK", PORT_IN);
-        add_port(ctx, new_cell.get(), "LATCHINPUTVALUE", PORT_IN);
-        add_port(ctx, new_cell.get(), "REFERENCECLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "RESETB", PORT_IN);
-
-        add_port(ctx, new_cell.get(), "SCLK", PORT_IN);
-        add_port(ctx, new_cell.get(), "SDI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SDO", PORT_OUT);
-
-        add_port(ctx, new_cell.get(), "LOCK", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PLLOUT_B", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PLLOUT_A_GLOBAL", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PLLOUT_B_GLOBAL", PORT_OUT);
+            new_cell->addInput(ctx->id("DYNAMICDELAY_" + std::to_string(i)));
+        new_cell->addInput(ctx->id("EXTFEEDBACK"));
+        new_cell->addInput(ctx->id("LATCHINPUTVALUE"));
+        new_cell->addInput(ctx->id("REFERENCECLK"));
+        new_cell->addInput(ctx->id("RESETB"));
+
+        new_cell->addInput(ctx->id("SCLK"));
+        new_cell->addInput(ctx->id("SDI"));
+        new_cell->addOutput(ctx->id("SDO"));
+
+        new_cell->addOutput(ctx->id("LOCK"));
+        new_cell->addOutput(ctx->id("PLLOUT_A"));
+        new_cell->addOutput(ctx->id("PLLOUT_B"));
+        new_cell->addOutput(ctx->id("PLLOUT_A_GLOBAL"));
+        new_cell->addOutput(ctx->id("PLLOUT_B_GLOBAL"));
     } else if (type == ctx->id("SB_RGBA_DRV")) {
         new_cell->params[ctx->id("CURRENT_MODE")] = std::string("0b0");
         new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
         new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
         new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
 
-        add_port(ctx, new_cell.get(), "CURREN", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGBLEDEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB0PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB1PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB2PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "RGB1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "RGB2", PORT_OUT);
+        new_cell->addInput(ctx->id("CURREN"));
+        new_cell->addInput(ctx->id("RGBLEDEN"));
+        new_cell->addInput(ctx->id("RGB0PWM"));
+        new_cell->addInput(ctx->id("RGB1PWM"));
+        new_cell->addInput(ctx->id("RGB2PWM"));
+        new_cell->addOutput(ctx->id("RGB0"));
+        new_cell->addOutput(ctx->id("RGB1"));
+        new_cell->addOutput(ctx->id("RGB2"));
     } else if (type == ctx->id("SB_LED_DRV_CUR")) {
-        add_port(ctx, new_cell.get(), "EN", PORT_IN);
-        add_port(ctx, new_cell.get(), "LEDPU", PORT_OUT);
+        new_cell->addInput(ctx->id("EN"));
+        new_cell->addOutput(ctx->id("LEDPU"));
     } else if (type == ctx->id("SB_RGB_DRV")) {
         new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
         new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
         new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
 
-        add_port(ctx, new_cell.get(), "RGBPU", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGBLEDEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB0PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB1PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB2PWM", PORT_IN);
-        add_port(ctx, new_cell.get(), "RGB0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "RGB1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "RGB2", PORT_OUT);
+        new_cell->addInput(ctx->id("RGBPU"));
+        new_cell->addInput(ctx->id("RGBLEDEN"));
+        new_cell->addInput(ctx->id("RGB0PWM"));
+        new_cell->addInput(ctx->id("RGB1PWM"));
+        new_cell->addInput(ctx->id("RGB2PWM"));
+        new_cell->addOutput(ctx->id("RGB0"));
+        new_cell->addOutput(ctx->id("RGB1"));
+        new_cell->addOutput(ctx->id("RGB2"));
     } else if (type == ctx->id("SB_LEDDA_IP")) {
-        add_port(ctx, new_cell.get(), "LEDDCS", PORT_IN);
-        add_port(ctx, new_cell.get(), "LEDDCLK", PORT_IN);
+        new_cell->addInput(ctx->id("LEDDCS"));
+        new_cell->addInput(ctx->id("LEDDCLK"));
         for (int i = 0; i < 8; i++)
-            add_port(ctx, new_cell.get(), "LEDDDAT" + std::to_string(i), PORT_IN);
+            new_cell->addInput(ctx->id("LEDDDAT" + std::to_string(i)));
         for (int i = 0; i < 3; i++)
-            add_port(ctx, new_cell.get(), "LEDDADDR" + std::to_string(i), PORT_IN);
-        add_port(ctx, new_cell.get(), "LEDDDEN", PORT_IN);
-        add_port(ctx, new_cell.get(), "LEDDEXE", PORT_IN);
-        add_port(ctx, new_cell.get(), "LEDDRST", PORT_IN); // doesn't actually exist, for icecube code compatibility
-                                                           // only
-        add_port(ctx, new_cell.get(), "PWMOUT0", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PWMOUT1", PORT_OUT);
-        add_port(ctx, new_cell.get(), "PWMOUT2", PORT_OUT);
-        add_port(ctx, new_cell.get(), "LEDDON", PORT_OUT);
+            new_cell->addInput(ctx->id("LEDDADDR" + std::to_string(i)));
+        new_cell->addInput(ctx->id("LEDDDEN"));
+        new_cell->addInput(ctx->id("LEDDEXE"));
+        new_cell->addInput(ctx->id("LEDDRST")); // doesn't actually exist, for icecube code compatibility
+                                                // only
+        new_cell->addOutput(ctx->id("PWMOUT0"));
+        new_cell->addOutput(ctx->id("PWMOUT1"));
+        new_cell->addOutput(ctx->id("PWMOUT2"));
+        new_cell->addOutput(ctx->id("LEDDON"));
     } else if (type == ctx->id("SB_I2C")) {
         new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = std::string("0b1111100001");
         new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0001");
         for (int i = 0; i < 8; i++) {
-            add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT);
+            new_cell->addInput(ctx->id("SBADRI" + std::to_string(i)));
+            new_cell->addInput(ctx->id("SBDATI" + std::to_string(i)));
+            new_cell->addOutput(ctx->id("SBDATO" + std::to_string(i)));
         }
-        add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBRWI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SCLI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SDAI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "I2CIRQ", PORT_OUT);
-        add_port(ctx, new_cell.get(), "I2CWKUP", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SCLO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SCLOE", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SDAO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SDAOE", PORT_OUT);
+        new_cell->addInput(ctx->id("SBCLKI"));
+        new_cell->addInput(ctx->id("SBRWI"));
+        new_cell->addInput(ctx->id("SBSTBI"));
+        new_cell->addInput(ctx->id("SCLI"));
+        new_cell->addInput(ctx->id("SDAI"));
+        new_cell->addOutput(ctx->id("SBACKO"));
+        new_cell->addOutput(ctx->id("I2CIRQ"));
+        new_cell->addOutput(ctx->id("I2CWKUP"));
+        new_cell->addOutput(ctx->id("SCLO"));
+        new_cell->addOutput(ctx->id("SCLOE"));
+        new_cell->addOutput(ctx->id("SDAO"));
+        new_cell->addOutput(ctx->id("SDAOE"));
     } else if (type == ctx->id("SB_SPI")) {
         new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0000");
         for (int i = 0; i < 8; i++) {
-            add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN);
-            add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT);
+            new_cell->addInput(ctx->id("SBADRI" + std::to_string(i)));
+            new_cell->addInput(ctx->id("SBDATI" + std::to_string(i)));
+            new_cell->addOutput(ctx->id("SBDATO" + std::to_string(i)));
         }
-        add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBRWI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN);
-        add_port(ctx, new_cell.get(), "MI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SCKI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SCSNI", PORT_IN);
-        add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SPIIRQ", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SPIWKUP", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SOE", PORT_OUT);
-        add_port(ctx, new_cell.get(), "MO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "MOE", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SCKO", PORT_OUT);
-        add_port(ctx, new_cell.get(), "SCKOE", PORT_OUT);
+        new_cell->addInput(ctx->id("SBCLKI"));
+        new_cell->addInput(ctx->id("SBRWI"));
+        new_cell->addInput(ctx->id("SBSTBI"));
+        new_cell->addInput(ctx->id("MI"));
+        new_cell->addInput(ctx->id("SI"));
+        new_cell->addInput(ctx->id("SCKI"));
+        new_cell->addInput(ctx->id("SCSNI"));
+        new_cell->addOutput(ctx->id("SBACKO"));
+        new_cell->addOutput(ctx->id("SPIIRQ"));
+        new_cell->addOutput(ctx->id("SPIWKUP"));
+        new_cell->addOutput(ctx->id("SO"));
+        new_cell->addOutput(ctx->id("SOE"));
+        new_cell->addOutput(ctx->id("MO"));
+        new_cell->addOutput(ctx->id("MOE"));
+        new_cell->addOutput(ctx->id("SCKO"));
+        new_cell->addOutput(ctx->id("SCKOE"));
         for (int i = 0; i < 4; i++) {
-            add_port(ctx, new_cell.get(), "MCSNO" + std::to_string(i), PORT_OUT);
-            add_port(ctx, new_cell.get(), "MCSNOE" + std::to_string(i), PORT_OUT);
+            new_cell->addOutput(ctx->id("MCSNO" + std::to_string(i)));
+            new_cell->addOutput(ctx->id("MCSNOE" + std::to_string(i)));
         }
     } else {
         log_error("unable to create iCE40 cell of type %s", type.c_str(ctx));
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index 534d8e3cc9..bbe3f2d636 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -25,19 +25,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
-{
-    IdString id = ctx->id(name);
-    NPNR_ASSERT(cell->ports.count(id) == 0);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
-void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
-{
-    NPNR_ASSERT(cell->ports.count(id) == 0);
-    cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
 std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name)
 {
     static int auto_idx = 0;
@@ -64,72 +51,72 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->params[id_CCU2_INJECT1_1] = std::string("YES");
         new_cell->params[id_WREMUX] = std::string("INV");
 
-        add_port(ctx, new_cell.get(), id_A0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_B0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_C0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_D0, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_A1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_B1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_C1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_D1, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_M0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_M1, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_FCI, PORT_IN);
-        add_port(ctx, new_cell.get(), id_FXA, PORT_IN);
-        add_port(ctx, new_cell.get(), id_FXB, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_CLK, PORT_IN);
-        add_port(ctx, new_cell.get(), id_LSR, PORT_IN);
-        add_port(ctx, new_cell.get(), id_CE, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_DI0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_DI1, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_WD0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WD1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WAD0, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WAD1, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WAD2, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WAD3, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WRE, PORT_IN);
-        add_port(ctx, new_cell.get(), id_WCK, PORT_IN);
-
-        add_port(ctx, new_cell.get(), id_F0, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_Q0, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_F1, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_Q1, PORT_OUT);
-
-        add_port(ctx, new_cell.get(), id_FCO, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_OFX0, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_OFX1, PORT_OUT);
-
-        add_port(ctx, new_cell.get(), id_WDO0, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WDO1, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WDO2, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WDO3, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WADO0, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WADO1, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WADO2, PORT_OUT);
-        add_port(ctx, new_cell.get(), id_WADO3, PORT_OUT);
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addInput(id_M0);
+        new_cell->addInput(id_M1);
+
+        new_cell->addInput(id_FCI);
+        new_cell->addInput(id_FXA);
+        new_cell->addInput(id_FXB);
+
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_LSR);
+        new_cell->addInput(id_CE);
+
+        new_cell->addInput(id_DI0);
+        new_cell->addInput(id_DI1);
+
+        new_cell->addInput(id_WD0);
+        new_cell->addInput(id_WD1);
+        new_cell->addInput(id_WAD0);
+        new_cell->addInput(id_WAD1);
+        new_cell->addInput(id_WAD2);
+        new_cell->addInput(id_WAD3);
+        new_cell->addInput(id_WRE);
+        new_cell->addInput(id_WCK);
+
+        new_cell->addOutput(id_F0);
+        new_cell->addOutput(id_Q0);
+        new_cell->addOutput(id_F1);
+        new_cell->addOutput(id_Q1);
+
+        new_cell->addOutput(id_FCO);
+        new_cell->addOutput(id_OFX0);
+        new_cell->addOutput(id_OFX1);
+
+        new_cell->addOutput(id_WDO0);
+        new_cell->addOutput(id_WDO1);
+        new_cell->addOutput(id_WDO2);
+        new_cell->addOutput(id_WDO3);
+        new_cell->addOutput(id_WADO0);
+        new_cell->addOutput(id_WADO1);
+        new_cell->addOutput(id_WADO2);
+        new_cell->addOutput(id_WADO3);
     } else if (type == id_FACADE_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
         new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
 
-        add_port(ctx, new_cell.get(), "PAD", PORT_INOUT);
-        add_port(ctx, new_cell.get(), "I", PORT_IN);
-        add_port(ctx, new_cell.get(), "EN", PORT_IN);
-        add_port(ctx, new_cell.get(), "O", PORT_OUT);
+        new_cell->addInout(ctx->id("PAD"));
+        new_cell->addInput(ctx->id("I"));
+        new_cell->addInput(ctx->id("EN"));
+        new_cell->addOutput(ctx->id("O"));
     } else if (type == id_LUT4) {
         new_cell->params[id_INIT] = Property(0, 16);
 
-        add_port(ctx, new_cell.get(), id_A, PORT_IN);
-        add_port(ctx, new_cell.get(), id_B, PORT_IN);
-        add_port(ctx, new_cell.get(), id_C, PORT_IN);
-        add_port(ctx, new_cell.get(), id_D, PORT_IN);
-        add_port(ctx, new_cell.get(), id_Z, PORT_OUT);
+        new_cell->addInput(id_A);
+        new_cell->addInput(id_B);
+        new_cell->addInput(id_C);
+        new_cell->addInput(id_D);
+        new_cell->addOutput(id_Z);
     } else {
         log_error("unable to create MachXO2 cell of type %s", type.c_str(ctx));
     }

From 76683a1e3c123d28deff750c38467c6377936879 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Feb 2022 17:09:54 +0000
Subject: [PATCH 068/712] refactor: Use constids instead of id("..")

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.cc         |  37 +-
 ecp5/arch_place.cc   |   2 +-
 ecp5/bitstream.cc    | 495 +++++++++++-------------
 ecp5/cells.cc        | 426 ++++++++++-----------
 ecp5/cells.h         |  33 +-
 ecp5/constids.inc    | 510 +++++++++++++++++++++++++
 ecp5/dcu_bitstream.h | 588 +++++++++++++---------------
 ecp5/globals.cc      |  14 +-
 ecp5/lpf.cc          |   2 +-
 ecp5/main.cc         |   2 +-
 ecp5/pack.cc         | 883 +++++++++++++++++++++----------------------
 gowin/arch.cc        |  24 +-
 gowin/arch.h         |   2 +-
 gowin/constids.inc   |   9 +
 gowin/pack.cc        |  60 +--
 ice40/arch.cc        |  90 ++---
 ice40/arch_place.cc  |   2 +-
 ice40/bitstream.cc   |  90 ++---
 ice40/cells.cc       | 588 ++++++++++++++--------------
 ice40/cells.h        |  80 ++--
 ice40/chains.cc      |  55 ++-
 ice40/constids.inc   | 166 +++++++-
 ice40/main.cc        |   8 +-
 ice40/pack.cc        | 363 +++++++++---------
 ice40/pcf.cc         |  16 +-
 machxo2/arch.cc      |  22 +-
 machxo2/arch.h       |   2 +-
 machxo2/bitstream.cc |  40 +-
 machxo2/cells.cc     |  34 +-
 machxo2/cells.h      |   6 +-
 machxo2/constids.inc |  19 +
 machxo2/pack.cc      |  22 +-
 mistral/arch.cc      |   8 +-
 mistral/constids.inc |   8 +
 mistral/globals.cc   |   6 +-
 mistral/main.cc      |   2 +-
 nexus/arch.cc        |  40 +-
 nexus/constids.inc   |  21 +
 nexus/main.cc        |   6 +-
 nexus/pack.cc        |  40 +-
 nexus/post_place.cc  |   2 +-
 41 files changed, 2686 insertions(+), 2137 deletions(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 2e453f2a90..3d20badb22 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -202,25 +202,25 @@ std::string Arch::get_full_chip_name() const
 IdString Arch::archArgsToId(ArchArgs args) const
 {
     if (args.type == ArchArgs::LFE5U_12F)
-        return id("lfe5u_12f");
+        return id_lfe5u_12f;
     if (args.type == ArchArgs::LFE5U_25F)
-        return id("lfe5u_25f");
+        return id_lfe5u_25f;
     if (args.type == ArchArgs::LFE5U_45F)
-        return id("lfe5u_45f");
+        return id_lfe5u_45f;
     if (args.type == ArchArgs::LFE5U_85F)
-        return id("lfe5u_85f");
+        return id_lfe5u_85f;
     if (args.type == ArchArgs::LFE5UM_25F)
-        return id("lfe5um_25f");
+        return id_lfe5um_25f;
     if (args.type == ArchArgs::LFE5UM_45F)
-        return id("lfe5um_45f");
+        return id_lfe5um_45f;
     if (args.type == ArchArgs::LFE5UM_85F)
-        return id("lfe5um_85f");
+        return id_lfe5um_85f;
     if (args.type == ArchArgs::LFE5UM5G_25F)
-        return id("lfe5um5g_25f");
+        return id_lfe5um5g_25f;
     if (args.type == ArchArgs::LFE5UM5G_45F)
-        return id("lfe5um5g_45f");
+        return id_lfe5um5g_45f;
     if (args.type == ArchArgs::LFE5UM5G_85F)
-        return id("lfe5um5g_85f");
+        return id_lfe5um5g_85f;
     return IdString();
 }
 
@@ -586,7 +586,7 @@ delay_t Arch::getRipupDelayPenalty() const { return 400; }
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
 
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
@@ -612,7 +612,7 @@ bool Arch::place()
         for (auto &cell : cells)
             cell.second->belStrength = STRENGTH_LOCKED;
 
-    getCtx()->settings[getCtx()->id("place")] = 1;
+    getCtx()->settings[id_place] = 1;
 
     archInfoToAttributes();
     return true;
@@ -620,7 +620,7 @@ bool Arch::place()
 
 bool Arch::route()
 {
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
 
     disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
 
@@ -639,7 +639,7 @@ bool Arch::route()
         log_error("ECP5 architecture does not support router '%s'\n", router.c_str());
     }
 
-    getCtx()->settings[getCtx()->id("route")] = 1;
+    getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
     return result;
 }
@@ -1033,12 +1033,12 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             get_setuphold_from_tmg_db(id_SDPRAME, id_WCK, port, info.setup, info.hold);
         } else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
                    (sd1 == 0 && port == id_M1)) {
-            info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
+            info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
             info.clock_port = id_CLK;
             get_setuphold_from_tmg_db(id_SLOGICB, id_CLK, port, info.setup, info.hold);
 
         } else {
-            info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
+            info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
             info.clock_port = id_CLK;
             bool is_path = get_delay_from_tmg_db(id_SLOGICB, id_CLK, port, info.clockToQ);
             NPNR_ASSERT(is_path);
@@ -1070,8 +1070,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         } else {
             info.clock_port = half_clock;
         }
-        info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id("CLKBMUX") : id("CLKAMUX"), "CLK") ==
-                     "INV")
+        info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id_CLKBMUX : id_CLKAMUX, "CLK") == "INV")
                             ? FALLING_EDGE
                             : RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
@@ -1298,7 +1297,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     std::vector<std::pair<IdString, std::string>> ret;
     auto &wi = loc_info(wire)->wire_data[wire.index];
 
-    ret.push_back(std::make_pair(id("TILE_WIRE_ID"), stringf("%d", wi.tile_wire)));
+    ret.push_back(std::make_pair(id_TILE_WIRE_ID, stringf("%d", wi.tile_wire)));
 
     return ret;
 }
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 3cc6d252f1..a1f8aa1f04 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -150,7 +150,7 @@ void Arch::permute_luts()
 
     for (auto &cell : cells) {
         CellInfo *ci = cell.second.get();
-        if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id("MODE"), "LOGIC") == "LOGIC") {
+        if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id_MODE, "LOGIC") == "LOGIC") {
             proc_lut(ci, 0);
             proc_lut(ci, 1);
         }
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index de6c711ece..11a855ec48 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -723,10 +723,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
-        if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
+        if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) {
             int bank = ctx->get_pio_bel_bank(ci->bel);
-            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
-            std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
+            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
 
             if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
                 IOVoltage vcc = get_vccio(ioType_from_str(iotype));
@@ -835,71 +835,65 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
         }
         BelId bel = ci->bel;
-        if (ci->type == ctx->id("TRELLIS_SLICE")) {
+        if (ci->type == id_TRELLIS_SLICE) {
             pool<IdString> used_phys_pins;
             std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
             std::string slice = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
-            int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
+            int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
+            int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
             cc.tiles[tname].add_word(slice + ".K0.INIT",
                                      int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 0, lut0_init), 16));
             cc.tiles[tname].add_word(slice + ".K1.INIT",
                                      int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 1, lut1_init), 16));
-            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
-            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, ctx->id("REG1_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE",
-                                     str_or_default(ci->params, ctx->id("REG0_LSRMODE"), "LSR"));
-            cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE",
-                                     str_or_default(ci->params, ctx->id("REG1_LSRMODE"), "LSR"));
-            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
+            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE", str_or_default(ci->params, id_REG0_LSRMODE, "LSR"));
+            cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE", str_or_default(ci->params, id_REG1_LSRMODE, "LSR"));
+            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
 
             if (ci->sliceInfo.using_dff) {
                 NetInfo *lsrnet = nullptr;
-                if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
-                    lsrnet = ci->ports.at(ctx->id("LSR")).net;
+                if (ci->ports.find(id_LSR) != ci->ports.end() && ci->ports.at(id_LSR).net != nullptr)
+                    lsrnet = ci->ports.at(id_LSR).net;
                 if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR0.SRMODE",
-                                             str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-                    cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+                    cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+                    cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
                 }
                 if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR1.SRMODE",
-                                             str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-                    cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+                    cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+                    cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
                 }
 
                 NetInfo *clknet = nullptr;
-                if (ci->ports.find(ctx->id("CLK")) != ci->ports.end() && ci->ports.at(ctx->id("CLK")).net != nullptr)
-                    clknet = ci->ports.at(ctx->id("CLK")).net;
+                if (ci->ports.find(id_CLK) != ci->ports.end() && ci->ports.at(id_CLK).net != nullptr)
+                    clknet = ci->ports.at(id_CLK).net;
                 if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+                    cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
                 }
                 if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+                    cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
                 }
             }
 
-            if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "CCU2") {
+            if (str_or_default(ci->params, id_MODE, "LOGIC") == "CCU2") {
                 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
-                                         str_or_default(ci->params, ctx->id("CCU2_INJECT1_0"), "YES"));
+                                         str_or_default(ci->params, id_CCU2_INJECT1_0, "YES"));
                 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
-                                         str_or_default(ci->params, ctx->id("CCU2_INJECT1_1"), "YES"));
+                                         str_or_default(ci->params, id_CCU2_INJECT1_1, "YES"));
             } else {
                 // Don't interfere with cascade mux wiring
                 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0", "_NONE_");
                 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1", "_NONE_");
             }
 
-            if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "DPRAM" && slice == "SLICEA") {
-                cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, ctx->id("WREMUX"), "WRE"));
+            if (str_or_default(ci->params, id_MODE, "LOGIC") == "DPRAM" && slice == "SLICEA") {
+                cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
 
-                std::string wckmux = str_or_default(ci->params, ctx->id("WCKMUX"), "WCK");
+                std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
                 wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
                 cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
             }
@@ -912,10 +906,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             }
 
             // TODO: CLKMUX
-        } else if (ci->type == ctx->id("TRELLIS_IO")) {
+        } else if (ci->type == id_TRELLIS_IO) {
             std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
-            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
+            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
             std::string pio_tile = get_pio_tile(ctx, bel);
             std::string pic_tile = get_pic_tile(ctx, bel);
             cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
@@ -950,10 +944,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             } else if (is_referenced(ioType_from_str(iotype))) {
                 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
             }
-            if (dir != "INPUT" &&
-                (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
-                (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
-                 ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
+            if (dir != "INPUT" && (ci->ports.find(id_T) == ci->ports.end() || ci->ports.at(id_T).net == nullptr) &&
+                (ci->ports.find(id_IOLTO) == ci->ports.end() || ci->ports.at(id_IOLTO).net == nullptr)) {
                 // Tie tristate low if unconnected for outputs or bidir
                 WireId jpt_wire = ctx->get_wire_by_loc_basename(bel.location, fmt_str("JPADDT" << pio.back()));
                 PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
@@ -964,31 +956,29 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             }
             if ((dir == "INPUT" || dir == "BIDIR") && !is_differential(ioType_from_str(iotype)) &&
                 !is_referenced(ioType_from_str(iotype))) {
-                cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS",
-                                            str_or_default(ci->attrs, ctx->id("HYSTERESIS"), "ON"));
+                cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", str_or_default(ci->attrs, id_HYSTERESIS, "ON"));
             }
-            if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
-                cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
-            if (ci->attrs.count(ctx->id("PULLMODE")))
-                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
-            if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
-                cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
-                                            str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
-            if (ci->attrs.count(ctx->id("CLAMP")))
-                cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, ctx->id("CLAMP"), "OFF"));
-
-            if (ci->attrs.count(ctx->id("DRIVE"))) {
+            if (ci->attrs.count(id_SLEWRATE) && !is_referenced(ioType_from_str(iotype)))
+                cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, id_SLEWRATE, "SLOW"));
+            if (ci->attrs.count(id_PULLMODE))
+                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, id_PULLMODE, "NONE"));
+            if (ci->attrs.count(id_DIFFRESISTOR))
+                cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", str_or_default(ci->attrs, id_DIFFRESISTOR, "OFF"));
+            if (ci->attrs.count(id_CLAMP))
+                cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, id_CLAMP, "OFF"));
+
+            if (ci->attrs.count(id_DRIVE)) {
                 static bool drive_3v3_warning_done = false;
                 if (iotype == "LVCMOS33") {
-                    cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "8"));
+                    cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "8"));
                 } else if (iotype == "LVCMOS33D") {
                     if (bel.location.y == 0) {
                         // Pseudo differential top IO
                         NPNR_ASSERT(dir == "OUTPUT");
                         NPNR_ASSERT(pio == "PIOA");
                         std::string cpio_tile = get_comp_pio_tile(ctx, bel);
-                        cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
-                        cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
+                        cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+                        cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
                     } else {
                         std::string other;
                         if (pio == "PIOA")
@@ -997,9 +987,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                             other = "PIOD";
                         else
                             log_error("cannot set DRIVE on differential IO at location %s\n", pio.c_str());
-                        cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
-                        cc.tiles[pio_tile].add_enum(other + ".DRIVE",
-                                                    str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
+                        cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+                        cc.tiles[pio_tile].add_enum(other + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
                     }
                 } else {
                     if (!drive_3v3_warning_done)
@@ -1007,28 +996,28 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                     drive_3v3_warning_done = true;
                 }
             }
-            if (ci->attrs.count(ctx->id("TERMINATION"))) {
+            if (ci->attrs.count(id_TERMINATION)) {
                 auto vccio = get_vccio(ioType_from_str(iotype));
                 switch (vccio) {
                 case IOVoltage::VCC_1V8:
                     cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
-                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
                     break;
                 case IOVoltage::VCC_1V5:
                     cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
-                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
                     break;
                 case IOVoltage::VCC_1V35:
                     cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
-                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
                     break;
                 default:
                     log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
                               iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
                 }
             }
-            if (ci->attrs.count(ctx->id("OPENDRAIN"))) {
-                cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, ctx->id("OPENDRAIN"), "OFF"));
+            if (ci->attrs.count(id_OPENDRAIN)) {
+                cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
                 if (is_differential(ioType_from_str(iotype))) {
                     std::string other;
                     if (pio == "PIOA")
@@ -1037,25 +1026,24 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                         other = "PIOD";
                     else
                         log_error("cannot set OPENDRAIN on differential IO at location %s\n", pio.c_str());
-                    cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN",
-                                                str_or_default(ci->attrs, ctx->id("OPENDRAIN"), "OFF"));
+                    cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
                 }
             }
 
-            std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
+            std::string datamux_oddr = str_or_default(ci->params, id_DATAMUX_ODDR, "PADDO");
             if (datamux_oddr != "PADDO")
                 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
-            std::string datamux_oreg = str_or_default(ci->params, ctx->id("DATAMUX_OREG"), "PADDO");
+            std::string datamux_oreg = str_or_default(ci->params, id_DATAMUX_OREG, "PADDO");
             if (datamux_oreg != "PADDO")
                 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
-            std::string datamux_mddr = str_or_default(ci->params, ctx->id("DATAMUX_MDDR"), "PADDO");
+            std::string datamux_mddr = str_or_default(ci->params, id_DATAMUX_MDDR, "PADDO");
             if (datamux_mddr != "PADDO")
                 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
-            std::string trimux_tsreg = str_or_default(ci->params, ctx->id("TRIMUX_TSREG"), "PADDT");
+            std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT");
             if (trimux_tsreg != "PADDT")
                 cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
-        } else if (ci->type == ctx->id("DCCA")) {
-            const NetInfo *cen = get_net_or_empty(ci, ctx->id("CE"));
+        } else if (ci->type == id_DCCA) {
+            const NetInfo *cen = get_net_or_empty(ci, id_CE);
             if (cen != nullptr) {
                 std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get();
                 Loc loc = ctx->getBelLocation(bel);
@@ -1084,12 +1072,12 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
                 cc.tilegroups.push_back(tg);
             }
-        } else if (ci->type == ctx->id("DCSC")) {
+        } else if (ci->type == id_DCSC) {
             std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
             std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles);
             std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, ctx->id("DCSMODE"), "POS"));
-        } else if (ci->type == ctx->id("DP16KD")) {
+            cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
+        } else if (ci->type == id_DP16KD) {
             TileGroup tg;
             Loc loc = ctx->getBelLocation(ci->bel);
             tg.tiles = get_bram_tiles(ctx, ci->bel);
@@ -1098,32 +1086,27 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             if (ci->ramInfo.is_pdp) {
                 tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
                 tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R",
-                                   intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "36"));
+                                   intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
             } else {
                 tg.config.add_enum(ebr + ".MODE", "DP16KD");
-                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A",
-                                   intstr_or_default(ci->params, ctx->id("DATA_WIDTH_A"), "18"));
-                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B",
-                                   intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "18"));
-                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A",
-                                   str_or_default(ci->params, ctx->id("WRITEMODE_A"), "NORMAL"));
-                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B",
-                                   str_or_default(ci->params, ctx->id("WRITEMODE_B"), "NORMAL"));
+                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
+                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
+                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
+                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
             }
 
-            auto csd_a = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_A"), "0b000"), 3),
-                 csd_b = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_B"), "0b000"), 3);
+            auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
+                 csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
 
-            tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, ctx->id("REGMODE_A"), "NOREG"));
-            tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, ctx->id("REGMODE_B"), "NOREG"));
+            tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
+            tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
 
-            tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+            tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
             tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE",
-                               str_or_default(ci->params, ctx->id("ASYNC_RESET_RELEASE"), "SYNC"));
-            tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+                               str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
+            tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
 
-            tg.config.add_word(ebr + ".WID",
-                               int_to_bitvector(bit_reverse(int_or_default(ci->attrs, ctx->id("WID"), 0), 9), 9));
+            tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9));
 
             // Tie signals as appropriate
             for (auto port : ci->ports) {
@@ -1169,19 +1152,19 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 }
             }
 
-            tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, ctx->id("CLKAMUX"), "CLKA"));
-            tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, ctx->id("CLKBMUX"), "CLKB"));
+            tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, id_CLKAMUX, "CLKA"));
+            tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, id_CLKBMUX, "CLKB"));
 
-            tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, ctx->id("RSTAMUX"), "RSTA"));
-            tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, ctx->id("RSTBMUX"), "RSTB"));
+            tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
+            tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
             if (!ci->ramInfo.is_pdp) {
-                tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, ctx->id("WEAMUX"), "WEA"));
-                tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, ctx->id("WEBMUX"), "WEB"));
+                tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
+                tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
             }
-            tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, ctx->id("CEAMUX"), "CEA"));
-            tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, ctx->id("CEBMUX"), "CEB"));
-            tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, ctx->id("OCEAMUX"), "OCEA"));
-            tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, ctx->id("OCEBMUX"), "OCEB"));
+            tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
+            tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
+            tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, id_OCEAMUX, "OCEA"));
+            tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, id_OCEBMUX, "OCEB"));
 
             std::reverse(csd_a.begin(), csd_a.end());
             std::reverse(csd_b.begin(), csd_b.end());
@@ -1205,7 +1188,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                     }
                 }
             }
-            int wid = int_or_default(ci->attrs, ctx->id("WID"), 0);
+            int wid = int_or_default(ci->attrs, id_WID, 0);
             NPNR_ASSERT(!cc.bram_data.count(wid));
             cc.bram_data[wid] = init_data;
             cc.tilegroups.push_back(tg);
@@ -1214,33 +1197,30 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             Loc loc = ctx->getBelLocation(ci->bel);
             tg.tiles = get_dsp_tiles(ctx, ci->bel);
             std::string dsp = "MULT18_" + std::to_string(loc.z);
-            tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, ctx->id("REG_INPUTA_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, ctx->id("REG_INPUTA_CE"), "CE0"));
-            tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, ctx->id("REG_INPUTA_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, ctx->id("REG_INPUTB_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, ctx->id("REG_INPUTB_CE"), "CE0"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, ctx->id("REG_INPUTB_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, ctx->id("REG_INPUTC_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_CLK",
-                               str_or_default(ci->params, ctx->id("REG_PIPELINE_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, ctx->id("REG_PIPELINE_CE"), "CE0"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_RST",
-                               str_or_default(ci->params, ctx->id("REG_PIPELINE_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE"));
+            tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0"));
+            tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, id_REG_INPUTA_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, id_REG_INPUTB_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, id_REG_INPUTB_CE, "CE0"));
+            tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, id_REG_INPUTB_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, id_REG_INPUTC_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_PIPELINE_CLK", str_or_default(ci->params, id_REG_PIPELINE_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, id_REG_PIPELINE_CE, "CE0"));
+            tg.config.add_enum(dsp + ".REG_PIPELINE_RST", str_or_default(ci->params, id_REG_PIPELINE_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE"));
             if (dsp == "MULT18_0" || dsp == "MULT18_4")
-                tg.config.add_enum(dsp + ".REG_OUTPUT_RST",
-                                   str_or_default(ci->params, ctx->id("REG_OUTPUT_RST"), "RST0"));
+                tg.config.add_enum(dsp + ".REG_OUTPUT_RST", str_or_default(ci->params, id_REG_OUTPUT_RST, "RST0"));
 
-            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
-            tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, ctx->id("SOURCEB_MODE"), "B_SHIFT"));
-            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+            tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, id_SOURCEB_MODE, "B_SHIFT"));
+            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
 
             tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
-            if (str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE") == "NONE" && ci->cluster == ClusterId())
+            if (str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE") == "NONE" && ci->cluster == ClusterId())
                 tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
 
             if (loc.z < 4)
@@ -1264,67 +1244,53 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             Loc loc = ctx->getBelLocation(ci->bel);
             tg.tiles = get_dsp_tiles(ctx, ci->bel);
             std::string dsp = "ALU54_" + std::to_string(loc.z);
-            tg.config.add_enum(dsp + ".REG_INPUTC0_CLK",
-                               str_or_default(ci->params, ctx->id("REG_INPUTC0_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTC1_CLK",
-                               str_or_default(ci->params, ctx->id("REG_INPUTC1_CLK"), "NONE"));
+            tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CE"), "CE0"));
+                               str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_RST"), "RST0"));
+                               str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP1_0_CLK"), "NONE"));
+                               str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CLK"), "NONE"));
+                               str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP1_1_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CE"), "CE0"));
+                               str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0"));
             tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CE"), "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CE"), "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST",
-                               str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_RST"), "RST0"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK",
-                               str_or_default(ci->params, ctx->id("REG_OUTPUT1_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE"));
-            tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, ctx->id("MCPAT_SOURCE"), "STATIC"));
-            tg.config.add_enum(dsp + ".MASKPAT_SOURCE",
-                               str_or_default(ci->params, ctx->id("MASKPAT_SOURCE"), "STATIC"));
-            tg.config.add_word(dsp + ".MASK01",
-                               parse_init_str(str_or_default(ci->params, ctx->id("MASK01"), "0x00000000000000"), 56,
-                                              ci->name.c_str(ctx)));
-            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
-            tg.config.add_word(dsp + ".MCPAT",
-                               parse_init_str(str_or_default(ci->params, ctx->id("MCPAT"), "0x00000000000000"), 56,
-                                              ci->name.c_str(ctx)));
+                               str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK", str_or_default(ci->params, id_REG_OPCODEIN_1_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE", str_or_default(ci->params, id_REG_OPCODEIN_1_CE, "CE0"));
+            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST", str_or_default(ci->params, id_REG_OPCODEIN_1_RST, "RST0"));
+            tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK", str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK", str_or_default(ci->params, id_REG_OUTPUT1_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE"));
+            tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC"));
+            tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC"));
+            tg.config.add_word(
+                    dsp + ".MASK01",
+                    parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"), 56, ci->name.c_str(ctx)));
+            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+            tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"),
+                                                              56, ci->name.c_str(ctx)));
             tg.config.add_word(dsp + ".MASKPAT",
-                               parse_init_str(str_or_default(ci->params, ctx->id("MASKPAT"), "0x00000000000000"), 56,
-                                              ci->name.c_str(ctx)));
-            tg.config.add_word(dsp + ".RNDPAT",
-                               parse_init_str(str_or_default(ci->params, ctx->id("RNDPAT"), "0x00000000000000"), 56,
+                               parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"), 56,
                                               ci->name.c_str(ctx)));
-            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
-            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+            tg.config.add_word(
+                    dsp + ".RNDPAT",
+                    parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"), 56, ci->name.c_str(ctx)));
+            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
             tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
-                               str_or_default(ci->params, ctx->id("FORCE_ZERO_BARREL_SHIFT"), "DISABLED"));
-            tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, ctx->id("LEGACY"), "DISABLED"));
+                               str_or_default(ci->params, id_FORCE_ZERO_BARREL_SHIFT, "DISABLED"));
+            tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, id_LEGACY, "DISABLED"));
 
             tg.config.add_enum(dsp + ".MODE", "ALU54B");
 
@@ -1332,14 +1298,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
             else
                 tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
-            if (str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE") == "NONE") {
+            if (str_or_default(ci->params, id_REG_FLAG_CLK, "NONE") == "NONE") {
                 if (dsp == "ALU54_7") {
                     tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
                 } else if (dsp == "ALU54_3") {
                     tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
                 }
             }
-            if (str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE") == "NONE") {
+            if (str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE") == "NONE") {
                 if (dsp == "ALU54_7") {
                     tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
                 } else if (dsp == "ALU54_3") {
@@ -1354,14 +1320,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
             tg.config.add_enum("MODE", "EHXPLLL");
 
-            tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
-            tg.config.add_word("CLKFB_DIV",
-                               int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
+            tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKI_DIV, 1) - 1, 7));
+            tg.config.add_word("CLKFB_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKFB_DIV, 1) - 1, 7));
 
-            tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
-            tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
-            tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
-            tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
+            tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, id_CLKOP_ENABLE, "ENABLED"));
+            tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, id_CLKOS_ENABLE, "ENABLED"));
+            tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, id_CLKOS2_ENABLE, "ENABLED"));
+            tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, id_CLKOS3_ENABLE, "ENABLED"));
 
             for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
                 tg.config.add_word(out + "_DIV",
@@ -1372,73 +1337,59 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                                    int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
             }
 
-            tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
-            tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
+            tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP"));
+            tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, id_CLKOP_TRIM_POL, "RISING"));
 
-            tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
+            tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOP_TRIM_DELAY, "0"));
 
-            tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
+            tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, id_CLKOS_TRIM_POL, "RISING"));
 
-            tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
+            tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
 
-            tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
+            tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, id_OUTDIVIDER_MUXA,
                                                                  get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
+            tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, id_OUTDIVIDER_MUXB,
                                                                  get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
+            tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, id_OUTDIVIDER_MUXC,
                                                                  get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
+            tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, id_OUTDIVIDER_MUXD,
                                                                  get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
 
-            tg.config.add_word("PLL_LOCK_MODE",
-                               int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
-
-            tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
-            tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
-            tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
-            tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
-            tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
-            tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
-            tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
-
-            tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
-            tg.config.add_word("LPF_CAPACITOR",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
-            tg.config.add_word("LPF_RESISTOR",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
-            tg.config.add_word("ICP_CURRENT",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
+            tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
+
+            tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, id_STDBY_ENABLE, "DISABLED"));
+            tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, id_REFIN_RESET, "DISABLED"));
+            tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, id_SYNC_ENABLE, "DISABLED"));
+            tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, id_INT_LOCK_STICKY, "ENABLED"));
+            tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, id_DPHASE_SOURCE, "DISABLED"));
+            tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
+            tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, id_INTFB_WAKE, "DISABLED"));
+
+            tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, id_KVCO, 0), 3));
+            tg.config.add_word("LPF_CAPACITOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_CAPACITOR, 0), 2));
+            tg.config.add_word("LPF_RESISTOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_RESISTOR, 0), 7));
+            tg.config.add_word("ICP_CURRENT", int_to_bitvector(int_or_default(ci->attrs, id_ICP_CURRENT, 0), 5));
             tg.config.add_word("FREQ_LOCK_ACCURACY",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
+                               int_to_bitvector(int_or_default(ci->attrs, id_FREQ_LOCK_ACCURACY, 0), 2));
 
-            tg.config.add_word("MFG_GMC_GAIN",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
-            tg.config.add_word("MFG_GMC_TEST",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
-            tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
-            tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
+            tg.config.add_word("MFG_GMC_GAIN", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_GAIN, 0), 3));
+            tg.config.add_word("MFG_GMC_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_TEST, 14), 4));
+            tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG1_TEST, 0), 3));
+            tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG2_TEST, 0), 3));
 
             tg.config.add_word("MFG_FORCE_VFILTER",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
-            tg.config.add_word("MFG_ICP_TEST",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
-            tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
-            tg.config.add_word("MFG_FLOAT_ICP",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
-            tg.config.add_word("MFG_GMC_PRESET",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
-            tg.config.add_word("MFG_LF_PRESET",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
-            tg.config.add_word("MFG_GMC_RESET",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
-            tg.config.add_word("MFG_LF_RESET",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
-            tg.config.add_word("MFG_LF_RESGRND",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
-            tg.config.add_word("MFG_GMCREF_SEL",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
+                               int_to_bitvector(int_or_default(ci->attrs, id_MFG_FORCE_VFILTER, 0), 1));
+            tg.config.add_word("MFG_ICP_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_ICP_TEST, 0), 1));
+            tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_EN_UP, 0), 1));
+            tg.config.add_word("MFG_FLOAT_ICP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_FLOAT_ICP, 0), 1));
+            tg.config.add_word("MFG_GMC_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_PRESET, 0), 1));
+            tg.config.add_word("MFG_LF_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_PRESET, 0), 1));
+            tg.config.add_word("MFG_GMC_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_RESET, 0), 1));
+            tg.config.add_word("MFG_LF_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESET, 0), 1));
+            tg.config.add_word("MFG_LF_RESGRND", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESGRND, 0), 1));
+            tg.config.add_word("MFG_GMCREF_SEL", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMCREF_SEL, 0), 2));
             tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
-                               int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
+                               int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
 
             cc.tilegroups.push_back(tg);
         } else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) {
@@ -1466,23 +1417,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
         } else if (ci->type == id_EXTREFB) {
             TileGroup tg;
             tg.tiles = get_dcu_tiles(ctx, ci->bel);
-            tg.config.add_word(
-                    "EXTREF.REFCK_DCBIAS_EN",
-                    parse_config_str(get_or_default(ci->params, ctx->id("REFCK_DCBIAS_EN"), Property(0)), 1));
+            tg.config.add_word("EXTREF.REFCK_DCBIAS_EN",
+                               parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
             tg.config.add_word("EXTREF.REFCK_RTERM",
-                               parse_config_str(get_or_default(ci->params, ctx->id("REFCK_RTERM"), Property(0)), 1));
+                               parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
             tg.config.add_word("EXTREF.REFCK_PWDNB",
-                               parse_config_str(get_or_default(ci->params, ctx->id("REFCK_PWDNB"), Property(0)), 1));
+                               parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
             cc.tilegroups.push_back(tg);
         } else if (ci->type == id_PCSCLKDIV) {
             Loc loc = ctx->getBelLocation(ci->bel);
             std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
             cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
-                                     str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+                                     str_or_default(ci->params, id_GSR, "ENABLED"));
         } else if (ci->type == id_DTR) {
             cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
         } else if (ci->type == id_OSCG) {
-            int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+            int div = int_or_default(ci->params, id_DIV, 128);
             if (div == 128)
                 div = 127;
             cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
@@ -1494,22 +1444,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
             cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
         } else if (ci->type == id_GSR) {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
-                    "GSR.GSRMODE", str_or_default(ci->params, ctx->id("MODE"), "ACTIVE_LOW"));
-            cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum(
-                    "GSR.SYNCMODE", str_or_default(ci->params, ctx->id("SYNCMODE"), "ASYNC"));
+            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("GSR.GSRMODE",
+                                                                   str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
+            cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
+                                                                str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
         } else if (ci->type == id_JTAGG) {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
-                    "JTAG.ER1", str_or_default(ci->params, ctx->id("ER1"), "ENABLED"));
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
-                    "JTAG.ER2", str_or_default(ci->params, ctx->id("ER2"), "ENABLED"));
+            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
+                                                                   str_or_default(ci->params, id_ER1, "ENABLED"));
+            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
+                                                                   str_or_default(ci->params, id_ER2, "ENABLED"));
         } else if (ci->type == id_CLKDIVF) {
             Loc loc = ctx->getBelLocation(ci->bel);
             bool r = loc.x > 5;
             std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
             std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0"));
-            cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+            cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
+            cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
         } else if (ci->type == id_TRELLIS_ECLKBUF) {
         } else if (ci->type == id_DQSBUFM) {
             Loc loc = ctx->getBelLocation(ci->bel);
@@ -1521,13 +1471,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, pic + "0_DQS2"));
             tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, pic + "1_DQS3"));
             tg.config.add_enum("DQS.MODE", "DQSBUFM");
-            tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS"));
-            tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS"));
-            int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0);
-            if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS")
+            tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS"));
+            tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS"));
+            int li_del_value = int_or_default(ci->params, id_DQS_LI_DEL_VAL, 0);
+            if (str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS") == "MINUS")
                 li_del_value = (256 - li_del_value) & 0xFF;
-            int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0);
-            if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS")
+            int lo_del_value = int_or_default(ci->params, id_DQS_LO_DEL_VAL, 0);
+            if (str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS") == "MINUS")
                 lo_del_value = (256 - lo_del_value) & 0xFF;
             tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
             tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
@@ -1539,7 +1489,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                                        ? "YES"
                                        : "NO");
             tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
-            tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+            tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
             cc.tilegroups.push_back(tg);
         } else if (ci->type == id_ECLKSYNCB) {
             Loc loc = ctx->getBelLocation(ci->bel);
@@ -1565,9 +1515,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 tiletype += "A";
             std::string tile = ctx->get_tile_by_type(tiletype);
             cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
-            cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
-            cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY",
-                                    str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO"));
+            cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+            cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY", str_or_default(ci->params, id_FORCE_MAX_DELAY, "NO"));
         } else {
             NPNR_ASSERT_FALSE("unsupported cell type");
         }
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 18d9107f51..6d88af7529 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -47,129 +47,129 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         }
     };
 
-    if (type == ctx->id("TRELLIS_SLICE")) {
-        new_cell->params[ctx->id("MODE")] = std::string("LOGIC");
-        new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
-        new_cell->params[ctx->id("SRMODE")] = std::string("LSR_OVER_CE");
-        new_cell->params[ctx->id("CEMUX")] = std::string("1");
-        new_cell->params[ctx->id("CLKMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
-        new_cell->params[ctx->id("LUT0_INITVAL")] = Property(0, 16);
-        new_cell->params[ctx->id("LUT1_INITVAL")] = Property(0, 16);
-        new_cell->params[ctx->id("REG0_SD")] = std::string("0");
-        new_cell->params[ctx->id("REG1_SD")] = std::string("0");
-        new_cell->params[ctx->id("REG0_REGSET")] = std::string("RESET");
-        new_cell->params[ctx->id("REG1_REGSET")] = std::string("RESET");
-        new_cell->params[ctx->id("CCU2_INJECT1_0")] = std::string("NO");
-        new_cell->params[ctx->id("CCU2_INJECT1_1")] = std::string("NO");
-        new_cell->params[ctx->id("WREMUX")] = std::string("WRE");
-
-        new_cell->addInput(ctx->id("A0"));
-        new_cell->addInput(ctx->id("B0"));
-        new_cell->addInput(ctx->id("C0"));
-        new_cell->addInput(ctx->id("D0"));
-
-        new_cell->addInput(ctx->id("A1"));
-        new_cell->addInput(ctx->id("B1"));
-        new_cell->addInput(ctx->id("C1"));
-        new_cell->addInput(ctx->id("D1"));
-
-        new_cell->addInput(ctx->id("M0"));
-        new_cell->addInput(ctx->id("M1"));
-
-        new_cell->addInput(ctx->id("FCI"));
-        new_cell->addInput(ctx->id("FXA"));
-        new_cell->addInput(ctx->id("FXB"));
-
-        new_cell->addInput(ctx->id("CLK"));
-        new_cell->addInput(ctx->id("LSR"));
-        new_cell->addInput(ctx->id("CE"));
-
-        new_cell->addInput(ctx->id("DI0"));
-        new_cell->addInput(ctx->id("DI1"));
-
-        new_cell->addInput(ctx->id("WD0"));
-        new_cell->addInput(ctx->id("WD1"));
-        new_cell->addInput(ctx->id("WAD0"));
-        new_cell->addInput(ctx->id("WAD1"));
-        new_cell->addInput(ctx->id("WAD2"));
-        new_cell->addInput(ctx->id("WAD3"));
-        new_cell->addInput(ctx->id("WRE"));
-        new_cell->addInput(ctx->id("WCK"));
-
-        new_cell->addOutput(ctx->id("F0"));
-        new_cell->addOutput(ctx->id("Q0"));
-        new_cell->addOutput(ctx->id("F1"));
-        new_cell->addOutput(ctx->id("Q1"));
-
-        new_cell->addOutput(ctx->id("FCO"));
-        new_cell->addOutput(ctx->id("OFX0"));
-        new_cell->addOutput(ctx->id("OFX1"));
-
-        new_cell->addOutput(ctx->id("WDO0"));
-        new_cell->addOutput(ctx->id("WDO1"));
-        new_cell->addOutput(ctx->id("WDO2"));
-        new_cell->addOutput(ctx->id("WDO3"));
-        new_cell->addOutput(ctx->id("WADO0"));
-        new_cell->addOutput(ctx->id("WADO1"));
-        new_cell->addOutput(ctx->id("WADO2"));
-        new_cell->addOutput(ctx->id("WADO3"));
-    } else if (type == ctx->id("TRELLIS_IO")) {
-        new_cell->params[ctx->id("DIR")] = std::string("INPUT");
-        new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
-        new_cell->params[ctx->id("DATAMUX_ODDR")] = std::string("PADDO");
-        new_cell->params[ctx->id("DATAMUX_MDDR")] = std::string("PADDO");
-
-        new_cell->addInout(ctx->id("B"));
-        new_cell->addInput(ctx->id("I"));
-        new_cell->addInput(ctx->id("T"));
-        new_cell->addOutput(ctx->id("O"));
-
-        new_cell->addInput(ctx->id("IOLDO"));
-        new_cell->addInput(ctx->id("IOLTO"));
-
-    } else if (type == ctx->id("LUT4")) {
-        new_cell->params[ctx->id("INIT")] = Property(0, 16);
-
-        new_cell->addInput(ctx->id("A"));
-        new_cell->addInput(ctx->id("B"));
-        new_cell->addInput(ctx->id("C"));
-        new_cell->addInput(ctx->id("D"));
-        new_cell->addOutput(ctx->id("Z"));
-    } else if (type == ctx->id("CCU2C")) {
-        new_cell->params[ctx->id("INIT0")] = Property(0, 16);
-        new_cell->params[ctx->id("INIT1")] = Property(0, 16);
-        new_cell->params[ctx->id("INJECT1_0")] = std::string("YES");
-        new_cell->params[ctx->id("INJECT1_1")] = std::string("YES");
-
-        new_cell->addInput(ctx->id("CIN"));
-
-        new_cell->addInput(ctx->id("A0"));
-        new_cell->addInput(ctx->id("B0"));
-        new_cell->addInput(ctx->id("C0"));
-        new_cell->addInput(ctx->id("D0"));
-
-        new_cell->addInput(ctx->id("A1"));
-        new_cell->addInput(ctx->id("B1"));
-        new_cell->addInput(ctx->id("C1"));
-        new_cell->addInput(ctx->id("D1"));
-
-        new_cell->addOutput(ctx->id("S0"));
-        new_cell->addOutput(ctx->id("S1"));
-        new_cell->addOutput(ctx->id("COUT"));
-
-    } else if (type == ctx->id("DCCA")) {
-        new_cell->addInput(ctx->id("CLKI"));
-        new_cell->addOutput(ctx->id("CLKO"));
-        new_cell->addInput(ctx->id("CE"));
+    if (type == id_TRELLIS_SLICE) {
+        new_cell->params[id_MODE] = std::string("LOGIC");
+        new_cell->params[id_GSR] = std::string("DISABLED");
+        new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
+        new_cell->params[id_CEMUX] = std::string("1");
+        new_cell->params[id_CLKMUX] = std::string("CLK");
+        new_cell->params[id_LSRMUX] = std::string("LSR");
+        new_cell->params[id_LUT0_INITVAL] = Property(0, 16);
+        new_cell->params[id_LUT1_INITVAL] = Property(0, 16);
+        new_cell->params[id_REG0_SD] = std::string("0");
+        new_cell->params[id_REG1_SD] = std::string("0");
+        new_cell->params[id_REG0_REGSET] = std::string("RESET");
+        new_cell->params[id_REG1_REGSET] = std::string("RESET");
+        new_cell->params[id_CCU2_INJECT1_0] = std::string("NO");
+        new_cell->params[id_CCU2_INJECT1_1] = std::string("NO");
+        new_cell->params[id_WREMUX] = std::string("WRE");
+
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addInput(id_M0);
+        new_cell->addInput(id_M1);
+
+        new_cell->addInput(id_FCI);
+        new_cell->addInput(id_FXA);
+        new_cell->addInput(id_FXB);
+
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_LSR);
+        new_cell->addInput(id_CE);
+
+        new_cell->addInput(id_DI0);
+        new_cell->addInput(id_DI1);
+
+        new_cell->addInput(id_WD0);
+        new_cell->addInput(id_WD1);
+        new_cell->addInput(id_WAD0);
+        new_cell->addInput(id_WAD1);
+        new_cell->addInput(id_WAD2);
+        new_cell->addInput(id_WAD3);
+        new_cell->addInput(id_WRE);
+        new_cell->addInput(id_WCK);
+
+        new_cell->addOutput(id_F0);
+        new_cell->addOutput(id_Q0);
+        new_cell->addOutput(id_F1);
+        new_cell->addOutput(id_Q1);
+
+        new_cell->addOutput(id_FCO);
+        new_cell->addOutput(id_OFX0);
+        new_cell->addOutput(id_OFX1);
+
+        new_cell->addOutput(id_WDO0);
+        new_cell->addOutput(id_WDO1);
+        new_cell->addOutput(id_WDO2);
+        new_cell->addOutput(id_WDO3);
+        new_cell->addOutput(id_WADO0);
+        new_cell->addOutput(id_WADO1);
+        new_cell->addOutput(id_WADO2);
+        new_cell->addOutput(id_WADO3);
+    } else if (type == id_TRELLIS_IO) {
+        new_cell->params[id_DIR] = std::string("INPUT");
+        new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
+        new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO");
+        new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO");
+
+        new_cell->addInout(id_B);
+        new_cell->addInput(id_I);
+        new_cell->addInput(id_T);
+        new_cell->addOutput(id_O);
+
+        new_cell->addInput(id_IOLDO);
+        new_cell->addInput(id_IOLTO);
+
+    } else if (type == id_LUT4) {
+        new_cell->params[id_INIT] = Property(0, 16);
+
+        new_cell->addInput(id_A);
+        new_cell->addInput(id_B);
+        new_cell->addInput(id_C);
+        new_cell->addInput(id_D);
+        new_cell->addOutput(id_Z);
+    } else if (type == id_CCU2C) {
+        new_cell->params[id_INIT0] = Property(0, 16);
+        new_cell->params[id_INIT1] = Property(0, 16);
+        new_cell->params[id_INJECT1_0] = std::string("YES");
+        new_cell->params[id_INJECT1_1] = std::string("YES");
+
+        new_cell->addInput(id_CIN);
+
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addOutput(id_S0);
+        new_cell->addOutput(id_S1);
+        new_cell->addOutput(id_COUT);
+
+    } else if (type == id_DCCA) {
+        new_cell->addInput(id_CLKI);
+        new_cell->addOutput(id_CLKO);
+        new_cell->addInput(id_CE);
     } else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
-        new_cell->params[ctx->id("MODE")] = std::string("NONE");
-        new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
-        new_cell->params[ctx->id("CLKIMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("CLKOMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("LSRIMUX")] = std::string("0");
-        new_cell->params[ctx->id("LSROMUX")] = std::string("0");
-        new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
+        new_cell->params[id_MODE] = std::string("NONE");
+        new_cell->params[id_GSR] = std::string("DISABLED");
+        new_cell->params[id_CLKIMUX] = std::string("CLK");
+        new_cell->params[id_CLKOMUX] = std::string("CLK");
+        new_cell->params[id_LSRIMUX] = std::string("0");
+        new_cell->params[id_LSROMUX] = std::string("0");
+        new_cell->params[id_LSRMUX] = std::string("LSR");
 
         new_cell->params[ctx->id("DELAY.OUTDEL")] = std::string("DISABLED");
         new_cell->params[ctx->id("DELAY.DEL_VALUE")] = Property(0, 7);
@@ -183,7 +183,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
             new_cell->params[ctx->id("MODDRX.MODE")] = std::string("NONE");
             new_cell->params[ctx->id("MTDDRX.MODE")] = std::string("NONE");
 
-            new_cell->params[ctx->id("IOLTOMUX")] = std::string("NONE");
+            new_cell->params[id_IOLTOMUX] = std::string("NONE");
             new_cell->params[ctx->id("MTDDRX.DQSW_INVERT")] = std::string("DISABLED");
             new_cell->params[ctx->id("MTDDRX.REGSET")] = std::string("RESET");
 
@@ -192,8 +192,8 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         // Just copy ports from the Bel
         copy_bel_ports();
     } else if (type == id_TRELLIS_ECLKBUF) {
-        new_cell->addInput(ctx->id("ECLKI"));
-        new_cell->addOutput(ctx->id("ECLKO"));
+        new_cell->addInput(id_ECLKI);
+        new_cell->addOutput(id_ECLKO);
     } else {
         log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
     }
@@ -225,38 +225,38 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ff->hierpath;
-    bool has_ff = lc->ports.at(ctx->id("Q0")).net != nullptr || lc->ports.at(ctx->id("Q1")).net != nullptr;
+    bool has_ff = lc->ports.at(id_Q0).net != nullptr || lc->ports.at(id_Q1).net != nullptr;
     std::string reg = "REG" + std::to_string(index);
-    set_param_safe(has_ff, lc, ctx->id("SRMODE"), str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-    set_param_safe(has_ff, lc, ctx->id("GSR"), str_or_default(ff->params, ctx->id("GSR"), "DISABLED"));
-    set_param_safe(has_ff, lc, ctx->id("CEMUX"), str_or_default(ff->params, ctx->id("CEMUX"), "1"));
-    set_param_safe(has_ff, lc, ctx->id("LSRMUX"), str_or_default(ff->params, ctx->id("LSRMUX"), "LSR"));
-    set_param_safe(has_ff, lc, ctx->id("CLKMUX"), str_or_default(ff->params, ctx->id("CLKMUX"), "CLK"));
+    set_param_safe(has_ff, lc, id_SRMODE, str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE"));
+    set_param_safe(has_ff, lc, id_GSR, str_or_default(ff->params, id_GSR, "DISABLED"));
+    set_param_safe(has_ff, lc, id_CEMUX, str_or_default(ff->params, id_CEMUX, "1"));
+    set_param_safe(has_ff, lc, id_LSRMUX, str_or_default(ff->params, id_LSRMUX, "LSR"));
+    set_param_safe(has_ff, lc, id_CLKMUX, str_or_default(ff->params, id_CLKMUX, "CLK"));
 
     lc->params[ctx->id(reg + "_SD")] = std::string(driven_by_lut ? "1" : "0");
-    lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, ctx->id("REGSET"), "RESET");
-    lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, ctx->id("LSRMODE"), "LSR");
-    replace_port_safe(has_ff, ff, ctx->id("CLK"), lc, ctx->id("CLK"));
-    if (ff->ports.find(ctx->id("LSR")) != ff->ports.end())
-        replace_port_safe(has_ff, ff, ctx->id("LSR"), lc, ctx->id("LSR"));
-    if (ff->ports.find(ctx->id("CE")) != ff->ports.end())
-        replace_port_safe(has_ff, ff, ctx->id("CE"), lc, ctx->id("CE"));
-
-    replace_port(ff, ctx->id("Q"), lc, ctx->id("Q" + std::to_string(index)));
-    if (get_net_or_empty(ff, ctx->id("M")) != nullptr) {
+    lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, id_REGSET, "RESET");
+    lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, id_LSRMODE, "LSR");
+    replace_port_safe(has_ff, ff, id_CLK, lc, id_CLK);
+    if (ff->ports.find(id_LSR) != ff->ports.end())
+        replace_port_safe(has_ff, ff, id_LSR, lc, id_LSR);
+    if (ff->ports.find(id_CE) != ff->ports.end())
+        replace_port_safe(has_ff, ff, id_CE, lc, id_CE);
+
+    replace_port(ff, id_Q, lc, ctx->id("Q" + std::to_string(index)));
+    if (get_net_or_empty(ff, id_M) != nullptr) {
         // PRLD FFs that use both M and DI
         NPNR_ASSERT(!driven_by_lut);
         // As M is used; must route DI through a new LUT
         lc->params[ctx->id(reg + "_SD")] = std::string("1");
         lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16);
-        replace_port(ff, ctx->id("DI"), lc, ctx->id("D" + std::to_string(index)));
-        replace_port(ff, ctx->id("M"), lc, ctx->id("M" + std::to_string(index)));
+        replace_port(ff, id_DI, lc, ctx->id("D" + std::to_string(index)));
+        replace_port(ff, id_M, lc, ctx->id("M" + std::to_string(index)));
         connect_ports(ctx, lc, ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
     } else {
         if (driven_by_lut) {
-            replace_port(ff, ctx->id("DI"), lc, ctx->id("DI" + std::to_string(index)));
+            replace_port(ff, id_DI, lc, ctx->id("DI" + std::to_string(index)));
         } else {
-            replace_port(ff, ctx->id("DI"), lc, ctx->id("M" + std::to_string(index)));
+            replace_port(ff, id_DI, lc, ctx->id("M" + std::to_string(index)));
         }
     }
 }
@@ -266,62 +266,62 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
     if (lc->hierpath == IdString())
         lc->hierpath = lut->hierpath;
     lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
-            get_or_default(lut->params, ctx->id("INIT"), Property(0, 16));
-    replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index)));
-    replace_port(lut, ctx->id("B"), lc, ctx->id("B" + std::to_string(index)));
-    replace_port(lut, ctx->id("C"), lc, ctx->id("C" + std::to_string(index)));
-    replace_port(lut, ctx->id("D"), lc, ctx->id("D" + std::to_string(index)));
-    replace_port(lut, ctx->id("Z"), lc, ctx->id("F" + std::to_string(index)));
+            get_or_default(lut->params, id_INIT, Property(0, 16));
+    replace_port(lut, id_A, lc, ctx->id("A" + std::to_string(index)));
+    replace_port(lut, id_B, lc, ctx->id("B" + std::to_string(index)));
+    replace_port(lut, id_C, lc, ctx->id("C" + std::to_string(index)));
+    replace_port(lut, id_D, lc, ctx->id("D" + std::to_string(index)));
+    replace_port(lut, id_Z, lc, ctx->id("F" + std::to_string(index)));
 }
 
 void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ccu->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("CCU2");
-    lc->params[ctx->id("LUT0_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT0"), Property(0, 16));
-    lc->params[ctx->id("LUT1_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT1"), Property(0, 16));
+    lc->params[id_MODE] = std::string("CCU2");
+    lc->params[id_LUT0_INITVAL] = get_or_default(ccu->params, id_INIT0, Property(0, 16));
+    lc->params[id_LUT1_INITVAL] = get_or_default(ccu->params, id_INIT1, Property(0, 16));
 
-    lc->params[ctx->id("CCU2_INJECT1_0")] = str_or_default(ccu->params, ctx->id("INJECT1_0"), "YES");
-    lc->params[ctx->id("CCU2_INJECT1_1")] = str_or_default(ccu->params, ctx->id("INJECT1_1"), "YES");
+    lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES");
+    lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES");
 
-    replace_port(ccu, ctx->id("CIN"), lc, ctx->id("FCI"));
+    replace_port(ccu, id_CIN, lc, id_FCI);
 
-    replace_port(ccu, ctx->id("A0"), lc, ctx->id("A0"));
-    replace_port(ccu, ctx->id("B0"), lc, ctx->id("B0"));
-    replace_port(ccu, ctx->id("C0"), lc, ctx->id("C0"));
-    replace_port(ccu, ctx->id("D0"), lc, ctx->id("D0"));
+    replace_port(ccu, id_A0, lc, id_A0);
+    replace_port(ccu, id_B0, lc, id_B0);
+    replace_port(ccu, id_C0, lc, id_C0);
+    replace_port(ccu, id_D0, lc, id_D0);
 
-    replace_port(ccu, ctx->id("A1"), lc, ctx->id("A1"));
-    replace_port(ccu, ctx->id("B1"), lc, ctx->id("B1"));
-    replace_port(ccu, ctx->id("C1"), lc, ctx->id("C1"));
-    replace_port(ccu, ctx->id("D1"), lc, ctx->id("D1"));
+    replace_port(ccu, id_A1, lc, id_A1);
+    replace_port(ccu, id_B1, lc, id_B1);
+    replace_port(ccu, id_C1, lc, id_C1);
+    replace_port(ccu, id_D1, lc, id_D1);
 
-    replace_port(ccu, ctx->id("S0"), lc, ctx->id("F0"));
-    replace_port(ccu, ctx->id("S1"), lc, ctx->id("F1"));
+    replace_port(ccu, id_S0, lc, id_F0);
+    replace_port(ccu, id_S1, lc, id_F1);
 
-    replace_port(ccu, ctx->id("COUT"), lc, ctx->id("FCO"));
+    replace_port(ccu, id_COUT, lc, id_FCO);
 }
 
 void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ram->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("RAMW");
-    replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0"));
-    replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0"));
-    replace_port(ram, ctx->id("WAD[2]"), lc, ctx->id("C0"));
-    replace_port(ram, ctx->id("WAD[3]"), lc, ctx->id("A0"));
-
-    replace_port(ram, ctx->id("DI[0]"), lc, ctx->id("C1"));
-    replace_port(ram, ctx->id("DI[1]"), lc, ctx->id("A1"));
-    replace_port(ram, ctx->id("DI[2]"), lc, ctx->id("D1"));
-    replace_port(ram, ctx->id("DI[3]"), lc, ctx->id("B1"));
+    lc->params[id_MODE] = std::string("RAMW");
+    replace_port(ram, ctx->id("WAD[0]"), lc, id_D0);
+    replace_port(ram, ctx->id("WAD[1]"), lc, id_B0);
+    replace_port(ram, ctx->id("WAD[2]"), lc, id_C0);
+    replace_port(ram, ctx->id("WAD[3]"), lc, id_A0);
+
+    replace_port(ram, ctx->id("DI[0]"), lc, id_C1);
+    replace_port(ram, ctx->id("DI[1]"), lc, id_A1);
+    replace_port(ram, ctx->id("DI[2]"), lc, id_D1);
+    replace_port(ram, ctx->id("DI[3]"), lc, id_B1);
 }
 
 static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
 {
-    auto init_prop = get_or_default(ram->params, ctx->id("INITVAL"), Property(0, 64));
+    auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
     NPNR_ASSERT(!init_prop.is_string);
     const std::string &idata = init_prop.str;
     NPNR_ASSERT(idata.length() == 64);
@@ -340,9 +340,9 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ram->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("DPRAM");
-    lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE");
-    lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK");
+    lc->params[id_MODE] = std::string("DPRAM");
+    lc->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
+    lc->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
 
     unsigned permuted_init0 = 0, permuted_init1 = 0;
     unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1);
@@ -363,30 +363,30 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
             permuted_init1 |= (1 << i);
     }
 
-    lc->params[ctx->id("LUT0_INITVAL")] = Property(permuted_init0, 16);
-    lc->params[ctx->id("LUT1_INITVAL")] = Property(permuted_init1, 16);
+    lc->params[id_LUT0_INITVAL] = Property(permuted_init0, 16);
+    lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16);
 
     if (ram->ports.count(ctx->id("RAD[0]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D1);
     }
     if (ram->ports.count(ctx->id("RAD[1]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B1);
     }
     if (ram->ports.count(ctx->id("RAD[2]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C1);
     }
     if (ram->ports.count(ctx->id("RAD[3]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A1);
     }
 
-    if (ram->ports.count(ctx->id("WRE")))
-        connect_port(ctx, ram->ports.at(ctx->id("WRE")).net, lc, ctx->id("WRE"));
-    if (ram->ports.count(ctx->id("WCK")))
-        connect_port(ctx, ram->ports.at(ctx->id("WCK")).net, lc, ctx->id("WCK"));
+    if (ram->ports.count(id_WRE))
+        connect_port(ctx, ram->ports.at(id_WRE).net, lc, id_WRE);
+    if (ram->ports.count(id_WCK))
+        connect_port(ctx, ram->ports.at(id_WCK).net, lc, id_WCK);
 
     connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0);
     connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1);
@@ -415,26 +415,26 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
                 pool<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
-        trio->params[ctx->id("DIR")] = std::string("INPUT");
-        replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+        trio->params[id_DIR] = std::string("INPUT");
+        replace_port(nxio, id_O, trio, id_O);
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
-        trio->params[ctx->id("DIR")] = std::string("OUTPUT");
-        replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+        trio->params[id_DIR] = std::string("OUTPUT");
+        replace_port(nxio, id_I, trio, id_I);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+        NetInfo *i = get_net_or_empty(nxio, id_I);
         if (i == nullptr || i->driver.cell == nullptr)
-            trio->params[ctx->id("DIR")] = std::string("INPUT");
+            trio->params[id_DIR] = std::string("INPUT");
         else {
             log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
-            trio->params[ctx->id("DIR")] = std::string("BIDIR");
+            trio->params[id_DIR] = std::string("BIDIR");
         }
-        replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
-        replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+        replace_port(nxio, id_I, trio, id_I);
+        replace_port(nxio, id_O, trio, id_O);
     } else {
         NPNR_ASSERT(false);
     }
-    NetInfo *donet = trio->ports.at(ctx->id("I")).net, *dinet = trio->ports.at(ctx->id("O")).net;
+    NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net;
 
     // Rename I/O nets to avoid conflicts
     if (donet != nullptr && donet->name == nxio->name)
@@ -458,20 +458,20 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         ctx->net_aliases.erase(tn_netname);
         NetInfo *toplevel_net = ctx->createNet(tn_netname);
         toplevel_net->name = tn_netname;
-        connect_port(ctx, toplevel_net, trio, ctx->id("B"));
+        connect_port(ctx, toplevel_net, trio, id_B);
         ctx->ports[nxio->name].net = toplevel_net;
     }
 
     CellInfo *tbuf = net_driven_by(
             ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
-            ctx->id("Y"));
+            id_Y);
     if (tbuf) {
-        replace_port(tbuf, ctx->id("A"), trio, ctx->id("I"));
+        replace_port(tbuf, id_A, trio, id_I);
         // Need to invert E to form T
-        std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T");
-        replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A"));
-        inv_lut->params[ctx->id("INIT")] = Property(21845, 16);
-        connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T"));
+        std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
+        replace_port(tbuf, id_E, inv_lut.get(), id_A);
+        inv_lut->params[id_INIT] = Property(21845, 16);
+        connect_ports(ctx, inv_lut.get(), id_Z, trio, id_T);
         created_cells.push_back(std::move(inv_lut));
 
         if (donet->users.size() > 1) {
diff --git a/ecp5/cells.h b/ecp5/cells.h
index c1165ddcf8..8f0a8cbf70 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -30,37 +30,36 @@ NEXTPNR_NAMESPACE_BEGIN
 std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT4"); }
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
 
 // Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_FF"); }
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
 
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("CCU2C"); }
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_SLICE"); }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
 
-inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_IO"); }
+inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
-inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_DPR16X4"); }
+inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
 
-inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("PFUMX"); }
+inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_PFUMX; }
 
-inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("L6MUX21"); }
+inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_L6MUX21; }
 
 inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("IDDRX1F") || cell->type == ctx->id("IDDRX2F") || cell->type == ctx->id("IDDR71B") ||
-           cell->type == ctx->id("IDDRX2DQA") ||
-           (cell->type == ctx->id("TRELLIS_FF") && bool_or_default(cell->attrs, ctx->id("syn_useioff")) &&
-            (str_or_default(cell->attrs, ctx->id("ioff_dir"), "") != "output"));
+    return cell->type == id_IDDRX1F || cell->type == id_IDDRX2F || cell->type == id_IDDR71B ||
+           cell->type == id_IDDRX2DQA ||
+           (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
+            (str_or_default(cell->attrs, id_ioff_dir, "") != "output"));
 }
 inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("ODDRX1F") || cell->type == ctx->id("ODDRX2F") || cell->type == ctx->id("ODDR71B") ||
-           cell->type == ctx->id("ODDRX2DQA") || cell->type == ctx->id("ODDRX2DQSB") ||
-           cell->type == ctx->id("OSHX2A") ||
-           (cell->type == ctx->id("TRELLIS_FF") && bool_or_default(cell->attrs, ctx->id("syn_useioff")) &&
-            (str_or_default(cell->attrs, ctx->id("ioff_dir"), "") != "input"));
+    return cell->type == id_ODDRX1F || cell->type == id_ODDRX2F || cell->type == id_ODDR71B ||
+           cell->type == id_ODDRX2DQA || cell->type == id_ODDRX2DQSB || cell->type == id_OSHX2A ||
+           (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
+            (str_or_default(cell->attrs, id_ioff_dir, "") != "input"));
 }
 
 void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 335f822a8a..760e162305 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1341,3 +1341,513 @@ X(IOLOGIC_MODE_TSREG)
 X(DCSC)
 X(DCSOUT)
 X(MODESEL)
+
+X(ALUT)
+X(ASYNC_RESET_RELEASE)
+X(BEL)
+X(BLUT)
+X(C)
+X(CCU2C)
+X(CCU2_INJECT1_0)
+X(CCU2_INJECT1_1)
+X(CEAMUX)
+X(CEBMUX)
+X(CEIMUX)
+X(CEMUX)
+X(CEOMUX)
+X(CER)
+X(CEW)
+X(CH0_AUTO_CALIB_EN)
+X(CH0_AUTO_FACQ_EN)
+X(CH0_BAND_THRESHOLD)
+X(CH0_CALIB_CK_MODE)
+X(CH0_CC_MATCH_1)
+X(CH0_CC_MATCH_2)
+X(CH0_CC_MATCH_3)
+X(CH0_CC_MATCH_4)
+X(CH0_CDR_CNT4SEL)
+X(CH0_CDR_CNT8SEL)
+X(CH0_CTC_BYPASS)
+X(CH0_DCOATDCFG)
+X(CH0_DCOATDDLY)
+X(CH0_DCOBYPSATD)
+X(CH0_DCOCALDIV)
+X(CH0_DCOCTLGI)
+X(CH0_DCODISBDAVOID)
+X(CH0_DCOFLTDAC)
+X(CH0_DCOFTNRG)
+X(CH0_DCOIOSTUNE)
+X(CH0_DCOITUNE)
+X(CH0_DCOITUNE4LSB)
+X(CH0_DCOIUPDNX2)
+X(CH0_DCONUOFLSB)
+X(CH0_DCOSCALEI)
+X(CH0_DCOSTARTVAL)
+X(CH0_DCOSTEP)
+X(CH0_DEC_BYPASS)
+X(CH0_ENABLE_CG_ALIGN)
+X(CH0_ENC_BYPASS)
+X(CH0_FF_RX_F_CLK_DIS)
+X(CH0_FF_RX_H_CLK_EN)
+X(CH0_FF_TX_F_CLK_DIS)
+X(CH0_FF_TX_H_CLK_EN)
+X(CH0_GE_AN_ENABLE)
+X(CH0_INVERT_RX)
+X(CH0_INVERT_TX)
+X(CH0_LDR_CORE2TX_SEL)
+X(CH0_LDR_RX2CORE_SEL)
+X(CH0_LEQ_OFFSET_SEL)
+X(CH0_LEQ_OFFSET_TRIM)
+X(CH0_LSM_DISABLE)
+X(CH0_MATCH_2_ENABLE)
+X(CH0_MATCH_4_ENABLE)
+X(CH0_MIN_IPG_CNT)
+X(CH0_PCIE_EI_EN)
+X(CH0_PCIE_MODE)
+X(CH0_PCS_DET_TIME_SEL)
+X(CH0_PDEN_SEL)
+X(CH0_PRBS_ENABLE)
+X(CH0_PRBS_LOCK)
+X(CH0_PRBS_SELECTION)
+X(CH0_RATE_MODE_RX)
+X(CH0_RATE_MODE_TX)
+X(CH0_RCV_DCC_EN)
+X(CH0_REG_BAND_OFFSET)
+X(CH0_REG_BAND_SEL)
+X(CH0_REG_IDAC_EN)
+X(CH0_REG_IDAC_SEL)
+X(CH0_REQ_EN)
+X(CH0_REQ_LVL_SET)
+X(CH0_RIO_MODE)
+X(CH0_RLOS_SEL)
+X(CH0_RPWDNB)
+X(CH0_RTERM_RX)
+X(CH0_RTERM_TX)
+X(CH0_RXIN_CM)
+X(CH0_RXTERM_CM)
+X(CH0_RX_DCO_CK_DIV)
+X(CH0_RX_DIV11_SEL)
+X(CH0_RX_GEAR_BYPASS)
+X(CH0_RX_GEAR_MODE)
+X(CH0_RX_LOS_CEQ)
+X(CH0_RX_LOS_EN)
+X(CH0_RX_LOS_HYST_EN)
+X(CH0_RX_LOS_LVL)
+X(CH0_RX_RATE_SEL)
+X(CH0_RX_SB_BYPASS)
+X(CH0_SB_BYPASS)
+X(CH0_SEL_SD_RX_CLK)
+X(CH0_TDRV_DAT_SEL)
+X(CH0_TDRV_POST_EN)
+X(CH0_TDRV_PRE_EN)
+X(CH0_TDRV_SLICE0_CUR)
+X(CH0_TDRV_SLICE0_SEL)
+X(CH0_TDRV_SLICE1_CUR)
+X(CH0_TDRV_SLICE1_SEL)
+X(CH0_TDRV_SLICE2_CUR)
+X(CH0_TDRV_SLICE2_SEL)
+X(CH0_TDRV_SLICE3_CUR)
+X(CH0_TDRV_SLICE3_SEL)
+X(CH0_TDRV_SLICE4_CUR)
+X(CH0_TDRV_SLICE4_SEL)
+X(CH0_TDRV_SLICE5_CUR)
+X(CH0_TDRV_SLICE5_SEL)
+X(CH0_TPWDNB)
+X(CH0_TX_CM_SEL)
+X(CH0_TX_DIV11_SEL)
+X(CH0_TX_GEAR_BYPASS)
+X(CH0_TX_GEAR_MODE)
+X(CH0_TX_POST_SIGN)
+X(CH0_TX_PRE_SIGN)
+X(CH0_UC_MODE)
+X(CH0_UDF_COMMA_A)
+X(CH0_UDF_COMMA_B)
+X(CH0_UDF_COMMA_MASK)
+X(CH0_WA_BYPASS)
+X(CH0_WA_MODE)
+X(CH1_AUTO_CALIB_EN)
+X(CH1_AUTO_FACQ_EN)
+X(CH1_BAND_THRESHOLD)
+X(CH1_CALIB_CK_MODE)
+X(CH1_CC_MATCH_1)
+X(CH1_CC_MATCH_2)
+X(CH1_CC_MATCH_3)
+X(CH1_CC_MATCH_4)
+X(CH1_CDR_CNT4SEL)
+X(CH1_CDR_CNT8SEL)
+X(CH1_CTC_BYPASS)
+X(CH1_DCOATDCFG)
+X(CH1_DCOATDDLY)
+X(CH1_DCOBYPSATD)
+X(CH1_DCOCALDIV)
+X(CH1_DCOCTLGI)
+X(CH1_DCODISBDAVOID)
+X(CH1_DCOFLTDAC)
+X(CH1_DCOFTNRG)
+X(CH1_DCOIOSTUNE)
+X(CH1_DCOITUNE)
+X(CH1_DCOITUNE4LSB)
+X(CH1_DCOIUPDNX2)
+X(CH1_DCONUOFLSB)
+X(CH1_DCOSCALEI)
+X(CH1_DCOSTARTVAL)
+X(CH1_DCOSTEP)
+X(CH1_DEC_BYPASS)
+X(CH1_ENABLE_CG_ALIGN)
+X(CH1_ENC_BYPASS)
+X(CH1_FF_RX_F_CLK_DIS)
+X(CH1_FF_RX_H_CLK_EN)
+X(CH1_FF_TX_F_CLK_DIS)
+X(CH1_FF_TX_H_CLK_EN)
+X(CH1_GE_AN_ENABLE)
+X(CH1_INVERT_RX)
+X(CH1_INVERT_TX)
+X(CH1_LDR_CORE2TX_SEL)
+X(CH1_LDR_RX2CORE_SEL)
+X(CH1_LEQ_OFFSET_SEL)
+X(CH1_LEQ_OFFSET_TRIM)
+X(CH1_LSM_DISABLE)
+X(CH1_MATCH_2_ENABLE)
+X(CH1_MATCH_4_ENABLE)
+X(CH1_MIN_IPG_CNT)
+X(CH1_PCIE_EI_EN)
+X(CH1_PCIE_MODE)
+X(CH1_PCS_DET_TIME_SEL)
+X(CH1_PDEN_SEL)
+X(CH1_PRBS_ENABLE)
+X(CH1_PRBS_LOCK)
+X(CH1_PRBS_SELECTION)
+X(CH1_RATE_MODE_RX)
+X(CH1_RATE_MODE_TX)
+X(CH1_RCV_DCC_EN)
+X(CH1_REG_BAND_OFFSET)
+X(CH1_REG_BAND_SEL)
+X(CH1_REG_IDAC_EN)
+X(CH1_REG_IDAC_SEL)
+X(CH1_REQ_EN)
+X(CH1_REQ_LVL_SET)
+X(CH1_RIO_MODE)
+X(CH1_RLOS_SEL)
+X(CH1_RPWDNB)
+X(CH1_RTERM_RX)
+X(CH1_RTERM_TX)
+X(CH1_RXIN_CM)
+X(CH1_RXTERM_CM)
+X(CH1_RX_DCO_CK_DIV)
+X(CH1_RX_DIV11_SEL)
+X(CH1_RX_GEAR_BYPASS)
+X(CH1_RX_GEAR_MODE)
+X(CH1_RX_LOS_CEQ)
+X(CH1_RX_LOS_EN)
+X(CH1_RX_LOS_HYST_EN)
+X(CH1_RX_LOS_LVL)
+X(CH1_RX_RATE_SEL)
+X(CH1_RX_SB_BYPASS)
+X(CH1_SB_BYPASS)
+X(CH1_SEL_SD_RX_CLK)
+X(CH1_TDRV_DAT_SEL)
+X(CH1_TDRV_POST_EN)
+X(CH1_TDRV_PRE_EN)
+X(CH1_TDRV_SLICE0_CUR)
+X(CH1_TDRV_SLICE0_SEL)
+X(CH1_TDRV_SLICE1_CUR)
+X(CH1_TDRV_SLICE1_SEL)
+X(CH1_TDRV_SLICE2_CUR)
+X(CH1_TDRV_SLICE2_SEL)
+X(CH1_TDRV_SLICE3_CUR)
+X(CH1_TDRV_SLICE3_SEL)
+X(CH1_TDRV_SLICE4_CUR)
+X(CH1_TDRV_SLICE4_SEL)
+X(CH1_TDRV_SLICE5_CUR)
+X(CH1_TDRV_SLICE5_SEL)
+X(CH1_TPWDNB)
+X(CH1_TX_CM_SEL)
+X(CH1_TX_DIV11_SEL)
+X(CH1_TX_GEAR_BYPASS)
+X(CH1_TX_GEAR_MODE)
+X(CH1_TX_POST_SIGN)
+X(CH1_TX_PRE_SIGN)
+X(CH1_UC_MODE)
+X(CH1_UDF_COMMA_A)
+X(CH1_UDF_COMMA_B)
+X(CH1_UDF_COMMA_MASK)
+X(CH1_WA_BYPASS)
+X(CH1_WA_MODE)
+X(CIN)
+X(CLAMP)
+X(CLK0_DIV)
+X(CLK1_DIV)
+X(CLK2_DIV)
+X(CLK3_DIV)
+X(CLKAMUX)
+X(CLKBMUX)
+X(CLKFB_DIV)
+X(CLKIMUX)
+X(CLKI_DIV)
+X(CLKOMUX)
+X(CLKOP_DIV)
+X(CLKOP_ENABLE)
+X(CLKOP_TRIM_DELAY)
+X(CLKOP_TRIM_POL)
+X(CLKOS2_DIV)
+X(CLKOS2_ENABLE)
+X(CLKOS3_DIV)
+X(CLKOS3_ENABLE)
+X(CLKOS_DIV)
+X(CLKOS_ENABLE)
+X(CLKOS_TRIM_DELAY)
+X(CLKOS_TRIM_POL)
+X(CLKR)
+X(CLKW)
+X(COUT)
+X(CSDECODE_A)
+X(CSDECODE_B)
+X(D)
+X(D2)
+X(D3)
+X(D4)
+X(D5)
+X(D6)
+X(DATAMUX_MDDR)
+X(DATAMUX_ODDR)
+X(DATAMUX_OREG)
+X(DATA_WIDTH_A)
+X(DATA_WIDTH_B)
+X(DATA_WIDTH_W)
+X(DCSMODE)
+X(DDRDLLA)
+X(DELAYF)
+X(DELAYG)
+X(DEL_MODE)
+X(DEL_VALUE)
+X(DIFFRESISTOR)
+X(DIR)
+X(DIV)
+X(DPHASE_SOURCE)
+X(DQS_LI_DEL_ADJ)
+X(DQS_LI_DEL_VAL)
+X(DQS_LO_DEL_ADJ)
+X(DQS_LO_DEL_VAL)
+X(DRIVE)
+X(D_BITCLK_FROM_ND_EN)
+X(D_BITCLK_LOCAL_EN)
+X(D_BITCLK_ND_EN)
+X(D_BUS8BIT_SEL)
+X(D_CDR_LOL_SET)
+X(D_CMUSETBIASI)
+X(D_CMUSETI4CPP)
+X(D_CMUSETI4CPZ)
+X(D_CMUSETI4VCO)
+X(D_CMUSETICP4P)
+X(D_CMUSETICP4Z)
+X(D_CMUSETINITVCT)
+X(D_CMUSETISCL4VCO)
+X(D_CMUSETP1GM)
+X(D_CMUSETP2AGM)
+X(D_CMUSETZGM)
+X(D_DCO_CALIB_TIME_SEL)
+X(D_HIGH_MARK)
+X(D_IB_PWDNB)
+X(D_ISETLOS)
+X(D_LOW_MARK)
+X(D_MACROPDB)
+X(D_PD_ISET)
+X(D_PLL_LOL_SET)
+X(D_REFCK_MODE)
+X(D_REQ_ISET)
+X(D_RG_EN)
+X(D_RG_SET)
+X(D_SETICONST_AUX)
+X(D_SETICONST_CH)
+X(D_SETIRPOLY_AUX)
+X(D_SETIRPOLY_CH)
+X(D_SETPLLRC)
+X(D_SYNC_LOCAL_EN)
+X(D_SYNC_ND_EN)
+X(D_TXPLL_PWDNB)
+X(D_TX_VCO_CK_DIV)
+X(D_XGE_MODE)
+X(E)
+X(ECP5_IS_GLOBAL)
+X(ER1)
+X(ER2)
+X(FEEDBK_PATH)
+X(FORCE_MAX_DELAY)
+X(FORCE_ZERO_BARREL_SHIFT)
+X(FREQ_LOCK_ACCURACY)
+X(GND)
+X(HYSTERESIS)
+X(ICP_CURRENT)
+X(IDDR71B)
+X(IDDRX1F)
+X(IDDRX2DQA)
+X(IDDRX2F)
+X(INIT)
+X(INIT0)
+X(INIT1)
+X(INITVAL)
+X(INJECT1_0)
+X(INJECT1_1)
+X(INTFB_WAKE)
+X(INT_LOCK_STICKY)
+X(INV)
+X(IOLTOMUX)
+X(IO_TYPE)
+X(KVCO)
+X(L6MUX21)
+X(LEGACY)
+X(LOC)
+X(LPF_CAPACITOR)
+X(LPF_RESISTOR)
+X(LSRIMUX)
+X(LSRMODE)
+X(LSROMUX)
+X(LUT0_INITVAL)
+X(LUT1_INITVAL)
+X(LUT4)
+X(M)
+X(MASK01)
+X(MASKPAT)
+X(MASKPAT_SOURCE)
+X(MCPAT)
+X(MCPAT_SOURCE)
+X(MFG1_TEST)
+X(MFG2_TEST)
+X(MFG_ENABLE_FILTEROPAMP)
+X(MFG_EN_UP)
+X(MFG_FLOAT_ICP)
+X(MFG_FORCE_VFILTER)
+X(MFG_GMCREF_SEL)
+X(MFG_GMC_GAIN)
+X(MFG_GMC_PRESET)
+X(MFG_GMC_RESET)
+X(MFG_GMC_TEST)
+X(MFG_ICP_TEST)
+X(MFG_LF_PRESET)
+X(MFG_LF_RESET)
+X(MFG_LF_RESGRND)
+X(MODE)
+X(MULT_BYPASS)
+X(OCEAMUX)
+X(OCEBMUX)
+X(OCER)
+X(ODDR71B)
+X(ODDRX1F)
+X(ODDRX2DQA)
+X(ODDRX2DQSB)
+X(ODDRX2F)
+X(OPENDRAIN)
+X(OSHX2A)
+X(OUTDIVIDER_MUXA)
+X(OUTDIVIDER_MUXB)
+X(OUTDIVIDER_MUXC)
+X(OUTDIVIDER_MUXD)
+X(PDPW16KD)
+X(PFUMX)
+X(PLLRST_ENA)
+X(PLL_LOCK_MODE)
+X(PULLMODE)
+X(Q)
+X(Q2)
+X(Q3)
+X(Q4)
+X(Q5)
+X(Q6)
+X(QWL)
+X(REFCK_DCBIAS_EN)
+X(REFCK_PWDNB)
+X(REFCK_RTERM)
+X(REFIN_RESET)
+X(REG0_LSRMODE)
+X(REG0_REGSET)
+X(REG0_SD)
+X(REG1_LSRMODE)
+X(REG1_REGSET)
+X(REG1_SD)
+X(REGMODE)
+X(REGMODE_A)
+X(REGMODE_B)
+X(REGSET)
+X(REG_FLAG_CLK)
+X(REG_INPUTA_CE)
+X(REG_INPUTA_CLK)
+X(REG_INPUTA_RST)
+X(REG_INPUTB_CE)
+X(REG_INPUTB_CLK)
+X(REG_INPUTB_RST)
+X(REG_INPUTC0_CLK)
+X(REG_INPUTC1_CLK)
+X(REG_INPUTC_CLK)
+X(REG_OPCODEIN_0_CE)
+X(REG_OPCODEIN_0_CLK)
+X(REG_OPCODEIN_0_RST)
+X(REG_OPCODEIN_1_CE)
+X(REG_OPCODEIN_1_CLK)
+X(REG_OPCODEIN_1_RST)
+X(REG_OPCODEOP0_0_CE)
+X(REG_OPCODEOP0_0_CLK)
+X(REG_OPCODEOP0_0_RST)
+X(REG_OPCODEOP0_1_CE)
+X(REG_OPCODEOP0_1_CLK)
+X(REG_OPCODEOP0_1_RST)
+X(REG_OPCODEOP1_0_CLK)
+X(REG_OPCODEOP1_1_CLK)
+X(REG_OUTPUT0_CLK)
+X(REG_OUTPUT1_CLK)
+X(REG_OUTPUT_CLK)
+X(REG_OUTPUT_RST)
+X(REG_PIPELINE_CE)
+X(REG_PIPELINE_CLK)
+X(REG_PIPELINE_RST)
+X(RESETMODE)
+X(RNDPAT)
+X(RSTAMUX)
+X(RSTBMUX)
+X(S0)
+X(S1)
+X(SD)
+X(SGSR)
+X(SLEWRATE)
+X(SOURCEB_MODE)
+X(STDBY_ENABLE)
+X(SYNCMODE)
+X(SYNC_ENABLE)
+X(T0)
+X(T1)
+X(TERMINATION)
+X(TILE_WIRE_ID)
+X(TRELLIS_DPR16X4)
+X(TRELLIS_FF)
+X(TRIMUX_TSREG)
+X(TSHX2DQA)
+X(TSHX2DQSA)
+X(USRMCLKI)
+X(USRMCLKO)
+X(USRMCLKTS)
+X(VCC)
+X(WCKMUX)
+X(WEAMUX)
+X(WEBMUX)
+X(WID)
+X(WREMUX)
+X(WRITEMODE_A)
+X(WRITEMODE_B)
+X(Y)
+X(ioff_dir)
+X(lfe5u_12f)
+X(lfe5u_25f)
+X(lfe5u_45f)
+X(lfe5u_85f)
+X(lfe5um5g_25f)
+X(lfe5um5g_45f)
+X(lfe5um5g_85f)
+X(lfe5um_25f)
+X(lfe5um_45f)
+X(lfe5um_85f)
+X(noglobal)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
+X(syn_useioff)
diff --git a/ecp5/dcu_bitstream.h b/ecp5/dcu_bitstream.h
index 0c461a6bb7..4f0e63e101 100644
--- a/ecp5/dcu_bitstream.h
+++ b/ecp5/dcu_bitstream.h
@@ -1,504 +1,424 @@
 tg.config.add_word("DCU.CH0_AUTO_CALIB_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_AUTO_CALIB_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_AUTO_CALIB_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_AUTO_FACQ_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_AUTO_FACQ_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_AUTO_FACQ_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_BAND_THRESHOLD",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_BAND_THRESHOLD"), Property(0)), 6));
+                   parse_config_str(get_or_default(ci->params, id_CH0_BAND_THRESHOLD, Property(0)), 6));
 tg.config.add_word("DCU.CH0_CALIB_CK_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CALIB_CK_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CALIB_CK_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_CC_MATCH_1",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_1"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_1, Property(0)), 10));
 tg.config.add_word("DCU.CH0_CC_MATCH_2",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_2"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_2, Property(0)), 10));
 tg.config.add_word("DCU.CH0_CC_MATCH_3",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_3"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_3, Property(0)), 10));
 tg.config.add_word("DCU.CH0_CC_MATCH_4",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_4"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_4, Property(0)), 10));
 tg.config.add_word("DCU.CH0_CDR_CNT4SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CDR_CNT4SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CDR_CNT4SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_CDR_CNT8SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CDR_CNT8SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CDR_CNT8SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_CTC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_CTC_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOATDCFG",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOATDCFG"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_DCOATDDLY",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOATDDLY"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_CTC_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOATDCFG", parse_config_str(get_or_default(ci->params, id_CH0_DCOATDCFG, Property(0)), 2));
+tg.config.add_word("DCU.CH0_DCOATDDLY", parse_config_str(get_or_default(ci->params, id_CH0_DCOATDDLY, Property(0)), 2));
 tg.config.add_word("DCU.CH0_DCOBYPSATD",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOBYPSATD"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOCALDIV",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOCALDIV"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOCTLGI",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOCTLGI"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCOBYPSATD, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOCALDIV", parse_config_str(get_or_default(ci->params, id_CH0_DCOCALDIV, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOCTLGI", parse_config_str(get_or_default(ci->params, id_CH0_DCOCTLGI, Property(0)), 3));
 tg.config.add_word("DCU.CH0_DCODISBDAVOID",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCODISBDAVOID"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOFLTDAC",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOFLTDAC"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_DCOFTNRG",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOFTNRG"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCODISBDAVOID, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOFLTDAC", parse_config_str(get_or_default(ci->params, id_CH0_DCOFLTDAC, Property(0)), 2));
+tg.config.add_word("DCU.CH0_DCOFTNRG", parse_config_str(get_or_default(ci->params, id_CH0_DCOFTNRG, Property(0)), 3));
 tg.config.add_word("DCU.CH0_DCOIOSTUNE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOIOSTUNE"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOITUNE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOITUNE"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCOIOSTUNE, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOITUNE", parse_config_str(get_or_default(ci->params, id_CH0_DCOITUNE, Property(0)), 2));
 tg.config.add_word("DCU.CH0_DCOITUNE4LSB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOITUNE4LSB"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCOITUNE4LSB, Property(0)), 3));
 tg.config.add_word("DCU.CH0_DCOIUPDNX2",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOIUPDNX2"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCOIUPDNX2, Property(0)), 1));
 tg.config.add_word("DCU.CH0_DCONUOFLSB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCONUOFLSB"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOSCALEI",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSCALEI"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCONUOFLSB, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOSCALEI", parse_config_str(get_or_default(ci->params, id_CH0_DCOSCALEI, Property(0)), 2));
 tg.config.add_word("DCU.CH0_DCOSTARTVAL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSTARTVAL"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOSTEP",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSTEP"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DCOSTARTVAL, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOSTEP", parse_config_str(get_or_default(ci->params, id_CH0_DCOSTEP, Property(0)), 2));
 tg.config.add_word("DCU.CH0_DEC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_DEC_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_DEC_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_ENABLE_CG_ALIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_ENABLE_CG_ALIGN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_ENABLE_CG_ALIGN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_ENC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_ENC_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_ENC_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_FF_RX_F_CLK_DIS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_RX_F_CLK_DIS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_FF_RX_F_CLK_DIS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_FF_RX_H_CLK_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_RX_H_CLK_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_FF_RX_H_CLK_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_FF_TX_F_CLK_DIS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_TX_F_CLK_DIS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_FF_TX_F_CLK_DIS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_FF_TX_H_CLK_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_TX_H_CLK_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_FF_TX_H_CLK_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_GE_AN_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_GE_AN_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_INVERT_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_INVERT_RX"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_INVERT_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_INVERT_TX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_GE_AN_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_INVERT_RX", parse_config_str(get_or_default(ci->params, id_CH0_INVERT_RX, Property(0)), 1));
+tg.config.add_word("DCU.CH0_INVERT_TX", parse_config_str(get_or_default(ci->params, id_CH0_INVERT_TX, Property(0)), 1));
 tg.config.add_word("DCU.CH0_LDR_CORE2TX_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_LDR_CORE2TX_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_LDR_CORE2TX_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_LDR_RX2CORE_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_LDR_RX2CORE_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_LDR_RX2CORE_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_LEQ_OFFSET_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_LEQ_OFFSET_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_LEQ_OFFSET_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_LEQ_OFFSET_TRIM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_LEQ_OFFSET_TRIM"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_LEQ_OFFSET_TRIM, Property(0)), 3));
 tg.config.add_word("DCU.CH0_LSM_DISABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_LSM_DISABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_LSM_DISABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_MATCH_2_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_MATCH_2_ENABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_MATCH_2_ENABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_MATCH_4_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_MATCH_4_ENABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_MATCH_4_ENABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_MIN_IPG_CNT",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_MIN_IPG_CNT"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_MIN_IPG_CNT, Property(0)), 2));
 tg.config.add_word("DCU.CH0_PCIE_EI_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCIE_EI_EN"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_PCIE_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCIE_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_PCIE_EI_EN, Property(0)), 1));
+tg.config.add_word("DCU.CH0_PCIE_MODE", parse_config_str(get_or_default(ci->params, id_CH0_PCIE_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_PCS_DET_TIME_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCS_DET_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_PDEN_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PDEN_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_PCS_DET_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH0_PDEN_SEL", parse_config_str(get_or_default(ci->params, id_CH0_PDEN_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_PRBS_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_PRBS_LOCK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_LOCK"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_PRBS_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_PRBS_LOCK", parse_config_str(get_or_default(ci->params, id_CH0_PRBS_LOCK, Property(0)), 1));
 tg.config.add_word("DCU.CH0_PRBS_SELECTION",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_SELECTION"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_PRBS_SELECTION, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RATE_MODE_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RATE_MODE_RX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RATE_MODE_RX, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RATE_MODE_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RATE_MODE_TX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RATE_MODE_TX, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RCV_DCC_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RCV_DCC_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RCV_DCC_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_REG_BAND_OFFSET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_BAND_OFFSET"), Property(0)), 4));
+                   parse_config_str(get_or_default(ci->params, id_CH0_REG_BAND_OFFSET, Property(0)), 4));
 tg.config.add_word("DCU.CH0_REG_BAND_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_BAND_SEL"), Property(0)), 6));
+                   parse_config_str(get_or_default(ci->params, id_CH0_REG_BAND_SEL, Property(0)), 6));
 tg.config.add_word("DCU.CH0_REG_IDAC_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_IDAC_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_REG_IDAC_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_REG_IDAC_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_IDAC_SEL"), Property(0)), 10));
-tg.config.add_word("DCU.CH0_REQ_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REQ_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_REG_IDAC_SEL, Property(0)), 10));
+tg.config.add_word("DCU.CH0_REQ_EN", parse_config_str(get_or_default(ci->params, id_CH0_REQ_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_REQ_LVL_SET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_REQ_LVL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RIO_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RIO_MODE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RLOS_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RLOS_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RPWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RTERM_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RTERM_RX"), Property(0)), 5));
-tg.config.add_word("DCU.CH0_RTERM_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RTERM_TX"), Property(0)), 5));
-tg.config.add_word("DCU.CH0_RXIN_CM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RXIN_CM"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RXTERM_CM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RXTERM_CM"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_REQ_LVL_SET, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RIO_MODE", parse_config_str(get_or_default(ci->params, id_CH0_RIO_MODE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RLOS_SEL", parse_config_str(get_or_default(ci->params, id_CH0_RLOS_SEL, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RPWDNB", parse_config_str(get_or_default(ci->params, id_CH0_RPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RTERM_RX", parse_config_str(get_or_default(ci->params, id_CH0_RTERM_RX, Property(0)), 5));
+tg.config.add_word("DCU.CH0_RTERM_TX", parse_config_str(get_or_default(ci->params, id_CH0_RTERM_TX, Property(0)), 5));
+tg.config.add_word("DCU.CH0_RXIN_CM", parse_config_str(get_or_default(ci->params, id_CH0_RXIN_CM, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RXTERM_CM", parse_config_str(get_or_default(ci->params, id_CH0_RXTERM_CM, Property(0)), 2));
 tg.config.add_word("DCU.CH0_RX_DCO_CK_DIV",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_DCO_CK_DIV"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_DCO_CK_DIV, Property(0)), 3));
 tg.config.add_word("DCU.CH0_RX_DIV11_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_DIV11_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_DIV11_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RX_GEAR_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_GEAR_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_GEAR_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RX_GEAR_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_GEAR_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_GEAR_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RX_LOS_CEQ",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_CEQ"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RX_LOS_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_CEQ, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RX_LOS_EN", parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RX_LOS_HYST_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_HYST_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_HYST_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_RX_LOS_LVL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_LVL"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_LVL, Property(0)), 3));
 tg.config.add_word("DCU.CH0_RX_RATE_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_RATE_SEL"), Property(0)), 4));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_RATE_SEL, Property(0)), 4));
 tg.config.add_word("DCU.CH0_RX_SB_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_SB_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_SB_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_SB_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_RX_SB_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_SB_BYPASS", parse_config_str(get_or_default(ci->params, id_CH0_SB_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_SEL_SD_RX_CLK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_SEL_SD_RX_CLK"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_SEL_SD_RX_CLK, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TDRV_DAT_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_DAT_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_DAT_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_POST_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_POST_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_POST_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TDRV_PRE_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_PRE_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_PRE_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TDRV_SLICE0_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE0_CUR"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE0_CUR, Property(0)), 3));
 tg.config.add_word("DCU.CH0_TDRV_SLICE0_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE0_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE0_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE1_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE1_CUR"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE1_CUR, Property(0)), 3));
 tg.config.add_word("DCU.CH0_TDRV_SLICE1_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE1_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE1_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE2_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE2_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE2_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE2_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE2_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE2_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE3_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE3_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE3_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE3_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE3_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE3_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE4_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE4_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE4_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE4_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE4_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE4_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE5_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE5_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE5_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TDRV_SLICE5_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE5_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_TPWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_TX_CM_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_CM_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE5_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH0_TPWDNB", parse_config_str(get_or_default(ci->params, id_CH0_TPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH0_TX_CM_SEL", parse_config_str(get_or_default(ci->params, id_CH0_TX_CM_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH0_TX_DIV11_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_DIV11_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TX_DIV11_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TX_GEAR_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_GEAR_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TX_GEAR_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TX_GEAR_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_GEAR_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TX_GEAR_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TX_POST_SIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_POST_SIGN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TX_POST_SIGN, Property(0)), 1));
 tg.config.add_word("DCU.CH0_TX_PRE_SIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_PRE_SIGN"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_UC_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_UC_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_TX_PRE_SIGN, Property(0)), 1));
+tg.config.add_word("DCU.CH0_UC_MODE", parse_config_str(get_or_default(ci->params, id_CH0_UC_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH0_UDF_COMMA_A",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_A"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_A, Property(0)), 10));
 tg.config.add_word("DCU.CH0_UDF_COMMA_B",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_B"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_B, Property(0)), 10));
 tg.config.add_word("DCU.CH0_UDF_COMMA_MASK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_MASK"), Property(0)), 10));
-tg.config.add_word("DCU.CH0_WA_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_WA_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_WA_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH0_WA_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_MASK, Property(0)), 10));
+tg.config.add_word("DCU.CH0_WA_BYPASS", parse_config_str(get_or_default(ci->params, id_CH0_WA_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_WA_MODE", parse_config_str(get_or_default(ci->params, id_CH0_WA_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_AUTO_CALIB_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_AUTO_CALIB_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_AUTO_CALIB_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_AUTO_FACQ_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_AUTO_FACQ_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_AUTO_FACQ_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_BAND_THRESHOLD",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_BAND_THRESHOLD"), Property(0)), 6));
+                   parse_config_str(get_or_default(ci->params, id_CH1_BAND_THRESHOLD, Property(0)), 6));
 tg.config.add_word("DCU.CH1_CALIB_CK_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CALIB_CK_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CALIB_CK_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_CC_MATCH_1",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_1"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_1, Property(0)), 10));
 tg.config.add_word("DCU.CH1_CC_MATCH_2",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_2"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_2, Property(0)), 10));
 tg.config.add_word("DCU.CH1_CC_MATCH_3",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_3"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_3, Property(0)), 10));
 tg.config.add_word("DCU.CH1_CC_MATCH_4",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_4"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_4, Property(0)), 10));
 tg.config.add_word("DCU.CH1_CDR_CNT4SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CDR_CNT4SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CDR_CNT4SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_CDR_CNT8SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CDR_CNT8SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CDR_CNT8SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_CTC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_CTC_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOATDCFG",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOATDCFG"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_DCOATDDLY",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOATDDLY"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_CTC_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOATDCFG", parse_config_str(get_or_default(ci->params, id_CH1_DCOATDCFG, Property(0)), 2));
+tg.config.add_word("DCU.CH1_DCOATDDLY", parse_config_str(get_or_default(ci->params, id_CH1_DCOATDDLY, Property(0)), 2));
 tg.config.add_word("DCU.CH1_DCOBYPSATD",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOBYPSATD"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOCALDIV",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOCALDIV"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOCTLGI",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOCTLGI"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCOBYPSATD, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOCALDIV", parse_config_str(get_or_default(ci->params, id_CH1_DCOCALDIV, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOCTLGI", parse_config_str(get_or_default(ci->params, id_CH1_DCOCTLGI, Property(0)), 3));
 tg.config.add_word("DCU.CH1_DCODISBDAVOID",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCODISBDAVOID"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOFLTDAC",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOFLTDAC"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_DCOFTNRG",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOFTNRG"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCODISBDAVOID, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOFLTDAC", parse_config_str(get_or_default(ci->params, id_CH1_DCOFLTDAC, Property(0)), 2));
+tg.config.add_word("DCU.CH1_DCOFTNRG", parse_config_str(get_or_default(ci->params, id_CH1_DCOFTNRG, Property(0)), 3));
 tg.config.add_word("DCU.CH1_DCOIOSTUNE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOIOSTUNE"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOITUNE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOITUNE"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCOIOSTUNE, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOITUNE", parse_config_str(get_or_default(ci->params, id_CH1_DCOITUNE, Property(0)), 2));
 tg.config.add_word("DCU.CH1_DCOITUNE4LSB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOITUNE4LSB"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCOITUNE4LSB, Property(0)), 3));
 tg.config.add_word("DCU.CH1_DCOIUPDNX2",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOIUPDNX2"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCOIUPDNX2, Property(0)), 1));
 tg.config.add_word("DCU.CH1_DCONUOFLSB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCONUOFLSB"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOSCALEI",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSCALEI"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCONUOFLSB, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOSCALEI", parse_config_str(get_or_default(ci->params, id_CH1_DCOSCALEI, Property(0)), 2));
 tg.config.add_word("DCU.CH1_DCOSTARTVAL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSTARTVAL"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOSTEP",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSTEP"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DCOSTARTVAL, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOSTEP", parse_config_str(get_or_default(ci->params, id_CH1_DCOSTEP, Property(0)), 2));
 tg.config.add_word("DCU.CH1_DEC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_DEC_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_DEC_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_ENABLE_CG_ALIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_ENABLE_CG_ALIGN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_ENABLE_CG_ALIGN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_ENC_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_ENC_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_ENC_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_FF_RX_F_CLK_DIS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_RX_F_CLK_DIS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_FF_RX_F_CLK_DIS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_FF_RX_H_CLK_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_RX_H_CLK_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_FF_RX_H_CLK_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_FF_TX_F_CLK_DIS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_TX_F_CLK_DIS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_FF_TX_F_CLK_DIS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_FF_TX_H_CLK_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_TX_H_CLK_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_FF_TX_H_CLK_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_GE_AN_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_GE_AN_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_INVERT_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_INVERT_RX"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_INVERT_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_INVERT_TX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_GE_AN_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_INVERT_RX", parse_config_str(get_or_default(ci->params, id_CH1_INVERT_RX, Property(0)), 1));
+tg.config.add_word("DCU.CH1_INVERT_TX", parse_config_str(get_or_default(ci->params, id_CH1_INVERT_TX, Property(0)), 1));
 tg.config.add_word("DCU.CH1_LDR_CORE2TX_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_LDR_CORE2TX_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_LDR_CORE2TX_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_LDR_RX2CORE_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_LDR_RX2CORE_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_LDR_RX2CORE_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_LEQ_OFFSET_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_LEQ_OFFSET_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_LEQ_OFFSET_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_LEQ_OFFSET_TRIM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_LEQ_OFFSET_TRIM"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_LEQ_OFFSET_TRIM, Property(0)), 3));
 tg.config.add_word("DCU.CH1_LSM_DISABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_LSM_DISABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_LSM_DISABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_MATCH_2_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_MATCH_2_ENABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_MATCH_2_ENABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_MATCH_4_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_MATCH_4_ENABLE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_MATCH_4_ENABLE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_MIN_IPG_CNT",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_MIN_IPG_CNT"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_MIN_IPG_CNT, Property(0)), 2));
 tg.config.add_word("DCU.CH1_PCIE_EI_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCIE_EI_EN"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_PCIE_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCIE_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_PCIE_EI_EN, Property(0)), 1));
+tg.config.add_word("DCU.CH1_PCIE_MODE", parse_config_str(get_or_default(ci->params, id_CH1_PCIE_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_PCS_DET_TIME_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCS_DET_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_PDEN_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PDEN_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_PCS_DET_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH1_PDEN_SEL", parse_config_str(get_or_default(ci->params, id_CH1_PDEN_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_PRBS_ENABLE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_PRBS_LOCK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_LOCK"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_PRBS_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_PRBS_LOCK", parse_config_str(get_or_default(ci->params, id_CH1_PRBS_LOCK, Property(0)), 1));
 tg.config.add_word("DCU.CH1_PRBS_SELECTION",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_SELECTION"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_PRBS_SELECTION, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RATE_MODE_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RATE_MODE_RX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RATE_MODE_RX, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RATE_MODE_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RATE_MODE_TX"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RATE_MODE_TX, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RCV_DCC_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RCV_DCC_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RCV_DCC_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_REG_BAND_OFFSET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_BAND_OFFSET"), Property(0)), 4));
+                   parse_config_str(get_or_default(ci->params, id_CH1_REG_BAND_OFFSET, Property(0)), 4));
 tg.config.add_word("DCU.CH1_REG_BAND_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_BAND_SEL"), Property(0)), 6));
+                   parse_config_str(get_or_default(ci->params, id_CH1_REG_BAND_SEL, Property(0)), 6));
 tg.config.add_word("DCU.CH1_REG_IDAC_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_IDAC_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_REG_IDAC_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_REG_IDAC_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_IDAC_SEL"), Property(0)), 10));
-tg.config.add_word("DCU.CH1_REQ_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REQ_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_REG_IDAC_SEL, Property(0)), 10));
+tg.config.add_word("DCU.CH1_REQ_EN", parse_config_str(get_or_default(ci->params, id_CH1_REQ_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_REQ_LVL_SET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_REQ_LVL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RIO_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RIO_MODE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RLOS_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RLOS_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RPWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RTERM_RX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RTERM_RX"), Property(0)), 5));
-tg.config.add_word("DCU.CH1_RTERM_TX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RTERM_TX"), Property(0)), 5));
-tg.config.add_word("DCU.CH1_RXIN_CM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RXIN_CM"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RXTERM_CM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RXTERM_CM"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_REQ_LVL_SET, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RIO_MODE", parse_config_str(get_or_default(ci->params, id_CH1_RIO_MODE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RLOS_SEL", parse_config_str(get_or_default(ci->params, id_CH1_RLOS_SEL, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RPWDNB", parse_config_str(get_or_default(ci->params, id_CH1_RPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RTERM_RX", parse_config_str(get_or_default(ci->params, id_CH1_RTERM_RX, Property(0)), 5));
+tg.config.add_word("DCU.CH1_RTERM_TX", parse_config_str(get_or_default(ci->params, id_CH1_RTERM_TX, Property(0)), 5));
+tg.config.add_word("DCU.CH1_RXIN_CM", parse_config_str(get_or_default(ci->params, id_CH1_RXIN_CM, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RXTERM_CM", parse_config_str(get_or_default(ci->params, id_CH1_RXTERM_CM, Property(0)), 2));
 tg.config.add_word("DCU.CH1_RX_DCO_CK_DIV",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_DCO_CK_DIV"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_DCO_CK_DIV, Property(0)), 3));
 tg.config.add_word("DCU.CH1_RX_DIV11_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_DIV11_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_DIV11_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RX_GEAR_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_GEAR_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_GEAR_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RX_GEAR_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_GEAR_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_GEAR_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RX_LOS_CEQ",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_CEQ"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RX_LOS_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_CEQ, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RX_LOS_EN", parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RX_LOS_HYST_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_HYST_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_HYST_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_RX_LOS_LVL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_LVL"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_LVL, Property(0)), 3));
 tg.config.add_word("DCU.CH1_RX_RATE_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_RATE_SEL"), Property(0)), 4));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_RATE_SEL, Property(0)), 4));
 tg.config.add_word("DCU.CH1_RX_SB_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_SB_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_SB_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_SB_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_RX_SB_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_SB_BYPASS", parse_config_str(get_or_default(ci->params, id_CH1_SB_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_SEL_SD_RX_CLK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_SEL_SD_RX_CLK"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_SEL_SD_RX_CLK, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TDRV_DAT_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_DAT_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_DAT_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_POST_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_POST_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_POST_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TDRV_PRE_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_PRE_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_PRE_EN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TDRV_SLICE0_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE0_CUR"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE0_CUR, Property(0)), 3));
 tg.config.add_word("DCU.CH1_TDRV_SLICE0_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE0_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE0_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE1_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE1_CUR"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE1_CUR, Property(0)), 3));
 tg.config.add_word("DCU.CH1_TDRV_SLICE1_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE1_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE1_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE2_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE2_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE2_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE2_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE2_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE2_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE3_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE3_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE3_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE3_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE3_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE3_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE4_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE4_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE4_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE4_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE4_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE4_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE5_CUR",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE5_CUR"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE5_CUR, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TDRV_SLICE5_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE5_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_TPWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_TX_CM_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_CM_SEL"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE5_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH1_TPWDNB", parse_config_str(get_or_default(ci->params, id_CH1_TPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH1_TX_CM_SEL", parse_config_str(get_or_default(ci->params, id_CH1_TX_CM_SEL, Property(0)), 2));
 tg.config.add_word("DCU.CH1_TX_DIV11_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_DIV11_SEL"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TX_DIV11_SEL, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TX_GEAR_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_GEAR_BYPASS"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TX_GEAR_BYPASS, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TX_GEAR_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_GEAR_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TX_GEAR_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TX_POST_SIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_POST_SIGN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TX_POST_SIGN, Property(0)), 1));
 tg.config.add_word("DCU.CH1_TX_PRE_SIGN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_PRE_SIGN"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_UC_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_UC_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_TX_PRE_SIGN, Property(0)), 1));
+tg.config.add_word("DCU.CH1_UC_MODE", parse_config_str(get_or_default(ci->params, id_CH1_UC_MODE, Property(0)), 1));
 tg.config.add_word("DCU.CH1_UDF_COMMA_A",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_A"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_A, Property(0)), 10));
 tg.config.add_word("DCU.CH1_UDF_COMMA_B",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_B"), Property(0)), 10));
+                   parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_B, Property(0)), 10));
 tg.config.add_word("DCU.CH1_UDF_COMMA_MASK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_MASK"), Property(0)), 10));
-tg.config.add_word("DCU.CH1_WA_BYPASS",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_WA_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_WA_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("CH1_WA_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_MASK, Property(0)), 10));
+tg.config.add_word("DCU.CH1_WA_BYPASS", parse_config_str(get_or_default(ci->params, id_CH1_WA_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_WA_MODE", parse_config_str(get_or_default(ci->params, id_CH1_WA_MODE, Property(0)), 1));
 tg.config.add_word("DCU.D_BITCLK_FROM_ND_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_FROM_ND_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_D_BITCLK_FROM_ND_EN, Property(0)), 1));
 tg.config.add_word("DCU.D_BITCLK_LOCAL_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_LOCAL_EN"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_D_BITCLK_LOCAL_EN, Property(0)), 1));
 tg.config.add_word("DCU.D_BITCLK_ND_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_ND_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_BUS8BIT_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_BUS8BIT_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.D_CDR_LOL_SET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CDR_LOL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETBIASI",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETBIASI"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETI4CPP",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4CPP"), Property(0)), 4));
-tg.config.add_word("DCU.D_CMUSETI4CPZ",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4CPZ"), Property(0)), 4));
-tg.config.add_word("DCU.D_CMUSETI4VCO",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4VCO"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETICP4P",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETICP4P"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETICP4Z",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETICP4Z"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_D_BITCLK_ND_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_BUS8BIT_SEL", parse_config_str(get_or_default(ci->params, id_D_BUS8BIT_SEL, Property(0)), 1));
+tg.config.add_word("DCU.D_CDR_LOL_SET", parse_config_str(get_or_default(ci->params, id_D_CDR_LOL_SET, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETBIASI", parse_config_str(get_or_default(ci->params, id_D_CMUSETBIASI, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETI4CPP", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4CPP, Property(0)), 4));
+tg.config.add_word("DCU.D_CMUSETI4CPZ", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4CPZ, Property(0)), 4));
+tg.config.add_word("DCU.D_CMUSETI4VCO", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4VCO, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETICP4P", parse_config_str(get_or_default(ci->params, id_D_CMUSETICP4P, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETICP4Z", parse_config_str(get_or_default(ci->params, id_D_CMUSETICP4Z, Property(0)), 3));
 tg.config.add_word("DCU.D_CMUSETINITVCT",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETINITVCT"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_D_CMUSETINITVCT, Property(0)), 2));
 tg.config.add_word("DCU.D_CMUSETISCL4VCO",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETISCL4VCO"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETP1GM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETP1GM"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETP2AGM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETP2AGM"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETZGM",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETZGM"), Property(0)), 3));
+                   parse_config_str(get_or_default(ci->params, id_D_CMUSETISCL4VCO, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETP1GM", parse_config_str(get_or_default(ci->params, id_D_CMUSETP1GM, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETP2AGM", parse_config_str(get_or_default(ci->params, id_D_CMUSETP2AGM, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETZGM", parse_config_str(get_or_default(ci->params, id_D_CMUSETZGM, Property(0)), 3));
 tg.config.add_word("DCU.D_DCO_CALIB_TIME_SEL",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_DCO_CALIB_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.D_HIGH_MARK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_HIGH_MARK"), Property(0)), 4));
-tg.config.add_word("DCU.D_IB_PWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_IB_PWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.D_ISETLOS", parse_config_str(get_or_default(ci->params, ctx->id("D_ISETLOS"), Property(0)), 8));
-tg.config.add_word("DCU.D_LOW_MARK",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_LOW_MARK"), Property(0)), 4));
-tg.config.add_word("DCU.D_MACROPDB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_MACROPDB"), Property(0)), 1));
-tg.config.add_word("DCU.D_PD_ISET", parse_config_str(get_or_default(ci->params, ctx->id("D_PD_ISET"), Property(0)), 2));
-tg.config.add_word("DCU.D_PLL_LOL_SET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_PLL_LOL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.D_REFCK_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_REFCK_MODE"), Property(0)), 3));
-tg.config.add_word("DCU.D_REQ_ISET",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_REQ_ISET"), Property(0)), 3));
-tg.config.add_word("DCU.D_RG_EN", parse_config_str(get_or_default(ci->params, ctx->id("D_RG_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_RG_SET", parse_config_str(get_or_default(ci->params, ctx->id("D_RG_SET"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_D_DCO_CALIB_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.D_HIGH_MARK", parse_config_str(get_or_default(ci->params, id_D_HIGH_MARK, Property(0)), 4));
+tg.config.add_word("DCU.D_IB_PWDNB", parse_config_str(get_or_default(ci->params, id_D_IB_PWDNB, Property(0)), 1));
+tg.config.add_word("DCU.D_ISETLOS", parse_config_str(get_or_default(ci->params, id_D_ISETLOS, Property(0)), 8));
+tg.config.add_word("DCU.D_LOW_MARK", parse_config_str(get_or_default(ci->params, id_D_LOW_MARK, Property(0)), 4));
+tg.config.add_word("DCU.D_MACROPDB", parse_config_str(get_or_default(ci->params, id_D_MACROPDB, Property(0)), 1));
+tg.config.add_word("DCU.D_PD_ISET", parse_config_str(get_or_default(ci->params, id_D_PD_ISET, Property(0)), 2));
+tg.config.add_word("DCU.D_PLL_LOL_SET", parse_config_str(get_or_default(ci->params, id_D_PLL_LOL_SET, Property(0)), 2));
+tg.config.add_word("DCU.D_REFCK_MODE", parse_config_str(get_or_default(ci->params, id_D_REFCK_MODE, Property(0)), 3));
+tg.config.add_word("DCU.D_REQ_ISET", parse_config_str(get_or_default(ci->params, id_D_REQ_ISET, Property(0)), 3));
+tg.config.add_word("DCU.D_RG_EN", parse_config_str(get_or_default(ci->params, id_D_RG_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_RG_SET", parse_config_str(get_or_default(ci->params, id_D_RG_SET, Property(0)), 2));
 tg.config.add_word("DCU.D_SETICONST_AUX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SETICONST_AUX"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_D_SETICONST_AUX, Property(0)), 2));
 tg.config.add_word("DCU.D_SETICONST_CH",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SETICONST_CH"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_D_SETICONST_CH, Property(0)), 2));
 tg.config.add_word("DCU.D_SETIRPOLY_AUX",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SETIRPOLY_AUX"), Property(0)), 2));
+                   parse_config_str(get_or_default(ci->params, id_D_SETIRPOLY_AUX, Property(0)), 2));
 tg.config.add_word("DCU.D_SETIRPOLY_CH",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SETIRPOLY_CH"), Property(0)), 2));
-tg.config.add_word("DCU.D_SETPLLRC",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SETPLLRC"), Property(0)), 6));
+                   parse_config_str(get_or_default(ci->params, id_D_SETIRPOLY_CH, Property(0)), 2));
+tg.config.add_word("DCU.D_SETPLLRC", parse_config_str(get_or_default(ci->params, id_D_SETPLLRC, Property(0)), 6));
 tg.config.add_word("DCU.D_SYNC_LOCAL_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SYNC_LOCAL_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_SYNC_ND_EN",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_SYNC_ND_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_TXPLL_PWDNB",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_TXPLL_PWDNB"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_D_SYNC_LOCAL_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_SYNC_ND_EN", parse_config_str(get_or_default(ci->params, id_D_SYNC_ND_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_TXPLL_PWDNB", parse_config_str(get_or_default(ci->params, id_D_TXPLL_PWDNB, Property(0)), 1));
 tg.config.add_word("DCU.D_TX_VCO_CK_DIV",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_TX_VCO_CK_DIV"), Property(0)), 3));
-tg.config.add_word("DCU.D_XGE_MODE",
-                   parse_config_str(get_or_default(ci->params, ctx->id("D_XGE_MODE"), Property(0)), 1));
+                   parse_config_str(get_or_default(ci->params, id_D_TX_VCO_CK_DIV, Property(0)), 3));
+tg.config.add_word("DCU.D_XGE_MODE", parse_config_str(get_or_default(ci->params, id_D_XGE_MODE, Property(0)), 1));
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index cc2208e00a..844c596b91 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -299,8 +299,8 @@ class Ecp5GlobalRouter
         dedicated_routing = false;
         if (drv.cell == nullptr) {
             return 0;
-        } else if (drv.cell->attrs.count(ctx->id("BEL"))) {
-            drv_bel = ctx->getBelByNameStr(drv.cell->attrs.at(ctx->id("BEL")).as_string());
+        } else if (drv.cell->attrs.count(id_BEL)) {
+            drv_bel = ctx->getBelByNameStr(drv.cell->attrs.at(id_BEL).as_string());
         } else {
             // Check if driver is a singleton
             BelId last_bel;
@@ -399,7 +399,7 @@ class Ecp5GlobalRouter
     {
         BelId best_bel;
         WireId best_bel_pclkcib;
-        bool using_ce = get_net_or_empty(dcc, ctx->id("CE")) != nullptr;
+        bool using_ce = get_net_or_empty(dcc, id_CE) != nullptr;
         wirelen_t best_wirelen = 9999999;
         bool dedicated_routing = false;
         for (auto bel : ctx->getBels()) {
@@ -492,8 +492,8 @@ class Ecp5GlobalRouter
             dccptr = dcc.get();
             ctx->cells[dcc->name] = std::move(dcc);
         }
-        glbptr->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1;
-        if (str_or_default(dccptr->attrs, ctx->id("BEL"), "") == "")
+        glbptr->attrs[id_ECP5_IS_GLOBAL] = 1;
+        if (str_or_default(dccptr->attrs, id_BEL, "") == "")
             place_dcc_dcs(dccptr);
         return glbptr;
     }
@@ -514,8 +514,8 @@ class Ecp5GlobalRouter
         log_info("Promoting globals...\n");
         auto clocks = get_clocks();
         for (auto clock : clocks) {
-            bool is_noglobal = bool_or_default(clock->attrs, ctx->id("noglobal"), false) ||
-                               bool_or_default(clock->attrs, ctx->id("ECP5_IS_GLOBAL"), false);
+            bool is_noglobal = bool_or_default(clock->attrs, id_noglobal, false) ||
+                               bool_or_default(clock->attrs, id_ECP5_IS_GLOBAL, false);
             if (is_noglobal)
                 continue;
             log_info("    promoting clock net %s to global network\n", clock->name.c_str(ctx));
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 3fd840cd5f..70ebfe81c3 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -134,7 +134,7 @@ bool Arch::apply_lpf(std::string filename, std::istream &in)
                         if (words.size() > 5)
                             log_error("unexpected input following LOCATE clause (on line %d)\n", lineno);
                         if (fnd_cell != cells.end()) {
-                            fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4));
+                            fnd_cell->second->attrs[id_LOC] = strip_quotes(words.at(4));
                         }
                     } else if (verb == "IOBUF") {
                         if (words.size() < 3)
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 1864548bac..f143d583c7 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -277,7 +277,7 @@ void ECP5CommandHandler::customAfterLoad(Context *ctx)
             CellInfo *ci = cell.second.get();
             if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") ||
                 ci->type == ctx->id("$nextpnr_iobuf")) {
-                if (!ci->attrs.count(ctx->id("LOC"))) {
+                if (!ci->attrs.count(id_LOC)) {
                     if (vm.count("lpf-allow-unconstrained"))
                         log_warning("IO '%s' is unconstrained in LPF and will be automatically placed\n",
                                     cell.first.c_str(ctx));
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 79644d1331..d49dbdf37b 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -108,11 +108,11 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
-                NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+                NetInfo *znet = ci->ports.at(id_Z).net;
                 if (znet != nullptr) {
-                    CellInfo *ff = net_only_drives(ctx, znet, is_ff, ctx->id("DI"), false);
+                    CellInfo *ff = net_only_drives(ctx, znet, is_ff, id_DI, false);
                     // Can't combine preload FF with LUT due to conflict on M
-                    if (ff != nullptr && get_net_or_empty(ff, ctx->id("M")) == nullptr) {
+                    if (ff != nullptr && get_net_or_empty(ff, id_M) == nullptr) {
                         lutffPairs[ci->name] = ff->name;
                         fflutPairs[ff->name] = ci->name;
                     }
@@ -134,13 +134,13 @@ class Ecp5Packer
     // Check if a flipflop can be added to a slice
     bool can_add_ff_to_slice(CellInfo *slice, CellInfo *ff)
     {
-        std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
-        std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
+        std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
+        std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
 
-        bool has_dpram = str_or_default(slice->params, ctx->id("MODE"), "LOGIC") == "DPRAM";
+        bool has_dpram = str_or_default(slice->params, id_MODE, "LOGIC") == "DPRAM";
         if (has_dpram) {
-            std::string wckmux = str_or_default(slice->params, ctx->id("WCKMUX"), "WCK");
-            std::string wremux = str_or_default(slice->params, ctx->id("WREMUX"), "WRE");
+            std::string wckmux = str_or_default(slice->params, id_WCKMUX, "WCK");
+            std::string wremux = str_or_default(slice->params, id_WREMUX, "WRE");
             if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
                 return false;
             if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
@@ -150,25 +150,22 @@ class Ecp5Packer
         bool has_ff1 = get_net_or_empty(slice, id_Q1) != nullptr;
         if (!has_ff0 && !has_ff1)
             return true;
-        if (str_or_default(ff->params, ctx->id("GSR"), "DISABLED") !=
-            str_or_default(slice->params, ctx->id("GSR"), "DISABLED"))
+        if (str_or_default(ff->params, id_GSR, "DISABLED") != str_or_default(slice->params, id_GSR, "DISABLED"))
             return false;
-        if (str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
-            str_or_default(slice->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+        if (str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE") !=
+            str_or_default(slice->params, id_SRMODE, "LSR_OVER_CE"))
             return false;
-        if (str_or_default(ff->params, ctx->id("CEMUX"), "1") != str_or_default(slice->params, ctx->id("CEMUX"), "1"))
+        if (str_or_default(ff->params, id_CEMUX, "1") != str_or_default(slice->params, id_CEMUX, "1"))
             return false;
-        if (str_or_default(ff->params, ctx->id("LSRMUX"), "LSR") !=
-            str_or_default(slice->params, ctx->id("LSRMUX"), "LSR"))
+        if (str_or_default(ff->params, id_LSRMUX, "LSR") != str_or_default(slice->params, id_LSRMUX, "LSR"))
             return false;
-        if (str_or_default(ff->params, ctx->id("CLKMUX"), "CLK") !=
-            str_or_default(slice->params, ctx->id("CLKMUX"), "CLK"))
+        if (str_or_default(ff->params, id_CLKMUX, "CLK") != str_or_default(slice->params, id_CLKMUX, "CLK"))
             return false;
-        if (net_or_nullptr(ff, ctx->id("CLK")) != net_or_nullptr(slice, ctx->id("CLK")))
+        if (net_or_nullptr(ff, id_CLK) != net_or_nullptr(slice, id_CLK))
             return false;
-        if (net_or_nullptr(ff, ctx->id("CE")) != net_or_nullptr(slice, ctx->id("CE")))
+        if (net_or_nullptr(ff, id_CE) != net_or_nullptr(slice, id_CE))
             return false;
-        if (net_or_nullptr(ff, ctx->id("LSR")) != net_or_nullptr(slice, ctx->id("LSR")))
+        if (net_or_nullptr(ff, id_LSR) != net_or_nullptr(slice, id_LSR))
             return false;
         return true;
     }
@@ -185,25 +182,22 @@ class Ecp5Packer
     // Return whether two FFs can be packed together in the same slice
     bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
     {
-        if (str_or_default(ff0->params, ctx->id("GSR"), "DISABLED") !=
-            str_or_default(ff1->params, ctx->id("GSR"), "DISABLED"))
+        if (str_or_default(ff0->params, id_GSR, "DISABLED") != str_or_default(ff1->params, id_GSR, "DISABLED"))
             return false;
-        if (str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
-            str_or_default(ff1->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+        if (str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE") !=
+            str_or_default(ff1->params, id_SRMODE, "LSR_OVER_CE"))
             return false;
-        if (str_or_default(ff0->params, ctx->id("CEMUX"), "1") != str_or_default(ff1->params, ctx->id("CEMUX"), "1"))
+        if (str_or_default(ff0->params, id_CEMUX, "1") != str_or_default(ff1->params, id_CEMUX, "1"))
             return false;
-        if (str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR") !=
-            str_or_default(ff1->params, ctx->id("LSRMUX"), "LSR"))
+        if (str_or_default(ff0->params, id_LSRMUX, "LSR") != str_or_default(ff1->params, id_LSRMUX, "LSR"))
             return false;
-        if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
-            str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
+        if (str_or_default(ff0->params, id_CLKMUX, "CLK") != str_or_default(ff1->params, id_CLKMUX, "CLK"))
             return false;
-        if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
+        if (net_or_nullptr(ff0, id_CLK) != net_or_nullptr(ff1, id_CLK))
             return false;
-        if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
+        if (net_or_nullptr(ff0, id_CE) != net_or_nullptr(ff1, id_CE))
             return false;
-        if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
+        if (net_or_nullptr(ff0, id_LSR) != net_or_nullptr(ff1, id_LSR))
             return false;
         return true;
     }
@@ -212,18 +206,16 @@ class Ecp5Packer
     bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
     {
         for (const auto &existing : tile_ffs) {
-            if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
+            if (net_or_nullptr(existing, id_CLK) != net_or_nullptr(ff0, id_CLK))
                 return false;
-            if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
+            if (net_or_nullptr(existing, id_LSR) != net_or_nullptr(ff0, id_LSR))
                 return false;
-            if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
-                str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
+            if (str_or_default(existing->params, id_CLKMUX, "CLK") != str_or_default(ff0->params, id_CLKMUX, "CLK"))
                 return false;
-            if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
-                str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
+            if (str_or_default(existing->params, id_LSRMUX, "LSR") != str_or_default(ff0->params, id_LSRMUX, "LSR"))
                 return false;
-            if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
-                str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+            if (str_or_default(existing->params, id_SRMODE, "LSR_OVER_CE") !=
+                str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE"))
                 return false;
         }
         return true;
@@ -232,14 +224,14 @@ class Ecp5Packer
     // Return true if a FF can be added to a DPRAM slice
     bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
     {
-        if (get_net_or_empty(ff, ctx->id("M")) != nullptr)
+        if (get_net_or_empty(ff, id_M) != nullptr)
             return false; // skip PRLD FFs due to M/DI conflict
-        std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
-        std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
+        std::string wckmux = str_or_default(dpram->params, id_WCKMUX, "WCK");
+        std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
         if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
             return false;
-        std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
-        std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
+        std::string wremux = str_or_default(dpram->params, id_WREMUX, "WRE");
+        std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
         if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
             return false;
         return true;
@@ -264,7 +256,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
-                NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+                NetInfo *znet = ci->ports.at(id_Z).net;
                 std::vector<NetInfo *> inpnets;
                 if (znet != nullptr) {
                     for (auto user : znet->users) {
@@ -284,7 +276,7 @@ class Ecp5Packer
                     }
                 }
                 if (lutffPairs.find(ci->name) != lutffPairs.end()) {
-                    NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(ctx->id("Q")).net;
+                    NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(id_Q).net;
                     if (qnet != nullptr) {
                         for (auto user : qnet->users) {
                             if (is_lut(ctx, user.cell) && user.cell != ci &&
@@ -309,7 +301,7 @@ class Ecp5Packer
                     NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
                     if (innet != nullptr && innet->driver.cell != nullptr) {
                         CellInfo *drv = innet->driver.cell;
-                        if (is_lut(ctx, drv) && drv != ci && innet->driver.port == ctx->id("Z")) {
+                        if (is_lut(ctx, drv) && drv != ci && innet->driver.port == id_Z) {
                             if (procdLuts.find(drv->name) == procdLuts.end()) {
                                 if (can_pack_lutff(ci->name, drv->name)) {
                                     procdLuts.insert(ci->name);
@@ -318,7 +310,7 @@ class Ecp5Packer
                                     goto paired_inlut;
                                 }
                             }
-                        } else if (is_ff(ctx, drv) && innet->driver.port == ctx->id("Q")) {
+                        } else if (is_ff(ctx, drv) && innet->driver.port == id_Q) {
                             auto fflut = fflutPairs.find(drv->name);
                             if (fflut != fflutPairs.end() && fflut->second != ci->name &&
                                 procdLuts.find(fflut->second) == procdLuts.end()) {
@@ -336,7 +328,7 @@ class Ecp5Packer
                 // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
                 if (znet != nullptr && znet->users.size() < 10) {
                     for (auto user : znet->users) {
-                        if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
+                        if (is_lc(ctx, user.cell) || user.cell->type == id_DP16KD || is_ff(ctx, user.cell)) {
                             for (auto port : user.cell->ports) {
                                 if (port.second.type != PORT_IN || port.second.net == nullptr ||
                                     port.second.net == znet)
@@ -449,12 +441,12 @@ class Ecp5Packer
                 NetInfo *ionet = nullptr;
                 PortRef tp;
                 if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
-                    ionet = ci->ports.at(ctx->id("O")).net;
-                    trio = net_only_drives(ctx, ionet, is_trellis_io, ctx->id("B"), true, ci);
+                    ionet = ci->ports.at(id_O).net;
+                    trio = net_only_drives(ctx, ionet, is_trellis_io, id_B, true, ci);
 
                 } else if (ci->type == ctx->id("$nextpnr_obuf")) {
-                    ionet = ci->ports.at(ctx->id("I")).net;
-                    trio = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_trellis_io, ctx->id("B"), true, ci);
+                    ionet = ci->ports.at(id_I).net;
+                    trio = net_only_drives(ctx, ci->ports.at(id_I).net, is_trellis_io, id_B, true, ci);
                 }
                 if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
                     // No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
@@ -466,18 +458,18 @@ class Ecp5Packer
                     log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
                              ci->type.c_str(ctx), ci->name.c_str(ctx));
 
-                    NetInfo *net = trio->ports.at(ctx->id("B")).net;
+                    NetInfo *net = trio->ports.at(id_B).net;
                     if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
                          net->users.size() > 1) ||
                         (ci->type == ctx->id("$nextpnr_obuf") &&
                          (net->users.size() > 2 || net->driver.cell != nullptr)) ||
-                        (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr &&
-                         ci->ports.at(ctx->id("I")).net->driver.cell != nullptr))
+                        (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(id_I).net != nullptr &&
+                         ci->ports.at(id_I).net->driver.cell != nullptr))
                         log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
                                   trio->type.c_str(ctx), trio->name.c_str(ctx));
                     if (net != nullptr) {
-                        if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) {
-                            NetInfo *onet = trio->ports.at(ctx->id("O")).net;
+                        if (net->clkconstr != nullptr && trio->ports.count(id_O)) {
+                            NetInfo *onet = trio->ports.at(id_O).net;
                             if (onet != nullptr && !onet->clkconstr) {
                                 // Move clock constraint from IO pad to input buffer output
                                 std::swap(net->clkconstr, onet->clkconstr);
@@ -492,7 +484,7 @@ class Ecp5Packer
                         tp.cell->ports.at(tp.port).net = nullptr;
                     }
                     if (ci->type == ctx->id("$nextpnr_iobuf")) {
-                        NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
+                        NetInfo *net2 = ci->ports.at(id_I).net;
                         if (net2 != nullptr) {
                             ctx->nets.erase(net2->name);
                         }
@@ -500,7 +492,7 @@ class Ecp5Packer
                 } else {
                     // Create a TRELLIS_IO buffer
                     std::unique_ptr<CellInfo> tr_cell =
-                            create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
+                            create_ecp5_cell(ctx, id_TRELLIS_IO, ci->name.str(ctx) + "$tr_io");
                     nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
                     new_cells.push_back(std::move(tr_cell));
                     trio = new_cells.back().get();
@@ -512,7 +504,7 @@ class Ecp5Packer
                     for (const auto &attr : ci->attrs)
                         trio->attrs[attr.first] = attr.second;
 
-                    auto loc_attr = trio->attrs.find(ctx->id("LOC"));
+                    auto loc_attr = trio->attrs.find(id_LOC);
                     if (loc_attr != trio->attrs.end()) {
                         std::string pin = loc_attr->second.as_string();
                         BelId pinBel = ctx->get_package_pin_bel(pin);
@@ -523,7 +515,7 @@ class Ecp5Packer
                             log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
                                      ctx->nameOfBel(pinBel));
                         }
-                        trio->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
+                        trio->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
                     }
                 }
             }
@@ -539,35 +531,33 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (is_pfumx(ctx, ci)) {
                 std::unique_ptr<CellInfo> packed =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
-                NetInfo *f0 = ci->ports.at(ctx->id("BLUT")).net;
+                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
+                NetInfo *f0 = ci->ports.at(id_BLUT).net;
                 if (f0 == nullptr)
                     log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
-                NetInfo *f1 = ci->ports.at(ctx->id("ALUT")).net;
+                NetInfo *f1 = ci->ports.at(id_ALUT).net;
                 if (f1 == nullptr)
                     log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
-                CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, ctx->id("Z"));
-                CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, ctx->id("Z"));
+                CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, id_Z);
+                CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, id_Z);
                 if (lut0 == nullptr)
                     log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
                 if (lut1 == nullptr)
                     log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
                 if (ctx->verbose)
                     log_info("   mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
-                replace_port(lut0, ctx->id("A"), packed.get(), ctx->id("A0"));
-                replace_port(lut0, ctx->id("B"), packed.get(), ctx->id("B0"));
-                replace_port(lut0, ctx->id("C"), packed.get(), ctx->id("C0"));
-                replace_port(lut0, ctx->id("D"), packed.get(), ctx->id("D0"));
-                replace_port(lut1, ctx->id("A"), packed.get(), ctx->id("A1"));
-                replace_port(lut1, ctx->id("B"), packed.get(), ctx->id("B1"));
-                replace_port(lut1, ctx->id("C"), packed.get(), ctx->id("C1"));
-                replace_port(lut1, ctx->id("D"), packed.get(), ctx->id("D1"));
-                replace_port(ci, ctx->id("C0"), packed.get(), ctx->id("M0"));
-                replace_port(ci, ctx->id("Z"), packed.get(), ctx->id("OFX0"));
-                packed->params[ctx->id("LUT0_INITVAL")] =
-                        get_or_default(lut0->params, ctx->id("INIT"), Property(0, 16));
-                packed->params[ctx->id("LUT1_INITVAL")] =
-                        get_or_default(lut1->params, ctx->id("INIT"), Property(0, 16));
+                replace_port(lut0, id_A, packed.get(), id_A0);
+                replace_port(lut0, id_B, packed.get(), id_B0);
+                replace_port(lut0, id_C, packed.get(), id_C0);
+                replace_port(lut0, id_D, packed.get(), id_D0);
+                replace_port(lut1, id_A, packed.get(), id_A1);
+                replace_port(lut1, id_B, packed.get(), id_B1);
+                replace_port(lut1, id_C, packed.get(), id_C1);
+                replace_port(lut1, id_D, packed.get(), id_D1);
+                replace_port(ci, id_C0, packed.get(), id_M0);
+                replace_port(ci, id_Z, packed.get(), id_OFX0);
+                packed->params[id_LUT0_INITVAL] = get_or_default(lut0->params, id_INIT, Property(0, 16));
+                packed->params[id_LUT1_INITVAL] = get_or_default(lut1->params, id_INIT, Property(0, 16));
 
                 ctx->nets.erase(f0->name);
                 ctx->nets.erase(f1->name);
@@ -595,17 +585,16 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx0_0 = ci->ports.at(ctx->id("D0")).net;
+                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
                 if (ofx0_0 == nullptr)
                     log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx0_1 = ci->ports.at(ctx->id("D1")).net;
+                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
                 if (ofx0_1 == nullptr)
                     log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX0"));
-                CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX0"));
+                CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, id_OFX0);
+                CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, id_OFX0);
                 if (slice0 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, ctx->id("Z")) &&
-                        !net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX1")))
+                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_0, is_lc, id_OFX1))
                         log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
                                   "('%s.%s')\n",
                                   ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
@@ -613,8 +602,7 @@ class Ecp5Packer
                     continue;
                 }
                 if (slice1 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, ctx->id("Z")) &&
-                        !net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX1")))
+                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_1, is_lc, id_OFX1))
                         log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
                                   "('%s.%s')\n",
                                   ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
@@ -623,10 +611,10 @@ class Ecp5Packer
                 }
                 if (ctx->verbose)
                     log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
-                replace_port(ci, ctx->id("D0"), slice1, id_FXA);
-                replace_port(ci, ctx->id("D1"), slice1, id_FXB);
-                replace_port(ci, ctx->id("SD"), slice1, id_M1);
-                replace_port(ci, ctx->id("Z"), slice1, id_OFX1);
+                replace_port(ci, id_D0, slice1, id_FXA);
+                replace_port(ci, id_D1, slice1, id_FXB);
+                replace_port(ci, id_SD, slice1, id_M1);
+                replace_port(ci, id_Z, slice1, id_OFX1);
                 slice0->constr_z = 1;
                 slice0->constr_x = 0;
                 slice0->constr_y = 0;
@@ -653,14 +641,14 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx1_0 = ci->ports.at(ctx->id("D0")).net;
+                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
                 if (ofx1_0 == nullptr)
                     log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx1_1 = ci->ports.at(ctx->id("D1")).net;
+                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
                 if (ofx1_1 == nullptr)
                     log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, ctx->id("OFX1"));
-                CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, ctx->id("OFX1"));
+                CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, id_OFX1);
+                CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, id_OFX1);
                 if (slice1 == nullptr)
                     log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
                               ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
@@ -677,8 +665,8 @@ class Ecp5Packer
                 if (fxa_1 == nullptr)
                     log_error("SLICE '%s' has disconnected port 'FXA'\n", slice3->name.c_str(ctx));
 
-                CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, ctx->id("OFX0"));
-                CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, ctx->id("OFX0"));
+                CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, id_OFX0);
+                CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, id_OFX0);
                 if (slice0 == nullptr)
                     log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
                               slice1->name.c_str(ctx), fxa_0->driver.cell->name.c_str(ctx),
@@ -688,10 +676,10 @@ class Ecp5Packer
                               slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
                               fxa_1->driver.port.c_str(ctx));
 
-                replace_port(ci, ctx->id("D0"), slice2, id_FXA);
-                replace_port(ci, ctx->id("D1"), slice2, id_FXB);
-                replace_port(ci, ctx->id("SD"), slice2, id_M1);
-                replace_port(ci, ctx->id("Z"), slice2, id_OFX1);
+                replace_port(ci, id_D0, slice2, id_FXA);
+                replace_port(ci, id_D1, slice2, id_FXB);
+                replace_port(ci, id_SD, slice2, id_M1);
+                replace_port(ci, id_Z, slice2, id_OFX1);
 
                 for (auto slice : {slice0, slice1, slice2, slice3}) {
                     slice->constr_children.clear();
@@ -747,12 +735,12 @@ class Ecp5Packer
     // Create a feed in to the carry chain
     CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
     {
-        std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+        std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, id_CCU2C);
 
-        feedin->params[ctx->id("INIT0")] = Property(10, 16); // LUT4 = 0; LUT2 = A
-        feedin->params[ctx->id("INIT1")] = Property(65535, 16);
-        feedin->params[ctx->id("INJECT1_0")] = std::string("NO");
-        feedin->params[ctx->id("INJECT1_1")] = std::string("YES");
+        feedin->params[id_INIT0] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedin->params[id_INIT1] = Property(65535, 16);
+        feedin->params[id_INJECT1_0] = std::string("NO");
+        feedin->params[id_INJECT1_1] = std::string("YES");
 
         carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
                                           [chain_in](const PortRef &user) {
@@ -762,7 +750,7 @@ class Ecp5Packer
         connect_port(ctx, carry, feedin.get(), id_A0);
 
         NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
-        connect_port(ctx, new_carry, feedin.get(), ctx->id("COUT"));
+        connect_port(ctx, new_carry, feedin.get(), id_COUT);
         chain_in.cell->ports[chain_in.port].net = nullptr;
         connect_port(ctx, new_carry, chain_in.cell, chain_in.port);
 
@@ -775,21 +763,21 @@ class Ecp5Packer
     // Create a feed out and loop through from the carry chain
     CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
     {
-        std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+        std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, id_CCU2C);
 
-        feedout->params[ctx->id("INIT0")] = Property(0, 16);
-        feedout->params[ctx->id("INIT1")] = Property(10, 16); // LUT4 = 0; LUT2 = A
-        feedout->params[ctx->id("INJECT1_0")] = std::string("NO");
-        feedout->params[ctx->id("INJECT1_1")] = std::string("NO");
+        feedout->params[id_INIT0] = Property(0, 16);
+        feedout->params[id_INIT1] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedout->params[id_INJECT1_0] = std::string("NO");
+        feedout->params[id_INJECT1_1] = std::string("NO");
 
         PortRef carry_drv = carry->driver;
         carry->driver.cell = nullptr;
-        connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
+        connect_port(ctx, carry, feedout.get(), id_S0);
 
         NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
         new_cin->driver = carry_drv;
         carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
-        connect_port(ctx, new_cin, feedout.get(), ctx->id("CIN"));
+        connect_port(ctx, new_cin, feedout.get(), id_CIN);
 
         if (chain_next) {
             // Loop back into LUT4_1 for feedthrough
@@ -802,7 +790,7 @@ class Ecp5Packer
                                carry->users.end());
 
             NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
-            connect_port(ctx, new_cout, feedout.get(), ctx->id("COUT"));
+            connect_port(ctx, new_cout, feedout.get(), id_COUT);
 
             chain_next->cell->ports[chain_next->port].net = nullptr;
             connect_port(ctx, new_cout, chain_next->cell, chain_next->port);
@@ -827,23 +815,23 @@ class Ecp5Packer
             if (start_of_chain) {
                 chains.emplace_back();
                 start_of_chain = false;
-                if (cell->ports.at(ctx->id("CIN")).net) {
+                if (cell->ports.at(id_CIN).net) {
                     // CIN is not constant and not part of a chain. Must feed in from fabric
                     PortRef inport;
                     inport.cell = cell;
-                    inport.port = ctx->id("CIN");
-                    CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
+                    inport.port = id_CIN;
+                    CellInfo *feedin = make_carry_feed_in(cell->ports.at(id_CIN).net, inport);
                     chains.back().cells.push_back(feedin);
                 }
             }
             chains.back().cells.push_back(cell);
             bool split_chain = int(chains.back().cells.size()) > max_length;
             if (split_chain) {
-                CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
+                CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net);
                 chains.back().cells.back() = passout;
                 start_of_chain = true;
             } else {
-                NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
+                NetInfo *carry_net = cell->ports.at(id_COUT).net;
                 bool at_end = (curr_cell == carryc.cells.end() - 1);
                 if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
                     boost::optional<PortRef> nextport;
@@ -851,10 +839,10 @@ class Ecp5Packer
                         auto next_cell = *(curr_cell + 1);
                         PortRef nextpr;
                         nextpr.cell = next_cell;
-                        nextpr.port = ctx->id("CIN");
+                        nextpr.port = id_CIN;
                         nextport = nextpr;
                     }
-                    CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
+                    CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net, nextport);
                     chains.back().cells.push_back(passout);
                 }
                 ++curr_cell;
@@ -871,10 +859,10 @@ class Ecp5Packer
         auto carry_chains = find_chains(
                 ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
                 [](const Context *ctx, const CellInfo *cell) {
-                    return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
+                    return net_driven_by(ctx, cell->ports.at(id_CIN).net, is_carry, id_COUT);
                 },
                 [](const Context *ctx, const CellInfo *cell) {
-                    return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
+                    return net_only_drives(ctx, cell->ports.at(id_COUT).net, is_carry, id_CIN, false);
                 },
                 1);
         std::vector<CellChain> all_chains;
@@ -905,14 +893,14 @@ class Ecp5Packer
                 if (cell_count % 4 == 0)
                     tile_ffs.clear();
                 std::unique_ptr<CellInfo> slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
+                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, cell->name.str(ctx) + "$CCU2_SLICE");
 
                 ccu2c_to_slice(ctx, cell, slice.get());
 
                 CellInfo *ff0 = nullptr;
-                NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+                NetInfo *f0net = slice->ports.at(id_F0).net;
                 if (f0net != nullptr) {
-                    ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+                    ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
                     if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
                         ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
                         tile_ffs.push_back(ff0);
@@ -921,9 +909,9 @@ class Ecp5Packer
                 }
 
                 CellInfo *ff1 = nullptr;
-                NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+                NetInfo *f1net = slice->ports.at(id_F1).net;
                 if (f1net != nullptr) {
-                    ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+                    ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
                     if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
                         can_add_ff_to_tile(tile_ffs, ff1)) {
                         ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
@@ -969,16 +957,16 @@ class Ecp5Packer
 
                 // Create RAMW slice
                 std::unique_ptr<CellInfo> ramw_slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
+                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$RAMW_SLICE");
                 dram_to_ramw(ctx, ci, ramw_slice.get());
 
                 // Create actual RAM slices
                 std::unique_ptr<CellInfo> ram0_slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
+                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM0_SLICE");
                 dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
 
                 std::unique_ptr<CellInfo> ram1_slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
+                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM1_SLICE");
                 dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
 
                 // Disconnect ports of original cell after packing
@@ -995,9 +983,9 @@ class Ecp5Packer
                 std::vector<CellInfo *> tile_ffs;
                 for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
                     CellInfo *ff0 = nullptr;
-                    NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+                    NetInfo *f0net = slice->ports.at(id_F0).net;
                     if (f0net != nullptr) {
-                        ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+                        ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
                         if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
                             if (can_pack_ff_dram(slice, ff0)) {
                                 ff_packing.push_back(std::make_tuple(ff0, slice, 0));
@@ -1008,9 +996,9 @@ class Ecp5Packer
                     }
 
                     CellInfo *ff1 = nullptr;
-                    NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+                    NetInfo *f1net = slice->ports.at(id_F1).net;
                     if (f1net != nullptr) {
-                        ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+                        ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
                         if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
                             can_add_ff_to_tile(tile_ffs, ff1)) {
                             if (can_pack_ff_dram(slice, ff1)) {
@@ -1060,8 +1048,7 @@ class Ecp5Packer
         for (auto pair : lutPairs) {
             CellInfo *lut0 = ctx->cells.at(pair.first).get();
             CellInfo *lut1 = ctx->cells.at(pair.second).get();
-            std::unique_ptr<CellInfo> slice =
-                    create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), lut0->name.str(ctx) + "_SLICE");
+            std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, lut0->name.str(ctx) + "_SLICE");
 
             lut_to_slice(ctx, lut0, slice.get(), 0);
             lut_to_slice(ctx, lut1, slice.get(), 1);
@@ -1099,8 +1086,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_lut(ctx, ci)) {
-                std::unique_ptr<CellInfo> slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
+                std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
                 lut_to_slice(ctx, ci, slice.get(), 1);
                 auto ff = lutffPairs.find(ci->name);
 
@@ -1173,7 +1159,7 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (is_ff(ctx, ci)) {
                 bool pack_dense = used_slices > (dense_pack_mode_thresh * available_slices);
-                bool requires_m = get_net_or_empty(ci, ctx->id("M")) != nullptr;
+                bool requires_m = get_net_or_empty(ci, id_M) != nullptr;
                 if (pack_dense && !requires_m) {
                     // If dense packing threshold exceeded; always try and pack the FF into an existing slice
                     // Find a SLICE with space "near" the flipflop in the netlist
@@ -1222,8 +1208,7 @@ class Ecp5Packer
                     }
                 }
 
-                std::unique_ptr<CellInfo> slice =
-                        create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
+                std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
                 ff_to_slice(ctx, ci, slice.get(), 0, false);
                 new_cells.push_back(std::move(slice));
                 ++used_slices;
@@ -1252,9 +1237,9 @@ class Ecp5Packer
     void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
     {
         int index = std::string("ABCD").find(input.str(ctx));
-        int init = int_or_default(cell->params, ctx->id("INIT"));
+        int init = int_or_default(cell->params, id_INIT);
         int new_init = make_init_with_const_input(init, index, value);
-        cell->params[ctx->id("INIT")] = Property(new_init, 16);
+        cell->params[id_INIT] = Property(new_init, 16);
         cell->ports.at(input).net = nullptr;
     }
 
@@ -1275,8 +1260,7 @@ class Ecp5Packer
             return true; // disconnected port is high
         if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
             return true; // disconnected or tied-high port
-        if (cell->ports.at(input).net->driver.cell != nullptr &&
-            cell->ports.at(input).net->driver.cell->type == ctx->id("VCC"))
+        if (cell->ports.at(input).net->driver.cell != nullptr && cell->ports.at(input).net->driver.cell->type == id_VCC)
             return true; // pre-pack high
         return false;
     }
@@ -1292,8 +1276,8 @@ class Ecp5Packer
                     log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
                 if (is_lut(ctx, uc)) {
                     set_lut_input_constant(uc, user.port, constval);
-                } else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
-                    uc->params[ctx->id("CEMUX")] = std::string(constval ? "1" : "0");
+                } else if (is_ff(ctx, uc) && user.port == id_CE) {
+                    uc->params[id_CEMUX] = std::string(constval ? "1" : "0");
                     uc->ports[user.port].net = nullptr;
                 } else if (is_carry(ctx, uc)) {
                     if (constval &&
@@ -1326,9 +1310,9 @@ class Ecp5Packer
                         uc->ports[user.port].net = constnet;
                         constnet->users.push_back(user);
                     }
-                } else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
-                           ((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
-                            (constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
+                } else if (is_ff(ctx, uc) && user.port == id_LSR &&
+                           ((!constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "LSR") ||
+                            (constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "INV"))) {
                     uc->ports[user.port].net = nullptr;
                 } else if (uc->type == id_DP16KD) {
                     if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
@@ -1371,19 +1355,19 @@ class Ecp5Packer
     {
         log_info("Packing constants..\n");
 
-        std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
-        gnd_cell->params[ctx->id("INIT")] = Property(0, 16);
+        std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, id_LUT4, "$PACKER_GND");
+        gnd_cell->params[id_INIT] = Property(0, 16);
         auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
         gnd_net->driver.cell = gnd_cell.get();
-        gnd_net->driver.port = ctx->id("Z");
-        gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
+        gnd_net->driver.port = id_Z;
+        gnd_cell->ports.at(id_Z).net = gnd_net.get();
 
-        std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
-        vcc_cell->params[ctx->id("INIT")] = Property(65535, 16);
+        std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, id_LUT4, "$PACKER_VCC");
+        vcc_cell->params[id_INIT] = Property(65535, 16);
         auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
         vcc_net->driver.cell = vcc_cell.get();
-        vcc_net->driver.port = ctx->id("Z");
-        vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
+        vcc_net->driver.port = id_Z;
+        vcc_cell->ports.at(id_Z).net = vcc_net.get();
 
         std::vector<IdString> dead_nets;
 
@@ -1391,13 +1375,13 @@ class Ecp5Packer
 
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
-            if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+            if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
                 IdString drv_cell = ni->driver.cell->name;
                 set_net_constant(ctx, ni, gnd_net.get(), false);
                 gnd_used = true;
                 dead_nets.push_back(net.first);
                 ctx->cells.erase(drv_cell);
-            } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+            } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
                 IdString drv_cell = ni->driver.cell->name;
                 set_net_constant(ctx, ni, vcc_net.get(), true);
                 vcc_used = true;
@@ -1450,9 +1434,9 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             // Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
-            if (ci->type == ctx->id("PDPW16KD")) {
-                ci->params[ctx->id("DATA_WIDTH_A")] = 36; // force PDP mode
-                ci->params.erase(ctx->id("DATA_WIDTH_W"));
+            if (ci->type == id_PDPW16KD) {
+                ci->params[id_DATA_WIDTH_A] = 36; // force PDP mode
+                ci->params.erase(id_DATA_WIDTH_W);
                 rename_bus(ci, "BE", "ADA", 4, 0, 0);
                 rename_bus(ci, "ADW", "ADA", 9, 0, 5);
                 rename_bus(ci, "ADR", "ADB", 14, 0, 0);
@@ -1462,23 +1446,23 @@ class Ecp5Packer
                 rename_bus(ci, "DI", "DIB", 18, 18, 0);
                 rename_bus(ci, "DO", "DOA", 18, 18, 0);
                 rename_bus(ci, "DO", "DOB", 18, 0, 0);
-                rename_port(ctx, ci, ctx->id("CLKW"), ctx->id("CLKA"));
-                rename_port(ctx, ci, ctx->id("CLKR"), ctx->id("CLKB"));
-                rename_port(ctx, ci, ctx->id("CEW"), ctx->id("CEA"));
-                rename_port(ctx, ci, ctx->id("CER"), ctx->id("CEB"));
-                rename_port(ctx, ci, ctx->id("OCER"), ctx->id("OCEB"));
+                rename_port(ctx, ci, id_CLKW, id_CLKA);
+                rename_port(ctx, ci, id_CLKR, id_CLKB);
+                rename_port(ctx, ci, id_CEW, id_CEA);
+                rename_port(ctx, ci, id_CER, id_CEB);
+                rename_port(ctx, ci, id_OCER, id_OCEB);
                 rename_param(ci, "CLKWMUX", "CLKAMUX");
-                if (str_or_default(ci->params, ctx->id("CLKAMUX")) == "CLKW")
-                    ci->params[ctx->id("CLKAMUX")] = std::string("CLKA");
-                if (str_or_default(ci->params, ctx->id("CLKBMUX")) == "CLKR")
-                    ci->params[ctx->id("CLKBMUX")] = std::string("CLKB");
+                if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
+                    ci->params[id_CLKAMUX] = std::string("CLKA");
+                if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
+                    ci->params[id_CLKBMUX] = std::string("CLKB");
                 rename_param(ci, "CLKRMUX", "CLKRMUX");
                 rename_param(ci, "CSDECODE_W", "CSDECODE_A");
                 rename_param(ci, "CSDECODE_R", "CSDECODE_B");
-                std::string outreg = str_or_default(ci->params, ctx->id("REGMODE"), "NOREG");
-                ci->params[ctx->id("REGMODE_A")] = outreg;
-                ci->params[ctx->id("REGMODE_B")] = outreg;
-                ci->params.erase(ctx->id("REGMODE"));
+                std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
+                ci->params[id_REGMODE_A] = outreg;
+                ci->params[id_REGMODE_B] = outreg;
+                ci->params.erase(id_REGMODE);
                 rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
                 if (ci->ports.count(id_RST)) {
                     autocreate_empty_port(ci, id_RSTA);
@@ -1525,7 +1509,7 @@ class Ecp5Packer
                 autocreate_empty_port(ci, id_WEB);
                 autocreate_empty_port(ci, id_RSTB);
 
-                ci->attrs[ctx->id("WID")] = wid++;
+                ci->attrs[id_WID] = wid++;
             }
         }
     }
@@ -1615,9 +1599,9 @@ class Ecp5Packer
 
         // Placement doesn't work if only one or the other of
         // the ALU and MULTs have a BEL specified.
-        auto alu_has_bel = alu->attrs.count(ctx->id("BEL"));
+        auto alu_has_bel = alu->attrs.count(id_BEL);
         for (auto mult : {mult_a, mult_b}) {
-            auto mult_has_bel = mult->attrs.count(ctx->id("BEL"));
+            auto mult_has_bel = mult->attrs.count(id_BEL);
             if (alu_has_bel && !mult_has_bel) {
                 log_error("ALU54B '%s' has a fixed BEL specified, but connected "
                           "MULT18X18D '%s' does not, specify both or neither.\n",
@@ -1632,8 +1616,8 @@ class Ecp5Packer
         // Cannot have MULT OUTPUT_CLK set when connected to an ALU unless
         // MULT_BYPASS is also enabled.
         for (auto mult : {mult_a, mult_b}) {
-            if (str_or_default(mult->params, ctx->id("REG_OUTPUT_CLK"), "NONE") != "NONE" &&
-                str_or_default(mult->params, ctx->id("MULT_BYPASS"), "DISABLED") != "ENABLED") {
+            if (str_or_default(mult->params, id_REG_OUTPUT_CLK, "NONE") != "NONE" &&
+                str_or_default(mult->params, id_MULT_BYPASS, "DISABLED") != "ENABLED") {
                 log_error("MULT18X18D '%s' REG_OUTPUT_CLK must be NONE when driving ALU without MULT_BYPASS\n",
                           mult->name.c_str(ctx));
             }
@@ -1700,27 +1684,27 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_DCUA) {
-                if (ci->attrs.count(ctx->id("LOC"))) {
-                    std::string loc = ci->attrs.at(ctx->id("LOC")).as_string();
+                if (ci->attrs.count(id_LOC)) {
+                    std::string loc = ci->attrs.at(id_LOC).as_string();
                     if (loc == "DCU0" &&
                         (ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F))
-                        ci->attrs[ctx->id("BEL")] = std::string("X42/Y50/DCU");
+                        ci->attrs[id_BEL] = std::string("X42/Y50/DCU");
                     else if (loc == "DCU0" &&
                              (ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
-                        ci->attrs[ctx->id("BEL")] = std::string("X42/Y71/DCU");
+                        ci->attrs[id_BEL] = std::string("X42/Y71/DCU");
                     else if (loc == "DCU1" &&
                              (ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
-                        ci->attrs[ctx->id("BEL")] = std::string("X69/Y71/DCU");
+                        ci->attrs[id_BEL] = std::string("X69/Y71/DCU");
                     else if (loc == "DCU0" &&
                              (ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
-                        ci->attrs[ctx->id("BEL")] = std::string("X46/Y95/DCU");
+                        ci->attrs[id_BEL] = std::string("X46/Y95/DCU");
                     else if (loc == "DCU1" &&
                              (ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
-                        ci->attrs[ctx->id("BEL")] = std::string("X71/Y95/DCU");
+                        ci->attrs[id_BEL] = std::string("X71/Y95/DCU");
                     else
                         log_error("no DCU location '%s' in device '%s'\n", loc.c_str(), ctx->getChipName().c_str());
                 }
-                if (!ci->attrs.count(ctx->id("BEL")))
+                if (!ci->attrs.count(id_BEL))
                     log_error("DCU must be constrained to a Bel!\n");
                 // Empty port auto-creation to generate correct tie-downs
                 BelId exemplar_bel;
@@ -1741,7 +1725,7 @@ class Ecp5Packer
                     if (net == nullptr || net->driver.cell == nullptr)
                         continue;
                     IdString ct = net->driver.cell->type;
-                    if (ct == ctx->id("GND") || ct == ctx->id("VCC")) {
+                    if (ct == id_GND || ct == id_VCC) {
                         disconnect_port(ctx, ci, ndport);
                         ci->ports.erase(ndport);
                     }
@@ -1755,8 +1739,8 @@ class Ecp5Packer
                 CellInfo *dcu = nullptr;
                 std::string loc_bel = std::string("NONE");
                 std::string dcu_bel = std::string("NONE");
-                if (ci->attrs.count(ctx->id("LOC"))) {
-                    std::string loc = ci->attrs.at(ctx->id("LOC")).as_string();
+                if (ci->attrs.count(id_LOC)) {
+                    std::string loc = ci->attrs.at(id_LOC).as_string();
                     if (loc == "EXTREF0" &&
                         (ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F))
                         loc_bel = std::string("X42/Y50/EXTREF");
@@ -1783,9 +1767,9 @@ class Ecp5Packer
                     dcu = user.cell;
                 }
                 if (dcu != nullptr) {
-                    if (!dcu->attrs.count(ctx->id("BEL")))
+                    if (!dcu->attrs.count(id_BEL))
                         log_error("DCU must be constrained to a Bel!\n");
-                    dcu_bel = dcu->attrs.at(ctx->id("BEL")).as_string();
+                    dcu_bel = dcu->attrs.at(id_BEL).as_string();
                     NPNR_ASSERT(dcu_bel.substr(dcu_bel.length() - 3) == "DCU");
                     dcu_bel.replace(dcu_bel.length() - 3, 3, "EXTREF");
                 }
@@ -1793,10 +1777,10 @@ class Ecp5Packer
                     if (dcu_bel == "NONE" && loc_bel == "NONE") {
                         log_error("EXTREFB has neither a LOC or a directly associated DCUA\n");
                     } else if (dcu_bel == "NONE") {
-                        ci->attrs[ctx->id("BEL")] = loc_bel;
+                        ci->attrs[id_BEL] = loc_bel;
                         dcu_bel = loc_bel;
                     } else if (loc_bel == "NONE") {
-                        ci->attrs[ctx->id("BEL")] = dcu_bel;
+                        ci->attrs[id_BEL] = dcu_bel;
                     } else {
                         log_error("EXTREFB has conflicting LOC '%s' and associated DCUA '%s'\n", loc_bel.c_str(),
                                   dcu_bel.c_str());
@@ -1804,17 +1788,17 @@ class Ecp5Packer
                 } else {
                     if (dcu_bel == "NONE")
                         log_error("EXTREFB has no LOC or associated DCUA\n");
-                    ci->attrs[ctx->id("BEL")] = dcu_bel;
+                    ci->attrs[id_BEL] = dcu_bel;
                 }
             } else if (ci->type == id_PCSCLKDIV) {
                 const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
                 if (clki != nullptr && clki->driver.cell != nullptr && clki->driver.cell->type == id_DCUA) {
                     CellInfo *dcu = clki->driver.cell;
-                    if (!dcu->attrs.count(ctx->id("BEL")))
+                    if (!dcu->attrs.count(id_BEL))
                         log_error("DCU must be constrained to a Bel!\n");
-                    BelId bel = ctx->getBelByNameStr(dcu->attrs.at(ctx->id("BEL")).as_string());
+                    BelId bel = ctx->getBelByNameStr(dcu->attrs.at(id_BEL).as_string());
                     if (bel == BelId())
-                        log_error("Invalid DCU bel '%s'\n", dcu->attrs.at(ctx->id("BEL")).c_str());
+                        log_error("Invalid DCU bel '%s'\n", dcu->attrs.at(id_BEL).c_str());
                     Loc loc = ctx->getBelLocation(bel);
                     // DCU0 -> CLKDIV z=0; DCU1 -> CLKDIV z=1
                     ci->constr_abs_z = true;
@@ -1830,18 +1814,17 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_USRMCLK) {
-                rename_port(ctx, ci, ctx->id("USRMCLKI"), id_PADDO);
-                rename_port(ctx, ci, ctx->id("USRMCLKTS"), id_PADDT);
-                rename_port(ctx, ci, ctx->id("USRMCLKO"), id_PADDI);
-            } else if (ci->type == id_GSR || ci->type == ctx->id("SGSR")) {
-                ci->params[ctx->id("MODE")] = std::string("ACTIVE_LOW");
-                ci->params[ctx->id("SYNCMODE")] =
-                        ci->type == ctx->id("SGSR") ? std::string("SYNC") : std::string("ASYNC");
+                rename_port(ctx, ci, id_USRMCLKI, id_PADDO);
+                rename_port(ctx, ci, id_USRMCLKTS, id_PADDT);
+                rename_port(ctx, ci, id_USRMCLKO, id_PADDI);
+            } else if (ci->type == id_GSR || ci->type == id_SGSR) {
+                ci->params[id_MODE] = std::string("ACTIVE_LOW");
+                ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC");
                 ci->type = id_GSR;
                 for (BelId bel : ctx->getBels()) {
                     if (ctx->getBelType(bel) != id_GSR)
                         continue;
-                    ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                    ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                     ctx->gsrclk_wire = ctx->getBelPinWire(bel, id_CLK);
                 }
             }
@@ -1858,20 +1841,20 @@ class Ecp5Packer
         }
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLL && ci->attrs.count(ctx->id("BEL")))
-                available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(ctx->id("BEL")).as_string()));
+            if (ci->type == id_EHXPLLL && ci->attrs.count(id_BEL))
+                available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(id_BEL).as_string()));
         }
         // Place PLL connected to fixed drivers such as IO close to their source
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
+            if (ci->type == id_EHXPLLL && !ci->attrs.count(id_BEL)) {
                 const NetInfo *drivernet = net_or_nullptr(ci, id_CLKI);
                 if (drivernet == nullptr || drivernet->driver.cell == nullptr)
                     continue;
                 const CellInfo *drivercell = drivernet->driver.cell;
-                if (!drivercell->attrs.count(ctx->id("BEL")))
+                if (!drivercell->attrs.count(id_BEL))
                     continue;
-                BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(ctx->id("BEL")).as_string());
+                BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(id_BEL).as_string());
                 Loc drvloc = ctx->getBelLocation(drvbel);
                 BelId closest_pll;
                 int closest_distance = std::numeric_limits<int>::max();
@@ -1886,18 +1869,18 @@ class Ecp5Packer
                 if (closest_pll == BelId())
                     log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
                 available_plls.erase(closest_pll);
-                ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest_pll).str(ctx);
+                ci->attrs[id_BEL] = ctx->getBelName(closest_pll).str(ctx);
             }
         }
         // Place PLLs driven by logic, etc, randomly
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
+            if (ci->type == id_EHXPLLL && !ci->attrs.count(id_BEL)) {
                 if (available_plls.empty())
                     log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
                 BelId next_pll = *(available_plls.begin());
                 available_plls.erase(next_pll);
-                ci->attrs[ctx->id("BEL")] = ctx->getBelName(next_pll).str(ctx);
+                ci->attrs[id_BEL] = ctx->getBelName(next_pll).str(ctx);
             }
         }
     }
@@ -1907,7 +1890,7 @@ class Ecp5Packer
     {
         if (a->driver.cell == nullptr || b->driver.cell == nullptr)
             return (a->driver.cell == nullptr && b->driver.cell == nullptr);
-        if (a->driver.cell->type != ctx->id("GND") && a->driver.cell->type != ctx->id("VCC"))
+        if (a->driver.cell->type != id_GND && a->driver.cell->type != id_VCC)
             return false;
         return a->driver.cell->type == b->driver.cell->type;
     }
@@ -1955,7 +1938,7 @@ class Ecp5Packer
                                            std::to_string(free_eclk));
 
                 NetInfo *promoted_ecknet = ctx->createNet(eckname);
-                promoted_ecknet->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1; // Prevents router etc touching this special net
+                promoted_ecknet->attrs[id_ECP5_IS_GLOBAL] = 1; // Prevents router etc touching this special net
                 eclk.buf = promoted_ecknet;
 
                 // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
@@ -1974,7 +1957,7 @@ class Ecp5Packer
                 }
                 NPNR_ASSERT(target_bel != BelId());
 
-                eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
+                eclkbuf->attrs[id_BEL] = ctx->getBelName(target_bel).str(ctx);
 
                 connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
                 connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
@@ -2038,10 +2021,10 @@ class Ecp5Packer
         }
         IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
 
-        auto zero_cell = std::make_unique<CellInfo>(ctx, name, ctx->id("GND"));
+        auto zero_cell = std::make_unique<CellInfo>(ctx, name, id_GND);
         NetInfo *zero_net = ctx->createNet(name);
-        zero_cell->addOutput(ctx->id("GND"));
-        connect_port(ctx, zero_net, zero_cell.get(), ctx->id("GND"));
+        zero_cell->addOutput(id_GND);
+        connect_port(ctx, zero_net, zero_cell.get(), id_GND);
         connect_port(ctx, zero_net, ci, port);
         new_cells.push_back(std::move(zero_cell));
     }
@@ -2053,15 +2036,15 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_DQSBUFM) {
-                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_DQSI).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(id_DQSI).net->users.size() > 1)
                     log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
-                if (!pio->attrs.count(ctx->id("BEL")))
+                if (!pio->attrs.count(id_BEL))
                     log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
                               "(while processing '%s').\n",
                               ci->name.c_str(ctx));
-                BelId pio_bel = ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string());
+                BelId pio_bel = ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string());
                 NPNR_ASSERT(pio_bel != BelId());
                 Loc pio_loc = ctx->getBelLocation(pio_bel);
                 if (pio_loc.z != 0)
@@ -2072,7 +2055,7 @@ class Ecp5Packer
                 if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
                     log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
                               ctx->nameOfBel(pio_bel));
-                ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
+                ci->attrs[id_BEL] = ctx->getBelName(dqsbuf).str(ctx);
                 bool got_dqsg =
                         ctx->get_pio_dqs_group(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
                 NPNR_ASSERT(got_dqsg);
@@ -2088,15 +2071,14 @@ class Ecp5Packer
                     if (pn == nullptr)
                         continue;
                     for (auto &usr : pn->users) {
-                        if (usr.port != port ||
-                            (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
-                             usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
-                             usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
+                        if (usr.port != port || (usr.cell->type != id_ODDRX2DQA && usr.cell->type != id_ODDRX2DQSB &&
+                                                 usr.cell->type != id_TSHX2DQSA && usr.cell->type != id_IDDRX2DQA &&
+                                                 usr.cell->type != id_TSHX2DQA && usr.cell->type != id_IOLOGIC))
                             log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
                                       port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
                                       usr.cell->name.c_str(ctx));
                     }
-                    pn->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1;
+                    pn->attrs[id_ECP5_IS_GLOBAL] = 1;
                 }
 
                 for (auto zport :
@@ -2146,9 +2128,9 @@ class Ecp5Packer
             if (prim->ports.count(port))
                 sclk = prim->ports[port].net;
             if (sclk == nullptr) {
-                iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("0");
+                iol->params[input ? id_CLKIMUX : id_CLKOMUX] = std::string("0");
             } else {
-                iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("CLK");
+                iol->params[input ? id_CLKIMUX : id_CLKOMUX] = std::string("CLK");
                 if (iol->ports[id_CLK].net != nullptr) {
                     if (iol->ports[id_CLK].net != sclk && !equal_constant(iol->ports[id_CLK].net, sclk))
                         log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx),
@@ -2184,9 +2166,9 @@ class Ecp5Packer
             if (prim->ports.count(port))
                 lsr = prim->ports[port].net;
             if (lsr == nullptr) {
-                iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("0");
+                iol->params[input ? id_LSRIMUX : id_LSROMUX] = std::string("0");
             } else {
-                iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("LSRMUX");
+                iol->params[input ? id_LSRIMUX : id_LSROMUX] = std::string("LSRMUX");
                 if (iol->ports[id_LSR].net != nullptr && !equal_constant(iol->ports[id_LSR].net, lsr)) {
                     if (iol->ports[id_LSR].net != lsr)
                         log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
@@ -2202,7 +2184,7 @@ class Ecp5Packer
         bool warned_oddrx_iddrx = false;
 
         auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
-            auto &curr_mode = iol->params[ctx->id("MODE")].str;
+            auto &curr_mode = iol->params[id_MODE].str;
             if (curr_mode != "NONE" && mode == "IREG_OREG")
                 return;
             if ((curr_mode == "IDDRXN" && mode == "ODDRXN") || (curr_mode == "ODDRXN" && mode == "IDDRXN")) {
@@ -2223,11 +2205,11 @@ class Ecp5Packer
         };
 
         auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
-            if (!pio->attrs.count(ctx->id("BEL")))
+            if (!pio->attrs.count(id_BEL))
                 log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
                           "(while processing '%s').\n",
                           curr->name.c_str(ctx));
-            BelId bel = ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string());
+            BelId bel = ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string());
             NPNR_ASSERT(bel != BelId());
             return bel;
         };
@@ -2243,7 +2225,7 @@ class Ecp5Packer
                     create_ecp5_cell(ctx, s ? id_SIOLOGIC : id_IOLOGIC, pio->name.str(ctx) + "$IOL");
 
             loc.z += s ? 2 : 4;
-            iol->attrs[ctx->id("BEL")] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
+            iol->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
 
             CellInfo *iol_ptr = iol.get();
             pio_iologic[pio->name] = iol_ptr;
@@ -2287,22 +2269,21 @@ class Ecp5Packer
 
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
-                CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
-                CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
+            if (ci->type == id_DELAYF || ci->type == id_DELAYG) {
+                CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(id_A).net, is_trellis_io, id_O);
+                CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(id_Z).net, is_trellis_io, id_I, true);
                 CellInfo *iol = nullptr;
-                if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
+                if (i_pio != nullptr && ci->ports.at(id_A).net->users.size() == 1) {
                     iol = create_pio_iologic(i_pio, ci);
                     set_iologic_mode(iol, "IREG_OREG");
                     bool drives_iologic = false;
-                    for (auto user : ci->ports.at(ctx->id("Z")).net->users)
+                    for (auto user : ci->ports.at(id_Z).net->users)
                         if (is_iologic_input_cell(ctx, user.cell) &&
-                            (user.port == ctx->id("D") ||
-                             (user.cell->type == ctx->id("TRELLIS_FF") && user.port == ctx->id("DI"))))
+                            (user.port == id_D || (user.cell->type == id_TRELLIS_FF && user.port == id_DI)))
                             drives_iologic = true;
                     if (drives_iologic) {
                         // Reconnect to PIO which the packer expects later on
-                        NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+                        NetInfo *input_net = ci->ports.at(id_A).net, *dly_net = ci->ports.at(id_Z).net;
                         disconnect_port(ctx, i_pio, id_O);
                         i_pio->ports.at(id_O).net = nullptr;
                         disconnect_port(ctx, ci, id_A);
@@ -2321,9 +2302,9 @@ class Ecp5Packer
                     iol = create_pio_iologic(o_pio, ci);
                     iol->params[ctx->id("DELAY.OUTDEL")] = std::string("ENABLED");
                     bool driven_by_iol = false;
-                    NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+                    NetInfo *input_net = ci->ports.at(id_A).net, *dly_net = ci->ports.at(id_Z).net;
                     if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
-                        input_net->driver.port == ctx->id("Q"))
+                        input_net->driver.port == id_Q)
                         driven_by_iol = true;
                     if (driven_by_iol) {
                         disconnect_port(ctx, o_pio, id_I);
@@ -2335,8 +2316,8 @@ class Ecp5Packer
                         connect_port(ctx, input_net, o_pio, id_I);
                         ctx->nets.erase(dly_net->name);
                     } else {
-                        replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
-                        replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
+                        replace_port(ci, id_A, iol, id_TXDATA0);
+                        replace_port(ci, id_Z, iol, id_IOLDO);
                         if (!o_pio->ports.count(id_IOLDO)) {
                             o_pio->ports[id_IOLDO].name = id_IOLDO;
                             o_pio->ports[id_IOLDO].type = PORT_IN;
@@ -2349,11 +2330,11 @@ class Ecp5Packer
                               ci->name.c_str(ctx));
                 }
                 iol->params[ctx->id("DELAY.DEL_VALUE")] =
-                        lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED"));
-                if (ci->params.count(ctx->id("DEL_VALUE")) &&
-                    (!ci->params.at(ctx->id("DEL_VALUE")).is_string ||
-                     std::string(ci->params.at(ctx->id("DEL_VALUE")).as_string()).substr(0, 5) != "DELAY"))
-                    iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
+                        lookup_delay(str_or_default(ci->params, id_DEL_MODE, "USER_DEFINED"));
+                if (ci->params.count(id_DEL_VALUE) &&
+                    (!ci->params.at(id_DEL_VALUE).is_string ||
+                     std::string(ci->params.at(id_DEL_VALUE).as_string()).substr(0, 5) != "DELAY"))
+                    iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(id_DEL_VALUE);
                 if (ci->ports.count(id_LOADN))
                     replace_port(ci, id_LOADN, iol, id_LOADN);
                 else
@@ -2373,9 +2354,9 @@ class Ecp5Packer
 
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == ctx->id("IDDRX1F")) {
-                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+            if (ci->type == id_IDDRX1F) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
                     log_error("IDDRX1F '%s' D input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2384,15 +2365,15 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRX1_ODDRX1");
-                replace_port(ci, ctx->id("D"), iol, id_PADDI);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
-                replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                replace_port(ci, id_D, iol, id_PADDI);
+                set_iologic_sclk(iol, ci, id_SCLK, true);
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_Q0, iol, id_RXDATA0);
+                replace_port(ci, id_Q1, iol, id_RXDATA1);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("ODDRX1F")) {
-                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+            } else if (ci->type == id_ODDRX1F) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("ODDRX1F '%s' Q output must be connected only to a top level output\n",
                               ci->name.c_str(ctx));
@@ -2402,21 +2383,21 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRX1_ODDRX1");
-                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                replace_port(ci, id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
                 replace_port(pio, id_I, pio, id_IOLDO);
-                pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
-                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
-                replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
+                set_iologic_sclk(iol, ci, id_SCLK, false);
+                set_iologic_lsr(iol, ci, id_RST, false);
+                replace_port(ci, id_D0, iol, id_TXDATA0);
+                replace_port(ci, id_D1, iol, id_TXDATA1);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("ODDRX2F") || ci->type == ctx->id("ODDR71B")) {
-                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+            } else if (ci->type == id_ODDRX2F || ci->type == id_ODDR71B) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
                               ci->name.c_str(ctx));
@@ -2426,38 +2407,38 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "ODDRXN");
-                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                replace_port(ci, id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
                 replace_port(pio, id_I, pio, id_IOLDO);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false, false);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                set_iologic_sclk(iol, ci, id_SCLK, false, false);
+                set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
-                replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
-                replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
-                replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
-                if (ci->type == ctx->id("ODDR71B")) {
-                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string()));
+                set_iologic_lsr(iol, ci, id_RST, false, false);
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_D0, iol, id_TXDATA0);
+                replace_port(ci, id_D1, iol, id_TXDATA1);
+                replace_port(ci, id_D2, iol, id_TXDATA2);
+                replace_port(ci, id_D3, iol, id_TXDATA3);
+                if (ci->type == id_ODDR71B) {
+                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
                     if (loc.z % 2 == 1)
                         log_error("ODDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
-                    replace_port(ci, ctx->id("D4"), iol, id_TXDATA4);
-                    replace_port(ci, ctx->id("D5"), iol, id_TXDATA5);
-                    replace_port(ci, ctx->id("D6"), iol, id_TXDATA6);
+                    replace_port(ci, id_D4, iol, id_TXDATA4);
+                    replace_port(ci, id_D5, iol, id_TXDATA5);
+                    replace_port(ci, id_D6, iol, id_TXDATA6);
                     iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDR71");
                 } else {
                     iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDRX2");
                 }
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
-                pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
+                pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("IDDRX2F") || ci->type == ctx->id("IDDR71B")) {
-                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+            } else if (ci->type == id_IDDRX2F || ci->type == id_IDDR71B) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
                     log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2466,30 +2447,30 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRXN");
-                replace_port(ci, ctx->id("D"), iol, id_PADDI);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                replace_port(ci, id_D, iol, id_PADDI);
+                set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
-                replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
-                replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
-                replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
-                if (ci->type == ctx->id("IDDR71B")) {
-                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string()));
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_Q0, iol, id_RXDATA0);
+                replace_port(ci, id_Q1, iol, id_RXDATA1);
+                replace_port(ci, id_Q2, iol, id_RXDATA2);
+                replace_port(ci, id_Q3, iol, id_RXDATA3);
+                if (ci->type == id_IDDR71B) {
+                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
                     if (loc.z % 2 == 1)
                         log_error("IDDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
-                    replace_port(ci, ctx->id("Q4"), iol, id_RXDATA4);
-                    replace_port(ci, ctx->id("Q5"), iol, id_RXDATA5);
-                    replace_port(ci, ctx->id("Q6"), iol, id_RXDATA6);
-                    replace_port(ci, ctx->id("ALIGNWD"), iol, id_SLIP);
+                    replace_port(ci, id_Q4, iol, id_RXDATA4);
+                    replace_port(ci, id_Q5, iol, id_RXDATA5);
+                    replace_port(ci, id_Q6, iol, id_RXDATA6);
+                    replace_port(ci, id_ALIGNWD, iol, id_SLIP);
                     iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDR71");
                 } else {
                     iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDRX2");
                 }
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("OSHX2A")) {
-                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+            } else if (ci->type == id_OSHX2A) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
                               ci->name.c_str(ctx));
@@ -2499,24 +2480,24 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                replace_port(ci, id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
                 replace_port(pio, id_I, pio, id_IOLDO);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
-                replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                set_iologic_lsr(iol, ci, id_RST, false, false);
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_D0, iol, id_TXDATA0);
+                replace_port(ci, id_D1, iol, id_TXDATA2);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2");
-                pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
+                pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
-                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+            } else if (ci->type == id_ODDRX2DQA || ci->type == id_ODDRX2DQSB) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
                               ci->name.c_str(ctx));
@@ -2526,30 +2507,30 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                replace_port(ci, id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
                 replace_port(pio, id_I, pio, id_IOLDO);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
-                replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
-                replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
-                replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                set_iologic_lsr(iol, ci, id_RST, false, false);
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_D0, iol, id_TXDATA0);
+                replace_port(ci, id_D1, iol, id_TXDATA1);
+                replace_port(ci, id_D2, iol, id_TXDATA2);
+                replace_port(ci, id_D3, iol, id_TXDATA3);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MODDRX.MODE")] = std::string("MODDRX2");
                 iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
-                        std::string(ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270");
-                process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
-                pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
+                        std::string(ci->type == id_ODDRX2DQSB ? "DQSW" : "DQSW270");
+                process_dqs_port(ci, pio, iol, ci->type == id_ODDRX2DQSB ? id_DQSW : id_DQSW270);
+                pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("IDDRX2DQA")) {
-                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+            } else if (ci->type == id_IDDRX2DQA) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
                     log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2558,16 +2539,16 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, ctx->id("D"), iol, id_PADDI);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                replace_port(ci, id_D, iol, id_PADDI);
+                set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
-                replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
-                replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
-                replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
-                replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
-                replace_port(ci, ctx->id("QWL"), iol, id_INFF);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                set_iologic_lsr(iol, ci, id_RST, true);
+                replace_port(ci, id_Q0, iol, id_RXDATA0);
+                replace_port(ci, id_Q1, iol, id_RXDATA1);
+                replace_port(ci, id_Q2, iol, id_RXDATA2);
+                replace_port(ci, id_Q3, iol, id_RXDATA3);
+                replace_port(ci, id_QWL, iol, id_INFF);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MIDDRX.MODE")] = std::string("MIDDRX2");
                 process_dqs_port(ci, pio, iol, id_DQSR90);
                 process_dqs_port(ci, pio, iol, id_RDPNTR2);
@@ -2577,8 +2558,8 @@ class Ecp5Packer
                 process_dqs_port(ci, pio, iol, id_WRPNTR1);
                 process_dqs_port(ci, pio, iol, id_WRPNTR0);
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
-                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
+            } else if (ci->type == id_TSHX2DQA || ci->type == id_TSHX2DQSA) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
                               ci->name.c_str(ctx));
@@ -2588,33 +2569,33 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
+                replace_port(ci, id_Q, iol, id_IOLTO);
                 if (!pio->ports.count(id_IOLTO)) {
                     pio->ports[id_IOLTO].name = id_IOLTO;
                     pio->ports[id_IOLTO].type = PORT_IN;
                 }
                 replace_port(pio, id_T, pio, id_IOLTO);
-                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
-                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
-                replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
-                replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
-                process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
-                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                set_iologic_lsr(iol, ci, id_RST, false);
+                replace_port(ci, id_T0, iol, id_TSDATA0);
+                replace_port(ci, id_T1, iol, id_TSDATA1);
+                process_dqs_port(ci, pio, iol, ci->type == id_TSHX2DQSA ? id_DQSW : id_DQSW270);
+                iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MTDDRX.MODE")] = std::string("MTSHX2");
                 iol->params[ctx->id("MTDDRX.REGSET")] = std::string("SET");
                 iol->params[ctx->id("MTDDRX.DQSW_INVERT")] =
-                        std::string(ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED");
+                        std::string(ci->type == id_TSHX2DQSA ? "ENABLED" : "DISABLED");
                 iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
-                        std::string(ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270");
-                iol->params[ctx->id("IOLTOMUX")] = std::string("TDDR");
+                        std::string(ci->type == id_TSHX2DQSA ? "DQSW" : "DQSW270");
+                iol->params[id_IOLTOMUX] = std::string("TDDR");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == ctx->id("TRELLIS_FF") && bool_or_default(ci->attrs, ctx->id("syn_useioff"))) {
+            } else if (ci->type == id_TRELLIS_FF && bool_or_default(ci->attrs, id_syn_useioff)) {
                 // Pack IO flipflop into IOLOGIC
-                std::string mode = str_or_default(ci->attrs, ctx->id("ioff_dir"), "");
+                std::string mode = str_or_default(ci->attrs, id_ioff_dir, "");
                 if (mode != "output") {
                     // See if it can be packed as an input ff
-                    NetInfo *d = get_net_or_empty(ci, ctx->id("DI"));
+                    NetInfo *d = get_net_or_empty(ci, id_DI);
                     CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
                     if (pio != nullptr && d->users.size() == 1) {
                         // Input FF
@@ -2624,35 +2605,35 @@ class Ecp5Packer
                         else
                             iol = create_pio_iologic(pio, ci);
                         set_iologic_mode(iol, "IREG_OREG");
-                        set_iologic_sclk(iol, ci, ctx->id("CLK"), true);
-                        set_iologic_lsr(iol, ci, ctx->id("LSR"), true);
+                        set_iologic_sclk(iol, ci, id_CLK, true);
+                        set_iologic_lsr(iol, ci, id_LSR, true);
                         // Handle CLK and CE muxes
-                        if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
-                            iol->params[ctx->id("CLKIMUX")] = std::string("INV");
-                        if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
-                            iol->params[ctx->id("CEIMUX")] = std::string("CEMUX");
-                            iol->params[ctx->id("CEMUX")] = std::string("CE");
-                            if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
-                                replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
+                        if (str_or_default(ci->params, id_CLKMUX) == "INV")
+                            iol->params[id_CLKIMUX] = std::string("INV");
+                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+                            iol->params[id_CEIMUX] = std::string("CEMUX");
+                            iol->params[id_CEMUX] = std::string("CE");
+                            if (get_net_or_empty(ci, id_CE) == nullptr)
+                                replace_port(ci, id_CE, iol, id_CE);
                             else
-                                disconnect_port(ctx, ci, ctx->id("CE"));
+                                disconnect_port(ctx, ci, id_CE);
                         } else {
-                            iol->params[ctx->id("CEIMUX")] = std::string("1");
+                            iol->params[id_CEIMUX] = std::string("1");
                         }
                         // Set IOLOGIC params from FF params
                         iol->params[ctx->id("FF.INREGMODE")] = std::string("FF");
-                        iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, ctx->id("REGSET"), "RESET");
-                        iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
-                        iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
-                        replace_port(ci, ctx->id("DI"), iol, id_PADDI);
-                        replace_port(ci, ctx->id("Q"), iol, id_INFF);
+                        iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, id_REGSET, "RESET");
+                        iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
+                        iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
+                        replace_port(ci, id_DI, iol, id_PADDI);
+                        replace_port(ci, id_Q, iol, id_INFF);
                         packed_cells.insert(cell.first);
                         continue;
                     }
                 }
                 if (mode != "input") {
-                    CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
-                    CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+                    CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true);
+                    CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                     if (pio_t != nullptr || pio_i != nullptr) {
                         // Output or tristate FF
                         bool tri = (pio_t != nullptr);
@@ -2664,47 +2645,47 @@ class Ecp5Packer
                             iol = create_pio_iologic(pio, ci);
                         set_iologic_mode(iol, "IREG_OREG");
                         // Connection between FF and PIO
-                        replace_port(ci, ctx->id("Q"), iol, tri ? id_IOLTO : id_IOLDO);
+                        replace_port(ci, id_Q, iol, tri ? id_IOLTO : id_IOLDO);
                         if (tri) {
                             if (!pio->ports.count(id_IOLTO)) {
                                 pio->ports[id_IOLTO].name = id_IOLTO;
                                 pio->ports[id_IOLTO].type = PORT_IN;
                             }
-                            pio->params[ctx->id("TRIMUX_TSREG")] = std::string("IOLTO");
+                            pio->params[id_TRIMUX_TSREG] = std::string("IOLTO");
                             replace_port(pio, id_T, pio, id_IOLTO);
                         } else {
                             if (!pio->ports.count(id_IOLDO)) {
                                 pio->ports[id_IOLDO].name = id_IOLDO;
                                 pio->ports[id_IOLDO].type = PORT_IN;
                             }
-                            pio->params[ctx->id("DATAMUX_OREG")] = std::string("IOLDO");
+                            pio->params[id_DATAMUX_OREG] = std::string("IOLDO");
                             replace_port(pio, id_I, pio, id_IOLDO);
                         }
 
-                        set_iologic_sclk(iol, ci, ctx->id("CLK"), false);
-                        set_iologic_lsr(iol, ci, ctx->id("LSR"), false);
+                        set_iologic_sclk(iol, ci, id_CLK, false);
+                        set_iologic_lsr(iol, ci, id_LSR, false);
 
                         // Handle CLK and CE muxes
-                        if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
-                            iol->params[ctx->id("CLKOMUX")] = std::string("INV");
-                        if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
-                            iol->params[ctx->id("CEOMUX")] = std::string("CEMUX");
-                            iol->params[ctx->id("CEMUX")] = std::string("CE");
-                            if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
-                                replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
+                        if (str_or_default(ci->params, id_CLKMUX) == "INV")
+                            iol->params[id_CLKOMUX] = std::string("INV");
+                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+                            iol->params[id_CEOMUX] = std::string("CEMUX");
+                            iol->params[id_CEMUX] = std::string("CE");
+                            if (get_net_or_empty(ci, id_CE) == nullptr)
+                                replace_port(ci, id_CE, iol, id_CE);
                             else
-                                disconnect_port(ctx, ci, ctx->id("CE"));
+                                disconnect_port(ctx, ci, id_CE);
                         } else {
-                            iol->params[ctx->id("CEOMUX")] = std::string("1");
+                            iol->params[id_CEOMUX] = std::string("1");
                         }
                         // FF params
                         iol->params[ctx->id(tri ? "TSREG.OUTREGMODE" : "OUTREG.OUTREGMODE")] = std::string("FF");
                         iol->params[ctx->id(tri ? "TSREG.REGSET" : "OUTREG.REGSET")] =
-                                str_or_default(ci->params, ctx->id("REGSET"), "RESET");
-                        iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
+                                str_or_default(ci->params, id_REGSET, "RESET");
+                        iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
                         // Data input
-                        replace_port(ci, ctx->id("DI"), iol, tri ? id_TSDATA0 : id_TXDATA0);
-                        iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                        replace_port(ci, id_DI, iol, tri ? id_TSDATA0 : id_TXDATA0);
+                        iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                         packed_cells.insert(cell.first);
                         continue;
                     }
@@ -2724,26 +2705,25 @@ class Ecp5Packer
                     if (input == nullptr)
                         continue;
                     for (auto user : input->users) {
-                        if (!user.cell->attrs.count(ctx->id("BEL")))
+                        if (!user.cell->attrs.count(id_BEL))
                             continue;
-                        Loc user_loc = ctx->getBelLocation(
-                                ctx->getBelByNameStr(user.cell->attrs.at(ctx->id("BEL")).as_string()));
+                        Loc user_loc =
+                                ctx->getBelLocation(ctx->getBelByNameStr(user.cell->attrs.at(id_BEL).as_string()));
                         for (auto bel : ctx->getBels()) {
                             if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
                                 continue;
                             loc = ctx->getBelLocation(bel);
                             if (loc.x == user_loc.x) {
-                                ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                                ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                                 goto eclkbridge_done;
                             }
                         }
                     }
                     if (input->driver.cell != nullptr) {
                         CellInfo *drv = input->driver.cell;
-                        if (!drv->attrs.count(ctx->id("BEL")))
+                        if (!drv->attrs.count(id_BEL))
                             continue;
-                        Loc drv_loc =
-                                ctx->getBelLocation(ctx->getBelByNameStr(drv->attrs.at(ctx->id("BEL")).as_string()));
+                        Loc drv_loc = ctx->getBelLocation(ctx->getBelByNameStr(drv->attrs.at(id_BEL).as_string()));
                         BelId closest;
                         int closest_x = -1; // aim for same side of chip
                         for (auto bel : ctx->getBels()) {
@@ -2757,7 +2737,7 @@ class Ecp5Packer
                         }
                         NPNR_ASSERT(closest != BelId());
                         loc = ctx->getBelLocation(closest);
-                        ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest).str(ctx);
+                        ci->attrs[id_BEL] = ctx->getBelName(closest).str(ctx);
                         goto eclkbridge_done;
                     }
                 }
@@ -2766,7 +2746,7 @@ class Ecp5Packer
                     if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
                         continue;
                     loc = ctx->getBelLocation(bel);
-                    ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                    ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                 }
             eclkbridge_done:
                 if (o != nullptr)
@@ -2787,7 +2767,7 @@ class Ecp5Packer
             if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
                 if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
                     continue;
-                BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, ctx->id("BEL")));
+                BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, id_BEL));
                 NPNR_ASSERT(bel != BelId());
                 Loc pioLoc = ctx->getBelLocation(bel);
                 if (ci->type == id_DQSBUFM)
@@ -2818,7 +2798,7 @@ class Ecp5Packer
                             // z-index of CLKDIVF must match index of ECLK
                             if (loc.z != eclk.first.second)
                                 continue;
-                            ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                            ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                             make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
                             goto clkdiv_done;
                         }
@@ -2831,10 +2811,9 @@ class Ecp5Packer
                 const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
                 if (eclki != nullptr && eclki->driver.cell != nullptr) {
                     if (eclki->driver.cell->type == id_ECLKBRIDGECS) {
-                        BelId bel = ctx->getBelByNameStr(eclki->driver.cell->attrs.at(ctx->id("BEL")).as_string());
+                        BelId bel = ctx->getBelByNameStr(eclki->driver.cell->attrs.at(id_BEL).as_string());
                         Loc loc = ctx->getBelLocation(bel);
-                        ci->attrs[ctx->id("BEL")] =
-                                ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
+                        ci->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
                         used_eclksyncb.insert(bel);
                         goto eclksync_done;
                     }
@@ -2843,14 +2822,14 @@ class Ecp5Packer
                     log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
                 for (auto user : eclko->users) {
                     if (user.cell->type == id_TRELLIS_ECLKBUF) {
-                        Loc eckbuf_loc = ctx->getBelLocation(
-                                ctx->getBelByNameStr(user.cell->attrs.at(ctx->id("BEL")).as_string()));
+                        Loc eckbuf_loc =
+                                ctx->getBelLocation(ctx->getBelByNameStr(user.cell->attrs.at(id_BEL).as_string()));
                         for (auto bel : ctx->getBels()) {
                             if (ctx->getBelType(bel) != id_ECLKSYNCB)
                                 continue;
                             Loc loc = ctx->getBelLocation(bel);
                             if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
-                                ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                                ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                                 used_eclksyncb.insert(bel);
                                 goto eclksync_done;
                             }
@@ -2859,7 +2838,7 @@ class Ecp5Packer
                 }
             eclksync_done:
                 continue;
-            } else if (ci->type == ctx->id("DDRDLLA")) {
+            } else if (ci->type == id_DDRDLLA) {
                 ci->type = id_DDRDLL; // transform from Verilog to Bel name
                 const NetInfo *clk = net_or_nullptr(ci, id_CLK);
                 if (clk == nullptr)
@@ -2871,9 +2850,9 @@ class Ecp5Packer
                 if (ddrdel != nullptr) {
                     for (auto &usr : ddrdel->users) {
                         const CellInfo *uc = usr.cell;
-                        if (uc->type != id_DQSBUFM || !uc->attrs.count(ctx->id("BEL")))
+                        if (uc->type != id_DQSBUFM || !uc->attrs.count(id_BEL))
                             continue;
-                        BelId dqsb_bel = ctx->getBelByNameStr(uc->attrs.at(ctx->id("BEL")).as_string());
+                        BelId dqsb_bel = ctx->getBelByNameStr(uc->attrs.at(id_BEL).as_string());
                         Loc dqsb_loc = ctx->getBelLocation(dqsb_bel);
                         if (dqsb_loc.x > 15)
                             right_bank_users = true;
@@ -2907,7 +2886,7 @@ class Ecp5Packer
                             if (eclk.first.first != ddrdll_bank)
                                 continue;
                             log_info("Constraining DDRDLLA '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
-                            ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                            ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                             make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
                             goto ddrdll_done;
                         }
@@ -2923,7 +2902,7 @@ class Ecp5Packer
             if (ci->type == id_ECLKSYNCB) {
                 // **All** ECLKSYNCBs must be constrained
                 // Most will be dealt with above, but there might be some rogue cases
-                if (ci->attrs.count(ctx->id("BEL")))
+                if (ci->attrs.count(id_BEL))
                     continue;
                 for (BelId bel : ctx->getBels()) {
                     if (ctx->getBelType(bel) != id_ECLKSYNCB)
@@ -2932,7 +2911,7 @@ class Ecp5Packer
                     if (used_eclksyncb.count(bel))
                         continue;
                     log_info("Constraining ECLKSYNCB '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
-                    ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                    ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
                     goto eclksync_ii_done;
                 }
                 if (0) {
@@ -2946,7 +2925,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_CLKDIVF) {
-                if (ci->attrs.count(ctx->id("BEL")))
+                if (ci->attrs.count(id_BEL))
                     continue;
                 // Case of a CLKDIVF driven by an ECLKSYNC constrained above; without the input being used elsewhere as
                 // an edge clock
@@ -2954,9 +2933,9 @@ class Ecp5Packer
                 if (clki == nullptr || clki->driver.cell == nullptr)
                     continue;
                 CellInfo *drv = clki->driver.cell;
-                if (drv->type != id_ECLKSYNCB || !drv->attrs.count(ctx->id("BEL")))
+                if (drv->type != id_ECLKSYNCB || !drv->attrs.count(id_BEL))
                     continue;
-                BelId bel = ctx->getBelByNameStr(drv->attrs.at(ctx->id("BEL")).as_string());
+                BelId bel = ctx->getBelByNameStr(drv->attrs.at(id_BEL).as_string());
                 // Find a CLKDIVF that is routeable from the ECLKSYNC
                 std::queue<WireId> visit;
                 visit.push(ctx->getBelPinWire(bel, id_ECLKO));
@@ -2966,7 +2945,7 @@ class Ecp5Packer
                     for (BelPin bp : ctx->getWireBelPins(cursor)) {
                         if (ctx->getBelType(bp.bel) != id_CLKDIVF || bp.pin != id_CLKI)
                             continue;
-                        ci->attrs[ctx->id("BEL")] = ctx->getBelName(bp.bel).str(ctx);
+                        ci->attrs[id_BEL] = ctx->getBelName(bp.bel).str(ctx);
                         log_info("Constraining CLKDIVF '%s' to bel '%s' based on ECLKSYNCB.\n", ctx->nameOf(ci),
                                  ctx->nameOfBel(bp.bel));
                         goto clkdiv_ii_done;
@@ -3076,7 +3055,7 @@ class Ecp5Packer
             for (auto cell : changed_cells) {
                 CellInfo *ci = ctx->cells.at(cell).get();
                 if (ci->type == id_CLKDIVF) {
-                    std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
+                    std::string div = str_or_default(ci->params, id_DIV, "2.0");
                     double ratio;
                     if (div == "2.0")
                         ratio = 1 / 2.0;
@@ -3098,17 +3077,17 @@ class Ecp5Packer
                         continue;
                     log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
                              MHz(period_in));
-                    double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
-                    std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
-                    int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
+                    double period_in_div = period_in * int_or_default(ci->params, id_CLKI_DIV, 1);
+                    std::string path = str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP");
+                    int feedback_div = int_or_default(ci->params, id_CLKFB_DIV, 1);
                     if (path == "CLKOP" || path == "INT_OP")
-                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
+                        feedback_div *= int_or_default(ci->params, id_CLKOP_DIV, 1);
                     else if (path == "CLKOS" || path == "INT_OS")
-                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
+                        feedback_div *= int_or_default(ci->params, id_CLKOS_DIV, 1);
                     else if (path == "CLKOS2" || path == "INT_OS2")
-                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
+                        feedback_div *= int_or_default(ci->params, id_CLKOS2_DIV, 1);
                     else if (path == "CLKOS3" || path == "INT_OS3")
-                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
+                        feedback_div *= int_or_default(ci->params, id_CLKOS3_DIV, 1);
                     else {
                         log_info("     Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
                                  ci->name.c_str(ctx), path.c_str());
@@ -3120,12 +3099,12 @@ class Ecp5Packer
                         log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
                                  "800MHz]\n",
                                  vco_freq, ci->name.c_str(ctx));
-                    set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
-                    set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
-                    set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
-                    set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
+                    set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1));
+                    set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1));
+                    set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1));
+                    set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1));
                 } else if (ci->type == id_OSCG) {
-                    int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+                    int div = int_or_default(ci->params, id_DIV, 128);
                     set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
                 }
             }
@@ -3137,8 +3116,8 @@ class Ecp5Packer
         // Check for legacy-style JSON (use CEMUX as a clue) and error out, avoiding a confusing assertion failure
         // later
         for (auto &cell : ctx->cells) {
-            if (is_ff(ctx, cell.second.get()) && cell.second->params.count(ctx->id("CEMUX")) &&
-                !cell.second->params[ctx->id("CEMUX")].is_string)
+            if (is_ff(ctx, cell.second.get()) && cell.second->params.count(id_CEMUX) &&
+                !cell.second->params[id_CEMUX].is_string)
                 log_error("Found netlist using legacy-style JSON parameter values, please update your Yosys.\n");
         }
     }
@@ -3199,7 +3178,7 @@ bool Arch::pack()
         Ecp5Packer(ctx).pack();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         assignArchInfo();
-        ctx->settings[ctx->id("pack")] = 1;
+        ctx->settings[id_pack] = 1;
         archInfoToAttributes();
         return true;
     } catch (log_execution_error_exception) {
@@ -3233,24 +3212,24 @@ void Arch::assignArchInfo()
             ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
             ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
             ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-            std::string mode = str_or_default(ci->params, id("MODE"), "LOGIC");
+            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
             ci->sliceInfo.is_carry = (mode == "CCU2");
             ci->sliceInfo.is_memory = (mode == "DPRAM" || mode == "RAMW");
-            ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id("REG0_SD"), "0"));
-            ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id("REG1_SD"), "0"));
+            ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id_REG0_SD, "0"));
+            ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id_REG1_SD, "0"));
             ci->sliceInfo.has_l6mux = false;
             if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
                 ci->ports[id_FXA].net->driver.port == id_OFX0)
                 ci->sliceInfo.has_l6mux = true;
         } else if (ci->type == id_DP16KD) {
-            ci->ramInfo.is_pdp = (int_or_default(ci->params, id("DATA_WIDTH_A"), 0) == 36);
+            ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 36);
 
             // Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
-            std::string regmode_a = str_or_default(ci->params, id("REGMODE_A"), "NOREG");
+            std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
             if (regmode_a != "NOREG" && regmode_a != "OUTREG")
                 log_error("DP16KD %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this),
                           regmode_a.c_str());
-            std::string regmode_b = str_or_default(ci->params, id("REGMODE_B"), "NOREG");
+            std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
             if (regmode_b != "NOREG" && regmode_b != "OUTREG")
                 log_error("DP16KD %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this),
                           regmode_b.c_str());
@@ -3326,7 +3305,7 @@ void Arch::assignArchInfo()
         }
     }
     for (auto &net : nets) {
-        net.second->is_global = bool_or_default(net.second->attrs, id("ECP5_IS_GLOBAL"));
+        net.second->is_global = bool_or_default(net.second->attrs, id_ECP5_IS_GLOBAL);
     }
 }
 
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 0793832601..b104013dbc 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -688,7 +688,7 @@ void Arch::read_cst(std::istream &in)
         insloc
     } cst_type;
 
-    settings.erase(id("cst"));
+    settings.erase(id_cst);
     while (!in.eof()) {
         std::getline(in, line);
         cst_type = ioloc;
@@ -756,7 +756,7 @@ void Arch::read_cst(std::istream &in)
         }
         }
     }
-    settings[id("cst")] = 1;
+    settings[id_cst] = 1;
 }
 
 // Add all MUXes for the cell
@@ -1455,13 +1455,13 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     bool retVal;
     if (placer == "heap") {
         bool have_iobuf_or_constr = false;
         for (auto &cell : cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id("IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) {
+            if (ci->type == id_IOB || ci->bel != BelId() || ci->attrs.count(id_BEL)) {
                 have_iobuf_or_constr = true;
                 break;
             }
@@ -1472,15 +1472,15 @@ bool Arch::place()
             retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
         } else {
             PlacerHeapCfg cfg(getCtx());
-            cfg.ioBufTypes.insert(id("IOB"));
+            cfg.ioBufTypes.insert(id_IOB);
             cfg.beta = 0.5;
             retVal = placer_heap(getCtx(), cfg);
         }
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
     } else if (placer == "sa") {
         retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
         return retVal;
     } else {
@@ -1497,7 +1497,7 @@ bool Arch::place()
 
 bool Arch::route()
 {
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -1507,7 +1507,7 @@ bool Arch::route()
     } else {
         log_error("Gowin architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->settings[getCtx()->id("route")] = 1;
+    getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
     return result;
 }
@@ -1600,9 +1600,9 @@ void Arch::assignArchInfo()
             ci->is_slice = true;
             ci->ff_used = ci->params.at(id_FF_USED).as_bool();
             ci->ff_type = id(ci->params.at(id_FF_TYPE).as_string());
-            ci->slice_clk = get_net_or_empty(ci, id("CLK"));
-            ci->slice_ce = get_net_or_empty(ci, id("CE"));
-            ci->slice_lsr = get_net_or_empty(ci, id("LSR"));
+            ci->slice_clk = get_net_or_empty(ci, id_CLK);
+            ci->slice_ce = get_net_or_empty(ci, id_CE);
+            ci->slice_lsr = get_net_or_empty(ci, id_LSR);
 
             // add timing paths
             addCellTimingClock(cname, id_CLK);
diff --git a/gowin/arch.h b/gowin/arch.h
index 9ce3bd1c29..7a5dfc466d 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -354,7 +354,7 @@ struct Arch : BaseArch<ArchRanges>
     std::string getChipName() const override { return device; }
 
     ArchArgs archArgs() const override { return args; }
-    IdString archArgsToId(ArchArgs args) const override { return id("none"); }
+    IdString archArgsToId(ArchArgs args) const override { return id_none; }
 
     int getGridDimX() const override { return gridDimX; }
     int getGridDimY() const override { return gridDimY; }
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 82d0bb11df..be016e0e62 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -806,3 +806,12 @@ X(DECAL_ALU_ACTIVE)
 
 
 
+
+X(SINGLE_INPUT_MUX)
+X(cst)
+X(none)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 3d33f2d8a4..1201e31086 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -114,7 +114,7 @@ static void pack_alus(Context *ctx)
 
         int alu_idx = 1;
         do { // go through the ALU chain
-            auto alu_bel = ci->attrs.find(ctx->id("BEL"));
+            auto alu_bel = ci->attrs.find(id_BEL);
             if (alu_bel != ci->attrs.end()) {
                 log_error("ALU %s placement restrictions are not supported.\n", ctx->nameOf(ci));
                 return;
@@ -243,7 +243,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
                            std::vector<std::unique_ptr<CellInfo>> &new_cells)
 {
 
-    if (bool_or_default(ci->attrs, ctx->id("SINGLE_INPUT_MUX"))) {
+    if (bool_or_default(ci->attrs, id_SINGLE_INPUT_MUX)) {
         // find the muxed LUT
         NetInfo *i1 = ci->ports.at(id_I1).net;
 
@@ -257,14 +257,14 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         }
 
         // XXX enable the placement constraints
-        auto mux_bel = ci->attrs.find(ctx->id("BEL"));
-        auto lut1_bel = lut1->attrs.find(ctx->id("BEL"));
+        auto mux_bel = ci->attrs.find(id_BEL);
+        auto lut1_bel = lut1->attrs.find(id_BEL);
         if (lut1_bel != lut1->attrs.end() || mux_bel != ci->attrs.end()) {
             log_error("MUX2_LUT5 '%s' placement restrictions are not supported yet\n", ctx->nameOf(ci));
             return;
         }
 
-        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("GW_MUX2_LUT5"), ci->name.str(ctx) + "_LC");
+        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC");
         if (ctx->verbose) {
             log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
         }
@@ -299,15 +299,15 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         }
 
         // XXX enable the placement constraints
-        auto mux_bel = ci->attrs.find(ctx->id("BEL"));
-        auto lut0_bel = lut0->attrs.find(ctx->id("BEL"));
-        auto lut1_bel = lut1->attrs.find(ctx->id("BEL"));
+        auto mux_bel = ci->attrs.find(id_BEL);
+        auto lut0_bel = lut0->attrs.find(id_BEL);
+        auto lut1_bel = lut1->attrs.find(id_BEL);
         if (lut0_bel != lut0->attrs.end() || lut1_bel != lut1->attrs.end() || mux_bel != ci->attrs.end()) {
             log_error("MUX2_LUT5 '%s' placement restrictions are not supported yet\n", ctx->nameOf(ci));
             return;
         }
 
-        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("GW_MUX2_LUT5"), ci->name.str(ctx) + "_LC");
+        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC");
         if (ctx->verbose) {
             log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
         }
@@ -354,9 +354,9 @@ static void pack_mux2_lut(Context *ctx, CellInfo *ci, bool (*pred)(const BaseCtx
     }
 
     // XXX enable the placement constraints
-    auto mux_bel = ci->attrs.find(ctx->id("BEL"));
-    auto mux0_bel = mux0->attrs.find(ctx->id("BEL"));
-    auto mux1_bel = mux1->attrs.find(ctx->id("BEL"));
+    auto mux_bel = ci->attrs.find(id_BEL);
+    auto mux0_bel = mux0->attrs.find(id_BEL);
+    auto mux1_bel = mux1->attrs.find(id_BEL);
     if (mux0_bel != mux0->attrs.end() || mux1_bel != mux1->attrs.end() || mux_bel != ci->attrs.end()) {
         log_error("MUX2_LUT%c '%s' placement restrictions are not supported yet\n", type_suffix, ctx->nameOf(ci));
         return;
@@ -512,7 +512,7 @@ static void pack_lut_lutffs(Context *ctx)
         if (ctx->verbose)
             log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
         if (is_lut(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_LC");
+            std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_LC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             packed_cells.insert(ci->name);
@@ -520,14 +520,14 @@ static void pack_lut_lutffs(Context *ctx)
                 log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
             // See if we can pack into a DFF
             // TODO: LUT cascade
-            NetInfo *o = ci->ports.at(ctx->id("F")).net;
-            CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
-            auto lut_bel = ci->attrs.find(ctx->id("BEL"));
+            NetInfo *o = ci->ports.at(id_F).net;
+            CellInfo *dff = net_only_drives(ctx, o, is_ff, id_D, true);
+            auto lut_bel = ci->attrs.find(id_BEL);
             bool packed_dff = false;
             if (dff) {
                 if (ctx->verbose)
                     log_info("found attached dff %s\n", ctx->nameOf(dff));
-                auto dff_bel = dff->attrs.find(ctx->id("BEL"));
+                auto dff_bel = dff->attrs.find(id_BEL);
                 if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
                     // Locations don't match, can't pack
                 } else {
@@ -535,7 +535,7 @@ static void pack_lut_lutffs(Context *ctx)
                     dff_to_lc(ctx, dff, packed.get(), false);
                     ctx->nets.erase(o->name);
                     if (dff_bel != dff->attrs.end())
-                        packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                        packed->attrs[id_BEL] = dff_bel->second;
                     packed_cells.insert(dff->name);
                     if (ctx->verbose)
                         log_info("packed cell %s into %s\n", ctx->nameOf(dff), ctx->nameOf(packed.get()));
@@ -567,7 +567,7 @@ static void pack_nonlut_ffs(Context *ctx)
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (is_ff(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_DFFLC");
+            std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_DFFLC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             if (ctx->verbose)
@@ -610,20 +610,20 @@ static void pack_constants(Context *ctx)
 {
     log_info("Packing constants..\n");
 
-    std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_GND");
-    gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << 4);
+    std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_GND");
+    gnd_cell->params[id_INIT] = Property(0, 1 << 4);
     auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
-    gnd_net->driver.port = ctx->id("F");
-    gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
+    gnd_net->driver.port = id_F;
+    gnd_cell->ports.at(id_F).net = gnd_net.get();
 
-    std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_VCC");
+    std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_VCC");
     // Fill with 1s
-    vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
+    vcc_cell->params[id_INIT] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
     auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
-    vcc_net->driver.port = ctx->id("F");
-    vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
+    vcc_net->driver.port = id_F;
+    vcc_cell->ports.at(id_F).net = vcc_net.get();
 
     std::vector<IdString> dead_nets;
 
@@ -631,13 +631,13 @@ static void pack_constants(Context *ctx)
 
     for (auto &net : ctx->nets) {
         NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, gnd_net.get(), false);
             gnd_used = true;
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
-        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, vcc_net.get(), true);
             dead_nets.push_back(net.first);
@@ -780,7 +780,7 @@ bool Arch::pack()
         pack_alus(ctx);
         pack_lut_lutffs(ctx);
         pack_nonlut_ffs(ctx);
-        ctx->settings[ctx->id("pack")] = 1;
+        ctx->settings[id_pack] = 1;
         ctx->assignArchInfo();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 0f0246ef0a..cf7e99a54b 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -169,29 +169,29 @@ std::string Arch::getChipName() const
 IdString Arch::archArgsToId(ArchArgs args) const
 {
     if (args.type == ArchArgs::LP384)
-        return id("lp384");
+        return id_lp384;
     if (args.type == ArchArgs::LP1K)
-        return id("lp1k");
+        return id_lp1k;
     if (args.type == ArchArgs::HX1K)
-        return id("hx1k");
+        return id_hx1k;
     if (args.type == ArchArgs::UP3K)
-        return id("up3k");
+        return id_up3k;
     if (args.type == ArchArgs::UP5K)
-        return id("up5k");
+        return id_up5k;
     if (args.type == ArchArgs::U1K)
-        return id("u1k");
+        return id_u1k;
     if (args.type == ArchArgs::U2K)
-        return id("u2k");
+        return id_u2k;
     if (args.type == ArchArgs::U4K)
-        return id("u4k");
+        return id_u4k;
     if (args.type == ArchArgs::LP4K)
-        return id("lp4k");
+        return id_lp4k;
     if (args.type == ArchArgs::LP8K)
-        return id("lp8k");
+        return id_lp8k;
     if (args.type == ArchArgs::HX4K)
-        return id("hx4k");
+        return id_hx4k;
     if (args.type == ArchArgs::HX8K)
-        return id("hx8k");
+        return id_hx8k;
     return IdString();
 }
 
@@ -289,7 +289,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
 
-    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", bel.index)));
+    ret.push_back(std::make_pair(id_INDEX, stringf("%d", bel.index)));
 
     return ret;
 }
@@ -387,33 +387,33 @@ IdString Arch::getWireType(WireId wire) const
     case WireInfoPOD::WIRE_TYPE_NONE:
         return IdString();
     case WireInfoPOD::WIRE_TYPE_GLB2LOCAL:
-        return id("GLB2LOCAL");
+        return id_GLB2LOCAL;
     case WireInfoPOD::WIRE_TYPE_GLB_NETWK:
-        return id("GLB_NETWK");
+        return id_GLB_NETWK;
     case WireInfoPOD::WIRE_TYPE_LOCAL:
-        return id("LOCAL");
+        return id_LOCAL;
     case WireInfoPOD::WIRE_TYPE_LUTFF_IN:
-        return id("LUTFF_IN");
+        return id_LUTFF_IN;
     case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
-        return id("LUTFF_IN_LUT");
+        return id_LUTFF_IN_LUT;
     case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT:
-        return id("LUTFF_LOUT");
+        return id_LUTFF_LOUT;
     case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
-        return id("LUTFF_OUT");
+        return id_LUTFF_OUT;
     case WireInfoPOD::WIRE_TYPE_LUTFF_COUT:
-        return id("LUTFF_COUT");
+        return id_LUTFF_COUT;
     case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL:
-        return id("LUTFF_GLOBAL");
+        return id_LUTFF_GLOBAL;
     case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX:
-        return id("CARRY_IN_MUX");
+        return id_CARRY_IN_MUX;
     case WireInfoPOD::WIRE_TYPE_SP4_V:
-        return id("SP4_V");
+        return id_SP4_V;
     case WireInfoPOD::WIRE_TYPE_SP4_H:
-        return id("SP4_H");
+        return id_SP4_H;
     case WireInfoPOD::WIRE_TYPE_SP12_V:
-        return id("SP12_V");
+        return id_SP12_V;
     case WireInfoPOD::WIRE_TYPE_SP12_H:
-        return id("SP12_H");
+        return id_SP12_H;
     }
     return IdString();
 }
@@ -423,11 +423,11 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     std::vector<std::pair<IdString, std::string>> ret;
     auto &wi = chip_info->wire_data[wire.index];
 
-    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wire.index)));
+    ret.push_back(std::make_pair(id_INDEX, stringf("%d", wire.index)));
 
-    ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
-    ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
-    ret.push_back(std::make_pair(id("GRID_Z"), stringf("%d", wi.z)));
+    ret.push_back(std::make_pair(id_GRID_X, stringf("%d", wi.x)));
+    ret.push_back(std::make_pair(id_GRID_Y, stringf("%d", wi.y)));
+    ret.push_back(std::make_pair(id_GRID_Z, stringf("%d", wi.z)));
 
     return ret;
 }
@@ -476,7 +476,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
 
-    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", pip.index)));
+    ret.push_back(std::make_pair(id_INDEX, stringf("%d", pip.index)));
 
     return ret;
 }
@@ -682,7 +682,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
         cfg.ioBufTypes.insert(id_SB_IO);
@@ -695,19 +695,19 @@ bool Arch::place()
         log_error("iCE40 architecture does not support placer '%s'\n", placer.c_str());
     }
     bool retVal = true;
-    if (bool_or_default(settings, id("opt_timing"), false)) {
+    if (bool_or_default(settings, id_opt_timing, false)) {
         TimingOptCfg tocfg(getCtx());
         tocfg.cellTypes.insert(id_ICESTORM_LC);
         retVal = timing_opt(getCtx(), tocfg);
     }
-    getCtx()->settings[getCtx()->id("place")] = 1;
+    getCtx()->settings[id_place] = 1;
     archInfoToAttributes();
     return retVal;
 }
 
 bool Arch::route()
 {
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -717,7 +717,7 @@ bool Arch::route()
     } else {
         log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->settings[getCtx()->id("route")] = 1;
+    getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
     return result;
 }
@@ -1064,7 +1064,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_CLOCK_INPUT;
         return TMG_IGNORE;
     } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) {
-        if (port == this->id("SBCLKI"))
+        if (port == id_SBCLKI)
             return TMG_CLOCK_INPUT;
 
         clockInfoCount = 1;
@@ -1108,10 +1108,10 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     } else if (cell->type == id_ICESTORM_RAM) {
         if (port.str(this)[0] == 'R') {
             info.clock_port = id_RCLK;
-            info.edge = bool_or_default(cell->params, id("NEG_CLK_R")) ? FALLING_EDGE : RISING_EDGE;
+            info.edge = bool_or_default(cell->params, id_NEG_CLK_R) ? FALLING_EDGE : RISING_EDGE;
         } else {
             info.clock_port = id_WCLK;
-            info.edge = bool_or_default(cell->params, id("NEG_CLK_W")) ? FALLING_EDGE : RISING_EDGE;
+            info.edge = bool_or_default(cell->params, id_NEG_CLK_W) ? FALLING_EDGE : RISING_EDGE;
         }
         if (cell->ports.at(port).type == PORT_OUT) {
             bool has_clktoq = get_cell_delay_internal(cell, info.clock_port, port, info.clockToQ);
@@ -1168,7 +1168,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.hold = DelayPair(0);
         }
     } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) {
-        info.clock_port = this->id("SBCLKI");
+        info.clock_port = id_SBCLKI;
         info.edge = RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
             /* Dummy number */
@@ -1233,12 +1233,12 @@ void Arch::assignCellInfo(CellInfo *cell)
             cell->lcInfo.inputCount++;
     } else if (cell->type == id_SB_IO) {
         cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT";
-        cell->ioInfo.global = bool_or_default(cell->attrs, this->id("GLOBAL"));
-        cell->ioInfo.pintype = int_or_default(cell->params, this->id("PIN_TYPE"));
-        cell->ioInfo.negtrig = bool_or_default(cell->params, this->id("NEG_TRIGGER"));
+        cell->ioInfo.global = bool_or_default(cell->attrs, id_GLOBAL);
+        cell->ioInfo.pintype = int_or_default(cell->params, id_PIN_TYPE);
+        cell->ioInfo.negtrig = bool_or_default(cell->params, id_NEG_TRIGGER);
 
     } else if (cell->type == id_SB_GB) {
-        cell->gbInfo.forPadIn = bool_or_default(cell->attrs, this->id("FOR_PAD_IN"));
+        cell->gbInfo.forPadIn = bool_or_default(cell->attrs, id_FOR_PAD_IN);
     }
 }
 
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index f01afdff6e..3b024d8175 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -120,7 +120,7 @@ bool Arch::isBelLocationValid(BelId bel) const
                         break;
 
                     // Are we perhaps a PAD INPUT Bel that can be placed here?
-                    if (pll_cell->attrs[id("BEL_PAD_INPUT")] == getBelName(bel).str(getCtx()))
+                    if (pll_cell->attrs[id_BEL_PAD_INPUT] == getBelName(bel).str(getCtx()))
                         return true;
 
                     // Conflict
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 8caa9dc698..89f8426207 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -391,7 +391,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     pool<Loc> sb_io_used_by_pll_pad;
 
     for (auto &cell : ctx->cells) {
-        if (cell.second->type != ctx->id("ICESTORM_PLL"))
+        if (cell.second->type != id_ICESTORM_PLL)
             continue;
 
         // Collect all locations matching an PLL output port
@@ -434,16 +434,16 @@ void write_asc(const Context *ctx, std::ostream &out)
             std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl;
             continue;
         }
-        if (cell.second->type == ctx->id("ICESTORM_LC")) {
+        if (cell.second->type == id_ICESTORM_LC) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
-            unsigned lut_init = get_param_or_def(ctx, cell.second.get(), ctx->id("LUT_INIT"));
-            bool neg_clk = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK"));
-            bool dff_enable = get_param_or_def(ctx, cell.second.get(), ctx->id("DFF_ENABLE"));
-            bool async_sr = get_param_or_def(ctx, cell.second.get(), ctx->id("ASYNC_SR"));
-            bool set_noreset = get_param_or_def(ctx, cell.second.get(), ctx->id("SET_NORESET"));
-            bool carry_enable = get_param_or_def(ctx, cell.second.get(), ctx->id("CARRY_ENABLE"));
+            unsigned lut_init = get_param_or_def(ctx, cell.second.get(), id_LUT_INIT);
+            bool neg_clk = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK);
+            bool dff_enable = get_param_or_def(ctx, cell.second.get(), id_DFF_ENABLE);
+            bool async_sr = get_param_or_def(ctx, cell.second.get(), id_ASYNC_SR);
+            bool set_noreset = get_param_or_def(ctx, cell.second.get(), id_SET_NORESET);
+            bool carry_enable = get_param_or_def(ctx, cell.second.get(), id_CARRY_ENABLE);
             std::vector<bool> lc(20, false);
 
             // Discover permutation
@@ -502,20 +502,20 @@ void write_asc(const Context *ctx, std::ostream &out)
             if (dff_enable)
                 set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
 
-            bool carry_const = get_param_or_def(ctx, cell.second.get(), ctx->id("CIN_CONST"));
-            bool carry_set = get_param_or_def(ctx, cell.second.get(), ctx->id("CIN_SET"));
+            bool carry_const = get_param_or_def(ctx, cell.second.get(), id_CIN_CONST);
+            bool carry_set = get_param_or_def(ctx, cell.second.get(), id_CIN_SET);
             if (carry_const) {
                 if (!ctx->force)
                     NPNR_ASSERT(z == 0);
                 set_config(ti, config.at(y).at(x), "CarryInSet", carry_set);
             }
-        } else if (cell.second->type == ctx->id("SB_IO")) {
+        } else if (cell.second->type == id_SB_IO) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-            unsigned pin_type = get_param_or_def(ctx, cell.second.get(), ctx->id("PIN_TYPE"));
-            bool neg_trigger = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_TRIGGER"));
-            bool pullup = get_param_or_def(ctx, cell.second.get(), ctx->id("PULLUP"));
+            unsigned pin_type = get_param_or_def(ctx, cell.second.get(), id_PIN_TYPE);
+            bool neg_trigger = get_param_or_def(ctx, cell.second.get(), id_NEG_TRIGGER);
+            bool pullup = get_param_or_def(ctx, cell.second.get(), id_PULLUP);
             bool lvds = cell.second->ioInfo.lvds;
             bool used_by_pll_out = sb_io_used_by_pll_out.count(Loc(x, y, z)) > 0;
             bool used_by_pll_pad = sb_io_used_by_pll_pad.count(Loc(x, y, z)) > 0;
@@ -550,8 +550,8 @@ void write_asc(const Context *ctx, std::ostream &out)
 
                 if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
                     std::string pullup_resistor = "100K";
-                    if (cell.second->attrs.count(ctx->id("PULLUP_RESISTOR")))
-                        pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR")).as_string();
+                    if (cell.second->attrs.count(id_PULLUP_RESISTOR))
+                        pullup_resistor = cell.second->attrs.at(id_PULLUP_RESISTOR).as_string();
                     NPNR_ASSERT(pullup_resistor == "100K" || pullup_resistor == "10K" || pullup_resistor == "6P8K" ||
                                 pullup_resistor == "3P3K");
                     if (iez == 0) {
@@ -599,7 +599,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                     }
                 }
             }
-        } else if (cell.second->type == ctx->id("SB_GB")) {
+        } else if (cell.second->type == id_SB_GB) {
             if (cell.second->gbInfo.forPadIn) {
                 Loc gb_loc = ctx->getBelLocation(bel);
                 for (auto &glb : ci.global_network_info) {
@@ -608,7 +608,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                     }
                 }
             }
-        } else if (cell.second->type == ctx->id("ICESTORM_RAM")) {
+        } else if (cell.second->type == id_ICESTORM_RAM) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y;
             const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
@@ -616,10 +616,10 @@ void write_asc(const Context *ctx, std::ostream &out)
             if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
                 set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true);
             }
-            bool negclk_r = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK_R"));
-            bool negclk_w = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK_W"));
-            int write_mode = get_param_or_def(ctx, cell.second.get(), ctx->id("WRITE_MODE"));
-            int read_mode = get_param_or_def(ctx, cell.second.get(), ctx->id("READ_MODE"));
+            bool negclk_r = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_R);
+            bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W);
+            int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE);
+            int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE);
             set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
             set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
 
@@ -627,27 +627,27 @@ void write_asc(const Context *ctx, std::ostream &out)
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1);
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", read_mode & 0x2);
-        } else if (cell.second->type == ctx->id("SB_LED_DRV_CUR")) {
+        } else if (cell.second->type == id_SB_LED_DRV_CUR) {
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "LED_DRV_CUR_EN", true,
                         "IpConfig.");
-        } else if (cell.second->type == ctx->id("SB_RGB_DRV")) {
+        } else if (cell.second->type == id_SB_RGB_DRV) {
             const std::vector<std::pair<std::string, int>> rgb_params = {
                     {"RGB0_CURRENT", 6}, {"RGB1_CURRENT", 6}, {"RGB2_CURRENT", 6}};
             configure_extra_cell(config, ctx, cell.second.get(), rgb_params, true, std::string("IpConfig."));
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "RGB_DRV_EN", true, "IpConfig.");
-        } else if (cell.second->type == ctx->id("SB_RGBA_DRV")) {
+        } else if (cell.second->type == id_SB_RGBA_DRV) {
             const std::vector<std::pair<std::string, int>> rgba_params = {
                     {"CURRENT_MODE", 1}, {"RGB0_CURRENT", 6}, {"RGB1_CURRENT", 6}, {"RGB2_CURRENT", 6}};
             configure_extra_cell(config, ctx, cell.second.get(), rgba_params, true, std::string("IpConfig."));
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "RGBA_DRV_EN", true, "IpConfig.");
-        } else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC") ||
-                   cell.second->type == ctx->id("SB_LEDDA_IP")) {
+        } else if (cell.second->type == id_SB_WARMBOOT || cell.second->type == id_ICESTORM_LFOSC ||
+                   cell.second->type == id_SB_LEDDA_IP) {
             // No config needed
-        } else if (cell.second->type == ctx->id("SB_I2C")) {
-            bool sda_in_dly = !cell.second->attrs.count(ctx->id("SDA_INPUT_DELAYED")) ||
-                              cell.second->attrs[ctx->id("SDA_INPUT_DELAYED")].as_bool();
-            bool sda_out_dly = !cell.second->attrs.count(ctx->id("SDA_OUTPUT_DELAYED")) ||
-                               cell.second->attrs[ctx->id("SDA_OUTPUT_DELAYED")].as_bool();
+        } else if (cell.second->type == id_SB_I2C) {
+            bool sda_in_dly = !cell.second->attrs.count(id_SDA_INPUT_DELAYED) ||
+                              cell.second->attrs[id_SDA_INPUT_DELAYED].as_bool();
+            bool sda_out_dly = !cell.second->attrs.count(id_SDA_OUTPUT_DELAYED) ||
+                               cell.second->attrs[id_SDA_OUTPUT_DELAYED].as_bool();
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_INPUT_DELAYED", sda_in_dly,
                         "IpConfig.");
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_OUTPUT_DELAYED", sda_out_dly,
@@ -656,7 +656,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                         "IpConfig.");
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "I2C_ENABLE_1", true,
                         "IpConfig.");
-        } else if (cell.second->type == ctx->id("SB_SPI")) {
+        } else if (cell.second->type == id_SB_SPI) {
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_0", true,
                         "IpConfig.");
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_1", true,
@@ -665,7 +665,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                         "IpConfig.");
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_3", true,
                         "IpConfig.");
-        } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) {
+        } else if (cell.second->type == id_ICESTORM_SPRAM) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K);
@@ -688,7 +688,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                     NPNR_ASSERT(false);
                 }
             }
-        } else if (cell.second->type == ctx->id("ICESTORM_DSP")) {
+        } else if (cell.second->type == id_ICESTORM_DSP) {
             const std::vector<std::pair<std::string, int>> mac16_params = {{"C_REG", 1},
                                                                            {"A_REG", 1},
                                                                            {"B_REG", 1},
@@ -709,13 +709,13 @@ void write_asc(const Context *ctx, std::ostream &out)
                                                                            {"A_SIGNED", 1},
                                                                            {"B_SIGNED", 1}};
             configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig."));
-        } else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) {
+        } else if (cell.second->type == id_ICESTORM_HFOSC) {
             std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}};
             if (ctx->args.type != ArchArgs::U4K && ctx->args.type != ArchArgs::U1K && ctx->args.type != ArchArgs::U2K)
                 hfosc_params.push_back(std::pair<std::string, int>("TRIM_EN", 1));
             configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig."));
 
-        } else if (cell.second->type == ctx->id("ICESTORM_PLL")) {
+        } else if (cell.second->type == id_ICESTORM_PLL) {
             const std::vector<std::pair<std::string, int>> pll_params = {{"DELAY_ADJMODE_FB", 1},
                                                                          {"DELAY_ADJMODE_REL", 1},
                                                                          {"DIVF", 7},
@@ -874,7 +874,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     // Write RAM init data
     for (auto &cell : ctx->cells) {
         if (cell.second->bel != BelId()) {
-            if (cell.second->type == ctx->id("ICESTORM_RAM")) {
+            if (cell.second->type == id_ICESTORM_RAM) {
                 const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
                 int x = beli.x, y = beli.y;
                 out << ".ram_data " << x << " " << y << std::endl;
@@ -1054,7 +1054,7 @@ bool read_asc(Context *ctx, std::istream &in)
                 isUsed |= carry_set;
 
                 if (isUsed) {
-                    std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
+                    std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_ICESTORM_LC);
                     IdString name = created->name;
                     ctx->cells[name] = std::move(created);
                     ctx->bindBel(bel, ctx->cells[name].get(), STRENGTH_WEAK);
@@ -1074,7 +1074,7 @@ bool read_asc(Context *ctx, std::istream &in)
                 isUsed |= neg_trigger;
 
                 if (isUsed) {
-                    std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));
+                    std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_SB_IO);
                     IdString name = created->name;
                     ctx->cells[name] = std::move(created);
                     ctx->bindBel(bel, ctx->cells[name].get(), STRENGTH_WEAK);
@@ -1091,35 +1091,35 @@ bool read_asc(Context *ctx, std::istream &in)
 
                         if (ctx->checkBelAvail(belpin.bel)) {
                             if (ctx->getBelType(belpin.bel) == id_ICESTORM_LC) {
-                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_ICESTORM_LC);
                                 IdString name = created->name;
                                 ctx->cells[name] = std::move(created);
                                 ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);
                                 // TODO: Add port mapping to nets
                             }
                             if (ctx->getBelType(belpin.bel) == id_SB_IO) {
-                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));
+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_SB_IO);
                                 IdString name = created->name;
                                 ctx->cells[name] = std::move(created);
                                 ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);
                                 // TODO: Add port mapping to nets
                             }
                             if (ctx->getBelType(belpin.bel) == id_SB_GB) {
-                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));
+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_SB_GB);
                                 IdString name = created->name;
                                 ctx->cells[name] = std::move(created);
                                 ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);
                                 // TODO: Add port mapping to nets
                             }
                             if (ctx->getBelType(belpin.bel) == id_SB_WARMBOOT) {
-                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));
+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_SB_WARMBOOT);
                                 IdString name = created->name;
                                 ctx->cells[name] = std::move(created);
                                 ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);
                                 // TODO: Add port mapping to nets
                             }
                             if (ctx->getBelType(belpin.bel) == id_ICESTORM_LFOSC) {
-                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));
+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, id_ICESTORM_LFOSC);
                                 IdString name = created->name;
                                 ctx->cells[name] = std::move(created);
                                 ctx->bindBel(belpin.bel, ctx->cells[name].get(), STRENGTH_WEAK);
diff --git a/ice40/cells.cc b/ice40/cells.cc
index b97131a62e..a8d3034708 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -33,61 +33,61 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
             name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
     auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
 
-    if (type == ctx->id("ICESTORM_LC")) {
-        new_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
-        new_cell->params[ctx->id("NEG_CLK")] = Property::State::S0;
-        new_cell->params[ctx->id("CARRY_ENABLE")] = Property::State::S0;
-        new_cell->params[ctx->id("DFF_ENABLE")] = Property::State::S0;
-        new_cell->params[ctx->id("SET_NORESET")] = Property::State::S0;
-        new_cell->params[ctx->id("ASYNC_SR")] = Property::State::S0;
-        new_cell->params[ctx->id("CIN_CONST")] = Property::State::S0;
-        new_cell->params[ctx->id("CIN_SET")] = Property::State::S0;
-
-        new_cell->addInput(ctx->id("I0"));
-        new_cell->addInput(ctx->id("I1"));
-        new_cell->addInput(ctx->id("I2"));
-        new_cell->addInput(ctx->id("I3"));
-        new_cell->addInput(ctx->id("CIN"));
-
-        new_cell->addInput(ctx->id("CLK"));
-        new_cell->addInput(ctx->id("CEN"));
-        new_cell->addInput(ctx->id("SR"));
-
-        new_cell->addOutput(ctx->id("LO"));
-        new_cell->addOutput(ctx->id("O"));
-        new_cell->addOutput(ctx->id("COUT"));
-    } else if (type == ctx->id("SB_IO")) {
-        new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6);
-        new_cell->params[ctx->id("PULLUP")] = Property::State::S0;
-        new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
-        new_cell->params[ctx->id("IO_STANDARD")] = Property("SB_LVCMOS");
-
-        new_cell->addInout(ctx->id("PACKAGE_PIN"));
-
-        new_cell->addInput(ctx->id("LATCH_INPUT_VALUE"));
-        new_cell->addInput(ctx->id("CLOCK_ENABLE"));
-        new_cell->addInput(ctx->id("INPUT_CLK"));
-        new_cell->addInput(ctx->id("OUTPUT_CLK"));
-
-        new_cell->addInput(ctx->id("OUTPUT_ENABLE"));
-        new_cell->addInput(ctx->id("D_OUT_0"));
-        new_cell->addInput(ctx->id("D_OUT_1"));
-
-        new_cell->addOutput(ctx->id("D_IN_0"));
-        new_cell->addOutput(ctx->id("D_IN_1"));
-    } else if (type == ctx->id("ICESTORM_RAM")) {
-        new_cell->params[ctx->id("NEG_CLK_W")] = Property::State::S0;
-        new_cell->params[ctx->id("NEG_CLK_R")] = Property::State::S0;
-        new_cell->params[ctx->id("WRITE_MODE")] = Property::State::S0;
-        new_cell->params[ctx->id("READ_MODE")] = Property::State::S0;
-
-        new_cell->addInput(ctx->id("RCLK"));
-        new_cell->addInput(ctx->id("RCLKE"));
-        new_cell->addInput(ctx->id("RE"));
-
-        new_cell->addInput(ctx->id("WCLK"));
-        new_cell->addInput(ctx->id("WCLKE"));
-        new_cell->addInput(ctx->id("WE"));
+    if (type == id_ICESTORM_LC) {
+        new_cell->params[id_LUT_INIT] = Property(0, 16);
+        new_cell->params[id_NEG_CLK] = Property::State::S0;
+        new_cell->params[id_CARRY_ENABLE] = Property::State::S0;
+        new_cell->params[id_DFF_ENABLE] = Property::State::S0;
+        new_cell->params[id_SET_NORESET] = Property::State::S0;
+        new_cell->params[id_ASYNC_SR] = Property::State::S0;
+        new_cell->params[id_CIN_CONST] = Property::State::S0;
+        new_cell->params[id_CIN_SET] = Property::State::S0;
+
+        new_cell->addInput(id_I0);
+        new_cell->addInput(id_I1);
+        new_cell->addInput(id_I2);
+        new_cell->addInput(id_I3);
+        new_cell->addInput(id_CIN);
+
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_CEN);
+        new_cell->addInput(id_SR);
+
+        new_cell->addOutput(id_LO);
+        new_cell->addOutput(id_O);
+        new_cell->addOutput(id_COUT);
+    } else if (type == id_SB_IO) {
+        new_cell->params[id_PIN_TYPE] = Property(0, 6);
+        new_cell->params[id_PULLUP] = Property::State::S0;
+        new_cell->params[id_NEG_TRIGGER] = Property::State::S0;
+        new_cell->params[id_IO_STANDARD] = Property("SB_LVCMOS");
+
+        new_cell->addInout(id_PACKAGE_PIN);
+
+        new_cell->addInput(id_LATCH_INPUT_VALUE);
+        new_cell->addInput(id_CLOCK_ENABLE);
+        new_cell->addInput(id_INPUT_CLK);
+        new_cell->addInput(id_OUTPUT_CLK);
+
+        new_cell->addInput(id_OUTPUT_ENABLE);
+        new_cell->addInput(id_D_OUT_0);
+        new_cell->addInput(id_D_OUT_1);
+
+        new_cell->addOutput(id_D_IN_0);
+        new_cell->addOutput(id_D_IN_1);
+    } else if (type == id_ICESTORM_RAM) {
+        new_cell->params[id_NEG_CLK_W] = Property::State::S0;
+        new_cell->params[id_NEG_CLK_R] = Property::State::S0;
+        new_cell->params[id_WRITE_MODE] = Property::State::S0;
+        new_cell->params[id_READ_MODE] = Property::State::S0;
+
+        new_cell->addInput(id_RCLK);
+        new_cell->addInput(id_RCLKE);
+        new_cell->addInput(id_RE);
+
+        new_cell->addInput(id_WCLK);
+        new_cell->addInput(id_WCLKE);
+        new_cell->addInput(id_WE);
 
         for (int i = 0; i < 16; i++) {
             new_cell->addInput(ctx->id("WDATA_" + std::to_string(i)));
@@ -99,31 +99,31 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
             new_cell->addInput(ctx->id("RADDR_" + std::to_string(i)));
             new_cell->addInput(ctx->id("WADDR_" + std::to_string(i)));
         }
-    } else if (type == ctx->id("ICESTORM_LFOSC")) {
-        new_cell->addInput(ctx->id("CLKLFEN"));
-        new_cell->addInput(ctx->id("CLKLFPU"));
-        new_cell->addOutput(ctx->id("CLKLF"));
-        new_cell->addOutput(ctx->id("CLKLF_FABRIC"));
-    } else if (type == ctx->id("ICESTORM_HFOSC")) {
-        new_cell->params[ctx->id("CLKHF_DIV")] = Property("0b00");
-        new_cell->params[ctx->id("TRIM_EN")] = Property("0b0");
-
-        new_cell->addInput(ctx->id("CLKHFEN"));
-        new_cell->addInput(ctx->id("CLKHFPU"));
-        new_cell->addOutput(ctx->id("CLKHF"));
-        new_cell->addOutput(ctx->id("CLKHF_FABRIC"));
+    } else if (type == id_ICESTORM_LFOSC) {
+        new_cell->addInput(id_CLKLFEN);
+        new_cell->addInput(id_CLKLFPU);
+        new_cell->addOutput(id_CLKLF);
+        new_cell->addOutput(id_CLKLF_FABRIC);
+    } else if (type == id_ICESTORM_HFOSC) {
+        new_cell->params[id_CLKHF_DIV] = Property("0b00");
+        new_cell->params[id_TRIM_EN] = Property("0b0");
+
+        new_cell->addInput(id_CLKHFEN);
+        new_cell->addInput(id_CLKHFPU);
+        new_cell->addOutput(id_CLKHF);
+        new_cell->addOutput(id_CLKHF_FABRIC);
         for (int i = 0; i < 10; i++)
             new_cell->addInput(ctx->id("TRIM" + std::to_string(i)));
-    } else if (type == ctx->id("SB_GB")) {
-        new_cell->addInput(ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER"));
-        new_cell->addOutput(ctx->id("GLOBAL_BUFFER_OUTPUT"));
-    } else if (type == ctx->id("ICESTORM_SPRAM")) {
-        new_cell->addInput(ctx->id("WREN"));
-        new_cell->addInput(ctx->id("CHIPSELECT"));
-        new_cell->addInput(ctx->id("CLOCK"));
-        new_cell->addInput(ctx->id("STANDBY"));
-        new_cell->addInput(ctx->id("SLEEP"));
-        new_cell->addInput(ctx->id("POWEROFF"));
+    } else if (type == id_SB_GB) {
+        new_cell->addInput(id_USER_SIGNAL_TO_GLOBAL_BUFFER);
+        new_cell->addOutput(id_GLOBAL_BUFFER_OUTPUT);
+    } else if (type == id_ICESTORM_SPRAM) {
+        new_cell->addInput(id_WREN);
+        new_cell->addInput(id_CHIPSELECT);
+        new_cell->addInput(id_CLOCK);
+        new_cell->addInput(id_STANDBY);
+        new_cell->addInput(id_SLEEP);
+        new_cell->addInput(id_POWEROFF);
 
         for (int i = 0; i < 16; i++) {
             new_cell->addInput(ctx->id("DATAIN_" + std::to_string(i)));
@@ -135,196 +135,196 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         for (int i = 0; i < 4; i++) {
             new_cell->addInput(ctx->id("MASKWREN_" + std::to_string(i)));
         }
-    } else if (type == ctx->id("ICESTORM_DSP")) {
-        new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
-
-        new_cell->params[ctx->id("C_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("A_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("B_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("D_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("TOP_8x8_MULT_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("BOT_8x8_MULT_REG")] = Property::State::S0;
-        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG1")] = Property::State::S0;
-        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG2")] = Property::State::S0;
-
-        new_cell->params[ctx->id("TOPOUTPUT_SELECT")] = Property(0, 2);
-        new_cell->params[ctx->id("TOPADDSUB_LOWERINPUT")] = Property(0, 2);
-        new_cell->params[ctx->id("TOPADDSUB_UPPERINPUT")] = Property::State::S0;
-        new_cell->params[ctx->id("TOPADDSUB_CARRYSELECT")] = Property(0, 2);
-
-        new_cell->params[ctx->id("BOTOUTPUT_SELECT")] = Property(0, 2);
-        new_cell->params[ctx->id("BOTADDSUB_LOWERINPUT")] = Property(0, 2);
-        new_cell->params[ctx->id("BOTADDSUB_UPPERINPUT")] = Property::State::S0;
-        new_cell->params[ctx->id("BOTADDSUB_CARRYSELECT")] = Property(0, 2);
-
-        new_cell->params[ctx->id("MODE_8x8")] = Property::State::S0;
-        new_cell->params[ctx->id("A_SIGNED")] = Property::State::S0;
-        new_cell->params[ctx->id("B_SIGNED")] = Property::State::S0;
-
-        new_cell->addInput(ctx->id("CLK"));
-        new_cell->addInput(ctx->id("CE"));
+    } else if (type == id_ICESTORM_DSP) {
+        new_cell->params[id_NEG_TRIGGER] = Property::State::S0;
+
+        new_cell->params[id_C_REG] = Property::State::S0;
+        new_cell->params[id_A_REG] = Property::State::S0;
+        new_cell->params[id_B_REG] = Property::State::S0;
+        new_cell->params[id_D_REG] = Property::State::S0;
+        new_cell->params[id_TOP_8x8_MULT_REG] = Property::State::S0;
+        new_cell->params[id_BOT_8x8_MULT_REG] = Property::State::S0;
+        new_cell->params[id_PIPELINE_16x16_MULT_REG1] = Property::State::S0;
+        new_cell->params[id_PIPELINE_16x16_MULT_REG2] = Property::State::S0;
+
+        new_cell->params[id_TOPOUTPUT_SELECT] = Property(0, 2);
+        new_cell->params[id_TOPADDSUB_LOWERINPUT] = Property(0, 2);
+        new_cell->params[id_TOPADDSUB_UPPERINPUT] = Property::State::S0;
+        new_cell->params[id_TOPADDSUB_CARRYSELECT] = Property(0, 2);
+
+        new_cell->params[id_BOTOUTPUT_SELECT] = Property(0, 2);
+        new_cell->params[id_BOTADDSUB_LOWERINPUT] = Property(0, 2);
+        new_cell->params[id_BOTADDSUB_UPPERINPUT] = Property::State::S0;
+        new_cell->params[id_BOTADDSUB_CARRYSELECT] = Property(0, 2);
+
+        new_cell->params[id_MODE_8x8] = Property::State::S0;
+        new_cell->params[id_A_SIGNED] = Property::State::S0;
+        new_cell->params[id_B_SIGNED] = Property::State::S0;
+
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_CE);
         for (int i = 0; i < 16; i++) {
             new_cell->addInput(ctx->id("C_" + std::to_string(i)));
             new_cell->addInput(ctx->id("A_" + std::to_string(i)));
             new_cell->addInput(ctx->id("B_" + std::to_string(i)));
             new_cell->addInput(ctx->id("D_" + std::to_string(i)));
         }
-        new_cell->addInput(ctx->id("AHOLD"));
-        new_cell->addInput(ctx->id("BHOLD"));
-        new_cell->addInput(ctx->id("CHOLD"));
-        new_cell->addInput(ctx->id("DHOLD"));
+        new_cell->addInput(id_AHOLD);
+        new_cell->addInput(id_BHOLD);
+        new_cell->addInput(id_CHOLD);
+        new_cell->addInput(id_DHOLD);
 
-        new_cell->addInput(ctx->id("IRSTTOP"));
-        new_cell->addInput(ctx->id("IRSTBOT"));
-        new_cell->addInput(ctx->id("ORSTTOP"));
-        new_cell->addInput(ctx->id("ORSTBOT"));
+        new_cell->addInput(id_IRSTTOP);
+        new_cell->addInput(id_IRSTBOT);
+        new_cell->addInput(id_ORSTTOP);
+        new_cell->addInput(id_ORSTBOT);
 
-        new_cell->addInput(ctx->id("OLOADTOP"));
-        new_cell->addInput(ctx->id("OLOADBOT"));
+        new_cell->addInput(id_OLOADTOP);
+        new_cell->addInput(id_OLOADBOT);
 
-        new_cell->addInput(ctx->id("ADDSUBTOP"));
-        new_cell->addInput(ctx->id("ADDSUBBOT"));
+        new_cell->addInput(id_ADDSUBTOP);
+        new_cell->addInput(id_ADDSUBBOT);
 
-        new_cell->addInput(ctx->id("OHOLDTOP"));
-        new_cell->addInput(ctx->id("OHOLDBOT"));
+        new_cell->addInput(id_OHOLDTOP);
+        new_cell->addInput(id_OHOLDBOT);
 
-        new_cell->addInput(ctx->id("CI"));
-        new_cell->addInput(ctx->id("ACCUMCI"));
-        new_cell->addInput(ctx->id("SIGNEXTIN"));
+        new_cell->addInput(id_CI);
+        new_cell->addInput(id_ACCUMCI);
+        new_cell->addInput(id_SIGNEXTIN);
 
         for (int i = 0; i < 32; i++) {
             new_cell->addOutput(ctx->id("O_" + std::to_string(i)));
         }
 
-        new_cell->addOutput(ctx->id("CO"));
-        new_cell->addOutput(ctx->id("ACCUMCO"));
-        new_cell->addOutput(ctx->id("SIGNEXTOUT"));
+        new_cell->addOutput(id_CO);
+        new_cell->addOutput(id_ACCUMCO);
+        new_cell->addOutput(id_SIGNEXTOUT);
 
-    } else if (type == ctx->id("ICESTORM_PLL")) {
-        new_cell->params[ctx->id("DELAY_ADJMODE_FB")] = Property::State::S0;
-        new_cell->params[ctx->id("DELAY_ADJMODE_REL")] = Property::State::S0;
+    } else if (type == id_ICESTORM_PLL) {
+        new_cell->params[id_DELAY_ADJMODE_FB] = Property::State::S0;
+        new_cell->params[id_DELAY_ADJMODE_REL] = Property::State::S0;
 
-        new_cell->params[ctx->id("DIVF")] = Property(0, 7);
-        new_cell->params[ctx->id("DIVQ")] = Property(0, 3);
-        new_cell->params[ctx->id("DIVR")] = Property(0, 4);
+        new_cell->params[id_DIVF] = Property(0, 7);
+        new_cell->params[id_DIVQ] = Property(0, 3);
+        new_cell->params[id_DIVR] = Property(0, 4);
 
-        new_cell->params[ctx->id("FDA_FEEDBACK")] = Property(0, 4);
-        new_cell->params[ctx->id("FDA_RELATIVE")] = Property(0, 4);
-        new_cell->params[ctx->id("FEEDBACK_PATH")] = Property(1, 3);
-        new_cell->params[ctx->id("FILTER_RANGE")] = Property(0, 3);
+        new_cell->params[id_FDA_FEEDBACK] = Property(0, 4);
+        new_cell->params[id_FDA_RELATIVE] = Property(0, 4);
+        new_cell->params[id_FEEDBACK_PATH] = Property(1, 3);
+        new_cell->params[id_FILTER_RANGE] = Property(0, 3);
 
-        new_cell->params[ctx->id("PLLOUT_SELECT_A")] = Property(0, 2);
-        new_cell->params[ctx->id("PLLOUT_SELECT_B")] = Property(0, 2);
+        new_cell->params[id_PLLOUT_SELECT_A] = Property(0, 2);
+        new_cell->params[id_PLLOUT_SELECT_B] = Property(0, 2);
 
-        new_cell->params[ctx->id("PLLTYPE")] = Property(0, 3);
-        new_cell->params[ctx->id("SHIFTREG_DIVMODE")] = Property::State::S0;
-        new_cell->params[ctx->id("TEST_MODE")] = Property::State::S0;
+        new_cell->params[id_PLLTYPE] = Property(0, 3);
+        new_cell->params[id_SHIFTREG_DIVMODE] = Property::State::S0;
+        new_cell->params[id_TEST_MODE] = Property::State::S0;
 
-        new_cell->addInput(ctx->id("BYPASS"));
+        new_cell->addInput(id_BYPASS);
         for (int i = 0; i < 8; i++)
             new_cell->addInput(ctx->id("DYNAMICDELAY_" + std::to_string(i)));
-        new_cell->addInput(ctx->id("EXTFEEDBACK"));
-        new_cell->addInput(ctx->id("LATCHINPUTVALUE"));
-        new_cell->addInput(ctx->id("REFERENCECLK"));
-        new_cell->addInput(ctx->id("RESETB"));
-
-        new_cell->addInput(ctx->id("SCLK"));
-        new_cell->addInput(ctx->id("SDI"));
-        new_cell->addOutput(ctx->id("SDO"));
-
-        new_cell->addOutput(ctx->id("LOCK"));
-        new_cell->addOutput(ctx->id("PLLOUT_A"));
-        new_cell->addOutput(ctx->id("PLLOUT_B"));
-        new_cell->addOutput(ctx->id("PLLOUT_A_GLOBAL"));
-        new_cell->addOutput(ctx->id("PLLOUT_B_GLOBAL"));
-    } else if (type == ctx->id("SB_RGBA_DRV")) {
-        new_cell->params[ctx->id("CURRENT_MODE")] = std::string("0b0");
-        new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
-        new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
-        new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
-
-        new_cell->addInput(ctx->id("CURREN"));
-        new_cell->addInput(ctx->id("RGBLEDEN"));
-        new_cell->addInput(ctx->id("RGB0PWM"));
-        new_cell->addInput(ctx->id("RGB1PWM"));
-        new_cell->addInput(ctx->id("RGB2PWM"));
-        new_cell->addOutput(ctx->id("RGB0"));
-        new_cell->addOutput(ctx->id("RGB1"));
-        new_cell->addOutput(ctx->id("RGB2"));
-    } else if (type == ctx->id("SB_LED_DRV_CUR")) {
-        new_cell->addInput(ctx->id("EN"));
-        new_cell->addOutput(ctx->id("LEDPU"));
-    } else if (type == ctx->id("SB_RGB_DRV")) {
-        new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
-        new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
-        new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
-
-        new_cell->addInput(ctx->id("RGBPU"));
-        new_cell->addInput(ctx->id("RGBLEDEN"));
-        new_cell->addInput(ctx->id("RGB0PWM"));
-        new_cell->addInput(ctx->id("RGB1PWM"));
-        new_cell->addInput(ctx->id("RGB2PWM"));
-        new_cell->addOutput(ctx->id("RGB0"));
-        new_cell->addOutput(ctx->id("RGB1"));
-        new_cell->addOutput(ctx->id("RGB2"));
-    } else if (type == ctx->id("SB_LEDDA_IP")) {
-        new_cell->addInput(ctx->id("LEDDCS"));
-        new_cell->addInput(ctx->id("LEDDCLK"));
+        new_cell->addInput(id_EXTFEEDBACK);
+        new_cell->addInput(id_LATCHINPUTVALUE);
+        new_cell->addInput(id_REFERENCECLK);
+        new_cell->addInput(id_RESETB);
+
+        new_cell->addInput(id_SCLK);
+        new_cell->addInput(id_SDI);
+        new_cell->addOutput(id_SDO);
+
+        new_cell->addOutput(id_LOCK);
+        new_cell->addOutput(id_PLLOUT_A);
+        new_cell->addOutput(id_PLLOUT_B);
+        new_cell->addOutput(id_PLLOUT_A_GLOBAL);
+        new_cell->addOutput(id_PLLOUT_B_GLOBAL);
+    } else if (type == id_SB_RGBA_DRV) {
+        new_cell->params[id_CURRENT_MODE] = std::string("0b0");
+        new_cell->params[id_RGB0_CURRENT] = std::string("0b000000");
+        new_cell->params[id_RGB1_CURRENT] = std::string("0b000000");
+        new_cell->params[id_RGB2_CURRENT] = std::string("0b000000");
+
+        new_cell->addInput(id_CURREN);
+        new_cell->addInput(id_RGBLEDEN);
+        new_cell->addInput(id_RGB0PWM);
+        new_cell->addInput(id_RGB1PWM);
+        new_cell->addInput(id_RGB2PWM);
+        new_cell->addOutput(id_RGB0);
+        new_cell->addOutput(id_RGB1);
+        new_cell->addOutput(id_RGB2);
+    } else if (type == id_SB_LED_DRV_CUR) {
+        new_cell->addInput(id_EN);
+        new_cell->addOutput(id_LEDPU);
+    } else if (type == id_SB_RGB_DRV) {
+        new_cell->params[id_RGB0_CURRENT] = std::string("0b000000");
+        new_cell->params[id_RGB1_CURRENT] = std::string("0b000000");
+        new_cell->params[id_RGB2_CURRENT] = std::string("0b000000");
+
+        new_cell->addInput(id_RGBPU);
+        new_cell->addInput(id_RGBLEDEN);
+        new_cell->addInput(id_RGB0PWM);
+        new_cell->addInput(id_RGB1PWM);
+        new_cell->addInput(id_RGB2PWM);
+        new_cell->addOutput(id_RGB0);
+        new_cell->addOutput(id_RGB1);
+        new_cell->addOutput(id_RGB2);
+    } else if (type == id_SB_LEDDA_IP) {
+        new_cell->addInput(id_LEDDCS);
+        new_cell->addInput(id_LEDDCLK);
         for (int i = 0; i < 8; i++)
             new_cell->addInput(ctx->id("LEDDDAT" + std::to_string(i)));
         for (int i = 0; i < 3; i++)
             new_cell->addInput(ctx->id("LEDDADDR" + std::to_string(i)));
-        new_cell->addInput(ctx->id("LEDDDEN"));
-        new_cell->addInput(ctx->id("LEDDEXE"));
-        new_cell->addInput(ctx->id("LEDDRST")); // doesn't actually exist, for icecube code compatibility
-                                                // only
-        new_cell->addOutput(ctx->id("PWMOUT0"));
-        new_cell->addOutput(ctx->id("PWMOUT1"));
-        new_cell->addOutput(ctx->id("PWMOUT2"));
-        new_cell->addOutput(ctx->id("LEDDON"));
-    } else if (type == ctx->id("SB_I2C")) {
-        new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = std::string("0b1111100001");
-        new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0001");
+        new_cell->addInput(id_LEDDDEN);
+        new_cell->addInput(id_LEDDEXE);
+        new_cell->addInput(id_LEDDRST); // doesn't actually exist, for icecube code compatibility
+                                        // only
+        new_cell->addOutput(id_PWMOUT0);
+        new_cell->addOutput(id_PWMOUT1);
+        new_cell->addOutput(id_PWMOUT2);
+        new_cell->addOutput(id_LEDDON);
+    } else if (type == id_SB_I2C) {
+        new_cell->params[id_I2C_SLAVE_INIT_ADDR] = std::string("0b1111100001");
+        new_cell->params[id_BUS_ADDR74] = std::string("0b0001");
         for (int i = 0; i < 8; i++) {
             new_cell->addInput(ctx->id("SBADRI" + std::to_string(i)));
             new_cell->addInput(ctx->id("SBDATI" + std::to_string(i)));
             new_cell->addOutput(ctx->id("SBDATO" + std::to_string(i)));
         }
-        new_cell->addInput(ctx->id("SBCLKI"));
-        new_cell->addInput(ctx->id("SBRWI"));
-        new_cell->addInput(ctx->id("SBSTBI"));
-        new_cell->addInput(ctx->id("SCLI"));
-        new_cell->addInput(ctx->id("SDAI"));
-        new_cell->addOutput(ctx->id("SBACKO"));
-        new_cell->addOutput(ctx->id("I2CIRQ"));
-        new_cell->addOutput(ctx->id("I2CWKUP"));
-        new_cell->addOutput(ctx->id("SCLO"));
-        new_cell->addOutput(ctx->id("SCLOE"));
-        new_cell->addOutput(ctx->id("SDAO"));
-        new_cell->addOutput(ctx->id("SDAOE"));
-    } else if (type == ctx->id("SB_SPI")) {
-        new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0000");
+        new_cell->addInput(id_SBCLKI);
+        new_cell->addInput(id_SBRWI);
+        new_cell->addInput(id_SBSTBI);
+        new_cell->addInput(id_SCLI);
+        new_cell->addInput(id_SDAI);
+        new_cell->addOutput(id_SBACKO);
+        new_cell->addOutput(id_I2CIRQ);
+        new_cell->addOutput(id_I2CWKUP);
+        new_cell->addOutput(id_SCLO);
+        new_cell->addOutput(id_SCLOE);
+        new_cell->addOutput(id_SDAO);
+        new_cell->addOutput(id_SDAOE);
+    } else if (type == id_SB_SPI) {
+        new_cell->params[id_BUS_ADDR74] = std::string("0b0000");
         for (int i = 0; i < 8; i++) {
             new_cell->addInput(ctx->id("SBADRI" + std::to_string(i)));
             new_cell->addInput(ctx->id("SBDATI" + std::to_string(i)));
             new_cell->addOutput(ctx->id("SBDATO" + std::to_string(i)));
         }
-        new_cell->addInput(ctx->id("SBCLKI"));
-        new_cell->addInput(ctx->id("SBRWI"));
-        new_cell->addInput(ctx->id("SBSTBI"));
-        new_cell->addInput(ctx->id("MI"));
-        new_cell->addInput(ctx->id("SI"));
-        new_cell->addInput(ctx->id("SCKI"));
-        new_cell->addInput(ctx->id("SCSNI"));
-        new_cell->addOutput(ctx->id("SBACKO"));
-        new_cell->addOutput(ctx->id("SPIIRQ"));
-        new_cell->addOutput(ctx->id("SPIWKUP"));
-        new_cell->addOutput(ctx->id("SO"));
-        new_cell->addOutput(ctx->id("SOE"));
-        new_cell->addOutput(ctx->id("MO"));
-        new_cell->addOutput(ctx->id("MOE"));
-        new_cell->addOutput(ctx->id("SCKO"));
-        new_cell->addOutput(ctx->id("SCKOE"));
+        new_cell->addInput(id_SBCLKI);
+        new_cell->addInput(id_SBRWI);
+        new_cell->addInput(id_SBSTBI);
+        new_cell->addInput(id_MI);
+        new_cell->addInput(id_SI);
+        new_cell->addInput(id_SCKI);
+        new_cell->addInput(id_SCSNI);
+        new_cell->addOutput(id_SBACKO);
+        new_cell->addOutput(id_SPIIRQ);
+        new_cell->addOutput(id_SPIWKUP);
+        new_cell->addOutput(id_SO);
+        new_cell->addOutput(id_SOE);
+        new_cell->addOutput(id_MO);
+        new_cell->addOutput(id_MOE);
+        new_cell->addOutput(id_SCKO);
+        new_cell->addOutput(id_SCKOE);
         for (int i = 0; i < 4; i++) {
             new_cell->addOutput(ctx->id("MCSNO" + std::to_string(i)));
             new_cell->addOutput(ctx->id("MCSNOE" + std::to_string(i)));
@@ -339,14 +339,14 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 {
     if (lc->hierpath == IdString())
         lc->hierpath = lut->hierpath;
-    lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")].extract(0, 16, Property::State::S0);
-    replace_port(lut, ctx->id("I0"), lc, ctx->id("I0"));
-    replace_port(lut, ctx->id("I1"), lc, ctx->id("I1"));
-    replace_port(lut, ctx->id("I2"), lc, ctx->id("I2"));
-    replace_port(lut, ctx->id("I3"), lc, ctx->id("I3"));
+    lc->params[id_LUT_INIT] = lut->params[id_LUT_INIT].extract(0, 16, Property::State::S0);
+    replace_port(lut, id_I0, lc, id_I0);
+    replace_port(lut, id_I1, lc, id_I1);
+    replace_port(lut, id_I2, lc, id_I2);
+    replace_port(lut, id_I3, lc, id_I3);
     if (no_dff) {
-        replace_port(lut, ctx->id("O"), lc, ctx->id("O"));
-        lc->params[ctx->id("DFF_ENABLE")] = Property::State::S0;
+        replace_port(lut, id_O, lc, id_O);
+        lc->params[id_DFF_ENABLE] = Property::State::S0;
     }
 }
 
@@ -354,20 +354,20 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 {
     if (lc->hierpath == IdString())
         lc->hierpath = dff->hierpath;
-    lc->params[ctx->id("DFF_ENABLE")] = Property::State::S1;
+    lc->params[id_DFF_ENABLE] = Property::State::S1;
     std::string config = dff->type.str(ctx).substr(6);
     auto citer = config.begin();
-    replace_port(dff, ctx->id("C"), lc, ctx->id("CLK"));
+    replace_port(dff, id_C, lc, id_CLK);
 
     if (citer != config.end() && *citer == 'N') {
-        lc->params[ctx->id("NEG_CLK")] = Property::State::S1;
+        lc->params[id_NEG_CLK] = Property::State::S1;
         ++citer;
     } else {
-        lc->params[ctx->id("NEG_CLK")] = Property::State::S0;
+        lc->params[id_NEG_CLK] = Property::State::S0;
     }
 
     if (citer != config.end() && *citer == 'E') {
-        replace_port(dff, ctx->id("E"), lc, ctx->id("CEN"));
+        replace_port(dff, id_E, lc, id_CEN);
         ++citer;
     }
 
@@ -375,60 +375,60 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
         if ((config.end() - citer) >= 2) {
             char c = *(citer++);
             NPNR_ASSERT(c == 'S');
-            lc->params[ctx->id("ASYNC_SR")] = Property::State::S0;
+            lc->params[id_ASYNC_SR] = Property::State::S0;
         } else {
-            lc->params[ctx->id("ASYNC_SR")] = Property::State::S1;
+            lc->params[id_ASYNC_SR] = Property::State::S1;
         }
 
         if (*citer == 'S') {
             citer++;
-            replace_port(dff, ctx->id("S"), lc, ctx->id("SR"));
-            lc->params[ctx->id("SET_NORESET")] = Property::State::S1;
+            replace_port(dff, id_S, lc, id_SR);
+            lc->params[id_SET_NORESET] = Property::State::S1;
         } else {
             NPNR_ASSERT(*citer == 'R');
             citer++;
-            replace_port(dff, ctx->id("R"), lc, ctx->id("SR"));
-            lc->params[ctx->id("SET_NORESET")] = Property::State::S0;
+            replace_port(dff, id_R, lc, id_SR);
+            lc->params[id_SET_NORESET] = Property::State::S0;
         }
     }
 
     NPNR_ASSERT(citer == config.end());
 
     if (pass_thru_lut) {
-        lc->params[ctx->id("LUT_INIT")] = Property(2, 16);
-        replace_port(dff, ctx->id("D"), lc, ctx->id("I0"));
+        lc->params[id_LUT_INIT] = Property(2, 16);
+        replace_port(dff, id_D, lc, id_I0);
     }
 
-    replace_port(dff, ctx->id("Q"), lc, ctx->id("O"));
+    replace_port(dff, id_Q, lc, id_O);
 }
 
 void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
-        sbio->params[ctx->id("PIN_TYPE")] = 1;
-        auto pu_attr = nxio->attrs.find(ctx->id("PULLUP"));
+        sbio->params[id_PIN_TYPE] = 1;
+        auto pu_attr = nxio->attrs.find(id_PULLUP);
         if (pu_attr != nxio->attrs.end())
-            sbio->params[ctx->id("PULLUP")] = pu_attr->second;
-        replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0"));
+            sbio->params[id_PULLUP] = pu_attr->second;
+        replace_port(nxio, id_O, sbio, id_D_IN_0);
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
-        sbio->params[ctx->id("PIN_TYPE")] = 25;
-        replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
+        sbio->params[id_PIN_TYPE] = 25;
+        replace_port(nxio, id_I, sbio, id_D_OUT_0);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+        NetInfo *i = get_net_or_empty(nxio, id_I);
         if (i == nullptr || i->driver.cell == nullptr)
-            sbio->params[ctx->id("PIN_TYPE")] = 1;
+            sbio->params[id_PIN_TYPE] = 1;
         else
-            sbio->params[ctx->id("PIN_TYPE")] = 25;
-        auto pu_attr = nxio->attrs.find(ctx->id("PULLUP"));
+            sbio->params[id_PIN_TYPE] = 25;
+        auto pu_attr = nxio->attrs.find(id_PULLUP);
         if (pu_attr != nxio->attrs.end())
-            sbio->params[ctx->id("PULLUP")] = pu_attr->second;
-        replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
-        replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0"));
+            sbio->params[id_PULLUP] = pu_attr->second;
+        replace_port(nxio, id_I, sbio, id_D_OUT_0);
+        replace_port(nxio, id_O, sbio, id_D_IN_0);
     } else {
         NPNR_ASSERT(false);
     }
-    NetInfo *donet = sbio->ports.at(ctx->id("D_OUT_0")).net, *dinet = sbio->ports.at(ctx->id("D_IN_0")).net;
+    NetInfo *donet = sbio->ports.at(id_D_OUT_0).net, *dinet = sbio->ports.at(id_D_IN_0).net;
 
     // Rename I/O nets to avoid conflicts
     if (donet != nullptr && donet->name == nxio->name)
@@ -451,17 +451,17 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         NPNR_ASSERT(!ctx->nets.count(tn_netname));
         ctx->net_aliases.erase(tn_netname);
         NetInfo *toplevel_net = ctx->createNet(tn_netname);
-        connect_port(ctx, toplevel_net, sbio, ctx->id("PACKAGE_PIN"));
+        connect_port(ctx, toplevel_net, sbio, id_PACKAGE_PIN);
         ctx->ports[nxio->name].net = toplevel_net;
     }
 
     CellInfo *tbuf = net_driven_by(
             ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
-            ctx->id("Y"));
+            id_Y);
     if (tbuf) {
-        sbio->params[ctx->id("PIN_TYPE")] = 41;
-        replace_port(tbuf, ctx->id("A"), sbio, ctx->id("D_OUT_0"));
-        replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE"));
+        sbio->params[id_PIN_TYPE] = 41;
+        replace_port(tbuf, id_A, sbio, id_D_OUT_0);
+        replace_port(tbuf, id_E, sbio, id_OUTPUT_ENABLE);
 
         if (donet->users.size() > 1) {
             for (auto user : donet->users)
@@ -477,15 +477,15 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
 
 uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell)
 {
-    if (cell->type == ctx->id("SB_PLL40_PAD"))
+    if (cell->type == id_SB_PLL40_PAD)
         return 2;
-    if (cell->type == ctx->id("SB_PLL40_2_PAD"))
+    if (cell->type == id_SB_PLL40_2_PAD)
         return 4;
-    if (cell->type == ctx->id("SB_PLL40_2F_PAD"))
+    if (cell->type == id_SB_PLL40_2F_PAD)
         return 6;
-    if (cell->type == ctx->id("SB_PLL40_CORE"))
+    if (cell->type == id_SB_PLL40_CORE)
         return 3;
-    if (cell->type == ctx->id("SB_PLL40_2F_CORE"))
+    if (cell->type == id_SB_PLL40_2F_CORE)
         return 7;
     NPNR_ASSERT(0);
 }
@@ -495,15 +495,14 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell == nullptr)
         return false;
     if (is_ff(ctx, port.cell))
-        return port.port == ctx->id("C");
-    if (port.cell->type == ctx->id("ICESTORM_LC"))
-        return port.port == ctx->id("CLK");
-    if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
-        return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK") || port.port == ctx->id("RCLKN") ||
-               port.port == ctx->id("WCLKN");
-    if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP"))
-        return port.port == ctx->id("CLK");
-    if (is_sb_spram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_SPRAM"))
+        return port.port == id_C;
+    if (port.cell->type == id_ICESTORM_LC)
+        return port.port == id_CLK;
+    if (is_ram(ctx, port.cell) || port.cell->type == id_ICESTORM_RAM)
+        return port.port == id_RCLK || port.port == id_WCLK || port.port == id_RCLKN || port.port == id_WCLKN;
+    if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP)
+        return port.port == id_CLK;
+    if (is_sb_spram(ctx, port.cell) || port.cell->type == id_ICESTORM_SPRAM)
         return port.port == id_CLOCK;
     if (is_sb_io(ctx, port.cell))
         return port.port == id_INPUT_CLK || port.port == id_OUTPUT_CLK;
@@ -515,12 +514,11 @@ bool is_reset_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell == nullptr)
         return false;
     if (is_ff(ctx, port.cell))
-        return port.port == ctx->id("R") || port.port == ctx->id("S");
-    if (port.cell->type == ctx->id("ICESTORM_LC"))
-        return port.port == ctx->id("SR");
-    if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP"))
-        return port.port == ctx->id("IRSTTOP") || port.port == ctx->id("IRSTBOT") || port.port == ctx->id("ORSTTOP") ||
-               port.port == ctx->id("ORSTBOT");
+        return port.port == id_R || port.port == id_S;
+    if (port.cell->type == id_ICESTORM_LC)
+        return port.port == id_SR;
+    if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP)
+        return port.port == id_IRSTTOP || port.port == id_IRSTBOT || port.port == id_ORSTTOP || port.port == id_ORSTBOT;
     return false;
 }
 
@@ -529,12 +527,12 @@ bool is_enable_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell == nullptr)
         return false;
     if (is_ff(ctx, port.cell))
-        return port.port == ctx->id("E");
-    if (port.cell->type == ctx->id("ICESTORM_LC"))
-        return port.port == ctx->id("CEN");
+        return port.port == id_E;
+    if (port.cell->type == id_ICESTORM_LC)
+        return port.port == id_CEN;
     // FIXME
-    // if (is_sb_mac16(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_DSP"))
-    //    return port.port == ctx->id("CE");
+    // if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP)
+    //    return port.port == id_CE;
     return false;
 }
 
diff --git a/ice40/cells.h b/ice40/cells.h
index 30fdd63167..724500d66c 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -30,90 +30,80 @@ NEXTPNR_NAMESPACE_BEGIN
 std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LUT4"); }
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LUT4; }
 
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_DFF") || cell->type == ctx->id("SB_DFFE") || cell->type == ctx->id("SB_DFFSR") ||
-           cell->type == ctx->id("SB_DFFR") || cell->type == ctx->id("SB_DFFSS") || cell->type == ctx->id("SB_DFFS") ||
-           cell->type == ctx->id("SB_DFFESR") || cell->type == ctx->id("SB_DFFER") ||
-           cell->type == ctx->id("SB_DFFESS") || cell->type == ctx->id("SB_DFFES") ||
-           cell->type == ctx->id("SB_DFFN") || cell->type == ctx->id("SB_DFFNE") ||
-           cell->type == ctx->id("SB_DFFNSR") || cell->type == ctx->id("SB_DFFNR") ||
-           cell->type == ctx->id("SB_DFFNSS") || cell->type == ctx->id("SB_DFFNS") ||
-           cell->type == ctx->id("SB_DFFNESR") || cell->type == ctx->id("SB_DFFNER") ||
-           cell->type == ctx->id("SB_DFFNESS") || cell->type == ctx->id("SB_DFFNES");
+    return cell->type == id_SB_DFF || cell->type == id_SB_DFFE || cell->type == id_SB_DFFSR ||
+           cell->type == id_SB_DFFR || cell->type == id_SB_DFFSS || cell->type == id_SB_DFFS ||
+           cell->type == id_SB_DFFESR || cell->type == id_SB_DFFER || cell->type == id_SB_DFFESS ||
+           cell->type == id_SB_DFFES || cell->type == id_SB_DFFN || cell->type == id_SB_DFFNE ||
+           cell->type == id_SB_DFFNSR || cell->type == id_SB_DFFNR || cell->type == id_SB_DFFNSS ||
+           cell->type == id_SB_DFFNS || cell->type == id_SB_DFFNESR || cell->type == id_SB_DFFNER ||
+           cell->type == id_SB_DFFNESS || cell->type == id_SB_DFFNES;
 }
 
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_CARRY"); }
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_CARRY; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("ICESTORM_LC"); }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_ICESTORM_LC; }
 
 // Return true if a cell is a SB_IO
-inline bool is_sb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_IO"); }
+inline bool is_sb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_IO; }
 
 // Return true if a cell is a SB_GB_IO
-inline bool is_sb_gb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_GB_IO"); }
+inline bool is_sb_gb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_GB_IO; }
 
 // Return true if a cell is a global buffer
-inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_GB"); }
+inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_GB; }
 
 // Return true if a cell is a RAM
 inline bool is_ram(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_RAM40_4K") || cell->type == ctx->id("SB_RAM40_4KNR") ||
-           cell->type == ctx->id("SB_RAM40_4KNW") || cell->type == ctx->id("SB_RAM40_4KNRNW");
+    return cell->type == id_SB_RAM40_4K || cell->type == id_SB_RAM40_4KNR || cell->type == id_SB_RAM40_4KNW ||
+           cell->type == id_SB_RAM40_4KNRNW;
 }
 
-inline bool is_sb_lfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LFOSC"); }
+inline bool is_sb_lfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LFOSC; }
 
-inline bool is_sb_hfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_HFOSC"); }
+inline bool is_sb_hfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_HFOSC; }
 
-inline bool is_sb_spram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_SPRAM256KA"); }
+inline bool is_sb_spram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_SPRAM256KA; }
 
-inline bool is_sb_mac16(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_MAC16"); }
+inline bool is_sb_mac16(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_MAC16; }
 
-inline bool is_sb_rgba_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_RGBA_DRV"); }
+inline bool is_sb_rgba_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_RGBA_DRV; }
 
-inline bool is_sb_rgb_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_RGB_DRV"); }
+inline bool is_sb_rgb_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_RGB_DRV; }
 
-inline bool is_sb_led_drv_cur(const BaseCtx *ctx, const CellInfo *cell)
-{
-    return cell->type == ctx->id("SB_LED_DRV_CUR");
-}
+inline bool is_sb_led_drv_cur(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LED_DRV_CUR; }
 
-inline bool is_sb_ledda_ip(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LEDDA_IP"); }
+inline bool is_sb_ledda_ip(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LEDDA_IP; }
 
-inline bool is_sb_i2c(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_I2C"); }
+inline bool is_sb_i2c(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_I2C; }
 
-inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_SPI"); }
+inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_SPI; }
 
 inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_PLL40_PAD") || cell->type == ctx->id("SB_PLL40_2_PAD") ||
-           cell->type == ctx->id("SB_PLL40_2F_PAD") || cell->type == ctx->id("SB_PLL40_CORE") ||
-           cell->type == ctx->id("SB_PLL40_2F_CORE");
+    return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD ||
+           cell->type == id_SB_PLL40_CORE || cell->type == id_SB_PLL40_2F_CORE;
 }
 
 inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_PLL40_PAD") || cell->type == ctx->id("SB_PLL40_2_PAD") ||
-           cell->type == ctx->id("SB_PLL40_2F_PAD") ||
-           (cell->type == ctx->id("ICESTORM_PLL") &&
-            (cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_PAD" ||
-             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2_PAD" ||
-             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_PAD"));
+    return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD ||
+           (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_PAD" ||
+                                              cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" ||
+                                              cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD"));
 }
 
 inline bool is_sb_pll40_dual(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == ctx->id("SB_PLL40_2_PAD") || cell->type == ctx->id("SB_PLL40_2F_PAD") ||
-           cell->type == ctx->id("SB_PLL40_2F_CORE") ||
-           (cell->type == ctx->id("ICESTORM_PLL") &&
-            (cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2_PAD" ||
-             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_PAD" ||
-             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_CORE"));
+    return cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD || cell->type == id_SB_PLL40_2F_CORE ||
+           (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" ||
+                                              cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD" ||
+                                              cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_CORE"));
 }
 
 uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell);
diff --git a/ice40/chains.cc b/ice40/chains.cc
index fa4ce413cf..e6a37044fa 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -53,9 +53,9 @@ class ChainConstrainer
                 tile.clear();
                 chains.emplace_back();
                 start_of_chain = false;
-                if (cell->ports.at(ctx->id("CIN")).net) {
+                if (cell->ports.at(id_CIN).net) {
                     // CIN is not constant and not part of a chain. Must feed in from fabric
-                    CellInfo *feedin = make_carry_feed_in(cell, cell->ports.at(ctx->id("CIN")));
+                    CellInfo *feedin = make_carry_feed_in(cell, cell->ports.at(id_CIN));
                     chains.back().cells.push_back(feedin);
                     tile.push_back(feedin);
                     ++feedio_lcs;
@@ -66,18 +66,18 @@ class ChainConstrainer
             bool split_chain = (!ctx->logic_cells_compatible(tile.data(), tile.size())) ||
                                (int(chains.back().cells.size()) > max_length);
             if (split_chain) {
-                CellInfo *passout = make_carry_pass_out((*(curr_cell - 1))->ports.at(ctx->id("COUT")));
+                CellInfo *passout = make_carry_pass_out((*(curr_cell - 1))->ports.at(id_COUT));
                 tile.pop_back();
                 chains.back().cells.back() = passout;
                 start_of_chain = true;
             } else {
-                NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
+                NetInfo *carry_net = cell->ports.at(id_COUT).net;
                 bool at_end = (curr_cell == carryc.cells.end() - 1);
                 if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
                     if (carry_net->users.size() > 2 ||
-                        (net_only_drives(ctx, carry_net, is_lc, ctx->id("I3"), false) !=
-                         net_only_drives(ctx, carry_net, is_lc, ctx->id("CIN"), false)) ||
-                        (at_end && !net_only_drives(ctx, carry_net, is_lc, ctx->id("I3"), true))) {
+                        (net_only_drives(ctx, carry_net, is_lc, id_I3, false) !=
+                         net_only_drives(ctx, carry_net, is_lc, id_CIN, false)) ||
+                        (at_end && !net_only_drives(ctx, carry_net, is_lc, id_I3, true))) {
                         if (ctx->debug)
                             log_info("      inserting feed-%s\n", at_end ? "out" : "out-in");
                         CellInfo *passout;
@@ -89,10 +89,10 @@ class ChainConstrainer
                             tile.pop_back();
                             if (split_chain_next)
                                 start_of_chain = true;
-                            passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")),
+                            passout = make_carry_pass_out(cell->ports.at(id_COUT),
                                                           split_chain_next ? nullptr : *(curr_cell + 1));
                         } else {
-                            passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")), nullptr);
+                            passout = make_carry_pass_out(cell->ports.at(id_COUT), nullptr);
                         }
 
                         chains.back().cells.push_back(passout);
@@ -110,9 +110,9 @@ class ChainConstrainer
     CellInfo *make_carry_pass_out(PortInfo &cout_port, CellInfo *cin_cell = nullptr)
     {
         NPNR_ASSERT(cout_port.net != nullptr);
-        std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
-        lc->params[ctx->id("LUT_INIT")] = Property(65280, 16); // 0xff00: O = I3
-        lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
+        std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, id_ICESTORM_LC);
+        lc->params[id_LUT_INIT] = Property(65280, 16); // 0xff00: O = I3
+        lc->params[id_CARRY_ENABLE] = Property::State::S1;
         lc->ports.at(id_O).net = cout_port.net;
         NetInfo *co_i3_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$I3"));
         co_i3_net->driver = cout_port.net->driver;
@@ -177,11 +177,11 @@ class ChainConstrainer
     CellInfo *make_carry_feed_in(CellInfo *cin_cell, PortInfo &cin_port)
     {
         NPNR_ASSERT(cin_port.net != nullptr);
-        std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
-        lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
-        lc->params[ctx->id("CIN_CONST")] = Property::State::S1;
-        lc->params[ctx->id("CIN_SET")] = Property::State::S1;
-        lc->ports.at(ctx->id("I1")).net = cin_port.net;
+        std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, id_ICESTORM_LC);
+        lc->params[id_CARRY_ENABLE] = Property::State::S1;
+        lc->params[id_CIN_CONST] = Property::State::S1;
+        lc->params[id_CIN_SET] = Property::State::S1;
+        lc->ports.at(id_I1).net = cin_port.net;
         cin_port.net->users.erase(std::remove_if(cin_port.net->users.begin(), cin_port.net->users.end(),
                                                  [cin_cell, cin_port](const PortRef &usr) {
                                                      return usr.cell == cin_cell && usr.port == cin_port.name;
@@ -189,16 +189,16 @@ class ChainConstrainer
 
         PortRef i1_ref;
         i1_ref.cell = lc.get();
-        i1_ref.port = ctx->id("I1");
-        lc->ports.at(ctx->id("I1")).net->users.push_back(i1_ref);
+        i1_ref.port = id_I1;
+        lc->ports.at(id_I1).net->users.push_back(i1_ref);
 
         NetInfo *out_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$O"));
 
         PortRef drv_ref;
-        drv_ref.port = ctx->id("COUT");
+        drv_ref.port = id_COUT;
         drv_ref.cell = lc.get();
         out_net->driver = drv_ref;
-        lc->ports.at(ctx->id("COUT")).net = out_net;
+        lc->ports.at(id_COUT).net = out_net;
 
         PortRef usr_ref;
         usr_ref.port = cin_port.name;
@@ -219,22 +219,19 @@ class ChainConstrainer
                 [](const Context *ctx, const
 
                    CellInfo *cell) {
-                    CellInfo *carry_prev =
-                            net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_lc, ctx->id("COUT"));
+                    CellInfo *carry_prev = net_driven_by(ctx, cell->ports.at(id_CIN).net, is_lc, id_COUT);
                     if (carry_prev != nullptr)
                         return carry_prev;
-                    CellInfo *i3_prev = net_driven_by(ctx, cell->ports.at(ctx->id("I3")).net, is_lc, ctx->id("COUT"));
+                    CellInfo *i3_prev = net_driven_by(ctx, cell->ports.at(id_I3).net, is_lc, id_COUT);
                     if (i3_prev != nullptr)
                         return i3_prev;
                     return (CellInfo *)nullptr;
                 },
                 [](const Context *ctx, const CellInfo *cell) {
-                    CellInfo *carry_next =
-                            net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, ctx->id("CIN"), false);
+                    CellInfo *carry_next = net_only_drives(ctx, cell->ports.at(id_COUT).net, is_lc, id_CIN, false);
                     if (carry_next != nullptr)
                         return carry_next;
-                    CellInfo *i3_next =
-                            net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, ctx->id("I3"), false);
+                    CellInfo *i3_next = net_only_drives(ctx, cell->ports.at(id_COUT).net, is_lc, id_I3, false);
                     if (i3_next != nullptr)
                         return i3_next;
                     return (CellInfo *)nullptr;
@@ -249,7 +246,7 @@ class ChainConstrainer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (chained.find(cell.first) == chained.end() && is_lc(ctx, ci) &&
-                bool_or_default(ci->params, ctx->id("CARRY_ENABLE"))) {
+                bool_or_default(ci->params, id_CARRY_ENABLE)) {
                 CellChain sChain;
                 sChain.cells.push_back(ci);
                 chained.insert(cell.first);
diff --git a/ice40/constids.inc b/ice40/constids.inc
index 6aa5c4c0c2..8bad9e2547 100644
--- a/ice40/constids.inc
+++ b/ice40/constids.inc
@@ -448,4 +448,168 @@ X(SB_RGB_DRV)
 X(DFF_ENABLE)
 X(CARRY_ENABLE)
 X(NEG_CLK)
-X(IO_STANDARD)
\ No newline at end of file
+X(IO_STANDARD)
+X(A)
+X(ASYNC_SR)
+X(A_REG)
+X(A_SIGNED)
+X(BEL)
+X(BEL_PAD_INPUT)
+X(BOTADDSUB_CARRYSELECT)
+X(BOTADDSUB_LOWERINPUT)
+X(BOTADDSUB_UPPERINPUT)
+X(BOTOUTPUT_SELECT)
+X(BOT_8x8_MULT_REG)
+X(BUS_ADDR74)
+X(B_REG)
+X(B_SIGNED)
+X(C)
+X(CARRY_IN_MUX)
+X(CIN_CONST)
+X(CIN_SET)
+X(CLKHF_DIV)
+X(CURRENT_MODE)
+X(C_REG)
+X(D)
+X(DELAY_ADJMODE_FB)
+X(DELAY_ADJMODE_REL)
+X(DELAY_ADJUSTMENT_MODE_FEEDBACK)
+X(DELAY_ADJUSTMENT_MODE_RELATIVE)
+X(DIVF)
+X(DIVQ)
+X(DIVR)
+X(D_REG)
+X(E)
+X(FDA_FEEDBACK)
+X(FDA_RELATIVE)
+X(FEEDBACK_PATH)
+X(FILTER_RANGE)
+X(FOR_PAD_IN)
+X(GLB2LOCAL)
+X(GLB_NETWK)
+X(GLOBAL)
+X(GND)
+X(GRID_X)
+X(GRID_Y)
+X(GRID_Z)
+X(I)
+X(I2C_SLAVE_INIT_ADDR)
+X(INDEX)
+X(LEDDRST)
+X(LOCAL)
+X(LUTFF_COUT)
+X(LUTFF_GLOBAL)
+X(LUTFF_IN)
+X(LUTFF_IN_LUT)
+X(LUTFF_LOUT)
+X(LUTFF_OUT)
+X(LUT_INIT)
+X(MODE_8x8)
+X(NEG_CLK_R)
+X(NEG_CLK_W)
+X(NEG_TRIGGER)
+X(PACKAGEPIN)
+X(PIN_TYPE)
+X(PIPELINE_16x16_MULT_REG1)
+X(PIPELINE_16x16_MULT_REG2)
+X(PLLOUTCORE)
+X(PLLOUTCOREA)
+X(PLLOUTCOREB)
+X(PLLOUTGLOBAL)
+X(PLLOUTGLOBALA)
+X(PLLOUTGLOBALB)
+X(PLLOUT_SELECT)
+X(PLLOUT_SELECT_A)
+X(PLLOUT_SELECT_B)
+X(PLLOUT_SELECT_PORTA)
+X(PLLOUT_SELECT_PORTB)
+X(PLLTYPE)
+X(PULLUP)
+X(PULLUP_RESISTOR)
+X(Q)
+X(R)
+X(RCLKN)
+X(READ_MODE)
+X(RGB0_CURRENT)
+X(RGB1_CURRENT)
+X(RGB2_CURRENT)
+X(ROUTE_THROUGH_FABRIC)
+X(S)
+X(SB_CARRY)
+X(SB_DFF)
+X(SB_DFFE)
+X(SB_DFFER)
+X(SB_DFFES)
+X(SB_DFFESR)
+X(SB_DFFESS)
+X(SB_DFFN)
+X(SB_DFFNE)
+X(SB_DFFNER)
+X(SB_DFFNES)
+X(SB_DFFNESR)
+X(SB_DFFNESS)
+X(SB_DFFNR)
+X(SB_DFFNS)
+X(SB_DFFNSR)
+X(SB_DFFNSS)
+X(SB_DFFR)
+X(SB_DFFS)
+X(SB_DFFSR)
+X(SB_DFFSS)
+X(SB_GB_IO)
+X(SB_HFOSC)
+X(SB_LFOSC)
+X(SB_LUT4)
+X(SB_MAC16)
+X(SB_PLL40_2F_CORE)
+X(SB_PLL40_2F_PAD)
+X(SB_PLL40_2_PAD)
+X(SB_PLL40_CORE)
+X(SB_PLL40_PAD)
+X(SB_RAM40_4K)
+X(SB_RAM40_4KNR)
+X(SB_RAM40_4KNRNW)
+X(SB_RAM40_4KNW)
+X(SB_SPRAM256KA)
+X(SDA_INPUT_DELAYED)
+X(SDA_OUTPUT_DELAYED)
+X(SET_NORESET)
+X(SHIFTREG_DIVMODE)
+X(SHIFTREG_DIV_MODE)
+X(SP12_H)
+X(SP12_V)
+X(SP4_H)
+X(SP4_V)
+X(TEST_MODE)
+X(TOPADDSUB_CARRYSELECT)
+X(TOPADDSUB_LOWERINPUT)
+X(TOPADDSUB_UPPERINPUT)
+X(TOPOUTPUT_SELECT)
+X(TOP_8x8_MULT_REG)
+X(TRIM_EN)
+X(TYPE)
+X(VCC)
+X(WCLKN)
+X(WRITE_MODE)
+X(Y)
+X(hx1k)
+X(hx4k)
+X(hx8k)
+X(lp1k)
+X(lp384)
+X(lp4k)
+X(lp8k)
+X(no_promote_globals)
+X(opt_timing)
+X(pack)
+X(pcf_allow_unconstrained)
+X(place)
+X(placer)
+X(promote_logic)
+X(route)
+X(router)
+X(u1k)
+X(u2k)
+X(u4k)
+X(up3k)
+X(up5k)
diff --git a/ice40/main.cc b/ice40/main.cc
index e480a6cede..224b027577 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -265,13 +265,13 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext(dict<std::string, Pr
 
     ctx->settings[ctx->id("arch.package")] = ctx->archArgs().package;
     if (vm.count("promote-logic"))
-        ctx->settings[ctx->id("promote_logic")] = Property::State::S1;
+        ctx->settings[id_promote_logic] = Property::State::S1;
     if (vm.count("no-promote-globals"))
-        ctx->settings[ctx->id("no_promote_globals")] = Property::State::S1;
+        ctx->settings[id_no_promote_globals] = Property::State::S1;
     if (vm.count("opt-timing"))
-        ctx->settings[ctx->id("opt_timing")] = Property::State::S1;
+        ctx->settings[id_opt_timing] = Property::State::S1;
     if (vm.count("pcf-allow-unconstrained"))
-        ctx->settings[ctx->id("pcf_allow_unconstrained")] = Property::State::S1;
+        ctx->settings[id_pcf_allow_unconstrained] = Property::State::S1;
     return ctx;
 }
 
diff --git a/ice40/pack.cc b/ice40/pack.cc
index fcbdf2bdad..0220d4fe76 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -41,7 +41,7 @@ static void pack_lut_lutffs(Context *ctx)
         if (ctx->verbose)
             log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
         if (is_lut(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_LC");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_LC, ci->name.str(ctx) + "_LC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             packed_cells.insert(ci->name);
@@ -49,14 +49,14 @@ static void pack_lut_lutffs(Context *ctx)
                 log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
             // See if we can pack into a DFF
             // TODO: LUT cascade
-            NetInfo *o = ci->ports.at(ctx->id("O")).net;
-            CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
-            auto lut_bel = ci->attrs.find(ctx->id("BEL"));
+            NetInfo *o = ci->ports.at(id_O).net;
+            CellInfo *dff = net_only_drives(ctx, o, is_ff, id_D, true);
+            auto lut_bel = ci->attrs.find(id_BEL);
             bool packed_dff = false;
             if (dff) {
                 if (ctx->verbose)
                     log_info("found attached dff %s\n", dff->name.c_str(ctx));
-                auto dff_bel = dff->attrs.find(ctx->id("BEL"));
+                auto dff_bel = dff->attrs.find(id_BEL);
                 if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
                     // Locations don't match, can't pack
                 } else {
@@ -65,10 +65,10 @@ static void pack_lut_lutffs(Context *ctx)
                     ++lut_and_ff;
                     ctx->nets.erase(o->name);
                     if (dff_bel != dff->attrs.end())
-                        packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                        packed->attrs[id_BEL] = dff_bel->second;
                     for (const auto &attr : dff->attrs) {
                         // BEL is dealt with specially
-                        if (attr.first != ctx->id("BEL"))
+                        if (attr.first != id_BEL)
                             packed->attrs[attr.first] = attr.second;
                     }
                     packed_cells.insert(dff->name);
@@ -106,8 +106,7 @@ static void pack_nonlut_ffs(Context *ctx)
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (is_ff(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "_DFFLC");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_LC, ci->name.str(ctx) + "_DFFLC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             if (ctx->verbose)
@@ -155,25 +154,25 @@ static void pack_carries(Context *ctx)
 
             CellInfo *carry_ci_lc;
             bool ci_value;
-            bool ci_const = net_is_constant(ctx, ci->ports.at(ctx->id("CI")).net, ci_value);
+            bool ci_const = net_is_constant(ctx, ci->ports.at(id_CI).net, ci_value);
             if (ci_const) {
                 carry_ci_lc = nullptr;
             } else {
-                carry_ci_lc = net_only_drives(ctx, ci->ports.at(ctx->id("CI")).net, is_lc, ctx->id("I3"), false);
+                carry_ci_lc = net_only_drives(ctx, ci->ports.at(id_CI).net, is_lc, id_I3, false);
             }
 
             std::set<IdString> i0_matches, i1_matches;
-            NetInfo *i0_net = ci->ports.at(ctx->id("I0")).net;
-            NetInfo *i1_net = ci->ports.at(ctx->id("I1")).net;
+            NetInfo *i0_net = ci->ports.at(id_I0).net;
+            NetInfo *i1_net = ci->ports.at(id_I1).net;
             // Find logic cells connected to both I0 and I1
             if (i0_net) {
                 for (auto usr : i0_net->users) {
-                    if (is_lc(ctx, usr.cell) && usr.port == ctx->id("I1")) {
+                    if (is_lc(ctx, usr.cell) && usr.port == id_I1) {
                         if (ctx->cells.find(usr.cell->name) != ctx->cells.end() &&
                             exhausted_cells.find(usr.cell->name) == exhausted_cells.end()) {
                             // This clause stops us double-packing cells
                             i0_matches.insert(usr.cell->name);
-                            if (!i1_net && !usr.cell->ports.at(ctx->id("I2")).net) {
+                            if (!i1_net && !usr.cell->ports.at(id_I2).net) {
                                 // I1 is don't care when disconnected, duplicate I0
                                 i1_matches.insert(usr.cell->name);
                             }
@@ -183,12 +182,12 @@ static void pack_carries(Context *ctx)
             }
             if (i1_net) {
                 for (auto usr : i1_net->users) {
-                    if (is_lc(ctx, usr.cell) && usr.port == ctx->id("I2")) {
+                    if (is_lc(ctx, usr.cell) && usr.port == id_I2) {
                         if (ctx->cells.find(usr.cell->name) != ctx->cells.end() &&
                             exhausted_cells.find(usr.cell->name) == exhausted_cells.end()) {
                             // This clause stops us double-packing cells
                             i1_matches.insert(usr.cell->name);
-                            if (!i0_net && !usr.cell->ports.at(ctx->id("I1")).net) {
+                            if (!i0_net && !usr.cell->ports.at(id_I1).net) {
                                 // I0 is don't care when disconnected, duplicate I1
                                 i0_matches.insert(usr.cell->name);
                             }
@@ -208,53 +207,53 @@ static void pack_carries(Context *ctx)
             } else {
                 // No LC to pack into matching I0/I1, insert a new one
                 std::unique_ptr<CellInfo> created_lc =
-                        create_ice_cell(ctx, ctx->id("ICESTORM_LC"), cell.first.str(ctx) + "$CARRY");
+                        create_ice_cell(ctx, id_ICESTORM_LC, cell.first.str(ctx) + "$CARRY");
                 carry_lc = created_lc.get();
-                created_lc->ports.at(ctx->id("I1")).net = i0_net;
+                created_lc->ports.at(id_I1).net = i0_net;
                 if (i0_net) {
                     PortRef pr;
                     pr.cell = created_lc.get();
-                    pr.port = ctx->id("I1");
+                    pr.port = id_I1;
                     i0_net->users.push_back(pr);
                 }
-                created_lc->ports.at(ctx->id("I2")).net = i1_net;
+                created_lc->ports.at(id_I2).net = i1_net;
                 if (i1_net) {
                     PortRef pr;
                     pr.cell = created_lc.get();
-                    pr.port = ctx->id("I2");
+                    pr.port = id_I2;
                     i1_net->users.push_back(pr);
                 }
                 new_cells.push_back(std::move(created_lc));
                 ++carry_only;
             }
-            carry_lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
-            replace_port(ci, ctx->id("CI"), carry_lc, ctx->id("CIN"));
-            replace_port(ci, ctx->id("CO"), carry_lc, ctx->id("COUT"));
+            carry_lc->params[id_CARRY_ENABLE] = Property::State::S1;
+            replace_port(ci, id_CI, carry_lc, id_CIN);
+            replace_port(ci, id_CO, carry_lc, id_COUT);
             if (i0_net) {
                 auto &i0_usrs = i0_net->users;
                 i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(), [ci, ctx](const PortRef &pr) {
-                    return pr.cell == ci && pr.port == ctx->id("I0");
+                    return pr.cell == ci && pr.port == id_I0;
                 }));
             }
             if (i1_net) {
                 auto &i1_usrs = i1_net->users;
                 i1_usrs.erase(std::remove_if(i1_usrs.begin(), i1_usrs.end(), [ci, ctx](const PortRef &pr) {
-                    return pr.cell == ci && pr.port == ctx->id("I1");
+                    return pr.cell == ci && pr.port == id_I1;
                 }));
             }
 
             // Check for constant driver on CIN
-            if (carry_lc->ports.at(ctx->id("CIN")).net != nullptr) {
-                IdString cin_net = carry_lc->ports.at(ctx->id("CIN")).net->name;
+            if (carry_lc->ports.at(id_CIN).net != nullptr) {
+                IdString cin_net = carry_lc->ports.at(id_CIN).net->name;
                 if (cin_net == ctx->id("$PACKER_GND_NET") || cin_net == ctx->id("$PACKER_VCC_NET")) {
-                    carry_lc->params[ctx->id("CIN_CONST")] = Property::State::S1;
-                    carry_lc->params[ctx->id("CIN_SET")] =
+                    carry_lc->params[id_CIN_CONST] = Property::State::S1;
+                    carry_lc->params[id_CIN_SET] =
                             cin_net == ctx->id("$PACKER_VCC_NET") ? Property::State::S1 : Property::State::S0;
-                    carry_lc->ports.at(ctx->id("CIN")).net = nullptr;
+                    carry_lc->ports.at(id_CIN).net = nullptr;
                     auto &cin_users = ctx->nets.at(cin_net)->users;
                     cin_users.erase(
                             std::remove_if(cin_users.begin(), cin_users.end(), [carry_lc, ctx](const PortRef &pr) {
-                                return pr.cell == carry_lc && pr.port == ctx->id("CIN");
+                                return pr.cell == carry_lc && pr.port == id_CIN;
                             }));
                 }
             }
@@ -281,18 +280,15 @@ static void pack_ram(Context *ctx)
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (is_ram(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_RAM"), ci->name.str(ctx) + "_RAM");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_RAM, ci->name.str(ctx) + "_RAM");
             packed_cells.insert(ci->name);
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             for (auto param : ci->params)
                 packed->params[param.first] = param.second;
-            packed->params[ctx->id("NEG_CLK_W")] =
-                    Property(ci->type == ctx->id("SB_RAM40_4KNW") || ci->type == ctx->id("SB_RAM40_4KNRNW"), 1);
-            packed->params[ctx->id("NEG_CLK_R")] =
-                    Property(ci->type == ctx->id("SB_RAM40_4KNR") || ci->type == ctx->id("SB_RAM40_4KNRNW"), 1);
-            packed->type = ctx->id("ICESTORM_RAM");
+            packed->params[id_NEG_CLK_W] = Property(ci->type == id_SB_RAM40_4KNW || ci->type == id_SB_RAM40_4KNRNW, 1);
+            packed->params[id_NEG_CLK_R] = Property(ci->type == id_SB_RAM40_4KNR || ci->type == id_SB_RAM40_4KNRNW, 1);
+            packed->type = id_ICESTORM_RAM;
             for (auto port : ci->ports) {
                 PortInfo &pi = port.second;
                 std::string newname = pi.name.str(ctx);
@@ -300,9 +296,9 @@ static void pack_ram(Context *ctx)
                 if (bpos != std::string::npos) {
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
-                if (pi.name == ctx->id("RCLKN"))
+                if (pi.name == id_RCLKN)
                     newname = "RCLK";
-                else if (pi.name == ctx->id("WCLKN"))
+                else if (pi.name == id_WCLKN)
                     newname = "WCLK";
                 replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
@@ -330,13 +326,13 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
             if ((is_lut(ctx, uc) || is_lc(ctx, uc) || is_carry(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') &&
                 !constval) {
                 uc->ports[user.port].net = nullptr;
-            } else if ((is_sb_mac16(ctx, uc) || uc->type == ctx->id("ICESTORM_DSP")) &&
-                       (user.port != ctx->id("CLK") &&
-                        ((constval && user.port == ctx->id("CE")) || (!constval && user.port != ctx->id("CE"))))) {
+            } else if ((is_sb_mac16(ctx, uc) || uc->type == id_ICESTORM_DSP) &&
+                       (user.port != id_CLK &&
+                        ((constval && user.port == id_CE) || (!constval && user.port != id_CE)))) {
                 uc->ports[user.port].net = nullptr;
-            } else if (is_ram(ctx, uc) && !constval && user.port != ctx->id("RCLK") && user.port != ctx->id("RCLKN") &&
-                       user.port != ctx->id("WCLK") && user.port != ctx->id("WCLKN") && user.port != ctx->id("RCLKE") &&
-                       user.port != ctx->id("WCLKE")) {
+            } else if (is_ram(ctx, uc) && !constval && user.port != id_RCLK && user.port != id_RCLKN &&
+                       user.port != id_WCLK && user.port != id_WCLKN && user.port != id_RCLKE &&
+                       user.port != id_WCLKE) {
                 uc->ports[user.port].net = nullptr;
             } else {
                 uc->ports[user.port].net = constnet;
@@ -352,24 +348,24 @@ static void pack_constants(Context *ctx)
 {
     log_info("Packing constants..\n");
 
-    std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
-    gnd_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
+    std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, id_ICESTORM_LC, "$PACKER_GND");
+    gnd_cell->params[id_LUT_INIT] = Property(0, 16);
     auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
-    gnd_net->driver.port = ctx->id("O");
-    gnd_cell->ports.at(ctx->id("O")).net = gnd_net.get();
+    gnd_net->driver.port = id_O;
+    gnd_cell->ports.at(id_O).net = gnd_net.get();
 
     NetInfo *gnd_net_info = gnd_net.get();
     if (ctx->nets.find(ctx->id("$PACKER_GND_NET")) != ctx->nets.end()) {
         gnd_net_info = ctx->nets.find(ctx->id("$PACKER_GND_NET"))->second.get();
     }
 
-    std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
-    vcc_cell->params[ctx->id("LUT_INIT")] = Property(1, 16);
+    std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, id_ICESTORM_LC, "$PACKER_VCC");
+    vcc_cell->params[id_LUT_INIT] = Property(1, 16);
     auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
-    vcc_net->driver.port = ctx->id("O");
-    vcc_cell->ports.at(ctx->id("O")).net = vcc_net.get();
+    vcc_net->driver.port = id_O;
+    vcc_cell->ports.at(id_O).net = vcc_net.get();
 
     NetInfo *vcc_net_info = vcc_net.get();
     if (ctx->nets.find(ctx->id("$PACKER_VCC_NET")) != ctx->nets.end()) {
@@ -382,13 +378,13 @@ static void pack_constants(Context *ctx)
 
     for (auto &net : ctx->nets) {
         NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, gnd_net_info, false);
             gnd_used = true;
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
-        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, vcc_net_info, true);
             dead_nets.push_back(net.first);
@@ -434,16 +430,16 @@ static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell,
                                                    std::string gbuf_name)
 {
     // Find the matching SB_GB BEL connected to the same global network
-    if (!cell->attrs.count(ctx->id("BEL")))
+    if (!cell->attrs.count(id_BEL))
         log_error("Unconstrained SB_GB_IO %s is not supported.\n", ctx->nameOf(cell));
-    BelId bel = ctx->getBelByNameStr(cell->attrs[ctx->id("BEL")].as_string());
+    BelId bel = ctx->getBelByNameStr(cell->attrs[id_BEL].as_string());
     BelId gb_bel = find_padin_gbuf(ctx, bel, port_name);
     NPNR_ASSERT(gb_bel != BelId());
 
     // Create a SB_GB Cell and lock it there
-    std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), gbuf_name);
-    gb->attrs[ctx->id("FOR_PAD_IN")] = Property::State::S1;
-    gb->attrs[ctx->id("BEL")] = ctx->getBelName(gb_bel).str(ctx);
+    std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, id_SB_GB, gbuf_name);
+    gb->attrs[id_FOR_PAD_IN] = Property::State::S1;
+    gb->attrs[id_BEL] = ctx->getBelName(gb_bel).str(ctx);
 
     // Reconnect the net to that port for easier identification it's a global net
     replace_port(cell, port_name, gb.get(), id_GLOBAL_BUFFER_OUTPUT);
@@ -475,11 +471,11 @@ static void pack_io(Context *ctx)
         if (is_nextpnr_iob(ctx, ci)) {
             CellInfo *sb = nullptr, *rgb = nullptr;
             if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
-                sb = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_ice_iob, ctx->id("PACKAGE_PIN"), true, ci);
+                sb = net_only_drives(ctx, ci->ports.at(id_O).net, is_ice_iob, id_PACKAGE_PIN, true, ci);
 
             } else if (ci->type == ctx->id("$nextpnr_obuf")) {
-                NetInfo *net = ci->ports.at(ctx->id("I")).net;
-                sb = net_only_drives(ctx, net, is_ice_iob, ctx->id("PACKAGE_PIN"), true, ci);
+                NetInfo *net = ci->ports.at(id_I).net;
+                sb = net_only_drives(ctx, net, is_ice_iob, id_PACKAGE_PIN, true, ci);
                 if (net && net->driver.cell &&
                     (is_sb_rgba_drv(ctx, net->driver.cell) || is_sb_rgb_drv(ctx, net->driver.cell)))
                     rgb = net->driver.cell;
@@ -488,7 +484,7 @@ static void pack_io(Context *ctx)
                 // Trivial case, SB_IO used. Just destroy the iobuf
                 log_info("%s feeds SB_IO %s, removing %s %s.\n", ci->name.c_str(ctx), sb->name.c_str(ctx),
                          ci->type.c_str(ctx), ci->name.c_str(ctx));
-                NetInfo *net = sb->ports.at(ctx->id("PACKAGE_PIN")).net;
+                NetInfo *net = sb->ports.at(id_PACKAGE_PIN).net;
                 if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
                      net->users.size() > 1) ||
                     (ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
@@ -518,13 +514,12 @@ static void pack_io(Context *ctx)
             } else if (rgb != nullptr) {
                 log_info("%s use by SB_RGBA_DRV/SB_RGB_DRV %s, not creating SB_IO\n", ci->name.c_str(ctx),
                          rgb->name.c_str(ctx));
-                disconnect_port(ctx, ci, ctx->id("I"));
+                disconnect_port(ctx, ci, id_I);
                 packed_cells.insert(ci->name);
                 continue;
             } else {
                 // Create a SB_IO buffer
-                std::unique_ptr<CellInfo> ice_cell =
-                        create_ice_cell(ctx, ctx->id("SB_IO"), ci->name.str(ctx) + "$sb_io");
+                std::unique_ptr<CellInfo> ice_cell = create_ice_cell(ctx, id_SB_IO, ci->name.str(ctx) + "$sb_io");
                 nxio_to_sb(ctx, ci, ice_cell.get(), packed_cells);
                 new_cells.push_back(std::move(ice_cell));
                 sb = new_cells.back().get();
@@ -535,7 +530,7 @@ static void pack_io(Context *ctx)
             for (auto &attr : ci->attrs)
                 sb->attrs[attr.first] = attr.second;
         } else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) {
-            NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net;
+            NetInfo *net = ci->ports.at(id_PACKAGE_PIN).net;
             if ((net != nullptr) && ((net->users.size() > 2) ||
                                      (net->driver.cell != nullptr &&
                                       net->driver.cell->type == ctx->id("$nextpnr_obuf") && net->users.size() > 1)))
@@ -552,8 +547,8 @@ static void pack_io(Context *ctx)
             new_cells.push_back(std::move(gb));
 
             // Make it a normal SB_IO with global marker
-            ci->type = ctx->id("SB_IO");
-            ci->attrs[ctx->id("GLOBAL")] = Property::State::S1;
+            ci->type = id_SB_IO;
+            ci->attrs[id_GLOBAL] = Property::State::S1;
         } else if (is_sb_io(ctx, ci)) {
             // Disconnect unused inputs
             NetInfo *net_in0 = ci->ports.count(id_D_IN_0) ? ci->ports[id_D_IN_0].net : nullptr;
@@ -595,18 +590,18 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
              is_cen ? " [cen]" : "", is_logic ? " [logic]" : "", fanout);
 
     std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
-    std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name);
-    gb->ports[ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER")].net = net;
+    std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, id_SB_GB, "$gbuf_" + glb_name);
+    gb->ports[id_USER_SIGNAL_TO_GLOBAL_BUFFER].net = net;
     PortRef pr;
     pr.cell = gb.get();
-    pr.port = ctx->id("USER_SIGNAL_TO_GLOBAL_BUFFER");
+    pr.port = id_USER_SIGNAL_TO_GLOBAL_BUFFER;
     net->users.push_back(pr);
 
     pr.cell = gb.get();
-    pr.port = ctx->id("GLOBAL_BUFFER_OUTPUT");
+    pr.port = id_GLOBAL_BUFFER_OUTPUT;
     NetInfo *glbnet = ctx->createNet(ctx->id(glb_name));
     glbnet->driver = pr;
-    gb->ports[ctx->id("GLOBAL_BUFFER_OUTPUT")].net = glbnet;
+    gb->ports[id_GLOBAL_BUFFER_OUTPUT].net = glbnet;
     std::vector<PortRef> keep_users;
     for (auto user : net->users) {
         if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) ||
@@ -664,9 +659,9 @@ static void promote_globals(Context *ctx)
             --gbs_available;
 
             /* And possibly limits what we can promote */
-            if (cell.second->attrs.find(ctx->id("BEL")) != cell.second->attrs.end()) {
+            if (cell.second->attrs.find(id_BEL) != cell.second->attrs.end()) {
                 /* If the SB_GB is locked, doesn't matter what it drives */
-                BelId bel = ctx->getBelByNameStr(cell.second->attrs[ctx->id("BEL")].as_string());
+                BelId bel = ctx->getBelByNameStr(cell.second->attrs[id_BEL].as_string());
                 int glb_id = ctx->get_driven_glb_netwk(bel);
                 if ((glb_id % 2) == 0)
                     resets_available--;
@@ -708,7 +703,7 @@ static void promote_globals(Context *ctx)
         if (global_clock->second == 0 && prom_logics < 4 && global_logic->second > logic_fanout_thresh &&
             (global_logic->second > global_cen->second || prom_cens >= cens_available) &&
             (global_logic->second > global_reset->second || prom_resets >= resets_available) &&
-            bool_or_default(ctx->settings, ctx->id("promote_logic"), false)) {
+            bool_or_default(ctx->settings, id_promote_logic, false)) {
             NetInfo *logicnet = ctx->nets[global_logic->first].get();
             insert_global(ctx, logicnet, false, false, true, global_logic->second);
             ++prom_globals;
@@ -784,11 +779,11 @@ static void place_plls(Context *ctx)
             continue;
 
         // If it's constrained already, add to already used list
-        if (ci->attrs.count(ctx->id("BEL"))) {
-            BelId bel_constrain = ctx->getBelByNameStr(ci->attrs[ctx->id("BEL")].as_string());
+        if (ci->attrs.count(id_BEL)) {
+            BelId bel_constrain = ctx->getBelByNameStr(ci->attrs[id_BEL].as_string());
             if (pll_all_bels.count(bel_constrain) == 0)
                 log_error("PLL '%s' is constrained to invalid BEL '%s'\n", ci->name.c_str(ctx),
-                          ci->attrs[ctx->id("BEL")].as_string().c_str());
+                          ci->attrs[id_BEL].as_string().c_str());
             pll_used_bels[bel_constrain] = ci;
         }
 
@@ -802,10 +797,10 @@ static void place_plls(Context *ctx)
             continue;
 
         // Check PACKAGEPIN connection
-        if (!ci->ports.count(ctx->id("PACKAGEPIN")))
+        if (!ci->ports.count(id_PACKAGEPIN))
             log_error("PLL '%s' is of PAD type but doesn't have a PACKAGEPIN port\n", ci->name.c_str(ctx));
 
-        NetInfo *ni = ci->ports.at(ctx->id("PACKAGEPIN")).net;
+        NetInfo *ni = ci->ports.at(id_PACKAGEPIN).net;
         if (ni == nullptr || ni->driver.cell == nullptr)
             log_error("PLL '%s' is of PAD type but doesn't have a valid PACKAGEPIN connection\n", ci->name.c_str(ctx));
 
@@ -816,11 +811,11 @@ static void place_plls(Context *ctx)
                       ci->name.c_str(ctx), io_cell->type.c_str(ctx));
         if (ni->users.size() != 1)
             log_error("PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx), ni->name.c_str(ctx));
-        if (!io_cell->attrs.count(ctx->id("BEL")))
+        if (!io_cell->attrs.count(id_BEL))
             log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
                       io_cell->name.c_str(ctx));
 
-        BelId io_bel = ctx->getBelByNameStr(io_cell->attrs.at(ctx->id("BEL")).as_string());
+        BelId io_bel = ctx->getBelByNameStr(io_cell->attrs.at(id_BEL).as_string());
         BelId found_bel;
 
         // Find the PLL BEL that would suit that connection
@@ -843,16 +838,16 @@ static void place_plls(Context *ctx)
         }
 
         // Is it user constrained ?
-        if (ci->attrs.count(ctx->id("BEL"))) {
+        if (ci->attrs.count(id_BEL)) {
             // Yes. Check it actually matches !
-            BelId bel_constrain = ctx->getBelByNameStr(ci->attrs[ctx->id("BEL")].as_string());
+            BelId bel_constrain = ctx->getBelByNameStr(ci->attrs[id_BEL].as_string());
             if (bel_constrain != found_bel)
                 log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
                           "connection\n",
                           ci->name.c_str(ctx), ctx->nameOfBel(bel_constrain), ctx->nameOfBel(found_bel));
         } else {
             // No, we can constrain it ourselves
-            ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
+            ci->attrs[id_BEL] = ctx->getBelName(found_bel).str(ctx);
             pll_used_bels[found_bel] = ci;
         }
 
@@ -867,15 +862,15 @@ static void place_plls(Context *ctx)
             continue;
 
         // Only consider bound IO that are used as inputs
-        if (!io_ci->attrs.count(ctx->id("BEL")))
+        if (!io_ci->attrs.count(id_BEL))
             continue;
         if ((!io_ci->ports.count(id_D_IN_0) || (io_ci->ports[id_D_IN_0].net == nullptr)) &&
             (!io_ci->ports.count(id_D_IN_1) || (io_ci->ports[id_D_IN_1].net == nullptr)) &&
-            !bool_or_default(io_ci->attrs, ctx->id("GLOBAL")))
+            !bool_or_default(io_ci->attrs, id_GLOBAL))
             continue;
 
         // Check all placed PLL (either forced by user, or forced by PACKAGEPIN)
-        BelId io_bel = ctx->getBelByNameStr(io_ci->attrs[ctx->id("BEL")].as_string());
+        BelId io_bel = ctx->getBelByNameStr(io_ci->attrs[id_BEL].as_string());
 
         for (auto placed_pll : pll_used_bels) {
             BelPin pll_io_a, pll_io_b;
@@ -905,11 +900,11 @@ static void place_plls(Context *ctx)
             continue;
 
         // Only consider the bound ones
-        if (!gb_ci->attrs.count(ctx->id("BEL")))
+        if (!gb_ci->attrs.count(id_BEL))
             continue;
 
         // Check all placed PLL (either forced by user, or forced by PACKAGEPIN)
-        BelId gb_bel = ctx->getBelByNameStr(gb_ci->attrs[ctx->id("BEL")].as_string());
+        BelId gb_bel = ctx->getBelByNameStr(gb_ci->attrs[id_BEL].as_string());
 
         for (auto placed_pll : pll_used_bels) {
             CellInfo *ci = placed_pll.second;
@@ -967,8 +962,8 @@ static void place_plls(Context *ctx)
             // Could this be a PAD PLL ?
             bool could_be_pad = false;
             BelId pad_bel;
-            if (ni->users.size() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(ctx->id("BEL")))
-                pad_bel = ctx->getBelByNameStr(ni->driver.cell->attrs[ctx->id("BEL")].as_string());
+            if (ni->users.size() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(id_BEL))
+                pad_bel = ctx->getBelByNameStr(ni->driver.cell->attrs[id_BEL].as_string());
 
             // Find a BEL for it
             BelId found_bel;
@@ -1002,7 +997,7 @@ static void place_plls(Context *ctx)
             if (could_be_pad)
                 log_info("  (given its connections, this PLL could have been a PAD PLL)\n");
 
-            ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
+            ci->attrs[id_BEL] = ctx->getBelName(found_bel).str(ctx);
             pll_used_bels[found_bel] = ci;
         }
     }
@@ -1017,20 +1012,20 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     NPNR_ASSERT(port.net != nullptr);
 
     // Create pass-through LUT.
-    std::unique_ptr<CellInfo> pt = create_ice_cell(ctx, ctx->id("ICESTORM_LC"),
-                                                   ci->name.str(ctx) + "$nextpnr_" + portId.str(ctx) + "_lut_through");
-    pt->params[ctx->id("LUT_INIT")] = Property(65280, 16); // output is always I3
+    std::unique_ptr<CellInfo> pt =
+            create_ice_cell(ctx, id_ICESTORM_LC, ci->name.str(ctx) + "$nextpnr_" + portId.str(ctx) + "_lut_through");
+    pt->params[id_LUT_INIT] = Property(65280, 16); // output is always I3
 
     // Create LUT output net.
     NetInfo *out_net = ctx->createNet(ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net"));
     out_net->driver.cell = pt.get();
-    out_net->driver.port = ctx->id("O");
-    pt->ports.at(ctx->id("O")).net = out_net;
+    out_net->driver.port = id_O;
+    pt->ports.at(id_O).net = out_net;
 
     // New users of the original cell's port
     std::vector<PortRef> new_users;
     for (const auto &user : port.net->users) {
-        if (onlyNonLUTs && user.cell->type == ctx->id("ICESTORM_LC")) {
+        if (onlyNonLUTs && user.cell->type == id_ICESTORM_LC) {
             new_users.push_back(user);
             continue;
         }
@@ -1046,9 +1041,9 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     // Add LUT to new users.
     PortRef pr;
     pr.cell = pt.get();
-    pr.port = ctx->id("I3");
+    pr.port = id_I3;
     new_users.push_back(pr);
-    pt->ports.at(ctx->id("I3")).net = port.net;
+    pt->ports.at(id_I3).net = port.net;
 
     // Replace users of the original net.
     port.net->users = new_users;
@@ -1065,7 +1060,7 @@ static BelId cell_place_unique(Context *ctx, CellInfo *ci)
         if (ctx->is_bel_locked(bel))
             continue;
         IdStringList bel_name = ctx->getBelName(bel);
-        ci->attrs[ctx->id("BEL")] = bel_name.str(ctx);
+        ci->attrs[id_BEL] = bel_name.str(ctx);
         log_info("  constrained %s '%s' to %s\n", ci->type.c_str(ctx), ci->name.c_str(ctx), ctx->nameOfBel(bel));
         return bel;
     }
@@ -1124,7 +1119,7 @@ static void pack_special(Context *ctx)
             /* Force placement (no choices anyway) */
             cell_place_unique(ctx, ci);
 
-            NetInfo *ledpu_net = ci->ports.at(ctx->id("LEDPU")).net;
+            NetInfo *ledpu_net = ci->ports.at(id_LEDPU).net;
             for (auto &user : ledpu_net->users) {
                 if (!is_sb_rgb_drv(ctx, user.cell)) {
                     log_error("SB_LED_DRV_CUR LEDPU port can only be connected to SB_RGB_DRV!\n");
@@ -1133,44 +1128,42 @@ static void pack_special(Context *ctx)
                     user.cell->ports.at(user.port).net = nullptr;
                 }
             }
-            ci->ports.erase(ctx->id("LEDPU"));
+            ci->ports.erase(id_LEDPU);
             ctx->nets.erase(ledpu_net->name);
         }
     }
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (is_sb_lfosc(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"), ci->name.str(ctx) + "_OSC");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_LFOSC, ci->name.str(ctx) + "_OSC");
             packed_cells.insert(ci->name);
             cell_place_unique(ctx, packed.get());
-            replace_port(ci, ctx->id("CLKLFEN"), packed.get(), ctx->id("CLKLFEN"));
-            replace_port(ci, ctx->id("CLKLFPU"), packed.get(), ctx->id("CLKLFPU"));
-            if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) {
-                replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF_FABRIC"));
-                set_period(ctx, packed.get(), ctx->id("CLKLF_FABRIC"), 100000000); // 10kHz
+            replace_port(ci, id_CLKLFEN, packed.get(), id_CLKLFEN);
+            replace_port(ci, id_CLKLFPU, packed.get(), id_CLKLFPU);
+            if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
+                replace_port(ci, id_CLKLF, packed.get(), id_CLKLF_FABRIC);
+                set_period(ctx, packed.get(), id_CLKLF_FABRIC, 100000000); // 10kHz
             } else {
-                replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF"));
+                replace_port(ci, id_CLKLF, packed.get(), id_CLKLF);
                 std::unique_ptr<CellInfo> gb =
-                        create_padin_gbuf(ctx, packed.get(), ctx->id("CLKLF"), "$gbuf_" + ci->name.str(ctx) + "_lfosc");
+                        create_padin_gbuf(ctx, packed.get(), id_CLKLF, "$gbuf_" + ci->name.str(ctx) + "_lfosc");
                 set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 100000000); // 10kHz
                 new_cells.push_back(std::move(gb));
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_hfosc(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_HFOSC"), ci->name.str(ctx) + "_OSC");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_HFOSC, ci->name.str(ctx) + "_OSC");
             packed_cells.insert(ci->name);
             cell_place_unique(ctx, packed.get());
-            packed->params[ctx->id("TRIM_EN")] = str_or_default(ci->params, ctx->id("TRIM_EN"), "0b0");
-            packed->params[ctx->id("CLKHF_DIV")] = str_or_default(ci->params, ctx->id("CLKHF_DIV"), "0b00");
-            replace_port(ci, ctx->id("CLKHFEN"), packed.get(), ctx->id("CLKHFEN"));
-            replace_port(ci, ctx->id("CLKHFPU"), packed.get(), ctx->id("CLKHFPU"));
+            packed->params[id_TRIM_EN] = str_or_default(ci->params, id_TRIM_EN, "0b0");
+            packed->params[id_CLKHF_DIV] = str_or_default(ci->params, id_CLKHF_DIV, "0b00");
+            replace_port(ci, id_CLKHFEN, packed.get(), id_CLKHFEN);
+            replace_port(ci, id_CLKHFPU, packed.get(), id_CLKHFPU);
             for (int i = 0; i < 10; i++) {
                 auto port = ctx->id("TRIM" + std::to_string(i));
                 replace_port(ci, port, packed.get(), port);
             }
-            std::string div = packed->params[ctx->id("CLKHF_DIV")].as_string();
+            std::string div = packed->params[id_CLKHF_DIV].as_string();
             int frequency;
             if (div == "0b00")
                 frequency = 48;
@@ -1182,20 +1175,19 @@ static void pack_special(Context *ctx)
                 frequency = 6;
             else
                 log_error("Invalid HFOSC divider value '%s' - expecting 0b00, 0b01, 0b10 or 0b11\n", div.c_str());
-            if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) {
-                replace_port(ci, ctx->id("CLKHF"), packed.get(), ctx->id("CLKHF_FABRIC"));
-                set_period(ctx, packed.get(), ctx->id("CLKHF_FABRIC"), 1000000 / frequency);
+            if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
+                replace_port(ci, id_CLKHF, packed.get(), id_CLKHF_FABRIC);
+                set_period(ctx, packed.get(), id_CLKHF_FABRIC, 1000000 / frequency);
             } else {
-                replace_port(ci, ctx->id("CLKHF"), packed.get(), ctx->id("CLKHF"));
+                replace_port(ci, id_CLKHF, packed.get(), id_CLKHF);
                 std::unique_ptr<CellInfo> gb =
-                        create_padin_gbuf(ctx, packed.get(), ctx->id("CLKHF"), "$gbuf_" + ci->name.str(ctx) + "_hfosc");
+                        create_padin_gbuf(ctx, packed.get(), id_CLKHF, "$gbuf_" + ci->name.str(ctx) + "_hfosc");
                 set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 1000000 / frequency);
                 new_cells.push_back(std::move(gb));
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_spram(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_SPRAM"), ci->name.str(ctx) + "_RAM");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_SPRAM, ci->name.str(ctx) + "_RAM");
             packed_cells.insert(ci->name);
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
@@ -1210,8 +1202,7 @@ static void pack_special(Context *ctx)
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_mac16(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_DSP"), ci->name.str(ctx) + "_DSP");
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_DSP, ci->name.str(ctx) + "_DSP");
             packed_cells.insert(ci->name);
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
@@ -1241,7 +1232,7 @@ static void pack_special(Context *ctx)
                 if (net == nullptr)
                     continue;
 
-                if ((pi.name != ctx->id("RGB0")) && (pi.name != ctx->id("RGB1")) && (pi.name != ctx->id("RGB2")))
+                if ((pi.name != id_RGB0) && (pi.name != id_RGB1) && (pi.name != id_RGB2))
                     continue;
 
                 if (net->users.size() > 0)
@@ -1253,10 +1244,10 @@ static void pack_special(Context *ctx)
             if (is_sb_rgb_drv(ctx, ci) && !ci->ledInfo.ledCurConnected)
                 log_error("Port RGBPU of SB_RGB_DRV should be driven by port LEDPU of SB_LED_DRV_CUR!\n");
 
-            ci->ports.erase(ctx->id("RGBPU"));
-            ci->ports.erase(ctx->id("RGB0"));
-            ci->ports.erase(ctx->id("RGB1"));
-            ci->ports.erase(ctx->id("RGB2"));
+            ci->ports.erase(id_RGBPU);
+            ci->ports.erase(id_RGB0);
+            ci->ports.erase(id_RGB1);
+            ci->ports.erase(id_RGB2);
         } else if (is_sb_ledda_ip(ctx, ci)) {
             /* Force placement (no choices anyway) */
             cell_place_unique(ctx, ci);
@@ -1268,7 +1259,7 @@ static void pack_special(Context *ctx)
                     {std::make_tuple(id_SB_I2C, "0b0011"), Loc(25, 31, 0)},
             };
             std::string bus_addr74 =
-                    str_or_default(ci->params, ctx->id("BUS_ADDR74"), is_sb_i2c(ctx, ci) ? "0b0001" : "0b0000");
+                    str_or_default(ci->params, id_BUS_ADDR74, is_sb_i2c(ctx, ci) ? "0b0001" : "0b0000");
             if (map_ba74.find(std::make_tuple(ci->type, bus_addr74)) == map_ba74.end())
                 log_error("Invalid value for BUS_ADDR74 for cell '%s' of type '%s'\n", ci->name.c_str(ctx),
                           ci->type.c_str(ctx));
@@ -1278,7 +1269,7 @@ static void pack_special(Context *ctx)
                 log_error("Unable to find placement for cell '%s' of type '%s'\n", ci->name.c_str(ctx),
                           ci->type.c_str(ctx));
             IdStringList bel_name = ctx->getBelName(bel);
-            ci->attrs[ctx->id("BEL")] = bel_name.str(ctx);
+            ci->attrs[id_BEL] = bel_name.str(ctx);
             log_info("  constrained %s '%s' to %s\n", ci->type.c_str(ctx), ci->name.c_str(ctx), ctx->nameOfBel(bel));
         }
     }
@@ -1303,15 +1294,14 @@ void pack_plls(Context *ctx)
             bool is_pad = is_sb_pll40_pad(ctx, ci);
             bool is_core = !is_pad;
 
-            std::unique_ptr<CellInfo> packed =
-                    create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL");
-            packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx);
+            std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_PLL, ci->name.str(ctx) + "_PLL");
+            packed->attrs[id_TYPE] = ci->type.str(ctx);
             packed_cells.insert(ci->name);
             if (!is_sb_pll40_dual(ctx, ci)) {
                 // Remove second output, so a buffer isn't created for it, for these
                 // cell types with only one output
-                packed->ports.erase(ctx->id("PLLOUT_B"));
-                packed->ports.erase(ctx->id("PLLOUT_B_GLOBAL"));
+                packed->ports.erase(id_PLLOUT_B);
+                packed->ports.erase(id_PLLOUT_B_GLOBAL);
             }
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
@@ -1319,9 +1309,9 @@ void pack_plls(Context *ctx)
                 packed->params[param.first] = param.second;
 
             const std::map<IdString, IdString> pos_map_name = {
-                    {ctx->id("PLLOUT_SELECT"), ctx->id("PLLOUT_SELECT_A")},
-                    {ctx->id("PLLOUT_SELECT_PORTA"), ctx->id("PLLOUT_SELECT_A")},
-                    {ctx->id("PLLOUT_SELECT_PORTB"), ctx->id("PLLOUT_SELECT_B")},
+                    {id_PLLOUT_SELECT, id_PLLOUT_SELECT_A},
+                    {id_PLLOUT_SELECT_PORTA, id_PLLOUT_SELECT_A},
+                    {id_PLLOUT_SELECT_PORTB, id_PLLOUT_SELECT_B},
             };
             const std::map<std::string, int> pos_map_val = {
                     {"GENCLK", 0},
@@ -1336,9 +1326,8 @@ void pack_plls(Context *ctx)
                     packed->params[pos_map_name.at(param.first)] = pos_map_val.at(param.second.as_string());
                 }
             const std::map<IdString, std::pair<IdString, IdString>> delmodes = {
-                    {ctx->id("DELAY_ADJUSTMENT_MODE_FEEDBACK"), {ctx->id("DELAY_ADJMODE_FB"), ctx->id("FDA_FEEDBACK")}},
-                    {ctx->id("DELAY_ADJUSTMENT_MODE_RELATIVE"),
-                     {ctx->id("DELAY_ADJMODE_REL"), ctx->id("FDA_RELATIVE")}},
+                    {id_DELAY_ADJUSTMENT_MODE_FEEDBACK, {id_DELAY_ADJMODE_FB, id_FDA_FEEDBACK}},
+                    {id_DELAY_ADJUSTMENT_MODE_RELATIVE, {id_DELAY_ADJMODE_REL, id_FDA_RELATIVE}},
             };
             for (auto delmode : delmodes) {
                 if (ci->params.count(delmode.first)) {
@@ -1352,9 +1341,9 @@ void pack_plls(Context *ctx)
                         log_error("Invalid PLL %s selection '%s'\n", delmode.first.c_str(ctx), value.c_str());
                 }
             }
-            auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")].is_string
-                                         ? packed->params[ctx->id("FEEDBACK_PATH")].as_string()
-                                         : std::to_string(packed->params[ctx->id("FEEDBACK_PATH")].as_int64());
+            auto feedback_path = packed->params[id_FEEDBACK_PATH].is_string
+                                         ? packed->params[id_FEEDBACK_PATH].as_string()
+                                         : std::to_string(packed->params[id_FEEDBACK_PATH].as_int64());
             std::string fbp_value = feedback_path == "DELAY"             ? "0"
                                     : feedback_path == "SIMPLE"          ? "1"
                                     : feedback_path == "PHASE_AND_DELAY" ? "2"
@@ -1363,8 +1352,8 @@ void pack_plls(Context *ctx)
             if (!std::all_of(fbp_value.begin(), fbp_value.end(), isdigit))
                 log_error("PLL '%s' has unsupported FEEDBACK_PATH value '%s'\n", ci->name.c_str(ctx),
                           feedback_path.c_str());
-            packed->params[ctx->id("FEEDBACK_PATH")] = Property(std::stoi(fbp_value), 3);
-            packed->params[ctx->id("PLLTYPE")] = sb_pll40_type(ctx, ci);
+            packed->params[id_FEEDBACK_PATH] = Property(std::stoi(fbp_value), 3);
+            packed->params[id_PLLTYPE] = sb_pll40_type(ctx, ci);
 
             NetInfo *pad_packagepin_net = nullptr;
 
@@ -1379,16 +1368,16 @@ void pack_plls(Context *ctx)
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
 
-                if (pi.name == ctx->id("PLLOUTCOREA") || pi.name == ctx->id("PLLOUTCORE"))
+                if (pi.name == id_PLLOUTCOREA || pi.name == id_PLLOUTCORE)
                     newname = "PLLOUT_A";
-                if (pi.name == ctx->id("PLLOUTCOREB"))
+                if (pi.name == id_PLLOUTCOREB)
                     newname = "PLLOUT_B";
-                if (pi.name == ctx->id("PLLOUTGLOBALA") || pi.name == ctx->id("PLLOUTGLOBAL"))
+                if (pi.name == id_PLLOUTGLOBALA || pi.name == id_PLLOUTGLOBAL)
                     newname = "PLLOUT_A_GLOBAL";
-                if (pi.name == ctx->id("PLLOUTGLOBALB"))
+                if (pi.name == id_PLLOUTGLOBALB)
                     newname = "PLLOUT_B_GLOBAL";
 
-                if (pi.name == ctx->id("PACKAGEPIN")) {
+                if (pi.name == id_PACKAGEPIN) {
                     if (!is_pad) {
                         log_error("PLL '%s' has a PACKAGEPIN but is not a PAD PLL\n", ci->name.c_str(ctx));
                     } else {
@@ -1399,7 +1388,7 @@ void pack_plls(Context *ctx)
                         continue;
                     }
                 }
-                if (pi.name == ctx->id("REFERENCECLK")) {
+                if (pi.name == id_REFERENCECLK) {
                     if (!is_core)
                         log_error("PLL '%s' has a REFERENCECLK but is not a CORE PLL\n", ci->name.c_str(ctx));
                     got_input_constr = get_period(ctx, ci, pi.name, input_constr);
@@ -1429,7 +1418,7 @@ void pack_plls(Context *ctx)
                 log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ctx->nameOf(ci),
                          MHz(ctx, input_constr));
                 // Input divider (DIVR)
-                input_constr *= (int_or_default(packed->params, ctx->id("DIVR"), 0) + 1);
+                input_constr *= (int_or_default(packed->params, id_DIVR, 0) + 1);
                 delay_t vco_constr = 0;
                 delay_t outa_constr = 0, outb_constr = 0;
                 int sr_div = 4;
@@ -1452,7 +1441,7 @@ void pack_plls(Context *ctx)
                 };
 
                 // Lookup shiftreg divider
-                int sr_div_mode = int_or_default(packed->params, ctx->id("SHIFTREG_DIV_MODE"), 0);
+                int sr_div_mode = int_or_default(packed->params, id_SHIFTREG_DIV_MODE, 0);
                 switch (sr_div_mode) {
                 case 0:
                     sr_div = 4;
@@ -1470,8 +1459,8 @@ void pack_plls(Context *ctx)
                 }
                 }
                 // Determine dividers in VCO path
-                vco_constr = input_constr / (int_or_default(packed->params, ctx->id("DIVF"), 0) + 1);
-                divq = 1 << (int_or_default(packed->params, ctx->id("DIVQ"), 0));
+                vco_constr = input_constr / (int_or_default(packed->params, id_DIVF, 0) + 1);
+                divq = 1 << (int_or_default(packed->params, id_DIVQ, 0));
                 if (fbp_value != "1") // anything other than SIMPLE - feedback after DIVQ
                     vco_constr /= divq;
                 if (fbp_value == "6") { // EXTERNAL
@@ -1484,19 +1473,19 @@ void pack_plls(Context *ctx)
                 }
                 log_info("    VCO frequency of PLL '%s' is constrained to %.1f MHz\n", ctx->nameOf(ci),
                          MHz(ctx, vco_constr));
-                if (ci->type == ctx->id("SB_PLL40_2_PAD"))
+                if (ci->type == id_SB_PLL40_2_PAD)
                     outa_constr = input_constr; // 2_PAD variant passes through input to OUTPUT A
                 else
-                    outa_constr = process_output(ctx->id("PLLOUT_SELECT_A"));
-                outb_constr = process_output(ctx->id("PLLOUT_SELECT_B"));
-                set_period(ctx, packed.get(), ctx->id("PLLOUT_A"), outa_constr);
-                set_period(ctx, packed.get(), ctx->id("PLLOUT_A_GLOBAL"), outa_constr);
-                set_period(ctx, packed.get(), ctx->id("PLLOUT_B"), outb_constr);
-                set_period(ctx, packed.get(), ctx->id("PLLOUT_B_GLOBAL"), outb_constr);
+                    outa_constr = process_output(id_PLLOUT_SELECT_A);
+                outb_constr = process_output(id_PLLOUT_SELECT_B);
+                set_period(ctx, packed.get(), id_PLLOUT_A, outa_constr);
+                set_period(ctx, packed.get(), id_PLLOUT_A_GLOBAL, outa_constr);
+                set_period(ctx, packed.get(), id_PLLOUT_B, outb_constr);
+                set_period(ctx, packed.get(), id_PLLOUT_B_GLOBAL, outb_constr);
             }
         constr_fail:
             // PLL must have been placed already in place_plls()
-            BelId pll_bel = ctx->getBelByNameStr(packed->attrs[ctx->id("BEL")].as_string());
+            BelId pll_bel = ctx->getBelByNameStr(packed->attrs[id_BEL].as_string());
             NPNR_ASSERT(pll_bel != BelId());
 
             // Deal with PAD PLL peculiarities
@@ -1505,10 +1494,10 @@ void pack_plls(Context *ctx)
                 auto pll_packagepin_driver = pad_packagepin_net->driver;
                 NPNR_ASSERT(pll_packagepin_driver.cell != nullptr);
                 auto packagepin_cell = pll_packagepin_driver.cell;
-                auto packagepin_bel_name = packagepin_cell->attrs.find(ctx->id("BEL"));
+                auto packagepin_bel_name = packagepin_cell->attrs.find(id_BEL);
 
                 // Set an attribute about this PLL's PAD SB_IO.
-                packed->attrs[ctx->id("BEL_PAD_INPUT")] = packagepin_bel_name->second;
+                packed->attrs[id_BEL_PAD_INPUT] = packagepin_bel_name->second;
 
                 // Disconnect PACKAGEPIN (it's a physical HW link)
                 for (auto user : pad_packagepin_net->users)
@@ -1522,7 +1511,7 @@ void pack_plls(Context *ctx)
             // In practice, this means the LOCK signal can only directly reach LUT
             // inputs.
             // If we have a net connected to LOCK, make sure it only drives LUTs.
-            auto port = packed->ports[ctx->id("LOCK")];
+            auto port = packed->ports[id_LOCK];
             if (port.net != nullptr) {
                 log_info("  PLL '%s' has LOCK output, need to pass all outputs via LUT\n", ci->name.c_str(ctx));
                 bool found_lut = false;
@@ -1531,8 +1520,8 @@ void pack_plls(Context *ctx)
                 unsigned int lut_count = 0;
                 for (const auto &user : port.net->users) {
                     NPNR_ASSERT(user.cell != nullptr);
-                    if (user.cell->type == ctx->id("ICESTORM_LC")) {
-                        if (bool_or_default(user.cell->params, ctx->id("CARRY_ENABLE"), false)) {
+                    if (user.cell->type == id_ICESTORM_LC) {
+                        if (bool_or_default(user.cell->params, id_CARRY_ENABLE, false)) {
                             found_carry = true;
                             all_luts = false;
                         } else {
@@ -1569,14 +1558,14 @@ void pack_plls(Context *ctx)
                 int z = 0;
                 for (const auto &user : port.net->users) {
                     NPNR_ASSERT(user.cell != nullptr);
-                    NPNR_ASSERT(user.cell->type == ctx->id("ICESTORM_LC"));
+                    NPNR_ASSERT(user.cell->type == id_ICESTORM_LC);
 
                     // TODO(q3k): handle when the Bel might be already the
                     // target of another constraint.
                     NPNR_ASSERT(z < 8);
                     auto target_bel = ctx->getBelByLocation(Loc(x, y, z++));
                     auto target_bel_name = ctx->getBelName(target_bel).str(ctx);
-                    user.cell->attrs[ctx->id("BEL")] = target_bel_name;
+                    user.cell->attrs[id_BEL] = target_bel_name;
                     log_info("  constrained '%s' to %s\n", user.cell->name.c_str(ctx), target_bel_name.c_str());
                 }
             }
@@ -1586,9 +1575,9 @@ void pack_plls(Context *ctx)
                 PortInfo &pi = port.second;
                 bool is_b_port;
 
-                if (pi.name == ctx->id("PLLOUT_A_GLOBAL"))
+                if (pi.name == id_PLLOUT_A_GLOBAL)
                     is_b_port = false;
-                else if (pi.name == ctx->id("PLLOUT_B_GLOBAL"))
+                else if (pi.name == id_PLLOUT_B_GLOBAL)
                     is_b_port = true;
                 else
                     continue;
@@ -1635,13 +1624,13 @@ bool Arch::pack()
         place_plls(ctx);
         pack_special(ctx);
         pack_plls(ctx);
-        if (!bool_or_default(ctx->settings, ctx->id("no_promote_globals"), false))
+        if (!bool_or_default(ctx->settings, id_no_promote_globals, false))
             promote_globals(ctx);
         ctx->assignArchInfo();
         constrain_chains(ctx);
         ctx->fixupHierarchy();
         ctx->assignArchInfo();
-        ctx->settings[ctx->id("pack")] = 1;
+        ctx->settings[id_pack] = 1;
         archInfoToAttributes();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;
diff --git a/ice40/pcf.cc b/ice40/pcf.cc
index 1003c037cf..d03820da5d 100644
--- a/ice40/pcf.cc
+++ b/ice40/pcf.cc
@@ -57,9 +57,9 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
                     if (setting == "-pullup") {
                         const auto &value = words.at(++args_end);
                         if (value == "yes" || value == "1")
-                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), Property::State::S1));
+                            extra_attrs.emplace_back(std::make_pair(id_PULLUP, Property::State::S1));
                         else if (value == "no" || value == "0")
-                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), Property::State::S0));
+                            extra_attrs.emplace_back(std::make_pair(id_PULLUP, Property::State::S0));
                         else
                             log_error("Invalid value '%s' for -pullup (on line %d)\n", value.c_str(), lineno);
                     } else if (setting == "-pullup_resistor") {
@@ -68,7 +68,7 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
                             log_error("Pullup resistance can only be set on UP5K/UP3K (on line %d)\n", lineno);
                         if (value != "3P3K" && value != "6P8K" && value != "10K" && value != "100K")
                             log_error("Invalid value '%s' for -pullup_resistor (on line %d)\n", value.c_str(), lineno);
-                        extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP_RESISTOR"), value));
+                        extra_attrs.emplace_back(std::make_pair(id_PULLUP_RESISTOR, value));
                     } else if (setting == "-nowarn") {
                         nowarn = true;
                     } else if (setting == "--warn-no-port") {
@@ -92,11 +92,11 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
                     BelId pin_bel = ctx->get_package_pin_bel(pin);
                     if (pin_bel == BelId())
                         log_error("package does not have a pin named '%s' (on line %d)\n", pin.c_str(), lineno);
-                    if (fnd_cell->second->attrs.count(ctx->id("BEL")))
+                    if (fnd_cell->second->attrs.count(id_BEL))
                         log_error("duplicate pin constraint on '%s' (on line %d)\n", cell.c_str(), lineno);
-                    fnd_cell->second->attrs[ctx->id("BEL")] = ctx->getBelName(pin_bel).str(ctx);
+                    fnd_cell->second->attrs[id_BEL] = ctx->getBelName(pin_bel).str(ctx);
                     log_info("constrained '%s' to bel '%s'\n", cell.c_str(),
-                             fnd_cell->second->attrs[ctx->id("BEL")].as_string().c_str());
+                             fnd_cell->second->attrs[id_BEL].as_string().c_str());
                     for (const auto &attr : extra_attrs)
                         fnd_cell->second->attrs[attr.first] = attr.second;
                 }
@@ -112,8 +112,8 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
             CellInfo *ci = cell.second.get();
             if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") ||
                 ci->type == ctx->id("$nextpnr_iobuf")) {
-                if (!ci->attrs.count(ctx->id("BEL"))) {
-                    if (bool_or_default(ctx->settings, ctx->id("pcf_allow_unconstrained")))
+                if (!ci->attrs.count(id_BEL)) {
+                    if (bool_or_default(ctx->settings, id_pcf_allow_unconstrained))
                         log_warning("IO '%s' is unconstrained in PCF and will be automatically placed\n",
                                     cell.first.c_str(ctx));
                     else
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6c0e48ced5..5fcdeaf759 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -171,17 +171,17 @@ std::string Arch::get_full_chip_name() const
 IdString Arch::archArgsToId(ArchArgs args) const
 {
     if (args.type == ArchArgs::LCMXO2_256HC) {
-        return id("lcmxo2_256hc");
+        return id_lcmxo2_256hc;
     } else if (args.type == ArchArgs::LCMXO2_640HC) {
-        return id("lcmxo2_640hc");
+        return id_lcmxo2_640hc;
     } else if (args.type == ArchArgs::LCMXO2_1200HC) {
-        return id("lcmxo2_1200hc");
+        return id_lcmxo2_1200hc;
     } else if (args.type == ArchArgs::LCMXO2_2000HC) {
-        return id("lcmxo2_2000hc");
+        return id_lcmxo2_2000hc;
     } else if (args.type == ArchArgs::LCMXO2_4000HC) {
-        return id("lcmxo2_4000hc");
+        return id_lcmxo2_4000hc;
     } else if (args.type == ArchArgs::LCMXO2_7000HC) {
-        return id("lcmxo2_7000hc");
+        return id_lcmxo2_7000hc;
     }
 
     return IdString();
@@ -414,17 +414,17 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     if (placer == "sa") {
         bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
         return retVal;
     } else if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
         cfg.ioBufTypes.insert(id_FACADE_IO);
         bool retVal = placer_heap(getCtx(), cfg);
-        getCtx()->settings[getCtx()->id("place")] = 1;
+        getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
         return retVal;
     } else {
@@ -434,7 +434,7 @@ bool Arch::place()
 
 bool Arch::route()
 {
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -444,7 +444,7 @@ bool Arch::route()
     } else {
         log_error("MachXO2 architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->settings[getCtx()->id("route")] = 1;
+    getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
     return result;
 }
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 29d8c3ffcc..347f4edec3 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -435,7 +435,7 @@ struct Arch : BaseArch<ArchRanges>
     // Extra helper
     std::string get_full_chip_name() const;
 
-    IdString archId() const override { return id("machxo2"); }
+    IdString archId() const override { return id_machxo2; }
     ArchArgs archArgs() const override { return args; }
     IdString archArgsToId(ArchArgs args) const override;
 
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index f624d91b61..9a711cbe45 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -235,36 +235,34 @@ void write_bitstream(Context *ctx, std::string text_config_file)
             int int_index = slice[5] - 'A';
             NPNR_ASSERT(int_index >= 0 && int_index < 4);
 
-            int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
-            int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
+            int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
+            int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
             cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
             cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
-            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".SRMODE",
-                                     str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-            cc.tiles[tname].add_enum(slice + ".CEMUX", intstr_or_default(ci->params, ctx->id("CEMUX"), "1"));
+                                     str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+            cc.tiles[tname].add_enum(slice + ".CEMUX", intstr_or_default(ci->params, id_CEMUX, "1"));
             cc.tiles[tname].add_enum("CLK" + std::to_string(int_index) + ".CLKMUX",
-                                     intstr_or_default(ci->params, ctx->id("CLKMUX"), "0"));
+                                     intstr_or_default(ci->params, id_CLKMUX, "0"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRMUX",
-                                     str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+                                     str_or_default(ci->params, id_LSRMUX, "LSR"));
             cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRONMUX",
-                                     intstr_or_default(ci->params, ctx->id("LSRONMUX"), "LSRMUX"));
-            cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, ctx->id("REGMODE"), "FF"));
-            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, ctx->id("REG1_SD"), "0"));
-            cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
-                                     str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
-        } else if (ci->type == ctx->id("FACADE_IO")) {
+                                     intstr_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+            cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
+            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
+        } else if (ci->type == id_FACADE_IO) {
             std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-            std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
-            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
+            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
             std::string pic_tile = get_pic_tile(ctx, bel);
             cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-        } else if (ci->type == ctx->id("OSCH")) {
-            std::string freq = str_or_default(ci->params, ctx->id("NOM_FREQ"), "2.08");
+        } else if (ci->type == id_OSCH) {
+            std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
             cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
             cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
         }
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index bbe3f2d636..1c4f753be9 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -103,12 +103,12 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_WADO3);
     } else if (type == id_FACADE_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
-        new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
+        new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
 
-        new_cell->addInout(ctx->id("PAD"));
-        new_cell->addInput(ctx->id("I"));
-        new_cell->addInput(ctx->id("EN"));
-        new_cell->addOutput(ctx->id("O"));
+        new_cell->addInout(id_PAD);
+        new_cell->addInput(id_I);
+        new_cell->addInput(id_EN);
+        new_cell->addOutput(id_O);
     } else if (type == id_LUT4) {
         new_cell->params[id_INIT] = Property(0, 16);
 
@@ -126,7 +126,7 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
 
 void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 {
-    lc->params[ctx->id("LUT0_INITVAL")] = lut->params[ctx->id("INIT")];
+    lc->params[id_LUT0_INITVAL] = lut->params[id_INIT];
 
     for (std::string i : {"A", "B", "C", "D"}) {
         IdString lut_port = ctx->id(i);
@@ -134,34 +134,34 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
         replace_port(lut, lut_port, lc, lc_port);
     }
 
-    replace_port(lut, ctx->id("Z"), lc, ctx->id("F0"));
+    replace_port(lut, id_Z, lc, id_F0);
 }
 
 void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
 {
     // FIXME: This will have to change once we support FFs with reset value of 1.
-    lc->params[ctx->id("REG0_REGSET")] = std::string("RESET");
+    lc->params[id_REG0_REGSET] = std::string("RESET");
 
-    replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
-    replace_port(dff, ctx->id("LSR"), lc, ctx->id("LSR"));
-    replace_port(dff, ctx->id("Q"), lc, ctx->id("Q0"));
+    replace_port(dff, id_CLK, lc, id_CLK);
+    replace_port(dff, id_LSR, lc, id_LSR);
+    replace_port(dff, id_Q, lc, id_Q0);
 
     if (lut_type == LutType::PassThru) {
         // If a register's DI port is fed by a constant, options for placing are
         // limited. Use the LUT to get around this.
         // LUT output will go to F0, which will feed back to DI0 input.
-        lc->params[ctx->id("LUT0_INITVAL")] = Property(0xAAAA, 16);
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("A0"));
-        connect_ports(ctx, lc, ctx->id("F0"), lc, ctx->id("DI0"));
+        lc->params[id_LUT0_INITVAL] = Property(0xAAAA, 16);
+        replace_port(dff, id_DI, lc, id_A0);
+        connect_ports(ctx, lc, id_F0, lc, id_DI0);
     } else if (lut_type == LutType::None) {
         // If there is no LUT, use the M0 input because DI0 requires
         // going through the LUTs.
-        lc->params[ctx->id("REG0_SD")] = std::string("0");
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("M0"));
+        lc->params[id_REG0_SD] = std::string("0");
+        replace_port(dff, id_DI, lc, id_M0);
     } else {
         // Otherwise, there's a LUT being used in the slice and mapping DI to
         // DI0 input is fine.
-        replace_port(dff, ctx->id("DI"), lc, ctx->id("DI0"));
+        replace_port(dff, id_DI, lc, id_DI0);
     }
 }
 
diff --git a/machxo2/cells.h b/machxo2/cells.h
index 409b68b118..7a9bab9267 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -40,12 +40,12 @@ enum class LutType
 std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT4"); }
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
 
 // Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("FACADE_FF"); }
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_FF; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("FACADE_SLICE"); }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_SLICE; }
 
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index b2ff51ae59..b216f8b4d1 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -116,3 +116,22 @@ X(CLK0)
 X(CLK1)
 X(SEL)
 X(DCMOUT)
+
+X(BEL)
+X(GND)
+X(IO_TYPE)
+X(LOC)
+X(NOM_FREQ)
+X(VCC)
+X(lcmxo2_1200hc)
+X(lcmxo2_2000hc)
+X(lcmxo2_256hc)
+X(lcmxo2_4000hc)
+X(lcmxo2_640hc)
+X(lcmxo2_7000hc)
+X(machxo2)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 0c2c945922..de6078656a 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -51,20 +51,20 @@ static void pack_lut_lutffs(Context *ctx)
             // LUT4 drives more than one FF.
             NetInfo *o = ci->ports.at(id_Z).net;
             CellInfo *dff = net_only_drives(ctx, o, is_ff, id_DI, false);
-            auto lut_bel = ci->attrs.find(ctx->id("BEL"));
+            auto lut_bel = ci->attrs.find(id_BEL);
             bool packed_dff = false;
 
             if (dff) {
                 if (ctx->verbose)
                     log_info("found attached dff %s\n", dff->name.c_str(ctx));
-                auto dff_bel = dff->attrs.find(ctx->id("BEL"));
+                auto dff_bel = dff->attrs.find(id_BEL);
                 if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
                     // Locations don't match, can't pack
                 } else {
                     lut_to_lc(ctx, ci, packed.get(), false);
                     dff_to_lc(ctx, dff, packed.get(), LutType::Normal);
                     if (dff_bel != dff->attrs.end())
-                        packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                        packed->attrs[id_BEL] = dff_bel->second;
                     packed_cells.insert(dff->name);
                     if (ctx->verbose)
                         log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
@@ -104,12 +104,12 @@ static void pack_remaining_ffs(Context *ctx)
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
 
-            auto dff_bel = ci->attrs.find(ctx->id("BEL"));
+            auto dff_bel = ci->attrs.find(id_BEL);
 
             dff_to_lc(ctx, ci, packed.get(), LutType::None);
 
             if (dff_bel != ci->attrs.end())
-                packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                packed->attrs[id_BEL] = dff_bel->second;
             packed_cells.insert(ci->name);
             if (ctx->verbose)
                 log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
@@ -198,12 +198,12 @@ static void pack_constants(Context *ctx)
 
     for (auto &net : ctx->nets) {
         NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, gnd_net, false);
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
-        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
             set_net_constant(ctx, ni, vcc_net, true);
             dead_nets.push_back(net.first);
@@ -294,8 +294,8 @@ static void pack_io(Context *ctx)
             // attribute already on a FACADE_IO is an error. Attributes on
             // the pin attached to the PAD of FACADE_IO are ignored by this
             // packing phase.
-            auto loc_attr_cell = ci->attrs.find(ctx->id("LOC"));
-            auto bel_attr_cell = ci->attrs.find(ctx->id("BEL"));
+            auto loc_attr_cell = ci->attrs.find(id_LOC);
+            auto bel_attr_cell = ci->attrs.find(id_BEL);
 
             if (loc_attr_cell != ci->attrs.end()) {
                 if (bel_attr_cell != ci->attrs.end()) {
@@ -312,7 +312,7 @@ static void pack_io(Context *ctx)
                 } else {
                     log_info("pin '%s' constrained to Bel '%s'.\n", ci->name.c_str(ctx), ctx->nameOfBel(pinBel));
                 }
-                ci->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
+                ci->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
             }
         }
     }
@@ -332,7 +332,7 @@ bool Arch::pack()
         pack_io(ctx);
         pack_lut_lutffs(ctx);
         pack_remaining_ffs(ctx);
-        ctx->settings[ctx->id("pack")] = 1;
+        ctx->settings[id_pack] = 1;
         ctx->assignArchInfo();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;
diff --git a/mistral/arch.cc b/mistral/arch.cc
index c50e30f49b..e79a391038 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -446,7 +446,7 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 bool Arch::place()
 {
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
 
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
@@ -468,7 +468,7 @@ bool Arch::place()
         log_error("Mistral architecture does not support placer '%s'\n", placer.c_str());
     }
 
-    getCtx()->attrs[getCtx()->id("step")] = std::string("place");
+    getCtx()->attrs[id_step] = std::string("place");
     archInfoToAttributes();
     return true;
 }
@@ -479,7 +479,7 @@ bool Arch::route()
 
     lab_pre_route();
 
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -489,7 +489,7 @@ bool Arch::route()
     } else {
         log_error("Mistral architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->attrs[getCtx()->id("step")] = std::string("route");
+    getCtx()->attrs[id_step] = std::string("route");
     archInfoToAttributes();
     return result;
 }
diff --git a/mistral/constids.inc b/mistral/constids.inc
index 2aa2c15739..d241c8ef2d 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -97,3 +97,11 @@ X(WE_INV)
 
 X(cyclonev_oscillator)
 X(cyclonev_hps_interface_mpu_general_purpose)
+
+X(clkout)
+X(clkout1)
+X(compress_rbf)
+X(oscena)
+X(placer)
+X(router)
+X(step)
diff --git a/mistral/globals.cc b/mistral/globals.cc
index d41b2afe62..1ba709191e 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -58,9 +58,9 @@ void Arch::create_hps_mpu_general_purpose(int x, int y)
 void Arch::create_control(int x, int y)
 {
     BelId oscillator_bel = add_bel(x, y, id_cyclonev_oscillator, id_cyclonev_oscillator);
-    add_bel_pin(oscillator_bel, id("oscena"), PORT_IN, get_port(CycloneV::CTRL, x, y, -1, CycloneV::OSC_ENA, -1));
-    add_bel_pin(oscillator_bel, id("clkout"), PORT_OUT, get_port(CycloneV::CTRL, x, y, -1, CycloneV::CLK_OUT, -1));
-    add_bel_pin(oscillator_bel, id("clkout1"), PORT_OUT, get_port(CycloneV::CTRL, x, y, -1, CycloneV::CLK_OUT1, -1));
+    add_bel_pin(oscillator_bel, id_oscena, PORT_IN, get_port(CycloneV::CTRL, x, y, -1, CycloneV::OSC_ENA, -1));
+    add_bel_pin(oscillator_bel, id_clkout, PORT_OUT, get_port(CycloneV::CTRL, x, y, -1, CycloneV::CLK_OUT, -1));
+    add_bel_pin(oscillator_bel, id_clkout1, PORT_OUT, get_port(CycloneV::CTRL, x, y, -1, CycloneV::CLK_OUT1, -1));
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/mistral/main.cc b/mistral/main.cc
index bd9ef59158..34bf759ee5 100644
--- a/mistral/main.cc
+++ b/mistral/main.cc
@@ -79,7 +79,7 @@ std::unique_ptr<Context> MistralCommandHandler::createContext(dict<std::string,
     chipArgs.device = vm["device"].as<std::string>();
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     if (vm.count("compress-rbf"))
-        ctx->settings[ctx->id("compress_rbf")] = Property::State::S1;
+        ctx->settings[id_compress_rbf] = Property::State::S1;
     return ctx;
 }
 
diff --git a/nexus/arch.cc b/nexus/arch.cc
index d553200fe0..cb8cacf8d0 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -186,8 +186,8 @@ Arch::Arch(ArchArgs args) : args(args)
                 disabled_pips.insert(pip);
         }
         // TODO: find a better solution to disable these
-        WireId dcs_out = getWireByName(
-                IdStringList(std::array<IdString, 3>{x_ids.at(37), y_ids.at(10), id("JDCSOUT_DCS_DCSIP")}));
+        WireId dcs_out =
+                getWireByName(IdStringList(std::array<IdString, 3>{x_ids.at(37), y_ids.at(10), id_JDCSOUT_DCS_DCSIP}));
         for (auto dcs_pip : getPipsUphill(dcs_out))
             disabled_pips.insert(dcs_pip);
         NPNR_ASSERT(disabled_pips.size() == 6);
@@ -300,13 +300,13 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
 
-    ret.emplace_back(id("INDEX"), stringf("%d", bel.index));
+    ret.emplace_back(id_INDEX, stringf("%d", bel.index));
 
-    ret.emplace_back(id("GRID_X"), stringf("%d", bel.tile % chip_info->width));
-    ret.emplace_back(id("GRID_Y"), stringf("%d", bel.tile / chip_info->width));
-    ret.emplace_back(id("BEL_Z"), stringf("%d", bel_data(bel).z));
+    ret.emplace_back(id_GRID_X, stringf("%d", bel.tile % chip_info->width));
+    ret.emplace_back(id_GRID_Y, stringf("%d", bel.tile / chip_info->width));
+    ret.emplace_back(id_BEL_Z, stringf("%d", bel_data(bel).z));
 
-    ret.emplace_back(id("BEL_TYPE"), nameOf(getBelType(bel)));
+    ret.emplace_back(id_BEL_TYPE, nameOf(getBelType(bel)));
 
     return ret;
 }
@@ -337,11 +337,11 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
 {
     std::vector<std::pair<IdString, std::string>> ret;
 
-    ret.emplace_back(id("INDEX"), stringf("%d", wire.index));
+    ret.emplace_back(id_INDEX, stringf("%d", wire.index));
 
-    ret.emplace_back(id("GRID_X"), stringf("%d", wire.tile % chip_info->width));
-    ret.emplace_back(id("GRID_Y"), stringf("%d", wire.tile / chip_info->width));
-    ret.emplace_back(id("FLAGS"), stringf("%u", wire_data(wire).flags));
+    ret.emplace_back(id_GRID_X, stringf("%d", wire.tile % chip_info->width));
+    ret.emplace_back(id_GRID_Y, stringf("%d", wire.tile / chip_info->width));
+    ret.emplace_back(id_FLAGS, stringf("%u", wire_data(wire).flags));
 
     return ret;
 }
@@ -388,13 +388,13 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
 
-    ret.emplace_back(id("INDEX"), stringf("%d", pip.index));
+    ret.emplace_back(id_INDEX, stringf("%d", pip.index));
 
-    ret.emplace_back(id("GRID_X"), stringf("%d", pip.tile % chip_info->width));
-    ret.emplace_back(id("GRID_Y"), stringf("%d", pip.tile / chip_info->width));
+    ret.emplace_back(id_GRID_X, stringf("%d", pip.tile % chip_info->width));
+    ret.emplace_back(id_GRID_Y, stringf("%d", pip.tile / chip_info->width));
 
-    ret.emplace_back(id("FROM_TILE_WIRE"), nameOf(IdString(loc_data(pip).wires[pip_data(pip).from_wire].name)));
-    ret.emplace_back(id("TO_TILE_WIRE"), nameOf(IdString(loc_data(pip).wires[pip_data(pip).to_wire].name)));
+    ret.emplace_back(id_FROM_TILE_WIRE, nameOf(IdString(loc_data(pip).wires[pip_data(pip).from_wire].name)));
+    ret.emplace_back(id_TO_TILE_WIRE, nameOf(IdString(loc_data(pip).wires[pip_data(pip).to_wire].name)));
 
     return ret;
 }
@@ -665,7 +665,7 @@ bool Arch::place()
     if (getCtx()->settings.count(getCtx()->id("estimate-delay-mult")))
         estimate_delay_mult = getCtx()->setting<int>("estimate-delay-mult");
 
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    std::string placer = str_or_default(settings, id_placer, defaultPlacer);
 
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
@@ -689,7 +689,7 @@ bool Arch::place()
 
     post_place_opt();
 
-    getCtx()->attrs[getCtx()->id("step")] = std::string("place");
+    getCtx()->attrs[id_step] = std::string("place");
     archInfoToAttributes();
     return true;
 }
@@ -740,7 +740,7 @@ bool Arch::route()
 
     route_globals();
 
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -752,7 +752,7 @@ bool Arch::route()
     } else {
         log_error("Nexus architecture does not support router '%s'\n", router.c_str());
     }
-    getCtx()->attrs[getCtx()->id("step")] = std::string("route");
+    getCtx()->attrs[id_step] = std::string("route");
     archInfoToAttributes();
     return result;
 }
diff --git a/nexus/constids.inc b/nexus/constids.inc
index ca6bed5a23..11726d3b1e 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -531,3 +531,24 @@ X(Q1)
 X(SCLK)
 
 X(LOCAL_VCC)
+
+X(BEL_TYPE)
+X(BEL_Z)
+X(CEOUTMUX)
+X(CLAMP)
+X(FLAGS)
+X(FROM_TILE_WIRE)
+X(GLITCHFILTER)
+X(GRID_X)
+X(GRID_Y)
+X(INDEX)
+X(JDCSOUT_DCS_DCSIP)
+X(PULLMODE)
+X(TO_TILE_WIRE)
+X(carry_lutff_ratio)
+X(no_pack_lutff)
+X(no_post_place_opt)
+X(placer)
+X(router)
+X(step)
+X(syn_useioff)
diff --git a/nexus/main.cc b/nexus/main.cc
index 88dddfe598..bca6661f66 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -79,15 +79,15 @@ std::unique_ptr<Context> NexusCommandHandler::createContext(dict<std::string, Pr
     chipArgs.device = vm["device"].as<std::string>();
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     if (vm.count("no-post-place-opt"))
-        ctx->settings[ctx->id("no_post_place_opt")] = Property::State::S1;
+        ctx->settings[id_no_post_place_opt] = Property::State::S1;
     if (vm.count("no-pack-lutff"))
-        ctx->settings[ctx->id("no_pack_lutff")] = Property::State::S1;
+        ctx->settings[id_no_pack_lutff] = Property::State::S1;
     if (vm.count("carry-lutff-ratio")) {
         float ratio = vm["carry-lutff-ratio"].as<float>();
         if (ratio < 0.0f || ratio > 1.0f) {
             log_error("Carry LUT+FF packing ration must be between 0.0 and 1.0");
         }
-        ctx->settings[ctx->id("carry_lutff_ratio")] = ratio;
+        ctx->settings[id_carry_lutff_ratio] = ratio;
     }
     if (vm.count("estimate-delay-mult"))
         ctx->settings[ctx->id("estimate-delay-mult")] = vm["estimate-delay-mult"].as<int>();
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 81a729b187..13522c78c7 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1132,7 +1132,7 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != id_LRAM_CORE)
                 continue;
-            if (str_or_default(ci->params, ctx->id("ECC_BYTE_SEL"), "BYTE_EN") == "BYTE_EN")
+            if (str_or_default(ci->params, id_ECC_BYTE_SEL, "BYTE_EN") == "BYTE_EN")
                 continue;
             for (int i = 0; i < 0x80; i++) {
                 // FIXME: document ECC and remove this DRC
@@ -1986,7 +1986,7 @@ struct NexusPacker
                 if (ci->type == id_DCC) {
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
                 } else if (ci->type == id_OSC_CORE) {
-                    int div = int_or_default(ci->params, ctx->id("HF_CLK_DIV"), 128);
+                    int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
                     const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
                     set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
                     set_period(ci, id_LFCLKOUT, delay_t((1.0e3 / 10) / tol));
@@ -2177,26 +2177,26 @@ struct NexusPacker
 
                 // We have IDDR+ODDR
                 if (isODDR && isIDDR) {
-                    if (!iob->attrs.count(ctx->id("GLITCHFILTER"))) {
-                        iob->attrs[ctx->id("GLITCHFILTER")] = std::string("ON");
+                    if (!iob->attrs.count(id_GLITCHFILTER)) {
+                        iob->attrs[id_GLITCHFILTER] = std::string("ON");
                     }
-                    if (!iob->attrs.count(ctx->id("CLAMP"))) {
-                        iob->attrs[ctx->id("CLAMP")] = std::string("ON");
+                    if (!iob->attrs.count(id_CLAMP)) {
+                        iob->attrs[id_CLAMP] = std::string("ON");
                     }
-                    if (!iob->attrs.count(ctx->id("PULLMODE"))) {
-                        iob->attrs[ctx->id("PULLMODE")] = std::string("DOWN");
+                    if (!iob->attrs.count(id_PULLMODE)) {
+                        iob->attrs[id_PULLMODE] = std::string("DOWN");
                     }
                 }
                 // We have ODDR only
                 else if (isODDR && !isIDDR) {
-                    if (!iob->attrs.count(ctx->id("GLITCHFILTER"))) {
-                        iob->attrs[ctx->id("GLITCHFILTER")] = std::string("OFF");
+                    if (!iob->attrs.count(id_GLITCHFILTER)) {
+                        iob->attrs[id_GLITCHFILTER] = std::string("OFF");
                     }
-                    if (!iob->attrs.count(ctx->id("CLAMP"))) {
-                        iob->attrs[ctx->id("CLAMP")] = std::string("OFF");
+                    if (!iob->attrs.count(id_CLAMP)) {
+                        iob->attrs[id_CLAMP] = std::string("OFF");
                     }
-                    if (!iob->attrs.count(ctx->id("PULLMODE"))) {
-                        iob->attrs[ctx->id("PULLMODE")] = std::string("NONE");
+                    if (!iob->attrs.count(id_PULLMODE)) {
+                        iob->attrs[id_PULLMODE] = std::string("NONE");
                     }
                 }
 
@@ -2237,8 +2237,8 @@ struct NexusPacker
                         // Check if the net wants to use the T flip-flop in
                         // IOLOGIC
                         bool syn_useioff = false;
-                        if (iob_t->attrs.count(ctx->id("syn_useioff"))) {
-                            syn_useioff = iob_t->attrs.at(ctx->id("syn_useioff")).as_bool();
+                        if (iob_t->attrs.count(id_syn_useioff)) {
+                            syn_useioff = iob_t->attrs.at(id_syn_useioff).as_bool();
                         }
 
                         // Check if the T input is driven by a flip-flop. Store
@@ -2281,7 +2281,7 @@ struct NexusPacker
                 iol->params[id_REGSET] = ff->params.at(id_REGSET);
 
                 // Enable the TSREG
-                iol->params[ctx->id("CEOUTMUX")] = std::string("1");
+                iol->params[id_CEOUTMUX] = std::string("1");
                 iol->params[ctx->id("TSREG.REGSET")] = std::string("SET");
                 iol->params[ctx->id("IDDRX1_ODDRX1.TRISTATE")] = std::string("ENABLED");
             }
@@ -2328,7 +2328,7 @@ struct NexusPacker
         log_info("Inferring LUT+FF pairs...\n");
 
         float carry_ratio = 1.0f;
-        if (ctx->settings.find(ctx->id("carry_lutff_ratio")) != ctx->settings.end()) {
+        if (ctx->settings.find(id_carry_lutff_ratio) != ctx->settings.end()) {
             carry_ratio = ctx->setting<float>("carry_lutff_ratio");
         }
 
@@ -2487,7 +2487,7 @@ struct NexusPacker
         pack_ip();
         handle_iologic();
 
-        if (!bool_or_default(ctx->settings, ctx->id("no_pack_lutff"))) {
+        if (!bool_or_default(ctx->settings, id_no_pack_lutff)) {
             pack_lutffs();
         }
 
@@ -2500,7 +2500,7 @@ struct NexusPacker
 bool Arch::pack()
 {
     (NexusPacker(getCtx()))();
-    attrs[id("step")] = std::string("pack");
+    attrs[id_step] = std::string("pack");
     archInfoToAttributes();
     assignArchInfo();
     return true;
diff --git a/nexus/post_place.cc b/nexus/post_place.cc
index eece4008ea..f42c0f1892 100644
--- a/nexus/post_place.cc
+++ b/nexus/post_place.cc
@@ -148,7 +148,7 @@ struct NexusPostPlaceOpt
 
 void Arch::post_place_opt()
 {
-    if (bool_or_default(settings, id("no_post_place_opt")))
+    if (bool_or_default(settings, id_no_post_place_opt))
         return;
     log_info("Running post-place optimisations...\n");
     NexusPostPlaceOpt opt(getCtx());

From 6a32aca4ac8705b637943c236cedd2f36422fb21 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 18 Feb 2022 10:52:37 +0000
Subject: [PATCH 069/712] refactor: New member functions to replace
 design_utils

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/basectx.cc                      |  15 +-
 common/basectx.h                       |   1 +
 common/design_utils.cc                 | 143 ------------
 common/design_utils.h                  |  26 ---
 common/nextpnr_types.cc                | 133 +++++++++++
 common/nextpnr_types.h                 |  21 ++
 ecp5/arch_place.cc                     |   4 +-
 ecp5/bitstream.cc                      |  28 ++-
 ecp5/cells.cc                          | 139 +++++------
 ecp5/globals.cc                        |   6 +-
 ecp5/pack.cc                           | 299 ++++++++++++------------
 fpga_interchange/arch_pack_clusters.cc |   2 +-
 fpga_interchange/macros.cc             |   6 +-
 fpga_interchange/site_router.cc        |   2 +-
 frontend/frontend_base.h               |  18 +-
 generic/arch.cc                        |   2 +-
 generic/cells.cc                       |  22 +-
 generic/pack.cc                        |   2 +-
 generic/viaduct/example/example.cc     |   6 +-
 generic/viaduct_helpers.cc             |   8 +-
 gowin/arch.cc                          |   6 +-
 gowin/cells.cc                         |  38 +--
 gowin/pack.cc                          |  66 +++---
 ice40/arch.cc                          |  14 +-
 ice40/cells.cc                         |  47 ++--
 ice40/pack.cc                          |  36 +--
 machxo2/cells.cc                       |  18 +-
 machxo2/pack.cc                        |   2 +-
 mistral/bitstream.cc                   |   9 +-
 mistral/lab.cc                         |  46 ++--
 mistral/pack.cc                        |  42 ++--
 nexus/fasm.cc                          |   8 +-
 nexus/pack.cc                          | 310 ++++++++++++-------------
 nexus/post_place.cc                    |   8 +-
 34 files changed, 765 insertions(+), 768 deletions(-)

diff --git a/common/basectx.cc b/common/basectx.cc
index b55cd072ab..83a2deea7b 100644
--- a/common/basectx.cc
+++ b/common/basectx.cc
@@ -22,7 +22,6 @@
 #include <boost/algorithm/string.hpp>
 
 #include "context.h"
-#include "design_utils.h"
 #include "log.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -223,13 +222,23 @@ void BaseCtx::connectPort(IdString net, IdString cell, IdString port)
 {
     NetInfo *net_info = getNetByAlias(net);
     CellInfo *cell_info = cells.at(cell).get();
-    connect_port(getCtx(), net_info, cell_info, port);
+    cell_info->connectPort(port, net_info);
 }
 
 void BaseCtx::disconnectPort(IdString cell, IdString port)
 {
     CellInfo *cell_info = cells.at(cell).get();
-    disconnect_port(getCtx(), cell_info, port);
+    cell_info->disconnectPort(port);
+}
+
+void BaseCtx::renameNet(IdString old_name, IdString new_name)
+{
+    NetInfo *net = nets.at(old_name).get();
+    NPNR_ASSERT(!nets.count(new_name));
+    nets[new_name];
+    std::swap(nets.at(net->name), nets.at(new_name));
+    nets.erase(net->name);
+    net->name = new_name;
 }
 
 void BaseCtx::ripupNet(IdString name)
diff --git a/common/basectx.h b/common/basectx.h
index 507f29cde9..21d6d63a9b 100644
--- a/common/basectx.h
+++ b/common/basectx.h
@@ -226,6 +226,7 @@ struct BaseCtx
     void disconnectPort(IdString cell, IdString port);
     void ripupNet(IdString name);
     void lockNetRouting(IdString name);
+    void renameNet(IdString old_name, IdString new_name);
 
     CellInfo *createCell(IdString name, IdString type);
     void copyBelPorts(IdString cell, BelId bel);
diff --git a/common/design_utils.cc b/common/design_utils.cc
index 9432b6cd71..f52cc30485 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -25,42 +25,6 @@
 #include "util.h"
 NEXTPNR_NAMESPACE_BEGIN
 
-void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdString rep_name)
-{
-    if (!old_cell->ports.count(old_name))
-        return;
-    PortInfo &old = old_cell->ports.at(old_name);
-
-    // Create port on the replacement cell if it doesn't already exist
-    if (!rep_cell->ports.count(rep_name)) {
-        rep_cell->ports[rep_name].name = rep_name;
-        rep_cell->ports[rep_name].type = old.type;
-    }
-
-    PortInfo &rep = rep_cell->ports.at(rep_name);
-    NPNR_ASSERT(old.type == rep.type);
-
-    rep.net = old.net;
-    old.net = nullptr;
-    if (rep.type == PORT_OUT) {
-        if (rep.net != nullptr) {
-            rep.net->driver.cell = rep_cell;
-            rep.net->driver.port = rep_name;
-        }
-    } else if (rep.type == PORT_IN) {
-        if (rep.net != nullptr) {
-            for (PortRef &load : rep.net->users) {
-                if (load.cell == old_cell && load.port == old_name) {
-                    load.cell = rep_cell;
-                    load.port = rep_name;
-                }
-            }
-        }
-    } else {
-        NPNR_ASSERT(false);
-    }
-}
-
 // Print utilisation of a design
 void print_utilisation(const Context *ctx)
 {
@@ -85,111 +49,4 @@ void print_utilisation(const Context *ctx)
     log_break();
 }
 
-// Connect a net to a port
-void connect_port(const Context *ctx, NetInfo *net, CellInfo *cell, IdString port_name)
-{
-    if (net == nullptr)
-        return;
-    PortInfo &port = cell->ports.at(port_name);
-    NPNR_ASSERT(port.net == nullptr);
-    port.net = net;
-    if (port.type == PORT_OUT) {
-        NPNR_ASSERT(net->driver.cell == nullptr);
-        net->driver.cell = cell;
-        net->driver.port = port_name;
-    } else if (port.type == PORT_IN || port.type == PORT_INOUT) {
-        PortRef user;
-        user.cell = cell;
-        user.port = port_name;
-        net->users.push_back(user);
-    } else {
-        NPNR_ASSERT_FALSE("invalid port type for connect_port");
-    }
-}
-
-void disconnect_port(const Context *ctx, CellInfo *cell, IdString port_name)
-{
-    if (!cell->ports.count(port_name))
-        return;
-    PortInfo &port = cell->ports.at(port_name);
-    if (port.net != nullptr) {
-        port.net->users.erase(std::remove_if(port.net->users.begin(), port.net->users.end(),
-                                             [cell, port_name](const PortRef &user) {
-                                                 return user.cell == cell && user.port == port_name;
-                                             }),
-                              port.net->users.end());
-        if (port.net->driver.cell == cell && port.net->driver.port == port_name)
-            port.net->driver.cell = nullptr;
-        port.net = nullptr;
-    }
-}
-
-void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo *cell2, IdString port2_name)
-{
-    PortInfo &port1 = cell1->ports.at(port1_name);
-    if (port1.net == nullptr) {
-        // No net on port1; need to create one
-        NetInfo *p1net = ctx->createNet(ctx->id(cell1->name.str(ctx) + "$conn$" + port1_name.str(ctx)));
-        connect_port(ctx, p1net, cell1, port1_name);
-    }
-    connect_port(ctx, port1.net, cell2, port2_name);
-}
-
-void rename_port(Context *ctx, CellInfo *cell, IdString old_name, IdString new_name)
-{
-    if (!cell->ports.count(old_name))
-        return;
-    PortInfo pi = cell->ports.at(old_name);
-    if (pi.net != nullptr) {
-        if (pi.net->driver.cell == cell && pi.net->driver.port == old_name)
-            pi.net->driver.port = new_name;
-        for (auto &usr : pi.net->users)
-            if (usr.cell == cell && usr.port == old_name)
-                usr.port = new_name;
-    }
-    cell->ports.erase(old_name);
-    pi.name = new_name;
-    cell->ports[new_name] = pi;
-}
-
-void rename_net(Context *ctx, NetInfo *net, IdString new_name)
-{
-    if (net == nullptr)
-        return;
-    NPNR_ASSERT(!ctx->nets.count(new_name));
-    ctx->nets[new_name];
-    std::swap(ctx->nets.at(net->name), ctx->nets.at(new_name));
-    ctx->nets.erase(net->name);
-    net->name = new_name;
-}
-
-void replace_bus(Context *ctx, CellInfo *old_cell, IdString old_name, int old_offset, bool old_brackets,
-                 CellInfo *new_cell, IdString new_name, int new_offset, bool new_brackets, int width)
-{
-    for (int i = 0; i < width; i++) {
-        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
-        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
-        replace_port(old_cell, old_port, new_cell, new_port);
-    }
-}
-
-void copy_port(Context *ctx, CellInfo *old_cell, IdString old_name, CellInfo *new_cell, IdString new_name)
-{
-    if (!old_cell->ports.count(old_name))
-        return;
-    new_cell->ports[new_name].name = new_name;
-    new_cell->ports[new_name].type = old_cell->ports.at(old_name).type;
-    connect_port(ctx, old_cell->ports.at(old_name).net, new_cell, new_name);
-}
-
-void copy_bus(Context *ctx, CellInfo *old_cell, IdString old_name, int old_offset, bool old_brackets,
-              CellInfo *new_cell, IdString new_name, int new_offset, bool new_brackets, int width)
-{
-    for (int i = 0; i < width; i++) {
-        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
-        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
-        copy_port(ctx, old_cell, old_port, new_cell, new_port);
-    }
-}
-
 NEXTPNR_NAMESPACE_END
diff --git a/common/design_utils.h b/common/design_utils.h
index 82c9ac4530..63cb71d7b3 100644
--- a/common/design_utils.h
+++ b/common/design_utils.h
@@ -89,34 +89,8 @@ inline bool port_used(CellInfo *cell, IdString port_name)
     return port_fnd != cell->ports.end() && port_fnd->second.net != nullptr;
 }
 
-// Connect a net to a port
-void connect_port(const Context *ctx, NetInfo *net, CellInfo *cell, IdString port_name);
-
-// Disconnect a net from a port
-void disconnect_port(const Context *ctx, CellInfo *cell, IdString port_name);
-
-// Connect two ports together
-void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo *cell2, IdString port2_name);
-
-// Rename a port if it exists on a cell
-void rename_port(Context *ctx, CellInfo *cell, IdString old_name, IdString new_name);
-
-// Rename a net without invalidating pointers to it
-void rename_net(Context *ctx, NetInfo *net, IdString new_name);
-
 void print_utilisation(const Context *ctx);
 
-// Disconnect a bus of nets (if connected) from old, and connect it to the new ports
-void replace_bus(Context *ctx, CellInfo *old_cell, IdString old_name, int old_offset, bool old_brackets,
-                 CellInfo *new_cell, IdString new_name, int new_offset, bool new_brackets, int width);
-
-// Copy a bus of nets (if connected) from old, and connect it to the new ports
-void copy_bus(Context *ctx, CellInfo *old_cell, IdString old_name, int old_offset, bool old_brackets,
-              CellInfo *new_cell, IdString new_name, int new_offset, bool new_brackets, int width);
-
-// Copy a port from one cell to another
-void copy_port(Context *ctx, CellInfo *old_cell, IdString old_name, CellInfo *new_cell, IdString new_name);
-
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/common/nextpnr_types.cc b/common/nextpnr_types.cc
index 3deed46fe5..c89a007102 100644
--- a/common/nextpnr_types.cc
+++ b/common/nextpnr_types.cc
@@ -18,6 +18,8 @@
  */
 
 #include "nextpnr_types.h"
+#include "context.h"
+#include "log.h"
 
 #include "nextpnr_namespaces.h"
 
@@ -49,4 +51,135 @@ bool CellInfo::testRegion(BelId bel) const
     return region == nullptr || !region->constr_bels || region->bels.count(bel);
 }
 
+void CellInfo::connectPort(IdString port_name, NetInfo *net)
+{
+    if (net == nullptr)
+        return;
+    PortInfo &port = ports.at(port_name);
+    NPNR_ASSERT(port.net == nullptr);
+    port.net = net;
+    if (port.type == PORT_OUT) {
+        NPNR_ASSERT(net->driver.cell == nullptr);
+        net->driver.cell = this;
+        net->driver.port = port_name;
+    } else if (port.type == PORT_IN || port.type == PORT_INOUT) {
+        PortRef user;
+        user.cell = this;
+        user.port = port_name;
+        net->users.push_back(user);
+    } else {
+        NPNR_ASSERT_FALSE("invalid port type for connect_port");
+    }
+}
+
+void CellInfo::disconnectPort(IdString port_name)
+{
+    if (!ports.count(port_name))
+        return;
+    PortInfo &port = ports.at(port_name);
+    if (port.net != nullptr) {
+        port.net->users.erase(std::remove_if(port.net->users.begin(), port.net->users.end(),
+                                             [this, port_name](const PortRef &user) {
+                                                 return user.cell == this && user.port == port_name;
+                                             }),
+                              port.net->users.end());
+        if (port.net->driver.cell == this && port.net->driver.port == port_name)
+            port.net->driver.cell = nullptr;
+        port.net = nullptr;
+    }
+}
+
+void CellInfo::connectPorts(IdString port, CellInfo *other, IdString other_port)
+{
+    PortInfo &port1 = ports.at(port);
+    if (port1.net == nullptr) {
+        // No net on port1; need to create one
+        NetInfo *p1net = ctx->createNet(ctx->id(name.str(ctx) + "$conn$" + port.str(ctx)));
+        connectPort(port, p1net);
+    }
+    other->connectPort(other_port, port1.net);
+}
+
+void CellInfo::movePortTo(IdString port, CellInfo *other, IdString other_port)
+{
+    if (!ports.count(port))
+        return;
+    PortInfo &old = ports.at(port);
+
+    // Create port on the replacement cell if it doesn't already exist
+    if (!other->ports.count(other_port)) {
+        other->ports[other_port].name = other_port;
+        other->ports[other_port].type = old.type;
+    }
+
+    PortInfo &rep = other->ports.at(other_port);
+    NPNR_ASSERT(old.type == rep.type);
+
+    rep.net = old.net;
+    old.net = nullptr;
+    if (rep.type == PORT_OUT) {
+        if (rep.net != nullptr) {
+            rep.net->driver.cell = other;
+            rep.net->driver.port = other_port;
+        }
+    } else if (rep.type == PORT_IN) {
+        if (rep.net != nullptr) {
+            for (PortRef &load : rep.net->users) {
+                if (load.cell == this && load.port == port) {
+                    load.cell = other;
+                    load.port = other_port;
+                }
+            }
+        }
+    } else {
+        NPNR_ASSERT(false);
+    }
+}
+
+void CellInfo::renamePort(IdString old_name, IdString new_name)
+{
+    if (!ports.count(old_name))
+        return;
+    PortInfo pi = ports.at(old_name);
+    if (pi.net != nullptr) {
+        if (pi.net->driver.cell == this && pi.net->driver.port == old_name)
+            pi.net->driver.port = new_name;
+        for (auto &usr : pi.net->users)
+            if (usr.cell == this && usr.port == old_name)
+                usr.port = new_name;
+    }
+    ports.erase(old_name);
+    pi.name = new_name;
+    ports[new_name] = pi;
+}
+
+void CellInfo::movePortBusTo(IdString old_name, int old_offset, bool old_brackets, CellInfo *new_cell,
+                             IdString new_name, int new_offset, bool new_brackets, int width)
+{
+    for (int i = 0; i < width; i++) {
+        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
+        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
+        movePortTo(old_port, new_cell, new_port);
+    }
+}
+
+void CellInfo::copyPortTo(IdString port, CellInfo *other, IdString other_port)
+{
+    if (!ports.count(port))
+        return;
+    other->ports[other_port].name = other_port;
+    other->ports[other_port].type = ports.at(port).type;
+    other->connectPort(other_port, ports.at(port).net);
+}
+
+void CellInfo::copyPortBusTo(IdString old_name, int old_offset, bool old_brackets, CellInfo *new_cell,
+                             IdString new_name, int new_offset, bool new_brackets, int width)
+{
+    for (int i = 0; i < width; i++) {
+        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
+        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
+        copyPortTo(old_port, new_cell, new_port);
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index 6debd2b8df..cf93a0714d 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -187,6 +187,27 @@ struct CellInfo : ArchCellInfo
     void unsetAttr(IdString name);
     // check whether a bel complies with the cell's region constraint
     bool testRegion(BelId bel) const;
+
+    NetInfo *getPort(IdString name)
+    {
+        auto found = ports.find(name);
+        return (found == ports.end()) ? nullptr : found->second.net;
+    }
+    const NetInfo *getPort(IdString name) const
+    {
+        auto found = ports.find(name);
+        return (found == ports.end()) ? nullptr : found->second.net;
+    }
+    void connectPort(IdString port, NetInfo *net);
+    void disconnectPort(IdString port);
+    void connectPorts(IdString port, CellInfo *other, IdString other_port);
+    void movePortTo(IdString port, CellInfo *other, IdString other_port);
+    void renamePort(IdString old_name, IdString new_name);
+    void movePortBusTo(IdString old_name, int old_offset, bool old_brackets, CellInfo *new_cell, IdString new_name,
+                       int new_offset, bool new_brackets, int width);
+    void copyPortTo(IdString port, CellInfo *other, IdString other_port);
+    void copyPortBusTo(IdString old_name, int old_offset, bool old_brackets, CellInfo *new_cell, IdString new_name,
+                       int new_offset, bool new_brackets, int width);
 };
 
 enum TimingPortClass
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index a1f8aa1f04..b1849ee672 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -124,10 +124,10 @@ void Arch::permute_luts()
         for (int i = 0; i < 4; i++) {
             IdString p = port_names.at(i);
             // log_info("%s %s %f\n", p.c_str(ctx), port_names.at(inputs.at(i).second).c_str(ctx), inputs.at(i).first);
-            disconnect_port(getCtx(), ci, p);
+            ci->disconnectPort(p);
             ci->ports.at(p).net = nullptr;
             if (orig_nets.at(inputs.at(i).second) != nullptr) {
-                connect_port(getCtx(), orig_nets.at(inputs.at(i).second), ci, p);
+                ci->connectPort(p, orig_nets.at(inputs.at(i).second));
                 ci->params[id(p.str(this) + "MUX")] = p.str(this);
             } else {
                 ci->params[id(p.str(this) + "MUX")] = std::string("1");
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 11a855ec48..a23e4cd2e5 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -1043,7 +1043,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             if (trimux_tsreg != "PADDT")
                 cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
         } else if (ci->type == id_DCCA) {
-            const NetInfo *cen = get_net_or_empty(ci, id_CE);
+            const NetInfo *cen = ci->getPort(id_CE);
             if (cen != nullptr) {
                 std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get();
                 Loc loc = ctx->getBelLocation(bel);
@@ -1347,13 +1347,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
 
             tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, id_OUTDIVIDER_MUXA,
-                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
+                                                                 ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK"));
             tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, id_OUTDIVIDER_MUXB,
-                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
+                                                                 ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK"));
             tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, id_OUTDIVIDER_MUXC,
-                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
+                                                                 ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK"));
             tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, id_OUTDIVIDER_MUXD,
-                                                                 get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
+                                                                 ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK"));
 
             tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
 
@@ -1404,7 +1404,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 else
                     cc.tiles[pic_tile].add_enum(prim + "." + param.first.str(ctx), param.second.as_string());
             }
-            if (get_net_or_empty(ci, id_LOADN) != nullptr) {
+            if (ci->getPort(id_LOADN) != nullptr) {
                 cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN");
             }
         } else if (ci->type == id_DCUA) {
@@ -1481,14 +1481,12 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 lo_del_value = (256 - lo_del_value) & 0xFF;
             tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
             tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
-            tg.config.add_enum("DQS.WRLOADN_USED", get_net_or_empty(ci, id_WRLOADN) != nullptr ? "YES" : "NO");
-            tg.config.add_enum("DQS.RDLOADN_USED", get_net_or_empty(ci, id_RDLOADN) != nullptr ? "YES" : "NO");
-            tg.config.add_enum("DQS.PAUSE_USED", get_net_or_empty(ci, id_PAUSE) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.WRLOADN_USED", ci->getPort(id_WRLOADN) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.RDLOADN_USED", ci->getPort(id_RDLOADN) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.PAUSE_USED", ci->getPort(id_PAUSE) != nullptr ? "YES" : "NO");
             tg.config.add_enum("DQS.READ_USED",
-                               (get_net_or_empty(ci, id_READ0) != nullptr || get_net_or_empty(ci, id_READ1) != nullptr)
-                                       ? "YES"
-                                       : "NO");
-            tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
+                               (ci->getPort(id_READ0) != nullptr || ci->getPort(id_READ1) != nullptr) ? "YES" : "NO");
+            tg.config.add_enum("DQS.DDRDEL", ci->getPort(id_DDRDEL) != nullptr ? "DDRDEL" : "0");
             tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
             cc.tilegroups.push_back(tg);
         } else if (ci->type == id_ECLKSYNCB) {
@@ -1496,14 +1494,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             bool r = loc.x > 5;
             std::string eclksync = ctx->loc_info(bel)->bel_data[bel.index].name.get();
             std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            if (get_net_or_empty(ci, id_STOP) != nullptr)
+            if (ci->getPort(id_STOP) != nullptr)
                 cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
         } else if (ci->type == id_ECLKBRIDGECS) {
             Loc loc = ctx->getBelLocation(ci->bel);
             bool r = loc.x > 5;
             std::string eclkb = ctx->loc_info(bel)->bel_data[bel.index].name.get();
             std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            if (get_net_or_empty(ci, id_STOP) != nullptr)
+            if (ci->getPort(id_STOP) != nullptr)
                 cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
         } else if (ci->type == id_DDRDLL) {
             Loc loc = ctx->getBelLocation(ci->bel);
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 6d88af7529..a5d484ff23 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -217,7 +217,7 @@ static void replace_port_safe(bool has_ff, CellInfo *ff, IdString ff_port, CellI
                                    [ff, ff_port](PortRef port) { return port.cell == ff && port.port == ff_port; }),
                     ffnet->users.end());
     } else {
-        replace_port(ff, ff_port, lc, lc_port);
+        ff->movePortTo(ff_port, lc, lc_port);
     }
 }
 
@@ -242,21 +242,21 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
     if (ff->ports.find(id_CE) != ff->ports.end())
         replace_port_safe(has_ff, ff, id_CE, lc, id_CE);
 
-    replace_port(ff, id_Q, lc, ctx->id("Q" + std::to_string(index)));
-    if (get_net_or_empty(ff, id_M) != nullptr) {
+    ff->movePortTo(id_Q, lc, ctx->id("Q" + std::to_string(index)));
+    if (ff->getPort(id_M) != nullptr) {
         // PRLD FFs that use both M and DI
         NPNR_ASSERT(!driven_by_lut);
         // As M is used; must route DI through a new LUT
         lc->params[ctx->id(reg + "_SD")] = std::string("1");
         lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16);
-        replace_port(ff, id_DI, lc, ctx->id("D" + std::to_string(index)));
-        replace_port(ff, id_M, lc, ctx->id("M" + std::to_string(index)));
-        connect_ports(ctx, lc, ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
+        ff->movePortTo(id_DI, lc, ctx->id("D" + std::to_string(index)));
+        ff->movePortTo(id_M, lc, ctx->id("M" + std::to_string(index)));
+        lc->connectPorts(ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
     } else {
         if (driven_by_lut) {
-            replace_port(ff, id_DI, lc, ctx->id("DI" + std::to_string(index)));
+            ff->movePortTo(id_DI, lc, ctx->id("DI" + std::to_string(index)));
         } else {
-            replace_port(ff, id_DI, lc, ctx->id("M" + std::to_string(index)));
+            ff->movePortTo(id_DI, lc, ctx->id("M" + std::to_string(index)));
         }
     }
 }
@@ -267,11 +267,11 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
         lc->hierpath = lut->hierpath;
     lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
             get_or_default(lut->params, id_INIT, Property(0, 16));
-    replace_port(lut, id_A, lc, ctx->id("A" + std::to_string(index)));
-    replace_port(lut, id_B, lc, ctx->id("B" + std::to_string(index)));
-    replace_port(lut, id_C, lc, ctx->id("C" + std::to_string(index)));
-    replace_port(lut, id_D, lc, ctx->id("D" + std::to_string(index)));
-    replace_port(lut, id_Z, lc, ctx->id("F" + std::to_string(index)));
+    lut->movePortTo(id_A, lc, ctx->id("A" + std::to_string(index)));
+    lut->movePortTo(id_B, lc, ctx->id("B" + std::to_string(index)));
+    lut->movePortTo(id_C, lc, ctx->id("C" + std::to_string(index)));
+    lut->movePortTo(id_D, lc, ctx->id("D" + std::to_string(index)));
+    lut->movePortTo(id_Z, lc, ctx->id("F" + std::to_string(index)));
 }
 
 void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
@@ -285,22 +285,22 @@ void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
     lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES");
     lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES");
 
-    replace_port(ccu, id_CIN, lc, id_FCI);
+    ccu->movePortTo(id_CIN, lc, id_FCI);
 
-    replace_port(ccu, id_A0, lc, id_A0);
-    replace_port(ccu, id_B0, lc, id_B0);
-    replace_port(ccu, id_C0, lc, id_C0);
-    replace_port(ccu, id_D0, lc, id_D0);
+    ccu->movePortTo(id_A0, lc, id_A0);
+    ccu->movePortTo(id_B0, lc, id_B0);
+    ccu->movePortTo(id_C0, lc, id_C0);
+    ccu->movePortTo(id_D0, lc, id_D0);
 
-    replace_port(ccu, id_A1, lc, id_A1);
-    replace_port(ccu, id_B1, lc, id_B1);
-    replace_port(ccu, id_C1, lc, id_C1);
-    replace_port(ccu, id_D1, lc, id_D1);
+    ccu->movePortTo(id_A1, lc, id_A1);
+    ccu->movePortTo(id_B1, lc, id_B1);
+    ccu->movePortTo(id_C1, lc, id_C1);
+    ccu->movePortTo(id_D1, lc, id_D1);
 
-    replace_port(ccu, id_S0, lc, id_F0);
-    replace_port(ccu, id_S1, lc, id_F1);
+    ccu->movePortTo(id_S0, lc, id_F0);
+    ccu->movePortTo(id_S1, lc, id_F1);
 
-    replace_port(ccu, id_COUT, lc, id_FCO);
+    ccu->movePortTo(id_COUT, lc, id_FCO);
 }
 
 void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
@@ -308,15 +308,15 @@ void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
     if (lc->hierpath == IdString())
         lc->hierpath = ram->hierpath;
     lc->params[id_MODE] = std::string("RAMW");
-    replace_port(ram, ctx->id("WAD[0]"), lc, id_D0);
-    replace_port(ram, ctx->id("WAD[1]"), lc, id_B0);
-    replace_port(ram, ctx->id("WAD[2]"), lc, id_C0);
-    replace_port(ram, ctx->id("WAD[3]"), lc, id_A0);
-
-    replace_port(ram, ctx->id("DI[0]"), lc, id_C1);
-    replace_port(ram, ctx->id("DI[1]"), lc, id_A1);
-    replace_port(ram, ctx->id("DI[2]"), lc, id_D1);
-    replace_port(ram, ctx->id("DI[3]"), lc, id_B1);
+    ram->movePortTo(ctx->id("WAD[0]"), lc, id_D0);
+    ram->movePortTo(ctx->id("WAD[1]"), lc, id_B0);
+    ram->movePortTo(ctx->id("WAD[2]"), lc, id_C0);
+    ram->movePortTo(ctx->id("WAD[3]"), lc, id_A0);
+
+    ram->movePortTo(ctx->id("DI[0]"), lc, id_C1);
+    ram->movePortTo(ctx->id("DI[1]"), lc, id_A1);
+    ram->movePortTo(ctx->id("DI[2]"), lc, id_D1);
+    ram->movePortTo(ctx->id("DI[3]"), lc, id_B1);
 }
 
 static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
@@ -367,45 +367,45 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
     lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16);
 
     if (ram->ports.count(ctx->id("RAD[0]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D0);
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D1);
+        lc->connectPort(id_D0, ram->ports.at(ctx->id("RAD[0]")).net);
+        lc->connectPort(id_D1, ram->ports.at(ctx->id("RAD[0]")).net);
     }
     if (ram->ports.count(ctx->id("RAD[1]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B0);
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B1);
+        lc->connectPort(id_B0, ram->ports.at(ctx->id("RAD[1]")).net);
+        lc->connectPort(id_B1, ram->ports.at(ctx->id("RAD[1]")).net);
     }
     if (ram->ports.count(ctx->id("RAD[2]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C0);
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C1);
+        lc->connectPort(id_C0, ram->ports.at(ctx->id("RAD[2]")).net);
+        lc->connectPort(id_C1, ram->ports.at(ctx->id("RAD[2]")).net);
     }
     if (ram->ports.count(ctx->id("RAD[3]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A0);
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A1);
+        lc->connectPort(id_A0, ram->ports.at(ctx->id("RAD[3]")).net);
+        lc->connectPort(id_A1, ram->ports.at(ctx->id("RAD[3]")).net);
     }
 
     if (ram->ports.count(id_WRE))
-        connect_port(ctx, ram->ports.at(id_WRE).net, lc, id_WRE);
+        lc->connectPort(id_WRE, ram->ports.at(id_WRE).net);
     if (ram->ports.count(id_WCK))
-        connect_port(ctx, ram->ports.at(id_WCK).net, lc, id_WCK);
+        lc->connectPort(id_WCK, ram->ports.at(id_WCK).net);
 
-    connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0);
-    connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1);
-    connect_ports(ctx, ramw, id_WADO2, lc, id_WAD2);
-    connect_ports(ctx, ramw, id_WADO3, lc, id_WAD3);
+    ramw->connectPorts(id_WADO0, lc, id_WAD0);
+    ramw->connectPorts(id_WADO1, lc, id_WAD1);
+    ramw->connectPorts(id_WADO2, lc, id_WAD2);
+    ramw->connectPorts(id_WADO3, lc, id_WAD3);
 
     if (index == 0) {
-        connect_ports(ctx, ramw, id_WDO0, lc, id_WD0);
-        connect_ports(ctx, ramw, id_WDO1, lc, id_WD1);
+        ramw->connectPorts(id_WDO0, lc, id_WD0);
+        ramw->connectPorts(id_WDO1, lc, id_WD1);
 
-        replace_port(ram, ctx->id("DO[0]"), lc, id_F0);
-        replace_port(ram, ctx->id("DO[1]"), lc, id_F1);
+        ram->movePortTo(ctx->id("DO[0]"), lc, id_F0);
+        ram->movePortTo(ctx->id("DO[1]"), lc, id_F1);
 
     } else if (index == 1) {
-        connect_ports(ctx, ramw, id_WDO2, lc, id_WD0);
-        connect_ports(ctx, ramw, id_WDO3, lc, id_WD1);
+        ramw->connectPorts(id_WDO2, lc, id_WD0);
+        ramw->connectPorts(id_WDO3, lc, id_WD1);
 
-        replace_port(ram, ctx->id("DO[2]"), lc, id_F0);
-        replace_port(ram, ctx->id("DO[3]"), lc, id_F1);
+        ram->movePortTo(ctx->id("DO[2]"), lc, id_F0);
+        ram->movePortTo(ctx->id("DO[3]"), lc, id_F1);
     } else {
         NPNR_ASSERT_FALSE("bad DPRAM index");
     }
@@ -416,21 +416,21 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
         trio->params[id_DIR] = std::string("INPUT");
-        replace_port(nxio, id_O, trio, id_O);
+        nxio->movePortTo(id_O, trio, id_O);
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
         trio->params[id_DIR] = std::string("OUTPUT");
-        replace_port(nxio, id_I, trio, id_I);
+        nxio->movePortTo(id_I, trio, id_I);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        NetInfo *i = get_net_or_empty(nxio, id_I);
+        NetInfo *i = nxio->getPort(id_I);
         if (i == nullptr || i->driver.cell == nullptr)
             trio->params[id_DIR] = std::string("INPUT");
         else {
             log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
             trio->params[id_DIR] = std::string("BIDIR");
         }
-        replace_port(nxio, id_I, trio, id_I);
-        replace_port(nxio, id_O, trio, id_O);
+        nxio->movePortTo(id_I, trio, id_I);
+        nxio->movePortTo(id_O, trio, id_O);
     } else {
         NPNR_ASSERT(false);
     }
@@ -438,9 +438,11 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
 
     // Rename I/O nets to avoid conflicts
     if (donet != nullptr && donet->name == nxio->name)
-        rename_net(ctx, donet, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT"));
+        if (donet)
+            ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT"));
     if (dinet != nullptr && dinet->name == nxio->name)
-        rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
+        if (dinet)
+            ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
 
     if (ctx->nets.count(nxio->name)) {
         int i = 0;
@@ -448,7 +450,8 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         do {
             new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
         } while (ctx->nets.count(new_name));
-        rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+        if (ctx->nets.at(nxio->name).get())
+            ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name);
     }
 
     // Create a new top port net for accurate IO timing analysis and simulation netlists
@@ -458,7 +461,7 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         ctx->net_aliases.erase(tn_netname);
         NetInfo *toplevel_net = ctx->createNet(tn_netname);
         toplevel_net->name = tn_netname;
-        connect_port(ctx, toplevel_net, trio, id_B);
+        trio->connectPort(id_B, toplevel_net);
         ctx->ports[nxio->name].net = toplevel_net;
     }
 
@@ -466,12 +469,12 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
             ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
             id_Y);
     if (tbuf) {
-        replace_port(tbuf, id_A, trio, id_I);
+        tbuf->movePortTo(id_A, trio, id_I);
         // Need to invert E to form T
         std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
-        replace_port(tbuf, id_E, inv_lut.get(), id_A);
+        tbuf->movePortTo(id_E, inv_lut.get(), id_A);
         inv_lut->params[id_INIT] = Property(21845, 16);
-        connect_ports(ctx, inv_lut.get(), id_Z, trio, id_T);
+        inv_lut->connectPorts(id_Z, trio, id_T);
         created_cells.push_back(std::move(inv_lut));
 
         if (donet->users.size() > 1) {
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 844c596b91..7b48e69388 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -399,7 +399,7 @@ class Ecp5GlobalRouter
     {
         BelId best_bel;
         WireId best_bel_pclkcib;
-        bool using_ce = get_net_or_empty(dcc, id_CE) != nullptr;
+        bool using_ce = dcc->getPort(id_CE) != nullptr;
         wirelen_t best_wirelen = 9999999;
         bool dedicated_routing = false;
         for (auto bel : ctx->getBels()) {
@@ -533,7 +533,7 @@ class Ecp5GlobalRouter
         }
         for (auto ci : dcsc_cells) {
             for (auto port : {id_CLK0, id_CLK1}) {
-                NetInfo *net = get_net_or_empty(ci, port);
+                NetInfo *net = ci->getPort(port);
                 if (net != nullptr)
                     insert_dcc(net, ci);
             }
@@ -609,7 +609,7 @@ class Ecp5GlobalRouter
                     pins.push_back(id_CLK1);
                 }
                 for (auto pin : pins) {
-                    NetInfo *ni = get_net_or_empty(ci, pin);
+                    NetInfo *ni = ci->getPort(pin);
                     if (ni == nullptr)
                         continue;
                     log_info("    trying dedicated routing for edge clock source %s\n", ctx->nameOf(ni));
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index d49dbdf37b..2b069db098 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -112,7 +112,7 @@ class Ecp5Packer
                 if (znet != nullptr) {
                     CellInfo *ff = net_only_drives(ctx, znet, is_ff, id_DI, false);
                     // Can't combine preload FF with LUT due to conflict on M
-                    if (ff != nullptr && get_net_or_empty(ff, id_M) == nullptr) {
+                    if (ff != nullptr && ff->getPort(id_M) == nullptr) {
                         lutffPairs[ci->name] = ff->name;
                         fflutPairs[ff->name] = ci->name;
                     }
@@ -124,9 +124,9 @@ class Ecp5Packer
     // Check if a flipflop is available in a slice
     bool is_ff_available(CellInfo *slice, int ff)
     {
-        if (get_net_or_empty(slice, (ff == 1) ? id_Q1 : id_Q0) != nullptr)
+        if (slice->getPort((ff == 1) ? id_Q1 : id_Q0) != nullptr)
             return false;
-        if (get_net_or_empty(slice, (ff == 1) ? id_M1 : id_M0) != nullptr)
+        if (slice->getPort((ff == 1) ? id_M1 : id_M0) != nullptr)
             return false;
         return true;
     }
@@ -146,8 +146,8 @@ class Ecp5Packer
             if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
                 return false;
         }
-        bool has_ff0 = get_net_or_empty(slice, id_Q0) != nullptr;
-        bool has_ff1 = get_net_or_empty(slice, id_Q1) != nullptr;
+        bool has_ff0 = slice->getPort(id_Q0) != nullptr;
+        bool has_ff1 = slice->getPort(id_Q1) != nullptr;
         if (!has_ff0 && !has_ff1)
             return true;
         if (str_or_default(ff->params, id_GSR, "DISABLED") != str_or_default(slice->params, id_GSR, "DISABLED"))
@@ -224,7 +224,7 @@ class Ecp5Packer
     // Return true if a FF can be added to a DPRAM slice
     bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
     {
-        if (get_net_or_empty(ff, id_M) != nullptr)
+        if (ff->getPort(id_M) != nullptr)
             return false; // skip PRLD FFs due to M/DI conflict
         std::string wckmux = str_or_default(dpram->params, id_WCKMUX, "WCK");
         std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
@@ -452,7 +452,7 @@ class Ecp5Packer
                     // No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
                     // and leave the top level port
                     for (auto &port : ci->ports)
-                        disconnect_port(ctx, ci, port.first);
+                        ci->disconnectPort(port.first);
                 } else if (trio != nullptr) {
                     // Trivial case, TRELLIS_IO used. Just remove the IOBUF
                     log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
@@ -498,7 +498,7 @@ class Ecp5Packer
                     trio = new_cells.back().get();
                 }
                 for (auto port : ci->ports)
-                    disconnect_port(ctx, ci, port.first);
+                    ci->disconnectPort(port.first);
                 packed_cells.insert(ci->name);
                 if (trio != nullptr) {
                     for (const auto &attr : ci->attrs)
@@ -546,16 +546,16 @@ class Ecp5Packer
                     log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
                 if (ctx->verbose)
                     log_info("   mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
-                replace_port(lut0, id_A, packed.get(), id_A0);
-                replace_port(lut0, id_B, packed.get(), id_B0);
-                replace_port(lut0, id_C, packed.get(), id_C0);
-                replace_port(lut0, id_D, packed.get(), id_D0);
-                replace_port(lut1, id_A, packed.get(), id_A1);
-                replace_port(lut1, id_B, packed.get(), id_B1);
-                replace_port(lut1, id_C, packed.get(), id_C1);
-                replace_port(lut1, id_D, packed.get(), id_D1);
-                replace_port(ci, id_C0, packed.get(), id_M0);
-                replace_port(ci, id_Z, packed.get(), id_OFX0);
+                lut0->movePortTo(id_A, packed.get(), id_A0);
+                lut0->movePortTo(id_B, packed.get(), id_B0);
+                lut0->movePortTo(id_C, packed.get(), id_C0);
+                lut0->movePortTo(id_D, packed.get(), id_D0);
+                lut1->movePortTo(id_A, packed.get(), id_A1);
+                lut1->movePortTo(id_B, packed.get(), id_B1);
+                lut1->movePortTo(id_C, packed.get(), id_C1);
+                lut1->movePortTo(id_D, packed.get(), id_D1);
+                ci->movePortTo(id_C0, packed.get(), id_M0);
+                ci->movePortTo(id_Z, packed.get(), id_OFX0);
                 packed->params[id_LUT0_INITVAL] = get_or_default(lut0->params, id_INIT, Property(0, 16));
                 packed->params[id_LUT1_INITVAL] = get_or_default(lut1->params, id_INIT, Property(0, 16));
 
@@ -611,10 +611,10 @@ class Ecp5Packer
                 }
                 if (ctx->verbose)
                     log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
-                replace_port(ci, id_D0, slice1, id_FXA);
-                replace_port(ci, id_D1, slice1, id_FXB);
-                replace_port(ci, id_SD, slice1, id_M1);
-                replace_port(ci, id_Z, slice1, id_OFX1);
+                ci->movePortTo(id_D0, slice1, id_FXA);
+                ci->movePortTo(id_D1, slice1, id_FXB);
+                ci->movePortTo(id_SD, slice1, id_M1);
+                ci->movePortTo(id_Z, slice1, id_OFX1);
                 slice0->constr_z = 1;
                 slice0->constr_x = 0;
                 slice0->constr_y = 0;
@@ -676,10 +676,10 @@ class Ecp5Packer
                               slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
                               fxa_1->driver.port.c_str(ctx));
 
-                replace_port(ci, id_D0, slice2, id_FXA);
-                replace_port(ci, id_D1, slice2, id_FXB);
-                replace_port(ci, id_SD, slice2, id_M1);
-                replace_port(ci, id_Z, slice2, id_OFX1);
+                ci->movePortTo(id_D0, slice2, id_FXA);
+                ci->movePortTo(id_D1, slice2, id_FXB);
+                ci->movePortTo(id_SD, slice2, id_M1);
+                ci->movePortTo(id_Z, slice2, id_OFX1);
 
                 for (auto slice : {slice0, slice1, slice2, slice3}) {
                     slice->constr_children.clear();
@@ -747,12 +747,12 @@ class Ecp5Packer
                                               return user.port == chain_in.port && user.cell == chain_in.cell;
                                           }),
                            carry->users.end());
-        connect_port(ctx, carry, feedin.get(), id_A0);
+        feedin->connectPort(id_A0, carry);
 
         NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
-        connect_port(ctx, new_carry, feedin.get(), id_COUT);
+        feedin->connectPort(id_COUT, new_carry);
         chain_in.cell->ports[chain_in.port].net = nullptr;
-        connect_port(ctx, new_carry, chain_in.cell, chain_in.port);
+        chain_in.cell->connectPort(chain_in.port, new_carry);
 
         CellInfo *feedin_ptr = feedin.get();
         IdString feedin_name = feedin->name;
@@ -772,16 +772,16 @@ class Ecp5Packer
 
         PortRef carry_drv = carry->driver;
         carry->driver.cell = nullptr;
-        connect_port(ctx, carry, feedout.get(), id_S0);
+        feedout->connectPort(id_S0, carry);
 
         NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
         new_cin->driver = carry_drv;
         carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
-        connect_port(ctx, new_cin, feedout.get(), id_CIN);
+        feedout->connectPort(id_CIN, new_cin);
 
         if (chain_next) {
             // Loop back into LUT4_1 for feedthrough
-            connect_port(ctx, carry, feedout.get(), id_A1);
+            feedout->connectPort(id_A1, carry);
 
             carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
                                               [chain_next](const PortRef &user) {
@@ -790,10 +790,10 @@ class Ecp5Packer
                                carry->users.end());
 
             NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
-            connect_port(ctx, new_cout, feedout.get(), id_COUT);
+            feedout->connectPort(id_COUT, new_cout);
 
             chain_next->cell->ports[chain_next->port].net = nullptr;
-            connect_port(ctx, new_cout, chain_next->cell, chain_next->port);
+            chain_next->cell->connectPort(chain_next->port, new_cout);
         }
 
         CellInfo *feedout_ptr = feedout.get();
@@ -970,13 +970,13 @@ class Ecp5Packer
                 dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
 
                 // Disconnect ports of original cell after packing
-                disconnect_port(ctx, ci, id_WCK);
-                disconnect_port(ctx, ci, id_WRE);
+                ci->disconnectPort(id_WCK);
+                ci->disconnectPort(id_WRE);
 
-                disconnect_port(ctx, ci, ctx->id("RAD[0]"));
-                disconnect_port(ctx, ci, ctx->id("RAD[1]"));
-                disconnect_port(ctx, ci, ctx->id("RAD[2]"));
-                disconnect_port(ctx, ci, ctx->id("RAD[3]"));
+                ci->disconnectPort(ctx->id("RAD[0]"));
+                ci->disconnectPort(ctx->id("RAD[1]"));
+                ci->disconnectPort(ctx->id("RAD[2]"));
+                ci->disconnectPort(ctx->id("RAD[3]"));
 
                 // Attempt to pack FFs into RAM slices
                 std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
@@ -1159,7 +1159,7 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (is_ff(ctx, ci)) {
                 bool pack_dense = used_slices > (dense_pack_mode_thresh * available_slices);
-                bool requires_m = get_net_or_empty(ci, id_M) != nullptr;
+                bool requires_m = ci->getPort(id_M) != nullptr;
                 if (pack_dense && !requires_m) {
                     // If dense packing threshold exceeded; always try and pack the FF into an existing slice
                     // Find a SLICE with space "near" the flipflop in the netlist
@@ -1421,8 +1421,8 @@ class Ecp5Packer
         auto rename_bus = [&](CellInfo *c, const std::string &oldname, const std::string &newname, int width,
                               int oldoffset, int newoffset) {
             for (int i = 0; i < width; i++)
-                rename_port(ctx, c, ctx->id(oldname + std::to_string(i + oldoffset)),
-                            ctx->id(newname + std::to_string(i + newoffset)));
+                c->renamePort(ctx->id(oldname + std::to_string(i + oldoffset)),
+                              ctx->id(newname + std::to_string(i + newoffset)));
         };
         auto rename_param = [&](CellInfo *c, const std::string &oldname, const std::string &newname) {
             IdString o = ctx->id(oldname), n = ctx->id(newname);
@@ -1446,11 +1446,11 @@ class Ecp5Packer
                 rename_bus(ci, "DI", "DIB", 18, 18, 0);
                 rename_bus(ci, "DO", "DOA", 18, 18, 0);
                 rename_bus(ci, "DO", "DOB", 18, 0, 0);
-                rename_port(ctx, ci, id_CLKW, id_CLKA);
-                rename_port(ctx, ci, id_CLKR, id_CLKB);
-                rename_port(ctx, ci, id_CEW, id_CEA);
-                rename_port(ctx, ci, id_CER, id_CEB);
-                rename_port(ctx, ci, id_OCER, id_OCEB);
+                ci->renamePort(id_CLKW, id_CLKA);
+                ci->renamePort(id_CLKR, id_CLKB);
+                ci->renamePort(id_CEW, id_CEA);
+                ci->renamePort(id_CER, id_CEB);
+                ci->renamePort(id_OCER, id_OCEB);
                 rename_param(ci, "CLKWMUX", "CLKAMUX");
                 if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
                     ci->params[id_CLKAMUX] = std::string("CLKA");
@@ -1468,9 +1468,9 @@ class Ecp5Packer
                     autocreate_empty_port(ci, id_RSTA);
                     autocreate_empty_port(ci, id_RSTB);
                     NetInfo *rst = ci->ports.at(id_RST).net;
-                    connect_port(ctx, rst, ci, id_RSTA);
-                    connect_port(ctx, rst, ci, id_RSTB);
-                    disconnect_port(ctx, ci, id_RST);
+                    ci->connectPort(id_RSTA, rst);
+                    ci->connectPort(id_RSTB, rst);
+                    ci->disconnectPort(id_RST);
                     ci->ports.erase(id_RST);
                 }
                 ci->type = id_DP16KD;
@@ -1721,12 +1721,12 @@ class Ecp5Packer
                 // Disconnect these ports if connected to constant to prevent routing failure
                 for (auto ndport : {id_D_TXBIT_CLKP_FROM_ND, id_D_TXBIT_CLKN_FROM_ND, id_D_SYNC_ND,
                                     id_D_TXPLL_LOL_FROM_ND, id_CH0_HDINN, id_CH0_HDINP, id_CH1_HDINN, id_CH1_HDINP}) {
-                    const NetInfo *net = get_net_or_empty(ci, ndport);
+                    const NetInfo *net = ci->getPort(ndport);
                     if (net == nullptr || net->driver.cell == nullptr)
                         continue;
                     IdString ct = net->driver.cell->type;
                     if (ct == id_GND || ct == id_VCC) {
-                        disconnect_port(ctx, ci, ndport);
+                        ci->disconnectPort(ndport);
                         ci->ports.erase(ndport);
                     }
                 }
@@ -1814,9 +1814,9 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_USRMCLK) {
-                rename_port(ctx, ci, id_USRMCLKI, id_PADDO);
-                rename_port(ctx, ci, id_USRMCLKTS, id_PADDT);
-                rename_port(ctx, ci, id_USRMCLKO, id_PADDI);
+                ci->renamePort(id_USRMCLKI, id_PADDO);
+                ci->renamePort(id_USRMCLKTS, id_PADDT);
+                ci->renamePort(id_USRMCLKO, id_PADDI);
             } else if (ci->type == id_GSR || ci->type == id_SGSR) {
                 ci->params[id_MODE] = std::string("ACTIVE_LOW");
                 ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC");
@@ -1959,8 +1959,8 @@ class Ecp5Packer
 
                 eclkbuf->attrs[id_BEL] = ctx->getBelName(target_bel).str(ctx);
 
-                connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
-                connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
+                eclkbuf->connectPort(id_ECLKI, ecknet);
+                eclkbuf->connectPort(id_ECLKO, eclk.buf);
                 found_eclk = free_eclk;
                 eclk.buffer = eclkbuf.get();
                 new_cells.push_back(std::move(eclkbuf));
@@ -1968,9 +1968,9 @@ class Ecp5Packer
         }
 
         auto &eclk = eclks[std::make_pair(bank, found_eclk)];
-        disconnect_port(ctx, usr_cell, usr_port.name);
+        usr_cell->disconnectPort(usr_port.name);
         usr_port.net = nullptr;
-        connect_port(ctx, eclk.buf, usr_cell, usr_port.name);
+        usr_cell->connectPort(usr_port.name, eclk.buf);
 
         // Simple ECLK router
         WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name);
@@ -2024,8 +2024,8 @@ class Ecp5Packer
         auto zero_cell = std::make_unique<CellInfo>(ctx, name, id_GND);
         NetInfo *zero_net = ctx->createNet(name);
         zero_cell->addOutput(id_GND);
-        connect_port(ctx, zero_net, zero_cell.get(), id_GND);
-        connect_port(ctx, zero_net, ci, port);
+        zero_cell->connectPort(id_GND, zero_net);
+        ci->connectPort(port, zero_net);
         new_cells.push_back(std::move(zero_cell));
     }
 
@@ -2136,11 +2136,11 @@ class Ecp5Packer
                         log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx),
                                   iol->ports[id_CLK].net->name.c_str(ctx), sclk->name.c_str(ctx));
                 } else {
-                    connect_port(ctx, sclk, iol, id_CLK);
+                    iol->connectPort(id_CLK, sclk);
                 }
             }
             if (prim->ports.count(port) && disconnect)
-                disconnect_port(ctx, prim, port);
+                prim->disconnectPort(port);
         };
 
         auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) {
@@ -2155,10 +2155,10 @@ class Ecp5Packer
                     log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx),
                               iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx));
             } else {
-                connect_port(ctx, eclk, iol, id_ECLK);
+                iol->connectPort(id_ECLK, eclk);
             }
             if (prim->ports.count(port))
-                disconnect_port(ctx, prim, port);
+                prim->disconnectPort(port);
         };
 
         auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
@@ -2174,11 +2174,11 @@ class Ecp5Packer
                         log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
                                   iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx));
                 } else if (iol->ports[id_LSR].net == nullptr) {
-                    connect_port(ctx, lsr, iol, id_LSR);
+                    iol->connectPort(id_LSR, lsr);
                 }
             }
             if (prim->ports.count(port) && disconnect)
-                disconnect_port(ctx, prim, port);
+                prim->disconnectPort(port);
         };
 
         bool warned_oddrx_iddrx = false;
@@ -2245,7 +2245,7 @@ class Ecp5Packer
                     log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx),
                               port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx));
                 }
-                disconnect_port(ctx, prim, port);
+                prim->disconnectPort(port);
             } else {
                 bool dqsr;
                 int dqsgroup;
@@ -2263,7 +2263,7 @@ class Ecp5Packer
                               "%cDQ%d\n",
                               port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup,
                               sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second);
-                replace_port(prim, port, iol, port);
+                prim->movePortTo(port, iol, port);
             }
         };
 
@@ -2284,18 +2284,18 @@ class Ecp5Packer
                     if (drives_iologic) {
                         // Reconnect to PIO which the packer expects later on
                         NetInfo *input_net = ci->ports.at(id_A).net, *dly_net = ci->ports.at(id_Z).net;
-                        disconnect_port(ctx, i_pio, id_O);
+                        i_pio->disconnectPort(id_O);
                         i_pio->ports.at(id_O).net = nullptr;
-                        disconnect_port(ctx, ci, id_A);
+                        ci->disconnectPort(id_A);
                         ci->ports.at(id_A).net = nullptr;
-                        disconnect_port(ctx, ci, id_Z);
+                        ci->disconnectPort(id_Z);
                         ci->ports.at(id_Z).net = nullptr;
-                        connect_port(ctx, dly_net, i_pio, id_O);
-                        connect_port(ctx, input_net, iol, id_INDD);
-                        connect_port(ctx, input_net, iol, id_DI);
+                        i_pio->connectPort(id_O, dly_net);
+                        iol->connectPort(id_INDD, input_net);
+                        iol->connectPort(id_DI, input_net);
                     } else {
-                        replace_port(ci, id_A, iol, id_PADDI);
-                        replace_port(ci, id_Z, iol, id_INDD);
+                        ci->movePortTo(id_A, iol, id_PADDI);
+                        ci->movePortTo(id_Z, iol, id_INDD);
                     }
                     packed_cells.insert(cell.first);
                 } else if (o_pio != nullptr) {
@@ -2307,22 +2307,22 @@ class Ecp5Packer
                         input_net->driver.port == id_Q)
                         driven_by_iol = true;
                     if (driven_by_iol) {
-                        disconnect_port(ctx, o_pio, id_I);
+                        o_pio->disconnectPort(id_I);
                         o_pio->ports.at(id_I).net = nullptr;
-                        disconnect_port(ctx, ci, id_A);
+                        ci->disconnectPort(id_A);
                         ci->ports.at(id_A).net = nullptr;
-                        disconnect_port(ctx, ci, id_Z);
+                        ci->disconnectPort(id_Z);
                         ci->ports.at(id_Z).net = nullptr;
-                        connect_port(ctx, input_net, o_pio, id_I);
+                        o_pio->connectPort(id_I, input_net);
                         ctx->nets.erase(dly_net->name);
                     } else {
-                        replace_port(ci, id_A, iol, id_TXDATA0);
-                        replace_port(ci, id_Z, iol, id_IOLDO);
+                        ci->movePortTo(id_A, iol, id_TXDATA0);
+                        ci->movePortTo(id_Z, iol, id_IOLDO);
                         if (!o_pio->ports.count(id_IOLDO)) {
                             o_pio->ports[id_IOLDO].name = id_IOLDO;
                             o_pio->ports[id_IOLDO].type = PORT_IN;
                         }
-                        replace_port(o_pio, id_I, o_pio, id_IOLDO);
+                        o_pio->movePortTo(id_I, o_pio, id_IOLDO);
                     }
                     packed_cells.insert(cell.first);
                 } else {
@@ -2336,19 +2336,19 @@ class Ecp5Packer
                      std::string(ci->params.at(id_DEL_VALUE).as_string()).substr(0, 5) != "DELAY"))
                     iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(id_DEL_VALUE);
                 if (ci->ports.count(id_LOADN))
-                    replace_port(ci, id_LOADN, iol, id_LOADN);
+                    ci->movePortTo(id_LOADN, iol, id_LOADN);
                 else
                     tie_zero(iol, id_LOADN);
                 if (ci->ports.count(id_MOVE))
-                    replace_port(ci, id_MOVE, iol, id_MOVE);
+                    ci->movePortTo(id_MOVE, iol, id_MOVE);
                 else
                     tie_zero(iol, id_MOVE);
                 if (ci->ports.count(id_DIRECTION))
-                    replace_port(ci, id_DIRECTION, iol, id_DIRECTION);
+                    ci->movePortTo(id_DIRECTION, iol, id_DIRECTION);
                 else
                     tie_zero(iol, id_DIRECTION);
                 if (ci->ports.count(id_CFLAG))
-                    replace_port(ci, id_CFLAG, iol, id_CFLAG);
+                    ci->movePortTo(id_CFLAG, iol, id_CFLAG);
             }
         }
 
@@ -2365,11 +2365,11 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRX1_ODDRX1");
-                replace_port(ci, id_D, iol, id_PADDI);
+                ci->movePortTo(id_D, iol, id_PADDI);
                 set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_Q0, iol, id_RXDATA0);
-                replace_port(ci, id_Q1, iol, id_RXDATA1);
+                ci->movePortTo(id_Q0, iol, id_RXDATA0);
+                ci->movePortTo(id_Q1, iol, id_RXDATA1);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
             } else if (ci->type == id_ODDRX1F) {
@@ -2383,17 +2383,17 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRX1_ODDRX1");
-                replace_port(ci, id_Q, iol, id_IOLDO);
+                ci->movePortTo(id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
-                replace_port(pio, id_I, pio, id_IOLDO);
+                pio->movePortTo(id_I, pio, id_IOLDO);
                 pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
                 set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_lsr(iol, ci, id_RST, false);
-                replace_port(ci, id_D0, iol, id_TXDATA0);
-                replace_port(ci, id_D1, iol, id_TXDATA1);
+                ci->movePortTo(id_D0, iol, id_TXDATA0);
+                ci->movePortTo(id_D1, iol, id_TXDATA1);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
             } else if (ci->type == id_ODDRX2F || ci->type == id_ODDR71B) {
@@ -2407,28 +2407,28 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "ODDRXN");
-                replace_port(ci, id_Q, iol, id_IOLDO);
+                ci->movePortTo(id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
-                replace_port(pio, id_I, pio, id_IOLDO);
+                pio->movePortTo(id_I, pio, id_IOLDO);
                 set_iologic_sclk(iol, ci, id_SCLK, false, false);
                 set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, false, false);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_D0, iol, id_TXDATA0);
-                replace_port(ci, id_D1, iol, id_TXDATA1);
-                replace_port(ci, id_D2, iol, id_TXDATA2);
-                replace_port(ci, id_D3, iol, id_TXDATA3);
+                ci->movePortTo(id_D0, iol, id_TXDATA0);
+                ci->movePortTo(id_D1, iol, id_TXDATA1);
+                ci->movePortTo(id_D2, iol, id_TXDATA2);
+                ci->movePortTo(id_D3, iol, id_TXDATA3);
                 if (ci->type == id_ODDR71B) {
                     Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
                     if (loc.z % 2 == 1)
                         log_error("ODDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
-                    replace_port(ci, id_D4, iol, id_TXDATA4);
-                    replace_port(ci, id_D5, iol, id_TXDATA5);
-                    replace_port(ci, id_D6, iol, id_TXDATA6);
+                    ci->movePortTo(id_D4, iol, id_TXDATA4);
+                    ci->movePortTo(id_D5, iol, id_TXDATA5);
+                    ci->movePortTo(id_D6, iol, id_TXDATA6);
                     iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDR71");
                 } else {
                     iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDRX2");
@@ -2447,22 +2447,22 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "IDDRXN");
-                replace_port(ci, id_D, iol, id_PADDI);
+                ci->movePortTo(id_D, iol, id_PADDI);
                 set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_Q0, iol, id_RXDATA0);
-                replace_port(ci, id_Q1, iol, id_RXDATA1);
-                replace_port(ci, id_Q2, iol, id_RXDATA2);
-                replace_port(ci, id_Q3, iol, id_RXDATA3);
+                ci->movePortTo(id_Q0, iol, id_RXDATA0);
+                ci->movePortTo(id_Q1, iol, id_RXDATA1);
+                ci->movePortTo(id_Q2, iol, id_RXDATA2);
+                ci->movePortTo(id_Q3, iol, id_RXDATA3);
                 if (ci->type == id_IDDR71B) {
                     Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
                     if (loc.z % 2 == 1)
                         log_error("IDDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
-                    replace_port(ci, id_Q4, iol, id_RXDATA4);
-                    replace_port(ci, id_Q5, iol, id_RXDATA5);
-                    replace_port(ci, id_Q6, iol, id_RXDATA6);
-                    replace_port(ci, id_ALIGNWD, iol, id_SLIP);
+                    ci->movePortTo(id_Q4, iol, id_RXDATA4);
+                    ci->movePortTo(id_Q5, iol, id_RXDATA5);
+                    ci->movePortTo(id_Q6, iol, id_RXDATA6);
+                    ci->movePortTo(id_ALIGNWD, iol, id_SLIP);
                     iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDR71");
                 } else {
                     iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDRX2");
@@ -2480,18 +2480,18 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, id_Q, iol, id_IOLDO);
+                ci->movePortTo(id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
-                replace_port(pio, id_I, pio, id_IOLDO);
+                pio->movePortTo(id_I, pio, id_IOLDO);
                 set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, false, false);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_D0, iol, id_TXDATA0);
-                replace_port(ci, id_D1, iol, id_TXDATA2);
+                ci->movePortTo(id_D0, iol, id_TXDATA0);
+                ci->movePortTo(id_D1, iol, id_TXDATA2);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2");
                 pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
@@ -2507,20 +2507,20 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, id_Q, iol, id_IOLDO);
+                ci->movePortTo(id_Q, iol, id_IOLDO);
                 if (!pio->ports.count(id_IOLDO)) {
                     pio->ports[id_IOLDO].name = id_IOLDO;
                     pio->ports[id_IOLDO].type = PORT_IN;
                 }
-                replace_port(pio, id_I, pio, id_IOLDO);
+                pio->movePortTo(id_I, pio, id_IOLDO);
                 set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, false, false);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_D0, iol, id_TXDATA0);
-                replace_port(ci, id_D1, iol, id_TXDATA1);
-                replace_port(ci, id_D2, iol, id_TXDATA2);
-                replace_port(ci, id_D3, iol, id_TXDATA3);
+                ci->movePortTo(id_D0, iol, id_TXDATA0);
+                ci->movePortTo(id_D1, iol, id_TXDATA1);
+                ci->movePortTo(id_D2, iol, id_TXDATA2);
+                ci->movePortTo(id_D3, iol, id_TXDATA3);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MODDRX.MODE")] = std::string("MODDRX2");
                 iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
@@ -2539,15 +2539,15 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, id_D, iol, id_PADDI);
+                ci->movePortTo(id_D, iol, id_PADDI);
                 set_iologic_sclk(iol, ci, id_SCLK, true);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, true);
-                replace_port(ci, id_Q0, iol, id_RXDATA0);
-                replace_port(ci, id_Q1, iol, id_RXDATA1);
-                replace_port(ci, id_Q2, iol, id_RXDATA2);
-                replace_port(ci, id_Q3, iol, id_RXDATA3);
-                replace_port(ci, id_QWL, iol, id_INFF);
+                ci->movePortTo(id_Q0, iol, id_RXDATA0);
+                ci->movePortTo(id_Q1, iol, id_RXDATA1);
+                ci->movePortTo(id_Q2, iol, id_RXDATA2);
+                ci->movePortTo(id_Q3, iol, id_RXDATA3);
+                ci->movePortTo(id_QWL, iol, id_INFF);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MIDDRX.MODE")] = std::string("MIDDRX2");
                 process_dqs_port(ci, pio, iol, id_DQSR90);
@@ -2569,17 +2569,17 @@ class Ecp5Packer
                 else
                     iol = create_pio_iologic(pio, ci);
                 set_iologic_mode(iol, "MIDDRX_MODDRX");
-                replace_port(ci, id_Q, iol, id_IOLTO);
+                ci->movePortTo(id_Q, iol, id_IOLTO);
                 if (!pio->ports.count(id_IOLTO)) {
                     pio->ports[id_IOLTO].name = id_IOLTO;
                     pio->ports[id_IOLTO].type = PORT_IN;
                 }
-                replace_port(pio, id_T, pio, id_IOLTO);
+                pio->movePortTo(id_T, pio, id_IOLTO);
                 set_iologic_sclk(iol, ci, id_SCLK, false);
                 set_iologic_eclk(iol, ci, id_ECLK);
                 set_iologic_lsr(iol, ci, id_RST, false);
-                replace_port(ci, id_T0, iol, id_TSDATA0);
-                replace_port(ci, id_T1, iol, id_TSDATA1);
+                ci->movePortTo(id_T0, iol, id_TSDATA0);
+                ci->movePortTo(id_T1, iol, id_TSDATA1);
                 process_dqs_port(ci, pio, iol, ci->type == id_TSHX2DQSA ? id_DQSW : id_DQSW270);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 iol->params[ctx->id("MTDDRX.MODE")] = std::string("MTSHX2");
@@ -2595,7 +2595,7 @@ class Ecp5Packer
                 std::string mode = str_or_default(ci->attrs, id_ioff_dir, "");
                 if (mode != "output") {
                     // See if it can be packed as an input ff
-                    NetInfo *d = get_net_or_empty(ci, id_DI);
+                    NetInfo *d = ci->getPort(id_DI);
                     CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
                     if (pio != nullptr && d->users.size() == 1) {
                         // Input FF
@@ -2613,10 +2613,10 @@ class Ecp5Packer
                         if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
                             iol->params[id_CEIMUX] = std::string("CEMUX");
                             iol->params[id_CEMUX] = std::string("CE");
-                            if (get_net_or_empty(ci, id_CE) == nullptr)
-                                replace_port(ci, id_CE, iol, id_CE);
+                            if (ci->getPort(id_CE) == nullptr)
+                                ci->movePortTo(id_CE, iol, id_CE);
                             else
-                                disconnect_port(ctx, ci, id_CE);
+                                ci->disconnectPort(id_CE);
                         } else {
                             iol->params[id_CEIMUX] = std::string("1");
                         }
@@ -2625,8 +2625,8 @@ class Ecp5Packer
                         iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, id_REGSET, "RESET");
                         iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
                         iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
-                        replace_port(ci, id_DI, iol, id_PADDI);
-                        replace_port(ci, id_Q, iol, id_INFF);
+                        ci->movePortTo(id_DI, iol, id_PADDI);
+                        ci->movePortTo(id_Q, iol, id_INFF);
                         packed_cells.insert(cell.first);
                         continue;
                     }
@@ -2645,21 +2645,21 @@ class Ecp5Packer
                             iol = create_pio_iologic(pio, ci);
                         set_iologic_mode(iol, "IREG_OREG");
                         // Connection between FF and PIO
-                        replace_port(ci, id_Q, iol, tri ? id_IOLTO : id_IOLDO);
+                        ci->movePortTo(id_Q, iol, tri ? id_IOLTO : id_IOLDO);
                         if (tri) {
                             if (!pio->ports.count(id_IOLTO)) {
                                 pio->ports[id_IOLTO].name = id_IOLTO;
                                 pio->ports[id_IOLTO].type = PORT_IN;
                             }
                             pio->params[id_TRIMUX_TSREG] = std::string("IOLTO");
-                            replace_port(pio, id_T, pio, id_IOLTO);
+                            pio->movePortTo(id_T, pio, id_IOLTO);
                         } else {
                             if (!pio->ports.count(id_IOLDO)) {
                                 pio->ports[id_IOLDO].name = id_IOLDO;
                                 pio->ports[id_IOLDO].type = PORT_IN;
                             }
                             pio->params[id_DATAMUX_OREG] = std::string("IOLDO");
-                            replace_port(pio, id_I, pio, id_IOLDO);
+                            pio->movePortTo(id_I, pio, id_IOLDO);
                         }
 
                         set_iologic_sclk(iol, ci, id_CLK, false);
@@ -2671,10 +2671,10 @@ class Ecp5Packer
                         if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
                             iol->params[id_CEOMUX] = std::string("CEMUX");
                             iol->params[id_CEMUX] = std::string("CE");
-                            if (get_net_or_empty(ci, id_CE) == nullptr)
-                                replace_port(ci, id_CE, iol, id_CE);
+                            if (ci->getPort(id_CE) == nullptr)
+                                ci->movePortTo(id_CE, iol, id_CE);
                             else
-                                disconnect_port(ctx, ci, id_CE);
+                                ci->disconnectPort(id_CE);
                         } else {
                             iol->params[id_CEOMUX] = std::string("1");
                         }
@@ -2684,7 +2684,7 @@ class Ecp5Packer
                                 str_or_default(ci->params, id_REGSET, "RESET");
                         iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
                         // Data input
-                        replace_port(ci, id_DI, iol, tri ? id_TSDATA0 : id_TXDATA0);
+                        ci->movePortTo(id_DI, iol, tri ? id_TSDATA0 : id_TXDATA0);
                         iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                         packed_cells.insert(cell.first);
                         continue;
@@ -2699,8 +2699,7 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (ci->type == id_ECLKBRIDGECS) {
                 Loc loc;
-                NetInfo *i0 = get_net_or_empty(ci, id_CLK0), *i1 = get_net_or_empty(ci, id_CLK1),
-                        *o = get_net_or_empty(ci, id_ECSOUT);
+                NetInfo *i0 = ci->getPort(id_CLK0), *i1 = ci->getPort(id_CLK1), *o = ci->getPort(id_ECSOUT);
                 for (NetInfo *input : {i0, i1}) {
                     if (input == nullptr)
                         continue;
@@ -2753,7 +2752,7 @@ class Ecp5Packer
                     for (auto user2 : o->users) {
                         // Set side hint to ensure edge clock choice is routeable
                         if (user2.cell->type == id_ECLKSYNCB && user2.port == id_ECLKI) {
-                            NetInfo *synco = get_net_or_empty(user2.cell, id_ECLKO);
+                            NetInfo *synco = user2.cell->getPort(id_ECLKO);
                             if (synco != nullptr)
                                 bridge_side_hint[synco] = (loc.x > 1) ? 0 : 1;
                         }
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc
index b003812ead..31e0522bf9 100644
--- a/fpga_interchange/arch_pack_clusters.cc
+++ b/fpga_interchange/arch_pack_clusters.cc
@@ -901,7 +901,7 @@ void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index)
             // reachable due to the fixed dedicated interconnect.
             // E.g.: The CI input of carry chains in 7series corresponds to the CIN bel port,
             //       which can only be connected to the COUT output of the tile below.
-            disconnect_port(ctx, ci, sink_port);
+            ci->disconnectPort(sink_port);
         }
     }
 
diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc
index aa7d318405..8f7f823162 100644
--- a/fpga_interchange/macros.cc
+++ b/fpga_interchange/macros.cc
@@ -99,9 +99,9 @@ void Arch::expand_macros()
                     // TODO: case of multiple top level ports on the same net?
                     NPNR_ASSERT(net == nullptr);
                     // Use the corresponding pre-expansion port net
-                    net = get_net_or_empty(cell, IdString(net_port.port));
+                    net = cell->getPort(IdString(net_port.port));
                     // Disconnect the original port pre-expansion
-                    disconnect_port(ctx, cell, IdString(net_port.port));
+                    cell->disconnectPort(IdString(net_port.port));
                 }
                 // If not on a top level port, create a new net
                 if (net == nullptr)
@@ -115,7 +115,7 @@ void Arch::expand_macros()
                             ctx->cells.at(derived_name(ctx, cell->name, IdString(net_port.instance))).get();
                     inst_cell->ports[port_name].name = port_name;
                     inst_cell->ports[port_name].type = PortType(net_port.dir);
-                    connect_port(ctx, net, inst_cell, port_name);
+                    inst_cell->connectPort(port_name, net);
                 }
             }
 
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index 08e950e21c..4e3d460a26 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -953,7 +953,7 @@ static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetI
         new_cell->belStrength = STRENGTH_PLACER;
         ctx->tileStatus.at(inverting_bel.tile).boundcells[inverting_bel.index] = new_cell;
 
-        connect_port(ctx, net_before_inverter, new_cell, id_I);
+        new_cell->connectPort(id_I, net_before_inverter);
 
         // The original BEL pin is now routed, but only through the inverter.
         // Because the cell/net model doesn't allow for multiple source pins
diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index ed9354b63f..8ac61bbea6 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -484,7 +484,7 @@ template <typename FrontendType> struct GenericFrontend
                     log_error("Net '%s' is multiply driven by cell ports %s.%s and %s.%s\n", ctx->nameOf(net),
                               ctx->nameOf(net->driver.cell), ctx->nameOf(net->driver.port), ctx->nameOf(inst_name),
                               port_bit_name.c_str());
-                connect_port(ctx, net, ci, port_bit_ids);
+                ci->connectPort(port_bit_ids, net);
             }
         });
         // Import attributes and parameters
@@ -578,12 +578,12 @@ template <typename FrontendType> struct GenericFrontend
             }
             NPNR_ASSERT(net->driver.cell == nullptr);
             // Connect IBUF output and net
-            connect_port(ctx, net, iobuf, ctx->id("O"));
+            iobuf->connectPort(ctx->id("O"), net);
         } else if (dir == PORT_OUT) {
             iobuf->type = ctx->id("$nextpnr_obuf");
             iobuf->addInput(ctx->id("I"));
             // Connect IBUF input and net
-            connect_port(ctx, net, iobuf, ctx->id("I"));
+            iobuf->connectPort(ctx->id("I"), net);
         } else if (dir == PORT_INOUT) {
             iobuf->type = ctx->id("$nextpnr_iobuf");
 
@@ -597,16 +597,16 @@ template <typename FrontendType> struct GenericFrontend
                 NetInfo *split_iobuf_i = ctx->createNet(unique_name("", "$" + name + "$iobuf_i", true));
                 auto drv = net->driver;
                 if (drv.cell != nullptr) {
-                    disconnect_port(ctx, drv.cell, drv.port);
+                    drv.cell->disconnectPort(drv.port);
                     drv.cell->ports[drv.port].net = nullptr;
-                    connect_port(ctx, split_iobuf_i, drv.cell, drv.port);
+                    drv.cell->connectPort(drv.port, split_iobuf_i);
                 }
-                connect_port(ctx, split_iobuf_i, iobuf, ctx->id("I"));
+                iobuf->connectPort(ctx->id("I"), split_iobuf_i);
                 NPNR_ASSERT(net->driver.cell == nullptr);
-                connect_port(ctx, net, iobuf, ctx->id("O"));
+                iobuf->connectPort(ctx->id("O"), net);
             } else {
                 iobuf->addInout(ctx->id("IO"));
-                connect_port(ctx, net, iobuf, ctx->id("IO"));
+                iobuf->connectPort(ctx->id("IO"), net);
             }
         }
 
@@ -669,7 +669,7 @@ template <typename FrontendType> struct GenericFrontend
         if (net->driver.cell != nullptr)
             log_error("Net '%s' is multiply driven by port %s.%s and constant '%c'\n", ctx->nameOf(net),
                       ctx->nameOf(net->driver.cell), ctx->nameOf(net->driver.port), constval);
-        connect_port(ctx, net, cc, ctx->id("Y"));
+        cc->connectPort(ctx->id("Y"), net);
     }
 
     // Merge two nets - e.g. if one net in a submodule bifurcates to two output bits and therefore two different
diff --git a/generic/arch.cc b/generic/arch.cc
index ad054efd6d..c4814bab0b 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -721,7 +721,7 @@ void Arch::assignArchInfo()
         CellInfo *ci = cell.second.get();
         if (ci->type == id("GENERIC_SLICE")) {
             ci->is_slice = true;
-            ci->slice_clk = get_net_or_empty(ci, id("CLK"));
+            ci->slice_clk = ci->getPort(id("CLK"));
         } else {
             ci->is_slice = false;
         }
diff --git a/generic/cells.cc b/generic/cells.cc
index c14ddf7306..76d6474f70 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -66,19 +66,19 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 
     for (int i = 0; i < lut_k; i++) {
         IdString port = ctx->id("I[" + std::to_string(i) + "]");
-        replace_port(lut, port, lc, port);
+        lut->movePortTo(port, lc, port);
     }
 
     if (no_dff) {
         lc->params[ctx->id("FF_USED")] = 0;
-        replace_port(lut, ctx->id("Q"), lc, ctx->id("F"));
+        lut->movePortTo(ctx->id("Q"), lc, ctx->id("F"));
     }
 }
 
 void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 {
     lc->params[ctx->id("FF_USED")] = 1;
-    replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
+    dff->movePortTo(ctx->id("CLK"), lc, ctx->id("CLK"));
 
     if (pass_thru_lut) {
         // Fill LUT with alternating 10
@@ -89,26 +89,26 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
             init.append("10");
         lc->params[ctx->id("INIT")] = Property::from_string(init);
 
-        replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
+        dff->movePortTo(ctx->id("D"), lc, ctx->id("I[0]"));
     }
 
-    replace_port(dff, ctx->id("Q"), lc, ctx->id("Q"));
+    dff->movePortTo(ctx->id("Q"), lc, ctx->id("Q"));
 }
 
 void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
         iob->params[ctx->id("INPUT_USED")] = 1;
-        replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
+        nxio->movePortTo(ctx->id("O"), iob, ctx->id("O"));
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
         iob->params[ctx->id("OUTPUT_USED")] = 1;
-        replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
+        nxio->movePortTo(ctx->id("I"), iob, ctx->id("I"));
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
         iob->params[ctx->id("INPUT_USED")] = 1;
         iob->params[ctx->id("OUTPUT_USED")] = 1;
-        replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
-        replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
+        nxio->movePortTo(ctx->id("I"), iob, ctx->id("I"));
+        nxio->movePortTo(ctx->id("O"), iob, ctx->id("O"));
     } else {
         NPNR_ASSERT(false);
     }
@@ -118,8 +118,8 @@ void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
             ctx->id("Y"));
     if (tbuf) {
         iob->params[ctx->id("ENABLE_USED")] = 1;
-        replace_port(tbuf, ctx->id("A"), iob, ctx->id("I"));
-        replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN"));
+        tbuf->movePortTo(ctx->id("A"), iob, ctx->id("I"));
+        tbuf->movePortTo(ctx->id("E"), iob, ctx->id("EN"));
 
         if (donet->users.size() > 1) {
             for (auto user : donet->users)
diff --git a/generic/pack.cc b/generic/pack.cc
index 8bdbbed07c..cb3f58974b 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -242,7 +242,7 @@ static void pack_io(Context *ctx)
             } else if (bool_or_default(ctx->settings, ctx->id("disable_iobs"))) {
                 // No IO buffer insertion; just remove nextpnr_[io]buf
                 for (auto &p : ci->ports)
-                    disconnect_port(ctx, ci, p.first);
+                    ci->disconnectPort(p.first);
             } else {
                 // Create a GENERIC_IOB buffer
                 std::unique_ptr<CellInfo> ice_cell =
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
index 3d1c201cbf..49b3679269 100644
--- a/generic/viaduct/example/example.cc
+++ b/generic/viaduct/example/example.cc
@@ -253,10 +253,10 @@ struct ExampleImpl : ViaductAPI
             CellInfo *ci = cell.second.get();
             auto &fc = fast_cell_info.at(ci->flat_index);
             if (ci->type == id_LUT4) {
-                fc.lut_f = get_net_or_empty(ci, id_F);
-                fc.lut_i3_used = (get_net_or_empty(ci, ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+                fc.lut_f = ci->getPort(id_F);
+                fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr);
             } else if (ci->type == id_DFF) {
-                fc.ff_d = get_net_or_empty(ci, id_D);
+                fc.ff_d = ci->getPort(id_D);
             }
         }
     }
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index e9f7fa60e6..10c3b8020a 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -59,13 +59,13 @@ void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
         auto &ci = *cell.second;
         if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
             continue;
-        NetInfo *i = get_net_or_empty(&ci, ctx->id("I"));
+        NetInfo *i = ci.getPort(ctx->id("I"));
         if (i && i->driver.cell) {
             if (!top_ports.count(CellTypePort(i->driver)))
                 log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
                           ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
         }
-        NetInfo *o = get_net_or_empty(&ci, ctx->id("O"));
+        NetInfo *o = ci.getPort(ctx->id("O"));
         if (o) {
             for (auto &usr : o->users) {
                 if (!top_ports.count(CellTypePort(usr)))
@@ -73,8 +73,8 @@ void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
                               ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
             }
         }
-        disconnect_port(ctx, &ci, ctx->id("I"));
-        disconnect_port(ctx, &ci, ctx->id("O"));
+        ci.disconnectPort(ctx->id("I"));
+        ci.disconnectPort(ctx->id("O"));
         to_remove.push_back(ci.name);
     }
     for (IdString cell_name : to_remove)
diff --git a/gowin/arch.cc b/gowin/arch.cc
index b104013dbc..af85146799 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1600,9 +1600,9 @@ void Arch::assignArchInfo()
             ci->is_slice = true;
             ci->ff_used = ci->params.at(id_FF_USED).as_bool();
             ci->ff_type = id(ci->params.at(id_FF_TYPE).as_string());
-            ci->slice_clk = get_net_or_empty(ci, id_CLK);
-            ci->slice_ce = get_net_or_empty(ci, id_CE);
-            ci->slice_lsr = get_net_or_empty(ci, id_LSR);
+            ci->slice_clk = ci->getPort(id_CLK);
+            ci->slice_ce = ci->getPort(id_CE);
+            ci->slice_lsr = ci->getPort(id_LSR);
 
             // add timing paths
             addCellTimingClock(cname, id_CLK);
diff --git a/gowin/cells.cc b/gowin/cells.cc
index aef34f535a..d862458c33 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -93,12 +93,12 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
     IdString sim_names[4] = {id_I0, id_I1, id_I2, id_I3};
     IdString wire_names[4] = {id_A, id_B, id_C, id_D};
     for (int i = 0; i < 4; i++) {
-        replace_port(lut, sim_names[i], lc, wire_names[i]);
+        lut->movePortTo(sim_names[i], lc, wire_names[i]);
     }
 
     if (no_dff) {
         lc->params[id_FF_USED] = 0;
-        replace_port(lut, id_F, lc, id_F);
+        lut->movePortTo(id_F, lc, id_F);
     }
 }
 
@@ -106,12 +106,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 {
     lc->params[id_FF_USED] = 1;
     lc->params[id_FF_TYPE] = dff->type.str(ctx);
-    replace_port(dff, id_CLK, lc, id_CLK);
-    replace_port(dff, id_CE, lc, id_CE);
-    replace_port(dff, id_SET, lc, id_LSR);
-    replace_port(dff, id_RESET, lc, id_LSR);
-    replace_port(dff, id_CLEAR, lc, id_LSR);
-    replace_port(dff, id_PRESET, lc, id_LSR);
+    dff->movePortTo(id_CLK, lc, id_CLK);
+    dff->movePortTo(id_CE, lc, id_CE);
+    dff->movePortTo(id_SET, lc, id_LSR);
+    dff->movePortTo(id_RESET, lc, id_LSR);
+    dff->movePortTo(id_CLEAR, lc, id_LSR);
+    dff->movePortTo(id_PRESET, lc, id_LSR);
     if (pass_thru_lut) {
         // Fill LUT with alternating 10
         const int init_size = 1 << 4;
@@ -121,10 +121,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
             init.append("10");
         lc->params[id_INIT] = Property::from_string(init);
 
-        replace_port(dff, id_D, lc, id_A);
+        dff->movePortTo(id_D, lc, id_A);
     }
 
-    replace_port(dff, id_Q, lc, id_Q);
+    dff->movePortTo(id_Q, lc, id_Q);
 }
 
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells)
@@ -132,29 +132,29 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
     if (nxio->type == id_IBUF) {
         if (iob->type == id_IOBS) {
             // VCC -> OEN
-            connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), iob, id_OEN);
+            iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
         }
         iob->params[id_INPUT_USED] = 1;
-        replace_port(nxio, id_O, iob, id_O);
+        nxio->movePortTo(id_O, iob, id_O);
     } else if (nxio->type == id_OBUF) {
         if (iob->type == id_IOBS) {
             // VSS -> OEN
-            connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), iob, id_OEN);
+            iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
         }
         iob->params[id_OUTPUT_USED] = 1;
-        replace_port(nxio, id_I, iob, id_I);
+        nxio->movePortTo(id_I, iob, id_I);
     } else if (nxio->type == id_TBUF) {
         iob->params[id_ENABLE_USED] = 1;
         iob->params[id_OUTPUT_USED] = 1;
-        replace_port(nxio, id_I, iob, id_I);
-        replace_port(nxio, id_OEN, iob, id_OEN);
+        nxio->movePortTo(id_I, iob, id_I);
+        nxio->movePortTo(id_OEN, iob, id_OEN);
     } else if (nxio->type == id_IOBUF) {
         iob->params[id_ENABLE_USED] = 1;
         iob->params[id_INPUT_USED] = 1;
         iob->params[id_OUTPUT_USED] = 1;
-        replace_port(nxio, id_I, iob, id_I);
-        replace_port(nxio, id_O, iob, id_O);
-        replace_port(nxio, id_OEN, iob, id_OEN);
+        nxio->movePortTo(id_I, iob, id_I);
+        nxio->movePortTo(id_O, iob, id_O);
+        nxio->movePortTo(id_OEN, iob, id_OEN);
     } else {
         NPNR_ASSERT(false);
     }
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 1201e31086..268f26ef4e 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -96,7 +96,7 @@ static void pack_alus(Context *ctx)
             log_info("packed ALU head into %s. CIN net is %s\n", ctx->nameOf(packed_head.get()),
                      ctx->nameOf(cin_netId));
         }
-        connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed_head.get(), id_C);
+        packed_head->connectPort(id_C, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
         if (cin_netId == ctx->id("$PACKER_GND_NET")) {
             // CIN = 0
             packed_head->params[id_ALU_MODE] = std::string("C2L");
@@ -106,8 +106,8 @@ static void pack_alus(Context *ctx)
                 packed_head->params[id_ALU_MODE] = std::string("ONE2C");
             } else {
                 // CIN from logic
-                connect_port(ctx, ctx->nets[cin_netId].get(), packed_head.get(), id_B);
-                connect_port(ctx, ctx->nets[cin_netId].get(), packed_head.get(), id_D);
+                packed_head->connectPort(id_B, ctx->nets[cin_netId].get());
+                packed_head->connectPort(id_D, ctx->nets[cin_netId].get());
                 packed_head->params[id_ALU_MODE] = std::string("0"); // ADD
             }
         }
@@ -123,9 +123,9 @@ static void pack_alus(Context *ctx)
             packed_cells.insert(ci->name);
 
             // CIN/COUT are hardwired, delete
-            disconnect_port(ctx, ci, id_CIN);
+            ci->disconnectPort(id_CIN);
             NetInfo *cout = ci->ports.at(id_COUT).net;
-            disconnect_port(ctx, ci, id_COUT);
+            ci->disconnectPort(id_COUT);
 
             std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_ALULC");
             if (ctx->verbose) {
@@ -135,9 +135,9 @@ static void pack_alus(Context *ctx)
             int mode = int_or_default(ci->params, id_ALU_MODE);
             packed->params[id_ALU_MODE] = mode;
             if (mode == 9) { // MULT
-                connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), packed.get(), id_C);
+                packed->connectPort(id_C, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
             } else {
-                connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed.get(), id_C);
+                packed->connectPort(id_C, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
             }
 
             // add to cluster
@@ -149,30 +149,30 @@ static void pack_alus(Context *ctx)
             ++alu_idx;
 
             // connect all remainig ports
-            replace_port(ci, id_SUM, packed.get(), id_F);
+            ci->movePortTo(id_SUM, packed.get(), id_F);
             switch (mode) {
             case 0: // ADD
-                replace_port(ci, id_I0, packed.get(), id_B);
-                replace_port(ci, id_I1, packed.get(), id_D);
+                ci->movePortTo(id_I0, packed.get(), id_B);
+                ci->movePortTo(id_I1, packed.get(), id_D);
                 break;
             case 1: // SUB
-                replace_port(ci, id_I0, packed.get(), id_A);
-                replace_port(ci, id_I1, packed.get(), id_D);
+                ci->movePortTo(id_I0, packed.get(), id_A);
+                ci->movePortTo(id_I1, packed.get(), id_D);
                 break;
             case 5: // LE
-                replace_port(ci, id_I0, packed.get(), id_A);
-                replace_port(ci, id_I1, packed.get(), id_B);
+                ci->movePortTo(id_I0, packed.get(), id_A);
+                ci->movePortTo(id_I1, packed.get(), id_B);
                 break;
             case 9: // MULT
-                replace_port(ci, id_I0, packed.get(), id_A);
-                replace_port(ci, id_I1, packed.get(), id_B);
-                disconnect_port(ctx, packed.get(), id_D);
-                connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), packed.get(), id_D);
+                ci->movePortTo(id_I0, packed.get(), id_A);
+                ci->movePortTo(id_I1, packed.get(), id_B);
+                packed->disconnectPort(id_D);
+                packed->connectPort(id_D, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 break;
             default:
-                replace_port(ci, id_I0, packed.get(), id_A);
-                replace_port(ci, id_I1, packed.get(), id_B);
-                replace_port(ci, id_I3, packed.get(), id_D);
+                ci->movePortTo(id_I0, packed.get(), id_A);
+                ci->movePortTo(id_I1, packed.get(), id_B);
+                ci->movePortTo(id_I3, packed.get(), id_D);
             }
 
             new_cells.push_back(std::move(packed));
@@ -191,7 +191,7 @@ static void pack_alus(Context *ctx)
                                  ctx->nameOf(cout));
                     }
                     packed_tail->params[id_ALU_MODE] = std::string("C2L");
-                    connect_port(ctx, cout, packed_tail.get(), id_F);
+                    packed_tail->connectPort(id_F, cout);
                     // add to cluster
                     packed_tail->cluster = packed_head->name;
                     packed_tail->constr_z = alu_idx % 6;
@@ -275,8 +275,8 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         packed->constr_children.clear();
 
         // reconnect MUX ports
-        replace_port(ci, id_O, packed.get(), id_OF);
-        replace_port(ci, id_I1, packed.get(), id_I1);
+        ci->movePortTo(id_O, packed.get(), id_OF);
+        ci->movePortTo(id_I1, packed.get(), id_I1);
 
         // remove cells
         packed_cells.insert(ci->name);
@@ -320,10 +320,10 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         packed->constr_children.clear();
 
         // reconnect MUX ports
-        replace_port(ci, id_O, packed.get(), id_OF);
-        replace_port(ci, id_S0, packed.get(), id_SEL);
-        replace_port(ci, id_I0, packed.get(), id_I0);
-        replace_port(ci, id_I1, packed.get(), id_I1);
+        ci->movePortTo(id_O, packed.get(), id_OF);
+        ci->movePortTo(id_S0, packed.get(), id_SEL);
+        ci->movePortTo(id_I0, packed.get(), id_I0);
+        ci->movePortTo(id_I1, packed.get(), id_I1);
 
         // remove cells
         packed_cells.insert(ci->name);
@@ -394,10 +394,10 @@ static void pack_mux2_lut(Context *ctx, CellInfo *ci, bool (*pred)(const BaseCtx
     packed->constr_children.push_back(mux1);
 
     // reconnect MUX ports
-    replace_port(ci, id_O, packed.get(), id_OF);
-    replace_port(ci, id_S0, packed.get(), id_SEL);
-    replace_port(ci, id_I0, packed.get(), id_I0);
-    replace_port(ci, id_I1, packed.get(), id_I1);
+    ci->movePortTo(id_O, packed.get(), id_OF);
+    ci->movePortTo(id_S0, packed.get(), id_SEL);
+    ci->movePortTo(id_I0, packed.get(), id_I0);
+    ci->movePortTo(id_I1, packed.get(), id_I1);
 
     // remove cells
     packed_cells.insert(ci->name);
@@ -711,7 +711,7 @@ static void pack_io(Context *ctx)
                 // delete the $nexpnr_[io]buf
                 for (auto &p : iob->ports) {
                     IdString netname = p.second.net->name;
-                    disconnect_port(ctx, iob, p.first);
+                    iob->disconnectPort(p.first);
                     delete_nets.insert(netname);
                 }
                 packed_cells.insert(iob->name);
diff --git a/ice40/arch.cc b/ice40/arch.cc
index cf7e99a54b..b36c82d522 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -1219,17 +1219,17 @@ void Arch::assignCellInfo(CellInfo *cell)
         cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
         cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
         cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
-        cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
-        cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
-        cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
+        cell->lcInfo.clk = cell->getPort(id_CLK);
+        cell->lcInfo.cen = cell->getPort(id_CEN);
+        cell->lcInfo.sr = cell->getPort(id_SR);
         cell->lcInfo.inputCount = 0;
-        if (get_net_or_empty(cell, id_I0))
+        if (cell->getPort(id_I0))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_I1))
+        if (cell->getPort(id_I1))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_I2))
+        if (cell->getPort(id_I2))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_I3))
+        if (cell->getPort(id_I3))
             cell->lcInfo.inputCount++;
     } else if (cell->type == id_SB_IO) {
         cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT";
diff --git a/ice40/cells.cc b/ice40/cells.cc
index a8d3034708..b5f759b22c 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -340,12 +340,12 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
     if (lc->hierpath == IdString())
         lc->hierpath = lut->hierpath;
     lc->params[id_LUT_INIT] = lut->params[id_LUT_INIT].extract(0, 16, Property::State::S0);
-    replace_port(lut, id_I0, lc, id_I0);
-    replace_port(lut, id_I1, lc, id_I1);
-    replace_port(lut, id_I2, lc, id_I2);
-    replace_port(lut, id_I3, lc, id_I3);
+    lut->movePortTo(id_I0, lc, id_I0);
+    lut->movePortTo(id_I1, lc, id_I1);
+    lut->movePortTo(id_I2, lc, id_I2);
+    lut->movePortTo(id_I3, lc, id_I3);
     if (no_dff) {
-        replace_port(lut, id_O, lc, id_O);
+        lut->movePortTo(id_O, lc, id_O);
         lc->params[id_DFF_ENABLE] = Property::State::S0;
     }
 }
@@ -357,7 +357,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
     lc->params[id_DFF_ENABLE] = Property::State::S1;
     std::string config = dff->type.str(ctx).substr(6);
     auto citer = config.begin();
-    replace_port(dff, id_C, lc, id_CLK);
+    dff->movePortTo(id_C, lc, id_CLK);
 
     if (citer != config.end() && *citer == 'N') {
         lc->params[id_NEG_CLK] = Property::State::S1;
@@ -367,7 +367,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
     }
 
     if (citer != config.end() && *citer == 'E') {
-        replace_port(dff, id_E, lc, id_CEN);
+        dff->movePortTo(id_E, lc, id_CEN);
         ++citer;
     }
 
@@ -382,12 +382,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 
         if (*citer == 'S') {
             citer++;
-            replace_port(dff, id_S, lc, id_SR);
+            dff->movePortTo(id_S, lc, id_SR);
             lc->params[id_SET_NORESET] = Property::State::S1;
         } else {
             NPNR_ASSERT(*citer == 'R');
             citer++;
-            replace_port(dff, id_R, lc, id_SR);
+            dff->movePortTo(id_R, lc, id_SR);
             lc->params[id_SET_NORESET] = Property::State::S0;
         }
     }
@@ -396,10 +396,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 
     if (pass_thru_lut) {
         lc->params[id_LUT_INIT] = Property(2, 16);
-        replace_port(dff, id_D, lc, id_I0);
+        dff->movePortTo(id_D, lc, id_I0);
     }
 
-    replace_port(dff, id_Q, lc, id_O);
+    dff->movePortTo(id_Q, lc, id_O);
 }
 
 void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells)
@@ -409,13 +409,13 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         auto pu_attr = nxio->attrs.find(id_PULLUP);
         if (pu_attr != nxio->attrs.end())
             sbio->params[id_PULLUP] = pu_attr->second;
-        replace_port(nxio, id_O, sbio, id_D_IN_0);
+        nxio->movePortTo(id_O, sbio, id_D_IN_0);
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
         sbio->params[id_PIN_TYPE] = 25;
-        replace_port(nxio, id_I, sbio, id_D_OUT_0);
+        nxio->movePortTo(id_I, sbio, id_D_OUT_0);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        NetInfo *i = get_net_or_empty(nxio, id_I);
+        NetInfo *i = nxio->getPort(id_I);
         if (i == nullptr || i->driver.cell == nullptr)
             sbio->params[id_PIN_TYPE] = 1;
         else
@@ -423,8 +423,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         auto pu_attr = nxio->attrs.find(id_PULLUP);
         if (pu_attr != nxio->attrs.end())
             sbio->params[id_PULLUP] = pu_attr->second;
-        replace_port(nxio, id_I, sbio, id_D_OUT_0);
-        replace_port(nxio, id_O, sbio, id_D_IN_0);
+        nxio->movePortTo(id_I, sbio, id_D_OUT_0);
+        nxio->movePortTo(id_O, sbio, id_D_IN_0);
     } else {
         NPNR_ASSERT(false);
     }
@@ -432,9 +432,11 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
 
     // Rename I/O nets to avoid conflicts
     if (donet != nullptr && donet->name == nxio->name)
-        rename_net(ctx, donet, ctx->id(donet->name.str(ctx) + "$SB_IO_OUT"));
+        if (donet)
+            ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$SB_IO_OUT"));
     if (dinet != nullptr && dinet->name == nxio->name)
-        rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$SB_IO_IN"));
+        if (dinet)
+            ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$SB_IO_IN"));
 
     if (ctx->nets.count(nxio->name)) {
         int i = 0;
@@ -442,7 +444,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         do {
             new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
         } while (ctx->nets.count(new_name));
-        rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+        if (ctx->nets.at(nxio->name).get())
+            ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name);
     }
 
     // Create a new top port net for accurate IO timing analysis and simulation netlists
@@ -451,7 +454,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         NPNR_ASSERT(!ctx->nets.count(tn_netname));
         ctx->net_aliases.erase(tn_netname);
         NetInfo *toplevel_net = ctx->createNet(tn_netname);
-        connect_port(ctx, toplevel_net, sbio, id_PACKAGE_PIN);
+        sbio->connectPort(id_PACKAGE_PIN, toplevel_net);
         ctx->ports[nxio->name].net = toplevel_net;
     }
 
@@ -460,8 +463,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
             id_Y);
     if (tbuf) {
         sbio->params[id_PIN_TYPE] = 41;
-        replace_port(tbuf, id_A, sbio, id_D_OUT_0);
-        replace_port(tbuf, id_E, sbio, id_OUTPUT_ENABLE);
+        tbuf->movePortTo(id_A, sbio, id_D_OUT_0);
+        tbuf->movePortTo(id_E, sbio, id_OUTPUT_ENABLE);
 
         if (donet->users.size() > 1) {
             for (auto user : donet->users)
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 0220d4fe76..4244f1921b 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -227,8 +227,8 @@ static void pack_carries(Context *ctx)
                 ++carry_only;
             }
             carry_lc->params[id_CARRY_ENABLE] = Property::State::S1;
-            replace_port(ci, id_CI, carry_lc, id_CIN);
-            replace_port(ci, id_CO, carry_lc, id_COUT);
+            ci->movePortTo(id_CI, carry_lc, id_CIN);
+            ci->movePortTo(id_CO, carry_lc, id_COUT);
             if (i0_net) {
                 auto &i0_usrs = i0_net->users;
                 i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(), [ci, ctx](const PortRef &pr) {
@@ -300,7 +300,7 @@ static void pack_ram(Context *ctx)
                     newname = "RCLK";
                 else if (pi.name == id_WCLKN)
                     newname = "WCLK";
-                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+                ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
             new_cells.push_back(std::move(packed));
         }
@@ -442,7 +442,7 @@ static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell,
     gb->attrs[id_BEL] = ctx->getBelName(gb_bel).str(ctx);
 
     // Reconnect the net to that port for easier identification it's a global net
-    replace_port(cell, port_name, gb.get(), id_GLOBAL_BUFFER_OUTPUT);
+    cell->movePortTo(port_name, gb.get(), id_GLOBAL_BUFFER_OUTPUT);
 
     return gb;
 }
@@ -514,7 +514,7 @@ static void pack_io(Context *ctx)
             } else if (rgb != nullptr) {
                 log_info("%s use by SB_RGBA_DRV/SB_RGB_DRV %s, not creating SB_IO\n", ci->name.c_str(ctx),
                          rgb->name.c_str(ctx));
-                disconnect_port(ctx, ci, id_I);
+                ci->disconnectPort(id_I);
                 packed_cells.insert(ci->name);
                 continue;
             } else {
@@ -525,7 +525,7 @@ static void pack_io(Context *ctx)
                 sb = new_cells.back().get();
             }
             for (auto port : ci->ports)
-                disconnect_port(ctx, ci, port.first);
+                ci->disconnectPort(port.first);
             packed_cells.insert(ci->name);
             for (auto &attr : ci->attrs)
                 sb->attrs[attr.first] = attr.second;
@@ -1138,13 +1138,13 @@ static void pack_special(Context *ctx)
             std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, id_ICESTORM_LFOSC, ci->name.str(ctx) + "_OSC");
             packed_cells.insert(ci->name);
             cell_place_unique(ctx, packed.get());
-            replace_port(ci, id_CLKLFEN, packed.get(), id_CLKLFEN);
-            replace_port(ci, id_CLKLFPU, packed.get(), id_CLKLFPU);
+            ci->movePortTo(id_CLKLFEN, packed.get(), id_CLKLFEN);
+            ci->movePortTo(id_CLKLFPU, packed.get(), id_CLKLFPU);
             if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
-                replace_port(ci, id_CLKLF, packed.get(), id_CLKLF_FABRIC);
+                ci->movePortTo(id_CLKLF, packed.get(), id_CLKLF_FABRIC);
                 set_period(ctx, packed.get(), id_CLKLF_FABRIC, 100000000); // 10kHz
             } else {
-                replace_port(ci, id_CLKLF, packed.get(), id_CLKLF);
+                ci->movePortTo(id_CLKLF, packed.get(), id_CLKLF);
                 std::unique_ptr<CellInfo> gb =
                         create_padin_gbuf(ctx, packed.get(), id_CLKLF, "$gbuf_" + ci->name.str(ctx) + "_lfosc");
                 set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 100000000); // 10kHz
@@ -1157,11 +1157,11 @@ static void pack_special(Context *ctx)
             cell_place_unique(ctx, packed.get());
             packed->params[id_TRIM_EN] = str_or_default(ci->params, id_TRIM_EN, "0b0");
             packed->params[id_CLKHF_DIV] = str_or_default(ci->params, id_CLKHF_DIV, "0b00");
-            replace_port(ci, id_CLKHFEN, packed.get(), id_CLKHFEN);
-            replace_port(ci, id_CLKHFPU, packed.get(), id_CLKHFPU);
+            ci->movePortTo(id_CLKHFEN, packed.get(), id_CLKHFEN);
+            ci->movePortTo(id_CLKHFPU, packed.get(), id_CLKHFPU);
             for (int i = 0; i < 10; i++) {
                 auto port = ctx->id("TRIM" + std::to_string(i));
-                replace_port(ci, port, packed.get(), port);
+                ci->movePortTo(port, packed.get(), port);
             }
             std::string div = packed->params[id_CLKHF_DIV].as_string();
             int frequency;
@@ -1176,10 +1176,10 @@ static void pack_special(Context *ctx)
             else
                 log_error("Invalid HFOSC divider value '%s' - expecting 0b00, 0b01, 0b10 or 0b11\n", div.c_str());
             if (bool_or_default(ci->attrs, id_ROUTE_THROUGH_FABRIC)) {
-                replace_port(ci, id_CLKHF, packed.get(), id_CLKHF_FABRIC);
+                ci->movePortTo(id_CLKHF, packed.get(), id_CLKHF_FABRIC);
                 set_period(ctx, packed.get(), id_CLKHF_FABRIC, 1000000 / frequency);
             } else {
-                replace_port(ci, id_CLKHF, packed.get(), id_CLKHF);
+                ci->movePortTo(id_CLKHF, packed.get(), id_CLKHF);
                 std::unique_ptr<CellInfo> gb =
                         create_padin_gbuf(ctx, packed.get(), id_CLKHF, "$gbuf_" + ci->name.str(ctx) + "_hfosc");
                 set_period(ctx, gb.get(), id_GLOBAL_BUFFER_OUTPUT, 1000000 / frequency);
@@ -1198,7 +1198,7 @@ static void pack_special(Context *ctx)
                 if (bpos != std::string::npos) {
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
-                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+                ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_mac16(ctx, ci)) {
@@ -1216,7 +1216,7 @@ static void pack_special(Context *ctx)
                 if (bpos != std::string::npos) {
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
-                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+                ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_rgba_drv(ctx, ci) || is_sb_rgb_drv(ctx, ci)) {
@@ -1410,7 +1410,7 @@ void pack_plls(Context *ctx)
                         }
                     }
                 }
-                replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
+                ci->movePortTo(ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
 
             // Compute derive constraints
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index 1c4f753be9..c546489201 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -131,10 +131,10 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
     for (std::string i : {"A", "B", "C", "D"}) {
         IdString lut_port = ctx->id(i);
         IdString lc_port = ctx->id(i + "0");
-        replace_port(lut, lut_port, lc, lc_port);
+        lut->movePortTo(lut_port, lc, lc_port);
     }
 
-    replace_port(lut, id_Z, lc, id_F0);
+    lut->movePortTo(id_Z, lc, id_F0);
 }
 
 void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
@@ -142,26 +142,26 @@ void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
     // FIXME: This will have to change once we support FFs with reset value of 1.
     lc->params[id_REG0_REGSET] = std::string("RESET");
 
-    replace_port(dff, id_CLK, lc, id_CLK);
-    replace_port(dff, id_LSR, lc, id_LSR);
-    replace_port(dff, id_Q, lc, id_Q0);
+    dff->movePortTo(id_CLK, lc, id_CLK);
+    dff->movePortTo(id_LSR, lc, id_LSR);
+    dff->movePortTo(id_Q, lc, id_Q0);
 
     if (lut_type == LutType::PassThru) {
         // If a register's DI port is fed by a constant, options for placing are
         // limited. Use the LUT to get around this.
         // LUT output will go to F0, which will feed back to DI0 input.
         lc->params[id_LUT0_INITVAL] = Property(0xAAAA, 16);
-        replace_port(dff, id_DI, lc, id_A0);
-        connect_ports(ctx, lc, id_F0, lc, id_DI0);
+        dff->movePortTo(id_DI, lc, id_A0);
+        lc->connectPorts(id_F0, lc, id_DI0);
     } else if (lut_type == LutType::None) {
         // If there is no LUT, use the M0 input because DI0 requires
         // going through the LUTs.
         lc->params[id_REG0_SD] = std::string("0");
-        replace_port(dff, id_DI, lc, id_M0);
+        dff->movePortTo(id_DI, lc, id_M0);
     } else {
         // Otherwise, there's a LUT being used in the slice and mapping DI to
         // DI0 input is fine.
-        replace_port(dff, id_DI, lc, id_DI0);
+        dff->movePortTo(id_DI, lc, id_DI0);
     }
 }
 
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index de6078656a..5051a98123 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -286,7 +286,7 @@ static void pack_io(Context *ctx)
                 log_info("Removing top-level IOBUF '%s' of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
 
             for (auto &p : ci->ports)
-                disconnect_port(ctx, ci, p.first);
+                ci->disconnectPort(p.first);
             packed_cells.insert(ci->name);
         } else if (is_facade_iob(ctx, ci)) {
             // If FACADE_IO has LOC attribute, convert the LOC (pin) to a BEL
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index e18d141346..35c1303a6e 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -86,8 +86,7 @@ struct MistralBitgen
 
     void write_io_cell(CellInfo *ci, int x, int y, int bi)
     {
-        bool is_output =
-                (ci->type == id_MISTRAL_OB || (ci->type == id_MISTRAL_IO && get_net_or_empty(ci, id_OE) != nullptr));
+        bool is_output = (ci->type == id_MISTRAL_OB || (ci->type == id_MISTRAL_IO && ci->getPort(id_OE) != nullptr));
         auto pos = CycloneV::xy2pos(x, y);
         // TODO: configurable pull, IO standard, etc
         cv->bmux_b_set(CycloneV::GPIO, pos, CycloneV::USE_WEAK_PULLUP, bi, false);
@@ -229,8 +228,8 @@ struct MistralBitgen
             cv->bmux_m_set(block_type, pos, clk_sel[i / 2], alm, clk_choice[ce_idx]);
             if (ff->ffInfo.ctrlset.clk.inverted)
                 cv->bmux_b_set(block_type, pos, clk_inv[ce_idx], 0, true);
-            if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to
-                                                           // ensure different constants don't collide
+            if (ff->getPort(id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to
+                                                  // ensure different constants don't collide
                 cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, true);
                 cv->bmux_b_set(block_type, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted);
             } else {
@@ -262,7 +261,7 @@ struct MistralBitgen
                 cv->bmux_m_set(block_type, pos, clk_sel[1], alm, clk_choice[ce_idx]);
                 if (lut->combInfo.wclk.inverted)
                     cv->bmux_b_set(block_type, pos, clk_inv[ce_idx], 0, true);
-                if (get_net_or_empty(lut, id_A1EN) != nullptr) {
+                if (lut->getPort(id_A1EN) != nullptr) {
                     cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, true);
                     cv->bmux_b_set(block_type, pos, en_ninv[ce_idx], 0, lut->combInfo.we.inverted);
                 } else {
diff --git a/mistral/lab.cc b/mistral/lab.cc
index 4f6b9b00bc..4b66ed0c8a 100644
--- a/mistral/lab.cc
+++ b/mistral/lab.cc
@@ -212,7 +212,7 @@ namespace {
 ControlSig get_ctrlsig(const Context *ctx, const CellInfo *cell, IdString port, bool explicit_const = false)
 {
     ControlSig result;
-    result.net = get_net_or_empty(cell, port);
+    result.net = cell->getPort(port);
     if (result.net == nullptr && explicit_const) {
         // For ENA, 1 (and 0) are explicit control set choices even though they aren't routed, as "no ENA" still
         // consumes a clock+ENA pair
@@ -278,10 +278,10 @@ void Arch::assign_comb_info(CellInfo *cell) const
         cell->combInfo.lut_input_count = 5;
         cell->combInfo.lut_bits_count = 32;
         for (int i = 0; i < 5; i++)
-            cell->combInfo.lut_in[i] = get_net_or_empty(cell, id(stringf("B1ADDR[%d]", i)));
+            cell->combInfo.lut_in[i] = cell->getPort(id(stringf("B1ADDR[%d]", i)));
         auto key = get_mlab_key(cell);
         cell->combInfo.mlab_group = mlab_groups(key);
-        cell->combInfo.comb_out = get_net_or_empty(cell, id_B1DATA);
+        cell->combInfo.comb_out = cell->getPort(id_B1DATA);
     } else if (cell->type == id_MISTRAL_ALUT_ARITH) {
         cell->combInfo.is_carry = true;
         cell->combInfo.lut_input_count = 5;
@@ -292,14 +292,14 @@ void Arch::assign_comb_info(CellInfo *cell) const
         {
             int i = 0;
             for (auto pin : arith_pins) {
-                cell->combInfo.lut_in[i++] = get_net_or_empty(cell, pin);
+                cell->combInfo.lut_in[i++] = cell->getPort(pin);
             }
         }
 
-        const NetInfo *ci = get_net_or_empty(cell, id_CI);
-        const NetInfo *co = get_net_or_empty(cell, id_CO);
+        const NetInfo *ci = cell->getPort(id_CI);
+        const NetInfo *co = cell->getPort(id_CO);
 
-        cell->combInfo.comb_out = get_net_or_empty(cell, id_SO);
+        cell->combInfo.comb_out = cell->getPort(id_SO);
         cell->combInfo.carry_start = (ci == nullptr) || (ci->driver.cell == nullptr);
         cell->combInfo.carry_end = (co == nullptr) || (co->users.empty());
 
@@ -308,10 +308,10 @@ void Arch::assign_comb_info(CellInfo *cell) const
             const CellInfo *prev = ci->driver.cell;
             if (prev != nullptr) {
                 for (int i = 0; i < 5; i++) {
-                    const NetInfo *a = get_net_or_empty(cell, arith_pins[i]);
+                    const NetInfo *a = cell->getPort(arith_pins[i]);
                     if (a == nullptr)
                         continue;
-                    const NetInfo *b = get_net_or_empty(prev, arith_pins[i]);
+                    const NetInfo *b = prev->getPort(arith_pins[i]);
                     if (a == b)
                         ++cell->combInfo.chain_shared_input_count;
                 }
@@ -323,28 +323,28 @@ void Arch::assign_comb_info(CellInfo *cell) const
         switch (cell->type.index) {
         case ID_MISTRAL_ALUT6:
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[5] = get_net_or_empty(cell, id_F);
+            cell->combInfo.lut_in[5] = cell->getPort(id_F);
             [[fallthrough]];
         case ID_MISTRAL_ALUT5:
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[4] = get_net_or_empty(cell, id_E);
+            cell->combInfo.lut_in[4] = cell->getPort(id_E);
             [[fallthrough]];
         case ID_MISTRAL_ALUT4:
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[3] = get_net_or_empty(cell, id_D);
+            cell->combInfo.lut_in[3] = cell->getPort(id_D);
             [[fallthrough]];
         case ID_MISTRAL_ALUT3:
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[2] = get_net_or_empty(cell, id_C);
+            cell->combInfo.lut_in[2] = cell->getPort(id_C);
             [[fallthrough]];
         case ID_MISTRAL_ALUT2:
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[1] = get_net_or_empty(cell, id_B);
+            cell->combInfo.lut_in[1] = cell->getPort(id_B);
             [[fallthrough]];
         case ID_MISTRAL_BUF: // used to route through to FFs etc
         case ID_MISTRAL_NOT: // used for inverters that map to LUTs
             ++cell->combInfo.lut_input_count;
-            cell->combInfo.lut_in[0] = get_net_or_empty(cell, id_A);
+            cell->combInfo.lut_in[0] = cell->getPort(id_A);
             [[fallthrough]];
         case ID_MISTRAL_CONST:
             // MISTRAL_CONST is a nextpnr-inserted cell type for 0-input, constant-generating LUTs
@@ -375,8 +375,8 @@ void Arch::assign_ff_info(CellInfo *cell) const
         cell->ffInfo.ctrlset.sload.inverted = false;
     }
 
-    cell->ffInfo.sdata = get_net_or_empty(cell, id_SDATA);
-    cell->ffInfo.datain = get_net_or_empty(cell, id_DATAIN);
+    cell->ffInfo.sdata = cell->getPort(id_SDATA);
+    cell->ffInfo.datain = cell->getPort(id_DATAIN);
 }
 
 // Validity checking functions
@@ -883,7 +883,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
                 auto &bel_pins = luts[i]->pin_data[log].bel_pins;
                 bel_pins.clear();
 
-                NetInfo *net = get_net_or_empty(luts[i], log);
+                NetInfo *net = luts[i]->getPort(log);
                 if (net == nullptr) {
                     // Disconnected inputs don't need to be allocated a pin, because the router won't be routing these
                     continue;
@@ -922,10 +922,10 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
             rt_lut->addInput(id_A);
             rt_lut->addOutput(id_Q);
             // Disconnect the original data input to the FF, and connect it to the route-thru LUT instead
-            NetInfo *datain = get_net_or_empty(ff, id_DATAIN);
-            disconnect_port(getCtx(), ff, id_DATAIN);
-            connect_port(getCtx(), datain, rt_lut, id_A);
-            connect_ports(getCtx(), rt_lut, id_Q, ff, id_DATAIN);
+            NetInfo *datain = ff->getPort(id_DATAIN);
+            ff->disconnectPort(id_DATAIN);
+            rt_lut->connectPort(id_A, datain);
+            rt_lut->connectPorts(id_Q, ff, id_DATAIN);
             // Assign route-thru LUT physical ports, input goes to the first half-specific input
             rt_lut->pin_data[id_A].bel_pins.push_back(i ? id_D : id_C);
             rt_lut->pin_data[id_Q].bel_pins.push_back(id_COMBOUT);
@@ -1050,7 +1050,7 @@ uint64_t Arch::compute_lut_mask(uint32_t lab, uint8_t alm)
                 else if (state == PIN_1)
                     index |= (1 << init_idx);
                 // Ignore if no associated physical pin
-                if (get_net_or_empty(lut, log_pin) == nullptr || lut->pin_data.at(log_pin).bel_pins.empty())
+                if (lut->getPort(log_pin) == nullptr || lut->pin_data.at(log_pin).bel_pins.empty())
                     continue;
                 // ALM inputs appear to be inverted by default (TODO: check!)
                 // so only invert if an inverter has _not_ been folded into the pin
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 4b434015b2..c4b3afe357 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -41,13 +41,13 @@ struct MistralPacker
         vcc_drv->addOutput(id_Q);
         gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
         vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
-        connect_port(ctx, gnd_net, gnd_drv, id_Q);
-        connect_port(ctx, vcc_net, vcc_drv, id_Q);
+        gnd_drv->connectPort(id_Q, gnd_net);
+        vcc_drv->connectPort(id_Q, vcc_net);
     }
 
     CellPinState get_pin_needed_muxval(CellInfo *cell, IdString port)
     {
-        NetInfo *net = get_net_or_empty(cell, port);
+        NetInfo *net = cell->getPort(port);
         if (net == nullptr || net->driver.cell == nullptr) {
             // Pin is disconnected
             // If a mux value exists already, honour it
@@ -78,14 +78,14 @@ struct MistralPacker
     void uninvert_port(CellInfo *cell, IdString port)
     {
         // Rewire a port so it is driven by the input to an inverter
-        NetInfo *net = get_net_or_empty(cell, port);
+        NetInfo *net = cell->getPort(port);
         NPNR_ASSERT(net != nullptr && net->driver.cell != nullptr && net->driver.cell->type == id_MISTRAL_NOT);
         CellInfo *inv = net->driver.cell;
-        disconnect_port(ctx, cell, port);
+        cell->disconnectPort(port);
 
-        NetInfo *inv_a = get_net_or_empty(inv, id_A);
+        NetInfo *inv_a = inv->getPort(id_A);
         if (inv_a != nullptr) {
-            connect_port(ctx, inv_a, cell, port);
+            cell->connectPort(port, inv_a);
         }
     }
 
@@ -117,12 +117,12 @@ struct MistralPacker
                 // Pin is tied to a constant
                 // If there is a hard constant option; use it
                 if ((pin_style & int(req_mux)) == req_mux) {
-                    disconnect_port(ctx, cell, port_name);
+                    cell->disconnectPort(port_name);
                     cell->pin_data[port_name].state = req_mux;
                 } else {
-                    disconnect_port(ctx, cell, port_name);
+                    cell->disconnectPort(port_name);
                     // There is no hard constant, we need to connect it to the relevant soft-constant net
-                    connect_port(ctx, (req_mux == PIN_1) ? vcc_net : gnd_net, cell, port_name);
+                    cell->connectPort(port_name, (req_mux == PIN_1) ? vcc_net : gnd_net);
                 }
             }
         }
@@ -138,7 +138,7 @@ struct MistralPacker
             if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC)
                 continue;
             IdString port = (ci->type == id_MISTRAL_NOT) ? id_Q : id_Y;
-            NetInfo *out = get_net_or_empty(ci, port);
+            NetInfo *out = ci->getPort(port);
             if (out == nullptr) {
                 trim_cells.push_back(ci->name);
                 continue;
@@ -146,7 +146,7 @@ struct MistralPacker
             if (!out->users.empty())
                 continue;
 
-            disconnect_port(ctx, ci, id_A);
+            ci->disconnectPort(id_A);
 
             trim_cells.push_back(ci->name);
             trim_nets.push_back(out->name);
@@ -174,7 +174,7 @@ struct MistralPacker
                 continue;
             if (ci->get_pin_state(id_SLOAD) != PIN_0)
                 continue;
-            disconnect_port(ctx, ci, id_SDATA);
+            ci->disconnectPort(id_SDATA);
         }
         // Remove superfluous inverters and constant drivers
         trim_design();
@@ -197,7 +197,7 @@ struct MistralPacker
             if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an input buffer (IB etc) connected to it
                 is_npnr_iob = true;
-                NetInfo *o = get_net_or_empty(ci, id_O);
+                NetInfo *o = ci->getPort(id_O);
                 if (o == nullptr)
                     ;
                 else if (o->users.size() > 1)
@@ -208,7 +208,7 @@ struct MistralPacker
             if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an output buffer (OB etc) connected to it
                 is_npnr_iob = true;
-                NetInfo *i = get_net_or_empty(ci, id_I);
+                NetInfo *i = ci->getPort(id_I);
                 if (i != nullptr && i->driver.cell != nullptr) {
                     if (top_port.cell != nullptr)
                         log_error("Top level pin '%s' has multiple input/output buffers\n", ctx->nameOf(port.first));
@@ -245,8 +245,8 @@ struct MistralPacker
                 port.second.net = top_port.cell->ports.at(top_port.port).net;
             }
             // Now remove the nextpnr-inserted buffer
-            disconnect_port(ctx, ci, id_I);
-            disconnect_port(ctx, ci, id_O);
+            ci->disconnectPort(id_I);
+            ci->disconnectPort(id_O);
             ctx->cells.erase(port.first);
         }
     }
@@ -290,14 +290,14 @@ struct MistralPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != id_MISTRAL_ALUT_ARITH)
                 continue;
-            const NetInfo *cin = get_net_or_empty(ci, id_CI);
+            const NetInfo *cin = ci->getPort(id_CI);
             if (cin != nullptr && cin->driver.cell != nullptr)
                 continue; // not the start of a chain
             std::vector<CellInfo *> chain;
             CellInfo *cursor = ci;
             while (true) {
                 chain.push_back(cursor);
-                const NetInfo *co = get_net_or_empty(cursor, id_CO);
+                const NetInfo *co = cursor->getPort(id_CO);
                 if (co == nullptr || co->users.empty())
                     break;
                 if (co->users.size() > 1)
@@ -327,7 +327,7 @@ struct MistralPacker
                 for (int i = 0; i < int(chain.size()); i++) {
                     auto &c = chain.at(i);
                     log_info("    i=%d cell=%s dy=%d z=%d ci=%s co=%s\n", i, ctx->nameOf(c), c->constr_y, c->constr_z,
-                             ctx->nameOf(get_net_or_empty(c, id_CI)), ctx->nameOf(get_net_or_empty(c, id_CO)));
+                             ctx->nameOf(c->getPort(id_CI)), ctx->nameOf(c->getPort(id_CO)));
                 }
             }
         }
@@ -338,7 +338,7 @@ struct MistralPacker
                 continue;
             if (ci->cluster == ClusterId())
                 log_error("Failed to include arith cell '%s' in any chain (CI=%s)\n", ctx->nameOf(ci),
-                          ctx->nameOf(get_net_or_empty(ci, id_CI)));
+                          ctx->nameOf(ci->getPort(id_CI)));
         }
     }
 
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 4aaecdf47d..c460e14bab 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -421,7 +421,7 @@ struct NexusFasmWriter
         BelId bel = cell->bel;
         used_io.insert(bel);
         push_bel(bel);
-        const NetInfo *t = get_net_or_empty(cell, id_T);
+        const NetInfo *t = cell->getPort(id_T);
         auto tmux = ctx->get_cell_pinmux(cell, id_T);
         bool is_input = false, is_output = false;
         if (tmux == PINMUX_0) {
@@ -444,7 +444,7 @@ struct NexusFasmWriter
         used_io.insert(bel);
         push_bel(bel);
         push("SEIO18");
-        const NetInfo *t = get_net_or_empty(cell, id_T);
+        const NetInfo *t = cell->getPort(id_T);
         auto tmux = ctx->get_cell_pinmux(cell, id_T);
         bool is_input = false, is_output = false;
         if (tmux == PINMUX_0) {
@@ -481,7 +481,7 @@ struct NexusFasmWriter
 
         bank.diff_used = true;
 
-        const NetInfo *t = get_net_or_empty(cell, id_T);
+        const NetInfo *t = cell->getPort(id_T);
         auto tmux = ctx->get_cell_pinmux(cell, id_T);
         bool is_input = false, is_output = false;
         if (tmux == PINMUX_0) {
@@ -843,7 +843,7 @@ struct NexusFasmWriter
             if (!ci->attrs.count(id_IO_TYPE))
                 continue;
             // VccO only concerns outputs
-            const NetInfo *t = get_net_or_empty(ci, id_T);
+            const NetInfo *t = ci->getPort(id_T);
             auto tmux = ctx->get_cell_pinmux(ci, id_T);
             if (tmux == PINMUX_1 || (tmux != PINMUX_0 && t == nullptr))
                 continue;
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 13522c78c7..5509d997e1 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -126,12 +126,12 @@ struct NexusPacker
         for (auto pname : orig_port_names) {
             if (rule.port_multixform.count(pname)) {
                 auto old_port = ci->ports.at(pname);
-                disconnect_port(ctx, ci, pname);
+                ci->disconnectPort(pname);
                 ci->ports.erase(pname);
                 for (auto new_name : rule.port_multixform.at(pname)) {
                     ci->ports[new_name].name = new_name;
                     ci->ports[new_name].type = old_port.type;
-                    connect_port(ctx, old_port.net, ci, new_name);
+                    ci->connectPort(new_name, old_port.net);
                 }
             } else {
                 IdString new_name;
@@ -145,7 +145,7 @@ struct NexusPacker
                     new_name = ctx->id(stripped_name);
                 }
                 if (new_name != pname) {
-                    rename_port(ctx, ci, pname, new_name);
+                    ci->renamePort(pname, new_name);
                 }
             }
         }
@@ -307,7 +307,7 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != type)
                 continue;
-            NetInfo *z = get_net_or_empty(ci, id_Z);
+            NetInfo *z = ci->getPort(id_Z);
             if (z == nullptr)
                 continue;
             return z;
@@ -316,13 +316,13 @@ struct NexusPacker
         NetInfo *new_net = ctx->createNet(ctx->id(stringf("$CONST_%s_NET_", type.c_str(ctx))));
         CellInfo *new_cell = ctx->createCell(ctx->id(stringf("$CONST_%s_DRV_", type.c_str(ctx))), type);
         new_cell->addOutput(id_Z);
-        connect_port(ctx, new_net, new_cell, id_Z);
+        new_cell->connectPort(id_Z, new_net);
         return new_net;
     }
 
     CellPinMux get_pin_needed_muxval(CellInfo *cell, IdString port)
     {
-        NetInfo *net = get_net_or_empty(cell, port);
+        NetInfo *net = cell->getPort(port);
         if (net == nullptr || net->driver.cell == nullptr) {
             // Pin is disconnected
             // If a mux value exists already, honour it
@@ -353,14 +353,14 @@ struct NexusPacker
     void uninvert_port(CellInfo *cell, IdString port)
     {
         // Rewire a port so it is driven by the input to an inverter
-        NetInfo *net = get_net_or_empty(cell, port);
+        NetInfo *net = cell->getPort(port);
         NPNR_ASSERT(net != nullptr && net->driver.cell != nullptr && net->driver.cell->type == id_INV);
         CellInfo *inv = net->driver.cell;
-        disconnect_port(ctx, cell, port);
+        cell->disconnectPort(port);
 
-        NetInfo *inv_a = get_net_or_empty(inv, id_A);
+        NetInfo *inv_a = inv->getPort(id_A);
         if (inv_a != nullptr) {
-            connect_port(ctx, inv_a, cell, port);
+            cell->connectPort(port, inv_a);
         }
     }
 
@@ -373,7 +373,7 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != id_INV && ci->type != id_VLO && ci->type != id_VHI && ci->type != id_VCC_DRV)
                 continue;
-            NetInfo *z = get_net_or_empty(ci, id_Z);
+            NetInfo *z = ci->getPort(id_Z);
             if (z == nullptr) {
                 trim_cells.push_back(ci->name);
                 continue;
@@ -381,7 +381,7 @@ struct NexusPacker
             if (!z->users.empty())
                 continue;
 
-            disconnect_port(ctx, ci, id_A);
+            ci->disconnectPort(id_A);
 
             trim_cells.push_back(ci->name);
             trim_nets.push_back(z->name);
@@ -415,7 +415,7 @@ struct NexusPacker
         for (IdString port : port_names) {
             IdString new_name = ctx->id(remove_brackets(port.str(ctx)));
             if (new_name != port)
-                rename_port(ctx, cell, port, new_name);
+                cell->renamePort(port, new_name);
         }
     }
 
@@ -453,17 +453,17 @@ struct NexusPacker
 
                     if ((cell->type == id_OXIDE_COMB) && (req_mux == PINMUX_1)) {
                         // We need to add a connection to the dedicated Vcc resource that can feed these cell ports
-                        disconnect_port(ctx, cell, port_name);
-                        connect_port(ctx, dedi_vcc_net, cell, port_name);
+                        cell->disconnectPort(port_name);
+                        cell->connectPort(port_name, dedi_vcc_net);
                         continue;
                     }
 
-                    disconnect_port(ctx, cell, port_name);
+                    cell->disconnectPort(port_name);
                     ctx->set_cell_pinmux(cell, port_name, req_mux);
                 } else if (port.second.net == nullptr) {
                     // If the port is disconnected; and there is no hard constant
                     // then we need to connect it to the relevant soft-constant net
-                    connect_port(ctx, (req_mux == PINMUX_1) ? vcc_net : gnd_net, cell, port_name);
+                    cell->connectPort(port_name, (req_mux == PINMUX_1) ? vcc_net : gnd_net);
                 }
             }
         }
@@ -486,7 +486,7 @@ struct NexusPacker
             if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an input buffer (IB etc) connected to it
                 is_npnr_iob = true;
-                NetInfo *o = get_net_or_empty(ci, id_O);
+                NetInfo *o = ci->getPort(id_O);
                 if (o == nullptr)
                     ;
                 else if (o->users.size() > 1)
@@ -497,7 +497,7 @@ struct NexusPacker
             if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an output buffer (OB etc) connected to it
                 is_npnr_iob = true;
-                NetInfo *i = get_net_or_empty(ci, id_I);
+                NetInfo *i = ci->getPort(id_I);
                 if (i != nullptr && i->driver.cell != nullptr) {
                     if (top_port.cell != nullptr)
                         log_error("Top level pin '%s' has multiple input/output buffers\n", ctx->nameOf(port.first));
@@ -534,8 +534,8 @@ struct NexusPacker
                 port.second.net = top_port.cell->ports.at(top_port.port).net;
             }
             // Now remove the nextpnr-inserted buffer
-            disconnect_port(ctx, ci, id_I);
-            disconnect_port(ctx, ci, id_O);
+            ci->disconnectPort(id_I);
+            ci->disconnectPort(id_O);
             ctx->cells.erase(port.first);
         }
     }
@@ -635,13 +635,13 @@ struct NexusPacker
             // For non-bidirectional IO, we also need to configure tristate and rename B
             if (ci->type == id_IB) {
                 ctx->set_cell_pinmux(ci, id_T, PINMUX_1);
-                rename_port(ctx, ci, id_I, id_B);
+                ci->renamePort(id_I, id_B);
             } else if (ci->type == id_OB) {
                 ctx->set_cell_pinmux(ci, id_T, PINMUX_0);
-                rename_port(ctx, ci, id_O, id_B);
+                ci->renamePort(id_O, id_B);
             } else if (ci->type == id_OBZ) {
                 ctx->set_cell_pinmux(ci, id_T, PINMUX_SIG);
-                rename_port(ctx, ci, id_O, id_B);
+                ci->renamePort(id_O, id_B);
             }
             // Get the IO bel
             BelId bel = get_bel_attr(ci);
@@ -760,7 +760,7 @@ struct NexusPacker
         if (cell->attrs.count(id_BEL))
             return false;
 
-        NetInfo *pin_net = get_net_or_empty(cell, pin);
+        NetInfo *pin_net = cell->getPort(pin);
         if (pin_net == nullptr)
             return false;
 
@@ -827,7 +827,7 @@ struct NexusPacker
         buffer->addInput(i);
         buffer->addOutput(o);
         // Drive the buffered net with the buffer
-        connect_port(ctx, buffered_net, buffer, o);
+        buffer->connectPort(o, buffered_net);
         // Filter users
         std::vector<PortRef> remaining_users;
 
@@ -843,7 +843,7 @@ struct NexusPacker
         std::swap(net->users, remaining_users);
 
         // Connect buffer input to original net
-        connect_port(ctx, net, buffer, i);
+        buffer->connectPort(i, net);
 
         return buffer;
     }
@@ -936,56 +936,56 @@ struct NexusPacker
                 combs.push_back(
                         ctx->createCell(ctx->id(stringf("%s$lutram_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB));
             // Rewiring - external WCK and WRE
-            replace_port(ci, id_WCK, ramw, id_CLK);
-            replace_port(ci, id_WRE, ramw, id_LSR);
+            ci->movePortTo(id_WCK, ramw, id_CLK);
+            ci->movePortTo(id_WRE, ramw, id_LSR);
 
             // Internal WCK and WRE signals
             ramw->addOutput(id_WCKO);
             ramw->addOutput(id_WREO);
             NetInfo *int_wck = ctx->createNet(ctx->id(stringf("%s$lutram_wck$", ctx->nameOf(ci))));
             NetInfo *int_wre = ctx->createNet(ctx->id(stringf("%s$lutram_wre$", ctx->nameOf(ci))));
-            connect_port(ctx, int_wck, ramw, id_WCKO);
-            connect_port(ctx, int_wre, ramw, id_WREO);
+            ramw->connectPort(id_WCKO, int_wck);
+            ramw->connectPort(id_WREO, int_wre);
 
             uint64_t initval = ctx->parse_lattice_param(ci, id_INITVAL, 64, 0).as_int64();
 
             // Rewiring - buses
             for (int i = 0; i < 4; i++) {
                 // Write address - external
-                replace_port(ci, bus("WAD", i), ramw, ramw_wado[i]);
+                ci->movePortTo(bus("WAD", i), ramw, ramw_wado[i]);
                 // Write data - external
-                replace_port(ci, bus("DI", i), ramw, ramw_wdo[i]);
+                ci->movePortTo(bus("DI", i), ramw, ramw_wdo[i]);
                 // Read data
-                replace_port(ci, bus("DO", i), combs[i], id_F);
+                ci->movePortTo(bus("DO", i), combs[i], id_F);
                 // Read address
-                NetInfo *rad = get_net_or_empty(ci, bus("RAD", i));
+                NetInfo *rad = ci->getPort(bus("RAD", i));
                 if (rad != nullptr) {
                     for (int j = 0; j < 4; j++) {
                         IdString port = (j % 2) ? comb1_rad[i] : comb0_rad[i];
                         combs[j]->addInput(port);
-                        connect_port(ctx, rad, combs[j], port);
+                        combs[j]->connectPort(port, rad);
                     }
-                    disconnect_port(ctx, ci, bus("RAD", i));
+                    ci->disconnectPort(bus("RAD", i));
                 }
                 // Write address - internal
                 NetInfo *int_wad = ctx->createNet(ctx->id(stringf("%s$lutram_wad[%d]$", ctx->nameOf(ci), i)));
                 ramw->addOutput(bus_flat("WADO", i));
-                connect_port(ctx, int_wad, ramw, bus_flat("WADO", i));
+                ramw->connectPort(bus_flat("WADO", i), int_wad);
                 for (int j = 0; j < 4; j++) {
                     combs[j]->addInput(bus_flat("WAD", i));
-                    connect_port(ctx, int_wad, combs[j], bus_flat("WAD", i));
+                    combs[j]->connectPort(bus_flat("WAD", i), int_wad);
                 }
                 // Write data - internal
                 NetInfo *int_wd = ctx->createNet(ctx->id(stringf("%s$lutram_wd[%d]$", ctx->nameOf(ci), i)));
                 ramw->addOutput(bus_flat("WDO", i));
-                connect_port(ctx, int_wd, ramw, bus_flat("WDO", i));
+                ramw->connectPort(bus_flat("WDO", i), int_wd);
                 combs[i]->addInput(id_WDI);
-                connect_port(ctx, int_wd, combs[i], id_WDI);
+                combs[i]->connectPort(id_WDI, int_wd);
                 // Write clock and enable - internal
                 combs[i]->addInput(id_WCK);
                 combs[i]->addInput(id_WRE);
-                connect_port(ctx, int_wck, combs[i], id_WCK);
-                connect_port(ctx, int_wre, combs[i], id_WRE);
+                combs[i]->connectPort(id_WCK, int_wck);
+                combs[i]->connectPort(id_WRE, int_wre);
                 // Remap init val
                 uint64_t split_init = 0;
                 for (int j = 0; j < 16; j++)
@@ -1178,7 +1178,7 @@ struct NexusPacker
             base->params[param.first] = param.second;
         }
         for (auto &port : mergee->ports) {
-            replace_port(mergee, port.first, base, port.first);
+            mergee->movePortTo(port.first, base, port.first);
         }
         ctx->cells.erase(mergee->name);
     }
@@ -1191,13 +1191,13 @@ struct NexusPacker
             if (ci->type != id_IOLOGIC)
                 continue;
             CellInfo *iob = nullptr;
-            NetInfo *di = get_net_or_empty(ci, id_DI);
+            NetInfo *di = ci->getPort(id_DI);
             if (di != nullptr && di->driver.cell != nullptr)
                 iob = di->driver.cell;
-            NetInfo *dout = get_net_or_empty(ci, id_DOUT);
+            NetInfo *dout = ci->getPort(id_DOUT);
             if (dout != nullptr && dout->users.size() == 1)
                 iob = dout->users.at(0).cell;
-            NetInfo *tout = get_net_or_empty(ci, id_TOUT);
+            NetInfo *tout = ci->getPort(id_TOUT);
             if (tout != nullptr && tout->users.size() == 1)
                 iob = tout->users.at(0).cell;
             if (iob == nullptr ||
@@ -1251,20 +1251,20 @@ struct NexusPacker
                         ctx->createCell(ctx->id(stringf("%s$widefn_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB));
 
             for (int i = 0; i < 2; i++) {
-                replace_port(ci, bus_flat("A", i), combs[i], id_A);
-                replace_port(ci, bus_flat("B", i), combs[i], id_B);
-                replace_port(ci, bus_flat("C", i), combs[i], id_C);
-                replace_port(ci, bus_flat("D", i), combs[i], id_D);
+                ci->movePortTo(bus_flat("A", i), combs[i], id_A);
+                ci->movePortTo(bus_flat("B", i), combs[i], id_B);
+                ci->movePortTo(bus_flat("C", i), combs[i], id_C);
+                ci->movePortTo(bus_flat("D", i), combs[i], id_D);
             }
 
-            replace_port(ci, id_SEL, combs[0], id_SEL);
-            replace_port(ci, id_Z, combs[0], id_OFX);
+            ci->movePortTo(id_SEL, combs[0], id_SEL);
+            ci->movePortTo(id_Z, combs[0], id_OFX);
 
             NetInfo *f1 = ctx->createNet(ctx->id(stringf("%s$widefn_f1$", ctx->nameOf(ci))));
             combs[0]->addInput(id_F1);
             combs[1]->addOutput(id_F);
-            connect_port(ctx, f1, combs[1], id_F);
-            connect_port(ctx, f1, combs[0], id_F1);
+            combs[1]->connectPort(id_F, f1);
+            combs[0]->connectPort(id_F1, f1);
 
             combs[0]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT0, 16, 0);
             combs[1]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT1, 16, 0);
@@ -1290,7 +1290,7 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != id_CCU2)
                 continue;
-            if (get_net_or_empty(ci, id_CIN) != nullptr)
+            if (ci->getPort(id_CIN) != nullptr)
                 continue;
             roots.push_back(ci);
         }
@@ -1309,16 +1309,16 @@ struct NexusPacker
                 // Rewire LUT ports
                 for (int i = 0; i < 2; i++) {
                     combs[i]->params[id_MODE] = std::string("CCU2");
-                    replace_port(ci, bus_flat("A", i), combs[i], id_A);
-                    replace_port(ci, bus_flat("B", i), combs[i], id_B);
-                    replace_port(ci, bus_flat("C", i), combs[i], id_C);
-                    replace_port(ci, bus_flat("D", i), combs[i], id_D);
-                    replace_port(ci, bus_flat("S", i), combs[i], id_F);
+                    ci->movePortTo(bus_flat("A", i), combs[i], id_A);
+                    ci->movePortTo(bus_flat("B", i), combs[i], id_B);
+                    ci->movePortTo(bus_flat("C", i), combs[i], id_C);
+                    ci->movePortTo(bus_flat("D", i), combs[i], id_D);
+                    ci->movePortTo(bus_flat("S", i), combs[i], id_F);
                 }
 
                 // External carry chain
-                replace_port(ci, id_CIN, combs[0], id_FCI);
-                replace_port(ci, id_COUT, combs[1], id_FCO);
+                ci->movePortTo(id_CIN, combs[0], id_FCI);
+                ci->movePortTo(id_COUT, combs[1], id_FCO);
 
                 // Copy parameters
                 if (ci->params.count(id_INJECT))
@@ -1330,8 +1330,8 @@ struct NexusPacker
                 NetInfo *int_cy = ctx->createNet(ctx->id(stringf("%s$widefn_int_cy$", ctx->nameOf(ci))));
                 combs[0]->addOutput(id_FCO);
                 combs[1]->addInput(id_FCI);
-                connect_port(ctx, int_cy, combs[0], id_FCO);
-                connect_port(ctx, int_cy, combs[1], id_FCI);
+                combs[0]->connectPort(id_FCO, int_cy);
+                combs[1]->connectPort(id_FCI, int_cy);
 
                 // Relative constraints
                 for (int i = 0; i < 2; i++) {
@@ -1355,7 +1355,7 @@ struct NexusPacker
                 ctx->cells.erase(ci->name);
 
                 // Find next cell in chain, if it exists
-                NetInfo *fco = get_net_or_empty(combs[1], id_FCO);
+                NetInfo *fco = combs[1]->getPort(id_FCO);
                 ci = nullptr;
                 if (fco != nullptr) {
                     if (fco->users.size() > 1)
@@ -1443,13 +1443,13 @@ struct NexusPacker
                         continue;
 
                     // Skip pins that are already in use
-                    if (get_net_or_empty(other_cell, bp.pin) != nullptr)
+                    if (other_cell->getPort(bp.pin) != nullptr)
                         continue;
                     // Create the input if it doesn't exist
                     if (!other_cell->ports.count(bp.pin))
                         other_cell->addInput(bp.pin);
                     // Make the connection
-                    connect_ports(ctx, cell, port.first, other_cell, bp.pin);
+                    cell->connectPorts(port.first, other_cell, bp.pin);
 
                     if (ctx->debug)
                         log_info("         found %s.%s\n", ctx->nameOf(other_cell), ctx->nameOf(bp.pin));
@@ -1729,31 +1729,31 @@ struct NexusPacker
 
                 if (mt.wide > 0) {
                     // Dot-product mode special case
-                    copy_bus(ctx, ci, ctx->id(stringf("B%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, preadd9[i],
-                             id_B, 0, false, 9);
-                    copy_bus(ctx, ci, ctx->id(stringf("A%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, mult9[i],
-                             id_A, 0, false, 9);
-                    copy_port(ctx, ci, id_CLK, mult9[i], id_CLK);
-                    copy_port(ctx, ci, (i > 1) ? id_CEA2A3 : id_CEA0A1, mult9[i], id_CEA);
-                    copy_port(ctx, ci, (i > 1) ? id_RSTA2A3 : id_RSTA0A1, mult9[i], id_RSTA);
-                    copy_port(ctx, ci, id_CLK, preadd9[i], id_CLK);
-                    copy_port(ctx, ci, (i > 1) ? id_CEB2B3 : id_CEB0B1, preadd9[i], id_CEB);
-                    copy_port(ctx, ci, (i > 1) ? id_RSTB2B3 : id_RSTB0B1, preadd9[i], id_RSTB);
+                    ci->copyPortBusTo(ctx->id(stringf("B%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, preadd9[i],
+                                      id_B, 0, false, 9);
+                    ci->copyPortBusTo(ctx->id(stringf("A%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, mult9[i],
+                                      id_A, 0, false, 9);
+                    ci->copyPortTo(id_CLK, mult9[i], id_CLK);
+                    ci->copyPortTo((i > 1) ? id_CEA2A3 : id_CEA0A1, mult9[i], id_CEA);
+                    ci->copyPortTo((i > 1) ? id_RSTA2A3 : id_RSTA0A1, mult9[i], id_RSTA);
+                    ci->copyPortTo(id_CLK, preadd9[i], id_CLK);
+                    ci->copyPortTo((i > 1) ? id_CEB2B3 : id_CEB0B1, preadd9[i], id_CEB);
+                    ci->copyPortTo((i > 1) ? id_RSTB2B3 : id_RSTB0B1, preadd9[i], id_RSTB);
                     // Copy register configuration
                     copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), mult9[i], id_REGBYPSA1);
                     copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), preadd9[i], id_REGBYPSBR0);
                 } else {
                     // B input split across pre-adders
-                    copy_bus(ctx, ci, id_B, b_start, true, preadd9[i], id_B, 0, false, 9);
+                    ci->copyPortBusTo(id_B, b_start, true, preadd9[i], id_B, 0, false, 9);
                     // A input split across MULT9s
-                    copy_bus(ctx, ci, id_A, a_start, true, mult9[i], id_A, 0, false, 9);
+                    ci->copyPortBusTo(id_A, a_start, true, mult9[i], id_A, 0, false, 9);
                     // Connect control set signals
-                    copy_port(ctx, ci, id_CLK, mult9[i], id_CLK);
-                    copy_port(ctx, ci, id_CEA, mult9[i], id_CEA);
-                    copy_port(ctx, ci, id_RSTA, mult9[i], id_RSTA);
-                    copy_port(ctx, ci, id_CLK, preadd9[i], id_CLK);
-                    copy_port(ctx, ci, id_CEB, preadd9[i], id_CEB);
-                    copy_port(ctx, ci, id_RSTB, preadd9[i], id_RSTB);
+                    ci->copyPortTo(id_CLK, mult9[i], id_CLK);
+                    ci->copyPortTo(id_CEA, mult9[i], id_CEA);
+                    ci->copyPortTo(id_RSTA, mult9[i], id_RSTA);
+                    ci->copyPortTo(id_CLK, preadd9[i], id_CLK);
+                    ci->copyPortTo(id_CEB, preadd9[i], id_CEB);
+                    ci->copyPortTo(id_RSTB, preadd9[i], id_RSTB);
                     // Copy register configuration
                     copy_param(ci, id_REGINPUTA, mult9[i], id_REGBYPSA1);
                     copy_param(ci, id_REGINPUTB, preadd9[i], id_REGBYPSBR0);
@@ -1761,12 +1761,12 @@ struct NexusPacker
 
                 // Connect and configure pre-adder if it isn't bypassed
                 if (mt.has_preadd) {
-                    copy_bus(ctx, ci, id_C, 9 * i, true, preadd9[i], id_C, 0, false, 9);
+                    ci->copyPortBusTo(id_C, 9 * i, true, preadd9[i], id_C, 0, false, 9);
                     if (i == (mt.N9x9 - 1))
-                        copy_port(ctx, ci, id_SIGNEDC, preadd9[i], id_C9);
+                        ci->copyPortTo(id_SIGNEDC, preadd9[i], id_C9);
                     copy_param(ci, id_REGINPUTC, preadd9[i], id_REGBYPSBL);
-                    copy_port(ctx, ci, id_CEC, preadd9[i], id_CECL);
-                    copy_port(ctx, ci, id_RSTC, preadd9[i], id_RSTCL);
+                    ci->copyPortTo(id_CEC, preadd9[i], id_CECL);
+                    ci->copyPortTo(id_RSTC, preadd9[i], id_RSTCL);
                     // Enable preadder
                     preadd9[i]->params[id_BYPASS_PREADD9] = std::string("USED");
                     preadd9[i]->params[id_OPC] = std::string("INPUT_C_AS_PREADDER_OPERAND");
@@ -1774,14 +1774,14 @@ struct NexusPacker
                         preadd9[i]->params[id_PREADDCAS_EN] = std::string("ENABLED");
                 } else if (mt.has_addsub) {
                     // Connect only for routeability reasons
-                    copy_bus(ctx, ci, id_C, 10 * i + ((i >= 4) ? 14 : 0), true, preadd9[i], id_C, 0, false, 10);
+                    ci->copyPortBusTo(id_C, 10 * i + ((i >= 4) ? 14 : 0), true, preadd9[i], id_C, 0, false, 10);
                 }
 
                 // Connect up signedness for the most significant nonet
                 if (((b_start + 9) == mt.b_width) || (mt.wide > 0))
-                    copy_port(ctx, ci, mt.has_addsub ? id_SIGNED : id_SIGNEDB, preadd9[i], id_BSIGNED);
+                    ci->copyPortTo(mt.has_addsub ? id_SIGNED : id_SIGNEDB, preadd9[i], id_BSIGNED);
                 if (((a_start + 9) == mt.a_width) || (mt.wide > 0))
-                    copy_port(ctx, ci, mt.has_addsub ? id_SIGNED : id_SIGNEDA, mult9[i], id_ASIGNED);
+                    ci->copyPortTo(mt.has_addsub ? id_SIGNED : id_SIGNEDA, mult9[i], id_ASIGNED);
             }
 
             bool mult36_used = (mt.a_width >= 36) && (mt.b_width >= 36) && !(mt.wide > 0);
@@ -1800,11 +1800,11 @@ struct NexusPacker
             for (int i = 0; i < Nreg18; i++) {
                 // Output split across reg18s
                 if (!mt.has_addsub)
-                    replace_bus(ctx, ci, id_Z, i * 18, true, reg18[i], id_PP, 0, false, 18);
+                    ci->movePortBusTo(id_Z, i * 18, true, reg18[i], id_PP, 0, false, 18);
                 // Connect control set signals
-                copy_port(ctx, ci, id_CLK, reg18[i], id_CLK);
-                copy_port(ctx, ci, mt.has_addsub ? id_CEPIPE : id_CEOUT, reg18[i], id_CEP);
-                copy_port(ctx, ci, mt.has_addsub ? id_RSTPIPE : id_RSTOUT, reg18[i], id_RSTP);
+                ci->copyPortTo(id_CLK, reg18[i], id_CLK);
+                ci->copyPortTo(mt.has_addsub ? id_CEPIPE : id_CEOUT, reg18[i], id_CEP);
+                ci->copyPortTo(mt.has_addsub ? id_RSTPIPE : id_RSTOUT, reg18[i], id_RSTP);
                 // Copy register configuration
                 copy_param(ci, mt.has_addsub ? id_REGPIPELINE : id_REGOUTPUT, reg18[i], id_REGBYPS);
             }
@@ -1817,35 +1817,35 @@ struct NexusPacker
                     acc54[i] = create_dsp_cell(ci->name, id_ACC54_CORE, preadd9[0], (i * 4) + 2, 5);
                 for (int i = 0; i < Nacc54; i++) {
                     // C addsub input
-                    copy_bus(ctx, ci, id_C, 54 * i, true, acc54[i], id_CINPUT, 0, false, 54);
+                    ci->copyPortBusTo(id_C, 54 * i, true, acc54[i], id_CINPUT, 0, false, 54);
                     // Output
-                    replace_bus(ctx, ci, id_Z, i * 54, true, acc54[i], id_SUM0, 0, false, 36);
-                    replace_bus(ctx, ci, id_Z, i * 54 + 36, true, acc54[i], id_SUM1, 0, false, 18);
+                    ci->movePortBusTo(id_Z, i * 54, true, acc54[i], id_SUM0, 0, false, 36);
+                    ci->movePortBusTo(id_Z, i * 54 + 36, true, acc54[i], id_SUM1, 0, false, 18);
                     // Control set
-                    copy_port(ctx, ci, id_CLK, acc54[i], id_CLK);
-                    copy_port(ctx, ci, id_RSTCTRL, acc54[i], id_RSTCTRL);
-                    copy_port(ctx, ci, id_CECTRL, acc54[i], id_CECTRL);
-                    copy_port(ctx, ci, id_RSTCIN, acc54[i], id_RSTCIN);
-                    copy_port(ctx, ci, id_CECIN, acc54[i], id_CECIN);
-                    copy_port(ctx, ci, id_RSTOUT, acc54[i], id_RSTO);
-                    copy_port(ctx, ci, id_CEOUT, acc54[i], id_CEO);
-                    copy_port(ctx, ci, id_RSTC, acc54[i], id_RSTC);
-                    copy_port(ctx, ci, id_CEC, acc54[i], id_CEC);
+                    ci->copyPortTo(id_CLK, acc54[i], id_CLK);
+                    ci->copyPortTo(id_RSTCTRL, acc54[i], id_RSTCTRL);
+                    ci->copyPortTo(id_CECTRL, acc54[i], id_CECTRL);
+                    ci->copyPortTo(id_RSTCIN, acc54[i], id_RSTCIN);
+                    ci->copyPortTo(id_CECIN, acc54[i], id_CECIN);
+                    ci->copyPortTo(id_RSTOUT, acc54[i], id_RSTO);
+                    ci->copyPortTo(id_CEOUT, acc54[i], id_CEO);
+                    ci->copyPortTo(id_RSTC, acc54[i], id_RSTC);
+                    ci->copyPortTo(id_CEC, acc54[i], id_CEC);
                     // Add/acc control
                     if (i == 0)
-                        copy_port(ctx, ci, id_CIN, acc54[i], id_CIN);
+                        ci->copyPortTo(id_CIN, acc54[i], id_CIN);
                     else
                         ctx->set_cell_pinmux(acc54[i], id_CIN, PINMUX_1);
                     if (i == (Nacc54 - 1))
-                        copy_port(ctx, ci, id_SIGNED, acc54[i], id_SIGNEDI);
+                        ci->copyPortTo(id_SIGNED, acc54[i], id_SIGNEDI);
                     if (mt.wide > 0) {
-                        replace_bus(ctx, ci, id_ADDSUB, 0, true, acc54[i], id_ADDSUB, 0, false, 2);
-                        replace_bus(ctx, ci, id_ADDSUB, 2, true, acc54[i], id_M9ADDSUB, 0, false, 2);
+                        ci->movePortBusTo(id_ADDSUB, 0, true, acc54[i], id_ADDSUB, 0, false, 2);
+                        ci->movePortBusTo(id_ADDSUB, 2, true, acc54[i], id_M9ADDSUB, 0, false, 2);
                     } else {
-                        copy_port(ctx, ci, id_ADDSUB, acc54[i], id_ADDSUB0);
-                        copy_port(ctx, ci, id_ADDSUB, acc54[i], id_ADDSUB1);
+                        ci->copyPortTo(id_ADDSUB, acc54[i], id_ADDSUB0);
+                        ci->copyPortTo(id_ADDSUB, acc54[i], id_ADDSUB1);
                     }
-                    copy_port(ctx, ci, id_LOADC, acc54[i], id_LOAD);
+                    ci->copyPortTo(id_LOADC, acc54[i], id_LOAD);
                     // Configuration
                     copy_param(ci, id_REGINPUTC, acc54[i], id_CREGBYPS1);
                     copy_param(ci, id_REGADDSUB, acc54[i], id_ADDSUBSIGNREGBYPS1);
@@ -1881,7 +1881,7 @@ struct NexusPacker
 
         for (auto cell : to_remove) {
             for (auto &port : cell->ports)
-                disconnect_port(ctx, cell, port.first);
+                cell->disconnectPort(port.first);
             ctx->cells.erase(cell->name);
         }
     }
@@ -2042,9 +2042,9 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type == id_PLL_CORE) {
                 // Extra log to phys rules
-                rename_port(ctx, ci, id_PLLPOWERDOWN_N, id_PLLPDN);
-                rename_port(ctx, ci, id_LMMIWRRD_N, id_LMMIWRRDN);
-                rename_port(ctx, ci, id_LMMIRESET_N, id_LMMIRESETN);
+                ci->renamePort(id_PLLPOWERDOWN_N, id_PLLPDN);
+                ci->renamePort(id_LMMIWRRD_N, id_LMMIWRRDN);
+                ci->renamePort(id_LMMIRESET_N, id_LMMIRESETN);
                 for (auto &defparam : pll_defaults)
                     if (!ci->params.count(defparam.first))
                         ci->params[defparam.first] = defparam.second;
@@ -2086,7 +2086,7 @@ struct NexusPacker
     {
 
         // Get the net
-        NetInfo *net = get_net_or_empty(iob, port);
+        NetInfo *net = iob->getPort(port);
         if (net == nullptr) {
             return nullptr;
         }
@@ -2099,8 +2099,8 @@ struct NexusPacker
 
         // Get clock nets of IOLOGIC and the flip-flop
         if (iol != nullptr) {
-            NetInfo *iol_c = get_net_or_empty(iol, id_SCLKOUT);
-            NetInfo *ff_c = get_net_or_empty(ff, id_CLK);
+            NetInfo *iol_c = iol->getPort(id_SCLKOUT);
+            NetInfo *ff_c = ff->getPort(id_CLK);
 
             // If one of them is floating or it is not the same net then abort
             if (iol_c == nullptr || ff_c == nullptr) {
@@ -2113,8 +2113,8 @@ struct NexusPacker
 
         // Get reset nets of IOLOGIC and the flip-flop
         if (iol != nullptr) {
-            NetInfo *iol_r = get_net_or_empty(iol, id_LSROUT);
-            NetInfo *ff_r = get_net_or_empty(ff, id_LSR);
+            NetInfo *iol_r = iol->getPort(id_LSROUT);
+            NetInfo *ff_r = ff->getPort(id_LSR);
 
             // If one of them is floating or it is not the same net then abort.
             // But both can be floating.
@@ -2155,17 +2155,17 @@ struct NexusPacker
             bool isODDR = false;
 
             CellInfo *iob = nullptr;
-            NetInfo *di = get_net_or_empty(iol, id_DI);
+            NetInfo *di = iol->getPort(id_DI);
             if (di != nullptr && di->driver.cell != nullptr) {
                 iob = di->driver.cell;
                 isIDDR = true;
             }
-            NetInfo *dout = get_net_or_empty(iol, id_DOUT);
+            NetInfo *dout = iol->getPort(id_DOUT);
             if (dout != nullptr && dout->users.size() == 1) {
                 iob = dout->users.at(0).cell;
                 isODDR = true;
             }
-            NetInfo *tout = get_net_or_empty(iol, id_TOUT);
+            NetInfo *tout = iol->getPort(id_TOUT);
             if (tout != nullptr && tout->users.size() == 1) {
                 iob = tout->users.at(0).cell;
                 isODDR = true; // FIXME: Not sure
@@ -2205,9 +2205,9 @@ struct NexusPacker
                 // same ned as SEIO33_CORE.I.
                 //
                 //
-                NetInfo *iob_t = get_net_or_empty(iob, id_T);
+                NetInfo *iob_t = iob->getPort(id_T);
                 if (iob_t != nullptr && isODDR) {
-                    NetInfo *iol_t = get_net_or_empty(iol, id_TOUT);
+                    NetInfo *iol_t = iol->getPort(id_TOUT);
 
                     // SIOLOGIC.TOUT is not driving SEIO33_CORE.T
                     if ((iol_t == nullptr) || (iol_t != nullptr && iol_t->users.empty()) ||
@@ -2216,7 +2216,7 @@ struct NexusPacker
                         // In this case if SIOLOGIC.TSDATA0 is not connected
                         // to the same net as SEIO33_CORE.T and is not
                         // floating then that configuration is illegal.
-                        NetInfo *iol_ti = get_net_or_empty(iol, id_TSDATA0);
+                        NetInfo *iol_ti = iol->getPort(id_TSDATA0);
                         if (iol_ti != nullptr && (iol_ti->name != iob_t->name) && (iol_ti->name != gnd_net->name)) {
                             log_error("Cannot have %s.TSDATA0 and %s.T driven by different nets (%s vs. %s)\n",
                                       ctx->nameOf(iol), ctx->nameOf(iob), ctx->nameOf(iol_ti), ctx->nameOf(iob_t));
@@ -2227,8 +2227,8 @@ struct NexusPacker
                         if (!iol->ports.count(id_TSDATA0)) {
                             iol->addInput(id_TSDATA0);
                         }
-                        disconnect_port(ctx, iol, id_TSDATA0);
-                        connect_port(ctx, iob_t, iol, id_TSDATA0);
+                        iol->disconnectPort(id_TSDATA0);
+                        iol->connectPort(id_TSDATA0, iob_t);
 
                         if (ctx->debug) {
                             log_info(" Reconnecting %s.TSDATA0 to %s\n", ctx->nameOf(iol), ctx->nameOf(iob_t));
@@ -2256,10 +2256,10 @@ struct NexusPacker
         for (auto &it : tff_map) {
             CellInfo *ff = ctx->cells.at(it.first).get();
 
-            NetInfo *ff_d = get_net_or_empty(ff, id_M); // FIXME: id_D or id_M ?!
+            NetInfo *ff_d = ff->getPort(id_M); // FIXME: id_D or id_M ?!
             NPNR_ASSERT(ff_d != nullptr);
 
-            NetInfo *ff_q = get_net_or_empty(ff, id_Q);
+            NetInfo *ff_q = ff->getPort(id_Q);
             NPNR_ASSERT(ff_q != nullptr);
 
             for (auto &ios : it.second) {
@@ -2269,12 +2269,12 @@ struct NexusPacker
                 log_info(" Integrating %s into %s\n", ctx->nameOf(ff), ctx->nameOf(iol));
 
                 // Disconnect "old" T net
-                disconnect_port(ctx, iol, id_TSDATA0);
-                disconnect_port(ctx, iob, id_T);
+                iol->disconnectPort(id_TSDATA0);
+                iob->disconnectPort(id_T);
 
                 // Connect the "new" one
-                connect_port(ctx, ff_d, iol, id_TSDATA0);
-                connect_port(ctx, ff_d, iob, id_T);
+                iol->connectPort(id_TSDATA0, ff_d);
+                iob->connectPort(id_T, ff_d);
 
                 // Propagate parameters
                 iol->params[id_SRMODE] = ff->params.at(id_SRMODE);
@@ -2288,7 +2288,7 @@ struct NexusPacker
 
             // Disconnect the flip-flop
             for (auto &port : ff->ports) {
-                disconnect_port(ctx, ff, port.first);
+                ff->disconnectPort(port.first);
             }
 
             // Check if the flip-flop can be removed
@@ -2316,9 +2316,9 @@ struct NexusPacker
         ctrlset.clkmux = ctx->id(str_or_default(cell->params, id_CLKMUX, "CLK")).index;
         ctrlset.cemux = ctx->id(str_or_default(cell->params, id_CEMUX, "CE")).index;
         ctrlset.lsrmux = ctx->id(str_or_default(cell->params, id_LSRMUX, "LSR")).index;
-        ctrlset.clk = get_net_or_empty(cell, id_CLK);
-        ctrlset.ce = get_net_or_empty(cell, id_CE);
-        ctrlset.lsr = get_net_or_empty(cell, id_LSR);
+        ctrlset.clk = cell->getPort(id_CLK);
+        ctrlset.ce = cell->getPort(id_CE);
+        ctrlset.lsr = cell->getPort(id_LSR);
 
         return ctrlset;
     }
@@ -2353,7 +2353,7 @@ struct NexusPacker
 
             // Get input net
             // At the packing stage all inputs go to M
-            NetInfo *di = get_net_or_empty(ff, id_M);
+            NetInfo *di = ff->getPort(id_M);
             if (di == nullptr || di->driver.cell == nullptr) {
                 continue;
             }
@@ -2373,7 +2373,7 @@ struct NexusPacker
             }
 
             // The FF must not use M and DI at the same time
-            if (get_net_or_empty(ff, id_DI)) {
+            if (ff->getPort(id_DI)) {
                 continue;
             }
 
@@ -2445,7 +2445,7 @@ struct NexusPacker
             }
 
             // Reconnect M to DI
-            rename_port(ctx, ff, id_M, id_DI);
+            ff->renamePort(id_M, id_DI);
             ff->params[id_SEL] = std::string("DL");
 
             // Store FF settings of the cluster
@@ -2528,8 +2528,8 @@ void Arch::assignCellInfo(CellInfo *cell)
         cell->lutInfo.is_memory = str_or_default(cell->params, id_MODE, "LOGIC") == "DPRAM";
         cell->lutInfo.is_carry = str_or_default(cell->params, id_MODE, "LOGIC") == "CCU2";
         cell->lutInfo.mux2_used = port_used(cell, id_OFX);
-        cell->lutInfo.f = get_net_or_empty(cell, id_F);
-        cell->lutInfo.ofx = get_net_or_empty(cell, id_OFX);
+        cell->lutInfo.f = cell->getPort(id_F);
+        cell->lutInfo.ofx = cell->getPort(id_OFX);
         if (cell->lutInfo.is_carry) {
             cell->tmg_portmap[id_A] = id_A0;
             cell->tmg_portmap[id_B] = id_B0;
@@ -2551,11 +2551,11 @@ void Arch::assignCellInfo(CellInfo *cell)
         cell->ffInfo.ctrlset.clkmux = id(str_or_default(cell->params, id_CLKMUX, "CLK")).index;
         cell->ffInfo.ctrlset.cemux = id(str_or_default(cell->params, id_CEMUX, "CE")).index;
         cell->ffInfo.ctrlset.lsrmux = id(str_or_default(cell->params, id_LSRMUX, "LSR")).index;
-        cell->ffInfo.ctrlset.clk = get_net_or_empty(cell, id_CLK);
-        cell->ffInfo.ctrlset.ce = get_net_or_empty(cell, id_CE);
-        cell->ffInfo.ctrlset.lsr = get_net_or_empty(cell, id_LSR);
-        cell->ffInfo.di = get_net_or_empty(cell, id_DI);
-        cell->ffInfo.m = get_net_or_empty(cell, id_M);
+        cell->ffInfo.ctrlset.clk = cell->getPort(id_CLK);
+        cell->ffInfo.ctrlset.ce = cell->getPort(id_CE);
+        cell->ffInfo.ctrlset.lsr = cell->getPort(id_LSR);
+        cell->ffInfo.di = cell->getPort(id_DI);
+        cell->ffInfo.m = cell->getPort(id_M);
         cell->tmg_index = get_cell_timing_idx(id_OXIDE_FF, id("PPP:SYNC"));
     } else if (cell->type == id_RAMW) {
         cell->ffInfo.ctrlset.async = true;
@@ -2564,9 +2564,9 @@ void Arch::assignCellInfo(CellInfo *cell)
         cell->ffInfo.ctrlset.clkmux = id(str_or_default(cell->params, id_CLKMUX, "CLK")).index;
         cell->ffInfo.ctrlset.cemux = ID_CE;
         cell->ffInfo.ctrlset.lsrmux = ID_INV;
-        cell->ffInfo.ctrlset.clk = get_net_or_empty(cell, id_CLK);
+        cell->ffInfo.ctrlset.clk = cell->getPort(id_CLK);
         cell->ffInfo.ctrlset.ce = nullptr;
-        cell->ffInfo.ctrlset.lsr = get_net_or_empty(cell, id_LSR);
+        cell->ffInfo.ctrlset.lsr = cell->getPort(id_LSR);
         cell->ffInfo.di = nullptr;
         cell->ffInfo.m = nullptr;
         cell->tmg_index = get_cell_timing_idx(id_RAMW);
diff --git a/nexus/post_place.cc b/nexus/post_place.cc
index f42c0f1892..289f82b254 100644
--- a/nexus/post_place.cc
+++ b/nexus/post_place.cc
@@ -94,12 +94,12 @@ struct NexusPostPlaceOpt
             if (ff->type != id_OXIDE_FF)
                 continue;
             // Check M ('fabric') input net
-            NetInfo *m = get_net_or_empty(ff, id_M);
+            NetInfo *m = ff->getPort(id_M);
             if (m == nullptr)
                 continue;
 
             // Ignore FFs that need both DI and M (PRLD mode)
-            if (get_net_or_empty(ff, id_DI) != nullptr)
+            if (ff->getPort(id_DI) != nullptr)
                 continue;
 
             const auto &drv = m->driver;
@@ -118,7 +118,7 @@ struct NexusPostPlaceOpt
             if (dest_ff != ff->bel) {
                 // If dest_ff is already placed *and* using direct 'DI' input, don't touch it
                 CellInfo *dest_ff_cell = ctx->getBoundBelCell(dest_ff);
-                if (dest_ff_cell != nullptr && get_net_or_empty(dest_ff_cell, id_DI) != nullptr)
+                if (dest_ff_cell != nullptr && dest_ff_cell->getPort(id_DI) != nullptr)
                     continue;
                 // Attempt the swap
                 bool swap_result = swap_cell_placement(ff, dest_ff);
@@ -126,7 +126,7 @@ struct NexusPostPlaceOpt
                     continue;
             }
             // Use direct interconnect
-            rename_port(ctx, ff, id_M, id_DI);
+            ff->renamePort(id_M, id_DI);
             ff->params[id_SEL] = std::string("DL");
             ++moves_made;
             continue;

From 75c45dbef158a7f8867e5fc9565cb14a5f06ab2a Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 20 Feb 2022 18:26:17 +0000
Subject: [PATCH 070/712] Add IdStringList::concat overrides taking IdString

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/idstringlist.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/common/idstringlist.h b/common/idstringlist.h
index fd57540b39..5e462d0e8d 100644
--- a/common/idstringlist.h
+++ b/common/idstringlist.h
@@ -67,6 +67,10 @@ struct IdStringList
     }
 
     static IdStringList concat(IdStringList a, IdStringList b);
+    static IdStringList concat(IdString a, IdString b) { return concat(IdStringList(a), IdStringList(b)); }
+    static IdStringList concat(IdStringList a, IdString b) { return concat(a, IdStringList(b)); }
+    static IdStringList concat(IdString a, IdStringList b) { return concat(IdStringList(a), b); }
+
     IdStringList slice(size_t s, size_t e) const;
 
     unsigned int hash() const

From ad49b7c78d393cf95d5d80707008d5904d302df2 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 23 Feb 2022 15:53:04 +1000
Subject: [PATCH 071/712] gowin: Add support for true differential output

The new primitive appears as an amalgamation of two existing OBUF
primitives.  Compatible with older versions of apicula, although, of
course, using TLVDS_OBUF with old databases will not bring the desired
result, but no crash.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/constids.inc |  5 +++
 gowin/pack.cc      | 82 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)

diff --git a/gowin/constids.inc b/gowin/constids.inc
index be016e0e62..3e72340abd 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -636,6 +636,8 @@ X(I)
 X(O)
 X(IO)
 X(OE)
+X(OB)
+
 // bels
 X(DFF0)
 X(DFF1)
@@ -735,6 +737,7 @@ X(IBUF)
 X(OBUF)
 X(IOBUF)
 X(TBUF)
+X(TLVDS_OBUF)
 
 // primitive attributes
 X(INIT)
@@ -744,6 +747,8 @@ X(INPUT_USED)
 X(OUTPUT_USED)
 X(ENABLE_USED)
 X(BEL)
+X(DIFF)
+X(DIFF_TYPE)
 
 // ports
 X(EN)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 268f26ef4e..cc71586436 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -678,6 +678,85 @@ static bool is_gowin_iob(const Context *ctx, const CellInfo *cell)
     }
 }
 
+static bool is_gowin_diff_iob(const Context *ctx, const CellInfo *cell)
+{
+    switch (cell->type.index) {
+    case ID_TLVDS_OBUF:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); }
+
+// Pack differential IO buffers
+static void pack_diff_io(Context *ctx)
+{
+    pool<IdString> packed_cells;
+    pool<IdString> delete_nets;
+
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    log_info("Packing diff IOs..\n");
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+        if (is_gowin_diff_iob(ctx, ci)) {
+            CellInfo *iob_p = nullptr;
+            CellInfo *iob_n = nullptr;
+            switch (ci->type.index) {
+            case ID_TLVDS_OBUF: {
+                iob_p = net_only_drives(ctx, ci->ports.at(id_O).net, is_iob, id_I);
+                iob_n = net_only_drives(ctx, ci->ports.at(id_OB).net, is_iob, id_I);
+                NPNR_ASSERT(iob_p != nullptr);
+                NPNR_ASSERT(iob_n != nullptr);
+                auto iob_p_bel_a = iob_p->attrs.find(id_BEL);
+                if (iob_p_bel_a == ci->attrs.end()) {
+                    log_error("LVDS '%s' must be restricted.\n", ctx->nameOf(ci));
+                    continue;
+                }
+                BelId iob_p_bel = ctx->getBelByNameStr(iob_p_bel_a->second.as_string());
+                Loc loc_p = ctx->getBelLocation(iob_p_bel);
+                if (loc_p.z != 0) {
+                    log_error("LVDS '%s' positive pin is not A.\n", ctx->nameOf(ci));
+                    continue;
+                }
+                // restrict the N buffer
+                loc_p.z = 1;
+                iob_n->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc_p)).str(ctx);
+                // mark IOBs as part of DS pair
+                iob_n->attrs[id_DIFF] = std::string("N");
+                iob_n->attrs[id_DIFF_TYPE] = std::string("TLVDS_OBUF");
+                iob_p->attrs[id_DIFF] = std::string("P");
+                iob_p->attrs[id_DIFF_TYPE] = std::string("TLVDS_OBUF");
+                // disconnect N input: it is wired internally
+                delete_nets.insert(iob_n->ports.at(id_I).net->name);
+                iob_n->disconnectPort(id_I);
+                ci->disconnectPort(id_OB);
+                // disconnect P output
+                delete_nets.insert(ci->ports.at(id_O).net->name);
+                ci->disconnectPort(id_O);
+                // connect TLVDS input to P input
+                ci->movePortTo(id_I, iob_p, id_I);
+                packed_cells.insert(ci->name);
+            } break;
+            default:
+                break;
+            }
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto dnet : delete_nets) {
+        ctx->nets.erase(dnet);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
 // Pack IO buffers
 static void pack_io(Context *ctx)
 {
@@ -689,6 +768,8 @@ static void pack_io(Context *ctx)
 
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
         if (is_gowin_iob(ctx, ci)) {
             CellInfo *iob = nullptr;
             switch (ci->type.index) {
@@ -776,6 +857,7 @@ bool Arch::pack()
         log_break();
         pack_constants(ctx);
         pack_io(ctx);
+        pack_diff_io(ctx);
         pack_wideluts(ctx);
         pack_alus(ctx);
         pack_lut_lutffs(ctx);

From 3894a36ddbbaf30494b77f0f108cfa359886807a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 24 Feb 2022 13:35:22 +1000
Subject: [PATCH 072/712] gowin: recognize partnumbers of GW1NZ-1

The model should be recognized by the partnumber, --family is needed
only if the same partnumbers belong to different models.
This is done in order to automatically generate parameters for calling
nextpnr from Gowin files without problems: there also only partnumber is
used and only in some cases the model is specified with the -name
parameter and GW1NZ-1 is not such a case.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/main.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index 38a67fcd18..1473f3e89b 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -55,7 +55,7 @@ po::options_description GowinCommandHandler::getArchOptions()
 
 std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Property> &values)
 {
-    std::regex devicere = std::regex("GW1N(S?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
+    std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
     std::smatch match;
     std::string device = vm["device"].as<std::string>();
     if (!std::regex_match(device, match, devicere)) {

From fbb02e286047108dbfbd6bd71cddc777a6752ecf Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 24 Feb 2022 20:29:43 +0000
Subject: [PATCH 073/712] okami: new Viaduct arch

---
 generic/family.cmake                     |   2 +-
 generic/viaduct/okami/constids.inc       |  14 +
 generic/viaduct/okami/okami.cc           | 546 +++++++++++++++++++++++
 generic/viaduct/okami/okami_map.v        |  12 +
 generic/viaduct/okami/okami_prims.v      |  35 ++
 generic/viaduct/okami/synth_okami.tcl    |  24 +
 generic/viaduct/okami/viaduct_example.sh |   6 +
 7 files changed, 638 insertions(+), 1 deletion(-)
 create mode 100644 generic/viaduct/okami/constids.inc
 create mode 100644 generic/viaduct/okami/okami.cc
 create mode 100644 generic/viaduct/okami/okami_map.v
 create mode 100644 generic/viaduct/okami/okami_prims.v
 create mode 100644 generic/viaduct/okami/synth_okami.tcl
 create mode 100755 generic/viaduct/okami/viaduct_example.sh

diff --git a/generic/family.cmake b/generic/family.cmake
index cd4e3801e4..de4ce1afa8 100644
--- a/generic/family.cmake
+++ b/generic/family.cmake
@@ -1,4 +1,4 @@
-set(VIADUCT_UARCHES "example")
+set(VIADUCT_UARCHES "example" "okami")
 foreach(uarch ${VIADUCT_UARCHES})
     aux_source_directory(${family}/viaduct/${uarch} UARCH_FILES)
     foreach(target ${family_targets})
diff --git a/generic/viaduct/okami/constids.inc b/generic/viaduct/okami/constids.inc
new file mode 100644
index 0000000000..b40d5be8a0
--- /dev/null
+++ b/generic/viaduct/okami/constids.inc
@@ -0,0 +1,14 @@
+X(LUT4)
+X(DFF)
+X(CLK)
+X(D)
+X(F)
+X(Q)
+X(INBUF)
+X(OUTBUF)
+X(I)
+X(EN)
+X(O)
+X(IOB)
+X(PAD)
+X(INIT)
diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc
new file mode 100644
index 0000000000..bcb34e8472
--- /dev/null
+++ b/generic/viaduct/okami/okami.cc
@@ -0,0 +1,546 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2022  Lofty <dan.ravensloft@gmail.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+#include "viaduct_api.h"
+#include "viaduct_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define VIADUCT_CONSTIDS "viaduct/okami/constids.inc"
+#include "viaduct_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct OkamiImpl : ViaductAPI
+{
+    ~OkamiImpl(){};
+    void init(Context *ctx) override
+    {
+        init_uarch_constids(ctx);
+        ViaductAPI::init(ctx);
+        h.init(ctx);
+        init_wires();
+        init_bels();
+        init_pips();
+    }
+
+    void pack() override
+    {
+        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_INBUF, id_PAD),
+                CellTypePort(id_OUTBUF, id_PAD),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+        // Replace constants with LUTs
+        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
+        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
+        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+        // Constrain directly connected LUTs and FFs together to use dedicated resources
+        int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1,
+                                            false);
+        log_info("Constrained %d LUTFF pairs.\n", lutffs);
+    }
+
+    void prePlace() override { assign_cell_info(); }
+
+    bool isBelLocationValid(BelId bel) const override
+    {
+        Loc l = ctx->getBelLocation(bel);
+        if (is_io(l.x, l.y)) {
+            return true;
+        } else {
+            return slice_valid(l.x, l.y, l.z / 2);
+        }
+    }
+
+  private:
+    ViaductHelpers h;
+    // Configuration
+    // Grid size including IOBs at edges
+    const int M = 32;
+    const int X = M, Y = M;
+    // SLICEs per tile
+    const int N = 8;
+    // LUT input count
+    const int K = 4;
+    // Number of tile input buses
+    const int InputMuxCount = 10; // >= 6 for attosoc; >= 10 for arbiter
+    // Number of output wires in a direction
+    const int OutputMuxCount = 8; // >= 5 for attosoc; >= 8 for arbiter
+
+    // For fast wire lookups
+    struct TileWires
+    {
+        std::vector<WireId> clk, q, f, d;
+        std::vector<WireId> slice_inputs;
+        std::vector<WireId> slice_outputs;
+        std::vector<WireId> tile_inputs_north, tile_inputs_east, tile_inputs_south, tile_inputs_west;
+        std::vector<WireId> tile_outputs_north, tile_outputs_east, tile_outputs_south, tile_outputs_west;
+        std::vector<WireId> pad;
+    };
+
+    std::vector<std::vector<TileWires>> wires_by_tile;
+
+    // Create wires to attach to bels and pips
+    void init_wires()
+    {
+        NPNR_ASSERT(X >= 3);
+        NPNR_ASSERT(Y >= 3);
+        NPNR_ASSERT(K >= 2);
+        NPNR_ASSERT(N >= 1);
+        NPNR_ASSERT(InputMuxCount >= OutputMuxCount);
+
+        log_info("Creating wires...\n");
+        wires_by_tile.resize(Y);
+        for (int y = 0; y < Y; y++) {
+            auto &row_wires = wires_by_tile.at(y);
+            row_wires.resize(X);
+            for (int x = 0; x < X; x++) {
+                auto &w = row_wires.at(x);
+                for (int z = 0; z < N; z++) {
+                    // Clock input
+                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y));
+                    // FF input
+                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y));
+                    // FF and LUT outputs
+                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y));
+                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y));
+                    // LUT inputs
+                    for (int i = 0; i < K; i++)
+                        w.slice_inputs.push_back(
+                                ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y));
+                    w.slice_outputs.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("SLICEOUT[%d]", z))),
+                                                           ctx->id("SLICEOUT"), x, y));
+                }
+                // Tile inputs
+                for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
+                    w.tile_inputs_north.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEINN[%d]", tile_input))), ctx->id("TILEINN"), x, y));
+                    w.tile_inputs_east.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEINE[%d]", tile_input))), ctx->id("TILEINE"), x, y));
+                    w.tile_inputs_south.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEINS[%d]", tile_input))), ctx->id("TILEINS"), x, y));
+                    w.tile_inputs_west.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEINW[%d]", tile_input))), ctx->id("TILEINW"), x, y));
+                }
+                // Tile outputs
+                for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++) {
+                    w.tile_outputs_north.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEOUTN[%d]", tile_output))), ctx->id("TILEOUTN"), x, y));
+                    w.tile_outputs_east.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEOUTE[%d]", tile_output))), ctx->id("TILEOUTE"), x, y));
+                    w.tile_outputs_south.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEOUTS[%d]", tile_output))), ctx->id("TILEOUTS"), x, y));
+                    w.tile_outputs_west.push_back(ctx->addWire(
+                            h.xy_id(x, y, ctx->id(stringf("TILEOUTW[%d]", tile_output))), ctx->id("TILEOUTW"), x, y));
+                }
+                // Pad wires for IO
+                if (is_io(x, y) && x != y)
+                    for (int z = 0; z < 2; z++)
+                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y));
+            }
+        }
+    }
+    bool is_io(int x, int y) const
+    {
+        // IO are on the edges of the device
+        return (x == 0) || (x == (X - 1)) || (y == 0) || (y == (Y - 1));
+    }
+    // Create IO bels in an IO tile
+    void add_io_bels(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        for (int z = 0; z < 2; z++) {
+            BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false);
+            ctx->addBelInout(b, id_PAD, w.pad.at(z));
+            ctx->addBelInput(b, id_I, w.slice_inputs.at(z * K + 0));
+            ctx->addBelInput(b, id_EN, w.slice_inputs.at(z * K + 1));
+            ctx->addBelOutput(b, id_O, w.slice_outputs.at(z));
+        }
+    }
+    PipId add_pip(Loc loc, WireId src, WireId dst, delay_t delay = 0.05)
+    {
+        IdStringList name = IdStringList::concat(ctx->getWireName(dst), ctx->getWireName(src));
+        return ctx->addPip(name, ctx->id("PIP"), src, dst, delay, loc);
+    }
+    // Create LUT and FF bels in a logic tile
+    void add_slice_bels(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        for (int z = 0; z < N; z++) {
+            // Create LUT bel
+            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false,
+                                    false);
+            for (int k = 0; k < K; k++)
+                ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.slice_inputs.at(z * K + k));
+            ctx->addBelOutput(lut, id_F, w.f.at(z));
+            // FF data can come from LUT output or LUT I3
+            add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
+            add_pip(Loc(x, y, 0), w.slice_inputs.at(z * K + (K - 1)), w.d.at(z));
+            // Create DFF bel
+            BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1),
+                                    false, false);
+            ctx->addBelInput(dff, id_CLK, w.clk.at(z));
+            ctx->addBelInput(dff, id_D, w.d.at(z));
+            ctx->addBelOutput(dff, id_Q, w.q.at(z));
+        }
+    }
+    // Create bels according to tile type
+    void init_bels()
+    {
+        log_info("Creating bels...\n");
+        for (int y = 0; y < Y; y++) {
+            for (int x = 0; x < X; x++) {
+                if (is_io(x, y)) {
+                    if (x == y)
+                        continue; // don't put IO in corners
+                    add_io_bels(x, y);
+                } else {
+                    add_slice_bels(x, y);
+                }
+            }
+        }
+    }
+
+    // Create PIPs inside a tile; following an example synthetic routing pattern
+    void add_io_pips(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        Loc loc(x, y, 0);
+
+        const uint16_t tile_input_config[8] = {
+                0b0000'0000'0000'0001, 0b0000'0000'0000'0001, 0b0000'0000'0000'0001, 0b0000'0000'0000'0001,
+                0b0000'0000'0000'0010, 0b0000'0000'0000'0010, 0b0000'0000'0000'0010, 0b0000'0000'0000'0010,
+        };
+
+        // Tile inputs
+        for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
+            auto &dst = w.tile_inputs_north.at(tile_input);
+            // North
+            for (int step = 1; step <= 4; step++) {
+                if (y - step <= 0 || x == 0 || x == X - 1)
+                    break;
+                auto &w = wires_by_tile.at(y - step).at(x);
+                for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++)
+                    if ((1 << tile_input) & tile_input_config[tile_output])
+                        add_pip(loc, w.tile_outputs_north.at(tile_output), dst);
+            }
+        }
+
+        for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
+            auto &dst = w.tile_inputs_east.at(tile_input);
+            // East
+            for (int step = 1; step <= 4; step++) {
+                if (x - step <= 0 || y == 0 || y == Y - 1)
+                    break;
+                auto &w = wires_by_tile.at(y).at(x - step);
+                for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++)
+                    if ((1 << tile_input) & tile_input_config[tile_output])
+                        add_pip(loc, w.tile_outputs_east.at(tile_output), dst);
+            }
+        }
+
+        for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
+            auto &dst = w.tile_inputs_south.at(tile_input);
+            // South
+            for (int step = 1; step <= 4; step++) {
+                if (y + step >= Y || x == 0 || x == X - 1)
+                    break;
+                auto &w = wires_by_tile.at(y + step).at(x);
+                for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++)
+                    if ((1 << tile_input) & tile_input_config[tile_output])
+                        add_pip(loc, w.tile_outputs_south.at(tile_output), dst);
+            }
+        }
+
+        for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
+            auto &dst = w.tile_inputs_west.at(tile_input);
+            // West
+            for (int step = 1; step <= 4; step++) {
+                if (x + step >= X || y == 0 || y == Y - 1)
+                    break;
+                auto &w = wires_by_tile.at(y).at(x + step);
+                for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++)
+                    if ((1 << tile_input) & tile_input_config[tile_output])
+                        add_pip(loc, w.tile_outputs_west.at(tile_output), dst);
+            }
+        }
+
+        // Tile outputs
+        for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++) {
+            for (int z = 0; z < 2; z++) {
+                WireId src = w.slice_outputs.at(z);
+                // O output
+                if (y == 0)
+                    add_pip(loc, src, w.tile_outputs_north.at(tile_output));
+                if (x == 0)
+                    add_pip(loc, src, w.tile_outputs_east.at(tile_output));
+                if (y == Y - 1)
+                    add_pip(loc, src, w.tile_outputs_south.at(tile_output));
+                if (x == X - 1)
+                    add_pip(loc, src, w.tile_outputs_west.at(tile_output));
+            }
+        }
+
+        // Pad inputs
+        for (const auto &src : w.tile_inputs_north) {
+            for (int z = 0; z < 2; z++) {
+                // I input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 0));
+                // EN input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 1));
+            }
+        }
+        for (const auto &src : w.tile_inputs_east) {
+            for (int z = 0; z < 2; z++) {
+                // I input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 0));
+                // EN input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 1));
+            }
+        }
+        for (const auto &src : w.tile_inputs_south) {
+            for (int z = 0; z < 2; z++) {
+                // I input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 0));
+                // EN input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 1));
+            }
+        }
+        for (const auto &src : w.tile_inputs_west) {
+            for (int z = 0; z < 2; z++) {
+                // I input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 0));
+                // EN input
+                add_pip(loc, src, w.slice_inputs.at(z * K + 1));
+            }
+        }
+    }
+    void add_slice_pips(int x, int y)
+    {
+        auto &w = wires_by_tile.at(y).at(x);
+        Loc loc(x, y, 0);
+
+        const uint16_t tile_input_config[8] = {0b1010'1010'1010'1010, 0b0101'0101'0101'0101, 0b0110'0110'0110'0110,
+                                               0b1001'1001'1001'1001, 0b0011'0011'0011'0011, 0b1100'1100'1100'1100,
+                                               0b1111'0000'1111'0000, 0b0000'1111'0000'1111};
+
+        // Slice input selector
+        for (int lut = 0; lut < N; lut++) {
+            for (int lut_input = 0; lut_input < K; lut_input++) {
+                for (const auto &tile_input : w.tile_inputs_north) // Tile input bus
+                    add_pip(loc, tile_input, w.slice_inputs.at(lut * K + lut_input));
+                for (const auto &tile_input : w.tile_inputs_east) // Tile input bus
+                    add_pip(loc, tile_input, w.slice_inputs.at(lut * K + lut_input));
+                for (const auto &tile_input : w.tile_inputs_south) // Tile input bus
+                    add_pip(loc, tile_input, w.slice_inputs.at(lut * K + lut_input));
+                for (const auto &tile_input : w.tile_inputs_west) // Tile input bus
+                    add_pip(loc, tile_input, w.slice_inputs.at(lut * K + lut_input));
+                for (const auto &slice_output : w.slice_outputs) // Slice output bus
+                    add_pip(loc, slice_output, w.slice_inputs.at(lut * K + lut_input));
+            }
+            for (const auto &tile_input : w.tile_inputs_north) // Clock selector
+                add_pip(loc, tile_input, w.clk.at(lut));
+            for (const auto &tile_input : w.tile_inputs_east) // Clock selector
+                add_pip(loc, tile_input, w.clk.at(lut));
+            for (const auto &tile_input : w.tile_inputs_south) // Clock selector
+                add_pip(loc, tile_input, w.clk.at(lut));
+            for (const auto &tile_input : w.tile_inputs_west) // Clock selector
+                add_pip(loc, tile_input, w.clk.at(lut));
+        }
+
+        // Slice output selector
+        for (int slice_output = 0; slice_output < N; slice_output++) {
+            add_pip(loc, w.f.at(slice_output), w.slice_outputs.at(slice_output)); // LUT output
+            add_pip(loc, w.q.at(slice_output), w.slice_outputs.at(slice_output)); // DFF output
+        }
+
+        // Tile input selector
+        for (int step = 1; step <= 4; step++) {
+            if (y + step < Y) // South
+                for (size_t tile_input_index = 0; tile_input_index < w.tile_inputs_north.size(); tile_input_index++)
+                    for (size_t tile_output_index = 0;
+                         tile_output_index < wires_by_tile.at(y + step).at(x).tile_outputs_south.size();
+                         tile_output_index++)
+                        if ((1 << tile_input_index) & tile_input_config[tile_output_index])
+                            add_pip(loc, wires_by_tile.at(y + step).at(x).tile_outputs_south.at(tile_output_index),
+                                    w.tile_inputs_north.at(tile_input_index));
+
+            if (x + step < X) // West
+                for (size_t tile_input_index = 0; tile_input_index < w.tile_inputs_east.size(); tile_input_index++)
+                    for (size_t tile_output_index = 0;
+                         tile_output_index < wires_by_tile.at(y).at(x + step).tile_outputs_west.size();
+                         tile_output_index++)
+                        if ((1 << tile_input_index) & tile_input_config[tile_output_index])
+                            add_pip(loc, wires_by_tile.at(y).at(x + step).tile_outputs_west.at(tile_output_index),
+                                    w.tile_inputs_east.at(tile_input_index));
+
+            if (y - step >= 0) // North
+                for (size_t tile_input_index = 0; tile_input_index < w.tile_inputs_south.size(); tile_input_index++)
+                    for (size_t tile_output_index = 0;
+                         tile_output_index < wires_by_tile.at(y - step).at(x).tile_outputs_north.size();
+                         tile_output_index++)
+                        if ((1 << tile_input_index) & tile_input_config[tile_output_index])
+                            add_pip(loc, wires_by_tile.at(y - step).at(x).tile_outputs_north.at(tile_output_index),
+                                    w.tile_inputs_south.at(tile_input_index));
+
+            if (x - step >= 0) // East
+                for (size_t tile_input_index = 0; tile_input_index < w.tile_inputs_west.size(); tile_input_index++)
+                    for (size_t tile_output_index = 0;
+                         tile_output_index < wires_by_tile.at(y).at(x - step).tile_outputs_east.size();
+                         tile_output_index++)
+                        if ((1 << tile_input_index) & tile_input_config[tile_output_index])
+                            add_pip(loc, wires_by_tile.at(y).at(x - step).tile_outputs_east.at(tile_output_index),
+                                    w.tile_inputs_west.at(tile_input_index));
+        }
+
+        // Tile output selector
+        for (const auto &slice_output : w.slice_outputs) {
+            for (const auto &tile_output : w.tile_outputs_north)
+                add_pip(loc, slice_output, tile_output);
+            for (const auto &tile_output : w.tile_outputs_east)
+                add_pip(loc, slice_output, tile_output);
+            for (const auto &tile_output : w.tile_outputs_south)
+                add_pip(loc, slice_output, tile_output);
+            for (const auto &tile_output : w.tile_outputs_west)
+                add_pip(loc, slice_output, tile_output);
+        }
+
+        for (const auto &tile_input : w.tile_inputs_north) {
+            for (const auto &tile_output : w.tile_outputs_north)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_east)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_south)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_west)
+                add_pip(loc, tile_input, tile_output);
+        }
+        for (const auto &tile_input : w.tile_inputs_east) {
+            for (const auto &tile_output : w.tile_outputs_north)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_east)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_south)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_west)
+                add_pip(loc, tile_input, tile_output);
+        }
+        for (const auto &tile_input : w.tile_inputs_south) {
+            for (const auto &tile_output : w.tile_outputs_north)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_east)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_south)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_west)
+                add_pip(loc, tile_input, tile_output);
+        }
+        for (const auto &tile_input : w.tile_inputs_west) {
+            for (const auto &tile_output : w.tile_outputs_north)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_east)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_south)
+                add_pip(loc, tile_input, tile_output);
+            for (const auto &tile_output : w.tile_outputs_west)
+                add_pip(loc, tile_input, tile_output);
+        }
+    }
+    void init_pips()
+    {
+        log_info("Creating pips...\n");
+        for (int y = 0; y < Y; y++)
+            for (int x = 0; x < X; x++) {
+                if (is_io(x, y)) {
+                    add_io_pips(x, y);
+                } else {
+                    add_slice_pips(x, y);
+                }
+            }
+    }
+    // Validity checking
+    struct OkamiCellInfo
+    {
+        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+        bool lut_i3_used = false;
+    };
+    std::vector<OkamiCellInfo> fast_cell_info;
+    void assign_cell_info()
+    {
+        fast_cell_info.resize(ctx->cells.size());
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto &fc = fast_cell_info.at(ci->flat_index);
+            if (ci->type == id_LUT4) {
+                fc.lut_f = ci->getPort(id_F);
+                fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+            } else if (ci->type == id_DFF) {
+                fc.ff_d = ci->getPort(id_D);
+            }
+        }
+    }
+    bool slice_valid(int x, int y, int z) const
+    {
+        const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+        const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+        if (!lut || !ff)
+            return true; // always valid if only LUT or FF used
+        const auto &lut_data = fast_cell_info.at(lut->flat_index);
+        const auto &ff_data = fast_cell_info.at(ff->flat_index);
+        // In our example arch; the FF D can either be driven from LUT F or LUT I3
+        // so either; FF D must equal LUT F or LUT I3 must be unused
+        if (ff_data.ff_d == lut_data.lut_f && lut_data.lut_f->users.size() == 1)
+            return true;
+        // Can't route FF and LUT output separately
+        return false;
+    }
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override
+    {
+        if (cell_type.in(id_INBUF, id_OUTBUF))
+            return id_IOB;
+        return cell_type;
+    }
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        IdString bel_type = ctx->getBelType(bel);
+        if (bel_type == id_IOB)
+            return cell_type.in(id_INBUF, id_OUTBUF);
+        else
+            return (bel_type == cell_type);
+    }
+};
+
+struct OkamiArch : ViaductArch
+{
+    OkamiArch() : ViaductArch("okami"){};
+    std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<OkamiImpl>();
+    }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/okami/okami_map.v b/generic/viaduct/okami/okami_map.v
new file mode 100644
index 0000000000..f701f0ed7a
--- /dev/null
+++ b/generic/viaduct/okami/okami_map.v
@@ -0,0 +1,12 @@
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+	input [WIDTH-1:0] A;
+	output Y;
+
+	localparam rep = 1<<(4-WIDTH);
+
+	LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .F(Y));
+endmodule
+
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
diff --git a/generic/viaduct/okami/okami_prims.v b/generic/viaduct/okami/okami_prims.v
new file mode 100644
index 0000000000..d2813129b4
--- /dev/null
+++ b/generic/viaduct/okami/okami_prims.v
@@ -0,0 +1,35 @@
+module LUT4 #(
+    parameter [15:0] INIT = 0
+) (
+    input [3:0] I,
+    output F
+);
+    wire [7:0] s3 = I[3] ?     INIT[15:8] :     INIT[7:0];
+    wire [3:0] s2 = I[2] ?       s3[ 7:4] :       s3[3:0];
+    wire [1:0] s1 = I[1] ?       s2[ 3:2] :       s2[1:0];
+    assign F = I[0] ? s1[1] : s1[0];
+endmodule
+
+module DFF (
+    input CLK, D,
+    output reg Q
+);
+    initial Q = 1'b0;
+    always @(posedge CLK)
+        Q <= D;
+endmodule
+
+module INBUF (
+    input PAD,
+    output O,
+);
+    assign O = PAD;
+endmodule
+
+module OUTBUF (
+    output PAD,
+    input I,
+);
+    assign PAD = I;
+endmodule
+
diff --git a/generic/viaduct/okami/synth_okami.tcl b/generic/viaduct/okami/synth_okami.tcl
new file mode 100644
index 0000000000..1a0212eb54
--- /dev/null
+++ b/generic/viaduct/okami/synth_okami.tcl
@@ -0,0 +1,24 @@
+# Usage
+# tcl synth_okami.tcl {out.json}
+
+yosys read_verilog -lib [file dirname [file normalize $argv0]]/okami_prims.v
+yosys hierarchy -check -top top
+yosys proc
+yosys flatten
+yosys tribuf -logic
+yosys deminout
+yosys synth -run coarse
+yosys memory_map
+yosys opt -full
+yosys iopadmap -bits -inpad INBUF O:PAD -outpad OUTBUF I:PAD
+yosys techmap -map +/techmap.v
+yosys opt -fast
+yosys dfflegalize -cell \$_DFF_P_ 0
+yosys abc -lut 4 -dress
+yosys clean
+yosys techmap -map [file dirname [file normalize $argv0]]/okami_map.v
+yosys clean
+yosys hierarchy -check
+yosys stat
+
+if {$argc > 0} { yosys write_json [lindex $argv 0] }
diff --git a/generic/viaduct/okami/viaduct_example.sh b/generic/viaduct/okami/viaduct_example.sh
new file mode 100755
index 0000000000..5a49dc10fd
--- /dev/null
+++ b/generic/viaduct/okami/viaduct_example.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -ex
+# Run synthesis
+yosys -p "tcl synth_okami.tcl blinky.json" ../../examples/blinky.v
+# Run PnR
+${NEXTPNR:-../../../build/nextpnr-generic} --uarch okami --json blinky.json --router router2

From 434a9737bb459189b463c8768454ea6c0e151406 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 26 Feb 2022 15:11:33 +0000
Subject: [PATCH 074/712] Add indexed_store container type

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/indexed_store.h | 266 +++++++++++++++++++++++++++++++++++++++++
 common/nextpnr_types.h |   1 +
 2 files changed, 267 insertions(+)
 create mode 100644 common/indexed_store.h

diff --git a/common/indexed_store.h b/common/indexed_store.h
new file mode 100644
index 0000000000..5579b039fb
--- /dev/null
+++ b/common/indexed_store.h
@@ -0,0 +1,266 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef INDEXED_STORE_H
+#define INDEXED_STORE_H
+
+#include <algorithm>
+#include <limits>
+#include <vector>
+
+#include "nextpnr_assertions.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+template <typename T> struct store_index
+{
+    int32_t m_index = -1;
+    store_index() = default;
+    explicit store_index(int32_t index) : m_index(index){};
+    int32_t idx() const { return m_index; }
+    void set(int32_t index) { m_index = index; }
+    bool empty() const { return m_index == -1; }
+    bool operator==(const store_index<T> &other) const { return m_index == other.m_index; }
+    bool operator!=(const store_index<T> &other) const { return m_index != other.m_index; }
+    bool operator<(const store_index<T> &other) const { return m_index < other.m_index; }
+    unsigned int hash() const { return m_index; }
+
+    operator bool() const { return !empty(); }
+    bool operator!() const { return empty(); }
+};
+
+// "Slotted" indexed object store
+template <typename T> class indexed_store
+{
+  private:
+    // This should move to using std::optional at some point
+    class slot
+    {
+      private:
+        alignas(T) unsigned char storage[sizeof(T)];
+        int32_t next_free;
+        bool active;
+        inline T &obj() { return reinterpret_cast<T &>(storage); }
+        inline const T &obj() const { return reinterpret_cast<const T &>(storage); }
+        friend class indexed_store<T>;
+
+      public:
+        slot() : active(false), next_free(std::numeric_limits<int32_t>::max()){};
+        slot(slot &&other) : active(other.active), next_free(other.next_free)
+        {
+            if (active)
+                ::new (static_cast<void *>(&storage)) T(std::move(other.obj()));
+        };
+
+        template <class... Args> void create(Args &&...args)
+        {
+            NPNR_ASSERT(!active);
+            active = true;
+            ::new (static_cast<void *>(&storage)) T(std::forward<Args &&>(args)...);
+        }
+        bool empty() const { return !active; }
+        T &get()
+        {
+            NPNR_ASSERT(active);
+            return reinterpret_cast<T &>(storage);
+        }
+        const T &get() const
+        {
+            NPNR_ASSERT(active);
+            return reinterpret_cast<const T &>(storage);
+        }
+        void free(int32_t first_free)
+        {
+            NPNR_ASSERT(active);
+            obj().~T();
+            active = false;
+            next_free = first_free;
+        }
+        ~slot()
+        {
+            if (active)
+                obj().~T();
+        }
+    };
+
+    std::vector<slot> slots;
+    int32_t first_free = 0;
+    int32_t active_count = 0;
+
+  public:
+    // Create a new entry and return its index
+    template <class... Args> store_index<T> add(Args &&...args)
+    {
+        ++active_count;
+        if (first_free == int32_t(slots.size())) {
+            slots.emplace_back();
+            slots.back().create(std::forward<Args &&>(args)...);
+            ++first_free;
+            return store_index<T>(int32_t(slots.size()) - 1);
+        } else {
+            int32_t idx = first_free;
+            auto &slot = slots.at(idx);
+            first_free = slot.next_free;
+            slot.create(std::forward<Args &&>(args)...);
+            return store_index<T>(idx);
+        }
+    }
+
+    // Remove an entry at an index
+    void remove(store_index<T> idx)
+    {
+        --active_count;
+        slots.at(idx.m_index).free(first_free);
+        first_free = idx.m_index;
+    }
+
+    // Number of live entries
+    int32_t entries() const { return active_count; }
+
+    // Reserve a certain amount of space
+    void reserve(int32_t size) { slots.reserve(size); }
+
+    // Check if an index exists
+    int32_t count(store_index<T> idx)
+    {
+        if (idx.m_index < 0 || idx.m_index >= int32_t(slots.size()))
+            return 0;
+        return slots.at(idx.m_index).empty() ? 0 : 1;
+    }
+
+    // Get an item by index
+    T &at(store_index<T> idx) { return slots.at(idx.m_index).get(); }
+    const T &at(store_index<T> idx) const { return slots.at(idx.m_index).get(); }
+    T &operator[](store_index<T> idx) { return slots.at(idx.m_index).get(); }
+    const T &operator[](store_index<T> idx) const { return slots.at(idx.m_index).get(); }
+
+    // Total size of the container
+    int32_t capacity() const { return int32_t(slots.size()); }
+
+    // Iterate over items
+    class iterator
+    {
+      private:
+        indexed_store *base;
+        int32_t index = 0;
+
+      public:
+        iterator(indexed_store *base, int32_t index) : base(base), index(index){};
+        inline bool operator!=(const iterator &other) const { return other.index != index; }
+        inline bool operator==(const iterator &other) const { return other.index == index; }
+        inline iterator operator++()
+        {
+            // skip over unused slots
+            do {
+                index++;
+            } while (index < int32_t(base->slots.size()) && !base->slots.at(index).active);
+            return *this;
+        }
+        inline iterator operator++(int)
+        {
+            iterator prior(*this);
+            do {
+                index++;
+            } while (index < int32_t(base->slots.size()) && !base->slots.at(index).active);
+            return prior;
+        }
+        T &operator*() { return base->at(store_index<T>(index)); }
+        template <typename It, typename S> friend class enumerated_iterator;
+    };
+    iterator begin() { return iterator{this, 0}; }
+    iterator end() { return iterator{this, int32_t(slots.size())}; }
+
+    class const_iterator
+    {
+      private:
+        const indexed_store *base;
+        int32_t index = 0;
+
+      public:
+        const_iterator(const indexed_store *base, int32_t index) : base(base), index(index){};
+        inline bool operator!=(const const_iterator &other) const { return other.index != index; }
+        inline bool operator==(const const_iterator &other) const { return other.index == index; }
+        inline const_iterator operator++()
+        {
+            // skip over unused slots
+            do {
+                index++;
+            } while (index < int32_t(base->slots.size()) && !base->slots.at(index).active);
+            return *this;
+        }
+        inline const_iterator operator++(int)
+        {
+            iterator prior(*this);
+            do {
+                index++;
+            } while (index < int32_t(base->slots.size()) && !base->slots.at(index).active);
+            return prior;
+        }
+        const T &operator*() { return base->at(store_index<T>(index)); }
+        template <typename It, typename S> friend class enumerated_iterator;
+    };
+    const_iterator begin() const { return const_iterator{this, 0}; }
+    const_iterator end() const { return const_iterator{this, int32_t(slots.size())}; }
+
+    template <typename S> struct enumerated_item
+    {
+        enumerated_item(int32_t index, T &value) : index(index), value(value){};
+        store_index<std::remove_const<S>> index;
+        S &value;
+    };
+
+    template <typename It, typename S> class enumerated_iterator
+    {
+      private:
+        It base;
+
+      public:
+        enumerated_iterator(const It &base) : base(base){};
+        inline bool operator!=(const enumerated_iterator<It, S> &other) const { return other.base != base; }
+        inline bool operator==(const enumerated_iterator<It, S> &other) const { return other.base == base; }
+        inline enumerated_iterator<It, S> operator++()
+        {
+            ++base;
+            return *this;
+        }
+        inline enumerated_iterator<It, S> operator++(int)
+        {
+            iterator prior(*this);
+            ++base;
+            return prior;
+        }
+        enumerated_item<S> operator*() { return enumerated_item<S>{base.index, *base}; }
+    };
+
+    template <typename It, typename S> struct enumerated_range
+    {
+        enumerated_range(const It &begin, const It &end) : m_begin(begin), m_end(end){};
+        enumerated_iterator<It, S> m_begin, m_end;
+        enumerated_iterator<It, S> begin() { return m_begin; }
+        enumerated_iterator<It, S> end() { return m_end; }
+    };
+
+    enumerated_range<iterator, T> enumerate() { return enumerated_range<iterator, T>{begin(), end()}; }
+    enumerated_range<const_iterator, const T> enumerate() const { return enumerated_range<iterator, T>{begin(), end()}; }
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index cf93a0714d..4e5432cedd 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -29,6 +29,7 @@
 
 #include "archdefs.h"
 #include "hashlib.h"
+#include "indexed_store.h"
 #include "nextpnr_base_types.h"
 #include "nextpnr_namespaces.h"
 #include "property.h"

From 86699b42f619960bfefd4d0b479dd44a90527ea4 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 26 Feb 2022 15:17:46 +0000
Subject: [PATCH 075/712] Switch to potentially-sparse net users array

This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/context.cc                      |  14 +--
 common/design_utils.h                  |  14 ++-
 common/indexed_store.h                 |  47 +++++++--
 common/nextpnr_types.cc                |  25 ++---
 common/nextpnr_types.h                 |   3 +-
 common/placer1.cc                      |  68 +++++-------
 common/placer_heap.cc                  |  14 +--
 common/pybindings.cc                   |   4 +-
 common/pycontainers.h                  |  57 ++++++++++
 common/router1.cc                      |  62 ++++++-----
 common/router2.cc                      | 139 +++++++++++++------------
 common/timing.cc                       |  10 +-
 common/timing.h                        |  23 ----
 common/timing_opt.cc                   |  65 ++++--------
 ecp5/cells.cc                          |   7 +-
 ecp5/globals.cc                        |  22 ++--
 ecp5/pack.cc                           |  56 +++++-----
 fpga_interchange/arch.cc               |   4 +-
 fpga_interchange/arch_pack_clusters.cc |   6 +-
 fpga_interchange/globals.cc            |  26 ++---
 frontend/frontend_base.h               |   2 +-
 generic/cells.cc                       |   2 +-
 generic/pack.cc                        |   7 +-
 generic/viaduct/okami/okami.cc         |   2 +-
 generic/viaduct_helpers.cc             |   4 +-
 gowin/pack.cc                          |  11 +-
 ice40/bitstream.cc                     |   2 +-
 ice40/cells.cc                         |   2 +-
 ice40/chains.cc                        |  61 +++--------
 ice40/pack.cc                          |  81 +++++++-------
 machxo2/pack.cc                        |   2 +-
 mistral/pack.cc                        |  14 +--
 nexus/global.cc                        |   8 +-
 nexus/pack.cc                          |  43 ++++----
 34 files changed, 442 insertions(+), 465 deletions(-)

diff --git a/common/context.cc b/common/context.cc
index faddf82595..e35d3e49ae 100644
--- a/common/context.cc
+++ b/common/context.cc
@@ -334,13 +334,13 @@ void Context::check() const
                                    nameOf(port.first), nameOf(net));
                     }
                 } else if (port.second.type == PORT_IN) {
-                    int usr_count = std::count_if(net->users.begin(), net->users.end(), [&](const PortRef &pr) {
-                        return pr.cell == c.second.get() && pr.port == port.first;
-                    });
-                    if (usr_count != 1)
-                        CHECK_FAIL("input cell port '%s.%s' appears %d rather than expected 1 times in users vector of "
-                                   "net '%s'\n",
-                                   nameOf(c.first), nameOf(port.first), usr_count, nameOf(net));
+                    if (!port.second.user_idx)
+                        CHECK_FAIL("input cell port '%s.%s' on net '%s' has no user index\n", nameOf(c.first),
+                                   nameOf(port.first), nameOf(net));
+                    auto net_user = net->users.at(port.second.user_idx);
+                    if (net_user.cell != c.second.get() || net_user.port != port.first)
+                        CHECK_FAIL("input cell port '%s.%s' not in associated user entry of net '%s'\n",
+                                   nameOf(c.first), nameOf(port.first), nameOf(net));
                 }
             }
         }
diff --git a/common/design_utils.h b/common/design_utils.h
index 63cb71d7b3..069600b548 100644
--- a/common/design_utils.h
+++ b/common/design_utils.h
@@ -47,14 +47,18 @@ CellInfo *net_only_drives(const Context *ctx, NetInfo *net, F1 cell_pred, IdStri
         return nullptr;
     if (exclusive) {
         if (exclude == nullptr) {
-            if (net->users.size() != 1)
+            if (net->users.entries() != 1)
                 return nullptr;
         } else {
-            if (net->users.size() > 2) {
+            if (net->users.entries() > 2) {
                 return nullptr;
-            } else if (net->users.size() == 2) {
-                if (std::find_if(net->users.begin(), net->users.end(),
-                                 [exclude](const PortRef &ref) { return ref.cell == exclude; }) == net->users.end())
+            } else if (net->users.entries() == 2) {
+                bool found = false;
+                for (auto &usr : net->users) {
+                    if (usr.cell == exclude)
+                        found = true;
+                }
+                if (!found)
                     return nullptr;
             }
         }
diff --git a/common/indexed_store.h b/common/indexed_store.h
index 5579b039fb..df607c13de 100644
--- a/common/indexed_store.h
+++ b/common/indexed_store.h
@@ -22,6 +22,7 @@
 
 #include <algorithm>
 #include <limits>
+#include <type_traits>
 #include <vector>
 
 #include "nextpnr_assertions.h"
@@ -43,6 +44,7 @@ template <typename T> struct store_index
     unsigned int hash() const { return m_index; }
 
     operator bool() const { return !empty(); }
+    operator int() const = delete;
     bool operator!() const { return empty(); }
 };
 
@@ -62,13 +64,19 @@ template <typename T> class indexed_store
         friend class indexed_store<T>;
 
       public:
-        slot() : active(false), next_free(std::numeric_limits<int32_t>::max()){};
-        slot(slot &&other) : active(other.active), next_free(other.next_free)
+        slot() : next_free(std::numeric_limits<int32_t>::max()), active(false){};
+        slot(slot &&other) : next_free(other.next_free), active(other.active)
         {
             if (active)
                 ::new (static_cast<void *>(&storage)) T(std::move(other.obj()));
         };
 
+        slot(const slot &other) : next_free(other.next_free), active(other.active)
+        {
+            if (active)
+                ::new (static_cast<void *>(&storage)) T(other.obj());
+        };
+
         template <class... Args> void create(Args &&...args)
         {
             NPNR_ASSERT(!active);
@@ -131,8 +139,16 @@ template <typename T> class indexed_store
         first_free = idx.m_index;
     }
 
+    void clear()
+    {
+        active_count = 0;
+        first_free = 0;
+        slots.clear();
+    }
+
     // Number of live entries
     int32_t entries() const { return active_count; }
+    bool empty() const { return (entries() == 0); }
 
     // Reserve a certain amount of space
     void reserve(int32_t size) { slots.reserve(size); }
@@ -155,6 +171,8 @@ template <typename T> class indexed_store
     int32_t capacity() const { return int32_t(slots.size()); }
 
     // Iterate over items
+    template <typename It, typename S> class enumerated_iterator;
+
     class iterator
     {
       private:
@@ -182,9 +200,14 @@ template <typename T> class indexed_store
             return prior;
         }
         T &operator*() { return base->at(store_index<T>(index)); }
-        template <typename It, typename S> friend class enumerated_iterator;
+        template <typename It, typename S> friend class indexed_store::enumerated_iterator;
     };
-    iterator begin() { return iterator{this, 0}; }
+    iterator begin()
+    {
+        auto it = iterator{this, -1};
+        ++it;
+        return it;
+    }
     iterator end() { return iterator{this, int32_t(slots.size())}; }
 
     class const_iterator
@@ -214,15 +237,20 @@ template <typename T> class indexed_store
             return prior;
         }
         const T &operator*() { return base->at(store_index<T>(index)); }
-        template <typename It, typename S> friend class enumerated_iterator;
+        template <typename It, typename S> friend class indexed_store::enumerated_iterator;
     };
-    const_iterator begin() const { return const_iterator{this, 0}; }
+    const_iterator begin() const
+    {
+        auto it = const_iterator{this, -1};
+        ++it;
+        return it;
+    }
     const_iterator end() const { return const_iterator{this, int32_t(slots.size())}; }
 
     template <typename S> struct enumerated_item
     {
         enumerated_item(int32_t index, T &value) : index(index), value(value){};
-        store_index<std::remove_const<S>> index;
+        store_index<std::remove_cv_t<S>> index;
         S &value;
     };
 
@@ -258,7 +286,10 @@ template <typename T> class indexed_store
     };
 
     enumerated_range<iterator, T> enumerate() { return enumerated_range<iterator, T>{begin(), end()}; }
-    enumerated_range<const_iterator, const T> enumerate() const { return enumerated_range<iterator, T>{begin(), end()}; }
+    enumerated_range<const_iterator, const T> enumerate() const
+    {
+        return enumerated_range<iterator, T>{begin(), end()};
+    }
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/nextpnr_types.cc b/common/nextpnr_types.cc
index c89a007102..57d816c008 100644
--- a/common/nextpnr_types.cc
+++ b/common/nextpnr_types.cc
@@ -66,7 +66,7 @@ void CellInfo::connectPort(IdString port_name, NetInfo *net)
         PortRef user;
         user.cell = this;
         user.port = port_name;
-        net->users.push_back(user);
+        port.user_idx = net->users.add(user);
     } else {
         NPNR_ASSERT_FALSE("invalid port type for connect_port");
     }
@@ -78,11 +78,8 @@ void CellInfo::disconnectPort(IdString port_name)
         return;
     PortInfo &port = ports.at(port_name);
     if (port.net != nullptr) {
-        port.net->users.erase(std::remove_if(port.net->users.begin(), port.net->users.end(),
-                                             [this, port_name](const PortRef &user) {
-                                                 return user.cell == this && user.port == port_name;
-                                             }),
-                              port.net->users.end());
+        if (port.user_idx)
+            port.net->users.remove(port.user_idx);
         if (port.net->driver.cell == this && port.net->driver.port == port_name)
             port.net->driver.cell = nullptr;
         port.net = nullptr;
@@ -116,7 +113,9 @@ void CellInfo::movePortTo(IdString port, CellInfo *other, IdString other_port)
     NPNR_ASSERT(old.type == rep.type);
 
     rep.net = old.net;
+    rep.user_idx = old.user_idx;
     old.net = nullptr;
+    old.user_idx = store_index<PortRef>{};
     if (rep.type == PORT_OUT) {
         if (rep.net != nullptr) {
             rep.net->driver.cell = other;
@@ -124,12 +123,9 @@ void CellInfo::movePortTo(IdString port, CellInfo *other, IdString other_port)
         }
     } else if (rep.type == PORT_IN) {
         if (rep.net != nullptr) {
-            for (PortRef &load : rep.net->users) {
-                if (load.cell == this && load.port == port) {
-                    load.cell = other;
-                    load.port = other_port;
-                }
-            }
+            auto &load = rep.net->users.at(rep.user_idx);
+            load.cell = other;
+            load.port = other_port;
         }
     } else {
         NPNR_ASSERT(false);
@@ -144,9 +140,8 @@ void CellInfo::renamePort(IdString old_name, IdString new_name)
     if (pi.net != nullptr) {
         if (pi.net->driver.cell == this && pi.net->driver.port == old_name)
             pi.net->driver.port = new_name;
-        for (auto &usr : pi.net->users)
-            if (usr.cell == this && usr.port == old_name)
-                usr.port = new_name;
+        if (pi.user_idx)
+            pi.net->users.at(pi.user_idx).port = new_name;
     }
     ports.erase(old_name);
     pi.name = new_name;
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index 4e5432cedd..c21182cc97 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -130,7 +130,7 @@ struct NetInfo : ArchNetInfo
     int32_t udata = 0;
 
     PortRef driver;
-    std::vector<PortRef> users;
+    indexed_store<PortRef> users;
     dict<IdString, Property> attrs;
 
     // wire -> uphill_pip
@@ -155,6 +155,7 @@ struct PortInfo
     IdString name;
     NetInfo *net;
     PortType type;
+    store_index<PortRef> user_idx{};
 };
 
 struct Context;
diff --git a/common/placer1.cc b/common/placer1.cc
index 6de035b444..a6ba389504 100644
--- a/common/placer1.cc
+++ b/common/placer1.cc
@@ -91,7 +91,7 @@ class SAPlacer
         decltype(NetInfo::udata) n = 0;
         for (auto &net : ctx->nets) {
             old_udata.emplace_back(net.second->udata);
-            net_arc_tcost.at(n).resize(net.second->users.size());
+            net_arc_tcost.at(n).resize(net.second->users.capacity());
             net.second->udata = n++;
             net_by_udata.push_back(net.second.get());
         }
@@ -118,7 +118,6 @@ class SAPlacer
             }
             region_bounds[r->name] = bb;
         }
-        build_port_index();
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->cluster == ClusterId())
@@ -858,7 +857,7 @@ class SAPlacer
     }
 
     // Get the timing cost for an arc of a net
-    inline double get_timing_cost(NetInfo *net, size_t user)
+    inline double get_timing_cost(NetInfo *net, const PortRef &user)
     {
         int cc;
         if (net->driver.cell == nullptr)
@@ -866,11 +865,11 @@ class SAPlacer
         if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
             return 0;
         if (cfg.budgetBased) {
-            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
-            return std::min(10.0, std::exp(delay - ctx->getDelayNS(net->users.at(user).budget) / 10));
+            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
+            return std::min(10.0, std::exp(delay - ctx->getDelayNS(user.budget) / 10));
         } else {
-            float crit = tmg.get_criticality(CellPortKey(net->users.at(user)));
-            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
+            float crit = tmg.get_criticality(CellPortKey(user));
+            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
             return delay * std::pow(crit, crit_exp);
         }
     }
@@ -883,9 +882,9 @@ class SAPlacer
             if (ignore_net(ni))
                 continue;
             net_bounds[ni->udata] = get_net_bounds(ni);
-            if (cfg.timing_driven && int(ni->users.size()) < cfg.timingFanoutThresh)
-                for (size_t i = 0; i < ni->users.size(); i++)
-                    net_arc_tcost[ni->udata][i] = get_timing_cost(ni, i);
+            if (cfg.timing_driven && int(ni->users.entries()) < cfg.timingFanoutThresh)
+                for (auto usr : ni->users.enumerate())
+                    net_arc_tcost[ni->udata][usr.index.idx()] = get_timing_cost(ni, usr.value);
         }
     }
 
@@ -923,13 +922,13 @@ class SAPlacer
         };
 
         std::vector<decltype(NetInfo::udata)> bounds_changed_nets_x, bounds_changed_nets_y;
-        std::vector<std::pair<decltype(NetInfo::udata), size_t>> changed_arcs;
+        std::vector<std::pair<decltype(NetInfo::udata), store_index<PortRef>>> changed_arcs;
 
         std::vector<BoundChangeType> already_bounds_changed_x, already_bounds_changed_y;
         std::vector<std::vector<bool>> already_changed_arcs;
 
         std::vector<BoundingBox> new_net_bounds;
-        std::vector<std::pair<std::pair<decltype(NetInfo::udata), size_t>, double>> new_arc_costs;
+        std::vector<std::pair<std::pair<decltype(NetInfo::udata), store_index<PortRef>>, double>> new_arc_costs;
 
         wirelen_t wirelen_delta = 0;
         double timing_delta = 0;
@@ -940,7 +939,7 @@ class SAPlacer
             already_bounds_changed_y.resize(p->ctx->nets.size());
             already_changed_arcs.resize(p->ctx->nets.size());
             for (auto &net : p->ctx->nets) {
-                already_changed_arcs.at(net.second->udata).resize(net.second->users.size());
+                already_changed_arcs.at(net.second->udata).resize(net.second->users.capacity());
             }
             new_net_bounds = p->net_bounds;
         }
@@ -956,7 +955,7 @@ class SAPlacer
                 already_bounds_changed_y[bc] = NO_CHANGE;
             }
             for (const auto &tc : changed_arcs)
-                already_changed_arcs[tc.first][tc.second] = false;
+                already_changed_arcs[tc.first][tc.second.idx()] = false;
             bounds_changed_nets_x.clear();
             bounds_changed_nets_y.clear();
             changed_arcs.clear();
@@ -1100,22 +1099,22 @@ class SAPlacer
                 }
             }
 
-            if (cfg.timing_driven && int(pn->users.size()) < cfg.timingFanoutThresh) {
+            if (cfg.timing_driven && int(pn->users.entries()) < cfg.timingFanoutThresh) {
                 // Output ports - all arcs change timing
                 if (port.second.type == PORT_OUT) {
                     int cc;
                     TimingPortClass cls = ctx->getPortTimingClass(cell, port.first, cc);
                     if (cls != TMG_IGNORE)
-                        for (size_t i = 0; i < pn->users.size(); i++)
-                            if (!mc.already_changed_arcs[pn->udata][i]) {
-                                mc.changed_arcs.emplace_back(std::make_pair(pn->udata, i));
-                                mc.already_changed_arcs[pn->udata][i] = true;
+                        for (auto usr : pn->users.enumerate())
+                            if (!mc.already_changed_arcs[pn->udata][usr.index.idx()]) {
+                                mc.changed_arcs.emplace_back(std::make_pair(pn->udata, usr.index));
+                                mc.already_changed_arcs[pn->udata][usr.index.idx()] = true;
                             }
                 } else if (port.second.type == PORT_IN) {
-                    auto usr = fast_port_to_user.at(std::make_pair(cell->name, port.first));
-                    if (!mc.already_changed_arcs[pn->udata][usr]) {
-                        mc.changed_arcs.emplace_back(std::make_pair(pn->udata, usr));
-                        mc.already_changed_arcs[pn->udata][usr] = true;
+                    auto usr_idx = port.second.user_idx;
+                    if (!mc.already_changed_arcs[pn->udata][usr_idx.idx()]) {
+                        mc.changed_arcs.emplace_back(std::make_pair(pn->udata, usr_idx));
+                        mc.already_changed_arcs[pn->udata][usr_idx.idx()] = true;
                     }
                 }
             }
@@ -1142,11 +1141,12 @@ class SAPlacer
 
         if (cfg.timing_driven) {
             for (const auto &tc : md.changed_arcs) {
-                double old_cost = net_arc_tcost.at(tc.first).at(tc.second);
-                double new_cost = get_timing_cost(net_by_udata.at(tc.first), tc.second);
+                double old_cost = net_arc_tcost.at(tc.first).at(tc.second.idx());
+                double new_cost =
+                        get_timing_cost(net_by_udata.at(tc.first), net_by_udata.at(tc.first)->users.at(tc.second));
                 md.new_arc_costs.emplace_back(std::make_pair(tc, new_cost));
                 md.timing_delta += (new_cost - old_cost);
-                md.already_changed_arcs[tc.first][tc.second] = false;
+                md.already_changed_arcs[tc.first][tc.second.idx()] = false;
             }
         }
     }
@@ -1158,21 +1158,10 @@ class SAPlacer
         for (const auto &bc : md.bounds_changed_nets_y)
             net_bounds[bc] = md.new_net_bounds[bc];
         for (const auto &tc : md.new_arc_costs)
-            net_arc_tcost[tc.first.first].at(tc.first.second) = tc.second;
+            net_arc_tcost[tc.first.first].at(tc.first.second.idx()) = tc.second;
         curr_wirelen_cost += md.wirelen_delta;
         curr_timing_cost += md.timing_delta;
     }
-    // Build the cell port -> user index
-    void build_port_index()
-    {
-        for (auto &net : ctx->nets) {
-            NetInfo *ni = net.second.get();
-            for (size_t i = 0; i < ni->users.size(); i++) {
-                auto &usr = ni->users.at(i);
-                fast_port_to_user[std::make_pair(usr.cell->name, usr.port)] = i;
-            }
-        }
-    }
 
     // Simple routeability driven placement
     const int large_cell_thresh = 50;
@@ -1240,9 +1229,6 @@ class SAPlacer
     // Map net arcs to their timing cost (criticality * delay ns)
     std::vector<std::vector<double>> net_arc_tcost;
 
-    // Fast lookup for cell port to net user index
-    dict<std::pair<IdString, IdString>, size_t> fast_port_to_user;
-
     // Fast lookup for cell to clusters
     dict<ClusterId, std::vector<CellInfo *>> cluster2cell;
 
diff --git a/common/placer_heap.cc b/common/placer_heap.cc
index f8385cef33..5b43dc7257 100644
--- a/common/placer_heap.cc
+++ b/common/placer_heap.cc
@@ -655,9 +655,9 @@ class HeAPPlacer
     template <typename Tf> void foreach_port(NetInfo *net, Tf func)
     {
         if (net->driver.cell != nullptr)
-            func(net->driver, -1);
-        for (size_t i = 0; i < net->users.size(); i++)
-            func(net->users.at(i), i);
+            func(net->driver, store_index<PortRef>());
+        for (auto usr : net->users.enumerate())
+            func(usr.value, usr.index);
     }
 
     // Build the system of equations for either X or Y
@@ -682,7 +682,7 @@ class HeAPPlacer
             // Find the bounds of the net in this axis, and the ports that correspond to these bounds
             PortRef *lbport = nullptr, *ubport = nullptr;
             int lbpos = std::numeric_limits<int>::max(), ubpos = std::numeric_limits<int>::min();
-            foreach_port(ni, [&](PortRef &port, int user_idx) {
+            foreach_port(ni, [&](PortRef &port, store_index<PortRef> user_idx) {
                 int pos = cell_pos(port.cell);
                 if (pos < lbpos) {
                     lbpos = pos;
@@ -713,17 +713,17 @@ class HeAPPlacer
             };
 
             // Add all relevant connections to the matrix
-            foreach_port(ni, [&](PortRef &port, int user_idx) {
+            foreach_port(ni, [&](PortRef &port, store_index<PortRef> user_idx) {
                 int this_pos = cell_pos(port.cell);
                 auto process_arc = [&](PortRef *other) {
                     if (other == &port)
                         return;
                     int o_pos = cell_pos(other->cell);
-                    double weight = 1.0 / (ni->users.size() *
+                    double weight = 1.0 / (ni->users.entries() *
                                            std::max<double>(1, (yaxis ? cfg.hpwl_scale_y : cfg.hpwl_scale_x) *
                                                                        std::abs(o_pos - this_pos)));
 
-                    if (user_idx != -1) {
+                    if (user_idx) {
                         weight *= (1.0 + cfg.timingWeight * std::pow(tmg.get_criticality(CellPortKey(port)),
                                                                      cfg.criticalityExponent));
                     }
diff --git a/common/pybindings.cc b/common/pybindings.cc
index eef460ce11..9a783eb41d 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -220,7 +220,7 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
     readwrite_wrapper<PortInfo &, decltype(&PortInfo::type), &PortInfo::type, pass_through<PortType>,
                       pass_through<PortType>>::def_wrap(pi_cls, "type");
 
-    typedef std::vector<PortRef> PortRefVector;
+    typedef indexed_store<PortRef> PortRefVector;
     typedef dict<WireId, PipMap> WireMap;
     typedef pool<BelId> BelSet;
     typedef pool<WireId> WireSet;
@@ -288,7 +288,7 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
     WRAP_MAP(m, WireMap, wrap_context<PipMap &>, "WireMap");
     WRAP_MAP_UPTR(m, RegionMap, "RegionMap");
 
-    WRAP_VECTOR(m, PortRefVector, wrap_context<PortRef>);
+    WRAP_INDEXSTORE(m, PortRefVector, wrap_context<PortRef>);
 
     typedef dict<IdString, ClockFmax> ClockFmaxMap;
     WRAP_MAP(m, ClockFmaxMap, pass_through<ClockFmax>, "ClockFmaxMap");
diff --git a/common/pycontainers.h b/common/pycontainers.h
index a93230ab78..ff49c34cbf 100644
--- a/common/pycontainers.h
+++ b/common/pycontainers.h
@@ -186,6 +186,63 @@ struct vector_wrapper
 
 #define WRAP_VECTOR(m, t, conv) vector_wrapper<t, py::return_value_policy::copy, conv>().wrap(m, #t, #t "Iterator")
 
+template <typename T, py::return_value_policy P = py::return_value_policy::copy,
+          typename value_conv = PythonConversion::pass_through<T>>
+struct indexed_store_wrapper
+{
+    typedef decltype(std::declval<T>().begin()) iterator_t;
+    typedef decltype(*(std::declval<iterator_t>())) value_t;
+    typedef typename PythonConversion::ContextualWrapper<T &> wrapped_vector;
+    typedef typename PythonConversion::ContextualWrapper<std::pair<iterator_t, iterator_t>> wrapped_pair;
+    using return_t = typename value_conv::ret_type;
+    static wrapped_pair iter(wrapped_vector &range)
+    {
+        return wrapped_pair(range.ctx, std::make_pair(range.base.begin(), range.base.end()));
+    }
+
+    static std::string repr(wrapped_vector &range)
+    {
+        PythonConversion::string_converter<value_t> conv;
+        bool first = true;
+        std::stringstream ss;
+        ss << "[";
+        for (const auto &item : range.base) {
+            if (!first)
+                ss << ", ";
+            ss << "'" << conv.to_str(range.ctx, item) << "'";
+            first = false;
+        }
+        ss << "]";
+        return ss.str();
+    }
+
+    static int len(wrapped_vector &range) { return range.base.capacity(); }
+
+    static py::object getitem(wrapped_vector &range, int i)
+    {
+        store_index<std::remove_reference_t<value_t>> idx(i);
+        if (!range.base.count(idx))
+            throw py::none();
+        return py::cast(value_conv()(range.ctx, boost::ref(range.base.at(idx))));
+    }
+
+    static void wrap(py::module &m, const char *range_name, const char *iter_name)
+    {
+        py::class_<wrapped_vector>(m, range_name)
+                .def("__iter__", iter)
+                .def("__repr__", repr)
+                .def("__len__", len)
+                .def("__getitem__", getitem);
+
+        iterator_wrapper<iterator_t, P, value_conv>().wrap(m, iter_name);
+    }
+
+    typedef iterator_wrapper<iterator_t, P, value_conv> iter_wrap;
+};
+
+#define WRAP_INDEXSTORE(m, t, conv)                                                                                    \
+    indexed_store_wrapper<t, py::return_value_policy::copy, conv>().wrap(m, #t, #t "Iterator")
+
 /*
 Wrapper for a pair, allows accessing either using C++-style members (.first and
 .second) or as a Python iterable and indexable object
diff --git a/common/router1.cc b/common/router1.cc
index f387aee1c5..981321163f 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -34,7 +34,7 @@ struct arc_key
 {
     NetInfo *net_info;
     // logical user cell port index
-    int user_idx;
+    store_index<PortRef> user_idx;
     // physical index into cell->bel pin mapping (usually 0)
     unsigned phys_idx;
 
@@ -52,7 +52,7 @@ struct arc_key
     unsigned int hash() const
     {
         std::size_t seed = std::hash<NetInfo *>()(net_info);
-        seed ^= std::hash<int>()(user_idx) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
+        seed ^= user_idx.hash() + 0x9e3779b9 + (seed << 6) + (seed >> 2);
         seed ^= std::hash<int>()(phys_idx) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
         return seed;
     }
@@ -157,7 +157,7 @@ struct Router1
             return;
 
         NetInfo *net_info = arc.net_info;
-        int user_idx = arc.user_idx;
+        auto user_idx = arc.user_idx;
         unsigned phys_idx = arc.phys_idx;
 
         auto src_wire = ctx->getNetinfoSourceWire(net_info);
@@ -318,14 +318,14 @@ struct Router1
             auto src_wire = ctx->getNetinfoSourceWire(net_info);
             log_assert(src_wire != WireId());
 
-            for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
+            for (auto user : net_info->users.enumerate()) {
                 unsigned phys_idx = 0;
-                for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, net_info->users[user_idx])) {
+                for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, user.value)) {
                     log_assert(dst_wire != WireId());
 
                     arc_key arc;
                     arc.net_info = net_info;
-                    arc.user_idx = user_idx;
+                    arc.user_idx = user.index;
                     arc.phys_idx = phys_idx++;
                     valid_arcs.insert(arc);
 #if 0
@@ -391,28 +391,29 @@ struct Router1
             if (dst_to_arc.count(src_wire))
                 log_error("Wire %s is used as source and sink in different nets: %s vs %s (%d)\n",
                           ctx->nameOfWire(src_wire), ctx->nameOf(net_info),
-                          ctx->nameOf(dst_to_arc.at(src_wire).net_info), dst_to_arc.at(src_wire).user_idx);
+                          ctx->nameOf(dst_to_arc.at(src_wire).net_info), dst_to_arc.at(src_wire).user_idx.idx());
 
-            for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
+            for (auto user : net_info->users.enumerate()) {
                 unsigned phys_idx = 0;
-                for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, net_info->users[user_idx])) {
+                for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, user.value)) {
                     arc_key arc;
                     arc.net_info = net_info;
-                    arc.user_idx = user_idx;
+                    arc.user_idx = user.index;
                     arc.phys_idx = phys_idx++;
 
                     if (dst_to_arc.count(dst_wire)) {
                         if (dst_to_arc.at(dst_wire).net_info == net_info)
                             continue;
                         log_error("Found two arcs with same sink wire %s: %s (%d) vs %s (%d)\n",
-                                  ctx->nameOfWire(dst_wire), ctx->nameOf(net_info), user_idx,
-                                  ctx->nameOf(dst_to_arc.at(dst_wire).net_info), dst_to_arc.at(dst_wire).user_idx);
+                                  ctx->nameOfWire(dst_wire), ctx->nameOf(net_info), user.index.idx(),
+                                  ctx->nameOf(dst_to_arc.at(dst_wire).net_info),
+                                  dst_to_arc.at(dst_wire).user_idx.idx());
                     }
 
                     if (src_to_net.count(dst_wire))
                         log_error("Wire %s is used as source and sink in different nets: %s vs %s (%d)\n",
                                   ctx->nameOfWire(dst_wire), ctx->nameOf(src_to_net.at(dst_wire)),
-                                  ctx->nameOf(net_info), user_idx);
+                                  ctx->nameOf(net_info), user.index.idx());
 
                     dst_to_arc[dst_wire] = arc;
 
@@ -441,9 +442,8 @@ struct Router1
                 // TODO: this matches the situation before supporting multiple cell->bel pins, but do we want to keep
                 // this invariant?
                 if (phys_idx == 0)
-                    log_warning("No wires found for port %s on destination cell %s.\n",
-                                ctx->nameOf(net_info->users[user_idx].port),
-                                ctx->nameOf(net_info->users[user_idx].cell));
+                    log_warning("No wires found for port %s on destination cell %s.\n", ctx->nameOf(user.value.port),
+                                ctx->nameOf(user.value.cell));
             }
 
             src_to_net[src_wire] = net_info;
@@ -463,7 +463,7 @@ struct Router1
     {
 
         NetInfo *net_info = arc.net_info;
-        int user_idx = arc.user_idx;
+        auto user_idx = arc.user_idx;
 
         auto src_wire = ctx->getNetinfoSourceWire(net_info);
         auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx], arc.phys_idx);
@@ -472,8 +472,8 @@ struct Router1
         float crit = tmg.get_criticality(CellPortKey(net_info->users.at(user_idx)));
 
         if (ctx->debug) {
-            log("Routing arc %d on net %s (%d arcs total):\n", user_idx, ctx->nameOf(net_info),
-                int(net_info->users.size()));
+            log("Routing arc %d on net %s (%d arcs total):\n", user_idx.idx(), ctx->nameOf(net_info),
+                int(net_info->users.capacity()));
             log("  source ... %s\n", ctx->nameOfWire(src_wire));
             log("  sink ..... %s\n", ctx->nameOfWire(dst_wire));
         }
@@ -805,8 +805,7 @@ struct Router1
             NetInfo *ni = net.second.get();
             if (skip_net(ni))
                 continue;
-            for (size_t i = 0; i < ni->users.size(); i++) {
-                auto &usr = ni->users.at(i);
+            for (auto &usr : ni->users) {
                 ++arc_count;
                 delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
                 if (slack == std::numeric_limits<delay_t>::min())
@@ -825,8 +824,7 @@ struct Router1
             NetInfo *ni = net.second.get();
             if (skip_net(ni))
                 continue;
-            for (size_t i = 0; i < ni->users.size(); i++) {
-                auto &usr = ni->users.at(i);
+            for (auto &usr : ni->users) {
                 delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
                 if (slack == std::numeric_limits<delay_t>::min())
                     continue;
@@ -912,7 +910,8 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
             arc_key arc = router.arc_queue_pop();
 
             if (!router.route_arc(arc, true)) {
-                log_warning("Failed to find a route for arc %d of net %s.\n", arc.user_idx, ctx->nameOf(arc.net_info));
+                log_warning("Failed to find a route for arc %d of net %s.\n", arc.user_idx.idx(),
+                            ctx->nameOf(arc.net_info));
 #ifndef NDEBUG
                 router.check();
                 ctx->check();
@@ -937,8 +936,7 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
                     }
                     if (is_locked)
                         continue;
-                    for (size_t i = 0; i < ni->users.size(); i++) {
-                        auto &usr = ni->users.at(i);
+                    for (auto &usr : ni->users) {
                         delay_t slack = router.tmg.get_setup_slack(CellPortKey(usr));
                         if (slack == std::numeric_limits<delay_t>::min())
                             continue;
@@ -1051,15 +1049,15 @@ bool Context::checkRoutedDesign() const
             found_unrouted = true;
         }
 
-        dict<WireId, int> dest_wires;
-        for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
-            for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, net_info->users[user_idx])) {
+        dict<WireId, store_index<PortRef>> dest_wires;
+        for (auto user : net_info->users.enumerate()) {
+            for (auto dst_wire : ctx->getNetinfoSinkWires(net_info, user.value)) {
                 log_assert(dst_wire != WireId());
-                dest_wires[dst_wire] = user_idx;
+                dest_wires[dst_wire] = user.index;
 
                 if (net_info->wires.count(dst_wire) == 0) {
                     if (ctx->debug)
-                        log("  sink %d (%s) not bound to net\n", user_idx, ctx->nameOfWire(dst_wire));
+                        log("  sink %d (%s) not bound to net\n", user.index.idx(), ctx->nameOfWire(dst_wire));
                     found_unrouted = true;
                 }
             }
@@ -1086,7 +1084,7 @@ bool Context::checkRoutedDesign() const
             if (db_entry.children.empty()) {
                 if (dest_wires.count(w) != 0) {
                     if (ctx->debug)
-                        log("  %*s=> sink %d\n", 2 * num, "", dest_wires.at(w));
+                        log("  %*s=> sink %d\n", 2 * num, "", dest_wires.at(w).idx());
                 } else {
                     if (ctx->debug)
                         log("  %*s=> stub\n", 2 * num, "");
diff --git a/common/router2.cc b/common/router2.cc
index c76e1f6153..e943e493bc 100644
--- a/common/router2.cc
+++ b/common/router2.cc
@@ -117,7 +117,7 @@ struct Router2
             NetInfo *ni = net.second.get();
             ni->udata = i;
             nets_by_udata.at(i) = ni;
-            nets.at(i).arcs.resize(ni->users.size());
+            nets.at(i).arcs.resize(ni->users.capacity());
 
             // Start net bounding box at overall min/max
             nets.at(i).bb.x0 = std::numeric_limits<int>::max();
@@ -133,10 +133,9 @@ struct Router2
                 nets.at(i).cy += drv_loc.y;
             }
 
-            for (size_t j = 0; j < ni->users.size(); j++) {
-                auto &usr = ni->users.at(j);
+            for (auto usr : ni->users.enumerate()) {
                 WireId src_wire = ctx->getNetinfoSourceWire(ni);
-                for (auto &dst_wire : ctx->getNetinfoSinkWires(ni, usr)) {
+                for (auto &dst_wire : ctx->getNetinfoSinkWires(ni, usr.value)) {
                     nets.at(i).src_wire = src_wire;
                     if (ni->driver.cell == nullptr)
                         src_wire = dst_wire;
@@ -146,10 +145,10 @@ struct Router2
                         log_error("No wire found for port %s on source cell %s.\n", ctx->nameOf(ni->driver.port),
                                   ctx->nameOf(ni->driver.cell));
                     if (dst_wire == WireId())
-                        log_error("No wire found for port %s on destination cell %s.\n", ctx->nameOf(usr.port),
-                                  ctx->nameOf(usr.cell));
-                    nets.at(i).arcs.at(j).emplace_back();
-                    auto &ad = nets.at(i).arcs.at(j).back();
+                        log_error("No wire found for port %s on destination cell %s.\n", ctx->nameOf(usr.value.port),
+                                  ctx->nameOf(usr.value.cell));
+                    nets.at(i).arcs.at(usr.index.idx()).emplace_back();
+                    auto &ad = nets.at(i).arcs.at(usr.index.idx()).back();
                     ad.sink_wire = dst_wire;
                     // Set bounding box for this arc
                     ad.bb = ctx->getRouteBoundingBox(src_wire, dst_wire);
@@ -160,14 +159,14 @@ struct Router2
                     nets.at(i).bb.y1 = std::max(nets.at(i).bb.y1, ad.bb.y1);
                 }
                 // Add location to centroid sum
-                Loc usr_loc = ctx->getBelLocation(usr.cell->bel);
+                Loc usr_loc = ctx->getBelLocation(usr.value.cell->bel);
                 nets.at(i).cx += usr_loc.x;
                 nets.at(i).cy += usr_loc.y;
             }
             nets.at(i).hpwl = std::max(
                     std::abs(nets.at(i).bb.y1 - nets.at(i).bb.y0) + std::abs(nets.at(i).bb.x1 - nets.at(i).bb.x0), 1);
-            nets.at(i).cx /= int(ni->users.size() + 1);
-            nets.at(i).cy /= int(ni->users.size() + 1);
+            nets.at(i).cx /= int(ni->users.entries() + 1);
+            nets.at(i).cy /= int(ni->users.entries() + 1);
             if (ctx->debug)
                 log_info("%s: bb=(%d, %d)->(%d, %d) c=(%d, %d) hpwl=%d\n", ctx->nameOf(ni), nets.at(i).bb.x0,
                          nets.at(i).bb.y0, nets.at(i).bb.x1, nets.at(i).bb.y1, nets.at(i).cx, nets.at(i).cy,
@@ -218,11 +217,11 @@ struct Router2
         for (auto &net_pair : ctx->nets) {
             auto *net = net_pair.second.get();
             auto &nd = nets.at(net->udata);
-            for (size_t usr = 0; usr < net->users.size(); usr++) {
-                auto &ad = nd.arcs.at(usr);
+            for (auto usr : net->users.enumerate()) {
+                auto &ad = nd.arcs.at(usr.index.idx());
                 for (size_t phys_pin = 0; phys_pin < ad.size(); phys_pin++) {
-                    if (check_arc_routing(net, usr, phys_pin)) {
-                        record_prerouted_net(net, usr, phys_pin);
+                    if (check_arc_routing(net, usr.index, phys_pin)) {
+                        record_prerouted_net(net, usr.index, phys_pin);
                     }
                 }
             }
@@ -261,7 +260,7 @@ struct Router2
         // Nets that failed routing
         std::vector<NetInfo *> failed_nets;
 
-        std::vector<std::pair<size_t, size_t>> route_arcs;
+        std::vector<std::pair<store_index<PortRef>, size_t>> route_arcs;
 
         std::priority_queue<QueuedWire, std::vector<QueuedWire>, QueuedWire::Greater> fwd_queue, bwd_queue;
         // Special case where one net has multiple logical arcs to the same physical sink
@@ -305,7 +304,7 @@ struct Router2
             log(__VA_ARGS__);                                                                                          \
     } while (0)
 
-    void bind_pip_internal(PerNetData &net, size_t user, int wire, PipId pip)
+    void bind_pip_internal(PerNetData &net, store_index<PortRef> user, int wire, PipId pip)
     {
         auto &wd = flat_wires.at(wire);
         auto found = net.wires.find(wd.w);
@@ -323,7 +322,7 @@ struct Router2
         }
     }
 
-    void unbind_pip_internal(PerNetData &net, size_t user, WireId wire)
+    void unbind_pip_internal(PerNetData &net, store_index<PortRef> user, WireId wire)
     {
         auto &wd = wire_data(wire);
         auto &b = net.wires.at(wd.w);
@@ -335,10 +334,10 @@ struct Router2
         }
     }
 
-    void ripup_arc(NetInfo *net, size_t user, size_t phys_pin)
+    void ripup_arc(NetInfo *net, store_index<PortRef> user, size_t phys_pin)
     {
         auto &nd = nets.at(net->udata);
-        auto &ad = nd.arcs.at(user).at(phys_pin);
+        auto &ad = nd.arcs.at(user.idx()).at(phys_pin);
         if (!ad.routed)
             return;
         WireId src = nets.at(net->udata).src_wire;
@@ -351,7 +350,8 @@ struct Router2
         ad.routed = false;
     }
 
-    float score_wire_for_arc(NetInfo *net, size_t user, size_t phys_pin, WireId wire, PipId pip, float crit_weight)
+    float score_wire_for_arc(NetInfo *net, store_index<PortRef> user, size_t phys_pin, WireId wire, PipId pip,
+                             float crit_weight)
     {
         auto &wd = wire_data(wire);
         auto &nd = nets.at(net->udata);
@@ -367,13 +367,14 @@ struct Router2
         float present_cost = 1.0f + overuse * curr_cong_weight * crit_weight;
         if (pip != PipId()) {
             Loc pl = ctx->getPipLocation(pip);
-            bias_cost = cfg.bias_cost_factor * (base_cost / int(net->users.size())) *
+            bias_cost = cfg.bias_cost_factor * (base_cost / int(net->users.entries())) *
                         ((std::abs(pl.x - nd.cx) + std::abs(pl.y - nd.cy)) / float(nd.hpwl));
         }
         return base_cost * hist_cost * present_cost / (1 + (source_uses * crit_weight)) + bias_cost;
     }
 
-    float get_togo_cost(NetInfo *net, size_t user, int wire, WireId src_sink, float crit_weight, bool bwd = false)
+    float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, float crit_weight,
+                        bool bwd = false)
     {
         auto &nd = nets.at(net->udata);
         auto &wd = flat_wires[wire];
@@ -386,10 +387,10 @@ struct Router2
         return (ctx->getDelayNS(est_delay) / (1 + source_uses * crit_weight)) + cfg.ipin_cost_adder;
     }
 
-    bool check_arc_routing(NetInfo *net, size_t usr, size_t phys_pin)
+    bool check_arc_routing(NetInfo *net, store_index<PortRef> usr, size_t phys_pin)
     {
         auto &nd = nets.at(net->udata);
-        auto &ad = nd.arcs.at(usr).at(phys_pin);
+        auto &ad = nd.arcs.at(usr.idx()).at(phys_pin);
         WireId src_wire = nets.at(net->udata).src_wire;
         WireId cursor = ad.sink_wire;
         while (nd.wires.count(cursor)) {
@@ -404,10 +405,10 @@ struct Router2
         return (cursor == src_wire);
     }
 
-    void record_prerouted_net(NetInfo *net, size_t usr, size_t phys_pin)
+    void record_prerouted_net(NetInfo *net, store_index<PortRef> usr, size_t phys_pin)
     {
         auto &nd = nets.at(net->udata);
-        auto &ad = nd.arcs.at(usr).at(phys_pin);
+        auto &ad = nd.arcs.at(usr.idx()).at(phys_pin);
         ad.routed = true;
 
         WireId src = nets.at(net->udata).src_wire;
@@ -449,7 +450,7 @@ struct Router2
     }
 
     // Find all the wires that must be used to route a given arc
-    bool reserve_wires_for_arc(NetInfo *net, size_t i)
+    bool reserve_wires_for_arc(NetInfo *net, store_index<PortRef> i)
     {
         bool did_something = false;
         WireId src = ctx->getNetinfoSourceWire(net);
@@ -459,7 +460,7 @@ struct Router2
             WireId cursor = sink;
             bool done = false;
             if (ctx->debug)
-                log("reserving wires for arc %d (%s.%s) of net %s\n", int(i), ctx->nameOf(usr.cell),
+                log("reserving wires for arc %d (%s.%s) of net %s\n", i.idx(), ctx->nameOf(usr.cell),
                     ctx->nameOf(usr.port), ctx->nameOf(net));
             while (!done) {
                 auto &wd = wire_data(cursor);
@@ -501,8 +502,8 @@ struct Router2
                 WireId src = ctx->getNetinfoSourceWire(net);
                 if (src == WireId())
                     continue;
-                for (size_t i = 0; i < net->users.size(); i++)
-                    did_something |= reserve_wires_for_arc(net, i);
+                for (auto usr : net->users.enumerate())
+                    did_something |= reserve_wires_for_arc(net, usr.index);
             }
         } while (did_something);
     }
@@ -529,12 +530,12 @@ struct Router2
         return false;
     }
 
-    void update_wire_by_loc(ThreadContext &t, NetInfo *net, size_t i, size_t phys_pin, bool is_mt)
+    void update_wire_by_loc(ThreadContext &t, NetInfo *net, store_index<PortRef> i, size_t phys_pin, bool is_mt)
     {
         if (is_pseudo_const_net(net))
             return;
         auto &nd = nets.at(net->udata);
-        auto &ad = nd.arcs.at(i).at(phys_pin);
+        auto &ad = nd.arcs.at(i.idx()).at(phys_pin);
         WireId cursor = ad.sink_wire;
         if (!nd.wires.count(cursor))
             return;
@@ -571,28 +572,29 @@ struct Router2
     bool was_visited_fwd(int wire) { return flat_wires.at(wire).visited_fwd; }
     bool was_visited_bwd(int wire) { return flat_wires.at(wire).visited_bwd; }
 
-    float get_arc_crit(NetInfo *net, size_t i)
+    float get_arc_crit(NetInfo *net, store_index<PortRef> i)
     {
         if (!timing_driven)
             return 0;
         return tmg.get_criticality(CellPortKey(net->users.at(i)));
     }
 
-    bool arc_failed_slack(NetInfo *net, size_t usr_idx)
+    bool arc_failed_slack(NetInfo *net, store_index<PortRef> usr_idx)
     {
         return timing_driven_ripup &&
                (tmg.get_setup_slack(CellPortKey(net->users.at(usr_idx))) < (2 * ctx->getDelayEpsilon()));
     }
 
-    ArcRouteResult route_arc(ThreadContext &t, NetInfo *net, size_t i, size_t phys_pin, bool is_mt, bool is_bb = true)
+    ArcRouteResult route_arc(ThreadContext &t, NetInfo *net, store_index<PortRef> i, size_t phys_pin, bool is_mt,
+                             bool is_bb = true)
     {
         // Do some initial lookups and checks
         auto arc_start = std::chrono::high_resolution_clock::now();
         auto &nd = nets[net->udata];
-        auto &ad = nd.arcs.at(i).at(phys_pin);
+        auto &ad = nd.arcs.at(i.idx()).at(phys_pin);
         auto &usr = net->users.at(i);
-        ROUTE_LOG_DBG("Routing arc %d of net '%s' (%d, %d) -> (%d, %d)\n", int(i), ctx->nameOf(net), ad.bb.x0, ad.bb.y0,
-                      ad.bb.x1, ad.bb.y1);
+        ROUTE_LOG_DBG("Routing arc %d of net '%s' (%d, %d) -> (%d, %d)\n", i.idx(), ctx->nameOf(net), ad.bb.x0,
+                      ad.bb.y0, ad.bb.x1, ad.bb.y1);
         WireId src_wire = ctx->getNetinfoSourceWire(net), dst_wire = ctx->getNetinfoSinkWire(net, usr, phys_pin);
         if (src_wire == WireId())
             ARC_LOG_ERR("No wire found for port %s on source cell %s.\n", ctx->nameOf(net->driver.port),
@@ -614,7 +616,7 @@ struct Router2
         //     0. starting within a small range of existing routing
         //     1. expanding from all routing
         int mode = 0;
-        if (net->users.size() < 4 || nd.wires.empty() || (crit > 0.95))
+        if (net->users.entries() < 4 || nd.wires.empty() || (crit > 0.95))
             mode = 1;
 
         // This records the point where forwards and backwards routing met
@@ -844,11 +846,11 @@ struct Router2
             t.processed_sinks.insert(dst_wire);
             ad.routed = true;
             auto arc_end = std::chrono::high_resolution_clock::now();
-            ROUTE_LOG_DBG("Routing arc %d of net '%s' (is_bb = %d) took %02fs\n", int(i), ctx->nameOf(net), is_bb,
+            ROUTE_LOG_DBG("Routing arc %d of net '%s' (is_bb = %d) took %02fs\n", i.idx(), ctx->nameOf(net), is_bb,
                           std::chrono::duration<float>(arc_end - arc_start).count());
         } else {
             auto arc_end = std::chrono::high_resolution_clock::now();
-            ROUTE_LOG_DBG("Failed routing arc %d of net '%s' (is_bb = %d) took %02fs\n", int(i), ctx->nameOf(net),
+            ROUTE_LOG_DBG("Failed routing arc %d of net '%s' (is_bb = %d) took %02fs\n", i.idx(), ctx->nameOf(net),
                           is_bb, std::chrono::duration<float>(arc_end - arc_start).count());
             result = ARC_RETRY_WITHOUT_BB;
         }
@@ -880,26 +882,26 @@ struct Router2
         t.in_wire_by_loc.clear();
         auto &nd = nets.at(net->udata);
         bool failed_slack = false;
-        for (size_t i = 0; i < net->users.size(); i++)
-            failed_slack |= arc_failed_slack(net, i);
-        for (size_t i = 0; i < net->users.size(); i++) {
-            auto &ad = nd.arcs.at(i);
+        for (auto usr : net->users.enumerate())
+            failed_slack |= arc_failed_slack(net, usr.index);
+        for (auto usr : net->users.enumerate()) {
+            auto &ad = nd.arcs.at(usr.index.idx());
             for (size_t j = 0; j < ad.size(); j++) {
                 // Ripup failed arcs to start with
                 // Check if arc is already legally routed
-                if (!failed_slack && check_arc_routing(net, i, j)) {
-                    update_wire_by_loc(t, net, i, j, true);
+                if (!failed_slack && check_arc_routing(net, usr.index, j)) {
+                    update_wire_by_loc(t, net, usr.index, j, true);
                     continue;
                 }
 
                 // Ripup arc to start with
-                ripup_arc(net, i, j);
-                t.route_arcs.emplace_back(i, j);
+                ripup_arc(net, usr.index, j);
+                t.route_arcs.emplace_back(usr.index, j);
             }
         }
         // Route most critical arc first
         std::stable_sort(t.route_arcs.begin(), t.route_arcs.end(),
-                         [&](std::pair<size_t, size_t> a, std::pair<size_t, size_t> b) {
+                         [&](std::pair<store_index<PortRef>, size_t> a, std::pair<store_index<PortRef>, size_t> b) {
                              return get_arc_crit(net, a.first) > get_arc_crit(net, b.first);
                          });
         for (auto a : t.route_arcs) {
@@ -913,7 +915,7 @@ struct Router2
                 } else {
                     // Attempt a re-route without the bounding box constraint
                     ROUTE_LOG_DBG("Rerouting arc %d.%d of net '%s' without bounding box, possible tricky routing...\n",
-                                  int(a.first), int(a.second), ctx->nameOf(net));
+                                  a.first.idx(), int(a.second), ctx->nameOf(net));
                     auto res2 = route_arc(t, net, a.first, a.second, is_mt, false);
                     // If this also fails, no choice but to give up
                     if (res2 != ARC_SUCCESS) {
@@ -926,7 +928,7 @@ struct Router2
                                 log("\n");
                             }
                         }
-                        log_error("Failed to route arc %d.%d of net '%s', from %s to %s.\n", int(a.first),
+                        log_error("Failed to route arc %d.%d of net '%s', from %s to %s.\n", a.first.idx(),
                                   int(a.second), ctx->nameOf(net), ctx->nameOfWire(ctx->getNetinfoSourceWire(net)),
                                   ctx->nameOfWire(ctx->getNetinfoSinkWire(net, net->users.at(a.first), a.second)));
                     }
@@ -991,7 +993,7 @@ struct Router2
         }
     }
 
-    bool bind_and_check(NetInfo *net, int usr_idx, int phys_pin)
+    bool bind_and_check(NetInfo *net, store_index<PortRef> usr_idx, int phys_pin)
     {
 #ifdef ARCH_ECP5
         if (net->is_global)
@@ -999,7 +1001,7 @@ struct Router2
 #endif
         bool success = true;
         auto &nd = nets.at(net->udata);
-        auto &ad = nd.arcs.at(usr_idx).at(phys_pin);
+        auto &ad = nd.arcs.at(usr_idx.idx()).at(phys_pin);
         auto &usr = net->users.at(usr_idx);
         WireId src = ctx->getNetinfoSourceWire(net);
         // Skip routes with no source
@@ -1043,7 +1045,8 @@ struct Router2
             if (!nd.wires.count(cursor)) {
                 log("Failure details:\n");
                 log("    Cursor: %s\n", ctx->nameOfWire(cursor));
-                log_error("Internal error; incomplete route tree for arc %d of net %s.\n", usr_idx, ctx->nameOf(net));
+                log_error("Internal error; incomplete route tree for arc %d of net %s.\n", usr_idx.idx(),
+                          ctx->nameOf(net));
             }
             PipId p = nd.wires.at(cursor).first;
             if (ctx->checkPipAvailForNet(p, net)) {
@@ -1104,9 +1107,9 @@ struct Router2
             }
 
             // Bind the arcs using the routes we have discovered
-            for (size_t i = 0; i < net->users.size(); i++) {
-                for (size_t phys_pin = 0; phys_pin < nets.at(net->udata).arcs.at(i).size(); phys_pin++) {
-                    if (!bind_and_check(net, i, phys_pin)) {
+            for (auto usr : net->users.enumerate()) {
+                for (size_t phys_pin = 0; phys_pin < nets.at(net->udata).arcs.at(usr.index.idx()).size(); phys_pin++) {
+                    if (!bind_and_check(net, usr.index, phys_pin)) {
                         ++arch_fail;
                         success = false;
                     }
@@ -1313,10 +1316,10 @@ struct Router2
                 route_net(tcs.at(N), fail, false);
     }
 
-    delay_t get_route_delay(int net, int usr_idx, int phys_idx)
+    delay_t get_route_delay(int net, store_index<PortRef> usr_idx, int phys_idx)
     {
         auto &nd = nets.at(net);
-        auto &ad = nd.arcs.at(usr_idx).at(phys_idx);
+        auto &ad = nd.arcs.at(usr_idx.idx()).at(phys_idx);
         WireId cursor = ad.sink_wire;
         if (cursor == WireId() || nd.src_wire == WireId())
             return 0;
@@ -1344,11 +1347,11 @@ struct Router2
                 continue;
 #endif
             auto &nd = nets.at(net);
-            for (int i = 0; i < int(nd.arcs.size()); i++) {
+            for (auto usr : ni->users.enumerate()) {
                 delay_t arc_delay = 0;
-                for (int j = 0; j < int(nd.arcs.at(i).size()); j++)
-                    arc_delay = std::max(arc_delay, get_route_delay(net, i, j));
-                tmg.set_route_delay(CellPortKey(ni->users.at(i)), DelayPair(arc_delay));
+                for (int j = 0; j < int(nd.arcs.at(usr.index.idx()).size()); j++)
+                    arc_delay = std::max(arc_delay, get_route_delay(net, usr.index, j));
+                tmg.set_route_delay(CellPortKey(usr.value), DelayPair(arc_delay));
             }
         }
     }
@@ -1416,8 +1419,8 @@ struct Router2
             if (timing_driven_ripup && iter < 500) {
                 for (size_t i = 0; i < nets_by_udata.size(); i++) {
                     NetInfo *ni = nets_by_udata.at(i);
-                    for (size_t j = 0; j < ni->users.size(); j++) {
-                        if (arc_failed_slack(ni, j)) {
+                    for (auto usr : ni->users.enumerate()) {
+                        if (arc_failed_slack(ni, usr.index)) {
                             failed_nets.insert(i);
                             ++tmgfail;
                         }
@@ -1451,7 +1454,7 @@ struct Router2
             log_info("1000 slowest nets by runtime:\n");
             for (int i = 0; i < std::min(int(nets_by_runtime.size()), 1000); i++) {
                 log("        %80s %6d %.1fms\n", nets_by_runtime.at(i).second.c_str(ctx),
-                    int(ctx->nets.at(nets_by_runtime.at(i).second)->users.size()),
+                    int(ctx->nets.at(nets_by_runtime.at(i).second)->users.entries()),
                     nets_by_runtime.at(i).first / 1000.0);
             }
         }
diff --git a/common/timing.cc b/common/timing.cc
index f30d4fc531..834785fbe3 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -60,14 +60,6 @@ void TimingAnalyser::init_ports()
             data.cell_port = CellPortKey(ci->name, port.first);
         }
     }
-    // Cell port to net port mapping
-    for (auto &net : ctx->nets) {
-        NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr)
-            ports[CellPortKey(ni->driver)].net_port = NetPortKey(ni->name);
-        for (size_t i = 0; i < ni->users.size(); i++)
-            ports[CellPortKey(ni->users.at(i))].net_port = NetPortKey(ni->name, i);
-    }
 }
 
 void TimingAnalyser::get_cell_delays()
@@ -79,7 +71,7 @@ void TimingAnalyser::get_cell_delays()
 
         IdString name = port.first.port;
         // Ignore dangling ports altogether for timing purposes
-        if (pd.net_port.net == IdString())
+        if (!pi.net)
             continue;
         pd.cell_arcs.clear();
         int clkInfoCount = 0;
diff --git a/common/timing.h b/common/timing.h
index b34fd63614..fe1bcaa84c 100644
--- a/common/timing.h
+++ b/common/timing.h
@@ -44,28 +44,6 @@ struct CellPortKey
     }
 };
 
-struct NetPortKey
-{
-    IdString net;
-    size_t idx;
-    NetPortKey(){};
-    explicit NetPortKey(IdString net) : net(net), idx(DRIVER_IDX){};        // driver
-    explicit NetPortKey(IdString net, size_t user) : net(net), idx(user){}; // user
-
-    static const size_t DRIVER_IDX = std::numeric_limits<size_t>::max();
-
-    inline bool is_driver() const { return (idx == DRIVER_IDX); }
-    inline size_t user_idx() const
-    {
-        NPNR_ASSERT(idx != DRIVER_IDX);
-        return idx;
-    }
-
-    unsigned int hash() const { return mkhash(net.hash(), idx); }
-
-    inline bool operator==(const NetPortKey &other) const { return (net == other.net) && (idx == other.idx); }
-};
-
 struct ClockDomainKey
 {
     IdString clock;
@@ -194,7 +172,6 @@ struct TimingAnalyser
     struct PerPort
     {
         CellPortKey cell_port;
-        NetPortKey net_port;
         PortType type;
         // per domain timings
         dict<domain_id_t, ArrivReqTime> arrival;
diff --git a/common/timing_opt.cc b/common/timing_opt.cc
index a73a70cf0f..f9246292d5 100644
--- a/common/timing_opt.cc
+++ b/common/timing_opt.cc
@@ -73,8 +73,7 @@ class TimingOptimiser
             for (auto usr : ni->users) {
                 max_net_delay[std::make_pair(usr.cell->name, usr.port)] = std::numeric_limits<delay_t>::max();
             }
-            for (size_t i = 0; i < ni->users.size(); i++) {
-                auto &usr = ni->users.at(i);
+            for (auto usr : ni->users) {
                 delay_t net_delay = ctx->getNetinfoRouteDelay(ni, usr);
                 delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
                 delay_t domain_slack = tmg.get_domain_setup_slack(CellPortKey(usr));
@@ -234,7 +233,7 @@ class TimingOptimiser
     std::vector<std::vector<PortRef *>> find_crit_paths(float crit_thresh, size_t max_count)
     {
         std::vector<std::vector<PortRef *>> crit_paths;
-        std::vector<std::pair<NetInfo *, int>> crit_nets;
+        std::vector<std::pair<NetInfo *, store_index<PortRef>>> crit_nets;
         std::vector<IdString> netnames;
         std::transform(ctx->nets.begin(), ctx->nets.end(), std::back_inserter(netnames),
                        [](const std::pair<IdString, std::unique_ptr<NetInfo>> &kv) { return kv.first; });
@@ -243,28 +242,19 @@ class TimingOptimiser
             if (crit_nets.size() >= max_count)
                 break;
             float highest_crit = 0;
-            size_t crit_user_idx = 0;
+            store_index<PortRef> crit_user_idx{};
             NetInfo *ni = ctx->nets.at(net).get();
-            for (size_t i = 0; i < ni->users.size(); i++) {
-                float crit = tmg.get_criticality(CellPortKey(ni->users.at(i)));
+            for (auto usr : ni->users.enumerate()) {
+                float crit = tmg.get_criticality(CellPortKey(usr.value));
                 if (crit > highest_crit) {
                     highest_crit = crit;
-                    crit_user_idx = i;
+                    crit_user_idx = usr.index;
                 }
             }
             if (highest_crit > crit_thresh)
-                crit_nets.push_back(std::make_pair(ni, crit_user_idx));
+                crit_nets.emplace_back(ni, crit_user_idx);
         }
 
-        auto port_user_index = [](CellInfo *cell, PortInfo &port) -> size_t {
-            NPNR_ASSERT(port.net != nullptr);
-            for (size_t i = 0; i < port.net->users.size(); i++) {
-                auto &usr = port.net->users.at(i);
-                if (usr.cell == cell && usr.port == port.name)
-                    return i;
-            }
-            NPNR_ASSERT_FALSE("port user not found on net");
-        };
         pool<PortRef *, hash_ptr_ops> used_ports;
 
         for (auto crit_net : crit_nets) {
@@ -280,7 +270,7 @@ class TimingOptimiser
             NetInfo *back_cursor = crit_net.first;
             while (back_cursor != nullptr) {
                 float max_crit = 0;
-                std::pair<NetInfo *, size_t> crit_sink{nullptr, 0};
+                std::pair<NetInfo *, store_index<PortRef>> crit_sink{nullptr, {}};
                 CellInfo *cell = back_cursor->driver.cell;
                 if (cell == nullptr)
                     break;
@@ -298,13 +288,12 @@ class TimingOptimiser
                     bool is_path = ctx->getCellDelay(cell, port.first, back_cursor->driver.port, combDelay);
                     if (!is_path)
                         continue;
-                    size_t user_idx = port_user_index(cell, port.second);
                     float usr_crit = tmg.get_criticality(CellPortKey(cell->name, port.first));
-                    if (used_ports.count(&(pn->users.at(user_idx))))
+                    if (used_ports.count(&(pn->users.at(port.second.user_idx))))
                         continue;
                     if (usr_crit >= max_crit) {
                         max_crit = usr_crit;
-                        crit_sink = std::make_pair(pn, user_idx);
+                        crit_sink = std::make_pair(pn, port.second.user_idx);
                     }
                 }
 
@@ -319,7 +308,7 @@ class TimingOptimiser
             while (fwd_cursor != nullptr) {
                 crit_path.push_back(fwd_cursor);
                 float max_crit = 0;
-                std::pair<NetInfo *, size_t> crit_sink{nullptr, 0};
+                std::pair<NetInfo *, store_index<PortRef>> crit_sink{nullptr, {}};
                 CellInfo *cell = fwd_cursor->cell;
                 for (auto port : cell->ports) {
                     if (port.second.type != PORT_OUT)
@@ -336,13 +325,13 @@ class TimingOptimiser
                     bool is_path = ctx->getCellDelay(cell, fwd_cursor->port, port.first, combDelay);
                     if (!is_path)
                         continue;
-                    for (size_t i = 0; i < pn->users.size(); i++) {
-                        if (used_ports.count(&(pn->users.at(i))))
+                    for (auto usr : pn->users.enumerate()) {
+                        if (used_ports.count(&(pn->users.at(usr.index))))
                             continue;
-                        float crit = tmg.get_criticality(CellPortKey(pn->users.at(i)));
+                        float crit = tmg.get_criticality(CellPortKey(usr.value));
                         if (crit >= max_crit) {
                             max_crit = crit;
-                            crit_sink = std::make_pair(pn, i);
+                            crit_sink = std::make_pair(pn, usr.index);
                         }
                     }
                 }
@@ -409,14 +398,10 @@ class TimingOptimiser
         delay_t original_delay = 0;
 
         for (size_t i = 0; i < path.size(); i++) {
-            NetInfo *pn = path.at(i)->cell->ports.at(path.at(i)->port).net;
-            for (size_t j = 0; j < pn->users.size(); j++) {
-                auto &usr = pn->users.at(j);
-                if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
-                    original_delay += ctx->predictArcDelay(pn, usr);
-                    break;
-                }
-            }
+            auto &port = path.at(i)->cell->ports.at(path.at(i)->port);
+            NetInfo *pn = port.net;
+            if (port.user_idx)
+                original_delay += ctx->predictArcDelay(pn, pn->users.at(port.user_idx));
         }
 
         IdString last_cell;
@@ -493,14 +478,10 @@ class TimingOptimiser
                 delay_t total_delay = 0;
 
                 for (size_t i = 0; i < path.size(); i++) {
-                    NetInfo *pn = path.at(i)->cell->ports.at(path.at(i)->port).net;
-                    for (size_t j = 0; j < pn->users.size(); j++) {
-                        auto &usr = pn->users.at(j);
-                        if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
-                            total_delay += ctx->predictArcDelay(pn, usr);
-                            break;
-                        }
-                    }
+                    auto &port = path.at(i)->cell->ports.at(path.at(i)->port);
+                    NetInfo *pn = port.net;
+                    if (port.user_idx)
+                        total_delay += ctx->predictArcDelay(pn, pn->users.at(port.user_idx));
                     if (path.at(i)->cell == next_cell)
                         break;
                 }
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index a5d484ff23..2c5f96d3fe 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -212,10 +212,7 @@ static void replace_port_safe(bool has_ff, CellInfo *ff, IdString ff_port, CellI
         NPNR_ASSERT(lc->ports.at(lc_port).net == ff->ports.at(ff_port).net);
         NetInfo *ffnet = ff->ports.at(ff_port).net;
         if (ffnet != nullptr)
-            ffnet->users.erase(
-                    std::remove_if(ffnet->users.begin(), ffnet->users.end(),
-                                   [ff, ff_port](PortRef port) { return port.cell == ff && port.port == ff_port; }),
-                    ffnet->users.end());
+            ffnet->users.remove(ff->ports.at(ff_port).user_idx);
     } else {
         ff->movePortTo(ff_port, lc, lc_port);
     }
@@ -477,7 +474,7 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         inv_lut->connectPorts(id_Z, trio, id_T);
         created_cells.push_back(std::move(inv_lut));
 
-        if (donet->users.size() > 1) {
+        if (donet->users.entries() > 1) {
             for (auto user : donet->users)
                 log_info("     remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
             log_error("unsupported tristate IO pattern for IO buffer '%s', "
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 7b48e69388..71188aa0fb 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -472,17 +472,15 @@ class Ecp5GlobalRouter
                 } else if (is_logic_port(user)) {
                     keep_users.push_back(user);
                 } else {
-                    glbptr->users.push_back(user);
                     user.cell->ports.at(user.port).net = glbptr;
+                    user.cell->ports.at(user.port).user_idx = glbptr->users.add(user);
                 }
             }
-            net->users = keep_users;
+            net->users.clear();
+            for (auto &usr : keep_users)
+                usr.cell->ports.at(usr.port).user_idx = net->users.add(usr);
 
-            dcc->ports[id_CLKI].net = net;
-            PortRef clki_pr;
-            clki_pr.port = id_CLKI;
-            clki_pr.cell = dcc.get();
-            net->users.push_back(clki_pr);
+            dcc->connectPort(id_CLKI, net);
             if (net->clkconstr) {
                 glbptr->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
                 glbptr->clkconstr->low = net->clkconstr->low;
@@ -556,9 +554,13 @@ class Ecp5GlobalRouter
             if (ci->type == id_DCCA || ci->type == id_DCSC) {
                 NetInfo *clock = ci->ports.at((ci->type == id_DCSC) ? id_DCSOUT : id_CLKO).net;
                 NPNR_ASSERT(clock != nullptr);
-                bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
-                                                 [this](const PortRef &port) { return !is_clock_port(port); });
-
+                bool drives_fabric = false;
+                for (auto &usr : clock->users) {
+                    if (!is_clock_port(usr)) {
+                        drives_fabric = true;
+                        break;
+                    }
+                }
                 int glbid;
                 if (drives_fabric) {
                     if (fab_globals.empty())
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 2b069db098..8c442843d1 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -326,14 +326,14 @@ class Ecp5Packer
                 }
 
                 // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
-                if (znet != nullptr && znet->users.size() < 10) {
+                if (znet != nullptr && znet->users.entries() < 10) {
                     for (auto user : znet->users) {
                         if (is_lc(ctx, user.cell) || user.cell->type == id_DP16KD || is_ff(ctx, user.cell)) {
                             for (auto port : user.cell->ports) {
                                 if (port.second.type != PORT_IN || port.second.net == nullptr ||
                                     port.second.net == znet)
                                     continue;
-                                if (port.second.net->users.size() > 10)
+                                if (port.second.net->users.entries() > 10)
                                     continue;
                                 CellInfo *drv = port.second.net->driver.cell;
                                 if (drv == nullptr)
@@ -355,11 +355,11 @@ class Ecp5Packer
                     if (!ci->ports.count(ctx->id(inp)))
                         continue;
                     NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
-                    if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
+                    if (innet != nullptr && innet->users.entries() < 5 && innet->users.entries() > 1)
                         inpnets.push_back(innet);
                 }
                 std::sort(inpnets.begin(), inpnets.end(),
-                          [&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
+                          [&](const NetInfo *a, const NetInfo *b) { return a->users.entries() < b->users.entries(); });
                 for (auto inet : inpnets) {
                     for (auto &user : inet->users) {
                         if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
@@ -412,7 +412,7 @@ class Ecp5Packer
             return false;
         for (auto user : net->users) {
             if (is_top_port(user)) {
-                if (net->users.size() > 1)
+                if (net->users.entries() > 1)
                     log_error("   port %s.%s must be connected to (and only to) a top level pin\n",
                               user.cell->name.c_str(ctx), user.port.c_str(ctx));
                 tp = user;
@@ -420,7 +420,7 @@ class Ecp5Packer
             }
         }
         if (net->driver.cell != nullptr && is_top_port(net->driver)) {
-            if (net->users.size() > 1)
+            if (net->users.entries() > 1)
                 log_error("   port %s.%s must be connected to (and only to) a top level pin\n",
                           net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
             tp = net->driver;
@@ -460,9 +460,9 @@ class Ecp5Packer
 
                     NetInfo *net = trio->ports.at(id_B).net;
                     if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
-                         net->users.size() > 1) ||
+                         net->users.entries() > 1) ||
                         (ci->type == ctx->id("$nextpnr_obuf") &&
-                         (net->users.size() > 2 || net->driver.cell != nullptr)) ||
+                         (net->users.entries() > 2 || net->driver.cell != nullptr)) ||
                         (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(id_I).net != nullptr &&
                          ci->ports.at(id_I).net->driver.cell != nullptr))
                         log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
@@ -742,16 +742,14 @@ class Ecp5Packer
         feedin->params[id_INJECT1_0] = std::string("NO");
         feedin->params[id_INJECT1_1] = std::string("YES");
 
-        carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
-                                          [chain_in](const PortRef &user) {
-                                              return user.port == chain_in.port && user.cell == chain_in.cell;
-                                          }),
-                           carry->users.end());
+        carry->users.remove(chain_in.cell->ports.at(chain_in.port).user_idx);
         feedin->connectPort(id_A0, carry);
 
         NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
         feedin->connectPort(id_COUT, new_carry);
         chain_in.cell->ports[chain_in.port].net = nullptr;
+        chain_in.cell->ports[chain_in.port].user_idx = {};
+
         chain_in.cell->connectPort(chain_in.port, new_carry);
 
         CellInfo *feedin_ptr = feedin.get();
@@ -782,12 +780,8 @@ class Ecp5Packer
         if (chain_next) {
             // Loop back into LUT4_1 for feedthrough
             feedout->connectPort(id_A1, carry);
-
-            carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
-                                              [chain_next](const PortRef &user) {
-                                                  return user.port == chain_next->port && user.cell == chain_next->cell;
-                                              }),
-                               carry->users.end());
+            if (chain_next->cell && chain_next->cell->ports.at(chain_next->port).user_idx)
+                carry->users.remove(chain_next->cell->ports.at(chain_next->port).user_idx);
 
             NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
             feedout->connectPort(id_COUT, new_cout);
@@ -833,7 +827,7 @@ class Ecp5Packer
             } else {
                 NetInfo *carry_net = cell->ports.at(id_COUT).net;
                 bool at_end = (curr_cell == carryc.cells.end() - 1);
-                if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
+                if (carry_net != nullptr && (carry_net->users.entries() > 1 || at_end)) {
                     boost::optional<PortRef> nextport;
                     if (!at_end) {
                         auto next_cell = *(curr_cell + 1);
@@ -1123,7 +1117,7 @@ class Ecp5Packer
                 if (pn == nullptr)
                     continue;
                 // Skip high-fanout nets that are unlikely to be relevant
-                if (pn->users.size() > 25)
+                if (pn->users.entries() > 25)
                     continue;
                 // Add other ports on this net if not already visited
                 auto visit_port = [&](const PortRef &port) {
@@ -1304,11 +1298,11 @@ class Ecp5Packer
                         } else {
                             // Not allowed to change to a tie-high
                             uc->ports[user.port].net = constnet;
-                            constnet->users.push_back(user);
+                            uc->ports[user.port].user_idx = constnet->users.add(user);
                         }
                     } else {
                         uc->ports[user.port].net = constnet;
-                        constnet->users.push_back(user);
+                        uc->ports[user.port].user_idx = constnet->users.add(user);
                     }
                 } else if (is_ff(ctx, uc) && user.port == id_LSR &&
                            ((!constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "LSR") ||
@@ -1335,7 +1329,7 @@ class Ecp5Packer
                         user.port.str(ctx).substr(0, 6) == "SOURCE" || user.port.str(ctx).substr(0, 6) == "SIGNED" ||
                         user.port.str(ctx).substr(0, 2) == "OP") {
                         uc->ports[user.port].net = constnet;
-                        constnet->users.push_back(user);
+                        uc->ports[user.port].user_idx = constnet->users.add(user);
                     } else {
                         // Connected to CIB ABCD. Default state is bitstream configurable
                         uc->params[ctx->id(user.port.str(ctx) + "MUX")] = std::string(constval ? "1" : "0");
@@ -1343,7 +1337,7 @@ class Ecp5Packer
                     }
                 } else {
                     uc->ports[user.port].net = constnet;
-                    constnet->users.push_back(user);
+                    uc->ports[user.port].user_idx = constnet->users.add(user);
                 }
             }
         }
@@ -2037,7 +2031,7 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (ci->type == id_DQSBUFM) {
                 CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_DQSI).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(id_DQSI).net->users.size() > 1)
+                if (pio == nullptr || ci->ports.at(id_DQSI).net->users.entries() > 1)
                     log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
                 if (!pio->attrs.count(id_BEL))
@@ -2273,7 +2267,7 @@ class Ecp5Packer
                 CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(id_A).net, is_trellis_io, id_O);
                 CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(id_Z).net, is_trellis_io, id_I, true);
                 CellInfo *iol = nullptr;
-                if (i_pio != nullptr && ci->ports.at(id_A).net->users.size() == 1) {
+                if (i_pio != nullptr && ci->ports.at(id_A).net->users.entries() == 1) {
                     iol = create_pio_iologic(i_pio, ci);
                     set_iologic_mode(iol, "IREG_OREG");
                     bool drives_iologic = false;
@@ -2356,7 +2350,7 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (ci->type == id_IDDRX1F) {
                 CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
+                if (pio == nullptr || ci->ports.at(id_D).net->users.entries() > 1)
                     log_error("IDDRX1F '%s' D input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2438,7 +2432,7 @@ class Ecp5Packer
                 packed_cells.insert(cell.first);
             } else if (ci->type == id_IDDRX2F || ci->type == id_IDDR71B) {
                 CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
+                if (pio == nullptr || ci->ports.at(id_D).net->users.entries() > 1)
                     log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2530,7 +2524,7 @@ class Ecp5Packer
                 packed_cells.insert(cell.first);
             } else if (ci->type == id_IDDRX2DQA) {
                 CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
-                if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
+                if (pio == nullptr || ci->ports.at(id_D).net->users.entries() > 1)
                     log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
                               ci->name.c_str(ctx));
                 CellInfo *iol;
@@ -2597,7 +2591,7 @@ class Ecp5Packer
                     // See if it can be packed as an input ff
                     NetInfo *d = ci->getPort(id_DI);
                     CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
-                    if (pio != nullptr && d->users.size() == 1) {
+                    if (pio != nullptr && d->users.entries() == 1) {
                         // Input FF
                         CellInfo *iol;
                         if (pio_iologic.count(pio->name))
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 917af85e92..a5e802d303 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1377,7 +1377,7 @@ void Arch::merge_constant_nets()
             }
 
             NPNR_ASSERT(net->driver.port == gnd_cell_port);
-            std::vector<PortRef> users_copy = net->users;
+            indexed_store<PortRef> users_copy = net->users;
             for (const PortRef &port_ref : users_copy) {
                 IdString cell = port_ref.cell->name;
                 disconnectPort(cell, port_ref.port);
@@ -1400,7 +1400,7 @@ void Arch::merge_constant_nets()
             }
 
             NPNR_ASSERT(net->driver.port == vcc_cell_port);
-            std::vector<PortRef> users_copy = net->users;
+            indexed_store<PortRef> users_copy = net->users;
             for (const PortRef &port_ref : users_copy) {
                 IdString cell = port_ref.cell->name;
                 disconnectPort(cell, port_ref.port);
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc
index 31e0522bf9..97a3e1a595 100644
--- a/fpga_interchange/arch_pack_clusters.cc
+++ b/fpga_interchange/arch_pack_clusters.cc
@@ -945,10 +945,10 @@ void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index)
                 if (port_info.type == PORT_OUT) {
                     exclude_nets.insert(port_info.net->name);
                     auto &users = port_info.net->users;
-                    if (users.size() != 1)
+                    if (users.entries() != 1)
                         continue;
 
-                    CellInfo *user_cell = users[0].cell;
+                    CellInfo *user_cell = (*users.begin()).cell;
                     if (user_cell == nullptr)
                         continue;
 
@@ -978,7 +978,7 @@ void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index)
                 } else if (port_info.type == PORT_IN) {
                     auto &driver = port_info.net->driver;
                     auto &users = port_info.net->users;
-                    if (users.size() != 1)
+                    if (users.entries() != 1)
                         continue;
 
                     CellInfo *driver_cell = driver.cell;
diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc
index ed9f73a65e..6efd1d8994 100644
--- a/fpga_interchange/globals.cc
+++ b/fpga_interchange/globals.cc
@@ -41,8 +41,8 @@ struct GlobalVist
 
 // This is our main global routing implementation. It is used both to actually route globals; and also to discover if
 // global buffers have available short routes from their source for auto-placement
-static int route_global_arc(Context *ctx, NetInfo *net, size_t usr_idx, size_t phys_port_idx, int max_hops,
-                            bool dry_run)
+static int route_global_arc(Context *ctx, NetInfo *net, store_index<PortRef> usr_idx, size_t phys_port_idx,
+                            int max_hops, bool dry_run)
 {
     auto &usr = net->users.at(usr_idx);
     WireId src = ctx->getNetinfoSourceWire(net);
@@ -51,7 +51,7 @@ static int route_global_arc(Context *ctx, NetInfo *net, size_t usr_idx, size_t p
         if (dry_run)
             return -1;
         else
-            log_error("Arc %d.%d (%s.%s) of net %s has no sink wire!\n", int(usr_idx), int(phys_port_idx),
+            log_error("Arc %d.%d (%s.%s) of net %s has no sink wire!\n", usr_idx.idx(), int(phys_port_idx),
                       ctx->nameOf(usr.cell), ctx->nameOf(usr.port), ctx->nameOf(net));
     }
     // Consider any existing routing put in place by the site router, etc
@@ -188,14 +188,6 @@ void Arch::place_globals()
             // Ignore if there is no driver; or the driver is not placed
             if (net->driver.cell == nullptr || net->driver.cell->bel == BelId())
                 continue;
-            size_t user_idx = 0;
-            bool found_user = false;
-            for (user_idx = 0; user_idx < net->users.size(); user_idx++)
-                if (net->users.at(user_idx).cell == ci && net->users.at(user_idx).port == pin_name) {
-                    found_user = true;
-                    break;
-                }
-            NPNR_ASSERT(found_user);
 
             // TODO: substantial performance improvements are probably possible, although of questionable benefit given
             // the low number of globals in a typical device...
@@ -213,7 +205,7 @@ void Arch::place_globals()
                 if (!isBelLocationValid(bel))
                     goto fail;
                 // Check distance
-                distance = route_global_arc(ctx, net, user_idx, 0, pin.max_hops, true);
+                distance = route_global_arc(ctx, net, port.user_idx, 0, pin.max_hops, true);
                 if (distance != -1 && distance < shortest_distance) {
                     best_bel = bel;
                     shortest_distance = distance;
@@ -262,16 +254,16 @@ void Arch::route_globals()
             int total_sinks = 0;
             int global_sinks = 0;
 
-            for (size_t i = 0; i < net->users.size(); i++) {
-                auto &usr = net->users.at(i);
-                for (size_t j = 0; j < ctx->getNetinfoSinkWireCount(net, usr); j++) {
-                    int result = route_global_arc(ctx, net, i, j, pin.max_hops, false);
+            for (auto usr : net->users.enumerate()) {
+                for (size_t j = 0; j < ctx->getNetinfoSinkWireCount(net, usr.value); j++) {
+                    int result = route_global_arc(ctx, net, usr.index, j, pin.max_hops, false);
                     ++total_sinks;
                     if (result != -1)
                         ++global_sinks;
                     if ((result == -1) && pin.force_routing)
                         log_error("Failed to route arc %d.%d (%s.%s) of net %s using dedicated global routing!\n",
-                                  int(i), int(j), ctx->nameOf(usr.cell), ctx->nameOf(usr.port), ctx->nameOf(net));
+                                  usr.index.idx(), int(j), ctx->nameOf(usr.value.cell), ctx->nameOf(usr.value.port),
+                                  ctx->nameOf(net));
                 }
             }
 
diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index 8ac61bbea6..a2ac219c45 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -690,7 +690,7 @@ template <typename FrontendType> struct GenericFrontend
         // Combine users
         for (auto &usr : mergee->users) {
             usr.cell->ports[usr.port].net = base;
-            base->users.push_back(usr);
+            usr.cell->ports[usr.port].user_idx = base->users.add(usr);
         }
         // Point aliases to the new net
         for (IdString alias : mergee->aliases) {
diff --git a/generic/cells.cc b/generic/cells.cc
index 76d6474f70..e4a24767f5 100644
--- a/generic/cells.cc
+++ b/generic/cells.cc
@@ -121,7 +121,7 @@ void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
         tbuf->movePortTo(ctx->id("A"), iob, ctx->id("I"));
         tbuf->movePortTo(ctx->id("E"), iob, ctx->id("EN"));
 
-        if (donet->users.size() > 1) {
+        if (donet->users.entries() > 1) {
             for (auto user : donet->users)
                 log_info("     remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
             log_error("unsupported tristate IO pattern for IO buffer '%s', "
diff --git a/generic/pack.cc b/generic/pack.cc
index cb3f58974b..428d6642b6 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -124,9 +124,10 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
             if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
                 uc->ports[user.port].net = nullptr;
+                uc->ports[user.port].user_idx = {};
             } else {
                 uc->ports[user.port].net = constnet;
-                constnet->users.push_back(user);
+                uc->ports[user.port].user_idx = constnet->users.add(user);
             }
         }
     }
@@ -224,8 +225,8 @@ static void pack_io(Context *ctx)
                          ci->type.c_str(ctx), ci->name.c_str(ctx));
                 NetInfo *net = iob->ports.at(ctx->id("PAD")).net;
                 if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
-                     net->users.size() > 1) ||
-                    (ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
+                     net->users.entries() > 1) ||
+                    (ci->type == ctx->id("$nextpnr_obuf") && (net->users.entries() > 2 || net->driver.cell != nullptr)))
                     log_error("PAD of %s '%s' connected to more than a single top level IO.\n", iob->type.c_str(ctx),
                               iob->name.c_str(ctx));
 
diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc
index bcb34e8472..864bdb456d 100644
--- a/generic/viaduct/okami/okami.cc
+++ b/generic/viaduct/okami/okami.cc
@@ -511,7 +511,7 @@ struct OkamiImpl : ViaductAPI
         const auto &ff_data = fast_cell_info.at(ff->flat_index);
         // In our example arch; the FF D can either be driven from LUT F or LUT I3
         // so either; FF D must equal LUT F or LUT I3 must be unused
-        if (ff_data.ff_d == lut_data.lut_f && lut_data.lut_f->users.size() == 1)
+        if (ff_data.ff_d == lut_data.lut_f && lut_data.lut_f->users.entries() == 1)
             return true;
         // Can't route FF and LUT output separately
         return false;
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index 10c3b8020a..a92d0de1b2 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -96,7 +96,7 @@ int ViaductHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, co
                 continue;
             if (!src_ports.count(CellTypePort(ci.type, port.first)))
                 continue;
-            if (!allow_fanout && port.second.net->users.size() > 1)
+            if (!allow_fanout && port.second.net->users.entries() > 1)
                 continue;
             for (auto &usr : port.second.net->users) {
                 if (!sink_ports.count(CellTypePort(usr)))
@@ -151,7 +151,7 @@ void ViaductHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd
         NetInfo *replace = (ni.driver.cell->type == ctx->id("VCC")) ? vcc_net : gnd_net;
         for (auto &usr : ni.users) {
             usr.cell->ports.at(usr.port).net = replace;
-            replace->users.push_back(usr);
+            usr.cell->ports.at(usr.port).user_idx = replace->users.add(usr);
         }
         trim_cells.push_back(ni.driver.cell->name);
         trim_nets.push_back(ni.name);
diff --git a/gowin/pack.cc b/gowin/pack.cc
index cc71586436..c17a20c7c5 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -68,7 +68,7 @@ static void pack_alus(Context *ctx)
                 continue;
             }
 
-            if (!is_alu(ctx, cin_ci) || cin->users.size() > 1) {
+            if (!is_alu(ctx, cin_ci) || cin->users.entries() > 1) {
                 if (ctx->verbose) {
                     log_info("ALU head found %s. CIN net is %s\n", ctx->nameOf(ci), ctx->nameOf(cin));
                 }
@@ -177,9 +177,9 @@ static void pack_alus(Context *ctx)
 
             new_cells.push_back(std::move(packed));
 
-            if (cout != nullptr && cout->users.size() > 0) {
+            if (cout != nullptr && cout->users.entries() > 0) {
                 // if COUT used by logic
-                if ((cout->users.size() > 1) || (!is_alu(ctx, cout->users.at(0).cell))) {
+                if ((cout->users.entries() > 1) || (!is_alu(ctx, (*cout->users.begin()).cell))) {
                     if (ctx->verbose) {
                         log_info("COUT is used by logic\n");
                     }
@@ -204,7 +204,7 @@ static void pack_alus(Context *ctx)
                     break;
                 }
                 // next ALU
-                ci = cout->users.at(0).cell;
+                ci = (*cout->users.begin()).cell;
                 // if ALU is too big
                 if (alu_idx == (ctx->gridDimX - 2) * 6 - 1) {
                     log_error("ALU %s is the %dth in the chain. Such long chains are not supported.\n", ctx->nameOf(ci),
@@ -596,9 +596,10 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 log_info("%s user %s\n", ctx->nameOf(orig), ctx->nameOf(uc));
             if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
                 uc->ports[user.port].net = nullptr;
+                uc->ports[user.port].user_idx = {};
             } else {
                 uc->ports[user.port].net = constnet;
-                constnet->users.push_back(user);
+                uc->ports[user.port].user_idx = constnet->users.add(user);
             }
         }
     }
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 89f8426207..48fbc1320b 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -1146,7 +1146,7 @@ bool read_asc(Context *ctx, std::istream &in)
                             if (port.second.type == PORT_OUT)
                                 net->driver = ref;
                             else
-                                net->users.push_back(ref);
+                                port.second.user_idx = net->users.add(ref);
                         }
                     }
                 }
diff --git a/ice40/cells.cc b/ice40/cells.cc
index b5f759b22c..9166b41b8d 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -466,7 +466,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         tbuf->movePortTo(id_A, sbio, id_D_OUT_0);
         tbuf->movePortTo(id_E, sbio, id_OUTPUT_ENABLE);
 
-        if (donet->users.size() > 1) {
+        if (donet->users.entries() > 1) {
             for (auto user : donet->users)
                 log_info("     remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
             log_error("unsupported tristate IO pattern for IO buffer '%s', "
diff --git a/ice40/chains.cc b/ice40/chains.cc
index e6a37044fa..6ea261de49 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -73,8 +73,8 @@ class ChainConstrainer
             } else {
                 NetInfo *carry_net = cell->ports.at(id_COUT).net;
                 bool at_end = (curr_cell == carryc.cells.end() - 1);
-                if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
-                    if (carry_net->users.size() > 2 ||
+                if (carry_net != nullptr && (carry_net->users.entries() > 1 || at_end)) {
+                    if (carry_net->users.entries() > 2 ||
                         (net_only_drives(ctx, carry_net, is_lc, id_I3, false) !=
                          net_only_drives(ctx, carry_net, is_lc, id_CIN, false)) ||
                         (at_end && !net_only_drives(ctx, carry_net, is_lc, id_I3, true))) {
@@ -116,15 +116,11 @@ class ChainConstrainer
         lc->ports.at(id_O).net = cout_port.net;
         NetInfo *co_i3_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$I3"));
         co_i3_net->driver = cout_port.net->driver;
-        PortRef i3_r;
-        i3_r.port = id_I3;
-        i3_r.cell = lc.get();
-        co_i3_net->users.push_back(i3_r);
+        lc->connectPort(id_I3, co_i3_net);
         PortRef o_r;
         o_r.port = id_O;
         o_r.cell = lc.get();
         cout_port.net->driver = o_r;
-        lc->ports.at(id_I3).net = co_i3_net;
         cout_port.net = co_i3_net;
 
         // If COUT also connects to a CIN; preserve the carry chain
@@ -133,34 +129,21 @@ class ChainConstrainer
 
             // Connect I1 to 1 to preserve carry chain
             NetInfo *vcc = ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get();
-            lc->ports.at(id_I1).net = vcc;
-            PortRef i1_r;
-            i1_r.port = id_I1;
-            i1_r.cell = lc.get();
-            vcc->users.push_back(i1_r);
+            lc->connectPort(id_I1, vcc);
 
             // Connect co_cin_net to the COUT of the LC
-            PortRef co_r;
-            co_r.port = id_COUT;
-            co_r.cell = lc.get();
-            co_cin_net->driver = co_r;
-            lc->ports.at(id_COUT).net = co_cin_net;
+            lc->connectPort(id_COUT, co_cin_net);
 
             // Find the user corresponding to the next CIN
             int replaced_ports = 0;
             if (ctx->debug)
                 log_info("cell: %s\n", cin_cell->name.c_str(ctx));
             for (auto port : {id_CIN, id_I3}) {
-                auto &usr = lc->ports.at(id_O).net->users;
-                if (ctx->debug)
-                    for (auto user : usr)
-                        log_info("%s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
-                auto fnd_user = std::find_if(usr.begin(), usr.end(),
-                                             [&](const PortRef &pr) { return pr.cell == cin_cell && pr.port == port; });
-                if (fnd_user != usr.end()) {
-                    co_cin_net->users.push_back(*fnd_user);
-                    usr.erase(fnd_user);
-                    cin_cell->ports.at(port).net = co_cin_net;
+                NetInfo *out_net = lc->ports.at(id_O).net;
+                auto &cin_p = cin_cell->ports.at(port);
+                if (cin_p.net == out_net) {
+                    cin_cell->disconnectPort(port);
+                    cin_cell->connectPort(port, co_cin_net);
                     ++replaced_ports;
                 }
             }
@@ -181,30 +164,16 @@ class ChainConstrainer
         lc->params[id_CARRY_ENABLE] = Property::State::S1;
         lc->params[id_CIN_CONST] = Property::State::S1;
         lc->params[id_CIN_SET] = Property::State::S1;
-        lc->ports.at(id_I1).net = cin_port.net;
-        cin_port.net->users.erase(std::remove_if(cin_port.net->users.begin(), cin_port.net->users.end(),
-                                                 [cin_cell, cin_port](const PortRef &usr) {
-                                                     return usr.cell == cin_cell && usr.port == cin_port.name;
-                                                 }));
 
-        PortRef i1_ref;
-        i1_ref.cell = lc.get();
-        i1_ref.port = id_I1;
-        lc->ports.at(id_I1).net->users.push_back(i1_ref);
+        lc->connectPort(id_I1, cin_port.net);
+        cin_port.net->users.remove(cin_port.user_idx);
 
         NetInfo *out_net = ctx->createNet(ctx->id(lc->name.str(ctx) + "$O"));
 
-        PortRef drv_ref;
-        drv_ref.port = id_COUT;
-        drv_ref.cell = lc.get();
-        out_net->driver = drv_ref;
-        lc->ports.at(id_COUT).net = out_net;
+        lc->connectPort(id_COUT, out_net);
 
-        PortRef usr_ref;
-        usr_ref.port = cin_port.name;
-        usr_ref.cell = cin_cell;
-        out_net->users.push_back(usr_ref);
-        cin_cell->ports.at(cin_port.name).net = out_net;
+        cin_port.net = nullptr;
+        cin_cell->connectPort(cin_port.name, out_net);
 
         IdString name = lc->name;
         ctx->assignCellInfo(lc.get());
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 4244f1921b..c32e346fcc 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -214,14 +214,14 @@ static void pack_carries(Context *ctx)
                     PortRef pr;
                     pr.cell = created_lc.get();
                     pr.port = id_I1;
-                    i0_net->users.push_back(pr);
+                    created_lc->ports.at(id_I1).user_idx = i0_net->users.add(pr);
                 }
                 created_lc->ports.at(id_I2).net = i1_net;
                 if (i1_net) {
                     PortRef pr;
                     pr.cell = created_lc.get();
                     pr.port = id_I2;
-                    i1_net->users.push_back(pr);
+                    created_lc->ports.at(id_I2).user_idx = i1_net->users.add(pr);
                 }
                 new_cells.push_back(std::move(created_lc));
                 ++carry_only;
@@ -230,16 +230,12 @@ static void pack_carries(Context *ctx)
             ci->movePortTo(id_CI, carry_lc, id_CIN);
             ci->movePortTo(id_CO, carry_lc, id_COUT);
             if (i0_net) {
-                auto &i0_usrs = i0_net->users;
-                i0_usrs.erase(std::remove_if(i0_usrs.begin(), i0_usrs.end(), [ci, ctx](const PortRef &pr) {
-                    return pr.cell == ci && pr.port == id_I0;
-                }));
+                if (ci->ports.count(id_I0) && ci->ports.at(id_I0).user_idx)
+                    i0_net->users.remove(ci->ports.at(id_I0).user_idx);
             }
             if (i1_net) {
-                auto &i1_usrs = i1_net->users;
-                i1_usrs.erase(std::remove_if(i1_usrs.begin(), i1_usrs.end(), [ci, ctx](const PortRef &pr) {
-                    return pr.cell == ci && pr.port == id_I1;
-                }));
+                if (ci->ports.count(id_I1) && ci->ports.at(id_I1).user_idx)
+                    i1_net->users.remove(ci->ports.at(id_I1).user_idx);
             }
 
             // Check for constant driver on CIN
@@ -251,10 +247,7 @@ static void pack_carries(Context *ctx)
                             cin_net == ctx->id("$PACKER_VCC_NET") ? Property::State::S1 : Property::State::S0;
                     carry_lc->ports.at(id_CIN).net = nullptr;
                     auto &cin_users = ctx->nets.at(cin_net)->users;
-                    cin_users.erase(
-                            std::remove_if(cin_users.begin(), cin_users.end(), [carry_lc, ctx](const PortRef &pr) {
-                                return pr.cell == carry_lc && pr.port == id_CIN;
-                            }));
+                    cin_users.remove(carry_lc->ports.at(id_CIN).user_idx);
                 }
             }
             exhausted_cells.insert(carry_lc->name);
@@ -326,17 +319,20 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
             if ((is_lut(ctx, uc) || is_lc(ctx, uc) || is_carry(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') &&
                 !constval) {
                 uc->ports[user.port].net = nullptr;
+                uc->ports[user.port].user_idx = {};
             } else if ((is_sb_mac16(ctx, uc) || uc->type == id_ICESTORM_DSP) &&
                        (user.port != id_CLK &&
                         ((constval && user.port == id_CE) || (!constval && user.port != id_CE)))) {
                 uc->ports[user.port].net = nullptr;
+                uc->ports[user.port].user_idx = {};
             } else if (is_ram(ctx, uc) && !constval && user.port != id_RCLK && user.port != id_RCLKN &&
                        user.port != id_WCLK && user.port != id_WCLKN && user.port != id_RCLKE &&
                        user.port != id_WCLKE) {
                 uc->ports[user.port].net = nullptr;
+                uc->ports[user.port].user_idx = {};
             } else {
                 uc->ports[user.port].net = constnet;
-                constnet->users.push_back(user);
+                uc->ports[user.port].user_idx = constnet->users.add(user);
             }
         }
     }
@@ -486,8 +482,8 @@ static void pack_io(Context *ctx)
                          ci->type.c_str(ctx), ci->name.c_str(ctx));
                 NetInfo *net = sb->ports.at(id_PACKAGE_PIN).net;
                 if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
-                     net->users.size() > 1) ||
-                    (ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
+                     net->users.entries() > 1) ||
+                    (ci->type == ctx->id("$nextpnr_obuf") && (net->users.entries() > 2 || net->driver.cell != nullptr)))
                     log_error("PACKAGE_PIN of %s '%s' connected to more than a single top level IO.\n",
                               sb->type.c_str(ctx), sb->name.c_str(ctx));
 
@@ -531,9 +527,9 @@ static void pack_io(Context *ctx)
                 sb->attrs[attr.first] = attr.second;
         } else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) {
             NetInfo *net = ci->ports.at(id_PACKAGE_PIN).net;
-            if ((net != nullptr) && ((net->users.size() > 2) ||
+            if ((net != nullptr) && ((net->users.entries() > 2) ||
                                      (net->driver.cell != nullptr &&
-                                      net->driver.cell->type == ctx->id("$nextpnr_obuf") && net->users.size() > 1)))
+                                      net->driver.cell->type == ctx->id("$nextpnr_obuf") && net->users.entries() > 1)))
                 log_error("PACKAGE_PIN of %s '%s' connected to more than a single top level IO.\n", ci->type.c_str(ctx),
                           ci->name.c_str(ctx));
         }
@@ -554,11 +550,11 @@ static void pack_io(Context *ctx)
             NetInfo *net_in0 = ci->ports.count(id_D_IN_0) ? ci->ports[id_D_IN_0].net : nullptr;
             NetInfo *net_in1 = ci->ports.count(id_D_IN_1) ? ci->ports[id_D_IN_1].net : nullptr;
 
-            if (net_in0 != nullptr && net_in0->users.size() == 0) {
+            if (net_in0 != nullptr && net_in0->users.entries() == 0) {
                 delete_nets.insert(net_in0->name);
                 ci->ports[id_D_IN_0].net = nullptr;
             }
-            if (net_in1 != nullptr && net_in1->users.size() == 0) {
+            if (net_in1 != nullptr && net_in1->users.entries() == 0) {
                 delete_nets.insert(net_in1->name);
                 ci->ports[id_D_IN_1].net = nullptr;
             }
@@ -591,28 +587,23 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
 
     std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
     std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, id_SB_GB, "$gbuf_" + glb_name);
-    gb->ports[id_USER_SIGNAL_TO_GLOBAL_BUFFER].net = net;
-    PortRef pr;
-    pr.cell = gb.get();
-    pr.port = id_USER_SIGNAL_TO_GLOBAL_BUFFER;
-    net->users.push_back(pr);
-
-    pr.cell = gb.get();
-    pr.port = id_GLOBAL_BUFFER_OUTPUT;
+    gb->connectPort(id_USER_SIGNAL_TO_GLOBAL_BUFFER, net);
     NetInfo *glbnet = ctx->createNet(ctx->id(glb_name));
-    glbnet->driver = pr;
-    gb->ports[id_GLOBAL_BUFFER_OUTPUT].net = glbnet;
+    gb->connectPort(id_GLOBAL_BUFFER_OUTPUT, glbnet);
+
     std::vector<PortRef> keep_users;
     for (auto user : net->users) {
         if (is_clock_port(ctx, user) || (is_reset && is_reset_port(ctx, user)) ||
             (is_cen && is_enable_port(ctx, user)) || (is_logic && is_logic_port(ctx, user))) {
             user.cell->ports[user.port].net = glbnet;
-            glbnet->users.push_back(user);
+            user.cell->ports[user.port].user_idx = glbnet->users.add(user);
         } else {
             keep_users.push_back(user);
         }
     }
-    net->users = keep_users;
+    net->users.clear();
+    for (auto &user : keep_users)
+        user.cell->ports[user.port].user_idx = net->users.add(user);
 
     if (net->clkconstr) {
         glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
@@ -809,7 +800,7 @@ static void place_plls(Context *ctx)
             log_error("PLL '%s' has a PACKAGEPIN driven by an %s, should be directly connected to an input "
                       "SB_IO.D_IN_0 port\n",
                       ci->name.c_str(ctx), io_cell->type.c_str(ctx));
-        if (ni->users.size() != 1)
+        if (ni->users.entries() != 1)
             log_error("PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx), ni->name.c_str(ctx));
         if (!io_cell->attrs.count(id_BEL))
             log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
@@ -911,10 +902,10 @@ static void place_plls(Context *ctx)
 
             // Used global connections
             bool gb_a_used = ci->ports.count(id_PLLOUT_A_GLOBAL) && (ci->ports[id_PLLOUT_A_GLOBAL].net != nullptr) &&
-                             (ci->ports[id_PLLOUT_A_GLOBAL].net->users.size() > 0);
+                             (ci->ports[id_PLLOUT_A_GLOBAL].net->users.entries() > 0);
             bool gb_b_used = is_sb_pll40_dual(ctx, ci) && ci->ports.count(id_PLLOUT_B_GLOBAL) &&
                              (ci->ports[id_PLLOUT_B_GLOBAL].net != nullptr) &&
-                             (ci->ports[id_PLLOUT_B_GLOBAL].net->users.size() > 0);
+                             (ci->ports[id_PLLOUT_B_GLOBAL].net->users.entries() > 0);
 
             // Check for conflict
             BelPin pll_io_a, pll_io_b;
@@ -954,15 +945,15 @@ static void place_plls(Context *ctx)
 
             // Used global connections
             bool gb_a_used = ci->ports.count(id_PLLOUT_A_GLOBAL) && (ci->ports[id_PLLOUT_A_GLOBAL].net != nullptr) &&
-                             (ci->ports[id_PLLOUT_A_GLOBAL].net->users.size() > 0);
+                             (ci->ports[id_PLLOUT_A_GLOBAL].net->users.entries() > 0);
             bool gb_b_used = is_sb_pll40_dual(ctx, ci) && ci->ports.count(id_PLLOUT_B_GLOBAL) &&
                              (ci->ports[id_PLLOUT_B_GLOBAL].net != nullptr) &&
-                             (ci->ports[id_PLLOUT_B_GLOBAL].net->users.size() > 0);
+                             (ci->ports[id_PLLOUT_B_GLOBAL].net->users.entries() > 0);
 
             // Could this be a PAD PLL ?
             bool could_be_pad = false;
             BelId pad_bel;
-            if (ni->users.size() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(id_BEL))
+            if (ni->users.entries() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(id_BEL))
                 pad_bel = ctx->getBelByNameStr(ni->driver.cell->attrs[id_BEL].as_string());
 
             // Find a BEL for it
@@ -1035,7 +1026,7 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
         PortRef pr;
         pr.cell = user.cell;
         pr.port = user.port;
-        out_net->users.push_back(pr);
+        user.cell->ports[user.port].user_idx = out_net->users.add(pr);
     }
 
     // Add LUT to new users.
@@ -1045,8 +1036,10 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     new_users.push_back(pr);
     pt->ports.at(id_I3).net = port.net;
 
-    // Replace users of the original net.
-    port.net->users = new_users;
+    // Replace users of the original net
+    port.net->users.clear();
+    for (auto &usr : new_users)
+        usr.cell->ports.at(usr.port).user_idx = port.net->users.add(usr);
 
     return pt;
 }
@@ -1235,7 +1228,7 @@ static void pack_special(Context *ctx)
                 if ((pi.name != id_RGB0) && (pi.name != id_RGB1) && (pi.name != id_RGB2))
                     continue;
 
-                if (net->users.size() > 0)
+                if (net->users.entries() > 0)
                     log_error("SB_RGB_DRV/SB_RGBA_DRV port connected to more than just package pin !\n");
 
                 ctx->nets.erase(net->name);
@@ -1585,7 +1578,7 @@ void pack_plls(Context *ctx)
                 // Only if there is actually a net ...
                 if (pi.net != nullptr) {
                     // ... and it's used
-                    if (pi.net->users.size() > 0) {
+                    if (pi.net->users.entries() > 0) {
                         std::unique_ptr<CellInfo> gb =
                                 create_padin_gbuf(ctx, packed.get(), pi.name,
                                                   "$gbuf_" + ci->name.str(ctx) + "_pllout_" + (is_b_port ? "b" : "a"));
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 5051a98123..56efb63fe5 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -160,7 +160,7 @@ static void set_net_constant(Context *ctx, NetInfo *orig, NetInfo *constnet, boo
                 uc->ports[user.port].net = constnet;
             }
 
-            constnet->users.push_back(user);
+            user.cell->ports.at(user.port).user_idx = constnet->users.add(user);
         }
     }
     orig->users.clear();
diff --git a/mistral/pack.cc b/mistral/pack.cc
index c4b3afe357..703fa386ac 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -200,10 +200,10 @@ struct MistralPacker
                 NetInfo *o = ci->getPort(id_O);
                 if (o == nullptr)
                     ;
-                else if (o->users.size() > 1)
+                else if (o->users.entries() > 1)
                     log_error("Top level pin '%s' has multiple input buffers\n", ctx->nameOf(port.first));
-                else if (o->users.size() == 1)
-                    top_port = o->users.at(0);
+                else if (o->users.entries() == 1)
+                    top_port = *o->users.begin();
             }
             if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an output buffer (OB etc) connected to it
@@ -215,9 +215,9 @@ struct MistralPacker
                     top_port = i->driver;
                 }
                 // Edge case of a bidirectional buffer driving an output pin
-                if (i->users.size() > 2) {
+                if (i->users.entries() > 2) {
                     log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
-                } else if (i->users.size() == 2) {
+                } else if (i->users.entries() == 2) {
                     if (top_port.cell != nullptr)
                         log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
                     for (auto &usr : i->users) {
@@ -300,9 +300,9 @@ struct MistralPacker
                 const NetInfo *co = cursor->getPort(id_CO);
                 if (co == nullptr || co->users.empty())
                     break;
-                if (co->users.size() > 1)
+                if (co->users.entries() > 1)
                     log_error("Carry net %s has more than one sink!\n", ctx->nameOf(co));
-                auto &usr = co->users.at(0);
+                auto &usr = *co->users.begin();
                 if (usr.port != id_CI)
                     log_error("Carry net %s drives port %s, expected CI\n", ctx->nameOf(co), ctx->nameOf(usr.port));
                 cursor = usr.cell;
diff --git a/nexus/global.cc b/nexus/global.cc
index 1c763a3100..31bf0a6b7a 100644
--- a/nexus/global.cc
+++ b/nexus/global.cc
@@ -72,7 +72,7 @@ struct NexusGlobalRouter
 
     // Dedicated backwards BFS routing for global networks
     template <typename Tfilt>
-    bool backwards_bfs_route(NetInfo *net, size_t user_idx, int iter_limit, bool strict, Tfilt pip_filter)
+    bool backwards_bfs_route(NetInfo *net, store_index<PortRef> user_idx, int iter_limit, bool strict, Tfilt pip_filter)
     {
         // Queue of wires to visit
         std::queue<WireId> visit;
@@ -178,9 +178,9 @@ struct NexusGlobalRouter
 
     void route_clk_net(NetInfo *net)
     {
-        for (size_t i = 0; i < net->users.size(); i++)
-            backwards_bfs_route(net, i, 1000000, true, [&](PipId pip) {
-                return (is_relaxed_sink(net->users.at(i)) || global_pip_filter(pip)) && routeability_pip_filter(pip);
+        for (auto usr : net->users.enumerate())
+            backwards_bfs_route(net, usr.index, 1000000, true, [&](PipId pip) {
+                return (is_relaxed_sink(usr.value) || global_pip_filter(pip)) && routeability_pip_filter(pip);
             });
         log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
     }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 5509d997e1..a769c05adc 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -489,10 +489,10 @@ struct NexusPacker
                 NetInfo *o = ci->getPort(id_O);
                 if (o == nullptr)
                     ;
-                else if (o->users.size() > 1)
+                else if (o->users.entries() > 1)
                     log_error("Top level pin '%s' has multiple input buffers\n", ctx->nameOf(port.first));
-                else if (o->users.size() == 1)
-                    top_port = o->users.at(0);
+                else if (o->users.entries() == 1)
+                    top_port = *o->users.begin();
             }
             if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
                 // Might have an output buffer (OB etc) connected to it
@@ -504,9 +504,9 @@ struct NexusPacker
                     top_port = i->driver;
                 }
                 // Edge case of a bidirectional buffer driving an output pin
-                if (i->users.size() > 2) {
+                if (i->users.entries() > 2) {
                     log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
-                } else if (i->users.size() == 2) {
+                } else if (i->users.entries() == 2) {
                     if (top_port.cell != nullptr)
                         log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
                     for (auto &usr : i->users) {
@@ -834,13 +834,15 @@ struct NexusPacker
         for (auto &usr : net->users) {
             if (pred(usr)) {
                 usr.cell->ports[usr.port].net = buffered_net;
-                buffered_net->users.push_back(usr);
+                usr.cell->ports[usr.port].user_idx = buffered_net->users.add(usr);
             } else {
                 remaining_users.push_back(usr);
             }
         }
 
-        std::swap(net->users, remaining_users);
+        net->users.clear();
+        for (auto &usr : remaining_users)
+            usr.cell->ports.at(usr.port).user_idx = net->users.add(usr);
 
         // Connect buffer input to original net
         buffer->connectPort(i, net);
@@ -1195,11 +1197,11 @@ struct NexusPacker
             if (di != nullptr && di->driver.cell != nullptr)
                 iob = di->driver.cell;
             NetInfo *dout = ci->getPort(id_DOUT);
-            if (dout != nullptr && dout->users.size() == 1)
-                iob = dout->users.at(0).cell;
+            if (dout != nullptr && dout->users.entries() == 1)
+                iob = (*dout->users.begin()).cell;
             NetInfo *tout = ci->getPort(id_TOUT);
-            if (tout != nullptr && tout->users.size() == 1)
-                iob = tout->users.at(0).cell;
+            if (tout != nullptr && tout->users.entries() == 1)
+                iob = (*tout->users.begin()).cell;
             if (iob == nullptr ||
                 (iob->type != id_SEIO18_CORE && iob->type != id_SEIO33_CORE && iob->type != id_DIFFIO18_CORE))
                 log_error("Failed to find associated IOB for IOLOGIC %s\n", ctx->nameOf(ci));
@@ -1358,11 +1360,12 @@ struct NexusPacker
                 NetInfo *fco = combs[1]->getPort(id_FCO);
                 ci = nullptr;
                 if (fco != nullptr) {
-                    if (fco->users.size() > 1)
+                    if (fco->users.entries() > 1)
                         log_error("Carry cell '%s' has multiple fanout on FCO\n", ctx->nameOf(combs[1]));
-                    else if (fco->users.size() == 1) {
-                        NPNR_ASSERT(fco->users.at(0).port == id_CIN);
-                        ci = fco->users.at(0).cell;
+                    else if (fco->users.entries() == 1) {
+                        auto &u0 = *fco->users.begin();
+                        NPNR_ASSERT(u0.port == id_CIN);
+                        ci = u0.cell;
                     }
                 }
             } while (ci != nullptr);
@@ -2161,13 +2164,13 @@ struct NexusPacker
                 isIDDR = true;
             }
             NetInfo *dout = iol->getPort(id_DOUT);
-            if (dout != nullptr && dout->users.size() == 1) {
-                iob = dout->users.at(0).cell;
+            if (dout != nullptr && dout->users.entries() == 1) {
+                iob = (*dout->users.begin()).cell;
                 isODDR = true;
             }
             NetInfo *tout = iol->getPort(id_TOUT);
-            if (tout != nullptr && tout->users.size() == 1) {
-                iob = tout->users.at(0).cell;
+            if (tout != nullptr && tout->users.entries() == 1) {
+                iob = (*tout->users.begin()).cell;
                 isODDR = true; // FIXME: Not sure
             }
             NPNR_ASSERT(iob != nullptr);
@@ -2359,7 +2362,7 @@ struct NexusPacker
             }
 
             // Skip if there are multiple sinks on that net
-            if (di->users.size() != 1) {
+            if (di->users.entries() != 1) {
                 continue;
             }
 

From 9b3e687eda12bc6ac2ce6208d046f36ca853aa67 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 28 Feb 2022 13:10:00 +0000
Subject: [PATCH 076/712] ecp5: Fix PDPW16K clock param renaming

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 2b069db098..e657e60cda 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -1454,9 +1454,9 @@ class Ecp5Packer
                 rename_param(ci, "CLKWMUX", "CLKAMUX");
                 if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
                     ci->params[id_CLKAMUX] = std::string("CLKA");
+                rename_param(ci, "CLKRMUX", "CLKBMUX");
                 if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
                     ci->params[id_CLKBMUX] = std::string("CLKB");
-                rename_param(ci, "CLKRMUX", "CLKRMUX");
                 rename_param(ci, "CSDECODE_W", "CSDECODE_A");
                 rename_param(ci, "CSDECODE_R", "CSDECODE_B");
                 std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");

From cc9f99a80c9aa9b69bc2a54060b5fbcec799f145 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 19 Dec 2021 19:29:44 +0000
Subject: [PATCH 077/712] parallel_refine: New, parallelised placement
 refinement pass

---
 common/command.cc         |  11 +
 common/parallel_refine.cc | 946 ++++++++++++++++++++++++++++++++++++++
 common/parallel_refine.h  |  43 ++
 common/placer_heap.cc     |  13 +-
 common/placer_heap.h      |   1 +
 5 files changed, 1012 insertions(+), 2 deletions(-)
 create mode 100644 common/parallel_refine.cc
 create mode 100644 common/parallel_refine.h

diff --git a/common/command.cc b/common/command.cc
index d4279a581f..5632784710 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -109,6 +109,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("debug", "debug output");
     general.add_options()("debug-placer", "debug output from placer only");
     general.add_options()("debug-router", "debug output from router only");
+    general.add_options()("threads", po::value<int>(), "number of threads for passes where this is configurable");
 
     general.add_options()("force,f", "keep running after errors");
 #ifndef NO_GUI
@@ -173,6 +174,8 @@ po::options_description CommandHandler::getGeneralOptions()
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
 
+    general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
+
     general.add_options()("router2-heatmap", po::value<std::string>(),
                           "prefix for router2 resource congestion heatmaps");
 
@@ -225,6 +228,10 @@ void CommandHandler::setupContext(Context *ctx)
         ctx->rngseed(vm["seed"].as<int>());
     }
 
+    if (vm.count("threads")) {
+        ctx->settings[ctx->id("threads")] = vm["threads"].as<int>();
+    }
+
     if (vm.count("randomize-seed")) {
         std::random_device randDev{};
         std::uniform_int_distribution<int> distrib{1};
@@ -298,6 +305,10 @@ void CommandHandler::setupContext(Context *ctx)
 
     if (vm.count("placer-heap-timingweight"))
         ctx->settings[ctx->id("placerHeap/timingWeight")] = std::to_string(vm["placer-heap-timingweight"].as<int>());
+
+    if (vm.count("parallel-refine"))
+        ctx->settings[ctx->id("placerHeap/parallelRefine")] = true;
+
     if (vm.count("router2-heatmap"))
         ctx->settings[ctx->id("router2/heatmap")] = vm["router2-heatmap"].as<std::string>();
     if (vm.count("tmg-ripup") || vm.count("router2-tmg-ripup"))
diff --git a/common/parallel_refine.cc b/common/parallel_refine.cc
new file mode 100644
index 0000000000..ea97b8521a
--- /dev/null
+++ b/common/parallel_refine.cc
@@ -0,0 +1,946 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "parallel_refine.h"
+#include "fast_bels.h"
+#include "log.h"
+#include "timing.h"
+#include "scope_lock.h"
+
+#include <chrono>
+#include <mutex>
+#include <queue>
+#include <shared_mutex>
+#include <thread>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct Partition
+{
+    int x0, y0, x1, y1;
+    std::vector<CellInfo *> cells;
+    Partition() = default;
+    explicit Partition(Context *ctx)
+    {
+        x0 = ctx->getGridDimX();
+        y0 = ctx->getGridDimY();
+        x1 = 0;
+        y1 = 0;
+        for (auto &cell : ctx->cells) {
+            Loc l = ctx->getBelLocation(cell.second->bel);
+            x0 = std::min(x0, l.x);
+            x1 = std::max(x1, l.x);
+            y0 = std::min(y0, l.y);
+            y1 = std::max(y1, l.y);
+            cells.push_back(cell.second.get());
+        }
+    }
+    void split(Context *ctx, bool yaxis, float pivot, Partition &l, Partition &r)
+    {
+        std::sort(cells.begin(), cells.end(), [&](CellInfo *a, CellInfo *b) {
+            Loc l0 = ctx->getBelLocation(a->bel), l1 = ctx->getBelLocation(b->bel);
+            return yaxis ? (l0.y < l1.y) : (l0.x < l1.x);
+        });
+        size_t pivot_point = size_t(cells.size() * pivot);
+        l.cells.clear();
+        r.cells.clear();
+        l.cells.reserve(pivot_point);
+        r.cells.reserve(cells.size() - pivot_point);
+        int pivot_coord = (pivot_point == 0) ? (yaxis ? y1 : x1)
+                                             : (yaxis ? ctx->getBelLocation(cells.at(pivot_point - 1)->bel).y
+                                                      : ctx->getBelLocation(cells.at(pivot_point - 1)->bel).x);
+        for (size_t i = 0; i < cells.size(); i++) {
+            Loc loc = ctx->getBelLocation(cells.at(i)->bel);
+            ((yaxis ? loc.y : loc.x) <= pivot_coord ? l.cells : r.cells).push_back(cells.at(i));
+        }
+        if (yaxis) {
+            l.x0 = r.x0 = x0;
+            l.x1 = r.x1 = x1;
+            l.y0 = y0;
+            l.y1 = pivot_coord;
+            r.y0 = (pivot_coord == y1) ? y1 : (pivot_coord + 1);
+            r.y1 = y1;
+        } else {
+            l.y0 = r.y0 = y0;
+            l.y1 = r.y1 = y1;
+            l.x0 = x0;
+            l.x1 = pivot_coord;
+            r.x0 = (pivot_coord == x1) ? x1 : (pivot_coord + 1);
+            r.x1 = x1;
+        }
+    }
+};
+
+typedef int64_t wirelen_t;
+
+struct NetBB
+{
+    // Actual bounding box
+    int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
+    // Number of cells at each extremity
+    int nx0 = 0, nx1 = 0, ny0 = 0, ny1 = 0;
+    wirelen_t hpwl(const ParallelRefineCfg &cfg) const
+    {
+        return wirelen_t(cfg.hpwl_scale_x * (x1 - x0) + cfg.hpwl_scale_y * (y1 - y0));
+    }
+    static NetBB compute(const Context *ctx, const NetInfo *net, const dict<IdString, BelId> *cell2bel = nullptr)
+    {
+        NetBB result{};
+        if (!net->driver.cell)
+            return result;
+        auto bel_loc = [&](const CellInfo *cell) {
+            BelId bel = cell2bel ? cell2bel->at(cell->name) : cell->bel;
+            return ctx->getBelLocation(bel);
+        };
+        result.nx0 = result.nx1 = result.ny0 = result.ny1 = 1;
+        Loc drv_loc = bel_loc(net->driver.cell);
+        result.x0 = result.x1 = drv_loc.x;
+        result.y0 = result.y1 = drv_loc.y;
+        for (auto &usr : net->users) {
+            Loc l = bel_loc(usr.cell);
+            if (l.x == result.x0)
+                ++result.nx0; // on the edge
+            else if (l.x < result.x0) {
+                result.x0 = l.x; // extends the edge
+                result.nx0 = 1;
+            }
+            if (l.x == result.x1)
+                ++result.nx1; // on the edge
+            else if (l.x > result.x1) {
+                result.x1 = l.x; // extends the edge
+                result.nx1 = 1;
+            }
+            if (l.y == result.y0)
+                ++result.ny0; // on the edge
+            else if (l.y < result.y0) {
+                result.y0 = l.y; // extends the edge
+                result.ny0 = 1;
+            }
+            if (l.y == result.y1)
+                ++result.ny1; // on the edge
+            else if (l.y > result.y1) {
+                result.y1 = l.y; // extends the edge
+                result.ny1 = 1;
+            }
+        }
+        return result;
+    }
+};
+
+struct GlobalState
+{
+    explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : ctx(ctx), cfg(cfg), bels(ctx, false, 64), tmg(ctx){};
+    Context *ctx;
+    ParallelRefineCfg cfg;
+    FastBels bels;
+    std::vector<NetInfo *> flat_nets; // flat array of all nets in the design for fast referencing by index
+    std::vector<NetBB> last_bounds;
+    std::vector<std::vector<double>> last_tmg_costs;
+    dict<IdString, NetBB> region_bounds;
+    TimingAnalyser tmg;
+
+    std::shared_timed_mutex archapi_mutex;
+
+    double temperature = 1e-7;
+    int radius = 3;
+
+    wirelen_t total_wirelen = 0;
+    double total_timing_cost = 0;
+
+    double get_timing_cost(const NetInfo *net, store_index<PortRef> user,
+                           const dict<IdString, BelId> *cell2bel = nullptr)
+    {
+        if (!net->driver.cell)
+            return 0;
+        const auto &sink = net->users.at(user);
+        IdString driver_pin, sink_pin;
+        // Pick the first pin for a prediction; assume all will be similar enouhg
+        for (auto pin : ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port)) {
+            driver_pin = pin;
+            break;
+        }
+        for (auto pin : ctx->getBelPinsForCellPin(sink.cell, sink.port)) {
+            sink_pin = pin;
+            break;
+        }
+        float crit = tmg.get_criticality(CellPortKey(sink));
+        BelId src_bel = cell2bel ? cell2bel->at(net->driver.cell->name) : net->driver.cell->bel;
+        BelId dst_bel = cell2bel ? cell2bel->at(sink.cell->name) : sink.cell->bel;
+        double delay = ctx->getDelayNS(ctx->predictDelay(src_bel, driver_pin, dst_bel, sink_pin));
+        return delay * std::pow(crit, cfg.crit_exp);
+    }
+
+    bool skip_net(const NetInfo *net) const
+    {
+        if (!net->driver.cell)
+            return true;
+        if (ctx->getBelGlobalBuf(net->driver.cell->bel))
+            return true;
+        return false;
+    }
+    bool timing_skip_net(const NetInfo *net) const
+    {
+        if (!net->driver.cell)
+            return true;
+        int cc;
+        auto cls = ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc);
+        if (cls == TMG_IGNORE || cls == TMG_GEN_CLOCK)
+            return true;
+        return false;
+    }
+    // ....
+};
+
+struct ThreadState
+{
+    Context *ctx;         // Nextpnr context pointer
+    GlobalState &g;       // Refinement engine state
+    int idx;              // Index of the thread
+    DeterministicRNG rng; // Local RNG
+    // The cell partition that the thread works on
+    Partition p;
+    // Mapping from design-wide net index to thread-wide net index -- not all nets are in all partitions, so we can
+    // optimise
+    std::vector<int> thread_net_idx;
+    // List of nets inside the partition; and their committed bounding boxes & timing costs from the thread's
+    // perspective
+    std::vector<NetInfo *> thread_nets;
+    std::vector<NetBB> net_bounds;
+    std::vector<std::vector<double>> arc_tmg_cost;
+    std::vector<bool> ignored_nets, tmg_ignored_nets;
+    bool arch_state_dirty = false;
+    // Our local cell-bel map; that won't be affected by out-of-partition moves
+    dict<IdString, BelId> local_cell2bel;
+
+    // Data on an inflight move
+    dict<IdString, std::pair<BelId, BelId>> moved_cells; // cell -> (old; new)
+    // For cluster moves only
+    std::vector<std::pair<CellInfo *, Loc>> cell_rel;
+    // For incremental wirelength and delay updates
+    wirelen_t wirelen_delta = 0;
+    double timing_delta = 0;
+
+    // Total made and accepted moved
+    int n_move = 0, n_accept = 0;
+
+    enum BoundChange
+    {
+        NO_CHANGE,
+        CELL_MOVED_INWARDS,
+        CELL_MOVED_OUTWARDS,
+        FULL_RECOMPUTE
+    };
+    // Wirelen related are handled on a per-axis basis to reduce
+    struct AxisChanges
+    {
+        std::vector<int> bounds_changed_nets;
+        std::vector<BoundChange> already_bounds_changed;
+    };
+    std::array<AxisChanges, 2> axes;
+    std::vector<NetBB> new_net_bounds;
+
+    std::vector<std::vector<bool>> already_timing_changed;
+    std::vector<std::pair<int, store_index<PortRef>>> timing_changed_arcs;
+    std::vector<double> new_timing_costs;
+
+    ThreadState(Context *ctx, GlobalState &g, int idx) : ctx(ctx), g(g), idx(idx){};
+    void set_partition(const Partition &part)
+    {
+        p = part;
+        thread_nets.clear();
+        thread_net_idx.resize(g.flat_nets.size());
+        std::fill(thread_net_idx.begin(), thread_net_idx.end(), -1);
+        // Determine the set of nets that are within the thread; and therefore we care about
+        for (auto thread_cell : part.cells) {
+            for (auto &port : thread_cell->ports) {
+                if (!port.second.net)
+                    continue;
+                int global_idx = port.second.net->udata;
+                auto &thread_idx = thread_net_idx.at(global_idx);
+                // Already added to the set
+                if (thread_idx != -1)
+                    continue;
+                thread_idx = thread_nets.size();
+                thread_nets.push_back(port.second.net);
+            }
+        }
+        tmg_ignored_nets.clear();
+        ignored_nets.clear();
+        for (auto tn : thread_nets) {
+            ignored_nets.push_back(g.skip_net(tn));
+            tmg_ignored_nets.push_back(g.timing_skip_net(tn));
+        }
+        // Set up the original cell-bel map for all nets inside the thread
+        local_cell2bel.clear();
+        for (NetInfo *net : thread_nets) {
+            if (net->driver.cell)
+                local_cell2bel[net->driver.cell->name] = net->driver.cell->bel;
+            for (auto &usr : net->users)
+                local_cell2bel[usr.cell->name] = usr.cell->bel;
+        }
+    }
+    void setup_initial_state()
+    {
+        // Setup initial net bounding boxes and timing costs
+        net_bounds.clear();
+        arc_tmg_cost.clear();
+        for (auto tn : thread_nets) {
+            net_bounds.push_back(g.last_bounds.at(tn->udata));
+            arc_tmg_cost.push_back(g.last_tmg_costs.at(tn->udata));
+        }
+        new_net_bounds = net_bounds;
+        for (int j = 0; j < 2; j++) {
+            auto &a = axes.at(j);
+            a.already_bounds_changed.resize(net_bounds.size());
+        }
+        already_timing_changed.clear();
+        already_timing_changed.resize(net_bounds.size());
+        for (size_t i = 0; i < thread_nets.size(); i++)
+            already_timing_changed.at(i) = std::vector<bool>(thread_nets.at(i)->users.capacity());
+    }
+    bool bounds_check(BelId bel)
+    {
+        Loc l = ctx->getBelLocation(bel);
+        if (l.x < p.x0 || l.x > p.x1 || l.y < p.y0 || l.y > p.y1)
+            return false;
+        return true;
+    }
+    bool bind_move()
+    {
+        std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+        for (auto &entry : moved_cells) {
+            ctx->unbindBel(entry.second.first);
+        }
+        bool success = true;
+        for (auto &entry : moved_cells) {
+            // Make sure targets are available before we bind them
+            if (!ctx->checkBelAvail(entry.second.second)) {
+                success = false;
+                break;
+            }
+            ctx->bindBel(entry.second.second, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
+        }
+        arch_state_dirty = true;
+        return success;
+    }
+    bool check_validity()
+    {
+        std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+        bool result = true;
+        for (auto e : moved_cells) {
+            if (!ctx->isBelLocationValid(e.second.first)) {
+                // Have to check old; too; as unbinding a bel could make a placement illegal by virtue of no longer
+                // enabling dedicated routes to be used
+                result = false;
+                break;
+            }
+            if (!ctx->isBelLocationValid(e.second.second)) {
+                result = false;
+                break;
+            }
+        }
+        return result;
+    }
+    void revert_move()
+    {
+        if (arch_state_dirty) {
+            // If changes to the arch state were made, revert them by restoring original cell bindings
+            std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+            for (auto &entry : moved_cells) {
+                BelId curr_bound = ctx->cells.at(entry.first)->bel;
+                if (curr_bound != BelId())
+                    ctx->unbindBel(curr_bound);
+            }
+            for (auto &entry : moved_cells) {
+                ctx->bindBel(entry.second.first, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
+            }
+            arch_state_dirty = false;
+        }
+        for (auto &entry : moved_cells)
+            local_cell2bel[entry.first] = entry.second.first;
+    }
+    void commit_move()
+    {
+        arch_state_dirty = false;
+        for (auto &axis : axes) {
+            for (auto bc : axis.bounds_changed_nets) {
+                // Commit updated net bounds
+                net_bounds.at(bc) = new_net_bounds.at(bc);
+            }
+        }
+        if (g.cfg.timing_driven) {
+            NPNR_ASSERT(timing_changed_arcs.size() == new_timing_costs.size());
+            for (size_t i = 0; i < timing_changed_arcs.size(); i++) {
+                auto arc = timing_changed_arcs.at(i);
+                arc_tmg_cost.at(arc.first).at(arc.second.idx()) = new_timing_costs.at(i);
+            }
+        }
+    }
+    void compute_changes_for_cell(CellInfo *cell, BelId old_bel, BelId new_bel)
+    {
+        Loc new_loc = ctx->getBelLocation(new_bel);
+        Loc old_loc = ctx->getBelLocation(old_bel);
+        for (const auto &port : cell->ports) {
+            NetInfo *pn = port.second.net;
+            if (!pn)
+                continue;
+            int idx = thread_net_idx.at(pn->udata);
+            if (ignored_nets.at(idx))
+                continue;
+            NetBB &new_bounds = new_net_bounds.at(idx);
+            // For the x-axis (i=0) and y-axis (i=1)
+            for (int i = 0; i < 2; i++) {
+                auto &axis = axes.at(i);
+                // New and old on this axis
+                int new_pos = i ? new_loc.y : new_loc.x, old_pos = i ? old_loc.y : old_loc.x;
+                // References to updated bounding box entries
+                auto &b0 = i ? new_bounds.y0 : new_bounds.x0;
+                auto &n0 = i ? new_bounds.ny0 : new_bounds.nx0;
+                auto &b1 = i ? new_bounds.y1 : new_bounds.x1;
+                auto &n1 = i ? new_bounds.ny1 : new_bounds.nx1;
+                auto &change = axis.already_bounds_changed.at(idx);
+                // Lower bound
+                if (new_pos < b0) {
+                    // Further out than current lower bound
+                    b0 = new_pos;
+                    n0 = 1;
+                    if (change == NO_CHANGE) {
+                        change = CELL_MOVED_OUTWARDS;
+                        axis.bounds_changed_nets.push_back(idx);
+                    }
+                } else if (new_pos == b0 && old_pos > b0) {
+                    // Moved from inside into current bound
+                    ++n0;
+                    if (change == NO_CHANGE) {
+                        change = CELL_MOVED_OUTWARDS;
+                        axis.bounds_changed_nets.push_back(idx);
+                    }
+                } else if (old_pos == b0 && new_pos > b0) {
+                    // Moved from current bound to inside
+                    if (change == NO_CHANGE)
+                        axis.bounds_changed_nets.push_back(idx);
+                    if (n0 == 1) {
+                        // Was the last cell on the bound; have to do a full recompute
+                        change = FULL_RECOMPUTE;
+                    } else {
+                        --n0;
+                        if (change == NO_CHANGE)
+                            change = CELL_MOVED_INWARDS;
+                    }
+                }
+                // Upper bound
+                if (new_pos > b1) {
+                    // Further out than current upper bound
+                    b1 = new_pos;
+                    n1 = new_pos;
+                    if (change == NO_CHANGE) {
+                        change = CELL_MOVED_OUTWARDS;
+                        axis.bounds_changed_nets.push_back(idx);
+                    }
+                } else if (new_pos == b1 && old_pos < b1) {
+                    // Moved onto current bound
+                    ++n1;
+                    if (change == NO_CHANGE) {
+                        change = CELL_MOVED_OUTWARDS;
+                        axis.bounds_changed_nets.push_back(idx);
+                    }
+                } else if (old_pos == b1 && new_pos < b1) {
+                    // Moved from current bound to inside
+                    if (change == NO_CHANGE)
+                        axis.bounds_changed_nets.push_back(idx);
+                    if (n1 == 1) {
+                        // Was the last cell on the bound; have to do a full recompute
+                        change = FULL_RECOMPUTE;
+                    } else {
+                        --n1;
+                        if (change == NO_CHANGE)
+                            change = CELL_MOVED_INWARDS;
+                    }
+                }
+            }
+            // Timing updates if timing driven
+            if (g.cfg.timing_driven && !tmg_ignored_nets.at(idx)) {
+                if (port.second.type == PORT_OUT) {
+                    int cc;
+                    TimingPortClass cls = ctx->getPortTimingClass(cell, port.first, cc);
+                    if (cls != TMG_IGNORE) {
+                        for (auto usr : pn->users.enumerate())
+                            if (!already_timing_changed.at(idx).at(usr.index.idx())) {
+                                timing_changed_arcs.emplace_back(std::make_pair(idx, usr.index));
+                                already_timing_changed.at(idx).at(usr.index.idx()) = true;
+                            }
+                    }
+                } else {
+                    auto usr = port.second.user_idx;
+                    if (!already_timing_changed.at(idx).at(usr.idx())) {
+                        timing_changed_arcs.emplace_back(std::make_pair(idx, usr));
+                        already_timing_changed.at(idx).at(usr.idx()) = true;
+                    }
+                }
+            }
+        }
+    }
+    void compute_total_change()
+    {
+        auto &xa = axes.at(0), &ya = axes.at(1);
+        for (auto &bc : xa.bounds_changed_nets)
+            if (xa.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
+                new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
+        for (auto &bc : ya.bounds_changed_nets)
+            if (xa.already_bounds_changed.at(bc) != FULL_RECOMPUTE &&
+                ya.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
+                new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
+        for (auto &bc : xa.bounds_changed_nets)
+            wirelen_delta += (new_net_bounds.at(bc).hpwl(g.cfg) - net_bounds.at(bc).hpwl(g.cfg));
+        for (auto &bc : ya.bounds_changed_nets)
+            if (xa.already_bounds_changed.at(bc) == NO_CHANGE)
+                wirelen_delta += (new_net_bounds.at(bc).hpwl(g.cfg) - net_bounds.at(bc).hpwl(g.cfg));
+        if (g.cfg.timing_driven) {
+            NPNR_ASSERT(new_timing_costs.empty());
+            for (auto arc : timing_changed_arcs) {
+                double new_cost = g.get_timing_cost(thread_nets.at(arc.first), arc.second, &local_cell2bel);
+                timing_delta += (new_cost - arc_tmg_cost.at(arc.first).at(arc.second.idx()));
+                new_timing_costs.push_back(new_cost);
+            }
+        }
+    }
+    void reset_move_state()
+    {
+        moved_cells.clear();
+        cell_rel.clear();
+        for (auto &axis : axes) {
+            for (auto bc : axis.bounds_changed_nets) {
+                new_net_bounds.at(bc) = net_bounds.at(bc);
+                axis.already_bounds_changed[bc] = NO_CHANGE;
+            }
+            axis.bounds_changed_nets.clear();
+        }
+        for (auto &arc : timing_changed_arcs) {
+            already_timing_changed.at(arc.first).at(arc.second.idx()) = false;
+        }
+        timing_changed_arcs.clear();
+        new_timing_costs.clear();
+        wirelen_delta = 0;
+        timing_delta = 0;
+    }
+
+    bool accept_move()
+    {
+        double delta = g.cfg.lambda * (timing_delta / std::max<double>(epsilon, g.total_timing_cost)) +
+                       (1.0 - g.cfg.lambda) * (double(wirelen_delta) / std::max<double>(epsilon, g.total_wirelen));
+        return delta < 0 ||
+               (g.temperature > 1e-8 && (rng.rng() / float(0x3fffffff)) <= std::exp(-delta / g.temperature));
+    }
+
+    bool add_to_move(CellInfo *cell, BelId old_bel, BelId new_bel)
+    {
+        if (!bounds_check(old_bel) || !bounds_check(new_bel))
+            return false;
+        if (!ctx->isValidBelForCellType(cell->type, new_bel))
+            return false;
+        NPNR_ASSERT(!moved_cells.count(cell->name));
+        moved_cells[cell->name] = std::make_pair(old_bel, new_bel);
+        local_cell2bel[cell->name] = new_bel;
+        compute_changes_for_cell(cell, old_bel, new_bel);
+        return true;
+    }
+
+    static constexpr double epsilon = 1e-20;
+    bool single_cell_swap(CellInfo *cell, BelId new_bel)
+    {
+        NPNR_ASSERT(moved_cells.empty());
+        BelId old_bel = cell->bel;
+        CellInfo *bound = ctx->getBoundBelCell(new_bel);
+        if (bound && (bound->belStrength > STRENGTH_STRONG || bound->cluster != ClusterId()))
+            return false;
+        if (!add_to_move(cell, old_bel, new_bel))
+            goto fail;
+        if (bound && !add_to_move(bound, new_bel, old_bel))
+            goto fail;
+        compute_total_change();
+        // SA acceptance criteria
+
+        if (!accept_move()) {
+            // SA fail
+            goto fail;
+        }
+        // Check validity rules
+        if (!bind_move())
+            goto fail;
+        if (!check_validity())
+            goto fail;
+        // Accepted!
+        commit_move();
+        reset_move_state();
+        return true;
+    fail:
+        revert_move();
+        reset_move_state();
+        return false;
+    }
+
+    bool chain_swap(CellInfo *root_cell, BelId new_root_bel)
+    {
+        NPNR_ASSERT(moved_cells.empty());
+        std::queue<std::pair<ClusterId, BelId>> displaced_clusters;
+        pool<BelId> used_bels;
+        displaced_clusters.emplace(root_cell->cluster, new_root_bel);
+        while (!displaced_clusters.empty()) {
+            std::vector<std::pair<CellInfo *, BelId>> dest_bels;
+            auto cursor = displaced_clusters.front();
+            displaced_clusters.pop();
+            if (!ctx->getClusterPlacement(cursor.first, cursor.second, dest_bels))
+                goto fail;
+            for (const auto &db : dest_bels) {
+                BelId old_bel = db.first->bel;
+                if (moved_cells.count(db.first->name))
+                    goto fail;
+                if (!add_to_move(db.first, old_bel, db.second))
+                    goto fail;
+                if (used_bels.count(db.second))
+                    goto fail;
+                used_bels.insert(db.second);
+
+                CellInfo *bound = ctx->getBoundBelCell(db.second);
+                if (bound) {
+                    if (moved_cells.count(bound->name)) {
+                        // Don't move a cell multiple times in the same go
+                        goto fail;
+                    } else if (bound->belStrength > STRENGTH_STRONG) {
+                        goto fail;
+                    } else if (bound->cluster != ClusterId()) {
+                        // Displace the entire cluster
+                        Loc old_loc = ctx->getBelLocation(old_bel);
+                        Loc bound_loc = ctx->getBelLocation(bound->bel);
+                        Loc root_loc = ctx->getBelLocation(ctx->getClusterRootCell(bound->cluster)->bel);
+                        BelId new_root = ctx->getBelByLocation(Loc(old_loc.x + (root_loc.x - bound_loc.x),
+                                                                   old_loc.y + (root_loc.y - bound_loc.y),
+                                                                   old_loc.z + (root_loc.z - bound_loc.z)));
+                        if (new_root == BelId())
+                            goto fail;
+                        displaced_clusters.emplace(bound->cluster, new_root);
+                    } else {
+                        // Single cell swap
+                        if (used_bels.count(old_bel))
+                            goto fail;
+                        used_bels.insert(old_bel);
+                        if (!add_to_move(bound, bound->bel, old_bel))
+                            goto fail;
+                    }
+                } else if (!ctx->checkBelAvail(db.second)) {
+                    goto fail;
+                }
+            }
+        }
+        compute_total_change();
+        // SA acceptance criteria
+
+        if (!accept_move()) {
+            // SA fail
+            goto fail;
+        }
+        // Check validity rules
+        if (!bind_move())
+            goto fail;
+        if (!check_validity())
+            goto fail;
+        // Accepted!
+        commit_move();
+        reset_move_state();
+        return true;
+    fail:
+        revert_move();
+        reset_move_state();
+        return false;
+    }
+
+    BelId random_bel_for_cell(CellInfo *cell, int force_z = -1)
+    {
+        IdString targetType = cell->type;
+        Loc curr_loc = ctx->getBelLocation(cell->bel);
+        int count = 0;
+
+        int dx = g.radius, dy = g.radius;
+        if (cell->region != nullptr && cell->region->constr_bels) {
+            dx = std::min(g.cfg.hpwl_scale_x * g.radius,
+                          (g.region_bounds[cell->region->name].x1 - g.region_bounds[cell->region->name].x0) + 1);
+            dy = std::min(g.cfg.hpwl_scale_y * g.radius,
+                          (g.region_bounds[cell->region->name].y1 - g.region_bounds[cell->region->name].y0) + 1);
+            // Clamp location to within bounds
+            curr_loc.x = std::max(g.region_bounds[cell->region->name].x0, curr_loc.x);
+            curr_loc.x = std::min(g.region_bounds[cell->region->name].x1, curr_loc.x);
+            curr_loc.y = std::max(g.region_bounds[cell->region->name].y0, curr_loc.y);
+            curr_loc.y = std::min(g.region_bounds[cell->region->name].y1, curr_loc.y);
+        }
+
+        FastBels::FastBelsData *bel_data;
+        auto type_cnt = g.bels.getBelsForCellType(targetType, &bel_data);
+
+        while (true) {
+            int nx = rng.rng(2 * dx + 1) + std::max(curr_loc.x - dx, 0);
+            int ny = rng.rng(2 * dy + 1) + std::max(curr_loc.y - dy, 0);
+            if (type_cnt < 64)
+                nx = ny = 0;
+            if (nx >= int(bel_data->size()))
+                continue;
+            if (ny >= int(bel_data->at(nx).size()))
+                continue;
+            const auto &fb = bel_data->at(nx).at(ny);
+            if (fb.size() == 0)
+                continue;
+            BelId bel = fb.at(rng.rng(int(fb.size())));
+            if (!bounds_check(bel))
+                continue;
+            if (force_z != -1) {
+                Loc loc = ctx->getBelLocation(bel);
+                if (loc.z != force_z)
+                    continue;
+            }
+            if (!cell->testRegion(bel))
+                continue;
+            count++;
+            return bel;
+        }
+    }
+
+    void run_iter()
+    {
+        setup_initial_state();
+        n_accept = 0;
+        n_move = 0;
+        for (int m = 0; m < g.cfg.inner_iters; m++) {
+            for (auto cell : p.cells) {
+                if (cell->belStrength > STRENGTH_STRONG)
+                    continue;
+                if (cell->cluster != ClusterId()) {
+                    if (cell != ctx->getClusterRootCell(cell->cluster))
+                        continue; // only move cluster root
+                    Loc old_loc = ctx->getBelLocation(cell->bel);
+                    BelId new_root = random_bel_for_cell(cell, old_loc.z);
+                    if (new_root == BelId() || new_root == cell->bel)
+                        continue;
+                    ++n_move;
+                    if (chain_swap(cell, new_root))
+                        ++n_accept;
+                } else {
+                    BelId new_bel = random_bel_for_cell(cell);
+                    if (new_bel == BelId() || new_bel == cell->bel)
+                        continue;
+                    ++n_move;
+                    if (single_cell_swap(cell, new_bel))
+                        ++n_accept;
+                }
+            }
+        }
+    }
+};
+
+struct ParallelRefine
+{
+    Context *ctx;
+    GlobalState g;
+    std::vector<ThreadState> t;
+    ParallelRefine(Context *ctx, ParallelRefineCfg cfg) : ctx(ctx), g(ctx, cfg)
+    {
+        g.flat_nets.reserve(ctx->nets.size());
+        for (auto &net : ctx->nets) {
+            net.second->udata = g.flat_nets.size();
+            g.flat_nets.push_back(net.second.get());
+        }
+        // Setup per thread context
+        for (int i = 0; i < cfg.threads; i++) {
+            t.emplace_back(ctx, g, i);
+        }
+        // Setup region bounds
+        for (auto &region : ctx->region) {
+            Region *r = region.second.get();
+            NetBB bb;
+            if (r->constr_bels) {
+                bb.x0 = std::numeric_limits<int>::max();
+                bb.x1 = std::numeric_limits<int>::min();
+                bb.y0 = std::numeric_limits<int>::max();
+                bb.y1 = std::numeric_limits<int>::min();
+                for (auto bel : r->bels) {
+                    Loc loc = ctx->getBelLocation(bel);
+                    bb.x0 = std::min(bb.x0, loc.x);
+                    bb.x1 = std::max(bb.x1, loc.x);
+                    bb.y0 = std::min(bb.y0, loc.y);
+                    bb.y1 = std::max(bb.y1, loc.y);
+                }
+            } else {
+                bb.x0 = 0;
+                bb.y0 = 0;
+                bb.x1 = ctx->getGridDimX();
+                bb.y1 = ctx->getGridDimY();
+            }
+            g.region_bounds[r->name] = bb;
+        }
+        // Setup fast bels map
+        pool<IdString> cell_types_in_use;
+        for (auto &cell : ctx->cells) {
+            IdString cell_type = cell.second->type;
+            cell_types_in_use.insert(cell_type);
+        }
+
+        for (auto cell_type : cell_types_in_use) {
+            g.bels.addCellType(cell_type);
+        }
+    };
+    std::vector<Partition> parts;
+    void do_partition()
+    {
+        parts.clear();
+        parts.emplace_back(ctx);
+        bool yaxis = false;
+        while (parts.size() < t.size()) {
+            std::vector<Partition> next(parts.size() * 2);
+            for (size_t i = 0; i < parts.size(); i++) {
+                // Randomly permute pivot every iteration so we get different thread boundaries
+                const float delta = 0.1;
+                float pivot = (0.5 - (delta / 2)) + (delta / 2) * (ctx->rng(10000) / 10000.0f);
+                parts.at(i).split(ctx, yaxis, pivot, next.at(i * 2), next.at(i * 2 + 1));
+            }
+            std::swap(parts, next);
+            yaxis = !yaxis;
+        }
+
+        NPNR_ASSERT(parts.size() == t.size());
+        // TODO: thread pool to make this worthwhile...
+        std::vector<std::thread> workers;
+        for (size_t i = 0; i < t.size(); i++) {
+            workers.emplace_back([i, this]() { t.at(i).set_partition(parts.at(i)); });
+        }
+        for (auto &w : workers)
+            w.join();
+    }
+
+    void update_global_costs()
+    {
+        g.last_bounds.resize(g.flat_nets.size());
+        g.last_tmg_costs.resize(g.flat_nets.size());
+        g.total_wirelen = 0;
+        g.total_timing_cost = 0;
+        for (size_t i = 0; i < g.flat_nets.size(); i++) {
+            NetInfo *ni = g.flat_nets.at(i);
+            if (g.skip_net(ni))
+                continue;
+            g.last_bounds.at(i) = NetBB::compute(ctx, ni);
+            g.total_wirelen += g.last_bounds.at(i).hpwl(g.cfg);
+            if (!g.timing_skip_net(ni)) {
+                auto &tc = g.last_tmg_costs.at(i);
+                tc.resize(ni->users.capacity());
+                for (auto usr : ni->users.enumerate()) {
+                    tc.at(usr.index.idx()) = g.get_timing_cost(ni, usr.index);
+                    g.total_timing_cost += tc.at(usr.index.idx());
+                }
+            }
+        }
+    }
+    void run()
+    {
+
+        ScopeLock<Context> lock(ctx);
+        auto refine_start = std::chrono::high_resolution_clock::now();
+
+        g.tmg.setup_only = true;
+        g.tmg.setup();
+        do_partition();
+        log_info("Running parallel refinement with %d threads.\n", int(t.size()));
+        int iter = 1;
+        bool done = false;
+        update_global_costs();
+        double avg_wirelen = g.total_wirelen;
+        wirelen_t min_wirelen = g.total_wirelen;
+        while (true) {
+            if (iter > 1) {
+                if (g.total_wirelen >= min_wirelen) {
+                    done = true;
+                } else if (g.total_wirelen < min_wirelen) {
+                    min_wirelen = g.total_wirelen;
+                }
+                int n_accept = 0, n_move = 0;
+                for (auto &t_data : t) {
+                    n_accept += t_data.n_accept;
+                    n_move += t_data.n_move;
+                }
+                double r_accept = n_accept / double(n_move);
+                if (g.total_wirelen < (0.95 * avg_wirelen) && g.total_wirelen > 0) {
+                    avg_wirelen = 0.8 * avg_wirelen + 0.2 * g.total_wirelen;
+                } else {
+                    if (r_accept > 0.15 && g.radius > 1) {
+                        g.temperature *= 0.95;
+                    } else {
+                        g.temperature *= 0.8;
+                    }
+                }
+                if ((iter % 10) == 0 && g.radius > 1)
+                    --g.radius;
+            }
+
+            if ((iter == 1) || ((iter % 5) == 0) || done)
+                log_info("  at iteration #%d: temp = %f, timing cost = "
+                         "%.0f, wirelen = %.0f\n",
+                         iter, g.temperature, double(g.total_timing_cost), double(g.total_wirelen));
+
+            if (done)
+                break;
+
+            do_partition();
+
+            std::vector<std::thread> workers;
+            workers.reserve(t.size());
+            for (int j = 0; j < int(t.size()); j++)
+                workers.emplace_back([this, j]() { t.at(j).run_iter(); });
+            for (auto &w : workers)
+                w.join();
+            g.tmg.run();
+            update_global_costs();
+            iter++;
+            ctx->yield();
+        }
+        auto refine_end = std::chrono::high_resolution_clock::now();
+        log_info("Placement refine time %.02fs\n", std::chrono::duration<float>(refine_end - refine_start).count());
+    }
+};
+} // namespace
+
+ParallelRefineCfg::ParallelRefineCfg(Context *ctx)
+{
+    timing_driven = ctx->setting<bool>("timing_driven");
+    threads = ctx->setting<int>("threads", 8);
+    // snap to nearest power of two; and minimum thread size
+    int actual_threads = 1;
+    while ((actual_threads * 2) <= threads && (int(ctx->cells.size()) / (actual_threads * 2)) >= min_thread_size)
+        actual_threads *= 2;
+    threads = actual_threads;
+    hpwl_scale_x = 1;
+    hpwl_scale_y = 1;
+}
+
+bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
+{
+    // TODO
+    ParallelRefine refine(ctx, cfg);
+    refine.run();
+    timing_analysis(ctx);
+    return true;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/parallel_refine.h b/common/parallel_refine.h
new file mode 100644
index 0000000000..556317cd19
--- /dev/null
+++ b/common/parallel_refine.h
@@ -0,0 +1,43 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef PARALLEL_REFINE_H
+#define PARALLEL_REFINE_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct ParallelRefineCfg
+{
+    ParallelRefineCfg(Context *ctx);
+    bool timing_driven;
+    int threads;
+    int hpwl_scale_x, hpwl_scale_y;
+    double lambda = 0.5f;
+    float crit_exp = 8;
+    int inner_iters = 15;
+    int min_thread_size = 500;
+};
+
+bool parallel_refine(Context *ctx, ParallelRefineCfg cfg);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/common/placer_heap.cc b/common/placer_heap.cc
index 5b43dc7257..5ffb764254 100644
--- a/common/placer_heap.cc
+++ b/common/placer_heap.cc
@@ -46,6 +46,7 @@
 #include "fast_bels.h"
 #include "log.h"
 #include "nextpnr.h"
+#include "parallel_refine.h"
 #include "place_common.h"
 #include "placer1.h"
 #include "scope_lock.h"
@@ -346,8 +347,14 @@ class HeAPPlacer
         ctx->check();
         lock.unlock_early();
 
-        if (!placer1_refine(ctx, Placer1Cfg(ctx))) {
-            return false;
+        if (cfg.parallelRefine) {
+            if (!parallel_refine(ctx, ParallelRefineCfg(ctx))) {
+                return false;
+            }
+        } else {
+            if (!placer1_refine(ctx, Placer1Cfg(ctx))) {
+                return false;
+            }
         }
 
         return true;
@@ -1786,6 +1793,8 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
     beta = ctx->setting<float>("placerHeap/beta");
     criticalityExponent = ctx->setting<int>("placerHeap/criticalityExponent");
     timingWeight = ctx->setting<int>("placerHeap/timingWeight");
+    parallelRefine = ctx->setting<bool>("placerHeap/parallelRefine", false);
+
     timing_driven = ctx->setting<bool>("timing_driven");
     solverTolerance = 1e-5;
     placeAllAtOnce = false;
diff --git a/common/placer_heap.h b/common/placer_heap.h
index bb40a12669..9c62869e9d 100644
--- a/common/placer_heap.h
+++ b/common/placer_heap.h
@@ -41,6 +41,7 @@ struct PlacerHeapCfg
     bool timing_driven;
     float solverTolerance;
     bool placeAllAtOnce;
+    bool parallelRefine;
 
     int hpwl_scale_x, hpwl_scale_y;
     int spread_scale_x, spread_scale_y;

From c93a3f35aca4399c290840f150f713aa81a515bb Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 4 Mar 2022 16:19:16 +1000
Subject: [PATCH 078/712] gowin: BUGFIX gui crash

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index af85146799..e6ee826720 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -209,6 +209,16 @@ void Arch::addWire(IdString name, IdString type, int x, int y)
     wi.y = y;
 
     wire_ids.push_back(name);
+
+    // Needed to ensure empty tile bel locations
+    if (int(bels_by_tile.size()) <= x)
+        bels_by_tile.resize(x + 1);
+    if (int(bels_by_tile[x].size()) <= y)
+        bels_by_tile[x].resize(y + 1);
+    if (int(tileBelDimZ.size()) <= x)
+        tileBelDimZ.resize(x + 1);
+    if (int(tileBelDimZ[x].size()) <= y)
+        tileBelDimZ[x].resize(y + 1);
 }
 
 void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayQuad delay, Loc loc)

From b5d6fc8ed7bc446b1d810c82029e7b327bea5049 Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Fri, 4 Mar 2022 16:53:03 +0100
Subject: [PATCH 079/712] interchange: lut map cache: remove hardcoded values

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 fpga_interchange/arch.cc                   |  9 +++++++++
 fpga_interchange/arch.h                    |  5 +++++
 fpga_interchange/site_lut_mapping_cache.cc |  7 ++++---
 fpga_interchange/site_lut_mapping_cache.h  | 12 +++---------
 4 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index a5e802d303..e55c94afe9 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -224,10 +224,14 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
 
     // Initially LutElement vectors for each tile type.
     tile_type_index = 0;
+    max_lut_cells = 0;
+    max_lut_pins = 0;
     lut_elements.resize(chip_info->tile_types.size());
     for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
         std::vector<LutElement> &elements = lut_elements[tile_type_index++];
         elements.reserve(tile_type.lut_elements.size());
+
+        int lut_cells_count = 0;
         for (auto &lut_element : tile_type.lut_elements) {
             elements.emplace_back();
 
@@ -252,10 +256,15 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
                 }
 
                 lut.output_pin = IdString(lut_bel.out_pin);
+                lut_cells_count++;
+
+                max_lut_pins = std::max((int)lut_bel.pins.size(), max_lut_pins);
             }
 
             element.compute_pin_order();
         }
+
+        max_lut_cells = std::max(lut_cells_count, max_lut_cells);
     }
 
     // Map lut cell types to their LutCellPOD
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 8bb2e2d149..7887745283 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -1134,6 +1134,11 @@ struct Arch : ArchAPI<ArchRanges>
     IdString vcc_cell_pin;
     std::vector<std::vector<LutElement>> lut_elements;
     dict<IdString, const LutCellPOD *> lut_cells;
+    
+    // Defines the max number of LUT cells in a site and LUT pins
+    // to allow a correct functioning of the site lut mapping cache
+    int max_lut_cells;
+    int max_lut_pins;
 
     // Of the LUT cells, which is used for wires?
     // Note: May be null in arch's without wire LUT types.  Assumption is
diff --git a/fpga_interchange/site_lut_mapping_cache.cc b/fpga_interchange/site_lut_mapping_cache.cc
index 0cf741f280..b7a71397c9 100644
--- a/fpga_interchange/site_lut_mapping_cache.cc
+++ b/fpga_interchange/site_lut_mapping_cache.cc
@@ -58,6 +58,7 @@ SiteLutMappingKey SiteLutMappingKey::create(const SiteInformation &siteInfo)
     key.tileType = siteInfo.tile_type;
     key.siteType = ctx->chip_info->sites[siteInfo.site].site_type;
     key.numCells = 0;
+    key.cells.resize(ctx->max_lut_cells);
 
     // Get bound nets. Store localized (to the LUT cluster) net indices only
     // to get always the same key for the same LUT port configuration even
@@ -65,13 +66,13 @@ SiteLutMappingKey SiteLutMappingKey::create(const SiteInformation &siteInfo)
     dict<IdString, int32_t> netMap;
     for (CellInfo *cellInfo : lutCells) {
 
-        NPNR_ASSERT(key.numCells < SiteLutMappingKey::MAX_LUT_CELLS);
+        NPNR_ASSERT(key.numCells < key.cells.size());
         auto &cell = key.cells[key.numCells++];
 
         cell.type = cellInfo->type;
         cell.belIndex = cellInfo->bel.index;
 
-        cell.conns.fill(0);
+        cell.conns.resize(ctx->max_lut_pins, 0);
 
         size_t portId = 0;
         for (const auto &port : cellInfo->ports) {
@@ -96,7 +97,7 @@ SiteLutMappingKey SiteLutMappingKey::create(const SiteInformation &siteInfo)
                 }
             }
 
-            NPNR_ASSERT(portId < SiteLutMappingKey::MAX_LUT_INPUTS);
+            NPNR_ASSERT(portId < cell.conns.size());
             cell.conns[portId++] = netId;
         }
     }
diff --git a/fpga_interchange/site_lut_mapping_cache.h b/fpga_interchange/site_lut_mapping_cache.h
index 7b1d60a42f..3efd040f8d 100644
--- a/fpga_interchange/site_lut_mapping_cache.h
+++ b/fpga_interchange/site_lut_mapping_cache.h
@@ -29,12 +29,6 @@ NEXTPNR_NAMESPACE_BEGIN
 // Key structure used in site LUT mapping cache
 struct SiteLutMappingKey
 {
-
-    // Maximum number of LUT cells per site
-    static constexpr size_t MAX_LUT_CELLS = 8;
-    // Maximum number of LUT inputs per cell
-    static constexpr size_t MAX_LUT_INPUTS = 6;
-
     // LUT Cell data
     struct Cell
     {
@@ -44,7 +38,7 @@ struct SiteLutMappingKey
         // Port to net assignments. These are local net ids generated during
         // key creation. This is to abstract connections from actual design
         // net names. the Id 0 means unconnected.
-        std::array<int32_t, MAX_LUT_INPUTS> conns;
+        std::vector<int32_t> conns;
 
         bool operator==(const Cell &other) const
         {
@@ -60,7 +54,7 @@ struct SiteLutMappingKey
     int32_t tileType;                      // Tile type
     int32_t siteType;                      // Site type in that tile type
     size_t numCells;                       // LUT cell count
-    std::array<Cell, MAX_LUT_CELLS> cells; // LUT cell data
+    std::vector<Cell> cells; // LUT cell data
 
     unsigned int hash_; // Precomputed hash
 
@@ -80,7 +74,7 @@ struct SiteLutMappingKey
             const auto &cell = cells[j];
             hash_ = mkhash(hash_, cell.type.index);
             hash_ = mkhash(hash_, cell.belIndex);
-            for (size_t i = 0; i < MAX_LUT_INPUTS; ++i) {
+            for (size_t i = 0; i < cell.conns.size(); ++i) {
                 hash_ = mkhash(hash_, cell.conns[i]);
             }
         }

From aee35768f4002c0a7d96ba79e5aa78632fb41c65 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Sat, 5 Mar 2022 16:32:44 +0000
Subject: [PATCH 080/712] Disable parallel refinement on WebAssembly.

---
 common/command.cc         |  2 ++
 common/parallel_refine.cc | 18 +++++++++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/common/command.cc b/common/command.cc
index 5632784710..2167deb92b 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -174,7 +174,9 @@ po::options_description CommandHandler::getGeneralOptions()
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
 
+#if !defined(__wasm)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
+#endif
 
     general.add_options()("router2-heatmap", po::value<std::string>(),
                           "prefix for router2 resource congestion heatmaps");
diff --git a/common/parallel_refine.cc b/common/parallel_refine.cc
index ea97b8521a..c2905480ca 100644
--- a/common/parallel_refine.cc
+++ b/common/parallel_refine.cc
@@ -18,8 +18,11 @@
  */
 
 #include "parallel_refine.h"
-#include "fast_bels.h"
 #include "log.h"
+
+#if !defined(__wasm)
+
+#include "fast_bels.h"
 #include "timing.h"
 #include "scope_lock.h"
 
@@ -944,3 +947,16 @@ bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
 }
 
 NEXTPNR_NAMESPACE_END
+
+#else /* !defined(__wasm) */
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
+{
+    log_abort();
+}
+
+NEXTPNR_NAMESPACE_END
+
+#endif

From 626eccdb89884b9e4792bdf3c74f72cbb363e9b9 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Tue, 8 Mar 2022 17:24:29 +0000
Subject: [PATCH 081/712] Add missing part of commit aee35768.

---
 common/placer_heap.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/common/placer_heap.cc b/common/placer_heap.cc
index 5ffb764254..4c9ffb2326 100644
--- a/common/placer_heap.cc
+++ b/common/placer_heap.cc
@@ -347,11 +347,14 @@ class HeAPPlacer
         ctx->check();
         lock.unlock_early();
 
+#if !defined(__wasm)
         if (cfg.parallelRefine) {
             if (!parallel_refine(ctx, ParallelRefineCfg(ctx))) {
                 return false;
             }
-        } else {
+        } else
+#endif
+        {
             if (!placer1_refine(ctx, Placer1Cfg(ctx))) {
                 return false;
             }

From 191be632e23b26fa9eae484b04dde0ad5af35e39 Mon Sep 17 00:00:00 2001
From: Maciej Dudek <mdudek@antmicro.com>
Date: Wed, 9 Mar 2022 14:13:29 +0100
Subject: [PATCH 082/712] nexus: DCCs cannot be cascaded This commit solves
 implicit cascading when clock signal drives DCC and logic

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
---
 nexus/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index a769c05adc..bff50d8906 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -883,7 +883,7 @@ struct NexusPacker
         for (size_t i = 0; i < std::min<size_t>(clk_fanout.size(), available_globals); i++) {
             NetInfo *net = ctx->nets.at(clk_fanout.at(i).second).get();
             log_info("     promoting clock net '%s'\n", ctx->nameOf(net));
-            insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO, [](const PortRef &port) { return true; });
+            insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO, [&](const PortRef &port) { return port.cell->type != id_DCC; });
         }
     }
 

From df7e26c1aa9b8727bacf56ab0d592df5cef63bb5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 9 Mar 2022 17:12:59 +0000
Subject: [PATCH 083/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/parallel_refine.cc                 | 7 ++-----
 fpga_interchange/arch.h                   | 2 +-
 fpga_interchange/site_lut_mapping_cache.h | 6 +++---
 nexus/pack.cc                             | 3 ++-
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/common/parallel_refine.cc b/common/parallel_refine.cc
index c2905480ca..bc665cd3ca 100644
--- a/common/parallel_refine.cc
+++ b/common/parallel_refine.cc
@@ -23,8 +23,8 @@
 #if !defined(__wasm)
 
 #include "fast_bels.h"
-#include "timing.h"
 #include "scope_lock.h"
+#include "timing.h"
 
 #include <chrono>
 #include <mutex>
@@ -952,10 +952,7 @@ NEXTPNR_NAMESPACE_END
 
 NEXTPNR_NAMESPACE_BEGIN
 
-bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
-{
-    log_abort();
-}
+bool parallel_refine(Context *ctx, ParallelRefineCfg cfg) { log_abort(); }
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 7887745283..789b188e65 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -1134,7 +1134,7 @@ struct Arch : ArchAPI<ArchRanges>
     IdString vcc_cell_pin;
     std::vector<std::vector<LutElement>> lut_elements;
     dict<IdString, const LutCellPOD *> lut_cells;
-    
+
     // Defines the max number of LUT cells in a site and LUT pins
     // to allow a correct functioning of the site lut mapping cache
     int max_lut_cells;
diff --git a/fpga_interchange/site_lut_mapping_cache.h b/fpga_interchange/site_lut_mapping_cache.h
index 3efd040f8d..31e7e5e124 100644
--- a/fpga_interchange/site_lut_mapping_cache.h
+++ b/fpga_interchange/site_lut_mapping_cache.h
@@ -51,9 +51,9 @@ struct SiteLutMappingKey
         }
     };
 
-    int32_t tileType;                      // Tile type
-    int32_t siteType;                      // Site type in that tile type
-    size_t numCells;                       // LUT cell count
+    int32_t tileType;        // Tile type
+    int32_t siteType;        // Site type in that tile type
+    size_t numCells;         // LUT cell count
     std::vector<Cell> cells; // LUT cell data
 
     unsigned int hash_; // Precomputed hash
diff --git a/nexus/pack.cc b/nexus/pack.cc
index bff50d8906..66d897a866 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -883,7 +883,8 @@ struct NexusPacker
         for (size_t i = 0; i < std::min<size_t>(clk_fanout.size(), available_globals); i++) {
             NetInfo *net = ctx->nets.at(clk_fanout.at(i).second).get();
             log_info("     promoting clock net '%s'\n", ctx->nameOf(net));
-            insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO, [&](const PortRef &port) { return port.cell->type != id_DCC; });
+            insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO,
+                          [&](const PortRef &port) { return port.cell->type != id_DCC; });
         }
     }
 

From af6735bdf413d1b3663d085b573f2aaf3e018e44 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 21 Dec 2021 17:10:45 +0000
Subject: [PATCH 084/712] mistral: add M10K bel

---
 mistral/arch.cc      |  3 ++
 mistral/arch.h       |  1 +
 mistral/constids.inc |  6 +++-
 mistral/m10k.cc      | 69 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 mistral/m10k.cc

diff --git a/mistral/arch.cc b/mistral/arch.cc
index e79a391038..6ba1693965 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -122,6 +122,9 @@ Arch::Arch(ArchArgs args)
                                        CycloneV::pos2y(hps_pos[CycloneV::I_HPS_MPU_GENERAL_PURPOSE]));
     }
 
+    for (auto m10k_pos : cyclonev->m10k_get_pos())
+        create_m10k(CycloneV::pos2x(m10k_pos), CycloneV::pos2y(m10k_pos));
+
     // This import takes about 5s, perhaps long term we can speed it up, e.g. defer to Mistral more...
     log_info("Initialising routing graph...\n");
     int pip_count = 0;
diff --git a/mistral/arch.h b/mistral/arch.h
index e17be33125..8fcea2915d 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -467,6 +467,7 @@ struct Arch : BaseArch<ArchRanges>
     bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
 
     void create_lab(int x, int y, bool is_mlab);       // lab.cc
+    void create_m10k(int x, int y);                    // m10k.cc
     void create_gpio(int x, int y);                    // io.cc
     void create_clkbuf(int x, int y);                  // globals.cc
     void create_control(int x, int y);                 // globals.cc
diff --git a/mistral/constids.inc b/mistral/constids.inc
index d241c8ef2d..82cd9ecc13 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -98,10 +98,14 @@ X(WE_INV)
 X(cyclonev_oscillator)
 X(cyclonev_hps_interface_mpu_general_purpose)
 
+X(MISTRAL_M10K)
+X(ADDRSTALLA)
+X(ADDRSTALLB)
+
 X(clkout)
 X(clkout1)
 X(compress_rbf)
 X(oscena)
 X(placer)
 X(router)
-X(step)
+X(step)
\ No newline at end of file
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
new file mode 100644
index 0000000000..4ab35096e5
--- /dev/null
+++ b/mistral/m10k.cc
@@ -0,0 +1,69 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  Lofty <dan.ravensloft@gmail.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void Arch::create_m10k(int x, int y)
+{
+    BelId bel = add_bel(x, y, id_MISTRAL_M10K, id_MISTRAL_M10K);
+    add_bel_pin(bel, id_ADDRSTALLA, PORT_IN,
+                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
+    add_bel_pin(bel, id_ADDRSTALLB, PORT_IN,
+                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
+    for (int z = 0; z < 2; z++) {
+        add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
+        add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
+        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
+        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
+        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z+6)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z+6));
+    }
+    for (int z = 0; z < 4; z++) {
+        add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, 0));
+    }
+    for (int z = 0; z < 12; z++) {
+        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
+        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
+    }
+    for (int z = 0; z < 20; z++) {
+        add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
+        add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
+        add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
+        add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
+    }
+}
+
+NEXTPNR_NAMESPACE_END
\ No newline at end of file

From 33e031a2841de813cae420becd8ece4286e08e0a Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 21 Dec 2021 21:04:05 +0000
Subject: [PATCH 085/712] mistral: M10K cell function

---
 mistral/constids.inc |  4 ++-
 mistral/m10k.cc      | 73 +++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/mistral/constids.inc b/mistral/constids.inc
index 82cd9ecc13..e032bf5353 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -101,6 +101,8 @@ X(cyclonev_hps_interface_mpu_general_purpose)
 X(MISTRAL_M10K)
 X(ADDRSTALLA)
 X(ADDRSTALLB)
+X(CFG_ABITS)
+X(CFG_DBITS)
 
 X(clkout)
 X(clkout1)
@@ -108,4 +110,4 @@ X(compress_rbf)
 X(oscena)
 X(placer)
 X(router)
-X(step)
\ No newline at end of file
+X(step)
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index 4ab35096e5..d6aa1ed28d 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -46,7 +46,7 @@ void Arch::create_m10k(int x, int y)
     }
     for (int z = 0; z < 4; z++) {
         add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, 0));
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
     }
     for (int z = 0; z < 12; z++) {
         add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
@@ -66,4 +66,75 @@ void Arch::create_m10k(int x, int y)
     }
 }
 
+static void assign_lab_pins(Context *ctx, CellInfo *cell)
+{
+    auto abits = cell->attrs[id_CFG_ABITS].as_int64();
+    auto dbits = cell->attrs[id_CFG_DBITS].as_int64();
+    NPNR_ASSERT(abits >= 7 && abits <= 13);
+    NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
+
+    // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
+
+    // It *does* generate ACLR[01] but leaves them unconnected if unused.
+
+    // Enables.
+    // RDEN[0] and WREN[1] are left unconnected.
+    cell->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
+    cell->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
+
+    // Clocks.
+    cell->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
+
+    // Enables left unconnected.
+
+    // Address lines.
+    int addr_offset = std::max(12 - std::max(abits, int64_t{9}), 0l);
+    int bit_offset = 0;
+    if (abits == 13) {
+        cell->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
+        cell->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
+        bit_offset = 1;
+    }
+    for (int bit = bit_offset; bit < abits; bit++) {
+        cell->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
+        cell->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
+    }
+
+    // Data lines
+    std::vector<int> offsets;
+    offsets.push_back(0);
+    if (abits >= 10 && dbits <= 10) {
+        offsets.push_back(10);
+    }
+    if (abits >= 11 && dbits <= 5) {
+        offsets.push_back(5);
+        offsets.push_back(15);
+    }
+    if (abits >= 12 && dbits <= 2) {
+        offsets.push_back(2);
+        offsets.push_back(7);
+        offsets.push_back(12);
+        offsets.push_back(17);
+    }
+    if (abits == 13 && dbits == 1) {
+        offsets.push_back(1);
+        offsets.push_back(3);
+        offsets.push_back(6);
+        offsets.push_back(8);
+        offsets.push_back(11);
+        offsets.push_back(13);
+        offsets.push_back(16);
+        offsets.push_back(18);
+    }
+    for (int bit = 0; bit < dbits; bit++) {
+        for (int offset : offsets) {
+            cell->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset)));
+        }
+    }
+
+    for (int bit = 0; bit < dbits; bit++) {
+        cell->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
+    }
+}
+
 NEXTPNR_NAMESPACE_END
\ No newline at end of file

From 34b7cdb5338dd25637b6b8491ea29ac38af0f5b7 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 21 Dec 2021 21:34:28 +0000
Subject: [PATCH 086/712] mistral: move M10K code to pack

---
 mistral/m10k.cc | 71 ---------------------------------------------
 mistral/pack.cc | 77 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+), 71 deletions(-)

diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index d6aa1ed28d..6d51625e2f 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -66,75 +66,4 @@ void Arch::create_m10k(int x, int y)
     }
 }
 
-static void assign_lab_pins(Context *ctx, CellInfo *cell)
-{
-    auto abits = cell->attrs[id_CFG_ABITS].as_int64();
-    auto dbits = cell->attrs[id_CFG_DBITS].as_int64();
-    NPNR_ASSERT(abits >= 7 && abits <= 13);
-    NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
-
-    // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
-
-    // It *does* generate ACLR[01] but leaves them unconnected if unused.
-
-    // Enables.
-    // RDEN[0] and WREN[1] are left unconnected.
-    cell->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
-    cell->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
-
-    // Clocks.
-    cell->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
-
-    // Enables left unconnected.
-
-    // Address lines.
-    int addr_offset = std::max(12 - std::max(abits, int64_t{9}), 0l);
-    int bit_offset = 0;
-    if (abits == 13) {
-        cell->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
-        cell->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
-        bit_offset = 1;
-    }
-    for (int bit = bit_offset; bit < abits; bit++) {
-        cell->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
-        cell->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
-    }
-
-    // Data lines
-    std::vector<int> offsets;
-    offsets.push_back(0);
-    if (abits >= 10 && dbits <= 10) {
-        offsets.push_back(10);
-    }
-    if (abits >= 11 && dbits <= 5) {
-        offsets.push_back(5);
-        offsets.push_back(15);
-    }
-    if (abits >= 12 && dbits <= 2) {
-        offsets.push_back(2);
-        offsets.push_back(7);
-        offsets.push_back(12);
-        offsets.push_back(17);
-    }
-    if (abits == 13 && dbits == 1) {
-        offsets.push_back(1);
-        offsets.push_back(3);
-        offsets.push_back(6);
-        offsets.push_back(8);
-        offsets.push_back(11);
-        offsets.push_back(13);
-        offsets.push_back(16);
-        offsets.push_back(18);
-    }
-    for (int bit = 0; bit < dbits; bit++) {
-        for (int offset : offsets) {
-            cell->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset)));
-        }
-    }
-
-    for (int bit = 0; bit < dbits; bit++) {
-        cell->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
-    }
-}
-
 NEXTPNR_NAMESPACE_END
\ No newline at end of file
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 703fa386ac..da1589f055 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -382,6 +382,83 @@ struct MistralPacker
         }
     }
 
+    void setup_m10ks()
+    {
+        for (auto& cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type != id_MISTRAL_M10K)
+                continue;
+
+            auto abits = ci->attrs[id_CFG_ABITS].as_int64();
+            auto dbits = ci->attrs[id_CFG_DBITS].as_int64();
+            NPNR_ASSERT(abits >= 7 && abits <= 13);
+            NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
+
+            // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
+
+            // It *does* generate ACLR[01] but leaves them unconnected if unused.
+
+            // Enables.
+            // RDEN[0] and WREN[1] are left unconnected.
+            ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
+            ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
+
+            // Clocks.
+            ci->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
+
+            // Enables left unconnected.
+
+            // Address lines.
+            int addr_offset = std::max(12 - std::max(abits, int64_t{9}), 0l);
+            int bit_offset = 0;
+            if (abits == 13) {
+                ci->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
+                ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
+                bit_offset = 1;
+            }
+            for (int bit = bit_offset; bit < abits; bit++) {
+                ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
+                ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
+            }
+
+            // Data lines
+            std::vector<int> offsets;
+            offsets.push_back(0);
+            if (abits >= 10 && dbits <= 10) {
+                offsets.push_back(10);
+            }
+            if (abits >= 11 && dbits <= 5) {
+                offsets.push_back(5);
+                offsets.push_back(15);
+            }
+            if (abits >= 12 && dbits <= 2) {
+                offsets.push_back(2);
+                offsets.push_back(7);
+                offsets.push_back(12);
+                offsets.push_back(17);
+            }
+            if (abits == 13 && dbits == 1) {
+                offsets.push_back(1);
+                offsets.push_back(3);
+                offsets.push_back(6);
+                offsets.push_back(8);
+                offsets.push_back(11);
+                offsets.push_back(13);
+                offsets.push_back(16);
+                offsets.push_back(18);
+            }
+            for (int bit = 0; bit < dbits; bit++) {
+                for (int offset : offsets) {
+                    ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset)));
+                }
+            }
+
+            for (int bit = 0; bit < dbits; bit++) {
+                ci->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
+            }
+        }
+    }
+
     void run()
     {
         init_constant_nets();

From 78474a5dec13236214c8e15906c40a05ae6ed4af Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 22 Dec 2021 12:01:24 +0000
Subject: [PATCH 087/712] mistral: preliminary bitstream info

---
 mistral/bitstream.cc | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 35c1303a6e..3490a3d739 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -118,6 +118,45 @@ struct MistralBitgen
         cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
     }
 
+    void write_m10k_cell(CellInfo* ci, int x, int y, int bi)
+    {
+        auto pos = CycloneV::xy2pos(x, y);
+
+        // Notes:
+        // DATA_FLOW_THRU is probably transparent reads.
+
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WL_DELAY, bi, 2);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
+
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WL_DELAY, bi, 2);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b);
+
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
+        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
+
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 1);
+
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
+
+        for (int bi = 0; bi < 256; bi++)
+            cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
+    }
+
     void write_cells()
     {
         for (auto &cell : ctx->cells) {
@@ -128,6 +167,8 @@ struct MistralBitgen
                 write_io_cell(ci, loc.x, loc.y, bi);
             else if (ctx->is_clkbuf_cell(ci->type))
                 write_clkbuf_cell(ci, loc.x, loc.y, bi);
+            else if (ci->type == id_MISTRAL_M10K)
+                write_m10k_cell(ci, loc.x, loc.y, bi);
         }
     }
 

From da65afc83b83f02efa96e9a7735f7044a1f1e6d1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 22 Dec 2021 13:54:30 +0000
Subject: [PATCH 088/712] mistral: M10K pack fixes

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/arch.cc |  2 ++
 mistral/pack.cc | 18 ++++++++++++------
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/mistral/arch.cc b/mistral/arch.cc
index 6ba1693965..46ed4f62a5 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -410,6 +410,8 @@ void Arch::add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire)
 
 void Arch::assign_default_pinmap(CellInfo *cell)
 {
+    if (cell->type == id_MISTRAL_M10K)
+        return; // M10Ks always have a custom pinmap
     for (auto &port : cell->ports) {
         auto &pinmap = cell->pin_data[port.first].bel_pins;
         if (!pinmap.empty())
diff --git a/mistral/pack.cc b/mistral/pack.cc
index da1589f055..09fedf10e9 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -384,13 +384,13 @@ struct MistralPacker
 
     void setup_m10ks()
     {
-        for (auto& cell : ctx->cells) {
+        for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type != id_MISTRAL_M10K)
                 continue;
 
-            auto abits = ci->attrs[id_CFG_ABITS].as_int64();
-            auto dbits = ci->attrs[id_CFG_DBITS].as_int64();
+            auto abits = ci->params.at(id_CFG_ABITS).as_int64();
+            auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
             NPNR_ASSERT(abits >= 7 && abits <= 13);
             NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
 
@@ -417,8 +417,10 @@ struct MistralPacker
                 bit_offset = 1;
             }
             for (int bit = bit_offset; bit < abits; bit++) {
-                ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
-                ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
+                ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {
+                        ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
+                ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {
+                        ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
             }
 
             // Data lines
@@ -449,7 +451,10 @@ struct MistralPacker
             }
             for (int bit = 0; bit < dbits; bit++) {
                 for (int offset : offsets) {
-                    ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset)));
+                    log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))),
+                             ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset))));
+                    ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
+                            ctx->id(stringf("DATAAIN[%d]", bit + offset)));
                 }
             }
 
@@ -466,6 +471,7 @@ struct MistralPacker
         pack_io();
         constrain_carries();
         constrain_lutram();
+        setup_m10ks();
     }
 };
 }; // namespace

From 9be65cd67c6a40ddc35460b97a014bbcd0af2f85 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 18 Jan 2022 12:15:01 +0000
Subject: [PATCH 089/712] mistral: some more M10K fixes

---
 mistral/bitstream.cc | 4 ++--
 mistral/pack.cc      | 8 +++-----
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 3490a3d739..660e367196 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -126,7 +126,7 @@ struct MistralBitgen
         // DATA_FLOW_THRU is probably transparent reads.
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
@@ -135,7 +135,7 @@ struct MistralBitgen
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
 
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 09fedf10e9..27ad3c92bd 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -399,9 +399,9 @@ struct MistralPacker
             // It *does* generate ACLR[01] but leaves them unconnected if unused.
 
             // Enables.
-            // RDEN[0] and WREN[1] are left unconnected.
-            ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
-            ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
+            // RDEN[1] and WREN[0] are left unconnected.
+            ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")};
+            ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("RDEN[0]")};
 
             // Clocks.
             ci->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
@@ -451,8 +451,6 @@ struct MistralPacker
             }
             for (int bit = 0; bit < dbits; bit++) {
                 for (int offset : offsets) {
-                    log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))),
-                             ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset))));
                     ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
                             ctx->id(stringf("DATAAIN[%d]", bit + offset)));
                 }

From 3e688a3ac9ae35a894d5c2c19f2d9591b746d8da Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 7 Mar 2022 18:22:56 +0000
Subject: [PATCH 090/712] mistral: fixes and debug info

---
 mistral/bitstream.cc | 21 +++++++++++----------
 mistral/constids.inc |  1 +
 mistral/delay.cc     | 36 ++++++++++++++++++++++++++++++++++++
 mistral/m10k.cc      | 30 +++++++++++-------------------
 4 files changed, 59 insertions(+), 29 deletions(-)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 660e367196..6a2c3825d4 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -118,7 +118,7 @@ struct MistralBitgen
         cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
     }
 
-    void write_m10k_cell(CellInfo* ci, int x, int y, int bi)
+    void write_m10k_cell(CellInfo *ci, int x, int y, int bi)
     {
         auto pos = CycloneV::xy2pos(x, y);
 
@@ -128,31 +128,32 @@ struct MistralBitgen
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
         cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WL_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
 
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
         cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WL_DELAY, bi, 2);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b);
 
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
-        cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
 
-        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 0);
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
 
+        // Note for future us: the RAM init contents are inverted.
         for (int bi = 0; bi < 256; bi++)
             cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
     }
diff --git a/mistral/constids.inc b/mistral/constids.inc
index e032bf5353..262fd12ab1 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -90,6 +90,7 @@ X(WE)
 X(MISTRAL_MLAB)
 X(CLK1)
 X(A1EN)
+X(B1EN)
 X(A1DATA)
 X(B1DATA)
 X(WCLK_INV)
diff --git a/mistral/delay.cc b/mistral/delay.cc
index 4d123249e8..c40ac3f095 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -57,6 +57,17 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         } else if (port.in(id_B1DATA)) {
             return TMG_COMB_OUTPUT;
         }
+    } else if (cell->type == id_MISTRAL_M10K) {
+        if (port == id_CLK1) {
+            return TMG_CLOCK_INPUT;
+        } else if (port.in(id_A1DATA, id_A1EN, id_B1EN) || port.str(this).find("A1ADDR") == 0) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        } else if (port.str(this).find("B1ADDR") == 0) {
+            return TMG_REGISTER_INPUT;
+        } else if (port.in(id_B1DATA)) {
+            return TMG_REGISTER_OUTPUT;
+        }
     }
     return TMG_IGNORE;
 }
@@ -87,6 +98,31 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             timing.clockToQ = DelayQuad{};
         }
         return timing;
+    } else if (cell->type == id_MISTRAL_M10K) {
+        timing.clock_port = id_CLK1;
+        timing.edge = RISING_EDGE;
+        if (port.str(this).find("A1ADDR") == 0 || port.str(this).find("B1ADDR") == 0) {
+            timing.setup = DelayPair{125, 125};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_A1DATA) {
+            timing.setup = DelayPair{97, 97};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_A1EN) {
+            timing.setup = DelayPair{140, 140};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_B1EN) {
+            timing.setup = DelayPair{161, 161};
+            timing.hold = DelayPair{42, 42};
+            timing.clockToQ = DelayQuad{};
+        } else if (port == id_B1DATA) {
+            timing.setup = DelayPair{};
+            timing.hold = DelayPair{};
+            timing.clockToQ = DelayQuad{1004};
+        }
+        return timing;
     }
     NPNR_ASSERT_FALSE("unreachable");
 }
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index 6d51625e2f..4da1204fd8 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -24,35 +24,27 @@ NEXTPNR_NAMESPACE_BEGIN
 void Arch::create_m10k(int x, int y)
 {
     BelId bel = add_bel(x, y, id_MISTRAL_M10K, id_MISTRAL_M10K);
-    add_bel_pin(bel, id_ADDRSTALLA, PORT_IN,
-                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
-    add_bel_pin(bel, id_ADDRSTALLB, PORT_IN,
-                get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
+    add_bel_pin(bel, id_ADDRSTALLA, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
+    add_bel_pin(bel, id_ADDRSTALLB, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
     for (int z = 0; z < 2; z++) {
         add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
         add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
-        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
-        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
-        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z+6)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z+6));
+        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
+        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
+        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
+        add_bel_pin(bel, id(stringf("CLKIN[%d]", z + 6)), PORT_IN,
+                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
     }
     for (int z = 0; z < 4; z++) {
         add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
     }
     for (int z = 0; z < 12; z++) {
-        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
-        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
+        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
+        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
     }
     for (int z = 0; z < 20; z++) {
         add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
@@ -66,4 +58,4 @@ void Arch::create_m10k(int x, int y)
     }
 }
 
-NEXTPNR_NAMESPACE_END
\ No newline at end of file
+NEXTPNR_NAMESPACE_END

From 8c0dbdb2184b17aaee42fb46efadda5e864cd865 Mon Sep 17 00:00:00 2001
From: Krzysztof Boronski <kboronski@antmicro.com>
Date: Fri, 11 Mar 2022 07:53:42 -0600
Subject: [PATCH 091/712] interchange: Don't hold reference to visit in global
 routing

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
---
 fpga_interchange/globals.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc
index 6efd1d8994..eaff30e08f 100644
--- a/fpga_interchange/globals.cc
+++ b/fpga_interchange/globals.cc
@@ -76,7 +76,7 @@ static int route_global_arc(Context *ctx, NetInfo *net, store_index<PortRef> usr
     while (!visit_queue.empty()) {
         WireId cursor = visit_queue.front();
         visit_queue.pop();
-        auto &curr_visit = visits.at(cursor);
+        auto curr_visit = visits.at(cursor);
         // We're now at least one layer deeper than a valid visit, any further exploration is futile
         if (startpoint != WireId() && curr_visit.total_hops > best_visit.total_hops)
             break;

From 2a3d0c1d29f99c96004564a74c0dc04f7713d870 Mon Sep 17 00:00:00 2001
From: Maya <96890070+VioletEternity@users.noreply.github.com>
Date: Fri, 11 Mar 2022 23:31:23 +0000
Subject: [PATCH 092/712] ecp5: verify hex strings contain only valid
 characters.

---
 ecp5/bitstream.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index a23e4cd2e5..b1c60ccb06 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -149,6 +149,8 @@ std::vector<bool> parse_init_str(const Property &p, int length, const char *cell
         for (int i = 0; i < int(str.length()) - 2; i++) {
             char c = str.at((str.size() - i) - 1);
             int nibble = chtohex(c);
+            if (nibble == (int)std::string::npos)
+                log_error("hex string has invalid char '%c' at position %d.\n", c, i);
             result.at(i * 4) = nibble & 0x1;
             if (i * 4 + 1 < length)
                 result.at(i * 4 + 1) = nibble & 0x2;
@@ -582,13 +584,16 @@ static std::vector<bool> parse_config_str(const Property &p, int length)
         if (base == "0b") {
             for (int i = 0; i < int(str.length()) - 2; i++) {
                 char c = str.at((str.size() - 1) - i);
-                NPNR_ASSERT(c == '0' || c == '1');
+                if (!(c == '0' || c == '1'))
+                    log_error("binary string has invalid char '%c' at position %d.\n", c, i);
                 word.at(i) = (c == '1');
             }
         } else if (base == "0x") {
             for (int i = 0; i < int(str.length()) - 2; i++) {
                 char c = str.at((str.size() - i) - 1);
                 int nibble = chtohex(c);
+                if (nibble == (int)std::string::npos)
+                    log_error("hex string has invalid char '%c' at position %d.\n", c, i);
                 word.at(i * 4) = nibble & 0x1;
                 if (i * 4 + 1 < length)
                     word.at(i * 4 + 1) = nibble & 0x2;

From 9f53bd42788460d6bebd4f2f50af32a710667c93 Mon Sep 17 00:00:00 2001
From: Maya <96890070+VioletEternity@users.noreply.github.com>
Date: Fri, 11 Mar 2022 23:34:45 +0000
Subject: [PATCH 093/712] ecp5: accept lowercase characters in hex strings.

---
 ecp5/bitstream.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index b1c60ccb06..40d843b965 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -131,7 +131,7 @@ static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value
 inline int chtohex(char c)
 {
     static const std::string hex = "0123456789ABCDEF";
-    return hex.find(c);
+    return hex.find(std::toupper(c));
 }
 
 std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)

From 4a2aa6deb49b70ed69f386898bcde7a6b2572618 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 12 Mar 2022 23:05:42 +1000
Subject: [PATCH 094/712] gowin: Add the Global Set/Reset primitive

GSR is added automatically if it was not instantiated by the user explicitly.

Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      |  8 ++++++++
 gowin/cells.cc     |  2 ++
 gowin/constids.inc |  5 +++++
 gowin/pack.cc      | 36 ++++++++++++++++++++++++++++++++++++
 4 files changed, 51 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index e6ee826720..22874810fd 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -991,6 +991,14 @@ Arch::Arch(ArchArgs args) : args(args)
             int z = 0;
             bool dff = true;
             switch (static_cast<ConstIds>(bel->type_id)) {
+            case ID_GSR0:
+                snprintf(buf, 32, "R%dC%d_GSR0", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_GSR, Loc(col, row, 0), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_GSRI)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_GSRI, id(buf));
+                break;
             // fall through the ++
             case ID_LUT7:
                 z++;
diff --git a/gowin/cells.cc b/gowin/cells.cc
index d862458c33..8e450b5140 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -63,6 +63,8 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_I);
         new_cell->addInput(id_OEN);
         new_cell->addOutput(id_O);
+    } else if (type == id_GSR) {
+        new_cell->addInput(id_GSRI);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 3e72340abd..d32a987df2 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -739,6 +739,11 @@ X(IOBUF)
 X(TBUF)
 X(TLVDS_OBUF)
 
+// global set/reset
+X(GSR)
+X(GSR0)
+X(GSRI)
+
 // primitive attributes
 X(INIT)
 X(FF_USED)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index c17a20c7c5..24daee31d6 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -660,6 +660,41 @@ static void pack_constants(Context *ctx)
     }
 }
 
+// Pack global set-reset
+static void pack_gsr(Context *ctx)
+{
+    log_info("Packing GSR..\n");
+
+    bool user_gsr = false;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+        if (ci->type == id_GSR) {
+            user_gsr = true;
+            break;
+        }
+    }
+    if (!user_gsr) {
+        // XXX
+        bool have_gsr_bel = false;
+        for (auto bi : ctx->bels) {
+            if (bi.second.type == id_GSR) {
+                have_gsr_bel = true;
+                break;
+            }
+        }
+        if (have_gsr_bel) {
+            // make default GSR
+            std::unique_ptr<CellInfo> gsr_cell = create_generic_cell(ctx, id_GSR, "GSR");
+            gsr_cell->connectPort(id_GSRI, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            ctx->cells[gsr_cell->name] = std::move(gsr_cell);
+        } else {
+            log_info("No GSR in the chip base\n");
+        }
+    }
+}
+
 static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
 {
     return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
@@ -857,6 +892,7 @@ bool Arch::pack()
     try {
         log_break();
         pack_constants(ctx);
+        pack_gsr(ctx);
         pack_io(ctx);
         pack_diff_io(ctx);
         pack_wideluts(ctx);

From 883f27480274cd6385bce118dc31d260ec9ae832 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 10 Mar 2022 10:28:57 +0000
Subject: [PATCH 095/712] mistral: M10K initialisation support

---
 mistral/bitstream.cc | 19 +++++++++++++++++--
 mistral/constids.inc |  1 +
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 6a2c3825d4..c51050083f 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -153,9 +153,24 @@ struct MistralBitgen
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0);
 
-        // Note for future us: the RAM init contents are inverted.
+        auto permute_init = [](int64_t init) -> int64_t {
+            const int permutation[40] = {0, 20, 10, 30, 1, 21, 11, 31, 2, 22, 12, 32, 3, 23, 13, 33, 4, 24, 14, 34,
+                                         5, 25, 15, 35, 6, 26, 16, 36, 7, 27, 17, 37, 8, 28, 18, 38, 9, 29, 19, 39};
+
+            int64_t output = 0;
+            for (int bit = 0; bit < 40; bit++)
+                output |= ((init >> permutation[bit]) & 1) << bit;
+            return ~output; // RAM init is inverted.
+        };
+
+        Property init;
+        if (ci->params.count(id_INIT) == 0) {
+            init = Property{0, 10240};
+        } else {
+            init = ci->params.at(id_INIT);
+        }
         for (int bi = 0; bi < 256; bi++)
-            cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff);
+            cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, permute_init(init.extract(bi * 40, 40).as_int64()));
     }
 
     void write_cells()
diff --git a/mistral/constids.inc b/mistral/constids.inc
index 262fd12ab1..754a96b367 100644
--- a/mistral/constids.inc
+++ b/mistral/constids.inc
@@ -100,6 +100,7 @@ X(cyclonev_oscillator)
 X(cyclonev_hps_interface_mpu_general_purpose)
 
 X(MISTRAL_M10K)
+X(INIT)
 X(ADDRSTALLA)
 X(ADDRSTALLB)
 X(CFG_ABITS)

From e0f55e6d69d76f62565a5cfacc41e7e2a18c04ee Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 14 Mar 2022 14:23:20 +1000
Subject: [PATCH 096/712] gowin: BUGFIX temporarily disable the budget

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gui/gowin/mainwindow.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/gui/gowin/mainwindow.cc b/gui/gowin/mainwindow.cc
index c7ba44ab60..133a116bdf 100644
--- a/gui/gowin/mainwindow.cc
+++ b/gui/gowin/mainwindow.cc
@@ -74,6 +74,9 @@ void MainWindow::createMenu()
 
     menuDesign->addSeparator();
     menuDesign->addAction(actionLoadCST);
+
+	// XXX
+	actionAssignBudget->setEnabled(false);
 }
 
 void MainWindow::new_proj() {}
@@ -99,5 +102,7 @@ void MainWindow::onUpdateActions()
     if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
         actionLoadCST->setEnabled(false);
     }
+	// XXX
+	actionAssignBudget->setEnabled(false);
 }
 NEXTPNR_NAMESPACE_END

From 4736acb3d552de7ad9251b519195c66f63913b6a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 14 Mar 2022 17:42:50 +1000
Subject: [PATCH 097/712] fix identation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gui/gowin/mainwindow.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gui/gowin/mainwindow.cc b/gui/gowin/mainwindow.cc
index 133a116bdf..8593bb4be4 100644
--- a/gui/gowin/mainwindow.cc
+++ b/gui/gowin/mainwindow.cc
@@ -75,8 +75,8 @@ void MainWindow::createMenu()
     menuDesign->addSeparator();
     menuDesign->addAction(actionLoadCST);
 
-	// XXX
-	actionAssignBudget->setEnabled(false);
+    // XXX
+    actionAssignBudget->setEnabled(false);
 }
 
 void MainWindow::new_proj() {}
@@ -102,7 +102,7 @@ void MainWindow::onUpdateActions()
     if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
         actionLoadCST->setEnabled(false);
     }
-	// XXX
-	actionAssignBudget->setEnabled(false);
+    // XXX
+    actionAssignBudget->setEnabled(false);
 }
 NEXTPNR_NAMESPACE_END

From 25d7e3ae8b409a1be550e25a2dbabc3c54f0d446 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 14 Mar 2022 21:41:57 +1000
Subject: [PATCH 098/712] gowin: support for locales other than en_US and C

Specifically, those locales where the fractional part separator in
floating point numbers is not a dot.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/main.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/gowin/main.cc b/gowin/main.cc
index 1473f3e89b..db74545edd 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -21,6 +21,7 @@
 #ifdef MAIN_EXECUTABLE
 
 #include <fstream>
+#include <locale>
 #include <regex>
 #include "command.h"
 #include "design_utils.h"
@@ -90,6 +91,11 @@ void GowinCommandHandler::customAfterLoad(Context *ctx)
 
 int main(int argc, char *argv[])
 {
+    // set the locale here because when you create a context you create several
+    // floating point strings whose representation depends on the locale. If
+    // you don't do this, the strings will be in the C locale and later when Qt
+    // starts it won't be able to read them back as numbers.
+    std::locale::global(std::locale(""));
     GowinCommandHandler handler(argc, argv);
     return handler.exec();
 }

From e9ce55bfd020a05b93fae5be8fe431876ae9c742 Mon Sep 17 00:00:00 2001
From: Stefan Riesenberger <stefan.riesenberger@gmail.com>
Date: Mon, 14 Mar 2022 12:43:19 +0100
Subject: [PATCH 099/712] ice40: fix crash when packing LUTs with no output

---
 ice40/pack.cc | 51 +++++++++++++++++++++++++++------------------------
 1 file changed, 27 insertions(+), 24 deletions(-)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index c32e346fcc..f533941ddd 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -49,32 +49,35 @@ static void pack_lut_lutffs(Context *ctx)
                 log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
             // See if we can pack into a DFF
             // TODO: LUT cascade
-            NetInfo *o = ci->ports.at(id_O).net;
-            CellInfo *dff = net_only_drives(ctx, o, is_ff, id_D, true);
-            auto lut_bel = ci->attrs.find(id_BEL);
+            auto port = ci->ports.find(id_O);
             bool packed_dff = false;
-            if (dff) {
-                if (ctx->verbose)
-                    log_info("found attached dff %s\n", dff->name.c_str(ctx));
-                auto dff_bel = dff->attrs.find(id_BEL);
-                if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
-                    // Locations don't match, can't pack
-                } else {
-                    lut_to_lc(ctx, ci, packed.get(), false);
-                    dff_to_lc(ctx, dff, packed.get(), false);
-                    ++lut_and_ff;
-                    ctx->nets.erase(o->name);
-                    if (dff_bel != dff->attrs.end())
-                        packed->attrs[id_BEL] = dff_bel->second;
-                    for (const auto &attr : dff->attrs) {
-                        // BEL is dealt with specially
-                        if (attr.first != id_BEL)
-                            packed->attrs[attr.first] = attr.second;
-                    }
-                    packed_cells.insert(dff->name);
+            if (port != ci->ports.end()) {
+                NetInfo *o = port->second.net;
+                CellInfo *dff = net_only_drives(ctx, o, is_ff, id_D, true);
+                auto lut_bel = ci->attrs.find(id_BEL);
+                if (dff) {
                     if (ctx->verbose)
-                        log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
-                    packed_dff = true;
+                        log_info("found attached dff %s\n", dff->name.c_str(ctx));
+                    auto dff_bel = dff->attrs.find(id_BEL);
+                    if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
+                        // Locations don't match, can't pack
+                    } else {
+                        lut_to_lc(ctx, ci, packed.get(), false);
+                        dff_to_lc(ctx, dff, packed.get(), false);
+                        ++lut_and_ff;
+                        ctx->nets.erase(o->name);
+                        if (dff_bel != dff->attrs.end())
+                            packed->attrs[id_BEL] = dff_bel->second;
+                        for (const auto &attr : dff->attrs) {
+                            // BEL is dealt with specially
+                            if (attr.first != id_BEL)
+                                packed->attrs[attr.first] = attr.second;
+                        }
+                        packed_cells.insert(dff->name);
+                        if (ctx->verbose)
+                            log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
+                        packed_dff = true;
+                    }
                 }
             }
             if (!packed_dff) {

From badef293ebdf15567ddbf060f65c2eb7c1faa4ed Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 15 Mar 2022 11:02:37 +1000
Subject: [PATCH 100/712] gowin: add support for ODDR primitive

Compatible with older versions of apicula bases.
Also small fixes and as the number of virtual Bels grows it is necessary
to assign them Z coordinate in a centralized way to avoid conflicts and
for this purpose introduced the BelZ enum.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      |  53 ++++++++++++++++++++++-
 gowin/arch.h       |  17 ++++++--
 gowin/constids.inc |  12 ++++++
 gowin/gfx.cc       |   4 +-
 gowin/pack.cc      | 102 +++++++++++++++++++++++++++++++++++++++++++--
 5 files changed, 177 insertions(+), 11 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 22874810fd..6213124f99 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -789,7 +789,7 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
 
     // 4 MUX2_LUT5, 2 MUX2_LUT6, 1 MUX2_LUT7, 1 MUX2_LUT8
     for (int j = 0; j < 8; ++j) {
-        z = j + mux_0_z;
+        z = j + BelZ::mux_0_z;
 
         int grow = row + 1;
         int gcol = col + 1;
@@ -990,6 +990,7 @@ Arch::Arch(ArchArgs args) : args(args)
             IdString portname;
             int z = 0;
             bool dff = true;
+            bool oddrc = false;
             switch (static_cast<ConstIds>(bel->type_id)) {
             case ID_GSR0:
                 snprintf(buf, 32, "R%dC%d_GSR0", row + 1, col + 1);
@@ -1119,6 +1120,56 @@ Arch::Arch(ArchArgs args) : args(args)
                 addBelInput(belname, id_OEN, id(buf));
                 break;
 
+                // IO logic
+            case ID_ODDRCB:
+                z++; /* fall-through*/
+            case ID_ODDRCA:
+                oddrc = true;
+                z++; /* fall-through*/
+            case ID_ODDRB:
+                z++; /* fall-through*/
+            case ID_ODDRA: {
+                snprintf(buf, 32, "R%dC%d_ODDR%s%c", row + 1, col + 1, oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
+                belname = id(buf);
+                addBel(belname, id_ODDR, Loc(col, row, BelZ::iologic_0_z + z), false);
+
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_D0)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_D0, id(buf));
+
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_D1)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_D1, id(buf));
+
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_TX)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_TX, id(buf));
+
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CLK)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_CLK, id(buf));
+
+                if (oddrc) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CE)->src_id);
+                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    addBelInput(belname, id_CE, id(buf));
+                }
+
+                // dummy wires
+                snprintf(buf, 32, "ODDR%s%c_Q0", oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
+                IdString id_q0 = id(buf);
+                IdString q0_name = wireToGlobal(row, col, db, id_q0);
+                if (wires.count(q0_name) == 0)
+                    addWire(q0_name, id_q0, row, col);
+                addBelOutput(belname, id_Q0, q0_name);
+
+                snprintf(buf, 32, "ODDR%s%c_Q1", oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
+                IdString id_q1 = id(buf);
+                IdString q1_name = wireToGlobal(row, col, db, id_q1);
+                if (wires.count(q1_name) == 0)
+                    addWire(q1_name, id_q1, row, col);
+                addBelOutput(belname, id_Q1, q1_name);
+            } break;
             default:
                 break;
             }
diff --git a/gowin/arch.h b/gowin/arch.h
index 7a5dfc466d..c8392e7e4e 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -287,8 +287,8 @@ struct Arch : BaseArch<ArchRanges>
 
     // These functions include useful errors if not found
     WireInfo &wire_info(IdString wire);
-    PipInfo &pip_info(IdString wire);
-    BelInfo &bel_info(IdString wire);
+    PipInfo &pip_info(IdString pip);
+    BelInfo &bel_info(IdString bel);
 
     std::vector<IdString> bel_ids, wire_ids, pip_ids;
 
@@ -459,8 +459,6 @@ struct Arch : BaseArch<ArchRanges>
     void assignArchInfo() override;
     bool cellsCompatible(const CellInfo **cells, int count) const;
     bool haveBelType(int x, int y, IdString bel_type);
-    // start Z for the MUX2LUT5 bels
-    int const mux_0_z = 10;
     // chip db version
     unsigned int const chipdb_version = 1;
 
@@ -476,6 +474,17 @@ struct Arch : BaseArch<ArchRanges>
     std::map<const IdString, IdString> dff_comp_mode;
 };
 
+// Bels Z range
+namespace BelZ {
+enum
+{
+    mux_0_z = 10,     // start Z for the MUX2LUT5 bels
+    iologic_0_z = 20, // start Z for the IOLOGIC bels
+    vcc_0_z = 277,    // virtual VCC bel Z
+    gnd_0_z = 278     // virtual VSS bel Z
+};
+}
+
 NEXTPNR_NAMESPACE_END
 
 #endif /* GOWIN_ARCH_H */
diff --git a/gowin/constids.inc b/gowin/constids.inc
index d32a987df2..125fdc74b4 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -679,6 +679,18 @@ X(IOBHS)
 X(IOBIS)
 X(IOBJS)
 
+// IOLOGIC
+X(TX)
+X(OBUF_TYPE)
+X(SBUF)
+X(DBUF)
+X(ODDR)
+X(ODDRC)
+X(ODDRA)
+X(ODDRB)
+X(ODDRCA)
+X(ODDRCB)
+
 // Wide LUTs
 X(MUX2_LUT5)
 X(MUX2_LUT6)
diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index daae5c71c3..fcd42c7c74 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -5639,14 +5639,14 @@ void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel)
         break;
     case ID_GW_MUX2_LUT5:
         active.x = inactive.x = bel.x + mux2lut5_x;
-        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - arch->mux_0_z) >> 1];
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - BelZ::mux_0_z) >> 1];
         active.decal = id_DECAL_MUXUPPER_ACTIVE;
         inactive.decal = id_DECAL_MUXUPPER_INACTIVE;
         arch->setBelDecal(bel.name, active, inactive);
         break;
     case ID_GW_MUX2_LUT6:
         active.x = inactive.x = bel.x + mux2lut6_x;
-        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - arch->mux_0_z) / 5];
+        active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - BelZ::mux_0_z) / 5];
         active.decal = id_DECAL_MUXLOWER_ACTIVE;
         inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
         arch->setBelDecal(bel.name, active, inactive);
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 24daee31d6..9f0a2478e6 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -271,7 +271,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         // mux is the cluster root
         packed->cluster = packed->name;
         lut1->cluster = packed->name;
-        lut1->constr_z = -ctx->mux_0_z + 1;
+        lut1->constr_z = -BelZ::mux_0_z + 1;
         packed->constr_children.clear();
 
         // reconnect MUX ports
@@ -314,9 +314,9 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
         // mux is the cluster root
         packed->cluster = packed->name;
         lut0->cluster = packed->name;
-        lut0->constr_z = -ctx->mux_0_z;
+        lut0->constr_z = -BelZ::mux_0_z;
         lut1->cluster = packed->name;
-        lut1->constr_z = -ctx->mux_0_z + 1;
+        lut1->constr_z = -BelZ::mux_0_z + 1;
         packed->constr_children.clear();
 
         // reconnect MUX ports
@@ -724,8 +724,100 @@ static bool is_gowin_diff_iob(const Context *ctx, const CellInfo *cell)
     }
 }
 
+static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
+{
+    switch (cell->type.index) {
+    case ID_ODDR: /* fall-through*/
+    case ID_ODDRC:
+        return true;
+    default:
+        return false;
+    }
+}
+
 static bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); }
 
+// Pack IO logic
+static void pack_iologic(Context *ctx)
+{
+    pool<IdString> packed_cells;
+    pool<IdString> delete_nets;
+
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    log_info("Packing IO logic..\n");
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+        if (is_gowin_iologic(ctx, ci)) {
+            CellInfo *q0_dst = nullptr;
+            CellInfo *q1_dst = nullptr;
+            switch (ci->type.index) {
+            case ID_ODDRC: /* fall-through*/
+            case ID_ODDR: {
+                q0_dst = net_only_drives(ctx, ci->ports.at(id_Q0).net, is_iob, id_I);
+                NPNR_ASSERT(q0_dst != nullptr);
+
+                auto iob_bel = q0_dst->attrs.find(id_BEL);
+                if (q0_dst->attrs.count(id_DIFF_TYPE)) {
+                    ci->attrs[id_OBUF_TYPE] = std::string("DBUF");
+                } else {
+                    ci->attrs[id_OBUF_TYPE] = std::string("SBUF");
+                }
+                if (iob_bel != q0_dst->attrs.end()) {
+                    // already know there to place, no need of any cluster stuff
+                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
+                    loc.z += BelZ::iologic_0_z;
+                    ci->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
+                } else {
+                    // make cluster from ODDR and OBUF
+                    ci->cluster = ci->name;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_abs_z = false;
+                    ci->constr_children.push_back(q0_dst);
+                    q0_dst->cluster = ci->name;
+                    q0_dst->constr_x = 0;
+                    q0_dst->constr_y = 0;
+                    q0_dst->constr_z = -BelZ::iologic_0_z;
+                    q0_dst->constr_abs_z = false;
+                }
+
+                // disconnect Q0 output: it is wired internally
+                delete_nets.insert(ci->ports.at(id_Q0).net->name);
+                q0_dst->disconnectPort(id_I);
+                ci->disconnectPort(id_Q0);
+
+                ci->attrs[id_IOBUF] = 0;
+                // if Q1 is conected then disconnet it too
+                if (port_used(ci, id_Q1)) {
+                    q1_dst = net_only_drives(ctx, ci->ports.at(id_Q1).net, is_iob, id_OEN);
+                    if (q1_dst != nullptr) {
+                        delete_nets.insert(ci->ports.at(id_Q1).net->name);
+                        q0_dst->disconnectPort(id_OEN);
+                        ci->disconnectPort(id_Q1);
+                        ci->attrs[id_IOBUF] = 1;
+                    }
+                }
+            } break;
+            default:
+                break;
+            }
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto dnet : delete_nets) {
+        ctx->nets.erase(dnet);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
 // Pack differential IO buffers
 static void pack_diff_io(Context *ctx)
 {
@@ -749,7 +841,7 @@ static void pack_diff_io(Context *ctx)
                 NPNR_ASSERT(iob_p != nullptr);
                 NPNR_ASSERT(iob_n != nullptr);
                 auto iob_p_bel_a = iob_p->attrs.find(id_BEL);
-                if (iob_p_bel_a == ci->attrs.end()) {
+                if (iob_p_bel_a == iob_p->attrs.end()) {
                     log_error("LVDS '%s' must be restricted.\n", ctx->nameOf(ci));
                     continue;
                 }
@@ -793,6 +885,7 @@ static void pack_diff_io(Context *ctx)
         ctx->cells[ncell->name] = std::move(ncell);
     }
 }
+
 // Pack IO buffers
 static void pack_io(Context *ctx)
 {
@@ -895,6 +988,7 @@ bool Arch::pack()
         pack_gsr(ctx);
         pack_io(ctx);
         pack_diff_io(ctx);
+        pack_iologic(ctx);
         pack_wideluts(ctx);
         pack_alus(ctx);
         pack_lut_lutffs(ctx);

From 1cc71c7846463c401b63c15cf7da3c674b50269e Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 15 Mar 2022 10:43:31 +0100
Subject: [PATCH 101/712] nexus: Added FASM feature emission for DCC and port
 timing class info

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/arch.cc |  8 ++++++++
 nexus/fasm.cc | 12 ++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index cb8cacf8d0..0241e83286 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -546,6 +546,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         if (type == TMG_REGISTER_INPUT || type == TMG_REGISTER_OUTPUT)
             clockInfoCount = 1;
         return type;
+    } else if (cell->type == id_DCC) {
+        if (port == id_CLKI)
+            return TMG_CLOCK_INPUT;
+        else if (port == id_CLKO)
+            return TMG_GEN_CLOCK;
+        else if (port == id_CE)
+            return TMG_COMB_INPUT;
+        return TMG_IGNORE;
     }
     return TMG_IGNORE;
 }
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index c460e14bab..c8404587ef 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -526,6 +526,16 @@ struct NexusFasmWriter
         write_cell_muxes(cell);
         pop(2);
     }
+    // Write config for DCC
+    void write_dcc(const CellInfo *cell)
+    {
+        BelId bel = cell->bel;
+        push_tile(bel.tile);
+        push_belname(bel);
+        write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer
+        write_cell_muxes(cell);
+        pop(2);
+    }
     // Write config for an OXIDE_EBR cell
     void write_bram(const CellInfo *cell)
     {
@@ -927,6 +937,8 @@ struct NexusFasmWriter
                 write_dphy(ci);
             else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC)
                 write_iol(ci);
+            else if (ci->type == id_DCC)
+                write_dcc(ci);
             blank();
         }
         // Handle DCC route-throughs

From ad00f3fdeb9e48a63c2781815d265266123f2621 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 15 Mar 2022 21:52:32 +1000
Subject: [PATCH 102/712] gowin: test locale workaround

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/main.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gowin/main.cc b/gowin/main.cc
index db74545edd..e3c6762bd2 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -95,7 +95,11 @@ int main(int argc, char *argv[])
     // floating point strings whose representation depends on the locale. If
     // you don't do this, the strings will be in the C locale and later when Qt
     // starts it won't be able to read them back as numbers.
-    std::locale::global(std::locale(""));
+    try {
+        std::locale::global(std::locale(""));
+    } catch (const std::runtime_error &e) {
+        // the locale is broken in this system, so leave it as it is
+    }
     GowinCommandHandler handler(argc, argv);
     return handler.exec();
 }

From 53ddbbaa8584bac463718ba4837d1ee8f79d88c4 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 16 Mar 2022 05:39:55 +1000
Subject: [PATCH 103/712] Set the locale as early as possible

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/command.cc | 10 +++++++++-
 gowin/main.cc     |  9 ---------
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/common/command.cc b/common/command.cc
index 2167deb92b..0de9ccc470 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -45,7 +45,15 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-CommandHandler::CommandHandler(int argc, char **argv) : argc(argc), argv(argv) { log_streams.clear(); }
+CommandHandler::CommandHandler(int argc, char **argv) : argc(argc), argv(argv)
+{
+    try {
+        std::locale::global(std::locale(""));
+    } catch (const std::runtime_error &e) {
+        // the locale is broken in this system, so leave it as it is
+    }
+    log_streams.clear();
+}
 
 bool CommandHandler::parseOptions()
 {
diff --git a/gowin/main.cc b/gowin/main.cc
index e3c6762bd2..19c1d02c2d 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -91,15 +91,6 @@ void GowinCommandHandler::customAfterLoad(Context *ctx)
 
 int main(int argc, char *argv[])
 {
-    // set the locale here because when you create a context you create several
-    // floating point strings whose representation depends on the locale. If
-    // you don't do this, the strings will be in the C locale and later when Qt
-    // starts it won't be able to read them back as numbers.
-    try {
-        std::locale::global(std::locale(""));
-    } catch (const std::runtime_error &e) {
-        // the locale is broken in this system, so leave it as it is
-    }
     GowinCommandHandler handler(argc, argv);
     return handler.exec();
 }

From e3b9c971f926ddf05f39eac0e37dd054ffdcdf28 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 16 Mar 2022 15:05:27 +1000
Subject: [PATCH 104/712] BUGFIX: disable the thousands separator

The wire numbers are very large and it is undesirable to use a thousand
separator there. This is a side effect of enabling locale.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/command.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/command.cc b/common/command.cc
index 0de9ccc470..00f900b375 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -45,10 +45,17 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+struct no_separator : std::numpunct<char>
+{
+  protected:
+    virtual string_type do_grouping() const { return "\000"; } // groups of 0 (disable)
+};
+
 CommandHandler::CommandHandler(int argc, char **argv) : argc(argc), argv(argv)
 {
     try {
-        std::locale::global(std::locale(""));
+        std::locale loc("");
+        std::locale::global(std::locale(loc, new no_separator()));
     } catch (const std::runtime_error &e) {
         // the locale is broken in this system, so leave it as it is
     }

From c898587b87c5501fb0278990fb2bd5b2bb339fb1 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 16 Mar 2022 15:47:13 +1000
Subject: [PATCH 105/712] gowin: don't crash if no arguments are set

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/main.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gowin/main.cc b/gowin/main.cc
index 19c1d02c2d..a45a49d40e 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -56,6 +56,10 @@ po::options_description GowinCommandHandler::getArchOptions()
 
 std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Property> &values)
 {
+    if (!vm.count("device")) {
+        log_error("The device must be specified\n");
+    }
+
     std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
     std::smatch match;
     std::string device = vm["device"].as<std::string>();

From 43861c0ee298c4d2a5cc89a42e816299c7f86138 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Fri, 11 Mar 2022 16:05:37 +0100
Subject: [PATCH 106/712] nexus: Added support for the DCS Bel

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/arch.cc      | 15 +++++++++++++++
 nexus/constids.inc |  7 +++++++
 nexus/fasm.cc      | 11 +++++++++++
 nexus/global.cc    |  2 +-
 nexus/pack.cc      | 25 +++++++++++++++++++++++--
 5 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index 0241e83286..39e51a5b15 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -486,6 +486,12 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         if (fromPort == id_CLK)
             return false; // don't include delays that are actually clock-to-out here
         return lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
+    } else if(cell->type == id_DCS) {
+        if (fromPort == id_SELFORCE || fromPort == id_SEL) {
+            return false;
+        }
+        int index = get_cell_timing_idx(id_DCS, id_DCS);
+        return lookup_cell_delay(index, fromPort, toPort, delay);
     }
     return false;
 }
@@ -553,6 +559,15 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_GEN_CLOCK;
         else if (port == id_CE)
             return TMG_COMB_INPUT;
+    } else if (cell->type == id_DCS) {
+        // FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN
+        // yielded in error in the timing analyzer. For now keep those as
+        // regular combinational ports.
+        if (port == id_CLK0 || port == id_CLK1)
+            return TMG_COMB_INPUT;
+        else if (port == id_DCSOUT) {
+            return TMG_COMB_OUTPUT;
+        }
         return TMG_IGNORE;
     }
     return TMG_IGNORE;
diff --git a/nexus/constids.inc b/nexus/constids.inc
index 11726d3b1e..bdf8867b50 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -532,6 +532,13 @@ X(SCLK)
 
 X(LOCAL_VCC)
 
+X(DCS)
+X(CLK0)
+X(CLK1)
+X(SELFORCE)
+X(DCSOUT)
+X(DCSMODE)
+
 X(BEL_TYPE)
 X(BEL_Z)
 X(CEOUTMUX)
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index c8404587ef..e2eb2305e6 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -536,6 +536,15 @@ struct NexusFasmWriter
         write_cell_muxes(cell);
         pop(2);
     }
+    // Write config for DCS
+    void write_dcs(const CellInfo *cell)
+    {
+        BelId bel = cell->bel;
+        push_tile(bel.tile, ctx->id("CMUX_0"));
+        push_belname(bel);
+        write_enum(cell, "DCSMODE", "VCC");
+        pop(2);
+    }
     // Write config for an OXIDE_EBR cell
     void write_bram(const CellInfo *cell)
     {
@@ -939,6 +948,8 @@ struct NexusFasmWriter
                 write_iol(ci);
             else if (ci->type == id_DCC)
                 write_dcc(ci);
+            else if (ci->type == id_DCS)
+                write_dcs(ci);
             blank();
         }
         // Handle DCC route-throughs
diff --git a/nexus/global.cc b/nexus/global.cc
index 31bf0a6b7a..37629f6417 100644
--- a/nexus/global.cc
+++ b/nexus/global.cc
@@ -193,7 +193,7 @@ struct NexusGlobalRouter
             CellInfo *drv = ni->driver.cell;
             if (drv == nullptr)
                 continue;
-            if (drv->type == id_DCC) {
+            if (drv->type == id_DCC || drv->type == id_DCS) {
                 route_clk_net(ni);
                 continue;
             }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 66d897a866..cc86699a6b 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -860,6 +860,9 @@ struct NexusPacker
             // Skip undriven nets; and nets that are already global
             if (ni->driver.cell == nullptr)
                 continue;
+            if (ni->driver.cell->type == id_DCS) {
+                continue;
+            }
             if (ni->driver.cell->type == id_DCC) {
                 --available_globals;
                 continue;
@@ -1981,14 +1984,32 @@ struct NexusPacker
                     if (user.port == id_CLKI || user.port == id_REFCK)
                         changed_cells.insert(user.cell->name);
                 auto &drv = ctx->nets.at(net)->driver;
-                if (iter == 1 && drv.cell != nullptr && (drv.port == id_HFCLKOUT || drv.port == id_LFCLKOUT))
-                    changed_cells.insert(drv.cell->name);
+                if (iter == 1 && drv.cell != nullptr) {
+                    if (drv.cell->type == id_OSC_CORE && (drv.port == id_HFCLKOUT || drv.port == id_LFCLKOUT))
+                        changed_cells.insert(drv.cell->name);
+                    if (drv.cell->type == id_DCC && drv.port == id_CLKO)
+                        changed_cells.insert(drv.cell->name);
+                    if (drv.cell->type == id_DCS && drv.port == id_DCSOUT)
+                        changed_cells.insert(drv.cell->name);
+                }
             }
             changed_nets.clear();
             for (auto cell : changed_cells) {
                 CellInfo *ci = ctx->cells.at(cell).get();
                 if (ci->type == id_DCC) {
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
+                } else if (ci->type == id_DCS) {
+                    // For DCC copy the worst case ("fastest") constraint
+                    delay_t period_clk0, period_clk1;
+                    bool have_clk0 = get_period(ci, id_CLK0, period_clk0);
+                    bool have_clk1 = get_period(ci, id_CLK1, period_clk1);
+                    if (have_clk0 && !have_clk1) {
+                        copy_constraint(ci, id_CLK0, id_DCSOUT);
+                    } else if (!have_clk0 && have_clk1) {
+                        copy_constraint(ci, id_CLK1, id_DCSOUT);
+                    } else if ( have_clk0 && have_clk1) {
+                        set_period(ci, id_DCSOUT, std::min(period_clk0, period_clk1));
+                    }
                 } else if (ci->type == id_OSC_CORE) {
                     int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
                     const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.

From 237391c1b8047d248dc5aa27c7d78edeb86f61e9 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 15 Mar 2022 12:35:10 +0100
Subject: [PATCH 107/712] nexus: Corrected auto frequency constraint for LF
 output of OSCA

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/pack.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index cc86699a6b..bb62ec852c 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2000,7 +2000,7 @@ struct NexusPacker
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
                 } else if (ci->type == id_DCS) {
                     // For DCC copy the worst case ("fastest") constraint
-                    delay_t period_clk0, period_clk1;
+                    delay_t period_clk0 = 0, period_clk1 = 0;
                     bool have_clk0 = get_period(ci, id_CLK0, period_clk0);
                     bool have_clk1 = get_period(ci, id_CLK1, period_clk1);
                     if (have_clk0 && !have_clk1) {
@@ -2014,7 +2014,7 @@ struct NexusPacker
                     int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
                     const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
                     set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
-                    set_period(ci, id_LFCLKOUT, delay_t((1.0e3 / 10) / tol));
+                    set_period(ci, id_LFCLKOUT, delay_t((1.0e9 /  32) / tol));
                 } else if (ci->type == id_PLL_CORE) {
                     static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
                     static const std::array<IdString, 6> output{id_CLKOP,  id_CLKOS,  id_CLKOS2,

From 2635bab2f1b1a32b2505e0918caa2a91c18ce571 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 16 Mar 2022 15:44:45 +0000
Subject: [PATCH 108/712] ecp5: Fix double-counting of FFs in report

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 02ce5aa13c..f65e992ee2 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -85,7 +85,7 @@ class Ecp5Packer
                 used_ramwluts += 2;
             }
             if (is_ff(ctx, ci))
-                used_ffs += 2;
+                ++used_ffs;
         }
         log_info("Logic utilisation before packing:\n");
         auto pc = [](int used, int total) { return 100 * used / total; };

From d8244bb62d695cc0326815136caac90ed3571082 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 17 Mar 2022 19:19:38 +0000
Subject: [PATCH 109/712] mistral: Update to latest upstream

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/mistral_ci.yml |  2 +-
 mistral/bitstream.cc             | 28 +++++++++++++++++-----------
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index a02026cfff..408179b47f 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: 0c2ab2b2c6af33fea1c20349be2e0068366ed615 
+        MISTRAL_REVISION: 6b0ce163d87200d0d5b7f330349aacf886f0f8be 
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index c51050083f..80490f1f6f 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -210,7 +210,8 @@ struct MistralBitgen
         if (is_lutram) {
             for (int i = 0; i < 10; i++) {
                 // Many MLAB settings apply to the whole LAB, not just the ALM
-                cv->bmux_m_set(block_type, pos, CycloneV::MODE, i, CycloneV::RAM);
+                cv->bmux_m_set(block_type, pos, CycloneV::TMODE, i, CycloneV::RAM);
+                cv->bmux_m_set(block_type, pos, CycloneV::BMODE, i, CycloneV::RAM);
                 cv->bmux_n_set(block_type, pos, CycloneV::T_FEEDBACK_SEL, i, 1);
             }
             cv->bmux_r_set(block_type, pos, CycloneV::LUT_MASK, alm, 0xFFFFFFFFFFFFFFFFULL); // TODO: LUTRAM init
@@ -222,11 +223,11 @@ struct MistralBitgen
             cv->bmux_n_set(block_type, pos, CycloneV::WRITE_PULSE_LENGTH, 0, 650); // picoseconds, presumably
             // TODO: understand how these enables really work
             cv->bmux_b_set(block_type, pos, CycloneV::EN2_EN, 0, false);
-            cv->bmux_b_set(block_type, pos, CycloneV::EN_SCLK_LOAD_WHAT, 0, true);
-            cv->bmux_m_set(block_type, pos, CycloneV::SCLR_MUX, 0, CycloneV::GIN2);
+            cv->bmux_b_set(block_type, pos, CycloneV::SCLR_DIS, 0, true);
         } else {
-            // Combinational mode - TODO: flop feedback
-            cv->bmux_m_set(block_type, pos, CycloneV::MODE, alm, alm_data.l6_mode ? CycloneV::L6 : CycloneV::L5);
+            // Combinational mode - TODO: flop feedback and more modes...
+            cv->bmux_m_set(block_type, pos, CycloneV::TMODE, alm, alm_data.l6_mode ? CycloneV::C_E : CycloneV::E_0);
+            cv->bmux_m_set(block_type, pos, CycloneV::BMODE, alm, alm_data.l6_mode ? CycloneV::D_E : CycloneV::E_1);
             // LUT function
             cv->bmux_r_set(block_type, pos, CycloneV::LUT_MASK, alm, ctx->compute_lut_mask(lab, alm));
         }
@@ -300,12 +301,17 @@ struct MistralBitgen
             // SCLR
             if (ff->ffInfo.ctrlset.sclr.net != nullptr) {
                 cv->bmux_b_set(block_type, pos, CycloneV::SCLR_INV, 0, ff->ffInfo.ctrlset.sclr.inverted);
+                cv->bmux_b_set(block_type, pos, CycloneV::SCLR_DIS, 0, false);
             } else {
                 cv->bmux_b_set(block_type, pos, sclr_dis[i / 2], alm, true);
             }
             // SLOAD
             if (ff->ffInfo.ctrlset.sload.net != nullptr) {
                 cv->bmux_b_set(block_type, pos, sload_en[i / 2], alm, true);
+                if (ff->ffInfo.ctrlset.sload.net->name == ctx->id("$PACKER_GND_NET")) {
+                    // force-disabled LOAD (see workaround in assign_ff_info)
+                    cv->bmux_b_set(block_type, pos, CycloneV::SLOAD_EN, 0, false);
+                }
                 cv->bmux_b_set(block_type, pos, CycloneV::SLOAD_INV, 0, ff->ffInfo.ctrlset.sload.inverted);
             }
         }
@@ -340,18 +346,18 @@ struct MistralBitgen
 
         const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL};
         for (int i = 0; i < 2; i++) {
-            // Quartus seems to set unused ACLRs to CLKI2...
-            if (!lab_data.aclr_used[i])
-                cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, CycloneV::CLKI2);
-            else
-                cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1);
+            // Quartus seems to set unused ACLRs to ACLR0
+            if (lab_data.aclr_used[i])
+                cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::DIN2 : CycloneV::DIN3);
+            else if (i == 0)
+                cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, CycloneV::ACLR0);
         }
         for (int i = 0; i < 3; i++) {
             // Check for fabric->clock routing
             if (ctx->wires_connected(
                         ctx->get_port(block_type, CycloneV::pos2x(pos), CycloneV::pos2y(pos), -1, CycloneV::DATAIN, 0),
                         lab_data.clk_wires[i]))
-                cv->bmux_m_set(block_type, pos, CycloneV::CLKA_SEL, 0, CycloneV::GIN2);
+                cv->bmux_m_set(block_type, pos, CycloneV::CLKA_SEL, 0, CycloneV::DIN0);
         }
     }
 

From 14d53dfec8dba93996f5c2877d60f6ed167d14fb Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 17 Mar 2022 19:24:05 +0000
Subject: [PATCH 110/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/pack.cc | 3 ++-
 nexus/arch.cc | 2 +-
 nexus/pack.cc | 4 ++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index f533941ddd..2b5def4666 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -59,7 +59,8 @@ static void pack_lut_lutffs(Context *ctx)
                     if (ctx->verbose)
                         log_info("found attached dff %s\n", dff->name.c_str(ctx));
                     auto dff_bel = dff->attrs.find(id_BEL);
-                    if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
+                    if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() &&
+                        lut_bel->second != dff_bel->second) {
                         // Locations don't match, can't pack
                     } else {
                         lut_to_lc(ctx, ci, packed.get(), false);
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 39e51a5b15..9679c3fbed 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -486,7 +486,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         if (fromPort == id_CLK)
             return false; // don't include delays that are actually clock-to-out here
         return lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
-    } else if(cell->type == id_DCS) {
+    } else if (cell->type == id_DCS) {
         if (fromPort == id_SELFORCE || fromPort == id_SEL) {
             return false;
         }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index bb62ec852c..26da3dc5b0 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2007,14 +2007,14 @@ struct NexusPacker
                         copy_constraint(ci, id_CLK0, id_DCSOUT);
                     } else if (!have_clk0 && have_clk1) {
                         copy_constraint(ci, id_CLK1, id_DCSOUT);
-                    } else if ( have_clk0 && have_clk1) {
+                    } else if (have_clk0 && have_clk1) {
                         set_period(ci, id_DCSOUT, std::min(period_clk0, period_clk1));
                     }
                 } else if (ci->type == id_OSC_CORE) {
                     int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
                     const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
                     set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
-                    set_period(ci, id_LFCLKOUT, delay_t((1.0e9 /  32) / tol));
+                    set_period(ci, id_LFCLKOUT, delay_t((1.0e9 / 32) / tol));
                 } else if (ci->type == id_PLL_CORE) {
                     static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
                     static const std::array<IdString, 6> output{id_CLKOP,  id_CLKOS,  id_CLKOS2,

From 29654c52be93df192ce3191b39e2d4ae57120d08 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 17 Mar 2022 20:01:44 +0000
Subject: [PATCH 111/712] ci: Fixes for latest RapidWright

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/ci/build_interchange.sh      | 3 ++-
 .github/workflows/interchange_ci.yml | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.github/ci/build_interchange.sh b/.github/ci/build_interchange.sh
index 674bd5c100..3976ce4ea5 100755
--- a/.github/ci/build_interchange.sh
+++ b/.github/ci/build_interchange.sh
@@ -48,7 +48,8 @@ function get_dependencies {
         # Install RapidWright
         git clone https://github.com/Xilinx/RapidWright.git ${RAPIDWRIGHT_PATH}
         pushd ${RAPIDWRIGHT_PATH}
-        make update_jars
+        ./gradlew updateJars --no-watch-fs
+        make compile
         popd
     fi
 }
diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml
index 16b502053f..27b19c5a54 100644
--- a/.github/workflows/interchange_ci.yml
+++ b/.github/workflows/interchange_ci.yml
@@ -16,7 +16,7 @@ jobs:
     - name: Install
       run: |
         sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
+        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig locales libtinfo-dev
 
     - name: ccache
       uses: hendrikmuhs/ccache-action@v1

From 49cc4ca30b6698b93bbe90c21bedbc3b31c7c946 Mon Sep 17 00:00:00 2001
From: Maciej Dudek <mdudek@antmicro.com>
Date: Wed, 16 Mar 2022 19:24:08 +0100
Subject: [PATCH 112/712] Nexus: Fixed OSCA parameters, add pll default
 parameters

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
---
 nexus/fasm.cc | 144 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 142 insertions(+), 2 deletions(-)

diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index e2eb2305e6..b2cb03fa5e 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -521,8 +521,10 @@ struct NexusFasmWriter
         write_enum(cell, "HFDIV_FABRIC_EN", "ENABLED");
         write_enum(cell, "LF_FABRIC_EN");
         write_enum(cell, "LF_OUTPUT_EN");
+        write_enum(cell, "DTR_EN", "ENABLED");
         write_enum(cell, "DEBUG_N", "DISABLED");
         write_int_vector(stringf("HF_CLK_DIV[7:0]"), ctx->parse_lattice_param(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
+        write_int_vector(stringf("HF_SED_SEC_DIV[7:0]"), 1, 8);
         write_cell_muxes(cell);
         pop(2);
     }
@@ -681,6 +683,125 @@ struct NexusFasmWriter
             {"V2I_PP_ICTRL", 5},
     };
 
+    const dict<std::string, std::string> pll_default_params = {
+        {"BW_CTL_BIAS", "0b0101"},
+        {"CLKOP_TRIM", "0b0000"},
+        {"CLKOS_TRIM", "0b0000"},
+        {"CLKOS2_TRIM", "0b0000"},
+        {"CLKOS3_TRIM", "0b0000"},
+        {"CLKOS4_TRIM", "0b0000"},
+        {"CLKOS5_TRIM", "0b0000"},
+        {"CRIPPLE", "5P"},
+        {"CSET", "40P"},
+        {"DELAY_CTRL", "200PS"},
+        {"DELA", "0"},
+        {"DELB", "0"},
+        {"DELC", "0"},
+        {"DELD", "0"},
+        {"DELE", "0"},
+        {"DELF", "0"},
+        {"DIRECTION", "DISABLED"},
+        {"DIVA", "0"},
+        {"DIVB", "0"},
+        {"DIVC", "0"},
+        {"DIVD", "0"},
+        {"DIVE", "0"},
+        {"DIVF", "0"},
+        {"DYN_SEL", "0b000"},
+        {"DYN_SOURCE", "STATIC"},
+        {"ENCLK_CLKOP", "DISABLED"},
+        {"ENCLK_CLKOS", "DISABLED"},
+        {"ENCLK_CLKOS2", "DISABLED"},
+        {"ENCLK_CLKOS3", "DISABLED"},
+        {"ENCLK_CLKOS4", "DISABLED"},
+        {"ENCLK_CLKOS5", "DISABLED"},
+        {"ENABLE_SYNC", "DISABLED"},
+        {"FAST_LOCK_EN", "ENABLED"},
+        {"V2I_1V_EN", "DISABLED"},
+        {"FBK_CUR_BLE", "0b00000000"},
+        {"FBK_EDGE_SEL", "POSITIVE"},
+        {"FBK_IF_TIMING_CTL", "0b00"},
+        {"FBK_INTEGER_MODE", "DISABLED"},
+        {"FBK_MASK", "0b00001000"},
+        {"FBK_MMD_DIG", "8"},
+        {"FBK_MMD_PULS_CTL", "0b0000"},
+        {"FBK_MODE", "0b00"},
+        {"FBK_PI_BYPASS", "NOT_BYPASSED"},
+        {"FBK_PI_RC", "0b1100"},
+        {"FBK_PR_CC", "0b0000"},
+        {"FBK_PR_IC", "0b1000"},
+        {"FLOAT_CP", "DISABLED"},
+        {"FLOCK_CTRL", "2X"},
+        {"FLOCK_EN", "ENABLED"},
+        {"FLOCK_SRC_SEL", "REFCLK"},
+        {"FORCE_FILTER", "DISABLED"},
+        {"I_CTRL", "10UA"},
+        {"IPI_CMP", "0b1000"},
+        {"IPI_CMPN", "0b0011"},
+        {"IPI_COMP_EN", "DISABLED"},
+        {"IPP_CTRL", "0b1000"},
+        {"IPP_SEL", "0b1111"},
+        {"KP_VCO", "0b11001"},
+        {"LDT_INT_LOCK_STICKY", "DISABLED"},
+        {"LDT_LOCK", "1536CYC"},
+        {"LDT_LOCK_SEL", "U_FREQ"},
+        {"LEGACY_ATT", "DISABLED"},
+        {"LOAD_REG", "DISABLED"},
+        {"OPENLOOP_EN", "DISABLED"},
+        {"PHIA", "0"},
+        {"PHIB", "0"},
+        {"PHIC", "0"},
+        {"PHID", "0"},
+        {"PHIE", "0"},
+        {"PHIF", "0"},
+        {"PLLPDN_EN", "DISABLED"},
+        {"PLLPD_N", "UNUSED"},
+        {"PLLRESET_ENA", "DISABLED"},
+        {"REF_INTEGER_MODE", "DISABLED"},
+        {"REF_MASK", "0b00000000"},
+        {"REF_MMD_DIG", "8"},
+        {"REF_MMD_IN", "0b00001000"},
+        {"REF_MMD_PULS_CTL", "0b0000"},
+        {"REF_TIMING_CTL", "0b00"},
+        {"REFIN_RESET", "SET"},
+        {"RESET_LF", "DISABLED"},
+        {"ROTATE", "DISABLED"},
+        {"SEL_OUTA", "DISABLED"},
+        {"SEL_OUTB", "DISABLED"},
+        {"SEL_OUTC", "DISABLED"},
+        {"SEL_OUTD", "DISABLED"},
+        {"SEL_OUTE", "DISABLED"},
+        {"SEL_OUTF", "DISABLED"},
+        {"SLEEP", "DISABLED"},
+        {"SSC_DELTA", "0b000000000000000"},
+        {"SSC_DELTA_CTL", "0b00"},
+        {"SSC_DITHER", "DISABLED"},
+        {"SSC_EN_CENTER_IN", "DOWN_TRIANGLE"},
+        {"SSC_EN_SDM", "DISABLED"},
+        {"SSC_EN_SSC", "DISABLED"},
+        {"SSC_F_CODE", "0b000000000000000"},
+        {"SSC_N_CODE", "0b000010100"},
+        {"SSC_ORDER", "SDM_ORDER2"},
+        {"SSC_PI_BYPASS", "NOT_BYPASSED"},
+        {"SSC_REG_WEIGHTING_SEL", "0b000"},
+        {"SSC_SQUARE_MODE", "DISABLED"},
+        {"SSC_STEP_IN", "0b0000000"},
+        {"SSC_TBASE", "0b000000000000"},
+        {"STDBY_ATT", "DISABLED"},
+        {"TRIMOP_BYPASS_N", "BYPASSED"},
+        {"TRIMOS_BYPASS_N", "BYPASSED"},
+        {"TRIMOS2_BYPASS_N", "BYPASSED"},
+        {"TRIMOS3_BYPASS_N", "BYPASSED"},
+        {"TRIMOS4_BYPASS_N", "BYPASSED"},
+        {"TRIMOS5_BYPASS_N", "BYPASSED"},
+        {"V2I_KVCO_SEL", "85"},
+        {"V2I_PP_ICTRL", "0b00110"},
+        {"V2I_PP_RES", "10K"},
+        {"CLKMUX_FB", "CMUX_CLKOP"},
+        {"SEL_FBK", "DIVA"},
+        {"DIV_DEL", "0b0000001"},
+    };
+
     // Which MIPI params are 'word' values
     const dict<std::string, int> dphy_word_params = {
             {"CM", 8}, {"CN", 5}, {"CO", 3}, {"RSEL", 2}, {"RXCDRP", 2},
@@ -691,6 +812,14 @@ struct NexusFasmWriter
     };
     /* clang-format on */
 
+    static bool is_number(std::string s) {
+        for (auto c  : s) {
+            if(!isdigit(c))
+                return false;
+        }
+        return true;
+    }
+
     // Write out config for some kind of PLL cell
     void write_pll(const CellInfo *cell)
     {
@@ -701,14 +830,25 @@ struct NexusFasmWriter
         write_cell_muxes(cell);
         pop();
         push(stringf("IP_%s", ctx->nameOf(IdString(ctx->bel_data(bel).name))));
-        for (auto &param : cell->params) {
+        CellInfo temp(*cell);
+        for (auto param : cell->params) temp.params.insert(param);
+        for (auto &value : pll_default_params) {
+            IdString n = IdString(ctx, value.first);
+            if (!temp.params.count(n)) {
+                if (is_number(value.second))
+                    temp.params[ctx->id(value.first)] = Property(std::stoi(value.second), 32);
+                else
+                    temp.params[ctx->id(value.first)] = Property::from_string(value.second);
+            }
+        }
+        for (auto &param : temp.params) {
             const std::string &name = param.first.str(ctx);
             if (is_mux_param(name) || name == "CLKMUX_FB" || name == "SEL_FBK")
                 continue;
             auto fnd_word = pll_word_params.find(name);
             if (fnd_word != pll_word_params.end()) {
                 write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
-                                 ctx->parse_lattice_param(cell, param.first, fnd_word->second, 0).as_int64(),
+                                 ctx->parse_lattice_param(&temp, param.first, fnd_word->second, 0).as_int64(),
                                  fnd_word->second);
             } else {
                 write_bit(stringf("%s.%s", name.c_str(), param.second.as_string().c_str()));

From 5e9236f9d4679d4596f0e593cdeff674229f5818 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 18 Mar 2022 18:54:12 +0000
Subject: [PATCH 113/712] mistral: Updated CLK mux select name

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/mistral_ci.yml | 2 +-
 mistral/bitstream.cc             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 408179b47f..b0bbfb521e 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: 6b0ce163d87200d0d5b7f330349aacf886f0f8be 
+        MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9 
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 80490f1f6f..3e1b8b6642 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -114,7 +114,7 @@ struct MistralBitgen
     {
         (void)ci; // currently unused
         auto pos = CycloneV::xy2pos(x, y);
-        cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing
+        cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SEL, bi, 0x1b); // hardcode to general routing
         cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
     }
 

From 774d3944b307a7b26164f728b5910f26b7d873f6 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 19 Mar 2022 18:43:31 +0000
Subject: [PATCH 114/712] parallel_refine: Fix compile error with some configs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/parallel_refine.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/parallel_refine.cc b/common/parallel_refine.cc
index bc665cd3ca..a868ca582f 100644
--- a/common/parallel_refine.cc
+++ b/common/parallel_refine.cc
@@ -546,6 +546,7 @@ struct ThreadState
 
     bool accept_move()
     {
+        static constexpr double epsilon = 1e-20;
         double delta = g.cfg.lambda * (timing_delta / std::max<double>(epsilon, g.total_timing_cost)) +
                        (1.0 - g.cfg.lambda) * (double(wirelen_delta) / std::max<double>(epsilon, g.total_wirelen));
         return delta < 0 ||
@@ -565,7 +566,6 @@ struct ThreadState
         return true;
     }
 
-    static constexpr double epsilon = 1e-20;
     bool single_cell_swap(CellInfo *cell, BelId new_bel)
     {
         NPNR_ASSERT(moved_cells.empty());

From bb923c7732dbf8c930c8af85acd6f0583115af8e Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sat, 19 Mar 2022 19:44:08 +0100
Subject: [PATCH 115/712] Gowin: use global VCC and VSS nets (#956)

* use global VCC and VSS nets

* derp

* remove init parameter
---
 gowin/arch.cc      | 11 ++++++++++-
 gowin/cells.cc     |  4 ++++
 gowin/constids.inc |  2 ++
 gowin/pack.cc      | 15 ++++++---------
 4 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 6213124f99..4400a55458 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -440,7 +440,9 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
 {
     const std::string &wirename = wire.str(this);
     char buf[32];
-    if (wirename == "VCC" || wirename == "GND") {
+    if (wirename == "VCC" || wirename == "VSS") {
+        row = 0;
+        col = 0;
         return wire;
     }
     if (!isdigit(wirename[1]) || !isdigit(wirename[2]) || !isdigit(wirename[3])) {
@@ -949,6 +951,13 @@ Arch::Arch(ArchArgs args) : args(args)
              package_name.c_str(this), speed_id.c_str(this));
 
     // setup db
+    // add global VCC and GND bels
+    addBel(id_GND, id_GND, Loc(0, 0, 998), true);
+    addWire(id_VSS, id_VSS, 0, 0);
+    addBelOutput(id_GND, id_G, id_VSS);
+    addBel(id_VCC, id_VCC, Loc(0, 0, 999), true);
+    addWire(id_VCC, id_VCC, 0, 0);
+    addBelOutput(id_VCC, id_V, id_VCC);
     char buf[32];
     // The reverse order of the enumeration simplifies the creation
     // of MUX2_LUT8s: they need the existence of the wire on the right.
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 8e450b5140..c3b2178259 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -65,6 +65,10 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_O);
     } else if (type == id_GSR) {
         new_cell->addInput(id_GSRI);
+    } else if (type == id_GND) {
+        new_cell->addOutput(id_G);
+    } else if (type == id_VCC) {
+        new_cell->addOutput(id_V);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 125fdc74b4..b293293b66 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -787,6 +787,8 @@ X(SUM)
 X(CIN)
 X(COUT)
 X(OF)
+X(V)
+X(G)
 
 // timing
 X(X0)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 9f0a2478e6..d31b4a84c8 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -611,20 +611,17 @@ static void pack_constants(Context *ctx)
 {
     log_info("Packing constants..\n");
 
-    std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_GND");
-    gnd_cell->params[id_INIT] = Property(0, 1 << 4);
+    std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, id_GND, "$PACKER_GND");
     auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
     gnd_net->driver.cell = gnd_cell.get();
-    gnd_net->driver.port = id_F;
-    gnd_cell->ports.at(id_F).net = gnd_net.get();
+    gnd_net->driver.port = id_G;
+    gnd_cell->ports.at(id_G).net = gnd_net.get();
 
-    std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_VCC");
-    // Fill with 1s
-    vcc_cell->params[id_INIT] = Property(Property::S1).extract(0, (1 << 4), Property::S1);
+    std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, id_VCC, "$PACKER_VCC");
     auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
     vcc_net->driver.cell = vcc_cell.get();
-    vcc_net->driver.port = id_F;
-    vcc_cell->ports.at(id_F).net = vcc_net.get();
+    vcc_net->driver.port = id_V;
+    vcc_cell->ports.at(id_V).net = vcc_net.get();
 
     std::vector<IdString> dead_nets;
 

From b2348281252f7dc4ea052269a5c5db02f7c03803 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 21 Mar 2022 19:58:36 +0000
Subject: [PATCH 116/712] docs: Initial reference for the Viaduct 'uarch' API

Signed-off-by: gatecat <gatecat@ds0.me>
---
 docs/generic.md |   8 ++-
 docs/viaduct.md | 131 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 137 insertions(+), 2 deletions(-)
 create mode 100644 docs/viaduct.md

diff --git a/docs/generic.md b/docs/generic.md
index 96db872e84..108d41d72d 100644
--- a/docs/generic.md
+++ b/docs/generic.md
@@ -1,8 +1,12 @@
 # nextpnr Generic Architecture
 
-Instead of implementing the [C++ API](archapi.md), you can programmatically 
+Instead of implementing the full [C++ API](archapi.md), you can programmatically 
 build up a description of an FPGA using the generic architecture and the 
-Python API.
+Python API, or the [Viaduct C++ API](viaduct.md) (described further in its own
+document).
+
+The Viaduct API allows more complex constraints to be implemented and has shorter
+startup times than using the Python API.
 
 A basic packer is provided that supports LUTs, flipflops and IO buffer insertion.
 Packing could also be implemented using the Python API.
diff --git a/docs/viaduct.md b/docs/viaduct.md
new file mode 100644
index 0000000000..a59310f14d
--- /dev/null
+++ b/docs/viaduct.md
@@ -0,0 +1,131 @@
+# Viaduct - a series of small arches
+
+Viaduct is a C++-based successor to the Python generic API that gets most of the benefits of a full-custom nextpnr architecture, with the simplicity of a harness to build from and a predefined flat set of data structures for the placement and routing resources.
+
+Like the Python generic API, the routing graph can be built programmatically, or loaded from an external data source at startup. However, the Viaduct framework provides considerably improved startup times by relying less on strings and eliminating the C++/Python boundary; and also enables more complex architectures to be modeled with arbitrary place-and-route time constraints implemented as code, in the spirit of nextpnr.
+
+A Viaduct implementation is called a 'uarch' (microarch), because it's smaller than a full architecture.
+
+Viaduct implementations, including some examples, are located as subfolders of `generic/viaduct/`.
+
+## Viaduct API Reference
+
+### Initialisation
+
+A Viaduct uarch must override `ViaductAPI` - see `generic/viaduct_api.h`. This contains virtual methods to be optionally overridden, in most cases only a small number of these need be.
+
+```c++
+void init(Context *ctx)
+```
+
+This should perform device resources initialisation. uarches should always call the superclass `ViaductAPI::init(ctx)` first, too.
+
+Bels (placement locations), wires ('metal' interconnect) and pips (programmable switches that connect wires) can be dynamically created by calling the methods of `Context` described in the [generic arch docs](coding.md) - the most important methods to start with are:
+
+```c++
+ctx->addWire(IdStringList name, IdString type, int x, int y);
+ctx->addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, float delay, Loc loc);
+ctx->addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
+ctx->addBelInput(BelId bel, IdString name, WireId wire);
+ctx->addBelOutput(BelId bel, IdString name, WireId wire);
+ctx->addBelInout(BelId bel, IdString name, WireId wire);
+```
+
+### Helpers
+
+nextpnr uses an indexed, interned string type for performance and object names (for bels, wires and pips) are based on lists of these. To performantly build these; you can add a `ViaductHelpers` instance to your uarch, call `init(ctx)` on it, and then use the `xy_id(x, y, base)` member functions of this. For example:
+
+```c++
+ViaductHelpers h;
+h.init(ctx);
+ctx->addWire(h.xy_id(13, 45, ctx->id("CLK0")), ctx->id("CLK"), 13, 45);
+```
+
+To create a wire named `X13/Y45/CLK0`.
+
+### Constant IDs
+
+In some cases, such as during packing and validity checks, `IdString`s for strings such as common port names will be needed a large number of times. To avoid the string hash and compare associated with `ctx->id("string")`, you can use the "constids" support. To use this:
+
+ - create a 'constids.inc' file in your uarch folder containing one ID per line; inside X( ). For example:
+```
+X(LUT4)
+X(DFF)
+X(CLK)
+X(D)
+X(F)
+```
+  -  set the `VIADUCT_CONSTIDS` macro to the path to this file relative to the generic arch base
+  -  in the same file as `init` is implemented; also define the `GEN_INIT_CONSTIDS` macro before the `viaduct_constids.h` include to create `init_uarch_constids`, which you should call in your `init` implementation.
+  -  in any file you need the constant `IdString`s, include `viaduct_constids.h` and the ids will be accessible as constants named like `id_LUT4`.
+
+### Constraints
+
+```c++
+bool checkBelAvail(BelId bel) const;
+bool isValidBelForCellType(IdString cell_type, BelId bel) const;
+bool isBelLocationValid(BelId bel) const;
+bool checkWireAvail(WireId wire) const;
+bool checkPipAvail(PipId pip) const;
+bool checkPipAvailForNet(PipId pip, NetInfo *net) const;
+```
+
+These can be overriden, if needed to implement nextpnr's system of arbitrary,architecture-defined constraints on legal placements and the availability of placement and routing resources. These could be used to implement placement rules inside tiles (like clocks that are shared between flipflops); or disable one routing resource when a conflicting one is used. They only need to be overriden, and return false, where a resource is unavailable due to a specific, custom constraint and not just because that resource itself is occupied.
+
+For more information on terminology, see [FAQ](faq.md); for references of these functions see the [Arch API](archapi.md) docs; and for some general hints see the [Coding Tips](coding.md).
+
+uarches may update internal, constraint-related structures based on placement and routing updates by optionally overriding the 'hook' functions called whenever bindings are changed.
+
+```c++
+void notifyBelChange(BelId bel, CellInfo *cell);
+void notifyWireChange(WireId wire, NetInfo *net);
+void notifyPipChange(PipId pip, NetInfo *net);
+```
+
+These will be called with `cell` or `net` pointing to the object the resource is being bound to for a bind; or `nullptr` for an unbind.
+
+### Packing
+
+Although arches can implement as much or as little packing as they like, nextpnr leans towards doing minimal pre-placement packing and leaving the combination of LUTs and flipflops into tiles, and similar tasks, down to placement validity checks (`checkBelAvail`).
+
+Any packing tasks that do need to be done; for example cleaning up top level IO pairing cells that should always stay together using relative constraints, should be done by overriding the `pack` method:
+
+```c++
+void pack();
+```
+
+
+There are also hooks to perform custom transformations or steps in-between and after placement and routing:
+
+```c++
+void prePlace();
+void postPlace();
+void preRoute();
+void postRoute();
+```
+
+The most common use for this would be to implement a custom bitstream generation step (or similar intermediate format) inside `postRoute` on the final design. Another example use case would be to implement a custom global clock routing pass in `preRoute`.
+
+### ViaductArch
+
+As well as creating the uarch class that derives from `ViaductAPI`, you also need to create a factory for it by creating a singleton of a class that derives from `ViaductArch`. This should, in its constructor, construct `ViaductArch` with the arch name, and also implement the `create` function to return a new instance of your `ViaductAPI` implementation. For example:
+
+```c++
+struct ExampleArch : ViaductArch
+{
+    ExampleArch() : ViaductArch("example"){};
+    std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<ExampleImpl>();
+    }
+} exampleArch;
+```
+
+### Adding a new uarch
+
+The reference above provides an overview of what a Viaduct uarch must implement, it's also recommended to look at the `generic` and `okami` examples in `generic/viaduct`. New uarches should have their source contained in subfolders of `generic/viaduct`; and added to `VIADUCT_UARCHES` list in `generic/family.cmake`.
+
+Once you've implemented `ViaductAPI` and created the `ViaductArch` singleton, you should be able to run nextpnr with the arch by running `nextpnr-generic --uarch <name>`.
+
+
+

From 69b4461f5531f6d05ed8bd4342a7dcecf774b8ef Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 22 Mar 2022 06:15:29 +1000
Subject: [PATCH 117/712] gowin: Name the constants (#958)

Place arbitrary constants side by side to avoid conflicts.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 4400a55458..fa0a66a3e8 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -952,10 +952,10 @@ Arch::Arch(ArchArgs args) : args(args)
 
     // setup db
     // add global VCC and GND bels
-    addBel(id_GND, id_GND, Loc(0, 0, 998), true);
+    addBel(id_GND, id_GND, Loc(0, 0, BelZ::gnd_0_z), true);
     addWire(id_VSS, id_VSS, 0, 0);
     addBelOutput(id_GND, id_G, id_VSS);
-    addBel(id_VCC, id_VCC, Loc(0, 0, 999), true);
+    addBel(id_VCC, id_VCC, Loc(0, 0, BelZ::vcc_0_z), true);
     addWire(id_VCC, id_VCC, 0, 0);
     addBelOutput(id_VCC, id_V, id_VCC);
     char buf[32];

From 07c8506372e48602787dda7fc3edd7b3aef31a37 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 25 Mar 2022 15:55:07 +0000
Subject: [PATCH 118/712] ice40: Improve error reporting for PLL conflicts

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/pack.cc | 39 ++++++++++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 7 deletions(-)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index 2b5def4666..263903b090 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -962,31 +962,56 @@ static void place_plls(Context *ctx)
 
             // Find a BEL for it
             BelId found_bel;
+            std::string conflict_str = "";
             for (auto bel_pll : pll_all_bels) {
-                if (pll_used_bels.count(bel_pll.first))
+                if (pll_used_bels.count(bel_pll.first)) {
+                    conflict_str +=
+                            stringf("    PLL bel '%s' is already used by '%s'.\n", ctx->nameOfBel(bel_pll.first),
+                                    pll_used_bels.at(bel_pll.first)->name.c_str(ctx));
                     continue;
+                }
                 BelPin pll_io_a, pll_io_b;
                 BelId gb_a, gb_b;
                 std::tie(pll_io_a, gb_a, pll_io_b, gb_b) = bel_pll.second;
                 if (bel2io.count(pll_io_a.bel)) {
                     if (pll_io_a.bel == pad_bel)
                         could_be_pad = !bel2io.count(pll_io_b.bel) || !is_sb_pll40_dual(ctx, ci);
+                    auto conflict_pin = ctx->get_bel_package_pin(pll_io_a.bel);
+                    conflict_str +=
+                            stringf("    PLL bel '%s' cannot be used as it conflicts with input '%s' on pin '%s'.\n",
+                                    ctx->nameOfBel(bel_pll.first), bel2io.at(pll_io_a.bel)->name.c_str(ctx),
+                                    conflict_pin.c_str());
                     continue;
                 }
-                if (bel2io.count(pll_io_b.bel) && is_sb_pll40_dual(ctx, ci))
+                if (bel2io.count(pll_io_b.bel) && is_sb_pll40_dual(ctx, ci)) {
+                    auto conflict_pin = ctx->get_bel_package_pin(pll_io_b.bel);
+                    conflict_str +=
+                            stringf("    PLL bel '%s' cannot be used as it conflicts with input '%s' on pin '%s'.\n",
+                                    ctx->nameOfBel(bel_pll.first), bel2io.at(pll_io_b.bel)->name.c_str(ctx),
+                                    conflict_pin.c_str());
                     continue;
-                if (gb_a_used && bel2gb.count(gb_a))
+                }
+                if (gb_a_used && bel2gb.count(gb_a)) {
+                    conflict_str += stringf(
+                            "    PLL bel '%s' cannot be used as it conflicts with global buffer '%s' at '%s'.\n",
+                            ctx->nameOfBel(bel_pll.first), bel2gb.at(gb_a)->name.c_str(ctx), ctx->nameOfBel(gb_a));
                     continue;
-                if (gb_b_used && bel2gb.count(gb_b))
+                }
+                if (gb_b_used && bel2gb.count(gb_b)) {
+                    conflict_str += stringf(
+                            "    PLL bel '%s' cannot be used as it conflicts with global buffer '%s' at '%s'.\n",
+                            ctx->nameOfBel(bel_pll.first), bel2gb.at(gb_b)->name.c_str(ctx), ctx->nameOfBel(gb_b));
                     continue;
+                }
                 found_bel = bel_pll.first;
                 break;
             }
 
             // Apply constrain & Inform user of result
-            if (found_bel == BelId())
-                log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n", ci->name.c_str(ctx),
-                          could_be_pad ? " Did you mean to use a PAD PLL ?" : "");
+            if (found_bel == BelId()) {
+                log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n%s\n", ci->name.c_str(ctx),
+                          could_be_pad ? " Did you mean to use a PAD PLL ?" : "", conflict_str.c_str());
+            }
 
             log_info("  constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->nameOfBel(found_bel));
             if (could_be_pad)

From be8d3fd74dae297d79e41165c2141aadef3d6582 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 26 Mar 2022 20:56:30 +1000
Subject: [PATCH 119/712] gowin: Consider the peculiarity of GW1BR-9C

The GW1NR-9C chip ODDR implementation differs from all other supported
chips by two suspicious inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 15 +++++++++++++++
 gowin/arch.h       |  3 +++
 gowin/constids.inc |  2 ++
 gowin/pack.cc      |  7 +++++++
 4 files changed, 27 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index fa0a66a3e8..dc40b17989 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1158,6 +1158,21 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_CLK, id(buf));
 
+                const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS);
+                if (xxx_port != nullptr) {
+                    ddr_has_extra_inputs = true;
+                    portname = IdString(xxx_port->src_id);
+                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    addBelInput(belname, id_XXX_VSS, id(buf));
+                }
+                xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC);
+                if (xxx_port != nullptr) {
+                    ddr_has_extra_inputs = true;
+                    portname = IdString(xxx_port->src_id);
+                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    addBelInput(belname, id_XXX_VCC, id(buf));
+                }
+
                 if (oddrc) {
                     portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CE)->src_id);
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
diff --git a/gowin/arch.h b/gowin/arch.h
index c8392e7e4e..bc29a59bf9 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -470,6 +470,9 @@ struct Arch : BaseArch<ArchRanges>
     void updateClockSpinesCache(IdString spine_id, IdString wire_id);
     void fixClockSpineDecals(void);
 
+    // XXX GW1N-9C DDR quirk
+    bool ddr_has_extra_inputs = false;
+
     // Permissible combinations of modes in a single slice
     std::map<const IdString, IdString> dff_comp_mode;
 };
diff --git a/gowin/constids.inc b/gowin/constids.inc
index b293293b66..8159cc108d 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -681,6 +681,8 @@ X(IOBJS)
 
 // IOLOGIC
 X(TX)
+X(XXX_VSS)
+X(XXX_VCC)
 X(OBUF_TYPE)
 X(SBUF)
 X(DBUF)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index d31b4a84c8..28370a7557 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -798,6 +798,13 @@ static void pack_iologic(Context *ctx)
                         ci->attrs[id_IOBUF] = 1;
                     }
                 }
+                // if have XXX_ inputs connect them
+                if (ctx->ddr_has_extra_inputs) {
+                    ci->addInput(id_XXX_VSS);
+                    ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                    ci->addInput(id_XXX_VCC);
+                    ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                }
             } break;
             default:
                 break;

From 12b38bab6d630e14381870f51ccfd52c5a10b337 Mon Sep 17 00:00:00 2001
From: Tim Pambor <tp@osasysteme.de>
Date: Sun, 27 Mar 2022 22:15:12 +0200
Subject: [PATCH 120/712] gowin: Add bels for oscillator

---
 gowin/arch.cc      | 38 ++++++++++++++++++++++++++++++++++++++
 gowin/constids.inc |  8 ++++++++
 2 files changed, 46 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index dc40b17989..2c1e50b740 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1009,6 +1009,44 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_GSRI, id(buf));
                 break;
+            case ID_OSC:
+                snprintf(buf, 32, "R%dC%d_OSC", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSC, Loc(col, row, 0), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                break;
+            case ID_OSCH:
+                snprintf(buf, 32, "R%dC%d_OSCH", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSCH, Loc(col, row, 0), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                break;
+            case ID_OSCF:
+                snprintf(buf, 32, "R%dC%d_OSCF", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSCF, Loc(col, row, 0), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_OSCEN, id(buf));
+                break;
+            case ID_OSCZ:
+                snprintf(buf, 32, "R%dC%d_OSCZ", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSCZ, Loc(col, row, 0), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_OSCEN, id(buf));
+                break;
             // fall through the ++
             case ID_LUT7:
                 z++;
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 8159cc108d..d2a6b171de 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -758,6 +758,12 @@ X(GSR)
 X(GSR0)
 X(GSRI)
 
+// Oscillators
+X(OSC)
+X(OSCZ)
+X(OSCH)
+X(OSCF)
+
 // primitive attributes
 X(INIT)
 X(FF_USED)
@@ -791,6 +797,8 @@ X(COUT)
 X(OF)
 X(V)
 X(G)
+X(OSCOUT)
+X(OSCEN)
 
 // timing
 X(X0)

From 5a9ddc067588c895a483dbb314f3ff72c72fabe2 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 28 Mar 2022 14:06:09 +0100
Subject: [PATCH 121/712] ice40: Merge driving LUT<=2s into carry-only LCs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .cirrus/Dockerfile.ubuntu20.04 |  2 +-
 ice40/arch.cc                  | 29 ++++++++++++++--
 ice40/archdefs.h               |  1 +
 ice40/pack.cc                  | 63 ++++++++++++++++++++++++++++++++++
 4 files changed, 91 insertions(+), 4 deletions(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index d1e7b47bf9..6561ed59a0 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -29,7 +29,7 @@ RUN set -e -x ;\
     cd /usr/local/src ;\
     git clone --recursive https://github.com/YosysHQ/icestorm.git ;\
     cd icestorm ;\
-    git reset --hard 4bc68c9620e6be20f8fe10d20f84681d80beac23 ;\
+    git reset --hard 9f66f9ce16941c6417813cb87653c735a78b53ae ;\
     make -j $(nproc) ;\
     make install
 
diff --git a/ice40/arch.cc b/ice40/arch.cc
index b36c82d522..6746b3028f 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -923,9 +923,20 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
 
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
-    if (cell->type == id_ICESTORM_LC && cell->lcInfo.dffEnable) {
-        if (toPort == id_O)
-            return false;
+    if (cell->type == id_ICESTORM_LC) {
+        if (toPort == id_O) {
+            if (cell->lcInfo.dffEnable)
+                return false;
+            // "false paths"
+            if (fromPort == id_I0 && ((cell->lcInfo.lutInputMask & 0x1U) == 0))
+                return false;
+            if (fromPort == id_I1 && ((cell->lcInfo.lutInputMask & 0x2U) == 0))
+                return false;
+            if (fromPort == id_I2 && ((cell->lcInfo.lutInputMask & 0x4U) == 0))
+                return false;
+            if (fromPort == id_I3 && ((cell->lcInfo.lutInputMask & 0x8U) == 0))
+                return false;
+        }
     } else if (cell->type == id_ICESTORM_RAM || cell->type == id_ICESTORM_SPRAM) {
         return false;
     }
@@ -1231,6 +1242,18 @@ void Arch::assignCellInfo(CellInfo *cell)
             cell->lcInfo.inputCount++;
         if (cell->getPort(id_I3))
             cell->lcInfo.inputCount++;
+        // Find don't care LUT inputs to mask for timing analysis
+        cell->lcInfo.lutInputMask = 0x0;
+        unsigned init = int_or_default(cell->params, id_LUT_INIT);
+        for (unsigned k = 0; k < 4; k++) {
+            for (unsigned i = 0; i < 16; i++) {
+                // If toggling the LUT input makes a difference it's not a don't care
+                if (((init >> i) & 0x1U) != ((init >> (i ^ (1U << k))) & 0x1U)) {
+                    cell->lcInfo.lutInputMask |= (1U << k);
+                    break;
+                }
+            }
+        }
     } else if (cell->type == id_SB_IO) {
         cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT";
         cell->ioInfo.global = bool_or_default(cell->attrs, id_GLOBAL);
diff --git a/ice40/archdefs.h b/ice40/archdefs.h
index 3d8ea28213..07b209f137 100644
--- a/ice40/archdefs.h
+++ b/ice40/archdefs.h
@@ -137,6 +137,7 @@ struct ArchCellInfo : BaseClusterInfo
             bool carryEnable;
             bool negClk;
             int inputCount;
+            unsigned lutInputMask;
             const NetInfo *clk, *cen, *sr;
         } lcInfo;
         struct
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 263903b090..92297e8edd 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -266,6 +266,68 @@ static void pack_carries(Context *ctx)
     log_info("    %4d LCs used as CARRY only\n", carry_only);
 }
 
+static void merge_carry_luts(Context *ctx)
+{
+    // Find carrys
+    log_info("Packing indirect carry+LUT pairs...\n");
+    // Find cases where a less-than-LUT2 is driving a carry and pack them together
+    //    +----+    +-----+ |
+    // A--|LUT2|----|CARRY| |
+    // B--|    |  C-|     |-+
+    //    +----+  +-|     |
+    //            | +-----+
+    //            |
+    pool<IdString> packed_cells;
+    auto rewrite_init = [](unsigned lut_init) {
+        // I0 -> LUT I2
+        // I1, I2 -> carry; don't care
+        // I3 -> LUT I3
+        unsigned result = 0;
+        for (unsigned i = 0; i < 16; i++) {
+            unsigned j = 0;
+            if ((i & 1))
+                j |= 4;
+            if ((i & 8))
+                j |= 8;
+            if (lut_init & (1 << j))
+                result |= (1 << i);
+        }
+        return result;
+    };
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_ICESTORM_LC || !bool_or_default(ci->params, id_CARRY_ENABLE))
+            continue; // not a carry LC
+        if (ci->getPort(id_O))
+            continue;                      // LUT output is already used
+        for (auto port : {id_I1, id_I2}) { // check carry inputs
+            NetInfo *i = ci->getPort(port);
+            if (!i)
+                continue;
+            CellInfo *drv = i->driver.cell;
+            if (i->driver.port != id_O)
+                continue;
+            if (!drv || drv->type != id_ICESTORM_LC || packed_cells.count(drv->name) ||
+                bool_or_default(drv->params, id_CARRY_ENABLE) || bool_or_default(drv->params, id_DFF_ENABLE))
+                continue; // not driven by a LUT, or driver already swallowed
+            // Check cardinality - must be LUT2 or less, noting top inputs used first
+            if (drv->getPort(id_I0) || drv->getPort(id_I1))
+                continue;
+            // Pack into carry
+            drv->movePortTo(id_I2, ci, id_I0);
+            drv->movePortTo(id_I3, ci, id_I3);
+            drv->movePortTo(id_O, ci, id_O);
+            ci->params[id_LUT_INIT] = Property(rewrite_init(int_or_default(drv->params, id_LUT_INIT)), 16);
+            packed_cells.insert(drv->name);
+            break;
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    log_info("    %4d LUTs merged into carry LCs\n", int(packed_cells.size()));
+}
+
 // "Pack" RAMs
 static void pack_ram(Context *ctx)
 {
@@ -1642,6 +1704,7 @@ bool Arch::pack()
         pack_lut_lutffs(ctx);
         pack_nonlut_ffs(ctx);
         pack_carries(ctx);
+        merge_carry_luts(ctx);
         pack_ram(ctx);
         place_plls(ctx);
         pack_special(ctx);

From b9e76d1bcd556da7b25d58ff9aa6134b4d81ab30 Mon Sep 17 00:00:00 2001
From: Maciej Dudek <mdudek@antmicro.com>
Date: Wed, 30 Mar 2022 14:59:47 +0200
Subject: [PATCH 122/712] Rename parse_lattice_param to
 parse_lattice_param_from_cell Add new definition for parse_lattice_param

Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
---
 nexus/arch.h  |  3 ++-
 nexus/fasm.cc | 39 ++++++++++++++++++++++-----------------
 nexus/pack.cc | 40 ++++++++++++++++++++++------------------
 3 files changed, 46 insertions(+), 36 deletions(-)

diff --git a/nexus/arch.h b/nexus/arch.h
index ea4e9f5bbe..323dcacdc7 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1408,7 +1408,8 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     // Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
-    Property parse_lattice_param(const CellInfo *ci, IdString prop, int width, int64_t defval) const;
+    Property parse_lattice_param_from_cell(const CellInfo *ci, IdString prop, int width, int64_t defval) const;
+    Property parse_lattice_param(const Property &val, IdString prop, int width, const char* ci="") const;
 
     // -------------------------------------------------
 
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index b2cb03fa5e..a6e94d73a7 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -523,7 +523,7 @@ struct NexusFasmWriter
         write_enum(cell, "LF_OUTPUT_EN");
         write_enum(cell, "DTR_EN", "ENABLED");
         write_enum(cell, "DEBUG_N", "DISABLED");
-        write_int_vector(stringf("HF_CLK_DIV[7:0]"), ctx->parse_lattice_param(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
+        write_int_vector(stringf("HF_CLK_DIV[7:0]"), ctx->parse_lattice_param_from_cell(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
         write_int_vector(stringf("HF_SED_SEC_DIV[7:0]"), 1, 8);
         write_cell_muxes(cell);
         pop(2);
@@ -830,28 +830,33 @@ struct NexusFasmWriter
         write_cell_muxes(cell);
         pop();
         push(stringf("IP_%s", ctx->nameOf(IdString(ctx->bel_data(bel).name))));
-        CellInfo temp(*cell);
-        for (auto param : cell->params) temp.params.insert(param);
         for (auto &value : pll_default_params) {
             IdString n = IdString(ctx, value.first);
-            if (!temp.params.count(n)) {
-                if (is_number(value.second))
-                    temp.params[ctx->id(value.first)] = Property(std::stoi(value.second), 32);
-                else
-                    temp.params[ctx->id(value.first)] = Property::from_string(value.second);
-            }
-        }
-        for (auto &param : temp.params) {
-            const std::string &name = param.first.str(ctx);
+            Property temp;
+            if (is_number(value.second))
+                temp = Property(std::stoi(value.second), 32);
+            else
+                temp = Property::from_string(value.second);
+            const std::string &name = n.str(ctx);
             if (is_mux_param(name) || name == "CLKMUX_FB" || name == "SEL_FBK")
                 continue;
             auto fnd_word = pll_word_params.find(name);
             if (fnd_word != pll_word_params.end()) {
-                write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
-                                 ctx->parse_lattice_param(&temp, param.first, fnd_word->second, 0).as_int64(),
-                                 fnd_word->second);
+                if (cell->params.count(n)) {
+                    write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
+                                    ctx->parse_lattice_param_from_cell(cell, n, fnd_word->second, 0).as_int64(),
+                                    fnd_word->second);
+                } else {
+                    write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
+                                    ctx->parse_lattice_param(temp, n, fnd_word->second).as_int64(),
+                                    fnd_word->second);
+                }
             } else {
-                write_bit(stringf("%s.%s", name.c_str(), param.second.as_string().c_str()));
+                if (cell->params.count(n)) {
+                    write_bit(stringf("%s.%s", name.c_str(), cell->params.at(n).as_string().c_str()));
+                } else {
+                    write_bit(stringf("%s.%s", name.c_str(), temp.as_string().c_str()));
+                }
             }
         }
         pop();
@@ -869,7 +874,7 @@ struct NexusFasmWriter
             auto fnd_word = dphy_word_params.find(name);
             if (fnd_word != dphy_word_params.end()) {
                 write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
-                                 ctx->parse_lattice_param(cell, param.first, fnd_word->second, 0).as_int64(),
+                                 ctx->parse_lattice_param_from_cell(cell, param.first, fnd_word->second, 0).as_int64(),
                                  fnd_word->second);
             } else {
                 write_bit(stringf("%s.%s", name.c_str(), param.second.as_string().c_str()));
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 26da3dc5b0..4eccc6343a 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -32,13 +32,17 @@ namespace {
 bool is_enabled(CellInfo *ci, IdString prop) { return str_or_default(ci->params, prop, "") == "ENABLED"; }
 } // namespace
 
-// Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
-Property Arch::parse_lattice_param(const CellInfo *ci, IdString prop, int width, int64_t defval) const
+Property Arch::parse_lattice_param_from_cell(const CellInfo *ci, IdString prop, int width, int64_t defval) const
 {
     auto fnd = ci->params.find(prop);
     if (fnd == ci->params.end())
         return Property(defval, width);
-    const auto &val = fnd->second;
+    return this->parse_lattice_param(fnd->second, prop, width, nameOf(ci));
+}
+
+// Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
+Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char* ci) const
+{
     if (val.is_string) {
         const std::string &s = val.str;
         Property temp;
@@ -47,7 +51,7 @@ Property Arch::parse_lattice_param(const CellInfo *ci, IdString prop, int width,
             for (int i = int(s.length()) - 1; i >= 2; i--) {
                 char c = s.at(i);
                 if (c != '0' && c != '1' && c != 'x')
-                    log_error("Invalid binary digit '%c' in property %s.%s\n", c, nameOf(ci), nameOf(prop));
+                    log_error("Invalid binary digit '%c' in property %s.%s\n", c, ci, nameOf(prop));
                 temp.str.push_back(c);
             }
         } else if (boost::starts_with(s, "0x")) {
@@ -61,7 +65,7 @@ Property Arch::parse_lattice_param(const CellInfo *ci, IdString prop, int width,
                 else if (c >= 'A' && c <= 'F')
                     nibble = (c - 'A') + 10;
                 else
-                    log_error("Invalid hex digit '%c' in property %s.%s\n", c, nameOf(ci), nameOf(prop));
+                    log_error("Invalid hex digit '%c' in property %s.%s\n", c, ci, nameOf(prop));
                 for (int j = 0; j < 4; j++)
                     temp.str.push_back(((nibble >> j) & 0x1) ? Property::S1 : Property::S0);
             }
@@ -73,14 +77,14 @@ Property Arch::parse_lattice_param(const CellInfo *ci, IdString prop, int width,
                 else
                     ival = std::stoll(s);
             } catch (std::runtime_error &e) {
-                log_error("Invalid decimal value for property %s.%s", nameOf(ci), nameOf(prop));
+                log_error("Invalid decimal value for property %s.%s", ci, nameOf(prop));
             }
             temp = Property(ival);
         }
 
         for (auto b : temp.str.substr(width)) {
             if (b == Property::S1)
-                log_error("Found value for property %s.%s with width greater than %d\n", nameOf(ci), nameOf(prop),
+                log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop),
                           width);
         }
         temp.update_intval();
@@ -90,7 +94,7 @@ Property Arch::parse_lattice_param(const CellInfo *ci, IdString prop, int width,
             if (b == Property::S1)
                 log_error("Found bitvector value for property %s.%s with width greater than %d - perhaps a string was "
                           "converted to bits?\n",
-                          nameOf(ci), nameOf(prop), width);
+                          ci, nameOf(prop), width);
         }
         return val.extract(0, width);
     }
@@ -170,7 +174,7 @@ struct NexusPacker
             int64_t def;
             for (const auto &p : rule.parse_params) {
                 std::tie(old_param, new_param, width, def) = p;
-                ci->params[new_param] = ctx->parse_lattice_param(ci, old_param, width, def);
+                ci->params[new_param] = ctx->parse_lattice_param_from_cell(ci, old_param, width, def);
             }
         }
 
@@ -953,7 +957,7 @@ struct NexusPacker
             ramw->connectPort(id_WCKO, int_wck);
             ramw->connectPort(id_WREO, int_wre);
 
-            uint64_t initval = ctx->parse_lattice_param(ci, id_INITVAL, 64, 0).as_int64();
+            uint64_t initval = ctx->parse_lattice_param_from_cell(ci, id_INITVAL, 64, 0).as_int64();
 
             // Rewiring - buses
             for (int i = 0; i < 4; i++) {
@@ -1272,8 +1276,8 @@ struct NexusPacker
             combs[1]->connectPort(id_F, f1);
             combs[0]->connectPort(id_F1, f1);
 
-            combs[0]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT0, 16, 0);
-            combs[1]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT1, 16, 0);
+            combs[0]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT0, 16, 0);
+            combs[1]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT1, 16, 0);
 
             combs[1]->cluster = combs[0]->name;
             combs[1]->constr_x = 0;
@@ -1329,8 +1333,8 @@ struct NexusPacker
                 // Copy parameters
                 if (ci->params.count(id_INJECT))
                     combs[0]->params[id_INJECT] = ci->params[id_INJECT];
-                combs[0]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT0, 16, 0);
-                combs[1]->params[id_INIT] = ctx->parse_lattice_param(ci, id_INIT1, 16, 0);
+                combs[0]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT0, 16, 0);
+                combs[1]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT1, 16, 0);
 
                 // Internal carry net between the two split COMB cells
                 NetInfo *int_cy = ctx->createNet(ctx->id(stringf("%s$widefn_int_cy$", ctx->nameOf(ci))));
@@ -2026,9 +2030,9 @@ struct NexusPacker
                     log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
                              MHz(period_in));
 
-                    int input_div = ctx->parse_lattice_param(ci, id_REF_MMD_DIG, 8, 1).as_int64();
+                    int input_div = ctx->parse_lattice_param_from_cell(ci, id_REF_MMD_DIG, 8, 1).as_int64();
                     period_in *= input_div;
-                    int feedback_div = ctx->parse_lattice_param(ci, id_REF_MMD_DIG, 8, 1).as_int64();
+                    int feedback_div = ctx->parse_lattice_param_from_cell(ci, id_REF_MMD_DIG, 8, 1).as_int64();
                     bool found_fbk = false;
                     std::string clkmux_fb = str_or_default(ci->params, id_CLKMUX_FB, "CMUX_CLKOP");
                     for (int i = 0; i < 6; i++) {
@@ -2036,7 +2040,7 @@ struct NexusPacker
                         if (clkmux_fb != stringf("CMUX_%s", output[i].c_str(ctx)))
                             continue;
                         // Multiply feedback output divider with
-                        feedback_div *= (ctx->parse_lattice_param(ci, div[i], 7, 0).as_int64() + 1);
+                        feedback_div *= (ctx->parse_lattice_param_from_cell(ci, div[i], 7, 0).as_int64() + 1);
                         found_fbk = true;
                     }
                     if (!found_fbk) {
@@ -2050,7 +2054,7 @@ struct NexusPacker
                              MHz(vco_period));
                     for (int i = 0; i < 6; i++) {
                         set_period(ci, output[i],
-                                   (ctx->parse_lattice_param(ci, div[i], 7, 0).as_int64() + 1) * vco_period);
+                                   (ctx->parse_lattice_param_from_cell(ci, div[i], 7, 0).as_int64() + 1) * vco_period);
                     }
                 }
             }

From 601b32948b8c8e79bf1ac394ce2f42f5d3d9fce9 Mon Sep 17 00:00:00 2001
From: Tim Pambor <tp@osasysteme.de>
Date: Wed, 30 Mar 2022 17:35:16 +0200
Subject: [PATCH 123/712] gowin: Fix z-index of oscillator

---
 gowin/arch.cc | 8 ++++----
 gowin/arch.h  | 3 ++-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 2c1e50b740..89bdade349 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1012,7 +1012,7 @@ Arch::Arch(ArchArgs args) : args(args)
             case ID_OSC:
                 snprintf(buf, 32, "R%dC%d_OSC", row + 1, col + 1);
                 belname = id(buf);
-                addBel(belname, id_OSC, Loc(col, row, 0), false);
+                addBel(belname, id_OSC, Loc(col, row, BelZ::osc_z), false);
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelOutput(belname, id_OSCOUT, id(buf));
@@ -1020,7 +1020,7 @@ Arch::Arch(ArchArgs args) : args(args)
             case ID_OSCH:
                 snprintf(buf, 32, "R%dC%d_OSCH", row + 1, col + 1);
                 belname = id(buf);
-                addBel(belname, id_OSCH, Loc(col, row, 0), false);
+                addBel(belname, id_OSCH, Loc(col, row, BelZ::osc_z), false);
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelOutput(belname, id_OSCOUT, id(buf));
@@ -1028,7 +1028,7 @@ Arch::Arch(ArchArgs args) : args(args)
             case ID_OSCF:
                 snprintf(buf, 32, "R%dC%d_OSCF", row + 1, col + 1);
                 belname = id(buf);
-                addBel(belname, id_OSCF, Loc(col, row, 0), false);
+                addBel(belname, id_OSCF, Loc(col, row, BelZ::osc_z), false);
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelOutput(belname, id_OSCOUT, id(buf));
@@ -1039,7 +1039,7 @@ Arch::Arch(ArchArgs args) : args(args)
             case ID_OSCZ:
                 snprintf(buf, 32, "R%dC%d_OSCZ", row + 1, col + 1);
                 belname = id(buf);
-                addBel(belname, id_OSCZ, Loc(col, row, 0), false);
+                addBel(belname, id_OSCZ, Loc(col, row, BelZ::osc_z), false);
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelOutput(belname, id_OSCOUT, id(buf));
diff --git a/gowin/arch.h b/gowin/arch.h
index bc29a59bf9..c5804bc44b 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -484,7 +484,8 @@ enum
     mux_0_z = 10,     // start Z for the MUX2LUT5 bels
     iologic_0_z = 20, // start Z for the IOLOGIC bels
     vcc_0_z = 277,    // virtual VCC bel Z
-    gnd_0_z = 278     // virtual VSS bel Z
+    gnd_0_z = 278,    // virtual VSS bel Z
+    osc_z = 280       // Z for the oscillator bels
 };
 }
 

From 336124b879495ca4b5ac3aad23c069eafb5231dd Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 30 Mar 2022 20:57:00 +0100
Subject: [PATCH 124/712] ice40: Fix wirenames containing / which is the list
 separator

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/chipdb.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index cc3397eb67..accafbcf47 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -1312,7 +1312,7 @@ def pop(self):
 
 bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
 for wire, info in enumerate(wireinfo):
-    bba.s(info["name"], "name")
+    bba.s(info["name"].replace('/', ':'), "name") # / is used as an IdStringList separator; can't also be within name
     bba.u8(info["name_x"], "name_x")
     bba.u8(info["name_y"], "name_y")
     bba.u16(0, "padding")

From 2ed68a21db9d04e5688c4c0784b0817f3485926e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 31 Mar 2022 10:49:00 +0100
Subject: [PATCH 125/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.h  |  2 +-
 nexus/fasm.cc | 17 +++++++++--------
 nexus/pack.cc |  5 ++---
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/nexus/arch.h b/nexus/arch.h
index 323dcacdc7..d713afcfe4 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1409,7 +1409,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
     Property parse_lattice_param_from_cell(const CellInfo *ci, IdString prop, int width, int64_t defval) const;
-    Property parse_lattice_param(const Property &val, IdString prop, int width, const char* ci="") const;
+    Property parse_lattice_param(const Property &val, IdString prop, int width, const char *ci = "") const;
 
     // -------------------------------------------------
 
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index a6e94d73a7..3ed5785eab 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -523,7 +523,8 @@ struct NexusFasmWriter
         write_enum(cell, "LF_OUTPUT_EN");
         write_enum(cell, "DTR_EN", "ENABLED");
         write_enum(cell, "DEBUG_N", "DISABLED");
-        write_int_vector(stringf("HF_CLK_DIV[7:0]"), ctx->parse_lattice_param_from_cell(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
+        write_int_vector(stringf("HF_CLK_DIV[7:0]"),
+                         ctx->parse_lattice_param_from_cell(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
         write_int_vector(stringf("HF_SED_SEC_DIV[7:0]"), 1, 8);
         write_cell_muxes(cell);
         pop(2);
@@ -812,9 +813,10 @@ struct NexusFasmWriter
     };
     /* clang-format on */
 
-    static bool is_number(std::string s) {
-        for (auto c  : s) {
-            if(!isdigit(c))
+    static bool is_number(std::string s)
+    {
+        for (auto c : s) {
+            if (!isdigit(c))
                 return false;
         }
         return true;
@@ -844,12 +846,11 @@ struct NexusFasmWriter
             if (fnd_word != pll_word_params.end()) {
                 if (cell->params.count(n)) {
                     write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
-                                    ctx->parse_lattice_param_from_cell(cell, n, fnd_word->second, 0).as_int64(),
-                                    fnd_word->second);
+                                     ctx->parse_lattice_param_from_cell(cell, n, fnd_word->second, 0).as_int64(),
+                                     fnd_word->second);
                 } else {
                     write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
-                                    ctx->parse_lattice_param(temp, n, fnd_word->second).as_int64(),
-                                    fnd_word->second);
+                                     ctx->parse_lattice_param(temp, n, fnd_word->second).as_int64(), fnd_word->second);
                 }
             } else {
                 if (cell->params.count(n)) {
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 4eccc6343a..0870bf4066 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -41,7 +41,7 @@ Property Arch::parse_lattice_param_from_cell(const CellInfo *ci, IdString prop,
 }
 
 // Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
-Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char* ci) const
+Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char *ci) const
 {
     if (val.is_string) {
         const std::string &s = val.str;
@@ -84,8 +84,7 @@ Property Arch::parse_lattice_param(const Property &val, IdString prop, int width
 
         for (auto b : temp.str.substr(width)) {
             if (b == Property::S1)
-                log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop),
-                          width);
+                log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop), width);
         }
         temp.update_intval();
         return temp.extract(0, width);

From 85e8570a73dce11d3cfd2ce82a3b6c47214758af Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 3 Apr 2022 10:05:27 +1000
Subject: [PATCH 126/712] gowin: handle the GW1N-9 feature.

This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 19 +++++++++++++++++--
 gowin/arch.h       |  2 ++
 gowin/constids.inc |  2 ++
 gowin/pack.cc      | 19 +++++++++++++++++++
 4 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 89bdade349..7bfef36e8e 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1119,7 +1119,7 @@ Arch::Arch(ArchArgs args) : args(args)
                 z++; /* fall-through*/
             case ID_IOBB:
                 z++; /* fall-through*/
-            case ID_IOBA:
+            case ID_IOBA: {
                 snprintf(buf, 32, "R%dC%d_IOB%c", row + 1, col + 1, 'A' + z);
                 belname = id(buf);
                 addBel(belname, id_IOB, Loc(col, row, z), false);
@@ -1132,7 +1132,22 @@ Arch::Arch(ArchArgs args) : args(args)
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OE)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OEN, id(buf));
-                break;
+                // GW1NR-9 quirk
+                const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS0);
+                if (xxx_port != nullptr) {
+                    gw1n9_quirk = true;
+                    portname = IdString(xxx_port->src_id);
+                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    addBelInput(belname, id_XXX_VSS0, id(buf));
+                }
+                xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS1);
+                if (xxx_port != nullptr) {
+                    gw1n9_quirk = true;
+                    portname = IdString(xxx_port->src_id);
+                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    addBelInput(belname, id_XXX_VSS1, id(buf));
+                }
+            } break;
                 // Simplified IO
             case ID_IOBJS:
                 z++; /* fall-through*/
diff --git a/gowin/arch.h b/gowin/arch.h
index c5804bc44b..14181d793b 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -472,6 +472,8 @@ struct Arch : BaseArch<ArchRanges>
 
     // XXX GW1N-9C DDR quirk
     bool ddr_has_extra_inputs = false;
+    // XXX GW1NR-9 iobuf quirk
+    bool gw1n9_quirk = false;
 
     // Permissible combinations of modes in a single slice
     std::map<const IdString, IdString> dff_comp_mode;
diff --git a/gowin/constids.inc b/gowin/constids.inc
index d2a6b171de..3691c50606 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -683,6 +683,8 @@ X(IOBJS)
 X(TX)
 X(XXX_VSS)
 X(XXX_VCC)
+X(XXX_VSS0)
+X(XXX_VSS1)
 X(OBUF_TYPE)
 X(SBUF)
 X(DBUF)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 28370a7557..4adfec1aa2 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -805,6 +805,14 @@ static void pack_iologic(Context *ctx)
                     ci->addInput(id_XXX_VCC);
                     ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 }
+                if (ctx->gw1n9_quirk && iob_bel != q0_dst->attrs.end()) {
+                    bool have_XXX_VSS0 =
+                            ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_VSS0);
+                    if (have_XXX_VSS0) {
+                        q0_dst->disconnectPort(id_XXX_VSS0);
+                        q0_dst->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    }
+                }
             } break;
             default:
                 break;
@@ -933,6 +941,7 @@ static void pack_io(Context *ctx)
             // what type to create
             IdString new_cell_type = id_IOB;
             std::string constr_bel_name = std::string("");
+            bool have_xxx_port = false;
             // check whether the given IO is limited to simplified IO cells
             auto constr_bel = ci->attrs.find(id_BEL);
             if (constr_bel != ci->attrs.end()) {
@@ -946,6 +955,9 @@ static void pack_io(Context *ctx)
                 BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
                 if (constr_bel != BelId()) {
                     new_cell_type = ctx->bels[constr_bel].type;
+                    if (ctx->gw1n9_quirk) {
+                        have_xxx_port = ctx->bels[constr_bel].pins.count(id_XXX_VSS0) != 0;
+                    }
                 }
             }
 
@@ -954,6 +966,13 @@ static void pack_io(Context *ctx)
             gwio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
             new_cells.push_back(std::move(ice_cell));
             auto gwiob = new_cells.back().get();
+            // XXX GW1NR-9 quirks
+            if (have_xxx_port && ci->type != id_IBUF) {
+                gwiob->addInput(id_XXX_VSS0);
+                gwiob->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_XXX_VSS1);
+                gwiob->connectPort(id_XXX_VSS1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+            }
 
             packed_cells.insert(ci->name);
             if (iob != nullptr) {

From c4e47ba1a85d840c31d4be5c3f2c032664abd814 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 4 Apr 2022 19:49:44 +0100
Subject: [PATCH 127/712] generic: Allow bel pins without wires

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/generic/arch.cc b/generic/arch.cc
index c4814bab0b..0aece64fe0 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -119,7 +119,8 @@ void Arch::addBelInput(BelId bel, IdString name, WireId wire)
     pi.wire = wire;
     pi.type = PORT_IN;
 
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
+    if (wire != WireId())
+        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
@@ -131,7 +132,8 @@ void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
     pi.wire = wire;
     pi.type = PORT_OUT;
 
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
+    if (wire != WireId())
+        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addBelInout(BelId bel, IdString name, WireId wire)
@@ -143,7 +145,8 @@ void Arch::addBelInout(BelId bel, IdString name, WireId wire)
     pi.wire = wire;
     pi.type = PORT_INOUT;
 
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
+    if (wire != WireId())
+        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addGroupBel(IdStringList group, BelId bel) { groups[group].bels.push_back(bel); }

From 03074cdbc242a06c861a703ad76365b4dca7cb4a Mon Sep 17 00:00:00 2001
From: Irides <irides@irides.network>
Date: Tue, 5 Apr 2022 10:12:44 -0500
Subject: [PATCH 128/712] cmake: properly include TBB libraries.

---
 CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 78c1caa1d1..fcbbbb13fe 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -257,7 +257,7 @@ if(PROFILER)
     list(APPEND EXTRA_LIB_DEPS profiler)
 endif()
 if(TBB_FOUND)
-    list(APPEND EXTRA_LIB_DEPS tbb)
+    list(APPEND EXTRA_LIB_DEPS TBB::tbb)
 endif()
 
 foreach (family ${ARCH})

From efb58711b0dfcdb8080f63bd64d3f9d9fafd2637 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 31 Mar 2022 11:17:57 +0100
Subject: [PATCH 129/712] ecp5: Split the SLICE bel into separate LUT/FF/RAMW
 bels

---
 .cirrus/Dockerfile.ubuntu20.04 |    2 +-
 ecp5/arch.cc                   |  147 ++--
 ecp5/arch.h                    |  107 ++-
 ecp5/arch_place.cc             |  237 +++---
 ecp5/archdefs.h                |   41 +-
 ecp5/bitstream.cc              |  115 ++-
 ecp5/cells.cc                  |  318 +++-----
 ecp5/cells.h                   |   11 +-
 ecp5/constids.inc              |   10 +
 ecp5/gfx.cc                    |   26 +-
 ecp5/globals.cc                |    8 +-
 ecp5/pack.cc                   | 1401 ++++++++++++--------------------
 ecp5/trellis_import.py         |   63 +-
 13 files changed, 1137 insertions(+), 1349 deletions(-)

diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
index 6561ed59a0..35ea18bd9a 100644
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ b/.cirrus/Dockerfile.ubuntu20.04
@@ -48,7 +48,7 @@ RUN set -e -x ;\
     cd /usr/local/src ;\
     git clone --recursive https://github.com/YosysHQ/prjtrellis.git ;\
     cd prjtrellis ;\
-    git reset --hard 7239331d5463321d4864164f320beef67310f1e5 ;\
+    git reset --hard 26f917d6052e084df30211ae3a78c8a165121e09 ;\
     cd libtrellis ;\
     cmake . ;\
     make -j $(nproc) ;\
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 3d20badb22..50993e2b97 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -103,7 +103,19 @@ Arch::Arch(ArchArgs args) : args(args)
     if (!package_info)
         log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
 
-    bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr);
+    tile_status.resize(chip_info->num_tiles);
+    for (int i = 0; i < chip_info->num_tiles; i++) {
+        auto &ts = tile_status.at(i);
+        auto &tile_data = chip_info->tile_info[i];
+        ts.boundcells.resize(chip_info->locations[chip_info->location_type[i]].bel_data.size(), nullptr);
+        for (auto &name : tile_data.tile_names) {
+            if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) {
+                // Is a logic tile
+                ts.lts = new LogicTileStatus();
+                break;
+            }
+        }
+    }
 
     BaseArch::init_cell_types();
     BaseArch::init_bel_buckets();
@@ -545,20 +557,24 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB)
+    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB ||
+        (src_pin == id_F && dst_pin == id_DI))
         return 0;
     auto driver_loc = getBelLocation(src_bel);
     auto sink_loc = getBelLocation(dst_bel);
     // Encourage use of direct interconnect
+    //   exact LUT input doesn't matter as they can be permuted by the router...
     if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
-        if ((dst_pin == id_A0 || dst_pin == id_A1) && (src_pin == id_F1) && (driver_loc.z == 2 || driver_loc.z == 3))
-            return 0;
-        if ((dst_pin == id_B0 || dst_pin == id_B1) && (src_pin == id_F1) && (driver_loc.z == 0 || driver_loc.z == 1))
-            return 0;
-        if ((dst_pin == id_C0 || dst_pin == id_C1) && (src_pin == id_F0) && (driver_loc.z == 2 || driver_loc.z == 3))
-            return 0;
-        if ((dst_pin == id_D0 || dst_pin == id_D1) && (src_pin == id_F0) && (driver_loc.z == 0 || driver_loc.z == 1))
-            return 0;
+        if (dst_pin.in(id_A, id_B, id_C, id_D) && src_pin == id_Q) {
+            int lut = (sink_loc.z >> lc_idx_shift), ff = (driver_loc.z >> lc_idx_shift);
+            if (lut == ff)
+                return 0;
+        }
+        if (dst_pin.in(id_A, id_B, id_C, id_D) && src_pin == id_F) {
+            int l0 = (driver_loc.z >> lc_idx_shift);
+            if (l0 != 1 && l0 != 6)
+                return 0;
+        }
     }
 
     int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
@@ -597,6 +613,14 @@ bool Arch::place()
         cfg.cellGroups.back().insert(id_MULT18X18D);
         cfg.cellGroups.back().insert(id_ALU54B);
 
+        cfg.cellGroups.emplace_back();
+        cfg.cellGroups.back().insert(id_TRELLIS_COMB);
+        cfg.cellGroups.back().insert(id_TRELLIS_FF);
+        cfg.cellGroups.back().insert(id_TRELLIS_RAMW);
+        cfg.placeAllAtOnce = true;
+
+        cfg.beta = 0.75;
+
         if (!placer_heap(getCtx(), cfg))
             return false;
     } else if (placer == "sa") {
@@ -605,7 +629,6 @@ bool Arch::place()
     } else {
         log_error("ECP5 architecture does not support placer '%s'\n", placer.c_str());
     }
-    permute_luts();
 
     // In out-of-context mode, create a locked macro
     if (bool_or_default(settings, id("arch.ooc")))
@@ -710,7 +733,7 @@ DecalXY Arch::getBelDecal(BelId bel) const
     decalxy.decal.type = DecalId::TYPE_BEL;
     decalxy.decal.location = bel.location;
     decalxy.decal.z = bel.index;
-    decalxy.decal.active = (bel_to_cell.at(get_bel_flat_index(bel)) != nullptr);
+    decalxy.decal.active = getBoundBelCell(bel) != nullptr;
     return decalxy;
 }
 
@@ -791,14 +814,19 @@ void Arch::get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString p
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
     // Data for -8 grade
-    if (cell->type == id_TRELLIS_SLICE) {
-        bool has_carry = cell->sliceInfo.is_carry;
-        if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 ||
-            fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 ||
-            fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) {
-            return get_delay_from_tmg_db(has_carry ? id_SCCU2C : id_SLOGICB, fromPort, toPort, delay);
-        }
-
+    if (cell->type == id_TRELLIS_COMB) {
+        bool has_carry = cell->combInfo.flags & ArchCellInfo::COMB_CARRY;
+        IdString tmg_type = has_carry ? (((cell->constr_z >> Arch::lc_idx_shift) % 2) ? id_TRELLIS_COMB_CARRY1
+                                                                                      : id_TRELLIS_COMB_CARRY0)
+                                      : id_TRELLIS_COMB;
+        if (fromPort == id_A || fromPort == id_B || fromPort == id_C || fromPort == id_D || fromPort == id_M ||
+            fromPort == id_F1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI)
+            return get_delay_from_tmg_db(tmg_type, fromPort, toPort, delay);
+        else
+            return false;
+    } else if (cell->type == id_TRELLIS_FF) {
+        return false;
+    } else if (cell->type == id_TRELLIS_RAMW) {
         if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
             (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
             (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
@@ -841,45 +869,46 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
 {
     auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
     clockInfoCount = 0;
-    if (cell->type == id_TRELLIS_SLICE) {
-        int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
-        if (port == id_CLK || port == id_WCK)
+    if (cell->type == id_TRELLIS_COMB) {
+        if (port == id_WCK)
             return TMG_CLOCK_INPUT;
-        if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
-            port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
+        if (port == id_A || port == id_B || port == id_C || port == id_D || port == id_FCI || port == id_FXA ||
+            port == id_FXB || port == id_F1)
             return TMG_COMB_INPUT;
-        if (port == id_F0 && disconnected(id_A0) && disconnected(id_B0) && disconnected(id_C0) && disconnected(id_D0) &&
+        if (port == id_F && disconnected(id_A) && disconnected(id_B) && disconnected(id_C) && disconnected(id_D) &&
             disconnected(id_FCI))
             return TMG_IGNORE; // LUT with no inputs is a constant
-        if (port == id_F1 && disconnected(id_A1) && disconnected(id_B1) && disconnected(id_C1) && disconnected(id_D1) &&
-            disconnected(id_FCI))
-            return TMG_IGNORE; // LUT with no inputs is a constant
-
-        if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
+        if (port == id_F || port == id_FCO || port == id_OFX)
             return TMG_COMB_OUTPUT;
-        if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
-            (sd1 == 0 && port == id_M1)) {
+        if (port == id_M)
+            return TMG_COMB_INPUT;
+        if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 ||
+            port == id_WRE) {
             clockInfoCount = 1;
             return TMG_REGISTER_INPUT;
         }
-        if (port == id_M0 || port == id_M1)
-            return TMG_COMB_INPUT;
-        if (port == id_Q0 || port == id_Q1) {
+        return TMG_IGNORE;
+    } else if (cell->type == id_TRELLIS_FF) {
+        bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        if (port == id_DI || (using_m && (port == id_M)) || port == id_CE || port == id_LSR) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        }
+        if (port == id_Q) {
             clockInfoCount = 1;
             return TMG_REGISTER_OUTPUT;
         }
-
+        return TMG_IGNORE;
+    } else if (cell->type == id_TRELLIS_RAMW) {
+        if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
+            port == id_D0 || port == id_D1)
+            return TMG_COMB_INPUT;
         if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 ||
             port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
             return TMG_COMB_OUTPUT;
-
-        if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
-            port == id_WAD3 || port == id_WRE) {
-            clockInfoCount = 1;
-            return TMG_REGISTER_INPUT;
-        }
-
-        NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'");
+        return TMG_IGNORE;
     } else if (cell->type == id_TRELLIS_IO) {
         if (port == id_T || port == id_I)
             return TMG_ENDPOINT;
@@ -1024,21 +1053,29 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     info.setup = DelayPair(0);
     info.hold = DelayPair(0);
     info.clockToQ = DelayQuad(0);
-    if (cell->type == id_TRELLIS_SLICE) {
-        int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
-        if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
-            port == id_WAD3 || port == id_WRE) {
-            info.edge = RISING_EDGE;
+    if (cell->type == id_TRELLIS_COMB) {
+        if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 ||
+            port == id_WRE) {
+            if (port == id_WD)
+                port = id_WD0;
+            info.edge = (cell->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV) ? FALLING_EDGE : RISING_EDGE;
             info.clock_port = id_WCK;
             get_setuphold_from_tmg_db(id_SDPRAME, id_WCK, port, info.setup, info.hold);
-        } else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
-                   (sd1 == 0 && port == id_M1)) {
-            info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
+        }
+    } else if (cell->type == id_TRELLIS_FF) {
+        bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
+        if (port == id_DI || port == id_CE || port == id_LSR || (using_m && port == id_M)) {
+            if (port == id_DI)
+                port = id_DI0;
+            if (port == id_M)
+                port = id_M0;
+            info.edge = (cell->ffInfo.flags & ArchCellInfo::FF_CLKINV) ? FALLING_EDGE : RISING_EDGE;
             info.clock_port = id_CLK;
             get_setuphold_from_tmg_db(id_SLOGICB, id_CLK, port, info.setup, info.hold);
-
         } else {
-            info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
+            NPNR_ASSERT(port == id_Q);
+            port = id_Q0;
+            info.edge = (cell->ffInfo.flags & ArchCellInfo::FF_CLKINV) ? FALLING_EDGE : RISING_EDGE;
             info.clock_port = id_CLK;
             bool is_path = get_delay_from_tmg_db(id_SLOGICB, id_CLK, port, info.clockToQ);
             NPNR_ASSERT(is_path);
diff --git a/ecp5/arch.h b/ecp5/arch.h
index c1bed2b361..3d95fc9b18 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -452,7 +452,6 @@ struct Arch : BaseArch<ArchRanges>
 
     mutable dict<IdStringList, PipId> pip_by_name;
 
-    std::vector<CellInfo *> bel_to_cell;
     enum class LutPermRule
     {
         NONE,
@@ -462,6 +461,39 @@ struct Arch : BaseArch<ArchRanges>
     std::vector<LutPermRule> lutperm_allowed;
     bool disable_router_lutperm = false;
 
+    // For fast, incremental validity checking of split SLICE
+
+    // BEL z-position lookup, x-ored with (index in tile) << 2
+    enum LogicBELType
+    {
+        BEL_COMB = 0,
+        BEL_FF = 1,
+        BEL_RAMW = 2
+    };
+    static const int lc_idx_shift = 2;
+
+    struct LogicTileStatus
+    {
+        // Per-SLICE valid and dirty bits
+        struct SliceStatus
+        {
+            bool valid = true, dirty = true;
+        } slices[4];
+        // Per-tile legality check for control set legality
+        bool tile_valid = true;
+        bool tile_dirty = true;
+        // Fast index from z-pos to cell
+        std::array<CellInfo *, 8 * (1 << lc_idx_shift)> cells;
+    };
+
+    struct TileStatus
+    {
+        std::vector<CellInfo *> boundcells;
+        LogicTileStatus *lts = nullptr;
+        // TODO: use similar mechanism for DSP legality checking
+        ~TileStatus() { delete lts; }
+    };
+
     // faster replacements for base_pip2net, base_wire2net
     // indexed by get_pip_vecidx()
     std::vector<NetInfo *> pip2net;
@@ -492,7 +524,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
 
-    static const int max_loc_bels = 20;
+    static const int max_loc_bels = 32;
 
     int getGridDimX() const override { return chip_info->width; };
     int getGridDimY() const override { return chip_info->height; };
@@ -509,6 +541,11 @@ struct Arch : BaseArch<ArchRanges>
         return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]);
     }
 
+    template <typename Id> inline int tile_index(Id id) const
+    {
+        return id.location.y * chip_info->width + id.location.x;
+    }
+
     IdStringList getBelName(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
@@ -519,41 +556,57 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getBelChecksum(BelId bel) const override { return bel.index; }
 
-    int get_bel_flat_index(BelId bel) const
-    {
-        return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
-    }
-
     int get_slice_index(int x, int y, int slice) const
     {
         NPNR_ASSERT(slice >= 0 && slice < 4);
         return (y * chip_info->width + x) * 4 + slice;
     }
 
+    void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
+    {
+        CellInfo *act_cell = (old_cell == nullptr) ? new_cell : old_cell;
+        if (act_cell->type == id_TRELLIS_FF || act_cell->type == id_TRELLIS_COMB || act_cell->type == id_TRELLIS_RAMW) {
+            LogicTileStatus *lts = tile_status.at(tile_index(bel)).lts;
+            NPNR_ASSERT(lts != nullptr);
+            int z = loc_info(bel)->bel_data[bel.index].z;
+            lts->slices[(z >> lc_idx_shift) / 2].dirty = true;
+            if (act_cell->type == id_TRELLIS_FF)
+                lts->tile_dirty = true; // because FF CLK/LSR signals are tile-wide
+            if (act_cell->type == id_TRELLIS_COMB && (act_cell->combInfo.flags & ArchCellInfo::COMB_LUTRAM))
+                lts->tile_dirty = true; // because RAM shares CLK/LSR signals with FFs
+            lts->cells[z] = new_cell;
+        }
+    }
+
     void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
     {
         NPNR_ASSERT(bel != BelId());
-        int idx = get_bel_flat_index(bel);
-        NPNR_ASSERT(bel_to_cell.at(idx) == nullptr);
-        bel_to_cell[idx] = cell;
+        auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        NPNR_ASSERT(slot == nullptr);
+        slot = cell;
         cell->bel = bel;
         cell->belStrength = strength;
-        if (getBelType(bel) == id_TRELLIS_SLICE) {
-            lutperm_allowed.at(get_slice_index(bel.location.x, bel.location.y, getBelLocation(bel).z)) =
-                    (cell->sliceInfo.is_memory ? LutPermRule::NONE
-                                               : (cell->sliceInfo.is_carry ? LutPermRule::CARRY : LutPermRule::ALL));
+        if (getBelType(bel) == id_TRELLIS_COMB) {
+            int flags = cell->combInfo.flags;
+            lutperm_allowed.at(
+                    get_slice_index(bel.location.x, bel.location.y, (getBelLocation(bel).z >> lc_idx_shift) / 2)) =
+                    (((flags & ArchCellInfo::COMB_LUTRAM) || (flags & ArchCellInfo::COMB_RAMW_BLOCK))
+                             ? LutPermRule::NONE
+                             : ((flags & ArchCellInfo::COMB_CARRY) ? LutPermRule::CARRY : LutPermRule::ALL));
         }
+        update_bel(bel, nullptr, cell);
         refreshUiBel(bel);
     }
 
     void unbindBel(BelId bel) override
     {
         NPNR_ASSERT(bel != BelId());
-        int idx = get_bel_flat_index(bel);
-        NPNR_ASSERT(bel_to_cell.at(idx) != nullptr);
-        bel_to_cell[idx]->bel = BelId();
-        bel_to_cell[idx]->belStrength = STRENGTH_NONE;
-        bel_to_cell[idx] = nullptr;
+        auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        NPNR_ASSERT(slot != nullptr);
+        update_bel(bel, slot, nullptr);
+        slot->bel = BelId();
+        slot->belStrength = STRENGTH_NONE;
+        slot = nullptr;
         refreshUiBel(bel);
     }
 
@@ -574,19 +627,22 @@ struct Arch : BaseArch<ArchRanges>
     bool checkBelAvail(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
-        return bel_to_cell[get_bel_flat_index(bel)] == nullptr;
+        const CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot == nullptr;
     }
 
     CellInfo *getBoundBelCell(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
-        return bel_to_cell[get_bel_flat_index(bel)];
+        CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot;
     }
 
     CellInfo *getConflictingBelCell(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
-        return bel_to_cell[get_bel_flat_index(bel)];
+        CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot;
     }
 
     BelRange getBels() const override
@@ -957,12 +1013,11 @@ struct Arch : BaseArch<ArchRanges>
     bool isBelLocationValid(BelId bel) const override;
 
     // Helper function for above
-    bool slices_compatible(const std::vector<const CellInfo *> &cells) const;
+    bool slices_compatible(LogicTileStatus *lts) const;
 
+    void assign_arch_info_for_cell(CellInfo *ci);
     void assignArchInfo() override;
 
-    void permute_luts();
-
     std::vector<std::pair<std::string, std::string>> get_tiles_at_loc(int row, int col);
     std::string get_tile_by_type_loc(int row, int col, std::string type) const
     {
@@ -1028,6 +1083,8 @@ struct Arch : BaseArch<ArchRanges>
 
     std::vector<IdString> cell_types;
     std::vector<BelBucketId> buckets;
+
+    mutable std::vector<TileStatus> tile_status;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index b1849ee672..afe9aca0d7 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -33,53 +33,156 @@ inline NetInfo *port_or_nullptr(const CellInfo *cell, IdString name)
     return found->second.net;
 }
 
-bool Arch::slices_compatible(const std::vector<const CellInfo *> &cells) const
+bool Arch::slices_compatible(LogicTileStatus *lts) const
 {
-    // TODO: allow different LSR/CLK and MUX/SRMODE settings once
-    // routing details are worked out
-    IdString clk_sig, lsr_sig;
-    IdString CLKMUX, LSRMUX, SRMODE;
-    bool first = true;
-    for (auto cell : cells) {
-        if (cell->sliceInfo.using_dff) {
-            if (first) {
-                clk_sig = cell->sliceInfo.clk_sig;
-                lsr_sig = cell->sliceInfo.lsr_sig;
-                CLKMUX = cell->sliceInfo.clkmux;
-                LSRMUX = cell->sliceInfo.lsrmux;
-                SRMODE = cell->sliceInfo.srmode;
-            } else {
-                if (cell->sliceInfo.clk_sig != clk_sig)
-                    return false;
-                if (cell->sliceInfo.lsr_sig != lsr_sig)
-                    return false;
-                if (cell->sliceInfo.clkmux != CLKMUX)
+    if (lts == nullptr)
+        return true;
+    for (int sl = 0; sl < 4; sl++) {
+        if (!lts->slices[sl].dirty) {
+            if (!lts->slices[sl].valid)
+                return false;
+            continue;
+        }
+        lts->slices[sl].dirty = false;
+        lts->slices[sl].valid = false;
+        bool found_ff = false;
+        uint8_t last_ff_flags = 0;
+        IdString last_ce_sig;
+        bool ramw_used = false;
+        if (sl == 2 && lts->cells[((sl * 2) << lc_idx_shift) | BEL_RAMW] != nullptr)
+            ramw_used = true;
+        for (int l = 0; l < 2; l++) {
+            bool comb_m_used = false;
+            CellInfo *comb = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_COMB];
+            if (comb != nullptr) {
+                uint8_t flags = comb->combInfo.flags;
+                if (ramw_used && !(flags & ArchCellInfo::COMB_RAMW_BLOCK))
                     return false;
-                if (cell->sliceInfo.lsrmux != LSRMUX)
+                if (flags & ArchCellInfo::COMB_MUX5) {
+                    // MUX5 uses M signal and must be in LC 0
+                    comb_m_used = true;
+                    if (l != 0)
+                        return false;
+                }
+                if (flags & ArchCellInfo::COMB_MUX6) {
+                    // MUX6+ uses M signal and must be in LC 1
+                    comb_m_used = true;
+                    if (l != 1)
+                        return false;
+                    if (comb->combInfo.mux_fxad != nullptr &&
+                        (comb->combInfo.mux_fxad->combInfo.flags & ArchCellInfo::COMB_MUX5)) {
+                        // LUT6 structure must be rooted at SLICE 0 or 2
+                        if (sl != 0 && sl != 2)
+                            return false;
+                    }
+                }
+                // LUTRAM must be in bottom two SLICEs only
+                if ((flags & ArchCellInfo::COMB_LUTRAM) && (sl > 1))
                     return false;
-                if (cell->sliceInfo.srmode != SRMODE)
+                if (l == 1) {
+                    // Carry usage must be the same for LCs 0 and 1 in a SLICE
+                    CellInfo *comb0 = lts->cells[((sl * 2 + 0) << lc_idx_shift) | BEL_COMB];
+                    if (comb0 &&
+                        ((comb0->combInfo.flags & ArchCellInfo::COMB_CARRY) != (flags & ArchCellInfo::COMB_CARRY)))
+                        return false;
+                }
+            }
+
+            CellInfo *ff = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                uint8_t flags = ff->ffInfo.flags;
+                if (comb_m_used && (flags & ArchCellInfo::FF_M_USED))
                     return false;
+                if (found_ff) {
+                    if ((flags & ArchCellInfo::FF_GSREN) != (last_ff_flags & ArchCellInfo::FF_GSREN))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CECONST) != (last_ff_flags & ArchCellInfo::FF_CECONST))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CEINV) != (last_ff_flags & ArchCellInfo::FF_CEINV))
+                        return false;
+                    if (ff->ffInfo.ce_sig != last_ce_sig)
+                        return false;
+                } else {
+                    found_ff = true;
+                    last_ff_flags = flags;
+                    last_ce_sig = ff->ffInfo.ce_sig;
+                }
+            }
+        }
+
+        lts->slices[sl].valid = true;
+    }
+    if (lts->tile_dirty) {
+        bool found_global_ff = false;
+        bool found_global_dpram = false;
+        bool global_lsrinv = false;
+        bool global_clkinv = false;
+        bool global_async = false;
+
+        IdString clk_sig, lsr_sig;
+
+        lts->tile_dirty = false;
+        lts->tile_valid = false;
+
+#define CHECK_EQUAL(x, y)                                                                                              \
+    do {                                                                                                               \
+        if ((x) != (y))                                                                                                \
+            return false;                                                                                              \
+    } while (0)
+        for (int i = 0; i < 8; i++) {
+            if (i < 4) {
+                // DPRAM
+                CellInfo *comb = lts->cells[(i << lc_idx_shift) | BEL_COMB];
+                if (comb != nullptr && (comb->combInfo.flags & ArchCellInfo::COMB_LUTRAM)) {
+                    if (found_global_dpram) {
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV), global_clkinv);
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV), global_lsrinv);
+                    } else {
+                        global_clkinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV);
+                        global_lsrinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV);
+                        found_global_dpram = true;
+                    }
+                }
+            }
+            // FF
+            CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                if (found_global_dpram) {
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                }
+                if (found_global_ff) {
+                    CHECK_EQUAL(ff->ffInfo.clk_sig, clk_sig);
+                    CHECK_EQUAL(ff->ffInfo.lsr_sig, lsr_sig);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC), global_async);
+
+                } else {
+                    clk_sig = ff->ffInfo.clk_sig;
+                    lsr_sig = ff->ffInfo.lsr_sig;
+                    global_clkinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV);
+                    global_lsrinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV);
+                    global_async = bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC);
+                    found_global_ff = true;
+                }
             }
-            first = false;
         }
+#undef CHECK_EQUAL
+        lts->tile_valid = true;
+    } else {
+        if (!lts->tile_valid)
+            return false;
     }
+
     return true;
 }
 
 bool Arch::isBelLocationValid(BelId bel) const
 {
-    if (getBelType(bel) == id_TRELLIS_SLICE) {
-        std::vector<const CellInfo *> bel_cells;
-        Loc bel_loc = getBelLocation(bel);
-        for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
-            CellInfo *cell_other = getBoundBelCell(bel_other);
-            if (cell_other != nullptr) {
-                bel_cells.push_back(cell_other);
-            }
-        }
-        if (getBoundBelCell(bel) != nullptr && getBoundBelCell(bel)->sliceInfo.has_l6mux && ((bel_loc.z % 2) == 1))
-            return false;
-        return slices_compatible(bel_cells);
+    IdString bel_type = getBelType(bel);
+    if (bel_type.in(id_TRELLIS_COMB, id_TRELLIS_FF, id_TRELLIS_RAMW)) {
+        return slices_compatible(tile_status.at(tile_index(bel)).lts);
     } else {
         CellInfo *cell = getBoundBelCell(bel);
         if (cell == nullptr) {
@@ -93,70 +196,6 @@ bool Arch::isBelLocationValid(BelId bel) const
     }
 }
 
-void Arch::permute_luts()
-{
-    TimingAnalyser tmg(getCtx());
-    tmg.setup();
-
-    auto proc_lut = [&](CellInfo *ci, int lut) {
-        std::vector<IdString> port_names;
-        for (int i = 0; i < 4; i++)
-            port_names.push_back(id(std::string("ABCD").substr(i, 1) + std::to_string(lut)));
-
-        std::vector<std::pair<float, int>> inputs;
-        std::vector<NetInfo *> orig_nets;
-
-        for (int i = 0; i < 4; i++) {
-            if (!ci->ports.count(port_names.at(i))) {
-                ci->ports[port_names.at(i)].name = port_names.at(i);
-                ci->ports[port_names.at(i)].type = PORT_IN;
-            }
-            auto &port = ci->ports.at(port_names.at(i));
-            float crit = (port.net == nullptr) ? 0 : tmg.get_criticality(CellPortKey(ci->name, port_names.at(i)));
-            orig_nets.push_back(port.net);
-            inputs.emplace_back(crit, i);
-        }
-        // Least critical first (A input is slowest)
-
-        // Avoid permuting locked LUTs (e.g. from an OOC submodule)
-        if (ci->belStrength <= STRENGTH_STRONG)
-            std::sort(inputs.begin(), inputs.end());
-        for (int i = 0; i < 4; i++) {
-            IdString p = port_names.at(i);
-            // log_info("%s %s %f\n", p.c_str(ctx), port_names.at(inputs.at(i).second).c_str(ctx), inputs.at(i).first);
-            ci->disconnectPort(p);
-            ci->ports.at(p).net = nullptr;
-            if (orig_nets.at(inputs.at(i).second) != nullptr) {
-                ci->connectPort(p, orig_nets.at(inputs.at(i).second));
-                ci->params[id(p.str(this) + "MUX")] = p.str(this);
-            } else {
-                ci->params[id(p.str(this) + "MUX")] = std::string("1");
-            }
-        }
-        // Rewrite function
-        int old_init = int_or_default(ci->params, id("LUT" + std::to_string(lut) + "_INITVAL"), 0);
-        int new_init = 0;
-        for (int i = 0; i < 16; i++) {
-            int old_index = 0;
-            for (int k = 0; k < 4; k++) {
-                if (i & (1 << k))
-                    old_index |= (1 << inputs.at(k).second);
-            }
-            if (old_init & (1 << old_index))
-                new_init |= (1 << i);
-        }
-        ci->params[id("LUT" + std::to_string(lut) + "_INITVAL")] = Property(new_init, 16);
-    };
-
-    for (auto &cell : cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id_MODE, "LOGIC") == "LOGIC") {
-            proc_lut(ci, 0);
-            proc_lut(ci, 1);
-        }
-    }
-}
-
 void Arch::setup_wire_locations()
 {
     wire_loc_overrides.clear();
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index dd260a3e87..b7d892c538 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -156,19 +156,46 @@ struct ArchNetInfo
 
 typedef IdString ClusterId;
 
+struct CellInfo;
 struct NetInfo;
 
 struct ArchCellInfo : BaseClusterInfo
 {
+    enum CombFlags : uint8_t
+    {
+        COMB_NONE = 0x00,
+        COMB_CARRY = 0x01,
+        COMB_LUTRAM = 0x02,
+        COMB_MUX5 = 0x04,
+        COMB_MUX6 = 0x08,
+        COMB_RAM_WCKINV = 0x10,
+        COMB_RAM_WREINV = 0x20,
+        COMB_RAMW_BLOCK = 0x40,
+    };
+
+    enum FFFlags : uint8_t
+    {
+        FF_NONE = 0x00,
+        FF_CLKINV = 0x01,
+        FF_CEINV = 0x02,
+        FF_CECONST = 0x04,
+        FF_LSRINV = 0x08,
+        FF_GSREN = 0x10,
+        FF_ASYNC = 0x20,
+        FF_M_USED = 0x40,
+    };
+
+    struct
+    {
+        uint8_t flags;
+        IdString ram_wck, ram_wre;
+        CellInfo *mux_fxad;
+    } combInfo;
     struct
     {
-        bool using_dff;
-        bool has_l6mux;
-        bool is_carry;
-        bool is_memory;
-        IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
-        int sd0, sd1;
-    } sliceInfo;
+        uint8_t flags;
+        IdString clk_sig, lsr_sig, ce_sig, di_sig;
+    } ffInfo;
     struct
     {
         bool is_pdp;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 40d843b965..3c01fe71d3 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -524,10 +524,10 @@ static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
     cc.tiles[tile].add_arc(sink, source);
 }
 
-static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, int k, unsigned orig_init)
+static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
 {
     std::array<std::vector<unsigned>, 4> phys_to_log;
-    const std::array<IdString, 4> ports{k ? id_A1 : id_A0, k ? id_B1 : id_B0, k ? id_C1 : id_C0, k ? id_D1 : id_D0};
+    const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
     for (unsigned i = 0; i < 4; i++) {
         WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
         for (PipId pip : ctx->getPipsUphill(pin_wire)) {
@@ -547,7 +547,7 @@ static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_p
     for (unsigned i = 0; i < 4; i++)
         if (!phys_to_log.at(i).empty())
             used_phys_pins.insert(ports.at(i));
-    if (cell->sliceInfo.is_carry) {
+    if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
         // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
         for (unsigned i = 0; i < 4; i++) {
             if (!phys_to_log.at(i).empty())
@@ -840,77 +840,72 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
         }
         BelId bel = ci->bel;
-        if (ci->type == id_TRELLIS_SLICE) {
+        if (ci->type == id_TRELLIS_COMB) {
             pool<IdString> used_phys_pins;
             std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
-            std::string slice = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
-            int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
-            cc.tiles[tname].add_word(slice + ".K0.INIT",
-                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 0, lut0_init), 16));
-            cc.tiles[tname].add_word(slice + ".K1.INIT",
-                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 1, lut1_init), 16));
-            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE", str_or_default(ci->params, id_REG0_LSRMODE, "LSR"));
-            cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE", str_or_default(ci->params, id_REG1_LSRMODE, "LSR"));
-            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
-
-            if (ci->sliceInfo.using_dff) {
-                NetInfo *lsrnet = nullptr;
-                if (ci->ports.find(id_LSR) != ci->ports.end() && ci->ports.at(id_LSR).net != nullptr)
-                    lsrnet = ci->ports.at(id_LSR).net;
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-                    cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                }
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-                    cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                }
-
-                NetInfo *clknet = nullptr;
-                if (ci->ports.find(id_CLK) != ci->ports.end() && ci->ports.at(id_CLK).net != nullptr)
-                    clknet = ci->ports.at(id_CLK).net;
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
-                }
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
-                }
-            }
-
-            if (str_or_default(ci->params, id_MODE, "LOGIC") == "CCU2") {
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
-                                         str_or_default(ci->params, id_CCU2_INJECT1_0, "YES"));
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
-                                         str_or_default(ci->params, id_CCU2_INJECT1_1, "YES"));
+            int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+            std::string lc = std::to_string(z % 2);
+            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+            if (mode == "RAMW_BLOCK")
+                continue;
+            int lut_init = int_or_default(ci->params, id_INITVAL);
+            cc.tiles[tname].add_enum(slice + ".MODE", mode);
+            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
+                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16));
+            if (mode == "CCU2") {
+                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc,
+                                         str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
             } else {
                 // Don't interfere with cascade mux wiring
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0", "_NONE_");
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1", "_NONE_");
+                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
             }
-
-            if (str_or_default(ci->params, id_MODE, "LOGIC") == "DPRAM" && slice == "SLICEA") {
+            if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
                 cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
-
                 std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
                 wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
                 cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
             }
-
-            // Tie unused inputs high
-            for (auto input : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1}) {
+            for (auto input : {id_A, id_B, id_C, id_D}) {
                 if (!used_phys_pins.count(input)) {
-                    cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + "MUX", "1");
+                    cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + lc + "MUX", "1");
                 }
             }
+        } else if (ci->type == id_TRELLIS_FF) {
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+            int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+            std::string lc = std::to_string(z % 2);
+
+            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".LSRMODE", str_or_default(ci->params, id_LSRMODE, "LSR"));
+
+            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+
+            NetInfo *lsrnet = ci->getPort(id_LSR);
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
+                cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+                cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+            }
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
+                cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+                cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+            }
 
-            // TODO: CLKMUX
+            NetInfo *clknet = ci->getPort(id_CLK);
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
+                cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
+            }
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
+                cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
+            }
+        } else if (ci->type == id_TRELLIS_RAMW) {
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+            cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
+            cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
+            cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
         } else if (ci->type == id_TRELLIS_IO) {
             std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
             std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 2c5f96d3fe..99f672a605 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -47,49 +47,28 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         }
     };
 
-    if (type == id_TRELLIS_SLICE) {
+    if (type == id_TRELLIS_COMB) {
         new_cell->params[id_MODE] = std::string("LOGIC");
-        new_cell->params[id_GSR] = std::string("DISABLED");
-        new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
-        new_cell->params[id_CEMUX] = std::string("1");
-        new_cell->params[id_CLKMUX] = std::string("CLK");
-        new_cell->params[id_LSRMUX] = std::string("LSR");
-        new_cell->params[id_LUT0_INITVAL] = Property(0, 16);
-        new_cell->params[id_LUT1_INITVAL] = Property(0, 16);
-        new_cell->params[id_REG0_SD] = std::string("0");
-        new_cell->params[id_REG1_SD] = std::string("0");
-        new_cell->params[id_REG0_REGSET] = std::string("RESET");
-        new_cell->params[id_REG1_REGSET] = std::string("RESET");
-        new_cell->params[id_CCU2_INJECT1_0] = std::string("NO");
-        new_cell->params[id_CCU2_INJECT1_1] = std::string("NO");
+        new_cell->params[id_INITVAL] = Property(0, 16);
+        new_cell->params[id_CCU2_INJECT1] = std::string("NO");
         new_cell->params[id_WREMUX] = std::string("WRE");
 
-        new_cell->addInput(id_A0);
-        new_cell->addInput(id_B0);
-        new_cell->addInput(id_C0);
-        new_cell->addInput(id_D0);
-
-        new_cell->addInput(id_A1);
-        new_cell->addInput(id_B1);
-        new_cell->addInput(id_C1);
-        new_cell->addInput(id_D1);
+        new_cell->addInput(id_A);
+        new_cell->addInput(id_B);
+        new_cell->addInput(id_C);
+        new_cell->addInput(id_D);
 
-        new_cell->addInput(id_M0);
-        new_cell->addInput(id_M1);
+        new_cell->addInput(id_M);
 
+        new_cell->addInput(id_F1);
         new_cell->addInput(id_FCI);
         new_cell->addInput(id_FXA);
         new_cell->addInput(id_FXB);
 
-        new_cell->addInput(id_CLK);
-        new_cell->addInput(id_LSR);
-        new_cell->addInput(id_CE);
-
         new_cell->addInput(id_DI0);
         new_cell->addInput(id_DI1);
 
-        new_cell->addInput(id_WD0);
-        new_cell->addInput(id_WD1);
+        new_cell->addInput(id_WD);
         new_cell->addInput(id_WAD0);
         new_cell->addInput(id_WAD1);
         new_cell->addInput(id_WAD2);
@@ -97,23 +76,15 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         new_cell->addInput(id_WRE);
         new_cell->addInput(id_WCK);
 
-        new_cell->addOutput(id_F0);
-        new_cell->addOutput(id_Q0);
-        new_cell->addOutput(id_F1);
-        new_cell->addOutput(id_Q1);
+        new_cell->addOutput(id_F);
 
         new_cell->addOutput(id_FCO);
-        new_cell->addOutput(id_OFX0);
-        new_cell->addOutput(id_OFX1);
-
-        new_cell->addOutput(id_WDO0);
-        new_cell->addOutput(id_WDO1);
-        new_cell->addOutput(id_WDO2);
-        new_cell->addOutput(id_WDO3);
-        new_cell->addOutput(id_WADO0);
-        new_cell->addOutput(id_WADO1);
-        new_cell->addOutput(id_WADO2);
-        new_cell->addOutput(id_WADO3);
+        new_cell->addOutput(id_OFX);
+    } else if (type == id_TRELLIS_RAMW) {
+        for (auto i : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1})
+            new_cell->addInput(i);
+        for (auto o : {id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3})
+            new_cell->addOutput(o);
     } else if (type == id_TRELLIS_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
         new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
@@ -200,122 +171,6 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
     return new_cell;
 }
 
-static void set_param_safe(bool has_ff, CellInfo *lc, IdString name, const std::string &value)
-{
-    NPNR_ASSERT(!has_ff || lc->params.at(name) == value);
-    lc->params[name] = value;
-}
-
-static void replace_port_safe(bool has_ff, CellInfo *ff, IdString ff_port, CellInfo *lc, IdString lc_port)
-{
-    if (has_ff) {
-        NPNR_ASSERT(lc->ports.at(lc_port).net == ff->ports.at(ff_port).net);
-        NetInfo *ffnet = ff->ports.at(ff_port).net;
-        if (ffnet != nullptr)
-            ffnet->users.remove(ff->ports.at(ff_port).user_idx);
-    } else {
-        ff->movePortTo(ff_port, lc, lc_port);
-    }
-}
-
-void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut)
-{
-    if (lc->hierpath == IdString())
-        lc->hierpath = ff->hierpath;
-    bool has_ff = lc->ports.at(id_Q0).net != nullptr || lc->ports.at(id_Q1).net != nullptr;
-    std::string reg = "REG" + std::to_string(index);
-    set_param_safe(has_ff, lc, id_SRMODE, str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE"));
-    set_param_safe(has_ff, lc, id_GSR, str_or_default(ff->params, id_GSR, "DISABLED"));
-    set_param_safe(has_ff, lc, id_CEMUX, str_or_default(ff->params, id_CEMUX, "1"));
-    set_param_safe(has_ff, lc, id_LSRMUX, str_or_default(ff->params, id_LSRMUX, "LSR"));
-    set_param_safe(has_ff, lc, id_CLKMUX, str_or_default(ff->params, id_CLKMUX, "CLK"));
-
-    lc->params[ctx->id(reg + "_SD")] = std::string(driven_by_lut ? "1" : "0");
-    lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, id_REGSET, "RESET");
-    lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, id_LSRMODE, "LSR");
-    replace_port_safe(has_ff, ff, id_CLK, lc, id_CLK);
-    if (ff->ports.find(id_LSR) != ff->ports.end())
-        replace_port_safe(has_ff, ff, id_LSR, lc, id_LSR);
-    if (ff->ports.find(id_CE) != ff->ports.end())
-        replace_port_safe(has_ff, ff, id_CE, lc, id_CE);
-
-    ff->movePortTo(id_Q, lc, ctx->id("Q" + std::to_string(index)));
-    if (ff->getPort(id_M) != nullptr) {
-        // PRLD FFs that use both M and DI
-        NPNR_ASSERT(!driven_by_lut);
-        // As M is used; must route DI through a new LUT
-        lc->params[ctx->id(reg + "_SD")] = std::string("1");
-        lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16);
-        ff->movePortTo(id_DI, lc, ctx->id("D" + std::to_string(index)));
-        ff->movePortTo(id_M, lc, ctx->id("M" + std::to_string(index)));
-        lc->connectPorts(ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
-    } else {
-        if (driven_by_lut) {
-            ff->movePortTo(id_DI, lc, ctx->id("DI" + std::to_string(index)));
-        } else {
-            ff->movePortTo(id_DI, lc, ctx->id("M" + std::to_string(index)));
-        }
-    }
-}
-
-void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
-{
-    if (lc->hierpath == IdString())
-        lc->hierpath = lut->hierpath;
-    lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
-            get_or_default(lut->params, id_INIT, Property(0, 16));
-    lut->movePortTo(id_A, lc, ctx->id("A" + std::to_string(index)));
-    lut->movePortTo(id_B, lc, ctx->id("B" + std::to_string(index)));
-    lut->movePortTo(id_C, lc, ctx->id("C" + std::to_string(index)));
-    lut->movePortTo(id_D, lc, ctx->id("D" + std::to_string(index)));
-    lut->movePortTo(id_Z, lc, ctx->id("F" + std::to_string(index)));
-}
-
-void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
-{
-    if (lc->hierpath == IdString())
-        lc->hierpath = ccu->hierpath;
-    lc->params[id_MODE] = std::string("CCU2");
-    lc->params[id_LUT0_INITVAL] = get_or_default(ccu->params, id_INIT0, Property(0, 16));
-    lc->params[id_LUT1_INITVAL] = get_or_default(ccu->params, id_INIT1, Property(0, 16));
-
-    lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES");
-    lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES");
-
-    ccu->movePortTo(id_CIN, lc, id_FCI);
-
-    ccu->movePortTo(id_A0, lc, id_A0);
-    ccu->movePortTo(id_B0, lc, id_B0);
-    ccu->movePortTo(id_C0, lc, id_C0);
-    ccu->movePortTo(id_D0, lc, id_D0);
-
-    ccu->movePortTo(id_A1, lc, id_A1);
-    ccu->movePortTo(id_B1, lc, id_B1);
-    ccu->movePortTo(id_C1, lc, id_C1);
-    ccu->movePortTo(id_D1, lc, id_D1);
-
-    ccu->movePortTo(id_S0, lc, id_F0);
-    ccu->movePortTo(id_S1, lc, id_F1);
-
-    ccu->movePortTo(id_COUT, lc, id_FCO);
-}
-
-void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
-{
-    if (lc->hierpath == IdString())
-        lc->hierpath = ram->hierpath;
-    lc->params[id_MODE] = std::string("RAMW");
-    ram->movePortTo(ctx->id("WAD[0]"), lc, id_D0);
-    ram->movePortTo(ctx->id("WAD[1]"), lc, id_B0);
-    ram->movePortTo(ctx->id("WAD[2]"), lc, id_C0);
-    ram->movePortTo(ctx->id("WAD[3]"), lc, id_A0);
-
-    ram->movePortTo(ctx->id("DI[0]"), lc, id_C1);
-    ram->movePortTo(ctx->id("DI[1]"), lc, id_A1);
-    ram->movePortTo(ctx->id("DI[2]"), lc, id_D1);
-    ram->movePortTo(ctx->id("DI[3]"), lc, id_B1);
-}
-
 static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
 {
     auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
@@ -333,16 +188,70 @@ static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
     return value;
 }
 
-void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index)
+void lut_to_comb(Context *ctx, CellInfo *lut)
+{
+    lut->type = id_TRELLIS_COMB;
+    lut->params[id_INITVAL] = get_or_default(lut->params, id_INIT, Property(0, 16));
+    lut->params.erase(id_INIT);
+    lut->renamePort(id_Z, id_F);
+}
+
+void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
+{
+    if (ramw->hierpath == IdString())
+        ramw->hierpath = ramw->hierpath;
+    ram->movePortTo(ctx->id("WAD[0]"), ramw, id_D0);
+    ram->movePortTo(ctx->id("WAD[1]"), ramw, id_B0);
+    ram->movePortTo(ctx->id("WAD[2]"), ramw, id_C0);
+    ram->movePortTo(ctx->id("WAD[3]"), ramw, id_A0);
+
+    ram->movePortTo(ctx->id("DI[0]"), ramw, id_C1);
+    ram->movePortTo(ctx->id("DI[1]"), ramw, id_A1);
+    ram->movePortTo(ctx->id("DI[2]"), ramw, id_D1);
+    ram->movePortTo(ctx->id("DI[3]"), ramw, id_B1);
+}
+
+void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i)
 {
-    if (lc->hierpath == IdString())
-        lc->hierpath = ram->hierpath;
-    lc->params[id_MODE] = std::string("DPRAM");
-    lc->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
-    lc->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
+    std::string ii = std::to_string(i);
+    if (comb->hierpath == IdString())
+        comb->hierpath = ccu->hierpath;
+
+    comb->params[id_MODE] = std::string("CCU2");
+    comb->params[id_INITVAL] = get_or_default(ccu->params, ctx->id("INIT" + ii), Property(0, 16));
+    comb->params[id_CCU2_INJECT1] = str_or_default(ccu->params, ctx->id("INJECT1_" + ii), "YES");
+
+    ccu->movePortTo(ctx->id("A" + ii), comb, id_A);
+    ccu->movePortTo(ctx->id("B" + ii), comb, id_B);
+    ccu->movePortTo(ctx->id("C" + ii), comb, id_C);
+    ccu->movePortTo(ctx->id("D" + ii), comb, id_D);
+
+    ccu->movePortTo(ctx->id("S" + ii), comb, id_F);
+
+    if (i == 0) {
+        ccu->movePortTo(id_CIN, comb, id_FCI);
+        comb->connectPort(id_FCO, internal_carry);
+    } else if (i == 1) {
+        comb->connectPort(id_FCI, internal_carry);
+        ccu->movePortTo(id_COUT, comb, id_FCO);
+    } else {
+        NPNR_ASSERT_FALSE("bad carry index!");
+    }
 
-    unsigned permuted_init0 = 0, permuted_init1 = 0;
-    unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1);
+    for (auto &attr : ccu->attrs)
+        comb->attrs[attr.first] = attr.second;
+}
+
+void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index)
+{
+    if (comb->hierpath == IdString())
+        comb->hierpath = ram->hierpath;
+    comb->params[id_MODE] = std::string("DPRAM");
+    comb->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
+    comb->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
+
+    unsigned permuted_init = 0;
+    unsigned init = get_dram_init(ctx, ram, index);
 
     for (int i = 0; i < 16; i++) {
         int permuted_addr = 0;
@@ -354,58 +263,41 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
             permuted_addr |= 4;
         if (i & 8)
             permuted_addr |= 1;
-        if (init0 & (1 << permuted_addr))
-            permuted_init0 |= (1 << i);
-        if (init1 & (1 << permuted_addr))
-            permuted_init1 |= (1 << i);
+        if (init & (1 << permuted_addr))
+            permuted_init |= (1 << i);
     }
 
-    lc->params[id_LUT0_INITVAL] = Property(permuted_init0, 16);
-    lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16);
+    comb->params[ctx->id("INITVAL")] = Property(permuted_init, 16);
 
-    if (ram->ports.count(ctx->id("RAD[0]"))) {
-        lc->connectPort(id_D0, ram->ports.at(ctx->id("RAD[0]")).net);
-        lc->connectPort(id_D1, ram->ports.at(ctx->id("RAD[0]")).net);
-    }
-    if (ram->ports.count(ctx->id("RAD[1]"))) {
-        lc->connectPort(id_B0, ram->ports.at(ctx->id("RAD[1]")).net);
-        lc->connectPort(id_B1, ram->ports.at(ctx->id("RAD[1]")).net);
-    }
-    if (ram->ports.count(ctx->id("RAD[2]"))) {
-        lc->connectPort(id_C0, ram->ports.at(ctx->id("RAD[2]")).net);
-        lc->connectPort(id_C1, ram->ports.at(ctx->id("RAD[2]")).net);
-    }
-    if (ram->ports.count(ctx->id("RAD[3]"))) {
-        lc->connectPort(id_A0, ram->ports.at(ctx->id("RAD[3]")).net);
-        lc->connectPort(id_A1, ram->ports.at(ctx->id("RAD[3]")).net);
-    }
+    if (ram->ports.count(ctx->id("RAD[0]")))
+        comb->connectPort(id_D, ram->ports.at(ctx->id("RAD[0]")).net);
 
-    if (ram->ports.count(id_WRE))
-        lc->connectPort(id_WRE, ram->ports.at(id_WRE).net);
-    if (ram->ports.count(id_WCK))
-        lc->connectPort(id_WCK, ram->ports.at(id_WCK).net);
+    if (ram->ports.count(ctx->id("RAD[1]")))
+        comb->connectPort(id_B, ram->ports.at(ctx->id("RAD[1]")).net);
+
+    if (ram->ports.count(ctx->id("RAD[2]")))
+        comb->connectPort(id_C, ram->ports.at(ctx->id("RAD[2]")).net);
 
-    ramw->connectPorts(id_WADO0, lc, id_WAD0);
-    ramw->connectPorts(id_WADO1, lc, id_WAD1);
-    ramw->connectPorts(id_WADO2, lc, id_WAD2);
-    ramw->connectPorts(id_WADO3, lc, id_WAD3);
+    if (ram->ports.count(ctx->id("RAD[3]")))
+        comb->connectPort(id_A, ram->ports.at(ctx->id("RAD[3]")).net);
 
-    if (index == 0) {
-        ramw->connectPorts(id_WDO0, lc, id_WD0);
-        ramw->connectPorts(id_WDO1, lc, id_WD1);
+    if (ram->ports.count(id_WRE))
+        comb->connectPort(id_WRE, ram->ports.at(id_WRE).net);
+    if (ram->ports.count(id_WCK))
+        comb->connectPort(id_WCK, ram->ports.at(id_WCK).net);
 
-        ram->movePortTo(ctx->id("DO[0]"), lc, id_F0);
-        ram->movePortTo(ctx->id("DO[1]"), lc, id_F1);
+    ramw->connectPorts(id_WADO0, comb, id_WAD0);
+    ramw->connectPorts(id_WADO1, comb, id_WAD1);
+    ramw->connectPorts(id_WADO2, comb, id_WAD2);
+    ramw->connectPorts(id_WADO3, comb, id_WAD3);
 
-    } else if (index == 1) {
-        ramw->connectPorts(id_WDO2, lc, id_WD0);
-        ramw->connectPorts(id_WDO3, lc, id_WD1);
+    NPNR_ASSERT(index < 4);
+    std::string ii = std::to_string(index);
+    ramw->connectPorts(ctx->id("WDO" + ii), comb, id_WD);
+    ram->movePortTo(ctx->id("DO[" + ii + "]"), comb, id_F);
 
-        ram->movePortTo(ctx->id("DO[2]"), lc, id_F0);
-        ram->movePortTo(ctx->id("DO[3]"), lc, id_F1);
-    } else {
-        NPNR_ASSERT_FALSE("bad DPRAM index");
-    }
+    for (auto &attr : ram->attrs)
+        comb->attrs[attr.first] = attr.second;
 }
 
 void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
diff --git a/ecp5/cells.h b/ecp5/cells.h
index 8f0a8cbf70..185b19ced3 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -37,8 +37,6 @@ inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 
 inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
-
 inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
 inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
@@ -62,11 +60,10 @@ inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
             (str_or_default(cell->attrs, id_ioff_dir, "") != "input"));
 }
 
-void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
-void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index);
-void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc);
-void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc);
-void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index);
+void lut_to_comb(Context *ctx, CellInfo *lut);
+void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
+void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i);
+void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index);
 
 // Convert a nextpnr IO buffer to a TRELLIS_IO
 void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 760e162305..c161f94f98 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1851,3 +1851,13 @@ X(placer)
 X(route)
 X(router)
 X(syn_useioff)
+
+X(TRELLIS_COMB)
+X(TRELLIS_RAMW)
+X(TRELLIS_COMB_CARRY0)
+X(TRELLIS_COMB_CARRY1)
+
+X(WD)
+X(OFX)
+X(F)
+X(CCU2_INJECT1)
diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc
index 8b5015f866..fe206de02b 100644
--- a/ecp5/gfx.cc
+++ b/ecp5/gfx.cc
@@ -23,11 +23,13 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 const float slice_x1 = 0.92;
+const float slice_x2_comb = 0.927;
+const float slice_x1_ff = 0.933;
 const float slice_x2 = 0.94;
 const float slice_x2_wide = 0.97;
 const float slice_y1 = 0.71;
-const float slice_y2 = 0.745 + 0.0068;
-const float slice_pitch = 0.0374 + 0.0068;
+const float slice_y2 = 0.7275 + 0.0068 / 2;
+const float slice_pitch = (0.0374 + 0.0068) / 2;
 
 const float io_cell_v_x1 = 0.76;
 const float io_cell_v_x2 = 0.95;
@@ -54,11 +56,25 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
     GraphicElement el;
     el.type = GraphicElement::TYPE_BOX;
     el.style = style;
-    if (bel_type == id_TRELLIS_SLICE) {
+    if (bel_type == id_TRELLIS_COMB) {
         el.x1 = x + slice_x1;
+        el.x2 = x + slice_x2_comb;
+        el.y1 = y + slice_y1 + (z >> Arch::lc_idx_shift) * slice_pitch;
+        el.y2 = y + slice_y2 + (z >> Arch::lc_idx_shift) * slice_pitch;
+        g.push_back(el);
+
+        el.style = GraphicElement::STYLE_FRAME;
+        el.x1 = x + slice_x2_comb + 15 * wire_distance;
+        el.x2 = el.x1 + wire_distance;
+        el.y1 = y + slice_y2 - wire_distance * (TILE_WIRE_CLK3_SLICE - TILE_WIRE_DUMMY_D2 + 5 + (3 - z) * 26) +
+                3 * slice_pitch - 0.0007f;
+        el.y2 = el.y1 + wire_distance * 5;
+        g.push_back(el);
+    } else if (bel_type == id_TRELLIS_FF) {
+        el.x1 = x + slice_x1_ff;
         el.x2 = x + slice_x2;
-        el.y1 = y + slice_y1 + (z)*slice_pitch;
-        el.y2 = y + slice_y2 + (z)*slice_pitch;
+        el.y1 = y + slice_y1 + (z >> Arch::lc_idx_shift) * slice_pitch;
+        el.y2 = y + slice_y2 + (z >> Arch::lc_idx_shift) * slice_pitch;
         g.push_back(el);
 
         el.style = GraphicElement::STYLE_FRAME;
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 71188aa0fb..7123705a63 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -53,7 +53,9 @@ class Ecp5GlobalRouter
   private:
     bool is_clock_port(const PortRef &user)
     {
-        if (user.cell->type == id_TRELLIS_SLICE && (user.port == id_CLK || user.port == id_WCK))
+        if (user.cell->type == id_TRELLIS_FF && user.port == id_CLK)
+            return true;
+        if (user.cell->type == id_TRELLIS_COMB && user.port == id_WCK)
             return true;
         if (user.cell->type == id_DCUA && (user.port == id_CH0_FF_RXI_CLK || user.port == id_CH1_FF_RXI_CLK ||
                                            user.port == id_CH0_FF_TXI_CLK || user.port == id_CH1_FF_TXI_CLK))
@@ -65,7 +67,9 @@ class Ecp5GlobalRouter
 
     bool is_logic_port(const PortRef &user)
     {
-        if (user.cell->type == id_TRELLIS_SLICE && user.port != id_CLK && user.port != id_WCK)
+        if (user.cell->type == id_TRELLIS_FF && user.port != id_CLK)
+            return true;
+        if (user.cell->type == id_TRELLIS_COMB && user.port != id_WCK)
             return true;
         return false;
     }
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index f65e992ee2..7aa9b4c4b0 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -56,22 +56,21 @@ class Ecp5Packer
     }
 
     // Print logic usage
-    int available_slices = 0;
     void print_logic_usage()
     {
         int total_luts = 0, total_ffs = 0;
         int total_ramluts = 0, total_ramwluts = 0;
         for (auto bel : ctx->getBels()) {
-            if (ctx->getBelType(bel) == id_TRELLIS_SLICE) {
-                available_slices += 1;
-                total_luts += 2;
-                total_ffs += 2;
+            if (ctx->getBelType(bel) == id_TRELLIS_COMB) {
+                total_luts += 1;
                 Loc l = ctx->getBelLocation(bel);
-                if (l.z == 0 || l.z == 1)
-                    total_ramluts += 2;
-                if (l.z == 2)
-                    total_ramwluts += 2;
+                if (l.z <= 3)
+                    total_ramluts += 1;
             }
+            if (ctx->getBelType(bel) == id_TRELLIS_FF)
+                total_ffs += 1;
+            if (ctx->getBelType(bel) == id_TRELLIS_RAMW)
+                total_ramwluts += 2;
         }
         int used_lgluts = 0, used_cyluts = 0, used_ramluts = 0, used_ramwluts = 0, used_ffs = 0;
         for (auto &cell : ctx->cells) {
@@ -101,292 +100,164 @@ class Ecp5Packer
         log_break();
     }
 
-    // Find FFs associated with LUTs, or LUT expansion muxes
-    void find_lutff_pairs()
+    // Pack LUTs
+    void pack_luts()
     {
-        log_info("Finding LUTFF pairs...\n");
+        log_info("Packing LUTs...\n");
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
-                NetInfo *znet = ci->ports.at(id_Z).net;
-                if (znet != nullptr) {
-                    CellInfo *ff = net_only_drives(ctx, znet, is_ff, id_DI, false);
-                    // Can't combine preload FF with LUT due to conflict on M
-                    if (ff != nullptr && ff->getPort(id_M) == nullptr) {
-                        lutffPairs[ci->name] = ff->name;
-                        fflutPairs[ff->name] = ci->name;
-                    }
-                }
-            }
-        }
-    }
-
-    // Check if a flipflop is available in a slice
-    bool is_ff_available(CellInfo *slice, int ff)
-    {
-        if (slice->getPort((ff == 1) ? id_Q1 : id_Q0) != nullptr)
-            return false;
-        if (slice->getPort((ff == 1) ? id_M1 : id_M0) != nullptr)
-            return false;
-        return true;
-    }
-
-    // Check if a flipflop can be added to a slice
-    bool can_add_ff_to_slice(CellInfo *slice, CellInfo *ff)
-    {
-        std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
-        std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
-
-        bool has_dpram = str_or_default(slice->params, id_MODE, "LOGIC") == "DPRAM";
-        if (has_dpram) {
-            std::string wckmux = str_or_default(slice->params, id_WCKMUX, "WCK");
-            std::string wremux = str_or_default(slice->params, id_WREMUX, "WRE");
-            if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
-                return false;
-            if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
-                return false;
+            if (is_lut(ctx, ci))
+                lut_to_comb(ctx, ci);
         }
-        bool has_ff0 = slice->getPort(id_Q0) != nullptr;
-        bool has_ff1 = slice->getPort(id_Q1) != nullptr;
-        if (!has_ff0 && !has_ff1)
-            return true;
-        if (str_or_default(ff->params, id_GSR, "DISABLED") != str_or_default(slice->params, id_GSR, "DISABLED"))
-            return false;
-        if (str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE") !=
-            str_or_default(slice->params, id_SRMODE, "LSR_OVER_CE"))
-            return false;
-        if (str_or_default(ff->params, id_CEMUX, "1") != str_or_default(slice->params, id_CEMUX, "1"))
-            return false;
-        if (str_or_default(ff->params, id_LSRMUX, "LSR") != str_or_default(slice->params, id_LSRMUX, "LSR"))
-            return false;
-        if (str_or_default(ff->params, id_CLKMUX, "CLK") != str_or_default(slice->params, id_CLKMUX, "CLK"))
-            return false;
-        if (net_or_nullptr(ff, id_CLK) != net_or_nullptr(slice, id_CLK))
-            return false;
-        if (net_or_nullptr(ff, id_CE) != net_or_nullptr(slice, id_CE))
-            return false;
-        if (net_or_nullptr(ff, id_LSR) != net_or_nullptr(slice, id_LSR))
-            return false;
-        return true;
     }
 
-    const NetInfo *net_or_nullptr(CellInfo *cell, IdString port)
+    // Gets the z-position of a cell in a macro
+    int get_macro_cell_z(const CellInfo *ci)
     {
-        auto fnd = cell->ports.find(port);
-        if (fnd == cell->ports.end())
-            return nullptr;
+        if (ci->constr_abs_z)
+            return ci->constr_z;
+        else if (ci->cluster != ClusterId() && ctx->getClusterRootCell(ci->cluster) != ci)
+            return ci->constr_z + get_macro_cell_z(ctx->getClusterRootCell(ci->cluster));
         else
-            return fnd->second.net;
+            return 0;
     }
 
-    // Return whether two FFs can be packed together in the same slice
-    bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
+    // Gets the relative xy-position of a cell in a macro
+    std::pair<int, int> get_macro_cell_xy(const CellInfo *ci)
     {
-        if (str_or_default(ff0->params, id_GSR, "DISABLED") != str_or_default(ff1->params, id_GSR, "DISABLED"))
-            return false;
-        if (str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE") !=
-            str_or_default(ff1->params, id_SRMODE, "LSR_OVER_CE"))
-            return false;
-        if (str_or_default(ff0->params, id_CEMUX, "1") != str_or_default(ff1->params, id_CEMUX, "1"))
-            return false;
-        if (str_or_default(ff0->params, id_LSRMUX, "LSR") != str_or_default(ff1->params, id_LSRMUX, "LSR"))
-            return false;
-        if (str_or_default(ff0->params, id_CLKMUX, "CLK") != str_or_default(ff1->params, id_CLKMUX, "CLK"))
-            return false;
-        if (net_or_nullptr(ff0, id_CLK) != net_or_nullptr(ff1, id_CLK))
-            return false;
-        if (net_or_nullptr(ff0, id_CE) != net_or_nullptr(ff1, id_CE))
-            return false;
-        if (net_or_nullptr(ff0, id_LSR) != net_or_nullptr(ff1, id_LSR))
-            return false;
-        return true;
+        if (ci->cluster != ClusterId())
+            return {ci->constr_x, ci->constr_y};
+        else
+            return {0, 0};
     }
 
-    // Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above)
-    bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
+    // Relatively constrain one cell to another
+    void rel_constr_cells(CellInfo *a, CellInfo *b, int dz)
     {
-        for (const auto &existing : tile_ffs) {
-            if (net_or_nullptr(existing, id_CLK) != net_or_nullptr(ff0, id_CLK))
-                return false;
-            if (net_or_nullptr(existing, id_LSR) != net_or_nullptr(ff0, id_LSR))
-                return false;
-            if (str_or_default(existing->params, id_CLKMUX, "CLK") != str_or_default(ff0->params, id_CLKMUX, "CLK"))
-                return false;
-            if (str_or_default(existing->params, id_LSRMUX, "LSR") != str_or_default(ff0->params, id_LSRMUX, "LSR"))
-                return false;
-            if (str_or_default(existing->params, id_SRMODE, "LSR_OVER_CE") !=
-                str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE"))
-                return false;
+        if (a->cluster != ClusterId() && ctx->getClusterRootCell(a->cluster) != a) {
+            NPNR_ASSERT(b->cluster == ClusterId());
+            NPNR_ASSERT(b->constr_children.empty());
+            CellInfo *root = ctx->getClusterRootCell(a->cluster);
+            root->constr_children.push_back(b);
+            b->cluster = root->cluster;
+            b->constr_x = a->constr_x;
+            b->constr_y = a->constr_y;
+            b->constr_z = get_macro_cell_z(a) + dz;
+            b->constr_abs_z = a->constr_abs_z;
+        } else if (b->cluster != ClusterId() && ctx->getClusterRootCell(b->cluster) != b) {
+            NPNR_ASSERT(a->constr_children.empty());
+            CellInfo *root = ctx->getClusterRootCell(b->cluster);
+            root->constr_children.push_back(a);
+            a->cluster = root->cluster;
+            a->constr_x = b->constr_x;
+            a->constr_y = b->constr_y;
+            a->constr_z = get_macro_cell_z(b) - dz;
+            a->constr_abs_z = b->constr_abs_z;
+        } else if (!b->constr_children.empty()) {
+            NPNR_ASSERT(a->constr_children.empty());
+            b->constr_children.push_back(a);
+            a->cluster = b->cluster;
+            a->constr_x = 0;
+            a->constr_y = 0;
+            a->constr_z = get_macro_cell_z(b) - dz;
+            a->constr_abs_z = b->constr_abs_z;
+        } else {
+            NPNR_ASSERT(a->cluster == ClusterId() || ctx->getClusterRootCell(a->cluster) == a);
+            a->constr_children.push_back(b);
+            a->cluster = a->name;
+            b->cluster = a->name;
+            b->constr_x = 0;
+            b->constr_y = 0;
+            b->constr_z = get_macro_cell_z(a) + dz;
+            b->constr_abs_z = a->constr_abs_z;
         }
-        return true;
     }
 
-    // Return true if a FF can be added to a DPRAM slice
-    bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
+    // Check if it is legal to add a FF to a macro
+    // This reuses the tile validity code
+    bool can_add_flipflop_to_macro(CellInfo *comb, CellInfo *ff)
     {
-        if (ff->getPort(id_M) != nullptr)
-            return false; // skip PRLD FFs due to M/DI conflict
-        std::string wckmux = str_or_default(dpram->params, id_WCKMUX, "WCK");
-        std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
-        if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
-            return false;
-        std::string wremux = str_or_default(dpram->params, id_WREMUX, "WRE");
-        std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
-        if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
-            return false;
-        return true;
-    }
+        Arch::LogicTileStatus lts;
+        std::fill(lts.cells.begin(), lts.cells.end(), nullptr);
+        lts.tile_dirty = true;
+        for (auto &sl : lts.slices)
+            sl.dirty = true;
+
+        auto process_cell = [&](CellInfo *ci) {
+            if (get_macro_cell_xy(ci) != get_macro_cell_xy(comb))
+                return;
+            int z = get_macro_cell_z(ci);
+            auto &slot = lts.cells.at(z);
+            NPNR_ASSERT(slot == nullptr);
+            slot = ci;
+            // Make sure fields needed for validity checking are set correctly
+            ctx->assign_arch_info_for_cell(ci);
+        };
 
-    // Return true if two LUTs can be paired considering FF compatibility
-    bool can_pack_lutff(IdString lut0, IdString lut1)
-    {
-        auto ff0 = lutffPairs.find(lut0), ff1 = lutffPairs.find(lut1);
-        if (ff0 != lutffPairs.end() && ff1 != lutffPairs.end()) {
-            return can_pack_ffs(ctx->cells.at(ff0->second).get(), ctx->cells.at(ff1->second).get());
+        if (comb->cluster != ClusterId()) {
+            CellInfo *root = ctx->getClusterRootCell(comb->cluster);
+            process_cell(root);
+            for (auto &ch : root->constr_children)
+                process_cell(ch);
         } else {
-            return true;
+            process_cell(comb);
+            for (auto &ch : comb->constr_children)
+                process_cell(ch);
         }
+        int ff_z = get_macro_cell_z(comb) + (Arch::BEL_FF - Arch::BEL_COMB);
+        if (lts.cells.at(ff_z) != nullptr)
+            return false;
+        ctx->assign_arch_info_for_cell(ff);
+        lts.cells.at(ff_z) = ff;
+        return ctx->slices_compatible(&lts);
     }
 
-    // Find "closely connected" LUTs and pair them together
-    void pair_luts()
+    void pack_ffs()
     {
-        log_info("Finding LUT-LUT pairs...\n");
-        pool<IdString> procdLuts;
+        log_info("Packing FFs...\n");
+        int pairs = 0;
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
-                NetInfo *znet = ci->ports.at(id_Z).net;
-                std::vector<NetInfo *> inpnets;
-                if (znet != nullptr) {
-                    for (auto user : znet->users) {
-                        if (is_lut(ctx, user.cell) && user.cell != ci &&
-                            procdLuts.find(user.cell->name) == procdLuts.end()) {
-                            if (can_pack_lutff(ci->name, user.cell->name)) {
-                                procdLuts.insert(ci->name);
-                                procdLuts.insert(user.cell->name);
-                                lutPairs[ci->name] = user.cell->name;
-                                goto paired;
-                            }
-                        }
-                    }
-                    if (false) {
-                    paired:
-                        continue;
-                    }
-                }
-                if (lutffPairs.find(ci->name) != lutffPairs.end()) {
-                    NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(id_Q).net;
-                    if (qnet != nullptr) {
-                        for (auto user : qnet->users) {
-                            if (is_lut(ctx, user.cell) && user.cell != ci &&
-                                procdLuts.find(user.cell->name) == procdLuts.end()) {
-                                if (can_pack_lutff(ci->name, user.cell->name)) {
-                                    procdLuts.insert(ci->name);
-                                    procdLuts.insert(user.cell->name);
-                                    lutPairs[ci->name] = user.cell->name;
-                                    goto paired_ff;
-                                }
-                            }
-                        }
-                        if (false) {
-                        paired_ff:
+            if (is_ff(ctx, ci)) {
+                NetInfo *di = get_net_or_empty(ci, id_DI);
+                if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
+                    CellInfo *comb = di->driver.cell;
+                    if (comb->cluster != ClusterId()) {
+                        // Special procedure where the comb cell is part of an existing macro
+                        // Need to make sure that CLK, CE, SR, etc are shared correctly, or
+                        // the design will not be routeable
+                        if (can_add_flipflop_to_macro(comb, ci)) {
+                            ci->params[id_SD] = std::string("1");
+                            rel_constr_cells(comb, ci, (Arch::BEL_FF - Arch::BEL_COMB));
+                            // Packed successfully
+                            ++pairs;
                             continue;
                         }
-                    }
-                }
-                for (const char *inp : {"A", "B", "C", "D"}) {
-                    if (!ci->ports.count(ctx->id(inp)))
-                        continue;
-                    NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
-                    if (innet != nullptr && innet->driver.cell != nullptr) {
-                        CellInfo *drv = innet->driver.cell;
-                        if (is_lut(ctx, drv) && drv != ci && innet->driver.port == id_Z) {
-                            if (procdLuts.find(drv->name) == procdLuts.end()) {
-                                if (can_pack_lutff(ci->name, drv->name)) {
-                                    procdLuts.insert(ci->name);
-                                    procdLuts.insert(drv->name);
-                                    lutPairs[ci->name] = drv->name;
-                                    goto paired_inlut;
-                                }
-                            }
-                        } else if (is_ff(ctx, drv) && innet->driver.port == id_Q) {
-                            auto fflut = fflutPairs.find(drv->name);
-                            if (fflut != fflutPairs.end() && fflut->second != ci->name &&
-                                procdLuts.find(fflut->second) == procdLuts.end()) {
-                                if (can_pack_lutff(ci->name, fflut->second)) {
-                                    procdLuts.insert(ci->name);
-                                    procdLuts.insert(fflut->second);
-                                    lutPairs[ci->name] = fflut->second;
-                                    goto paired_inlut;
-                                }
-                            }
-                        }
-                    }
-                }
-
-                // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
-                if (znet != nullptr && znet->users.entries() < 10) {
-                    for (auto user : znet->users) {
-                        if (is_lc(ctx, user.cell) || user.cell->type == id_DP16KD || is_ff(ctx, user.cell)) {
-                            for (auto port : user.cell->ports) {
-                                if (port.second.type != PORT_IN || port.second.net == nullptr ||
-                                    port.second.net == znet)
-                                    continue;
-                                if (port.second.net->users.entries() > 10)
-                                    continue;
-                                CellInfo *drv = port.second.net->driver.cell;
-                                if (drv == nullptr)
-                                    continue;
-                                if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
-                                    can_pack_lutff(ci->name, drv->name)) {
-                                    procdLuts.insert(ci->name);
-                                    procdLuts.insert(drv->name);
-                                    lutPairs[ci->name] = drv->name;
-                                    goto paired_inlut;
-                                }
-                            }
-                        }
-                    }
-                }
-
-                // Pack LUTs sharing an input with a simple fanout-based heuristic
-                for (const char *inp : {"A", "B", "C", "D"}) {
-                    if (!ci->ports.count(ctx->id(inp)))
+                    } else {
+                        // LUT/COMB is not part of a macro, this is the easy case
+                        // Constrain FF and LUT together, no need to rewire
+                        ci->params[id_SD] = std::string("1");
+                        comb->constr_children.push_back(ci);
+                        ci->cluster = comb->name;
+                        comb->cluster = comb->name;
+                        ci->constr_x = 0;
+                        ci->constr_y = 0;
+                        ci->constr_z = (Arch::BEL_FF - Arch::BEL_COMB);
+                        ci->constr_abs_z = false;
+                        // Packed successfully
+                        ++pairs;
                         continue;
-                    NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
-                    if (innet != nullptr && innet->users.entries() < 5 && innet->users.entries() > 1)
-                        inpnets.push_back(innet);
-                }
-                std::sort(inpnets.begin(), inpnets.end(),
-                          [&](const NetInfo *a, const NetInfo *b) { return a->users.entries() < b->users.entries(); });
-                for (auto inet : inpnets) {
-                    for (auto &user : inet->users) {
-                        if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
-                            continue;
-                        if (procdLuts.count(user.cell->name))
-                            continue;
-                        if (can_pack_lutff(ci->name, user.cell->name)) {
-                            procdLuts.insert(ci->name);
-                            procdLuts.insert(user.cell->name);
-                            lutPairs[ci->name] = user.cell->name;
-                            goto paired_inlut;
-                        }
                     }
                 }
-
-                if (false) {
-                paired_inlut:
-                    continue;
+                {
+                    // Didn't manage to pack it with a driving combinational cell
+                    // Rewire to use general routing
+                    ci->params[id_SD] = std::string("0");
+                    ci->renamePort(id_DI, id_M);
                 }
             }
         }
-        if (ctx->debug) {
-            log_info("Singleton LUTs (packer QoR debug): \n");
-            for (auto &cell : ctx->cells)
-                if (is_lut(ctx, cell.second.get()) && !procdLuts.count(cell.first))
-                    log_info("     %s\n", cell.first.c_str(ctx));
-        }
+        log_info("    %d FFs paired with LUTs.\n", pairs);
     }
 
     // Return true if an port is a top level port that provides its own IOBUF
@@ -429,6 +300,192 @@ class Ecp5Packer
         return false;
     }
 
+    // Pass to pack LUT5s into a newly created slice
+    void pack_lut5xs()
+    {
+        log_info("Packing LUT5-7s...\n");
+
+        // Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
+        auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
+            NetInfo *f1 = get_net_or_empty(lut5, id_F1);
+            NPNR_ASSERT(f1 != nullptr);
+            NPNR_ASSERT(f1->driver.cell != nullptr);
+            return f1->driver.cell;
+        };
+
+        dict<IdString, std::pair<CellInfo *, CellInfo *>> lut5_roots, lut6_roots, lut7_roots;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_pfumx(ctx, ci)) {
+                NetInfo *f0 = ci->ports.at(id_BLUT).net;
+
+                if (f0 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
+                NetInfo *f1 = ci->ports.at(id_ALUT).net;
+                if (f1 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
+
+                CellInfo *lut0 =
+                        (f0->driver.cell && f0->driver.cell->type == id_TRELLIS_COMB && f0->driver.port == id_F)
+                                ? f0->driver.cell
+                                : nullptr;
+                CellInfo *lut1 =
+                        (f1->driver.cell && f1->driver.cell->type == id_TRELLIS_COMB && f1->driver.port == id_F)
+                                ? f1->driver.cell
+                                : nullptr;
+                if (lut0 == nullptr || lut0->cluster != ClusterId())
+                    log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                if (lut1 == nullptr || lut1->cluster != ClusterId())
+                    log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                lut0->addInput(id_F1);
+                lut0->addInput(id_M);
+                lut0->addOutput(id_OFX);
+
+                ci->movePortTo(id_Z, lut0, id_OFX);
+                ci->movePortTo(id_ALUT, lut0, id_F1);
+                ci->movePortTo(id_C0, lut0, id_M);
+                ci->disconnectPort(id_BLUT);
+
+                lut5_roots[lut0->name] = {lut0, lut1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT6s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
+                if (ofx0_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
+                if (ofx0_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb0 = (ofx0_0->driver.cell && ofx0_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_0->driver.port == id_OFX)
+                                          ? ofx0_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb1 = (ofx0_1->driver.cell && ofx0_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_1->driver.port == id_OFX)
+                                          ? ofx0_1->driver.cell
+                                          : nullptr;
+                if (comb0 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb0->name))
+                    continue;
+
+                if (comb1 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb1->name))
+                    continue;
+                if (ctx->verbose)
+                    log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
+                comb0 = get_comb1_from_lut5(comb0);
+                comb1 = get_comb1_from_lut5(comb1);
+
+                comb1->addInput(id_FXA);
+                comb1->addInput(id_FXB);
+                comb1->addInput(id_M);
+                comb1->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb1, id_FXA);
+                ci->movePortTo(id_D1, comb1, id_FXB);
+                ci->movePortTo(id_SD, comb1, id_M);
+                ci->movePortTo(id_Z, comb1, id_OFX);
+                lut6_roots[comb1->name] = {comb0, comb1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT7s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
+                if (ofx1_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
+                if (ofx1_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb1 = (ofx1_0->driver.cell && ofx1_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_0->driver.port == id_OFX)
+                                          ? ofx1_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb3 = (ofx1_1->driver.cell && ofx1_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_1->driver.port == id_OFX)
+                                          ? ofx1_1->driver.cell
+                                          : nullptr;
+                if (comb1 == nullptr)
+                    log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
+                              ofx1_0->driver.port.c_str(ctx));
+                if (comb3 == nullptr)
+                    log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
+                              ofx1_1->driver.port.c_str(ctx));
+
+                NetInfo *fxa_0 = comb1->ports.at(id_FXA).net;
+                if (fxa_0 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb1->name.c_str(ctx));
+                NetInfo *fxa_1 = comb3->ports.at(id_FXA).net;
+                if (fxa_1 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb3->name.c_str(ctx));
+
+                CellInfo *comb2 = net_driven_by(
+                        ctx, fxa_1,
+                        [](const Context *ctx, const CellInfo *ci) {
+                            (void)ctx;
+                            return ci->type == id_TRELLIS_COMB;
+                        },
+                        id_OFX);
+                if (comb2 == nullptr)
+                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
+                              comb3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
+                              fxa_1->driver.port.c_str(ctx));
+                comb2 = get_comb1_from_lut5(comb2);
+                comb2->addInput(id_FXA);
+                comb2->addInput(id_FXB);
+                comb2->addInput(id_M);
+                comb2->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb2, id_FXA);
+                ci->movePortTo(id_D1, comb2, id_FXB);
+                ci->movePortTo(id_SD, comb2, id_M);
+                ci->movePortTo(id_Z, comb2, id_OFX);
+
+                lut7_roots[comb2->name] = {comb1, comb3};
+                packed_cells.insert(ci->name);
+            }
+        }
+
+        for (auto &root : lut7_roots) {
+            auto &cells = root.second;
+            cells.second->cluster = cells.second->name;
+            cells.second->constr_abs_z = true;
+            cells.second->constr_z = (1 << Arch::lc_idx_shift) | Arch::BEL_COMB;
+            rel_constr_cells(cells.second, cells.first, (4 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut6_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.second, cells.first, (2 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut5_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.first, cells.second, (1 << Arch::lc_idx_shift));
+        }
+        flush_cells();
+    }
+
     // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
     void pack_io()
     {
@@ -523,215 +580,6 @@ class Ecp5Packer
         flush_cells();
     }
 
-    // Pass to pack LUT5s into a newly created slice
-    void pack_lut5xs()
-    {
-        log_info("Packing LUT5-7s...\n");
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_pfumx(ctx, ci)) {
-                std::unique_ptr<CellInfo> packed =
-                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
-                NetInfo *f0 = ci->ports.at(id_BLUT).net;
-                if (f0 == nullptr)
-                    log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
-                NetInfo *f1 = ci->ports.at(id_ALUT).net;
-                if (f1 == nullptr)
-                    log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
-                CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, id_Z);
-                CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, id_Z);
-                if (lut0 == nullptr)
-                    log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
-                if (lut1 == nullptr)
-                    log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
-                if (ctx->verbose)
-                    log_info("   mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
-                lut0->movePortTo(id_A, packed.get(), id_A0);
-                lut0->movePortTo(id_B, packed.get(), id_B0);
-                lut0->movePortTo(id_C, packed.get(), id_C0);
-                lut0->movePortTo(id_D, packed.get(), id_D0);
-                lut1->movePortTo(id_A, packed.get(), id_A1);
-                lut1->movePortTo(id_B, packed.get(), id_B1);
-                lut1->movePortTo(id_C, packed.get(), id_C1);
-                lut1->movePortTo(id_D, packed.get(), id_D1);
-                ci->movePortTo(id_C0, packed.get(), id_M0);
-                ci->movePortTo(id_Z, packed.get(), id_OFX0);
-                packed->params[id_LUT0_INITVAL] = get_or_default(lut0->params, id_INIT, Property(0, 16));
-                packed->params[id_LUT1_INITVAL] = get_or_default(lut1->params, id_INIT, Property(0, 16));
-
-                ctx->nets.erase(f0->name);
-                ctx->nets.erase(f1->name);
-                sliceUsage[packed->name].lut0_used = true;
-                sliceUsage[packed->name].lut1_used = true;
-                sliceUsage[packed->name].mux5_used = true;
-
-                if (lutffPairs.find(ci->name) != lutffPairs.end()) {
-                    CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
-                    ff_to_slice(ctx, ff, packed.get(), 0, true);
-                    packed_cells.insert(ff->name);
-                    sliceUsage[packed->name].ff0_used = true;
-                    lutffPairs.erase(ci->name);
-                    fflutPairs.erase(ff->name);
-                }
-
-                new_cells.push_back(std::move(packed));
-                packed_cells.insert(lut0->name);
-                packed_cells.insert(lut1->name);
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-        // Pack LUT6s
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
-                if (ofx0_0 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
-                if (ofx0_1 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, id_OFX0);
-                CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, id_OFX0);
-                if (slice0 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_0, is_lc, id_OFX1))
-                        log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
-                                  "('%s.%s')\n",
-                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
-                                  ofx0_0->driver.port.c_str(ctx));
-                    continue;
-                }
-                if (slice1 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_1, is_lc, id_OFX1))
-                        log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
-                                  "('%s.%s')\n",
-                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
-                                  ofx0_0->driver.port.c_str(ctx));
-                    continue;
-                }
-                if (ctx->verbose)
-                    log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
-                ci->movePortTo(id_D0, slice1, id_FXA);
-                ci->movePortTo(id_D1, slice1, id_FXB);
-                ci->movePortTo(id_SD, slice1, id_M1);
-                ci->movePortTo(id_Z, slice1, id_OFX1);
-                slice0->constr_z = 1;
-                slice0->constr_x = 0;
-                slice0->constr_y = 0;
-                slice0->cluster = slice1->name;
-                slice1->constr_z = 0;
-                slice1->constr_abs_z = true;
-                slice1->constr_children.push_back(slice0);
-                slice1->cluster = slice1->name;
-
-                if (lutffPairs.find(ci->name) != lutffPairs.end()) {
-                    CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
-                    ff_to_slice(ctx, ff, slice1, 1, true);
-                    packed_cells.insert(ff->name);
-                    sliceUsage[slice1->name].ff1_used = true;
-                    lutffPairs.erase(ci->name);
-                    fflutPairs.erase(ff->name);
-                }
-
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-        // Pack LUT7s
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
-                if (ofx1_0 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
-                if (ofx1_1 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, id_OFX1);
-                CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, id_OFX1);
-                if (slice1 == nullptr)
-                    log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
-                              ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
-                              ofx1_0->driver.port.c_str(ctx));
-                if (slice3 == nullptr)
-                    log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
-                              ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
-                              ofx1_1->driver.port.c_str(ctx));
-
-                NetInfo *fxa_0 = slice1->ports.at(id_FXA).net;
-                if (fxa_0 == nullptr)
-                    log_error("SLICE '%s' has disconnected port 'FXA'\n", slice1->name.c_str(ctx));
-                NetInfo *fxa_1 = slice3->ports.at(id_FXA).net;
-                if (fxa_1 == nullptr)
-                    log_error("SLICE '%s' has disconnected port 'FXA'\n", slice3->name.c_str(ctx));
-
-                CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, id_OFX0);
-                CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, id_OFX0);
-                if (slice0 == nullptr)
-                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
-                              slice1->name.c_str(ctx), fxa_0->driver.cell->name.c_str(ctx),
-                              fxa_0->driver.port.c_str(ctx));
-                if (slice2 == nullptr)
-                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
-                              slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
-                              fxa_1->driver.port.c_str(ctx));
-
-                ci->movePortTo(id_D0, slice2, id_FXA);
-                ci->movePortTo(id_D1, slice2, id_FXB);
-                ci->movePortTo(id_SD, slice2, id_M1);
-                ci->movePortTo(id_Z, slice2, id_OFX1);
-
-                for (auto slice : {slice0, slice1, slice2, slice3}) {
-                    slice->constr_children.clear();
-                    slice->constr_abs_z = false;
-                    slice->constr_x = 0;
-                    slice->constr_y = 0;
-                    slice->constr_z = 0;
-                    slice->cluster = ClusterId();
-                }
-                slice3->constr_children.clear();
-                slice3->constr_abs_z = true;
-                slice3->constr_z = 0;
-                slice3->cluster = slice3->name;
-
-                slice2->constr_children.clear();
-                slice2->constr_abs_z = true;
-                slice2->constr_z = 1;
-                slice2->constr_x = 0;
-                slice2->constr_y = 0;
-                slice2->cluster = slice3->name;
-                slice3->constr_children.push_back(slice2);
-
-                slice1->constr_children.clear();
-                slice1->constr_abs_z = true;
-                slice1->constr_z = 2;
-                slice1->constr_x = 0;
-                slice1->constr_y = 0;
-                slice1->cluster = slice3->name;
-                slice3->constr_children.push_back(slice1);
-
-                slice0->constr_children.clear();
-                slice0->constr_abs_z = true;
-                slice0->constr_z = 3;
-                slice0->constr_x = 0;
-                slice0->constr_y = 0;
-                slice0->cluster = slice3->name;
-                slice3->constr_children.push_back(slice0);
-
-                if (lutffPairs.find(ci->name) != lutffPairs.end()) {
-                    CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
-                    ff_to_slice(ctx, ff, slice2, 1, true);
-                    packed_cells.insert(ff->name);
-                    sliceUsage[slice2->name].ff1_used = true;
-                    lutffPairs.erase(ci->name);
-                    fflutPairs.erase(ff->name);
-                }
-
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-    }
     // Create a feed in to the carry chain
     CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
     {
@@ -881,58 +729,37 @@ class Ecp5Packer
         std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
         for (auto &chain : all_chains) {
             int cell_count = 0;
-            std::vector<CellInfo *> tile_ffs;
             std::vector<CellInfo *> packed_chain;
             for (auto &cell : chain.cells) {
-                if (cell_count % 4 == 0)
-                    tile_ffs.clear();
-                std::unique_ptr<CellInfo> slice =
-                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, cell->name.str(ctx) + "$CCU2_SLICE");
-
-                ccu2c_to_slice(ctx, cell, slice.get());
-
-                CellInfo *ff0 = nullptr;
-                NetInfo *f0net = slice->ports.at(id_F0).net;
-                if (f0net != nullptr) {
-                    ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
-                    if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
-                        ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
-                        tile_ffs.push_back(ff0);
-                        packed_cells.insert(ff0->name);
-                    }
-                }
+                std::unique_ptr<CellInfo> comb0 =
+                        create_ecp5_cell(ctx, id_TRELLIS_COMB, cell->name.str(ctx) + "$CCU2_COMB0");
+                std::unique_ptr<CellInfo> comb1 =
+                        create_ecp5_cell(ctx, id_TRELLIS_COMB, cell->name.str(ctx) + "$CCU2_COMB1");
+                NetInfo *carry_net = ctx->createNet(ctx->id(cell->name.str(ctx) + "$CCU2_FCI_INT"));
 
-                CellInfo *ff1 = nullptr;
-                NetInfo *f1net = slice->ports.at(id_F1).net;
-                if (f1net != nullptr) {
-                    ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
-                    if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
-                        can_add_ff_to_tile(tile_ffs, ff1)) {
-                        ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
-                        tile_ffs.push_back(ff1);
-                        packed_cells.insert(ff1->name);
-                    }
-                }
-                packed_chain.push_back(slice.get());
-                new_cells.push_back(std::move(slice));
+                ccu2_to_comb(ctx, cell, comb0.get(), carry_net, 0);
+                ccu2_to_comb(ctx, cell, comb1.get(), carry_net, 1);
+
+                packed_chain.push_back(comb0.get());
+                packed_chain.push_back(comb1.get());
+
+                new_cells.push_back(std::move(comb0));
+                new_cells.push_back(std::move(comb1));
                 packed_cells.insert(cell->name);
                 cell_count++;
             }
             packed_chains.push_back(packed_chain);
         }
 
-        for (auto ff : ff_packing)
-            ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
-
         // Relative chain placement
         for (auto &chain : packed_chains) {
             chain.at(0)->constr_abs_z = true;
             chain.at(0)->constr_z = 0;
             chain.at(0)->cluster = chain.at(0)->name;
             for (int i = 1; i < int(chain.size()); i++) {
-                chain.at(i)->constr_x = (i / 4);
+                chain.at(i)->constr_x = (i / 8);
                 chain.at(i)->constr_y = 0;
-                chain.at(i)->constr_z = i % 4;
+                chain.at(i)->constr_z = (i % 8) << ctx->lc_idx_shift | Arch::BEL_COMB;
                 chain.at(i)->constr_abs_z = true;
                 chain.at(i)->cluster = chain.at(0)->name;
                 chain.at(0)->constr_children.push_back(chain.at(i));
@@ -951,83 +778,64 @@ class Ecp5Packer
 
                 // Create RAMW slice
                 std::unique_ptr<CellInfo> ramw_slice =
-                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$RAMW_SLICE");
-                dram_to_ramw(ctx, ci, ramw_slice.get());
+                        create_ecp5_cell(ctx, id_TRELLIS_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
+                dram_to_ramw_split(ctx, ci, ramw_slice.get());
 
                 // Create actual RAM slices
-                std::unique_ptr<CellInfo> ram0_slice =
-                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM0_SLICE");
-                dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
-
-                std::unique_ptr<CellInfo> ram1_slice =
-                        create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM1_SLICE");
-                dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
+                std::unique_ptr<CellInfo> ram_comb[4];
+                for (int i = 0; i < 4; i++) {
+                    ram_comb[i] = create_ecp5_cell(ctx, id_TRELLIS_COMB,
+                                                   ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i));
+                    dram_to_comb(ctx, ci, ram_comb[i].get(), ramw_slice.get(), i);
+                }
+                // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
+                std::unique_ptr<CellInfo> ramw_block[2];
+                for (int i = 0; i < 2; i++) {
+                    ramw_block[i] = create_ecp5_cell(ctx, id_TRELLIS_COMB,
+                                                     ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
+                    ramw_block[i]->params[id_MODE] = std::string("RAMW_BLOCK");
+                }
 
                 // Disconnect ports of original cell after packing
                 ci->disconnectPort(id_WCK);
                 ci->disconnectPort(id_WRE);
 
-                ci->disconnectPort(ctx->id("RAD[0]"));
-                ci->disconnectPort(ctx->id("RAD[1]"));
-                ci->disconnectPort(ctx->id("RAD[2]"));
-                ci->disconnectPort(ctx->id("RAD[3]"));
-
-                // Attempt to pack FFs into RAM slices
-                std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
-                std::vector<CellInfo *> tile_ffs;
-                for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
-                    CellInfo *ff0 = nullptr;
-                    NetInfo *f0net = slice->ports.at(id_F0).net;
-                    if (f0net != nullptr) {
-                        ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
-                        if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
-                            if (can_pack_ff_dram(slice, ff0)) {
-                                ff_packing.push_back(std::make_tuple(ff0, slice, 0));
-                                tile_ffs.push_back(ff0);
-                                packed_cells.insert(ff0->name);
-                            }
-                        }
-                    }
-
-                    CellInfo *ff1 = nullptr;
-                    NetInfo *f1net = slice->ports.at(id_F1).net;
-                    if (f1net != nullptr) {
-                        ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
-                        if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
-                            can_add_ff_to_tile(tile_ffs, ff1)) {
-                            if (can_pack_ff_dram(slice, ff1)) {
-                                ff_packing.push_back(std::make_tuple(ff1, slice, 1));
-                                tile_ffs.push_back(ff1);
-                                packed_cells.insert(ff1->name);
-                            }
-                        }
-                    }
-                }
-
-                for (auto ff : ff_packing)
-                    ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
+                for (int i = 0; i < 4; i++)
+                    ci->disconnectPort(ctx->id(stringf("RAD[%d]", i)));
 
                 // Setup placement constraints
-                ram0_slice->constr_abs_z = true;
-                ram0_slice->constr_z = 0;
-                ram0_slice->cluster = ram0_slice->name;
-
-                ram1_slice->cluster = ram0_slice->name;
-                ram1_slice->constr_abs_z = true;
-                ram1_slice->constr_x = 0;
-                ram1_slice->constr_y = 0;
-                ram1_slice->constr_z = 1;
-                ram0_slice->constr_children.push_back(ram1_slice.get());
-
-                ramw_slice->cluster = ram0_slice->name;
+                // Use the 0th bit as an anchor
+                ram_comb[0]->constr_abs_z = true;
+                ram_comb[0]->constr_z = Arch::BEL_COMB;
+                ram_comb[0]->cluster = ram_comb[0]->name;
+                for (int i = 1; i < 4; i++) {
+                    ram_comb[i]->cluster = ram_comb[0]->name;
+                    ram_comb[i]->constr_abs_z = true;
+                    ram_comb[i]->constr_x = 0;
+                    ram_comb[i]->constr_y = 0;
+                    ram_comb[i]->constr_z = (i << ctx->lc_idx_shift) | Arch::BEL_COMB;
+                    ram_comb[0]->constr_children.push_back(ram_comb[i].get());
+                }
+                for (int i = 0; i < 2; i++) {
+                    ramw_block[i]->cluster = ram_comb[0]->name;
+                    ramw_block[i]->constr_abs_z = true;
+                    ramw_block[i]->constr_x = 0;
+                    ramw_block[i]->constr_y = 0;
+                    ramw_block[i]->constr_z = ((i + 4) << ctx->lc_idx_shift) | Arch::BEL_COMB;
+                    ram_comb[0]->constr_children.push_back(ramw_block[i].get());
+                }
+
+                ramw_slice->cluster = ram_comb[0]->name;
                 ramw_slice->constr_abs_z = true;
                 ramw_slice->constr_x = 0;
                 ramw_slice->constr_y = 0;
-                ramw_slice->constr_z = 2;
-                ram0_slice->constr_children.push_back(ramw_slice.get());
+                ramw_slice->constr_z = (4 << ctx->lc_idx_shift) | Arch::BEL_RAMW;
+                ram_comb[0]->constr_children.push_back(ramw_slice.get());
 
-                new_cells.push_back(std::move(ram0_slice));
-                new_cells.push_back(std::move(ram1_slice));
+                for (int i = 0; i < 4; i++)
+                    new_cells.push_back(std::move(ram_comb[i]));
+                for (int i = 0; i < 2; i++)
+                    new_cells.push_back(std::move(ramw_block[i]));
                 new_cells.push_back(std::move(ramw_slice));
                 packed_cells.insert(ci->name);
             }
@@ -1035,183 +843,6 @@ class Ecp5Packer
         flush_cells();
     }
 
-    // Pack LUTs that have been paired together
-    void pack_lut_pairs()
-    {
-        log_info("Packing paired LUTs into a SLICE...\n");
-        for (auto pair : lutPairs) {
-            CellInfo *lut0 = ctx->cells.at(pair.first).get();
-            CellInfo *lut1 = ctx->cells.at(pair.second).get();
-            std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, lut0->name.str(ctx) + "_SLICE");
-
-            lut_to_slice(ctx, lut0, slice.get(), 0);
-            lut_to_slice(ctx, lut1, slice.get(), 1);
-
-            auto ff0 = lutffPairs.find(lut0->name);
-
-            if (ff0 != lutffPairs.end()) {
-                ff_to_slice(ctx, ctx->cells.at(ff0->second).get(), slice.get(), 0, true);
-                packed_cells.insert(ff0->second);
-                fflutPairs.erase(ff0->second);
-                lutffPairs.erase(lut0->name);
-            }
-
-            auto ff1 = lutffPairs.find(lut1->name);
-
-            if (ff1 != lutffPairs.end()) {
-                ff_to_slice(ctx, ctx->cells.at(ff1->second).get(), slice.get(), 1, true);
-                packed_cells.insert(ff1->second);
-                fflutPairs.erase(ff1->second);
-                lutffPairs.erase(lut1->name);
-            }
-
-            new_cells.push_back(std::move(slice));
-            packed_cells.insert(lut0->name);
-            packed_cells.insert(lut1->name);
-        }
-        flush_cells();
-    }
-
-    // Pack single LUTs that weren't paired into their own slice,
-    // with an optional FF also
-    void pack_remaining_luts()
-    {
-        log_info("Packing unpaired LUTs into a SLICE...\n");
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_lut(ctx, ci)) {
-                std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
-                lut_to_slice(ctx, ci, slice.get(), 1);
-                auto ff = lutffPairs.find(ci->name);
-
-                if (ff != lutffPairs.end()) {
-                    ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true);
-                    packed_cells.insert(ff->second);
-                    fflutPairs.erase(ff->second);
-                    lutffPairs.erase(ci->name);
-                }
-
-                new_cells.push_back(std::move(slice));
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-    }
-
-    // Find a cell that meets some criteria near an origin cell
-    // Used for packing an FF into a nearby SLICE
-    template <typename TFunc> CellInfo *find_nearby_cell(CellInfo *origin, TFunc Func)
-    {
-        pool<CellInfo *, hash_ptr_ops> visited_cells;
-        std::queue<CellInfo *> to_visit;
-        visited_cells.insert(origin);
-        to_visit.push(origin);
-        int iter = 0;
-        while (!to_visit.empty() && iter < 10000) {
-            CellInfo *cursor = to_visit.front();
-            to_visit.pop();
-            if (Func(cursor))
-                return cursor;
-            for (const auto &port : cursor->ports) {
-                NetInfo *pn = port.second.net;
-                if (pn == nullptr)
-                    continue;
-                // Skip high-fanout nets that are unlikely to be relevant
-                if (pn->users.entries() > 25)
-                    continue;
-                // Add other ports on this net if not already visited
-                auto visit_port = [&](const PortRef &port) {
-                    if (port.cell == nullptr)
-                        return;
-                    if (visited_cells.count(port.cell))
-                        return;
-                    // If not already visited; add the cell of this port to the queue
-                    to_visit.push(port.cell);
-                    visited_cells.insert(port.cell);
-                };
-                visit_port(pn->driver);
-                for (const auto &usr : pn->users)
-                    visit_port(usr);
-            }
-            ++iter;
-        }
-        return nullptr;
-    }
-
-    // Pack flipflops that weren't paired with a LUT
-    float dense_pack_mode_thresh = 0.95f;
-    void pack_remaining_ffs()
-    {
-        // Enter dense flipflop packing mode once utilisation exceeds a threshold (default: 95%)
-        int used_slices = 0;
-        for (auto &cell : ctx->cells)
-            if (cell.second->type == id_TRELLIS_SLICE)
-                ++used_slices;
-
-        log_info("Packing unpaired FFs into a SLICE...\n");
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_ff(ctx, ci)) {
-                bool pack_dense = used_slices > (dense_pack_mode_thresh * available_slices);
-                bool requires_m = ci->getPort(id_M) != nullptr;
-                if (pack_dense && !requires_m) {
-                    // If dense packing threshold exceeded; always try and pack the FF into an existing slice
-                    // Find a SLICE with space "near" the flipflop in the netlist
-                    std::vector<CellInfo *> ltile;
-                    CellInfo *target = find_nearby_cell(ci, [&](CellInfo *cursor) {
-                        if (cursor->type != id_TRELLIS_SLICE)
-                            return false;
-                        if (cursor->cluster != ClusterId()) {
-                            auto &constr_children = ctx->cells.at(cursor->cluster)->constr_children;
-                            // Skip big chains for performance
-                            if (constr_children.size() > 8)
-                                return false;
-                            // Have to check the whole of the tile for legality when dealing with chains, not just slice
-                            ltile.clear();
-                            if (cursor->cluster != cursor->name)
-                                ltile.push_back(ctx->cells.at(cursor->cluster).get());
-                            else
-                                ltile.push_back(cursor);
-                            for (auto c : constr_children)
-                                ltile.push_back(c);
-                            if (!can_add_ff_to_tile(ltile, cursor))
-                                return false;
-                        }
-                        if (!can_add_ff_to_slice(cursor, ci))
-                            return false;
-                        for (int i = 0; i < 2; i++)
-                            if (is_ff_available(cursor, i))
-                                return true;
-                        return false;
-                    });
-
-                    // If found, add the FF to this slice instead of creating a new one
-                    if (target != nullptr) {
-                        for (int i = 0; i < 2; i++) {
-                            if (is_ff_available(target, i)) {
-                                ff_to_slice(ctx, ci, target, i, false);
-                                goto ff_packed;
-                            }
-                        }
-                    }
-
-                    if (false) {
-                    ff_packed:
-                        packed_cells.insert(ci->name);
-                        continue;
-                    }
-                }
-
-                std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
-                ff_to_slice(ctx, ci, slice.get(), 0, false);
-                new_cells.push_back(std::move(slice));
-                ++used_slices;
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-    }
-
     int make_init_with_const_input(int init, int input, bool value)
     {
         int new_init = 0;
@@ -1729,7 +1360,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_EXTREFB) {
-                const NetInfo *refo = net_or_nullptr(ci, id_REFCLKO);
+                const NetInfo *refo = ci->getPort(id_REFCLKO);
                 CellInfo *dcu = nullptr;
                 std::string loc_bel = std::string("NONE");
                 std::string dcu_bel = std::string("NONE");
@@ -1785,7 +1416,7 @@ class Ecp5Packer
                     ci->attrs[id_BEL] = dcu_bel;
                 }
             } else if (ci->type == id_PCSCLKDIV) {
-                const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+                const NetInfo *clki = ci->getPort(id_CLKI);
                 if (clki != nullptr && clki->driver.cell != nullptr && clki->driver.cell->type == id_DCUA) {
                     CellInfo *dcu = clki->driver.cell;
                     if (!dcu->attrs.count(id_BEL))
@@ -1842,7 +1473,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_EHXPLLL && !ci->attrs.count(id_BEL)) {
-                const NetInfo *drivernet = net_or_nullptr(ci, id_CLKI);
+                const NetInfo *drivernet = ci->getPort(id_CLKI);
                 if (drivernet == nullptr || drivernet->driver.cell == nullptr)
                     continue;
                 const CellInfo *drivercell = drivernet->driver.cell;
@@ -2079,7 +1710,7 @@ class Ecp5Packer
                      {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0,
                       id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3,
                       id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) {
-                    if (net_or_nullptr(ci, zport) == nullptr)
+                    if (ci->getPort(zport) == nullptr)
                         tie_zero(ci, zport);
                 }
             }
@@ -2778,7 +2409,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_CLKDIVF) {
-                const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+                const NetInfo *clki = ci->getPort(id_CLKI);
                 for (auto &eclk : eclks) {
                     if (eclk.second.unbuf == clki) {
                         for (auto bel : ctx->getBels()) {
@@ -2800,8 +2431,8 @@ class Ecp5Packer
             clkdiv_done:
                 continue;
             } else if (ci->type == id_ECLKSYNCB) {
-                const NetInfo *eclki = net_or_nullptr(ci, id_ECLKI);
-                const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
+                const NetInfo *eclki = ci->getPort(id_ECLKI);
+                const NetInfo *eclko = ci->getPort(id_ECLKO);
                 if (eclki != nullptr && eclki->driver.cell != nullptr) {
                     if (eclki->driver.cell->type == id_ECLKBRIDGECS) {
                         BelId bel = ctx->getBelByNameStr(eclki->driver.cell->attrs.at(id_BEL).as_string());
@@ -2833,13 +2464,13 @@ class Ecp5Packer
                 continue;
             } else if (ci->type == id_DDRDLLA) {
                 ci->type = id_DDRDLL; // transform from Verilog to Bel name
-                const NetInfo *clk = net_or_nullptr(ci, id_CLK);
+                const NetInfo *clk = ci->getPort(id_CLK);
                 if (clk == nullptr)
                     log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx));
 
                 bool left_bank_users = false, right_bank_users = false;
                 // Check which side the delay codes (DDRDEL) are used on
-                const NetInfo *ddrdel = net_or_nullptr(ci, id_DDRDEL);
+                const NetInfo *ddrdel = ci->getPort(id_DDRDEL);
                 if (ddrdel != nullptr) {
                     for (auto &usr : ddrdel->users) {
                         const CellInfo *uc = usr.cell;
@@ -2922,7 +2553,7 @@ class Ecp5Packer
                     continue;
                 // Case of a CLKDIVF driven by an ECLKSYNC constrained above; without the input being used elsewhere as
                 // an edge clock
-                const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+                const NetInfo *clki = ci->getPort(id_CLKI);
                 if (clki == nullptr || clki->driver.cell == nullptr)
                     continue;
                 CellInfo *drv = clki->driver.cell;
@@ -3131,12 +2762,9 @@ class Ecp5Packer
         pack_constants();
         pack_dram();
         pack_carries();
-        find_lutff_pairs();
+        pack_luts();
         pack_lut5xs();
-        pair_luts();
-        pack_lut_pairs();
-        pack_remaining_luts();
-        pack_remaining_ffs();
+        pack_ffs();
         generate_constraints();
         promote_ecp5_globals(ctx);
         ctx->fixupHierarchy();
@@ -3180,122 +2808,147 @@ bool Arch::pack()
     }
 }
 
-void Arch::assignArchInfo()
+void Arch::assign_arch_info_for_cell(CellInfo *ci)
 {
-    for (auto &cell : cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->type == id_TRELLIS_SLICE) {
-
-            ci->sliceInfo.using_dff = false;
-            if (ci->ports.count(id_Q0) && ci->ports[id_Q0].net != nullptr)
-                ci->sliceInfo.using_dff = true;
-            if (ci->ports.count(id_Q1) && ci->ports[id_Q1].net != nullptr)
-                ci->sliceInfo.using_dff = true;
-
-            if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr)
-                ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name;
-            else
-                ci->sliceInfo.clk_sig = IdString();
+    auto get_port_net = [&](CellInfo *ci, IdString p) {
+        NetInfo *n = get_net_or_empty(ci, p);
+        return n ? n->name : IdString();
+    };
+    if (ci->type == id_TRELLIS_COMB) {
+        std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+        ci->combInfo.flags = ArchCellInfo::COMB_NONE;
+        if (mode == "CCU2")
+            ci->combInfo.flags |= ArchCellInfo::COMB_CARRY;
+        if (mode == "DPRAM") {
+            ci->combInfo.flags |= ArchCellInfo::COMB_LUTRAM;
+            std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+            if (wckmux == "INV")
+                ci->combInfo.flags |= ArchCellInfo::COMB_RAM_WCKINV;
+            std::string wremux = str_or_default(ci->params, id_WREMUX, "WRE");
+            if (wremux == "INV" || wremux == "0")
+                ci->combInfo.flags |= ArchCellInfo::COMB_RAM_WREINV;
+            ci->combInfo.ram_wck = get_port_net(ci, id_WCK);
+            ci->combInfo.ram_wre = get_port_net(ci, id_WRE);
+        }
+        if (mode == "RAMW_BLOCK")
+            ci->combInfo.flags |= ArchCellInfo::COMB_RAMW_BLOCK;
+        if (ci->getPort(id_F1) != nullptr)
+            ci->combInfo.flags |= ArchCellInfo::COMB_MUX5;
+        if (ci->getPort(id_FXA) != nullptr || ci->getPort(id_FXB) != nullptr) {
+            ci->combInfo.flags |= ArchCellInfo::COMB_MUX6;
+            NetInfo *fxa = ci->getPort(id_FXA);
+            if (fxa != nullptr)
+                ci->combInfo.mux_fxad = fxa->driver.cell;
+        }
+    } else if (ci->type == id_TRELLIS_FF) {
+        ci->ffInfo.flags = ArchCellInfo::FF_NONE;
+        if (str_or_default(ci->params, id_GSR, "ENABLED") == "ENABLED")
+            ci->ffInfo.flags |= ArchCellInfo::FF_GSREN;
+        if (str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE") == "ASYNC")
+            ci->ffInfo.flags |= ArchCellInfo::FF_ASYNC;
+        if (ci->getPort(id_M) != nullptr)
+            ci->ffInfo.flags |= ArchCellInfo::FF_M_USED;
+        std::string clkmux = str_or_default(ci->params, id_CLKMUX, "CLK");
+        std::string cemux = str_or_default(ci->params, id_CEMUX, "CE");
+        std::string lsrmux = str_or_default(ci->params, id_LSRMUX, "LSR");
+        if (clkmux == "INV" || clkmux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CLKINV;
+        if (cemux == "INV" || cemux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CEINV;
+        if (cemux == "1" || cemux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CECONST;
+        if (lsrmux == "INV")
+            ci->ffInfo.flags |= ArchCellInfo::FF_LSRINV;
+        ci->ffInfo.clk_sig = get_port_net(ci, id_CLK);
+        ci->ffInfo.ce_sig = get_port_net(ci, id_CE);
+        ci->ffInfo.lsr_sig = get_port_net(ci, id_LSR);
+    } else if (ci->type == id_DP16KD) {
+        ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 36);
+
+        // Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
+        std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
+        if (regmode_a != "NOREG" && regmode_a != "OUTREG")
+            log_error("DP16KD %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this), regmode_a.c_str());
+        std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
+        if (regmode_b != "NOREG" && regmode_b != "OUTREG")
+            log_error("DP16KD %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this), regmode_b.c_str());
+        ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
+        ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
+
+        // Based on the REGMODE, we have different timing lookup tables.
+        if (!ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG;
+        } else if (!ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG;
+        } else if (ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG;
+        } else if (ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
+        }
+    } else if (ci->type == id_MULT18X18D) {
+        // For the multiplier block, our timing db is dictated by whether any of the input/output registers are
+        // enabled. To that end, we need to work out what the parameters are for the INPUTA_CLK, INPUTB_CLK and
+        // OUTPUT_CLK are.
+        // The clock check is the same IN_A/B and OUT, so hoist it to a function
+        auto get_clock_parameter = [&](std::string param_name) {
+            std::string clk = str_or_default(ci->params, id(param_name), "NONE");
+            if (clk != "NONE" && clk != "CLK0" && clk != "CLK1" && clk != "CLK2" && clk != "CLK3")
+                log_error("MULT18X18D %s has invalid %s configuration '%s'\n", ci->name.c_str(this), param_name.c_str(),
+                          clk.c_str());
+            return clk;
+        };
 
-            if (ci->ports.count(id_LSR) && ci->ports[id_LSR].net != nullptr)
-                ci->sliceInfo.lsr_sig = ci->ports[id_LSR].net->name;
-            else
-                ci->sliceInfo.lsr_sig = IdString();
-
-            ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
-            ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
-            ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
-            ci->sliceInfo.is_carry = (mode == "CCU2");
-            ci->sliceInfo.is_memory = (mode == "DPRAM" || mode == "RAMW");
-            ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id_REG0_SD, "0"));
-            ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id_REG1_SD, "0"));
-            ci->sliceInfo.has_l6mux = false;
-            if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
-                ci->ports[id_FXA].net->driver.port == id_OFX0)
-                ci->sliceInfo.has_l6mux = true;
-        } else if (ci->type == id_DP16KD) {
-            ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 36);
-
-            // Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
-            std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
-            if (regmode_a != "NOREG" && regmode_a != "OUTREG")
-                log_error("DP16KD %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this),
-                          regmode_a.c_str());
-            std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
-            if (regmode_b != "NOREG" && regmode_b != "OUTREG")
-                log_error("DP16KD %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this),
-                          regmode_b.c_str());
-            ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
-            ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
-
-            // Based on the REGMODE, we have different timing lookup tables.
-            if (!ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
-                ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG;
-            } else if (!ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
-                ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG;
-            } else if (ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
-                ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG;
-            } else if (ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
-                ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
-            }
-        } else if (ci->type == id_MULT18X18D) {
-            // For the multiplier block, our timing db is dictated by whether any of the input/output registers are
-            // enabled. To that end, we need to work out what the parameters are for the INPUTA_CLK, INPUTB_CLK and
-            // OUTPUT_CLK are.
-            // The clock check is the same IN_A/B and OUT, so hoist it to a function
-            auto get_clock_parameter = [&](std::string param_name) {
-                std::string clk = str_or_default(ci->params, id(param_name), "NONE");
-                if (clk != "NONE" && clk != "CLK0" && clk != "CLK1" && clk != "CLK2" && clk != "CLK3")
-                    log_error("MULT18X18D %s has invalid %s configuration '%s'\n", ci->name.c_str(this),
-                              param_name.c_str(), clk.c_str());
-                return clk;
-            };
-
-            // Get the input clock setting from the cell
-            std::string reg_inputa_clk = get_clock_parameter("REG_INPUTA_CLK");
-            std::string reg_inputb_clk = get_clock_parameter("REG_INPUTB_CLK");
-
-            // Inputs are registered IFF the REG_INPUT value is not NONE
-            const bool is_in_a_registered = reg_inputa_clk != "NONE";
-            const bool is_in_b_registered = reg_inputb_clk != "NONE";
-
-            // Similarly, get the output register clock
-            std::string reg_output_clk = get_clock_parameter("REG_OUTPUT_CLK");
-            const bool is_output_registered = reg_output_clk != "NONE";
-
-            // If only one of the inputs is registered, we are going to treat that as
-            // neither input registered so that we don't have to deal with mixed timing.
-            // Emit a warning to that effect.
-            const bool any_input_registered = is_in_a_registered || is_in_b_registered;
-            const bool both_inputs_registered = is_in_a_registered && is_in_b_registered;
-            const bool input_registers_mismatched = any_input_registered && !both_inputs_registered;
-            if (input_registers_mismatched) {
-                log_warning("MULT18X18D %s has unsupported mixed input register modes (reg_inputa_clk=%s, "
-                            "reg_inputb_clk=%s)\n",
-                            ci->name.c_str(this), reg_inputa_clk.c_str(), reg_inputb_clk.c_str());
-                log_warning("Timings for MULT18X18D %s will be calculated as though neither input were registered\n",
-                            ci->name.c_str(this));
-
-                // Act as though the inputs are unregistered, so select timing DB based only on the
-                // output register mode
-                ci->multInfo.timing_id = is_output_registered ? id_MULT18X18D_REGS_OUTPUT : id_MULT18X18D_REGS_NONE;
-            } else {
-                // Based on our register settings, pick the timing data to use for this cell
-                if (!both_inputs_registered && !is_output_registered) {
-                    ci->multInfo.timing_id = id_MULT18X18D_REGS_NONE;
-                } else if (both_inputs_registered && !is_output_registered) {
-                    ci->multInfo.timing_id = id_MULT18X18D_REGS_INPUT;
-                } else if (!both_inputs_registered && is_output_registered) {
-                    ci->multInfo.timing_id = id_MULT18X18D_REGS_OUTPUT;
-                } else if (both_inputs_registered && is_output_registered) {
-                    ci->multInfo.timing_id = id_MULT18X18D_REGS_ALL;
-                }
+        // Get the input clock setting from the cell
+        std::string reg_inputa_clk = get_clock_parameter("REG_INPUTA_CLK");
+        std::string reg_inputb_clk = get_clock_parameter("REG_INPUTB_CLK");
+
+        // Inputs are registered IFF the REG_INPUT value is not NONE
+        const bool is_in_a_registered = reg_inputa_clk != "NONE";
+        const bool is_in_b_registered = reg_inputb_clk != "NONE";
+
+        // Similarly, get the output register clock
+        std::string reg_output_clk = get_clock_parameter("REG_OUTPUT_CLK");
+        const bool is_output_registered = reg_output_clk != "NONE";
+
+        // If only one of the inputs is registered, we are going to treat that as
+        // neither input registered so that we don't have to deal with mixed timing.
+        // Emit a warning to that effect.
+        const bool any_input_registered = is_in_a_registered || is_in_b_registered;
+        const bool both_inputs_registered = is_in_a_registered && is_in_b_registered;
+        const bool input_registers_mismatched = any_input_registered && !both_inputs_registered;
+        if (input_registers_mismatched) {
+            log_warning("MULT18X18D %s has unsupported mixed input register modes (reg_inputa_clk=%s, "
+                        "reg_inputb_clk=%s)\n",
+                        ci->name.c_str(this), reg_inputa_clk.c_str(), reg_inputb_clk.c_str());
+            log_warning("Timings for MULT18X18D %s will be calculated as though neither input were registered\n",
+                        ci->name.c_str(this));
+
+            // Act as though the inputs are unregistered, so select timing DB based only on the
+            // output register mode
+            ci->multInfo.timing_id = is_output_registered ? id_MULT18X18D_REGS_OUTPUT : id_MULT18X18D_REGS_NONE;
+        } else {
+            // Based on our register settings, pick the timing data to use for this cell
+            if (!both_inputs_registered && !is_output_registered) {
+                ci->multInfo.timing_id = id_MULT18X18D_REGS_NONE;
+            } else if (both_inputs_registered && !is_output_registered) {
+                ci->multInfo.timing_id = id_MULT18X18D_REGS_INPUT;
+            } else if (!both_inputs_registered && is_output_registered) {
+                ci->multInfo.timing_id = id_MULT18X18D_REGS_OUTPUT;
+            } else if (both_inputs_registered && is_output_registered) {
+                ci->multInfo.timing_id = id_MULT18X18D_REGS_ALL;
             }
-            // If we aren't a pure combinatorial multiplier, then our timings are
-            // calculated with respect to CLK0
-            ci->multInfo.is_clocked = ci->multInfo.timing_id != id_MULT18X18D_REGS_NONE;
         }
+        // If we aren't a pure combinatorial multiplier, then our timings are
+        // calculated with respect to CLK0
+        ci->multInfo.is_clocked = ci->multInfo.timing_id != id_MULT18X18D_REGS_NONE;
+    }
+}
+
+void Arch::assignArchInfo()
+{
+    for (auto &cell : cells) {
+        CellInfo *ci = cell.second.get();
+        assign_arch_info_for_cell(ci);
     }
     for (auto &net : nets) {
         net.second->is_global = bool_or_default(net.second->attrs, id_ECP5_IS_GLOBAL);
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index a586db7b90..1554ea1a0c 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -311,6 +311,64 @@ def process_loc_globals(chip):
 }
 
 
+delay_db = {}
+# Convert from Lattice-style grouped SLICE to new nextpnr split style SLICE
+def postprocess_timing_data(cells):
+    def delay_diff(x, y):
+        return (x[0] - y[0], x[1] - y[1])
+
+    split_cells = {}
+    comb_delays = {}
+    comb_delays[("A", "F")] = delay_db["SLOGICB"][("A0", "F0")]
+    comb_delays[("B", "F")] = delay_db["SLOGICB"][("B0", "F0")]
+    comb_delays[("C", "F")] = delay_db["SLOGICB"][("C0", "F0")]
+    comb_delays[("D", "F")] = delay_db["SLOGICB"][("D0", "F0")]
+    comb_delays[("A", "OFX")] = delay_db["SLOGICB"][("A0", "OFX0")]
+    comb_delays[("B", "OFX")] = delay_db["SLOGICB"][("B0", "OFX0")]
+    comb_delays[("C", "OFX")] = delay_db["SLOGICB"][("C0", "OFX0")]
+    comb_delays[("D", "OFX")] = delay_db["SLOGICB"][("D0", "OFX0")]
+    comb_delays[("M", "OFX")] = delay_db["SLOGICB"][("M0", "OFX0")] # worst case
+    comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLOGICB"][("A1", "OFX0")],
+                                            delay_db["SLOGICB"][("A1", "F1")])
+    comb_delays[("FXA", "OFX")] = delay_db["SLOGICB"][("FXA", "OFX1")]
+    comb_delays[("FXB", "OFX")] = delay_db["SLOGICB"][("FXB", "OFX1")]
+    split_cells["TRELLIS_COMB"] = comb_delays
+
+    carry0_delays = {}
+    carry0_delays[("A", "F")] = delay_db["SCCU2C"][("A0", "F0")]
+    carry0_delays[("B", "F")] = delay_db["SCCU2C"][("B0", "F0")]
+    carry0_delays[("C", "F")] = delay_db["SCCU2C"][("C0", "F0")]
+    carry0_delays[("D", "F")] = delay_db["SCCU2C"][("D0", "F0")]
+    carry0_delays[("A", "FCO")] = delay_db["SCCU2C"][("A0", "FCO")]
+    carry0_delays[("B", "FCO")] = delay_db["SCCU2C"][("B0", "FCO")]
+    carry0_delays[("C", "FCO")] = delay_db["SCCU2C"][("C0", "FCO")]
+    carry0_delays[("D", "FCO")] = delay_db["SCCU2C"][("D0", "FCO")]
+    carry0_delays[("FCI", "F")] = delay_db["SCCU2C"][("FCI", "F0")]
+    carry0_delays[("FCI", "FCO")] = delay_db["SCCU2C"][("FCI", "FCO")]
+
+    split_cells["TRELLIS_COMB_CARRY0"] = carry0_delays
+
+    carry1_delays = {}
+    carry1_delays[("A", "F")] = delay_db["SCCU2C"][("A1", "F1")]
+    carry1_delays[("B", "F")] = delay_db["SCCU2C"][("B1", "F1")]
+    carry1_delays[("C", "F")] = delay_db["SCCU2C"][("C1", "F1")]
+    carry1_delays[("D", "F")] = delay_db["SCCU2C"][("D1", "F1")]
+    carry1_delays[("A", "FCO")] = delay_db["SCCU2C"][("A1", "FCO")]
+    carry1_delays[("B", "FCO")] = delay_db["SCCU2C"][("B1", "FCO")]
+    carry1_delays[("C", "FCO")] = delay_db["SCCU2C"][("C1", "FCO")]
+    carry1_delays[("D", "FCO")] = delay_db["SCCU2C"][("D1", "FCO")]
+    carry1_delays[("FCI", "F")] = delay_diff(delay_db["SCCU2C"][("FCI", "F1")], delay_db["SCCU2C"][("FCI", "FCO")])
+    carry1_delays[("FCI", "FCO")] = (0, 0)
+
+    split_cells["TRELLIS_COMB_CARRY1"] = carry1_delays
+
+    for celltype, celldelays in sorted(split_cells.items()):
+        delays = []
+        setupholds = []
+        for (from_pin, to_pin), (min_delay, max_delay) in sorted(celldelays.items()):
+            delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
+        cells.append((constids[celltype], delays, setupholds))
+
 def process_timing_data():
     for grade in speed_grade_names:
         with open(timing_dbs.cells_db_path("ECP5", grade)) as f:
@@ -320,6 +378,7 @@ def process_timing_data():
             celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
             delays = []
             setupholds = []
+            delay_db[cell] = {}
             for entry in cdata:
                 if entry["type"] == "Width":
                     continue
@@ -332,6 +391,7 @@ def process_timing_data():
                         to_pin = timing_port_xform[to_pin]
                     min_delay = min(entry["rising"][0], entry["falling"][0])
                     max_delay = min(entry["rising"][2], entry["falling"][2])
+                    delay_db[cell][(from_pin, to_pin)] = (min_delay, max_delay)
                     delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
                 elif entry["type"] == "SetupHold":
                     if type(entry["pin"]) is list:
@@ -346,6 +406,7 @@ def process_timing_data():
                 else:
                     assert False, entry["type"]
             cells.append((celltype, delays, setupholds))
+        postprocess_timing_data(cells)
         pip_class_delays = []
         for i in range(len(pip_class_to_idx)):
             pip_class_delays.append((50, 50, 0, 0))
@@ -625,7 +686,7 @@ def main():
     # print("Initialising chip...")
     chip = pytrellis.Chip(dev_names[args.device])
     # print("Building routing graph...")
-    ddrg = pytrellis.make_dedup_chipdb(chip, include_lutperm_pips=True)
+    ddrg = pytrellis.make_dedup_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_timing_data()

From 49f178ed94b5fad00d25dbd12adea0bf4732f803 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 8 Apr 2022 13:42:54 +0100
Subject: [PATCH 130/712] Split up common into kernel,place,route

Signed-off-by: gatecat <gatecat@ds0.me>
---
 CMakeLists.txt                                    | 9 ++++++---
 common/{ => kernel}/arch_api.h                    | 0
 common/{ => kernel}/arch_pybindings_shared.h      | 0
 common/{ => kernel}/archcheck.cc                  | 0
 common/{ => kernel}/base_arch.h                   | 0
 common/{ => kernel}/base_clusterinfo.h            | 0
 common/{ => kernel}/basectx.cc                    | 0
 common/{ => kernel}/basectx.h                     | 0
 common/{ => kernel}/bits.cc                       | 0
 common/{ => kernel}/bits.h                        | 0
 common/{ => kernel}/chain_utils.h                 | 0
 common/{ => kernel}/command.cc                    | 0
 common/{ => kernel}/command.h                     | 0
 common/{ => kernel}/constraints.h                 | 0
 common/{ => kernel}/constraints.impl.h            | 0
 common/{ => kernel}/context.cc                    | 0
 common/{ => kernel}/context.h                     | 0
 common/{ => kernel}/design_utils.cc               | 0
 common/{ => kernel}/design_utils.h                | 0
 common/{ => kernel}/deterministic_rng.h           | 0
 common/{ => kernel}/dynamic_bitarray.h            | 0
 common/{ => kernel}/embed.cc                      | 0
 common/{ => kernel}/embed.h                       | 0
 common/{ => kernel}/exclusive_state_groups.h      | 0
 common/{ => kernel}/exclusive_state_groups.impl.h | 0
 common/{ => kernel}/handle_error.cc               | 0
 common/{ => kernel}/hashlib.h                     | 0
 common/{ => kernel}/idstring.cc                   | 0
 common/{ => kernel}/idstring.h                    | 0
 common/{ => kernel}/idstringlist.cc               | 0
 common/{ => kernel}/idstringlist.h                | 0
 common/{ => kernel}/indexed_store.h               | 0
 common/{ => kernel}/log.cc                        | 0
 common/{ => kernel}/log.h                         | 0
 common/{ => kernel}/nextpnr.cc                    | 0
 common/{ => kernel}/nextpnr.h                     | 0
 common/{ => kernel}/nextpnr_assertions.cc         | 0
 common/{ => kernel}/nextpnr_assertions.h          | 0
 common/{ => kernel}/nextpnr_base_types.h          | 0
 common/{ => kernel}/nextpnr_namespaces.cc         | 0
 common/{ => kernel}/nextpnr_namespaces.h          | 0
 common/{ => kernel}/nextpnr_types.cc              | 0
 common/{ => kernel}/nextpnr_types.h               | 0
 common/{ => kernel}/property.cc                   | 0
 common/{ => kernel}/property.h                    | 0
 common/{ => kernel}/pybindings.cc                 | 0
 common/{ => kernel}/pybindings.h                  | 0
 common/{ => kernel}/pycontainers.h                | 0
 common/{ => kernel}/pywrappers.h                  | 0
 common/{ => kernel}/relptr.h                      | 0
 common/{ => kernel}/report.cc                     | 0
 common/{ => kernel}/scope_lock.h                  | 0
 common/{ => kernel}/sdf.cc                        | 0
 common/{ => kernel}/sso_array.h                   | 0
 common/{ => kernel}/str_ring_buffer.cc            | 0
 common/{ => kernel}/str_ring_buffer.h             | 0
 common/{ => kernel}/svg.cc                        | 0
 common/{ => kernel}/timing.cc                     | 0
 common/{ => kernel}/timing.h                      | 0
 common/{ => kernel}/util.h                        | 0
 common/{ => place}/fast_bels.h                    | 0
 common/{ => place}/parallel_refine.cc             | 0
 common/{ => place}/parallel_refine.h              | 0
 common/{ => place}/place_common.cc                | 0
 common/{ => place}/place_common.h                 | 0
 common/{ => place}/placer1.cc                     | 0
 common/{ => place}/placer1.h                      | 0
 common/{ => place}/placer_heap.cc                 | 0
 common/{ => place}/placer_heap.h                  | 0
 common/{ => place}/timing_opt.cc                  | 0
 common/{ => place}/timing_opt.h                   | 0
 common/{ => route}/router1.cc                     | 0
 common/{ => route}/router1.h                      | 0
 common/{ => route}/router2.cc                     | 0
 common/{ => route}/router2.h                      | 0
 75 files changed, 6 insertions(+), 3 deletions(-)
 rename common/{ => kernel}/arch_api.h (100%)
 rename common/{ => kernel}/arch_pybindings_shared.h (100%)
 rename common/{ => kernel}/archcheck.cc (100%)
 rename common/{ => kernel}/base_arch.h (100%)
 rename common/{ => kernel}/base_clusterinfo.h (100%)
 rename common/{ => kernel}/basectx.cc (100%)
 rename common/{ => kernel}/basectx.h (100%)
 rename common/{ => kernel}/bits.cc (100%)
 rename common/{ => kernel}/bits.h (100%)
 rename common/{ => kernel}/chain_utils.h (100%)
 rename common/{ => kernel}/command.cc (100%)
 rename common/{ => kernel}/command.h (100%)
 rename common/{ => kernel}/constraints.h (100%)
 rename common/{ => kernel}/constraints.impl.h (100%)
 rename common/{ => kernel}/context.cc (100%)
 rename common/{ => kernel}/context.h (100%)
 rename common/{ => kernel}/design_utils.cc (100%)
 rename common/{ => kernel}/design_utils.h (100%)
 rename common/{ => kernel}/deterministic_rng.h (100%)
 rename common/{ => kernel}/dynamic_bitarray.h (100%)
 rename common/{ => kernel}/embed.cc (100%)
 rename common/{ => kernel}/embed.h (100%)
 rename common/{ => kernel}/exclusive_state_groups.h (100%)
 rename common/{ => kernel}/exclusive_state_groups.impl.h (100%)
 rename common/{ => kernel}/handle_error.cc (100%)
 rename common/{ => kernel}/hashlib.h (100%)
 rename common/{ => kernel}/idstring.cc (100%)
 rename common/{ => kernel}/idstring.h (100%)
 rename common/{ => kernel}/idstringlist.cc (100%)
 rename common/{ => kernel}/idstringlist.h (100%)
 rename common/{ => kernel}/indexed_store.h (100%)
 rename common/{ => kernel}/log.cc (100%)
 rename common/{ => kernel}/log.h (100%)
 rename common/{ => kernel}/nextpnr.cc (100%)
 rename common/{ => kernel}/nextpnr.h (100%)
 rename common/{ => kernel}/nextpnr_assertions.cc (100%)
 rename common/{ => kernel}/nextpnr_assertions.h (100%)
 rename common/{ => kernel}/nextpnr_base_types.h (100%)
 rename common/{ => kernel}/nextpnr_namespaces.cc (100%)
 rename common/{ => kernel}/nextpnr_namespaces.h (100%)
 rename common/{ => kernel}/nextpnr_types.cc (100%)
 rename common/{ => kernel}/nextpnr_types.h (100%)
 rename common/{ => kernel}/property.cc (100%)
 rename common/{ => kernel}/property.h (100%)
 rename common/{ => kernel}/pybindings.cc (100%)
 rename common/{ => kernel}/pybindings.h (100%)
 rename common/{ => kernel}/pycontainers.h (100%)
 rename common/{ => kernel}/pywrappers.h (100%)
 rename common/{ => kernel}/relptr.h (100%)
 rename common/{ => kernel}/report.cc (100%)
 rename common/{ => kernel}/scope_lock.h (100%)
 rename common/{ => kernel}/sdf.cc (100%)
 rename common/{ => kernel}/sso_array.h (100%)
 rename common/{ => kernel}/str_ring_buffer.cc (100%)
 rename common/{ => kernel}/str_ring_buffer.h (100%)
 rename common/{ => kernel}/svg.cc (100%)
 rename common/{ => kernel}/timing.cc (100%)
 rename common/{ => kernel}/timing.h (100%)
 rename common/{ => kernel}/util.h (100%)
 rename common/{ => place}/fast_bels.h (100%)
 rename common/{ => place}/parallel_refine.cc (100%)
 rename common/{ => place}/parallel_refine.h (100%)
 rename common/{ => place}/place_common.cc (100%)
 rename common/{ => place}/place_common.h (100%)
 rename common/{ => place}/placer1.cc (100%)
 rename common/{ => place}/placer1.h (100%)
 rename common/{ => place}/placer_heap.cc (100%)
 rename common/{ => place}/placer_heap.h (100%)
 rename common/{ => place}/timing_opt.cc (100%)
 rename common/{ => place}/timing_opt.h (100%)
 rename common/{ => route}/router1.cc (100%)
 rename common/{ => route}/router1.h (100%)
 rename common/{ => route}/router2.cc (100%)
 rename common/{ => route}/router2.h (100%)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index fcbbbb13fe..89bdb3607c 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -216,7 +216,7 @@ configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/common/version.h.in ${CMAKE_CURRENT_BINARY_DIR}/generated/version.h
 )
 
-include_directories(common/ json/ frontend/ 3rdparty/json11/ 3rdparty/pybind11/include ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
+include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ 3rdparty/pybind11/include ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
 
 if(BUILD_HEAP)
     find_package (Eigen3 REQUIRED NO_MODULE)
@@ -225,12 +225,15 @@ if(BUILD_HEAP)
     add_definitions(-DWITH_HEAP)
 endif()
 
-aux_source_directory(common/ COMMON_SRC_FILES)
+aux_source_directory(common/kernel/ KERNEL_SRC_FILES)
+aux_source_directory(common/place/ PLACE_SRC_FILES)
+aux_source_directory(common/route/ ROUTE_SRC_FILES)
+
 aux_source_directory(json/ JSON_PARSER_FILES)
 aux_source_directory(3rdparty/json11 EXT_JSON11_FILES)
 aux_source_directory(frontend/ FRONTEND_FILES)
 
-set(COMMON_FILES ${COMMON_SRC_FILES} ${EXT_JSON11_FILES} ${JSON_PARSER_FILES} ${FRONTEND_FILES})
+set(COMMON_FILES ${KERNEL_SRC_FILES} ${PLACE_SRC_FILES} ${ROUTE_SRC_FILES} ${EXT_JSON11_FILES} ${JSON_PARSER_FILES} ${FRONTEND_FILES})
 if( NOT CMAKE_BUILD_TYPE )
     set(CMAKE_BUILD_TYPE Release)
 endif()
diff --git a/common/arch_api.h b/common/kernel/arch_api.h
similarity index 100%
rename from common/arch_api.h
rename to common/kernel/arch_api.h
diff --git a/common/arch_pybindings_shared.h b/common/kernel/arch_pybindings_shared.h
similarity index 100%
rename from common/arch_pybindings_shared.h
rename to common/kernel/arch_pybindings_shared.h
diff --git a/common/archcheck.cc b/common/kernel/archcheck.cc
similarity index 100%
rename from common/archcheck.cc
rename to common/kernel/archcheck.cc
diff --git a/common/base_arch.h b/common/kernel/base_arch.h
similarity index 100%
rename from common/base_arch.h
rename to common/kernel/base_arch.h
diff --git a/common/base_clusterinfo.h b/common/kernel/base_clusterinfo.h
similarity index 100%
rename from common/base_clusterinfo.h
rename to common/kernel/base_clusterinfo.h
diff --git a/common/basectx.cc b/common/kernel/basectx.cc
similarity index 100%
rename from common/basectx.cc
rename to common/kernel/basectx.cc
diff --git a/common/basectx.h b/common/kernel/basectx.h
similarity index 100%
rename from common/basectx.h
rename to common/kernel/basectx.h
diff --git a/common/bits.cc b/common/kernel/bits.cc
similarity index 100%
rename from common/bits.cc
rename to common/kernel/bits.cc
diff --git a/common/bits.h b/common/kernel/bits.h
similarity index 100%
rename from common/bits.h
rename to common/kernel/bits.h
diff --git a/common/chain_utils.h b/common/kernel/chain_utils.h
similarity index 100%
rename from common/chain_utils.h
rename to common/kernel/chain_utils.h
diff --git a/common/command.cc b/common/kernel/command.cc
similarity index 100%
rename from common/command.cc
rename to common/kernel/command.cc
diff --git a/common/command.h b/common/kernel/command.h
similarity index 100%
rename from common/command.h
rename to common/kernel/command.h
diff --git a/common/constraints.h b/common/kernel/constraints.h
similarity index 100%
rename from common/constraints.h
rename to common/kernel/constraints.h
diff --git a/common/constraints.impl.h b/common/kernel/constraints.impl.h
similarity index 100%
rename from common/constraints.impl.h
rename to common/kernel/constraints.impl.h
diff --git a/common/context.cc b/common/kernel/context.cc
similarity index 100%
rename from common/context.cc
rename to common/kernel/context.cc
diff --git a/common/context.h b/common/kernel/context.h
similarity index 100%
rename from common/context.h
rename to common/kernel/context.h
diff --git a/common/design_utils.cc b/common/kernel/design_utils.cc
similarity index 100%
rename from common/design_utils.cc
rename to common/kernel/design_utils.cc
diff --git a/common/design_utils.h b/common/kernel/design_utils.h
similarity index 100%
rename from common/design_utils.h
rename to common/kernel/design_utils.h
diff --git a/common/deterministic_rng.h b/common/kernel/deterministic_rng.h
similarity index 100%
rename from common/deterministic_rng.h
rename to common/kernel/deterministic_rng.h
diff --git a/common/dynamic_bitarray.h b/common/kernel/dynamic_bitarray.h
similarity index 100%
rename from common/dynamic_bitarray.h
rename to common/kernel/dynamic_bitarray.h
diff --git a/common/embed.cc b/common/kernel/embed.cc
similarity index 100%
rename from common/embed.cc
rename to common/kernel/embed.cc
diff --git a/common/embed.h b/common/kernel/embed.h
similarity index 100%
rename from common/embed.h
rename to common/kernel/embed.h
diff --git a/common/exclusive_state_groups.h b/common/kernel/exclusive_state_groups.h
similarity index 100%
rename from common/exclusive_state_groups.h
rename to common/kernel/exclusive_state_groups.h
diff --git a/common/exclusive_state_groups.impl.h b/common/kernel/exclusive_state_groups.impl.h
similarity index 100%
rename from common/exclusive_state_groups.impl.h
rename to common/kernel/exclusive_state_groups.impl.h
diff --git a/common/handle_error.cc b/common/kernel/handle_error.cc
similarity index 100%
rename from common/handle_error.cc
rename to common/kernel/handle_error.cc
diff --git a/common/hashlib.h b/common/kernel/hashlib.h
similarity index 100%
rename from common/hashlib.h
rename to common/kernel/hashlib.h
diff --git a/common/idstring.cc b/common/kernel/idstring.cc
similarity index 100%
rename from common/idstring.cc
rename to common/kernel/idstring.cc
diff --git a/common/idstring.h b/common/kernel/idstring.h
similarity index 100%
rename from common/idstring.h
rename to common/kernel/idstring.h
diff --git a/common/idstringlist.cc b/common/kernel/idstringlist.cc
similarity index 100%
rename from common/idstringlist.cc
rename to common/kernel/idstringlist.cc
diff --git a/common/idstringlist.h b/common/kernel/idstringlist.h
similarity index 100%
rename from common/idstringlist.h
rename to common/kernel/idstringlist.h
diff --git a/common/indexed_store.h b/common/kernel/indexed_store.h
similarity index 100%
rename from common/indexed_store.h
rename to common/kernel/indexed_store.h
diff --git a/common/log.cc b/common/kernel/log.cc
similarity index 100%
rename from common/log.cc
rename to common/kernel/log.cc
diff --git a/common/log.h b/common/kernel/log.h
similarity index 100%
rename from common/log.h
rename to common/kernel/log.h
diff --git a/common/nextpnr.cc b/common/kernel/nextpnr.cc
similarity index 100%
rename from common/nextpnr.cc
rename to common/kernel/nextpnr.cc
diff --git a/common/nextpnr.h b/common/kernel/nextpnr.h
similarity index 100%
rename from common/nextpnr.h
rename to common/kernel/nextpnr.h
diff --git a/common/nextpnr_assertions.cc b/common/kernel/nextpnr_assertions.cc
similarity index 100%
rename from common/nextpnr_assertions.cc
rename to common/kernel/nextpnr_assertions.cc
diff --git a/common/nextpnr_assertions.h b/common/kernel/nextpnr_assertions.h
similarity index 100%
rename from common/nextpnr_assertions.h
rename to common/kernel/nextpnr_assertions.h
diff --git a/common/nextpnr_base_types.h b/common/kernel/nextpnr_base_types.h
similarity index 100%
rename from common/nextpnr_base_types.h
rename to common/kernel/nextpnr_base_types.h
diff --git a/common/nextpnr_namespaces.cc b/common/kernel/nextpnr_namespaces.cc
similarity index 100%
rename from common/nextpnr_namespaces.cc
rename to common/kernel/nextpnr_namespaces.cc
diff --git a/common/nextpnr_namespaces.h b/common/kernel/nextpnr_namespaces.h
similarity index 100%
rename from common/nextpnr_namespaces.h
rename to common/kernel/nextpnr_namespaces.h
diff --git a/common/nextpnr_types.cc b/common/kernel/nextpnr_types.cc
similarity index 100%
rename from common/nextpnr_types.cc
rename to common/kernel/nextpnr_types.cc
diff --git a/common/nextpnr_types.h b/common/kernel/nextpnr_types.h
similarity index 100%
rename from common/nextpnr_types.h
rename to common/kernel/nextpnr_types.h
diff --git a/common/property.cc b/common/kernel/property.cc
similarity index 100%
rename from common/property.cc
rename to common/kernel/property.cc
diff --git a/common/property.h b/common/kernel/property.h
similarity index 100%
rename from common/property.h
rename to common/kernel/property.h
diff --git a/common/pybindings.cc b/common/kernel/pybindings.cc
similarity index 100%
rename from common/pybindings.cc
rename to common/kernel/pybindings.cc
diff --git a/common/pybindings.h b/common/kernel/pybindings.h
similarity index 100%
rename from common/pybindings.h
rename to common/kernel/pybindings.h
diff --git a/common/pycontainers.h b/common/kernel/pycontainers.h
similarity index 100%
rename from common/pycontainers.h
rename to common/kernel/pycontainers.h
diff --git a/common/pywrappers.h b/common/kernel/pywrappers.h
similarity index 100%
rename from common/pywrappers.h
rename to common/kernel/pywrappers.h
diff --git a/common/relptr.h b/common/kernel/relptr.h
similarity index 100%
rename from common/relptr.h
rename to common/kernel/relptr.h
diff --git a/common/report.cc b/common/kernel/report.cc
similarity index 100%
rename from common/report.cc
rename to common/kernel/report.cc
diff --git a/common/scope_lock.h b/common/kernel/scope_lock.h
similarity index 100%
rename from common/scope_lock.h
rename to common/kernel/scope_lock.h
diff --git a/common/sdf.cc b/common/kernel/sdf.cc
similarity index 100%
rename from common/sdf.cc
rename to common/kernel/sdf.cc
diff --git a/common/sso_array.h b/common/kernel/sso_array.h
similarity index 100%
rename from common/sso_array.h
rename to common/kernel/sso_array.h
diff --git a/common/str_ring_buffer.cc b/common/kernel/str_ring_buffer.cc
similarity index 100%
rename from common/str_ring_buffer.cc
rename to common/kernel/str_ring_buffer.cc
diff --git a/common/str_ring_buffer.h b/common/kernel/str_ring_buffer.h
similarity index 100%
rename from common/str_ring_buffer.h
rename to common/kernel/str_ring_buffer.h
diff --git a/common/svg.cc b/common/kernel/svg.cc
similarity index 100%
rename from common/svg.cc
rename to common/kernel/svg.cc
diff --git a/common/timing.cc b/common/kernel/timing.cc
similarity index 100%
rename from common/timing.cc
rename to common/kernel/timing.cc
diff --git a/common/timing.h b/common/kernel/timing.h
similarity index 100%
rename from common/timing.h
rename to common/kernel/timing.h
diff --git a/common/util.h b/common/kernel/util.h
similarity index 100%
rename from common/util.h
rename to common/kernel/util.h
diff --git a/common/fast_bels.h b/common/place/fast_bels.h
similarity index 100%
rename from common/fast_bels.h
rename to common/place/fast_bels.h
diff --git a/common/parallel_refine.cc b/common/place/parallel_refine.cc
similarity index 100%
rename from common/parallel_refine.cc
rename to common/place/parallel_refine.cc
diff --git a/common/parallel_refine.h b/common/place/parallel_refine.h
similarity index 100%
rename from common/parallel_refine.h
rename to common/place/parallel_refine.h
diff --git a/common/place_common.cc b/common/place/place_common.cc
similarity index 100%
rename from common/place_common.cc
rename to common/place/place_common.cc
diff --git a/common/place_common.h b/common/place/place_common.h
similarity index 100%
rename from common/place_common.h
rename to common/place/place_common.h
diff --git a/common/placer1.cc b/common/place/placer1.cc
similarity index 100%
rename from common/placer1.cc
rename to common/place/placer1.cc
diff --git a/common/placer1.h b/common/place/placer1.h
similarity index 100%
rename from common/placer1.h
rename to common/place/placer1.h
diff --git a/common/placer_heap.cc b/common/place/placer_heap.cc
similarity index 100%
rename from common/placer_heap.cc
rename to common/place/placer_heap.cc
diff --git a/common/placer_heap.h b/common/place/placer_heap.h
similarity index 100%
rename from common/placer_heap.h
rename to common/place/placer_heap.h
diff --git a/common/timing_opt.cc b/common/place/timing_opt.cc
similarity index 100%
rename from common/timing_opt.cc
rename to common/place/timing_opt.cc
diff --git a/common/timing_opt.h b/common/place/timing_opt.h
similarity index 100%
rename from common/timing_opt.h
rename to common/place/timing_opt.h
diff --git a/common/router1.cc b/common/route/router1.cc
similarity index 100%
rename from common/router1.cc
rename to common/route/router1.cc
diff --git a/common/router1.h b/common/route/router1.h
similarity index 100%
rename from common/router1.h
rename to common/route/router1.h
diff --git a/common/router2.cc b/common/route/router2.cc
similarity index 100%
rename from common/router2.cc
rename to common/route/router2.cc
diff --git a/common/router2.h b/common/route/router2.h
similarity index 100%
rename from common/router2.h
rename to common/route/router2.h

From 92a58a2631a30ac3f4c0291ecd1f2f01a912b9e9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 8 Apr 2022 14:05:03 +0100
Subject: [PATCH 131/712] ci: Restructure and move entirely to GH actions from
 Cirrus

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .cirrus.yml                          | 18 ------
 .cirrus/Dockerfile.ubuntu20.04       | 68 --------------------
 .cirrus/archcheck.sh                 |  8 ---
 .github/ci/build_common.sh           | 55 ++++++++++++++++
 .github/ci/build_ecp5.sh             | 24 +++++++
 .github/ci/build_generic.sh          | 25 ++++++++
 .github/ci/build_gowin.sh            | 23 +++++++
 .github/ci/build_ice40.sh            | 27 ++++++++
 .github/ci/build_machxo2.sh          | 21 ++++++
 .github/ci/build_mistral.sh          |  6 ++
 .github/ci/build_nexus.sh            | 23 +++++++
 .github/workflows/arch_ci.yml        | 95 ++++++++++++++++++++++++++++
 .github/workflows/mistral_ci.yml     | 29 ---------
 CMakeLists.txt                       |  2 +-
 ice40/smoketest/attosoc/smoketest.sh |  2 +-
 tests                                |  2 +-
 16 files changed, 302 insertions(+), 126 deletions(-)
 delete mode 100644 .cirrus.yml
 delete mode 100644 .cirrus/Dockerfile.ubuntu20.04
 delete mode 100755 .cirrus/archcheck.sh
 create mode 100644 .github/ci/build_common.sh
 create mode 100644 .github/ci/build_ecp5.sh
 create mode 100644 .github/ci/build_generic.sh
 create mode 100644 .github/ci/build_gowin.sh
 create mode 100644 .github/ci/build_ice40.sh
 create mode 100644 .github/ci/build_machxo2.sh
 create mode 100644 .github/ci/build_nexus.sh
 create mode 100644 .github/workflows/arch_ci.yml
 delete mode 100644 .github/workflows/mistral_ci.yml

diff --git a/.cirrus.yml b/.cirrus.yml
deleted file mode 100644
index 86edee591e..0000000000
--- a/.cirrus.yml
+++ /dev/null
@@ -1,18 +0,0 @@
-task:
-  name: build-test-ubuntu2004
-  container:
-    cpu: 5
-    memory: 20
-    dockerfile: .cirrus/Dockerfile.ubuntu20.04
-
-  submodule_script: git submodule sync --recursive && git submodule update --init --recursive
-  build_script: mkdir build && cd build && cmake .. -DARCH='ecp5;generic;gowin;ice40;machxo2;nexus' -DOXIDE_INSTALL_PREFIX=$HOME/.cargo -DBUILD_TESTS=on -DBUILD_GUI=on -DWERROR=on && make -j3
-  test_generic_script: cd build && ./nextpnr-generic-test
-  flow_test_generic_script: export NPNR=$(pwd)/build/nextpnr-generic && cd tests/generic/flow && ./run.sh
-  test_ice40_script: cd build && ./nextpnr-ice40-test
-  smoketest_ice40_script: export NEXTPNR=$(pwd)/build/nextpnr-ice40 && cd ice40/smoketest/attosoc && ./smoketest.sh
-  test_ecp5_script: cd build && ./nextpnr-ecp5-test
-  smoketest_generic_script: export NEXTPNR=$(pwd)/build/nextpnr-generic && cd generic/examples && ./simple.sh && ./simtest.sh
-  regressiontest_ice40_script: make -j $(nproc) -C tests/ice40/regressions NPNR=$(pwd)/build/nextpnr-ice40
-  regressiontest_ecp5_script: make -j $(nproc) -C tests/ecp5/regressions NPNR=$(pwd)/build/nextpnr-ecp5
-  archcheck_script: BUILD_DIR=$(pwd)/build ./.cirrus/archcheck.sh
diff --git a/.cirrus/Dockerfile.ubuntu20.04 b/.cirrus/Dockerfile.ubuntu20.04
deleted file mode 100644
index 35ea18bd9a..0000000000
--- a/.cirrus/Dockerfile.ubuntu20.04
+++ /dev/null
@@ -1,68 +0,0 @@
-FROM ubuntu:focal-20201106
-
-ENV DEBIAN_FRONTEND=noninteractive
-
-RUN set -e -x ;\
-    apt-get -y update ;\
-    apt-get -y upgrade ;\
-    apt-get -y install \
-        build-essential autoconf cmake clang bison wget flex gperf \
-        libreadline-dev gawk tcl-dev libffi-dev graphviz xdot python3-dev \
-        libboost-all-dev qt5-default git libftdi-dev pkg-config libeigen3-dev \
-        zlib1g-dev curl python3-pip libcapnp-dev capnproto
-
-
-RUN set -e -x ;\
-    mkdir -p /usr/local/src ;\
-    cd /usr/local/src ;\
-    git clone --recursive https://github.com/steveicarus/iverilog.git ;\
-    cd iverilog ;\
-    git reset --hard 84b4ebee0cfcda28a242d89a07020cd70b1d3e7f ;\
-    sh autoconf.sh ;\
-    ./configure ;\
-    make -j $(nproc) ;\
-    make install ;\
-    rm -rf /usr/local/src/iverilog
-
-RUN set -e -x ;\
-    mkdir -p /usr/local/src ;\
-    cd /usr/local/src ;\
-    git clone --recursive https://github.com/YosysHQ/icestorm.git ;\
-    cd icestorm ;\
-    git reset --hard 9f66f9ce16941c6417813cb87653c735a78b53ae ;\
-    make -j $(nproc) ;\
-    make install
-
-RUN set -e -x ;\
-    mkdir -p /usr/local/src ;\
-    cd /usr/local/src ;\
-    git clone --recursive https://github.com/YosysHQ/yosys.git ;\
-    cd yosys ;\
-    git reset --hard cd8b2ed4e6f9447c94d801de7db7ae6ce0976d57 ;\
-    make -j $(nproc) ;\
-    make install ;\
-    rm -rf /usr/local/src/yosys
-
-RUN set -e -x ;\
-    mkdir -p /usr/local/src ;\
-    cd /usr/local/src ;\
-    git clone --recursive https://github.com/YosysHQ/prjtrellis.git ;\
-    cd prjtrellis ;\
-    git reset --hard 26f917d6052e084df30211ae3a78c8a165121e09 ;\
-    cd libtrellis ;\
-    cmake . ;\
-    make -j $(nproc) ;\
-    make install
-
-RUN set -e -x ;\
-    curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y ;\
-    mkdir -p /usr/local/src ;\
-    cd /usr/local/src ;\
-    git clone --recursive https://github.com/gatecat/prjoxide.git ;\
-    cd prjoxide ;\
-    git reset --hard 318331f8b30c2e2a31cc41d51f104b671e180a8a ;\
-    cd libprjoxide ;\
-    PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide
-
-RUN set -e -x ;\
-    pip3 install apycula==0.2a4
diff --git a/.cirrus/archcheck.sh b/.cirrus/archcheck.sh
deleted file mode 100755
index 6ff6c043e9..0000000000
--- a/.cirrus/archcheck.sh
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/usr/bin/env bash
-set -ex
-echo "Running archcheck!"
-${BUILD_DIR}/nextpnr-ice40 --hx8k --package ct256 --test
-${BUILD_DIR}/nextpnr-ice40 --up5k --package sg48 --test
-${BUILD_DIR}/nextpnr-ecp5 --um5g-25k --package CABGA381 --test
-${BUILD_DIR}/nextpnr-nexus --device LIFCL-40-9BG400CES --test
-${BUILD_DIR}/nextpnr-gowin --device GW1N-UV4LQ144C6/I5 --test
diff --git a/.github/ci/build_common.sh b/.github/ci/build_common.sh
new file mode 100644
index 0000000000..2a2d844751
--- /dev/null
+++ b/.github/ci/build_common.sh
@@ -0,0 +1,55 @@
+#!/bin/bash
+
+# Install latest Yosys
+function build_yosys {
+    PREFIX=`pwd`/.yosys
+    YOSYS_PATH=${DEPS_PATH}/yosys
+    mkdir -p ${YOSYS_PATH}
+    git clone --recursive https://github.com/YosysHQ/yosys ${YOSYS_PATH}
+    pushd ${YOSYS_PATH}
+    git reset --hard ${YOSYS_REVISION}
+    make -j`nproc` PREFIX=$PREFIX
+    make install PREFIX=$PREFIX
+    popd
+}
+
+function build_icestorm {
+    PREFIX=`pwd`/.icestorm
+    ICESTORM_PATH=${DEPS_PATH}/icestorm
+    mkdir -p ${ICESTORM_PATH}
+    git clone --recursive https://github.com/YosysHQ/icestorm ${ICESTORM_PATH}
+    pushd ${ICESTORM_PATH}
+    git reset --hard ${ICESTORM_REVISION}
+    make -j`nproc` PREFIX=${PREFIX}
+    make install PREFIX=${PREFIX}
+    popd
+}
+
+function build_trellis {
+    PREFIX=`pwd`/.trellis
+    TRELLIS_PATH=${DEPS_PATH}/prjtrellis
+    mkdir -p ${TRELLIS_PATH}
+    git clone --recursive https://github.com/YosysHQ/prjtrellis ${TRELLIS_PATH}
+    pushd ${TRELLIS_PATH}
+    git reset --hard ${TRELLIS_REVISION}
+    mkdir -p libtrellis/build
+    pushd libtrellis/build
+    cmake -DCMAKE_INSTALL_PREFIX=${PREFIX} ..
+    make -j`nproc`
+    make install
+    popd
+    popd
+}
+
+function build_prjoxide {
+    PREFIX=`pwd`/.prjoxide
+    PRJOXIDE_PATH=${DEPS_PATH}/prjoxide
+    curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y ;\
+    mkdir -p ${PRJOXIDE_PATH}
+    git clone --recursive https://github.com/gatecat/prjoxide ${PRJOXIDE_PATH}
+    pushd ${PRJOXIDE_PATH}
+    git reset --hard ${PRJOXIDE_REVISION}
+    cd libprjoxide
+    PATH=$PATH:$HOME/.cargo/bin cargo install --root $PREFIX --path prjoxide
+    popd
+}
diff --git a/.github/ci/build_ecp5.sh b/.github/ci/build_ecp5.sh
new file mode 100644
index 0000000000..2d09a6f65b
--- /dev/null
+++ b/.github/ci/build_ecp5.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=ecp5 -DTRELLIS_INSTALL_PREFIX=${GITHUB_WORKSPACE}/.trellis -DWERROR=on -DBUILD_GUI=on -DUSE_IPO=off
+    make nextpnr-ecp5 -j`nproc`
+    popd
+}
+
+function run_tests {
+    export PATH=${GITHUB_WORKSPACE}/.trellis/bin:${GITHUB_WORKSPACE}/.yosys/bin:$PATH
+    make -j $(nproc) -C tests/ecp5/regressions NPNR=$(pwd)/build/nextpnr-ecp5
+}
+
+function run_archcheck {
+    pushd build
+    ./nextpnr-ecp5 --um5g-25k --package CABGA381 --test
+    popd
+}
diff --git a/.github/ci/build_generic.sh b/.github/ci/build_generic.sh
new file mode 100644
index 0000000000..49a73d3a15
--- /dev/null
+++ b/.github/ci/build_generic.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=generic -DWERROR=on
+    make nextpnr-generic -j`nproc`
+    popd
+}
+
+function run_tests {
+    export PATH=${GITHUB_WORKSPACE}/.yosys/bin:$PATH
+    ( export NPNR=$(pwd)/build/nextpnr-generic && cd tests/generic/flow && ./run.sh )
+}
+
+function run_archcheck {
+    pushd build
+    # TODO
+    # ./nextpnr-generic --uarch example --test
+    popd
+}
diff --git a/.github/ci/build_gowin.sh b/.github/ci/build_gowin.sh
new file mode 100644
index 0000000000..430cd2b046
--- /dev/null
+++ b/.github/ci/build_gowin.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+function get_dependencies {
+    pip3 install apycula==${APYCULA_REVISION}
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=gowin -DWERROR=on -DBUILD_GUI=on -DUSE_IPO=off
+    make nextpnr-gowin -j`nproc`
+    popd
+}
+
+function run_tests {
+    :
+}
+
+function run_archcheck {
+    pushd build
+    ./nextpnr-gowin --device GW1N-UV4LQ144C6/I5 --test
+    popd
+}
diff --git a/.github/ci/build_ice40.sh b/.github/ci/build_ice40.sh
new file mode 100644
index 0000000000..ea9234ccd9
--- /dev/null
+++ b/.github/ci/build_ice40.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=ice40 -DICESTORM_INSTALL_PREFIX=${GITHUB_WORKSPACE}/.icestorm -DWERROR=on -DBUILD_TESTS=on -DBUILD_GUI=on
+    make nextpnr-ice40 nextpnr-ice40-test -j`nproc`
+    popd
+}
+
+function run_tests {
+    export PATH=${GITHUB_WORKSPACE}/.yosys/bin:${GITHUB_WORKSPACE}/.icestorm/bin:$PATH
+    (cd build && ./nextpnr-ice40-test)
+    (export NEXTPNR=$(pwd)/build/nextpnr-ice40 && cd ice40/smoketest/attosoc && ./smoketest.sh)
+    make -j $(nproc) -C tests/ice40/regressions NPNR=$(pwd)/build/nextpnr-ice40
+}
+
+function run_archcheck {
+    pushd build
+    ./nextpnr-ice40 --hx8k --package ct256 --test
+    ./nextpnr-ice40 --up5k --package sg48 --test
+    popd
+}
diff --git a/.github/ci/build_machxo2.sh b/.github/ci/build_machxo2.sh
new file mode 100644
index 0000000000..c81a538ba6
--- /dev/null
+++ b/.github/ci/build_machxo2.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=machxo2 -DTRELLIS_INSTALL_PREFIX=${GITHUB_WORKSPACE}/.trellis -DWERROR=on -DUSE_IPO=off
+    make nextpnr-machxo2 -j`nproc`
+    popd
+}
+
+function run_tests {
+    :
+}
+
+function run_archcheck {
+    :
+}
diff --git a/.github/ci/build_mistral.sh b/.github/ci/build_mistral.sh
index 3c809b0ee0..807c620649 100644
--- a/.github/ci/build_mistral.sh
+++ b/.github/ci/build_mistral.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 
+export MISTRAL_PATH=${DEPS_PATH}/mistral
+
 function get_dependencies {
     # Fetch mistral
     mkdir -p ${MISTRAL_PATH}
@@ -17,6 +19,10 @@ function build_nextpnr {
     popd
 }
 
+function run_tests {
+    :
+}
+
 function run_archcheck {
     pushd build
     ./nextpnr-mistral --device 5CEBA2F17A7 --test
diff --git a/.github/ci/build_nexus.sh b/.github/ci/build_nexus.sh
new file mode 100644
index 0000000000..e8acd9b6d7
--- /dev/null
+++ b/.github/ci/build_nexus.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=nexus -DOXIDE_INSTALL_PREFIX=${GITHUB_WORKSPACE}/.prjoxide
+    make nextpnr-nexus -j`nproc`
+    popd
+}
+
+function run_tests {
+    :
+}
+
+function run_archcheck {
+    pushd build
+    ./nextpnr-nexus --device LIFCL-40-9BG400CES --test
+    popd
+}
diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
new file mode 100644
index 0000000000..5bf83630d5
--- /dev/null
+++ b/.github/workflows/arch_ci.yml
@@ -0,0 +1,95 @@
+# CI for everything other than the sui generis FPGA interchange arrangements
+
+name: Arch CI tests
+
+on: [push, pull_request]
+
+jobs:
+  Build-nextpnr:
+    strategy:
+      fail-fast: false
+      matrix:
+        arch: [mistral, ice40, ecp5, generic, nexus, machxo2, gowin]
+    runs-on: ubuntu-latest
+    env:
+      DEPS_PATH: ${{ github.workspace }}/deps
+      YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
+      ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
+      TRELLIS_REVISION: 48486ebd1e03e4ac42c96299e881adf9d43bc241
+      PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
+      MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
+      APYCULA_REVISION: 0.2a4
+    steps:
+    - uses: actions/checkout@v2
+      with:
+        submodules: recursive
+
+    - uses: actions/setup-python@v2
+
+    - name: Install
+      run: |
+        sudo apt-get update
+        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qt5-default iverilog
+
+    - name: Cache yosys installation
+      uses: actions/cache@v2
+      id: cache-yosys
+      with:
+        path: .yosys
+        key: cache-yosys-${{ env.YOSYS_REVISION }}-r2
+
+    - name: Build yosys
+      run: |
+        source ./.github/ci/build_common.sh
+        build_yosys
+      if: steps.cache-yosys.outputs.cache-hit != 'true'
+
+    - name: Cache icestorm installation
+      uses: actions/cache@v2
+      id: cache-icestorm
+      with:
+        path: .icestorm
+        key: cache-icestorm-${{ env.ICESTORM_REVISION }}
+      if: matrix.arch == 'ice40'
+
+    - name: Build icestorm
+      run: |
+        source ./.github/ci/build_common.sh
+        build_icestorm
+      if: matrix.arch == 'ice40' && steps.cache-icestorm.outputs.cache-hit != 'true'
+
+    - name: Cache trellis installation
+      uses: actions/cache@v2
+      id: cache-trellis
+      with:
+        path: .trellis
+        key: cache-trellis-${{ env.TRELLIS_REVISION }}
+      if: matrix.arch == 'ecp5' || matrix.arch == 'machxo2'
+
+    - name: Build trellis
+      run: |
+        source ./.github/ci/build_common.sh
+        build_trellis
+      if: (matrix.arch == 'ecp5' || matrix.arch == 'machxo2') && steps.cache-trellis.outputs.cache-hit != 'true'
+
+    - name: Cache prjoxide installation
+      uses: actions/cache@v2
+      id: cache-prjoxide
+      with:
+        path: .prjoxide
+        key: cache-prjoxide-${{ env.PRJOXIDE_REVISION }}
+      if: matrix.arch == 'nexus'
+
+    - name: Build prjoxide
+      run: |
+        source ./.github/ci/build_common.sh
+        build_prjoxide
+      if: matrix.arch == 'nexus' && steps.cache-prjoxide.outputs.cache-hit != 'true'
+
+    - name: Execute build nextpnr
+      run: |
+        source ./.github/ci/build_${{ matrix.arch }}.sh
+        get_dependencies
+        build_nextpnr
+        run_tests
+        run_archcheck
diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
deleted file mode 100644
index b0bbfb521e..0000000000
--- a/.github/workflows/mistral_ci.yml
+++ /dev/null
@@ -1,29 +0,0 @@
-name: Mistral CI tests
-
-on: [push, pull_request]
-
-jobs:
-  Build-nextpnr:
-    runs-on: ubuntu-latest
-    steps:
-
-    - uses: actions/checkout@v2
-      with:
-        submodules: recursive
-
-    - uses: actions/setup-python@v2
-
-    - name: Install
-      run: |
-        sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev clang bison flex swig
-
-    - name: Execute build nextpnr
-      env:
-        MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9 
-      run: |
-        source ./.github/ci/build_mistral.sh
-        get_dependencies
-        build_nextpnr
-        run_archcheck
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 89bdb3607c..3120cf402b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -134,7 +134,7 @@ if (MSVC)
     set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996 /wd4127")
 else()
     # N.B. the -Wno-array-bounds is to work around a false positive in GCC 9
-    set(WARN_FLAGS "-Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers -Wno-array-bounds")
+    set(WARN_FLAGS "-Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers -Wno-array-bounds -Wno-format-truncation")
     if (WERROR)
         set(WARN_FLAGS "${WARN_FLAGS} -Werror")
     endif()
diff --git a/ice40/smoketest/attosoc/smoketest.sh b/ice40/smoketest/attosoc/smoketest.sh
index 05408ab16c..6582346168 100755
--- a/ice40/smoketest/attosoc/smoketest.sh
+++ b/ice40/smoketest/attosoc/smoketest.sh
@@ -4,6 +4,6 @@ yosys -q -p 'synth_ice40 -json attosoc.json -top attosoc' attosoc.v picorv32.v
 $NEXTPNR --hx8k --json attosoc.json --pcf attosoc.pcf --asc attosoc.asc --freq 50
 icetime -tmd hx8k -c 50 attosoc.asc
 icebox_vlog -L -l -p attosoc.pcf -c -n attosoc attosoc.asc > attosoc_pnr.v
-iverilog -o attosoc_pnr_tb attosoc_pnr.v attosoc_tb.v `yosys-config --datdir/ice40/cells_sim.v`
+iverilog -DNO_ICE40_DEFAULT_ASSIGNMENTS -o attosoc_pnr_tb attosoc_pnr.v attosoc_tb.v `yosys-config --datdir/ice40/cells_sim.v`
 vvp attosoc_pnr_tb
 diff output.txt golden.txt
diff --git a/tests b/tests
index ccc61e5ec7..00c55a9eb9 160000
--- a/tests
+++ b/tests
@@ -1 +1 @@
-Subproject commit ccc61e5ec7cc04410462ec3196ad467354787afb
+Subproject commit 00c55a9eb9ea2e062b51fe0d64741412b185d95d

From d3ba259db2d857a075113706cec2fad9a00c3f72 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 11 Apr 2022 18:46:44 +0100
Subject: [PATCH 132/712] ice40: Avoid chain finder from mixing up chains by
 only allowing I3 chaining at end

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/chains.cc | 79 ++++++++++++++++++++++++++++---------------------
 1 file changed, 45 insertions(+), 34 deletions(-)

diff --git a/ice40/chains.cc b/ice40/chains.cc
index 6ea261de49..20edafaac4 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -183,43 +183,54 @@ class ChainConstrainer
 
     void process_carries()
     {
-        std::vector<CellChain> carry_chains = find_chains(
-                ctx, [](const Context *ctx, const CellInfo *cell) { return is_lc(ctx, cell); },
-                [](const Context *ctx, const
-
-                   CellInfo *cell) {
-                    CellInfo *carry_prev = net_driven_by(ctx, cell->ports.at(id_CIN).net, is_lc, id_COUT);
-                    if (carry_prev != nullptr)
-                        return carry_prev;
-                    CellInfo *i3_prev = net_driven_by(ctx, cell->ports.at(id_I3).net, is_lc, id_COUT);
-                    if (i3_prev != nullptr)
-                        return i3_prev;
-                    return (CellInfo *)nullptr;
-                },
-                [](const Context *ctx, const CellInfo *cell) {
-                    CellInfo *carry_next = net_only_drives(ctx, cell->ports.at(id_COUT).net, is_lc, id_CIN, false);
-                    if (carry_next != nullptr)
-                        return carry_next;
-                    CellInfo *i3_next = net_only_drives(ctx, cell->ports.at(id_COUT).net, is_lc, id_I3, false);
-                    if (i3_next != nullptr)
-                        return i3_next;
-                    return (CellInfo *)nullptr;
-                });
-        pool<IdString> chained;
-        for (auto &base_chain : carry_chains) {
-            for (auto c : base_chain.cells)
-                chained.insert(c->name);
+        // Find carry roots
+        std::vector<CellChain> carry_chains;
+        pool<IdString> processed;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_lc(ctx, ci) && bool_or_default(ci->params, id_CARRY_ENABLE)) {
+                // possibly a non-root if CIN or I3 driven by another cout
+                NetInfo *cin = ci->getPort(id_CIN);
+                if (cin && cin->driver.cell && is_lc(ctx, cin->driver.cell) && cin->driver.port == id_COUT) {
+                    continue;
+                }
+                carry_chains.emplace_back();
+                auto &cc = carry_chains.back();
+                CellInfo *cursor = ci;
+                while (cursor) {
+                    cc.cells.push_back(cursor);
+                    processed.insert(cursor->name);
+                    NetInfo *cout = cursor->getPort(id_COUT);
+                    if (!cout)
+                        break;
+                    cursor = nullptr;
+                    // look for CIN connectivity
+                    for (auto &usr : cout->users) {
+                        if (is_lc(ctx, usr.cell) && usr.port == id_CIN && !processed.count(usr.cell->name)) {
+                            cursor = usr.cell;
+                            break;
+                        }
+                    }
+                    // look for I3 connectivity - only to a top cell with no further chaining
+                    if (cursor)
+                        continue;
+                    for (auto &usr : cout->users) {
+                        if (is_lc(ctx, usr.cell) && usr.port == id_I3 && !processed.count(usr.cell->name) &&
+                            !usr.cell->getPort(id_COUT)) {
+                            cursor = usr.cell;
+                            break;
+                        }
+                    }
+                }
+            }
         }
-        // Any cells not in chains, but with carry enabled, must also be put in a single-carry chain
-        // for correct processing
+        // anything left behind....
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (chained.find(cell.first) == chained.end() && is_lc(ctx, ci) &&
-                bool_or_default(ci->params, id_CARRY_ENABLE)) {
-                CellChain sChain;
-                sChain.cells.push_back(ci);
-                chained.insert(cell.first);
-                carry_chains.push_back(sChain);
+            if (is_lc(ctx, ci) && bool_or_default(ci->params, id_CARRY_ENABLE) && !processed.count(ci->name)) {
+                carry_chains.emplace_back();
+                carry_chains.back().cells.push_back(ci);
+                processed.insert(ci->name);
             }
         }
         std::vector<CellChain> all_chains;

From 61b3e2e1ffbf0c0438c734a04d9d86d75668677e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 13 Apr 2022 19:18:13 +0100
Subject: [PATCH 133/712] Move general parallel detail place code out of
 parallel_refine

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/detail_place_cfg.h   |  36 ++
 common/place/detail_place_core.cc | 457 +++++++++++++++++++++++++
 common/place/detail_place_core.h  | 224 ++++++++++++
 common/place/parallel_refine.cc   | 552 +-----------------------------
 common/place/parallel_refine.h    |   6 +-
 5 files changed, 730 insertions(+), 545 deletions(-)
 create mode 100644 common/place/detail_place_cfg.h
 create mode 100644 common/place/detail_place_core.cc
 create mode 100644 common/place/detail_place_core.h

diff --git a/common/place/detail_place_cfg.h b/common/place/detail_place_cfg.h
new file mode 100644
index 0000000000..dadda0e831
--- /dev/null
+++ b/common/place/detail_place_cfg.h
@@ -0,0 +1,36 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef DETAIL_PLACE_CFG_H
+#define DETAIL_PLACE_CFG_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct DetailPlaceCfg
+{
+    DetailPlaceCfg(Context *ctx);
+    bool timing_driven;
+    int hpwl_scale_x, hpwl_scale_y;
+    float crit_exp = 8;
+};
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/common/place/detail_place_core.cc b/common/place/detail_place_core.cc
new file mode 100644
index 0000000000..bb3836394b
--- /dev/null
+++ b/common/place/detail_place_core.cc
@@ -0,0 +1,457 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "detail_place_core.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+DetailPlaceCfg::DetailPlaceCfg(Context *ctx)
+{
+    timing_driven = ctx->setting<bool>("timing_driven");
+
+    hpwl_scale_x = 1;
+    hpwl_scale_y = 1;
+}
+
+PlacePartition::PlacePartition(Context *ctx)
+{
+    x0 = ctx->getGridDimX();
+    y0 = ctx->getGridDimY();
+    x1 = 0;
+    y1 = 0;
+    for (auto &cell : ctx->cells) {
+        Loc l = ctx->getBelLocation(cell.second->bel);
+        x0 = std::min(x0, l.x);
+        x1 = std::max(x1, l.x);
+        y0 = std::min(y0, l.y);
+        y1 = std::max(y1, l.y);
+        cells.push_back(cell.second.get());
+    }
+}
+
+void PlacePartition::split(Context *ctx, bool yaxis, float pivot, PlacePartition &l, PlacePartition &r)
+{
+    std::sort(cells.begin(), cells.end(), [&](CellInfo *a, CellInfo *b) {
+        Loc l0 = ctx->getBelLocation(a->bel), l1 = ctx->getBelLocation(b->bel);
+        return yaxis ? (l0.y < l1.y) : (l0.x < l1.x);
+    });
+    size_t pivot_point = size_t(cells.size() * pivot);
+    l.cells.clear();
+    r.cells.clear();
+    l.cells.reserve(pivot_point);
+    r.cells.reserve(cells.size() - pivot_point);
+    int pivot_coord = (pivot_point == 0) ? (yaxis ? y1 : x1)
+                                         : (yaxis ? ctx->getBelLocation(cells.at(pivot_point - 1)->bel).y
+                                                  : ctx->getBelLocation(cells.at(pivot_point - 1)->bel).x);
+    for (size_t i = 0; i < cells.size(); i++) {
+        Loc loc = ctx->getBelLocation(cells.at(i)->bel);
+        ((yaxis ? loc.y : loc.x) <= pivot_coord ? l.cells : r.cells).push_back(cells.at(i));
+    }
+    if (yaxis) {
+        l.x0 = r.x0 = x0;
+        l.x1 = r.x1 = x1;
+        l.y0 = y0;
+        l.y1 = pivot_coord;
+        r.y0 = (pivot_coord == y1) ? y1 : (pivot_coord + 1);
+        r.y1 = y1;
+    } else {
+        l.y0 = r.y0 = y0;
+        l.y1 = r.y1 = y1;
+        l.x0 = x0;
+        l.x1 = pivot_coord;
+        r.x0 = (pivot_coord == x1) ? x1 : (pivot_coord + 1);
+        r.x1 = x1;
+    }
+}
+
+void DetailPlacerState::update_global_costs()
+{
+    last_bounds.resize(flat_nets.size());
+    last_tmg_costs.resize(flat_nets.size());
+    total_wirelen = 0;
+    total_timing_cost = 0;
+    for (size_t i = 0; i < flat_nets.size(); i++) {
+        NetInfo *ni = flat_nets.at(i);
+        if (skip_net(ni))
+            continue;
+        last_bounds.at(i) = NetBB::compute(ctx, ni);
+        total_wirelen += last_bounds.at(i).hpwl(base_cfg);
+        if (!timing_skip_net(ni)) {
+            auto &tc = last_tmg_costs.at(i);
+            tc.resize(ni->users.capacity());
+            for (auto usr : ni->users.enumerate()) {
+                tc.at(usr.index.idx()) = get_timing_cost(ni, usr.index);
+                total_timing_cost += tc.at(usr.index.idx());
+            }
+        }
+    }
+}
+
+NetBB NetBB::compute(const Context *ctx, const NetInfo *net, const dict<IdString, BelId> *cell2bel)
+{
+    NetBB result{};
+    if (!net->driver.cell)
+        return result;
+    auto bel_loc = [&](const CellInfo *cell) {
+        BelId bel = cell2bel ? cell2bel->at(cell->name) : cell->bel;
+        return ctx->getBelLocation(bel);
+    };
+    result.nx0 = result.nx1 = result.ny0 = result.ny1 = 1;
+    Loc drv_loc = bel_loc(net->driver.cell);
+    result.x0 = result.x1 = drv_loc.x;
+    result.y0 = result.y1 = drv_loc.y;
+    for (auto &usr : net->users) {
+        Loc l = bel_loc(usr.cell);
+        if (l.x == result.x0)
+            ++result.nx0; // on the edge
+        else if (l.x < result.x0) {
+            result.x0 = l.x; // extends the edge
+            result.nx0 = 1;
+        }
+        if (l.x == result.x1)
+            ++result.nx1; // on the edge
+        else if (l.x > result.x1) {
+            result.x1 = l.x; // extends the edge
+            result.nx1 = 1;
+        }
+        if (l.y == result.y0)
+            ++result.ny0; // on the edge
+        else if (l.y < result.y0) {
+            result.y0 = l.y; // extends the edge
+            result.ny0 = 1;
+        }
+        if (l.y == result.y1)
+            ++result.ny1; // on the edge
+        else if (l.y > result.y1) {
+            result.y1 = l.y; // extends the edge
+            result.ny1 = 1;
+        }
+    }
+    return result;
+}
+
+void DetailPlacerThreadState::set_partition(const PlacePartition &part)
+{
+    p = part;
+    thread_nets.clear();
+    thread_net_idx.resize(g.flat_nets.size());
+    std::fill(thread_net_idx.begin(), thread_net_idx.end(), -1);
+    // Determine the set of nets that are within the thread; and therefore we care about
+    for (auto thread_cell : part.cells) {
+        for (auto &port : thread_cell->ports) {
+            if (!port.second.net)
+                continue;
+            int global_idx = port.second.net->udata;
+            auto &thread_idx = thread_net_idx.at(global_idx);
+            // Already added to the set
+            if (thread_idx != -1)
+                continue;
+            thread_idx = thread_nets.size();
+            thread_nets.push_back(port.second.net);
+        }
+    }
+    tmg_ignored_nets.clear();
+    ignored_nets.clear();
+    for (auto tn : thread_nets) {
+        ignored_nets.push_back(g.skip_net(tn));
+        tmg_ignored_nets.push_back(g.timing_skip_net(tn));
+    }
+    // Set up the original cell-bel map for all nets inside the thread
+    local_cell2bel.clear();
+    for (NetInfo *net : thread_nets) {
+        if (net->driver.cell)
+            local_cell2bel[net->driver.cell->name] = net->driver.cell->bel;
+        for (auto &usr : net->users)
+            local_cell2bel[usr.cell->name] = usr.cell->bel;
+    }
+}
+
+void DetailPlacerThreadState::setup_initial_state()
+{
+    // Setup initial net bounding boxes and timing costs
+    net_bounds.clear();
+    arc_tmg_cost.clear();
+    for (auto tn : thread_nets) {
+        net_bounds.push_back(g.last_bounds.at(tn->udata));
+        arc_tmg_cost.push_back(g.last_tmg_costs.at(tn->udata));
+    }
+    new_net_bounds = net_bounds;
+    for (int j = 0; j < 2; j++) {
+        auto &a = axes.at(j);
+        a.already_bounds_changed.resize(net_bounds.size());
+    }
+    already_timing_changed.clear();
+    already_timing_changed.resize(net_bounds.size());
+    for (size_t i = 0; i < thread_nets.size(); i++)
+        already_timing_changed.at(i) = std::vector<bool>(thread_nets.at(i)->users.capacity());
+}
+
+bool DetailPlacerThreadState::bounds_check(BelId bel)
+{
+    Loc l = ctx->getBelLocation(bel);
+    if (l.x < p.x0 || l.x > p.x1 || l.y < p.y0 || l.y > p.y1)
+        return false;
+    return true;
+}
+
+bool DetailPlacerThreadState::bind_move()
+{
+#if !defined(__wasm)
+    std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
+    for (auto &entry : moved_cells) {
+        ctx->unbindBel(entry.second.first);
+    }
+    bool success = true;
+    for (auto &entry : moved_cells) {
+        // Make sure targets are available before we bind them
+        if (!ctx->checkBelAvail(entry.second.second)) {
+            success = false;
+            break;
+        }
+        ctx->bindBel(entry.second.second, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
+    }
+    arch_state_dirty = true;
+    return success;
+}
+
+bool DetailPlacerThreadState::check_validity()
+{
+#if !defined(__wasm)
+    std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
+    bool result = true;
+    for (auto e : moved_cells) {
+        if (!ctx->isBelLocationValid(e.second.first)) {
+            // Have to check old; too; as unbinding a bel could make a placement illegal by virtue of no longer
+            // enabling dedicated routes to be used
+            result = false;
+            break;
+        }
+        if (!ctx->isBelLocationValid(e.second.second)) {
+            result = false;
+            break;
+        }
+    }
+    return result;
+}
+
+void DetailPlacerThreadState::revert_move()
+{
+    if (arch_state_dirty) {
+        // If changes to the arch state were made, revert them by restoring original cell bindings
+#if !defined(__wasm)
+        std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
+        for (auto &entry : moved_cells) {
+            BelId curr_bound = ctx->cells.at(entry.first)->bel;
+            if (curr_bound != BelId())
+                ctx->unbindBel(curr_bound);
+        }
+        for (auto &entry : moved_cells) {
+            ctx->bindBel(entry.second.first, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
+        }
+        arch_state_dirty = false;
+    }
+    for (auto &entry : moved_cells)
+        local_cell2bel[entry.first] = entry.second.first;
+}
+
+void DetailPlacerThreadState::commit_move()
+{
+    arch_state_dirty = false;
+    for (auto &axis : axes) {
+        for (auto bc : axis.bounds_changed_nets) {
+            // Commit updated net bounds
+            net_bounds.at(bc) = new_net_bounds.at(bc);
+        }
+    }
+    if (g.base_cfg.timing_driven) {
+        NPNR_ASSERT(timing_changed_arcs.size() == new_timing_costs.size());
+        for (size_t i = 0; i < timing_changed_arcs.size(); i++) {
+            auto arc = timing_changed_arcs.at(i);
+            arc_tmg_cost.at(arc.first).at(arc.second.idx()) = new_timing_costs.at(i);
+        }
+    }
+}
+
+void DetailPlacerThreadState::compute_changes_for_cell(CellInfo *cell, BelId old_bel, BelId new_bel)
+{
+    Loc new_loc = ctx->getBelLocation(new_bel);
+    Loc old_loc = ctx->getBelLocation(old_bel);
+    for (const auto &port : cell->ports) {
+        NetInfo *pn = port.second.net;
+        if (!pn)
+            continue;
+        int idx = thread_net_idx.at(pn->udata);
+        if (ignored_nets.at(idx))
+            continue;
+        NetBB &new_bounds = new_net_bounds.at(idx);
+        // For the x-axis (i=0) and y-axis (i=1)
+        for (int i = 0; i < 2; i++) {
+            auto &axis = axes.at(i);
+            // New and old on this axis
+            int new_pos = i ? new_loc.y : new_loc.x, old_pos = i ? old_loc.y : old_loc.x;
+            // References to updated bounding box entries
+            auto &b0 = i ? new_bounds.y0 : new_bounds.x0;
+            auto &n0 = i ? new_bounds.ny0 : new_bounds.nx0;
+            auto &b1 = i ? new_bounds.y1 : new_bounds.x1;
+            auto &n1 = i ? new_bounds.ny1 : new_bounds.nx1;
+            auto &change = axis.already_bounds_changed.at(idx);
+            // Lower bound
+            if (new_pos < b0) {
+                // Further out than current lower bound
+                b0 = new_pos;
+                n0 = 1;
+                if (change == NO_CHANGE) {
+                    change = CELL_MOVED_OUTWARDS;
+                    axis.bounds_changed_nets.push_back(idx);
+                }
+            } else if (new_pos == b0 && old_pos > b0) {
+                // Moved from inside into current bound
+                ++n0;
+                if (change == NO_CHANGE) {
+                    change = CELL_MOVED_OUTWARDS;
+                    axis.bounds_changed_nets.push_back(idx);
+                }
+            } else if (old_pos == b0 && new_pos > b0) {
+                // Moved from current bound to inside
+                if (change == NO_CHANGE)
+                    axis.bounds_changed_nets.push_back(idx);
+                if (n0 == 1) {
+                    // Was the last cell on the bound; have to do a full recompute
+                    change = FULL_RECOMPUTE;
+                } else {
+                    --n0;
+                    if (change == NO_CHANGE)
+                        change = CELL_MOVED_INWARDS;
+                }
+            }
+            // Upper bound
+            if (new_pos > b1) {
+                // Further out than current upper bound
+                b1 = new_pos;
+                n1 = new_pos;
+                if (change == NO_CHANGE) {
+                    change = CELL_MOVED_OUTWARDS;
+                    axis.bounds_changed_nets.push_back(idx);
+                }
+            } else if (new_pos == b1 && old_pos < b1) {
+                // Moved onto current bound
+                ++n1;
+                if (change == NO_CHANGE) {
+                    change = CELL_MOVED_OUTWARDS;
+                    axis.bounds_changed_nets.push_back(idx);
+                }
+            } else if (old_pos == b1 && new_pos < b1) {
+                // Moved from current bound to inside
+                if (change == NO_CHANGE)
+                    axis.bounds_changed_nets.push_back(idx);
+                if (n1 == 1) {
+                    // Was the last cell on the bound; have to do a full recompute
+                    change = FULL_RECOMPUTE;
+                } else {
+                    --n1;
+                    if (change == NO_CHANGE)
+                        change = CELL_MOVED_INWARDS;
+                }
+            }
+        }
+        // Timing updates if timing driven
+        if (g.base_cfg.timing_driven && !tmg_ignored_nets.at(idx)) {
+            if (port.second.type == PORT_OUT) {
+                int cc;
+                TimingPortClass cls = ctx->getPortTimingClass(cell, port.first, cc);
+                if (cls != TMG_IGNORE) {
+                    for (auto usr : pn->users.enumerate())
+                        if (!already_timing_changed.at(idx).at(usr.index.idx())) {
+                            timing_changed_arcs.emplace_back(std::make_pair(idx, usr.index));
+                            already_timing_changed.at(idx).at(usr.index.idx()) = true;
+                        }
+                }
+            } else {
+                auto usr = port.second.user_idx;
+                if (!already_timing_changed.at(idx).at(usr.idx())) {
+                    timing_changed_arcs.emplace_back(std::make_pair(idx, usr));
+                    already_timing_changed.at(idx).at(usr.idx()) = true;
+                }
+            }
+        }
+    }
+}
+
+void DetailPlacerThreadState::compute_total_change()
+{
+    auto &xa = axes.at(0), &ya = axes.at(1);
+    for (auto &bc : xa.bounds_changed_nets)
+        if (xa.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
+            new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
+    for (auto &bc : ya.bounds_changed_nets)
+        if (xa.already_bounds_changed.at(bc) != FULL_RECOMPUTE && ya.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
+            new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
+    for (auto &bc : xa.bounds_changed_nets)
+        wirelen_delta += (new_net_bounds.at(bc).hpwl(g.base_cfg) - net_bounds.at(bc).hpwl(g.base_cfg));
+    for (auto &bc : ya.bounds_changed_nets)
+        if (xa.already_bounds_changed.at(bc) == NO_CHANGE)
+            wirelen_delta += (new_net_bounds.at(bc).hpwl(g.base_cfg) - net_bounds.at(bc).hpwl(g.base_cfg));
+    if (g.base_cfg.timing_driven) {
+        NPNR_ASSERT(new_timing_costs.empty());
+        for (auto arc : timing_changed_arcs) {
+            double new_cost = g.get_timing_cost(thread_nets.at(arc.first), arc.second, &local_cell2bel);
+            timing_delta += (new_cost - arc_tmg_cost.at(arc.first).at(arc.second.idx()));
+            new_timing_costs.push_back(new_cost);
+        }
+    }
+}
+
+void DetailPlacerThreadState::reset_move_state()
+{
+    moved_cells.clear();
+    cell_rel.clear();
+    for (auto &axis : axes) {
+        for (auto bc : axis.bounds_changed_nets) {
+            new_net_bounds.at(bc) = net_bounds.at(bc);
+            axis.already_bounds_changed[bc] = NO_CHANGE;
+        }
+        axis.bounds_changed_nets.clear();
+    }
+    for (auto &arc : timing_changed_arcs) {
+        already_timing_changed.at(arc.first).at(arc.second.idx()) = false;
+    }
+    timing_changed_arcs.clear();
+    new_timing_costs.clear();
+    wirelen_delta = 0;
+    timing_delta = 0;
+}
+
+bool DetailPlacerThreadState::add_to_move(CellInfo *cell, BelId old_bel, BelId new_bel)
+{
+    if (!bounds_check(old_bel) || !bounds_check(new_bel))
+        return false;
+    if (!ctx->isValidBelForCellType(cell->type, new_bel))
+        return false;
+    NPNR_ASSERT(!moved_cells.count(cell->name));
+    moved_cells[cell->name] = std::make_pair(old_bel, new_bel);
+    local_cell2bel[cell->name] = new_bel;
+    compute_changes_for_cell(cell, old_bel, new_bel);
+    return true;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/place/detail_place_core.h b/common/place/detail_place_core.h
new file mode 100644
index 0000000000..1c280f24b7
--- /dev/null
+++ b/common/place/detail_place_core.h
@@ -0,0 +1,224 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/*
+This provides core data structures for a thread-safe detail placer that needs to swap cells and evaluate the cost
+changes of swaps.
+
+It works on a partition-based threading approach; although threading can be avoided by only instantiating one
+per-thread structure and calling its methods from the main thread.
+
+Each thread's data includes its own local net indexing for nets inside the partition (which can overlap thread
+boundaries); and its own local cell-to-bel mapping for any cells on those nets, so there are no races with moves
+made by other threads.
+
+A move is an atomic transaction of updated cell to bel mappings inside a thread. The first step is to reset the
+per-move structures; then to add all of the moved cells to the move with add_to_move.
+
+Evaluation of wirelength and timing changes of a move is done with compute_changes_for_cell and compute_total_change.
+
+bind_move will probationally bind the move using the arch API functions, acquiring a lock during this time to prevent
+races on non-thread-safe arch implementations, returning true if the bind succeeded or false if something went wrong
+and it should be aborted. check_validity must then be called to use the arch API validity check functions on the move.
+
+Finally if the move meets criteria and is accepted then commit_move marks it as committed, otherwise revert_move
+aborts the entire move transaction.
+*/
+
+#ifndef DETAIL_PLACE_CORE_H
+#define DETAIL_PLACE_CORE_H
+
+#include "nextpnr.h"
+
+#include "detail_place_cfg.h"
+#include "fast_bels.h"
+#include "timing.h"
+
+#include <queue>
+
+#if !defined(__wasm)
+#include <shared_mutex>
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct PlacePartition
+{
+    int x0, y0, x1, y1;
+    std::vector<CellInfo *> cells;
+    PlacePartition() = default;
+    explicit PlacePartition(Context *ctx);
+    void split(Context *ctx, bool yaxis, float pivot, PlacePartition &l, PlacePartition &r);
+};
+
+typedef int64_t wirelen_t;
+
+struct NetBB
+{
+    // Actual bounding box
+    int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
+    // Number of cells at each extremity
+    int nx0 = 0, nx1 = 0, ny0 = 0, ny1 = 0;
+    inline wirelen_t hpwl(const DetailPlaceCfg &cfg) const
+    {
+        return wirelen_t(cfg.hpwl_scale_x * (x1 - x0) + cfg.hpwl_scale_y * (y1 - y0));
+    }
+    static NetBB compute(const Context *ctx, const NetInfo *net, const dict<IdString, BelId> *cell2bel = nullptr);
+};
+
+struct DetailPlacerState
+{
+    explicit DetailPlacerState(Context *ctx, DetailPlaceCfg &cfg)
+            : ctx(ctx), base_cfg(cfg), bels(ctx, false, 64), tmg(ctx){};
+    Context *ctx;
+    DetailPlaceCfg &base_cfg;
+    FastBels bels;
+    std::vector<NetInfo *> flat_nets; // flat array of all nets in the design for fast referencing by index
+    std::vector<NetBB> last_bounds;
+    std::vector<std::vector<double>> last_tmg_costs;
+    dict<IdString, NetBB> region_bounds;
+    TimingAnalyser tmg;
+
+    wirelen_t total_wirelen = 0;
+    double total_timing_cost = 0;
+
+#if !defined(__wasm)
+    std::shared_timed_mutex archapi_mutex;
+#endif
+
+    inline double get_timing_cost(const NetInfo *net, store_index<PortRef> user,
+                                  const dict<IdString, BelId> *cell2bel = nullptr)
+    {
+        if (!net->driver.cell)
+            return 0;
+        const auto &sink = net->users.at(user);
+        IdString driver_pin, sink_pin;
+        // Pick the first pin for a prediction; assume all will be similar enouhg
+        for (auto pin : ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port)) {
+            driver_pin = pin;
+            break;
+        }
+        for (auto pin : ctx->getBelPinsForCellPin(sink.cell, sink.port)) {
+            sink_pin = pin;
+            break;
+        }
+        float crit = tmg.get_criticality(CellPortKey(sink));
+        BelId src_bel = cell2bel ? cell2bel->at(net->driver.cell->name) : net->driver.cell->bel;
+        BelId dst_bel = cell2bel ? cell2bel->at(sink.cell->name) : sink.cell->bel;
+        double delay = ctx->getDelayNS(ctx->predictDelay(src_bel, driver_pin, dst_bel, sink_pin));
+        return delay * std::pow(crit, base_cfg.crit_exp);
+    }
+
+    inline bool skip_net(const NetInfo *net) const
+    {
+        if (!net->driver.cell)
+            return true;
+        if (ctx->getBelGlobalBuf(net->driver.cell->bel))
+            return true;
+        return false;
+    }
+
+    inline bool timing_skip_net(const NetInfo *net) const
+    {
+        if (!net->driver.cell)
+            return true;
+        int cc;
+        auto cls = ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc);
+        if (cls == TMG_IGNORE || cls == TMG_GEN_CLOCK)
+            return true;
+        return false;
+    }
+
+    void update_global_costs();
+};
+
+struct DetailPlacerThreadState
+{
+    Context *ctx;         // Nextpnr context pointer
+    DetailPlacerState &g; // Placer engine state
+    int idx;              // Index of the thread
+    DeterministicRNG rng; // Local RNG
+    // The cell partition that the thread works on
+    PlacePartition p;
+    // Mapping from design-wide net index to thread-wide net index -- not all nets are in all partitions, so we can
+    // optimise
+    std::vector<int> thread_net_idx;
+    // List of nets inside the partition; and their committed bounding boxes & timing costs from the thread's
+    // perspective
+    std::vector<NetInfo *> thread_nets;
+    std::vector<NetBB> net_bounds;
+    std::vector<std::vector<double>> arc_tmg_cost;
+    std::vector<bool> ignored_nets, tmg_ignored_nets;
+    bool arch_state_dirty = false;
+    // Our local cell-bel map; that won't be affected by out-of-partition moves
+    dict<IdString, BelId> local_cell2bel;
+
+    // Data on an inflight move
+    dict<IdString, std::pair<BelId, BelId>> moved_cells; // cell -> (old; new)
+    // For cluster moves only
+    std::vector<std::pair<CellInfo *, Loc>> cell_rel;
+    // For incremental wirelength and delay updates
+    wirelen_t wirelen_delta = 0;
+    double timing_delta = 0;
+    // Wirelen related are handled on a per-axis basis to reduce
+    enum BoundChange
+    {
+        NO_CHANGE,
+        CELL_MOVED_INWARDS,
+        CELL_MOVED_OUTWARDS,
+        FULL_RECOMPUTE
+    };
+    struct AxisChanges
+    {
+        std::vector<int> bounds_changed_nets;
+        std::vector<BoundChange> already_bounds_changed;
+    };
+    std::array<AxisChanges, 2> axes;
+    std::vector<NetBB> new_net_bounds;
+
+    std::vector<std::vector<bool>> already_timing_changed;
+    std::vector<std::pair<int, store_index<PortRef>>> timing_changed_arcs;
+    std::vector<double> new_timing_costs;
+
+    DetailPlacerThreadState(Context *ctx, DetailPlacerState &g, int idx) : ctx(ctx), g(g), idx(idx){};
+    void set_partition(const PlacePartition &part);
+    void setup_initial_state();
+    bool bounds_check(BelId bel);
+
+    // Reset the inflight move state
+    void reset_move_state();
+    // Add a cell change to the move
+    bool add_to_move(CellInfo *cell, BelId old_bel, BelId new_bel);
+    // For an inflight move; attempt to actually apply the changes to the arch API
+    bool bind_move();
+    // Checks if the arch API bel validity for a move is accepted
+    bool check_validity();
+    // Undo any changes relating to an inflight move
+    void revert_move();
+    // Mark the inflight move as complete and update cost structures
+    void commit_move();
+    // Update the inflight cost change structures for a given cell moe
+    void compute_changes_for_cell(CellInfo *cell, BelId old_bel, BelId new_bel);
+    // Update the total cost change for an inflight move
+    void compute_total_change();
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index a868ca582f..a2de5b1365 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -22,9 +22,8 @@
 
 #if !defined(__wasm)
 
-#include "fast_bels.h"
+#include "detail_place_core.h"
 #include "scope_lock.h"
-#include "timing.h"
 
 #include <chrono>
 #include <mutex>
@@ -35,515 +34,24 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
-struct Partition
-{
-    int x0, y0, x1, y1;
-    std::vector<CellInfo *> cells;
-    Partition() = default;
-    explicit Partition(Context *ctx)
-    {
-        x0 = ctx->getGridDimX();
-        y0 = ctx->getGridDimY();
-        x1 = 0;
-        y1 = 0;
-        for (auto &cell : ctx->cells) {
-            Loc l = ctx->getBelLocation(cell.second->bel);
-            x0 = std::min(x0, l.x);
-            x1 = std::max(x1, l.x);
-            y0 = std::min(y0, l.y);
-            y1 = std::max(y1, l.y);
-            cells.push_back(cell.second.get());
-        }
-    }
-    void split(Context *ctx, bool yaxis, float pivot, Partition &l, Partition &r)
-    {
-        std::sort(cells.begin(), cells.end(), [&](CellInfo *a, CellInfo *b) {
-            Loc l0 = ctx->getBelLocation(a->bel), l1 = ctx->getBelLocation(b->bel);
-            return yaxis ? (l0.y < l1.y) : (l0.x < l1.x);
-        });
-        size_t pivot_point = size_t(cells.size() * pivot);
-        l.cells.clear();
-        r.cells.clear();
-        l.cells.reserve(pivot_point);
-        r.cells.reserve(cells.size() - pivot_point);
-        int pivot_coord = (pivot_point == 0) ? (yaxis ? y1 : x1)
-                                             : (yaxis ? ctx->getBelLocation(cells.at(pivot_point - 1)->bel).y
-                                                      : ctx->getBelLocation(cells.at(pivot_point - 1)->bel).x);
-        for (size_t i = 0; i < cells.size(); i++) {
-            Loc loc = ctx->getBelLocation(cells.at(i)->bel);
-            ((yaxis ? loc.y : loc.x) <= pivot_coord ? l.cells : r.cells).push_back(cells.at(i));
-        }
-        if (yaxis) {
-            l.x0 = r.x0 = x0;
-            l.x1 = r.x1 = x1;
-            l.y0 = y0;
-            l.y1 = pivot_coord;
-            r.y0 = (pivot_coord == y1) ? y1 : (pivot_coord + 1);
-            r.y1 = y1;
-        } else {
-            l.y0 = r.y0 = y0;
-            l.y1 = r.y1 = y1;
-            l.x0 = x0;
-            l.x1 = pivot_coord;
-            r.x0 = (pivot_coord == x1) ? x1 : (pivot_coord + 1);
-            r.x1 = x1;
-        }
-    }
-};
 
-typedef int64_t wirelen_t;
-
-struct NetBB
+struct GlobalState : DetailPlacerState
 {
-    // Actual bounding box
-    int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
-    // Number of cells at each extremity
-    int nx0 = 0, nx1 = 0, ny0 = 0, ny1 = 0;
-    wirelen_t hpwl(const ParallelRefineCfg &cfg) const
-    {
-        return wirelen_t(cfg.hpwl_scale_x * (x1 - x0) + cfg.hpwl_scale_y * (y1 - y0));
-    }
-    static NetBB compute(const Context *ctx, const NetInfo *net, const dict<IdString, BelId> *cell2bel = nullptr)
-    {
-        NetBB result{};
-        if (!net->driver.cell)
-            return result;
-        auto bel_loc = [&](const CellInfo *cell) {
-            BelId bel = cell2bel ? cell2bel->at(cell->name) : cell->bel;
-            return ctx->getBelLocation(bel);
-        };
-        result.nx0 = result.nx1 = result.ny0 = result.ny1 = 1;
-        Loc drv_loc = bel_loc(net->driver.cell);
-        result.x0 = result.x1 = drv_loc.x;
-        result.y0 = result.y1 = drv_loc.y;
-        for (auto &usr : net->users) {
-            Loc l = bel_loc(usr.cell);
-            if (l.x == result.x0)
-                ++result.nx0; // on the edge
-            else if (l.x < result.x0) {
-                result.x0 = l.x; // extends the edge
-                result.nx0 = 1;
-            }
-            if (l.x == result.x1)
-                ++result.nx1; // on the edge
-            else if (l.x > result.x1) {
-                result.x1 = l.x; // extends the edge
-                result.nx1 = 1;
-            }
-            if (l.y == result.y0)
-                ++result.ny0; // on the edge
-            else if (l.y < result.y0) {
-                result.y0 = l.y; // extends the edge
-                result.ny0 = 1;
-            }
-            if (l.y == result.y1)
-                ++result.ny1; // on the edge
-            else if (l.y > result.y1) {
-                result.y1 = l.y; // extends the edge
-                result.ny1 = 1;
-            }
-        }
-        return result;
-    }
-};
+    explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : DetailPlacerState(ctx, this->cfg), cfg(cfg){};
 
-struct GlobalState
-{
-    explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : ctx(ctx), cfg(cfg), bels(ctx, false, 64), tmg(ctx){};
-    Context *ctx;
     ParallelRefineCfg cfg;
-    FastBels bels;
-    std::vector<NetInfo *> flat_nets; // flat array of all nets in the design for fast referencing by index
-    std::vector<NetBB> last_bounds;
-    std::vector<std::vector<double>> last_tmg_costs;
-    dict<IdString, NetBB> region_bounds;
-    TimingAnalyser tmg;
-
-    std::shared_timed_mutex archapi_mutex;
-
     double temperature = 1e-7;
     int radius = 3;
-
-    wirelen_t total_wirelen = 0;
-    double total_timing_cost = 0;
-
-    double get_timing_cost(const NetInfo *net, store_index<PortRef> user,
-                           const dict<IdString, BelId> *cell2bel = nullptr)
-    {
-        if (!net->driver.cell)
-            return 0;
-        const auto &sink = net->users.at(user);
-        IdString driver_pin, sink_pin;
-        // Pick the first pin for a prediction; assume all will be similar enouhg
-        for (auto pin : ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port)) {
-            driver_pin = pin;
-            break;
-        }
-        for (auto pin : ctx->getBelPinsForCellPin(sink.cell, sink.port)) {
-            sink_pin = pin;
-            break;
-        }
-        float crit = tmg.get_criticality(CellPortKey(sink));
-        BelId src_bel = cell2bel ? cell2bel->at(net->driver.cell->name) : net->driver.cell->bel;
-        BelId dst_bel = cell2bel ? cell2bel->at(sink.cell->name) : sink.cell->bel;
-        double delay = ctx->getDelayNS(ctx->predictDelay(src_bel, driver_pin, dst_bel, sink_pin));
-        return delay * std::pow(crit, cfg.crit_exp);
-    }
-
-    bool skip_net(const NetInfo *net) const
-    {
-        if (!net->driver.cell)
-            return true;
-        if (ctx->getBelGlobalBuf(net->driver.cell->bel))
-            return true;
-        return false;
-    }
-    bool timing_skip_net(const NetInfo *net) const
-    {
-        if (!net->driver.cell)
-            return true;
-        int cc;
-        auto cls = ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc);
-        if (cls == TMG_IGNORE || cls == TMG_GEN_CLOCK)
-            return true;
-        return false;
-    }
     // ....
 };
 
-struct ThreadState
+struct ThreadState : DetailPlacerThreadState
 {
-    Context *ctx;         // Nextpnr context pointer
-    GlobalState &g;       // Refinement engine state
-    int idx;              // Index of the thread
-    DeterministicRNG rng; // Local RNG
-    // The cell partition that the thread works on
-    Partition p;
-    // Mapping from design-wide net index to thread-wide net index -- not all nets are in all partitions, so we can
-    // optimise
-    std::vector<int> thread_net_idx;
-    // List of nets inside the partition; and their committed bounding boxes & timing costs from the thread's
-    // perspective
-    std::vector<NetInfo *> thread_nets;
-    std::vector<NetBB> net_bounds;
-    std::vector<std::vector<double>> arc_tmg_cost;
-    std::vector<bool> ignored_nets, tmg_ignored_nets;
-    bool arch_state_dirty = false;
-    // Our local cell-bel map; that won't be affected by out-of-partition moves
-    dict<IdString, BelId> local_cell2bel;
-
-    // Data on an inflight move
-    dict<IdString, std::pair<BelId, BelId>> moved_cells; // cell -> (old; new)
-    // For cluster moves only
-    std::vector<std::pair<CellInfo *, Loc>> cell_rel;
-    // For incremental wirelength and delay updates
-    wirelen_t wirelen_delta = 0;
-    double timing_delta = 0;
-
+    ThreadState(Context *ctx, GlobalState &g, int idx) : DetailPlacerThreadState(ctx, g, idx), g(g){};
     // Total made and accepted moved
+    GlobalState &g;
     int n_move = 0, n_accept = 0;
 
-    enum BoundChange
-    {
-        NO_CHANGE,
-        CELL_MOVED_INWARDS,
-        CELL_MOVED_OUTWARDS,
-        FULL_RECOMPUTE
-    };
-    // Wirelen related are handled on a per-axis basis to reduce
-    struct AxisChanges
-    {
-        std::vector<int> bounds_changed_nets;
-        std::vector<BoundChange> already_bounds_changed;
-    };
-    std::array<AxisChanges, 2> axes;
-    std::vector<NetBB> new_net_bounds;
-
-    std::vector<std::vector<bool>> already_timing_changed;
-    std::vector<std::pair<int, store_index<PortRef>>> timing_changed_arcs;
-    std::vector<double> new_timing_costs;
-
-    ThreadState(Context *ctx, GlobalState &g, int idx) : ctx(ctx), g(g), idx(idx){};
-    void set_partition(const Partition &part)
-    {
-        p = part;
-        thread_nets.clear();
-        thread_net_idx.resize(g.flat_nets.size());
-        std::fill(thread_net_idx.begin(), thread_net_idx.end(), -1);
-        // Determine the set of nets that are within the thread; and therefore we care about
-        for (auto thread_cell : part.cells) {
-            for (auto &port : thread_cell->ports) {
-                if (!port.second.net)
-                    continue;
-                int global_idx = port.second.net->udata;
-                auto &thread_idx = thread_net_idx.at(global_idx);
-                // Already added to the set
-                if (thread_idx != -1)
-                    continue;
-                thread_idx = thread_nets.size();
-                thread_nets.push_back(port.second.net);
-            }
-        }
-        tmg_ignored_nets.clear();
-        ignored_nets.clear();
-        for (auto tn : thread_nets) {
-            ignored_nets.push_back(g.skip_net(tn));
-            tmg_ignored_nets.push_back(g.timing_skip_net(tn));
-        }
-        // Set up the original cell-bel map for all nets inside the thread
-        local_cell2bel.clear();
-        for (NetInfo *net : thread_nets) {
-            if (net->driver.cell)
-                local_cell2bel[net->driver.cell->name] = net->driver.cell->bel;
-            for (auto &usr : net->users)
-                local_cell2bel[usr.cell->name] = usr.cell->bel;
-        }
-    }
-    void setup_initial_state()
-    {
-        // Setup initial net bounding boxes and timing costs
-        net_bounds.clear();
-        arc_tmg_cost.clear();
-        for (auto tn : thread_nets) {
-            net_bounds.push_back(g.last_bounds.at(tn->udata));
-            arc_tmg_cost.push_back(g.last_tmg_costs.at(tn->udata));
-        }
-        new_net_bounds = net_bounds;
-        for (int j = 0; j < 2; j++) {
-            auto &a = axes.at(j);
-            a.already_bounds_changed.resize(net_bounds.size());
-        }
-        already_timing_changed.clear();
-        already_timing_changed.resize(net_bounds.size());
-        for (size_t i = 0; i < thread_nets.size(); i++)
-            already_timing_changed.at(i) = std::vector<bool>(thread_nets.at(i)->users.capacity());
-    }
-    bool bounds_check(BelId bel)
-    {
-        Loc l = ctx->getBelLocation(bel);
-        if (l.x < p.x0 || l.x > p.x1 || l.y < p.y0 || l.y > p.y1)
-            return false;
-        return true;
-    }
-    bool bind_move()
-    {
-        std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-        for (auto &entry : moved_cells) {
-            ctx->unbindBel(entry.second.first);
-        }
-        bool success = true;
-        for (auto &entry : moved_cells) {
-            // Make sure targets are available before we bind them
-            if (!ctx->checkBelAvail(entry.second.second)) {
-                success = false;
-                break;
-            }
-            ctx->bindBel(entry.second.second, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
-        }
-        arch_state_dirty = true;
-        return success;
-    }
-    bool check_validity()
-    {
-        std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-        bool result = true;
-        for (auto e : moved_cells) {
-            if (!ctx->isBelLocationValid(e.second.first)) {
-                // Have to check old; too; as unbinding a bel could make a placement illegal by virtue of no longer
-                // enabling dedicated routes to be used
-                result = false;
-                break;
-            }
-            if (!ctx->isBelLocationValid(e.second.second)) {
-                result = false;
-                break;
-            }
-        }
-        return result;
-    }
-    void revert_move()
-    {
-        if (arch_state_dirty) {
-            // If changes to the arch state were made, revert them by restoring original cell bindings
-            std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-            for (auto &entry : moved_cells) {
-                BelId curr_bound = ctx->cells.at(entry.first)->bel;
-                if (curr_bound != BelId())
-                    ctx->unbindBel(curr_bound);
-            }
-            for (auto &entry : moved_cells) {
-                ctx->bindBel(entry.second.first, ctx->cells.at(entry.first).get(), STRENGTH_WEAK);
-            }
-            arch_state_dirty = false;
-        }
-        for (auto &entry : moved_cells)
-            local_cell2bel[entry.first] = entry.second.first;
-    }
-    void commit_move()
-    {
-        arch_state_dirty = false;
-        for (auto &axis : axes) {
-            for (auto bc : axis.bounds_changed_nets) {
-                // Commit updated net bounds
-                net_bounds.at(bc) = new_net_bounds.at(bc);
-            }
-        }
-        if (g.cfg.timing_driven) {
-            NPNR_ASSERT(timing_changed_arcs.size() == new_timing_costs.size());
-            for (size_t i = 0; i < timing_changed_arcs.size(); i++) {
-                auto arc = timing_changed_arcs.at(i);
-                arc_tmg_cost.at(arc.first).at(arc.second.idx()) = new_timing_costs.at(i);
-            }
-        }
-    }
-    void compute_changes_for_cell(CellInfo *cell, BelId old_bel, BelId new_bel)
-    {
-        Loc new_loc = ctx->getBelLocation(new_bel);
-        Loc old_loc = ctx->getBelLocation(old_bel);
-        for (const auto &port : cell->ports) {
-            NetInfo *pn = port.second.net;
-            if (!pn)
-                continue;
-            int idx = thread_net_idx.at(pn->udata);
-            if (ignored_nets.at(idx))
-                continue;
-            NetBB &new_bounds = new_net_bounds.at(idx);
-            // For the x-axis (i=0) and y-axis (i=1)
-            for (int i = 0; i < 2; i++) {
-                auto &axis = axes.at(i);
-                // New and old on this axis
-                int new_pos = i ? new_loc.y : new_loc.x, old_pos = i ? old_loc.y : old_loc.x;
-                // References to updated bounding box entries
-                auto &b0 = i ? new_bounds.y0 : new_bounds.x0;
-                auto &n0 = i ? new_bounds.ny0 : new_bounds.nx0;
-                auto &b1 = i ? new_bounds.y1 : new_bounds.x1;
-                auto &n1 = i ? new_bounds.ny1 : new_bounds.nx1;
-                auto &change = axis.already_bounds_changed.at(idx);
-                // Lower bound
-                if (new_pos < b0) {
-                    // Further out than current lower bound
-                    b0 = new_pos;
-                    n0 = 1;
-                    if (change == NO_CHANGE) {
-                        change = CELL_MOVED_OUTWARDS;
-                        axis.bounds_changed_nets.push_back(idx);
-                    }
-                } else if (new_pos == b0 && old_pos > b0) {
-                    // Moved from inside into current bound
-                    ++n0;
-                    if (change == NO_CHANGE) {
-                        change = CELL_MOVED_OUTWARDS;
-                        axis.bounds_changed_nets.push_back(idx);
-                    }
-                } else if (old_pos == b0 && new_pos > b0) {
-                    // Moved from current bound to inside
-                    if (change == NO_CHANGE)
-                        axis.bounds_changed_nets.push_back(idx);
-                    if (n0 == 1) {
-                        // Was the last cell on the bound; have to do a full recompute
-                        change = FULL_RECOMPUTE;
-                    } else {
-                        --n0;
-                        if (change == NO_CHANGE)
-                            change = CELL_MOVED_INWARDS;
-                    }
-                }
-                // Upper bound
-                if (new_pos > b1) {
-                    // Further out than current upper bound
-                    b1 = new_pos;
-                    n1 = new_pos;
-                    if (change == NO_CHANGE) {
-                        change = CELL_MOVED_OUTWARDS;
-                        axis.bounds_changed_nets.push_back(idx);
-                    }
-                } else if (new_pos == b1 && old_pos < b1) {
-                    // Moved onto current bound
-                    ++n1;
-                    if (change == NO_CHANGE) {
-                        change = CELL_MOVED_OUTWARDS;
-                        axis.bounds_changed_nets.push_back(idx);
-                    }
-                } else if (old_pos == b1 && new_pos < b1) {
-                    // Moved from current bound to inside
-                    if (change == NO_CHANGE)
-                        axis.bounds_changed_nets.push_back(idx);
-                    if (n1 == 1) {
-                        // Was the last cell on the bound; have to do a full recompute
-                        change = FULL_RECOMPUTE;
-                    } else {
-                        --n1;
-                        if (change == NO_CHANGE)
-                            change = CELL_MOVED_INWARDS;
-                    }
-                }
-            }
-            // Timing updates if timing driven
-            if (g.cfg.timing_driven && !tmg_ignored_nets.at(idx)) {
-                if (port.second.type == PORT_OUT) {
-                    int cc;
-                    TimingPortClass cls = ctx->getPortTimingClass(cell, port.first, cc);
-                    if (cls != TMG_IGNORE) {
-                        for (auto usr : pn->users.enumerate())
-                            if (!already_timing_changed.at(idx).at(usr.index.idx())) {
-                                timing_changed_arcs.emplace_back(std::make_pair(idx, usr.index));
-                                already_timing_changed.at(idx).at(usr.index.idx()) = true;
-                            }
-                    }
-                } else {
-                    auto usr = port.second.user_idx;
-                    if (!already_timing_changed.at(idx).at(usr.idx())) {
-                        timing_changed_arcs.emplace_back(std::make_pair(idx, usr));
-                        already_timing_changed.at(idx).at(usr.idx()) = true;
-                    }
-                }
-            }
-        }
-    }
-    void compute_total_change()
-    {
-        auto &xa = axes.at(0), &ya = axes.at(1);
-        for (auto &bc : xa.bounds_changed_nets)
-            if (xa.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
-                new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
-        for (auto &bc : ya.bounds_changed_nets)
-            if (xa.already_bounds_changed.at(bc) != FULL_RECOMPUTE &&
-                ya.already_bounds_changed.at(bc) == FULL_RECOMPUTE)
-                new_net_bounds.at(bc) = NetBB::compute(ctx, thread_nets.at(bc), &local_cell2bel);
-        for (auto &bc : xa.bounds_changed_nets)
-            wirelen_delta += (new_net_bounds.at(bc).hpwl(g.cfg) - net_bounds.at(bc).hpwl(g.cfg));
-        for (auto &bc : ya.bounds_changed_nets)
-            if (xa.already_bounds_changed.at(bc) == NO_CHANGE)
-                wirelen_delta += (new_net_bounds.at(bc).hpwl(g.cfg) - net_bounds.at(bc).hpwl(g.cfg));
-        if (g.cfg.timing_driven) {
-            NPNR_ASSERT(new_timing_costs.empty());
-            for (auto arc : timing_changed_arcs) {
-                double new_cost = g.get_timing_cost(thread_nets.at(arc.first), arc.second, &local_cell2bel);
-                timing_delta += (new_cost - arc_tmg_cost.at(arc.first).at(arc.second.idx()));
-                new_timing_costs.push_back(new_cost);
-            }
-        }
-    }
-    void reset_move_state()
-    {
-        moved_cells.clear();
-        cell_rel.clear();
-        for (auto &axis : axes) {
-            for (auto bc : axis.bounds_changed_nets) {
-                new_net_bounds.at(bc) = net_bounds.at(bc);
-                axis.already_bounds_changed[bc] = NO_CHANGE;
-            }
-            axis.bounds_changed_nets.clear();
-        }
-        for (auto &arc : timing_changed_arcs) {
-            already_timing_changed.at(arc.first).at(arc.second.idx()) = false;
-        }
-        timing_changed_arcs.clear();
-        new_timing_costs.clear();
-        wirelen_delta = 0;
-        timing_delta = 0;
-    }
-
     bool accept_move()
     {
         static constexpr double epsilon = 1e-20;
@@ -553,19 +61,6 @@ struct ThreadState
                (g.temperature > 1e-8 && (rng.rng() / float(0x3fffffff)) <= std::exp(-delta / g.temperature));
     }
 
-    bool add_to_move(CellInfo *cell, BelId old_bel, BelId new_bel)
-    {
-        if (!bounds_check(old_bel) || !bounds_check(new_bel))
-            return false;
-        if (!ctx->isValidBelForCellType(cell->type, new_bel))
-            return false;
-        NPNR_ASSERT(!moved_cells.count(cell->name));
-        moved_cells[cell->name] = std::make_pair(old_bel, new_bel);
-        local_cell2bel[cell->name] = new_bel;
-        compute_changes_for_cell(cell, old_bel, new_bel);
-        return true;
-    }
-
     bool single_cell_swap(CellInfo *cell, BelId new_bel)
     {
         NPNR_ASSERT(moved_cells.empty());
@@ -806,14 +301,14 @@ struct ParallelRefine
             g.bels.addCellType(cell_type);
         }
     };
-    std::vector<Partition> parts;
+    std::vector<PlacePartition> parts;
     void do_partition()
     {
         parts.clear();
         parts.emplace_back(ctx);
         bool yaxis = false;
         while (parts.size() < t.size()) {
-            std::vector<Partition> next(parts.size() * 2);
+            std::vector<PlacePartition> next(parts.size() * 2);
             for (size_t i = 0; i < parts.size(); i++) {
                 // Randomly permute pivot every iteration so we get different thread boundaries
                 const float delta = 0.1;
@@ -834,28 +329,6 @@ struct ParallelRefine
             w.join();
     }
 
-    void update_global_costs()
-    {
-        g.last_bounds.resize(g.flat_nets.size());
-        g.last_tmg_costs.resize(g.flat_nets.size());
-        g.total_wirelen = 0;
-        g.total_timing_cost = 0;
-        for (size_t i = 0; i < g.flat_nets.size(); i++) {
-            NetInfo *ni = g.flat_nets.at(i);
-            if (g.skip_net(ni))
-                continue;
-            g.last_bounds.at(i) = NetBB::compute(ctx, ni);
-            g.total_wirelen += g.last_bounds.at(i).hpwl(g.cfg);
-            if (!g.timing_skip_net(ni)) {
-                auto &tc = g.last_tmg_costs.at(i);
-                tc.resize(ni->users.capacity());
-                for (auto usr : ni->users.enumerate()) {
-                    tc.at(usr.index.idx()) = g.get_timing_cost(ni, usr.index);
-                    g.total_timing_cost += tc.at(usr.index.idx());
-                }
-            }
-        }
-    }
     void run()
     {
 
@@ -868,7 +341,7 @@ struct ParallelRefine
         log_info("Running parallel refinement with %d threads.\n", int(t.size()));
         int iter = 1;
         bool done = false;
-        update_global_costs();
+        g.update_global_costs();
         double avg_wirelen = g.total_wirelen;
         wirelen_t min_wirelen = g.total_wirelen;
         while (true) {
@@ -914,7 +387,7 @@ struct ParallelRefine
             for (auto &w : workers)
                 w.join();
             g.tmg.run();
-            update_global_costs();
+            g.update_global_costs();
             iter++;
             ctx->yield();
         }
@@ -924,17 +397,14 @@ struct ParallelRefine
 };
 } // namespace
 
-ParallelRefineCfg::ParallelRefineCfg(Context *ctx)
+ParallelRefineCfg::ParallelRefineCfg(Context *ctx) : DetailPlaceCfg(ctx)
 {
-    timing_driven = ctx->setting<bool>("timing_driven");
     threads = ctx->setting<int>("threads", 8);
     // snap to nearest power of two; and minimum thread size
     int actual_threads = 1;
     while ((actual_threads * 2) <= threads && (int(ctx->cells.size()) / (actual_threads * 2)) >= min_thread_size)
         actual_threads *= 2;
     threads = actual_threads;
-    hpwl_scale_x = 1;
-    hpwl_scale_y = 1;
 }
 
 bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
diff --git a/common/place/parallel_refine.h b/common/place/parallel_refine.h
index 556317cd19..a6c8b469bf 100644
--- a/common/place/parallel_refine.h
+++ b/common/place/parallel_refine.h
@@ -20,18 +20,16 @@
 #ifndef PARALLEL_REFINE_H
 #define PARALLEL_REFINE_H
 
+#include "detail_place_cfg.h"
 #include "nextpnr.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-struct ParallelRefineCfg
+struct ParallelRefineCfg : DetailPlaceCfg
 {
     ParallelRefineCfg(Context *ctx);
-    bool timing_driven;
     int threads;
-    int hpwl_scale_x, hpwl_scale_y;
     double lambda = 0.5f;
-    float crit_exp = 8;
     int inner_iters = 15;
     int min_thread_size = 500;
 };

From 19cade3b3b84ac7bfa07aa9eb8f47866dcd52d4e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 19 Apr 2022 14:28:07 +0100
Subject: [PATCH 134/712] prefine: Do full-tile swaps, too

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/detail_place_core.cc |  2 +-
 common/place/parallel_refine.cc   | 99 +++++++++++++++++++++++++++++++
 2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/common/place/detail_place_core.cc b/common/place/detail_place_core.cc
index bb3836394b..7e629f24e1 100644
--- a/common/place/detail_place_core.cc
+++ b/common/place/detail_place_core.cc
@@ -348,7 +348,7 @@ void DetailPlacerThreadState::compute_changes_for_cell(CellInfo *cell, BelId old
             if (new_pos > b1) {
                 // Further out than current upper bound
                 b1 = new_pos;
-                n1 = new_pos;
+                n1 = 1;
                 if (change == NO_CHANGE) {
                     change = CELL_MOVED_OUTWARDS;
                     axis.bounds_changed_nets.push_back(idx);
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index a2de5b1365..de71b8e093 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -39,6 +39,8 @@ struct GlobalState : DetailPlacerState
 {
     explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : DetailPlacerState(ctx, this->cfg), cfg(cfg){};
 
+    dict<ClusterId, std::vector<CellInfo *>> cluster2cells;
+
     ParallelRefineCfg cfg;
     double temperature = 1e-7;
     int radius = 3;
@@ -52,6 +54,8 @@ struct ThreadState : DetailPlacerThreadState
     GlobalState &g;
     int n_move = 0, n_accept = 0;
 
+    dict<std::pair<int, int>, std::vector<CellInfo *>> tile2cell;
+
     bool accept_move()
     {
         static constexpr double epsilon = 1e-20;
@@ -218,6 +222,97 @@ struct ThreadState : DetailPlacerThreadState
         }
     }
 
+    bool cluster_inside_tile(ClusterId cluster, int x, int y)
+    {
+        for (auto &c : g.cluster2cells.at(cluster)) {
+            Loc l = ctx->getBelLocation(c->bel);
+            if (l.x != x || l.y != y)
+                return false;
+        }
+        return true;
+    }
+
+    bool do_tile_swap(int x, int y, int xn, int yn)
+    {
+        if (xn < p.x0 || xn > p.x1)
+            return false;
+        if (yn < p.y0 || yn > p.y1)
+            return false;
+        if ((x == xn) && (y == yn))
+            return false;
+
+        NPNR_ASSERT(moved_cells.empty());
+
+        auto move_tile = [&](int sx, int sy, int dx, int dy) -> bool {
+            for (auto c : tile2cell[std::make_pair(sx, sy)]) {
+                if (c->belStrength > STRENGTH_STRONG ||
+                    ((c->cluster != ClusterId()) && !cluster_inside_tile(c->cluster, sx, sy)))
+                    return false; // check clusters before we start moving stuff
+            }
+            for (auto c : tile2cell[std::make_pair(sx, sy)]) {
+                Loc l = ctx->getBelLocation(c->bel);
+                l.x = dx;
+                l.y = dy;
+                BelId new_bel = ctx->getBelByLocation(l);
+                if (new_bel == BelId() || !ctx->isValidBelForCellType(c->type, new_bel))
+                    return false;
+                if (!add_to_move(c, c->bel, new_bel))
+                    return false;
+            }
+            return true;
+        };
+
+        if (!move_tile(x, y, xn, yn))
+            goto fail;
+        if (!move_tile(xn, yn, x, y))
+            goto fail;
+
+        compute_total_change();
+        // SA acceptance criteria
+        if (!accept_move()) {
+            // SA fail
+            goto fail;
+        }
+        // Check validity rules
+        if (!bind_move())
+            goto fail;
+        if (!check_validity())
+            goto fail;
+        // Accepted!
+        commit_move();
+        reset_move_state();
+        std::swap(tile2cell[std::make_pair(x, y)], tile2cell[std::make_pair(xn, yn)]);
+        return true;
+    fail:
+        revert_move();
+        reset_move_state();
+        return false;
+    }
+
+    void do_tile_swaps()
+    {
+        tile2cell.clear();
+        for (auto c : p.cells) {
+            auto loc = ctx->getBelLocation(c->bel);
+            tile2cell[std::make_pair(loc.x, loc.y)].push_back(c);
+        }
+        std::vector<std::pair<int, int>> tiles;
+        for (auto &t : tile2cell)
+            tiles.push_back(t.first);
+        rng.shuffle(tiles);
+        for (auto &t : tiles) {
+            int x = t.first, y = t.second;
+            int lx = std::max(x - g.radius, p.x0), rx = std::min(x + g.radius, p.x1);
+            int by = std::max(y - g.radius, p.y0), ty = std::min(y + g.radius, p.y1);
+            int xn = lx + ctx->rng((rx - lx) + 1);
+            int yn = by + ctx->rng((ty - by) + 1);
+            ++n_move;
+            if (do_tile_swap(x, y, xn, yn)) {
+                ++n_accept;
+            }
+        }
+    }
+
     void run_iter()
     {
         setup_initial_state();
@@ -246,6 +341,8 @@ struct ThreadState : DetailPlacerThreadState
                         ++n_accept;
                 }
             }
+            if ((m % 2) == 0)
+                do_tile_swaps();
         }
     }
 };
@@ -295,6 +392,8 @@ struct ParallelRefine
         for (auto &cell : ctx->cells) {
             IdString cell_type = cell.second->type;
             cell_types_in_use.insert(cell_type);
+            if (cell.second->cluster != ClusterId())
+                g.cluster2cells[cell.second->cluster].push_back(cell.second.get());
         }
 
         for (auto cell_type : cell_types_in_use) {

From a35c80cc10c69f88ceddee604ea29f172fbae1c0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 20 Apr 2022 11:29:08 +0100
Subject: [PATCH 135/712] ecp5: Tweak delay prediction

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 50993e2b97..d98ee54cee 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -580,7 +580,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
 
     return (120 - 22 * args.speed) *
-           (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
+           (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const

From 20cfafa109c15ef8f12307cf23f595c893f5a2e1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 27 Apr 2022 14:18:42 +0100
Subject: [PATCH 136/712] generic: Add missing uarch guard

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/generic/arch.cc b/generic/arch.cc
index 0aece64fe0..f622fed3bf 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -390,7 +390,8 @@ void Arch::unbindWire(WireId wire)
         refreshUiPip(pip);
     }
 
-    uarch->notifyWireChange(wire, nullptr);
+    if (uarch)
+        uarch->notifyWireChange(wire, nullptr);
     net_wires.erase(wire);
     wire_info(wire).bound_net = nullptr;
     refreshUiWire(wire);

From f0d4e4fbc3847635e0f6151a9eda52b7fb952c19 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 2 May 2022 09:56:36 +0100
Subject: [PATCH 137/712] generic: Add some extra helpers for viaduct uarches

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.cc            | 24 ++++++++++++++++++++++++
 generic/arch.h             |  4 ++++
 generic/viaduct_helpers.cc | 22 ++++++++++++++++++++--
 generic/viaduct_helpers.h  |  6 ++++--
 4 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/generic/arch.cc b/generic/arch.cc
index f622fed3bf..11b5868b15 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -43,6 +43,30 @@ WireId Arch::addWire(IdStringList name, IdString type, int x, int y)
     return wire;
 }
 
+WireId Arch::addWireAsBelInput(BelId bel, IdString name)
+{
+    Loc l = getBelLocation(bel);
+    WireId w = addWire(IdStringList::concat(getBelName(bel), name), name, l.x, l.y);
+    addBelInput(bel, name, w);
+    return w;
+}
+
+WireId Arch::addWireAsBelOutput(BelId bel, IdString name)
+{
+    Loc l = getBelLocation(bel);
+    WireId w = addWire(IdStringList::concat(getBelName(bel), name), name, l.x, l.y);
+    addBelOutput(bel, name, w);
+    return w;
+}
+
+WireId Arch::addWireAsBelInout(BelId bel, IdString name)
+{
+    Loc l = getBelLocation(bel);
+    WireId w = addWire(IdStringList::concat(getBelName(bel), name), name, l.x, l.y);
+    addBelInout(bel, name, w);
+    return w;
+}
+
 PipId Arch::addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc)
 {
     NPNR_ASSERT(pip_by_name.count(name) == 0);
diff --git a/generic/arch.h b/generic/arch.h
index e96853f1de..157ff8afec 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -201,6 +201,10 @@ struct Arch : BaseArch<ArchRanges>
     void addBelOutput(BelId bel, IdString name, WireId wire);
     void addBelInout(BelId bel, IdString name, WireId wire);
 
+    WireId addWireAsBelInput(BelId bel, IdString name);
+    WireId addWireAsBelOutput(BelId bel, IdString name);
+    WireId addWireAsBelInout(BelId bel, IdString name);
+
     void addGroupBel(IdStringList group, BelId bel);
     void addGroupWire(IdStringList group, WireId wire);
     void addGroupPip(IdStringList group, PipId pip);
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index a92d0de1b2..153d2a0e6a 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -25,9 +25,9 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void ViaductHelpers::resize_ids(int x, int y)
+void ViaductHelpers::resize_ids(int x, int y, int z)
 {
-    NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000);
+    NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000 && z <= 1000);
     while (int(x_ids.size()) <= x) {
         IdString next = ctx->id(stringf("X%d", int(x_ids.size())));
         x_ids.push_back(next);
@@ -36,6 +36,10 @@ void ViaductHelpers::resize_ids(int x, int y)
         IdString next = ctx->id(stringf("Y%d", int(y_ids.size())));
         y_ids.push_back(next);
     }
+    while (int(z_ids.size()) <= y) {
+        IdString next = ctx->id(stringf("Z%d", int(z_ids.size())));
+        z_ids.push_back(next);
+    }
 }
 
 IdStringList ViaductHelpers::xy_id(int x, int y, IdString base)
@@ -52,6 +56,20 @@ IdStringList ViaductHelpers::xy_id(int x, int y, IdStringList base)
     return IdStringList::concat(IdStringList(prefix), base);
 }
 
+IdStringList ViaductHelpers::xyz_id(int x, int y, int z, IdString base)
+{
+    resize_ids(x, y, z);
+    std::array<IdString, 4> result{x_ids.at(x), y_ids.at(y), z_ids.at(z), base};
+    return IdStringList(result);
+}
+
+IdStringList ViaductHelpers::xyz_id(int x, int y, int z, IdStringList base)
+{
+    resize_ids(x, y, z);
+    std::array<IdString, 3> prefix{x_ids.at(x), y_ids.at(y), z_ids.at(z)};
+    return IdStringList::concat(IdStringList(prefix), base);
+}
+
 void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
 {
     std::vector<IdString> to_remove;
diff --git a/generic/viaduct_helpers.h b/generic/viaduct_helpers.h
index cac2230421..213995dba1 100644
--- a/generic/viaduct_helpers.h
+++ b/generic/viaduct_helpers.h
@@ -58,13 +58,15 @@ struct ViaductHelpers
     Context *ctx;
     void init(Context *ctx) { this->ctx = ctx; }
     // IdStringList components for x and y locations
-    std::vector<IdString> x_ids, y_ids;
-    void resize_ids(int x, int y);
+    std::vector<IdString> x_ids, y_ids, z_ids;
+    void resize_ids(int x, int y, int z = 0);
     // Get an IdStringList for a hierarchical ID
     // Because this uses an IdStringList with seperate X and Y components; this will be much more efficient than
     // creating unique strings for each object in each X and Y position
     IdStringList xy_id(int x, int y, IdString base);
     IdStringList xy_id(int x, int y, IdStringList base);
+    IdStringList xyz_id(int x, int y, int z, IdString base);
+    IdStringList xyz_id(int x, int y, int z, IdStringList base);
     // Common packing functions
     // Remove nextpnr-inserted IO buffers; where IO buffer insertion is done in synthesis
     // expects a set of top-level port types

From 15413de3597404d3a68cc95a4b6170004a098ff7 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 2 May 2022 20:40:33 +1000
Subject: [PATCH 138/712] gowin: Add initial syntax support for long wires

Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 34 +++++++++++++++++++++++++++-------
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 7bfef36e8e..4fc2cd4321 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -691,13 +691,15 @@ void Arch::read_cst(std::istream &in)
     std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
     std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
     std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
+    std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])[^;]*;");
     std::smatch match, match_attr, match_pinloc;
     std::string line, pinline;
     enum
     {
         ioloc,
         ioport,
-        insloc
+        insloc,
+        clock
     } cst_type;
 
     settings.erase(id_cst);
@@ -708,24 +710,42 @@ void Arch::read_cst(std::istream &in)
             if (std::regex_match(line, match, portre)) {
                 cst_type = ioport;
             } else {
-                if (std::regex_match(line, match, inslocre)) {
-                    cst_type = insloc;
+                if (std::regex_match(line, match, clockre)) {
+                    cst_type = clock;
                 } else {
-                    if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
-                        log_warning("Invalid constraint: %s\n", line.c_str());
+                    if (std::regex_match(line, match, inslocre)) {
+                        cst_type = insloc;
+                    } else {
+                        if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
+                            log_warning("Invalid constraint: %s\n", line.c_str());
+                        }
+                        continue;
                     }
-                    continue;
                 }
             }
         }
 
         IdString net = id(match[1]);
         auto it = cells.find(net);
-        if (it == cells.end()) {
+        if (cst_type != clock && it == cells.end()) {
             log_info("Cell %s not found\n", net.c_str(this));
             continue;
         }
         switch (cst_type) {
+        case clock: { // CLOCK name BUFG|S
+            std::string which_clock = match[2];
+            if (which_clock.at(0) == 'S') {
+                auto ni = nets.find(net);
+                if (ni == nets.end()) {
+                    log_info("Net %s not found\n", net.c_str(this));
+                    continue;
+                }
+                log_info("Long wires are not implemented. The %s network will use normal routing.\n", net.c_str(this));
+            } else {
+                log_info("BUFG isn't supported\n");
+                continue;
+            }
+        } break;
         case ioloc: { // IO_LOC name pin
             IdString pinname = id(match[2]);
             pinline = match[2];

From 27966f101f52415b671cc794b3926a0fc9e667d7 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 8 May 2022 12:44:03 +0100
Subject: [PATCH 139/712] ice40: Fix propagation of constraints through SB_GB

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/pack.cc | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index 92297e8edd..9eff053e65 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -671,13 +671,6 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
     for (auto &user : keep_users)
         user.cell->ports[user.port].user_idx = net->users.add(user);
 
-    if (net->clkconstr) {
-        glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-        glbnet->clkconstr->low = net->clkconstr->low;
-        glbnet->clkconstr->high = net->clkconstr->high;
-        glbnet->clkconstr->period = net->clkconstr->period;
-    }
-
     ctx->cells[gb->name] = std::move(gb);
 }
 
@@ -803,6 +796,29 @@ static void promote_globals(Context *ctx)
     }
 }
 
+static void copy_gb_constraints(Context *ctx)
+{
+    // Copy constraints through GBs and PLLs
+    bool did_something = false;
+    do {
+        did_something = false;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (!is_gbuf(ctx, ci))
+                continue;
+            NetInfo *in = ci->getPort(id_USER_SIGNAL_TO_GLOBAL_BUFFER);
+            NetInfo *out = ci->getPort(id_GLOBAL_BUFFER_OUTPUT);
+            if (in && out && in->clkconstr && !out->clkconstr) {
+                out->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+                out->clkconstr->low = in->clkconstr->low;
+                out->clkconstr->high = in->clkconstr->high;
+                out->clkconstr->period = in->clkconstr->period;
+                did_something = true;
+            }
+        }
+    } while (did_something);
+}
+
 // Figure out where to place PLLs
 static void place_plls(Context *ctx)
 {
@@ -1711,6 +1727,7 @@ bool Arch::pack()
         pack_plls(ctx);
         if (!bool_or_default(ctx->settings, id_no_promote_globals, false))
             promote_globals(ctx);
+        copy_gb_constraints(ctx);
         ctx->assignArchInfo();
         constrain_chains(ctx);
         ctx->fixupHierarchy();

From 1aa693732c079eab2f3e49d734aef65d73bfe3d0 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 10 May 2022 21:19:02 +1000
Subject: [PATCH 140/712] common: Correct a minor typo in the message

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/kernel/nextpnr_types.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/nextpnr_types.cc b/common/kernel/nextpnr_types.cc
index 57d816c008..82725d6ff5 100644
--- a/common/kernel/nextpnr_types.cc
+++ b/common/kernel/nextpnr_types.cc
@@ -68,7 +68,7 @@ void CellInfo::connectPort(IdString port_name, NetInfo *net)
         user.port = port_name;
         port.user_idx = net->users.add(user);
     } else {
-        NPNR_ASSERT_FALSE("invalid port type for connect_port");
+        NPNR_ASSERT_FALSE("invalid port type for connectPort");
     }
 }
 

From aafe1a176c821a3919e773b57ac08fb348c91597 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Thu, 28 Apr 2022 17:18:26 +0200
Subject: [PATCH 141/712] Generalized representation of unused LUT pins
 connections

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 fpga_interchange/arch.cc                   | 43 ++++++++++--
 fpga_interchange/luts.cc                   | 82 ++++++++++++----------
 fpga_interchange/luts.h                    | 13 +++-
 fpga_interchange/site_arch.cc              | 76 +++++++++++++++++---
 fpga_interchange/site_lut_mapping_cache.cc |  4 +-
 5 files changed, 160 insertions(+), 58 deletions(-)

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index e55c94afe9..05b50ae270 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -874,17 +874,26 @@ static void prepare_sites_for_routing(Context *ctx)
 
     // Fixup LUT vcc pins.
     IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
+    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
+
+    IdString const_net_name(ctx->chip_info->constants->best_constant_net);
+    NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+
     for (BelId bel : ctx->getBels()) {
         CellInfo *cell = ctx->getBoundBelCell(bel);
         if (cell == nullptr) {
             continue;
         }
 
-        if (cell->lut_cell.vcc_pins.empty()) {
-            continue;
-        }
+        for (const auto &it : cell->lut_cell.pin_connections) {
+            const auto &bel_pin = it.first;
+            const auto &conn = it.second;
+
+            // Connected to an active signal or unconnected
+            if (conn == LutCell::PinConnection::Signal || conn == LutCell::PinConnection::Unconnected) {
+                continue;
+            }
 
-        for (auto bel_pin : cell->lut_cell.vcc_pins) {
             // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for
             // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it
             IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin)));
@@ -896,17 +905,37 @@ static void prepare_sites_for_routing(Context *ctx)
 
 #ifdef DEBUG_LUT_MAPPING
             if (ctx->verbose) {
-                log_info("%s must be tied to VCC, tying now\n", ctx->nameOfWire(lut_pin_wire));
+                log_info("%s must be tied to %s, tying now\n", ctx->nameOfWire(lut_pin_wire),
+                         LutCell::nameOfPinConnection(conn).c_str());
             }
 #endif
 
+            IdString tie_net_name;
+            switch (conn) {
+            case LutCell::PinConnection::Vcc:
+                tie_net_name = vcc_net_name;
+                break;
+            case LutCell::PinConnection::Gnd:
+                tie_net_name = gnd_net_name;
+                break;
+            case LutCell::PinConnection::Const:
+                tie_net_name = const_net_name;
+                break;
+            default:
+                // Should never happen
+                NPNR_ASSERT_FALSE(
+                        stringf("Invalid LUT cell pin connection '%s'", LutCell::nameOfPinConnection(conn).c_str())
+                                .c_str());
+                break;
+            }
+
             auto result = cell->ports.emplace(cell_pin, port_info);
             if (result.second) {
                 cell->cell_bel_pins[cell_pin].push_back(bel_pin);
-                ctx->connectPort(vcc_net_name, cell->name, cell_pin);
+                ctx->connectPort(tie_net_name, cell->name, cell_pin);
                 cell->const_ports.emplace(cell_pin);
             } else {
-                NPNR_ASSERT(result.first->second.net == ctx->getNetByAlias(vcc_net_name));
+                NPNR_ASSERT(result.first->second.net == ctx->getNetByAlias(tie_net_name));
                 auto result2 = cell->cell_bel_pins.emplace(cell_pin, std::vector<IdString>({bel_pin}));
                 NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
                 NPNR_ASSERT(result2.first->second.size() == 1);
diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
index d9e17ca94c..8c4672c7ad 100644
--- a/fpga_interchange/luts.cc
+++ b/fpga_interchange/luts.cc
@@ -47,14 +47,6 @@ bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel
             // This address line is 0, so don't translate this bit to the cell
             // address.
             if ((bel_address & (1 << bel_pin_idx)) == 0) {
-                // This pin is unused, so the line will be tied high, this
-                // address is unreachable.
-                //
-                // FIXME: The assumption is that unused pins are tied VCC.
-                // This is not generally true.
-                //
-                // Use Arch::prefered_constant_net_type to determine what
-                // constant net should be used for unused pins.
                 if ((used_pins & (1 << bel_pin_idx)) == 0) {
                     address_reachable = false;
                     break;
@@ -132,6 +124,26 @@ struct LutPin
     bool operator<(const LutPin &other) const { return max_pin < other.max_pin; }
 };
 
+const std::string LutCell::nameOfPinConnection(LutCell::PinConnection conn)
+{
+    switch (conn) {
+    case PinConnection::Unconnected:
+        return std::string("unconnected");
+    case PinConnection::Gnd:
+        return std::string("Gnd");
+    case PinConnection::Vcc:
+        return std::string("Vcc");
+    case PinConnection::Const:
+        return std::string("Const");
+    case PinConnection::Signal:
+        return std::string("Signal");
+    default:
+        // Should never happen
+        NPNR_ASSERT_FALSE("Invalid value of LutCell::PinConnection");
+        return std::string();
+    }
+}
+
 uint32_t LutMapper::check_wires(const Context *ctx) const
 {
     // Unlike the 3 argument version of check_wires, this version needs to
@@ -184,12 +196,7 @@ uint32_t LutMapper::check_wires(const std::vector<std::vector<int32_t>> &bel_to_
         }
     }
 
-    // FIXME: The assumption is that unused pins are tied VCC.
-    // This is not generally true.
-    //
-    // Use Arch::prefered_constant_net_type to determine what
-    // constant net should be used for unused pins.
-    uint32_t vcc_mask = 0;
+    uint32_t pin_mask = 0;
 
     DynamicBitarray<> wire_equation;
     wire_equation.resize(2);
@@ -248,11 +255,11 @@ uint32_t LutMapper::check_wires(const std::vector<std::vector<int32_t>> &bel_to_
 
         bool good_for_wire = valid_pin_for_wire && !invalid_pin_for_wire;
         if (!good_for_wire) {
-            vcc_mask |= (1 << pin_idx);
+            pin_mask |= (1 << pin_idx);
         }
     }
 
-    return vcc_mask;
+    return pin_mask;
 }
 
 bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping,
@@ -381,26 +388,18 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
     }
 
     // Not all LUT inputs are used
-    uint32_t vcc_pins = 0;
+    uint32_t pin_mask = 0;
     if (cells.size() != element.lut_bels.size()) {
-        // Look to see if wires can be run from element inputs to unused
-        // outputs. If not, block the BEL pin by tying to VCC.
-        //
-        // FIXME: The assumption is that unused pins are tied VCC.
-        // This is not generally true.
-        //
-        // Use Arch::prefered_constant_net_type to determine what
-        // constant net should be used for unused pins.
-        vcc_pins = check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, blocked_luts);
+        pin_mask = check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, blocked_luts);
+    }
+
 #if defined(DEBUG_LUT_ROTATION)
-        log_info("vcc_pins = 0x%x", vcc_pins);
-        for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-            CellInfo *cell = cells[cell_idx];
-            log(", %s => %s", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx));
-        }
-        log("\n");
-#endif
+    log_info("Cell bindings:\n");
+    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
+        CellInfo *cell = cells[cell_idx];
+        log_info(" - %s => %s\n", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx));
     }
+#endif
 
     // Fill in the LUT mapping result
 
@@ -422,28 +421,35 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
             cell.belPins[cellPin] = belPin;
         }
 
-        cell.lutCell.vcc_pins.clear();
+        cell.lutCell.pin_connections.clear();
 
         // All LUT inputs used
         if (cells.size() == element.lut_bels.size()) {
             for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) {
                 if ((used_pins & (1 << bel_pin_idx)) == 0) {
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    cell.lutCell.vcc_pins.emplace(lutBel.pins.at(bel_pin_idx));
+                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Vcc);
                 }
             }
         }
         // Only some LUT inputs used
         else {
             for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) {
-                if ((vcc_pins & (1 << bel_pin_idx)) != 0) {
+                if ((pin_mask & (1 << bel_pin_idx)) != 0) {
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
                     auto pin = lutBel.pins.at(bel_pin_idx);
-                    cell.lutCell.vcc_pins.emplace(pin);
+                    cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Vcc);
                 }
             }
         }
 
+#if defined(DEBUG_LUT_ROTATION)
+        log_info("Pin connections for LUT cell %s:\n", cellInfo->name.c_str(ctx));
+        for (const auto &it : cell.lutCell.pin_connections) {
+            log_info(" - %s : %s\n", it.first.c_str(ctx), LutCell::nameOfPinConnection(it.second).c_str());
+        }
+#endif
+
         lut_mapping->cells.push_back(cell);
     }
 
@@ -456,7 +462,7 @@ void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cel
     std::vector<int8_t> pin_map;
     pin_map.resize(lut_bel.pins.size(), -1);
 
-    NPNR_ASSERT(lut_cell.pins.size() < std::numeric_limits<decltype(pin_map)::value_type>::max());
+    NPNR_ASSERT(lut_cell.pins.size() < (size_t)std::numeric_limits<decltype(pin_map)::value_type>::max());
 
     for (size_t cell_pin_idx = 0; cell_pin_idx < lut_cell.pins.size(); ++cell_pin_idx) {
         IdString cell_pin = lut_cell.pins[cell_pin_idx];
diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h
index 8f33507ae7..892f457c19 100644
--- a/fpga_interchange/luts.h
+++ b/fpga_interchange/luts.h
@@ -42,11 +42,22 @@ enum LogicLevel
 
 struct LutCell
 {
+    enum class PinConnection
+    {
+        Unconnected,
+        Gnd,
+        Vcc,
+        Const,
+        Signal
+    };
+
     // LUT cell pins for equation, LSB first.
     std::vector<IdString> pins;
     pool<IdString> lut_pins;
-    pool<IdString> vcc_pins;
+    dict<IdString, PinConnection> pin_connections;
     DynamicBitarray<> equation;
+
+    static const std::string nameOfPinConnection(PinConnection conn);
 };
 
 struct LutBel
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
index f78e8af44f..bb9c9a11cb 100644
--- a/fpga_interchange/site_arch.cc
+++ b/fpga_interchange/site_arch.cc
@@ -133,8 +133,15 @@ SiteArch::SiteArch(const SiteInformation *site_info)
     }
 
     // Create list of out of site sources and sinks.
-
     bool have_vcc_pins = false;
+    bool have_gnd_pins = false;
+
+    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
+    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
+
+    IdString const_net_name(ctx->chip_info->constants->best_constant_net);
+    NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+
     for (CellInfo *cell : site_info->cells_in_site) {
         for (const auto &pin_pair : cell->cell_bel_pins) {
             if (!cell->ports.count(pin_pair.first))
@@ -145,8 +152,18 @@ SiteArch::SiteArch(const SiteInformation *site_info)
             }
         }
 
-        if (!cell->lut_cell.vcc_pins.empty()) {
-            have_vcc_pins = true;
+        for (const auto &conn : cell->lut_cell.pin_connections) {
+            if (conn.second == LutCell::PinConnection::Vcc) {
+                have_vcc_pins = true;
+            } else if (conn.second == LutCell::PinConnection::Gnd) {
+                have_gnd_pins = true;
+            } else if (conn.second == LutCell::PinConnection::Const) {
+                if (const_net_name == vcc_net_name) {
+                    have_vcc_pins = true;
+                } else if (const_net_name == gnd_net_name) {
+                    have_gnd_pins = true;
+                }
+            }
         }
     }
 
@@ -239,10 +256,9 @@ SiteArch::SiteArch(const SiteInformation *site_info)
         }
     }
 
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
     NetInfo *vcc_net = ctx->nets.at(vcc_net_name).get();
-    auto iter = nets.find(vcc_net);
-    if (iter == nets.end() && have_vcc_pins) {
+    auto vcc_iter = nets.find(vcc_net);
+    if (vcc_iter == nets.end() && have_vcc_pins) {
         // VCC net isn't present, add it.
         SiteNetInfo net_info;
         net_info.net = vcc_net;
@@ -250,13 +266,53 @@ SiteArch::SiteArch(const SiteInformation *site_info)
         net_info.driver.net = vcc_net;
         auto result = nets.emplace(vcc_net, net_info);
         NPNR_ASSERT(result.second);
-        iter = result.first;
+        vcc_iter = result.first;
+    }
+
+    NetInfo *gnd_net = ctx->nets.at(gnd_net_name).get();
+    auto gnd_iter = nets.find(gnd_net);
+    if (gnd_iter == nets.end() && have_gnd_pins) {
+        // GND net isn't present, add it.
+        SiteNetInfo net_info;
+        net_info.net = gnd_net;
+        net_info.driver.type = SiteWire::OUT_OF_SITE_SOURCE;
+        net_info.driver.net = gnd_net;
+        auto result = nets.emplace(gnd_net, net_info);
+        NPNR_ASSERT(result.second);
+        gnd_iter = result.first;
     }
 
     for (CellInfo *cell : site_info->cells_in_site) {
-        for (IdString vcc_pin : cell->lut_cell.vcc_pins) {
-            SiteWire wire = getBelPinWire(cell->bel, vcc_pin);
-            iter->second.users.emplace(wire);
+        for (const auto &it : cell->lut_cell.pin_connections) {
+            const auto &pin = it.first;
+            const auto &conn = it.second;
+
+            if (conn == LutCell::PinConnection::Unconnected || conn == LutCell::PinConnection::Signal) {
+                continue;
+            }
+
+            if (conn == LutCell::PinConnection::Vcc) {
+                SiteWire wire = getBelPinWire(cell->bel, pin);
+                vcc_iter->second.users.emplace(wire);
+            } else if (conn == LutCell::PinConnection::Gnd) {
+                SiteWire wire = getBelPinWire(cell->bel, pin);
+                gnd_iter->second.users.emplace(wire);
+            } else if (conn == LutCell::PinConnection::Const) {
+                SiteWire wire = getBelPinWire(cell->bel, pin);
+                if (const_net_name == vcc_net_name) {
+                    vcc_iter->second.users.emplace(wire);
+                }
+                if (const_net_name == gnd_net_name) {
+                    gnd_iter->second.users.emplace(wire);
+                }
+            }
+
+#ifdef DEBUG_LUT_MAPPING
+            if (ctx->verbose) {
+                log_info("Tying %s.%s to %s\n", cell->name.c_str(ctx), pin.c_str(ctx),
+                         LutCell::nameOfPinConnection(conn).c_str());
+            }
+#endif
         }
     }
 
diff --git a/fpga_interchange/site_lut_mapping_cache.cc b/fpga_interchange/site_lut_mapping_cache.cc
index b7a71397c9..82832ed9e8 100644
--- a/fpga_interchange/site_lut_mapping_cache.cc
+++ b/fpga_interchange/site_lut_mapping_cache.cc
@@ -138,8 +138,8 @@ bool SiteLutMappingResult::apply(const SiteInformation &siteInfo)
         }
 
         // LUT data
-        // FIXME: Is there any other info that is being updated than vcc_pins ?
-        cellInfo->lut_cell.vcc_pins = std::move(cell.lutCell.vcc_pins);
+        // FIXME: Is there any other info that is being updated than pin_connections ?
+        cellInfo->lut_cell.pin_connections = std::move(cell.lutCell.pin_connections);
     }
 
     return true;

From 7c7a4f095921f4f6dbec27a73862e5d26ffb230e Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Wed, 11 May 2022 15:50:18 +0200
Subject: [PATCH 142/712] Added tying unused LUT pins to preferred constant
 instead of Vcc

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 fpga_interchange/luts.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
index 8c4672c7ad..03c01803c0 100644
--- a/fpga_interchange/luts.cc
+++ b/fpga_interchange/luts.cc
@@ -428,7 +428,10 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
             for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) {
                 if ((used_pins & (1 << bel_pin_idx)) == 0) {
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Vcc);
+                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Const);
+                }
+                else {
+                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
                 }
             }
         }
@@ -438,7 +441,10 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
                 if ((pin_mask & (1 << bel_pin_idx)) != 0) {
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
                     auto pin = lutBel.pins.at(bel_pin_idx);
-                    cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Vcc);
+                    cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Const);
+                }
+                else {
+                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
                 }
             }
         }

From d75c45c63f444af0349463346101c9d7d7ae6283 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Thu, 12 May 2022 11:55:16 +0200
Subject: [PATCH 143/712] Added fallback to VCC as the preferred constant if
 the architecture does not specify one.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 fpga_interchange/arch.cc      | 13 ++++++++++++-
 fpga_interchange/luts.cc      |  6 ++----
 fpga_interchange/site_arch.cc |  7 ++++++-
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 05b50ae270..6a7c4fe137 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -301,6 +301,12 @@ void Arch::init()
     for (size_t tile_type = 0; tile_type < chip_info->tile_types.size(); ++tile_type) {
         pseudo_pip_data.init_tile_type(getCtx(), tile_type);
     }
+
+    // Warn if there is no preferred constant net defined in the architecture
+    IdString const_net_name(getCtx()->chip_info->constants->best_constant_net);
+    if (const_net_name == IdString()) {
+        log_warning("The architecture does not specify preferred constant net. Using VCC as default.\n");
+    }
 }
 
 // -----------------------------------------------------------------------
@@ -877,7 +883,12 @@ static void prepare_sites_for_routing(Context *ctx)
     IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
 
     IdString const_net_name(ctx->chip_info->constants->best_constant_net);
-    NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+    NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+
+    // FIXME: Use VCC if the architecture does not device the best constant
+    if (const_net_name == IdString()) {
+        const_net_name = vcc_net_name;
+    }
 
     for (BelId bel : ctx->getBels()) {
         CellInfo *cell = ctx->getBoundBelCell(bel);
diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
index 03c01803c0..2a84725316 100644
--- a/fpga_interchange/luts.cc
+++ b/fpga_interchange/luts.cc
@@ -429,8 +429,7 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
                 if ((used_pins & (1 << bel_pin_idx)) == 0) {
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
                     cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Const);
-                }
-                else {
+                } else {
                     cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
                 }
             }
@@ -442,8 +441,7 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
                     NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
                     auto pin = lutBel.pins.at(bel_pin_idx);
                     cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Const);
-                }
-                else {
+                } else {
                     cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
                 }
             }
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
index bb9c9a11cb..d0a5c48c2e 100644
--- a/fpga_interchange/site_arch.cc
+++ b/fpga_interchange/site_arch.cc
@@ -140,7 +140,12 @@ SiteArch::SiteArch(const SiteInformation *site_info)
     IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
 
     IdString const_net_name(ctx->chip_info->constants->best_constant_net);
-    NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+    NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
+
+    // FIXME: Use VCC if the architecture does not device the best constant
+    if (const_net_name == IdString()) {
+        const_net_name = vcc_net_name;
+    }
 
     for (CellInfo *cell : site_info->cells_in_site) {
         for (const auto &pin_pair : cell->cell_bel_pins) {

From ae67c98f111be066ee806598b8b605dede0688d5 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Sat, 21 May 2022 18:26:36 +0100
Subject: [PATCH 144/712] Bump minimum CMake to 3.13

---
 CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3120cf402b..e000144784 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.13)
 project(nextpnr CXX C)
 
 # Allow family.cmake add additional dependencies to gui_${family}.

From 447b5b905cb274f3abbad64812026240d7044c37 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 22 May 2022 13:56:36 +0100
Subject: [PATCH 145/712] Don't assert on mixed domain paths in report

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/report.cc | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index 98ff14fb77..8f583b33e2 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -131,11 +131,6 @@ static Json::array report_detailed_net_timings(const Context *ctx)
 
         Json::array endpointsJson;
         for (const auto &sink_timing : it.second) {
-
-            // FIXME: Is it possible that there are multiple different start
-            // events for a single net? It has a single driver
-            NPNR_ASSERT(sink_timing.clock_pair.start == start);
-
             auto endpointJson = Json::object({{"cell", sink_timing.cell_port.first.c_str(ctx)},
                                               {"port", sink_timing.cell_port.second.c_str(ctx)},
                                               {"event", clock_event_name(ctx, sink_timing.clock_pair.end)},

From 8c4e3e91ccd7fc5c994f05e67a4605290d72079e Mon Sep 17 00:00:00 2001
From: Maciej Dudek <mdudek@antmicro.com>
Date: Fri, 27 May 2022 10:58:24 +0200
Subject: [PATCH 146/712] Change write_dcc to work with tilegroups from
 prjoxide

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
---
 nexus/fasm.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 3ed5785eab..de03fb8226 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -533,11 +533,10 @@ struct NexusFasmWriter
     void write_dcc(const CellInfo *cell)
     {
         BelId bel = cell->bel;
-        push_tile(bel.tile);
-        push_belname(bel);
+        push_bel(bel);
         write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer
         write_cell_muxes(cell);
-        pop(2);
+        pop();
     }
     // Write config for DCS
     void write_dcs(const CellInfo *cell)

From db696af2fe53ab4dc341a09303bb6cd371d76519 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 27 May 2022 22:44:21 +1000
Subject: [PATCH 147/712] gowin: Add support for long wires

Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.

This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.

To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.

* VCC and GND can not use long wires because they are in every cell and
  there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
  long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
  candidates for long wires.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 206 ++++++++++++++++++++++++++++++++++++++++++++-
 gowin/arch.h       |  10 ++-
 gowin/cells.cc     |   3 +
 gowin/constids.inc |  80 ++++++++++++++++++
 gowin/pack.cc      |   8 +-
 5 files changed, 299 insertions(+), 8 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 4fc2cd4321..a991879ebc 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -19,6 +19,7 @@
  */
 
 #include <boost/algorithm/string.hpp>
+#include <cells.h>
 #include <iostream>
 #include <math.h>
 #include <regex>
@@ -175,6 +176,145 @@ DecalXY Arch::getWireDecal(WireId wire) const
     return wires.at(wire).decalxy_active;
 }
 
+bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
+{
+    NPNR_ASSERT(ni != nullptr);
+    if (ni->driver.cell == nullptr) {
+        return false;
+    }
+    if (ni->name == id("$PACKER_VCC_NET") || ni->name == id("$PACKER_GND_NET")) {
+        return false;
+    }
+    // So far only for OBUF
+    switch (ni->driver.cell->type.index) {
+    case ID_ODDR:  /* fall-through*/
+    case ID_ODDRC: /* fall-through*/
+    case ID_IOBUF: /* fall-through*/
+    case ID_TBUF:
+        return false;
+    case ID_OBUF:
+        if (getCtx()->debug) {
+            log_info("Long wire for IO %s\n", nameOf(ni));
+        }
+        ni = ni->driver.cell->ports.at(id_I).net;
+        return allocate_longwire(ni, lw_idx);
+        break;
+    default:
+        break;
+    }
+
+    if (getCtx()->debug) {
+        log_info("Requested index:%d\n", lw_idx);
+    }
+    if (avail_longwires == 0 || (lw_idx != -1 && (avail_longwires & (1 << lw_idx)) == 0)) {
+        return false;
+    }
+    int longwire = lw_idx;
+    if (lw_idx == -1) {
+        for (longwire = 7; longwire >= 0; --longwire) {
+            if (avail_longwires & (1 << longwire)) {
+                break;
+            }
+        }
+    }
+    avail_longwires &= ~(1 << longwire);
+
+    // BUFS cell
+    CellInfo *bufs;
+    char buf[40];
+    snprintf(buf, sizeof(buf), "$PACKER_BUFS%d", longwire);
+    std::unique_ptr<CellInfo> new_cell = create_generic_cell(getCtx(), id_BUFS, buf);
+    bufs = new_cell.get();
+    cells[bufs->name] = std::move(new_cell);
+    if (lw_idx != -1) {
+        bufs->cluster = bufs->name;
+        bufs->constr_z = lw_idx + BelZ::bufs_0_z;
+        bufs->constr_abs_z = true;
+        bufs->constr_children.clear();
+    }
+
+    // old driver -> bufs LW input net
+    snprintf(buf, sizeof(buf), "$PACKER_BUFS_%c", longwire + 'A');
+    auto net = std::make_unique<NetInfo>(id(buf));
+    NetInfo *bufs_net = net.get();
+    nets[net->name] = std::move(net);
+
+    // split the net
+    CellInfo *driver_cell = ni->driver.cell;
+    IdString driver_port = ni->driver.port;
+    driver_cell->disconnectPort(driver_port);
+
+    bufs->connectPort(id_O, ni);
+    bufs->connectPort(id_I, bufs_net);
+    driver_cell->connectPort(driver_port, bufs_net);
+
+    if (getCtx()->debug) {
+        log_info("Long wire %d was allocated\n", longwire);
+    }
+    return true;
+}
+
+void Arch::fix_longwire_bels()
+{
+    // After routing, it is clear which wires and in which bus SS00 and SS40 are used and
+    // in which quadrant they are routed. Here we write it in the attributes.
+    for (auto &cell : cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_BUFS) {
+            continue;
+        }
+        const NetInfo *ni = ci->getPort(id_O);
+        if (ni == nullptr) {
+            continue;
+        }
+        // bus wire is one of the wires
+        // value does not matter, but the L/R parameter itself
+        for (auto &wire : ni->wires) {
+            WireId w = wires[wire.first].type;
+            switch (w.hash()) {
+            case ID_LWSPINETL0:
+            case ID_LWSPINETL1:
+            case ID_LWSPINETL2:
+            case ID_LWSPINETL3:
+            case ID_LWSPINETL4:
+            case ID_LWSPINETL5:
+            case ID_LWSPINETL6:
+            case ID_LWSPINETL7:
+            case ID_LWSPINEBL0:
+            case ID_LWSPINEBL1:
+            case ID_LWSPINEBL2:
+            case ID_LWSPINEBL3:
+            case ID_LWSPINEBL4:
+            case ID_LWSPINEBL5:
+            case ID_LWSPINEBL6:
+            case ID_LWSPINEBL7:
+                ci->setParam(id("L"), Property(w.str(this)));
+                break;
+            case ID_LWSPINETR0:
+            case ID_LWSPINETR1:
+            case ID_LWSPINETR2:
+            case ID_LWSPINETR3:
+            case ID_LWSPINETR4:
+            case ID_LWSPINETR5:
+            case ID_LWSPINETR6:
+            case ID_LWSPINETR7:
+            case ID_LWSPINEBR0:
+            case ID_LWSPINEBR1:
+            case ID_LWSPINEBR2:
+            case ID_LWSPINEBR3:
+            case ID_LWSPINEBR4:
+            case ID_LWSPINEBR5:
+            case ID_LWSPINEBR6:
+            case ID_LWSPINEBR7:
+                ci->setParam(id("R"), Property(w.str(this)));
+                break;
+            default:
+                break;
+            }
+        }
+    }
+}
+
 WireInfo &Arch::wire_info(IdString wire)
 {
     auto w = wires.find(wire);
@@ -628,6 +768,28 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
     case ID_W830:
         len = id_X8;
         break;
+    case ID_LT02:
+    case ID_LT13:
+        glbsrc = id_SPINE_TAP_SCLK_0;
+        break;
+    case ID_LT01:
+    case ID_LT04:
+        glbsrc = id_SPINE_TAP_SCLK_1;
+        break;
+    case ID_LBO0:
+    case ID_LBO1:
+        glbsrc = id_TAP_BRANCH_SCLK;
+        break;
+    case ID_LB01:
+    case ID_LB11:
+    case ID_LB21:
+    case ID_LB31:
+    case ID_LB41:
+    case ID_LB51:
+    case ID_LB61:
+    case ID_LB71:
+        glbsrc = id_BRANCH_SCLK;
+        break;
     case ID_GT00:
     case ID_GT10:
         glbsrc = id_SPINE_TAP_PCLK;
@@ -647,7 +809,9 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
         glbsrc = id_BRANCH_PCLK;
         break;
     default:
-        if (wire.str(this).rfind("SPINE", 0) == 0) {
+        if (wire.str(this).rfind("LWSPINE", 0) == 0) {
+            glbsrc = IdString(ID_CENT_SPINE_SCLK);
+        } else if (wire.str(this).rfind("SPINE", 0) == 0) {
             glbsrc = IdString(ID_CENT_SPINE_PCLK);
         } else if (wire.str(this).rfind("UNK", 0) == 0) {
             glbsrc = IdString(ID_PIO_CENT_PCLK);
@@ -691,7 +855,7 @@ void Arch::read_cst(std::istream &in)
     std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
     std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
     std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
-    std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])[^;]*;");
+    std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*");
     std::smatch match, match_attr, match_pinloc;
     std::string line, pinline;
     enum
@@ -732,15 +896,23 @@ void Arch::read_cst(std::istream &in)
             continue;
         }
         switch (cst_type) {
-        case clock: { // CLOCK name BUFG|S
+        case clock: { // CLOCK name BUFG|S=#
             std::string which_clock = match[2];
+            std::string lw = match[4];
+            int lw_idx = -1;
+            if (lw.length() > 0) {
+                lw_idx = atoi(lw.c_str());
+                log_info("lw_idx:%d\n", lw_idx);
+            }
             if (which_clock.at(0) == 'S') {
                 auto ni = nets.find(net);
                 if (ni == nets.end()) {
                     log_info("Net %s not found\n", net.c_str(this));
                     continue;
                 }
-                log_info("Long wires are not implemented. The %s network will use normal routing.\n", net.c_str(this));
+                if (!allocate_longwire(ni->second.get(), lw_idx)) {
+                    log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(this));
+                }
             } else {
                 log_info("BUFG isn't supported\n");
                 continue;
@@ -1021,6 +1193,31 @@ Arch::Arch(ArchArgs args) : args(args)
             bool dff = true;
             bool oddrc = false;
             switch (static_cast<ConstIds>(bel->type_id)) {
+            case ID_BUFS7:
+                z++; /* fall-through*/
+            case ID_BUFS6:
+                z++; /* fall-through*/
+            case ID_BUFS5:
+                z++; /* fall-through*/
+            case ID_BUFS4:
+                z++; /* fall-through*/
+            case ID_BUFS3:
+                z++; /* fall-through*/
+            case ID_BUFS2:
+                z++; /* fall-through*/
+            case ID_BUFS1:
+                z++; /* fall-through*/
+            case ID_BUFS0:
+                snprintf(buf, 32, "R%dC%d_BUFS%d", row + 1, col + 1, z);
+                belname = id(buf);
+                addBel(belname, id_BUFS, Loc(col, row, BelZ::bufs_0_z + z), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_I)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_I, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_O)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_O, id(buf));
+                break;
             case ID_GSR0:
                 snprintf(buf, 32, "R%dC%d_GSR0", row + 1, col + 1);
                 belname = id(buf);
@@ -1675,6 +1872,7 @@ bool Arch::route()
     }
     getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
+    fix_longwire_bels();
     return result;
 }
 
diff --git a/gowin/arch.h b/gowin/arch.h
index 14181d793b..8bbbd51488 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -459,6 +459,9 @@ struct Arch : BaseArch<ArchRanges>
     void assignArchInfo() override;
     bool cellsCompatible(const CellInfo **cells, int count) const;
     bool haveBelType(int x, int y, IdString bel_type);
+    bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
+    void fix_longwire_bels();
+
     // chip db version
     unsigned int const chipdb_version = 1;
 
@@ -475,6 +478,9 @@ struct Arch : BaseArch<ArchRanges>
     // XXX GW1NR-9 iobuf quirk
     bool gw1n9_quirk = false;
 
+    // 8 Long wires
+    uint8_t avail_longwires = 0xff;
+
     // Permissible combinations of modes in a single slice
     std::map<const IdString, IdString> dff_comp_mode;
 };
@@ -487,7 +493,9 @@ enum
     iologic_0_z = 20, // start Z for the IOLOGIC bels
     vcc_0_z = 277,    // virtual VCC bel Z
     gnd_0_z = 278,    // virtual VSS bel Z
-    osc_z = 280       // Z for the oscillator bels
+    osc_z = 280,      // Z for the oscillator bels
+    bufs_0_z = 281,   // Z for long wire buffer bel
+    free_z = 289      // Must be the last, one can use z starting from this value, adjust accordingly.
 };
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index c3b2178259..6010164a70 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -69,6 +69,9 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_G);
     } else if (type == id_VCC) {
         new_cell->addOutput(id_V);
+    } else if (type == id_BUFS) {
+        new_cell->addInput(id_I);
+        new_cell->addOutput(id_O);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 3691c50606..99c791f890 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -679,6 +679,81 @@ X(IOBHS)
 X(IOBIS)
 X(IOBJS)
 
+// long wires
+X(BUFS)
+X(BUFS0)
+X(BUFS1)
+X(BUFS2)
+X(BUFS3)
+X(BUFS4)
+X(BUFS5)
+X(BUFS6)
+X(BUFS7)
+X(LWT0)
+X(LWB0)
+X(LWT1)
+X(LWB1)
+X(LWT2)
+X(LWB2)
+X(LWT3)
+X(LWB3)
+X(LWT4)
+X(LWB4)
+X(LWT5)
+X(LWB5)
+X(LWT6)
+X(LWB6)
+X(LWT7)
+X(LWB7)
+X(LWSPINETL0)
+X(LWSPINETL1)
+X(LWSPINETL2)
+X(LWSPINETL3)
+X(LWSPINETL4)
+X(LWSPINETL5)
+X(LWSPINETL6)
+X(LWSPINETL7)
+X(LWSPINETR0)
+X(LWSPINETR1)
+X(LWSPINETR2)
+X(LWSPINETR3)
+X(LWSPINETR4)
+X(LWSPINETR5)
+X(LWSPINETR6)
+X(LWSPINETR7)
+X(LWSPINEBL0)
+X(LWSPINEBL1)
+X(LWSPINEBL2)
+X(LWSPINEBL3)
+X(LWSPINEBL4)
+X(LWSPINEBL5)
+X(LWSPINEBL6)
+X(LWSPINEBL7)
+X(LWSPINEBR0)
+X(LWSPINEBR1)
+X(LWSPINEBR2)
+X(LWSPINEBR3)
+X(LWSPINEBR4)
+X(LWSPINEBR5)
+X(LWSPINEBR6)
+X(LWSPINEBR7)
+X(LWI0)
+X(LWI1)
+X(LWI2)
+X(LWI3)
+X(LWI4)
+X(LWI5)
+X(LWI6)
+X(LWI7)
+X(LWO0)
+X(LWO1)
+X(LWO2)
+X(LWO3)
+X(LWO4)
+X(LWO5)
+X(LWO6)
+X(LWO7)
+
 // IOLOGIC
 X(TX)
 X(XXX_VSS)
@@ -812,6 +887,11 @@ X(CENT_SPINE_PCLK)
 X(SPINE_TAP_PCLK)
 X(TAP_BRANCH_PCLK)
 X(BRANCH_PCLK)
+X(CENT_SPINE_SCLK)
+X(SPINE_TAP_SCLK_0)
+X(SPINE_TAP_SCLK_1)
+X(TAP_BRANCH_SCLK)
+X(BRANCH_SCLK)
 X(clksetpos)
 X(clkholdpos)
 X(clk_qpos)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 4adfec1aa2..838201423d 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -947,9 +947,11 @@ static void pack_io(Context *ctx)
             if (constr_bel != ci->attrs.end()) {
                 constr_bel_name = constr_bel->second.as_string();
             }
-            constr_bel = iob->attrs.find(id_BEL);
-            if (constr_bel != iob->attrs.end()) {
-                constr_bel_name = constr_bel->second.as_string();
+            if (iob != nullptr) {
+                constr_bel = iob->attrs.find(id_BEL);
+                if (constr_bel != iob->attrs.end()) {
+                    constr_bel_name = constr_bel->second.as_string();
+                }
             }
             if (!constr_bel_name.empty()) {
                 BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);

From 490dddf636bc50945ee6e6858f7c1942faa3aaf5 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sun, 5 Jun 2022 16:59:06 +0200
Subject: [PATCH 148/712] WIP shadowram

---
 gowin/arch.cc      | 36 ++++++++++++++++++++
 gowin/arch.h       |  2 ++
 gowin/cells.cc     | 33 ++++++++++++++++++
 gowin/cells.h      |  8 +++++
 gowin/constids.inc | 13 ++++++++
 gowin/pack.cc      | 83 ++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 175 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 4fc2cd4321..d554bd6454 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -791,6 +791,39 @@ void Arch::read_cst(std::istream &in)
     settings[id_cst] = 1;
 }
 
+void Arch::addShadowRamBels(const DatabasePOD *db, int row, int col)
+{
+    IdString belname, bel_id;
+    char buf[32];
+    snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
+    belname = id(buf);
+    addBel(belname, id_RAMW, Loc(col, row, BelZ::lutram_0_z), false);
+
+    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 4);
+    addBelInput(belname, id_A4, id(buf));
+    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 4);
+    addBelInput(belname, id_B4, id(buf));
+    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 4);
+    addBelInput(belname, id_C4, id(buf));
+    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 4);
+    addBelInput(belname, id_D4, id(buf));
+
+    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 5);
+    addBelInput(belname, id_A5, id(buf));
+    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 5);
+    addBelInput(belname, id_B5, id(buf));
+    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 5);
+    addBelInput(belname, id_C5, id(buf));
+    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 5);
+    addBelInput(belname, id_D5, id(buf));
+
+    snprintf(buf, 32, "R%dC%d_CLK%d", row + 1, col + 1, 2);
+    addBelInput(belname, id_CLK, id(buf));
+    snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
+    addBelInput(belname, id_LSR, id(buf));
+}
+
+
 // Add all MUXes for the cell
 void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
 {
@@ -1112,6 +1145,9 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (z == 0) {
                     addMuxBels(db, row, col);
                 }
+                if (z == 4) {
+                    addShadowRamBels(db, row, col);
+                }
                 if (z % 2 == 0) {
                     snprintf(buf, 32, "R%dC%d_LUT_GRP%d", row + 1, col + 1, z);
                     grpname = id(buf);
diff --git a/gowin/arch.h b/gowin/arch.h
index 14181d793b..80f887bb36 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -344,6 +344,7 @@ struct Arch : BaseArch<ArchRanges>
     DelayQuad getWireTypeDelay(IdString wire);
     void read_cst(std::istream &in);
     void addMuxBels(const DatabasePOD *db, int row, int col);
+    void addShadowRamBels(const DatabasePOD *db, int row, int col);
 
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
@@ -485,6 +486,7 @@ enum
 {
     mux_0_z = 10,     // start Z for the MUX2LUT5 bels
     iologic_0_z = 20, // start Z for the IOLOGIC bels
+    lutram_0_z = 30, // start Z for the IOLOGIC bels
     vcc_0_z = 277,    // virtual VCC bel Z
     gnd_0_z = 278,    // virtual VSS bel Z
     osc_z = 280       // Z for the oscillator bels
diff --git a/gowin/cells.cc b/gowin/cells.cc
index c3b2178259..8285dc4e36 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -166,4 +166,37 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
     }
 }
 
+void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
+{
+    if (ramw->hierpath == IdString())
+        ramw->hierpath = ramw->hierpath;
+    ram->movePortTo(ctx->id("WAD[0]"), ramw, id_A4);
+    ram->movePortTo(ctx->id("WAD[1]"), ramw, id_B4);
+    ram->movePortTo(ctx->id("WAD[2]"), ramw, id_C4);
+    ram->movePortTo(ctx->id("WAD[3]"), ramw, id_D4);
+
+    ram->movePortTo(ctx->id("DI[0]"), ramw, id_A5);
+    ram->movePortTo(ctx->id("DI[1]"), ramw, id_B5);
+    ram->movePortTo(ctx->id("DI[2]"), ramw, id_C5);
+    ram->movePortTo(ctx->id("DI[3]"), ramw, id_D5);
+    
+    ram->movePortTo(ctx->id("CLK"), ramw, id_CLK);
+    ram->movePortTo(ctx->id("WRE"), ramw, id_LSR);
+}
+
+void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index)
+{
+    char buf1[32];
+    if (slice->hierpath == IdString())
+        slice->hierpath = slice->hierpath;
+
+    snprintf(buf1, 32, "DO[%d]", index);
+    ram->movePortTo(ctx->id(buf1), slice, id_F);
+
+    ram->copyPortTo(ctx->id("RAD[0]"), slice, id_A);
+    ram->copyPortTo(ctx->id("RAD[1]"), slice, id_B);
+    ram->copyPortTo(ctx->id("RAD[2]"), slice, id_C);
+    ram->copyPortTo(ctx->id("RAD[3]"), slice, id_D);
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/gowin/cells.h b/gowin/cells.h
index 8f0636b812..b6d8649733 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -111,6 +111,8 @@ inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
 
 inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SLICE; }
 
+inline bool is_sram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_RAM16SDP4; }
+
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
 // can be reconnected
@@ -125,6 +127,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 // Convert a Gowin IO buffer to a IOB bel
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
 
+// Convert RAM16 to write port
+void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
+
+// Convert RAM16 to slice
+void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index);
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 3691c50606..d9ca1f0c95 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -748,6 +748,19 @@ X(DFFNPE)
 X(DFFNC)
 X(DFFNCE)
 
+// Shadow RAM
+X(RAMW)
+X(RAM16SDP4)
+X(WADA)
+X(WADB)
+X(WADC)
+X(WADD)
+X(DIA)
+X(DIB)
+X(DIC)
+X(DID)
+X(WRE)
+
 // IOB types
 X(IBUF)
 X(OBUF)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 4adfec1aa2..fa88772a92 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -692,6 +692,89 @@ static void pack_gsr(Context *ctx)
     }
 }
 
+// Pack shadow RAM
+void pack_sram(Context *ctx)
+{
+    pool<IdString> packed_cells;
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (is_sram(ctx, ci)) {
+
+            // Create RAMW slice
+            std::unique_ptr<CellInfo> ramw_slice =
+                    create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
+            sram_to_ramw_split(ctx, ci, ramw_slice.get());
+
+            // Create actual RAM slices
+            std::unique_ptr<CellInfo> ram_comb[4];
+            for (int i = 0; i < 4; i++) {
+                ram_comb[i] = create_generic_cell(ctx, id_SLICE,
+                                                ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
+                sram_to_slice(ctx, ci, ram_comb[i].get(), i);
+            }
+            // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
+            std::unique_ptr<CellInfo> ramw_block[2];
+            for (int i = 0; i < 2; i++) {
+                ramw_block[i] = create_generic_cell(ctx, id_SLICE,
+                                                    ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
+                ramw_block[i]->params[id_FF_TYPE] = std::string("RAMW_BLOCK");
+            }
+
+            // Disconnect ports of original cell after packing
+            // ci->disconnectPort(id_WCK);
+            // ci->disconnectPort(id_WRE);
+
+            for (int i = 0; i < 4; i++)
+                ci->disconnectPort(ctx->id(stringf("RAD[%d]", i)));
+
+            // Setup placement constraints
+            // Use the 0th bit as an anchor
+            ram_comb[0]->constr_abs_z = true;
+            ram_comb[0]->constr_z = 0;
+            ram_comb[0]->cluster = ram_comb[0]->name;
+            for (int i = 1; i < 4; i++) {
+                ram_comb[i]->cluster = ram_comb[0]->name;
+                ram_comb[i]->constr_abs_z = true;
+                ram_comb[i]->constr_x = 0;
+                ram_comb[i]->constr_y = 0;
+                ram_comb[i]->constr_z = i;
+                ram_comb[0]->constr_children.push_back(ram_comb[i].get());
+            }
+            for (int i = 0; i < 2; i++) {
+                ramw_block[i]->cluster = ram_comb[0]->name;
+                ramw_block[i]->constr_abs_z = true;
+                ramw_block[i]->constr_x = 0;
+                ramw_block[i]->constr_y = 0;
+                ramw_block[i]->constr_z = i + 4;
+                ram_comb[0]->constr_children.push_back(ramw_block[i].get());
+            }
+
+            ramw_slice->cluster = ram_comb[0]->name;
+            ramw_slice->constr_abs_z = true;
+            ramw_slice->constr_x = 0;
+            ramw_slice->constr_y = 0;
+            ramw_slice->constr_z = 4;
+            ram_comb[0]->constr_children.push_back(ramw_slice.get());
+
+            for (int i = 0; i < 4; i++)
+                new_cells.push_back(std::move(ram_comb[i]));
+            for (int i = 0; i < 2; i++)
+                new_cells.push_back(std::move(ramw_block[i]));
+            new_cells.push_back(std::move(ramw_slice));
+            packed_cells.insert(ci->name);
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
+
 static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
 {
     return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||

From de1bee9352c9f760cb21a35912c48ed2f830c023 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 6 Jun 2022 14:35:33 +0200
Subject: [PATCH 149/712] lutram actually PnRs

---
 gowin/arch.cc      | 64 ++++++++++++++++++++--------------------------
 gowin/arch.h       |  1 -
 gowin/cells.cc     | 10 ++++++++
 gowin/constids.inc |  1 +
 gowin/pack.cc      |  5 +++-
 5 files changed, 43 insertions(+), 38 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index d554bd6454..cba492abe1 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -791,39 +791,6 @@ void Arch::read_cst(std::istream &in)
     settings[id_cst] = 1;
 }
 
-void Arch::addShadowRamBels(const DatabasePOD *db, int row, int col)
-{
-    IdString belname, bel_id;
-    char buf[32];
-    snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
-    belname = id(buf);
-    addBel(belname, id_RAMW, Loc(col, row, BelZ::lutram_0_z), false);
-
-    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_A4, id(buf));
-    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_B4, id(buf));
-    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_C4, id(buf));
-    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_D4, id(buf));
-
-    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_A5, id(buf));
-    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_B5, id(buf));
-    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_C5, id(buf));
-    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_D5, id(buf));
-
-    snprintf(buf, 32, "R%dC%d_CLK%d", row + 1, col + 1, 2);
-    addBelInput(belname, id_CLK, id(buf));
-    snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
-    addBelInput(belname, id_LSR, id(buf));
-}
-
-
 // Add all MUXes for the cell
 void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
 {
@@ -1100,6 +1067,34 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OSCEN, id(buf));
                 break;
+            case ID_RAM16:
+                snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_RAMW, Loc(col, row, BelZ::lutram_0_z), false);
+
+                snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_A4, id(buf));
+                snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_B4, id(buf));
+                snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_C4, id(buf));
+                snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_D4, id(buf));
+
+                snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_A5, id(buf));
+                snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_B5, id(buf));
+                snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_C5, id(buf));
+                snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_D5, id(buf));
+
+                snprintf(buf, 32, "R%dC%d_CLK%d", row + 1, col + 1, 2);
+                addBelInput(belname, id_CLK, id(buf));
+                snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
+                addBelInput(belname, id_LSR, id(buf));
+                break;
             // fall through the ++
             case ID_LUT7:
                 z++;
@@ -1145,9 +1140,6 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (z == 0) {
                     addMuxBels(db, row, col);
                 }
-                if (z == 4) {
-                    addShadowRamBels(db, row, col);
-                }
                 if (z % 2 == 0) {
                     snprintf(buf, 32, "R%dC%d_LUT_GRP%d", row + 1, col + 1, z);
                     grpname = id(buf);
diff --git a/gowin/arch.h b/gowin/arch.h
index 80f887bb36..c13cdf093f 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -344,7 +344,6 @@ struct Arch : BaseArch<ArchRanges>
     DelayQuad getWireTypeDelay(IdString wire);
     void read_cst(std::istream &in);
     void addMuxBels(const DatabasePOD *db, int row, int col);
-    void addShadowRamBels(const DatabasePOD *db, int row, int col);
 
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 8285dc4e36..63ee71ed9a 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -48,6 +48,13 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_Q);
         new_cell->addInput(id_CE);
         new_cell->addInput(id_LSR);
+    } else if (type == id_RAMW) {
+        IdString names[8] = {id_A4, id_B4, id_C4, id_D4, id_A5, id_B5, id_C5, id_D5};
+        for (int i = 0; i < 8; i++) {
+            new_cell->addInput(names[i]);
+        }
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_LSR);
     } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
                type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
         new_cell->addInput(id_I0);
@@ -190,6 +197,9 @@ void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index)
     if (slice->hierpath == IdString())
         slice->hierpath = slice->hierpath;
 
+    snprintf(buf1, 32, "INIT_%d", index);
+    slice->params[id_INIT] = ram->params[ctx->id(buf1)];
+
     snprintf(buf1, 32, "DO[%d]", index);
     ram->movePortTo(ctx->id(buf1), slice, id_F);
 
diff --git a/gowin/constids.inc b/gowin/constids.inc
index d9ca1f0c95..0c788ecd83 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -749,6 +749,7 @@ X(DFFNC)
 X(DFFNCE)
 
 // Shadow RAM
+X(RAM16)
 X(RAMW)
 X(RAM16SDP4)
 X(WADA)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index fa88772a92..7d3a8e98ed 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -695,6 +695,8 @@ static void pack_gsr(Context *ctx)
 // Pack shadow RAM
 void pack_sram(Context *ctx)
 {
+    log_info("Packing Shadow RAM..\n");
+
     pool<IdString> packed_cells;
     std::vector<std::unique_ptr<CellInfo>> new_cells;
 
@@ -755,7 +757,7 @@ void pack_sram(Context *ctx)
             ramw_slice->constr_abs_z = true;
             ramw_slice->constr_x = 0;
             ramw_slice->constr_y = 0;
-            ramw_slice->constr_z = 4;
+            ramw_slice->constr_z = BelZ::lutram_0_z;
             ram_comb[0]->constr_children.push_back(ramw_slice.get());
 
             for (int i = 0; i < 4; i++)
@@ -1091,6 +1093,7 @@ bool Arch::pack()
     try {
         log_break();
         pack_constants(ctx);
+        pack_sram(ctx);
         pack_gsr(ctx);
         pack_io(ctx);
         pack_diff_io(ctx);

From bd0af4052c434b1cf3ed8522360b5acc78bd17a2 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 9 Jun 2022 08:20:29 +1000
Subject: [PATCH 150/712] gowin: Use local aliases

In the Gowin chips, the tiles are connected to each other by a one-hop
wire, among others. There are 4 one-hop wires, of which 2 are shared
between north/south and east/west, have three names: e.g. SN10 and N110
and S110.

But only one of them, the first, occurs as a sink for PIP, that is, you
can not get a route that would pass through the S110 for example.

This commit corrects the names to SN?0 and EW?0 at the wire creation
stage to avoid dead wires.

In addition, the SN?0 and EW?0 are among the few sinks for global clock
wires and now there is the possibility of a more optimal clock routing.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index a991879ebc..82f5018b32 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -34,6 +34,8 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+const PairPOD *pairLookup(const PairPOD *list, const size_t len, const int dest);
+
 // GUI
 void Arch::fixClockSpineDecals(void)
 {
@@ -627,7 +629,15 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
     }
     snprintf(buf, 32, "%c%d0", direction, num);
     wire = id(buf);
-    snprintf(buf, 32, "R%dC%d_%c%d", row + 1, col + 1, direction, num);
+    // local aliases
+    const TilePOD *tile = db->grid[row * db->cols + col].get();
+    auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, wire.index);
+    if (local_alias != nullptr) {
+        wire = IdString(local_alias->src_id);
+        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, wire.c_str(this));
+    } else {
+        snprintf(buf, 32, "R%dC%d_%c%d", row + 1, col + 1, direction, num);
+    }
     return id(buf);
 }
 
@@ -1491,12 +1501,6 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s_%s", row + 1, col + 1, srcid.c_str(this), destid.c_str(this));
                 IdString pipname = id(buf);
                 DelayQuad delay = getWireTypeDelay(destid);
-                // local alias
-                auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, srcid.index);
-                if (local_alias != nullptr) {
-                    srcid = IdString(local_alias->src_id);
-                    gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
-                }
                 // global alias
                 srcid = IdString(pip.src_id);
                 GlobalAliasPOD alias;

From eac864ebdcdf7cf366e0dcbd5497e3c5cce3c479 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 9 Jun 2022 20:05:20 +0100
Subject: [PATCH 151/712] ecp5: Bind write_bitstream to Python

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch_pybindings.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc
index 593feb335f..693d3199ec 100644
--- a/ecp5/arch_pybindings.cc
+++ b/ecp5/arch_pybindings.cc
@@ -23,6 +23,7 @@
 #include "arch_pybindings.h"
 #include "nextpnr.h"
 #include "pybindings.h"
+#include "bitstream.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -69,6 +70,8 @@ void arch_wrap_python(py::module &m)
     WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
     WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
     WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
+
+    m.def("write_bitstream", &write_bitstream);
 }
 
 NEXTPNR_NAMESPACE_END

From 8d063d38b148b1e7095a032ffc9cf957c2407f32 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 12 Jun 2022 07:59:36 +0100
Subject: [PATCH 152/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch_pybindings.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc
index 693d3199ec..1621eda55a 100644
--- a/ecp5/arch_pybindings.cc
+++ b/ecp5/arch_pybindings.cc
@@ -21,9 +21,9 @@
 #ifndef NO_PYTHON
 
 #include "arch_pybindings.h"
+#include "bitstream.h"
 #include "nextpnr.h"
 #include "pybindings.h"
-#include "bitstream.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 

From b7992ec7724000f813ab053ac6042326f3795471 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 16 Jun 2022 11:38:23 +0200
Subject: [PATCH 153/712] hook up CE maybe

---
 gowin/arch.cc  | 2 ++
 gowin/cells.cc | 1 +
 gowin/pack.cc  | 1 +
 3 files changed, 4 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index cba492abe1..65f1520477 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1094,6 +1094,8 @@ Arch::Arch(ArchArgs args) : args(args)
                 addBelInput(belname, id_CLK, id(buf));
                 snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
                 addBelInput(belname, id_LSR, id(buf));
+                snprintf(buf, 32, "R%dC%d_CE%d", row + 1, col + 1, 2);
+                addBelInput(belname, id_CE, id(buf));
                 break;
             // fall through the ++
             case ID_LUT7:
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 63ee71ed9a..0dc0ce06fa 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -54,6 +54,7 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
             new_cell->addInput(names[i]);
         }
         new_cell->addInput(id_CLK);
+        new_cell->addInput(id_CE);
         new_cell->addInput(id_LSR);
     } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
                type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 7d3a8e98ed..0ba71705b7 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -708,6 +708,7 @@ void pack_sram(Context *ctx)
             std::unique_ptr<CellInfo> ramw_slice =
                     create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
             sram_to_ramw_split(ctx, ci, ramw_slice.get());
+            ramw_slice->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
 
             // Create actual RAM slices
             std::unique_ptr<CellInfo> ram_comb[4];

From b950f5cb6de869658564855eb64c46c50c4bc249 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 21 Jun 2022 12:35:13 +0100
Subject: [PATCH 154/712] Disable broken and failing interchange CI

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .../workflows/{interchange_ci.yml => interchange_ci.yml.disable}  | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename .github/workflows/{interchange_ci.yml => interchange_ci.yml.disable} (100%)

diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml.disable
similarity index 100%
rename from .github/workflows/interchange_ci.yml
rename to .github/workflows/interchange_ci.yml.disable

From b502499a1e7cfc97bf8a69ffa0365c040dadf2fd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Chandler=20Kl=C3=BCser?= <chandler.kluser@gmail.com>
Date: Wed, 22 Jun 2022 21:03:04 -0300
Subject: [PATCH 155/712] Update README.md

---
 README.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 14128b87ec..36ff9a8b6b 100644
--- a/README.md
+++ b/README.md
@@ -145,7 +145,8 @@ An example of how to use the generic flow is in [generic/examples](generic/examp
 
 The nextpnr GUI is not built by default, to reduce the number of dependencies for a standard headless build. To enable it, add `-DBUILD_GUI=ON` to the CMake command line and ensure that Qt5 and OpenGL are available:
 
- - On Ubuntu, install `qt5-default`
+ - On Ubuntu 22.04 LTS, install `qtcreator qtbase5-dev qt5-qmake` 
+ - On other Ubuntu versions, install `qt5-default`
  - For MSVC vcpkg, install `qt5-base` (32-bit) or `qt5-base:x64-windows` (64-bit)
  - For Homebrew, install `qt5` and add qt5 in path: `echo 'export PATH="/usr/local/opt/qt/bin:$PATH"' >> ~/.bash_profile`
 ` - this change is effective in next terminal session, so please re-open terminal window before building

From 590b9050ff5cc618b4df50e0877b4bf6d9e7949d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 23 Jun 2022 11:42:58 +1000
Subject: [PATCH 156/712] gowin: add a separate router for the clocks

A simple router that takes advantage of the fact that in each cell with
DFFs their CLK inputs can directly connect to the global clock network.

Networks with a large number of such sinks are sought and then each
network is assigned to the available independent global clock networks.

There are limited possibilities for routing mixed networks, that is,
when the sinks are not only CLKs: in this case an attempt is made to use
wires such as SN10/20 and EW10/20, that is, one short transition can be
added between the global clock network and the sink.

* At this time, networks with a source other than the I/O pin are not
  supported. This is typical for Tangnano4k and runber boards.

* Router is disabled by default, you need to specify option
  --enable-globals to activate

* No new chip bases are required. This may change in the distant future.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc    |  15 +++
 gowin/arch.h     |   1 +
 gowin/globals.cc | 335 +++++++++++++++++++++++++++++++++++++++++++++++
 gowin/globals.h  |  26 ++++
 gowin/main.cc    |  16 ++-
 5 files changed, 392 insertions(+), 1 deletion(-)
 create mode 100644 gowin/globals.cc
 create mode 100644 gowin/globals.h

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 82f5018b32..7b9097c93d 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -25,6 +25,7 @@
 #include <regex>
 #include "embed.h"
 #include "gfx.h"
+#include "globals.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
@@ -341,6 +342,14 @@ BelInfo &Arch::bel_info(IdString bel)
     return b->second;
 }
 
+NetInfo &Arch::net_info(IdString net)
+{
+    auto b = nets.find(net);
+    if (b == nets.end())
+        NPNR_ASSERT_FALSE_STR("no net named " + net.str(this));
+    return *b->second;
+}
+
 void Arch::addWire(IdString name, IdString type, int x, int y)
 {
     NPNR_ASSERT(wires.count(name) == 0);
@@ -657,6 +666,7 @@ bool aliasCompare(GlobalAliasPOD i, GlobalAliasPOD j)
     return (i.dest_row < j.dest_row) || (i.dest_row == j.dest_row && i.dest_col < j.dest_col) ||
            (i.dest_row == j.dest_row && i.dest_col == j.dest_col && i.dest_id < j.dest_id);
 }
+
 bool timingCompare(TimingPOD i, TimingPOD j) { return i.name_id < j.name_id; }
 
 template <class T, class C> const T *genericLookup(const T *first, int len, const T val, C compare)
@@ -1865,6 +1875,11 @@ bool Arch::place()
 bool Arch::route()
 {
     std::string router = str_or_default(settings, id_router, defaultRouter);
+
+    if (bool_or_default(settings, id("arch.enable-globals"))) {
+        route_gowin_globals(getCtx());
+    }
+
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
diff --git a/gowin/arch.h b/gowin/arch.h
index 8bbbd51488..c59f8eb353 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -289,6 +289,7 @@ struct Arch : BaseArch<ArchRanges>
     WireInfo &wire_info(IdString wire);
     PipInfo &pip_info(IdString pip);
     BelInfo &bel_info(IdString bel);
+    NetInfo &net_info(IdString net);
 
     std::vector<IdString> bel_ids, wire_ids, pip_ids;
 
diff --git a/gowin/globals.cc b/gowin/globals.cc
new file mode 100644
index 0000000000..5010cf79e7
--- /dev/null
+++ b/gowin/globals.cc
@@ -0,0 +1,335 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "globals.h"
+#include <algorithm>
+#include <iomanip>
+#include <iostream>
+#include <queue>
+#include "cells.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "place_common.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class GowinGlobalRouter
+{
+  public:
+    GowinGlobalRouter(Context *ctx) : ctx(ctx){};
+
+  private:
+    // wire -> clock#
+    dict<WireId, int> used_wires;
+
+    // ordered nets
+    struct onet_t
+    {
+        IdString name;
+        int clock_ports;
+        WireId clock_io_wire; // IO wire if there is one
+
+        onet_t() : name(IdString()), clock_ports(0), clock_io_wire(WireId()) {}
+        onet_t(IdString _name) : name(_name), clock_ports(0), clock_io_wire(WireId()) {}
+
+        // sort
+        bool operator<(const onet_t &other) const
+        {
+            if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
+                return !(clock_io_wire != WireId());
+            }
+            return clock_ports < other.clock_ports;
+        }
+        // search
+        bool operator==(const onet_t &other) const { return name == other.name; }
+    };
+
+    bool is_clock_port(PortRef const &user)
+    {
+        if (user.cell->type == id_SLICE && user.port == id_CLK) {
+            return true;
+        }
+        return false;
+    }
+
+    WireId clock_io(PortRef const &driver)
+    {
+        // XXX normally all alternative functions of the pins should be passed
+        // in the chip database, but at the moment we find them from aliases/pips
+        // XXX check diff inputs too
+        if (driver.cell == nullptr || driver.cell->bel == BelId()) {
+            return WireId();
+        }
+        // clock IOs have pips output->SPINExx
+        BelInfo &bel = ctx->bels.at(driver.cell->bel);
+        if (bel.type != id_IOB) {
+            return WireId();
+        }
+        WireId wire = bel.pins[id_O].wire;
+        for (auto const &pip : ctx->getPipsDownhill(wire)) {
+            if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
+                return wire;
+            }
+        }
+        return WireId();
+    }
+
+    // gather the clock nets
+    void gather_clock_nets(std::vector<onet_t> &clock_nets)
+    {
+        for (auto const &net : ctx->nets) {
+            NetInfo const *ni = net.second.get();
+            auto new_clock = clock_nets.end();
+            WireId clock_wire = clock_io(ni->driver);
+            if (clock_wire != WireId()) {
+                clock_nets.emplace_back(net.first);
+                new_clock = --clock_nets.end();
+                new_clock->clock_io_wire = clock_wire;
+            }
+            for (auto const &user : ni->users) {
+                if (is_clock_port(user)) {
+                    if (new_clock == clock_nets.end()) {
+                        clock_nets.emplace_back(net.first);
+                        new_clock = --clock_nets.end();
+                    }
+                    ++(new_clock->clock_ports);
+                }
+            }
+        }
+        // need to prioritize the nets
+        std::sort(clock_nets.begin(), clock_nets.end());
+
+        if (ctx->verbose) {
+            for (auto const &net : clock_nets) {
+                log_info("  Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
+                         net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
+            }
+        }
+    }
+
+    // non clock port
+    // returns GB pip
+    IdString route_to_non_clock_port(WireId const dstWire, int clock, pool<IdString> &used_pips,
+                                     pool<IdString> &undo_wires)
+    {
+        static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
+        char buf[40];
+        // uphill pips
+        for (auto const &uphill : ctx->getPipsUphill(dstWire)) {
+            WireId srcWire = ctx->getPipSrcWire(uphill);
+            if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
+                one_hop.end()) {
+                // found one hop pip
+                if (used_wires.count(srcWire)) {
+                    if (used_wires[srcWire] != clock) {
+                        continue;
+                    }
+                }
+                WireInfo wi = ctx->wire_info(srcWire);
+                std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
+                snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
+                IdString gb = ctx->id(buf);
+                auto up_pips = ctx->getPipsUphill(srcWire);
+                if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
+                    if (!used_wires.count(srcWire)) {
+                        used_wires.insert(std::make_pair(srcWire, clock));
+                        undo_wires.insert(srcWire);
+                    }
+                    used_pips.insert(uphill);
+                    if (ctx->verbose) {
+                        log_info("    1-hop Pip:%s\n", uphill.c_str(ctx));
+                    }
+                    return gb;
+                }
+            }
+        }
+        return IdString();
+    }
+
+    // route one net
+    void route_net(onet_t const &net, int clock)
+    {
+        // For failed routing undo
+        pool<IdString> used_pips;
+        pool<IdString> undo_wires;
+
+        log_info("  Route net %s, use clock #%d.\n", net.name.c_str(ctx), clock);
+        for (auto const &user : ctx->net_info(net.name).users) {
+            // >>> port <- GB<clock>0
+            WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
+            if (ctx->verbose) {
+                log_info("   Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
+                         dstWire.c_str(ctx));
+            }
+
+            char buf[30];
+            PipId gb_pip_id;
+            if (user.port == id_CLK) {
+                WireInfo const wi = ctx->wire_info(dstWire);
+                snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock,
+                         ctx->wire_info(dstWire).type.c_str(ctx));
+                gb_pip_id = ctx->id(buf);
+                // sanity
+                NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
+                            ctx->getPipsUphill(dstWire).end());
+            } else {
+                // Non clock port
+                gb_pip_id = route_to_non_clock_port(dstWire, clock, used_pips, undo_wires);
+                if (gb_pip_id == IdString()) {
+                    if (ctx->verbose) {
+                        log_info("  Can't find route to %s, net %s will be routed in a standard way.\n",
+                                 dstWire.c_str(ctx), net.name.c_str(ctx));
+                    }
+                    for (IdString const &undo : undo_wires) {
+                        used_wires.erase(undo);
+                    }
+                    return;
+                }
+            }
+            if (ctx->verbose) {
+                log_info("    GB Pip:%s\n", gb_pip_id.c_str(ctx));
+            }
+
+            if (used_pips.count(gb_pip_id)) {
+                if (ctx->verbose) {
+                    log_info("    ^routed already^\n");
+                }
+                continue;
+            }
+            used_pips.insert(gb_pip_id);
+
+            // >>> GBOx <- GTx0
+            dstWire = ctx->getPipSrcWire(gb_pip_id);
+            WireInfo dstWireInfo = ctx->wire_info(dstWire);
+            int branch_tap_idx = clock > 3 ? 1 : 0;
+            snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
+                     branch_tap_idx);
+            PipId gt_pip_id = ctx->id(buf);
+            if (ctx->verbose) {
+                log_info("     GT Pip:%s\n", buf);
+            }
+            // sanity
+            NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
+                        ctx->getPipsUphill(dstWire).end());
+            // if already routed
+            if (used_pips.count(gt_pip_id)) {
+                if (ctx->verbose) {
+                    log_info("     ^routed already^\n");
+                }
+                continue;
+            }
+            used_pips.insert(gt_pip_id);
+
+            // >>> GTx0 <- SPINExx
+            // XXX no optimization here, we need to store
+            // the SPINE <-> clock# correspondence in the database. In the
+            // meantime, we define in run-time in a completely suboptimal way.
+            std::vector<std::string> clock_spine;
+            dstWire = ctx->getPipSrcWire(gt_pip_id);
+            for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
+                std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
+                if (name.rfind("SPINE", 0) == 0) {
+                    clock_spine.push_back(name);
+                }
+            }
+            sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
+                return (a.size() < b.size()) || (a.size() == b.size() && a < b);
+            });
+            dstWireInfo = ctx->wire_info(dstWire);
+            snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
+                     clock_spine[clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
+            PipId spine_pip_id = ctx->id(buf);
+            if (ctx->verbose) {
+                log_info("      Spine Pip:%s\n", buf);
+            }
+            // sanity
+            NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
+                        ctx->getPipsUphill(dstWire).end());
+            // if already routed
+            if (used_pips.count(spine_pip_id)) {
+                if (ctx->verbose) {
+                    log_info("      ^routed already^\n");
+                }
+                continue;
+            }
+            used_pips.insert(spine_pip_id);
+
+            // >>> SPINExx <- IO
+            dstWire = ctx->getPipSrcWire(spine_pip_id);
+            dstWireInfo = ctx->wire_info(dstWire);
+            PipId io_pip_id = PipId();
+            for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
+                if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
+                    io_pip_id = uphill_pip;
+                }
+            }
+            NPNR_ASSERT(io_pip_id != PipId());
+            if (ctx->verbose) {
+                log_info("       IO Pip:%s\n", io_pip_id.c_str(ctx));
+            }
+            // if already routed
+            if (used_pips.count(io_pip_id)) {
+                if (ctx->verbose) {
+                    log_info("      ^routed already^\n");
+                }
+                continue;
+            }
+            used_pips.insert(io_pip_id);
+        }
+        log_info("  Net %s is routed.\n", net.name.c_str(ctx));
+        for (auto const pip : used_pips) {
+            ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
+        }
+        ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
+    }
+
+  public:
+    Context *ctx;
+    void route_globals()
+    {
+        log_info("Routing globals...\n");
+
+        std::vector<onet_t> clock_nets;
+        gather_clock_nets(clock_nets);
+        // XXX we need to use the list of indexes of clocks from the database
+        // use 6 clocks (XXX 3 for GW1NZ-1)
+        int max_clock = 3, cur_clock = -1;
+        for (auto const &net : clock_nets) {
+            // XXX only IO clock for now
+            if (net.clock_io_wire == WireId()) {
+                log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
+                continue;
+            }
+            if (++cur_clock >= max_clock) {
+                log_info(" No more clock wires left, skip the remaining nets.\n");
+                break;
+            }
+            route_net(net, cur_clock);
+        }
+    }
+};
+
+void route_gowin_globals(Context *ctx)
+{
+    GowinGlobalRouter router(ctx);
+    router.route_globals();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gowin/globals.h b/gowin/globals.h
new file mode 100644
index 0000000000..4731447cab
--- /dev/null
+++ b/gowin/globals.h
@@ -0,0 +1,26 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void route_gowin_globals(Context *ctx);
+
+NEXTPNR_NAMESPACE_END
diff --git a/gowin/main.cc b/gowin/main.cc
index a45a49d40e..36bd865669 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -51,6 +51,8 @@ po::options_description GowinCommandHandler::getArchOptions()
     specific.add_options()("device", po::value<std::string>(), "device name");
     specific.add_options()("family", po::value<std::string>(), "family name");
     specific.add_options()("cst", po::value<std::string>(), "physical constraints file");
+    specific.add_options()("enable-globals", "separate routing of the clocks");
+    specific.add_options()("enable-auto-longwires", "automatic detection and routing of long wires");
     return specific;
 }
 
@@ -79,7 +81,19 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
         chipArgs.family = buf;
     }
     chipArgs.partnumber = match[0];
-    return std::unique_ptr<Context>(new Context(chipArgs));
+
+    auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
+    // routing options
+    // the default values will change in the future
+    ctx->settings[ctx->id("arch.enable-globals")] = 0;
+    ctx->settings[ctx->id("arch.enable-auto-longwires")] = 0;
+    if (vm.count("enable-globals")) {
+        ctx->settings[ctx->id("arch.enable-globals")] = 1;
+    }
+    if (vm.count("enable-auto-longwires")) {
+        ctx->settings[ctx->id("arch.enable-auto-longwires")] = 1;
+    }
+    return ctx;
 }
 
 void GowinCommandHandler::customAfterLoad(Context *ctx)

From 63f2acd42adf3884d153381696cf7845c6d74162 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 24 Jun 2022 08:20:06 +1000
Subject: [PATCH 157/712] gowin: process the CLK ports of the ODDR[C]
 primitives

Also removed the useless references.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/globals.cc | 15 ++++++++-------
 gowin/globals.h  |  1 +
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/gowin/globals.cc b/gowin/globals.cc
index 5010cf79e7..ed75a93888 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2022  YRabbit <rabbit@yrabbit.cyou>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -63,7 +64,7 @@ class GowinGlobalRouter
 
     bool is_clock_port(PortRef const &user)
     {
-        if (user.cell->type == id_SLICE && user.port == id_CLK) {
+        if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) && user.port == id_CLK) {
             return true;
         }
         return false;
@@ -78,12 +79,12 @@ class GowinGlobalRouter
             return WireId();
         }
         // clock IOs have pips output->SPINExx
-        BelInfo &bel = ctx->bels.at(driver.cell->bel);
+        BelInfo &bel = ctx->bel_info(driver.cell->bel);
         if (bel.type != id_IOB) {
             return WireId();
         }
         WireId wire = bel.pins[id_O].wire;
-        for (auto const &pip : ctx->getPipsDownhill(wire)) {
+        for (auto const pip : ctx->getPipsDownhill(wire)) {
             if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
                 return wire;
             }
@@ -132,7 +133,7 @@ class GowinGlobalRouter
         static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
         char buf[40];
         // uphill pips
-        for (auto const &uphill : ctx->getPipsUphill(dstWire)) {
+        for (auto const uphill : ctx->getPipsUphill(dstWire)) {
             WireId srcWire = ctx->getPipSrcWire(uphill);
             if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
                 one_hop.end()) {
@@ -197,7 +198,7 @@ class GowinGlobalRouter
                         log_info("  Can't find route to %s, net %s will be routed in a standard way.\n",
                                  dstWire.c_str(ctx), net.name.c_str(ctx));
                     }
-                    for (IdString const &undo : undo_wires) {
+                    for (IdString const undo : undo_wires) {
                         used_wires.erase(undo);
                     }
                     return;
@@ -243,7 +244,7 @@ class GowinGlobalRouter
             // meantime, we define in run-time in a completely suboptimal way.
             std::vector<std::string> clock_spine;
             dstWire = ctx->getPipSrcWire(gt_pip_id);
-            for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
+            for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
                 std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
                 if (name.rfind("SPINE", 0) == 0) {
                     clock_spine.push_back(name);
@@ -275,7 +276,7 @@ class GowinGlobalRouter
             dstWire = ctx->getPipSrcWire(spine_pip_id);
             dstWireInfo = ctx->wire_info(dstWire);
             PipId io_pip_id = PipId();
-            for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
+            for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
                 if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
                     io_pip_id = uphill_pip;
                 }
diff --git a/gowin/globals.h b/gowin/globals.h
index 4731447cab..41a8727abe 100644
--- a/gowin/globals.h
+++ b/gowin/globals.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2022  YRabbit <rabbit@yrabbit.cyou>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

From 6122f172e3f15115cfb755ed702cc0438c341269 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 25 Jun 2022 15:56:16 +0100
Subject: [PATCH 158/712] ice40: Fix accidental creation of empty ports

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/arch_place.cc | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 3b024d8175..67ddf77763 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -95,7 +95,7 @@ bool Arch::isBelLocationValid(BelId bel) const
         }
         return logic_cells_compatible(bel_cells.data(), num_cells);
     } else {
-        CellInfo *cell = getBoundBelCell(bel);
+        const CellInfo *cell = getBoundBelCell(bel);
         if (cell == nullptr)
             return true;
         else if (cell->type == id_SB_IO) {
@@ -107,7 +107,7 @@ bool Arch::isBelLocationValid(BelId bel) const
             for (auto pin : getWireBelPins(wire)) {
                 if (pin.pin == id_PLLOUT_A || pin.pin == id_PLLOUT_B) {
                     // Is there a PLL there ?
-                    auto pll_cell = getBoundBelCell(pin.bel);
+                    const CellInfo *pll_cell = getBoundBelCell(pin.bel);
                     if (pll_cell == nullptr)
                         break;
 
@@ -116,11 +116,11 @@ bool Arch::isBelLocationValid(BelId bel) const
                         break;
 
                     // Is that SB_IO used at an input ?
-                    if ((cell->ports[id_D_IN_0].net == nullptr) && (cell->ports[id_D_IN_1].net == nullptr))
+                    if ((cell->getPort(id_D_IN_0) == nullptr) && (cell->getPort(id_D_IN_1) == nullptr))
                         break;
 
                     // Are we perhaps a PAD INPUT Bel that can be placed here?
-                    if (pll_cell->attrs[id_BEL_PAD_INPUT] == getBelName(bel).str(getCtx()))
+                    if (str_or_default(pll_cell->attrs, id_BEL_PAD_INPUT, "") == getBelName(bel).str(getCtx()))
                         return true;
 
                     // Conflict
@@ -144,7 +144,7 @@ bool Arch::isBelLocationValid(BelId bel) const
             } else {
                 // Check LVDS IO is not placed at complement location
                 BelId compBel = getBelByLocation(compLoc);
-                CellInfo *compCell = getBoundBelCell(compBel);
+                const CellInfo *compCell = getBoundBelCell(compBel);
                 if (compCell && compCell->ioInfo.lvds)
                     return false;
 
@@ -161,10 +161,10 @@ bool Arch::isBelLocationValid(BelId bel) const
                             _io_pintype_need_clk_en(cell->ioInfo.pintype),
                             _io_pintype_need_clk_en(compCell->ioInfo.pintype),
                     };
-                    NetInfo *nets[] = {
-                            cell->ports[id_INPUT_CLK].net,    compCell->ports[id_INPUT_CLK].net,
-                            cell->ports[id_OUTPUT_CLK].net,   compCell->ports[id_OUTPUT_CLK].net,
-                            cell->ports[id_CLOCK_ENABLE].net, compCell->ports[id_CLOCK_ENABLE].net,
+                    const NetInfo *nets[] = {
+                            cell->getPort(id_INPUT_CLK),    compCell->getPort(id_INPUT_CLK),
+                            cell->getPort(id_OUTPUT_CLK),   compCell->getPort(id_OUTPUT_CLK),
+                            cell->getPort(id_CLOCK_ENABLE), compCell->getPort(id_CLOCK_ENABLE),
                     };
 
                     for (int i = 0; i < 6; i++)

From 6f56ad298c1a94259698cbd487f03efbd68f0342 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sat, 2 Jul 2022 20:44:59 +0200
Subject: [PATCH 159/712] use DFF RAM mode

---
 gowin/pack.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index fbd2092f1c..9f4b54e2a7 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -715,6 +715,8 @@ void pack_sram(Context *ctx)
             for (int i = 0; i < 4; i++) {
                 ram_comb[i] = create_generic_cell(ctx, id_SLICE,
                                                 ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
+                ram_comb[i]->params[id_FF_USED] = 1;
+                ram_comb[i]->params[id_FF_TYPE] = std::string("RAM");
                 sram_to_slice(ctx, ci, ram_comb[i].get(), i);
             }
             // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
@@ -722,7 +724,8 @@ void pack_sram(Context *ctx)
             for (int i = 0; i < 2; i++) {
                 ramw_block[i] = create_generic_cell(ctx, id_SLICE,
                                                     ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
-                ramw_block[i]->params[id_FF_TYPE] = std::string("RAMW_BLOCK");
+                ram_comb[i]->params[id_FF_USED] = 1;
+                ramw_block[i]->params[id_FF_TYPE] = std::string("RAM");
             }
 
             // Disconnect ports of original cell after packing

From 3172a38daeb4588d3aaa686816c09d64ccf08587 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 4 Jul 2022 10:32:39 +1000
Subject: [PATCH 160/712] gowin: Let the placer know about global networks

Refactor in order to detect networks that will be routed in a special
mode earlier. This makes it possible to mark the source of such networks
as a global buffer, thereby removing their influence on element
placement.

In addition, timing classes are set for some cells.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc    |  56 +++++-
 gowin/arch.h     |  14 ++
 gowin/globals.cc | 486 ++++++++++++++++++++++-------------------------
 gowin/globals.h  |  66 ++++++-
 gowin/pack.cc    |   4 +
 5 files changed, 367 insertions(+), 259 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 7b9097c93d..a968c112bb 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -25,7 +25,6 @@
 #include <regex>
 #include "embed.h"
 #include "gfx.h"
-#include "globals.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
@@ -257,6 +256,8 @@ bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
     return true;
 }
 
+void Arch::auto_longwires() {}
+
 void Arch::fix_longwire_bels()
 {
     // After routing, it is clear which wires and in which bus SS00 and SS40 are used and
@@ -552,6 +553,28 @@ void Arch::setDelayScaling(double scale, double offset)
     args.delayOffset = offset;
 }
 
+void Arch::addCellTimingCombIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_INPUT; }
+
+void Arch::addCellTimingCombOut(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_OUTPUT; }
+
+void Arch::addCellTimingRegIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; }
+
+void Arch::addCellTimingRegOut(IdString cell, IdString port)
+{
+    cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
+}
+
+void Arch::addCellTimingIO(IdString cell, IdString port)
+{
+    if (port == id_I) {
+        cellTiming[cell].portClasses[port] = TMG_ENDPOINT;
+    } else {
+        if (port == id_O) {
+            cellTiming[cell].portClasses[port] = TMG_STARTPOINT;
+        }
+    }
+}
+
 void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
 
 void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay)
@@ -1989,6 +2012,8 @@ void Arch::assignArchInfo()
 
             // add timing paths
             addCellTimingClock(cname, id_CLK);
+            addCellTimingRegIn(cname, id_CE);
+            addCellTimingRegIn(cname, id_LSR);
             IdString ports[4] = {id_A, id_B, id_C, id_D};
             for (int i = 0; i < 4; i++) {
                 DelayPair setup =
@@ -2019,7 +2044,18 @@ void Arch::assignArchInfo()
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             addCellTimingDelay(cname, id_I0, id_OF, delay);
             addCellTimingDelay(cname, id_I1, id_OF, delay);
+            addCellTimingCombIn(cname, id_SEL);
         }
+        case ID_IOB:
+            /* FALLTHRU */
+        case ID_IOBS:
+            addCellTimingIO(cname, id_I);
+            addCellTimingIO(cname, id_O);
+            break;
+        case ID_BUFS:
+            addCellTimingCombIn(cname, id_I);
+            addCellTimingCombOut(cname, id_O);
+            break;
         default:
             break;
         }
@@ -2063,4 +2099,22 @@ bool Arch::cellsCompatible(const CellInfo **cells, int count) const
     return true;
 }
 
+void Arch::route_gowin_globals(Context *ctx) { globals_router.route_globals(ctx); }
+
+void Arch::mark_gowin_globals(Context *ctx) { globals_router.mark_globals(ctx); }
+// ---------------------------------------------------------------
+void Arch::pre_pack(Context *ctx)
+{
+    if (bool_or_default(settings, id("arch.enable-auto-longwires"))) {
+        auto_longwires();
+    }
+}
+
+void Arch::post_pack(Context *ctx)
+{
+    if (bool_or_default(settings, id("arch.enable-globals"))) {
+        mark_gowin_globals(ctx);
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/gowin/arch.h b/gowin/arch.h
index c59f8eb353..cd43aa7a90 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -31,6 +31,8 @@
 #include "nextpnr_namespaces.h"
 #include "nextpnr_types.h"
 
+#include "globals.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 template <typename T> struct RelPtr
@@ -337,6 +339,11 @@ struct Arch : BaseArch<ArchRanges>
     void setDelayScaling(double scale, double offset);
 
     void addCellTimingClock(IdString cell, IdString port);
+    void addCellTimingIO(IdString cell, IdString port);
+    void addCellTimingCombIn(IdString cell, IdString port);
+    void addCellTimingCombOut(IdString cell, IdString port);
+    void addCellTimingRegIn(IdString cell, IdString port);
+    void addCellTimingRegOut(IdString cell, IdString port);
     void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
     void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
     void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);
@@ -462,6 +469,13 @@ struct Arch : BaseArch<ArchRanges>
     bool haveBelType(int x, int y, IdString bel_type);
     bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
     void fix_longwire_bels();
+    void pre_pack(Context *ctx);
+    void post_pack(Context *ctx);
+    void auto_longwires();
+
+    GowinGlobalRouter globals_router;
+    void mark_gowin_globals(Context *ctx);
+    void route_gowin_globals(Context *ctx);
 
     // chip db version
     unsigned int const chipdb_version = 1;
diff --git a/gowin/globals.cc b/gowin/globals.cc
index ed75a93888..1794dd4c39 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -18,7 +18,6 @@
  *
  */
 
-#include "globals.h"
 #include <algorithm>
 #include <iomanip>
 #include <iostream>
@@ -31,306 +30,279 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-class GowinGlobalRouter
+bool GowinGlobalRouter::is_clock_port(PortRef const &user)
 {
-  public:
-    GowinGlobalRouter(Context *ctx) : ctx(ctx){};
-
-  private:
-    // wire -> clock#
-    dict<WireId, int> used_wires;
-
-    // ordered nets
-    struct onet_t
-    {
-        IdString name;
-        int clock_ports;
-        WireId clock_io_wire; // IO wire if there is one
-
-        onet_t() : name(IdString()), clock_ports(0), clock_io_wire(WireId()) {}
-        onet_t(IdString _name) : name(_name), clock_ports(0), clock_io_wire(WireId()) {}
-
-        // sort
-        bool operator<(const onet_t &other) const
-        {
-            if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
-                return !(clock_io_wire != WireId());
-            }
-            return clock_ports < other.clock_ports;
-        }
-        // search
-        bool operator==(const onet_t &other) const { return name == other.name; }
-    };
+    if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) &&
+        user.port == id_CLK) {
+        return true;
+    }
+    return false;
+}
 
-    bool is_clock_port(PortRef const &user)
-    {
-        if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) && user.port == id_CLK) {
-            return true;
-        }
-        return false;
+std::pair<WireId, BelId> GowinGlobalRouter::clock_io(Context *ctx, PortRef const &driver)
+{
+    // XXX normally all alternative functions of the pins should be passed
+    // in the chip database, but at the moment we find them from aliases/pips
+    // XXX check diff inputs too
+    if (driver.cell == nullptr || driver.cell->type != id_IOB || !driver.cell->attrs.count(id_BEL)) {
+        return std::make_pair(WireId(), BelId());
     }
+    // clock IOs have pips output->SPINExx
 
-    WireId clock_io(PortRef const &driver)
-    {
-        // XXX normally all alternative functions of the pins should be passed
-        // in the chip database, but at the moment we find them from aliases/pips
-        // XXX check diff inputs too
-        if (driver.cell == nullptr || driver.cell->bel == BelId()) {
-            return WireId();
-        }
-        // clock IOs have pips output->SPINExx
-        BelInfo &bel = ctx->bel_info(driver.cell->bel);
-        if (bel.type != id_IOB) {
-            return WireId();
+    BelInfo &bel = ctx->bel_info(ctx->id(driver.cell->attrs[id_BEL].as_string()));
+    WireId wire = bel.pins[id_O].wire;
+    for (auto const pip : ctx->getPipsDownhill(wire)) {
+        if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
+            return std::make_pair(wire, bel.name);
         }
-        WireId wire = bel.pins[id_O].wire;
-        for (auto const pip : ctx->getPipsDownhill(wire)) {
-            if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
-                return wire;
-            }
-        }
-        return WireId();
     }
+    return std::make_pair(WireId(), BelId());
+}
 
-    // gather the clock nets
-    void gather_clock_nets(std::vector<onet_t> &clock_nets)
-    {
-        for (auto const &net : ctx->nets) {
-            NetInfo const *ni = net.second.get();
-            auto new_clock = clock_nets.end();
-            WireId clock_wire = clock_io(ni->driver);
-            if (clock_wire != WireId()) {
-                clock_nets.emplace_back(net.first);
-                new_clock = --clock_nets.end();
-                new_clock->clock_io_wire = clock_wire;
-            }
-            for (auto const &user : ni->users) {
-                if (is_clock_port(user)) {
-                    if (new_clock == clock_nets.end()) {
-                        clock_nets.emplace_back(net.first);
-                        new_clock = --clock_nets.end();
-                    }
-                    ++(new_clock->clock_ports);
+// gather the clock nets
+void GowinGlobalRouter::gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets)
+{
+    for (auto const &net : ctx->nets) {
+        NetInfo const *ni = net.second.get();
+        auto new_clock = clock_nets.end();
+        auto clock_wire_bel = clock_io(ctx, ni->driver);
+        if (clock_wire_bel.first != WireId()) {
+            clock_nets.emplace_back(net.first);
+            new_clock = --clock_nets.end();
+            new_clock->clock_io_wire = clock_wire_bel.first;
+            new_clock->clock_io_bel = clock_wire_bel.second;
+        }
+        for (auto const &user : ni->users) {
+            if (is_clock_port(user)) {
+                if (new_clock == clock_nets.end()) {
+                    clock_nets.emplace_back(net.first);
+                    new_clock = --clock_nets.end();
                 }
+                ++(new_clock->clock_ports);
             }
         }
-        // need to prioritize the nets
-        std::sort(clock_nets.begin(), clock_nets.end());
+    }
+    // need to prioritize the nets
+    std::sort(clock_nets.begin(), clock_nets.end());
 
-        if (ctx->verbose) {
-            for (auto const &net : clock_nets) {
-                log_info("  Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
-                         net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
-            }
+    if (ctx->verbose) {
+        for (auto const &net : clock_nets) {
+            log_info("  Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
+                     net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
         }
     }
+}
 
-    // non clock port
-    // returns GB pip
-    IdString route_to_non_clock_port(WireId const dstWire, int clock, pool<IdString> &used_pips,
-                                     pool<IdString> &undo_wires)
-    {
-        static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
-        char buf[40];
-        // uphill pips
-        for (auto const uphill : ctx->getPipsUphill(dstWire)) {
-            WireId srcWire = ctx->getPipSrcWire(uphill);
-            if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
-                one_hop.end()) {
-                // found one hop pip
-                if (used_wires.count(srcWire)) {
-                    if (used_wires[srcWire] != clock) {
-                        continue;
-                    }
+// non clock port
+// returns GB pip
+IdString GowinGlobalRouter::route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock,
+                                                    pool<IdString> &used_pips, pool<IdString> &undo_wires)
+{
+    static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
+    char buf[40];
+    // uphill pips
+    for (auto const uphill : ctx->getPipsUphill(dstWire)) {
+        WireId srcWire = ctx->getPipSrcWire(uphill);
+        if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) != one_hop.end()) {
+            // found one hop pip
+            if (used_wires.count(srcWire)) {
+                if (used_wires[srcWire] != clock) {
+                    continue;
+                }
+            }
+            WireInfo wi = ctx->wire_info(srcWire);
+            std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
+            snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
+            IdString gb = ctx->id(buf);
+            auto up_pips = ctx->getPipsUphill(srcWire);
+            if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
+                if (!used_wires.count(srcWire)) {
+                    used_wires.insert(std::make_pair(srcWire, clock));
+                    undo_wires.insert(srcWire);
                 }
-                WireInfo wi = ctx->wire_info(srcWire);
-                std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
-                snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
-                IdString gb = ctx->id(buf);
-                auto up_pips = ctx->getPipsUphill(srcWire);
-                if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
-                    if (!used_wires.count(srcWire)) {
-                        used_wires.insert(std::make_pair(srcWire, clock));
-                        undo_wires.insert(srcWire);
-                    }
-                    used_pips.insert(uphill);
-                    if (ctx->verbose) {
-                        log_info("    1-hop Pip:%s\n", uphill.c_str(ctx));
-                    }
-                    return gb;
+                used_pips.insert(uphill);
+                if (ctx->verbose) {
+                    log_info("    1-hop Pip:%s\n", uphill.c_str(ctx));
                 }
+                return gb;
             }
         }
-        return IdString();
     }
+    return IdString();
+}
 
-    // route one net
-    void route_net(onet_t const &net, int clock)
-    {
-        // For failed routing undo
-        pool<IdString> used_pips;
-        pool<IdString> undo_wires;
-
-        log_info("  Route net %s, use clock #%d.\n", net.name.c_str(ctx), clock);
-        for (auto const &user : ctx->net_info(net.name).users) {
-            // >>> port <- GB<clock>0
-            WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
-            if (ctx->verbose) {
-                log_info("   Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
-                         dstWire.c_str(ctx));
-            }
-
-            char buf[30];
-            PipId gb_pip_id;
-            if (user.port == id_CLK) {
-                WireInfo const wi = ctx->wire_info(dstWire);
-                snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock,
-                         ctx->wire_info(dstWire).type.c_str(ctx));
-                gb_pip_id = ctx->id(buf);
-                // sanity
-                NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
-                            ctx->getPipsUphill(dstWire).end());
-            } else {
-                // Non clock port
-                gb_pip_id = route_to_non_clock_port(dstWire, clock, used_pips, undo_wires);
-                if (gb_pip_id == IdString()) {
-                    if (ctx->verbose) {
-                        log_info("  Can't find route to %s, net %s will be routed in a standard way.\n",
-                                 dstWire.c_str(ctx), net.name.c_str(ctx));
-                    }
-                    for (IdString const undo : undo_wires) {
-                        used_wires.erase(undo);
-                    }
-                    return;
-                }
-            }
-            if (ctx->verbose) {
-                log_info("    GB Pip:%s\n", gb_pip_id.c_str(ctx));
-            }
+// route one net
+void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
+{
+    // For failed routing undo
+    pool<IdString> used_pips;
+    pool<IdString> undo_wires;
 
-            if (used_pips.count(gb_pip_id)) {
-                if (ctx->verbose) {
-                    log_info("    ^routed already^\n");
-                }
-                continue;
-            }
-            used_pips.insert(gb_pip_id);
+    log_info("  Route net %s, use clock #%d.\n", net.name.c_str(ctx), net.clock);
+    for (auto const &user : ctx->net_info(net.name).users) {
+        // >>> port <- GB<clock>0
+        WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
+        if (ctx->verbose) {
+            log_info("   Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
+                     dstWire.c_str(ctx));
+        }
 
-            // >>> GBOx <- GTx0
-            dstWire = ctx->getPipSrcWire(gb_pip_id);
-            WireInfo dstWireInfo = ctx->wire_info(dstWire);
-            int branch_tap_idx = clock > 3 ? 1 : 0;
-            snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
-                     branch_tap_idx);
-            PipId gt_pip_id = ctx->id(buf);
-            if (ctx->verbose) {
-                log_info("     GT Pip:%s\n", buf);
-            }
+        char buf[30];
+        PipId gb_pip_id;
+        if (user.port == id_CLK) {
+            WireInfo const wi = ctx->wire_info(dstWire);
+            snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, net.clock,
+                     ctx->wire_info(dstWire).type.c_str(ctx));
+            gb_pip_id = ctx->id(buf);
             // sanity
-            NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
+            NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
                         ctx->getPipsUphill(dstWire).end());
-            // if already routed
-            if (used_pips.count(gt_pip_id)) {
+        } else {
+            // Non clock port
+            gb_pip_id = route_to_non_clock_port(ctx, dstWire, net.clock, used_pips, undo_wires);
+            if (gb_pip_id == IdString()) {
                 if (ctx->verbose) {
-                    log_info("     ^routed already^\n");
+                    log_info("  Can't find route to %s, net %s will be routed in a standard way.\n", dstWire.c_str(ctx),
+                             net.name.c_str(ctx));
                 }
-                continue;
-            }
-            used_pips.insert(gt_pip_id);
-
-            // >>> GTx0 <- SPINExx
-            // XXX no optimization here, we need to store
-            // the SPINE <-> clock# correspondence in the database. In the
-            // meantime, we define in run-time in a completely suboptimal way.
-            std::vector<std::string> clock_spine;
-            dstWire = ctx->getPipSrcWire(gt_pip_id);
-            for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
-                std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
-                if (name.rfind("SPINE", 0) == 0) {
-                    clock_spine.push_back(name);
+                for (IdString const undo : undo_wires) {
+                    used_wires.erase(undo);
                 }
+                return;
             }
-            sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
-                return (a.size() < b.size()) || (a.size() == b.size() && a < b);
-            });
-            dstWireInfo = ctx->wire_info(dstWire);
-            snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
-                     clock_spine[clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
-            PipId spine_pip_id = ctx->id(buf);
+        }
+        if (ctx->verbose) {
+            log_info("    GB Pip:%s\n", gb_pip_id.c_str(ctx));
+        }
+
+        if (used_pips.count(gb_pip_id)) {
             if (ctx->verbose) {
-                log_info("      Spine Pip:%s\n", buf);
+                log_info("    ^routed already^\n");
             }
-            // sanity
-            NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
-                        ctx->getPipsUphill(dstWire).end());
-            // if already routed
-            if (used_pips.count(spine_pip_id)) {
-                if (ctx->verbose) {
-                    log_info("      ^routed already^\n");
-                }
-                continue;
+            continue;
+        }
+        used_pips.insert(gb_pip_id);
+
+        // >>> GBOx <- GTx0
+        dstWire = ctx->getPipSrcWire(gb_pip_id);
+        WireInfo dstWireInfo = ctx->wire_info(dstWire);
+        int branch_tap_idx = net.clock > 3 ? 1 : 0;
+        snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
+                 branch_tap_idx);
+        PipId gt_pip_id = ctx->id(buf);
+        if (ctx->verbose) {
+            log_info("     GT Pip:%s\n", buf);
+        }
+        // sanity
+        NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
+                    ctx->getPipsUphill(dstWire).end());
+        // if already routed
+        if (used_pips.count(gt_pip_id)) {
+            if (ctx->verbose) {
+                log_info("     ^routed already^\n");
             }
-            used_pips.insert(spine_pip_id);
+            continue;
+        }
+        used_pips.insert(gt_pip_id);
 
-            // >>> SPINExx <- IO
-            dstWire = ctx->getPipSrcWire(spine_pip_id);
-            dstWireInfo = ctx->wire_info(dstWire);
-            PipId io_pip_id = PipId();
-            for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
-                if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
-                    io_pip_id = uphill_pip;
-                }
+        // >>> GTx0 <- SPINExx
+        // XXX no optimization here, we need to store
+        // the SPINE <-> clock# correspondence in the database. In the
+        // meantime, we define in run-time in a completely suboptimal way.
+        std::vector<std::string> clock_spine;
+        dstWire = ctx->getPipSrcWire(gt_pip_id);
+        for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
+            std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
+            if (name.rfind("SPINE", 0) == 0) {
+                clock_spine.push_back(name);
             }
-            NPNR_ASSERT(io_pip_id != PipId());
+        }
+        sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
+            return (a.size() < b.size()) || (a.size() == b.size() && a < b);
+        });
+        dstWireInfo = ctx->wire_info(dstWire);
+        snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
+                 clock_spine[net.clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
+        PipId spine_pip_id = ctx->id(buf);
+        if (ctx->verbose) {
+            log_info("      Spine Pip:%s\n", buf);
+        }
+        // sanity
+        NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
+                    ctx->getPipsUphill(dstWire).end());
+        // if already routed
+        if (used_pips.count(spine_pip_id)) {
             if (ctx->verbose) {
-                log_info("       IO Pip:%s\n", io_pip_id.c_str(ctx));
+                log_info("      ^routed already^\n");
             }
-            // if already routed
-            if (used_pips.count(io_pip_id)) {
-                if (ctx->verbose) {
-                    log_info("      ^routed already^\n");
-                }
-                continue;
+            continue;
+        }
+        used_pips.insert(spine_pip_id);
+
+        // >>> SPINExx <- IO
+        dstWire = ctx->getPipSrcWire(spine_pip_id);
+        dstWireInfo = ctx->wire_info(dstWire);
+        PipId io_pip_id = PipId();
+        for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
+            if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
+                io_pip_id = uphill_pip;
             }
-            used_pips.insert(io_pip_id);
         }
-        log_info("  Net %s is routed.\n", net.name.c_str(ctx));
-        for (auto const pip : used_pips) {
-            ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
+        NPNR_ASSERT(io_pip_id != PipId());
+        if (ctx->verbose) {
+            log_info("       IO Pip:%s\n", io_pip_id.c_str(ctx));
+        }
+        // if already routed
+        if (used_pips.count(io_pip_id)) {
+            if (ctx->verbose) {
+                log_info("      ^routed already^\n");
+            }
+            continue;
         }
-        ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
+        used_pips.insert(io_pip_id);
     }
+    log_info("  Net %s is routed.\n", net.name.c_str(ctx));
+    for (auto const pip : used_pips) {
+        ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
+    }
+    ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
+}
 
-  public:
-    Context *ctx;
-    void route_globals()
-    {
-        log_info("Routing globals...\n");
+void GowinGlobalRouter::route_globals(Context *ctx)
+{
+    log_info("Routing globals...\n");
 
-        std::vector<onet_t> clock_nets;
-        gather_clock_nets(clock_nets);
-        // XXX we need to use the list of indexes of clocks from the database
-        // use 6 clocks (XXX 3 for GW1NZ-1)
-        int max_clock = 3, cur_clock = -1;
-        for (auto const &net : clock_nets) {
-            // XXX only IO clock for now
-            if (net.clock_io_wire == WireId()) {
-                log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
-                continue;
-            }
-            if (++cur_clock >= max_clock) {
-                log_info(" No more clock wires left, skip the remaining nets.\n");
-                break;
-            }
-            route_net(net, cur_clock);
-        }
+    for (auto const &net : nets) {
+        route_net(ctx, net);
     }
-};
+}
 
-void route_gowin_globals(Context *ctx)
+// Allocate networks that will be routed through the global system.
+// Mark their driver cells as global buffers to exclude them from the analysis.
+void GowinGlobalRouter::mark_globals(Context *ctx)
 {
-    GowinGlobalRouter router(ctx);
-    router.route_globals();
+    log_info("Find global nets...\n");
+
+    std::vector<globalnet_t> clock_nets;
+    gather_clock_nets(ctx, clock_nets);
+    // XXX we need to use the list of indexes of clocks from the database
+    // use 6 clocks (XXX 3 for GW1NZ-1)
+    int max_clock = 3, cur_clock = -1;
+    for (auto &net : clock_nets) {
+        // XXX only IO clock for now
+        if (net.clock_io_wire == WireId()) {
+            log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
+            continue;
+        }
+        if (++cur_clock >= max_clock) {
+            log_info(" No more clock wires left, skip the remaining nets.\n");
+            break;
+        }
+        net.clock = cur_clock;
+        BelInfo &bi = ctx->bel_info(net.clock_io_bel);
+        bi.gb = true;
+        nets.emplace_back(net);
+    }
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/gowin/globals.h b/gowin/globals.h
index 41a8727abe..69232d7c88 100644
--- a/gowin/globals.h
+++ b/gowin/globals.h
@@ -18,10 +18,74 @@
  *
  */
 
+#ifndef GOWIN_GLOBALS_H
+#define GOWIN_GLOBALS_H
+
 #include "nextpnr.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void route_gowin_globals(Context *ctx);
+class GowinGlobalRouter
+{
+  public:
+    GowinGlobalRouter() {}
+
+  private:
+    // wire -> clock#
+    dict<WireId, int> used_wires;
+
+    // ordered nets
+    struct globalnet_t
+    {
+        IdString name;
+        int clock_ports;
+        BelId clock_io_bel;
+        WireId clock_io_wire; // IO wire if there is one
+        int clock;            // clock #
+
+        globalnet_t()
+        {
+            name = IdString();
+            clock_ports = 0;
+            clock_io_bel = BelId();
+            clock_io_wire = WireId();
+            clock = -1;
+        }
+        globalnet_t(IdString _name)
+        {
+            name = _name;
+            clock_ports = 0;
+            clock_io_bel = BelId();
+            clock_io_wire = WireId();
+            clock = -1;
+        }
+
+        // sort
+        bool operator<(const globalnet_t &other) const
+        {
+            if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
+                return !(clock_io_wire != WireId());
+            }
+            return clock_ports < other.clock_ports;
+        }
+        // search
+        bool operator==(const globalnet_t &other) const { return name == other.name; }
+    };
+
+    // discovered nets
+    std::vector<globalnet_t> nets;
+
+    bool is_clock_port(PortRef const &user);
+    std::pair<WireId, BelId> clock_io(Context *ctx, PortRef const &driver);
+    void gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets);
+    IdString route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock, pool<IdString> &used_pips,
+                                     pool<IdString> &undo_wires);
+    void route_net(Context *ctx, globalnet_t const &net);
+
+  public:
+    void mark_globals(Context *ctx);
+    void route_globals(Context *ctx);
+};
 
 NEXTPNR_NAMESPACE_END
+#endif // GOWIN_GLOBALS_H
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 838201423d..5b304f10b4 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -26,6 +26,8 @@
 #include "log.h"
 #include "util.h"
 
+#include "globals.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 static void make_dummy_alu(Context *ctx, int alu_idx, CellInfo *ci, CellInfo *packed_head,
@@ -1009,6 +1011,7 @@ bool Arch::pack()
     Context *ctx = getCtx();
     try {
         log_break();
+        pre_pack(ctx);
         pack_constants(ctx);
         pack_gsr(ctx);
         pack_io(ctx);
@@ -1018,6 +1021,7 @@ bool Arch::pack()
         pack_alus(ctx);
         pack_lut_lutffs(ctx);
         pack_nonlut_ffs(ctx);
+        post_pack(ctx);
         ctx->settings[id_pack] = 1;
         ctx->assignArchInfo();
         log_info("Checksum: 0x%08x\n", ctx->checksum());

From 5d915a550ba8a825fa29a2cab3851adea20f40fb Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 4 Jul 2022 11:23:21 +1000
Subject: [PATCH 161/712] gowin: fix compilation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index a968c112bb..cdb932a621 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2045,6 +2045,7 @@ void Arch::assignArchInfo()
             addCellTimingDelay(cname, id_I0, id_OF, delay);
             addCellTimingDelay(cname, id_I1, id_OF, delay);
             addCellTimingCombIn(cname, id_SEL);
+            break;
         }
         case ID_IOB:
             /* FALLTHRU */

From e1ba379fb7633c7bc3f0545bd62906f1b0665b4b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 4 Jul 2022 18:24:15 +0200
Subject: [PATCH 162/712] generic: Use arch_pybindings_shared

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_pybindings_shared.h |   6 ++
 generic/arch_pybindings.cc             | 117 +++----------------------
 2 files changed, 18 insertions(+), 105 deletions(-)

diff --git a/common/kernel/arch_pybindings_shared.h b/common/kernel/arch_pybindings_shared.h
index b3dc0506d0..bfb58f11ab 100644
--- a/common/kernel/arch_pybindings_shared.h
+++ b/common/kernel/arch_pybindings_shared.h
@@ -145,3 +145,9 @@ fn_wrapper_1a<Context, decltype(&Context::getBelsInBucket), &Context::getBelsInB
 // bool isValidBelForCellType(IdString cell\_type, BelId bel) const
 fn_wrapper_2a<Context, decltype(&Context::isValidBelForCellType), &Context::isValidBelForCellType, pass_through<bool>,
               conv_from_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "isValidBelForCellType");
+
+fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<delay_t>,
+              pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
+
+fn_wrapper_1a<Context, decltype(&Context::getDelayNS), &Context::getDelayNS, pass_through<double>,
+              pass_through<delay_t>>::def_wrap(ctx_cls, "getDelayNS");
\ No newline at end of file
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 6d3d981c53..e0a2f0f285 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -46,6 +46,13 @@ void arch_wrap_python(py::module &m)
     typedef linear_range<WireId> WireRange;
     typedef linear_range<PipId> AllPipRange;
 
+    typedef const std::vector<PipId> &UphillPipRange;
+    typedef const std::vector<PipId> &DownhillPipRange;
+
+    typedef const std::vector<BelBucketId> &BelBucketRange;
+    typedef const std::vector<BelId> &BelRangeForBelBucket;
+    typedef const std::vector<BelPin> &BelPinRange;
+
     auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
 
     auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
@@ -62,82 +69,8 @@ void arch_wrap_python(py::module &m)
                            .def("place", &Context::place)
                            .def("route", &Context::route);
 
-    py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
-
-    fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
-    fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
-    fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
-    fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
-                    addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
-    fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
-            ctx_cls, "unbindBel");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
-    fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
-                  deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
-    fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
-                                                                                                             "getBels");
-
-    fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
-                  conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
-    fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins,
-                  wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
-                                                                                              "getWireBelPins");
-
-    fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
-                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
-    fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
-                    addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
-    fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
-            ctx_cls, "unbindWire");
-    fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
-                  conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
-                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
-    fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
-                  deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
-
-    fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap(
-            ctx_cls, "getWires");
-
-    fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap(
-            ctx_cls, "getPips");
-    fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
-    fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
-                    addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
-    fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
-            ctx_cls, "unbindPip");
-    fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
-    fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
-    fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
-                  deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
-
-    fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill,
-                  wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
-                                                                                             "getPipsDownhill");
-    fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
-                  wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
-
-    fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
-    fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
-    fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayQuad>,
-                  conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
-
-    fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<delay_t>,
-                  pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
-
-    fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
-            ctx_cls, "getChipName");
-    fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
-                                                                                                          "archId");
+    auto belpin_cls =
+            py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
 
     fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
                   conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
@@ -145,14 +78,10 @@ void arch_wrap_python(py::module &m)
     typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap;
     typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap;
     typedef dict<IdString, HierarchicalCell> HierarchyMap;
+    typedef dict<IdString, IdString> AliasMap;
+    typedef dict<IdString, HierarchicalCell> HierarchyMap;
 
-    readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
-                                                                                                             "cells");
-    readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
-                                                                                                          "nets");
-
-    fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
-                    pass_through<float>>::def_wrap(ctx_cls, "addClock");
+#include "arch_pybindings_shared.h"
 
     // Generic arch construction API
     fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdStringList>,
@@ -236,28 +165,6 @@ void arch_wrap_python(py::module &m)
                     conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellBelPinMapping", "cell"_a, "cell_pin"_a,
                                                        "bel_pin"_a);
 
-    // const\_range\<BelBucketId\> getBelBuckets() const
-    fn_wrapper_0a<Context, decltype(&Context::getBelBuckets), &Context::getBelBuckets,
-                  wrap_context<const std::vector<BelBucketId> &>>::def_wrap(ctx_cls, "getBelBuckets");
-
-    // BelBucketId getBelBucketForBel(BelId bel) const
-    fn_wrapper_1a<Context, decltype(&Context::getBelBucketForBel), &Context::getBelBucketForBel,
-                  conv_to_str<BelBucketId>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelBucketForBel");
-
-    // BelBucketId getBelBucketForCellType(IdString cell\_type) const
-    fn_wrapper_1a<Context, decltype(&Context::getBelBucketForCellType), &Context::getBelBucketForCellType,
-                  conv_to_str<BelBucketId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelBucketForCellType");
-
-    // const\_range\<BelId\> getBelsInBucket(BelBucketId bucket) const
-    fn_wrapper_1a<Context, decltype(&Context::getBelsInBucket), &Context::getBelsInBucket,
-                  wrap_context<const std::vector<BelId> &>, conv_from_str<BelBucketId>>::def_wrap(ctx_cls,
-                                                                                                  "getBelsInBucket");
-
-    // bool isValidBelForCellType(IdString cell\_type, BelId bel) const
-    fn_wrapper_2a<Context, decltype(&Context::isValidBelForCellType), &Context::isValidBelForCellType,
-                  pass_through<bool>, conv_from_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls,
-                                                                                               "isValidBelForCellType");
-
     WRAP_RANGE(m, Bel, conv_to_str<BelId>);
     WRAP_RANGE(m, Wire, conv_to_str<WireId>);
     WRAP_RANGE(m, AllPip, conv_to_str<PipId>);

From 9914f56137e152a46a921f88bc894bbced3d4c27 Mon Sep 17 00:00:00 2001
From: Gabriel Somlo <gsomlo@gmail.com>
Date: Mon, 4 Jul 2022 13:43:46 -0400
Subject: [PATCH 163/712] Enable building against unbundled pybind11

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
---
 CMakeLists.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index e000144784..3812f7dcc9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -216,7 +216,12 @@ configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/common/version.h.in ${CMAKE_CURRENT_BINARY_DIR}/generated/version.h
 )
 
-include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ 3rdparty/pybind11/include ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
+if (NOT DEFINED PYBIND11_INCLUDE_DIR)
+    # Use bundled pybind11
+    set(PYBIND11_INCLUDE_DIR "3rdparty/pybind11/include")
+endif()
+
+include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
 
 if(BUILD_HEAP)
     find_package (Eigen3 REQUIRED NO_MODULE)

From 1ebfe67daf2ec3e1e64150f09ab4c194f41d1d9d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 5 Jul 2022 20:02:12 +1000
Subject: [PATCH 164/712] gowin: Remove unnecessary functions

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 36 ++++++++----------------------------
 gowin/arch.h  |  6 +-----
 2 files changed, 9 insertions(+), 33 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 82b44f91dc..6fe40f76d6 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -553,27 +553,7 @@ void Arch::setDelayScaling(double scale, double offset)
     args.delayOffset = offset;
 }
 
-void Arch::addCellTimingCombIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_INPUT; }
-
-void Arch::addCellTimingCombOut(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_COMB_OUTPUT; }
-
-void Arch::addCellTimingRegIn(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; }
-
-void Arch::addCellTimingRegOut(IdString cell, IdString port)
-{
-    cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
-}
-
-void Arch::addCellTimingIO(IdString cell, IdString port)
-{
-    if (port == id_I) {
-        cellTiming[cell].portClasses[port] = TMG_ENDPOINT;
-    } else {
-        if (port == id_O) {
-            cellTiming[cell].portClasses[port] = TMG_STARTPOINT;
-        }
-    }
-}
+void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls) {cellTiming[cell].portClasses[port] = cls;}
 
 void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
 
@@ -2042,8 +2022,8 @@ void Arch::assignArchInfo()
 
             // add timing paths
             addCellTimingClock(cname, id_CLK);
-            addCellTimingRegIn(cname, id_CE);
-            addCellTimingRegIn(cname, id_LSR);
+            addCellTimingClass(cname, id_CE, TMG_REGISTER_INPUT);
+            addCellTimingClass(cname, id_LSR, TMG_REGISTER_INPUT);
             IdString ports[4] = {id_A, id_B, id_C, id_D};
             for (int i = 0; i < 4; i++) {
                 DelayPair setup =
@@ -2074,18 +2054,18 @@ void Arch::assignArchInfo()
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             addCellTimingDelay(cname, id_I0, id_OF, delay);
             addCellTimingDelay(cname, id_I1, id_OF, delay);
-            addCellTimingCombIn(cname, id_SEL);
+            addCellTimingClass(cname, id_SEL, TMG_COMB_INPUT);
             break;
         }
         case ID_IOB:
             /* FALLTHRU */
         case ID_IOBS:
-            addCellTimingIO(cname, id_I);
-            addCellTimingIO(cname, id_O);
+            addCellTimingClass(cname, id_I, TMG_ENDPOINT);
+            addCellTimingClass(cname, id_O, TMG_STARTPOINT);
             break;
         case ID_BUFS:
-            addCellTimingCombIn(cname, id_I);
-            addCellTimingCombOut(cname, id_O);
+            addCellTimingClass(cname, id_I, TMG_ENDPOINT);
+            addCellTimingClass(cname, id_O, TMG_STARTPOINT);
             break;
         default:
             break;
diff --git a/gowin/arch.h b/gowin/arch.h
index d02a2488ef..034e4b8604 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -339,11 +339,7 @@ struct Arch : BaseArch<ArchRanges>
     void setDelayScaling(double scale, double offset);
 
     void addCellTimingClock(IdString cell, IdString port);
-    void addCellTimingIO(IdString cell, IdString port);
-    void addCellTimingCombIn(IdString cell, IdString port);
-    void addCellTimingCombOut(IdString cell, IdString port);
-    void addCellTimingRegIn(IdString cell, IdString port);
-    void addCellTimingRegOut(IdString cell, IdString port);
+    void addCellTimingClass(IdString cell, IdString port, TimingPortClass cls);
     void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayQuad delay);
     void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayPair setup, DelayPair hold);
     void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayQuad clktoq);

From 09e388f453d9cf998391495349c88e5478b62e34 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 23 Jun 2022 18:48:31 +0100
Subject: [PATCH 165/712] netlist: Add PseudoCell API

When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.

The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
---
 common/kernel/arch_pybindings_shared.h |  8 ++-
 common/kernel/basectx.cc               | 24 +++++++
 common/kernel/basectx.h                |  4 ++
 common/kernel/context.cc               |  5 ++
 common/kernel/context.h                | 18 ++++++
 common/kernel/nextpnr_types.cc         | 10 +++
 common/kernel/nextpnr_types.h          | 86 ++++++++++++++++++--------
 common/place/detail_place_core.cc      | 12 +++-
 common/place/parallel_refine.cc        |  2 +
 common/place/place_common.cc           |  6 +-
 common/place/placer1.cc                | 20 +++---
 common/place/placer_heap.cc            | 24 ++++++-
 common/route/router2.cc                |  4 +-
 docs/netlist.md                        | 16 ++++-
 fpga_interchange/arch.h                |  6 +-
 generic/arch.cc                        |  2 +-
 16 files changed, 198 insertions(+), 49 deletions(-)

diff --git a/common/kernel/arch_pybindings_shared.h b/common/kernel/arch_pybindings_shared.h
index bfb58f11ab..d78d240c90 100644
--- a/common/kernel/arch_pybindings_shared.h
+++ b/common/kernel/arch_pybindings_shared.h
@@ -150,4 +150,10 @@ fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFro
               pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
 
 fn_wrapper_1a<Context, decltype(&Context::getDelayNS), &Context::getDelayNS, pass_through<double>,
-              pass_through<delay_t>>::def_wrap(ctx_cls, "getDelayNS");
\ No newline at end of file
+              pass_through<delay_t>>::def_wrap(ctx_cls, "getDelayNS");
+
+fn_wrapper_3a_v<Context, decltype(&Context::createRegionPlug), &Context::createRegionPlug, conv_from_str<IdString>,
+                conv_from_str<IdString>, pass_through<Loc>>::def_wrap(ctx_cls, "createRegionPlug");
+fn_wrapper_4a_v<Context, decltype(&Context::addPlugPin), &Context::addPlugPin, conv_from_str<IdString>,
+                conv_from_str<IdString>, pass_through<PortType>, conv_from_str<WireId>>::def_wrap(ctx_cls,
+                                                                                                  "addPlugPin");
diff --git a/common/kernel/basectx.cc b/common/kernel/basectx.cc
index 83a2deea7b..82cdd835b9 100644
--- a/common/kernel/basectx.cc
+++ b/common/kernel/basectx.cc
@@ -131,6 +131,30 @@ void BaseCtx::constrainCellToRegion(IdString cell, IdString region_name)
     if (!matched)
         log_warning("No cell matched '%s' when constraining to region '%s'\n", nameOf(cell), nameOf(region_name));
 }
+
+void BaseCtx::createRegionPlug(IdString name, IdString type, Loc approx_loc)
+{
+    CellInfo *cell = nullptr;
+    if (cells.count(name))
+        cell = cells.at(name).get();
+    else
+        cell = createCell(name, type);
+    cell->pseudo_cell = std::make_unique<RegionPlug>(approx_loc);
+}
+
+void BaseCtx::addPlugPin(IdString plug, IdString pin, PortType dir, WireId wire)
+{
+    if (!cells.count(plug))
+        log_error("no cell named '%s' found\n", plug.c_str(this));
+    CellInfo *ci = cells.at(plug).get();
+    RegionPlug *rplug = dynamic_cast<RegionPlug *>(ci->pseudo_cell.get());
+    if (!rplug)
+        log_error("cell '%s' is not a RegionPlug\n", plug.c_str(this));
+    rplug->port_wires[pin] = wire;
+    ci->ports[pin].name = pin;
+    ci->ports[pin].type = dir;
+}
+
 DecalXY BaseCtx::constructDecalXY(DecalId decal, float x, float y)
 {
     DecalXY dxy;
diff --git a/common/kernel/basectx.h b/common/kernel/basectx.h
index 21d6d63a9b..5775e47f21 100644
--- a/common/kernel/basectx.h
+++ b/common/kernel/basectx.h
@@ -220,6 +220,10 @@ struct BaseCtx
     void addBelToRegion(IdString name, BelId bel);
     void constrainCellToRegion(IdString cell, IdString region_name);
 
+    // Helper functions for the partial reconfiguration plug API using PseudoCells
+    void createRegionPlug(IdString name, IdString type, Loc approx_loc);
+    void addPlugPin(IdString plug, IdString pin, PortType dir, WireId wire);
+
     // Helper functions for Python bindings
     NetInfo *createNet(IdString name);
     void connectPort(IdString net, IdString cell, IdString port);
diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index e35d3e49ae..014394a60d 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -30,6 +30,9 @@ WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
     if (net_info->driver.cell == nullptr)
         return WireId();
 
+    if (net_info->driver.cell->isPseudo())
+        return net_info->driver.cell->pseudo_cell->getPortWire(net_info->driver.port);
+
     auto src_bel = net_info->driver.cell->bel;
 
     if (src_bel == BelId())
@@ -47,6 +50,8 @@ WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
 
 SSOArray<WireId, 2> Context::getNetinfoSinkWires(const NetInfo *net_info, const PortRef &user_info) const
 {
+    if (user_info.cell->isPseudo())
+        return SSOArray<WireId, 2>(1, user_info.cell->pseudo_cell->getPortWire(user_info.port));
     auto dst_bel = user_info.cell->bel;
     if (dst_bel == BelId())
         return SSOArray<WireId, 2>(0, WireId());
diff --git a/common/kernel/context.h b/common/kernel/context.h
index cb8fd25707..4a5667d039 100644
--- a/common/kernel/context.h
+++ b/common/kernel/context.h
@@ -64,6 +64,24 @@ struct Context : Arch, DeterministicRNG
     bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr,
                              dict<WireId, PipId> *route = nullptr, bool useEstimate = true);
 
+    // --------------------------------------------------------------
+    // Dispatch to the Arch API or pseudo-cell API accordingly
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override
+    {
+        return cell->pseudo_cell ? cell->pseudo_cell->getDelay(fromPort, toPort, delay)
+                                 : Arch::getCellDelay(cell, fromPort, toPort, delay);
+    }
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override
+    {
+        return cell->pseudo_cell ? cell->pseudo_cell->getPortTimingClass(port, clockInfoCount)
+                                 : Arch::getPortTimingClass(cell, port, clockInfoCount);
+    }
+    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override
+    {
+        return cell->pseudo_cell ? cell->pseudo_cell->getPortClockingInfo(port, index)
+                                 : Arch::getPortClockingInfo(cell, port, index);
+    }
+
     // --------------------------------------------------------------
     // call after changing hierpath or adding/removing nets and cells
     void fixupHierarchy();
diff --git a/common/kernel/nextpnr_types.cc b/common/kernel/nextpnr_types.cc
index 82725d6ff5..8563eb27ad 100644
--- a/common/kernel/nextpnr_types.cc
+++ b/common/kernel/nextpnr_types.cc
@@ -177,4 +177,14 @@ void CellInfo::copyPortBusTo(IdString old_name, int old_offset, bool old_bracket
     }
 }
 
+Loc CellInfo::getLocation() const
+{
+    if (pseudo_cell) {
+        return pseudo_cell->getLocation();
+    } else {
+        NPNR_ASSERT(bel != BelId());
+        return ctx->getBelLocation(bel);
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index c21182cc97..e4042aecc3 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -160,6 +160,59 @@ struct PortInfo
 
 struct Context;
 
+enum TimingPortClass
+{
+    TMG_CLOCK_INPUT,     // Clock input to a sequential cell
+    TMG_GEN_CLOCK,       // Generated clock output (PLL, DCC, etc)
+    TMG_REGISTER_INPUT,  // Input to a register, with an associated clock (may also have comb. fanout too)
+    TMG_REGISTER_OUTPUT, // Output from a register
+    TMG_COMB_INPUT,      // Combinational input, no paths end here
+    TMG_COMB_OUTPUT,     // Combinational output, no paths start here
+    TMG_STARTPOINT,      // Unclocked primary startpoint, such as an IO cell output
+    TMG_ENDPOINT,        // Unclocked primary endpoint, such as an IO cell input
+    TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
+};
+
+enum ClockEdge
+{
+    RISING_EDGE,
+    FALLING_EDGE
+};
+
+struct TimingClockingInfo
+{
+    IdString clock_port; // Port name of clock domain
+    ClockEdge edge;
+    DelayPair setup, hold; // Input timing checks
+    DelayQuad clockToQ;    // Output clock-to-Q time
+};
+
+struct PseudoCell
+{
+    virtual Loc getLocation() const = 0;
+    virtual WireId getPortWire(IdString port) const = 0;
+
+    virtual bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const = 0;
+    virtual TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const = 0;
+    virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const = 0;
+    virtual ~PseudoCell(){};
+};
+
+struct RegionPlug : PseudoCell
+{
+    RegionPlug(Loc loc) : loc(loc){}; // 'loc' is a notional location for the placer only
+    Loc getLocation() const override { return loc; }
+    WireId getPortWire(IdString port) const override { return port_wires.at(port); }
+
+    // TODO: partial reconfiguration region timing
+    bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; }
+    TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; }
+    virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; }
+
+    dict<IdString, WireId> port_wires;
+    Loc loc;
+};
+
 struct CellInfo : ArchCellInfo
 {
     CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type){};
@@ -179,6 +232,8 @@ struct CellInfo : ArchCellInfo
 
     Region *region = nullptr;
 
+    std::unique_ptr<PseudoCell> pseudo_cell{};
+
     void addInput(IdString name);
     void addOutput(IdString name);
     void addInout(IdString name);
@@ -190,6 +245,10 @@ struct CellInfo : ArchCellInfo
     // check whether a bel complies with the cell's region constraint
     bool testRegion(BelId bel) const;
 
+    bool isPseudo() const { return bool(pseudo_cell); }
+
+    Loc getLocation() const;
+
     NetInfo *getPort(IdString name)
     {
         auto found = ports.find(name);
@@ -212,33 +271,6 @@ struct CellInfo : ArchCellInfo
                        int new_offset, bool new_brackets, int width);
 };
 
-enum TimingPortClass
-{
-    TMG_CLOCK_INPUT,     // Clock input to a sequential cell
-    TMG_GEN_CLOCK,       // Generated clock output (PLL, DCC, etc)
-    TMG_REGISTER_INPUT,  // Input to a register, with an associated clock (may also have comb. fanout too)
-    TMG_REGISTER_OUTPUT, // Output from a register
-    TMG_COMB_INPUT,      // Combinational input, no paths end here
-    TMG_COMB_OUTPUT,     // Combinational output, no paths start here
-    TMG_STARTPOINT,      // Unclocked primary startpoint, such as an IO cell output
-    TMG_ENDPOINT,        // Unclocked primary endpoint, such as an IO cell input
-    TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
-};
-
-enum ClockEdge
-{
-    RISING_EDGE,
-    FALLING_EDGE
-};
-
-struct TimingClockingInfo
-{
-    IdString clock_port; // Port name of clock domain
-    ClockEdge edge;
-    DelayPair setup, hold; // Input timing checks
-    DelayQuad clockToQ;    // Output clock-to-Q time
-};
-
 struct ClockConstraint
 {
     DelayPair high;
diff --git a/common/place/detail_place_core.cc b/common/place/detail_place_core.cc
index 7e629f24e1..18118fc873 100644
--- a/common/place/detail_place_core.cc
+++ b/common/place/detail_place_core.cc
@@ -37,6 +37,8 @@ PlacePartition::PlacePartition(Context *ctx)
     x1 = 0;
     y1 = 0;
     for (auto &cell : ctx->cells) {
+        if (cell.second->isPseudo())
+            continue;
         Loc l = ctx->getBelLocation(cell.second->bel);
         x0 = std::min(x0, l.x);
         x1 = std::max(x1, l.x);
@@ -110,6 +112,8 @@ NetBB NetBB::compute(const Context *ctx, const NetInfo *net, const dict<IdString
     if (!net->driver.cell)
         return result;
     auto bel_loc = [&](const CellInfo *cell) {
+        if (cell->isPseudo())
+            return cell->getLocation();
         BelId bel = cell2bel ? cell2bel->at(cell->name) : cell->bel;
         return ctx->getBelLocation(bel);
     };
@@ -176,10 +180,12 @@ void DetailPlacerThreadState::set_partition(const PlacePartition &part)
     // Set up the original cell-bel map for all nets inside the thread
     local_cell2bel.clear();
     for (NetInfo *net : thread_nets) {
-        if (net->driver.cell)
+        if (net->driver.cell && !net->driver.cell->isPseudo())
             local_cell2bel[net->driver.cell->name] = net->driver.cell->bel;
-        for (auto &usr : net->users)
-            local_cell2bel[usr.cell->name] = usr.cell->bel;
+        for (auto &usr : net->users) {
+            if (!usr.cell->isPseudo())
+                local_cell2bel[usr.cell->name] = usr.cell->bel;
+        }
     }
 }
 
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index de71b8e093..0fb99be52b 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -390,6 +390,8 @@ struct ParallelRefine
         // Setup fast bels map
         pool<IdString> cell_types_in_use;
         for (auto &cell : ctx->cells) {
+            if (cell.second->isPseudo())
+                continue;
             IdString cell_type = cell.second->type;
             cell_types_in_use.insert(cell_type);
             if (cell.second->cluster != ClusterId())
diff --git a/common/place/place_common.cc b/common/place/place_common.cc
index e03fca553f..c2fc3b7db4 100644
--- a/common/place/place_common.cc
+++ b/common/place/place_common.cc
@@ -293,6 +293,8 @@ class ConstraintLegaliseWorker
     {
         if (cell->cluster != ClusterId() && ctx->getClusterRootCell(cell->cluster) != cell)
             return true; // Only process chain roots
+        if (cell->isPseudo())
+            return true;
         if (constraints_satisfied(cell)) {
             if (cell->cluster != ClusterId())
                 lockdown_chain(cell);
@@ -415,7 +417,7 @@ class ConstraintLegaliseWorker
     {
         log_info("Legalising relative constraints...\n");
         for (auto &cell : ctx->cells) {
-            oldLocations[cell.first] = ctx->getBelLocation(cell.second->bel);
+            oldLocations[cell.first] = cell.second->getLocation();
         }
         for (auto &cell : ctx->cells) {
             bool res = legalise_cell(cell.second.get());
@@ -448,6 +450,8 @@ bool legalise_relative_constraints(Context *ctx) { return ConstraintLegaliseWork
 int get_constraints_distance(const Context *ctx, const CellInfo *cell)
 {
     int dist = 0;
+    if (cell->isPseudo())
+        return 0;
     if (cell->bel == BelId())
         return 100000;
     Loc loc = ctx->getBelLocation(cell->bel);
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index a6ba389504..23264ce2d5 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -76,6 +76,8 @@ class SAPlacer
 
         pool<IdString> cell_types_in_use;
         for (auto &cell : ctx->cells) {
+            if (cell.second->isPseudo())
+                continue;
             IdString cell_type = cell.second->type;
             cell_types_in_use.insert(cell_type);
         }
@@ -120,7 +122,7 @@ class SAPlacer
         }
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->cluster == ClusterId())
+            if (ci->isPseudo() || ci->cluster == ClusterId())
                 continue;
             cluster2cell[ci->cluster].push_back(ci);
         }
@@ -145,6 +147,8 @@ class SAPlacer
             // Initial constraints placer
             for (auto &cell_entry : ctx->cells) {
                 CellInfo *cell = cell_entry.second.get();
+                if (cell->isPseudo())
+                    continue;
                 auto loc = cell->attrs.find(ctx->id("BEL"));
                 if (loc != cell->attrs.end()) {
                     std::string loc_name = loc->second.as_string();
@@ -187,7 +191,7 @@ class SAPlacer
 
             for (auto &cell : ctx->cells) {
                 CellInfo *ci = cell.second.get();
-                if (ci->bel == BelId()) {
+                if (!ci->isPseudo() && (ci->bel == BelId())) {
                     autoplaced.push_back(cell.second.get());
                 }
             }
@@ -217,7 +221,7 @@ class SAPlacer
         } else {
             for (auto &cell : ctx->cells) {
                 CellInfo *ci = cell.second.get();
-                if (ci->belStrength > STRENGTH_STRONG) {
+                if (ci->isPseudo() || ci->belStrength > STRENGTH_STRONG) {
                     continue;
                 } else if (ci->cluster != ClusterId()) {
                     if (ctx->getClusterRootCell(ci->cluster) == ci)
@@ -353,6 +357,8 @@ class SAPlacer
                     autoplaced.clear();
                     chain_basis.clear();
                     for (auto &cell : ctx->cells) {
+                        if (cell.second->isPseudo())
+                            continue;
                         if (cell.second->belStrength <= STRENGTH_STRONG && cell.second->cluster != ClusterId() &&
                             ctx->getClusterRootCell(cell.second->cluster) == cell.second.get())
                             chain_basis.push_back(cell.second.get());
@@ -814,7 +820,7 @@ class SAPlacer
     {
         BoundingBox bb;
         NPNR_ASSERT(net->driver.cell != nullptr);
-        Loc dloc = ctx->getBelLocation(net->driver.cell->bel);
+        Loc dloc = net->driver.cell->getLocation();
         bb.x0 = dloc.x;
         bb.x1 = dloc.x;
         bb.y0 = dloc.y;
@@ -824,9 +830,9 @@ class SAPlacer
         bb.ny0 = 1;
         bb.ny1 = 1;
         for (auto user : net->users) {
-            if (user.cell->bel == BelId())
+            if (!user.cell->isPseudo() && user.cell->bel == BelId())
                 continue;
-            Loc uloc = ctx->getBelLocation(user.cell->bel);
+            Loc uloc = user.cell->getLocation();
             if (bb.x0 == uloc.x)
                 ++bb.nx0;
             else if (uloc.x < bb.x0) {
@@ -1173,7 +1179,7 @@ class SAPlacer
         nets_by_tile.resize(max_x + 1, std::vector<dict<IdString, int>>(max_y + 1));
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (int(ci->ports.size()) > large_cell_thresh)
+            if (ci->isPseudo() || (int(ci->ports.size()) > large_cell_thresh))
                 continue;
             Loc loc = ctx->getBelLocation(ci->bel);
             auto &nbt = nets_by_tile.at(loc.x).at(loc.y);
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 4c9ffb2326..bd8cd37def 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -147,7 +147,7 @@ class HeAPPlacer
         tmg.setup();
 
         for (auto &cell : ctx->cells)
-            if (cell.second->cluster != ClusterId())
+            if (!cell.second->isPseudo() && cell.second->cluster != ClusterId())
                 cluster2cells[cell.second->cluster].push_back(cell.second.get());
     }
 
@@ -284,6 +284,8 @@ class HeAPPlacer
                 // Save solution
                 solution.clear();
                 for (auto &cell : ctx->cells) {
+                    if (cell.second->isPseudo())
+                        continue;
                     solution.emplace_back(cell.second.get(), cell.second->bel, cell.second->belStrength);
                 }
             } else {
@@ -312,6 +314,8 @@ class HeAPPlacer
         }
 
         for (auto &cell : ctx->cells) {
+            if (cell.second->isPseudo())
+                continue;
             if (cell.second->bel == BelId())
                 log_error("Found unbound cell %s\n", cell.first.c_str(ctx));
             if (ctx->getBoundBelCell(cell.second->bel) != cell.second.get())
@@ -411,7 +415,8 @@ class HeAPPlacer
         // Initial constraints placer
         for (auto &cell_entry : ctx->cells) {
             CellInfo *cell = cell_entry.second.get();
-
+            if (cell->isPseudo())
+                continue;
             auto loc = cell->attrs.find(ctx->id("BEL"));
             if (loc != cell->attrs.end()) {
                 std::string loc_name = loc->second.as_string();
@@ -461,6 +466,8 @@ class HeAPPlacer
         pool<IdString> cell_types_in_use;
         pool<BelBucketId> buckets_in_use;
         for (auto &cell : ctx->cells) {
+            if (cell.second->isPseudo())
+                continue;
             IdString cell_type = cell.second->type;
             cell_types_in_use.insert(cell_type);
             BelBucketId bucket = ctx->getBelBucketForCellType(cell_type);
@@ -527,6 +534,8 @@ class HeAPPlacer
     {
         pool<IdString> cell_types;
         for (const auto &cell : ctx->cells) {
+            if (cell.second->isPseudo())
+                continue;
             cell_types.insert(cell.second->type);
         }
 
@@ -551,6 +560,14 @@ class HeAPPlacer
 
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
+            if (ci->isPseudo()) {
+                Loc loc = ci->pseudo_cell->getLocation();
+                cell_locs[cell.first].x = loc.x;
+                cell_locs[cell.first].y = loc.y;
+                cell_locs[cell.first].locked = true;
+                cell_locs[cell.first].global = false;
+                continue;
+            }
             if (ci->bel != BelId()) {
                 Loc loc = ctx->getBelLocation(ci->bel);
                 cell_locs[cell.first].x = loc.x;
@@ -627,8 +644,9 @@ class HeAPPlacer
         int row = 0;
         solve_cells.clear();
         // First clear the udata of all cells
-        for (auto &cell : ctx->cells)
+        for (auto &cell : ctx->cells) {
             cell.second->udata = dont_solve;
+        }
         // Then update cells to be placed, which excludes cell children
         for (auto cell : place_cells) {
             if (buckets && !buckets->count(ctx->getBelBucketForCellType(cell->type)))
diff --git a/common/route/router2.cc b/common/route/router2.cc
index e943e493bc..1153f054bc 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -128,7 +128,7 @@ struct Router2
             nets.at(i).cy = 0;
 
             if (ni->driver.cell != nullptr) {
-                Loc drv_loc = ctx->getBelLocation(ni->driver.cell->bel);
+                Loc drv_loc = ni->driver.cell->getLocation();
                 nets.at(i).cx += drv_loc.x;
                 nets.at(i).cy += drv_loc.y;
             }
@@ -159,7 +159,7 @@ struct Router2
                     nets.at(i).bb.y1 = std::max(nets.at(i).bb.y1, ad.bb.y1);
                 }
                 // Add location to centroid sum
-                Loc usr_loc = ctx->getBelLocation(usr.value.cell->bel);
+                Loc usr_loc = usr.value.cell->getLocation();
                 nets.at(i).cx += usr_loc.x;
                 nets.at(i).cy += usr_loc.y;
             }
diff --git a/docs/netlist.md b/docs/netlist.md
index 5d8ca572df..43a96dde04 100644
--- a/docs/netlist.md
+++ b/docs/netlist.md
@@ -25,10 +25,24 @@ Other structures used by these basic structures include:
  - `params` and `attrs` store parameters and attributes - from the input JSON or assigned in flows to add metadata - by mapping from parameter name `IdString` to `Property`.
  - `cluster` is used to specify that the cell is inside a placement cluster, with the details of the placement within the cluster provided by the architecture.
  - `region` is a reference to a `Region` if the cell is constrained to a placement region (e.g. for partial reconfiguration or out-of-context flows) or `nullptr` otherwise.
+ - `pseudo_cell` is an optional pointer to an implementation of the pseudo-cell API, used for cells implementing virtual functions such as partition pins without a mapped bel. `bel` will always be `BelId()` for pseudo-cells.
+
+## PseudoCellAPI
+
+Pseudo-cells can be used to implement cells with runtime-defined cell pin to wire mappings. This means they don't have to be a fixed part of the architecture, example use cases could be for implementing partition pins for partial reconfiguration regions; or forcing splits between SLRs. Pseudo-cells implement a series of virtual functions to provide data that for an ordinary cell would be obtained by calling 'bel' ArchAPI functions
+
+The pseudo-cell API is as follows:
+ - `Loc getLocation() const` : get an approximate location of the pseudocell
+ - `WireId getPortWire(IdString port) const`: gets the wire corresponding to a port (or WireId if it has no wire)
+
+It also implements functions for getting timing data, mirroring that of the Arch API:
+ - `bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const`
+ - `TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const`
+ - `TimingClockingInfo getPortClockingInfo(IdString port, int index) const`
 
 ## NetInfo
 
-`NetInfo` instances have the following fields:
+`NetInfo` instances have the following fields:\
 
  - `name` is the IdString name of the net - for nets with multiple names, one name is chosen according to a set of rules by the JSON frontend
  - `hierpath` is name of the hierarchical cell containing the instance, for designs with hierarchy
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 789b188e65..aeb5578f87 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -748,11 +748,11 @@ struct Arch : ArchAPI<ArchRanges>
 
     // Get the delay through a cell from one port to another, returning false
     // if no path exists. This only considers combinational delays, as required by the Arch API
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const final;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const;
     // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
-    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const final;
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
     // Get the TimingClockingInfo of a port
-    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const final;
+    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
 
     // -------------------------------------------------
 
diff --git a/generic/arch.cc b/generic/arch.cc
index 11b5868b15..3df58c9beb 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -605,7 +605,7 @@ bool Arch::place()
         bool have_iobuf_or_constr = false;
         for (auto &cell : cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id("GENERIC_IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) {
+            if (ci->isPseudo() || ci->type == id("GENERIC_IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) {
                 have_iobuf_or_constr = true;
                 break;
             }

From 6969782a4b76dd7846bb206d08768736b9cac341 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 19 Jul 2022 18:51:25 +1000
Subject: [PATCH 166/712] gowin: Remove incomprehensible names of the muxes

There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.

Fully compatible with older versions of Apicula.

Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 15 +++++++++------
 gowin/arch.h       |  2 +-
 gowin/cells.cc     |  6 +++---
 gowin/cells.h      |  8 ++++----
 gowin/constids.inc |  4 ----
 gowin/gfx.cc       |  8 ++++----
 gowin/pack.cc      | 21 +++++++++------------
 7 files changed, 30 insertions(+), 34 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 6fe40f76d6..b37d444cee 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -553,7 +553,10 @@ void Arch::setDelayScaling(double scale, double offset)
     args.delayOffset = offset;
 }
 
-void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls) {cellTiming[cell].portClasses[port] = cls;}
+void Arch::addCellTimingClass(IdString cell, IdString port, TimingPortClass cls)
+{
+    cellTiming[cell].portClasses[port] = cls;
+}
 
 void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
 
@@ -1019,7 +1022,7 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
         // bel
         snprintf(buf, 40, "R%dC%d_MUX2_LUT%c%c", grow, gcol, mux_names[j].type, mux_names[j].bel_idx);
         belname = id(buf);
-        snprintf(buf, 40, "GW_MUX2_LUT%c", mux_names[j].type);
+        snprintf(buf, 40, "MUX2_LUT%c", mux_names[j].type);
         bel_id = id(buf);
         addBel(belname, bel_id, Loc(col, row, z), false);
 
@@ -2041,16 +2044,16 @@ void Arch::assignArchInfo()
             }
             break;
         }
-        case ID_GW_MUX2_LUT8:
+        case ID_MUX2_LUT8:
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             /* FALLTHRU */
-        case ID_GW_MUX2_LUT7:
+        case ID_MUX2_LUT7:
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             /* FALLTHRU */
-        case ID_GW_MUX2_LUT6:
+        case ID_MUX2_LUT6:
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             /* FALLTHRU */
-        case ID_GW_MUX2_LUT5: {
+        case ID_MUX2_LUT5: {
             delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
             addCellTimingDelay(cname, id_I0, id_OF, delay);
             addCellTimingDelay(cname, id_I1, id_OF, delay);
diff --git a/gowin/arch.h b/gowin/arch.h
index 034e4b8604..a1fc25ae7a 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -502,7 +502,7 @@ enum
 {
     mux_0_z = 10,     // start Z for the MUX2LUT5 bels
     iologic_0_z = 20, // start Z for the IOLOGIC bels
-    lutram_0_z = 30, // start Z for the IOLOGIC bels
+    lutram_0_z = 30,  // start Z for the IOLOGIC bels
     vcc_0_z = 277,    // virtual VCC bel Z
     gnd_0_z = 278,    // virtual VSS bel Z
     osc_z = 280,      // Z for the oscillator bels
diff --git a/gowin/cells.cc b/gowin/cells.cc
index d83b07c8a7..0c027d38a4 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -56,8 +56,8 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_CLK);
         new_cell->addInput(id_CE);
         new_cell->addInput(id_LSR);
-    } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
-               type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
+    } else if (type == id_MUX2_LUT5 || type == id_MUX2_LUT6 || type == id_MUX2_LUT7 || type == id_MUX2_LUT7 ||
+               type == id_MUX2_LUT8) {
         new_cell->addInput(id_I0);
         new_cell->addInput(id_I1);
         new_cell->addInput(id_SEL);
@@ -190,7 +190,7 @@ void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
     ram->movePortTo(ctx->id("DI[1]"), ramw, id_B5);
     ram->movePortTo(ctx->id("DI[2]"), ramw, id_C5);
     ram->movePortTo(ctx->id("DI[3]"), ramw, id_D5);
-    
+
     ram->movePortTo(ctx->id("CLK"), ramw, id_CLK);
     ram->movePortTo(ctx->id("WRE"), ramw, id_LSR);
 }
diff --git a/gowin/cells.h b/gowin/cells.h
index b6d8649733..84de70bdf0 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -62,22 +62,22 @@ inline bool is_alu(const BaseCtx *ctx, const CellInfo *cell) { return (cell->typ
 // is MUX2_LUT5
 inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); }
 
-inline bool is_gw_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT5); }
+inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); }
 
 // is MUX2_LUT6
 inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); }
 
-inline bool is_gw_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT6); }
+inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); }
 
 // is MUX2_LUT7
 inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); }
 
-inline bool is_gw_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT7); }
+inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); }
 
 // is MUX2_LUT8
 inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); }
 
-inline bool is_gw_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_GW_MUX2_LUT8); }
+inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); }
 
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 8916f093ff..ec1137fc59 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -775,10 +775,6 @@ X(MUX2_LUT5)
 X(MUX2_LUT6)
 X(MUX2_LUT7)
 X(MUX2_LUT8)
-X(GW_MUX2_LUT5)
-X(GW_MUX2_LUT6)
-X(GW_MUX2_LUT7)
-X(GW_MUX2_LUT8)
 X(I0MUX0)
 X(I1MUX0)
 X(I0MUX1)
diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index fcd42c7c74..9c9bc3fc02 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -5637,28 +5637,28 @@ void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel)
         }
         arch->setBelDecal(bel.name, active, inactive);
         break;
-    case ID_GW_MUX2_LUT5:
+    case ID_MUX2_LUT5:
         active.x = inactive.x = bel.x + mux2lut5_x;
         active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut5_y[(bel.z - BelZ::mux_0_z) >> 1];
         active.decal = id_DECAL_MUXUPPER_ACTIVE;
         inactive.decal = id_DECAL_MUXUPPER_INACTIVE;
         arch->setBelDecal(bel.name, active, inactive);
         break;
-    case ID_GW_MUX2_LUT6:
+    case ID_MUX2_LUT6:
         active.x = inactive.x = bel.x + mux2lut6_x;
         active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut6_y[(bel.z - BelZ::mux_0_z) / 5];
         active.decal = id_DECAL_MUXLOWER_ACTIVE;
         inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
         arch->setBelDecal(bel.name, active, inactive);
         break;
-    case ID_GW_MUX2_LUT7:
+    case ID_MUX2_LUT7:
         active.x = inactive.x = bel.x + mux2lut7_x;
         active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut7_y;
         active.decal = id_DECAL_MUXLOWER_ACTIVE;
         inactive.decal = id_DECAL_MUXLOWER_INACTIVE;
         arch->setBelDecal(bel.name, active, inactive);
         break;
-    case ID_GW_MUX2_LUT8:
+    case ID_MUX2_LUT8:
         active.x = inactive.x = bel.x + mux2lut8_x;
         active.y = inactive.y = arch->gridDimY - 1. - bel.y + mux2lut8_y;
         active.decal = id_DECAL_MUXUPPER_ACTIVE;
diff --git a/gowin/pack.cc b/gowin/pack.cc
index dbf949d4f1..4b5bc81db6 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -266,7 +266,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
             return;
         }
 
-        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC");
+        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_MUX2_LUT5, ci->name.str(ctx) + "_LC");
         if (ctx->verbose) {
             log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
         }
@@ -309,7 +309,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
             return;
         }
 
-        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC");
+        std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_MUX2_LUT5, ci->name.str(ctx) + "_LC");
         if (ctx->verbose) {
             log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
         }
@@ -413,7 +413,7 @@ static void pack_mux2_lut6(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
 {
     static int x[] = {0, 0};
     static int z[] = {+1, -1};
-    pack_mux2_lut(ctx, ci, is_gw_mux2_lut5, '6', id_GW_MUX2_LUT6, x, z, packed_cells, delete_nets, new_cells);
+    pack_mux2_lut(ctx, ci, is_mux2_lut5, '6', id_MUX2_LUT6, x, z, packed_cells, delete_nets, new_cells);
 }
 
 // pack MUX2_LUT7
@@ -422,7 +422,7 @@ static void pack_mux2_lut7(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
 {
     static int x[] = {0, 0};
     static int z[] = {+2, -2};
-    pack_mux2_lut(ctx, ci, is_gw_mux2_lut6, '7', id_GW_MUX2_LUT7, x, z, packed_cells, delete_nets, new_cells);
+    pack_mux2_lut(ctx, ci, is_mux2_lut6, '7', id_MUX2_LUT7, x, z, packed_cells, delete_nets, new_cells);
 }
 
 // pack MUX2_LUT8
@@ -431,7 +431,7 @@ static void pack_mux2_lut8(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce
 {
     static int x[] = {1, 0};
     static int z[] = {-4, -4};
-    pack_mux2_lut(ctx, ci, is_gw_mux2_lut7, '8', id_GW_MUX2_LUT8, x, z, packed_cells, delete_nets, new_cells);
+    pack_mux2_lut(ctx, ci, is_mux2_lut7, '8', id_MUX2_LUT8, x, z, packed_cells, delete_nets, new_cells);
 }
 
 // Pack wide LUTs
@@ -707,16 +707,14 @@ void pack_sram(Context *ctx)
         if (is_sram(ctx, ci)) {
 
             // Create RAMW slice
-            std::unique_ptr<CellInfo> ramw_slice =
-                    create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
+            std::unique_ptr<CellInfo> ramw_slice = create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
             sram_to_ramw_split(ctx, ci, ramw_slice.get());
             ramw_slice->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
 
             // Create actual RAM slices
             std::unique_ptr<CellInfo> ram_comb[4];
             for (int i = 0; i < 4; i++) {
-                ram_comb[i] = create_generic_cell(ctx, id_SLICE,
-                                                ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
+                ram_comb[i] = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "$SRAM_SLICE" + std::to_string(i));
                 ram_comb[i]->params[id_FF_USED] = 1;
                 ram_comb[i]->params[id_FF_TYPE] = std::string("RAM");
                 sram_to_slice(ctx, ci, ram_comb[i].get(), i);
@@ -724,8 +722,8 @@ void pack_sram(Context *ctx)
             // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
             std::unique_ptr<CellInfo> ramw_block[2];
             for (int i = 0; i < 2; i++) {
-                ramw_block[i] = create_generic_cell(ctx, id_SLICE,
-                                                    ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
+                ramw_block[i] =
+                        create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
                 ram_comb[i]->params[id_FF_USED] = 1;
                 ramw_block[i]->params[id_FF_TYPE] = std::string("RAM");
             }
@@ -782,7 +780,6 @@ void pack_sram(Context *ctx)
     }
 }
 
-
 static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
 {
     return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||

From ad502bf64b9d4100da131eb76814351b4aa11bce Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 19 Jul 2022 09:58:00 +0100
Subject: [PATCH 167/712] nexus: Fix CSDECODE parsing

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 0870bf4066..15752171e4 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -43,7 +43,7 @@ Property Arch::parse_lattice_param_from_cell(const CellInfo *ci, IdString prop,
 // Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
 Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char *ci) const
 {
-    if (val.is_string) {
+    if (val.is_string && !prop.in(id_CSDECODE_A, id_CSDECODE_B, id_CSDECODE_R, id_CSDECODE_W)) {
         const std::string &s = val.str;
         Property temp;
 

From ce2335bc0065df5217585f341f7ed46aa8f66c36 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 19 Jul 2022 20:20:26 +1000
Subject: [PATCH 168/712] gowin: fix compilation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/cells.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/gowin/cells.h b/gowin/cells.h
index 84de70bdf0..3a570f9740 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -62,23 +62,15 @@ inline bool is_alu(const BaseCtx *ctx, const CellInfo *cell) { return (cell->typ
 // is MUX2_LUT5
 inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); }
 
-inline bool is_mux2_lut5(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT5); }
-
 // is MUX2_LUT6
 inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); }
 
-inline bool is_mux2_lut6(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT6); }
-
 // is MUX2_LUT7
 inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); }
 
-inline bool is_mux2_lut7(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT7); }
-
 // is MUX2_LUT8
 inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); }
 
-inline bool is_mux2_lut8(const BaseCtx *ctx, const CellInfo *cell) { return (cell->type.index == ID_MUX2_LUT8); }
-
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
 {

From 37f0886cb9e949cb49250f973a852c816b5ab892 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 4 Aug 2022 10:55:19 +0200
Subject: [PATCH 169/712] generic: addBelPin with direction as an arg

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.cc            | 30 +++++-------------------------
 generic/arch.h             |  1 +
 generic/arch_pybindings.cc |  6 ++++++
 3 files changed, 12 insertions(+), 25 deletions(-)

diff --git a/generic/arch.cc b/generic/arch.cc
index 3df58c9beb..9992e1cd2e 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -134,40 +134,20 @@ BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidd
     return bel;
 }
 
-void Arch::addBelInput(BelId bel, IdString name, WireId wire)
-{
-    auto &bi = bel_info(bel);
-    NPNR_ASSERT(bi.pins.count(name) == 0);
-    PinInfo &pi = bi.pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_IN;
-
-    if (wire != WireId())
-        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_IN); }
 
-void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
-{
-    auto &bi = bel_info(bel);
-    NPNR_ASSERT(bi.pins.count(name) == 0);
-    PinInfo &pi = bi.pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_OUT;
+void Arch::addBelOutput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_OUT); }
 
-    if (wire != WireId())
-        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInout(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_INOUT); }
 
-void Arch::addBelInout(BelId bel, IdString name, WireId wire)
+void Arch::addBelPin(BelId bel, IdString name, WireId wire, PortType type)
 {
     auto &bi = bel_info(bel);
     NPNR_ASSERT(bi.pins.count(name) == 0);
     PinInfo &pi = bi.pins[name];
     pi.name = name;
     pi.wire = wire;
-    pi.type = PORT_INOUT;
+    pi.type = type;
 
     if (wire != WireId())
         wire_info(wire).bel_pins.push_back(BelPin{bel, name});
diff --git a/generic/arch.h b/generic/arch.h
index 157ff8afec..688392da2d 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -200,6 +200,7 @@ struct Arch : BaseArch<ArchRanges>
     void addBelInput(BelId bel, IdString name, WireId wire);
     void addBelOutput(BelId bel, IdString name, WireId wire);
     void addBelInout(BelId bel, IdString name, WireId wire);
+    void addBelPin(BelId bel, IdString name, WireId wire, PortType type);
 
     WireId addWireAsBelInput(BelId bel, IdString name);
     WireId addWireAsBelOutput(BelId bel, IdString name);
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index e0a2f0f285..a5a0bed94c 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -105,6 +105,12 @@ void arch_wrap_python(py::module &m)
     fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>,
                     conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a,
                                                                               "wire"_a);
+    fn_wrapper_4a_v<Context, decltype(&Context::addBelPin), &Context::addBelPin, conv_from_str<BelId>,
+                    conv_from_str<IdString>, conv_from_str<WireId>, pass_through<PortType>>::def_wrap(ctx_cls,
+                                                                                                      "addBelPin",
+                                                                                                      "bel"_a, "name"_a,
+                                                                                                      "wire"_a,
+                                                                                                      "type"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
                     conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);

From 77c82b0fbf15892b0c8222bac89564f3f024493e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 10 Aug 2022 10:57:17 +0100
Subject: [PATCH 170/712] refactor: id(stringf(...)) to new idf(...) helper

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/basectx.cc           | 12 ++++++
 common/kernel/basectx.h            |  2 +
 common/kernel/nextpnr_types.cc     |  8 ++--
 ecp5/arch.cc                       |  8 ++--
 ecp5/pack.cc                       |  2 +-
 fpga_interchange/arch.cc           |  2 +-
 fpga_interchange/macros.cc         |  2 +-
 generic/viaduct/example/example.cc | 28 +++++++-------
 generic/viaduct/okami/okami.cc     | 61 +++++++++++++++---------------
 generic/viaduct_helpers.cc         |  6 +--
 gowin/pack.cc                      |  2 +-
 ice40/arch.cc                      |  4 +-
 machxo2/arch.cc                    |  8 ++--
 mistral/arch.cc                    |  2 +-
 mistral/globals.cc                 |  6 +--
 mistral/io.cc                      |  4 +-
 mistral/lab.cc                     | 38 +++++++++----------
 mistral/m10k.cc                    | 34 +++++++----------
 mistral/pack.cc                    | 11 ++----
 nexus/arch.cc                      | 10 ++---
 nexus/fasm.cc                      |  4 +-
 nexus/pack.cc                      | 51 ++++++++++++-------------
 22 files changed, 152 insertions(+), 153 deletions(-)

diff --git a/common/kernel/basectx.cc b/common/kernel/basectx.cc
index 82cdd835b9..777d06e15d 100644
--- a/common/kernel/basectx.cc
+++ b/common/kernel/basectx.cc
@@ -26,6 +26,18 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+IdString BaseCtx::idf(const char *fmt, ...) const
+{
+    std::string string;
+    va_list ap;
+
+    va_start(ap, fmt);
+    string = vstringf(fmt, ap);
+    va_end(ap);
+
+    return id(string);
+}
+
 const char *BaseCtx::nameOfBel(BelId bel) const
 {
     const Context *ctx = getCtx();
diff --git a/common/kernel/basectx.h b/common/kernel/basectx.h
index 5775e47f21..c8791a2b96 100644
--- a/common/kernel/basectx.h
+++ b/common/kernel/basectx.h
@@ -162,6 +162,8 @@ struct BaseCtx
 
     IdString id(const char *s) const { return IdString(this, s); }
 
+    IdString idf(const char *fmt, ...) const; // create IdString using printf formatting
+
     Context *getCtx() { return as_ctx; }
 
     const Context *getCtx() const { return as_ctx; }
diff --git a/common/kernel/nextpnr_types.cc b/common/kernel/nextpnr_types.cc
index 8563eb27ad..6da37763bf 100644
--- a/common/kernel/nextpnr_types.cc
+++ b/common/kernel/nextpnr_types.cc
@@ -152,8 +152,8 @@ void CellInfo::movePortBusTo(IdString old_name, int old_offset, bool old_bracket
                              IdString new_name, int new_offset, bool new_brackets, int width)
 {
     for (int i = 0; i < width; i++) {
-        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
-        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
+        IdString old_port = ctx->idf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset);
+        IdString new_port = ctx->idf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset);
         movePortTo(old_port, new_cell, new_port);
     }
 }
@@ -171,8 +171,8 @@ void CellInfo::copyPortBusTo(IdString old_name, int old_offset, bool old_bracket
                              IdString new_name, int new_offset, bool new_brackets, int width)
 {
     for (int i = 0; i < width; i++) {
-        IdString old_port = ctx->id(stringf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset));
-        IdString new_port = ctx->id(stringf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset));
+        IdString old_port = ctx->idf(old_brackets ? "%s[%d]" : "%s%d", old_name.c_str(ctx), i + old_offset);
+        IdString new_port = ctx->idf(new_brackets ? "%s[%d]" : "%s%d", new_name.c_str(ctx), i + new_offset);
         copyPortTo(old_port, new_cell, new_port);
     }
 }
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index d98ee54cee..0b763612de 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -121,17 +121,17 @@ Arch::Arch(ArchArgs args) : args(args)
     BaseArch::init_bel_buckets();
 
     for (int i = 0; i < chip_info->width; i++)
-        x_ids.push_back(id(stringf("X%d", i)));
+        x_ids.push_back(idf("X%d", i));
     for (int i = 0; i < chip_info->height; i++)
-        y_ids.push_back(id(stringf("Y%d", i)));
+        y_ids.push_back(idf("Y%d", i));
 
     for (int i = 0; i < chip_info->width; i++) {
-        IdString x_id = id(stringf("X%d", i));
+        IdString x_id = idf("X%d", i);
         x_ids.push_back(x_id);
         id_to_x[x_id] = i;
     }
     for (int i = 0; i < chip_info->height; i++) {
-        IdString y_id = id(stringf("Y%d", i));
+        IdString y_id = idf("Y%d", i);
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 7aa9b4c4b0..4cd33deee3 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -801,7 +801,7 @@ class Ecp5Packer
                 ci->disconnectPort(id_WRE);
 
                 for (int i = 0; i < 4; i++)
-                    ci->disconnectPort(ctx->id(stringf("RAD[%d]", i)));
+                    ci->disconnectPort(ctx->idf("RAD[%d]", i));
 
                 // Setup placement constraints
                 // Use the 0th bit as an anchor
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 6a7c4fe137..3ce9f79e4a 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -907,7 +907,7 @@ static void prepare_sites_for_routing(Context *ctx)
 
             // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for
             // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it
-            IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin)));
+            IdString cell_pin = ctx->idf("%s_PHYS", ctx->nameOf(bel_pin));
 
             PortInfo port_info;
             port_info.name = cell_pin;
diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc
index 8f7f823162..cc67833aba 100644
--- a/fpga_interchange/macros.cc
+++ b/fpga_interchange/macros.cc
@@ -45,7 +45,7 @@ static const MacroExpansionPOD *lookup_macro_rules(const ChipInfoPOD *chip, IdSt
 
 static IdString derived_name(Context *ctx, IdString base_name, IdString suffix)
 {
-    return ctx->id(stringf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx)));
+    return ctx->idf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx));
 }
 
 void Arch::expand_macros()
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
index 49b3679269..987c323697 100644
--- a/generic/viaduct/example/example.cc
+++ b/generic/viaduct/example/example.cc
@@ -108,24 +108,23 @@ struct ExampleImpl : ViaductAPI
                 auto &w = row_wires.at(x);
                 for (int z = 0; z < N; z++) {
                     // Clock input
-                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y));
+                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("CLK%d", z)), ctx->id("CLK"), x, y));
                     // FF input
-                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y));
+                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("D%d", z)), ctx->id("D"), x, y));
                     // FF and LUT outputs
-                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y));
-                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y));
+                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("Q%d", z)), ctx->id("Q"), x, y));
+                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("F%d", z)), ctx->id("F"), x, y));
                     // LUT inputs
                     for (int i = 0; i < K; i++)
-                        w.i.push_back(
-                                ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y));
+                        w.i.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("L%dI%d", z, i)), ctx->id("I"), x, y));
                 }
                 // Local wires
                 for (int l = 0; l < Wl; l++)
-                    w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("LOCAL%d", l))), ctx->id("LOCAL"), x, y));
+                    w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("LOCAL%d", l)), ctx->id("LOCAL"), x, y));
                 // Pad wires for IO
                 if (is_io(x, y) && x != y)
                     for (int z = 0; z < 2; z++)
-                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y));
+                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)), id_PAD, x, y));
             }
         }
     }
@@ -139,7 +138,7 @@ struct ExampleImpl : ViaductAPI
     {
         auto &w = wires_by_tile.at(y).at(x);
         for (int z = 0; z < 2; z++) {
-            BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false);
+            BelId b = ctx->addBel(h.xy_id(x, y, ctx->idf("IO%d", z)), id_IOB, Loc(x, y, z), false, false);
             ctx->addBelInout(b, id_PAD, w.pad.at(z));
             ctx->addBelInput(b, id_I, w.i.at(z * K + 0));
             ctx->addBelInput(b, id_EN, w.i.at(z * K + 1));
@@ -157,17 +156,16 @@ struct ExampleImpl : ViaductAPI
         auto &w = wires_by_tile.at(y).at(x);
         for (int z = 0; z < N; z++) {
             // Create LUT bel
-            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false,
-                                    false);
+            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_LUT", z)), id_LUT4, Loc(x, y, z * 2), false, false);
             for (int k = 0; k < K; k++)
-                ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.i.at(z * K + k));
+                ctx->addBelInput(lut, ctx->idf("I[%d]", k), w.i.at(z * K + k));
             ctx->addBelOutput(lut, id_F, w.f.at(z));
             // FF data can come from LUT output or LUT I3
             add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
             add_pip(Loc(x, y, 0), w.i.at(z * K + (K - 1)), w.d.at(z));
             // Create DFF bel
-            BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1),
-                                    false, false);
+            BelId dff =
+                    ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_FF", z)), id_DFF, Loc(x, y, z * 2 + 1), false, false);
             ctx->addBelInput(dff, id_CLK, w.clk.at(z));
             ctx->addBelInput(dff, id_D, w.d.at(z));
             ctx->addBelOutput(dff, id_Q, w.q.at(z));
@@ -254,7 +252,7 @@ struct ExampleImpl : ViaductAPI
             auto &fc = fast_cell_info.at(ci->flat_index);
             if (ci->type == id_LUT4) {
                 fc.lut_f = ci->getPort(id_F);
-                fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+                fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr);
             } else if (ci->type == id_DFF) {
                 fc.ff_d = ci->getPort(id_D);
             }
diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc
index 864bdb456d..8142756fec 100644
--- a/generic/viaduct/okami/okami.cc
+++ b/generic/viaduct/okami/okami.cc
@@ -120,45 +120,45 @@ struct OkamiImpl : ViaductAPI
                 auto &w = row_wires.at(x);
                 for (int z = 0; z < N; z++) {
                     // Clock input
-                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y));
+                    w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("CLK%d", z)), ctx->id("CLK"), x, y));
                     // FF input
-                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y));
+                    w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("D%d", z)), ctx->id("D"), x, y));
                     // FF and LUT outputs
-                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y));
-                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y));
+                    w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("Q%d", z)), ctx->id("Q"), x, y));
+                    w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("F%d", z)), ctx->id("F"), x, y));
                     // LUT inputs
                     for (int i = 0; i < K; i++)
                         w.slice_inputs.push_back(
-                                ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y));
-                    w.slice_outputs.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("SLICEOUT[%d]", z))),
-                                                           ctx->id("SLICEOUT"), x, y));
+                                ctx->addWire(h.xy_id(x, y, ctx->idf("L%dI%d", z, i)), ctx->id("I"), x, y));
+                    w.slice_outputs.push_back(
+                            ctx->addWire(h.xy_id(x, y, ctx->idf("SLICEOUT[%d]", z)), ctx->id("SLICEOUT"), x, y));
                 }
                 // Tile inputs
                 for (int tile_input = 0; tile_input < InputMuxCount; tile_input++) {
-                    w.tile_inputs_north.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEINN[%d]", tile_input))), ctx->id("TILEINN"), x, y));
-                    w.tile_inputs_east.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEINE[%d]", tile_input))), ctx->id("TILEINE"), x, y));
-                    w.tile_inputs_south.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEINS[%d]", tile_input))), ctx->id("TILEINS"), x, y));
-                    w.tile_inputs_west.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEINW[%d]", tile_input))), ctx->id("TILEINW"), x, y));
+                    w.tile_inputs_north.push_back(
+                            ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINN[%d]", tile_input)), ctx->id("TILEINN"), x, y));
+                    w.tile_inputs_east.push_back(
+                            ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINE[%d]", tile_input)), ctx->id("TILEINE"), x, y));
+                    w.tile_inputs_south.push_back(
+                            ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINS[%d]", tile_input)), ctx->id("TILEINS"), x, y));
+                    w.tile_inputs_west.push_back(
+                            ctx->addWire(h.xy_id(x, y, ctx->idf("TILEINW[%d]", tile_input)), ctx->id("TILEINW"), x, y));
                 }
                 // Tile outputs
                 for (int tile_output = 0; tile_output < OutputMuxCount; tile_output++) {
-                    w.tile_outputs_north.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEOUTN[%d]", tile_output))), ctx->id("TILEOUTN"), x, y));
-                    w.tile_outputs_east.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEOUTE[%d]", tile_output))), ctx->id("TILEOUTE"), x, y));
-                    w.tile_outputs_south.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEOUTS[%d]", tile_output))), ctx->id("TILEOUTS"), x, y));
-                    w.tile_outputs_west.push_back(ctx->addWire(
-                            h.xy_id(x, y, ctx->id(stringf("TILEOUTW[%d]", tile_output))), ctx->id("TILEOUTW"), x, y));
+                    w.tile_outputs_north.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTN[%d]", tile_output)),
+                                                                ctx->id("TILEOUTN"), x, y));
+                    w.tile_outputs_east.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTE[%d]", tile_output)),
+                                                               ctx->id("TILEOUTE"), x, y));
+                    w.tile_outputs_south.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTS[%d]", tile_output)),
+                                                                ctx->id("TILEOUTS"), x, y));
+                    w.tile_outputs_west.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("TILEOUTW[%d]", tile_output)),
+                                                               ctx->id("TILEOUTW"), x, y));
                 }
                 // Pad wires for IO
                 if (is_io(x, y) && x != y)
                     for (int z = 0; z < 2; z++)
-                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y));
+                        w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)), id_PAD, x, y));
             }
         }
     }
@@ -172,7 +172,7 @@ struct OkamiImpl : ViaductAPI
     {
         auto &w = wires_by_tile.at(y).at(x);
         for (int z = 0; z < 2; z++) {
-            BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false);
+            BelId b = ctx->addBel(h.xy_id(x, y, ctx->idf("IO%d", z)), id_IOB, Loc(x, y, z), false, false);
             ctx->addBelInout(b, id_PAD, w.pad.at(z));
             ctx->addBelInput(b, id_I, w.slice_inputs.at(z * K + 0));
             ctx->addBelInput(b, id_EN, w.slice_inputs.at(z * K + 1));
@@ -190,17 +190,16 @@ struct OkamiImpl : ViaductAPI
         auto &w = wires_by_tile.at(y).at(x);
         for (int z = 0; z < N; z++) {
             // Create LUT bel
-            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false,
-                                    false);
+            BelId lut = ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_LUT", z)), id_LUT4, Loc(x, y, z * 2), false, false);
             for (int k = 0; k < K; k++)
-                ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.slice_inputs.at(z * K + k));
+                ctx->addBelInput(lut, ctx->idf("I[%d]", k), w.slice_inputs.at(z * K + k));
             ctx->addBelOutput(lut, id_F, w.f.at(z));
             // FF data can come from LUT output or LUT I3
             add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
             add_pip(Loc(x, y, 0), w.slice_inputs.at(z * K + (K - 1)), w.d.at(z));
             // Create DFF bel
-            BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1),
-                                    false, false);
+            BelId dff =
+                    ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_FF", z)), id_DFF, Loc(x, y, z * 2 + 1), false, false);
             ctx->addBelInput(dff, id_CLK, w.clk.at(z));
             ctx->addBelInput(dff, id_D, w.d.at(z));
             ctx->addBelOutput(dff, id_Q, w.q.at(z));
@@ -495,7 +494,7 @@ struct OkamiImpl : ViaductAPI
             auto &fc = fast_cell_info.at(ci->flat_index);
             if (ci->type == id_LUT4) {
                 fc.lut_f = ci->getPort(id_F);
-                fc.lut_i3_used = (ci->getPort(ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+                fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr);
             } else if (ci->type == id_DFF) {
                 fc.ff_d = ci->getPort(id_D);
             }
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index 153d2a0e6a..53df625cf9 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -29,15 +29,15 @@ void ViaductHelpers::resize_ids(int x, int y, int z)
 {
     NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000 && z <= 1000);
     while (int(x_ids.size()) <= x) {
-        IdString next = ctx->id(stringf("X%d", int(x_ids.size())));
+        IdString next = ctx->idf("X%d", int(x_ids.size()));
         x_ids.push_back(next);
     }
     while (int(y_ids.size()) <= y) {
-        IdString next = ctx->id(stringf("Y%d", int(y_ids.size())));
+        IdString next = ctx->idf("Y%d", int(y_ids.size()));
         y_ids.push_back(next);
     }
     while (int(z_ids.size()) <= y) {
-        IdString next = ctx->id(stringf("Z%d", int(z_ids.size())));
+        IdString next = ctx->idf("Z%d", int(z_ids.size()));
         z_ids.push_back(next);
     }
 }
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 4b5bc81db6..d978ac408a 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -733,7 +733,7 @@ void pack_sram(Context *ctx)
             // ci->disconnectPort(id_WRE);
 
             for (int i = 0; i < 4; i++)
-                ci->disconnectPort(ctx->id(stringf("RAD[%d]", i)));
+                ci->disconnectPort(ctx->idf("RAD[%d]", i));
 
             // Setup placement constraints
             // Use the 0th bit as an anchor
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 6746b3028f..905b8d615e 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -111,12 +111,12 @@ Arch::Arch(ArchArgs args) : args(args)
         log_error("Unsupported package '%s'.\n", args.package.c_str());
 
     for (int i = 0; i < chip_info->width; i++) {
-        IdString x_id = id(stringf("X%d", i));
+        IdString x_id = idf("X%d", i);
         x_ids.push_back(x_id);
         id_to_x[x_id] = i;
     }
     for (int i = 0; i < chip_info->height; i++) {
-        IdString y_id = id(stringf("Y%d", i));
+        IdString y_id = idf("Y%d", i);
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 5fcdeaf759..b1a4a62a99 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -93,17 +93,17 @@ Arch::Arch(ArchArgs args) : args(args)
     BaseArch::init_bel_buckets();
 
     for (int i = 0; i < chip_info->width; i++)
-        x_ids.push_back(id(stringf("X%d", i)));
+        x_ids.push_back(idf("X%d", i));
     for (int i = 0; i < chip_info->height; i++)
-        y_ids.push_back(id(stringf("Y%d", i)));
+        y_ids.push_back(idf("Y%d", i));
 
     for (int i = 0; i < chip_info->width; i++) {
-        IdString x_id = id(stringf("X%d", i));
+        IdString x_id = idf("X%d", i);
         x_ids.push_back(x_id);
         id_to_x[x_id] = i;
     }
     for (int i = 0; i < chip_info->height; i++) {
-        IdString y_id = id(stringf("Y%d", i));
+        IdString y_id = idf("Y%d", i);
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
diff --git a/mistral/arch.cc b/mistral/arch.cc
index 46ed4f62a5..4023f5c317 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -88,7 +88,7 @@ Arch::Arch(ArchArgs args)
 
     // Setup fast identifier maps
     for (int i = 0; i < 1024; i++) {
-        IdString int_id = id(stringf("%d", i));
+        IdString int_id = idf("%d", i);
         int2id.push_back(int_id);
         id2int[int_id] = i;
     }
diff --git a/mistral/globals.cc b/mistral/globals.cc
index 1ba709191e..6af8920d76 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -30,7 +30,7 @@ void Arch::create_clkbuf(int x, int y)
             continue; // TODO: why do other Zs not work?
         // For now we only consider the input path from general routing, other inputs like dedicated clock pins are
         // still a TODO
-        BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA);
+        BelId bel = add_bel(x, y, idf("CLKBUF[%d]", z), id_MISTRAL_CLKENA);
         add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z));
         add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT));
         // TODO: enable pin
@@ -48,9 +48,9 @@ void Arch::create_hps_mpu_general_purpose(int x, int y)
     BelId gp_bel =
             add_bel(x, y, id_cyclonev_hps_interface_mpu_general_purpose, id_cyclonev_hps_interface_mpu_general_purpose);
     for (int i = 0; i < 32; i++) {
-        add_bel_pin(gp_bel, id(stringf("gp_in[%d]", i)), PORT_IN,
+        add_bel_pin(gp_bel, idf("gp_in[%d]", i), PORT_IN,
                     get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_IN, i));
-        add_bel_pin(gp_bel, id(stringf("gp_out[%d]", i)), PORT_OUT,
+        add_bel_pin(gp_bel, idf("gp_out[%d]", i), PORT_OUT,
                     get_port(CycloneV::HPS_MPU_GENERAL_PURPOSE, x, y, -1, CycloneV::GP_OUT, i));
     }
 }
diff --git a/mistral/io.cc b/mistral/io.cc
index c8d0238dcf..6690fc16e2 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -27,8 +27,8 @@ void Arch::create_gpio(int x, int y)
 {
     for (int z = 0; z < 4; z++) {
         // Notional pad wire
-        WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
-        BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
+        WireId pad = add_wire(x, y, idf("PAD[%d]", z));
+        BelId bel = add_bel(x, y, idf("IO[%d]", z), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
         if (has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
             // FIXME: is the port index of zero always correct?
diff --git a/mistral/lab.cc b/mistral/lab.cc
index 4b66ed0c8a..d65ccf537f 100644
--- a/mistral/lab.cc
+++ b/mistral/lab.cc
@@ -37,10 +37,10 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
     // Create the control set and E/F selection - which is per pair of FF
     for (int i = 0; i < 2; i++) {
         // Wires
-        alm.sel_clk[i] = arch->add_wire(x, y, arch->id(stringf("CLK%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_ena[i] = arch->add_wire(x, y, arch->id(stringf("ENA%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z)));
-        alm.sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z)));
+        alm.sel_clk[i] = arch->add_wire(x, y, arch->idf("CLK%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_ena[i] = arch->add_wire(x, y, arch->idf("ENA%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_aclr[i] = arch->add_wire(x, y, arch->idf("ACLR%c[%d]", i ? 'B' : 'T', z));
+        alm.sel_ef[i] = arch->add_wire(x, y, arch->idf("%cEF[%d]", i ? 'B' : 'T', z));
         // Muxes - three CLK/ENA per LAB, two ACLR
         for (int j = 0; j < 3; j++) {
             arch->add_pip(lab.clk_wires[j], alm.sel_clk[i]);
@@ -72,20 +72,20 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
             }
         } else {
             // Output from last combinational unit
-            carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1)));
-            share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1)));
+            carry_in = arch->add_wire(x, y, arch->idf("CARRY[%d]", (z * 2 + i) - 1));
+            share_in = arch->add_wire(x, y, arch->idf("SHARE[%d]", (z * 2 + i) - 1));
         }
 
         if (z == 9 && i == 1) {
             carry_out = arch->add_wire(x, y, id_CO);
             share_out = arch->add_wire(x, y, id_SHAREOUT);
         } else {
-            carry_out = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", z * 2 + i)));
-            share_out = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", z * 2 + i)));
+            carry_out = arch->add_wire(x, y, arch->idf("CARRY[%d]", z * 2 + i));
+            share_out = arch->add_wire(x, y, arch->idf("SHARE[%d]", z * 2 + i));
         }
 
-        BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_COMB%d", z, i)),
-                                  lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB);
+        BelId bel =
+                arch->add_bel(x, y, arch->idf("ALM%d_COMB%d", z, i), lab.is_mlab ? id_MISTRAL_MCOMB : id_MISTRAL_COMB);
         // LUT/MUX inputs
         arch->add_bel_pin(bel, id_A, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::A));
         arch->add_bel_pin(bel, id_B, PORT_IN, arch->get_port(block_type, x, y, z, CycloneV::B));
@@ -101,7 +101,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
         arch->add_bel_pin(bel, id_CO, PORT_OUT, carry_out);
         arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out);
         // Combinational output
-        alm.comb_out[i] = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i)));
+        alm.comb_out[i] = arch->add_wire(x, y, arch->idf("COMBOUT[%d]", z * 2 + i));
         arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, alm.comb_out[i]);
         if (lab.is_mlab) {
             // Write address - shared between all ALMs in a LAB
@@ -128,11 +128,11 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
 
     for (int i = 0; i < 4; i++) {
         // FF input, selected by *PKREG*
-        alm.ff_in[i] = arch->add_wire(x, y, arch->id(stringf("FFIN[%d]", (z * 4) + i)));
+        alm.ff_in[i] = arch->add_wire(x, y, arch->idf("FFIN[%d]", (z * 4) + i));
         arch->add_pip(alm.comb_out[i / 2], alm.ff_in[i]);
         arch->add_pip(alm.sel_ef[i / 2], alm.ff_in[i]);
         // FF bel
-        BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_FF%d", z, i)), id_MISTRAL_FF);
+        BelId bel = arch->add_bel(x, y, arch->idf("ALM%d_FF%d", z, i), id_MISTRAL_FF);
         arch->add_bel_pin(bel, id_CLK, PORT_IN, alm.sel_clk[i / 2]);
         arch->add_bel_pin(bel, id_ENA, PORT_IN, alm.sel_ena[i / 2]);
         arch->add_bel_pin(bel, id_ACLR, PORT_IN, alm.sel_aclr[i / 2]);
@@ -142,7 +142,7 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
         arch->add_bel_pin(bel, id_SDATA, PORT_IN, alm.sel_ef[i / 2]);
 
         // FF output
-        alm.ff_out[i] = arch->add_wire(x, y, arch->id(stringf("FFOUT[%d]", (z * 4) + i)));
+        alm.ff_out[i] = arch->add_wire(x, y, arch->idf("FFOUT[%d]", (z * 4) + i));
         arch->add_bel_pin(bel, id_Q, PORT_OUT, alm.ff_out[i]);
         // Output mux (*DFF*)
         WireId out = arch->get_port(block_type, x, y, z, outputs[i]);
@@ -182,7 +182,7 @@ void Arch::create_lab(int x, int y, bool is_mlab)
     // Clocks - hardcode to CLKA choices, as both CLKA and CLKB coming from general routing causes unexpected
     // permutations
     for (int i = 0; i < 3; i++) {
-        lab.clk_wires[i] = add_wire(x, y, id(stringf("CLK%d", i)));
+        lab.clk_wires[i] = add_wire(x, y, idf("CLK%d", i));
         add_pip(get_port(block_type, x, y, -1, CycloneV::CLKIN, 0), lab.clk_wires[i]);  // dedicated routing
         add_pip(get_port(block_type, x, y, -1, CycloneV::DATAIN, 0), lab.clk_wires[i]); // general routing
     }
@@ -278,7 +278,7 @@ void Arch::assign_comb_info(CellInfo *cell) const
         cell->combInfo.lut_input_count = 5;
         cell->combInfo.lut_bits_count = 32;
         for (int i = 0; i < 5; i++)
-            cell->combInfo.lut_in[i] = cell->getPort(id(stringf("B1ADDR[%d]", i)));
+            cell->combInfo.lut_in[i] = cell->getPort(idf("B1ADDR[%d]", i));
         auto key = get_mlab_key(cell);
         cell->combInfo.mlab_group = mlab_groups(key);
         cell->combInfo.comb_out = cell->getPort(id_B1DATA);
@@ -797,8 +797,8 @@ static void assign_mlab_inputs(Context *ctx, CellInfo *cell, int lut)
 
     std::array<IdString, 6> raddr_pins{id_A, id_B, id_C, id_D, id_F0};
     for (int i = 0; i < 5; i++) {
-        cell->pin_data[ctx->id(stringf("A1ADDR[%d]", i))].bel_pins = {ctx->id(stringf("WA%d", i))};
-        cell->pin_data[ctx->id(stringf("B1ADDR[%d]", i))].bel_pins = {raddr_pins.at(i)};
+        cell->pin_data[ctx->idf("A1ADDR[%d]", i)].bel_pins = {ctx->idf("WA%d", i)};
+        cell->pin_data[ctx->idf("B1ADDR[%d]", i)].bel_pins = {raddr_pins.at(i)};
     }
 }
 
@@ -918,7 +918,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
             CellInfo *ff = ffs[i * 2 + j];
             if (!ff || !ff->ffInfo.datain || alm_data.l6_mode)
                 continue;
-            CellInfo *rt_lut = createCell(id(stringf("%s$ROUTETHRU", nameOf(ff))), id_MISTRAL_BUF);
+            CellInfo *rt_lut = createCell(idf("%s$ROUTETHRU", nameOf(ff)), id_MISTRAL_BUF);
             rt_lut->addInput(id_A);
             rt_lut->addOutput(id_Q);
             // Disconnect the original data input to the FF, and connect it to the route-thru LUT instead
diff --git a/mistral/m10k.cc b/mistral/m10k.cc
index 4da1204fd8..df44c66399 100644
--- a/mistral/m10k.cc
+++ b/mistral/m10k.cc
@@ -27,34 +27,28 @@ void Arch::create_m10k(int x, int y)
     add_bel_pin(bel, id_ADDRSTALLA, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
     add_bel_pin(bel, id_ADDRSTALLB, PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
     for (int z = 0; z < 2; z++) {
-        add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
+        add_bel_pin(bel, idf("BYTEENABLEA[%d]", z), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
-        add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
+        add_bel_pin(bel, idf("BYTEENABLEB[%d]", z), PORT_IN,
                     get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
-        add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
-        add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
-        add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
-        add_bel_pin(bel, id(stringf("CLKIN[%d]", z + 6)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
+        add_bel_pin(bel, idf("ACLR[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
+        add_bel_pin(bel, idf("RDEN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
+        add_bel_pin(bel, idf("WREN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
+        add_bel_pin(bel, idf("CLKIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
+        add_bel_pin(bel, idf("CLKIN[%d]", z + 6), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z + 6));
     }
     for (int z = 0; z < 4; z++) {
-        add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
+        add_bel_pin(bel, idf("ENABLE[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
     }
     for (int z = 0; z < 12; z++) {
-        add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
-        add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
+        add_bel_pin(bel, idf("ADDRA[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
+        add_bel_pin(bel, idf("ADDRB[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
     }
     for (int z = 0; z < 20; z++) {
-        add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
-        add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
-        add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
-        add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT,
-                    get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
+        add_bel_pin(bel, idf("DATAAIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
+        add_bel_pin(bel, idf("DATABIN[%d]", z), PORT_IN, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
+        add_bel_pin(bel, idf("DATAAOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
+        add_bel_pin(bel, idf("DATABOUT[%d]", z), PORT_OUT, get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
     }
 }
 
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 27ad3c92bd..709479a294 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -417,10 +417,8 @@ struct MistralPacker
                 bit_offset = 1;
             }
             for (int bit = bit_offset; bit < abits; bit++) {
-                ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {
-                        ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
-                ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {
-                        ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
+                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset)};
+                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset)};
             }
 
             // Data lines
@@ -451,13 +449,12 @@ struct MistralPacker
             }
             for (int bit = 0; bit < dbits; bit++) {
                 for (int offset : offsets) {
-                    ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
-                            ctx->id(stringf("DATAAIN[%d]", bit + offset)));
+                    ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset));
                 }
             }
 
             for (int bit = 0; bit < dbits; bit++) {
-                ci->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
+                ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit)};
             }
         }
     }
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 9679c3fbed..b2ae22ce37 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -125,12 +125,12 @@ Arch::Arch(ArchArgs args) : args(args)
     }
 
     for (int i = 0; i < chip_info->width; i++) {
-        IdString x_id = id(stringf("X%d", i));
+        IdString x_id = idf("X%d", i);
         x_ids.push_back(x_id);
         id_to_x[x_id] = i;
     }
     for (int i = 0; i < chip_info->height; i++) {
-        IdString y_id = id(stringf("Y%d", i));
+        IdString y_id = idf("Y%d", i);
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
@@ -377,7 +377,7 @@ IdStringList Arch::getPipName(PipId pip) const
 {
     NPNR_ASSERT(pip != PipId());
     std::array<IdString, 5> ids{x_ids.at(pip.tile % chip_info->width), y_ids.at(pip.tile / chip_info->width),
-                                id(stringf("%d", pip.index)), IdString(loc_data(pip).wires[pip_data(pip).to_wire].name),
+                                idf("%d", pip.index), IdString(loc_data(pip).wires[pip_data(pip).to_wire].name),
                                 IdString(loc_data(pip).wires[pip_data(pip).from_wire].name)};
     return IdStringList(ids);
 }
@@ -784,7 +784,7 @@ bool Arch::route()
 
 CellPinMux Arch::get_cell_pinmux(const CellInfo *cell, IdString pin) const
 {
-    IdString param = id(stringf("%sMUX", pin.c_str(this)));
+    IdString param = idf("%sMUX", pin.c_str(this));
     auto fnd_param = cell->params.find(param);
     if (fnd_param == cell->params.end())
         return PINMUX_SIG;
@@ -805,7 +805,7 @@ CellPinMux Arch::get_cell_pinmux(const CellInfo *cell, IdString pin) const
 
 void Arch::set_cell_pinmux(CellInfo *cell, IdString pin, CellPinMux state)
 {
-    IdString param = id(stringf("%sMUX", pin.c_str(this)));
+    IdString param = idf("%sMUX", pin.c_str(this));
     switch (state) {
     case PINMUX_SIG:
         cell->params.erase(param);
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index de03fb8226..48a3d2591b 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -595,7 +595,7 @@ struct NexusFasmWriter
         if (wid > 0) {
             push(stringf("IP_EBR_WID%d", wid));
             for (int i = 0; i < 64; i++) {
-                IdString param = ctx->id(stringf("INITVAL_%02X", i));
+                IdString param = ctx->idf("INITVAL_%02X", i);
                 if (!cell->params.count(param))
                     continue;
                 auto &prop = cell->params.at(param);
@@ -906,7 +906,7 @@ struct NexusFasmWriter
             l.x = 1;
         push(stringf("IP_LRAM_CORE_R%dC%d", l.y, l.x));
         for (int i = 0; i < 128; i++) {
-            IdString param = ctx->id(stringf("INITVAL_%02X", i));
+            IdString param = ctx->idf("INITVAL_%02X", i);
             if (!cell->params.count(param))
                 continue;
             auto &prop = cell->params.at(param);
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 15752171e4..0aa611440a 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -316,8 +316,8 @@ struct NexusPacker
             return z;
         }
 
-        NetInfo *new_net = ctx->createNet(ctx->id(stringf("$CONST_%s_NET_", type.c_str(ctx))));
-        CellInfo *new_cell = ctx->createCell(ctx->id(stringf("$CONST_%s_DRV_", type.c_str(ctx))), type);
+        NetInfo *new_net = ctx->createNet(ctx->idf("$CONST_%s_NET_", type.c_str(ctx)));
+        CellInfo *new_cell = ctx->createCell(ctx->idf("$CONST_%s_DRV_", type.c_str(ctx)), type);
         new_cell->addOutput(id_Z);
         new_cell->connectPort(id_Z, new_net);
         return new_net;
@@ -823,10 +823,10 @@ struct NexusPacker
                             Tpred pred)
     {
         // Create the buffered net
-        NetInfo *buffered_net = ctx->createNet(ctx->id(stringf("%s$%s", ctx->nameOf(net), name_postfix.c_str())));
+        NetInfo *buffered_net = ctx->createNet(ctx->idf("%s$%s", ctx->nameOf(net), name_postfix.c_str()));
         // Create the buffer cell
-        CellInfo *buffer = ctx->createCell(
-                ctx->id(stringf("%s$drv_%s", ctx->nameOf(buffered_net), ctx->nameOf(buffer_type))), buffer_type);
+        CellInfo *buffer = ctx->createCell(ctx->idf("%s$drv_%s", ctx->nameOf(buffered_net), ctx->nameOf(buffer_type)),
+                                           buffer_type);
         buffer->addInput(i);
         buffer->addOutput(o);
         // Drive the buffered net with the buffer
@@ -915,9 +915,9 @@ struct NexusPacker
     }
 
     // Get a bus port name
-    IdString bus(const std::string &base, int i) { return ctx->id(stringf("%s[%d]", base.c_str(), i)); }
+    IdString bus(const std::string &base, int i) { return ctx->idf("%s[%d]", base.c_str(), i); }
 
-    IdString bus_flat(const std::string &base, int i) { return ctx->id(stringf("%s%d", base.c_str(), i)); }
+    IdString bus_flat(const std::string &base, int i) { return ctx->idf("%s%d", base.c_str(), i); }
 
     // Pack a LUTRAM into COMB and RAMW cells
     void pack_lutram()
@@ -939,11 +939,10 @@ struct NexusPacker
 
         for (CellInfo *ci : lutrams) {
             // Create constituent cells
-            CellInfo *ramw = ctx->createCell(ctx->id(stringf("%s$lutram_ramw$", ctx->nameOf(ci))), id_RAMW);
+            CellInfo *ramw = ctx->createCell(ctx->idf("%s$lutram_ramw$", ctx->nameOf(ci)), id_RAMW);
             std::vector<CellInfo *> combs;
             for (int i = 0; i < 4; i++)
-                combs.push_back(
-                        ctx->createCell(ctx->id(stringf("%s$lutram_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB));
+                combs.push_back(ctx->createCell(ctx->idf("%s$lutram_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB));
             // Rewiring - external WCK and WRE
             ci->movePortTo(id_WCK, ramw, id_CLK);
             ci->movePortTo(id_WRE, ramw, id_LSR);
@@ -951,8 +950,8 @@ struct NexusPacker
             // Internal WCK and WRE signals
             ramw->addOutput(id_WCKO);
             ramw->addOutput(id_WREO);
-            NetInfo *int_wck = ctx->createNet(ctx->id(stringf("%s$lutram_wck$", ctx->nameOf(ci))));
-            NetInfo *int_wre = ctx->createNet(ctx->id(stringf("%s$lutram_wre$", ctx->nameOf(ci))));
+            NetInfo *int_wck = ctx->createNet(ctx->idf("%s$lutram_wck$", ctx->nameOf(ci)));
+            NetInfo *int_wre = ctx->createNet(ctx->idf("%s$lutram_wre$", ctx->nameOf(ci)));
             ramw->connectPort(id_WCKO, int_wck);
             ramw->connectPort(id_WREO, int_wre);
 
@@ -977,7 +976,7 @@ struct NexusPacker
                     ci->disconnectPort(bus("RAD", i));
                 }
                 // Write address - internal
-                NetInfo *int_wad = ctx->createNet(ctx->id(stringf("%s$lutram_wad[%d]$", ctx->nameOf(ci), i)));
+                NetInfo *int_wad = ctx->createNet(ctx->idf("%s$lutram_wad[%d]$", ctx->nameOf(ci), i));
                 ramw->addOutput(bus_flat("WADO", i));
                 ramw->connectPort(bus_flat("WADO", i), int_wad);
                 for (int j = 0; j < 4; j++) {
@@ -985,7 +984,7 @@ struct NexusPacker
                     combs[j]->connectPort(bus_flat("WAD", i), int_wad);
                 }
                 // Write data - internal
-                NetInfo *int_wd = ctx->createNet(ctx->id(stringf("%s$lutram_wd[%d]$", ctx->nameOf(ci), i)));
+                NetInfo *int_wd = ctx->createNet(ctx->idf("%s$lutram_wd[%d]$", ctx->nameOf(ci), i));
                 ramw->addOutput(bus_flat("WDO", i));
                 ramw->connectPort(bus_flat("WDO", i), int_wd);
                 combs[i]->addInput(id_WDI);
@@ -1256,8 +1255,7 @@ struct NexusPacker
         for (CellInfo *ci : widefns) {
             std::vector<CellInfo *> combs;
             for (int i = 0; i < 2; i++)
-                combs.push_back(
-                        ctx->createCell(ctx->id(stringf("%s$widefn_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB));
+                combs.push_back(ctx->createCell(ctx->idf("%s$widefn_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB));
 
             for (int i = 0; i < 2; i++) {
                 ci->movePortTo(bus_flat("A", i), combs[i], id_A);
@@ -1269,7 +1267,7 @@ struct NexusPacker
             ci->movePortTo(id_SEL, combs[0], id_SEL);
             ci->movePortTo(id_Z, combs[0], id_OFX);
 
-            NetInfo *f1 = ctx->createNet(ctx->id(stringf("%s$widefn_f1$", ctx->nameOf(ci))));
+            NetInfo *f1 = ctx->createNet(ctx->idf("%s$widefn_f1$", ctx->nameOf(ci)));
             combs[0]->addInput(id_F1);
             combs[1]->addOutput(id_F);
             combs[1]->connectPort(id_F, f1);
@@ -1313,8 +1311,7 @@ struct NexusPacker
                 // Split the carry into two COMB cells
                 std::vector<CellInfo *> combs;
                 for (int i = 0; i < 2; i++)
-                    combs.push_back(
-                            ctx->createCell(ctx->id(stringf("%s$ccu2_comb[%d]$", ctx->nameOf(ci), i)), id_OXIDE_COMB));
+                    combs.push_back(ctx->createCell(ctx->idf("%s$ccu2_comb[%d]$", ctx->nameOf(ci), i), id_OXIDE_COMB));
                 // Rewire LUT ports
                 for (int i = 0; i < 2; i++) {
                     combs[i]->params[id_MODE] = std::string("CCU2");
@@ -1336,7 +1333,7 @@ struct NexusPacker
                 combs[1]->params[id_INIT] = ctx->parse_lattice_param_from_cell(ci, id_INIT1, 16, 0);
 
                 // Internal carry net between the two split COMB cells
-                NetInfo *int_cy = ctx->createNet(ctx->id(stringf("%s$widefn_int_cy$", ctx->nameOf(ci))));
+                NetInfo *int_cy = ctx->createNet(ctx->idf("%s$widefn_int_cy$", ctx->nameOf(ci)));
                 combs[0]->addOutput(id_FCO);
                 combs[1]->addInput(id_FCI);
                 combs[0]->connectPort(id_FCO, int_cy);
@@ -1550,7 +1547,7 @@ struct NexusPacker
     // Create a DSP cell
     CellInfo *create_dsp_cell(IdString base_name, IdString type, CellInfo *constr_base, int dx, int dz)
     {
-        IdString name = ctx->id(stringf("%s/%s_x%d_z%d", ctx->nameOf(base_name), ctx->nameOf(type), dx, dz));
+        IdString name = ctx->idf("%s/%s_x%d_z%d", ctx->nameOf(base_name), ctx->nameOf(type), dx, dz);
         CellInfo *cell = ctx->createCell(name, type);
         if (constr_base != nullptr) {
             // We might be constraining against an already-constrained cell
@@ -1739,10 +1736,10 @@ struct NexusPacker
 
                 if (mt.wide > 0) {
                     // Dot-product mode special case
-                    ci->copyPortBusTo(ctx->id(stringf("B%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, preadd9[i],
-                                      id_B, 0, false, 9);
-                    ci->copyPortBusTo(ctx->id(stringf("A%d", (i * 9) / mt.wide)), (i * 9) % mt.wide, true, mult9[i],
-                                      id_A, 0, false, 9);
+                    ci->copyPortBusTo(ctx->idf("B%d", (i * 9) / mt.wide), (i * 9) % mt.wide, true, preadd9[i], id_B, 0,
+                                      false, 9);
+                    ci->copyPortBusTo(ctx->idf("A%d", (i * 9) / mt.wide), (i * 9) % mt.wide, true, mult9[i], id_A, 0,
+                                      false, 9);
                     ci->copyPortTo(id_CLK, mult9[i], id_CLK);
                     ci->copyPortTo((i > 1) ? id_CEA2A3 : id_CEA0A1, mult9[i], id_CEA);
                     ci->copyPortTo((i > 1) ? id_RSTA2A3 : id_RSTA0A1, mult9[i], id_RSTA);
@@ -1750,8 +1747,8 @@ struct NexusPacker
                     ci->copyPortTo((i > 1) ? id_CEB2B3 : id_CEB0B1, preadd9[i], id_CEB);
                     ci->copyPortTo((i > 1) ? id_RSTB2B3 : id_RSTB0B1, preadd9[i], id_RSTB);
                     // Copy register configuration
-                    copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), mult9[i], id_REGBYPSA1);
-                    copy_param(ci, ctx->id(stringf("REGINPUTAB%d", i)), preadd9[i], id_REGBYPSBR0);
+                    copy_param(ci, ctx->idf("REGINPUTAB%d", i), mult9[i], id_REGBYPSA1);
+                    copy_param(ci, ctx->idf("REGINPUTAB%d", i), preadd9[i], id_REGBYPSBR0);
                 } else {
                     // B input split across pre-adders
                     ci->copyPortBusTo(id_B, b_start, true, preadd9[i], id_B, 0, false, 9);

From f7354d092ddcb6020f1fc0a23267920884cf8641 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 10 Aug 2022 15:47:22 +0100
Subject: [PATCH 171/712] nexus: Add timing data for LRAM

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.cc      | 16 ++++++++++++++++
 nexus/constids.inc |  1 +
 nexus/pack.cc      | 13 +++++++++++++
 3 files changed, 30 insertions(+)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index b2ae22ce37..4a956fae54 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -543,6 +543,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_CLOCK_INPUT;
         clockInfoCount = 1;
         return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
+    } else if (cell->type == id_LRAM_CORE) {
+        if (port.in(id_OPCGLDCK, id_OPCGLOADCLK, id_SCANCLK, id_SCANRST, id_TBISTN, id_INITN, id_STDBYN, id_IGN,
+                    id_DPS))
+            return TMG_IGNORE;
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        clockInfoCount = 1;
+        return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
     } else if (cell->type == id_MULT18_CORE || cell->type == id_MULT18X36_CORE || cell->type == id_MULT36_CORE) {
         return (cell->ports.at(port).type == PORT_IN) ? TMG_COMB_INPUT : TMG_COMB_OUTPUT;
     } else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
@@ -602,6 +610,14 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         }
         // Lookup edge based on inversion
         info.edge = (get_cell_pinmux(cell, info.clock_port) == PINMUX_INV) ? FALLING_EDGE : RISING_EDGE;
+    } else if (cell->type == id_LRAM_CORE) {
+        info.clock_port = id_CLK;
+        if (cell->ports.at(port).type == PORT_IN) {
+            lookup_cell_setuphold(cell->tmg_index, lookup_port(port), id_CLK, info.setup, info.hold);
+        } else {
+            NPNR_ASSERT(lookup_cell_delay(cell->tmg_index, id_CLK, lookup_port(port), info.clockToQ));
+        }
+        info.edge = (get_cell_pinmux(cell, info.clock_port) == PINMUX_INV) ? FALLING_EDGE : RISING_EDGE;
     } else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
         info.clock_port = id_CLK;
         if (cell->ports.at(port).type == PORT_IN) {
diff --git a/nexus/constids.inc b/nexus/constids.inc
index bdf8867b50..8731fad7b3 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -465,6 +465,7 @@ X(TBISTN)
 X(WE)
 X(CEOUTA)
 X(CEOUTB)
+X(OPCGLOADCLK)
 
 X(MULTADDSUB9X9WIDE)
 X(MULTADDSUB18X18WIDE)
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 0aa611440a..e727364d6b 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2614,6 +2614,19 @@ void Arch::assignCellInfo(CellInfo *cell)
 
         cell->tmg_index = get_cell_timing_idx(id(str_or_default(cell->params, id_MODE, "DP16K") + "_MODE"));
         NPNR_ASSERT(cell->tmg_index != -1);
+    } else if (cell->type == id_LRAM_CORE) {
+        // Strip off bus indices to get the timing ports
+        // as timing is generally word-wide
+        for (const auto &port : cell->ports) {
+            const std::string &name = port.first.str(this);
+            size_t idx_end = name.find_last_not_of("0123456789");
+            std::string base = name.substr(0, idx_end + 1);
+            // Strip off bus index
+            cell->tmg_portmap[port.first] = id(base);
+        }
+
+        cell->tmg_index = get_cell_timing_idx(id_LRAM_CORE);
+        NPNR_ASSERT(cell->tmg_index != -1);
     } else if (is_dsp_cell(cell)) {
         // Strip off bus indices to get the timing ports
         // as timing is generally word-wide

From c60fb94b6c45ca74632e972995555170063b3a03 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 10 Aug 2022 18:58:22 +0100
Subject: [PATCH 172/712] refactor: Use IdString::in instead of || chains

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.cc        | 76 +++++++++++++++++++--------------------------
 ecp5/arch.h         |  2 +-
 ecp5/arch_place.cc  |  5 ++-
 ecp5/bitstream.cc   | 13 +++-----
 ecp5/cells.cc       |  2 +-
 ecp5/cells.h        |  6 ++--
 ecp5/gfx.cc         | 45 ++++++++++-----------------
 ecp5/globals.cc     | 22 ++++++-------
 ecp5/pack.cc        | 41 +++++++++++-------------
 gowin/cells.cc      |  5 ++-
 gowin/gfx.cc        |  2 +-
 gowin/globals.cc    |  3 +-
 ice40/arch.cc       | 36 ++++++++++-----------
 ice40/arch_place.cc |  2 +-
 ice40/bitstream.cc  |  3 +-
 ice40/cells.cc      |  8 ++---
 ice40/cells.h       | 20 +++++-------
 ice40/pack.cc       |  8 ++---
 mistral/globals.cc  |  5 +--
 nexus/arch.cc       | 37 ++++++++++------------
 nexus/arch.h        |  2 +-
 nexus/fasm.cc       |  7 ++---
 nexus/global.cc     |  2 +-
 nexus/pack.cc       |  4 +--
 24 files changed, 153 insertions(+), 203 deletions(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 0b763612de..f031c9044e 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -557,8 +557,7 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB ||
-        (src_pin == id_F && dst_pin == id_DI))
+    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin.in(id_FXA, id_FXB) || (src_pin == id_F && dst_pin == id_DI))
         return 0;
     auto driver_loc = getBelLocation(src_bel);
     auto sink_loc = getBelLocation(dst_bel);
@@ -588,7 +587,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
     if (net_info->driver.port == id_FCO && sink.port == id_FCI) {
         budget = 0;
         return true;
-    } else if (sink.port == id_FXA || sink.port == id_FXB) {
+    } else if (sink.port.in(id_FXA, id_FXB)) {
         budget = 0;
         return true;
     } else {
@@ -819,8 +818,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         IdString tmg_type = has_carry ? (((cell->constr_z >> Arch::lc_idx_shift) % 2) ? id_TRELLIS_COMB_CARRY1
                                                                                       : id_TRELLIS_COMB_CARRY0)
                                       : id_TRELLIS_COMB;
-        if (fromPort == id_A || fromPort == id_B || fromPort == id_C || fromPort == id_D || fromPort == id_M ||
-            fromPort == id_F1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI)
+        if (fromPort.in(id_A, id_B, id_C, id_D, id_M, id_F1, id_FXA, id_FXB, id_FCI))
             return get_delay_from_tmg_db(tmg_type, fromPort, toPort, delay);
         else
             return false;
@@ -842,7 +840,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         }
         return false;
     } else if (cell->type == id_DCSC) {
-        if ((fromPort == id_CLK0 || fromPort == id_CLK1) && toPort == id_DCSOUT) {
+        if ((fromPort.in(id_CLK0, id_CLK1)) && toPort == id_DCSOUT) {
             delay = DelayQuad(0);
             return true;
         }
@@ -858,7 +856,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
                 return get_delay_from_tmg_db(cell->multInfo.timing_id, id(std::string("") + fn.front()), id_P, delay);
         }
         return false;
-    } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
+    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
         return false;
     } else {
         return false;
@@ -872,18 +870,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
     if (cell->type == id_TRELLIS_COMB) {
         if (port == id_WCK)
             return TMG_CLOCK_INPUT;
-        if (port == id_A || port == id_B || port == id_C || port == id_D || port == id_FCI || port == id_FXA ||
-            port == id_FXB || port == id_F1)
+        if (port.in(id_A, id_B, id_C, id_D, id_FCI, id_FXA, id_FXB, id_F1))
             return TMG_COMB_INPUT;
         if (port == id_F && disconnected(id_A) && disconnected(id_B) && disconnected(id_C) && disconnected(id_D) &&
             disconnected(id_FCI))
             return TMG_IGNORE; // LUT with no inputs is a constant
-        if (port == id_F || port == id_FCO || port == id_OFX)
+        if (port.in(id_F, id_FCO, id_OFX))
             return TMG_COMB_OUTPUT;
         if (port == id_M)
             return TMG_COMB_INPUT;
-        if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 ||
-            port == id_WRE) {
+        if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) {
             clockInfoCount = 1;
             return TMG_REGISTER_INPUT;
         }
@@ -892,7 +888,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
         if (port == id_CLK)
             return TMG_CLOCK_INPUT;
-        if (port == id_DI || (using_m && (port == id_M)) || port == id_CE || port == id_LSR) {
+        if (port == id_DI || (using_m && (port == id_M)) || port.in(id_CE, id_LSR)) {
             clockInfoCount = 1;
             return TMG_REGISTER_INPUT;
         }
@@ -902,15 +898,13 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         }
         return TMG_IGNORE;
     } else if (cell->type == id_TRELLIS_RAMW) {
-        if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
-            port == id_D0 || port == id_D1)
+        if (port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))
             return TMG_COMB_INPUT;
-        if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 ||
-            port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
+        if (port.in(id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3))
             return TMG_COMB_OUTPUT;
         return TMG_IGNORE;
     } else if (cell->type == id_TRELLIS_IO) {
-        if (port == id_T || port == id_I)
+        if (port.in(id_T, id_I))
             return TMG_ENDPOINT;
         if (port == id_O)
             return TMG_STARTPOINT;
@@ -922,13 +916,13 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_COMB_OUTPUT;
         return TMG_IGNORE;
     } else if (cell->type == id_DCSC) {
-        if (port == id_CLK0 || port == id_CLK1)
+        if (port.in(id_CLK0, id_CLK1))
             return TMG_COMB_INPUT;
         if (port == id_DCSOUT)
             return TMG_COMB_OUTPUT;
         return TMG_IGNORE;
     } else if (cell->type == id_DP16KD) {
-        if (port == id_CLKA || port == id_CLKB)
+        if (port.in(id_CLKA, id_CLKB))
             return TMG_CLOCK_INPUT;
         std::string port_name = port.str(this);
         for (auto c : boost::adaptors::reverse(port_name)) {
@@ -942,10 +936,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         }
         NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
     } else if (cell->type == id_MULT18X18D) {
-        if (port == id_CLK0 || port == id_CLK1 || port == id_CLK2 || port == id_CLK3)
+        if (port.in(id_CLK0, id_CLK1, id_CLK2, id_CLK3))
             return TMG_CLOCK_INPUT;
-        if (port == id_CE0 || port == id_CE1 || port == id_CE2 || port == id_CE3 || port == id_RST0 ||
-            port == id_RST1 || port == id_RST2 || port == id_RST3 || port == id_SIGNEDA || port == id_SIGNEDB) {
+        if (port.in(id_CE0, id_CE1, id_CE2, id_CE3, id_RST0, id_RST1, id_RST2, id_RST3, id_SIGNEDA, id_SIGNEDB)) {
             if (cell->multInfo.is_clocked) {
                 clockInfoCount = 1;
                 return TMG_REGISTER_INPUT;
@@ -977,9 +970,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         return TMG_IGNORE; // FIXME
     } else if (cell->type == id_EHXPLLL) {
         return TMG_IGNORE;
-    } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) {
-        if (port == id_CH0_FF_TXI_CLK || port == id_CH0_FF_RXI_CLK || port == id_CH1_FF_TXI_CLK ||
-            port == id_CH1_FF_RXI_CLK)
+    } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
+        if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
             return TMG_CLOCK_INPUT;
         std::string prefix = port.str(this).substr(0, 9);
         if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
@@ -987,18 +979,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
         }
         return TMG_IGNORE;
-    } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
-        if (port == id_CLK || port == id_ECLK) {
+    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
+        if (port.in(id_CLK, id_ECLK)) {
             return TMG_CLOCK_INPUT;
-        } else if (port == id_IOLDO || port == id_IOLDOI || port == id_IOLDOD || port == id_IOLTO || port == id_PADDI ||
-                   port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
+        } else if (port.in(id_IOLDO, id_IOLDOI, id_IOLDOD, id_IOLTO, id_PADDI, id_DQSR90, id_DQSW, id_DQSW270)) {
             return TMG_IGNORE;
         } else {
             clockInfoCount = 1;
             return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
         }
-    } else if (cell->type == id_DTR || cell->type == id_USRMCLK || cell->type == id_SEDGA || cell->type == id_GSR ||
-               cell->type == id_JTAGG) {
+    } else if (cell->type.in(id_DTR, id_USRMCLK, id_SEDGA, id_GSR, id_JTAGG)) {
         return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
     } else if (cell->type == id_OSCG) {
         if (port == id_OSC)
@@ -1008,22 +998,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
     } else if (cell->type == id_CLKDIVF) {
         if (port == id_CLKI)
             return TMG_CLOCK_INPUT;
-        else if (port == id_RST || port == id_ALIGNWD)
+        else if (port.in(id_RST, id_ALIGNWD))
             return TMG_ENDPOINT;
         else if (port == id_CDIVX)
             return TMG_GEN_CLOCK;
         else
             NPNR_ASSERT_FALSE("bad clkdiv port");
     } else if (cell->type == id_DQSBUFM) {
-        if (port == id_READ0 || port == id_READ1) {
+        if (port.in(id_READ0, id_READ1)) {
             clockInfoCount = 1;
             return TMG_REGISTER_INPUT;
         } else if (port == id_DATAVALID) {
             clockInfoCount = 1;
             return TMG_REGISTER_OUTPUT;
-        } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) {
+        } else if (port.in(id_SCLK, id_ECLK, id_DQSI)) {
             return TMG_CLOCK_INPUT;
-        } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
+        } else if (port.in(id_DQSR90, id_DQSW, id_DQSW270)) {
             return TMG_GEN_CLOCK;
         }
         return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
@@ -1054,8 +1044,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     info.hold = DelayPair(0);
     info.clockToQ = DelayQuad(0);
     if (cell->type == id_TRELLIS_COMB) {
-        if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 ||
-            port == id_WRE) {
+        if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) {
             if (port == id_WD)
                 port = id_WD0;
             info.edge = (cell->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV) ? FALLING_EDGE : RISING_EDGE;
@@ -1064,7 +1053,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         }
     } else if (cell->type == id_TRELLIS_FF) {
         bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
-        if (port == id_DI || port == id_CE || port == id_LSR || (using_m && port == id_M)) {
+        if (port.in(id_DI, id_CE, id_LSR) || (using_m && port == id_M)) {
             if (port == id_DI)
                 port = id_DI0;
             if (port == id_M)
@@ -1098,9 +1087,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         if (cell->ramInfo.is_pdp) {
             bool is_output = cell->ports.at(port).type == PORT_OUT;
             // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain
-            if (is_output || port == id_OCEB || port == id_CEB || port == id_ADB5 || port == id_ADB6 ||
-                port == id_ADB7 || port == id_ADB8 || port == id_ADB9 || port == id_ADB10 || port == id_ADB11 ||
-                port == id_ADB12 || port == id_ADB13)
+            if (is_output || port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11,
+                                     id_ADB12, id_ADB13))
                 info.clock_port = id_CLKB;
             else
                 info.clock_port = id_CLKA;
@@ -1133,7 +1121,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.setup = DelayPair(getDelayFromNS(1));
             info.hold = DelayPair(getDelayFromNS(0));
         }
-    } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
+    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
         info.clock_port = id_CLK;
         info.edge = RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
@@ -1147,7 +1135,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         info.edge = RISING_EDGE;
         if (port == id_DATAVALID) {
             info.clockToQ = DelayQuad(getDelayFromNS(0.2));
-        } else if (port == id_READ0 || port == id_READ1) {
+        } else if (port.in(id_READ0, id_READ1)) {
             info.setup = DelayPair(getDelayFromNS(0.5));
             info.hold = DelayPair(getDelayFromNS(-0.4));
         } else {
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 3d95fc9b18..12f043b786 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -565,7 +565,7 @@ struct Arch : BaseArch<ArchRanges>
     void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
     {
         CellInfo *act_cell = (old_cell == nullptr) ? new_cell : old_cell;
-        if (act_cell->type == id_TRELLIS_FF || act_cell->type == id_TRELLIS_COMB || act_cell->type == id_TRELLIS_RAMW) {
+        if (act_cell->type.in(id_TRELLIS_FF, id_TRELLIS_COMB, id_TRELLIS_RAMW)) {
             LogicTileStatus *lts = tile_status.at(tile_index(bel)).lts;
             NPNR_ASSERT(lts != nullptr);
             int z = loc_info(bel)->bel_data[bel.index].z;
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index afe9aca0d7..fed9c055d3 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -187,7 +187,7 @@ bool Arch::isBelLocationValid(BelId bel) const
         CellInfo *cell = getBoundBelCell(bel);
         if (cell == nullptr) {
             return true;
-        } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) {
+        } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
             return args.type != ArchArgs::LFE5U_25F && args.type != ArchArgs::LFE5U_45F &&
                    args.type != ArchArgs::LFE5U_85F;
         } else {
@@ -203,8 +203,7 @@ void Arch::setup_wire_locations()
         CellInfo *ci = cell.second.get();
         if (ci->bel == BelId())
             continue;
-        if (ci->type == id_MULT18X18D || ci->type == id_DCUA || ci->type == id_DDRDLL || ci->type == id_DQSBUFM ||
-            ci->type == id_EHXPLLL) {
+        if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
             for (auto &port : ci->ports) {
                 if (port.second.net == nullptr)
                     continue;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 3c01fe71d3..37883bdad6 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -1110,25 +1110,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
             // Tie signals as appropriate
             for (auto port : ci->ports) {
-                if (ci->ramInfo.is_pdp && (port.first == id_WEA || port.first == id_WEB || port.first == id_ADA4))
+                if (ci->ramInfo.is_pdp && (port.first.in(id_WEA, id_WEB, id_ADA4)))
                     continue;
                 if (port.second.net == nullptr && port.second.type == PORT_IN) {
-                    if (port.first == id_CLKA || port.first == id_CLKB || port.first == id_WEA ||
-                        port.first == id_WEB || port.first == id_RSTA || port.first == id_RSTB) {
+                    if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) {
                         // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
                         // If MUX doesn't exist, set to INV to emulate default 0
                         tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
                         if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
                             ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
-                    } else if (port.first == id_CEA || port.first == id_CEB || port.first == id_OCEA ||
-                               port.first == id_OCEB) {
+                    } else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) {
                         // CIB CE. Tie to "1" in CIB
                         // If MUX doesn't exist, set to passthru to emulate default 1
                         tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
                         if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
                             ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
-                    } else if (port.first == id_CSA0 || port.first == id_CSA1 || port.first == id_CSA2 ||
-                               port.first == id_CSB0 || port.first == id_CSB1 || port.first == id_CSB2) {
+                    } else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) {
                         // CIB CE. Tie to "1" in CIB.
                         // If MUX doesn't exist, set to INV to emulate default 0
                         tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
@@ -1392,7 +1389,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                                int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
 
             cc.tilegroups.push_back(tg);
-        } else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) {
+        } else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) {
             Loc pio_loc = ctx->getBelLocation(ci->bel);
             pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4;
             std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc));
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 99f672a605..23d4b855f6 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -133,7 +133,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         new_cell->addInput(id_CLKI);
         new_cell->addOutput(id_CLKO);
         new_cell->addInput(id_CE);
-    } else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
+    } else if (type.in(id_IOLOGIC, id_SIOLOGIC)) {
         new_cell->params[id_MODE] = std::string("NONE");
         new_cell->params[id_GSR] = std::string("DISABLED");
         new_cell->params[id_CLKIMUX] = std::string("CLK");
diff --git a/ecp5/cells.h b/ecp5/cells.h
index 185b19ced3..c79bf8cd21 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -47,15 +47,13 @@ inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty
 
 inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_IDDRX1F || cell->type == id_IDDRX2F || cell->type == id_IDDR71B ||
-           cell->type == id_IDDRX2DQA ||
+    return cell->type.in(id_IDDRX1F, id_IDDRX2F, id_IDDR71B, id_IDDRX2DQA) ||
            (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
             (str_or_default(cell->attrs, id_ioff_dir, "") != "output"));
 }
 inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_ODDRX1F || cell->type == id_ODDRX2F || cell->type == id_ODDR71B ||
-           cell->type == id_ODDRX2DQA || cell->type == id_ODDRX2DQSB || cell->type == id_OSHX2A ||
+    return cell->type.in(id_ODDRX1F, id_ODDRX2F, id_ODDR71B, id_ODDRX2DQA, id_ODDRX2DQSB, id_OSHX2A) ||
            (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
             (str_or_default(cell->attrs, id_ioff_dir, "") != "input"));
 }
diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc
index fe206de02b..b1f3d4dd7a 100644
--- a/ecp5/gfx.cc
+++ b/ecp5/gfx.cc
@@ -84,8 +84,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
                 3 * slice_pitch - 0.0007f;
         el.y2 = el.y1 + wire_distance * 5;
         g.push_back(el);
-    } else if (bel_type == id_TRELLIS_IO || bel_type == id_IOLOGIC || bel_type == id_SIOLOGIC ||
-               bel_type == id_DQSBUFM) {
+    } else if (bel_type.in(id_TRELLIS_IO, id_IOLOGIC, id_SIOLOGIC, id_DQSBUFM)) {
         bool top_bottom = (y == 0 || y == (h - 1));
         if (top_bottom) {
             el.x1 = x + io_cell_h_x1 + (z + 2) * io_cell_gap;
@@ -115,7 +114,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
         el.x2 = x + switchbox_x1 + (z)*0.025 + 0.020;
         el.y2 = y + 0.18;
         g.push_back(el);
-    } else if (bel_type == id_DP16KD || bel_type == id_MULT18X18D || bel_type == id_ALU54B) {
+    } else if (bel_type.in(id_DP16KD, id_MULT18X18D, id_ALU54B)) {
         el.x1 = x + slice_x1;
         el.x2 = x + slice_x2_wide;
         el.y1 = y + slice_y1 - 1 * slice_pitch;
@@ -133,8 +132,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
         el.y1 = y + slice_y2;
         el.y2 = y + 0.25;
         g.push_back(el);
-    } else if (bel_type == id_EXTREFB || bel_type == id_PCSCLKDIV || bel_type == id_DTR || bel_type == id_USRMCLK ||
-               bel_type == id_SEDGA || bel_type == id_GSR || bel_type == id_JTAGG || bel_type == id_OSCG) {
+    } else if (bel_type.in(id_EXTREFB, id_PCSCLKDIV, id_DTR, id_USRMCLK, id_SEDGA, id_GSR, id_JTAGG, id_OSCG)) {
         el.x1 = x + slice_x1;
         el.x2 = x + slice_x2_wide;
         el.y1 = y + slice_y1 + (z)*slice_pitch;
@@ -146,8 +144,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
         el.y1 = y + dll_cell_y1;
         el.y2 = y + dll_cell_y2;
         g.push_back(el);
-    } else if (bel_type == id_DLLDELD || bel_type == id_CLKDIVF || bel_type == id_ECLKSYNCB ||
-               bel_type == id_TRELLIS_ECLKBUF || bel_type == id_ECLKBRIDGECS) {
+    } else if (bel_type.in(id_DLLDELD, id_CLKDIVF, id_ECLKSYNCB, id_TRELLIS_ECLKBUF, id_ECLKBRIDGECS)) {
         el.x1 = x + 0.1 + z * 0.05;
         el.x2 = x + 0.14 + z * 0.05;
         el.y1 = y + 0.475;
@@ -1455,15 +1452,13 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire
                         dst_id - TILE_WIRE_JCE0);
     }
 
-    if ((src_type == id_WIRE_TYPE_H02 || src_type == id_WIRE_TYPE_V00 || src_type == id_WIRE_TYPE_V01 ||
-         src_type == id_WIRE_TYPE_V02) &&
+    if ((src_type.in(id_WIRE_TYPE_H02, id_WIRE_TYPE_V00, id_WIRE_TYPE_V01, id_WIRE_TYPE_V02)) &&
         dst_type == id_WIRE_TYPE_NONE &&
         ((dst_id >= TILE_WIRE_FCO && dst_id <= TILE_WIRE_FCI) ||
          (dst_id >= TILE_WIRE_JCE0 && dst_id <= TILE_WIRE_JQ7))) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
-    if ((dst_type == id_WIRE_TYPE_H02 || dst_type == id_WIRE_TYPE_V00 || dst_type == id_WIRE_TYPE_V01 ||
-         dst_type == id_WIRE_TYPE_V02) &&
+    if ((dst_type.in(id_WIRE_TYPE_H02, id_WIRE_TYPE_V00, id_WIRE_TYPE_V01, id_WIRE_TYPE_V02)) &&
         src_type == id_WIRE_TYPE_NONE &&
         ((src_id >= TILE_WIRE_FCO && src_id <= TILE_WIRE_FCI) ||
          (src_id >= TILE_WIRE_JCE0 && src_id <= TILE_WIRE_JQ7))) {
@@ -1480,33 +1475,27 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire
     }
 
     if (src_type == id_WIRE_TYPE_NONE &&
-        (dst_type == id_WIRE_TYPE_PLL || dst_type == id_WIRE_TYPE_GSR || dst_type == id_WIRE_TYPE_JTAG ||
-         dst_type == id_WIRE_TYPE_OSC || dst_type == id_WIRE_TYPE_SED || dst_type == id_WIRE_TYPE_DTR ||
-         dst_type == id_WIRE_TYPE_EXTREF || dst_type == id_WIRE_TYPE_DCU || dst_type == id_WIRE_TYPE_PCSCLKDIV ||
-         dst_type == id_WIRE_TYPE_DDRDLL || dst_type == id_WIRE_TYPE_CCLK || dst_type == id_WIRE_TYPE_DQS ||
-         dst_type == id_WIRE_TYPE_IOLOGIC || dst_type == id_WIRE_TYPE_SIOLOGIC || dst_type == id_WIRE_TYPE_EBR ||
-         dst_type == id_WIRE_TYPE_MULT18 || dst_type == id_WIRE_TYPE_ALU54) &&
+        (dst_type.in(id_WIRE_TYPE_PLL, id_WIRE_TYPE_GSR, id_WIRE_TYPE_JTAG, id_WIRE_TYPE_OSC, id_WIRE_TYPE_SED,
+                     id_WIRE_TYPE_DTR, id_WIRE_TYPE_EXTREF, id_WIRE_TYPE_DCU, id_WIRE_TYPE_PCSCLKDIV,
+                     id_WIRE_TYPE_DDRDLL, id_WIRE_TYPE_CCLK, id_WIRE_TYPE_DQS, id_WIRE_TYPE_IOLOGIC,
+                     id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_EBR, id_WIRE_TYPE_MULT18, id_WIRE_TYPE_ALU54)) &&
         (src_id >= TILE_WIRE_JCE0 && src_id <= TILE_WIRE_JQ7)) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
     if (dst_type == id_WIRE_TYPE_NONE &&
-        (src_type == id_WIRE_TYPE_PLL || src_type == id_WIRE_TYPE_GSR || src_type == id_WIRE_TYPE_JTAG ||
-         src_type == id_WIRE_TYPE_OSC || src_type == id_WIRE_TYPE_SED || src_type == id_WIRE_TYPE_DTR ||
-         src_type == id_WIRE_TYPE_EXTREF || src_type == id_WIRE_TYPE_DCU || src_type == id_WIRE_TYPE_PCSCLKDIV ||
-         src_type == id_WIRE_TYPE_DDRDLL || src_type == id_WIRE_TYPE_CCLK || src_type == id_WIRE_TYPE_DQS ||
-         src_type == id_WIRE_TYPE_IOLOGIC || src_type == id_WIRE_TYPE_SIOLOGIC || src_type == id_WIRE_TYPE_EBR ||
-         src_type == id_WIRE_TYPE_MULT18 || src_type == id_WIRE_TYPE_ALU54) &&
+        (src_type.in(id_WIRE_TYPE_PLL, id_WIRE_TYPE_GSR, id_WIRE_TYPE_JTAG, id_WIRE_TYPE_OSC, id_WIRE_TYPE_SED,
+                     id_WIRE_TYPE_DTR, id_WIRE_TYPE_EXTREF, id_WIRE_TYPE_DCU, id_WIRE_TYPE_PCSCLKDIV,
+                     id_WIRE_TYPE_DDRDLL, id_WIRE_TYPE_CCLK, id_WIRE_TYPE_DQS, id_WIRE_TYPE_IOLOGIC,
+                     id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_EBR, id_WIRE_TYPE_MULT18, id_WIRE_TYPE_ALU54)) &&
         (dst_id >= TILE_WIRE_JCE0 && dst_id <= TILE_WIRE_JQ7)) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
 
-    if (src_type == id_WIRE_TYPE_NONE &&
-        (dst_type == id_WIRE_TYPE_IOLOGIC || dst_type == id_WIRE_TYPE_SIOLOGIC || dst_type == id_WIRE_TYPE_PIO) &&
+    if (src_type == id_WIRE_TYPE_NONE && (dst_type.in(id_WIRE_TYPE_IOLOGIC, id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_PIO)) &&
         (src_id >= TILE_WIRE_JDIA && src_id <= TILE_WIRE_ECLKD)) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
-    if (dst_type == id_WIRE_TYPE_NONE &&
-        (src_type == id_WIRE_TYPE_IOLOGIC || src_type == id_WIRE_TYPE_SIOLOGIC || src_type == id_WIRE_TYPE_PIO) &&
+    if (dst_type == id_WIRE_TYPE_NONE && (src_type.in(id_WIRE_TYPE_IOLOGIC, id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_PIO)) &&
         (dst_id >= TILE_WIRE_JDIA && dst_id <= TILE_WIRE_ECLKD)) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
@@ -1526,7 +1515,7 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire
          (dst_id >= TILE_WIRE_CLK0 && dst_id <= TILE_WIRE_FCI))) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
-    if ((dst_type == id_WIRE_TYPE_H01 || dst_type == id_WIRE_TYPE_V01) && src_type == id_WIRE_TYPE_G_HPBX) {
+    if ((dst_type.in(id_WIRE_TYPE_H01, id_WIRE_TYPE_V01)) && src_type == id_WIRE_TYPE_G_HPBX) {
         straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
     }
 }
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 7123705a63..6c7ffba07d 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -57,10 +57,10 @@ class Ecp5GlobalRouter
             return true;
         if (user.cell->type == id_TRELLIS_COMB && user.port == id_WCK)
             return true;
-        if (user.cell->type == id_DCUA && (user.port == id_CH0_FF_RXI_CLK || user.port == id_CH1_FF_RXI_CLK ||
-                                           user.port == id_CH0_FF_TXI_CLK || user.port == id_CH1_FF_TXI_CLK))
+        if (user.cell->type == id_DCUA &&
+            (user.port.in(id_CH0_FF_RXI_CLK, id_CH1_FF_RXI_CLK, id_CH0_FF_TXI_CLK, id_CH1_FF_TXI_CLK)))
             return true;
-        if ((user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC) && (user.port == id_CLK))
+        if ((user.cell->type.in(id_IOLOGIC, id_SIOLOGIC)) && (user.port == id_CLK))
             return true;
         return false;
     }
@@ -88,7 +88,7 @@ class Ecp5GlobalRouter
                     clockCount[ni->name]++;
                     if (user.cell->type == id_DCUA)
                         clockCount[ni->name] += 100;
-                    if (user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC)
+                    if (user.cell->type.in(id_IOLOGIC, id_SIOLOGIC))
                         clockCount[ni->name] += 10;
                 }
             }
@@ -282,7 +282,7 @@ class Ecp5GlobalRouter
     bool route_onto_global(NetInfo *net, int network)
     {
         WireId glb_src;
-        NPNR_ASSERT(net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC);
+        NPNR_ASSERT(net->driver.cell->type.in(id_DCCA, id_DCSC));
         glb_src = ctx->getNetinfoSourceWire(net);
         for (int quad = QUAD_UL; quad < QUAD_LR + 1; quad++) {
             WireId glb_dst = get_global_wire(GlobalQuadrant(quad), network);
@@ -454,7 +454,7 @@ class Ecp5GlobalRouter
     {
         NetInfo *glbptr = nullptr;
         CellInfo *dccptr = nullptr;
-        if (net->driver.cell != nullptr && (net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC)) {
+        if (net->driver.cell != nullptr && (net->driver.cell->type.in(id_DCCA, id_DCSC))) {
             // Already have a DCC (such as clock gating)
             glbptr = net;
             dccptr = net->driver.cell;
@@ -502,7 +502,7 @@ class Ecp5GlobalRouter
 
     int global_route_priority(const PortRef &load)
     {
-        if (load.port == id_WCK || load.port == id_WRE)
+        if (load.port.in(id_WCK, id_WRE))
             return 90;
         return 99;
     }
@@ -555,7 +555,7 @@ class Ecp5GlobalRouter
         dict<int, NetInfo *> clocks;
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_DCCA || ci->type == id_DCSC) {
+            if (ci->type.in(id_DCCA, id_DCSC)) {
                 NetInfo *clock = ci->ports.at((ci->type == id_DCSC) ? id_DCSOUT : id_CLKO).net;
                 NPNR_ASSERT(clock != nullptr);
                 bool drives_fabric = false;
@@ -591,7 +591,7 @@ class Ecp5GlobalRouter
                       return global_route_priority(*a.first) < global_route_priority(*b.first);
                   });
         for (const auto &user : toroute) {
-            if (user.first->cell->type == id_DCSC && (user.first->port == id_CLK0 || user.first->port == id_CLK1)) {
+            if (user.first->cell->type == id_DCSC && (user.first->port.in(id_CLK0, id_CLK1))) {
                 // Special case, skips most of the typical global network
                 NetInfo *net = clocks.at(user.second);
                 simple_router(net, ctx->getNetinfoSourceWire(net), ctx->getNetinfoSinkWire(net, *(user.first), 0));
@@ -606,9 +606,9 @@ class Ecp5GlobalRouter
         // Try and use dedicated paths if possible
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF || ci->type == id_ECLKBRIDGECS) {
+            if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF, id_ECLKBRIDGECS)) {
                 std::vector<IdString> pins;
-                if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
+                if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) {
                     pins.push_back(id_ECLKI);
                 } else {
                     pins.push_back(id_CLK0);
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 4cd33deee3..4c8ceee83f 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -266,11 +266,10 @@ class Ecp5Packer
         if (port.cell == nullptr)
             return false;
         if (port.cell->type == id_DCUA) {
-            return port.port == id_CH0_HDINP || port.port == id_CH0_HDINN || port.port == id_CH0_HDOUTP ||
-                   port.port == id_CH0_HDOUTN || port.port == id_CH1_HDINP || port.port == id_CH1_HDINN ||
-                   port.port == id_CH1_HDOUTP || port.port == id_CH1_HDOUTN;
+            return port.port.in(id_CH0_HDINP, id_CH0_HDINN, id_CH0_HDOUTP, id_CH0_HDOUTN, id_CH1_HDINP, id_CH1_HDINN,
+                                id_CH1_HDOUTP, id_CH1_HDOUTN);
         } else if (port.cell->type == id_EXTREFB) {
-            return port.port == id_REFCLKP || port.port == id_REFCLKN;
+            return port.port.in(id_REFCLKP, id_REFCLKN);
         } else {
             return false;
         }
@@ -905,13 +904,11 @@ class Ecp5Packer
                     uc->params[id_CEMUX] = std::string(constval ? "1" : "0");
                     uc->ports[user.port].net = nullptr;
                 } else if (is_carry(ctx, uc)) {
-                    if (constval &&
-                        (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 ||
-                         user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) {
+                    if (constval && (user.port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))) {
                         // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
                         uc->ports[user.port].net = nullptr;
                     } else if (!constval) {
-                        if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) {
+                        if (user.port.in(id_A0, id_A1, id_B0, id_B1)) {
                             // These inputs can be switched to tie-high without consequence
                             set_ccu2c_input_constant(uc, user.port, constval);
                         } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
@@ -940,10 +937,8 @@ class Ecp5Packer
                             (constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "INV"))) {
                     uc->ports[user.port].net = nullptr;
                 } else if (uc->type == id_DP16KD) {
-                    if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
-                        user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB ||
-                        user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 ||
-                        user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) {
+                    if (user.port.in(id_CLKA, id_CLKB, id_RSTA, id_RSTB, id_WEA, id_WEB, id_CEA, id_CEB, id_OCEA,
+                                     id_OCEB, id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) {
                         // Connect to CIB CLK, LSR or CE. Default state is 1
                         uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV";
                     } else {
@@ -951,7 +946,7 @@ class Ecp5Packer
                         uc->params[ctx->id(user.port.str(ctx) + "MUX")] = std::string(constval ? "1" : "0");
                     }
                     uc->ports[user.port].net = nullptr;
-                } else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) {
+                } else if (uc->type.in(id_ALU54B, id_MULT18X18D)) {
                     if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" ||
                         user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" ||
                         user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" ||
@@ -1350,7 +1345,7 @@ class Ecp5Packer
                     if (net == nullptr || net->driver.cell == nullptr)
                         continue;
                     IdString ct = net->driver.cell->type;
-                    if (ct == id_GND || ct == id_VCC) {
+                    if (ct.in(id_GND, id_VCC)) {
                         ci->disconnectPort(ndport);
                         ci->ports.erase(ndport);
                     }
@@ -1442,7 +1437,7 @@ class Ecp5Packer
                 ci->renamePort(id_USRMCLKI, id_PADDO);
                 ci->renamePort(id_USRMCLKTS, id_PADDT);
                 ci->renamePort(id_USRMCLKO, id_PADDI);
-            } else if (ci->type == id_GSR || ci->type == id_SGSR) {
+            } else if (ci->type.in(id_GSR, id_SGSR)) {
                 ci->params[id_MODE] = std::string("ACTIVE_LOW");
                 ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC");
                 ci->type = id_GSR;
@@ -1894,7 +1889,7 @@ class Ecp5Packer
 
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_DELAYF || ci->type == id_DELAYG) {
+            if (ci->type.in(id_DELAYF, id_DELAYG)) {
                 CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(id_A).net, is_trellis_io, id_O);
                 CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(id_Z).net, is_trellis_io, id_I, true);
                 CellInfo *iol = nullptr;
@@ -2021,7 +2016,7 @@ class Ecp5Packer
                 ci->movePortTo(id_D1, iol, id_TXDATA1);
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == id_ODDRX2F || ci->type == id_ODDR71B) {
+            } else if (ci->type.in(id_ODDRX2F, id_ODDR71B)) {
                 CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
@@ -2061,7 +2056,7 @@ class Ecp5Packer
                 iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
                 pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == id_IDDRX2F || ci->type == id_IDDR71B) {
+            } else if (ci->type.in(id_IDDRX2F, id_IDDR71B)) {
                 CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
                 if (pio == nullptr || ci->ports.at(id_D).net->users.entries() > 1)
                     log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
@@ -2121,7 +2116,7 @@ class Ecp5Packer
                 iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2");
                 pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
                 packed_cells.insert(cell.first);
-            } else if (ci->type == id_ODDRX2DQA || ci->type == id_ODDRX2DQSB) {
+            } else if (ci->type.in(id_ODDRX2DQA, id_ODDRX2DQSB)) {
                 CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
@@ -2183,7 +2178,7 @@ class Ecp5Packer
                 process_dqs_port(ci, pio, iol, id_WRPNTR1);
                 process_dqs_port(ci, pio, iol, id_WRPNTR0);
                 packed_cells.insert(cell.first);
-            } else if (ci->type == id_TSHX2DQA || ci->type == id_TSHX2DQSA) {
+            } else if (ci->type.in(id_TSHX2DQA, id_TSHX2DQSA)) {
                 CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true);
                 if (pio == nullptr)
                     log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
@@ -2388,7 +2383,7 @@ class Ecp5Packer
         // Promote/route edge clocks
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
-            if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
+            if (ci->type.in(id_IOLOGIC, id_DQSBUFM)) {
                 if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
                     continue;
                 BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, id_BEL));
@@ -2669,7 +2664,7 @@ class Ecp5Packer
             pool<IdString> changed_cells;
             for (auto net : changed_nets) {
                 for (auto &user : ctx->nets.at(net)->users)
-                    if (user.port == id_CLKI || user.port == id_ECLKI || user.port == id_CLK0 || user.port == id_CLK1)
+                    if (user.port.in(id_CLKI, id_ECLKI, id_CLK0, id_CLK1))
                         changed_cells.insert(user.cell->name);
                 auto &drv = ctx->nets.at(net)->driver;
                 if (iter == 1 && drv.cell != nullptr && drv.port == id_OSC)
@@ -2688,7 +2683,7 @@ class Ecp5Packer
                     else
                         log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
                     copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
-                } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
+                } else if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) {
                     copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
                 } else if (ci->type == id_ECLKBRIDGECS) {
                     copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 0c027d38a4..fc5e7388c1 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -56,13 +56,12 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_CLK);
         new_cell->addInput(id_CE);
         new_cell->addInput(id_LSR);
-    } else if (type == id_MUX2_LUT5 || type == id_MUX2_LUT6 || type == id_MUX2_LUT7 || type == id_MUX2_LUT7 ||
-               type == id_MUX2_LUT8) {
+    } else if (type.in(id_MUX2_LUT5, id_MUX2_LUT6, id_MUX2_LUT7, id_MUX2_LUT7, id_MUX2_LUT8)) {
         new_cell->addInput(id_I0);
         new_cell->addInput(id_I1);
         new_cell->addInput(id_SEL);
         new_cell->addOutput(id_OF);
-    } else if (type == id_IOB || type == id_IOBS) {
+    } else if (type.in(id_IOB, id_IOBS)) {
         new_cell->params[id_INPUT_USED] = 0;
         new_cell->params[id_OUTPUT_USED] = 0;
         new_cell->params[id_ENABLE_USED] = 0;
diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index 9c9bc3fc02..048ae62efa 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -4969,7 +4969,7 @@ void gfxSetPipDefaultDecal(Arch *arch, PipInfo &pip)
     // create if absent
     if (arch->decal_graphics.count(active_id) == 0) {
         // clock?
-        if (dst_loc_id == id_GT00 || dst_loc_id == id_GT10) {
+        if (dst_loc_id.in(id_GT00, id_GT10)) {
             WireInfo &wi = arch->wire_info(pip.srcWire);
             if (wi.type.str(arch).substr(0, 3) != "UNK") {
                 // create pip
diff --git a/gowin/globals.cc b/gowin/globals.cc
index 1794dd4c39..21ee722ab8 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -32,8 +32,7 @@ NEXTPNR_NAMESPACE_BEGIN
 
 bool GowinGlobalRouter::is_clock_port(PortRef const &user)
 {
-    if ((user.cell->type == id_SLICE || user.cell->type == id_ODDR || user.cell->type == id_ODDRC) &&
-        user.port == id_CLK) {
+    if ((user.cell->type.in(id_SLICE, id_ODDR, id_ODDRC)) && user.port == id_CLK) {
         return true;
     }
     return false;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 905b8d615e..c9c99d3aa4 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -643,7 +643,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
 {
     const auto &driver = net_info->driver;
     if (driver.port == id_COUT) {
-        NPNR_ASSERT(sink.port == id_CIN || sink.port == id_I3);
+        NPNR_ASSERT(sink.port.in(id_CIN, id_I3));
         NPNR_ASSERT(driver.cell->constr_abs_z);
         bool cin = sink.port == id_CIN;
         bool same_y = driver.cell->constr_z < 7;
@@ -904,7 +904,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
             ret.push_back(el);
         }
 
-        if (bel_type == id_ICESTORM_PLL || bel_type == id_SB_WARMBOOT) {
+        if (bel_type.in(id_ICESTORM_PLL, id_SB_WARMBOOT)) {
             GraphicElement el;
             el.type = GraphicElement::TYPE_BOX;
             el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
@@ -937,7 +937,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
             if (fromPort == id_I3 && ((cell->lcInfo.lutInputMask & 0x8U) == 0))
                 return false;
         }
-    } else if (cell->type == id_ICESTORM_RAM || cell->type == id_ICESTORM_SPRAM) {
+    } else if (cell->type.in(id_ICESTORM_RAM, id_ICESTORM_SPRAM)) {
         return false;
     }
     return get_cell_delay_internal(cell, fromPort, toPort, delay);
@@ -971,7 +971,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_CLOCK_INPUT;
         if (port == id_CIN)
             return TMG_COMB_INPUT;
-        if (port == id_COUT || port == id_LO)
+        if (port.in(id_COUT, id_LO))
             return TMG_COMB_OUTPUT;
         if (port == id_O) {
             // LCs with no inputs are constant drivers
@@ -991,7 +991,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         }
     } else if (cell->type == id_ICESTORM_RAM) {
 
-        if (port == id_RCLK || port == id_WCLK)
+        if (port.in(id_RCLK, id_WCLK))
             return TMG_CLOCK_INPUT;
 
         clockInfoCount = 1;
@@ -1000,8 +1000,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_REGISTER_OUTPUT;
         else
             return TMG_REGISTER_INPUT;
-    } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) {
-        if (port == id_CLK || port == id_CLOCK)
+    } else if (cell->type.in(id_ICESTORM_DSP, id_ICESTORM_SPRAM)) {
+        if (port.in(id_CLK, id_CLOCK))
             return TMG_CLOCK_INPUT;
         else {
             clockInfoCount = 1;
@@ -1011,7 +1011,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
                 return TMG_REGISTER_INPUT;
         }
     } else if (cell->type == id_SB_IO) {
-        if (port == id_INPUT_CLK || port == id_OUTPUT_CLK)
+        if (port.in(id_INPUT_CLK, id_OUTPUT_CLK))
             return TMG_CLOCK_INPUT;
         if (port == id_CLOCK_ENABLE) {
             clockInfoCount = 2;
@@ -1023,7 +1023,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         } else if (port == id_D_IN_0) {
             return TMG_STARTPOINT;
         }
-        if (port == id_D_OUT_0 || port == id_D_OUT_1) {
+        if (port.in(id_D_OUT_0, id_D_OUT_1)) {
             if ((cell->ioInfo.pintype & 0xC) == 0x8) {
                 return TMG_ENDPOINT;
             } else {
@@ -1041,7 +1041,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
 
         return TMG_IGNORE;
     } else if (cell->type == id_ICESTORM_PLL) {
-        if (port == id_PLLOUT_A || port == id_PLLOUT_B || port == id_PLLOUT_A_GLOBAL || port == id_PLLOUT_B_GLOBAL)
+        if (port.in(id_PLLOUT_A, id_PLLOUT_B, id_PLLOUT_A_GLOBAL, id_PLLOUT_B_GLOBAL))
             return TMG_GEN_CLOCK;
         return TMG_IGNORE;
     } else if (cell->type == id_ICESTORM_LFOSC) {
@@ -1063,18 +1063,18 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_IGNORE;
         return TMG_ENDPOINT;
     } else if (cell->type == id_SB_RGB_DRV) {
-        if (port == id_RGB0 || port == id_RGB1 || port == id_RGB2 || port == id_RGBPU)
+        if (port.in(id_RGB0, id_RGB1, id_RGB2, id_RGBPU))
             return TMG_IGNORE;
         return TMG_ENDPOINT;
     } else if (cell->type == id_SB_RGBA_DRV) {
-        if (port == id_RGB0 || port == id_RGB1 || port == id_RGB2)
+        if (port.in(id_RGB0, id_RGB1, id_RGB2))
             return TMG_IGNORE;
         return TMG_ENDPOINT;
     } else if (cell->type == id_SB_LEDDA_IP) {
-        if (port == id_CLK || port == id_CLOCK)
+        if (port.in(id_CLK, id_CLOCK))
             return TMG_CLOCK_INPUT;
         return TMG_IGNORE;
-    } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) {
+    } else if (cell->type.in(id_SB_I2C, id_SB_SPI)) {
         if (port == id_SBCLKI)
             return TMG_CLOCK_INPUT;
 
@@ -1098,7 +1098,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             bool has_clktoq = get_cell_delay_internal(cell, id_CLK, id_O, info.clockToQ);
             NPNR_ASSERT(has_clktoq);
         } else {
-            if (port == id_I0 || port == id_I1 || port == id_I2 || port == id_I3) {
+            if (port.in(id_I0, id_I1, id_I2, id_I3)) {
                 DelayQuad dlut;
                 bool has_ld = get_cell_delay_internal(cell, port, id_O, dlut);
                 NPNR_ASSERT(has_ld);
@@ -1146,7 +1146,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE;
             info.setup = DelayPair(io_setup);
             info.hold = DelayPair(0);
-        } else if (port == id_D_OUT_0 || port == id_OUTPUT_ENABLE) {
+        } else if (port.in(id_D_OUT_0, id_OUTPUT_ENABLE)) {
             info.clock_port = id_OUTPUT_CLK;
             info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE;
             info.setup = DelayPair(io_setup);
@@ -1167,7 +1167,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         } else {
             NPNR_ASSERT_FALSE("no clock data for IO cell port");
         }
-    } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) {
+    } else if (cell->type.in(id_ICESTORM_DSP, id_ICESTORM_SPRAM)) {
         info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK;
         info.edge = RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
@@ -1178,7 +1178,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.setup = DelayPair(100);
             info.hold = DelayPair(0);
         }
-    } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) {
+    } else if (cell->type.in(id_SB_I2C, id_SB_SPI)) {
         info.clock_port = id_SBCLKI;
         info.edge = RISING_EDGE;
         if (cell->ports.at(port).type == PORT_OUT) {
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 67ddf77763..5c3fa3c5c1 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -105,7 +105,7 @@ bool Arch::isBelLocationValid(BelId bel) const
             // that are a PLL clock output.
             auto wire = getBelPinWire(bel, id_D_IN_0);
             for (auto pin : getWireBelPins(wire)) {
-                if (pin.pin == id_PLLOUT_A || pin.pin == id_PLLOUT_B) {
+                if (pin.pin.in(id_PLLOUT_A, id_PLLOUT_B)) {
                     // Is there a PLL there ?
                     const CellInfo *pll_cell = getBoundBelCell(pin.bel);
                     if (pll_cell == nullptr)
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 48fbc1320b..3e50c06585 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -640,8 +640,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                     {"CURRENT_MODE", 1}, {"RGB0_CURRENT", 6}, {"RGB1_CURRENT", 6}, {"RGB2_CURRENT", 6}};
             configure_extra_cell(config, ctx, cell.second.get(), rgba_params, true, std::string("IpConfig."));
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "RGBA_DRV_EN", true, "IpConfig.");
-        } else if (cell.second->type == id_SB_WARMBOOT || cell.second->type == id_ICESTORM_LFOSC ||
-                   cell.second->type == id_SB_LEDDA_IP) {
+        } else if (cell.second->type.in(id_SB_WARMBOOT, id_ICESTORM_LFOSC, id_SB_LEDDA_IP)) {
             // No config needed
         } else if (cell.second->type == id_SB_I2C) {
             bool sda_in_dly = !cell.second->attrs.count(id_SDA_INPUT_DELAYED) ||
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 9166b41b8d..fc24caaf4f 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -502,13 +502,13 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell->type == id_ICESTORM_LC)
         return port.port == id_CLK;
     if (is_ram(ctx, port.cell) || port.cell->type == id_ICESTORM_RAM)
-        return port.port == id_RCLK || port.port == id_WCLK || port.port == id_RCLKN || port.port == id_WCLKN;
+        return port.port.in(id_RCLK, id_WCLK, id_RCLKN, id_WCLKN);
     if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP)
         return port.port == id_CLK;
     if (is_sb_spram(ctx, port.cell) || port.cell->type == id_ICESTORM_SPRAM)
         return port.port == id_CLOCK;
     if (is_sb_io(ctx, port.cell))
-        return port.port == id_INPUT_CLK || port.port == id_OUTPUT_CLK;
+        return port.port.in(id_INPUT_CLK, id_OUTPUT_CLK);
     return false;
 }
 
@@ -517,11 +517,11 @@ bool is_reset_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell == nullptr)
         return false;
     if (is_ff(ctx, port.cell))
-        return port.port == id_R || port.port == id_S;
+        return port.port.in(id_R, id_S);
     if (port.cell->type == id_ICESTORM_LC)
         return port.port == id_SR;
     if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP)
-        return port.port == id_IRSTTOP || port.port == id_IRSTBOT || port.port == id_ORSTTOP || port.port == id_ORSTBOT;
+        return port.port.in(id_IRSTTOP, id_IRSTBOT, id_ORSTTOP, id_ORSTBOT);
     return false;
 }
 
diff --git a/ice40/cells.h b/ice40/cells.h
index 724500d66c..8aed649de3 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -35,13 +35,9 @@ inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_SB_DFF || cell->type == id_SB_DFFE || cell->type == id_SB_DFFSR ||
-           cell->type == id_SB_DFFR || cell->type == id_SB_DFFSS || cell->type == id_SB_DFFS ||
-           cell->type == id_SB_DFFESR || cell->type == id_SB_DFFER || cell->type == id_SB_DFFESS ||
-           cell->type == id_SB_DFFES || cell->type == id_SB_DFFN || cell->type == id_SB_DFFNE ||
-           cell->type == id_SB_DFFNSR || cell->type == id_SB_DFFNR || cell->type == id_SB_DFFNSS ||
-           cell->type == id_SB_DFFNS || cell->type == id_SB_DFFNESR || cell->type == id_SB_DFFNER ||
-           cell->type == id_SB_DFFNESS || cell->type == id_SB_DFFNES;
+    return cell->type.in(id_SB_DFF, id_SB_DFFE, id_SB_DFFSR, id_SB_DFFR, id_SB_DFFSS, id_SB_DFFS, id_SB_DFFESR,
+                         id_SB_DFFER, id_SB_DFFESS, id_SB_DFFES, id_SB_DFFN, id_SB_DFFNE, id_SB_DFFNSR, id_SB_DFFNR,
+                         id_SB_DFFNSS, id_SB_DFFNS, id_SB_DFFNESR, id_SB_DFFNER, id_SB_DFFNESS, id_SB_DFFNES);
 }
 
 inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_CARRY; }
@@ -60,8 +56,7 @@ inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->typ
 // Return true if a cell is a RAM
 inline bool is_ram(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_SB_RAM40_4K || cell->type == id_SB_RAM40_4KNR || cell->type == id_SB_RAM40_4KNW ||
-           cell->type == id_SB_RAM40_4KNRNW;
+    return cell->type.in(id_SB_RAM40_4K, id_SB_RAM40_4KNR, id_SB_RAM40_4KNW, id_SB_RAM40_4KNRNW);
 }
 
 inline bool is_sb_lfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LFOSC; }
@@ -86,13 +81,12 @@ inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->t
 
 inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD ||
-           cell->type == id_SB_PLL40_CORE || cell->type == id_SB_PLL40_2F_CORE;
+    return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_CORE, id_SB_PLL40_2F_CORE);
 }
 
 inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD ||
+    return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD) ||
            (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_PAD" ||
                                               cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" ||
                                               cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD"));
@@ -100,7 +94,7 @@ inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
 
 inline bool is_sb_pll40_dual(const BaseCtx *ctx, const CellInfo *cell)
 {
-    return cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD || cell->type == id_SB_PLL40_2F_CORE ||
+    return cell->type.in(id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_2F_CORE) ||
            (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" ||
                                               cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD" ||
                                               cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_CORE"));
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 9eff053e65..c981172175 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -345,8 +345,8 @@ static void pack_ram(Context *ctx)
                 packed->attrs[attr.first] = attr.second;
             for (auto param : ci->params)
                 packed->params[param.first] = param.second;
-            packed->params[id_NEG_CLK_W] = Property(ci->type == id_SB_RAM40_4KNW || ci->type == id_SB_RAM40_4KNRNW, 1);
-            packed->params[id_NEG_CLK_R] = Property(ci->type == id_SB_RAM40_4KNR || ci->type == id_SB_RAM40_4KNRNW, 1);
+            packed->params[id_NEG_CLK_W] = Property(ci->type.in(id_SB_RAM40_4KNW, id_SB_RAM40_4KNRNW), 1);
+            packed->params[id_NEG_CLK_R] = Property(ci->type.in(id_SB_RAM40_4KNR, id_SB_RAM40_4KNRNW), 1);
             packed->type = id_ICESTORM_RAM;
             for (auto port : ci->ports) {
                 PortInfo &pi = port.second;
@@ -1468,11 +1468,11 @@ void pack_plls(Context *ctx)
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
 
-                if (pi.name == id_PLLOUTCOREA || pi.name == id_PLLOUTCORE)
+                if (pi.name.in(id_PLLOUTCOREA, id_PLLOUTCORE))
                     newname = "PLLOUT_A";
                 if (pi.name == id_PLLOUTCOREB)
                     newname = "PLLOUT_B";
-                if (pi.name == id_PLLOUTGLOBALA || pi.name == id_PLLOUTGLOBAL)
+                if (pi.name.in(id_PLLOUTGLOBALA, id_PLLOUTGLOBAL))
                     newname = "PLLOUT_A_GLOBAL";
                 if (pi.name == id_PLLOUTGLOBALB)
                     newname = "PLLOUT_B_GLOBAL";
diff --git a/mistral/globals.cc b/mistral/globals.cc
index 6af8920d76..bdd835a7e0 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -38,10 +38,7 @@ void Arch::create_clkbuf(int x, int y)
     }
 }
 
-bool Arch::is_clkbuf_cell(IdString cell_type) const
-{
-    return cell_type == id_MISTRAL_CLKENA || cell_type == id_MISTRAL_CLKBUF;
-}
+bool Arch::is_clkbuf_cell(IdString cell_type) const { return cell_type.in(id_MISTRAL_CLKENA, id_MISTRAL_CLKBUF); }
 
 void Arch::create_hps_mpu_general_purpose(int x, int y)
 {
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 4a956fae54..c2d3b6e41c 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -479,7 +479,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
             }
             return result;
         } else {
-            if (toPort == id_F || toPort == id_OFX)
+            if (toPort.in(id_F, id_OFX))
                 return lookup_cell_delay(cell->tmg_index, fromPort, toPort, delay);
         }
     } else if (is_dsp_cell(cell)) {
@@ -487,7 +487,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
             return false; // don't include delays that are actually clock-to-out here
         return lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
     } else if (cell->type == id_DCS) {
-        if (fromPort == id_SELFORCE || fromPort == id_SEL) {
+        if (fromPort.in(id_SELFORCE, id_SEL)) {
             return false;
         }
         int index = get_cell_timing_idx(id_DCS, id_DCS);
@@ -505,10 +505,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
     };
     clockInfoCount = 0;
     if (cell->type == id_OXIDE_COMB) {
-        if (port == id_A || port == id_B || port == id_C || port == id_D || port == id_SEL || port == id_F1 ||
-            port == id_FCI || port == id_WDI)
+        if (port.in(id_A, id_B, id_C, id_D, id_SEL, id_F1, id_FCI, id_WDI))
             return TMG_COMB_INPUT;
-        if (port == id_F || port == id_OFX || port == id_FCO) {
+        if (port.in(id_F, id_OFX, id_FCO)) {
             if (disconnected(id_A) && disconnected(id_B) && disconnected(id_C) && disconnected(id_D) &&
                 disconnected(id_FCI) && disconnected(id_SEL) && disconnected(id_WDI))
                 return TMG_IGNORE;
@@ -528,18 +527,17 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
     } else if (cell->type == id_RAMW) {
         if (port == id_CLK)
             return TMG_CLOCK_INPUT;
-        else if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3) {
+        else if (port.in(id_WDO0, id_WDO1, id_WDO2, id_WDO3)) {
             clockInfoCount = 1;
             return TMG_REGISTER_OUTPUT;
-        } else if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
-                   port == id_D0 || port == id_D1) {
+        } else if (port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1)) {
             clockInfoCount = 1;
             return TMG_REGISTER_INPUT;
         }
     } else if (cell->type == id_OXIDE_EBR) {
-        if (port == id_DWS0 || port == id_DWS1 || port == id_DWS2 || port == id_DWS3 || port == id_DWS4)
+        if (port.in(id_DWS0, id_DWS1, id_DWS2, id_DWS3, id_DWS4))
             return TMG_IGNORE;
-        if (port == id_CLKA || port == id_CLKB)
+        if (port.in(id_CLKA, id_CLKB))
             return TMG_CLOCK_INPUT;
         clockInfoCount = 1;
         return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
@@ -551,9 +549,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_CLOCK_INPUT;
         clockInfoCount = 1;
         return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
-    } else if (cell->type == id_MULT18_CORE || cell->type == id_MULT18X36_CORE || cell->type == id_MULT36_CORE) {
+    } else if (cell->type.in(id_MULT18_CORE, id_MULT18X36_CORE, id_MULT36_CORE)) {
         return (cell->ports.at(port).type == PORT_IN) ? TMG_COMB_INPUT : TMG_COMB_OUTPUT;
-    } else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
+    } else if (cell->type.in(id_PREADD9_CORE, id_REG18_CORE, id_MULT9_CORE)) {
         if (port == id_CLK)
             return TMG_CLOCK_INPUT;
         auto type = lookup_port_type(cell->tmg_index, lookup_port(port), cell->ports.at(port).type, id_CLK);
@@ -571,7 +569,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         // FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN
         // yielded in error in the timing analyzer. For now keep those as
         // regular combinational ports.
-        if (port == id_CLK0 || port == id_CLK1)
+        if (port.in(id_CLK0, id_CLK1))
             return TMG_COMB_INPUT;
         else if (port == id_DCSOUT) {
             return TMG_COMB_OUTPUT;
@@ -598,7 +596,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     } else if (cell->type == id_RAMW) {
         info.edge = (cell->ffInfo.ctrlset.clkmux == ID_INV) ? FALLING_EDGE : RISING_EDGE;
         info.clock_port = id_CLK;
-        if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3)
+        if (port.in(id_WDO0, id_WDO1, id_WDO2, id_WDO3))
             NPNR_ASSERT(lookup_cell_delay(cell->tmg_index, id_CLK, port, info.clockToQ));
         else
             lookup_cell_setuphold(cell->tmg_index, port, id_CLK, info.setup, info.hold);
@@ -618,7 +616,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             NPNR_ASSERT(lookup_cell_delay(cell->tmg_index, id_CLK, lookup_port(port), info.clockToQ));
         }
         info.edge = (get_cell_pinmux(cell, info.clock_port) == PINMUX_INV) ? FALLING_EDGE : RISING_EDGE;
-    } else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
+    } else if (cell->type.in(id_PREADD9_CORE, id_REG18_CORE, id_MULT9_CORE)) {
         info.clock_port = id_CLK;
         if (cell->ports.at(port).type == PORT_IN) {
             lookup_cell_setuphold(cell->tmg_index, lookup_port(port), id_CLK, info.setup, info.hold);
@@ -737,9 +735,8 @@ void Arch::pre_routing()
 {
     for (auto &cell : cells) {
         CellInfo *ci = cell.second.get();
-        if (ci->type == id_MULT9_CORE || ci->type == id_PREADD9_CORE || ci->type == id_MULT18_CORE ||
-            ci->type == id_MULT18X36_CORE || ci->type == id_MULT36_CORE || ci->type == id_REG18_CORE ||
-            ci->type == id_ACC54_CORE) {
+        if (ci->type.in(id_MULT9_CORE, id_PREADD9_CORE, id_MULT18_CORE, id_MULT18X36_CORE, id_MULT36_CORE,
+                        id_REG18_CORE, id_ACC54_CORE)) {
             for (auto &port : ci->ports) {
                 WireId wire = getBelPinWire(ci->bel, port.first);
                 if (wire != WireId())
@@ -953,8 +950,8 @@ int db_binary_search(const Tres *list, int count, Tgetter key_getter, Tkey key)
 
 bool Arch::is_dsp_cell(const CellInfo *cell) const
 {
-    return cell->type == id_MULT18_CORE || cell->type == id_MULT18X36_CORE || cell->type == id_MULT36_CORE ||
-           cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE;
+    return cell->type.in(id_MULT18_CORE, id_MULT18X36_CORE, id_MULT36_CORE, id_PREADD9_CORE, id_REG18_CORE,
+                         id_MULT9_CORE);
 }
 
 int Arch::get_cell_timing_idx(IdString cell_type, IdString cell_variant) const
diff --git a/nexus/arch.h b/nexus/arch.h
index d713afcfe4..4a28dfb704 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1072,7 +1072,7 @@ struct Arch : BaseArch<ArchRanges>
     bool getBelGlobalBuf(BelId bel) const override
     {
         IdString type = getBelType(bel);
-        return type == id_DCC || type == id_VCC_DRV;
+        return type.in(id_DCC, id_VCC_DRV);
     }
 
     IdString getBelType(BelId bel) const override
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 48a3d2591b..81208c0f20 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -1079,9 +1079,8 @@ struct NexusFasmWriter
                 write_osc(ci);
             else if (ci->type == id_OXIDE_EBR)
                 write_bram(ci);
-            else if (ci->type == id_MULT9_CORE || ci->type == id_PREADD9_CORE || ci->type == id_MULT18_CORE ||
-                     ci->type == id_MULT18X36_CORE || ci->type == id_MULT36_CORE || ci->type == id_REG18_CORE ||
-                     ci->type == id_ACC54_CORE)
+            else if (ci->type.in(id_MULT9_CORE, id_PREADD9_CORE, id_MULT18_CORE, id_MULT18X36_CORE, id_MULT36_CORE,
+                                 id_REG18_CORE, id_ACC54_CORE))
                 write_dsp(ci);
             else if (ci->type == id_PLL_CORE)
                 write_pll(ci);
@@ -1089,7 +1088,7 @@ struct NexusFasmWriter
                 write_lram(ci);
             else if (ci->type == id_DPHY_CORE)
                 write_dphy(ci);
-            else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC)
+            else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC))
                 write_iol(ci);
             else if (ci->type == id_DCC)
                 write_dcc(ci);
diff --git a/nexus/global.cc b/nexus/global.cc
index 37629f6417..0792715dbd 100644
--- a/nexus/global.cc
+++ b/nexus/global.cc
@@ -193,7 +193,7 @@ struct NexusGlobalRouter
             CellInfo *drv = ni->driver.cell;
             if (drv == nullptr)
                 continue;
-            if (drv->type == id_DCC || drv->type == id_DCS) {
+            if (drv->type.in(id_DCC, id_DCS)) {
                 route_clk_net(ni);
                 continue;
             }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index e727364d6b..3d293f6903 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1981,11 +1981,11 @@ struct NexusPacker
             pool<IdString> changed_cells;
             for (auto net : changed_nets) {
                 for (auto &user : ctx->nets.at(net)->users)
-                    if (user.port == id_CLKI || user.port == id_REFCK)
+                    if (user.port.in(id_CLKI, id_REFCK))
                         changed_cells.insert(user.cell->name);
                 auto &drv = ctx->nets.at(net)->driver;
                 if (iter == 1 && drv.cell != nullptr) {
-                    if (drv.cell->type == id_OSC_CORE && (drv.port == id_HFCLKOUT || drv.port == id_LFCLKOUT))
+                    if (drv.cell->type == id_OSC_CORE && (drv.port.in(id_HFCLKOUT, id_LFCLKOUT)))
                         changed_cells.insert(drv.cell->name);
                     if (drv.cell->type == id_DCC && drv.port == id_CLKO)
                         changed_cells.insert(drv.cell->name);

From 47da562600315f99b4de269a056f00b9d14ed62f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 15 Aug 2022 12:15:00 +0200
Subject: [PATCH 173/712] viaduct: Allow passing command line options to uarch
 with -o

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/main.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/generic/main.cc b/generic/main.cc
index d08ae3819a..3ee1c790fa 100644
--- a/generic/main.cc
+++ b/generic/main.cc
@@ -49,6 +49,8 @@ po::options_description GenericCommandHandler::getArchOptions()
     po::options_description specific("Architecture specific options");
     specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
     specific.add_options()("no-iobs", "disable automatic IO buffer insertion");
+    specific.add_options()("vopt,o", po::value<std::vector<std::string>>(), "options to pass to the viaduct uarch");
+
     return specific;
 }
 
@@ -68,6 +70,16 @@ std::unique_ptr<Context> GenericCommandHandler::createContext(dict<std::string,
     if (vm.count("uarch")) {
         std::string uarch_name = vm["uarch"].as<std::string>();
         dict<std::string, std::string> args; // TODO
+        if (vm.count("vopt")) {
+            std::vector<std::string> options = vm["vopt"].as<std::vector<std::string>>();
+            for (const auto &opt : options) {
+                size_t epos = opt.find('=');
+                if (epos == std::string::npos)
+                    args[opt] = "";
+                else
+                    args[opt.substr(0, epos)] = opt.substr(epos + 1);
+            }
+        }
         auto uarch = ViaductArch::create(uarch_name, args);
         if (!uarch) {
             std::string all_uarches = ViaductArch::list();
@@ -75,6 +87,8 @@ std::unique_ptr<Context> GenericCommandHandler::createContext(dict<std::string,
         }
         ctx->uarch = std::move(uarch);
         ctx->uarch->init(ctx.get());
+    } else if (vm.count("vopt")) {
+        log_error("Viaduct options passed in non-viaduct mode!\n");
     }
     return ctx;
 }

From ae8966040bc7f148958d4ac0b989e04059b6ba06 Mon Sep 17 00:00:00 2001
From: LAK132 <lakridesagain@gmail.com>
Date: Tue, 16 Aug 2022 20:14:43 +0930
Subject: [PATCH 174/712] Replace deprecated method of finding Python 3

---
 CMakeLists.txt | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3812f7dcc9..269e90eb5e 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -173,10 +173,10 @@ if (BUILD_GUI)
     set(CMAKE_ENABLE_EXPORTS ON)
 endif()
 
-find_package(PythonInterp 3.5 REQUIRED)
+find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 if (BUILD_PYTHON)
     # TODO: sensible minimum Python version
-    find_package(PythonLibs 3.5 REQUIRED)
+    find_package(Python3 3.5 REQUIRED COMPONENTS Development)
 else()
     add_definitions("-DNO_PYTHON")
 endif()
@@ -221,7 +221,7 @@ if (NOT DEFINED PYBIND11_INCLUDE_DIR)
     set(PYBIND11_INCLUDE_DIR "3rdparty/pybind11/include")
 endif()
 
-include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
+include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${Python3_INCLUDE_DIRS})
 
 if(BUILD_HEAP)
     find_package (Eigen3 REQUIRED NO_MODULE)
@@ -339,7 +339,7 @@ foreach (family ${ARCH})
             target_link_libraries(${target} LINK_PUBLIC gui_${family} ${GUI_LIBRARY_FILES_${ufamily}})
         endif()
         if (BUILD_PYTHON)
-            target_link_libraries(${target} LINK_PUBLIC ${PYTHON_LIBRARIES})
+            target_link_libraries(${target} LINK_PUBLIC ${Python3_LIBRARIES})
             if (STATIC_BUILD)
                 target_link_libraries(${target} LINK_PUBLIC ${CMAKE_THREAD_LIBS_INIT} ${CMAKE_DL_LIBS} ${ZLIB_LIBRARIES} ${EXPAT_LIBRARIES})
                 if(${CMAKE_SYSTEM_NAME} MATCHES "Darwin")

From 05167fcb8bf9cd85ea605331ca36cac6f25ce67f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 18 Aug 2022 15:09:41 +0200
Subject: [PATCH 175/712] pybindings: Mark CellInfo::bel as readonly

bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement.

Fixes #522

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/pybindings.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index 9a783eb41d..f738f081a2 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -191,8 +191,7 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
             ci_cls, "params");
     readonly_wrapper<CellInfo &, decltype(&CellInfo::ports), &CellInfo::ports, wrap_context<PortMap &>>::def_wrap(
             ci_cls, "ports");
-    readwrite_wrapper<CellInfo &, decltype(&CellInfo::bel), &CellInfo::bel, conv_to_str<BelId>,
-                      conv_from_str<BelId>>::def_wrap(ci_cls, "bel");
+    readonly_wrapper<CellInfo &, decltype(&CellInfo::bel), &CellInfo::bel, conv_to_str<BelId>>::def_wrap(ci_cls, "bel");
     readwrite_wrapper<CellInfo &, decltype(&CellInfo::belStrength), &CellInfo::belStrength, pass_through<PlaceStrength>,
                       pass_through<PlaceStrength>>::def_wrap(ci_cls, "belStrength");
 

From 19160f10ae8916f9bb22166ce38186550c56b6d5 Mon Sep 17 00:00:00 2001
From: Adam Sampson <ats@offog.org>
Date: Sun, 21 Aug 2022 17:47:35 +0100
Subject: [PATCH 176/712] Use CMake's Python3 rather than PythonInterp in
 subdirs

---
 README.md                                     | 2 +-
 ecp5/CMakeLists.txt                           | 4 ++--
 fpga_interchange/examples/chipdb.cmake        | 8 ++++----
 fpga_interchange/examples/chipdb_xilinx.cmake | 2 +-
 fpga_interchange/examples/tests.cmake         | 8 ++++----
 ice40/CMakeLists.txt                          | 4 ++--
 machxo2/CMakeLists.txt                        | 4 ++--
 7 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/README.md b/README.md
index 36ff9a8b6b..957be8899a 100644
--- a/README.md
+++ b/README.md
@@ -65,7 +65,7 @@ sudo make install
 On Windows, you may specify paths explicitly:
 
 ```
-cmake . -DARCH=ice40 -DICESTORM_INSTALL_PREFIX=C:/ProgramData/icestorm -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake -DVCPKG_TARGET_TRIPLET=x64-windows -G "Visual Studio 15 2017 Win64" -DPYTHON_EXECUTABLE=C:/Python364/python.exe -DPYTHON_LIBRARY=C:/vcpkg/packages/python3_x64-windows/lib/python36.lib -DPYTHON_INCLUDE_DIR=C:/vcpkg/packages/python3_x64-windows/include/python3.6 .
+cmake . -DARCH=ice40 -DICESTORM_INSTALL_PREFIX=C:/ProgramData/icestorm -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake -DVCPKG_TARGET_TRIPLET=x64-windows -G "Visual Studio 15 2017 Win64" -DPython3_EXECUTABLE=C:/Python364/python.exe -DPython3_LIBRARY=C:/vcpkg/packages/python3_x64-windows/lib/python36.lib -DPython3_INCLUDE_DIR=C:/vcpkg/packages/python3_x64-windows/include/python3.6 .
 cmake --build . --config Release
 ```
 
diff --git a/ecp5/CMakeLists.txt b/ecp5/CMakeLists.txt
index bc34d51b90..115e0ce896 100644
--- a/ecp5/CMakeLists.txt
+++ b/ecp5/CMakeLists.txt
@@ -9,7 +9,7 @@ message(STATUS "Enabled ECP5 devices: ${ECP5_DEVICES}")
 if(DEFINED ECP5_CHIPDB)
     add_custom_target(chipdb-ecp5-bbas ALL)
 else()
-    find_package(PythonInterp 3.5 REQUIRED)
+    find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 
     # shared among all families
     set(SERIALIZE_CHIPDBS TRUE CACHE BOOL
@@ -81,7 +81,7 @@ else()
         set(device_bba chipdb/chipdb-${device}.bba)
         add_custom_command(
             OUTPUT ${device_bba}
-            COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/trellis_import.py
+            COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/trellis_import.py
                 -L ${TRELLIS_LIBDIR}
                 -L ${TRELLIS_DATADIR}/util/common
                 -L ${TRELLIS_DATADIR}/timing/util
diff --git a/fpga_interchange/examples/chipdb.cmake b/fpga_interchange/examples/chipdb.cmake
index a060576de6..e820124baa 100644
--- a/fpga_interchange/examples/chipdb.cmake
+++ b/fpga_interchange/examples/chipdb.cmake
@@ -57,7 +57,7 @@ function(create_patched_device_db)
     add_custom_command(
         OUTPUT ${output_device_file}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.patch
+            ${Python3_EXECUTABLE} -mfpga_interchange.patch
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --schema device
                 --patch_path ${patch_path}
@@ -76,7 +76,7 @@ function(create_patched_device_db)
 
     add_custom_target(${patch_name}-${device}-device-yaml
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
+            ${Python3_EXECUTABLE} -mfpga_interchange.convert
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --schema device
                 --input_format capnp
@@ -145,7 +145,7 @@ function(patch_device_with_prim_lib)
     add_custom_command(
         OUTPUT ${output_device_file}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.add_prim_lib
+            ${Python3_EXECUTABLE} -mfpga_interchange.add_prim_lib
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 ${input_device_loc}
                 ${output_json_file}
@@ -227,7 +227,7 @@ function(generate_chipdb)
     add_custom_command(
         OUTPUT ${chipdb_bba}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.nextpnr_emit
+            ${Python3_EXECUTABLE} -mfpga_interchange.nextpnr_emit
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --output_dir ${CMAKE_CURRENT_BINARY_DIR}
                 --device_config ${device_config}
diff --git a/fpga_interchange/examples/chipdb_xilinx.cmake b/fpga_interchange/examples/chipdb_xilinx.cmake
index 23b4d7f127..62e6b9eda6 100644
--- a/fpga_interchange/examples/chipdb_xilinx.cmake
+++ b/fpga_interchange/examples/chipdb_xilinx.cmake
@@ -53,7 +53,7 @@ function(create_rapidwright_device_db)
 
     add_custom_target(rapidwright-${device}-device-yaml
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
+            ${Python3_EXECUTABLE} -mfpga_interchange.convert
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --schema device
                 --input_format capnp
diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake
index 48b1cee3b7..b568c5df7b 100644
--- a/fpga_interchange/examples/tests.cmake
+++ b/fpga_interchange/examples/tests.cmake
@@ -98,7 +98,7 @@ function(add_interchange_test)
     add_custom_command(
         OUTPUT ${netlist}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.yosys_json
+            ${Python3_EXECUTABLE} -mfpga_interchange.yosys_json
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --device ${device_loc}
                 --top ${top}
@@ -117,7 +117,7 @@ function(add_interchange_test)
     add_custom_command(
         OUTPUT ${netlist_yaml}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
+            ${Python3_EXECUTABLE} -mfpga_interchange.convert
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --schema logical
                 --input_format capnp
@@ -248,7 +248,7 @@ function(add_interchange_test)
     add_custom_command(
         OUTPUT ${phys_yaml}
         COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
+            ${Python3_EXECUTABLE} -mfpga_interchange.convert
                 --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                 --schema physical
                 --input_format capnp
@@ -296,7 +296,7 @@ function(add_interchange_test)
         add_custom_command(
             OUTPUT ${fasm}
             COMMAND
-                ${PYTHON_EXECUTABLE} -mfpga_interchange.fasm_generator
+                ${Python3_EXECUTABLE} -mfpga_interchange.fasm_generator
                     --schema_dir ${INTERCHANGE_SCHEMA_PATH}
                     --family ${device_family}
                     ${device_loc}
diff --git a/ice40/CMakeLists.txt b/ice40/CMakeLists.txt
index 7a878bf45a..3bdfa26de2 100644
--- a/ice40/CMakeLists.txt
+++ b/ice40/CMakeLists.txt
@@ -9,7 +9,7 @@ message(STATUS "Enabled iCE40 devices: ${ICE40_DEVICES}")
 if(DEFINED ICE40_CHIPDB)
     add_custom_target(chipdb-ice40-bbas ALL)
 else()
-    find_package(PythonInterp 3.5 REQUIRED)
+    find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 
     # shared among all families
     set(SERIALIZE_CHIPDBS TRUE CACHE BOOL
@@ -57,7 +57,7 @@ else()
         set(device_bba chipdb/chipdb-${device}.bba)
         add_custom_command(
             OUTPUT ${device_bba}
-            COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/chipdb.py
+            COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/chipdb.py
                 -p ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
                 -g ${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
                 ${timing_opts}
diff --git a/machxo2/CMakeLists.txt b/machxo2/CMakeLists.txt
index ab4eded6c2..f772f80124 100644
--- a/machxo2/CMakeLists.txt
+++ b/machxo2/CMakeLists.txt
@@ -10,7 +10,7 @@ message(STATUS "Enabled MachXO2 devices: ${MACHXO2_DEVICES}")
 if(DEFINED MACHXO2_CHIPDB)
     add_custom_target(chipdb-machxo2-bbas ALL)
 else()
-    find_package(PythonInterp 3.5 REQUIRED)
+    find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 
     # shared among all families
     set(SERIALIZE_CHIPDBS TRUE CACHE BOOL
@@ -58,7 +58,7 @@ else()
         set(device_bba chipdb/chipdb-${device}.bba)
         add_custom_command(
             OUTPUT ${device_bba}
-            COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/facade_import.py
+            COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/facade_import.py
                 -L ${TRELLIS_LIBDIR}
                 -L ${TRELLIS_DATADIR}/util/common
                 -L ${TRELLIS_DATADIR}/timing/util

From 1aa797b82068a6ac0691c2e6a5e2ebe91a9a7b72 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 22 Aug 2022 12:32:50 +0200
Subject: [PATCH 177/712] Fix parameter order

---
 common/route/router2.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index 1153f054bc..d054c9efbd 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -373,8 +373,7 @@ struct Router2
         return base_cost * hist_cost * present_cost / (1 + (source_uses * crit_weight)) + bias_cost;
     }
 
-    float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, float crit_weight,
-                        bool bwd = false)
+    float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, bool bwd, float crit_weight)
     {
         auto &nd = nets.at(net->udata);
         auto &wd = flat_wires[wire];

From a00b997cf19c0123f46f6509b2e42142e72f1d8c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 22 Aug 2022 12:35:24 +0200
Subject: [PATCH 178/712] add missing overrides

---
 common/kernel/nextpnr_types.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index e4042aecc3..2a9062fd2a 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -205,9 +205,9 @@ struct RegionPlug : PseudoCell
     WireId getPortWire(IdString port) const override { return port_wires.at(port); }
 
     // TODO: partial reconfiguration region timing
-    bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; }
-    TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; }
-    virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; }
+    bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const override { return false; }
+    TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const override { return TMG_IGNORE; }
+    TimingClockingInfo getPortClockingInfo(IdString port, int index) const override { return TimingClockingInfo{}; }
 
     dict<IdString, WireId> port_wires;
     Loc loc;

From e0539f0ed77b0dd9400f3947fcd2dbf1b5b78ae0 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 25 Aug 2022 11:52:29 +1000
Subject: [PATCH 179/712] gowin: BUGFIX. Really memorize the chip

When it really needed to distinguish between the chips, this
unforgivable error was discovered :)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index b37d444cee..e33a904ac1 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1168,6 +1168,8 @@ Arch::Arch(ArchArgs args) : args(args)
     log_info("Series:%s Device:%s Package:%s Speed:%s\n", family.c_str(), device_id.c_str(this),
              package_name.c_str(this), speed_id.c_str(this));
 
+    device = device_id.str(this);
+
     // setup db
     // add global VCC and GND bels
     addBel(id_GND, id_GND, Loc(0, 0, BelZ::gnd_0_z), true);

From 8b6be098094c6de151199a33690d6e8ecacdd446 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 30 Aug 2022 17:30:13 +0200
Subject: [PATCH 180/712] Fixed port timing classes of DCC ports in the Nexus
 architecture

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 nexus/arch.cc | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index c2d3b6e41c..70e3d38de3 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -492,6 +492,15 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         }
         int index = get_cell_timing_idx(id_DCS, id_DCS);
         return lookup_cell_delay(index, fromPort, toPort, delay);
+    } else if (cell->type == id_DCC) {
+        if (fromPort == id_CLKI && toPort == id_CLKO) {
+            // TODO: Use actual DCC delays
+            delay.rise.min_delay = 1000;
+            delay.rise.max_delay = 1000;
+            delay.fall.min_delay = 1000;
+            delay.fall.max_delay = 1000;
+            return true;
+        }
     }
     return false;
 }
@@ -560,11 +569,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         return type;
     } else if (cell->type == id_DCC) {
         if (port == id_CLKI)
-            return TMG_CLOCK_INPUT;
-        else if (port == id_CLKO)
-            return TMG_GEN_CLOCK;
-        else if (port == id_CE)
             return TMG_COMB_INPUT;
+        else if (port == id_CLKO)
+            return TMG_COMB_OUTPUT;
     } else if (cell->type == id_DCS) {
         // FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN
         // yielded in error in the timing analyzer. For now keep those as

From 9a61ad923444bbf01f777bd76b4b2e74e4e5c503 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 30 Aug 2022 17:30:58 +0200
Subject: [PATCH 181/712] Augmented TimingAnalyser class with detection of
 clock to clock relations

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 common/kernel/timing.cc | 226 ++++++++++++++++++++++++++++++++++++++--
 common/kernel/timing.h  |   6 ++
 2 files changed, 225 insertions(+), 7 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 834785fbe3..370b43c65b 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -29,12 +29,17 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+namespace {
+const char *edge_name(ClockEdge edge) { return (edge == FALLING_EDGE) ? "negedge" : "posedge"; }
+} // namespace
+
 void TimingAnalyser::setup()
 {
     init_ports();
     get_cell_delays();
     topo_sort();
     setup_port_domains();
+    identify_related_domains();
     run();
 }
 
@@ -249,6 +254,7 @@ void TimingAnalyser::setup_port_domains()
                     copy_domains(port, CellPortKey(pi.net->driver), true);
             }
         }
+
         // Iterate over ports and find domain paris
         for (auto port : topological_order) {
             auto &pd = ports.at(port);
@@ -280,6 +286,174 @@ void TimingAnalyser::setup_port_domains()
     }
 }
 
+void TimingAnalyser::identify_related_domains() {
+
+    // Identify clock nets
+    pool<IdString> clock_nets;
+    for (const auto& domain : domains) {
+        clock_nets.insert(domain.key.clock);
+    }
+
+    // For each clock net identify all nets that can possibly drive it. Compute
+    // cumulative delays to each of them.
+    std::function<void(const NetInfo*, dict<IdString, delay_t>&, delay_t, int32_t)> find_net_drivers =
+        [&] (const NetInfo* ni, dict<IdString, delay_t>& drivers, delay_t delay_acc, int32_t level)
+    {
+        // Get driving cell and port
+        const CellInfo* cell = ni->driver.cell;
+        const IdString  port = ni->driver.port;
+
+        bool didGoUpstream = false;
+
+        std::string indent (level, ' ');
+
+        log("%sout %s.%s\n", indent.c_str(), cell->name.str(ctx).c_str(), port.str(ctx).c_str());
+
+        // The cell has only one port
+        if (cell->ports.size() == 1) {
+            drivers[ni->name] = delay_acc;
+            return;
+        }
+
+        // Count cell port types
+        size_t num_inp = 0;
+        size_t num_out = 0;
+        for (const auto& it : cell->ports) {
+            const auto& pi = it.second;
+            if (pi.type != PORT_IN) {
+                num_inp++;
+            } else {
+                num_out++;
+            }
+        }
+
+        // Get the driver timing class
+        int  info_count   = 0;
+        auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
+
+        // The driver must be a combinational output
+        if (timing_class != TMG_COMB_OUTPUT) {
+            drivers[ni->name] = delay_acc;
+            return;
+        }
+
+        // Recurse upstream through all input ports that have combinational
+        // paths to this driver
+        for (const auto& it : cell->ports) {
+            const auto& pi = it.second;
+
+            // Only connected inputs
+            if (pi.type != PORT_IN) {
+                continue;
+            }
+            if (pi.net == nullptr) {
+                continue;
+            }
+
+            // The input must be a combinational input
+            timing_class = ctx->getPortTimingClass(cell, pi.name, info_count);
+            if (timing_class != TMG_COMB_INPUT) {
+                continue;
+            }
+            // There must be a combinational arc
+            DelayQuad delay;
+            if (!ctx->getCellDelay(cell, pi.name, port, delay)) {
+                continue;
+            }
+
+            log("%sinp %s.%s\n", indent.c_str(), cell->name.str(ctx).c_str(), pi.name.str(ctx).c_str());
+
+            // Recurse
+            find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay(), level+1);
+            didGoUpstream = true;
+        }
+
+        // Did not propagate upstream through the cell, mark the net as driver
+        if (!didGoUpstream) {
+            log("%send %s\n", indent.c_str(), ni->name.str(ctx).c_str());
+            drivers[ni->name] = delay_acc;
+        }
+    };
+
+    // Identify possible drivers for each clock domain
+    dict<IdString, dict<IdString, delay_t>> clock_drivers;
+    for (const auto& domain : domains) {
+
+        const NetInfo* ni = ctx->nets.at(domain.key.clock).get();
+        dict<IdString, delay_t> drivers;
+        find_net_drivers(ni, drivers, 0, 0);
+
+        clock_drivers[domain.key.clock] = drivers;
+
+        log("Clock '%s' can be driven by:\n", domain.key.clock.str(ctx).c_str());
+        for (const auto& it : drivers) {
+            log(" net '%s' delay %.3fns\n", it.first.str(ctx).c_str(), ctx->getDelayNS(it.second));
+        }
+    }
+
+    // Identify related clocks
+    for (const auto& c1 : clock_drivers) {
+        for (const auto& c2 : clock_drivers) {
+
+            // Evident?
+            if (c1 == c2) {
+                continue;
+            }
+
+            // Make an intersection of the two drivers sets
+            pool<IdString> common_drivers;
+            for (const auto& it : c1.second) {
+                common_drivers.insert(it.first);
+            }
+            for (const auto& it : c2.second) {
+                common_drivers.insert(it.first);
+            }
+
+            for (auto it=common_drivers.begin(); it!=common_drivers.end();) {
+                if (!c1.second.count(*it) || !c2.second.count(*it)) {
+                    it = common_drivers.erase(it);
+                } else {
+                    ++it;
+                }
+            }
+
+            // DEBUG //
+            log("Clocks '%s' and '%s'\n", c1.first.str(ctx).c_str(), c2.first.str(ctx).c_str());
+            for (const auto& it : common_drivers) {
+
+                // TEST //
+                const NetInfo* ni = ctx->nets.at(it).get();
+                const CellInfo* cell = ni->driver.cell;
+                const IdString  port = ni->driver.port;
+
+                int  info_count;
+                auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
+                // TEST //
+
+                log(" net '%s', cell %s (%s), port %s, class%d\n", 
+                    it.str(ctx).c_str(),
+                    cell->name.str(ctx).c_str(),
+                    cell->type.str(ctx).c_str(),
+                    port.str(ctx).c_str(),
+                    int(timing_class)
+                );
+            }
+            // DEBUG //
+
+            // If there is no single driver then consider the two clocks
+            // unrelated.
+            if (common_drivers.size() != 1) {
+                continue;
+            }
+
+            // Compute delay from c1 to c2 and store it
+            auto driver = *common_drivers.begin();
+            auto delay  = c2.second.at(driver) - c1.second.at(driver);
+            clock_delays[std::make_pair(c1.first, c2.first)] = delay;
+        }
+    }
+}
+
 void TimingAnalyser::reset_times()
 {
     for (auto &port : ports) {
@@ -466,11 +640,23 @@ void TimingAnalyser::compute_slack()
         auto &pd = ports.at(p);
         for (auto &pdp : pd.domain_pairs) {
             auto &dp = domain_pairs.at(pdp.first);
+
+            // Get clock names
+            const auto& launch_clock = domains.at(dp.key.launch).key.clock;
+            const auto& capture_clock = domains.at(dp.key.capture).key.clock;
+
+            // Get clock-to-clock delay if any
+            delay_t clock_to_clock = 0;
+            auto clocks = std::make_pair(launch_clock, capture_clock);
+            if (clock_delays.count(clocks)) {
+                clock_to_clock = clock_delays.at(clocks);
+            }
+
             auto &arr = pd.arrival.at(dp.key.launch);
             auto &req = pd.required.at(dp.key.capture);
-            pdp.second.setup_slack = 0 - (arr.value.maxDelay() - req.value.minDelay());
+            pdp.second.setup_slack = 0 - (arr.value.maxDelay() - req.value.minDelay() + clock_to_clock);
             if (!setup_only)
-                pdp.second.hold_slack = arr.value.minDelay() - req.value.maxDelay();
+                pdp.second.hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
             pdp.second.max_path_length = arr.path_length + req.path_length;
             if (dp.key.launch == dp.key.capture)
                 pd.worst_setup_slack = std::min(pd.worst_setup_slack, dp.period.minDelay() + pdp.second.setup_slack);
@@ -541,10 +727,6 @@ void TimingAnalyser::print_critical_path(CellPortKey endpoint, domain_id_t domai
     }
 }
 
-namespace {
-const char *edge_name(ClockEdge edge) { return (edge == FALLING_EDGE) ? "negedge" : "posedge"; }
-} // namespace
-
 void TimingAnalyser::print_report()
 {
     for (int i = 0; i < int(domain_pairs.size()); i++) {
@@ -558,6 +740,16 @@ void TimingAnalyser::print_report()
             print_critical_path(ep, i);
         log_break();
     }
+
+    print_fmax();
+
+    for (const auto& it : clock_delays) {
+        log_info("Clock-to-clock %s -> %s: %0.02f ns\n",
+            it.first.first.str(ctx).c_str(),
+            it.first.second.str(ctx).c_str(),
+            ctx->getDelayNS(it.second)
+        );
+    }
 }
 
 domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
@@ -1216,11 +1408,15 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                   (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
     timing.walk_paths();
 
+    TimingAnalyser timingAnalyser (ctx);
+    timingAnalyser.setup();
+
     bool report_critical_paths = print_path || print_fmax || update_results;
 
     dict<IdString, CriticalPath> clock_reports;
     std::vector<CriticalPath> xclock_reports;
     dict<IdString, ClockFmax> clock_fmax;
+    dict<std::pair<IdString, IdString>, ClockFmax> xclock_fmax;
     std::set<IdString> empty_clocks; // set of clocks with no interior paths
 
     if (report_critical_paths) {
@@ -1256,12 +1452,24 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             if (a.clock == b.clock && a.clock != ctx->id("$async$"))
                 continue;
 
+            double Fmax;
+            if (a.edge == b.edge)
+                Fmax = 1000 / ctx->getDelayNS(path.second.path_delay);
+            else
+                Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
+
+            auto key = std::make_pair(a.clock, b.clock);
+            if (!xclock_fmax.count(key) || Fmax < xclock_fmax.at(key).achieved) {
+                xclock_fmax[key].achieved = Fmax;
+                xclock_fmax[key].constraint = 0.0f; // Will be filled later
+            }
+
             auto &crit_path = crit_paths.at(path.first).ports;
             xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
             xclock_reports.back().period = path.second.path_period;
         }
 
-        if (clock_reports.empty()) {
+        if (clock_reports.empty() && xclock_reports.empty()) {
             log_info("No Fmax available; no interior timing paths found in design.\n");
         }
 
@@ -1418,6 +1626,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
             print_path_report(report);
         }
+
+        log("== NEW CODE ==\n");
+        timingAnalyser.print_report();
+        log("== NEW CODE ==\n");
     }
 
     if (print_fmax) {
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index fe1bcaa84c..9562ba9347 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -92,6 +92,10 @@ struct TimingAnalyser
         return slack;
     }
 
+    auto get_clock_delays () const {
+        return clock_delays;
+    }
+
     bool setup_only = false;
     bool verbose_mode = false;
     bool have_loops = false;
@@ -103,6 +107,7 @@ struct TimingAnalyser
     void get_route_delays();
     void topo_sort();
     void setup_port_domains();
+    void identify_related_domains();
 
     void reset_times();
 
@@ -217,6 +222,7 @@ struct TimingAnalyser
     dict<ClockDomainPairKey, domain_id_t> pair_to_id;
     std::vector<PerDomain> domains;
     std::vector<PerDomainPair> domain_pairs;
+    dict<std::pair<IdString, IdString>, delay_t> clock_delays;
 
     std::vector<CellPortKey> topological_order;
 

From 60a6e8b070081492f1df0b829123c3bf08de8566 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Wed, 31 Aug 2022 14:15:33 +0200
Subject: [PATCH 182/712] Added timing check for cross-domain paths for related
 clocks

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 common/kernel/timing.cc | 108 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 104 insertions(+), 4 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 370b43c65b..0141da9311 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -1408,6 +1408,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                   (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
     timing.walk_paths();
 
+    // Use TimingAnalyser to determine clock-to-clock relations
     TimingAnalyser timingAnalyser (ctx);
     timingAnalyser.setup();
 
@@ -1626,10 +1627,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
             print_path_report(report);
         }
-
-        log("== NEW CODE ==\n");
-        timingAnalyser.print_report();
-        log("== NEW CODE ==\n");
     }
 
     if (print_fmax) {
@@ -1657,6 +1654,109 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                 log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
                                    clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
         }
+        log_break();
+
+        // All clock to clock delays
+        const auto& clock_delays = timingAnalyser.get_clock_delays();
+
+        // Clock to clock delays for xpaths
+        dict<ClockPair, delay_t> xclock_delays;
+        for (auto &report : xclock_reports) {
+            const auto& clock1_name = report.clock_pair.start.clock;
+            const auto& clock2_name = report.clock_pair.end.clock;
+
+            const auto key = std::make_pair(clock1_name, clock2_name);
+            if (clock_delays.count(key)) {
+                xclock_delays[report.clock_pair] = clock_delays.at(key);
+            }
+        }
+
+        unsigned max_width_xca = 0;
+        unsigned max_width_xcb = 0;
+        for (auto &report : xclock_reports) {
+            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
+            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(),   max_width_xcb);
+        }
+
+        // Check and report xpath delays for related clocks
+        if (!xclock_reports.empty()) {
+            for (auto &report : xclock_reports) {
+                const auto& clock_a = report.clock_pair.start.clock;
+                const auto& clock_b = report.clock_pair.end.clock;
+
+                const auto key = std::make_pair(clock_a, clock_b);
+                if (!clock_delays.count(key)) {
+                    continue;
+                }
+
+                delay_t path_delay = 0;
+                for (const auto &segment : report.segments) {
+                    path_delay += segment.delay;
+                }
+
+                // Compensate path delay for clock-to-clock delay. If the
+                // result is negative then only the latter matters. Otherwise
+                // the compensated path delay is taken.
+                auto clock_delay = clock_delays.at(key);
+                path_delay -= clock_delay;
+
+                float fmax = std::numeric_limits<float>::infinity();
+                if (path_delay < 0) {
+                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
+                } else if (path_delay > 0) {
+                    fmax = 1e3f / ctx->getDelayNS(path_delay);
+                }
+
+                // Both clocks are related so they should have the same
+                // frequency. However, they may get different constraints from
+                // user input. In case of only one constraint preset take it,
+                // otherwise get the worst case (min.)
+                float target;
+                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_a).constraint;
+                }
+                else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_b).constraint;
+                }
+                else {
+                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
+                }
+
+                bool passed = target < fmax;
+
+                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
+                auto ev_b = format_event(report.clock_pair.end,   max_width_xcb);
+
+                if (!warn_on_failure || passed)
+                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
+                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
+                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                else
+                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
+                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            }
+            log_break();
+        }
+
+        // Report clock delays for xpaths
+        if (!clock_delays.empty()) {
+            for (auto &pair : xclock_delays) {
+                auto ev_a = format_event(pair.first.start, max_width_xca);
+                auto ev_b = format_event(pair.first.end, max_width_xcb);
+
+                delay_t delay = pair.second;
+                if (pair.first.start.edge != pair.first.end.edge) {
+                    delay /= 2;
+                }
+
+                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(delay));
+            }
+
+            log_break();
+        }
+
         for (auto &eclock : empty_clocks) {
             if (eclock != ctx->id("$async$"))
                 log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));

From 1f1bae3e23bd3acb932d9287350ab2c38489a2f4 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Wed, 31 Aug 2022 14:31:24 +0200
Subject: [PATCH 183/712] Code cleanup

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 common/kernel/timing.cc | 99 +++++++++++++++--------------------------
 nexus/arch.cc           |  8 ++--
 2 files changed, 39 insertions(+), 68 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 0141da9311..b7b979fc08 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -254,7 +254,6 @@ void TimingAnalyser::setup_port_domains()
                     copy_domains(port, CellPortKey(pi.net->driver), true);
             }
         }
-
         // Iterate over ports and find domain paris
         for (auto port : topological_order) {
             auto &pd = ports.at(port);
@@ -296,8 +295,8 @@ void TimingAnalyser::identify_related_domains() {
 
     // For each clock net identify all nets that can possibly drive it. Compute
     // cumulative delays to each of them.
-    std::function<void(const NetInfo*, dict<IdString, delay_t>&, delay_t, int32_t)> find_net_drivers =
-        [&] (const NetInfo* ni, dict<IdString, delay_t>& drivers, delay_t delay_acc, int32_t level)
+    std::function<void(const NetInfo*, dict<IdString, delay_t>&, delay_t)> find_net_drivers =
+        [&] (const NetInfo* ni, dict<IdString, delay_t>& drivers, delay_t delay_acc)
     {
         // Get driving cell and port
         const CellInfo* cell = ni->driver.cell;
@@ -305,30 +304,14 @@ void TimingAnalyser::identify_related_domains() {
 
         bool didGoUpstream = false;
 
-        std::string indent (level, ' ');
-
-        log("%sout %s.%s\n", indent.c_str(), cell->name.str(ctx).c_str(), port.str(ctx).c_str());
-
         // The cell has only one port
         if (cell->ports.size() == 1) {
             drivers[ni->name] = delay_acc;
             return;
         }
 
-        // Count cell port types
-        size_t num_inp = 0;
-        size_t num_out = 0;
-        for (const auto& it : cell->ports) {
-            const auto& pi = it.second;
-            if (pi.type != PORT_IN) {
-                num_inp++;
-            } else {
-                num_out++;
-            }
-        }
-
         // Get the driver timing class
-        int  info_count   = 0;
+        int  info_count = 0;
         auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
 
         // The driver must be a combinational output
@@ -361,16 +344,13 @@ void TimingAnalyser::identify_related_domains() {
                 continue;
             }
 
-            log("%sinp %s.%s\n", indent.c_str(), cell->name.str(ctx).c_str(), pi.name.str(ctx).c_str());
-
             // Recurse
-            find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay(), level+1);
+            find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay());
             didGoUpstream = true;
         }
 
         // Did not propagate upstream through the cell, mark the net as driver
         if (!didGoUpstream) {
-            log("%send %s\n", indent.c_str(), ni->name.str(ctx).c_str());
             drivers[ni->name] = delay_acc;
         }
     };
@@ -381,21 +361,28 @@ void TimingAnalyser::identify_related_domains() {
 
         const NetInfo* ni = ctx->nets.at(domain.key.clock).get();
         dict<IdString, delay_t> drivers;
-        find_net_drivers(ni, drivers, 0, 0);
+        find_net_drivers(ni, drivers, 0);
 
         clock_drivers[domain.key.clock] = drivers;
 
-        log("Clock '%s' can be driven by:\n", domain.key.clock.str(ctx).c_str());
-        for (const auto& it : drivers) {
-            log(" net '%s' delay %.3fns\n", it.first.str(ctx).c_str(), ctx->getDelayNS(it.second));
+        if (ctx->debug) {
+            log("Clock '%s' can be driven by:\n", domain.key.clock.str(ctx).c_str());
+            for (const auto& it : drivers) {
+                const NetInfo* net = ctx->nets.at(it.first).get();
+                log(" %s.%s delay %.3fns\n",
+                    net->driver.cell->name.str(ctx).c_str(),
+                    net->driver.port.str(ctx).c_str(),
+                    ctx->getDelayNS(it.second)
+                );
+            }
         }
     }
 
-    // Identify related clocks
+    // Identify related clocks. For simplicity do it both for A->B and B->A
+    // cases.
     for (const auto& c1 : clock_drivers) {
         for (const auto& c2 : clock_drivers) {
 
-            // Evident?
             if (c1 == c2) {
                 continue;
             }
@@ -417,28 +404,25 @@ void TimingAnalyser::identify_related_domains() {
                 }
             }
 
-            // DEBUG //
-            log("Clocks '%s' and '%s'\n", c1.first.str(ctx).c_str(), c2.first.str(ctx).c_str());
-            for (const auto& it : common_drivers) {
-
-                // TEST //
-                const NetInfo* ni = ctx->nets.at(it).get();
-                const CellInfo* cell = ni->driver.cell;
-                const IdString  port = ni->driver.port;
-
-                int  info_count;
-                auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
-                // TEST //
-
-                log(" net '%s', cell %s (%s), port %s, class%d\n", 
-                    it.str(ctx).c_str(),
-                    cell->name.str(ctx).c_str(),
-                    cell->type.str(ctx).c_str(),
-                    port.str(ctx).c_str(),
-                    int(timing_class)
-                );
+            if (ctx->debug) {
+
+                log("Possible common driver(s) for clocks '%s' and '%s'\n",
+                    c1.first.str(ctx).c_str(), c2.first.str(ctx).c_str());
+
+                for (const auto& it : common_drivers) {
+    
+                    const NetInfo* ni = ctx->nets.at(it).get();
+                    const CellInfo* cell = ni->driver.cell;
+                    const IdString  port = ni->driver.port;
+    
+                    log(" net '%s', cell %s (%s), port %s\n", 
+                        it.str(ctx).c_str(),
+                        cell->name.str(ctx).c_str(),
+                        cell->type.str(ctx).c_str(),
+                        port.str(ctx).c_str()
+                    );
+                }
             }
-            // DEBUG //
 
             // If there is no single driver then consider the two clocks
             // unrelated.
@@ -1417,7 +1401,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     dict<IdString, CriticalPath> clock_reports;
     std::vector<CriticalPath> xclock_reports;
     dict<IdString, ClockFmax> clock_fmax;
-    dict<std::pair<IdString, IdString>, ClockFmax> xclock_fmax;
     std::set<IdString> empty_clocks; // set of clocks with no interior paths
 
     if (report_critical_paths) {
@@ -1453,18 +1436,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             if (a.clock == b.clock && a.clock != ctx->id("$async$"))
                 continue;
 
-            double Fmax;
-            if (a.edge == b.edge)
-                Fmax = 1000 / ctx->getDelayNS(path.second.path_delay);
-            else
-                Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
-
-            auto key = std::make_pair(a.clock, b.clock);
-            if (!xclock_fmax.count(key) || Fmax < xclock_fmax.at(key).achieved) {
-                xclock_fmax[key].achieved = Fmax;
-                xclock_fmax[key].constraint = 0.0f; // Will be filled later
-            }
-
             auto &crit_path = crit_paths.at(path.first).ports;
             xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
             xclock_reports.back().period = path.second.path_period;
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 70e3d38de3..bc00a1e98a 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -495,10 +495,10 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
     } else if (cell->type == id_DCC) {
         if (fromPort == id_CLKI && toPort == id_CLKO) {
             // TODO: Use actual DCC delays
-            delay.rise.min_delay = 1000;
-            delay.rise.max_delay = 1000;
-            delay.fall.min_delay = 1000;
-            delay.fall.max_delay = 1000;
+            delay.rise.min_delay = 1;
+            delay.rise.max_delay = 1;
+            delay.fall.min_delay = 1;
+            delay.fall.max_delay = 1;
             return true;
         }
     }

From f4230553901de30f07be5906471b219ed255cb6e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 4 Aug 2022 09:04:02 +0200
Subject: [PATCH 184/712] fabulous: Add a viaduct uarch

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/family.cmake                       |   2 +-
 generic/viaduct/fabulous/constids.inc      |  88 +++++
 generic/viaduct/fabulous/fab_cfg.h         | 102 ++++++
 generic/viaduct/fabulous/fab_defs.h        |  39 ++
 generic/viaduct/fabulous/fabric_parsing.h  | 175 +++++++++
 generic/viaduct/fabulous/fabulous.cc       | 396 +++++++++++++++++++++
 generic/viaduct/fabulous/fasm.cc           | 191 ++++++++++
 generic/viaduct/fabulous/fasm.h            |  32 ++
 generic/viaduct/fabulous/pack.cc           | 253 +++++++++++++
 generic/viaduct/fabulous/pack.h            |  32 ++
 generic/viaduct/fabulous/validity_check.cc | 201 +++++++++++
 generic/viaduct/fabulous/validity_check.h  | 127 +++++++
 12 files changed, 1637 insertions(+), 1 deletion(-)
 create mode 100644 generic/viaduct/fabulous/constids.inc
 create mode 100644 generic/viaduct/fabulous/fab_cfg.h
 create mode 100644 generic/viaduct/fabulous/fab_defs.h
 create mode 100644 generic/viaduct/fabulous/fabric_parsing.h
 create mode 100644 generic/viaduct/fabulous/fabulous.cc
 create mode 100644 generic/viaduct/fabulous/fasm.cc
 create mode 100644 generic/viaduct/fabulous/fasm.h
 create mode 100644 generic/viaduct/fabulous/pack.cc
 create mode 100644 generic/viaduct/fabulous/pack.h
 create mode 100644 generic/viaduct/fabulous/validity_check.cc
 create mode 100644 generic/viaduct/fabulous/validity_check.h

diff --git a/generic/family.cmake b/generic/family.cmake
index de4ce1afa8..b6a674f7f2 100644
--- a/generic/family.cmake
+++ b/generic/family.cmake
@@ -1,4 +1,4 @@
-set(VIADUCT_UARCHES "example" "okami")
+set(VIADUCT_UARCHES "example" "okami" "fabulous")
 foreach(uarch ${VIADUCT_UARCHES})
     aux_source_directory(${family}/viaduct/${uarch} UARCH_FILES)
     foreach(target ${family_targets})
diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
new file mode 100644
index 0000000000..c46d5e6d39
--- /dev/null
+++ b/generic/viaduct/fabulous/constids.inc
@@ -0,0 +1,88 @@
+X(FABULOUS_LC)
+X(FABULOUS_COMB)
+X(FABULOUS_FF)
+
+X(SET_NORESET)
+X(ASYNC_SR)
+X(NEG_CLK)
+X(FF)
+X(LATCH_NOFF)
+
+X(IO_1_bidirectional_frame_config_pass)
+X(InPass4_frame_config)
+X(OutPass4_frame_config)
+X(RegFile_32x4)
+X(MULADD)
+X(MUX8LUT_frame_config)
+
+X(CLK)
+X(I)
+X(T)
+X(O)
+X(Q)
+X(Ci)
+X(Co)
+
+X(X0Y0)
+
+X(REG_CLK)
+X(LUT_CLK)
+X(global_clock)
+
+X(Global_Clock)
+X(O2Q)
+
+X(WRITE_DATA)
+X(WRITE_ADDRESS)
+X(READ_DATA)
+X(READ_ADDRESS)
+X(DSP_DATA_OUT)
+X(DSP_DATA_IN)
+X(DSP_CLR)
+
+X(carry_in)
+X(carry_out)
+
+X(LUTFF)
+X(LUTFF_E)
+X(LUTFF_SR)
+X(LUTFF_SS)
+X(LUTFF_ESR)
+X(LUTFF_ESS)
+X(LUTFF_R)
+X(LUTFF_S)
+X(LUTFF_ER)
+X(LUTFF_ES)
+
+X(LUTFF_N)
+X(LUTFF_NE)
+X(LUTFF_NSR)
+X(LUTFF_NSS)
+X(LUTFF_NESR)
+X(LUTFF_NESS)
+X(LUTFF_NR)
+X(LUTFF_NS)
+X(LUTFF_NER)
+X(LUTFF_NES)
+
+X(clr)
+
+X(__disconnected)
+X(INIT)
+
+X(E)
+X(C)
+X(D)
+X(S)
+X(R)
+X(SR)
+X(EN)
+
+X(BEL)
+X(PAD)
+X(LUT1)
+
+X(BelBegin)
+X(BelEnd)
+X(GlobalClk)
+X(CFG)
diff --git a/generic/viaduct/fabulous/fab_cfg.h b/generic/viaduct/fabulous/fab_cfg.h
new file mode 100644
index 0000000000..dc487fbddd
--- /dev/null
+++ b/generic/viaduct/fabulous/fab_cfg.h
@@ -0,0 +1,102 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef FAB_CFG_H
+#define FAB_CFG_H
+
+#include "fab_defs.h"
+#include "hashlib.h"
+#include "idstring.h"
+#include "nextpnr_assertions.h"
+#include "nextpnr_namespaces.h"
+
+#include <string>
+#include <vector>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+This set of structures is designed to enumerate the different configurable options for a fabulous architecture,
+affecting the packer etc...
+*/
+
+struct ControlSetConfig
+{
+    /*
+    CLB signal routing masks for fast validity checking
+       for each unique CLK/CE/SR input to a CLB, add an entry to this vector, and set the bits to 1 for each ff that
+    signal can drive for a CLB with 8 FFs and 2 clocks split at halfway, the first entry would be 0x0F and the second
+    0xF0
+    */
+    std::vector<route_mask_t> routing = {0b11111111}; // default 1 shared between all
+    bool have_signal = true;
+    bool can_invert = false;
+};
+
+struct LogicConfig
+{
+    // ** Core CLB config
+    unsigned lc_per_clb = 8; // number of logic cells per clb
+    bool split_lc = false; // whether to represent SLICE as a single bel or separate lut+ff (latter important if ff and
+                           // lut can be used separately)
+
+    // ** LUT config
+    unsigned lut_k = 4; // base number of inputs for lookup table
+    enum LutType
+    {
+        SINGLE_LUT,
+        // ...
+    } lut_type = LutType::SINGLE_LUT; // different types of fracturable LUT structure
+
+    enum LutCascade
+    {
+        NO_CASCADE,
+        // ...
+    } lut_casc = LutCascade::NO_CASCADE; // different types of cascading between LUTs
+
+    // TODO: other features we might want to represent...
+    // TODO: fracLUT/FF/mux/carry output sharing matrices
+
+    // ** Carry config
+    enum CarryType
+    {
+        NO_CARRY,    // no carry chain
+        HA_PRE_LUT,  // half addder before LUT (classic fabulous LC)
+        PG_POST_LUT, // prop/gen logic after a fractured LUT
+        FA_POST_LUT, // full adder after a fractured LUT
+    } carry_type = CarryType::HA_PRE_LUT;
+    int carry_lut_frac = -1; // how the LUT is fractured for PG_POST_LUT/FA_POST_LUT, if the LUT fracturing is different
+                             // (or only supported) for carry modes and not in general
+
+    // ** FF config
+    unsigned ff_per_lc = 1;      // number of flipflops per logic cell
+    uint32_t dedi_ff_input = 0;  // mask of flipflops in a LC that have dedicated inputs
+    uint32_t dedi_ff_output = 0; // mask of flipflops in a LC that have dedicated outputs
+
+    ControlSetConfig clk, sr, en; // flipflop control set routing
+};
+
+struct FabricConfig
+{
+    LogicConfig clb;
+    // DSP cascading, BRAM, IP rules, IO, clocking ...
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct/fabulous/fab_defs.h b/generic/viaduct/fabulous/fab_defs.h
new file mode 100644
index 0000000000..bd026b18c0
--- /dev/null
+++ b/generic/viaduct/fabulous/fab_defs.h
@@ -0,0 +1,39 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FAB_DEFS_H
+#define FAB_DEFS_H
+
+#include <cstdint>
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+This defines some compile-time maximums for the fabulous arch
+*/
+
+static constexpr unsigned MAX_LUTK = 6; // max number of LUT inputs
+
+typedef uint64_t route_mask_t; // the width of this type defines the max number of FFs in a CLB (for defining control
+                               // set route patterns)
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct/fabulous/fabric_parsing.h b/generic/viaduct/fabulous/fabric_parsing.h
new file mode 100644
index 0000000000..3fa263ca5d
--- /dev/null
+++ b/generic/viaduct/fabulous/fabric_parsing.h
@@ -0,0 +1,175 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FABULOUS_PARSING_H
+#define FABULOUS_PARSING_H
+
+#include <iostream>
+#include <limits>
+#include <string>
+#include "idstring.h"
+#include "nextpnr_assertions.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct BaseCtx;
+
+// Lightweight NIH string_view
+struct parser_view
+{
+    char *m_ptr;
+    size_t m_length;
+    parser_view() : m_ptr(nullptr), m_length(0){};
+    explicit parser_view(std::string &str) : m_ptr(&(str[0])), m_length(str.size()){};
+    parser_view(char *ptr, size_t length) : m_ptr(ptr), m_length(length){};
+
+    static constexpr size_t npos = std::numeric_limits<size_t>::max();
+    char operator[](size_t idx)
+    {
+        NPNR_ASSERT(idx < m_length);
+        return m_ptr[idx];
+    }
+
+    size_t size() const { return m_length; }
+
+    bool empty() const { return m_length == 0; }
+
+    parser_view substr(size_t start, size_t length = npos)
+    {
+        NPNR_ASSERT(start <= m_length);
+        if (length == npos)
+            length = m_length - start;
+        NPNR_ASSERT(length <= m_length);
+        return parser_view(m_ptr + start, length);
+    }
+
+    size_t find(char tok) const
+    {
+        for (size_t i = 0; i < m_length; i++)
+            if (m_ptr[i] == tok)
+                return i;
+        return npos;
+    }
+
+    IdString to_id(const BaseCtx *ctx)
+    {
+        // This isn't really ideal, let's hope one day we can move to C++20 and have proper string_views instead :3
+        char tmp = m_ptr[m_length];
+        m_ptr[m_length] = '\0';
+        IdString id = IdString(ctx, m_ptr);
+        m_ptr[m_length] = tmp;
+        return id;
+    }
+
+    long to_int()
+    {
+        // This isn't really ideal, let's hope one day we can move to C++20 and have proper string_views instead :3
+        char tmp = m_ptr[m_length];
+        m_ptr[m_length] = '\0';
+        long l = strtol(m_ptr, nullptr, 0);
+        m_ptr[m_length] = tmp;
+        return l;
+    }
+
+    parser_view strip(const std::string &ws = " \r\n\t")
+    {
+        char *ptr = m_ptr;
+        size_t length = m_length;
+        while (length > 0) {                        // strip front
+            if (ws.find(*ptr) == std::string::npos) // not whitespace
+                break;
+            ptr++;
+            length--;
+        }
+        while (length > 0) {                                   // strip back
+            if (ws.find(ptr[length - 1]) == std::string::npos) // not whitespace
+                break;
+            length--;
+        }
+        return parser_view(ptr, length);
+    }
+
+    char back()
+    {
+        NPNR_ASSERT(m_length > 0);
+        return m_ptr[m_length - 1];
+    }
+
+    parser_view back(size_t count)
+    {
+        NPNR_ASSERT(count <= m_length);
+        return parser_view(m_ptr + (m_length - count), count);
+    }
+
+    bool starts_with(const std::string &st)
+    {
+        if (m_length < st.size())
+            return false;
+        for (size_t i = 0; i < st.length(); i++)
+            if (m_ptr[i] != st[i])
+                return false;
+        return true;
+    }
+    std::pair<parser_view, parser_view> split(char delim) const
+    {
+        size_t pos = find(delim);
+        NPNR_ASSERT(pos != npos);
+        return std::make_pair(parser_view(m_ptr, pos), parser_view(m_ptr + pos + 1, m_length - (pos + 1)));
+    }
+};
+
+struct CsvParser
+{
+    explicit CsvParser(std::istream &in) : in(in){};
+    std::istream &in;
+    std::string buf;
+    parser_view view;
+    bool fetch_next_line()
+    {
+        while (!in.eof()) {
+            std::getline(in, buf);
+            view = parser_view(buf).strip();
+            size_t end_pos = view.find('#');
+            if (end_pos != parser_view::npos)
+                view = view.substr(0, end_pos);
+            view = view.strip();
+            if (!view.empty())
+                return true;
+        }
+        return false;
+    }
+    parser_view next_field()
+    {
+        size_t next_delim = view.find(',');
+        if (next_delim == parser_view::npos) {
+            parser_view result = view.substr(0, next_delim);
+            view = parser_view();
+            return result;
+        } else {
+            parser_view result = view.substr(0, next_delim);
+            view = view.substr(next_delim + 1);
+            return result;
+        }
+    }
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
new file mode 100644
index 0000000000..e2adb8947c
--- /dev/null
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -0,0 +1,396 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "fabric_parsing.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+#include "viaduct_api.h"
+#include "viaduct_helpers.h"
+
+#include <fstream>
+
+#define GEN_INIT_CONSTIDS
+#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
+#include "viaduct_constids.h"
+
+#include "fab_cfg.h"
+#include "fab_defs.h"
+#include "fasm.h"
+#include "pack.h"
+#include "validity_check.h"
+
+#include <boost/filesystem.hpp>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct FabulousImpl : ViaductAPI
+{
+    FabulousImpl(const dict<std::string, std::string> &args)
+    {
+        for (auto a : args) {
+            if (a.first == "fasm")
+                fasm_file = a.second;
+            else
+                log_error("unrecognised fabulous option '%s'\n", a.first.c_str());
+        }
+    }
+    ~FabulousImpl(){};
+    void init(Context *ctx) override
+    {
+        init_uarch_constids(ctx);
+        ViaductAPI::init(ctx);
+        h.init(ctx);
+        fab_root = get_env_var("FAB_ROOT", ", set it to the fabulous build output or project path");
+        if (boost::filesystem::exists(fab_root + "/.FABulous"))
+            is_new_fab = true;
+        else
+            is_new_fab = false;
+        log_info("Detected FABulous %s format project.\n", is_new_fab ? "2.0" : "1.0");
+        // To consider: a faster serialised form of the device data (like bba that other arches use) so we don't have to
+        // go through the whole csv parsing malarkey each time
+        blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
+        is_new_fab ? init_bels_v2() : init_bels_v1();
+        init_pips();
+    }
+
+    void pack() override { fabulous_pack(ctx, cfg); }
+
+    void postRoute() override
+    {
+        if (!fasm_file.empty())
+            fabulous_write_fasm(ctx, cfg, fasm_file);
+    }
+
+    void prePlace() override { assign_cell_info(); }
+    bool isBelLocationValid(BelId bel) const override { return blk_trk->check_validity(bel, cfg, cell_tags); }
+
+  private:
+    FabricConfig cfg; // TODO: non-default config
+    ViaductHelpers h;
+
+    WireId global_clk_wire;
+
+    std::string fasm_file;
+
+    std::unique_ptr<BlockTracker> blk_trk;
+
+    std::string get_env_var(const std::string &name, const std::string &prompt = "")
+    {
+        const char *var = getenv(name.c_str());
+        if (var == nullptr)
+            log_error("environment variable '%s' is not set%s\n", name.c_str(), prompt.c_str());
+        return std::string(var);
+    }
+
+    std::ifstream open_data_rel(const std::string &postfix)
+    {
+        const std::string filename(fab_root + postfix);
+        std::ifstream in(filename);
+        if (!in)
+            log_error("failed to open data file '%s' (is FAB_ROOT set correctly?)\n", filename.c_str());
+        return in;
+    }
+
+    std::string fab_root;
+    bool is_new_fab;
+
+    pool<IdString> warned_beltypes;
+
+    void add_pseudo_pip(WireId src, WireId dst, IdString pip_type)
+    {
+        const auto &src_data = ctx->wire_info(src);
+        IdStringList pip_name = IdStringList::concat(ctx->getWireName(src), ctx->getWireName(dst));
+        ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(0.05), Loc(src_data.x, src_data.y, 0));
+    }
+
+    void handle_bel_ports(BelId bel, IdString tile, IdString bel_type, const std::vector<parser_view> &ports)
+    {
+        // TODO: improve the scalability here as we support more bel types
+        IdString idx = ctx->getBelName(bel)[1];
+        Loc loc = ctx->getBelLocation(bel);
+        if (bel_type == id_IO_1_bidirectional_frame_config_pass) {
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                WireId port_wire = get_wire(tile, port_id, ctx->idf("W_IO_%s", port_id.c_str(ctx)));
+                IdString pin = p.back(1).to_id(ctx);
+                ctx->addBelPin(bel, pin, port_wire, pin.in(id_I, id_T) ? PORT_IN : PORT_OUT);
+            }
+        } else if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) {
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                WireId port_wire = get_wire(tile, port_id, port_id);
+                IdString pin = p.back(2).to_id(ctx);
+                ctx->addBelPin(bel, pin, port_wire, bel_type == id_OutPass4_frame_config ? PORT_IN : PORT_OUT);
+            }
+        } else if (bel_type == id_RegFile_32x4) {
+            WireId clk_wire = get_wire(tile, id_CLK, id_REG_CLK);
+            ctx->addBelInput(bel, id_CLK, clk_wire);
+            add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                // TODO: nicer way of determining port type?
+                if (p[0] == 'D') {
+                    ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_WRITE_DATA));
+                } else if (p[0] == 'W') {
+                    ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_WRITE_ADDRESS));
+                } else if (p[1] == 'D') {
+                    ctx->addBelOutput(bel, port_id, get_wire(tile, port_id, id_READ_DATA));
+                } else {
+                    ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_READ_ADDRESS));
+                }
+            }
+        } else if (bel_type == id_MULADD) {
+            // TODO: do DSPs need a clock too like regfiles?
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                if (p[0] == 'Q') {
+                    ctx->addBelOutput(bel, port_id, get_wire(tile, port_id, id_DSP_DATA_OUT));
+                } else if (port_id == id_clr) {
+                    ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_DSP_CLR));
+                } else {
+                    ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_DSP_DATA_IN));
+                }
+            }
+        } else if (bel_type == id_MUX8LUT_frame_config) {
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                ctx->addBelPin(bel, port_id, get_wire(tile, port_id, ctx->idf("LUTMUX_%s", port_id.c_str(ctx))),
+                               p[0] == 'M' ? PORT_OUT : PORT_IN);
+            }
+        } else if (bel_type == id_FABULOUS_LC) {
+            // TODO: split LC mode, LUT permutation pseudo-switchbox, LUT thru pseudo-pips
+            WireId clk_wire = get_wire(tile, ctx->idf("L%s_CLK", idx.c_str(ctx)), id_LUT_CLK);
+            ctx->addBelInput(bel, id_CLK, clk_wire);
+            add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
+            blk_trk->set_bel_type(bel, BelFlags::BLOCK_CLB, BelFlags::FUNC_LC_COMB, loc.z);
+            for (parser_view p : ports) {
+                IdString port_id = p.to_id(ctx);
+                WireId port_wire = get_wire(tile, port_id, ctx->idf("LUT_%s", port_id.c_str(ctx)));
+                // TODO: more robust port name handling
+                if (p[3] == 'S' || p[3] == 'E' || p[3] == 'I') { // set/reset, enable, LUT input
+                    ctx->addBelInput(bel, p.substr(3).to_id(ctx), port_wire);
+                } else if (p[3] == 'O') { // LUT otuput
+                    ctx->addBelOutput(bel, p.substr(3, 1).to_id(ctx), port_wire);
+                } else if (p[3] == 'C') { // carry chain
+                    if (p[4] == 'i') {
+                        ctx->addBelInput(bel, id_Ci, port_wire);
+                    } else {
+                        NPNR_ASSERT(p[4] == 'o');
+                        ctx->addBelOutput(bel, id_Co, port_wire);
+                    }
+                } else {
+                    log_error("don't know what to do with LC port '%s'\n", port_id.c_str(ctx));
+                }
+            }
+        } else {
+            // ...
+            if (!warned_beltypes.count(bel_type) && !ports.empty()) {
+                log_warning("don't know how to handle ports for bel type '%s'\n", bel_type.c_str(ctx));
+                warned_beltypes.insert(bel_type);
+            }
+        }
+    }
+
+    void init_global_clock()
+    {
+        // TODO: how do we extend this to more complex clocking topologies?
+        BelId global_clk_bel =
+                ctx->addBel(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_Global_Clock, Loc(0, 0, 0), true, false);
+        global_clk_wire = ctx->addWire(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_CLK, 0, 0);
+        ctx->addBelOutput(global_clk_bel, id_CLK, global_clk_wire);
+    }
+
+    // TODO: this is for legacy fabulous only, the new code path can be a lot simpler
+    void init_bels_v1()
+    {
+        std::ifstream in = open_data_rel("/npnroutput/bel.txt");
+        CsvParser csv(in);
+        init_global_clock();
+        while (csv.fetch_next_line()) {
+            IdString tile = csv.next_field().to_id(ctx);
+            int bel_x = csv.next_field().substr(1).to_int();
+            int bel_y = csv.next_field().substr(1).to_int();
+            auto bel_idx = csv.next_field();
+            IdString bel_type = csv.next_field().to_id(ctx);
+            NPNR_ASSERT(bel_idx.size() == 1);
+            int bel_z = bel_idx[0] - 'A';
+            NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
+            /*
+            In the future we will need to handle optionally splitting SLICEs into separate LUT/COMB and FF bels
+            This is the preferred approach in nextpnr for arches where the LUT and FF can be used separately of
+            each other (e.g. there is a way of routing the LUT and FF outputs individually, and some extra
+            optional FF input).
+            While this isn't yet the standard fabulous SLICE, it should be considered as a future option in fabulous.
+            */
+            Loc loc(bel_x, bel_y, bel_z);
+            BelId bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type, loc, false, false);
+            std::vector<parser_view> ports;
+            parser_view port;
+            while (!(port = csv.next_field()).empty()) {
+                ports.push_back(port);
+            }
+            handle_bel_ports(bel, tile, bel_type, ports);
+        }
+        postprocess_bels();
+    }
+
+    void init_bels_v2()
+    {
+        std::ifstream in = open_data_rel("/.FABulous/bel.v2.txt");
+        CsvParser csv(in);
+        init_global_clock();
+        BelId curr_bel;
+        while (csv.fetch_next_line()) {
+            IdString cmd = csv.next_field().to_id(ctx);
+            if (cmd == id_BelBegin) {
+                IdString tile = csv.next_field().to_id(ctx);
+                auto bel_idx = csv.next_field();
+                IdString bel_type = csv.next_field().to_id(ctx);
+                NPNR_ASSERT(bel_idx.size() == 1);
+                int bel_z = bel_idx[0] - 'A';
+                NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
+                Loc loc = tile_loc(tile);
+                curr_bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type,
+                                       Loc(loc.x, loc.y, bel_z), false, false);
+            } else if (cmd.in(id_I, id_O)) {
+                IdString port = csv.next_field().to_id(ctx);
+                auto wire_name = csv.next_field().split('.');
+                WireId wire =
+                        get_wire(wire_name.first.to_id(ctx), wire_name.second.to_id(ctx), wire_name.second.to_id(ctx));
+                ctx->addBelPin(curr_bel, port, wire, cmd == id_O ? PORT_OUT : PORT_IN);
+            } else if (cmd == id_GlobalClk) {
+                IdStringList bel_name = ctx->getBelName(curr_bel);
+                WireId clk_wire = get_wire(bel_name[0], ctx->idf("%s_CLK", bel_name[1].c_str(ctx)), id_REG_CLK);
+                ctx->addBelInput(curr_bel, id_CLK, clk_wire);
+                add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
+            } else if (cmd == id_CFG) {
+                // TODO...
+            } else if (cmd == id_BelEnd) {
+                curr_bel = BelId();
+            } else if (cmd != IdString()) {
+                log_error("unsupported command %s in definition of bel %s\n", cmd.c_str(ctx),
+                          curr_bel == BelId() ? "<none>" : ctx->nameOfBel(curr_bel));
+            }
+        }
+        postprocess_bels();
+    }
+
+    void postprocess_bels()
+    {
+        // This does some post-processing on bels to make them useful for nextpnr place-and-route regardless of the code
+        // path that creates them. In the future, splitting muxes and creating split LCs would be done here, too
+        for (auto bel : ctx->getBels()) {
+            auto &data = ctx->bel_info(bel);
+            if (data.type == id_FABULOUS_LC) {
+                if (!data.pins.count(id_Q)) {
+                    // Add a Q pseudo-pin and pseudo-pip from Q to O
+                    WireId o_wire = ctx->getBelPinWire(bel, id_O);
+                    IdString q_name = ctx->idf("%s_Q", data.name[1].c_str(ctx));
+                    WireId q_wire = get_wire(data.name[0], q_name, q_name);
+                    ctx->addBelOutput(bel, id_Q, q_wire);
+                    // Pseudo-pip for FF mode
+                    add_pseudo_pip(q_wire, o_wire, id_O2Q);
+                }
+            } else if (data.type == id_IO_1_bidirectional_frame_config_pass) {
+                if (!data.pins.count(id_PAD)) {
+                    // Add a PAD pseudo-pin for the top level
+                    ctx->addBelInout(bel, id_PAD,
+                                     get_wire(data.name[0], ctx->idf("PAD_%s", data.name[1].c_str(ctx)), id_PAD));
+                }
+            }
+        }
+    }
+
+    void init_pips()
+    {
+        std::ifstream in = open_data_rel(is_new_fab ? "/.FABulous/pips.txt" : "/npnroutput/pips.txt");
+        CsvParser csv(in);
+        while (csv.fetch_next_line()) {
+            IdString src_tile = csv.next_field().to_id(ctx);
+            IdString src_port = csv.next_field().to_id(ctx);
+            IdString dst_tile = csv.next_field().to_id(ctx);
+            IdString dst_port = csv.next_field().to_id(ctx);
+            int delay = csv.next_field().to_int();
+            IdString pip_name = csv.next_field().to_id(ctx);
+            WireId src_wire = get_wire(src_tile, src_port, src_port);
+            WireId dst_wire = get_wire(dst_tile, dst_port, dst_port);
+            ctx->addPip(IdStringList::concat(src_tile, pip_name), pip_name, src_wire, dst_wire,
+                        ctx->getDelayFromNS(0.01 * delay), tile_loc(src_tile));
+        }
+    }
+
+    // Fast lookup of tile names to XY pairs
+    dict<IdString, Loc> tile2loc;
+    Loc tile_loc(IdString tile)
+    {
+        if (!tile2loc.count(tile)) {
+            std::string tile_name = tile.str(ctx);
+            parser_view view(tile_name);
+            NPNR_ASSERT(view[0] == 'X');
+            size_t ypos = view.find('Y');
+            NPNR_ASSERT(ypos != parser_view::npos);
+            int x = view.substr(1, ypos - 1).to_int();
+            int y = view.substr(ypos + 1).to_int();
+            tile2loc[tile] = Loc(x, y, 0);
+        }
+        return tile2loc.at(tile);
+    }
+
+    // Create a wire if it doesn't exist, otherwise just return it
+    WireId get_wire(IdString tile, IdString wire, IdString type)
+    {
+        // Create a wire name by using the built-in IdStringList mechanism to store a (tile, wire) pair
+        // this way we don't store a full string in memory of every concatenated wire name, reducing the memory
+        // footprint and start time significantly beyond the ~1k LUT scale
+        auto wire_name = IdStringList::concat(tile, wire);
+        auto found = ctx->wire_by_name.find(wire_name);
+        if (found != ctx->wire_by_name.end())
+            return found->second;
+        // doesn't exist
+        Loc loc = tile_loc(tile);
+        return ctx->addWire(wire_name, type, loc.x, loc.y);
+    }
+
+    CellTagger cell_tags;
+    void assign_cell_info()
+    {
+        for (auto &cell : ctx->cells) {
+            cell_tags.assign_for(ctx, cfg, cell.second.get());
+        }
+    }
+    void notifyBelChange(BelId bel, CellInfo *cell)
+    {
+        CellInfo *old = ctx->getBoundBelCell(bel);
+        blk_trk->update_bel(bel, old, cell);
+    }
+};
+
+struct FabulousArch : ViaductArch
+{
+    FabulousArch() : ViaductArch("fabulous"){};
+    std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<FabulousImpl>(args);
+    }
+} fabulousArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
new file mode 100644
index 0000000000..1405766e49
--- /dev/null
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -0,0 +1,191 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "fasm.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include <algorithm>
+#include <boost/range/adaptor/reversed.hpp>
+#include <fstream>
+
+#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
+#include "viaduct_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct FabFasmWriter
+{
+    FabFasmWriter(const Context *ctx, const FabricConfig &cfg, const std::string &filename)
+            : ctx(ctx), cfg(cfg), out(filename)
+    {
+        if (!out)
+            log_error("failed to open fasm file '%s' for writing\n", filename.c_str());
+    }
+    std::string format_name(IdStringList name)
+    {
+        std::string result;
+        for (IdString entry : name) {
+            if (!result.empty())
+                result += ".";
+            result += entry.str(ctx);
+        }
+        return result;
+    }
+    void write_pip(PipId pip)
+    {
+        auto &data = ctx->pip_info(pip);
+        if (data.type.in(id_global_clock, id_O2Q))
+            return; // pseudo-pips with no underlying bitstream bits
+        // write pip name but with '.' instead of '/' for separator
+        out << format_name(data.name) << std::endl;
+    }
+    void write_routing(const NetInfo *net)
+    {
+        std::vector<PipId> sorted_pips;
+        for (auto &w : net->wires)
+            if (w.second.pip != PipId())
+                sorted_pips.push_back(w.second.pip);
+        std::sort(sorted_pips.begin(), sorted_pips.end());
+        out << stringf("# routing for net '%s'\n", ctx->nameOf(net)) << std::endl;
+        for (auto pip : sorted_pips)
+            write_pip(pip);
+        out << std::endl;
+    }
+
+    std::string prefix;
+
+    // Write a FASM bitvector; optionally inverting the values in the process
+    void write_vector(const std::string &name, const std::vector<bool> &value, bool invert = false)
+    {
+        out << prefix << name << " = " << int(value.size()) << "'b";
+        for (auto bit : boost::adaptors::reverse(value))
+            out << ((bit ^ invert) ? '1' : '0');
+        out << std::endl;
+    }
+    // Write a FASM bitvector given an integer value
+    void write_int_vector(const std::string &name, uint64_t value, int width, bool invert = false)
+    {
+        std::vector<bool> bits(width, false);
+        for (int i = 0; i < width; i++)
+            bits[i] = (value & (1ULL << i)) != 0;
+        write_vector(name, bits, invert);
+    }
+    // Write an int vector param
+    void write_int_vector_param(const CellInfo *cell, const std::string &name, uint64_t defval, int width,
+                                bool invert = false)
+    {
+        uint64_t value = int_or_default(cell->params, ctx->id(name), defval);
+        std::vector<bool> bits(width, false);
+        for (int i = 0; i < width; i++)
+            bits[i] = (value & (1ULL << i)) != 0;
+        write_vector(stringf("%s[%d:0]", name.c_str(), width - 1), bits, invert);
+    }
+
+    void write_bool(const CellInfo *cell, const std::string &name)
+    {
+        if (bool_or_default(cell->params, ctx->id(name))) {
+            out << prefix << name << std::endl;
+        }
+    }
+
+    void write_logic(const CellInfo *lc)
+    {
+        prefix = format_name(ctx->getBelName(lc->bel)) + ".";
+        if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_COMB)) {
+            write_int_vector_param(lc, "INIT", 0U, 1U << cfg.clb.lut_k); // todo lut depermute and thru
+        }
+        if (lc->type == id_FABULOUS_LC) {
+            write_bool(lc, "FF");
+        }
+        if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_FF)) {
+            write_bool(lc, "SET_NORESET");
+            write_bool(lc, "NEG_CLK");
+            write_bool(lc, "NEG_EN");
+            write_bool(lc, "NEG_SR");
+            write_bool(lc, "ASYNC_SR");
+        }
+    }
+
+    void write_io(const CellInfo *io)
+    {
+        write_bool(io, "INPUT_USED");
+        write_bool(io, "OUTPUT_USED");
+        write_bool(io, "ENABLE_USED");
+    }
+
+    void write_generic_cell(const CellInfo *ci)
+    {
+        prefix = format_name(ctx->getBelName(ci->bel)) + ".";
+        for (auto &param : ci->params) {
+            // TODO: better parameter type auto-detection
+            if (param.second.is_string) {
+                // enum type parameter
+                out << prefix << param.first.c_str(ctx) << "." << param.second.str << std::endl;
+            } else if (param.second.str.size() == 1) {
+                // boolean type parameter
+                if (param.second.intval != 0)
+                    out << prefix << param.first.c_str(ctx) << std::endl;
+            } else {
+                // vector type parameter
+                int msb = int(param.second.str.size()) - 1;
+                out << prefix << param.first.c_str(ctx) << "[" << msb << ":0] = ";
+                for (auto bit : boost::adaptors::reverse(param.second.str))
+                    out << bit;
+                out << std::endl;
+            }
+        }
+    }
+
+    void write_cell(const CellInfo *ci)
+    {
+        out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl;
+        if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC))
+            write_logic(ci);
+        else if (ci->type == id_IO_1_bidirectional_frame_config_pass)
+            write_io(ci);
+        else
+            write_generic_cell(ci);
+        // TODO: other cell types
+        out << std::endl;
+    }
+
+    void write_fasm()
+    {
+        for (const auto &net : ctx->nets)
+            write_routing(net.second.get());
+        for (const auto &cell : ctx->cells)
+            write_cell(cell.second.get());
+    }
+
+    const Context *ctx;
+    const FabricConfig &cfg;
+    std::ofstream out;
+};
+} // namespace
+
+void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::string &filename)
+{
+    FabFasmWriter wr(ctx, cfg, filename);
+    wr.write_fasm();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/fabulous/fasm.h b/generic/viaduct/fabulous/fasm.h
new file mode 100644
index 0000000000..0f152c64cc
--- /dev/null
+++ b/generic/viaduct/fabulous/fasm.h
@@ -0,0 +1,32 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FABULOUS_FASM_H
+#define FABULOUS_FASM_H
+
+#include "fab_cfg.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::string &filename);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct/fabulous/pack.cc b/generic/viaduct/fabulous/pack.cc
new file mode 100644
index 0000000000..0273a28a59
--- /dev/null
+++ b/generic/viaduct/fabulous/pack.cc
@@ -0,0 +1,253 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "pack.h"
+#include "log.h"
+#include "util.h"
+
+#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
+#include "viaduct_constids.h"
+#include "viaduct_helpers.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct FabulousPacker
+{
+    Context *ctx;
+    const FabricConfig &cfg;
+    ViaductHelpers h;
+
+    dict<IdString, unsigned> lut_types;
+    std::vector<IdString> lut_inputs;
+
+    FabulousPacker(Context *ctx, const FabricConfig &cfg) : ctx(ctx), cfg(cfg)
+    {
+        // Set up some structures for faster lookups
+        for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
+            lut_types[ctx->idf("LUT%d", i + 1)] = i + 1;
+            lut_inputs.push_back(ctx->idf("I%d", i));
+        }
+        h.init(ctx);
+    }
+
+    void pack_luts()
+    {
+        // Pack LUTs into FABULOUS_COMB (split-LUTFF mode) or FABULOUS_LC (packed-LUTFF mode)
+        // TODO: fracturable LUT handling
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto fnd_lut = lut_types.find(ci->type);
+            if (fnd_lut == lut_types.end())
+                continue;
+            unsigned lut_n = fnd_lut->second;
+            // convert to the necessary type
+            ci->type = cfg.clb.split_lc ? id_FABULOUS_COMB : id_FABULOUS_LC;
+            // add disconnected unused inputs
+            for (unsigned i = 0; i < cfg.clb.lut_k; i++)
+                if (!ci->ports.count(lut_inputs.at(i)))
+                    ci->addInput(lut_inputs.at(i));
+            // replicate the INIT value so the unused MSBs become don't-cares
+            auto inst_init = get_or_default(ci->params, id_INIT, Property(0));
+            unsigned orig_init_len = 1U << lut_n, prim_len = 1U << cfg.clb.lut_k;
+            Property new_init(0, prim_len);
+            for (unsigned i = 0; i < prim_len; i += orig_init_len) {
+                auto chunk = inst_init.extract(0, orig_init_len);
+                for (unsigned j = 0; j < orig_init_len; j++)
+                    new_init.str.at(i + j) = chunk.str.at(j);
+            }
+            new_init.update_intval();
+            ci->params[id_INIT] = new_init;
+        }
+    }
+
+    // Two-stage flipflop packing. First convert all the random primitives into a much easier-to-handle FABULOUS_FF
+    // Then for split-LC mode, cluster it to connected LUTs; separate-LC mode, pack it into a connected or new LC
+
+    void prepare_ffs()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            const std::string &type_str = ci->type.str(ctx);
+            if (type_str.size() < 5 || type_str.substr(0, 5) != "LUTFF")
+                continue;
+            ci->type = id_FABULOUS_FF;
+            // parse config string and unify
+            size_t idx = 5;
+            if (idx < type_str.size() && type_str.at(idx) == '_')
+                ++idx;
+            // clock inversion
+            if (idx < type_str.size() && type_str.at(idx) == 'N') {
+                ci->params[id_NEG_CLK] = 1;
+                ++idx;
+            } else {
+                ci->params[id_NEG_CLK] = 0;
+            }
+            // clock enable
+            if (idx < type_str.size() && type_str.at(idx) == 'E')
+                ++idx;
+            if (ci->ports.count(id_E))
+                ci->renamePort(id_E, id_EN);
+            else
+                ci->addInput(id_EN); // autocreate emtpy enable port if enable missing or unused
+            // sr presence and type
+            std::string srt = type_str.substr(idx);
+            if (srt == "S") {
+                ci->params[id_SET_NORESET] = 1;
+                ci->params[id_ASYNC_SR] = 1;
+            } else if (srt == "R") {
+                ci->params[id_SET_NORESET] = 0;
+                ci->params[id_ASYNC_SR] = 1;
+            } else if (srt == "SS") {
+                ci->params[id_SET_NORESET] = 1;
+                ci->params[id_ASYNC_SR] = 0;
+            } else if (srt == "SR" || srt == "") {
+                ci->params[id_SET_NORESET] = 0;
+                ci->params[id_ASYNC_SR] = 0;
+            } else {
+                NPNR_ASSERT_FALSE("unhandled FF type");
+            }
+            if (ci->ports.count(id_S))
+                ci->renamePort(id_S, id_SR);
+            else if (ci->ports.count(id_R))
+                ci->renamePort(id_R, id_SR);
+            if (!ci->ports.count(id_SR))
+                ci->addInput(id_SR); // autocreate emtpy enable port if enable missing or unused
+        }
+    }
+
+    void pack_ffs()
+    {
+        pool<IdString> to_delete;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type != id_FABULOUS_FF)
+                continue;
+            NetInfo *d = ci->getPort(id_D);
+            if (!d || !d->driver.cell)
+                continue;
+            CellInfo *drv = d->driver.cell;
+            if (drv->type != (cfg.clb.split_lc ? id_FABULOUS_COMB : id_FABULOUS_LC) || d->driver.port != id_O)
+                continue;
+            if (!cfg.clb.split_lc && d->users.entries() > 1)
+                continue; // TODO: could also resolve by duplicating LUT
+            if (drv->cluster != ClusterId()) {
+                // TODO: actually we can pack these often, we just have to be more careful to check control sets
+                continue;
+            }
+            // we can pack them together
+            if (cfg.clb.split_lc) {
+                // create/modify cluster and add constraints. copy from an arch where we do this already...
+                NPNR_ASSERT_FALSE("unimplemented");
+            } else {
+                to_delete.insert(ci->name);
+                // this connection is packed inside the LC
+                ci->disconnectPort(id_D);
+                drv->disconnectPort(id_O);
+                // move other ports/params
+                ci->movePortTo(id_CLK, drv, id_CLK);
+                ci->movePortTo(id_SR, drv, id_SR);
+                ci->movePortTo(id_EN, drv, id_EN);
+                ci->movePortTo(id_O, drv, id_Q);
+                drv->params[id_NEG_CLK] = ci->params[id_NEG_CLK];
+                drv->params[id_ASYNC_SR] = ci->params[id_ASYNC_SR];
+                drv->params[id_SET_NORESET] = ci->params[id_SET_NORESET];
+                drv->params[id_FF] = 1;
+                for (auto &attr : ci->attrs)
+                    drv->attrs[attr.first] = attr.second;
+            }
+        }
+        for (auto del : to_delete)
+            ctx->cells.erase(del);
+        if (!cfg.clb.split_lc) {
+            // convert remaining ffs to their own lc
+            for (auto &cell : ctx->cells) {
+                CellInfo *ci = cell.second.get();
+                if (ci->type != id_FABULOUS_FF)
+                    continue;
+                ci->type = id_FABULOUS_LC;
+                ci->renamePort(id_D, lut_inputs.at(0));
+                ci->renamePort(id_O, id_Q);
+                // configure LUT as a thru
+                Property init(1U << cfg.clb.lut_k);
+                for (unsigned i = 0; i < (1U << cfg.clb.lut_k); i += 2) {
+                    init.str[i] = Property::S0;
+                    init.str[i + 1] = Property::S1;
+                }
+                init.update_intval();
+                ci->params[id_INIT] = init;
+                ci->params[id_FF] = 1;
+            }
+        }
+    }
+
+    void update_bel_attrs()
+    {
+        // This new arch uses the new IdStringList system with a / separator
+        // old fabulous arches used a dot separator in bel names
+        // update old attributes for maximum cross-compat
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (!ci->attrs.count(id_BEL))
+                continue;
+            std::string &bel = ci->attrs.at(id_BEL).str;
+            if (bel.find('/') != std::string::npos) // new style
+                continue;
+            size_t dot_pos = bel.find('.');
+            if (dot_pos != std::string::npos)
+                bel[dot_pos] = '/';
+        }
+    }
+
+    void handle_constants()
+    {
+        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0x3, 2)}};
+        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0, 2)}};
+        h.replace_constants(CellTypePort(id_LUT1, id_O), CellTypePort(id_LUT1, id_O), vcc_params, gnd_params);
+    }
+
+    void handle_io()
+    {
+        // As per the preferred approach for new nextpnr flows, we require IO to be inserted by Yosys
+        // pre-place-and-route, or just manually instantiated
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_IO_1_bidirectional_frame_config_pass, id_PAD),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+    }
+
+    void run()
+    {
+        update_bel_attrs();
+        handle_constants();
+        handle_io();
+        pack_luts();
+        prepare_ffs();
+        pack_ffs();
+    }
+};
+} // namespace
+
+void fabulous_pack(Context *ctx, const FabricConfig &cfg)
+{
+    FabulousPacker packer(ctx, cfg);
+    packer.run();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/fabulous/pack.h b/generic/viaduct/fabulous/pack.h
new file mode 100644
index 0000000000..0ee35e0c4f
--- /dev/null
+++ b/generic/viaduct/fabulous/pack.h
@@ -0,0 +1,32 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FABULOUS_PACK_H
+#define FABULOUS_PACK_H
+
+#include "fab_cfg.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void fabulous_pack(Context *ctx, const FabricConfig &cfg);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct/fabulous/validity_check.cc b/generic/viaduct/fabulous/validity_check.cc
new file mode 100644
index 0000000000..91dba689c6
--- /dev/null
+++ b/generic/viaduct/fabulous/validity_check.cc
@@ -0,0 +1,201 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "validity_check.h"
+#include "log.h"
+#include "util.h"
+
+#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
+#include "viaduct_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+CLBState::CLBState(const LogicConfig &cfg)
+{
+    // TODO: more than one per LC if in split-SLICE mode with fracturable LUTs
+    lc_comb = std::make_unique<CellInfo *[]>(cfg.lc_per_clb);
+    if (cfg.split_lc) {
+        ff = std::make_unique<CellInfo *[]>(cfg.lc_per_clb * cfg.ff_per_lc);
+    }
+    // TODO: mux
+}
+
+void CellTagger::assign_for(const Context *ctx, const FabricConfig &cfg, const CellInfo *ci)
+{
+    if (int(data.size()) <= ci->flat_index)
+        data.resize(ci->flat_index + 1);
+    auto &t = data.at(ci->flat_index);
+    // Use the same logic to handle both packed and split LC modes
+    if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_LC)) {
+        unsigned lut_input_count = 0;
+        for (unsigned i = 0; i < cfg.clb.lut_k; i++)
+            if (ci->getPort(ctx->idf("I%d", i)))
+                lut_input_count = i + 1;
+        t.comb.lut_inputs = SSOArray<IdString, MAX_LUTK>(lut_input_count, IdString());
+        for (unsigned i = 0; i < lut_input_count; i++) {
+            const NetInfo *sig = ci->getPort(ctx->idf("I%d", i));
+            t.comb.lut_inputs[i] = sig ? sig->name : IdString();
+        }
+        t.comb.carry_used = false; // TODO
+        t.comb.lut_out = ci->getPort(id_O);
+    }
+    if (ci->type.in(id_FABULOUS_FF, id_FABULOUS_LC)) {
+        if (ci->type == id_FABULOUS_FF || bool_or_default(ci->params, id_FF)) {
+            t.ff.ff_used = true;
+            auto get_ctrlsig = [&](IdString name) {
+                const NetInfo *sig = ci->getPort(name);
+                bool invert = sig && bool_or_default(ci->params, ctx->idf("NEG_%s", name.c_str(ctx)));
+                return ControlSig(sig ? sig->name : id___disconnected, invert);
+            };
+            t.ff.clk = get_ctrlsig(id_CLK);
+            t.ff.sr = get_ctrlsig(id_SR);
+            t.ff.en = get_ctrlsig(id_EN);
+            t.ff.async = bool_or_default(ci->params, id_ASYNC_SR);
+            t.ff.latch = bool_or_default(ci->params, id_LATCH_NOFF);
+            t.ff.d = ci->getPort(id_D);
+            t.ff.q = ci->getPort(id_Q);
+        } else {
+            t.ff.ff_used = false;
+        }
+    }
+}
+
+void BlockTracker::set_bel_type(BelId bel, BelFlags::BlockType block, BelFlags::FuncType func, uint8_t index)
+{
+    Loc loc = ctx->getBelLocation(bel);
+    if (int(tiles.size()) <= loc.y)
+        tiles.resize(loc.y + 1);
+    auto &row = tiles.at(loc.y);
+    if (int(row.size()) <= loc.x)
+        row.resize(loc.x + 1);
+    auto &tile = row.at(loc.x);
+    if (block == BelFlags::BLOCK_CLB) {
+        if (!tile.clb)
+            tile.clb = std::make_unique<CLBState>(cfg.clb);
+    }
+    if (int(bel_data.size()) <= bel.index)
+        bel_data.resize(bel.index + 1);
+    auto &flags = bel_data.at(bel.index);
+    flags.block = block;
+    flags.func = func;
+    flags.index = index;
+}
+
+void BlockTracker::update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
+{
+    if (bel.index >= int(bel_data.size()))
+        return; // some kind of bel not being tracked
+    auto flags = bel_data.at(bel.index);
+    if (flags.block == BelFlags::BLOCK_OTHER)
+        return; // no structures to update
+    Loc loc = ctx->getBelLocation(bel);
+    if (loc.y >= int(tiles.size()))
+        return; // some kind of bel not being tracked
+    const auto &row = tiles.at(loc.y);
+    if (loc.x >= int(row.size()))
+        return; // some kind of bel not being tracked
+    const auto &entry = row.at(loc.x);
+    if (flags.block == BelFlags::BLOCK_CLB) {
+        NPNR_ASSERT(entry.clb);
+        // TODO: incremental validity check updates might care about this in the future, hence keeping it in the
+        // interface for now
+        NPNR_UNUSED(old_cell);
+        if (flags.func == BelFlags::FUNC_LC_COMB)
+            entry.clb->lc_comb[flags.index] = new_cell;
+        else if (flags.func == BelFlags::FUNC_FF)
+            entry.clb->ff[flags.index] = new_cell;
+        else if (flags.func == BelFlags::FUNC_MUX)
+            entry.clb->mux[flags.index] = new_cell;
+    }
+}
+
+bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_data)
+{
+    SSOArray<ControlSig, 2> used_clk(cfg.clk.routing.size()), used_sr(cfg.sr.routing.size()),
+            used_en(cfg.en.routing.size());
+    auto check_ctrlsig = [&](unsigned idx, ControlSig actual, const ControlSetConfig &ctrl,
+                             SSOArray<ControlSig, 2> &used) {
+        // see if we have an already-matching signal available
+        for (unsigned i = 0; i < ctrl.routing.size(); i++) {
+            // doesn't route to this pin
+            if (((ctrl.routing.at(i) >> unsigned(idx)) & 0x1U) == 0)
+                continue;
+            if (used[i] == actual)
+                return true;
+        }
+        // see if we have a free slot available
+        for (unsigned i = 0; i < ctrl.routing.size(); i++) {
+            // doesn't route to this pin
+            if (((ctrl.routing.at(i) >> unsigned(idx)) & 0x1U) == 0)
+                continue;
+            if (used[i] != ControlSig())
+                continue;
+            used[i] = actual;
+            return true;
+        }
+        // no option available
+        return false;
+    };
+    for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
+        // flipflop control set checking
+        if (cfg.split_lc) {
+            NPNR_ASSERT_FALSE("unimplemented!"); // TODO
+        } else {
+            NPNR_ASSERT(cfg.ff_per_lc == 1); // split-slice mode must be used for more
+            const CellInfo *lc = lc_comb[z];
+            if (!lc)
+                continue;
+            auto &lct = cell_data.get(lc);
+            if (lct.ff.ff_used) {
+                // check shared control signals
+                if (!check_ctrlsig(z, lct.ff.clk, cfg.clk, used_clk))
+                    return false;
+                if (cfg.en.have_signal && !check_ctrlsig(z, lct.ff.en, cfg.en, used_en))
+                    return false;
+                if (cfg.sr.have_signal && !check_ctrlsig(z, lct.ff.sr, cfg.sr, used_sr))
+                    return false;
+            }
+        }
+    }
+    // TODO: other checks...
+    return true;
+}
+
+bool BlockTracker::check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data)
+{
+    if (bel.index >= int(bel_data.size()))
+        return true; // some kind of bel not being tracked
+    auto flags = bel_data.at(bel.index);
+    if (flags.block == BelFlags::BLOCK_OTHER)
+        return true; // no structures to update
+    Loc loc = ctx->getBelLocation(bel);
+    if (loc.y >= int(tiles.size()))
+        return true; // some kind of bel not being tracked
+    const auto &row = tiles.at(loc.y);
+    if (loc.x >= int(row.size()))
+        return true; // some kind of bel not being tracked
+    const auto &entry = row.at(loc.x);
+    if (flags.block == BelFlags::BLOCK_CLB) {
+        return entry.clb->check_validity(cfg.clb, cell_data);
+    } else {
+        return true;
+    }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/fabulous/validity_check.h b/generic/viaduct/fabulous/validity_check.h
new file mode 100644
index 0000000000..43291f6eec
--- /dev/null
+++ b/generic/viaduct/fabulous/validity_check.h
@@ -0,0 +1,127 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef VALIDITY_CHECKING_H
+#define VALIDITY_CHECKING_H
+
+#include "fab_cfg.h"
+#include "fab_defs.h"
+#include "sso_array.h"
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// The validity checking engine for the fabulous configurable CLB
+
+// data that we tag onto cells for fast lookup, so we aren't doing slow hash map accesses in the inner-loop-critical
+// validity checking code
+struct ControlSig
+{
+    ControlSig() : net(), invert(false){};
+    ControlSig(IdString net, bool invert) : net(net), invert(invert){};
+    IdString net;
+    bool invert;
+    bool operator==(const ControlSig &other) const { return net == other.net && invert == other.invert; }
+    bool operator!=(const ControlSig &other) const { return net != other.net || invert != other.invert; }
+};
+
+struct CellTags
+{
+    struct
+    {
+        SSOArray<IdString, MAX_LUTK> lut_inputs; // for checking fracturable LUTs
+        bool carry_used = false;
+        const NetInfo *lut_out = nullptr;
+        // ...
+    } comb; // data for LUTs, or the LUT part of combined LUT+FF cells
+    struct
+    {
+        ControlSig clk, sr, en;
+        bool ff_used = false;
+        bool async = false;
+        bool latch = false;
+        const NetInfo *d = nullptr, *q = nullptr;
+    } ff; // data for FFs, or the FF part of combined LUT+FF cells
+};
+
+// map between cell and tags, using the flat_index that viaduct defines for this purpose
+struct CellTagger
+{
+    std::vector<CellTags> data;
+    const CellTags &get(const CellInfo *ci) const { return data.at(ci->flat_index); }
+    void assign_for(const Context *ctx, const FabricConfig &cfg, const CellInfo *ci);
+};
+
+// we need to add some extra data to CLB bels to track what they do, so we can update CLBState accordingly
+struct BelFlags
+{
+    enum BlockType : uint8_t
+    {
+        BLOCK_OTHER,
+        BLOCK_CLB,
+        // ...
+    } block = BlockType::BLOCK_OTHER;
+    enum FuncType : uint8_t
+    {
+        FUNC_LC_COMB,
+        FUNC_FF,
+        FUNC_MUX,
+        FUNC_OTHER,
+    } func;
+    uint8_t index;
+    // ...
+};
+
+// state of a CLB, for fast bel->cell lookup
+// TODO: add valid/dirty tracking for incremental validity re-checking, important once we have bigger/more complex CLBs
+// (cf. xilinx/intel arches in nextpnr)
+struct CLBState
+{
+    explicit CLBState(const LogicConfig &cfg);
+    // In combined-LC mode (LC bel contains LUT and FF), this indexes the entire LC bel to cell. In separate mode, this
+    // indexes the combinational part (LUT or LUT+carry only).
+    std::unique_ptr<CellInfo *[]> lc_comb;
+    // In split-LC mode only, this maps FF bel (in CLB) index to cell
+    std::unique_ptr<CellInfo *[]> ff;
+    // If there is (a) separate mux bel(s), map them to cells
+    std::unique_ptr<CellInfo *[]> mux;
+    bool check_validity(const LogicConfig &cfg, const CellTagger &cell_data);
+};
+
+struct BlockTracker
+{
+    Context *ctx;
+    const FabricConfig &cfg;
+    std::vector<BelFlags> bel_data;
+
+    BlockTracker(Context *ctx, const FabricConfig &cfg) : ctx(ctx), cfg(cfg){};
+    void set_bel_type(BelId bel, BelFlags::BlockType block, BelFlags::FuncType func, uint8_t index);
+    void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell);
+    struct TileData
+    {
+        std::unique_ptr<CLBState> clb;
+        // ...
+    };
+    std::vector<std::vector<TileData>> tiles;
+    bool check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif

From 0a8c411692629b4748673b11f8dca8c3db7552fb Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 14 Sep 2022 09:24:49 +0200
Subject: [PATCH 185/712] ice40: Fix UltraPlus BRAM clock polarity

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/bitstream.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 3e50c06585..2e1a6d4e21 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out)
             bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W);
             int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE);
             int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE);
-            set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
-            set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
-
+            if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
+                set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r);
+                set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w);
+            } else {
+                set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
+                set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
+            }
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1);
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1);

From a72f898ff4c4237424c468044a6db9d6953b541e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 14 Sep 2022 09:28:47 +0200
Subject: [PATCH 186/712] 3rdparty: Bump vendored pybind11 version for py3.11
 support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 3rdparty/pybind11/.appveyor.yml               |    8 +-
 3rdparty/pybind11/.clang-format               |   38 +
 3rdparty/pybind11/.clang-tidy                 |   82 +-
 3rdparty/pybind11/.codespell-ignore-lines     |   24 +
 3rdparty/pybind11/.gitattributes              |    1 +
 3rdparty/pybind11/.github/CODEOWNERS          |    9 +
 3rdparty/pybind11/.github/CONTRIBUTING.md     |  103 +-
 .../.github/ISSUE_TEMPLATE/bug-report.yml     |   45 +
 .../.github/ISSUE_TEMPLATE/config.yml         |    3 +
 3rdparty/pybind11/.github/dependabot.yml      |    4 -
 .../pybind11/.github/pull_request_template.md |    7 +-
 3rdparty/pybind11/.github/workflows/ci.yml    |  688 +++--
 .../pybind11/.github/workflows/configure.yml  |   16 +-
 .../pybind11/.github/workflows/format.yml     |   23 +-
 3rdparty/pybind11/.github/workflows/pip.yml   |   39 +-
 .../pybind11/.github/workflows/upstream.yml   |  112 +
 3rdparty/pybind11/.gitignore                  |    2 +
 3rdparty/pybind11/.pre-commit-config.yaml     |  131 +-
 3rdparty/pybind11/CMakeLists.txt              |   78 +-
 3rdparty/pybind11/MANIFEST.in                 |    1 -
 3rdparty/pybind11/README.rst                  |   63 +-
 3rdparty/pybind11/docs/Doxyfile               |    4 +-
 3rdparty/pybind11/docs/_static/css/custom.css |    3 +
 .../pybind11/docs/advanced/cast/custom.rst    |    8 +-
 .../pybind11/docs/advanced/cast/eigen.rst     |    6 +-
 .../pybind11/docs/advanced/cast/overview.rst  |  181 +-
 3rdparty/pybind11/docs/advanced/cast/stl.rst  |   19 +-
 .../pybind11/docs/advanced/cast/strings.rst   |   51 +-
 3rdparty/pybind11/docs/advanced/classes.rst   |  144 +-
 3rdparty/pybind11/docs/advanced/embedding.rst |   27 +-
 .../pybind11/docs/advanced/exceptions.rst     |  132 +-
 3rdparty/pybind11/docs/advanced/functions.rst |   87 +-
 3rdparty/pybind11/docs/advanced/misc.rst      |    2 +-
 .../pybind11/docs/advanced/pycpp/numpy.rst    |   67 +-
 .../pybind11/docs/advanced/pycpp/object.rst   |   37 +-
 .../docs/advanced/pycpp/utilities.rst         |   23 +-
 .../pybind11/docs/advanced/smart_ptrs.rst     |    3 +-
 3rdparty/pybind11/docs/basics.rst             |   20 +-
 3rdparty/pybind11/docs/benchmark.py           |   33 +-
 3rdparty/pybind11/docs/changelog.rst          |  934 ++++++-
 3rdparty/pybind11/docs/classes.rst            |   59 +-
 3rdparty/pybind11/docs/compiling.rst          |   96 +-
 3rdparty/pybind11/docs/conf.py                |   40 +-
 3rdparty/pybind11/docs/faq.rst                |   52 +-
 3rdparty/pybind11/docs/installing.rst         |    4 +-
 3rdparty/pybind11/docs/limitations.rst        |   20 +-
 3rdparty/pybind11/docs/pybind11-logo.png      |  Bin 58510 -> 61034 bytes
 3rdparty/pybind11/docs/reference.rst          |   15 +-
 3rdparty/pybind11/docs/release.rst            |   80 +-
 3rdparty/pybind11/docs/requirements.txt       |   13 +-
 3rdparty/pybind11/docs/upgrade.rst            |   46 +-
 3rdparty/pybind11/include/pybind11/attr.h     |  355 ++-
 .../pybind11/include/pybind11/buffer_info.h   |  131 +-
 3rdparty/pybind11/include/pybind11/cast.h     | 2202 ++++++---------
 3rdparty/pybind11/include/pybind11/chrono.h   |  172 +-
 3rdparty/pybind11/include/pybind11/complex.h  |   31 +-
 .../pybind11/include/pybind11/detail/class.h  |  333 +--
 .../pybind11/include/pybind11/detail/common.h | 1040 ++++---
 .../pybind11/include/pybind11/detail/descr.h  |  108 +-
 .../pybind11/include/pybind11/detail/init.h   |  290 +-
 .../include/pybind11/detail/internals.h       |  447 +++-
 .../pybind11/detail/type_caster_base.h        | 1010 +++++++
 .../pybind11/include/pybind11/detail/typeid.h |   30 +-
 3rdparty/pybind11/include/pybind11/eigen.h    |  546 ++--
 3rdparty/pybind11/include/pybind11/embed.h    |  180 +-
 3rdparty/pybind11/include/pybind11/eval.h     |  112 +-
 .../pybind11/include/pybind11/functional.h    |   72 +-
 3rdparty/pybind11/include/pybind11/gil.h      |  202 ++
 3rdparty/pybind11/include/pybind11/iostream.h |  143 +-
 3rdparty/pybind11/include/pybind11/numpy.h    | 1392 ++++++----
 .../pybind11/include/pybind11/operators.h     |  246 +-
 3rdparty/pybind11/include/pybind11/options.h  |   41 +-
 3rdparty/pybind11/include/pybind11/pybind11.h | 2384 ++++++++++-------
 3rdparty/pybind11/include/pybind11/pytypes.h  | 1765 ++++++++----
 3rdparty/pybind11/include/pybind11/stl.h      |  277 +-
 .../include/pybind11/stl/filesystem.h         |  116 +
 3rdparty/pybind11/include/pybind11/stl_bind.h |  674 +++--
 3rdparty/pybind11/noxfile.py                  |  107 +
 3rdparty/pybind11/pybind11/__init__.py        |   11 +-
 3rdparty/pybind11/pybind11/__main__.py        |   18 +-
 3rdparty/pybind11/pybind11/_version.py        |    6 +-
 3rdparty/pybind11/pybind11/commands.py        |   33 +-
 3rdparty/pybind11/pybind11/setup_helpers.py   |  278 +-
 3rdparty/pybind11/pyproject.toml              |   60 +-
 3rdparty/pybind11/setup.cfg                   |   49 +-
 3rdparty/pybind11/setup.py                    |  121 +-
 3rdparty/pybind11/tests/CMakeLists.txt        |  337 ++-
 3rdparty/pybind11/tests/conftest.py           |   31 +-
 3rdparty/pybind11/tests/constructor_stats.h   |  143 +-
 .../pybind11/tests/cross_module_gil_utils.cpp |   48 +-
 ...s_module_interleaved_error_already_set.cpp |   51 +
 3rdparty/pybind11/tests/env.py                |   20 +-
 .../tests/extra_python_package/test_files.py  |  164 +-
 .../extra_setuptools/test_setuphelper.py      |   68 +-
 3rdparty/pybind11/tests/local_bindings.h      |   52 +-
 3rdparty/pybind11/tests/object.h              |  112 +-
 .../tests/pybind11_cross_module_tests.cpp     |   90 +-
 3rdparty/pybind11/tests/pybind11_tests.cpp    |   54 +-
 3rdparty/pybind11/tests/pybind11_tests.h      |   54 +-
 3rdparty/pybind11/tests/pytest.ini            |   13 +-
 3rdparty/pybind11/tests/requirements.txt      |   17 +-
 3rdparty/pybind11/tests/test_async.cpp        |    5 +-
 3rdparty/pybind11/tests/test_async.py         |    1 -
 3rdparty/pybind11/tests/test_buffers.cpp      |  134 +-
 3rdparty/pybind11/tests/test_buffers.py       |   23 +-
 .../pybind11/tests/test_builtin_casters.cpp   |  337 ++-
 .../pybind11/tests/test_builtin_casters.py    |  319 ++-
 .../pybind11/tests/test_call_policies.cpp     |   44 +-
 3rdparty/pybind11/tests/test_call_policies.py |   34 +-
 3rdparty/pybind11/tests/test_callbacks.cpp    |  181 +-
 3rdparty/pybind11/tests/test_callbacks.py     |   57 +-
 3rdparty/pybind11/tests/test_chrono.cpp       |   33 +-
 3rdparty/pybind11/tests/test_chrono.py        |   41 +-
 3rdparty/pybind11/tests/test_class.cpp        |  392 +--
 3rdparty/pybind11/tests/test_class.py         |   23 +-
 .../tests/test_cmake_build/CMakeLists.txt     |    7 +-
 .../pybind11/tests/test_cmake_build/embed.cpp |    8 +-
 .../installed_embed/CMakeLists.txt            |    6 +-
 .../installed_function/CMakeLists.txt         |    3 +-
 .../installed_target/CMakeLists.txt           |    3 +-
 .../subdirectory_embed/CMakeLists.txt         |    8 +-
 .../subdirectory_function/CMakeLists.txt      |    5 +-
 .../subdirectory_target/CMakeLists.txt        |    5 +-
 .../pybind11/tests/test_cmake_build/test.py   |    6 +-
 3rdparty/pybind11/tests/test_const_name.cpp   |   55 +
 3rdparty/pybind11/tests/test_const_name.py    |   29 +
 .../tests/test_constants_and_functions.cpp    |  116 +-
 .../tests/test_constants_and_functions.py     |   12 +-
 3rdparty/pybind11/tests/test_copy_move.cpp    |  236 +-
 3rdparty/pybind11/tests/test_copy_move.py     |   13 +-
 .../tests/test_custom_type_casters.cpp        |  174 +-
 .../tests/test_custom_type_casters.py         |   12 +-
 .../pybind11/tests/test_custom_type_setup.cpp |   41 +
 .../pybind11/tests/test_custom_type_setup.py  |   48 +
 .../pybind11/tests/test_docstring_options.cpp |   63 +-
 .../pybind11/tests/test_docstring_options.py  |    4 +-
 3rdparty/pybind11/tests/test_eigen.cpp        |  269 +-
 3rdparty/pybind11/tests/test_eigen.py         |   91 +-
 .../pybind11/tests/test_embed/CMakeLists.txt  |    8 +-
 3rdparty/pybind11/tests/test_embed/catch.cpp  |   29 +-
 .../tests/test_embed/external_module.cpp      |   11 +-
 .../tests/test_embed/test_interpreter.cpp     |  180 +-
 .../tests/test_embed/test_interpreter.py      |    8 +-
 .../tests/test_embed/test_trampoline.py       |   16 +
 3rdparty/pybind11/tests/test_enum.cpp         |  106 +-
 3rdparty/pybind11/tests/test_enum.py          |   69 +-
 3rdparty/pybind11/tests/test_eval.cpp         |   53 +-
 3rdparty/pybind11/tests/test_eval.py          |   21 +-
 3rdparty/pybind11/tests/test_eval_call.py     |    1 -
 3rdparty/pybind11/tests/test_exceptions.cpp   |  232 +-
 3rdparty/pybind11/tests/test_exceptions.h     |   13 +
 3rdparty/pybind11/tests/test_exceptions.py    |  196 +-
 .../tests/test_factory_constructors.cpp       |  323 ++-
 .../tests/test_factory_constructors.py        |   24 +-
 3rdparty/pybind11/tests/test_gil_scoped.cpp   |   49 +-
 3rdparty/pybind11/tests/test_gil_scoped.py    |    1 -
 3rdparty/pybind11/tests/test_iostream.cpp     |   95 +-
 3rdparty/pybind11/tests/test_iostream.py      |  155 +-
 .../tests/test_kwargs_and_defaults.cpp        |  282 +-
 .../tests/test_kwargs_and_defaults.py         |  123 +-
 .../pybind11/tests/test_local_bindings.cpp    |   47 +-
 .../pybind11/tests/test_local_bindings.py     |    6 +-
 .../tests/test_methods_and_attributes.cpp     |  322 ++-
 .../tests/test_methods_and_attributes.py      |   94 +-
 3rdparty/pybind11/tests/test_modules.cpp      |   72 +-
 3rdparty/pybind11/tests/test_modules.py       |   52 +-
 .../tests/test_multiple_inheritance.cpp       |  277 +-
 .../tests/test_multiple_inheritance.py        |  148 +-
 3rdparty/pybind11/tests/test_numpy_array.cpp  |  470 ++--
 3rdparty/pybind11/tests/test_numpy_array.py   |   74 +-
 3rdparty/pybind11/tests/test_numpy_dtypes.cpp |  399 ++-
 3rdparty/pybind11/tests/test_numpy_dtypes.py  |   71 +-
 .../pybind11/tests/test_numpy_vectorize.cpp   |   94 +-
 .../pybind11/tests/test_numpy_vectorize.py    |    2 +-
 3rdparty/pybind11/tests/test_opaque_types.cpp |   20 +-
 3rdparty/pybind11/tests/test_opaque_types.py  |    8 +-
 .../tests/test_operator_overloading.cpp       |  198 +-
 .../tests/test_operator_overloading.py        |   15 +-
 3rdparty/pybind11/tests/test_pickling.cpp     |  110 +-
 3rdparty/pybind11/tests/test_pickling.py      |   60 +-
 3rdparty/pybind11/tests/test_pytypes.cpp      |  671 ++++-
 3rdparty/pybind11/tests/test_pytypes.py       |  517 +++-
 .../tests/test_sequences_and_iterators.cpp    |  420 ++-
 .../tests/test_sequences_and_iterators.py     |   78 +-
 3rdparty/pybind11/tests/test_smart_ptr.cpp    |  512 ++--
 3rdparty/pybind11/tests/test_smart_ptr.py     |   29 +-
 3rdparty/pybind11/tests/test_stl.cpp          |  403 ++-
 3rdparty/pybind11/tests/test_stl.py           |  123 +-
 3rdparty/pybind11/tests/test_stl_binders.cpp  |  111 +-
 3rdparty/pybind11/tests/test_stl_binders.py   |   48 +-
 .../tests/test_tagbased_polymorphic.cpp       |  117 +-
 .../tests/test_tagbased_polymorphic.py        |    1 -
 3rdparty/pybind11/tests/test_thread.cpp       |   66 +
 3rdparty/pybind11/tests/test_thread.py        |   42 +
 3rdparty/pybind11/tests/test_union.py         |    1 -
 .../pybind11/tests/test_virtual_functions.cpp |  341 ++-
 .../pybind11/tests/test_virtual_functions.py  |   78 +-
 .../pybind11/tests/valgrind-numpy-scipy.supp  |  140 +
 3rdparty/pybind11/tests/valgrind-python.supp  |  117 +
 3rdparty/pybind11/tools/FindCatch.cmake       |    2 +
 3rdparty/pybind11/tools/FindEigen3.cmake      |    3 +
 .../pybind11/tools/FindPythonLibsNew.cmake    |   58 +-
 3rdparty/pybind11/tools/JoinPaths.cmake       |   23 +
 3rdparty/pybind11/tools/check-style.sh        |    6 +-
 .../codespell_ignore_lines_from_errors.py     |   35 +
 3rdparty/pybind11/tools/libsize.py            |    6 +-
 3rdparty/pybind11/tools/make_changelog.py     |   63 +
 3rdparty/pybind11/tools/pybind11.pc.in        |    7 +
 3rdparty/pybind11/tools/pybind11Common.cmake  |   86 +-
 .../pybind11/tools/pybind11Config.cmake.in    |   19 +-
 .../pybind11/tools/pybind11NewTools.cmake     |  104 +-
 3rdparty/pybind11/tools/pybind11Tools.cmake   |  125 +-
 3rdparty/pybind11/tools/setup_global.py.in    |   14 +-
 3rdparty/pybind11/tools/setup_main.py.in      |   12 +-
 214 files changed, 21644 insertions(+), 10025 deletions(-)
 create mode 100644 3rdparty/pybind11/.clang-format
 create mode 100644 3rdparty/pybind11/.codespell-ignore-lines
 create mode 100644 3rdparty/pybind11/.gitattributes
 create mode 100644 3rdparty/pybind11/.github/CODEOWNERS
 create mode 100644 3rdparty/pybind11/.github/ISSUE_TEMPLATE/bug-report.yml
 create mode 100644 3rdparty/pybind11/.github/workflows/upstream.yml
 create mode 100644 3rdparty/pybind11/docs/_static/css/custom.css
 create mode 100644 3rdparty/pybind11/include/pybind11/detail/type_caster_base.h
 create mode 100644 3rdparty/pybind11/include/pybind11/gil.h
 create mode 100644 3rdparty/pybind11/include/pybind11/stl/filesystem.h
 create mode 100644 3rdparty/pybind11/noxfile.py
 create mode 100644 3rdparty/pybind11/tests/cross_module_interleaved_error_already_set.cpp
 create mode 100644 3rdparty/pybind11/tests/test_const_name.cpp
 create mode 100644 3rdparty/pybind11/tests/test_const_name.py
 create mode 100644 3rdparty/pybind11/tests/test_custom_type_setup.cpp
 create mode 100644 3rdparty/pybind11/tests/test_custom_type_setup.py
 create mode 100644 3rdparty/pybind11/tests/test_embed/test_trampoline.py
 create mode 100644 3rdparty/pybind11/tests/test_exceptions.h
 create mode 100644 3rdparty/pybind11/tests/test_thread.cpp
 create mode 100644 3rdparty/pybind11/tests/test_thread.py
 create mode 100644 3rdparty/pybind11/tests/valgrind-numpy-scipy.supp
 create mode 100644 3rdparty/pybind11/tests/valgrind-python.supp
 create mode 100644 3rdparty/pybind11/tools/JoinPaths.cmake
 create mode 100644 3rdparty/pybind11/tools/codespell_ignore_lines_from_errors.py
 create mode 100755 3rdparty/pybind11/tools/make_changelog.py
 create mode 100644 3rdparty/pybind11/tools/pybind11.pc.in

diff --git a/3rdparty/pybind11/.appveyor.yml b/3rdparty/pybind11/.appveyor.yml
index 149a8a3dc9..360760ac8d 100644
--- a/3rdparty/pybind11/.appveyor.yml
+++ b/3rdparty/pybind11/.appveyor.yml
@@ -1,6 +1,6 @@
 version: 1.0.{build}
 image:
-- Visual Studio 2015
+- Visual Studio 2017
 test: off
 skip_branch_with_pr: true
 build:
@@ -11,15 +11,13 @@ environment:
   matrix:
   - PYTHON: 36
     CONFIG: Debug
-  - PYTHON: 27
-    CONFIG: Debug
 install:
 - ps: |
-    $env:CMAKE_GENERATOR = "Visual Studio 14 2015"
+    $env:CMAKE_GENERATOR = "Visual Studio 15 2017"
     if ($env:PLATFORM -eq "x64") { $env:PYTHON = "$env:PYTHON-x64" }
     $env:PATH = "C:\Python$env:PYTHON\;C:\Python$env:PYTHON\Scripts\;$env:PATH"
     python -W ignore -m pip install --upgrade pip wheel
-    python -W ignore -m pip install pytest numpy --no-warn-script-location
+    python -W ignore -m pip install pytest numpy --no-warn-script-location pytest-timeout
 - ps: |
     Start-FileDownload 'https://gitlab.com/libeigen/eigen/-/archive/3.3.7/eigen-3.3.7.zip'
     7z x eigen-3.3.7.zip -y > $null
diff --git a/3rdparty/pybind11/.clang-format b/3rdparty/pybind11/.clang-format
new file mode 100644
index 0000000000..b477a16037
--- /dev/null
+++ b/3rdparty/pybind11/.clang-format
@@ -0,0 +1,38 @@
+---
+# See all possible options and defaults with:
+# clang-format --style=llvm --dump-config
+BasedOnStyle: LLVM
+AccessModifierOffset: -4
+AllowShortLambdasOnASingleLine: true
+AlwaysBreakTemplateDeclarations: Yes
+BinPackArguments: false
+BinPackParameters: false
+BreakBeforeBinaryOperators: All
+BreakConstructorInitializers: BeforeColon
+ColumnLimit: 99
+CommentPragmas: 'NOLINT:.*|^ IWYU pragma:'
+IncludeBlocks: Regroup
+IndentCaseLabels: true
+IndentPPDirectives: AfterHash
+IndentWidth: 4
+Language: Cpp
+SpaceAfterCStyleCast: true
+Standard: Cpp11
+StatementMacros: ['PyObject_HEAD']
+TabWidth: 4
+IncludeCategories:
+  - Regex:           '<pybind11/.*'
+    Priority:        -1
+  - Regex:           'pybind11.h"$'
+    Priority:        1
+  - Regex:           '^".*/?detail/'
+    Priority:        1
+    SortPriority:    2
+  - Regex:           '^"'
+    Priority:        1
+    SortPriority:    3
+  - Regex:           '<[[:alnum:]._]+>'
+    Priority:        4
+  - Regex:           '.*'
+    Priority:        5
+...
diff --git a/3rdparty/pybind11/.clang-tidy b/3rdparty/pybind11/.clang-tidy
index e29d929897..23018386c1 100644
--- a/3rdparty/pybind11/.clang-tidy
+++ b/3rdparty/pybind11/.clang-tidy
@@ -1,13 +1,77 @@
 FormatStyle: file
 
-Checks: '
-llvm-namespace-comment,
-modernize-use-override,
-readability-container-size-empty,
-modernize-use-using,
-modernize-use-equals-default,
-modernize-use-auto,
-modernize-use-emplace,
-'
+Checks: |
+  *bugprone*,
+  *performance*,
+  clang-analyzer-optin.cplusplus.VirtualCall,
+  clang-analyzer-optin.performance.Padding,
+  cppcoreguidelines-init-variables,
+  cppcoreguidelines-prefer-member-initializer,
+  cppcoreguidelines-pro-type-static-cast-downcast,
+  cppcoreguidelines-slicing,
+  google-explicit-constructor,
+  llvm-namespace-comment,
+  misc-definitions-in-headers,
+  misc-misplaced-const,
+  misc-non-copyable-objects,
+  misc-static-assert,
+  misc-throw-by-value-catch-by-reference,
+  misc-uniqueptr-reset-release,
+  misc-unused-parameters,
+  modernize-avoid-bind,
+  modernize-loop-convert,
+  modernize-make-shared,
+  modernize-redundant-void-arg,
+  modernize-replace-auto-ptr,
+  modernize-replace-disallow-copy-and-assign-macro,
+  modernize-replace-random-shuffle,
+  modernize-shrink-to-fit,
+  modernize-use-auto,
+  modernize-use-bool-literals,
+  modernize-use-default-member-init,
+  modernize-use-emplace,
+  modernize-use-equals-default,
+  modernize-use-equals-delete,
+  modernize-use-noexcept,
+  modernize-use-nullptr,
+  modernize-use-override,
+  modernize-use-using,
+  readability-avoid-const-params-in-decls,
+  readability-braces-around-statements,
+  readability-const-return-type,
+  readability-container-size-empty,
+  readability-delete-null-pointer,
+  readability-else-after-return,
+  readability-implicit-bool-conversion,
+  readability-inconsistent-declaration-parameter-name,
+  readability-make-member-function-const,
+  readability-misplaced-array-index,
+  readability-non-const-parameter,
+  readability-qualified-auto,
+  readability-redundant-function-ptr-dereference,
+  readability-redundant-smartptr-get,
+  readability-redundant-string-cstr,
+  readability-simplify-subscript-expr,
+  readability-static-accessed-through-instance,
+  readability-static-definition-in-anonymous-namespace,
+  readability-string-compare,
+  readability-suspicious-call-argument,
+  readability-uniqueptr-delete-release,
+  -bugprone-easily-swappable-parameters,
+  -bugprone-exception-escape,
+  -bugprone-reserved-identifier,
+  -bugprone-unused-raii,
+
+CheckOptions:
+- key:             modernize-use-equals-default.IgnoreMacros
+  value:           false
+- key:             performance-for-range-copy.WarnOnAllAutoCopies
+  value:           true
+- key:             performance-inefficient-string-concatenation.StrictMode
+  value:           true
+- key:             performance-unnecessary-value-param.AllowedTypes
+  value:           'exception_ptr$;'
+- key:             readability-implicit-bool-conversion.AllowPointerConditions
+  value:           true
 
 HeaderFilterRegex: 'pybind11/.*h'
diff --git a/3rdparty/pybind11/.codespell-ignore-lines b/3rdparty/pybind11/.codespell-ignore-lines
new file mode 100644
index 0000000000..2a01d63ebb
--- /dev/null
+++ b/3rdparty/pybind11/.codespell-ignore-lines
@@ -0,0 +1,24 @@
+template <op_id id, op_type ot, typename L = undefined_t, typename R = undefined_t>
+    template <typename ThisT>
+        auto &this_ = static_cast<ThisT &>(*this);
+                if (load_impl<ThisT>(temp, false)) {
+        ssize_t nd = 0;
+        auto trivial = broadcast(buffers, nd, shape);
+        auto ndim = (size_t) nd;
+    int nd;
+    ssize_t ndim() const { return detail::array_proxy(m_ptr)->nd; }
+        using op = op_impl<id, ot, Base, L_type, R_type>;
+template <op_id id, op_type ot, typename L, typename R>
+    template <detail::op_id id, detail::op_type ot, typename L, typename R, typename... Extra>
+    class_ &def(const detail::op_<id, ot, L, R> &op, const Extra &...extra) {
+    class_ &def_cast(const detail::op_<id, ot, L, R> &op, const Extra &...extra) {
+@pytest.mark.parametrize("access", ["ro", "rw", "static_ro", "static_rw"])
+struct IntStruct {
+    explicit IntStruct(int v) : value(v){};
+    ~IntStruct() { value = -value; }
+    IntStruct(const IntStruct &) = default;
+    IntStruct &operator=(const IntStruct &) = default;
+    py::class_<IntStruct>(m, "IntStruct").def(py::init([](const int i) { return IntStruct(i); }));
+    py::implicitly_convertible<int, IntStruct>();
+    m.def("test", [](int expected, const IntStruct &in) {
+        [](int expected, const IntStruct &in) {
diff --git a/3rdparty/pybind11/.gitattributes b/3rdparty/pybind11/.gitattributes
new file mode 100644
index 0000000000..d611e1496d
--- /dev/null
+++ b/3rdparty/pybind11/.gitattributes
@@ -0,0 +1 @@
+docs/*.svg binary
diff --git a/3rdparty/pybind11/.github/CODEOWNERS b/3rdparty/pybind11/.github/CODEOWNERS
new file mode 100644
index 0000000000..4e2c66902e
--- /dev/null
+++ b/3rdparty/pybind11/.github/CODEOWNERS
@@ -0,0 +1,9 @@
+*.cmake @henryiii
+CMakeLists.txt @henryiii
+*.yml @henryiii
+*.yaml @henryiii
+/tools/ @henryiii
+/pybind11/ @henryiii
+noxfile.py @henryiii
+.clang-format @henryiii
+.clang-tidy @henryiii
diff --git a/3rdparty/pybind11/.github/CONTRIBUTING.md b/3rdparty/pybind11/.github/CONTRIBUTING.md
index 4ced21baaa..00b1fea4cf 100644
--- a/3rdparty/pybind11/.github/CONTRIBUTING.md
+++ b/3rdparty/pybind11/.github/CONTRIBUTING.md
@@ -53,6 +53,33 @@ derivative works thereof, in binary and source code form.
 
 ## Development of pybind11
 
+### Quick setup
+
+To setup a quick development environment, use [`nox`](https://nox.thea.codes).
+This will allow you to do some common tasks with minimal setup effort, but will
+take more time to run and be less flexible than a full development environment.
+If you use [`pipx run nox`](https://pipx.pypa.io), you don't even need to
+install `nox`. Examples:
+
+```bash
+# List all available sessions
+nox -l
+
+# Run linters
+nox -s lint
+
+# Run tests on Python 3.9
+nox -s tests-3.9
+
+# Build and preview docs
+nox -s docs -- serve
+
+# Build SDists and wheels
+nox -s build
+```
+
+### Full setup
+
 To setup an ideal development environment, run the following commands on a
 system with CMake 3.14+:
 
@@ -66,11 +93,10 @@ cmake --build build -j4
 
 Tips:
 
-* You can use `virtualenv` (from PyPI) instead of `venv` (which is Python 3
-  only).
+* You can use `virtualenv` (faster, from PyPI) instead of `venv`.
 * You can select any name for your environment folder; if it contains "env" it
   will be ignored by git.
-* If you don’t have CMake 3.14+, just add “cmake” to the pip install command.
+* If you don't have CMake 3.14+, just add "cmake" to the pip install command.
 * You can use `-DPYBIND11_FINDPYTHON=ON` to use FindPython on CMake 3.12+
 * In classic mode, you may need to set `-DPYTHON_EXECUTABLE=/path/to/python`.
   FindPython uses `-DPython_ROOT_DIR=/path/to` or
@@ -78,7 +104,7 @@ Tips:
 
 ### Configuration options
 
-In CMake, configuration options are given with “-D”. Options are stored in the
+In CMake, configuration options are given with "-D". Options are stored in the
 build directory, in the `CMakeCache.txt` file, so they are remembered for each
 build directory. Two selections are special - the generator, given with `-G`,
 and the compiler, which is selected based on environment variables `CXX` and
@@ -88,12 +114,12 @@ after the initial run.
 The valid options are:
 
 * `-DCMAKE_BUILD_TYPE`: Release, Debug, MinSizeRel, RelWithDebInfo
-* `-DPYBIND11_FINDPYTHON=ON`: Use CMake 3.12+’s FindPython instead of the
+* `-DPYBIND11_FINDPYTHON=ON`: Use CMake 3.12+'s FindPython instead of the
   classic, deprecated, custom FindPythonLibs
 * `-DPYBIND11_NOPYTHON=ON`: Disable all Python searching (disables tests)
 * `-DBUILD_TESTING=ON`: Enable the tests
 * `-DDOWNLOAD_CATCH=ON`: Download catch to build the C++ tests
-* `-DOWNLOAD_EIGEN=ON`: Download Eigen for the NumPy tests
+* `-DDOWNLOAD_EIGEN=ON`: Download Eigen for the NumPy tests
 * `-DPYBIND11_INSTALL=ON/OFF`: Enable the install target (on by default for the
   master project)
 * `-DUSE_PYTHON_INSTALL_DIR=ON`: Try to install into the python dir
@@ -126,13 +152,26 @@ cmake --build build --target check
 `--target` can be spelled `-t` in CMake 3.15+. You can also run individual
 tests with these targets:
 
-* `pytest`: Python tests only
+* `pytest`: Python tests only, using the
+[pytest](https://docs.pytest.org/en/stable/) framework
 * `cpptest`: C++ tests only
 * `test_cmake_build`: Install / subdirectory tests
 
 If you want to build just a subset of tests, use
-`-DPYBIND11_TEST_OVERRIDE="test_callbacks.cpp;test_pickling.cpp"`. If this is
-empty, all tests will be built.
+`-DPYBIND11_TEST_OVERRIDE="test_callbacks;test_pickling"`. If this is
+empty, all tests will be built. Tests are specified without an extension if they need both a .py and
+.cpp file.
+
+You may also pass flags to the `pytest` target by editing `tests/pytest.ini` or
+by using the `PYTEST_ADDOPTS` environment variable
+(see [`pytest` docs](https://docs.pytest.org/en/2.7.3/customize.html#adding-default-options)). As an example:
+
+```bash
+env PYTEST_ADDOPTS="--capture=no --exitfirst" \
+    cmake --build build --target pytest
+# Or using abbreviated flags
+env PYTEST_ADDOPTS="-s -x" cmake --build build --target pytest
+```
 
 ### Formatting
 
@@ -164,18 +203,46 @@ name, pre-commit):
 pre-commit install
 ```
 
+### Clang-Format
+
+As of v2.6.2, pybind11 ships with a [`clang-format`][clang-format]
+configuration file at the top level of the repo (the filename is
+`.clang-format`). Currently, formatting is NOT applied automatically, but
+manually using `clang-format` for newly developed files is highly encouraged.
+To check if a file needs formatting:
+
+```bash
+clang-format -style=file --dry-run some.cpp
+```
+
+The output will show things to be fixed, if any. To actually format the file:
+
+```bash
+clang-format -style=file -i some.cpp
+```
+
+Note that the `-style-file` option searches the parent directories for the
+`.clang-format` file, i.e. the commands above can be run in any subdirectory
+of the pybind11 repo.
+
 ### Clang-Tidy
 
-To run Clang tidy, the following recipe should work. Files will be modified in
-place, so you can use git to monitor the changes.
+[`clang-tidy`][clang-tidy] performs deeper static code analyses and is
+more complex to run, compared to `clang-format`, but support for `clang-tidy`
+is built into the pybind11 CMake configuration. To run `clang-tidy`, the
+following recipe should work. Run the `docker` command from the top-level
+directory inside your pybind11 git clone. Files will be modified in place,
+so you can use git to monitor the changes.
 
 ```bash
-docker run --rm -v $PWD:/pybind11 -it silkeh/clang:10
-apt-get update && apt-get install python3-dev python3-pytest
-cmake -S pybind11/ -B build -DCMAKE_CXX_CLANG_TIDY="$(which clang-tidy);-fix"
-cmake --build build
+docker run --rm -v $PWD:/mounted_pybind11 -it silkeh/clang:13
+apt-get update && apt-get install -y python3-dev python3-pytest
+cmake -S /mounted_pybind11/ -B build -DCMAKE_CXX_CLANG_TIDY="$(which clang-tidy);--use-color" -DDOWNLOAD_EIGEN=ON -DDOWNLOAD_CATCH=ON -DCMAKE_CXX_STANDARD=17
+cmake --build build -j 2
 ```
 
+You can add `--fix` to the options list if you want.
+
 ### Include what you use
 
 To run include what you use, install (`brew install include-what-you-use` on
@@ -186,12 +253,12 @@ cmake -S . -B build-iwyu -DCMAKE_CXX_INCLUDE_WHAT_YOU_USE=$(which include-what-y
 cmake --build build
 ```
 
-The report is sent to stderr; you can pip it into a file if you wish.
+The report is sent to stderr; you can pipe it into a file if you wish.
 
 ### Build recipes
 
 This builds with the Intel compiler (assuming it is in your path, along with a
-recent CMake and Python 3):
+recent CMake and Python):
 
 ```bash
 python3 -m venv venv
@@ -313,6 +380,8 @@ if you really want to.
 
 
 [pre-commit]: https://pre-commit.com
+[clang-format]: https://clang.llvm.org/docs/ClangFormat.html
+[clang-tidy]: https://clang.llvm.org/extra/clang-tidy/
 [pybind11.readthedocs.org]: http://pybind11.readthedocs.org/en/latest
 [issue tracker]: https://github.com/pybind/pybind11/issues
 [gitter]: https://gitter.im/pybind/Lobby
diff --git a/3rdparty/pybind11/.github/ISSUE_TEMPLATE/bug-report.yml b/3rdparty/pybind11/.github/ISSUE_TEMPLATE/bug-report.yml
new file mode 100644
index 0000000000..bd6a9a8e22
--- /dev/null
+++ b/3rdparty/pybind11/.github/ISSUE_TEMPLATE/bug-report.yml
@@ -0,0 +1,45 @@
+name: Bug Report
+description: File an issue about a bug
+title: "[BUG]: "
+labels: [triage]
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Maintainers will only make a best effort to triage PRs. Please do your best to make the issue as easy to act on as possible, and only open if clearly a problem with pybind11 (ask first if unsure).
+  - type: checkboxes
+    id: steps
+    attributes:
+      label: Required prerequisites
+      description: Make sure you've completed the following steps before submitting your issue -- thank you!
+      options:
+        - label: Make sure you've read the [documentation](https://pybind11.readthedocs.io). Your issue may be addressed there.
+          required: true
+        - label: Search the [issue tracker](https://github.com/pybind/pybind11/issues) and [Discussions](https:/pybind/pybind11/discussions) to verify that this hasn't already been reported. +1 or comment there if it has.
+          required: true
+        - label: Consider asking first in the [Gitter chat room](https://gitter.im/pybind/Lobby) or in a [Discussion](https:/pybind/pybind11/discussions/new).
+          required: false
+
+  - type: textarea
+    id: description
+    attributes:
+      label: Problem description
+      placeholder: >-
+        Provide a short description, state the expected behavior and what
+        actually happens. Include relevant information like what version of
+        pybind11 you are using, what system you are on, and any useful commands
+        / output.
+    validations:
+      required: true
+
+  - type: textarea
+    id: code
+    attributes:
+      label: Reproducible example code
+      placeholder: >-
+        The code should be minimal, have no external dependencies, isolate the
+        function(s) that cause breakage. Submit matched and complete C++ and
+        Python snippets that can be easily compiled and run to diagnose the
+        issue. If possible, make a PR with a new, failing test to give us a
+        starting point to work on!
+      render: text
diff --git a/3rdparty/pybind11/.github/ISSUE_TEMPLATE/config.yml b/3rdparty/pybind11/.github/ISSUE_TEMPLATE/config.yml
index 20e743136f..27f9a80441 100644
--- a/3rdparty/pybind11/.github/ISSUE_TEMPLATE/config.yml
+++ b/3rdparty/pybind11/.github/ISSUE_TEMPLATE/config.yml
@@ -1,5 +1,8 @@
 blank_issues_enabled: false
 contact_links:
+  - name: Ask a question
+    url: https://github.com/pybind/pybind11/discussions/new
+    about: Please ask and answer questions here, or propose new ideas.
   - name: Gitter room
     url: https://gitter.im/pybind/Lobby
     about: A room for discussing pybind11 with an active community
diff --git a/3rdparty/pybind11/.github/dependabot.yml b/3rdparty/pybind11/.github/dependabot.yml
index c1eac3c443..2c7d170839 100644
--- a/3rdparty/pybind11/.github/dependabot.yml
+++ b/3rdparty/pybind11/.github/dependabot.yml
@@ -5,7 +5,3 @@ updates:
     directory: "/"
     schedule:
       interval: "daily"
-    ignore:
-      # Offical actions have moving tags like v1
-      # that are used, so they don't need updates here
-      - dependency-name: "actions/*"
diff --git a/3rdparty/pybind11/.github/pull_request_template.md b/3rdparty/pybind11/.github/pull_request_template.md
index 5570f6f28b..54b7f5100d 100644
--- a/3rdparty/pybind11/.github/pull_request_template.md
+++ b/3rdparty/pybind11/.github/pull_request_template.md
@@ -1,3 +1,7 @@
+<!--
+Title (above): please place [branch_name] at the beginning if you are targeting a branch other than master. *Do not target stable*.
+It is recommended to use conventional commit format, see conventionalcommits.org, but not required.
+-->
 ## Description
 
 <!-- Include relevant issues or PRs here, describe what changed and why -->
@@ -5,7 +9,8 @@
 
 ## Suggested changelog entry:
 
-<!-- fill in the below block with the expected RestructuredText entry (delete if no entry needed) -->
+<!-- Fill in the below block with the expected RestructuredText entry. Delete if no entry needed;
+     but do not delete header or rst block if an entry is needed! Will be collected via a script. -->
 
 ```rst
 
diff --git a/3rdparty/pybind11/.github/workflows/ci.yml b/3rdparty/pybind11/.github/workflows/ci.yml
index 73424f92da..213c690050 100644
--- a/3rdparty/pybind11/.github/workflows/ci.yml
+++ b/3rdparty/pybind11/.github/workflows/ci.yml
@@ -9,6 +9,15 @@ on:
       - stable
       - v*
 
+concurrency:
+  group: test-${{ github.ref }}
+  cancel-in-progress: true
+
+env:
+  PIP_ONLY_BINARY: numpy
+  FORCE_COLOR: 3
+  PYTEST_TIMEOUT: 300
+
 jobs:
   # This is the "main" test suite, which tests a large number of different
   # versions of default compilers and Python versions in GitHub Actions.
@@ -16,74 +25,66 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        runs-on: [ubuntu-latest, windows-latest, macos-latest]
+        runs-on: [ubuntu-latest, windows-2022, macos-latest]
         python:
-        - 2.7
-        - 3.5
-        - 3.6
-        - 3.7
-        - 3.8
-        - 3.9
-        # - 3.10.0-alpha.1 - need next release for pybind11 fix
-        - pypy2
-        - pypy3
+        - '3.6'
+        - '3.9'
+        - '3.10'
+        - '3.11-dev'
+        - 'pypy-3.7'
+        - 'pypy-3.8'
+        - 'pypy-3.9'
 
         # Items in here will either be added to the build matrix (if not
         # present), or add new keys to an existing matrix element if all the
         # existing keys match.
         #
-        # We support three optional keys: args (both build), args1 (first
-        # build), and args2 (second build).
+        # We support an optional key: args, for cmake args
         include:
           # Just add a key
           - runs-on: ubuntu-latest
-            python: 3.6
+            python: '3.6'
             args: >
               -DPYBIND11_FINDPYTHON=ON
-          - runs-on: windows-latest
-            python: 3.6
+              -DCMAKE_CXX_FLAGS="-D_=1"
+          - runs-on: ubuntu-latest
+            python: 'pypy-3.8'
             args: >
               -DPYBIND11_FINDPYTHON=ON
-          - runs-on: ubuntu-latest
-            python: 3.8
+          - runs-on: windows-2019
+            python: '3.6'
             args: >
               -DPYBIND11_FINDPYTHON=ON
-
-        # These items will be removed from the build matrix, keys must match.
-        exclude:
-            # Currently 32bit only, and we build 64bit
-          - runs-on: windows-latest
-            python: pypy2
-          - runs-on: windows-latest
-            python: pypy3
-
-          # Let's drop a few macOS runs since that tends to be 2.7 or 3.8+
-          - runs-on: macos-latest
-            python: 3.6
-          - runs-on: macos-latest
-            python: 3.7
+          # Inject a couple Windows 2019 runs
+          - runs-on: windows-2019
+            python: '3.9'
 
     name: "🐍 ${{ matrix.python }} • ${{ matrix.runs-on }} • x64 ${{ matrix.args }}"
     runs-on: ${{ matrix.runs-on }}
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Setup Python ${{ matrix.python }}
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
       with:
         python-version: ${{ matrix.python }}
 
-    - name: Setup Boost (Windows / Linux latest)
-      shell: bash
-      run: echo "BOOST_ROOT=$BOOST_ROOT_1_72_0" >> $GITHUB_ENV
+    - name: Setup Boost (Linux)
+      # Can't use boost + define _
+      if: runner.os == 'Linux' && matrix.python != '3.6'
+      run: sudo apt-get install libboost-dev
+
+    - name: Setup Boost (macOS)
+      if: runner.os == 'macOS'
+      run: brew install boost
 
     - name: Update CMake
-      uses: jwlawson/actions-setup-cmake@v1.4
+      uses: jwlawson/actions-setup-cmake@v1.12
 
     - name: Cache wheels
       if: runner.os == 'macOS'
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       with:
         # This path is specific to macOS - we really only need it for PyPy NumPy wheels
         # See https://github.com/actions/cache/blob/master/examples.md#python---pip
@@ -93,7 +94,8 @@ jobs:
         key: ${{ runner.os }}-pip-${{ matrix.python }}-x64-${{ hashFiles('tests/requirements.txt') }}
 
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt --prefer-binary
+      run: |
+        python -m pip install -r tests/requirements.txt
 
     - name: Setup annotations on Linux
       if: runner.os == 'Linux'
@@ -117,7 +119,7 @@ jobs:
 
     - name: C++11 tests
       # TODO: Figure out how to load the DLL on Python 3.8+
-      if: "!(runner.os == 'Windows' && (matrix.python == 3.8 || matrix.python == 3.9))"
+      if: "!(runner.os == 'Windows' && (matrix.python == 3.8 || matrix.python == 3.9 || matrix.python == '3.10' || matrix.python == '3.11-dev' || matrix.python == 'pypy-3.8'))"
       run: cmake --build .  --target cpptest -j 2
 
     - name: Interface test C++11
@@ -127,7 +129,7 @@ jobs:
       run: git clean -fdx
 
     # Second build - C++17 mode and in a build directory
-    - name: Configure ${{ matrix.args2 }}
+    - name: Configure C++17
       run: >
         cmake -S . -B build2
         -DPYBIND11_WERROR=ON
@@ -135,7 +137,6 @@ jobs:
         -DDOWNLOAD_EIGEN=ON
         -DCMAKE_CXX_STANDARD=17
         ${{ matrix.args }}
-        ${{ matrix.args2 }}
 
     - name: Build
       run: cmake --build build2 -j 2
@@ -145,32 +146,117 @@ jobs:
 
     - name: C++ tests
       # TODO: Figure out how to load the DLL on Python 3.8+
-      if: "!(runner.os == 'Windows' && (matrix.python == 3.8 || matrix.python == 3.9))"
+      if: "!(runner.os == 'Windows' && (matrix.python == 3.8 || matrix.python == 3.9 || matrix.python == '3.10' || matrix.python == '3.11-dev' || matrix.python == 'pypy-3.8'))"
       run: cmake --build build2 --target cpptest
 
-    - name: Interface test
-      run: cmake --build build2 --target test_cmake_build
+    # Third build - C++17 mode with unstable ABI
+    - name: Configure (unstable ABI)
+      run: >
+        cmake -S . -B build3
+        -DPYBIND11_WERROR=ON
+        -DDOWNLOAD_CATCH=ON
+        -DDOWNLOAD_EIGEN=ON
+        -DCMAKE_CXX_STANDARD=17
+        -DPYBIND11_INTERNALS_VERSION=10000000
+        "-DPYBIND11_TEST_OVERRIDE=test_call_policies.cpp;test_gil_scoped.cpp;test_thread.cpp"
+        ${{ matrix.args }}
 
-    # Eventually Microsoft might have an action for setting up
-    # MSVC, but for now, this action works:
-    - name: Prepare compiler environment for Windows 🐍 2.7
-      if: matrix.python == 2.7 && runner.os == 'Windows'
-      uses: ilammy/msvc-dev-cmd@v1
-      with:
-        arch: x64
+    - name: Build (unstable ABI)
+      run: cmake --build build3 -j 2
 
-    # This makes two environment variables available in the following step(s)
-    - name: Set Windows 🐍 2.7 environment variables
-      if: matrix.python == 2.7 && runner.os == 'Windows'
-      shell: bash
-      run: |
-        echo "DISTUTILS_USE_SDK=1" >> $GITHUB_ENV
-        echo "MSSdk=1" >> $GITHUB_ENV
+    - name: Python tests (unstable ABI)
+      run: cmake --build build3 --target pytest
+
+    - name: Interface test
+      run: cmake --build build2 --target test_cmake_build
 
     # This makes sure the setup_helpers module can build packages using
     # setuptools
     - name: Setuptools helpers test
       run: pytest tests/extra_setuptools
+      if: "!(matrix.runs-on == 'windows-2022')"
+
+
+  deadsnakes:
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+        # TODO: Fails on 3.10, investigate
+        - python-version: "3.9"
+          python-debug: true
+          valgrind: true
+        - python-version: "3.11-dev"
+          python-debug: false
+
+    name: "🐍 ${{ matrix.python-version }}${{ matrix.python-debug && '-dbg' || '' }} (deadsnakes)${{ matrix.valgrind && ' • Valgrind' || '' }} • x64"
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Setup Python ${{ matrix.python-version }} (deadsnakes)
+      uses: deadsnakes/action@v2.1.1
+      with:
+        python-version: ${{ matrix.python-version }}
+        debug: ${{ matrix.python-debug }}
+
+    - name: Update CMake
+      uses: jwlawson/actions-setup-cmake@v1.12
+
+    - name: Valgrind cache
+      if: matrix.valgrind
+      uses: actions/cache@v3
+      id: cache-valgrind
+      with:
+        path: valgrind
+        key: 3.16.1 # Valgrind version
+
+    - name: Compile Valgrind
+      if: matrix.valgrind && steps.cache-valgrind.outputs.cache-hit != 'true'
+      run: |
+        VALGRIND_VERSION=3.16.1
+        curl https://sourceware.org/pub/valgrind/valgrind-$VALGRIND_VERSION.tar.bz2 -o - | tar xj
+        mv valgrind-$VALGRIND_VERSION valgrind
+        cd valgrind
+        ./configure
+        make -j 2 > /dev/null
+
+    - name: Install Valgrind
+      if: matrix.valgrind
+      working-directory: valgrind
+      run: |
+        sudo make install
+        sudo apt-get update
+        sudo apt-get install libc6-dbg  # Needed by Valgrind
+
+    - name: Prepare env
+      run: |
+        python -m pip install -r tests/requirements.txt
+
+    - name: Configure
+      env:
+        SETUPTOOLS_USE_DISTUTILS: stdlib
+      run: >
+        cmake -S . -B build
+        -DCMAKE_BUILD_TYPE=Debug
+        -DPYBIND11_WERROR=ON
+        -DDOWNLOAD_CATCH=ON
+        -DDOWNLOAD_EIGEN=ON
+        -DCMAKE_CXX_STANDARD=17
+
+    - name: Build
+      run: cmake --build build -j 2
+
+    - name: Python tests
+      run: cmake --build build --target pytest
+
+    - name: C++ tests
+      run: cmake --build build --target cpptest
+
+    - name: Run Valgrind on Python tests
+      if: matrix.valgrind
+      run: cmake --build build --target memcheck
 
 
   # Testing on clang using the excellent silkeh clang docker images
@@ -195,12 +281,20 @@ jobs:
             std: 20
           - clang: 10
             std: 17
+          - clang: 11
+            std: 20
+          - clang: 12
+            std: 20
+          - clang: 13
+            std: 20
+          - clang: 14
+            std: 20
 
     name: "🐍 3 • Clang ${{ matrix.clang }} • C++${{ matrix.std }} • x64"
     container: "silkeh/clang:${{ matrix.clang }}"
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Add wget and python3
       run: apt-get update && apt-get install -y python3-dev python3-numpy python3-pytest libeigen3-dev
@@ -230,11 +324,11 @@ jobs:
   # Testing NVCC; forces sources to behave like .cu files
   cuda:
     runs-on: ubuntu-latest
-    name: "🐍 3.8 • CUDA 11 • Ubuntu 20.04"
-    container: nvidia/cuda:11.0-devel-ubuntu20.04
+    name: "🐍 3.8 • CUDA 11.2 • Ubuntu 20.04"
+    container: nvidia/cuda:11.2.2-devel-ubuntu20.04
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     # tzdata will try to ask for the timezone, so set the DEBIAN_FRONTEND
     - name: Install 🐍 3
@@ -250,70 +344,74 @@ jobs:
       run: cmake --build build --target pytest
 
 
-  # Testing CentOS 8 + PGI compilers
-  centos-nvhpc8:
-    runs-on: ubuntu-latest
-    name: "🐍 3 • CentOS8 / PGI 20.7 • x64"
-    container: centos:8
-
-    steps:
-    - uses: actions/checkout@v2
-
-    - name: Add Python 3 and a few requirements
-      run: yum update -y && yum install -y git python3-devel python3-numpy python3-pytest make environment-modules
-
-    - name: Install CMake with pip
-      run: |
-        python3 -m pip install --upgrade pip
-        python3 -m pip install cmake --prefer-binary
-
-    - name: Install NVidia HPC SDK
-      run: yum -y install https://developer.download.nvidia.com/hpc-sdk/nvhpc-20-7-20.7-1.x86_64.rpm https://developer.download.nvidia.com/hpc-sdk/nvhpc-2020-20.7-1.x86_64.rpm
-
-    - name: Configure
-      shell: bash
-      run: |
-        source /etc/profile.d/modules.sh
-        module load /opt/nvidia/hpc_sdk/modulefiles/nvhpc/20.7
-        cmake -S . -B build -DDOWNLOAD_CATCH=ON -DCMAKE_CXX_STANDARD=14 -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)")
-
-    - name: Build
-      run: cmake --build build -j 2 --verbose
-
-    - name: Python tests
-      run: cmake --build build --target pytest
-
-    - name: C++ tests
-      run: cmake --build build --target cpptest
-
-    - name: Interface test
-      run: cmake --build build --target test_cmake_build
+# TODO: Internal compiler error - report to NVidia
+#  # Testing CentOS 8 + PGI compilers
+#  centos-nvhpc8:
+#    runs-on: ubuntu-latest
+#    name: "🐍 3 • CentOS8 / PGI 20.11 • x64"
+#    container: centos:8
+#
+#    steps:
+#    - uses: actions/checkout@v3
+#
+#    - name: Add Python 3 and a few requirements
+#      run: yum update -y && yum install -y git python3-devel python3-numpy python3-pytest make environment-modules
+#
+#    - name: Install CMake with pip
+#      run: |
+#        python3 -m pip install --upgrade pip
+#        python3 -m pip install cmake --prefer-binary
+#
+#    - name: Install NVidia HPC SDK
+#      run: >
+#        yum -y install
+#        https://developer.download.nvidia.com/hpc-sdk/20.11/nvhpc-20-11-20.11-1.x86_64.rpm
+#        https://developer.download.nvidia.com/hpc-sdk/20.11/nvhpc-2020-20.11-1.x86_64.rpm
+#
+#    - name: Configure
+#      shell: bash
+#      run: |
+#        source /etc/profile.d/modules.sh
+#        module load /opt/nvidia/hpc_sdk/modulefiles/nvhpc/20.11
+#        cmake -S . -B build -DDOWNLOAD_CATCH=ON -DCMAKE_CXX_STANDARD=14 -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)")
+#
+#    - name: Build
+#      run: cmake --build build -j 2 --verbose
+#
+#    - name: Python tests
+#      run: cmake --build build --target pytest
+#
+#    - name: C++ tests
+#      run: cmake --build build --target cpptest
+#
+#    - name: Interface test
+#      run: cmake --build build --target test_cmake_build
 
 
   # Testing on CentOS 7 + PGI compilers, which seems to require more workarounds
   centos-nvhpc7:
     runs-on: ubuntu-latest
-    name: "🐍 3 • CentOS7 / PGI 20.9 • x64"
+    name: "🐍 3 • CentOS7 / PGI 22.3 • x64"
     container: centos:7
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Add Python 3 and a few requirements
-      run: yum update -y && yum install -y epel-release && yum install -y git python3-devel make environment-modules cmake3
+      run: yum update -y && yum install -y epel-release && yum install -y git python3-devel make environment-modules cmake3 yum-utils
 
     - name: Install NVidia HPC SDK
-      run:  yum -y install https://developer.download.nvidia.com/hpc-sdk/20.9/nvhpc-20-9-20.9-1.x86_64.rpm https://developer.download.nvidia.com/hpc-sdk/20.9/nvhpc-2020-20.9-1.x86_64.rpm
+      run: yum-config-manager --add-repo https://developer.download.nvidia.com/hpc-sdk/rhel/nvhpc.repo && yum -y install nvhpc-22.3
 
     # On CentOS 7, we have to filter a few tests (compiler internal error)
-    # and allow deeper templete recursion (not needed on CentOS 8 with a newer
+    # and allow deeper template recursion (not needed on CentOS 8 with a newer
     # standard library). On some systems, you many need further workarounds:
     # https://github.com/pybind/pybind11/pull/2475
     - name: Configure
       shell: bash
       run: |
         source /etc/profile.d/modules.sh
-        module load /opt/nvidia/hpc_sdk/modulefiles/nvhpc/20.9
+        module load /opt/nvidia/hpc_sdk/modulefiles/nvhpc/22.3
         cmake3 -S . -B build -DDOWNLOAD_CATCH=ON \
                             -DCMAKE_CXX_STANDARD=11 \
                             -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)") \
@@ -338,26 +436,27 @@ jobs:
     - name: Interface test
       run: cmake3 --build build --target test_cmake_build
 
+
   # Testing on GCC using the GCC docker images (only recent images supported)
   gcc:
     runs-on: ubuntu-latest
     strategy:
       fail-fast: false
       matrix:
-        gcc:
-          - 7
-          - latest
-        std:
-          - 11
         include:
-          - gcc: 10
-            std: 20
+          - { gcc: 7, std: 11 }
+          - { gcc: 7, std: 17 }
+          - { gcc: 8, std: 14 }
+          - { gcc: 8, std: 17 }
+          - { gcc: 10, std: 17 }
+          - { gcc: 11, std: 20 }
+          - { gcc: 12, std: 20 }
 
     name: "🐍 3 • GCC ${{ matrix.gcc }} • C++${{ matrix.std }}• x64"
     container: "gcc:${{ matrix.gcc }}"
 
     steps:
-    - uses: actions/checkout@v1
+    - uses: actions/checkout@v3
 
     - name: Add Python 3
       run: apt-get update; apt-get install -y python3-dev python3-numpy python3-pytest python3-pip libeigen3-dev
@@ -365,10 +464,8 @@ jobs:
     - name: Update pip
       run: python3 -m pip install --upgrade pip
 
-    - name: Setup CMake 3.18
-      uses: jwlawson/actions-setup-cmake@v1.4
-      with:
-        cmake-version: 3.18
+    - name: Update CMake
+      uses: jwlawson/actions-setup-cmake@v1.12
 
     - name: Configure
       shell: bash
@@ -392,6 +489,103 @@ jobs:
       run: cmake --build build --target test_cmake_build
 
 
+  # Testing on ICC using the oneAPI apt repo
+  icc:
+    runs-on: ubuntu-20.04
+    strategy:
+      fail-fast: false
+
+    name: "🐍 3 • ICC latest • x64"
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Add apt repo
+      run: |
+        sudo apt-get update
+        sudo apt-get install -y wget build-essential pkg-config cmake ca-certificates gnupg
+        wget https://apt.repos.intel.com/intel-gpg-keys/GPG-PUB-KEY-INTEL-SW-PRODUCTS-2023.PUB
+        sudo apt-key add GPG-PUB-KEY-INTEL-SW-PRODUCTS-2023.PUB
+        echo "deb https://apt.repos.intel.com/oneapi all main" | sudo tee /etc/apt/sources.list.d/oneAPI.list
+
+    - name: Add ICC & Python 3
+      run: sudo apt-get update; sudo apt-get install -y intel-oneapi-compiler-dpcpp-cpp-and-cpp-classic cmake python3-dev python3-numpy python3-pytest python3-pip
+
+    - name: Update pip
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        python3 -m pip install --upgrade pip
+
+    - name: Install dependencies
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        python3 -m pip install -r tests/requirements.txt
+
+    - name: Configure C++11
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake -S . -B build-11     \
+        -DPYBIND11_WERROR=ON    \
+        -DDOWNLOAD_CATCH=ON     \
+        -DDOWNLOAD_EIGEN=OFF    \
+        -DCMAKE_CXX_STANDARD=11             \
+        -DCMAKE_CXX_COMPILER=$(which icpc)  \
+        -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)")
+
+    - name: Build C++11
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-11 -j 2 -v
+
+    - name: Python tests C++11
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        sudo service apport stop
+        cmake --build build-11 --target check
+
+    - name: C++ tests C++11
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-11 --target cpptest
+
+    - name: Interface test C++11
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-11 --target test_cmake_build
+
+    - name: Configure C++17
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake -S . -B build-17     \
+        -DPYBIND11_WERROR=ON    \
+        -DDOWNLOAD_CATCH=ON     \
+        -DDOWNLOAD_EIGEN=OFF    \
+        -DCMAKE_CXX_STANDARD=17             \
+        -DCMAKE_CXX_COMPILER=$(which icpc)  \
+        -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)")
+
+    - name: Build C++17
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-17 -j 2 -v
+
+    - name: Python tests C++17
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        sudo service apport stop
+        cmake --build build-17 --target check
+
+    - name: C++ tests C++17
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-17 --target cpptest
+
+    - name: Interface test C++17
+      run: |
+        set +e; source /opt/intel/oneapi/setvars.sh; set -e
+        cmake --build build-17 --target test_cmake_build
+
+
   # Testing on CentOS (manylinux uses a centos base, and this is an easy way
   # to get GCC 4.8, which is the manylinux1 compiler).
   centos:
@@ -399,29 +593,37 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        centos:
-          - 7  # GCC 4.8
-          - 8
+        container:
+          - "centos:7"  # GCC 4.8
+          - "almalinux:8"
+          - "almalinux:9"
 
-    name: "🐍 3 • CentOS ${{ matrix.centos }} • x64"
-    container: "centos:${{ matrix.centos }}"
+    name: "🐍 3 • ${{ matrix.container }} • x64"
+    container: "${{ matrix.container }}"
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
-    - name: Add Python 3
+    - name: Add Python 3 (RHEL 7)
+      if: matrix.container == 'centos:7'
       run: yum update -y && yum install -y python3-devel gcc-c++ make git
 
+    - name: Add Python 3 (RHEL 8+)
+      if: matrix.container != 'centos:7'
+      run: dnf update -y && dnf install -y python3-devel gcc-c++ make git
+
     - name: Update pip
       run: python3 -m pip install --upgrade pip
 
     - name: Install dependencies
-      run: python3 -m pip install cmake -r tests/requirements.txt --prefer-binary
+      run: |
+        python3 -m pip install cmake -r tests/requirements.txt
 
     - name: Configure
       shell: bash
       run: >
         cmake -S . -B build
+        -DCMAKE_BUILD_TYPE=MinSizeRel
         -DPYBIND11_WERROR=ON
         -DDOWNLOAD_CATCH=ON
         -DDOWNLOAD_EIGEN=ON
@@ -443,18 +645,18 @@ jobs:
 
   # This tests an "install" with the CMake tools
   install-classic:
-    name: "🐍 3.5 • Debian • x86 •  Install"
+    name: "🐍 3.7 • Debian • x86 •  Install"
     runs-on: ubuntu-latest
-    container: i386/debian:stretch
+    container: i386/debian:buster
 
     steps:
-    - uses: actions/checkout@v1
+    - uses: actions/checkout@v1  # Required to run inside docker
 
     - name: Install requirements
       run: |
         apt-get update
         apt-get install -y git make cmake g++ libeigen3-dev python3-dev python3-pip
-        pip3 install "pytest==3.1.*"
+        pip3 install "pytest==6.*"
 
     - name: Configure for install
       run: >
@@ -479,33 +681,32 @@ jobs:
         -DPYTHON_EXECUTABLE=$(python3 -c "import sys; print(sys.executable)")
       working-directory: /build-tests
 
-    - name: Run tests
+    - name: Python tests
       run: make pytest -j 2
       working-directory: /build-tests
 
 
   # This verifies that the documentation is not horribly broken, and does a
-  # basic sanity check on the SDist.
+  # basic validation check on the SDist.
   doxygen:
     name: "Documentation build test"
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
-    - uses: actions/setup-python@v2
+    - uses: actions/setup-python@v4
+      with:
+        python-version: "3.x"
 
     - name: Install Doxygen
       run: sudo apt-get install -y doxygen librsvg2-bin # Changed to rsvg-convert in 20.04
 
-    - name: Install docs & setup requirements
-      run: python3 -m pip install -r docs/requirements.txt
-
     - name: Build docs
-      run: python3 -m sphinx -W -b html docs docs/.build
+      run: pipx run nox -s docs
 
     - name: Make SDist
-      run: python3 setup.py sdist
+      run: pipx run nox -s build -- --sdist
 
     - run: git status --ignored
 
@@ -517,7 +718,7 @@ jobs:
     - name: Compare Dists (headers only)
       working-directory: include
       run: |
-        python3 -m pip install --user -U ../dist/*
+        python3 -m pip install --user -U ../dist/*.tar.gz
         installed=$(python3 -c "import pybind11; print(pybind11.get_include() + '/pybind11')")
         diff -rq $installed ./pybind11
 
@@ -526,42 +727,40 @@ jobs:
       fail-fast: false
       matrix:
         python:
-        - 3.5
         - 3.6
         - 3.7
         - 3.8
         - 3.9
-        - pypy3
-        # TODO: fix hang on pypy2
 
         include:
           - python: 3.9
-            args: -DCMAKE_CXX_STANDARD=20 -DDOWNLOAD_EIGEN=OFF
+            args: -DCMAKE_CXX_STANDARD=20
           - python: 3.8
             args: -DCMAKE_CXX_STANDARD=17
 
     name: "🐍 ${{ matrix.python }} • MSVC 2019 • x86 ${{ matrix.args }}"
-    runs-on: windows-latest
+    runs-on: windows-2019
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Setup Python ${{ matrix.python }}
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
       with:
         python-version: ${{ matrix.python }}
         architecture: x86
 
     - name: Update CMake
-      uses: jwlawson/actions-setup-cmake@v1.4
+      uses: jwlawson/actions-setup-cmake@v1.12
 
     - name: Prepare MSVC
-      uses: ilammy/msvc-dev-cmd@v1
+      uses: ilammy/msvc-dev-cmd@v1.11.0
       with:
         arch: x86
 
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt --prefer-binary
+      run: |
+        python -m pip install -r tests/requirements.txt
 
     # First build - C++11 mode and inplace
     - name: Configure ${{ matrix.args }}
@@ -575,102 +774,189 @@ jobs:
     - name: Build C++11
       run: cmake --build build -j 2
 
-    - name: Run tests
+    - name: Python tests
       run: cmake --build build -t pytest
 
-  win32-msvc2015:
-    name: "🐍 ${{ matrix.python }} • MSVC 2015 • x64"
-    runs-on: windows-latest
+  win32-debug:
     strategy:
       fail-fast: false
       matrix:
         python:
-          - 2.7
-          - 3.6
-          - 3.7
-          # todo: check/cpptest does not support 3.8+ yet
+        - 3.8
+        - 3.9
+
+        include:
+          - python: 3.9
+            args: -DCMAKE_CXX_STANDARD=20
+          - python: 3.8
+            args: -DCMAKE_CXX_STANDARD=17
+
+    name: "🐍 ${{ matrix.python }} • MSVC 2019 (Debug) • x86 ${{ matrix.args }}"
+    runs-on: windows-2019
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
-    - name: Setup 🐍 ${{ matrix.python }}
-      uses: actions/setup-python@v2
+    - name: Setup Python ${{ matrix.python }}
+      uses: actions/setup-python@v4
       with:
         python-version: ${{ matrix.python }}
+        architecture: x86
 
     - name: Update CMake
-      uses: jwlawson/actions-setup-cmake@v1.4
+      uses: jwlawson/actions-setup-cmake@v1.12
 
     - name: Prepare MSVC
-      uses: ilammy/msvc-dev-cmd@v1
+      uses: ilammy/msvc-dev-cmd@v1.11.0
       with:
-        toolset: 14.0
+        arch: x86
 
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt --prefer-binary
+      run: |
+        python -m pip install -r tests/requirements.txt
 
     # First build - C++11 mode and inplace
-    - name: Configure
+    - name: Configure ${{ matrix.args }}
       run: >
         cmake -S . -B build
-        -G "Visual Studio 14 2015" -A x64
+        -G "Visual Studio 16 2019" -A Win32
+        -DCMAKE_BUILD_TYPE=Debug
         -DPYBIND11_WERROR=ON
         -DDOWNLOAD_CATCH=ON
         -DDOWNLOAD_EIGEN=ON
+        ${{ matrix.args }}
+    - name: Build C++11
+      run: cmake --build build --config Debug -j 2
 
-    - name: Build C++14
-      run: cmake --build build -j 2
-
-    - name: Run all checks
-      run: cmake --build build -t check
+    - name: Python tests
+      run: cmake --build build --config Debug -t pytest
 
 
-  win32-msvc2017:
-    name: "🐍 ${{ matrix.python }} • MSVC 2017 • x64"
-    runs-on: windows-2016
+  windows-2022:
     strategy:
       fail-fast: false
       matrix:
         python:
-          - 2.7
-          - 3.5
-          - 3.7
-        std:
-          - 14
+        - 3.9
 
-        include:
-          - python: 2.7
-            std: 17
-            args: >
-              -DCMAKE_CXX_FLAGS="/permissive- /EHsc /GR"
+    name: "🐍 ${{ matrix.python }} • MSVC 2022 C++20 • x64"
+    runs-on: windows-2022
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
-    - name: Setup 🐍 ${{ matrix.python }}
-      uses: actions/setup-python@v2
+    - name: Setup Python ${{ matrix.python }}
+      uses: actions/setup-python@v4
       with:
         python-version: ${{ matrix.python }}
 
-    - name: Update CMake
-      uses: jwlawson/actions-setup-cmake@v1.4
-
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt --prefer-binary
+      run: |
+        python3 -m pip install -r tests/requirements.txt
 
-    # First build - C++11 mode and inplace
-    - name: Configure
+    - name: Update CMake
+      uses: jwlawson/actions-setup-cmake@v1.12
+
+    - name: Configure C++20
       run: >
         cmake -S . -B build
-        -G "Visual Studio 15 2017" -A x64
         -DPYBIND11_WERROR=ON
         -DDOWNLOAD_CATCH=ON
         -DDOWNLOAD_EIGEN=ON
-        -DCMAKE_CXX_STANDARD=${{ matrix.std }}
-        ${{ matrix.args }}
+        -DCMAKE_CXX_STANDARD=20
 
-    - name: Build ${{ matrix.std }}
+    - name: Build C++20
       run: cmake --build build -j 2
 
-    - name: Run all checks
-      run: cmake --build build -t check
+    - name: Python tests
+      run: cmake --build build --target pytest
+
+    - name: C++20 tests
+      run: cmake --build build --target cpptest -j 2
+
+    - name: Interface test C++20
+      run: cmake --build build --target test_cmake_build
+
+  mingw:
+    name: "🐍 3 • windows-latest • ${{ matrix.sys }}"
+    runs-on: windows-latest
+    defaults:
+      run:
+        shell: msys2 {0}
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - { sys: mingw64, env: x86_64 }
+          - { sys: mingw32, env: i686 }
+    steps:
+    - uses: msys2/setup-msys2@v2
+      with:
+        msystem: ${{matrix.sys}}
+        install: >-
+          git
+          mingw-w64-${{matrix.env}}-gcc
+          mingw-w64-${{matrix.env}}-python-pip
+          mingw-w64-${{matrix.env}}-python-numpy
+          mingw-w64-${{matrix.env}}-python-scipy
+          mingw-w64-${{matrix.env}}-cmake
+          mingw-w64-${{matrix.env}}-make
+          mingw-w64-${{matrix.env}}-python-pytest
+          mingw-w64-${{matrix.env}}-eigen3
+          mingw-w64-${{matrix.env}}-boost
+          mingw-w64-${{matrix.env}}-catch
+
+    - uses: actions/checkout@v3
+
+    - name: Configure C++11
+      # LTO leads to many undefined reference like
+      # `pybind11::detail::function_call::function_call(pybind11::detail::function_call&&)
+      run: cmake -G "MinGW Makefiles" -DCMAKE_CXX_STANDARD=11 -DCMAKE_VERBOSE_MAKEFILE=ON -DPYBIND11_WERROR=ON -DDOWNLOAD_CATCH=ON -S . -B build
+
+    - name: Build C++11
+      run: cmake --build build -j 2
+
+    - name: Python tests C++11
+      run: cmake --build build --target pytest -j 2
+
+    - name: C++11 tests
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build --target cpptest -j 2
+
+    - name: Interface test C++11
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build --target test_cmake_build
+
+    - name: Clean directory
+      run: git clean -fdx
+
+    - name: Configure C++14
+      run: cmake -G "MinGW Makefiles" -DCMAKE_CXX_STANDARD=14 -DCMAKE_VERBOSE_MAKEFILE=ON -DPYBIND11_WERROR=ON -DDOWNLOAD_CATCH=ON -S . -B build2
+
+    - name: Build C++14
+      run: cmake --build build2 -j 2
+
+    - name: Python tests C++14
+      run: cmake --build build2 --target pytest -j 2
+
+    - name: C++14 tests
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build2 --target cpptest -j 2
+
+    - name: Interface test C++14
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build2 --target test_cmake_build
+
+    - name: Clean directory
+      run: git clean -fdx
+
+    - name: Configure C++17
+      run: cmake -G "MinGW Makefiles" -DCMAKE_CXX_STANDARD=17 -DCMAKE_VERBOSE_MAKEFILE=ON -DPYBIND11_WERROR=ON -DDOWNLOAD_CATCH=ON -S . -B build3
+
+    - name: Build C++17
+      run: cmake --build build3 -j 2
+
+    - name: Python tests C++17
+      run: cmake --build build3 --target pytest -j 2
+
+    - name: C++17 tests
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build3 --target cpptest -j 2
+
+    - name: Interface test C++17
+      run: PYTHONHOME=/${{matrix.sys}} PYTHONPATH=/${{matrix.sys}} cmake --build build3 --target test_cmake_build
diff --git a/3rdparty/pybind11/.github/workflows/configure.yml b/3rdparty/pybind11/.github/workflows/configure.yml
index 23f60229f3..edcad4198b 100644
--- a/3rdparty/pybind11/.github/workflows/configure.yml
+++ b/3rdparty/pybind11/.github/workflows/configure.yml
@@ -18,7 +18,7 @@ jobs:
       matrix:
         runs-on: [ubuntu-latest, macos-latest, windows-latest]
         arch: [x64]
-        cmake: [3.18]
+        cmake: ["3.23"]
 
         include:
         - runs-on: ubuntu-latest
@@ -29,22 +29,18 @@ jobs:
           arch: x64
           cmake: 3.7
 
-        - runs-on: windows-2016
-          arch: x86
-          cmake: 3.8
-
-        - runs-on: windows-2016
-          arch: x86
+        - runs-on: windows-2019
+          arch: x64 # x86 compilers seem to be missing on 2019 image
           cmake: 3.18
 
     name: 🐍 3.7 • CMake ${{ matrix.cmake }} • ${{ matrix.runs-on }}
     runs-on: ${{ matrix.runs-on }}
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Setup Python 3.7
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
       with:
         python-version: 3.7
         architecture: ${{ matrix.arch }}
@@ -55,7 +51,7 @@ jobs:
     # An action for adding a specific version of CMake:
     #   https://github.com/jwlawson/actions-setup-cmake
     - name: Setup CMake ${{ matrix.cmake }}
-      uses: jwlawson/actions-setup-cmake@v1.3
+      uses: jwlawson/actions-setup-cmake@v1.12
       with:
         cmake-version: ${{ matrix.cmake }}
 
diff --git a/3rdparty/pybind11/.github/workflows/format.yml b/3rdparty/pybind11/.github/workflows/format.yml
index 5cebed17da..31d893c479 100644
--- a/3rdparty/pybind11/.github/workflows/format.yml
+++ b/3rdparty/pybind11/.github/workflows/format.yml
@@ -12,24 +12,33 @@ on:
     - stable
     - "v*"
 
+env:
+  FORCE_COLOR: 3
+
 jobs:
   pre-commit:
     name: Format
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v2
-    - uses: actions/setup-python@v2
-    - uses: pre-commit/action@v2.0.0
+    - uses: actions/checkout@v3
+    - uses: actions/setup-python@v4
+      with:
+        python-version: "3.x"
+    - name: Add matchers
+      run: echo "::add-matcher::$GITHUB_WORKSPACE/.github/matchers/pylint.json"
+    - uses: pre-commit/action@v3.0.0
       with:
         # Slow hooks are marked with manual - slow is okay here, run them too
         extra_args: --hook-stage manual --all-files
 
   clang-tidy:
+    # When making changes here, please also review the "Clang-Tidy" section
+    # in .github/CONTRIBUTING.md and update as needed.
     name: Clang-Tidy
     runs-on: ubuntu-latest
-    container: silkeh/clang:10
+    container: silkeh/clang:13
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Install requirements
       run: apt-get update && apt-get install -y python3-dev python3-pytest
@@ -37,10 +46,10 @@ jobs:
     - name: Configure
       run: >
         cmake -S . -B build
-        -DCMAKE_CXX_CLANG_TIDY="$(which clang-tidy);--warnings-as-errors=*"
+        -DCMAKE_CXX_CLANG_TIDY="$(which clang-tidy);--use-color;--warnings-as-errors=*"
         -DDOWNLOAD_EIGEN=ON
         -DDOWNLOAD_CATCH=ON
         -DCMAKE_CXX_STANDARD=17
 
     - name: Build
-      run: cmake --build build -j 2
+      run: cmake --build build -j 2 -- --keep-going
diff --git a/3rdparty/pybind11/.github/workflows/pip.yml b/3rdparty/pybind11/.github/workflows/pip.yml
index 4414a12ee4..f03a397019 100644
--- a/3rdparty/pybind11/.github/workflows/pip.yml
+++ b/3rdparty/pybind11/.github/workflows/pip.yml
@@ -12,24 +12,28 @@ on:
     types:
     - published
 
+env:
+  PIP_ONLY_BINARY: numpy
+
 jobs:
   # This builds the sdists and wheels and makes sure the files are exactly as
-  # expected. Using Windows and Python 2.7, since that is often the most
+  # expected. Using Windows and Python 3.6, since that is often the most
   # challenging matrix element.
   test-packaging:
-    name: 🐍 2.7 • 📦 tests • windows-latest
+    name: 🐍 3.6 • 📦 tests • windows-latest
     runs-on: windows-latest
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
-    - name: Setup 🐍 2.7
-      uses: actions/setup-python@v2
+    - name: Setup 🐍 3.6
+      uses: actions/setup-python@v4
       with:
-        python-version: 2.7
+        python-version: 3.6
 
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt --prefer-binary
+      run: |
+        python -m pip install -r tests/requirements.txt
 
     - name: Python Packaging tests
       run: pytest tests/extra_python_package/
@@ -42,15 +46,16 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Setup 🐍 3.8
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
       with:
         python-version: 3.8
 
     - name: Prepare env
-      run: python -m pip install -r tests/requirements.txt build twine --prefer-binary
+      run: |
+        python -m pip install -r tests/requirements.txt build twine
 
     - name: Python Packaging tests
       run: pytest tests/extra_python_package/
@@ -64,13 +69,13 @@ jobs:
       run: twine check dist/*
 
     - name: Save standard package
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v3
       with:
         name: standard
         path: dist/pybind11-*
 
     - name: Save global package
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v3
       with:
         name: global
         path: dist/pybind11_global-*
@@ -85,19 +90,21 @@ jobs:
     needs: [packaging]
 
     steps:
-    - uses: actions/setup-python@v2
+    - uses: actions/setup-python@v4
+      with:
+        python-version: "3.x"
 
     # Downloads all to directories matching the artifact names
-    - uses: actions/download-artifact@v2
+    - uses: actions/download-artifact@v3
 
     - name: Publish standard package
-      uses: pypa/gh-action-pypi-publish@v1.4.1
+      uses: pypa/gh-action-pypi-publish@v1.5.1
       with:
         password: ${{ secrets.pypi_password }}
         packages_dir: standard/
 
     - name: Publish global package
-      uses: pypa/gh-action-pypi-publish@v1.4.1
+      uses: pypa/gh-action-pypi-publish@v1.5.1
       with:
         password: ${{ secrets.pypi_password_global }}
         packages_dir: global/
diff --git a/3rdparty/pybind11/.github/workflows/upstream.yml b/3rdparty/pybind11/.github/workflows/upstream.yml
new file mode 100644
index 0000000000..95ff4cb83d
--- /dev/null
+++ b/3rdparty/pybind11/.github/workflows/upstream.yml
@@ -0,0 +1,112 @@
+
+name: Upstream
+
+on:
+  workflow_dispatch:
+  pull_request:
+
+concurrency:
+  group: upstream-${{ github.ref }}
+  cancel-in-progress: true
+
+env:
+  PIP_ONLY_BINARY: numpy
+
+jobs:
+  standard:
+    name: "🐍 3.11 latest internals • ubuntu-latest • x64"
+    runs-on: ubuntu-latest
+    if: "contains(github.event.pull_request.labels.*.name, 'python dev')"
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Setup Python 3.11
+      uses: actions/setup-python@v4
+      with:
+        python-version: "3.11-dev"
+
+    - name: Setup Boost (Linux)
+      if: runner.os == 'Linux'
+      run: sudo apt-get install libboost-dev
+
+    - name: Update CMake
+      uses: jwlawson/actions-setup-cmake@v1.12
+
+    - name: Prepare env
+      run: |
+        python -m pip install -r tests/requirements.txt
+
+    - name: Setup annotations on Linux
+      if: runner.os == 'Linux'
+      run: python -m pip install pytest-github-actions-annotate-failures
+
+    # First build - C++11 mode and inplace
+    - name: Configure C++11
+      run: >
+        cmake -S . -B .
+        -DPYBIND11_WERROR=ON
+        -DDOWNLOAD_CATCH=ON
+        -DDOWNLOAD_EIGEN=ON
+        -DCMAKE_CXX_STANDARD=11
+
+    - name: Build C++11
+      run: cmake --build . -j 2
+
+    - name: Python tests C++11
+      run: cmake --build . --target pytest -j 2
+
+    - name: C++11 tests
+      run: cmake --build .  --target cpptest -j 2
+
+    - name: Interface test C++11
+      run: cmake --build . --target test_cmake_build
+
+    - name: Clean directory
+      run: git clean -fdx
+
+    # Second build - C++17 mode and in a build directory
+    - name: Configure C++17
+      run: >
+        cmake -S . -B build2
+        -DPYBIND11_WERROR=ON
+        -DDOWNLOAD_CATCH=ON
+        -DDOWNLOAD_EIGEN=ON
+        -DCMAKE_CXX_STANDARD=17
+        ${{ matrix.args }}
+        ${{ matrix.args2 }}
+
+    - name: Build
+      run: cmake --build build2 -j 2
+
+    - name: Python tests
+      run: cmake --build build2 --target pytest
+
+    - name: C++ tests
+      run: cmake --build build2 --target cpptest
+
+    # Third build - C++17 mode with unstable ABI
+    - name: Configure (unstable ABI)
+      run: >
+        cmake -S . -B build3
+        -DPYBIND11_WERROR=ON
+        -DDOWNLOAD_CATCH=ON
+        -DDOWNLOAD_EIGEN=ON
+        -DCMAKE_CXX_STANDARD=17
+        -DPYBIND11_INTERNALS_VERSION=10000000
+        "-DPYBIND11_TEST_OVERRIDE=test_call_policies.cpp;test_gil_scoped.cpp;test_thread.cpp"
+        ${{ matrix.args }}
+
+    - name: Build (unstable ABI)
+      run: cmake --build build3 -j 2
+
+    - name: Python tests (unstable ABI)
+      run: cmake --build build3 --target pytest
+
+    - name: Interface test
+      run: cmake --build build3 --target test_cmake_build
+
+    # This makes sure the setup_helpers module can build packages using
+    # setuptools
+    - name: Setuptools helpers test
+      run: pytest tests/extra_setuptools
diff --git a/3rdparty/pybind11/.gitignore b/3rdparty/pybind11/.gitignore
index 3f36b89e0c..3cf4fbbda0 100644
--- a/3rdparty/pybind11/.gitignore
+++ b/3rdparty/pybind11/.gitignore
@@ -41,3 +41,5 @@ pybind11Targets.cmake
 /.vscode
 /pybind11/include/*
 /pybind11/share/*
+/docs/_build/*
+.ipynb_checkpoints/
diff --git a/3rdparty/pybind11/.pre-commit-config.yaml b/3rdparty/pybind11/.pre-commit-config.yaml
index 85254a8a98..5d794a7496 100644
--- a/3rdparty/pybind11/.pre-commit-config.yaml
+++ b/3rdparty/pybind11/.pre-commit-config.yaml
@@ -12,49 +12,112 @@
 #
 # See https://github.com/pre-commit/pre-commit
 
+# third-party content
+exclude: ^tools/JoinPaths.cmake$
+
 repos:
 # Standard hooks
 - repo: https://github.com/pre-commit/pre-commit-hooks
-  rev: v3.2.0
+  rev: "v4.3.0"
   hooks:
   - id: check-added-large-files
   - id: check-case-conflict
+  - id: check-docstring-first
   - id: check-merge-conflict
   - id: check-symlinks
+  - id: check-toml
   - id: check-yaml
   - id: debug-statements
   - id: end-of-file-fixer
   - id: mixed-line-ending
   - id: requirements-txt-fixer
   - id: trailing-whitespace
-  - id: fix-encoding-pragma
+
+# Upgrade old Python syntax
+- repo: https://github.com/asottile/pyupgrade
+  rev: "v2.37.3"
+  hooks:
+  - id: pyupgrade
+    args: [--py36-plus]
+
+# Nicely sort includes
+- repo: https://github.com/PyCQA/isort
+  rev: "5.10.1"
+  hooks:
+  - id: isort
 
 # Black, the code formatter, natively supports pre-commit
 - repo: https://github.com/psf/black
-  rev: 20.8b1
+  rev: "22.8.0" # Keep in sync with blacken-docs
   hooks:
   - id: black
-    # By default, this ignores pyi files, though black supports them
-    types: [text]
-    files: \.pyi?$
+
+# Also code format the docs
+- repo: https://github.com/asottile/blacken-docs
+  rev: "v1.12.1"
+  hooks:
+  - id: blacken-docs
+    additional_dependencies:
+    - black==22.8.0 # keep in sync with black hook
 
 # Changes tabs to spaces
 - repo: https://github.com/Lucas-C/pre-commit-hooks
-  rev: v1.1.9
+  rev: "v1.3.1"
   hooks:
   - id: remove-tabs
 
+- repo: https://github.com/sirosen/texthooks
+  rev: "0.4.0"
+  hooks:
+  - id: fix-ligatures
+  - id: fix-smartquotes
+
+# Autoremoves unused imports
+- repo: https://github.com/hadialqattan/pycln
+  rev: "v2.1.1"
+  hooks:
+  - id: pycln
+    stages: [manual]
+
+# Checking for common mistakes
+- repo: https://github.com/pre-commit/pygrep-hooks
+  rev: "v1.9.0"
+  hooks:
+  - id: python-check-blanket-noqa
+  - id: python-check-blanket-type-ignore
+  - id: python-no-log-warn
+  - id: python-use-type-annotations
+  - id: rst-backticks
+  - id: rst-directive-colons
+  - id: rst-inline-touching-normal
+
+# Automatically remove noqa that are not used
+- repo: https://github.com/asottile/yesqa
+  rev: "v1.4.0"
+  hooks:
+  - id: yesqa
+    additional_dependencies: &flake8_dependencies
+      - flake8-bugbear
+      - pep8-naming
+
 # Flake8 also supports pre-commit natively (same author)
-- repo: https://gitlab.com/pycqa/flake8
-  rev: 3.8.3
+- repo: https://github.com/PyCQA/flake8
+  rev: "5.0.4"
   hooks:
   - id: flake8
-    additional_dependencies: [flake8-bugbear, pep8-naming]
     exclude: ^(docs/.*|tools/.*)$
+    additional_dependencies: *flake8_dependencies
+
+# PyLint has native support - not always usable, but works for us
+- repo: https://github.com/PyCQA/pylint
+  rev: "v2.15.2"
+  hooks:
+  - id: pylint
+    files: ^pybind11
 
 # CMake formatting
 - repo: https://github.com/cheshirekow/cmake-format-precommit
-  rev: v0.6.13
+  rev: "v0.6.13"
   hooks:
   - id: cmake-format
     additional_dependencies: [pyyaml]
@@ -63,38 +126,50 @@ repos:
 
 # Check static types with mypy
 - repo: https://github.com/pre-commit/mirrors-mypy
-  rev: v0.790
+  rev: "v0.971"
   hooks:
   - id: mypy
-    # The default Python type ignores .pyi files, so let's rerun if detected
-    types: [text]
-    files: ^pybind11.*\.pyi?$
-    # Running per-file misbehaves a bit, so just run on all files, it's fast
-    pass_filenames: false
+    args: []
+    exclude: ^(tests|docs)/
+    additional_dependencies: [nox, rich]
 
 # Checks the manifest for missing files (native support)
 - repo: https://github.com/mgedmin/check-manifest
-  rev: "0.43"
+  rev: "0.48"
   hooks:
   - id: check-manifest
     # This is a slow hook, so only run this if --hook-stage manual is passed
     stages: [manual]
     additional_dependencies: [cmake, ninja]
 
-# The original pybind11 checks for a few C++ style items
+# Check for spelling
+# Use tools/codespell_ignore_lines_from_errors.py
+# to rebuild .codespell-ignore-lines
+- repo: https://github.com/codespell-project/codespell
+  rev: "v2.2.1"
+  hooks:
+  - id: codespell
+    exclude: ".supp$"
+    args: ["-x", ".codespell-ignore-lines"]
+
+# Check for common shell mistakes
+- repo: https://github.com/shellcheck-py/shellcheck-py
+  rev: "v0.8.0.4"
+  hooks:
+  - id: shellcheck
+
+# Disallow some common capitalization mistakes
 - repo: local
   hooks:
   - id: disallow-caps
     name: Disallow improper capitalization
     language: pygrep
-    entry: PyBind|Numpy|Cmake|CCache
-    exclude: .pre-commit-config.yaml
+    entry: PyBind|Numpy|Cmake|CCache|PyTest
+    exclude: ^\.pre-commit-config.yaml$
 
-- repo: local
+# Clang format the codebase automatically
+- repo: https://github.com/pre-commit/mirrors-clang-format
+  rev: "v14.0.6"
   hooks:
-  - id: check-style
-    name: Classic check-style
-    language: system
-    types:
-    - c++
-    entry: ./tools/check-style.sh
+  - id: clang-format
+    types_or: [c++, c, cuda]
diff --git a/3rdparty/pybind11/CMakeLists.txt b/3rdparty/pybind11/CMakeLists.txt
index 2c08ff0b98..ee0975bc1f 100644
--- a/3rdparty/pybind11/CMakeLists.txt
+++ b/3rdparty/pybind11/CMakeLists.txt
@@ -7,13 +7,18 @@
 
 cmake_minimum_required(VERSION 3.4)
 
-# The `cmake_minimum_required(VERSION 3.4...3.18)` syntax does not work with
+# The `cmake_minimum_required(VERSION 3.4...3.22)` syntax does not work with
 # some versions of VS that have a patched CMake 3.11. This forces us to emulate
 # the behavior using the following workaround:
-if(${CMAKE_VERSION} VERSION_LESS 3.18)
+if(${CMAKE_VERSION} VERSION_LESS 3.22)
   cmake_policy(VERSION ${CMAKE_MAJOR_VERSION}.${CMAKE_MINOR_VERSION})
 else()
-  cmake_policy(VERSION 3.18)
+  cmake_policy(VERSION 3.22)
+endif()
+
+# Avoid infinite recursion if tests include this as a subdirectory
+if(DEFINED PYBIND11_MASTER_PROJECT)
+  return()
 endif()
 
 # Extract project version from source
@@ -73,6 +78,10 @@ if(CMAKE_SOURCE_DIR STREQUAL PROJECT_SOURCE_DIR)
     set(CMAKE_CXX_EXTENSIONS OFF)
     set(CMAKE_CXX_STANDARD_REQUIRED ON)
   endif()
+
+  set(pybind11_system "")
+
+  set_property(GLOBAL PROPERTY USE_FOLDERS ON)
 else()
   set(PYBIND11_MASTER_PROJECT OFF)
   set(pybind11_system SYSTEM)
@@ -82,6 +91,9 @@ endif()
 option(PYBIND11_INSTALL "Install pybind11 header files?" ${PYBIND11_MASTER_PROJECT})
 option(PYBIND11_TEST "Build pybind11 test suite?" ${PYBIND11_MASTER_PROJECT})
 option(PYBIND11_NOPYTHON "Disable search for Python" OFF)
+set(PYBIND11_INTERNALS_VERSION
+    ""
+    CACHE STRING "Override the ABI version, may be used to enable the unstable ABI.")
 
 cmake_dependent_option(
   USE_PYTHON_INCLUDE_DIR
@@ -98,6 +110,7 @@ set(PYBIND11_HEADERS
     include/pybind11/detail/descr.h
     include/pybind11/detail/init.h
     include/pybind11/detail/internals.h
+    include/pybind11/detail/type_caster_base.h
     include/pybind11/detail/typeid.h
     include/pybind11/attr.h
     include/pybind11/buffer_info.h
@@ -109,6 +122,7 @@ set(PYBIND11_HEADERS
     include/pybind11/eigen.h
     include/pybind11/embed.h
     include/pybind11/eval.h
+    include/pybind11/gil.h
     include/pybind11/iostream.h
     include/pybind11/functional.h
     include/pybind11/numpy.h
@@ -116,7 +130,8 @@ set(PYBIND11_HEADERS
     include/pybind11/pybind11.h
     include/pybind11/pytypes.h
     include/pybind11/stl.h
-    include/pybind11/stl_bind.h)
+    include/pybind11/stl_bind.h
+    include/pybind11/stl/filesystem.h)
 
 # Compare with grep and warn if mismatched
 if(PYBIND11_MASTER_PROJECT AND NOT CMAKE_VERSION VERSION_LESS 3.12)
@@ -159,14 +174,33 @@ endif()
 # You can also place ifs *in* the Config.in, but not here.
 
 # This section builds targets, but does *not* touch Python
-
-# Build the headers-only target (no Python included):
-# (long name used here to keep this from clashing in subdirectory mode)
-add_library(pybind11_headers INTERFACE)
-add_library(pybind11::pybind11_headers ALIAS pybind11_headers) # to match exported target
-add_library(pybind11::headers ALIAS pybind11_headers) # easier to use/remember
+# Non-IMPORT targets cannot be defined twice
+if(NOT TARGET pybind11_headers)
+  # Build the headers-only target (no Python included):
+  # (long name used here to keep this from clashing in subdirectory mode)
+  add_library(pybind11_headers INTERFACE)
+  add_library(pybind11::pybind11_headers ALIAS pybind11_headers) # to match exported target
+  add_library(pybind11::headers ALIAS pybind11_headers) # easier to use/remember
+
+  target_include_directories(
+    pybind11_headers ${pybind11_system} INTERFACE $<BUILD_INTERFACE:${pybind11_INCLUDE_DIR}>
+                                                  $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
+
+  target_compile_features(pybind11_headers INTERFACE cxx_inheriting_constructors cxx_user_literals
+                                                     cxx_right_angle_brackets)
+  if(NOT "${PYBIND11_INTERNALS_VERSION}" STREQUAL "")
+    target_compile_definitions(
+      pybind11_headers INTERFACE "PYBIND11_INTERNALS_VERSION=${PYBIND11_INTERNALS_VERSION}")
+  endif()
+else()
+  # It is invalid to install a target twice, too.
+  set(PYBIND11_INSTALL OFF)
+endif()
 
 include("${CMAKE_CURRENT_SOURCE_DIR}/tools/pybind11Common.cmake")
+# https://github.com/jtojnar/cmake-snips/#concatenating-paths-when-building-pkg-config-files
+# TODO: cmake 3.20 adds the cmake_path() function, which obsoletes this snippet
+include("${CMAKE_CURRENT_SOURCE_DIR}/tools/JoinPaths.cmake")
 
 # Relative directory setting
 if(USE_PYTHON_INCLUDE_DIR AND DEFINED Python_INCLUDE_DIRS)
@@ -175,20 +209,18 @@ elseif(USE_PYTHON_INCLUDE_DIR AND DEFINED PYTHON_INCLUDE_DIR)
   file(RELATIVE_PATH CMAKE_INSTALL_INCLUDEDIR ${CMAKE_INSTALL_PREFIX} ${PYTHON_INCLUDE_DIRS})
 endif()
 
-# Fill in headers target
-target_include_directories(
-  pybind11_headers ${pybind11_system} INTERFACE $<BUILD_INTERFACE:${pybind11_INCLUDE_DIR}>
-                                                $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
-
-target_compile_features(pybind11_headers INTERFACE cxx_inheriting_constructors cxx_user_literals
-                                                   cxx_right_angle_brackets)
-
 if(PYBIND11_INSTALL)
   install(DIRECTORY ${pybind11_INCLUDE_DIR}/pybind11 DESTINATION ${CMAKE_INSTALL_INCLUDEDIR})
   set(PYBIND11_CMAKECONFIG_INSTALL_DIR
       "${CMAKE_INSTALL_DATAROOTDIR}/cmake/${PROJECT_NAME}"
       CACHE STRING "install path for pybind11Config.cmake")
 
+  if(IS_ABSOLUTE "${CMAKE_INSTALL_INCLUDEDIR}")
+    set(pybind11_INCLUDEDIR "${CMAKE_INSTALL_FULL_INCLUDEDIR}")
+  else()
+    set(pybind11_INCLUDEDIR "\$\{PACKAGE_PREFIX_DIR\}/${CMAKE_INSTALL_INCLUDEDIR}")
+  endif()
+
   configure_package_config_file(
     tools/${PROJECT_NAME}Config.cmake.in "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}Config.cmake"
     INSTALL_DESTINATION ${PYBIND11_CMAKECONFIG_INSTALL_DIR})
@@ -233,6 +265,16 @@ if(PYBIND11_INSTALL)
     NAMESPACE "pybind11::"
     DESTINATION ${PYBIND11_CMAKECONFIG_INSTALL_DIR})
 
+  # pkg-config support
+  if(NOT prefix_for_pc_file)
+    set(prefix_for_pc_file "${CMAKE_INSTALL_PREFIX}")
+  endif()
+  join_paths(includedir_for_pc_file "\${prefix}" "${CMAKE_INSTALL_INCLUDEDIR}")
+  configure_file("${CMAKE_CURRENT_SOURCE_DIR}/tools/pybind11.pc.in"
+                 "${CMAKE_CURRENT_BINARY_DIR}/pybind11.pc" @ONLY)
+  install(FILES "${CMAKE_CURRENT_BINARY_DIR}/pybind11.pc"
+          DESTINATION "${CMAKE_INSTALL_DATAROOTDIR}/pkgconfig/")
+
   # Uninstall target
   if(PYBIND11_MASTER_PROJECT)
     configure_file("${CMAKE_CURRENT_SOURCE_DIR}/tools/cmake_uninstall.cmake.in"
diff --git a/3rdparty/pybind11/MANIFEST.in b/3rdparty/pybind11/MANIFEST.in
index aed183e874..033303a74a 100644
--- a/3rdparty/pybind11/MANIFEST.in
+++ b/3rdparty/pybind11/MANIFEST.in
@@ -1,6 +1,5 @@
 recursive-include pybind11/include/pybind11 *.h
 recursive-include pybind11 *.py
 recursive-include pybind11 py.typed
-recursive-include pybind11 *.pyi
 include pybind11/share/cmake/pybind11/*.cmake
 include LICENSE README.rst pyproject.toml setup.py setup.cfg
diff --git a/3rdparty/pybind11/README.rst b/3rdparty/pybind11/README.rst
index 1474cb95af..3c75edb575 100644
--- a/3rdparty/pybind11/README.rst
+++ b/3rdparty/pybind11/README.rst
@@ -3,20 +3,16 @@
 
 **pybind11 — Seamless operability between C++11 and Python**
 
-|Latest Documentation Status| |Stable Documentation Status| |Gitter chat| |CI| |Build status|
+|Latest Documentation Status| |Stable Documentation Status| |Gitter chat| |GitHub Discussions| |CI| |Build status|
 
-.. warning::
+|Repology| |PyPI package| |Conda-forge| |Python Versions|
 
-   Combining older versions of pybind11 (< 2.6.0) with the brand-new Python
-   3.9.0 will trigger undefined behavior that typically manifests as crashes
-   during interpreter shutdown (but could also destroy your data. **You have been
-   warned.**)
+`Setuptools example <https://github.com/pybind/python_example>`_
+• `Scikit-build example <https://github.com/pybind/scikit_build_example>`_
+• `CMake example <https://github.com/pybind/cmake_example>`_
+
+.. start
 
-   We recommend that you wait for Python 3.9.1 slated for release in December,
-   which will include a `fix <https://github.com/python/cpython/pull/22670>`_
-   that resolves this problem.  In the meantime, please update to the latest
-   version of pybind11 (2.6.0 or newer), which includes a temporary workaround
-   specifically when Python 3.9.0 is detected at runtime.
 
 **pybind11** is a lightweight header-only library that exposes C++ types
 in Python and vice versa, mainly to create Python bindings of existing
@@ -36,9 +32,9 @@ this heavy machinery has become an excessively large and unnecessary
 dependency.
 
 Think of this library as a tiny self-contained version of Boost.Python
-with everything stripped away that isn’t relevant for binding
+with everything stripped away that isn't relevant for binding
 generation. Without comments, the core header files only require ~4K
-lines of code and depend on Python (2.7 or 3.5+, or PyPy) and the C++
+lines of code and depend on Python (3.6+, or PyPy) and the C++
 standard library. This compact implementation was possible thanks to
 some of the new C++11 language features (specifically: tuples, lambda
 functions and variadic templates). Since its creation, this library has
@@ -82,8 +78,8 @@ Goodies
 In addition to the core functionality, pybind11 provides some extra
 goodies:
 
-- Python 2.7, 3.5+, and PyPy/PyPy3 7.3 are supported with an
-  implementation-agnostic interface.
+- Python 3.6+, and PyPy3 7.3 are supported with an implementation-agnostic
+  interface (pybind11 2.9 was the last version to support Python 2 and 3.5).
 
 - It is possible to bind C++11 lambda functions with captured
   variables. The lambda capture data is stored inside the resulting
@@ -92,8 +88,8 @@ goodies:
 - pybind11 uses C++11 move constructors and move assignment operators
   whenever possible to efficiently transfer custom data types.
 
-- It’s easy to expose the internal storage of custom data types through
-  Pythons’ buffer protocols. This is handy e.g. for fast conversion
+- It's easy to expose the internal storage of custom data types through
+  Pythons' buffer protocols. This is handy e.g. for fast conversion
   between C++ matrix classes like Eigen and NumPy without expensive
   copy operations.
 
@@ -101,7 +97,7 @@ goodies:
   transparently applied to all entries of one or more NumPy array
   arguments.
 
-- Python’s slice-based access and assignment operations can be
+- Python's slice-based access and assignment operations can be
   supported with just a few lines of code.
 
 - Everything is contained in just a few header files; there is no need
@@ -110,7 +106,7 @@ goodies:
 - Binaries are generally smaller by a factor of at least 2 compared to
   equivalent bindings generated by Boost.Python. A recent pybind11
   conversion of PyRosetta, an enormous Boost.Python binding project,
-  `reported <http://graylab.jhu.edu/RosettaCon2016/PyRosetta-4.pdf>`_
+  `reported <https://graylab.jhu.edu/Sergey/2016.RosettaCon/PyRosetta-4.pdf>`_
   a binary size reduction of **5.4x** and compile time reduction by
   **5.8x**.
 
@@ -123,15 +119,14 @@ goodies:
 Supported compilers
 -------------------
 
-1. Clang/LLVM 3.3 or newer (for Apple Xcode’s clang, this is 5.0.0 or
+1. Clang/LLVM 3.3 or newer (for Apple Xcode's clang, this is 5.0.0 or
    newer)
 2. GCC 4.8 or newer
-3. Microsoft Visual Studio 2015 Update 3 or newer
-4. Intel C++ compiler 18 or newer
-   (`possible issue <https://github.com/pybind/pybind11/pull/2573>`_ on 20.2)
-5. Cygwin/GCC (tested on 2.5.1)
-6. NVCC (CUDA 11.0 tested)
-7. NVIDIA PGI (20.7 and 20.9 tested)
+3. Microsoft Visual Studio 2017 or newer
+4. Intel classic C++ compiler 18 or newer (ICC 20.2 tested in CI)
+5. Cygwin/GCC (previously tested on 2.5.1)
+6. NVCC (CUDA 11.0 tested in CI)
+7. NVIDIA PGI (20.9 tested in CI)
 
 About
 -----
@@ -139,9 +134,9 @@ About
 This project was created by `Wenzel
 Jakob <http://rgl.epfl.ch/people/wjakob>`_. Significant features and/or
 improvements to the code were contributed by Jonas Adler, Lori A. Burns,
-Sylvain Corlay, Eric Cousineau, Ralf Grosse-Kunstleve, Trent Houliston, Axel
+Sylvain Corlay, Eric Cousineau, Aaron Gokaslan, Ralf Grosse-Kunstleve, Trent Houliston, Axel
 Huebl, @hulucc, Yannick Jadoul, Sergey Lyskov Johan Mabille, Tomasz Miąsko,
-Dean Moldovan, Ben Pritchard, Jason Rhinelander, Boris Schäling,  Pim
+Dean Moldovan, Ben Pritchard, Jason Rhinelander, Boris Schäling, Pim
 Schellart, Henry Schreiner, Ivan Smirnov, Boris Staletic, and Patrick Stewart.
 
 We thank Google for a generous financial contribution to the continuous
@@ -165,7 +160,7 @@ to the terms and conditions of this license.
 
 .. |Latest Documentation Status| image:: https://readthedocs.org/projects/pybind11/badge?version=latest
    :target: http://pybind11.readthedocs.org/en/latest
-.. |Stable Documentation Status| image:: https://img.shields.io/badge/docs-stable-blue
+.. |Stable Documentation Status| image:: https://img.shields.io/badge/docs-stable-blue.svg
    :target: http://pybind11.readthedocs.org/en/stable
 .. |Gitter chat| image:: https://img.shields.io/gitter/room/gitterHQ/gitter.svg
    :target: https://gitter.im/pybind/Lobby
@@ -173,3 +168,13 @@ to the terms and conditions of this license.
    :target: https://github.com/pybind/pybind11/actions
 .. |Build status| image:: https://ci.appveyor.com/api/projects/status/riaj54pn4h08xy40?svg=true
    :target: https://ci.appveyor.com/project/wjakob/pybind11
+.. |PyPI package| image:: https://img.shields.io/pypi/v/pybind11.svg
+   :target: https://pypi.org/project/pybind11/
+.. |Conda-forge| image:: https://img.shields.io/conda/vn/conda-forge/pybind11.svg
+   :target: https://github.com/conda-forge/pybind11-feedstock
+.. |Repology| image:: https://repology.org/badge/latest-versions/python:pybind11.svg
+   :target: https://repology.org/project/python:pybind11/versions
+.. |Python Versions| image:: https://img.shields.io/pypi/pyversions/pybind11.svg
+   :target: https://pypi.org/project/pybind11/
+.. |GitHub Discussions| image:: https://img.shields.io/static/v1?label=Discussions&message=Ask&color=blue&logo=github
+   :target: https://github.com/pybind/pybind11/discussions
diff --git a/3rdparty/pybind11/docs/Doxyfile b/3rdparty/pybind11/docs/Doxyfile
index c8562952ef..09138db364 100644
--- a/3rdparty/pybind11/docs/Doxyfile
+++ b/3rdparty/pybind11/docs/Doxyfile
@@ -18,6 +18,4 @@ ALIASES               += "endrst=\endverbatim"
 QUIET                  = YES
 WARNINGS               = YES
 WARN_IF_UNDOCUMENTED   = NO
-PREDEFINED             = DOXYGEN_SHOULD_SKIP_THIS \
-                         PY_MAJOR_VERSION=3 \
-                         PYBIND11_NOINLINE
+PREDEFINED             = PYBIND11_NOINLINE
diff --git a/3rdparty/pybind11/docs/_static/css/custom.css b/3rdparty/pybind11/docs/_static/css/custom.css
new file mode 100644
index 0000000000..7a49a6ac4f
--- /dev/null
+++ b/3rdparty/pybind11/docs/_static/css/custom.css
@@ -0,0 +1,3 @@
+.highlight .go {
+  color: #707070;
+}
diff --git a/3rdparty/pybind11/docs/advanced/cast/custom.rst b/3rdparty/pybind11/docs/advanced/cast/custom.rst
index a779444c24..8138cac619 100644
--- a/3rdparty/pybind11/docs/advanced/cast/custom.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/custom.rst
@@ -26,7 +26,9 @@ The following Python snippet demonstrates the intended usage from the Python sid
         def __int__(self):
             return 123
 
+
     from example import print
+
     print(A())
 
 To register the necessary conversion routines, it is necessary to add an
@@ -36,7 +38,7 @@ type is explicitly allowed.
 
 .. code-block:: cpp
 
-    namespace pybind11 { namespace detail {
+    namespace PYBIND11_NAMESPACE { namespace detail {
         template <> struct type_caster<inty> {
         public:
             /**
@@ -44,7 +46,7 @@ type is explicitly allowed.
              * function signatures and declares a local variable
              * 'value' of type inty
              */
-            PYBIND11_TYPE_CASTER(inty, _("inty"));
+            PYBIND11_TYPE_CASTER(inty, const_name("inty"));
 
             /**
              * Conversion part 1 (Python->C++): convert a PyObject into a inty
@@ -76,7 +78,7 @@ type is explicitly allowed.
                 return PyLong_FromLong(src.long_value);
             }
         };
-    }} // namespace pybind11::detail
+    }} // namespace PYBIND11_NAMESPACE::detail
 
 .. note::
 
diff --git a/3rdparty/pybind11/docs/advanced/cast/eigen.rst b/3rdparty/pybind11/docs/advanced/cast/eigen.rst
index e01472d5ae..a5c11a3f14 100644
--- a/3rdparty/pybind11/docs/advanced/cast/eigen.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/eigen.rst
@@ -52,7 +52,7 @@ can be mapped *and* if the numpy array is writeable (that is
 the passed variable will be transparently carried out directly on the
 ``numpy.ndarray``.
 
-This means you can can write code such as the following and have it work as
+This means you can write code such as the following and have it work as
 expected:
 
 .. code-block:: cpp
@@ -112,7 +112,7 @@ example:
 .. code-block:: python
 
     a = MyClass()
-    m = a.get_matrix()   # flags.writeable = True,  flags.owndata = False
+    m = a.get_matrix()  # flags.writeable = True,  flags.owndata = False
     v = a.view_matrix()  # flags.writeable = False, flags.owndata = False
     c = a.copy_matrix()  # flags.writeable = True,  flags.owndata = True
     # m[5,6] and v[5,6] refer to the same element, c[5,6] does not.
@@ -203,7 +203,7 @@ adding the ``order='F'`` option when creating an array:
 
 .. code-block:: python
 
-    myarray = np.array(source, order='F')
+    myarray = np.array(source, order="F")
 
 Such an object will be passable to a bound function accepting an
 ``Eigen::Ref<MatrixXd>`` (or similar column-major Eigen type).
diff --git a/3rdparty/pybind11/docs/advanced/cast/overview.rst b/3rdparty/pybind11/docs/advanced/cast/overview.rst
index b0e32a52f9..011bd4c7a3 100644
--- a/3rdparty/pybind11/docs/advanced/cast/overview.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/overview.rst
@@ -75,91 +75,96 @@ The following basic data types are supported out of the box (some may require
 an additional extension header to be included). To pass other data structures
 as arguments and return values, refer to the section on binding :ref:`classes`.
 
-+------------------------------------+---------------------------+-------------------------------+
-|  Data type                         |  Description              | Header file                   |
-+====================================+===========================+===============================+
-| ``int8_t``, ``uint8_t``            | 8-bit integers            | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``int16_t``, ``uint16_t``          | 16-bit integers           | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``int32_t``, ``uint32_t``          | 32-bit integers           | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``int64_t``, ``uint64_t``          | 64-bit integers           | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``ssize_t``, ``size_t``            | Platform-dependent size   | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``float``, ``double``              | Floating point types      | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``bool``                           | Two-state Boolean type    | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``char``                           | Character literal         | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``char16_t``                       | UTF-16 character literal  | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``char32_t``                       | UTF-32 character literal  | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``wchar_t``                        | Wide character literal    | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``const char *``                   | UTF-8 string literal      | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``const char16_t *``               | UTF-16 string literal     | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``const char32_t *``               | UTF-32 string literal     | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``const wchar_t *``                | Wide string literal       | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::string``                    | STL dynamic UTF-8 string  | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::u16string``                 | STL dynamic UTF-16 string | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::u32string``                 | STL dynamic UTF-32 string | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::wstring``                   | STL dynamic wide string   | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::string_view``,              | STL C++17 string views    | :file:`pybind11/pybind11.h`   |
-| ``std::u16string_view``, etc.      |                           |                               |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::pair<T1, T2>``              | Pair of two custom types  | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::tuple<...>``                | Arbitrary tuple of types  | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::reference_wrapper<...>``    | Reference type wrapper    | :file:`pybind11/pybind11.h`   |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::complex<T>``                | Complex numbers           | :file:`pybind11/complex.h`    |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::array<T, Size>``            | STL static array          | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::vector<T>``                 | STL dynamic array         | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::deque<T>``                  | STL double-ended queue    | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::valarray<T>``               | STL value array           | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::list<T>``                   | STL linked list           | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::map<T1, T2>``               | STL ordered map           | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::unordered_map<T1, T2>``     | STL unordered map         | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::set<T>``                    | STL ordered set           | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::unordered_set<T>``          | STL unordered set         | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::optional<T>``               | STL optional type (C++17) | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::experimental::optional<T>`` | STL optional type (exp.)  | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::variant<...>``              | Type-safe union (C++17)   | :file:`pybind11/stl.h`        |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::function<...>``             | STL polymorphic function  | :file:`pybind11/functional.h` |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::chrono::duration<...>``     | STL time duration         | :file:`pybind11/chrono.h`     |
-+------------------------------------+---------------------------+-------------------------------+
-| ``std::chrono::time_point<...>``   | STL date/time             | :file:`pybind11/chrono.h`     |
-+------------------------------------+---------------------------+-------------------------------+
-| ``Eigen::Matrix<...>``             | Eigen: dense matrix       | :file:`pybind11/eigen.h`      |
-+------------------------------------+---------------------------+-------------------------------+
-| ``Eigen::Map<...>``                | Eigen: mapped memory      | :file:`pybind11/eigen.h`      |
-+------------------------------------+---------------------------+-------------------------------+
-| ``Eigen::SparseMatrix<...>``       | Eigen: sparse matrix      | :file:`pybind11/eigen.h`      |
-+------------------------------------+---------------------------+-------------------------------+
++------------------------------------+---------------------------+-----------------------------------+
+|  Data type                         |  Description              | Header file                       |
++====================================+===========================+===================================+
+| ``int8_t``, ``uint8_t``            | 8-bit integers            | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``int16_t``, ``uint16_t``          | 16-bit integers           | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``int32_t``, ``uint32_t``          | 32-bit integers           | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``int64_t``, ``uint64_t``          | 64-bit integers           | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``ssize_t``, ``size_t``            | Platform-dependent size   | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``float``, ``double``              | Floating point types      | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``bool``                           | Two-state Boolean type    | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``char``                           | Character literal         | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``char16_t``                       | UTF-16 character literal  | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``char32_t``                       | UTF-32 character literal  | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``wchar_t``                        | Wide character literal    | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``const char *``                   | UTF-8 string literal      | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``const char16_t *``               | UTF-16 string literal     | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``const char32_t *``               | UTF-32 string literal     | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``const wchar_t *``                | Wide string literal       | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::string``                    | STL dynamic UTF-8 string  | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::u16string``                 | STL dynamic UTF-16 string | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::u32string``                 | STL dynamic UTF-32 string | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::wstring``                   | STL dynamic wide string   | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::string_view``,              | STL C++17 string views    | :file:`pybind11/pybind11.h`       |
+| ``std::u16string_view``, etc.      |                           |                                   |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::pair<T1, T2>``              | Pair of two custom types  | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::tuple<...>``                | Arbitrary tuple of types  | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::reference_wrapper<...>``    | Reference type wrapper    | :file:`pybind11/pybind11.h`       |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::complex<T>``                | Complex numbers           | :file:`pybind11/complex.h`        |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::array<T, Size>``            | STL static array          | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::vector<T>``                 | STL dynamic array         | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::deque<T>``                  | STL double-ended queue    | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::valarray<T>``               | STL value array           | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::list<T>``                   | STL linked list           | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::map<T1, T2>``               | STL ordered map           | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::unordered_map<T1, T2>``     | STL unordered map         | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::set<T>``                    | STL ordered set           | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::unordered_set<T>``          | STL unordered set         | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::optional<T>``               | STL optional type (C++17) | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::experimental::optional<T>`` | STL optional type (exp.)  | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::variant<...>``              | Type-safe union (C++17)   | :file:`pybind11/stl.h`            |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::filesystem::path<T>``       | STL path (C++17) [#]_     | :file:`pybind11/stl/filesystem.h` |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::function<...>``             | STL polymorphic function  | :file:`pybind11/functional.h`     |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::chrono::duration<...>``     | STL time duration         | :file:`pybind11/chrono.h`         |
++------------------------------------+---------------------------+-----------------------------------+
+| ``std::chrono::time_point<...>``   | STL date/time             | :file:`pybind11/chrono.h`         |
++------------------------------------+---------------------------+-----------------------------------+
+| ``Eigen::Matrix<...>``             | Eigen: dense matrix       | :file:`pybind11/eigen.h`          |
++------------------------------------+---------------------------+-----------------------------------+
+| ``Eigen::Map<...>``                | Eigen: mapped memory      | :file:`pybind11/eigen.h`          |
++------------------------------------+---------------------------+-----------------------------------+
+| ``Eigen::SparseMatrix<...>``       | Eigen: sparse matrix      | :file:`pybind11/eigen.h`          |
++------------------------------------+---------------------------+-----------------------------------+
+
+.. [#] ``std::filesystem::path`` is converted to ``pathlib.Path`` and
+   ``os.PathLike`` is converted to ``std::filesystem::path``.
diff --git a/3rdparty/pybind11/docs/advanced/cast/stl.rst b/3rdparty/pybind11/docs/advanced/cast/stl.rst
index 70fde0d2f4..03d49b2950 100644
--- a/3rdparty/pybind11/docs/advanced/cast/stl.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/stl.rst
@@ -42,7 +42,7 @@ types:
 .. code-block:: cpp
 
     // `boost::optional` as an example -- can be any `std::optional`-like container
-    namespace pybind11 { namespace detail {
+    namespace PYBIND11_NAMESPACE { namespace detail {
         template <typename T>
         struct type_caster<boost::optional<T>> : optional_caster<boost::optional<T>> {};
     }}
@@ -54,7 +54,7 @@ for custom variant types:
 .. code-block:: cpp
 
     // `boost::variant` as an example -- can be any `std::variant`-like container
-    namespace pybind11 { namespace detail {
+    namespace PYBIND11_NAMESPACE { namespace detail {
         template <typename... Ts>
         struct type_caster<boost::variant<Ts...>> : variant_caster<boost::variant<Ts...>> {};
 
@@ -66,18 +66,27 @@ for custom variant types:
                 return boost::apply_visitor(args...);
             }
         };
-    }} // namespace pybind11::detail
+    }} // namespace PYBIND11_NAMESPACE::detail
 
 The ``visit_helper`` specialization is not required if your ``name::variant`` provides
 a ``name::visit()`` function. For any other function name, the specialization must be
 included to tell pybind11 how to visit the variant.
 
+.. warning::
+
+    When converting a ``variant`` type, pybind11 follows the same rules as when
+    determining which function overload to call (:ref:`overload_resolution`), and
+    so the same caveats hold. In particular, the order in which the ``variant``'s
+    alternatives are listed is important, since pybind11 will try conversions in
+    this order. This means that, for example, when converting ``variant<int, bool>``,
+    the ``bool`` variant will never be selected, as any Python ``bool`` is already
+    an ``int`` and is convertible to a C++ ``int``. Changing the order of alternatives
+    (and using ``variant<bool, int>``, in this example) provides a solution.
+
 .. note::
 
     pybind11 only supports the modern implementation of ``boost::variant``
     which makes use of variadic templates. This requires Boost 1.56 or newer.
-    Additionally, on Windows, MSVC 2017 is required because ``boost::variant``
-    falls back to the old non-variadic implementation on MSVC 2015.
 
 .. _opaque:
 
diff --git a/3rdparty/pybind11/docs/advanced/cast/strings.rst b/3rdparty/pybind11/docs/advanced/cast/strings.rst
index e25701ecab..e246c5219a 100644
--- a/3rdparty/pybind11/docs/advanced/cast/strings.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/strings.rst
@@ -1,14 +1,6 @@
 Strings, bytes and Unicode conversions
 ######################################
 
-.. note::
-
-    This section discusses string handling in terms of Python 3 strings. For
-    Python 2.7, replace all occurrences of ``str`` with ``unicode`` and
-    ``bytes`` with ``str``.  Python 2.7 users may find it best to use ``from
-    __future__ import unicode_literals`` to avoid unintentionally using ``str``
-    instead of ``unicode``.
-
 Passing Python strings to C++
 =============================
 
@@ -36,13 +28,13 @@ everywhere <http://utf8everywhere.org/>`_.
         }
     );
 
-.. code-block:: python
+.. code-block:: pycon
 
-    >>> utf8_test('🎂')
+    >>> utf8_test("🎂")
     utf-8 is icing on the cake.
     🎂
 
-    >>> utf8_charptr('🍕')
+    >>> utf8_charptr("🍕")
     My favorite food is
     🍕
 
@@ -58,9 +50,9 @@ Passing bytes to C++
 --------------------
 
 A Python ``bytes`` object will be passed to C++ functions that accept
-``std::string`` or ``char*`` *without* conversion.  On Python 3, in order to
-make a function *only* accept ``bytes`` (and not ``str``), declare it as taking
-a ``py::bytes`` argument.
+``std::string`` or ``char*`` *without* conversion.  In order to make a function
+*only* accept ``bytes`` (and not ``str``), declare it as taking a ``py::bytes``
+argument.
 
 
 Returning C++ strings to Python
@@ -80,7 +72,7 @@ raise a ``UnicodeDecodeError``.
         }
     );
 
-.. code-block:: python
+.. code-block:: pycon
 
     >>> isinstance(example.std_string_return(), str)
     True
@@ -114,7 +106,7 @@ conversion has the same overhead as implicit conversion.
         }
     );
 
-.. code-block:: python
+.. code-block:: pycon
 
     >>> str_output()
     'Send your résumé to Alice in HR'
@@ -143,7 +135,7 @@ returned to Python as ``bytes``, then one can return the data as a
         }
     );
 
-.. code-block:: python
+.. code-block:: pycon
 
     >>> example.return_bytes()
     b'\xba\xd0\xba\xd0'
@@ -160,7 +152,7 @@ encoding, but cannot convert ``std::string`` back to ``bytes`` implicitly.
         }
     );
 
-.. code-block:: python
+.. code-block:: pycon
 
     >>> isinstance(example.asymmetry(b"have some bytes"), str)
     True
@@ -204,11 +196,6 @@ decoded to Python ``str``.
         }
     );
 
-.. warning::
-
-    Wide character strings may not work as described on Python 2.7 or Python
-    3.3 compiled with ``--enable-unicode=ucs2``.
-
 Strings in multibyte encodings such as Shift-JIS must transcoded to a
 UTF-8/16/32 before being returned to Python.
 
@@ -229,16 +216,16 @@ character.
     m.def("pass_char", [](char c) { return c; });
     m.def("pass_wchar", [](wchar_t w) { return w; });
 
-.. code-block:: python
+.. code-block:: pycon
 
-    >>> example.pass_char('A')
+    >>> example.pass_char("A")
     'A'
 
 While C++ will cast integers to character types (``char c = 0x65;``), pybind11
 does not convert Python integers to characters implicitly. The Python function
 ``chr()`` can be used to convert integers to characters.
 
-.. code-block:: python
+.. code-block:: pycon
 
     >>> example.pass_char(0x65)
     TypeError
@@ -259,17 +246,17 @@ a combining acute accent). The combining character will be lost if the
 two-character sequence is passed as an argument, even though it renders as a
 single grapheme.
 
-.. code-block:: python
+.. code-block:: pycon
 
-    >>> example.pass_wchar('é')
+    >>> example.pass_wchar("é")
     'é'
 
-    >>> combining_e_acute = 'e' + '\u0301'
+    >>> combining_e_acute = "e" + "\u0301"
 
     >>> combining_e_acute
     'é'
 
-    >>> combining_e_acute == 'é'
+    >>> combining_e_acute == "é"
     False
 
     >>> example.pass_wchar(combining_e_acute)
@@ -278,9 +265,9 @@ single grapheme.
 Normalizing combining characters before passing the character literal to C++
 may resolve *some* of these issues:
 
-.. code-block:: python
+.. code-block:: pycon
 
-    >>> example.pass_wchar(unicodedata.normalize('NFC', combining_e_acute))
+    >>> example.pass_wchar(unicodedata.normalize("NFC", combining_e_acute))
     'é'
 
 In some languages (Thai for example), there are `graphemes that cannot be
diff --git a/3rdparty/pybind11/docs/advanced/classes.rst b/3rdparty/pybind11/docs/advanced/classes.rst
index 4927902069..01a490b721 100644
--- a/3rdparty/pybind11/docs/advanced/classes.rst
+++ b/3rdparty/pybind11/docs/advanced/classes.rst
@@ -9,7 +9,7 @@ that you are already familiar with the basics from :doc:`/classes`.
 Overriding virtual functions in Python
 ======================================
 
-Suppose that a C++ class or interface has a virtual function that we'd like to
+Suppose that a C++ class or interface has a virtual function that we'd like
 to override from within Python (we'll focus on the class ``Animal``; ``Dog`` is
 given as a specific example of how one would do this with traditional C++
 code).
@@ -133,14 +133,14 @@ a virtual method call.
     >>> from example import *
     >>> d = Dog()
     >>> call_go(d)
-    u'woof! woof! woof! '
+    'woof! woof! woof! '
     >>> class Cat(Animal):
     ...     def go(self, n_times):
-    ...             return "meow! " * n_times
+    ...         return "meow! " * n_times
     ...
     >>> c = Cat()
     >>> call_go(c)
-    u'meow! meow! meow! '
+    'meow! meow! meow! '
 
 If you are defining a custom constructor in a derived Python class, you *must*
 ensure that you explicitly call the bound C++ constructor using ``__init__``,
@@ -159,8 +159,9 @@ Here is an example:
 
     class Dachshund(Dog):
         def __init__(self, name):
-            Dog.__init__(self) # Without this, a TypeError is raised.
+            Dog.__init__(self)  # Without this, a TypeError is raised.
             self.name = name
+
         def bark(self):
             return "yap!"
 
@@ -259,7 +260,7 @@ override the ``name()`` method):
 
 .. note::
 
-    Note the trailing commas in the ``PYBIND11_OVERIDE`` calls to ``name()``
+    Note the trailing commas in the ``PYBIND11_OVERRIDE`` calls to ``name()``
     and ``bark()``. These are needed to portably implement a trampoline for a
     function that does not take any arguments. For functions that take
     a nonzero number of arguments, the trailing comma must be omitted.
@@ -804,7 +805,7 @@ to bind these two functions:
             }
         ));
 
-The ``__setstate__`` part of the ``py::picke()`` definition follows the same
+The ``__setstate__`` part of the ``py::pickle()`` definition follows the same
 rules as the single-argument version of ``py::init()``. The return type can be
 a value, pointer or holder type. See :ref:`custom_constructors` for details.
 
@@ -812,26 +813,21 @@ An instance can now be pickled as follows:
 
 .. code-block:: python
 
-    try:
-        import cPickle as pickle  # Use cPickle on Python 2.7
-    except ImportError:
-        import pickle
+    import pickle
 
     p = Pickleable("test_value")
     p.setExtra(15)
-    data = pickle.dumps(p, 2)
+    data = pickle.dumps(p)
 
 
 .. note::
-    Note that only the cPickle module is supported on Python 2.7.
-
-    The second argument to ``dumps`` is also crucial: it selects the pickle
-    protocol version 2, since the older version 1 is not supported. Newer
-    versions are also fine—for instance, specify ``-1`` to always use the
-    latest available version. Beware: failure to follow these instructions
-    will cause important pybind11 memory allocation routines to be skipped
-    during unpickling, which will likely lead to memory corruption and/or
-    segmentation faults.
+    If given, the second argument to ``dumps`` must be 2 or larger - 0 and 1 are
+    not supported. Newer versions are also fine; for instance, specify ``-1`` to
+    always use the latest available version. Beware: failure to follow these
+    instructions will cause important pybind11 memory allocation routines to be
+    skipped during unpickling, which will likely lead to memory corruption
+    and/or segmentation faults. Python defaults to version 3 (Python 3-3.7) and
+    version 4 for Python 3.8+.
 
 .. seealso::
 
@@ -848,11 +844,9 @@ Python normally uses references in assignments. Sometimes a real copy is needed
 to prevent changing all copies. The ``copy`` module [#f5]_ provides these
 capabilities.
 
-On Python 3, a class with pickle support is automatically also (deep)copy
+A class with pickle support is automatically also (deep)copy
 compatible. However, performance can be improved by adding custom
-``__copy__`` and ``__deepcopy__`` methods. With Python 2.7, these custom methods
-are mandatory for (deep)copy compatibility, because pybind11 only supports
-cPickle.
+``__copy__`` and ``__deepcopy__`` methods.
 
 For simple classes (deep)copy can be enabled by using the copy constructor,
 which should look as follows:
@@ -1124,13 +1118,6 @@ described trampoline:
     py::class_<A, Trampoline>(m, "A") // <-- `Trampoline` here
         .def("foo", &Publicist::foo); // <-- `Publicist` here, not `Trampoline`!
 
-.. note::
-
-    MSVC 2015 has a compiler bug (fixed in version 2017) which
-    requires a more explicit function binding in the form of
-    ``.def("foo", static_cast<int (A::*)() const>(&Publicist::foo));``
-    where ``int (A::*)() const`` is the type of ``A::foo``.
-
 Binding final classes
 =====================
 
@@ -1153,12 +1140,65 @@ error:
 
     >>> class PyFinalChild(IsFinal):
     ...     pass
+    ...
     TypeError: type 'IsFinal' is not an acceptable base type
 
 .. note:: This attribute is currently ignored on PyPy
 
 .. versionadded:: 2.6
 
+Binding classes with template parameters
+========================================
+
+pybind11 can also wrap classes that have template parameters. Consider these classes:
+
+.. code-block:: cpp
+
+    struct Cat {};
+    struct Dog {};
+
+    template <typename PetType>
+    struct Cage {
+        Cage(PetType& pet);
+        PetType& get();
+    };
+
+C++ templates may only be instantiated at compile time, so pybind11 can only
+wrap instantiated templated classes. You cannot wrap a non-instantiated template:
+
+.. code-block:: cpp
+
+    // BROKEN (this will not compile)
+    py::class_<Cage>(m, "Cage");
+        .def("get", &Cage::get);
+
+You must explicitly specify each template/type combination that you want to
+wrap separately.
+
+.. code-block:: cpp
+
+    // ok
+    py::class_<Cage<Cat>>(m, "CatCage")
+        .def("get", &Cage<Cat>::get);
+
+    // ok
+    py::class_<Cage<Dog>>(m, "DogCage")
+        .def("get", &Cage<Dog>::get);
+
+If your class methods have template parameters you can wrap those as well,
+but once again each instantiation must be explicitly specified:
+
+.. code-block:: cpp
+
+    typename <typename T>
+    struct MyClass {
+        template <typename V>
+        T fn(V v);
+    };
+
+    py::class<MyClass<int>>(m, "MyClassT")
+        .def("fn", &MyClass<int>::fn<std::string>);
+
 Custom automatic downcasters
 ============================
 
@@ -1188,7 +1228,7 @@ whether a downcast is safe, you can proceed by specializing the
         std::string bark() const { return sound; }
     };
 
-    namespace pybind11 {
+    namespace PYBIND11_NAMESPACE {
         template<> struct polymorphic_type_hook<Pet> {
             static const void *get(const Pet *src, const std::type_info*& type) {
                 // note that src may be nullptr
@@ -1199,7 +1239,7 @@ whether a downcast is safe, you can proceed by specializing the
                 return src;
             }
         };
-    } // namespace pybind11
+    } // namespace PYBIND11_NAMESPACE
 
 When pybind11 wants to convert a C++ pointer of type ``Base*`` to a
 Python object, it calls ``polymorphic_type_hook<Base>::get()`` to
@@ -1247,7 +1287,7 @@ Accessing the type object
 
 You can get the type object from a C++ class that has already been registered using:
 
-.. code-block:: python
+.. code-block:: cpp
 
     py::type T_py = py::type::of<T>();
 
@@ -1259,3 +1299,37 @@ object, just like ``type(ob)`` in Python.
     Other types, like ``py::type::of<int>()``, do not work, see :ref:`type-conversions`.
 
 .. versionadded:: 2.6
+
+Custom type setup
+=================
+
+For advanced use cases, such as enabling garbage collection support, you may
+wish to directly manipulate the ``PyHeapTypeObject`` corresponding to a
+``py::class_`` definition.
+
+You can do that using ``py::custom_type_setup``:
+
+.. code-block:: cpp
+
+   struct OwnsPythonObjects {
+       py::object value = py::none();
+   };
+   py::class_<OwnsPythonObjects> cls(
+       m, "OwnsPythonObjects", py::custom_type_setup([](PyHeapTypeObject *heap_type) {
+           auto *type = &heap_type->ht_type;
+           type->tp_flags |= Py_TPFLAGS_HAVE_GC;
+           type->tp_traverse = [](PyObject *self_base, visitproc visit, void *arg) {
+               auto &self = py::cast<OwnsPythonObjects&>(py::handle(self_base));
+               Py_VISIT(self.value.ptr());
+               return 0;
+           };
+           type->tp_clear = [](PyObject *self_base) {
+               auto &self = py::cast<OwnsPythonObjects&>(py::handle(self_base));
+               self.value = py::none();
+               return 0;
+           };
+       }));
+   cls.def(py::init<>());
+   cls.def_readwrite("value", &OwnsPythonObjects::value);
+
+.. versionadded:: 2.8
diff --git a/3rdparty/pybind11/docs/advanced/embedding.rst b/3rdparty/pybind11/docs/advanced/embedding.rst
index dfdaad2d7f..dd980d483a 100644
--- a/3rdparty/pybind11/docs/advanced/embedding.rst
+++ b/3rdparty/pybind11/docs/advanced/embedding.rst
@@ -40,15 +40,15 @@ The essential structure of the ``main.cpp`` file looks like this:
     }
 
 The interpreter must be initialized before using any Python API, which includes
-all the functions and classes in pybind11. The RAII guard class `scoped_interpreter`
+all the functions and classes in pybind11. The RAII guard class ``scoped_interpreter``
 takes care of the interpreter lifetime. After the guard is destroyed, the interpreter
 shuts down and clears its memory. No Python functions can be called after this.
 
 Executing Python code
 =====================
 
-There are a few different ways to run Python code. One option is to use `eval`,
-`exec` or `eval_file`, as explained in :ref:`eval`. Here is a quick example in
+There are a few different ways to run Python code. One option is to use ``eval``,
+``exec`` or ``eval_file``, as explained in :ref:`eval`. Here is a quick example in
 the context of an executable with an embedded interpreter:
 
 .. code-block:: cpp
@@ -108,7 +108,7 @@ The two approaches can also be combined:
 Importing modules
 =================
 
-Python modules can be imported using `module_::import()`:
+Python modules can be imported using ``module_::import()``:
 
 .. code-block:: cpp
 
@@ -122,6 +122,7 @@ embedding the interpreter. This makes it easy to import local Python files:
 
     """calc.py located in the working directory"""
 
+
     def add(i, j):
         return i + j
 
@@ -133,7 +134,7 @@ embedding the interpreter. This makes it easy to import local Python files:
     int n = result.cast<int>();
     assert(n == 3);
 
-Modules can be reloaded using `module_::reload()` if the source is modified e.g.
+Modules can be reloaded using ``module_::reload()`` if the source is modified e.g.
 by an external process. This can be useful in scenarios where the application
 imports a user defined data processing script which needs to be updated after
 changes by the user. Note that this function does not reload modules recursively.
@@ -143,7 +144,7 @@ changes by the user. Note that this function does not reload modules recursively
 Adding embedded modules
 =======================
 
-Embedded binary modules can be added using the `PYBIND11_EMBEDDED_MODULE` macro.
+Embedded binary modules can be added using the ``PYBIND11_EMBEDDED_MODULE`` macro.
 Note that the definition must be placed at global scope. They can be imported
 like any other module.
 
@@ -169,7 +170,7 @@ like any other module.
 
 Unlike extension modules where only a single binary module can be created, on
 the embedded side an unlimited number of modules can be added using multiple
-`PYBIND11_EMBEDDED_MODULE` definitions (as long as they have unique names).
+``PYBIND11_EMBEDDED_MODULE`` definitions (as long as they have unique names).
 
 These modules are added to Python's list of builtins, so they can also be
 imported in pure Python files loaded by the interpreter. Everything interacts
@@ -215,9 +216,9 @@ naturally:
 Interpreter lifetime
 ====================
 
-The Python interpreter shuts down when `scoped_interpreter` is destroyed. After
+The Python interpreter shuts down when ``scoped_interpreter`` is destroyed. After
 this, creating a new instance will restart the interpreter. Alternatively, the
-`initialize_interpreter` / `finalize_interpreter` pair of functions can be used
+``initialize_interpreter`` / ``finalize_interpreter`` pair of functions can be used
 to directly set the state at any time.
 
 Modules created with pybind11 can be safely re-initialized after the interpreter
@@ -229,8 +230,8 @@ global data. All the details can be found in the CPython documentation.
 
 .. warning::
 
-    Creating two concurrent `scoped_interpreter` guards is a fatal error. So is
-    calling `initialize_interpreter` for a second time after the interpreter
+    Creating two concurrent ``scoped_interpreter`` guards is a fatal error. So is
+    calling ``initialize_interpreter`` for a second time after the interpreter
     has already been initialized.
 
     Do not use the raw CPython API functions ``Py_Initialize`` and
@@ -241,7 +242,7 @@ global data. All the details can be found in the CPython documentation.
 Sub-interpreter support
 =======================
 
-Creating multiple copies of `scoped_interpreter` is not possible because it
+Creating multiple copies of ``scoped_interpreter`` is not possible because it
 represents the main Python interpreter. Sub-interpreters are something different
 and they do permit the existence of multiple interpreters. This is an advanced
 feature of the CPython API and should be handled with care. pybind11 does not
@@ -257,5 +258,5 @@ We'll just mention a couple of caveats the sub-interpreters support in pybind11:
  2. Managing multiple threads, multiple interpreters and the GIL can be
     challenging and there are several caveats here, even within the pure
     CPython API (please refer to the Python docs for details). As for
-    pybind11, keep in mind that `gil_scoped_release` and `gil_scoped_acquire`
+    pybind11, keep in mind that ``gil_scoped_release`` and ``gil_scoped_acquire``
     do not take sub-interpreters into account.
diff --git a/3rdparty/pybind11/docs/advanced/exceptions.rst b/3rdparty/pybind11/docs/advanced/exceptions.rst
index 5eae556247..2211caf5d3 100644
--- a/3rdparty/pybind11/docs/advanced/exceptions.rst
+++ b/3rdparty/pybind11/docs/advanced/exceptions.rst
@@ -43,18 +43,28 @@ at its exception handler.
 |                                      | of bounds access in ``__getitem__``, |
 |                                      | ``__setitem__``, etc.)               |
 +--------------------------------------+--------------------------------------+
-| :class:`pybind11::value_error`       | ``ValueError`` (used to indicate     |
-|                                      | wrong value passed in                |
-|                                      | ``container.remove(...)``)           |
-+--------------------------------------+--------------------------------------+
 | :class:`pybind11::key_error`         | ``KeyError`` (used to indicate out   |
 |                                      | of bounds access in ``__getitem__``, |
 |                                      | ``__setitem__`` in dict-like         |
 |                                      | objects, etc.)                       |
 +--------------------------------------+--------------------------------------+
+| :class:`pybind11::value_error`       | ``ValueError`` (used to indicate     |
+|                                      | wrong value passed in                |
+|                                      | ``container.remove(...)``)           |
++--------------------------------------+--------------------------------------+
+| :class:`pybind11::type_error`        | ``TypeError``                        |
++--------------------------------------+--------------------------------------+
+| :class:`pybind11::buffer_error`      | ``BufferError``                      |
++--------------------------------------+--------------------------------------+
+| :class:`pybind11::import_error`      | ``ImportError``                      |
++--------------------------------------+--------------------------------------+
+| :class:`pybind11::attribute_error`   | ``AttributeError``                   |
++--------------------------------------+--------------------------------------+
+| Any other exception                  | ``RuntimeError``                     |
++--------------------------------------+--------------------------------------+
 
 Exception translation is not bidirectional. That is, *catching* the C++
-exceptions defined above above will not trap exceptions that originate from
+exceptions defined above will not trap exceptions that originate from
 Python. For that, catch :class:`pybind11::error_already_set`. See :ref:`below
 <handling_python_exceptions_cpp>` for further details.
 
@@ -67,9 +77,10 @@ Registering custom translators
 
 If the default exception conversion policy described above is insufficient,
 pybind11 also provides support for registering custom exception translators.
-To register a simple exception conversion that translates a C++ exception into
-a new Python exception using the C++ exception's ``what()`` method, a helper
-function is available:
+Similar to pybind11 classes, exception translators can be local to the module
+they are defined in or global to the entire python session.  To register a simple
+exception conversion that translates a C++ exception into a new Python exception
+using the C++ exception's ``what()`` method, a helper function is available:
 
 .. code-block:: cpp
 
@@ -79,29 +90,39 @@ This call creates a Python exception class with the name ``PyExp`` in the given
 module and automatically converts any encountered exceptions of type ``CppExp``
 into Python exceptions of type ``PyExp``.
 
+A matching function is available for registering a local exception translator:
+
+.. code-block:: cpp
+
+    py::register_local_exception<CppExp>(module, "PyExp");
+
+
 It is possible to specify base class for the exception using the third
-parameter, a `handle`:
+parameter, a ``handle``:
 
 .. code-block:: cpp
 
     py::register_exception<CppExp>(module, "PyExp", PyExc_RuntimeError);
+    py::register_local_exception<CppExp>(module, "PyExp", PyExc_RuntimeError);
 
-Then `PyExp` can be caught both as `PyExp` and `RuntimeError`.
+Then ``PyExp`` can be caught both as ``PyExp`` and ``RuntimeError``.
 
 The class objects of the built-in Python exceptions are listed in the Python
 documentation on `Standard Exceptions <https://docs.python.org/3/c-api/exceptions.html#standard-exceptions>`_.
-The default base class is `PyExc_Exception`.
+The default base class is ``PyExc_Exception``.
 
-When more advanced exception translation is needed, the function
-``py::register_exception_translator(translator)`` can be used to register
+When more advanced exception translation is needed, the functions
+``py::register_exception_translator(translator)`` and
+``py::register_local_exception_translator(translator)`` can be used to register
 functions that can translate arbitrary exception types (and which may include
-additional logic to do so).  The function takes a stateless callable (e.g.  a
+additional logic to do so).  The functions takes a stateless callable (e.g. a
 function pointer or a lambda function without captured variables) with the call
 signature ``void(std::exception_ptr)``.
 
 When a C++ exception is thrown, the registered exception translators are tried
 in reverse order of registration (i.e. the last registered translator gets the
-first shot at handling the exception).
+first shot at handling the exception). All local translators will be tried
+before a global translator is tried.
 
 Inside the translator, ``std::rethrow_exception`` should be used within
 a try block to re-throw the exception.  One or more catch clauses to catch
@@ -156,6 +177,57 @@ section.
     may be explicitly (re-)thrown to delegate it to the other,
     previously-declared existing exception translators.
 
+    Note that ``libc++`` and ``libstdc++`` `behave differently <https://stackoverflow.com/questions/19496643/using-clang-fvisibility-hidden-and-typeinfo-and-type-erasure/28827430>`_
+    with ``-fvisibility=hidden``. Therefore exceptions that are used across ABI boundaries need to be explicitly exported, as exercised in ``tests/test_exceptions.h``.
+    See also: "Problems with C++ exceptions" under `GCC Wiki <https://gcc.gnu.org/wiki/Visibility>`_.
+
+
+Local vs Global Exception Translators
+=====================================
+
+When a global exception translator is registered, it will be applied across all
+modules in the reverse order of registration. This can create behavior where the
+order of module import influences how exceptions are translated.
+
+If module1 has the following translator:
+
+.. code-block:: cpp
+
+      py::register_exception_translator([](std::exception_ptr p) {
+        try {
+            if (p) std::rethrow_exception(p);
+        } catch (const std::invalid_argument &e) {
+            PyErr_SetString("module1 handled this")
+        }
+      }
+
+and module2 has the following similar translator:
+
+.. code-block:: cpp
+
+      py::register_exception_translator([](std::exception_ptr p) {
+        try {
+            if (p) std::rethrow_exception(p);
+        } catch (const std::invalid_argument &e) {
+            PyErr_SetString("module2 handled this")
+        }
+      }
+
+then which translator handles the invalid_argument will be determined by the
+order that module1 and module2 are imported. Since exception translators are
+applied in the reverse order of registration, which ever module was imported
+last will "win" and that translator will be applied.
+
+If there are multiple pybind11 modules that share exception types (either
+standard built-in or custom) loaded into a single python instance and
+consistent error handling behavior is needed, then local translators should be
+used.
+
+Changing the previous example to use ``register_local_exception_translator``
+would mean that when invalid_argument is thrown in the module2 code, the
+module2 translator will always handle it, while in module1, the module1
+translator will do the same.
+
 .. _handling_python_exceptions_cpp:
 
 Handling exceptions from Python in C++
@@ -188,7 +260,7 @@ For example:
     } catch (py::error_already_set &e) {
         if (e.matches(PyExc_FileNotFoundError)) {
             py::print("missing.txt not found");
-        } else if (e.match(PyExc_PermissionError)) {
+        } else if (e.matches(PyExc_PermissionError)) {
             py::print("missing.txt found but not accessible");
         } else {
             throw;
@@ -253,6 +325,34 @@ Alternately, to ignore the error, call `PyErr_Clear
 Any Python error must be thrown or cleared, or Python/pybind11 will be left in
 an invalid state.
 
+Chaining exceptions ('raise from')
+==================================
+
+Python has a mechanism for indicating that exceptions were caused by other
+exceptions:
+
+.. code-block:: py
+
+    try:
+        print(1 / 0)
+    except Exception as exc:
+        raise RuntimeError("could not divide by zero") from exc
+
+To do a similar thing in pybind11, you can use the ``py::raise_from`` function. It
+sets the current python error indicator, so to continue propagating the exception
+you should ``throw py::error_already_set()``.
+
+.. code-block:: cpp
+
+    try {
+        py::eval("print(1 / 0"));
+    } catch (py::error_already_set &e) {
+        py::raise_from(e, PyExc_RuntimeError, "could not divide by zero");
+        throw py::error_already_set();
+    }
+
+.. versionadded:: 2.8
+
 .. _unraisable_exceptions:
 
 Handling unraisable exceptions
diff --git a/3rdparty/pybind11/docs/advanced/functions.rst b/3rdparty/pybind11/docs/advanced/functions.rst
index ebdff9c93d..69e3d8a1df 100644
--- a/3rdparty/pybind11/docs/advanced/functions.rst
+++ b/3rdparty/pybind11/docs/advanced/functions.rst
@@ -50,7 +50,7 @@ implied transfer of ownership, i.e.:
 
 .. code-block:: cpp
 
-    m.def("get_data", &get_data, return_value_policy::reference);
+    m.def("get_data", &get_data, py::return_value_policy::reference);
 
 On the other hand, this is not the right policy for many other situations,
 where ignoring ownership could lead to resource leaks.
@@ -90,17 +90,18 @@ The following table provides an overview of available policies:
 |                                                  | return value is referenced by Python. This is the default policy for       |
 |                                                  | property getters created via ``def_property``, ``def_readwrite``, etc.     |
 +--------------------------------------------------+----------------------------------------------------------------------------+
-| :enum:`return_value_policy::automatic`           | **Default policy.** This policy falls back to the policy                   |
+| :enum:`return_value_policy::automatic`           | This policy falls back to the policy                                       |
 |                                                  | :enum:`return_value_policy::take_ownership` when the return value is a     |
 |                                                  | pointer. Otherwise, it uses :enum:`return_value_policy::move` or           |
 |                                                  | :enum:`return_value_policy::copy` for rvalue and lvalue references,        |
 |                                                  | respectively. See above for a description of what all of these different   |
-|                                                  | policies do.                                                               |
+|                                                  | policies do. This is the default policy for ``py::class_``-wrapped types.  |
 +--------------------------------------------------+----------------------------------------------------------------------------+
 | :enum:`return_value_policy::automatic_reference` | As above, but use policy :enum:`return_value_policy::reference` when the   |
 |                                                  | return value is a pointer. This is the default conversion policy for       |
 |                                                  | function arguments when calling Python functions manually from C++ code    |
-|                                                  | (i.e. via handle::operator()). You probably won't need to use this.        |
+|                                                  | (i.e. via ``handle::operator()``) and the casters in ``pybind11/stl.h``.   |
+|                                                  | You probably won't need to use this explicitly.                            |
 +--------------------------------------------------+----------------------------------------------------------------------------+
 
 Return value policies can also be applied to properties:
@@ -119,7 +120,7 @@ targeted arguments can be passed through the :class:`cpp_function` constructor:
 .. code-block:: cpp
 
     class_<MyClass>(m, "MyClass")
-        .def_property("data"
+        .def_property("data",
             py::cpp_function(&MyClass::getData, py::return_value_policy::copy),
             py::cpp_function(&MyClass::setData)
         );
@@ -182,6 +183,9 @@ relies on the ability to create a *weak reference* to the nurse object. When
 the nurse object is not a pybind11-registered type and does not support weak
 references, an exception will be thrown.
 
+If you use an incorrect argument index, you will get a ``RuntimeError`` saying
+``Could not activate keep_alive!``. You should review the indices you're using.
+
 Consider the following example: here, the binding code for a list append
 operation ties the lifetime of the newly added element to the underlying
 container:
@@ -228,7 +232,7 @@ is equivalent to the following pseudocode:
     });
 
 The only requirement is that ``T`` is default-constructible, but otherwise any
-scope guard will work. This is very useful in combination with `gil_scoped_release`.
+scope guard will work. This is very useful in combination with ``gil_scoped_release``.
 See :ref:`gil`.
 
 Multiple guards can also be specified as ``py::call_guard<T1, T2, T3...>``. The
@@ -251,7 +255,7 @@ For instance, the following statement iterates over a Python ``dict``:
 
 .. code-block:: cpp
 
-    void print_dict(py::dict dict) {
+    void print_dict(const py::dict& dict) {
         /* Easily interact with Python types */
         for (auto item : dict)
             std::cout << "key=" << std::string(py::str(item.first)) << ", "
@@ -268,7 +272,7 @@ And used in Python as usual:
 
 .. code-block:: pycon
 
-    >>> print_dict({'foo': 123, 'bar': 'hello'})
+    >>> print_dict({"foo": 123, "bar": "hello"})
     key=foo, value=123
     key=bar, value=hello
 
@@ -289,7 +293,7 @@ Such functions can also be created using pybind11:
 
 .. code-block:: cpp
 
-   void generic(py::args args, py::kwargs kwargs) {
+   void generic(py::args args, const py::kwargs& kwargs) {
        /// .. do something with args
        if (kwargs)
            /// .. do something with kwargs
@@ -302,8 +306,9 @@ The class ``py::args`` derives from ``py::tuple`` and ``py::kwargs`` derives
 from ``py::dict``.
 
 You may also use just one or the other, and may combine these with other
-arguments as long as the ``py::args`` and ``py::kwargs`` arguments are the last
-arguments accepted by the function.
+arguments.  Note, however, that ``py::kwargs`` must always be the last argument
+of the function, and ``py::args`` implies that any further arguments are
+keyword-only (see :ref:`keyword_only_arguments`).
 
 Please refer to the other examples for details on how to iterate over these,
 and on how to cast their entries into C++ objects. A demonstration is also
@@ -362,10 +367,12 @@ like so:
     py::class_<MyClass>("MyClass")
         .def("myFunction", py::arg("arg") = static_cast<SomeType *>(nullptr));
 
+.. _keyword_only_arguments:
+
 Keyword-only arguments
 ======================
 
-Python 3 introduced keyword-only arguments by specifying an unnamed ``*``
+Python implements keyword-only arguments by specifying an unnamed ``*``
 argument in a function definition:
 
 .. code-block:: python
@@ -373,10 +380,11 @@ argument in a function definition:
     def f(a, *, b):  # a can be positional or via keyword; b must be via keyword
         pass
 
+
     f(a=1, b=2)  # good
     f(b=2, a=1)  # good
-    f(1, b=2)    # good
-    f(1, 2)      # TypeError: f() takes 1 positional argument but 2 were given
+    f(1, b=2)  # good
+    f(1, 2)  # TypeError: f() takes 1 positional argument but 2 were given
 
 Pybind11 provides a ``py::kw_only`` object that allows you to implement
 the same behaviour by specifying the object between positional and keyword-only
@@ -387,11 +395,19 @@ argument annotations when registering the function:
     m.def("f", [](int a, int b) { /* ... */ },
           py::arg("a"), py::kw_only(), py::arg("b"));
 
-Note that you currently cannot combine this with a ``py::args`` argument.  This
-feature does *not* require Python 3 to work.
-
 .. versionadded:: 2.6
 
+A ``py::args`` argument implies that any following arguments are keyword-only,
+as if ``py::kw_only()`` had been specified in the same relative location of the
+argument list as the ``py::args`` argument.  The ``py::kw_only()`` may be
+included to be explicit about this, but is not required.
+
+.. versionchanged:: 2.9
+   This can now be combined with ``py::args``. Before, ``py::args`` could only
+   occur at the end of the argument list, or immediately before a ``py::kwargs``
+   argument at the end.
+
+
 Positional-only arguments
 =========================
 
@@ -524,6 +540,8 @@ The default behaviour when the tag is unspecified is to allow ``None``.
     not allow ``None`` as argument.  To pass optional argument of these copied types consider
     using ``std::optional<T>``
 
+.. _overload_resolution:
+
 Overload resolution order
 =========================
 
@@ -559,3 +577,38 @@ prefers earlier-defined overloads to later-defined ones.
 .. versionadded:: 2.6
 
     The ``py::prepend()`` tag.
+
+Binding functions with template parameters
+==========================================
+
+You can bind functions that have template parameters. Here's a function:
+
+.. code-block:: cpp
+
+    template <typename T>
+    void set(T t);
+
+C++ templates cannot be instantiated at runtime, so you cannot bind the
+non-instantiated function:
+
+.. code-block:: cpp
+
+    // BROKEN (this will not compile)
+    m.def("set", &set);
+
+You must bind each instantiated function template separately. You may bind
+each instantiation with the same name, which will be treated the same as
+an overloaded function:
+
+.. code-block:: cpp
+
+    m.def("set", &set<int>);
+    m.def("set", &set<std::string>);
+
+Sometimes it's more clear to bind them with separate names, which is also
+an option:
+
+.. code-block:: cpp
+
+    m.def("setInt", &set<int>);
+    m.def("setString", &set<std::string>);
diff --git a/3rdparty/pybind11/docs/advanced/misc.rst b/3rdparty/pybind11/docs/advanced/misc.rst
index b3f3b2265a..edab15fcb7 100644
--- a/3rdparty/pybind11/docs/advanced/misc.rst
+++ b/3rdparty/pybind11/docs/advanced/misc.rst
@@ -84,7 +84,7 @@ could be realized as follows (important changes highlighted):
         });
     }
 
-The ``call_go`` wrapper can also be simplified using the `call_guard` policy
+The ``call_go`` wrapper can also be simplified using the ``call_guard`` policy
 (see :ref:`call_policies`) which yields the same result:
 
 .. code-block:: cpp
diff --git a/3rdparty/pybind11/docs/advanced/pycpp/numpy.rst b/3rdparty/pybind11/docs/advanced/pycpp/numpy.rst
index 19ed10b3bf..07c969305d 100644
--- a/3rdparty/pybind11/docs/advanced/pycpp/numpy.rst
+++ b/3rdparty/pybind11/docs/advanced/pycpp/numpy.rst
@@ -87,7 +87,7 @@ buffer objects (e.g. a NumPy matrix).
             /* Request a buffer descriptor from Python */
             py::buffer_info info = b.request();
 
-            /* Some sanity checks ... */
+            /* Some basic validation checks ... */
             if (info.format != py::format_descriptor<Scalar>::format())
                 throw std::runtime_error("Incompatible format: expected a double array!");
 
@@ -150,8 +150,10 @@ NumPy array containing double precision values.
 
 When it is invoked with a different type (e.g. an integer or a list of
 integers), the binding code will attempt to cast the input into a NumPy array
-of the requested type. Note that this feature requires the
-:file:`pybind11/numpy.h` header to be included.
+of the requested type. This feature requires the :file:`pybind11/numpy.h`
+header to be included. Note that :file:`pybind11/numpy.h` does not depend on
+the NumPy headers, and thus can be used without declaring a build-time
+dependency on NumPy; NumPy>=1.7.0 is a runtime dependency.
 
 Data in NumPy arrays is not guaranteed to packed in a dense manner;
 furthermore, entries can be separated by arbitrary column and row strides.
@@ -169,6 +171,31 @@ template parameter, and it ensures that non-conforming arguments are converted
 into an array satisfying the specified requirements instead of trying the next
 function overload.
 
+There are several methods on arrays; the methods listed below under references
+work, as well as the following functions based on the NumPy API:
+
+- ``.dtype()`` returns the type of the contained values.
+
+- ``.strides()`` returns a pointer to the strides of the array (optionally pass
+  an integer axis to get a number).
+
+- ``.flags()`` returns the flag settings. ``.writable()`` and ``.owndata()``
+  are directly available.
+
+- ``.offset_at()`` returns the offset (optionally pass indices).
+
+- ``.squeeze()`` returns a view with length-1 axes removed.
+
+- ``.view(dtype)`` returns a view of the array with a different dtype.
+
+- ``.reshape({i, j, ...})`` returns a view of the array with a different shape.
+  ``.resize({...})`` is also available.
+
+- ``.index_at(i, j, ...)`` gets the count from the beginning to a given index.
+
+
+There are also several methods for getting references (described below).
+
 Structured types
 ================
 
@@ -231,8 +258,8 @@ by the compiler. The result is returned as a NumPy array of type
 
 .. code-block:: pycon
 
-    >>> x = np.array([[1, 3],[5, 7]])
-    >>> y = np.array([[2, 4],[6, 8]])
+    >>> x = np.array([[1, 3], [5, 7]])
+    >>> y = np.array([[2, 4], [6, 8]])
     >>> z = 3
     >>> result = vectorized_func(x, y, z)
 
@@ -343,21 +370,21 @@ The returned proxy object supports some of the same methods as ``py::array`` so
 that it can be used as a drop-in replacement for some existing, index-checked
 uses of ``py::array``:
 
-- ``r.ndim()`` returns the number of dimensions
+- ``.ndim()`` returns the number of dimensions
 
-- ``r.data(1, 2, ...)`` and ``r.mutable_data(1, 2, ...)``` returns a pointer to
+- ``.data(1, 2, ...)`` and ``r.mutable_data(1, 2, ...)``` returns a pointer to
   the ``const T`` or ``T`` data, respectively, at the given indices.  The
   latter is only available to proxies obtained via ``a.mutable_unchecked()``.
 
-- ``itemsize()`` returns the size of an item in bytes, i.e. ``sizeof(T)``.
+- ``.itemsize()`` returns the size of an item in bytes, i.e. ``sizeof(T)``.
 
-- ``ndim()`` returns the number of dimensions.
+- ``.ndim()`` returns the number of dimensions.
 
-- ``shape(n)`` returns the size of dimension ``n``
+- ``.shape(n)`` returns the size of dimension ``n``
 
-- ``size()`` returns the total number of elements (i.e. the product of the shapes).
+- ``.size()`` returns the total number of elements (i.e. the product of the shapes).
 
-- ``nbytes()`` returns the number of bytes used by the referenced elements
+- ``.nbytes()`` returns the number of bytes used by the referenced elements
   (i.e. ``itemsize()`` times ``size()``).
 
 .. seealso::
@@ -368,15 +395,13 @@ uses of ``py::array``:
 Ellipsis
 ========
 
-Python 3 provides a convenient ``...`` ellipsis notation that is often used to
+Python provides a convenient ``...`` ellipsis notation that is often used to
 slice multidimensional arrays. For instance, the following snippet extracts the
 middle dimensions of a tensor with the first and last index set to zero.
-In Python 2, the syntactic sugar ``...`` is not available, but the singleton
-``Ellipsis`` (of type ``ellipsis``) can still be used directly.
 
 .. code-block:: python
 
-   a = # a NumPy array
+   a = ...  # a NumPy array
    b = a[0, ..., 0]
 
 The function ``py::ellipsis()`` function can be used to perform the same
@@ -387,8 +412,6 @@ operation on the C++ side:
    py::array a = /* A NumPy array */;
    py::array b = a[py::make_tuple(0, py::ellipsis(), 0)];
 
-.. versionchanged:: 2.6
-   ``py::ellipsis()`` is now also avaliable in Python 2.
 
 Memory view
 ===========
@@ -410,7 +433,7 @@ following:
             { 2, 4 },                                  // shape (rows, cols)
             { sizeof(uint8_t) * 4, sizeof(uint8_t) }   // strides in bytes
         );
-    })
+    });
 
 This approach is meant for providing a ``memoryview`` for a C/C++ buffer not
 managed by Python. The user is responsible for managing the lifetime of the
@@ -426,11 +449,7 @@ We can also use ``memoryview::from_memory`` for a simple 1D contiguous buffer:
             buffer,               // buffer pointer
             sizeof(uint8_t) * 8   // buffer size
         );
-    })
-
-.. note::
-
-    ``memoryview::from_memory`` is not available in Python 2.
+    });
 
 .. versionchanged:: 2.6
     ``memoryview::from_memory`` added.
diff --git a/3rdparty/pybind11/docs/advanced/pycpp/object.rst b/3rdparty/pybind11/docs/advanced/pycpp/object.rst
index 6c7525ceaf..93e1a94d8f 100644
--- a/3rdparty/pybind11/docs/advanced/pycpp/object.rst
+++ b/3rdparty/pybind11/docs/advanced/pycpp/object.rst
@@ -20,6 +20,40 @@ Available types include :class:`handle`, :class:`object`, :class:`bool_`,
     Be sure to review the :ref:`pytypes_gotchas` before using this heavily in
     your C++ API.
 
+.. _instantiating_compound_types:
+
+Instantiating compound Python types from C++
+============================================
+
+Dictionaries can be initialized in the :class:`dict` constructor:
+
+.. code-block:: cpp
+
+    using namespace pybind11::literals; // to bring in the `_a` literal
+    py::dict d("spam"_a=py::none(), "eggs"_a=42);
+
+A tuple of python objects can be instantiated using :func:`py::make_tuple`:
+
+.. code-block:: cpp
+
+    py::tuple tup = py::make_tuple(42, py::none(), "spam");
+
+Each element is converted to a supported Python type.
+
+A `simple namespace`_ can be instantiated using
+
+.. code-block:: cpp
+
+    using namespace pybind11::literals;  // to bring in the `_a` literal
+    py::object SimpleNamespace = py::module_::import("types").attr("SimpleNamespace");
+    py::object ns = SimpleNamespace("spam"_a=py::none(), "eggs"_a=42);
+
+Attributes on a namespace can be modified with the :func:`py::delattr`,
+:func:`py::getattr`, and :func:`py::setattr` functions. Simple namespaces can
+be useful as lightweight stand-ins for class instances.
+
+.. _simple namespace: https://docs.python.org/3/library/types.html#types.SimpleNamespace
+
 .. _casting_back_and_forth:
 
 Casting back and forth
@@ -30,7 +64,7 @@ types to Python, which can be done using :func:`py::cast`:
 
 .. code-block:: cpp
 
-    MyClass *cls = ..;
+    MyClass *cls = ...;
     py::object obj = py::cast(cls);
 
 The reverse direction uses the following syntax:
@@ -132,6 +166,7 @@ Keyword arguments are also supported. In Python, there is the usual call syntax:
     def f(number, say, to):
         ...  # function code
 
+
     f(1234, say="hello", to=some_instance)  # keyword call in Python
 
 In C++, the same call can be made using:
diff --git a/3rdparty/pybind11/docs/advanced/pycpp/utilities.rst b/3rdparty/pybind11/docs/advanced/pycpp/utilities.rst
index c15051fb96..af0f9cb2b0 100644
--- a/3rdparty/pybind11/docs/advanced/pycpp/utilities.rst
+++ b/3rdparty/pybind11/docs/advanced/pycpp/utilities.rst
@@ -28,7 +28,7 @@ Capturing standard output from ostream
 
 Often, a library will use the streams ``std::cout`` and ``std::cerr`` to print,
 but this does not play well with Python's standard ``sys.stdout`` and ``sys.stderr``
-redirection. Replacing a library's printing with `py::print <print>` may not
+redirection. Replacing a library's printing with ``py::print <print>`` may not
 be feasible. This can be fixed using a guard around the library function that
 redirects output to the corresponding Python streams:
 
@@ -47,15 +47,26 @@ redirects output to the corresponding Python streams:
         call_noisy_func();
     });
 
+.. warning::
+
+    The implementation in ``pybind11/iostream.h`` is NOT thread safe. Multiple
+    threads writing to a redirected ostream concurrently cause data races
+    and potentially buffer overflows. Therefore it is currently a requirement
+    that all (possibly) concurrent redirected ostream writes are protected by
+    a mutex. #HelpAppreciated: Work on iostream.h thread safety. For more
+    background see the discussions under
+    `PR #2982 <https://github.com/pybind/pybind11/pull/2982>`_ and
+    `PR #2995 <https://github.com/pybind/pybind11/pull/2995>`_.
+
 This method respects flushes on the output streams and will flush if needed
 when the scoped guard is destroyed. This allows the output to be redirected in
 real time, such as to a Jupyter notebook. The two arguments, the C++ stream and
 the Python output, are optional, and default to standard output if not given. An
-extra type, `py::scoped_estream_redirect <scoped_estream_redirect>`, is identical
+extra type, ``py::scoped_estream_redirect <scoped_estream_redirect>``, is identical
 except for defaulting to ``std::cerr`` and ``sys.stderr``; this can be useful with
-`py::call_guard`, which allows multiple items, but uses the default constructor:
+``py::call_guard``, which allows multiple items, but uses the default constructor:
 
-.. code-block:: py
+.. code-block:: cpp
 
     // Alternative: Call single function using call guard
     m.def("noisy_func", &call_noisy_function,
@@ -63,7 +74,7 @@ except for defaulting to ``std::cerr`` and ``sys.stderr``; this can be useful wi
                          py::scoped_estream_redirect>());
 
 The redirection can also be done in Python with the addition of a context
-manager, using the `py::add_ostream_redirect() <add_ostream_redirect>` function:
+manager, using the ``py::add_ostream_redirect() <add_ostream_redirect>`` function:
 
 .. code-block:: cpp
 
@@ -92,7 +103,7 @@ arguments to disable one of the streams if needed.
 Evaluating Python expressions from strings and files
 ====================================================
 
-pybind11 provides the `eval`, `exec` and `eval_file` functions to evaluate
+pybind11 provides the ``eval``, ``exec`` and ``eval_file`` functions to evaluate
 Python expressions and statements. The following example illustrates how they
 can be used.
 
diff --git a/3rdparty/pybind11/docs/advanced/smart_ptrs.rst b/3rdparty/pybind11/docs/advanced/smart_ptrs.rst
index da57748ca5..3c40ce1237 100644
--- a/3rdparty/pybind11/docs/advanced/smart_ptrs.rst
+++ b/3rdparty/pybind11/docs/advanced/smart_ptrs.rst
@@ -77,6 +77,7 @@ segmentation fault).
 .. code-block:: python
 
    from example import Parent
+
    print(Parent().get_child())
 
 The problem is that ``Parent::get_child()`` returns a pointer to an instance of
@@ -156,7 +157,7 @@ specialized:
     PYBIND11_DECLARE_HOLDER_TYPE(T, SmartPtr<T>);
 
     // Only needed if the type's `.get()` goes by another name
-    namespace pybind11 { namespace detail {
+    namespace PYBIND11_NAMESPACE { namespace detail {
         template <typename T>
         struct holder_helper<SmartPtr<T>> { // <-- specialization
             static const T *get(const SmartPtr<T> &p) { return p.getPointer(); }
diff --git a/3rdparty/pybind11/docs/basics.rst b/3rdparty/pybind11/docs/basics.rst
index b9d386c3f3..e9b24c7fa7 100644
--- a/3rdparty/pybind11/docs/basics.rst
+++ b/3rdparty/pybind11/docs/basics.rst
@@ -32,8 +32,7 @@ The last line will both compile and run the tests.
 Windows
 -------
 
-On Windows, only **Visual Studio 2015** and newer are supported since pybind11 relies
-on various C++11 language features that break older versions of Visual Studio.
+On Windows, only **Visual Studio 2017** and newer are supported.
 
 .. Note::
 
@@ -109,7 +108,7 @@ a file named :file:`example.cpp` with the following contents:
     PYBIND11_MODULE(example, m) {
         m.doc() = "pybind11 example plugin"; // optional module docstring
 
-        m.def("add", &add, "A function which adds two numbers");
+        m.def("add", &add, "A function that adds two numbers");
     }
 
 .. [#f1] In practice, implementation and binding code will generally be located
@@ -136,7 +135,14 @@ On Linux, the above example can be compiled using the following command:
 
 .. code-block:: bash
 
-    $ c++ -O3 -Wall -shared -std=c++11 -fPIC `python3 -m pybind11 --includes` example.cpp -o example`python3-config --extension-suffix`
+    $ c++ -O3 -Wall -shared -std=c++11 -fPIC $(python3 -m pybind11 --includes) example.cpp -o example$(python3-config --extension-suffix)
+
+.. note::
+
+    If you used :ref:`include_as_a_submodule` to get the pybind11 source, then
+    use ``$(python3-config --includes) -Iextern/pybind11/include`` instead of
+    ``$(python3 -m pybind11 --includes)`` in the above compilation, as
+    explained in :ref:`building_manually`.
 
 For more details on the required compiler flags on Linux and macOS, see
 :ref:`building_manually`. For complete cross-platform compilation instructions,
@@ -159,12 +165,12 @@ load and execute the example:
 .. code-block:: pycon
 
     $ python
-    Python 2.7.10 (default, Aug 22 2015, 20:33:39)
-    [GCC 4.2.1 Compatible Apple LLVM 7.0.0 (clang-700.0.59.1)] on darwin
+    Python 3.9.10 (main, Jan 15 2022, 11:48:04)
+    [Clang 13.0.0 (clang-1300.0.29.3)] on darwin
     Type "help", "copyright", "credits" or "license" for more information.
     >>> import example
     >>> example.add(1, 2)
-    3L
+    3
     >>>
 
 .. _keyword_args:
diff --git a/3rdparty/pybind11/docs/benchmark.py b/3rdparty/pybind11/docs/benchmark.py
index 33d78fb4e6..2150b6ca78 100644
--- a/3rdparty/pybind11/docs/benchmark.py
+++ b/3rdparty/pybind11/docs/benchmark.py
@@ -1,8 +1,6 @@
-# -*- coding: utf-8 -*-
-import random
-import os
-import time
 import datetime as dt
+import os
+import random
 
 nfns = 4  # Functions per class
 nargs = 4  # Arguments per function
@@ -13,20 +11,20 @@ def generate_dummy_code_pybind11(nclasses=10):
     bindings = ""
 
     for cl in range(nclasses):
-        decl += "class cl%03i;\n" % cl
+        decl += f"class cl{cl:03};\n"
     decl += "\n"
 
     for cl in range(nclasses):
-        decl += "class cl%03i {\n" % cl
+        decl += f"class {cl:03} {{\n"
         decl += "public:\n"
-        bindings += '    py::class_<cl%03i>(m, "cl%03i")\n' % (cl, cl)
+        bindings += f'    py::class_<cl{cl:03}>(m, "cl{cl:03}")\n'
         for fn in range(nfns):
             ret = random.randint(0, nclasses - 1)
             params = [random.randint(0, nclasses - 1) for i in range(nargs)]
-            decl += "    cl%03i *fn_%03i(" % (ret, fn)
-            decl += ", ".join("cl%03i *" % p for p in params)
+            decl += f"    cl{ret:03} *fn_{fn:03}("
+            decl += ", ".join(f"cl{p:03} *" for p in params)
             decl += ");\n"
-            bindings += '        .def("fn_%03i", &cl%03i::fn_%03i)\n' % (fn, cl, fn)
+            bindings += f'        .def("fn_{fn:03}", &cl{cl:03}::fn_{fn:03})\n'
         decl += "};\n\n"
         bindings += "        ;\n"
 
@@ -44,23 +42,20 @@ def generate_dummy_code_boost(nclasses=10):
     bindings = ""
 
     for cl in range(nclasses):
-        decl += "class cl%03i;\n" % cl
+        decl += f"class cl{cl:03};\n"
     decl += "\n"
 
     for cl in range(nclasses):
         decl += "class cl%03i {\n" % cl
         decl += "public:\n"
-        bindings += '    py::class_<cl%03i>("cl%03i")\n' % (cl, cl)
+        bindings += f'    py::class_<cl{cl:03}>("cl{cl:03}")\n'
         for fn in range(nfns):
             ret = random.randint(0, nclasses - 1)
             params = [random.randint(0, nclasses - 1) for i in range(nargs)]
-            decl += "    cl%03i *fn_%03i(" % (ret, fn)
-            decl += ", ".join("cl%03i *" % p for p in params)
+            decl += f"    cl{ret:03} *fn_{fn:03}("
+            decl += ", ".join(f"cl{p:03} *" for p in params)
             decl += ");\n"
-            bindings += (
-                '        .def("fn_%03i", &cl%03i::fn_%03i, py::return_value_policy<py::manage_new_object>())\n'
-                % (fn, cl, fn)
-            )
+            bindings += f'        .def("fn_{fn:03}", &cl{cl:03}::fn_{fn:03}, py::return_value_policy<py::manage_new_object>())\n'
         decl += "};\n\n"
         bindings += "        ;\n"
 
@@ -76,7 +71,7 @@ def generate_dummy_code_boost(nclasses=10):
 for codegen in [generate_dummy_code_pybind11, generate_dummy_code_boost]:
     print("{")
     for i in range(0, 10):
-        nclasses = 2 ** i
+        nclasses = 2**i
         with open("test.cpp", "w") as f:
             f.write(codegen(nclasses))
         n1 = dt.datetime.now()
diff --git a/3rdparty/pybind11/docs/changelog.rst b/3rdparty/pybind11/docs/changelog.rst
index 561baa5f1f..9c8ff423f4 100644
--- a/3rdparty/pybind11/docs/changelog.rst
+++ b/3rdparty/pybind11/docs/changelog.rst
@@ -6,6 +6,931 @@ Changelog
 Starting with version 1.8.0, pybind11 releases use a `semantic versioning
 <http://semver.org>`_ policy.
 
+Changes will be added here periodically from the "Suggested changelog entry"
+block in pull request descriptions.
+
+
+
+IN DEVELOPMENT
+--------------
+
+Changes will be summarized here periodically.
+
+Version 2.10.0 (Jul 15, 2022)
+-----------------------------
+
+Removed support for Python 2.7, Python 3.5, and MSVC 2015. Support for MSVC
+2017 is limited due to availability of CI runners; we highly recommend MSVC
+2019 or 2022 be used. Initial support added for Python 3.11.
+
+New features:
+
+* ``py::anyset`` & ``py::frozenset`` were added, with copying (cast) to
+  ``std::set`` (similar to ``set``).
+  `#3901 <https://github.com/pybind/pybind11/pull/3901>`_
+
+* Support bytearray casting to string.
+  `#3707 <https://github.com/pybind/pybind11/pull/3707>`_
+
+* ``type_caster<std::monostate>`` was added. ``std::monostate`` is a tag type
+  that allows ``std::variant`` to act as an optional, or allows default
+  construction of a ``std::variant`` holding a non-default constructible type.
+  `#3818 <https://github.com/pybind/pybind11/pull/3818>`_
+
+* ``pybind11::capsule::set_name`` added to mutate the name of the capsule instance.
+  `#3866 <https://github.com/pybind/pybind11/pull/3866>`_
+
+* NumPy: dtype constructor from type number added, accessors corresponding to
+  Python API ``dtype.num``, ``dtype.byteorder``, ``dtype.flags`` and
+  ``dtype.alignment`` added.
+  `#3868 <https://github.com/pybind/pybind11/pull/3868>`_
+
+
+Changes:
+
+* Python 3.6 is now the minimum supported version.
+  `#3688 <https://github.com/pybind/pybind11/pull/3688>`_
+  `#3719 <https://github.com/pybind/pybind11/pull/3719>`_
+
+* The minimum version for MSVC is now 2017.
+  `#3722 <https://github.com/pybind/pybind11/pull/3722>`_
+
+* Fix issues with CPython 3.11 betas and add to supported test matrix.
+  `#3923 <https://github.com/pybind/pybind11/pull/3923>`_
+
+* ``error_already_set`` is now safer and more performant, especially for
+  exceptions with long tracebacks, by delaying computation.
+  `#1895 <https://github.com/pybind/pybind11/pull/1895>`_
+
+* Improve exception handling in python ``str`` bindings.
+  `#3826 <https://github.com/pybind/pybind11/pull/3826>`_
+
+* The bindings for capsules now have more consistent exception handling.
+  `#3825 <https://github.com/pybind/pybind11/pull/3825>`_
+
+* ``PYBIND11_OBJECT_CVT`` and ``PYBIND11_OBJECT_CVT_DEFAULT`` macro can now be
+  used to define classes in namespaces other than pybind11.
+  `#3797 <https://github.com/pybind/pybind11/pull/3797>`_
+
+* Error printing code now uses ``PYBIND11_DETAILED_ERROR_MESSAGES`` instead of
+  requiring ``NDEBUG``, allowing use with release builds if desired.
+  `#3913 <https://github.com/pybind/pybind11/pull/3913>`_
+
+* Implicit conversion of the literal ``0`` to ``pybind11::handle`` is now disabled.
+  `#4008 <https://github.com/pybind/pybind11/pull/4008>`_
+
+
+Bug fixes:
+
+* Fix exception handling when ``pybind11::weakref()`` fails.
+  `#3739 <https://github.com/pybind/pybind11/pull/3739>`_
+
+* ``module_::def_submodule`` was missing proper error handling. This is fixed now.
+  `#3973 <https://github.com/pybind/pybind11/pull/3973>`_
+
+* The behavior or ``error_already_set`` was made safer and the highly opaque
+  "Unknown internal error occurred" message was replaced with a more helpful
+  message.
+  `#3982 <https://github.com/pybind/pybind11/pull/3982>`_
+
+* ``error_already_set::what()`` now handles non-normalized exceptions correctly.
+  `#3971 <https://github.com/pybind/pybind11/pull/3971>`_
+
+* Support older C++ compilers where filesystem is not yet part of the standard
+  library and is instead included in ``std::experimental::filesystem``.
+  `#3840 <https://github.com/pybind/pybind11/pull/3840>`_
+
+* Fix ``-Wfree-nonheap-object`` warnings produced by GCC by avoiding returning
+  pointers to static objects with ``return_value_policy::take_ownership``.
+  `#3946 <https://github.com/pybind/pybind11/pull/3946>`_
+
+* Fix cast from pytype rvalue to another pytype.
+  `#3949 <https://github.com/pybind/pybind11/pull/3949>`_
+
+* Ensure proper behavior when garbage collecting classes with dynamic attributes in Python >=3.9.
+  `#4051 <https://github.com/pybind/pybind11/pull/4051>`_
+
+* A couple long-standing ``PYBIND11_NAMESPACE``
+  ``__attribute__((visibility("hidden")))`` inconsistencies are now fixed
+  (affects only unusual environments).
+  `#4043 <https://github.com/pybind/pybind11/pull/4043>`_
+
+* ``pybind11::detail::get_internals()`` is now resilient to in-flight Python
+  exceptions.
+  `#3981 <https://github.com/pybind/pybind11/pull/3981>`_
+
+* Arrays with a dimension of size 0 are now properly converted to dynamic Eigen
+  matrices (more common in NumPy 1.23).
+  `#4038 <https://github.com/pybind/pybind11/pull/4038>`_
+
+* Avoid catching unrelated errors when importing NumPy.
+  `#3974 <https://github.com/pybind/pybind11/pull/3974>`_
+
+Performance and style:
+
+* Added an accessor overload of ``(object &&key)`` to reference steal the
+  object when using python types as keys. This prevents unnecessary reference
+  count overhead for attr, dictionary, tuple, and sequence look ups. Added
+  additional regression tests. Fixed a performance bug the caused accessor
+  assignments to potentially perform unnecessary copies.
+  `#3970 <https://github.com/pybind/pybind11/pull/3970>`_
+
+* Perfect forward all args of ``make_iterator``.
+  `#3980 <https://github.com/pybind/pybind11/pull/3980>`_
+
+* Avoid potential bug in pycapsule destructor by adding an ``error_guard`` to
+  one of the dtors.
+  `#3958 <https://github.com/pybind/pybind11/pull/3958>`_
+
+* Optimize dictionary access in ``strip_padding`` for numpy.
+  `#3994 <https://github.com/pybind/pybind11/pull/3994>`_
+
+* ``stl_bind.h`` bindings now take slice args as a const-ref.
+  `#3852 <https://github.com/pybind/pybind11/pull/3852>`_
+
+* Made slice constructor more consistent, and improve performance of some
+  casters by allowing reference stealing.
+  `#3845 <https://github.com/pybind/pybind11/pull/3845>`_
+
+* Change numpy dtype from_args method to use const ref.
+  `#3878 <https://github.com/pybind/pybind11/pull/3878>`_
+
+* Follow rule of three to ensure ``PyErr_Restore`` is called only once.
+  `#3872 <https://github.com/pybind/pybind11/pull/3872>`_
+
+* Added missing perfect forwarding for ``make_iterator`` functions.
+  `#3860 <https://github.com/pybind/pybind11/pull/3860>`_
+
+* Optimize c++ to python function casting by using the rvalue caster.
+  `#3966 <https://github.com/pybind/pybind11/pull/3966>`_
+
+* Optimize Eigen sparse matrix casting by removing unnecessary temporary.
+  `#4064 <https://github.com/pybind/pybind11/pull/4064>`_
+
+* Avoid potential implicit copy/assignment constructors causing double free in
+  ``strdup_gaurd``.
+  `#3905 <https://github.com/pybind/pybind11/pull/3905>`_
+
+* Enable clang-tidy checks ``misc-definitions-in-headers``,
+  ``modernize-loop-convert``, and ``modernize-use-nullptr``.
+  `#3881 <https://github.com/pybind/pybind11/pull/3881>`_
+  `#3988 <https://github.com/pybind/pybind11/pull/3988>`_
+
+
+Build system improvements:
+
+* CMake: Fix file extension on Windows with cp36 and cp37 using FindPython.
+  `#3919 <https://github.com/pybind/pybind11/pull/3919>`_
+
+* CMake: Support multiple Python targets (such as on vcpkg).
+  `#3948 <https://github.com/pybind/pybind11/pull/3948>`_
+
+* CMake: Fix issue with NVCC on Windows.
+  `#3947 <https://github.com/pybind/pybind11/pull/3947>`_
+
+* CMake: Drop the bitness check on cross compiles (like targeting WebAssembly
+  via Emscripten).
+  `#3959 <https://github.com/pybind/pybind11/pull/3959>`_
+
+* Add MSVC builds in debug mode to CI.
+  `#3784 <https://github.com/pybind/pybind11/pull/3784>`_
+
+* MSVC 2022 C++20 coverage was added to GitHub Actions, including Eigen.
+  `#3732 <https://github.com/pybind/pybind11/pull/3732>`_,
+  `#3741 <https://github.com/pybind/pybind11/pull/3741>`_
+
+
+Backend and tidying up:
+
+* New theme for the documentation.
+  `#3109 <https://github.com/pybind/pybind11/pull/3109>`_
+
+* Remove idioms in code comments.  Use more inclusive language.
+  `#3809 <https://github.com/pybind/pybind11/pull/3809>`_
+
+* ``#include <iostream>`` was removed from the ``pybind11/stl.h`` header. Your
+  project may break if it has a transitive dependency on this include. The fix
+  is to "Include What You Use".
+  `#3928 <https://github.com/pybind/pybind11/pull/3928>`_
+
+* Avoid ``setup.py <command>`` usage in internal tests.
+  `#3734 <https://github.com/pybind/pybind11/pull/3734>`_
+
+
+Version 2.9.2 (Mar 29, 2022)
+----------------------------
+
+Changes:
+
+* Enum now has an ``__index__`` method on Python <3.8 too.
+  `#3700 <https://github.com/pybind/pybind11/pull/3700>`_
+
+* Local internals are now cleared after finalizing the interpreter.
+  `#3744 <https://github.com/pybind/pybind11/pull/3744>`_
+
+Bug fixes:
+
+* Better support for Python 3.11 alphas.
+  `#3694 <https://github.com/pybind/pybind11/pull/3694>`_
+
+* ``PYBIND11_TYPE_CASTER`` now uses fully qualified symbols, so it can be used
+  outside of ``pybind11::detail``.
+  `#3758 <https://github.com/pybind/pybind11/pull/3758>`_
+
+* Some fixes for PyPy 3.9.
+  `#3768 <https://github.com/pybind/pybind11/pull/3768>`_
+
+* Fixed a potential memleak in PyPy in ``get_type_override``.
+  `#3774 <https://github.com/pybind/pybind11/pull/3774>`_
+
+* Fix usage of ``VISIBILITY_INLINES_HIDDEN``.
+  `#3721 <https://github.com/pybind/pybind11/pull/3721>`_
+
+
+Build system improvements:
+
+* Uses ``sysconfig`` module to determine installation locations on Python >=
+  3.10, instead of ``distutils`` which has been deprecated.
+  `#3764 <https://github.com/pybind/pybind11/pull/3764>`_
+
+* Support Catch 2.13.5+ (supporting GLIBC 2.34+).
+  `#3679 <https://github.com/pybind/pybind11/pull/3679>`_
+
+* Fix test failures with numpy 1.22 by ignoring whitespace when comparing
+  ``str()`` of dtypes.
+  `#3682 <https://github.com/pybind/pybind11/pull/3682>`_
+
+
+Backend and tidying up:
+
+* clang-tidy: added ``readability-qualified-auto``,
+  ``readability-braces-around-statements``,
+  ``cppcoreguidelines-prefer-member-initializer``,
+  ``clang-analyzer-optin.performance.Padding``,
+  ``cppcoreguidelines-pro-type-static-cast-downcast``, and
+  ``readability-inconsistent-declaration-parameter-name``.
+  `#3702 <https://github.com/pybind/pybind11/pull/3702>`_,
+  `#3699 <https://github.com/pybind/pybind11/pull/3699>`_,
+  `#3716 <https://github.com/pybind/pybind11/pull/3716>`_,
+  `#3709 <https://github.com/pybind/pybind11/pull/3709>`_
+
+* clang-format was added to the pre-commit actions, and the entire code base
+  automatically reformatted (after several iterations preparing for this leap).
+  `#3713 <https://github.com/pybind/pybind11/pull/3713>`_
+
+
+Version 2.9.1 (Feb 2, 2022)
+---------------------------
+
+Changes:
+
+* If possible, attach Python exception with ``py::raise_from`` to ``TypeError``
+  when casting from C++ to Python. This will give additional info if Python
+  exceptions occur in the caster. Adds a test case of trying to convert a set
+  from C++ to Python when the hash function is not defined in Python.
+  `#3605 <https://github.com/pybind/pybind11/pull/3605>`_
+
+* Add a mapping of C++11 nested exceptions to their Python exception
+  equivalent using ``py::raise_from``. This attaches the nested exceptions in
+  Python using the ``__cause__`` field.
+  `#3608 <https://github.com/pybind/pybind11/pull/3608>`_
+
+* Propagate Python exception traceback using ``raise_from`` if a pybind11
+  function runs out of overloads.
+  `#3671 <https://github.com/pybind/pybind11/pull/3671>`_
+
+* ``py::multiple_inheritance`` is now only needed when C++ bases are hidden
+  from pybind11.
+  `#3650 <https://github.com/pybind/pybind11/pull/3650>`_ and
+  `#3659 <https://github.com/pybind/pybind11/pull/3659>`_
+
+
+Bug fixes:
+
+* Remove a boolean cast in ``numpy.h`` that causes MSVC C4800 warnings when
+  compiling against Python 3.10 or newer.
+  `#3669 <https://github.com/pybind/pybind11/pull/3669>`_
+
+* Render ``py::bool_`` and ``py::float_`` as ``bool`` and ``float``
+  respectively.
+  `#3622 <https://github.com/pybind/pybind11/pull/3622>`_
+
+Build system improvements:
+
+* Fix CMake extension suffix computation on Python 3.10+.
+  `#3663 <https://github.com/pybind/pybind11/pull/3663>`_
+
+* Allow ``CMAKE_ARGS`` to override CMake args in pybind11's own ``setup.py``.
+  `#3577 <https://github.com/pybind/pybind11/pull/3577>`_
+
+* Remove a few deprecated c-headers.
+  `#3610 <https://github.com/pybind/pybind11/pull/3610>`_
+
+* More uniform handling of test targets.
+  `#3590 <https://github.com/pybind/pybind11/pull/3590>`_
+
+* Add clang-tidy readability check to catch potentially swapped function args.
+  `#3611 <https://github.com/pybind/pybind11/pull/3611>`_
+
+
+Version 2.9.0 (Dec 28, 2021)
+----------------------------
+
+This is the last version to support Python 2.7 and 3.5.
+
+New Features:
+
+* Allow ``py::args`` to be followed by other arguments; the remaining arguments
+  are implicitly keyword-only, as if a ``py::kw_only{}`` annotation had been
+  used.
+  `#3402 <https://github.com/pybind/pybind11/pull/3402>`_
+
+Changes:
+
+* Make str/bytes/memoryview more interoperable with ``std::string_view``.
+  `#3521 <https://github.com/pybind/pybind11/pull/3521>`_
+
+* Replace ``_`` with ``const_name`` in internals, avoid defining ``pybind::_``
+  if ``_`` defined as macro (common gettext usage)
+  `#3423 <https://github.com/pybind/pybind11/pull/3423>`_
+
+
+Bug fixes:
+
+* Fix a rare warning about extra copy in an Eigen constructor.
+  `#3486 <https://github.com/pybind/pybind11/pull/3486>`_
+
+* Fix caching of the C++ overrides.
+  `#3465 <https://github.com/pybind/pybind11/pull/3465>`_
+
+* Add missing ``std::forward`` calls to some ``cpp_function`` overloads.
+  `#3443 <https://github.com/pybind/pybind11/pull/3443>`_
+
+* Support PyPy 7.3.7 and the PyPy3.8 beta. Test python-3.11 on PRs with the
+  ``python dev`` label.
+  `#3419 <https://github.com/pybind/pybind11/pull/3419>`_
+
+* Replace usage of deprecated ``Eigen::MappedSparseMatrix`` with
+  ``Eigen::Map<Eigen::SparseMatrix<...>>`` for Eigen 3.3+.
+  `#3499 <https://github.com/pybind/pybind11/pull/3499>`_
+
+* Tweaks to support Microsoft Visual Studio 2022.
+  `#3497 <https://github.com/pybind/pybind11/pull/3497>`_
+
+Build system improvements:
+
+* Nicer CMake printout and IDE organisation for pybind11's own tests.
+  `#3479 <https://github.com/pybind/pybind11/pull/3479>`_
+
+* CMake: report version type as part of the version string to avoid a spurious
+  space in the package status message.
+  `#3472 <https://github.com/pybind/pybind11/pull/3472>`_
+
+* Flags starting with ``-g`` in ``$CFLAGS`` and ``$CPPFLAGS`` are no longer
+  overridden by ``.Pybind11Extension``.
+  `#3436 <https://github.com/pybind/pybind11/pull/3436>`_
+
+* Ensure ThreadPool is closed in ``setup_helpers``.
+  `#3548 <https://github.com/pybind/pybind11/pull/3548>`_
+
+* Avoid LTS on ``mips64`` and ``ppc64le`` (reported broken).
+  `#3557 <https://github.com/pybind/pybind11/pull/3557>`_
+
+
+v2.8.1 (Oct 27, 2021)
+---------------------
+
+Changes and additions:
+
+* The simple namespace creation shortcut added in 2.8.0 was deprecated due to
+  usage of CPython internal API, and will be removed soon. Use
+  ``py::module_::import("types").attr("SimpleNamespace")``.
+  `#3374 <https://github.com/pybinyyd/pybind11/pull/3374>`_
+
+* Add C++ Exception type to throw and catch ``AttributeError``. Useful for
+  defining custom ``__setattr__`` and ``__getattr__`` methods.
+  `#3387 <https://github.com/pybind/pybind11/pull/3387>`_
+
+Fixes:
+
+* Fixed the potential for dangling references when using properties with
+  ``std::optional`` types.
+  `#3376 <https://github.com/pybind/pybind11/pull/3376>`_
+
+* Modernize usage of ``PyCodeObject`` on Python 3.9+ (moving toward support for
+  Python 3.11a1)
+  `#3368 <https://github.com/pybind/pybind11/pull/3368>`_
+
+* A long-standing bug in ``eigen.h`` was fixed (originally PR #3343). The bug
+  was unmasked by newly added ``static_assert``'s in the Eigen 3.4.0 release.
+  `#3352 <https://github.com/pybind/pybind11/pull/3352>`_
+
+* Support multiple raw inclusion of CMake helper files (Conan.io does this for
+  multi-config generators).
+  `#3420 <https://github.com/pybind/pybind11/pull/3420>`_
+
+* Fix harmless warning on upcoming CMake 3.22.
+  `#3368 <https://github.com/pybind/pybind11/pull/3368>`_
+
+* Fix 2.8.0 regression with MSVC 2017 + C++17 mode + Python 3.
+  `#3407 <https://github.com/pybind/pybind11/pull/3407>`_
+
+* Fix 2.8.0 regression that caused undefined behavior (typically
+  segfaults) in ``make_key_iterator``/``make_value_iterator`` if dereferencing
+  the iterator returned a temporary value instead of a reference.
+  `#3348 <https://github.com/pybind/pybind11/pull/3348>`_
+
+
+v2.8.0 (Oct 4, 2021)
+--------------------
+
+New features:
+
+* Added ``py::raise_from`` to enable chaining exceptions.
+  `#3215 <https://github.com/pybind/pybind11/pull/3215>`_
+
+* Allow exception translators to be optionally registered local to a module
+  instead of applying globally across all pybind11 modules. Use
+  ``register_local_exception_translator(ExceptionTranslator&& translator)``
+  instead of  ``register_exception_translator(ExceptionTranslator&&
+  translator)`` to keep your exception remapping code local to the module.
+  `#2650 <https://github.com/pybinyyd/pybind11/pull/2650>`_
+
+* Add ``make_simple_namespace`` function for instantiating Python
+  ``SimpleNamespace`` objects. **Deprecated in 2.8.1.**
+  `#2840 <https://github.com/pybind/pybind11/pull/2840>`_
+
+* ``pybind11::scoped_interpreter`` and ``initialize_interpreter`` have new
+  arguments to allow ``sys.argv`` initialization.
+  `#2341 <https://github.com/pybind/pybind11/pull/2341>`_
+
+* Allow Python builtins to be used as callbacks in CPython.
+  `#1413 <https://github.com/pybind/pybind11/pull/1413>`_
+
+* Added ``view`` to view arrays with a different datatype.
+  `#987 <https://github.com/pybind/pybind11/pull/987>`_
+
+* Implemented ``reshape`` on arrays.
+  `#984 <https://github.com/pybind/pybind11/pull/984>`_
+
+* Enable defining custom ``__new__`` methods on classes by fixing bug
+  preventing overriding methods if they have non-pybind11 siblings.
+  `#3265 <https://github.com/pybind/pybind11/pull/3265>`_
+
+* Add ``make_value_iterator()``, and fix ``make_key_iterator()`` to return
+  references instead of copies.
+  `#3293 <https://github.com/pybind/pybind11/pull/3293>`_
+
+* Improve the classes generated by ``bind_map``: `#3310 <https://github.com/pybind/pybind11/pull/3310>`_
+
+  * Change ``.items`` from an iterator to a dictionary view.
+  * Add ``.keys`` and ``.values`` (both dictionary views).
+  * Allow ``__contains__`` to take any object.
+
+* ``pybind11::custom_type_setup`` was added, for customizing the
+  ``PyHeapTypeObject`` corresponding to a class, which may be useful for
+  enabling garbage collection support, among other things.
+  `#3287 <https://github.com/pybind/pybind11/pull/3287>`_
+
+
+Changes:
+
+* Set ``__file__`` constant when running ``eval_file`` in an embedded interpreter.
+  `#3233 <https://github.com/pybind/pybind11/pull/3233>`_
+
+* Python objects and (C++17) ``std::optional`` now accepted in ``py::slice``
+  constructor.
+  `#1101 <https://github.com/pybind/pybind11/pull/1101>`_
+
+* The pybind11 proxy types ``str``, ``bytes``, ``bytearray``, ``tuple``,
+  ``list`` now consistently support passing ``ssize_t`` values for sizes and
+  indexes. Previously, only ``size_t`` was accepted in several interfaces.
+  `#3219 <https://github.com/pybind/pybind11/pull/3219>`_
+
+* Avoid evaluating ``PYBIND11_TLS_REPLACE_VALUE`` arguments more than once.
+  `#3290 <https://github.com/pybind/pybind11/pull/3290>`_
+
+Fixes:
+
+* Bug fix: enum value's ``__int__`` returning non-int when underlying type is
+  bool or of char type.
+  `#1334 <https://github.com/pybind/pybind11/pull/1334>`_
+
+* Fixes bug in setting error state in Capsule's pointer methods.
+  `#3261 <https://github.com/pybind/pybind11/pull/3261>`_
+
+* A long-standing memory leak in ``py::cpp_function::initialize`` was fixed.
+  `#3229 <https://github.com/pybind/pybind11/pull/3229>`_
+
+* Fixes thread safety for some ``pybind11::type_caster`` which require lifetime
+  extension, such as for ``std::string_view``.
+  `#3237 <https://github.com/pybind/pybind11/pull/3237>`_
+
+* Restore compatibility with gcc 4.8.4 as distributed by ubuntu-trusty, linuxmint-17.
+  `#3270 <https://github.com/pybind/pybind11/pull/3270>`_
+
+
+Build system improvements:
+
+* Fix regression in CMake Python package config: improper use of absolute path.
+  `#3144 <https://github.com/pybind/pybind11/pull/3144>`_
+
+* Cached Python version information could become stale when CMake was re-run
+  with a different Python version. The build system now detects this and
+  updates this information.
+  `#3299 <https://github.com/pybind/pybind11/pull/3299>`_
+
+* Specified UTF8-encoding in setup.py calls of open().
+  `#3137 <https://github.com/pybind/pybind11/pull/3137>`_
+
+* Fix a harmless warning from CMake 3.21 with the classic Python discovery.
+  `#3220 <https://github.com/pybind/pybind11/pull/3220>`_
+
+* Eigen repo and version can now be specified as cmake options.
+  `#3324 <https://github.com/pybind/pybind11/pull/3324>`_
+
+
+Backend and tidying up:
+
+* Reduced thread-local storage required for keeping alive temporary data for
+  type conversion to one key per ABI version, rather than one key per extension
+  module.  This makes the total thread-local storage required by pybind11 2
+  keys per ABI version.
+  `#3275 <https://github.com/pybind/pybind11/pull/3275>`_
+
+* Optimize NumPy array construction with additional moves.
+  `#3183 <https://github.com/pybind/pybind11/pull/3183>`_
+
+* Conversion to ``std::string`` and ``std::string_view`` now avoids making an
+  extra copy of the data on Python >= 3.3.
+  `#3257 <https://github.com/pybind/pybind11/pull/3257>`_
+
+* Remove const modifier from certain C++ methods on Python collections
+  (``list``, ``set``, ``dict``) such as (``clear()``, ``append()``,
+  ``insert()``, etc...) and annotated them with ``py-non-const``.
+
+* Enable readability ``clang-tidy-const-return`` and remove useless consts.
+  `#3254 <https://github.com/pybind/pybind11/pull/3254>`_
+  `#3194 <https://github.com/pybind/pybind11/pull/3194>`_
+
+* The clang-tidy ``google-explicit-constructor`` option was enabled.
+  `#3250 <https://github.com/pybind/pybind11/pull/3250>`_
+
+* Mark a pytype move constructor as noexcept (perf).
+  `#3236 <https://github.com/pybind/pybind11/pull/3236>`_
+
+* Enable clang-tidy check to guard against inheritance slicing.
+  `#3210 <https://github.com/pybind/pybind11/pull/3210>`_
+
+* Legacy warning suppression pragma were removed from eigen.h. On Unix
+  platforms, please use -isystem for Eigen include directories, to suppress
+  compiler warnings originating from Eigen headers. Note that CMake does this
+  by default. No adjustments are needed for Windows.
+  `#3198 <https://github.com/pybind/pybind11/pull/3198>`_
+
+* Format pybind11 with isort consistent ordering of imports
+  `#3195 <https://github.com/pybind/pybind11/pull/3195>`_
+
+* The warnings-suppression "pragma clamp" at the top/bottom of pybind11 was
+  removed, clearing the path to refactoring and IWYU cleanup.
+  `#3186 <https://github.com/pybind/pybind11/pull/3186>`_
+
+* Enable most bugprone checks in clang-tidy and fix the found potential bugs
+  and poor coding styles.
+  `#3166 <https://github.com/pybind/pybind11/pull/3166>`_
+
+* Add ``clang-tidy-readability`` rules to make boolean casts explicit improving
+  code readability. Also enabled other misc and readability clang-tidy checks.
+  `#3148 <https://github.com/pybind/pybind11/pull/3148>`_
+
+* Move object in ``.pop()`` for list.
+  `#3116 <https://github.com/pybind/pybind11/pull/3116>`_
+
+
+
+
+v2.7.1 (Aug 3, 2021)
+---------------------
+
+Minor missing functionality added:
+
+* Allow Python builtins to be used as callbacks in CPython.
+  `#1413 <https://github.com/pybind/pybind11/pull/1413>`_
+
+Bug fixes:
+
+* Fix regression in CMake Python package config: improper use of absolute path.
+  `#3144 <https://github.com/pybind/pybind11/pull/3144>`_
+
+* Fix Mingw64 and add to the CI testing matrix.
+  `#3132 <https://github.com/pybind/pybind11/pull/3132>`_
+
+* Specified UTF8-encoding in setup.py calls of open().
+  `#3137 <https://github.com/pybind/pybind11/pull/3137>`_
+
+* Add clang-tidy-readability rules to make boolean casts explicit improving
+  code readability. Also enabled other misc and readability clang-tidy checks.
+  `#3148 <https://github.com/pybind/pybind11/pull/3148>`_
+
+* Move object in ``.pop()`` for list.
+  `#3116 <https://github.com/pybind/pybind11/pull/3116>`_
+
+Backend and tidying up:
+
+* Removed and fixed warning suppressions.
+  `#3127 <https://github.com/pybind/pybind11/pull/3127>`_
+  `#3129 <https://github.com/pybind/pybind11/pull/3129>`_
+  `#3135 <https://github.com/pybind/pybind11/pull/3135>`_
+  `#3141 <https://github.com/pybind/pybind11/pull/3141>`_
+  `#3142 <https://github.com/pybind/pybind11/pull/3142>`_
+  `#3150 <https://github.com/pybind/pybind11/pull/3150>`_
+  `#3152 <https://github.com/pybind/pybind11/pull/3152>`_
+  `#3160 <https://github.com/pybind/pybind11/pull/3160>`_
+  `#3161 <https://github.com/pybind/pybind11/pull/3161>`_
+
+
+v2.7.0 (Jul 16, 2021)
+---------------------
+
+New features:
+
+* Enable ``py::implicitly_convertible<py::none, ...>`` for
+  ``py::class_``-wrapped types.
+  `#3059 <https://github.com/pybind/pybind11/pull/3059>`_
+
+* Allow function pointer extraction from overloaded functions.
+  `#2944 <https://github.com/pybind/pybind11/pull/2944>`_
+
+* NumPy: added ``.char_()`` to type which gives the NumPy public ``char``
+  result, which also distinguishes types by bit length (unlike ``.kind()``).
+  `#2864 <https://github.com/pybind/pybind11/pull/2864>`_
+
+* Add ``pybind11::bytearray`` to manipulate ``bytearray`` similar to ``bytes``.
+  `#2799 <https://github.com/pybind/pybind11/pull/2799>`_
+
+* ``pybind11/stl/filesystem.h`` registers a type caster that, on C++17/Python
+  3.6+, converts ``std::filesystem::path`` to ``pathlib.Path`` and any
+  ``os.PathLike`` to ``std::filesystem::path``.
+  `#2730 <https://github.com/pybind/pybind11/pull/2730>`_
+
+* A ``PYBIND11_VERSION_HEX`` define was added, similar to ``PY_VERSION_HEX``.
+  `#3120 <https://github.com/pybind/pybind11/pull/3120>`_
+
+
+
+Changes:
+
+* ``py::str`` changed to exclusively hold ``PyUnicodeObject``. Previously
+  ``py::str`` could also hold ``bytes``, which is probably surprising, was
+  never documented, and can mask bugs (e.g. accidental use of ``py::str``
+  instead of ``py::bytes``).
+  `#2409 <https://github.com/pybind/pybind11/pull/2409>`_
+
+* Add a safety guard to ensure that the Python GIL is held when C++ calls back
+  into Python via ``object_api<>::operator()`` (e.g. ``py::function``
+  ``__call__``).  (This feature is available for Python 3.6+ only.)
+  `#2919 <https://github.com/pybind/pybind11/pull/2919>`_
+
+* Catch a missing ``self`` argument in calls to ``__init__()``.
+  `#2914 <https://github.com/pybind/pybind11/pull/2914>`_
+
+* Use ``std::string_view`` if available to avoid a copy when passing an object
+  to a ``std::ostream``.
+  `#3042 <https://github.com/pybind/pybind11/pull/3042>`_
+
+* An important warning about thread safety was added to the ``iostream.h``
+  documentation; attempts to make ``py::scoped_ostream_redirect`` thread safe
+  have been removed, as it was only partially effective.
+  `#2995 <https://github.com/pybind/pybind11/pull/2995>`_
+
+
+Fixes:
+
+* Performance: avoid unnecessary strlen calls.
+  `#3058 <https://github.com/pybind/pybind11/pull/3058>`_
+
+* Fix auto-generated documentation string when using ``const T`` in
+  ``pyarray_t``.
+  `#3020 <https://github.com/pybind/pybind11/pull/3020>`_
+
+* Unify error messages thrown by ``simple_collector``/``unpacking_collector``.
+  `#3013 <https://github.com/pybind/pybind11/pull/3013>`_
+
+* ``pybind11::builtin_exception`` is now explicitly exported, which means the
+  types included/defined in different modules are identical, and exceptions
+  raised in different modules can be caught correctly. The documentation was
+  updated to explain that custom exceptions that are used across module
+  boundaries need to be explicitly exported as well.
+  `#2999 <https://github.com/pybind/pybind11/pull/2999>`_
+
+* Fixed exception when printing UTF-8 to a ``scoped_ostream_redirect``.
+  `#2982 <https://github.com/pybind/pybind11/pull/2982>`_
+
+* Pickle support enhancement: ``setstate`` implementation will attempt to
+  ``setattr`` ``__dict__`` only if the unpickled ``dict`` object is not empty,
+  to not force use of ``py::dynamic_attr()`` unnecessarily.
+  `#2972 <https://github.com/pybind/pybind11/pull/2972>`_
+
+* Allow negative timedelta values to roundtrip.
+  `#2870 <https://github.com/pybind/pybind11/pull/2870>`_
+
+* Fix unchecked errors could potentially swallow signals/other exceptions.
+  `#2863 <https://github.com/pybind/pybind11/pull/2863>`_
+
+* Add null pointer check with ``std::localtime``.
+  `#2846 <https://github.com/pybind/pybind11/pull/2846>`_
+
+* Fix the ``weakref`` constructor from ``py::object`` to create a new
+  ``weakref`` on conversion.
+  `#2832 <https://github.com/pybind/pybind11/pull/2832>`_
+
+* Avoid relying on exceptions in C++17 when getting a ``shared_ptr`` holder
+  from a ``shared_from_this`` class.
+  `#2819 <https://github.com/pybind/pybind11/pull/2819>`_
+
+* Allow the codec's exception to be raised instead of :code:`RuntimeError` when
+  casting from :code:`py::str` to :code:`std::string`.
+  `#2903 <https://github.com/pybind/pybind11/pull/2903>`_
+
+
+Build system improvements:
+
+* In ``setup_helpers.py``, test for platforms that have some multiprocessing
+  features but lack semaphores, which ``ParallelCompile`` requires.
+  `#3043 <https://github.com/pybind/pybind11/pull/3043>`_
+
+* Fix ``pybind11_INCLUDE_DIR`` in case ``CMAKE_INSTALL_INCLUDEDIR`` is
+  absolute.
+  `#3005 <https://github.com/pybind/pybind11/pull/3005>`_
+
+* Fix bug not respecting ``WITH_SOABI`` or ``WITHOUT_SOABI`` to CMake.
+  `#2938 <https://github.com/pybind/pybind11/pull/2938>`_
+
+* Fix the default ``Pybind11Extension`` compilation flags with a Mingw64 python.
+  `#2921 <https://github.com/pybind/pybind11/pull/2921>`_
+
+* Clang on Windows: do not pass ``/MP`` (ignored flag).
+  `#2824 <https://github.com/pybind/pybind11/pull/2824>`_
+
+* ``pybind11.setup_helpers.intree_extensions`` can be used to generate
+  ``Pybind11Extension`` instances from cpp files placed in the Python package
+  source tree.
+  `#2831 <https://github.com/pybind/pybind11/pull/2831>`_
+
+Backend and tidying up:
+
+* Enable clang-tidy performance, readability, and modernization checks
+  throughout the codebase to enforce best coding practices.
+  `#3046 <https://github.com/pybind/pybind11/pull/3046>`_,
+  `#3049 <https://github.com/pybind/pybind11/pull/3049>`_,
+  `#3051 <https://github.com/pybind/pybind11/pull/3051>`_,
+  `#3052 <https://github.com/pybind/pybind11/pull/3052>`_,
+  `#3080 <https://github.com/pybind/pybind11/pull/3080>`_, and
+  `#3094 <https://github.com/pybind/pybind11/pull/3094>`_
+
+
+* Checks for common misspellings were added to the pre-commit hooks.
+  `#3076 <https://github.com/pybind/pybind11/pull/3076>`_
+
+* Changed ``Werror`` to stricter ``Werror-all`` for Intel compiler and fixed
+  minor issues.
+  `#2948 <https://github.com/pybind/pybind11/pull/2948>`_
+
+* Fixed compilation with GCC < 5 when the user defines ``_GLIBCXX_USE_CXX11_ABI``.
+  `#2956 <https://github.com/pybind/pybind11/pull/2956>`_
+
+* Added nox support for easier local testing and linting of contributions.
+  `#3101 <https://github.com/pybind/pybind11/pull/3101>`_ and
+  `#3121 <https://github.com/pybind/pybind11/pull/3121>`_
+
+* Avoid RTD style issue with docutils 0.17+.
+  `#3119 <https://github.com/pybind/pybind11/pull/3119>`_
+
+* Support pipx run, such as ``pipx run pybind11 --include`` for a quick compile.
+  `#3117 <https://github.com/pybind/pybind11/pull/3117>`_
+
+
+
+v2.6.2 (Jan 26, 2021)
+---------------------
+
+Minor missing functionality added:
+
+* enum: add missing Enum.value property.
+  `#2739 <https://github.com/pybind/pybind11/pull/2739>`_
+
+* Allow thread termination to be avoided during shutdown for CPython 3.7+ via
+  ``.disarm`` for ``gil_scoped_acquire``/``gil_scoped_release``.
+  `#2657 <https://github.com/pybind/pybind11/pull/2657>`_
+
+Fixed or improved behavior in a few special cases:
+
+* Fix bug where the constructor of ``object`` subclasses would not throw on
+  being passed a Python object of the wrong type.
+  `#2701 <https://github.com/pybind/pybind11/pull/2701>`_
+
+* The ``type_caster`` for integers does not convert Python objects with
+  ``__int__`` anymore with ``noconvert`` or during the first round of trying
+  overloads.
+  `#2698 <https://github.com/pybind/pybind11/pull/2698>`_
+
+* When casting to a C++ integer, ``__index__`` is always called and not
+  considered as conversion, consistent with Python 3.8+.
+  `#2801 <https://github.com/pybind/pybind11/pull/2801>`_
+
+Build improvements:
+
+* Setup helpers: ``extra_compile_args`` and ``extra_link_args`` automatically set by
+  Pybind11Extension are now prepended, which allows them to be overridden
+  by user-set ``extra_compile_args`` and ``extra_link_args``.
+  `#2808 <https://github.com/pybind/pybind11/pull/2808>`_
+
+* Setup helpers: Don't trigger unused parameter warning.
+  `#2735 <https://github.com/pybind/pybind11/pull/2735>`_
+
+* CMake: Support running with ``--warn-uninitialized`` active.
+  `#2806 <https://github.com/pybind/pybind11/pull/2806>`_
+
+* CMake: Avoid error if included from two submodule directories.
+  `#2804 <https://github.com/pybind/pybind11/pull/2804>`_
+
+* CMake: Fix ``STATIC`` / ``SHARED`` being ignored in FindPython mode.
+  `#2796 <https://github.com/pybind/pybind11/pull/2796>`_
+
+* CMake: Respect the setting for ``CMAKE_CXX_VISIBILITY_PRESET`` if defined.
+  `#2793 <https://github.com/pybind/pybind11/pull/2793>`_
+
+* CMake: Fix issue with FindPython2/FindPython3 not working with ``pybind11::embed``.
+  `#2662 <https://github.com/pybind/pybind11/pull/2662>`_
+
+* CMake: mixing local and installed pybind11's would prioritize the installed
+  one over the local one (regression in 2.6.0).
+  `#2716 <https://github.com/pybind/pybind11/pull/2716>`_
+
+
+Bug fixes:
+
+* Fixed segfault in multithreaded environments when using
+  ``scoped_ostream_redirect``.
+  `#2675 <https://github.com/pybind/pybind11/pull/2675>`_
+
+* Leave docstring unset when all docstring-related options are disabled, rather
+  than set an empty string.
+  `#2745 <https://github.com/pybind/pybind11/pull/2745>`_
+
+* The module key in builtins that pybind11 uses to store its internals changed
+  from std::string to a python str type (more natural on Python 2, no change on
+  Python 3).
+  `#2814 <https://github.com/pybind/pybind11/pull/2814>`_
+
+* Fixed assertion error related to unhandled (later overwritten) exception in
+  CPython 3.8 and 3.9 debug builds.
+  `#2685 <https://github.com/pybind/pybind11/pull/2685>`_
+
+* Fix ``py::gil_scoped_acquire`` assert with CPython 3.9 debug build.
+  `#2683 <https://github.com/pybind/pybind11/pull/2683>`_
+
+* Fix issue with a test failing on pytest 6.2.
+  `#2741 <https://github.com/pybind/pybind11/pull/2741>`_
+
+Warning fixes:
+
+* Fix warning modifying constructor parameter 'flag' that shadows a field of
+  'set_flag' ``[-Wshadow-field-in-constructor-modified]``.
+  `#2780 <https://github.com/pybind/pybind11/pull/2780>`_
+
+* Suppressed some deprecation warnings about old-style
+  ``__init__``/``__setstate__`` in the tests.
+  `#2759 <https://github.com/pybind/pybind11/pull/2759>`_
+
+Valgrind work:
+
+* Fix invalid access when calling a pybind11 ``__init__`` on a non-pybind11
+  class instance.
+  `#2755 <https://github.com/pybind/pybind11/pull/2755>`_
+
+* Fixed various minor memory leaks in pybind11's test suite.
+  `#2758 <https://github.com/pybind/pybind11/pull/2758>`_
+
+* Resolved memory leak in cpp_function initialization when exceptions occurred.
+  `#2756 <https://github.com/pybind/pybind11/pull/2756>`_
+
+* Added a Valgrind build, checking for leaks and memory-related UB, to CI.
+  `#2746 <https://github.com/pybind/pybind11/pull/2746>`_
+
+Compiler support:
+
+* Intel compiler was not activating C++14 support due to a broken define.
+  `#2679 <https://github.com/pybind/pybind11/pull/2679>`_
+
+* Support ICC and NVIDIA HPC SDK in C++17 mode.
+  `#2729 <https://github.com/pybind/pybind11/pull/2729>`_
+
+* Support Intel OneAPI compiler (ICC 20.2) and add to CI.
+  `#2573 <https://github.com/pybind/pybind11/pull/2573>`_
+
+
+
 v2.6.1 (Nov 11, 2020)
 ---------------------
 
@@ -14,7 +939,7 @@ v2.6.1 (Nov 11, 2020)
   and ``eval`` in pure Python.
   `#2616 <https://github.com/pybind/pybind11/pull/2616>`_
 
-* ``setup_helpers`` will no longer set a minimum macOS version lower than the
+* ``setup_helpers`` will no longer set a minimum macOS version higher than the
   current version.
   `#2622 <https://github.com/pybind/pybind11/pull/2622>`_
 
@@ -142,7 +1067,7 @@ Packaging / building improvements:
   `#2338 <https://github.com/pybind/pybind11/pull/2338>`_ and
   `#2370 <https://github.com/pybind/pybind11/pull/2370>`_
 
-  * Full integration with CMake’s C++ standard system and compile features
+  * Full integration with CMake's C++ standard system and compile features
     replaces ``PYBIND11_CPP_STANDARD``.
 
   * Generated config file is now portable to different Python/compiler/CMake
@@ -374,7 +1299,7 @@ v2.4.0 (Sep 19, 2019)
   `#1888 <https://github.com/pybind/pybind11/pull/1888>`_.
 
 * ``py::details::overload_cast_impl`` is available in C++11 mode, can be used
-  like ``overload_cast`` with an additional set of parantheses.
+  like ``overload_cast`` with an additional set of parentheses.
   `#1581 <https://github.com/pybind/pybind11/pull/1581>`_.
 
 * Fixed ``get_include()`` on Conda.
@@ -696,6 +1621,7 @@ v2.2.0 (August 31, 2017)
 
       from cpp_module import CppBase1, CppBase2
 
+
       class PyDerived(CppBase1, CppBase2):
           def __init__(self):
               CppBase1.__init__(self)  # C++ bases must be initialized explicitly
@@ -908,7 +1834,7 @@ v2.2.0 (August 31, 2017)
 * Intel C++ compiler compatibility fixes.
   `#937 <https://github.com/pybind/pybind11/pull/937>`_.
 
-* Fixed implicit conversion of `py::enum_` to integer types on Python 2.7.
+* Fixed implicit conversion of ``py::enum_`` to integer types on Python 2.7.
   `#821 <https://github.com/pybind/pybind11/pull/821>`_.
 
 * Added ``py::hash`` to fetch the hash value of Python objects, and
diff --git a/3rdparty/pybind11/docs/classes.rst b/3rdparty/pybind11/docs/classes.rst
index f3610ef367..c0c53135b8 100644
--- a/3rdparty/pybind11/docs/classes.rst
+++ b/3rdparty/pybind11/docs/classes.rst
@@ -44,14 +44,14 @@ interactive Python session demonstrating this example is shown below:
 
     % python
     >>> import example
-    >>> p = example.Pet('Molly')
+    >>> p = example.Pet("Molly")
     >>> print(p)
     <example.Pet object at 0x10cd98060>
     >>> p.getName()
-    u'Molly'
-    >>> p.setName('Charly')
+    'Molly'
+    >>> p.setName("Charly")
     >>> p.getName()
-    u'Charly'
+    'Charly'
 
 .. seealso::
 
@@ -122,12 +122,12 @@ This makes it possible to write
 
 .. code-block:: pycon
 
-    >>> p = example.Pet('Molly')
+    >>> p = example.Pet("Molly")
     >>> p.name
-    u'Molly'
-    >>> p.name = 'Charly'
+    'Molly'
+    >>> p.name = "Charly"
     >>> p.name
-    u'Charly'
+    'Charly'
 
 Now suppose that ``Pet::name`` was a private internal variable
 that can only be accessed via setters and getters.
@@ -174,10 +174,10 @@ Native Python classes can pick up new attributes dynamically:
 .. code-block:: pycon
 
     >>> class Pet:
-    ...     name = 'Molly'
+    ...     name = "Molly"
     ...
     >>> p = Pet()
-    >>> p.name = 'Charly'  # overwrite existing
+    >>> p.name = "Charly"  # overwrite existing
     >>> p.age = 2  # dynamically add a new attribute
 
 By default, classes exported from C++ do not support this and the only writable
@@ -195,7 +195,7 @@ Trying to set any other attribute results in an error:
 .. code-block:: pycon
 
     >>> p = example.Pet()
-    >>> p.name = 'Charly'  # OK, attribute defined in C++
+    >>> p.name = "Charly"  # OK, attribute defined in C++
     >>> p.age = 2  # fail
     AttributeError: 'Pet' object has no attribute 'age'
 
@@ -213,7 +213,7 @@ Now everything works as expected:
 .. code-block:: pycon
 
     >>> p = example.Pet()
-    >>> p.name = 'Charly'  # OK, overwrite value in C++
+    >>> p.name = "Charly"  # OK, overwrite value in C++
     >>> p.age = 2  # OK, dynamically add a new attribute
     >>> p.__dict__  # just like a native Python class
     {'age': 2}
@@ -280,11 +280,11 @@ expose fields and methods of both types:
 
 .. code-block:: pycon
 
-    >>> p = example.Dog('Molly')
+    >>> p = example.Dog("Molly")
     >>> p.name
-    u'Molly'
+    'Molly'
     >>> p.bark()
-    u'woof!'
+    'woof!'
 
 The C++ classes defined above are regular non-polymorphic types with an
 inheritance relationship. This is reflected in Python:
@@ -332,7 +332,7 @@ will automatically recognize this:
     >>> type(p)
     PolymorphicDog  # automatically downcast
     >>> p.bark()
-    u'woof!'
+    'woof!'
 
 Given a pointer to a polymorphic base, pybind11 performs automatic downcasting
 to the actual derived type. Note that this goes beyond the usual situation in
@@ -434,8 +434,7 @@ you can use ``py::detail::overload_cast_impl`` with an additional set of parenth
         .def("set", overload_cast_<int>()(&Pet::set), "Set the pet's age")
         .def("set", overload_cast_<const std::string &>()(&Pet::set), "Set the pet's name");
 
-.. [#cpp14] A compiler which supports the ``-std=c++14`` flag
-            or Visual Studio 2015 Update 2 and newer.
+.. [#cpp14] A compiler which supports the ``-std=c++14`` flag.
 
 .. note::
 
@@ -446,8 +445,7 @@ you can use ``py::detail::overload_cast_impl`` with an additional set of parenth
 Enumerations and internal types
 ===============================
 
-Let's now suppose that the example class contains an internal enumeration type,
-e.g.:
+Let's now suppose that the example class contains internal types like enumerations, e.g.:
 
 .. code-block:: cpp
 
@@ -457,10 +455,15 @@ e.g.:
             Cat
         };
 
+        struct Attributes {
+            float age = 0;
+        };
+
         Pet(const std::string &name, Kind type) : name(name), type(type) { }
 
         std::string name;
         Kind type;
+        Attributes attr;
     };
 
 The binding code for this example looks as follows:
@@ -471,22 +474,28 @@ The binding code for this example looks as follows:
 
     pet.def(py::init<const std::string &, Pet::Kind>())
         .def_readwrite("name", &Pet::name)
-        .def_readwrite("type", &Pet::type);
+        .def_readwrite("type", &Pet::type)
+        .def_readwrite("attr", &Pet::attr);
 
     py::enum_<Pet::Kind>(pet, "Kind")
         .value("Dog", Pet::Kind::Dog)
         .value("Cat", Pet::Kind::Cat)
         .export_values();
 
-To ensure that the ``Kind`` type is created within the scope of ``Pet``, the
-``pet`` :class:`class_` instance must be supplied to the :class:`enum_`.
+    py::class_<Pet::Attributes>(pet, "Attributes")
+        .def(py::init<>())
+        .def_readwrite("age", &Pet::Attributes::age);
+
+
+To ensure that the nested types ``Kind`` and ``Attributes`` are created within the scope of ``Pet``, the
+``pet`` :class:`class_` instance must be supplied to the :class:`enum_` and :class:`class_`
 constructor. The :func:`enum_::export_values` function exports the enum entries
 into the parent scope, which should be skipped for newer C++11-style strongly
 typed enums.
 
 .. code-block:: pycon
 
-    >>> p = Pet('Lucy', Pet.Cat)
+    >>> p = Pet("Lucy", Pet.Cat)
     >>> p.type
     Kind.Cat
     >>> int(p.type)
@@ -508,7 +517,7 @@ The ``name`` property returns the name of the enum value as a unicode string.
 
     .. code-block:: pycon
 
-        >>> p = Pet( "Lucy", Pet.Cat )
+        >>> p = Pet("Lucy", Pet.Cat)
         >>> pet_type = p.type
         >>> pet_type
         Pet.Cat
diff --git a/3rdparty/pybind11/docs/compiling.rst b/3rdparty/pybind11/docs/compiling.rst
index f26e6cf602..2b543be0be 100644
--- a/3rdparty/pybind11/docs/compiling.rst
+++ b/3rdparty/pybind11/docs/compiling.rst
@@ -42,10 +42,7 @@ An example of a ``setup.py`` using pybind11's helpers:
         ),
     ]
 
-    setup(
-        ...,
-        ext_modules=ext_modules
-    )
+    setup(..., ext_modules=ext_modules)
 
 If you want to do an automatic search for the highest supported C++ standard,
 that is supported via a ``build_ext`` command override; it will only affect
@@ -64,11 +61,20 @@ that is supported via a ``build_ext`` command override; it will only affect
         ),
     ]
 
-    setup(
-        ...,
-        cmdclass={"build_ext": build_ext},
-        ext_modules=ext_modules
-    )
+    setup(..., cmdclass={"build_ext": build_ext}, ext_modules=ext_modules)
+
+If you have single-file extension modules that are directly stored in the
+Python source tree (``foo.cpp`` in the same directory as where a ``foo.py``
+would be located), you can also generate ``Pybind11Extensions`` using
+``setup_helpers.intree_extensions``: ``intree_extensions(["path/to/foo.cpp",
+...])`` returns a list of ``Pybind11Extensions`` which can be passed to
+``ext_modules``, possibly after further customizing their attributes
+(``libraries``, ``include_dirs``, etc.).  By doing so, a ``foo.*.so`` extension
+module will be generated and made available upon installation.
+
+``intree_extension`` will automatically detect if you are using a ``src``-style
+layout (as long as no namespace packages are involved), but you can also
+explicitly pass ``package_dir`` to it (as in ``setuptools.setup``).
 
 Since pybind11 does not require NumPy when building, a light-weight replacement
 for NumPy's parallel compilation distutils tool is included. Use it like this:
@@ -84,22 +90,23 @@ for NumPy's parallel compilation distutils tool is included. Use it like this:
 
 The argument is the name of an environment variable to control the number of
 threads, such as ``NPY_NUM_BUILD_JOBS`` (as used by NumPy), though you can set
-something different if you want. You can also pass ``default=N`` to set the
-default number of threads (0 will take the number of threads available) and
-``max=N``, the maximum number of threads; if you have a large extension you may
-want set this to a memory dependent number.
+something different if you want; ``CMAKE_BUILD_PARALLEL_LEVEL`` is another choice
+a user might expect. You can also pass ``default=N`` to set the default number
+of threads (0 will take the number of threads available) and ``max=N``, the
+maximum number of threads; if you have a large extension you may want set this
+to a memory dependent number.
 
 If you are developing rapidly and have a lot of C++ files, you may want to
 avoid rebuilding files that have not changed. For simple cases were you are
 using ``pip install -e .`` and do not have local headers, you can skip the
-rebuild if a object file is newer than it's source (headers are not checked!)
+rebuild if an object file is newer than its source (headers are not checked!)
 with the following:
 
 .. code-block:: python
 
     from pybind11.setup_helpers import ParallelCompile, naive_recompile
 
-    SmartCompile("NPY_NUM_BUILD_JOBS", needs_recompile=naive_recompile).install()
+    ParallelCompile("NPY_NUM_BUILD_JOBS", needs_recompile=naive_recompile).install()
 
 
 If you have a more complex build, you can implement a smarter function and pass
@@ -136,7 +143,7 @@ Your ``pyproject.toml`` file will likely look something like this:
 .. code-block:: toml
 
     [build-system]
-    requires = ["setuptools", "wheel", "pybind11==2.6.0"]
+    requires = ["setuptools>=42", "wheel", "pybind11~=2.6.1"]
     build-backend = "setuptools.build_meta"
 
 .. note::
@@ -147,10 +154,12 @@ Your ``pyproject.toml`` file will likely look something like this:
     in Python) using something like `cibuildwheel`_, remember that ``setup.py``
     and ``pyproject.toml`` are not even contained in the wheel, so this high
     Pip requirement is only for source builds, and will not affect users of
-    your binary wheels.
+    your binary wheels. If you are building SDists and wheels, then
+    `pypa-build`_ is the recommended official tool.
 
 .. _PEP 517: https://www.python.org/dev/peps/pep-0517/
 .. _cibuildwheel: https://cibuildwheel.readthedocs.io
+.. _pypa-build: https://pypa-build.readthedocs.io/en/latest/
 
 .. _setup_helpers-setup_requires:
 
@@ -331,7 +340,7 @@ standard explicitly with
 
     set(CMAKE_CXX_STANDARD 14 CACHE STRING "C++ version selection")  # or 11, 14, 17, 20
     set(CMAKE_CXX_STANDARD_REQUIRED ON)  # optional, ensure standard is supported
-    set(CMAKE_CXX_EXTENSIONS OFF)  # optional, keep compiler extensionsn off
+    set(CMAKE_CXX_EXTENSIONS OFF)  # optional, keep compiler extensions off
 
 The variables can also be set when calling CMake from the command line using
 the ``-D<variable>=<value>`` flag. You can also manually set ``CXX_STANDARD``
@@ -401,16 +410,17 @@ can refer to the same [cmake_example]_ repository for a full sample project
 FindPython mode
 ---------------
 
-CMake 3.12+ (3.15+ recommended) added a new module called FindPython that had a
-highly improved search algorithm and modern targets and tools. If you use
-FindPython, pybind11 will detect this and use the existing targets instead:
+CMake 3.12+ (3.15+ recommended, 3.18.2+ ideal) added a new module called
+FindPython that had a highly improved search algorithm and modern targets
+and tools. If you use FindPython, pybind11 will detect this and use the
+existing targets instead:
 
 .. code-block:: cmake
 
-    cmake_minumum_required(VERSION 3.15...3.18)
+    cmake_minimum_required(VERSION 3.15...3.22)
     project(example LANGUAGES CXX)
 
-    find_package(Python COMPONENTS Interpreter Development REQUIRED)
+    find_package(Python 3.6 COMPONENTS Interpreter Development REQUIRED)
     find_package(pybind11 CONFIG REQUIRED)
     # or add_subdirectory(pybind11)
 
@@ -423,9 +433,8 @@ algorithms from the CMake invocation, with ``-DPYBIND11_FINDPYTHON=ON``.
 
 .. warning::
 
-    If you use FindPython2 and FindPython3 to dual-target Python, use the
-    individual targets listed below, and avoid targets that directly include
-    Python parts.
+    If you use FindPython to multi-target Python versions, use the individual
+    targets listed below, and avoid targets that directly include Python parts.
 
 There are `many ways to hint or force a discovery of a specific Python
 installation <https://cmake.org/cmake/help/latest/module/FindPython.html>`_),
@@ -433,6 +442,14 @@ setting ``Python_ROOT_DIR`` may be the most common one (though with
 virtualenv/venv support, and Conda support, this tends to find the correct
 Python version more often than the old system did).
 
+.. warning::
+
+    When the Python libraries (i.e. ``libpythonXX.a`` and ``libpythonXX.so``
+    on Unix) are not available, as is the case on a manylinux image, the
+    ``Development`` component will not be resolved by ``FindPython``. When not
+    using the embedding functionality, CMake 3.18+ allows you to specify
+    ``Development.Module`` instead of ``Development`` to resolve this issue.
+
 .. versionadded:: 2.6
 
 Advanced: interface library targets
@@ -444,11 +461,8 @@ available in all modes. The targets provided are:
    ``pybind11::headers``
      Just the pybind11 headers and minimum compile requirements
 
-   ``pybind11::python2_no_register``
-     Quiets the warning/error when mixing C++14 or higher and Python 2
-
    ``pybind11::pybind11``
-     Python headers + ``pybind11::headers`` + ``pybind11::python2_no_register`` (Python 2 only)
+     Python headers + ``pybind11::headers``
 
    ``pybind11::python_link_helper``
      Just the "linking" part of pybind11:module
@@ -457,7 +471,7 @@ available in all modes. The targets provided are:
      Everything for extension modules - ``pybind11::pybind11`` + ``Python::Module`` (FindPython CMake 3.15+) or ``pybind11::python_link_helper``
 
    ``pybind11::embed``
-     Everything for embedding the Python interpreter - ``pybind11::pybind11`` + ``Python::Embed`` (FindPython) or Python libs
+     Everything for embedding the Python interpreter - ``pybind11::pybind11`` + ``Python::Python`` (FindPython) or Python libs
 
    ``pybind11::lto`` / ``pybind11::thin_lto``
      An alternative to `INTERPROCEDURAL_OPTIMIZATION` for adding link-time optimization.
@@ -491,7 +505,10 @@ You can use these targets to build complex applications. For example, the
     target_link_libraries(example PRIVATE pybind11::module pybind11::lto pybind11::windows_extras)
 
     pybind11_extension(example)
-    pybind11_strip(example)
+    if(NOT MSVC AND NOT ${CMAKE_BUILD_TYPE} MATCHES Debug|RelWithDebInfo)
+        # Strip unnecessary sections of the binary on Linux/macOS
+        pybind11_strip(example)
+    endif()
 
     set_target_properties(example PROPERTIES CXX_VISIBILITY_PRESET "hidden"
                                              CUDA_VISIBILITY_PRESET "hidden")
@@ -504,7 +521,7 @@ Instead of setting properties, you can set ``CMAKE_*`` variables to initialize t
     compiler flags are provided to ensure high quality code generation. In
     contrast to the ``pybind11_add_module()`` command, the CMake interface
     provides a *composable* set of targets to ensure that you retain flexibility.
-    It can be expecially important to provide or set these properties; the
+    It can be especially important to provide or set these properties; the
     :ref:`FAQ <faq:symhidden>` contains an explanation on why these are needed.
 
 .. versionadded:: 2.6
@@ -557,10 +574,7 @@ On Linux, you can compile an example such as the one given in
 
 .. code-block:: bash
 
-    $ c++ -O3 -Wall -shared -std=c++11 -fPIC `python3 -m pybind11 --includes` example.cpp -o example`python3-config --extension-suffix`
-
-The flags given here assume that you're using Python 3. For Python 2, just
-change the executable appropriately (to ``python`` or ``python2``).
+    $ c++ -O3 -Wall -shared -std=c++11 -fPIC $(python3 -m pybind11 --includes) example.cpp -o example$(python3-config --extension-suffix)
 
 The ``python3 -m pybind11 --includes`` command fetches the include paths for
 both pybind11 and Python headers. This assumes that pybind11 has been installed
@@ -568,19 +582,13 @@ using ``pip`` or ``conda``. If it hasn't, you can also manually specify
 ``-I <path-to-pybind11>/include`` together with the Python includes path
 ``python3-config --includes``.
 
-Note that Python 2.7 modules don't use a special suffix, so you should simply
-use ``example.so`` instead of ``example`python3-config --extension-suffix```.
-Besides, the ``--extension-suffix`` option may or may not be available, depending
-on the distribution; in the latter case, the module extension can be manually
-set to ``.so``.
-
 On macOS: the build command is almost the same but it also requires passing
 the ``-undefined dynamic_lookup`` flag so as to ignore missing symbols when
 building the module:
 
 .. code-block:: bash
 
-    $ c++ -O3 -Wall -shared -std=c++11 -undefined dynamic_lookup `python3 -m pybind11 --includes` example.cpp -o example`python3-config --extension-suffix`
+    $ c++ -O3 -Wall -shared -std=c++11 -undefined dynamic_lookup $(python3 -m pybind11 --includes) example.cpp -o example$(python3-config --extension-suffix)
 
 In general, it is advisable to include several additional build parameters
 that can considerably reduce the size of the created binary. Refer to section
diff --git a/3rdparty/pybind11/docs/conf.py b/3rdparty/pybind11/docs/conf.py
index 66db310e46..2da6773f4f 100644
--- a/3rdparty/pybind11/docs/conf.py
+++ b/3rdparty/pybind11/docs/conf.py
@@ -1,5 +1,4 @@
 #!/usr/bin/env python3
-# -*- coding: utf-8 -*-
 #
 # pybind11 documentation build configuration file, created by
 # sphinx-quickstart on Sun Oct 11 19:23:48 2015.
@@ -13,12 +12,11 @@
 # All configuration values have a default; values that are commented out
 # serve to show the default.
 
-import sys
 import os
-import shlex
+import re
 import subprocess
+import sys
 from pathlib import Path
-import re
 
 DIR = Path(__file__).parent.resolve()
 
@@ -37,6 +35,7 @@
 # ones.
 extensions = [
     "breathe",
+    "sphinx_copybutton",
     "sphinxcontrib.rsvgconverter",
     "sphinxcontrib.moderncmakedomain",
 ]
@@ -127,23 +126,7 @@
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
 
-on_rtd = os.environ.get("READTHEDOCS", None) == "True"
-
-if not on_rtd:  # only import and set the theme if we're building docs locally
-    import sphinx_rtd_theme
-
-    html_theme = "sphinx_rtd_theme"
-    html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
-
-    html_context = {"css_files": ["_static/theme_overrides.css"]}
-else:
-    html_context = {
-        "css_files": [
-            "//media.readthedocs.org/css/sphinx_rtd_theme.css",
-            "//media.readthedocs.org/css/readthedocs-doc-embed.css",
-            "_static/theme_overrides.css",
-        ]
-    }
+html_theme = "furo"
 
 # Theme options are theme-specific and customize the look and feel of a theme
 # further.  For a list of options available for each theme, see the
@@ -174,6 +157,10 @@
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ["_static"]
 
+html_css_files = [
+    "css/custom.css",
+]
+
 # Add any extra paths that contain custom files (such as robots.txt or
 # .htaccess) here, relative to this directory. These files are copied
 # directly to the root of the documentation.
@@ -239,6 +226,8 @@
 
 # -- Options for LaTeX output ---------------------------------------------
 
+latex_engine = "pdflatex"
+
 latex_elements = {
     # The paper size ('letterpaper' or 'a4paper').
     # 'papersize': 'letterpaper',
@@ -344,17 +333,20 @@ def generate_doxygen_xml(app):
         subprocess.call(["doxygen", "--version"])
         retcode = subprocess.call(["doxygen"], cwd=app.confdir)
         if retcode < 0:
-            sys.stderr.write("doxygen error code: {}\n".format(-retcode))
+            sys.stderr.write(f"doxygen error code: {-retcode}\n")
     except OSError as e:
-        sys.stderr.write("doxygen execution failed: {}\n".format(e))
+        sys.stderr.write(f"doxygen execution failed: {e}\n")
 
 
 def prepare(app):
     with open(DIR.parent / "README.rst") as f:
         contents = f.read()
 
-    # Filter out section titles for index.rst for LaTeX
     if app.builder.name == "latex":
+        # Remove badges and stuff from start
+        contents = contents[contents.find(r".. start") :]
+
+        # Filter out section titles for index.rst for LaTeX
         contents = re.sub(r"^(.*)\n[-~]{3,}$", r"**\1**", contents, flags=re.MULTILINE)
 
     with open(DIR / "readme.rst", "w") as f:
diff --git a/3rdparty/pybind11/docs/faq.rst b/3rdparty/pybind11/docs/faq.rst
index 8bf05a40a4..28498e7dfc 100644
--- a/3rdparty/pybind11/docs/faq.rst
+++ b/3rdparty/pybind11/docs/faq.rst
@@ -5,12 +5,10 @@ Frequently asked questions
 ===========================================================
 
 1. Make sure that the name specified in PYBIND11_MODULE is identical to the
-filename of the extension library (without suffixes such as .so)
+filename of the extension library (without suffixes such as ``.so``).
 
 2. If the above did not fix the issue, you are likely using an incompatible
-version of Python (for instance, the extension library was compiled against
-Python 2, while the interpreter is running on top of some version of Python
-3, or vice versa).
+version of Python that does not match what you compiled with.
 
 "Symbol not found: ``__Py_ZeroStruct`` / ``_PyInstanceMethod_Type``"
 ========================================================================
@@ -54,7 +52,7 @@ provided by the caller -- in fact, it does nothing at all.
 .. code-block:: python
 
     def increment(i):
-        i += 1 # nope..
+        i += 1  # nope..
 
 pybind11 is also affected by such language-level conventions, which means that
 binding ``increment`` or ``increment_ptr`` will also create Python functions
@@ -147,7 +145,7 @@ using C++14 template metaprogramming.
 
 .. _`faq:hidden_visibility`:
 
-"‘SomeClass’ declared with greater visibility than the type of its field ‘SomeClass::member’ [-Wattributes]"
+"'SomeClass' declared with greater visibility than the type of its field 'SomeClass::member' [-Wattributes]"
 ============================================================================================================
 
 This error typically indicates that you are compiling without the required
@@ -169,8 +167,8 @@ can be changed, but even if it isn't it is not always enough to guarantee
 complete independence of the symbols involved when not using
 ``-fvisibility=hidden``.
 
-Additionally, ``-fvisiblity=hidden`` can deliver considerably binary size
-savings.  (See the following section for more details).
+Additionally, ``-fvisibility=hidden`` can deliver considerably binary size
+savings. (See the following section for more details.)
 
 
 .. _`faq:symhidden`:
@@ -180,7 +178,7 @@ How can I create smaller binaries?
 
 To do its job, pybind11 extensively relies on a programming technique known as
 *template metaprogramming*, which is a way of performing computation at compile
-time using type information. Template metaprogamming usually instantiates code
+time using type information. Template metaprogramming usually instantiates code
 involving significant numbers of deeply nested types that are either completely
 removed or reduced to just a few instructions during the compiler's optimization
 phase. However, due to the nested nature of these types, the resulting symbol
@@ -222,20 +220,6 @@ In addition to decreasing binary size, ``-fvisibility=hidden`` also avoids
 potential serious issues when loading multiple modules and is required for
 proper pybind operation.  See the previous FAQ entry for more details.
 
-Working with ancient Visual Studio 2008 builds on Windows
-=========================================================
-
-The official Windows distributions of Python are compiled using truly
-ancient versions of Visual Studio that lack good C++11 support. Some users
-implicitly assume that it would be impossible to load a plugin built with
-Visual Studio 2015 into a Python distribution that was compiled using Visual
-Studio 2008. However, no such issue exists: it's perfectly legitimate to
-interface DLLs that are built with different compilers and/or C libraries.
-Common gotchas to watch out for involve not ``free()``-ing memory region
-that that were ``malloc()``-ed in another shared library, using data
-structures with incompatible ABIs, and so on. pybind11 is very careful not
-to make these types of mistakes.
-
 How can I properly handle Ctrl-C in long-running functions?
 ===========================================================
 
@@ -289,27 +273,7 @@ Conflicts can arise, however, when using pybind11 in a project that *also* uses
 the CMake Python detection in a system with several Python versions installed.
 
 This difference may cause inconsistencies and errors if *both* mechanisms are
-used in the same project. Consider the following CMake code executed in a
-system with Python 2.7 and 3.x installed:
-
-.. code-block:: cmake
-
-    find_package(PythonInterp)
-    find_package(PythonLibs)
-    find_package(pybind11)
-
-It will detect Python 2.7 and pybind11 will pick it as well.
-
-In contrast this code:
-
-.. code-block:: cmake
-
-    find_package(pybind11)
-    find_package(PythonInterp)
-    find_package(PythonLibs)
-
-will detect Python 3.x for pybind11 and may crash on
-``find_package(PythonLibs)`` afterwards.
+used in the same project.
 
 There are three possible solutions:
 
diff --git a/3rdparty/pybind11/docs/installing.rst b/3rdparty/pybind11/docs/installing.rst
index 2597285981..30b9f1853d 100644
--- a/3rdparty/pybind11/docs/installing.rst
+++ b/3rdparty/pybind11/docs/installing.rst
@@ -8,6 +8,8 @@ There are several ways to get the pybind11 source, which lives at
 developers recommend one of the first three ways listed here, submodule, PyPI,
 or conda-forge, for obtaining pybind11.
 
+.. _include_as_a_submodule:
+
 Include as a submodule
 ======================
 
@@ -16,7 +18,7 @@ as a submodule. From your git repository, use:
 
 .. code-block:: bash
 
-    git submodule add ../../pybind/pybind11 extern/pybind11 -b stable
+    git submodule add -b stable ../../pybind/pybind11 extern/pybind11
     git submodule update --init
 
 This assumes you are placing your dependencies in ``extern/``, and that you are
diff --git a/3rdparty/pybind11/docs/limitations.rst b/3rdparty/pybind11/docs/limitations.rst
index be7300cdb6..def5ad659c 100644
--- a/3rdparty/pybind11/docs/limitations.rst
+++ b/3rdparty/pybind11/docs/limitations.rst
@@ -57,16 +57,16 @@ clean, well written patch would likely be accepted to solve them.
 Python 3.9.0 warning
 ^^^^^^^^^^^^^^^^^^^^
 
-Combining older versions of pybind11 (< 2.6.0) with Python on 3.9.0 will
-trigger undefined behavior that typically manifests as crashes during
+Combining older versions of pybind11 (< 2.6.0) with Python on exactly 3.9.0
+will trigger undefined behavior that typically manifests as crashes during
 interpreter shutdown (but could also destroy your data. **You have been
 warned**).
 
-This issue has been
-`fixed in Python <https://github.com/python/cpython/pull/22670>`_.  As a
-mitigation until 3.9.1 is released and commonly used, pybind11 (2.6.0 or newer)
-includes a temporary workaround specifically when Python 3.9.0 is detected at
-runtime, leaking about 50 bytes of memory when a callback function is garbage
-collected. For reference; the pybind11 test suite has about 2,000 such
-callbacks, but only 49 are garbage collected before the end-of-process. Wheels
-built with Python 3.9.0 will correctly avoid the leak when run in Python 3.9.1.
+This issue was `fixed in Python <https://github.com/python/cpython/pull/22670>`_.
+As a mitigation for this bug, pybind11 2.6.0 or newer includes a workaround
+specifically when Python 3.9.0 is detected at runtime, leaking about 50 bytes
+of memory when a callback function is garbage collected.  For reference, the
+pybind11 test suite has about 2,000 such callbacks, but only 49 are garbage
+collected before the end-of-process. Wheels (even if built with Python 3.9.0)
+will correctly avoid the leak when run in Python 3.9.1, and this does not
+affect other 3.X versions.
diff --git a/3rdparty/pybind11/docs/pybind11-logo.png b/3rdparty/pybind11/docs/pybind11-logo.png
index 4cbad54f797d3ced04d4048f282df5e4336d4af4..2d633a4d0c129d6bdd94b4134c9516fdc92bb192 100644
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diff --git a/3rdparty/pybind11/docs/reference.rst b/3rdparty/pybind11/docs/reference.rst
index e3a61afb6b..e64a03519d 100644
--- a/3rdparty/pybind11/docs/reference.rst
+++ b/3rdparty/pybind11/docs/reference.rst
@@ -52,6 +52,20 @@ Convenience classes for specific Python types
 .. doxygengroup:: pytypes
     :members:
 
+Convenience functions converting to Python types
+================================================
+
+.. doxygenfunction:: make_tuple(Args&&...)
+
+.. doxygenfunction:: make_iterator(Iterator, Sentinel, Extra &&...)
+.. doxygenfunction:: make_iterator(Type &, Extra&&...)
+
+.. doxygenfunction:: make_key_iterator(Iterator, Sentinel, Extra &&...)
+.. doxygenfunction:: make_key_iterator(Type &, Extra&&...)
+
+.. doxygenfunction:: make_value_iterator(Iterator, Sentinel, Extra &&...)
+.. doxygenfunction:: make_value_iterator(Type &, Extra&&...)
+
 .. _extras:
 
 Passing extra arguments to ``def`` or ``class_``
@@ -110,7 +124,6 @@ Exceptions
 .. doxygenclass:: builtin_exception
     :members:
 
-
 Literals
 ========
 
diff --git a/3rdparty/pybind11/docs/release.rst b/3rdparty/pybind11/docs/release.rst
index 43f502a154..e761cdf7a6 100644
--- a/3rdparty/pybind11/docs/release.rst
+++ b/3rdparty/pybind11/docs/release.rst
@@ -15,26 +15,37 @@ For example:
 
 For beta, ``PYBIND11_VERSION_PATCH`` should be ``Z.b1``. RC's can be ``Z.rc1``.
 Always include the dot (even though PEP 440 allows it to be dropped). For a
-final release, this must be a simple integer.
+final release, this must be a simple integer. There is also a HEX version of
+the version just below.
 
 
 To release a new version of pybind11:
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
+If you don't have nox, you should either use ``pipx run nox`` instead, or use
+``pipx install nox`` or ``brew install nox`` (Unix).
+
 - Update the version number
-  - Update ``PYBIND11_VERSION_MAJOR`` etc. in
-    ``include/pybind11/detail/common.h``. PATCH should be a simple integer.
-  - Update ``pybind11/_version.py`` (match above)
-  - Ensure that all the information in ``setup.py`` is up-to-date.
-  - Add release date in ``docs/changelog.rst``.
-  - ``git add`` and ``git commit``, ``git push``. **Ensure CI passes**. (If it
-    fails due to a known flake issue, either ignore or restart CI.)
-- Add a release branch if this is a new minor version
-  - ``git checkout -b vX.Y``, ``git push -u origin vX.Y``
+    - Update ``PYBIND11_VERSION_MAJOR`` etc. in
+      ``include/pybind11/detail/common.h``. PATCH should be a simple integer.
+    - Update the version HEX just below, as well.
+    - Update ``pybind11/_version.py`` (match above)
+    - Run ``nox -s tests_packaging`` to ensure this was done correctly.
+    - Ensure that all the information in ``setup.cfg`` is up-to-date, like
+      supported Python versions.
+    - Add release date in ``docs/changelog.rst``.
+          - Check to make sure
+            `needs-changelog <https://github.com/pybind/pybind11/pulls?q=is%3Apr+is%3Aclosed+label%3A%22needs+changelog%22>`_
+            issues are entered in the changelog (clear the label when done).
+    - ``git add`` and ``git commit``, ``git push``. **Ensure CI passes**. (If it
+      fails due to a known flake issue, either ignore or restart CI.)
+- Add a release branch if this is a new minor version, or update the existing release branch if it is a patch version
+    - New branch: ``git checkout -b vX.Y``, ``git push -u origin vX.Y``
+    - Update branch: ``git checkout vX.Y``, ``git merge <release branch>``, ``git push``
 - Update tags (optional; if you skip this, the GitHub release makes a
-  non-annotated tag for you)
-  - ``git tag -a vX.Y.Z -m 'vX.Y.Z release'``.
-  - ``git push --tags``.
+    non-annotated tag for you)
+    - ``git tag -a vX.Y.Z -m 'vX.Y.Z release'``.
+    - ``git push --tags``.
 - Update stable
     - ``git checkout stable``
     - ``git merge master``
@@ -42,25 +53,36 @@ To release a new version of pybind11:
 - Make a GitHub release (this shows up in the UI, sends new release
   notifications to users watching releases, and also uploads PyPI packages).
   (Note: if you do not use an existing tag, this creates a new lightweight tag
-  for you, so you could skip the above step).
-  - GUI method: click "Create a new release" on the far right, fill in the tag
-    name (if you didn't tag above, it will be made here), fill in a release
-    name like "Version X.Y.Z", and optionally copy-and-paste the changelog into
-    the description (processed as markdown by Pandoc). Check "pre-release" if
-    this is a beta/RC.
-  - CLI method: with ``gh`` installed, run ``gh release create vX.Y.Z -t "Version X.Y.Z"``
-    If this is a pre-release, add ``-p``.
+  for you, so you could skip the above step.)
+    - GUI method: Under `releases <https://github.com/pybind/pybind11/releases>`_
+      click "Draft a new release" on the far right, fill in the tag name
+      (if you didn't tag above, it will be made here), fill in a release name
+      like "Version X.Y.Z", and copy-and-paste the markdown-formatted (!) changelog
+      into the description (usually ``cat docs/changelog.rst | pandoc -f rst -t gfm``).
+      Check "pre-release" if this is a beta/RC.
+    - CLI method: with ``gh`` installed, run ``gh release create vX.Y.Z -t "Version X.Y.Z"``
+      If this is a pre-release, add ``-p``.
 
 - Get back to work
-  - Make sure you are on master, not somewhere else: ``git checkout master``
-  - Update version macros in ``include/pybind11/detail/common.h`` (set PATCH to
-    ``0.dev1`` and increment MINOR).
-  - Update ``_version.py`` to match
-  - Add a plot for in-development updates in ``docs/changelog.rst``.
-  - ``git add``, ``git commit``, ``git push``
+    - Make sure you are on master, not somewhere else: ``git checkout master``
+    - Update version macros in ``include/pybind11/detail/common.h`` (set PATCH to
+      ``0.dev1`` and increment MINOR).
+    - Update ``_version.py`` to match
+    - Run ``nox -s tests_packaging`` to ensure this was done correctly.
+    - Add a spot for in-development updates in ``docs/changelog.rst``.
+    - ``git add``, ``git commit``, ``git push``
 
 If a version branch is updated, remember to set PATCH to ``1.dev1``.
 
+If you'd like to bump homebrew, run:
+
+.. code-block:: console
+
+    brew bump-formula-pr --url https://github.com/pybind/pybind11/archive/vX.Y.Z.tar.gz
+
+Conda-forge should automatically make a PR in a few hours, and automatically
+merge it if there are no issues.
+
 
 Manual packaging
 ^^^^^^^^^^^^^^^^
@@ -69,9 +91,7 @@ If you need to manually upload releases, you can download the releases from the
 
 .. code-block:: bash
 
-    python3 -m pip install build
-    python3 -m build
-    PYBIND11_SDIST_GLOBAL=1 python3 -m build
+    nox -s build
     twine upload dist/*
 
 This makes SDists and wheels, and the final line uploads them.
diff --git a/3rdparty/pybind11/docs/requirements.txt b/3rdparty/pybind11/docs/requirements.txt
index 35366e3c8a..d2a9ae1645 100644
--- a/3rdparty/pybind11/docs/requirements.txt
+++ b/3rdparty/pybind11/docs/requirements.txt
@@ -1,7 +1,6 @@
-breathe==4.20.0
-commonmark==0.9.1
-recommonmark==0.6.0
-sphinx==3.2.1
-sphinx_rtd_theme==0.5.0
-sphinxcontrib-moderncmakedomain==3.13
-sphinxcontrib-svg2pdfconverter==1.1.0
+breathe==4.34.0
+furo==2022.6.21
+sphinx==5.0.2
+sphinx-copybutton==0.5.0
+sphinxcontrib-moderncmakedomain==3.21.4
+sphinxcontrib-svg2pdfconverter==1.2.0
diff --git a/3rdparty/pybind11/docs/upgrade.rst b/3rdparty/pybind11/docs/upgrade.rst
index 87bcebee2c..6a9db2d08f 100644
--- a/3rdparty/pybind11/docs/upgrade.rst
+++ b/3rdparty/pybind11/docs/upgrade.rst
@@ -8,6 +8,46 @@ to a new version. But it goes into more detail. This includes things like
 deprecated APIs and their replacements, build system changes, general code
 modernization and other useful information.
 
+.. _upgrade-guide-2.9:
+
+v2.9
+====
+
+* Any usage of the recently added ``py::make_simple_namespace`` should be
+  converted to using ``py::module_::import("types").attr("SimpleNamespace")``
+  instead.
+
+* The use of ``_`` in custom type casters can now be replaced with the more
+  readable ``const_name`` instead. The old ``_`` shortcut has been retained
+  unless it is being used as a macro (like for gettext).
+
+
+.. _upgrade-guide-2.7:
+
+v2.7
+====
+
+*Before* v2.7, ``py::str`` can hold ``PyUnicodeObject`` or ``PyBytesObject``,
+and ``py::isinstance<str>()`` is ``true`` for both ``py::str`` and
+``py::bytes``. Starting with v2.7, ``py::str`` exclusively holds
+``PyUnicodeObject`` (`#2409 <https://github.com/pybind/pybind11/pull/2409>`_),
+and ``py::isinstance<str>()`` is ``true`` only for ``py::str``. To help in
+the transition of user code, the ``PYBIND11_STR_LEGACY_PERMISSIVE`` macro
+is provided as an escape hatch to go back to the legacy behavior. This macro
+will be removed in future releases. Two types of required fixes are expected
+to be common:
+
+* Accidental use of ``py::str`` instead of ``py::bytes``, masked by the legacy
+  behavior. These are probably very easy to fix, by changing from
+  ``py::str`` to ``py::bytes``.
+
+* Reliance on py::isinstance<str>(obj) being ``true`` for
+  ``py::bytes``. This is likely to be easy to fix in most cases by adding
+  ``|| py::isinstance<bytes>(obj)``, but a fix may be more involved, e.g. if
+  ``py::isinstance<T>`` appears in a template. Such situations will require
+  careful review and custom fixes.
+
+
 .. _upgrade-guide-2.6:
 
 v2.6
@@ -192,7 +232,7 @@ way to get and set object state. See :ref:`pickling` for details.
         ...
         .def(py::pickle(
             [](const Foo &self) { // __getstate__
-                return py::make_tuple(f.value1(), f.value2(), ...); // unchanged
+                return py::make_tuple(self.value1(), self.value2(), ...); // unchanged
             },
             [](py::tuple t) { // __setstate__, note: no `self` argument
                 return new Foo(t[0].cast<std::string>(), ...);
@@ -256,7 +296,7 @@ Within pybind11's CMake build system, ``pybind11_add_module`` has always been
 setting the ``-fvisibility=hidden`` flag in release mode. From now on, it's
 being applied unconditionally, even in debug mode and it can no longer be opted
 out of with the ``NO_EXTRAS`` option. The ``pybind11::module`` target now also
-adds this flag to it's interface. The ``pybind11::embed`` target is unchanged.
+adds this flag to its interface. The ``pybind11::embed`` target is unchanged.
 
 The most significant change here is for the ``pybind11::module`` target. If you
 were previously relying on default visibility, i.e. if your Python module was
@@ -484,7 +524,7 @@ include a declaration of the form:
 
     PYBIND11_DECLARE_HOLDER_TYPE(T, std::shared_ptr<T>)
 
-Continuing to do so won’t cause an error or even a deprecation warning,
+Continuing to do so won't cause an error or even a deprecation warning,
 but it's completely redundant.
 
 
diff --git a/3rdparty/pybind11/include/pybind11/attr.h b/3rdparty/pybind11/include/pybind11/attr.h
index 0c41670926..db7cd8efff 100644
--- a/3rdparty/pybind11/include/pybind11/attr.h
+++ b/3rdparty/pybind11/include/pybind11/attr.h
@@ -10,72 +10,113 @@
 
 #pragma once
 
+#include "detail/common.h"
 #include "cast.h"
 
+#include <functional>
+
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
 /// \addtogroup annotations
 /// @{
 
 /// Annotation for methods
-struct is_method { handle class_; is_method(const handle &c) : class_(c) { } };
+struct is_method {
+    handle class_;
+    explicit is_method(const handle &c) : class_(c) {}
+};
 
 /// Annotation for operators
-struct is_operator { };
+struct is_operator {};
 
 /// Annotation for classes that cannot be subclassed
-struct is_final { };
+struct is_final {};
 
 /// Annotation for parent scope
-struct scope { handle value; scope(const handle &s) : value(s) { } };
+struct scope {
+    handle value;
+    explicit scope(const handle &s) : value(s) {}
+};
 
 /// Annotation for documentation
-struct doc { const char *value; doc(const char *value) : value(value) { } };
+struct doc {
+    const char *value;
+    explicit doc(const char *value) : value(value) {}
+};
 
 /// Annotation for function names
-struct name { const char *value; name(const char *value) : value(value) { } };
+struct name {
+    const char *value;
+    explicit name(const char *value) : value(value) {}
+};
 
 /// Annotation indicating that a function is an overload associated with a given "sibling"
-struct sibling { handle value; sibling(const handle &value) : value(value.ptr()) { } };
+struct sibling {
+    handle value;
+    explicit sibling(const handle &value) : value(value.ptr()) {}
+};
 
 /// Annotation indicating that a class derives from another given type
-template <typename T> struct base {
+template <typename T>
+struct base {
 
-    PYBIND11_DEPRECATED("base<T>() was deprecated in favor of specifying 'T' as a template argument to class_")
-    base() { } // NOLINT(modernize-use-equals-default): breaks MSVC 2015 when adding an attribute
+    PYBIND11_DEPRECATED(
+        "base<T>() was deprecated in favor of specifying 'T' as a template argument to class_")
+    base() = default;
 };
 
 /// Keep patient alive while nurse lives
-template <size_t Nurse, size_t Patient> struct keep_alive { };
+template <size_t Nurse, size_t Patient>
+struct keep_alive {};
 
 /// Annotation indicating that a class is involved in a multiple inheritance relationship
-struct multiple_inheritance { };
+struct multiple_inheritance {};
 
 /// Annotation which enables dynamic attributes, i.e. adds `__dict__` to a class
-struct dynamic_attr { };
+struct dynamic_attr {};
 
 /// Annotation which enables the buffer protocol for a type
-struct buffer_protocol { };
+struct buffer_protocol {};
 
 /// Annotation which requests that a special metaclass is created for a type
 struct metaclass {
     handle value;
 
     PYBIND11_DEPRECATED("py::metaclass() is no longer required. It's turned on by default now.")
-    metaclass() { } // NOLINT(modernize-use-equals-default): breaks MSVC 2015 when adding an attribute
+    metaclass() = default;
 
     /// Override pybind11's default metaclass
-    explicit metaclass(handle value) : value(value) { }
+    explicit metaclass(handle value) : value(value) {}
+};
+
+/// Specifies a custom callback with signature `void (PyHeapTypeObject*)` that
+/// may be used to customize the Python type.
+///
+/// The callback is invoked immediately before `PyType_Ready`.
+///
+/// Note: This is an advanced interface, and uses of it may require changes to
+/// work with later versions of pybind11.  You may wish to consult the
+/// implementation of `make_new_python_type` in `detail/classes.h` to understand
+/// the context in which the callback will be run.
+struct custom_type_setup {
+    using callback = std::function<void(PyHeapTypeObject *heap_type)>;
+
+    explicit custom_type_setup(callback value) : value(std::move(value)) {}
+
+    callback value;
 };
 
 /// Annotation that marks a class as local to the module:
-struct module_local { const bool value; constexpr module_local(bool v = true) : value(v) { } };
+struct module_local {
+    const bool value;
+    constexpr explicit module_local(bool v = true) : value(v) {}
+};
 
 /// Annotation to mark enums as an arithmetic type
-struct arithmetic { };
+struct arithmetic {};
 
 /// Mark a function for addition at the beginning of the existing overload chain instead of the end
-struct prepend { };
+struct prepend {};
 
 /** \rst
     A call policy which places one or more guard variables (``Ts...``) around the function call.
@@ -95,9 +136,13 @@ struct prepend { };
             return foo(args...); // forwarded arguments
         });
  \endrst */
-template <typename... Ts> struct call_guard;
+template <typename... Ts>
+struct call_guard;
 
-template <> struct call_guard<> { using type = detail::void_type; };
+template <>
+struct call_guard<> {
+    using type = detail::void_type;
+};
 
 template <typename T>
 struct call_guard<T> {
@@ -122,8 +167,9 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 enum op_id : int;
 enum op_type : int;
 struct undefined_t;
-template <op_id id, op_type ot, typename L = undefined_t, typename R = undefined_t> struct op_;
-inline void keep_alive_impl(size_t Nurse, size_t Patient, function_call &call, handle ret);
+template <op_id id, op_type ot, typename L = undefined_t, typename R = undefined_t>
+struct op_;
+void keep_alive_impl(size_t Nurse, size_t Patient, function_call &call, handle ret);
 
 /// Internal data structure which holds metadata about a keyword argument
 struct argument_record {
@@ -134,15 +180,16 @@ struct argument_record {
     bool none : 1;     ///< True if None is allowed when loading
 
     argument_record(const char *name, const char *descr, handle value, bool convert, bool none)
-        : name(name), descr(descr), value(value), convert(convert), none(none) { }
+        : name(name), descr(descr), value(value), convert(convert), none(none) {}
 };
 
-/// Internal data structure which holds metadata about a bound function (signature, overloads, etc.)
+/// Internal data structure which holds metadata about a bound function (signature, overloads,
+/// etc.)
 struct function_record {
     function_record()
         : is_constructor(false), is_new_style_constructor(false), is_stateless(false),
-          is_operator(false), is_method(false), has_args(false),
-          has_kwargs(false), has_kw_only_args(false), prepend(false) { }
+          is_operator(false), is_method(false), has_args(false), has_kwargs(false),
+          prepend(false) {}
 
     /// Function name
     char *name = nullptr; /* why no C++ strings? They generate heavier code.. */
@@ -157,13 +204,13 @@ struct function_record {
     std::vector<argument_record> args;
 
     /// Pointer to lambda function which converts arguments and performs the actual call
-    handle (*impl) (function_call &) = nullptr;
+    handle (*impl)(function_call &) = nullptr;
 
     /// Storage for the wrapped function pointer and captured data, if any
-    void *data[3] = { };
+    void *data[3] = {};
 
     /// Pointer to custom destructor for 'data' (if needed)
-    void (*free_data) (function_record *ptr) = nullptr;
+    void (*free_data)(function_record *ptr) = nullptr;
 
     /// Return value policy associated with this function
     return_value_policy policy = return_value_policy::automatic;
@@ -189,17 +236,15 @@ struct function_record {
     /// True if the function has a '**kwargs' argument
     bool has_kwargs : 1;
 
-    /// True once a 'py::kw_only' is encountered (any following args are keyword-only)
-    bool has_kw_only_args : 1;
-
     /// True if this function is to be inserted at the beginning of the overload resolution chain
     bool prepend : 1;
 
     /// Number of arguments (including py::args and/or py::kwargs, if present)
     std::uint16_t nargs;
 
-    /// Number of trailing arguments (counted in `nargs`) that are keyword-only
-    std::uint16_t nargs_kw_only = 0;
+    /// Number of leading positional arguments, which are terminated by a py::args or py::kwargs
+    /// argument or by a py::kw_only annotation.
+    std::uint16_t nargs_pos = 0;
 
     /// Number of leading arguments (counted in `nargs`) that are positional-only
     std::uint16_t nargs_pos_only = 0;
@@ -221,7 +266,7 @@ struct function_record {
 struct type_record {
     PYBIND11_NOINLINE type_record()
         : multiple_inheritance(false), dynamic_attr(false), buffer_protocol(false),
-          default_holder(true), module_local(false), is_final(false) { }
+          default_holder(true), module_local(false), is_final(false) {}
 
     /// Handle to the parent scope
     handle scope;
@@ -259,6 +304,9 @@ struct type_record {
     /// Custom metaclass (optional)
     handle metaclass;
 
+    /// Custom type setup.
+    custom_type_setup::callback custom_type_setup_callback;
+
     /// Multiple inheritance marker
     bool multiple_inheritance : 1;
 
@@ -277,42 +325,45 @@ struct type_record {
     /// Is the class inheritable from python classes?
     bool is_final : 1;
 
-    PYBIND11_NOINLINE void add_base(const std::type_info &base, void *(*caster)(void *)) {
-        auto base_info = detail::get_type_info(base, false);
+    PYBIND11_NOINLINE void add_base(const std::type_info &base, void *(*caster)(void *) ) {
+        auto *base_info = detail::get_type_info(base, false);
         if (!base_info) {
             std::string tname(base.name());
             detail::clean_type_id(tname);
-            pybind11_fail("generic_type: type \"" + std::string(name) +
-                          "\" referenced unknown base type \"" + tname + "\"");
+            pybind11_fail("generic_type: type \"" + std::string(name)
+                          + "\" referenced unknown base type \"" + tname + "\"");
         }
 
         if (default_holder != base_info->default_holder) {
             std::string tname(base.name());
             detail::clean_type_id(tname);
-            pybind11_fail("generic_type: type \"" + std::string(name) + "\" " +
-                    (default_holder ? "does not have" : "has") +
-                    " a non-default holder type while its base \"" + tname + "\" " +
-                    (base_info->default_holder ? "does not" : "does"));
+            pybind11_fail("generic_type: type \"" + std::string(name) + "\" "
+                          + (default_holder ? "does not have" : "has")
+                          + " a non-default holder type while its base \"" + tname + "\" "
+                          + (base_info->default_holder ? "does not" : "does"));
         }
 
         bases.append((PyObject *) base_info->type);
 
-        if (base_info->type->tp_dictoffset != 0)
-            dynamic_attr = true;
+#if PY_VERSION_HEX < 0x030B0000
+        dynamic_attr |= base_info->type->tp_dictoffset != 0;
+#else
+        dynamic_attr |= (base_info->type->tp_flags & Py_TPFLAGS_MANAGED_DICT) != 0;
+#endif
 
-        if (caster)
+        if (caster) {
             base_info->implicit_casts.emplace_back(type, caster);
+        }
     }
 };
 
-inline function_call::function_call(const function_record &f, handle p) :
-        func(f), parent(p) {
+inline function_call::function_call(const function_record &f, handle p) : func(f), parent(p) {
     args.reserve(f.nargs);
     args_convert.reserve(f.nargs);
 }
 
 /// Tag for a new-style `__init__` defined in `detail/init.h`
-struct is_new_style_constructor { };
+struct is_new_style_constructor {};
 
 /**
  * Partial template specializations to process custom attributes provided to
@@ -320,129 +371,177 @@ struct is_new_style_constructor { };
  * fields in the type_record and function_record data structures or executed at
  * runtime to deal with custom call policies (e.g. keep_alive).
  */
-template <typename T, typename SFINAE = void> struct process_attribute;
+template <typename T, typename SFINAE = void>
+struct process_attribute;
 
-template <typename T> struct process_attribute_default {
+template <typename T>
+struct process_attribute_default {
     /// Default implementation: do nothing
-    static void init(const T &, function_record *) { }
-    static void init(const T &, type_record *) { }
-    static void precall(function_call &) { }
-    static void postcall(function_call &, handle) { }
+    static void init(const T &, function_record *) {}
+    static void init(const T &, type_record *) {}
+    static void precall(function_call &) {}
+    static void postcall(function_call &, handle) {}
 };
 
 /// Process an attribute specifying the function's name
-template <> struct process_attribute<name> : process_attribute_default<name> {
+template <>
+struct process_attribute<name> : process_attribute_default<name> {
     static void init(const name &n, function_record *r) { r->name = const_cast<char *>(n.value); }
 };
 
 /// Process an attribute specifying the function's docstring
-template <> struct process_attribute<doc> : process_attribute_default<doc> {
+template <>
+struct process_attribute<doc> : process_attribute_default<doc> {
     static void init(const doc &n, function_record *r) { r->doc = const_cast<char *>(n.value); }
 };
 
 /// Process an attribute specifying the function's docstring (provided as a C-style string)
-template <> struct process_attribute<const char *> : process_attribute_default<const char *> {
+template <>
+struct process_attribute<const char *> : process_attribute_default<const char *> {
     static void init(const char *d, function_record *r) { r->doc = const_cast<char *>(d); }
     static void init(const char *d, type_record *r) { r->doc = const_cast<char *>(d); }
 };
-template <> struct process_attribute<char *> : process_attribute<const char *> { };
+template <>
+struct process_attribute<char *> : process_attribute<const char *> {};
 
 /// Process an attribute indicating the function's return value policy
-template <> struct process_attribute<return_value_policy> : process_attribute_default<return_value_policy> {
+template <>
+struct process_attribute<return_value_policy> : process_attribute_default<return_value_policy> {
     static void init(const return_value_policy &p, function_record *r) { r->policy = p; }
 };
 
-/// Process an attribute which indicates that this is an overloaded function associated with a given sibling
-template <> struct process_attribute<sibling> : process_attribute_default<sibling> {
+/// Process an attribute which indicates that this is an overloaded function associated with a
+/// given sibling
+template <>
+struct process_attribute<sibling> : process_attribute_default<sibling> {
     static void init(const sibling &s, function_record *r) { r->sibling = s.value; }
 };
 
 /// Process an attribute which indicates that this function is a method
-template <> struct process_attribute<is_method> : process_attribute_default<is_method> {
-    static void init(const is_method &s, function_record *r) { r->is_method = true; r->scope = s.class_; }
+template <>
+struct process_attribute<is_method> : process_attribute_default<is_method> {
+    static void init(const is_method &s, function_record *r) {
+        r->is_method = true;
+        r->scope = s.class_;
+    }
 };
 
 /// Process an attribute which indicates the parent scope of a method
-template <> struct process_attribute<scope> : process_attribute_default<scope> {
+template <>
+struct process_attribute<scope> : process_attribute_default<scope> {
     static void init(const scope &s, function_record *r) { r->scope = s.value; }
 };
 
 /// Process an attribute which indicates that this function is an operator
-template <> struct process_attribute<is_operator> : process_attribute_default<is_operator> {
+template <>
+struct process_attribute<is_operator> : process_attribute_default<is_operator> {
     static void init(const is_operator &, function_record *r) { r->is_operator = true; }
 };
 
-template <> struct process_attribute<is_new_style_constructor> : process_attribute_default<is_new_style_constructor> {
-    static void init(const is_new_style_constructor &, function_record *r) { r->is_new_style_constructor = true; }
+template <>
+struct process_attribute<is_new_style_constructor>
+    : process_attribute_default<is_new_style_constructor> {
+    static void init(const is_new_style_constructor &, function_record *r) {
+        r->is_new_style_constructor = true;
+    }
 };
 
-inline void process_kw_only_arg(const arg &a, function_record *r) {
-    if (!a.name || strlen(a.name) == 0)
-        pybind11_fail("arg(): cannot specify an unnamed argument after an kw_only() annotation");
-    ++r->nargs_kw_only;
+inline void check_kw_only_arg(const arg &a, function_record *r) {
+    if (r->args.size() > r->nargs_pos && (!a.name || a.name[0] == '\0')) {
+        pybind11_fail("arg(): cannot specify an unnamed argument after a kw_only() annotation or "
+                      "args() argument");
+    }
+}
+
+inline void append_self_arg_if_needed(function_record *r) {
+    if (r->is_method && r->args.empty()) {
+        r->args.emplace_back("self", nullptr, handle(), /*convert=*/true, /*none=*/false);
+    }
 }
 
 /// Process a keyword argument attribute (*without* a default value)
-template <> struct process_attribute<arg> : process_attribute_default<arg> {
+template <>
+struct process_attribute<arg> : process_attribute_default<arg> {
     static void init(const arg &a, function_record *r) {
-        if (r->is_method && r->args.empty())
-            r->args.emplace_back("self", nullptr, handle(), true /*convert*/, false /*none not allowed*/);
+        append_self_arg_if_needed(r);
         r->args.emplace_back(a.name, nullptr, handle(), !a.flag_noconvert, a.flag_none);
 
-        if (r->has_kw_only_args) process_kw_only_arg(a, r);
+        check_kw_only_arg(a, r);
     }
 };
 
 /// Process a keyword argument attribute (*with* a default value)
-template <> struct process_attribute<arg_v> : process_attribute_default<arg_v> {
+template <>
+struct process_attribute<arg_v> : process_attribute_default<arg_v> {
     static void init(const arg_v &a, function_record *r) {
-        if (r->is_method && r->args.empty())
-            r->args.emplace_back("self", nullptr /*descr*/, handle() /*parent*/, true /*convert*/, false /*none not allowed*/);
+        if (r->is_method && r->args.empty()) {
+            r->args.emplace_back(
+                "self", /*descr=*/nullptr, /*parent=*/handle(), /*convert=*/true, /*none=*/false);
+        }
 
         if (!a.value) {
-#if !defined(NDEBUG)
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
             std::string descr("'");
-            if (a.name) descr += std::string(a.name) + ": ";
+            if (a.name) {
+                descr += std::string(a.name) + ": ";
+            }
             descr += a.type + "'";
             if (r->is_method) {
-                if (r->name)
-                    descr += " in method '" + (std::string) str(r->scope) + "." + (std::string) r->name + "'";
-                else
+                if (r->name) {
+                    descr += " in method '" + (std::string) str(r->scope) + "."
+                             + (std::string) r->name + "'";
+                } else {
                     descr += " in method of '" + (std::string) str(r->scope) + "'";
+                }
             } else if (r->name) {
                 descr += " in function '" + (std::string) r->name + "'";
             }
-            pybind11_fail("arg(): could not convert default argument "
-                          + descr + " into a Python object (type not registered yet?)");
+            pybind11_fail("arg(): could not convert default argument " + descr
+                          + " into a Python object (type not registered yet?)");
 #else
             pybind11_fail("arg(): could not convert default argument "
                           "into a Python object (type not registered yet?). "
-                          "Compile in debug mode for more information.");
+                          "#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for "
+                          "more information.");
 #endif
         }
         r->args.emplace_back(a.name, a.descr, a.value.inc_ref(), !a.flag_noconvert, a.flag_none);
 
-        if (r->has_kw_only_args) process_kw_only_arg(a, r);
+        check_kw_only_arg(a, r);
     }
 };
 
 /// Process a keyword-only-arguments-follow pseudo argument
-template <> struct process_attribute<kw_only> : process_attribute_default<kw_only> {
+template <>
+struct process_attribute<kw_only> : process_attribute_default<kw_only> {
     static void init(const kw_only &, function_record *r) {
-        r->has_kw_only_args = true;
+        append_self_arg_if_needed(r);
+        if (r->has_args && r->nargs_pos != static_cast<std::uint16_t>(r->args.size())) {
+            pybind11_fail("Mismatched args() and kw_only(): they must occur at the same relative "
+                          "argument location (or omit kw_only() entirely)");
+        }
+        r->nargs_pos = static_cast<std::uint16_t>(r->args.size());
     }
 };
 
 /// Process a positional-only-argument maker
-template <> struct process_attribute<pos_only> : process_attribute_default<pos_only> {
+template <>
+struct process_attribute<pos_only> : process_attribute_default<pos_only> {
     static void init(const pos_only &, function_record *r) {
+        append_self_arg_if_needed(r);
         r->nargs_pos_only = static_cast<std::uint16_t>(r->args.size());
+        if (r->nargs_pos_only > r->nargs_pos) {
+            pybind11_fail("pos_only(): cannot follow a py::args() argument");
+        }
+        // It also can't follow a kw_only, but a static_assert in pybind11.h checks that
     }
 };
 
-/// Process a parent class attribute.  Single inheritance only (class_ itself already guarantees that)
+/// Process a parent class attribute.  Single inheritance only (class_ itself already guarantees
+/// that)
 template <typename T>
-struct process_attribute<T, enable_if_t<is_pyobject<T>::value>> : process_attribute_default<handle> {
+struct process_attribute<T, enable_if_t<is_pyobject<T>::value>>
+    : process_attribute_default<handle> {
     static void init(const handle &h, type_record *r) { r->bases.append(h); }
 };
 
@@ -455,7 +554,9 @@ struct process_attribute<base<T>> : process_attribute_default<base<T>> {
 /// Process a multiple inheritance attribute
 template <>
 struct process_attribute<multiple_inheritance> : process_attribute_default<multiple_inheritance> {
-    static void init(const multiple_inheritance &, type_record *r) { r->multiple_inheritance = true; }
+    static void init(const multiple_inheritance &, type_record *r) {
+        r->multiple_inheritance = true;
+    }
 };
 
 template <>
@@ -463,6 +564,13 @@ struct process_attribute<dynamic_attr> : process_attribute_default<dynamic_attr>
     static void init(const dynamic_attr &, type_record *r) { r->dynamic_attr = true; }
 };
 
+template <>
+struct process_attribute<custom_type_setup> {
+    static void init(const custom_type_setup &value, type_record *r) {
+        r->custom_type_setup_callback = value.value;
+    }
+};
+
 template <>
 struct process_attribute<is_final> : process_attribute_default<is_final> {
     static void init(const is_final &, type_record *r) { r->is_final = true; }
@@ -494,41 +602,59 @@ template <>
 struct process_attribute<arithmetic> : process_attribute_default<arithmetic> {};
 
 template <typename... Ts>
-struct process_attribute<call_guard<Ts...>> : process_attribute_default<call_guard<Ts...>> { };
+struct process_attribute<call_guard<Ts...>> : process_attribute_default<call_guard<Ts...>> {};
 
 /**
  * Process a keep_alive call policy -- invokes keep_alive_impl during the
  * pre-call handler if both Nurse, Patient != 0 and use the post-call handler
  * otherwise
  */
-template <size_t Nurse, size_t Patient> struct process_attribute<keep_alive<Nurse, Patient>> : public process_attribute_default<keep_alive<Nurse, Patient>> {
+template <size_t Nurse, size_t Patient>
+struct process_attribute<keep_alive<Nurse, Patient>>
+    : public process_attribute_default<keep_alive<Nurse, Patient>> {
     template <size_t N = Nurse, size_t P = Patient, enable_if_t<N != 0 && P != 0, int> = 0>
-    static void precall(function_call &call) { keep_alive_impl(Nurse, Patient, call, handle()); }
+    static void precall(function_call &call) {
+        keep_alive_impl(Nurse, Patient, call, handle());
+    }
     template <size_t N = Nurse, size_t P = Patient, enable_if_t<N != 0 && P != 0, int> = 0>
-    static void postcall(function_call &, handle) { }
+    static void postcall(function_call &, handle) {}
     template <size_t N = Nurse, size_t P = Patient, enable_if_t<N == 0 || P == 0, int> = 0>
-    static void precall(function_call &) { }
+    static void precall(function_call &) {}
     template <size_t N = Nurse, size_t P = Patient, enable_if_t<N == 0 || P == 0, int> = 0>
-    static void postcall(function_call &call, handle ret) { keep_alive_impl(Nurse, Patient, call, ret); }
+    static void postcall(function_call &call, handle ret) {
+        keep_alive_impl(Nurse, Patient, call, ret);
+    }
 };
 
 /// Recursively iterate over variadic template arguments
-template <typename... Args> struct process_attributes {
-    static void init(const Args&... args, function_record *r) {
-        int unused[] = { 0, (process_attribute<typename std::decay<Args>::type>::init(args, r), 0) ... };
-        ignore_unused(unused);
+template <typename... Args>
+struct process_attributes {
+    static void init(const Args &...args, function_record *r) {
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(r);
+        PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(r);
+        using expander = int[];
+        (void) expander{
+            0, ((void) process_attribute<typename std::decay<Args>::type>::init(args, r), 0)...};
     }
-    static void init(const Args&... args, type_record *r) {
-        int unused[] = { 0, (process_attribute<typename std::decay<Args>::type>::init(args, r), 0) ... };
-        ignore_unused(unused);
+    static void init(const Args &...args, type_record *r) {
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(r);
+        PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(r);
+        using expander = int[];
+        (void) expander{0,
+                        (process_attribute<typename std::decay<Args>::type>::init(args, r), 0)...};
     }
     static void precall(function_call &call) {
-        int unused[] = { 0, (process_attribute<typename std::decay<Args>::type>::precall(call), 0) ... };
-        ignore_unused(unused);
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(call);
+        using expander = int[];
+        (void) expander{0,
+                        (process_attribute<typename std::decay<Args>::type>::precall(call), 0)...};
     }
     static void postcall(function_call &call, handle fn_ret) {
-        int unused[] = { 0, (process_attribute<typename std::decay<Args>::type>::postcall(call, fn_ret), 0) ... };
-        ignore_unused(unused);
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(call, fn_ret);
+        PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(fn_ret);
+        using expander = int[];
+        (void) expander{
+            0, (process_attribute<typename std::decay<Args>::type>::postcall(call, fn_ret), 0)...};
     }
 };
 
@@ -542,9 +668,10 @@ using extract_guard_t = typename exactly_one_t<is_call_guard, call_guard<>, Extr
 /// Check the number of named arguments at compile time
 template <typename... Extra,
           size_t named = constexpr_sum(std::is_base_of<arg, Extra>::value...),
-          size_t self  = constexpr_sum(std::is_same<is_method, Extra>::value...)>
+          size_t self = constexpr_sum(std::is_same<is_method, Extra>::value...)>
 constexpr bool expected_num_args(size_t nargs, bool has_args, bool has_kwargs) {
-    return named == 0 || (self + named + has_args + has_kwargs) == nargs;
+    PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(nargs, has_args, has_kwargs);
+    return named == 0 || (self + named + size_t(has_args) + size_t(has_kwargs)) == nargs;
 }
 
 PYBIND11_NAMESPACE_END(detail)
diff --git a/3rdparty/pybind11/include/pybind11/buffer_info.h b/3rdparty/pybind11/include/pybind11/buffer_info.h
index d803004a10..06120d5563 100644
--- a/3rdparty/pybind11/include/pybind11/buffer_info.h
+++ b/3rdparty/pybind11/include/pybind11/buffer_info.h
@@ -19,9 +19,11 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 inline std::vector<ssize_t> c_strides(const std::vector<ssize_t> &shape, ssize_t itemsize) {
     auto ndim = shape.size();
     std::vector<ssize_t> strides(ndim, itemsize);
-    if (ndim > 0)
-        for (size_t i = ndim - 1; i > 0; --i)
+    if (ndim > 0) {
+        for (size_t i = ndim - 1; i > 0; --i) {
             strides[i - 1] = strides[i] * shape[i];
+        }
+    }
     return strides;
 }
 
@@ -29,8 +31,9 @@ inline std::vector<ssize_t> c_strides(const std::vector<ssize_t> &shape, ssize_t
 inline std::vector<ssize_t> f_strides(const std::vector<ssize_t> &shape, ssize_t itemsize) {
     auto ndim = shape.size();
     std::vector<ssize_t> strides(ndim, itemsize);
-    for (size_t i = 1; i < ndim; ++i)
+    for (size_t i = 1; i < ndim; ++i) {
         strides[i] = strides[i - 1] * shape[i - 1];
+    }
     return strides;
 }
 
@@ -41,61 +44,89 @@ struct buffer_info {
     void *ptr = nullptr;          // Pointer to the underlying storage
     ssize_t itemsize = 0;         // Size of individual items in bytes
     ssize_t size = 0;             // Total number of entries
-    std::string format;           // For homogeneous buffers, this should be set to format_descriptor<T>::format()
+    std::string format;           // For homogeneous buffers, this should be set to
+                                  // format_descriptor<T>::format()
     ssize_t ndim = 0;             // Number of dimensions
     std::vector<ssize_t> shape;   // Shape of the tensor (1 entry per dimension)
-    std::vector<ssize_t> strides; // Number of bytes between adjacent entries (for each per dimension)
+    std::vector<ssize_t> strides; // Number of bytes between adjacent entries
+                                  // (for each per dimension)
     bool readonly = false;        // flag to indicate if the underlying storage may be written to
 
     buffer_info() = default;
 
-    buffer_info(void *ptr, ssize_t itemsize, const std::string &format, ssize_t ndim,
-                detail::any_container<ssize_t> shape_in, detail::any_container<ssize_t> strides_in, bool readonly=false)
-    : ptr(ptr), itemsize(itemsize), size(1), format(format), ndim(ndim),
-      shape(std::move(shape_in)), strides(std::move(strides_in)), readonly(readonly) {
-        if (ndim != (ssize_t) shape.size() || ndim != (ssize_t) strides.size())
+    buffer_info(void *ptr,
+                ssize_t itemsize,
+                const std::string &format,
+                ssize_t ndim,
+                detail::any_container<ssize_t> shape_in,
+                detail::any_container<ssize_t> strides_in,
+                bool readonly = false)
+        : ptr(ptr), itemsize(itemsize), size(1), format(format), ndim(ndim),
+          shape(std::move(shape_in)), strides(std::move(strides_in)), readonly(readonly) {
+        if (ndim != (ssize_t) shape.size() || ndim != (ssize_t) strides.size()) {
             pybind11_fail("buffer_info: ndim doesn't match shape and/or strides length");
-        for (size_t i = 0; i < (size_t) ndim; ++i)
+        }
+        for (size_t i = 0; i < (size_t) ndim; ++i) {
             size *= shape[i];
+        }
     }
 
     template <typename T>
-    buffer_info(T *ptr, detail::any_container<ssize_t> shape_in, detail::any_container<ssize_t> strides_in, bool readonly=false)
-    : buffer_info(private_ctr_tag(), ptr, sizeof(T), format_descriptor<T>::format(), static_cast<ssize_t>(shape_in->size()), std::move(shape_in), std::move(strides_in), readonly) { }
-
-    buffer_info(void *ptr, ssize_t itemsize, const std::string &format, ssize_t size, bool readonly=false)
-    : buffer_info(ptr, itemsize, format, 1, {size}, {itemsize}, readonly) { }
+    buffer_info(T *ptr,
+                detail::any_container<ssize_t> shape_in,
+                detail::any_container<ssize_t> strides_in,
+                bool readonly = false)
+        : buffer_info(private_ctr_tag(),
+                      ptr,
+                      sizeof(T),
+                      format_descriptor<T>::format(),
+                      static_cast<ssize_t>(shape_in->size()),
+                      std::move(shape_in),
+                      std::move(strides_in),
+                      readonly) {}
+
+    buffer_info(void *ptr,
+                ssize_t itemsize,
+                const std::string &format,
+                ssize_t size,
+                bool readonly = false)
+        : buffer_info(ptr, itemsize, format, 1, {size}, {itemsize}, readonly) {}
 
     template <typename T>
-    buffer_info(T *ptr, ssize_t size, bool readonly=false)
-    : buffer_info(ptr, sizeof(T), format_descriptor<T>::format(), size, readonly) { }
+    buffer_info(T *ptr, ssize_t size, bool readonly = false)
+        : buffer_info(ptr, sizeof(T), format_descriptor<T>::format(), size, readonly) {}
 
     template <typename T>
-    buffer_info(const T *ptr, ssize_t size, bool readonly=true)
-    : buffer_info(const_cast<T*>(ptr), sizeof(T), format_descriptor<T>::format(), size, readonly) { }
+    buffer_info(const T *ptr, ssize_t size, bool readonly = true)
+        : buffer_info(
+            const_cast<T *>(ptr), sizeof(T), format_descriptor<T>::format(), size, readonly) {}
 
     explicit buffer_info(Py_buffer *view, bool ownview = true)
-    : buffer_info(view->buf, view->itemsize, view->format, view->ndim,
+        : buffer_info(
+            view->buf,
+            view->itemsize,
+            view->format,
+            view->ndim,
             {view->shape, view->shape + view->ndim},
             /* Though buffer::request() requests PyBUF_STRIDES, ctypes objects
              * ignore this flag and return a view with NULL strides.
              * When strides are NULL, build them manually.  */
             view->strides
-            ? std::vector<ssize_t>(view->strides, view->strides + view->ndim)
-            : detail::c_strides({view->shape, view->shape + view->ndim}, view->itemsize),
-            view->readonly) {
+                ? std::vector<ssize_t>(view->strides, view->strides + view->ndim)
+                : detail::c_strides({view->shape, view->shape + view->ndim}, view->itemsize),
+            (view->readonly != 0)) {
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
         this->m_view = view;
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
         this->ownview = ownview;
     }
 
     buffer_info(const buffer_info &) = delete;
-    buffer_info& operator=(const buffer_info &) = delete;
+    buffer_info &operator=(const buffer_info &) = delete;
 
-    buffer_info(buffer_info &&other) {
-        (*this) = std::move(other);
-    }
+    buffer_info(buffer_info &&other) noexcept { (*this) = std::move(other); }
 
-    buffer_info& operator=(buffer_info &&rhs) {
+    buffer_info &operator=(buffer_info &&rhs) noexcept {
         ptr = rhs.ptr;
         itemsize = rhs.itemsize;
         size = rhs.size;
@@ -110,17 +141,28 @@ struct buffer_info {
     }
 
     ~buffer_info() {
-        if (m_view && ownview) { PyBuffer_Release(m_view); delete m_view; }
+        if (m_view && ownview) {
+            PyBuffer_Release(m_view);
+            delete m_view;
+        }
     }
 
     Py_buffer *view() const { return m_view; }
     Py_buffer *&view() { return m_view; }
-private:
-    struct private_ctr_tag { };
 
-    buffer_info(private_ctr_tag, void *ptr, ssize_t itemsize, const std::string &format, ssize_t ndim,
-                detail::any_container<ssize_t> &&shape_in, detail::any_container<ssize_t> &&strides_in, bool readonly)
-    : buffer_info(ptr, itemsize, format, ndim, std::move(shape_in), std::move(strides_in), readonly) { }
+private:
+    struct private_ctr_tag {};
+
+    buffer_info(private_ctr_tag,
+                void *ptr,
+                ssize_t itemsize,
+                const std::string &format,
+                ssize_t ndim,
+                detail::any_container<ssize_t> &&shape_in,
+                detail::any_container<ssize_t> &&strides_in,
+                bool readonly)
+        : buffer_info(
+            ptr, itemsize, format, ndim, std::move(shape_in), std::move(strides_in), readonly) {}
 
     Py_buffer *m_view = nullptr;
     bool ownview = false;
@@ -128,17 +170,22 @@ struct buffer_info {
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-template <typename T, typename SFINAE = void> struct compare_buffer_info {
-    static bool compare(const buffer_info& b) {
+template <typename T, typename SFINAE = void>
+struct compare_buffer_info {
+    static bool compare(const buffer_info &b) {
         return b.format == format_descriptor<T>::format() && b.itemsize == (ssize_t) sizeof(T);
     }
 };
 
-template <typename T> struct compare_buffer_info<T, detail::enable_if_t<std::is_integral<T>::value>> {
-    static bool compare(const buffer_info& b) {
-        return (size_t) b.itemsize == sizeof(T) && (b.format == format_descriptor<T>::value ||
-            ((sizeof(T) == sizeof(long)) && b.format == (std::is_unsigned<T>::value ? "L" : "l")) ||
-            ((sizeof(T) == sizeof(size_t)) && b.format == (std::is_unsigned<T>::value ? "N" : "n")));
+template <typename T>
+struct compare_buffer_info<T, detail::enable_if_t<std::is_integral<T>::value>> {
+    static bool compare(const buffer_info &b) {
+        return (size_t) b.itemsize == sizeof(T)
+               && (b.format == format_descriptor<T>::value
+                   || ((sizeof(T) == sizeof(long))
+                       && b.format == (std::is_unsigned<T>::value ? "L" : "l"))
+                   || ((sizeof(T) == sizeof(size_t))
+                       && b.format == (std::is_unsigned<T>::value ? "N" : "n")));
     }
 };
 
diff --git a/3rdparty/pybind11/include/pybind11/cast.h b/3rdparty/pybind11/include/pybind11/cast.h
index 11c61a441f..a0e32281bc 100644
--- a/3rdparty/pybind11/include/pybind11/cast.h
+++ b/3rdparty/pybind11/include/pybind11/cast.h
@@ -10,1029 +10,168 @@
 
 #pragma once
 
-#include "pytypes.h"
-#include "detail/typeid.h"
+#include "detail/common.h"
 #include "detail/descr.h"
-#include "detail/internals.h"
+#include "detail/type_caster_base.h"
+#include "detail/typeid.h"
+#include "pytypes.h"
+
 #include <array>
-#include <limits>
+#include <cstring>
+#include <functional>
+#include <iosfwd>
+#include <iterator>
+#include <memory>
+#include <string>
 #include <tuple>
 #include <type_traits>
-
-#if defined(PYBIND11_CPP17)
-#  if defined(__has_include)
-#    if __has_include(<string_view>)
-#      define PYBIND11_HAS_STRING_VIEW
-#    endif
-#  elif defined(_MSC_VER)
-#    define PYBIND11_HAS_STRING_VIEW
-#  endif
-#endif
-#ifdef PYBIND11_HAS_STRING_VIEW
-#include <string_view>
-#endif
-
-#if defined(__cpp_lib_char8_t) && __cpp_lib_char8_t >= 201811L
-#  define PYBIND11_HAS_U8STRING
-#endif
+#include <utility>
+#include <vector>
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-/// A life support system for temporary objects created by `type_caster::load()`.
-/// Adding a patient will keep it alive up until the enclosing function returns.
-class loader_life_support {
-public:
-    /// A new patient frame is created when a function is entered
-    loader_life_support() {
-        get_internals().loader_patient_stack.push_back(nullptr);
-    }
-
-    /// ... and destroyed after it returns
-    ~loader_life_support() {
-        auto &stack = get_internals().loader_patient_stack;
-        if (stack.empty())
-            pybind11_fail("loader_life_support: internal error");
-
-        auto ptr = stack.back();
-        stack.pop_back();
-        Py_CLEAR(ptr);
-
-        // A heuristic to reduce the stack's capacity (e.g. after long recursive calls)
-        if (stack.capacity() > 16 && !stack.empty() && stack.capacity() / stack.size() > 2)
-            stack.shrink_to_fit();
-    }
-
-    /// This can only be used inside a pybind11-bound function, either by `argument_loader`
-    /// at argument preparation time or by `py::cast()` at execution time.
-    PYBIND11_NOINLINE static void add_patient(handle h) {
-        auto &stack = get_internals().loader_patient_stack;
-        if (stack.empty())
-            throw cast_error("When called outside a bound function, py::cast() cannot "
-                             "do Python -> C++ conversions which require the creation "
-                             "of temporary values");
-
-        auto &list_ptr = stack.back();
-        if (list_ptr == nullptr) {
-            list_ptr = PyList_New(1);
-            if (!list_ptr)
-                pybind11_fail("loader_life_support: error allocating list");
-            PyList_SET_ITEM(list_ptr, 0, h.inc_ref().ptr());
-        } else {
-            auto result = PyList_Append(list_ptr, h.ptr());
-            if (result == -1)
-                pybind11_fail("loader_life_support: error adding patient");
-        }
-    }
-};
-
-// Gets the cache entry for the given type, creating it if necessary.  The return value is the pair
-// returned by emplace, i.e. an iterator for the entry and a bool set to `true` if the entry was
-// just created.
-inline std::pair<decltype(internals::registered_types_py)::iterator, bool> all_type_info_get_cache(PyTypeObject *type);
-
-// Populates a just-created cache entry.
-PYBIND11_NOINLINE inline void all_type_info_populate(PyTypeObject *t, std::vector<type_info *> &bases) {
-    std::vector<PyTypeObject *> check;
-    for (handle parent : reinterpret_borrow<tuple>(t->tp_bases))
-        check.push_back((PyTypeObject *) parent.ptr());
-
-    auto const &type_dict = get_internals().registered_types_py;
-    for (size_t i = 0; i < check.size(); i++) {
-        auto type = check[i];
-        // Ignore Python2 old-style class super type:
-        if (!PyType_Check((PyObject *) type)) continue;
-
-        // Check `type` in the current set of registered python types:
-        auto it = type_dict.find(type);
-        if (it != type_dict.end()) {
-            // We found a cache entry for it, so it's either pybind-registered or has pre-computed
-            // pybind bases, but we have to make sure we haven't already seen the type(s) before: we
-            // want to follow Python/virtual C++ rules that there should only be one instance of a
-            // common base.
-            for (auto *tinfo : it->second) {
-                // NB: Could use a second set here, rather than doing a linear search, but since
-                // having a large number of immediate pybind11-registered types seems fairly
-                // unlikely, that probably isn't worthwhile.
-                bool found = false;
-                for (auto *known : bases) {
-                    if (known == tinfo) { found = true; break; }
-                }
-                if (!found) bases.push_back(tinfo);
-            }
-        }
-        else if (type->tp_bases) {
-            // It's some python type, so keep follow its bases classes to look for one or more
-            // registered types
-            if (i + 1 == check.size()) {
-                // When we're at the end, we can pop off the current element to avoid growing
-                // `check` when adding just one base (which is typical--i.e. when there is no
-                // multiple inheritance)
-                check.pop_back();
-                i--;
-            }
-            for (handle parent : reinterpret_borrow<tuple>(type->tp_bases))
-                check.push_back((PyTypeObject *) parent.ptr());
-        }
-    }
-}
-
-/**
- * Extracts vector of type_info pointers of pybind-registered roots of the given Python type.  Will
- * be just 1 pybind type for the Python type of a pybind-registered class, or for any Python-side
- * derived class that uses single inheritance.  Will contain as many types as required for a Python
- * class that uses multiple inheritance to inherit (directly or indirectly) from multiple
- * pybind-registered classes.  Will be empty if neither the type nor any base classes are
- * pybind-registered.
- *
- * The value is cached for the lifetime of the Python type.
- */
-inline const std::vector<detail::type_info *> &all_type_info(PyTypeObject *type) {
-    auto ins = all_type_info_get_cache(type);
-    if (ins.second)
-        // New cache entry: populate it
-        all_type_info_populate(type, ins.first->second);
-
-    return ins.first->second;
-}
-
-/**
- * Gets a single pybind11 type info for a python type.  Returns nullptr if neither the type nor any
- * ancestors are pybind11-registered.  Throws an exception if there are multiple bases--use
- * `all_type_info` instead if you want to support multiple bases.
- */
-PYBIND11_NOINLINE inline detail::type_info* get_type_info(PyTypeObject *type) {
-    auto &bases = all_type_info(type);
-    if (bases.empty())
-        return nullptr;
-    if (bases.size() > 1)
-        pybind11_fail("pybind11::detail::get_type_info: type has multiple pybind11-registered bases");
-    return bases.front();
-}
-
-inline detail::type_info *get_local_type_info(const std::type_index &tp) {
-    auto &locals = registered_local_types_cpp();
-    auto it = locals.find(tp);
-    if (it != locals.end())
-        return it->second;
-    return nullptr;
-}
-
-inline detail::type_info *get_global_type_info(const std::type_index &tp) {
-    auto &types = get_internals().registered_types_cpp;
-    auto it = types.find(tp);
-    if (it != types.end())
-        return it->second;
-    return nullptr;
-}
-
-/// Return the type info for a given C++ type; on lookup failure can either throw or return nullptr.
-PYBIND11_NOINLINE inline detail::type_info *get_type_info(const std::type_index &tp,
-                                                          bool throw_if_missing = false) {
-    if (auto ltype = get_local_type_info(tp))
-        return ltype;
-    if (auto gtype = get_global_type_info(tp))
-        return gtype;
-
-    if (throw_if_missing) {
-        std::string tname = tp.name();
-        detail::clean_type_id(tname);
-        pybind11_fail("pybind11::detail::get_type_info: unable to find type info for \"" + tname + "\"");
-    }
-    return nullptr;
-}
-
-PYBIND11_NOINLINE inline handle get_type_handle(const std::type_info &tp, bool throw_if_missing) {
-    detail::type_info *type_info = get_type_info(tp, throw_if_missing);
-    return handle(type_info ? ((PyObject *) type_info->type) : nullptr);
-}
-
-struct value_and_holder {
-    instance *inst = nullptr;
-    size_t index = 0u;
-    const detail::type_info *type = nullptr;
-    void **vh = nullptr;
-
-    // Main constructor for a found value/holder:
-    value_and_holder(instance *i, const detail::type_info *type, size_t vpos, size_t index) :
-        inst{i}, index{index}, type{type},
-        vh{inst->simple_layout ? inst->simple_value_holder : &inst->nonsimple.values_and_holders[vpos]}
-    {}
-
-    // Default constructor (used to signal a value-and-holder not found by get_value_and_holder())
-    value_and_holder() = default;
-
-    // Used for past-the-end iterator
-    value_and_holder(size_t index) : index{index} {}
-
-    template <typename V = void> V *&value_ptr() const {
-        return reinterpret_cast<V *&>(vh[0]);
-    }
-    // True if this `value_and_holder` has a non-null value pointer
-    explicit operator bool() const { return value_ptr(); }
-
-    template <typename H> H &holder() const {
-        return reinterpret_cast<H &>(vh[1]);
-    }
-    bool holder_constructed() const {
-        return inst->simple_layout
-            ? inst->simple_holder_constructed
-            : inst->nonsimple.status[index] & instance::status_holder_constructed;
-    }
-    void set_holder_constructed(bool v = true) {
-        if (inst->simple_layout)
-            inst->simple_holder_constructed = v;
-        else if (v)
-            inst->nonsimple.status[index] |= instance::status_holder_constructed;
-        else
-            inst->nonsimple.status[index] &= (uint8_t) ~instance::status_holder_constructed;
-    }
-    bool instance_registered() const {
-        return inst->simple_layout
-            ? inst->simple_instance_registered
-            : inst->nonsimple.status[index] & instance::status_instance_registered;
-    }
-    void set_instance_registered(bool v = true) {
-        if (inst->simple_layout)
-            inst->simple_instance_registered = v;
-        else if (v)
-            inst->nonsimple.status[index] |= instance::status_instance_registered;
-        else
-            inst->nonsimple.status[index] &= (uint8_t) ~instance::status_instance_registered;
-    }
-};
-
-// Container for accessing and iterating over an instance's values/holders
-struct values_and_holders {
-private:
-    instance *inst;
-    using type_vec = std::vector<detail::type_info *>;
-    const type_vec &tinfo;
-
-public:
-    values_and_holders(instance *inst) : inst{inst}, tinfo(all_type_info(Py_TYPE(inst))) {}
-
-    struct iterator {
-    private:
-        instance *inst = nullptr;
-        const type_vec *types = nullptr;
-        value_and_holder curr;
-        friend struct values_and_holders;
-        iterator(instance *inst, const type_vec *tinfo)
-            : inst{inst}, types{tinfo},
-            curr(inst /* instance */,
-                 types->empty() ? nullptr : (*types)[0] /* type info */,
-                 0, /* vpos: (non-simple types only): the first vptr comes first */
-                 0 /* index */)
-        {}
-        // Past-the-end iterator:
-        iterator(size_t end) : curr(end) {}
-    public:
-        bool operator==(const iterator &other) const { return curr.index == other.curr.index; }
-        bool operator!=(const iterator &other) const { return curr.index != other.curr.index; }
-        iterator &operator++() {
-            if (!inst->simple_layout)
-                curr.vh += 1 + (*types)[curr.index]->holder_size_in_ptrs;
-            ++curr.index;
-            curr.type = curr.index < types->size() ? (*types)[curr.index] : nullptr;
-            return *this;
-        }
-        value_and_holder &operator*() { return curr; }
-        value_and_holder *operator->() { return &curr; }
-    };
-
-    iterator begin() { return iterator(inst, &tinfo); }
-    iterator end() { return iterator(tinfo.size()); }
-
-    iterator find(const type_info *find_type) {
-        auto it = begin(), endit = end();
-        while (it != endit && it->type != find_type) ++it;
-        return it;
-    }
-
-    size_t size() { return tinfo.size(); }
-};
-
-/**
- * Extracts C++ value and holder pointer references from an instance (which may contain multiple
- * values/holders for python-side multiple inheritance) that match the given type.  Throws an error
- * if the given type (or ValueType, if omitted) is not a pybind11 base of the given instance.  If
- * `find_type` is omitted (or explicitly specified as nullptr) the first value/holder are returned,
- * regardless of type (and the resulting .type will be nullptr).
- *
- * The returned object should be short-lived: in particular, it must not outlive the called-upon
- * instance.
- */
-PYBIND11_NOINLINE inline value_and_holder instance::get_value_and_holder(const type_info *find_type /*= nullptr default in common.h*/, bool throw_if_missing /*= true in common.h*/) {
-    // Optimize common case:
-    if (!find_type || Py_TYPE(this) == find_type->type)
-        return value_and_holder(this, find_type, 0, 0);
-
-    detail::values_and_holders vhs(this);
-    auto it = vhs.find(find_type);
-    if (it != vhs.end())
-        return *it;
-
-    if (!throw_if_missing)
-        return value_and_holder();
-
-#if defined(NDEBUG)
-    pybind11_fail("pybind11::detail::instance::get_value_and_holder: "
-            "type is not a pybind11 base of the given instance "
-            "(compile in debug mode for type details)");
-#else
-    pybind11_fail("pybind11::detail::instance::get_value_and_holder: `" +
-            get_fully_qualified_tp_name(find_type->type) + "' is not a pybind11 base of the given `" +
-            get_fully_qualified_tp_name(Py_TYPE(this)) + "' instance");
-#endif
-}
-
-PYBIND11_NOINLINE inline void instance::allocate_layout() {
-    auto &tinfo = all_type_info(Py_TYPE(this));
-
-    const size_t n_types = tinfo.size();
-
-    if (n_types == 0)
-        pybind11_fail("instance allocation failed: new instance has no pybind11-registered base types");
-
-    simple_layout =
-        n_types == 1 && tinfo.front()->holder_size_in_ptrs <= instance_simple_holder_in_ptrs();
-
-    // Simple path: no python-side multiple inheritance, and a small-enough holder
-    if (simple_layout) {
-        simple_value_holder[0] = nullptr;
-        simple_holder_constructed = false;
-        simple_instance_registered = false;
-    }
-    else { // multiple base types or a too-large holder
-        // Allocate space to hold: [v1*][h1][v2*][h2]...[bb...] where [vN*] is a value pointer,
-        // [hN] is the (uninitialized) holder instance for value N, and [bb...] is a set of bool
-        // values that tracks whether each associated holder has been initialized.  Each [block] is
-        // padded, if necessary, to an integer multiple of sizeof(void *).
-        size_t space = 0;
-        for (auto t : tinfo) {
-            space += 1; // value pointer
-            space += t->holder_size_in_ptrs; // holder instance
-        }
-        size_t flags_at = space;
-        space += size_in_ptrs(n_types); // status bytes (holder_constructed and instance_registered)
-
-        // Allocate space for flags, values, and holders, and initialize it to 0 (flags and values,
-        // in particular, need to be 0).  Use Python's memory allocation functions: in Python 3.6
-        // they default to using pymalloc, which is designed to be efficient for small allocations
-        // like the one we're doing here; in earlier versions (and for larger allocations) they are
-        // just wrappers around malloc.
-#if PY_VERSION_HEX >= 0x03050000
-        nonsimple.values_and_holders = (void **) PyMem_Calloc(space, sizeof(void *));
-        if (!nonsimple.values_and_holders) throw std::bad_alloc();
-#else
-        nonsimple.values_and_holders = (void **) PyMem_New(void *, space);
-        if (!nonsimple.values_and_holders) throw std::bad_alloc();
-        std::memset(nonsimple.values_and_holders, 0, space * sizeof(void *));
-#endif
-        nonsimple.status = reinterpret_cast<uint8_t *>(&nonsimple.values_and_holders[flags_at]);
-    }
-    owned = true;
-}
-
-PYBIND11_NOINLINE inline void instance::deallocate_layout() {
-    if (!simple_layout)
-        PyMem_Free(nonsimple.values_and_holders);
-}
-
-PYBIND11_NOINLINE inline bool isinstance_generic(handle obj, const std::type_info &tp) {
-    handle type = detail::get_type_handle(tp, false);
-    if (!type)
-        return false;
-    return isinstance(obj, type);
-}
-
-PYBIND11_NOINLINE inline std::string error_string() {
-    if (!PyErr_Occurred()) {
-        PyErr_SetString(PyExc_RuntimeError, "Unknown internal error occurred");
-        return "Unknown internal error occurred";
-    }
-
-    error_scope scope; // Preserve error state
-
-    std::string errorString;
-    if (scope.type) {
-        errorString += handle(scope.type).attr("__name__").cast<std::string>();
-        errorString += ": ";
-    }
-    if (scope.value)
-        errorString += (std::string) str(scope.value);
-
-    PyErr_NormalizeException(&scope.type, &scope.value, &scope.trace);
-
-#if PY_MAJOR_VERSION >= 3
-    if (scope.trace != nullptr)
-        PyException_SetTraceback(scope.value, scope.trace);
-#endif
-
-#if !defined(PYPY_VERSION)
-    if (scope.trace) {
-        auto *trace = (PyTracebackObject *) scope.trace;
-
-        /* Get the deepest trace possible */
-        while (trace->tb_next)
-            trace = trace->tb_next;
-
-        PyFrameObject *frame = trace->tb_frame;
-        errorString += "\n\nAt:\n";
-        while (frame) {
-            int lineno = PyFrame_GetLineNumber(frame);
-            errorString +=
-                "  " + handle(frame->f_code->co_filename).cast<std::string>() +
-                "(" + std::to_string(lineno) + "): " +
-                handle(frame->f_code->co_name).cast<std::string>() + "\n";
-            frame = frame->f_back;
-        }
-    }
-#endif
-
-    return errorString;
-}
-
-PYBIND11_NOINLINE inline handle get_object_handle(const void *ptr, const detail::type_info *type ) {
-    auto &instances = get_internals().registered_instances;
-    auto range = instances.equal_range(ptr);
-    for (auto it = range.first; it != range.second; ++it) {
-        for (const auto &vh : values_and_holders(it->second)) {
-            if (vh.type == type)
-                return handle((PyObject *) it->second);
-        }
-    }
-    return handle();
-}
-
-inline PyThreadState *get_thread_state_unchecked() {
-#if defined(PYPY_VERSION)
-    return PyThreadState_GET();
-#elif PY_VERSION_HEX < 0x03000000
-    return _PyThreadState_Current;
-#elif PY_VERSION_HEX < 0x03050000
-    return (PyThreadState*) _Py_atomic_load_relaxed(&_PyThreadState_Current);
-#elif PY_VERSION_HEX < 0x03050200
-    return (PyThreadState*) _PyThreadState_Current.value;
-#else
-    return _PyThreadState_UncheckedGet();
-#endif
-}
-
-// Forward declarations
-inline void keep_alive_impl(handle nurse, handle patient);
-inline PyObject *make_new_instance(PyTypeObject *type);
-
-class type_caster_generic {
-public:
-    PYBIND11_NOINLINE type_caster_generic(const std::type_info &type_info)
-        : typeinfo(get_type_info(type_info)), cpptype(&type_info) { }
-
-    type_caster_generic(const type_info *typeinfo)
-        : typeinfo(typeinfo), cpptype(typeinfo ? typeinfo->cpptype : nullptr) { }
-
-    bool load(handle src, bool convert) {
-        return load_impl<type_caster_generic>(src, convert);
-    }
-
-    PYBIND11_NOINLINE static handle cast(const void *_src, return_value_policy policy, handle parent,
-                                         const detail::type_info *tinfo,
-                                         void *(*copy_constructor)(const void *),
-                                         void *(*move_constructor)(const void *),
-                                         const void *existing_holder = nullptr) {
-        if (!tinfo) // no type info: error will be set already
-            return handle();
-
-        void *src = const_cast<void *>(_src);
-        if (src == nullptr)
-            return none().release();
-
-        auto it_instances = get_internals().registered_instances.equal_range(src);
-        for (auto it_i = it_instances.first; it_i != it_instances.second; ++it_i) {
-            for (auto instance_type : detail::all_type_info(Py_TYPE(it_i->second))) {
-                if (instance_type && same_type(*instance_type->cpptype, *tinfo->cpptype))
-                    return handle((PyObject *) it_i->second).inc_ref();
-            }
-        }
-
-        auto inst = reinterpret_steal<object>(make_new_instance(tinfo->type));
-        auto wrapper = reinterpret_cast<instance *>(inst.ptr());
-        wrapper->owned = false;
-        void *&valueptr = values_and_holders(wrapper).begin()->value_ptr();
-
-        switch (policy) {
-            case return_value_policy::automatic:
-            case return_value_policy::take_ownership:
-                valueptr = src;
-                wrapper->owned = true;
-                break;
-
-            case return_value_policy::automatic_reference:
-            case return_value_policy::reference:
-                valueptr = src;
-                wrapper->owned = false;
-                break;
-
-            case return_value_policy::copy:
-                if (copy_constructor)
-                    valueptr = copy_constructor(src);
-                else {
-#if defined(NDEBUG)
-                    throw cast_error("return_value_policy = copy, but type is "
-                                     "non-copyable! (compile in debug mode for details)");
-#else
-                    std::string type_name(tinfo->cpptype->name());
-                    detail::clean_type_id(type_name);
-                    throw cast_error("return_value_policy = copy, but type " +
-                                     type_name + " is non-copyable!");
-#endif
-                }
-                wrapper->owned = true;
-                break;
-
-            case return_value_policy::move:
-                if (move_constructor)
-                    valueptr = move_constructor(src);
-                else if (copy_constructor)
-                    valueptr = copy_constructor(src);
-                else {
-#if defined(NDEBUG)
-                    throw cast_error("return_value_policy = move, but type is neither "
-                                     "movable nor copyable! "
-                                     "(compile in debug mode for details)");
-#else
-                    std::string type_name(tinfo->cpptype->name());
-                    detail::clean_type_id(type_name);
-                    throw cast_error("return_value_policy = move, but type " +
-                                     type_name + " is neither movable nor copyable!");
-#endif
-                }
-                wrapper->owned = true;
-                break;
-
-            case return_value_policy::reference_internal:
-                valueptr = src;
-                wrapper->owned = false;
-                keep_alive_impl(inst, parent);
-                break;
-
-            default:
-                throw cast_error("unhandled return_value_policy: should not happen!");
-        }
-
-        tinfo->init_instance(wrapper, existing_holder);
-
-        return inst.release();
-    }
-
-    // Base methods for generic caster; there are overridden in copyable_holder_caster
-    void load_value(value_and_holder &&v_h) {
-        auto *&vptr = v_h.value_ptr();
-        // Lazy allocation for unallocated values:
-        if (vptr == nullptr) {
-            auto *type = v_h.type ? v_h.type : typeinfo;
-            if (type->operator_new) {
-                vptr = type->operator_new(type->type_size);
-            } else {
-                #if defined(__cpp_aligned_new) && (!defined(_MSC_VER) || _MSC_VER >= 1912)
-                    if (type->type_align > __STDCPP_DEFAULT_NEW_ALIGNMENT__)
-                        vptr = ::operator new(type->type_size,
-                                              std::align_val_t(type->type_align));
-                    else
-                #endif
-                vptr = ::operator new(type->type_size);
-            }
-        }
-        value = vptr;
-    }
-    bool try_implicit_casts(handle src, bool convert) {
-        for (auto &cast : typeinfo->implicit_casts) {
-            type_caster_generic sub_caster(*cast.first);
-            if (sub_caster.load(src, convert)) {
-                value = cast.second(sub_caster.value);
-                return true;
-            }
-        }
-        return false;
-    }
-    bool try_direct_conversions(handle src) {
-        for (auto &converter : *typeinfo->direct_conversions) {
-            if (converter(src.ptr(), value))
-                return true;
-        }
-        return false;
-    }
-    void check_holder_compat() {}
-
-    PYBIND11_NOINLINE static void *local_load(PyObject *src, const type_info *ti) {
-        auto caster = type_caster_generic(ti);
-        if (caster.load(src, false))
-            return caster.value;
-        return nullptr;
-    }
-
-    /// Try to load with foreign typeinfo, if available. Used when there is no
-    /// native typeinfo, or when the native one wasn't able to produce a value.
-    PYBIND11_NOINLINE bool try_load_foreign_module_local(handle src) {
-        constexpr auto *local_key = PYBIND11_MODULE_LOCAL_ID;
-        const auto pytype = type::handle_of(src);
-        if (!hasattr(pytype, local_key))
-            return false;
-
-        type_info *foreign_typeinfo = reinterpret_borrow<capsule>(getattr(pytype, local_key));
-        // Only consider this foreign loader if actually foreign and is a loader of the correct cpp type
-        if (foreign_typeinfo->module_local_load == &local_load
-            || (cpptype && !same_type(*cpptype, *foreign_typeinfo->cpptype)))
-            return false;
-
-        if (auto result = foreign_typeinfo->module_local_load(src.ptr(), foreign_typeinfo)) {
-            value = result;
-            return true;
-        }
-        return false;
-    }
-
-    // Implementation of `load`; this takes the type of `this` so that it can dispatch the relevant
-    // bits of code between here and copyable_holder_caster where the two classes need different
-    // logic (without having to resort to virtual inheritance).
-    template <typename ThisT>
-    PYBIND11_NOINLINE bool load_impl(handle src, bool convert) {
-        if (!src) return false;
-        if (!typeinfo) return try_load_foreign_module_local(src);
-        if (src.is_none()) {
-            // Defer accepting None to other overloads (if we aren't in convert mode):
-            if (!convert) return false;
-            value = nullptr;
-            return true;
-        }
-
-        auto &this_ = static_cast<ThisT &>(*this);
-        this_.check_holder_compat();
-
-        PyTypeObject *srctype = Py_TYPE(src.ptr());
-
-        // Case 1: If src is an exact type match for the target type then we can reinterpret_cast
-        // the instance's value pointer to the target type:
-        if (srctype == typeinfo->type) {
-            this_.load_value(reinterpret_cast<instance *>(src.ptr())->get_value_and_holder());
-            return true;
-        }
-        // Case 2: We have a derived class
-        else if (PyType_IsSubtype(srctype, typeinfo->type)) {
-            auto &bases = all_type_info(srctype);
-            bool no_cpp_mi = typeinfo->simple_type;
-
-            // Case 2a: the python type is a Python-inherited derived class that inherits from just
-            // one simple (no MI) pybind11 class, or is an exact match, so the C++ instance is of
-            // the right type and we can use reinterpret_cast.
-            // (This is essentially the same as case 2b, but because not using multiple inheritance
-            // is extremely common, we handle it specially to avoid the loop iterator and type
-            // pointer lookup overhead)
-            if (bases.size() == 1 && (no_cpp_mi || bases.front()->type == typeinfo->type)) {
-                this_.load_value(reinterpret_cast<instance *>(src.ptr())->get_value_and_holder());
-                return true;
-            }
-            // Case 2b: the python type inherits from multiple C++ bases.  Check the bases to see if
-            // we can find an exact match (or, for a simple C++ type, an inherited match); if so, we
-            // can safely reinterpret_cast to the relevant pointer.
-            else if (bases.size() > 1) {
-                for (auto base : bases) {
-                    if (no_cpp_mi ? PyType_IsSubtype(base->type, typeinfo->type) : base->type == typeinfo->type) {
-                        this_.load_value(reinterpret_cast<instance *>(src.ptr())->get_value_and_holder(base));
-                        return true;
-                    }
-                }
-            }
-
-            // Case 2c: C++ multiple inheritance is involved and we couldn't find an exact type match
-            // in the registered bases, above, so try implicit casting (needed for proper C++ casting
-            // when MI is involved).
-            if (this_.try_implicit_casts(src, convert))
-                return true;
-        }
-
-        // Perform an implicit conversion
-        if (convert) {
-            for (auto &converter : typeinfo->implicit_conversions) {
-                auto temp = reinterpret_steal<object>(converter(src.ptr(), typeinfo->type));
-                if (load_impl<ThisT>(temp, false)) {
-                    loader_life_support::add_patient(temp);
-                    return true;
-                }
-            }
-            if (this_.try_direct_conversions(src))
-                return true;
-        }
-
-        // Failed to match local typeinfo. Try again with global.
-        if (typeinfo->module_local) {
-            if (auto gtype = get_global_type_info(*typeinfo->cpptype)) {
-                typeinfo = gtype;
-                return load(src, false);
-            }
-        }
-
-        // Global typeinfo has precedence over foreign module_local
-        return try_load_foreign_module_local(src);
-    }
-
-
-    // Called to do type lookup and wrap the pointer and type in a pair when a dynamic_cast
-    // isn't needed or can't be used.  If the type is unknown, sets the error and returns a pair
-    // with .second = nullptr.  (p.first = nullptr is not an error: it becomes None).
-    PYBIND11_NOINLINE static std::pair<const void *, const type_info *> src_and_type(
-            const void *src, const std::type_info &cast_type, const std::type_info *rtti_type = nullptr) {
-        if (auto *tpi = get_type_info(cast_type))
-            return {src, const_cast<const type_info *>(tpi)};
-
-        // Not found, set error:
-        std::string tname = rtti_type ? rtti_type->name() : cast_type.name();
-        detail::clean_type_id(tname);
-        std::string msg = "Unregistered type : " + tname;
-        PyErr_SetString(PyExc_TypeError, msg.c_str());
-        return {nullptr, nullptr};
-    }
-
-    const type_info *typeinfo = nullptr;
-    const std::type_info *cpptype = nullptr;
-    void *value = nullptr;
-};
-
-/**
- * Determine suitable casting operator for pointer-or-lvalue-casting type casters.  The type caster
- * needs to provide `operator T*()` and `operator T&()` operators.
- *
- * If the type supports moving the value away via an `operator T&&() &&` method, it should use
- * `movable_cast_op_type` instead.
- */
-template <typename T>
-using cast_op_type =
-    conditional_t<std::is_pointer<remove_reference_t<T>>::value,
-        typename std::add_pointer<intrinsic_t<T>>::type,
-        typename std::add_lvalue_reference<intrinsic_t<T>>::type>;
-
-/**
- * Determine suitable casting operator for a type caster with a movable value.  Such a type caster
- * needs to provide `operator T*()`, `operator T&()`, and `operator T&&() &&`.  The latter will be
- * called in appropriate contexts where the value can be moved rather than copied.
- *
- * These operator are automatically provided when using the PYBIND11_TYPE_CASTER macro.
- */
-template <typename T>
-using movable_cast_op_type =
-    conditional_t<std::is_pointer<typename std::remove_reference<T>::type>::value,
-        typename std::add_pointer<intrinsic_t<T>>::type,
-    conditional_t<std::is_rvalue_reference<T>::value,
-        typename std::add_rvalue_reference<intrinsic_t<T>>::type,
-        typename std::add_lvalue_reference<intrinsic_t<T>>::type>>;
-
-// std::is_copy_constructible isn't quite enough: it lets std::vector<T> (and similar) through when
-// T is non-copyable, but code containing such a copy constructor fails to actually compile.
-template <typename T, typename SFINAE = void> struct is_copy_constructible : std::is_copy_constructible<T> {};
-
-// Specialization for types that appear to be copy constructible but also look like stl containers
-// (we specifically check for: has `value_type` and `reference` with `reference = value_type&`): if
-// so, copy constructability depends on whether the value_type is copy constructible.
-template <typename Container> struct is_copy_constructible<Container, enable_if_t<all_of<
-        std::is_copy_constructible<Container>,
-        std::is_same<typename Container::value_type &, typename Container::reference>,
-        // Avoid infinite recursion
-        negation<std::is_same<Container, typename Container::value_type>>
-    >::value>> : is_copy_constructible<typename Container::value_type> {};
-
-// Likewise for std::pair
-// (after C++17 it is mandatory that the copy constructor not exist when the two types aren't themselves
-// copy constructible, but this can not be relied upon when T1 or T2 are themselves containers).
-template <typename T1, typename T2> struct is_copy_constructible<std::pair<T1, T2>>
-    : all_of<is_copy_constructible<T1>, is_copy_constructible<T2>> {};
-
-// The same problems arise with std::is_copy_assignable, so we use the same workaround.
-template <typename T, typename SFINAE = void> struct is_copy_assignable : std::is_copy_assignable<T> {};
-template <typename Container> struct is_copy_assignable<Container, enable_if_t<all_of<
-        std::is_copy_assignable<Container>,
-        std::is_same<typename Container::value_type &, typename Container::reference>
-    >::value>> : is_copy_assignable<typename Container::value_type> {};
-template <typename T1, typename T2> struct is_copy_assignable<std::pair<T1, T2>>
-    : all_of<is_copy_assignable<T1>, is_copy_assignable<T2>> {};
-
-PYBIND11_NAMESPACE_END(detail)
-
-// polymorphic_type_hook<itype>::get(src, tinfo) determines whether the object pointed
-// to by `src` actually is an instance of some class derived from `itype`.
-// If so, it sets `tinfo` to point to the std::type_info representing that derived
-// type, and returns a pointer to the start of the most-derived object of that type
-// (in which `src` is a subobject; this will be the same address as `src` in most
-// single inheritance cases). If not, or if `src` is nullptr, it simply returns `src`
-// and leaves `tinfo` at its default value of nullptr.
-//
-// The default polymorphic_type_hook just returns src. A specialization for polymorphic
-// types determines the runtime type of the passed object and adjusts the this-pointer
-// appropriately via dynamic_cast<void*>. This is what enables a C++ Animal* to appear
-// to Python as a Dog (if Dog inherits from Animal, Animal is polymorphic, Dog is
-// registered with pybind11, and this Animal is in fact a Dog).
-//
-// You may specialize polymorphic_type_hook yourself for types that want to appear
-// polymorphic to Python but do not use C++ RTTI. (This is a not uncommon pattern
-// in performance-sensitive applications, used most notably in LLVM.)
-//
-// polymorphic_type_hook_base allows users to specialize polymorphic_type_hook with
-// std::enable_if. User provided specializations will always have higher priority than
-// the default implementation and specialization provided in polymorphic_type_hook_base.
-template <typename itype, typename SFINAE = void>
-struct polymorphic_type_hook_base
-{
-    static const void *get(const itype *src, const std::type_info*&) { return src; }
-};
-template <typename itype>
-struct polymorphic_type_hook_base<itype, detail::enable_if_t<std::is_polymorphic<itype>::value>>
-{
-    static const void *get(const itype *src, const std::type_info*& type) {
-        type = src ? &typeid(*src) : nullptr;
-        return dynamic_cast<const void*>(src);
-    }
-};
-template <typename itype, typename SFINAE = void>
-struct polymorphic_type_hook : public polymorphic_type_hook_base<itype> {};
-
-PYBIND11_NAMESPACE_BEGIN(detail)
-
-/// Generic type caster for objects stored on the heap
-template <typename type> class type_caster_base : public type_caster_generic {
-    using itype = intrinsic_t<type>;
-
-public:
-    static constexpr auto name = _<type>();
-
-    type_caster_base() : type_caster_base(typeid(type)) { }
-    explicit type_caster_base(const std::type_info &info) : type_caster_generic(info) { }
-
-    static handle cast(const itype &src, return_value_policy policy, handle parent) {
-        if (policy == return_value_policy::automatic || policy == return_value_policy::automatic_reference)
-            policy = return_value_policy::copy;
-        return cast(&src, policy, parent);
-    }
-
-    static handle cast(itype &&src, return_value_policy, handle parent) {
-        return cast(&src, return_value_policy::move, parent);
-    }
-
-    // Returns a (pointer, type_info) pair taking care of necessary type lookup for a
-    // polymorphic type (using RTTI by default, but can be overridden by specializing
-    // polymorphic_type_hook). If the instance isn't derived, returns the base version.
-    static std::pair<const void *, const type_info *> src_and_type(const itype *src) {
-        auto &cast_type = typeid(itype);
-        const std::type_info *instance_type = nullptr;
-        const void *vsrc = polymorphic_type_hook<itype>::get(src, instance_type);
-        if (instance_type && !same_type(cast_type, *instance_type)) {
-            // This is a base pointer to a derived type. If the derived type is registered
-            // with pybind11, we want to make the full derived object available.
-            // In the typical case where itype is polymorphic, we get the correct
-            // derived pointer (which may be != base pointer) by a dynamic_cast to
-            // most derived type. If itype is not polymorphic, we won't get here
-            // except via a user-provided specialization of polymorphic_type_hook,
-            // and the user has promised that no this-pointer adjustment is
-            // required in that case, so it's OK to use static_cast.
-            if (const auto *tpi = get_type_info(*instance_type))
-                return {vsrc, tpi};
-        }
-        // Otherwise we have either a nullptr, an `itype` pointer, or an unknown derived pointer, so
-        // don't do a cast
-        return type_caster_generic::src_and_type(src, cast_type, instance_type);
-    }
-
-    static handle cast(const itype *src, return_value_policy policy, handle parent) {
-        auto st = src_and_type(src);
-        return type_caster_generic::cast(
-            st.first, policy, parent, st.second,
-            make_copy_constructor(src), make_move_constructor(src));
-    }
-
-    static handle cast_holder(const itype *src, const void *holder) {
-        auto st = src_and_type(src);
-        return type_caster_generic::cast(
-            st.first, return_value_policy::take_ownership, {}, st.second,
-            nullptr, nullptr, holder);
-    }
-
-    template <typename T> using cast_op_type = detail::cast_op_type<T>;
-
-    operator itype*() { return (type *) value; }
-    operator itype&() { if (!value) throw reference_cast_error(); return *((itype *) value); }
-
-protected:
-    using Constructor = void *(*)(const void *);
-
-    /* Only enabled when the types are {copy,move}-constructible *and* when the type
-       does not have a private operator new implementation. */
-    template <typename T, typename = enable_if_t<is_copy_constructible<T>::value>>
-    static auto make_copy_constructor(const T *x) -> decltype(new T(*x), Constructor{}) {
-        return [](const void *arg) -> void * {
-            return new T(*reinterpret_cast<const T *>(arg));
-        };
-    }
-
-    template <typename T, typename = enable_if_t<std::is_move_constructible<T>::value>>
-    static auto make_move_constructor(const T *x) -> decltype(new T(std::move(*const_cast<T *>(x))), Constructor{}) {
-        return [](const void *arg) -> void * {
-            return new T(std::move(*const_cast<T *>(reinterpret_cast<const T *>(arg))));
-        };
-    }
-
-    static Constructor make_copy_constructor(...) { return nullptr; }
-    static Constructor make_move_constructor(...) { return nullptr; }
-};
-
-template <typename type, typename SFINAE = void> class type_caster : public type_caster_base<type> { };
-template <typename type> using make_caster = type_caster<intrinsic_t<type>>;
+template <typename type, typename SFINAE = void>
+class type_caster : public type_caster_base<type> {};
+template <typename type>
+using make_caster = type_caster<intrinsic_t<type>>;
 
 // Shortcut for calling a caster's `cast_op_type` cast operator for casting a type_caster to a T
-template <typename T> typename make_caster<T>::template cast_op_type<T> cast_op(make_caster<T> &caster) {
+template <typename T>
+typename make_caster<T>::template cast_op_type<T> cast_op(make_caster<T> &caster) {
     return caster.operator typename make_caster<T>::template cast_op_type<T>();
 }
-template <typename T> typename make_caster<T>::template cast_op_type<typename std::add_rvalue_reference<T>::type>
+template <typename T>
+typename make_caster<T>::template cast_op_type<typename std::add_rvalue_reference<T>::type>
 cast_op(make_caster<T> &&caster) {
-    return std::move(caster).operator
-        typename make_caster<T>::template cast_op_type<typename std::add_rvalue_reference<T>::type>();
+    return std::move(caster).operator typename make_caster<T>::
+        template cast_op_type<typename std::add_rvalue_reference<T>::type>();
 }
 
-template <typename type> class type_caster<std::reference_wrapper<type>> {
+template <typename type>
+class type_caster<std::reference_wrapper<type>> {
 private:
     using caster_t = make_caster<type>;
     caster_t subcaster;
-    using subcaster_cast_op_type = typename caster_t::template cast_op_type<type>;
-    static_assert(std::is_same<typename std::remove_const<type>::type &, subcaster_cast_op_type>::value,
-            "std::reference_wrapper<T> caster requires T to have a caster with an `T &` operator");
+    using reference_t = type &;
+    using subcaster_cast_op_type = typename caster_t::template cast_op_type<reference_t>;
+
+    static_assert(
+        std::is_same<typename std::remove_const<type>::type &, subcaster_cast_op_type>::value
+            || std::is_same<reference_t, subcaster_cast_op_type>::value,
+        "std::reference_wrapper<T> caster requires T to have a caster with an "
+        "`operator T &()` or `operator const T &()`");
+
 public:
     bool load(handle src, bool convert) { return subcaster.load(src, convert); }
     static constexpr auto name = caster_t::name;
-    static handle cast(const std::reference_wrapper<type> &src, return_value_policy policy, handle parent) {
+    static handle
+    cast(const std::reference_wrapper<type> &src, return_value_policy policy, handle parent) {
         // It is definitely wrong to take ownership of this pointer, so mask that rvp
-        if (policy == return_value_policy::take_ownership || policy == return_value_policy::automatic)
+        if (policy == return_value_policy::take_ownership
+            || policy == return_value_policy::automatic) {
             policy = return_value_policy::automatic_reference;
+        }
         return caster_t::cast(&src.get(), policy, parent);
     }
-    template <typename T> using cast_op_type = std::reference_wrapper<type>;
-    operator std::reference_wrapper<type>() { return subcaster.operator subcaster_cast_op_type&(); }
+    template <typename T>
+    using cast_op_type = std::reference_wrapper<type>;
+    explicit operator std::reference_wrapper<type>() { return cast_op<type &>(subcaster); }
 };
 
-#define PYBIND11_TYPE_CASTER(type, py_name) \
-    protected: \
-        type value; \
-    public: \
-        static constexpr auto name = py_name; \
-        template <typename T_, enable_if_t<std::is_same<type, remove_cv_t<T_>>::value, int> = 0> \
-        static handle cast(T_ *src, return_value_policy policy, handle parent) { \
-            if (!src) return none().release(); \
-            if (policy == return_value_policy::take_ownership) { \
-                auto h = cast(std::move(*src), policy, parent); delete src; return h; \
-            } else { \
-                return cast(*src, policy, parent); \
-            } \
-        } \
-        operator type*() { return &value; } \
-        operator type&() { return value; } \
-        operator type&&() && { return std::move(value); } \
-        template <typename T_> using cast_op_type = pybind11::detail::movable_cast_op_type<T_>
-
-
-template <typename CharT> using is_std_char_type = any_of<
-    std::is_same<CharT, char>, /* std::string */
+#define PYBIND11_TYPE_CASTER(type, py_name)                                                       \
+protected:                                                                                        \
+    type value;                                                                                   \
+                                                                                                  \
+public:                                                                                           \
+    static constexpr auto name = py_name;                                                         \
+    template <typename T_,                                                                        \
+              ::pybind11::detail::enable_if_t<                                                    \
+                  std::is_same<type, ::pybind11::detail::remove_cv_t<T_>>::value,                 \
+                  int> = 0>                                                                       \
+    static ::pybind11::handle cast(                                                               \
+        T_ *src, ::pybind11::return_value_policy policy, ::pybind11::handle parent) {             \
+        if (!src)                                                                                 \
+            return ::pybind11::none().release();                                                  \
+        if (policy == ::pybind11::return_value_policy::take_ownership) {                          \
+            auto h = cast(std::move(*src), policy, parent);                                       \
+            delete src;                                                                           \
+            return h;                                                                             \
+        }                                                                                         \
+        return cast(*src, policy, parent);                                                        \
+    }                                                                                             \
+    operator type *() { return &value; }               /* NOLINT(bugprone-macro-parentheses) */   \
+    operator type &() { return value; }                /* NOLINT(bugprone-macro-parentheses) */   \
+    operator type &&() && { return std::move(value); } /* NOLINT(bugprone-macro-parentheses) */   \
+    template <typename T_>                                                                        \
+    using cast_op_type = ::pybind11::detail::movable_cast_op_type<T_>
+
+template <typename CharT>
+using is_std_char_type = any_of<std::is_same<CharT, char>, /* std::string */
 #if defined(PYBIND11_HAS_U8STRING)
-    std::is_same<CharT, char8_t>, /* std::u8string */
+                                std::is_same<CharT, char8_t>, /* std::u8string */
 #endif
-    std::is_same<CharT, char16_t>, /* std::u16string */
-    std::is_same<CharT, char32_t>, /* std::u32string */
-    std::is_same<CharT, wchar_t> /* std::wstring */
->;
-
+                                std::is_same<CharT, char16_t>, /* std::u16string */
+                                std::is_same<CharT, char32_t>, /* std::u32string */
+                                std::is_same<CharT, wchar_t>   /* std::wstring */
+                                >;
 
 template <typename T>
 struct type_caster<T, enable_if_t<std::is_arithmetic<T>::value && !is_std_char_type<T>::value>> {
     using _py_type_0 = conditional_t<sizeof(T) <= sizeof(long), long, long long>;
-    using _py_type_1 = conditional_t<std::is_signed<T>::value, _py_type_0, typename std::make_unsigned<_py_type_0>::type>;
+    using _py_type_1 = conditional_t<std::is_signed<T>::value,
+                                     _py_type_0,
+                                     typename std::make_unsigned<_py_type_0>::type>;
     using py_type = conditional_t<std::is_floating_point<T>::value, double, _py_type_1>;
-public:
 
+public:
     bool load(handle src, bool convert) {
         py_type py_value;
 
-        if (!src)
+        if (!src) {
             return false;
+        }
+
+#if !defined(PYPY_VERSION)
+        auto index_check = [](PyObject *o) { return PyIndex_Check(o); };
+#else
+        // In PyPy 7.3.3, `PyIndex_Check` is implemented by calling `__index__`,
+        // while CPython only considers the existence of `nb_index`/`__index__`.
+        auto index_check = [](PyObject *o) { return hasattr(o, "__index__"); };
+#endif
 
         if (std::is_floating_point<T>::value) {
-            if (convert || PyFloat_Check(src.ptr()))
+            if (convert || PyFloat_Check(src.ptr())) {
                 py_value = (py_type) PyFloat_AsDouble(src.ptr());
-            else
+            } else {
                 return false;
-        } else if (PyFloat_Check(src.ptr())) {
+            }
+        } else if (PyFloat_Check(src.ptr())
+                   || (!convert && !PYBIND11_LONG_CHECK(src.ptr()) && !index_check(src.ptr()))) {
             return false;
-        } else if (std::is_unsigned<py_type>::value) {
-            py_value = as_unsigned<py_type>(src.ptr());
-        } else { // signed integer:
-            py_value = sizeof(T) <= sizeof(long)
-                ? (py_type) PyLong_AsLong(src.ptr())
-                : (py_type) PYBIND11_LONG_AS_LONGLONG(src.ptr());
+        } else {
+            handle src_or_index = src;
+            // PyPy: 7.3.7's 3.8 does not implement PyLong_*'s __index__ calls.
+#if PY_VERSION_HEX < 0x03080000 || defined(PYPY_VERSION)
+            object index;
+            if (!PYBIND11_LONG_CHECK(src.ptr())) { // So: index_check(src.ptr())
+                index = reinterpret_steal<object>(PyNumber_Index(src.ptr()));
+                if (!index) {
+                    PyErr_Clear();
+                    if (!convert)
+                        return false;
+                } else {
+                    src_or_index = index;
+                }
+            }
+#endif
+            if (std::is_unsigned<py_type>::value) {
+                py_value = as_unsigned<py_type>(src_or_index.ptr());
+            } else { // signed integer:
+                py_value = sizeof(T) <= sizeof(long)
+                               ? (py_type) PyLong_AsLong(src_or_index.ptr())
+                               : (py_type) PYBIND11_LONG_AS_LONGLONG(src_or_index.ptr());
+            }
         }
 
         // Python API reported an error
@@ -1040,19 +179,14 @@ struct type_caster<T, enable_if_t<std::is_arithmetic<T>::value && !is_std_char_t
 
         // Check to see if the conversion is valid (integers should match exactly)
         // Signed/unsigned checks happen elsewhere
-        if (py_err || (std::is_integral<T>::value && sizeof(py_type) != sizeof(T) && py_value != (py_type) (T) py_value)) {
-            bool type_error = py_err && PyErr_ExceptionMatches(
-#if PY_VERSION_HEX < 0x03000000 && !defined(PYPY_VERSION)
-                PyExc_SystemError
-#else
-                PyExc_TypeError
-#endif
-            );
+        if (py_err
+            || (std::is_integral<T>::value && sizeof(py_type) != sizeof(T)
+                && py_value != (py_type) (T) py_value)) {
             PyErr_Clear();
-            if (type_error && convert && PyNumber_Check(src.ptr())) {
+            if (py_err && convert && (PyNumber_Check(src.ptr()) != 0)) {
                 auto tmp = reinterpret_steal<object>(std::is_floating_point<T>::value
-                                                     ? PyNumber_Float(src.ptr())
-                                                     : PyNumber_Long(src.ptr()));
+                                                         ? PyNumber_Float(src.ptr())
+                                                         : PyNumber_Long(src.ptr()));
                 PyErr_Clear();
                 return load(tmp, false);
             }
@@ -1063,62 +197,75 @@ struct type_caster<T, enable_if_t<std::is_arithmetic<T>::value && !is_std_char_t
         return true;
     }
 
-    template<typename U = T>
+    template <typename U = T>
     static typename std::enable_if<std::is_floating_point<U>::value, handle>::type
     cast(U src, return_value_policy /* policy */, handle /* parent */) {
         return PyFloat_FromDouble((double) src);
     }
 
-    template<typename U = T>
-    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_signed<U>::value && (sizeof(U) <= sizeof(long)), handle>::type
+    template <typename U = T>
+    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_signed<U>::value
+                                       && (sizeof(U) <= sizeof(long)),
+                                   handle>::type
     cast(U src, return_value_policy /* policy */, handle /* parent */) {
         return PYBIND11_LONG_FROM_SIGNED((long) src);
     }
 
-    template<typename U = T>
-    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_unsigned<U>::value && (sizeof(U) <= sizeof(unsigned long)), handle>::type
+    template <typename U = T>
+    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_unsigned<U>::value
+                                       && (sizeof(U) <= sizeof(unsigned long)),
+                                   handle>::type
     cast(U src, return_value_policy /* policy */, handle /* parent */) {
         return PYBIND11_LONG_FROM_UNSIGNED((unsigned long) src);
     }
 
-    template<typename U = T>
-    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_signed<U>::value && (sizeof(U) > sizeof(long)), handle>::type
+    template <typename U = T>
+    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_signed<U>::value
+                                       && (sizeof(U) > sizeof(long)),
+                                   handle>::type
     cast(U src, return_value_policy /* policy */, handle /* parent */) {
         return PyLong_FromLongLong((long long) src);
     }
 
-    template<typename U = T>
-    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_unsigned<U>::value && (sizeof(U) > sizeof(unsigned long)), handle>::type
+    template <typename U = T>
+    static typename std::enable_if<!std::is_floating_point<U>::value && std::is_unsigned<U>::value
+                                       && (sizeof(U) > sizeof(unsigned long)),
+                                   handle>::type
     cast(U src, return_value_policy /* policy */, handle /* parent */) {
         return PyLong_FromUnsignedLongLong((unsigned long long) src);
     }
 
-    PYBIND11_TYPE_CASTER(T, _<std::is_integral<T>::value>("int", "float"));
+    PYBIND11_TYPE_CASTER(T, const_name<std::is_integral<T>::value>("int", "float"));
 };
 
-template<typename T> struct void_caster {
+template <typename T>
+struct void_caster {
 public:
     bool load(handle src, bool) {
-        if (src && src.is_none())
+        if (src && src.is_none()) {
             return true;
+        }
         return false;
     }
     static handle cast(T, return_value_policy /* policy */, handle /* parent */) {
         return none().inc_ref();
     }
-    PYBIND11_TYPE_CASTER(T, _("None"));
+    PYBIND11_TYPE_CASTER(T, const_name("None"));
 };
 
-template <> class type_caster<void_type> : public void_caster<void_type> {};
+template <>
+class type_caster<void_type> : public void_caster<void_type> {};
 
-template <> class type_caster<void> : public type_caster<void_type> {
+template <>
+class type_caster<void> : public type_caster<void_type> {
 public:
     using type_caster<void_type>::cast;
 
     bool load(handle h, bool) {
         if (!h) {
             return false;
-        } else if (h.is_none()) {
+        }
+        if (h.is_none()) {
             value = nullptr;
             return true;
         }
@@ -1130,7 +277,7 @@ template <> class type_caster<void> : public type_caster<void_type> {
         }
 
         /* Check if this is a C++ type */
-        auto &bases = all_type_info((PyTypeObject *) type::handle_of(h).ptr());
+        const auto &bases = all_type_info((PyTypeObject *) type::handle_of(h).ptr());
         if (bases.size() == 1) { // Only allowing loading from a single-value type
             value = values_and_holders(reinterpret_cast<instance *>(h.ptr())).begin()->value_ptr();
             return true;
@@ -1141,191 +288,247 @@ template <> class type_caster<void> : public type_caster<void_type> {
     }
 
     static handle cast(const void *ptr, return_value_policy /* policy */, handle /* parent */) {
-        if (ptr)
+        if (ptr) {
             return capsule(ptr).release();
-        else
-            return none().inc_ref();
+        }
+        return none().inc_ref();
     }
 
-    template <typename T> using cast_op_type = void*&;
-    operator void *&() { return value; }
-    static constexpr auto name = _("capsule");
+    template <typename T>
+    using cast_op_type = void *&;
+    explicit operator void *&() { return value; }
+    static constexpr auto name = const_name("capsule");
+
 private:
     void *value = nullptr;
 };
 
-template <> class type_caster<std::nullptr_t> : public void_caster<std::nullptr_t> { };
+template <>
+class type_caster<std::nullptr_t> : public void_caster<std::nullptr_t> {};
 
-template <> class type_caster<bool> {
+template <>
+class type_caster<bool> {
 public:
     bool load(handle src, bool convert) {
-        if (!src) return false;
-        else if (src.ptr() == Py_True) { value = true; return true; }
-        else if (src.ptr() == Py_False) { value = false; return true; }
-        else if (convert || !strcmp("numpy.bool_", Py_TYPE(src.ptr())->tp_name)) {
+        if (!src) {
+            return false;
+        }
+        if (src.ptr() == Py_True) {
+            value = true;
+            return true;
+        }
+        if (src.ptr() == Py_False) {
+            value = false;
+            return true;
+        }
+        if (convert || (std::strcmp("numpy.bool_", Py_TYPE(src.ptr())->tp_name) == 0)) {
             // (allow non-implicit conversion for numpy booleans)
 
             Py_ssize_t res = -1;
             if (src.is_none()) {
-                res = 0;  // None is implicitly converted to False
+                res = 0; // None is implicitly converted to False
             }
-            #if defined(PYPY_VERSION)
-            // On PyPy, check that "__bool__" (or "__nonzero__" on Python 2.7) attr exists
+#if defined(PYPY_VERSION)
+            // On PyPy, check that "__bool__" attr exists
             else if (hasattr(src, PYBIND11_BOOL_ATTR)) {
                 res = PyObject_IsTrue(src.ptr());
             }
-            #else
+#else
             // Alternate approach for CPython: this does the same as the above, but optimized
             // using the CPython API so as to avoid an unneeded attribute lookup.
-            else if (auto tp_as_number = src.ptr()->ob_type->tp_as_number) {
+            else if (auto *tp_as_number = src.ptr()->ob_type->tp_as_number) {
                 if (PYBIND11_NB_BOOL(tp_as_number)) {
                     res = (*PYBIND11_NB_BOOL(tp_as_number))(src.ptr());
                 }
             }
-            #endif
+#endif
             if (res == 0 || res == 1) {
-                value = (bool) res;
+                value = (res != 0);
                 return true;
-            } else {
-                PyErr_Clear();
             }
+            PyErr_Clear();
         }
         return false;
     }
     static handle cast(bool src, return_value_policy /* policy */, handle /* parent */) {
         return handle(src ? Py_True : Py_False).inc_ref();
     }
-    PYBIND11_TYPE_CASTER(bool, _("bool"));
+    PYBIND11_TYPE_CASTER(bool, const_name("bool"));
 };
 
 // Helper class for UTF-{8,16,32} C++ stl strings:
-template <typename StringType, bool IsView = false> struct string_caster {
+template <typename StringType, bool IsView = false>
+struct string_caster {
     using CharT = typename StringType::value_type;
 
     // Simplify life by being able to assume standard char sizes (the standard only guarantees
     // minimums, but Python requires exact sizes)
-    static_assert(!std::is_same<CharT, char>::value || sizeof(CharT) == 1, "Unsupported char size != 1");
+    static_assert(!std::is_same<CharT, char>::value || sizeof(CharT) == 1,
+                  "Unsupported char size != 1");
 #if defined(PYBIND11_HAS_U8STRING)
-    static_assert(!std::is_same<CharT, char8_t>::value || sizeof(CharT) == 1, "Unsupported char8_t size != 1");
+    static_assert(!std::is_same<CharT, char8_t>::value || sizeof(CharT) == 1,
+                  "Unsupported char8_t size != 1");
 #endif
-    static_assert(!std::is_same<CharT, char16_t>::value || sizeof(CharT) == 2, "Unsupported char16_t size != 2");
-    static_assert(!std::is_same<CharT, char32_t>::value || sizeof(CharT) == 4, "Unsupported char32_t size != 4");
+    static_assert(!std::is_same<CharT, char16_t>::value || sizeof(CharT) == 2,
+                  "Unsupported char16_t size != 2");
+    static_assert(!std::is_same<CharT, char32_t>::value || sizeof(CharT) == 4,
+                  "Unsupported char32_t size != 4");
     // wchar_t can be either 16 bits (Windows) or 32 (everywhere else)
     static_assert(!std::is_same<CharT, wchar_t>::value || sizeof(CharT) == 2 || sizeof(CharT) == 4,
-            "Unsupported wchar_t size != 2/4");
+                  "Unsupported wchar_t size != 2/4");
     static constexpr size_t UTF_N = 8 * sizeof(CharT);
 
     bool load(handle src, bool) {
-#if PY_MAJOR_VERSION < 3
-        object temp;
-#endif
         handle load_src = src;
         if (!src) {
             return false;
-        } else if (!PyUnicode_Check(load_src.ptr())) {
-#if PY_MAJOR_VERSION >= 3
-            return load_bytes(load_src);
-#else
-            if (std::is_same<CharT, char>::value) {
-                return load_bytes(load_src);
-            }
+        }
+        if (!PyUnicode_Check(load_src.ptr())) {
+            return load_raw(load_src);
+        }
 
-            // The below is a guaranteed failure in Python 3 when PyUnicode_Check returns false
-            if (!PYBIND11_BYTES_CHECK(load_src.ptr()))
+        // For UTF-8 we avoid the need for a temporary `bytes` object by using
+        // `PyUnicode_AsUTF8AndSize`.
+        if (PYBIND11_SILENCE_MSVC_C4127(UTF_N == 8)) {
+            Py_ssize_t size = -1;
+            const auto *buffer
+                = reinterpret_cast<const CharT *>(PyUnicode_AsUTF8AndSize(load_src.ptr(), &size));
+            if (!buffer) {
+                PyErr_Clear();
                 return false;
-
-            temp = reinterpret_steal<object>(PyUnicode_FromObject(load_src.ptr()));
-            if (!temp) { PyErr_Clear(); return false; }
-            load_src = temp;
-#endif
+            }
+            value = StringType(buffer, static_cast<size_t>(size));
+            return true;
         }
 
-        auto utfNbytes = reinterpret_steal<object>(PyUnicode_AsEncodedString(
-            load_src.ptr(), UTF_N == 8 ? "utf-8" : UTF_N == 16 ? "utf-16" : "utf-32", nullptr));
-        if (!utfNbytes) { PyErr_Clear(); return false; }
+        auto utfNbytes
+            = reinterpret_steal<object>(PyUnicode_AsEncodedString(load_src.ptr(),
+                                                                  UTF_N == 8    ? "utf-8"
+                                                                  : UTF_N == 16 ? "utf-16"
+                                                                                : "utf-32",
+                                                                  nullptr));
+        if (!utfNbytes) {
+            PyErr_Clear();
+            return false;
+        }
 
-        const auto *buffer = reinterpret_cast<const CharT *>(PYBIND11_BYTES_AS_STRING(utfNbytes.ptr()));
+        const auto *buffer
+            = reinterpret_cast<const CharT *>(PYBIND11_BYTES_AS_STRING(utfNbytes.ptr()));
         size_t length = (size_t) PYBIND11_BYTES_SIZE(utfNbytes.ptr()) / sizeof(CharT);
-        if (UTF_N > 8) { buffer++; length--; } // Skip BOM for UTF-16/32
+        // Skip BOM for UTF-16/32
+        if (PYBIND11_SILENCE_MSVC_C4127(UTF_N > 8)) {
+            buffer++;
+            length--;
+        }
         value = StringType(buffer, length);
 
         // If we're loading a string_view we need to keep the encoded Python object alive:
-        if (IsView)
+        if (IsView) {
             loader_life_support::add_patient(utfNbytes);
+        }
 
         return true;
     }
 
-    static handle cast(const StringType &src, return_value_policy /* policy */, handle /* parent */) {
+    static handle
+    cast(const StringType &src, return_value_policy /* policy */, handle /* parent */) {
         const char *buffer = reinterpret_cast<const char *>(src.data());
         auto nbytes = ssize_t(src.size() * sizeof(CharT));
         handle s = decode_utfN(buffer, nbytes);
-        if (!s) throw error_already_set();
+        if (!s) {
+            throw error_already_set();
+        }
         return s;
     }
 
-    PYBIND11_TYPE_CASTER(StringType, _(PYBIND11_STRING_NAME));
+    PYBIND11_TYPE_CASTER(StringType, const_name(PYBIND11_STRING_NAME));
 
 private:
     static handle decode_utfN(const char *buffer, ssize_t nbytes) {
 #if !defined(PYPY_VERSION)
-        return
-            UTF_N == 8  ? PyUnicode_DecodeUTF8(buffer, nbytes, nullptr) :
-            UTF_N == 16 ? PyUnicode_DecodeUTF16(buffer, nbytes, nullptr, nullptr) :
-                          PyUnicode_DecodeUTF32(buffer, nbytes, nullptr, nullptr);
+        return UTF_N == 8    ? PyUnicode_DecodeUTF8(buffer, nbytes, nullptr)
+               : UTF_N == 16 ? PyUnicode_DecodeUTF16(buffer, nbytes, nullptr, nullptr)
+                             : PyUnicode_DecodeUTF32(buffer, nbytes, nullptr, nullptr);
 #else
-        // PyPy segfaults when on PyUnicode_DecodeUTF16 (and possibly on PyUnicode_DecodeUTF32 as well),
-        // so bypass the whole thing by just passing the encoding as a string value, which works properly:
-        return PyUnicode_Decode(buffer, nbytes, UTF_N == 8 ? "utf-8" : UTF_N == 16 ? "utf-16" : "utf-32", nullptr);
+        // PyPy segfaults when on PyUnicode_DecodeUTF16 (and possibly on PyUnicode_DecodeUTF32 as
+        // well), so bypass the whole thing by just passing the encoding as a string value, which
+        // works properly:
+        return PyUnicode_Decode(buffer,
+                                nbytes,
+                                UTF_N == 8    ? "utf-8"
+                                : UTF_N == 16 ? "utf-16"
+                                              : "utf-32",
+                                nullptr);
 #endif
     }
 
-    // When loading into a std::string or char*, accept a bytes object as-is (i.e.
+    // When loading into a std::string or char*, accept a bytes/bytearray object as-is (i.e.
     // without any encoding/decoding attempt).  For other C++ char sizes this is a no-op.
     // which supports loading a unicode from a str, doesn't take this path.
     template <typename C = CharT>
-    bool load_bytes(enable_if_t<std::is_same<C, char>::value, handle> src) {
+    bool load_raw(enable_if_t<std::is_same<C, char>::value, handle> src) {
         if (PYBIND11_BYTES_CHECK(src.ptr())) {
-            // We were passed a Python 3 raw bytes; accept it into a std::string or char*
+            // We were passed raw bytes; accept it into a std::string or char*
             // without any encoding attempt.
             const char *bytes = PYBIND11_BYTES_AS_STRING(src.ptr());
-            if (bytes) {
-                value = StringType(bytes, (size_t) PYBIND11_BYTES_SIZE(src.ptr()));
-                return true;
+            if (!bytes) {
+                pybind11_fail("Unexpected PYBIND11_BYTES_AS_STRING() failure.");
             }
+            value = StringType(bytes, (size_t) PYBIND11_BYTES_SIZE(src.ptr()));
+            return true;
+        }
+        if (PyByteArray_Check(src.ptr())) {
+            // We were passed a bytearray; accept it into a std::string or char*
+            // without any encoding attempt.
+            const char *bytearray = PyByteArray_AsString(src.ptr());
+            if (!bytearray) {
+                pybind11_fail("Unexpected PyByteArray_AsString() failure.");
+            }
+            value = StringType(bytearray, (size_t) PyByteArray_Size(src.ptr()));
+            return true;
         }
 
         return false;
     }
 
     template <typename C = CharT>
-    bool load_bytes(enable_if_t<!std::is_same<C, char>::value, handle>) { return false; }
+    bool load_raw(enable_if_t<!std::is_same<C, char>::value, handle>) {
+        return false;
+    }
 };
 
 template <typename CharT, class Traits, class Allocator>
-struct type_caster<std::basic_string<CharT, Traits, Allocator>, enable_if_t<is_std_char_type<CharT>::value>>
+struct type_caster<std::basic_string<CharT, Traits, Allocator>,
+                   enable_if_t<is_std_char_type<CharT>::value>>
     : string_caster<std::basic_string<CharT, Traits, Allocator>> {};
 
 #ifdef PYBIND11_HAS_STRING_VIEW
 template <typename CharT, class Traits>
-struct type_caster<std::basic_string_view<CharT, Traits>, enable_if_t<is_std_char_type<CharT>::value>>
+struct type_caster<std::basic_string_view<CharT, Traits>,
+                   enable_if_t<is_std_char_type<CharT>::value>>
     : string_caster<std::basic_string_view<CharT, Traits>, true> {};
 #endif
 
 // Type caster for C-style strings.  We basically use a std::string type caster, but also add the
 // ability to use None as a nullptr char* (which the string caster doesn't allow).
-template <typename CharT> struct type_caster<CharT, enable_if_t<is_std_char_type<CharT>::value>> {
+template <typename CharT>
+struct type_caster<CharT, enable_if_t<is_std_char_type<CharT>::value>> {
     using StringType = std::basic_string<CharT>;
-    using StringCaster = type_caster<StringType>;
+    using StringCaster = make_caster<StringType>;
     StringCaster str_caster;
     bool none = false;
     CharT one_char = 0;
+
 public:
     bool load(handle src, bool convert) {
-        if (!src) return false;
+        if (!src) {
+            return false;
+        }
         if (src.is_none()) {
             // Defer accepting None to other overloads (if we aren't in convert mode):
-            if (!convert) return false;
+            if (!convert) {
+                return false;
+            }
             none = true;
             return true;
         }
@@ -1333,45 +536,58 @@ template <typename CharT> struct type_caster<CharT, enable_if_t<is_std_char_type
     }
 
     static handle cast(const CharT *src, return_value_policy policy, handle parent) {
-        if (src == nullptr) return pybind11::none().inc_ref();
+        if (src == nullptr) {
+            return pybind11::none().inc_ref();
+        }
         return StringCaster::cast(StringType(src), policy, parent);
     }
 
     static handle cast(CharT src, return_value_policy policy, handle parent) {
         if (std::is_same<char, CharT>::value) {
             handle s = PyUnicode_DecodeLatin1((const char *) &src, 1, nullptr);
-            if (!s) throw error_already_set();
+            if (!s) {
+                throw error_already_set();
+            }
             return s;
         }
         return StringCaster::cast(StringType(1, src), policy, parent);
     }
 
-    operator CharT*() { return none ? nullptr : const_cast<CharT *>(static_cast<StringType &>(str_caster).c_str()); }
-    operator CharT&() {
-        if (none)
+    explicit operator CharT *() {
+        return none ? nullptr : const_cast<CharT *>(static_cast<StringType &>(str_caster).c_str());
+    }
+    explicit operator CharT &() {
+        if (none) {
             throw value_error("Cannot convert None to a character");
+        }
 
         auto &value = static_cast<StringType &>(str_caster);
         size_t str_len = value.size();
-        if (str_len == 0)
+        if (str_len == 0) {
             throw value_error("Cannot convert empty string to a character");
+        }
 
         // If we're in UTF-8 mode, we have two possible failures: one for a unicode character that
-        // is too high, and one for multiple unicode characters (caught later), so we need to figure
-        // out how long the first encoded character is in bytes to distinguish between these two
-        // errors.  We also allow want to allow unicode characters U+0080 through U+00FF, as those
-        // can fit into a single char value.
-        if (StringCaster::UTF_N == 8 && str_len > 1 && str_len <= 4) {
+        // is too high, and one for multiple unicode characters (caught later), so we need to
+        // figure out how long the first encoded character is in bytes to distinguish between these
+        // two errors.  We also allow want to allow unicode characters U+0080 through U+00FF, as
+        // those can fit into a single char value.
+        if (PYBIND11_SILENCE_MSVC_C4127(StringCaster::UTF_N == 8) && str_len > 1 && str_len <= 4) {
             auto v0 = static_cast<unsigned char>(value[0]);
-            size_t char0_bytes = !(v0 & 0x80) ? 1 : // low bits only: 0-127
-                (v0 & 0xE0) == 0xC0 ? 2 : // 0b110xxxxx - start of 2-byte sequence
-                (v0 & 0xF0) == 0xE0 ? 3 : // 0b1110xxxx - start of 3-byte sequence
-                4; // 0b11110xxx - start of 4-byte sequence
+            // low bits only: 0-127
+            // 0b110xxxxx - start of 2-byte sequence
+            // 0b1110xxxx - start of 3-byte sequence
+            // 0b11110xxx - start of 4-byte sequence
+            size_t char0_bytes = (v0 & 0x80) == 0      ? 1
+                                 : (v0 & 0xE0) == 0xC0 ? 2
+                                 : (v0 & 0xF0) == 0xE0 ? 3
+                                                       : 4;
 
             if (char0_bytes == str_len) {
                 // If we have a 128-255 value, we can decode it into a single char:
                 if (char0_bytes == 2 && (v0 & 0xFC) == 0xC0) { // 0x110000xx 0x10xxxxxx
-                    one_char = static_cast<CharT>(((v0 & 3) << 6) + (static_cast<unsigned char>(value[1]) & 0x3F));
+                    one_char = static_cast<CharT>(((v0 & 3) << 6)
+                                                  + (static_cast<unsigned char>(value[1]) & 0x3F));
                     return one_char;
                 }
                 // Otherwise we have a single character, but it's > U+00FF
@@ -1382,36 +598,42 @@ template <typename CharT> struct type_caster<CharT, enable_if_t<is_std_char_type
         // UTF-16 is much easier: we can only have a surrogate pair for values above U+FFFF, thus a
         // surrogate pair with total length 2 instantly indicates a range error (but not a "your
         // string was too long" error).
-        else if (StringCaster::UTF_N == 16 && str_len == 2) {
+        else if (PYBIND11_SILENCE_MSVC_C4127(StringCaster::UTF_N == 16) && str_len == 2) {
             one_char = static_cast<CharT>(value[0]);
-            if (one_char >= 0xD800 && one_char < 0xE000)
+            if (one_char >= 0xD800 && one_char < 0xE000) {
                 throw value_error("Character code point not in range(0x10000)");
+            }
         }
 
-        if (str_len != 1)
+        if (str_len != 1) {
             throw value_error("Expected a character, but multi-character string found");
+        }
 
         one_char = value[0];
         return one_char;
     }
 
-    static constexpr auto name = _(PYBIND11_STRING_NAME);
-    template <typename _T> using cast_op_type = pybind11::detail::cast_op_type<_T>;
+    static constexpr auto name = const_name(PYBIND11_STRING_NAME);
+    template <typename _T>
+    using cast_op_type = pybind11::detail::cast_op_type<_T>;
 };
 
 // Base implementation for std::tuple and std::pair
-template <template<typename...> class Tuple, typename... Ts> class tuple_caster {
+template <template <typename...> class Tuple, typename... Ts>
+class tuple_caster {
     using type = Tuple<Ts...>;
     static constexpr auto size = sizeof...(Ts);
     using indices = make_index_sequence<size>;
-public:
 
+public:
     bool load(handle src, bool convert) {
-        if (!isinstance<sequence>(src))
+        if (!isinstance<sequence>(src)) {
             return false;
+        }
         const auto seq = reinterpret_borrow<sequence>(src);
-        if (seq.size() != size)
+        if (seq.size() != size) {
             return false;
+        }
         return load_impl(seq, convert, indices{});
     }
 
@@ -1423,66 +645,83 @@ template <template<typename...> class Tuple, typename... Ts> class tuple_caster
     // copied from the PYBIND11_TYPE_CASTER macro
     template <typename T>
     static handle cast(T *src, return_value_policy policy, handle parent) {
-        if (!src) return none().release();
+        if (!src) {
+            return none().release();
+        }
         if (policy == return_value_policy::take_ownership) {
-            auto h = cast(std::move(*src), policy, parent); delete src; return h;
-        } else {
-            return cast(*src, policy, parent);
+            auto h = cast(std::move(*src), policy, parent);
+            delete src;
+            return h;
         }
+        return cast(*src, policy, parent);
     }
 
-    static constexpr auto name = _("Tuple[") + concat(make_caster<Ts>::name...) + _("]");
+    static constexpr auto name
+        = const_name("Tuple[") + concat(make_caster<Ts>::name...) + const_name("]");
 
-    template <typename T> using cast_op_type = type;
+    template <typename T>
+    using cast_op_type = type;
 
-    operator type() & { return implicit_cast(indices{}); }
-    operator type() && { return std::move(*this).implicit_cast(indices{}); }
+    explicit operator type() & { return implicit_cast(indices{}); }
+    explicit operator type() && { return std::move(*this).implicit_cast(indices{}); }
 
 protected:
     template <size_t... Is>
-    type implicit_cast(index_sequence<Is...>) & { return type(cast_op<Ts>(std::get<Is>(subcasters))...); }
+    type implicit_cast(index_sequence<Is...>) & {
+        return type(cast_op<Ts>(std::get<Is>(subcasters))...);
+    }
     template <size_t... Is>
-    type implicit_cast(index_sequence<Is...>) && { return type(cast_op<Ts>(std::move(std::get<Is>(subcasters)))...); }
+    type implicit_cast(index_sequence<Is...>) && {
+        return type(cast_op<Ts>(std::move(std::get<Is>(subcasters)))...);
+    }
 
     static constexpr bool load_impl(const sequence &, bool, index_sequence<>) { return true; }
 
     template <size_t... Is>
     bool load_impl(const sequence &seq, bool convert, index_sequence<Is...>) {
 #ifdef __cpp_fold_expressions
-        if ((... || !std::get<Is>(subcasters).load(seq[Is], convert)))
+        if ((... || !std::get<Is>(subcasters).load(seq[Is], convert))) {
             return false;
+        }
 #else
-        for (bool r : {std::get<Is>(subcasters).load(seq[Is], convert)...})
-            if (!r)
+        for (bool r : {std::get<Is>(subcasters).load(seq[Is], convert)...}) {
+            if (!r) {
                 return false;
+            }
+        }
 #endif
         return true;
     }
 
     /* Implementation: Convert a C++ tuple into a Python tuple */
     template <typename T, size_t... Is>
-    static handle cast_impl(T &&src, return_value_policy policy, handle parent, index_sequence<Is...>) {
-        std::array<object, size> entries{{
-            reinterpret_steal<object>(make_caster<Ts>::cast(std::get<Is>(std::forward<T>(src)), policy, parent))...
-        }};
-        for (const auto &entry: entries)
-            if (!entry)
+    static handle
+    cast_impl(T &&src, return_value_policy policy, handle parent, index_sequence<Is...>) {
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(src, policy, parent);
+        PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(policy, parent);
+        std::array<object, size> entries{{reinterpret_steal<object>(
+            make_caster<Ts>::cast(std::get<Is>(std::forward<T>(src)), policy, parent))...}};
+        for (const auto &entry : entries) {
+            if (!entry) {
                 return handle();
+            }
+        }
         tuple result(size);
         int counter = 0;
-        for (auto & entry: entries)
+        for (auto &entry : entries) {
             PyTuple_SET_ITEM(result.ptr(), counter++, entry.release().ptr());
+        }
         return result.release();
     }
 
     Tuple<make_caster<Ts>...> subcasters;
 };
 
-template <typename T1, typename T2> class type_caster<std::pair<T1, T2>>
-    : public tuple_caster<std::pair, T1, T2> {};
+template <typename T1, typename T2>
+class type_caster<std::pair<T1, T2>> : public tuple_caster<std::pair, T1, T2> {};
 
-template <typename... Ts> class type_caster<std::tuple<Ts...>>
-    : public tuple_caster<std::tuple, Ts...> {};
+template <typename... Ts>
+class type_caster<std::tuple<Ts...>> : public tuple_caster<std::tuple, Ts...> {};
 
 /// Helper class which abstracts away certain actions. Users can provide specializations for
 /// custom holders, but it's only necessary if the type has a non-standard interface.
@@ -1492,12 +731,16 @@ struct holder_helper {
 };
 
 /// Type caster for holder types like std::shared_ptr, etc.
-template <typename type, typename holder_type>
+/// The SFINAE hook is provided to help work around the current lack of support
+/// for smart-pointer interoperability. Please consider it an implementation
+/// detail that may change in the future, as formal support for smart-pointer
+/// interoperability is added into pybind11.
+template <typename type, typename holder_type, typename SFINAE = void>
 struct copyable_holder_caster : public type_caster_base<type> {
 public:
     using base = type_caster_base<type>;
     static_assert(std::is_base_of<base, type_caster<type>>::value,
-            "Holder classes are only supported for custom types");
+                  "Holder classes are only supported for custom types");
     using base::base;
     using base::cast;
     using base::typeinfo;
@@ -1507,12 +750,12 @@ struct copyable_holder_caster : public type_caster_base<type> {
         return base::template load_impl<copyable_holder_caster<type, holder_type>>(src, convert);
     }
 
-    explicit operator type*() { return this->value; }
+    explicit operator type *() { return this->value; }
     // static_cast works around compiler error with MSVC 17 and CUDA 10.2
     // see issue #2180
-    explicit operator type&() { return *(static_cast<type *>(this->value)); }
-    explicit operator holder_type*() { return std::addressof(holder); }
-    explicit operator holder_type&() { return holder; }
+    explicit operator type &() { return *(static_cast<type *>(this->value)); }
+    explicit operator holder_type *() { return std::addressof(holder); }
+    explicit operator holder_type &() { return holder; }
 
     static handle cast(const holder_type &src, return_value_policy, handle) {
         const auto *ptr = holder_helper<holder_type>::get(src);
@@ -1522,8 +765,9 @@ struct copyable_holder_caster : public type_caster_base<type> {
 protected:
     friend class type_caster_generic;
     void check_holder_compat() {
-        if (typeinfo->default_holder)
+        if (typeinfo->default_holder) {
             throw cast_error("Unable to load a custom holder type from a default-holder instance");
+        }
     }
 
     bool load_value(value_and_holder &&v_h) {
@@ -1531,20 +775,25 @@ struct copyable_holder_caster : public type_caster_base<type> {
             value = v_h.value_ptr();
             holder = v_h.template holder<holder_type>();
             return true;
-        } else {
-            throw cast_error("Unable to cast from non-held to held instance (T& to Holder<T>) "
-#if defined(NDEBUG)
-                             "(compile in debug mode for type information)");
+        }
+        throw cast_error("Unable to cast from non-held to held instance (T& to Holder<T>) "
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+                         "(#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for "
+                         "type information)");
 #else
-                             "of type '" + type_id<holder_type>() + "''");
+                         "of type '"
+                         + type_id<holder_type>() + "''");
 #endif
-        }
     }
 
-    template <typename T = holder_type, detail::enable_if_t<!std::is_constructible<T, const T &, type*>::value, int> = 0>
-    bool try_implicit_casts(handle, bool) { return false; }
+    template <typename T = holder_type,
+              detail::enable_if_t<!std::is_constructible<T, const T &, type *>::value, int> = 0>
+    bool try_implicit_casts(handle, bool) {
+        return false;
+    }
 
-    template <typename T = holder_type, detail::enable_if_t<std::is_constructible<T, const T &, type*>::value, int> = 0>
+    template <typename T = holder_type,
+              detail::enable_if_t<std::is_constructible<T, const T &, type *>::value, int> = 0>
     bool try_implicit_casts(handle src, bool convert) {
         for (auto &cast : typeinfo->implicit_casts) {
             copyable_holder_caster sub_caster(*cast.first);
@@ -1559,18 +808,20 @@ struct copyable_holder_caster : public type_caster_base<type> {
 
     static bool try_direct_conversions(handle) { return false; }
 
-
     holder_type holder;
 };
 
 /// Specialize for the common std::shared_ptr, so users don't need to
 template <typename T>
-class type_caster<std::shared_ptr<T>> : public copyable_holder_caster<T, std::shared_ptr<T>> { };
+class type_caster<std::shared_ptr<T>> : public copyable_holder_caster<T, std::shared_ptr<T>> {};
 
-template <typename type, typename holder_type>
+/// Type caster for holder types like std::unique_ptr.
+/// Please consider the SFINAE hook an implementation detail, as explained
+/// in the comment for the copyable_holder_caster.
+template <typename type, typename holder_type, typename SFINAE = void>
 struct move_only_holder_caster {
     static_assert(std::is_base_of<type_caster_base<type>, type_caster<type>>::value,
-            "Holder classes are only supported for custom types");
+                  "Holder classes are only supported for custom types");
 
     static handle cast(holder_type &&src, return_value_policy, handle) {
         auto *ptr = holder_helper<holder_type>::get(src);
@@ -1581,50 +832,101 @@ struct move_only_holder_caster {
 
 template <typename type, typename deleter>
 class type_caster<std::unique_ptr<type, deleter>>
-    : public move_only_holder_caster<type, std::unique_ptr<type, deleter>> { };
+    : public move_only_holder_caster<type, std::unique_ptr<type, deleter>> {};
 
 template <typename type, typename holder_type>
 using type_caster_holder = conditional_t<is_copy_constructible<holder_type>::value,
                                          copyable_holder_caster<type, holder_type>,
                                          move_only_holder_caster<type, holder_type>>;
 
-template <typename T, bool Value = false> struct always_construct_holder { static constexpr bool value = Value; };
+template <typename T, bool Value = false>
+struct always_construct_holder {
+    static constexpr bool value = Value;
+};
 
 /// Create a specialization for custom holder types (silently ignores std::shared_ptr)
-#define PYBIND11_DECLARE_HOLDER_TYPE(type, holder_type, ...) \
-    namespace pybind11 { namespace detail { \
-    template <typename type> \
-    struct always_construct_holder<holder_type> : always_construct_holder<void, ##__VA_ARGS__>  { }; \
-    template <typename type> \
-    class type_caster<holder_type, enable_if_t<!is_shared_ptr<holder_type>::value>> \
-        : public type_caster_holder<type, holder_type> { }; \
-    }}
+#define PYBIND11_DECLARE_HOLDER_TYPE(type, holder_type, ...)                                      \
+    PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)                                                  \
+    namespace detail {                                                                            \
+    template <typename type>                                                                      \
+    struct always_construct_holder<holder_type> : always_construct_holder<void, ##__VA_ARGS__> {  \
+    };                                                                                            \
+    template <typename type>                                                                      \
+    class type_caster<holder_type, enable_if_t<!is_shared_ptr<holder_type>::value>>               \
+        : public type_caster_holder<type, holder_type> {};                                        \
+    }                                                                                             \
+    PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
 
 // PYBIND11_DECLARE_HOLDER_TYPE holder types:
-template <typename base, typename holder> struct is_holder_type :
-    std::is_base_of<detail::type_caster_holder<base, holder>, detail::type_caster<holder>> {};
+template <typename base, typename holder>
+struct is_holder_type
+    : std::is_base_of<detail::type_caster_holder<base, holder>, detail::type_caster<holder>> {};
 // Specialization for always-supported unique_ptr holders:
-template <typename base, typename deleter> struct is_holder_type<base, std::unique_ptr<base, deleter>> :
-    std::true_type {};
-
-template <typename T> struct handle_type_name { static constexpr auto name = _<T>(); };
-template <> struct handle_type_name<bytes> { static constexpr auto name = _(PYBIND11_BYTES_NAME); };
-template <> struct handle_type_name<int_> { static constexpr auto name = _("int"); };
-template <> struct handle_type_name<iterable> { static constexpr auto name = _("Iterable"); };
-template <> struct handle_type_name<iterator> { static constexpr auto name = _("Iterator"); };
-template <> struct handle_type_name<none> { static constexpr auto name = _("None"); };
-template <> struct handle_type_name<args> { static constexpr auto name = _("*args"); };
-template <> struct handle_type_name<kwargs> { static constexpr auto name = _("**kwargs"); };
+template <typename base, typename deleter>
+struct is_holder_type<base, std::unique_ptr<base, deleter>> : std::true_type {};
+
+template <typename T>
+struct handle_type_name {
+    static constexpr auto name = const_name<T>();
+};
+template <>
+struct handle_type_name<bool_> {
+    static constexpr auto name = const_name("bool");
+};
+template <>
+struct handle_type_name<bytes> {
+    static constexpr auto name = const_name(PYBIND11_BYTES_NAME);
+};
+template <>
+struct handle_type_name<int_> {
+    static constexpr auto name = const_name("int");
+};
+template <>
+struct handle_type_name<iterable> {
+    static constexpr auto name = const_name("Iterable");
+};
+template <>
+struct handle_type_name<iterator> {
+    static constexpr auto name = const_name("Iterator");
+};
+template <>
+struct handle_type_name<float_> {
+    static constexpr auto name = const_name("float");
+};
+template <>
+struct handle_type_name<none> {
+    static constexpr auto name = const_name("None");
+};
+template <>
+struct handle_type_name<args> {
+    static constexpr auto name = const_name("*args");
+};
+template <>
+struct handle_type_name<kwargs> {
+    static constexpr auto name = const_name("**kwargs");
+};
 
 template <typename type>
 struct pyobject_caster {
     template <typename T = type, enable_if_t<std::is_same<T, handle>::value, int> = 0>
-    bool load(handle src, bool /* convert */) { value = src; return static_cast<bool>(value); }
+    pyobject_caster() : value() {}
 
+    // `type` may not be default constructible (e.g. frozenset, anyset).  Initializing `value`
+    // to a nil handle is safe since it will only be accessed if `load` succeeds.
     template <typename T = type, enable_if_t<std::is_base_of<object, T>::value, int> = 0>
+    pyobject_caster() : value(reinterpret_steal<type>(handle())) {}
+
+    template <typename T = type, enable_if_t<std::is_same<T, handle>::value, int> = 0>
     bool load(handle src, bool /* convert */) {
-        if (!isinstance<type>(src))
+        value = src;
+        return static_cast<bool>(value);
+    }
+
+    template <typename T = type, enable_if_t<std::is_base_of<object, T>::value, int> = 0>
+    bool load(handle src, bool /* convert */) {
+        if (!isinstance<type>(src)) {
             return false;
+        }
         value = reinterpret_borrow<type>(src);
         return true;
     }
@@ -1636,7 +938,7 @@ struct pyobject_caster {
 };
 
 template <typename T>
-class type_caster<T, enable_if_t<is_pyobject<T>::value>> : public pyobject_caster<T> { };
+class type_caster<T, enable_if_t<is_pyobject<T>::value>> : public pyobject_caster<T> {};
 
 // Our conditions for enabling moving are quite restrictive:
 // At compile time:
@@ -1647,65 +949,83 @@ class type_caster<T, enable_if_t<is_pyobject<T>::value>> : public pyobject_caste
 // - if the type is non-copy-constructible, the object must be the sole owner of the type (i.e. it
 //   must have ref_count() == 1)h
 // If any of the above are not satisfied, we fall back to copying.
-template <typename T> using move_is_plain_type = satisfies_none_of<T,
-    std::is_void, std::is_pointer, std::is_reference, std::is_const
->;
-template <typename T, typename SFINAE = void> struct move_always : std::false_type {};
-template <typename T> struct move_always<T, enable_if_t<all_of<
-    move_is_plain_type<T>,
-    negation<is_copy_constructible<T>>,
-    std::is_move_constructible<T>,
-    std::is_same<decltype(std::declval<make_caster<T>>().operator T&()), T&>
->::value>> : std::true_type {};
-template <typename T, typename SFINAE = void> struct move_if_unreferenced : std::false_type {};
-template <typename T> struct move_if_unreferenced<T, enable_if_t<all_of<
-    move_is_plain_type<T>,
-    negation<move_always<T>>,
-    std::is_move_constructible<T>,
-    std::is_same<decltype(std::declval<make_caster<T>>().operator T&()), T&>
->::value>> : std::true_type {};
-template <typename T> using move_never = none_of<move_always<T>, move_if_unreferenced<T>>;
+template <typename T>
+using move_is_plain_type
+    = satisfies_none_of<T, std::is_void, std::is_pointer, std::is_reference, std::is_const>;
+template <typename T, typename SFINAE = void>
+struct move_always : std::false_type {};
+template <typename T>
+struct move_always<
+    T,
+    enable_if_t<
+        all_of<move_is_plain_type<T>,
+               negation<is_copy_constructible<T>>,
+               std::is_move_constructible<T>,
+               std::is_same<decltype(std::declval<make_caster<T>>().operator T &()), T &>>::value>>
+    : std::true_type {};
+template <typename T, typename SFINAE = void>
+struct move_if_unreferenced : std::false_type {};
+template <typename T>
+struct move_if_unreferenced<
+    T,
+    enable_if_t<
+        all_of<move_is_plain_type<T>,
+               negation<move_always<T>>,
+               std::is_move_constructible<T>,
+               std::is_same<decltype(std::declval<make_caster<T>>().operator T &()), T &>>::value>>
+    : std::true_type {};
+template <typename T>
+using move_never = none_of<move_always<T>, move_if_unreferenced<T>>;
 
 // Detect whether returning a `type` from a cast on type's type_caster is going to result in a
 // reference or pointer to a local variable of the type_caster.  Basically, only
 // non-reference/pointer `type`s and reference/pointers from a type_caster_generic are safe;
 // everything else returns a reference/pointer to a local variable.
-template <typename type> using cast_is_temporary_value_reference = bool_constant<
-    (std::is_reference<type>::value || std::is_pointer<type>::value) &&
-    !std::is_base_of<type_caster_generic, make_caster<type>>::value &&
-    !std::is_same<intrinsic_t<type>, void>::value
->;
+template <typename type>
+using cast_is_temporary_value_reference
+    = bool_constant<(std::is_reference<type>::value || std::is_pointer<type>::value)
+                    && !std::is_base_of<type_caster_generic, make_caster<type>>::value
+                    && !std::is_same<intrinsic_t<type>, void>::value>;
 
 // When a value returned from a C++ function is being cast back to Python, we almost always want to
 // force `policy = move`, regardless of the return value policy the function/method was declared
 // with.
-template <typename Return, typename SFINAE = void> struct return_value_policy_override {
+template <typename Return, typename SFINAE = void>
+struct return_value_policy_override {
     static return_value_policy policy(return_value_policy p) { return p; }
 };
 
-template <typename Return> struct return_value_policy_override<Return,
-        detail::enable_if_t<std::is_base_of<type_caster_generic, make_caster<Return>>::value, void>> {
+template <typename Return>
+struct return_value_policy_override<
+    Return,
+    detail::enable_if_t<std::is_base_of<type_caster_generic, make_caster<Return>>::value, void>> {
     static return_value_policy policy(return_value_policy p) {
-        return !std::is_lvalue_reference<Return>::value &&
-               !std::is_pointer<Return>::value
-                   ? return_value_policy::move : p;
+        return !std::is_lvalue_reference<Return>::value && !std::is_pointer<Return>::value
+                   ? return_value_policy::move
+                   : p;
     }
 };
 
 // Basic python -> C++ casting; throws if casting fails
-template <typename T, typename SFINAE> type_caster<T, SFINAE> &load_type(type_caster<T, SFINAE> &conv, const handle &handle) {
+template <typename T, typename SFINAE>
+type_caster<T, SFINAE> &load_type(type_caster<T, SFINAE> &conv, const handle &handle) {
+    static_assert(!detail::is_pyobject<T>::value,
+                  "Internal error: type_caster should only be used for C++ types");
     if (!conv.load(handle, true)) {
-#if defined(NDEBUG)
-        throw cast_error("Unable to cast Python instance to C++ type (compile in debug mode for details)");
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+        throw cast_error("Unable to cast Python instance to C++ type (#define "
+                         "PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)");
 #else
-        throw cast_error("Unable to cast Python instance of type " +
-            (std::string) str(type::handle_of(handle)) + " to C++ type '" + type_id<T>() + "'");
+        throw cast_error("Unable to cast Python instance of type "
+                         + (std::string) str(type::handle_of(handle)) + " to C++ type '"
+                         + type_id<T>() + "'");
 #endif
     }
     return conv;
 }
 // Wrapper around the above that also constructs and returns a type_caster
-template <typename T> make_caster<T> load_type(const handle &handle) {
+template <typename T>
+make_caster<T> load_type(const handle &handle) {
     make_caster<T> conv;
     load_type(conv, handle);
     return conv;
@@ -1718,44 +1038,60 @@ template <typename T, detail::enable_if_t<!detail::is_pyobject<T>::value, int> =
 T cast(const handle &handle) {
     using namespace detail;
     static_assert(!cast_is_temporary_value_reference<T>::value,
-            "Unable to cast type to reference: value is local to type caster");
+                  "Unable to cast type to reference: value is local to type caster");
     return cast_op<T>(load_type<T>(handle));
 }
 
 // pytype -> pytype (calls converting constructor)
 template <typename T, detail::enable_if_t<detail::is_pyobject<T>::value, int> = 0>
-T cast(const handle &handle) { return T(reinterpret_borrow<object>(handle)); }
+T cast(const handle &handle) {
+    return T(reinterpret_borrow<object>(handle));
+}
 
 // C++ type -> py::object
 template <typename T, detail::enable_if_t<!detail::is_pyobject<T>::value, int> = 0>
-object cast(T &&value, return_value_policy policy = return_value_policy::automatic_reference,
+object cast(T &&value,
+            return_value_policy policy = return_value_policy::automatic_reference,
             handle parent = handle()) {
     using no_ref_T = typename std::remove_reference<T>::type;
-    if (policy == return_value_policy::automatic)
-        policy = std::is_pointer<no_ref_T>::value ? return_value_policy::take_ownership :
-                 std::is_lvalue_reference<T>::value ? return_value_policy::copy : return_value_policy::move;
-    else if (policy == return_value_policy::automatic_reference)
-        policy = std::is_pointer<no_ref_T>::value ? return_value_policy::reference :
-                 std::is_lvalue_reference<T>::value ? return_value_policy::copy : return_value_policy::move;
-    return reinterpret_steal<object>(detail::make_caster<T>::cast(std::forward<T>(value), policy, parent));
+    if (policy == return_value_policy::automatic) {
+        policy = std::is_pointer<no_ref_T>::value     ? return_value_policy::take_ownership
+                 : std::is_lvalue_reference<T>::value ? return_value_policy::copy
+                                                      : return_value_policy::move;
+    } else if (policy == return_value_policy::automatic_reference) {
+        policy = std::is_pointer<no_ref_T>::value     ? return_value_policy::reference
+                 : std::is_lvalue_reference<T>::value ? return_value_policy::copy
+                                                      : return_value_policy::move;
+    }
+    return reinterpret_steal<object>(
+        detail::make_caster<T>::cast(std::forward<T>(value), policy, parent));
 }
 
-template <typename T> T handle::cast() const { return pybind11::cast<T>(*this); }
-template <> inline void handle::cast() const { return; }
+template <typename T>
+T handle::cast() const {
+    return pybind11::cast<T>(*this);
+}
+template <>
+inline void handle::cast() const {
+    return;
+}
 
 template <typename T>
 detail::enable_if_t<!detail::move_never<T>::value, T> move(object &&obj) {
-    if (obj.ref_count() > 1)
-#if defined(NDEBUG)
-        throw cast_error("Unable to cast Python instance to C++ rvalue: instance has multiple references"
-            " (compile in debug mode for details)");
+    if (obj.ref_count() > 1) {
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+        throw cast_error(
+            "Unable to cast Python instance to C++ rvalue: instance has multiple references"
+            " (#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)");
 #else
-        throw cast_error("Unable to move from Python " + (std::string) str(type::handle_of(obj)) +
-                " instance to C++ " + type_id<T>() + " instance: instance has multiple references");
+        throw cast_error("Unable to move from Python " + (std::string) str(type::handle_of(obj))
+                         + " instance to C++ " + type_id<T>()
+                         + " instance: instance has multiple references");
 #endif
+    }
 
     // Move into a temporary and return that, because the reference may be a local value of `conv`
-    T ret = std::move(detail::load_type<T>(obj).operator T&());
+    T ret = std::move(detail::load_type<T>(obj).operator T &());
     return ret;
 }
 
@@ -1764,96 +1100,164 @@ detail::enable_if_t<!detail::move_never<T>::value, T> move(object &&obj) {
 //   object has multiple references, but trying to copy will fail to compile.
 // - If both movable and copyable, check ref count: if 1, move; otherwise copy
 // - Otherwise (not movable), copy.
-template <typename T> detail::enable_if_t<detail::move_always<T>::value, T> cast(object &&object) {
+template <typename T>
+detail::enable_if_t<!detail::is_pyobject<T>::value && detail::move_always<T>::value, T>
+cast(object &&object) {
     return move<T>(std::move(object));
 }
-template <typename T> detail::enable_if_t<detail::move_if_unreferenced<T>::value, T> cast(object &&object) {
-    if (object.ref_count() > 1)
+template <typename T>
+detail::enable_if_t<!detail::is_pyobject<T>::value && detail::move_if_unreferenced<T>::value, T>
+cast(object &&object) {
+    if (object.ref_count() > 1) {
         return cast<T>(object);
-    else
-        return move<T>(std::move(object));
+    }
+    return move<T>(std::move(object));
 }
-template <typename T> detail::enable_if_t<detail::move_never<T>::value, T> cast(object &&object) {
+template <typename T>
+detail::enable_if_t<!detail::is_pyobject<T>::value && detail::move_never<T>::value, T>
+cast(object &&object) {
     return cast<T>(object);
 }
 
-template <typename T> T object::cast() const & { return pybind11::cast<T>(*this); }
-template <typename T> T object::cast() && { return pybind11::cast<T>(std::move(*this)); }
-template <> inline void object::cast() const & { return; }
-template <> inline void object::cast() && { return; }
+// pytype rvalue -> pytype (calls converting constructor)
+template <typename T>
+detail::enable_if_t<detail::is_pyobject<T>::value, T> cast(object &&object) {
+    return T(std::move(object));
+}
+
+template <typename T>
+T object::cast() const & {
+    return pybind11::cast<T>(*this);
+}
+template <typename T>
+T object::cast() && {
+    return pybind11::cast<T>(std::move(*this));
+}
+template <>
+inline void object::cast() const & {
+    return;
+}
+template <>
+inline void object::cast() && {
+    return;
+}
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 // Declared in pytypes.h:
 template <typename T, enable_if_t<!is_pyobject<T>::value, int>>
-object object_or_cast(T &&o) { return pybind11::cast(std::forward<T>(o)); }
+object object_or_cast(T &&o) {
+    return pybind11::cast(std::forward<T>(o));
+}
 
-struct override_unused {}; // Placeholder type for the unneeded (and dead code) static variable in the PYBIND11_OVERRIDE_OVERRIDE macro
-template <typename ret_type> using override_caster_t = conditional_t<
-    cast_is_temporary_value_reference<ret_type>::value, make_caster<ret_type>, override_unused>;
+// Placeholder type for the unneeded (and dead code) static variable in the
+// PYBIND11_OVERRIDE_OVERRIDE macro
+struct override_unused {};
+template <typename ret_type>
+using override_caster_t = conditional_t<cast_is_temporary_value_reference<ret_type>::value,
+                                        make_caster<ret_type>,
+                                        override_unused>;
 
 // Trampoline use: for reference/pointer types to value-converted values, we do a value cast, then
 // store the result in the given variable.  For other types, this is a no-op.
-template <typename T> enable_if_t<cast_is_temporary_value_reference<T>::value, T> cast_ref(object &&o, make_caster<T> &caster) {
+template <typename T>
+enable_if_t<cast_is_temporary_value_reference<T>::value, T> cast_ref(object &&o,
+                                                                     make_caster<T> &caster) {
     return cast_op<T>(load_type(caster, o));
 }
-template <typename T> enable_if_t<!cast_is_temporary_value_reference<T>::value, T> cast_ref(object &&, override_unused &) {
-    pybind11_fail("Internal error: cast_ref fallback invoked"); }
-
-// Trampoline use: Having a pybind11::cast with an invalid reference type is going to static_assert, even
-// though if it's in dead code, so we provide a "trampoline" to pybind11::cast that only does anything in
-// cases where pybind11::cast is valid.
-template <typename T> enable_if_t<!cast_is_temporary_value_reference<T>::value, T> cast_safe(object &&o) {
-    return pybind11::cast<T>(std::move(o)); }
-template <typename T> enable_if_t<cast_is_temporary_value_reference<T>::value, T> cast_safe(object &&) {
-    pybind11_fail("Internal error: cast_safe fallback invoked"); }
-template <> inline void cast_safe<void>(object &&) {}
+template <typename T>
+enable_if_t<!cast_is_temporary_value_reference<T>::value, T> cast_ref(object &&,
+                                                                      override_unused &) {
+    pybind11_fail("Internal error: cast_ref fallback invoked");
+}
+
+// Trampoline use: Having a pybind11::cast with an invalid reference type is going to
+// static_assert, even though if it's in dead code, so we provide a "trampoline" to pybind11::cast
+// that only does anything in cases where pybind11::cast is valid.
+template <typename T>
+enable_if_t<cast_is_temporary_value_reference<T>::value, T> cast_safe(object &&) {
+    pybind11_fail("Internal error: cast_safe fallback invoked");
+}
+template <typename T>
+enable_if_t<std::is_same<void, intrinsic_t<T>>::value, void> cast_safe(object &&) {}
+template <typename T>
+enable_if_t<detail::none_of<cast_is_temporary_value_reference<T>,
+                            std::is_same<void, intrinsic_t<T>>>::value,
+            T>
+cast_safe(object &&o) {
+    return pybind11::cast<T>(std::move(o));
+}
 
 PYBIND11_NAMESPACE_END(detail)
 
+// The overloads could coexist, i.e. the #if is not strictly speaking needed,
+// but it is an easy minor optimization.
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+inline cast_error cast_error_unable_to_convert_call_arg() {
+    return cast_error("Unable to convert call argument to Python object (#define "
+                      "PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)");
+}
+#else
+inline cast_error cast_error_unable_to_convert_call_arg(const std::string &name,
+                                                        const std::string &type) {
+    return cast_error("Unable to convert call argument '" + name + "' of type '" + type
+                      + "' to Python object");
+}
+#endif
+
 template <return_value_policy policy = return_value_policy::automatic_reference>
-tuple make_tuple() { return tuple(0); }
+tuple make_tuple() {
+    return tuple(0);
+}
 
-template <return_value_policy policy = return_value_policy::automatic_reference,
-          typename... Args> tuple make_tuple(Args&&... args_) {
+template <return_value_policy policy = return_value_policy::automatic_reference, typename... Args>
+tuple make_tuple(Args &&...args_) {
     constexpr size_t size = sizeof...(Args);
-    std::array<object, size> args {
-        { reinterpret_steal<object>(detail::make_caster<Args>::cast(
-            std::forward<Args>(args_), policy, nullptr))... }
-    };
+    std::array<object, size> args{{reinterpret_steal<object>(
+        detail::make_caster<Args>::cast(std::forward<Args>(args_), policy, nullptr))...}};
     for (size_t i = 0; i < args.size(); i++) {
         if (!args[i]) {
-#if defined(NDEBUG)
-            throw cast_error("make_tuple(): unable to convert arguments to Python object (compile in debug mode for details)");
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+            throw cast_error_unable_to_convert_call_arg();
 #else
-            std::array<std::string, size> argtypes { {type_id<Args>()...} };
-            throw cast_error("make_tuple(): unable to convert argument of type '" +
-                argtypes[i] + "' to Python object");
+            std::array<std::string, size> argtypes{{type_id<Args>()...}};
+            throw cast_error_unable_to_convert_call_arg(std::to_string(i), argtypes[i]);
 #endif
         }
     }
     tuple result(size);
     int counter = 0;
-    for (auto &arg_value : args)
+    for (auto &arg_value : args) {
         PyTuple_SET_ITEM(result.ptr(), counter++, arg_value.release().ptr());
+    }
     return result;
 }
 
 /// \ingroup annotations
 /// Annotation for arguments
 struct arg {
-    /// Constructs an argument with the name of the argument; if null or omitted, this is a positional argument.
-    constexpr explicit arg(const char *name = nullptr) : name(name), flag_noconvert(false), flag_none(true) { }
+    /// Constructs an argument with the name of the argument; if null or omitted, this is a
+    /// positional argument.
+    constexpr explicit arg(const char *name = nullptr)
+        : name(name), flag_noconvert(false), flag_none(true) {}
     /// Assign a value to this argument
-    template <typename T> arg_v operator=(T &&value) const;
+    template <typename T>
+    arg_v operator=(T &&value) const;
     /// Indicate that the type should not be converted in the type caster
-    arg &noconvert(bool flag = true) { flag_noconvert = flag; return *this; }
+    arg &noconvert(bool flag = true) {
+        flag_noconvert = flag;
+        return *this;
+    }
     /// Indicates that the argument should/shouldn't allow None (e.g. for nullable pointer args)
-    arg &none(bool flag = true) { flag_none = flag; return *this; }
+    arg &none(bool flag = true) {
+        flag_none = flag;
+        return *this;
+    }
 
-    const char *name; ///< If non-null, this is a named kwargs argument
-    bool flag_noconvert : 1; ///< If set, do not allow conversion (requires a supporting type caster!)
-    bool flag_none : 1; ///< If set (the default), allow None to be passed to this argument
+    const char *name;        ///< If non-null, this is a named kwargs argument
+    bool flag_noconvert : 1; ///< If set, do not allow conversion (requires a supporting type
+                             ///< caster!)
+    bool flag_none : 1;      ///< If set (the default), allow None to be passed to this argument
 };
 
 /// \ingroup annotations
@@ -1862,58 +1266,73 @@ struct arg_v : arg {
 private:
     template <typename T>
     arg_v(arg &&base, T &&x, const char *descr = nullptr)
-        : arg(base),
-          value(reinterpret_steal<object>(
-              detail::make_caster<T>::cast(x, return_value_policy::automatic, {})
-          )),
+        : arg(base), value(reinterpret_steal<object>(detail::make_caster<T>::cast(
+                         std::forward<T>(x), return_value_policy::automatic, {}))),
           descr(descr)
-#if !defined(NDEBUG)
-        , type(type_id<T>())
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+          ,
+          type(type_id<T>())
 #endif
-    { }
+    {
+        // Workaround! See:
+        // https://github.com/pybind/pybind11/issues/2336
+        // https://github.com/pybind/pybind11/pull/2685#issuecomment-731286700
+        if (PyErr_Occurred()) {
+            PyErr_Clear();
+        }
+    }
 
 public:
     /// Direct construction with name, default, and description
     template <typename T>
     arg_v(const char *name, T &&x, const char *descr = nullptr)
-        : arg_v(arg(name), std::forward<T>(x), descr) { }
+        : arg_v(arg(name), std::forward<T>(x), descr) {}
 
     /// Called internally when invoking `py::arg("a") = value`
     template <typename T>
     arg_v(const arg &base, T &&x, const char *descr = nullptr)
-        : arg_v(arg(base), std::forward<T>(x), descr) { }
+        : arg_v(arg(base), std::forward<T>(x), descr) {}
 
     /// Same as `arg::noconvert()`, but returns *this as arg_v&, not arg&
-    arg_v &noconvert(bool flag = true) { arg::noconvert(flag); return *this; }
+    arg_v &noconvert(bool flag = true) {
+        arg::noconvert(flag);
+        return *this;
+    }
 
     /// Same as `arg::nonone()`, but returns *this as arg_v&, not arg&
-    arg_v &none(bool flag = true) { arg::none(flag); return *this; }
+    arg_v &none(bool flag = true) {
+        arg::none(flag);
+        return *this;
+    }
 
     /// The default value
     object value;
     /// The (optional) description of the default value
     const char *descr;
-#if !defined(NDEBUG)
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
     /// The C++ type name of the default value (only available when compiled in debug mode)
     std::string type;
 #endif
 };
 
 /// \ingroup annotations
-/// Annotation indicating that all following arguments are keyword-only; the is the equivalent of an
-/// unnamed '*' argument (in Python 3)
+/// Annotation indicating that all following arguments are keyword-only; the is the equivalent of
+/// an unnamed '*' argument
 struct kw_only {};
 
 /// \ingroup annotations
-/// Annotation indicating that all previous arguments are positional-only; the is the equivalent of an
-/// unnamed '/' argument (in Python 3.8)
+/// Annotation indicating that all previous arguments are positional-only; the is the equivalent of
+/// an unnamed '/' argument (in Python 3.8)
 struct pos_only {};
 
 template <typename T>
-arg_v arg::operator=(T &&value) const { return {std::move(*this), std::forward<T>(value)}; }
+arg_v arg::operator=(T &&value) const {
+    return {*this, std::forward<T>(value)};
+}
 
 /// Alias for backward compatibility -- to be removed in version 2.0
-template <typename /*unused*/> using arg_t = arg_v;
+template <typename /*unused*/>
+using arg_t = arg_v;
 
 inline namespace literals {
 /** \rst
@@ -1924,6 +1343,11 @@ constexpr arg operator"" _a(const char *name, size_t) { return arg(name); }
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
+template <typename T>
+using is_kw_only = std::is_same<intrinsic_t<T>, kw_only>;
+template <typename T>
+using is_pos_only = std::is_same<intrinsic_t<T>, pos_only>;
+
 // forward declaration (definition in attr.h)
 struct function_record;
 
@@ -1951,56 +1375,63 @@ struct function_call {
     handle init_self;
 };
 
-
 /// Helper class which loads arguments for C++ functions called from Python
 template <typename... Args>
 class argument_loader {
     using indices = make_index_sequence<sizeof...(Args)>;
 
-    template <typename Arg> using argument_is_args   = std::is_same<intrinsic_t<Arg>, args>;
-    template <typename Arg> using argument_is_kwargs = std::is_same<intrinsic_t<Arg>, kwargs>;
-    // Get args/kwargs argument positions relative to the end of the argument list:
-    static constexpr auto args_pos = constexpr_first<argument_is_args, Args...>() - (int) sizeof...(Args),
-                        kwargs_pos = constexpr_first<argument_is_kwargs, Args...>() - (int) sizeof...(Args);
-
-    static constexpr bool args_kwargs_are_last = kwargs_pos >= - 1 && args_pos >= kwargs_pos - 1;
+    template <typename Arg>
+    using argument_is_args = std::is_same<intrinsic_t<Arg>, args>;
+    template <typename Arg>
+    using argument_is_kwargs = std::is_same<intrinsic_t<Arg>, kwargs>;
+    // Get kwargs argument position, or -1 if not present:
+    static constexpr auto kwargs_pos = constexpr_last<argument_is_kwargs, Args...>();
 
-    static_assert(args_kwargs_are_last, "py::args/py::kwargs are only permitted as the last argument(s) of a function");
+    static_assert(kwargs_pos == -1 || kwargs_pos == (int) sizeof...(Args) - 1,
+                  "py::kwargs is only permitted as the last argument of a function");
 
 public:
-    static constexpr bool has_kwargs = kwargs_pos < 0;
-    static constexpr bool has_args = args_pos < 0;
+    static constexpr bool has_kwargs = kwargs_pos != -1;
+
+    // py::args argument position; -1 if not present.
+    static constexpr int args_pos = constexpr_last<argument_is_args, Args...>();
+
+    static_assert(args_pos == -1 || args_pos == constexpr_first<argument_is_args, Args...>(),
+                  "py::args cannot be specified more than once");
 
     static constexpr auto arg_names = concat(type_descr(make_caster<Args>::name)...);
 
-    bool load_args(function_call &call) {
-        return load_impl_sequence(call, indices{});
-    }
+    bool load_args(function_call &call) { return load_impl_sequence(call, indices{}); }
 
     template <typename Return, typename Guard, typename Func>
+    // NOLINTNEXTLINE(readability-const-return-type)
     enable_if_t<!std::is_void<Return>::value, Return> call(Func &&f) && {
-        return std::move(*this).template call_impl<Return>(std::forward<Func>(f), indices{}, Guard{});
+        return std::move(*this).template call_impl<remove_cv_t<Return>>(
+            std::forward<Func>(f), indices{}, Guard{});
     }
 
     template <typename Return, typename Guard, typename Func>
     enable_if_t<std::is_void<Return>::value, void_type> call(Func &&f) && {
-        std::move(*this).template call_impl<Return>(std::forward<Func>(f), indices{}, Guard{});
+        std::move(*this).template call_impl<remove_cv_t<Return>>(
+            std::forward<Func>(f), indices{}, Guard{});
         return void_type();
     }
 
 private:
-
     static bool load_impl_sequence(function_call &, index_sequence<>) { return true; }
 
     template <size_t... Is>
     bool load_impl_sequence(function_call &call, index_sequence<Is...>) {
 #ifdef __cpp_fold_expressions
-        if ((... || !std::get<Is>(argcasters).load(call.args[Is], call.args_convert[Is])))
+        if ((... || !std::get<Is>(argcasters).load(call.args[Is], call.args_convert[Is]))) {
             return false;
+        }
 #else
-        for (bool r : {std::get<Is>(argcasters).load(call.args[Is], call.args_convert[Is])...})
-            if (!r)
+        for (bool r : {std::get<Is>(argcasters).load(call.args[Is], call.args_convert[Is])...}) {
+            if (!r) {
                 return false;
+            }
+        }
 #endif
         return true;
     }
@@ -2020,7 +1451,7 @@ class simple_collector {
 public:
     template <typename... Ts>
     explicit simple_collector(Ts &&...values)
-        : m_args(pybind11::make_tuple<policy>(std::forward<Ts>(values)...)) { }
+        : m_args(pybind11::make_tuple<policy>(std::forward<Ts>(values)...)) {}
 
     const tuple &args() const & { return m_args; }
     dict kwargs() const { return {}; }
@@ -2030,8 +1461,9 @@ class simple_collector {
     /// Call a Python function and pass the collected arguments
     object call(PyObject *ptr) const {
         PyObject *result = PyObject_CallObject(ptr, m_args.ptr());
-        if (!result)
+        if (!result) {
             throw error_already_set();
+        }
         return reinterpret_steal<object>(result);
     }
 
@@ -2048,8 +1480,8 @@ class unpacking_collector {
         // Tuples aren't (easily) resizable so a list is needed for collection,
         // but the actual function call strictly requires a tuple.
         auto args_list = list();
-        int _[] = { 0, (process(args_list, std::forward<Ts>(values)), 0)... };
-        ignore_unused(_);
+        using expander = int[];
+        (void) expander{0, (process(args_list, std::forward<Ts>(values)), 0)...};
 
         m_args = std::move(args_list);
     }
@@ -2063,61 +1495,66 @@ class unpacking_collector {
     /// Call a Python function and pass the collected arguments
     object call(PyObject *ptr) const {
         PyObject *result = PyObject_Call(ptr, m_args.ptr(), m_kwargs.ptr());
-        if (!result)
+        if (!result) {
             throw error_already_set();
+        }
         return reinterpret_steal<object>(result);
     }
 
 private:
     template <typename T>
     void process(list &args_list, T &&x) {
-        auto o = reinterpret_steal<object>(detail::make_caster<T>::cast(std::forward<T>(x), policy, {}));
+        auto o = reinterpret_steal<object>(
+            detail::make_caster<T>::cast(std::forward<T>(x), policy, {}));
         if (!o) {
-#if defined(NDEBUG)
-            argument_cast_error();
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+            throw cast_error_unable_to_convert_call_arg();
 #else
-            argument_cast_error(std::to_string(args_list.size()), type_id<T>());
+            throw cast_error_unable_to_convert_call_arg(std::to_string(args_list.size()),
+                                                        type_id<T>());
 #endif
         }
-        args_list.append(o);
+        args_list.append(std::move(o));
     }
 
     void process(list &args_list, detail::args_proxy ap) {
-        for (auto a : ap)
+        for (auto a : ap) {
             args_list.append(a);
+        }
     }
 
-    void process(list &/*args_list*/, arg_v a) {
-        if (!a.name)
-#if defined(NDEBUG)
+    void process(list & /*args_list*/, arg_v a) {
+        if (!a.name) {
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
             nameless_argument_error();
 #else
             nameless_argument_error(a.type);
 #endif
-
+        }
         if (m_kwargs.contains(a.name)) {
-#if defined(NDEBUG)
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
             multiple_values_error();
 #else
             multiple_values_error(a.name);
 #endif
         }
         if (!a.value) {
-#if defined(NDEBUG)
-            argument_cast_error();
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+            throw cast_error_unable_to_convert_call_arg();
 #else
-            argument_cast_error(a.name, a.type);
+            throw cast_error_unable_to_convert_call_arg(a.name, a.type);
 #endif
         }
         m_kwargs[a.name] = a.value;
     }
 
-    void process(list &/*args_list*/, detail::kwargs_proxy kp) {
-        if (!kp)
+    void process(list & /*args_list*/, detail::kwargs_proxy kp) {
+        if (!kp) {
             return;
+        }
         for (auto k : reinterpret_borrow<dict>(kp)) {
             if (m_kwargs.contains(k.first)) {
-#if defined(NDEBUG)
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
                 multiple_values_error();
 #else
                 multiple_values_error(str(k.first));
@@ -2128,62 +1565,71 @@ class unpacking_collector {
     }
 
     [[noreturn]] static void nameless_argument_error() {
-        throw type_error("Got kwargs without a name; only named arguments "
-                         "may be passed via py::arg() to a python function call. "
-                         "(compile in debug mode for details)");
+        throw type_error(
+            "Got kwargs without a name; only named arguments "
+            "may be passed via py::arg() to a python function call. "
+            "(#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)");
     }
-    [[noreturn]] static void nameless_argument_error(std::string type) {
-        throw type_error("Got kwargs without a name of type '" + type + "'; only named "
-                         "arguments may be passed via py::arg() to a python function call. ");
+    [[noreturn]] static void nameless_argument_error(const std::string &type) {
+        throw type_error("Got kwargs without a name of type '" + type
+                         + "'; only named "
+                           "arguments may be passed via py::arg() to a python function call. ");
     }
     [[noreturn]] static void multiple_values_error() {
-        throw type_error("Got multiple values for keyword argument "
-                         "(compile in debug mode for details)");
+        throw type_error(
+            "Got multiple values for keyword argument "
+            "(#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)");
     }
 
-    [[noreturn]] static void multiple_values_error(std::string name) {
+    [[noreturn]] static void multiple_values_error(const std::string &name) {
         throw type_error("Got multiple values for keyword argument '" + name + "'");
     }
 
-    [[noreturn]] static void argument_cast_error() {
-        throw cast_error("Unable to convert call argument to Python object "
-                         "(compile in debug mode for details)");
-    }
-
-    [[noreturn]] static void argument_cast_error(std::string name, std::string type) {
-        throw cast_error("Unable to convert call argument '" + name
-                         + "' of type '" + type + "' to Python object");
-    }
-
 private:
     tuple m_args;
     dict m_kwargs;
 };
 
+// [workaround(intel)] Separate function required here
+// We need to put this into a separate function because the Intel compiler
+// fails to compile enable_if_t<!all_of<is_positional<Args>...>::value>
+// (tested with ICC 2021.1 Beta 20200827).
+template <typename... Args>
+constexpr bool args_are_all_positional() {
+    return all_of<is_positional<Args>...>::value;
+}
+
 /// Collect only positional arguments for a Python function call
-template <return_value_policy policy, typename... Args,
-          typename = enable_if_t<all_of<is_positional<Args>...>::value>>
+template <return_value_policy policy,
+          typename... Args,
+          typename = enable_if_t<args_are_all_positional<Args...>()>>
 simple_collector<policy> collect_arguments(Args &&...args) {
     return simple_collector<policy>(std::forward<Args>(args)...);
 }
 
 /// Collect all arguments, including keywords and unpacking (only instantiated when needed)
-template <return_value_policy policy, typename... Args,
-          typename = enable_if_t<!all_of<is_positional<Args>...>::value>>
+template <return_value_policy policy,
+          typename... Args,
+          typename = enable_if_t<!args_are_all_positional<Args...>()>>
 unpacking_collector<policy> collect_arguments(Args &&...args) {
     // Following argument order rules for generalized unpacking according to PEP 448
-    static_assert(
-        constexpr_last<is_positional, Args...>() < constexpr_first<is_keyword_or_ds, Args...>()
-        && constexpr_last<is_s_unpacking, Args...>() < constexpr_first<is_ds_unpacking, Args...>(),
-        "Invalid function call: positional args must precede keywords and ** unpacking; "
-        "* unpacking must precede ** unpacking"
-    );
+    static_assert(constexpr_last<is_positional, Args...>()
+                          < constexpr_first<is_keyword_or_ds, Args...>()
+                      && constexpr_last<is_s_unpacking, Args...>()
+                             < constexpr_first<is_ds_unpacking, Args...>(),
+                  "Invalid function call: positional args must precede keywords and ** unpacking; "
+                  "* unpacking must precede ** unpacking");
     return unpacking_collector<policy>(std::forward<Args>(args)...);
 }
 
 template <typename Derived>
 template <return_value_policy policy, typename... Args>
 object object_api<Derived>::operator()(Args &&...args) const {
+#ifndef NDEBUG
+    if (!PyGILState_Check()) {
+        pybind11_fail("pybind11::object_api<>::operator() PyGILState_Check() failure.");
+    }
+#endif
     return detail::collect_arguments<policy>(std::forward<Args>(args)...).call(derived().ptr());
 }
 
@@ -2195,25 +1641,25 @@ object object_api<Derived>::call(Args &&...args) const {
 
 PYBIND11_NAMESPACE_END(detail)
 
-
-template<typename T>
+template <typename T>
 handle type::handle_of() {
-   static_assert(
-      std::is_base_of<detail::type_caster_generic, detail::make_caster<T>>::value,
-      "py::type::of<T> only supports the case where T is a registered C++ types."
-    );
+    static_assert(std::is_base_of<detail::type_caster_generic, detail::make_caster<T>>::value,
+                  "py::type::of<T> only supports the case where T is a registered C++ types.");
 
     return detail::get_type_handle(typeid(T), true);
 }
 
-
-#define PYBIND11_MAKE_OPAQUE(...) \
-    namespace pybind11 { namespace detail { \
-        template<> class type_caster<__VA_ARGS__> : public type_caster_base<__VA_ARGS__> { }; \
-    }}
+#define PYBIND11_MAKE_OPAQUE(...)                                                                 \
+    PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)                                                  \
+    namespace detail {                                                                            \
+    template <>                                                                                   \
+    class type_caster<__VA_ARGS__> : public type_caster_base<__VA_ARGS__> {};                     \
+    }                                                                                             \
+    PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
 
 /// Lets you pass a type containing a `,` through a macro parameter without needing a separate
-/// typedef, e.g.: `PYBIND11_OVERRIDE(PYBIND11_TYPE(ReturnType<A, B>), PYBIND11_TYPE(Parent<C, D>), f, arg)`
+/// typedef, e.g.:
+/// `PYBIND11_OVERRIDE(PYBIND11_TYPE(ReturnType<A, B>), PYBIND11_TYPE(Parent<C, D>), f, arg)`
 #define PYBIND11_TYPE(...) __VA_ARGS__
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/chrono.h b/3rdparty/pybind11/include/pybind11/chrono.h
index c3681102da..167ea0e3d1 100644
--- a/3rdparty/pybind11/include/pybind11/chrono.h
+++ b/3rdparty/pybind11/include/pybind11/chrono.h
@@ -11,62 +11,63 @@
 #pragma once
 
 #include "pybind11.h"
+
+#include <chrono>
 #include <cmath>
 #include <ctime>
-#include <chrono>
 #include <datetime.h>
-
-// Backport the PyDateTime_DELTA functions from Python3.3 if required
-#ifndef PyDateTime_DELTA_GET_DAYS
-#define PyDateTime_DELTA_GET_DAYS(o)         (((PyDateTime_Delta*)o)->days)
-#endif
-#ifndef PyDateTime_DELTA_GET_SECONDS
-#define PyDateTime_DELTA_GET_SECONDS(o)      (((PyDateTime_Delta*)o)->seconds)
-#endif
-#ifndef PyDateTime_DELTA_GET_MICROSECONDS
-#define PyDateTime_DELTA_GET_MICROSECONDS(o) (((PyDateTime_Delta*)o)->microseconds)
-#endif
+#include <mutex>
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-template <typename type> class duration_caster {
+template <typename type>
+class duration_caster {
 public:
     using rep = typename type::rep;
     using period = typename type::period;
 
-    using days = std::chrono::duration<uint_fast32_t, std::ratio<86400>>;
+    // signed 25 bits required by the standard.
+    using days = std::chrono::duration<int_least32_t, std::ratio<86400>>;
 
     bool load(handle src, bool) {
         using namespace std::chrono;
 
         // Lazy initialise the PyDateTime import
-        if (!PyDateTimeAPI) { PyDateTime_IMPORT; }
+        if (!PyDateTimeAPI) {
+            PyDateTime_IMPORT;
+        }
 
-        if (!src) return false;
+        if (!src) {
+            return false;
+        }
         // If invoked with datetime.delta object
         if (PyDelta_Check(src.ptr())) {
             value = type(duration_cast<duration<rep, period>>(
-                  days(PyDateTime_DELTA_GET_DAYS(src.ptr()))
+                days(PyDateTime_DELTA_GET_DAYS(src.ptr()))
                 + seconds(PyDateTime_DELTA_GET_SECONDS(src.ptr()))
                 + microseconds(PyDateTime_DELTA_GET_MICROSECONDS(src.ptr()))));
             return true;
         }
         // If invoked with a float we assume it is seconds and convert
-        else if (PyFloat_Check(src.ptr())) {
-            value = type(duration_cast<duration<rep, period>>(duration<double>(PyFloat_AsDouble(src.ptr()))));
+        if (PyFloat_Check(src.ptr())) {
+            value = type(duration_cast<duration<rep, period>>(
+                duration<double>(PyFloat_AsDouble(src.ptr()))));
             return true;
         }
-        else return false;
+        return false;
     }
 
     // If this is a duration just return it back
-    static const std::chrono::duration<rep, period>& get_duration(const std::chrono::duration<rep, period> &src) {
+    static const std::chrono::duration<rep, period> &
+    get_duration(const std::chrono::duration<rep, period> &src) {
         return src;
     }
 
     // If this is a time_point get the time_since_epoch
-    template <typename Clock> static std::chrono::duration<rep, period> get_duration(const std::chrono::time_point<Clock, std::chrono::duration<rep, period>> &src) {
+    template <typename Clock>
+    static std::chrono::duration<rep, period>
+    get_duration(const std::chrono::time_point<Clock, std::chrono::duration<rep, period>> &src) {
         return src.time_since_epoch();
     }
 
@@ -78,9 +79,12 @@ template <typename type> class duration_caster {
         auto d = get_duration(src);
 
         // Lazy initialise the PyDateTime import
-        if (!PyDateTimeAPI) { PyDateTime_IMPORT; }
+        if (!PyDateTimeAPI) {
+            PyDateTime_IMPORT;
+        }
 
-        // Declare these special duration types so the conversions happen with the correct primitive types (int)
+        // Declare these special duration types so the conversions happen with the correct
+        // primitive types (int)
         using dd_t = duration<int, std::ratio<86400>>;
         using ss_t = duration<int, std::ratio<1>>;
         using us_t = duration<int, std::micro>;
@@ -92,79 +96,109 @@ template <typename type> class duration_caster {
         return PyDelta_FromDSU(dd.count(), ss.count(), us.count());
     }
 
-    PYBIND11_TYPE_CASTER(type, _("datetime.timedelta"));
+    PYBIND11_TYPE_CASTER(type, const_name("datetime.timedelta"));
 };
 
+inline std::tm *localtime_thread_safe(const std::time_t *time, std::tm *buf) {
+#if (defined(__STDC_LIB_EXT1__) && defined(__STDC_WANT_LIB_EXT1__)) || defined(_MSC_VER)
+    if (localtime_s(buf, time))
+        return nullptr;
+    return buf;
+#else
+    static std::mutex mtx;
+    std::lock_guard<std::mutex> lock(mtx);
+    std::tm *tm_ptr = std::localtime(time);
+    if (tm_ptr != nullptr) {
+        *buf = *tm_ptr;
+    }
+    return tm_ptr;
+#endif
+}
+
 // This is for casting times on the system clock into datetime.datetime instances
-template <typename Duration> class type_caster<std::chrono::time_point<std::chrono::system_clock, Duration>> {
+template <typename Duration>
+class type_caster<std::chrono::time_point<std::chrono::system_clock, Duration>> {
 public:
     using type = std::chrono::time_point<std::chrono::system_clock, Duration>;
     bool load(handle src, bool) {
         using namespace std::chrono;
 
         // Lazy initialise the PyDateTime import
-        if (!PyDateTimeAPI) { PyDateTime_IMPORT; }
+        if (!PyDateTimeAPI) {
+            PyDateTime_IMPORT;
+        }
 
-        if (!src) return false;
+        if (!src) {
+            return false;
+        }
 
         std::tm cal;
         microseconds msecs;
 
         if (PyDateTime_Check(src.ptr())) {
-            cal.tm_sec   = PyDateTime_DATE_GET_SECOND(src.ptr());
-            cal.tm_min   = PyDateTime_DATE_GET_MINUTE(src.ptr());
-            cal.tm_hour  = PyDateTime_DATE_GET_HOUR(src.ptr());
-            cal.tm_mday  = PyDateTime_GET_DAY(src.ptr());
-            cal.tm_mon   = PyDateTime_GET_MONTH(src.ptr()) - 1;
-            cal.tm_year  = PyDateTime_GET_YEAR(src.ptr()) - 1900;
+            cal.tm_sec = PyDateTime_DATE_GET_SECOND(src.ptr());
+            cal.tm_min = PyDateTime_DATE_GET_MINUTE(src.ptr());
+            cal.tm_hour = PyDateTime_DATE_GET_HOUR(src.ptr());
+            cal.tm_mday = PyDateTime_GET_DAY(src.ptr());
+            cal.tm_mon = PyDateTime_GET_MONTH(src.ptr()) - 1;
+            cal.tm_year = PyDateTime_GET_YEAR(src.ptr()) - 1900;
             cal.tm_isdst = -1;
-            msecs        = microseconds(PyDateTime_DATE_GET_MICROSECOND(src.ptr()));
+            msecs = microseconds(PyDateTime_DATE_GET_MICROSECOND(src.ptr()));
         } else if (PyDate_Check(src.ptr())) {
-            cal.tm_sec   = 0;
-            cal.tm_min   = 0;
-            cal.tm_hour  = 0;
-            cal.tm_mday  = PyDateTime_GET_DAY(src.ptr());
-            cal.tm_mon   = PyDateTime_GET_MONTH(src.ptr()) - 1;
-            cal.tm_year  = PyDateTime_GET_YEAR(src.ptr()) - 1900;
+            cal.tm_sec = 0;
+            cal.tm_min = 0;
+            cal.tm_hour = 0;
+            cal.tm_mday = PyDateTime_GET_DAY(src.ptr());
+            cal.tm_mon = PyDateTime_GET_MONTH(src.ptr()) - 1;
+            cal.tm_year = PyDateTime_GET_YEAR(src.ptr()) - 1900;
             cal.tm_isdst = -1;
-            msecs        = microseconds(0);
+            msecs = microseconds(0);
         } else if (PyTime_Check(src.ptr())) {
-            cal.tm_sec   = PyDateTime_TIME_GET_SECOND(src.ptr());
-            cal.tm_min   = PyDateTime_TIME_GET_MINUTE(src.ptr());
-            cal.tm_hour  = PyDateTime_TIME_GET_HOUR(src.ptr());
-            cal.tm_mday  = 1;   // This date (day, month, year) = (1, 0, 70)
-            cal.tm_mon   = 0;   // represents 1-Jan-1970, which is the first
-            cal.tm_year  = 70;  // earliest available date for Python's datetime
+            cal.tm_sec = PyDateTime_TIME_GET_SECOND(src.ptr());
+            cal.tm_min = PyDateTime_TIME_GET_MINUTE(src.ptr());
+            cal.tm_hour = PyDateTime_TIME_GET_HOUR(src.ptr());
+            cal.tm_mday = 1;  // This date (day, month, year) = (1, 0, 70)
+            cal.tm_mon = 0;   // represents 1-Jan-1970, which is the first
+            cal.tm_year = 70; // earliest available date for Python's datetime
             cal.tm_isdst = -1;
-            msecs        = microseconds(PyDateTime_TIME_GET_MICROSECOND(src.ptr()));
+            msecs = microseconds(PyDateTime_TIME_GET_MICROSECOND(src.ptr()));
+        } else {
+            return false;
         }
-        else return false;
 
         value = time_point_cast<Duration>(system_clock::from_time_t(std::mktime(&cal)) + msecs);
         return true;
     }
 
-    static handle cast(const std::chrono::time_point<std::chrono::system_clock, Duration> &src, return_value_policy /* policy */, handle /* parent */) {
+    static handle cast(const std::chrono::time_point<std::chrono::system_clock, Duration> &src,
+                       return_value_policy /* policy */,
+                       handle /* parent */) {
         using namespace std::chrono;
 
         // Lazy initialise the PyDateTime import
-        if (!PyDateTimeAPI) { PyDateTime_IMPORT; }
+        if (!PyDateTimeAPI) {
+            PyDateTime_IMPORT;
+        }
 
-        // Get out microseconds, and make sure they are positive, to avoid bug in eastern hemisphere time zones
-        // (cfr. https://github.com/pybind/pybind11/issues/2417)
+        // Get out microseconds, and make sure they are positive, to avoid bug in eastern
+        // hemisphere time zones (cfr. https://github.com/pybind/pybind11/issues/2417)
         using us_t = duration<int, std::micro>;
         auto us = duration_cast<us_t>(src.time_since_epoch() % seconds(1));
-        if (us.count() < 0)
+        if (us.count() < 0) {
             us += seconds(1);
+        }
 
         // Subtract microseconds BEFORE `system_clock::to_time_t`, because:
-        // > If std::time_t has lower precision, it is implementation-defined whether the value is rounded or truncated.
-        // (https://en.cppreference.com/w/cpp/chrono/system_clock/to_time_t)
-        std::time_t tt = system_clock::to_time_t(time_point_cast<system_clock::duration>(src - us));
-        // this function uses static memory so it's best to copy it out asap just in case
-        // otherwise other code that is using localtime may break this (not just python code)
-        std::tm localtime = *std::localtime(&tt);
-
+        // > If std::time_t has lower precision, it is implementation-defined whether the value is
+        // rounded or truncated. (https://en.cppreference.com/w/cpp/chrono/system_clock/to_time_t)
+        std::time_t tt
+            = system_clock::to_time_t(time_point_cast<system_clock::duration>(src - us));
+
+        std::tm localtime;
+        std::tm *localtime_ptr = localtime_thread_safe(&tt, &localtime);
+        if (!localtime_ptr) {
+            throw cast_error("Unable to represent system_clock in local time");
+        }
         return PyDateTime_FromDateAndTime(localtime.tm_year + 1900,
                                           localtime.tm_mon + 1,
                                           localtime.tm_mday,
@@ -173,19 +207,19 @@ template <typename Duration> class type_caster<std::chrono::time_point<std::chro
                                           localtime.tm_sec,
                                           us.count());
     }
-    PYBIND11_TYPE_CASTER(type, _("datetime.datetime"));
+    PYBIND11_TYPE_CASTER(type, const_name("datetime.datetime"));
 };
 
 // Other clocks that are not the system clock are not measured as datetime.datetime objects
 // since they are not measured on calendar time. So instead we just make them timedeltas
 // Or if they have passed us a time as a float we convert that
-template <typename Clock, typename Duration> class type_caster<std::chrono::time_point<Clock, Duration>>
-: public duration_caster<std::chrono::time_point<Clock, Duration>> {
-};
+template <typename Clock, typename Duration>
+class type_caster<std::chrono::time_point<Clock, Duration>>
+    : public duration_caster<std::chrono::time_point<Clock, Duration>> {};
 
-template <typename Rep, typename Period> class type_caster<std::chrono::duration<Rep, Period>>
-: public duration_caster<std::chrono::duration<Rep, Period>> {
-};
+template <typename Rep, typename Period>
+class type_caster<std::chrono::duration<Rep, Period>>
+    : public duration_caster<std::chrono::duration<Rep, Period>> {};
 
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/complex.h b/3rdparty/pybind11/include/pybind11/complex.h
index f8327eb373..8a831c12ce 100644
--- a/3rdparty/pybind11/include/pybind11/complex.h
+++ b/3rdparty/pybind11/include/pybind11/complex.h
@@ -10,42 +10,50 @@
 #pragma once
 
 #include "pybind11.h"
+
 #include <complex>
 
 /// glibc defines I as a macro which breaks things, e.g., boost template names
 #ifdef I
-#  undef I
+#    undef I
 #endif
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
-template <typename T> struct format_descriptor<std::complex<T>, detail::enable_if_t<std::is_floating_point<T>::value>> {
+template <typename T>
+struct format_descriptor<std::complex<T>, detail::enable_if_t<std::is_floating_point<T>::value>> {
     static constexpr const char c = format_descriptor<T>::c;
-    static constexpr const char value[3] = { 'Z', c, '\0' };
+    static constexpr const char value[3] = {'Z', c, '\0'};
     static std::string format() { return std::string(value); }
 };
 
 #ifndef PYBIND11_CPP17
 
-template <typename T> constexpr const char format_descriptor<
-    std::complex<T>, detail::enable_if_t<std::is_floating_point<T>::value>>::value[3];
+template <typename T>
+constexpr const char
+    format_descriptor<std::complex<T>,
+                      detail::enable_if_t<std::is_floating_point<T>::value>>::value[3];
 
 #endif
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-template <typename T> struct is_fmt_numeric<std::complex<T>, detail::enable_if_t<std::is_floating_point<T>::value>> {
+template <typename T>
+struct is_fmt_numeric<std::complex<T>, detail::enable_if_t<std::is_floating_point<T>::value>> {
     static constexpr bool value = true;
     static constexpr int index = is_fmt_numeric<T>::index + 3;
 };
 
-template <typename T> class type_caster<std::complex<T>> {
+template <typename T>
+class type_caster<std::complex<T>> {
 public:
     bool load(handle src, bool convert) {
-        if (!src)
+        if (!src) {
             return false;
-        if (!convert && !PyComplex_Check(src.ptr()))
+        }
+        if (!convert && !PyComplex_Check(src.ptr())) {
             return false;
+        }
         Py_complex result = PyComplex_AsCComplex(src.ptr());
         if (result.real == -1.0 && PyErr_Occurred()) {
             PyErr_Clear();
@@ -55,11 +63,12 @@ template <typename T> class type_caster<std::complex<T>> {
         return true;
     }
 
-    static handle cast(const std::complex<T> &src, return_value_policy /* policy */, handle /* parent */) {
+    static handle
+    cast(const std::complex<T> &src, return_value_policy /* policy */, handle /* parent */) {
         return PyComplex_FromDoubles((double) src.real(), (double) src.imag());
     }
 
-    PYBIND11_TYPE_CASTER(std::complex<T>, _("complex"));
+    PYBIND11_TYPE_CASTER(std::complex<T>, const_name("complex"));
 };
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/detail/class.h b/3rdparty/pybind11/include/pybind11/detail/class.h
index 65dad5a57e..a98e5e5414 100644
--- a/3rdparty/pybind11/include/pybind11/detail/class.h
+++ b/3rdparty/pybind11/include/pybind11/detail/class.h
@@ -15,13 +15,14 @@
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-#if PY_VERSION_HEX >= 0x03030000 && !defined(PYPY_VERSION)
-#  define PYBIND11_BUILTIN_QUALNAME
-#  define PYBIND11_SET_OLDPY_QUALNAME(obj, nameobj)
+#if !defined(PYPY_VERSION)
+#    define PYBIND11_BUILTIN_QUALNAME
+#    define PYBIND11_SET_OLDPY_QUALNAME(obj, nameobj)
 #else
-// In pre-3.3 Python, we still set __qualname__ so that we can produce reliable function type
-// signatures; in 3.3+ this macro expands to nothing:
-#  define PYBIND11_SET_OLDPY_QUALNAME(obj, nameobj) setattr((PyObject *) obj, "__qualname__", nameobj)
+// In PyPy, we still set __qualname__ so that we can produce reliable function type
+// signatures; in CPython this macro expands to nothing:
+#    define PYBIND11_SET_OLDPY_QUALNAME(obj, nameobj)                                             \
+        setattr((PyObject *) obj, "__qualname__", nameobj)
 #endif
 
 inline std::string get_fully_qualified_tp_name(PyTypeObject *type) {
@@ -65,24 +66,26 @@ inline PyTypeObject *make_static_property_type() {
        issue no Python C API calls which could potentially invoke the
        garbage collector (the GC will call type_traverse(), which will in
        turn find the newly constructed type in an invalid state) */
-    auto heap_type = (PyHeapTypeObject *) PyType_Type.tp_alloc(&PyType_Type, 0);
-    if (!heap_type)
+    auto *heap_type = (PyHeapTypeObject *) PyType_Type.tp_alloc(&PyType_Type, 0);
+    if (!heap_type) {
         pybind11_fail("make_static_property_type(): error allocating type!");
+    }
 
     heap_type->ht_name = name_obj.inc_ref().ptr();
-#ifdef PYBIND11_BUILTIN_QUALNAME
+#    ifdef PYBIND11_BUILTIN_QUALNAME
     heap_type->ht_qualname = name_obj.inc_ref().ptr();
-#endif
+#    endif
 
-    auto type = &heap_type->ht_type;
+    auto *type = &heap_type->ht_type;
     type->tp_name = name;
     type->tp_base = type_incref(&PyProperty_Type);
     type->tp_flags = Py_TPFLAGS_DEFAULT | Py_TPFLAGS_BASETYPE | Py_TPFLAGS_HEAPTYPE;
     type->tp_descr_get = pybind11_static_get;
     type->tp_descr_set = pybind11_static_set;
 
-    if (PyType_Ready(type) < 0)
+    if (PyType_Ready(type) < 0) {
         pybind11_fail("make_static_property_type(): failure in PyType_Ready()!");
+    }
 
     setattr((PyObject *) type, "__module__", str("pybind11_builtins"));
     PYBIND11_SET_OLDPY_QUALNAME(type, name_obj);
@@ -98,15 +101,17 @@ inline PyTypeObject *make_static_property_type() {
 inline PyTypeObject *make_static_property_type() {
     auto d = dict();
     PyObject *result = PyRun_String(R"(\
-        class pybind11_static_property(property):
-            def __get__(self, obj, cls):
-                return property.__get__(self, cls, cls)
-
-            def __set__(self, obj, value):
-                cls = obj if isinstance(obj, type) else type(obj)
-                property.__set__(self, cls, value)
-        )", Py_file_input, d.ptr(), d.ptr()
-    );
+class pybind11_static_property(property):
+    def __get__(self, obj, cls):
+        return property.__get__(self, cls, cls)
+
+    def __set__(self, obj, value):
+        cls = obj if isinstance(obj, type) else type(obj)
+        property.__set__(self, cls, value)
+)",
+                                    Py_file_input,
+                                    d.ptr(),
+                                    d.ptr());
     if (result == nullptr)
         throw error_already_set();
     Py_DECREF(result);
@@ -119,7 +124,7 @@ inline PyTypeObject *make_static_property_type() {
     By default, Python replaces the `static_property` itself, but for wrapped C++ types
     we need to call `static_property.__set__()` in order to propagate the new value to
     the underlying C++ data structure. */
-extern "C" inline int pybind11_meta_setattro(PyObject* obj, PyObject* name, PyObject* value) {
+extern "C" inline int pybind11_meta_setattro(PyObject *obj, PyObject *name, PyObject *value) {
     // Use `_PyType_Lookup()` instead of `PyObject_GetAttr()` in order to get the raw
     // descriptor (`property`) instead of calling `tp_descr_get` (`property.__get__()`).
     PyObject *descr = _PyType_Lookup((PyTypeObject *) obj, name);
@@ -128,9 +133,10 @@ extern "C" inline int pybind11_meta_setattro(PyObject* obj, PyObject* name, PyOb
     //   1. `Type.static_prop = value`             --> descr_set: `Type.static_prop.__set__(value)`
     //   2. `Type.static_prop = other_static_prop` --> setattro:  replace existing `static_prop`
     //   3. `Type.regular_attribute = value`       --> setattro:  regular attribute assignment
-    const auto static_prop = (PyObject *) get_internals().static_property_type;
-    const auto call_descr_set = descr && value && PyObject_IsInstance(descr, static_prop)
-                                && !PyObject_IsInstance(value, static_prop);
+    auto *const static_prop = (PyObject *) get_internals().static_property_type;
+    const auto call_descr_set = (descr != nullptr) && (value != nullptr)
+                                && (PyObject_IsInstance(descr, static_prop) != 0)
+                                && (PyObject_IsInstance(value, static_prop) == 0);
     if (call_descr_set) {
         // Call `static_property.__set__()` instead of replacing the `static_property`.
 #if !defined(PYPY_VERSION)
@@ -149,7 +155,6 @@ extern "C" inline int pybind11_meta_setattro(PyObject* obj, PyObject* name, PyOb
     }
 }
 
-#if PY_MAJOR_VERSION >= 3
 /**
  * Python 3's PyInstanceMethod_Type hides itself via its tp_descr_get, which prevents aliasing
  * methods via cls.attr("m2") = cls.attr("m1"): instead the tp_descr_get returns a plain function,
@@ -162,11 +167,8 @@ extern "C" inline PyObject *pybind11_meta_getattro(PyObject *obj, PyObject *name
         Py_INCREF(descr);
         return descr;
     }
-    else {
-        return PyType_Type.tp_getattro(obj, name);
-    }
+    return PyType_Type.tp_getattro(obj, name);
 }
-#endif
 
 /// metaclass `__call__` function that is used to create all pybind11 objects.
 extern "C" inline PyObject *pybind11_meta_call(PyObject *type, PyObject *args, PyObject *kwargs) {
@@ -178,12 +180,13 @@ extern "C" inline PyObject *pybind11_meta_call(PyObject *type, PyObject *args, P
     }
 
     // This must be a pybind11 instance
-    auto instance = reinterpret_cast<detail::instance *>(self);
+    auto *instance = reinterpret_cast<detail::instance *>(self);
 
     // Ensure that the base __init__ function(s) were called
     for (const auto &vh : values_and_holders(instance)) {
         if (!vh.holder_constructed()) {
-            PyErr_Format(PyExc_TypeError, "%.200s.__init__() must be called when overriding __init__",
+            PyErr_Format(PyExc_TypeError,
+                         "%.200s.__init__() must be called when overriding __init__",
                          get_fully_qualified_tp_name(vh.type->type).c_str());
             Py_DECREF(self);
             return nullptr;
@@ -202,27 +205,28 @@ extern "C" inline void pybind11_meta_dealloc(PyObject *obj) {
     // 1) be found in internals.registered_types_py
     // 2) have exactly one associated `detail::type_info`
     auto found_type = internals.registered_types_py.find(type);
-    if (found_type != internals.registered_types_py.end() &&
-        found_type->second.size() == 1 &&
-        found_type->second[0]->type == type) {
+    if (found_type != internals.registered_types_py.end() && found_type->second.size() == 1
+        && found_type->second[0]->type == type) {
 
         auto *tinfo = found_type->second[0];
         auto tindex = std::type_index(*tinfo->cpptype);
         internals.direct_conversions.erase(tindex);
 
-        if (tinfo->module_local)
-            registered_local_types_cpp().erase(tindex);
-        else
+        if (tinfo->module_local) {
+            get_local_internals().registered_types_cpp.erase(tindex);
+        } else {
             internals.registered_types_cpp.erase(tindex);
+        }
         internals.registered_types_py.erase(tinfo->type);
 
         // Actually just `std::erase_if`, but that's only available in C++20
         auto &cache = internals.inactive_override_cache;
-        for (auto it = cache.begin(), last = cache.end(); it != last; ) {
-            if (it->first == (PyObject *) tinfo->type)
+        for (auto it = cache.begin(), last = cache.end(); it != last;) {
+            if (it->first == (PyObject *) tinfo->type) {
                 it = cache.erase(it);
-            else
+            } else {
                 ++it;
+            }
         }
 
         delete tinfo;
@@ -234,7 +238,7 @@ extern "C" inline void pybind11_meta_dealloc(PyObject *obj) {
 /** This metaclass is assigned by default to all pybind11 types and is required in order
     for static properties to function correctly. Users may override this using `py::metaclass`.
     Return value: New reference. */
-inline PyTypeObject* make_default_metaclass() {
+inline PyTypeObject *make_default_metaclass() {
     constexpr auto *name = "pybind11_type";
     auto name_obj = reinterpret_steal<object>(PYBIND11_FROM_STRING(name));
 
@@ -242,16 +246,17 @@ inline PyTypeObject* make_default_metaclass() {
        issue no Python C API calls which could potentially invoke the
        garbage collector (the GC will call type_traverse(), which will in
        turn find the newly constructed type in an invalid state) */
-    auto heap_type = (PyHeapTypeObject *) PyType_Type.tp_alloc(&PyType_Type, 0);
-    if (!heap_type)
+    auto *heap_type = (PyHeapTypeObject *) PyType_Type.tp_alloc(&PyType_Type, 0);
+    if (!heap_type) {
         pybind11_fail("make_default_metaclass(): error allocating metaclass!");
+    }
 
     heap_type->ht_name = name_obj.inc_ref().ptr();
 #ifdef PYBIND11_BUILTIN_QUALNAME
     heap_type->ht_qualname = name_obj.inc_ref().ptr();
 #endif
 
-    auto type = &heap_type->ht_type;
+    auto *type = &heap_type->ht_type;
     type->tp_name = name;
     type->tp_base = type_incref(&PyType_Type);
     type->tp_flags = Py_TPFLAGS_DEFAULT | Py_TPFLAGS_BASETYPE | Py_TPFLAGS_HEAPTYPE;
@@ -259,14 +264,13 @@ inline PyTypeObject* make_default_metaclass() {
     type->tp_call = pybind11_meta_call;
 
     type->tp_setattro = pybind11_meta_setattro;
-#if PY_MAJOR_VERSION >= 3
     type->tp_getattro = pybind11_meta_getattro;
-#endif
 
     type->tp_dealloc = pybind11_meta_dealloc;
 
-    if (PyType_Ready(type) < 0)
+    if (PyType_Ready(type) < 0) {
         pybind11_fail("make_default_metaclass(): failure in PyType_Ready()!");
+    }
 
     setattr((PyObject *) type, "__module__", str("pybind11_builtins"));
     PYBIND11_SET_OLDPY_QUALNAME(type, name_obj);
@@ -276,16 +280,20 @@ inline PyTypeObject* make_default_metaclass() {
 
 /// For multiple inheritance types we need to recursively register/deregister base pointers for any
 /// base classes with pointers that are difference from the instance value pointer so that we can
-/// correctly recognize an offset base class pointer. This calls a function with any offset base ptrs.
-inline void traverse_offset_bases(void *valueptr, const detail::type_info *tinfo, instance *self,
-        bool (*f)(void * /*parentptr*/, instance * /*self*/)) {
+/// correctly recognize an offset base class pointer. This calls a function with any offset base
+/// ptrs.
+inline void traverse_offset_bases(void *valueptr,
+                                  const detail::type_info *tinfo,
+                                  instance *self,
+                                  bool (*f)(void * /*parentptr*/, instance * /*self*/)) {
     for (handle h : reinterpret_borrow<tuple>(tinfo->type->tp_bases)) {
-        if (auto parent_tinfo = get_type_info((PyTypeObject *) h.ptr())) {
+        if (auto *parent_tinfo = get_type_info((PyTypeObject *) h.ptr())) {
             for (auto &c : parent_tinfo->implicit_casts) {
                 if (c.first == tinfo->cpptype) {
                     auto *parentptr = c.second(valueptr);
-                    if (parentptr != valueptr)
+                    if (parentptr != valueptr) {
                         f(parentptr, self);
+                    }
                     traverse_offset_bases(parentptr, parent_tinfo, self, f);
                     break;
                 }
@@ -312,36 +320,36 @@ inline bool deregister_instance_impl(void *ptr, instance *self) {
 
 inline void register_instance(instance *self, void *valptr, const type_info *tinfo) {
     register_instance_impl(valptr, self);
-    if (!tinfo->simple_ancestors)
+    if (!tinfo->simple_ancestors) {
         traverse_offset_bases(valptr, tinfo, self, register_instance_impl);
+    }
 }
 
 inline bool deregister_instance(instance *self, void *valptr, const type_info *tinfo) {
     bool ret = deregister_instance_impl(valptr, self);
-    if (!tinfo->simple_ancestors)
+    if (!tinfo->simple_ancestors) {
         traverse_offset_bases(valptr, tinfo, self, deregister_instance_impl);
+    }
     return ret;
 }
 
-/// Instance creation function for all pybind11 types. It allocates the internal instance layout for
-/// holding C++ objects and holders.  Allocation is done lazily (the first time the instance is cast
-/// to a reference or pointer), and initialization is done by an `__init__` function.
+/// Instance creation function for all pybind11 types. It allocates the internal instance layout
+/// for holding C++ objects and holders.  Allocation is done lazily (the first time the instance is
+/// cast to a reference or pointer), and initialization is done by an `__init__` function.
 inline PyObject *make_new_instance(PyTypeObject *type) {
 #if defined(PYPY_VERSION)
-    // PyPy gets tp_basicsize wrong (issue 2482) under multiple inheritance when the first inherited
-    // object is a a plain Python type (i.e. not derived from an extension type).  Fix it.
+    // PyPy gets tp_basicsize wrong (issue 2482) under multiple inheritance when the first
+    // inherited object is a plain Python type (i.e. not derived from an extension type).  Fix it.
     ssize_t instance_size = static_cast<ssize_t>(sizeof(instance));
     if (type->tp_basicsize < instance_size) {
         type->tp_basicsize = instance_size;
     }
 #endif
     PyObject *self = type->tp_alloc(type, 0);
-    auto inst = reinterpret_cast<instance *>(self);
+    auto *inst = reinterpret_cast<instance *>(self);
     // Allocate the value/holder internals:
     inst->allocate_layout();
 
-    inst->owned = true;
-
     return self;
 }
 
@@ -363,14 +371,14 @@ extern "C" inline int pybind11_object_init(PyObject *self, PyObject *, PyObject
 
 inline void add_patient(PyObject *nurse, PyObject *patient) {
     auto &internals = get_internals();
-    auto instance = reinterpret_cast<detail::instance *>(nurse);
+    auto *instance = reinterpret_cast<detail::instance *>(nurse);
     instance->has_patients = true;
     Py_INCREF(patient);
     internals.patients[nurse].push_back(patient);
 }
 
 inline void clear_patients(PyObject *self) {
-    auto instance = reinterpret_cast<detail::instance *>(self);
+    auto *instance = reinterpret_cast<detail::instance *>(self);
     auto &internals = get_internals();
     auto pos = internals.patients.find(self);
     assert(pos != internals.patients.end());
@@ -380,14 +388,15 @@ inline void clear_patients(PyObject *self) {
     auto patients = std::move(pos->second);
     internals.patients.erase(pos);
     instance->has_patients = false;
-    for (PyObject *&patient : patients)
+    for (PyObject *&patient : patients) {
         Py_CLEAR(patient);
+    }
 }
 
 /// Clears all internal data from the instance and removes it from registered instances in
 /// preparation for deallocation.
 inline void clear_instance(PyObject *self) {
-    auto instance = reinterpret_cast<detail::instance *>(self);
+    auto *instance = reinterpret_cast<detail::instance *>(self);
 
     // Deallocate any values/holders, if present:
     for (auto &v_h : values_and_holders(instance)) {
@@ -395,25 +404,32 @@ inline void clear_instance(PyObject *self) {
 
             // We have to deregister before we call dealloc because, for virtual MI types, we still
             // need to be able to get the parent pointers.
-            if (v_h.instance_registered() && !deregister_instance(instance, v_h.value_ptr(), v_h.type))
-                pybind11_fail("pybind11_object_dealloc(): Tried to deallocate unregistered instance!");
+            if (v_h.instance_registered()
+                && !deregister_instance(instance, v_h.value_ptr(), v_h.type)) {
+                pybind11_fail(
+                    "pybind11_object_dealloc(): Tried to deallocate unregistered instance!");
+            }
 
-            if (instance->owned || v_h.holder_constructed())
+            if (instance->owned || v_h.holder_constructed()) {
                 v_h.type->dealloc(v_h);
+            }
         }
     }
     // Deallocate the value/holder layout internals:
     instance->deallocate_layout();
 
-    if (instance->weakrefs)
+    if (instance->weakrefs) {
         PyObject_ClearWeakRefs(self);
+    }
 
     PyObject **dict_ptr = _PyObject_GetDictPtr(self);
-    if (dict_ptr)
+    if (dict_ptr) {
         Py_CLEAR(*dict_ptr);
+    }
 
-    if (instance->has_patients)
+    if (instance->has_patients) {
         clear_patients(self);
+    }
 }
 
 /// Instance destructor function for all pybind11 types. It calls `type_info.dealloc`
@@ -421,7 +437,7 @@ inline void clear_instance(PyObject *self) {
 extern "C" inline void pybind11_object_dealloc(PyObject *self) {
     clear_instance(self);
 
-    auto type = Py_TYPE(self);
+    auto *type = Py_TYPE(self);
     type->tp_free(self);
 
 #if PY_VERSION_HEX < 0x03080000
@@ -439,6 +455,8 @@ extern "C" inline void pybind11_object_dealloc(PyObject *self) {
 #endif
 }
 
+std::string error_string();
+
 /** Create the type which can be used as a common base for all classes.  This is
     needed in order to satisfy Python's requirements for multiple inheritance.
     Return value: New reference. */
@@ -450,16 +468,17 @@ inline PyObject *make_object_base_type(PyTypeObject *metaclass) {
        issue no Python C API calls which could potentially invoke the
        garbage collector (the GC will call type_traverse(), which will in
        turn find the newly constructed type in an invalid state) */
-    auto heap_type = (PyHeapTypeObject *) metaclass->tp_alloc(metaclass, 0);
-    if (!heap_type)
+    auto *heap_type = (PyHeapTypeObject *) metaclass->tp_alloc(metaclass, 0);
+    if (!heap_type) {
         pybind11_fail("make_object_base_type(): error allocating type!");
+    }
 
     heap_type->ht_name = name_obj.inc_ref().ptr();
 #ifdef PYBIND11_BUILTIN_QUALNAME
     heap_type->ht_qualname = name_obj.inc_ref().ptr();
 #endif
 
-    auto type = &heap_type->ht_type;
+    auto *type = &heap_type->ht_type;
     type->tp_name = name;
     type->tp_base = type_incref(&PyBaseObject_Type);
     type->tp_basicsize = static_cast<ssize_t>(sizeof(instance));
@@ -472,8 +491,9 @@ inline PyObject *make_object_base_type(PyTypeObject *metaclass) {
     /* Support weak references (needed for the keep_alive feature) */
     type->tp_weaklistoffset = offsetof(instance, weakrefs);
 
-    if (PyType_Ready(type) < 0)
-        pybind11_fail("PyType_Ready failed in make_object_base_type():" + error_string());
+    if (PyType_Ready(type) < 0) {
+        pybind11_fail("PyType_Ready failed in make_object_base_type(): " + error_string());
+    }
 
     setattr((PyObject *) type, "__module__", str("pybind11_builtins"));
     PYBIND11_SET_OLDPY_QUALNAME(type, name_obj);
@@ -482,33 +502,14 @@ inline PyObject *make_object_base_type(PyTypeObject *metaclass) {
     return (PyObject *) heap_type;
 }
 
-/// dynamic_attr: Support for `d = instance.__dict__`.
-extern "C" inline PyObject *pybind11_get_dict(PyObject *self, void *) {
-    PyObject *&dict = *_PyObject_GetDictPtr(self);
-    if (!dict)
-        dict = PyDict_New();
-    Py_XINCREF(dict);
-    return dict;
-}
-
-/// dynamic_attr: Support for `instance.__dict__ = dict()`.
-extern "C" inline int pybind11_set_dict(PyObject *self, PyObject *new_dict, void *) {
-    if (!PyDict_Check(new_dict)) {
-        PyErr_Format(PyExc_TypeError, "__dict__ must be set to a dictionary, not a '%.200s'",
-                     get_fully_qualified_tp_name(Py_TYPE(new_dict)).c_str());
-        return -1;
-    }
-    PyObject *&dict = *_PyObject_GetDictPtr(self);
-    Py_INCREF(new_dict);
-    Py_CLEAR(dict);
-    dict = new_dict;
-    return 0;
-}
-
 /// dynamic_attr: Allow the garbage collector to traverse the internal instance `__dict__`.
 extern "C" inline int pybind11_traverse(PyObject *self, visitproc visit, void *arg) {
     PyObject *&dict = *_PyObject_GetDictPtr(self);
     Py_VISIT(dict);
+// https://docs.python.org/3/c-api/typeobj.html#c.PyTypeObject.tp_traverse
+#if PY_VERSION_HEX >= 0x03090000
+    Py_VISIT(Py_TYPE(self));
+#endif
     return 0;
 }
 
@@ -521,17 +522,28 @@ extern "C" inline int pybind11_clear(PyObject *self) {
 
 /// Give instances of this type a `__dict__` and opt into garbage collection.
 inline void enable_dynamic_attributes(PyHeapTypeObject *heap_type) {
-    auto type = &heap_type->ht_type;
+    auto *type = &heap_type->ht_type;
     type->tp_flags |= Py_TPFLAGS_HAVE_GC;
-    type->tp_dictoffset = type->tp_basicsize; // place dict at the end
-    type->tp_basicsize += (ssize_t)sizeof(PyObject *); // and allocate enough space for it
+#if PY_VERSION_HEX < 0x030B0000
+    type->tp_dictoffset = type->tp_basicsize;           // place dict at the end
+    type->tp_basicsize += (ssize_t) sizeof(PyObject *); // and allocate enough space for it
+#else
+    type->tp_flags |= Py_TPFLAGS_MANAGED_DICT;
+#endif
     type->tp_traverse = pybind11_traverse;
     type->tp_clear = pybind11_clear;
 
-    static PyGetSetDef getset[] = {
-        {const_cast<char*>("__dict__"), pybind11_get_dict, pybind11_set_dict, nullptr, nullptr},
-        {nullptr, nullptr, nullptr, nullptr, nullptr}
-    };
+    static PyGetSetDef getset[] = {{
+#if PY_VERSION_HEX < 0x03070000
+                                       const_cast<char *>("__dict__"),
+#else
+                                       "__dict__",
+#endif
+                                       PyObject_GenericGetDict,
+                                       PyObject_GenericSetDict,
+                                       nullptr,
+                                       nullptr},
+                                   {nullptr, nullptr, nullptr, nullptr, nullptr}};
     type->tp_getset = getset;
 }
 
@@ -541,38 +553,42 @@ extern "C" inline int pybind11_getbuffer(PyObject *obj, Py_buffer *view, int fla
     type_info *tinfo = nullptr;
     for (auto type : reinterpret_borrow<tuple>(Py_TYPE(obj)->tp_mro)) {
         tinfo = get_type_info((PyTypeObject *) type.ptr());
-        if (tinfo && tinfo->get_buffer)
+        if (tinfo && tinfo->get_buffer) {
             break;
+        }
     }
     if (view == nullptr || !tinfo || !tinfo->get_buffer) {
-        if (view)
+        if (view) {
             view->obj = nullptr;
+        }
         PyErr_SetString(PyExc_BufferError, "pybind11_getbuffer(): Internal error");
         return -1;
     }
     std::memset(view, 0, sizeof(Py_buffer));
     buffer_info *info = tinfo->get_buffer(obj, tinfo->get_buffer_data);
+    if ((flags & PyBUF_WRITABLE) == PyBUF_WRITABLE && info->readonly) {
+        delete info;
+        // view->obj = nullptr;  // Was just memset to 0, so not necessary
+        PyErr_SetString(PyExc_BufferError, "Writable buffer requested for readonly storage");
+        return -1;
+    }
     view->obj = obj;
     view->ndim = 1;
     view->internal = info;
     view->buf = info->ptr;
     view->itemsize = info->itemsize;
     view->len = view->itemsize;
-    for (auto s : info->shape)
+    for (auto s : info->shape) {
         view->len *= s;
-    view->readonly = info->readonly;
-    if ((flags & PyBUF_WRITABLE) == PyBUF_WRITABLE && info->readonly) {
-        if (view)
-            view->obj = nullptr;
-        PyErr_SetString(PyExc_BufferError, "Writable buffer requested for readonly storage");
-        return -1;
     }
-    if ((flags & PyBUF_FORMAT) == PyBUF_FORMAT)
+    view->readonly = static_cast<int>(info->readonly);
+    if ((flags & PyBUF_FORMAT) == PyBUF_FORMAT) {
         view->format = const_cast<char *>(info->format.c_str());
+    }
     if ((flags & PyBUF_STRIDES) == PyBUF_STRIDES) {
         view->ndim = (int) info->ndim;
-        view->strides = &info->strides[0];
-        view->shape = &info->shape[0];
+        view->strides = info->strides.data();
+        view->shape = info->shape.data();
     }
     Py_INCREF(view->obj);
     return 0;
@@ -586,9 +602,6 @@ extern "C" inline void pybind11_releasebuffer(PyObject *, Py_buffer *view) {
 /// Give this type a buffer interface.
 inline void enable_buffer_protocol(PyHeapTypeObject *heap_type) {
     heap_type->ht_type.tp_as_buffer = &heap_type->as_buffer;
-#if PY_MAJOR_VERSION < 3
-    heap_type->ht_type.tp_flags |= Py_TPFLAGS_HAVE_NEWBUFFER;
-#endif
 
     heap_type->as_buffer.bf_getbuffer = pybind11_getbuffer;
     heap_type->as_buffer.bf_releasebuffer = pybind11_releasebuffer;
@@ -596,70 +609,68 @@ inline void enable_buffer_protocol(PyHeapTypeObject *heap_type) {
 
 /** Create a brand new Python type according to the `type_record` specification.
     Return value: New reference. */
-inline PyObject* make_new_python_type(const type_record &rec) {
+inline PyObject *make_new_python_type(const type_record &rec) {
     auto name = reinterpret_steal<object>(PYBIND11_FROM_STRING(rec.name));
 
     auto qualname = name;
     if (rec.scope && !PyModule_Check(rec.scope.ptr()) && hasattr(rec.scope, "__qualname__")) {
-#if PY_MAJOR_VERSION >= 3
         qualname = reinterpret_steal<object>(
             PyUnicode_FromFormat("%U.%U", rec.scope.attr("__qualname__").ptr(), name.ptr()));
-#else
-        qualname = str(rec.scope.attr("__qualname__").cast<std::string>() + "." + rec.name);
-#endif
     }
 
     object module_;
     if (rec.scope) {
-        if (hasattr(rec.scope, "__module__"))
+        if (hasattr(rec.scope, "__module__")) {
             module_ = rec.scope.attr("__module__");
-        else if (hasattr(rec.scope, "__name__"))
+        } else if (hasattr(rec.scope, "__name__")) {
             module_ = rec.scope.attr("__name__");
+        }
     }
 
-    auto full_name = c_str(
+    const auto *full_name = c_str(
 #if !defined(PYPY_VERSION)
         module_ ? str(module_).cast<std::string>() + "." + rec.name :
 #endif
-        rec.name);
+                rec.name);
 
     char *tp_doc = nullptr;
     if (rec.doc && options::show_user_defined_docstrings()) {
         /* Allocate memory for docstring (using PyObject_MALLOC, since
            Python will free this later on) */
-        size_t size = strlen(rec.doc) + 1;
+        size_t size = std::strlen(rec.doc) + 1;
         tp_doc = (char *) PyObject_MALLOC(size);
-        memcpy((void *) tp_doc, rec.doc, size);
+        std::memcpy((void *) tp_doc, rec.doc, size);
     }
 
     auto &internals = get_internals();
     auto bases = tuple(rec.bases);
-    auto base = (bases.empty()) ? internals.instance_base
-                                    : bases[0].ptr();
+    auto *base = (bases.empty()) ? internals.instance_base : bases[0].ptr();
 
     /* Danger zone: from now (and until PyType_Ready), make sure to
        issue no Python C API calls which could potentially invoke the
        garbage collector (the GC will call type_traverse(), which will in
        turn find the newly constructed type in an invalid state) */
-    auto metaclass = rec.metaclass.ptr() ? (PyTypeObject *) rec.metaclass.ptr()
-                                         : internals.default_metaclass;
+    auto *metaclass
+        = rec.metaclass.ptr() ? (PyTypeObject *) rec.metaclass.ptr() : internals.default_metaclass;
 
-    auto heap_type = (PyHeapTypeObject *) metaclass->tp_alloc(metaclass, 0);
-    if (!heap_type)
+    auto *heap_type = (PyHeapTypeObject *) metaclass->tp_alloc(metaclass, 0);
+    if (!heap_type) {
         pybind11_fail(std::string(rec.name) + ": Unable to create type object!");
+    }
 
     heap_type->ht_name = name.release().ptr();
 #ifdef PYBIND11_BUILTIN_QUALNAME
     heap_type->ht_qualname = qualname.inc_ref().ptr();
 #endif
 
-    auto type = &heap_type->ht_type;
+    auto *type = &heap_type->ht_type;
     type->tp_name = full_name;
     type->tp_doc = tp_doc;
-    type->tp_base = type_incref((PyTypeObject *)base);
+    type->tp_base = type_incref((PyTypeObject *) base);
     type->tp_basicsize = static_cast<ssize_t>(sizeof(instance));
-    if (!bases.empty())
+    if (!bases.empty()) {
         type->tp_bases = bases.release().ptr();
+    }
 
     /* Don't inherit base __init__ */
     type->tp_init = pybind11_object_init;
@@ -668,38 +679,42 @@ inline PyObject* make_new_python_type(const type_record &rec) {
     type->tp_as_number = &heap_type->as_number;
     type->tp_as_sequence = &heap_type->as_sequence;
     type->tp_as_mapping = &heap_type->as_mapping;
-#if PY_VERSION_HEX >= 0x03050000
     type->tp_as_async = &heap_type->as_async;
-#endif
 
     /* Flags */
     type->tp_flags |= Py_TPFLAGS_DEFAULT | Py_TPFLAGS_HEAPTYPE;
-#if PY_MAJOR_VERSION < 3
-    type->tp_flags |= Py_TPFLAGS_CHECKTYPES;
-#endif
-    if (!rec.is_final)
+    if (!rec.is_final) {
         type->tp_flags |= Py_TPFLAGS_BASETYPE;
+    }
 
-    if (rec.dynamic_attr)
+    if (rec.dynamic_attr) {
         enable_dynamic_attributes(heap_type);
+    }
 
-    if (rec.buffer_protocol)
+    if (rec.buffer_protocol) {
         enable_buffer_protocol(heap_type);
+    }
 
-    if (PyType_Ready(type) < 0)
-        pybind11_fail(std::string(rec.name) + ": PyType_Ready failed (" + error_string() + ")!");
+    if (rec.custom_type_setup_callback) {
+        rec.custom_type_setup_callback(heap_type);
+    }
+
+    if (PyType_Ready(type) < 0) {
+        pybind11_fail(std::string(rec.name) + ": PyType_Ready failed: " + error_string());
+    }
 
-    assert(rec.dynamic_attr ? PyType_HasFeature(type, Py_TPFLAGS_HAVE_GC)
-                            : !PyType_HasFeature(type, Py_TPFLAGS_HAVE_GC));
+    assert(!rec.dynamic_attr || PyType_HasFeature(type, Py_TPFLAGS_HAVE_GC));
 
     /* Register type with the parent scope */
-    if (rec.scope)
+    if (rec.scope) {
         setattr(rec.scope, rec.name, (PyObject *) type);
-    else
+    } else {
         Py_INCREF(type); // Keep it alive forever (reference leak)
+    }
 
-    if (module_) // Needed by pydoc
+    if (module_) { // Needed by pydoc
         setattr((PyObject *) type, "__module__", module_);
+    }
 
     PYBIND11_SET_OLDPY_QUALNAME(type, qualname);
 
diff --git a/3rdparty/pybind11/include/pybind11/detail/common.h b/3rdparty/pybind11/include/pybind11/detail/common.h
index 751141a927..9e6947daa3 100644
--- a/3rdparty/pybind11/include/pybind11/detail/common.h
+++ b/3rdparty/pybind11/include/pybind11/detail/common.h
@@ -10,116 +10,209 @@
 #pragma once
 
 #define PYBIND11_VERSION_MAJOR 2
-#define PYBIND11_VERSION_MINOR 6
-#define PYBIND11_VERSION_PATCH 1
+#define PYBIND11_VERSION_MINOR 11
+#define PYBIND11_VERSION_PATCH 0.dev1
+
+// Similar to Python's convention: https://docs.python.org/3/c-api/apiabiversion.html
+// Additional convention: 0xD = dev
+#define PYBIND11_VERSION_HEX 0x020B00D1
 
 #define PYBIND11_NAMESPACE_BEGIN(name) namespace name {
 #define PYBIND11_NAMESPACE_END(name) }
 
 // Robust support for some features and loading modules compiled against different pybind versions
-// requires forcing hidden visibility on pybind code, so we enforce this by setting the attribute on
-// the main `pybind11` namespace.
+// requires forcing hidden visibility on pybind code, so we enforce this by setting the attribute
+// on the main `pybind11` namespace.
 #if !defined(PYBIND11_NAMESPACE)
-#  ifdef __GNUG__
-#    define PYBIND11_NAMESPACE pybind11 __attribute__((visibility("hidden")))
-#  else
-#    define PYBIND11_NAMESPACE pybind11
-#  endif
-#endif
-
-#if !(defined(_MSC_VER) && __cplusplus == 199711L) && !defined(__INTEL_COMPILER)
-#  if __cplusplus >= 201402L
-#    define PYBIND11_CPP14
-#    if __cplusplus >= 201703L
-#      define PYBIND11_CPP17
+#    ifdef __GNUG__
+#        define PYBIND11_NAMESPACE pybind11 __attribute__((visibility("hidden")))
+#    else
+#        define PYBIND11_NAMESPACE pybind11
+#    endif
+#endif
+
+#if !(defined(_MSC_VER) && __cplusplus == 199711L)
+#    if __cplusplus >= 201402L
+#        define PYBIND11_CPP14
+#        if __cplusplus >= 201703L
+#            define PYBIND11_CPP17
+#            if __cplusplus >= 202002L
+#                define PYBIND11_CPP20
+// Please update tests/pybind11_tests.cpp `cpp_std()` when adding a macro here.
+#            endif
+#        endif
 #    endif
-#  endif
 #elif defined(_MSC_VER) && __cplusplus == 199711L
-// MSVC sets _MSVC_LANG rather than __cplusplus (supposedly until the standard is fully implemented)
-// Unless you use the /Zc:__cplusplus flag on Visual Studio 2017 15.7 Preview 3 or newer
-#  if _MSVC_LANG >= 201402L
-#    define PYBIND11_CPP14
-#    if _MSVC_LANG > 201402L && _MSC_VER >= 1910
-#      define PYBIND11_CPP17
+// MSVC sets _MSVC_LANG rather than __cplusplus (supposedly until the standard is fully
+// implemented). Unless you use the /Zc:__cplusplus flag on Visual Studio 2017 15.7 Preview 3
+// or newer.
+#    if _MSVC_LANG >= 201402L
+#        define PYBIND11_CPP14
+#        if _MSVC_LANG > 201402L
+#            define PYBIND11_CPP17
+#            if _MSVC_LANG >= 202002L
+#                define PYBIND11_CPP20
+#            endif
+#        endif
 #    endif
-#  endif
 #endif
 
 // Compiler version assertions
 #if defined(__INTEL_COMPILER)
-#  if __INTEL_COMPILER < 1800
-#    error pybind11 requires Intel C++ compiler v18 or newer
-#  endif
+#    if __INTEL_COMPILER < 1800
+#        error pybind11 requires Intel C++ compiler v18 or newer
+#    elif __INTEL_COMPILER < 1900 && defined(PYBIND11_CPP14)
+#        error pybind11 supports only C++11 with Intel C++ compiler v18. Use v19 or newer for C++14.
+#    endif
+/* The following pragma cannot be pop'ed:
+   https://community.intel.com/t5/Intel-C-Compiler/Inline-and-no-inline-warning/td-p/1216764 */
+#    pragma warning disable 2196 // warning #2196: routine is both "inline" and "noinline"
 #elif defined(__clang__) && !defined(__apple_build_version__)
-#  if __clang_major__ < 3 || (__clang_major__ == 3 && __clang_minor__ < 3)
-#    error pybind11 requires clang 3.3 or newer
-#  endif
+#    if __clang_major__ < 3 || (__clang_major__ == 3 && __clang_minor__ < 3)
+#        error pybind11 requires clang 3.3 or newer
+#    endif
 #elif defined(__clang__)
 // Apple changes clang version macros to its Xcode version; the first Xcode release based on
 // (upstream) clang 3.3 was Xcode 5:
-#  if __clang_major__ < 5
-#    error pybind11 requires Xcode/clang 5.0 or newer
-#  endif
+#    if __clang_major__ < 5
+#        error pybind11 requires Xcode/clang 5.0 or newer
+#    endif
 #elif defined(__GNUG__)
-#  if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)
-#    error pybind11 requires gcc 4.8 or newer
-#  endif
+#    if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)
+#        error pybind11 requires gcc 4.8 or newer
+#    endif
 #elif defined(_MSC_VER)
-// Pybind hits various compiler bugs in 2015u2 and earlier, and also makes use of some stl features
-// (e.g. std::negation) added in 2015u3:
-#  if _MSC_FULL_VER < 190024210
-#    error pybind11 requires MSVC 2015 update 3 or newer
-#  endif
+#    if _MSC_VER < 1910
+#        error pybind11 2.10+ requires MSVC 2017 or newer
+#    endif
 #endif
 
 #if !defined(PYBIND11_EXPORT)
-#  if defined(WIN32) || defined(_WIN32)
-#    define PYBIND11_EXPORT __declspec(dllexport)
-#  else
-#    define PYBIND11_EXPORT __attribute__ ((visibility("default")))
-#  endif
+#    if defined(WIN32) || defined(_WIN32)
+#        define PYBIND11_EXPORT __declspec(dllexport)
+#    else
+#        define PYBIND11_EXPORT __attribute__((visibility("default")))
+#    endif
 #endif
 
-#if defined(_MSC_VER)
-#  define PYBIND11_NOINLINE __declspec(noinline)
+#if !defined(PYBIND11_EXPORT_EXCEPTION)
+#    ifdef __MINGW32__
+// workaround for:
+// error: 'dllexport' implies default visibility, but xxx has already been declared with a
+// different visibility
+#        define PYBIND11_EXPORT_EXCEPTION
+#    else
+#        define PYBIND11_EXPORT_EXCEPTION PYBIND11_EXPORT
+#    endif
+#endif
+
+// For CUDA, GCC7, GCC8:
+// PYBIND11_NOINLINE_FORCED is incompatible with `-Wattributes -Werror`.
+// When defining PYBIND11_NOINLINE_FORCED, it is best to also use `-Wno-attributes`.
+// However, the measured shared-library size saving when using noinline are only
+// 1.7% for CUDA, -0.2% for GCC7, and 0.0% for GCC8 (using -DCMAKE_BUILD_TYPE=MinSizeRel,
+// the default under pybind11/tests).
+#if !defined(PYBIND11_NOINLINE_FORCED)                                                            \
+    && (defined(__CUDACC__) || (defined(__GNUC__) && (__GNUC__ == 7 || __GNUC__ == 8)))
+#    define PYBIND11_NOINLINE_DISABLED
+#endif
+
+// The PYBIND11_NOINLINE macro is for function DEFINITIONS.
+// In contrast, FORWARD DECLARATIONS should never use this macro:
+// https://stackoverflow.com/questions/9317473/forward-declaration-of-inline-functions
+#if defined(PYBIND11_NOINLINE_DISABLED) // Option for maximum portability and experimentation.
+#    define PYBIND11_NOINLINE inline
+#elif defined(_MSC_VER)
+#    define PYBIND11_NOINLINE __declspec(noinline) inline
 #else
-#  define PYBIND11_NOINLINE __attribute__ ((noinline))
+#    define PYBIND11_NOINLINE __attribute__((noinline)) inline
 #endif
 
-#if defined(PYBIND11_CPP14)
-#  define PYBIND11_DEPRECATED(reason) [[deprecated(reason)]]
+#if defined(__MINGW32__)
+// For unknown reasons all PYBIND11_DEPRECATED member trigger a warning when declared
+// whether it is used or not
+#    define PYBIND11_DEPRECATED(reason)
+#elif defined(PYBIND11_CPP14)
+#    define PYBIND11_DEPRECATED(reason) [[deprecated(reason)]]
 #else
-#  define PYBIND11_DEPRECATED(reason) __attribute__((deprecated(reason)))
+#    define PYBIND11_DEPRECATED(reason) __attribute__((deprecated(reason)))
 #endif
 
 #if defined(PYBIND11_CPP17)
-#  define PYBIND11_MAYBE_UNUSED [[maybe_unused]]
+#    define PYBIND11_MAYBE_UNUSED [[maybe_unused]]
 #elif defined(_MSC_VER) && !defined(__clang__)
-#  define PYBIND11_MAYBE_UNUSED
+#    define PYBIND11_MAYBE_UNUSED
 #else
-#  define PYBIND11_MAYBE_UNUSED __attribute__ ((__unused__))
+#    define PYBIND11_MAYBE_UNUSED __attribute__((__unused__))
 #endif
 
 /* Don't let Python.h #define (v)snprintf as macro because they are implemented
    properly in Visual Studio since 2015. */
-#if defined(_MSC_VER) && _MSC_VER >= 1900
-#  define HAVE_SNPRINTF 1
+#if defined(_MSC_VER)
+#    define HAVE_SNPRINTF 1
 #endif
 
 /// Include Python header, disable linking to pythonX_d.lib on Windows in debug mode
 #if defined(_MSC_VER)
-#  if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION < 4)
-#    define HAVE_ROUND 1
-#  endif
-#  pragma warning(push)
-#  pragma warning(disable: 4510 4610 4512 4005)
-#  if defined(_DEBUG) && !defined(Py_DEBUG)
-#    define PYBIND11_DEBUG_MARKER
-#    undef _DEBUG
-#  endif
+#    pragma warning(push)
+// C4505: 'PySlice_GetIndicesEx': unreferenced local function has been removed (PyPy only)
+#    pragma warning(disable : 4505)
+#    if defined(_DEBUG) && !defined(Py_DEBUG)
+// Workaround for a VS 2022 issue.
+// NOTE: This workaround knowingly violates the Python.h include order requirement:
+// https://docs.python.org/3/c-api/intro.html#include-files
+// See https://github.com/pybind/pybind11/pull/3497 for full context.
+#        include <yvals.h>
+#        if _MSVC_STL_VERSION >= 143
+#            include <crtdefs.h>
+#        endif
+#        define PYBIND11_DEBUG_MARKER
+#        undef _DEBUG
+#    endif
+#endif
+
+// https://en.cppreference.com/w/c/chrono/localtime
+#if defined(__STDC_LIB_EXT1__) && !defined(__STDC_WANT_LIB_EXT1__)
+#    define __STDC_WANT_LIB_EXT1__
+#endif
+
+#ifdef __has_include
+// std::optional (but including it in c++14 mode isn't allowed)
+#    if defined(PYBIND11_CPP17) && __has_include(<optional>)
+#        define PYBIND11_HAS_OPTIONAL 1
+#    endif
+// std::experimental::optional (but not allowed in c++11 mode)
+#    if defined(PYBIND11_CPP14) && (__has_include(<experimental/optional>) && \
+                                 !__has_include(<optional>))
+#        define PYBIND11_HAS_EXP_OPTIONAL 1
+#    endif
+// std::variant
+#    if defined(PYBIND11_CPP17) && __has_include(<variant>)
+#        define PYBIND11_HAS_VARIANT 1
+#    endif
+#elif defined(_MSC_VER) && defined(PYBIND11_CPP17)
+#    define PYBIND11_HAS_OPTIONAL 1
+#    define PYBIND11_HAS_VARIANT 1
+#endif
+
+#if defined(PYBIND11_CPP17)
+#    if defined(__has_include)
+#        if __has_include(<string_view>)
+#            define PYBIND11_HAS_STRING_VIEW
+#        endif
+#    elif defined(_MSC_VER)
+#        define PYBIND11_HAS_STRING_VIEW
+#    endif
+#endif
+
+#if defined(__cpp_lib_char8_t) && __cpp_lib_char8_t >= 201811L
+#    define PYBIND11_HAS_U8STRING
 #endif
 
 #include <Python.h>
+#if PY_VERSION_HEX < 0x03060000
+#    error "PYTHON < 3.6 IS UNSUPPORTED. pybind11 v2.9 was the last to support Python 2 and 3.5."
+#endif
 #include <frameobject.h>
 #include <pythread.h>
 
@@ -127,41 +220,59 @@
    tends to weak havok in C++ codebases that expect these to work
    like regular functions (potentially with several overloads) */
 #if defined(isalnum)
-#  undef isalnum
-#  undef isalpha
-#  undef islower
-#  undef isspace
-#  undef isupper
-#  undef tolower
-#  undef toupper
+#    undef isalnum
+#    undef isalpha
+#    undef islower
+#    undef isspace
+#    undef isupper
+#    undef tolower
+#    undef toupper
 #endif
 
 #if defined(copysign)
-#  undef copysign
+#    undef copysign
 #endif
 
 #if defined(_MSC_VER)
-#  if defined(PYBIND11_DEBUG_MARKER)
-#    define _DEBUG
-#    undef PYBIND11_DEBUG_MARKER
-#  endif
-#  pragma warning(pop)
+#    if defined(PYBIND11_DEBUG_MARKER)
+#        define _DEBUG
+#        undef PYBIND11_DEBUG_MARKER
+#    endif
+#    pragma warning(pop)
 #endif
 
 #include <cstddef>
 #include <cstring>
-#include <forward_list>
-#include <vector>
-#include <string>
-#include <stdexcept>
 #include <exception>
-#include <unordered_set>
-#include <unordered_map>
+#include <forward_list>
 #include <memory>
-#include <typeindex>
+#include <stdexcept>
+#include <string>
 #include <type_traits>
+#include <typeindex>
+#include <unordered_map>
+#include <unordered_set>
+#include <vector>
+#if defined(__has_include)
+#    if __has_include(<version>)
+#        include <version>
+#    endif
+#endif
 
-#if PY_MAJOR_VERSION >= 3 /// Compatibility macros for various Python versions
+// #define PYBIND11_STR_LEGACY_PERMISSIVE
+// If DEFINED, pybind11::str can hold PyUnicodeObject or PyBytesObject
+//             (probably surprising and never documented, but this was the
+//             legacy behavior until and including v2.6.x). As a side-effect,
+//             pybind11::isinstance<str>() is true for both pybind11::str and
+//             pybind11::bytes.
+// If UNDEFINED, pybind11::str can only hold PyUnicodeObject, and
+//               pybind11::isinstance<str>() is true only for pybind11::str.
+//               However, for Python 2 only (!), the pybind11::str caster
+//               implicitly decoded bytes to PyUnicodeObject. This was to ease
+//               the transition from the legacy behavior to the non-permissive
+//               behavior.
+
+/// Compatibility macros for Python 2 / Python 3 versions TODO: remove
 #define PYBIND11_INSTANCE_METHOD_NEW(ptr, class_) PyInstanceMethod_New(ptr)
 #define PYBIND11_INSTANCE_METHOD_CHECK PyInstanceMethod_Check
 #define PYBIND11_INSTANCE_METHOD_GET_FUNCTION PyInstanceMethod_GET_FUNCTION
@@ -173,8 +284,8 @@
 #define PYBIND11_BYTES_SIZE PyBytes_Size
 #define PYBIND11_LONG_CHECK(o) PyLong_Check(o)
 #define PYBIND11_LONG_AS_LONGLONG(o) PyLong_AsLongLong(o)
-#define PYBIND11_LONG_FROM_SIGNED(o) PyLong_FromSsize_t((ssize_t) o)
-#define PYBIND11_LONG_FROM_UNSIGNED(o) PyLong_FromSize_t((size_t) o)
+#define PYBIND11_LONG_FROM_SIGNED(o) PyLong_FromSsize_t((ssize_t) (o))
+#define PYBIND11_LONG_FROM_UNSIGNED(o) PyLong_FromSize_t((size_t) (o))
 #define PYBIND11_BYTES_NAME "bytes"
 #define PYBIND11_STRING_NAME "str"
 #define PYBIND11_SLICE_OBJECT PyObject
@@ -185,81 +296,42 @@
 #define PYBIND11_BUILTINS_MODULE "builtins"
 // Providing a separate declaration to make Clang's -Wmissing-prototypes happy.
 // See comment for PYBIND11_MODULE below for why this is marked "maybe unused".
-#define PYBIND11_PLUGIN_IMPL(name) \
-    extern "C" PYBIND11_MAYBE_UNUSED PYBIND11_EXPORT PyObject *PyInit_##name(); \
+#define PYBIND11_PLUGIN_IMPL(name)                                                                \
+    extern "C" PYBIND11_MAYBE_UNUSED PYBIND11_EXPORT PyObject *PyInit_##name();                   \
     extern "C" PYBIND11_EXPORT PyObject *PyInit_##name()
 
-#else
-#define PYBIND11_INSTANCE_METHOD_NEW(ptr, class_) PyMethod_New(ptr, nullptr, class_)
-#define PYBIND11_INSTANCE_METHOD_CHECK PyMethod_Check
-#define PYBIND11_INSTANCE_METHOD_GET_FUNCTION PyMethod_GET_FUNCTION
-#define PYBIND11_BYTES_CHECK PyString_Check
-#define PYBIND11_BYTES_FROM_STRING PyString_FromString
-#define PYBIND11_BYTES_FROM_STRING_AND_SIZE PyString_FromStringAndSize
-#define PYBIND11_BYTES_AS_STRING_AND_SIZE PyString_AsStringAndSize
-#define PYBIND11_BYTES_AS_STRING PyString_AsString
-#define PYBIND11_BYTES_SIZE PyString_Size
-#define PYBIND11_LONG_CHECK(o) (PyInt_Check(o) || PyLong_Check(o))
-#define PYBIND11_LONG_AS_LONGLONG(o) (PyInt_Check(o) ? (long long) PyLong_AsLong(o) : PyLong_AsLongLong(o))
-#define PYBIND11_LONG_FROM_SIGNED(o) PyInt_FromSsize_t((ssize_t) o) // Returns long if needed.
-#define PYBIND11_LONG_FROM_UNSIGNED(o) PyInt_FromSize_t((size_t) o) // Returns long if needed.
-#define PYBIND11_BYTES_NAME "str"
-#define PYBIND11_STRING_NAME "unicode"
-#define PYBIND11_SLICE_OBJECT PySliceObject
-#define PYBIND11_FROM_STRING PyString_FromString
-#define PYBIND11_STR_TYPE ::pybind11::bytes
-#define PYBIND11_BOOL_ATTR "__nonzero__"
-#define PYBIND11_NB_BOOL(ptr) ((ptr)->nb_nonzero)
-#define PYBIND11_BUILTINS_MODULE "__builtin__"
-// Providing a separate PyInit decl to make Clang's -Wmissing-prototypes happy.
-// See comment for PYBIND11_MODULE below for why this is marked "maybe unused".
-#define PYBIND11_PLUGIN_IMPL(name) \
-    static PyObject *pybind11_init_wrapper();                           \
-    extern "C" PYBIND11_MAYBE_UNUSED PYBIND11_EXPORT void init##name(); \
-    extern "C" PYBIND11_EXPORT void init##name() {                      \
-        (void)pybind11_init_wrapper();                                  \
-    }                                                                   \
-    PyObject *pybind11_init_wrapper()
-#endif
-
-#if PY_VERSION_HEX >= 0x03050000 && PY_VERSION_HEX < 0x03050200
-extern "C" {
-    struct _Py_atomic_address { void *value; };
-    PyAPI_DATA(_Py_atomic_address) _PyThreadState_Current;
-}
-#endif
-
 #define PYBIND11_TRY_NEXT_OVERLOAD ((PyObject *) 1) // special failure return code
 #define PYBIND11_STRINGIFY(x) #x
 #define PYBIND11_TOSTRING(x) PYBIND11_STRINGIFY(x)
 #define PYBIND11_CONCAT(first, second) first##second
-#define PYBIND11_ENSURE_INTERNALS_READY \
-    pybind11::detail::get_internals();
-
-#define PYBIND11_CHECK_PYTHON_VERSION \
-    {                                                                          \
-        const char *compiled_ver = PYBIND11_TOSTRING(PY_MAJOR_VERSION)         \
-            "." PYBIND11_TOSTRING(PY_MINOR_VERSION);                           \
-        const char *runtime_ver = Py_GetVersion();                             \
-        size_t len = std::strlen(compiled_ver);                                \
-        if (std::strncmp(runtime_ver, compiled_ver, len) != 0                  \
-                || (runtime_ver[len] >= '0' && runtime_ver[len] <= '9')) {     \
-            PyErr_Format(PyExc_ImportError,                                    \
-                "Python version mismatch: module was compiled for Python %s, " \
-                "but the interpreter version is incompatible: %s.",            \
-                compiled_ver, runtime_ver);                                    \
-            return nullptr;                                                    \
-        }                                                                      \
+#define PYBIND11_ENSURE_INTERNALS_READY pybind11::detail::get_internals();
+
+#define PYBIND11_CHECK_PYTHON_VERSION                                                             \
+    {                                                                                             \
+        const char *compiled_ver                                                                  \
+            = PYBIND11_TOSTRING(PY_MAJOR_VERSION) "." PYBIND11_TOSTRING(PY_MINOR_VERSION);        \
+        const char *runtime_ver = Py_GetVersion();                                                \
+        size_t len = std::strlen(compiled_ver);                                                   \
+        if (std::strncmp(runtime_ver, compiled_ver, len) != 0                                     \
+            || (runtime_ver[len] >= '0' && runtime_ver[len] <= '9')) {                            \
+            PyErr_Format(PyExc_ImportError,                                                       \
+                         "Python version mismatch: module was compiled for Python %s, "           \
+                         "but the interpreter version is incompatible: %s.",                      \
+                         compiled_ver,                                                            \
+                         runtime_ver);                                                            \
+            return nullptr;                                                                       \
+        }                                                                                         \
     }
 
-#define PYBIND11_CATCH_INIT_EXCEPTIONS \
-        catch (pybind11::error_already_set &e) {                               \
-            PyErr_SetString(PyExc_ImportError, e.what());                      \
-            return nullptr;                                                    \
-        } catch (const std::exception &e) {                                    \
-            PyErr_SetString(PyExc_ImportError, e.what());                      \
-            return nullptr;                                                    \
-        }                                                                      \
+#define PYBIND11_CATCH_INIT_EXCEPTIONS                                                            \
+    catch (pybind11::error_already_set & e) {                                                     \
+        pybind11::raise_from(e, PyExc_ImportError, "initialization failed");                      \
+        return nullptr;                                                                           \
+    }                                                                                             \
+    catch (const std::exception &e) {                                                             \
+        PyErr_SetString(PyExc_ImportError, e.what());                                             \
+        return nullptr;                                                                           \
+    }
 
 /** \rst
     ***Deprecated in favor of PYBIND11_MODULE***
@@ -276,16 +348,17 @@ extern "C" {
             return m.ptr();
         }
 \endrst */
-#define PYBIND11_PLUGIN(name)                                                  \
-    PYBIND11_DEPRECATED("PYBIND11_PLUGIN is deprecated, use PYBIND11_MODULE")  \
-    static PyObject *pybind11_init();                                          \
-    PYBIND11_PLUGIN_IMPL(name) {                                               \
-        PYBIND11_CHECK_PYTHON_VERSION                                          \
-        PYBIND11_ENSURE_INTERNALS_READY                                        \
-        try {                                                                  \
-            return pybind11_init();                                            \
-        } PYBIND11_CATCH_INIT_EXCEPTIONS                                       \
-    }                                                                          \
+#define PYBIND11_PLUGIN(name)                                                                     \
+    PYBIND11_DEPRECATED("PYBIND11_PLUGIN is deprecated, use PYBIND11_MODULE")                     \
+    static PyObject *pybind11_init();                                                             \
+    PYBIND11_PLUGIN_IMPL(name) {                                                                  \
+        PYBIND11_CHECK_PYTHON_VERSION                                                             \
+        PYBIND11_ENSURE_INTERNALS_READY                                                           \
+        try {                                                                                     \
+            return pybind11_init();                                                               \
+        }                                                                                         \
+        PYBIND11_CATCH_INIT_EXCEPTIONS                                                            \
+    }                                                                                             \
     PyObject *pybind11_init()
 
 /** \rst
@@ -309,29 +382,34 @@ extern "C" {
             });
         }
 \endrst */
-#define PYBIND11_MODULE(name, variable)                                        \
-    static ::pybind11::module_::module_def                                     \
-        PYBIND11_CONCAT(pybind11_module_def_, name) PYBIND11_MAYBE_UNUSED;     \
-    PYBIND11_MAYBE_UNUSED                                                      \
-    static void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &);  \
-    PYBIND11_PLUGIN_IMPL(name) {                                               \
-        PYBIND11_CHECK_PYTHON_VERSION                                          \
-        PYBIND11_ENSURE_INTERNALS_READY                                        \
-        auto m = ::pybind11::module_::create_extension_module(                 \
-            PYBIND11_TOSTRING(name), nullptr,                                  \
-            &PYBIND11_CONCAT(pybind11_module_def_, name));                     \
-        try {                                                                  \
-            PYBIND11_CONCAT(pybind11_init_, name)(m);                          \
-            return m.ptr();                                                    \
-        } PYBIND11_CATCH_INIT_EXCEPTIONS                                       \
-    }                                                                          \
-    void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &variable)
-
+#define PYBIND11_MODULE(name, variable)                                                           \
+    static ::pybind11::module_::module_def PYBIND11_CONCAT(pybind11_module_def_, name)            \
+        PYBIND11_MAYBE_UNUSED;                                                                    \
+    PYBIND11_MAYBE_UNUSED                                                                         \
+    static void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &);                     \
+    PYBIND11_PLUGIN_IMPL(name) {                                                                  \
+        PYBIND11_CHECK_PYTHON_VERSION                                                             \
+        PYBIND11_ENSURE_INTERNALS_READY                                                           \
+        auto m = ::pybind11::module_::create_extension_module(                                    \
+            PYBIND11_TOSTRING(name), nullptr, &PYBIND11_CONCAT(pybind11_module_def_, name));      \
+        try {                                                                                     \
+            PYBIND11_CONCAT(pybind11_init_, name)(m);                                             \
+            return m.ptr();                                                                       \
+        }                                                                                         \
+        PYBIND11_CATCH_INIT_EXCEPTIONS                                                            \
+    }                                                                                             \
+    void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ & (variable))
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
 using ssize_t = Py_ssize_t;
-using size_t  = std::size_t;
+using size_t = std::size_t;
+
+template <typename IntType>
+inline ssize_t ssize_t_cast(const IntType &val) {
+    static_assert(sizeof(IntType) <= sizeof(ssize_t), "Implicit narrowing is not permitted.");
+    return static_cast<ssize_t>(val);
+}
 
 /// Approach used to cast a previously unknown C++ instance into a Python object
 enum class return_value_policy : uint8_t {
@@ -350,7 +428,7 @@ enum class return_value_policy : uint8_t {
 
     /** Reference an existing object (i.e. do not create a new copy) and take
         ownership. Python will call the destructor and delete operator when the
-        object’s reference count reaches zero. Undefined behavior ensues when
+        object's reference count reaches zero. Undefined behavior ensues when
         the C++ side does the same.. */
     take_ownership,
 
@@ -366,7 +444,7 @@ enum class return_value_policy : uint8_t {
     move,
 
     /** Reference an existing object, but do not take ownership. The C++ side
-        is responsible for managing the object’s lifetime and deallocating it
+        is responsible for managing the object's lifetime and deallocating it
         when it is no longer used. Warning: undefined behavior will ensue when
         the C++ side deletes an object that is still referenced and used by
         Python. */
@@ -375,7 +453,7 @@ enum class return_value_policy : uint8_t {
     /** This policy only applies to methods and properties. It references the
         object without taking ownership similar to the above
         return_value_policy::reference policy. In contrast to that policy, the
-        function or property’s implicit this argument (called the parent) is
+        function or property's implicit this argument (called the parent) is
         considered to be the the owner of the return value (the child).
         pybind11 then couples the lifetime of the parent to the child via a
         reference relationship that ensures that the parent cannot be garbage
@@ -387,10 +465,14 @@ enum class return_value_policy : uint8_t {
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-inline static constexpr int log2(size_t n, int k = 0) { return (n <= 1) ? k : log2(n >> 1, k + 1); }
+inline static constexpr int log2(size_t n, int k = 0) {
+    return (n <= 1) ? k : log2(n >> 1, k + 1);
+}
 
 // Returns the size as a multiple of sizeof(void *), rounded up.
-inline static constexpr size_t size_in_ptrs(size_t s) { return 1 + ((s - 1) >> log2(sizeof(void *))); }
+inline static constexpr size_t size_in_ptrs(size_t s) {
+    return 1 + ((s - 1) >> log2(sizeof(void *)));
+}
 
 /**
  * The space to allocate for simple layout instance holders (see below) in multiple of the size of
@@ -400,7 +482,7 @@ inline static constexpr size_t size_in_ptrs(size_t s) { return 1 + ((s - 1) >> l
  */
 constexpr size_t instance_simple_holder_in_ptrs() {
     static_assert(sizeof(std::shared_ptr<int>) >= sizeof(std::unique_ptr<int>),
-            "pybind assumes std::shared_ptrs are at least as big as std::unique_ptrs");
+                  "pybind assumes std::shared_ptrs are at least as big as std::unique_ptrs");
     return size_in_ptrs(sizeof(std::shared_ptr<int>));
 }
 
@@ -428,21 +510,21 @@ struct instance {
     /**
      * An instance has two possible value/holder layouts.
      *
-     * Simple layout (when this flag is true), means the `simple_value_holder` is set with a pointer
-     * and the holder object governing that pointer, i.e. [val1*][holder].  This layout is applied
-     * whenever there is no python-side multiple inheritance of bound C++ types *and* the type's
-     * holder will fit in the default space (which is large enough to hold either a std::unique_ptr
-     * or std::shared_ptr).
+     * Simple layout (when this flag is true), means the `simple_value_holder` is set with a
+     * pointer and the holder object governing that pointer, i.e. [val1*][holder].  This layout is
+     * applied whenever there is no python-side multiple inheritance of bound C++ types *and* the
+     * type's holder will fit in the default space (which is large enough to hold either a
+     * std::unique_ptr or std::shared_ptr).
      *
-     * Non-simple layout applies when using custom holders that require more space than `shared_ptr`
-     * (which is typically the size of two pointers), or when multiple inheritance is used on the
-     * python side.  Non-simple layout allocates the required amount of memory to have multiple
-     * bound C++ classes as parents.  Under this layout, `nonsimple.values_and_holders` is set to a
-     * pointer to allocated space of the required space to hold a sequence of value pointers and
-     * holders followed `status`, a set of bit flags (1 byte each), i.e.
-     * [val1*][holder1][val2*][holder2]...[bb...]  where each [block] is rounded up to a multiple of
-     * `sizeof(void *)`.  `nonsimple.status` is, for convenience, a pointer to the
-     * beginning of the [bb...] block (but not independently allocated).
+     * Non-simple layout applies when using custom holders that require more space than
+     * `shared_ptr` (which is typically the size of two pointers), or when multiple inheritance is
+     * used on the python side.  Non-simple layout allocates the required amount of memory to have
+     * multiple bound C++ classes as parents.  Under this layout, `nonsimple.values_and_holders` is
+     * set to a pointer to allocated space of the required space to hold a sequence of value
+     * pointers and holders followed `status`, a set of bit flags (1 byte each), i.e.
+     * [val1*][holder1][val2*][holder2]...[bb...]  where each [block] is rounded up to a multiple
+     * of `sizeof(void *)`.  `nonsimple.status` is, for convenience, a pointer to the beginning of
+     * the [bb...] block (but not independently allocated).
      *
      * Status bits indicate whether the associated holder is constructed (&
      * status_holder_constructed) and whether the value pointer is registered (&
@@ -456,7 +538,8 @@ struct instance {
     /// If true, get_internals().patients has an entry for this object
     bool has_patients : 1;
 
-    /// Initializes all of the above type/values/holders data (but not the instance values themselves)
+    /// Initializes all of the above type/values/holders data (but not the instance values
+    /// themselves)
     void allocate_layout();
 
     /// Destroys/deallocates all of the above
@@ -465,26 +548,44 @@ struct instance {
     /// Returns the value_and_holder wrapper for the given type (or the first, if `find_type`
     /// omitted).  Returns a default-constructed (with `.inst = nullptr`) object on failure if
     /// `throw_if_missing` is false.
-    value_and_holder get_value_and_holder(const type_info *find_type = nullptr, bool throw_if_missing = true);
+    value_and_holder get_value_and_holder(const type_info *find_type = nullptr,
+                                          bool throw_if_missing = true);
 
     /// Bit values for the non-simple status flags
-    static constexpr uint8_t status_holder_constructed  = 1;
+    static constexpr uint8_t status_holder_constructed = 1;
     static constexpr uint8_t status_instance_registered = 2;
 };
 
-static_assert(std::is_standard_layout<instance>::value, "Internal error: `pybind11::detail::instance` is not standard layout!");
+static_assert(std::is_standard_layout<instance>::value,
+              "Internal error: `pybind11::detail::instance` is not standard layout!");
 
 /// from __cpp_future__ import (convenient aliases from C++14/17)
-#if defined(PYBIND11_CPP14) && (!defined(_MSC_VER) || _MSC_VER >= 1910)
-using std::enable_if_t;
+#if defined(PYBIND11_CPP14)
 using std::conditional_t;
+using std::enable_if_t;
 using std::remove_cv_t;
 using std::remove_reference_t;
 #else
-template <bool B, typename T = void> using enable_if_t = typename std::enable_if<B, T>::type;
-template <bool B, typename T, typename F> using conditional_t = typename std::conditional<B, T, F>::type;
-template <typename T> using remove_cv_t = typename std::remove_cv<T>::type;
-template <typename T> using remove_reference_t = typename std::remove_reference<T>::type;
+template <bool B, typename T = void>
+using enable_if_t = typename std::enable_if<B, T>::type;
+template <bool B, typename T, typename F>
+using conditional_t = typename std::conditional<B, T, F>::type;
+template <typename T>
+using remove_cv_t = typename std::remove_cv<T>::type;
+template <typename T>
+using remove_reference_t = typename std::remove_reference<T>::type;
+#endif
+
+#if defined(PYBIND11_CPP20)
+using std::remove_cvref;
+using std::remove_cvref_t;
+#else
+template <class T>
+struct remove_cvref {
+    using type = remove_cv_t<remove_reference_t<T>>;
+};
+template <class T>
+using remove_cvref_t = typename remove_cvref<T>::type;
 #endif
 
 /// Index sequences
@@ -492,114 +593,189 @@ template <typename T> using remove_reference_t = typename std::remove_reference<
 using std::index_sequence;
 using std::make_index_sequence;
 #else
-template<size_t ...> struct index_sequence  { };
-template<size_t N, size_t ...S> struct make_index_sequence_impl : make_index_sequence_impl <N - 1, N - 1, S...> { };
-template<size_t ...S> struct make_index_sequence_impl <0, S...> { using type = index_sequence<S...>; };
-template<size_t N> using make_index_sequence = typename make_index_sequence_impl<N>::type;
+template <size_t...>
+struct index_sequence {};
+template <size_t N, size_t... S>
+struct make_index_sequence_impl : make_index_sequence_impl<N - 1, N - 1, S...> {};
+template <size_t... S>
+struct make_index_sequence_impl<0, S...> {
+    using type = index_sequence<S...>;
+};
+template <size_t N>
+using make_index_sequence = typename make_index_sequence_impl<N>::type;
 #endif
 
 /// Make an index sequence of the indices of true arguments
-template <typename ISeq, size_t, bool...> struct select_indices_impl { using type = ISeq; };
-template <size_t... IPrev, size_t I, bool B, bool... Bs> struct select_indices_impl<index_sequence<IPrev...>, I, B, Bs...>
-    : select_indices_impl<conditional_t<B, index_sequence<IPrev..., I>, index_sequence<IPrev...>>, I + 1, Bs...> {};
-template <bool... Bs> using select_indices = typename select_indices_impl<index_sequence<>, 0, Bs...>::type;
+template <typename ISeq, size_t, bool...>
+struct select_indices_impl {
+    using type = ISeq;
+};
+template <size_t... IPrev, size_t I, bool B, bool... Bs>
+struct select_indices_impl<index_sequence<IPrev...>, I, B, Bs...>
+    : select_indices_impl<conditional_t<B, index_sequence<IPrev..., I>, index_sequence<IPrev...>>,
+                          I + 1,
+                          Bs...> {};
+template <bool... Bs>
+using select_indices = typename select_indices_impl<index_sequence<>, 0, Bs...>::type;
 
 /// Backports of std::bool_constant and std::negation to accommodate older compilers
-template <bool B> using bool_constant = std::integral_constant<bool, B>;
-template <typename T> struct negation : bool_constant<!T::value> { };
+template <bool B>
+using bool_constant = std::integral_constant<bool, B>;
+template <typename T>
+struct negation : bool_constant<!T::value> {};
 
 // PGI/Intel cannot detect operator delete with the "compatible" void_t impl, so
 // using the new one (C++14 defect, so generally works on newer compilers, even
 // if not in C++17 mode)
 #if defined(__PGIC__) || defined(__INTEL_COMPILER)
-template<typename... > using void_t = void;
+template <typename...>
+using void_t = void;
 #else
-template <typename...> struct void_t_impl { using type = void; };
-template <typename... Ts> using void_t = typename void_t_impl<Ts...>::type;
+template <typename...>
+struct void_t_impl {
+    using type = void;
+};
+template <typename... Ts>
+using void_t = typename void_t_impl<Ts...>::type;
 #endif
 
-
 /// Compile-time all/any/none of that check the boolean value of all template types
 #if defined(__cpp_fold_expressions) && !(defined(_MSC_VER) && (_MSC_VER < 1916))
-template <class... Ts> using all_of = bool_constant<(Ts::value && ...)>;
-template <class... Ts> using any_of = bool_constant<(Ts::value || ...)>;
+template <class... Ts>
+using all_of = bool_constant<(Ts::value && ...)>;
+template <class... Ts>
+using any_of = bool_constant<(Ts::value || ...)>;
 #elif !defined(_MSC_VER)
-template <bool...> struct bools {};
-template <class... Ts> using all_of = std::is_same<
-    bools<Ts::value..., true>,
-    bools<true, Ts::value...>>;
-template <class... Ts> using any_of = negation<all_of<negation<Ts>...>>;
+template <bool...>
+struct bools {};
+template <class... Ts>
+using all_of = std::is_same<bools<Ts::value..., true>, bools<true, Ts::value...>>;
+template <class... Ts>
+using any_of = negation<all_of<negation<Ts>...>>;
 #else
 // MSVC has trouble with the above, but supports std::conjunction, which we can use instead (albeit
 // at a slight loss of compilation efficiency).
-template <class... Ts> using all_of = std::conjunction<Ts...>;
-template <class... Ts> using any_of = std::disjunction<Ts...>;
+template <class... Ts>
+using all_of = std::conjunction<Ts...>;
+template <class... Ts>
+using any_of = std::disjunction<Ts...>;
 #endif
-template <class... Ts> using none_of = negation<any_of<Ts...>>;
+template <class... Ts>
+using none_of = negation<any_of<Ts...>>;
 
-template <class T, template<class> class... Predicates> using satisfies_all_of = all_of<Predicates<T>...>;
-template <class T, template<class> class... Predicates> using satisfies_any_of = any_of<Predicates<T>...>;
-template <class T, template<class> class... Predicates> using satisfies_none_of = none_of<Predicates<T>...>;
+template <class T, template <class> class... Predicates>
+using satisfies_all_of = all_of<Predicates<T>...>;
+template <class T, template <class> class... Predicates>
+using satisfies_any_of = any_of<Predicates<T>...>;
+template <class T, template <class> class... Predicates>
+using satisfies_none_of = none_of<Predicates<T>...>;
 
 /// Strip the class from a method type
-template <typename T> struct remove_class { };
-template <typename C, typename R, typename... A> struct remove_class<R (C::*)(A...)> { using type = R (A...); };
-template <typename C, typename R, typename... A> struct remove_class<R (C::*)(A...) const> { using type = R (A...); };
+template <typename T>
+struct remove_class {};
+template <typename C, typename R, typename... A>
+struct remove_class<R (C::*)(A...)> {
+    using type = R(A...);
+};
+template <typename C, typename R, typename... A>
+struct remove_class<R (C::*)(A...) const> {
+    using type = R(A...);
+};
 
 /// Helper template to strip away type modifiers
-template <typename T> struct intrinsic_type                       { using type = T; };
-template <typename T> struct intrinsic_type<const T>              { using type = typename intrinsic_type<T>::type; };
-template <typename T> struct intrinsic_type<T*>                   { using type = typename intrinsic_type<T>::type; };
-template <typename T> struct intrinsic_type<T&>                   { using type = typename intrinsic_type<T>::type; };
-template <typename T> struct intrinsic_type<T&&>                  { using type = typename intrinsic_type<T>::type; };
-template <typename T, size_t N> struct intrinsic_type<const T[N]> { using type = typename intrinsic_type<T>::type; };
-template <typename T, size_t N> struct intrinsic_type<T[N]>       { using type = typename intrinsic_type<T>::type; };
-template <typename T> using intrinsic_t = typename intrinsic_type<T>::type;
+template <typename T>
+struct intrinsic_type {
+    using type = T;
+};
+template <typename T>
+struct intrinsic_type<const T> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T>
+struct intrinsic_type<T *> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T>
+struct intrinsic_type<T &> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T>
+struct intrinsic_type<T &&> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T, size_t N>
+struct intrinsic_type<const T[N]> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T, size_t N>
+struct intrinsic_type<T[N]> {
+    using type = typename intrinsic_type<T>::type;
+};
+template <typename T>
+using intrinsic_t = typename intrinsic_type<T>::type;
 
 /// Helper type to replace 'void' in some expressions
-struct void_type { };
+struct void_type {};
 
 /// Helper template which holds a list of types
-template <typename...> struct type_list { };
+template <typename...>
+struct type_list {};
 
 /// Compile-time integer sum
 #ifdef __cpp_fold_expressions
-template <typename... Ts> constexpr size_t constexpr_sum(Ts... ns) { return (0 + ... + size_t{ns}); }
+template <typename... Ts>
+constexpr size_t constexpr_sum(Ts... ns) {
+    return (0 + ... + size_t{ns});
+}
 #else
 constexpr size_t constexpr_sum() { return 0; }
 template <typename T, typename... Ts>
-constexpr size_t constexpr_sum(T n, Ts... ns) { return size_t{n} + constexpr_sum(ns...); }
+constexpr size_t constexpr_sum(T n, Ts... ns) {
+    return size_t{n} + constexpr_sum(ns...);
+}
 #endif
 
 PYBIND11_NAMESPACE_BEGIN(constexpr_impl)
 /// Implementation details for constexpr functions
 constexpr int first(int i) { return i; }
 template <typename T, typename... Ts>
-constexpr int first(int i, T v, Ts... vs) { return v ? i : first(i + 1, vs...); }
+constexpr int first(int i, T v, Ts... vs) {
+    return v ? i : first(i + 1, vs...);
+}
 
 constexpr int last(int /*i*/, int result) { return result; }
 template <typename T, typename... Ts>
-constexpr int last(int i, int result, T v, Ts... vs) { return last(i + 1, v ? i : result, vs...); }
+constexpr int last(int i, int result, T v, Ts... vs) {
+    return last(i + 1, v ? i : result, vs...);
+}
 PYBIND11_NAMESPACE_END(constexpr_impl)
 
-/// Return the index of the first type in Ts which satisfies Predicate<T>.  Returns sizeof...(Ts) if
-/// none match.
-template <template<typename> class Predicate, typename... Ts>
-constexpr int constexpr_first() { return constexpr_impl::first(0, Predicate<Ts>::value...); }
+/// Return the index of the first type in Ts which satisfies Predicate<T>.
+/// Returns sizeof...(Ts) if none match.
+template <template <typename> class Predicate, typename... Ts>
+constexpr int constexpr_first() {
+    return constexpr_impl::first(0, Predicate<Ts>::value...);
+}
 
 /// Return the index of the last type in Ts which satisfies Predicate<T>, or -1 if none match.
-template <template<typename> class Predicate, typename... Ts>
-constexpr int constexpr_last() { return constexpr_impl::last(0, -1, Predicate<Ts>::value...); }
+template <template <typename> class Predicate, typename... Ts>
+constexpr int constexpr_last() {
+    return constexpr_impl::last(0, -1, Predicate<Ts>::value...);
+}
 
 /// Return the Nth element from the parameter pack
 template <size_t N, typename T, typename... Ts>
-struct pack_element { using type = typename pack_element<N - 1, Ts...>::type; };
+struct pack_element {
+    using type = typename pack_element<N - 1, Ts...>::type;
+};
 template <typename T, typename... Ts>
-struct pack_element<0, T, Ts...> { using type = T; };
+struct pack_element<0, T, Ts...> {
+    using type = T;
+};
 
 /// Return the one and only type which matches the predicate, or Default if none match.
 /// If more than one type matches the predicate, fail at compile-time.
-template <template<typename> class Predicate, typename Default, typename... Ts>
+template <template <typename> class Predicate, typename Default, typename... Ts>
 struct exactly_one {
     static constexpr auto found = constexpr_sum(Predicate<Ts>::value...);
     static_assert(found <= 1, "Found more than one type matching the predicate");
@@ -607,62 +783,87 @@ struct exactly_one {
     static constexpr auto index = found ? constexpr_first<Predicate, Ts...>() : 0;
     using type = conditional_t<found, typename pack_element<index, Ts...>::type, Default>;
 };
-template <template<typename> class P, typename Default>
-struct exactly_one<P, Default> { using type = Default; };
+template <template <typename> class P, typename Default>
+struct exactly_one<P, Default> {
+    using type = Default;
+};
 
-template <template<typename> class Predicate, typename Default, typename... Ts>
+template <template <typename> class Predicate, typename Default, typename... Ts>
 using exactly_one_t = typename exactly_one<Predicate, Default, Ts...>::type;
 
 /// Defer the evaluation of type T until types Us are instantiated
-template <typename T, typename... /*Us*/> struct deferred_type { using type = T; };
-template <typename T, typename... Us> using deferred_t = typename deferred_type<T, Us...>::type;
+template <typename T, typename... /*Us*/>
+struct deferred_type {
+    using type = T;
+};
+template <typename T, typename... Us>
+using deferred_t = typename deferred_type<T, Us...>::type;
 
 /// Like is_base_of, but requires a strict base (i.e. `is_strict_base_of<T, T>::value == false`,
 /// unlike `std::is_base_of`)
-template <typename Base, typename Derived> using is_strict_base_of = bool_constant<
-    std::is_base_of<Base, Derived>::value && !std::is_same<Base, Derived>::value>;
-
-/// Like is_base_of, but also requires that the base type is accessible (i.e. that a Derived pointer
-/// can be converted to a Base pointer)
-/// For unions, `is_base_of<T, T>::value` is False, so we need to check `is_same` as well.
-template <typename Base, typename Derived> using is_accessible_base_of = bool_constant<
-    (std::is_same<Base, Derived>::value || std::is_base_of<Base, Derived>::value) && std::is_convertible<Derived *, Base *>::value>;
-
-template <template<typename...> class Base>
+template <typename Base, typename Derived>
+using is_strict_base_of
+    = bool_constant<std::is_base_of<Base, Derived>::value && !std::is_same<Base, Derived>::value>;
+
+/// Like is_base_of, but also requires that the base type is accessible (i.e. that a Derived
+/// pointer can be converted to a Base pointer) For unions, `is_base_of<T, T>::value` is False, so
+/// we need to check `is_same` as well.
+template <typename Base, typename Derived>
+using is_accessible_base_of
+    = bool_constant<(std::is_same<Base, Derived>::value || std::is_base_of<Base, Derived>::value)
+                    && std::is_convertible<Derived *, Base *>::value>;
+
+template <template <typename...> class Base>
 struct is_template_base_of_impl {
-    template <typename... Us> static std::true_type check(Base<Us...> *);
+    template <typename... Us>
+    static std::true_type check(Base<Us...> *);
     static std::false_type check(...);
 };
 
 /// Check if a template is the base of a type. For example:
 /// `is_template_base_of<Base, T>` is true if `struct T : Base<U> {}` where U can be anything
-template <template<typename...> class Base, typename T>
+template <template <typename...> class Base, typename T>
+// Sadly, all MSVC versions incl. 2022 need the workaround, even in C++20 mode.
+// See also: https://github.com/pybind/pybind11/pull/3741
 #if !defined(_MSC_VER)
-using is_template_base_of = decltype(is_template_base_of_impl<Base>::check((intrinsic_t<T>*)nullptr));
-#else // MSVC2015 has trouble with decltype in template aliases
-struct is_template_base_of : decltype(is_template_base_of_impl<Base>::check((intrinsic_t<T>*)nullptr)) { };
+using is_template_base_of
+    = decltype(is_template_base_of_impl<Base>::check((intrinsic_t<T> *) nullptr));
+#else
+struct is_template_base_of
+    : decltype(is_template_base_of_impl<Base>::check((intrinsic_t<T> *) nullptr)) {
+};
 #endif
 
 /// Check if T is an instantiation of the template `Class`. For example:
 /// `is_instantiation<shared_ptr, T>` is true if `T == shared_ptr<U>` where U can be anything.
-template <template<typename...> class Class, typename T>
-struct is_instantiation : std::false_type { };
-template <template<typename...> class Class, typename... Us>
-struct is_instantiation<Class, Class<Us...>> : std::true_type { };
+template <template <typename...> class Class, typename T>
+struct is_instantiation : std::false_type {};
+template <template <typename...> class Class, typename... Us>
+struct is_instantiation<Class, Class<Us...>> : std::true_type {};
 
 /// Check if T is std::shared_ptr<U> where U can be anything
-template <typename T> using is_shared_ptr = is_instantiation<std::shared_ptr, T>;
+template <typename T>
+using is_shared_ptr = is_instantiation<std::shared_ptr, T>;
 
 /// Check if T looks like an input iterator
-template <typename T, typename = void> struct is_input_iterator : std::false_type {};
+template <typename T, typename = void>
+struct is_input_iterator : std::false_type {};
 template <typename T>
-struct is_input_iterator<T, void_t<decltype(*std::declval<T &>()), decltype(++std::declval<T &>())>>
+struct is_input_iterator<T,
+                         void_t<decltype(*std::declval<T &>()), decltype(++std::declval<T &>())>>
     : std::true_type {};
 
-template <typename T> using is_function_pointer = bool_constant<
-    std::is_pointer<T>::value && std::is_function<typename std::remove_pointer<T>::type>::value>;
-
-template <typename F> struct strip_function_object {
+template <typename T>
+using is_function_pointer
+    = bool_constant<std::is_pointer<T>::value
+                    && std::is_function<typename std::remove_pointer<T>::type>::value>;
+
+template <typename F>
+struct strip_function_object {
+    // If you are encountering an
+    // 'error: name followed by "::" must be a class or namespace name'
+    // with the Intel compiler and a noexcept function here,
+    // try to use noexcept(true) instead of plain noexcept.
     using type = typename remove_class<decltype(&F::operator())>::type;
 };
 
@@ -671,45 +872,55 @@ template <typename Function, typename F = remove_reference_t<Function>>
 using function_signature_t = conditional_t<
     std::is_function<F>::value,
     F,
-    typename conditional_t<
-        std::is_pointer<F>::value || std::is_member_pointer<F>::value,
-        std::remove_pointer<F>,
-        strip_function_object<F>
-    >::type
->;
+    typename conditional_t<std::is_pointer<F>::value || std::is_member_pointer<F>::value,
+                           std::remove_pointer<F>,
+                           strip_function_object<F>>::type>;
 
 /// Returns true if the type looks like a lambda: that is, isn't a function, pointer or member
 /// pointer.  Note that this can catch all sorts of other things, too; this is intended to be used
 /// in a place where passing a lambda makes sense.
-template <typename T> using is_lambda = satisfies_none_of<remove_reference_t<T>,
-        std::is_function, std::is_pointer, std::is_member_pointer>;
-
-/// Ignore that a variable is unused in compiler warnings
-inline void ignore_unused(const int *) { }
+template <typename T>
+using is_lambda = satisfies_none_of<remove_reference_t<T>,
+                                    std::is_function,
+                                    std::is_pointer,
+                                    std::is_member_pointer>;
 
+// [workaround(intel)] Internal error on fold expression
 /// Apply a function over each element of a parameter pack
-#ifdef __cpp_fold_expressions
-#define PYBIND11_EXPAND_SIDE_EFFECTS(PATTERN) (((PATTERN), void()), ...)
+#if defined(__cpp_fold_expressions) && !defined(__INTEL_COMPILER)
+// Intel compiler produces an internal error on this fold expression (tested with ICC 19.0.2)
+#    define PYBIND11_EXPAND_SIDE_EFFECTS(PATTERN) (((PATTERN), void()), ...)
 #else
 using expand_side_effects = bool[];
-#define PYBIND11_EXPAND_SIDE_EFFECTS(PATTERN) (void)pybind11::detail::expand_side_effects{ ((PATTERN), void(), false)..., false }
+#    define PYBIND11_EXPAND_SIDE_EFFECTS(PATTERN)                                                 \
+        (void) pybind11::detail::expand_side_effects { ((PATTERN), void(), false)..., false }
 #endif
 
 PYBIND11_NAMESPACE_END(detail)
 
+#if defined(_MSC_VER)
+#    pragma warning(push)
+#    pragma warning(disable : 4275)
+//     warning C4275: An exported class was derived from a class that wasn't exported.
+//     Can be ignored when derived from a STL class.
+#endif
 /// C++ bindings of builtin Python exceptions
-class builtin_exception : public std::runtime_error {
+class PYBIND11_EXPORT_EXCEPTION builtin_exception : public std::runtime_error {
 public:
     using std::runtime_error::runtime_error;
     /// Set the error using the Python C API
     virtual void set_error() const = 0;
 };
+#if defined(_MSC_VER)
+#    pragma warning(pop)
+#endif
 
-#define PYBIND11_RUNTIME_EXCEPTION(name, type) \
-    class name : public builtin_exception { public: \
-        using builtin_exception::builtin_exception; \
-        name() : name("") { } \
-        void set_error() const override { PyErr_SetString(type, what()); } \
+#define PYBIND11_RUNTIME_EXCEPTION(name, type)                                                    \
+    class PYBIND11_EXPORT_EXCEPTION name : public builtin_exception {                             \
+    public:                                                                                       \
+        using builtin_exception::builtin_exception;                                               \
+        name() : name("") {}                                                                      \
+        void set_error() const override { PyErr_SetString(type, what()); }                        \
     };
 
 PYBIND11_RUNTIME_EXCEPTION(stop_iteration, PyExc_StopIteration)
@@ -719,13 +930,23 @@ PYBIND11_RUNTIME_EXCEPTION(value_error, PyExc_ValueError)
 PYBIND11_RUNTIME_EXCEPTION(type_error, PyExc_TypeError)
 PYBIND11_RUNTIME_EXCEPTION(buffer_error, PyExc_BufferError)
 PYBIND11_RUNTIME_EXCEPTION(import_error, PyExc_ImportError)
-PYBIND11_RUNTIME_EXCEPTION(cast_error, PyExc_RuntimeError) /// Thrown when pybind11::cast or handle::call fail due to a type casting error
+PYBIND11_RUNTIME_EXCEPTION(attribute_error, PyExc_AttributeError)
+PYBIND11_RUNTIME_EXCEPTION(cast_error, PyExc_RuntimeError) /// Thrown when pybind11::cast or
+                                                           /// handle::call fail due to a type
+                                                           /// casting error
 PYBIND11_RUNTIME_EXCEPTION(reference_cast_error, PyExc_RuntimeError) /// Used internally
 
-[[noreturn]] PYBIND11_NOINLINE inline void pybind11_fail(const char *reason) { throw std::runtime_error(reason); }
-[[noreturn]] PYBIND11_NOINLINE inline void pybind11_fail(const std::string &reason) { throw std::runtime_error(reason); }
+[[noreturn]] PYBIND11_NOINLINE void pybind11_fail(const char *reason) {
+    assert(!PyErr_Occurred());
+    throw std::runtime_error(reason);
+}
+[[noreturn]] PYBIND11_NOINLINE void pybind11_fail(const std::string &reason) {
+    assert(!PyErr_Occurred());
+    throw std::runtime_error(reason);
+}
 
-template <typename T, typename SFINAE = void> struct format_descriptor { };
+template <typename T, typename SFINAE = void>
+struct format_descriptor {};
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 // Returns the index of the given type in the type char array below, and in the list in numpy.h
@@ -733,25 +954,38 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 // complex float,double,long double.  Note that the long double types only participate when long
 // double is actually longer than double (it isn't under MSVC).
 // NB: not only the string below but also complex.h and numpy.h rely on this order.
-template <typename T, typename SFINAE = void> struct is_fmt_numeric { static constexpr bool value = false; };
-template <typename T> struct is_fmt_numeric<T, enable_if_t<std::is_arithmetic<T>::value>> {
+template <typename T, typename SFINAE = void>
+struct is_fmt_numeric {
+    static constexpr bool value = false;
+};
+template <typename T>
+struct is_fmt_numeric<T, enable_if_t<std::is_arithmetic<T>::value>> {
     static constexpr bool value = true;
-    static constexpr int index = std::is_same<T, bool>::value ? 0 : 1 + (
-        std::is_integral<T>::value ? detail::log2(sizeof(T))*2 + std::is_unsigned<T>::value : 8 + (
-        std::is_same<T, double>::value ? 1 : std::is_same<T, long double>::value ? 2 : 0));
+    static constexpr int index
+        = std::is_same<T, bool>::value
+              ? 0
+              : 1
+                    + (std::is_integral<T>::value
+                           ? detail::log2(sizeof(T)) * 2 + std::is_unsigned<T>::value
+                           : 8
+                                 + (std::is_same<T, double>::value        ? 1
+                                    : std::is_same<T, long double>::value ? 2
+                                                                          : 0));
 };
 PYBIND11_NAMESPACE_END(detail)
 
-template <typename T> struct format_descriptor<T, detail::enable_if_t<std::is_arithmetic<T>::value>> {
+template <typename T>
+struct format_descriptor<T, detail::enable_if_t<std::is_arithmetic<T>::value>> {
     static constexpr const char c = "?bBhHiIqQfdg"[detail::is_fmt_numeric<T>::index];
-    static constexpr const char value[2] = { c, '\0' };
+    static constexpr const char value[2] = {c, '\0'};
     static std::string format() { return std::string(1, c); }
 };
 
 #if !defined(PYBIND11_CPP17)
 
-template <typename T> constexpr const char format_descriptor<
-    T, detail::enable_if_t<std::is_arithmetic<T>::value>>::value[2];
+template <typename T>
+constexpr const char
+    format_descriptor<T, detail::enable_if_t<std::is_arithmetic<T>::value>>::value[2];
 
 #endif
 
@@ -759,40 +993,52 @@ template <typename T> constexpr const char format_descriptor<
 struct error_scope {
     PyObject *type, *value, *trace;
     error_scope() { PyErr_Fetch(&type, &value, &trace); }
+    error_scope(const error_scope &) = delete;
+    error_scope &operator=(const error_scope &) = delete;
     ~error_scope() { PyErr_Restore(type, value, trace); }
 };
 
 /// Dummy destructor wrapper that can be used to expose classes with a private destructor
-struct nodelete { template <typename T> void operator()(T*) { } };
+struct nodelete {
+    template <typename T>
+    void operator()(T *) {}
+};
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 template <typename... Args>
 struct overload_cast_impl {
-    constexpr overload_cast_impl() {}; // NOLINT(modernize-use-equals-default):  MSVC 2015 needs this
-
     template <typename Return>
-    constexpr auto operator()(Return (*pf)(Args...)) const noexcept
-                              -> decltype(pf) { return pf; }
+    constexpr auto operator()(Return (*pf)(Args...)) const noexcept -> decltype(pf) {
+        return pf;
+    }
 
     template <typename Return, typename Class>
     constexpr auto operator()(Return (Class::*pmf)(Args...), std::false_type = {}) const noexcept
-                              -> decltype(pmf) { return pmf; }
+        -> decltype(pmf) {
+        return pmf;
+    }
 
     template <typename Return, typename Class>
     constexpr auto operator()(Return (Class::*pmf)(Args...) const, std::true_type) const noexcept
-                              -> decltype(pmf) { return pmf; }
+        -> decltype(pmf) {
+        return pmf;
+    }
 };
 PYBIND11_NAMESPACE_END(detail)
 
 // overload_cast requires variable templates: C++14
 #if defined(PYBIND11_CPP14)
-#define PYBIND11_OVERLOAD_CAST 1
+#    define PYBIND11_OVERLOAD_CAST 1
 /// Syntax sugar for resolving overloaded function pointers:
 ///  - regular: static_cast<Return (Class::*)(Arg0, Arg1, Arg2)>(&Class::func)
 ///  - sweet:   overload_cast<Arg0, Arg1, Arg2>(&Class::func)
 template <typename... Args>
+#    if (defined(_MSC_VER) && _MSC_VER < 1920) /* MSVC 2017 */                                    \
+        || (defined(__clang__) && __clang_major__ == 5)
 static constexpr detail::overload_cast_impl<Args...> overload_cast = {};
-// MSVC 2015 only accepts this particular initialization syntax for this variable template.
+#    else
+static constexpr detail::overload_cast_impl<Args...> overload_cast;
+#    endif
 #endif
 
 /// Const member function selector for overload_cast
@@ -801,7 +1047,8 @@ static constexpr detail::overload_cast_impl<Args...> overload_cast = {};
 static constexpr auto const_ = std::true_type{};
 
 #if !defined(PYBIND11_CPP14) // no overload_cast: providing something that static_assert-fails:
-template <typename... Args> struct overload_cast {
+template <typename... Args>
+struct overload_cast {
     static_assert(detail::deferred_t<std::false_type, Args...>::value,
                   "pybind11::overload_cast<...> requires compiling in C++14 mode");
 };
@@ -815,26 +1062,34 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 template <typename T>
 class any_container {
     std::vector<T> v;
+
 public:
     any_container() = default;
 
     // Can construct from a pair of iterators
     template <typename It, typename = enable_if_t<is_input_iterator<It>::value>>
-    any_container(It first, It last) : v(first, last) { }
-
-    // Implicit conversion constructor from any arbitrary container type with values convertible to T
-    template <typename Container, typename = enable_if_t<std::is_convertible<decltype(*std::begin(std::declval<const Container &>())), T>::value>>
-    any_container(const Container &c) : any_container(std::begin(c), std::end(c)) { }
-
-    // initializer_list's aren't deducible, so don't get matched by the above template; we need this
-    // to explicitly allow implicit conversion from one:
+    any_container(It first, It last) : v(first, last) {}
+
+    // Implicit conversion constructor from any arbitrary container type
+    // with values convertible to T
+    template <typename Container,
+              typename = enable_if_t<
+                  std::is_convertible<decltype(*std::begin(std::declval<const Container &>())),
+                                      T>::value>>
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    any_container(const Container &c) : any_container(std::begin(c), std::end(c)) {}
+
+    // initializer_list's aren't deducible, so don't get matched by the above template;
+    // we need this to explicitly allow implicit conversion from one:
     template <typename TIn, typename = enable_if_t<std::is_convertible<TIn, T>::value>>
-    any_container(const std::initializer_list<TIn> &c) : any_container(c.begin(), c.end()) { }
+    any_container(const std::initializer_list<TIn> &c) : any_container(c.begin(), c.end()) {}
 
     // Avoid copying if given an rvalue vector of the correct type.
-    any_container(std::vector<T> &&v) : v(std::move(v)) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    any_container(std::vector<T> &&v) : v(std::move(v)) {}
 
     // Moves the vector out of an rvalue any_container
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator std::vector<T> &&() && { return std::move(v); }
 
     // Dereferencing obtains a reference to the underlying vector
@@ -847,7 +1102,86 @@ class any_container {
 };
 
 // Forward-declaration; see detail/class.h
-std::string get_fully_qualified_tp_name(PyTypeObject*);
+std::string get_fully_qualified_tp_name(PyTypeObject *);
+
+template <typename T>
+inline static std::shared_ptr<T>
+try_get_shared_from_this(std::enable_shared_from_this<T> *holder_value_ptr) {
+// Pre C++17, this code path exploits undefined behavior, but is known to work on many platforms.
+// Use at your own risk!
+// See also https://en.cppreference.com/w/cpp/memory/enable_shared_from_this, and in particular
+// the `std::shared_ptr<Good> gp1 = not_so_good.getptr();` and `try`-`catch` parts of the example.
+#if defined(__cpp_lib_enable_shared_from_this) && (!defined(_MSC_VER) || _MSC_VER >= 1912)
+    return holder_value_ptr->weak_from_this().lock();
+#else
+    try {
+        return holder_value_ptr->shared_from_this();
+    } catch (const std::bad_weak_ptr &) {
+        return nullptr;
+    }
+#endif
+}
+
+// For silencing "unused" compiler warnings in special situations.
+template <typename... Args>
+#if defined(_MSC_VER) && _MSC_VER < 1920 // MSVC 2017
+constexpr
+#endif
+    inline void
+    silence_unused_warnings(Args &&...) {
+}
+
+// MSVC warning C4100: Unreferenced formal parameter
+#if defined(_MSC_VER) && _MSC_VER <= 1916
+#    define PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(...)                                         \
+        detail::silence_unused_warnings(__VA_ARGS__)
+#else
+#    define PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(...)
+#endif
+
+// GCC -Wunused-but-set-parameter  All GCC versions (as of July 2021).
+#if defined(__GNUG__) && !defined(__clang__) && !defined(__INTEL_COMPILER)
+#    define PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(...)                       \
+        detail::silence_unused_warnings(__VA_ARGS__)
+#else
+#    define PYBIND11_WORKAROUND_INCORRECT_GCC_UNUSED_BUT_SET_PARAMETER(...)
+#endif
+
+#if defined(_MSC_VER) // All versions (as of July 2021).
+
+// warning C4127: Conditional expression is constant
+constexpr inline bool silence_msvc_c4127(bool cond) { return cond; }
+
+#    define PYBIND11_SILENCE_MSVC_C4127(...) ::pybind11::detail::silence_msvc_c4127(__VA_ARGS__)
+
+#else
+#    define PYBIND11_SILENCE_MSVC_C4127(...) __VA_ARGS__
+#endif
+
+#if defined(__clang__)                                                                            \
+    && (defined(__apple_build_version__) /* AppleClang 13.0.0.13000029 was the only data point    \
+                                            available. */                                         \
+        || (__clang_major__ >= 7                                                                  \
+            && __clang_major__ <= 12) /* Clang 3, 5, 13, 14, 15 do not generate the warning. */   \
+    )
+#    define PYBIND11_DETECTED_CLANG_WITH_MISLEADING_CALL_STD_MOVE_EXPLICITLY_WARNING
+// Example:
+// tests/test_kwargs_and_defaults.cpp:46:68: error: local variable 'args' will be copied despite
+// being returned by name [-Werror,-Wreturn-std-move]
+//     m.def("args_function", [](py::args args) -> py::tuple { return args; });
+//                                                                    ^~~~
+// test_kwargs_and_defaults.cpp:46:68: note: call 'std::move' explicitly to avoid copying
+//     m.def("args_function", [](py::args args) -> py::tuple { return args; });
+//                                                                    ^~~~
+//                                                                    std::move(args)
+#endif
+
+// Pybind offers detailed error messages by default for all builts that are debug (through the
+// negation of ndebug). This can also be manually enabled by users, for any builds, through
+// defining PYBIND11_DETAILED_ERROR_MESSAGES.
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES) && !defined(NDEBUG)
+#    define PYBIND11_DETAILED_ERROR_MESSAGES
+#endif
 
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/detail/descr.h b/3rdparty/pybind11/include/pybind11/detail/descr.h
index 92720cd562..e7a5e2c145 100644
--- a/3rdparty/pybind11/include/pybind11/detail/descr.h
+++ b/3rdparty/pybind11/include/pybind11/detail/descr.h
@@ -15,24 +15,26 @@ PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 #if !defined(_MSC_VER)
-#  define PYBIND11_DESCR_CONSTEXPR static constexpr
+#    define PYBIND11_DESCR_CONSTEXPR static constexpr
 #else
-#  define PYBIND11_DESCR_CONSTEXPR const
+#    define PYBIND11_DESCR_CONSTEXPR const
 #endif
 
 /* Concatenate type signatures at compile time */
 template <size_t N, typename... Ts>
 struct descr {
-    char text[N + 1];
+    char text[N + 1]{'\0'};
 
-    constexpr descr() : text{'\0'} { }
-    constexpr descr(char const (&s)[N+1]) : descr(s, make_index_sequence<N>()) { }
+    constexpr descr() = default;
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    constexpr descr(char const (&s)[N + 1]) : descr(s, make_index_sequence<N>()) {}
 
     template <size_t... Is>
-    constexpr descr(char const (&s)[N+1], index_sequence<Is...>) : text{s[Is]..., '\0'} { }
+    constexpr descr(char const (&s)[N + 1], index_sequence<Is...>) : text{s[Is]..., '\0'} {}
 
     template <typename... Chars>
-    constexpr descr(char c, Chars... cs) : text{c, static_cast<char>(cs)..., '\0'} { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    constexpr descr(char c, Chars... cs) : text{c, static_cast<char>(cs)..., '\0'} {}
 
     static constexpr std::array<const std::type_info *, sizeof...(Ts) + 1> types() {
         return {{&typeid(Ts)..., nullptr}};
@@ -40,60 +42,116 @@ struct descr {
 };
 
 template <size_t N1, size_t N2, typename... Ts1, typename... Ts2, size_t... Is1, size_t... Is2>
-constexpr descr<N1 + N2, Ts1..., Ts2...> plus_impl(const descr<N1, Ts1...> &a, const descr<N2, Ts2...> &b,
-                                                   index_sequence<Is1...>, index_sequence<Is2...>) {
+constexpr descr<N1 + N2, Ts1..., Ts2...> plus_impl(const descr<N1, Ts1...> &a,
+                                                   const descr<N2, Ts2...> &b,
+                                                   index_sequence<Is1...>,
+                                                   index_sequence<Is2...>) {
+    PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(b);
     return {a.text[Is1]..., b.text[Is2]...};
 }
 
 template <size_t N1, size_t N2, typename... Ts1, typename... Ts2>
-constexpr descr<N1 + N2, Ts1..., Ts2...> operator+(const descr<N1, Ts1...> &a, const descr<N2, Ts2...> &b) {
+constexpr descr<N1 + N2, Ts1..., Ts2...> operator+(const descr<N1, Ts1...> &a,
+                                                   const descr<N2, Ts2...> &b) {
     return plus_impl(a, b, make_index_sequence<N1>(), make_index_sequence<N2>());
 }
 
 template <size_t N>
-constexpr descr<N - 1> _(char const(&text)[N]) { return descr<N - 1>(text); }
-constexpr descr<0> _(char const(&)[1]) { return {}; }
+constexpr descr<N - 1> const_name(char const (&text)[N]) {
+    return descr<N - 1>(text);
+}
+constexpr descr<0> const_name(char const (&)[1]) { return {}; }
 
-template <size_t Rem, size_t... Digits> struct int_to_str : int_to_str<Rem/10, Rem%10, Digits...> { };
-template <size_t...Digits> struct int_to_str<0, Digits...> {
+template <size_t Rem, size_t... Digits>
+struct int_to_str : int_to_str<Rem / 10, Rem % 10, Digits...> {};
+template <size_t... Digits>
+struct int_to_str<0, Digits...> {
+    // WARNING: This only works with C++17 or higher.
     static constexpr auto digits = descr<sizeof...(Digits)>(('0' + Digits)...);
 };
 
 // Ternary description (like std::conditional)
 template <bool B, size_t N1, size_t N2>
-constexpr enable_if_t<B, descr<N1 - 1>> _(char const(&text1)[N1], char const(&)[N2]) {
-    return _(text1);
+constexpr enable_if_t<B, descr<N1 - 1>> const_name(char const (&text1)[N1], char const (&)[N2]) {
+    return const_name(text1);
 }
 template <bool B, size_t N1, size_t N2>
-constexpr enable_if_t<!B, descr<N2 - 1>> _(char const(&)[N1], char const(&text2)[N2]) {
-    return _(text2);
+constexpr enable_if_t<!B, descr<N2 - 1>> const_name(char const (&)[N1], char const (&text2)[N2]) {
+    return const_name(text2);
 }
 
 template <bool B, typename T1, typename T2>
-constexpr enable_if_t<B, T1> _(const T1 &d, const T2 &) { return d; }
+constexpr enable_if_t<B, T1> const_name(const T1 &d, const T2 &) {
+    return d;
+}
 template <bool B, typename T1, typename T2>
-constexpr enable_if_t<!B, T2> _(const T1 &, const T2 &d) { return d; }
+constexpr enable_if_t<!B, T2> const_name(const T1 &, const T2 &d) {
+    return d;
+}
 
-template <size_t Size> auto constexpr _() -> decltype(int_to_str<Size / 10, Size % 10>::digits) {
+template <size_t Size>
+auto constexpr const_name() -> remove_cv_t<decltype(int_to_str<Size / 10, Size % 10>::digits)> {
     return int_to_str<Size / 10, Size % 10>::digits;
 }
 
-template <typename Type> constexpr descr<1, Type> _() { return {'%'}; }
+template <typename Type>
+constexpr descr<1, Type> const_name() {
+    return {'%'};
+}
+
+// If "_" is defined as a macro, py::detail::_ cannot be provided.
+// It is therefore best to use py::detail::const_name universally.
+// This block is for backward compatibility only.
+// (The const_name code is repeated to avoid introducing a "_" #define ourselves.)
+#ifndef _
+#    define PYBIND11_DETAIL_UNDERSCORE_BACKWARD_COMPATIBILITY
+template <size_t N>
+constexpr descr<N - 1> _(char const (&text)[N]) {
+    return const_name<N>(text);
+}
+template <bool B, size_t N1, size_t N2>
+constexpr enable_if_t<B, descr<N1 - 1>> _(char const (&text1)[N1], char const (&text2)[N2]) {
+    return const_name<B, N1, N2>(text1, text2);
+}
+template <bool B, size_t N1, size_t N2>
+constexpr enable_if_t<!B, descr<N2 - 1>> _(char const (&text1)[N1], char const (&text2)[N2]) {
+    return const_name<B, N1, N2>(text1, text2);
+}
+template <bool B, typename T1, typename T2>
+constexpr enable_if_t<B, T1> _(const T1 &d1, const T2 &d2) {
+    return const_name<B, T1, T2>(d1, d2);
+}
+template <bool B, typename T1, typename T2>
+constexpr enable_if_t<!B, T2> _(const T1 &d1, const T2 &d2) {
+    return const_name<B, T1, T2>(d1, d2);
+}
+
+template <size_t Size>
+auto constexpr _() -> remove_cv_t<decltype(int_to_str<Size / 10, Size % 10>::digits)> {
+    return const_name<Size>();
+}
+template <typename Type>
+constexpr descr<1, Type> _() {
+    return const_name<Type>();
+}
+#endif // #ifndef _
 
 constexpr descr<0> concat() { return {}; }
 
 template <size_t N, typename... Ts>
-constexpr descr<N, Ts...> concat(const descr<N, Ts...> &descr) { return descr; }
+constexpr descr<N, Ts...> concat(const descr<N, Ts...> &descr) {
+    return descr;
+}
 
 template <size_t N, typename... Ts, typename... Args>
 constexpr auto concat(const descr<N, Ts...> &d, const Args &...args)
     -> decltype(std::declval<descr<N + 2, Ts...>>() + concat(args...)) {
-    return d + _(", ") + concat(args...);
+    return d + const_name(", ") + concat(args...);
 }
 
 template <size_t N, typename... Ts>
 constexpr descr<N + 2, Ts...> type_descr(const descr<N, Ts...> &descr) {
-    return _("{") + descr + _("}");
+    return const_name("{") + descr + const_name("}");
 }
 
 PYBIND11_NAMESPACE_END(detail)
diff --git a/3rdparty/pybind11/include/pybind11/detail/init.h b/3rdparty/pybind11/include/pybind11/detail/init.h
index 3ef78c1179..05f4fe54aa 100644
--- a/3rdparty/pybind11/include/pybind11/detail/init.h
+++ b/3rdparty/pybind11/include/pybind11/detail/init.h
@@ -22,9 +22,10 @@ class type_caster<value_and_holder> {
         return true;
     }
 
-    template <typename> using cast_op_type = value_and_holder &;
-    operator value_and_holder &() { return *value; }
-    static constexpr auto name = _<value_and_holder>();
+    template <typename>
+    using cast_op_type = value_and_holder &;
+    explicit operator value_and_holder &() { return *value; }
+    static constexpr auto name = const_name<value_and_holder>();
 
 private:
     value_and_holder *value = nullptr;
@@ -33,15 +34,21 @@ class type_caster<value_and_holder> {
 PYBIND11_NAMESPACE_BEGIN(initimpl)
 
 inline void no_nullptr(void *ptr) {
-    if (!ptr) throw type_error("pybind11::init(): factory function returned nullptr");
+    if (!ptr) {
+        throw type_error("pybind11::init(): factory function returned nullptr");
+    }
 }
 
 // Implementing functions for all forms of py::init<...> and py::init(...)
-template <typename Class> using Cpp = typename Class::type;
-template <typename Class> using Alias = typename Class::type_alias;
-template <typename Class> using Holder = typename Class::holder_type;
+template <typename Class>
+using Cpp = typename Class::type;
+template <typename Class>
+using Alias = typename Class::type_alias;
+template <typename Class>
+using Holder = typename Class::holder_type;
 
-template <typename Class> using is_alias_constructible = std::is_constructible<Alias<Class>, Cpp<Class> &&>;
+template <typename Class>
+using is_alias_constructible = std::is_constructible<Alias<Class>, Cpp<Class> &&>;
 
 // Takes a Cpp pointer and returns true if it actually is a polymorphic Alias instance.
 template <typename Class, enable_if_t<Class::has_alias, int> = 0>
@@ -50,17 +57,27 @@ bool is_alias(Cpp<Class> *ptr) {
 }
 // Failing fallback version of the above for a no-alias class (always returns false)
 template <typename /*Class*/>
-constexpr bool is_alias(void *) { return false; }
+constexpr bool is_alias(void *) {
+    return false;
+}
 
 // Constructs and returns a new object; if the given arguments don't map to a constructor, we fall
 // back to brace aggregate initiailization so that for aggregate initialization can be used with
 // py::init, e.g.  `py::init<int, int>` to initialize a `struct T { int a; int b; }`.  For
 // non-aggregate types, we need to use an ordinary T(...) constructor (invoking as `T{...}` usually
 // works, but will not do the expected thing when `T` has an `initializer_list<T>` constructor).
-template <typename Class, typename... Args, detail::enable_if_t<std::is_constructible<Class, Args...>::value, int> = 0>
-inline Class *construct_or_initialize(Args &&...args) { return new Class(std::forward<Args>(args)...); }
-template <typename Class, typename... Args, detail::enable_if_t<!std::is_constructible<Class, Args...>::value, int> = 0>
-inline Class *construct_or_initialize(Args &&...args) { return new Class{std::forward<Args>(args)...}; }
+template <typename Class,
+          typename... Args,
+          detail::enable_if_t<std::is_constructible<Class, Args...>::value, int> = 0>
+inline Class *construct_or_initialize(Args &&...args) {
+    return new Class(std::forward<Args>(args)...);
+}
+template <typename Class,
+          typename... Args,
+          detail::enable_if_t<!std::is_constructible<Class, Args...>::value, int> = 0>
+inline Class *construct_or_initialize(Args &&...args) {
+    return new Class{std::forward<Args>(args)...};
+}
 
 // Attempts to constructs an alias using a `Alias(Cpp &&)` constructor.  This allows types with
 // an alias to provide only a single Cpp factory function as long as the Alias can be
@@ -69,12 +86,14 @@ inline Class *construct_or_initialize(Args &&...args) { return new Class{std::fo
 // inherit all the base class constructors.
 template <typename Class>
 void construct_alias_from_cpp(std::true_type /*is_alias_constructible*/,
-                              value_and_holder &v_h, Cpp<Class> &&base) {
+                              value_and_holder &v_h,
+                              Cpp<Class> &&base) {
     v_h.value_ptr() = new Alias<Class>(std::move(base));
 }
 template <typename Class>
 [[noreturn]] void construct_alias_from_cpp(std::false_type /*!is_alias_constructible*/,
-                                           value_and_holder &, Cpp<Class> &&) {
+                                           value_and_holder &,
+                                           Cpp<Class> &&) {
     throw type_error("pybind11::init(): unable to convert returned instance to required "
                      "alias class: no `Alias<Class>(Class &&)` constructor available");
 }
@@ -84,8 +103,8 @@ template <typename Class>
 template <typename Class>
 void construct(...) {
     static_assert(!std::is_same<Class, Class>::value /* always false */,
-            "pybind11::init(): init function must return a compatible pointer, "
-            "holder, or value");
+                  "pybind11::init(): init function must return a compatible pointer, "
+                  "holder, or value");
 }
 
 // Pointer return v1: the factory function returns a class pointer for a registered class.
@@ -94,8 +113,9 @@ void construct(...) {
 // construct an Alias from the returned base instance.
 template <typename Class>
 void construct(value_and_holder &v_h, Cpp<Class> *ptr, bool need_alias) {
+    PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(need_alias);
     no_nullptr(ptr);
-    if (Class::has_alias && need_alias && !is_alias<Class>(ptr)) {
+    if (PYBIND11_SILENCE_MSVC_C4127(Class::has_alias) && need_alias && !is_alias<Class>(ptr)) {
         // We're going to try to construct an alias by moving the cpp type.  Whether or not
         // that succeeds, we still need to destroy the original cpp pointer (either the
         // moved away leftover, if the alias construction works, or the value itself if we
@@ -105,7 +125,7 @@ void construct(value_and_holder &v_h, Cpp<Class> *ptr, bool need_alias) {
         // the holder and destruction happens when we leave the C++ scope, and the holder
         // class gets to handle the destruction however it likes.
         v_h.value_ptr() = ptr;
-        v_h.set_instance_registered(true); // To prevent init_instance from registering it
+        v_h.set_instance_registered(true);          // To prevent init_instance from registering it
         v_h.type->init_instance(v_h.inst, nullptr); // Set up the holder
         Holder<Class> temp_holder(std::move(v_h.holder<Holder<Class>>())); // Steal the holder
         v_h.type->dealloc(v_h); // Destroys the moved-out holder remains, resets value ptr to null
@@ -128,15 +148,18 @@ void construct(value_and_holder &v_h, Alias<Class> *alias_ptr, bool) {
 
 // Holder return: copy its pointer, and move or copy the returned holder into the new instance's
 // holder.  This also handles types like std::shared_ptr<T> and std::unique_ptr<T> where T is a
-// derived type (through those holder's implicit conversion from derived class holder constructors).
+// derived type (through those holder's implicit conversion from derived class holder
+// constructors).
 template <typename Class>
 void construct(value_and_holder &v_h, Holder<Class> holder, bool need_alias) {
+    PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(need_alias);
     auto *ptr = holder_helper<Holder<Class>>::get(holder);
     no_nullptr(ptr);
     // If we need an alias, check that the held pointer is actually an alias instance
-    if (Class::has_alias && need_alias && !is_alias<Class>(ptr))
+    if (PYBIND11_SILENCE_MSVC_C4127(Class::has_alias) && need_alias && !is_alias<Class>(ptr)) {
         throw type_error("pybind11::init(): construction failed: returned holder-wrapped instance "
                          "is not an alias instance");
+    }
 
     v_h.value_ptr() = ptr;
     v_h.type->init_instance(v_h.inst, &holder);
@@ -148,12 +171,14 @@ void construct(value_and_holder &v_h, Holder<Class> holder, bool need_alias) {
 // need it, we simply move-construct the cpp value into a new instance.
 template <typename Class>
 void construct(value_and_holder &v_h, Cpp<Class> &&result, bool need_alias) {
+    PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(need_alias);
     static_assert(std::is_move_constructible<Cpp<Class>>::value,
-        "pybind11::init() return-by-value factory function requires a movable class");
-    if (Class::has_alias && need_alias)
+                  "pybind11::init() return-by-value factory function requires a movable class");
+    if (PYBIND11_SILENCE_MSVC_C4127(Class::has_alias) && need_alias) {
         construct_alias_from_cpp<Class>(is_alias_constructible<Class>{}, v_h, std::move(result));
-    else
+    } else {
         v_h.value_ptr() = new Cpp<Class>(std::move(result));
+    }
 }
 
 // return-by-value version 2: returning a value of the alias type itself.  We move-construct an
@@ -161,7 +186,8 @@ void construct(value_and_holder &v_h, Cpp<Class> &&result, bool need_alias) {
 // cases where Alias initialization is always desired.
 template <typename Class>
 void construct(value_and_holder &v_h, Alias<Class> &&result, bool) {
-    static_assert(std::is_move_constructible<Alias<Class>>::value,
+    static_assert(
+        std::is_move_constructible<Alias<Class>>::value,
         "pybind11::init() return-by-alias-value factory function requires a movable alias class");
     v_h.value_ptr() = new Alias<Class>(std::move(result));
 }
@@ -170,48 +196,76 @@ void construct(value_and_holder &v_h, Alias<Class> &&result, bool) {
 template <typename... Args>
 struct constructor {
     template <typename Class, typename... Extra, enable_if_t<!Class::has_alias, int> = 0>
-    static void execute(Class &cl, const Extra&... extra) {
-        cl.def("__init__", [](value_and_holder &v_h, Args... args) {
-            v_h.value_ptr() = construct_or_initialize<Cpp<Class>>(std::forward<Args>(args)...);
-        }, is_new_style_constructor(), extra...);
+    static void execute(Class &cl, const Extra &...extra) {
+        cl.def(
+            "__init__",
+            [](value_and_holder &v_h, Args... args) {
+                v_h.value_ptr() = construct_or_initialize<Cpp<Class>>(std::forward<Args>(args)...);
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 
-    template <typename Class, typename... Extra,
-              enable_if_t<Class::has_alias &&
-                          std::is_constructible<Cpp<Class>, Args...>::value, int> = 0>
-    static void execute(Class &cl, const Extra&... extra) {
-        cl.def("__init__", [](value_and_holder &v_h, Args... args) {
-            if (Py_TYPE(v_h.inst) == v_h.type->type)
-                v_h.value_ptr() = construct_or_initialize<Cpp<Class>>(std::forward<Args>(args)...);
-            else
-                v_h.value_ptr() = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
-        }, is_new_style_constructor(), extra...);
+    template <typename Class,
+              typename... Extra,
+              enable_if_t<Class::has_alias && std::is_constructible<Cpp<Class>, Args...>::value,
+                          int> = 0>
+    static void execute(Class &cl, const Extra &...extra) {
+        cl.def(
+            "__init__",
+            [](value_and_holder &v_h, Args... args) {
+                if (Py_TYPE(v_h.inst) == v_h.type->type) {
+                    v_h.value_ptr()
+                        = construct_or_initialize<Cpp<Class>>(std::forward<Args>(args)...);
+                } else {
+                    v_h.value_ptr()
+                        = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
+                }
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 
-    template <typename Class, typename... Extra,
-              enable_if_t<Class::has_alias &&
-                          !std::is_constructible<Cpp<Class>, Args...>::value, int> = 0>
-    static void execute(Class &cl, const Extra&... extra) {
-        cl.def("__init__", [](value_and_holder &v_h, Args... args) {
-            v_h.value_ptr() = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
-        }, is_new_style_constructor(), extra...);
+    template <typename Class,
+              typename... Extra,
+              enable_if_t<Class::has_alias && !std::is_constructible<Cpp<Class>, Args...>::value,
+                          int> = 0>
+    static void execute(Class &cl, const Extra &...extra) {
+        cl.def(
+            "__init__",
+            [](value_and_holder &v_h, Args... args) {
+                v_h.value_ptr()
+                    = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 };
 
 // Implementing class for py::init_alias<...>()
-template <typename... Args> struct alias_constructor {
-    template <typename Class, typename... Extra,
-              enable_if_t<Class::has_alias && std::is_constructible<Alias<Class>, Args...>::value, int> = 0>
-    static void execute(Class &cl, const Extra&... extra) {
-        cl.def("__init__", [](value_and_holder &v_h, Args... args) {
-            v_h.value_ptr() = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
-        }, is_new_style_constructor(), extra...);
+template <typename... Args>
+struct alias_constructor {
+    template <typename Class,
+              typename... Extra,
+              enable_if_t<Class::has_alias && std::is_constructible<Alias<Class>, Args...>::value,
+                          int> = 0>
+    static void execute(Class &cl, const Extra &...extra) {
+        cl.def(
+            "__init__",
+            [](value_and_holder &v_h, Args... args) {
+                v_h.value_ptr()
+                    = construct_or_initialize<Alias<Class>>(std::forward<Args>(args)...);
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 };
 
 // Implementation class for py::init(Func) and py::init(Func, AliasFunc)
-template <typename CFunc, typename AFunc = void_type (*)(),
-          typename = function_signature_t<CFunc>, typename = function_signature_t<AFunc>>
+template <typename CFunc,
+          typename AFunc = void_type (*)(),
+          typename = function_signature_t<CFunc>,
+          typename = function_signature_t<AFunc>>
 struct factory;
 
 // Specialization for py::init(Func)
@@ -219,7 +273,8 @@ template <typename Func, typename Return, typename... Args>
 struct factory<Func, void_type (*)(), Return(Args...)> {
     remove_reference_t<Func> class_factory;
 
-    factory(Func &&f) : class_factory(std::forward<Func>(f)) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    factory(Func &&f) : class_factory(std::forward<Func>(f)) {}
 
     // The given class either has no alias or has no separate alias factory;
     // this always constructs the class itself.  If the class is registered with an alias
@@ -228,22 +283,32 @@ struct factory<Func, void_type (*)(), Return(Args...)> {
     // instance, or the alias needs to be constructible from a `Class &&` argument.
     template <typename Class, typename... Extra>
     void execute(Class &cl, const Extra &...extra) && {
-        #if defined(PYBIND11_CPP14)
-        cl.def("__init__", [func = std::move(class_factory)]
-        #else
+#if defined(PYBIND11_CPP14)
+        cl.def(
+            "__init__",
+            [func = std::move(class_factory)]
+#else
         auto &func = class_factory;
-        cl.def("__init__", [func]
-        #endif
-        (value_and_holder &v_h, Args... args) {
-            construct<Class>(v_h, func(std::forward<Args>(args)...),
-                             Py_TYPE(v_h.inst) != v_h.type->type);
-        }, is_new_style_constructor(), extra...);
+        cl.def(
+            "__init__",
+            [func]
+#endif
+            (value_and_holder &v_h, Args... args) {
+                construct<Class>(
+                    v_h, func(std::forward<Args>(args)...), Py_TYPE(v_h.inst) != v_h.type->type);
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 };
 
 // Specialization for py::init(Func, AliasFunc)
-template <typename CFunc, typename AFunc,
-          typename CReturn, typename... CArgs, typename AReturn, typename... AArgs>
+template <typename CFunc,
+          typename AFunc,
+          typename CReturn,
+          typename... CArgs,
+          typename AReturn,
+          typename... AArgs>
 struct factory<CFunc, AFunc, CReturn(CArgs...), AReturn(AArgs...)> {
     static_assert(sizeof...(CArgs) == sizeof...(AArgs),
                   "pybind11::init(class_factory, alias_factory): class and alias factories "
@@ -256,29 +321,37 @@ struct factory<CFunc, AFunc, CReturn(CArgs...), AReturn(AArgs...)> {
     remove_reference_t<AFunc> alias_factory;
 
     factory(CFunc &&c, AFunc &&a)
-        : class_factory(std::forward<CFunc>(c)), alias_factory(std::forward<AFunc>(a)) { }
+        : class_factory(std::forward<CFunc>(c)), alias_factory(std::forward<AFunc>(a)) {}
 
     // The class factory is called when the `self` type passed to `__init__` is the direct
     // class (i.e. not inherited), the alias factory when `self` is a Python-side subtype.
     template <typename Class, typename... Extra>
-    void execute(Class &cl, const Extra&... extra) && {
-        static_assert(Class::has_alias, "The two-argument version of `py::init()` can "
-                                        "only be used if the class has an alias");
-        #if defined(PYBIND11_CPP14)
-        cl.def("__init__", [class_func = std::move(class_factory), alias_func = std::move(alias_factory)]
-        #else
+    void execute(Class &cl, const Extra &...extra) && {
+        static_assert(Class::has_alias,
+                      "The two-argument version of `py::init()` can "
+                      "only be used if the class has an alias");
+#if defined(PYBIND11_CPP14)
+        cl.def(
+            "__init__",
+            [class_func = std::move(class_factory), alias_func = std::move(alias_factory)]
+#else
         auto &class_func = class_factory;
         auto &alias_func = alias_factory;
-        cl.def("__init__", [class_func, alias_func]
-        #endif
-        (value_and_holder &v_h, CArgs... args) {
-            if (Py_TYPE(v_h.inst) == v_h.type->type)
-                // If the instance type equals the registered type we don't have inheritance, so
-                // don't need the alias and can construct using the class function:
-                construct<Class>(v_h, class_func(std::forward<CArgs>(args)...), false);
-            else
-                construct<Class>(v_h, alias_func(std::forward<CArgs>(args)...), true);
-        }, is_new_style_constructor(), extra...);
+        cl.def(
+            "__init__",
+            [class_func, alias_func]
+#endif
+            (value_and_holder &v_h, CArgs... args) {
+                if (Py_TYPE(v_h.inst) == v_h.type->type) {
+                    // If the instance type equals the registered type we don't have inheritance,
+                    // so don't need the alias and can construct using the class function:
+                    construct<Class>(v_h, class_func(std::forward<CArgs>(args)...), false);
+                } else {
+                    construct<Class>(v_h, alias_func(std::forward<CArgs>(args)...), true);
+                }
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 };
 
@@ -289,20 +362,34 @@ void setstate(value_and_holder &v_h, T &&result, bool need_alias) {
 }
 
 /// Set both the C++ and Python states
-template <typename Class, typename T, typename O,
+template <typename Class,
+          typename T,
+          typename O,
           enable_if_t<std::is_convertible<O, handle>::value, int> = 0>
 void setstate(value_and_holder &v_h, std::pair<T, O> &&result, bool need_alias) {
     construct<Class>(v_h, std::move(result.first), need_alias);
-    setattr((PyObject *) v_h.inst, "__dict__", result.second);
+    auto d = handle(result.second);
+    if (PyDict_Check(d.ptr()) && PyDict_Size(d.ptr()) == 0) {
+        // Skipping setattr below, to not force use of py::dynamic_attr() for Class unnecessarily.
+        // See PR #2972 for details.
+        return;
+    }
+    setattr((PyObject *) v_h.inst, "__dict__", d);
 }
 
 /// Implementation for py::pickle(GetState, SetState)
-template <typename Get, typename Set,
-          typename = function_signature_t<Get>, typename = function_signature_t<Set>>
+template <typename Get,
+          typename Set,
+          typename = function_signature_t<Get>,
+          typename = function_signature_t<Set>>
 struct pickle_factory;
 
-template <typename Get, typename Set,
-          typename RetState, typename Self, typename NewInstance, typename ArgState>
+template <typename Get,
+          typename Set,
+          typename RetState,
+          typename Self,
+          typename NewInstance,
+          typename ArgState>
 struct pickle_factory<Get, Set, RetState(Self), NewInstance(ArgState)> {
     static_assert(std::is_same<intrinsic_t<RetState>, intrinsic_t<ArgState>>::value,
                   "The type returned by `__getstate__` must be the same "
@@ -311,26 +398,31 @@ struct pickle_factory<Get, Set, RetState(Self), NewInstance(ArgState)> {
     remove_reference_t<Get> get;
     remove_reference_t<Set> set;
 
-    pickle_factory(Get get, Set set)
-        : get(std::forward<Get>(get)), set(std::forward<Set>(set)) { }
+    pickle_factory(Get get, Set set) : get(std::forward<Get>(get)), set(std::forward<Set>(set)) {}
 
     template <typename Class, typename... Extra>
     void execute(Class &cl, const Extra &...extra) && {
         cl.def("__getstate__", std::move(get));
 
 #if defined(PYBIND11_CPP14)
-        cl.def("__setstate__", [func = std::move(set)]
+        cl.def(
+            "__setstate__",
+            [func = std::move(set)]
 #else
         auto &func = set;
-        cl.def("__setstate__", [func]
+        cl.def(
+            "__setstate__",
+            [func]
 #endif
-        (value_and_holder &v_h, ArgState state) {
-            setstate<Class>(v_h, func(std::forward<ArgState>(state)),
-                            Py_TYPE(v_h.inst) != v_h.type->type);
-        }, is_new_style_constructor(), extra...);
+            (value_and_holder &v_h, ArgState state) {
+                setstate<Class>(
+                    v_h, func(std::forward<ArgState>(state)), Py_TYPE(v_h.inst) != v_h.type->type);
+            },
+            is_new_style_constructor(),
+            extra...);
     }
 };
 
 PYBIND11_NAMESPACE_END(initimpl)
 PYBIND11_NAMESPACE_END(detail)
-PYBIND11_NAMESPACE_END(pybind11)
+PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/detail/internals.h b/3rdparty/pybind11/include/pybind11/detail/internals.h
index a455715bfd..6ca5e1482f 100644
--- a/3rdparty/pybind11/include/pybind11/detail/internals.h
+++ b/3rdparty/pybind11/include/pybind11/detail/internals.h
@@ -11,8 +11,32 @@
 
 #include "../pytypes.h"
 
+#include <exception>
+
+/// Tracks the `internals` and `type_info` ABI version independent of the main library version.
+///
+/// Some portions of the code use an ABI that is conditional depending on this
+/// version number.  That allows ABI-breaking changes to be "pre-implemented".
+/// Once the default version number is incremented, the conditional logic that
+/// no longer applies can be removed.  Additionally, users that need not
+/// maintain ABI compatibility can increase the version number in order to take
+/// advantage of any functionality/efficiency improvements that depend on the
+/// newer ABI.
+///
+/// WARNING: If you choose to manually increase the ABI version, note that
+/// pybind11 may not be tested as thoroughly with a non-default ABI version, and
+/// further ABI-incompatible changes may be made before the ABI is officially
+/// changed to the new version.
+#ifndef PYBIND11_INTERNALS_VERSION
+#    define PYBIND11_INTERNALS_VERSION 4
+#endif
+
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
+
+using ExceptionTranslator = void (*)(std::exception_ptr);
+
 PYBIND11_NAMESPACE_BEGIN(detail)
+
 // Forward declarations
 inline PyTypeObject *make_static_property_type();
 inline PyTypeObject *make_default_metaclass();
@@ -21,30 +45,59 @@ inline PyObject *make_object_base_type(PyTypeObject *metaclass);
 // The old Python Thread Local Storage (TLS) API is deprecated in Python 3.7 in favor of the new
 // Thread Specific Storage (TSS) API.
 #if PY_VERSION_HEX >= 0x03070000
-#    define PYBIND11_TLS_KEY_INIT(var) Py_tss_t *var = nullptr
-#    define PYBIND11_TLS_GET_VALUE(key) PyThread_tss_get((key))
-#    define PYBIND11_TLS_REPLACE_VALUE(key, value) PyThread_tss_set((key), (value))
-#    define PYBIND11_TLS_DELETE_VALUE(key) PyThread_tss_set((key), nullptr)
-#    define PYBIND11_TLS_FREE(key) PyThread_tss_free(key)
+// Avoid unnecessary allocation of `Py_tss_t`, since we cannot use
+// `Py_LIMITED_API` anyway.
+#    if PYBIND11_INTERNALS_VERSION > 4
+#        define PYBIND11_TLS_KEY_REF Py_tss_t &
+#        ifdef __GNUC__
+// Clang on macOS warns due to `Py_tss_NEEDS_INIT` not specifying an initializer
+// for every field.
+#            define PYBIND11_TLS_KEY_INIT(var)                                                    \
+                _Pragma("GCC diagnostic push")                                         /**/       \
+                    _Pragma("GCC diagnostic ignored \"-Wmissing-field-initializers\"") /**/       \
+                    Py_tss_t var                                                                  \
+                    = Py_tss_NEEDS_INIT;                                                          \
+                _Pragma("GCC diagnostic pop")
+#        else
+#            define PYBIND11_TLS_KEY_INIT(var) Py_tss_t var = Py_tss_NEEDS_INIT;
+#        endif
+#        define PYBIND11_TLS_KEY_CREATE(var) (PyThread_tss_create(&(var)) == 0)
+#        define PYBIND11_TLS_GET_VALUE(key) PyThread_tss_get(&(key))
+#        define PYBIND11_TLS_REPLACE_VALUE(key, value) PyThread_tss_set(&(key), (value))
+#        define PYBIND11_TLS_DELETE_VALUE(key) PyThread_tss_set(&(key), nullptr)
+#        define PYBIND11_TLS_FREE(key) PyThread_tss_delete(&(key))
+#    else
+#        define PYBIND11_TLS_KEY_REF Py_tss_t *
+#        define PYBIND11_TLS_KEY_INIT(var) Py_tss_t *var = nullptr;
+#        define PYBIND11_TLS_KEY_CREATE(var)                                                      \
+            (((var) = PyThread_tss_alloc()) != nullptr && (PyThread_tss_create((var)) == 0))
+#        define PYBIND11_TLS_GET_VALUE(key) PyThread_tss_get((key))
+#        define PYBIND11_TLS_REPLACE_VALUE(key, value) PyThread_tss_set((key), (value))
+#        define PYBIND11_TLS_DELETE_VALUE(key) PyThread_tss_set((key), nullptr)
+#        define PYBIND11_TLS_FREE(key) PyThread_tss_free(key)
+#    endif
 #else
-    // Usually an int but a long on Cygwin64 with Python 3.x
-#    define PYBIND11_TLS_KEY_INIT(var) decltype(PyThread_create_key()) var = 0
+// Usually an int but a long on Cygwin64 with Python 3.x
+#    define PYBIND11_TLS_KEY_REF decltype(PyThread_create_key())
+#    define PYBIND11_TLS_KEY_INIT(var) PYBIND11_TLS_KEY_REF var = 0;
+#    define PYBIND11_TLS_KEY_CREATE(var) (((var) = PyThread_create_key()) != -1)
 #    define PYBIND11_TLS_GET_VALUE(key) PyThread_get_key_value((key))
-#    if PY_MAJOR_VERSION < 3
-#        define PYBIND11_TLS_DELETE_VALUE(key)                               \
-             PyThread_delete_key_value(key)
-#        define PYBIND11_TLS_REPLACE_VALUE(key, value)                       \
-             do {                                                            \
-                 PyThread_delete_key_value((key));                           \
-                 PyThread_set_key_value((key), (value));                     \
-             } while (false)
+#    if defined(PYPY_VERSION)
+// On CPython < 3.4 and on PyPy, `PyThread_set_key_value` strangely does not set
+// the value if it has already been set.  Instead, it must first be deleted and
+// then set again.
+inline void tls_replace_value(PYBIND11_TLS_KEY_REF key, void *value) {
+    PyThread_delete_key_value(key);
+    PyThread_set_key_value(key, value);
+}
+#        define PYBIND11_TLS_DELETE_VALUE(key) PyThread_delete_key_value(key)
+#        define PYBIND11_TLS_REPLACE_VALUE(key, value)                                            \
+            ::pybind11::detail::tls_replace_value((key), (value))
 #    else
-#        define PYBIND11_TLS_DELETE_VALUE(key)                               \
-             PyThread_set_key_value((key), nullptr)
-#        define PYBIND11_TLS_REPLACE_VALUE(key, value)                       \
-             PyThread_set_key_value((key), (value))
+#        define PYBIND11_TLS_DELETE_VALUE(key) PyThread_set_key_value((key), nullptr)
+#        define PYBIND11_TLS_REPLACE_VALUE(key, value) PyThread_set_key_value((key), (value))
 #    endif
-#    define PYBIND11_TLS_FREE(key) (void)key
+#    define PYBIND11_TLS_FREE(key) (void) key
 #endif
 
 // Python loads modules by default with dlopen with the RTLD_LOCAL flag; under libc++ and possibly
@@ -66,8 +119,9 @@ struct type_hash {
     size_t operator()(const std::type_index &t) const {
         size_t hash = 5381;
         const char *ptr = t.name();
-        while (auto c = static_cast<unsigned char>(*ptr++))
+        while (auto c = static_cast<unsigned char>(*ptr++)) {
             hash = (hash * 33) ^ c;
+        }
         return hash;
     }
 };
@@ -83,9 +137,9 @@ template <typename value_type>
 using type_map = std::unordered_map<std::type_index, value_type, type_hash, type_equal_to>;
 
 struct override_hash {
-    inline size_t operator()(const std::pair<const PyObject *, const char *>& v) const {
+    inline size_t operator()(const std::pair<const PyObject *, const char *> &v) const {
         size_t value = std::hash<const void *>()(v.first);
-        value ^= std::hash<const void *>()(v.second) + 0x9e3779b9 + (value<<6) + (value>>2);
+        value ^= std::hash<const void *>()(v.second) + 0x9e3779b9 + (value << 6) + (value >> 2);
         return value;
     }
 };
@@ -94,30 +148,44 @@ struct override_hash {
 /// Whenever binary incompatible changes are made to this structure,
 /// `PYBIND11_INTERNALS_VERSION` must be incremented.
 struct internals {
-    type_map<type_info *> registered_types_cpp; // std::type_index -> pybind11's type information
-    std::unordered_map<PyTypeObject *, std::vector<type_info *>> registered_types_py; // PyTypeObject* -> base type_info(s)
-    std::unordered_multimap<const void *, instance*> registered_instances; // void * -> instance*
-    std::unordered_set<std::pair<const PyObject *, const char *>, override_hash> inactive_override_cache;
+    // std::type_index -> pybind11's type information
+    type_map<type_info *> registered_types_cpp;
+    // PyTypeObject* -> base type_info(s)
+    std::unordered_map<PyTypeObject *, std::vector<type_info *>> registered_types_py;
+    std::unordered_multimap<const void *, instance *> registered_instances; // void * -> instance*
+    std::unordered_set<std::pair<const PyObject *, const char *>, override_hash>
+        inactive_override_cache;
     type_map<std::vector<bool (*)(PyObject *, void *&)>> direct_conversions;
     std::unordered_map<const PyObject *, std::vector<PyObject *>> patients;
-    std::forward_list<void (*) (std::exception_ptr)> registered_exception_translators;
-    std::unordered_map<std::string, void *> shared_data; // Custom data to be shared across extensions
-    std::vector<PyObject *> loader_patient_stack; // Used by `loader_life_support`
-    std::forward_list<std::string> static_strings; // Stores the std::strings backing detail::c_str()
+    std::forward_list<ExceptionTranslator> registered_exception_translators;
+    std::unordered_map<std::string, void *> shared_data; // Custom data to be shared across
+                                                         // extensions
+#if PYBIND11_INTERNALS_VERSION == 4
+    std::vector<PyObject *> unused_loader_patient_stack_remove_at_v5;
+#endif
+    std::forward_list<std::string> static_strings; // Stores the std::strings backing
+                                                   // detail::c_str()
     PyTypeObject *static_property_type;
     PyTypeObject *default_metaclass;
     PyObject *instance_base;
 #if defined(WITH_THREAD)
-    PYBIND11_TLS_KEY_INIT(tstate);
+    PYBIND11_TLS_KEY_INIT(tstate)
+#    if PYBIND11_INTERNALS_VERSION > 4
+    PYBIND11_TLS_KEY_INIT(loader_life_support_tls_key)
+#    endif // PYBIND11_INTERNALS_VERSION > 4
     PyInterpreterState *istate = nullptr;
     ~internals() {
+#    if PYBIND11_INTERNALS_VERSION > 4
+        PYBIND11_TLS_FREE(loader_life_support_tls_key);
+#    endif // PYBIND11_INTERNALS_VERSION > 4
+
         // This destructor is called *after* Py_Finalize() in finalize_interpreter().
-        // That *SHOULD BE* fine. The following details what happens whe PyThread_tss_free is called.
-        // PYBIND11_TLS_FREE is PyThread_tss_free on python 3.7+. On older python, it does nothing.
-        // PyThread_tss_free calls PyThread_tss_delete and PyMem_RawFree.
-        // PyThread_tss_delete just calls TlsFree (on Windows) or pthread_key_delete (on *NIX). Neither
-        // of those have anything to do with CPython internals.
-        // PyMem_RawFree *requires* that the `tstate` be allocated with the CPython allocator.
+        // That *SHOULD BE* fine. The following details what happens when PyThread_tss_free is
+        // called. PYBIND11_TLS_FREE is PyThread_tss_free on python 3.7+. On older python, it does
+        // nothing. PyThread_tss_free calls PyThread_tss_delete and PyMem_RawFree.
+        // PyThread_tss_delete just calls TlsFree (on Windows) or pthread_key_delete (on *NIX).
+        // Neither of those have anything to do with CPython internals. PyMem_RawFree *requires*
+        // that the `tstate` be allocated with the CPython allocator.
         PYBIND11_TLS_FREE(tstate);
     }
 #endif
@@ -132,14 +200,16 @@ struct type_info {
     void *(*operator_new)(size_t);
     void (*init_instance)(instance *, const void *);
     void (*dealloc)(value_and_holder &v_h);
-    std::vector<PyObject *(*)(PyObject *, PyTypeObject *)> implicit_conversions;
-    std::vector<std::pair<const std::type_info *, void *(*)(void *)>> implicit_casts;
+    std::vector<PyObject *(*) (PyObject *, PyTypeObject *)> implicit_conversions;
+    std::vector<std::pair<const std::type_info *, void *(*) (void *)>> implicit_casts;
     std::vector<bool (*)(PyObject *, void *&)> *direct_conversions;
     buffer_info *(*get_buffer)(PyObject *, void *) = nullptr;
     void *get_buffer_data = nullptr;
     void *(*module_local_load)(PyObject *, const type_info *) = nullptr;
     /* A simple type never occurs as a (direct or indirect) parent
-     * of a class that makes use of multiple inheritance */
+     * of a class that makes use of multiple inheritance.
+     * A type can be simple even if it has non-simple ancestors as long as it has no descendants.
+     */
     bool simple_type : 1;
     /* True if there is no multiple inheritance in this type's inheritance tree */
     bool simple_ancestors : 1;
@@ -149,72 +219,73 @@ struct type_info {
     bool module_local : 1;
 };
 
-/// Tracks the `internals` and `type_info` ABI version independent of the main library version
-#define PYBIND11_INTERNALS_VERSION 4
-
 /// On MSVC, debug and release builds are not ABI-compatible!
 #if defined(_MSC_VER) && defined(_DEBUG)
-#  define PYBIND11_BUILD_TYPE "_debug"
+#    define PYBIND11_BUILD_TYPE "_debug"
 #else
-#  define PYBIND11_BUILD_TYPE ""
+#    define PYBIND11_BUILD_TYPE ""
 #endif
 
 /// Let's assume that different compilers are ABI-incompatible.
 /// A user can manually set this string if they know their
 /// compiler is compatible.
 #ifndef PYBIND11_COMPILER_TYPE
-#  if defined(_MSC_VER)
-#    define PYBIND11_COMPILER_TYPE "_msvc"
-#  elif defined(__INTEL_COMPILER)
-#    define PYBIND11_COMPILER_TYPE "_icc"
-#  elif defined(__clang__)
-#    define PYBIND11_COMPILER_TYPE "_clang"
-#  elif defined(__PGI)
-#    define PYBIND11_COMPILER_TYPE "_pgi"
-#  elif defined(__MINGW32__)
-#    define PYBIND11_COMPILER_TYPE "_mingw"
-#  elif defined(__CYGWIN__)
-#    define PYBIND11_COMPILER_TYPE "_gcc_cygwin"
-#  elif defined(__GNUC__)
-#    define PYBIND11_COMPILER_TYPE "_gcc"
-#  else
-#    define PYBIND11_COMPILER_TYPE "_unknown"
-#  endif
+#    if defined(_MSC_VER)
+#        define PYBIND11_COMPILER_TYPE "_msvc"
+#    elif defined(__INTEL_COMPILER)
+#        define PYBIND11_COMPILER_TYPE "_icc"
+#    elif defined(__clang__)
+#        define PYBIND11_COMPILER_TYPE "_clang"
+#    elif defined(__PGI)
+#        define PYBIND11_COMPILER_TYPE "_pgi"
+#    elif defined(__MINGW32__)
+#        define PYBIND11_COMPILER_TYPE "_mingw"
+#    elif defined(__CYGWIN__)
+#        define PYBIND11_COMPILER_TYPE "_gcc_cygwin"
+#    elif defined(__GNUC__)
+#        define PYBIND11_COMPILER_TYPE "_gcc"
+#    else
+#        define PYBIND11_COMPILER_TYPE "_unknown"
+#    endif
 #endif
 
 /// Also standard libs
 #ifndef PYBIND11_STDLIB
-#  if defined(_LIBCPP_VERSION)
-#    define PYBIND11_STDLIB "_libcpp"
-#  elif defined(__GLIBCXX__) || defined(__GLIBCPP__)
-#    define PYBIND11_STDLIB "_libstdcpp"
-#  else
-#    define PYBIND11_STDLIB ""
-#  endif
+#    if defined(_LIBCPP_VERSION)
+#        define PYBIND11_STDLIB "_libcpp"
+#    elif defined(__GLIBCXX__) || defined(__GLIBCPP__)
+#        define PYBIND11_STDLIB "_libstdcpp"
+#    else
+#        define PYBIND11_STDLIB ""
+#    endif
 #endif
 
 /// On Linux/OSX, changes in __GXX_ABI_VERSION__ indicate ABI incompatibility.
 #ifndef PYBIND11_BUILD_ABI
-#  if defined(__GXX_ABI_VERSION)
-#    define PYBIND11_BUILD_ABI "_cxxabi" PYBIND11_TOSTRING(__GXX_ABI_VERSION)
-#  else
-#    define PYBIND11_BUILD_ABI ""
-#  endif
+#    if defined(__GXX_ABI_VERSION)
+#        define PYBIND11_BUILD_ABI "_cxxabi" PYBIND11_TOSTRING(__GXX_ABI_VERSION)
+#    else
+#        define PYBIND11_BUILD_ABI ""
+#    endif
 #endif
 
 #ifndef PYBIND11_INTERNALS_KIND
-#  if defined(WITH_THREAD)
-#    define PYBIND11_INTERNALS_KIND ""
-#  else
-#    define PYBIND11_INTERNALS_KIND "_without_thread"
-#  endif
+#    if defined(WITH_THREAD)
+#        define PYBIND11_INTERNALS_KIND ""
+#    else
+#        define PYBIND11_INTERNALS_KIND "_without_thread"
+#    endif
 #endif
 
-#define PYBIND11_INTERNALS_ID "__pybind11_internals_v" \
-    PYBIND11_TOSTRING(PYBIND11_INTERNALS_VERSION) PYBIND11_INTERNALS_KIND PYBIND11_COMPILER_TYPE PYBIND11_STDLIB PYBIND11_BUILD_ABI PYBIND11_BUILD_TYPE "__"
+#define PYBIND11_INTERNALS_ID                                                                     \
+    "__pybind11_internals_v" PYBIND11_TOSTRING(PYBIND11_INTERNALS_VERSION)                        \
+        PYBIND11_INTERNALS_KIND PYBIND11_COMPILER_TYPE PYBIND11_STDLIB PYBIND11_BUILD_ABI         \
+            PYBIND11_BUILD_TYPE "__"
 
-#define PYBIND11_MODULE_LOCAL_ID "__pybind11_module_local_v" \
-    PYBIND11_TOSTRING(PYBIND11_INTERNALS_VERSION) PYBIND11_INTERNALS_KIND PYBIND11_COMPILER_TYPE PYBIND11_STDLIB PYBIND11_BUILD_ABI PYBIND11_BUILD_TYPE "__"
+#define PYBIND11_MODULE_LOCAL_ID                                                                  \
+    "__pybind11_module_local_v" PYBIND11_TOSTRING(PYBIND11_INTERNALS_VERSION)                     \
+        PYBIND11_INTERNALS_KIND PYBIND11_COMPILER_TYPE PYBIND11_STDLIB PYBIND11_BUILD_ABI         \
+            PYBIND11_BUILD_TYPE "__"
 
 /// Each module locally stores a pointer to the `internals` data. The data
 /// itself is shared among modules with the same `PYBIND11_INTERNALS_ID`.
@@ -223,21 +294,93 @@ inline internals **&get_internals_pp() {
     return internals_pp;
 }
 
+// forward decl
+inline void translate_exception(std::exception_ptr);
+
+template <class T,
+          enable_if_t<std::is_same<std::nested_exception, remove_cvref_t<T>>::value, int> = 0>
+bool handle_nested_exception(const T &exc, const std::exception_ptr &p) {
+    std::exception_ptr nested = exc.nested_ptr();
+    if (nested != nullptr && nested != p) {
+        translate_exception(nested);
+        return true;
+    }
+    return false;
+}
+
+template <class T,
+          enable_if_t<!std::is_same<std::nested_exception, remove_cvref_t<T>>::value, int> = 0>
+bool handle_nested_exception(const T &exc, const std::exception_ptr &p) {
+    if (const auto *nep = dynamic_cast<const std::nested_exception *>(std::addressof(exc))) {
+        return handle_nested_exception(*nep, p);
+    }
+    return false;
+}
+
+inline bool raise_err(PyObject *exc_type, const char *msg) {
+    if (PyErr_Occurred()) {
+        raise_from(exc_type, msg);
+        return true;
+    }
+    PyErr_SetString(exc_type, msg);
+    return false;
+}
+
 inline void translate_exception(std::exception_ptr p) {
+    if (!p) {
+        return;
+    }
     try {
-        if (p) std::rethrow_exception(p);
-    } catch (error_already_set &e)           { e.restore();                                    return;
-    } catch (const builtin_exception &e)     { e.set_error();                                  return;
-    } catch (const std::bad_alloc &e)        { PyErr_SetString(PyExc_MemoryError,   e.what()); return;
-    } catch (const std::domain_error &e)     { PyErr_SetString(PyExc_ValueError,    e.what()); return;
-    } catch (const std::invalid_argument &e) { PyErr_SetString(PyExc_ValueError,    e.what()); return;
-    } catch (const std::length_error &e)     { PyErr_SetString(PyExc_ValueError,    e.what()); return;
-    } catch (const std::out_of_range &e)     { PyErr_SetString(PyExc_IndexError,    e.what()); return;
-    } catch (const std::range_error &e)      { PyErr_SetString(PyExc_ValueError,    e.what()); return;
-    } catch (const std::overflow_error &e)   { PyErr_SetString(PyExc_OverflowError, e.what()); return;
-    } catch (const std::exception &e)        { PyErr_SetString(PyExc_RuntimeError,  e.what()); return;
+        std::rethrow_exception(p);
+    } catch (error_already_set &e) {
+        handle_nested_exception(e, p);
+        e.restore();
+        return;
+    } catch (const builtin_exception &e) {
+        // Could not use template since it's an abstract class.
+        if (const auto *nep = dynamic_cast<const std::nested_exception *>(std::addressof(e))) {
+            handle_nested_exception(*nep, p);
+        }
+        e.set_error();
+        return;
+    } catch (const std::bad_alloc &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_MemoryError, e.what());
+        return;
+    } catch (const std::domain_error &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_ValueError, e.what());
+        return;
+    } catch (const std::invalid_argument &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_ValueError, e.what());
+        return;
+    } catch (const std::length_error &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_ValueError, e.what());
+        return;
+    } catch (const std::out_of_range &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_IndexError, e.what());
+        return;
+    } catch (const std::range_error &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_ValueError, e.what());
+        return;
+    } catch (const std::overflow_error &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_OverflowError, e.what());
+        return;
+    } catch (const std::exception &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_RuntimeError, e.what());
+        return;
+    } catch (const std::nested_exception &e) {
+        handle_nested_exception(e, p);
+        raise_err(PyExc_RuntimeError, "Caught an unknown nested exception!");
+        return;
     } catch (...) {
-        PyErr_SetString(PyExc_RuntimeError, "Caught an unknown exception!");
+        raise_err(PyExc_RuntimeError, "Caught an unknown exception!");
         return;
     }
 }
@@ -245,28 +388,36 @@ inline void translate_exception(std::exception_ptr p) {
 #if !defined(__GLIBCXX__)
 inline void translate_local_exception(std::exception_ptr p) {
     try {
-        if (p) std::rethrow_exception(p);
-    } catch (error_already_set &e)       { e.restore();   return;
-    } catch (const builtin_exception &e) { e.set_error(); return;
+        if (p) {
+            std::rethrow_exception(p);
+        }
+    } catch (error_already_set &e) {
+        e.restore();
+        return;
+    } catch (const builtin_exception &e) {
+        e.set_error();
+        return;
     }
 }
 #endif
 
 /// Return a reference to the current `internals` data
-PYBIND11_NOINLINE inline internals &get_internals() {
+PYBIND11_NOINLINE internals &get_internals() {
     auto **&internals_pp = get_internals_pp();
-    if (internals_pp && *internals_pp)
+    if (internals_pp && *internals_pp) {
         return **internals_pp;
+    }
 
     // Ensure that the GIL is held since we will need to make Python calls.
     // Cannot use py::gil_scoped_acquire here since that constructor calls get_internals.
     struct gil_scoped_acquire_local {
-        gil_scoped_acquire_local() : state (PyGILState_Ensure()) {}
+        gil_scoped_acquire_local() : state(PyGILState_Ensure()) {}
         ~gil_scoped_acquire_local() { PyGILState_Release(state); }
         const PyGILState_STATE state;
     } gil;
+    error_scope err_scope;
 
-    constexpr auto *id = PYBIND11_INTERNALS_ID;
+    PYBIND11_STR_TYPE id(PYBIND11_INTERNALS_ID);
     auto builtins = handle(PyEval_GetBuiltins());
     if (builtins.contains(id) && isinstance<capsule>(builtins[id])) {
         internals_pp = static_cast<internals **>(capsule(builtins[id]));
@@ -276,30 +427,34 @@ PYBIND11_NOINLINE inline internals &get_internals() {
         // initial exception translator, below, so add another for our local exception classes.
         //
         // libstdc++ doesn't require this (types there are identified only by name)
+        // libc++ with CPython doesn't require this (types are explicitly exported)
+        // libc++ with PyPy still need it, awaiting further investigation
 #if !defined(__GLIBCXX__)
         (*internals_pp)->registered_exception_translators.push_front(&translate_local_exception);
 #endif
     } else {
-        if (!internals_pp) internals_pp = new internals*();
+        if (!internals_pp) {
+            internals_pp = new internals *();
+        }
         auto *&internals_ptr = *internals_pp;
         internals_ptr = new internals();
 #if defined(WITH_THREAD)
 
-        #if PY_VERSION_HEX < 0x03090000
-                PyEval_InitThreads();
-        #endif
+#    if PY_VERSION_HEX < 0x03090000
+        PyEval_InitThreads();
+#    endif
         PyThreadState *tstate = PyThreadState_Get();
-        #if PY_VERSION_HEX >= 0x03070000
-            internals_ptr->tstate = PyThread_tss_alloc();
-            if (!internals_ptr->tstate || PyThread_tss_create(internals_ptr->tstate))
-                pybind11_fail("get_internals: could not successfully initialize the TSS key!");
-            PyThread_tss_set(internals_ptr->tstate, tstate);
-        #else
-            internals_ptr->tstate = PyThread_create_key();
-            if (internals_ptr->tstate == -1)
-                pybind11_fail("get_internals: could not successfully initialize the TLS key!");
-            PyThread_set_key_value(internals_ptr->tstate, tstate);
-        #endif
+        if (!PYBIND11_TLS_KEY_CREATE(internals_ptr->tstate)) {
+            pybind11_fail("get_internals: could not successfully initialize the tstate TSS key!");
+        }
+        PYBIND11_TLS_REPLACE_VALUE(internals_ptr->tstate, tstate);
+
+#    if PYBIND11_INTERNALS_VERSION > 4
+        if (!PYBIND11_TLS_KEY_CREATE(internals_ptr->loader_life_support_tls_key)) {
+            pybind11_fail("get_internals: could not successfully initialize the "
+                          "loader_life_support TSS key!");
+        }
+#    endif
         internals_ptr->istate = tstate->interp;
 #endif
         builtins[id] = capsule(internals_pp);
@@ -311,9 +466,53 @@ PYBIND11_NOINLINE inline internals &get_internals() {
     return **internals_pp;
 }
 
-/// Works like `internals.registered_types_cpp`, but for module-local registered types:
-inline type_map<type_info *> &registered_local_types_cpp() {
-    static type_map<type_info *> locals{};
+// the internals struct (above) is shared between all the modules. local_internals are only
+// for a single module. Any changes made to internals may require an update to
+// PYBIND11_INTERNALS_VERSION, breaking backwards compatibility. local_internals is, by design,
+// restricted to a single module. Whether a module has local internals or not should not
+// impact any other modules, because the only things accessing the local internals is the
+// module that contains them.
+struct local_internals {
+    type_map<type_info *> registered_types_cpp;
+    std::forward_list<ExceptionTranslator> registered_exception_translators;
+#if defined(WITH_THREAD) && PYBIND11_INTERNALS_VERSION == 4
+
+    // For ABI compatibility, we can't store the loader_life_support TLS key in
+    // the `internals` struct directly.  Instead, we store it in `shared_data` and
+    // cache a copy in `local_internals`.  If we allocated a separate TLS key for
+    // each instance of `local_internals`, we could end up allocating hundreds of
+    // TLS keys if hundreds of different pybind11 modules are loaded (which is a
+    // plausible number).
+    PYBIND11_TLS_KEY_INIT(loader_life_support_tls_key)
+
+    // Holds the shared TLS key for the loader_life_support stack.
+    struct shared_loader_life_support_data {
+        PYBIND11_TLS_KEY_INIT(loader_life_support_tls_key)
+        shared_loader_life_support_data() {
+            if (!PYBIND11_TLS_KEY_CREATE(loader_life_support_tls_key)) {
+                pybind11_fail("local_internals: could not successfully initialize the "
+                              "loader_life_support TLS key!");
+            }
+        }
+        // We can't help but leak the TLS key, because Python never unloads extension modules.
+    };
+
+    local_internals() {
+        auto &internals = get_internals();
+        // Get or create the `loader_life_support_stack_key`.
+        auto &ptr = internals.shared_data["_life_support"];
+        if (!ptr) {
+            ptr = new shared_loader_life_support_data;
+        }
+        loader_life_support_tls_key
+            = static_cast<shared_loader_life_support_data *>(ptr)->loader_life_support_tls_key;
+    }
+#endif //  defined(WITH_THREAD) && PYBIND11_INTERNALS_VERSION == 4
+};
+
+/// Works like `get_internals`, but for things which are locally registered.
+inline local_internals &get_local_internals() {
+    static local_internals locals;
     return locals;
 }
 
@@ -333,14 +532,14 @@ PYBIND11_NAMESPACE_END(detail)
 /// Returns a named pointer that is shared among all extension modules (using the same
 /// pybind11 version) running in the current interpreter. Names starting with underscores
 /// are reserved for internal usage. Returns `nullptr` if no matching entry was found.
-inline PYBIND11_NOINLINE void *get_shared_data(const std::string &name) {
+PYBIND11_NOINLINE void *get_shared_data(const std::string &name) {
     auto &internals = detail::get_internals();
     auto it = internals.shared_data.find(name);
     return it != internals.shared_data.end() ? it->second : nullptr;
 }
 
 /// Set the shared data that can be later recovered by `get_shared_data()`.
-inline PYBIND11_NOINLINE void *set_shared_data(const std::string &name, void *data) {
+PYBIND11_NOINLINE void *set_shared_data(const std::string &name, void *data) {
     detail::get_internals().shared_data[name] = data;
     return data;
 }
@@ -348,7 +547,7 @@ inline PYBIND11_NOINLINE void *set_shared_data(const std::string &name, void *da
 /// Returns a typed reference to a shared data entry (by using `get_shared_data()`) if
 /// such entry exists. Otherwise, a new object of default-constructible type `T` is
 /// added to the shared data under the given name and a reference to it is returned.
-template<typename T>
+template <typename T>
 T &get_or_create_shared_data(const std::string &name) {
     auto &internals = detail::get_internals();
     auto it = internals.shared_data.find(name);
diff --git a/3rdparty/pybind11/include/pybind11/detail/type_caster_base.h b/3rdparty/pybind11/include/pybind11/detail/type_caster_base.h
new file mode 100644
index 0000000000..21f69c289f
--- /dev/null
+++ b/3rdparty/pybind11/include/pybind11/detail/type_caster_base.h
@@ -0,0 +1,1010 @@
+/*
+    pybind11/detail/type_caster_base.h (originally first part of pybind11/cast.h)
+
+    Copyright (c) 2016 Wenzel Jakob <wenzel.jakob@epfl.ch>
+
+    All rights reserved. Use of this source code is governed by a
+    BSD-style license that can be found in the LICENSE file.
+*/
+
+#pragma once
+
+#include "../pytypes.h"
+#include "common.h"
+#include "descr.h"
+#include "internals.h"
+#include "typeid.h"
+
+#include <cstdint>
+#include <iterator>
+#include <new>
+#include <string>
+#include <type_traits>
+#include <typeindex>
+#include <typeinfo>
+#include <unordered_map>
+#include <utility>
+#include <vector>
+
+PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
+PYBIND11_NAMESPACE_BEGIN(detail)
+
+/// A life support system for temporary objects created by `type_caster::load()`.
+/// Adding a patient will keep it alive up until the enclosing function returns.
+class loader_life_support {
+private:
+    loader_life_support *parent = nullptr;
+    std::unordered_set<PyObject *> keep_alive;
+
+#if defined(WITH_THREAD)
+    // Store stack pointer in thread-local storage.
+    static PYBIND11_TLS_KEY_REF get_stack_tls_key() {
+#    if PYBIND11_INTERNALS_VERSION == 4
+        return get_local_internals().loader_life_support_tls_key;
+#    else
+        return get_internals().loader_life_support_tls_key;
+#    endif
+    }
+    static loader_life_support *get_stack_top() {
+        return static_cast<loader_life_support *>(PYBIND11_TLS_GET_VALUE(get_stack_tls_key()));
+    }
+    static void set_stack_top(loader_life_support *value) {
+        PYBIND11_TLS_REPLACE_VALUE(get_stack_tls_key(), value);
+    }
+#else
+    // Use single global variable for stack.
+    static loader_life_support **get_stack_pp() {
+        static loader_life_support *global_stack = nullptr;
+        return global_stack;
+    }
+    static loader_life_support *get_stack_top() { return *get_stack_pp(); }
+    static void set_stack_top(loader_life_support *value) { *get_stack_pp() = value; }
+#endif
+
+public:
+    /// A new patient frame is created when a function is entered
+    loader_life_support() : parent{get_stack_top()} { set_stack_top(this); }
+
+    /// ... and destroyed after it returns
+    ~loader_life_support() {
+        if (get_stack_top() != this) {
+            pybind11_fail("loader_life_support: internal error");
+        }
+        set_stack_top(parent);
+        for (auto *item : keep_alive) {
+            Py_DECREF(item);
+        }
+    }
+
+    /// This can only be used inside a pybind11-bound function, either by `argument_loader`
+    /// at argument preparation time or by `py::cast()` at execution time.
+    PYBIND11_NOINLINE static void add_patient(handle h) {
+        loader_life_support *frame = get_stack_top();
+        if (!frame) {
+            // NOTE: It would be nice to include the stack frames here, as this indicates
+            // use of pybind11::cast<> outside the normal call framework, finding such
+            // a location is challenging. Developers could consider printing out
+            // stack frame addresses here using something like __builtin_frame_address(0)
+            throw cast_error("When called outside a bound function, py::cast() cannot "
+                             "do Python -> C++ conversions which require the creation "
+                             "of temporary values");
+        }
+
+        if (frame->keep_alive.insert(h.ptr()).second) {
+            Py_INCREF(h.ptr());
+        }
+    }
+};
+
+// Gets the cache entry for the given type, creating it if necessary.  The return value is the pair
+// returned by emplace, i.e. an iterator for the entry and a bool set to `true` if the entry was
+// just created.
+inline std::pair<decltype(internals::registered_types_py)::iterator, bool>
+all_type_info_get_cache(PyTypeObject *type);
+
+// Populates a just-created cache entry.
+PYBIND11_NOINLINE void all_type_info_populate(PyTypeObject *t, std::vector<type_info *> &bases) {
+    std::vector<PyTypeObject *> check;
+    for (handle parent : reinterpret_borrow<tuple>(t->tp_bases)) {
+        check.push_back((PyTypeObject *) parent.ptr());
+    }
+
+    auto const &type_dict = get_internals().registered_types_py;
+    for (size_t i = 0; i < check.size(); i++) {
+        auto *type = check[i];
+        // Ignore Python2 old-style class super type:
+        if (!PyType_Check((PyObject *) type)) {
+            continue;
+        }
+
+        // Check `type` in the current set of registered python types:
+        auto it = type_dict.find(type);
+        if (it != type_dict.end()) {
+            // We found a cache entry for it, so it's either pybind-registered or has pre-computed
+            // pybind bases, but we have to make sure we haven't already seen the type(s) before:
+            // we want to follow Python/virtual C++ rules that there should only be one instance of
+            // a common base.
+            for (auto *tinfo : it->second) {
+                // NB: Could use a second set here, rather than doing a linear search, but since
+                // having a large number of immediate pybind11-registered types seems fairly
+                // unlikely, that probably isn't worthwhile.
+                bool found = false;
+                for (auto *known : bases) {
+                    if (known == tinfo) {
+                        found = true;
+                        break;
+                    }
+                }
+                if (!found) {
+                    bases.push_back(tinfo);
+                }
+            }
+        } else if (type->tp_bases) {
+            // It's some python type, so keep follow its bases classes to look for one or more
+            // registered types
+            if (i + 1 == check.size()) {
+                // When we're at the end, we can pop off the current element to avoid growing
+                // `check` when adding just one base (which is typical--i.e. when there is no
+                // multiple inheritance)
+                check.pop_back();
+                i--;
+            }
+            for (handle parent : reinterpret_borrow<tuple>(type->tp_bases)) {
+                check.push_back((PyTypeObject *) parent.ptr());
+            }
+        }
+    }
+}
+
+/**
+ * Extracts vector of type_info pointers of pybind-registered roots of the given Python type.  Will
+ * be just 1 pybind type for the Python type of a pybind-registered class, or for any Python-side
+ * derived class that uses single inheritance.  Will contain as many types as required for a Python
+ * class that uses multiple inheritance to inherit (directly or indirectly) from multiple
+ * pybind-registered classes.  Will be empty if neither the type nor any base classes are
+ * pybind-registered.
+ *
+ * The value is cached for the lifetime of the Python type.
+ */
+inline const std::vector<detail::type_info *> &all_type_info(PyTypeObject *type) {
+    auto ins = all_type_info_get_cache(type);
+    if (ins.second) {
+        // New cache entry: populate it
+        all_type_info_populate(type, ins.first->second);
+    }
+
+    return ins.first->second;
+}
+
+/**
+ * Gets a single pybind11 type info for a python type.  Returns nullptr if neither the type nor any
+ * ancestors are pybind11-registered.  Throws an exception if there are multiple bases--use
+ * `all_type_info` instead if you want to support multiple bases.
+ */
+PYBIND11_NOINLINE detail::type_info *get_type_info(PyTypeObject *type) {
+    const auto &bases = all_type_info(type);
+    if (bases.empty()) {
+        return nullptr;
+    }
+    if (bases.size() > 1) {
+        pybind11_fail(
+            "pybind11::detail::get_type_info: type has multiple pybind11-registered bases");
+    }
+    return bases.front();
+}
+
+inline detail::type_info *get_local_type_info(const std::type_index &tp) {
+    auto &locals = get_local_internals().registered_types_cpp;
+    auto it = locals.find(tp);
+    if (it != locals.end()) {
+        return it->second;
+    }
+    return nullptr;
+}
+
+inline detail::type_info *get_global_type_info(const std::type_index &tp) {
+    auto &types = get_internals().registered_types_cpp;
+    auto it = types.find(tp);
+    if (it != types.end()) {
+        return it->second;
+    }
+    return nullptr;
+}
+
+/// Return the type info for a given C++ type; on lookup failure can either throw or return
+/// nullptr.
+PYBIND11_NOINLINE detail::type_info *get_type_info(const std::type_index &tp,
+                                                   bool throw_if_missing = false) {
+    if (auto *ltype = get_local_type_info(tp)) {
+        return ltype;
+    }
+    if (auto *gtype = get_global_type_info(tp)) {
+        return gtype;
+    }
+
+    if (throw_if_missing) {
+        std::string tname = tp.name();
+        detail::clean_type_id(tname);
+        pybind11_fail("pybind11::detail::get_type_info: unable to find type info for \""
+                      + std::move(tname) + '"');
+    }
+    return nullptr;
+}
+
+PYBIND11_NOINLINE handle get_type_handle(const std::type_info &tp, bool throw_if_missing) {
+    detail::type_info *type_info = get_type_info(tp, throw_if_missing);
+    return handle(type_info ? ((PyObject *) type_info->type) : nullptr);
+}
+
+// Searches the inheritance graph for a registered Python instance, using all_type_info().
+PYBIND11_NOINLINE handle find_registered_python_instance(void *src,
+                                                         const detail::type_info *tinfo) {
+    auto it_instances = get_internals().registered_instances.equal_range(src);
+    for (auto it_i = it_instances.first; it_i != it_instances.second; ++it_i) {
+        for (auto *instance_type : detail::all_type_info(Py_TYPE(it_i->second))) {
+            if (instance_type && same_type(*instance_type->cpptype, *tinfo->cpptype)) {
+                return handle((PyObject *) it_i->second).inc_ref();
+            }
+        }
+    }
+    return handle();
+}
+
+struct value_and_holder {
+    instance *inst = nullptr;
+    size_t index = 0u;
+    const detail::type_info *type = nullptr;
+    void **vh = nullptr;
+
+    // Main constructor for a found value/holder:
+    value_and_holder(instance *i, const detail::type_info *type, size_t vpos, size_t index)
+        : inst{i}, index{index}, type{type}, vh{inst->simple_layout
+                                                    ? inst->simple_value_holder
+                                                    : &inst->nonsimple.values_and_holders[vpos]} {}
+
+    // Default constructor (used to signal a value-and-holder not found by get_value_and_holder())
+    value_and_holder() = default;
+
+    // Used for past-the-end iterator
+    explicit value_and_holder(size_t index) : index{index} {}
+
+    template <typename V = void>
+    V *&value_ptr() const {
+        return reinterpret_cast<V *&>(vh[0]);
+    }
+    // True if this `value_and_holder` has a non-null value pointer
+    explicit operator bool() const { return value_ptr() != nullptr; }
+
+    template <typename H>
+    H &holder() const {
+        return reinterpret_cast<H &>(vh[1]);
+    }
+    bool holder_constructed() const {
+        return inst->simple_layout
+                   ? inst->simple_holder_constructed
+                   : (inst->nonsimple.status[index] & instance::status_holder_constructed) != 0u;
+    }
+    // NOLINTNEXTLINE(readability-make-member-function-const)
+    void set_holder_constructed(bool v = true) {
+        if (inst->simple_layout) {
+            inst->simple_holder_constructed = v;
+        } else if (v) {
+            inst->nonsimple.status[index] |= instance::status_holder_constructed;
+        } else {
+            inst->nonsimple.status[index] &= (std::uint8_t) ~instance::status_holder_constructed;
+        }
+    }
+    bool instance_registered() const {
+        return inst->simple_layout
+                   ? inst->simple_instance_registered
+                   : ((inst->nonsimple.status[index] & instance::status_instance_registered) != 0);
+    }
+    // NOLINTNEXTLINE(readability-make-member-function-const)
+    void set_instance_registered(bool v = true) {
+        if (inst->simple_layout) {
+            inst->simple_instance_registered = v;
+        } else if (v) {
+            inst->nonsimple.status[index] |= instance::status_instance_registered;
+        } else {
+            inst->nonsimple.status[index] &= (std::uint8_t) ~instance::status_instance_registered;
+        }
+    }
+};
+
+// Container for accessing and iterating over an instance's values/holders
+struct values_and_holders {
+private:
+    instance *inst;
+    using type_vec = std::vector<detail::type_info *>;
+    const type_vec &tinfo;
+
+public:
+    explicit values_and_holders(instance *inst)
+        : inst{inst}, tinfo(all_type_info(Py_TYPE(inst))) {}
+
+    struct iterator {
+    private:
+        instance *inst = nullptr;
+        const type_vec *types = nullptr;
+        value_and_holder curr;
+        friend struct values_and_holders;
+        iterator(instance *inst, const type_vec *tinfo)
+            : inst{inst}, types{tinfo},
+              curr(inst /* instance */,
+                   types->empty() ? nullptr : (*types)[0] /* type info */,
+                   0, /* vpos: (non-simple types only): the first vptr comes first */
+                   0 /* index */) {}
+        // Past-the-end iterator:
+        explicit iterator(size_t end) : curr(end) {}
+
+    public:
+        bool operator==(const iterator &other) const { return curr.index == other.curr.index; }
+        bool operator!=(const iterator &other) const { return curr.index != other.curr.index; }
+        iterator &operator++() {
+            if (!inst->simple_layout) {
+                curr.vh += 1 + (*types)[curr.index]->holder_size_in_ptrs;
+            }
+            ++curr.index;
+            curr.type = curr.index < types->size() ? (*types)[curr.index] : nullptr;
+            return *this;
+        }
+        value_and_holder &operator*() { return curr; }
+        value_and_holder *operator->() { return &curr; }
+    };
+
+    iterator begin() { return iterator(inst, &tinfo); }
+    iterator end() { return iterator(tinfo.size()); }
+
+    iterator find(const type_info *find_type) {
+        auto it = begin(), endit = end();
+        while (it != endit && it->type != find_type) {
+            ++it;
+        }
+        return it;
+    }
+
+    size_t size() { return tinfo.size(); }
+};
+
+/**
+ * Extracts C++ value and holder pointer references from an instance (which may contain multiple
+ * values/holders for python-side multiple inheritance) that match the given type.  Throws an error
+ * if the given type (or ValueType, if omitted) is not a pybind11 base of the given instance.  If
+ * `find_type` is omitted (or explicitly specified as nullptr) the first value/holder are returned,
+ * regardless of type (and the resulting .type will be nullptr).
+ *
+ * The returned object should be short-lived: in particular, it must not outlive the called-upon
+ * instance.
+ */
+PYBIND11_NOINLINE value_and_holder
+instance::get_value_and_holder(const type_info *find_type /*= nullptr default in common.h*/,
+                               bool throw_if_missing /*= true in common.h*/) {
+    // Optimize common case:
+    if (!find_type || Py_TYPE(this) == find_type->type) {
+        return value_and_holder(this, find_type, 0, 0);
+    }
+
+    detail::values_and_holders vhs(this);
+    auto it = vhs.find(find_type);
+    if (it != vhs.end()) {
+        return *it;
+    }
+
+    if (!throw_if_missing) {
+        return value_and_holder();
+    }
+
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+    pybind11_fail("pybind11::detail::instance::get_value_and_holder: `"
+                  + get_fully_qualified_tp_name(find_type->type)
+                  + "' is not a pybind11 base of the given `"
+                  + get_fully_qualified_tp_name(Py_TYPE(this)) + "' instance");
+#else
+    pybind11_fail(
+        "pybind11::detail::instance::get_value_and_holder: "
+        "type is not a pybind11 base of the given instance "
+        "(#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for type details)");
+#endif
+}
+
+PYBIND11_NOINLINE void instance::allocate_layout() {
+    const auto &tinfo = all_type_info(Py_TYPE(this));
+
+    const size_t n_types = tinfo.size();
+
+    if (n_types == 0) {
+        pybind11_fail(
+            "instance allocation failed: new instance has no pybind11-registered base types");
+    }
+
+    simple_layout
+        = n_types == 1 && tinfo.front()->holder_size_in_ptrs <= instance_simple_holder_in_ptrs();
+
+    // Simple path: no python-side multiple inheritance, and a small-enough holder
+    if (simple_layout) {
+        simple_value_holder[0] = nullptr;
+        simple_holder_constructed = false;
+        simple_instance_registered = false;
+    } else { // multiple base types or a too-large holder
+        // Allocate space to hold: [v1*][h1][v2*][h2]...[bb...] where [vN*] is a value pointer,
+        // [hN] is the (uninitialized) holder instance for value N, and [bb...] is a set of bool
+        // values that tracks whether each associated holder has been initialized.  Each [block] is
+        // padded, if necessary, to an integer multiple of sizeof(void *).
+        size_t space = 0;
+        for (auto *t : tinfo) {
+            space += 1;                      // value pointer
+            space += t->holder_size_in_ptrs; // holder instance
+        }
+        size_t flags_at = space;
+        space += size_in_ptrs(n_types); // status bytes (holder_constructed and
+                                        // instance_registered)
+
+        // Allocate space for flags, values, and holders, and initialize it to 0 (flags and values,
+        // in particular, need to be 0).  Use Python's memory allocation
+        // functions: Python is using pymalloc, which is designed to be
+        // efficient for small allocations like the one we're doing here;
+        // for larger allocations they are just wrappers around malloc.
+        // TODO: is this still true for pure Python 3.6?
+        nonsimple.values_and_holders = (void **) PyMem_Calloc(space, sizeof(void *));
+        if (!nonsimple.values_and_holders) {
+            throw std::bad_alloc();
+        }
+        nonsimple.status
+            = reinterpret_cast<std::uint8_t *>(&nonsimple.values_and_holders[flags_at]);
+    }
+    owned = true;
+}
+
+// NOLINTNEXTLINE(readability-make-member-function-const)
+PYBIND11_NOINLINE void instance::deallocate_layout() {
+    if (!simple_layout) {
+        PyMem_Free(nonsimple.values_and_holders);
+    }
+}
+
+PYBIND11_NOINLINE bool isinstance_generic(handle obj, const std::type_info &tp) {
+    handle type = detail::get_type_handle(tp, false);
+    if (!type) {
+        return false;
+    }
+    return isinstance(obj, type);
+}
+
+PYBIND11_NOINLINE handle get_object_handle(const void *ptr, const detail::type_info *type) {
+    auto &instances = get_internals().registered_instances;
+    auto range = instances.equal_range(ptr);
+    for (auto it = range.first; it != range.second; ++it) {
+        for (const auto &vh : values_and_holders(it->second)) {
+            if (vh.type == type) {
+                return handle((PyObject *) it->second);
+            }
+        }
+    }
+    return handle();
+}
+
+inline PyThreadState *get_thread_state_unchecked() {
+#if defined(PYPY_VERSION)
+    return PyThreadState_GET();
+#else
+    return _PyThreadState_UncheckedGet();
+#endif
+}
+
+// Forward declarations
+void keep_alive_impl(handle nurse, handle patient);
+inline PyObject *make_new_instance(PyTypeObject *type);
+
+class type_caster_generic {
+public:
+    PYBIND11_NOINLINE explicit type_caster_generic(const std::type_info &type_info)
+        : typeinfo(get_type_info(type_info)), cpptype(&type_info) {}
+
+    explicit type_caster_generic(const type_info *typeinfo)
+        : typeinfo(typeinfo), cpptype(typeinfo ? typeinfo->cpptype : nullptr) {}
+
+    bool load(handle src, bool convert) { return load_impl<type_caster_generic>(src, convert); }
+
+    PYBIND11_NOINLINE static handle cast(const void *_src,
+                                         return_value_policy policy,
+                                         handle parent,
+                                         const detail::type_info *tinfo,
+                                         void *(*copy_constructor)(const void *),
+                                         void *(*move_constructor)(const void *),
+                                         const void *existing_holder = nullptr) {
+        if (!tinfo) { // no type info: error will be set already
+            return handle();
+        }
+
+        void *src = const_cast<void *>(_src);
+        if (src == nullptr) {
+            return none().release();
+        }
+
+        if (handle registered_inst = find_registered_python_instance(src, tinfo)) {
+            return registered_inst;
+        }
+
+        auto inst = reinterpret_steal<object>(make_new_instance(tinfo->type));
+        auto *wrapper = reinterpret_cast<instance *>(inst.ptr());
+        wrapper->owned = false;
+        void *&valueptr = values_and_holders(wrapper).begin()->value_ptr();
+
+        switch (policy) {
+            case return_value_policy::automatic:
+            case return_value_policy::take_ownership:
+                valueptr = src;
+                wrapper->owned = true;
+                break;
+
+            case return_value_policy::automatic_reference:
+            case return_value_policy::reference:
+                valueptr = src;
+                wrapper->owned = false;
+                break;
+
+            case return_value_policy::copy:
+                if (copy_constructor) {
+                    valueptr = copy_constructor(src);
+                } else {
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+                    std::string type_name(tinfo->cpptype->name());
+                    detail::clean_type_id(type_name);
+                    throw cast_error("return_value_policy = copy, but type " + type_name
+                                     + " is non-copyable!");
+#else
+                    throw cast_error("return_value_policy = copy, but type is "
+                                     "non-copyable! (#define PYBIND11_DETAILED_ERROR_MESSAGES or "
+                                     "compile in debug mode for details)");
+#endif
+                }
+                wrapper->owned = true;
+                break;
+
+            case return_value_policy::move:
+                if (move_constructor) {
+                    valueptr = move_constructor(src);
+                } else if (copy_constructor) {
+                    valueptr = copy_constructor(src);
+                } else {
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+                    std::string type_name(tinfo->cpptype->name());
+                    detail::clean_type_id(type_name);
+                    throw cast_error("return_value_policy = move, but type " + type_name
+                                     + " is neither movable nor copyable!");
+#else
+                    throw cast_error("return_value_policy = move, but type is neither "
+                                     "movable nor copyable! "
+                                     "(#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in "
+                                     "debug mode for details)");
+#endif
+                }
+                wrapper->owned = true;
+                break;
+
+            case return_value_policy::reference_internal:
+                valueptr = src;
+                wrapper->owned = false;
+                keep_alive_impl(inst, parent);
+                break;
+
+            default:
+                throw cast_error("unhandled return_value_policy: should not happen!");
+        }
+
+        tinfo->init_instance(wrapper, existing_holder);
+
+        return inst.release();
+    }
+
+    // Base methods for generic caster; there are overridden in copyable_holder_caster
+    void load_value(value_and_holder &&v_h) {
+        auto *&vptr = v_h.value_ptr();
+        // Lazy allocation for unallocated values:
+        if (vptr == nullptr) {
+            const auto *type = v_h.type ? v_h.type : typeinfo;
+            if (type->operator_new) {
+                vptr = type->operator_new(type->type_size);
+            } else {
+#if defined(__cpp_aligned_new) && (!defined(_MSC_VER) || _MSC_VER >= 1912)
+                if (type->type_align > __STDCPP_DEFAULT_NEW_ALIGNMENT__) {
+                    vptr = ::operator new(type->type_size, std::align_val_t(type->type_align));
+                } else {
+                    vptr = ::operator new(type->type_size);
+                }
+#else
+                vptr = ::operator new(type->type_size);
+#endif
+            }
+        }
+        value = vptr;
+    }
+    bool try_implicit_casts(handle src, bool convert) {
+        for (const auto &cast : typeinfo->implicit_casts) {
+            type_caster_generic sub_caster(*cast.first);
+            if (sub_caster.load(src, convert)) {
+                value = cast.second(sub_caster.value);
+                return true;
+            }
+        }
+        return false;
+    }
+    bool try_direct_conversions(handle src) {
+        for (auto &converter : *typeinfo->direct_conversions) {
+            if (converter(src.ptr(), value)) {
+                return true;
+            }
+        }
+        return false;
+    }
+    void check_holder_compat() {}
+
+    PYBIND11_NOINLINE static void *local_load(PyObject *src, const type_info *ti) {
+        auto caster = type_caster_generic(ti);
+        if (caster.load(src, false)) {
+            return caster.value;
+        }
+        return nullptr;
+    }
+
+    /// Try to load with foreign typeinfo, if available. Used when there is no
+    /// native typeinfo, or when the native one wasn't able to produce a value.
+    PYBIND11_NOINLINE bool try_load_foreign_module_local(handle src) {
+        constexpr auto *local_key = PYBIND11_MODULE_LOCAL_ID;
+        const auto pytype = type::handle_of(src);
+        if (!hasattr(pytype, local_key)) {
+            return false;
+        }
+
+        type_info *foreign_typeinfo = reinterpret_borrow<capsule>(getattr(pytype, local_key));
+        // Only consider this foreign loader if actually foreign and is a loader of the correct cpp
+        // type
+        if (foreign_typeinfo->module_local_load == &local_load
+            || (cpptype && !same_type(*cpptype, *foreign_typeinfo->cpptype))) {
+            return false;
+        }
+
+        if (auto *result = foreign_typeinfo->module_local_load(src.ptr(), foreign_typeinfo)) {
+            value = result;
+            return true;
+        }
+        return false;
+    }
+
+    // Implementation of `load`; this takes the type of `this` so that it can dispatch the relevant
+    // bits of code between here and copyable_holder_caster where the two classes need different
+    // logic (without having to resort to virtual inheritance).
+    template <typename ThisT>
+    PYBIND11_NOINLINE bool load_impl(handle src, bool convert) {
+        if (!src) {
+            return false;
+        }
+        if (!typeinfo) {
+            return try_load_foreign_module_local(src);
+        }
+
+        auto &this_ = static_cast<ThisT &>(*this);
+        this_.check_holder_compat();
+
+        PyTypeObject *srctype = Py_TYPE(src.ptr());
+
+        // Case 1: If src is an exact type match for the target type then we can reinterpret_cast
+        // the instance's value pointer to the target type:
+        if (srctype == typeinfo->type) {
+            this_.load_value(reinterpret_cast<instance *>(src.ptr())->get_value_and_holder());
+            return true;
+        }
+        // Case 2: We have a derived class
+        if (PyType_IsSubtype(srctype, typeinfo->type)) {
+            const auto &bases = all_type_info(srctype);
+            bool no_cpp_mi = typeinfo->simple_type;
+
+            // Case 2a: the python type is a Python-inherited derived class that inherits from just
+            // one simple (no MI) pybind11 class, or is an exact match, so the C++ instance is of
+            // the right type and we can use reinterpret_cast.
+            // (This is essentially the same as case 2b, but because not using multiple inheritance
+            // is extremely common, we handle it specially to avoid the loop iterator and type
+            // pointer lookup overhead)
+            if (bases.size() == 1 && (no_cpp_mi || bases.front()->type == typeinfo->type)) {
+                this_.load_value(reinterpret_cast<instance *>(src.ptr())->get_value_and_holder());
+                return true;
+            }
+            // Case 2b: the python type inherits from multiple C++ bases.  Check the bases to see
+            // if we can find an exact match (or, for a simple C++ type, an inherited match); if
+            // so, we can safely reinterpret_cast to the relevant pointer.
+            if (bases.size() > 1) {
+                for (auto *base : bases) {
+                    if (no_cpp_mi ? PyType_IsSubtype(base->type, typeinfo->type)
+                                  : base->type == typeinfo->type) {
+                        this_.load_value(
+                            reinterpret_cast<instance *>(src.ptr())->get_value_and_holder(base));
+                        return true;
+                    }
+                }
+            }
+
+            // Case 2c: C++ multiple inheritance is involved and we couldn't find an exact type
+            // match in the registered bases, above, so try implicit casting (needed for proper C++
+            // casting when MI is involved).
+            if (this_.try_implicit_casts(src, convert)) {
+                return true;
+            }
+        }
+
+        // Perform an implicit conversion
+        if (convert) {
+            for (const auto &converter : typeinfo->implicit_conversions) {
+                auto temp = reinterpret_steal<object>(converter(src.ptr(), typeinfo->type));
+                if (load_impl<ThisT>(temp, false)) {
+                    loader_life_support::add_patient(temp);
+                    return true;
+                }
+            }
+            if (this_.try_direct_conversions(src)) {
+                return true;
+            }
+        }
+
+        // Failed to match local typeinfo. Try again with global.
+        if (typeinfo->module_local) {
+            if (auto *gtype = get_global_type_info(*typeinfo->cpptype)) {
+                typeinfo = gtype;
+                return load(src, false);
+            }
+        }
+
+        // Global typeinfo has precedence over foreign module_local
+        if (try_load_foreign_module_local(src)) {
+            return true;
+        }
+
+        // Custom converters didn't take None, now we convert None to nullptr.
+        if (src.is_none()) {
+            // Defer accepting None to other overloads (if we aren't in convert mode):
+            if (!convert) {
+                return false;
+            }
+            value = nullptr;
+            return true;
+        }
+
+        return false;
+    }
+
+    // Called to do type lookup and wrap the pointer and type in a pair when a dynamic_cast
+    // isn't needed or can't be used.  If the type is unknown, sets the error and returns a pair
+    // with .second = nullptr.  (p.first = nullptr is not an error: it becomes None).
+    PYBIND11_NOINLINE static std::pair<const void *, const type_info *>
+    src_and_type(const void *src,
+                 const std::type_info &cast_type,
+                 const std::type_info *rtti_type = nullptr) {
+        if (auto *tpi = get_type_info(cast_type)) {
+            return {src, const_cast<const type_info *>(tpi)};
+        }
+
+        // Not found, set error:
+        std::string tname = rtti_type ? rtti_type->name() : cast_type.name();
+        detail::clean_type_id(tname);
+        std::string msg = "Unregistered type : " + tname;
+        PyErr_SetString(PyExc_TypeError, msg.c_str());
+        return {nullptr, nullptr};
+    }
+
+    const type_info *typeinfo = nullptr;
+    const std::type_info *cpptype = nullptr;
+    void *value = nullptr;
+};
+
+/**
+ * Determine suitable casting operator for pointer-or-lvalue-casting type casters.  The type caster
+ * needs to provide `operator T*()` and `operator T&()` operators.
+ *
+ * If the type supports moving the value away via an `operator T&&() &&` method, it should use
+ * `movable_cast_op_type` instead.
+ */
+template <typename T>
+using cast_op_type = conditional_t<std::is_pointer<remove_reference_t<T>>::value,
+                                   typename std::add_pointer<intrinsic_t<T>>::type,
+                                   typename std::add_lvalue_reference<intrinsic_t<T>>::type>;
+
+/**
+ * Determine suitable casting operator for a type caster with a movable value.  Such a type caster
+ * needs to provide `operator T*()`, `operator T&()`, and `operator T&&() &&`.  The latter will be
+ * called in appropriate contexts where the value can be moved rather than copied.
+ *
+ * These operator are automatically provided when using the PYBIND11_TYPE_CASTER macro.
+ */
+template <typename T>
+using movable_cast_op_type
+    = conditional_t<std::is_pointer<typename std::remove_reference<T>::type>::value,
+                    typename std::add_pointer<intrinsic_t<T>>::type,
+                    conditional_t<std::is_rvalue_reference<T>::value,
+                                  typename std::add_rvalue_reference<intrinsic_t<T>>::type,
+                                  typename std::add_lvalue_reference<intrinsic_t<T>>::type>>;
+
+// std::is_copy_constructible isn't quite enough: it lets std::vector<T> (and similar) through when
+// T is non-copyable, but code containing such a copy constructor fails to actually compile.
+template <typename T, typename SFINAE = void>
+struct is_copy_constructible : std::is_copy_constructible<T> {};
+
+// Specialization for types that appear to be copy constructible but also look like stl containers
+// (we specifically check for: has `value_type` and `reference` with `reference = value_type&`): if
+// so, copy constructability depends on whether the value_type is copy constructible.
+template <typename Container>
+struct is_copy_constructible<
+    Container,
+    enable_if_t<
+        all_of<std::is_copy_constructible<Container>,
+               std::is_same<typename Container::value_type &, typename Container::reference>,
+               // Avoid infinite recursion
+               negation<std::is_same<Container, typename Container::value_type>>>::value>>
+    : is_copy_constructible<typename Container::value_type> {};
+
+// Likewise for std::pair
+// (after C++17 it is mandatory that the copy constructor not exist when the two types aren't
+// themselves copy constructible, but this can not be relied upon when T1 or T2 are themselves
+// containers).
+template <typename T1, typename T2>
+struct is_copy_constructible<std::pair<T1, T2>>
+    : all_of<is_copy_constructible<T1>, is_copy_constructible<T2>> {};
+
+// The same problems arise with std::is_copy_assignable, so we use the same workaround.
+template <typename T, typename SFINAE = void>
+struct is_copy_assignable : std::is_copy_assignable<T> {};
+template <typename Container>
+struct is_copy_assignable<Container,
+                          enable_if_t<all_of<std::is_copy_assignable<Container>,
+                                             std::is_same<typename Container::value_type &,
+                                                          typename Container::reference>>::value>>
+    : is_copy_assignable<typename Container::value_type> {};
+template <typename T1, typename T2>
+struct is_copy_assignable<std::pair<T1, T2>>
+    : all_of<is_copy_assignable<T1>, is_copy_assignable<T2>> {};
+
+PYBIND11_NAMESPACE_END(detail)
+
+// polymorphic_type_hook<itype>::get(src, tinfo) determines whether the object pointed
+// to by `src` actually is an instance of some class derived from `itype`.
+// If so, it sets `tinfo` to point to the std::type_info representing that derived
+// type, and returns a pointer to the start of the most-derived object of that type
+// (in which `src` is a subobject; this will be the same address as `src` in most
+// single inheritance cases). If not, or if `src` is nullptr, it simply returns `src`
+// and leaves `tinfo` at its default value of nullptr.
+//
+// The default polymorphic_type_hook just returns src. A specialization for polymorphic
+// types determines the runtime type of the passed object and adjusts the this-pointer
+// appropriately via dynamic_cast<void*>. This is what enables a C++ Animal* to appear
+// to Python as a Dog (if Dog inherits from Animal, Animal is polymorphic, Dog is
+// registered with pybind11, and this Animal is in fact a Dog).
+//
+// You may specialize polymorphic_type_hook yourself for types that want to appear
+// polymorphic to Python but do not use C++ RTTI. (This is a not uncommon pattern
+// in performance-sensitive applications, used most notably in LLVM.)
+//
+// polymorphic_type_hook_base allows users to specialize polymorphic_type_hook with
+// std::enable_if. User provided specializations will always have higher priority than
+// the default implementation and specialization provided in polymorphic_type_hook_base.
+template <typename itype, typename SFINAE = void>
+struct polymorphic_type_hook_base {
+    static const void *get(const itype *src, const std::type_info *&) { return src; }
+};
+template <typename itype>
+struct polymorphic_type_hook_base<itype, detail::enable_if_t<std::is_polymorphic<itype>::value>> {
+    static const void *get(const itype *src, const std::type_info *&type) {
+        type = src ? &typeid(*src) : nullptr;
+        return dynamic_cast<const void *>(src);
+    }
+};
+template <typename itype, typename SFINAE = void>
+struct polymorphic_type_hook : public polymorphic_type_hook_base<itype> {};
+
+PYBIND11_NAMESPACE_BEGIN(detail)
+
+/// Generic type caster for objects stored on the heap
+template <typename type>
+class type_caster_base : public type_caster_generic {
+    using itype = intrinsic_t<type>;
+
+public:
+    static constexpr auto name = const_name<type>();
+
+    type_caster_base() : type_caster_base(typeid(type)) {}
+    explicit type_caster_base(const std::type_info &info) : type_caster_generic(info) {}
+
+    static handle cast(const itype &src, return_value_policy policy, handle parent) {
+        if (policy == return_value_policy::automatic
+            || policy == return_value_policy::automatic_reference) {
+            policy = return_value_policy::copy;
+        }
+        return cast(&src, policy, parent);
+    }
+
+    static handle cast(itype &&src, return_value_policy, handle parent) {
+        return cast(&src, return_value_policy::move, parent);
+    }
+
+    // Returns a (pointer, type_info) pair taking care of necessary type lookup for a
+    // polymorphic type (using RTTI by default, but can be overridden by specializing
+    // polymorphic_type_hook). If the instance isn't derived, returns the base version.
+    static std::pair<const void *, const type_info *> src_and_type(const itype *src) {
+        const auto &cast_type = typeid(itype);
+        const std::type_info *instance_type = nullptr;
+        const void *vsrc = polymorphic_type_hook<itype>::get(src, instance_type);
+        if (instance_type && !same_type(cast_type, *instance_type)) {
+            // This is a base pointer to a derived type. If the derived type is registered
+            // with pybind11, we want to make the full derived object available.
+            // In the typical case where itype is polymorphic, we get the correct
+            // derived pointer (which may be != base pointer) by a dynamic_cast to
+            // most derived type. If itype is not polymorphic, we won't get here
+            // except via a user-provided specialization of polymorphic_type_hook,
+            // and the user has promised that no this-pointer adjustment is
+            // required in that case, so it's OK to use static_cast.
+            if (const auto *tpi = get_type_info(*instance_type)) {
+                return {vsrc, tpi};
+            }
+        }
+        // Otherwise we have either a nullptr, an `itype` pointer, or an unknown derived pointer,
+        // so don't do a cast
+        return type_caster_generic::src_and_type(src, cast_type, instance_type);
+    }
+
+    static handle cast(const itype *src, return_value_policy policy, handle parent) {
+        auto st = src_and_type(src);
+        return type_caster_generic::cast(st.first,
+                                         policy,
+                                         parent,
+                                         st.second,
+                                         make_copy_constructor(src),
+                                         make_move_constructor(src));
+    }
+
+    static handle cast_holder(const itype *src, const void *holder) {
+        auto st = src_and_type(src);
+        return type_caster_generic::cast(st.first,
+                                         return_value_policy::take_ownership,
+                                         {},
+                                         st.second,
+                                         nullptr,
+                                         nullptr,
+                                         holder);
+    }
+
+    template <typename T>
+    using cast_op_type = detail::cast_op_type<T>;
+
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator itype *() { return (type *) value; }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator itype &() {
+        if (!value) {
+            throw reference_cast_error();
+        }
+        return *((itype *) value);
+    }
+
+protected:
+    using Constructor = void *(*) (const void *);
+
+    /* Only enabled when the types are {copy,move}-constructible *and* when the type
+       does not have a private operator new implementation. A comma operator is used in the
+       decltype argument to apply SFINAE to the public copy/move constructors.*/
+    template <typename T, typename = enable_if_t<is_copy_constructible<T>::value>>
+    static auto make_copy_constructor(const T *)
+        -> decltype(new T(std::declval<const T>()), Constructor{}) {
+        return [](const void *arg) -> void * { return new T(*reinterpret_cast<const T *>(arg)); };
+    }
+
+    template <typename T, typename = enable_if_t<std::is_move_constructible<T>::value>>
+    static auto make_move_constructor(const T *)
+        -> decltype(new T(std::declval<T &&>()), Constructor{}) {
+        return [](const void *arg) -> void * {
+            return new T(std::move(*const_cast<T *>(reinterpret_cast<const T *>(arg))));
+        };
+    }
+
+    static Constructor make_copy_constructor(...) { return nullptr; }
+    static Constructor make_move_constructor(...) { return nullptr; }
+};
+
+PYBIND11_NAMESPACE_END(detail)
+PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/detail/typeid.h b/3rdparty/pybind11/include/pybind11/detail/typeid.h
index 148889ffef..a67b52135b 100644
--- a/3rdparty/pybind11/include/pybind11/detail/typeid.h
+++ b/3rdparty/pybind11/include/pybind11/detail/typeid.h
@@ -13,29 +13,33 @@
 #include <cstdlib>
 
 #if defined(__GNUG__)
-#include <cxxabi.h>
+#    include <cxxabi.h>
 #endif
 
 #include "common.h"
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
+
 /// Erase all occurrences of a substring
 inline void erase_all(std::string &string, const std::string &search) {
     for (size_t pos = 0;;) {
         pos = string.find(search, pos);
-        if (pos == std::string::npos) break;
+        if (pos == std::string::npos) {
+            break;
+        }
         string.erase(pos, search.length());
     }
 }
 
-PYBIND11_NOINLINE inline void clean_type_id(std::string &name) {
+PYBIND11_NOINLINE void clean_type_id(std::string &name) {
 #if defined(__GNUG__)
     int status = 0;
-    std::unique_ptr<char, void (*)(void *)> res {
-        abi::__cxa_demangle(name.c_str(), nullptr, nullptr, &status), std::free };
-    if (status == 0)
+    std::unique_ptr<char, void (*)(void *)> res{
+        abi::__cxa_demangle(name.c_str(), nullptr, nullptr, &status), std::free};
+    if (status == 0) {
         name = res.get();
+    }
 #else
     detail::erase_all(name, "class ");
     detail::erase_all(name, "struct ");
@@ -43,13 +47,19 @@ PYBIND11_NOINLINE inline void clean_type_id(std::string &name) {
 #endif
     detail::erase_all(name, "pybind11::");
 }
-PYBIND11_NAMESPACE_END(detail)
 
-/// Return a string representation of a C++ type
-template <typename T> static std::string type_id() {
-    std::string name(typeid(T).name());
+inline std::string clean_type_id(const char *typeid_name) {
+    std::string name(typeid_name);
     detail::clean_type_id(name);
     return name;
 }
 
+PYBIND11_NAMESPACE_END(detail)
+
+/// Return a string representation of a C++ type
+template <typename T>
+static std::string type_id() {
+    return detail::clean_type_id(typeid(T).name());
+}
+
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/eigen.h b/3rdparty/pybind11/include/pybind11/eigen.h
index e8c6f63391..8316252294 100644
--- a/3rdparty/pybind11/include/pybind11/eigen.h
+++ b/3rdparty/pybind11/include/pybind11/eigen.h
@@ -9,218 +9,266 @@
 
 #pragma once
 
-#include "numpy.h"
+/* HINT: To suppress warnings originating from the Eigen headers, use -isystem.
+   See also:
+       https://stackoverflow.com/questions/2579576/i-dir-vs-isystem-dir
+       https://stackoverflow.com/questions/1741816/isystem-for-ms-visual-studio-c-compiler
+*/
 
-#if defined(__INTEL_COMPILER)
-#  pragma warning(disable: 1682) // implicit conversion of a 64-bit integral type to a smaller integral type (potential portability problem)
-#elif defined(__GNUG__) || defined(__clang__)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wconversion"
-#  pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-#  ifdef __clang__
-//   Eigen generates a bunch of implicit-copy-constructor-is-deprecated warnings with -Wdeprecated
-//   under Clang, so disable that warning here:
-#    pragma GCC diagnostic ignored "-Wdeprecated"
-#  endif
-#  if __GNUC__ >= 7
-#    pragma GCC diagnostic ignored "-Wint-in-bool-context"
-#  endif
-#endif
+#include "numpy.h"
 
+// The C4127 suppression was introduced for Eigen 3.4.0. In theory we could
+// make it version specific, or even remove it later, but considering that
+// 1. C4127 is generally far more distracting than useful for modern template code, and
+// 2. we definitely want to ignore any MSVC warnings originating from Eigen code,
+//    it is probably best to keep this around indefinitely.
 #if defined(_MSC_VER)
-#  pragma warning(push)
-#  pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#  pragma warning(disable: 4996) // warning C4996: std::unary_negate is deprecated in C++17
+#    pragma warning(push)
+#    pragma warning(disable : 4127) // C4127: conditional expression is constant
+#    pragma warning(disable : 5054) // https://github.com/pybind/pybind11/pull/3741
+//       C5054: operator '&': deprecated between enumerations of different types
+#elif defined(__MINGW32__)
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wmaybe-uninitialized"
 #endif
 
 #include <Eigen/Core>
 #include <Eigen/SparseCore>
 
+#if defined(_MSC_VER)
+#    pragma warning(pop)
+#elif defined(__MINGW32__)
+#    pragma GCC diagnostic pop
+#endif
+
 // Eigen prior to 3.2.7 doesn't have proper move constructors--but worse, some classes get implicit
 // move constructors that break things.  We could detect this an explicitly copy, but an extra copy
 // of matrices seems highly undesirable.
-static_assert(EIGEN_VERSION_AT_LEAST(3,2,7), "Eigen support in pybind11 requires Eigen >= 3.2.7");
+static_assert(EIGEN_VERSION_AT_LEAST(3, 2, 7),
+              "Eigen support in pybind11 requires Eigen >= 3.2.7");
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
 // Provide a convenience alias for easier pass-by-ref usage with fully dynamic strides:
 using EigenDStride = Eigen::Stride<Eigen::Dynamic, Eigen::Dynamic>;
-template <typename MatrixType> using EigenDRef = Eigen::Ref<MatrixType, 0, EigenDStride>;
-template <typename MatrixType> using EigenDMap = Eigen::Map<MatrixType, 0, EigenDStride>;
+template <typename MatrixType>
+using EigenDRef = Eigen::Ref<MatrixType, 0, EigenDStride>;
+template <typename MatrixType>
+using EigenDMap = Eigen::Map<MatrixType, 0, EigenDStride>;
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-#if EIGEN_VERSION_AT_LEAST(3,3,0)
+#if EIGEN_VERSION_AT_LEAST(3, 3, 0)
 using EigenIndex = Eigen::Index;
+template <typename Scalar, int Flags, typename StorageIndex>
+using EigenMapSparseMatrix = Eigen::Map<Eigen::SparseMatrix<Scalar, Flags, StorageIndex>>;
 #else
 using EigenIndex = EIGEN_DEFAULT_DENSE_INDEX_TYPE;
+template <typename Scalar, int Flags, typename StorageIndex>
+using EigenMapSparseMatrix = Eigen::MappedSparseMatrix<Scalar, Flags, StorageIndex>;
 #endif
 
 // Matches Eigen::Map, Eigen::Ref, blocks, etc:
-template <typename T> using is_eigen_dense_map = all_of<is_template_base_of<Eigen::DenseBase, T>, std::is_base_of<Eigen::MapBase<T, Eigen::ReadOnlyAccessors>, T>>;
-template <typename T> using is_eigen_mutable_map = std::is_base_of<Eigen::MapBase<T, Eigen::WriteAccessors>, T>;
-template <typename T> using is_eigen_dense_plain = all_of<negation<is_eigen_dense_map<T>>, is_template_base_of<Eigen::PlainObjectBase, T>>;
-template <typename T> using is_eigen_sparse = is_template_base_of<Eigen::SparseMatrixBase, T>;
+template <typename T>
+using is_eigen_dense_map = all_of<is_template_base_of<Eigen::DenseBase, T>,
+                                  std::is_base_of<Eigen::MapBase<T, Eigen::ReadOnlyAccessors>, T>>;
+template <typename T>
+using is_eigen_mutable_map = std::is_base_of<Eigen::MapBase<T, Eigen::WriteAccessors>, T>;
+template <typename T>
+using is_eigen_dense_plain
+    = all_of<negation<is_eigen_dense_map<T>>, is_template_base_of<Eigen::PlainObjectBase, T>>;
+template <typename T>
+using is_eigen_sparse = is_template_base_of<Eigen::SparseMatrixBase, T>;
 // Test for objects inheriting from EigenBase<Derived> that aren't captured by the above.  This
 // basically covers anything that can be assigned to a dense matrix but that don't have a typical
 // matrix data layout that can be copied from their .data().  For example, DiagonalMatrix and
 // SelfAdjointView fall into this category.
-template <typename T> using is_eigen_other = all_of<
-    is_template_base_of<Eigen::EigenBase, T>,
-    negation<any_of<is_eigen_dense_map<T>, is_eigen_dense_plain<T>, is_eigen_sparse<T>>>
->;
+template <typename T>
+using is_eigen_other
+    = all_of<is_template_base_of<Eigen::EigenBase, T>,
+             negation<any_of<is_eigen_dense_map<T>, is_eigen_dense_plain<T>, is_eigen_sparse<T>>>>;
 
 // Captures numpy/eigen conformability status (returned by EigenProps::conformable()):
-template <bool EigenRowMajor> struct EigenConformable {
+template <bool EigenRowMajor>
+struct EigenConformable {
     bool conformable = false;
     EigenIndex rows = 0, cols = 0;
-    EigenDStride stride{0, 0};      // Only valid if negativestrides is false!
-    bool negativestrides = false;   // If true, do not use stride!
+    EigenDStride stride{0, 0};    // Only valid if negativestrides is false!
+    bool negativestrides = false; // If true, do not use stride!
 
+    // NOLINTNEXTLINE(google-explicit-constructor)
     EigenConformable(bool fits = false) : conformable{fits} {}
     // Matrix type:
-    EigenConformable(EigenIndex r, EigenIndex c,
-            EigenIndex rstride, EigenIndex cstride) :
-        conformable{true}, rows{r}, cols{c} {
-        // TODO: when Eigen bug #747 is fixed, remove the tests for non-negativity. http://eigen.tuxfamily.org/bz/show_bug.cgi?id=747
-        if (rstride < 0 || cstride < 0) {
-            negativestrides = true;
-        } else {
-            stride = {EigenRowMajor ? rstride : cstride /* outer stride */,
-                      EigenRowMajor ? cstride : rstride /* inner stride */ };
-        }
-    }
+    EigenConformable(EigenIndex r, EigenIndex c, EigenIndex rstride, EigenIndex cstride)
+        : conformable{true}, rows{r}, cols{c},
+          // TODO: when Eigen bug #747 is fixed, remove the tests for non-negativity.
+          // http://eigen.tuxfamily.org/bz/show_bug.cgi?id=747
+          stride{EigenRowMajor ? (rstride > 0 ? rstride : 0)
+                               : (cstride > 0 ? cstride : 0) /* outer stride */,
+                 EigenRowMajor ? (cstride > 0 ? cstride : 0)
+                               : (rstride > 0 ? rstride : 0) /* inner stride */},
+          negativestrides{rstride < 0 || cstride < 0} {}
     // Vector type:
     EigenConformable(EigenIndex r, EigenIndex c, EigenIndex stride)
-        : EigenConformable(r, c, r == 1 ? c*stride : stride, c == 1 ? r : r*stride) {}
+        : EigenConformable(r, c, r == 1 ? c * stride : stride, c == 1 ? r : r * stride) {}
 
-    template <typename props> bool stride_compatible() const {
+    template <typename props>
+    bool stride_compatible() const {
         // To have compatible strides, we need (on both dimensions) one of fully dynamic strides,
-        // matching strides, or a dimension size of 1 (in which case the stride value is irrelevant)
-        return
-            !negativestrides &&
-            (props::inner_stride == Eigen::Dynamic || props::inner_stride == stride.inner() ||
-                (EigenRowMajor ? cols : rows) == 1) &&
-            (props::outer_stride == Eigen::Dynamic || props::outer_stride == stride.outer() ||
-                (EigenRowMajor ? rows : cols) == 1);
+        // matching strides, or a dimension size of 1 (in which case the stride value is
+        // irrelevant). Alternatively, if any dimension size is 0, the strides are not relevant
+        // (and numpy ≥ 1.23 sets the strides to 0 in that case, so we need to check explicitly).
+        if (negativestrides) {
+            return false;
+        }
+        if (rows == 0 || cols == 0) {
+            return true;
+        }
+        return (props::inner_stride == Eigen::Dynamic || props::inner_stride == stride.inner()
+                || (EigenRowMajor ? cols : rows) == 1)
+               && (props::outer_stride == Eigen::Dynamic || props::outer_stride == stride.outer()
+                   || (EigenRowMajor ? rows : cols) == 1);
     }
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator bool() const { return conformable; }
 };
 
-template <typename Type> struct eigen_extract_stride { using type = Type; };
+template <typename Type>
+struct eigen_extract_stride {
+    using type = Type;
+};
 template <typename PlainObjectType, int MapOptions, typename StrideType>
-struct eigen_extract_stride<Eigen::Map<PlainObjectType, MapOptions, StrideType>> { using type = StrideType; };
+struct eigen_extract_stride<Eigen::Map<PlainObjectType, MapOptions, StrideType>> {
+    using type = StrideType;
+};
 template <typename PlainObjectType, int Options, typename StrideType>
-struct eigen_extract_stride<Eigen::Ref<PlainObjectType, Options, StrideType>> { using type = StrideType; };
+struct eigen_extract_stride<Eigen::Ref<PlainObjectType, Options, StrideType>> {
+    using type = StrideType;
+};
 
 // Helper struct for extracting information from an Eigen type
-template <typename Type_> struct EigenProps {
+template <typename Type_>
+struct EigenProps {
     using Type = Type_;
     using Scalar = typename Type::Scalar;
     using StrideType = typename eigen_extract_stride<Type>::type;
-    static constexpr EigenIndex
-        rows = Type::RowsAtCompileTime,
-        cols = Type::ColsAtCompileTime,
-        size = Type::SizeAtCompileTime;
-    static constexpr bool
-        row_major = Type::IsRowMajor,
-        vector = Type::IsVectorAtCompileTime, // At least one dimension has fixed size 1
-        fixed_rows = rows != Eigen::Dynamic,
-        fixed_cols = cols != Eigen::Dynamic,
-        fixed = size != Eigen::Dynamic, // Fully-fixed size
-        dynamic = !fixed_rows && !fixed_cols; // Fully-dynamic size
-
-    template <EigenIndex i, EigenIndex ifzero> using if_zero = std::integral_constant<EigenIndex, i == 0 ? ifzero : i>;
-    static constexpr EigenIndex inner_stride = if_zero<StrideType::InnerStrideAtCompileTime, 1>::value,
-                                outer_stride = if_zero<StrideType::OuterStrideAtCompileTime,
-                                                       vector ? size : row_major ? cols : rows>::value;
-    static constexpr bool dynamic_stride = inner_stride == Eigen::Dynamic && outer_stride == Eigen::Dynamic;
-    static constexpr bool requires_row_major = !dynamic_stride && !vector && (row_major ? inner_stride : outer_stride) == 1;
-    static constexpr bool requires_col_major = !dynamic_stride && !vector && (row_major ? outer_stride : inner_stride) == 1;
+    static constexpr EigenIndex rows = Type::RowsAtCompileTime, cols = Type::ColsAtCompileTime,
+                                size = Type::SizeAtCompileTime;
+    static constexpr bool row_major = Type::IsRowMajor,
+                          vector
+                          = Type::IsVectorAtCompileTime, // At least one dimension has fixed size 1
+        fixed_rows = rows != Eigen::Dynamic, fixed_cols = cols != Eigen::Dynamic,
+                          fixed = size != Eigen::Dynamic, // Fully-fixed size
+        dynamic = !fixed_rows && !fixed_cols;             // Fully-dynamic size
+
+    template <EigenIndex i, EigenIndex ifzero>
+    using if_zero = std::integral_constant<EigenIndex, i == 0 ? ifzero : i>;
+    static constexpr EigenIndex inner_stride
+        = if_zero<StrideType::InnerStrideAtCompileTime, 1>::value,
+        outer_stride = if_zero < StrideType::OuterStrideAtCompileTime,
+        vector      ? size
+        : row_major ? cols
+                    : rows > ::value;
+    static constexpr bool dynamic_stride
+        = inner_stride == Eigen::Dynamic && outer_stride == Eigen::Dynamic;
+    static constexpr bool requires_row_major
+        = !dynamic_stride && !vector && (row_major ? inner_stride : outer_stride) == 1;
+    static constexpr bool requires_col_major
+        = !dynamic_stride && !vector && (row_major ? outer_stride : inner_stride) == 1;
 
     // Takes an input array and determines whether we can make it fit into the Eigen type.  If
     // the array is a vector, we attempt to fit it into either an Eigen 1xN or Nx1 vector
     // (preferring the latter if it will fit in either, i.e. for a fully dynamic matrix type).
     static EigenConformable<row_major> conformable(const array &a) {
         const auto dims = a.ndim();
-        if (dims < 1 || dims > 2)
+        if (dims < 1 || dims > 2) {
             return false;
+        }
 
         if (dims == 2) { // Matrix type: require exact match (or dynamic)
 
-            EigenIndex
-                np_rows = a.shape(0),
-                np_cols = a.shape(1),
-                np_rstride = a.strides(0) / static_cast<ssize_t>(sizeof(Scalar)),
-                np_cstride = a.strides(1) / static_cast<ssize_t>(sizeof(Scalar));
-            if ((fixed_rows && np_rows != rows) || (fixed_cols && np_cols != cols))
+            EigenIndex np_rows = a.shape(0), np_cols = a.shape(1),
+                       np_rstride = a.strides(0) / static_cast<ssize_t>(sizeof(Scalar)),
+                       np_cstride = a.strides(1) / static_cast<ssize_t>(sizeof(Scalar));
+            if ((PYBIND11_SILENCE_MSVC_C4127(fixed_rows) && np_rows != rows)
+                || (PYBIND11_SILENCE_MSVC_C4127(fixed_cols) && np_cols != cols)) {
                 return false;
+            }
 
             return {np_rows, np_cols, np_rstride, np_cstride};
         }
 
-        // Otherwise we're storing an n-vector.  Only one of the strides will be used, but whichever
-        // is used, we want the (single) numpy stride value.
+        // Otherwise we're storing an n-vector.  Only one of the strides will be used, but
+        // whichever is used, we want the (single) numpy stride value.
         const EigenIndex n = a.shape(0),
-              stride = a.strides(0) / static_cast<ssize_t>(sizeof(Scalar));
+                         stride = a.strides(0) / static_cast<ssize_t>(sizeof(Scalar));
 
         if (vector) { // Eigen type is a compile-time vector
-            if (fixed && size != n)
+            if (PYBIND11_SILENCE_MSVC_C4127(fixed) && size != n) {
                 return false; // Vector size mismatch
+            }
             return {rows == 1 ? 1 : n, cols == 1 ? 1 : n, stride};
         }
-        else if (fixed) {
+        if (fixed) {
             // The type has a fixed size, but is not a vector: abort
             return false;
         }
-        else if (fixed_cols) {
+        if (fixed_cols) {
             // Since this isn't a vector, cols must be != 1.  We allow this only if it exactly
             // equals the number of elements (rows is Dynamic, and so 1 row is allowed).
-            if (cols != n) return false;
+            if (cols != n) {
+                return false;
+            }
             return {1, n, stride};
+        } // Otherwise it's either fully dynamic, or column dynamic; both become a column vector
+        if (PYBIND11_SILENCE_MSVC_C4127(fixed_rows) && rows != n) {
+            return false;
         }
-        else {
-            // Otherwise it's either fully dynamic, or column dynamic; both become a column vector
-            if (fixed_rows && rows != n) return false;
-            return {n, 1, stride};
-        }
+        return {n, 1, stride};
     }
 
-    static constexpr bool show_writeable = is_eigen_dense_map<Type>::value && is_eigen_mutable_map<Type>::value;
+    static constexpr bool show_writeable
+        = is_eigen_dense_map<Type>::value && is_eigen_mutable_map<Type>::value;
     static constexpr bool show_order = is_eigen_dense_map<Type>::value;
     static constexpr bool show_c_contiguous = show_order && requires_row_major;
-    static constexpr bool show_f_contiguous = !show_c_contiguous && show_order && requires_col_major;
-
-    static constexpr auto descriptor =
-        _("numpy.ndarray[") + npy_format_descriptor<Scalar>::name +
-        _("[")  + _<fixed_rows>(_<(size_t) rows>(), _("m")) +
-        _(", ") + _<fixed_cols>(_<(size_t) cols>(), _("n")) +
-        _("]") +
-        // For a reference type (e.g. Ref<MatrixXd>) we have other constraints that might need to be
-        // satisfied: writeable=True (for a mutable reference), and, depending on the map's stride
-        // options, possibly f_contiguous or c_contiguous.  We include them in the descriptor output
-        // to provide some hint as to why a TypeError is occurring (otherwise it can be confusing to
-        // see that a function accepts a 'numpy.ndarray[float64[3,2]]' and an error message that you
-        // *gave* a numpy.ndarray of the right type and dimensions.
-        _<show_writeable>(", flags.writeable", "") +
-        _<show_c_contiguous>(", flags.c_contiguous", "") +
-        _<show_f_contiguous>(", flags.f_contiguous", "") +
-        _("]");
+    static constexpr bool show_f_contiguous
+        = !show_c_contiguous && show_order && requires_col_major;
+
+    static constexpr auto descriptor
+        = const_name("numpy.ndarray[") + npy_format_descriptor<Scalar>::name + const_name("[")
+          + const_name<fixed_rows>(const_name<(size_t) rows>(), const_name("m")) + const_name(", ")
+          + const_name<fixed_cols>(const_name<(size_t) cols>(), const_name("n")) + const_name("]")
+          +
+          // For a reference type (e.g. Ref<MatrixXd>) we have other constraints that might need to
+          // be satisfied: writeable=True (for a mutable reference), and, depending on the map's
+          // stride options, possibly f_contiguous or c_contiguous.  We include them in the
+          // descriptor output to provide some hint as to why a TypeError is occurring (otherwise
+          // it can be confusing to see that a function accepts a 'numpy.ndarray[float64[3,2]]' and
+          // an error message that you *gave* a numpy.ndarray of the right type and dimensions.
+          const_name<show_writeable>(", flags.writeable", "")
+          + const_name<show_c_contiguous>(", flags.c_contiguous", "")
+          + const_name<show_f_contiguous>(", flags.f_contiguous", "") + const_name("]");
 };
 
 // Casts an Eigen type to numpy array.  If given a base, the numpy array references the src data,
 // otherwise it'll make a copy.  writeable lets you turn off the writeable flag for the array.
-template <typename props> handle eigen_array_cast(typename props::Type const &src, handle base = handle(), bool writeable = true) {
+template <typename props>
+handle
+eigen_array_cast(typename props::Type const &src, handle base = handle(), bool writeable = true) {
     constexpr ssize_t elem_size = sizeof(typename props::Scalar);
     array a;
-    if (props::vector)
-        a = array({ src.size() }, { elem_size * src.innerStride() }, src.data(), base);
-    else
-        a = array({ src.rows(), src.cols() }, { elem_size * src.rowStride(), elem_size * src.colStride() },
-                  src.data(), base);
+    if (props::vector) {
+        a = array({src.size()}, {elem_size * src.innerStride()}, src.data(), base);
+    } else {
+        a = array({src.rows(), src.cols()},
+                  {elem_size * src.rowStride(), elem_size * src.colStride()},
+                  src.data(),
+                  base);
+    }
 
-    if (!writeable)
+    if (!writeable) {
         array_proxy(a.ptr())->flags &= ~detail::npy_api::NPY_ARRAY_WRITEABLE_;
+    }
 
     return a.release();
 }
@@ -236,10 +284,10 @@ handle eigen_ref_array(Type &src, handle parent = none()) {
     return eigen_array_cast<props>(src, parent, !std::is_const<Type>::value);
 }
 
-// Takes a pointer to some dense, plain Eigen type, builds a capsule around it, then returns a numpy
-// array that references the encapsulated data with a python-side reference to the capsule to tie
-// its destruction to that of any dependent python objects.  Const-ness is determined by whether or
-// not the Type of the pointer given is const.
+// Takes a pointer to some dense, plain Eigen type, builds a capsule around it, then returns a
+// numpy array that references the encapsulated data with a python-side reference to the capsule to
+// tie its destruction to that of any dependent python objects.  Const-ness is determined by
+// whether or not the Type of the pointer given is const.
 template <typename props, typename Type, typename = enable_if_t<is_eigen_dense_plain<Type>::value>>
 handle eigen_encapsulate(Type *src) {
     capsule base(src, [](void *o) { delete static_cast<Type *>(o); });
@@ -248,35 +296,42 @@ handle eigen_encapsulate(Type *src) {
 
 // Type caster for regular, dense matrix types (e.g. MatrixXd), but not maps/refs/etc. of dense
 // types.
-template<typename Type>
+template <typename Type>
 struct type_caster<Type, enable_if_t<is_eigen_dense_plain<Type>::value>> {
     using Scalar = typename Type::Scalar;
     using props = EigenProps<Type>;
 
     bool load(handle src, bool convert) {
         // If we're in no-convert mode, only load if given an array of the correct type
-        if (!convert && !isinstance<array_t<Scalar>>(src))
+        if (!convert && !isinstance<array_t<Scalar>>(src)) {
             return false;
+        }
 
         // Coerce into an array, but don't do type conversion yet; the copy below handles it.
         auto buf = array::ensure(src);
 
-        if (!buf)
+        if (!buf) {
             return false;
+        }
 
         auto dims = buf.ndim();
-        if (dims < 1 || dims > 2)
+        if (dims < 1 || dims > 2) {
             return false;
+        }
 
         auto fits = props::conformable(buf);
-        if (!fits)
+        if (!fits) {
             return false;
+        }
 
         // Allocate the new type, then build a numpy reference into it
         value = Type(fits.rows, fits.cols);
         auto ref = reinterpret_steal<array>(eigen_ref_array<props>(value));
-        if (dims == 1) ref = ref.squeeze();
-        else if (ref.ndim() == 1) buf = buf.squeeze();
+        if (dims == 1) {
+            ref = ref.squeeze();
+        } else if (ref.ndim() == 1) {
+            buf = buf.squeeze();
+        }
 
         int result = detail::npy_api::get().PyArray_CopyInto_(ref.ptr(), buf.ptr());
 
@@ -289,7 +344,6 @@ struct type_caster<Type, enable_if_t<is_eigen_dense_plain<Type>::value>> {
     }
 
 private:
-
     // Cast implementation
     template <typename CType>
     static handle cast_impl(CType *src, return_value_policy policy, handle parent) {
@@ -312,7 +366,6 @@ struct type_caster<Type, enable_if_t<is_eigen_dense_plain<Type>::value>> {
     }
 
 public:
-
     // Normal returned non-reference, non-const value:
     static handle cast(Type &&src, return_value_policy /* policy */, handle parent) {
         return cast_impl(&src, return_value_policy::move, parent);
@@ -323,14 +376,18 @@ struct type_caster<Type, enable_if_t<is_eigen_dense_plain<Type>::value>> {
     }
     // lvalue reference return; default (automatic) becomes copy
     static handle cast(Type &src, return_value_policy policy, handle parent) {
-        if (policy == return_value_policy::automatic || policy == return_value_policy::automatic_reference)
+        if (policy == return_value_policy::automatic
+            || policy == return_value_policy::automatic_reference) {
             policy = return_value_policy::copy;
+        }
         return cast_impl(&src, policy, parent);
     }
     // const lvalue reference return; default (automatic) becomes copy
     static handle cast(const Type &src, return_value_policy policy, handle parent) {
-        if (policy == return_value_policy::automatic || policy == return_value_policy::automatic_reference)
+        if (policy == return_value_policy::automatic
+            || policy == return_value_policy::automatic_reference) {
             policy = return_value_policy::copy;
+        }
         return cast(&src, policy, parent);
     }
     // non-const pointer return
@@ -344,28 +401,32 @@ struct type_caster<Type, enable_if_t<is_eigen_dense_plain<Type>::value>> {
 
     static constexpr auto name = props::descriptor;
 
-    operator Type*() { return &value; }
-    operator Type&() { return value; }
-    operator Type&&() && { return std::move(value); }
-    template <typename T> using cast_op_type = movable_cast_op_type<T>;
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator Type *() { return &value; }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator Type &() { return value; }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator Type &&() && { return std::move(value); }
+    template <typename T>
+    using cast_op_type = movable_cast_op_type<T>;
 
 private:
     Type value;
 };
 
 // Base class for casting reference/map/block/etc. objects back to python.
-template <typename MapType> struct eigen_map_caster {
+template <typename MapType>
+struct eigen_map_caster {
 private:
     using props = EigenProps<MapType>;
 
 public:
-
     // Directly referencing a ref/map's data is a bit dangerous (whatever the map/ref points to has
-    // to stay around), but we'll allow it under the assumption that you know what you're doing (and
-    // have an appropriate keep_alive in place).  We return a numpy array pointing directly at the
-    // ref's data (The numpy array ends up read-only if the ref was to a const matrix type.) Note
-    // that this means you need to ensure you don't destroy the object in some other way (e.g. with
-    // an appropriate keep_alive, or with a reference to a statically allocated matrix).
+    // to stay around), but we'll allow it under the assumption that you know what you're doing
+    // (and have an appropriate keep_alive in place).  We return a numpy array pointing directly at
+    // the ref's data (The numpy array ends up read-only if the ref was to a const matrix type.)
+    // Note that this means you need to ensure you don't destroy the object in some other way (e.g.
+    // with an appropriate keep_alive, or with a reference to a statically allocated matrix).
     static handle cast(const MapType &src, return_value_policy policy, handle parent) {
         switch (policy) {
             case return_value_policy::copy:
@@ -389,43 +450,50 @@ template <typename MapType> struct eigen_map_caster {
     // you end up here if you try anyway.
     bool load(handle, bool) = delete;
     operator MapType() = delete;
-    template <typename> using cast_op_type = MapType;
+    template <typename>
+    using cast_op_type = MapType;
 };
 
 // We can return any map-like object (but can only load Refs, specialized next):
-template <typename Type> struct type_caster<Type, enable_if_t<is_eigen_dense_map<Type>::value>>
-    : eigen_map_caster<Type> {};
+template <typename Type>
+struct type_caster<Type, enable_if_t<is_eigen_dense_map<Type>::value>> : eigen_map_caster<Type> {};
 
 // Loader for Ref<...> arguments.  See the documentation for info on how to make this work without
 // copying (it requires some extra effort in many cases).
 template <typename PlainObjectType, typename StrideType>
 struct type_caster<
     Eigen::Ref<PlainObjectType, 0, StrideType>,
-    enable_if_t<is_eigen_dense_map<Eigen::Ref<PlainObjectType, 0, StrideType>>::value>
-> : public eigen_map_caster<Eigen::Ref<PlainObjectType, 0, StrideType>> {
+    enable_if_t<is_eigen_dense_map<Eigen::Ref<PlainObjectType, 0, StrideType>>::value>>
+    : public eigen_map_caster<Eigen::Ref<PlainObjectType, 0, StrideType>> {
 private:
     using Type = Eigen::Ref<PlainObjectType, 0, StrideType>;
     using props = EigenProps<Type>;
     using Scalar = typename props::Scalar;
     using MapType = Eigen::Map<PlainObjectType, 0, StrideType>;
-    using Array = array_t<Scalar, array::forcecast |
-                ((props::row_major ? props::inner_stride : props::outer_stride) == 1 ? array::c_style :
-                 (props::row_major ? props::outer_stride : props::inner_stride) == 1 ? array::f_style : 0)>;
+    using Array
+        = array_t<Scalar,
+                  array::forcecast
+                      | ((props::row_major ? props::inner_stride : props::outer_stride) == 1
+                             ? array::c_style
+                         : (props::row_major ? props::outer_stride : props::inner_stride) == 1
+                             ? array::f_style
+                             : 0)>;
     static constexpr bool need_writeable = is_eigen_mutable_map<Type>::value;
     // Delay construction (these have no default constructor)
     std::unique_ptr<MapType> map;
     std::unique_ptr<Type> ref;
     // Our array.  When possible, this is just a numpy array pointing to the source data, but
-    // sometimes we can't avoid copying (e.g. input is not a numpy array at all, has an incompatible
-    // layout, or is an array of a type that needs to be converted).  Using a numpy temporary
-    // (rather than an Eigen temporary) saves an extra copy when we need both type conversion and
-    // storage order conversion.  (Note that we refuse to use this temporary copy when loading an
-    // argument for a Ref<M> with M non-const, i.e. a read-write reference).
+    // sometimes we can't avoid copying (e.g. input is not a numpy array at all, has an
+    // incompatible layout, or is an array of a type that needs to be converted).  Using a numpy
+    // temporary (rather than an Eigen temporary) saves an extra copy when we need both type
+    // conversion and storage order conversion.  (Note that we refuse to use this temporary copy
+    // when loading an argument for a Ref<M> with M non-const, i.e. a read-write reference).
     Array copy_or_ref;
+
 public:
     bool load(handle src, bool convert) {
-        // First check whether what we have is already an array of the right type.  If not, we can't
-        // avoid a copy (because the copy is also going to do type conversion).
+        // First check whether what we have is already an array of the right type.  If not, we
+        // can't avoid a copy (because the copy is also going to do type conversion).
         bool need_copy = !isinstance<Array>(src);
 
         EigenConformable<props::row_major> fits;
@@ -436,13 +504,15 @@ struct type_caster<
 
             if (aref && (!need_writeable || aref.writeable())) {
                 fits = props::conformable(aref);
-                if (!fits) return false; // Incompatible dimensions
-                if (!fits.template stride_compatible<props>())
+                if (!fits) {
+                    return false; // Incompatible dimensions
+                }
+                if (!fits.template stride_compatible<props>()) {
                     need_copy = true;
-                else
+                } else {
                     copy_or_ref = std::move(aref);
-            }
-            else {
+                }
+            } else {
                 need_copy = true;
             }
         }
@@ -451,64 +521,93 @@ struct type_caster<
             // We need to copy: If we need a mutable reference, or we're not supposed to convert
             // (either because we're in the no-convert overload pass, or because we're explicitly
             // instructed not to copy (via `py::arg().noconvert()`) we have to fail loading.
-            if (!convert || need_writeable) return false;
+            if (!convert || need_writeable) {
+                return false;
+            }
 
             Array copy = Array::ensure(src);
-            if (!copy) return false;
+            if (!copy) {
+                return false;
+            }
             fits = props::conformable(copy);
-            if (!fits || !fits.template stride_compatible<props>())
+            if (!fits || !fits.template stride_compatible<props>()) {
                 return false;
+            }
             copy_or_ref = std::move(copy);
             loader_life_support::add_patient(copy_or_ref);
         }
 
         ref.reset();
-        map.reset(new MapType(data(copy_or_ref), fits.rows, fits.cols, make_stride(fits.stride.outer(), fits.stride.inner())));
+        map.reset(new MapType(data(copy_or_ref),
+                              fits.rows,
+                              fits.cols,
+                              make_stride(fits.stride.outer(), fits.stride.inner())));
         ref.reset(new Type(*map));
 
         return true;
     }
 
-    operator Type*() { return ref.get(); }
-    operator Type&() { return *ref; }
-    template <typename _T> using cast_op_type = pybind11::detail::cast_op_type<_T>;
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator Type *() { return ref.get(); }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator Type &() { return *ref; }
+    template <typename _T>
+    using cast_op_type = pybind11::detail::cast_op_type<_T>;
 
 private:
     template <typename T = Type, enable_if_t<is_eigen_mutable_map<T>::value, int> = 0>
-    Scalar *data(Array &a) { return a.mutable_data(); }
+    Scalar *data(Array &a) {
+        return a.mutable_data();
+    }
 
     template <typename T = Type, enable_if_t<!is_eigen_mutable_map<T>::value, int> = 0>
-    const Scalar *data(Array &a) { return a.data(); }
+    const Scalar *data(Array &a) {
+        return a.data();
+    }
 
     // Attempt to figure out a constructor of `Stride` that will work.
     // If both strides are fixed, use a default constructor:
-    template <typename S> using stride_ctor_default = bool_constant<
-        S::InnerStrideAtCompileTime != Eigen::Dynamic && S::OuterStrideAtCompileTime != Eigen::Dynamic &&
-        std::is_default_constructible<S>::value>;
+    template <typename S>
+    using stride_ctor_default = bool_constant<S::InnerStrideAtCompileTime != Eigen::Dynamic
+                                              && S::OuterStrideAtCompileTime != Eigen::Dynamic
+                                              && std::is_default_constructible<S>::value>;
     // Otherwise, if there is a two-index constructor, assume it is (outer,inner) like
     // Eigen::Stride, and use it:
-    template <typename S> using stride_ctor_dual = bool_constant<
-        !stride_ctor_default<S>::value && std::is_constructible<S, EigenIndex, EigenIndex>::value>;
+    template <typename S>
+    using stride_ctor_dual
+        = bool_constant<!stride_ctor_default<S>::value
+                        && std::is_constructible<S, EigenIndex, EigenIndex>::value>;
     // Otherwise, if there is a one-index constructor, and just one of the strides is dynamic, use
     // it (passing whichever stride is dynamic).
-    template <typename S> using stride_ctor_outer = bool_constant<
-        !any_of<stride_ctor_default<S>, stride_ctor_dual<S>>::value &&
-        S::OuterStrideAtCompileTime == Eigen::Dynamic && S::InnerStrideAtCompileTime != Eigen::Dynamic &&
-        std::is_constructible<S, EigenIndex>::value>;
-    template <typename S> using stride_ctor_inner = bool_constant<
-        !any_of<stride_ctor_default<S>, stride_ctor_dual<S>>::value &&
-        S::InnerStrideAtCompileTime == Eigen::Dynamic && S::OuterStrideAtCompileTime != Eigen::Dynamic &&
-        std::is_constructible<S, EigenIndex>::value>;
+    template <typename S>
+    using stride_ctor_outer
+        = bool_constant<!any_of<stride_ctor_default<S>, stride_ctor_dual<S>>::value
+                        && S::OuterStrideAtCompileTime == Eigen::Dynamic
+                        && S::InnerStrideAtCompileTime != Eigen::Dynamic
+                        && std::is_constructible<S, EigenIndex>::value>;
+    template <typename S>
+    using stride_ctor_inner
+        = bool_constant<!any_of<stride_ctor_default<S>, stride_ctor_dual<S>>::value
+                        && S::InnerStrideAtCompileTime == Eigen::Dynamic
+                        && S::OuterStrideAtCompileTime != Eigen::Dynamic
+                        && std::is_constructible<S, EigenIndex>::value>;
 
     template <typename S = StrideType, enable_if_t<stride_ctor_default<S>::value, int> = 0>
-    static S make_stride(EigenIndex, EigenIndex) { return S(); }
+    static S make_stride(EigenIndex, EigenIndex) {
+        return S();
+    }
     template <typename S = StrideType, enable_if_t<stride_ctor_dual<S>::value, int> = 0>
-    static S make_stride(EigenIndex outer, EigenIndex inner) { return S(outer, inner); }
+    static S make_stride(EigenIndex outer, EigenIndex inner) {
+        return S(outer, inner);
+    }
     template <typename S = StrideType, enable_if_t<stride_ctor_outer<S>::value, int> = 0>
-    static S make_stride(EigenIndex outer, EigenIndex) { return S(outer); }
+    static S make_stride(EigenIndex outer, EigenIndex) {
+        return S(outer);
+    }
     template <typename S = StrideType, enable_if_t<stride_ctor_inner<S>::value, int> = 0>
-    static S make_stride(EigenIndex, EigenIndex inner) { return S(inner); }
-
+    static S make_stride(EigenIndex, EigenIndex inner) {
+        return S(inner);
+    }
 };
 
 // type_caster for special matrix types (e.g. DiagonalMatrix), which are EigenBase, but not
@@ -518,14 +617,18 @@ struct type_caster<
 template <typename Type>
 struct type_caster<Type, enable_if_t<is_eigen_other<Type>::value>> {
 protected:
-    using Matrix = Eigen::Matrix<typename Type::Scalar, Type::RowsAtCompileTime, Type::ColsAtCompileTime>;
+    using Matrix
+        = Eigen::Matrix<typename Type::Scalar, Type::RowsAtCompileTime, Type::ColsAtCompileTime>;
     using props = EigenProps<Matrix>;
+
 public:
     static handle cast(const Type &src, return_value_policy /* policy */, handle /* parent */) {
         handle h = eigen_encapsulate<props>(new Matrix(src));
         return h;
     }
-    static handle cast(const Type *src, return_value_policy policy, handle parent) { return cast(*src, policy, parent); }
+    static handle cast(const Type *src, return_value_policy policy, handle parent) {
+        return cast(*src, policy, parent);
+    }
 
     static constexpr auto name = props::descriptor;
 
@@ -534,10 +637,11 @@ struct type_caster<Type, enable_if_t<is_eigen_other<Type>::value>> {
     // you end up here if you try anyway.
     bool load(handle, bool) = delete;
     operator Type() = delete;
-    template <typename> using cast_op_type = Type;
+    template <typename>
+    using cast_op_type = Type;
 };
 
-template<typename Type>
+template <typename Type>
 struct type_caster<Type, enable_if_t<is_eigen_sparse<Type>::value>> {
     using Scalar = typename Type::Scalar;
     using StorageIndex = remove_reference_t<decltype(*std::declval<Type>().outerIndexPtr())>;
@@ -545,13 +649,13 @@ struct type_caster<Type, enable_if_t<is_eigen_sparse<Type>::value>> {
     static constexpr bool rowMajor = Type::IsRowMajor;
 
     bool load(handle src, bool) {
-        if (!src)
+        if (!src) {
             return false;
+        }
 
         auto obj = reinterpret_borrow<object>(src);
         object sparse_module = module_::import("scipy.sparse");
-        object matrix_type = sparse_module.attr(
-            rowMajor ? "csr_matrix" : "csc_matrix");
+        object matrix_type = sparse_module.attr(rowMajor ? "csr_matrix" : "csc_matrix");
 
         if (!type::handle_of(obj).is(matrix_type)) {
             try {
@@ -567,41 +671,43 @@ struct type_caster<Type, enable_if_t<is_eigen_sparse<Type>::value>> {
         auto shape = pybind11::tuple((pybind11::object) obj.attr("shape"));
         auto nnz = obj.attr("nnz").cast<Index>();
 
-        if (!values || !innerIndices || !outerIndices)
+        if (!values || !innerIndices || !outerIndices) {
             return false;
+        }
 
-        value = Eigen::MappedSparseMatrix<Scalar, Type::Flags, StorageIndex>(
-            shape[0].cast<Index>(), shape[1].cast<Index>(), nnz,
-            outerIndices.mutable_data(), innerIndices.mutable_data(), values.mutable_data());
+        value = EigenMapSparseMatrix<Scalar,
+                                     Type::Flags &(Eigen::RowMajor | Eigen::ColMajor),
+                                     StorageIndex>(shape[0].cast<Index>(),
+                                                   shape[1].cast<Index>(),
+                                                   std::move(nnz),
+                                                   outerIndices.mutable_data(),
+                                                   innerIndices.mutable_data(),
+                                                   values.mutable_data());
 
         return true;
     }
 
     static handle cast(const Type &src, return_value_policy /* policy */, handle /* parent */) {
-        const_cast<Type&>(src).makeCompressed();
+        const_cast<Type &>(src).makeCompressed();
 
-        object matrix_type = module_::import("scipy.sparse").attr(
-            rowMajor ? "csr_matrix" : "csc_matrix");
+        object matrix_type
+            = module_::import("scipy.sparse").attr(rowMajor ? "csr_matrix" : "csc_matrix");
 
         array data(src.nonZeros(), src.valuePtr());
         array outerIndices((rowMajor ? src.rows() : src.cols()) + 1, src.outerIndexPtr());
         array innerIndices(src.nonZeros(), src.innerIndexPtr());
 
-        return matrix_type(
-            std::make_tuple(data, innerIndices, outerIndices),
-            std::make_pair(src.rows(), src.cols())
-        ).release();
+        return matrix_type(pybind11::make_tuple(
+                               std::move(data), std::move(innerIndices), std::move(outerIndices)),
+                           pybind11::make_tuple(src.rows(), src.cols()))
+            .release();
     }
 
-    PYBIND11_TYPE_CASTER(Type, _<(Type::IsRowMajor) != 0>("scipy.sparse.csr_matrix[", "scipy.sparse.csc_matrix[")
-            + npy_format_descriptor<Scalar>::name + _("]"));
+    PYBIND11_TYPE_CASTER(Type,
+                         const_name<(Type::IsRowMajor) != 0>("scipy.sparse.csr_matrix[",
+                                                             "scipy.sparse.csc_matrix[")
+                             + npy_format_descriptor<Scalar>::name + const_name("]"));
 };
 
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
-
-#if defined(__GNUG__) || defined(__clang__)
-#  pragma GCC diagnostic pop
-#elif defined(_MSC_VER)
-#  pragma warning(pop)
-#endif
diff --git a/3rdparty/pybind11/include/pybind11/embed.h b/3rdparty/pybind11/include/pybind11/embed.h
index 204aaf989f..0ac609e0f1 100644
--- a/3rdparty/pybind11/include/pybind11/embed.h
+++ b/3rdparty/pybind11/include/pybind11/embed.h
@@ -12,23 +12,16 @@
 #include "pybind11.h"
 #include "eval.h"
 
+#include <memory>
+#include <vector>
+
 #if defined(PYPY_VERSION)
-#  error Embedding the interpreter is not supported with PyPy
+#    error Embedding the interpreter is not supported with PyPy
 #endif
 
-#if PY_MAJOR_VERSION >= 3
-#  define PYBIND11_EMBEDDED_MODULE_IMPL(name)            \
-      extern "C" PyObject *pybind11_init_impl_##name();  \
-      extern "C" PyObject *pybind11_init_impl_##name() { \
-          return pybind11_init_wrapper_##name();         \
-      }
-#else
-#  define PYBIND11_EMBEDDED_MODULE_IMPL(name)            \
-      extern "C" void pybind11_init_impl_##name();       \
-      extern "C" void pybind11_init_impl_##name() {      \
-          pybind11_init_wrapper_##name();                \
-      }
-#endif
+#define PYBIND11_EMBEDDED_MODULE_IMPL(name)                                                       \
+    extern "C" PyObject *pybind11_init_impl_##name();                                             \
+    extern "C" PyObject *pybind11_init_impl_##name() { return pybind11_init_wrapper_##name(); }
 
 /** \rst
     Add a new module to the table of builtins for the interpreter. Must be
@@ -45,69 +38,143 @@
             });
         }
  \endrst */
-#define PYBIND11_EMBEDDED_MODULE(name, variable)                                \
-    static ::pybind11::module_::module_def                                      \
-        PYBIND11_CONCAT(pybind11_module_def_, name);                            \
-    static void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &);   \
-    static PyObject PYBIND11_CONCAT(*pybind11_init_wrapper_, name)() {          \
-        auto m = ::pybind11::module_::create_extension_module(                  \
-            PYBIND11_TOSTRING(name), nullptr,                                   \
-            &PYBIND11_CONCAT(pybind11_module_def_, name));                      \
-        try {                                                                   \
-            PYBIND11_CONCAT(pybind11_init_, name)(m);                           \
-            return m.ptr();                                                     \
-        } PYBIND11_CATCH_INIT_EXCEPTIONS                                        \
-    }                                                                           \
-    PYBIND11_EMBEDDED_MODULE_IMPL(name)                                         \
-    ::pybind11::detail::embedded_module PYBIND11_CONCAT(pybind11_module_, name) \
-                              (PYBIND11_TOSTRING(name),                         \
-                               PYBIND11_CONCAT(pybind11_init_impl_, name));     \
-    void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &variable)
-
+#define PYBIND11_EMBEDDED_MODULE(name, variable)                                                  \
+    static ::pybind11::module_::module_def PYBIND11_CONCAT(pybind11_module_def_, name);           \
+    static void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ &);                     \
+    static PyObject PYBIND11_CONCAT(*pybind11_init_wrapper_, name)() {                            \
+        auto m = ::pybind11::module_::create_extension_module(                                    \
+            PYBIND11_TOSTRING(name), nullptr, &PYBIND11_CONCAT(pybind11_module_def_, name));      \
+        try {                                                                                     \
+            PYBIND11_CONCAT(pybind11_init_, name)(m);                                             \
+            return m.ptr();                                                                       \
+        }                                                                                         \
+        PYBIND11_CATCH_INIT_EXCEPTIONS                                                            \
+    }                                                                                             \
+    PYBIND11_EMBEDDED_MODULE_IMPL(name)                                                           \
+    ::pybind11::detail::embedded_module PYBIND11_CONCAT(pybind11_module_, name)(                  \
+        PYBIND11_TOSTRING(name), PYBIND11_CONCAT(pybind11_init_impl_, name));                     \
+    void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_                                \
+                                               & variable) // NOLINT(bugprone-macro-parentheses)
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 /// Python 2.7/3.x compatible version of `PyImport_AppendInittab` and error checks.
 struct embedded_module {
-#if PY_MAJOR_VERSION >= 3
-    using init_t = PyObject *(*)();
-#else
-    using init_t = void (*)();
-#endif
+    using init_t = PyObject *(*) ();
     embedded_module(const char *name, init_t init) {
-        if (Py_IsInitialized())
+        if (Py_IsInitialized() != 0) {
             pybind11_fail("Can't add new modules after the interpreter has been initialized");
+        }
 
         auto result = PyImport_AppendInittab(name, init);
-        if (result == -1)
+        if (result == -1) {
             pybind11_fail("Insufficient memory to add a new module");
+        }
     }
 };
 
+struct wide_char_arg_deleter {
+    void operator()(wchar_t *ptr) const {
+        // API docs: https://docs.python.org/3/c-api/sys.html#c.Py_DecodeLocale
+        PyMem_RawFree(ptr);
+    }
+};
+
+inline wchar_t *widen_chars(const char *safe_arg) {
+    wchar_t *widened_arg = Py_DecodeLocale(safe_arg, nullptr);
+    return widened_arg;
+}
+
 PYBIND11_NAMESPACE_END(detail)
 
 /** \rst
     Initialize the Python interpreter. No other pybind11 or CPython API functions can be
     called before this is done; with the exception of `PYBIND11_EMBEDDED_MODULE`. The
-    optional parameter can be used to skip the registration of signal handlers (see the
-    `Python documentation`_ for details). Calling this function again after the interpreter
-    has already been initialized is a fatal error.
+    optional `init_signal_handlers` parameter can be used to skip the registration of
+    signal handlers (see the `Python documentation`_ for details). Calling this function
+    again after the interpreter has already been initialized is a fatal error.
 
     If initializing the Python interpreter fails, then the program is terminated.  (This
     is controlled by the CPython runtime and is an exception to pybind11's normal behavior
     of throwing exceptions on errors.)
 
+    The remaining optional parameters, `argc`, `argv`, and `add_program_dir_to_path` are
+    used to populate ``sys.argv`` and ``sys.path``.
+    See the |PySys_SetArgvEx documentation|_ for details.
+
     .. _Python documentation: https://docs.python.org/3/c-api/init.html#c.Py_InitializeEx
+    .. |PySys_SetArgvEx documentation| replace:: ``PySys_SetArgvEx`` documentation
+    .. _PySys_SetArgvEx documentation: https://docs.python.org/3/c-api/init.html#c.PySys_SetArgvEx
  \endrst */
-inline void initialize_interpreter(bool init_signal_handlers = true) {
-    if (Py_IsInitialized())
+inline void initialize_interpreter(bool init_signal_handlers = true,
+                                   int argc = 0,
+                                   const char *const *argv = nullptr,
+                                   bool add_program_dir_to_path = true) {
+    if (Py_IsInitialized() != 0) {
         pybind11_fail("The interpreter is already running");
+    }
+
+#if PY_VERSION_HEX < 0x030B0000
 
     Py_InitializeEx(init_signal_handlers ? 1 : 0);
 
-    // Make .py files in the working directory available by default
-    module_::import("sys").attr("path").cast<list>().append(".");
+    // Before it was special-cased in python 3.8, passing an empty or null argv
+    // caused a segfault, so we have to reimplement the special case ourselves.
+    bool special_case = (argv == nullptr || argc <= 0);
+
+    const char *const empty_argv[]{"\0"};
+    const char *const *safe_argv = special_case ? empty_argv : argv;
+    if (special_case) {
+        argc = 1;
+    }
+
+    auto argv_size = static_cast<size_t>(argc);
+    // SetArgv* on python 3 takes wchar_t, so we have to convert.
+    std::unique_ptr<wchar_t *[]> widened_argv(new wchar_t *[argv_size]);
+    std::vector<std::unique_ptr<wchar_t[], detail::wide_char_arg_deleter>> widened_argv_entries;
+    widened_argv_entries.reserve(argv_size);
+    for (size_t ii = 0; ii < argv_size; ++ii) {
+        widened_argv_entries.emplace_back(detail::widen_chars(safe_argv[ii]));
+        if (!widened_argv_entries.back()) {
+            // A null here indicates a character-encoding failure or the python
+            // interpreter out of memory. Give up.
+            return;
+        }
+        widened_argv[ii] = widened_argv_entries.back().get();
+    }
+
+    auto *pysys_argv = widened_argv.get();
+
+    PySys_SetArgvEx(argc, pysys_argv, static_cast<int>(add_program_dir_to_path));
+#else
+    PyConfig config;
+    PyConfig_InitIsolatedConfig(&config);
+    config.isolated = 0;
+    config.use_environment = 1;
+    config.install_signal_handlers = init_signal_handlers ? 1 : 0;
+
+    PyStatus status = PyConfig_SetBytesArgv(&config, argc, const_cast<char *const *>(argv));
+    if (PyStatus_Exception(status)) {
+        // A failure here indicates a character-encoding failure or the python
+        // interpreter out of memory. Give up.
+        PyConfig_Clear(&config);
+        throw std::runtime_error(PyStatus_IsError(status) ? status.err_msg
+                                                          : "Failed to prepare CPython");
+    }
+    status = Py_InitializeFromConfig(&config);
+    PyConfig_Clear(&config);
+    if (PyStatus_Exception(status)) {
+        throw std::runtime_error(PyStatus_IsError(status) ? status.err_msg
+                                                          : "Failed to init CPython");
+    }
+    if (add_program_dir_to_path) {
+        PyRun_SimpleString("import sys, os.path; "
+                           "sys.path.insert(0, "
+                           "os.path.abspath(os.path.dirname(sys.argv[0])) "
+                           "if sys.argv and os.path.exists(sys.argv[0]) else '')");
+    }
+#endif
 }
 
 /** \rst
@@ -154,8 +221,13 @@ inline void finalize_interpreter() {
     // during destruction), so we get the pointer-pointer here and check it after Py_Finalize().
     detail::internals **internals_ptr_ptr = detail::get_internals_pp();
     // It could also be stashed in builtins, so look there too:
-    if (builtins.contains(id) && isinstance<capsule>(builtins[id]))
+    if (builtins.contains(id) && isinstance<capsule>(builtins[id])) {
         internals_ptr_ptr = capsule(builtins[id]);
+    }
+    // Local internals contains data managed by the current interpreter, so we must clear them to
+    // avoid undefined behaviors when initializing another interpreter
+    detail::get_local_internals().registered_types_cpp.clear();
+    detail::get_local_internals().registered_exception_translators.clear();
 
     Py_Finalize();
 
@@ -169,6 +241,8 @@ inline void finalize_interpreter() {
     Scope guard version of `initialize_interpreter` and `finalize_interpreter`.
     This a move-only guard and only a single instance can exist.
 
+    See `initialize_interpreter` for a discussion of its constructor arguments.
+
     .. code-block:: cpp
 
         #include <pybind11/embed.h>
@@ -180,8 +254,11 @@ inline void finalize_interpreter() {
  \endrst */
 class scoped_interpreter {
 public:
-    scoped_interpreter(bool init_signal_handlers = true) {
-        initialize_interpreter(init_signal_handlers);
+    explicit scoped_interpreter(bool init_signal_handlers = true,
+                                int argc = 0,
+                                const char *const *argv = nullptr,
+                                bool add_program_dir_to_path = true) {
+        initialize_interpreter(init_signal_handlers, argc, argv, add_program_dir_to_path);
     }
 
     scoped_interpreter(const scoped_interpreter &) = delete;
@@ -190,8 +267,9 @@ class scoped_interpreter {
     scoped_interpreter &operator=(scoped_interpreter &&) = delete;
 
     ~scoped_interpreter() {
-        if (is_valid)
+        if (is_valid) {
             finalize_interpreter();
+        }
     }
 
 private:
diff --git a/3rdparty/pybind11/include/pybind11/eval.h b/3rdparty/pybind11/include/pybind11/eval.h
index fa6b8af479..bd5f981f53 100644
--- a/3rdparty/pybind11/include/pybind11/eval.h
+++ b/3rdparty/pybind11/include/pybind11/eval.h
@@ -1,5 +1,5 @@
 /*
-    pybind11/exec.h: Support for evaluating Python expressions and statements
+    pybind11/eval.h: Support for evaluating Python expressions and statements
     from strings and files
 
     Copyright (c) 2016 Klemens Morgenstern <klemens.morgenstern@ed-chemnitz.de> and
@@ -13,20 +13,22 @@
 
 #include "pybind11.h"
 
+#include <utility>
+
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 inline void ensure_builtins_in_globals(object &global) {
-    #if PY_VERSION_HEX < 0x03080000
-        // Running exec and eval on Python 2 and 3 adds `builtins` module under
-        // `__builtins__` key to globals if not yet present.
-        // Python 3.8 made PyRun_String behave similarly. Let's also do that for
-        // older versions, for consistency.
-        if (!global.contains("__builtins__"))
-            global["__builtins__"] = module_::import(PYBIND11_BUILTINS_MODULE);
-    #else
-        (void) global;
-    #endif
+#if defined(PYPY_VERSION) || PY_VERSION_HEX < 0x03080000
+    // Running exec and eval adds `builtins` module under `__builtins__` key to
+    // globals if not yet present.  Python 3.8 made PyRun_String behave
+    // similarly. Let's also do that for older versions, for consistency. This
+    // was missing from PyPy3.8 7.3.7.
+    if (!global.contains("__builtins__"))
+        global["__builtins__"] = module_::import(PYBIND11_BUILTINS_MODULE);
+#else
+    (void) global;
+#endif
 }
 
 PYBIND11_NAMESPACE_END(detail)
@@ -43,9 +45,10 @@ enum eval_mode {
 };
 
 template <eval_mode mode = eval_expr>
-object eval(str expr, object global = globals(), object local = object()) {
-    if (!local)
+object eval(const str &expr, object global = globals(), object local = object()) {
+    if (!local) {
         local = global;
+    }
 
     detail::ensure_builtins_in_globals(global);
 
@@ -53,38 +56,45 @@ object eval(str expr, object global = globals(), object local = object()) {
        this seems to be the only alternative */
     std::string buffer = "# -*- coding: utf-8 -*-\n" + (std::string) expr;
 
-    int start;
+    int start = 0;
     switch (mode) {
-        case eval_expr:             start = Py_eval_input;   break;
-        case eval_single_statement: start = Py_single_input; break;
-        case eval_statements:       start = Py_file_input;   break;
-        default: pybind11_fail("invalid evaluation mode");
+        case eval_expr:
+            start = Py_eval_input;
+            break;
+        case eval_single_statement:
+            start = Py_single_input;
+            break;
+        case eval_statements:
+            start = Py_file_input;
+            break;
+        default:
+            pybind11_fail("invalid evaluation mode");
     }
 
     PyObject *result = PyRun_String(buffer.c_str(), start, global.ptr(), local.ptr());
-    if (!result)
+    if (!result) {
         throw error_already_set();
+    }
     return reinterpret_steal<object>(result);
 }
 
 template <eval_mode mode = eval_expr, size_t N>
 object eval(const char (&s)[N], object global = globals(), object local = object()) {
     /* Support raw string literals by removing common leading whitespace */
-    auto expr = (s[0] == '\n') ? str(module_::import("textwrap").attr("dedent")(s))
-                               : str(s);
-    return eval<mode>(expr, global, local);
+    auto expr = (s[0] == '\n') ? str(module_::import("textwrap").attr("dedent")(s)) : str(s);
+    return eval<mode>(expr, std::move(global), std::move(local));
 }
 
-inline void exec(str expr, object global = globals(), object local = object()) {
-    eval<eval_statements>(expr, global, local);
+inline void exec(const str &expr, object global = globals(), object local = object()) {
+    eval<eval_statements>(expr, std::move(global), std::move(local));
 }
 
 template <size_t N>
 void exec(const char (&s)[N], object global = globals(), object local = object()) {
-    eval<eval_statements>(s, global, local);
+    eval<eval_statements>(s, std::move(global), std::move(local));
 }
 
-#if defined(PYPY_VERSION) && PY_VERSION_HEX >= 0x03000000
+#if defined(PYPY_VERSION)
 template <eval_mode mode = eval_statements>
 object eval_file(str, object, object) {
     pybind11_fail("eval_file not supported in PyPy3. Use eval");
@@ -100,51 +110,45 @@ object eval_file(str) {
 #else
 template <eval_mode mode = eval_statements>
 object eval_file(str fname, object global = globals(), object local = object()) {
-    if (!local)
+    if (!local) {
         local = global;
+    }
 
     detail::ensure_builtins_in_globals(global);
 
-    int start;
+    int start = 0;
     switch (mode) {
-        case eval_expr:             start = Py_eval_input;   break;
-        case eval_single_statement: start = Py_single_input; break;
-        case eval_statements:       start = Py_file_input;   break;
-        default: pybind11_fail("invalid evaluation mode");
+        case eval_expr:
+            start = Py_eval_input;
+            break;
+        case eval_single_statement:
+            start = Py_single_input;
+            break;
+        case eval_statements:
+            start = Py_file_input;
+            break;
+        default:
+            pybind11_fail("invalid evaluation mode");
     }
 
     int closeFile = 1;
     std::string fname_str = (std::string) fname;
-#if PY_VERSION_HEX >= 0x03040000
     FILE *f = _Py_fopen_obj(fname.ptr(), "r");
-#elif PY_VERSION_HEX >= 0x03000000
-    FILE *f = _Py_fopen(fname.ptr(), "r");
-#else
-    /* No unicode support in open() :( */
-    auto fobj = reinterpret_steal<object>(PyFile_FromString(
-        const_cast<char *>(fname_str.c_str()),
-        const_cast<char*>("r")));
-    FILE *f = nullptr;
-    if (fobj)
-        f = PyFile_AsFile(fobj.ptr());
-    closeFile = 0;
-#endif
     if (!f) {
         PyErr_Clear();
         pybind11_fail("File \"" + fname_str + "\" could not be opened!");
     }
 
-#if PY_VERSION_HEX < 0x03000000 && defined(PYPY_VERSION)
-    PyObject *result = PyRun_File(f, fname_str.c_str(), start, global.ptr(),
-                                  local.ptr());
-    (void) closeFile;
-#else
-    PyObject *result = PyRun_FileEx(f, fname_str.c_str(), start, global.ptr(),
-                                    local.ptr(), closeFile);
-#endif
+    if (!global.contains("__file__")) {
+        global["__file__"] = std::move(fname);
+    }
+
+    PyObject *result
+        = PyRun_FileEx(f, fname_str.c_str(), start, global.ptr(), local.ptr(), closeFile);
 
-    if (!result)
+    if (!result) {
         throw error_already_set();
+    }
     return reinterpret_steal<object>(result);
 }
 #endif
diff --git a/3rdparty/pybind11/include/pybind11/functional.h b/3rdparty/pybind11/include/pybind11/functional.h
index 92c17dc225..4034990d89 100644
--- a/3rdparty/pybind11/include/pybind11/functional.h
+++ b/3rdparty/pybind11/include/pybind11/functional.h
@@ -10,6 +10,7 @@
 #pragma once
 
 #include "pybind11.h"
+
 #include <functional>
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
@@ -19,18 +20,21 @@ template <typename Return, typename... Args>
 struct type_caster<std::function<Return(Args...)>> {
     using type = std::function<Return(Args...)>;
     using retval_type = conditional_t<std::is_same<Return, void>::value, void_type, Return>;
-    using function_type = Return (*) (Args...);
+    using function_type = Return (*)(Args...);
 
 public:
     bool load(handle src, bool convert) {
         if (src.is_none()) {
             // Defer accepting None to other overloads (if we aren't in convert mode):
-            if (!convert) return false;
+            if (!convert) {
+                return false;
+            }
             return true;
         }
 
-        if (!isinstance<function>(src))
+        if (!isinstance<function>(src)) {
             return false;
+        }
 
         auto func = reinterpret_borrow<function>(src);
 
@@ -43,24 +47,44 @@ struct type_caster<std::function<Return(Args...)>> {
            captured variables), in which case the roundtrip can be avoided.
          */
         if (auto cfunc = func.cpp_function()) {
-            auto c = reinterpret_borrow<capsule>(PyCFunction_GET_SELF(cfunc.ptr()));
-            auto rec = (function_record *) c;
-
-            if (rec && rec->is_stateless &&
-                    same_type(typeid(function_type), *reinterpret_cast<const std::type_info *>(rec->data[1]))) {
-                struct capture { function_type f; };
-                value = ((capture *) &rec->data)->f;
-                return true;
+            auto *cfunc_self = PyCFunction_GET_SELF(cfunc.ptr());
+            if (isinstance<capsule>(cfunc_self)) {
+                auto c = reinterpret_borrow<capsule>(cfunc_self);
+                auto *rec = (function_record *) c;
+
+                while (rec != nullptr) {
+                    if (rec->is_stateless
+                        && same_type(typeid(function_type),
+                                     *reinterpret_cast<const std::type_info *>(rec->data[1]))) {
+                        struct capture {
+                            function_type f;
+                        };
+                        value = ((capture *) &rec->data)->f;
+                        return true;
+                    }
+                    rec = rec->next;
+                }
             }
+            // PYPY segfaults here when passing builtin function like sum.
+            // Raising an fail exception here works to prevent the segfault, but only on gcc.
+            // See PR #1413 for full details
         }
 
         // ensure GIL is held during functor destruction
         struct func_handle {
             function f;
-            func_handle(function&& f_) : f(std::move(f_)) {}
-            func_handle(const func_handle& f_) {
+#if !(defined(_MSC_VER) && _MSC_VER == 1916 && defined(PYBIND11_CPP17))
+            // This triggers a syntax error under very special conditions (very weird indeed).
+            explicit
+#endif
+                func_handle(function &&f_) noexcept
+                : f(std::move(f_)) {
+            }
+            func_handle(const func_handle &f_) { operator=(f_); }
+            func_handle &operator=(const func_handle &f_) {
                 gil_scoped_acquire acq;
                 f = f_.f;
+                return *this;
             }
             ~func_handle() {
                 gil_scoped_acquire acq;
@@ -71,12 +95,11 @@ struct type_caster<std::function<Return(Args...)>> {
         // to emulate 'move initialization capture' in C++11
         struct func_wrapper {
             func_handle hfunc;
-            func_wrapper(func_handle&& hf): hfunc(std::move(hf)) {}
+            explicit func_wrapper(func_handle &&hf) noexcept : hfunc(std::move(hf)) {}
             Return operator()(Args... args) const {
                 gil_scoped_acquire acq;
-                object retval(hfunc.f(std::forward<Args>(args)...));
-                /* Visual studio 2015 parser issue: need parentheses around this expression */
-                return (retval.template cast<Return>());
+                // casts the returned object as a rvalue to the return type
+                return hfunc.f(std::forward<Args>(args)...).template cast<Return>();
             }
         };
 
@@ -86,18 +109,21 @@ struct type_caster<std::function<Return(Args...)>> {
 
     template <typename Func>
     static handle cast(Func &&f_, return_value_policy policy, handle /* parent */) {
-        if (!f_)
+        if (!f_) {
             return none().inc_ref();
+        }
 
         auto result = f_.template target<function_type>();
-        if (result)
+        if (result) {
             return cpp_function(*result, policy).release();
-        else
-            return cpp_function(std::forward<Func>(f_), policy).release();
+        }
+        return cpp_function(std::forward<Func>(f_), policy).release();
     }
 
-    PYBIND11_TYPE_CASTER(type, _("Callable[[") + concat(make_caster<Args>::name...) + _("], ")
-                               + make_caster<retval_type>::name + _("]"));
+    PYBIND11_TYPE_CASTER(type,
+                         const_name("Callable[[") + concat(make_caster<Args>::name...)
+                             + const_name("], ") + make_caster<retval_type>::name
+                             + const_name("]"));
 };
 
 PYBIND11_NAMESPACE_END(detail)
diff --git a/3rdparty/pybind11/include/pybind11/gil.h b/3rdparty/pybind11/include/pybind11/gil.h
new file mode 100644
index 0000000000..a0b5de1514
--- /dev/null
+++ b/3rdparty/pybind11/include/pybind11/gil.h
@@ -0,0 +1,202 @@
+/*
+    pybind11/gil.h: RAII helpers for managing the GIL
+
+    Copyright (c) 2016 Wenzel Jakob <wenzel.jakob@epfl.ch>
+
+    All rights reserved. Use of this source code is governed by a
+    BSD-style license that can be found in the LICENSE file.
+*/
+
+#pragma once
+
+#include "detail/common.h"
+#include "detail/internals.h"
+
+PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
+
+PYBIND11_NAMESPACE_BEGIN(detail)
+
+// forward declarations
+PyThreadState *get_thread_state_unchecked();
+
+PYBIND11_NAMESPACE_END(detail)
+
+#if defined(WITH_THREAD) && !defined(PYPY_VERSION)
+
+/* The functions below essentially reproduce the PyGILState_* API using a RAII
+ * pattern, but there are a few important differences:
+ *
+ * 1. When acquiring the GIL from an non-main thread during the finalization
+ *    phase, the GILState API blindly terminates the calling thread, which
+ *    is often not what is wanted. This API does not do this.
+ *
+ * 2. The gil_scoped_release function can optionally cut the relationship
+ *    of a PyThreadState and its associated thread, which allows moving it to
+ *    another thread (this is a fairly rare/advanced use case).
+ *
+ * 3. The reference count of an acquired thread state can be controlled. This
+ *    can be handy to prevent cases where callbacks issued from an external
+ *    thread would otherwise constantly construct and destroy thread state data
+ *    structures.
+ *
+ * See the Python bindings of NanoGUI (http://github.com/wjakob/nanogui) for an
+ * example which uses features 2 and 3 to migrate the Python thread of
+ * execution to another thread (to run the event loop on the original thread,
+ * in this case).
+ */
+
+class gil_scoped_acquire {
+public:
+    PYBIND11_NOINLINE gil_scoped_acquire() {
+        auto &internals = detail::get_internals();
+        tstate = (PyThreadState *) PYBIND11_TLS_GET_VALUE(internals.tstate);
+
+        if (!tstate) {
+            /* Check if the GIL was acquired using the PyGILState_* API instead (e.g. if
+               calling from a Python thread). Since we use a different key, this ensures
+               we don't create a new thread state and deadlock in PyEval_AcquireThread
+               below. Note we don't save this state with internals.tstate, since we don't
+               create it we would fail to clear it (its reference count should be > 0). */
+            tstate = PyGILState_GetThisThreadState();
+        }
+
+        if (!tstate) {
+            tstate = PyThreadState_New(internals.istate);
+#    if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+            if (!tstate) {
+                pybind11_fail("scoped_acquire: could not create thread state!");
+            }
+#    endif
+            tstate->gilstate_counter = 0;
+            PYBIND11_TLS_REPLACE_VALUE(internals.tstate, tstate);
+        } else {
+            release = detail::get_thread_state_unchecked() != tstate;
+        }
+
+        if (release) {
+            PyEval_AcquireThread(tstate);
+        }
+
+        inc_ref();
+    }
+
+    void inc_ref() { ++tstate->gilstate_counter; }
+
+    PYBIND11_NOINLINE void dec_ref() {
+        --tstate->gilstate_counter;
+#    if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+        if (detail::get_thread_state_unchecked() != tstate) {
+            pybind11_fail("scoped_acquire::dec_ref(): thread state must be current!");
+        }
+        if (tstate->gilstate_counter < 0) {
+            pybind11_fail("scoped_acquire::dec_ref(): reference count underflow!");
+        }
+#    endif
+        if (tstate->gilstate_counter == 0) {
+#    if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+            if (!release) {
+                pybind11_fail("scoped_acquire::dec_ref(): internal error!");
+            }
+#    endif
+            PyThreadState_Clear(tstate);
+            if (active) {
+                PyThreadState_DeleteCurrent();
+            }
+            PYBIND11_TLS_DELETE_VALUE(detail::get_internals().tstate);
+            release = false;
+        }
+    }
+
+    /// This method will disable the PyThreadState_DeleteCurrent call and the
+    /// GIL won't be acquired. This method should be used if the interpreter
+    /// could be shutting down when this is called, as thread deletion is not
+    /// allowed during shutdown. Check _Py_IsFinalizing() on Python 3.7+, and
+    /// protect subsequent code.
+    PYBIND11_NOINLINE void disarm() { active = false; }
+
+    PYBIND11_NOINLINE ~gil_scoped_acquire() {
+        dec_ref();
+        if (release) {
+            PyEval_SaveThread();
+        }
+    }
+
+private:
+    PyThreadState *tstate = nullptr;
+    bool release = true;
+    bool active = true;
+};
+
+class gil_scoped_release {
+public:
+    explicit gil_scoped_release(bool disassoc = false) : disassoc(disassoc) {
+        // `get_internals()` must be called here unconditionally in order to initialize
+        // `internals.tstate` for subsequent `gil_scoped_acquire` calls. Otherwise, an
+        // initialization race could occur as multiple threads try `gil_scoped_acquire`.
+        auto &internals = detail::get_internals();
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        tstate = PyEval_SaveThread();
+        if (disassoc) {
+            // Python >= 3.7 can remove this, it's an int before 3.7
+            // NOLINTNEXTLINE(readability-qualified-auto)
+            auto key = internals.tstate;
+            PYBIND11_TLS_DELETE_VALUE(key);
+        }
+    }
+
+    /// This method will disable the PyThreadState_DeleteCurrent call and the
+    /// GIL won't be acquired. This method should be used if the interpreter
+    /// could be shutting down when this is called, as thread deletion is not
+    /// allowed during shutdown. Check _Py_IsFinalizing() on Python 3.7+, and
+    /// protect subsequent code.
+    PYBIND11_NOINLINE void disarm() { active = false; }
+
+    ~gil_scoped_release() {
+        if (!tstate) {
+            return;
+        }
+        // `PyEval_RestoreThread()` should not be called if runtime is finalizing
+        if (active) {
+            PyEval_RestoreThread(tstate);
+        }
+        if (disassoc) {
+            // Python >= 3.7 can remove this, it's an int before 3.7
+            // NOLINTNEXTLINE(readability-qualified-auto)
+            auto key = detail::get_internals().tstate;
+            PYBIND11_TLS_REPLACE_VALUE(key, tstate);
+        }
+    }
+
+private:
+    PyThreadState *tstate;
+    bool disassoc;
+    bool active = true;
+};
+#elif defined(PYPY_VERSION)
+class gil_scoped_acquire {
+    PyGILState_STATE state;
+
+public:
+    gil_scoped_acquire() { state = PyGILState_Ensure(); }
+    ~gil_scoped_acquire() { PyGILState_Release(state); }
+    void disarm() {}
+};
+
+class gil_scoped_release {
+    PyThreadState *state;
+
+public:
+    gil_scoped_release() { state = PyEval_SaveThread(); }
+    ~gil_scoped_release() { PyEval_RestoreThread(state); }
+    void disarm() {}
+};
+#else
+class gil_scoped_acquire {
+    void disarm() {}
+};
+class gil_scoped_release {
+    void disarm() {}
+};
+#endif
+
+PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/iostream.h b/3rdparty/pybind11/include/pybind11/iostream.h
index 5e9a8143d0..1878089e31 100644
--- a/3rdparty/pybind11/include/pybind11/iostream.h
+++ b/3rdparty/pybind11/include/pybind11/iostream.h
@@ -5,17 +5,31 @@
 
     All rights reserved. Use of this source code is governed by a
     BSD-style license that can be found in the LICENSE file.
+
+    WARNING: The implementation in this file is NOT thread safe. Multiple
+    threads writing to a redirected ostream concurrently cause data races
+    and potentially buffer overflows. Therefore it is currently a requirement
+    that all (possibly) concurrent redirected ostream writes are protected by
+    a mutex.
+    #HelpAppreciated: Work on iostream.h thread safety.
+    For more background see the discussions under
+    https://github.com/pybind/pybind11/pull/2982 and
+    https://github.com/pybind/pybind11/pull/2995.
 */
 
 #pragma once
 
 #include "pybind11.h"
 
-#include <streambuf>
+#include <algorithm>
+#include <cstring>
+#include <iostream>
+#include <iterator>
+#include <memory>
 #include <ostream>
+#include <streambuf>
 #include <string>
-#include <memory>
-#include <iostream>
+#include <utility>
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
@@ -38,50 +52,85 @@ class pythonbuf : public std::streambuf {
         return sync() == 0 ? traits_type::not_eof(c) : traits_type::eof();
     }
 
-    // This function must be non-virtual to be called in a destructor. If the
-    // rare MSVC test failure shows up with this version, then this should be
-    // simplified to a fully qualified call.
-    int _sync() {
-        if (pbase() != pptr()) {
-            // This subtraction cannot be negative, so dropping the sign
-            str line(pbase(), static_cast<size_t>(pptr() - pbase()));
+    // Computes how many bytes at the end of the buffer are part of an
+    // incomplete sequence of UTF-8 bytes.
+    // Precondition: pbase() < pptr()
+    size_t utf8_remainder() const {
+        const auto rbase = std::reverse_iterator<char *>(pbase());
+        const auto rpptr = std::reverse_iterator<char *>(pptr());
+        auto is_ascii = [](char c) { return (static_cast<unsigned char>(c) & 0x80) == 0x00; };
+        auto is_leading = [](char c) { return (static_cast<unsigned char>(c) & 0xC0) == 0xC0; };
+        auto is_leading_2b = [](char c) { return static_cast<unsigned char>(c) <= 0xDF; };
+        auto is_leading_3b = [](char c) { return static_cast<unsigned char>(c) <= 0xEF; };
+        // If the last character is ASCII, there are no incomplete code points
+        if (is_ascii(*rpptr)) {
+            return 0;
+        }
+        // Otherwise, work back from the end of the buffer and find the first
+        // UTF-8 leading byte
+        const auto rpend = rbase - rpptr >= 3 ? rpptr + 3 : rbase;
+        const auto leading = std::find_if(rpptr, rpend, is_leading);
+        if (leading == rbase) {
+            return 0;
+        }
+        const auto dist = static_cast<size_t>(leading - rpptr);
+        size_t remainder = 0;
+
+        if (dist == 0) {
+            remainder = 1; // 1-byte code point is impossible
+        } else if (dist == 1) {
+            remainder = is_leading_2b(*leading) ? 0 : dist + 1;
+        } else if (dist == 2) {
+            remainder = is_leading_3b(*leading) ? 0 : dist + 1;
+        }
+        // else if (dist >= 3), at least 4 bytes before encountering an UTF-8
+        // leading byte, either no remainder or invalid UTF-8.
+        // Invalid UTF-8 will cause an exception later when converting
+        // to a Python string, so that's not handled here.
+        return remainder;
+    }
 
-            {
-                gil_scoped_acquire tmp;
-                pywrite(line);
+    // This function must be non-virtual to be called in a destructor.
+    int _sync() {
+        if (pbase() != pptr()) { // If buffer is not empty
+            gil_scoped_acquire tmp;
+            // This subtraction cannot be negative, so dropping the sign.
+            auto size = static_cast<size_t>(pptr() - pbase());
+            size_t remainder = utf8_remainder();
+
+            if (size > remainder) {
+                str line(pbase(), size - remainder);
+                pywrite(std::move(line));
                 pyflush();
             }
 
+            // Copy the remainder at the end of the buffer to the beginning:
+            if (remainder > 0) {
+                std::memmove(pbase(), pptr() - remainder, remainder);
+            }
             setp(pbase(), epptr());
+            pbump(static_cast<int>(remainder));
         }
         return 0;
     }
 
-    int sync() override {
-        return _sync();
-    }
+    int sync() override { return _sync(); }
 
 public:
-
-    pythonbuf(object pyostream, size_t buffer_size = 1024)
-        : buf_size(buffer_size),
-          d_buffer(new char[buf_size]),
-          pywrite(pyostream.attr("write")),
+    explicit pythonbuf(const object &pyostream, size_t buffer_size = 1024)
+        : buf_size(buffer_size), d_buffer(new char[buf_size]), pywrite(pyostream.attr("write")),
           pyflush(pyostream.attr("flush")) {
         setp(d_buffer.get(), d_buffer.get() + buf_size - 1);
     }
 
-    pythonbuf(pythonbuf&&) = default;
+    pythonbuf(pythonbuf &&) = default;
 
     /// Sync before destroy
-    ~pythonbuf() override {
-        _sync();
-    }
+    ~pythonbuf() override { _sync(); }
 };
 
 PYBIND11_NAMESPACE_END(detail)
 
-
 /** \rst
     This a move-only guard that redirects output.
 
@@ -102,8 +151,9 @@ PYBIND11_NAMESPACE_END(detail)
     .. code-block:: cpp
 
         {
-            py::scoped_ostream_redirect output{std::cerr, py::module_::import("sys").attr("stderr")};
-            std::cerr << "Hello, World!";
+            py::scoped_ostream_redirect output{
+                std::cerr, py::module::import("sys").attr("stderr")};
+            std::cout << "Hello, World!";
         }
  \endrst */
 class scoped_ostream_redirect {
@@ -113,16 +163,14 @@ class scoped_ostream_redirect {
     detail::pythonbuf buffer;
 
 public:
-    scoped_ostream_redirect(
-            std::ostream &costream = std::cout,
-            object pyostream = module_::import("sys").attr("stdout"))
+    explicit scoped_ostream_redirect(std::ostream &costream = std::cout,
+                                     const object &pyostream
+                                     = module_::import("sys").attr("stdout"))
         : costream(costream), buffer(pyostream) {
         old = costream.rdbuf(&buffer);
     }
 
-    ~scoped_ostream_redirect() {
-        costream.rdbuf(old);
-    }
+    ~scoped_ostream_redirect() { costream.rdbuf(old); }
 
     scoped_ostream_redirect(const scoped_ostream_redirect &) = delete;
     scoped_ostream_redirect(scoped_ostream_redirect &&other) = default;
@@ -130,7 +178,6 @@ class scoped_ostream_redirect {
     scoped_ostream_redirect &operator=(scoped_ostream_redirect &&) = delete;
 };
 
-
 /** \rst
     Like `scoped_ostream_redirect`, but redirects cerr by default. This class
     is provided primary to make ``py::call_guard`` easier to make.
@@ -144,13 +191,12 @@ class scoped_ostream_redirect {
 \endrst */
 class scoped_estream_redirect : public scoped_ostream_redirect {
 public:
-    scoped_estream_redirect(
-            std::ostream &costream = std::cerr,
-            object pyostream = module_::import("sys").attr("stderr"))
-        : scoped_ostream_redirect(costream,pyostream) {}
+    explicit scoped_estream_redirect(std::ostream &costream = std::cerr,
+                                     const object &pyostream
+                                     = module_::import("sys").attr("stderr"))
+        : scoped_ostream_redirect(costream, pyostream) {}
 };
 
-
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 // Class to redirect output as a context manager. C++ backend.
@@ -161,14 +207,16 @@ class OstreamRedirect {
     std::unique_ptr<scoped_estream_redirect> redirect_stderr;
 
 public:
-    OstreamRedirect(bool do_stdout = true, bool do_stderr = true)
+    explicit OstreamRedirect(bool do_stdout = true, bool do_stderr = true)
         : do_stdout_(do_stdout), do_stderr_(do_stderr) {}
 
     void enter() {
-        if (do_stdout_)
+        if (do_stdout_) {
             redirect_stdout.reset(new scoped_ostream_redirect());
-        if (do_stderr_)
+        }
+        if (do_stderr_) {
             redirect_stderr.reset(new scoped_estream_redirect());
+        }
     }
 
     void exit() {
@@ -206,11 +254,12 @@ PYBIND11_NAMESPACE_END(detail)
             m.noisy_function_with_error_printing()
 
  \endrst */
-inline class_<detail::OstreamRedirect> add_ostream_redirect(module_ m, std::string name = "ostream_redirect") {
-    return class_<detail::OstreamRedirect>(m, name.c_str(), module_local())
-        .def(init<bool,bool>(), arg("stdout")=true, arg("stderr")=true)
+inline class_<detail::OstreamRedirect>
+add_ostream_redirect(module_ m, const std::string &name = "ostream_redirect") {
+    return class_<detail::OstreamRedirect>(std::move(m), name.c_str(), module_local())
+        .def(init<bool, bool>(), arg("stdout") = true, arg("stderr") = true)
         .def("__enter__", &detail::OstreamRedirect::enter)
-        .def("__exit__", [](detail::OstreamRedirect &self_, args) { self_.exit(); });
+        .def("__exit__", [](detail::OstreamRedirect &self_, const args &) { self_.exit(); });
 }
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/numpy.h b/3rdparty/pybind11/include/pybind11/numpy.h
index 019f5688e7..369e18649b 100644
--- a/3rdparty/pybind11/include/pybind11/numpy.h
+++ b/3rdparty/pybind11/include/pybind11/numpy.h
@@ -11,24 +11,20 @@
 
 #include "pybind11.h"
 #include "complex.h"
-#include <numeric>
+
 #include <algorithm>
 #include <array>
 #include <cstdint>
 #include <cstdlib>
 #include <cstring>
+#include <functional>
+#include <numeric>
 #include <sstream>
 #include <string>
-#include <functional>
 #include <type_traits>
+#include <typeindex>
 #include <utility>
 #include <vector>
-#include <typeindex>
-
-#if defined(_MSC_VER)
-#  pragma warning(push)
-#  pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#endif
 
 /* This will be true on all flat address space platforms and allows us to reduce the
    whole npy_intp / ssize_t / Py_intptr_t business down to just ssize_t for all size
@@ -44,9 +40,13 @@ class array; // Forward declaration
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-template <> struct handle_type_name<array> { static constexpr auto name = _("numpy.ndarray"); };
+template <>
+struct handle_type_name<array> {
+    static constexpr auto name = const_name("numpy.ndarray");
+};
 
-template <typename type, typename SFINAE = void> struct npy_format_descriptor;
+template <typename type, typename SFINAE = void>
+struct npy_format_descriptor;
 
 struct PyArrayDescr_Proxy {
     PyObject_HEAD
@@ -75,51 +75,59 @@ struct PyArray_Proxy {
 };
 
 struct PyVoidScalarObject_Proxy {
-    PyObject_VAR_HEAD
-    char *obval;
+    PyObject_VAR_HEAD char *obval;
     PyArrayDescr_Proxy *descr;
     int flags;
     PyObject *base;
 };
 
 struct numpy_type_info {
-    PyObject* dtype_ptr;
+    PyObject *dtype_ptr;
     std::string format_str;
 };
 
 struct numpy_internals {
     std::unordered_map<std::type_index, numpy_type_info> registered_dtypes;
 
-    numpy_type_info *get_type_info(const std::type_info& tinfo, bool throw_if_missing = true) {
+    numpy_type_info *get_type_info(const std::type_info &tinfo, bool throw_if_missing = true) {
         auto it = registered_dtypes.find(std::type_index(tinfo));
-        if (it != registered_dtypes.end())
+        if (it != registered_dtypes.end()) {
             return &(it->second);
-        if (throw_if_missing)
+        }
+        if (throw_if_missing) {
             pybind11_fail(std::string("NumPy type info missing for ") + tinfo.name());
+        }
         return nullptr;
     }
 
-    template<typename T> numpy_type_info *get_type_info(bool throw_if_missing = true) {
+    template <typename T>
+    numpy_type_info *get_type_info(bool throw_if_missing = true) {
         return get_type_info(typeid(typename std::remove_cv<T>::type), throw_if_missing);
     }
 };
 
-inline PYBIND11_NOINLINE void load_numpy_internals(numpy_internals* &ptr) {
+PYBIND11_NOINLINE void load_numpy_internals(numpy_internals *&ptr) {
     ptr = &get_or_create_shared_data<numpy_internals>("_numpy_internals");
 }
 
-inline numpy_internals& get_numpy_internals() {
-    static numpy_internals* ptr = nullptr;
-    if (!ptr)
+inline numpy_internals &get_numpy_internals() {
+    static numpy_internals *ptr = nullptr;
+    if (!ptr) {
         load_numpy_internals(ptr);
+    }
     return *ptr;
 }
 
-template <typename T> struct same_size {
-    template <typename U> using as = bool_constant<sizeof(T) == sizeof(U)>;
+template <typename T>
+struct same_size {
+    template <typename U>
+    using as = bool_constant<sizeof(T) == sizeof(U)>;
 };
 
-template <typename Concrete> constexpr int platform_lookup() { return -1; }
+template <typename Concrete>
+constexpr int platform_lookup() {
+    return -1;
+}
 
 // Lookup a type according to its size, and return a value corresponding to the NumPy typenum.
 template <typename Concrete, typename T, typename... Ts, typename... Ints>
@@ -137,15 +145,26 @@ struct npy_api {
         NPY_ARRAY_ALIGNED_ = 0x0100,
         NPY_ARRAY_WRITEABLE_ = 0x0400,
         NPY_BOOL_ = 0,
-        NPY_BYTE_, NPY_UBYTE_,
-        NPY_SHORT_, NPY_USHORT_,
-        NPY_INT_, NPY_UINT_,
-        NPY_LONG_, NPY_ULONG_,
-        NPY_LONGLONG_, NPY_ULONGLONG_,
-        NPY_FLOAT_, NPY_DOUBLE_, NPY_LONGDOUBLE_,
-        NPY_CFLOAT_, NPY_CDOUBLE_, NPY_CLONGDOUBLE_,
+        NPY_BYTE_,
+        NPY_UBYTE_,
+        NPY_SHORT_,
+        NPY_USHORT_,
+        NPY_INT_,
+        NPY_UINT_,
+        NPY_LONG_,
+        NPY_ULONG_,
+        NPY_LONGLONG_,
+        NPY_ULONGLONG_,
+        NPY_FLOAT_,
+        NPY_DOUBLE_,
+        NPY_LONGDOUBLE_,
+        NPY_CFLOAT_,
+        NPY_CDOUBLE_,
+        NPY_CLONGDOUBLE_,
         NPY_OBJECT_ = 17,
-        NPY_STRING_, NPY_UNICODE_, NPY_VOID_,
+        NPY_STRING_,
+        NPY_UNICODE_,
+        NPY_VOID_,
         // Platform-dependent normalization
         NPY_INT8_ = NPY_BYTE_,
         NPY_UINT8_ = NPY_UBYTE_,
@@ -154,38 +173,44 @@ struct npy_api {
         // `npy_common.h` defines the integer aliases. In order, it checks:
         // NPY_BITSOF_LONG, NPY_BITSOF_LONGLONG, NPY_BITSOF_INT, NPY_BITSOF_SHORT, NPY_BITSOF_CHAR
         // and assigns the alias to the first matching size, so we should check in this order.
-        NPY_INT32_ = platform_lookup<std::int32_t, long, int, short>(
-            NPY_LONG_, NPY_INT_, NPY_SHORT_),
+        NPY_INT32_
+        = platform_lookup<std::int32_t, long, int, short>(NPY_LONG_, NPY_INT_, NPY_SHORT_),
         NPY_UINT32_ = platform_lookup<std::uint32_t, unsigned long, unsigned int, unsigned short>(
             NPY_ULONG_, NPY_UINT_, NPY_USHORT_),
-        NPY_INT64_ = platform_lookup<std::int64_t, long, long long, int>(
-            NPY_LONG_, NPY_LONGLONG_, NPY_INT_),
-        NPY_UINT64_ = platform_lookup<std::uint64_t, unsigned long, unsigned long long, unsigned int>(
+        NPY_INT64_
+        = platform_lookup<std::int64_t, long, long long, int>(NPY_LONG_, NPY_LONGLONG_, NPY_INT_),
+        NPY_UINT64_
+        = platform_lookup<std::uint64_t, unsigned long, unsigned long long, unsigned int>(
             NPY_ULONG_, NPY_ULONGLONG_, NPY_UINT_),
     };
 
-    typedef struct {
+    struct PyArray_Dims {
         Py_intptr_t *ptr;
         int len;
-    } PyArray_Dims;
+    };
 
-    static npy_api& get() {
+    static npy_api &get() {
         static npy_api api = lookup();
         return api;
     }
 
     bool PyArray_Check_(PyObject *obj) const {
-        return (bool) PyObject_TypeCheck(obj, PyArray_Type_);
+        return PyObject_TypeCheck(obj, PyArray_Type_) != 0;
     }
     bool PyArrayDescr_Check_(PyObject *obj) const {
-        return (bool) PyObject_TypeCheck(obj, PyArrayDescr_Type_);
+        return PyObject_TypeCheck(obj, PyArrayDescr_Type_) != 0;
     }
 
     unsigned int (*PyArray_GetNDArrayCFeatureVersion_)();
     PyObject *(*PyArray_DescrFromType_)(int);
-    PyObject *(*PyArray_NewFromDescr_)
-        (PyTypeObject *, PyObject *, int, Py_intptr_t const *,
-         Py_intptr_t const *, void *, int, PyObject *);
+    PyObject *(*PyArray_NewFromDescr_)(PyTypeObject *,
+                                       PyObject *,
+                                       int,
+                                       Py_intptr_t const *,
+                                       Py_intptr_t const *,
+                                       void *,
+                                       int,
+                                       PyObject *);
     // Unused. Not removed because that affects ABI of the class.
     PyObject *(*PyArray_DescrNewFromType_)(int);
     int (*PyArray_CopyInto_)(PyObject *, PyObject *);
@@ -194,15 +219,24 @@ struct npy_api {
     PyTypeObject *PyVoidArrType_Type_;
     PyTypeObject *PyArrayDescr_Type_;
     PyObject *(*PyArray_DescrFromScalar_)(PyObject *);
-    PyObject *(*PyArray_FromAny_) (PyObject *, PyObject *, int, int, int, PyObject *);
-    int (*PyArray_DescrConverter_) (PyObject *, PyObject **);
-    bool (*PyArray_EquivTypes_) (PyObject *, PyObject *);
-    int (*PyArray_GetArrayParamsFromObject_)(PyObject *, PyObject *, unsigned char, PyObject **, int *,
-                                             Py_intptr_t *, PyObject **, PyObject *);
+    PyObject *(*PyArray_FromAny_)(PyObject *, PyObject *, int, int, int, PyObject *);
+    int (*PyArray_DescrConverter_)(PyObject *, PyObject **);
+    bool (*PyArray_EquivTypes_)(PyObject *, PyObject *);
+    int (*PyArray_GetArrayParamsFromObject_)(PyObject *,
+                                             PyObject *,
+                                             unsigned char,
+                                             PyObject **,
+                                             int *,
+                                             Py_intptr_t *,
+                                             PyObject **,
+                                             PyObject *);
     PyObject *(*PyArray_Squeeze_)(PyObject *);
     // Unused. Not removed because that affects ABI of the class.
     int (*PyArray_SetBaseObject_)(PyObject *, PyObject *);
-    PyObject* (*PyArray_Resize_)(PyObject*, PyArray_Dims*, int, int);
+    PyObject *(*PyArray_Resize_)(PyObject *, PyArray_Dims *, int, int);
+    PyObject *(*PyArray_Newshape_)(PyObject *, PyArray_Dims *, int);
+    PyObject *(*PyArray_View_)(PyObject *, PyObject *, PyObject *);
+
 private:
     enum functions {
         API_PyArray_GetNDArrayCFeatureVersion = 211,
@@ -217,26 +251,25 @@ struct npy_api {
         API_PyArray_NewCopy = 85,
         API_PyArray_NewFromDescr = 94,
         API_PyArray_DescrNewFromType = 96,
+        API_PyArray_Newshape = 135,
+        API_PyArray_Squeeze = 136,
+        API_PyArray_View = 137,
         API_PyArray_DescrConverter = 174,
         API_PyArray_EquivTypes = 182,
         API_PyArray_GetArrayParamsFromObject = 278,
-        API_PyArray_Squeeze = 136,
         API_PyArray_SetBaseObject = 282
     };
 
     static npy_api lookup() {
         module_ m = module_::import("numpy.core.multiarray");
         auto c = m.attr("_ARRAY_API");
-#if PY_MAJOR_VERSION >= 3
-        void **api_ptr = (void **) PyCapsule_GetPointer(c.ptr(), NULL);
-#else
-        void **api_ptr = (void **) PyCObject_AsVoidPtr(c.ptr());
-#endif
+        void **api_ptr = (void **) PyCapsule_GetPointer(c.ptr(), nullptr);
         npy_api api;
 #define DECL_NPY_API(Func) api.Func##_ = (decltype(api.Func##_)) api_ptr[API_##Func];
         DECL_NPY_API(PyArray_GetNDArrayCFeatureVersion);
-        if (api.PyArray_GetNDArrayCFeatureVersion_() < 0x7)
+        if (api.PyArray_GetNDArrayCFeatureVersion_() < 0x7) {
             pybind11_fail("pybind11 numpy support requires numpy >= 1.7.0");
+        }
         DECL_NPY_API(PyArray_Type);
         DECL_NPY_API(PyVoidArrType_Type);
         DECL_NPY_API(PyArrayDescr_Type);
@@ -248,96 +281,116 @@ struct npy_api {
         DECL_NPY_API(PyArray_NewCopy);
         DECL_NPY_API(PyArray_NewFromDescr);
         DECL_NPY_API(PyArray_DescrNewFromType);
+        DECL_NPY_API(PyArray_Newshape);
+        DECL_NPY_API(PyArray_Squeeze);
+        DECL_NPY_API(PyArray_View);
         DECL_NPY_API(PyArray_DescrConverter);
         DECL_NPY_API(PyArray_EquivTypes);
         DECL_NPY_API(PyArray_GetArrayParamsFromObject);
-        DECL_NPY_API(PyArray_Squeeze);
         DECL_NPY_API(PyArray_SetBaseObject);
+
 #undef DECL_NPY_API
         return api;
     }
 };
 
-inline PyArray_Proxy* array_proxy(void* ptr) {
-    return reinterpret_cast<PyArray_Proxy*>(ptr);
-}
+inline PyArray_Proxy *array_proxy(void *ptr) { return reinterpret_cast<PyArray_Proxy *>(ptr); }
 
-inline const PyArray_Proxy* array_proxy(const void* ptr) {
-    return reinterpret_cast<const PyArray_Proxy*>(ptr);
+inline const PyArray_Proxy *array_proxy(const void *ptr) {
+    return reinterpret_cast<const PyArray_Proxy *>(ptr);
 }
 
-inline PyArrayDescr_Proxy* array_descriptor_proxy(PyObject* ptr) {
-   return reinterpret_cast<PyArrayDescr_Proxy*>(ptr);
+inline PyArrayDescr_Proxy *array_descriptor_proxy(PyObject *ptr) {
+    return reinterpret_cast<PyArrayDescr_Proxy *>(ptr);
 }
 
-inline const PyArrayDescr_Proxy* array_descriptor_proxy(const PyObject* ptr) {
-   return reinterpret_cast<const PyArrayDescr_Proxy*>(ptr);
+inline const PyArrayDescr_Proxy *array_descriptor_proxy(const PyObject *ptr) {
+    return reinterpret_cast<const PyArrayDescr_Proxy *>(ptr);
 }
 
-inline bool check_flags(const void* ptr, int flag) {
+inline bool check_flags(const void *ptr, int flag) {
     return (flag == (array_proxy(ptr)->flags & flag));
 }
 
-template <typename T> struct is_std_array : std::false_type { };
-template <typename T, size_t N> struct is_std_array<std::array<T, N>> : std::true_type { };
-template <typename T> struct is_complex : std::false_type { };
-template <typename T> struct is_complex<std::complex<T>> : std::true_type { };
+template <typename T>
+struct is_std_array : std::false_type {};
+template <typename T, size_t N>
+struct is_std_array<std::array<T, N>> : std::true_type {};
+template <typename T>
+struct is_complex : std::false_type {};
+template <typename T>
+struct is_complex<std::complex<T>> : std::true_type {};
 
-template <typename T> struct array_info_scalar {
+template <typename T>
+struct array_info_scalar {
     using type = T;
     static constexpr bool is_array = false;
     static constexpr bool is_empty = false;
-    static constexpr auto extents = _("");
-    static void append_extents(list& /* shape */) { }
+    static constexpr auto extents = const_name("");
+    static void append_extents(list & /* shape */) {}
 };
 // Computes underlying type and a comma-separated list of extents for array
 // types (any mix of std::array and built-in arrays). An array of char is
 // treated as scalar because it gets special handling.
-template <typename T> struct array_info : array_info_scalar<T> { };
-template <typename T, size_t N> struct array_info<std::array<T, N>> {
+template <typename T>
+struct array_info : array_info_scalar<T> {};
+template <typename T, size_t N>
+struct array_info<std::array<T, N>> {
     using type = typename array_info<T>::type;
     static constexpr bool is_array = true;
     static constexpr bool is_empty = (N == 0) || array_info<T>::is_empty;
     static constexpr size_t extent = N;
 
     // appends the extents to shape
-    static void append_extents(list& shape) {
+    static void append_extents(list &shape) {
         shape.append(N);
         array_info<T>::append_extents(shape);
     }
 
-    static constexpr auto extents = _<array_info<T>::is_array>(
-        concat(_<N>(), array_info<T>::extents), _<N>()
-    );
+    static constexpr auto extents = const_name<array_info<T>::is_array>(
+        concat(const_name<N>(), array_info<T>::extents), const_name<N>());
 };
 // For numpy we have special handling for arrays of characters, so we don't include
 // the size in the array extents.
-template <size_t N> struct array_info<char[N]> : array_info_scalar<char[N]> { };
-template <size_t N> struct array_info<std::array<char, N>> : array_info_scalar<std::array<char, N>> { };
-template <typename T, size_t N> struct array_info<T[N]> : array_info<std::array<T, N>> { };
-template <typename T> using remove_all_extents_t = typename array_info<T>::type;
-
-template <typename T> using is_pod_struct = all_of<
-    std::is_standard_layout<T>,     // since we're accessing directly in memory we need a standard layout type
-#if !defined(__GNUG__) || defined(_LIBCPP_VERSION) || defined(_GLIBCXX_USE_CXX11_ABI)
-    // _GLIBCXX_USE_CXX11_ABI indicates that we're using libstdc++ from GCC 5 or newer, independent
-    // of the actual compiler (Clang can also use libstdc++, but it always defines __GNUC__ == 4).
-    std::is_trivially_copyable<T>,
+template <size_t N>
+struct array_info<char[N]> : array_info_scalar<char[N]> {};
+template <size_t N>
+struct array_info<std::array<char, N>> : array_info_scalar<std::array<char, N>> {};
+template <typename T, size_t N>
+struct array_info<T[N]> : array_info<std::array<T, N>> {};
+template <typename T>
+using remove_all_extents_t = typename array_info<T>::type;
+
+template <typename T>
+using is_pod_struct
+    = all_of<std::is_standard_layout<T>, // since we're accessing directly in memory
+                                         // we need a standard layout type
+#if defined(__GLIBCXX__)                                                                          \
+    && (__GLIBCXX__ < 20150422 || __GLIBCXX__ == 20150426 || __GLIBCXX__ == 20150623              \
+        || __GLIBCXX__ == 20150626 || __GLIBCXX__ == 20160803)
+             // libstdc++ < 5 (including versions 4.8.5, 4.9.3 and 4.9.4 which were released after
+             // 5) don't implement is_trivially_copyable, so approximate it
+             std::is_trivially_destructible<T>,
+             satisfies_any_of<T, std::has_trivial_copy_constructor, std::has_trivial_copy_assign>,
 #else
-    // GCC 4 doesn't implement is_trivially_copyable, so approximate it
-    std::is_trivially_destructible<T>,
-    satisfies_any_of<T, std::has_trivial_copy_constructor, std::has_trivial_copy_assign>,
+             std::is_trivially_copyable<T>,
 #endif
-    satisfies_none_of<T, std::is_reference, std::is_array, is_std_array, std::is_arithmetic, is_complex, std::is_enum>
->;
+             satisfies_none_of<T,
+                               std::is_reference,
+                               std::is_array,
+                               is_std_array,
+                               std::is_arithmetic,
+                               is_complex,
+                               std::is_enum>>;
 
 // Replacement for std::is_pod (deprecated in C++20)
-template <typename T> using is_pod = all_of<
-    std::is_standard_layout<T>,
-    std::is_trivial<T>
->;
+template <typename T>
+using is_pod = all_of<std::is_standard_layout<T>, std::is_trivial<T>>;
 
-template <ssize_t Dim = 0, typename Strides> ssize_t byte_offset_unsafe(const Strides &) { return 0; }
+template <ssize_t Dim = 0, typename Strides>
+ssize_t byte_offset_unsafe(const Strides &) {
+    return 0;
+}
 template <ssize_t Dim = 0, typename Strides, typename... Ix>
 ssize_t byte_offset_unsafe(const Strides &strides, ssize_t i, Ix... index) {
     return i * strides[Dim] + byte_offset_unsafe<Dim + 1>(strides, index...);
@@ -345,7 +398,7 @@ ssize_t byte_offset_unsafe(const Strides &strides, ssize_t i, Ix... index) {
 
 /**
  * Proxy class providing unsafe, unchecked const access to array data.  This is constructed through
- * the `unchecked<T, N>()` method of `array` or the `unchecked<N>()` method of `array_t<T>`.  `Dims`
+ * the `unchecked<T, N>()` method of `array` or the `unchecked<N>()` method of `array_t<T>`. `Dims`
  * will be -1 for dimensions determined at runtime.
  */
 template <typename T, ssize_t Dims>
@@ -355,15 +408,17 @@ class unchecked_reference {
     const unsigned char *data_;
     // Storing the shape & strides in local variables (i.e. these arrays) allows the compiler to
     // make large performance gains on big, nested loops, but requires compile-time dimensions
-    conditional_t<Dynamic, const ssize_t *, std::array<ssize_t, (size_t) Dims>>
-            shape_, strides_;
+    conditional_t<Dynamic, const ssize_t *, std::array<ssize_t, (size_t) Dims>> shape_, strides_;
     const ssize_t dims_;
 
     friend class pybind11::array;
     // Constructor for compile-time dimensions:
     template <bool Dyn = Dynamic>
-    unchecked_reference(const void *data, const ssize_t *shape, const ssize_t *strides, enable_if_t<!Dyn, ssize_t>)
-    : data_{reinterpret_cast<const unsigned char *>(data)}, dims_{Dims} {
+    unchecked_reference(const void *data,
+                        const ssize_t *shape,
+                        const ssize_t *strides,
+                        enable_if_t<!Dyn, ssize_t>)
+        : data_{reinterpret_cast<const unsigned char *>(data)}, dims_{Dims} {
         for (size_t i = 0; i < (size_t) dims_; i++) {
             shape_[i] = shape[i];
             strides_[i] = strides[i];
@@ -371,8 +426,12 @@ class unchecked_reference {
     }
     // Constructor for runtime dimensions:
     template <bool Dyn = Dynamic>
-    unchecked_reference(const void *data, const ssize_t *shape, const ssize_t *strides, enable_if_t<Dyn, ssize_t> dims)
-    : data_{reinterpret_cast<const unsigned char *>(data)}, shape_{shape}, strides_{strides}, dims_{dims} {}
+    unchecked_reference(const void *data,
+                        const ssize_t *shape,
+                        const ssize_t *strides,
+                        enable_if_t<Dyn, ssize_t> dims)
+        : data_{reinterpret_cast<const unsigned char *>(data)}, shape_{shape}, strides_{strides},
+          dims_{dims} {}
 
 public:
     /**
@@ -380,20 +439,27 @@ class unchecked_reference {
      * number of dimensions, this requires the correct number of arguments; for run-time
      * dimensionality, this is not checked (and so is up to the caller to use safely).
      */
-    template <typename... Ix> const T &operator()(Ix... index) const {
+    template <typename... Ix>
+    const T &operator()(Ix... index) const {
         static_assert(ssize_t{sizeof...(Ix)} == Dims || Dynamic,
-                "Invalid number of indices for unchecked array reference");
-        return *reinterpret_cast<const T *>(data_ + byte_offset_unsafe(strides_, ssize_t(index)...));
+                      "Invalid number of indices for unchecked array reference");
+        return *reinterpret_cast<const T *>(data_
+                                            + byte_offset_unsafe(strides_, ssize_t(index)...));
     }
     /**
      * Unchecked const reference access to data; this operator only participates if the reference
      * is to a 1-dimensional array.  When present, this is exactly equivalent to `obj(index)`.
      */
     template <ssize_t D = Dims, typename = enable_if_t<D == 1 || Dynamic>>
-    const T &operator[](ssize_t index) const { return operator()(index); }
+    const T &operator[](ssize_t index) const {
+        return operator()(index);
+    }
 
     /// Pointer access to the data at the given indices.
-    template <typename... Ix> const T *data(Ix... ix) const { return &operator()(ssize_t(ix)...); }
+    template <typename... Ix>
+    const T *data(Ix... ix) const {
+        return &operator()(ssize_t(ix)...);
+    }
 
     /// Returns the item size, i.e. sizeof(T)
     constexpr static ssize_t itemsize() { return sizeof(T); }
@@ -404,21 +470,22 @@ class unchecked_reference {
     /// Returns the number of dimensions of the array
     ssize_t ndim() const { return dims_; }
 
-    /// Returns the total number of elements in the referenced array, i.e. the product of the shapes
+    /// Returns the total number of elements in the referenced array, i.e. the product of the
+    /// shapes
     template <bool Dyn = Dynamic>
     enable_if_t<!Dyn, ssize_t> size() const {
-        return std::accumulate(shape_.begin(), shape_.end(), (ssize_t) 1, std::multiplies<ssize_t>());
+        return std::accumulate(
+            shape_.begin(), shape_.end(), (ssize_t) 1, std::multiplies<ssize_t>());
     }
     template <bool Dyn = Dynamic>
     enable_if_t<Dyn, ssize_t> size() const {
         return std::accumulate(shape_, shape_ + ndim(), (ssize_t) 1, std::multiplies<ssize_t>());
     }
 
-    /// Returns the total number of bytes used by the referenced data.  Note that the actual span in
-    /// memory may be larger if the referenced array has non-contiguous strides (e.g. for a slice).
-    ssize_t nbytes() const {
-        return size() * itemsize();
-    }
+    /// Returns the total number of bytes used by the referenced data.  Note that the actual span
+    /// in memory may be larger if the referenced array has non-contiguous strides (e.g. for a
+    /// slice).
+    ssize_t nbytes() const { return size() * itemsize(); }
 };
 
 template <typename T, ssize_t Dims>
@@ -427,15 +494,17 @@ class unchecked_mutable_reference : public unchecked_reference<T, Dims> {
     using ConstBase = unchecked_reference<T, Dims>;
     using ConstBase::ConstBase;
     using ConstBase::Dynamic;
+
 public:
     // Bring in const-qualified versions from base class
     using ConstBase::operator();
     using ConstBase::operator[];
 
     /// Mutable, unchecked access to data at the given indices.
-    template <typename... Ix> T& operator()(Ix... index) {
+    template <typename... Ix>
+    T &operator()(Ix... index) {
         static_assert(ssize_t{sizeof...(Ix)} == Dims || Dynamic,
-                "Invalid number of indices for unchecked array reference");
+                      "Invalid number of indices for unchecked array reference");
         return const_cast<T &>(ConstBase::operator()(index...));
     }
     /**
@@ -444,112 +513,167 @@ class unchecked_mutable_reference : public unchecked_reference<T, Dims> {
      * exactly equivalent to `obj(index)`.
      */
     template <ssize_t D = Dims, typename = enable_if_t<D == 1 || Dynamic>>
-    T &operator[](ssize_t index) { return operator()(index); }
+    T &operator[](ssize_t index) {
+        return operator()(index);
+    }
 
     /// Mutable pointer access to the data at the given indices.
-    template <typename... Ix> T *mutable_data(Ix... ix) { return &operator()(ssize_t(ix)...); }
+    template <typename... Ix>
+    T *mutable_data(Ix... ix) {
+        return &operator()(ssize_t(ix)...);
+    }
 };
 
 template <typename T, ssize_t Dim>
 struct type_caster<unchecked_reference<T, Dim>> {
-    static_assert(Dim == 0 && Dim > 0 /* always fail */, "unchecked array proxy object is not castable");
+    static_assert(Dim == 0 && Dim > 0 /* always fail */,
+                  "unchecked array proxy object is not castable");
 };
 template <typename T, ssize_t Dim>
-struct type_caster<unchecked_mutable_reference<T, Dim>> : type_caster<unchecked_reference<T, Dim>> {};
+struct type_caster<unchecked_mutable_reference<T, Dim>>
+    : type_caster<unchecked_reference<T, Dim>> {};
 
 PYBIND11_NAMESPACE_END(detail)
 
 class dtype : public object {
 public:
-    PYBIND11_OBJECT_DEFAULT(dtype, object, detail::npy_api::get().PyArrayDescr_Check_);
+    PYBIND11_OBJECT_DEFAULT(dtype, object, detail::npy_api::get().PyArrayDescr_Check_)
 
     explicit dtype(const buffer_info &info) {
-        dtype descr(_dtype_from_pep3118()(PYBIND11_STR_TYPE(info.format)));
+        dtype descr(_dtype_from_pep3118()(pybind11::str(info.format)));
         // If info.itemsize == 0, use the value calculated from the format string
-        m_ptr = descr.strip_padding(info.itemsize ? info.itemsize : descr.itemsize()).release().ptr();
+        m_ptr = descr.strip_padding(info.itemsize != 0 ? info.itemsize : descr.itemsize())
+                    .release()
+                    .ptr();
     }
 
-    explicit dtype(const std::string &format) {
-        m_ptr = from_args(pybind11::str(format)).release().ptr();
-    }
+    explicit dtype(const pybind11::str &format) : dtype(from_args(format)) {}
+
+    explicit dtype(const std::string &format) : dtype(pybind11::str(format)) {}
 
-    dtype(const char *format) : dtype(std::string(format)) { }
+    explicit dtype(const char *format) : dtype(pybind11::str(format)) {}
 
     dtype(list names, list formats, list offsets, ssize_t itemsize) {
         dict args;
-        args["names"] = names;
-        args["formats"] = formats;
-        args["offsets"] = offsets;
+        args["names"] = std::move(names);
+        args["formats"] = std::move(formats);
+        args["offsets"] = std::move(offsets);
         args["itemsize"] = pybind11::int_(itemsize);
         m_ptr = from_args(args).release().ptr();
     }
 
+    explicit dtype(int typenum)
+        : object(detail::npy_api::get().PyArray_DescrFromType_(typenum), stolen_t{}) {
+        if (m_ptr == nullptr) {
+            throw error_already_set();
+        }
+    }
+
     /// This is essentially the same as calling numpy.dtype(args) in Python.
-    static dtype from_args(object args) {
+    static dtype from_args(const object &args) {
         PyObject *ptr = nullptr;
-        if (!detail::npy_api::get().PyArray_DescrConverter_(args.ptr(), &ptr) || !ptr)
+        if ((detail::npy_api::get().PyArray_DescrConverter_(args.ptr(), &ptr) == 0) || !ptr) {
             throw error_already_set();
+        }
         return reinterpret_steal<dtype>(ptr);
     }
 
     /// Return dtype associated with a C++ type.
-    template <typename T> static dtype of() {
+    template <typename T>
+    static dtype of() {
         return detail::npy_format_descriptor<typename std::remove_cv<T>::type>::dtype();
     }
 
     /// Size of the data type in bytes.
-    ssize_t itemsize() const {
-        return detail::array_descriptor_proxy(m_ptr)->elsize;
-    }
+    ssize_t itemsize() const { return detail::array_descriptor_proxy(m_ptr)->elsize; }
 
     /// Returns true for structured data types.
-    bool has_fields() const {
-        return detail::array_descriptor_proxy(m_ptr)->names != nullptr;
+    bool has_fields() const { return detail::array_descriptor_proxy(m_ptr)->names != nullptr; }
+
+    /// Single-character code for dtype's kind.
+    /// For example, floating point types are 'f' and integral types are 'i'.
+    char kind() const { return detail::array_descriptor_proxy(m_ptr)->kind; }
+
+    /// Single-character for dtype's type.
+    /// For example, ``float`` is 'f', ``double`` 'd', ``int`` 'i', and ``long`` 'l'.
+    char char_() const {
+        // Note: The signature, `dtype::char_` follows the naming of NumPy's
+        // public Python API (i.e., ``dtype.char``), rather than its internal
+        // C API (``PyArray_Descr::type``).
+        return detail::array_descriptor_proxy(m_ptr)->type;
     }
 
-    /// Single-character type code.
-    char kind() const {
-        return detail::array_descriptor_proxy(m_ptr)->kind;
+    /// type number of dtype.
+    int num() const {
+        // Note: The signature, `dtype::num` follows the naming of NumPy's public
+        // Python API (i.e., ``dtype.num``), rather than its internal
+        // C API (``PyArray_Descr::type_num``).
+        return detail::array_descriptor_proxy(m_ptr)->type_num;
     }
 
+    /// Single character for byteorder
+    char byteorder() const { return detail::array_descriptor_proxy(m_ptr)->byteorder; }
+
+    /// Alignment of the data type
+    int alignment() const { return detail::array_descriptor_proxy(m_ptr)->alignment; }
+
+    /// Flags for the array descriptor
+    char flags() const { return detail::array_descriptor_proxy(m_ptr)->flags; }
+
 private:
     static object _dtype_from_pep3118() {
         static PyObject *obj = module_::import("numpy.core._internal")
-            .attr("_dtype_from_pep3118").cast<object>().release().ptr();
+                                   .attr("_dtype_from_pep3118")
+                                   .cast<object>()
+                                   .release()
+                                   .ptr();
         return reinterpret_borrow<object>(obj);
     }
 
     dtype strip_padding(ssize_t itemsize) {
         // Recursively strip all void fields with empty names that are generated for
         // padding fields (as of NumPy v1.11).
-        if (!has_fields())
+        if (!has_fields()) {
             return *this;
+        }
 
-        struct field_descr { PYBIND11_STR_TYPE name; object format; pybind11::int_ offset; };
+        struct field_descr {
+            pybind11::str name;
+            object format;
+            pybind11::int_ offset;
+            field_descr(pybind11::str &&name, object &&format, pybind11::int_ &&offset)
+                : name{std::move(name)}, format{std::move(format)}, offset{std::move(offset)} {};
+        };
+        auto field_dict = attr("fields").cast<dict>();
         std::vector<field_descr> field_descriptors;
+        field_descriptors.reserve(field_dict.size());
 
-        for (auto field : attr("fields").attr("items")()) {
+        for (auto field : field_dict.attr("items")()) {
             auto spec = field.cast<tuple>();
             auto name = spec[0].cast<pybind11::str>();
-            auto format = spec[1].cast<tuple>()[0].cast<dtype>();
-            auto offset = spec[1].cast<tuple>()[1].cast<pybind11::int_>();
-            if (!len(name) && format.kind() == 'V')
+            auto spec_fo = spec[1].cast<tuple>();
+            auto format = spec_fo[0].cast<dtype>();
+            auto offset = spec_fo[1].cast<pybind11::int_>();
+            if ((len(name) == 0u) && format.kind() == 'V') {
                 continue;
-            field_descriptors.push_back({(PYBIND11_STR_TYPE) name, format.strip_padding(format.itemsize()), offset});
+            }
+            field_descriptors.emplace_back(
+                std::move(name), format.strip_padding(format.itemsize()), std::move(offset));
         }
 
-        std::sort(field_descriptors.begin(), field_descriptors.end(),
-                  [](const field_descr& a, const field_descr& b) {
+        std::sort(field_descriptors.begin(),
+                  field_descriptors.end(),
+                  [](const field_descr &a, const field_descr &b) {
                       return a.offset.cast<int>() < b.offset.cast<int>();
                   });
 
         list names, formats, offsets;
-        for (auto& descr : field_descriptors) {
-            names.append(descr.name);
-            formats.append(descr.format);
-            offsets.append(descr.offset);
+        for (auto &descr : field_descriptors) {
+            names.append(std::move(descr.name));
+            formats.append(std::move(descr.format));
+            offsets.append(std::move(descr.offset));
         }
-        return dtype(names, formats, offsets, itemsize);
+        return dtype(std::move(names), std::move(formats), std::move(offsets), itemsize);
     }
 };
 
@@ -569,66 +693,85 @@ class array : public buffer {
     using StridesContainer = detail::any_container<ssize_t>;
 
     // Constructs an array taking shape/strides from arbitrary container types
-    array(const pybind11::dtype &dt, ShapeContainer shape, StridesContainer strides,
-          const void *ptr = nullptr, handle base = handle()) {
+    array(const pybind11::dtype &dt,
+          ShapeContainer shape,
+          StridesContainer strides,
+          const void *ptr = nullptr,
+          handle base = handle()) {
 
-        if (strides->empty())
+        if (strides->empty()) {
             *strides = detail::c_strides(*shape, dt.itemsize());
+        }
 
         auto ndim = shape->size();
-        if (ndim != strides->size())
+        if (ndim != strides->size()) {
             pybind11_fail("NumPy: shape ndim doesn't match strides ndim");
+        }
         auto descr = dt;
 
         int flags = 0;
         if (base && ptr) {
-            if (isinstance<array>(base))
+            if (isinstance<array>(base)) {
                 /* Copy flags from base (except ownership bit) */
-                flags = reinterpret_borrow<array>(base).flags() & ~detail::npy_api::NPY_ARRAY_OWNDATA_;
-            else
+                flags = reinterpret_borrow<array>(base).flags()
+                        & ~detail::npy_api::NPY_ARRAY_OWNDATA_;
+            } else {
                 /* Writable by default, easy to downgrade later on if needed */
                 flags = detail::npy_api::NPY_ARRAY_WRITEABLE_;
+            }
         }
 
         auto &api = detail::npy_api::get();
         auto tmp = reinterpret_steal<object>(api.PyArray_NewFromDescr_(
-            api.PyArray_Type_, descr.release().ptr(), (int) ndim,
+            api.PyArray_Type_,
+            descr.release().ptr(),
+            (int) ndim,
             // Use reinterpret_cast for PyPy on Windows (remove if fixed, checked on 7.3.1)
-            reinterpret_cast<Py_intptr_t*>(shape->data()),
-            reinterpret_cast<Py_intptr_t*>(strides->data()),
-            const_cast<void *>(ptr), flags, nullptr));
-        if (!tmp)
+            reinterpret_cast<Py_intptr_t *>(shape->data()),
+            reinterpret_cast<Py_intptr_t *>(strides->data()),
+            const_cast<void *>(ptr),
+            flags,
+            nullptr));
+        if (!tmp) {
             throw error_already_set();
+        }
         if (ptr) {
             if (base) {
                 api.PyArray_SetBaseObject_(tmp.ptr(), base.inc_ref().ptr());
             } else {
-                tmp = reinterpret_steal<object>(api.PyArray_NewCopy_(tmp.ptr(), -1 /* any order */));
+                tmp = reinterpret_steal<object>(
+                    api.PyArray_NewCopy_(tmp.ptr(), -1 /* any order */));
             }
         }
         m_ptr = tmp.release().ptr();
     }
 
-    array(const pybind11::dtype &dt, ShapeContainer shape, const void *ptr = nullptr, handle base = handle())
-        : array(dt, std::move(shape), {}, ptr, base) { }
+    array(const pybind11::dtype &dt,
+          ShapeContainer shape,
+          const void *ptr = nullptr,
+          handle base = handle())
+        : array(dt, std::move(shape), {}, ptr, base) {}
 
-    template <typename T, typename = detail::enable_if_t<std::is_integral<T>::value && !std::is_same<bool, T>::value>>
+    template <typename T,
+              typename
+              = detail::enable_if_t<std::is_integral<T>::value && !std::is_same<bool, T>::value>>
     array(const pybind11::dtype &dt, T count, const void *ptr = nullptr, handle base = handle())
-        : array(dt, {{count}}, ptr, base) { }
+        : array(dt, {{count}}, ptr, base) {}
 
     template <typename T>
     array(ShapeContainer shape, StridesContainer strides, const T *ptr, handle base = handle())
-        : array(pybind11::dtype::of<T>(), std::move(shape), std::move(strides), ptr, base) { }
+        : array(pybind11::dtype::of<T>(), std::move(shape), std::move(strides), ptr, base) {}
 
     template <typename T>
     array(ShapeContainer shape, const T *ptr, handle base = handle())
-        : array(std::move(shape), {}, ptr, base) { }
+        : array(std::move(shape), {}, ptr, base) {}
 
     template <typename T>
-    explicit array(ssize_t count, const T *ptr, handle base = handle()) : array({count}, {}, ptr, base) { }
+    explicit array(ssize_t count, const T *ptr, handle base = handle())
+        : array({count}, {}, ptr, base) {}
 
     explicit array(const buffer_info &info, handle base = handle())
-    : array(pybind11::dtype(info), info.shape, info.strides, info.ptr, base) { }
+        : array(pybind11::dtype(info), info.shape, info.strides, info.ptr, base) {}
 
     /// Array descriptor (dtype)
     pybind11::dtype dtype() const {
@@ -646,48 +789,38 @@ class array : public buffer {
     }
 
     /// Total number of bytes
-    ssize_t nbytes() const {
-        return size() * itemsize();
-    }
+    ssize_t nbytes() const { return size() * itemsize(); }
 
     /// Number of dimensions
-    ssize_t ndim() const {
-        return detail::array_proxy(m_ptr)->nd;
-    }
+    ssize_t ndim() const { return detail::array_proxy(m_ptr)->nd; }
 
     /// Base object
-    object base() const {
-        return reinterpret_borrow<object>(detail::array_proxy(m_ptr)->base);
-    }
+    object base() const { return reinterpret_borrow<object>(detail::array_proxy(m_ptr)->base); }
 
     /// Dimensions of the array
-    const ssize_t* shape() const {
-        return detail::array_proxy(m_ptr)->dimensions;
-    }
+    const ssize_t *shape() const { return detail::array_proxy(m_ptr)->dimensions; }
 
     /// Dimension along a given axis
     ssize_t shape(ssize_t dim) const {
-        if (dim >= ndim())
+        if (dim >= ndim()) {
             fail_dim_check(dim, "invalid axis");
+        }
         return shape()[dim];
     }
 
     /// Strides of the array
-    const ssize_t* strides() const {
-        return detail::array_proxy(m_ptr)->strides;
-    }
+    const ssize_t *strides() const { return detail::array_proxy(m_ptr)->strides; }
 
     /// Stride along a given axis
     ssize_t strides(ssize_t dim) const {
-        if (dim >= ndim())
+        if (dim >= ndim()) {
             fail_dim_check(dim, "invalid axis");
+        }
         return strides()[dim];
     }
 
     /// Return the NumPy array flags
-    int flags() const {
-        return detail::array_proxy(m_ptr)->flags;
-    }
+    int flags() const { return detail::array_proxy(m_ptr)->flags; }
 
     /// If set, the array is writeable (otherwise the buffer is read-only)
     bool writeable() const {
@@ -701,23 +834,27 @@ class array : public buffer {
 
     /// Pointer to the contained data. If index is not provided, points to the
     /// beginning of the buffer. May throw if the index would lead to out of bounds access.
-    template<typename... Ix> const void* data(Ix... index) const {
+    template <typename... Ix>
+    const void *data(Ix... index) const {
         return static_cast<const void *>(detail::array_proxy(m_ptr)->data + offset_at(index...));
     }
 
     /// Mutable pointer to the contained data. If index is not provided, points to the
     /// beginning of the buffer. May throw if the index would lead to out of bounds access.
     /// May throw if the array is not writeable.
-    template<typename... Ix> void* mutable_data(Ix... index) {
+    template <typename... Ix>
+    void *mutable_data(Ix... index) {
         check_writeable();
         return static_cast<void *>(detail::array_proxy(m_ptr)->data + offset_at(index...));
     }
 
     /// Byte offset from beginning of the array to a given index (full or partial).
     /// May throw if the index would lead to out of bounds access.
-    template<typename... Ix> ssize_t offset_at(Ix... index) const {
-        if ((ssize_t) sizeof...(index) > ndim())
+    template <typename... Ix>
+    ssize_t offset_at(Ix... index) const {
+        if ((ssize_t) sizeof...(index) > ndim()) {
             fail_dim_check(sizeof...(index), "too many indices for an array");
+        }
         return byte_offset(ssize_t(index)...);
     }
 
@@ -725,7 +862,8 @@ class array : public buffer {
 
     /// Item count from beginning of the array to a given index (full or partial).
     /// May throw if the index would lead to out of bounds access.
-    template<typename... Ix> ssize_t index_at(Ix... index) const {
+    template <typename... Ix>
+    ssize_t index_at(Ix... index) const {
         return offset_at(index...) / itemsize();
     }
 
@@ -735,30 +873,37 @@ class array : public buffer {
      * care: the array must not be destroyed or reshaped for the duration of the returned object,
      * and the caller must take care not to access invalid dimensions or dimension indices.
      */
-    template <typename T, ssize_t Dims = -1> detail::unchecked_mutable_reference<T, Dims> mutable_unchecked() & {
-        if (Dims >= 0 && ndim() != Dims)
-            throw std::domain_error("array has incorrect number of dimensions: " + std::to_string(ndim()) +
-                    "; expected " + std::to_string(Dims));
-        return detail::unchecked_mutable_reference<T, Dims>(mutable_data(), shape(), strides(), ndim());
+    template <typename T, ssize_t Dims = -1>
+    detail::unchecked_mutable_reference<T, Dims> mutable_unchecked() & {
+        if (PYBIND11_SILENCE_MSVC_C4127(Dims >= 0) && ndim() != Dims) {
+            throw std::domain_error("array has incorrect number of dimensions: "
+                                    + std::to_string(ndim()) + "; expected "
+                                    + std::to_string(Dims));
+        }
+        return detail::unchecked_mutable_reference<T, Dims>(
+            mutable_data(), shape(), strides(), ndim());
     }
 
     /**
      * Returns a proxy object that provides const access to the array's data without bounds or
      * dimensionality checking.  Unlike `mutable_unchecked()`, this does not require that the
-     * underlying array have the `writable` flag.  Use with care: the array must not be destroyed or
-     * reshaped for the duration of the returned object, and the caller must take care not to access
-     * invalid dimensions or dimension indices.
+     * underlying array have the `writable` flag.  Use with care: the array must not be destroyed
+     * or reshaped for the duration of the returned object, and the caller must take care not to
+     * access invalid dimensions or dimension indices.
      */
-    template <typename T, ssize_t Dims = -1> detail::unchecked_reference<T, Dims> unchecked() const & {
-        if (Dims >= 0 && ndim() != Dims)
-            throw std::domain_error("array has incorrect number of dimensions: " + std::to_string(ndim()) +
-                    "; expected " + std::to_string(Dims));
+    template <typename T, ssize_t Dims = -1>
+    detail::unchecked_reference<T, Dims> unchecked() const & {
+        if (PYBIND11_SILENCE_MSVC_C4127(Dims >= 0) && ndim() != Dims) {
+            throw std::domain_error("array has incorrect number of dimensions: "
+                                    + std::to_string(ndim()) + "; expected "
+                                    + std::to_string(Dims));
+        }
         return detail::unchecked_reference<T, Dims>(data(), shape(), strides(), ndim());
     }
 
     /// Return a new view with all of the dimensions of length 1 removed
     array squeeze() {
-        auto& api = detail::npy_api::get();
+        auto &api = detail::npy_api::get();
         return reinterpret_steal<array>(api.PyArray_Squeeze_(m_ptr));
     }
 
@@ -766,57 +911,92 @@ class array : public buffer {
     /// If refcheck is true and more that one reference exist to this array
     /// then resize will succeed only if it makes a reshape, i.e. original size doesn't change
     void resize(ShapeContainer new_shape, bool refcheck = true) {
-        detail::npy_api::PyArray_Dims d = {
-            // Use reinterpret_cast for PyPy on Windows (remove if fixed, checked on 7.3.1)
-            reinterpret_cast<Py_intptr_t*>(new_shape->data()),
-            int(new_shape->size())
-        };
+        detail::npy_api::PyArray_Dims d
+            = {// Use reinterpret_cast for PyPy on Windows (remove if fixed, checked on 7.3.1)
+               reinterpret_cast<Py_intptr_t *>(new_shape->data()),
+               int(new_shape->size())};
         // try to resize, set ordering param to -1 cause it's not used anyway
         auto new_array = reinterpret_steal<object>(
-            detail::npy_api::get().PyArray_Resize_(m_ptr, &d, int(refcheck), -1)
-        );
-        if (!new_array) throw error_already_set();
-        if (isinstance<array>(new_array)) { *this = std::move(new_array); }
+            detail::npy_api::get().PyArray_Resize_(m_ptr, &d, int(refcheck), -1));
+        if (!new_array) {
+            throw error_already_set();
+        }
+        if (isinstance<array>(new_array)) {
+            *this = std::move(new_array);
+        }
+    }
+
+    /// Optional `order` parameter omitted, to be added as needed.
+    array reshape(ShapeContainer new_shape) {
+        detail::npy_api::PyArray_Dims d
+            = {reinterpret_cast<Py_intptr_t *>(new_shape->data()), int(new_shape->size())};
+        auto new_array
+            = reinterpret_steal<array>(detail::npy_api::get().PyArray_Newshape_(m_ptr, &d, 0));
+        if (!new_array) {
+            throw error_already_set();
+        }
+        return new_array;
+    }
+
+    /// Create a view of an array in a different data type.
+    /// This function may fundamentally reinterpret the data in the array.
+    /// It is the responsibility of the caller to ensure that this is safe.
+    /// Only supports the `dtype` argument, the `type` argument is omitted,
+    /// to be added as needed.
+    array view(const std::string &dtype) {
+        auto &api = detail::npy_api::get();
+        auto new_view = reinterpret_steal<array>(api.PyArray_View_(
+            m_ptr, dtype::from_args(pybind11::str(dtype)).release().ptr(), nullptr));
+        if (!new_view) {
+            throw error_already_set();
+        }
+        return new_view;
     }
 
     /// Ensure that the argument is a NumPy array
     /// In case of an error, nullptr is returned and the Python error is cleared.
     static array ensure(handle h, int ExtraFlags = 0) {
         auto result = reinterpret_steal<array>(raw_array(h.ptr(), ExtraFlags));
-        if (!result)
+        if (!result) {
             PyErr_Clear();
+        }
         return result;
     }
 
 protected:
-    template<typename, typename> friend struct detail::npy_format_descriptor;
+    template <typename, typename>
+    friend struct detail::npy_format_descriptor;
 
-    void fail_dim_check(ssize_t dim, const std::string& msg) const {
-        throw index_error(msg + ": " + std::to_string(dim) +
-                          " (ndim = " + std::to_string(ndim()) + ")");
+    void fail_dim_check(ssize_t dim, const std::string &msg) const {
+        throw index_error(msg + ": " + std::to_string(dim) + " (ndim = " + std::to_string(ndim())
+                          + ')');
     }
 
-    template<typename... Ix> ssize_t byte_offset(Ix... index) const {
+    template <typename... Ix>
+    ssize_t byte_offset(Ix... index) const {
         check_dimensions(index...);
         return detail::byte_offset_unsafe(strides(), ssize_t(index)...);
     }
 
     void check_writeable() const {
-        if (!writeable())
+        if (!writeable()) {
             throw std::domain_error("array is not writeable");
+        }
     }
 
-    template<typename... Ix> void check_dimensions(Ix... index) const {
+    template <typename... Ix>
+    void check_dimensions(Ix... index) const {
         check_dimensions_impl(ssize_t(0), shape(), ssize_t(index)...);
     }
 
-    void check_dimensions_impl(ssize_t, const ssize_t*) const { }
+    void check_dimensions_impl(ssize_t, const ssize_t *) const {}
 
-    template<typename... Ix> void check_dimensions_impl(ssize_t axis, const ssize_t* shape, ssize_t i, Ix... index) const {
+    template <typename... Ix>
+    void check_dimensions_impl(ssize_t axis, const ssize_t *shape, ssize_t i, Ix... index) const {
         if (i >= *shape) {
-            throw index_error(std::string("index ") + std::to_string(i) +
-                              " is out of bounds for axis " + std::to_string(axis) +
-                              " with size " + std::to_string(*shape));
+            throw index_error(std::string("index ") + std::to_string(i)
+                              + " is out of bounds for axis " + std::to_string(axis)
+                              + " with size " + std::to_string(*shape));
         }
         check_dimensions_impl(axis + 1, shape + 1, index...);
     }
@@ -832,74 +1012,98 @@ class array : public buffer {
     }
 };
 
-template <typename T, int ExtraFlags = array::forcecast> class array_t : public array {
+template <typename T, int ExtraFlags = array::forcecast>
+class array_t : public array {
 private:
     struct private_ctor {};
     // Delegating constructor needed when both moving and accessing in the same constructor
-    array_t(private_ctor, ShapeContainer &&shape, StridesContainer &&strides, const T *ptr, handle base)
+    array_t(private_ctor,
+            ShapeContainer &&shape,
+            StridesContainer &&strides,
+            const T *ptr,
+            handle base)
         : array(std::move(shape), std::move(strides), ptr, base) {}
+
 public:
     static_assert(!detail::array_info<T>::is_array, "Array types cannot be used with array_t");
 
     using value_type = T;
 
     array_t() : array(0, static_cast<const T *>(nullptr)) {}
-    array_t(handle h, borrowed_t) : array(h, borrowed_t{}) { }
-    array_t(handle h, stolen_t) : array(h, stolen_t{}) { }
+    array_t(handle h, borrowed_t) : array(h, borrowed_t{}) {}
+    array_t(handle h, stolen_t) : array(h, stolen_t{}) {}
 
     PYBIND11_DEPRECATED("Use array_t<T>::ensure() instead")
     array_t(handle h, bool is_borrowed) : array(raw_array_t(h.ptr()), stolen_t{}) {
-        if (!m_ptr) PyErr_Clear();
-        if (!is_borrowed) Py_XDECREF(h.ptr());
+        if (!m_ptr) {
+            PyErr_Clear();
+        }
+        if (!is_borrowed) {
+            Py_XDECREF(h.ptr());
+        }
     }
 
+    // NOLINTNEXTLINE(google-explicit-constructor)
     array_t(const object &o) : array(raw_array_t(o.ptr()), stolen_t{}) {
-        if (!m_ptr) throw error_already_set();
+        if (!m_ptr) {
+            throw error_already_set();
+        }
     }
 
-    explicit array_t(const buffer_info& info, handle base = handle()) : array(info, base) { }
+    explicit array_t(const buffer_info &info, handle base = handle()) : array(info, base) {}
 
-    array_t(ShapeContainer shape, StridesContainer strides, const T *ptr = nullptr, handle base = handle())
-        : array(std::move(shape), std::move(strides), ptr, base) { }
+    array_t(ShapeContainer shape,
+            StridesContainer strides,
+            const T *ptr = nullptr,
+            handle base = handle())
+        : array(std::move(shape), std::move(strides), ptr, base) {}
 
     explicit array_t(ShapeContainer shape, const T *ptr = nullptr, handle base = handle())
-        : array_t(private_ctor{}, std::move(shape),
-                ExtraFlags & f_style
-                ? detail::f_strides(*shape, itemsize())
-                : detail::c_strides(*shape, itemsize()),
-                ptr, base) { }
+        : array_t(private_ctor{},
+                  std::move(shape),
+                  (ExtraFlags & f_style) != 0 ? detail::f_strides(*shape, itemsize())
+                                              : detail::c_strides(*shape, itemsize()),
+                  ptr,
+                  base) {}
 
     explicit array_t(ssize_t count, const T *ptr = nullptr, handle base = handle())
-        : array({count}, {}, ptr, base) { }
+        : array({count}, {}, ptr, base) {}
 
-    constexpr ssize_t itemsize() const {
-        return sizeof(T);
-    }
+    constexpr ssize_t itemsize() const { return sizeof(T); }
 
-    template<typename... Ix> ssize_t index_at(Ix... index) const {
+    template <typename... Ix>
+    ssize_t index_at(Ix... index) const {
         return offset_at(index...) / itemsize();
     }
 
-    template<typename... Ix> const T* data(Ix... index) const {
-        return static_cast<const T*>(array::data(index...));
+    template <typename... Ix>
+    const T *data(Ix... index) const {
+        return static_cast<const T *>(array::data(index...));
     }
 
-    template<typename... Ix> T* mutable_data(Ix... index) {
-        return static_cast<T*>(array::mutable_data(index...));
+    template <typename... Ix>
+    T *mutable_data(Ix... index) {
+        return static_cast<T *>(array::mutable_data(index...));
     }
 
     // Reference to element at a given index
-    template<typename... Ix> const T& at(Ix... index) const {
-        if ((ssize_t) sizeof...(index) != ndim())
+    template <typename... Ix>
+    const T &at(Ix... index) const {
+        if ((ssize_t) sizeof...(index) != ndim()) {
             fail_dim_check(sizeof...(index), "index dimension mismatch");
-        return *(static_cast<const T*>(array::data()) + byte_offset(ssize_t(index)...) / itemsize());
+        }
+        return *(static_cast<const T *>(array::data())
+                 + byte_offset(ssize_t(index)...) / itemsize());
     }
 
     // Mutable reference to element at a given index
-    template<typename... Ix> T& mutable_at(Ix... index) {
-        if ((ssize_t) sizeof...(index) != ndim())
+    template <typename... Ix>
+    T &mutable_at(Ix... index) {
+        if ((ssize_t) sizeof...(index) != ndim()) {
             fail_dim_check(sizeof...(index), "index dimension mismatch");
-        return *(static_cast<T*>(array::mutable_data()) + byte_offset(ssize_t(index)...) / itemsize());
+        }
+        return *(static_cast<T *>(array::mutable_data())
+                 + byte_offset(ssize_t(index)...) / itemsize());
     }
 
     /**
@@ -908,7 +1112,8 @@ template <typename T, int ExtraFlags = array::forcecast> class array_t : public
      * care: the array must not be destroyed or reshaped for the duration of the returned object,
      * and the caller must take care not to access invalid dimensions or dimension indices.
      */
-    template <ssize_t Dims = -1> detail::unchecked_mutable_reference<T, Dims> mutable_unchecked() & {
+    template <ssize_t Dims = -1>
+    detail::unchecked_mutable_reference<T, Dims> mutable_unchecked() & {
         return array::mutable_unchecked<T, Dims>();
     }
 
@@ -919,7 +1124,8 @@ template <typename T, int ExtraFlags = array::forcecast> class array_t : public
      * for the duration of the returned object, and the caller must take care not to access invalid
      * dimensions or dimension indices.
      */
-    template <ssize_t Dims = -1> detail::unchecked_reference<T, Dims> unchecked() const & {
+    template <ssize_t Dims = -1>
+    detail::unchecked_reference<T, Dims> unchecked() const & {
         return array::unchecked<T, Dims>();
     }
 
@@ -927,15 +1133,17 @@ template <typename T, int ExtraFlags = array::forcecast> class array_t : public
     /// it).  In case of an error, nullptr is returned and the Python error is cleared.
     static array_t ensure(handle h) {
         auto result = reinterpret_steal<array_t>(raw_array_t(h.ptr()));
-        if (!result)
+        if (!result) {
             PyErr_Clear();
+        }
         return result;
     }
 
     static bool check_(handle h) {
         const auto &api = detail::npy_api::get();
         return api.PyArray_Check_(h.ptr())
-               && api.PyArray_EquivTypes_(detail::array_proxy(h.ptr())->descr, dtype::of<T>().ptr())
+               && api.PyArray_EquivTypes_(detail::array_proxy(h.ptr())->descr,
+                                          dtype::of<T>().ptr())
                && detail::check_flags(h.ptr(), ExtraFlags & (array::c_style | array::f_style));
     }
 
@@ -946,9 +1154,13 @@ template <typename T, int ExtraFlags = array::forcecast> class array_t : public
             PyErr_SetString(PyExc_ValueError, "cannot create a pybind11::array_t from a nullptr");
             return nullptr;
         }
-        return detail::npy_api::get().PyArray_FromAny_(
-            ptr, dtype::of<T>().release().ptr(), 0, 0,
-            detail::npy_api::NPY_ARRAY_ENSUREARRAY_ | ExtraFlags, nullptr);
+        return detail::npy_api::get().PyArray_FromAny_(ptr,
+                                                       dtype::of<T>().release().ptr(),
+                                                       0,
+                                                       0,
+                                                       detail::npy_api::NPY_ARRAY_ENSUREARRAY_
+                                                           | ExtraFlags,
+                                                       nullptr);
     }
 };
 
@@ -959,11 +1171,13 @@ struct format_descriptor<T, detail::enable_if_t<detail::is_pod_struct<T>::value>
     }
 };
 
-template <size_t N> struct format_descriptor<char[N]> {
-    static std::string format() { return std::to_string(N) + "s"; }
+template <size_t N>
+struct format_descriptor<char[N]> {
+    static std::string format() { return std::to_string(N) + 's'; }
 };
-template <size_t N> struct format_descriptor<std::array<char, N>> {
-    static std::string format() { return std::to_string(N) + "s"; }
+template <size_t N>
+struct format_descriptor<std::array<char, N>> {
+    static std::string format() { return std::to_string(N) + 's'; }
 };
 
 template <typename T>
@@ -978,7 +1192,7 @@ template <typename T>
 struct format_descriptor<T, detail::enable_if_t<detail::array_info<T>::is_array>> {
     static std::string format() {
         using namespace detail;
-        static constexpr auto extents = _("(") + array_info<T>::extents + _(")");
+        static constexpr auto extents = const_name("(") + array_info<T>::extents + const_name(")");
         return extents.text + format_descriptor<remove_all_extents_t<T>>::format();
     }
 };
@@ -989,8 +1203,9 @@ struct pyobject_caster<array_t<T, ExtraFlags>> {
     using type = array_t<T, ExtraFlags>;
 
     bool load(handle src, bool convert) {
-        if (!convert && !type::check_(src))
+        if (!convert && !type::check_(src)) {
             return false;
+        }
         value = type::ensure(src);
         return static_cast<bool>(value);
     }
@@ -1003,7 +1218,7 @@ struct pyobject_caster<array_t<T, ExtraFlags>> {
 
 template <typename T>
 struct compare_buffer_info<T, detail::enable_if_t<detail::is_pod_struct<T>::value>> {
-    static bool compare(const buffer_info& b) {
+    static bool compare(const buffer_info &b) {
         return npy_api::get().PyArray_EquivTypes_(dtype::of<T>().ptr(), dtype(b).ptr());
     }
 };
@@ -1013,73 +1228,105 @@ struct npy_format_descriptor_name;
 
 template <typename T>
 struct npy_format_descriptor_name<T, enable_if_t<std::is_integral<T>::value>> {
-    static constexpr auto name = _<std::is_same<T, bool>::value>(
-        _("bool"), _<std::is_signed<T>::value>("numpy.int", "numpy.uint") + _<sizeof(T)*8>()
-    );
+    static constexpr auto name = const_name<std::is_same<T, bool>::value>(
+        const_name("bool"),
+        const_name<std::is_signed<T>::value>("numpy.int", "numpy.uint")
+            + const_name<sizeof(T) * 8>());
 };
 
 template <typename T>
 struct npy_format_descriptor_name<T, enable_if_t<std::is_floating_point<T>::value>> {
-    static constexpr auto name = _<std::is_same<T, float>::value || std::is_same<T, double>::value>(
-        _("numpy.float") + _<sizeof(T)*8>(), _("numpy.longdouble")
-    );
+    static constexpr auto name = const_name < std::is_same<T, float>::value
+                                 || std::is_same<T, const float>::value
+                                 || std::is_same<T, double>::value
+                                 || std::is_same<T, const double>::value
+                                        > (const_name("numpy.float") + const_name<sizeof(T) * 8>(),
+                                           const_name("numpy.longdouble"));
 };
 
 template <typename T>
 struct npy_format_descriptor_name<T, enable_if_t<is_complex<T>::value>> {
-    static constexpr auto name = _<std::is_same<typename T::value_type, float>::value
-                                   || std::is_same<typename T::value_type, double>::value>(
-        _("numpy.complex") + _<sizeof(typename T::value_type)*16>(), _("numpy.longcomplex")
-    );
+    static constexpr auto name = const_name < std::is_same<typename T::value_type, float>::value
+                                 || std::is_same<typename T::value_type, const float>::value
+                                 || std::is_same<typename T::value_type, double>::value
+                                 || std::is_same<typename T::value_type, const double>::value
+                                        > (const_name("numpy.complex")
+                                               + const_name<sizeof(typename T::value_type) * 16>(),
+                                           const_name("numpy.longcomplex"));
 };
 
 template <typename T>
-struct npy_format_descriptor<T, enable_if_t<satisfies_any_of<T, std::is_arithmetic, is_complex>::value>>
+struct npy_format_descriptor<
+    T,
+    enable_if_t<satisfies_any_of<T, std::is_arithmetic, is_complex>::value>>
     : npy_format_descriptor_name<T> {
 private:
     // NB: the order here must match the one in common.h
-    constexpr static const int values[15] = {
-        npy_api::NPY_BOOL_,
-        npy_api::NPY_BYTE_,   npy_api::NPY_UBYTE_,   npy_api::NPY_INT16_,    npy_api::NPY_UINT16_,
-        npy_api::NPY_INT32_,  npy_api::NPY_UINT32_,  npy_api::NPY_INT64_,    npy_api::NPY_UINT64_,
-        npy_api::NPY_FLOAT_,  npy_api::NPY_DOUBLE_,  npy_api::NPY_LONGDOUBLE_,
-        npy_api::NPY_CFLOAT_, npy_api::NPY_CDOUBLE_, npy_api::NPY_CLONGDOUBLE_
-    };
+    constexpr static const int values[15] = {npy_api::NPY_BOOL_,
+                                             npy_api::NPY_BYTE_,
+                                             npy_api::NPY_UBYTE_,
+                                             npy_api::NPY_INT16_,
+                                             npy_api::NPY_UINT16_,
+                                             npy_api::NPY_INT32_,
+                                             npy_api::NPY_UINT32_,
+                                             npy_api::NPY_INT64_,
+                                             npy_api::NPY_UINT64_,
+                                             npy_api::NPY_FLOAT_,
+                                             npy_api::NPY_DOUBLE_,
+                                             npy_api::NPY_LONGDOUBLE_,
+                                             npy_api::NPY_CFLOAT_,
+                                             npy_api::NPY_CDOUBLE_,
+                                             npy_api::NPY_CLONGDOUBLE_};
 
 public:
     static constexpr int value = values[detail::is_fmt_numeric<T>::index];
 
     static pybind11::dtype dtype() {
-        if (auto ptr = npy_api::get().PyArray_DescrFromType_(value))
+        if (auto *ptr = npy_api::get().PyArray_DescrFromType_(value)) {
             return reinterpret_steal<pybind11::dtype>(ptr);
+        }
         pybind11_fail("Unsupported buffer format!");
     }
 };
 
-#define PYBIND11_DECL_CHAR_FMT \
-    static constexpr auto name = _("S") + _<N>(); \
-    static pybind11::dtype dtype() { return pybind11::dtype(std::string("S") + std::to_string(N)); }
-template <size_t N> struct npy_format_descriptor<char[N]> { PYBIND11_DECL_CHAR_FMT };
-template <size_t N> struct npy_format_descriptor<std::array<char, N>> { PYBIND11_DECL_CHAR_FMT };
+#define PYBIND11_DECL_CHAR_FMT                                                                    \
+    static constexpr auto name = const_name("S") + const_name<N>();                               \
+    static pybind11::dtype dtype() {                                                              \
+        return pybind11::dtype(std::string("S") + std::to_string(N));                             \
+    }
+template <size_t N>
+struct npy_format_descriptor<char[N]> {
+    PYBIND11_DECL_CHAR_FMT
+};
+template <size_t N>
+struct npy_format_descriptor<std::array<char, N>> {
+    PYBIND11_DECL_CHAR_FMT
+};
 #undef PYBIND11_DECL_CHAR_FMT
 
-template<typename T> struct npy_format_descriptor<T, enable_if_t<array_info<T>::is_array>> {
+template <typename T>
+struct npy_format_descriptor<T, enable_if_t<array_info<T>::is_array>> {
 private:
     using base_descr = npy_format_descriptor<typename array_info<T>::type>;
+
 public:
     static_assert(!array_info<T>::is_empty, "Zero-sized arrays are not supported");
 
-    static constexpr auto name = _("(") + array_info<T>::extents + _(")") + base_descr::name;
+    static constexpr auto name
+        = const_name("(") + array_info<T>::extents + const_name(")") + base_descr::name;
     static pybind11::dtype dtype() {
         list shape;
         array_info<T>::append_extents(shape);
-        return pybind11::dtype::from_args(pybind11::make_tuple(base_descr::dtype(), shape));
+        return pybind11::dtype::from_args(
+            pybind11::make_tuple(base_descr::dtype(), std::move(shape)));
     }
 };
 
-template<typename T> struct npy_format_descriptor<T, enable_if_t<std::is_enum<T>::value>> {
+template <typename T>
+struct npy_format_descriptor<T, enable_if_t<std::is_enum<T>::value>> {
 private:
     using base_descr = npy_format_descriptor<typename std::underlying_type<T>::type>;
+
 public:
     static constexpr auto name = base_descr::name;
     static pybind11::dtype dtype() { return base_descr::dtype(); }
@@ -1093,31 +1340,38 @@ struct field_descriptor {
     dtype descr;
 };
 
-inline PYBIND11_NOINLINE void register_structured_dtype(
-    any_container<field_descriptor> fields,
-    const std::type_info& tinfo, ssize_t itemsize,
-    bool (*direct_converter)(PyObject *, void *&)) {
+PYBIND11_NOINLINE void register_structured_dtype(any_container<field_descriptor> fields,
+                                                 const std::type_info &tinfo,
+                                                 ssize_t itemsize,
+                                                 bool (*direct_converter)(PyObject *, void *&)) {
 
-    auto& numpy_internals = get_numpy_internals();
-    if (numpy_internals.get_type_info(tinfo, false))
+    auto &numpy_internals = get_numpy_internals();
+    if (numpy_internals.get_type_info(tinfo, false)) {
         pybind11_fail("NumPy: dtype is already registered");
+    }
 
     // Use ordered fields because order matters as of NumPy 1.14:
     // https://docs.scipy.org/doc/numpy/release.html#multiple-field-indexing-assignment-of-structured-arrays
     std::vector<field_descriptor> ordered_fields(std::move(fields));
-    std::sort(ordered_fields.begin(), ordered_fields.end(),
+    std::sort(
+        ordered_fields.begin(),
+        ordered_fields.end(),
         [](const field_descriptor &a, const field_descriptor &b) { return a.offset < b.offset; });
 
     list names, formats, offsets;
-    for (auto& field : ordered_fields) {
-        if (!field.descr)
-            pybind11_fail(std::string("NumPy: unsupported field dtype: `") +
-                            field.name + "` @ " + tinfo.name());
-        names.append(PYBIND11_STR_TYPE(field.name));
+    for (auto &field : ordered_fields) {
+        if (!field.descr) {
+            pybind11_fail(std::string("NumPy: unsupported field dtype: `") + field.name + "` @ "
+                          + tinfo.name());
+        }
+        names.append(pybind11::str(field.name));
         formats.append(field.descr);
         offsets.append(pybind11::int_(field.offset));
     }
-    auto dtype_ptr = pybind11::dtype(names, formats, offsets, itemsize).release().ptr();
+    auto *dtype_ptr
+        = pybind11::dtype(std::move(names), std::move(formats), std::move(offsets), itemsize)
+              .release()
+              .ptr();
 
     // There is an existing bug in NumPy (as of v1.11): trailing bytes are
     // not encoded explicitly into the format string. This will supposedly
@@ -1134,36 +1388,39 @@ inline PYBIND11_NOINLINE void register_structured_dtype(
     // overriding the endianness. Putting the ^ in front of individual fields
     // isn't guaranteed to work due to https://github.com/numpy/numpy/issues/9049
     oss << "^T{";
-    for (auto& field : ordered_fields) {
-        if (field.offset > offset)
+    for (auto &field : ordered_fields) {
+        if (field.offset > offset) {
             oss << (field.offset - offset) << 'x';
+        }
         oss << field.format << ':' << field.name << ':';
         offset = field.offset + field.size;
     }
-    if (itemsize > offset)
+    if (itemsize > offset) {
         oss << (itemsize - offset) << 'x';
+    }
     oss << '}';
     auto format_str = oss.str();
 
-    // Sanity check: verify that NumPy properly parses our buffer format string
-    auto& api = npy_api::get();
-    auto arr =  array(buffer_info(nullptr, itemsize, format_str, 1));
-    if (!api.PyArray_EquivTypes_(dtype_ptr, arr.dtype().ptr()))
+    // Smoke test: verify that NumPy properly parses our buffer format string
+    auto &api = npy_api::get();
+    auto arr = array(buffer_info(nullptr, itemsize, format_str, 1));
+    if (!api.PyArray_EquivTypes_(dtype_ptr, arr.dtype().ptr())) {
         pybind11_fail("NumPy: invalid buffer descriptor!");
+    }
 
     auto tindex = std::type_index(tinfo);
-    numpy_internals.registered_dtypes[tindex] = { dtype_ptr, format_str };
+    numpy_internals.registered_dtypes[tindex] = {dtype_ptr, std::move(format_str)};
     get_internals().direct_conversions[tindex].push_back(direct_converter);
 }
 
-template <typename T, typename SFINAE> struct npy_format_descriptor {
-    static_assert(is_pod_struct<T>::value, "Attempt to use a non-POD or unimplemented POD type as a numpy dtype");
+template <typename T, typename SFINAE>
+struct npy_format_descriptor {
+    static_assert(is_pod_struct<T>::value,
+                  "Attempt to use a non-POD or unimplemented POD type as a numpy dtype");
 
     static constexpr auto name = make_caster<T>::name;
 
-    static pybind11::dtype dtype() {
-        return reinterpret_borrow<pybind11::dtype>(dtype_ptr());
-    }
+    static pybind11::dtype dtype() { return reinterpret_borrow<pybind11::dtype>(dtype_ptr()); }
 
     static std::string format() {
         static auto format_str = get_numpy_internals().get_type_info<T>(true)->format_str;
@@ -1171,20 +1428,23 @@ template <typename T, typename SFINAE> struct npy_format_descriptor {
     }
 
     static void register_dtype(any_container<field_descriptor> fields) {
-        register_structured_dtype(std::move(fields), typeid(typename std::remove_cv<T>::type),
-                                  sizeof(T), &direct_converter);
+        register_structured_dtype(std::move(fields),
+                                  typeid(typename std::remove_cv<T>::type),
+                                  sizeof(T),
+                                  &direct_converter);
     }
 
 private:
-    static PyObject* dtype_ptr() {
-        static PyObject* ptr = get_numpy_internals().get_type_info<T>(true)->dtype_ptr;
+    static PyObject *dtype_ptr() {
+        static PyObject *ptr = get_numpy_internals().get_type_info<T>(true)->dtype_ptr;
         return ptr;
     }
 
-    static bool direct_converter(PyObject *obj, void*& value) {
-        auto& api = npy_api::get();
-        if (!PyObject_TypeCheck(obj, api.PyVoidArrType_Type_))
+    static bool direct_converter(PyObject *obj, void *&value) {
+        auto &api = npy_api::get();
+        if (!PyObject_TypeCheck(obj, api.PyVoidArrType_Type_)) {
             return false;
+        }
         if (auto descr = reinterpret_steal<object>(api.PyArray_DescrFromScalar_(obj))) {
             if (api.PyArray_EquivTypes_(dtype_ptr(), descr.ptr())) {
                 value = ((PyVoidScalarObject_Proxy *) obj)->obval;
@@ -1196,78 +1456,80 @@ template <typename T, typename SFINAE> struct npy_format_descriptor {
 };
 
 #ifdef __CLION_IDE__ // replace heavy macro with dummy code for the IDE (doesn't affect code)
-# define PYBIND11_NUMPY_DTYPE(Type, ...) ((void)0)
-# define PYBIND11_NUMPY_DTYPE_EX(Type, ...) ((void)0)
+#    define PYBIND11_NUMPY_DTYPE(Type, ...) ((void) 0)
+#    define PYBIND11_NUMPY_DTYPE_EX(Type, ...) ((void) 0)
 #else
 
-#define PYBIND11_FIELD_DESCRIPTOR_EX(T, Field, Name)                                          \
-    ::pybind11::detail::field_descriptor {                                                    \
-        Name, offsetof(T, Field), sizeof(decltype(std::declval<T>().Field)),                  \
-        ::pybind11::format_descriptor<decltype(std::declval<T>().Field)>::format(),           \
-        ::pybind11::detail::npy_format_descriptor<decltype(std::declval<T>().Field)>::dtype() \
-    }
+#    define PYBIND11_FIELD_DESCRIPTOR_EX(T, Field, Name)                                          \
+        ::pybind11::detail::field_descriptor {                                                    \
+            Name, offsetof(T, Field), sizeof(decltype(std::declval<T>().Field)),                  \
+                ::pybind11::format_descriptor<decltype(std::declval<T>().Field)>::format(),       \
+                ::pybind11::detail::npy_format_descriptor<                                        \
+                    decltype(std::declval<T>().Field)>::dtype()                                   \
+        }
 
 // Extract name, offset and format descriptor for a struct field
-#define PYBIND11_FIELD_DESCRIPTOR(T, Field) PYBIND11_FIELD_DESCRIPTOR_EX(T, Field, #Field)
+#    define PYBIND11_FIELD_DESCRIPTOR(T, Field) PYBIND11_FIELD_DESCRIPTOR_EX(T, Field, #    Field)
 
 // The main idea of this macro is borrowed from https://github.com/swansontec/map-macro
 // (C) William Swanson, Paul Fultz
-#define PYBIND11_EVAL0(...) __VA_ARGS__
-#define PYBIND11_EVAL1(...) PYBIND11_EVAL0 (PYBIND11_EVAL0 (PYBIND11_EVAL0 (__VA_ARGS__)))
-#define PYBIND11_EVAL2(...) PYBIND11_EVAL1 (PYBIND11_EVAL1 (PYBIND11_EVAL1 (__VA_ARGS__)))
-#define PYBIND11_EVAL3(...) PYBIND11_EVAL2 (PYBIND11_EVAL2 (PYBIND11_EVAL2 (__VA_ARGS__)))
-#define PYBIND11_EVAL4(...) PYBIND11_EVAL3 (PYBIND11_EVAL3 (PYBIND11_EVAL3 (__VA_ARGS__)))
-#define PYBIND11_EVAL(...)  PYBIND11_EVAL4 (PYBIND11_EVAL4 (PYBIND11_EVAL4 (__VA_ARGS__)))
-#define PYBIND11_MAP_END(...)
-#define PYBIND11_MAP_OUT
-#define PYBIND11_MAP_COMMA ,
-#define PYBIND11_MAP_GET_END() 0, PYBIND11_MAP_END
-#define PYBIND11_MAP_NEXT0(test, next, ...) next PYBIND11_MAP_OUT
-#define PYBIND11_MAP_NEXT1(test, next) PYBIND11_MAP_NEXT0 (test, next, 0)
-#define PYBIND11_MAP_NEXT(test, next)  PYBIND11_MAP_NEXT1 (PYBIND11_MAP_GET_END test, next)
-#if defined(_MSC_VER) && !defined(__clang__) // MSVC is not as eager to expand macros, hence this workaround
-#define PYBIND11_MAP_LIST_NEXT1(test, next) \
-    PYBIND11_EVAL0 (PYBIND11_MAP_NEXT0 (test, PYBIND11_MAP_COMMA next, 0))
-#else
-#define PYBIND11_MAP_LIST_NEXT1(test, next) \
-    PYBIND11_MAP_NEXT0 (test, PYBIND11_MAP_COMMA next, 0)
-#endif
-#define PYBIND11_MAP_LIST_NEXT(test, next) \
-    PYBIND11_MAP_LIST_NEXT1 (PYBIND11_MAP_GET_END test, next)
-#define PYBIND11_MAP_LIST0(f, t, x, peek, ...) \
-    f(t, x) PYBIND11_MAP_LIST_NEXT (peek, PYBIND11_MAP_LIST1) (f, t, peek, __VA_ARGS__)
-#define PYBIND11_MAP_LIST1(f, t, x, peek, ...) \
-    f(t, x) PYBIND11_MAP_LIST_NEXT (peek, PYBIND11_MAP_LIST0) (f, t, peek, __VA_ARGS__)
+#    define PYBIND11_EVAL0(...) __VA_ARGS__
+#    define PYBIND11_EVAL1(...) PYBIND11_EVAL0(PYBIND11_EVAL0(PYBIND11_EVAL0(__VA_ARGS__)))
+#    define PYBIND11_EVAL2(...) PYBIND11_EVAL1(PYBIND11_EVAL1(PYBIND11_EVAL1(__VA_ARGS__)))
+#    define PYBIND11_EVAL3(...) PYBIND11_EVAL2(PYBIND11_EVAL2(PYBIND11_EVAL2(__VA_ARGS__)))
+#    define PYBIND11_EVAL4(...) PYBIND11_EVAL3(PYBIND11_EVAL3(PYBIND11_EVAL3(__VA_ARGS__)))
+#    define PYBIND11_EVAL(...) PYBIND11_EVAL4(PYBIND11_EVAL4(PYBIND11_EVAL4(__VA_ARGS__)))
+#    define PYBIND11_MAP_END(...)
+#    define PYBIND11_MAP_OUT
+#    define PYBIND11_MAP_COMMA ,
+#    define PYBIND11_MAP_GET_END() 0, PYBIND11_MAP_END
+#    define PYBIND11_MAP_NEXT0(test, next, ...) next PYBIND11_MAP_OUT
+#    define PYBIND11_MAP_NEXT1(test, next) PYBIND11_MAP_NEXT0(test, next, 0)
+#    define PYBIND11_MAP_NEXT(test, next) PYBIND11_MAP_NEXT1(PYBIND11_MAP_GET_END test, next)
+#    if defined(_MSC_VER)                                                                         \
+        && !defined(__clang__) // MSVC is not as eager to expand macros, hence this workaround
+#        define PYBIND11_MAP_LIST_NEXT1(test, next)                                               \
+            PYBIND11_EVAL0(PYBIND11_MAP_NEXT0(test, PYBIND11_MAP_COMMA next, 0))
+#    else
+#        define PYBIND11_MAP_LIST_NEXT1(test, next)                                               \
+            PYBIND11_MAP_NEXT0(test, PYBIND11_MAP_COMMA next, 0)
+#    endif
+#    define PYBIND11_MAP_LIST_NEXT(test, next)                                                    \
+        PYBIND11_MAP_LIST_NEXT1(PYBIND11_MAP_GET_END test, next)
+#    define PYBIND11_MAP_LIST0(f, t, x, peek, ...)                                                \
+        f(t, x) PYBIND11_MAP_LIST_NEXT(peek, PYBIND11_MAP_LIST1)(f, t, peek, __VA_ARGS__)
+#    define PYBIND11_MAP_LIST1(f, t, x, peek, ...)                                                \
+        f(t, x) PYBIND11_MAP_LIST_NEXT(peek, PYBIND11_MAP_LIST0)(f, t, peek, __VA_ARGS__)
 // PYBIND11_MAP_LIST(f, t, a1, a2, ...) expands to f(t, a1), f(t, a2), ...
-#define PYBIND11_MAP_LIST(f, t, ...) \
-    PYBIND11_EVAL (PYBIND11_MAP_LIST1 (f, t, __VA_ARGS__, (), 0))
-
-#define PYBIND11_NUMPY_DTYPE(Type, ...) \
-    ::pybind11::detail::npy_format_descriptor<Type>::register_dtype \
-        (::std::vector<::pybind11::detail::field_descriptor> \
-         {PYBIND11_MAP_LIST (PYBIND11_FIELD_DESCRIPTOR, Type, __VA_ARGS__)})
-
-#if defined(_MSC_VER) && !defined(__clang__)
-#define PYBIND11_MAP2_LIST_NEXT1(test, next) \
-    PYBIND11_EVAL0 (PYBIND11_MAP_NEXT0 (test, PYBIND11_MAP_COMMA next, 0))
-#else
-#define PYBIND11_MAP2_LIST_NEXT1(test, next) \
-    PYBIND11_MAP_NEXT0 (test, PYBIND11_MAP_COMMA next, 0)
-#endif
-#define PYBIND11_MAP2_LIST_NEXT(test, next) \
-    PYBIND11_MAP2_LIST_NEXT1 (PYBIND11_MAP_GET_END test, next)
-#define PYBIND11_MAP2_LIST0(f, t, x1, x2, peek, ...) \
-    f(t, x1, x2) PYBIND11_MAP2_LIST_NEXT (peek, PYBIND11_MAP2_LIST1) (f, t, peek, __VA_ARGS__)
-#define PYBIND11_MAP2_LIST1(f, t, x1, x2, peek, ...) \
-    f(t, x1, x2) PYBIND11_MAP2_LIST_NEXT (peek, PYBIND11_MAP2_LIST0) (f, t, peek, __VA_ARGS__)
+#    define PYBIND11_MAP_LIST(f, t, ...)                                                          \
+        PYBIND11_EVAL(PYBIND11_MAP_LIST1(f, t, __VA_ARGS__, (), 0))
+
+#    define PYBIND11_NUMPY_DTYPE(Type, ...)                                                       \
+        ::pybind11::detail::npy_format_descriptor<Type>::register_dtype(                          \
+            ::std::vector<::pybind11::detail::field_descriptor>{                                  \
+                PYBIND11_MAP_LIST(PYBIND11_FIELD_DESCRIPTOR, Type, __VA_ARGS__)})
+
+#    if defined(_MSC_VER) && !defined(__clang__)
+#        define PYBIND11_MAP2_LIST_NEXT1(test, next)                                              \
+            PYBIND11_EVAL0(PYBIND11_MAP_NEXT0(test, PYBIND11_MAP_COMMA next, 0))
+#    else
+#        define PYBIND11_MAP2_LIST_NEXT1(test, next)                                              \
+            PYBIND11_MAP_NEXT0(test, PYBIND11_MAP_COMMA next, 0)
+#    endif
+#    define PYBIND11_MAP2_LIST_NEXT(test, next)                                                   \
+        PYBIND11_MAP2_LIST_NEXT1(PYBIND11_MAP_GET_END test, next)
+#    define PYBIND11_MAP2_LIST0(f, t, x1, x2, peek, ...)                                          \
+        f(t, x1, x2) PYBIND11_MAP2_LIST_NEXT(peek, PYBIND11_MAP2_LIST1)(f, t, peek, __VA_ARGS__)
+#    define PYBIND11_MAP2_LIST1(f, t, x1, x2, peek, ...)                                          \
+        f(t, x1, x2) PYBIND11_MAP2_LIST_NEXT(peek, PYBIND11_MAP2_LIST0)(f, t, peek, __VA_ARGS__)
 // PYBIND11_MAP2_LIST(f, t, a1, a2, ...) expands to f(t, a1, a2), f(t, a3, a4), ...
-#define PYBIND11_MAP2_LIST(f, t, ...) \
-    PYBIND11_EVAL (PYBIND11_MAP2_LIST1 (f, t, __VA_ARGS__, (), 0))
+#    define PYBIND11_MAP2_LIST(f, t, ...)                                                         \
+        PYBIND11_EVAL(PYBIND11_MAP2_LIST1(f, t, __VA_ARGS__, (), 0))
 
-#define PYBIND11_NUMPY_DTYPE_EX(Type, ...) \
-    ::pybind11::detail::npy_format_descriptor<Type>::register_dtype \
-        (::std::vector<::pybind11::detail::field_descriptor> \
-         {PYBIND11_MAP2_LIST (PYBIND11_FIELD_DESCRIPTOR_EX, Type, __VA_ARGS__)})
+#    define PYBIND11_NUMPY_DTYPE_EX(Type, ...)                                                    \
+        ::pybind11::detail::npy_format_descriptor<Type>::register_dtype(                          \
+            ::std::vector<::pybind11::detail::field_descriptor>{                                  \
+                PYBIND11_MAP2_LIST(PYBIND11_FIELD_DESCRIPTOR_EX, Type, __VA_ARGS__)})
 
 #endif // __CLION_IDE__
 
@@ -1277,10 +1539,10 @@ class common_iterator {
     using value_type = container_type::value_type;
     using size_type = container_type::size_type;
 
-    common_iterator() : p_ptr(0), m_strides() {}
+    common_iterator() : m_strides() {}
 
-    common_iterator(void* ptr, const container_type& strides, const container_type& shape)
-        : p_ptr(reinterpret_cast<char*>(ptr)), m_strides(strides.size()) {
+    common_iterator(void *ptr, const container_type &strides, const container_type &shape)
+        : p_ptr(reinterpret_cast<char *>(ptr)), m_strides(strides.size()) {
         m_strides.back() = static_cast<value_type>(strides.back());
         for (size_type i = m_strides.size() - 1; i != 0; --i) {
             size_type j = i - 1;
@@ -1289,56 +1551,52 @@ class common_iterator {
         }
     }
 
-    void increment(size_type dim) {
-        p_ptr += m_strides[dim];
-    }
+    void increment(size_type dim) { p_ptr += m_strides[dim]; }
 
-    void* data() const {
-        return p_ptr;
-    }
+    void *data() const { return p_ptr; }
 
 private:
-    char* p_ptr;
+    char *p_ptr{nullptr};
     container_type m_strides;
 };
 
-template <size_t N> class multi_array_iterator {
+template <size_t N>
+class multi_array_iterator {
 public:
     using container_type = std::vector<ssize_t>;
 
-    multi_array_iterator(const std::array<buffer_info, N> &buffers,
-                         const container_type &shape)
-        : m_shape(shape.size()), m_index(shape.size(), 0),
-          m_common_iterator() {
+    multi_array_iterator(const std::array<buffer_info, N> &buffers, const container_type &shape)
+        : m_shape(shape.size()), m_index(shape.size(), 0), m_common_iterator() {
 
         // Manual copy to avoid conversion warning if using std::copy
-        for (size_t i = 0; i < shape.size(); ++i)
+        for (size_t i = 0; i < shape.size(); ++i) {
             m_shape[i] = shape[i];
+        }
 
         container_type strides(shape.size());
-        for (size_t i = 0; i < N; ++i)
+        for (size_t i = 0; i < N; ++i) {
             init_common_iterator(buffers[i], shape, m_common_iterator[i], strides);
+        }
     }
 
-    multi_array_iterator& operator++() {
+    multi_array_iterator &operator++() {
         for (size_t j = m_index.size(); j != 0; --j) {
             size_t i = j - 1;
             if (++m_index[i] != m_shape[i]) {
                 increment_common_iterator(i);
                 break;
-            } else {
-                m_index[i] = 0;
             }
+            m_index[i] = 0;
         }
         return *this;
     }
 
-    template <size_t K, class T = void> T* data() const {
-        return reinterpret_cast<T*>(m_common_iterator[K].data());
+    template <size_t K, class T = void>
+    T *data() const {
+        return reinterpret_cast<T *>(m_common_iterator[K].data());
     }
 
 private:
-
     using common_iter = common_iterator;
 
     void init_common_iterator(const buffer_info &buffer,
@@ -1351,10 +1609,11 @@ template <size_t N> class multi_array_iterator {
         auto strides_iter = strides.rbegin();
 
         while (buffer_shape_iter != buffer.shape.rend()) {
-            if (*shape_iter == *buffer_shape_iter)
+            if (*shape_iter == *buffer_shape_iter) {
                 *strides_iter = *buffer_strides_iter;
-            else
+            } else {
                 *strides_iter = 0;
+            }
 
             ++buffer_shape_iter;
             ++buffer_strides_iter;
@@ -1367,8 +1626,9 @@ template <size_t N> class multi_array_iterator {
     }
 
     void increment_common_iterator(size_t dim) {
-        for (auto &iter : m_common_iterator)
+        for (auto &iter : m_common_iterator) {
             iter.increment(dim);
+        }
     }
 
     container_type m_shape;
@@ -1378,60 +1638,71 @@ template <size_t N> class multi_array_iterator {
 
 enum class broadcast_trivial { non_trivial, c_trivial, f_trivial };
 
-// Populates the shape and number of dimensions for the set of buffers.  Returns a broadcast_trivial
-// enum value indicating whether the broadcast is "trivial"--that is, has each buffer being either a
-// singleton or a full-size, C-contiguous (`c_trivial`) or Fortran-contiguous (`f_trivial`) storage
-// buffer; returns `non_trivial` otherwise.
+// Populates the shape and number of dimensions for the set of buffers.  Returns a
+// broadcast_trivial enum value indicating whether the broadcast is "trivial"--that is, has each
+// buffer being either a singleton or a full-size, C-contiguous (`c_trivial`) or Fortran-contiguous
+// (`f_trivial`) storage buffer; returns `non_trivial` otherwise.
 template <size_t N>
-broadcast_trivial broadcast(const std::array<buffer_info, N> &buffers, ssize_t &ndim, std::vector<ssize_t> &shape) {
-    ndim = std::accumulate(buffers.begin(), buffers.end(), ssize_t(0), [](ssize_t res, const buffer_info &buf) {
-        return std::max(res, buf.ndim);
-    });
+broadcast_trivial
+broadcast(const std::array<buffer_info, N> &buffers, ssize_t &ndim, std::vector<ssize_t> &shape) {
+    ndim = std::accumulate(
+        buffers.begin(), buffers.end(), ssize_t(0), [](ssize_t res, const buffer_info &buf) {
+            return std::max(res, buf.ndim);
+        });
 
     shape.clear();
     shape.resize((size_t) ndim, 1);
 
-    // Figure out the output size, and make sure all input arrays conform (i.e. are either size 1 or
-    // the full size).
+    // Figure out the output size, and make sure all input arrays conform (i.e. are either size 1
+    // or the full size).
     for (size_t i = 0; i < N; ++i) {
         auto res_iter = shape.rbegin();
         auto end = buffers[i].shape.rend();
-        for (auto shape_iter = buffers[i].shape.rbegin(); shape_iter != end; ++shape_iter, ++res_iter) {
+        for (auto shape_iter = buffers[i].shape.rbegin(); shape_iter != end;
+             ++shape_iter, ++res_iter) {
             const auto &dim_size_in = *shape_iter;
             auto &dim_size_out = *res_iter;
 
-            // Each input dimension can either be 1 or `n`, but `n` values must match across buffers
-            if (dim_size_out == 1)
+            // Each input dimension can either be 1 or `n`, but `n` values must match across
+            // buffers
+            if (dim_size_out == 1) {
                 dim_size_out = dim_size_in;
-            else if (dim_size_in != 1 && dim_size_in != dim_size_out)
+            } else if (dim_size_in != 1 && dim_size_in != dim_size_out) {
                 pybind11_fail("pybind11::vectorize: incompatible size/dimension of inputs!");
+            }
         }
     }
 
     bool trivial_broadcast_c = true;
     bool trivial_broadcast_f = true;
     for (size_t i = 0; i < N && (trivial_broadcast_c || trivial_broadcast_f); ++i) {
-        if (buffers[i].size == 1)
+        if (buffers[i].size == 1) {
             continue;
+        }
 
         // Require the same number of dimensions:
-        if (buffers[i].ndim != ndim)
+        if (buffers[i].ndim != ndim) {
             return broadcast_trivial::non_trivial;
+        }
 
         // Require all dimensions be full-size:
-        if (!std::equal(buffers[i].shape.cbegin(), buffers[i].shape.cend(), shape.cbegin()))
+        if (!std::equal(buffers[i].shape.cbegin(), buffers[i].shape.cend(), shape.cbegin())) {
             return broadcast_trivial::non_trivial;
+        }
 
         // Check for C contiguity (but only if previous inputs were also C contiguous)
         if (trivial_broadcast_c) {
             ssize_t expect_stride = buffers[i].itemsize;
             auto end = buffers[i].shape.crend();
-            for (auto shape_iter = buffers[i].shape.crbegin(), stride_iter = buffers[i].strides.crbegin();
-                    trivial_broadcast_c && shape_iter != end; ++shape_iter, ++stride_iter) {
-                if (expect_stride == *stride_iter)
+            for (auto shape_iter = buffers[i].shape.crbegin(),
+                      stride_iter = buffers[i].strides.crbegin();
+                 trivial_broadcast_c && shape_iter != end;
+                 ++shape_iter, ++stride_iter) {
+                if (expect_stride == *stride_iter) {
                     expect_stride *= *shape_iter;
-                else
+                } else {
                     trivial_broadcast_c = false;
+                }
             }
         }
 
@@ -1439,61 +1710,61 @@ broadcast_trivial broadcast(const std::array<buffer_info, N> &buffers, ssize_t &
         if (trivial_broadcast_f) {
             ssize_t expect_stride = buffers[i].itemsize;
             auto end = buffers[i].shape.cend();
-            for (auto shape_iter = buffers[i].shape.cbegin(), stride_iter = buffers[i].strides.cbegin();
-                    trivial_broadcast_f && shape_iter != end; ++shape_iter, ++stride_iter) {
-                if (expect_stride == *stride_iter)
+            for (auto shape_iter = buffers[i].shape.cbegin(),
+                      stride_iter = buffers[i].strides.cbegin();
+                 trivial_broadcast_f && shape_iter != end;
+                 ++shape_iter, ++stride_iter) {
+                if (expect_stride == *stride_iter) {
                     expect_stride *= *shape_iter;
-                else
+                } else {
                     trivial_broadcast_f = false;
+                }
             }
         }
     }
 
-    return
-        trivial_broadcast_c ? broadcast_trivial::c_trivial :
-        trivial_broadcast_f ? broadcast_trivial::f_trivial :
-        broadcast_trivial::non_trivial;
+    return trivial_broadcast_c   ? broadcast_trivial::c_trivial
+           : trivial_broadcast_f ? broadcast_trivial::f_trivial
+                                 : broadcast_trivial::non_trivial;
 }
 
 template <typename T>
 struct vectorize_arg {
-    static_assert(!std::is_rvalue_reference<T>::value, "Functions with rvalue reference arguments cannot be vectorized");
+    static_assert(!std::is_rvalue_reference<T>::value,
+                  "Functions with rvalue reference arguments cannot be vectorized");
     // The wrapped function gets called with this type:
     using call_type = remove_reference_t<T>;
     // Is this a vectorized argument?
-    static constexpr bool vectorize =
-        satisfies_any_of<call_type, std::is_arithmetic, is_complex, is_pod>::value &&
-        satisfies_none_of<call_type, std::is_pointer, std::is_array, is_std_array, std::is_enum>::value &&
-        (!std::is_reference<T>::value ||
-         (std::is_lvalue_reference<T>::value && std::is_const<call_type>::value));
+    static constexpr bool vectorize
+        = satisfies_any_of<call_type, std::is_arithmetic, is_complex, is_pod>::value
+          && satisfies_none_of<call_type,
+                               std::is_pointer,
+                               std::is_array,
+                               is_std_array,
+                               std::is_enum>::value
+          && (!std::is_reference<T>::value
+              || (std::is_lvalue_reference<T>::value && std::is_const<call_type>::value));
     // Accept this type: an array for vectorized types, otherwise the type as-is:
     using type = conditional_t<vectorize, array_t<remove_cv_t<call_type>, array::forcecast>, T>;
 };
 
-
 // py::vectorize when a return type is present
 template <typename Func, typename Return, typename... Args>
 struct vectorize_returned_array {
     using Type = array_t<Return>;
 
     static Type create(broadcast_trivial trivial, const std::vector<ssize_t> &shape) {
-        if (trivial == broadcast_trivial::f_trivial)
+        if (trivial == broadcast_trivial::f_trivial) {
             return array_t<Return, array::f_style>(shape);
-        else
-            return array_t<Return>(shape);
+        }
+        return array_t<Return>(shape);
     }
 
-    static Return *mutable_data(Type &array) {
-        return array.mutable_data();
-    }
+    static Return *mutable_data(Type &array) { return array.mutable_data(); }
 
-    static Return call(Func &f, Args &... args) {
-        return f(args...);
-    }
+    static Return call(Func &f, Args &...args) { return f(args...); }
 
-    static void call(Return *out, size_t i, Func &f, Args &... args) {
-        out[i] = f(args...);
-    }
+    static void call(Return *out, size_t i, Func &f, Args &...args) { out[i] = f(args...); }
 };
 
 // py::vectorize when a return type is not present
@@ -1501,25 +1772,18 @@ template <typename Func, typename... Args>
 struct vectorize_returned_array<Func, void, Args...> {
     using Type = none;
 
-    static Type create(broadcast_trivial, const std::vector<ssize_t> &) {
-        return none();
-    }
+    static Type create(broadcast_trivial, const std::vector<ssize_t> &) { return none(); }
 
-    static void *mutable_data(Type &) {
-        return nullptr;
-    }
+    static void *mutable_data(Type &) { return nullptr; }
 
-    static detail::void_type call(Func &f, Args &... args) {
+    static detail::void_type call(Func &f, Args &...args) {
         f(args...);
         return {};
     }
 
-    static void call(void *, size_t, Func &f, Args &... args) {
-        f(args...);
-    }
+    static void call(void *, size_t, Func &f, Args &...args) { f(args...); }
 };
 
-
 template <typename Func, typename Return, typename... Args>
 struct vectorize_helper {
 
@@ -1532,12 +1796,16 @@ struct vectorize_helper {
 
     static constexpr size_t N = sizeof...(Args);
     static constexpr size_t NVectorized = constexpr_sum(vectorize_arg<Args>::vectorize...);
-    static_assert(NVectorized >= 1,
-            "pybind11::vectorize(...) requires a function with at least one vectorizable argument");
+    static_assert(
+        NVectorized >= 1,
+        "pybind11::vectorize(...) requires a function with at least one vectorizable argument");
 
 public:
-    template <typename T>
-    explicit vectorize_helper(T &&f) : f(std::forward<T>(f)) { }
+    template <typename T,
+              // SFINAE to prevent shadowing the copy constructor.
+              typename = detail::enable_if_t<
+                  !std::is_same<vectorize_helper, typename std::decay<T>::type>::value>>
+    explicit vectorize_helper(T &&f) : f(std::forward<T>(f)) {}
 
     object operator()(typename vectorize_arg<Args>::type... args) {
         return run(args...,
@@ -1549,10 +1817,11 @@ struct vectorize_helper {
 private:
     remove_reference_t<Func> f;
 
-    // Internal compiler error in MSVC 19.16.27025.1 (Visual Studio 2017 15.9.4), when compiling with "/permissive-" flag
-    // when arg_call_types is manually inlined.
+    // Internal compiler error in MSVC 19.16.27025.1 (Visual Studio 2017 15.9.4), when compiling
+    // with "/permissive-" flag when arg_call_types is manually inlined.
     using arg_call_types = std::tuple<typename vectorize_arg<Args>::call_type...>;
-    template <size_t Index> using param_n_t = typename std::tuple_element<Index, arg_call_types>::type;
+    template <size_t Index>
+    using param_n_t = typename std::tuple_element<Index, arg_call_types>::type;
 
     using returned_array = vectorize_returned_array<Func, Return, Args...>;
 
@@ -1563,17 +1832,20 @@ struct vectorize_helper {
     //     - BIndex is a incremental sequence (beginning at 0) of the same size as VIndex, so that
     //       we can store vectorized buffer_infos in an array (argument VIndex has its buffer at
     //       index BIndex in the array).
-    template <size_t... Index, size_t... VIndex, size_t... BIndex> object run(
-            typename vectorize_arg<Args>::type &...args,
-            index_sequence<Index...> i_seq, index_sequence<VIndex...> vi_seq, index_sequence<BIndex...> bi_seq) {
+    template <size_t... Index, size_t... VIndex, size_t... BIndex>
+    object run(typename vectorize_arg<Args>::type &...args,
+               index_sequence<Index...> i_seq,
+               index_sequence<VIndex...> vi_seq,
+               index_sequence<BIndex...> bi_seq) {
 
         // Pointers to values the function was called with; the vectorized ones set here will start
         // out as array_t<T> pointers, but they will be changed them to T pointers before we make
         // call the wrapped function.  Non-vectorized pointers are left as-is.
-        std::array<void *, N> params{{ &args... }};
+        std::array<void *, N> params{{&args...}};
 
         // The array of `buffer_info`s of vectorized arguments:
-        std::array<buffer_info, NVectorized> buffers{{ reinterpret_cast<array *>(params[VIndex])->request()... }};
+        std::array<buffer_info, NVectorized> buffers{
+            {reinterpret_cast<array *>(params[VIndex])->request()...}};
 
         /* Determine dimensions parameters of output array */
         ssize_t nd = 0;
@@ -1581,27 +1853,39 @@ struct vectorize_helper {
         auto trivial = broadcast(buffers, nd, shape);
         auto ndim = (size_t) nd;
 
-        size_t size = std::accumulate(shape.begin(), shape.end(), (size_t) 1, std::multiplies<size_t>());
+        size_t size
+            = std::accumulate(shape.begin(), shape.end(), (size_t) 1, std::multiplies<size_t>());
 
         // If all arguments are 0-dimension arrays (i.e. single values) return a plain value (i.e.
         // not wrapped in an array).
         if (size == 1 && ndim == 0) {
             PYBIND11_EXPAND_SIDE_EFFECTS(params[VIndex] = buffers[BIndex].ptr);
-            return cast(returned_array::call(f, *reinterpret_cast<param_n_t<Index> *>(params[Index])...));
+            return cast(
+                returned_array::call(f, *reinterpret_cast<param_n_t<Index> *>(params[Index])...));
         }
 
         auto result = returned_array::create(trivial, shape);
+#ifdef PYBIND11_DETECTED_CLANG_WITH_MISLEADING_CALL_STD_MOVE_EXPLICITLY_WARNING
+#    pragma clang diagnostic push
+#    pragma clang diagnostic ignored "-Wreturn-std-move"
+#endif
 
-        if (size == 0) return std::move(result);
+        if (size == 0) {
+            return result;
+        }
 
         /* Call the function */
-        auto mutable_data = returned_array::mutable_data(result);
-        if (trivial == broadcast_trivial::non_trivial)
+        auto *mutable_data = returned_array::mutable_data(result);
+        if (trivial == broadcast_trivial::non_trivial) {
             apply_broadcast(buffers, params, mutable_data, size, shape, i_seq, vi_seq, bi_seq);
-        else
+        } else {
             apply_trivial(buffers, params, mutable_data, size, i_seq, vi_seq, bi_seq);
+        }
 
-        return std::move(result);
+        return result;
+#ifdef PYBIND11_DETECTED_CLANG_WITH_MISLEADING_CALL_STD_MOVE_EXPLICITLY_WARNING
+#    pragma clang diagnostic pop
+#endif
     }
 
     template <size_t... Index, size_t... VIndex, size_t... BIndex>
@@ -1609,21 +1893,24 @@ struct vectorize_helper {
                        std::array<void *, N> &params,
                        Return *out,
                        size_t size,
-                       index_sequence<Index...>, index_sequence<VIndex...>, index_sequence<BIndex...>) {
+                       index_sequence<Index...>,
+                       index_sequence<VIndex...>,
+                       index_sequence<BIndex...>) {
 
         // Initialize an array of mutable byte references and sizes with references set to the
         // appropriate pointer in `params`; as we iterate, we'll increment each pointer by its size
         // (except for singletons, which get an increment of 0).
-        std::array<std::pair<unsigned char *&, const size_t>, NVectorized> vecparams{{
-            std::pair<unsigned char *&, const size_t>(
-                    reinterpret_cast<unsigned char *&>(params[VIndex] = buffers[BIndex].ptr),
-                    buffers[BIndex].size == 1 ? 0 : sizeof(param_n_t<VIndex>)
-            )...
-        }};
+        std::array<std::pair<unsigned char *&, const size_t>, NVectorized> vecparams{
+            {std::pair<unsigned char *&, const size_t>(
+                reinterpret_cast<unsigned char *&>(params[VIndex] = buffers[BIndex].ptr),
+                buffers[BIndex].size == 1 ? 0 : sizeof(param_n_t<VIndex>))...}};
 
         for (size_t i = 0; i < size; ++i) {
-            returned_array::call(out, i, f, *reinterpret_cast<param_n_t<Index> *>(params[Index])...);
-            for (auto &x : vecparams) x.first += x.second;
+            returned_array::call(
+                out, i, f, *reinterpret_cast<param_n_t<Index> *>(params[Index])...);
+            for (auto &x : vecparams) {
+                x.first += x.second;
+            }
         }
     }
 
@@ -1633,61 +1920,72 @@ struct vectorize_helper {
                          Return *out,
                          size_t size,
                          const std::vector<ssize_t> &output_shape,
-                         index_sequence<Index...>, index_sequence<VIndex...>, index_sequence<BIndex...>) {
+                         index_sequence<Index...>,
+                         index_sequence<VIndex...>,
+                         index_sequence<BIndex...>) {
 
         multi_array_iterator<NVectorized> input_iter(buffers, output_shape);
 
         for (size_t i = 0; i < size; ++i, ++input_iter) {
-            PYBIND11_EXPAND_SIDE_EFFECTS((
-                params[VIndex] = input_iter.template data<BIndex>()
-            ));
-            returned_array::call(out, i, f, *reinterpret_cast<param_n_t<Index> *>(std::get<Index>(params))...);
+            PYBIND11_EXPAND_SIDE_EFFECTS((params[VIndex] = input_iter.template data<BIndex>()));
+            returned_array::call(
+                out, i, f, *reinterpret_cast<param_n_t<Index> *>(std::get<Index>(params))...);
         }
     }
 };
 
 template <typename Func, typename Return, typename... Args>
-vectorize_helper<Func, Return, Args...>
-vectorize_extractor(const Func &f, Return (*) (Args ...)) {
+vectorize_helper<Func, Return, Args...> vectorize_extractor(const Func &f, Return (*)(Args...)) {
     return detail::vectorize_helper<Func, Return, Args...>(f);
 }
 
-template <typename T, int Flags> struct handle_type_name<array_t<T, Flags>> {
-    static constexpr auto name = _("numpy.ndarray[") + npy_format_descriptor<T>::name + _("]");
+template <typename T, int Flags>
+struct handle_type_name<array_t<T, Flags>> {
+    static constexpr auto name
+        = const_name("numpy.ndarray[") + npy_format_descriptor<T>::name + const_name("]");
 };
 
 PYBIND11_NAMESPACE_END(detail)
 
 // Vanilla pointer vectorizer:
 template <typename Return, typename... Args>
-detail::vectorize_helper<Return (*)(Args...), Return, Args...>
-vectorize(Return (*f) (Args ...)) {
+detail::vectorize_helper<Return (*)(Args...), Return, Args...> vectorize(Return (*f)(Args...)) {
     return detail::vectorize_helper<Return (*)(Args...), Return, Args...>(f);
 }
 
 // lambda vectorizer:
 template <typename Func, detail::enable_if_t<detail::is_lambda<Func>::value, int> = 0>
-auto vectorize(Func &&f) -> decltype(
-        detail::vectorize_extractor(std::forward<Func>(f), (detail::function_signature_t<Func> *) nullptr)) {
-    return detail::vectorize_extractor(std::forward<Func>(f), (detail::function_signature_t<Func> *) nullptr);
+auto vectorize(Func &&f)
+    -> decltype(detail::vectorize_extractor(std::forward<Func>(f),
+                                            (detail::function_signature_t<Func> *) nullptr)) {
+    return detail::vectorize_extractor(std::forward<Func>(f),
+                                       (detail::function_signature_t<Func> *) nullptr);
 }
 
 // Vectorize a class method (non-const):
-template <typename Return, typename Class, typename... Args,
-          typename Helper = detail::vectorize_helper<decltype(std::mem_fn(std::declval<Return (Class::*)(Args...)>())), Return, Class *, Args...>>
+template <typename Return,
+          typename Class,
+          typename... Args,
+          typename Helper = detail::vectorize_helper<
+              decltype(std::mem_fn(std::declval<Return (Class::*)(Args...)>())),
+              Return,
+              Class *,
+              Args...>>
 Helper vectorize(Return (Class::*f)(Args...)) {
     return Helper(std::mem_fn(f));
 }
 
 // Vectorize a class method (const):
-template <typename Return, typename Class, typename... Args,
-          typename Helper = detail::vectorize_helper<decltype(std::mem_fn(std::declval<Return (Class::*)(Args...) const>())), Return, const Class *, Args...>>
+template <typename Return,
+          typename Class,
+          typename... Args,
+          typename Helper = detail::vectorize_helper<
+              decltype(std::mem_fn(std::declval<Return (Class::*)(Args...) const>())),
+              Return,
+              const Class *,
+              Args...>>
 Helper vectorize(Return (Class::*f)(Args...) const) {
     return Helper(std::mem_fn(f));
 }
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
-
-#if defined(_MSC_VER)
-#pragma warning(pop)
-#endif
diff --git a/3rdparty/pybind11/include/pybind11/operators.h b/3rdparty/pybind11/include/pybind11/operators.h
index 086cb4cfd8..a0c3b78d65 100644
--- a/3rdparty/pybind11/include/pybind11/operators.h
+++ b/3rdparty/pybind11/include/pybind11/operators.h
@@ -11,24 +11,55 @@
 
 #include "pybind11.h"
 
-#if defined(__clang__) && !defined(__INTEL_COMPILER)
-#  pragma clang diagnostic ignored "-Wunsequenced" // multiple unsequenced modifications to 'self' (when using def(py::self OP Type()))
-#elif defined(_MSC_VER)
-#  pragma warning(push)
-#  pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#endif
-
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 /// Enumeration with all supported operator types
 enum op_id : int {
-    op_add, op_sub, op_mul, op_div, op_mod, op_divmod, op_pow, op_lshift,
-    op_rshift, op_and, op_xor, op_or, op_neg, op_pos, op_abs, op_invert,
-    op_int, op_long, op_float, op_str, op_cmp, op_gt, op_ge, op_lt, op_le,
-    op_eq, op_ne, op_iadd, op_isub, op_imul, op_idiv, op_imod, op_ilshift,
-    op_irshift, op_iand, op_ixor, op_ior, op_complex, op_bool, op_nonzero,
-    op_repr, op_truediv, op_itruediv, op_hash
+    op_add,
+    op_sub,
+    op_mul,
+    op_div,
+    op_mod,
+    op_divmod,
+    op_pow,
+    op_lshift,
+    op_rshift,
+    op_and,
+    op_xor,
+    op_or,
+    op_neg,
+    op_pos,
+    op_abs,
+    op_invert,
+    op_int,
+    op_long,
+    op_float,
+    op_str,
+    op_cmp,
+    op_gt,
+    op_ge,
+    op_lt,
+    op_le,
+    op_eq,
+    op_ne,
+    op_iadd,
+    op_isub,
+    op_imul,
+    op_idiv,
+    op_imod,
+    op_ilshift,
+    op_irshift,
+    op_iand,
+    op_ixor,
+    op_ior,
+    op_complex,
+    op_bool,
+    op_nonzero,
+    op_repr,
+    op_truediv,
+    op_itruediv,
+    op_hash
 };
 
 enum op_type : int {
@@ -37,125 +68,126 @@ enum op_type : int {
     op_u  /* unary operator */
 };
 
-struct self_t { };
+struct self_t {};
 static const self_t self = self_t();
 
 /// Type for an unused type slot
-struct undefined_t { };
+struct undefined_t {};
 
 /// Don't warn about an unused variable
 inline self_t __self() { return self; }
 
 /// base template of operator implementations
-template <op_id, op_type, typename B, typename L, typename R> struct op_impl { };
+template <op_id, op_type, typename B, typename L, typename R>
+struct op_impl {};
 
 /// Operator implementation generator
-template <op_id id, op_type ot, typename L, typename R> struct op_ {
-    template <typename Class, typename... Extra> void execute(Class &cl, const Extra&... extra) const {
+template <op_id id, op_type ot, typename L, typename R>
+struct op_ {
+    template <typename Class, typename... Extra>
+    void execute(Class &cl, const Extra &...extra) const {
         using Base = typename Class::type;
         using L_type = conditional_t<std::is_same<L, self_t>::value, Base, L>;
         using R_type = conditional_t<std::is_same<R, self_t>::value, Base, R>;
         using op = op_impl<id, ot, Base, L_type, R_type>;
         cl.def(op::name(), &op::execute, is_operator(), extra...);
-        #if PY_MAJOR_VERSION < 3
-        if (id == op_truediv || id == op_itruediv)
-            cl.def(id == op_itruediv ? "__idiv__" : ot == op_l ? "__div__" : "__rdiv__",
-                    &op::execute, is_operator(), extra...);
-        #endif
     }
-    template <typename Class, typename... Extra> void execute_cast(Class &cl, const Extra&... extra) const {
+    template <typename Class, typename... Extra>
+    void execute_cast(Class &cl, const Extra &...extra) const {
         using Base = typename Class::type;
         using L_type = conditional_t<std::is_same<L, self_t>::value, Base, L>;
         using R_type = conditional_t<std::is_same<R, self_t>::value, Base, R>;
         using op = op_impl<id, ot, Base, L_type, R_type>;
         cl.def(op::name(), &op::execute_cast, is_operator(), extra...);
-        #if PY_MAJOR_VERSION < 3
-        if (id == op_truediv || id == op_itruediv)
-            cl.def(id == op_itruediv ? "__idiv__" : ot == op_l ? "__div__" : "__rdiv__",
-                    &op::execute, is_operator(), extra...);
-        #endif
     }
 };
 
-#define PYBIND11_BINARY_OPERATOR(id, rid, op, expr)                                    \
-template <typename B, typename L, typename R> struct op_impl<op_##id, op_l, B, L, R> { \
-    static char const* name() { return "__" #id "__"; }                                \
-    static auto execute(const L &l, const R &r) -> decltype(expr) { return (expr); }   \
-    static B execute_cast(const L &l, const R &r) { return B(expr); }                  \
-};                                                                                     \
-template <typename B, typename L, typename R> struct op_impl<op_##id, op_r, B, L, R> { \
-    static char const* name() { return "__" #rid "__"; }                               \
-    static auto execute(const R &r, const L &l) -> decltype(expr) { return (expr); }   \
-    static B execute_cast(const R &r, const L &l) { return B(expr); }                  \
-};                                                                                     \
-inline op_<op_##id, op_l, self_t, self_t> op(const self_t &, const self_t &) {         \
-    return op_<op_##id, op_l, self_t, self_t>();                                       \
-}                                                                                      \
-template <typename T> op_<op_##id, op_l, self_t, T> op(const self_t &, const T &) {    \
-    return op_<op_##id, op_l, self_t, T>();                                            \
-}                                                                                      \
-template <typename T> op_<op_##id, op_r, T, self_t> op(const T &, const self_t &) {    \
-    return op_<op_##id, op_r, T, self_t>();                                            \
-}
-
-#define PYBIND11_INPLACE_OPERATOR(id, op, expr)                                        \
-template <typename B, typename L, typename R> struct op_impl<op_##id, op_l, B, L, R> { \
-    static char const* name() { return "__" #id "__"; }                                \
-    static auto execute(L &l, const R &r) -> decltype(expr) { return expr; }           \
-    static B execute_cast(L &l, const R &r) { return B(expr); }                        \
-};                                                                                     \
-template <typename T> op_<op_##id, op_l, self_t, T> op(const self_t &, const T &) {    \
-    return op_<op_##id, op_l, self_t, T>();                                            \
-}
-
-#define PYBIND11_UNARY_OPERATOR(id, op, expr)                                          \
-template <typename B, typename L> struct op_impl<op_##id, op_u, B, L, undefined_t> {   \
-    static char const* name() { return "__" #id "__"; }                                \
-    static auto execute(const L &l) -> decltype(expr) { return expr; }                 \
-    static B execute_cast(const L &l) { return B(expr); }                              \
-};                                                                                     \
-inline op_<op_##id, op_u, self_t, undefined_t> op(const self_t &) {                    \
-    return op_<op_##id, op_u, self_t, undefined_t>();                                  \
-}
-
-PYBIND11_BINARY_OPERATOR(sub,       rsub,         operator-,    l - r)
-PYBIND11_BINARY_OPERATOR(add,       radd,         operator+,    l + r)
-PYBIND11_BINARY_OPERATOR(mul,       rmul,         operator*,    l * r)
-PYBIND11_BINARY_OPERATOR(truediv,   rtruediv,     operator/,    l / r)
-PYBIND11_BINARY_OPERATOR(mod,       rmod,         operator%,    l % r)
-PYBIND11_BINARY_OPERATOR(lshift,    rlshift,      operator<<,   l << r)
-PYBIND11_BINARY_OPERATOR(rshift,    rrshift,      operator>>,   l >> r)
-PYBIND11_BINARY_OPERATOR(and,       rand,         operator&,    l & r)
-PYBIND11_BINARY_OPERATOR(xor,       rxor,         operator^,    l ^ r)
-PYBIND11_BINARY_OPERATOR(eq,        eq,           operator==,   l == r)
-PYBIND11_BINARY_OPERATOR(ne,        ne,           operator!=,   l != r)
-PYBIND11_BINARY_OPERATOR(or,        ror,          operator|,    l | r)
-PYBIND11_BINARY_OPERATOR(gt,        lt,           operator>,    l > r)
-PYBIND11_BINARY_OPERATOR(ge,        le,           operator>=,   l >= r)
-PYBIND11_BINARY_OPERATOR(lt,        gt,           operator<,    l < r)
-PYBIND11_BINARY_OPERATOR(le,        ge,           operator<=,   l <= r)
-//PYBIND11_BINARY_OPERATOR(pow,       rpow,         pow,          std::pow(l,  r))
-PYBIND11_INPLACE_OPERATOR(iadd,     operator+=,   l += r)
-PYBIND11_INPLACE_OPERATOR(isub,     operator-=,   l -= r)
-PYBIND11_INPLACE_OPERATOR(imul,     operator*=,   l *= r)
-PYBIND11_INPLACE_OPERATOR(itruediv, operator/=,   l /= r)
-PYBIND11_INPLACE_OPERATOR(imod,     operator%=,   l %= r)
-PYBIND11_INPLACE_OPERATOR(ilshift,  operator<<=,  l <<= r)
-PYBIND11_INPLACE_OPERATOR(irshift,  operator>>=,  l >>= r)
-PYBIND11_INPLACE_OPERATOR(iand,     operator&=,   l &= r)
-PYBIND11_INPLACE_OPERATOR(ixor,     operator^=,   l ^= r)
-PYBIND11_INPLACE_OPERATOR(ior,      operator|=,   l |= r)
-PYBIND11_UNARY_OPERATOR(neg,        operator-,    -l)
-PYBIND11_UNARY_OPERATOR(pos,        operator+,    +l)
+#define PYBIND11_BINARY_OPERATOR(id, rid, op, expr)                                               \
+    template <typename B, typename L, typename R>                                                 \
+    struct op_impl<op_##id, op_l, B, L, R> {                                                      \
+        static char const *name() { return "__" #id "__"; }                                       \
+        static auto execute(const L &l, const R &r) -> decltype(expr) { return (expr); }          \
+        static B execute_cast(const L &l, const R &r) { return B(expr); }                         \
+    };                                                                                            \
+    template <typename B, typename L, typename R>                                                 \
+    struct op_impl<op_##id, op_r, B, L, R> {                                                      \
+        static char const *name() { return "__" #rid "__"; }                                      \
+        static auto execute(const R &r, const L &l) -> decltype(expr) { return (expr); }          \
+        static B execute_cast(const R &r, const L &l) { return B(expr); }                         \
+    };                                                                                            \
+    inline op_<op_##id, op_l, self_t, self_t> op(const self_t &, const self_t &) {                \
+        return op_<op_##id, op_l, self_t, self_t>();                                              \
+    }                                                                                             \
+    template <typename T>                                                                         \
+    op_<op_##id, op_l, self_t, T> op(const self_t &, const T &) {                                 \
+        return op_<op_##id, op_l, self_t, T>();                                                   \
+    }                                                                                             \
+    template <typename T>                                                                         \
+    op_<op_##id, op_r, T, self_t> op(const T &, const self_t &) {                                 \
+        return op_<op_##id, op_r, T, self_t>();                                                   \
+    }
+
+#define PYBIND11_INPLACE_OPERATOR(id, op, expr)                                                   \
+    template <typename B, typename L, typename R>                                                 \
+    struct op_impl<op_##id, op_l, B, L, R> {                                                      \
+        static char const *name() { return "__" #id "__"; }                                       \
+        static auto execute(L &l, const R &r) -> decltype(expr) { return expr; }                  \
+        static B execute_cast(L &l, const R &r) { return B(expr); }                               \
+    };                                                                                            \
+    template <typename T>                                                                         \
+    op_<op_##id, op_l, self_t, T> op(const self_t &, const T &) {                                 \
+        return op_<op_##id, op_l, self_t, T>();                                                   \
+    }
+
+#define PYBIND11_UNARY_OPERATOR(id, op, expr)                                                     \
+    template <typename B, typename L>                                                             \
+    struct op_impl<op_##id, op_u, B, L, undefined_t> {                                            \
+        static char const *name() { return "__" #id "__"; }                                       \
+        static auto execute(const L &l) -> decltype(expr) { return expr; }                        \
+        static B execute_cast(const L &l) { return B(expr); }                                     \
+    };                                                                                            \
+    inline op_<op_##id, op_u, self_t, undefined_t> op(const self_t &) {                           \
+        return op_<op_##id, op_u, self_t, undefined_t>();                                         \
+    }
+
+PYBIND11_BINARY_OPERATOR(sub, rsub, operator-, l - r)
+PYBIND11_BINARY_OPERATOR(add, radd, operator+, l + r)
+PYBIND11_BINARY_OPERATOR(mul, rmul, operator*, l *r)
+PYBIND11_BINARY_OPERATOR(truediv, rtruediv, operator/, l / r)
+PYBIND11_BINARY_OPERATOR(mod, rmod, operator%, l % r)
+PYBIND11_BINARY_OPERATOR(lshift, rlshift, operator<<, l << r)
+PYBIND11_BINARY_OPERATOR(rshift, rrshift, operator>>, l >> r)
+PYBIND11_BINARY_OPERATOR(and, rand, operator&, l &r)
+PYBIND11_BINARY_OPERATOR(xor, rxor, operator^, l ^ r)
+PYBIND11_BINARY_OPERATOR(eq, eq, operator==, l == r)
+PYBIND11_BINARY_OPERATOR(ne, ne, operator!=, l != r)
+PYBIND11_BINARY_OPERATOR(or, ror, operator|, l | r)
+PYBIND11_BINARY_OPERATOR(gt, lt, operator>, l > r)
+PYBIND11_BINARY_OPERATOR(ge, le, operator>=, l >= r)
+PYBIND11_BINARY_OPERATOR(lt, gt, operator<, l < r)
+PYBIND11_BINARY_OPERATOR(le, ge, operator<=, l <= r)
+// PYBIND11_BINARY_OPERATOR(pow,       rpow,         pow,          std::pow(l,  r))
+PYBIND11_INPLACE_OPERATOR(iadd, operator+=, l += r)
+PYBIND11_INPLACE_OPERATOR(isub, operator-=, l -= r)
+PYBIND11_INPLACE_OPERATOR(imul, operator*=, l *= r)
+PYBIND11_INPLACE_OPERATOR(itruediv, operator/=, l /= r)
+PYBIND11_INPLACE_OPERATOR(imod, operator%=, l %= r)
+PYBIND11_INPLACE_OPERATOR(ilshift, operator<<=, l <<= r)
+PYBIND11_INPLACE_OPERATOR(irshift, operator>>=, l >>= r)
+PYBIND11_INPLACE_OPERATOR(iand, operator&=, l &= r)
+PYBIND11_INPLACE_OPERATOR(ixor, operator^=, l ^= r)
+PYBIND11_INPLACE_OPERATOR(ior, operator|=, l |= r)
+PYBIND11_UNARY_OPERATOR(neg, operator-, -l)
+PYBIND11_UNARY_OPERATOR(pos, operator+, +l)
 // WARNING: This usage of `abs` should only be done for existing STL overloads.
 // Adding overloads directly in to the `std::` namespace is advised against:
 // https://en.cppreference.com/w/cpp/language/extending_std
-PYBIND11_UNARY_OPERATOR(abs,        abs,          std::abs(l))
-PYBIND11_UNARY_OPERATOR(hash,       hash,         std::hash<L>()(l))
-PYBIND11_UNARY_OPERATOR(invert,     operator~,    (~l))
-PYBIND11_UNARY_OPERATOR(bool,       operator!,    !!l)
-PYBIND11_UNARY_OPERATOR(int,        int_,         (int) l)
-PYBIND11_UNARY_OPERATOR(float,      float_,       (double) l)
+PYBIND11_UNARY_OPERATOR(abs, abs, std::abs(l))
+PYBIND11_UNARY_OPERATOR(hash, hash, std::hash<L>()(l))
+PYBIND11_UNARY_OPERATOR(invert, operator~, (~l))
+PYBIND11_UNARY_OPERATOR(bool, operator!, !!l)
+PYBIND11_UNARY_OPERATOR(int, int_, (int) l)
+PYBIND11_UNARY_OPERATOR(float, float_, (double) l)
 
 #undef PYBIND11_BINARY_OPERATOR
 #undef PYBIND11_INPLACE_OPERATOR
@@ -167,7 +199,3 @@ using detail::self;
 using detail::hash;
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
-
-#if defined(_MSC_VER)
-#  pragma warning(pop)
-#endif
diff --git a/3rdparty/pybind11/include/pybind11/options.h b/3rdparty/pybind11/include/pybind11/options.h
index d74db1c68d..1e493bdcc4 100644
--- a/3rdparty/pybind11/include/pybind11/options.h
+++ b/3rdparty/pybind11/include/pybind11/options.h
@@ -15,43 +15,54 @@ PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
 class options {
 public:
-
     // Default RAII constructor, which leaves settings as they currently are.
     options() : previous_state(global_state()) {}
 
     // Class is non-copyable.
-    options(const options&) = delete;
-    options& operator=(const options&) = delete;
+    options(const options &) = delete;
+    options &operator=(const options &) = delete;
 
     // Destructor, which restores settings that were in effect before.
-    ~options() {
-        global_state() = previous_state;
-    }
+    ~options() { global_state() = previous_state; }
 
     // Setter methods (affect the global state):
 
-    options& disable_user_defined_docstrings() & { global_state().show_user_defined_docstrings = false; return *this; }
+    options &disable_user_defined_docstrings() & {
+        global_state().show_user_defined_docstrings = false;
+        return *this;
+    }
 
-    options& enable_user_defined_docstrings() & { global_state().show_user_defined_docstrings = true; return *this; }
+    options &enable_user_defined_docstrings() & {
+        global_state().show_user_defined_docstrings = true;
+        return *this;
+    }
 
-    options& disable_function_signatures() & { global_state().show_function_signatures = false; return *this; }
+    options &disable_function_signatures() & {
+        global_state().show_function_signatures = false;
+        return *this;
+    }
 
-    options& enable_function_signatures() & { global_state().show_function_signatures = true; return *this; }
+    options &enable_function_signatures() & {
+        global_state().show_function_signatures = true;
+        return *this;
+    }
 
     // Getter methods (return the global state):
 
-    static bool show_user_defined_docstrings() { return global_state().show_user_defined_docstrings; }
+    static bool show_user_defined_docstrings() {
+        return global_state().show_user_defined_docstrings;
+    }
 
     static bool show_function_signatures() { return global_state().show_function_signatures; }
 
     // This type is not meant to be allocated on the heap.
-    void* operator new(size_t) = delete;
+    void *operator new(size_t) = delete;
 
 private:
-
     struct state {
-        bool show_user_defined_docstrings = true;  //< Include user-supplied texts in docstrings.
-        bool show_function_signatures = true;      //< Include auto-generated function signatures in docstrings.
+        bool show_user_defined_docstrings = true; //< Include user-supplied texts in docstrings.
+        bool show_function_signatures = true;     //< Include auto-generated function signatures
+                                                  //  in docstrings.
     };
 
     static state &global_state() {
diff --git a/3rdparty/pybind11/include/pybind11/pybind11.h b/3rdparty/pybind11/include/pybind11/pybind11.h
index e2ddda020b..c889dc4169 100644
--- a/3rdparty/pybind11/include/pybind11/pybind11.h
+++ b/3rdparty/pybind11/include/pybind11/pybind11.h
@@ -10,178 +10,245 @@
 
 #pragma once
 
-#if defined(__INTEL_COMPILER)
-#  pragma warning push
-#  pragma warning disable 68    // integer conversion resulted in a change of sign
-#  pragma warning disable 186   // pointless comparison of unsigned integer with zero
-#  pragma warning disable 878   // incompatible exception specifications
-#  pragma warning disable 1334  // the "template" keyword used for syntactic disambiguation may only be used within a template
-#  pragma warning disable 1682  // implicit conversion of a 64-bit integral type to a smaller integral type (potential portability problem)
-#  pragma warning disable 1786  // function "strdup" was declared deprecated
-#  pragma warning disable 1875  // offsetof applied to non-POD (Plain Old Data) types is nonstandard
-#  pragma warning disable 2196  // warning #2196: routine is both "inline" and "noinline"
-#elif defined(_MSC_VER)
-#  pragma warning(push)
-#  pragma warning(disable: 4100) // warning C4100: Unreferenced formal parameter
-#  pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#  pragma warning(disable: 4512) // warning C4512: Assignment operator was implicitly defined as deleted
-#  pragma warning(disable: 4800) // warning C4800: 'int': forcing value to bool 'true' or 'false' (performance warning)
-#  pragma warning(disable: 4996) // warning C4996: The POSIX name for this item is deprecated. Instead, use the ISO C and C++ conformant name
-#  pragma warning(disable: 4702) // warning C4702: unreachable code
-#  pragma warning(disable: 4522) // warning C4522: multiple assignment operators specified
-#  pragma warning(disable: 4505) // warning C4505: 'PySlice_GetIndicesEx': unreferenced local function has been removed (PyPy only)
-#elif defined(__GNUG__) && !defined(__clang__)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wunused-but-set-parameter"
-#  pragma GCC diagnostic ignored "-Wunused-but-set-variable"
-#  pragma GCC diagnostic ignored "-Wmissing-field-initializers"
-#  pragma GCC diagnostic ignored "-Wstrict-aliasing"
-#  pragma GCC diagnostic ignored "-Wattributes"
-#  if __GNUC__ >= 7
-#    pragma GCC diagnostic ignored "-Wnoexcept-type"
-#  endif
-#endif
-
-#include "attr.h"
-#include "options.h"
 #include "detail/class.h"
 #include "detail/init.h"
+#include "attr.h"
+#include "gil.h"
+#include "options.h"
 
+#include <cstdlib>
+#include <cstring>
 #include <memory>
-#include <vector>
+#include <new>
 #include <string>
 #include <utility>
+#include <vector>
 
+#if defined(__cpp_lib_launder) && !(defined(_MSC_VER) && (_MSC_VER < 1914))
+#    define PYBIND11_STD_LAUNDER std::launder
+#    define PYBIND11_HAS_STD_LAUNDER 1
+#else
+#    define PYBIND11_STD_LAUNDER
+#    define PYBIND11_HAS_STD_LAUNDER 0
+#endif
 #if defined(__GNUG__) && !defined(__clang__)
-#  include <cxxabi.h>
+#    include <cxxabi.h>
+#endif
+
+/* https://stackoverflow.com/questions/46798456/handling-gccs-noexcept-type-warning
+   This warning is about ABI compatibility, not code health.
+   It is only actually needed in a couple places, but apparently GCC 7 "generates this warning if
+   and only if the first template instantiation ... involves noexcept" [stackoverflow], therefore
+   it could get triggered from seemingly random places, depending on user code.
+   No other GCC version generates this warning.
+ */
+#if defined(__GNUC__) && __GNUC__ == 7
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wnoexcept-type"
 #endif
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
+PYBIND11_NAMESPACE_BEGIN(detail)
+
+// Apply all the extensions translators from a list
+// Return true if one of the translators completed without raising an exception
+// itself. Return of false indicates that if there are other translators
+// available, they should be tried.
+inline bool apply_exception_translators(std::forward_list<ExceptionTranslator> &translators) {
+    auto last_exception = std::current_exception();
+
+    for (auto &translator : translators) {
+        try {
+            translator(last_exception);
+            return true;
+        } catch (...) {
+            last_exception = std::current_exception();
+        }
+    }
+    return false;
+}
+
+#if defined(_MSC_VER)
+#    define PYBIND11_COMPAT_STRDUP _strdup
+#else
+#    define PYBIND11_COMPAT_STRDUP strdup
+#endif
+
+PYBIND11_NAMESPACE_END(detail)
+
 /// Wraps an arbitrary C++ function/method/lambda function/.. into a callable Python object
 class cpp_function : public function {
 public:
     cpp_function() = default;
-    cpp_function(std::nullptr_t) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(std::nullptr_t) {}
 
     /// Construct a cpp_function from a vanilla function pointer
     template <typename Return, typename... Args, typename... Extra>
-    cpp_function(Return (*f)(Args...), const Extra&... extra) {
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Return (*f)(Args...), const Extra &...extra) {
         initialize(f, f, extra...);
     }
 
     /// Construct a cpp_function from a lambda function (possibly with internal state)
-    template <typename Func, typename... Extra,
+    template <typename Func,
+              typename... Extra,
               typename = detail::enable_if_t<detail::is_lambda<Func>::value>>
-    cpp_function(Func &&f, const Extra&... extra) {
-        initialize(std::forward<Func>(f),
-                   (detail::function_signature_t<Func> *) nullptr, extra...);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Func &&f, const Extra &...extra) {
+        initialize(
+            std::forward<Func>(f), (detail::function_signature_t<Func> *) nullptr, extra...);
     }
 
     /// Construct a cpp_function from a class method (non-const, no ref-qualifier)
     template <typename Return, typename Class, typename... Arg, typename... Extra>
-    cpp_function(Return (Class::*f)(Arg...), const Extra&... extra) {
-        initialize([f](Class *c, Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
-                   (Return (*) (Class *, Arg...)) nullptr, extra...);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Return (Class::*f)(Arg...), const Extra &...extra) {
+        initialize(
+            [f](Class *c, Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
+            (Return(*)(Class *, Arg...)) nullptr,
+            extra...);
     }
 
     /// Construct a cpp_function from a class method (non-const, lvalue ref-qualifier)
     /// A copy of the overload for non-const functions without explicit ref-qualifier
     /// but with an added `&`.
     template <typename Return, typename Class, typename... Arg, typename... Extra>
-    cpp_function(Return (Class::*f)(Arg...)&, const Extra&... extra) {
-        initialize([f](Class *c, Arg... args) -> Return { return (c->*f)(args...); },
-                   (Return (*) (Class *, Arg...)) nullptr, extra...);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Return (Class::*f)(Arg...) &, const Extra &...extra) {
+        initialize(
+            [f](Class *c, Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
+            (Return(*)(Class *, Arg...)) nullptr,
+            extra...);
     }
 
     /// Construct a cpp_function from a class method (const, no ref-qualifier)
     template <typename Return, typename Class, typename... Arg, typename... Extra>
-    cpp_function(Return (Class::*f)(Arg...) const, const Extra&... extra) {
-        initialize([f](const Class *c, Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
-                   (Return (*)(const Class *, Arg ...)) nullptr, extra...);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Return (Class::*f)(Arg...) const, const Extra &...extra) {
+        initialize([f](const Class *c,
+                       Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
+                   (Return(*)(const Class *, Arg...)) nullptr,
+                   extra...);
     }
 
     /// Construct a cpp_function from a class method (const, lvalue ref-qualifier)
     /// A copy of the overload for const functions without explicit ref-qualifier
     /// but with an added `&`.
     template <typename Return, typename Class, typename... Arg, typename... Extra>
-    cpp_function(Return (Class::*f)(Arg...) const&, const Extra&... extra) {
-        initialize([f](const Class *c, Arg... args) -> Return { return (c->*f)(args...); },
-                   (Return (*)(const Class *, Arg ...)) nullptr, extra...);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    cpp_function(Return (Class::*f)(Arg...) const &, const Extra &...extra) {
+        initialize([f](const Class *c,
+                       Arg... args) -> Return { return (c->*f)(std::forward<Arg>(args)...); },
+                   (Return(*)(const Class *, Arg...)) nullptr,
+                   extra...);
     }
 
     /// Return the function name
     object name() const { return attr("__name__"); }
 
 protected:
+    struct InitializingFunctionRecordDeleter {
+        // `destruct(function_record, false)`: `initialize_generic` copies strings and
+        // takes care of cleaning up in case of exceptions. So pass `false` to `free_strings`.
+        void operator()(detail::function_record *rec) { destruct(rec, false); }
+    };
+    using unique_function_record
+        = std::unique_ptr<detail::function_record, InitializingFunctionRecordDeleter>;
+
     /// Space optimization: don't inline this frequently instantiated fragment
-    PYBIND11_NOINLINE detail::function_record *make_function_record() {
-        return new detail::function_record();
+    PYBIND11_NOINLINE unique_function_record make_function_record() {
+        return unique_function_record(new detail::function_record());
     }
 
     /// Special internal constructor for functors, lambda functions, etc.
     template <typename Func, typename Return, typename... Args, typename... Extra>
-    void initialize(Func &&f, Return (*)(Args...), const Extra&... extra) {
+    void initialize(Func &&f, Return (*)(Args...), const Extra &...extra) {
         using namespace detail;
-        struct capture { remove_reference_t<Func> f; };
+        struct capture {
+            remove_reference_t<Func> f;
+        };
 
-        /* Store the function including any extra state it might have (e.g. a lambda capture object) */
-        auto rec = make_function_record();
+        /* Store the function including any extra state it might have (e.g. a lambda capture
+         * object) */
+        // The unique_ptr makes sure nothing is leaked in case of an exception.
+        auto unique_rec = make_function_record();
+        auto *rec = unique_rec.get();
 
         /* Store the capture object directly in the function record if there is enough space */
-        if (sizeof(capture) <= sizeof(rec->data)) {
+        if (PYBIND11_SILENCE_MSVC_C4127(sizeof(capture) <= sizeof(rec->data))) {
             /* Without these pragmas, GCC warns that there might not be
                enough space to use the placement new operator. However, the
                'if' statement above ensures that this is the case. */
-#if defined(__GNUG__) && !defined(__clang__) && __GNUC__ >= 6
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wplacement-new"
+#if defined(__GNUG__) && __GNUC__ >= 6 && !defined(__clang__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wplacement-new"
 #endif
-            new ((capture *) &rec->data) capture { std::forward<Func>(f) };
-#if defined(__GNUG__) && !defined(__clang__) && __GNUC__ >= 6
-#  pragma GCC diagnostic pop
+            new ((capture *) &rec->data) capture{std::forward<Func>(f)};
+#if defined(__GNUG__) && __GNUC__ >= 6 && !defined(__clang__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic pop
+#endif
+#if defined(__GNUG__) && !PYBIND11_HAS_STD_LAUNDER && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wstrict-aliasing"
+#endif
+            // UB without std::launder, but without breaking ABI and/or
+            // a significant refactoring it's "impossible" to solve.
+            if (!std::is_trivially_destructible<capture>::value) {
+                rec->free_data = [](function_record *r) {
+                    auto data = PYBIND11_STD_LAUNDER((capture *) &r->data);
+                    (void) data;
+                    data->~capture();
+                };
+            }
+#if defined(__GNUG__) && !PYBIND11_HAS_STD_LAUNDER && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic pop
 #endif
-            if (!std::is_trivially_destructible<Func>::value)
-                rec->free_data = [](function_record *r) { ((capture *) &r->data)->~capture(); };
         } else {
-            rec->data[0] = new capture { std::forward<Func>(f) };
+            rec->data[0] = new capture{std::forward<Func>(f)};
             rec->free_data = [](function_record *r) { delete ((capture *) r->data[0]); };
         }
 
         /* Type casters for the function arguments and return value */
         using cast_in = argument_loader<Args...>;
-        using cast_out = make_caster<
-            conditional_t<std::is_void<Return>::value, void_type, Return>
-        >;
+        using cast_out
+            = make_caster<conditional_t<std::is_void<Return>::value, void_type, Return>>;
 
-        static_assert(expected_num_args<Extra...>(sizeof...(Args), cast_in::has_args, cast_in::has_kwargs),
-                      "The number of argument annotations does not match the number of function arguments");
+        static_assert(
+            expected_num_args<Extra...>(
+                sizeof...(Args), cast_in::args_pos >= 0, cast_in::has_kwargs),
+            "The number of argument annotations does not match the number of function arguments");
 
         /* Dispatch code which converts function arguments and performs the actual function call */
         rec->impl = [](function_call &call) -> handle {
             cast_in args_converter;
 
             /* Try to cast the function arguments into the C++ domain */
-            if (!args_converter.load_args(call))
+            if (!args_converter.load_args(call)) {
                 return PYBIND11_TRY_NEXT_OVERLOAD;
+            }
 
             /* Invoke call policy pre-call hook */
             process_attributes<Extra...>::precall(call);
 
             /* Get a pointer to the capture object */
-            auto data = (sizeof(capture) <= sizeof(call.func.data)
-                         ? &call.func.data : call.func.data[0]);
+            const auto *data = (sizeof(capture) <= sizeof(call.func.data) ? &call.func.data
+                                                                          : call.func.data[0]);
             auto *cap = const_cast<capture *>(reinterpret_cast<const capture *>(data));
 
             /* Override policy for rvalues -- usually to enforce rvp::move on an rvalue */
-            return_value_policy policy = return_value_policy_override<Return>::policy(call.func.policy);
+            return_value_policy policy
+                = return_value_policy_override<Return>::policy(call.func.policy);
 
             /* Function scope guard -- defaults to the compile-to-nothing `void_type` */
             using Guard = extract_guard_t<Extra...>;
 
             /* Perform the function call */
-            handle result = cast_out::cast(
-                std::move(args_converter).template call<Return, Guard>(cap->f), policy, call.parent);
+            handle result
+                = cast_out::cast(std::move(args_converter).template call<Return, Guard>(cap->f),
+                                 policy,
+                                 call.parent);
 
             /* Invoke call policy post-call hook */
             process_attributes<Extra...>::postcall(call, result);
@@ -189,86 +256,156 @@ class cpp_function : public function {
             return result;
         };
 
+        rec->nargs_pos = cast_in::args_pos >= 0
+                             ? static_cast<std::uint16_t>(cast_in::args_pos)
+                             : sizeof...(Args) - cast_in::has_kwargs; // Will get reduced more if
+                                                                      // we have a kw_only
+        rec->has_args = cast_in::args_pos >= 0;
+        rec->has_kwargs = cast_in::has_kwargs;
+
         /* Process any user-provided function attributes */
         process_attributes<Extra...>::init(extra..., rec);
 
         {
             constexpr bool has_kw_only_args = any_of<std::is_same<kw_only, Extra>...>::value,
                            has_pos_only_args = any_of<std::is_same<pos_only, Extra>...>::value,
-                           has_args = any_of<std::is_same<args, Args>...>::value,
                            has_arg_annotations = any_of<is_keyword<Extra>...>::value;
-            static_assert(has_arg_annotations || !has_kw_only_args, "py::kw_only requires the use of argument annotations");
-            static_assert(has_arg_annotations || !has_pos_only_args, "py::pos_only requires the use of argument annotations (for docstrings and aligning the annotations to the argument)");
-            static_assert(!(has_args && has_kw_only_args), "py::kw_only cannot be combined with a py::args argument");
+            static_assert(has_arg_annotations || !has_kw_only_args,
+                          "py::kw_only requires the use of argument annotations");
+            static_assert(has_arg_annotations || !has_pos_only_args,
+                          "py::pos_only requires the use of argument annotations (for docstrings "
+                          "and aligning the annotations to the argument)");
+
+            static_assert(constexpr_sum(is_kw_only<Extra>::value...) <= 1,
+                          "py::kw_only may be specified only once");
+            static_assert(constexpr_sum(is_pos_only<Extra>::value...) <= 1,
+                          "py::pos_only may be specified only once");
+            constexpr auto kw_only_pos = constexpr_first<is_kw_only, Extra...>();
+            constexpr auto pos_only_pos = constexpr_first<is_pos_only, Extra...>();
+            static_assert(!(has_kw_only_args && has_pos_only_args) || pos_only_pos < kw_only_pos,
+                          "py::pos_only must come before py::kw_only");
         }
 
-        /* Generate a readable signature describing the function's arguments and return value types */
-        static constexpr auto signature = _("(") + cast_in::arg_names + _(") -> ") + cast_out::name;
+        /* Generate a readable signature describing the function's arguments and return
+           value types */
+        static constexpr auto signature
+            = const_name("(") + cast_in::arg_names + const_name(") -> ") + cast_out::name;
         PYBIND11_DESCR_CONSTEXPR auto types = decltype(signature)::types();
 
         /* Register the function with Python from generic (non-templated) code */
-        initialize_generic(rec, signature.text, types.data(), sizeof...(Args));
-
-        if (cast_in::has_args) rec->has_args = true;
-        if (cast_in::has_kwargs) rec->has_kwargs = true;
+        // Pass on the ownership over the `unique_rec` to `initialize_generic`. `rec` stays valid.
+        initialize_generic(std::move(unique_rec), signature.text, types.data(), sizeof...(Args));
 
         /* Stash some additional information used by an important optimization in 'functional.h' */
         using FunctionType = Return (*)(Args...);
-        constexpr bool is_function_ptr =
-            std::is_convertible<Func, FunctionType>::value &&
-            sizeof(capture) == sizeof(void *);
+        constexpr bool is_function_ptr
+            = std::is_convertible<Func, FunctionType>::value && sizeof(capture) == sizeof(void *);
         if (is_function_ptr) {
             rec->is_stateless = true;
-            rec->data[1] = const_cast<void *>(reinterpret_cast<const void *>(&typeid(FunctionType)));
+            rec->data[1]
+                = const_cast<void *>(reinterpret_cast<const void *>(&typeid(FunctionType)));
         }
     }
 
+    // Utility class that keeps track of all duplicated strings, and cleans them up in its
+    // destructor, unless they are released. Basically a RAII-solution to deal with exceptions
+    // along the way.
+    class strdup_guard {
+    public:
+        strdup_guard() = default;
+        strdup_guard(const strdup_guard &) = delete;
+        strdup_guard &operator=(const strdup_guard &) = delete;
+
+        ~strdup_guard() {
+            for (auto *s : strings) {
+                std::free(s);
+            }
+        }
+        char *operator()(const char *s) {
+            auto *t = PYBIND11_COMPAT_STRDUP(s);
+            strings.push_back(t);
+            return t;
+        }
+        void release() { strings.clear(); }
+
+    private:
+        std::vector<char *> strings;
+    };
+
     /// Register a function call with Python (generic non-templated code goes here)
-    void initialize_generic(detail::function_record *rec, const char *text,
-                            const std::type_info *const *types, size_t args) {
+    void initialize_generic(unique_function_record &&unique_rec,
+                            const char *text,
+                            const std::type_info *const *types,
+                            size_t args) {
+        // Do NOT receive `unique_rec` by value. If this function fails to move out the unique_ptr,
+        // we do not want this to destruct the pointer. `initialize` (the caller) still relies on
+        // the pointee being alive after this call. Only move out if a `capsule` is going to keep
+        // it alive.
+        auto *rec = unique_rec.get();
+
+        // Keep track of strdup'ed strings, and clean them up as long as the function's capsule
+        // has not taken ownership yet (when `unique_rec.release()` is called).
+        // Note: This cannot easily be fixed by a `unique_ptr` with custom deleter, because the
+        // strings are only referenced before strdup'ing. So only *after* the following block could
+        // `destruct` safely be called, but even then, `repr` could still throw in the middle of
+        // copying all strings.
+        strdup_guard guarded_strdup;
 
         /* Create copies of all referenced C-style strings */
-        rec->name = strdup(rec->name ? rec->name : "");
-        if (rec->doc) rec->doc = strdup(rec->doc);
-        for (auto &a: rec->args) {
-            if (a.name)
-                a.name = strdup(a.name);
-            if (a.descr)
-                a.descr = strdup(a.descr);
-            else if (a.value)
-                a.descr = strdup(repr(a.value).cast<std::string>().c_str());
+        rec->name = guarded_strdup(rec->name ? rec->name : "");
+        if (rec->doc) {
+            rec->doc = guarded_strdup(rec->doc);
+        }
+        for (auto &a : rec->args) {
+            if (a.name) {
+                a.name = guarded_strdup(a.name);
+            }
+            if (a.descr) {
+                a.descr = guarded_strdup(a.descr);
+            } else if (a.value) {
+                a.descr = guarded_strdup(repr(a.value).cast<std::string>().c_str());
+            }
         }
 
-        rec->is_constructor = !strcmp(rec->name, "__init__") || !strcmp(rec->name, "__setstate__");
+        rec->is_constructor = (std::strcmp(rec->name, "__init__") == 0)
+                              || (std::strcmp(rec->name, "__setstate__") == 0);
 
-#if !defined(NDEBUG) && !defined(PYBIND11_DISABLE_NEW_STYLE_INIT_WARNING)
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES) && !defined(PYBIND11_DISABLE_NEW_STYLE_INIT_WARNING)
         if (rec->is_constructor && !rec->is_new_style_constructor) {
-            const auto class_name = detail::get_fully_qualified_tp_name((PyTypeObject *) rec->scope.ptr());
+            const auto class_name
+                = detail::get_fully_qualified_tp_name((PyTypeObject *) rec->scope.ptr());
             const auto func_name = std::string(rec->name);
-            PyErr_WarnEx(
-                PyExc_FutureWarning,
-                ("pybind11-bound class '" + class_name + "' is using an old-style "
-                 "placement-new '" + func_name + "' which has been deprecated. See "
-                 "the upgrade guide in pybind11's docs. This message is only visible "
-                 "when compiled in debug mode.").c_str(), 0
-            );
+            PyErr_WarnEx(PyExc_FutureWarning,
+                         ("pybind11-bound class '" + class_name
+                          + "' is using an old-style "
+                            "placement-new '"
+                          + func_name
+                          + "' which has been deprecated. See "
+                            "the upgrade guide in pybind11's docs. This message is only visible "
+                            "when compiled in debug mode.")
+                             .c_str(),
+                         0);
         }
 #endif
 
         /* Generate a proper function signature */
         std::string signature;
         size_t type_index = 0, arg_index = 0;
-        for (auto *pc = text; *pc != '\0'; ++pc) {
+        bool is_starred = false;
+        for (const auto *pc = text; *pc != '\0'; ++pc) {
             const auto c = *pc;
 
             if (c == '{') {
                 // Write arg name for everything except *args and **kwargs.
-                if (*(pc + 1) == '*')
+                is_starred = *(pc + 1) == '*';
+                if (is_starred) {
                     continue;
+                }
                 // Separator for keyword-only arguments, placed before the kw
-                // arguments start
-                if (rec->nargs_kw_only > 0 && arg_index + rec->nargs_kw_only == args)
+                // arguments start (unless we are already putting an *args)
+                if (!rec->has_args && arg_index == rec->nargs_pos) {
                     signature += "*, ";
+                }
                 if (arg_index < rec->args.size() && rec->args[arg_index].name) {
                     signature += rec->args[arg_index].name;
                 } else if (arg_index == 0 && rec->is_method) {
@@ -279,30 +416,32 @@ class cpp_function : public function {
                 signature += ": ";
             } else if (c == '}') {
                 // Write default value if available.
-                if (arg_index < rec->args.size() && rec->args[arg_index].descr) {
+                if (!is_starred && arg_index < rec->args.size() && rec->args[arg_index].descr) {
                     signature += " = ";
                     signature += rec->args[arg_index].descr;
                 }
                 // Separator for positional-only arguments (placed after the
                 // argument, rather than before like *
-                if (rec->nargs_pos_only > 0 && (arg_index + 1) == rec->nargs_pos_only)
+                if (rec->nargs_pos_only > 0 && (arg_index + 1) == rec->nargs_pos_only) {
                     signature += ", /";
-                arg_index++;
+                }
+                if (!is_starred) {
+                    arg_index++;
+                }
             } else if (c == '%') {
                 const std::type_info *t = types[type_index++];
-                if (!t)
+                if (!t) {
                     pybind11_fail("Internal error while parsing type signature (1)");
-                if (auto tinfo = detail::get_type_info(*t)) {
+                }
+                if (auto *tinfo = detail::get_type_info(*t)) {
                     handle th((PyObject *) tinfo->type);
-                    signature +=
-                        th.attr("__module__").cast<std::string>() + "." +
-                        th.attr("__qualname__").cast<std::string>(); // Python 3.3+, but we backport it to earlier versions
+                    signature += th.attr("__module__").cast<std::string>() + "."
+                                 + th.attr("__qualname__").cast<std::string>();
                 } else if (rec->is_new_style_constructor && arg_index == 0) {
                     // A new-style `__init__` takes `self` as `value_and_holder`.
                     // Rewrite it to the proper class type.
-                    signature +=
-                        rec->scope.attr("__module__").cast<std::string>() + "." +
-                        rec->scope.attr("__qualname__").cast<std::string>();
+                    signature += rec->scope.attr("__module__").cast<std::string>() + "."
+                                 + rec->scope.attr("__qualname__").cast<std::string>();
                 } else {
                     std::string tname(t->name());
                     detail::clean_type_id(tname);
@@ -313,39 +452,37 @@ class cpp_function : public function {
             }
         }
 
-        if (arg_index != args || types[type_index] != nullptr)
+        if (arg_index != args - rec->has_args - rec->has_kwargs || types[type_index] != nullptr) {
             pybind11_fail("Internal error while parsing type signature (2)");
-
-#if PY_MAJOR_VERSION < 3
-        if (strcmp(rec->name, "__next__") == 0) {
-            std::free(rec->name);
-            rec->name = strdup("next");
-        } else if (strcmp(rec->name, "__bool__") == 0) {
-            std::free(rec->name);
-            rec->name = strdup("__nonzero__");
         }
-#endif
-        rec->signature = strdup(signature.c_str());
+
+        rec->signature = guarded_strdup(signature.c_str());
         rec->args.shrink_to_fit();
         rec->nargs = (std::uint16_t) args;
 
-        if (rec->sibling && PYBIND11_INSTANCE_METHOD_CHECK(rec->sibling.ptr()))
+        if (rec->sibling && PYBIND11_INSTANCE_METHOD_CHECK(rec->sibling.ptr())) {
             rec->sibling = PYBIND11_INSTANCE_METHOD_GET_FUNCTION(rec->sibling.ptr());
+        }
 
         detail::function_record *chain = nullptr, *chain_start = rec;
         if (rec->sibling) {
             if (PyCFunction_Check(rec->sibling.ptr())) {
-                auto rec_capsule = reinterpret_borrow<capsule>(PyCFunction_GET_SELF(rec->sibling.ptr()));
+                auto *self = PyCFunction_GET_SELF(rec->sibling.ptr());
+                capsule rec_capsule = isinstance<capsule>(self) ? reinterpret_borrow<capsule>(self)
+                                                                : capsule(self);
                 chain = (detail::function_record *) rec_capsule;
                 /* Never append a method to an overload chain of a parent class;
                    instead, hide the parent's overloads in this case */
-                if (!chain->scope.is(rec->scope))
+                if (!chain->scope.is(rec->scope)) {
                     chain = nullptr;
+                }
+            }
+            // Don't trigger for things like the default __init__, which are wrapper_descriptors
+            // that we are intentionally replacing
+            else if (!rec->sibling.is_none() && rec->name[0] != '_') {
+                pybind11_fail("Cannot overload existing non-function object \""
+                              + std::string(rec->name) + "\" with a function of the same name");
             }
-            // Don't trigger for things like the default __init__, which are wrapper_descriptors that we are intentionally replacing
-            else if (!rec->sibling.is_none() && rec->name[0] != '_')
-                pybind11_fail("Cannot overload existing non-function object \"" + std::string(rec->name) +
-                        "\" with a function of the same name");
         }
 
         if (!chain) {
@@ -353,12 +490,13 @@ class cpp_function : public function {
             rec->def = new PyMethodDef();
             std::memset(rec->def, 0, sizeof(PyMethodDef));
             rec->def->ml_name = rec->name;
-            rec->def->ml_meth = reinterpret_cast<PyCFunction>(reinterpret_cast<void (*) (void)>(*dispatcher));
+            rec->def->ml_meth
+                = reinterpret_cast<PyCFunction>(reinterpret_cast<void (*)()>(dispatcher));
             rec->def->ml_flags = METH_VARARGS | METH_KEYWORDS;
 
-            capsule rec_capsule(rec, [](void *ptr) {
-                destruct((detail::function_record *) ptr);
-            });
+            capsule rec_capsule(unique_rec.release(),
+                                [](void *ptr) { destruct((detail::function_record *) ptr); });
+            guarded_strdup.release();
 
             object scope_module;
             if (rec->scope) {
@@ -370,21 +508,27 @@ class cpp_function : public function {
             }
 
             m_ptr = PyCFunction_NewEx(rec->def, rec_capsule.ptr(), scope_module.ptr());
-            if (!m_ptr)
+            if (!m_ptr) {
                 pybind11_fail("cpp_function::cpp_function(): Could not allocate function object");
+            }
         } else {
             /* Append at the beginning or end of the overload chain */
             m_ptr = rec->sibling.ptr();
             inc_ref();
-            if (chain->is_method != rec->is_method)
-                pybind11_fail("overloading a method with both static and instance methods is not supported; "
-                    #if defined(NDEBUG)
-                        "compile in debug mode for more details"
-                    #else
-                        "error while attempting to bind " + std::string(rec->is_method ? "instance" : "static") + " method " +
-                        std::string(pybind11::str(rec->scope.attr("__name__"))) + "." + std::string(rec->name) + signature
-                    #endif
+            if (chain->is_method != rec->is_method) {
+                pybind11_fail(
+                    "overloading a method with both static and instance methods is not supported; "
+#if !defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+                    "#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for more "
+                    "details"
+#else
+                    "error while attempting to bind "
+                    + std::string(rec->is_method ? "instance" : "static") + " method "
+                    + std::string(pybind11::str(rec->scope.attr("__name__"))) + "."
+                    + std::string(rec->name) + signature
+#endif
                 );
+            }
 
             if (rec->prepend) {
                 // Beginning of chain; we need to replace the capsule's current head-of-the-chain
@@ -392,14 +536,18 @@ class cpp_function : public function {
                 // chain.
                 chain_start = rec;
                 rec->next = chain;
-                auto rec_capsule = reinterpret_borrow<capsule>(((PyCFunctionObject *) m_ptr)->m_self);
-                rec_capsule.set_pointer(rec);
+                auto rec_capsule
+                    = reinterpret_borrow<capsule>(((PyCFunctionObject *) m_ptr)->m_self);
+                rec_capsule.set_pointer(unique_rec.release());
+                guarded_strdup.release();
             } else {
                 // Or end of chain (normal behavior)
                 chain_start = chain;
-                while (chain->next)
+                while (chain->next) {
                     chain = chain->next;
-                chain->next = rec;
+                }
+                chain->next = unique_rec.release();
+                guarded_strdup.release();
             }
         }
 
@@ -415,73 +563,95 @@ class cpp_function : public function {
         }
         // Then specific overload signatures
         bool first_user_def = true;
-        for (auto it = chain_start; it != nullptr; it = it->next) {
+        for (auto *it = chain_start; it != nullptr; it = it->next) {
             if (options::show_function_signatures()) {
-                if (index > 0) signatures += "\n";
-                if (chain)
+                if (index > 0) {
+                    signatures += '\n';
+                }
+                if (chain) {
                     signatures += std::to_string(++index) + ". ";
+                }
                 signatures += rec->name;
                 signatures += it->signature;
-                signatures += "\n";
+                signatures += '\n';
             }
-            if (it->doc && strlen(it->doc) > 0 && options::show_user_defined_docstrings()) {
-                // If we're appending another docstring, and aren't printing function signatures, we
-                // need to append a newline first:
+            if (it->doc && it->doc[0] != '\0' && options::show_user_defined_docstrings()) {
+                // If we're appending another docstring, and aren't printing function signatures,
+                // we need to append a newline first:
                 if (!options::show_function_signatures()) {
-                    if (first_user_def) first_user_def = false;
-                    else signatures += "\n";
+                    if (first_user_def) {
+                        first_user_def = false;
+                    } else {
+                        signatures += '\n';
+                    }
+                }
+                if (options::show_function_signatures()) {
+                    signatures += '\n';
                 }
-                if (options::show_function_signatures()) signatures += "\n";
                 signatures += it->doc;
-                if (options::show_function_signatures()) signatures += "\n";
+                if (options::show_function_signatures()) {
+                    signatures += '\n';
+                }
             }
         }
 
         /* Install docstring */
         auto *func = (PyCFunctionObject *) m_ptr;
-        if (func->m_ml->ml_doc)
-            std::free(const_cast<char *>(func->m_ml->ml_doc));
-        func->m_ml->ml_doc = strdup(signatures.c_str());
+        std::free(const_cast<char *>(func->m_ml->ml_doc));
+        // Install docstring if it's non-empty (when at least one option is enabled)
+        func->m_ml->ml_doc
+            = signatures.empty() ? nullptr : PYBIND11_COMPAT_STRDUP(signatures.c_str());
 
         if (rec->is_method) {
             m_ptr = PYBIND11_INSTANCE_METHOD_NEW(m_ptr, rec->scope.ptr());
-            if (!m_ptr)
-                pybind11_fail("cpp_function::cpp_function(): Could not allocate instance method object");
+            if (!m_ptr) {
+                pybind11_fail(
+                    "cpp_function::cpp_function(): Could not allocate instance method object");
+            }
             Py_DECREF(func);
         }
     }
 
     /// When a cpp_function is GCed, release any memory allocated by pybind11
-    static void destruct(detail::function_record *rec) {
-        // If on Python 3.9, check the interpreter "MICRO" (patch) version.
-        // If this is running on 3.9.0, we have to work around a bug.
-        #if !defined(PYPY_VERSION) && PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION == 9
-            static bool is_zero = Py_GetVersion()[4] == '0';
-        #endif
+    static void destruct(detail::function_record *rec, bool free_strings = true) {
+// If on Python 3.9, check the interpreter "MICRO" (patch) version.
+// If this is running on 3.9.0, we have to work around a bug.
+#if !defined(PYPY_VERSION) && PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION == 9
+        static bool is_zero = Py_GetVersion()[4] == '0';
+#endif
 
         while (rec) {
             detail::function_record *next = rec->next;
-            if (rec->free_data)
+            if (rec->free_data) {
                 rec->free_data(rec);
-            std::free((char *) rec->name);
-            std::free((char *) rec->doc);
-            std::free((char *) rec->signature);
-            for (auto &arg: rec->args) {
-                std::free(const_cast<char *>(arg.name));
-                std::free(const_cast<char *>(arg.descr));
+            }
+            // During initialization, these strings might not have been copied yet,
+            // so they cannot be freed. Once the function has been created, they can.
+            // Check `make_function_record` for more details.
+            if (free_strings) {
+                std::free((char *) rec->name);
+                std::free((char *) rec->doc);
+                std::free((char *) rec->signature);
+                for (auto &arg : rec->args) {
+                    std::free(const_cast<char *>(arg.name));
+                    std::free(const_cast<char *>(arg.descr));
+                }
+            }
+            for (auto &arg : rec->args) {
                 arg.value.dec_ref();
             }
             if (rec->def) {
                 std::free(const_cast<char *>(rec->def->ml_doc));
-                // Python 3.9.0 decref's these in the wrong order; rec->def
-                // If loaded on 3.9.0, let these leak (use Python 3.9.1 at runtime to fix)
-                // See https://github.com/python/cpython/pull/22670
-                #if !defined(PYPY_VERSION) && PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION == 9
-                    if (!is_zero)
-                        delete rec->def;
-                #else
+// Python 3.9.0 decref's these in the wrong order; rec->def
+// If loaded on 3.9.0, let these leak (use Python 3.9.1 at runtime to fix)
+// See https://github.com/python/cpython/pull/22670
+#if !defined(PYPY_VERSION) && PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION == 9
+                if (!is_zero) {
                     delete rec->def;
-                #endif
+                }
+#else
+                delete rec->def;
+#endif
             }
             delete rec;
             rec = next;
@@ -496,7 +666,8 @@ class cpp_function : public function {
         const function_record *overloads = (function_record *) PyCapsule_GetPointer(self, nullptr),
                               *it = overloads;
 
-        /* Need to know how many arguments + keyword arguments there are to pick the right overload */
+        /* Need to know how many arguments + keyword arguments there are to pick the right
+           overload */
         const auto n_args_in = (size_t) PyTuple_GET_SIZE(args_in);
 
         handle parent = n_args_in > 0 ? PyTuple_GET_ITEM(args_in, 0) : nullptr,
@@ -504,19 +675,23 @@ class cpp_function : public function {
 
         auto self_value_and_holder = value_and_holder();
         if (overloads->is_constructor) {
-            const auto tinfo = get_type_info((PyTypeObject *) overloads->scope.ptr());
-            const auto pi = reinterpret_cast<instance *>(parent.ptr());
-            self_value_and_holder = pi->get_value_and_holder(tinfo, false);
-
-            if (!self_value_and_holder.type || !self_value_and_holder.inst) {
-                PyErr_SetString(PyExc_TypeError, "__init__(self, ...) called with invalid `self` argument");
+            if (!parent
+                || !PyObject_TypeCheck(parent.ptr(), (PyTypeObject *) overloads->scope.ptr())) {
+                PyErr_SetString(
+                    PyExc_TypeError,
+                    "__init__(self, ...) called with invalid or missing `self` argument");
                 return nullptr;
             }
 
+            auto *const tinfo = get_type_info((PyTypeObject *) overloads->scope.ptr());
+            auto *const pi = reinterpret_cast<instance *>(parent.ptr());
+            self_value_and_holder = pi->get_value_and_holder(tinfo, true);
+
             // If this value is already registered it must mean __init__ is invoked multiple times;
             // we really can't support that in C++, so just ignore the second __init__.
-            if (self_value_and_holder.instance_registered())
+            if (self_value_and_holder.instance_registered()) {
                 return none().release().ptr();
+            }
         }
 
         try {
@@ -535,44 +710,53 @@ class cpp_function : public function {
                    1. Copy all positional arguments we were given, also checking to make sure that
                       named positional arguments weren't *also* specified via kwarg.
                    2. If we weren't given enough, try to make up the omitted ones by checking
-                      whether they were provided by a kwarg matching the `py::arg("name")` name.  If
-                      so, use it (and remove it from kwargs; if not, see if the function binding
+                      whether they were provided by a kwarg matching the `py::arg("name")` name. If
+                      so, use it (and remove it from kwargs); if not, see if the function binding
                       provided a default that we can use.
-                   3. Ensure that either all keyword arguments were "consumed", or that the function
-                      takes a kwargs argument to accept unconsumed kwargs.
+                   3. Ensure that either all keyword arguments were "consumed", or that the
+                   function takes a kwargs argument to accept unconsumed kwargs.
                    4. Any positional arguments still left get put into a tuple (for args), and any
                       leftover kwargs get put into a dict.
                    5. Pack everything into a vector; if we have py::args or py::kwargs, they are an
                       extra tuple or dict at the end of the positional arguments.
                    6. Call the function call dispatcher (function_record::impl)
 
-                   If one of these fail, move on to the next overload and keep trying until we get a
-                   result other than PYBIND11_TRY_NEXT_OVERLOAD.
+                   If one of these fail, move on to the next overload and keep trying until we get
+                   a result other than PYBIND11_TRY_NEXT_OVERLOAD.
                  */
 
                 const function_record &func = *it;
-                size_t num_args = func.nargs;    // Number of positional arguments that we need
-                if (func.has_args) --num_args;   // (but don't count py::args
-                if (func.has_kwargs) --num_args; //  or py::kwargs)
-                size_t pos_args = num_args - func.nargs_kw_only;
+                size_t num_args = func.nargs; // Number of positional arguments that we need
+                if (func.has_args) {
+                    --num_args; // (but don't count py::args
+                }
+                if (func.has_kwargs) {
+                    --num_args; //  or py::kwargs)
+                }
+                size_t pos_args = func.nargs_pos;
 
-                if (!func.has_args && n_args_in > pos_args)
+                if (!func.has_args && n_args_in > pos_args) {
                     continue; // Too many positional arguments for this overload
+                }
 
-                if (n_args_in < pos_args && func.args.size() < pos_args)
-                    continue; // Not enough positional arguments given, and not enough defaults to fill in the blanks
+                if (n_args_in < pos_args && func.args.size() < pos_args) {
+                    continue; // Not enough positional arguments given, and not enough defaults to
+                              // fill in the blanks
+                }
 
                 function_call call(func, parent);
 
-                size_t args_to_copy = (std::min)(pos_args, n_args_in); // Protect std::min with parentheses
+                // Protect std::min with parentheses
+                size_t args_to_copy = (std::min)(pos_args, n_args_in);
                 size_t args_copied = 0;
 
                 // 0. Inject new-style `self` argument
                 if (func.is_new_style_constructor) {
                     // The `value` may have been preallocated by an old-style `__init__`
                     // if it was a preceding candidate for overload resolution.
-                    if (self_value_and_holder)
+                    if (self_value_and_holder) {
                         self_value_and_holder.type->dealloc(self_value_and_holder);
+                    }
 
                     call.init_self = PyTuple_GET_ITEM(args_in, 0);
                     call.args.emplace_back(reinterpret_cast<PyObject *>(&self_value_and_holder));
@@ -583,8 +767,10 @@ class cpp_function : public function {
                 // 1. Copy any position arguments given.
                 bool bad_arg = false;
                 for (; args_copied < args_to_copy; ++args_copied) {
-                    const argument_record *arg_rec = args_copied < func.args.size() ? &func.args[args_copied] : nullptr;
-                    if (kwargs_in && arg_rec && arg_rec->name && PyDict_GetItemString(kwargs_in, arg_rec->name)) {
+                    const argument_record *arg_rec
+                        = args_copied < func.args.size() ? &func.args[args_copied] : nullptr;
+                    if (kwargs_in && arg_rec && arg_rec->name
+                        && dict_getitemstring(kwargs_in, arg_rec->name)) {
                         bad_arg = true;
                         break;
                     }
@@ -597,8 +783,13 @@ class cpp_function : public function {
                     call.args.push_back(arg);
                     call.args_convert.push_back(arg_rec ? arg_rec->convert : true);
                 }
-                if (bad_arg)
+                if (bad_arg) {
                     continue; // Maybe it was meant for another overload (issue #688)
+                }
+
+                // Keep track of how many position args we copied out in case we need to come back
+                // to copy the rest into a py::args argument.
+                size_t positional_args_copied = args_copied;
 
                 // We'll need to copy this if we steal some kwargs for defaults
                 dict kwargs = reinterpret_borrow<dict>(kwargs_in);
@@ -615,12 +806,14 @@ class cpp_function : public function {
                         if (value) {
                             call.args.push_back(value);
                             call.args_convert.push_back(arg_rec.convert);
-                        } else
+                        } else {
                             break;
+                        }
                     }
 
-                    if (args_copied < func.nargs_pos_only)
+                    if (args_copied < func.nargs_pos_only) {
                         continue; // Not enough defaults to fill the positional arguments
+                    }
                 }
 
                 // 2. Check kwargs and, failing that, defaults that may help complete the list
@@ -631,8 +824,9 @@ class cpp_function : public function {
                         const auto &arg_rec = func.args[args_copied];
 
                         handle value;
-                        if (kwargs_in && arg_rec.name)
-                            value = PyDict_GetItemString(kwargs.ptr(), arg_rec.name);
+                        if (kwargs_in && arg_rec.name) {
+                            value = dict_getitemstring(kwargs.ptr(), arg_rec.name);
+                        }
 
                         if (value) {
                             // Consume a kwargs value
@@ -640,7 +834,9 @@ class cpp_function : public function {
                                 kwargs = reinterpret_steal<dict>(PyDict_Copy(kwargs.ptr()));
                                 copied_kwargs = true;
                             }
-                            PyDict_DelItemString(kwargs.ptr(), arg_rec.name);
+                            if (PyDict_DelItemString(kwargs.ptr(), arg_rec.name) == -1) {
+                                throw error_already_set();
+                            }
                         } else if (arg_rec.value) {
                             value = arg_rec.value;
                         }
@@ -650,20 +846,29 @@ class cpp_function : public function {
                         }
 
                         if (value) {
+                            // If we're at the py::args index then first insert a stub for it to be
+                            // replaced later
+                            if (func.has_args && call.args.size() == func.nargs_pos) {
+                                call.args.push_back(none());
+                            }
+
                             call.args.push_back(value);
                             call.args_convert.push_back(arg_rec.convert);
-                        }
-                        else
+                        } else {
                             break;
+                        }
                     }
 
-                    if (args_copied < num_args)
-                        continue; // Not enough arguments, defaults, or kwargs to fill the positional arguments
+                    if (args_copied < num_args) {
+                        continue; // Not enough arguments, defaults, or kwargs to fill the
+                                  // positional arguments
+                    }
                 }
 
                 // 3. Check everything was consumed (unless we have a kwargs arg)
-                if (kwargs && !kwargs.empty() && !func.has_kwargs)
+                if (kwargs && !kwargs.empty() && !func.has_kwargs) {
                     continue; // Unconsumed kwargs, but no py::kwargs argument to accept them
+                }
 
                 // 4a. If we have a py::args argument, create a new tuple with leftovers
                 if (func.has_args) {
@@ -672,35 +877,42 @@ class cpp_function : public function {
                         // We didn't copy out any position arguments from the args_in tuple, so we
                         // can reuse it directly without copying:
                         extra_args = reinterpret_borrow<tuple>(args_in);
-                    } else if (args_copied >= n_args_in) {
+                    } else if (positional_args_copied >= n_args_in) {
                         extra_args = tuple(0);
                     } else {
-                        size_t args_size = n_args_in - args_copied;
+                        size_t args_size = n_args_in - positional_args_copied;
                         extra_args = tuple(args_size);
                         for (size_t i = 0; i < args_size; ++i) {
-                            extra_args[i] = PyTuple_GET_ITEM(args_in, args_copied + i);
+                            extra_args[i] = PyTuple_GET_ITEM(args_in, positional_args_copied + i);
                         }
                     }
-                    call.args.push_back(extra_args);
+                    if (call.args.size() <= func.nargs_pos) {
+                        call.args.push_back(extra_args);
+                    } else {
+                        call.args[func.nargs_pos] = extra_args;
+                    }
                     call.args_convert.push_back(false);
                     call.args_ref = std::move(extra_args);
                 }
 
                 // 4b. If we have a py::kwargs, pass on any remaining kwargs
                 if (func.has_kwargs) {
-                    if (!kwargs.ptr())
+                    if (!kwargs.ptr()) {
                         kwargs = dict(); // If we didn't get one, send an empty one
+                    }
                     call.args.push_back(kwargs);
                     call.args_convert.push_back(false);
                     call.kwargs_ref = std::move(kwargs);
                 }
 
-                // 5. Put everything in a vector.  Not technically step 5, we've been building it
-                // in `call.args` all along.
-                #if !defined(NDEBUG)
-                if (call.args.size() != func.nargs || call.args_convert.size() != func.nargs)
-                    pybind11_fail("Internal error: function call dispatcher inserted wrong number of arguments!");
-                #endif
+// 5. Put everything in a vector.  Not technically step 5, we've been building it
+// in `call.args` all along.
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+                if (call.args.size() != func.nargs || call.args_convert.size() != func.nargs) {
+                    pybind11_fail("Internal error: function call dispatcher inserted wrong number "
+                                  "of arguments!");
+                }
+#endif
 
                 std::vector<bool> second_pass_convert;
                 if (overloaded) {
@@ -719,8 +931,9 @@ class cpp_function : public function {
                     result = PYBIND11_TRY_NEXT_OVERLOAD;
                 }
 
-                if (result.ptr() != PYBIND11_TRY_NEXT_OVERLOAD)
+                if (result.ptr() != PYBIND11_TRY_NEXT_OVERLOAD) {
                     break;
+                }
 
                 if (overloaded) {
                     // The (overloaded) call failed; if the call has at least one argument that
@@ -739,7 +952,8 @@ class cpp_function : public function {
             }
 
             if (overloaded && !second_pass.empty() && result.ptr() == PYBIND11_TRY_NEXT_OVERLOAD) {
-                // The no-conversion pass finished without success, try again with conversion allowed
+                // The no-conversion pass finished without success, try again with conversion
+                // allowed
                 for (auto &call : second_pass) {
                     try {
                         loader_life_support guard{};
@@ -751,8 +965,9 @@ class cpp_function : public function {
                     if (result.ptr() != PYBIND11_TRY_NEXT_OVERLOAD) {
                         // The error reporting logic below expects 'it' to be valid, as it would be
                         // if we'd encountered this failure in the first-pass loop.
-                        if (!result)
+                        if (!result) {
                             it = &call.func;
+                        }
                         break;
                     }
                 }
@@ -761,33 +976,38 @@ class cpp_function : public function {
             e.restore();
             return nullptr;
 #ifdef __GLIBCXX__
-        } catch ( abi::__forced_unwind& ) {
+        } catch (abi::__forced_unwind &) {
             throw;
 #endif
         } catch (...) {
             /* When an exception is caught, give each registered exception
-               translator a chance to translate it to a Python exception
-               in reverse order of registration.
+               translator a chance to translate it to a Python exception. First
+               all module-local translators will be tried in reverse order of
+               registration. If none of the module-locale translators handle
+               the exception (or there are no module-locale translators) then
+               the global translators will be tried, also in reverse order of
+               registration.
 
                A translator may choose to do one of the following:
 
                 - catch the exception and call PyErr_SetString or PyErr_SetObject
                   to set a standard (or custom) Python exception, or
                 - do nothing and let the exception fall through to the next translator, or
-                - delegate translation to the next translator by throwing a new type of exception. */
+                - delegate translation to the next translator by throwing a new type of exception.
+             */
 
-            auto last_exception = std::current_exception();
-            auto &registered_exception_translators = get_internals().registered_exception_translators;
-            for (auto& translator : registered_exception_translators) {
-                try {
-                    translator(last_exception);
-                } catch (...) {
-                    last_exception = std::current_exception();
-                    continue;
-                }
+            auto &local_exception_translators
+                = get_local_internals().registered_exception_translators;
+            if (detail::apply_exception_translators(local_exception_translators)) {
+                return nullptr;
+            }
+            auto &exception_translators = get_internals().registered_exception_translators;
+            if (detail::apply_exception_translators(exception_translators)) {
                 return nullptr;
             }
-            PyErr_SetString(PyExc_SystemError, "Exception escaped from default exception translator!");
+
+            PyErr_SetString(PyExc_SystemError,
+                            "Exception escaped from default exception translator!");
             return nullptr;
         }
 
@@ -802,20 +1022,22 @@ class cpp_function : public function {
         };
 
         if (result.ptr() == PYBIND11_TRY_NEXT_OVERLOAD) {
-            if (overloads->is_operator)
+            if (overloads->is_operator) {
                 return handle(Py_NotImplemented).inc_ref().ptr();
+            }
 
-            std::string msg = std::string(overloads->name) + "(): incompatible " +
-                std::string(overloads->is_constructor ? "constructor" : "function") +
-                " arguments. The following argument types are supported:\n";
+            std::string msg = std::string(overloads->name) + "(): incompatible "
+                              + std::string(overloads->is_constructor ? "constructor" : "function")
+                              + " arguments. The following argument types are supported:\n";
 
             int ctr = 0;
             for (const function_record *it2 = overloads; it2 != nullptr; it2 = it2->next) {
-                msg += "    "+ std::to_string(++ctr) + ". ";
+                msg += "    " + std::to_string(++ctr) + ". ";
 
                 bool wrote_sig = false;
                 if (overloads->is_constructor) {
-                    // For a constructor, rewrite `(self: Object, arg0, ...) -> NoneType` as `Object(arg0, ...)`
+                    // For a constructor, rewrite `(self: Object, arg0, ...) -> NoneType` as
+                    // `Object(arg0, ...)`
                     std::string sig = it2->signature;
                     size_t start = sig.find('(') + 7; // skip "(self: "
                     if (start < sig.size()) {
@@ -823,7 +1045,9 @@ class cpp_function : public function {
                         size_t end = sig.find(", "), next = end + 2;
                         size_t ret = sig.rfind(" -> ");
                         // Or the ), if there is no comma:
-                        if (end >= sig.size()) next = end = sig.find(')');
+                        if (end >= sig.size()) {
+                            next = end = sig.find(')');
+                        }
                         if (start < end && next < sig.size()) {
                             msg.append(sig, start, end - start);
                             msg += '(';
@@ -832,35 +1056,45 @@ class cpp_function : public function {
                         }
                     }
                 }
-                if (!wrote_sig) msg += it2->signature;
+                if (!wrote_sig) {
+                    msg += it2->signature;
+                }
 
-                msg += "\n";
+                msg += '\n';
             }
             msg += "\nInvoked with: ";
             auto args_ = reinterpret_borrow<tuple>(args_in);
             bool some_args = false;
             for (size_t ti = overloads->is_constructor ? 1 : 0; ti < args_.size(); ++ti) {
-                if (!some_args) some_args = true;
-                else msg += ", ";
+                if (!some_args) {
+                    some_args = true;
+                } else {
+                    msg += ", ";
+                }
                 try {
                     msg += pybind11::repr(args_[ti]);
-                } catch (const error_already_set&) {
+                } catch (const error_already_set &) {
                     msg += "<repr raised Error>";
                 }
             }
             if (kwargs_in) {
                 auto kwargs = reinterpret_borrow<dict>(kwargs_in);
                 if (!kwargs.empty()) {
-                    if (some_args) msg += "; ";
+                    if (some_args) {
+                        msg += "; ";
+                    }
                     msg += "kwargs: ";
                     bool first = true;
                     for (auto kwarg : kwargs) {
-                        if (first) first = false;
-                        else msg += ", ";
+                        if (first) {
+                            first = false;
+                        } else {
+                            msg += ", ";
+                        }
                         msg += pybind11::str("{}=").format(kwarg.first);
                         try {
                             msg += pybind11::repr(kwarg.second);
-                        } catch (const error_already_set&) {
+                        } catch (const error_already_set &) {
                             msg += "<repr raised Error>";
                         }
                     }
@@ -868,22 +1102,33 @@ class cpp_function : public function {
             }
 
             append_note_if_missing_header_is_suspected(msg);
+            // Attach additional error info to the exception if supported
+            if (PyErr_Occurred()) {
+                // #HelpAppreciated: unit test coverage for this branch.
+                raise_from(PyExc_TypeError, msg.c_str());
+                return nullptr;
+            }
             PyErr_SetString(PyExc_TypeError, msg.c_str());
             return nullptr;
-        } else if (!result) {
+        }
+        if (!result) {
             std::string msg = "Unable to convert function return value to a "
                               "Python type! The signature was\n\t";
             msg += it->signature;
             append_note_if_missing_header_is_suspected(msg);
+            // Attach additional error info to the exception if supported
+            if (PyErr_Occurred()) {
+                raise_from(PyExc_TypeError, msg.c_str());
+                return nullptr;
+            }
             PyErr_SetString(PyExc_TypeError, msg.c_str());
             return nullptr;
-        } else {
-            if (overloads->is_constructor && !self_value_and_holder.holder_constructed()) {
-                auto *pi = reinterpret_cast<instance *>(parent.ptr());
-                self_value_and_holder.type->init_instance(pi, nullptr);
-            }
-            return result.ptr();
         }
+        if (overloads->is_constructor && !self_value_and_holder.holder_constructed()) {
+            auto *pi = reinterpret_cast<instance *>(parent.ptr());
+            self_value_and_holder.type->init_instance(pi, nullptr);
+        }
+        return result.ptr();
     }
 };
 
@@ -895,11 +1140,7 @@ class module_ : public object {
     /// Create a new top-level Python module with the given name and docstring
     PYBIND11_DEPRECATED("Use PYBIND11_MODULE or module_::create_extension_module instead")
     explicit module_(const char *name, const char *doc = nullptr) {
-#if PY_MAJOR_VERSION >= 3
         *this = create_extension_module(name, doc, new PyModuleDef());
-#else
-        *this = create_extension_module(name, doc, nullptr);
-#endif
     }
 
     /** \rst
@@ -908,11 +1149,15 @@ class module_ : public object {
         details on the ``Extra&& ... extra`` argument, see section :ref:`extras`.
     \endrst */
     template <typename Func, typename... Extra>
-    module_ &def(const char *name_, Func &&f, const Extra& ... extra) {
-        cpp_function func(std::forward<Func>(f), name(name_), scope(*this),
-                          sibling(getattr(*this, name_, none())), extra...);
+    module_ &def(const char *name_, Func &&f, const Extra &...extra) {
+        cpp_function func(std::forward<Func>(f),
+                          name(name_),
+                          scope(*this),
+                          sibling(getattr(*this, name_, none())),
+                          extra...);
         // NB: allow overwriting here because cpp_function sets up a chain with the intention of
-        // overwriting (and has already checked internally that it isn't overwriting non-functions).
+        // overwriting (and has already checked internally that it isn't overwriting
+        // non-functions).
         add_object(name_, func, true /* overwrite */);
         return *this;
     }
@@ -928,11 +1173,19 @@ class module_ : public object {
             py::module_ m3 = m2.def_submodule("subsub", "A submodule of 'example.sub'");
     \endrst */
     module_ def_submodule(const char *name, const char *doc = nullptr) {
-        std::string full_name = std::string(PyModule_GetName(m_ptr))
-            + std::string(".") + std::string(name);
-        auto result = reinterpret_borrow<module_>(PyImport_AddModule(full_name.c_str()));
-        if (doc && options::show_user_defined_docstrings())
+        const char *this_name = PyModule_GetName(m_ptr);
+        if (this_name == nullptr) {
+            throw error_already_set();
+        }
+        std::string full_name = std::string(this_name) + '.' + name;
+        handle submodule = PyImport_AddModule(full_name.c_str());
+        if (!submodule) {
+            throw error_already_set();
+        }
+        auto result = reinterpret_borrow<module_>(submodule);
+        if (doc && options::show_user_defined_docstrings()) {
             result.attr("__doc__") = pybind11::str(doc);
+        }
         attr(name) = result;
         return result;
     }
@@ -940,16 +1193,18 @@ class module_ : public object {
     /// Import and return a module or throws `error_already_set`.
     static module_ import(const char *name) {
         PyObject *obj = PyImport_ImportModule(name);
-        if (!obj)
+        if (!obj) {
             throw error_already_set();
+        }
         return reinterpret_steal<module_>(obj);
     }
 
     /// Reload the module or throws `error_already_set`.
     void reload() {
         PyObject *obj = PyImport_ReloadModule(ptr());
-        if (!obj)
+        if (!obj) {
             throw error_already_set();
+        }
         *this = reinterpret_steal<module_>(obj);
     }
 
@@ -957,56 +1212,49 @@ class module_ : public object {
         Adds an object to the module using the given name.  Throws if an object with the given name
         already exists.
 
-        ``overwrite`` should almost always be false: attempting to overwrite objects that pybind11 has
-        established will, in most cases, break things.
+        ``overwrite`` should almost always be false: attempting to overwrite objects that pybind11
+        has established will, in most cases, break things.
     \endrst */
     PYBIND11_NOINLINE void add_object(const char *name, handle obj, bool overwrite = false) {
-        if (!overwrite && hasattr(*this, name))
-            pybind11_fail("Error during initialization: multiple incompatible definitions with name \"" +
-                    std::string(name) + "\"");
+        if (!overwrite && hasattr(*this, name)) {
+            pybind11_fail(
+                "Error during initialization: multiple incompatible definitions with name \""
+                + std::string(name) + "\"");
+        }
 
         PyModule_AddObject(ptr(), name, obj.inc_ref().ptr() /* steals a reference */);
     }
 
-#if PY_MAJOR_VERSION >= 3
-    using module_def = PyModuleDef;
-#else
-    struct module_def {};
-#endif
+    using module_def = PyModuleDef; // TODO: Can this be removed (it was needed only for Python 2)?
 
     /** \rst
         Create a new top-level module that can be used as the main module of a C extension.
 
-        For Python 3, ``def`` should point to a staticly allocated module_def.
-        For Python 2, ``def`` can be a nullptr and is completely ignored.
+        ``def`` should point to a statically allocated module_def.
     \endrst */
     static module_ create_extension_module(const char *name, const char *doc, module_def *def) {
-#if PY_MAJOR_VERSION >= 3
         // module_def is PyModuleDef
-        def = new (def) PyModuleDef {  // Placement new (not an allocation).
-            /* m_base */     PyModuleDef_HEAD_INIT,
-            /* m_name */     name,
-            /* m_doc */      options::show_user_defined_docstrings() ? doc : nullptr,
-            /* m_size */     -1,
-            /* m_methods */  nullptr,
-            /* m_slots */    nullptr,
-            /* m_traverse */ nullptr,
-            /* m_clear */    nullptr,
-            /* m_free */     nullptr
-        };
-        auto m = PyModule_Create(def);
-#else
-        // Ignore module_def *def; only necessary for Python 3
-        (void) def;
-        auto m = Py_InitModule3(name, nullptr, options::show_user_defined_docstrings() ? doc : nullptr);
-#endif
+        // Placement new (not an allocation).
+        def = new (def)
+            PyModuleDef{/* m_base */ PyModuleDef_HEAD_INIT,
+                        /* m_name */ name,
+                        /* m_doc */ options::show_user_defined_docstrings() ? doc : nullptr,
+                        /* m_size */ -1,
+                        /* m_methods */ nullptr,
+                        /* m_slots */ nullptr,
+                        /* m_traverse */ nullptr,
+                        /* m_clear */ nullptr,
+                        /* m_free */ nullptr};
+        auto *m = PyModule_Create(def);
         if (m == nullptr) {
-            if (PyErr_Occurred())
+            if (PyErr_Occurred()) {
                 throw error_already_set();
+            }
             pybind11_fail("Internal error in module_::create_extension_module()");
         }
-        // TODO: Sould be reinterpret_steal for Python 3, but Python also steals it again when returned from PyInit_...
-        //       For Python 2, reinterpret_borrow is correct.
+        // TODO: Should be reinterpret_steal for Python 3, but Python also steals it again when
+        //       returned from PyInit_...
+        //       For Python 2, reinterpret_borrow was correct.
         return reinterpret_borrow<module_>(m);
     }
 };
@@ -1024,6 +1272,13 @@ inline dict globals() {
     return reinterpret_borrow<dict>(p ? p : module_::import("__main__").attr("__dict__").ptr());
 }
 
+template <typename... Args, typename = detail::enable_if_t<args_are_all_keyword_or_ds<Args...>()>>
+PYBIND11_DEPRECATED("make_simple_namespace should be replaced with "
+                    "py::module_::import(\"types\").attr(\"SimpleNamespace\") ")
+object make_simple_namespace(Args &&...args_) {
+    return module_::import("types").attr("SimpleNamespace")(std::forward<Args>(args_)...);
+}
+
 PYBIND11_NAMESPACE_BEGIN(detail)
 /// Generic support for creating new Python heap types
 class generic_type : public object {
@@ -1031,13 +1286,17 @@ class generic_type : public object {
     PYBIND11_OBJECT_DEFAULT(generic_type, object, PyType_Check)
 protected:
     void initialize(const type_record &rec) {
-        if (rec.scope && hasattr(rec.scope, "__dict__") && rec.scope.attr("__dict__").contains(rec.name))
-            pybind11_fail("generic_type: cannot initialize type \"" + std::string(rec.name) +
-                          "\": an object with that name is already defined");
+        if (rec.scope && hasattr(rec.scope, "__dict__")
+            && rec.scope.attr("__dict__").contains(rec.name)) {
+            pybind11_fail("generic_type: cannot initialize type \"" + std::string(rec.name)
+                          + "\": an object with that name is already defined");
+        }
 
-        if (rec.module_local ? get_local_type_info(*rec.type) : get_global_type_info(*rec.type))
-            pybind11_fail("generic_type: type \"" + std::string(rec.name) +
-                          "\" is already registered!");
+        if ((rec.module_local ? get_local_type_info(*rec.type) : get_global_type_info(*rec.type))
+            != nullptr) {
+            pybind11_fail("generic_type: type \"" + std::string(rec.name)
+                          + "\" is already registered!");
+        }
 
         m_ptr = make_new_python_type(rec);
 
@@ -1059,19 +1318,23 @@ class generic_type : public object {
         auto &internals = get_internals();
         auto tindex = std::type_index(*rec.type);
         tinfo->direct_conversions = &internals.direct_conversions[tindex];
-        if (rec.module_local)
-            registered_local_types_cpp()[tindex] = tinfo;
-        else
+        if (rec.module_local) {
+            get_local_internals().registered_types_cpp[tindex] = tinfo;
+        } else {
             internals.registered_types_cpp[tindex] = tinfo;
-        internals.registered_types_py[(PyTypeObject *) m_ptr] = { tinfo };
+        }
+        internals.registered_types_py[(PyTypeObject *) m_ptr] = {tinfo};
 
         if (rec.bases.size() > 1 || rec.multiple_inheritance) {
             mark_parents_nonsimple(tinfo->type);
             tinfo->simple_ancestors = false;
-        }
-        else if (rec.bases.size() == 1) {
-            auto parent_tinfo = get_type_info((PyTypeObject *) rec.bases[0].ptr());
-            tinfo->simple_ancestors = parent_tinfo->simple_ancestors;
+        } else if (rec.bases.size() == 1) {
+            auto *parent_tinfo = get_type_info((PyTypeObject *) rec.bases[0].ptr());
+            assert(parent_tinfo != nullptr);
+            bool parent_simple_ancestors = parent_tinfo->simple_ancestors;
+            tinfo->simple_ancestors = parent_simple_ancestors;
+            // The parent can no longer be a simple type if it has MI and has a child
+            parent_tinfo->simple_type = parent_tinfo->simple_type && parent_simple_ancestors;
         }
 
         if (rec.module_local) {
@@ -1085,25 +1348,25 @@ class generic_type : public object {
     void mark_parents_nonsimple(PyTypeObject *value) {
         auto t = reinterpret_borrow<tuple>(value->tp_bases);
         for (handle h : t) {
-            auto tinfo2 = get_type_info((PyTypeObject *) h.ptr());
-            if (tinfo2)
+            auto *tinfo2 = get_type_info((PyTypeObject *) h.ptr());
+            if (tinfo2) {
                 tinfo2->simple_type = false;
+            }
             mark_parents_nonsimple((PyTypeObject *) h.ptr());
         }
     }
 
-    void install_buffer_funcs(
-            buffer_info *(*get_buffer)(PyObject *, void *),
-            void *get_buffer_data) {
-        auto *type = (PyHeapTypeObject*) m_ptr;
-        auto tinfo = detail::get_type_info(&type->ht_type);
+    void install_buffer_funcs(buffer_info *(*get_buffer)(PyObject *, void *),
+                              void *get_buffer_data) {
+        auto *type = (PyHeapTypeObject *) m_ptr;
+        auto *tinfo = detail::get_type_info(&type->ht_type);
 
-        if (!type->ht_type.tp_as_buffer)
-            pybind11_fail(
-                "To be able to register buffer protocol support for the type '" +
-                get_fully_qualified_tp_name(tinfo->type) +
-                "' the associated class<>(..) invocation must "
-                "include the pybind11::buffer_protocol() annotation!");
+        if (!type->ht_type.tp_as_buffer) {
+            pybind11_fail("To be able to register buffer protocol support for the type '"
+                          + get_fully_qualified_tp_name(tinfo->type)
+                          + "' the associated class<>(..) invocation must "
+                            "include the pybind11::buffer_protocol() annotation!");
+        }
 
         tinfo->get_buffer = get_buffer;
         tinfo->get_buffer_data = get_buffer_data;
@@ -1111,60 +1374,79 @@ class generic_type : public object {
 
     // rec_func must be set for either fget or fset.
     void def_property_static_impl(const char *name,
-                                  handle fget, handle fset,
+                                  handle fget,
+                                  handle fset,
                                   detail::function_record *rec_func) {
-        const auto is_static = rec_func && !(rec_func->is_method && rec_func->scope);
-        const auto has_doc = rec_func && rec_func->doc && pybind11::options::show_user_defined_docstrings();
-        auto property = handle((PyObject *) (is_static ? get_internals().static_property_type
-                                                       : &PyProperty_Type));
+        const auto is_static = (rec_func != nullptr) && !(rec_func->is_method && rec_func->scope);
+        const auto has_doc = (rec_func != nullptr) && (rec_func->doc != nullptr)
+                             && pybind11::options::show_user_defined_docstrings();
+        auto property = handle(
+            (PyObject *) (is_static ? get_internals().static_property_type : &PyProperty_Type));
         attr(name) = property(fget.ptr() ? fget : none(),
                               fset.ptr() ? fset : none(),
-                              /*deleter*/none(),
+                              /*deleter*/ none(),
                               pybind11::str(has_doc ? rec_func->doc : ""));
     }
 };
 
 /// Set the pointer to operator new if it exists. The cast is needed because it can be overloaded.
-template <typename T, typename = void_t<decltype(static_cast<void *(*)(size_t)>(T::operator new))>>
-void set_operator_new(type_record *r) { r->operator_new = &T::operator new; }
-
-template <typename> void set_operator_new(...) { }
+template <typename T,
+          typename = void_t<decltype(static_cast<void *(*) (size_t)>(T::operator new))>>
+void set_operator_new(type_record *r) {
+    r->operator_new = &T::operator new;
+}
 
-template <typename T, typename SFINAE = void> struct has_operator_delete : std::false_type { };
-template <typename T> struct has_operator_delete<T, void_t<decltype(static_cast<void (*)(void *)>(T::operator delete))>>
-    : std::true_type { };
-template <typename T, typename SFINAE = void> struct has_operator_delete_size : std::false_type { };
-template <typename T> struct has_operator_delete_size<T, void_t<decltype(static_cast<void (*)(void *, size_t)>(T::operator delete))>>
-    : std::true_type { };
+template <typename>
+void set_operator_new(...) {}
+
+template <typename T, typename SFINAE = void>
+struct has_operator_delete : std::false_type {};
+template <typename T>
+struct has_operator_delete<T, void_t<decltype(static_cast<void (*)(void *)>(T::operator delete))>>
+    : std::true_type {};
+template <typename T, typename SFINAE = void>
+struct has_operator_delete_size : std::false_type {};
+template <typename T>
+struct has_operator_delete_size<
+    T,
+    void_t<decltype(static_cast<void (*)(void *, size_t)>(T::operator delete))>> : std::true_type {
+};
 /// Call class-specific delete if it exists or global otherwise. Can also be an overload set.
 template <typename T, enable_if_t<has_operator_delete<T>::value, int> = 0>
-void call_operator_delete(T *p, size_t, size_t) { T::operator delete(p); }
-template <typename T, enable_if_t<!has_operator_delete<T>::value && has_operator_delete_size<T>::value, int> = 0>
-void call_operator_delete(T *p, size_t s, size_t) { T::operator delete(p, s); }
+void call_operator_delete(T *p, size_t, size_t) {
+    T::operator delete(p);
+}
+template <
+    typename T,
+    enable_if_t<!has_operator_delete<T>::value && has_operator_delete_size<T>::value, int> = 0>
+void call_operator_delete(T *p, size_t s, size_t) {
+    T::operator delete(p, s);
+}
 
 inline void call_operator_delete(void *p, size_t s, size_t a) {
-    (void)s; (void)a;
-    #if defined(__cpp_aligned_new) && (!defined(_MSC_VER) || _MSC_VER >= 1912)
-        if (a > __STDCPP_DEFAULT_NEW_ALIGNMENT__) {
-            #ifdef __cpp_sized_deallocation
-                ::operator delete(p, s, std::align_val_t(a));
-            #else
-                ::operator delete(p, std::align_val_t(a));
-            #endif
-            return;
-        }
-    #endif
-    #ifdef __cpp_sized_deallocation
-        ::operator delete(p, s);
-    #else
-        ::operator delete(p);
-    #endif
+    (void) s;
+    (void) a;
+#if defined(__cpp_aligned_new) && (!defined(_MSC_VER) || _MSC_VER >= 1912)
+    if (a > __STDCPP_DEFAULT_NEW_ALIGNMENT__) {
+#    ifdef __cpp_sized_deallocation
+        ::operator delete(p, s, std::align_val_t(a));
+#    else
+        ::operator delete(p, std::align_val_t(a));
+#    endif
+        return;
+    }
+#endif
+#ifdef __cpp_sized_deallocation
+    ::operator delete(p, s);
+#else
+    ::operator delete(p);
+#endif
 }
 
-inline void add_class_method(object& cls, const char *name_, const cpp_function &cf) {
+inline void add_class_method(object &cls, const char *name_, const cpp_function &cf) {
     cls.attr(cf.name()) = cf;
-    if (strcmp(name_, "__eq__") == 0 && !cls.attr("__dict__").contains("__hash__")) {
-      cls.attr("__hash__") = none();
+    if (std::strcmp(name_, "__eq__") == 0 && !cls.attr("__dict__").contains("__hash__")) {
+        cls.attr("__hash__") = none();
     }
 }
 
@@ -1173,30 +1455,37 @@ PYBIND11_NAMESPACE_END(detail)
 /// Given a pointer to a member function, cast it to its `Derived` version.
 /// Forward everything else unchanged.
 template <typename /*Derived*/, typename F>
-auto method_adaptor(F &&f) -> decltype(std::forward<F>(f)) { return std::forward<F>(f); }
+auto method_adaptor(F &&f) -> decltype(std::forward<F>(f)) {
+    return std::forward<F>(f);
+}
 
 template <typename Derived, typename Return, typename Class, typename... Args>
 auto method_adaptor(Return (Class::*pmf)(Args...)) -> Return (Derived::*)(Args...) {
-    static_assert(detail::is_accessible_base_of<Class, Derived>::value,
+    static_assert(
+        detail::is_accessible_base_of<Class, Derived>::value,
         "Cannot bind an inaccessible base class method; use a lambda definition instead");
     return pmf;
 }
 
 template <typename Derived, typename Return, typename Class, typename... Args>
 auto method_adaptor(Return (Class::*pmf)(Args...) const) -> Return (Derived::*)(Args...) const {
-    static_assert(detail::is_accessible_base_of<Class, Derived>::value,
+    static_assert(
+        detail::is_accessible_base_of<Class, Derived>::value,
         "Cannot bind an inaccessible base class method; use a lambda definition instead");
     return pmf;
 }
 
 template <typename type_, typename... options>
 class class_ : public detail::generic_type {
-    template <typename T> using is_holder = detail::is_holder_type<type_, T>;
-    template <typename T> using is_subtype = detail::is_strict_base_of<type_, T>;
-    template <typename T> using is_base = detail::is_strict_base_of<T, type_>;
+    template <typename T>
+    using is_holder = detail::is_holder_type<type_, T>;
+    template <typename T>
+    using is_subtype = detail::is_strict_base_of<type_, T>;
+    template <typename T>
+    using is_base = detail::is_strict_base_of<T, type_>;
     // struct instead of using here to help MSVC:
-    template <typename T> struct is_valid_class_option :
-        detail::any_of<is_holder<T>, is_subtype<T>, is_base<T>> {};
+    template <typename T>
+    struct is_valid_class_option : detail::any_of<is_holder<T>, is_subtype<T>, is_base<T>> {};
 
 public:
     using type = type_;
@@ -1205,23 +1494,24 @@ class class_ : public detail::generic_type {
     using holder_type = detail::exactly_one_t<is_holder, std::unique_ptr<type>, options...>;
 
     static_assert(detail::all_of<is_valid_class_option<options>...>::value,
-            "Unknown/invalid class_ template parameters provided");
+                  "Unknown/invalid class_ template parameters provided");
 
     static_assert(!has_alias || std::is_polymorphic<type>::value,
-            "Cannot use an alias class with a non-polymorphic type");
+                  "Cannot use an alias class with a non-polymorphic type");
 
     PYBIND11_OBJECT(class_, generic_type, PyType_Check)
 
     template <typename... Extra>
-    class_(handle scope, const char *name, const Extra &... extra) {
+    class_(handle scope, const char *name, const Extra &...extra) {
         using namespace detail;
 
         // MI can only be specified via class_ template options, not constructor parameters
         static_assert(
             none_of<is_pyobject<Extra>...>::value || // no base class arguments, or:
-            (   constexpr_sum(is_pyobject<Extra>::value...) == 1 && // Exactly one base
-                constexpr_sum(is_base<options>::value...)   == 0 && // no template option bases
-                none_of<std::is_same<multiple_inheritance, Extra>...>::value), // no multiple_inheritance attr
+                (constexpr_sum(is_pyobject<Extra>::value...) == 1 && // Exactly one base
+                 constexpr_sum(is_base<options>::value...) == 0 &&   // no template option bases
+                 // no multiple_inheritance attr
+                 none_of<std::is_same<multiple_inheritance, Extra>...>::value),
             "Error: multiple inheritance bases must be specified via class_ template options");
 
         type_record record;
@@ -1229,7 +1519,7 @@ class class_ : public detail::generic_type {
         record.name = name;
         record.type = &typeid(type);
         record.type_size = sizeof(conditional_t<has_alias, type_alias, type>);
-        record.type_align = alignof(conditional_t<has_alias, type_alias, type>&);
+        record.type_align = alignof(conditional_t<has_alias, type_alias, type> &);
         record.holder_size = sizeof(holder_type);
         record.init_instance = init_instance;
         record.dealloc = dealloc;
@@ -1246,8 +1536,10 @@ class class_ : public detail::generic_type {
         generic_type::initialize(record);
 
         if (has_alias) {
-            auto &instances = record.module_local ? registered_local_types_cpp() : get_internals().registered_types_cpp;
-            instances[std::type_index(typeid(type_alias))] = instances[std::type_index(typeid(type))];
+            auto &instances = record.module_local ? get_local_internals().registered_types_cpp
+                                                  : get_internals().registered_types_cpp;
+            instances[std::type_index(typeid(type_alias))]
+                = instances[std::type_index(typeid(type))];
         }
     }
 
@@ -1259,52 +1551,61 @@ class class_ : public detail::generic_type {
     }
 
     template <typename Base, detail::enable_if_t<!is_base<Base>::value, int> = 0>
-    static void add_base(detail::type_record &) { }
+    static void add_base(detail::type_record &) {}
 
     template <typename Func, typename... Extra>
-    class_ &def(const char *name_, Func&& f, const Extra&... extra) {
-        cpp_function cf(method_adaptor<type>(std::forward<Func>(f)), name(name_), is_method(*this),
-                        sibling(getattr(*this, name_, none())), extra...);
+    class_ &def(const char *name_, Func &&f, const Extra &...extra) {
+        cpp_function cf(method_adaptor<type>(std::forward<Func>(f)),
+                        name(name_),
+                        is_method(*this),
+                        sibling(getattr(*this, name_, none())),
+                        extra...);
         add_class_method(*this, name_, cf);
         return *this;
     }
 
-    template <typename Func, typename... Extra> class_ &
-    def_static(const char *name_, Func &&f, const Extra&... extra) {
+    template <typename Func, typename... Extra>
+    class_ &def_static(const char *name_, Func &&f, const Extra &...extra) {
         static_assert(!std::is_member_function_pointer<Func>::value,
-                "def_static(...) called with a non-static member function pointer");
-        cpp_function cf(std::forward<Func>(f), name(name_), scope(*this),
-                        sibling(getattr(*this, name_, none())), extra...);
-        attr(cf.name()) = staticmethod(cf);
+                      "def_static(...) called with a non-static member function pointer");
+        cpp_function cf(std::forward<Func>(f),
+                        name(name_),
+                        scope(*this),
+                        sibling(getattr(*this, name_, none())),
+                        extra...);
+        auto cf_name = cf.name();
+        attr(std::move(cf_name)) = staticmethod(std::move(cf));
         return *this;
     }
 
     template <detail::op_id id, detail::op_type ot, typename L, typename R, typename... Extra>
-    class_ &def(const detail::op_<id, ot, L, R> &op, const Extra&... extra) {
+    class_ &def(const detail::op_<id, ot, L, R> &op, const Extra &...extra) {
         op.execute(*this, extra...);
         return *this;
     }
 
     template <detail::op_id id, detail::op_type ot, typename L, typename R, typename... Extra>
-    class_ & def_cast(const detail::op_<id, ot, L, R> &op, const Extra&... extra) {
+    class_ &def_cast(const detail::op_<id, ot, L, R> &op, const Extra &...extra) {
         op.execute_cast(*this, extra...);
         return *this;
     }
 
     template <typename... Args, typename... Extra>
-    class_ &def(const detail::initimpl::constructor<Args...> &init, const Extra&... extra) {
+    class_ &def(const detail::initimpl::constructor<Args...> &init, const Extra &...extra) {
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(init);
         init.execute(*this, extra...);
         return *this;
     }
 
     template <typename... Args, typename... Extra>
-    class_ &def(const detail::initimpl::alias_constructor<Args...> &init, const Extra&... extra) {
+    class_ &def(const detail::initimpl::alias_constructor<Args...> &init, const Extra &...extra) {
+        PYBIND11_WORKAROUND_INCORRECT_MSVC_C4100(init);
         init.execute(*this, extra...);
         return *this;
     }
 
     template <typename... Args, typename... Extra>
-    class_ &def(detail::initimpl::factory<Args...> &&init, const Extra&... extra) {
+    class_ &def(detail::initimpl::factory<Args...> &&init, const Extra &...extra) {
         std::move(init).execute(*this, extra...);
         return *this;
     }
@@ -1316,135 +1617,170 @@ class class_ : public detail::generic_type {
     }
 
     template <typename Func>
-    class_& def_buffer(Func &&func) {
-        struct capture { Func func; };
-        auto *ptr = new capture { std::forward<Func>(func) };
-        install_buffer_funcs([](PyObject *obj, void *ptr) -> buffer_info* {
-            detail::make_caster<type> caster;
-            if (!caster.load(obj, false))
-                return nullptr;
-            return new buffer_info(((capture *) ptr)->func(caster));
-        }, ptr);
+    class_ &def_buffer(Func &&func) {
+        struct capture {
+            Func func;
+        };
+        auto *ptr = new capture{std::forward<Func>(func)};
+        install_buffer_funcs(
+            [](PyObject *obj, void *ptr) -> buffer_info * {
+                detail::make_caster<type> caster;
+                if (!caster.load(obj, false)) {
+                    return nullptr;
+                }
+                return new buffer_info(((capture *) ptr)->func(std::move(caster)));
+            },
+            ptr);
         weakref(m_ptr, cpp_function([ptr](handle wr) {
-            delete ptr;
-            wr.dec_ref();
-        })).release();
+                    delete ptr;
+                    wr.dec_ref();
+                }))
+            .release();
         return *this;
     }
 
     template <typename Return, typename Class, typename... Args>
     class_ &def_buffer(Return (Class::*func)(Args...)) {
-        return def_buffer([func] (type &obj) { return (obj.*func)(); });
+        return def_buffer([func](type &obj) { return (obj.*func)(); });
     }
 
     template <typename Return, typename Class, typename... Args>
     class_ &def_buffer(Return (Class::*func)(Args...) const) {
-        return def_buffer([func] (const type &obj) { return (obj.*func)(); });
+        return def_buffer([func](const type &obj) { return (obj.*func)(); });
     }
 
     template <typename C, typename D, typename... Extra>
-    class_ &def_readwrite(const char *name, D C::*pm, const Extra&... extra) {
-        static_assert(std::is_same<C, type>::value || std::is_base_of<C, type>::value, "def_readwrite() requires a class member (or base class member)");
-        cpp_function fget([pm](const type &c) -> const D &{ return c.*pm; }, is_method(*this)),
-                     fset([pm](type &c, const D &value) { c.*pm = value; }, is_method(*this));
+    class_ &def_readwrite(const char *name, D C::*pm, const Extra &...extra) {
+        static_assert(std::is_same<C, type>::value || std::is_base_of<C, type>::value,
+                      "def_readwrite() requires a class member (or base class member)");
+        cpp_function fget([pm](const type &c) -> const D & { return c.*pm; }, is_method(*this)),
+            fset([pm](type &c, const D &value) { c.*pm = value; }, is_method(*this));
         def_property(name, fget, fset, return_value_policy::reference_internal, extra...);
         return *this;
     }
 
     template <typename C, typename D, typename... Extra>
-    class_ &def_readonly(const char *name, const D C::*pm, const Extra& ...extra) {
-        static_assert(std::is_same<C, type>::value || std::is_base_of<C, type>::value, "def_readonly() requires a class member (or base class member)");
-        cpp_function fget([pm](const type &c) -> const D &{ return c.*pm; }, is_method(*this));
+    class_ &def_readonly(const char *name, const D C::*pm, const Extra &...extra) {
+        static_assert(std::is_same<C, type>::value || std::is_base_of<C, type>::value,
+                      "def_readonly() requires a class member (or base class member)");
+        cpp_function fget([pm](const type &c) -> const D & { return c.*pm; }, is_method(*this));
         def_property_readonly(name, fget, return_value_policy::reference_internal, extra...);
         return *this;
     }
 
     template <typename D, typename... Extra>
-    class_ &def_readwrite_static(const char *name, D *pm, const Extra& ...extra) {
-        cpp_function fget([pm](object) -> const D &{ return *pm; }, scope(*this)),
-                     fset([pm](object, const D &value) { *pm = value; }, scope(*this));
+    class_ &def_readwrite_static(const char *name, D *pm, const Extra &...extra) {
+        cpp_function fget([pm](const object &) -> const D & { return *pm; }, scope(*this)),
+            fset([pm](const object &, const D &value) { *pm = value; }, scope(*this));
         def_property_static(name, fget, fset, return_value_policy::reference, extra...);
         return *this;
     }
 
     template <typename D, typename... Extra>
-    class_ &def_readonly_static(const char *name, const D *pm, const Extra& ...extra) {
-        cpp_function fget([pm](object) -> const D &{ return *pm; }, scope(*this));
+    class_ &def_readonly_static(const char *name, const D *pm, const Extra &...extra) {
+        cpp_function fget([pm](const object &) -> const D & { return *pm; }, scope(*this));
         def_property_readonly_static(name, fget, return_value_policy::reference, extra...);
         return *this;
     }
 
     /// Uses return_value_policy::reference_internal by default
     template <typename Getter, typename... Extra>
-    class_ &def_property_readonly(const char *name, const Getter &fget, const Extra& ...extra) {
-        return def_property_readonly(name, cpp_function(method_adaptor<type>(fget)),
-                                     return_value_policy::reference_internal, extra...);
+    class_ &def_property_readonly(const char *name, const Getter &fget, const Extra &...extra) {
+        return def_property_readonly(name,
+                                     cpp_function(method_adaptor<type>(fget)),
+                                     return_value_policy::reference_internal,
+                                     extra...);
     }
 
     /// Uses cpp_function's return_value_policy by default
     template <typename... Extra>
-    class_ &def_property_readonly(const char *name, const cpp_function &fget, const Extra& ...extra) {
+    class_ &
+    def_property_readonly(const char *name, const cpp_function &fget, const Extra &...extra) {
         return def_property(name, fget, nullptr, extra...);
     }
 
     /// Uses return_value_policy::reference by default
     template <typename Getter, typename... Extra>
-    class_ &def_property_readonly_static(const char *name, const Getter &fget, const Extra& ...extra) {
-        return def_property_readonly_static(name, cpp_function(fget), return_value_policy::reference, extra...);
+    class_ &
+    def_property_readonly_static(const char *name, const Getter &fget, const Extra &...extra) {
+        return def_property_readonly_static(
+            name, cpp_function(fget), return_value_policy::reference, extra...);
     }
 
     /// Uses cpp_function's return_value_policy by default
     template <typename... Extra>
-    class_ &def_property_readonly_static(const char *name, const cpp_function &fget, const Extra& ...extra) {
+    class_ &def_property_readonly_static(const char *name,
+                                         const cpp_function &fget,
+                                         const Extra &...extra) {
         return def_property_static(name, fget, nullptr, extra...);
     }
 
     /// Uses return_value_policy::reference_internal by default
     template <typename Getter, typename Setter, typename... Extra>
-    class_ &def_property(const char *name, const Getter &fget, const Setter &fset, const Extra& ...extra) {
+    class_ &
+    def_property(const char *name, const Getter &fget, const Setter &fset, const Extra &...extra) {
         return def_property(name, fget, cpp_function(method_adaptor<type>(fset)), extra...);
     }
     template <typename Getter, typename... Extra>
-    class_ &def_property(const char *name, const Getter &fget, const cpp_function &fset, const Extra& ...extra) {
-        return def_property(name, cpp_function(method_adaptor<type>(fget)), fset,
-                            return_value_policy::reference_internal, extra...);
+    class_ &def_property(const char *name,
+                         const Getter &fget,
+                         const cpp_function &fset,
+                         const Extra &...extra) {
+        return def_property(name,
+                            cpp_function(method_adaptor<type>(fget)),
+                            fset,
+                            return_value_policy::reference_internal,
+                            extra...);
     }
 
     /// Uses cpp_function's return_value_policy by default
     template <typename... Extra>
-    class_ &def_property(const char *name, const cpp_function &fget, const cpp_function &fset, const Extra& ...extra) {
+    class_ &def_property(const char *name,
+                         const cpp_function &fget,
+                         const cpp_function &fset,
+                         const Extra &...extra) {
         return def_property_static(name, fget, fset, is_method(*this), extra...);
     }
 
     /// Uses return_value_policy::reference by default
     template <typename Getter, typename... Extra>
-    class_ &def_property_static(const char *name, const Getter &fget, const cpp_function &fset, const Extra& ...extra) {
-        return def_property_static(name, cpp_function(fget), fset, return_value_policy::reference, extra...);
+    class_ &def_property_static(const char *name,
+                                const Getter &fget,
+                                const cpp_function &fset,
+                                const Extra &...extra) {
+        return def_property_static(
+            name, cpp_function(fget), fset, return_value_policy::reference, extra...);
     }
 
     /// Uses cpp_function's return_value_policy by default
     template <typename... Extra>
-    class_ &def_property_static(const char *name, const cpp_function &fget, const cpp_function &fset, const Extra& ...extra) {
-        static_assert( 0 == detail::constexpr_sum(std::is_base_of<arg, Extra>::value...),
+    class_ &def_property_static(const char *name,
+                                const cpp_function &fget,
+                                const cpp_function &fset,
+                                const Extra &...extra) {
+        static_assert(0 == detail::constexpr_sum(std::is_base_of<arg, Extra>::value...),
                       "Argument annotations are not allowed for properties");
         auto rec_fget = get_function_record(fget), rec_fset = get_function_record(fset);
         auto *rec_active = rec_fget;
         if (rec_fget) {
-           char *doc_prev = rec_fget->doc; /* 'extra' field may include a property-specific documentation string */
-           detail::process_attributes<Extra...>::init(extra..., rec_fget);
-           if (rec_fget->doc && rec_fget->doc != doc_prev) {
-              free(doc_prev);
-              rec_fget->doc = strdup(rec_fget->doc);
-           }
+            char *doc_prev = rec_fget->doc; /* 'extra' field may include a property-specific
+                                               documentation string */
+            detail::process_attributes<Extra...>::init(extra..., rec_fget);
+            if (rec_fget->doc && rec_fget->doc != doc_prev) {
+                std::free(doc_prev);
+                rec_fget->doc = PYBIND11_COMPAT_STRDUP(rec_fget->doc);
+            }
         }
         if (rec_fset) {
             char *doc_prev = rec_fset->doc;
             detail::process_attributes<Extra...>::init(extra..., rec_fset);
             if (rec_fset->doc && rec_fset->doc != doc_prev) {
-                free(doc_prev);
-                rec_fset->doc = strdup(rec_fset->doc);
+                std::free(doc_prev);
+                rec_fset->doc = PYBIND11_COMPAT_STRDUP(rec_fset->doc);
+            }
+            if (!rec_active) {
+                rec_active = rec_fset;
             }
-            if (! rec_active) rec_active = rec_fset;
         }
         def_property_static_impl(name, fget, fset, rec_active);
         return *this;
@@ -1453,16 +1789,17 @@ class class_ : public detail::generic_type {
 private:
     /// Initialize holder object, variant 1: object derives from enable_shared_from_this
     template <typename T>
-    static void init_holder(detail::instance *inst, detail::value_and_holder &v_h,
-            const holder_type * /* unused */, const std::enable_shared_from_this<T> * /* dummy */) {
-        try {
-            auto sh = std::dynamic_pointer_cast<typename holder_type::element_type>(
-                    v_h.value_ptr<type>()->shared_from_this());
-            if (sh) {
-                new (std::addressof(v_h.holder<holder_type>())) holder_type(std::move(sh));
-                v_h.set_holder_constructed();
-            }
-        } catch (const std::bad_weak_ptr &) {}
+    static void init_holder(detail::instance *inst,
+                            detail::value_and_holder &v_h,
+                            const holder_type * /* unused */,
+                            const std::enable_shared_from_this<T> * /* dummy */) {
+
+        auto sh = std::dynamic_pointer_cast<typename holder_type::element_type>(
+            detail::try_get_shared_from_this(v_h.value_ptr<type>()));
+        if (sh) {
+            new (std::addressof(v_h.holder<holder_type>())) holder_type(std::move(sh));
+            v_h.set_holder_constructed();
+        }
 
         if (!v_h.holder_constructed() && inst->owned) {
             new (std::addressof(v_h.holder<holder_type>())) holder_type(v_h.value_ptr<type>());
@@ -1471,30 +1808,38 @@ class class_ : public detail::generic_type {
     }
 
     static void init_holder_from_existing(const detail::value_and_holder &v_h,
-            const holder_type *holder_ptr, std::true_type /*is_copy_constructible*/) {
-        new (std::addressof(v_h.holder<holder_type>())) holder_type(*reinterpret_cast<const holder_type *>(holder_ptr));
+                                          const holder_type *holder_ptr,
+                                          std::true_type /*is_copy_constructible*/) {
+        new (std::addressof(v_h.holder<holder_type>()))
+            holder_type(*reinterpret_cast<const holder_type *>(holder_ptr));
     }
 
     static void init_holder_from_existing(const detail::value_and_holder &v_h,
-            const holder_type *holder_ptr, std::false_type /*is_copy_constructible*/) {
-        new (std::addressof(v_h.holder<holder_type>())) holder_type(std::move(*const_cast<holder_type *>(holder_ptr)));
-    }
-
-    /// Initialize holder object, variant 2: try to construct from existing holder object, if possible
-    static void init_holder(detail::instance *inst, detail::value_and_holder &v_h,
-            const holder_type *holder_ptr, const void * /* dummy -- not enable_shared_from_this<T>) */) {
+                                          const holder_type *holder_ptr,
+                                          std::false_type /*is_copy_constructible*/) {
+        new (std::addressof(v_h.holder<holder_type>()))
+            holder_type(std::move(*const_cast<holder_type *>(holder_ptr)));
+    }
+
+    /// Initialize holder object, variant 2: try to construct from existing holder object, if
+    /// possible
+    static void init_holder(detail::instance *inst,
+                            detail::value_and_holder &v_h,
+                            const holder_type *holder_ptr,
+                            const void * /* dummy -- not enable_shared_from_this<T>) */) {
         if (holder_ptr) {
             init_holder_from_existing(v_h, holder_ptr, std::is_copy_constructible<holder_type>());
             v_h.set_holder_constructed();
-        } else if (inst->owned || detail::always_construct_holder<holder_type>::value) {
+        } else if (PYBIND11_SILENCE_MSVC_C4127(detail::always_construct_holder<holder_type>::value)
+                   || inst->owned) {
             new (std::addressof(v_h.holder<holder_type>())) holder_type(v_h.value_ptr<type>());
             v_h.set_holder_constructed();
         }
     }
 
     /// Performs instance initialization including constructing a holder and registering the known
-    /// instance.  Should be called as soon as the `type` value_ptr is set for an instance.  Takes an
-    /// optional pointer to an existing holder to use; if not specified and the instance is
+    /// instance.  Should be called as soon as the `type` value_ptr is set for an instance.  Takes
+    /// an optional pointer to an existing holder to use; if not specified and the instance is
     /// `.owned`, a new holder will be constructed to manage the value pointer.
     static void init_instance(detail::instance *inst, const void *holder_ptr) {
         auto v_h = inst->get_value_and_holder(detail::get_type_info(typeid(type)));
@@ -1517,35 +1862,42 @@ class class_ : public detail::generic_type {
         if (v_h.holder_constructed()) {
             v_h.holder<holder_type>().~holder_type();
             v_h.set_holder_constructed(false);
-        }
-        else {
-            detail::call_operator_delete(v_h.value_ptr<type>(),
-                v_h.type->type_size,
-                v_h.type->type_align
-            );
+        } else {
+            detail::call_operator_delete(
+                v_h.value_ptr<type>(), v_h.type->type_size, v_h.type->type_align);
         }
         v_h.value_ptr() = nullptr;
     }
 
     static detail::function_record *get_function_record(handle h) {
         h = detail::get_function(h);
-        return h ? (detail::function_record *) reinterpret_borrow<capsule>(PyCFunction_GET_SELF(h.ptr()))
+        return h ? (detail::function_record *) reinterpret_borrow<capsule>(
+                   PyCFunction_GET_SELF(h.ptr()))
                  : nullptr;
     }
 };
 
 /// Binds an existing constructor taking arguments Args...
-template <typename... Args> detail::initimpl::constructor<Args...> init() { return {}; }
+template <typename... Args>
+detail::initimpl::constructor<Args...> init() {
+    return {};
+}
 /// Like `init<Args...>()`, but the instance is always constructed through the alias class (even
 /// when not inheriting on the Python side).
-template <typename... Args> detail::initimpl::alias_constructor<Args...> init_alias() { return {}; }
+template <typename... Args>
+detail::initimpl::alias_constructor<Args...> init_alias() {
+    return {};
+}
 
 /// Binds a factory function as a constructor
 template <typename Func, typename Ret = detail::initimpl::factory<Func>>
-Ret init(Func &&f) { return {std::forward<Func>(f)}; }
+Ret init(Func &&f) {
+    return {std::forward<Func>(f)};
+}
 
-/// Dual-argument factory function: the first function is called when no alias is needed, the second
-/// when an alias is needed (i.e. due to python-side inheritance).  Arguments must be identical.
+/// Dual-argument factory function: the first function is called when no alias is needed, the
+/// second when an alias is needed (i.e. due to python-side inheritance).  Arguments must be
+/// identical.
 template <typename CFunc, typename AFunc, typename Ret = detail::initimpl::factory<CFunc, AFunc>>
 Ret init(CFunc &&c, AFunc &&a) {
     return {std::forward<CFunc>(c), std::forward<AFunc>(a)};
@@ -1563,14 +1915,15 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 inline str enum_name(handle arg) {
     dict entries = arg.get_type().attr("__entries");
     for (auto kv : entries) {
-        if (handle(kv.second[int_(0)]).equal(arg))
+        if (handle(kv.second[int_(0)]).equal(arg)) {
             return pybind11::str(kv.first);
+        }
     }
     return "???";
 }
 
 struct enum_base {
-    enum_base(handle base, handle parent) : m_base(base), m_parent(parent) { }
+    enum_base(const handle &base, const handle &parent) : m_base(base), m_parent(parent) {}
 
     PYBIND11_NOINLINE void init(bool is_arithmetic, bool is_convertible) {
         m_base.attr("__entries") = dict();
@@ -1578,183 +1931,250 @@ struct enum_base {
         auto static_property = handle((PyObject *) get_internals().static_property_type);
 
         m_base.attr("__repr__") = cpp_function(
-            [](object arg) -> str {
+            [](const object &arg) -> str {
                 handle type = type::handle_of(arg);
                 object type_name = type.attr("__name__");
-                return pybind11::str("<{}.{}: {}>").format(type_name, enum_name(arg), int_(arg));
-            }, name("__repr__"), is_method(m_base)
-        );
+                return pybind11::str("<{}.{}: {}>")
+                    .format(std::move(type_name), enum_name(arg), int_(arg));
+            },
+            name("__repr__"),
+            is_method(m_base));
 
         m_base.attr("name") = property(cpp_function(&enum_name, name("name"), is_method(m_base)));
 
         m_base.attr("__str__") = cpp_function(
             [](handle arg) -> str {
                 object type_name = type::handle_of(arg).attr("__name__");
-                return pybind11::str("{}.{}").format(type_name, enum_name(arg));
-            }, name("name"), is_method(m_base)
-        );
-
-        m_base.attr("__doc__") = static_property(cpp_function(
-            [](handle arg) -> std::string {
-                std::string docstring;
-                dict entries = arg.attr("__entries");
-                if (((PyTypeObject *) arg.ptr())->tp_doc)
-                    docstring += std::string(((PyTypeObject *) arg.ptr())->tp_doc) + "\n\n";
-                docstring += "Members:";
-                for (auto kv : entries) {
-                    auto key = std::string(pybind11::str(kv.first));
-                    auto comment = kv.second[int_(1)];
-                    docstring += "\n\n  " + key;
-                    if (!comment.is_none())
-                        docstring += " : " + (std::string) pybind11::str(comment);
-                }
-                return docstring;
-            }, name("__doc__")
-        ), none(), none(), "");
+                return pybind11::str("{}.{}").format(std::move(type_name), enum_name(arg));
+            },
+            name("name"),
+            is_method(m_base));
+
+        m_base.attr("__doc__") = static_property(
+            cpp_function(
+                [](handle arg) -> std::string {
+                    std::string docstring;
+                    dict entries = arg.attr("__entries");
+                    if (((PyTypeObject *) arg.ptr())->tp_doc) {
+                        docstring += std::string(((PyTypeObject *) arg.ptr())->tp_doc) + "\n\n";
+                    }
+                    docstring += "Members:";
+                    for (auto kv : entries) {
+                        auto key = std::string(pybind11::str(kv.first));
+                        auto comment = kv.second[int_(1)];
+                        docstring += "\n\n  " + key;
+                        if (!comment.is_none()) {
+                            docstring += " : " + (std::string) pybind11::str(comment);
+                        }
+                    }
+                    return docstring;
+                },
+                name("__doc__")),
+            none(),
+            none(),
+            "");
 
         m_base.attr("__members__") = static_property(cpp_function(
-            [](handle arg) -> dict {
-                dict entries = arg.attr("__entries"), m;
-                for (auto kv : entries)
-                    m[kv.first] = kv.second[int_(0)];
-                return m;
-            }, name("__members__")), none(), none(), ""
-        );
-
-        #define PYBIND11_ENUM_OP_STRICT(op, expr, strict_behavior)                     \
-            m_base.attr(op) = cpp_function(                                            \
-                [](object a, object b) {                                               \
-                    if (!type::handle_of(a).is(type::handle_of(b)))                    \
-                        strict_behavior;                                               \
-                    return expr;                                                       \
-                },                                                                     \
-                name(op), is_method(m_base), arg("other"))
-
-        #define PYBIND11_ENUM_OP_CONV(op, expr)                                        \
-            m_base.attr(op) = cpp_function(                                            \
-                [](object a_, object b_) {                                             \
-                    int_ a(a_), b(b_);                                                 \
-                    return expr;                                                       \
-                },                                                                     \
-                name(op), is_method(m_base), arg("other"))
-
-        #define PYBIND11_ENUM_OP_CONV_LHS(op, expr)                                    \
-            m_base.attr(op) = cpp_function(                                            \
-                [](object a_, object b) {                                              \
-                    int_ a(a_);                                                        \
-                    return expr;                                                       \
-                },                                                                     \
-                name(op), is_method(m_base), arg("other"))
+                                                         [](handle arg) -> dict {
+                                                             dict entries = arg.attr("__entries"),
+                                                                  m;
+                                                             for (auto kv : entries) {
+                                                                 m[kv.first] = kv.second[int_(0)];
+                                                             }
+                                                             return m;
+                                                         },
+                                                         name("__members__")),
+                                                     none(),
+                                                     none(),
+                                                     "");
+
+#define PYBIND11_ENUM_OP_STRICT(op, expr, strict_behavior)                                        \
+    m_base.attr(op) = cpp_function(                                                               \
+        [](const object &a, const object &b) {                                                    \
+            if (!type::handle_of(a).is(type::handle_of(b)))                                       \
+                strict_behavior; /* NOLINT(bugprone-macro-parentheses) */                         \
+            return expr;                                                                          \
+        },                                                                                        \
+        name(op),                                                                                 \
+        is_method(m_base),                                                                        \
+        arg("other"))
+
+#define PYBIND11_ENUM_OP_CONV(op, expr)                                                           \
+    m_base.attr(op) = cpp_function(                                                               \
+        [](const object &a_, const object &b_) {                                                  \
+            int_ a(a_), b(b_);                                                                    \
+            return expr;                                                                          \
+        },                                                                                        \
+        name(op),                                                                                 \
+        is_method(m_base),                                                                        \
+        arg("other"))
+
+#define PYBIND11_ENUM_OP_CONV_LHS(op, expr)                                                       \
+    m_base.attr(op) = cpp_function(                                                               \
+        [](const object &a_, const object &b) {                                                   \
+            int_ a(a_);                                                                           \
+            return expr;                                                                          \
+        },                                                                                        \
+        name(op),                                                                                 \
+        is_method(m_base),                                                                        \
+        arg("other"))
 
         if (is_convertible) {
-            PYBIND11_ENUM_OP_CONV_LHS("__eq__", !b.is_none() &&  a.equal(b));
-            PYBIND11_ENUM_OP_CONV_LHS("__ne__",  b.is_none() || !a.equal(b));
+            PYBIND11_ENUM_OP_CONV_LHS("__eq__", !b.is_none() && a.equal(b));
+            PYBIND11_ENUM_OP_CONV_LHS("__ne__", b.is_none() || !a.equal(b));
 
             if (is_arithmetic) {
-                PYBIND11_ENUM_OP_CONV("__lt__",   a <  b);
-                PYBIND11_ENUM_OP_CONV("__gt__",   a >  b);
-                PYBIND11_ENUM_OP_CONV("__le__",   a <= b);
-                PYBIND11_ENUM_OP_CONV("__ge__",   a >= b);
-                PYBIND11_ENUM_OP_CONV("__and__",  a &  b);
-                PYBIND11_ENUM_OP_CONV("__rand__", a &  b);
-                PYBIND11_ENUM_OP_CONV("__or__",   a |  b);
-                PYBIND11_ENUM_OP_CONV("__ror__",  a |  b);
-                PYBIND11_ENUM_OP_CONV("__xor__",  a ^  b);
-                PYBIND11_ENUM_OP_CONV("__rxor__", a ^  b);
-                m_base.attr("__invert__") = cpp_function(
-                    [](object arg) { return ~(int_(arg)); }, name("__invert__"), is_method(m_base));
+                PYBIND11_ENUM_OP_CONV("__lt__", a < b);
+                PYBIND11_ENUM_OP_CONV("__gt__", a > b);
+                PYBIND11_ENUM_OP_CONV("__le__", a <= b);
+                PYBIND11_ENUM_OP_CONV("__ge__", a >= b);
+                PYBIND11_ENUM_OP_CONV("__and__", a & b);
+                PYBIND11_ENUM_OP_CONV("__rand__", a & b);
+                PYBIND11_ENUM_OP_CONV("__or__", a | b);
+                PYBIND11_ENUM_OP_CONV("__ror__", a | b);
+                PYBIND11_ENUM_OP_CONV("__xor__", a ^ b);
+                PYBIND11_ENUM_OP_CONV("__rxor__", a ^ b);
+                m_base.attr("__invert__")
+                    = cpp_function([](const object &arg) { return ~(int_(arg)); },
+                                   name("__invert__"),
+                                   is_method(m_base));
             }
         } else {
-            PYBIND11_ENUM_OP_STRICT("__eq__",  int_(a).equal(int_(b)), return false);
+            PYBIND11_ENUM_OP_STRICT("__eq__", int_(a).equal(int_(b)), return false);
             PYBIND11_ENUM_OP_STRICT("__ne__", !int_(a).equal(int_(b)), return true);
 
             if (is_arithmetic) {
-                #define PYBIND11_THROW throw type_error("Expected an enumeration of matching type!");
-                PYBIND11_ENUM_OP_STRICT("__lt__", int_(a) <  int_(b), PYBIND11_THROW);
-                PYBIND11_ENUM_OP_STRICT("__gt__", int_(a) >  int_(b), PYBIND11_THROW);
+#define PYBIND11_THROW throw type_error("Expected an enumeration of matching type!");
+                PYBIND11_ENUM_OP_STRICT("__lt__", int_(a) < int_(b), PYBIND11_THROW);
+                PYBIND11_ENUM_OP_STRICT("__gt__", int_(a) > int_(b), PYBIND11_THROW);
                 PYBIND11_ENUM_OP_STRICT("__le__", int_(a) <= int_(b), PYBIND11_THROW);
                 PYBIND11_ENUM_OP_STRICT("__ge__", int_(a) >= int_(b), PYBIND11_THROW);
-                #undef PYBIND11_THROW
+#undef PYBIND11_THROW
             }
         }
 
-        #undef PYBIND11_ENUM_OP_CONV_LHS
-        #undef PYBIND11_ENUM_OP_CONV
-        #undef PYBIND11_ENUM_OP_STRICT
+#undef PYBIND11_ENUM_OP_CONV_LHS
+#undef PYBIND11_ENUM_OP_CONV
+#undef PYBIND11_ENUM_OP_STRICT
 
         m_base.attr("__getstate__") = cpp_function(
-            [](object arg) { return int_(arg); }, name("__getstate__"), is_method(m_base));
+            [](const object &arg) { return int_(arg); }, name("__getstate__"), is_method(m_base));
 
         m_base.attr("__hash__") = cpp_function(
-            [](object arg) { return int_(arg); }, name("__hash__"), is_method(m_base));
+            [](const object &arg) { return int_(arg); }, name("__hash__"), is_method(m_base));
     }
 
-    PYBIND11_NOINLINE void value(char const* name_, object value, const char *doc = nullptr) {
+    PYBIND11_NOINLINE void value(char const *name_, object value, const char *doc = nullptr) {
         dict entries = m_base.attr("__entries");
         str name(name_);
         if (entries.contains(name)) {
             std::string type_name = (std::string) str(m_base.attr("__name__"));
-            throw value_error(type_name + ": element \"" + std::string(name_) + "\" already exists!");
+            throw value_error(std::move(type_name) + ": element \"" + std::string(name_)
+                              + "\" already exists!");
         }
 
-        entries[name] = std::make_pair(value, doc);
-        m_base.attr(name) = value;
+        entries[name] = pybind11::make_tuple(value, doc);
+        m_base.attr(std::move(name)) = std::move(value);
     }
 
     PYBIND11_NOINLINE void export_values() {
         dict entries = m_base.attr("__entries");
-        for (auto kv : entries)
+        for (auto kv : entries) {
             m_parent.attr(kv.first) = kv.second[int_(0)];
+        }
     }
 
     handle m_base;
     handle m_parent;
 };
 
+template <bool is_signed, size_t length>
+struct equivalent_integer {};
+template <>
+struct equivalent_integer<true, 1> {
+    using type = int8_t;
+};
+template <>
+struct equivalent_integer<false, 1> {
+    using type = uint8_t;
+};
+template <>
+struct equivalent_integer<true, 2> {
+    using type = int16_t;
+};
+template <>
+struct equivalent_integer<false, 2> {
+    using type = uint16_t;
+};
+template <>
+struct equivalent_integer<true, 4> {
+    using type = int32_t;
+};
+template <>
+struct equivalent_integer<false, 4> {
+    using type = uint32_t;
+};
+template <>
+struct equivalent_integer<true, 8> {
+    using type = int64_t;
+};
+template <>
+struct equivalent_integer<false, 8> {
+    using type = uint64_t;
+};
+
+template <typename IntLike>
+using equivalent_integer_t =
+    typename equivalent_integer<std::is_signed<IntLike>::value, sizeof(IntLike)>::type;
+
 PYBIND11_NAMESPACE_END(detail)
 
 /// Binds C++ enumerations and enumeration classes to Python
-template <typename Type> class enum_ : public class_<Type> {
+template <typename Type>
+class enum_ : public class_<Type> {
 public:
     using Base = class_<Type>;
-    using Base::def;
     using Base::attr;
+    using Base::def;
     using Base::def_property_readonly;
     using Base::def_property_readonly_static;
-    using Scalar = typename std::underlying_type<Type>::type;
+    using Underlying = typename std::underlying_type<Type>::type;
+    // Scalar is the integer representation of underlying type
+    using Scalar = detail::conditional_t<detail::any_of<detail::is_std_char_type<Underlying>,
+                                                        std::is_same<Underlying, bool>>::value,
+                                         detail::equivalent_integer_t<Underlying>,
+                                         Underlying>;
 
     template <typename... Extra>
-    enum_(const handle &scope, const char *name, const Extra&... extra)
-      : class_<Type>(scope, name, extra...), m_base(*this, scope) {
+    enum_(const handle &scope, const char *name, const Extra &...extra)
+        : class_<Type>(scope, name, extra...), m_base(*this, scope) {
         constexpr bool is_arithmetic = detail::any_of<std::is_same<arithmetic, Extra>...>::value;
-        constexpr bool is_convertible = std::is_convertible<Type, Scalar>::value;
+        constexpr bool is_convertible = std::is_convertible<Type, Underlying>::value;
         m_base.init(is_arithmetic, is_convertible);
 
         def(init([](Scalar i) { return static_cast<Type>(i); }), arg("value"));
+        def_property_readonly("value", [](Type value) { return (Scalar) value; });
         def("__int__", [](Type value) { return (Scalar) value; });
-        #if PY_MAJOR_VERSION < 3
-            def("__long__", [](Type value) { return (Scalar) value; });
-        #endif
-        #if PY_MAJOR_VERSION > 3 || (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8)
-            def("__index__", [](Type value) { return (Scalar) value; });
-        #endif
-
+        def("__index__", [](Type value) { return (Scalar) value; });
         attr("__setstate__") = cpp_function(
             [](detail::value_and_holder &v_h, Scalar arg) {
-                detail::initimpl::setstate<Base>(v_h, static_cast<Type>(arg),
-                        Py_TYPE(v_h.inst) != v_h.type->type); },
+                detail::initimpl::setstate<Base>(
+                    v_h, static_cast<Type>(arg), Py_TYPE(v_h.inst) != v_h.type->type);
+            },
             detail::is_new_style_constructor(),
-            pybind11::name("__setstate__"), is_method(*this), arg("state"));
+            pybind11::name("__setstate__"),
+            is_method(*this),
+            arg("state"));
     }
 
     /// Export enumeration entries into the parent scope
-    enum_& export_values() {
+    enum_ &export_values() {
         m_base.export_values();
         return *this;
     }
 
     /// Add an enumeration entry
-    enum_& value(char const* name, Type value, const char *doc = nullptr) {
+    enum_ &value(char const *name, Type value, const char *doc = nullptr) {
         m_base.value(name, pybind11::cast(value, return_value_policy::copy), doc);
         return *this;
     }
@@ -1765,26 +2185,28 @@ template <typename Type> class enum_ : public class_<Type> {
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 
-
-inline void keep_alive_impl(handle nurse, handle patient) {
-    if (!nurse || !patient)
+PYBIND11_NOINLINE void keep_alive_impl(handle nurse, handle patient) {
+    if (!nurse || !patient) {
         pybind11_fail("Could not activate keep_alive!");
+    }
 
-    if (patient.is_none() || nurse.is_none())
+    if (patient.is_none() || nurse.is_none()) {
         return; /* Nothing to keep alive or nothing to be kept alive by */
+    }
 
     auto tinfo = all_type_info(Py_TYPE(nurse.ptr()));
     if (!tinfo.empty()) {
         /* It's a pybind-registered type, so we can store the patient in the
          * internal list. */
         add_patient(nurse.ptr(), patient.ptr());
-    }
-    else {
+    } else {
         /* Fall back to clever approach based on weak references taken from
          * Boost.Python. This is not used for pybind-registered types because
          * the objects can be destroyed out-of-order in a GC pass. */
-        cpp_function disable_lifesupport(
-            [patient](handle weakref) { patient.dec_ref(); weakref.dec_ref(); });
+        cpp_function disable_lifesupport([patient](handle weakref) {
+            patient.dec_ref();
+            weakref.dec_ref();
+        });
 
         weakref wr(nurse, disable_lifesupport);
 
@@ -1793,152 +2215,286 @@ inline void keep_alive_impl(handle nurse, handle patient) {
     }
 }
 
-PYBIND11_NOINLINE inline void keep_alive_impl(size_t Nurse, size_t Patient, function_call &call, handle ret) {
+PYBIND11_NOINLINE void
+keep_alive_impl(size_t Nurse, size_t Patient, function_call &call, handle ret) {
     auto get_arg = [&](size_t n) {
-        if (n == 0)
+        if (n == 0) {
             return ret;
-        else if (n == 1 && call.init_self)
+        }
+        if (n == 1 && call.init_self) {
             return call.init_self;
-        else if (n <= call.args.size())
+        }
+        if (n <= call.args.size()) {
             return call.args[n - 1];
+        }
         return handle();
     };
 
     keep_alive_impl(get_arg(Nurse), get_arg(Patient));
 }
 
-inline std::pair<decltype(internals::registered_types_py)::iterator, bool> all_type_info_get_cache(PyTypeObject *type) {
-    auto res = get_internals().registered_types_py
+inline std::pair<decltype(internals::registered_types_py)::iterator, bool>
+all_type_info_get_cache(PyTypeObject *type) {
+    auto res = get_internals()
+                   .registered_types_py
 #ifdef __cpp_lib_unordered_map_try_emplace
-        .try_emplace(type);
+                   .try_emplace(type);
 #else
-        .emplace(type, std::vector<detail::type_info *>());
+                   .emplace(type, std::vector<detail::type_info *>());
 #endif
     if (res.second) {
         // New cache entry created; set up a weak reference to automatically remove it if the type
         // gets destroyed:
         weakref((PyObject *) type, cpp_function([type](handle wr) {
-            get_internals().registered_types_py.erase(type);
-            wr.dec_ref();
-        })).release();
+                    get_internals().registered_types_py.erase(type);
+
+                    // TODO consolidate the erasure code in pybind11_meta_dealloc() in class.h
+                    auto &cache = get_internals().inactive_override_cache;
+                    for (auto it = cache.begin(), last = cache.end(); it != last;) {
+                        if (it->first == reinterpret_cast<PyObject *>(type)) {
+                            it = cache.erase(it);
+                        } else {
+                            ++it;
+                        }
+                    }
+
+                    wr.dec_ref();
+                }))
+            .release();
     }
 
     return res;
 }
 
-template <typename Iterator, typename Sentinel, bool KeyIterator, return_value_policy Policy>
+/* There are a large number of apparently unused template arguments because
+ * each combination requires a separate py::class_ registration.
+ */
+template <typename Access,
+          return_value_policy Policy,
+          typename Iterator,
+          typename Sentinel,
+          typename ValueType,
+          typename... Extra>
 struct iterator_state {
     Iterator it;
     Sentinel end;
     bool first_or_done;
 };
 
-PYBIND11_NAMESPACE_END(detail)
+// Note: these helpers take the iterator by non-const reference because some
+// iterators in the wild can't be dereferenced when const. The & after Iterator
+// is required for MSVC < 16.9. SFINAE cannot be reused for result_type due to
+// bugs in ICC, NVCC, and PGI compilers. See PR #3293.
+template <typename Iterator, typename SFINAE = decltype(*std::declval<Iterator &>())>
+struct iterator_access {
+    using result_type = decltype(*std::declval<Iterator &>());
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
+    result_type operator()(Iterator &it) const { return *it; }
+};
 
-/// Makes a python iterator from a first and past-the-end C++ InputIterator.
-template <return_value_policy Policy = return_value_policy::reference_internal,
+template <typename Iterator, typename SFINAE = decltype((*std::declval<Iterator &>()).first)>
+class iterator_key_access {
+private:
+    using pair_type = decltype(*std::declval<Iterator &>());
+
+public:
+    /* If either the pair itself or the element of the pair is a reference, we
+     * want to return a reference, otherwise a value. When the decltype
+     * expression is parenthesized it is based on the value category of the
+     * expression; otherwise it is the declared type of the pair member.
+     * The use of declval<pair_type> in the second branch rather than directly
+     * using *std::declval<Iterator &>() is a workaround for nvcc
+     * (it's not used in the first branch because going via decltype and back
+     * through declval does not perfectly preserve references).
+     */
+    using result_type
+        = conditional_t<std::is_reference<decltype(*std::declval<Iterator &>())>::value,
+                        decltype(((*std::declval<Iterator &>()).first)),
+                        decltype(std::declval<pair_type>().first)>;
+    result_type operator()(Iterator &it) const { return (*it).first; }
+};
+
+template <typename Iterator, typename SFINAE = decltype((*std::declval<Iterator &>()).second)>
+class iterator_value_access {
+private:
+    using pair_type = decltype(*std::declval<Iterator &>());
+
+public:
+    using result_type
+        = conditional_t<std::is_reference<decltype(*std::declval<Iterator &>())>::value,
+                        decltype(((*std::declval<Iterator &>()).second)),
+                        decltype(std::declval<pair_type>().second)>;
+    result_type operator()(Iterator &it) const { return (*it).second; }
+};
+
+template <typename Access,
+          return_value_policy Policy,
           typename Iterator,
           typename Sentinel,
-          typename ValueType = decltype(*std::declval<Iterator>()),
+          typename ValueType,
           typename... Extra>
-iterator make_iterator(Iterator first, Sentinel last, Extra &&... extra) {
-    using state = detail::iterator_state<Iterator, Sentinel, false, Policy>;
+iterator make_iterator_impl(Iterator &&first, Sentinel &&last, Extra &&...extra) {
+    using state = detail::iterator_state<Access, Policy, Iterator, Sentinel, ValueType, Extra...>;
+    // TODO: state captures only the types of Extra, not the values
 
     if (!detail::get_type_info(typeid(state), false)) {
         class_<state>(handle(), "iterator", pybind11::module_local())
-            .def("__iter__", [](state &s) -> state& { return s; })
-            .def("__next__", [](state &s) -> ValueType {
-                if (!s.first_or_done)
-                    ++s.it;
-                else
-                    s.first_or_done = false;
-                if (s.it == s.end) {
-                    s.first_or_done = true;
-                    throw stop_iteration();
-                }
-                return *s.it;
-            }, std::forward<Extra>(extra)..., Policy);
+            .def("__iter__", [](state &s) -> state & { return s; })
+            .def(
+                "__next__",
+                [](state &s) -> ValueType {
+                    if (!s.first_or_done) {
+                        ++s.it;
+                    } else {
+                        s.first_or_done = false;
+                    }
+                    if (s.it == s.end) {
+                        s.first_or_done = true;
+                        throw stop_iteration();
+                    }
+                    return Access()(s.it);
+                    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
+                },
+                std::forward<Extra>(extra)...,
+                Policy);
     }
 
-    return cast(state{first, last, true});
+    return cast(state{std::forward<Iterator>(first), std::forward<Sentinel>(last), true});
 }
 
-/// Makes an python iterator over the keys (`.first`) of a iterator over pairs from a
-/// first and past-the-end InputIterator.
+PYBIND11_NAMESPACE_END(detail)
+
+/// Makes a python iterator from a first and past-the-end C++ InputIterator.
 template <return_value_policy Policy = return_value_policy::reference_internal,
           typename Iterator,
           typename Sentinel,
-          typename KeyType = decltype((*std::declval<Iterator>()).first),
+          typename ValueType = typename detail::iterator_access<Iterator>::result_type,
           typename... Extra>
-iterator make_key_iterator(Iterator first, Sentinel last, Extra &&... extra) {
-    using state = detail::iterator_state<Iterator, Sentinel, true, Policy>;
+iterator make_iterator(Iterator &&first, Sentinel &&last, Extra &&...extra) {
+    return detail::make_iterator_impl<detail::iterator_access<Iterator>,
+                                      Policy,
+                                      Iterator,
+                                      Sentinel,
+                                      ValueType,
+                                      Extra...>(std::forward<Iterator>(first),
+                                                std::forward<Sentinel>(last),
+                                                std::forward<Extra>(extra)...);
+}
 
-    if (!detail::get_type_info(typeid(state), false)) {
-        class_<state>(handle(), "iterator", pybind11::module_local())
-            .def("__iter__", [](state &s) -> state& { return s; })
-            .def("__next__", [](state &s) -> KeyType {
-                if (!s.first_or_done)
-                    ++s.it;
-                else
-                    s.first_or_done = false;
-                if (s.it == s.end) {
-                    s.first_or_done = true;
-                    throw stop_iteration();
-                }
-                return (*s.it).first;
-            }, std::forward<Extra>(extra)..., Policy);
-    }
+/// Makes a python iterator over the keys (`.first`) of a iterator over pairs from a
+/// first and past-the-end InputIterator.
+template <return_value_policy Policy = return_value_policy::reference_internal,
+          typename Iterator,
+          typename Sentinel,
+          typename KeyType = typename detail::iterator_key_access<Iterator>::result_type,
+          typename... Extra>
+iterator make_key_iterator(Iterator &&first, Sentinel &&last, Extra &&...extra) {
+    return detail::make_iterator_impl<detail::iterator_key_access<Iterator>,
+                                      Policy,
+                                      Iterator,
+                                      Sentinel,
+                                      KeyType,
+                                      Extra...>(std::forward<Iterator>(first),
+                                                std::forward<Sentinel>(last),
+                                                std::forward<Extra>(extra)...);
+}
 
-    return cast(state{first, last, true});
+/// Makes a python iterator over the values (`.second`) of a iterator over pairs from a
+/// first and past-the-end InputIterator.
+template <return_value_policy Policy = return_value_policy::reference_internal,
+          typename Iterator,
+          typename Sentinel,
+          typename ValueType = typename detail::iterator_value_access<Iterator>::result_type,
+          typename... Extra>
+iterator make_value_iterator(Iterator &&first, Sentinel &&last, Extra &&...extra) {
+    return detail::make_iterator_impl<detail::iterator_value_access<Iterator>,
+                                      Policy,
+                                      Iterator,
+                                      Sentinel,
+                                      ValueType,
+                                      Extra...>(std::forward<Iterator>(first),
+                                                std::forward<Sentinel>(last),
+                                                std::forward<Extra>(extra)...);
 }
 
 /// Makes an iterator over values of an stl container or other container supporting
 /// `std::begin()`/`std::end()`
 template <return_value_policy Policy = return_value_policy::reference_internal,
-          typename Type, typename... Extra> iterator make_iterator(Type &value, Extra&&... extra) {
-    return make_iterator<Policy>(std::begin(value), std::end(value), extra...);
+          typename Type,
+          typename... Extra>
+iterator make_iterator(Type &value, Extra &&...extra) {
+    return make_iterator<Policy>(
+        std::begin(value), std::end(value), std::forward<Extra>(extra)...);
 }
 
 /// Makes an iterator over the keys (`.first`) of a stl map-like container supporting
 /// `std::begin()`/`std::end()`
 template <return_value_policy Policy = return_value_policy::reference_internal,
-          typename Type, typename... Extra> iterator make_key_iterator(Type &value, Extra&&... extra) {
-    return make_key_iterator<Policy>(std::begin(value), std::end(value), extra...);
+          typename Type,
+          typename... Extra>
+iterator make_key_iterator(Type &value, Extra &&...extra) {
+    return make_key_iterator<Policy>(
+        std::begin(value), std::end(value), std::forward<Extra>(extra)...);
 }
 
-template <typename InputType, typename OutputType> void implicitly_convertible() {
+/// Makes an iterator over the values (`.second`) of a stl map-like container supporting
+/// `std::begin()`/`std::end()`
+template <return_value_policy Policy = return_value_policy::reference_internal,
+          typename Type,
+          typename... Extra>
+iterator make_value_iterator(Type &value, Extra &&...extra) {
+    return make_value_iterator<Policy>(
+        std::begin(value), std::end(value), std::forward<Extra>(extra)...);
+}
+
+template <typename InputType, typename OutputType>
+void implicitly_convertible() {
     struct set_flag {
         bool &flag;
-        set_flag(bool &flag) : flag(flag) { flag = true; }
+        explicit set_flag(bool &flag_) : flag(flag_) { flag_ = true; }
         ~set_flag() { flag = false; }
     };
     auto implicit_caster = [](PyObject *obj, PyTypeObject *type) -> PyObject * {
         static bool currently_used = false;
-        if (currently_used) // implicit conversions are non-reentrant
+        if (currently_used) { // implicit conversions are non-reentrant
             return nullptr;
+        }
         set_flag flag_helper(currently_used);
-        if (!detail::make_caster<InputType>().load(obj, false))
+        if (!detail::make_caster<InputType>().load(obj, false)) {
             return nullptr;
+        }
         tuple args(1);
         args[0] = obj;
         PyObject *result = PyObject_Call((PyObject *) type, args.ptr(), nullptr);
-        if (result == nullptr)
+        if (result == nullptr) {
             PyErr_Clear();
+        }
         return result;
     };
 
-    if (auto tinfo = detail::get_type_info(typeid(OutputType)))
-        tinfo->implicit_conversions.push_back(implicit_caster);
-    else
+    if (auto *tinfo = detail::get_type_info(typeid(OutputType))) {
+        tinfo->implicit_conversions.emplace_back(std::move(implicit_caster));
+    } else {
         pybind11_fail("implicitly_convertible: Unable to find type " + type_id<OutputType>());
+    }
 }
 
-template <typename ExceptionTranslator>
-void register_exception_translator(ExceptionTranslator&& translator) {
+inline void register_exception_translator(ExceptionTranslator &&translator) {
     detail::get_internals().registered_exception_translators.push_front(
         std::forward<ExceptionTranslator>(translator));
 }
 
+/**
+ * Add a new module-local exception translator. Locally registered functions
+ * will be tried before any globally registered exception translators, which
+ * will only be invoked if the module-local handlers do not deal with
+ * the exception.
+ */
+inline void register_local_exception_translator(ExceptionTranslator &&translator) {
+    detail::get_local_internals().registered_exception_translators.push_front(
+        std::forward<ExceptionTranslator>(translator));
+}
+
 /**
  * Wrapper to generate a new Python exception type.
  *
@@ -1951,19 +2507,19 @@ class exception : public object {
 public:
     exception() = default;
     exception(handle scope, const char *name, handle base = PyExc_Exception) {
-        std::string full_name = scope.attr("__name__").cast<std::string>() +
-                                std::string(".") + name;
-        m_ptr = PyErr_NewException(const_cast<char *>(full_name.c_str()), base.ptr(), NULL);
-        if (hasattr(scope, "__dict__") && scope.attr("__dict__").contains(name))
+        std::string full_name
+            = scope.attr("__name__").cast<std::string>() + std::string(".") + name;
+        m_ptr = PyErr_NewException(const_cast<char *>(full_name.c_str()), base.ptr(), nullptr);
+        if (hasattr(scope, "__dict__") && scope.attr("__dict__").contains(name)) {
             pybind11_fail("Error during initialization: multiple incompatible "
-                          "definitions with name \"" + std::string(name) + "\"");
+                          "definitions with name \""
+                          + std::string(name) + "\"");
+        }
         scope.attr(name) = *this;
     }
 
     // Sets the current python exception to this exception object with the given message
-    void operator()(const char *message) {
-        PyErr_SetString(m_ptr, message);
-    }
+    void operator()(const char *message) { PyErr_SetString(m_ptr, message); }
 };
 
 PYBIND11_NAMESPACE_BEGIN(detail)
@@ -1971,24 +2527,27 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 // register_exception approach below.  (It would be simpler to have the static local variable
 // directly in register_exception, but that makes clang <3.5 segfault - issue #1349).
 template <typename CppException>
-exception<CppException> &get_exception_object() { static exception<CppException> ex; return ex; }
-PYBIND11_NAMESPACE_END(detail)
+exception<CppException> &get_exception_object() {
+    static exception<CppException> ex;
+    return ex;
+}
 
-/**
- * Registers a Python exception in `m` of the given `name` and installs an exception translator to
- * translate the C++ exception to the created Python exception using the exceptions what() method.
- * This is intended for simple exception translations; for more complex translation, register the
- * exception object and translator directly.
- */
+// Helper function for register_exception and register_local_exception
 template <typename CppException>
-exception<CppException> &register_exception(handle scope,
-                                            const char *name,
-                                            handle base = PyExc_Exception) {
+exception<CppException> &
+register_exception_impl(handle scope, const char *name, handle base, bool isLocal) {
     auto &ex = detail::get_exception_object<CppException>();
-    if (!ex) ex = exception<CppException>(scope, name, base);
+    if (!ex) {
+        ex = exception<CppException>(scope, name, base);
+    }
+
+    auto register_func
+        = isLocal ? &register_local_exception_translator : &register_exception_translator;
 
-    register_exception_translator([](std::exception_ptr p) {
-        if (!p) return;
+    register_func([](std::exception_ptr p) {
+        if (!p) {
+            return;
+        }
         try {
             std::rethrow_exception(p);
         } catch (const CppException &e) {
@@ -1998,14 +2557,42 @@ exception<CppException> &register_exception(handle scope,
     return ex;
 }
 
+PYBIND11_NAMESPACE_END(detail)
+
+/**
+ * Registers a Python exception in `m` of the given `name` and installs a translator to
+ * translate the C++ exception to the created Python exception using the what() method.
+ * This is intended for simple exception translations; for more complex translation, register the
+ * exception object and translator directly.
+ */
+template <typename CppException>
+exception<CppException> &
+register_exception(handle scope, const char *name, handle base = PyExc_Exception) {
+    return detail::register_exception_impl<CppException>(scope, name, base, false /* isLocal */);
+}
+
+/**
+ * Registers a Python exception in `m` of the given `name` and installs a translator to
+ * translate the C++ exception to the created Python exception using the what() method.
+ * This translator will only be used for exceptions that are thrown in this module and will be
+ * tried before global exception translators, including those registered with register_exception.
+ * This is intended for simple exception translations; for more complex translation, register the
+ * exception object and translator directly.
+ */
+template <typename CppException>
+exception<CppException> &
+register_local_exception(handle scope, const char *name, handle base = PyExc_Exception) {
+    return detail::register_exception_impl<CppException>(scope, name, base, true /* isLocal */);
+}
+
 PYBIND11_NAMESPACE_BEGIN(detail)
-PYBIND11_NOINLINE inline void print(tuple args, dict kwargs) {
+PYBIND11_NOINLINE void print(const tuple &args, const dict &kwargs) {
     auto strings = tuple(args.size());
     for (size_t i = 0; i < args.size(); ++i) {
         strings[i] = str(args[i]);
     }
-    auto sep = kwargs.contains("sep") ? kwargs["sep"] : cast(" ");
-    auto line = sep.attr("join")(strings);
+    auto sep = kwargs.contains("sep") ? kwargs["sep"] : str(" ");
+    auto line = sep.attr("join")(std::move(strings));
 
     object file;
     if (kwargs.contains("file")) {
@@ -2023,11 +2610,12 @@ PYBIND11_NOINLINE inline void print(tuple args, dict kwargs) {
     }
 
     auto write = file.attr("write");
-    write(line);
-    write(kwargs.contains("end") ? kwargs["end"] : cast("\n"));
+    write(std::move(line));
+    write(kwargs.contains("end") ? kwargs["end"] : str("\n"));
 
-    if (kwargs.contains("flush") && kwargs["flush"].cast<bool>())
+    if (kwargs.contains("flush") && kwargs["flush"].cast<bool>()) {
         file.attr("flush")();
+    }
 }
 PYBIND11_NAMESPACE_END(detail)
 
@@ -2037,214 +2625,106 @@ void print(Args &&...args) {
     detail::print(c.args(), c.kwargs());
 }
 
-#if defined(WITH_THREAD) && !defined(PYPY_VERSION)
-
-/* The functions below essentially reproduce the PyGILState_* API using a RAII
- * pattern, but there are a few important differences:
- *
- * 1. When acquiring the GIL from an non-main thread during the finalization
- *    phase, the GILState API blindly terminates the calling thread, which
- *    is often not what is wanted. This API does not do this.
- *
- * 2. The gil_scoped_release function can optionally cut the relationship
- *    of a PyThreadState and its associated thread, which allows moving it to
- *    another thread (this is a fairly rare/advanced use case).
- *
- * 3. The reference count of an acquired thread state can be controlled. This
- *    can be handy to prevent cases where callbacks issued from an external
- *    thread would otherwise constantly construct and destroy thread state data
- *    structures.
- *
- * See the Python bindings of NanoGUI (http://github.com/wjakob/nanogui) for an
- * example which uses features 2 and 3 to migrate the Python thread of
- * execution to another thread (to run the event loop on the original thread,
- * in this case).
- */
-
-class gil_scoped_acquire {
-public:
-    PYBIND11_NOINLINE gil_scoped_acquire() {
-        auto const &internals = detail::get_internals();
-        tstate = (PyThreadState *) PYBIND11_TLS_GET_VALUE(internals.tstate);
-
-        if (!tstate) {
-            /* Check if the GIL was acquired using the PyGILState_* API instead (e.g. if
-               calling from a Python thread). Since we use a different key, this ensures
-               we don't create a new thread state and deadlock in PyEval_AcquireThread
-               below. Note we don't save this state with internals.tstate, since we don't
-               create it we would fail to clear it (its reference count should be > 0). */
-            tstate = PyGILState_GetThisThreadState();
-        }
-
-        if (!tstate) {
-            tstate = PyThreadState_New(internals.istate);
-            #if !defined(NDEBUG)
-                if (!tstate)
-                    pybind11_fail("scoped_acquire: could not create thread state!");
-            #endif
-            tstate->gilstate_counter = 0;
-            PYBIND11_TLS_REPLACE_VALUE(internals.tstate, tstate);
-        } else {
-            release = detail::get_thread_state_unchecked() != tstate;
-        }
-
-        if (release) {
-            /* Work around an annoying assertion in PyThreadState_Swap */
-            #if defined(Py_DEBUG)
-                PyInterpreterState *interp = tstate->interp;
-                tstate->interp = nullptr;
-            #endif
-            PyEval_AcquireThread(tstate);
-            #if defined(Py_DEBUG)
-                tstate->interp = interp;
-            #endif
-        }
-
-        inc_ref();
-    }
-
-    void inc_ref() {
-        ++tstate->gilstate_counter;
-    }
-
-    PYBIND11_NOINLINE void dec_ref() {
-        --tstate->gilstate_counter;
-        #if !defined(NDEBUG)
-            if (detail::get_thread_state_unchecked() != tstate)
-                pybind11_fail("scoped_acquire::dec_ref(): thread state must be current!");
-            if (tstate->gilstate_counter < 0)
-                pybind11_fail("scoped_acquire::dec_ref(): reference count underflow!");
-        #endif
-        if (tstate->gilstate_counter == 0) {
-            #if !defined(NDEBUG)
-                if (!release)
-                    pybind11_fail("scoped_acquire::dec_ref(): internal error!");
-            #endif
-            PyThreadState_Clear(tstate);
-            PyThreadState_DeleteCurrent();
-            PYBIND11_TLS_DELETE_VALUE(detail::get_internals().tstate);
-            release = false;
-        }
-    }
-
-    PYBIND11_NOINLINE ~gil_scoped_acquire() {
-        dec_ref();
-        if (release)
-           PyEval_SaveThread();
-    }
-private:
-    PyThreadState *tstate = nullptr;
-    bool release = true;
-};
-
-class gil_scoped_release {
-public:
-    explicit gil_scoped_release(bool disassoc = false) : disassoc(disassoc) {
-        // `get_internals()` must be called here unconditionally in order to initialize
-        // `internals.tstate` for subsequent `gil_scoped_acquire` calls. Otherwise, an
-        // initialization race could occur as multiple threads try `gil_scoped_acquire`.
-        const auto &internals = detail::get_internals();
-        tstate = PyEval_SaveThread();
-        if (disassoc) {
-            auto key = internals.tstate;
-            PYBIND11_TLS_DELETE_VALUE(key);
-        }
-    }
-    ~gil_scoped_release() {
-        if (!tstate)
-            return;
-        PyEval_RestoreThread(tstate);
-        if (disassoc) {
-            auto key = detail::get_internals().tstate;
-            PYBIND11_TLS_REPLACE_VALUE(key, tstate);
-        }
-    }
-private:
-    PyThreadState *tstate;
-    bool disassoc;
-};
-#elif defined(PYPY_VERSION)
-class gil_scoped_acquire {
-    PyGILState_STATE state;
-public:
-    gil_scoped_acquire() { state = PyGILState_Ensure(); }
-    ~gil_scoped_acquire() { PyGILState_Release(state); }
-};
-
-class gil_scoped_release {
-    PyThreadState *state;
-public:
-    gil_scoped_release() { state = PyEval_SaveThread(); }
-    ~gil_scoped_release() { PyEval_RestoreThread(state); }
-};
-#else
-class gil_scoped_acquire { };
-class gil_scoped_release { };
-#endif
+inline void
+error_already_set::m_fetched_error_deleter(detail::error_fetch_and_normalize *raw_ptr) {
+    gil_scoped_acquire gil;
+    error_scope scope;
+    delete raw_ptr;
+}
 
-error_already_set::~error_already_set() {
-    if (m_type) {
-        gil_scoped_acquire gil;
-        error_scope scope;
-        m_type.release().dec_ref();
-        m_value.release().dec_ref();
-        m_trace.release().dec_ref();
-    }
+inline const char *error_already_set::what() const noexcept {
+    gil_scoped_acquire gil;
+    error_scope scope;
+    return m_fetched_error->error_string().c_str();
 }
 
 PYBIND11_NAMESPACE_BEGIN(detail)
-inline function get_type_override(const void *this_ptr, const type_info *this_type, const char *name)  {
+
+inline function
+get_type_override(const void *this_ptr, const type_info *this_type, const char *name) {
     handle self = get_object_handle(this_ptr, this_type);
-    if (!self)
+    if (!self) {
         return function();
+    }
     handle type = type::handle_of(self);
     auto key = std::make_pair(type.ptr(), name);
 
     /* Cache functions that aren't overridden in Python to avoid
        many costly Python dictionary lookups below */
     auto &cache = get_internals().inactive_override_cache;
-    if (cache.find(key) != cache.end())
+    if (cache.find(key) != cache.end()) {
         return function();
+    }
 
     function override = getattr(self, name, function());
     if (override.is_cpp_function()) {
-        cache.insert(key);
+        cache.insert(std::move(key));
         return function();
     }
 
     /* Don't call dispatch code if invoked from overridden function.
        Unfortunately this doesn't work on PyPy. */
 #if !defined(PYPY_VERSION)
+#    if PY_VERSION_HEX >= 0x03090000
+    PyFrameObject *frame = PyThreadState_GetFrame(PyThreadState_Get());
+    if (frame != nullptr) {
+        PyCodeObject *f_code = PyFrame_GetCode(frame);
+        // f_code is guaranteed to not be NULL
+        if ((std::string) str(f_code->co_name) == name && f_code->co_argcount > 0) {
+            PyObject *locals = PyEval_GetLocals();
+            if (locals != nullptr) {
+                PyObject *co_varnames = PyObject_GetAttrString((PyObject *) f_code, "co_varnames");
+                PyObject *self_arg = PyTuple_GET_ITEM(co_varnames, 0);
+                Py_DECREF(co_varnames);
+                PyObject *self_caller = dict_getitem(locals, self_arg);
+                if (self_caller == self.ptr()) {
+                    Py_DECREF(f_code);
+                    Py_DECREF(frame);
+                    return function();
+                }
+            }
+        }
+        Py_DECREF(f_code);
+        Py_DECREF(frame);
+    }
+#    else
     PyFrameObject *frame = PyThreadState_Get()->frame;
-    if (frame && (std::string) str(frame->f_code->co_name) == name &&
-        frame->f_code->co_argcount > 0) {
+    if (frame != nullptr && (std::string) str(frame->f_code->co_name) == name
+        && frame->f_code->co_argcount > 0) {
         PyFrame_FastToLocals(frame);
-        PyObject *self_caller = PyDict_GetItem(
-            frame->f_locals, PyTuple_GET_ITEM(frame->f_code->co_varnames, 0));
-        if (self_caller == self.ptr())
+        PyObject *self_caller
+            = dict_getitem(frame->f_locals, PyTuple_GET_ITEM(frame->f_code->co_varnames, 0));
+        if (self_caller == self.ptr()) {
             return function();
+        }
     }
+#    endif
+
 #else
     /* PyPy currently doesn't provide a detailed cpyext emulation of
        frame objects, so we have to emulate this using Python. This
        is going to be slow..*/
-    dict d; d["self"] = self; d["name"] = pybind11::str(name);
-    PyObject *result = PyRun_String(
-        "import inspect\n"
-        "frame = inspect.currentframe()\n"
-        "if frame is not None:\n"
-        "    frame = frame.f_back\n"
-        "    if frame is not None and str(frame.f_code.co_name) == name and "
-        "frame.f_code.co_argcount > 0:\n"
-        "        self_caller = frame.f_locals[frame.f_code.co_varnames[0]]\n"
-        "        if self_caller == self:\n"
-        "            self = None\n",
-        Py_file_input, d.ptr(), d.ptr());
+    dict d;
+    d["self"] = self;
+    d["name"] = pybind11::str(name);
+    PyObject *result
+        = PyRun_String("import inspect\n"
+                       "frame = inspect.currentframe()\n"
+                       "if frame is not None:\n"
+                       "    frame = frame.f_back\n"
+                       "    if frame is not None and str(frame.f_code.co_name) == name and "
+                       "frame.f_code.co_argcount > 0:\n"
+                       "        self_caller = frame.f_locals[frame.f_code.co_varnames[0]]\n"
+                       "        if self_caller == self:\n"
+                       "            self = None\n",
+                       Py_file_input,
+                       d.ptr(),
+                       d.ptr());
     if (result == nullptr)
         throw error_already_set();
+    Py_DECREF(result);
     if (d["self"].is_none())
         return function();
-    Py_DECREF(result);
 #endif
 
     return override;
@@ -2252,36 +2732,40 @@ inline function get_type_override(const void *this_ptr, const type_info *this_ty
 PYBIND11_NAMESPACE_END(detail)
 
 /** \rst
-  Try to retrieve a python method by the provided name from the instance pointed to by the this_ptr.
+  Try to retrieve a python method by the provided name from the instance pointed to by the
+  this_ptr.
 
-  :this_ptr: The pointer to the object the overriden method should be retrieved for. This should be
-             the first non-trampoline class encountered in the inheritance chain.
+  :this_ptr: The pointer to the object the overridden method should be retrieved for. This should
+             be the first non-trampoline class encountered in the inheritance chain.
   :name: The name of the overridden Python method to retrieve.
   :return: The Python method by this name from the object or an empty function wrapper.
  \endrst */
-template <class T> function get_override(const T *this_ptr, const char *name) {
-    auto tinfo = detail::get_type_info(typeid(T));
+template <class T>
+function get_override(const T *this_ptr, const char *name) {
+    auto *tinfo = detail::get_type_info(typeid(T));
     return tinfo ? detail::get_type_override(this_ptr, tinfo, name) : function();
 }
 
-#define PYBIND11_OVERRIDE_IMPL(ret_type, cname, name, ...) \
-    do { \
-        pybind11::gil_scoped_acquire gil; \
-        pybind11::function override = pybind11::get_override(static_cast<const cname *>(this), name); \
-        if (override) { \
-            auto o = override(__VA_ARGS__); \
-            if (pybind11::detail::cast_is_temporary_value_reference<ret_type>::value) { \
-                static pybind11::detail::override_caster_t<ret_type> caster; \
-                return pybind11::detail::cast_ref<ret_type>(std::move(o), caster); \
-            } \
-            else return pybind11::detail::cast_safe<ret_type>(std::move(o)); \
-        } \
+#define PYBIND11_OVERRIDE_IMPL(ret_type, cname, name, ...)                                        \
+    do {                                                                                          \
+        pybind11::gil_scoped_acquire gil;                                                         \
+        pybind11::function override                                                               \
+            = pybind11::get_override(static_cast<const cname *>(this), name);                     \
+        if (override) {                                                                           \
+            auto o = override(__VA_ARGS__);                                                       \
+            if (pybind11::detail::cast_is_temporary_value_reference<ret_type>::value) {           \
+                static pybind11::detail::override_caster_t<ret_type> caster;                      \
+                return pybind11::detail::cast_ref<ret_type>(std::move(o), caster);                \
+            }                                                                                     \
+            return pybind11::detail::cast_safe<ret_type>(std::move(o));                           \
+        }                                                                                         \
     } while (false)
 
 /** \rst
-    Macro to populate the virtual method in the trampoline class. This macro tries to look up a method named 'fn'
-    from the Python side, deals with the :ref:`gil` and necessary argument conversions to call this method and return
-    the appropriate type. See :ref:`overriding_virtuals` for more information. This macro should be used when the method
+    Macro to populate the virtual method in the trampoline class. This macro tries to look up a
+    method named 'fn' from the Python side, deals with the :ref:`gil` and necessary argument
+    conversions to call this method and return the appropriate type.
+    See :ref:`overriding_virtuals` for more information. This macro should be used when the method
     name in C is not the same as the method name in Python. For example with `__str__`.
 
     .. code-block:: cpp
@@ -2295,26 +2779,28 @@ template <class T> function get_override(const T *this_ptr, const char *name) {
         );
       }
 \endrst */
-#define PYBIND11_OVERRIDE_NAME(ret_type, cname, name, fn, ...) \
-    do { \
+#define PYBIND11_OVERRIDE_NAME(ret_type, cname, name, fn, ...)                                    \
+    do {                                                                                          \
         PYBIND11_OVERRIDE_IMPL(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, __VA_ARGS__); \
-        return cname::fn(__VA_ARGS__); \
+        return cname::fn(__VA_ARGS__);                                                            \
     } while (false)
 
 /** \rst
-    Macro for pure virtual functions, this function is identical to :c:macro:`PYBIND11_OVERRIDE_NAME`, except that it
-    throws if no override can be found.
+    Macro for pure virtual functions, this function is identical to
+    :c:macro:`PYBIND11_OVERRIDE_NAME`, except that it throws if no override can be found.
 \endrst */
-#define PYBIND11_OVERRIDE_PURE_NAME(ret_type, cname, name, fn, ...) \
-    do { \
+#define PYBIND11_OVERRIDE_PURE_NAME(ret_type, cname, name, fn, ...)                               \
+    do {                                                                                          \
         PYBIND11_OVERRIDE_IMPL(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, __VA_ARGS__); \
-        pybind11::pybind11_fail("Tried to call pure virtual function \"" PYBIND11_STRINGIFY(cname) "::" name "\""); \
+        pybind11::pybind11_fail(                                                                  \
+            "Tried to call pure virtual function \"" PYBIND11_STRINGIFY(cname) "::" name "\"");   \
     } while (false)
 
 /** \rst
-    Macro to populate the virtual method in the trampoline class. This macro tries to look up the method
-    from the Python side, deals with the :ref:`gil` and necessary argument conversions to call this method and return
-    the appropriate type. This macro should be used if the method name in C and in Python are identical.
+    Macro to populate the virtual method in the trampoline class. This macro tries to look up the
+    method from the Python side, deals with the :ref:`gil` and necessary argument conversions to
+    call this method and return the appropriate type. This macro should be used if the method name
+    in C and in Python are identical.
     See :ref:`overriding_virtuals` for more information.
 
     .. code-block:: cpp
@@ -2335,21 +2821,22 @@ template <class T> function get_override(const T *this_ptr, const char *name) {
           }
       };
 \endrst */
-#define PYBIND11_OVERRIDE(ret_type, cname, fn, ...) \
+#define PYBIND11_OVERRIDE(ret_type, cname, fn, ...)                                               \
     PYBIND11_OVERRIDE_NAME(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), #fn, fn, __VA_ARGS__)
 
 /** \rst
-    Macro for pure virtual functions, this function is identical to :c:macro:`PYBIND11_OVERRIDE`, except that it throws
-    if no override can be found.
+    Macro for pure virtual functions, this function is identical to :c:macro:`PYBIND11_OVERRIDE`,
+    except that it throws if no override can be found.
 \endrst */
-#define PYBIND11_OVERRIDE_PURE(ret_type, cname, fn, ...) \
-    PYBIND11_OVERRIDE_PURE_NAME(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), #fn, fn, __VA_ARGS__)
-
+#define PYBIND11_OVERRIDE_PURE(ret_type, cname, fn, ...)                                          \
+    PYBIND11_OVERRIDE_PURE_NAME(                                                                  \
+        PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), #fn, fn, __VA_ARGS__)
 
 // Deprecated versions
 
 PYBIND11_DEPRECATED("get_type_overload has been deprecated")
-inline function get_type_overload(const void *this_ptr, const detail::type_info *this_type, const char *name) {
+inline function
+get_type_overload(const void *this_ptr, const detail::type_info *this_type, const char *name) {
     return detail::get_type_override(this_ptr, this_type, name);
 }
 
@@ -2358,21 +2845,20 @@ inline function get_overload(const T *this_ptr, const char *name) {
     return get_override(this_ptr, name);
 }
 
-#define PYBIND11_OVERLOAD_INT(ret_type, cname, name, ...) \
+#define PYBIND11_OVERLOAD_INT(ret_type, cname, name, ...)                                         \
     PYBIND11_OVERRIDE_IMPL(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, __VA_ARGS__)
-#define PYBIND11_OVERLOAD_NAME(ret_type, cname, name, fn, ...) \
+#define PYBIND11_OVERLOAD_NAME(ret_type, cname, name, fn, ...)                                    \
     PYBIND11_OVERRIDE_NAME(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, fn, __VA_ARGS__)
-#define PYBIND11_OVERLOAD_PURE_NAME(ret_type, cname, name, fn, ...) \
-    PYBIND11_OVERRIDE_PURE_NAME(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, fn, __VA_ARGS__);
-#define PYBIND11_OVERLOAD(ret_type, cname, fn, ...) \
+#define PYBIND11_OVERLOAD_PURE_NAME(ret_type, cname, name, fn, ...)                               \
+    PYBIND11_OVERRIDE_PURE_NAME(                                                                  \
+        PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), name, fn, __VA_ARGS__);
+#define PYBIND11_OVERLOAD(ret_type, cname, fn, ...)                                               \
     PYBIND11_OVERRIDE(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), fn, __VA_ARGS__)
-#define PYBIND11_OVERLOAD_PURE(ret_type, cname, fn, ...) \
+#define PYBIND11_OVERLOAD_PURE(ret_type, cname, fn, ...)                                          \
     PYBIND11_OVERRIDE_PURE(PYBIND11_TYPE(ret_type), PYBIND11_TYPE(cname), fn, __VA_ARGS__);
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
 
-#if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
-#  pragma warning(pop)
-#elif defined(__GNUG__) && !defined(__clang__)
-#  pragma GCC diagnostic pop
+#if defined(__GNUC__) && __GNUC__ == 7
+#    pragma GCC diagnostic pop // -Wnoexcept-type
 #endif
diff --git a/3rdparty/pybind11/include/pybind11/pytypes.h b/3rdparty/pybind11/include/pybind11/pytypes.h
index 1010ad713c..f4ba459f20 100644
--- a/3rdparty/pybind11/include/pybind11/pytypes.h
+++ b/3rdparty/pybind11/include/pybind11/pytypes.h
@@ -11,30 +11,51 @@
 
 #include "detail/common.h"
 #include "buffer_info.h"
-#include <utility>
+
+#include <assert.h>
+#include <cstddef>
+#include <exception>
+#include <frameobject.h>
+#include <iterator>
+#include <memory>
+#include <string>
 #include <type_traits>
+#include <typeinfo>
+#include <utility>
+
+#if defined(PYBIND11_HAS_OPTIONAL)
+#    include <optional>
+#endif
+
+#ifdef PYBIND11_HAS_STRING_VIEW
+#    include <string_view>
+#endif
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 
 /* A few forward declarations */
-class handle; class object;
-class str; class iterator;
+class handle;
+class object;
+class str;
+class iterator;
 class type;
-struct arg; struct arg_v;
+struct arg;
+struct arg_v;
 
 PYBIND11_NAMESPACE_BEGIN(detail)
 class args_proxy;
-inline bool isinstance_generic(handle obj, const std::type_info &tp);
+bool isinstance_generic(handle obj, const std::type_info &tp);
 
 // Accessor forward declarations
-template <typename Policy> class accessor;
+template <typename Policy>
+class accessor;
 namespace accessor_policies {
-    struct obj_attr;
-    struct str_attr;
-    struct generic_item;
-    struct sequence_item;
-    struct list_item;
-    struct tuple_item;
+struct obj_attr;
+struct str_attr;
+struct generic_item;
+struct sequence_item;
+struct list_item;
+struct tuple_item;
 } // namespace accessor_policies
 using obj_attr_accessor = accessor<accessor_policies::obj_attr>;
 using str_attr_accessor = accessor<accessor_policies::str_attr>;
@@ -44,8 +65,9 @@ using list_accessor = accessor<accessor_policies::list_item>;
 using tuple_accessor = accessor<accessor_policies::tuple_item>;
 
 /// Tag and check to identify a class which implements the Python object API
-class pyobject_tag { };
-template <typename T> using is_pyobject = std::is_base_of<pyobject_tag, remove_reference_t<T>>;
+class pyobject_tag {};
+template <typename T>
+using is_pyobject = std::is_base_of<pyobject_tag, remove_reference_t<T>>;
 
 /** \rst
     A mixin class which adds common functions to `handle`, `object` and various accessors.
@@ -71,7 +93,9 @@ class object_api : public pyobject_tag {
         or `object` subclass causes a call to ``__setitem__``.
     \endrst */
     item_accessor operator[](handle key) const;
-    /// See above (the only difference is that they key is provided as a string literal)
+    /// See above (the only difference is that the key's reference is stolen)
+    item_accessor operator[](object &&key) const;
+    /// See above (the only difference is that the key is provided as a string literal)
     item_accessor operator[](const char *key) const;
 
     /** \rst
@@ -81,7 +105,9 @@ class object_api : public pyobject_tag {
         or `object` subclass causes a call to ``setattr``.
     \endrst */
     obj_attr_accessor attr(handle key) const;
-    /// See above (the only difference is that they key is provided as a string literal)
+    /// See above (the only difference is that the key's reference is stolen)
+    obj_attr_accessor attr(object &&key) const;
+    /// See above (the only difference is that the key is provided as a string literal)
     str_attr_accessor attr(const char *key) const;
 
     /** \rst
@@ -93,7 +119,8 @@ class object_api : public pyobject_tag {
     args_proxy operator*() const;
 
     /// Check if the given item is contained within this object, i.e. ``item in obj``.
-    template <typename T> bool contains(T &&item) const;
+    template <typename T>
+    bool contains(T &&item) const;
 
     /** \rst
         Assuming the Python object is a function or implements the ``__call__``
@@ -105,44 +132,46 @@ class object_api : public pyobject_tag {
         function will throw a `cast_error` exception. When the Python function
         call fails, a `error_already_set` exception is thrown.
     \endrst */
-    template <return_value_policy policy = return_value_policy::automatic_reference, typename... Args>
+    template <return_value_policy policy = return_value_policy::automatic_reference,
+              typename... Args>
     object operator()(Args &&...args) const;
-    template <return_value_policy policy = return_value_policy::automatic_reference, typename... Args>
+    template <return_value_policy policy = return_value_policy::automatic_reference,
+              typename... Args>
     PYBIND11_DEPRECATED("call(...) was deprecated in favor of operator()(...)")
-        object call(Args&&... args) const;
+    object call(Args &&...args) const;
 
     /// Equivalent to ``obj is other`` in Python.
-    bool is(object_api const& other) const { return derived().ptr() == other.derived().ptr(); }
+    bool is(object_api const &other) const { return derived().ptr() == other.derived().ptr(); }
     /// Equivalent to ``obj is None`` in Python.
     bool is_none() const { return derived().ptr() == Py_None; }
     /// Equivalent to obj == other in Python
-    bool equal(object_api const &other) const      { return rich_compare(other, Py_EQ); }
-    bool not_equal(object_api const &other) const  { return rich_compare(other, Py_NE); }
-    bool operator<(object_api const &other) const  { return rich_compare(other, Py_LT); }
+    bool equal(object_api const &other) const { return rich_compare(other, Py_EQ); }
+    bool not_equal(object_api const &other) const { return rich_compare(other, Py_NE); }
+    bool operator<(object_api const &other) const { return rich_compare(other, Py_LT); }
     bool operator<=(object_api const &other) const { return rich_compare(other, Py_LE); }
-    bool operator>(object_api const &other) const  { return rich_compare(other, Py_GT); }
+    bool operator>(object_api const &other) const { return rich_compare(other, Py_GT); }
     bool operator>=(object_api const &other) const { return rich_compare(other, Py_GE); }
 
     object operator-() const;
     object operator~() const;
     object operator+(object_api const &other) const;
-    object operator+=(object_api const &other) const;
+    object operator+=(object_api const &other);
     object operator-(object_api const &other) const;
-    object operator-=(object_api const &other) const;
+    object operator-=(object_api const &other);
     object operator*(object_api const &other) const;
-    object operator*=(object_api const &other) const;
+    object operator*=(object_api const &other);
     object operator/(object_api const &other) const;
-    object operator/=(object_api const &other) const;
+    object operator/=(object_api const &other);
     object operator|(object_api const &other) const;
-    object operator|=(object_api const &other) const;
+    object operator|=(object_api const &other);
     object operator&(object_api const &other) const;
-    object operator&=(object_api const &other) const;
+    object operator&=(object_api const &other);
     object operator^(object_api const &other) const;
-    object operator^=(object_api const &other) const;
+    object operator^=(object_api const &other);
     object operator<<(object_api const &other) const;
-    object operator<<=(object_api const &other) const;
+    object operator<<=(object_api const &other);
     object operator>>(object_api const &other) const;
-    object operator>>=(object_api const &other) const;
+    object operator>>=(object_api const &other);
 
     PYBIND11_DEPRECATED("Use py::str(obj) instead")
     pybind11::str str() const;
@@ -153,15 +182,25 @@ class object_api : public pyobject_tag {
     /// Return the object's current reference count
     int ref_count() const { return static_cast<int>(Py_REFCNT(derived().ptr())); }
 
-    // TODO PYBIND11_DEPRECATED("Call py::type::handle_of(h) or py::type::of(h) instead of h.get_type()")
+    // TODO PYBIND11_DEPRECATED(
+    //     "Call py::type::handle_of(h) or py::type::of(h) instead of h.get_type()")
     handle get_type() const;
 
 private:
     bool rich_compare(object_api const &other, int value) const;
 };
 
+template <typename T>
+using is_pyobj_ptr_or_nullptr_t = detail::any_of<std::is_same<T, PyObject *>,
+                                                 std::is_same<T, PyObject *const>,
+                                                 std::is_same<T, std::nullptr_t>>;
+
 PYBIND11_NAMESPACE_END(detail)
 
+#if !defined(PYBIND11_HANDLE_REF_DEBUG) && !defined(NDEBUG)
+#    define PYBIND11_HANDLE_REF_DEBUG
+#endif
+
 /** \rst
     Holds a reference to a Python object (no reference counting)
 
@@ -177,8 +216,23 @@ class handle : public detail::object_api<handle> {
 public:
     /// The default constructor creates a handle with a ``nullptr``-valued pointer
     handle() = default;
-    /// Creates a ``handle`` from the given raw Python object pointer
-    handle(PyObject *ptr) : m_ptr(ptr) { } // Allow implicit conversion from PyObject*
+
+    /// Enable implicit conversion from ``PyObject *`` and ``nullptr``.
+    /// Not using ``handle(PyObject *ptr)`` to avoid implicit conversion from ``0``.
+    template <typename T,
+              detail::enable_if_t<detail::is_pyobj_ptr_or_nullptr_t<T>::value, int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    handle(T ptr) : m_ptr(ptr) {}
+
+    /// Enable implicit conversion through ``T::operator PyObject *()``.
+    template <
+        typename T,
+        detail::enable_if_t<detail::all_of<detail::none_of<std::is_base_of<handle, T>,
+                                                           detail::is_pyobj_ptr_or_nullptr_t<T>>,
+                                           std::is_convertible<T, PyObject *>>::value,
+                            int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    handle(T &obj) : m_ptr(obj) {}
 
     /// Return the underlying ``PyObject *`` pointer
     PyObject *ptr() const { return m_ptr; }
@@ -189,20 +243,30 @@ class handle : public detail::object_api<handle> {
         preferable to use the `object` class which derives from `handle` and calls
         this function automatically. Returns a reference to itself.
     \endrst */
-    const handle& inc_ref() const & { Py_XINCREF(m_ptr); return *this; }
+    const handle &inc_ref() const & {
+#ifdef PYBIND11_HANDLE_REF_DEBUG
+        inc_ref_counter(1);
+#endif
+        Py_XINCREF(m_ptr);
+        return *this;
+    }
 
     /** \rst
         Manually decrease the reference count of the Python object. Usually, it is
         preferable to use the `object` class which derives from `handle` and calls
         this function automatically. Returns a reference to itself.
     \endrst */
-    const handle& dec_ref() const & { Py_XDECREF(m_ptr); return *this; }
+    const handle &dec_ref() const & {
+        Py_XDECREF(m_ptr);
+        return *this;
+    }
 
     /** \rst
         Attempt to cast the Python object into the given C++ type. A `cast_error`
         will be throw upon failure.
     \endrst */
-    template <typename T> T cast() const;
+    template <typename T>
+    T cast() const;
     /// Return ``true`` when the `handle` wraps a valid Python object
     explicit operator bool() const { return m_ptr != nullptr; }
     /** \rst
@@ -215,8 +279,21 @@ class handle : public detail::object_api<handle> {
     bool operator!=(const handle &h) const { return m_ptr != h.m_ptr; }
     PYBIND11_DEPRECATED("Use handle::operator bool() instead")
     bool check() const { return m_ptr != nullptr; }
+
 protected:
     PyObject *m_ptr = nullptr;
+
+#ifdef PYBIND11_HANDLE_REF_DEBUG
+private:
+    static std::size_t inc_ref_counter(std::size_t add) {
+        thread_local std::size_t counter = 0;
+        counter += add;
+        return counter;
+    }
+
+public:
+    static std::size_t inc_ref_counter() { return inc_ref_counter(0); }
+#endif
 };
 
 /** \rst
@@ -233,11 +310,15 @@ class object : public handle {
 public:
     object() = default;
     PYBIND11_DEPRECATED("Use reinterpret_borrow<object>() or reinterpret_steal<object>()")
-    object(handle h, bool is_borrowed) : handle(h) { if (is_borrowed) inc_ref(); }
+    object(handle h, bool is_borrowed) : handle(h) {
+        if (is_borrowed) {
+            inc_ref();
+        }
+    }
     /// Copy constructor; always increases the reference count
     object(const object &o) : handle(o) { inc_ref(); }
     /// Move constructor; steals the object from ``other`` and preserves its reference count
-    object(object &&other) noexcept { m_ptr = other.m_ptr; other.m_ptr = nullptr; }
+    object(object &&other) noexcept : handle(other) { other.m_ptr = nullptr; }
     /// Destructor; automatically calls `handle::dec_ref()`
     ~object() { dec_ref(); }
 
@@ -247,19 +328,25 @@ class object : public handle {
         Python object.
     \endrst */
     handle release() {
-      PyObject *tmp = m_ptr;
-      m_ptr = nullptr;
-      return handle(tmp);
+        PyObject *tmp = m_ptr;
+        m_ptr = nullptr;
+        return handle(tmp);
     }
 
-    object& operator=(const object &other) {
-        other.inc_ref();
-        dec_ref();
-        m_ptr = other.m_ptr;
+    object &operator=(const object &other) {
+        // Skip inc_ref and dec_ref if both objects are the same
+        if (!this->is(other)) {
+            other.inc_ref();
+            // Use temporary variable to ensure `*this` remains valid while
+            // `Py_XDECREF` executes, in case `*this` is accessible from Python.
+            handle temp(m_ptr);
+            m_ptr = other.m_ptr;
+            temp.dec_ref();
+        }
         return *this;
     }
 
-    object& operator=(object &&other) noexcept {
+    object &operator=(object &&other) noexcept {
         if (this != &other) {
             handle temp(m_ptr);
             m_ptr = other.m_ptr;
@@ -269,23 +356,43 @@ class object : public handle {
         return *this;
     }
 
+#define PYBIND11_INPLACE_OP(iop)                                                                  \
+    object iop(object_api const &other) { return operator=(handle::iop(other)); }
+
+    PYBIND11_INPLACE_OP(operator+=)
+    PYBIND11_INPLACE_OP(operator-=)
+    PYBIND11_INPLACE_OP(operator*=)
+    PYBIND11_INPLACE_OP(operator/=)
+    PYBIND11_INPLACE_OP(operator|=)
+    PYBIND11_INPLACE_OP(operator&=)
+    PYBIND11_INPLACE_OP(operator^=)
+    PYBIND11_INPLACE_OP(operator<<=)
+    PYBIND11_INPLACE_OP(operator>>=)
+#undef PYBIND11_INPLACE_OP
+
     // Calling cast() on an object lvalue just copies (via handle::cast)
-    template <typename T> T cast() const &;
+    template <typename T>
+    T cast() const &;
     // Calling on an object rvalue does a move, if needed and/or possible
-    template <typename T> T cast() &&;
+    template <typename T>
+    T cast() &&;
 
 protected:
     // Tags for choosing constructors from raw PyObject *
-    struct borrowed_t { };
-    struct stolen_t { };
+    struct borrowed_t {};
+    struct stolen_t {};
 
-    template <typename T> friend T reinterpret_borrow(handle);
-    template <typename T> friend T reinterpret_steal(handle);
+    /// @cond BROKEN
+    template <typename T>
+    friend T reinterpret_borrow(handle);
+    template <typename T>
+    friend T reinterpret_steal(handle);
+    /// @endcond
 
 public:
     // Only accessible from derived classes and the reinterpret_* functions
     object(handle h, borrowed_t) : handle(h) { inc_ref(); }
-    object(handle h, stolen_t) : handle(h) { }
+    object(handle h, stolen_t) : handle(h) {}
 };
 
 /** \rst
@@ -301,7 +408,10 @@ class object : public handle {
         // or
         py::tuple t = reinterpret_borrow<py::tuple>(p); // <-- `p` must be already be a `tuple`
 \endrst */
-template <typename T> T reinterpret_borrow(handle h) { return {h, object::borrowed_t{}}; }
+template <typename T>
+T reinterpret_borrow(handle h) {
+    return {h, object::borrowed_t{}};
+}
 
 /** \rst
     Like `reinterpret_borrow`, but steals the reference.
@@ -311,44 +421,231 @@ template <typename T> T reinterpret_borrow(handle h) { return {h, object::borrow
         PyObject *p = PyObject_Str(obj);
         py::str s = reinterpret_steal<py::str>(p); // <-- `p` must be already be a `str`
 \endrst */
-template <typename T> T reinterpret_steal(handle h) { return {h, object::stolen_t{}}; }
+template <typename T>
+T reinterpret_steal(handle h) {
+    return {h, object::stolen_t{}};
+}
 
 PYBIND11_NAMESPACE_BEGIN(detail)
-inline std::string error_string();
-PYBIND11_NAMESPACE_END(detail)
 
-/// Fetch and hold an error which was already set in Python.  An instance of this is typically
-/// thrown to propagate python-side errors back through C++ which can either be caught manually or
-/// else falls back to the function dispatcher (which then raises the captured error back to
-/// python).
-class error_already_set : public std::runtime_error {
-public:
-    /// Constructs a new exception from the current Python error indicator, if any.  The current
-    /// Python error indicator will be cleared.
-    error_already_set() : std::runtime_error(detail::error_string()) {
+// Equivalent to obj.__class__.__name__ (or obj.__name__ if obj is a class).
+inline const char *obj_class_name(PyObject *obj) {
+    if (Py_TYPE(obj) == &PyType_Type) {
+        return reinterpret_cast<PyTypeObject *>(obj)->tp_name;
+    }
+    return Py_TYPE(obj)->tp_name;
+}
+
+std::string error_string();
+
+struct error_fetch_and_normalize {
+    // Immediate normalization is long-established behavior (starting with
+    // https://github.com/pybind/pybind11/commit/135ba8deafb8bf64a15b24d1513899eb600e2011
+    // from Sep 2016) and safest. Normalization could be deferred, but this could mask
+    // errors elsewhere, the performance gain is very minor in typical situations
+    // (usually the dominant bottleneck is EH unwinding), and the implementation here
+    // would be more complex.
+    explicit error_fetch_and_normalize(const char *called) {
         PyErr_Fetch(&m_type.ptr(), &m_value.ptr(), &m_trace.ptr());
+        if (!m_type) {
+            pybind11_fail("Internal error: " + std::string(called)
+                          + " called while "
+                            "Python error indicator not set.");
+        }
+        const char *exc_type_name_orig = detail::obj_class_name(m_type.ptr());
+        if (exc_type_name_orig == nullptr) {
+            pybind11_fail("Internal error: " + std::string(called)
+                          + " failed to obtain the name "
+                            "of the original active exception type.");
+        }
+        m_lazy_error_string = exc_type_name_orig;
+        // PyErr_NormalizeException() may change the exception type if there are cascading
+        // failures. This can potentially be extremely confusing.
+        PyErr_NormalizeException(&m_type.ptr(), &m_value.ptr(), &m_trace.ptr());
+        if (m_type.ptr() == nullptr) {
+            pybind11_fail("Internal error: " + std::string(called)
+                          + " failed to normalize the "
+                            "active exception.");
+        }
+        const char *exc_type_name_norm = detail::obj_class_name(m_type.ptr());
+        if (exc_type_name_orig == nullptr) {
+            pybind11_fail("Internal error: " + std::string(called)
+                          + " failed to obtain the name "
+                            "of the normalized active exception type.");
+        }
+#if defined(PYPY_VERSION_NUM) && PYPY_VERSION_NUM < 0x07030a00
+        // This behavior runs the risk of masking errors in the error handling, but avoids a
+        // conflict with PyPy, which relies on the normalization here to change OSError to
+        // FileNotFoundError (https://github.com/pybind/pybind11/issues/4075).
+        m_lazy_error_string = exc_type_name_norm;
+#else
+        if (exc_type_name_norm != m_lazy_error_string) {
+            std::string msg = std::string(called)
+                              + ": MISMATCH of original and normalized "
+                                "active exception types: ";
+            msg += "ORIGINAL ";
+            msg += m_lazy_error_string;
+            msg += " REPLACED BY ";
+            msg += exc_type_name_norm;
+            msg += ": " + format_value_and_trace();
+            pybind11_fail(msg);
+        }
+#endif
+    }
+
+    error_fetch_and_normalize(const error_fetch_and_normalize &) = delete;
+    error_fetch_and_normalize(error_fetch_and_normalize &&) = delete;
+
+    std::string format_value_and_trace() const {
+        std::string result;
+        std::string message_error_string;
+        if (m_value) {
+            auto value_str = reinterpret_steal<object>(PyObject_Str(m_value.ptr()));
+            if (!value_str) {
+                message_error_string = detail::error_string();
+                result = "<MESSAGE UNAVAILABLE DUE TO ANOTHER EXCEPTION>";
+            } else {
+                result = value_str.cast<std::string>();
+            }
+        } else {
+            result = "<MESSAGE UNAVAILABLE>";
+        }
+        if (result.empty()) {
+            result = "<EMPTY MESSAGE>";
+        }
+
+        bool have_trace = false;
+        if (m_trace) {
+#if !defined(PYPY_VERSION)
+            auto *tb = reinterpret_cast<PyTracebackObject *>(m_trace.ptr());
+
+            // Get the deepest trace possible.
+            while (tb->tb_next) {
+                tb = tb->tb_next;
+            }
+
+            PyFrameObject *frame = tb->tb_frame;
+            Py_XINCREF(frame);
+            result += "\n\nAt:\n";
+            while (frame) {
+#    if PY_VERSION_HEX >= 0x030900B1
+                PyCodeObject *f_code = PyFrame_GetCode(frame);
+#    else
+                PyCodeObject *f_code = frame->f_code;
+                Py_INCREF(f_code);
+#    endif
+                int lineno = PyFrame_GetLineNumber(frame);
+                result += "  ";
+                result += handle(f_code->co_filename).cast<std::string>();
+                result += '(';
+                result += std::to_string(lineno);
+                result += "): ";
+                result += handle(f_code->co_name).cast<std::string>();
+                result += '\n';
+                Py_DECREF(f_code);
+#    if PY_VERSION_HEX >= 0x030900B1
+                auto *b_frame = PyFrame_GetBack(frame);
+#    else
+                auto *b_frame = frame->f_back;
+                Py_XINCREF(b_frame);
+#    endif
+                Py_DECREF(frame);
+                frame = b_frame;
+            }
+
+            have_trace = true;
+#endif //! defined(PYPY_VERSION)
+        }
+
+        if (!message_error_string.empty()) {
+            if (!have_trace) {
+                result += '\n';
+            }
+            result += "\nMESSAGE UNAVAILABLE DUE TO EXCEPTION: " + message_error_string;
+        }
+
+        return result;
     }
 
-    error_already_set(const error_already_set &) = default;
-    error_already_set(error_already_set &&) = default;
+    std::string const &error_string() const {
+        if (!m_lazy_error_string_completed) {
+            m_lazy_error_string += ": " + format_value_and_trace();
+            m_lazy_error_string_completed = true;
+        }
+        return m_lazy_error_string;
+    }
 
-    inline ~error_already_set() override;
+    void restore() {
+        if (m_restore_called) {
+            pybind11_fail("Internal error: pybind11::detail::error_fetch_and_normalize::restore() "
+                          "called a second time. ORIGINAL ERROR: "
+                          + error_string());
+        }
+        PyErr_Restore(m_type.inc_ref().ptr(), m_value.inc_ref().ptr(), m_trace.inc_ref().ptr());
+        m_restore_called = true;
+    }
 
-    /// Give the currently-held error back to Python, if any.  If there is currently a Python error
-    /// already set it is cleared first.  After this call, the current object no longer stores the
-    /// error variables (but the `.what()` string is still available).
-    void restore() { PyErr_Restore(m_type.release().ptr(), m_value.release().ptr(), m_trace.release().ptr()); }
+    bool matches(handle exc) const {
+        return (PyErr_GivenExceptionMatches(m_type.ptr(), exc.ptr()) != 0);
+    }
 
-    /// If it is impossible to raise the currently-held error, such as in destructor, we can write
-    /// it out using Python's unraisable hook (sys.unraisablehook). The error context should be
-    /// some object whose repr() helps identify the location of the error. Python already knows the
-    /// type and value of the error, so there is no need to repeat that. For example, __func__ could
-    /// be helpful. After this call, the current object no longer stores the error variables,
-    /// and neither does Python.
+    // Not protecting these for simplicity.
+    object m_type, m_value, m_trace;
+
+private:
+    // Only protecting invariants.
+    mutable std::string m_lazy_error_string;
+    mutable bool m_lazy_error_string_completed = false;
+    mutable bool m_restore_called = false;
+};
+
+inline std::string error_string() {
+    return error_fetch_and_normalize("pybind11::detail::error_string").error_string();
+}
+
+PYBIND11_NAMESPACE_END(detail)
+
+#if defined(_MSC_VER)
+#    pragma warning(push)
+#    pragma warning(disable : 4275 4251)
+//     warning C4275: An exported class was derived from a class that wasn't exported.
+//     Can be ignored when derived from a STL class.
+#endif
+/// Fetch and hold an error which was already set in Python.  An instance of this is typically
+/// thrown to propagate python-side errors back through C++ which can either be caught manually or
+/// else falls back to the function dispatcher (which then raises the captured error back to
+/// python).
+class PYBIND11_EXPORT_EXCEPTION error_already_set : public std::exception {
+public:
+    /// Fetches the current Python exception (using PyErr_Fetch()), which will clear the
+    /// current Python error indicator.
+    error_already_set()
+        : m_fetched_error{new detail::error_fetch_and_normalize("pybind11::error_already_set"),
+                          m_fetched_error_deleter} {}
+
+    /// The what() result is built lazily on demand.
+    /// WARNING: This member function needs to acquire the Python GIL. This can lead to
+    ///          crashes (undefined behavior) if the Python interpreter is finalizing.
+    const char *what() const noexcept override;
+
+    /// Restores the currently-held Python error (which will clear the Python error indicator first
+    /// if already set).
+    /// NOTE: This member function will always restore the normalized exception, which may or may
+    ///       not be the original Python exception.
+    /// WARNING: The GIL must be held when this member function is called!
+    void restore() { m_fetched_error->restore(); }
+
+    /// If it is impossible to raise the currently-held error, such as in a destructor, we can
+    /// write it out using Python's unraisable hook (`sys.unraisablehook`). The error context
+    /// should be some object whose `repr()` helps identify the location of the error. Python
+    /// already knows the type and value of the error, so there is no need to repeat that.
     void discard_as_unraisable(object err_context) {
         restore();
         PyErr_WriteUnraisable(err_context.ptr());
     }
+    /// An alternate version of `discard_as_unraisable()`, where a string provides information on
+    /// the location of the error. For example, `__func__` could be helpful.
+    /// WARNING: The GIL must be held when this member function is called!
     void discard_as_unraisable(const char *err_context) {
         discard_as_unraisable(reinterpret_steal<object>(PYBIND11_FROM_STRING(err_context)));
     }
@@ -360,17 +657,60 @@ class error_already_set : public std::runtime_error {
     /// Check if the currently trapped error type matches the given Python exception class (or a
     /// subclass thereof).  May also be passed a tuple to search for any exception class matches in
     /// the given tuple.
-    bool matches(handle exc) const { return PyErr_GivenExceptionMatches(m_type.ptr(), exc.ptr()); }
+    bool matches(handle exc) const { return m_fetched_error->matches(exc); }
 
-    const object& type() const { return m_type; }
-    const object& value() const { return m_value; }
-    const object& trace() const { return m_trace; }
+    const object &type() const { return m_fetched_error->m_type; }
+    const object &value() const { return m_fetched_error->m_value; }
+    const object &trace() const { return m_fetched_error->m_trace; }
 
 private:
-    object m_type, m_value, m_trace;
+    std::shared_ptr<detail::error_fetch_and_normalize> m_fetched_error;
+
+    /// WARNING: This custom deleter needs to acquire the Python GIL. This can lead to
+    ///          crashes (undefined behavior) if the Python interpreter is finalizing.
+    static void m_fetched_error_deleter(detail::error_fetch_and_normalize *raw_ptr);
 };
+#if defined(_MSC_VER)
+#    pragma warning(pop)
+#endif
+
+/// Replaces the current Python error indicator with the chosen error, performing a
+/// 'raise from' to indicate that the chosen error was caused by the original error.
+inline void raise_from(PyObject *type, const char *message) {
+    // Based on _PyErr_FormatVFromCause:
+    // https://github.com/python/cpython/blob/467ab194fc6189d9f7310c89937c51abeac56839/Python/errors.c#L405
+    // See https://github.com/pybind/pybind11/pull/2112 for details.
+    PyObject *exc = nullptr, *val = nullptr, *val2 = nullptr, *tb = nullptr;
+
+    assert(PyErr_Occurred());
+    PyErr_Fetch(&exc, &val, &tb);
+    PyErr_NormalizeException(&exc, &val, &tb);
+    if (tb != nullptr) {
+        PyException_SetTraceback(val, tb);
+        Py_DECREF(tb);
+    }
+    Py_DECREF(exc);
+    assert(!PyErr_Occurred());
+
+    PyErr_SetString(type, message);
+
+    PyErr_Fetch(&exc, &val2, &tb);
+    PyErr_NormalizeException(&exc, &val2, &tb);
+    Py_INCREF(val);
+    PyException_SetCause(val2, val);
+    PyException_SetContext(val2, val);
+    PyErr_Restore(exc, val2, tb);
+}
+
+/// Sets the current Python error indicator with the chosen error, performing a 'raise from'
+/// from the error contained in error_already_set to indicate that the chosen error was
+/// caused by the original error.
+inline void raise_from(error_already_set &err, PyObject *type, const char *message) {
+    err.restore();
+    raise_from(type, message);
+}
 
-/** \defgroup python_builtins _
+/** \defgroup python_builtins const_name
     Unless stated otherwise, the following C++ functions behave the same
     as their Python counterparts.
  */
@@ -381,20 +721,29 @@ class error_already_set : public std::runtime_error {
     `object` or a class which was exposed to Python as ``py::class_<T>``.
 \endrst */
 template <typename T, detail::enable_if_t<std::is_base_of<object, T>::value, int> = 0>
-bool isinstance(handle obj) { return T::check_(obj); }
+bool isinstance(handle obj) {
+    return T::check_(obj);
+}
 
 template <typename T, detail::enable_if_t<!std::is_base_of<object, T>::value, int> = 0>
-bool isinstance(handle obj) { return detail::isinstance_generic(obj, typeid(T)); }
+bool isinstance(handle obj) {
+    return detail::isinstance_generic(obj, typeid(T));
+}
 
-template <> inline bool isinstance<handle>(handle) = delete;
-template <> inline bool isinstance<object>(handle obj) { return obj.ptr() != nullptr; }
+template <>
+inline bool isinstance<handle>(handle) = delete;
+template <>
+inline bool isinstance<object>(handle obj) {
+    return obj.ptr() != nullptr;
+}
 
 /// \ingroup python_builtins
 /// Return true if ``obj`` is an instance of the ``type``.
 inline bool isinstance(handle obj, handle type) {
     const auto result = PyObject_IsInstance(obj.ptr(), type.ptr());
-    if (result == -1)
+    if (result == -1) {
         throw error_already_set();
+    }
     return result != 0;
 }
 
@@ -409,54 +758,66 @@ inline bool hasattr(handle obj, const char *name) {
 }
 
 inline void delattr(handle obj, handle name) {
-    if (PyObject_DelAttr(obj.ptr(), name.ptr()) != 0) { throw error_already_set(); }
+    if (PyObject_DelAttr(obj.ptr(), name.ptr()) != 0) {
+        throw error_already_set();
+    }
 }
 
 inline void delattr(handle obj, const char *name) {
-    if (PyObject_DelAttrString(obj.ptr(), name) != 0) { throw error_already_set(); }
+    if (PyObject_DelAttrString(obj.ptr(), name) != 0) {
+        throw error_already_set();
+    }
 }
 
 inline object getattr(handle obj, handle name) {
     PyObject *result = PyObject_GetAttr(obj.ptr(), name.ptr());
-    if (!result) { throw error_already_set(); }
+    if (!result) {
+        throw error_already_set();
+    }
     return reinterpret_steal<object>(result);
 }
 
 inline object getattr(handle obj, const char *name) {
     PyObject *result = PyObject_GetAttrString(obj.ptr(), name);
-    if (!result) { throw error_already_set(); }
+    if (!result) {
+        throw error_already_set();
+    }
     return reinterpret_steal<object>(result);
 }
 
 inline object getattr(handle obj, handle name, handle default_) {
     if (PyObject *result = PyObject_GetAttr(obj.ptr(), name.ptr())) {
         return reinterpret_steal<object>(result);
-    } else {
-        PyErr_Clear();
-        return reinterpret_borrow<object>(default_);
     }
+    PyErr_Clear();
+    return reinterpret_borrow<object>(default_);
 }
 
 inline object getattr(handle obj, const char *name, handle default_) {
     if (PyObject *result = PyObject_GetAttrString(obj.ptr(), name)) {
         return reinterpret_steal<object>(result);
-    } else {
-        PyErr_Clear();
-        return reinterpret_borrow<object>(default_);
     }
+    PyErr_Clear();
+    return reinterpret_borrow<object>(default_);
 }
 
 inline void setattr(handle obj, handle name, handle value) {
-    if (PyObject_SetAttr(obj.ptr(), name.ptr(), value.ptr()) != 0) { throw error_already_set(); }
+    if (PyObject_SetAttr(obj.ptr(), name.ptr(), value.ptr()) != 0) {
+        throw error_already_set();
+    }
 }
 
 inline void setattr(handle obj, const char *name, handle value) {
-    if (PyObject_SetAttrString(obj.ptr(), name, value.ptr()) != 0) { throw error_already_set(); }
+    if (PyObject_SetAttrString(obj.ptr(), name, value.ptr()) != 0) {
+        throw error_already_set();
+    }
 }
 
 inline ssize_t hash(handle obj) {
     auto h = PyObject_Hash(obj.ptr());
-    if (h == -1) { throw error_already_set(); }
+    if (h == -1) {
+        throw error_already_set();
+    }
     return h;
 }
 
@@ -465,68 +826,114 @@ inline ssize_t hash(handle obj) {
 PYBIND11_NAMESPACE_BEGIN(detail)
 inline handle get_function(handle value) {
     if (value) {
-#if PY_MAJOR_VERSION >= 3
-        if (PyInstanceMethod_Check(value.ptr()))
+        if (PyInstanceMethod_Check(value.ptr())) {
             value = PyInstanceMethod_GET_FUNCTION(value.ptr());
-        else
-#endif
-        if (PyMethod_Check(value.ptr()))
+        } else if (PyMethod_Check(value.ptr())) {
             value = PyMethod_GET_FUNCTION(value.ptr());
+        }
     }
     return value;
 }
 
-// Helper aliases/functions to support implicit casting of values given to python accessors/methods.
-// When given a pyobject, this simply returns the pyobject as-is; for other C++ type, the value goes
-// through pybind11::cast(obj) to convert it to an `object`.
+// Reimplementation of python's dict helper functions to ensure that exceptions
+// aren't swallowed (see #2862)
+
+// copied from cpython _PyDict_GetItemStringWithError
+inline PyObject *dict_getitemstring(PyObject *v, const char *key) {
+    PyObject *kv = nullptr, *rv = nullptr;
+    kv = PyUnicode_FromString(key);
+    if (kv == nullptr) {
+        throw error_already_set();
+    }
+
+    rv = PyDict_GetItemWithError(v, kv);
+    Py_DECREF(kv);
+    if (rv == nullptr && PyErr_Occurred()) {
+        throw error_already_set();
+    }
+    return rv;
+}
+
+inline PyObject *dict_getitem(PyObject *v, PyObject *key) {
+    PyObject *rv = PyDict_GetItemWithError(v, key);
+    if (rv == nullptr && PyErr_Occurred()) {
+        throw error_already_set();
+    }
+    return rv;
+}
+
+// Helper aliases/functions to support implicit casting of values given to python
+// accessors/methods. When given a pyobject, this simply returns the pyobject as-is; for other C++
+// type, the value goes through pybind11::cast(obj) to convert it to an `object`.
 template <typename T, enable_if_t<is_pyobject<T>::value, int> = 0>
-auto object_or_cast(T &&o) -> decltype(std::forward<T>(o)) { return std::forward<T>(o); }
+auto object_or_cast(T &&o) -> decltype(std::forward<T>(o)) {
+    return std::forward<T>(o);
+}
 // The following casting version is implemented in cast.h:
 template <typename T, enable_if_t<!is_pyobject<T>::value, int> = 0>
 object object_or_cast(T &&o);
 // Match a PyObject*, which we want to convert directly to handle via its converting constructor
 inline handle object_or_cast(PyObject *ptr) { return ptr; }
 
+#if defined(_MSC_VER) && _MSC_VER < 1920
+#    pragma warning(push)
+#    pragma warning(disable : 4522) // warning C4522: multiple assignment operators specified
+#endif
 template <typename Policy>
 class accessor : public object_api<accessor<Policy>> {
     using key_type = typename Policy::key_type;
 
 public:
-    accessor(handle obj, key_type key) : obj(obj), key(std::move(key)) { }
+    accessor(handle obj, key_type key) : obj(obj), key(std::move(key)) {}
     accessor(const accessor &) = default;
-    accessor(accessor &&) = default;
+    accessor(accessor &&) noexcept = default;
 
-    // accessor overload required to override default assignment operator (templates are not allowed
-    // to replace default compiler-generated assignments).
+    // accessor overload required to override default assignment operator (templates are not
+    // allowed to replace default compiler-generated assignments).
     void operator=(const accessor &a) && { std::move(*this).operator=(handle(a)); }
     void operator=(const accessor &a) & { operator=(handle(a)); }
 
-    template <typename T> void operator=(T &&value) && {
+    template <typename T>
+    void operator=(T &&value) && {
         Policy::set(obj, key, object_or_cast(std::forward<T>(value)));
     }
-    template <typename T> void operator=(T &&value) & {
-        get_cache() = reinterpret_borrow<object>(object_or_cast(std::forward<T>(value)));
+    template <typename T>
+    void operator=(T &&value) & {
+        get_cache() = ensure_object(object_or_cast(std::forward<T>(value)));
     }
 
     template <typename T = Policy>
-    PYBIND11_DEPRECATED("Use of obj.attr(...) as bool is deprecated in favor of pybind11::hasattr(obj, ...)")
-    explicit operator enable_if_t<std::is_same<T, accessor_policies::str_attr>::value ||
-            std::is_same<T, accessor_policies::obj_attr>::value, bool>() const {
+    PYBIND11_DEPRECATED(
+        "Use of obj.attr(...) as bool is deprecated in favor of pybind11::hasattr(obj, ...)")
+    explicit
+    operator enable_if_t<std::is_same<T, accessor_policies::str_attr>::value
+                             || std::is_same<T, accessor_policies::obj_attr>::value,
+                         bool>() const {
         return hasattr(obj, key);
     }
     template <typename T = Policy>
     PYBIND11_DEPRECATED("Use of obj[key] as bool is deprecated in favor of obj.contains(key)")
-    explicit operator enable_if_t<std::is_same<T, accessor_policies::generic_item>::value, bool>() const {
+    explicit
+    operator enable_if_t<std::is_same<T, accessor_policies::generic_item>::value, bool>() const {
         return obj.contains(key);
     }
 
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator object() const { return get_cache(); }
     PyObject *ptr() const { return get_cache().ptr(); }
-    template <typename T> T cast() const { return get_cache().template cast<T>(); }
+    template <typename T>
+    T cast() const {
+        return get_cache().template cast<T>();
+    }
 
 private:
+    static object ensure_object(object &&o) { return std::move(o); }
+    static object ensure_object(handle h) { return reinterpret_borrow<object>(h); }
+
     object &get_cache() const {
-        if (!cache) { cache = Policy::get(obj, key); }
+        if (!cache) {
+            cache = Policy::get(obj, key);
+        }
         return cache;
     }
 
@@ -535,6 +942,9 @@ class accessor : public object_api<accessor<Policy>> {
     key_type key;
     mutable object cache;
 };
+#if defined(_MSC_VER) && _MSC_VER < 1920
+#    pragma warning(pop)
+#endif
 
 PYBIND11_NAMESPACE_BEGIN(accessor_policies)
 struct obj_attr {
@@ -554,27 +964,35 @@ struct generic_item {
 
     static object get(handle obj, handle key) {
         PyObject *result = PyObject_GetItem(obj.ptr(), key.ptr());
-        if (!result) { throw error_already_set(); }
+        if (!result) {
+            throw error_already_set();
+        }
         return reinterpret_steal<object>(result);
     }
 
     static void set(handle obj, handle key, handle val) {
-        if (PyObject_SetItem(obj.ptr(), key.ptr(), val.ptr()) != 0) { throw error_already_set(); }
+        if (PyObject_SetItem(obj.ptr(), key.ptr(), val.ptr()) != 0) {
+            throw error_already_set();
+        }
     }
 };
 
 struct sequence_item {
     using key_type = size_t;
 
-    static object get(handle obj, size_t index) {
-        PyObject *result = PySequence_GetItem(obj.ptr(), static_cast<ssize_t>(index));
-        if (!result) { throw error_already_set(); }
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static object get(handle obj, const IdxType &index) {
+        PyObject *result = PySequence_GetItem(obj.ptr(), ssize_t_cast(index));
+        if (!result) {
+            throw error_already_set();
+        }
         return reinterpret_steal<object>(result);
     }
 
-    static void set(handle obj, size_t index, handle val) {
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static void set(handle obj, const IdxType &index, handle val) {
         // PySequence_SetItem does not steal a reference to 'val'
-        if (PySequence_SetItem(obj.ptr(), static_cast<ssize_t>(index), val.ptr()) != 0) {
+        if (PySequence_SetItem(obj.ptr(), ssize_t_cast(index), val.ptr()) != 0) {
             throw error_already_set();
         }
     }
@@ -583,15 +1001,19 @@ struct sequence_item {
 struct list_item {
     using key_type = size_t;
 
-    static object get(handle obj, size_t index) {
-        PyObject *result = PyList_GetItem(obj.ptr(), static_cast<ssize_t>(index));
-        if (!result) { throw error_already_set(); }
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static object get(handle obj, const IdxType &index) {
+        PyObject *result = PyList_GetItem(obj.ptr(), ssize_t_cast(index));
+        if (!result) {
+            throw error_already_set();
+        }
         return reinterpret_borrow<object>(result);
     }
 
-    static void set(handle obj, size_t index, handle val) {
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static void set(handle obj, const IdxType &index, handle val) {
         // PyList_SetItem steals a reference to 'val'
-        if (PyList_SetItem(obj.ptr(), static_cast<ssize_t>(index), val.inc_ref().ptr()) != 0) {
+        if (PyList_SetItem(obj.ptr(), ssize_t_cast(index), val.inc_ref().ptr()) != 0) {
             throw error_already_set();
         }
     }
@@ -600,15 +1022,19 @@ struct list_item {
 struct tuple_item {
     using key_type = size_t;
 
-    static object get(handle obj, size_t index) {
-        PyObject *result = PyTuple_GetItem(obj.ptr(), static_cast<ssize_t>(index));
-        if (!result) { throw error_already_set(); }
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static object get(handle obj, const IdxType &index) {
+        PyObject *result = PyTuple_GetItem(obj.ptr(), ssize_t_cast(index));
+        if (!result) {
+            throw error_already_set();
+        }
         return reinterpret_borrow<object>(result);
     }
 
-    static void set(handle obj, size_t index, handle val) {
+    template <typename IdxType, detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    static void set(handle obj, const IdxType &index, handle val) {
         // PyTuple_SetItem steals a reference to 'val'
-        if (PyTuple_SetItem(obj.ptr(), static_cast<ssize_t>(index), val.inc_ref().ptr()) != 0) {
+        if (PyTuple_SetItem(obj.ptr(), ssize_t_cast(index), val.inc_ref().ptr()) != 0) {
             throw error_already_set();
         }
     }
@@ -628,28 +1054,56 @@ class generic_iterator : public Policy {
     using pointer = typename Policy::pointer;
 
     generic_iterator() = default;
-    generic_iterator(handle seq, ssize_t index) : Policy(seq, index) { }
+    generic_iterator(handle seq, ssize_t index) : Policy(seq, index) {}
 
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
     reference operator*() const { return Policy::dereference(); }
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
     reference operator[](difference_type n) const { return *(*this + n); }
     pointer operator->() const { return **this; }
 
-    It &operator++() { Policy::increment(); return *this; }
-    It operator++(int) { auto copy = *this; Policy::increment(); return copy; }
-    It &operator--() { Policy::decrement(); return *this; }
-    It operator--(int) { auto copy = *this; Policy::decrement(); return copy; }
-    It &operator+=(difference_type n) { Policy::advance(n); return *this; }
-    It &operator-=(difference_type n) { Policy::advance(-n); return *this; }
+    It &operator++() {
+        Policy::increment();
+        return *this;
+    }
+    It operator++(int) {
+        auto copy = *this;
+        Policy::increment();
+        return copy;
+    }
+    It &operator--() {
+        Policy::decrement();
+        return *this;
+    }
+    It operator--(int) {
+        auto copy = *this;
+        Policy::decrement();
+        return copy;
+    }
+    It &operator+=(difference_type n) {
+        Policy::advance(n);
+        return *this;
+    }
+    It &operator-=(difference_type n) {
+        Policy::advance(-n);
+        return *this;
+    }
 
-    friend It operator+(const It &a, difference_type n) { auto copy = a; return copy += n; }
+    friend It operator+(const It &a, difference_type n) {
+        auto copy = a;
+        return copy += n;
+    }
     friend It operator+(difference_type n, const It &b) { return b + n; }
-    friend It operator-(const It &a, difference_type n) { auto copy = a; return copy -= n; }
+    friend It operator-(const It &a, difference_type n) {
+        auto copy = a;
+        return copy -= n;
+    }
     friend difference_type operator-(const It &a, const It &b) { return a.distance_to(b); }
 
     friend bool operator==(const It &a, const It &b) { return a.equal(b); }
     friend bool operator!=(const It &a, const It &b) { return !(a == b); }
-    friend bool operator< (const It &a, const It &b) { return b - a > 0; }
-    friend bool operator> (const It &a, const It &b) { return b < a; }
+    friend bool operator<(const It &a, const It &b) { return b - a > 0; }
+    friend bool operator>(const It &a, const It &b) { return b < a; }
     friend bool operator>=(const It &a, const It &b) { return !(a < b); }
     friend bool operator<=(const It &a, const It &b) { return !(a > b); }
 };
@@ -660,7 +1114,8 @@ template <typename T>
 struct arrow_proxy {
     T value;
 
-    arrow_proxy(T &&value) : value(std::move(value)) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    arrow_proxy(T &&value) noexcept : value(std::move(value)) {}
     T *operator->() const { return &value; }
 };
 
@@ -669,11 +1124,12 @@ class sequence_fast_readonly {
 protected:
     using iterator_category = std::random_access_iterator_tag;
     using value_type = handle;
-    using reference = const handle;
+    using reference = const handle; // PR #3263
     using pointer = arrow_proxy<const handle>;
 
-    sequence_fast_readonly(handle obj, ssize_t n) : ptr(PySequence_Fast_ITEMS(obj.ptr()) + n) { }
+    sequence_fast_readonly(handle obj, ssize_t n) : ptr(PySequence_Fast_ITEMS(obj.ptr()) + n) {}
 
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
     reference dereference() const { return *ptr; }
     void increment() { ++ptr; }
     void decrement() { --ptr; }
@@ -693,7 +1149,7 @@ class sequence_slow_readwrite {
     using reference = sequence_accessor;
     using pointer = arrow_proxy<const sequence_accessor>;
 
-    sequence_slow_readwrite(handle obj, ssize_t index) : obj(obj), index(index) { }
+    sequence_slow_readwrite(handle obj, ssize_t index) : obj(obj), index(index) {}
 
     reference dereference() const { return {obj, static_cast<size_t>(index)}; }
     void increment() { ++index; }
@@ -712,14 +1168,19 @@ class dict_readonly {
 protected:
     using iterator_category = std::forward_iterator_tag;
     using value_type = std::pair<handle, handle>;
-    using reference = const value_type;
+    using reference = const value_type; // PR #3263
     using pointer = arrow_proxy<const value_type>;
 
     dict_readonly() = default;
     dict_readonly(handle obj, ssize_t pos) : obj(obj), pos(pos) { increment(); }
 
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
     reference dereference() const { return {key, value}; }
-    void increment() { if (!PyDict_Next(obj.ptr(), &pos, &key, &value)) { pos = -1; } }
+    void increment() {
+        if (PyDict_Next(obj.ptr(), &pos, &key, &value) == 0) {
+            pos = -1;
+        }
+    }
     bool equal(const dict_readonly &b) const { return pos == b.pos; }
 
 private:
@@ -745,38 +1206,47 @@ inline bool PyIterable_Check(PyObject *obj) {
     if (iter) {
         Py_DECREF(iter);
         return true;
-    } else {
-        PyErr_Clear();
-        return false;
     }
+    PyErr_Clear();
+    return false;
 }
 
 inline bool PyNone_Check(PyObject *o) { return o == Py_None; }
 inline bool PyEllipsis_Check(PyObject *o) { return o == Py_Ellipsis; }
 
-inline bool PyUnicode_Check_Permissive(PyObject *o) { return PyUnicode_Check(o) || PYBIND11_BYTES_CHECK(o); }
+#ifdef PYBIND11_STR_LEGACY_PERMISSIVE
+inline bool PyUnicode_Check_Permissive(PyObject *o) {
+    return PyUnicode_Check(o) || PYBIND11_BYTES_CHECK(o);
+}
+#    define PYBIND11_STR_CHECK_FUN detail::PyUnicode_Check_Permissive
+#else
+#    define PYBIND11_STR_CHECK_FUN PyUnicode_Check
+#endif
 
 inline bool PyStaticMethod_Check(PyObject *o) { return o->ob_type == &PyStaticMethod_Type; }
 
 class kwargs_proxy : public handle {
 public:
-    explicit kwargs_proxy(handle h) : handle(h) { }
+    explicit kwargs_proxy(handle h) : handle(h) {}
 };
 
 class args_proxy : public handle {
 public:
-    explicit args_proxy(handle h) : handle(h) { }
+    explicit args_proxy(handle h) : handle(h) {}
     kwargs_proxy operator*() const { return kwargs_proxy(*this); }
 };
 
 /// Python argument categories (using PEP 448 terms)
-template <typename T> using is_keyword = std::is_base_of<arg, T>;
-template <typename T> using is_s_unpacking = std::is_same<args_proxy, T>; // * unpacking
-template <typename T> using is_ds_unpacking = std::is_same<kwargs_proxy, T>; // ** unpacking
-template <typename T> using is_positional = satisfies_none_of<T,
-    is_keyword, is_s_unpacking, is_ds_unpacking
->;
-template <typename T> using is_keyword_or_ds = satisfies_any_of<T, is_keyword, is_ds_unpacking>;
+template <typename T>
+using is_keyword = std::is_base_of<arg, T>;
+template <typename T>
+using is_s_unpacking = std::is_same<args_proxy, T>; // * unpacking
+template <typename T>
+using is_ds_unpacking = std::is_same<kwargs_proxy, T>; // ** unpacking
+template <typename T>
+using is_positional = satisfies_none_of<T, is_keyword, is_s_unpacking, is_ds_unpacking>;
+template <typename T>
+using is_keyword_or_ds = satisfies_any_of<T, is_keyword, is_ds_unpacking>;
 
 // Call argument collector forward declarations
 template <return_value_policy policy = return_value_policy::automatic_reference>
@@ -790,44 +1260,60 @@ PYBIND11_NAMESPACE_END(detail)
 //       inheriting ctors: `using Parent::Parent`. It's not an option right now because
 //       the `using` statement triggers the parent deprecation warning even if the ctor
 //       isn't even used.
-#define PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun) \
-    public: \
-        PYBIND11_DEPRECATED("Use reinterpret_borrow<"#Name">() or reinterpret_steal<"#Name">()") \
-        Name(handle h, bool is_borrowed) : Parent(is_borrowed ? Parent(h, borrowed_t{}) : Parent(h, stolen_t{})) { } \
-        Name(handle h, borrowed_t) : Parent(h, borrowed_t{}) { } \
-        Name(handle h, stolen_t) : Parent(h, stolen_t{}) { } \
-        PYBIND11_DEPRECATED("Use py::isinstance<py::python_type>(obj) instead") \
-        bool check() const { return m_ptr != nullptr && (bool) CheckFun(m_ptr); } \
-        static bool check_(handle h) { return h.ptr() != nullptr && CheckFun(h.ptr()); } \
-        template <typename Policy_> \
-        Name(const ::pybind11::detail::accessor<Policy_> &a) : Name(object(a)) { }
-
-#define PYBIND11_OBJECT_CVT(Name, Parent, CheckFun, ConvertFun) \
-    PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun) \
-    /* This is deliberately not 'explicit' to allow implicit conversion from object: */ \
-    Name(const object &o) \
-    : Parent(check_(o) ? o.inc_ref().ptr() : ConvertFun(o.ptr()), stolen_t{}) \
-    { if (!m_ptr) throw error_already_set(); } \
-    Name(object &&o) \
-    : Parent(check_(o) ? o.release().ptr() : ConvertFun(o.ptr()), stolen_t{}) \
-    { if (!m_ptr) throw error_already_set(); }
-
-#define PYBIND11_OBJECT_CHECK_FAILED(Name, o) \
-    ::pybind11::type_error("Object of type '" + \
-                           ::pybind11::detail::get_fully_qualified_tp_name(Py_TYPE(o.ptr())) + \
-                           "' is not an instance of '" #Name "'")
-
-#define PYBIND11_OBJECT(Name, Parent, CheckFun) \
-    PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun) \
-    /* This is deliberately not 'explicit' to allow implicit conversion from object: */ \
-    Name(const object &o) : Parent(o) \
-    { if (o && !check_(o)) throw PYBIND11_OBJECT_CHECK_FAILED(Name, o); } \
-    Name(object &&o) : Parent(std::move(o)) \
-    { if (o && !check_(o)) throw PYBIND11_OBJECT_CHECK_FAILED(Name, o); }
-
-#define PYBIND11_OBJECT_DEFAULT(Name, Parent, CheckFun) \
-    PYBIND11_OBJECT(Name, Parent, CheckFun) \
-    Name() : Parent() { }
+#define PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun)                                            \
+public:                                                                                           \
+    PYBIND11_DEPRECATED("Use reinterpret_borrow<" #Name ">() or reinterpret_steal<" #Name ">()")  \
+    Name(handle h, bool is_borrowed)                                                              \
+        : Parent(is_borrowed ? Parent(h, borrowed_t{}) : Parent(h, stolen_t{})) {}                \
+    Name(handle h, borrowed_t) : Parent(h, borrowed_t{}) {}                                       \
+    Name(handle h, stolen_t) : Parent(h, stolen_t{}) {}                                           \
+    PYBIND11_DEPRECATED("Use py::isinstance<py::python_type>(obj) instead")                       \
+    bool check() const { return m_ptr != nullptr && (CheckFun(m_ptr) != 0); }                     \
+    static bool check_(handle h) { return h.ptr() != nullptr && CheckFun(h.ptr()); }              \
+    template <typename Policy_> /* NOLINTNEXTLINE(google-explicit-constructor) */                 \
+    Name(const ::pybind11::detail::accessor<Policy_> &a) : Name(object(a)) {}
+
+#define PYBIND11_OBJECT_CVT(Name, Parent, CheckFun, ConvertFun)                                   \
+    PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun)                                                \
+    /* This is deliberately not 'explicit' to allow implicit conversion from object: */           \
+    /* NOLINTNEXTLINE(google-explicit-constructor) */                                             \
+    Name(const object &o)                                                                         \
+        : Parent(check_(o) ? o.inc_ref().ptr() : ConvertFun(o.ptr()), stolen_t{}) {               \
+        if (!m_ptr)                                                                               \
+            throw ::pybind11::error_already_set();                                                \
+    }                                                                                             \
+    /* NOLINTNEXTLINE(google-explicit-constructor) */                                             \
+    Name(object &&o) : Parent(check_(o) ? o.release().ptr() : ConvertFun(o.ptr()), stolen_t{}) {  \
+        if (!m_ptr)                                                                               \
+            throw ::pybind11::error_already_set();                                                \
+    }
+
+#define PYBIND11_OBJECT_CVT_DEFAULT(Name, Parent, CheckFun, ConvertFun)                           \
+    PYBIND11_OBJECT_CVT(Name, Parent, CheckFun, ConvertFun)                                       \
+    Name() = default;
+
+#define PYBIND11_OBJECT_CHECK_FAILED(Name, o_ptr)                                                 \
+    ::pybind11::type_error("Object of type '"                                                     \
+                           + ::pybind11::detail::get_fully_qualified_tp_name(Py_TYPE(o_ptr))      \
+                           + "' is not an instance of '" #Name "'")
+
+#define PYBIND11_OBJECT(Name, Parent, CheckFun)                                                   \
+    PYBIND11_OBJECT_COMMON(Name, Parent, CheckFun)                                                \
+    /* This is deliberately not 'explicit' to allow implicit conversion from object: */           \
+    /* NOLINTNEXTLINE(google-explicit-constructor) */                                             \
+    Name(const object &o) : Parent(o) {                                                           \
+        if (m_ptr && !check_(m_ptr))                                                              \
+            throw PYBIND11_OBJECT_CHECK_FAILED(Name, m_ptr);                                      \
+    }                                                                                             \
+    /* NOLINTNEXTLINE(google-explicit-constructor) */                                             \
+    Name(object &&o) : Parent(std::move(o)) {                                                     \
+        if (m_ptr && !check_(m_ptr))                                                              \
+            throw PYBIND11_OBJECT_CHECK_FAILED(Name, m_ptr);                                      \
+    }
+
+#define PYBIND11_OBJECT_DEFAULT(Name, Parent, CheckFun)                                           \
+    PYBIND11_OBJECT(Name, Parent, CheckFun)                                                       \
+    Name() = default;
 
 /// \addtogroup pytypes
 /// @{
@@ -845,12 +1331,12 @@ class iterator : public object {
     using iterator_category = std::input_iterator_tag;
     using difference_type = ssize_t;
     using value_type = handle;
-    using reference = const handle;
+    using reference = const handle; // PR #3263
     using pointer = const handle *;
 
     PYBIND11_OBJECT_DEFAULT(iterator, object, PyIter_Check)
 
-    iterator& operator++() {
+    iterator &operator++() {
         advance();
         return *this;
     }
@@ -861,15 +1347,19 @@ class iterator : public object {
         return rv;
     }
 
+    // NOLINTNEXTLINE(readability-const-return-type) // PR #3263
     reference operator*() const {
         if (m_ptr && !value.ptr()) {
-            auto& self = const_cast<iterator &>(*this);
+            auto &self = const_cast<iterator &>(*this);
             self.advance();
         }
         return value;
     }
 
-    pointer operator->() const { operator*(); return &value; }
+    pointer operator->() const {
+        operator*();
+        return &value;
+    }
 
     /** \rst
          The value which marks the end of the iteration. ``it == iterator::sentinel()``
@@ -892,21 +1382,21 @@ class iterator : public object {
 private:
     void advance() {
         value = reinterpret_steal<object>(PyIter_Next(m_ptr));
-        if (PyErr_Occurred()) { throw error_already_set(); }
+        if (PyErr_Occurred()) {
+            throw error_already_set();
+        }
     }
 
 private:
     object value = {};
 };
 
-
-
 class type : public object {
 public:
     PYBIND11_OBJECT(type, object, PyType_Check)
 
     /// Return a type handle from a handle or an object
-    static handle handle_of(handle h) { return handle((PyObject*) Py_TYPE(h.ptr())); }
+    static handle handle_of(handle h) { return handle((PyObject *) Py_TYPE(h.ptr())); }
 
     /// Return a type object from a handle or an object
     static type of(handle h) { return type(type::handle_of(h), borrowed_t{}); }
@@ -915,14 +1405,16 @@ class type : public object {
     /// Convert C++ type to handle if previously registered. Does not convert
     /// standard types, like int, float. etc. yet.
     /// See https://github.com/pybind/pybind11/issues/2486
-    template<typename T>
+    template <typename T>
     static handle handle_of();
 
     /// Convert C++ type to type if previously registered. Does not convert
     /// standard types, like int, float. etc. yet.
     /// See https://github.com/pybind/pybind11/issues/2486
-    template<typename T>
-    static type of() {return type(type::handle_of<T>(), borrowed_t{}); }
+    template <typename T>
+    static type of() {
+        return type(type::handle_of<T>(), borrowed_t{});
+    }
 };
 
 class iterable : public object {
@@ -934,20 +1426,41 @@ class bytes;
 
 class str : public object {
 public:
-    PYBIND11_OBJECT_CVT(str, object, detail::PyUnicode_Check_Permissive, raw_str)
+    PYBIND11_OBJECT_CVT(str, object, PYBIND11_STR_CHECK_FUN, raw_str)
 
-    str(const char *c, size_t n)
-        : object(PyUnicode_FromStringAndSize(c, (ssize_t) n), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate string object!");
+    template <typename SzType, detail::enable_if_t<std::is_integral<SzType>::value, int> = 0>
+    str(const char *c, const SzType &n)
+        : object(PyUnicode_FromStringAndSize(c, ssize_t_cast(n)), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate string object!");
+        }
     }
 
-    // 'explicit' is explicitly omitted from the following constructors to allow implicit conversion to py::str from C++ string-like objects
-    str(const char *c = "")
-        : object(PyUnicode_FromString(c), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate string object!");
+    // 'explicit' is explicitly omitted from the following constructors to allow implicit
+    // conversion to py::str from C++ string-like objects
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    str(const char *c = "") : object(PyUnicode_FromString(c), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate string object!");
+        }
     }
 
-    str(const std::string &s) : str(s.data(), s.size()) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    str(const std::string &s) : str(s.data(), s.size()) {}
+
+#ifdef PYBIND11_HAS_STRING_VIEW
+    // enable_if is needed to avoid "ambiguous conversion" errors (see PR #3521).
+    template <typename T, detail::enable_if_t<std::is_same<T, std::string_view>::value, int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    str(T s) : str(s.data(), s.size()) {}
+
+#    ifdef PYBIND11_HAS_U8STRING
+    // reinterpret_cast here is safe (C++20 guarantees char8_t has the same size/alignment as char)
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    str(std::u8string_view s) : str(reinterpret_cast<const char *>(s.data()), s.size()) {}
+#    endif
+
+#endif
 
     explicit str(const bytes &b);
 
@@ -955,19 +1468,26 @@ class str : public object {
         Return a string representation of the object. This is analogous to
         the ``str()`` function in Python.
     \endrst */
-    explicit str(handle h) : object(raw_str(h.ptr()), stolen_t{}) { if (!m_ptr) throw error_already_set(); }
+    explicit str(handle h) : object(raw_str(h.ptr()), stolen_t{}) {
+        if (!m_ptr) {
+            throw error_already_set();
+        }
+    }
 
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator std::string() const {
         object temp = *this;
         if (PyUnicode_Check(m_ptr)) {
             temp = reinterpret_steal<object>(PyUnicode_AsUTF8String(m_ptr));
-            if (!temp)
-                pybind11_fail("Unable to extract string contents! (encoding issue)");
+            if (!temp) {
+                throw error_already_set();
+            }
+        }
+        char *buffer = nullptr;
+        ssize_t length = 0;
+        if (PyBytes_AsStringAndSize(temp.ptr(), &buffer, &length) != 0) {
+            throw error_already_set();
         }
-        char *buffer;
-        ssize_t length;
-        if (PYBIND11_BYTES_AS_STRING_AND_SIZE(temp.ptr(), &buffer, &length))
-            pybind11_fail("Unable to extract string contents! (invalid type)");
         return std::string(buffer, (size_t) length);
     }
 
@@ -980,11 +1500,6 @@ class str : public object {
     /// Return string representation -- always returns a new reference, even if already a str
     static PyObject *raw_str(PyObject *op) {
         PyObject *str_value = PyObject_Str(op);
-#if PY_MAJOR_VERSION < 3
-        if (!str_value) throw error_already_set();
-        PyObject *unicode = PyUnicode_FromEncodedObject(str_value, "utf-8", nullptr);
-        Py_XDECREF(str_value); str_value = unicode;
-#endif
         return str_value;
     }
 };
@@ -1004,27 +1519,51 @@ class bytes : public object {
     PYBIND11_OBJECT(bytes, object, PYBIND11_BYTES_CHECK)
 
     // Allow implicit conversion:
-    bytes(const char *c = "")
-        : object(PYBIND11_BYTES_FROM_STRING(c), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate bytes object!");
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    bytes(const char *c = "") : object(PYBIND11_BYTES_FROM_STRING(c), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate bytes object!");
+        }
     }
 
-    bytes(const char *c, size_t n)
-        : object(PYBIND11_BYTES_FROM_STRING_AND_SIZE(c, (ssize_t) n), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate bytes object!");
+    template <typename SzType, detail::enable_if_t<std::is_integral<SzType>::value, int> = 0>
+    bytes(const char *c, const SzType &n)
+        : object(PYBIND11_BYTES_FROM_STRING_AND_SIZE(c, ssize_t_cast(n)), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate bytes object!");
+        }
     }
 
     // Allow implicit conversion:
-    bytes(const std::string &s) : bytes(s.data(), s.size()) { }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    bytes(const std::string &s) : bytes(s.data(), s.size()) {}
 
     explicit bytes(const pybind11::str &s);
 
-    operator std::string() const {
-        char *buffer;
-        ssize_t length;
-        if (PYBIND11_BYTES_AS_STRING_AND_SIZE(m_ptr, &buffer, &length))
-            pybind11_fail("Unable to extract bytes contents!");
-        return std::string(buffer, (size_t) length);
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator std::string() const { return string_op<std::string>(); }
+
+#ifdef PYBIND11_HAS_STRING_VIEW
+    // enable_if is needed to avoid "ambiguous conversion" errors (see PR #3521).
+    template <typename T, detail::enable_if_t<std::is_same<T, std::string_view>::value, int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    bytes(T s) : bytes(s.data(), s.size()) {}
+
+    // Obtain a string view that views the current `bytes` buffer value.  Note that this is only
+    // valid so long as the `bytes` instance remains alive and so generally should not outlive the
+    // lifetime of the `bytes` instance.
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator std::string_view() const { return string_op<std::string_view>(); }
+#endif
+private:
+    template <typename T>
+    T string_op() const {
+        char *buffer = nullptr;
+        ssize_t length = 0;
+        if (PyBytes_AsStringAndSize(m_ptr, &buffer, &length) != 0) {
+            throw error_already_set();
+        }
+        return {buffer, static_cast<size_t>(length)};
     }
 };
 // Note: breathe >= 4.17.0 will fail to build docs if the below two constructors
@@ -1035,58 +1574,97 @@ inline bytes::bytes(const pybind11::str &s) {
     object temp = s;
     if (PyUnicode_Check(s.ptr())) {
         temp = reinterpret_steal<object>(PyUnicode_AsUTF8String(s.ptr()));
-        if (!temp)
-            pybind11_fail("Unable to extract string contents! (encoding issue)");
+        if (!temp) {
+            throw error_already_set();
+        }
+    }
+    char *buffer = nullptr;
+    ssize_t length = 0;
+    if (PyBytes_AsStringAndSize(temp.ptr(), &buffer, &length) != 0) {
+        throw error_already_set();
     }
-    char *buffer;
-    ssize_t length;
-    if (PYBIND11_BYTES_AS_STRING_AND_SIZE(temp.ptr(), &buffer, &length))
-        pybind11_fail("Unable to extract string contents! (invalid type)");
     auto obj = reinterpret_steal<object>(PYBIND11_BYTES_FROM_STRING_AND_SIZE(buffer, length));
-    if (!obj)
+    if (!obj) {
         pybind11_fail("Could not allocate bytes object!");
+    }
     m_ptr = obj.release().ptr();
 }
 
-inline str::str(const bytes& b) {
-    char *buffer;
-    ssize_t length;
-    if (PYBIND11_BYTES_AS_STRING_AND_SIZE(b.ptr(), &buffer, &length))
-        pybind11_fail("Unable to extract bytes contents!");
-    auto obj = reinterpret_steal<object>(PyUnicode_FromStringAndSize(buffer, (ssize_t) length));
-    if (!obj)
+inline str::str(const bytes &b) {
+    char *buffer = nullptr;
+    ssize_t length = 0;
+    if (PyBytes_AsStringAndSize(b.ptr(), &buffer, &length) != 0) {
+        throw error_already_set();
+    }
+    auto obj = reinterpret_steal<object>(PyUnicode_FromStringAndSize(buffer, length));
+    if (!obj) {
         pybind11_fail("Could not allocate string object!");
+    }
     m_ptr = obj.release().ptr();
 }
 
+/// \addtogroup pytypes
+/// @{
+class bytearray : public object {
+public:
+    PYBIND11_OBJECT_CVT(bytearray, object, PyByteArray_Check, PyByteArray_FromObject)
+
+    template <typename SzType, detail::enable_if_t<std::is_integral<SzType>::value, int> = 0>
+    bytearray(const char *c, const SzType &n)
+        : object(PyByteArray_FromStringAndSize(c, ssize_t_cast(n)), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate bytearray object!");
+        }
+    }
+
+    bytearray() : bytearray("", 0) {}
+
+    explicit bytearray(const std::string &s) : bytearray(s.data(), s.size()) {}
+
+    size_t size() const { return static_cast<size_t>(PyByteArray_Size(m_ptr)); }
+
+    explicit operator std::string() const {
+        char *buffer = PyByteArray_AS_STRING(m_ptr);
+        ssize_t size = PyByteArray_GET_SIZE(m_ptr);
+        return std::string(buffer, static_cast<size_t>(size));
+    }
+};
+// Note: breathe >= 4.17.0 will fail to build docs if the below two constructors
+// are included in the doxygen group; close here and reopen after as a workaround
+/// @} pytypes
+
 /// \addtogroup pytypes
 /// @{
 class none : public object {
 public:
     PYBIND11_OBJECT(none, object, detail::PyNone_Check)
-    none() : object(Py_None, borrowed_t{}) { }
+    none() : object(Py_None, borrowed_t{}) {}
 };
 
 class ellipsis : public object {
 public:
     PYBIND11_OBJECT(ellipsis, object, detail::PyEllipsis_Check)
-    ellipsis() : object(Py_Ellipsis, borrowed_t{}) { }
+    ellipsis() : object(Py_Ellipsis, borrowed_t{}) {}
 };
 
 class bool_ : public object {
 public:
     PYBIND11_OBJECT_CVT(bool_, object, PyBool_Check, raw_bool)
-    bool_() : object(Py_False, borrowed_t{}) { }
+    bool_() : object(Py_False, borrowed_t{}) {}
     // Allow implicit conversion from and to `bool`:
-    bool_(bool value) : object(value ? Py_True : Py_False, borrowed_t{}) { }
-    operator bool() const { return m_ptr && PyLong_AsLong(m_ptr) != 0; }
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    bool_(bool value) : object(value ? Py_True : Py_False, borrowed_t{}) {}
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    operator bool() const { return (m_ptr != nullptr) && PyLong_AsLong(m_ptr) != 0; }
 
 private:
     /// Return the truth value of an object -- always returns a new reference
     static PyObject *raw_bool(PyObject *op) {
         const auto value = PyObject_IsTrue(op);
-        if (value == -1) return nullptr;
-        return handle(value ? Py_True : Py_False).inc_ref().ptr();
+        if (value == -1) {
+            return nullptr;
+        }
+        return handle(value != 0 ? Py_True : Py_False).inc_ref().ptr();
     }
 };
 
@@ -1097,51 +1675,47 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 // unsigned type: (A)-1 != (B)-1 when A and B are unsigned types of different sizes).
 template <typename Unsigned>
 Unsigned as_unsigned(PyObject *o) {
-    if (sizeof(Unsigned) <= sizeof(unsigned long)
-#if PY_VERSION_HEX < 0x03000000
-            || PyInt_Check(o)
-#endif
-    ) {
+    if (PYBIND11_SILENCE_MSVC_C4127(sizeof(Unsigned) <= sizeof(unsigned long))) {
         unsigned long v = PyLong_AsUnsignedLong(o);
         return v == (unsigned long) -1 && PyErr_Occurred() ? (Unsigned) -1 : (Unsigned) v;
     }
-    else {
-        unsigned long long v = PyLong_AsUnsignedLongLong(o);
-        return v == (unsigned long long) -1 && PyErr_Occurred() ? (Unsigned) -1 : (Unsigned) v;
-    }
+    unsigned long long v = PyLong_AsUnsignedLongLong(o);
+    return v == (unsigned long long) -1 && PyErr_Occurred() ? (Unsigned) -1 : (Unsigned) v;
 }
 PYBIND11_NAMESPACE_END(detail)
 
 class int_ : public object {
 public:
     PYBIND11_OBJECT_CVT(int_, object, PYBIND11_LONG_CHECK, PyNumber_Long)
-    int_() : object(PyLong_FromLong(0), stolen_t{}) { }
+    int_() : object(PyLong_FromLong(0), stolen_t{}) {}
     // Allow implicit conversion from C++ integral types:
-    template <typename T,
-              detail::enable_if_t<std::is_integral<T>::value, int> = 0>
+    template <typename T, detail::enable_if_t<std::is_integral<T>::value, int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
     int_(T value) {
-        if (sizeof(T) <= sizeof(long)) {
-            if (std::is_signed<T>::value)
+        if (PYBIND11_SILENCE_MSVC_C4127(sizeof(T) <= sizeof(long))) {
+            if (std::is_signed<T>::value) {
                 m_ptr = PyLong_FromLong((long) value);
-            else
+            } else {
                 m_ptr = PyLong_FromUnsignedLong((unsigned long) value);
+            }
         } else {
-            if (std::is_signed<T>::value)
+            if (std::is_signed<T>::value) {
                 m_ptr = PyLong_FromLongLong((long long) value);
-            else
+            } else {
                 m_ptr = PyLong_FromUnsignedLongLong((unsigned long long) value);
+            }
+        }
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate int object!");
         }
-        if (!m_ptr) pybind11_fail("Could not allocate int object!");
     }
 
-    template <typename T,
-              detail::enable_if_t<std::is_integral<T>::value, int> = 0>
+    template <typename T, detail::enable_if_t<std::is_integral<T>::value, int> = 0>
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator T() const {
-        return std::is_unsigned<T>::value
-            ? detail::as_unsigned<T>(m_ptr)
-            : sizeof(T) <= sizeof(long)
-              ? (T) PyLong_AsLong(m_ptr)
-              : (T) PYBIND11_LONG_AS_LONGLONG(m_ptr);
+        return std::is_unsigned<T>::value  ? detail::as_unsigned<T>(m_ptr)
+               : sizeof(T) <= sizeof(long) ? (T) PyLong_AsLong(m_ptr)
+                                           : (T) PYBIND11_LONG_AS_LONGLONG(m_ptr);
     }
 };
 
@@ -1149,46 +1723,80 @@ class float_ : public object {
 public:
     PYBIND11_OBJECT_CVT(float_, object, PyFloat_Check, PyNumber_Float)
     // Allow implicit conversion from float/double:
+    // NOLINTNEXTLINE(google-explicit-constructor)
     float_(float value) : object(PyFloat_FromDouble((double) value), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate float object!");
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate float object!");
+        }
     }
+    // NOLINTNEXTLINE(google-explicit-constructor)
     float_(double value = .0) : object(PyFloat_FromDouble((double) value), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate float object!");
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate float object!");
+        }
     }
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator float() const { return (float) PyFloat_AsDouble(m_ptr); }
+    // NOLINTNEXTLINE(google-explicit-constructor)
     operator double() const { return (double) PyFloat_AsDouble(m_ptr); }
 };
 
 class weakref : public object {
 public:
-    PYBIND11_OBJECT_DEFAULT(weakref, object, PyWeakref_Check)
+    PYBIND11_OBJECT_CVT_DEFAULT(weakref, object, PyWeakref_Check, raw_weakref)
     explicit weakref(handle obj, handle callback = {})
         : object(PyWeakref_NewRef(obj.ptr(), callback.ptr()), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate weak reference!");
+        if (!m_ptr) {
+            if (PyErr_Occurred()) {
+                throw error_already_set();
+            }
+            pybind11_fail("Could not allocate weak reference!");
+        }
     }
+
+private:
+    static PyObject *raw_weakref(PyObject *o) { return PyWeakref_NewRef(o, nullptr); }
 };
 
 class slice : public object {
 public:
     PYBIND11_OBJECT_DEFAULT(slice, object, PySlice_Check)
-    slice(ssize_t start_, ssize_t stop_, ssize_t step_) {
-        int_ start(start_), stop(stop_), step(step_);
-        m_ptr = PySlice_New(start.ptr(), stop.ptr(), step.ptr());
-        if (!m_ptr) pybind11_fail("Could not allocate slice object!");
+    slice(handle start, handle stop, handle step)
+        : object(PySlice_New(start.ptr(), stop.ptr(), step.ptr()), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate slice object!");
+        }
     }
-    bool compute(size_t length, size_t *start, size_t *stop, size_t *step,
-                 size_t *slicelength) const {
+
+#ifdef PYBIND11_HAS_OPTIONAL
+    slice(std::optional<ssize_t> start, std::optional<ssize_t> stop, std::optional<ssize_t> step)
+        : slice(index_to_object(start), index_to_object(stop), index_to_object(step)) {}
+#else
+    slice(ssize_t start_, ssize_t stop_, ssize_t step_)
+        : slice(int_(start_), int_(stop_), int_(step_)) {}
+#endif
+
+    bool
+    compute(size_t length, size_t *start, size_t *stop, size_t *step, size_t *slicelength) const {
         return PySlice_GetIndicesEx((PYBIND11_SLICE_OBJECT *) m_ptr,
-                                    (ssize_t) length, (ssize_t *) start,
-                                    (ssize_t *) stop, (ssize_t *) step,
-                                    (ssize_t *) slicelength) == 0;
+                                    (ssize_t) length,
+                                    (ssize_t *) start,
+                                    (ssize_t *) stop,
+                                    (ssize_t *) step,
+                                    (ssize_t *) slicelength)
+               == 0;
     }
-    bool compute(ssize_t length, ssize_t *start, ssize_t *stop, ssize_t *step,
-      ssize_t *slicelength) const {
-      return PySlice_GetIndicesEx((PYBIND11_SLICE_OBJECT *) m_ptr,
-          length, start,
-          stop, step,
-          slicelength) == 0;
+    bool compute(
+        ssize_t length, ssize_t *start, ssize_t *stop, ssize_t *step, ssize_t *slicelength) const {
+        return PySlice_GetIndicesEx(
+                   (PYBIND11_SLICE_OBJECT *) m_ptr, length, start, stop, step, slicelength)
+               == 0;
+    }
+
+private:
+    template <typename T>
+    static object index_to_object(T index) {
+        return index ? object(int_(*index)) : object(none());
     }
 };
 
@@ -1196,107 +1804,178 @@ class capsule : public object {
 public:
     PYBIND11_OBJECT_DEFAULT(capsule, object, PyCapsule_CheckExact)
     PYBIND11_DEPRECATED("Use reinterpret_borrow<capsule>() or reinterpret_steal<capsule>()")
-    capsule(PyObject *ptr, bool is_borrowed) : object(is_borrowed ? object(ptr, borrowed_t{}) : object(ptr, stolen_t{})) { }
+    capsule(PyObject *ptr, bool is_borrowed)
+        : object(is_borrowed ? object(ptr, borrowed_t{}) : object(ptr, stolen_t{})) {}
 
-    explicit capsule(const void *value, const char *name = nullptr, void (*destructor)(PyObject *) = nullptr)
+    explicit capsule(const void *value,
+                     const char *name = nullptr,
+                     void (*destructor)(PyObject *) = nullptr)
         : object(PyCapsule_New(const_cast<void *>(value), name, destructor), stolen_t{}) {
-        if (!m_ptr)
-            pybind11_fail("Could not allocate capsule object!");
+        if (!m_ptr) {
+            throw error_already_set();
+        }
     }
 
     PYBIND11_DEPRECATED("Please pass a destructor that takes a void pointer as input")
     capsule(const void *value, void (*destruct)(PyObject *))
-        : object(PyCapsule_New(const_cast<void*>(value), nullptr, destruct), stolen_t{}) {
-        if (!m_ptr)
-            pybind11_fail("Could not allocate capsule object!");
+        : object(PyCapsule_New(const_cast<void *>(value), nullptr, destruct), stolen_t{}) {
+        if (!m_ptr) {
+            throw error_already_set();
+        }
     }
 
     capsule(const void *value, void (*destructor)(void *)) {
         m_ptr = PyCapsule_New(const_cast<void *>(value), nullptr, [](PyObject *o) {
+            // guard if destructor called while err indicator is set
+            error_scope error_guard;
             auto destructor = reinterpret_cast<void (*)(void *)>(PyCapsule_GetContext(o));
-            void *ptr = PyCapsule_GetPointer(o, nullptr);
+            if (destructor == nullptr) {
+                if (PyErr_Occurred()) {
+                    throw error_already_set();
+                }
+                pybind11_fail("Unable to get capsule context");
+            }
+            const char *name = get_name_in_error_scope(o);
+            void *ptr = PyCapsule_GetPointer(o, name);
+            if (ptr == nullptr) {
+                throw error_already_set();
+            }
             destructor(ptr);
         });
 
-        if (!m_ptr)
-            pybind11_fail("Could not allocate capsule object!");
-
-        if (PyCapsule_SetContext(m_ptr, (void *) destructor) != 0)
-            pybind11_fail("Could not set capsule context!");
+        if (!m_ptr || PyCapsule_SetContext(m_ptr, (void *) destructor) != 0) {
+            throw error_already_set();
+        }
     }
 
-    capsule(void (*destructor)()) {
+    explicit capsule(void (*destructor)()) {
         m_ptr = PyCapsule_New(reinterpret_cast<void *>(destructor), nullptr, [](PyObject *o) {
-            auto destructor = reinterpret_cast<void (*)()>(PyCapsule_GetPointer(o, nullptr));
+            const char *name = get_name_in_error_scope(o);
+            auto destructor = reinterpret_cast<void (*)()>(PyCapsule_GetPointer(o, name));
+            if (destructor == nullptr) {
+                throw error_already_set();
+            }
             destructor();
         });
 
-        if (!m_ptr)
-            pybind11_fail("Could not allocate capsule object!");
+        if (!m_ptr) {
+            throw error_already_set();
+        }
     }
 
-    template <typename T> operator T *() const {
+    template <typename T>
+    operator T *() const { // NOLINT(google-explicit-constructor)
         return get_pointer<T>();
     }
 
     /// Get the pointer the capsule holds.
-    template<typename T = void>
-    T* get_pointer() const {
-        auto name = this->name();
+    template <typename T = void>
+    T *get_pointer() const {
+        const auto *name = this->name();
         T *result = static_cast<T *>(PyCapsule_GetPointer(m_ptr, name));
-        if (!result) pybind11_fail("Unable to extract capsule contents!");
+        if (!result) {
+            throw error_already_set();
+        }
         return result;
     }
 
     /// Replaces a capsule's pointer *without* calling the destructor on the existing one.
     void set_pointer(const void *value) {
-        if (PyCapsule_SetPointer(m_ptr, const_cast<void *>(value)) != 0)
-            pybind11_fail("Could not set capsule pointer");
+        if (PyCapsule_SetPointer(m_ptr, const_cast<void *>(value)) != 0) {
+            throw error_already_set();
+        }
     }
 
-    const char *name() const { return PyCapsule_GetName(m_ptr); }
+    const char *name() const {
+        const char *name = PyCapsule_GetName(m_ptr);
+        if ((name == nullptr) && PyErr_Occurred()) {
+            throw error_already_set();
+        }
+        return name;
+    }
+
+    /// Replaces a capsule's name *without* calling the destructor on the existing one.
+    void set_name(const char *new_name) {
+        if (PyCapsule_SetName(m_ptr, new_name) != 0) {
+            throw error_already_set();
+        }
+    }
+
+private:
+    static const char *get_name_in_error_scope(PyObject *o) {
+        error_scope error_guard;
+
+        const char *name = PyCapsule_GetName(o);
+        if ((name == nullptr) && PyErr_Occurred()) {
+            // write out and consume error raised by call to PyCapsule_GetName
+            PyErr_WriteUnraisable(o);
+        }
+
+        return name;
+    }
 };
 
 class tuple : public object {
 public:
     PYBIND11_OBJECT_CVT(tuple, object, PyTuple_Check, PySequence_Tuple)
-    explicit tuple(size_t size = 0) : object(PyTuple_New((ssize_t) size), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate tuple object!");
+    template <typename SzType = ssize_t,
+              detail::enable_if_t<std::is_integral<SzType>::value, int> = 0>
+    // Some compilers generate link errors when using `const SzType &` here:
+    explicit tuple(SzType size = 0) : object(PyTuple_New(ssize_t_cast(size)), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate tuple object!");
+        }
     }
     size_t size() const { return (size_t) PyTuple_Size(m_ptr); }
     bool empty() const { return size() == 0; }
     detail::tuple_accessor operator[](size_t index) const { return {*this, index}; }
-    detail::item_accessor operator[](handle h) const { return object::operator[](h); }
+    template <typename T, detail::enable_if_t<detail::is_pyobject<T>::value, int> = 0>
+    detail::item_accessor operator[](T &&o) const {
+        return object::operator[](std::forward<T>(o));
+    }
     detail::tuple_iterator begin() const { return {*this, 0}; }
     detail::tuple_iterator end() const { return {*this, PyTuple_GET_SIZE(m_ptr)}; }
 };
 
+// We need to put this into a separate function because the Intel compiler
+// fails to compile enable_if_t<all_of<is_keyword_or_ds<Args>...>::value> part below
+// (tested with ICC 2021.1 Beta 20200827).
+template <typename... Args>
+constexpr bool args_are_all_keyword_or_ds() {
+    return detail::all_of<detail::is_keyword_or_ds<Args>...>::value;
+}
+
 class dict : public object {
 public:
     PYBIND11_OBJECT_CVT(dict, object, PyDict_Check, raw_dict)
     dict() : object(PyDict_New(), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate dict object!");
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate dict object!");
+        }
     }
     template <typename... Args,
-              typename = detail::enable_if_t<detail::all_of<detail::is_keyword_or_ds<Args>...>::value>,
-              // MSVC workaround: it can't compile an out-of-line definition, so defer the collector
+              typename = detail::enable_if_t<args_are_all_keyword_or_ds<Args...>()>,
+              // MSVC workaround: it can't compile an out-of-line definition, so defer the
+              // collector
               typename collector = detail::deferred_t<detail::unpacking_collector<>, Args...>>
-    explicit dict(Args &&...args) : dict(collector(std::forward<Args>(args)...).kwargs()) { }
+    explicit dict(Args &&...args) : dict(collector(std::forward<Args>(args)...).kwargs()) {}
 
     size_t size() const { return (size_t) PyDict_Size(m_ptr); }
     bool empty() const { return size() == 0; }
     detail::dict_iterator begin() const { return {*this, 0}; }
     detail::dict_iterator end() const { return {}; }
-    void clear() const { PyDict_Clear(ptr()); }
-    template <typename T> bool contains(T &&key) const {
+    void clear() /* py-non-const */ { PyDict_Clear(ptr()); }
+    template <typename T>
+    bool contains(T &&key) const {
         return PyDict_Contains(m_ptr, detail::object_or_cast(std::forward<T>(key)).ptr()) == 1;
     }
 
 private:
     /// Call the `dict` Python type -- always returns a new reference
     static PyObject *raw_dict(PyObject *op) {
-        if (PyDict_Check(op))
+        if (PyDict_Check(op)) {
             return handle(op).inc_ref().ptr();
+        }
         return PyObject_CallFunctionObjArgs((PyObject *) &PyDict_Type, op, nullptr);
     }
 };
@@ -1306,13 +1985,17 @@ class sequence : public object {
     PYBIND11_OBJECT_DEFAULT(sequence, object, PySequence_Check)
     size_t size() const {
         ssize_t result = PySequence_Size(m_ptr);
-        if (result == -1)
+        if (result == -1) {
             throw error_already_set();
+        }
         return (size_t) result;
     }
     bool empty() const { return size() == 0; }
     detail::sequence_accessor operator[](size_t index) const { return {*this, index}; }
-    detail::item_accessor operator[](handle h) const { return object::operator[](h); }
+    template <typename T, detail::enable_if_t<detail::is_pyobject<T>::value, int> = 0>
+    detail::item_accessor operator[](T &&o) const {
+        return object::operator[](std::forward<T>(o));
+    }
     detail::sequence_iterator begin() const { return {*this, 0}; }
     detail::sequence_iterator end() const { return {*this, PySequence_Size(m_ptr)}; }
 };
@@ -1320,51 +2003,82 @@ class sequence : public object {
 class list : public object {
 public:
     PYBIND11_OBJECT_CVT(list, object, PyList_Check, PySequence_List)
-    explicit list(size_t size = 0) : object(PyList_New((ssize_t) size), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate list object!");
+    template <typename SzType = ssize_t,
+              detail::enable_if_t<std::is_integral<SzType>::value, int> = 0>
+    // Some compilers generate link errors when using `const SzType &` here:
+    explicit list(SzType size = 0) : object(PyList_New(ssize_t_cast(size)), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate list object!");
+        }
     }
     size_t size() const { return (size_t) PyList_Size(m_ptr); }
     bool empty() const { return size() == 0; }
     detail::list_accessor operator[](size_t index) const { return {*this, index}; }
-    detail::item_accessor operator[](handle h) const { return object::operator[](h); }
+    template <typename T, detail::enable_if_t<detail::is_pyobject<T>::value, int> = 0>
+    detail::item_accessor operator[](T &&o) const {
+        return object::operator[](std::forward<T>(o));
+    }
     detail::list_iterator begin() const { return {*this, 0}; }
     detail::list_iterator end() const { return {*this, PyList_GET_SIZE(m_ptr)}; }
-    template <typename T> void append(T &&val) const {
+    template <typename T>
+    void append(T &&val) /* py-non-const */ {
         PyList_Append(m_ptr, detail::object_or_cast(std::forward<T>(val)).ptr());
     }
-    template <typename T> void insert(size_t index, T &&val) const {
-        PyList_Insert(m_ptr, static_cast<ssize_t>(index),
-            detail::object_or_cast(std::forward<T>(val)).ptr());
+    template <typename IdxType,
+              typename ValType,
+              detail::enable_if_t<std::is_integral<IdxType>::value, int> = 0>
+    void insert(const IdxType &index, ValType &&val) /* py-non-const */ {
+        PyList_Insert(
+            m_ptr, ssize_t_cast(index), detail::object_or_cast(std::forward<ValType>(val)).ptr());
     }
 };
 
-class args : public tuple { PYBIND11_OBJECT_DEFAULT(args, tuple, PyTuple_Check) };
-class kwargs : public dict { PYBIND11_OBJECT_DEFAULT(kwargs, dict, PyDict_Check)  };
+class args : public tuple {
+    PYBIND11_OBJECT_DEFAULT(args, tuple, PyTuple_Check)
+};
+class kwargs : public dict {
+    PYBIND11_OBJECT_DEFAULT(kwargs, dict, PyDict_Check)
+};
 
-class set : public object {
+class anyset : public object {
 public:
-    PYBIND11_OBJECT_CVT(set, object, PySet_Check, PySet_New)
-    set() : object(PySet_New(nullptr), stolen_t{}) {
-        if (!m_ptr) pybind11_fail("Could not allocate set object!");
-    }
-    size_t size() const { return (size_t) PySet_Size(m_ptr); }
+    PYBIND11_OBJECT(anyset, object, PyAnySet_Check)
+    size_t size() const { return static_cast<size_t>(PySet_Size(m_ptr)); }
     bool empty() const { return size() == 0; }
-    template <typename T> bool add(T &&val) const {
-        return PySet_Add(m_ptr, detail::object_or_cast(std::forward<T>(val)).ptr()) == 0;
-    }
-    void clear() const { PySet_Clear(m_ptr); }
-    template <typename T> bool contains(T &&val) const {
+    template <typename T>
+    bool contains(T &&val) const {
         return PySet_Contains(m_ptr, detail::object_or_cast(std::forward<T>(val)).ptr()) == 1;
     }
 };
 
+class set : public anyset {
+public:
+    PYBIND11_OBJECT_CVT(set, anyset, PySet_Check, PySet_New)
+    set() : anyset(PySet_New(nullptr), stolen_t{}) {
+        if (!m_ptr) {
+            pybind11_fail("Could not allocate set object!");
+        }
+    }
+    template <typename T>
+    bool add(T &&val) /* py-non-const */ {
+        return PySet_Add(m_ptr, detail::object_or_cast(std::forward<T>(val)).ptr()) == 0;
+    }
+    void clear() /* py-non-const */ { PySet_Clear(m_ptr); }
+};
+
+class frozenset : public anyset {
+public:
+    PYBIND11_OBJECT_CVT(frozenset, anyset, PyFrozenSet_Check, PyFrozenSet_New)
+};
+
 class function : public object {
 public:
     PYBIND11_OBJECT_DEFAULT(function, object, PyCallable_Check)
     handle cpp_function() const {
         handle fun = detail::get_function(m_ptr);
-        if (fun && PyCFunction_Check(fun.ptr()))
+        if (fun && PyCFunction_Check(fun.ptr())) {
             return fun;
+        }
         return handle();
     }
     bool is_cpp_function() const { return (bool) cpp_function(); }
@@ -1381,7 +2095,9 @@ class buffer : public object {
 
     buffer_info request(bool writable = false) const {
         int flags = PyBUF_STRIDES | PyBUF_FORMAT;
-        if (writable) flags |= PyBUF_WRITABLE;
+        if (writable) {
+            flags |= PyBUF_WRITABLE;
+        }
         auto *view = new Py_buffer();
         if (PyObject_GetBuffer(m_ptr, view, flags) != 0) {
             delete view;
@@ -1404,15 +2120,16 @@ class memoryview : public object {
         For creating a ``memoryview`` from objects that support buffer protocol,
         use ``memoryview(const object& obj)`` instead of this constructor.
      \endrst */
-    explicit memoryview(const buffer_info& info) {
-        if (!info.view())
+    explicit memoryview(const buffer_info &info) {
+        if (!info.view()) {
             pybind11_fail("Prohibited to create memoryview without Py_buffer");
+        }
         // Note: PyMemoryView_FromBuffer never increments obj reference.
-        m_ptr = (info.view()->obj) ?
-            PyMemoryView_FromObject(info.view()->obj) :
-            PyMemoryView_FromBuffer(info.view());
-        if (!m_ptr)
+        m_ptr = (info.view()->obj) ? PyMemoryView_FromObject(info.view()->obj)
+                                   : PyMemoryView_FromBuffer(info.view());
+        if (!m_ptr) {
             pybind11_fail("Unable to create memoryview from buffer descriptor");
+        }
     }
 
     /** \rst
@@ -1425,7 +2142,8 @@ class memoryview : public object {
 
         See also: Python C API documentation for `PyMemoryView_FromBuffer`_.
 
-        .. _PyMemoryView_FromBuffer: https://docs.python.org/c-api/memoryview.html#c.PyMemoryView_FromBuffer
+        .. _PyMemoryView_FromBuffer:
+           https://docs.python.org/c-api/memoryview.html#c.PyMemoryView_FromBuffer
 
         :param ptr: Pointer to the buffer.
         :param itemsize: Byte size of an element.
@@ -1438,37 +2156,43 @@ class memoryview : public object {
         :param readonly: Flag to indicate if the underlying storage may be
             written to.
      \endrst */
-    static memoryview from_buffer(
-        void *ptr, ssize_t itemsize, const char *format,
-        detail::any_container<ssize_t> shape,
-        detail::any_container<ssize_t> strides, bool readonly = false);
-
-    static memoryview from_buffer(
-        const void *ptr, ssize_t itemsize, const char *format,
-        detail::any_container<ssize_t> shape,
-        detail::any_container<ssize_t> strides) {
+    static memoryview from_buffer(void *ptr,
+                                  ssize_t itemsize,
+                                  const char *format,
+                                  detail::any_container<ssize_t> shape,
+                                  detail::any_container<ssize_t> strides,
+                                  bool readonly = false);
+
+    static memoryview from_buffer(const void *ptr,
+                                  ssize_t itemsize,
+                                  const char *format,
+                                  detail::any_container<ssize_t> shape,
+                                  detail::any_container<ssize_t> strides) {
         return memoryview::from_buffer(
-            const_cast<void*>(ptr), itemsize, format, shape, strides, true);
-    }
-
-    template<typename T>
-    static memoryview from_buffer(
-        T *ptr, detail::any_container<ssize_t> shape,
-        detail::any_container<ssize_t> strides, bool readonly = false) {
-        return memoryview::from_buffer(
-            reinterpret_cast<void*>(ptr), sizeof(T),
-            format_descriptor<T>::value, shape, strides, readonly);
-    }
-
-    template<typename T>
-    static memoryview from_buffer(
-        const T *ptr, detail::any_container<ssize_t> shape,
-        detail::any_container<ssize_t> strides) {
+            const_cast<void *>(ptr), itemsize, format, std::move(shape), std::move(strides), true);
+    }
+
+    template <typename T>
+    static memoryview from_buffer(T *ptr,
+                                  detail::any_container<ssize_t> shape,
+                                  detail::any_container<ssize_t> strides,
+                                  bool readonly = false) {
+        return memoryview::from_buffer(reinterpret_cast<void *>(ptr),
+                                       sizeof(T),
+                                       format_descriptor<T>::value,
+                                       std::move(shape),
+                                       std::move(strides),
+                                       readonly);
+    }
+
+    template <typename T>
+    static memoryview from_buffer(const T *ptr,
+                                  detail::any_container<ssize_t> shape,
+                                  detail::any_container<ssize_t> strides) {
         return memoryview::from_buffer(
-            const_cast<T*>(ptr), shape, strides, true);
+            const_cast<T *>(ptr), std::move(shape), std::move(strides), true);
     }
 
-#if PY_MAJOR_VERSION >= 3
     /** \rst
         Creates ``memoryview`` from static memory.
 
@@ -1476,56 +2200,65 @@ class memoryview : public object {
         managed by Python. The caller is responsible for managing the lifetime
         of ``mem``, which MUST outlive the memoryview constructed here.
 
-        This method is not available in Python 2.
-
         See also: Python C API documentation for `PyMemoryView_FromBuffer`_.
 
-        .. _PyMemoryView_FromMemory: https://docs.python.org/c-api/memoryview.html#c.PyMemoryView_FromMemory
+        .. _PyMemoryView_FromMemory:
+           https://docs.python.org/c-api/memoryview.html#c.PyMemoryView_FromMemory
      \endrst */
     static memoryview from_memory(void *mem, ssize_t size, bool readonly = false) {
-        PyObject* ptr = PyMemoryView_FromMemory(
-            reinterpret_cast<char*>(mem), size,
-            (readonly) ? PyBUF_READ : PyBUF_WRITE);
-        if (!ptr)
+        PyObject *ptr = PyMemoryView_FromMemory(
+            reinterpret_cast<char *>(mem), size, (readonly) ? PyBUF_READ : PyBUF_WRITE);
+        if (!ptr) {
             pybind11_fail("Could not allocate memoryview object!");
+        }
         return memoryview(object(ptr, stolen_t{}));
     }
 
     static memoryview from_memory(const void *mem, ssize_t size) {
-        return memoryview::from_memory(const_cast<void*>(mem), size, true);
+        return memoryview::from_memory(const_cast<void *>(mem), size, true);
+    }
+
+#ifdef PYBIND11_HAS_STRING_VIEW
+    static memoryview from_memory(std::string_view mem) {
+        return from_memory(const_cast<char *>(mem.data()), static_cast<ssize_t>(mem.size()), true);
     }
 #endif
 };
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-inline memoryview memoryview::from_buffer(
-    void *ptr, ssize_t itemsize, const char* format,
-    detail::any_container<ssize_t> shape,
-    detail::any_container<ssize_t> strides, bool readonly) {
+/// @cond DUPLICATE
+inline memoryview memoryview::from_buffer(void *ptr,
+                                          ssize_t itemsize,
+                                          const char *format,
+                                          detail::any_container<ssize_t> shape,
+                                          detail::any_container<ssize_t> strides,
+                                          bool readonly) {
     size_t ndim = shape->size();
-    if (ndim != strides->size())
+    if (ndim != strides->size()) {
         pybind11_fail("memoryview: shape length doesn't match strides length");
-    ssize_t size = ndim ? 1 : 0;
-    for (size_t i = 0; i < ndim; ++i)
+    }
+    ssize_t size = ndim != 0u ? 1 : 0;
+    for (size_t i = 0; i < ndim; ++i) {
         size *= (*shape)[i];
+    }
     Py_buffer view;
     view.buf = ptr;
     view.obj = nullptr;
     view.len = size * itemsize;
     view.readonly = static_cast<int>(readonly);
     view.itemsize = itemsize;
-    view.format = const_cast<char*>(format);
+    view.format = const_cast<char *>(format);
     view.ndim = static_cast<int>(ndim);
     view.shape = shape->data();
     view.strides = strides->data();
     view.suboffsets = nullptr;
     view.internal = nullptr;
-    PyObject* obj = PyMemoryView_FromBuffer(&view);
-    if (!obj)
+    PyObject *obj = PyMemoryView_FromBuffer(&view);
+    if (!obj) {
         throw error_already_set();
+    }
     return memoryview(object(obj, stolen_t{}));
 }
-#endif  // DOXYGEN_SHOULD_SKIP_THIS
+/// @endcond
 /// @} pytypes
 
 /// \addtogroup python_builtins
@@ -1534,19 +2267,16 @@ inline memoryview memoryview::from_buffer(
 /// Get the length of a Python object.
 inline size_t len(handle h) {
     ssize_t result = PyObject_Length(h.ptr());
-    if (result < 0)
+    if (result < 0) {
         throw error_already_set();
+    }
     return (size_t) result;
 }
 
 /// Get the length hint of a Python object.
 /// Returns 0 when this cannot be determined.
 inline size_t len_hint(handle h) {
-#if PY_VERSION_HEX >= 0x03040000
     ssize_t result = PyObject_LengthHint(h.ptr(), 0);
-#else
-    ssize_t result = PyObject_Length(h.ptr());
-#endif
     if (result < 0) {
         // Sometimes a length can't be determined at all (eg generators)
         // In which case simply return 0
@@ -1558,102 +2288,139 @@ inline size_t len_hint(handle h) {
 
 inline str repr(handle h) {
     PyObject *str_value = PyObject_Repr(h.ptr());
-    if (!str_value) throw error_already_set();
-#if PY_MAJOR_VERSION < 3
-    PyObject *unicode = PyUnicode_FromEncodedObject(str_value, "utf-8", nullptr);
-    Py_XDECREF(str_value); str_value = unicode;
-    if (!str_value) throw error_already_set();
-#endif
+    if (!str_value) {
+        throw error_already_set();
+    }
     return reinterpret_steal<str>(str_value);
 }
 
 inline iterator iter(handle obj) {
     PyObject *result = PyObject_GetIter(obj.ptr());
-    if (!result) { throw error_already_set(); }
+    if (!result) {
+        throw error_already_set();
+    }
     return reinterpret_steal<iterator>(result);
 }
 /// @} python_builtins
 
 PYBIND11_NAMESPACE_BEGIN(detail)
-template <typename D> iterator object_api<D>::begin() const { return iter(derived()); }
-template <typename D> iterator object_api<D>::end() const { return iterator::sentinel(); }
-template <typename D> item_accessor object_api<D>::operator[](handle key) const {
+template <typename D>
+iterator object_api<D>::begin() const {
+    return iter(derived());
+}
+template <typename D>
+iterator object_api<D>::end() const {
+    return iterator::sentinel();
+}
+template <typename D>
+item_accessor object_api<D>::operator[](handle key) const {
     return {derived(), reinterpret_borrow<object>(key)};
 }
-template <typename D> item_accessor object_api<D>::operator[](const char *key) const {
+template <typename D>
+item_accessor object_api<D>::operator[](object &&key) const {
+    return {derived(), std::move(key)};
+}
+template <typename D>
+item_accessor object_api<D>::operator[](const char *key) const {
     return {derived(), pybind11::str(key)};
 }
-template <typename D> obj_attr_accessor object_api<D>::attr(handle key) const {
+template <typename D>
+obj_attr_accessor object_api<D>::attr(handle key) const {
     return {derived(), reinterpret_borrow<object>(key)};
 }
-template <typename D> str_attr_accessor object_api<D>::attr(const char *key) const {
+template <typename D>
+obj_attr_accessor object_api<D>::attr(object &&key) const {
+    return {derived(), std::move(key)};
+}
+template <typename D>
+str_attr_accessor object_api<D>::attr(const char *key) const {
     return {derived(), key};
 }
-template <typename D> args_proxy object_api<D>::operator*() const {
+template <typename D>
+args_proxy object_api<D>::operator*() const {
     return args_proxy(derived().ptr());
 }
-template <typename D> template <typename T> bool object_api<D>::contains(T &&item) const {
+template <typename D>
+template <typename T>
+bool object_api<D>::contains(T &&item) const {
     return attr("__contains__")(std::forward<T>(item)).template cast<bool>();
 }
 
 template <typename D>
-pybind11::str object_api<D>::str() const { return pybind11::str(derived()); }
+pybind11::str object_api<D>::str() const {
+    return pybind11::str(derived());
+}
 
 template <typename D>
-str_attr_accessor object_api<D>::doc() const { return attr("__doc__"); }
+str_attr_accessor object_api<D>::doc() const {
+    return attr("__doc__");
+}
 
 template <typename D>
-handle object_api<D>::get_type() const { return type::handle_of(derived()); }
+handle object_api<D>::get_type() const {
+    return type::handle_of(derived());
+}
 
 template <typename D>
 bool object_api<D>::rich_compare(object_api const &other, int value) const {
     int rv = PyObject_RichCompareBool(derived().ptr(), other.derived().ptr(), value);
-    if (rv == -1)
+    if (rv == -1) {
         throw error_already_set();
+    }
     return rv == 1;
 }
 
-#define PYBIND11_MATH_OPERATOR_UNARY(op, fn)                                   \
-    template <typename D> object object_api<D>::op() const {                   \
-        object result = reinterpret_steal<object>(fn(derived().ptr()));        \
-        if (!result.ptr())                                                     \
-            throw error_already_set();                                         \
-        return result;                                                         \
-    }
-
-#define PYBIND11_MATH_OPERATOR_BINARY(op, fn)                                  \
-    template <typename D>                                                      \
-    object object_api<D>::op(object_api const &other) const {                  \
-        object result = reinterpret_steal<object>(                             \
-            fn(derived().ptr(), other.derived().ptr()));                       \
-        if (!result.ptr())                                                     \
-            throw error_already_set();                                         \
-        return result;                                                         \
-    }
-
-PYBIND11_MATH_OPERATOR_UNARY (operator~,   PyNumber_Invert)
-PYBIND11_MATH_OPERATOR_UNARY (operator-,   PyNumber_Negative)
-PYBIND11_MATH_OPERATOR_BINARY(operator+,   PyNumber_Add)
-PYBIND11_MATH_OPERATOR_BINARY(operator+=,  PyNumber_InPlaceAdd)
-PYBIND11_MATH_OPERATOR_BINARY(operator-,   PyNumber_Subtract)
-PYBIND11_MATH_OPERATOR_BINARY(operator-=,  PyNumber_InPlaceSubtract)
-PYBIND11_MATH_OPERATOR_BINARY(operator*,   PyNumber_Multiply)
-PYBIND11_MATH_OPERATOR_BINARY(operator*=,  PyNumber_InPlaceMultiply)
-PYBIND11_MATH_OPERATOR_BINARY(operator/,   PyNumber_TrueDivide)
-PYBIND11_MATH_OPERATOR_BINARY(operator/=,  PyNumber_InPlaceTrueDivide)
-PYBIND11_MATH_OPERATOR_BINARY(operator|,   PyNumber_Or)
-PYBIND11_MATH_OPERATOR_BINARY(operator|=,  PyNumber_InPlaceOr)
-PYBIND11_MATH_OPERATOR_BINARY(operator&,   PyNumber_And)
-PYBIND11_MATH_OPERATOR_BINARY(operator&=,  PyNumber_InPlaceAnd)
-PYBIND11_MATH_OPERATOR_BINARY(operator^,   PyNumber_Xor)
-PYBIND11_MATH_OPERATOR_BINARY(operator^=,  PyNumber_InPlaceXor)
-PYBIND11_MATH_OPERATOR_BINARY(operator<<,  PyNumber_Lshift)
-PYBIND11_MATH_OPERATOR_BINARY(operator<<=, PyNumber_InPlaceLshift)
-PYBIND11_MATH_OPERATOR_BINARY(operator>>,  PyNumber_Rshift)
-PYBIND11_MATH_OPERATOR_BINARY(operator>>=, PyNumber_InPlaceRshift)
+#define PYBIND11_MATH_OPERATOR_UNARY(op, fn)                                                      \
+    template <typename D>                                                                         \
+    object object_api<D>::op() const {                                                            \
+        object result = reinterpret_steal<object>(fn(derived().ptr()));                           \
+        if (!result.ptr())                                                                        \
+            throw error_already_set();                                                            \
+        return result;                                                                            \
+    }
+
+#define PYBIND11_MATH_OPERATOR_BINARY(op, fn)                                                     \
+    template <typename D>                                                                         \
+    object object_api<D>::op(object_api const &other) const {                                     \
+        object result = reinterpret_steal<object>(fn(derived().ptr(), other.derived().ptr()));    \
+        if (!result.ptr())                                                                        \
+            throw error_already_set();                                                            \
+        return result;                                                                            \
+    }
+
+#define PYBIND11_MATH_OPERATOR_BINARY_INPLACE(iop, fn)                                            \
+    template <typename D>                                                                         \
+    object object_api<D>::iop(object_api const &other) {                                          \
+        object result = reinterpret_steal<object>(fn(derived().ptr(), other.derived().ptr()));    \
+        if (!result.ptr())                                                                        \
+            throw error_already_set();                                                            \
+        return result;                                                                            \
+    }
+
+PYBIND11_MATH_OPERATOR_UNARY(operator~, PyNumber_Invert)
+PYBIND11_MATH_OPERATOR_UNARY(operator-, PyNumber_Negative)
+PYBIND11_MATH_OPERATOR_BINARY(operator+, PyNumber_Add)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator+=, PyNumber_InPlaceAdd)
+PYBIND11_MATH_OPERATOR_BINARY(operator-, PyNumber_Subtract)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator-=, PyNumber_InPlaceSubtract)
+PYBIND11_MATH_OPERATOR_BINARY(operator*, PyNumber_Multiply)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator*=, PyNumber_InPlaceMultiply)
+PYBIND11_MATH_OPERATOR_BINARY(operator/, PyNumber_TrueDivide)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator/=, PyNumber_InPlaceTrueDivide)
+PYBIND11_MATH_OPERATOR_BINARY(operator|, PyNumber_Or)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator|=, PyNumber_InPlaceOr)
+PYBIND11_MATH_OPERATOR_BINARY(operator&, PyNumber_And)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator&=, PyNumber_InPlaceAnd)
+PYBIND11_MATH_OPERATOR_BINARY(operator^, PyNumber_Xor)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator^=, PyNumber_InPlaceXor)
+PYBIND11_MATH_OPERATOR_BINARY(operator<<, PyNumber_Lshift)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator<<=, PyNumber_InPlaceLshift)
+PYBIND11_MATH_OPERATOR_BINARY(operator>>, PyNumber_Rshift)
+PYBIND11_MATH_OPERATOR_BINARY_INPLACE(operator>>=, PyNumber_InPlaceRshift)
 
 #undef PYBIND11_MATH_OPERATOR_UNARY
 #undef PYBIND11_MATH_OPERATOR_BINARY
+#undef PYBIND11_MATH_OPERATOR_BINARY_INPLACE
 
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/stl.h b/3rdparty/pybind11/include/pybind11/stl.h
index 721bb669f0..48031c2a60 100644
--- a/3rdparty/pybind11/include/pybind11/stl.h
+++ b/3rdparty/pybind11/include/pybind11/stl.h
@@ -10,42 +10,26 @@
 #pragma once
 
 #include "pybind11.h"
-#include <set>
-#include <unordered_set>
+#include "detail/common.h"
+
+#include <deque>
+#include <list>
 #include <map>
+#include <ostream>
+#include <set>
 #include <unordered_map>
-#include <iostream>
-#include <list>
-#include <deque>
+#include <unordered_set>
 #include <valarray>
 
-#if defined(_MSC_VER)
-#pragma warning(push)
-#pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#endif
-
-#ifdef __has_include
-// std::optional (but including it in c++14 mode isn't allowed)
-#  if defined(PYBIND11_CPP17) && __has_include(<optional>)
+// See `detail/common.h` for implementation of these guards.
+#if defined(PYBIND11_HAS_OPTIONAL)
 #    include <optional>
-#    define PYBIND11_HAS_OPTIONAL 1
-#  endif
-// std::experimental::optional (but not allowed in c++11 mode)
-#  if defined(PYBIND11_CPP14) && (__has_include(<experimental/optional>) && \
-                                 !__has_include(<optional>))
+#elif defined(PYBIND11_HAS_EXP_OPTIONAL)
 #    include <experimental/optional>
-#    define PYBIND11_HAS_EXP_OPTIONAL 1
-#  endif
-// std::variant
-#  if defined(PYBIND11_CPP17) && __has_include(<variant>)
+#endif
+
+#if defined(PYBIND11_HAS_VARIANT)
 #    include <variant>
-#    define PYBIND11_HAS_VARIANT 1
-#  endif
-#elif defined(_MSC_VER) && defined(PYBIND11_CPP17)
-#  include <optional>
-#  include <variant>
-#  define PYBIND11_HAS_OPTIONAL 1
-#  define PYBIND11_HAS_VARIANT 1
 #endif
 
 PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
@@ -54,29 +38,33 @@ PYBIND11_NAMESPACE_BEGIN(detail)
 /// Extracts an const lvalue reference or rvalue reference for U based on the type of T (e.g. for
 /// forwarding a container element).  Typically used indirect via forwarded_type(), below.
 template <typename T, typename U>
-using forwarded_type = conditional_t<
-    std::is_lvalue_reference<T>::value, remove_reference_t<U> &, remove_reference_t<U> &&>;
+using forwarded_type = conditional_t<std::is_lvalue_reference<T>::value,
+                                     remove_reference_t<U> &,
+                                     remove_reference_t<U> &&>;
 
 /// Forwards a value U as rvalue or lvalue according to whether T is rvalue or lvalue; typically
 /// used for forwarding a container's elements.
 template <typename T, typename U>
-forwarded_type<T, U> forward_like(U &&u) {
+constexpr forwarded_type<T, U> forward_like(U &&u) {
     return std::forward<detail::forwarded_type<T, U>>(std::forward<U>(u));
 }
 
-template <typename Type, typename Key> struct set_caster {
+template <typename Type, typename Key>
+struct set_caster {
     using type = Type;
     using key_conv = make_caster<Key>;
 
     bool load(handle src, bool convert) {
-        if (!isinstance<pybind11::set>(src))
+        if (!isinstance<anyset>(src)) {
             return false;
-        auto s = reinterpret_borrow<pybind11::set>(src);
+        }
+        auto s = reinterpret_borrow<anyset>(src);
         value.clear();
         for (auto entry : s) {
             key_conv conv;
-            if (!conv.load(entry, convert))
+            if (!conv.load(entry, convert)) {
                 return false;
+            }
             value.insert(cast_op<Key &&>(std::move(conv)));
         }
         return true;
@@ -84,35 +72,40 @@ template <typename Type, typename Key> struct set_caster {
 
     template <typename T>
     static handle cast(T &&src, return_value_policy policy, handle parent) {
-        if (!std::is_lvalue_reference<T>::value)
+        if (!std::is_lvalue_reference<T>::value) {
             policy = return_value_policy_override<Key>::policy(policy);
+        }
         pybind11::set s;
         for (auto &&value : src) {
-            auto value_ = reinterpret_steal<object>(key_conv::cast(forward_like<T>(value), policy, parent));
-            if (!value_ || !s.add(value_))
+            auto value_ = reinterpret_steal<object>(
+                key_conv::cast(detail::forward_like<T>(value), policy, parent));
+            if (!value_ || !s.add(std::move(value_))) {
                 return handle();
+            }
         }
         return s.release();
     }
 
-    PYBIND11_TYPE_CASTER(type, _("Set[") + key_conv::name + _("]"));
+    PYBIND11_TYPE_CASTER(type, const_name("Set[") + key_conv::name + const_name("]"));
 };
 
-template <typename Type, typename Key, typename Value> struct map_caster {
-    using key_conv   = make_caster<Key>;
+template <typename Type, typename Key, typename Value>
+struct map_caster {
+    using key_conv = make_caster<Key>;
     using value_conv = make_caster<Value>;
 
     bool load(handle src, bool convert) {
-        if (!isinstance<dict>(src))
+        if (!isinstance<dict>(src)) {
             return false;
+        }
         auto d = reinterpret_borrow<dict>(src);
         value.clear();
         for (auto it : d) {
             key_conv kconv;
             value_conv vconv;
-            if (!kconv.load(it.first.ptr(), convert) ||
-                !vconv.load(it.second.ptr(), convert))
+            if (!kconv.load(it.first.ptr(), convert) || !vconv.load(it.second.ptr(), convert)) {
                 return false;
+            }
             value.emplace(cast_op<Key &&>(std::move(kconv)), cast_op<Value &&>(std::move(vconv)));
         }
         return true;
@@ -128,78 +121,94 @@ template <typename Type, typename Key, typename Value> struct map_caster {
             policy_value = return_value_policy_override<Value>::policy(policy_value);
         }
         for (auto &&kv : src) {
-            auto key = reinterpret_steal<object>(key_conv::cast(forward_like<T>(kv.first), policy_key, parent));
-            auto value = reinterpret_steal<object>(value_conv::cast(forward_like<T>(kv.second), policy_value, parent));
-            if (!key || !value)
+            auto key = reinterpret_steal<object>(
+                key_conv::cast(detail::forward_like<T>(kv.first), policy_key, parent));
+            auto value = reinterpret_steal<object>(
+                value_conv::cast(detail::forward_like<T>(kv.second), policy_value, parent));
+            if (!key || !value) {
                 return handle();
-            d[key] = value;
+            }
+            d[std::move(key)] = std::move(value);
         }
         return d.release();
     }
 
-    PYBIND11_TYPE_CASTER(Type, _("Dict[") + key_conv::name + _(", ") + value_conv::name + _("]"));
+    PYBIND11_TYPE_CASTER(Type,
+                         const_name("Dict[") + key_conv::name + const_name(", ") + value_conv::name
+                             + const_name("]"));
 };
 
-template <typename Type, typename Value> struct list_caster {
+template <typename Type, typename Value>
+struct list_caster {
     using value_conv = make_caster<Value>;
 
     bool load(handle src, bool convert) {
-        if (!isinstance<sequence>(src) || isinstance<str>(src))
+        if (!isinstance<sequence>(src) || isinstance<bytes>(src) || isinstance<str>(src)) {
             return false;
+        }
         auto s = reinterpret_borrow<sequence>(src);
         value.clear();
         reserve_maybe(s, &value);
         for (auto it : s) {
             value_conv conv;
-            if (!conv.load(it, convert))
+            if (!conv.load(it, convert)) {
                 return false;
+            }
             value.push_back(cast_op<Value &&>(std::move(conv)));
         }
         return true;
     }
 
 private:
-    template <typename T = Type,
-              enable_if_t<std::is_same<decltype(std::declval<T>().reserve(0)), void>::value, int> = 0>
-    void reserve_maybe(sequence s, Type *) { value.reserve(s.size()); }
-    void reserve_maybe(sequence, void *) { }
+    template <
+        typename T = Type,
+        enable_if_t<std::is_same<decltype(std::declval<T>().reserve(0)), void>::value, int> = 0>
+    void reserve_maybe(const sequence &s, Type *) {
+        value.reserve(s.size());
+    }
+    void reserve_maybe(const sequence &, void *) {}
 
 public:
     template <typename T>
     static handle cast(T &&src, return_value_policy policy, handle parent) {
-        if (!std::is_lvalue_reference<T>::value)
+        if (!std::is_lvalue_reference<T>::value) {
             policy = return_value_policy_override<Value>::policy(policy);
+        }
         list l(src.size());
-        size_t index = 0;
+        ssize_t index = 0;
         for (auto &&value : src) {
-            auto value_ = reinterpret_steal<object>(value_conv::cast(forward_like<T>(value), policy, parent));
-            if (!value_)
+            auto value_ = reinterpret_steal<object>(
+                value_conv::cast(detail::forward_like<T>(value), policy, parent));
+            if (!value_) {
                 return handle();
-            PyList_SET_ITEM(l.ptr(), (ssize_t) index++, value_.release().ptr()); // steals a reference
+            }
+            PyList_SET_ITEM(l.ptr(), index++, value_.release().ptr()); // steals a reference
         }
         return l.release();
     }
 
-    PYBIND11_TYPE_CASTER(Type, _("List[") + value_conv::name + _("]"));
+    PYBIND11_TYPE_CASTER(Type, const_name("List[") + value_conv::name + const_name("]"));
 };
 
-template <typename Type, typename Alloc> struct type_caster<std::vector<Type, Alloc>>
- : list_caster<std::vector<Type, Alloc>, Type> { };
+template <typename Type, typename Alloc>
+struct type_caster<std::vector<Type, Alloc>> : list_caster<std::vector<Type, Alloc>, Type> {};
 
-template <typename Type, typename Alloc> struct type_caster<std::deque<Type, Alloc>>
- : list_caster<std::deque<Type, Alloc>, Type> { };
+template <typename Type, typename Alloc>
+struct type_caster<std::deque<Type, Alloc>> : list_caster<std::deque<Type, Alloc>, Type> {};
 
-template <typename Type, typename Alloc> struct type_caster<std::list<Type, Alloc>>
- : list_caster<std::list<Type, Alloc>, Type> { };
+template <typename Type, typename Alloc>
+struct type_caster<std::list<Type, Alloc>> : list_caster<std::list<Type, Alloc>, Type> {};
 
-template <typename ArrayType, typename Value, bool Resizable, size_t Size = 0> struct array_caster {
+template <typename ArrayType, typename Value, bool Resizable, size_t Size = 0>
+struct array_caster {
     using value_conv = make_caster<Value>;
 
 private:
     template <bool R = Resizable>
     bool require_size(enable_if_t<R, size_t> size) {
-        if (value.size() != size)
+        if (value.size() != size) {
             value.resize(size);
+        }
         return true;
     }
     template <bool R = Resizable>
@@ -209,16 +218,19 @@ template <typename ArrayType, typename Value, bool Resizable, size_t Size = 0> s
 
 public:
     bool load(handle src, bool convert) {
-        if (!isinstance<sequence>(src))
+        if (!isinstance<sequence>(src)) {
             return false;
+        }
         auto l = reinterpret_borrow<sequence>(src);
-        if (!require_size(l.size()))
+        if (!require_size(l.size())) {
             return false;
+        }
         size_t ctr = 0;
         for (auto it : l) {
             value_conv conv;
-            if (!conv.load(it, convert))
+            if (!conv.load(it, convert)) {
                 return false;
+            }
             value[ctr++] = cast_op<Value &&>(std::move(conv));
         }
         return true;
@@ -227,81 +239,99 @@ template <typename ArrayType, typename Value, bool Resizable, size_t Size = 0> s
     template <typename T>
     static handle cast(T &&src, return_value_policy policy, handle parent) {
         list l(src.size());
-        size_t index = 0;
+        ssize_t index = 0;
         for (auto &&value : src) {
-            auto value_ = reinterpret_steal<object>(value_conv::cast(forward_like<T>(value), policy, parent));
-            if (!value_)
+            auto value_ = reinterpret_steal<object>(
+                value_conv::cast(detail::forward_like<T>(value), policy, parent));
+            if (!value_) {
                 return handle();
-            PyList_SET_ITEM(l.ptr(), (ssize_t) index++, value_.release().ptr()); // steals a reference
+            }
+            PyList_SET_ITEM(l.ptr(), index++, value_.release().ptr()); // steals a reference
         }
         return l.release();
     }
 
-    PYBIND11_TYPE_CASTER(ArrayType, _("List[") + value_conv::name + _<Resizable>(_(""), _("[") + _<Size>() + _("]")) + _("]"));
+    PYBIND11_TYPE_CASTER(ArrayType,
+                         const_name("List[") + value_conv::name
+                             + const_name<Resizable>(const_name(""),
+                                                     const_name("[") + const_name<Size>()
+                                                         + const_name("]"))
+                             + const_name("]"));
 };
 
-template <typename Type, size_t Size> struct type_caster<std::array<Type, Size>>
- : array_caster<std::array<Type, Size>, Type, false, Size> { };
+template <typename Type, size_t Size>
+struct type_caster<std::array<Type, Size>>
+    : array_caster<std::array<Type, Size>, Type, false, Size> {};
 
-template <typename Type> struct type_caster<std::valarray<Type>>
- : array_caster<std::valarray<Type>, Type, true> { };
+template <typename Type>
+struct type_caster<std::valarray<Type>> : array_caster<std::valarray<Type>, Type, true> {};
 
-template <typename Key, typename Compare, typename Alloc> struct type_caster<std::set<Key, Compare, Alloc>>
-  : set_caster<std::set<Key, Compare, Alloc>, Key> { };
+template <typename Key, typename Compare, typename Alloc>
+struct type_caster<std::set<Key, Compare, Alloc>>
+    : set_caster<std::set<Key, Compare, Alloc>, Key> {};
 
-template <typename Key, typename Hash, typename Equal, typename Alloc> struct type_caster<std::unordered_set<Key, Hash, Equal, Alloc>>
-  : set_caster<std::unordered_set<Key, Hash, Equal, Alloc>, Key> { };
+template <typename Key, typename Hash, typename Equal, typename Alloc>
+struct type_caster<std::unordered_set<Key, Hash, Equal, Alloc>>
+    : set_caster<std::unordered_set<Key, Hash, Equal, Alloc>, Key> {};
 
-template <typename Key, typename Value, typename Compare, typename Alloc> struct type_caster<std::map<Key, Value, Compare, Alloc>>
-  : map_caster<std::map<Key, Value, Compare, Alloc>, Key, Value> { };
+template <typename Key, typename Value, typename Compare, typename Alloc>
+struct type_caster<std::map<Key, Value, Compare, Alloc>>
+    : map_caster<std::map<Key, Value, Compare, Alloc>, Key, Value> {};
 
-template <typename Key, typename Value, typename Hash, typename Equal, typename Alloc> struct type_caster<std::unordered_map<Key, Value, Hash, Equal, Alloc>>
-  : map_caster<std::unordered_map<Key, Value, Hash, Equal, Alloc>, Key, Value> { };
+template <typename Key, typename Value, typename Hash, typename Equal, typename Alloc>
+struct type_caster<std::unordered_map<Key, Value, Hash, Equal, Alloc>>
+    : map_caster<std::unordered_map<Key, Value, Hash, Equal, Alloc>, Key, Value> {};
 
 // This type caster is intended to be used for std::optional and std::experimental::optional
-template<typename T> struct optional_caster {
-    using value_conv = make_caster<typename T::value_type>;
+template <typename Type, typename Value = typename Type::value_type>
+struct optional_caster {
+    using value_conv = make_caster<Value>;
 
-    template <typename T_>
-    static handle cast(T_ &&src, return_value_policy policy, handle parent) {
-        if (!src)
+    template <typename T>
+    static handle cast(T &&src, return_value_policy policy, handle parent) {
+        if (!src) {
             return none().inc_ref();
+        }
         if (!std::is_lvalue_reference<T>::value) {
-            policy = return_value_policy_override<T>::policy(policy);
+            policy = return_value_policy_override<Value>::policy(policy);
         }
-        return value_conv::cast(*std::forward<T_>(src), policy, parent);
+        return value_conv::cast(*std::forward<T>(src), policy, parent);
     }
 
     bool load(handle src, bool convert) {
         if (!src) {
             return false;
-        } else if (src.is_none()) {
-            return true;  // default-constructed value is already empty
+        }
+        if (src.is_none()) {
+            return true; // default-constructed value is already empty
         }
         value_conv inner_caster;
-        if (!inner_caster.load(src, convert))
+        if (!inner_caster.load(src, convert)) {
             return false;
+        }
 
-        value.emplace(cast_op<typename T::value_type &&>(std::move(inner_caster)));
+        value.emplace(cast_op<Value &&>(std::move(inner_caster)));
         return true;
     }
 
-    PYBIND11_TYPE_CASTER(T, _("Optional[") + value_conv::name + _("]"));
+    PYBIND11_TYPE_CASTER(Type, const_name("Optional[") + value_conv::name + const_name("]"));
 };
 
 #if defined(PYBIND11_HAS_OPTIONAL)
-template<typename T> struct type_caster<std::optional<T>>
-    : public optional_caster<std::optional<T>> {};
+template <typename T>
+struct type_caster<std::optional<T>> : public optional_caster<std::optional<T>> {};
 
-template<> struct type_caster<std::nullopt_t>
-    : public void_caster<std::nullopt_t> {};
+template <>
+struct type_caster<std::nullopt_t> : public void_caster<std::nullopt_t> {};
 #endif
 
 #if defined(PYBIND11_HAS_EXP_OPTIONAL)
-template<typename T> struct type_caster<std::experimental::optional<T>>
+template <typename T>
+struct type_caster<std::experimental::optional<T>>
     : public optional_caster<std::experimental::optional<T>> {};
 
-template<> struct type_caster<std::experimental::nullopt_t>
+template <>
+struct type_caster<std::experimental::nullopt_t>
     : public void_caster<std::experimental::nullopt_t> {};
 #endif
 
@@ -322,7 +352,7 @@ struct variant_caster_visitor {
 /// `namespace::variant` types which provide a `namespace::visit()` function are handled here
 /// automatically using argument-dependent lookup. Users can provide specializations for other
 /// variant-like classes, e.g. `boost::variant` and `boost::apply_visitor`.
-template <template<typename...> class Variant>
+template <template <typename...> class Variant>
 struct visit_helper {
     template <typename... Args>
     static auto call(Args &&...args) -> decltype(visit(std::forward<Args>(args)...)) {
@@ -331,9 +361,10 @@ struct visit_helper {
 };
 
 /// Generic variant caster
-template <typename Variant> struct variant_caster;
+template <typename Variant>
+struct variant_caster;
 
-template <template<typename...> class V, typename... Ts>
+template <template <typename...> class V, typename... Ts>
 struct variant_caster<V<Ts...>> {
     static_assert(sizeof...(Ts) > 0, "Variant must consist of at least one alternative.");
 
@@ -341,7 +372,7 @@ struct variant_caster<V<Ts...>> {
     bool load_alternative(handle src, bool convert, type_list<U, Us...>) {
         auto caster = make_caster<U>();
         if (caster.load(src, convert)) {
-            value = cast_op<U>(caster);
+            value = cast_op<U>(std::move(caster));
             return true;
         }
         return load_alternative(src, convert, type_list<Us...>{});
@@ -354,8 +385,9 @@ struct variant_caster<V<Ts...>> {
         // E.g. `py::int_(1).cast<variant<double, int>>()` needs to fill the `int`
         // slot of the variant. Without two-pass loading `double` would be filled
         // because it appears first and a conversion is possible.
-        if (convert && load_alternative(src, false, type_list<Ts...>{}))
+        if (convert && load_alternative(src, false, type_list<Ts...>{})) {
             return true;
+        }
         return load_alternative(src, convert, type_list<Ts...>{});
     }
 
@@ -366,23 +398,28 @@ struct variant_caster<V<Ts...>> {
     }
 
     using Type = V<Ts...>;
-    PYBIND11_TYPE_CASTER(Type, _("Union[") + detail::concat(make_caster<Ts>::name...) + _("]"));
+    PYBIND11_TYPE_CASTER(Type,
+                         const_name("Union[") + detail::concat(make_caster<Ts>::name...)
+                             + const_name("]"));
 };
 
 #if defined(PYBIND11_HAS_VARIANT)
 template <typename... Ts>
-struct type_caster<std::variant<Ts...>> : variant_caster<std::variant<Ts...>> { };
+struct type_caster<std::variant<Ts...>> : variant_caster<std::variant<Ts...>> {};
+
+template <>
+struct type_caster<std::monostate> : public void_caster<std::monostate> {};
 #endif
 
 PYBIND11_NAMESPACE_END(detail)
 
 inline std::ostream &operator<<(std::ostream &os, const handle &obj) {
+#ifdef PYBIND11_HAS_STRING_VIEW
+    os << str(obj).cast<std::string_view>();
+#else
     os << (std::string) str(obj);
+#endif
     return os;
 }
 
 PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
-
-#if defined(_MSC_VER)
-#pragma warning(pop)
-#endif
diff --git a/3rdparty/pybind11/include/pybind11/stl/filesystem.h b/3rdparty/pybind11/include/pybind11/stl/filesystem.h
new file mode 100644
index 0000000000..e26f421776
--- /dev/null
+++ b/3rdparty/pybind11/include/pybind11/stl/filesystem.h
@@ -0,0 +1,116 @@
+// Copyright (c) 2021 The Pybind Development Team.
+// All rights reserved. Use of this source code is governed by a
+// BSD-style license that can be found in the LICENSE file.
+
+#pragma once
+
+#include "../pybind11.h"
+#include "../detail/common.h"
+#include "../detail/descr.h"
+#include "../cast.h"
+#include "../pytypes.h"
+
+#include <string>
+
+#ifdef __has_include
+#    if defined(PYBIND11_CPP17)
+#        if __has_include(<filesystem>) && \
+          PY_VERSION_HEX >= 0x03060000
+#            include <filesystem>
+#            define PYBIND11_HAS_FILESYSTEM 1
+#        elif __has_include(<experimental/filesystem>)
+#            include <experimental/filesystem>
+#            define PYBIND11_HAS_EXPERIMENTAL_FILESYSTEM 1
+#        endif
+#    endif
+#endif
+
+#if !defined(PYBIND11_HAS_FILESYSTEM) && !defined(PYBIND11_HAS_EXPERIMENTAL_FILESYSTEM)           \
+    && !defined(PYBIND11_HAS_FILESYSTEM_IS_OPTIONAL)
+#    error                                                                                        \
+        "Neither #include <filesystem> nor #include <experimental/filesystem is available. (Use -DPYBIND11_HAS_FILESYSTEM_IS_OPTIONAL to ignore.)"
+#endif
+
+PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
+PYBIND11_NAMESPACE_BEGIN(detail)
+
+#if defined(PYBIND11_HAS_FILESYSTEM) || defined(PYBIND11_HAS_EXPERIMENTAL_FILESYSTEM)
+template <typename T>
+struct path_caster {
+
+private:
+    static PyObject *unicode_from_fs_native(const std::string &w) {
+#    if !defined(PYPY_VERSION)
+        return PyUnicode_DecodeFSDefaultAndSize(w.c_str(), ssize_t(w.size()));
+#    else
+        // PyPy mistakenly declares the first parameter as non-const.
+        return PyUnicode_DecodeFSDefaultAndSize(const_cast<char *>(w.c_str()), ssize_t(w.size()));
+#    endif
+    }
+
+    static PyObject *unicode_from_fs_native(const std::wstring &w) {
+        return PyUnicode_FromWideChar(w.c_str(), ssize_t(w.size()));
+    }
+
+public:
+    static handle cast(const T &path, return_value_policy, handle) {
+        if (auto py_str = unicode_from_fs_native(path.native())) {
+            return module_::import("pathlib")
+                .attr("Path")(reinterpret_steal<object>(py_str))
+                .release();
+        }
+        return nullptr;
+    }
+
+    bool load(handle handle, bool) {
+        // PyUnicode_FSConverter and PyUnicode_FSDecoder normally take care of
+        // calling PyOS_FSPath themselves, but that's broken on PyPy (PyPy
+        // issue #3168) so we do it ourselves instead.
+        PyObject *buf = PyOS_FSPath(handle.ptr());
+        if (!buf) {
+            PyErr_Clear();
+            return false;
+        }
+        PyObject *native = nullptr;
+        if constexpr (std::is_same_v<typename T::value_type, char>) {
+            if (PyUnicode_FSConverter(buf, &native) != 0) {
+                if (auto *c_str = PyBytes_AsString(native)) {
+                    // AsString returns a pointer to the internal buffer, which
+                    // must not be free'd.
+                    value = c_str;
+                }
+            }
+        } else if constexpr (std::is_same_v<typename T::value_type, wchar_t>) {
+            if (PyUnicode_FSDecoder(buf, &native) != 0) {
+                if (auto *c_str = PyUnicode_AsWideCharString(native, nullptr)) {
+                    // AsWideCharString returns a new string that must be free'd.
+                    value = c_str; // Copies the string.
+                    PyMem_Free(c_str);
+                }
+            }
+        }
+        Py_XDECREF(native);
+        Py_DECREF(buf);
+        if (PyErr_Occurred()) {
+            PyErr_Clear();
+            return false;
+        }
+        return true;
+    }
+
+    PYBIND11_TYPE_CASTER(T, const_name("os.PathLike"));
+};
+
+#endif // PYBIND11_HAS_FILESYSTEM || defined(PYBIND11_HAS_EXPERIMENTAL_FILESYSTEM)
+
+#if defined(PYBIND11_HAS_FILESYSTEM)
+template <>
+struct type_caster<std::filesystem::path> : public path_caster<std::filesystem::path> {};
+#elif defined(PYBIND11_HAS_EXPERIMENTAL_FILESYSTEM)
+template <>
+struct type_caster<std::experimental::filesystem::path>
+    : public path_caster<std::experimental::filesystem::path> {};
+#endif
+
+PYBIND11_NAMESPACE_END(detail)
+PYBIND11_NAMESPACE_END(PYBIND11_NAMESPACE)
diff --git a/3rdparty/pybind11/include/pybind11/stl_bind.h b/3rdparty/pybind11/include/pybind11/stl_bind.h
index 9d8ed0c825..22a29b476f 100644
--- a/3rdparty/pybind11/include/pybind11/stl_bind.h
+++ b/3rdparty/pybind11/include/pybind11/stl_bind.h
@@ -19,254 +19,274 @@ PYBIND11_NAMESPACE_BEGIN(PYBIND11_NAMESPACE)
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 /* SFINAE helper class used by 'is_comparable */
-template <typename T>  struct container_traits {
-    template <typename T2> static std::true_type test_comparable(decltype(std::declval<const T2 &>() == std::declval<const T2 &>())*);
-    template <typename T2> static std::false_type test_comparable(...);
-    template <typename T2> static std::true_type test_value(typename T2::value_type *);
-    template <typename T2> static std::false_type test_value(...);
-    template <typename T2> static std::true_type test_pair(typename T2::first_type *, typename T2::second_type *);
-    template <typename T2> static std::false_type test_pair(...);
-
-    static constexpr const bool is_comparable = std::is_same<std::true_type, decltype(test_comparable<T>(nullptr))>::value;
-    static constexpr const bool is_pair = std::is_same<std::true_type, decltype(test_pair<T>(nullptr, nullptr))>::value;
-    static constexpr const bool is_vector = std::is_same<std::true_type, decltype(test_value<T>(nullptr))>::value;
+template <typename T>
+struct container_traits {
+    template <typename T2>
+    static std::true_type
+    test_comparable(decltype(std::declval<const T2 &>() == std::declval<const T2 &>()) *);
+    template <typename T2>
+    static std::false_type test_comparable(...);
+    template <typename T2>
+    static std::true_type test_value(typename T2::value_type *);
+    template <typename T2>
+    static std::false_type test_value(...);
+    template <typename T2>
+    static std::true_type test_pair(typename T2::first_type *, typename T2::second_type *);
+    template <typename T2>
+    static std::false_type test_pair(...);
+
+    static constexpr const bool is_comparable
+        = std::is_same<std::true_type, decltype(test_comparable<T>(nullptr))>::value;
+    static constexpr const bool is_pair
+        = std::is_same<std::true_type, decltype(test_pair<T>(nullptr, nullptr))>::value;
+    static constexpr const bool is_vector
+        = std::is_same<std::true_type, decltype(test_value<T>(nullptr))>::value;
     static constexpr const bool is_element = !is_pair && !is_vector;
 };
 
 /* Default: is_comparable -> std::false_type */
 template <typename T, typename SFINAE = void>
-struct is_comparable : std::false_type { };
+struct is_comparable : std::false_type {};
 
 /* For non-map data structures, check whether operator== can be instantiated */
 template <typename T>
 struct is_comparable<
-    T, enable_if_t<container_traits<T>::is_element &&
-                   container_traits<T>::is_comparable>>
-    : std::true_type { };
+    T,
+    enable_if_t<container_traits<T>::is_element && container_traits<T>::is_comparable>>
+    : std::true_type {};
 
-/* For a vector/map data structure, recursively check the value type (which is std::pair for maps) */
+/* For a vector/map data structure, recursively check the value type
+   (which is std::pair for maps) */
 template <typename T>
 struct is_comparable<T, enable_if_t<container_traits<T>::is_vector>> {
-    static constexpr const bool value =
-        is_comparable<typename T::value_type>::value;
+    static constexpr const bool value = is_comparable<typename T::value_type>::value;
 };
 
 /* For pairs, recursively check the two data types */
 template <typename T>
 struct is_comparable<T, enable_if_t<container_traits<T>::is_pair>> {
-    static constexpr const bool value =
-        is_comparable<typename T::first_type>::value &&
-        is_comparable<typename T::second_type>::value;
+    static constexpr const bool value = is_comparable<typename T::first_type>::value
+                                        && is_comparable<typename T::second_type>::value;
 };
 
 /* Fallback functions */
-template <typename, typename, typename... Args> void vector_if_copy_constructible(const Args &...) { }
-template <typename, typename, typename... Args> void vector_if_equal_operator(const Args &...) { }
-template <typename, typename, typename... Args> void vector_if_insertion_operator(const Args &...) { }
-template <typename, typename, typename... Args> void vector_modifiers(const Args &...) { }
+template <typename, typename, typename... Args>
+void vector_if_copy_constructible(const Args &...) {}
+template <typename, typename, typename... Args>
+void vector_if_equal_operator(const Args &...) {}
+template <typename, typename, typename... Args>
+void vector_if_insertion_operator(const Args &...) {}
+template <typename, typename, typename... Args>
+void vector_modifiers(const Args &...) {}
 
-template<typename Vector, typename Class_>
+template <typename Vector, typename Class_>
 void vector_if_copy_constructible(enable_if_t<is_copy_constructible<Vector>::value, Class_> &cl) {
     cl.def(init<const Vector &>(), "Copy constructor");
 }
 
-template<typename Vector, typename Class_>
+template <typename Vector, typename Class_>
 void vector_if_equal_operator(enable_if_t<is_comparable<Vector>::value, Class_> &cl) {
     using T = typename Vector::value_type;
 
     cl.def(self == self);
     cl.def(self != self);
 
-    cl.def("count",
-        [](const Vector &v, const T &x) {
-            return std::count(v.begin(), v.end(), x);
-        },
+    cl.def(
+        "count",
+        [](const Vector &v, const T &x) { return std::count(v.begin(), v.end(), x); },
         arg("x"),
-        "Return the number of times ``x`` appears in the list"
-    );
+        "Return the number of times ``x`` appears in the list");
 
-    cl.def("remove", [](Vector &v, const T &x) {
+    cl.def(
+        "remove",
+        [](Vector &v, const T &x) {
             auto p = std::find(v.begin(), v.end(), x);
-            if (p != v.end())
+            if (p != v.end()) {
                 v.erase(p);
-            else
+            } else {
                 throw value_error();
+            }
         },
         arg("x"),
         "Remove the first item from the list whose value is x. "
-        "It is an error if there is no such item."
-    );
+        "It is an error if there is no such item.");
 
-    cl.def("__contains__",
-        [](const Vector &v, const T &x) {
-            return std::find(v.begin(), v.end(), x) != v.end();
-        },
+    cl.def(
+        "__contains__",
+        [](const Vector &v, const T &x) { return std::find(v.begin(), v.end(), x) != v.end(); },
         arg("x"),
-        "Return true the container contains ``x``"
-    );
+        "Return true the container contains ``x``");
 }
 
 // Vector modifiers -- requires a copyable vector_type:
-// (Technically, some of these (pop and __delitem__) don't actually require copyability, but it seems
-// silly to allow deletion but not insertion, so include them here too.)
+// (Technically, some of these (pop and __delitem__) don't actually require copyability, but it
+// seems silly to allow deletion but not insertion, so include them here too.)
 template <typename Vector, typename Class_>
-void vector_modifiers(enable_if_t<is_copy_constructible<typename Vector::value_type>::value, Class_> &cl) {
+void vector_modifiers(
+    enable_if_t<is_copy_constructible<typename Vector::value_type>::value, Class_> &cl) {
     using T = typename Vector::value_type;
     using SizeType = typename Vector::size_type;
     using DiffType = typename Vector::difference_type;
 
     auto wrap_i = [](DiffType i, SizeType n) {
-        if (i < 0)
+        if (i < 0) {
             i += n;
-        if (i < 0 || (SizeType)i >= n)
+        }
+        if (i < 0 || (SizeType) i >= n) {
             throw index_error();
+        }
         return i;
     };
 
-    cl.def("append",
-           [](Vector &v, const T &value) { v.push_back(value); },
-           arg("x"),
-           "Add an item to the end of the list");
+    cl.def(
+        "append",
+        [](Vector &v, const T &value) { v.push_back(value); },
+        arg("x"),
+        "Add an item to the end of the list");
 
-    cl.def(init([](iterable it) {
+    cl.def(init([](const iterable &it) {
         auto v = std::unique_ptr<Vector>(new Vector());
         v->reserve(len_hint(it));
-        for (handle h : it)
-           v->push_back(h.cast<T>());
+        for (handle h : it) {
+            v->push_back(h.cast<T>());
+        }
         return v.release();
     }));
 
-    cl.def("clear",
-        [](Vector &v) {
-            v.clear();
+    cl.def(
+        "clear", [](Vector &v) { v.clear(); }, "Clear the contents");
+
+    cl.def(
+        "extend",
+        [](Vector &v, const Vector &src) { v.insert(v.end(), src.begin(), src.end()); },
+        arg("L"),
+        "Extend the list by appending all the items in the given list");
+
+    cl.def(
+        "extend",
+        [](Vector &v, const iterable &it) {
+            const size_t old_size = v.size();
+            v.reserve(old_size + len_hint(it));
+            try {
+                for (handle h : it) {
+                    v.push_back(h.cast<T>());
+                }
+            } catch (const cast_error &) {
+                v.erase(v.begin() + static_cast<typename Vector::difference_type>(old_size),
+                        v.end());
+                try {
+                    v.shrink_to_fit();
+                } catch (const std::exception &) {
+                    // Do nothing
+                }
+                throw;
+            }
         },
-        "Clear the contents"
-    );
-
-    cl.def("extend",
-       [](Vector &v, const Vector &src) {
-           v.insert(v.end(), src.begin(), src.end());
-       },
-       arg("L"),
-       "Extend the list by appending all the items in the given list"
-    );
+        arg("L"),
+        "Extend the list by appending all the items in the given list");
 
-    cl.def("extend",
-       [](Vector &v, iterable it) {
-           const size_t old_size = v.size();
-           v.reserve(old_size + len_hint(it));
-           try {
-               for (handle h : it) {
-                   v.push_back(h.cast<T>());
-               }
-           } catch (const cast_error &) {
-               v.erase(v.begin() + static_cast<typename Vector::difference_type>(old_size), v.end());
-               try {
-                   v.shrink_to_fit();
-               } catch (const std::exception &) {
-                   // Do nothing
-               }
-               throw;
-           }
-       },
-       arg("L"),
-       "Extend the list by appending all the items in the given list"
-    );
-
-    cl.def("insert",
+    cl.def(
+        "insert",
         [](Vector &v, DiffType i, const T &x) {
             // Can't use wrap_i; i == v.size() is OK
-            if (i < 0)
+            if (i < 0) {
                 i += v.size();
-            if (i < 0 || (SizeType)i > v.size())
+            }
+            if (i < 0 || (SizeType) i > v.size()) {
                 throw index_error();
+            }
             v.insert(v.begin() + i, x);
         },
-        arg("i") , arg("x"),
-        "Insert an item at a given position."
-    );
+        arg("i"),
+        arg("x"),
+        "Insert an item at a given position.");
 
-    cl.def("pop",
+    cl.def(
+        "pop",
         [](Vector &v) {
-            if (v.empty())
+            if (v.empty()) {
                 throw index_error();
-            T t = v.back();
+            }
+            T t = std::move(v.back());
             v.pop_back();
             return t;
         },
-        "Remove and return the last item"
-    );
+        "Remove and return the last item");
 
-    cl.def("pop",
+    cl.def(
+        "pop",
         [wrap_i](Vector &v, DiffType i) {
             i = wrap_i(i, v.size());
-            T t = v[(SizeType) i];
-            v.erase(v.begin() + i);
+            T t = std::move(v[(SizeType) i]);
+            v.erase(std::next(v.begin(), i));
             return t;
         },
         arg("i"),
-        "Remove and return the item at index ``i``"
-    );
+        "Remove and return the item at index ``i``");
 
-    cl.def("__setitem__",
-        [wrap_i](Vector &v, DiffType i, const T &t) {
-            i = wrap_i(i, v.size());
-            v[(SizeType)i] = t;
-        }
-    );
+    cl.def("__setitem__", [wrap_i](Vector &v, DiffType i, const T &t) {
+        i = wrap_i(i, v.size());
+        v[(SizeType) i] = t;
+    });
 
     /// Slicing protocol
-    cl.def("__getitem__",
-        [](const Vector &v, slice slice) -> Vector * {
-            size_t start, stop, step, slicelength;
+    cl.def(
+        "__getitem__",
+        [](const Vector &v, const slice &slice) -> Vector * {
+            size_t start = 0, stop = 0, step = 0, slicelength = 0;
 
-            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength))
+            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength)) {
                 throw error_already_set();
+            }
 
             auto *seq = new Vector();
             seq->reserve((size_t) slicelength);
 
-            for (size_t i=0; i<slicelength; ++i) {
+            for (size_t i = 0; i < slicelength; ++i) {
                 seq->push_back(v[start]);
                 start += step;
             }
             return seq;
         },
         arg("s"),
-        "Retrieve list elements using a slice object"
-    );
+        "Retrieve list elements using a slice object");
 
-    cl.def("__setitem__",
-        [](Vector &v, slice slice,  const Vector &value) {
-            size_t start, stop, step, slicelength;
-            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength))
+    cl.def(
+        "__setitem__",
+        [](Vector &v, const slice &slice, const Vector &value) {
+            size_t start = 0, stop = 0, step = 0, slicelength = 0;
+            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength)) {
                 throw error_already_set();
+            }
 
-            if (slicelength != value.size())
-                throw std::runtime_error("Left and right hand size of slice assignment have different sizes!");
+            if (slicelength != value.size()) {
+                throw std::runtime_error(
+                    "Left and right hand size of slice assignment have different sizes!");
+            }
 
-            for (size_t i=0; i<slicelength; ++i) {
+            for (size_t i = 0; i < slicelength; ++i) {
                 v[start] = value[i];
                 start += step;
             }
         },
-        "Assign list elements using a slice object"
-    );
+        "Assign list elements using a slice object");
 
-    cl.def("__delitem__",
+    cl.def(
+        "__delitem__",
         [wrap_i](Vector &v, DiffType i) {
             i = wrap_i(i, v.size());
             v.erase(v.begin() + i);
         },
-        "Delete the list elements at index ``i``"
-    );
+        "Delete the list elements at index ``i``");
 
-    cl.def("__delitem__",
-        [](Vector &v, slice slice) {
-            size_t start, stop, step, slicelength;
+    cl.def(
+        "__delitem__",
+        [](Vector &v, const slice &slice) {
+            size_t start = 0, stop = 0, step = 0, slicelength = 0;
 
-            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength))
+            if (!slice.compute(v.size(), &start, &stop, &step, &slicelength)) {
                 throw error_already_set();
+            }
 
             if (step == 1 && false) {
                 v.erase(v.begin() + (DiffType) start, v.begin() + DiffType(start + slicelength));
@@ -277,15 +297,15 @@ void vector_modifiers(enable_if_t<is_copy_constructible<typename Vector::value_t
                 }
             }
         },
-        "Delete list elements using a slice object"
-    );
-
+        "Delete list elements using a slice object");
 }
 
 // If the type has an operator[] that doesn't return a reference (most notably std::vector<bool>),
 // we have to access by copying; otherwise we return by reference.
-template <typename Vector> using vector_needs_copy = negation<
-    std::is_same<decltype(std::declval<Vector>()[typename Vector::size_type()]), typename Vector::value_type &>>;
+template <typename Vector>
+using vector_needs_copy
+    = negation<std::is_same<decltype(std::declval<Vector>()[typename Vector::size_type()]),
+                            typename Vector::value_type &>>;
 
 // The usual case: access and iterate by reference
 template <typename Vector, typename Class_>
@@ -293,31 +313,34 @@ void vector_accessor(enable_if_t<!vector_needs_copy<Vector>::value, Class_> &cl)
     using T = typename Vector::value_type;
     using SizeType = typename Vector::size_type;
     using DiffType = typename Vector::difference_type;
-    using ItType   = typename Vector::iterator;
+    using ItType = typename Vector::iterator;
 
     auto wrap_i = [](DiffType i, SizeType n) {
-        if (i < 0)
+        if (i < 0) {
             i += n;
-        if (i < 0 || (SizeType)i >= n)
+        }
+        if (i < 0 || (SizeType) i >= n) {
             throw index_error();
+        }
         return i;
     };
 
-    cl.def("__getitem__",
+    cl.def(
+        "__getitem__",
         [wrap_i](Vector &v, DiffType i) -> T & {
             i = wrap_i(i, v.size());
-            return v[(SizeType)i];
+            return v[(SizeType) i];
         },
         return_value_policy::reference_internal // ref + keepalive
     );
 
-    cl.def("__iter__",
-           [](Vector &v) {
-               return make_iterator<
-                   return_value_policy::reference_internal, ItType, ItType, T&>(
-                   v.begin(), v.end());
-           },
-           keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
+    cl.def(
+        "__iter__",
+        [](Vector &v) {
+            return make_iterator<return_value_policy::reference_internal, ItType, ItType, T &>(
+                v.begin(), v.end());
+        },
+        keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
     );
 }
 
@@ -327,96 +350,129 @@ void vector_accessor(enable_if_t<vector_needs_copy<Vector>::value, Class_> &cl)
     using T = typename Vector::value_type;
     using SizeType = typename Vector::size_type;
     using DiffType = typename Vector::difference_type;
-    using ItType   = typename Vector::iterator;
-    cl.def("__getitem__",
-        [](const Vector &v, DiffType i) -> T {
-            if (i < 0 && (i += v.size()) < 0)
-                throw index_error();
-            if ((SizeType)i >= v.size())
-                throw index_error();
-            return v[(SizeType)i];
+    using ItType = typename Vector::iterator;
+    cl.def("__getitem__", [](const Vector &v, DiffType i) -> T {
+        if (i < 0 && (i += v.size()) < 0) {
+            throw index_error();
         }
-    );
+        if ((SizeType) i >= v.size()) {
+            throw index_error();
+        }
+        return v[(SizeType) i];
+    });
 
-    cl.def("__iter__",
-           [](Vector &v) {
-               return make_iterator<
-                   return_value_policy::copy, ItType, ItType, T>(
-                   v.begin(), v.end());
-           },
-           keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
+    cl.def(
+        "__iter__",
+        [](Vector &v) {
+            return make_iterator<return_value_policy::copy, ItType, ItType, T>(v.begin(), v.end());
+        },
+        keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
     );
 }
 
-template <typename Vector, typename Class_> auto vector_if_insertion_operator(Class_ &cl, std::string const &name)
-    -> decltype(std::declval<std::ostream&>() << std::declval<typename Vector::value_type>(), void()) {
+template <typename Vector, typename Class_>
+auto vector_if_insertion_operator(Class_ &cl, std::string const &name)
+    -> decltype(std::declval<std::ostream &>() << std::declval<typename Vector::value_type>(),
+                void()) {
     using size_type = typename Vector::size_type;
 
-    cl.def("__repr__",
-           [name](Vector &v) {
+    cl.def(
+        "__repr__",
+        [name](Vector &v) {
             std::ostringstream s;
             s << name << '[';
-            for (size_type i=0; i < v.size(); ++i) {
+            for (size_type i = 0; i < v.size(); ++i) {
                 s << v[i];
-                if (i != v.size() - 1)
+                if (i != v.size() - 1) {
                     s << ", ";
+                }
             }
             s << ']';
             return s.str();
         },
-        "Return the canonical string representation of this list."
-    );
+        "Return the canonical string representation of this list.");
 }
 
 // Provide the buffer interface for vectors if we have data() and we have a format for it
-// GCC seems to have "void std::vector<bool>::data()" - doing SFINAE on the existence of data() is insufficient, we need to check it returns an appropriate pointer
+// GCC seems to have "void std::vector<bool>::data()" - doing SFINAE on the existence of data()
+// is insufficient, we need to check it returns an appropriate pointer
 template <typename Vector, typename = void>
 struct vector_has_data_and_format : std::false_type {};
 template <typename Vector>
-struct vector_has_data_and_format<Vector, enable_if_t<std::is_same<decltype(format_descriptor<typename Vector::value_type>::format(), std::declval<Vector>().data()), typename Vector::value_type*>::value>> : std::true_type {};
+struct vector_has_data_and_format<
+    Vector,
+    enable_if_t<std::is_same<decltype(format_descriptor<typename Vector::value_type>::format(),
+                                      std::declval<Vector>().data()),
+                             typename Vector::value_type *>::value>> : std::true_type {};
+
+// [workaround(intel)] Separate function required here
+// Workaround as the Intel compiler does not compile the enable_if_t part below
+// (tested with icc (ICC) 2021.1 Beta 20200827)
+template <typename... Args>
+constexpr bool args_any_are_buffer() {
+    return detail::any_of<std::is_same<Args, buffer_protocol>...>::value;
+}
+
+// [workaround(intel)] Separate function required here
+// [workaround(msvc)] Can't use constexpr bool in return type
 
 // Add the buffer interface to a vector
 template <typename Vector, typename Class_, typename... Args>
-enable_if_t<detail::any_of<std::is_same<Args, buffer_protocol>...>::value>
-vector_buffer(Class_& cl) {
+void vector_buffer_impl(Class_ &cl, std::true_type) {
     using T = typename Vector::value_type;
 
-    static_assert(vector_has_data_and_format<Vector>::value, "There is not an appropriate format descriptor for this vector");
+    static_assert(vector_has_data_and_format<Vector>::value,
+                  "There is not an appropriate format descriptor for this vector");
 
-    // numpy.h declares this for arbitrary types, but it may raise an exception and crash hard at runtime if PYBIND11_NUMPY_DTYPE hasn't been called, so check here
+    // numpy.h declares this for arbitrary types, but it may raise an exception and crash hard
+    // at runtime if PYBIND11_NUMPY_DTYPE hasn't been called, so check here
     format_descriptor<T>::format();
 
-    cl.def_buffer([](Vector& v) -> buffer_info {
-        return buffer_info(v.data(), static_cast<ssize_t>(sizeof(T)), format_descriptor<T>::format(), 1, {v.size()}, {sizeof(T)});
+    cl.def_buffer([](Vector &v) -> buffer_info {
+        return buffer_info(v.data(),
+                           static_cast<ssize_t>(sizeof(T)),
+                           format_descriptor<T>::format(),
+                           1,
+                           {v.size()},
+                           {sizeof(T)});
     });
 
-    cl.def(init([](buffer buf) {
+    cl.def(init([](const buffer &buf) {
         auto info = buf.request();
-        if (info.ndim != 1 || info.strides[0] % static_cast<ssize_t>(sizeof(T)))
+        if (info.ndim != 1 || info.strides[0] % static_cast<ssize_t>(sizeof(T))) {
             throw type_error("Only valid 1D buffers can be copied to a vector");
-        if (!detail::compare_buffer_info<T>::compare(info) || (ssize_t) sizeof(T) != info.itemsize)
-            throw type_error("Format mismatch (Python: " + info.format + " C++: " + format_descriptor<T>::format() + ")");
+        }
+        if (!detail::compare_buffer_info<T>::compare(info)
+            || (ssize_t) sizeof(T) != info.itemsize) {
+            throw type_error("Format mismatch (Python: " + info.format
+                             + " C++: " + format_descriptor<T>::format() + ")");
+        }
 
-        T *p = static_cast<T*>(info.ptr);
+        T *p = static_cast<T *>(info.ptr);
         ssize_t step = info.strides[0] / static_cast<ssize_t>(sizeof(T));
         T *end = p + info.shape[0] * step;
         if (step == 1) {
             return Vector(p, end);
         }
-        else {
-            Vector vec;
-            vec.reserve((size_t) info.shape[0]);
-            for (; p != end; p += step)
-                vec.push_back(*p);
-            return vec;
+        Vector vec;
+        vec.reserve((size_t) info.shape[0]);
+        for (; p != end; p += step) {
+            vec.push_back(*p);
         }
+        return vec;
     }));
 
     return;
 }
 
 template <typename Vector, typename Class_, typename... Args>
-enable_if_t<!detail::any_of<std::is_same<Args, buffer_protocol>...>::value> vector_buffer(Class_&) {}
+void vector_buffer_impl(Class_ &, std::false_type) {}
+
+template <typename Vector, typename Class_, typename... Args>
+void vector_buffer(Class_ &cl) {
+    vector_buffer_impl<Vector, Class_, Args...>(
+        cl, detail::any_of<std::is_same<Args, buffer_protocol>...>{});
+}
 
 PYBIND11_NAMESPACE_END(detail)
 
@@ -424,13 +480,13 @@ PYBIND11_NAMESPACE_END(detail)
 // std::vector
 //
 template <typename Vector, typename holder_type = std::unique_ptr<Vector>, typename... Args>
-class_<Vector, holder_type> bind_vector(handle scope, std::string const &name, Args&&... args) {
+class_<Vector, holder_type> bind_vector(handle scope, std::string const &name, Args &&...args) {
     using Class_ = class_<Vector, holder_type>;
 
     // If the value_type is unregistered (e.g. a converting type) or is itself registered
     // module-local then make the vector binding module-local as well:
     using vtype = typename Vector::value_type;
-    auto vtype_info = detail::get_type_info(typeid(vtype));
+    auto *vtype_info = detail::get_type_info(typeid(vtype));
     bool local = !vtype_info || vtype_info->module_local;
 
     Class_ cl(scope, name.c_str(), pybind11::module_local(local), std::forward<Args>(args)...);
@@ -455,18 +511,13 @@ class_<Vector, holder_type> bind_vector(handle scope, std::string const &name, A
     // Accessor and iterator; return by value if copyable, otherwise we return by ref + keep-alive
     detail::vector_accessor<Vector, Class_>(cl);
 
-    cl.def("__bool__",
-        [](const Vector &v) -> bool {
-            return !v.empty();
-        },
-        "Check whether the list is nonempty"
-    );
+    cl.def(
+        "__bool__",
+        [](const Vector &v) -> bool { return !v.empty(); },
+        "Check whether the list is nonempty");
 
     cl.def("__len__", &Vector::size);
 
-
-
-
 #if 0
     // C++ style functions deprecated, leaving it here as an example
     cl.def(init<size_type>());
@@ -510,8 +561,6 @@ class_<Vector, holder_type> bind_vector(handle scope, std::string const &name, A
     return cl;
 }
 
-
-
 //
 // std::map, std::unordered_map
 //
@@ -519,81 +568,104 @@ class_<Vector, holder_type> bind_vector(handle scope, std::string const &name, A
 PYBIND11_NAMESPACE_BEGIN(detail)
 
 /* Fallback functions */
-template <typename, typename, typename... Args> void map_if_insertion_operator(const Args &...) { }
-template <typename, typename, typename... Args> void map_assignment(const Args &...) { }
+template <typename, typename, typename... Args>
+void map_if_insertion_operator(const Args &...) {}
+template <typename, typename, typename... Args>
+void map_assignment(const Args &...) {}
 
 // Map assignment when copy-assignable: just copy the value
 template <typename Map, typename Class_>
-void map_assignment(enable_if_t<is_copy_assignable<typename Map::mapped_type>::value, Class_> &cl) {
+void map_assignment(
+    enable_if_t<is_copy_assignable<typename Map::mapped_type>::value, Class_> &cl) {
     using KeyType = typename Map::key_type;
     using MappedType = typename Map::mapped_type;
 
-    cl.def("__setitem__",
-           [](Map &m, const KeyType &k, const MappedType &v) {
-               auto it = m.find(k);
-               if (it != m.end()) it->second = v;
-               else m.emplace(k, v);
-           }
-    );
+    cl.def("__setitem__", [](Map &m, const KeyType &k, const MappedType &v) {
+        auto it = m.find(k);
+        if (it != m.end()) {
+            it->second = v;
+        } else {
+            m.emplace(k, v);
+        }
+    });
 }
 
-// Not copy-assignable, but still copy-constructible: we can update the value by erasing and reinserting
-template<typename Map, typename Class_>
-void map_assignment(enable_if_t<
-        !is_copy_assignable<typename Map::mapped_type>::value &&
-        is_copy_constructible<typename Map::mapped_type>::value,
-        Class_> &cl) {
+// Not copy-assignable, but still copy-constructible: we can update the value by erasing and
+// reinserting
+template <typename Map, typename Class_>
+void map_assignment(enable_if_t<!is_copy_assignable<typename Map::mapped_type>::value
+                                    && is_copy_constructible<typename Map::mapped_type>::value,
+                                Class_> &cl) {
     using KeyType = typename Map::key_type;
     using MappedType = typename Map::mapped_type;
 
-    cl.def("__setitem__",
-           [](Map &m, const KeyType &k, const MappedType &v) {
-               // We can't use m[k] = v; because value type might not be default constructable
-               auto r = m.emplace(k, v);
-               if (!r.second) {
-                   // value type is not copy assignable so the only way to insert it is to erase it first...
-                   m.erase(r.first);
-                   m.emplace(k, v);
-               }
-           }
-    );
+    cl.def("__setitem__", [](Map &m, const KeyType &k, const MappedType &v) {
+        // We can't use m[k] = v; because value type might not be default constructable
+        auto r = m.emplace(k, v);
+        if (!r.second) {
+            // value type is not copy assignable so the only way to insert it is to erase it
+            // first...
+            m.erase(r.first);
+            m.emplace(k, v);
+        }
+    });
 }
 
-
-template <typename Map, typename Class_> auto map_if_insertion_operator(Class_ &cl, std::string const &name)
--> decltype(std::declval<std::ostream&>() << std::declval<typename Map::key_type>() << std::declval<typename Map::mapped_type>(), void()) {
-
-    cl.def("__repr__",
-           [name](Map &m) {
+template <typename Map, typename Class_>
+auto map_if_insertion_operator(Class_ &cl, std::string const &name)
+    -> decltype(std::declval<std::ostream &>() << std::declval<typename Map::key_type>()
+                                               << std::declval<typename Map::mapped_type>(),
+                void()) {
+
+    cl.def(
+        "__repr__",
+        [name](Map &m) {
             std::ostringstream s;
             s << name << '{';
             bool f = false;
             for (auto const &kv : m) {
-                if (f)
+                if (f) {
                     s << ", ";
+                }
                 s << kv.first << ": " << kv.second;
                 f = true;
             }
             s << '}';
             return s.str();
         },
-        "Return the canonical string representation of this map."
-    );
+        "Return the canonical string representation of this map.");
 }
 
+template <typename Map>
+struct keys_view {
+    Map &map;
+};
+
+template <typename Map>
+struct values_view {
+    Map &map;
+};
+
+template <typename Map>
+struct items_view {
+    Map &map;
+};
 
 PYBIND11_NAMESPACE_END(detail)
 
 template <typename Map, typename holder_type = std::unique_ptr<Map>, typename... Args>
-class_<Map, holder_type> bind_map(handle scope, const std::string &name, Args&&... args) {
+class_<Map, holder_type> bind_map(handle scope, const std::string &name, Args &&...args) {
     using KeyType = typename Map::key_type;
     using MappedType = typename Map::mapped_type;
+    using KeysView = detail::keys_view<Map>;
+    using ValuesView = detail::values_view<Map>;
+    using ItemsView = detail::items_view<Map>;
     using Class_ = class_<Map, holder_type>;
 
     // If either type is a non-module-local bound type then make the map binding non-local as well;
     // otherwise (e.g. both types are either module-local or converting) the map will be
     // module-local.
-    auto tinfo = detail::get_type_info(typeid(MappedType));
+    auto *tinfo = detail::get_type_info(typeid(MappedType));
     bool local = !tinfo || tinfo->module_local;
     if (local) {
         tinfo = detail::get_type_info(typeid(KeyType));
@@ -601,60 +673,112 @@ class_<Map, holder_type> bind_map(handle scope, const std::string &name, Args&&.
     }
 
     Class_ cl(scope, name.c_str(), pybind11::module_local(local), std::forward<Args>(args)...);
+    class_<KeysView> keys_view(
+        scope, ("KeysView[" + name + "]").c_str(), pybind11::module_local(local));
+    class_<ValuesView> values_view(
+        scope, ("ValuesView[" + name + "]").c_str(), pybind11::module_local(local));
+    class_<ItemsView> items_view(
+        scope, ("ItemsView[" + name + "]").c_str(), pybind11::module_local(local));
 
     cl.def(init<>());
 
     // Register stream insertion operator (if possible)
     detail::map_if_insertion_operator<Map, Class_>(cl, name);
 
-    cl.def("__bool__",
+    cl.def(
+        "__bool__",
         [](const Map &m) -> bool { return !m.empty(); },
-        "Check whether the map is nonempty"
+        "Check whether the map is nonempty");
+
+    cl.def(
+        "__iter__",
+        [](Map &m) { return make_key_iterator(m.begin(), m.end()); },
+        keep_alive<0, 1>() /* Essential: keep map alive while iterator exists */
     );
 
-    cl.def("__iter__",
-           [](Map &m) { return make_key_iterator(m.begin(), m.end()); },
-           keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
+    cl.def(
+        "keys",
+        [](Map &m) { return KeysView{m}; },
+        keep_alive<0, 1>() /* Essential: keep map alive while view exists */
     );
 
-    cl.def("items",
-           [](Map &m) { return make_iterator(m.begin(), m.end()); },
-           keep_alive<0, 1>() /* Essential: keep list alive while iterator exists */
+    cl.def(
+        "values",
+        [](Map &m) { return ValuesView{m}; },
+        keep_alive<0, 1>() /* Essential: keep map alive while view exists */
     );
 
-    cl.def("__getitem__",
+    cl.def(
+        "items",
+        [](Map &m) { return ItemsView{m}; },
+        keep_alive<0, 1>() /* Essential: keep map alive while view exists */
+    );
+
+    cl.def(
+        "__getitem__",
         [](Map &m, const KeyType &k) -> MappedType & {
             auto it = m.find(k);
-            if (it == m.end())
-              throw key_error();
-           return it->second;
+            if (it == m.end()) {
+                throw key_error();
+            }
+            return it->second;
         },
         return_value_policy::reference_internal // ref + keepalive
     );
 
-    cl.def("__contains__",
-        [](Map &m, const KeyType &k) -> bool {
-            auto it = m.find(k);
-            if (it == m.end())
-              return false;
-           return true;
+    cl.def("__contains__", [](Map &m, const KeyType &k) -> bool {
+        auto it = m.find(k);
+        if (it == m.end()) {
+            return false;
         }
-    );
+        return true;
+    });
+    // Fallback for when the object is not of the key type
+    cl.def("__contains__", [](Map &, const object &) -> bool { return false; });
 
     // Assignment provided only if the type is copyable
     detail::map_assignment<Map, Class_>(cl);
 
-    cl.def("__delitem__",
-           [](Map &m, const KeyType &k) {
-               auto it = m.find(k);
-               if (it == m.end())
-                   throw key_error();
-               m.erase(it);
-           }
-    );
+    cl.def("__delitem__", [](Map &m, const KeyType &k) {
+        auto it = m.find(k);
+        if (it == m.end()) {
+            throw key_error();
+        }
+        m.erase(it);
+    });
 
     cl.def("__len__", &Map::size);
 
+    keys_view.def("__len__", [](KeysView &view) { return view.map.size(); });
+    keys_view.def(
+        "__iter__",
+        [](KeysView &view) { return make_key_iterator(view.map.begin(), view.map.end()); },
+        keep_alive<0, 1>() /* Essential: keep view alive while iterator exists */
+    );
+    keys_view.def("__contains__", [](KeysView &view, const KeyType &k) -> bool {
+        auto it = view.map.find(k);
+        if (it == view.map.end()) {
+            return false;
+        }
+        return true;
+    });
+    // Fallback for when the object is not of the key type
+    keys_view.def("__contains__", [](KeysView &, const object &) -> bool { return false; });
+
+    values_view.def("__len__", [](ValuesView &view) { return view.map.size(); });
+    values_view.def(
+        "__iter__",
+        [](ValuesView &view) { return make_value_iterator(view.map.begin(), view.map.end()); },
+        keep_alive<0, 1>() /* Essential: keep view alive while iterator exists */
+    );
+
+    items_view.def("__len__", [](ItemsView &view) { return view.map.size(); });
+    items_view.def(
+        "__iter__",
+        [](ItemsView &view) { return make_iterator(view.map.begin(), view.map.end()); },
+        keep_alive<0, 1>() /* Essential: keep view alive while iterator exists */
+    );
+
     return cl;
 }
 
diff --git a/3rdparty/pybind11/noxfile.py b/3rdparty/pybind11/noxfile.py
new file mode 100644
index 0000000000..021ced2453
--- /dev/null
+++ b/3rdparty/pybind11/noxfile.py
@@ -0,0 +1,107 @@
+import os
+
+import nox
+
+nox.needs_version = ">=2022.1.7"
+nox.options.sessions = ["lint", "tests", "tests_packaging"]
+
+PYTHON_VERSIONS = [
+    "3.6",
+    "3.7",
+    "3.8",
+    "3.9",
+    "3.10",
+    "3.11",
+    "pypy3.7",
+    "pypy3.8",
+    "pypy3.9",
+]
+
+if os.environ.get("CI", None):
+    nox.options.error_on_missing_interpreters = True
+
+
+@nox.session(reuse_venv=True)
+def lint(session: nox.Session) -> None:
+    """
+    Lint the codebase (except for clang-format/tidy).
+    """
+    session.install("pre-commit")
+    session.run("pre-commit", "run", "-a", *session.posargs)
+
+
+@nox.session(python=PYTHON_VERSIONS)
+def tests(session: nox.Session) -> None:
+    """
+    Run the tests (requires a compiler).
+    """
+    tmpdir = session.create_tmp()
+    session.install("cmake")
+    session.install("-r", "tests/requirements.txt")
+    session.run(
+        "cmake",
+        "-S.",
+        f"-B{tmpdir}",
+        "-DPYBIND11_WERROR=ON",
+        "-DDOWNLOAD_CATCH=ON",
+        "-DDOWNLOAD_EIGEN=ON",
+        *session.posargs,
+    )
+    session.run("cmake", "--build", tmpdir)
+    session.run("cmake", "--build", tmpdir, "--config=Release", "--target", "check")
+
+
+@nox.session
+def tests_packaging(session: nox.Session) -> None:
+    """
+    Run the packaging tests.
+    """
+
+    session.install("-r", "tests/requirements.txt", "--prefer-binary")
+    session.run("pytest", "tests/extra_python_package", *session.posargs)
+
+
+@nox.session(reuse_venv=True)
+def docs(session: nox.Session) -> None:
+    """
+    Build the docs. Pass "serve" to serve.
+    """
+
+    session.install("-r", "docs/requirements.txt")
+    session.chdir("docs")
+
+    if "pdf" in session.posargs:
+        session.run("sphinx-build", "-M", "latexpdf", ".", "_build")
+        return
+
+    session.run("sphinx-build", "-M", "html", ".", "_build")
+
+    if "serve" in session.posargs:
+        session.log("Launching docs at http://localhost:8000/ - use Ctrl-C to quit")
+        session.run("python", "-m", "http.server", "8000", "-d", "_build/html")
+    elif session.posargs:
+        session.error("Unsupported argument to docs")
+
+
+@nox.session(reuse_venv=True)
+def make_changelog(session: nox.Session) -> None:
+    """
+    Inspect the closed issues and make entries for a changelog.
+    """
+    session.install("ghapi", "rich")
+    session.run("python", "tools/make_changelog.py")
+
+
+@nox.session(reuse_venv=True)
+def build(session: nox.Session) -> None:
+    """
+    Build SDists and wheels.
+    """
+
+    session.install("build")
+    session.log("Building normal files")
+    session.run("python", "-m", "build", *session.posargs)
+    session.log("Building pybind11-global files (PYBIND11_GLOBAL_SDIST=1)")
+    session.run(
+        "python", "-m", "build", *session.posargs, env={"PYBIND11_GLOBAL_SDIST": "1"}
+    )
diff --git a/3rdparty/pybind11/pybind11/__init__.py b/3rdparty/pybind11/pybind11/__init__.py
index ad65420893..4fbb17079f 100644
--- a/3rdparty/pybind11/pybind11/__init__.py
+++ b/3rdparty/pybind11/pybind11/__init__.py
@@ -1,12 +1,17 @@
-# -*- coding: utf-8 -*-
+import sys
 
-from ._version import version_info, __version__
-from .commands import get_include, get_cmake_dir
+if sys.version_info < (3, 6):
+    msg = "pybind11 does not support Python < 3.6. 2.9 was the last release supporting Python 2.7 and 3.5."
+    raise ImportError(msg)
 
 
+from ._version import __version__, version_info
+from .commands import get_cmake_dir, get_include, get_pkgconfig_dir
+
 __all__ = (
     "version_info",
     "__version__",
     "get_include",
     "get_cmake_dir",
+    "get_pkgconfig_dir",
 )
diff --git a/3rdparty/pybind11/pybind11/__main__.py b/3rdparty/pybind11/pybind11/__main__.py
index 020988c671..8c89533843 100644
--- a/3rdparty/pybind11/pybind11/__main__.py
+++ b/3rdparty/pybind11/pybind11/__main__.py
@@ -1,15 +1,13 @@
-# -*- coding: utf-8 -*-
-from __future__ import print_function
+# pylint: disable=missing-function-docstring
 
 import argparse
 import sys
 import sysconfig
 
-from .commands import get_include, get_cmake_dir
+from .commands import get_cmake_dir, get_include, get_pkgconfig_dir
 
 
-def print_includes():
-    # type: () -> None
+def print_includes() -> None:
     dirs = [
         sysconfig.get_path("include"),
         sysconfig.get_path("platinclude"),
@@ -25,8 +23,7 @@ def print_includes():
     print(" ".join("-I" + d for d in unique_dirs))
 
 
-def main():
-    # type: () -> None
+def main() -> None:
 
     parser = argparse.ArgumentParser()
     parser.add_argument(
@@ -39,6 +36,11 @@ def main():
         action="store_true",
         help="Print the CMake module directory, ideal for setting -Dpybind11_ROOT in CMake.",
     )
+    parser.add_argument(
+        "--pkgconfigdir",
+        action="store_true",
+        help="Print the pkgconfig directory, ideal for setting $PKG_CONFIG_PATH.",
+    )
     args = parser.parse_args()
     if not sys.argv[1:]:
         parser.print_help()
@@ -46,6 +48,8 @@ def main():
         print_includes()
     if args.cmakedir:
         print(get_cmake_dir())
+    if args.pkgconfigdir:
+        print(get_pkgconfig_dir())
 
 
 if __name__ == "__main__":
diff --git a/3rdparty/pybind11/pybind11/_version.py b/3rdparty/pybind11/pybind11/_version.py
index d18535cd7b..1cb51fc5c2 100644
--- a/3rdparty/pybind11/pybind11/_version.py
+++ b/3rdparty/pybind11/pybind11/_version.py
@@ -1,12 +1,12 @@
-# -*- coding: utf-8 -*-
+from typing import Union
 
 
-def _to_int(s):
+def _to_int(s: str) -> Union[int, str]:
     try:
         return int(s)
     except ValueError:
         return s
 
 
-__version__ = "2.6.1"
+__version__ = "2.11.0.dev1"
 version_info = tuple(_to_int(s) for s in __version__.split("."))
diff --git a/3rdparty/pybind11/pybind11/commands.py b/3rdparty/pybind11/pybind11/commands.py
index 34dbaf8a89..152fa20ce7 100644
--- a/3rdparty/pybind11/pybind11/commands.py
+++ b/3rdparty/pybind11/pybind11/commands.py
@@ -1,22 +1,37 @@
-# -*- coding: utf-8 -*-
 import os
 
-
 DIR = os.path.abspath(os.path.dirname(__file__))
 
 
-def get_include(user=False):
-    # type: (bool) -> str
+def get_include(user: bool = False) -> str:  # pylint: disable=unused-argument
+    """
+    Return the path to the pybind11 include directory. The historical "user"
+    argument is unused, and may be removed.
+    """
     installed_path = os.path.join(DIR, "include")
     source_path = os.path.join(os.path.dirname(DIR), "include")
     return installed_path if os.path.exists(installed_path) else source_path
 
 
-def get_cmake_dir():
-    # type: () -> str
+def get_cmake_dir() -> str:
+    """
+    Return the path to the pybind11 CMake module directory.
+    """
     cmake_installed_path = os.path.join(DIR, "share", "cmake", "pybind11")
     if os.path.exists(cmake_installed_path):
         return cmake_installed_path
-    else:
-        msg = "pybind11 not installed, installation required to access the CMake files"
-        raise ImportError(msg)
+
+    msg = "pybind11 not installed, installation required to access the CMake files"
+    raise ImportError(msg)
+
+
+def get_pkgconfig_dir() -> str:
+    """
+    Return the path to the pybind11 pkgconfig directory.
+    """
+    pkgconfig_installed_path = os.path.join(DIR, "share", "pkgconfig")
+    if os.path.exists(pkgconfig_installed_path):
+        return pkgconfig_installed_path
+
+    msg = "pybind11 not installed, installation required to access the pkgconfig files"
+    raise ImportError(msg)
diff --git a/3rdparty/pybind11/pybind11/setup_helpers.py b/3rdparty/pybind11/pybind11/setup_helpers.py
index 33605ddfd1..1fd04b9154 100644
--- a/3rdparty/pybind11/pybind11/setup_helpers.py
+++ b/3rdparty/pybind11/pybind11/setup_helpers.py
@@ -1,5 +1,3 @@
-# -*- coding: utf-8 -*-
-
 """
 This module provides helpers for C++11+ projects using pybind11.
 
@@ -41,26 +39,40 @@
 
 import contextlib
 import os
+import platform
+import shlex
 import shutil
 import sys
+import sysconfig
 import tempfile
 import threading
-import platform
 import warnings
+from functools import lru_cache
+from pathlib import Path
+from typing import (
+    Any,
+    Callable,
+    Dict,
+    Iterable,
+    Iterator,
+    List,
+    Optional,
+    Tuple,
+    TypeVar,
+    Union,
+)
 
 try:
-    from setuptools.command.build_ext import build_ext as _build_ext
     from setuptools import Extension as _Extension
+    from setuptools.command.build_ext import build_ext as _build_ext
 except ImportError:
     from distutils.command.build_ext import build_ext as _build_ext
     from distutils.extension import Extension as _Extension
 
-import distutils.errors
 import distutils.ccompiler
+import distutils.errors
 
-
-WIN = sys.platform.startswith("win32")
-PY2 = sys.version_info[0] < 3
+WIN = sys.platform.startswith("win32") and "mingw" not in sysconfig.get_platform()
 MACOS = sys.platform.startswith("darwin")
 STD_TMPL = "/std:c++{}" if WIN else "-std=c++{}"
 
@@ -72,7 +84,7 @@
 # directory into your path if it sits beside your setup.py.
 
 
-class Pybind11Extension(_Extension):
+class Pybind11Extension(_Extension):  # type: ignore[misc]
     """
     Build a C++11+ Extension module with pybind11. This automatically adds the
     recommended flags when you init the extension and assumes C++ sources - you
@@ -84,7 +96,7 @@ class Pybind11Extension(_Extension):
     * ``stdlib=libc++`` on macOS
     * ``visibility=hidden`` and ``-g0`` on Unix
 
-    Finally, you can set ``cxx_std`` via constructor or afterwords to enable
+    Finally, you can set ``cxx_std`` via constructor or afterwards to enable
     flags for C++ std, and a few extra helper flags related to the C++ standard
     level. It is _highly_ recommended you either set this, or use the provided
     ``build_ext``, which will search for the highest supported extension for
@@ -94,22 +106,18 @@ class Pybind11Extension(_Extension):
 
     If you want to add pybind11 headers manually, for example for an exact
     git checkout, then set ``include_pybind11=False``.
-
-    Warning: do not use property-based access to the instance on Python 2 -
-    this is an ugly old-style class due to Distutils.
     """
 
-    def _add_cflags(self, *flags):
-        for flag in flags:
-            if flag not in self.extra_compile_args:
-                self.extra_compile_args.append(flag)
+    # flags are prepended, so that they can be further overridden, e.g. by
+    # ``extra_compile_args=["-g"]``.
+
+    def _add_cflags(self, flags: List[str]) -> None:
+        self.extra_compile_args[:0] = flags
 
-    def _add_lflags(self, *flags):
-        for flag in flags:
-            if flag not in self.extra_link_args:
-                self.extra_link_args.append(flag)
+    def _add_ldflags(self, flags: List[str]) -> None:
+        self.extra_link_args[:0] = flags
 
-    def __init__(self, *args, **kwargs):
+    def __init__(self, *args: Any, **kwargs: Any) -> None:
 
         self._cxx_level = 0
         cxx_std = kwargs.pop("cxx_std", 0)
@@ -119,9 +127,7 @@ def __init__(self, *args, **kwargs):
 
         include_pybind11 = kwargs.pop("include_pybind11", True)
 
-        # Can't use super here because distutils has old-style classes in
-        # Python 2!
-        _Extension.__init__(self, *args, **kwargs)
+        super().__init__(*args, **kwargs)
 
         # Include the installed package pybind11 headers
         if include_pybind11:
@@ -133,33 +139,41 @@ def __init__(self, *args, **kwargs):
 
                 if pyinc not in self.include_dirs:
                     self.include_dirs.append(pyinc)
-            except ImportError:
+            except ModuleNotFoundError:
                 pass
 
-        # Have to use the accessor manually to support Python 2 distutils
-        Pybind11Extension.cxx_std.__set__(self, cxx_std)
+        self.cxx_std = cxx_std
 
+        cflags = []
+        ldflags = []
         if WIN:
-            self._add_cflags("/EHsc", "/bigobj")
+            cflags += ["/EHsc", "/bigobj"]
         else:
-            self._add_cflags("-fvisibility=hidden", "-g0")
+            cflags += ["-fvisibility=hidden"]
+            env_cflags = os.environ.get("CFLAGS", "")
+            env_cppflags = os.environ.get("CPPFLAGS", "")
+            c_cpp_flags = shlex.split(env_cflags) + shlex.split(env_cppflags)
+            if not any(opt.startswith("-g") for opt in c_cpp_flags):
+                cflags += ["-g0"]
             if MACOS:
-                self._add_cflags("-stdlib=libc++")
-                self._add_lflags("-stdlib=libc++")
+                cflags += ["-stdlib=libc++"]
+                ldflags += ["-stdlib=libc++"]
+        self._add_cflags(cflags)
+        self._add_ldflags(ldflags)
 
     @property
-    def cxx_std(self):
+    def cxx_std(self) -> int:
         """
-        The CXX standard level. If set, will add the required flags. If left
-        at 0, it will trigger an automatic search when pybind11's build_ext
-        is used. If None, will have no effect.  Besides just the flags, this
-        may add a register warning/error fix for Python 2 or macos-min 10.9
-        or 10.14.
+        The CXX standard level. If set, will add the required flags. If left at
+        0, it will trigger an automatic search when pybind11's build_ext is
+        used. If None, will have no effect.  Besides just the flags, this may
+        add a macos-min 10.9 or 10.14 flag if MACOSX_DEPLOYMENT_TARGET is
+        unset.
         """
         return self._cxx_level
 
     @cxx_std.setter
-    def cxx_std(self, level):
+    def cxx_std(self, level: int) -> None:
 
         if self._cxx_level:
             warnings.warn("You cannot safely change the cxx_level after setting it!")
@@ -174,7 +188,8 @@ def cxx_std(self, level):
         if not level:
             return
 
-        self.extra_compile_args.append(STD_TMPL.format(level))
+        cflags = [STD_TMPL.format(level)]
+        ldflags = []
 
         if MACOS and "MACOSX_DEPLOYMENT_TARGET" not in os.environ:
             # C++17 requires a higher min version of macOS. An earlier version
@@ -185,28 +200,20 @@ def cxx_std(self, level):
             current_macos = tuple(int(x) for x in platform.mac_ver()[0].split(".")[:2])
             desired_macos = (10, 9) if level < 17 else (10, 14)
             macos_string = ".".join(str(x) for x in min(current_macos, desired_macos))
-            macosx_min = "-mmacosx-version-min=" + macos_string
-            self.extra_compile_args.append(macosx_min)
-            self.extra_link_args.append(macosx_min)
+            macosx_min = f"-mmacosx-version-min={macos_string}"
+            cflags += [macosx_min]
+            ldflags += [macosx_min]
 
-        if PY2:
-            if WIN:
-                # Will be ignored on MSVC 2015, where C++17 is not supported so
-                # this flag is not valid.
-                self.extra_compile_args.append("/wd5033")
-            elif level >= 17:
-                self.extra_compile_args.append("-Wno-register")
-            elif level >= 14:
-                self.extra_compile_args.append("-Wno-deprecated-register")
+        self._add_cflags(cflags)
+        self._add_ldflags(ldflags)
 
 
 # Just in case someone clever tries to multithread
 tmp_chdir_lock = threading.Lock()
-cpp_cache_lock = threading.Lock()
 
 
 @contextlib.contextmanager
-def tmp_chdir():
+def tmp_chdir() -> Iterator[str]:
     "Prepare and enter a temporary directory, cleanup when done"
 
     # Threadsafe
@@ -222,7 +229,7 @@ def tmp_chdir():
 
 
 # cf http://bugs.python.org/issue26689
-def has_flag(compiler, flag):
+def has_flag(compiler: Any, flag: str) -> bool:
     """
     Return the flag if a flag name is supported on the
     specified compiler, otherwise None (can be used as a boolean).
@@ -230,12 +237,12 @@ def has_flag(compiler, flag):
     """
 
     with tmp_chdir():
-        fname = "flagcheck.cpp"
-        with open(fname, "w") as f:
-            f.write("int main (int argc, char **argv) { return 0; }")
+        fname = Path("flagcheck.cpp")
+        # Don't trigger -Wunused-parameter.
+        fname.write_text("int main (int, char **) { return 0; }", encoding="utf-8")
 
         try:
-            compiler.compile([fname], extra_postargs=[flag])
+            compiler.compile([str(fname)], extra_postargs=[flag])
         except distutils.errors.CompileError:
             return False
         return True
@@ -245,7 +252,8 @@ def has_flag(compiler, flag):
 cpp_flag_cache = None
 
 
-def auto_cpp_level(compiler):
+@lru_cache()
+def auto_cpp_level(compiler: Any) -> Union[str, int]:
     """
     Return the max supported C++ std level (17, 14, or 11). Returns latest on Windows.
     """
@@ -253,48 +261,78 @@ def auto_cpp_level(compiler):
     if WIN:
         return "latest"
 
-    global cpp_flag_cache
-
-    # If this has been previously calculated with the same args, return that
-    with cpp_cache_lock:
-        if cpp_flag_cache:
-            return cpp_flag_cache
-
     levels = [17, 14, 11]
 
     for level in levels:
         if has_flag(compiler, STD_TMPL.format(level)):
-            with cpp_cache_lock:
-                cpp_flag_cache = level
             return level
 
     msg = "Unsupported compiler -- at least C++11 support is needed!"
     raise RuntimeError(msg)
 
 
-class build_ext(_build_ext):  # noqa: N801
+class build_ext(_build_ext):  # type: ignore[misc] # noqa: N801
     """
     Customized build_ext that allows an auto-search for the highest supported
     C++ level for Pybind11Extension. This is only needed for the auto-search
     for now, and is completely optional otherwise.
     """
 
-    def build_extensions(self):
+    def build_extensions(self) -> None:
         """
         Build extensions, injecting C++ std for Pybind11Extension if needed.
         """
 
         for ext in self.extensions:
             if hasattr(ext, "_cxx_level") and ext._cxx_level == 0:
-                # Python 2 syntax - old-style distutils class
-                ext.__class__.cxx_std.__set__(ext, auto_cpp_level(self.compiler))
+                ext.cxx_std = auto_cpp_level(self.compiler)
 
-        # Python 2 doesn't allow super here, since distutils uses old-style
-        # classes!
-        _build_ext.build_extensions(self)
+        super().build_extensions()
 
 
-def naive_recompile(obj, src):
+def intree_extensions(
+    paths: Iterable[str], package_dir: Optional[Dict[str, str]] = None
+) -> List[Pybind11Extension]:
+    """
+    Generate Pybind11Extensions from source files directly located in a Python
+    source tree.
+
+    ``package_dir`` behaves as in ``setuptools.setup``.  If unset, the Python
+    package root parent is determined as the first parent directory that does
+    not contain an ``__init__.py`` file.
+    """
+    exts = []
+
+    if package_dir is None:
+        for path in paths:
+            parent, _ = os.path.split(path)
+            while os.path.exists(os.path.join(parent, "__init__.py")):
+                parent, _ = os.path.split(parent)
+            relname, _ = os.path.splitext(os.path.relpath(path, parent))
+            qualified_name = relname.replace(os.path.sep, ".")
+            exts.append(Pybind11Extension(qualified_name, [path]))
+        return exts
+
+    for path in paths:
+        for prefix, parent in package_dir.items():
+            if path.startswith(parent):
+                relname, _ = os.path.splitext(os.path.relpath(path, parent))
+                qualified_name = relname.replace(os.path.sep, ".")
+                if prefix:
+                    qualified_name = prefix + "." + qualified_name
+                exts.append(Pybind11Extension(qualified_name, [path]))
+                break
+        else:
+            msg = (
+                f"path {path} is not a child of any of the directories listed "
+                f"in 'package_dir' ({package_dir})"
+            )
+            raise ValueError(msg)
+
+    return exts
+
+
+def naive_recompile(obj: str, src: str) -> bool:
     """
     This will recompile only if the source file changes. It does not check
     header files, so a more advanced function or Ccache is better if you have
@@ -303,7 +341,7 @@ def naive_recompile(obj, src):
     return os.stat(obj).st_mtime < os.stat(src).st_mtime
 
 
-def no_recompile(obg, src):
+def no_recompile(obg: str, src: str) -> bool:  # pylint: disable=unused-argument
     """
     This is the safest but slowest choice (and is the default) - will always
     recompile sources.
@@ -311,15 +349,33 @@ def no_recompile(obg, src):
     return True
 
 
+S = TypeVar("S", bound="ParallelCompile")
+
+CCompilerMethod = Callable[
+    [
+        distutils.ccompiler.CCompiler,
+        List[str],
+        Optional[str],
+        Optional[Union[Tuple[str], Tuple[str, Optional[str]]]],
+        Optional[List[str]],
+        bool,
+        Optional[List[str]],
+        Optional[List[str]],
+        Optional[List[str]],
+    ],
+    List[str],
+]
+
+
 # Optional parallel compile utility
 # inspired by: http://stackoverflow.com/questions/11013851/speeding-up-build-process-with-distutils
 # and: https://github.com/tbenthompson/cppimport/blob/stable/cppimport/build_module.py
 # and NumPy's parallel distutils module:
 #              https://github.com/numpy/numpy/blob/master/numpy/distutils/ccompiler.py
-class ParallelCompile(object):
+class ParallelCompile:
     """
     Make a parallel compile function. Inspired by
-    numpy.distutils.ccompiler.CCompiler_compile and cppimport.
+    numpy.distutils.ccompiler.CCompiler.compile and cppimport.
 
     This takes several arguments that allow you to customize the compile
     function created:
@@ -354,35 +410,41 @@ class ParallelCompile(object):
 
     __slots__ = ("envvar", "default", "max", "_old", "needs_recompile")
 
-    def __init__(self, envvar=None, default=0, max=0, needs_recompile=no_recompile):
+    def __init__(
+        self,
+        envvar: Optional[str] = None,
+        default: int = 0,
+        max: int = 0,  # pylint: disable=redefined-builtin
+        needs_recompile: Callable[[str, str], bool] = no_recompile,
+    ) -> None:
         self.envvar = envvar
         self.default = default
         self.max = max
         self.needs_recompile = needs_recompile
-        self._old = []
+        self._old: List[CCompilerMethod] = []
 
-    def function(self):
+    def function(self) -> CCompilerMethod:
         """
         Builds a function object usable as distutils.ccompiler.CCompiler.compile.
         """
 
         def compile_function(
-            compiler,
-            sources,
-            output_dir=None,
-            macros=None,
-            include_dirs=None,
-            debug=0,
-            extra_preargs=None,
-            extra_postargs=None,
-            depends=None,
-        ):
+            compiler: distutils.ccompiler.CCompiler,
+            sources: List[str],
+            output_dir: Optional[str] = None,
+            macros: Optional[Union[Tuple[str], Tuple[str, Optional[str]]]] = None,
+            include_dirs: Optional[List[str]] = None,
+            debug: bool = False,
+            extra_preargs: Optional[List[str]] = None,
+            extra_postargs: Optional[List[str]] = None,
+            depends: Optional[List[str]] = None,
+        ) -> Any:
 
             # These lines are directly from distutils.ccompiler.CCompiler
-            macros, objects, extra_postargs, pp_opts, build = compiler._setup_compile(
+            macros, objects, extra_postargs, pp_opts, build = compiler._setup_compile(  # type: ignore[attr-defined]
                 output_dir, macros, include_dirs, sources, depends, extra_postargs
             )
-            cc_args = compiler._get_cc_args(pp_opts, debug, extra_preargs)
+            cc_args = compiler._get_cc_args(pp_opts, debug, extra_preargs)  # type: ignore[attr-defined]
 
             # The number of threads; start with default.
             threads = self.default
@@ -391,17 +453,19 @@ def compile_function(
             if self.envvar is not None:
                 threads = int(os.environ.get(self.envvar, self.default))
 
-            def _single_compile(obj):
+            def _single_compile(obj: Any) -> None:
                 try:
                     src, ext = build[obj]
                 except KeyError:
                     return
 
                 if not os.path.exists(obj) or self.needs_recompile(obj, src):
-                    compiler._compile(obj, src, ext, cc_args, extra_postargs, pp_opts)
+                    compiler._compile(obj, src, ext, cc_args, extra_postargs, pp_opts)  # type: ignore[attr-defined]
 
             try:
-                import multiprocessing
+                # Importing .synchronize checks for platforms that have some multiprocessing
+                # capabilities but lack semaphores, such as AWS Lambda and Android Termux.
+                import multiprocessing.synchronize
                 from multiprocessing.pool import ThreadPool
             except ImportError:
                 threads = 1
@@ -414,8 +478,9 @@ def _single_compile(obj):
                     threads = 1
 
             if threads > 1:
-                for _ in ThreadPool(threads).imap_unordered(_single_compile, objects):
-                    pass
+                with ThreadPool(threads) as pool:
+                    for _ in pool.imap_unordered(_single_compile, objects):
+                        pass
             else:
                 for ob in objects:
                     _single_compile(ob)
@@ -424,13 +489,16 @@ def _single_compile(obj):
 
         return compile_function
 
-    def install(self):
-        distutils.ccompiler.CCompiler.compile = self.function()
+    def install(self: S) -> S:
+        """
+        Installs the compile function into distutils.ccompiler.CCompiler.compile.
+        """
+        distutils.ccompiler.CCompiler.compile = self.function()  # type: ignore[assignment]
         return self
 
-    def __enter__(self):
+    def __enter__(self: S) -> S:
         self._old.append(distutils.ccompiler.CCompiler.compile)
         return self.install()
 
-    def __exit__(self, *args):
-        distutils.ccompiler.CCompiler.compile = self._old.pop()
+    def __exit__(self, *args: Any) -> None:
+        distutils.ccompiler.CCompiler.compile = self._old.pop()  # type: ignore[assignment]
diff --git a/3rdparty/pybind11/pyproject.toml b/3rdparty/pybind11/pyproject.toml
index 5c9d153541..3ba1b4b22f 100644
--- a/3rdparty/pybind11/pyproject.toml
+++ b/3rdparty/pybind11/pyproject.toml
@@ -1,3 +1,61 @@
 [build-system]
-requires = ["setuptools>=42", "wheel", "cmake>=3.18", "ninja"]
+requires = ["setuptools>=42", "cmake>=3.18", "ninja"]
 build-backend = "setuptools.build_meta"
+
+[tool.check-manifest]
+ignore = [
+    "tests/**",
+    "docs/**",
+    "tools/**",
+    "include/**",
+    ".*",
+    "pybind11/include/**",
+    "pybind11/share/**",
+    "CMakeLists.txt",
+    "noxfile.py",
+]
+
+[tool.isort]
+# Needs the compiled .so modules and env.py from tests
+known_first_party = "env,pybind11_cross_module_tests,pybind11_tests,"
+# For black compatibility
+profile = "black"
+
+[tool.mypy]
+files = ["pybind11"]
+python_version = "3.6"
+strict = true
+show_error_codes = true
+enable_error_code = ["ignore-without-code", "redundant-expr", "truthy-bool"]
+warn_unreachable = true
+
+[[tool.mypy.overrides]]
+module = ["ghapi.*", "setuptools.*"]
+ignore_missing_imports = true
+
+
+[tool.pytest.ini_options]
+minversion = "6.0"
+addopts = ["-ra", "--showlocals", "--strict-markers", "--strict-config"]
+xfail_strict = true
+filterwarnings = ["error"]
+log_cli_level = "info"
+testpaths = [
+    "tests",
+]
+timeout=300
+
+
+[tool.pylint]
+master.py-version = "3.6"
+reports.output-format = "colorized"
+messages_control.disable = [
+  "design",
+  "fixme",
+  "imports",
+  "line-too-long",
+  "imports",
+  "invalid-name",
+  "protected-access",
+  "missing-module-docstring",
+]
diff --git a/3rdparty/pybind11/setup.cfg b/3rdparty/pybind11/setup.cfg
index e7fc8f4da5..9af50ea483 100644
--- a/3rdparty/pybind11/setup.cfg
+++ b/3rdparty/pybind11/setup.cfg
@@ -13,13 +13,13 @@ classifiers =
     Topic :: Software Development :: Libraries :: Python Modules
     Topic :: Utilities
     Programming Language :: C++
-    Programming Language :: Python :: 2.7
-    Programming Language :: Python :: 3
-    Programming Language :: Python :: 3.5
+    Programming Language :: Python :: 3 :: Only
     Programming Language :: Python :: 3.6
     Programming Language :: Python :: 3.7
     Programming Language :: Python :: 3.8
     Programming Language :: Python :: 3.9
+    Programming Language :: Python :: 3.10
+    Programming Language :: Python :: 3.11
     License :: OSI Approved :: BSD License
     Programming Language :: Python :: Implementation :: PyPy
     Programming Language :: Python :: Implementation :: CPython
@@ -30,42 +30,21 @@ keywords =
     C++11
     Python bindings
 
+project_urls =
+    Documentation = https://pybind11.readthedocs.io/
+    Bug Tracker = https://github.com/pybind/pybind11/issues
+    Discussions = https://github.com/pybind/pybind11/discussions
+    Changelog = https://pybind11.readthedocs.io/en/latest/changelog.html
+    Chat = https://gitter.im/pybind/Lobby
+
 [options]
-python_requires = >=2.7, !=3.0, !=3.1, !=3.2, !=3.3, !=3.4
+python_requires = >=3.6
 zip_safe = False
 
-[bdist_wheel]
-universal=1
-
-[check-manifest]
-ignore =
-    tests/**
-    docs/**
-    tools/**
-    include/**
-    .appveyor.yml
-    .cmake-format.yaml
-    .gitmodules
-    .pre-commit-config.yaml
-    .readthedocs.yml
-    .clang-tidy
-    pybind11/include/**
-    pybind11/share/**
-    CMakeLists.txt
-
 
 [flake8]
-max-line-length = 99
+max-line-length = 120
 show_source = True
 exclude = .git, __pycache__, build, dist, docs, tools, venv
-ignore =
-    # required for pretty matrix formatting: multiple spaces after `,` and `[`
-    E201, E241, W504,
-    # camelcase 'cPickle' imported as lowercase 'pickle'
-    N813
-    # Black conflict
-    W503, E203
-
-[mypy]
-files = pybind11
-strict = True
+extend-ignore = E203, E722, B903, B950
+extend-select = B9
diff --git a/3rdparty/pybind11/setup.py b/3rdparty/pybind11/setup.py
index 3a0327982a..68573519c1 100644
--- a/3rdparty/pybind11/setup.py
+++ b/3rdparty/pybind11/setup.py
@@ -1,5 +1,4 @@
-#!/usr/bin/env python
-# -*- coding: utf-8 -*-
+#!/usr/bin/env python3
 
 # Setup script for PyPI; use CMakeFile.txt to build extension modules
 
@@ -10,87 +9,110 @@
 import string
 import subprocess
 import sys
-import tempfile
+from pathlib import Path
+from tempfile import TemporaryDirectory
+from typing import Dict, Iterator, List, Union
 
 import setuptools.command.sdist
 
-DIR = os.path.abspath(os.path.dirname(__file__))
+DIR = Path(__file__).parent.absolute()
 VERSION_REGEX = re.compile(
     r"^\s*#\s*define\s+PYBIND11_VERSION_([A-Z]+)\s+(.*)$", re.MULTILINE
 )
+VERSION_FILE = Path("pybind11/_version.py")
+COMMON_FILE = Path("include/pybind11/detail/common.h")
+
+
+def build_expected_version_hex(matches: Dict[str, str]) -> str:
+    patch_level_serial = matches["PATCH"]
+    serial = None
+    major = int(matches["MAJOR"])
+    minor = int(matches["MINOR"])
+    flds = patch_level_serial.split(".")
+    if flds:
+        patch = int(flds[0])
+        if len(flds) == 1:
+            level = "0"
+            serial = 0
+        elif len(flds) == 2:
+            level_serial = flds[1]
+            for level in ("a", "b", "c", "dev"):
+                if level_serial.startswith(level):
+                    serial = int(level_serial[len(level) :])
+                    break
+    if serial is None:
+        msg = f'Invalid PYBIND11_VERSION_PATCH: "{patch_level_serial}"'
+        raise RuntimeError(msg)
+    version_hex_str = f"{major:02x}{minor:02x}{patch:02x}{level[:1]}{serial:x}"
+    return f"0x{version_hex_str.upper()}"
+
 
 # PYBIND11_GLOBAL_SDIST will build a different sdist, with the python-headers
 # files, and the sys.prefix files (CMake and headers).
 
 global_sdist = os.environ.get("PYBIND11_GLOBAL_SDIST", False)
 
-setup_py = "tools/setup_global.py.in" if global_sdist else "tools/setup_main.py.in"
+setup_py = Path(
+    "tools/setup_global.py.in" if global_sdist else "tools/setup_main.py.in"
+)
 extra_cmd = 'cmdclass["sdist"] = SDist\n'
 
 to_src = (
-    ("pyproject.toml", "tools/pyproject.toml"),
-    ("setup.py", setup_py),
+    (Path("pyproject.toml"), Path("tools/pyproject.toml")),
+    (Path("setup.py"), setup_py),
 )
 
+
 # Read the listed version
-with open("pybind11/_version.py") as f:
-    code = compile(f.read(), "pybind11/_version.py", "exec")
-loc = {}
+loc: Dict[str, str] = {}
+code = compile(VERSION_FILE.read_text(encoding="utf-8"), "pybind11/_version.py", "exec")
 exec(code, loc)
 version = loc["__version__"]
 
 # Verify that the version matches the one in C++
-with open("include/pybind11/detail/common.h") as f:
-    matches = dict(VERSION_REGEX.findall(f.read()))
+matches = dict(VERSION_REGEX.findall(COMMON_FILE.read_text(encoding="utf8")))
 cpp_version = "{MAJOR}.{MINOR}.{PATCH}".format(**matches)
 if version != cpp_version:
-    msg = "Python version {} does not match C++ version {}!".format(
-        version, cpp_version
-    )
+    msg = f"Python version {version} does not match C++ version {cpp_version}!"
+    raise RuntimeError(msg)
+
+version_hex = matches.get("HEX", "MISSING")
+exp_version_hex = build_expected_version_hex(matches)
+if version_hex != exp_version_hex:
+    msg = f"PYBIND11_VERSION_HEX {version_hex} does not match expected value {exp_version_hex}!"
     raise RuntimeError(msg)
 
 
-def get_and_replace(filename, binary=False, **opts):
-    with open(filename, "rb" if binary else "r") as f:
-        contents = f.read()
-    # Replacement has to be done on text in Python 3 (both work in Python 2)
+# TODO: use literals & overload (typing extensions or Python 3.8)
+def get_and_replace(
+    filename: Path, binary: bool = False, **opts: str
+) -> Union[bytes, str]:
     if binary:
+        contents = filename.read_bytes()
         return string.Template(contents.decode()).substitute(opts).encode()
-    else:
-        return string.Template(contents).substitute(opts)
+
+    return string.Template(filename.read_text()).substitute(opts)
 
 
 # Use our input files instead when making the SDist (and anything that depends
 # on it, like a wheel)
-class SDist(setuptools.command.sdist.sdist):
-    def make_release_tree(self, base_dir, files):
-        setuptools.command.sdist.sdist.make_release_tree(self, base_dir, files)
+class SDist(setuptools.command.sdist.sdist):  # type: ignore[misc]
+    def make_release_tree(self, base_dir: str, files: List[str]) -> None:
+        super().make_release_tree(base_dir, files)
 
         for to, src in to_src:
             txt = get_and_replace(src, binary=True, version=version, extra_cmd="")
 
-            dest = os.path.join(base_dir, to)
+            dest = Path(base_dir) / to
 
             # This is normally linked, so unlink before writing!
-            os.unlink(dest)
-            with open(dest, "wb") as f:
-                f.write(txt)
-
-
-# Backport from Python 3
-@contextlib.contextmanager
-def TemporaryDirectory():  # noqa: N802
-    "Prepare a temporary directory, cleanup when done"
-    try:
-        tmpdir = tempfile.mkdtemp()
-        yield tmpdir
-    finally:
-        shutil.rmtree(tmpdir)
+            dest.unlink()
+            dest.write_bytes(txt)  # type: ignore[arg-type]
 
 
 # Remove the CMake install directory when done
 @contextlib.contextmanager
-def remove_output(*sources):
+def remove_output(*sources: str) -> Iterator[None]:
     try:
         yield
     finally:
@@ -105,10 +127,23 @@ def remove_output(*sources):
             "-DCMAKE_INSTALL_PREFIX=pybind11",
             "-DBUILD_TESTING=OFF",
             "-DPYBIND11_NOPYTHON=ON",
+            "-Dprefix_for_pc_file=${pcfiledir}/../../",
         ]
-        cmake_opts = dict(cwd=DIR, stdout=sys.stdout, stderr=sys.stderr)
-        subprocess.check_call(cmd, **cmake_opts)
-        subprocess.check_call(["cmake", "--install", tmpdir], **cmake_opts)
+        if "CMAKE_ARGS" in os.environ:
+            fcommand = [
+                c
+                for c in os.environ["CMAKE_ARGS"].split()
+                if "DCMAKE_INSTALL_PREFIX" not in c
+            ]
+            cmd += fcommand
+        subprocess.run(cmd, check=True, cwd=DIR, stdout=sys.stdout, stderr=sys.stderr)
+        subprocess.run(
+            ["cmake", "--install", tmpdir],
+            check=True,
+            cwd=DIR,
+            stdout=sys.stdout,
+            stderr=sys.stderr,
+        )
 
     txt = get_and_replace(setup_py, version=version, extra_cmd=extra_cmd)
     code = compile(txt, setup_py, "exec")
diff --git a/3rdparty/pybind11/tests/CMakeLists.txt b/3rdparty/pybind11/tests/CMakeLists.txt
index dae8b5ad43..7296cd1b81 100644
--- a/3rdparty/pybind11/tests/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/CMakeLists.txt
@@ -10,27 +10,34 @@ cmake_minimum_required(VERSION 3.4)
 # The `cmake_minimum_required(VERSION 3.4...3.18)` syntax does not work with
 # some versions of VS that have a patched CMake 3.11. This forces us to emulate
 # the behavior using the following workaround:
-if(${CMAKE_VERSION} VERSION_LESS 3.18)
+if(${CMAKE_VERSION} VERSION_LESS 3.21)
   cmake_policy(VERSION ${CMAKE_MAJOR_VERSION}.${CMAKE_MINOR_VERSION})
 else()
-  cmake_policy(VERSION 3.18)
+  cmake_policy(VERSION 3.21)
 endif()
 
 # Only needed for CMake < 3.5 support
 include(CMakeParseArguments)
 
-# Filter out items; print an optional message if any items filtered
+# Filter out items; print an optional message if any items filtered. This ignores extensions.
 #
 # Usage:
 #   pybind11_filter_tests(LISTNAME file1.cpp file2.cpp ... MESSAGE "")
 #
-macro(PYBIND11_FILTER_TESTS LISTNAME)
+macro(pybind11_filter_tests LISTNAME)
   cmake_parse_arguments(ARG "" "MESSAGE" "" ${ARGN})
   set(PYBIND11_FILTER_TESTS_FOUND OFF)
+  # Make a list of the test without any extensions, for easier filtering.
+  set(_TMP_ACTUAL_LIST "${${LISTNAME}};") # enforce ';' at the end to allow matching last item.
+  string(REGEX REPLACE "\\.[^.;]*;" ";" LIST_WITHOUT_EXTENSIONS "${_TMP_ACTUAL_LIST}")
   foreach(filename IN LISTS ARG_UNPARSED_ARGUMENTS)
-    list(FIND ${LISTNAME} ${filename} _FILE_FOUND)
+    string(REGEX REPLACE "\\.[^.]*$" "" filename_no_ext ${filename})
+    # Search in the list without extensions.
+    list(FIND LIST_WITHOUT_EXTENSIONS ${filename_no_ext} _FILE_FOUND)
     if(_FILE_FOUND GREATER -1)
-      list(REMOVE_AT ${LISTNAME} ${_FILE_FOUND})
+      list(REMOVE_AT ${LISTNAME} ${_FILE_FOUND}) # And remove from the list with extensions.
+      list(REMOVE_AT LIST_WITHOUT_EXTENSIONS ${_FILE_FOUND}
+      )# And our search list, to ensure it is in sync.
       set(PYBIND11_FILTER_TESTS_FOUND ON)
     endif()
   endforeach()
@@ -39,6 +46,26 @@ macro(PYBIND11_FILTER_TESTS LISTNAME)
   endif()
 endmacro()
 
+macro(possibly_uninitialized)
+  foreach(VARNAME ${ARGN})
+    if(NOT DEFINED "${VARNAME}")
+      set("${VARNAME}" "")
+    endif()
+  endforeach()
+endmacro()
+
+# Function to add additional targets if any of the provided tests are found.
+# Needles; Specifies the test names to look for.
+# Additions; Specifies the additional test targets to add when any of the needles are found.
+macro(tests_extra_targets needles additions)
+  # Add the index for this relation to the index extra targets map.
+  list(LENGTH PYBIND11_TEST_EXTRA_TARGETS PYBIND11_TEST_EXTRA_TARGETS_LEN)
+  list(APPEND PYBIND11_TEST_EXTRA_TARGETS ${PYBIND11_TEST_EXTRA_TARGETS_LEN})
+  # Add the test names to look for, and the associated test target additions.
+  set(PYBIND11_TEST_EXTRA_TARGETS_NEEDLES_${PYBIND11_TEST_EXTRA_TARGETS_LEN} ${needles})
+  set(PYBIND11_TEST_EXTRA_TARGETS_ADDITION_${PYBIND11_TEST_EXTRA_TARGETS_LEN} ${additions})
+endmacro()
+
 # New Python support
 if(DEFINED Python_EXECUTABLE)
   set(PYTHON_EXECUTABLE "${Python_EXECUTABLE}")
@@ -67,7 +94,7 @@ if(CMAKE_CURRENT_SOURCE_DIR STREQUAL CMAKE_SOURCE_DIR)
   find_package(pybind11 REQUIRED CONFIG)
 endif()
 
-if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
+if(NOT CMAKE_BUILD_TYPE AND NOT DEFINED CMAKE_CONFIGURATION_TYPES)
   message(STATUS "Setting tests build type to MinSizeRel as none was specified")
   set(CMAKE_BUILD_TYPE
       MinSizeRel
@@ -84,52 +111,67 @@ if(PYBIND11_CUDA_TESTS)
   set(CMAKE_CUDA_STANDARD_REQUIRED ON)
 endif()
 
-# Full set of test files (you can override these; see below)
+# Full set of test files (you can override these; see below, overrides ignore extension)
+# Any test that has no extension is both .py and .cpp, so 'foo' will add 'foo.cpp' and 'foo.py'.
+# Any test that has an extension is exclusively that and handled as such.
 set(PYBIND11_TEST_FILES
-    test_async.cpp
-    test_buffers.cpp
-    test_builtin_casters.cpp
-    test_call_policies.cpp
-    test_callbacks.cpp
-    test_chrono.cpp
-    test_class.cpp
-    test_constants_and_functions.cpp
-    test_copy_move.cpp
-    test_custom_type_casters.cpp
-    test_docstring_options.cpp
-    test_eigen.cpp
-    test_enum.cpp
-    test_eval.cpp
-    test_exceptions.cpp
-    test_factory_constructors.cpp
-    test_gil_scoped.cpp
-    test_iostream.cpp
-    test_kwargs_and_defaults.cpp
-    test_local_bindings.cpp
-    test_methods_and_attributes.cpp
-    test_modules.cpp
-    test_multiple_inheritance.cpp
-    test_numpy_array.cpp
-    test_numpy_dtypes.cpp
-    test_numpy_vectorize.cpp
-    test_opaque_types.cpp
-    test_operator_overloading.cpp
-    test_pickling.cpp
-    test_pytypes.cpp
-    test_sequences_and_iterators.cpp
-    test_smart_ptr.cpp
-    test_stl.cpp
-    test_stl_binders.cpp
-    test_tagbased_polymorphic.cpp
-    test_union.cpp
-    test_virtual_functions.cpp)
+    test_async
+    test_buffers
+    test_builtin_casters
+    test_call_policies
+    test_callbacks
+    test_chrono
+    test_class
+    test_const_name
+    test_constants_and_functions
+    test_copy_move
+    test_custom_type_casters
+    test_custom_type_setup
+    test_docstring_options
+    test_eigen
+    test_enum
+    test_eval
+    test_exceptions
+    test_factory_constructors
+    test_gil_scoped
+    test_iostream
+    test_kwargs_and_defaults
+    test_local_bindings
+    test_methods_and_attributes
+    test_modules
+    test_multiple_inheritance
+    test_numpy_array
+    test_numpy_dtypes
+    test_numpy_vectorize
+    test_opaque_types
+    test_operator_overloading
+    test_pickling
+    test_pytypes
+    test_sequences_and_iterators
+    test_smart_ptr
+    test_stl
+    test_stl_binders
+    test_tagbased_polymorphic
+    test_thread
+    test_union
+    test_virtual_functions)
 
 # Invoking cmake with something like:
 #     cmake -DPYBIND11_TEST_OVERRIDE="test_callbacks.cpp;test_pickling.cpp" ..
 # lets you override the tests that get compiled and run.  You can restore to all tests with:
 #     cmake -DPYBIND11_TEST_OVERRIDE= ..
 if(PYBIND11_TEST_OVERRIDE)
-  set(PYBIND11_TEST_FILES ${PYBIND11_TEST_OVERRIDE})
+  # Instead of doing a direct override here, we iterate over the overrides without extension and
+  # match them against entries from the PYBIND11_TEST_FILES, anything that not matches goes into the filter list.
+  string(REGEX REPLACE "\\.[^.;]*;" ";" TEST_OVERRIDE_NO_EXT "${PYBIND11_TEST_OVERRIDE};")
+  string(REGEX REPLACE "\\.[^.;]*;" ";" TEST_FILES_NO_EXT "${PYBIND11_TEST_FILES};")
+  # This allows the override to be done with extensions, preserving backwards compatibility.
+  foreach(test_name ${TEST_FILES_NO_EXT})
+    if(NOT ${test_name} IN_LIST TEST_OVERRIDE_NO_EXT
+    )# If not in the whitelist, add to be filtered out.
+      list(APPEND PYBIND11_TEST_FILTER ${test_name})
+    endif()
+  endforeach()
 endif()
 
 # You can also filter tests:
@@ -137,11 +179,6 @@ if(PYBIND11_TEST_FILTER)
   pybind11_filter_tests(PYBIND11_TEST_FILES ${PYBIND11_TEST_FILTER})
 endif()
 
-if(PYTHON_VERSION VERSION_LESS 3.5)
-  pybind11_filter_tests(PYBIND11_TEST_FILES test_async.cpp MESSAGE
-                        "Skipping test_async on Python 2")
-endif()
-
 # Skip tests for CUDA check:
 # /pybind11/tests/test_constants_and_functions.cpp(125):
 #   error: incompatible exception specifications
@@ -151,15 +188,47 @@ if(PYBIND11_CUDA_TESTS)
     "Skipping test_constants_and_functions due to incompatible exception specifications")
 endif()
 
-string(REPLACE ".cpp" ".py" PYBIND11_PYTEST_FILES "${PYBIND11_TEST_FILES}")
+# Now that the test filtering is complete, we need to split the list into the test for PYTEST
+# and the list for the cpp targets.
+set(PYBIND11_CPPTEST_FILES "")
+set(PYBIND11_PYTEST_FILES "")
+
+foreach(test_name ${PYBIND11_TEST_FILES})
+  if(test_name MATCHES "\\.py$") # Ends in .py, purely python test.
+    list(APPEND PYBIND11_PYTEST_FILES ${test_name})
+  elseif(test_name MATCHES "\\.cpp$") # Ends in .cpp, purely cpp test.
+    list(APPEND PYBIND11_CPPTEST_FILES ${test_name})
+  elseif(NOT test_name MATCHES "\\.") # No extension specified, assume both, add extension.
+    list(APPEND PYBIND11_PYTEST_FILES ${test_name}.py)
+    list(APPEND PYBIND11_CPPTEST_FILES ${test_name}.cpp)
+  else()
+    message(WARNING "Unhanded test extension in test: ${test_name}")
+  endif()
+endforeach()
+set(PYBIND11_TEST_FILES ${PYBIND11_CPPTEST_FILES})
+list(SORT PYBIND11_PYTEST_FILES)
 
 # Contains the set of test files that require pybind11_cross_module_tests to be
 # built; if none of these are built (i.e. because TEST_OVERRIDE is used and
 # doesn't include them) the second module doesn't get built.
-set(PYBIND11_CROSS_MODULE_TESTS test_exceptions.py test_local_bindings.py test_stl.py
-                                test_stl_binders.py)
+tests_extra_targets("test_exceptions.py;test_local_bindings.py;test_stl.py;test_stl_binders.py"
+                    "pybind11_cross_module_tests")
+
+# And add additional targets for other tests.
+tests_extra_targets("test_exceptions.py" "cross_module_interleaved_error_already_set")
+tests_extra_targets("test_gil_scoped.py" "cross_module_gil_utils")
 
-set(PYBIND11_CROSS_MODULE_GIL_TESTS test_gil_scoped.py)
+set(PYBIND11_EIGEN_REPO
+    "https://gitlab.com/libeigen/eigen.git"
+    CACHE STRING "Eigen repository to use for tests")
+# Always use a hash for reconfigure speed and security reasons
+# Include the version number for pretty printing (keep in sync)
+set(PYBIND11_EIGEN_VERSION_AND_HASH
+    "3.4.0;929bc0e191d0927b1735b9a1ddc0e8b77e3a25ec"
+    CACHE STRING "Eigen version to use for tests, format: VERSION;HASH")
+
+list(GET PYBIND11_EIGEN_VERSION_AND_HASH 0 PYBIND11_EIGEN_VERSION_STRING)
+list(GET PYBIND11_EIGEN_VERSION_AND_HASH 1 PYBIND11_EIGEN_VERSION_HASH)
 
 # Check if Eigen is available; if not, remove from PYBIND11_TEST_FILES (but
 # keep it in PYBIND11_PYTEST_FILES, so that we get the "eigen is not installed"
@@ -174,22 +243,26 @@ if(PYBIND11_TEST_FILES_EIGEN_I GREATER -1)
       message(FATAL_ERROR "CMake 3.11+ required when using DOWNLOAD_EIGEN")
     endif()
 
-    set(EIGEN3_VERSION_STRING "3.3.8")
-
     include(FetchContent)
     FetchContent_Declare(
       eigen
-      GIT_REPOSITORY https://gitlab.com/libeigen/eigen.git
-      GIT_TAG ${EIGEN3_VERSION_STRING})
+      GIT_REPOSITORY "${PYBIND11_EIGEN_REPO}"
+      GIT_TAG "${PYBIND11_EIGEN_VERSION_HASH}")
 
     FetchContent_GetProperties(eigen)
     if(NOT eigen_POPULATED)
-      message(STATUS "Downloading Eigen")
+      message(
+        STATUS
+          "Downloading Eigen ${PYBIND11_EIGEN_VERSION_STRING} (${PYBIND11_EIGEN_VERSION_HASH}) from ${PYBIND11_EIGEN_REPO}"
+      )
       FetchContent_Populate(eigen)
     endif()
 
     set(EIGEN3_INCLUDE_DIR ${eigen_SOURCE_DIR})
     set(EIGEN3_FOUND TRUE)
+    # When getting locally, the version is not visible from a superprojet,
+    # so just force it.
+    set(EIGEN3_VERSION "${PYBIND11_EIGEN_VERSION_STRING}")
 
   else()
     find_package(Eigen3 3.2.7 QUIET CONFIG)
@@ -217,7 +290,8 @@ if(PYBIND11_TEST_FILES_EIGEN_I GREATER -1)
     message(STATUS "Building tests with Eigen v${EIGEN3_VERSION}")
   else()
     list(REMOVE_AT PYBIND11_TEST_FILES ${PYBIND11_TEST_FILES_EIGEN_I})
-    message(STATUS "Building tests WITHOUT Eigen, use -DDOWNLOAD_EIGEN on CMake 3.11+ to download")
+    message(
+      STATUS "Building tests WITHOUT Eigen, use -DDOWNLOAD_EIGEN=ON on CMake 3.11+ to download")
   endif()
 endif()
 
@@ -238,10 +312,47 @@ if(Boost_FOUND)
   endif()
 endif()
 
+# Check if we need to add -lstdc++fs or -lc++fs or nothing
+if(DEFINED CMAKE_CXX_STANDARD AND CMAKE_CXX_STANDARD LESS 17)
+  set(STD_FS_NO_LIB_NEEDED TRUE)
+elseif(MSVC)
+  set(STD_FS_NO_LIB_NEEDED TRUE)
+else()
+  file(
+    WRITE ${CMAKE_CURRENT_BINARY_DIR}/main.cpp
+    "#include <filesystem>\nint main(int argc, char ** argv) {\n  std::filesystem::path p(argv[0]);\n  return p.string().length();\n}"
+  )
+  try_compile(
+    STD_FS_NO_LIB_NEEDED ${CMAKE_CURRENT_BINARY_DIR}
+    SOURCES ${CMAKE_CURRENT_BINARY_DIR}/main.cpp
+    COMPILE_DEFINITIONS -std=c++17)
+  try_compile(
+    STD_FS_NEEDS_STDCXXFS ${CMAKE_CURRENT_BINARY_DIR}
+    SOURCES ${CMAKE_CURRENT_BINARY_DIR}/main.cpp
+    COMPILE_DEFINITIONS -std=c++17
+    LINK_LIBRARIES stdc++fs)
+  try_compile(
+    STD_FS_NEEDS_CXXFS ${CMAKE_CURRENT_BINARY_DIR}
+    SOURCES ${CMAKE_CURRENT_BINARY_DIR}/main.cpp
+    COMPILE_DEFINITIONS -std=c++17
+    LINK_LIBRARIES c++fs)
+endif()
+
+if(${STD_FS_NEEDS_STDCXXFS})
+  set(STD_FS_LIB stdc++fs)
+elseif(${STD_FS_NEEDS_CXXFS})
+  set(STD_FS_LIB c++fs)
+elseif(${STD_FS_NO_LIB_NEEDED})
+  set(STD_FS_LIB "")
+else()
+  message(WARNING "Unknown C++17 compiler - not passing -lstdc++fs")
+  set(STD_FS_LIB "")
+endif()
+
 # Compile with compiler warnings turned on
 function(pybind11_enable_warnings target_name)
   if(MSVC)
-    target_compile_options(${target_name} PRIVATE /W4)
+    target_compile_options(${target_name} PRIVATE /W4 /wd4189)
   elseif(CMAKE_CXX_COMPILER_ID MATCHES "(GNU|Intel|Clang)" AND NOT PYBIND11_CUDA_TESTS)
     target_compile_options(
       ${target_name}
@@ -259,40 +370,35 @@ function(pybind11_enable_warnings target_name)
       target_compile_options(${target_name} PRIVATE /WX)
     elseif(PYBIND11_CUDA_TESTS)
       target_compile_options(${target_name} PRIVATE "SHELL:-Werror all-warnings")
-    elseif(CMAKE_CXX_COMPILER_ID MATCHES "(GNU|Intel|Clang)")
+    elseif(CMAKE_CXX_COMPILER_ID MATCHES "(GNU|Clang|IntelLLVM)")
       target_compile_options(${target_name} PRIVATE -Werror)
-    endif()
-  endif()
-
-  # Needs to be readded since the ordering requires these to be after the ones above
-  if(CMAKE_CXX_STANDARD
-     AND CMAKE_CXX_COMPILER_ID MATCHES "Clang"
-     AND PYTHON_VERSION VERSION_LESS 3.0)
-    if(CMAKE_CXX_STANDARD LESS 17)
-      target_compile_options(${target_name} PUBLIC -Wno-deprecated-register)
-    else()
-      target_compile_options(${target_name} PUBLIC -Wno-register)
+    elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Intel")
+      if(CMAKE_CXX_STANDARD EQUAL 17) # See PR #3570
+        target_compile_options(${target_name} PRIVATE -Wno-conversion)
+      endif()
+      target_compile_options(
+        ${target_name}
+        PRIVATE
+          -Werror-all
+          # "Inlining inhibited by limit max-size", "Inlining inhibited by limit max-total-size"
+          -diag-disable 11074,11076)
     endif()
   endif()
 endfunction()
 
 set(test_targets pybind11_tests)
 
-# Build pybind11_cross_module_tests if any test_whatever.py are being built that require it
-foreach(t ${PYBIND11_CROSS_MODULE_TESTS})
-  list(FIND PYBIND11_PYTEST_FILES ${t} i)
-  if(i GREATER -1)
-    list(APPEND test_targets pybind11_cross_module_tests)
-    break()
-  endif()
-endforeach()
-
-foreach(t ${PYBIND11_CROSS_MODULE_GIL_TESTS})
-  list(FIND PYBIND11_PYTEST_FILES ${t} i)
-  if(i GREATER -1)
-    list(APPEND test_targets cross_module_gil_utils)
-    break()
-  endif()
+# Check if any tests need extra targets by iterating through the mappings registered.
+foreach(i ${PYBIND11_TEST_EXTRA_TARGETS})
+  foreach(needle ${PYBIND11_TEST_EXTRA_TARGETS_NEEDLES_${i}})
+    if(needle IN_LIST PYBIND11_PYTEST_FILES)
+      # Add all the additional targets to the test list. List join in newer cmake.
+      foreach(extra_target ${PYBIND11_TEST_EXTRA_TARGETS_ADDITION_${i}})
+        list(APPEND test_targets ${extra_target})
+      endforeach()
+      break() # Breaks out of the needle search, continues with the next mapping.
+    endif()
+  endforeach()
 endforeach()
 
 # Support CUDA testing by forcing the target file to compile with NVCC
@@ -341,18 +447,31 @@ foreach(target ${test_targets})
     target_compile_definitions(${target} PRIVATE -DPYBIND11_TEST_BOOST)
   endif()
 
+  target_link_libraries(${target} PRIVATE ${STD_FS_LIB})
+
   # Always write the output file directly into the 'tests' directory (even on MSVC)
   if(NOT CMAKE_LIBRARY_OUTPUT_DIRECTORY)
     set_target_properties(${target} PROPERTIES LIBRARY_OUTPUT_DIRECTORY
                                                "${CMAKE_CURRENT_BINARY_DIR}")
-    foreach(config ${CMAKE_CONFIGURATION_TYPES})
-      string(TOUPPER ${config} config)
-      set_target_properties(${target} PROPERTIES LIBRARY_OUTPUT_DIRECTORY_${config}
-                                                 "${CMAKE_CURRENT_BINARY_DIR}")
-    endforeach()
+
+    if(DEFINED CMAKE_CONFIGURATION_TYPES)
+      foreach(config ${CMAKE_CONFIGURATION_TYPES})
+        string(TOUPPER ${config} config)
+        set_target_properties(${target} PROPERTIES LIBRARY_OUTPUT_DIRECTORY_${config}
+                                                   "${CMAKE_CURRENT_BINARY_DIR}")
+      endforeach()
+    endif()
   endif()
 endforeach()
 
+# Provide nice organisation in IDEs
+if(NOT CMAKE_VERSION VERSION_LESS 3.8)
+  source_group(
+    TREE "${CMAKE_CURRENT_SOURCE_DIR}/../include"
+    PREFIX "Header Files"
+    FILES ${PYBIND11_HEADERS})
+endif()
+
 # Make sure pytest is found or produce a warning
 pybind11_find_import(pytest VERSION 3.1)
 
@@ -370,12 +489,17 @@ endif()
 string(REPLACE "test_" "${CMAKE_CURRENT_SOURCE_DIR}/test_" PYBIND11_ABS_PYTEST_FILES
                "${PYBIND11_PYTEST_FILES}")
 
+set(PYBIND11_TEST_PREFIX_COMMAND
+    ""
+    CACHE STRING "Put this before pytest, use for checkers and such")
+
 # A single command to compile and run the tests
 add_custom_target(
   pytest
-  COMMAND ${PYTHON_EXECUTABLE} -m pytest ${PYBIND11_ABS_PYTEST_FILES}
+  COMMAND ${PYBIND11_TEST_PREFIX_COMMAND} ${PYTHON_EXECUTABLE} -m pytest
+          ${PYBIND11_ABS_PYTEST_FILES}
   DEPENDS ${test_targets}
-  WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
+  WORKING_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}"
   USES_TERMINAL)
 
 if(PYBIND11_TEST_OVERRIDE)
@@ -386,6 +510,27 @@ if(PYBIND11_TEST_OVERRIDE)
             "Note: not all tests run: -DPYBIND11_TEST_OVERRIDE is in effect")
 endif()
 
+# cmake-format: off
+add_custom_target(
+  memcheck
+  COMMAND
+    PYTHONMALLOC=malloc
+    valgrind
+    --leak-check=full
+    --show-leak-kinds=definite,indirect
+    --errors-for-leak-kinds=definite,indirect
+    --error-exitcode=1
+    --read-var-info=yes
+    --track-origins=yes
+    --suppressions="${CMAKE_CURRENT_SOURCE_DIR}/valgrind-python.supp"
+    --suppressions="${CMAKE_CURRENT_SOURCE_DIR}/valgrind-numpy-scipy.supp"
+    --gen-suppressions=all
+    ${PYTHON_EXECUTABLE} -m pytest ${PYBIND11_ABS_PYTEST_FILES}
+  DEPENDS ${test_targets}
+  WORKING_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}"
+  USES_TERMINAL)
+# cmake-format: on
+
 # Add a check target to run all the tests, starting with pytest (we add dependencies to this below)
 add_custom_target(check DEPENDS pytest)
 
diff --git a/3rdparty/pybind11/tests/conftest.py b/3rdparty/pybind11/tests/conftest.py
index 362eb80691..02ce263afc 100644
--- a/3rdparty/pybind11/tests/conftest.py
+++ b/3rdparty/pybind11/tests/conftest.py
@@ -1,8 +1,7 @@
-# -*- coding: utf-8 -*-
 """pytest configuration
 
 Extends output capture as needed by pybind11: ignore constructors, optional unordered lines.
-Adds docstring and exceptions message sanitizers: ignore Python 2 vs 3 differences.
+Adds docstring and exceptions message sanitizers.
 """
 
 import contextlib
@@ -13,19 +12,14 @@
 
 import pytest
 
-import env
-
 # Early diagnostic for failed imports
-import pybind11_tests  # noqa: F401
+import pybind11_tests
 
-_unicode_marker = re.compile(r"u(\'[^\']*\')")
 _long_marker = re.compile(r"([0-9])L")
 _hexadecimal = re.compile(r"0x[0-9a-fA-F]+")
 
 # Avoid collecting Python3 only files
 collect_ignore = []
-if env.PY2:
-    collect_ignore.append("test_async.py")
 
 
 def _strip_and_dedent(s):
@@ -45,7 +39,7 @@ def _make_explanation(a, b):
     ]
 
 
-class Output(object):
+class Output:
     """Basic output post-processing and comparison"""
 
     def __init__(self, string):
@@ -83,7 +77,7 @@ def __eq__(self, other):
             return False
 
 
-class Capture(object):
+class Capture:
     def __init__(self, capfd):
         self.capfd = capfd
         self.out = ""
@@ -126,7 +120,7 @@ def capture(capsys):
     return Capture(capsys)
 
 
-class SanitizedString(object):
+class SanitizedString:
     def __init__(self, sanitizer):
         self.sanitizer = sanitizer
         self.string = ""
@@ -149,9 +143,7 @@ def __eq__(self, other):
 def _sanitize_general(s):
     s = s.strip()
     s = s.replace("pybind11_tests.", "m.")
-    s = s.replace("unicode", "str")
     s = _long_marker.sub(r"\1", s)
-    s = _unicode_marker.sub(r"\1", s)
     return s
 
 
@@ -206,3 +198,16 @@ def gc_collect():
 def pytest_configure():
     pytest.suppress = suppress
     pytest.gc_collect = gc_collect
+
+
+def pytest_report_header(config):
+    del config  # Unused.
+    assert (
+        pybind11_tests.compiler_info is not None
+    ), "Please update pybind11_tests.cpp if this assert fails."
+    return (
+        "C++ Info:"
+        f" {pybind11_tests.compiler_info}"
+        f" {pybind11_tests.cpp_std}"
+        f" {pybind11_tests.PYBIND11_INTERNALS_ID}"
+    )
diff --git a/3rdparty/pybind11/tests/constructor_stats.h b/3rdparty/pybind11/tests/constructor_stats.h
index 805968a09b..937f6c233b 100644
--- a/3rdparty/pybind11/tests/constructor_stats.h
+++ b/3rdparty/pybind11/tests/constructor_stats.h
@@ -56,7 +56,8 @@ from the ConstructorStats instance `.values()` method.
 In some cases, when you need to track instances of a C++ class not registered with pybind11, you
 need to add a function returning the ConstructorStats for the C++ class; this can be done with:
 
-    m.def("get_special_cstats", &ConstructorStats::get<SpecialClass>, py::return_value_policy::reference)
+    m.def("get_special_cstats", &ConstructorStats::get<SpecialClass>,
+py::return_value_policy::reference)
 
 Finally, you can suppress the output messages, but keep the constructor tracking (for
 inspection/testing in python) by using the functions with `print_` replaced with `track_` (e.g.
@@ -65,15 +66,18 @@ inspection/testing in python) by using the functions with `print_` replaced with
 */
 
 #include "pybind11_tests.h"
-#include <unordered_map>
+
 #include <list>
-#include <typeindex>
 #include <sstream>
+#include <typeindex>
+#include <unordered_map>
 
 class ConstructorStats {
 protected:
-    std::unordered_map<void*, int> _instances; // Need a map rather than set because members can shared address with parents
-    std::list<std::string> _values; // Used to track values (e.g. of value constructors)
+    std::unordered_map<void *, int> _instances; // Need a map rather than set because members can
+                                                // shared address with parents
+    std::list<std::string> _values;             // Used to track values
+                                                // (e.g. of value constructors)
 public:
     int default_constructions = 0;
     int copy_constructions = 0;
@@ -96,26 +100,26 @@ class ConstructorStats {
         default_constructions++;
     }
 
-    void created(void *inst) {
-        ++_instances[inst];
-    }
+    void created(void *inst) { ++_instances[inst]; }
 
     void destroyed(void *inst) {
-        if (--_instances[inst] < 0)
+        if (--_instances[inst] < 0) {
             throw std::runtime_error("cstats.destroyed() called with unknown "
                                      "instance; potential double-destruction "
                                      "or a missing cstats.created()");
+        }
     }
 
     static void gc() {
         // Force garbage collection to ensure any pending destructors are invoked:
 #if defined(PYPY_VERSION)
         PyObject *globals = PyEval_GetGlobals();
-        PyObject *result = PyRun_String(
-            "import gc\n"
-            "for i in range(2):"
-            "    gc.collect()\n",
-            Py_file_input, globals, globals);
+        PyObject *result = PyRun_String("import gc\n"
+                                        "for i in range(2):\n"
+                                        "    gc.collect()\n",
+                                        Py_file_input,
+                                        globals,
+                                        globals);
         if (result == nullptr)
             throw py::error_already_set();
         Py_DECREF(result);
@@ -127,15 +131,18 @@ class ConstructorStats {
     int alive() {
         gc();
         int total = 0;
-        for (const auto &p : _instances)
-            if (p.second > 0)
+        for (const auto &p : _instances) {
+            if (p.second > 0) {
                 total += p.second;
+            }
+        }
         return total;
     }
 
     void value() {} // Recursion terminator
     // Takes one or more values, converts them to strings, then stores them.
-    template <typename T, typename... Tmore> void value(const T &v, Tmore &&...args) {
+    template <typename T, typename... Tmore>
+    void value(const T &v, Tmore &&...args) {
         std::ostringstream oss;
         oss << v;
         _values.push_back(oss.str());
@@ -145,19 +152,22 @@ class ConstructorStats {
     // Move out stored values
     py::list values() {
         py::list l;
-        for (const auto &v : _values) l.append(py::cast(v));
+        for (const auto &v : _values) {
+            l.append(py::cast(v));
+        }
         _values.clear();
         return l;
     }
 
     // Gets constructor stats from a C++ type index
-    static ConstructorStats& get(std::type_index type) {
+    static ConstructorStats &get(std::type_index type) {
         static std::unordered_map<std::type_index, ConstructorStats> all_cstats;
         return all_cstats[type];
     }
 
     // Gets constructor stats from a C++ type
-    template <typename T> static ConstructorStats& get() {
+    template <typename T>
+    static ConstructorStats &get() {
 #if defined(PYPY_VERSION)
         gc();
 #endif
@@ -165,11 +175,12 @@ class ConstructorStats {
     }
 
     // Gets constructor stats from a Python class
-    static ConstructorStats& get(py::object class_) {
+    static ConstructorStats &get(py::object class_) {
         auto &internals = py::detail::get_internals();
         const std::type_index *t1 = nullptr, *t2 = nullptr;
         try {
-            auto *type_info = internals.registered_types_py.at((PyTypeObject *) class_.ptr()).at(0);
+            auto *type_info
+                = internals.registered_types_py.at((PyTypeObject *) class_.ptr()).at(0);
             for (auto &p : internals.registered_types_cpp) {
                 if (p.second == type_info) {
                     if (t1) {
@@ -179,17 +190,23 @@ class ConstructorStats {
                     t1 = &p.first;
                 }
             }
+        } catch (const std::out_of_range &) {
+        }
+        if (!t1) {
+            throw std::runtime_error("Unknown class passed to ConstructorStats::get()");
         }
-        catch (const std::out_of_range&) {}
-        if (!t1) throw std::runtime_error("Unknown class passed to ConstructorStats::get()");
         auto &cs1 = get(*t1);
-        // If we have both a t1 and t2 match, one is probably the trampoline class; return whichever
-        // has more constructions (typically one or the other will be 0)
+        // If we have both a t1 and t2 match, one is probably the trampoline class; return
+        // whichever has more constructions (typically one or the other will be 0)
         if (t2) {
             auto &cs2 = get(*t2);
-            int cs1_total = cs1.default_constructions + cs1.copy_constructions + cs1.move_constructions + (int) cs1._values.size();
-            int cs2_total = cs2.default_constructions + cs2.copy_constructions + cs2.move_constructions + (int) cs2._values.size();
-            if (cs2_total > cs1_total) return cs2;
+            int cs1_total = cs1.default_constructions + cs1.copy_constructions
+                            + cs1.move_constructions + (int) cs1._values.size();
+            int cs2_total = cs2.default_constructions + cs2.copy_constructions
+                            + cs2.move_constructions + (int) cs2._values.size();
+            if (cs2_total > cs1_total) {
+                return cs2;
+            }
         }
         return cs1;
     }
@@ -198,78 +215,108 @@ class ConstructorStats {
 // To track construction/destruction, you need to call these methods from the various
 // constructors/operators.  The ones that take extra values record the given values in the
 // constructor stats values for later inspection.
-template <class T> void track_copy_created(T *inst) { ConstructorStats::get<T>().copy_created(inst); }
-template <class T> void track_move_created(T *inst) { ConstructorStats::get<T>().move_created(inst); }
-template <class T, typename... Values> void track_copy_assigned(T *, Values &&...values) {
+template <class T>
+void track_copy_created(T *inst) {
+    ConstructorStats::get<T>().copy_created(inst);
+}
+template <class T>
+void track_move_created(T *inst) {
+    ConstructorStats::get<T>().move_created(inst);
+}
+template <class T, typename... Values>
+void track_copy_assigned(T *, Values &&...values) {
     auto &cst = ConstructorStats::get<T>();
     cst.copy_assignments++;
     cst.value(std::forward<Values>(values)...);
 }
-template <class T, typename... Values> void track_move_assigned(T *, Values &&...values) {
+template <class T, typename... Values>
+void track_move_assigned(T *, Values &&...values) {
     auto &cst = ConstructorStats::get<T>();
     cst.move_assignments++;
     cst.value(std::forward<Values>(values)...);
 }
-template <class T, typename... Values> void track_default_created(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void track_default_created(T *inst, Values &&...values) {
     auto &cst = ConstructorStats::get<T>();
     cst.default_created(inst);
     cst.value(std::forward<Values>(values)...);
 }
-template <class T, typename... Values> void track_created(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void track_created(T *inst, Values &&...values) {
     auto &cst = ConstructorStats::get<T>();
     cst.created(inst);
     cst.value(std::forward<Values>(values)...);
 }
-template <class T, typename... Values> void track_destroyed(T *inst) {
+template <class T, typename... Values>
+void track_destroyed(T *inst) {
     ConstructorStats::get<T>().destroyed(inst);
 }
-template <class T, typename... Values> void track_values(T *, Values &&...values) {
+template <class T, typename... Values>
+void track_values(T *, Values &&...values) {
     ConstructorStats::get<T>().value(std::forward<Values>(values)...);
 }
 
 /// Don't cast pointers to Python, print them as strings
 inline const char *format_ptrs(const char *p) { return p; }
 template <typename T>
-py::str format_ptrs(T *p) { return "{:#x}"_s.format(reinterpret_cast<std::uintptr_t>(p)); }
+py::str format_ptrs(T *p) {
+    return "{:#x}"_s.format(reinterpret_cast<std::uintptr_t>(p));
+}
 template <typename T>
-auto format_ptrs(T &&x) -> decltype(std::forward<T>(x)) { return std::forward<T>(x); }
+auto format_ptrs(T &&x) -> decltype(std::forward<T>(x)) {
+    return std::forward<T>(x);
+}
 
 template <class T, typename... Output>
 void print_constr_details(T *inst, const std::string &action, Output &&...output) {
-    py::print("###", py::type_id<T>(), "@", format_ptrs(inst), action,
+    py::print("###",
+              py::type_id<T>(),
+              "@",
+              format_ptrs(inst),
+              action,
               format_ptrs(std::forward<Output>(output))...);
 }
 
 // Verbose versions of the above:
-template <class T, typename... Values> void print_copy_created(T *inst, Values &&...values) { // NB: this prints, but doesn't store, given values
+template <class T, typename... Values>
+void print_copy_created(T *inst,
+                        Values &&...values) { // NB: this prints, but doesn't store, given values
     print_constr_details(inst, "created via copy constructor", values...);
     track_copy_created(inst);
 }
-template <class T, typename... Values> void print_move_created(T *inst, Values &&...values) { // NB: this prints, but doesn't store, given values
+template <class T, typename... Values>
+void print_move_created(T *inst,
+                        Values &&...values) { // NB: this prints, but doesn't store, given values
     print_constr_details(inst, "created via move constructor", values...);
     track_move_created(inst);
 }
-template <class T, typename... Values> void print_copy_assigned(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void print_copy_assigned(T *inst, Values &&...values) {
     print_constr_details(inst, "assigned via copy assignment", values...);
     track_copy_assigned(inst, values...);
 }
-template <class T, typename... Values> void print_move_assigned(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void print_move_assigned(T *inst, Values &&...values) {
     print_constr_details(inst, "assigned via move assignment", values...);
     track_move_assigned(inst, values...);
 }
-template <class T, typename... Values> void print_default_created(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void print_default_created(T *inst, Values &&...values) {
     print_constr_details(inst, "created via default constructor", values...);
     track_default_created(inst, values...);
 }
-template <class T, typename... Values> void print_created(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void print_created(T *inst, Values &&...values) {
     print_constr_details(inst, "created", values...);
     track_created(inst, values...);
 }
-template <class T, typename... Values> void print_destroyed(T *inst, Values &&...values) { // Prints but doesn't store given values
+template <class T, typename... Values>
+void print_destroyed(T *inst, Values &&...values) { // Prints but doesn't store given values
     print_constr_details(inst, "destroyed", values...);
     track_destroyed(inst);
 }
-template <class T, typename... Values> void print_values(T *inst, Values &&...values) {
+template <class T, typename... Values>
+void print_values(T *inst, Values &&...values) {
     print_constr_details(inst, ":", values...);
     track_values(inst, values...);
 }
diff --git a/3rdparty/pybind11/tests/cross_module_gil_utils.cpp b/3rdparty/pybind11/tests/cross_module_gil_utils.cpp
index 07db9f6e48..1436c35d6e 100644
--- a/3rdparty/pybind11/tests/cross_module_gil_utils.cpp
+++ b/3rdparty/pybind11/tests/cross_module_gil_utils.cpp
@@ -7,6 +7,7 @@
     BSD-style license that can be found in the LICENSE file.
 */
 #include <pybind11/pybind11.h>
+
 #include <cstdint>
 
 // This file mimics a DSO that makes pybind11 calls but does not define a
@@ -24,50 +25,21 @@ void gil_acquire() { py::gil_scoped_acquire gil; }
 
 constexpr char kModuleName[] = "cross_module_gil_utils";
 
-#if PY_MAJOR_VERSION >= 3
 struct PyModuleDef moduledef = {
-    PyModuleDef_HEAD_INIT,
-    kModuleName,
-    NULL,
-    0,
-    NULL,
-    NULL,
-    NULL,
-    NULL,
-    NULL
-};
-#else
-PyMethodDef module_methods[] = {
-    {NULL, NULL, 0, NULL}
-};
-#endif
+    PyModuleDef_HEAD_INIT, kModuleName, nullptr, 0, nullptr, nullptr, nullptr, nullptr, nullptr};
 
-}  // namespace
+} // namespace
 
-extern "C" PYBIND11_EXPORT
-#if PY_MAJOR_VERSION >= 3
-PyObject* PyInit_cross_module_gil_utils()
-#else
-void initcross_module_gil_utils()
-#endif
-{
+extern "C" PYBIND11_EXPORT PyObject *PyInit_cross_module_gil_utils() {
 
-    PyObject* m =
-#if PY_MAJOR_VERSION >= 3
-        PyModule_Create(&moduledef);
-#else
-        Py_InitModule(kModuleName, module_methods);
-#endif
+    PyObject *m = PyModule_Create(&moduledef);
 
-    if (m != NULL) {
-        static_assert(
-            sizeof(&gil_acquire) == sizeof(void*),
-            "Function pointer must have the same size as void*");
-        PyModule_AddObject(m, "gil_acquire_funcaddr",
-                           PyLong_FromVoidPtr(reinterpret_cast<void*>(&gil_acquire)));
+    if (m != nullptr) {
+        static_assert(sizeof(&gil_acquire) == sizeof(void *),
+                      "Function pointer must have the same size as void*");
+        PyModule_AddObject(
+            m, "gil_acquire_funcaddr", PyLong_FromVoidPtr(reinterpret_cast<void *>(&gil_acquire)));
     }
 
-#if PY_MAJOR_VERSION >= 3
     return m;
-#endif
 }
diff --git a/3rdparty/pybind11/tests/cross_module_interleaved_error_already_set.cpp b/3rdparty/pybind11/tests/cross_module_interleaved_error_already_set.cpp
new file mode 100644
index 0000000000..fdd9939e45
--- /dev/null
+++ b/3rdparty/pybind11/tests/cross_module_interleaved_error_already_set.cpp
@@ -0,0 +1,51 @@
+/*
+    Copyright (c) 2022 Google LLC
+
+    All rights reserved. Use of this source code is governed by a
+    BSD-style license that can be found in the LICENSE file.
+*/
+
+#include <pybind11/pybind11.h>
+
+// This file mimics a DSO that makes pybind11 calls but does not define a PYBIND11_MODULE,
+// so that the first call of cross_module_error_already_set() triggers the first call of
+// pybind11::detail::get_internals().
+
+namespace {
+
+namespace py = pybind11;
+
+void interleaved_error_already_set() {
+    PyErr_SetString(PyExc_RuntimeError, "1st error.");
+    try {
+        throw py::error_already_set();
+    } catch (const py::error_already_set &) {
+        // The 2nd error could be conditional in a real application.
+        PyErr_SetString(PyExc_RuntimeError, "2nd error.");
+    } // Here the 1st error is destroyed before the 2nd error is fetched.
+    // The error_already_set dtor triggers a pybind11::detail::get_internals()
+    // call via pybind11::gil_scoped_acquire.
+    if (PyErr_Occurred()) {
+        throw py::error_already_set();
+    }
+}
+
+constexpr char kModuleName[] = "cross_module_interleaved_error_already_set";
+
+struct PyModuleDef moduledef = {
+    PyModuleDef_HEAD_INIT, kModuleName, nullptr, 0, nullptr, nullptr, nullptr, nullptr, nullptr};
+
+} // namespace
+
+extern "C" PYBIND11_EXPORT PyObject *PyInit_cross_module_interleaved_error_already_set() {
+    PyObject *m = PyModule_Create(&moduledef);
+    if (m != nullptr) {
+        static_assert(sizeof(&interleaved_error_already_set) == sizeof(void *),
+                      "Function pointer must have the same size as void *");
+        PyModule_AddObject(
+            m,
+            "funcaddr",
+            PyLong_FromVoidPtr(reinterpret_cast<void *>(&interleaved_error_already_set)));
+    }
+    return m;
+}
diff --git a/3rdparty/pybind11/tests/env.py b/3rdparty/pybind11/tests/env.py
index 5cded44127..0345df65dc 100644
--- a/3rdparty/pybind11/tests/env.py
+++ b/3rdparty/pybind11/tests/env.py
@@ -1,7 +1,8 @@
-# -*- coding: utf-8 -*-
 import platform
 import sys
 
+import pytest
+
 LINUX = sys.platform.startswith("linux")
 MACOS = sys.platform.startswith("darwin")
 WIN = sys.platform.startswith("win32") or sys.platform.startswith("cygwin")
@@ -9,6 +10,19 @@
 CPYTHON = platform.python_implementation() == "CPython"
 PYPY = platform.python_implementation() == "PyPy"
 
-PY2 = sys.version_info.major == 2
 
-PY = sys.version_info
+def deprecated_call():
+    """
+    pytest.deprecated_call() seems broken in pytest<3.9.x; concretely, it
+    doesn't work on CPython 3.8.0 with pytest==3.3.2 on Ubuntu 18.04 (#2922).
+
+    This is a narrowed reimplementation of the following PR :(
+    https://github.com/pytest-dev/pytest/pull/4104
+    """
+    # TODO: Remove this when testing requires pytest>=3.9.
+    pieces = pytest.__version__.split(".")
+    pytest_major_minor = (int(pieces[0]), int(pieces[1]))
+    if pytest_major_minor < (3, 9):
+        return pytest.warns((DeprecationWarning, PendingDeprecationWarning))
+    else:
+        return pytest.deprecated_call()
diff --git a/3rdparty/pybind11/tests/extra_python_package/test_files.py b/3rdparty/pybind11/tests/extra_python_package/test_files.py
index cbd4bff1bc..8e1ddd8508 100644
--- a/3rdparty/pybind11/tests/extra_python_package/test_files.py
+++ b/3rdparty/pybind11/tests/extra_python_package/test_files.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import contextlib
 import os
 import string
@@ -13,6 +12,16 @@
 DIR = os.path.abspath(os.path.dirname(__file__))
 MAIN_DIR = os.path.dirname(os.path.dirname(DIR))
 
+PKGCONFIG = """\
+prefix=${{pcfiledir}}/../../
+includedir=${{prefix}}/include
+
+Name: pybind11
+Description: Seamless operability between C++11 and Python
+Version: {VERSION}
+Cflags: -I${{includedir}}
+"""
+
 
 main_headers = {
     "include/pybind11/attr.h",
@@ -25,6 +34,7 @@
     "include/pybind11/embed.h",
     "include/pybind11/eval.h",
     "include/pybind11/functional.h",
+    "include/pybind11/gil.h",
     "include/pybind11/iostream.h",
     "include/pybind11/numpy.h",
     "include/pybind11/operators.h",
@@ -41,9 +51,14 @@
     "include/pybind11/detail/descr.h",
     "include/pybind11/detail/init.h",
     "include/pybind11/detail/internals.h",
+    "include/pybind11/detail/type_caster_base.h",
     "include/pybind11/detail/typeid.h",
 }
 
+stl_headers = {
+    "include/pybind11/stl/filesystem.h",
+}
+
 cmake_files = {
     "share/cmake/pybind11/FindPythonLibsNew.cmake",
     "share/cmake/pybind11/pybind11Common.cmake",
@@ -54,19 +69,21 @@
     "share/cmake/pybind11/pybind11Tools.cmake",
 }
 
+pkgconfig_files = {
+    "share/pkgconfig/pybind11.pc",
+}
+
 py_files = {
     "__init__.py",
     "__main__.py",
     "_version.py",
-    "_version.pyi",
     "commands.py",
     "py.typed",
     "setup_helpers.py",
-    "setup_helpers.pyi",
 }
 
-headers = main_headers | detail_headers
-src_files = headers | cmake_files
+headers = main_headers | detail_headers | stl_headers
+src_files = headers | cmake_files | pkgconfig_files
 all_files = src_files | py_files
 
 
@@ -75,9 +92,11 @@
     "pybind11/include",
     "pybind11/include/pybind11",
     "pybind11/include/pybind11/detail",
+    "pybind11/include/pybind11/stl",
     "pybind11/share",
     "pybind11/share/cmake",
     "pybind11/share/cmake/pybind11",
+    "pybind11/share/pkgconfig",
     "pyproject.toml",
     "setup.cfg",
     "setup.py",
@@ -97,105 +116,106 @@
 }
 
 
+def read_tz_file(tar: tarfile.TarFile, name: str) -> bytes:
+    start = tar.getnames()[0] + "/"
+    inner_file = tar.extractfile(tar.getmember(f"{start}{name}"))
+    assert inner_file
+    with contextlib.closing(inner_file) as f:
+        return f.read()
+
+
+def normalize_line_endings(value: bytes) -> bytes:
+    return value.replace(os.linesep.encode("utf-8"), b"\n")
+
+
 def test_build_sdist(monkeypatch, tmpdir):
 
     monkeypatch.chdir(MAIN_DIR)
 
-    out = subprocess.check_output(
-        [
-            sys.executable,
-            "setup.py",
-            "sdist",
-            "--formats=tar",
-            "--dist-dir",
-            str(tmpdir),
-        ]
+    subprocess.run(
+        [sys.executable, "-m", "build", "--sdist", f"--outdir={tmpdir}"], check=True
     )
-    if hasattr(out, "decode"):
-        out = out.decode()
 
-    (sdist,) = tmpdir.visit("*.tar")
+    (sdist,) = tmpdir.visit("*.tar.gz")
 
-    with tarfile.open(str(sdist)) as tar:
+    with tarfile.open(str(sdist), "r:gz") as tar:
         start = tar.getnames()[0] + "/"
         version = start[9:-1]
-        simpler = set(n.split("/", 1)[-1] for n in tar.getnames()[1:])
+        simpler = {n.split("/", 1)[-1] for n in tar.getnames()[1:]}
 
-        with contextlib.closing(
-            tar.extractfile(tar.getmember(start + "setup.py"))
-        ) as f:
-            setup_py = f.read()
+        setup_py = read_tz_file(tar, "setup.py")
+        pyproject_toml = read_tz_file(tar, "pyproject.toml")
+        pkgconfig = read_tz_file(tar, "pybind11/share/pkgconfig/pybind11.pc")
+        cmake_cfg = read_tz_file(
+            tar, "pybind11/share/cmake/pybind11/pybind11Config.cmake"
+        )
 
-        with contextlib.closing(
-            tar.extractfile(tar.getmember(start + "pyproject.toml"))
-        ) as f:
-            pyproject_toml = f.read()
+    assert (
+        'set(pybind11_INCLUDE_DIR "${PACKAGE_PREFIX_DIR}/include")'
+        in cmake_cfg.decode("utf-8")
+    )
 
-    files = set("pybind11/{}".format(n) for n in all_files)
+    files = {f"pybind11/{n}" for n in all_files}
     files |= sdist_files
-    files |= set("pybind11{}".format(n) for n in local_sdist_files)
+    files |= {f"pybind11{n}" for n in local_sdist_files}
     files.add("pybind11.egg-info/entry_points.txt")
     files.add("pybind11.egg-info/requires.txt")
     assert simpler == files
 
     with open(os.path.join(MAIN_DIR, "tools", "setup_main.py.in"), "rb") as f:
         contents = (
-            string.Template(f.read().decode())
+            string.Template(f.read().decode("utf-8"))
             .substitute(version=version, extra_cmd="")
-            .encode()
+            .encode("utf-8")
         )
-        assert setup_py == contents
+    assert setup_py == contents
 
     with open(os.path.join(MAIN_DIR, "tools", "pyproject.toml"), "rb") as f:
         contents = f.read()
-        assert pyproject_toml == contents
+    assert pyproject_toml == contents
+
+    simple_version = ".".join(version.split(".")[:3])
+    pkgconfig_expected = PKGCONFIG.format(VERSION=simple_version).encode("utf-8")
+    assert normalize_line_endings(pkgconfig) == pkgconfig_expected
 
 
 def test_build_global_dist(monkeypatch, tmpdir):
 
     monkeypatch.chdir(MAIN_DIR)
     monkeypatch.setenv("PYBIND11_GLOBAL_SDIST", "1")
-
-    out = subprocess.check_output(
-        [
-            sys.executable,
-            "setup.py",
-            "sdist",
-            "--formats=tar",
-            "--dist-dir",
-            str(tmpdir),
-        ]
+    subprocess.run(
+        [sys.executable, "-m", "build", "--sdist", "--outdir", str(tmpdir)], check=True
     )
-    if hasattr(out, "decode"):
-        out = out.decode()
 
-    (sdist,) = tmpdir.visit("*.tar")
+    (sdist,) = tmpdir.visit("*.tar.gz")
 
-    with tarfile.open(str(sdist)) as tar:
+    with tarfile.open(str(sdist), "r:gz") as tar:
         start = tar.getnames()[0] + "/"
         version = start[16:-1]
-        simpler = set(n.split("/", 1)[-1] for n in tar.getnames()[1:])
+        simpler = {n.split("/", 1)[-1] for n in tar.getnames()[1:]}
 
-        with contextlib.closing(
-            tar.extractfile(tar.getmember(start + "setup.py"))
-        ) as f:
-            setup_py = f.read()
+        setup_py = read_tz_file(tar, "setup.py")
+        pyproject_toml = read_tz_file(tar, "pyproject.toml")
+        pkgconfig = read_tz_file(tar, "pybind11/share/pkgconfig/pybind11.pc")
+        cmake_cfg = read_tz_file(
+            tar, "pybind11/share/cmake/pybind11/pybind11Config.cmake"
+        )
 
-        with contextlib.closing(
-            tar.extractfile(tar.getmember(start + "pyproject.toml"))
-        ) as f:
-            pyproject_toml = f.read()
+    assert (
+        'set(pybind11_INCLUDE_DIR "${PACKAGE_PREFIX_DIR}/include")'
+        in cmake_cfg.decode("utf-8")
+    )
 
-    files = set("pybind11/{}".format(n) for n in all_files)
+    files = {f"pybind11/{n}" for n in all_files}
     files |= sdist_files
-    files |= set("pybind11_global{}".format(n) for n in local_sdist_files)
+    files |= {f"pybind11_global{n}" for n in local_sdist_files}
     assert simpler == files
 
     with open(os.path.join(MAIN_DIR, "tools", "setup_global.py.in"), "rb") as f:
         contents = (
             string.Template(f.read().decode())
             .substitute(version=version, extra_cmd="")
-            .encode()
+            .encode("utf-8")
         )
         assert setup_py == contents
 
@@ -203,17 +223,21 @@ def test_build_global_dist(monkeypatch, tmpdir):
         contents = f.read()
         assert pyproject_toml == contents
 
+    simple_version = ".".join(version.split(".")[:3])
+    pkgconfig_expected = PKGCONFIG.format(VERSION=simple_version).encode("utf-8")
+    assert normalize_line_endings(pkgconfig) == pkgconfig_expected
+
 
 def tests_build_wheel(monkeypatch, tmpdir):
     monkeypatch.chdir(MAIN_DIR)
 
-    subprocess.check_output(
-        [sys.executable, "-m", "pip", "wheel", ".", "-w", str(tmpdir)]
+    subprocess.run(
+        [sys.executable, "-m", "pip", "wheel", ".", "-w", str(tmpdir)], check=True
     )
 
     (wheel,) = tmpdir.visit("*.whl")
 
-    files = set("pybind11/{}".format(n) for n in all_files)
+    files = {f"pybind11/{n}" for n in all_files}
     files |= {
         "dist-info/LICENSE",
         "dist-info/METADATA",
@@ -226,10 +250,8 @@ def tests_build_wheel(monkeypatch, tmpdir):
     with zipfile.ZipFile(str(wheel)) as z:
         names = z.namelist()
 
-    trimmed = set(n for n in names if "dist-info" not in n)
-    trimmed |= set(
-        "dist-info/{}".format(n.split("/", 1)[-1]) for n in names if "dist-info" in n
-    )
+    trimmed = {n for n in names if "dist-info" not in n}
+    trimmed |= {f"dist-info/{n.split('/', 1)[-1]}" for n in names if "dist-info" in n}
     assert files == trimmed
 
 
@@ -237,14 +259,14 @@ def tests_build_global_wheel(monkeypatch, tmpdir):
     monkeypatch.chdir(MAIN_DIR)
     monkeypatch.setenv("PYBIND11_GLOBAL_SDIST", "1")
 
-    subprocess.check_output(
-        [sys.executable, "-m", "pip", "wheel", ".", "-w", str(tmpdir)]
+    subprocess.run(
+        [sys.executable, "-m", "pip", "wheel", ".", "-w", str(tmpdir)], check=True
     )
 
     (wheel,) = tmpdir.visit("*.whl")
 
-    files = set("data/data/{}".format(n) for n in src_files)
-    files |= set("data/headers/{}".format(n[8:]) for n in headers)
+    files = {f"data/data/{n}" for n in src_files}
+    files |= {f"data/headers/{n[8:]}" for n in headers}
     files |= {
         "dist-info/LICENSE",
         "dist-info/METADATA",
@@ -257,6 +279,6 @@ def tests_build_global_wheel(monkeypatch, tmpdir):
         names = z.namelist()
 
     beginning = names[0].split("/", 1)[0].rsplit(".", 1)[0]
-    trimmed = set(n[len(beginning) + 1 :] for n in names)
+    trimmed = {n[len(beginning) + 1 :] for n in names}
 
     assert files == trimmed
diff --git a/3rdparty/pybind11/tests/extra_setuptools/test_setuphelper.py b/3rdparty/pybind11/tests/extra_setuptools/test_setuphelper.py
index 0d8bd0e4d6..d5d3093bf0 100644
--- a/3rdparty/pybind11/tests/extra_setuptools/test_setuphelper.py
+++ b/3rdparty/pybind11/tests/extra_setuptools/test_setuphelper.py
@@ -1,13 +1,13 @@
-# -*- coding: utf-8 -*-
 import os
-import sys
 import subprocess
+import sys
 from textwrap import dedent
 
 import pytest
 
 DIR = os.path.abspath(os.path.dirname(__file__))
 MAIN_DIR = os.path.dirname(os.path.dirname(DIR))
+WIN = sys.platform.startswith("win32") or sys.platform.startswith("cygwin")
 
 
 @pytest.mark.parametrize("parallel", [False, True])
@@ -18,7 +18,7 @@ def test_simple_setup_py(monkeypatch, tmpdir, parallel, std):
 
     (tmpdir / "setup.py").write_text(
         dedent(
-            u"""\
+            f"""\
             import sys
             sys.path.append({MAIN_DIR!r})
 
@@ -51,13 +51,13 @@ def test_simple_setup_py(monkeypatch, tmpdir, parallel, std):
                 ext_modules=ext_modules,
             )
             """
-        ).format(MAIN_DIR=MAIN_DIR, std=std, parallel=parallel),
+        ),
         encoding="ascii",
     )
 
     (tmpdir / "main.cpp").write_text(
         dedent(
-            u"""\
+            """\
             #include <pybind11/pybind11.h>
 
             int f(int x) {
@@ -71,13 +71,20 @@ def test_simple_setup_py(monkeypatch, tmpdir, parallel, std):
         encoding="ascii",
     )
 
-    subprocess.check_call(
+    out = subprocess.check_output(
         [sys.executable, "setup.py", "build_ext", "--inplace"],
-        stdout=sys.stdout,
-        stderr=sys.stderr,
     )
+    if not WIN:
+        assert b"-g0" in out
+    out = subprocess.check_output(
+        [sys.executable, "setup.py", "build_ext", "--inplace", "--force"],
+        env=dict(os.environ, CFLAGS="-g"),
+    )
+    if not WIN:
+        assert b"-g0" not in out
 
     # Debug helper printout, normally hidden
+    print(out)
     for item in tmpdir.listdir():
         print(item.basename)
 
@@ -88,7 +95,7 @@ def test_simple_setup_py(monkeypatch, tmpdir, parallel, std):
 
     (tmpdir / "test.py").write_text(
         dedent(
-            u"""\
+            """\
             import simple_setup
             assert simple_setup.f(3) == 9
             """
@@ -99,3 +106,46 @@ def test_simple_setup_py(monkeypatch, tmpdir, parallel, std):
     subprocess.check_call(
         [sys.executable, "test.py"], stdout=sys.stdout, stderr=sys.stderr
     )
+
+
+def test_intree_extensions(monkeypatch, tmpdir):
+    monkeypatch.syspath_prepend(MAIN_DIR)
+
+    from pybind11.setup_helpers import intree_extensions
+
+    monkeypatch.chdir(tmpdir)
+    root = tmpdir
+    root.ensure_dir()
+    subdir = root / "dir"
+    subdir.ensure_dir()
+    src = subdir / "ext.cpp"
+    src.ensure()
+    relpath = src.relto(tmpdir)
+    (ext,) = intree_extensions([relpath])
+    assert ext.name == "ext"
+    subdir.ensure("__init__.py")
+    (ext,) = intree_extensions([relpath])
+    assert ext.name == "dir.ext"
+
+
+def test_intree_extensions_package_dir(monkeypatch, tmpdir):
+    monkeypatch.syspath_prepend(MAIN_DIR)
+
+    from pybind11.setup_helpers import intree_extensions
+
+    monkeypatch.chdir(tmpdir)
+    root = tmpdir / "src"
+    root.ensure_dir()
+    subdir = root / "dir"
+    subdir.ensure_dir()
+    src = subdir / "ext.cpp"
+    src.ensure()
+    (ext,) = intree_extensions([src.relto(tmpdir)], package_dir={"": "src"})
+    assert ext.name == "dir.ext"
+    (ext,) = intree_extensions([src.relto(tmpdir)], package_dir={"foo": "src"})
+    assert ext.name == "foo.dir.ext"
+    subdir.ensure("__init__.py")
+    (ext,) = intree_extensions([src.relto(tmpdir)], package_dir={"": "src"})
+    assert ext.name == "dir.ext"
+    (ext,) = intree_extensions([src.relto(tmpdir)], package_dir={"foo": "src"})
+    assert ext.name == "foo.dir.ext"
diff --git a/3rdparty/pybind11/tests/local_bindings.h b/3rdparty/pybind11/tests/local_bindings.h
index 22537b13ad..01d2785353 100644
--- a/3rdparty/pybind11/tests/local_bindings.h
+++ b/3rdparty/pybind11/tests/local_bindings.h
@@ -1,10 +1,13 @@
 #pragma once
 #include "pybind11_tests.h"
 
+#include <utility>
+
 /// Simple class used to test py::local:
-template <int> class LocalBase {
+template <int>
+class LocalBase {
 public:
-    LocalBase(int i) : i(i) { }
+    explicit LocalBase(int i) : i(i) {}
     int i = -1;
 };
 
@@ -33,32 +36,57 @@ using NonLocalVec2 = std::vector<NonLocal2>;
 using NonLocalMap = std::unordered_map<std::string, NonLocalType>;
 using NonLocalMap2 = std::unordered_map<std::string, uint8_t>;
 
+// Exception that will be caught via the module local translator.
+class LocalException : public std::exception {
+public:
+    explicit LocalException(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
+private:
+    std::string message = "";
+};
+
+// Exception that will be registered with register_local_exception_translator
+class LocalSimpleException : public std::exception {
+public:
+    explicit LocalSimpleException(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
+private:
+    std::string message = "";
+};
+
 PYBIND11_MAKE_OPAQUE(LocalVec);
 PYBIND11_MAKE_OPAQUE(LocalVec2);
 PYBIND11_MAKE_OPAQUE(LocalMap);
 PYBIND11_MAKE_OPAQUE(NonLocalVec);
-//PYBIND11_MAKE_OPAQUE(NonLocalVec2); // same type as LocalVec2
+// PYBIND11_MAKE_OPAQUE(NonLocalVec2); // same type as LocalVec2
 PYBIND11_MAKE_OPAQUE(NonLocalMap);
 PYBIND11_MAKE_OPAQUE(NonLocalMap2);
 
-
 // Simple bindings (used with the above):
 template <typename T, int Adjust = 0, typename... Args>
-py::class_<T> bind_local(Args && ...args) {
-    return py::class_<T>(std::forward<Args>(args)...)
-        .def(py::init<int>())
-        .def("get", [](T &i) { return i.i + Adjust; });
+py::class_<T> bind_local(Args &&...args) {
+    return py::class_<T>(std::forward<Args>(args)...).def(py::init<int>()).def("get", [](T &i) {
+        return i.i + Adjust;
+    });
 };
 
 // Simulate a foreign library base class (to match the example in the docs):
 namespace pets {
 class Pet {
 public:
-    Pet(std::string name) : name_(name) {}
+    explicit Pet(std::string name) : name_(std::move(name)) {}
     std::string name_;
-    const std::string &name() { return name_; }
+    const std::string &name() const { return name_; }
 };
 } // namespace pets
 
-struct MixGL { int i; MixGL(int i) : i{i} {} };
-struct MixGL2 { int i; MixGL2(int i) : i{i} {} };
+struct MixGL {
+    int i;
+    explicit MixGL(int i) : i{i} {}
+};
+struct MixGL2 {
+    int i;
+    explicit MixGL2(int i) : i{i} {}
+};
diff --git a/3rdparty/pybind11/tests/object.h b/3rdparty/pybind11/tests/object.h
index 9235f19c20..564dd4a7a5 100644
--- a/3rdparty/pybind11/tests/object.h
+++ b/3rdparty/pybind11/tests/object.h
@@ -1,8 +1,9 @@
 #if !defined(__OBJECT_H)
-#define __OBJECT_H
+#    define __OBJECT_H
 
-#include <atomic>
-#include "constructor_stats.h"
+#    include "constructor_stats.h"
+
+#    include <atomic>
 
 /// Reference counted object base class
 class Object {
@@ -27,20 +28,23 @@ class Object {
      */
     void decRef(bool dealloc = true) const {
         --m_refCount;
-        if (m_refCount == 0 && dealloc)
+        if (m_refCount == 0 && dealloc) {
             delete this;
-        else if (m_refCount < 0)
+        } else if (m_refCount < 0) {
             throw std::runtime_error("Internal error: reference count < 0!");
+        }
     }
 
     virtual std::string toString() const = 0;
+
 protected:
     /** \brief Virtual protected deconstructor.
      * (Will only be called by \ref ref)
      */
     virtual ~Object() { print_destroyed(this); }
+
 private:
-    mutable std::atomic<int> m_refCount { 0 };
+    mutable std::atomic<int> m_refCount{0};
 };
 
 // Tag class used to track constructions of ref objects.  When we track constructors, below, we
@@ -59,80 +63,105 @@ class ref_tag {};
  *
  * \ingroup libcore
  */
-template <typename T> class ref {
+template <typename T>
+class ref {
 public:
     /// Create a nullptr reference
-    ref() : m_ptr(nullptr) { print_default_created(this); track_default_created((ref_tag*) this); }
+    ref() : m_ptr(nullptr) {
+        print_default_created(this);
+        track_default_created((ref_tag *) this);
+    }
 
     /// Construct a reference from a pointer
-    ref(T *ptr) : m_ptr(ptr) {
-        if (m_ptr) ((Object *) m_ptr)->incRef();
-
-        print_created(this, "from pointer", m_ptr); track_created((ref_tag*) this, "from pointer");
+    explicit ref(T *ptr) : m_ptr(ptr) {
+        if (m_ptr) {
+            ((Object *) m_ptr)->incRef();
+        }
 
+        print_created(this, "from pointer", m_ptr);
+        track_created((ref_tag *) this, "from pointer");
     }
 
     /// Copy constructor
     ref(const ref &r) : m_ptr(r.m_ptr) {
-        if (m_ptr)
+        if (m_ptr) {
             ((Object *) m_ptr)->incRef();
+        }
 
-        print_copy_created(this, "with pointer", m_ptr); track_copy_created((ref_tag*) this);
+        print_copy_created(this, "with pointer", m_ptr);
+        track_copy_created((ref_tag *) this);
     }
 
     /// Move constructor
-    ref(ref &&r) : m_ptr(r.m_ptr) {
+    ref(ref &&r) noexcept : m_ptr(r.m_ptr) {
         r.m_ptr = nullptr;
 
-        print_move_created(this, "with pointer", m_ptr); track_move_created((ref_tag*) this);
+        print_move_created(this, "with pointer", m_ptr);
+        track_move_created((ref_tag *) this);
     }
 
     /// Destroy this reference
     ~ref() {
-        if (m_ptr)
+        if (m_ptr) {
             ((Object *) m_ptr)->decRef();
+        }
 
-        print_destroyed(this); track_destroyed((ref_tag*) this);
+        print_destroyed(this);
+        track_destroyed((ref_tag *) this);
     }
 
     /// Move another reference into the current one
-    ref& operator=(ref&& r) {
-        print_move_assigned(this, "pointer", r.m_ptr); track_move_assigned((ref_tag*) this);
+    ref &operator=(ref &&r) noexcept {
+        print_move_assigned(this, "pointer", r.m_ptr);
+        track_move_assigned((ref_tag *) this);
 
-        if (*this == r)
+        if (*this == r) {
             return *this;
-        if (m_ptr)
+        }
+        if (m_ptr) {
             ((Object *) m_ptr)->decRef();
+        }
         m_ptr = r.m_ptr;
         r.m_ptr = nullptr;
         return *this;
     }
 
     /// Overwrite this reference with another reference
-    ref& operator=(const ref& r) {
-        print_copy_assigned(this, "pointer", r.m_ptr); track_copy_assigned((ref_tag*) this);
+    ref &operator=(const ref &r) {
+        if (this == &r) {
+            return *this;
+        }
+        print_copy_assigned(this, "pointer", r.m_ptr);
+        track_copy_assigned((ref_tag *) this);
 
-        if (m_ptr == r.m_ptr)
+        if (m_ptr == r.m_ptr) {
             return *this;
-        if (m_ptr)
+        }
+        if (m_ptr) {
             ((Object *) m_ptr)->decRef();
+        }
         m_ptr = r.m_ptr;
-        if (m_ptr)
+        if (m_ptr) {
             ((Object *) m_ptr)->incRef();
+        }
         return *this;
     }
 
     /// Overwrite this reference with a pointer to another object
-    ref& operator=(T *ptr) {
-        print_values(this, "assigned pointer"); track_values((ref_tag*) this, "assigned pointer");
+    ref &operator=(T *ptr) {
+        print_values(this, "assigned pointer");
+        track_values((ref_tag *) this, "assigned pointer");
 
-        if (m_ptr == ptr)
+        if (m_ptr == ptr) {
             return *this;
-        if (m_ptr)
+        }
+        if (m_ptr) {
             ((Object *) m_ptr)->decRef();
+        }
         m_ptr = ptr;
-        if (m_ptr)
+        if (m_ptr) {
             ((Object *) m_ptr)->incRef();
+        }
         return *this;
     }
 
@@ -143,31 +172,32 @@ template <typename T> class ref {
     bool operator!=(const ref &r) const { return m_ptr != r.m_ptr; }
 
     /// Compare this reference with a pointer
-    bool operator==(const T* ptr) const { return m_ptr == ptr; }
+    bool operator==(const T *ptr) const { return m_ptr == ptr; }
 
     /// Compare this reference with a pointer
-    bool operator!=(const T* ptr) const { return m_ptr != ptr; }
+    bool operator!=(const T *ptr) const { return m_ptr != ptr; }
 
     /// Access the object referenced by this reference
-    T* operator->() { return m_ptr; }
+    T *operator->() { return m_ptr; }
 
     /// Access the object referenced by this reference
-    const T* operator->() const { return m_ptr; }
+    const T *operator->() const { return m_ptr; }
 
     /// Return a C++ reference to the referenced object
-    T& operator*() { return *m_ptr; }
+    T &operator*() { return *m_ptr; }
 
     /// Return a const C++ reference to the referenced object
-    const T& operator*() const { return *m_ptr; }
+    const T &operator*() const { return *m_ptr; }
 
     /// Return a pointer to the referenced object
-    operator T* () { return m_ptr; }
+    explicit operator T *() { return m_ptr; }
 
     /// Return a const pointer to the referenced object
-    T* get_ptr() { return m_ptr; }
+    T *get_ptr() { return m_ptr; }
 
     /// Return a pointer to the referenced object
-    const T* get_ptr() const { return m_ptr; }
+    const T *get_ptr() const { return m_ptr; }
+
 private:
     T *m_ptr;
 };
diff --git a/3rdparty/pybind11/tests/pybind11_cross_module_tests.cpp b/3rdparty/pybind11/tests/pybind11_cross_module_tests.cpp
index f705e31061..9379f3f259 100644
--- a/3rdparty/pybind11/tests/pybind11_cross_module_tests.cpp
+++ b/3rdparty/pybind11/tests/pybind11_cross_module_tests.cpp
@@ -7,10 +7,14 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "local_bindings.h"
 #include <pybind11/stl_bind.h>
+
+#include "local_bindings.h"
+#include "pybind11_tests.h"
+#include "test_exceptions.h"
+
 #include <numeric>
+#include <utility>
 
 PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     m.doc() = "pybind11 cross-module test module";
@@ -25,17 +29,46 @@ PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     bind_local<ExternalType2>(m, "ExternalType2", py::module_local());
 
     // test_exceptions.py
-    m.def("raise_runtime_error", []() { PyErr_SetString(PyExc_RuntimeError, "My runtime error"); throw py::error_already_set(); });
-    m.def("raise_value_error", []() { PyErr_SetString(PyExc_ValueError, "My value error"); throw py::error_already_set(); });
+    py::register_local_exception<LocalSimpleException>(m, "LocalSimpleException");
+    m.def("raise_runtime_error", []() {
+        PyErr_SetString(PyExc_RuntimeError, "My runtime error");
+        throw py::error_already_set();
+    });
+    m.def("raise_value_error", []() {
+        PyErr_SetString(PyExc_ValueError, "My value error");
+        throw py::error_already_set();
+    });
     m.def("throw_pybind_value_error", []() { throw py::value_error("pybind11 value error"); });
     m.def("throw_pybind_type_error", []() { throw py::type_error("pybind11 type error"); });
     m.def("throw_stop_iteration", []() { throw py::stop_iteration(); });
+    m.def("throw_local_error", []() { throw LocalException("just local"); });
+    m.def("throw_local_simple_error", []() { throw LocalSimpleException("external mod"); });
+    py::register_exception_translator([](std::exception_ptr p) {
+        try {
+            if (p) {
+                std::rethrow_exception(p);
+            }
+        } catch (const shared_exception &e) {
+            PyErr_SetString(PyExc_KeyError, e.what());
+        }
+    });
+
+    // translate the local exception into a key error but only in this module
+    py::register_local_exception_translator([](std::exception_ptr p) {
+        try {
+            if (p) {
+                std::rethrow_exception(p);
+            }
+        } catch (const LocalException &e) {
+            PyErr_SetString(PyExc_KeyError, e.what());
+        }
+    });
 
     // test_local_bindings.py
     // Local to both:
-    bind_local<LocalType, 1>(m, "LocalType", py::module_local())
-        .def("get2", [](LocalType &t) { return t.i + 2; })
-        ;
+    bind_local<LocalType, 1>(m, "LocalType", py::module_local()).def("get2", [](LocalType &t) {
+        return t.i + 2;
+    });
 
     // Can only be called with our python type:
     m.def("local_value", [](LocalType &l) { return l.i; });
@@ -43,9 +76,7 @@ PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     // test_nonlocal_failure
     // This registration will fail (global registration when LocalFail is already registered
     // globally in the main test module):
-    m.def("register_nonlocal", [m]() {
-        bind_local<NonLocalType, 0>(m, "NonLocalType");
-    });
+    m.def("register_nonlocal", [m]() { bind_local<NonLocalType, 0>(m, "NonLocalType"); });
 
     // test_stl_bind_local
     // stl_bind.h binders defaults to py::module_local if the types are local or converting:
@@ -55,27 +86,21 @@ PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     // test_stl_bind_global
     // and global if the type (or one of the types, for the map) is global (so these will fail,
     // assuming pybind11_tests is already loaded):
-    m.def("register_nonlocal_vec", [m]() {
-        py::bind_vector<NonLocalVec>(m, "NonLocalVec");
-    });
-    m.def("register_nonlocal_map", [m]() {
-        py::bind_map<NonLocalMap>(m, "NonLocalMap");
-    });
+    m.def("register_nonlocal_vec", [m]() { py::bind_vector<NonLocalVec>(m, "NonLocalVec"); });
+    m.def("register_nonlocal_map", [m]() { py::bind_map<NonLocalMap>(m, "NonLocalMap"); });
     // The default can, however, be overridden to global using `py::module_local()` or
     // `py::module_local(false)`.
     // Explicitly made local:
     py::bind_vector<NonLocalVec2>(m, "NonLocalVec2", py::module_local());
     // Explicitly made global (and so will fail to bind):
-    m.def("register_nonlocal_map2", [m]() {
-        py::bind_map<NonLocalMap2>(m, "NonLocalMap2", py::module_local(false));
-    });
+    m.def("register_nonlocal_map2",
+          [m]() { py::bind_map<NonLocalMap2>(m, "NonLocalMap2", py::module_local(false)); });
 
     // test_mixed_local_global
     // We try this both with the global type registered first and vice versa (the order shouldn't
     // matter).
-    m.def("register_mixed_global_local", [m]() {
-        bind_local<MixedGlobalLocal, 200>(m, "MixedGlobalLocal", py::module_local());
-    });
+    m.def("register_mixed_global_local",
+          [m]() { bind_local<MixedGlobalLocal, 200>(m, "MixedGlobalLocal", py::module_local()); });
     m.def("register_mixed_local_global", [m]() {
         bind_local<MixedLocalGlobal, 2000>(m, "MixedLocalGlobal", py::module_local(false));
     });
@@ -83,25 +108,26 @@ PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     m.def("get_mixed_lg", [](int i) { return MixedLocalGlobal(i); });
 
     // test_internal_locals_differ
-    m.def("local_cpp_types_addr", []() { return (uintptr_t) &py::detail::registered_local_types_cpp(); });
+    m.def("local_cpp_types_addr",
+          []() { return (uintptr_t) &py::detail::get_local_internals().registered_types_cpp; });
 
     // test_stl_caster_vs_stl_bind
     py::bind_vector<std::vector<int>>(m, "VectorInt");
 
-    m.def("load_vector_via_binding", [](std::vector<int> &v) {
-        return std::accumulate(v.begin(), v.end(), 0);
-    });
+    m.def("load_vector_via_binding",
+          [](std::vector<int> &v) { return std::accumulate(v.begin(), v.end(), 0); });
 
     // test_cross_module_calls
     m.def("return_self", [](LocalVec *v) { return v; });
     m.def("return_copy", [](const LocalVec &v) { return LocalVec(v); });
 
-    class Dog : public pets::Pet { public: Dog(std::string name) : Pet(name) {}; };
-    py::class_<pets::Pet>(m, "Pet", py::module_local())
-        .def("name", &pets::Pet::name);
+    class Dog : public pets::Pet {
+    public:
+        explicit Dog(std::string name) : Pet(std::move(name)) {}
+    };
+    py::class_<pets::Pet>(m, "Pet", py::module_local()).def("name", &pets::Pet::name);
     // Binding for local extending class:
-    py::class_<Dog, pets::Pet>(m, "Dog")
-        .def(py::init<std::string>());
+    py::class_<Dog, pets::Pet>(m, "Dog").def(py::init<std::string>());
     m.def("pet_name", [](pets::Pet &p) { return p.name(); });
 
     py::class_<MixGL>(m, "MixGL", py::module_local()).def(py::init<int>());
@@ -118,6 +144,6 @@ PYBIND11_MODULE(pybind11_cross_module_tests, m) {
     // test_missing_header_message
     // The main module already includes stl.h, but we need to test the error message
     // which appears when this header is missing.
-    m.def("missing_header_arg", [](std::vector<float>) { });
+    m.def("missing_header_arg", [](const std::vector<float> &) {});
     m.def("missing_header_return", []() { return std::vector<float>(); });
 }
diff --git a/3rdparty/pybind11/tests/pybind11_tests.cpp b/3rdparty/pybind11/tests/pybind11_tests.cpp
index 439cd40129..aa3095594b 100644
--- a/3rdparty/pybind11/tests/pybind11_tests.cpp
+++ b/3rdparty/pybind11/tests/pybind11_tests.cpp
@@ -8,6 +8,7 @@
 */
 
 #include "pybind11_tests.h"
+
 #include "constructor_stats.h"
 
 #include <functional>
@@ -31,9 +32,7 @@ std::list<std::function<void(py::module_ &)>> &initializers() {
     return inits;
 }
 
-test_initializer::test_initializer(Initializer init) {
-    initializers().emplace_back(init);
-}
+test_initializer::test_initializer(Initializer init) { initializers().emplace_back(init); }
 
 test_initializer::test_initializer(const char *submodule_name, Initializer init) {
     initializers().emplace_back([=](py::module_ &parent) {
@@ -51,26 +50,52 @@ void bind_ConstructorStats(py::module_ &m) {
         .def_readwrite("move_assignments", &ConstructorStats::move_assignments)
         .def_readwrite("copy_constructions", &ConstructorStats::copy_constructions)
         .def_readwrite("move_constructions", &ConstructorStats::move_constructions)
-        .def_static("get", (ConstructorStats &(*)(py::object)) &ConstructorStats::get, py::return_value_policy::reference_internal)
+        .def_static("get",
+                    (ConstructorStats & (*) (py::object)) & ConstructorStats::get,
+                    py::return_value_policy::reference_internal)
 
-        // Not exactly ConstructorStats, but related: expose the internal pybind number of registered instances
-        // to allow instance cleanup checks (invokes a GC first)
+        // Not exactly ConstructorStats, but related: expose the internal pybind number of
+        // registered instances to allow instance cleanup checks (invokes a GC first)
         .def_static("detail_reg_inst", []() {
             ConstructorStats::gc();
             return py::detail::get_internals().registered_instances.size();
-        })
-        ;
+        });
+}
+
+const char *cpp_std() {
+    return
+#if defined(PYBIND11_CPP20)
+        "C++20";
+#elif defined(PYBIND11_CPP17)
+        "C++17";
+#elif defined(PYBIND11_CPP14)
+        "C++14";
+#else
+        "C++11";
+#endif
 }
 
 PYBIND11_MODULE(pybind11_tests, m) {
     m.doc() = "pybind11 test module";
 
+    // Intentionally kept minimal to not create a maintenance chore
+    // ("just enough" to be conclusive).
+#if defined(_MSC_FULL_VER)
+    m.attr("compiler_info") = "MSVC " PYBIND11_TOSTRING(_MSC_FULL_VER);
+#elif defined(__VERSION__)
+    m.attr("compiler_info") = __VERSION__;
+#else
+    m.attr("compiler_info") = py::none();
+#endif
+    m.attr("cpp_std") = cpp_std();
+    m.attr("PYBIND11_INTERNALS_ID") = PYBIND11_INTERNALS_ID;
+
     bind_ConstructorStats(m);
 
-#if !defined(NDEBUG)
-    m.attr("debug_enabled") = true;
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+    m.attr("detailed_error_messages_enabled") = true;
 #else
-    m.attr("debug_enabled") = false;
+    m.attr("detailed_error_messages_enabled") = false;
 #endif
 
     py::class_<UserType>(m, "UserType", "A `py::class_` type for testing")
@@ -79,13 +104,14 @@ PYBIND11_MODULE(pybind11_tests, m) {
         .def("get_value", &UserType::value, "Get value using a method")
         .def("set_value", &UserType::set, "Set value using a method")
         .def_property("value", &UserType::value, &UserType::set, "Get/set value using a property")
-        .def("__repr__", [](const UserType& u) { return "UserType({})"_s.format(u.value()); });
+        .def("__repr__", [](const UserType &u) { return "UserType({})"_s.format(u.value()); });
 
     py::class_<IncType, UserType>(m, "IncType")
         .def(py::init<>())
         .def(py::init<int>())
-        .def("__repr__", [](const IncType& u) { return "IncType({})"_s.format(u.value()); });
+        .def("__repr__", [](const IncType &u) { return "IncType({})"_s.format(u.value()); });
 
-    for (const auto &initializer : initializers())
+    for (const auto &initializer : initializers()) {
         initializer(m);
+    }
 }
diff --git a/3rdparty/pybind11/tests/pybind11_tests.h b/3rdparty/pybind11/tests/pybind11_tests.h
index 4ff56c07de..a7c00c2f9b 100644
--- a/3rdparty/pybind11/tests/pybind11_tests.h
+++ b/3rdparty/pybind11/tests/pybind11_tests.h
@@ -1,10 +1,7 @@
 #pragma once
-#include <pybind11/pybind11.h>
 
-#if defined(_MSC_VER) && _MSC_VER < 1910
-// We get some really long type names here which causes MSVC 2015 to emit warnings
-#  pragma warning(disable: 4503) // warning C4503: decorated name length exceeded, name was truncated
-#endif
+#include <pybind11/eval.h>
+#include <pybind11/pybind11.h>
 
 namespace py = pybind11;
 using namespace pybind11::literals;
@@ -13,24 +10,23 @@ class test_initializer {
     using Initializer = void (*)(py::module_ &);
 
 public:
-    test_initializer(Initializer init);
+    explicit test_initializer(Initializer init);
     test_initializer(const char *submodule_name, Initializer init);
 };
 
-#define TEST_SUBMODULE(name, variable)                   \
-    void test_submodule_##name(py::module_ &);            \
-    test_initializer name(#name, test_submodule_##name); \
-    void test_submodule_##name(py::module_ &variable)
-
+#define TEST_SUBMODULE(name, variable)                                                            \
+    void test_submodule_##name(py::module_ &);                                                    \
+    test_initializer name(#name, test_submodule_##name);                                          \
+    void test_submodule_##name(py::module_ &(variable))
 
 /// Dummy type which is not exported anywhere -- something to trigger a conversion error
-struct UnregisteredType { };
+struct UnregisteredType {};
 
 /// A user-defined type which is exported and can be used by any test
 class UserType {
 public:
     UserType() = default;
-    UserType(int i) : i(i) { }
+    explicit UserType(int i) : i(i) {}
 
     int value() const { return i; }
     void set(int set) { i = set; }
@@ -44,7 +40,7 @@ class IncType : public UserType {
 public:
     using UserType::UserType;
     IncType() = default;
-    IncType(const IncType &other) : IncType(other.value() + 1) { }
+    IncType(const IncType &other) : IncType(other.value() + 1) {}
     IncType(IncType &&) = delete;
     IncType &operator=(const IncType &) = delete;
     IncType &operator=(IncType &&) = delete;
@@ -56,16 +52,34 @@ union IntFloat {
     float f;
 };
 
-/// Custom cast-only type that casts to a string "rvalue" or "lvalue" depending on the cast context.
-/// Used to test recursive casters (e.g. std::tuple, stl containers).
+/// Custom cast-only type that casts to a string "rvalue" or "lvalue" depending on the cast
+/// context. Used to test recursive casters (e.g. std::tuple, stl containers).
 struct RValueCaster {};
 PYBIND11_NAMESPACE_BEGIN(pybind11)
 PYBIND11_NAMESPACE_BEGIN(detail)
-template<> class type_caster<RValueCaster> {
+template <>
+class type_caster<RValueCaster> {
 public:
-    PYBIND11_TYPE_CASTER(RValueCaster, _("RValueCaster"));
-    static handle cast(RValueCaster &&, return_value_policy, handle) { return py::str("rvalue").release(); }
-    static handle cast(const RValueCaster &, return_value_policy, handle) { return py::str("lvalue").release(); }
+    PYBIND11_TYPE_CASTER(RValueCaster, const_name("RValueCaster"));
+    static handle cast(RValueCaster &&, return_value_policy, handle) {
+        return py::str("rvalue").release();
+    }
+    static handle cast(const RValueCaster &, return_value_policy, handle) {
+        return py::str("lvalue").release();
+    }
 };
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(pybind11)
+
+template <typename F>
+void ignoreOldStyleInitWarnings(F &&body) {
+    py::exec(R"(
+    message = "pybind11-bound class '.+' is using an old-style placement-new '(?:__init__|__setstate__)' which has been deprecated"
+
+    import warnings
+    with warnings.catch_warnings():
+        warnings.filterwarnings("ignore", message=message, category=FutureWarning)
+        body()
+    )",
+             py::dict(py::arg("body") = py::cpp_function(body)));
+}
diff --git a/3rdparty/pybind11/tests/pytest.ini b/3rdparty/pybind11/tests/pytest.ini
index c47cbe9c1e..792ba361f7 100644
--- a/3rdparty/pybind11/tests/pytest.ini
+++ b/3rdparty/pybind11/tests/pytest.ini
@@ -1,17 +1,20 @@
 [pytest]
-minversion = 3.1
+minversion = 3.10
 norecursedirs = test_* extra_*
 xfail_strict = True
 addopts =
-    # show summary of skipped tests
-    -rs
+    # show summary of tests
+    -ra
     # capture only Python print and C++ py::print, but not C output (low-level Python errors)
     --capture=sys
-    # enable all warnings
-    -Wa
+    # Show local info when a failure occurs
+    --showlocals
+log_cli_level = info
 filterwarnings =
     # make warnings into errors but ignore certain third-party extension issues
     error
+    # somehow, some DeprecationWarnings do not get turned into errors
+    always::DeprecationWarning
     # importing scipy submodules on some version of Python
     ignore::ImportWarning
     # bogus numpy ABI warning (see numpy/#432)
diff --git a/3rdparty/pybind11/tests/requirements.txt b/3rdparty/pybind11/tests/requirements.txt
index 80ed6171d7..04aafa8cf9 100644
--- a/3rdparty/pybind11/tests/requirements.txt
+++ b/3rdparty/pybind11/tests/requirements.txt
@@ -1,8 +1,9 @@
---extra-index-url https://antocuni.github.io/pypy-wheels/manylinux2010/
-numpy==1.16.6; python_version<"3.6" and sys_platform!="win32"
-numpy==1.18.0; platform_python_implementation=="PyPy" and sys_platform=="darwin" and python_version>="3.6"
-numpy==1.19.3; (platform_python_implementation!="PyPy" or sys_platform=="linux") and python_version>="3.6" and python_version<"3.10"
-pytest==4.6.9; python_version<"3.5"
-pytest==5.4.3; python_version>="3.5"
-scipy==1.2.3; (platform_python_implementation!="PyPy" or sys_platform=="linux") and python_version<"3.6"
-scipy==1.5.2; (platform_python_implementation!="PyPy" or sys_platform=="linux") and python_version>="3.6" and python_version<"3.9"
+build==0.8.0
+numpy==1.21.5; platform_python_implementation=="PyPy" and sys_platform=="linux" and python_version=="3.7"
+numpy==1.19.3; platform_python_implementation!="PyPy" and python_version=="3.6"
+numpy==1.21.5; platform_python_implementation!="PyPy" and python_version>="3.7" and python_version<"3.10"
+numpy==1.22.2; platform_python_implementation!="PyPy" and python_version>="3.10" and python_version<"3.11"
+pytest==7.0.0
+pytest-timeout
+scipy==1.5.4; platform_python_implementation!="PyPy" and python_version<"3.10"
+scipy==1.8.0; platform_python_implementation!="PyPy" and python_version=="3.10"
diff --git a/3rdparty/pybind11/tests/test_async.cpp b/3rdparty/pybind11/tests/test_async.cpp
index e6e01d72c9..a5d7224657 100644
--- a/3rdparty/pybind11/tests/test_async.cpp
+++ b/3rdparty/pybind11/tests/test_async.cpp
@@ -11,12 +11,11 @@
 
 TEST_SUBMODULE(async_module, m) {
     struct DoesNotSupportAsync {};
-    py::class_<DoesNotSupportAsync>(m, "DoesNotSupportAsync")
-        .def(py::init<>());
+    py::class_<DoesNotSupportAsync>(m, "DoesNotSupportAsync").def(py::init<>());
     struct SupportsAsync {};
     py::class_<SupportsAsync>(m, "SupportsAsync")
         .def(py::init<>())
-        .def("__await__", [](const SupportsAsync& self) -> py::object {
+        .def("__await__", [](const SupportsAsync &self) -> py::object {
             static_cast<void>(self);
             py::object loop = py::module_::import("asyncio.events").attr("get_event_loop")();
             py::object f = loop.attr("create_future")();
diff --git a/3rdparty/pybind11/tests/test_async.py b/3rdparty/pybind11/tests/test_async.py
index df4489c499..b9ff9514d2 100644
--- a/3rdparty/pybind11/tests/test_async.py
+++ b/3rdparty/pybind11/tests/test_async.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 asyncio = pytest.importorskip("asyncio")
diff --git a/3rdparty/pybind11/tests/test_buffers.cpp b/3rdparty/pybind11/tests/test_buffers.cpp
index 46eabf3963..6b6e8cba7f 100644
--- a/3rdparty/pybind11/tests/test_buffers.cpp
+++ b/3rdparty/pybind11/tests/test_buffers.cpp
@@ -7,27 +7,31 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/stl.h>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 TEST_SUBMODULE(buffers, m) {
     // test_from_python / test_to_python:
     class Matrix {
     public:
         Matrix(py::ssize_t rows, py::ssize_t cols) : m_rows(rows), m_cols(cols) {
             print_created(this, std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
-            m_data = new float[(size_t) (rows*cols)];
+            // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+            m_data = new float[(size_t) (rows * cols)];
             memset(m_data, 0, sizeof(float) * (size_t) (rows * cols));
         }
 
         Matrix(const Matrix &s) : m_rows(s.m_rows), m_cols(s.m_cols) {
-            print_copy_created(this, std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
+            print_copy_created(this,
+                               std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
+            // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
             m_data = new float[(size_t) (m_rows * m_cols)];
             memcpy(m_data, s.m_data, sizeof(float) * (size_t) (m_rows * m_cols));
         }
 
-        Matrix(Matrix &&s) : m_rows(s.m_rows), m_cols(s.m_cols), m_data(s.m_data) {
+        Matrix(Matrix &&s) noexcept : m_rows(s.m_rows), m_cols(s.m_cols), m_data(s.m_data) {
             print_move_created(this);
             s.m_rows = 0;
             s.m_cols = 0;
@@ -35,12 +39,17 @@ TEST_SUBMODULE(buffers, m) {
         }
 
         ~Matrix() {
-            print_destroyed(this, std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
+            print_destroyed(this,
+                            std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
             delete[] m_data;
         }
 
         Matrix &operator=(const Matrix &s) {
-            print_copy_assigned(this, std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
+            if (this == &s) {
+                return *this;
+            }
+            print_copy_assigned(this,
+                                std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
             delete[] m_data;
             m_rows = s.m_rows;
             m_cols = s.m_cols;
@@ -49,28 +58,34 @@ TEST_SUBMODULE(buffers, m) {
             return *this;
         }
 
-        Matrix &operator=(Matrix &&s) {
-            print_move_assigned(this, std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
+        Matrix &operator=(Matrix &&s) noexcept {
+            print_move_assigned(this,
+                                std::to_string(m_rows) + "x" + std::to_string(m_cols) + " matrix");
             if (&s != this) {
                 delete[] m_data;
-                m_rows = s.m_rows; m_cols = s.m_cols; m_data = s.m_data;
-                s.m_rows = 0; s.m_cols = 0; s.m_data = nullptr;
+                m_rows = s.m_rows;
+                m_cols = s.m_cols;
+                m_data = s.m_data;
+                s.m_rows = 0;
+                s.m_cols = 0;
+                s.m_data = nullptr;
             }
             return *this;
         }
 
         float operator()(py::ssize_t i, py::ssize_t j) const {
-            return m_data[(size_t) (i*m_cols + j)];
+            return m_data[(size_t) (i * m_cols + j)];
         }
 
         float &operator()(py::ssize_t i, py::ssize_t j) {
-            return m_data[(size_t) (i*m_cols + j)];
+            return m_data[(size_t) (i * m_cols + j)];
         }
 
         float *data() { return m_data; }
 
         py::ssize_t rows() const { return m_rows; }
         py::ssize_t cols() const { return m_cols; }
+
     private:
         py::ssize_t m_rows;
         py::ssize_t m_cols;
@@ -79,51 +94,51 @@ TEST_SUBMODULE(buffers, m) {
     py::class_<Matrix>(m, "Matrix", py::buffer_protocol())
         .def(py::init<py::ssize_t, py::ssize_t>())
         /// Construct from a buffer
-        .def(py::init([](py::buffer const b) {
+        .def(py::init([](const py::buffer &b) {
             py::buffer_info info = b.request();
-            if (info.format != py::format_descriptor<float>::format() || info.ndim != 2)
+            if (info.format != py::format_descriptor<float>::format() || info.ndim != 2) {
                 throw std::runtime_error("Incompatible buffer format!");
+            }
 
-            auto v = new Matrix(info.shape[0], info.shape[1]);
+            auto *v = new Matrix(info.shape[0], info.shape[1]);
             memcpy(v->data(), info.ptr, sizeof(float) * (size_t) (v->rows() * v->cols()));
             return v;
         }))
 
-       .def("rows", &Matrix::rows)
-       .def("cols", &Matrix::cols)
+        .def("rows", &Matrix::rows)
+        .def("cols", &Matrix::cols)
 
         /// Bare bones interface
-       .def("__getitem__", [](const Matrix &m, std::pair<py::ssize_t, py::ssize_t> i) {
-            if (i.first >= m.rows() || i.second >= m.cols())
-                throw py::index_error();
-            return m(i.first, i.second);
-        })
-       .def("__setitem__", [](Matrix &m, std::pair<py::ssize_t, py::ssize_t> i, float v) {
-            if (i.first >= m.rows() || i.second >= m.cols())
-                throw py::index_error();
-            m(i.first, i.second) = v;
-        })
-       /// Provide buffer access
-       .def_buffer([](Matrix &m) -> py::buffer_info {
+        .def("__getitem__",
+             [](const Matrix &m, std::pair<py::ssize_t, py::ssize_t> i) {
+                 if (i.first >= m.rows() || i.second >= m.cols()) {
+                     throw py::index_error();
+                 }
+                 return m(i.first, i.second);
+             })
+        .def("__setitem__",
+             [](Matrix &m, std::pair<py::ssize_t, py::ssize_t> i, float v) {
+                 if (i.first >= m.rows() || i.second >= m.cols()) {
+                     throw py::index_error();
+                 }
+                 m(i.first, i.second) = v;
+             })
+        /// Provide buffer access
+        .def_buffer([](Matrix &m) -> py::buffer_info {
             return py::buffer_info(
-                m.data(),                               /* Pointer to buffer */
-                { m.rows(), m.cols() },                 /* Buffer dimensions */
-                { sizeof(float) * size_t(m.cols()),     /* Strides (in bytes) for each index */
-                  sizeof(float) }
-            );
-        })
-        ;
-
+                m.data(),                          /* Pointer to buffer */
+                {m.rows(), m.cols()},              /* Buffer dimensions */
+                {sizeof(float) * size_t(m.cols()), /* Strides (in bytes) for each index */
+                 sizeof(float)});
+        });
 
     // test_inherited_protocol
     class SquareMatrix : public Matrix {
     public:
-        SquareMatrix(py::ssize_t n) : Matrix(n, n) { }
+        explicit SquareMatrix(py::ssize_t n) : Matrix(n, n) {}
     };
     // Derived classes inherit the buffer protocol and the buffer access function
-    py::class_<SquareMatrix, Matrix>(m, "SquareMatrix")
-        .def(py::init<py::ssize_t>());
-
+    py::class_<SquareMatrix, Matrix>(m, "SquareMatrix").def(py::init<py::ssize_t>());
 
     // test_pointer_to_member_fn
     // Tests that passing a pointer to member to the base class works in
@@ -132,8 +147,8 @@ TEST_SUBMODULE(buffers, m) {
         int32_t value = 0;
 
         py::buffer_info get_buffer_info() {
-            return py::buffer_info(&value, sizeof(value),
-                                   py::format_descriptor<int32_t>::format(), 1);
+            return py::buffer_info(
+                &value, sizeof(value), py::format_descriptor<int32_t>::format(), 1);
         }
     };
     py::class_<Buffer>(m, "Buffer", py::buffer_protocol())
@@ -141,7 +156,6 @@ TEST_SUBMODULE(buffers, m) {
         .def_readwrite("value", &Buffer::value)
         .def_buffer(&Buffer::get_buffer_info);
 
-
     class ConstBuffer {
         std::unique_ptr<int32_t> value;
 
@@ -150,18 +164,18 @@ TEST_SUBMODULE(buffers, m) {
         void set_value(int32_t v) { *value = v; }
 
         py::buffer_info get_buffer_info() const {
-            return py::buffer_info(value.get(), sizeof(*value),
-                                   py::format_descriptor<int32_t>::format(), 1);
+            return py::buffer_info(
+                value.get(), sizeof(*value), py::format_descriptor<int32_t>::format(), 1);
         }
 
-        ConstBuffer() : value(new int32_t{0}) { };
+        ConstBuffer() : value(new int32_t{0}) {}
     };
     py::class_<ConstBuffer>(m, "ConstBuffer", py::buffer_protocol())
         .def(py::init<>())
         .def_property("value", &ConstBuffer::get_value, &ConstBuffer::set_value)
         .def_buffer(&ConstBuffer::get_buffer_info);
 
-    struct DerivedBuffer : public Buffer { };
+    struct DerivedBuffer : public Buffer {};
     py::class_<DerivedBuffer>(m, "DerivedBuffer", py::buffer_protocol())
         .def(py::init<>())
         .def_readwrite("value", (int32_t DerivedBuffer::*) &DerivedBuffer::value)
@@ -169,11 +183,9 @@ TEST_SUBMODULE(buffers, m) {
 
     struct BufferReadOnly {
         const uint8_t value = 0;
-        BufferReadOnly(uint8_t value): value(value) {}
+        explicit BufferReadOnly(uint8_t value) : value(value) {}
 
-        py::buffer_info get_buffer_info() {
-            return py::buffer_info(&value, 1);
-        }
+        py::buffer_info get_buffer_info() { return py::buffer_info(&value, 1); }
     };
     py::class_<BufferReadOnly>(m, "BufferReadOnly", py::buffer_protocol())
         .def(py::init<uint8_t>())
@@ -183,9 +195,7 @@ TEST_SUBMODULE(buffers, m) {
         uint8_t value = 0;
         bool readonly = false;
 
-        py::buffer_info get_buffer_info() {
-            return py::buffer_info(&value, 1, readonly);
-        }
+        py::buffer_info get_buffer_info() { return py::buffer_info(&value, 1, readonly); }
     };
     py::class_<BufferReadOnlySelect>(m, "BufferReadOnlySelect", py::buffer_protocol())
         .def(py::init<>())
@@ -204,11 +214,11 @@ TEST_SUBMODULE(buffers, m) {
         .def_readonly("strides", &py::buffer_info::strides)
         .def_readonly("readonly", &py::buffer_info::readonly)
         .def("__repr__", [](py::handle self) {
-             return py::str("itemsize={0.itemsize!r}, size={0.size!r}, format={0.format!r}, ndim={0.ndim!r}, shape={0.shape!r}, strides={0.strides!r}, readonly={0.readonly!r}").format(self);
-        })
-        ;
+            return py::str("itemsize={0.itemsize!r}, size={0.size!r}, format={0.format!r}, "
+                           "ndim={0.ndim!r}, shape={0.shape!r}, strides={0.strides!r}, "
+                           "readonly={0.readonly!r}")
+                .format(self);
+        });
 
-    m.def("get_buffer_info", [](py::buffer buffer) {
-        return buffer.request();
-    });
+    m.def("get_buffer_info", [](const py::buffer &buffer) { return buffer.request(); });
 }
diff --git a/3rdparty/pybind11/tests/test_buffers.py b/3rdparty/pybind11/tests/test_buffers.py
index f0f370844b..8354b68cda 100644
--- a/3rdparty/pybind11/tests/test_buffers.py
+++ b/3rdparty/pybind11/tests/test_buffers.py
@@ -1,14 +1,12 @@
-# -*- coding: utf-8 -*-
+import ctypes
 import io
 import struct
-import ctypes
 
 import pytest
 
-import env  # noqa: F401
-
-from pybind11_tests import buffers as m
+import env
 from pybind11_tests import ConstructorStats
+from pybind11_tests import buffers as m
 
 np = pytest.importorskip("numpy")
 
@@ -37,6 +35,10 @@ def test_from_python():
 
 
 # https://foss.heptapod.net/pypy/pypy/-/issues/2444
+# TODO: fix on recent PyPy
+@pytest.mark.xfail(
+    env.PYPY, reason="PyPy 7.3.7 doesn't clear this anymore", strict=False
+)
 def test_to_python():
     mat = m.Matrix(5, 4)
     assert memoryview(mat).shape == (5, 4)
@@ -90,14 +92,16 @@ def test_pointer_to_member_fn():
 def test_readonly_buffer():
     buf = m.BufferReadOnly(0x64)
     view = memoryview(buf)
-    assert view[0] == b"d" if env.PY2 else 0x64
+    assert view[0] == 0x64
     assert view.readonly
+    with pytest.raises(TypeError):
+        view[0] = 0
 
 
 def test_selective_readonly_buffer():
     buf = m.BufferReadOnlySelect()
 
-    memoryview(buf)[0] = b"d" if env.PY2 else 0x64
+    memoryview(buf)[0] = 0x64
     assert buf.value == 0x64
 
     io.BytesIO(b"A").readinto(buf)
@@ -105,7 +109,7 @@ def test_selective_readonly_buffer():
 
     buf.readonly = True
     with pytest.raises(TypeError):
-        memoryview(buf)[0] = b"\0" if env.PY2 else 0
+        memoryview(buf)[0] = 0
     with pytest.raises(TypeError):
         io.BytesIO(b"1").readinto(buf)
 
@@ -140,9 +144,6 @@ def test_ctypes_array_2d():
         assert not info.readonly
 
 
-@pytest.mark.skipif(
-    "env.PYPY and env.PY2", reason="PyPy2 bytes buffer not reported as readonly"
-)
 def test_ctypes_from_buffer():
     test_pystr = b"0123456789"
     for pyarray in (test_pystr, bytearray(test_pystr)):
diff --git a/3rdparty/pybind11/tests/test_builtin_casters.cpp b/3rdparty/pybind11/tests/test_builtin_casters.cpp
index acc9f8fb36..6ff63edfc6 100644
--- a/3rdparty/pybind11/tests/test_builtin_casters.cpp
+++ b/3rdparty/pybind11/tests/test_builtin_casters.cpp
@@ -7,40 +7,117 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/complex.h>
 
-#if defined(_MSC_VER)
-#  pragma warning(push)
-#  pragma warning(disable: 4127) // warning C4127: Conditional expression is constant
-#endif
+#include "pybind11_tests.h"
+
+struct ConstRefCasted {
+    int tag;
+};
+
+PYBIND11_NAMESPACE_BEGIN(pybind11)
+PYBIND11_NAMESPACE_BEGIN(detail)
+template <>
+class type_caster<ConstRefCasted> {
+public:
+    static constexpr auto name = const_name<ConstRefCasted>();
+
+    // Input is unimportant, a new value will always be constructed based on the
+    // cast operator.
+    bool load(handle, bool) { return true; }
+
+    explicit operator ConstRefCasted &&() {
+        value = {1};
+        // NOLINTNEXTLINE(performance-move-const-arg)
+        return std::move(value);
+    }
+    explicit operator ConstRefCasted &() {
+        value = {2};
+        return value;
+    }
+    explicit operator ConstRefCasted *() {
+        value = {3};
+        return &value;
+    }
+
+    explicit operator const ConstRefCasted &() {
+        value = {4};
+        return value;
+    }
+    explicit operator const ConstRefCasted *() {
+        value = {5};
+        return &value;
+    }
+
+    // custom cast_op to explicitly propagate types to the conversion operators.
+    template <typename T_>
+    using cast_op_type =
+        /// const
+        conditional_t<
+            std::is_same<remove_reference_t<T_>, const ConstRefCasted *>::value,
+            const ConstRefCasted *,
+            conditional_t<
+                std::is_same<T_, const ConstRefCasted &>::value,
+                const ConstRefCasted &,
+                /// non-const
+                conditional_t<std::is_same<remove_reference_t<T_>, ConstRefCasted *>::value,
+                              ConstRefCasted *,
+                              conditional_t<std::is_same<T_, ConstRefCasted &>::value,
+                                            ConstRefCasted &,
+                                            /* else */ ConstRefCasted &&>>>>;
+
+private:
+    ConstRefCasted value = {0};
+};
+PYBIND11_NAMESPACE_END(detail)
+PYBIND11_NAMESPACE_END(pybind11)
 
 TEST_SUBMODULE(builtin_casters, m) {
     // test_simple_string
     m.def("string_roundtrip", [](const char *s) { return s; });
 
     // test_unicode_conversion
-    // Some test characters in utf16 and utf32 encodings.  The last one (the 𝐀) contains a null byte
-    char32_t a32 = 0x61 /*a*/, z32 = 0x7a /*z*/, ib32 = 0x203d /*‽*/, cake32 = 0x1f382 /*🎂*/,              mathbfA32 = 0x1d400 /*𝐀*/;
-    char16_t b16 = 0x62 /*b*/, z16 = 0x7a,       ib16 = 0x203d,       cake16_1 = 0xd83c, cake16_2 = 0xdf82, mathbfA16_1 = 0xd835, mathbfA16_2 = 0xdc00;
+    // Some test characters in utf16 and utf32 encodings.  The last one (the 𝐀) contains a null
+    // byte
+    char32_t a32 = 0x61 /*a*/, z32 = 0x7a /*z*/, ib32 = 0x203d /*‽*/, cake32 = 0x1f382 /*🎂*/,
+             mathbfA32 = 0x1d400 /*𝐀*/;
+    char16_t b16 = 0x62 /*b*/, z16 = 0x7a, ib16 = 0x203d, cake16_1 = 0xd83c, cake16_2 = 0xdf82,
+             mathbfA16_1 = 0xd835, mathbfA16_2 = 0xdc00;
     std::wstring wstr;
-    wstr.push_back(0x61); // a
+    wstr.push_back(0x61);   // a
     wstr.push_back(0x2e18); // ⸘
-    if (sizeof(wchar_t) == 2) { wstr.push_back(mathbfA16_1); wstr.push_back(mathbfA16_2); } // 𝐀, utf16
-    else { wstr.push_back((wchar_t) mathbfA32); } // 𝐀, utf32
+    if (PYBIND11_SILENCE_MSVC_C4127(sizeof(wchar_t) == 2)) {
+        wstr.push_back(mathbfA16_1);
+        wstr.push_back(mathbfA16_2);
+    } // 𝐀, utf16
+    else {
+        wstr.push_back((wchar_t) mathbfA32);
+    }                     // 𝐀, utf32
     wstr.push_back(0x7a); // z
 
-    m.def("good_utf8_string", []() { return std::string((const char*)u8"Say utf8\u203d \U0001f382 \U0001d400"); }); // Say utf8‽ 🎂 𝐀
-    m.def("good_utf16_string", [=]() { return std::u16string({ b16, ib16, cake16_1, cake16_2, mathbfA16_1, mathbfA16_2, z16 }); }); // b‽🎂𝐀z
-    m.def("good_utf32_string", [=]() { return std::u32string({ a32, mathbfA32, cake32, ib32, z32 }); }); // a𝐀🎂‽z
+    m.def("good_utf8_string", []() {
+        return std::string((const char *) u8"Say utf8\u203d \U0001f382 \U0001d400");
+    }); // Say utf8‽ 🎂 𝐀
+    m.def("good_utf16_string", [=]() {
+        return std::u16string({b16, ib16, cake16_1, cake16_2, mathbfA16_1, mathbfA16_2, z16});
+    }); // b‽🎂𝐀z
+    m.def("good_utf32_string", [=]() {
+        return std::u32string({a32, mathbfA32, cake32, ib32, z32});
+    });                                                 // a𝐀🎂‽z
     m.def("good_wchar_string", [=]() { return wstr; }); // a‽𝐀z
-    m.def("bad_utf8_string", []()  { return std::string("abc\xd0" "def"); });
-    m.def("bad_utf16_string", [=]() { return std::u16string({ b16, char16_t(0xd800), z16 }); });
-    // Under Python 2.7, invalid unicode UTF-32 characters don't appear to trigger UnicodeDecodeError
-    if (PY_MAJOR_VERSION >= 3)
-        m.def("bad_utf32_string", [=]() { return std::u32string({ a32, char32_t(0xd800), z32 }); });
-    if (PY_MAJOR_VERSION >= 3 || sizeof(wchar_t) == 2)
-        m.def("bad_wchar_string", [=]() { return std::wstring({ wchar_t(0x61), wchar_t(0xd800) }); });
+    m.def("bad_utf8_string", []() {
+        return std::string("abc\xd0"
+                           "def");
+    });
+    m.def("bad_utf16_string", [=]() { return std::u16string({b16, char16_t(0xd800), z16}); });
+    // Under Python 2.7, invalid unicode UTF-32 characters didn't appear to trigger
+    // UnicodeDecodeError
+    m.def("bad_utf32_string", [=]() { return std::u32string({a32, char32_t(0xd800), z32}); });
+    if (PYBIND11_SILENCE_MSVC_C4127(sizeof(wchar_t) == 2)) {
+        m.def("bad_wchar_string", [=]() {
+            return std::wstring({wchar_t(0x61), wchar_t(0xd800)});
+        });
+    }
     m.def("u8_Z", []() -> char { return 'Z'; });
     m.def("u8_eacute", []() -> char { return '\xe9'; });
     m.def("u16_ibang", [=]() -> char16_t { return ib16; });
@@ -58,12 +135,17 @@ TEST_SUBMODULE(builtin_casters, m) {
 
     // test_bytes_to_string
     m.def("strlen", [](char *s) { return strlen(s); });
-    m.def("string_length", [](std::string s) { return s.length(); });
+    m.def("string_length", [](const std::string &s) { return s.length(); });
 
 #ifdef PYBIND11_HAS_U8STRING
     m.attr("has_u8string") = true;
-    m.def("good_utf8_u8string", []() { return std::u8string(u8"Say utf8\u203d \U0001f382 \U0001d400"); }); // Say utf8‽ 🎂 𝐀
-    m.def("bad_utf8_u8string", []()  { return std::u8string((const char8_t*)"abc\xd0" "def"); });
+    m.def("good_utf8_u8string", []() {
+        return std::u8string(u8"Say utf8\u203d \U0001f382 \U0001d400");
+    }); // Say utf8‽ 🎂 𝐀
+    m.def("bad_utf8_u8string", []() {
+        return std::u8string((const char8_t *) "abc\xd0"
+                                               "def");
+    });
 
     m.def("u8_char8_Z", []() -> char8_t { return u8'Z'; });
 
@@ -75,21 +157,72 @@ TEST_SUBMODULE(builtin_casters, m) {
     // test_string_view
 #ifdef PYBIND11_HAS_STRING_VIEW
     m.attr("has_string_view") = true;
-    m.def("string_view_print",   [](std::string_view s)    { py::print(s, s.size()); });
+    m.def("string_view_print", [](std::string_view s) { py::print(s, s.size()); });
     m.def("string_view16_print", [](std::u16string_view s) { py::print(s, s.size()); });
     m.def("string_view32_print", [](std::u32string_view s) { py::print(s, s.size()); });
-    m.def("string_view_chars",   [](std::string_view s)    { py::list l; for (auto c : s) l.append((std::uint8_t) c); return l; });
-    m.def("string_view16_chars", [](std::u16string_view s) { py::list l; for (auto c : s) l.append((int) c); return l; });
-    m.def("string_view32_chars", [](std::u32string_view s) { py::list l; for (auto c : s) l.append((int) c); return l; });
-    m.def("string_view_return",   []() { return std::string_view((const char*)u8"utf8 secret \U0001f382"); });
-    m.def("string_view16_return", []() { return std::u16string_view(u"utf16 secret \U0001f382"); });
-    m.def("string_view32_return", []() { return std::u32string_view(U"utf32 secret \U0001f382"); });
-
-#   ifdef PYBIND11_HAS_U8STRING
-    m.def("string_view8_print",  [](std::u8string_view s) { py::print(s, s.size()); });
-    m.def("string_view8_chars",  [](std::u8string_view s) { py::list l; for (auto c : s) l.append((std::uint8_t) c); return l; });
+    m.def("string_view_chars", [](std::string_view s) {
+        py::list l;
+        for (auto c : s) {
+            l.append((std::uint8_t) c);
+        }
+        return l;
+    });
+    m.def("string_view16_chars", [](std::u16string_view s) {
+        py::list l;
+        for (auto c : s) {
+            l.append((int) c);
+        }
+        return l;
+    });
+    m.def("string_view32_chars", [](std::u32string_view s) {
+        py::list l;
+        for (auto c : s) {
+            l.append((int) c);
+        }
+        return l;
+    });
+    m.def("string_view_return",
+          []() { return std::string_view((const char *) u8"utf8 secret \U0001f382"); });
+    m.def("string_view16_return",
+          []() { return std::u16string_view(u"utf16 secret \U0001f382"); });
+    m.def("string_view32_return",
+          []() { return std::u32string_view(U"utf32 secret \U0001f382"); });
+
+    // The inner lambdas here are to also test implicit conversion
+    using namespace std::literals;
+    m.def("string_view_bytes",
+          []() { return [](py::bytes b) { return b; }("abc \x80\x80 def"sv); });
+    m.def("string_view_str",
+          []() { return [](py::str s) { return s; }("abc \342\200\275 def"sv); });
+    m.def("string_view_from_bytes",
+          [](const py::bytes &b) { return [](std::string_view s) { return s; }(b); });
+    m.def("string_view_memoryview", []() {
+        static constexpr auto val = "Have some \360\237\216\202"sv;
+        return py::memoryview::from_memory(val);
+    });
+
+#    ifdef PYBIND11_HAS_U8STRING
+    m.def("string_view8_print", [](std::u8string_view s) { py::print(s, s.size()); });
+    m.def("string_view8_chars", [](std::u8string_view s) {
+        py::list l;
+        for (auto c : s)
+            l.append((std::uint8_t) c);
+        return l;
+    });
     m.def("string_view8_return", []() { return std::u8string_view(u8"utf8 secret \U0001f382"); });
-#   endif
+    m.def("string_view8_str", []() { return py::str{std::u8string_view{u8"abc ‽ def"}}; });
+#    endif
+
+    struct TypeWithBothOperatorStringAndStringView {
+        // NOLINTNEXTLINE(google-explicit-constructor)
+        operator std::string() const { return "success"; }
+        // NOLINTNEXTLINE(google-explicit-constructor)
+        operator std::string_view() const { return "failure"; }
+    };
+    m.def("bytes_from_type_with_both_operator_string_and_string_view",
+          []() { return py::bytes(TypeWithBothOperatorStringAndStringView()); });
+    m.def("str_from_type_with_both_operator_string_and_string_view",
+          []() { return py::str(TypeWithBothOperatorStringAndStringView()); });
 #endif
 
     // test_integer_casting
@@ -98,71 +231,121 @@ TEST_SUBMODULE(builtin_casters, m) {
     m.def("i64_str", [](std::int64_t v) { return std::to_string(v); });
     m.def("u64_str", [](std::uint64_t v) { return std::to_string(v); });
 
+    // test_int_convert
+    m.def("int_passthrough", [](int arg) { return arg; });
+    m.def(
+        "int_passthrough_noconvert", [](int arg) { return arg; }, py::arg{}.noconvert());
+
     // test_tuple
-    m.def("pair_passthrough", [](std::pair<bool, std::string> input) {
-        return std::make_pair(input.second, input.first);
-    }, "Return a pair in reversed order");
-    m.def("tuple_passthrough", [](std::tuple<bool, std::string, int> input) {
-        return std::make_tuple(std::get<2>(input), std::get<1>(input), std::get<0>(input));
-    }, "Return a triple in reversed order");
+    m.def(
+        "pair_passthrough",
+        [](const std::pair<bool, std::string> &input) {
+            return std::make_pair(input.second, input.first);
+        },
+        "Return a pair in reversed order");
+    m.def(
+        "tuple_passthrough",
+        [](std::tuple<bool, std::string, int> input) {
+            return std::make_tuple(std::get<2>(input), std::get<1>(input), std::get<0>(input));
+        },
+        "Return a triple in reversed order");
     m.def("empty_tuple", []() { return std::tuple<>(); });
     static std::pair<RValueCaster, RValueCaster> lvpair;
     static std::tuple<RValueCaster, RValueCaster, RValueCaster> lvtuple;
-    static std::pair<RValueCaster, std::tuple<RValueCaster, std::pair<RValueCaster, RValueCaster>>> lvnested;
+    static std::pair<RValueCaster, std::tuple<RValueCaster, std::pair<RValueCaster, RValueCaster>>>
+        lvnested;
     m.def("rvalue_pair", []() { return std::make_pair(RValueCaster{}, RValueCaster{}); });
     m.def("lvalue_pair", []() -> const decltype(lvpair) & { return lvpair; });
-    m.def("rvalue_tuple", []() { return std::make_tuple(RValueCaster{}, RValueCaster{}, RValueCaster{}); });
+    m.def("rvalue_tuple",
+          []() { return std::make_tuple(RValueCaster{}, RValueCaster{}, RValueCaster{}); });
     m.def("lvalue_tuple", []() -> const decltype(lvtuple) & { return lvtuple; });
     m.def("rvalue_nested", []() {
-        return std::make_pair(RValueCaster{}, std::make_tuple(RValueCaster{}, std::make_pair(RValueCaster{}, RValueCaster{}))); });
+        return std::make_pair(
+            RValueCaster{},
+            std::make_tuple(RValueCaster{}, std::make_pair(RValueCaster{}, RValueCaster{})));
+    });
     m.def("lvalue_nested", []() -> const decltype(lvnested) & { return lvnested; });
 
-    static std::pair<int, std::string> int_string_pair{2, "items"};
-    m.def("int_string_pair", []() { return &int_string_pair; });
+    m.def(
+        "int_string_pair",
+        []() {
+            // Using no-destructor idiom to side-step warnings from overzealous compilers.
+            static auto *int_string_pair = new std::pair<int, std::string>{2, "items"};
+            return int_string_pair;
+        },
+        py::return_value_policy::reference);
 
     // test_builtins_cast_return_none
     m.def("return_none_string", []() -> std::string * { return nullptr; });
-    m.def("return_none_char",   []() -> const char *  { return nullptr; });
-    m.def("return_none_bool",   []() -> bool *        { return nullptr; });
-    m.def("return_none_int",    []() -> int *         { return nullptr; });
-    m.def("return_none_float",  []() -> float *       { return nullptr; });
-    m.def("return_none_pair",   []() -> std::pair<int,int> * { return nullptr; });
+    m.def("return_none_char", []() -> const char * { return nullptr; });
+    m.def("return_none_bool", []() -> bool * { return nullptr; });
+    m.def("return_none_int", []() -> int * { return nullptr; });
+    m.def("return_none_float", []() -> float * { return nullptr; });
+    m.def("return_none_pair", []() -> std::pair<int, int> * { return nullptr; });
 
     // test_none_deferred
     m.def("defer_none_cstring", [](char *) { return false; });
-    m.def("defer_none_cstring", [](py::none) { return true; });
+    m.def("defer_none_cstring", [](const py::none &) { return true; });
     m.def("defer_none_custom", [](UserType *) { return false; });
-    m.def("defer_none_custom", [](py::none) { return true; });
+    m.def("defer_none_custom", [](const py::none &) { return true; });
     m.def("nodefer_none_void", [](void *) { return true; });
-    m.def("nodefer_none_void", [](py::none) { return false; });
+    m.def("nodefer_none_void", [](const py::none &) { return false; });
 
     // test_void_caster
     m.def("load_nullptr_t", [](std::nullptr_t) {}); // not useful, but it should still compile
     m.def("cast_nullptr_t", []() { return std::nullptr_t{}; });
 
+    // [workaround(intel)] ICC 20/21 breaks with py::arg().stuff, using py::arg{}.stuff works.
+
     // test_bool_caster
     m.def("bool_passthrough", [](bool arg) { return arg; });
-    m.def("bool_passthrough_noconvert", [](bool arg) { return arg; }, py::arg().noconvert());
+    m.def(
+        "bool_passthrough_noconvert", [](bool arg) { return arg; }, py::arg{}.noconvert());
+
+    // TODO: This should be disabled and fixed in future Intel compilers
+#if !defined(__INTEL_COMPILER)
+    // Test "bool_passthrough_noconvert" again, but using () instead of {} to construct py::arg
+    // When compiled with the Intel compiler, this results in segmentation faults when importing
+    // the module. Tested with icc (ICC) 2021.1 Beta 20200827, this should be tested again when
+    // a newer version of icc is available.
+    m.def(
+        "bool_passthrough_noconvert2", [](bool arg) { return arg; }, py::arg().noconvert());
+#endif
 
     // test_reference_wrapper
     m.def("refwrap_builtin", [](std::reference_wrapper<int> p) { return 10 * p.get(); });
     m.def("refwrap_usertype", [](std::reference_wrapper<UserType> p) { return p.get().value(); });
+    m.def("refwrap_usertype_const",
+          [](std::reference_wrapper<const UserType> p) { return p.get().value(); });
+
+    m.def("refwrap_lvalue", []() -> std::reference_wrapper<UserType> {
+        static UserType x(1);
+        return std::ref(x);
+    });
+    m.def("refwrap_lvalue_const", []() -> std::reference_wrapper<const UserType> {
+        static UserType x(1);
+        return std::cref(x);
+    });
+
     // Not currently supported (std::pair caster has return-by-value cast operator);
     // triggers static_assert failure.
-    //m.def("refwrap_pair", [](std::reference_wrapper<std::pair<int, int>>) { });
+    // m.def("refwrap_pair", [](std::reference_wrapper<std::pair<int, int>>) { });
 
-    m.def("refwrap_list", [](bool copy) {
-        static IncType x1(1), x2(2);
-        py::list l;
-        for (auto &f : {std::ref(x1), std::ref(x2)}) {
-            l.append(py::cast(f, copy ? py::return_value_policy::copy
-                                      : py::return_value_policy::reference));
-        }
-        return l;
-    }, "copy"_a);
+    m.def(
+        "refwrap_list",
+        [](bool copy) {
+            static IncType x1(1), x2(2);
+            py::list l;
+            for (const auto &f : {std::ref(x1), std::ref(x2)}) {
+                l.append(py::cast(
+                    f, copy ? py::return_value_policy::copy : py::return_value_policy::reference));
+            }
+            return l;
+        },
+        "copy"_a);
 
     m.def("refwrap_iiw", [](const IncType &w) { return w.value(); });
-    m.def("refwrap_call_iiw", [](IncType &w, py::function f) {
+    m.def("refwrap_call_iiw", [](IncType &w, const py::function &f) {
         py::list l;
         l.append(f(std::ref(w)));
         l.append(f(std::cref(w)));
@@ -176,12 +359,13 @@ TEST_SUBMODULE(builtin_casters, m) {
 
     // test_complex
     m.def("complex_cast", [](float x) { return "{}"_s.format(x); });
-    m.def("complex_cast", [](std::complex<float> x) { return "({}, {})"_s.format(x.real(), x.imag()); });
+    m.def("complex_cast",
+          [](std::complex<float> x) { return "({}, {})"_s.format(x.real(), x.imag()); });
 
     // test int vs. long (Python 2)
-    m.def("int_cast", []() {return (int) 42;});
-    m.def("long_cast", []() {return (long) 42;});
-    m.def("longlong_cast", []() {return  ULLONG_MAX;});
+    m.def("int_cast", []() { return (int) 42; });
+    m.def("long_cast", []() { return (long) 42; });
+    m.def("longlong_cast", []() { return ULLONG_MAX; });
 
     /// test void* cast operator
     m.def("test_void_caster", []() -> bool {
@@ -189,4 +373,15 @@ TEST_SUBMODULE(builtin_casters, m) {
         py::object o = py::cast(v);
         return py::cast<void *>(o) == v;
     });
+
+    // Tests const/non-const propagation in cast_op.
+    m.def("takes", [](ConstRefCasted x) { return x.tag; });
+    m.def("takes_move", [](ConstRefCasted &&x) { return x.tag; });
+    m.def("takes_ptr", [](ConstRefCasted *x) { return x->tag; });
+    m.def("takes_ref", [](ConstRefCasted &x) { return x.tag; });
+    m.def("takes_ref_wrap", [](std::reference_wrapper<ConstRefCasted> x) { return x.get().tag; });
+    m.def("takes_const_ptr", [](const ConstRefCasted *x) { return x->tag; });
+    m.def("takes_const_ref", [](const ConstRefCasted &x) { return x.tag; });
+    m.def("takes_const_ref_wrap",
+          [](std::reference_wrapper<const ConstRefCasted> x) { return x.get().tag; });
 }
diff --git a/3rdparty/pybind11/tests/test_builtin_casters.py b/3rdparty/pybind11/tests/test_builtin_casters.py
index bd7996b620..d38ae68028 100644
--- a/3rdparty/pybind11/tests/test_builtin_casters.py
+++ b/3rdparty/pybind11/tests/test_builtin_casters.py
@@ -1,10 +1,10 @@
-# -*- coding: utf-8 -*-
-import pytest
+import sys
 
-import env  # noqa: F401
+import pytest
 
+import env
+from pybind11_tests import IncType, UserType
 from pybind11_tests import builtin_casters as m
-from pybind11_tests import UserType, IncType
 
 
 def test_simple_string():
@@ -13,12 +13,12 @@ def test_simple_string():
 
 def test_unicode_conversion():
     """Tests unicode conversion and error reporting."""
-    assert m.good_utf8_string() == u"Say utf8‽ 🎂 𝐀"
-    assert m.good_utf16_string() == u"b‽🎂𝐀z"
-    assert m.good_utf32_string() == u"a𝐀🎂‽z"
-    assert m.good_wchar_string() == u"a⸘𝐀z"
+    assert m.good_utf8_string() == "Say utf8‽ 🎂 𝐀"
+    assert m.good_utf16_string() == "b‽🎂𝐀z"
+    assert m.good_utf32_string() == "a𝐀🎂‽z"
+    assert m.good_wchar_string() == "a⸘𝐀z"
     if hasattr(m, "has_u8string"):
-        assert m.good_utf8_u8string() == u"Say utf8‽ 🎂 𝐀"
+        assert m.good_utf8_u8string() == "Say utf8‽ 🎂 𝐀"
 
     with pytest.raises(UnicodeDecodeError):
         m.bad_utf8_string()
@@ -26,7 +26,7 @@ def test_unicode_conversion():
     with pytest.raises(UnicodeDecodeError):
         m.bad_utf16_string()
 
-    # These are provided only if they actually fail (they don't when 32-bit and under Python 2.7)
+    # These are provided only if they actually fail (they don't when 32-bit)
     if hasattr(m, "bad_utf32_string"):
         with pytest.raises(UnicodeDecodeError):
             m.bad_utf32_string()
@@ -38,10 +38,10 @@ def test_unicode_conversion():
             m.bad_utf8_u8string()
 
     assert m.u8_Z() == "Z"
-    assert m.u8_eacute() == u"é"
-    assert m.u16_ibang() == u"‽"
-    assert m.u32_mathbfA() == u"𝐀"
-    assert m.wchar_heart() == u"♥"
+    assert m.u8_eacute() == "é"
+    assert m.u16_ibang() == "‽"
+    assert m.u32_mathbfA() == "𝐀"
+    assert m.wchar_heart() == "♥"
     if hasattr(m, "has_u8string"):
         assert m.u8_char8_Z() == "Z"
 
@@ -50,72 +50,72 @@ def test_single_char_arguments():
     """Tests failures for passing invalid inputs to char-accepting functions"""
 
     def toobig_message(r):
-        return "Character code point not in range({0:#x})".format(r)
+        return f"Character code point not in range({r:#x})"
 
     toolong_message = "Expected a character, but multi-character string found"
 
-    assert m.ord_char(u"a") == 0x61  # simple ASCII
-    assert m.ord_char_lv(u"b") == 0x62
+    assert m.ord_char("a") == 0x61  # simple ASCII
+    assert m.ord_char_lv("b") == 0x62
     assert (
-        m.ord_char(u"é") == 0xE9
+        m.ord_char("é") == 0xE9
     )  # requires 2 bytes in utf-8, but can be stuffed in a char
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_char(u"Ā") == 0x100  # requires 2 bytes, doesn't fit in a char
+        assert m.ord_char("Ā") == 0x100  # requires 2 bytes, doesn't fit in a char
     assert str(excinfo.value) == toobig_message(0x100)
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_char(u"ab")
+        assert m.ord_char("ab")
     assert str(excinfo.value) == toolong_message
 
-    assert m.ord_char16(u"a") == 0x61
-    assert m.ord_char16(u"é") == 0xE9
-    assert m.ord_char16_lv(u"ê") == 0xEA
-    assert m.ord_char16(u"Ā") == 0x100
-    assert m.ord_char16(u"‽") == 0x203D
-    assert m.ord_char16(u"♥") == 0x2665
-    assert m.ord_char16_lv(u"♡") == 0x2661
+    assert m.ord_char16("a") == 0x61
+    assert m.ord_char16("é") == 0xE9
+    assert m.ord_char16_lv("ê") == 0xEA
+    assert m.ord_char16("Ā") == 0x100
+    assert m.ord_char16("‽") == 0x203D
+    assert m.ord_char16("♥") == 0x2665
+    assert m.ord_char16_lv("♡") == 0x2661
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_char16(u"🎂") == 0x1F382  # requires surrogate pair
+        assert m.ord_char16("🎂") == 0x1F382  # requires surrogate pair
     assert str(excinfo.value) == toobig_message(0x10000)
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_char16(u"aa")
+        assert m.ord_char16("aa")
     assert str(excinfo.value) == toolong_message
 
-    assert m.ord_char32(u"a") == 0x61
-    assert m.ord_char32(u"é") == 0xE9
-    assert m.ord_char32(u"Ā") == 0x100
-    assert m.ord_char32(u"‽") == 0x203D
-    assert m.ord_char32(u"♥") == 0x2665
-    assert m.ord_char32(u"🎂") == 0x1F382
+    assert m.ord_char32("a") == 0x61
+    assert m.ord_char32("é") == 0xE9
+    assert m.ord_char32("Ā") == 0x100
+    assert m.ord_char32("‽") == 0x203D
+    assert m.ord_char32("♥") == 0x2665
+    assert m.ord_char32("🎂") == 0x1F382
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_char32(u"aa")
+        assert m.ord_char32("aa")
     assert str(excinfo.value) == toolong_message
 
-    assert m.ord_wchar(u"a") == 0x61
-    assert m.ord_wchar(u"é") == 0xE9
-    assert m.ord_wchar(u"Ā") == 0x100
-    assert m.ord_wchar(u"‽") == 0x203D
-    assert m.ord_wchar(u"♥") == 0x2665
+    assert m.ord_wchar("a") == 0x61
+    assert m.ord_wchar("é") == 0xE9
+    assert m.ord_wchar("Ā") == 0x100
+    assert m.ord_wchar("‽") == 0x203D
+    assert m.ord_wchar("♥") == 0x2665
     if m.wchar_size == 2:
         with pytest.raises(ValueError) as excinfo:
-            assert m.ord_wchar(u"🎂") == 0x1F382  # requires surrogate pair
+            assert m.ord_wchar("🎂") == 0x1F382  # requires surrogate pair
         assert str(excinfo.value) == toobig_message(0x10000)
     else:
-        assert m.ord_wchar(u"🎂") == 0x1F382
+        assert m.ord_wchar("🎂") == 0x1F382
     with pytest.raises(ValueError) as excinfo:
-        assert m.ord_wchar(u"aa")
+        assert m.ord_wchar("aa")
     assert str(excinfo.value) == toolong_message
 
     if hasattr(m, "has_u8string"):
-        assert m.ord_char8(u"a") == 0x61  # simple ASCII
-        assert m.ord_char8_lv(u"b") == 0x62
+        assert m.ord_char8("a") == 0x61  # simple ASCII
+        assert m.ord_char8_lv("b") == 0x62
         assert (
-            m.ord_char8(u"é") == 0xE9
+            m.ord_char8("é") == 0xE9
         )  # requires 2 bytes in utf-8, but can be stuffed in a char
         with pytest.raises(ValueError) as excinfo:
-            assert m.ord_char8(u"Ā") == 0x100  # requires 2 bytes, doesn't fit in a char
+            assert m.ord_char8("Ā") == 0x100  # requires 2 bytes, doesn't fit in a char
         assert str(excinfo.value) == toobig_message(0x100)
         with pytest.raises(ValueError) as excinfo:
-            assert m.ord_char8(u"ab")
+            assert m.ord_char8("ab")
         assert str(excinfo.value) == toolong_message
 
 
@@ -124,18 +124,22 @@ def test_bytes_to_string():
     one-way: the only way to return bytes to Python is via the pybind11::bytes class."""
     # Issue #816
 
-    def to_bytes(s):
-        b = s if env.PY2 else s.encode("utf8")
-        assert isinstance(b, bytes)
-        return b
-
-    assert m.strlen(to_bytes("hi")) == 2
-    assert m.string_length(to_bytes("world")) == 5
-    assert m.string_length(to_bytes("a\x00b")) == 3
-    assert m.strlen(to_bytes("a\x00b")) == 1  # C-string limitation
+    assert m.strlen(b"hi") == 2
+    assert m.string_length(b"world") == 5
+    assert m.string_length("a\x00b".encode()) == 3
+    assert m.strlen("a\x00b".encode()) == 1  # C-string limitation
 
     # passing in a utf8 encoded string should work
-    assert m.string_length(u"💩".encode("utf8")) == 4
+    assert m.string_length("💩".encode()) == 4
+
+
+def test_bytearray_to_string():
+    """Tests the ability to pass bytearray to C++ string-accepting functions"""
+    assert m.string_length(bytearray(b"Hi")) == 2
+    assert m.strlen(bytearray(b"bytearray")) == 9
+    assert m.string_length(bytearray()) == 0
+    assert m.string_length(bytearray("🦜", "utf-8", "strict")) == 4
+    assert m.string_length(bytearray(b"\x80")) == 1
 
 
 @pytest.mark.skipif(not hasattr(m, "has_string_view"), reason="no <string_view>")
@@ -143,26 +147,26 @@ def test_string_view(capture):
     """Tests support for C++17 string_view arguments and return values"""
     assert m.string_view_chars("Hi") == [72, 105]
     assert m.string_view_chars("Hi 🎂") == [72, 105, 32, 0xF0, 0x9F, 0x8E, 0x82]
-    assert m.string_view16_chars(u"Hi 🎂") == [72, 105, 32, 0xD83C, 0xDF82]
-    assert m.string_view32_chars(u"Hi 🎂") == [72, 105, 32, 127874]
+    assert m.string_view16_chars("Hi 🎂") == [72, 105, 32, 0xD83C, 0xDF82]
+    assert m.string_view32_chars("Hi 🎂") == [72, 105, 32, 127874]
     if hasattr(m, "has_u8string"):
         assert m.string_view8_chars("Hi") == [72, 105]
-        assert m.string_view8_chars(u"Hi 🎂") == [72, 105, 32, 0xF0, 0x9F, 0x8E, 0x82]
+        assert m.string_view8_chars("Hi 🎂") == [72, 105, 32, 0xF0, 0x9F, 0x8E, 0x82]
 
-    assert m.string_view_return() == u"utf8 secret 🎂"
-    assert m.string_view16_return() == u"utf16 secret 🎂"
-    assert m.string_view32_return() == u"utf32 secret 🎂"
+    assert m.string_view_return() == "utf8 secret 🎂"
+    assert m.string_view16_return() == "utf16 secret 🎂"
+    assert m.string_view32_return() == "utf32 secret 🎂"
     if hasattr(m, "has_u8string"):
-        assert m.string_view8_return() == u"utf8 secret 🎂"
+        assert m.string_view8_return() == "utf8 secret 🎂"
 
     with capture:
         m.string_view_print("Hi")
         m.string_view_print("utf8 🎂")
-        m.string_view16_print(u"utf16 🎂")
-        m.string_view32_print(u"utf32 🎂")
+        m.string_view16_print("utf16 🎂")
+        m.string_view32_print("utf32 🎂")
     assert (
         capture
-        == u"""
+        == """
         Hi 2
         utf8 🎂 9
         utf16 🎂 8
@@ -172,10 +176,10 @@ def test_string_view(capture):
     if hasattr(m, "has_u8string"):
         with capture:
             m.string_view8_print("Hi")
-            m.string_view8_print(u"utf8 🎂")
+            m.string_view8_print("utf8 🎂")
         assert (
             capture
-            == u"""
+            == """
             Hi 2
             utf8 🎂 9
         """
@@ -184,11 +188,11 @@ def test_string_view(capture):
     with capture:
         m.string_view_print("Hi, ascii")
         m.string_view_print("Hi, utf8 🎂")
-        m.string_view16_print(u"Hi, utf16 🎂")
-        m.string_view32_print(u"Hi, utf32 🎂")
+        m.string_view16_print("Hi, utf16 🎂")
+        m.string_view32_print("Hi, utf32 🎂")
     assert (
         capture
-        == u"""
+        == """
         Hi, ascii 9
         Hi, utf8 🎂 13
         Hi, utf16 🎂 12
@@ -198,15 +202,25 @@ def test_string_view(capture):
     if hasattr(m, "has_u8string"):
         with capture:
             m.string_view8_print("Hi, ascii")
-            m.string_view8_print(u"Hi, utf8 🎂")
+            m.string_view8_print("Hi, utf8 🎂")
         assert (
             capture
-            == u"""
+            == """
             Hi, ascii 9
             Hi, utf8 🎂 13
         """
         )
 
+    assert m.string_view_bytes() == b"abc \x80\x80 def"
+    assert m.string_view_str() == "abc ‽ def"
+    assert m.string_view_from_bytes("abc ‽ def".encode()) == "abc ‽ def"
+    if hasattr(m, "has_u8string"):
+        assert m.string_view8_str() == "abc ‽ def"
+    assert m.string_view_memoryview() == "Have some 🎂".encode()
+
+    assert m.bytes_from_type_with_both_operator_string_and_string_view() == b"success"
+    assert m.str_from_type_with_both_operator_string_and_string_view() == "success"
+
 
 def test_integer_casting():
     """Issue #929 - out-of-range integer values shouldn't be accepted"""
@@ -214,20 +228,8 @@ def test_integer_casting():
     assert m.i64_str(-1) == "-1"
     assert m.i32_str(2000000000) == "2000000000"
     assert m.u32_str(2000000000) == "2000000000"
-    if env.PY2:
-        assert m.i32_str(long(-1)) == "-1"  # noqa: F821 undefined name 'long'
-        assert m.i64_str(long(-1)) == "-1"  # noqa: F821 undefined name 'long'
-        assert (
-            m.i64_str(long(-999999999999))  # noqa: F821 undefined name 'long'
-            == "-999999999999"
-        )
-        assert (
-            m.u64_str(long(999999999999))  # noqa: F821 undefined name 'long'
-            == "999999999999"
-        )
-    else:
-        assert m.i64_str(-999999999999) == "-999999999999"
-        assert m.u64_str(999999999999) == "999999999999"
+    assert m.i64_str(-999999999999) == "-999999999999"
+    assert m.u64_str(999999999999) == "999999999999"
 
     with pytest.raises(TypeError) as excinfo:
         m.u32_str(-1)
@@ -242,13 +244,100 @@ def test_integer_casting():
         m.i32_str(3000000000)
     assert "incompatible function arguments" in str(excinfo.value)
 
-    if env.PY2:
-        with pytest.raises(TypeError) as excinfo:
-            m.u32_str(long(-1))  # noqa: F821 undefined name 'long'
-        assert "incompatible function arguments" in str(excinfo.value)
-        with pytest.raises(TypeError) as excinfo:
-            m.u64_str(long(-1))  # noqa: F821 undefined name 'long'
-        assert "incompatible function arguments" in str(excinfo.value)
+
+def test_int_convert():
+    class Int:
+        def __int__(self):
+            return 42
+
+    class NotInt:
+        pass
+
+    class Float:
+        def __float__(self):
+            return 41.99999
+
+    class Index:
+        def __index__(self):
+            return 42
+
+    class IntAndIndex:
+        def __int__(self):
+            return 42
+
+        def __index__(self):
+            return 0
+
+    class RaisingTypeErrorOnIndex:
+        def __index__(self):
+            raise TypeError
+
+        def __int__(self):
+            return 42
+
+    class RaisingValueErrorOnIndex:
+        def __index__(self):
+            raise ValueError
+
+        def __int__(self):
+            return 42
+
+    convert, noconvert = m.int_passthrough, m.int_passthrough_noconvert
+
+    def requires_conversion(v):
+        pytest.raises(TypeError, noconvert, v)
+
+    def cant_convert(v):
+        pytest.raises(TypeError, convert, v)
+
+    assert convert(7) == 7
+    assert noconvert(7) == 7
+    cant_convert(3.14159)
+    # TODO: Avoid DeprecationWarning in `PyLong_AsLong` (and similar)
+    # TODO: PyPy 3.8 does not behave like CPython 3.8 here yet (7.3.7)
+    if (3, 8) <= sys.version_info < (3, 10) and env.CPYTHON:
+        with env.deprecated_call():
+            assert convert(Int()) == 42
+    else:
+        assert convert(Int()) == 42
+    requires_conversion(Int())
+    cant_convert(NotInt())
+    cant_convert(Float())
+
+    # Before Python 3.8, `PyLong_AsLong` does not pick up on `obj.__index__`,
+    # but pybind11 "backports" this behavior.
+    assert convert(Index()) == 42
+    assert noconvert(Index()) == 42
+    assert convert(IntAndIndex()) == 0  # Fishy; `int(DoubleThought)` == 42
+    assert noconvert(IntAndIndex()) == 0
+    assert convert(RaisingTypeErrorOnIndex()) == 42
+    requires_conversion(RaisingTypeErrorOnIndex())
+    assert convert(RaisingValueErrorOnIndex()) == 42
+    requires_conversion(RaisingValueErrorOnIndex())
+
+
+def test_numpy_int_convert():
+    np = pytest.importorskip("numpy")
+
+    convert, noconvert = m.int_passthrough, m.int_passthrough_noconvert
+
+    def require_implicit(v):
+        pytest.raises(TypeError, noconvert, v)
+
+    # `np.intc` is an alias that corresponds to a C++ `int`
+    assert convert(np.intc(42)) == 42
+    assert noconvert(np.intc(42)) == 42
+
+    # The implicit conversion from np.float32 is undesirable but currently accepted.
+    # TODO: Avoid DeprecationWarning in `PyLong_AsLong` (and similar)
+    # TODO: PyPy 3.8 does not behave like CPython 3.8 here yet (7.3.7)
+    # https://github.com/pybind/pybind11/issues/3408
+    if (3, 8) <= sys.version_info < (3, 10) and env.CPYTHON:
+        with env.deprecated_call():
+            assert convert(np.float32(3.14159)) == 3
+    else:
+        assert convert(np.float32(3.14159)) == 3
+    require_implicit(np.float32(3.14159))
 
 
 def test_tuple(doc):
@@ -315,6 +404,7 @@ def test_reference_wrapper():
     """std::reference_wrapper for builtin and user types"""
     assert m.refwrap_builtin(42) == 420
     assert m.refwrap_usertype(UserType(42)) == 42
+    assert m.refwrap_usertype_const(UserType(42)) == 42
 
     with pytest.raises(TypeError) as excinfo:
         m.refwrap_builtin(None)
@@ -324,6 +414,9 @@ def test_reference_wrapper():
         m.refwrap_usertype(None)
     assert "incompatible function arguments" in str(excinfo.value)
 
+    assert m.refwrap_lvalue().value == 1
+    assert m.refwrap_lvalue_const().value == 1
+
     a1 = m.refwrap_list(copy=True)
     a2 = m.refwrap_list(copy=True)
     assert [x.value for x in a1] == [2, 3]
@@ -366,7 +459,7 @@ def cant_convert(v):
     require_implicit(None)
     assert convert(None) is False
 
-    class A(object):
+    class A:
         def __init__(self, x):
             self.x = x
 
@@ -376,7 +469,7 @@ def __nonzero__(self):
         def __bool__(self):
             return self.x
 
-    class B(object):
+    class B:
         pass
 
     # Arbitrary objects are not accepted
@@ -406,18 +499,28 @@ def cant_convert(v):
 
 
 def test_int_long():
-    """In Python 2, a C++ int should return a Python int rather than long
-    if possible: longs are not always accepted where ints are used (such
-    as the argument to sys.exit()). A C++ long long is always a Python
-    long."""
-
-    import sys
-
-    must_be_long = type(getattr(sys, "maxint", 1) + 1)
     assert isinstance(m.int_cast(), int)
     assert isinstance(m.long_cast(), int)
-    assert isinstance(m.longlong_cast(), must_be_long)
+    assert isinstance(m.longlong_cast(), int)
 
 
 def test_void_caster_2():
     assert m.test_void_caster()
+
+
+def test_const_ref_caster():
+    """Verifies that const-ref is propagated through type_caster cast_op.
+    The returned ConstRefCasted type is a minimal type that is constructed to
+    reference the casting mode used.
+    """
+    x = False
+    assert m.takes(x) == 1
+    assert m.takes_move(x) == 1
+
+    assert m.takes_ptr(x) == 3
+    assert m.takes_ref(x) == 2
+    assert m.takes_ref_wrap(x) == 2
+
+    assert m.takes_const_ptr(x) == 5
+    assert m.takes_const_ref(x) == 4
+    assert m.takes_const_ref_wrap(x) == 4
diff --git a/3rdparty/pybind11/tests/test_call_policies.cpp b/3rdparty/pybind11/tests/test_call_policies.cpp
index 26c83f81b0..d177008cfe 100644
--- a/3rdparty/pybind11/tests/test_call_policies.cpp
+++ b/3rdparty/pybind11/tests/test_call_policies.cpp
@@ -40,17 +40,17 @@ TEST_SUBMODULE(call_policies, m) {
         Child(Child &&) = default;
         ~Child() { py::print("Releasing child."); }
     };
-    py::class_<Child>(m, "Child")
-        .def(py::init<>());
+    py::class_<Child>(m, "Child").def(py::init<>());
 
     class Parent {
     public:
         Parent() { py::print("Allocating parent."); }
-        Parent(const Parent& parent) = default;
+        Parent(const Parent &parent) = default;
         ~Parent() { py::print("Releasing parent."); }
-        void addChild(Child *) { }
+        void addChild(Child *) {}
         Child *returnChild() { return new Child(); }
         Child *returnNullChild() { return nullptr; }
+        static Child *staticFunction(Parent *) { return new Child(); }
     };
     py::class_<Parent>(m, "Parent")
         .def(py::init<>())
@@ -60,7 +60,13 @@ TEST_SUBMODULE(call_policies, m) {
         .def("returnChild", &Parent::returnChild)
         .def("returnChildKeepAlive", &Parent::returnChild, py::keep_alive<1, 0>())
         .def("returnNullChildKeepAliveChild", &Parent::returnNullChild, py::keep_alive<1, 0>())
-        .def("returnNullChildKeepAliveParent", &Parent::returnNullChild, py::keep_alive<0, 1>());
+        .def("returnNullChildKeepAliveParent", &Parent::returnNullChild, py::keep_alive<0, 1>())
+        .def_static("staticFunction", &Parent::staticFunction, py::keep_alive<1, 0>());
+
+    m.def(
+        "free_function", [](Parent *, Child *) {}, py::keep_alive<1, 2>());
+    m.def(
+        "invalid_arg_index", [] {}, py::keep_alive<0, 1>());
 
 #if !defined(PYPY_VERSION)
     // test_alive_gc
@@ -68,29 +74,37 @@ TEST_SUBMODULE(call_policies, m) {
     public:
         using Parent::Parent;
     };
-    py::class_<ParentGC, Parent>(m, "ParentGC", py::dynamic_attr())
-        .def(py::init<>());
+    py::class_<ParentGC, Parent>(m, "ParentGC", py::dynamic_attr()).def(py::init<>());
 #endif
 
     // test_call_guard
     m.def("unguarded_call", &CustomGuard::report_status);
     m.def("guarded_call", &CustomGuard::report_status, py::call_guard<CustomGuard>());
 
-    m.def("multiple_guards_correct_order", []() {
-        return CustomGuard::report_status() + std::string(" & ") + DependentGuard::report_status();
-    }, py::call_guard<CustomGuard, DependentGuard>());
-
-    m.def("multiple_guards_wrong_order", []() {
-        return DependentGuard::report_status() + std::string(" & ") + CustomGuard::report_status();
-    }, py::call_guard<DependentGuard, CustomGuard>());
+    m.def(
+        "multiple_guards_correct_order",
+        []() {
+            return CustomGuard::report_status() + std::string(" & ")
+                   + DependentGuard::report_status();
+        },
+        py::call_guard<CustomGuard, DependentGuard>());
+
+    m.def(
+        "multiple_guards_wrong_order",
+        []() {
+            return DependentGuard::report_status() + std::string(" & ")
+                   + CustomGuard::report_status();
+        },
+        py::call_guard<DependentGuard, CustomGuard>());
 
 #if defined(WITH_THREAD) && !defined(PYPY_VERSION)
     // `py::call_guard<py::gil_scoped_release>()` should work in PyPy as well,
     // but it's unclear how to test it without `PyGILState_GetThisThreadState`.
     auto report_gil_status = []() {
         auto is_gil_held = false;
-        if (auto tstate = py::detail::get_thread_state_unchecked())
+        if (auto *tstate = py::detail::get_thread_state_unchecked()) {
             is_gil_held = (tstate == PyGILState_GetThisThreadState());
+        }
 
         return is_gil_held ? "GIL held" : "GIL released";
     };
diff --git a/3rdparty/pybind11/tests/test_call_policies.py b/3rdparty/pybind11/tests/test_call_policies.py
index e0413d1451..6160564123 100644
--- a/3rdparty/pybind11/tests/test_call_policies.py
+++ b/3rdparty/pybind11/tests/test_call_policies.py
@@ -1,10 +1,8 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
-
-from pybind11_tests import call_policies as m
 from pybind11_tests import ConstructorStats
+from pybind11_tests import call_policies as m
 
 
 @pytest.mark.xfail("env.PYPY", reason="sometimes comes out 1 off on PyPy", strict=False)
@@ -46,6 +44,19 @@ def test_keep_alive_argument(capture):
     """
     )
 
+    p = m.Parent()
+    c = m.Child()
+    assert ConstructorStats.detail_reg_inst() == n_inst + 2
+    m.free_function(p, c)
+    del c
+    assert ConstructorStats.detail_reg_inst() == n_inst + 2
+    del p
+    assert ConstructorStats.detail_reg_inst() == n_inst
+
+    with pytest.raises(RuntimeError) as excinfo:
+        m.invalid_arg_index()
+    assert str(excinfo.value) == "Could not activate keep_alive!"
+
 
 def test_keep_alive_return_value(capture):
     n_inst = ConstructorStats.detail_reg_inst()
@@ -85,6 +96,23 @@ def test_keep_alive_return_value(capture):
     """
     )
 
+    p = m.Parent()
+    assert ConstructorStats.detail_reg_inst() == n_inst + 1
+    with capture:
+        m.Parent.staticFunction(p)
+        assert ConstructorStats.detail_reg_inst() == n_inst + 2
+    assert capture == "Allocating child."
+    with capture:
+        del p
+        assert ConstructorStats.detail_reg_inst() == n_inst
+    assert (
+        capture
+        == """
+        Releasing parent.
+        Releasing child.
+    """
+    )
+
 
 # https://foss.heptapod.net/pypy/pypy/-/issues/2447
 @pytest.mark.xfail("env.PYPY", reason="_PyObject_GetDictPtr is unimplemented")
diff --git a/3rdparty/pybind11/tests/test_callbacks.cpp b/3rdparty/pybind11/tests/test_callbacks.cpp
index 683dfb3efe..92b8053de4 100644
--- a/3rdparty/pybind11/tests/test_callbacks.cpp
+++ b/3rdparty/pybind11/tests/test_callbacks.cpp
@@ -7,72 +7,79 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/functional.h>
-#include <thread>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
+#include <thread>
 
 int dummy_function(int i) { return i + 1; }
 
 TEST_SUBMODULE(callbacks, m) {
     // test_callbacks, test_function_signatures
-    m.def("test_callback1", [](py::object func) { return func(); });
-    m.def("test_callback2", [](py::object func) { return func("Hello", 'x', true, 5); });
+    m.def("test_callback1", [](const py::object &func) { return func(); });
+    m.def("test_callback2", [](const py::object &func) { return func("Hello", 'x', true, 5); });
     m.def("test_callback3", [](const std::function<int(int)> &func) {
-        return "func(43) = " + std::to_string(func(43)); });
-    m.def("test_callback4", []() -> std::function<int(int)> { return [](int i) { return i+1; }; });
-    m.def("test_callback5", []() {
-        return py::cpp_function([](int i) { return i+1; }, py::arg("number"));
+        return "func(43) = " + std::to_string(func(43));
     });
+    m.def("test_callback4",
+          []() -> std::function<int(int)> { return [](int i) { return i + 1; }; });
+    m.def("test_callback5",
+          []() { return py::cpp_function([](int i) { return i + 1; }, py::arg("number")); });
 
     // test_keyword_args_and_generalized_unpacking
-    m.def("test_tuple_unpacking", [](py::function f) {
+    m.def("test_tuple_unpacking", [](const py::function &f) {
         auto t1 = py::make_tuple(2, 3);
         auto t2 = py::make_tuple(5, 6);
         return f("positional", 1, *t1, 4, *t2);
     });
 
-    m.def("test_dict_unpacking", [](py::function f) {
-        auto d1 = py::dict("key"_a="value", "a"_a=1);
+    m.def("test_dict_unpacking", [](const py::function &f) {
+        auto d1 = py::dict("key"_a = "value", "a"_a = 1);
         auto d2 = py::dict();
-        auto d3 = py::dict("b"_a=2);
+        auto d3 = py::dict("b"_a = 2);
         return f("positional", 1, **d1, **d2, **d3);
     });
 
-    m.def("test_keyword_args", [](py::function f) {
-        return f("x"_a=10, "y"_a=20);
-    });
+    m.def("test_keyword_args", [](const py::function &f) { return f("x"_a = 10, "y"_a = 20); });
 
-    m.def("test_unpacking_and_keywords1", [](py::function f) {
+    m.def("test_unpacking_and_keywords1", [](const py::function &f) {
         auto args = py::make_tuple(2);
-        auto kwargs = py::dict("d"_a=4);
-        return f(1, *args, "c"_a=3, **kwargs);
+        auto kwargs = py::dict("d"_a = 4);
+        return f(1, *args, "c"_a = 3, **kwargs);
     });
 
-    m.def("test_unpacking_and_keywords2", [](py::function f) {
-        auto kwargs1 = py::dict("a"_a=1);
-        auto kwargs2 = py::dict("c"_a=3, "d"_a=4);
-        return f("positional", *py::make_tuple(1), 2, *py::make_tuple(3, 4), 5,
-                 "key"_a="value", **kwargs1, "b"_a=2, **kwargs2, "e"_a=5);
+    m.def("test_unpacking_and_keywords2", [](const py::function &f) {
+        auto kwargs1 = py::dict("a"_a = 1);
+        auto kwargs2 = py::dict("c"_a = 3, "d"_a = 4);
+        return f("positional",
+                 *py::make_tuple(1),
+                 2,
+                 *py::make_tuple(3, 4),
+                 5,
+                 "key"_a = "value",
+                 **kwargs1,
+                 "b"_a = 2,
+                 **kwargs2,
+                 "e"_a = 5);
     });
 
-    m.def("test_unpacking_error1", [](py::function f) {
-        auto kwargs = py::dict("x"_a=3);
-        return f("x"_a=1, "y"_a=2, **kwargs); // duplicate ** after keyword
+    m.def("test_unpacking_error1", [](const py::function &f) {
+        auto kwargs = py::dict("x"_a = 3);
+        return f("x"_a = 1, "y"_a = 2, **kwargs); // duplicate ** after keyword
     });
 
-    m.def("test_unpacking_error2", [](py::function f) {
-        auto kwargs = py::dict("x"_a=3);
-        return f(**kwargs, "x"_a=1); // duplicate keyword after **
+    m.def("test_unpacking_error2", [](const py::function &f) {
+        auto kwargs = py::dict("x"_a = 3);
+        return f(**kwargs, "x"_a = 1); // duplicate keyword after **
     });
 
-    m.def("test_arg_conversion_error1", [](py::function f) {
-        f(234, UnregisteredType(), "kw"_a=567);
-    });
+    m.def("test_arg_conversion_error1",
+          [](const py::function &f) { f(234, UnregisteredType(), "kw"_a = 567); });
 
-    m.def("test_arg_conversion_error2", [](py::function f) {
-        f(234, "expected_name"_a=UnregisteredType(), "kw"_a=567);
+    m.def("test_arg_conversion_error2", [](const py::function &f) {
+        f(234, "expected_name"_a = UnregisteredType(), "kw"_a = 567);
     });
 
     // test_lambda_closure_cleanup
@@ -80,49 +87,99 @@ TEST_SUBMODULE(callbacks, m) {
         Payload() { print_default_created(this); }
         ~Payload() { print_destroyed(this); }
         Payload(const Payload &) { print_copy_created(this); }
-        Payload(Payload &&) { print_move_created(this); }
+        Payload(Payload &&) noexcept { print_move_created(this); }
     };
     // Export the payload constructor statistics for testing purposes:
     m.def("payload_cstats", &ConstructorStats::get<Payload>);
-    /* Test cleanup of lambda closure */
-    m.def("test_cleanup", []() -> std::function<void(void)> {
+    m.def("test_lambda_closure_cleanup", []() -> std::function<void()> {
         Payload p;
 
+        // In this situation, `Func` in the implementation of
+        // `cpp_function::initialize` is NOT trivially destructible.
         return [p]() {
             /* p should be cleaned up when the returned function is garbage collected */
             (void) p;
         };
     });
 
+    class CppCallable {
+    public:
+        CppCallable() { track_default_created(this); }
+        ~CppCallable() { track_destroyed(this); }
+        CppCallable(const CppCallable &) { track_copy_created(this); }
+        CppCallable(CppCallable &&) noexcept { track_move_created(this); }
+        void operator()() {}
+    };
+
+    m.def("test_cpp_callable_cleanup", []() {
+        // Related issue: https://github.com/pybind/pybind11/issues/3228
+        // Related PR: https://github.com/pybind/pybind11/pull/3229
+        py::list alive_counts;
+        ConstructorStats &stat = ConstructorStats::get<CppCallable>();
+        alive_counts.append(stat.alive());
+        {
+            CppCallable cpp_callable;
+            alive_counts.append(stat.alive());
+            {
+                // In this situation, `Func` in the implementation of
+                // `cpp_function::initialize` IS trivially destructible,
+                // only `capture` is not.
+                py::cpp_function py_func(cpp_callable);
+                py::detail::silence_unused_warnings(py_func);
+                alive_counts.append(stat.alive());
+            }
+            alive_counts.append(stat.alive());
+            {
+                py::cpp_function py_func(std::move(cpp_callable));
+                py::detail::silence_unused_warnings(py_func);
+                alive_counts.append(stat.alive());
+            }
+            alive_counts.append(stat.alive());
+        }
+        alive_counts.append(stat.alive());
+        return alive_counts;
+    });
+
     // test_cpp_function_roundtrip
     /* Test if passing a function pointer from C++ -> Python -> C++ yields the original pointer */
     m.def("dummy_function", &dummy_function);
+    m.def("dummy_function_overloaded", [](int i, int j) { return i + j; });
+    m.def("dummy_function_overloaded", &dummy_function);
     m.def("dummy_function2", [](int i, int j) { return i + j; });
-    m.def("roundtrip", [](std::function<int(int)> f, bool expect_none = false) {
-        if (expect_none && f)
-            throw std::runtime_error("Expected None to be converted to empty std::function");
-        return f;
-    }, py::arg("f"), py::arg("expect_none")=false);
+    m.def(
+        "roundtrip",
+        [](std::function<int(int)> f, bool expect_none = false) {
+            if (expect_none && f) {
+                throw std::runtime_error("Expected None to be converted to empty std::function");
+            }
+            return f;
+        },
+        py::arg("f"),
+        py::arg("expect_none") = false);
     m.def("test_dummy_function", [](const std::function<int(int)> &f) -> std::string {
         using fn_type = int (*)(int);
-        auto result = f.target<fn_type>();
+        const auto *result = f.target<fn_type>();
         if (!result) {
             auto r = f(1);
             return "can't convert to function pointer: eval(1) = " + std::to_string(r);
-        } else if (*result == dummy_function) {
+        }
+        if (*result == dummy_function) {
             auto r = (*result)(1);
             return "matches dummy_function: eval(1) = " + std::to_string(r);
-        } else {
-            return "argument does NOT match dummy_function. This should never happen!";
         }
+        return "argument does NOT match dummy_function. This should never happen!";
     });
 
     class AbstractBase {
     public:
-        virtual ~AbstractBase() = default;
+        // [workaround(intel)] = default does not work here
+        // Defaulting this destructor results in linking errors with the Intel compiler
+        // (in Debug builds only, tested with icpc (ICC) 2021.1 Beta 20200827)
+        virtual ~AbstractBase() {} // NOLINT(modernize-use-equals-default)
         virtual unsigned int func() = 0;
     };
-    m.def("func_accepting_func_accepting_base", [](std::function<double(AbstractBase&)>) { });
+    m.def("func_accepting_func_accepting_base",
+          [](const std::function<double(AbstractBase &)> &) {});
 
     struct MovableObject {
         bool valid = true;
@@ -130,8 +187,8 @@ TEST_SUBMODULE(callbacks, m) {
         MovableObject() = default;
         MovableObject(const MovableObject &) = default;
         MovableObject &operator=(const MovableObject &) = default;
-        MovableObject(MovableObject &&o) : valid(o.valid) { o.valid = false; }
-        MovableObject &operator=(MovableObject &&o) {
+        MovableObject(MovableObject &&o) noexcept : valid(o.valid) { o.valid = false; }
+        MovableObject &operator=(MovableObject &&o) noexcept {
             valid = o.valid;
             o.valid = false;
             return *this;
@@ -140,9 +197,9 @@ TEST_SUBMODULE(callbacks, m) {
     py::class_<MovableObject>(m, "MovableObject");
 
     // test_movable_object
-    m.def("callback_with_movable", [](std::function<void(MovableObject &)> f) {
+    m.def("callback_with_movable", [](const std::function<void(MovableObject &)> &f) {
         auto x = MovableObject();
-        f(x); // lvalue reference shouldn't move out object
+        f(x);           // lvalue reference shouldn't move out object
         return x.valid; // must still return `true`
     });
 
@@ -152,9 +209,16 @@ TEST_SUBMODULE(callbacks, m) {
         .def(py::init<>())
         .def("triple", [](CppBoundMethodTest &, int val) { return 3 * val; });
 
+    // This checks that builtin functions can be passed as callbacks
+    // rather than throwing RuntimeError due to trying to extract as capsule
+    m.def("test_sum_builtin",
+          [](const std::function<double(py::iterable)> &sum_builtin, const py::iterable &i) {
+              return sum_builtin(i);
+          });
+
     // test async Python callbacks
     using callback_f = std::function<void(int)>;
-    m.def("test_async_callback", [](callback_f f, py::list work) {
+    m.def("test_async_callback", [](const callback_f &f, const py::list &work) {
         // make detached thread that calls `f` with piece of work after a little delay
         auto start_f = [f](int j) {
             auto invoke_f = [f, j] {
@@ -166,7 +230,14 @@ TEST_SUBMODULE(callbacks, m) {
         };
 
         // spawn worker threads
-        for (auto i : work)
+        for (auto i : work) {
             start_f(py::cast<int>(i));
+        }
+    });
+
+    m.def("callback_num_times", [](const py::function &f, std::size_t num) {
+        for (std::size_t i = 0; i < num; i++) {
+            f();
+        }
     });
 }
diff --git a/3rdparty/pybind11/tests/test_callbacks.py b/3rdparty/pybind11/tests/test_callbacks.py
index 039b877ced..0b1047bbf2 100644
--- a/3rdparty/pybind11/tests/test_callbacks.py
+++ b/3rdparty/pybind11/tests/test_callbacks.py
@@ -1,7 +1,10 @@
-# -*- coding: utf-8 -*-
+import time
+from threading import Thread
+
 import pytest
+
+import env  # noqa: F401
 from pybind11_tests import callbacks as m
-from threading import Thread
 
 
 def test_callbacks():
@@ -14,7 +17,7 @@ def func2(a, b, c, d):
         return "func2", a, b, c, d
 
     def func3(a):
-        return "func3({})".format(a)
+        return f"func3({a})"
 
     assert m.test_callback1(func1) == "func1"
     assert m.test_callback2(func2) == ("func2", "Hello", "x", True, 5)
@@ -75,13 +78,18 @@ def f(*args, **kwargs):
 
 
 def test_lambda_closure_cleanup():
-    m.test_cleanup()
+    m.test_lambda_closure_cleanup()
     cstats = m.payload_cstats()
     assert cstats.alive() == 0
     assert cstats.copy_constructions == 1
     assert cstats.move_constructions >= 1
 
 
+def test_cpp_callable_cleanup():
+    alive_counts = m.test_cpp_callable_cleanup()
+    assert alive_counts == [0, 1, 2, 1, 2, 1, 0]
+
+
 def test_cpp_function_roundtrip():
     """Test if passing a function pointer from C++ -> Python -> C++ yields the original pointer"""
 
@@ -92,6 +100,10 @@ def test_cpp_function_roundtrip():
         m.test_dummy_function(m.roundtrip(m.dummy_function))
         == "matches dummy_function: eval(1) = 2"
     )
+    assert (
+        m.test_dummy_function(m.dummy_function_overloaded)
+        == "matches dummy_function: eval(1) = 2"
+    )
     assert m.roundtrip(None, expect_none=True) is None
     assert (
         m.test_dummy_function(lambda x: x + 2)
@@ -119,6 +131,16 @@ def test_movable_object():
     assert m.callback_with_movable(lambda _: None) is True
 
 
+@pytest.mark.skipif(
+    "env.PYPY",
+    reason="PyPy segfaults on here. See discussion on #1413.",
+)
+def test_python_builtins():
+    """Test if python builtins like sum() can be used as callbacks"""
+    assert m.test_sum_builtin(sum, [1, 2, 3]) == 6
+    assert m.test_sum_builtin(sum, []) == 0
+
+
 def test_async_callbacks():
     # serves as state for async callback
     class Item:
@@ -139,10 +161,35 @@ def gen_f():
     from time import sleep
 
     sleep(0.5)
-    assert sum(res) == sum([x + 3 for x in work])
+    assert sum(res) == sum(x + 3 for x in work)
 
 
 def test_async_async_callbacks():
     t = Thread(target=test_async_callbacks)
     t.start()
     t.join()
+
+
+def test_callback_num_times():
+    # Super-simple micro-benchmarking related to PR #2919.
+    # Example runtimes (Intel Xeon 2.2GHz, fully optimized):
+    #   num_millions  1, repeats  2:  0.1 secs
+    #   num_millions 20, repeats 10: 11.5 secs
+    one_million = 1000000
+    num_millions = 1  # Try 20 for actual micro-benchmarking.
+    repeats = 2  # Try 10.
+    rates = []
+    for rep in range(repeats):
+        t0 = time.time()
+        m.callback_num_times(lambda: None, num_millions * one_million)
+        td = time.time() - t0
+        rate = num_millions / td if td else 0
+        rates.append(rate)
+        if not rep:
+            print()
+        print(
+            f"callback_num_times: {num_millions:d} million / {td:.3f} seconds = {rate:.3f} million / second"
+        )
+    if len(rates) > 1:
+        print("Min    Mean   Max")
+        print(f"{min(rates):6.3f} {sum(rates) / len(rates):6.3f} {max(rates):6.3f}")
diff --git a/3rdparty/pybind11/tests/test_chrono.cpp b/3rdparty/pybind11/tests/test_chrono.cpp
index 6537050803..8be0ffd183 100644
--- a/3rdparty/pybind11/tests/test_chrono.cpp
+++ b/3rdparty/pybind11/tests/test_chrono.cpp
@@ -8,21 +8,20 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/chrono.h>
+
+#include "pybind11_tests.h"
+
 #include <chrono>
 
 struct different_resolutions {
-    using time_point_h = std::chrono::time_point<
-        std::chrono::system_clock, std::chrono::hours>;
-    using time_point_m = std::chrono::time_point<
-        std::chrono::system_clock, std::chrono::minutes>;
-    using time_point_s = std::chrono::time_point<
-        std::chrono::system_clock, std::chrono::seconds>;
-    using time_point_ms = std::chrono::time_point<
-        std::chrono::system_clock, std::chrono::milliseconds>;
-    using time_point_us = std::chrono::time_point<
-        std::chrono::system_clock, std::chrono::microseconds>;
+    using time_point_h = std::chrono::time_point<std::chrono::system_clock, std::chrono::hours>;
+    using time_point_m = std::chrono::time_point<std::chrono::system_clock, std::chrono::minutes>;
+    using time_point_s = std::chrono::time_point<std::chrono::system_clock, std::chrono::seconds>;
+    using time_point_ms
+        = std::chrono::time_point<std::chrono::system_clock, std::chrono::milliseconds>;
+    using time_point_us
+        = std::chrono::time_point<std::chrono::system_clock, std::chrono::microseconds>;
     time_point_h timestamp_h;
     time_point_m timestamp_m;
     time_point_s timestamp_s;
@@ -65,12 +64,11 @@ TEST_SUBMODULE(chrono, m) {
     // Roundtrip a duration in microseconds from a float argument
     m.def("test_chrono7", [](std::chrono::microseconds t) { return t; });
     // Float durations (issue #719)
-    m.def("test_chrono_float_diff", [](std::chrono::duration<float> a, std::chrono::duration<float> b) {
-        return a - b; });
+    m.def("test_chrono_float_diff",
+          [](std::chrono::duration<float> a, std::chrono::duration<float> b) { return a - b; });
 
-    m.def("test_nano_timepoint", [](timestamp start, timespan delta) -> timestamp {
-        return start + delta;
-    });
+    m.def("test_nano_timepoint",
+          [](timestamp start, timespan delta) -> timestamp { return start + delta; });
 
     // Test different resolutions
     py::class_<different_resolutions>(m, "different_resolutions")
@@ -79,6 +77,5 @@ TEST_SUBMODULE(chrono, m) {
         .def_readwrite("timestamp_m", &different_resolutions::timestamp_m)
         .def_readwrite("timestamp_s", &different_resolutions::timestamp_s)
         .def_readwrite("timestamp_ms", &different_resolutions::timestamp_ms)
-        .def_readwrite("timestamp_us", &different_resolutions::timestamp_us)
-        ;
+        .def_readwrite("timestamp_us", &different_resolutions::timestamp_us);
 }
diff --git a/3rdparty/pybind11/tests/test_chrono.py b/3rdparty/pybind11/tests/test_chrono.py
index e9e24e0826..7f47b37a25 100644
--- a/3rdparty/pybind11/tests/test_chrono.py
+++ b/3rdparty/pybind11/tests/test_chrono.py
@@ -1,9 +1,9 @@
-# -*- coding: utf-8 -*-
-from pybind11_tests import chrono as m
 import datetime
+
 import pytest
 
 import env  # noqa: F401
+from pybind11_tests import chrono as m
 
 
 def test_chrono_system_clock():
@@ -39,9 +39,7 @@ def test_chrono_system_clock_roundtrip():
 
     # They should be identical (no information lost on roundtrip)
     diff = abs(date1 - date2)
-    assert diff.days == 0
-    assert diff.seconds == 0
-    assert diff.microseconds == 0
+    assert diff == datetime.timedelta(0)
 
 
 def test_chrono_system_clock_roundtrip_date():
@@ -64,9 +62,7 @@ def test_chrono_system_clock_roundtrip_date():
     assert diff.microseconds == 0
 
     # Year, Month & Day should be the same after the round trip
-    assert date1.year == date2.year
-    assert date1.month == date2.month
-    assert date1.day == date2.day
+    assert date1 == date2
 
     # There should be no time information
     assert time2.hour == 0
@@ -104,7 +100,7 @@ def test_chrono_system_clock_roundtrip_date():
 )
 def test_chrono_system_clock_roundtrip_time(time1, tz, monkeypatch):
     if tz is not None:
-        monkeypatch.setenv("TZ", "/usr/share/zoneinfo/{}".format(tz))
+        monkeypatch.setenv("TZ", f"/usr/share/zoneinfo/{tz}")
 
     # Roundtrip the time
     datetime2 = m.test_chrono2(time1)
@@ -117,10 +113,7 @@ def test_chrono_system_clock_roundtrip_time(time1, tz, monkeypatch):
     assert isinstance(time2, datetime.time)
 
     # Hour, Minute, Second & Microsecond should be the same after the round trip
-    assert time1.hour == time2.hour
-    assert time1.minute == time2.minute
-    assert time1.second == time2.second
-    assert time1.microsecond == time2.microsecond
+    assert time1 == time2
 
     # There should be no date information (i.e. date = python base date)
     assert date2.year == 1970
@@ -140,9 +133,13 @@ def test_chrono_duration_roundtrip():
 
     cpp_diff = m.test_chrono3(diff)
 
-    assert cpp_diff.days == diff.days
-    assert cpp_diff.seconds == diff.seconds
-    assert cpp_diff.microseconds == diff.microseconds
+    assert cpp_diff == diff
+
+    # Negative timedelta roundtrip
+    diff = datetime.timedelta(microseconds=-1)
+    cpp_diff = m.test_chrono3(diff)
+
+    assert cpp_diff == diff
 
 
 def test_chrono_duration_subtraction_equivalence():
@@ -153,9 +150,7 @@ def test_chrono_duration_subtraction_equivalence():
     diff = date2 - date1
     cpp_diff = m.test_chrono4(date2, date1)
 
-    assert cpp_diff.days == diff.days
-    assert cpp_diff.seconds == diff.seconds
-    assert cpp_diff.microseconds == diff.microseconds
+    assert cpp_diff == diff
 
 
 def test_chrono_duration_subtraction_equivalence_date():
@@ -166,9 +161,7 @@ def test_chrono_duration_subtraction_equivalence_date():
     diff = date2 - date1
     cpp_diff = m.test_chrono4(date2, date1)
 
-    assert cpp_diff.days == diff.days
-    assert cpp_diff.seconds == diff.seconds
-    assert cpp_diff.microseconds == diff.microseconds
+    assert cpp_diff == diff
 
 
 def test_chrono_steady_clock():
@@ -183,9 +176,7 @@ def test_chrono_steady_clock_roundtrip():
     assert isinstance(time2, datetime.timedelta)
 
     # They should be identical (no information lost on roundtrip)
-    assert time1.days == time2.days
-    assert time1.seconds == time2.seconds
-    assert time1.microseconds == time2.microseconds
+    assert time1 == time2
 
 
 def test_floating_point_duration():
diff --git a/3rdparty/pybind11/tests/test_class.cpp b/3rdparty/pybind11/tests/test_class.cpp
index 890fab736f..c8b8071dc9 100644
--- a/3rdparty/pybind11/tests/test_class.cpp
+++ b/3rdparty/pybind11/tests/test_class.cpp
@@ -7,18 +7,29 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
+#if defined(__INTEL_COMPILER) && __cplusplus >= 201703L
+// Intel compiler requires a separate header file to support aligned new operators
+// and does not set the __cpp_aligned_new feature macro.
+// This header needs to be included before pybind11.
+#    include <aligned_new>
+#endif
+
+#include <pybind11/stl.h>
+
 #include "constructor_stats.h"
 #include "local_bindings.h"
-#include <pybind11/stl.h>
+#include "pybind11_tests.h"
+
+#include <utility>
 
 #if defined(_MSC_VER)
-#  pragma warning(disable: 4324) // warning C4324: structure was padded due to alignment specifier
+#    pragma warning(disable : 4324)
+//     warning C4324: structure was padded due to alignment specifier
 #endif
 
 // test_brace_initialization
 struct NoBraceInitialization {
-    NoBraceInitialization(std::vector<int> v) : vec{std::move(v)} {}
+    explicit NoBraceInitialization(std::vector<int> v) : vec{std::move(v)} {}
     template <typename T>
     NoBraceInitialization(std::initializer_list<T> l) : vec(l) {}
 
@@ -38,10 +49,26 @@ TEST_SUBMODULE(class_, m) {
         }
         ~NoConstructor() { print_destroyed(this); }
     };
+    struct NoConstructorNew {
+        NoConstructorNew() = default;
+        NoConstructorNew(const NoConstructorNew &) = default;
+        NoConstructorNew(NoConstructorNew &&) = default;
+        static NoConstructorNew *new_instance() {
+            auto *ptr = new NoConstructorNew();
+            print_created(ptr, "via new_instance");
+            return ptr;
+        }
+        ~NoConstructorNew() { print_destroyed(this); }
+    };
 
     py::class_<NoConstructor>(m, "NoConstructor")
         .def_static("new_instance", &NoConstructor::new_instance, "Return an instance");
 
+    py::class_<NoConstructorNew>(m, "NoConstructorNew")
+        .def(py::init([](const NoConstructorNew &self) { return self; })) // Need a NOOP __init__
+        .def_static("__new__",
+                    [](const py::object &) { return NoConstructorNew::new_instance(); });
+
     // test_inheritance
     class Pet {
     public:
@@ -49,6 +76,7 @@ TEST_SUBMODULE(class_, m) {
             : m_name(name), m_species(species) {}
         std::string name() const { return m_name; }
         std::string species() const { return m_species; }
+
     private:
         std::string m_name;
         std::string m_species;
@@ -56,18 +84,18 @@ TEST_SUBMODULE(class_, m) {
 
     class Dog : public Pet {
     public:
-        Dog(const std::string &name) : Pet(name, "dog") {}
+        explicit Dog(const std::string &name) : Pet(name, "dog") {}
         std::string bark() const { return "Woof!"; }
     };
 
     class Rabbit : public Pet {
     public:
-        Rabbit(const std::string &name) : Pet(name, "parrot") {}
+        explicit Rabbit(const std::string &name) : Pet(name, "parrot") {}
     };
 
     class Hamster : public Pet {
     public:
-        Hamster(const std::string &name) : Pet(name, "rodent") {}
+        explicit Hamster(const std::string &name) : Pet(name, "rodent") {}
     };
 
     class Chimera : public Pet {
@@ -75,27 +103,24 @@ TEST_SUBMODULE(class_, m) {
     };
 
     py::class_<Pet> pet_class(m, "Pet");
-    pet_class
-        .def(py::init<std::string, std::string>())
+    pet_class.def(py::init<std::string, std::string>())
         .def("name", &Pet::name)
         .def("species", &Pet::species);
 
     /* One way of declaring a subclass relationship: reference parent's class_ object */
-    py::class_<Dog>(m, "Dog", pet_class)
-        .def(py::init<std::string>());
+    py::class_<Dog>(m, "Dog", pet_class).def(py::init<std::string>());
 
     /* Another way of declaring a subclass relationship: reference parent's C++ type */
-    py::class_<Rabbit, Pet>(m, "Rabbit")
-        .def(py::init<std::string>());
+    py::class_<Rabbit, Pet>(m, "Rabbit").def(py::init<std::string>());
 
     /* And another: list parent in class template arguments */
-    py::class_<Hamster, Pet>(m, "Hamster")
-        .def(py::init<std::string>());
+    py::class_<Hamster, Pet>(m, "Hamster").def(py::init<std::string>());
 
     /* Constructors are not inherited by default */
     py::class_<Chimera, Pet>(m, "Chimera");
 
-    m.def("pet_name_species", [](const Pet &pet) { return pet.name() + " is a " + pet.species(); });
+    m.def("pet_name_species",
+          [](const Pet &pet) { return pet.name() + " is a " + pet.species(); });
     m.def("dog_bark", [](const Dog &dog) { return dog.bark(); });
 
     // test_automatic_upcasting
@@ -105,33 +130,35 @@ TEST_SUBMODULE(class_, m) {
         BaseClass(BaseClass &&) = default;
         virtual ~BaseClass() = default;
     };
-    struct DerivedClass1 : BaseClass { };
-    struct DerivedClass2 : BaseClass { };
+    struct DerivedClass1 : BaseClass {};
+    struct DerivedClass2 : BaseClass {};
 
     py::class_<BaseClass>(m, "BaseClass").def(py::init<>());
     py::class_<DerivedClass1>(m, "DerivedClass1").def(py::init<>());
     py::class_<DerivedClass2>(m, "DerivedClass2").def(py::init<>());
 
-    m.def("return_class_1", []() -> BaseClass* { return new DerivedClass1(); });
-    m.def("return_class_2", []() -> BaseClass* { return new DerivedClass2(); });
-    m.def("return_class_n", [](int n) -> BaseClass* {
-        if (n == 1) return new DerivedClass1();
-        if (n == 2) return new DerivedClass2();
+    m.def("return_class_1", []() -> BaseClass * { return new DerivedClass1(); });
+    m.def("return_class_2", []() -> BaseClass * { return new DerivedClass2(); });
+    m.def("return_class_n", [](int n) -> BaseClass * {
+        if (n == 1) {
+            return new DerivedClass1();
+        }
+        if (n == 2) {
+            return new DerivedClass2();
+        }
         return new BaseClass();
     });
-    m.def("return_none", []() -> BaseClass* { return nullptr; });
+    m.def("return_none", []() -> BaseClass * { return nullptr; });
 
     // test_isinstance
-    m.def("check_instances", [](py::list l) {
-        return py::make_tuple(
-            py::isinstance<py::tuple>(l[0]),
-            py::isinstance<py::dict>(l[1]),
-            py::isinstance<Pet>(l[2]),
-            py::isinstance<Pet>(l[3]),
-            py::isinstance<Dog>(l[4]),
-            py::isinstance<Rabbit>(l[5]),
-            py::isinstance<UnregisteredType>(l[6])
-        );
+    m.def("check_instances", [](const py::list &l) {
+        return py::make_tuple(py::isinstance<py::tuple>(l[0]),
+                              py::isinstance<py::dict>(l[1]),
+                              py::isinstance<Pet>(l[2]),
+                              py::isinstance<Pet>(l[3]),
+                              py::isinstance<Dog>(l[4]),
+                              py::isinstance<Rabbit>(l[5]),
+                              py::isinstance<UnregisteredType>(l[6]));
     });
 
     struct Invalid {};
@@ -142,30 +169,24 @@ TEST_SUBMODULE(class_, m) {
         // See https://github.com/pybind/pybind11/issues/2486
         // if (category == 2)
         //     return py::type::of<int>();
-        if (category == 1)
+        if (category == 1) {
             return py::type::of<DerivedClass1>();
-        else
-            return py::type::of<Invalid>();
+        }
+        return py::type::of<Invalid>();
     });
 
-    m.def("get_type_of", [](py::object ob) {
-        return py::type::of(ob);
-    });
+    m.def("get_type_of", [](py::object ob) { return py::type::of(std::move(ob)); });
 
-    m.def("get_type_classic", [](py::handle h) {
-        return h.get_type();
-    });
+    m.def("get_type_classic", [](py::handle h) { return h.get_type(); });
 
-    m.def("as_type", [](py::object ob) {
-        return py::type(ob);
-    });
+    m.def("as_type", [](const py::object &ob) { return py::type(ob); });
 
     // test_mismatched_holder
-    struct MismatchBase1 { };
-    struct MismatchDerived1 : MismatchBase1 { };
+    struct MismatchBase1 {};
+    struct MismatchDerived1 : MismatchBase1 {};
 
-    struct MismatchBase2 { };
-    struct MismatchDerived2 : MismatchBase2 { };
+    struct MismatchBase2 {};
+    struct MismatchDerived2 : MismatchBase2 {};
 
     m.def("mismatched_holder_1", []() {
         auto mod = py::module_::import("__main__");
@@ -175,16 +196,14 @@ TEST_SUBMODULE(class_, m) {
     m.def("mismatched_holder_2", []() {
         auto mod = py::module_::import("__main__");
         py::class_<MismatchBase2>(mod, "MismatchBase2");
-        py::class_<MismatchDerived2, std::shared_ptr<MismatchDerived2>,
-                   MismatchBase2>(mod, "MismatchDerived2");
+        py::class_<MismatchDerived2, std::shared_ptr<MismatchDerived2>, MismatchBase2>(
+            mod, "MismatchDerived2");
     });
 
     // test_override_static
     // #511: problem with inheritance + overwritten def_static
     struct MyBase {
-        static std::unique_ptr<MyBase> make() {
-            return std::unique_ptr<MyBase>(new MyBase());
-        }
+        static std::unique_ptr<MyBase> make() { return std::unique_ptr<MyBase>(new MyBase()); }
     };
 
     struct MyDerived : MyBase {
@@ -193,8 +212,7 @@ TEST_SUBMODULE(class_, m) {
         }
     };
 
-    py::class_<MyBase>(m, "MyBase")
-        .def_static("make", &MyBase::make);
+    py::class_<MyBase>(m, "MyBase").def_static("make", &MyBase::make);
 
     py::class_<MyDerived, MyBase>(m, "MyDerived")
         .def_static("make", &MyDerived::make)
@@ -204,15 +222,14 @@ TEST_SUBMODULE(class_, m) {
     struct ConvertibleFromUserType {
         int i;
 
-        ConvertibleFromUserType(UserType u) : i(u.value()) { }
+        explicit ConvertibleFromUserType(UserType u) : i(u.value()) {}
     };
 
-    py::class_<ConvertibleFromUserType>(m, "AcceptsUserType")
-        .def(py::init<UserType>());
+    py::class_<ConvertibleFromUserType>(m, "AcceptsUserType").def(py::init<UserType>());
     py::implicitly_convertible<UserType, ConvertibleFromUserType>();
 
     m.def("implicitly_convert_argument", [](const ConvertibleFromUserType &r) { return r.i; });
-    m.def("implicitly_convert_variable", [](py::object o) {
+    m.def("implicitly_convert_variable", [](const py::object &o) {
         // `o` is `UserType` and `r` is a reference to a temporary created by implicit
         // conversion. This is valid when called inside a bound function because the temp
         // object is attached to the same life support system as the arguments.
@@ -230,48 +247,91 @@ TEST_SUBMODULE(class_, m) {
             return py::str().release().ptr();
         };
 
-        auto def = new PyMethodDef{"f", f, METH_VARARGS, nullptr};
-        return py::reinterpret_steal<py::object>(PyCFunction_NewEx(def, nullptr, m.ptr()));
+        auto *def = new PyMethodDef{"f", f, METH_VARARGS, nullptr};
+        py::capsule def_capsule(def,
+                                [](void *ptr) { delete reinterpret_cast<PyMethodDef *>(ptr); });
+        return py::reinterpret_steal<py::object>(
+            PyCFunction_NewEx(def, def_capsule.ptr(), m.ptr()));
     }());
 
     // test_operator_new_delete
     struct HasOpNewDel {
         std::uint64_t i;
-        static void *operator new(size_t s) { py::print("A new", s); return ::operator new(s); }
-        static void *operator new(size_t s, void *ptr) { py::print("A placement-new", s); return ptr; }
-        static void operator delete(void *p) { py::print("A delete"); return ::operator delete(p); }
+        static void *operator new(size_t s) {
+            py::print("A new", s);
+            return ::operator new(s);
+        }
+        static void *operator new(size_t s, void *ptr) {
+            py::print("A placement-new", s);
+            return ptr;
+        }
+        static void operator delete(void *p) {
+            py::print("A delete");
+            return ::operator delete(p);
+        }
     };
     struct HasOpNewDelSize {
         std::uint32_t i;
-        static void *operator new(size_t s) { py::print("B new", s); return ::operator new(s); }
-        static void *operator new(size_t s, void *ptr) { py::print("B placement-new", s); return ptr; }
-        static void operator delete(void *p, size_t s) { py::print("B delete", s); return ::operator delete(p); }
+        static void *operator new(size_t s) {
+            py::print("B new", s);
+            return ::operator new(s);
+        }
+        static void *operator new(size_t s, void *ptr) {
+            py::print("B placement-new", s);
+            return ptr;
+        }
+        static void operator delete(void *p, size_t s) {
+            py::print("B delete", s);
+            return ::operator delete(p);
+        }
     };
     struct AliasedHasOpNewDelSize {
         std::uint64_t i;
-        static void *operator new(size_t s) { py::print("C new", s); return ::operator new(s); }
-        static void *operator new(size_t s, void *ptr) { py::print("C placement-new", s); return ptr; }
-        static void operator delete(void *p, size_t s) { py::print("C delete", s); return ::operator delete(p); }
+        static void *operator new(size_t s) {
+            py::print("C new", s);
+            return ::operator new(s);
+        }
+        static void *operator new(size_t s, void *ptr) {
+            py::print("C placement-new", s);
+            return ptr;
+        }
+        static void operator delete(void *p, size_t s) {
+            py::print("C delete", s);
+            return ::operator delete(p);
+        }
         virtual ~AliasedHasOpNewDelSize() = default;
         AliasedHasOpNewDelSize() = default;
-        AliasedHasOpNewDelSize(const AliasedHasOpNewDelSize&) = delete;
+        AliasedHasOpNewDelSize(const AliasedHasOpNewDelSize &) = delete;
     };
     struct PyAliasedHasOpNewDelSize : AliasedHasOpNewDelSize {
         PyAliasedHasOpNewDelSize() = default;
-        PyAliasedHasOpNewDelSize(int) { }
+        explicit PyAliasedHasOpNewDelSize(int) {}
         std::uint64_t j;
     };
     struct HasOpNewDelBoth {
         std::uint32_t i[8];
-        static void *operator new(size_t s) { py::print("D new", s); return ::operator new(s); }
-        static void *operator new(size_t s, void *ptr) { py::print("D placement-new", s); return ptr; }
-        static void operator delete(void *p) { py::print("D delete"); return ::operator delete(p); }
-        static void operator delete(void *p, size_t s) { py::print("D wrong delete", s); return ::operator delete(p); }
+        static void *operator new(size_t s) {
+            py::print("D new", s);
+            return ::operator new(s);
+        }
+        static void *operator new(size_t s, void *ptr) {
+            py::print("D placement-new", s);
+            return ptr;
+        }
+        static void operator delete(void *p) {
+            py::print("D delete");
+            return ::operator delete(p);
+        }
+        static void operator delete(void *p, size_t s) {
+            py::print("D wrong delete", s);
+            return ::operator delete(p);
+        }
     };
     py::class_<HasOpNewDel>(m, "HasOpNewDel").def(py::init<>());
     py::class_<HasOpNewDelSize>(m, "HasOpNewDelSize").def(py::init<>());
     py::class_<HasOpNewDelBoth>(m, "HasOpNewDelBoth").def(py::init<>());
-    py::class_<AliasedHasOpNewDelSize, PyAliasedHasOpNewDelSize> aliased(m, "AliasedHasOpNewDelSize");
+    py::class_<AliasedHasOpNewDelSize, PyAliasedHasOpNewDelSize> aliased(m,
+                                                                         "AliasedHasOpNewDelSize");
     aliased.def(py::init<>());
     aliased.attr("size_noalias") = py::int_(sizeof(AliasedHasOpNewDelSize));
     aliased.attr("size_alias") = py::int_(sizeof(PyAliasedHasOpNewDelSize));
@@ -294,13 +354,7 @@ TEST_SUBMODULE(class_, m) {
         using ProtectedA::foo;
     };
 
-    py::class_<ProtectedA>(m, "ProtectedA")
-        .def(py::init<>())
-#if !defined(_MSC_VER) || _MSC_VER >= 1910
-        .def("foo", &PublicistA::foo);
-#else
-        .def("foo", static_cast<int (ProtectedA::*)() const>(&PublicistA::foo));
-#endif
+    py::class_<ProtectedA>(m, "ProtectedA").def(py::init<>()).def("foo", &PublicistA::foo);
 
     class ProtectedB {
     public:
@@ -322,16 +376,16 @@ TEST_SUBMODULE(class_, m) {
 
     class PublicistB : public ProtectedB {
     public:
+        // [workaround(intel)] = default does not work here
+        // Removing or defaulting this destructor results in linking errors with the Intel compiler
+        // (in Debug builds only, tested with icpc (ICC) 2021.1 Beta 20200827)
+        ~PublicistB() override{}; // NOLINT(modernize-use-equals-default)
         using ProtectedB::foo;
     };
 
     py::class_<ProtectedB, TrampolineB>(m, "ProtectedB")
         .def(py::init<>())
-#if !defined(_MSC_VER) || _MSC_VER >= 1910
         .def("foo", &PublicistB::foo);
-#else
-        .def("foo", static_cast<int (ProtectedB::*)() const>(&PublicistB::foo));
-#endif
 
     // test_brace_initialization
     struct BraceInitialization {
@@ -371,8 +425,8 @@ TEST_SUBMODULE(class_, m) {
     py::class_<Nested>(base, "Nested")
         .def(py::init<>())
         .def("fn", [](Nested &, int, NestBase &, Nested &) {})
-        .def("fa", [](Nested &, int, NestBase &, Nested &) {},
-                "a"_a, "b"_a, "c"_a);
+        .def(
+            "fa", [](Nested &, int, NestBase &, Nested &) {}, "a"_a, "b"_a, "c"_a);
     base.def("g", [](NestBase &, Nested &) {});
     base.def("h", []() { return NestBase(); });
 
@@ -382,21 +436,21 @@ TEST_SUBMODULE(class_, m) {
     // generate a useful error message
 
     struct NotRegistered {};
-    struct StringWrapper { std::string str; };
+    struct StringWrapper {
+        std::string str;
+    };
     m.def("test_error_after_conversions", [](int) {});
     m.def("test_error_after_conversions",
-          [](StringWrapper) -> NotRegistered { return {}; });
+          [](const StringWrapper &) -> NotRegistered { return {}; });
     py::class_<StringWrapper>(m, "StringWrapper").def(py::init<std::string>());
     py::implicitly_convertible<std::string, StringWrapper>();
 
-    #if defined(PYBIND11_CPP17)
-        struct alignas(1024) Aligned {
-            std::uintptr_t ptr() const { return (uintptr_t) this; }
-        };
-        py::class_<Aligned>(m, "Aligned")
-            .def(py::init<>())
-            .def("ptr", &Aligned::ptr);
-    #endif
+#if defined(PYBIND11_CPP17)
+    struct alignas(1024) Aligned {
+        std::uintptr_t ptr() const { return (uintptr_t) this; }
+    };
+    py::class_<Aligned>(m, "Aligned").def(py::init<>()).def("ptr", &Aligned::ptr);
+#endif
 
     // test_final
     struct IsFinal final {};
@@ -409,9 +463,7 @@ TEST_SUBMODULE(class_, m) {
     // test_exception_rvalue_abort
     struct PyPrintDestructor {
         PyPrintDestructor() = default;
-        ~PyPrintDestructor() {
-            py::print("Print from destructor");
-        }
+        ~PyPrintDestructor() { py::print("Print from destructor"); }
         void throw_something() { throw std::runtime_error("error"); }
     };
     py::class_<PyPrintDestructor>(m, "PyPrintDestructor")
@@ -422,12 +474,10 @@ TEST_SUBMODULE(class_, m) {
     struct SamePointer {};
     static SamePointer samePointer;
     py::class_<SamePointer, std::unique_ptr<SamePointer, py::nodelete>>(m, "SamePointer")
-        .def(py::init([]() { return &samePointer; }))
-        .def("__del__", [](SamePointer&) { py::print("__del__ called"); });
+        .def(py::init([]() { return &samePointer; }));
 
     struct Empty {};
-    py::class_<Empty>(m, "Empty")
-        .def(py::init<>());
+    py::class_<Empty>(m, "Empty").def(py::init<>());
 
     // test_base_and_derived_nested_scope
     struct BaseWithNested {
@@ -450,30 +500,34 @@ TEST_SUBMODULE(class_, m) {
     struct OtherDuplicate {};
     struct DuplicateNested {};
     struct OtherDuplicateNested {};
-    m.def("register_duplicate_class_name", [](py::module_ m) {
+
+    m.def("register_duplicate_class_name", [](const py::module_ &m) {
         py::class_<Duplicate>(m, "Duplicate");
         py::class_<OtherDuplicate>(m, "Duplicate");
     });
-    m.def("register_duplicate_class_type", [](py::module_ m) {
+    m.def("register_duplicate_class_type", [](const py::module_ &m) {
         py::class_<OtherDuplicate>(m, "OtherDuplicate");
         py::class_<OtherDuplicate>(m, "YetAnotherDuplicate");
     });
-    m.def("register_duplicate_nested_class_name", [](py::object gt) {
+    m.def("register_duplicate_nested_class_name", [](const py::object &gt) {
         py::class_<DuplicateNested>(gt, "DuplicateNested");
         py::class_<OtherDuplicateNested>(gt, "DuplicateNested");
     });
-    m.def("register_duplicate_nested_class_type", [](py::object gt) {
+    m.def("register_duplicate_nested_class_type", [](const py::object &gt) {
         py::class_<OtherDuplicateNested>(gt, "OtherDuplicateNested");
         py::class_<OtherDuplicateNested>(gt, "YetAnotherDuplicateNested");
     });
 }
 
-template <int N> class BreaksBase { public:
+template <int N>
+class BreaksBase {
+public:
     virtual ~BreaksBase() = default;
     BreaksBase() = default;
-    BreaksBase(const BreaksBase&) = delete;
+    BreaksBase(const BreaksBase &) = delete;
 };
-template <int N> class BreaksTramp : public BreaksBase<N> {};
+template <int N>
+class BreaksTramp : public BreaksBase<N> {};
 // These should all compile just fine:
 using DoesntBreak1 = py::class_<BreaksBase<1>, std::unique_ptr<BreaksBase<1>>, BreaksTramp<1>>;
 using DoesntBreak2 = py::class_<BreaksBase<2>, BreaksTramp<2>, std::unique_ptr<BreaksBase<2>>>;
@@ -483,43 +537,83 @@ using DoesntBreak5 = py::class_<BreaksBase<5>>;
 using DoesntBreak6 = py::class_<BreaksBase<6>, std::shared_ptr<BreaksBase<6>>, BreaksTramp<6>>;
 using DoesntBreak7 = py::class_<BreaksBase<7>, BreaksTramp<7>, std::shared_ptr<BreaksBase<7>>>;
 using DoesntBreak8 = py::class_<BreaksBase<8>, std::shared_ptr<BreaksBase<8>>>;
-#define CHECK_BASE(N) static_assert(std::is_same<typename DoesntBreak##N::type, BreaksBase<N>>::value, \
-        "DoesntBreak" #N " has wrong type!")
-CHECK_BASE(1); CHECK_BASE(2); CHECK_BASE(3); CHECK_BASE(4); CHECK_BASE(5); CHECK_BASE(6); CHECK_BASE(7); CHECK_BASE(8);
-#define CHECK_ALIAS(N) static_assert(DoesntBreak##N::has_alias && std::is_same<typename DoesntBreak##N::type_alias, BreaksTramp<N>>::value, \
+#define CHECK_BASE(N)                                                                             \
+    static_assert(std::is_same<typename DoesntBreak##N::type, BreaksBase<(N)>>::value,            \
+                  "DoesntBreak" #N " has wrong type!")
+CHECK_BASE(1);
+CHECK_BASE(2);
+CHECK_BASE(3);
+CHECK_BASE(4);
+CHECK_BASE(5);
+CHECK_BASE(6);
+CHECK_BASE(7);
+CHECK_BASE(8);
+#define CHECK_ALIAS(N)                                                                            \
+    static_assert(                                                                                \
+        DoesntBreak##N::has_alias                                                                 \
+            && std::is_same<typename DoesntBreak##N::type_alias, BreaksTramp<(N)>>::value,        \
         "DoesntBreak" #N " has wrong type_alias!")
-#define CHECK_NOALIAS(N) static_assert(!DoesntBreak##N::has_alias && std::is_void<typename DoesntBreak##N::type_alias>::value, \
-        "DoesntBreak" #N " has type alias, but shouldn't!")
-CHECK_ALIAS(1); CHECK_ALIAS(2); CHECK_NOALIAS(3); CHECK_ALIAS(4); CHECK_NOALIAS(5); CHECK_ALIAS(6); CHECK_ALIAS(7); CHECK_NOALIAS(8);
-#define CHECK_HOLDER(N, TYPE) static_assert(std::is_same<typename DoesntBreak##N::holder_type, std::TYPE##_ptr<BreaksBase<N>>>::value, \
-        "DoesntBreak" #N " has wrong holder_type!")
-CHECK_HOLDER(1, unique); CHECK_HOLDER(2, unique); CHECK_HOLDER(3, unique); CHECK_HOLDER(4, unique); CHECK_HOLDER(5, unique);
-CHECK_HOLDER(6, shared); CHECK_HOLDER(7, shared); CHECK_HOLDER(8, shared);
+#define CHECK_NOALIAS(N)                                                                          \
+    static_assert(!DoesntBreak##N::has_alias                                                      \
+                      && std::is_void<typename DoesntBreak##N::type_alias>::value,                \
+                  "DoesntBreak" #N " has type alias, but shouldn't!")
+CHECK_ALIAS(1);
+CHECK_ALIAS(2);
+CHECK_NOALIAS(3);
+CHECK_ALIAS(4);
+CHECK_NOALIAS(5);
+CHECK_ALIAS(6);
+CHECK_ALIAS(7);
+CHECK_NOALIAS(8);
+#define CHECK_HOLDER(N, TYPE)                                                                     \
+    static_assert(std::is_same<typename DoesntBreak##N::holder_type,                              \
+                               std::TYPE##_ptr<BreaksBase<(N)>>>::value,                          \
+                  "DoesntBreak" #N " has wrong holder_type!")
+CHECK_HOLDER(1, unique);
+CHECK_HOLDER(2, unique);
+CHECK_HOLDER(3, unique);
+CHECK_HOLDER(4, unique);
+CHECK_HOLDER(5, unique);
+CHECK_HOLDER(6, shared);
+CHECK_HOLDER(7, shared);
+CHECK_HOLDER(8, shared);
 
 // There's no nice way to test that these fail because they fail to compile; leave them here,
 // though, so that they can be manually tested by uncommenting them (and seeing that compilation
 // failures occurs).
 
 // We have to actually look into the type: the typedef alone isn't enough to instantiate the type:
-#define CHECK_BROKEN(N) static_assert(std::is_same<typename Breaks##N::type, BreaksBase<-N>>::value, \
-        "Breaks1 has wrong type!");
-
-//// Two holder classes:
-//typedef py::class_<BreaksBase<-1>, std::unique_ptr<BreaksBase<-1>>, std::unique_ptr<BreaksBase<-1>>> Breaks1;
-//CHECK_BROKEN(1);
-//// Two aliases:
-//typedef py::class_<BreaksBase<-2>, BreaksTramp<-2>, BreaksTramp<-2>> Breaks2;
-//CHECK_BROKEN(2);
-//// Holder + 2 aliases
-//typedef py::class_<BreaksBase<-3>, std::unique_ptr<BreaksBase<-3>>, BreaksTramp<-3>, BreaksTramp<-3>> Breaks3;
-//CHECK_BROKEN(3);
-//// Alias + 2 holders
-//typedef py::class_<BreaksBase<-4>, std::unique_ptr<BreaksBase<-4>>, BreaksTramp<-4>, std::shared_ptr<BreaksBase<-4>>> Breaks4;
-//CHECK_BROKEN(4);
-//// Invalid option (not a subclass or holder)
-//typedef py::class_<BreaksBase<-5>, BreaksTramp<-4>> Breaks5;
-//CHECK_BROKEN(5);
-//// Invalid option: multiple inheritance not supported:
-//template <> struct BreaksBase<-8> : BreaksBase<-6>, BreaksBase<-7> {};
-//typedef py::class_<BreaksBase<-8>, BreaksBase<-6>, BreaksBase<-7>> Breaks8;
-//CHECK_BROKEN(8);
+#define CHECK_BROKEN(N)                                                                           \
+    static_assert(std::is_same<typename Breaks##N::type, BreaksBase<-(N)>>::value,                \
+                  "Breaks1 has wrong type!");
+
+#ifdef PYBIND11_NEVER_DEFINED_EVER
+// Two holder classes:
+typedef py::
+    class_<BreaksBase<-1>, std::unique_ptr<BreaksBase<-1>>, std::unique_ptr<BreaksBase<-1>>>
+        Breaks1;
+CHECK_BROKEN(1);
+// Two aliases:
+typedef py::class_<BreaksBase<-2>, BreaksTramp<-2>, BreaksTramp<-2>> Breaks2;
+CHECK_BROKEN(2);
+// Holder + 2 aliases
+typedef py::
+    class_<BreaksBase<-3>, std::unique_ptr<BreaksBase<-3>>, BreaksTramp<-3>, BreaksTramp<-3>>
+        Breaks3;
+CHECK_BROKEN(3);
+// Alias + 2 holders
+typedef py::class_<BreaksBase<-4>,
+                   std::unique_ptr<BreaksBase<-4>>,
+                   BreaksTramp<-4>,
+                   std::shared_ptr<BreaksBase<-4>>>
+    Breaks4;
+CHECK_BROKEN(4);
+// Invalid option (not a subclass or holder)
+typedef py::class_<BreaksBase<-5>, BreaksTramp<-4>> Breaks5;
+CHECK_BROKEN(5);
+// Invalid option: multiple inheritance not supported:
+template <>
+struct BreaksBase<-8> : BreaksBase<-6>, BreaksBase<-7> {};
+typedef py::class_<BreaksBase<-8>, BreaksBase<-6>, BreaksBase<-7>> Breaks8;
+CHECK_BROKEN(8);
+#endif
diff --git a/3rdparty/pybind11/tests/test_class.py b/3rdparty/pybind11/tests/test_class.py
index bdcced9643..ff9196f0f2 100644
--- a/3rdparty/pybind11/tests/test_class.py
+++ b/3rdparty/pybind11/tests/test_class.py
@@ -1,14 +1,11 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
-
+from pybind11_tests import ConstructorStats, UserType
 from pybind11_tests import class_ as m
-from pybind11_tests import UserType, ConstructorStats
 
 
 def test_repr():
-    # In Python 3.3+, repr() accesses __qualname__
     assert "pybind11_type" in repr(type(UserType))
     assert "UserType" in repr(UserType)
 
@@ -26,6 +23,14 @@ def test_instance(msg):
     assert cstats.alive() == 0
 
 
+def test_instance_new(msg):
+    instance = m.NoConstructorNew()  # .__new__(m.NoConstructor.__class__)
+    cstats = ConstructorStats.get(m.NoConstructorNew)
+    assert cstats.alive() == 1
+    del instance
+    assert cstats.alive() == 0
+
+
 def test_type():
     assert m.check_type(1) == m.DerivedClass1
     with pytest.raises(RuntimeError) as execinfo:
@@ -96,8 +101,8 @@ def test_docstrings(doc):
 
 
 def test_qualname(doc):
-    """Tests that a properly qualified name is set in __qualname__ (even in pre-3.3, where we
-    backport the attribute) and that generated docstrings properly use it and the module name"""
+    """Tests that a properly qualified name is set in __qualname__ and that
+    generated docstrings properly use it and the module name"""
     assert m.NestBase.__qualname__ == "NestBase"
     assert m.NestBase.Nested.__qualname__ == "NestBase.Nested"
 
@@ -123,13 +128,13 @@ def test_qualname(doc):
         doc(m.NestBase.Nested.fn)
         == """
         fn(self: m.class_.NestBase.Nested, arg0: int, arg1: m.class_.NestBase, arg2: m.class_.NestBase.Nested) -> None
-    """  # noqa: E501 line too long
+    """
     )
     assert (
         doc(m.NestBase.Nested.fa)
         == """
         fa(self: m.class_.NestBase.Nested, a: int, b: m.class_.NestBase, c: m.class_.NestBase.Nested) -> None
-    """  # noqa: E501 line too long
+    """
     )
     assert m.NestBase.__module__ == "pybind11_tests.class_"
     assert m.NestBase.Nested.__module__ == "pybind11_tests.class_"
@@ -321,7 +326,7 @@ def foo(self):
 
 
 def test_brace_initialization():
-    """ Tests that simple POD classes can be constructed using C++11 brace initialization """
+    """Tests that simple POD classes can be constructed using C++11 brace initialization"""
     a = m.BraceInitialization(123, "test")
     assert a.field1 == 123
     assert a.field2 == "test"
diff --git a/3rdparty/pybind11/tests/test_cmake_build/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/CMakeLists.txt
index 0c0578ad3d..8bfaa386ae 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/CMakeLists.txt
@@ -25,7 +25,7 @@ function(pybind11_add_build_test name)
   endif()
 
   if(NOT ARG_INSTALL)
-    list(APPEND build_options "-DPYBIND11_PROJECT_DIR=${pybind11_SOURCE_DIR}")
+    list(APPEND build_options "-Dpybind11_SOURCE_DIR=${pybind11_SOURCE_DIR}")
   else()
     list(APPEND build_options "-DCMAKE_PREFIX_PATH=${pybind11_BINARY_DIR}/mock_install")
   endif()
@@ -55,6 +55,8 @@ function(pybind11_add_build_test name)
   add_dependencies(test_cmake_build test_build_${name})
 endfunction()
 
+possibly_uninitialized(PYTHON_MODULE_EXTENSION Python_INTERPRETER_ID)
+
 pybind11_add_build_test(subdirectory_function)
 pybind11_add_build_test(subdirectory_target)
 if("${PYTHON_MODULE_EXTENSION}" MATCHES "pypy" OR "${Python_INTERPRETER_ID}" STREQUAL "PyPy")
@@ -77,3 +79,6 @@ if(PYBIND11_INSTALL)
 endif()
 
 add_dependencies(check test_cmake_build)
+
+add_subdirectory(subdirectory_target EXCLUDE_FROM_ALL)
+add_subdirectory(subdirectory_embed EXCLUDE_FROM_ALL)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/embed.cpp b/3rdparty/pybind11/tests/test_cmake_build/embed.cpp
index a3abc8a84d..30bc4f1e14 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/embed.cpp
+++ b/3rdparty/pybind11/tests/test_cmake_build/embed.cpp
@@ -6,15 +6,17 @@ PYBIND11_EMBEDDED_MODULE(test_cmake_build, m) {
 }
 
 int main(int argc, char *argv[]) {
-    if (argc != 2)
+    if (argc != 2) {
         throw std::runtime_error("Expected test.py file as the first argument");
-    auto test_py_file = argv[1];
+    }
+    auto *test_py_file = argv[1];
 
     py::scoped_interpreter guard{};
 
     auto m = py::module_::import("test_cmake_build");
-    if (m.attr("add")(1, 2).cast<int>() != 3)
+    if (m.attr("add")(1, 2).cast<int>() != 3) {
         throw std::runtime_error("embed.cpp failed");
+    }
 
     py::module_::import("sys").attr("argv") = py::make_tuple("test.py", "embed.cpp");
     py::eval_file(test_py_file, py::globals());
diff --git a/3rdparty/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
index 64ae5c4bff..f7d6939982 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
@@ -22,5 +22,7 @@ set_target_properties(test_installed_embed PROPERTIES OUTPUT_NAME test_cmake_bui
 # This may be needed to resolve header conflicts, e.g. between Python release and debug headers.
 set_target_properties(test_installed_embed PROPERTIES NO_SYSTEM_FROM_IMPORTED ON)
 
-add_custom_target(check_installed_embed $<TARGET_FILE:test_installed_embed>
-                                        ${PROJECT_SOURCE_DIR}/../test.py)
+add_custom_target(
+  check_installed_embed
+  $<TARGET_FILE:test_installed_embed> ${PROJECT_SOURCE_DIR}/../test.py
+  DEPENDS test_installed_embed)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt
index 1a502863c0..d7ca4db55d 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt
@@ -35,4 +35,5 @@ add_custom_target(
   PYTHONPATH=$<TARGET_FILE_DIR:test_installed_function>
   ${_Python_EXECUTABLE}
   ${PROJECT_SOURCE_DIR}/../test.py
-  ${PROJECT_NAME})
+  ${PROJECT_NAME}
+  DEPENDS test_installed_function)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt
index b38eb77470..bc5e101f1d 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt
@@ -42,4 +42,5 @@ add_custom_target(
   PYTHONPATH=$<TARGET_FILE_DIR:test_installed_target>
   ${_Python_EXECUTABLE}
   ${PROJECT_SOURCE_DIR}/../test.py
-  ${PROJECT_NAME})
+  ${PROJECT_NAME}
+  DEPENDS test_installed_target)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
index c7df0cf77c..58cdd7cfd1 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
@@ -16,15 +16,17 @@ set(PYBIND11_INSTALL
     CACHE BOOL "")
 set(PYBIND11_EXPORT_NAME test_export)
 
-add_subdirectory(${PYBIND11_PROJECT_DIR} pybind11)
+add_subdirectory("${pybind11_SOURCE_DIR}" pybind11)
 
 # Test basic target functionality
 add_executable(test_subdirectory_embed ../embed.cpp)
 target_link_libraries(test_subdirectory_embed PRIVATE pybind11::embed)
 set_target_properties(test_subdirectory_embed PROPERTIES OUTPUT_NAME test_cmake_build)
 
-add_custom_target(check_subdirectory_embed $<TARGET_FILE:test_subdirectory_embed>
-                                           ${PROJECT_SOURCE_DIR}/../test.py)
+add_custom_target(
+  check_subdirectory_embed
+  $<TARGET_FILE:test_subdirectory_embed> "${PROJECT_SOURCE_DIR}/../test.py"
+  DEPENDS test_subdirectory_embed)
 
 # Test custom export group -- PYBIND11_EXPORT_NAME
 add_library(test_embed_lib ../embed.cpp)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_function/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_function/CMakeLists.txt
index 624c600f85..01557c439a 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_function/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_function/CMakeLists.txt
@@ -11,7 +11,7 @@ endif()
 
 project(test_subdirectory_function CXX)
 
-add_subdirectory("${PYBIND11_PROJECT_DIR}" pybind11)
+add_subdirectory("${pybind11_SOURCE_DIR}" pybind11)
 pybind11_add_module(test_subdirectory_function ../main.cpp)
 set_target_properties(test_subdirectory_function PROPERTIES OUTPUT_NAME test_cmake_build)
 
@@ -31,4 +31,5 @@ add_custom_target(
   PYTHONPATH=$<TARGET_FILE_DIR:test_subdirectory_function>
   ${_Python_EXECUTABLE}
   ${PROJECT_SOURCE_DIR}/../test.py
-  ${PROJECT_NAME})
+  ${PROJECT_NAME}
+  DEPENDS test_subdirectory_function)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt
index 2471941fb6..ba82fdee2e 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt
@@ -11,7 +11,7 @@ endif()
 
 project(test_subdirectory_target CXX)
 
-add_subdirectory(${PYBIND11_PROJECT_DIR} pybind11)
+add_subdirectory("${pybind11_SOURCE_DIR}" pybind11)
 
 add_library(test_subdirectory_target MODULE ../main.cpp)
 set_target_properties(test_subdirectory_target PROPERTIES OUTPUT_NAME test_cmake_build)
@@ -37,4 +37,5 @@ add_custom_target(
   PYTHONPATH=$<TARGET_FILE_DIR:test_subdirectory_target>
   ${_Python_EXECUTABLE}
   ${PROJECT_SOURCE_DIR}/../test.py
-  ${PROJECT_NAME})
+  ${PROJECT_NAME}
+  DEPENDS test_subdirectory_target)
diff --git a/3rdparty/pybind11/tests/test_cmake_build/test.py b/3rdparty/pybind11/tests/test_cmake_build/test.py
index 87ed5135ff..807fd43b4a 100644
--- a/3rdparty/pybind11/tests/test_cmake_build/test.py
+++ b/3rdparty/pybind11/tests/test_cmake_build/test.py
@@ -1,6 +1,8 @@
-# -*- coding: utf-8 -*-
 import sys
+
 import test_cmake_build
 
+assert isinstance(__file__, str)  # Test this is properly set
+
 assert test_cmake_build.add(1, 2) == 3
-print("{} imports, runs, and adds: 1 + 2 = 3".format(sys.argv[1]))
+print(f"{sys.argv[1]} imports, runs, and adds: 1 + 2 = 3")
diff --git a/3rdparty/pybind11/tests/test_const_name.cpp b/3rdparty/pybind11/tests/test_const_name.cpp
new file mode 100644
index 0000000000..2ad01e6827
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_const_name.cpp
@@ -0,0 +1,55 @@
+// Copyright (c) 2021 The Pybind Development Team.
+// All rights reserved. Use of this source code is governed by a
+// BSD-style license that can be found in the LICENSE file.
+
+#include "pybind11_tests.h"
+
+// IUT = Implementation Under Test
+#define CONST_NAME_TESTS(TEST_FUNC, IUT)                                                          \
+    std::string TEST_FUNC(int selector) {                                                         \
+        switch (selector) {                                                                       \
+            case 0:                                                                               \
+                return IUT("").text;                                                              \
+            case 1:                                                                               \
+                return IUT("A").text;                                                             \
+            case 2:                                                                               \
+                return IUT("Bd").text;                                                            \
+            case 3:                                                                               \
+                return IUT("Cef").text;                                                           \
+            case 4:                                                                               \
+                return IUT<int>().text; /*NOLINT(bugprone-macro-parentheses)*/                    \
+            case 5:                                                                               \
+                return IUT<std::string>().text; /*NOLINT(bugprone-macro-parentheses)*/            \
+            case 6:                                                                               \
+                return IUT<true>("T1", "T2").text; /*NOLINT(bugprone-macro-parentheses)*/         \
+            case 7:                                                                               \
+                return IUT<false>("U1", "U2").text; /*NOLINT(bugprone-macro-parentheses)*/        \
+            case 8:                                                                               \
+                /*NOLINTNEXTLINE(bugprone-macro-parentheses)*/                                    \
+                return IUT<true>(IUT("D1"), IUT("D2")).text;                                      \
+            case 9:                                                                               \
+                /*NOLINTNEXTLINE(bugprone-macro-parentheses)*/                                    \
+                return IUT<false>(IUT("E1"), IUT("E2")).text;                                     \
+            case 10:                                                                              \
+                return IUT("KeepAtEnd").text;                                                     \
+            default:                                                                              \
+                break;                                                                            \
+        }                                                                                         \
+        throw std::runtime_error("Invalid selector value.");                                      \
+    }
+
+CONST_NAME_TESTS(const_name_tests, py::detail::const_name)
+
+#ifdef PYBIND11_DETAIL_UNDERSCORE_BACKWARD_COMPATIBILITY
+CONST_NAME_TESTS(underscore_tests, py::detail::_)
+#endif
+
+TEST_SUBMODULE(const_name, m) {
+    m.def("const_name_tests", const_name_tests);
+
+#if defined(PYBIND11_DETAIL_UNDERSCORE_BACKWARD_COMPATIBILITY)
+    m.def("underscore_tests", underscore_tests);
+#else
+    m.attr("underscore_tests") = "PYBIND11_DETAIL_UNDERSCORE_BACKWARD_COMPATIBILITY not defined.";
+#endif
+}
diff --git a/3rdparty/pybind11/tests/test_const_name.py b/3rdparty/pybind11/tests/test_const_name.py
new file mode 100644
index 0000000000..10b0caee2e
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_const_name.py
@@ -0,0 +1,29 @@
+import pytest
+
+from pybind11_tests import const_name as m
+
+
+@pytest.mark.parametrize("func", (m.const_name_tests, m.underscore_tests))
+@pytest.mark.parametrize(
+    "selector, expected",
+    enumerate(
+        (
+            "",
+            "A",
+            "Bd",
+            "Cef",
+            "%",
+            "%",
+            "T1",
+            "U2",
+            "D1",
+            "E2",
+            "KeepAtEnd",
+        )
+    ),
+)
+def test_const_name(func, selector, expected):
+    if isinstance(func, str):
+        pytest.skip(func)
+    text = func(selector)
+    assert text == expected
diff --git a/3rdparty/pybind11/tests/test_constants_and_functions.cpp b/3rdparty/pybind11/tests/test_constants_and_functions.cpp
index f607795593..1918a429c8 100644
--- a/3rdparty/pybind11/tests/test_constants_and_functions.cpp
+++ b/3rdparty/pybind11/tests/test_constants_and_functions.cpp
@@ -1,5 +1,6 @@
 /*
-    tests/test_constants_and_functions.cpp -- global constants and functions, enumerations, raw byte strings
+    tests/test_constants_and_functions.cpp -- global constants and functions, enumerations, raw
+    byte strings
 
     Copyright (c) 2016 Wenzel Jakob <wenzel.jakob@epfl.ch>
 
@@ -11,20 +12,14 @@
 
 enum MyEnum { EFirstEntry = 1, ESecondEntry };
 
-std::string test_function1() {
-    return "test_function()";
-}
+std::string test_function1() { return "test_function()"; }
 
-std::string test_function2(MyEnum k) {
-    return "test_function(enum=" + std::to_string(k) + ")";
-}
+std::string test_function2(MyEnum k) { return "test_function(enum=" + std::to_string(k) + ")"; }
 
-std::string test_function3(int i) {
-    return "test_function(" + std::to_string(i) + ")";
-}
+std::string test_function3(int i) { return "test_function(" + std::to_string(i) + ")"; }
 
-py::str test_function4()           { return "test_function()"; }
-py::str test_function4(char *)     { return "test_function(char *)"; }
+py::str test_function4() { return "test_function()"; }
+py::str test_function4(char *) { return "test_function(char *)"; }
 py::str test_function4(int, float) { return "test_function(int, float)"; }
 py::str test_function4(float, int) { return "test_function(float, int)"; }
 
@@ -33,50 +28,60 @@ py::bytes return_bytes() {
     return std::string(data, 4);
 }
 
-std::string print_bytes(py::bytes bytes) {
+std::string print_bytes(const py::bytes &bytes) {
     std::string ret = "bytes[";
     const auto value = static_cast<std::string>(bytes);
-    for (size_t i = 0; i < value.length(); ++i) {
-        ret += std::to_string(static_cast<int>(value[i])) + " ";
+    for (char c : value) {
+        ret += std::to_string(static_cast<int>(c)) + ' ';
     }
     ret.back() = ']';
     return ret;
 }
 
-// Test that we properly handle C++17 exception specifiers (which are part of the function signature
-// in C++17).  These should all still work before C++17, but don't affect the function signature.
+// Test that we properly handle C++17 exception specifiers (which are part of the function
+// signature in C++17).  These should all still work before C++17, but don't affect the function
+// signature.
 namespace test_exc_sp {
-int f1(int x) noexcept { return x+1; }
-int f2(int x) noexcept(true) { return x+2; }
-int f3(int x) noexcept(false) { return x+3; }
-#if defined(__GNUG__)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wdeprecated"
+// [workaround(intel)] Unable to use noexcept instead of noexcept(true)
+// Make the f1 test basically the same as the f2 test in C++17 mode for the Intel compiler as
+// it fails to compile with a plain noexcept (tested with icc (ICC) 2021.1 Beta 20200827).
+#if defined(__INTEL_COMPILER) && defined(PYBIND11_CPP17)
+int f1(int x) noexcept(true) { return x + 1; }
+#else
+int f1(int x) noexcept { return x + 1; }
+#endif
+int f2(int x) noexcept(true) { return x + 2; }
+int f3(int x) noexcept(false) { return x + 3; }
+#if defined(__GNUG__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wdeprecated"
 #endif
-int f4(int x) throw() { return x+4; } // Deprecated equivalent to noexcept(true)
-#if defined(__GNUG__)
-#  pragma GCC diagnostic pop
+// NOLINTNEXTLINE(modernize-use-noexcept)
+int f4(int x) throw() { return x + 4; } // Deprecated equivalent to noexcept(true)
+#if defined(__GNUG__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic pop
 #endif
 struct C {
-    int m1(int x) noexcept { return x-1; }
-    int m2(int x) const noexcept { return x-2; }
-    int m3(int x) noexcept(true) { return x-3; }
-    int m4(int x) const noexcept(true) { return x-4; }
-    int m5(int x) noexcept(false) { return x-5; }
-    int m6(int x) const noexcept(false) { return x-6; }
-#if defined(__GNUG__)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wdeprecated"
+    int m1(int x) noexcept { return x - 1; }
+    int m2(int x) const noexcept { return x - 2; }
+    int m3(int x) noexcept(true) { return x - 3; }
+    int m4(int x) const noexcept(true) { return x - 4; }
+    int m5(int x) noexcept(false) { return x - 5; }
+    int m6(int x) const noexcept(false) { return x - 6; }
+#if defined(__GNUG__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic push
+#    pragma GCC diagnostic ignored "-Wdeprecated"
 #endif
-    int m7(int x) throw() { return x-7; }
-    int m8(int x) const throw() { return x-8; }
-#if defined(__GNUG__)
-#  pragma GCC diagnostic pop
+    // NOLINTNEXTLINE(modernize-use-noexcept)
+    int m7(int x) throw() { return x - 7; }
+    // NOLINTNEXTLINE(modernize-use-noexcept)
+    int m8(int x) const throw() { return x - 8; }
+#if defined(__GNUG__) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic pop
 #endif
 };
 } // namespace test_exc_sp
 
-
 TEST_SUBMODULE(constants_and_functions, m) {
     // test_constants
     m.attr("some_constant") = py::int_(14);
@@ -118,10 +123,37 @@ TEST_SUBMODULE(constants_and_functions, m) {
         .def("m5", &C::m5)
         .def("m6", &C::m6)
         .def("m7", &C::m7)
-        .def("m8", &C::m8)
-        ;
+        .def("m8", &C::m8);
     m.def("f1", f1);
     m.def("f2", f2);
+#if defined(__INTEL_COMPILER)
+#    pragma warning push
+#    pragma warning disable 878 // incompatible exception specifications
+#endif
     m.def("f3", f3);
+#if defined(__INTEL_COMPILER)
+#    pragma warning pop
+#endif
     m.def("f4", f4);
+
+    // test_function_record_leaks
+    m.def("register_large_capture_with_invalid_arguments", [](py::module_ m) {
+        // This should always be enough to trigger the alternative branch
+        // where `sizeof(capture) > sizeof(rec->data)`
+        uint64_t capture[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
+#if defined(__GNUC__) && __GNUC__ == 4 // CentOS7
+        py::detail::silence_unused_warnings(capture);
+#endif
+        m.def(
+            "should_raise", [capture](int) { return capture[9] + 33; }, py::kw_only(), py::arg());
+    });
+    m.def("register_with_raising_repr", [](py::module_ m, const py::object &default_value) {
+        m.def(
+            "should_raise",
+            [](int, int, const py::object &) { return 42; },
+            "some docstring",
+            py::arg_v("x", 42),
+            py::arg_v("y", 42, "<the answer>"),
+            py::arg_v("z", default_value));
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_constants_and_functions.py b/3rdparty/pybind11/tests/test_constants_and_functions.py
index b980ccf1cc..5da0b84b8e 100644
--- a/3rdparty/pybind11/tests/test_constants_and_functions.py
+++ b/3rdparty/pybind11/tests/test_constants_and_functions.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 m = pytest.importorskip("pybind11_tests.constants_and_functions")
@@ -40,3 +39,14 @@ def test_exception_specifiers():
     assert m.f2(53) == 55
     assert m.f3(86) == 89
     assert m.f4(140) == 144
+
+
+def test_function_record_leaks():
+    class RaisingRepr:
+        def __repr__(self):
+            raise RuntimeError("Surprise!")
+
+    with pytest.raises(RuntimeError):
+        m.register_large_capture_with_invalid_arguments(m)
+    with pytest.raises(RuntimeError):
+        m.register_with_raising_repr(m, RaisingRepr())
diff --git a/3rdparty/pybind11/tests/test_copy_move.cpp b/3rdparty/pybind11/tests/test_copy_move.cpp
index 2704217aa6..28c2445644 100644
--- a/3rdparty/pybind11/tests/test_copy_move.cpp
+++ b/3rdparty/pybind11/tests/test_copy_move.cpp
@@ -8,38 +8,48 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/stl.h>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 template <typename derived>
 struct empty {
-    static const derived& get_one() { return instance_; }
+    static const derived &get_one() { return instance_; }
     static derived instance_;
 };
 
 struct lacking_copy_ctor : public empty<lacking_copy_ctor> {
     lacking_copy_ctor() = default;
-    lacking_copy_ctor(const lacking_copy_ctor& other) = delete;
+    lacking_copy_ctor(const lacking_copy_ctor &other) = delete;
 };
 
-template <> lacking_copy_ctor empty<lacking_copy_ctor>::instance_ = {};
+template <>
+lacking_copy_ctor empty<lacking_copy_ctor>::instance_ = {};
 
 struct lacking_move_ctor : public empty<lacking_move_ctor> {
     lacking_move_ctor() = default;
-    lacking_move_ctor(const lacking_move_ctor& other) = delete;
-    lacking_move_ctor(lacking_move_ctor&& other) = delete;
+    lacking_move_ctor(const lacking_move_ctor &other) = delete;
+    lacking_move_ctor(lacking_move_ctor &&other) = delete;
 };
 
-template <> lacking_move_ctor empty<lacking_move_ctor>::instance_ = {};
+template <>
+lacking_move_ctor empty<lacking_move_ctor>::instance_ = {};
 
 /* Custom type caster move/copy test classes */
 class MoveOnlyInt {
 public:
     MoveOnlyInt() { print_default_created(this); }
-    MoveOnlyInt(int v) : value{std::move(v)} { print_created(this, value); }
-    MoveOnlyInt(MoveOnlyInt &&m) { print_move_created(this, m.value); std::swap(value, m.value); }
-    MoveOnlyInt &operator=(MoveOnlyInt &&m) { print_move_assigned(this, m.value); std::swap(value, m.value); return *this; }
+    explicit MoveOnlyInt(int v) : value{v} { print_created(this, value); }
+    MoveOnlyInt(MoveOnlyInt &&m) noexcept {
+        print_move_created(this, m.value);
+        std::swap(value, m.value);
+    }
+    MoveOnlyInt &operator=(MoveOnlyInt &&m) noexcept {
+        print_move_assigned(this, m.value);
+        std::swap(value, m.value);
+        return *this;
+    }
     MoveOnlyInt(const MoveOnlyInt &) = delete;
     MoveOnlyInt &operator=(const MoveOnlyInt &) = delete;
     ~MoveOnlyInt() { print_destroyed(this); }
@@ -49,11 +59,26 @@ class MoveOnlyInt {
 class MoveOrCopyInt {
 public:
     MoveOrCopyInt() { print_default_created(this); }
-    MoveOrCopyInt(int v) : value{std::move(v)} { print_created(this, value); }
-    MoveOrCopyInt(MoveOrCopyInt &&m) { print_move_created(this, m.value); std::swap(value, m.value); }
-    MoveOrCopyInt &operator=(MoveOrCopyInt &&m) { print_move_assigned(this, m.value); std::swap(value, m.value); return *this; }
-    MoveOrCopyInt(const MoveOrCopyInt &c) { print_copy_created(this, c.value); value = c.value; }
-    MoveOrCopyInt &operator=(const MoveOrCopyInt &c) { print_copy_assigned(this, c.value); value = c.value; return *this; }
+    explicit MoveOrCopyInt(int v) : value{v} { print_created(this, value); }
+    MoveOrCopyInt(MoveOrCopyInt &&m) noexcept {
+        print_move_created(this, m.value);
+        std::swap(value, m.value);
+    }
+    MoveOrCopyInt &operator=(MoveOrCopyInt &&m) noexcept {
+        print_move_assigned(this, m.value);
+        std::swap(value, m.value);
+        return *this;
+    }
+    MoveOrCopyInt(const MoveOrCopyInt &c) {
+        print_copy_created(this, c.value);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = c.value;
+    }
+    MoveOrCopyInt &operator=(const MoveOrCopyInt &c) {
+        print_copy_assigned(this, c.value);
+        value = c.value;
+        return *this;
+    }
     ~MoveOrCopyInt() { print_destroyed(this); }
 
     int value;
@@ -61,41 +86,71 @@ class MoveOrCopyInt {
 class CopyOnlyInt {
 public:
     CopyOnlyInt() { print_default_created(this); }
-    CopyOnlyInt(int v) : value{std::move(v)} { print_created(this, value); }
-    CopyOnlyInt(const CopyOnlyInt &c) { print_copy_created(this, c.value); value = c.value; }
-    CopyOnlyInt &operator=(const CopyOnlyInt &c) { print_copy_assigned(this, c.value); value = c.value; return *this; }
+    explicit CopyOnlyInt(int v) : value{v} { print_created(this, value); }
+    CopyOnlyInt(const CopyOnlyInt &c) {
+        print_copy_created(this, c.value);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = c.value;
+    }
+    CopyOnlyInt &operator=(const CopyOnlyInt &c) {
+        print_copy_assigned(this, c.value);
+        value = c.value;
+        return *this;
+    }
     ~CopyOnlyInt() { print_destroyed(this); }
 
     int value;
 };
 PYBIND11_NAMESPACE_BEGIN(pybind11)
 PYBIND11_NAMESPACE_BEGIN(detail)
-template <> struct type_caster<MoveOnlyInt> {
-    PYBIND11_TYPE_CASTER(MoveOnlyInt, _("MoveOnlyInt"));
-    bool load(handle src, bool) { value = MoveOnlyInt(src.cast<int>()); return true; }
-    static handle cast(const MoveOnlyInt &m, return_value_policy r, handle p) { return pybind11::cast(m.value, r, p); }
+template <>
+struct type_caster<MoveOnlyInt> {
+    PYBIND11_TYPE_CASTER(MoveOnlyInt, const_name("MoveOnlyInt"));
+    bool load(handle src, bool) {
+        value = MoveOnlyInt(src.cast<int>());
+        return true;
+    }
+    static handle cast(const MoveOnlyInt &m, return_value_policy r, handle p) {
+        return pybind11::cast(m.value, r, p);
+    }
 };
 
-template <> struct type_caster<MoveOrCopyInt> {
-    PYBIND11_TYPE_CASTER(MoveOrCopyInt, _("MoveOrCopyInt"));
-    bool load(handle src, bool) { value = MoveOrCopyInt(src.cast<int>()); return true; }
-    static handle cast(const MoveOrCopyInt &m, return_value_policy r, handle p) { return pybind11::cast(m.value, r, p); }
+template <>
+struct type_caster<MoveOrCopyInt> {
+    PYBIND11_TYPE_CASTER(MoveOrCopyInt, const_name("MoveOrCopyInt"));
+    bool load(handle src, bool) {
+        value = MoveOrCopyInt(src.cast<int>());
+        return true;
+    }
+    static handle cast(const MoveOrCopyInt &m, return_value_policy r, handle p) {
+        return pybind11::cast(m.value, r, p);
+    }
 };
 
-template <> struct type_caster<CopyOnlyInt> {
+template <>
+struct type_caster<CopyOnlyInt> {
 protected:
     CopyOnlyInt value;
+
 public:
-    static constexpr auto name = _("CopyOnlyInt");
-    bool load(handle src, bool) { value = CopyOnlyInt(src.cast<int>()); return true; }
-    static handle cast(const CopyOnlyInt &m, return_value_policy r, handle p) { return pybind11::cast(m.value, r, p); }
+    static constexpr auto name = const_name("CopyOnlyInt");
+    bool load(handle src, bool) {
+        value = CopyOnlyInt(src.cast<int>());
+        return true;
+    }
+    static handle cast(const CopyOnlyInt &m, return_value_policy r, handle p) {
+        return pybind11::cast(m.value, r, p);
+    }
     static handle cast(const CopyOnlyInt *src, return_value_policy policy, handle parent) {
-        if (!src) return none().release();
+        if (!src) {
+            return none().release();
+        }
         return cast(*src, policy, parent);
     }
-    operator CopyOnlyInt*() { return &value; }
-    operator CopyOnlyInt&() { return value; }
-    template <typename T> using cast_op_type = pybind11::detail::cast_op_type<T>;
+    explicit operator CopyOnlyInt *() { return &value; }
+    explicit operator CopyOnlyInt &() { return value; }
+    template <typename T>
+    using cast_op_type = pybind11::detail::cast_op_type<T>;
 };
 PYBIND11_NAMESPACE_END(detail)
 PYBIND11_NAMESPACE_END(pybind11)
@@ -103,22 +158,21 @@ PYBIND11_NAMESPACE_END(pybind11)
 TEST_SUBMODULE(copy_move_policies, m) {
     // test_lacking_copy_ctor
     py::class_<lacking_copy_ctor>(m, "lacking_copy_ctor")
-        .def_static("get_one", &lacking_copy_ctor::get_one,
-                    py::return_value_policy::copy);
+        .def_static("get_one", &lacking_copy_ctor::get_one, py::return_value_policy::copy);
     // test_lacking_move_ctor
     py::class_<lacking_move_ctor>(m, "lacking_move_ctor")
-        .def_static("get_one", &lacking_move_ctor::get_one,
-                    py::return_value_policy::move);
+        .def_static("get_one", &lacking_move_ctor::get_one, py::return_value_policy::move);
 
     // test_move_and_copy_casts
-    m.def("move_and_copy_casts", [](py::object o) {
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
+    m.def("move_and_copy_casts", [](const py::object &o) {
         int r = 0;
         r += py::cast<MoveOrCopyInt>(o).value; /* moves */
-        r += py::cast<MoveOnlyInt>(o).value; /* moves */
-        r += py::cast<CopyOnlyInt>(o).value; /* copies */
-        auto m1(py::cast<MoveOrCopyInt>(o)); /* moves */
-        auto m2(py::cast<MoveOnlyInt>(o)); /* moves */
-        auto m3(py::cast<CopyOnlyInt>(o)); /* copies */
+        r += py::cast<MoveOnlyInt>(o).value;   /* moves */
+        r += py::cast<CopyOnlyInt>(o).value;   /* copies */
+        auto m1(py::cast<MoveOrCopyInt>(o));   /* moves */
+        auto m2(py::cast<MoveOnlyInt>(o));     /* moves */
+        auto m3(py::cast<CopyOnlyInt>(o));     /* copies */
         r += m1.value + m2.value + m3.value;
 
         return r;
@@ -126,30 +180,40 @@ TEST_SUBMODULE(copy_move_policies, m) {
 
     // test_move_and_copy_loads
     m.def("move_only", [](MoveOnlyInt m) { return m.value; });
+    // Changing this breaks the existing test: needs careful review.
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
     m.def("move_or_copy", [](MoveOrCopyInt m) { return m.value; });
+    // Changing this breaks the existing test: needs careful review.
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
     m.def("copy_only", [](CopyOnlyInt m) { return m.value; });
-    m.def("move_pair", [](std::pair<MoveOnlyInt, MoveOrCopyInt> p) {
-        return p.first.value + p.second.value;
-    });
+    m.def("move_pair",
+          [](std::pair<MoveOnlyInt, MoveOrCopyInt> p) { return p.first.value + p.second.value; });
     m.def("move_tuple", [](std::tuple<MoveOnlyInt, MoveOrCopyInt, MoveOnlyInt> t) {
         return std::get<0>(t).value + std::get<1>(t).value + std::get<2>(t).value;
     });
     m.def("copy_tuple", [](std::tuple<CopyOnlyInt, CopyOnlyInt> t) {
         return std::get<0>(t).value + std::get<1>(t).value;
     });
-    m.def("move_copy_nested", [](std::pair<MoveOnlyInt, std::pair<std::tuple<MoveOrCopyInt, CopyOnlyInt, std::tuple<MoveOnlyInt>>, MoveOrCopyInt>> x) {
-        return x.first.value + std::get<0>(x.second.first).value + std::get<1>(x.second.first).value +
-            std::get<0>(std::get<2>(x.second.first)).value + x.second.second.value;
-    });
+    m.def("move_copy_nested",
+          [](std::pair<MoveOnlyInt,
+                       std::pair<std::tuple<MoveOrCopyInt, CopyOnlyInt, std::tuple<MoveOnlyInt>>,
+                                 MoveOrCopyInt>> x) {
+              return x.first.value + std::get<0>(x.second.first).value
+                     + std::get<1>(x.second.first).value
+                     + std::get<0>(std::get<2>(x.second.first)).value + x.second.second.value;
+          });
     m.def("move_and_copy_cstats", []() {
         ConstructorStats::gc();
         // Reset counts to 0 so that previous tests don't affect later ones:
         auto &mc = ConstructorStats::get<MoveOrCopyInt>();
-        mc.move_assignments = mc.move_constructions = mc.copy_assignments = mc.copy_constructions = 0;
+        mc.move_assignments = mc.move_constructions = mc.copy_assignments = mc.copy_constructions
+            = 0;
         auto &mo = ConstructorStats::get<MoveOnlyInt>();
-        mo.move_assignments = mo.move_constructions = mo.copy_assignments = mo.copy_constructions = 0;
+        mo.move_assignments = mo.move_constructions = mo.copy_assignments = mo.copy_constructions
+            = 0;
         auto &co = ConstructorStats::get<CopyOnlyInt>();
-        co.move_assignments = co.move_constructions = co.copy_assignments = co.copy_constructions = 0;
+        co.move_assignments = co.move_constructions = co.copy_assignments = co.copy_constructions
+            = 0;
         py::dict d;
         d["MoveOrCopyInt"] = py::cast(mc, py::return_value_policy::reference);
         d["MoveOnlyInt"] = py::cast(mo, py::return_value_policy::reference);
@@ -159,18 +223,13 @@ TEST_SUBMODULE(copy_move_policies, m) {
 #ifdef PYBIND11_HAS_OPTIONAL
     // test_move_and_copy_load_optional
     m.attr("has_optional") = true;
-    m.def("move_optional", [](std::optional<MoveOnlyInt> o) {
-        return o->value;
-    });
-    m.def("move_or_copy_optional", [](std::optional<MoveOrCopyInt> o) {
-        return o->value;
-    });
-    m.def("copy_optional", [](std::optional<CopyOnlyInt> o) {
-        return o->value;
-    });
-    m.def("move_optional_tuple", [](std::optional<std::tuple<MoveOrCopyInt, MoveOnlyInt, CopyOnlyInt>> x) {
-        return std::get<0>(*x).value + std::get<1>(*x).value + std::get<2>(*x).value;
-    });
+    m.def("move_optional", [](std::optional<MoveOnlyInt> o) { return o->value; });
+    m.def("move_or_copy_optional", [](std::optional<MoveOrCopyInt> o) { return o->value; });
+    m.def("copy_optional", [](std::optional<CopyOnlyInt> o) { return o->value; });
+    m.def("move_optional_tuple",
+          [](std::optional<std::tuple<MoveOrCopyInt, MoveOnlyInt, CopyOnlyInt>> x) {
+              return std::get<0>(*x).value + std::get<1>(*x).value + std::get<2>(*x).value;
+          });
 #else
     m.attr("has_optional") = false;
 #endif
@@ -181,39 +240,56 @@ TEST_SUBMODULE(copy_move_policies, m) {
     // added later.
     struct PrivateOpNew {
         int value = 1;
+
     private:
         void *operator new(size_t bytes) {
             void *ptr = std::malloc(bytes);
-            if (ptr)
+            if (ptr) {
                 return ptr;
-            else
-                throw std::bad_alloc{};
+            }
+            throw std::bad_alloc{};
         }
     };
     py::class_<PrivateOpNew>(m, "PrivateOpNew").def_readonly("value", &PrivateOpNew::value);
     m.def("private_op_new_value", []() { return PrivateOpNew(); });
-    m.def("private_op_new_reference", []() -> const PrivateOpNew & {
-        static PrivateOpNew x{};
-        return x;
-    }, py::return_value_policy::reference);
+    m.def(
+        "private_op_new_reference",
+        []() -> const PrivateOpNew & {
+            static PrivateOpNew x{};
+            return x;
+        },
+        py::return_value_policy::reference);
 
     // test_move_fallback
     // #389: rvp::move should fall-through to copy on non-movable objects
     struct MoveIssue1 {
         int v;
-        MoveIssue1(int v) : v{v} {}
+        explicit MoveIssue1(int v) : v{v} {}
         MoveIssue1(const MoveIssue1 &c) = default;
         MoveIssue1(MoveIssue1 &&) = delete;
     };
-    py::class_<MoveIssue1>(m, "MoveIssue1").def(py::init<int>()).def_readwrite("value", &MoveIssue1::v);
+    py::class_<MoveIssue1>(m, "MoveIssue1")
+        .def(py::init<int>())
+        .def_readwrite("value", &MoveIssue1::v);
 
     struct MoveIssue2 {
         int v;
-        MoveIssue2(int v) : v{v} {}
+        explicit MoveIssue2(int v) : v{v} {}
         MoveIssue2(MoveIssue2 &&) = default;
     };
-    py::class_<MoveIssue2>(m, "MoveIssue2").def(py::init<int>()).def_readwrite("value", &MoveIssue2::v);
+    py::class_<MoveIssue2>(m, "MoveIssue2")
+        .def(py::init<int>())
+        .def_readwrite("value", &MoveIssue2::v);
+
+    // #2742: Don't expect ownership of raw pointer to `new`ed object to be transferred with
+    // `py::return_value_policy::move`
+    m.def(
+        "get_moveissue1",
+        [](int i) { return std::unique_ptr<MoveIssue1>(new MoveIssue1(i)); },
+        py::return_value_policy::move);
+    m.def(
+        "get_moveissue2", [](int i) { return MoveIssue2(i); }, py::return_value_policy::move);
 
-    m.def("get_moveissue1", [](int i) { return new MoveIssue1(i); }, py::return_value_policy::move);
-    m.def("get_moveissue2", [](int i) { return MoveIssue2(i); }, py::return_value_policy::move);
+    // Make sure that cast from pytype rvalue to other pytype works
+    m.def("get_pytype_rvalue_castissue", [](double i) { return py::float_(i).cast<py::int_>(); });
 }
diff --git a/3rdparty/pybind11/tests/test_copy_move.py b/3rdparty/pybind11/tests/test_copy_move.py
index 7e3cc168ca..9fef089339 100644
--- a/3rdparty/pybind11/tests/test_copy_move.py
+++ b/3rdparty/pybind11/tests/test_copy_move.py
@@ -1,5 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
+
 from pybind11_tests import copy_move_policies as m
 
 
@@ -119,7 +119,14 @@ def test_private_op_new():
 def test_move_fallback():
     """#389: rvp::move should fall-through to copy on non-movable objects"""
 
-    m2 = m.get_moveissue2(2)
-    assert m2.value == 2
     m1 = m.get_moveissue1(1)
     assert m1.value == 1
+    m2 = m.get_moveissue2(2)
+    assert m2.value == 2
+
+
+def test_pytype_rvalue_cast():
+    """Make sure that cast from pytype rvalue to other pytype works"""
+
+    value = m.get_pytype_rvalue_castissue(1.0)
+    assert value == 1
diff --git a/3rdparty/pybind11/tests/test_custom_type_casters.cpp b/3rdparty/pybind11/tests/test_custom_type_casters.cpp
index d565add264..b4af02a452 100644
--- a/3rdparty/pybind11/tests/test_custom_type_casters.cpp
+++ b/3rdparty/pybind11/tests/test_custom_type_casters.cpp
@@ -7,23 +7,37 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include "constructor_stats.h"
-
+#include "pybind11_tests.h"
 
 // py::arg/py::arg_v testing: these arguments just record their argument when invoked
-class ArgInspector1 { public: std::string arg = "(default arg inspector 1)"; };
-class ArgInspector2 { public: std::string arg = "(default arg inspector 2)"; };
-class ArgAlwaysConverts { };
-namespace pybind11 { namespace detail {
-template <> struct type_caster<ArgInspector1> {
+class ArgInspector1 {
+public:
+    std::string arg = "(default arg inspector 1)";
+};
+class ArgInspector2 {
+public:
+    std::string arg = "(default arg inspector 2)";
+};
+class ArgAlwaysConverts {};
+
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <>
+struct type_caster<ArgInspector1> {
 public:
+    // Classic
+#ifdef PYBIND11_DETAIL_UNDERSCORE_BACKWARD_COMPATIBILITY
     PYBIND11_TYPE_CASTER(ArgInspector1, _("ArgInspector1"));
+#else
+    PYBIND11_TYPE_CASTER(ArgInspector1, const_name("ArgInspector1"));
+#endif
 
     bool load(handle src, bool convert) {
-        value.arg = "loading ArgInspector1 argument " +
-            std::string(convert ? "WITH" : "WITHOUT") + " conversion allowed.  "
-            "Argument value = " + (std::string) str(src);
+        value.arg = "loading ArgInspector1 argument " + std::string(convert ? "WITH" : "WITHOUT")
+                    + " conversion allowed.  "
+                      "Argument value = "
+                    + (std::string) str(src);
         return true;
     }
 
@@ -31,14 +45,16 @@ template <> struct type_caster<ArgInspector1> {
         return str(src.arg).release();
     }
 };
-template <> struct type_caster<ArgInspector2> {
+template <>
+struct type_caster<ArgInspector2> {
 public:
-    PYBIND11_TYPE_CASTER(ArgInspector2, _("ArgInspector2"));
+    PYBIND11_TYPE_CASTER(ArgInspector2, const_name("ArgInspector2"));
 
     bool load(handle src, bool convert) {
-        value.arg = "loading ArgInspector2 argument " +
-            std::string(convert ? "WITH" : "WITHOUT") + " conversion allowed.  "
-            "Argument value = " + (std::string) str(src);
+        value.arg = "loading ArgInspector2 argument " + std::string(convert ? "WITH" : "WITHOUT")
+                    + " conversion allowed.  "
+                      "Argument value = "
+                    + (std::string) str(src);
         return true;
     }
 
@@ -46,20 +62,19 @@ template <> struct type_caster<ArgInspector2> {
         return str(src.arg).release();
     }
 };
-template <> struct type_caster<ArgAlwaysConverts> {
+template <>
+struct type_caster<ArgAlwaysConverts> {
 public:
-    PYBIND11_TYPE_CASTER(ArgAlwaysConverts, _("ArgAlwaysConverts"));
+    PYBIND11_TYPE_CASTER(ArgAlwaysConverts, const_name("ArgAlwaysConverts"));
 
-    bool load(handle, bool convert) {
-        return convert;
-    }
+    bool load(handle, bool convert) { return convert; }
 
     static handle cast(const ArgAlwaysConverts &, return_value_policy, handle) {
         return py::none().release();
     }
 };
 } // namespace detail
-} // namespace pybind11
+} // namespace PYBIND11_NAMESPACE
 
 // test_custom_caster_destruction
 class DestructionTester {
@@ -67,13 +82,21 @@ class DestructionTester {
     DestructionTester() { print_default_created(this); }
     ~DestructionTester() { print_destroyed(this); }
     DestructionTester(const DestructionTester &) { print_copy_created(this); }
-    DestructionTester(DestructionTester &&) { print_move_created(this); }
-    DestructionTester &operator=(const DestructionTester &) { print_copy_assigned(this); return *this; }
-    DestructionTester &operator=(DestructionTester &&) { print_move_assigned(this); return *this; }
+    DestructionTester(DestructionTester &&) noexcept { print_move_created(this); }
+    DestructionTester &operator=(const DestructionTester &) {
+        print_copy_assigned(this);
+        return *this;
+    }
+    DestructionTester &operator=(DestructionTester &&) noexcept {
+        print_move_assigned(this);
+        return *this;
+    }
 };
-namespace pybind11 { namespace detail {
-template <> struct type_caster<DestructionTester> {
-    PYBIND11_TYPE_CASTER(DestructionTester, _("DestructionTester"));
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <>
+struct type_caster<DestructionTester> {
+    PYBIND11_TYPE_CASTER(DestructionTester, const_name("DestructionTester"));
     bool load(handle, bool) { return true; }
 
     static handle cast(const DestructionTester &, return_value_policy, handle) {
@@ -81,7 +104,35 @@ template <> struct type_caster<DestructionTester> {
     }
 };
 } // namespace detail
-} // namespace pybind11
+} // namespace PYBIND11_NAMESPACE
+
+// Define type caster outside of `pybind11::detail` and then alias it.
+namespace other_lib {
+struct MyType {};
+// Corrupt `py` shorthand alias for surrounding context.
+namespace py {}
+// Corrupt unqualified relative `pybind11` namespace.
+namespace PYBIND11_NAMESPACE {}
+// Correct alias.
+namespace py_ = ::pybind11;
+// Define caster. This is effectively no-op, we only ensure it compiles and we
+// don't have any symbol collision when using macro mixin.
+struct my_caster {
+    PYBIND11_TYPE_CASTER(MyType, py_::detail::const_name("MyType"));
+    bool load(py_::handle, bool) { return true; }
+
+    static py_::handle cast(const MyType &, py_::return_value_policy, py_::handle) {
+        return py_::bool_(true).release();
+    }
+};
+} // namespace other_lib
+// Effectively "alias" it into correct namespace (via inheritance).
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <>
+struct type_caster<other_lib::MyType> : public other_lib::my_caster {};
+} // namespace detail
+} // namespace PYBIND11_NAMESPACE
 
 TEST_SUBMODULE(custom_type_casters, m) {
     // test_custom_type_casters
@@ -94,34 +145,65 @@ TEST_SUBMODULE(custom_type_casters, m) {
     class ArgInspector {
     public:
         ArgInspector1 f(ArgInspector1 a, ArgAlwaysConverts) { return a; }
-        std::string g(ArgInspector1 a, const ArgInspector1 &b, int c, ArgInspector2 *d, ArgAlwaysConverts) {
+        std::string g(const ArgInspector1 &a,
+                      const ArgInspector1 &b,
+                      int c,
+                      ArgInspector2 *d,
+                      ArgAlwaysConverts) {
             return a.arg + "\n" + b.arg + "\n" + std::to_string(c) + "\n" + d->arg;
         }
         static ArgInspector2 h(ArgInspector2 a, ArgAlwaysConverts) { return a; }
     };
+    // [workaround(intel)] ICC 20/21 breaks with py::arg().stuff, using py::arg{}.stuff works.
     py::class_<ArgInspector>(m, "ArgInspector")
         .def(py::init<>())
         .def("f", &ArgInspector::f, py::arg(), py::arg() = ArgAlwaysConverts())
-        .def("g", &ArgInspector::g, "a"_a.noconvert(), "b"_a, "c"_a.noconvert()=13, "d"_a=ArgInspector2(), py::arg() = ArgAlwaysConverts())
-        .def_static("h", &ArgInspector::h, py::arg().noconvert(), py::arg() = ArgAlwaysConverts())
-        ;
-    m.def("arg_inspect_func", [](ArgInspector2 a, ArgInspector1 b, ArgAlwaysConverts) { return a.arg + "\n" + b.arg; },
-            py::arg().noconvert(false), py::arg_v(nullptr, ArgInspector1()).noconvert(true), py::arg() = ArgAlwaysConverts());
-
-    m.def("floats_preferred", [](double f) { return 0.5 * f; }, py::arg("f"));
-    m.def("floats_only", [](double f) { return 0.5 * f; }, py::arg("f").noconvert());
-    m.def("ints_preferred", [](int i) { return i / 2; }, py::arg("i"));
-    m.def("ints_only", [](int i) { return i / 2; }, py::arg("i").noconvert());
+        .def("g",
+             &ArgInspector::g,
+             "a"_a.noconvert(),
+             "b"_a,
+             "c"_a.noconvert() = 13,
+             "d"_a = ArgInspector2(),
+             py::arg() = ArgAlwaysConverts())
+        .def_static("h", &ArgInspector::h, py::arg{}.noconvert(), py::arg() = ArgAlwaysConverts());
+    m.def(
+        "arg_inspect_func",
+        [](const ArgInspector2 &a, const ArgInspector1 &b, ArgAlwaysConverts) {
+            return a.arg + "\n" + b.arg;
+        },
+        py::arg{}.noconvert(false),
+        py::arg_v(nullptr, ArgInspector1()).noconvert(true),
+        py::arg() = ArgAlwaysConverts());
+
+    m.def(
+        "floats_preferred", [](double f) { return 0.5 * f; }, "f"_a);
+    m.def(
+        "floats_only", [](double f) { return 0.5 * f; }, "f"_a.noconvert());
+    m.def(
+        "ints_preferred", [](int i) { return i / 2; }, "i"_a);
+    m.def(
+        "ints_only", [](int i) { return i / 2; }, "i"_a.noconvert());
 
     // test_custom_caster_destruction
     // Test that `take_ownership` works on types with a custom type caster when given a pointer
 
     // default policy: don't take ownership:
-    m.def("custom_caster_no_destroy", []() { static auto *dt = new DestructionTester(); return dt; });
-
-    m.def("custom_caster_destroy", []() { return new DestructionTester(); },
-            py::return_value_policy::take_ownership); // Takes ownership: destroy when finished
-    m.def("custom_caster_destroy_const", []() -> const DestructionTester * { return new DestructionTester(); },
-            py::return_value_policy::take_ownership); // Likewise (const doesn't inhibit destruction)
-    m.def("destruction_tester_cstats", &ConstructorStats::get<DestructionTester>, py::return_value_policy::reference);
+    m.def("custom_caster_no_destroy", []() {
+        static auto *dt = new DestructionTester();
+        return dt;
+    });
+
+    m.def(
+        "custom_caster_destroy",
+        []() { return new DestructionTester(); },
+        py::return_value_policy::take_ownership); // Takes ownership: destroy when finished
+    m.def(
+        "custom_caster_destroy_const",
+        []() -> const DestructionTester * { return new DestructionTester(); },
+        py::return_value_policy::take_ownership); // Likewise (const doesn't inhibit destruction)
+    m.def("destruction_tester_cstats",
+          &ConstructorStats::get<DestructionTester>,
+          py::return_value_policy::reference);
+
+    m.def("other_lib_type", [](other_lib::MyType x) { return x; });
 }
diff --git a/3rdparty/pybind11/tests/test_custom_type_casters.py b/3rdparty/pybind11/tests/test_custom_type_casters.py
index bb74d54eb3..adfa6cf86e 100644
--- a/3rdparty/pybind11/tests/test_custom_type_casters.py
+++ b/3rdparty/pybind11/tests/test_custom_type_casters.py
@@ -1,5 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
+
 from pybind11_tests import custom_type_casters as m
 
 
@@ -18,7 +18,7 @@ def test_noconvert_args(msg):
         loading ArgInspector1 argument WITH conversion allowed.  Argument value = this is b
         13
         loading ArgInspector2 argument WITH conversion allowed.  Argument value = (default arg inspector 2)
-    """  # noqa: E501 line too long
+    """
     )
     assert (
         msg(a.g("this is a", "this is b", 42))
@@ -27,7 +27,7 @@ def test_noconvert_args(msg):
         loading ArgInspector1 argument WITH conversion allowed.  Argument value = this is b
         42
         loading ArgInspector2 argument WITH conversion allowed.  Argument value = (default arg inspector 2)
-    """  # noqa: E501 line too long
+    """
     )
     assert (
         msg(a.g("this is a", "this is b", 42, "this is d"))
@@ -75,7 +75,7 @@ def test_noconvert_args(msg):
             1. (i: int) -> int
 
         Invoked with: 4.0
-    """  # noqa: E501 line too long
+    """
     )
 
     assert m.ints_only(4) == 2
@@ -114,3 +114,7 @@ def test_custom_caster_destruction():
 
     # Make sure we still only have the original object (from ..._no_destroy()) alive:
     assert cstats.alive() == 1
+
+
+def test_custom_caster_other_lib():
+    assert m.other_lib_type(True)
diff --git a/3rdparty/pybind11/tests/test_custom_type_setup.cpp b/3rdparty/pybind11/tests/test_custom_type_setup.cpp
new file mode 100644
index 0000000000..42fae05d5d
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_custom_type_setup.cpp
@@ -0,0 +1,41 @@
+/*
+    tests/test_custom_type_setup.cpp -- Tests `pybind11::custom_type_setup`
+
+    Copyright (c) Google LLC
+
+    All rights reserved. Use of this source code is governed by a
+    BSD-style license that can be found in the LICENSE file.
+*/
+
+#include <pybind11/pybind11.h>
+
+#include "pybind11_tests.h"
+
+namespace py = pybind11;
+
+namespace {
+
+struct OwnsPythonObjects {
+    py::object value = py::none();
+};
+} // namespace
+
+TEST_SUBMODULE(custom_type_setup, m) {
+    py::class_<OwnsPythonObjects> cls(
+        m, "OwnsPythonObjects", py::custom_type_setup([](PyHeapTypeObject *heap_type) {
+            auto *type = &heap_type->ht_type;
+            type->tp_flags |= Py_TPFLAGS_HAVE_GC;
+            type->tp_traverse = [](PyObject *self_base, visitproc visit, void *arg) {
+                auto &self = py::cast<OwnsPythonObjects &>(py::handle(self_base));
+                Py_VISIT(self.value.ptr());
+                return 0;
+            };
+            type->tp_clear = [](PyObject *self_base) {
+                auto &self = py::cast<OwnsPythonObjects &>(py::handle(self_base));
+                self.value = py::none();
+                return 0;
+            };
+        }));
+    cls.def(py::init<>());
+    cls.def_readwrite("value", &OwnsPythonObjects::value);
+}
diff --git a/3rdparty/pybind11/tests/test_custom_type_setup.py b/3rdparty/pybind11/tests/test_custom_type_setup.py
new file mode 100644
index 0000000000..19b44c9de2
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_custom_type_setup.py
@@ -0,0 +1,48 @@
+import gc
+import weakref
+
+import pytest
+
+import env  # noqa: F401
+from pybind11_tests import custom_type_setup as m
+
+
+@pytest.fixture
+def gc_tester():
+    """Tests that an object is garbage collected.
+
+    Assumes that any unreferenced objects are fully collected after calling
+    `gc.collect()`.  That is true on CPython, but does not appear to reliably
+    hold on PyPy.
+    """
+
+    weak_refs = []
+
+    def add_ref(obj):
+        # PyPy does not support `gc.is_tracked`.
+        if hasattr(gc, "is_tracked"):
+            assert gc.is_tracked(obj)
+        weak_refs.append(weakref.ref(obj))
+
+    yield add_ref
+
+    gc.collect()
+    for ref in weak_refs:
+        assert ref() is None
+
+
+# PyPy does not seem to reliably garbage collect.
+@pytest.mark.skipif("env.PYPY")
+def test_self_cycle(gc_tester):
+    obj = m.OwnsPythonObjects()
+    obj.value = obj
+    gc_tester(obj)
+
+
+# PyPy does not seem to reliably garbage collect.
+@pytest.mark.skipif("env.PYPY")
+def test_indirect_cycle(gc_tester):
+    obj = m.OwnsPythonObjects()
+    obj_list = [obj]
+    obj.value = obj_list
+    gc_tester(obj)
diff --git a/3rdparty/pybind11/tests/test_docstring_options.cpp b/3rdparty/pybind11/tests/test_docstring_options.cpp
index 8c8f79fd5f..4d44f4e20d 100644
--- a/3rdparty/pybind11/tests/test_docstring_options.cpp
+++ b/3rdparty/pybind11/tests/test_docstring_options.cpp
@@ -15,35 +15,60 @@ TEST_SUBMODULE(docstring_options, m) {
         py::options options;
         options.disable_function_signatures();
 
-        m.def("test_function1", [](int, int) {}, py::arg("a"), py::arg("b"));
-        m.def("test_function2", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
-
-        m.def("test_overloaded1", [](int) {}, py::arg("i"), "Overload docstring");
-        m.def("test_overloaded1", [](double) {}, py::arg("d"));
-
-        m.def("test_overloaded2", [](int) {}, py::arg("i"), "overload docstring 1");
-        m.def("test_overloaded2", [](double) {}, py::arg("d"), "overload docstring 2");
-
-        m.def("test_overloaded3", [](int) {}, py::arg("i"));
-        m.def("test_overloaded3", [](double) {}, py::arg("d"), "Overload docstr");
+        m.def(
+            "test_function1", [](int, int) {}, py::arg("a"), py::arg("b"));
+        m.def(
+            "test_function2", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+
+        m.def(
+            "test_overloaded1", [](int) {}, py::arg("i"), "Overload docstring");
+        m.def(
+            "test_overloaded1", [](double) {}, py::arg("d"));
+
+        m.def(
+            "test_overloaded2", [](int) {}, py::arg("i"), "overload docstring 1");
+        m.def(
+            "test_overloaded2", [](double) {}, py::arg("d"), "overload docstring 2");
+
+        m.def(
+            "test_overloaded3", [](int) {}, py::arg("i"));
+        m.def(
+            "test_overloaded3", [](double) {}, py::arg("d"), "Overload docstr");
 
         options.enable_function_signatures();
 
-        m.def("test_function3", [](int, int) {}, py::arg("a"), py::arg("b"));
-        m.def("test_function4", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+        m.def(
+            "test_function3", [](int, int) {}, py::arg("a"), py::arg("b"));
+        m.def(
+            "test_function4", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
 
         options.disable_function_signatures().disable_user_defined_docstrings();
 
-        m.def("test_function5", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+        m.def(
+            "test_function5", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
 
         {
             py::options nested_options;
             nested_options.enable_user_defined_docstrings();
-            m.def("test_function6", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+            m.def(
+                "test_function6",
+                [](int, int) {},
+                py::arg("a"),
+                py::arg("b"),
+                "A custom docstring");
         }
     }
 
-    m.def("test_function7", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+    m.def(
+        "test_function7", [](int, int) {}, py::arg("a"), py::arg("b"), "A custom docstring");
+
+    {
+        py::options options;
+        options.disable_user_defined_docstrings();
+        options.disable_function_signatures();
+
+        m.def("test_function8", []() {});
+    }
 
     {
         py::options options;
@@ -55,7 +80,9 @@ TEST_SUBMODULE(docstring_options, m) {
             int getValue() const { return value; }
         };
         py::class_<DocstringTestFoo>(m, "DocstringTestFoo", "This is a class docstring")
-            .def_property("value_prop", &DocstringTestFoo::getValue, &DocstringTestFoo::setValue, "This is a property docstring")
-        ;
+            .def_property("value_prop",
+                          &DocstringTestFoo::getValue,
+                          &DocstringTestFoo::setValue,
+                          "This is a property docstring");
     }
 }
diff --git a/3rdparty/pybind11/tests/test_docstring_options.py b/3rdparty/pybind11/tests/test_docstring_options.py
index 87d80d2df6..fcd16b89fd 100644
--- a/3rdparty/pybind11/tests/test_docstring_options.py
+++ b/3rdparty/pybind11/tests/test_docstring_options.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 from pybind11_tests import docstring_options as m
 
 
@@ -34,6 +33,9 @@ def test_docstring_options():
     assert m.test_function7.__doc__.startswith("test_function7(a: int, b: int) -> None")
     assert m.test_function7.__doc__.endswith("A custom docstring\n")
 
+    # when all options are disabled, no docstring (instead of an empty one) should be generated
+    assert m.test_function8.__doc__ is None
+
     # Suppression of user-defined docstrings for non-function objects
     assert not m.DocstringTestFoo.__doc__
     assert not m.DocstringTestFoo.value_prop.__doc__
diff --git a/3rdparty/pybind11/tests/test_eigen.cpp b/3rdparty/pybind11/tests/test_eigen.cpp
index 2cc2243d6f..591dacc624 100644
--- a/3rdparty/pybind11/tests/test_eigen.cpp
+++ b/3rdparty/pybind11/tests/test_eigen.cpp
@@ -7,26 +7,29 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/eigen.h>
 #include <pybind11/stl.h>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 #if defined(_MSC_VER)
-#  pragma warning(disable: 4996) // C4996: std::unary_negation is deprecated
+#    pragma warning(disable : 4996) // C4996: std::unary_negation is deprecated
 #endif
 
 #include <Eigen/Cholesky>
 
 using MatrixXdR = Eigen::Matrix<double, Eigen::Dynamic, Eigen::Dynamic, Eigen::RowMajor>;
 
-
-
 // Sets/resets a testing reference matrix to have values of 10*r + c, where r and c are the
 // (1-based) row/column number.
-template <typename M> void reset_ref(M &x) {
-    for (int i = 0; i < x.rows(); i++) for (int j = 0; j < x.cols(); j++)
-        x(i, j) = 11 + 10*i + j;
+template <typename M>
+void reset_ref(M &x) {
+    for (int i = 0; i < x.rows(); i++) {
+        for (int j = 0; j < x.cols(); j++) {
+            x(i, j) = 11 + 10 * i + j;
+        }
+    }
 }
 
 // Returns a static, column-major matrix
@@ -54,16 +57,18 @@ void reset_refs() {
 }
 
 // Returns element 2,1 from a matrix (used to test copy/nocopy)
-double get_elem(Eigen::Ref<const Eigen::MatrixXd> m) { return m(2, 1); };
-
+double get_elem(const Eigen::Ref<const Eigen::MatrixXd> &m) { return m(2, 1); };
 
 // Returns a matrix with 10*r + 100*c added to each matrix element (to help test that the matrix
 // reference is referencing rows/columns correctly).
-template <typename MatrixArgType> Eigen::MatrixXd adjust_matrix(MatrixArgType m) {
+template <typename MatrixArgType>
+Eigen::MatrixXd adjust_matrix(MatrixArgType m) {
     Eigen::MatrixXd ret(m);
-    for (int c = 0; c < m.cols(); c++)
-        for (int r = 0; r < m.rows(); r++)
-            ret(r, c) += 10*r + 100*c;  // NOLINT(clang-analyzer-core.uninitialized.Assign)
+    for (int c = 0; c < m.cols(); c++) {
+        for (int r = 0; r < m.rows(); r++) {
+            ret(r, c) += 10 * r + 100 * c; // NOLINT(clang-analyzer-core.uninitialized.Assign)
+        }
+    }
     return ret;
 }
 
@@ -90,27 +95,35 @@ TEST_SUBMODULE(eigen, m) {
 
     // various tests
     m.def("double_col", [](const Eigen::VectorXf &x) -> Eigen::VectorXf { return 2.0f * x; });
-    m.def("double_row", [](const Eigen::RowVectorXf &x) -> Eigen::RowVectorXf { return 2.0f * x; });
-    m.def("double_complex", [](const Eigen::VectorXcf &x) -> Eigen::VectorXcf { return 2.0f * x; });
+    m.def("double_row",
+          [](const Eigen::RowVectorXf &x) -> Eigen::RowVectorXf { return 2.0f * x; });
+    m.def("double_complex",
+          [](const Eigen::VectorXcf &x) -> Eigen::VectorXcf { return 2.0f * x; });
     m.def("double_threec", [](py::EigenDRef<Eigen::Vector3f> x) { x *= 2; });
     m.def("double_threer", [](py::EigenDRef<Eigen::RowVector3f> x) { x *= 2; });
-    m.def("double_mat_cm", [](Eigen::MatrixXf x) -> Eigen::MatrixXf { return 2.0f * x; });
-    m.def("double_mat_rm", [](DenseMatrixR x) -> DenseMatrixR { return 2.0f * x; });
+    m.def("double_mat_cm", [](const Eigen::MatrixXf &x) -> Eigen::MatrixXf { return 2.0f * x; });
+    m.def("double_mat_rm", [](const DenseMatrixR &x) -> DenseMatrixR { return 2.0f * x; });
 
     // test_eigen_ref_to_python
     // Different ways of passing via Eigen::Ref; the first and second are the Eigen-recommended
-    m.def("cholesky1", [](Eigen::Ref<MatrixXdR> x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
-    m.def("cholesky2", [](const Eigen::Ref<const MatrixXdR> &x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
-    m.def("cholesky3", [](const Eigen::Ref<MatrixXdR> &x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
-    m.def("cholesky4", [](Eigen::Ref<const MatrixXdR> x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
+    m.def("cholesky1",
+          [](const Eigen::Ref<MatrixXdR> &x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
+    m.def("cholesky2", [](const Eigen::Ref<const MatrixXdR> &x) -> Eigen::MatrixXd {
+        return x.llt().matrixL();
+    });
+    m.def("cholesky3",
+          [](const Eigen::Ref<MatrixXdR> &x) -> Eigen::MatrixXd { return x.llt().matrixL(); });
+    m.def("cholesky4", [](const Eigen::Ref<const MatrixXdR> &x) -> Eigen::MatrixXd {
+        return x.llt().matrixL();
+    });
 
     // test_eigen_ref_mutators
-    // Mutators: these add some value to the given element using Eigen, but Eigen should be mapping into
-    // the numpy array data and so the result should show up there.  There are three versions: one that
-    // works on a contiguous-row matrix (numpy's default), one for a contiguous-column matrix, and one
-    // for any matrix.
-    auto add_rm = [](Eigen::Ref<MatrixXdR> x, int r, int c, double v) { x(r,c) += v; };
-    auto add_cm = [](Eigen::Ref<Eigen::MatrixXd> x, int r, int c, double v) { x(r,c) += v; };
+    // Mutators: these add some value to the given element using Eigen, but Eigen should be mapping
+    // into the numpy array data and so the result should show up there.  There are three versions:
+    // one that works on a contiguous-row matrix (numpy's default), one for a contiguous-column
+    // matrix, and one for any matrix.
+    auto add_rm = [](Eigen::Ref<MatrixXdR> x, int r, int c, double v) { x(r, c) += v; };
+    auto add_cm = [](Eigen::Ref<Eigen::MatrixXd> x, int r, int c, double v) { x(r, c) += v; };
 
     // Mutators (Eigen maps into numpy variables):
     m.def("add_rm", add_rm); // Only takes row-contiguous
@@ -121,7 +134,8 @@ TEST_SUBMODULE(eigen, m) {
     m.def("add2", add_cm);
     m.def("add2", add_rm);
     // This one accepts a matrix of any stride:
-    m.def("add_any", [](py::EigenDRef<Eigen::MatrixXd> x, int r, int c, double v) { x(r,c) += v; });
+    m.def("add_any",
+          [](py::EigenDRef<Eigen::MatrixXd> x, int r, int c, double v) { x(r, c) += v; });
 
     // Return mutable references (numpy maps into eigen variables)
     m.def("get_cm_ref", []() { return Eigen::Ref<Eigen::MatrixXd>(get_cm()); });
@@ -133,49 +147,72 @@ TEST_SUBMODULE(eigen, m) {
     m.def("reset_refs", reset_refs); // Restores get_{cm,rm}_ref to original values
 
     // Increments and returns ref to (same) matrix
-    m.def("incr_matrix", [](Eigen::Ref<Eigen::MatrixXd> m, double v) {
-        m += Eigen::MatrixXd::Constant(m.rows(), m.cols(), v);
-        return m;
-    }, py::return_value_policy::reference);
+    m.def(
+        "incr_matrix",
+        [](Eigen::Ref<Eigen::MatrixXd> m, double v) {
+            m += Eigen::MatrixXd::Constant(m.rows(), m.cols(), v);
+            return m;
+        },
+        py::return_value_policy::reference);
 
     // Same, but accepts a matrix of any strides
-    m.def("incr_matrix_any", [](py::EigenDRef<Eigen::MatrixXd> m, double v) {
-        m += Eigen::MatrixXd::Constant(m.rows(), m.cols(), v);
-        return m;
-    }, py::return_value_policy::reference);
+    m.def(
+        "incr_matrix_any",
+        [](py::EigenDRef<Eigen::MatrixXd> m, double v) {
+            m += Eigen::MatrixXd::Constant(m.rows(), m.cols(), v);
+            return m;
+        },
+        py::return_value_policy::reference);
 
     // Returns an eigen slice of even rows
-    m.def("even_rows", [](py::EigenDRef<Eigen::MatrixXd> m) {
-        return py::EigenDMap<Eigen::MatrixXd>(
-                m.data(), (m.rows() + 1) / 2, m.cols(),
+    m.def(
+        "even_rows",
+        [](py::EigenDRef<Eigen::MatrixXd> m) {
+            return py::EigenDMap<Eigen::MatrixXd>(
+                m.data(),
+                (m.rows() + 1) / 2,
+                m.cols(),
                 py::EigenDStride(m.outerStride(), 2 * m.innerStride()));
-    }, py::return_value_policy::reference);
+        },
+        py::return_value_policy::reference);
 
     // Returns an eigen slice of even columns
-    m.def("even_cols", [](py::EigenDRef<Eigen::MatrixXd> m) {
-        return py::EigenDMap<Eigen::MatrixXd>(
-                m.data(), m.rows(), (m.cols() + 1) / 2,
+    m.def(
+        "even_cols",
+        [](py::EigenDRef<Eigen::MatrixXd> m) {
+            return py::EigenDMap<Eigen::MatrixXd>(
+                m.data(),
+                m.rows(),
+                (m.cols() + 1) / 2,
                 py::EigenDStride(2 * m.outerStride(), m.innerStride()));
-    }, py::return_value_policy::reference);
+        },
+        py::return_value_policy::reference);
 
     // Returns diagonals: a vector-like object with an inner stride != 1
     m.def("diagonal", [](const Eigen::Ref<const Eigen::MatrixXd> &x) { return x.diagonal(); });
-    m.def("diagonal_1", [](const Eigen::Ref<const Eigen::MatrixXd> &x) { return x.diagonal<1>(); });
-    m.def("diagonal_n", [](const Eigen::Ref<const Eigen::MatrixXd> &x, int index) { return x.diagonal(index); });
+    m.def("diagonal_1",
+          [](const Eigen::Ref<const Eigen::MatrixXd> &x) { return x.diagonal<1>(); });
+    m.def("diagonal_n",
+          [](const Eigen::Ref<const Eigen::MatrixXd> &x, int index) { return x.diagonal(index); });
 
     // Return a block of a matrix (gives non-standard strides)
-    m.def("block", [](const Eigen::Ref<const Eigen::MatrixXd> &x, int start_row, int start_col, int block_rows, int block_cols) {
-        return x.block(start_row, start_col, block_rows, block_cols);
-    });
+    m.def("block",
+          [](const Eigen::Ref<const Eigen::MatrixXd> &x,
+             int start_row,
+             int start_col,
+             int block_rows,
+             int block_cols) { return x.block(start_row, start_col, block_rows, block_cols); });
 
     // test_eigen_return_references, test_eigen_keepalive
     // return value referencing/copying tests:
     class ReturnTester {
         Eigen::MatrixXd mat = create();
+
     public:
         ReturnTester() { print_created(this); }
         ~ReturnTester() { print_destroyed(this); }
         static Eigen::MatrixXd create() { return Eigen::MatrixXd::Ones(10, 10); }
+        // NOLINTNEXTLINE(readability-const-return-type)
         static const Eigen::MatrixXd createConst() { return Eigen::MatrixXd::Ones(10, 10); }
         Eigen::MatrixXd &get() { return mat; }
         Eigen::MatrixXd *getPtr() { return &mat; }
@@ -183,12 +220,24 @@ TEST_SUBMODULE(eigen, m) {
         const Eigen::MatrixXd *viewPtr() { return &mat; }
         Eigen::Ref<Eigen::MatrixXd> ref() { return mat; }
         Eigen::Ref<const Eigen::MatrixXd> refConst() { return mat; }
-        Eigen::Block<Eigen::MatrixXd> block(int r, int c, int nrow, int ncol) { return mat.block(r, c, nrow, ncol); }
-        Eigen::Block<const Eigen::MatrixXd> blockConst(int r, int c, int nrow, int ncol) const { return mat.block(r, c, nrow, ncol); }
-        py::EigenDMap<Eigen::Matrix2d> corners() { return py::EigenDMap<Eigen::Matrix2d>(mat.data(),
-                    py::EigenDStride(mat.outerStride() * (mat.outerSize()-1), mat.innerStride() * (mat.innerSize()-1))); }
-        py::EigenDMap<const Eigen::Matrix2d> cornersConst() const { return py::EigenDMap<const Eigen::Matrix2d>(mat.data(),
-                    py::EigenDStride(mat.outerStride() * (mat.outerSize()-1), mat.innerStride() * (mat.innerSize()-1))); }
+        Eigen::Block<Eigen::MatrixXd> block(int r, int c, int nrow, int ncol) {
+            return mat.block(r, c, nrow, ncol);
+        }
+        Eigen::Block<const Eigen::MatrixXd> blockConst(int r, int c, int nrow, int ncol) const {
+            return mat.block(r, c, nrow, ncol);
+        }
+        py::EigenDMap<Eigen::Matrix2d> corners() {
+            return py::EigenDMap<Eigen::Matrix2d>(
+                mat.data(),
+                py::EigenDStride(mat.outerStride() * (mat.outerSize() - 1),
+                                 mat.innerStride() * (mat.innerSize() - 1)));
+        }
+        py::EigenDMap<const Eigen::Matrix2d> cornersConst() const {
+            return py::EigenDMap<const Eigen::Matrix2d>(
+                mat.data(),
+                py::EigenDStride(mat.outerStride() * (mat.outerSize() - 1),
+                                 mat.innerStride() * (mat.innerSize() - 1)));
+        }
     };
     using rvp = py::return_value_policy;
     py::class_<ReturnTester>(m, "ReturnTester")
@@ -199,9 +248,9 @@ TEST_SUBMODULE(eigen, m) {
         .def("get_ptr", &ReturnTester::getPtr, rvp::reference_internal)
         .def("view", &ReturnTester::view, rvp::reference_internal)
         .def("view_ptr", &ReturnTester::view, rvp::reference_internal)
-        .def("copy_get", &ReturnTester::get)   // Default rvp: copy
-        .def("copy_view", &ReturnTester::view) //         "
-        .def("ref", &ReturnTester::ref) // Default for Ref is to reference
+        .def("copy_get", &ReturnTester::get)       // Default rvp: copy
+        .def("copy_view", &ReturnTester::view)     //         "
+        .def("ref", &ReturnTester::ref)            // Default for Ref is to reference
         .def("ref_const", &ReturnTester::refConst) // Likewise, but const
         .def("ref_safe", &ReturnTester::ref, rvp::reference_internal)
         .def("ref_const_safe", &ReturnTester::refConst, rvp::reference_internal)
@@ -212,52 +261,55 @@ TEST_SUBMODULE(eigen, m) {
         .def("block_const", &ReturnTester::blockConst, rvp::reference_internal)
         .def("copy_block", &ReturnTester::block, rvp::copy)
         .def("corners", &ReturnTester::corners, rvp::reference_internal)
-        .def("corners_const", &ReturnTester::cornersConst, rvp::reference_internal)
-        ;
+        .def("corners_const", &ReturnTester::cornersConst, rvp::reference_internal);
 
     // test_special_matrix_objects
     // Returns a DiagonalMatrix with diagonal (1,2,3,...)
     m.def("incr_diag", [](int k) {
         Eigen::DiagonalMatrix<int, Eigen::Dynamic> m(k);
-        for (int i = 0; i < k; i++) m.diagonal()[i] = i+1;
+        for (int i = 0; i < k; i++) {
+            m.diagonal()[i] = i + 1;
+        }
         return m;
     });
 
     // Returns a SelfAdjointView referencing the lower triangle of m
-    m.def("symmetric_lower", [](const Eigen::MatrixXi &m) {
-            return m.selfadjointView<Eigen::Lower>();
-    });
+    m.def("symmetric_lower",
+          [](const Eigen::MatrixXi &m) { return m.selfadjointView<Eigen::Lower>(); });
     // Returns a SelfAdjointView referencing the lower triangle of m
-    m.def("symmetric_upper", [](const Eigen::MatrixXi &m) {
-            return m.selfadjointView<Eigen::Upper>();
-    });
+    m.def("symmetric_upper",
+          [](const Eigen::MatrixXi &m) { return m.selfadjointView<Eigen::Upper>(); });
 
     // Test matrix for various functions below.
     Eigen::MatrixXf mat(5, 6);
-    mat << 0,  3,  0,  0,  0, 11,
-           22, 0,  0,  0, 17, 11,
-           7,  5,  0,  1,  0, 11,
-           0,  0,  0,  0,  0, 11,
-           0,  0, 14,  0,  8, 11;
+    mat << 0, 3, 0, 0, 0, 11, 22, 0, 0, 0, 17, 11, 7, 5, 0, 1, 0, 11, 0, 0, 0, 0, 0, 11, 0, 0, 14,
+        0, 8, 11;
 
     // test_fixed, and various other tests
     m.def("fixed_r", [mat]() -> FixedMatrixR { return FixedMatrixR(mat); });
+    // Our Eigen does a hack which respects constness through the numpy writeable flag.
+    // Therefore, the const return actually affects this type despite being an rvalue.
+    // NOLINTNEXTLINE(readability-const-return-type)
     m.def("fixed_r_const", [mat]() -> const FixedMatrixR { return FixedMatrixR(mat); });
     m.def("fixed_c", [mat]() -> FixedMatrixC { return FixedMatrixC(mat); });
     m.def("fixed_copy_r", [](const FixedMatrixR &m) -> FixedMatrixR { return m; });
     m.def("fixed_copy_c", [](const FixedMatrixC &m) -> FixedMatrixC { return m; });
     // test_mutator_descriptors
-    m.def("fixed_mutator_r", [](Eigen::Ref<FixedMatrixR>) {});
-    m.def("fixed_mutator_c", [](Eigen::Ref<FixedMatrixC>) {});
-    m.def("fixed_mutator_a", [](py::EigenDRef<FixedMatrixC>) {});
+    m.def("fixed_mutator_r", [](const Eigen::Ref<FixedMatrixR> &) {});
+    m.def("fixed_mutator_c", [](const Eigen::Ref<FixedMatrixC> &) {});
+    m.def("fixed_mutator_a", [](const py::EigenDRef<FixedMatrixC> &) {});
     // test_dense
     m.def("dense_r", [mat]() -> DenseMatrixR { return DenseMatrixR(mat); });
     m.def("dense_c", [mat]() -> DenseMatrixC { return DenseMatrixC(mat); });
     m.def("dense_copy_r", [](const DenseMatrixR &m) -> DenseMatrixR { return m; });
     m.def("dense_copy_c", [](const DenseMatrixC &m) -> DenseMatrixC { return m; });
     // test_sparse, test_sparse_signature
-    m.def("sparse_r", [mat]() -> SparseMatrixR { return Eigen::SparseView<Eigen::MatrixXf>(mat); }); //NOLINT(clang-analyzer-core.uninitialized.UndefReturn)
-    m.def("sparse_c", [mat]() -> SparseMatrixC { return Eigen::SparseView<Eigen::MatrixXf>(mat); });
+    m.def("sparse_r", [mat]() -> SparseMatrixR {
+        // NOLINTNEXTLINE(clang-analyzer-core.uninitialized.UndefReturn)
+        return Eigen::SparseView<Eigen::MatrixXf>(mat);
+    });
+    m.def("sparse_c",
+          [mat]() -> SparseMatrixC { return Eigen::SparseView<Eigen::MatrixXf>(mat); });
     m.def("sparse_copy_r", [](const SparseMatrixR &m) -> SparseMatrixR { return m; });
     m.def("sparse_copy_c", [](const SparseMatrixC &m) -> SparseMatrixC { return m; });
     // test_partially_fixed
@@ -271,41 +323,62 @@ TEST_SUBMODULE(eigen, m) {
     m.def("cpp_copy", [](py::handle m) { return m.cast<Eigen::MatrixXd>()(1, 0); });
     m.def("cpp_ref_c", [](py::handle m) { return m.cast<Eigen::Ref<Eigen::MatrixXd>>()(1, 0); });
     m.def("cpp_ref_r", [](py::handle m) { return m.cast<Eigen::Ref<MatrixXdR>>()(1, 0); });
-    m.def("cpp_ref_any", [](py::handle m) { return m.cast<py::EigenDRef<Eigen::MatrixXd>>()(1, 0); });
+    m.def("cpp_ref_any",
+          [](py::handle m) { return m.cast<py::EigenDRef<Eigen::MatrixXd>>()(1, 0); });
 
+    // [workaround(intel)] ICC 20/21 breaks with py::arg().stuff, using py::arg{}.stuff works.
 
     // test_nocopy_wrapper
     // Test that we can prevent copying into an argument that would normally copy: First a version
     // that would allow copying (if types or strides don't match) for comparison:
     m.def("get_elem", &get_elem);
     // Now this alternative that calls the tells pybind to fail rather than copy:
-    m.def("get_elem_nocopy", [](Eigen::Ref<const Eigen::MatrixXd> m) -> double { return get_elem(m); },
-            py::arg().noconvert());
+    m.def(
+        "get_elem_nocopy",
+        [](const Eigen::Ref<const Eigen::MatrixXd> &m) -> double { return get_elem(m); },
+        py::arg{}.noconvert());
     // Also test a row-major-only no-copy const ref:
-    m.def("get_elem_rm_nocopy", [](Eigen::Ref<const Eigen::Matrix<long, -1, -1, Eigen::RowMajor>> &m) -> long { return m(2, 1); },
-            py::arg().noconvert());
-
-    // test_issue738
-    // Issue #738: 1xN or Nx1 2D matrices were neither accepted nor properly copied with an
+    m.def(
+        "get_elem_rm_nocopy",
+        [](Eigen::Ref<const Eigen::Matrix<long, -1, -1, Eigen::RowMajor>> &m) -> long {
+            return m(2, 1);
+        },
+        py::arg{}.noconvert());
+
+    // test_issue738, test_zero_length
+    // Issue #738: 1×N or N×1 2D matrices were neither accepted nor properly copied with an
     // incompatible stride value on the length-1 dimension--but that should be allowed (without
     // requiring a copy!) because the stride value can be safely ignored on a size-1 dimension.
-    m.def("iss738_f1", &adjust_matrix<const Eigen::Ref<const Eigen::MatrixXd> &>, py::arg().noconvert());
-    m.def("iss738_f2", &adjust_matrix<const Eigen::Ref<const Eigen::Matrix<double, -1, -1, Eigen::RowMajor>> &>, py::arg().noconvert());
+    // Similarly, 0×N or N×0 matrices were not accepted--again, these should be allowed since
+    // they contain no data. This particularly affects numpy ≥ 1.23, which sets the strides to
+    // 0 if any dimension size is 0.
+    m.def("iss738_f1",
+          &adjust_matrix<const Eigen::Ref<const Eigen::MatrixXd> &>,
+          py::arg{}.noconvert());
+    m.def("iss738_f2",
+          &adjust_matrix<const Eigen::Ref<const Eigen::Matrix<double, -1, -1, Eigen::RowMajor>> &>,
+          py::arg{}.noconvert());
 
     // test_issue1105
     // Issue #1105: when converting from a numpy two-dimensional (Nx1) or (1xN) value into a dense
-    // eigen Vector or RowVector, the argument would fail to load because the numpy copy would fail:
-    // numpy won't broadcast a Nx1 into a 1-dimensional vector.
-    m.def("iss1105_col", [](Eigen::VectorXd) { return true; });
-    m.def("iss1105_row", [](Eigen::RowVectorXd) { return true; });
+    // eigen Vector or RowVector, the argument would fail to load because the numpy copy would
+    // fail: numpy won't broadcast a Nx1 into a 1-dimensional vector.
+    m.def("iss1105_col", [](const Eigen::VectorXd &) { return true; });
+    m.def("iss1105_row", [](const Eigen::RowVectorXd &) { return true; });
 
     // test_named_arguments
     // Make sure named arguments are working properly:
-    m.def("matrix_multiply", [](const py::EigenDRef<const Eigen::MatrixXd> A, const py::EigenDRef<const Eigen::MatrixXd> B)
-            -> Eigen::MatrixXd {
-        if (A.cols() != B.rows()) throw std::domain_error("Nonconformable matrices!");
-        return A * B;
-    }, py::arg("A"), py::arg("B"));
+    m.def(
+        "matrix_multiply",
+        [](const py::EigenDRef<const Eigen::MatrixXd> &A,
+           const py::EigenDRef<const Eigen::MatrixXd> &B) -> Eigen::MatrixXd {
+            if (A.cols() != B.rows()) {
+                throw std::domain_error("Nonconformable matrices!");
+            }
+            return A * B;
+        },
+        py::arg("A"),
+        py::arg("B"));
 
     // test_custom_operator_new
     py::class_<CustomOperatorNew>(m, "CustomOperatorNew")
@@ -317,7 +390,7 @@ TEST_SUBMODULE(eigen, m) {
     // In case of a failure (the caster's temp array does not live long enough), creating
     // a new array (np.ones(10)) increases the chances that the temp array will be garbage
     // collected and/or that its memory will be overridden with different values.
-    m.def("get_elem_direct", [](Eigen::Ref<const Eigen::VectorXd> v) {
+    m.def("get_elem_direct", [](const Eigen::Ref<const Eigen::VectorXd> &v) {
         py::module_::import("numpy").attr("ones")(10);
         return v(5);
     });
diff --git a/3rdparty/pybind11/tests/test_eigen.py b/3rdparty/pybind11/tests/test_eigen.py
index a131dc15d6..9c6485de3c 100644
--- a/3rdparty/pybind11/tests/test_eigen.py
+++ b/3rdparty/pybind11/tests/test_eigen.py
@@ -1,5 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
+
 from pybind11_tests import ConstructorStats
 
 np = pytest.importorskip("numpy")
@@ -200,7 +200,7 @@ def test_negative_stride_from_python(msg):
         double_threer(): incompatible function arguments. The following argument types are supported:
             1. (arg0: numpy.ndarray[numpy.float32[1, 3], flags.writeable]) -> None
 
-        Invoked with: """  # noqa: E501 line too long
+        Invoked with: """
         + repr(np.array([5.0, 4.0, 3.0], dtype="float32"))
     )
 
@@ -212,7 +212,7 @@ def test_negative_stride_from_python(msg):
         double_threec(): incompatible function arguments. The following argument types are supported:
             1. (arg0: numpy.ndarray[numpy.float32[3, 1], flags.writeable]) -> None
 
-        Invoked with: """  # noqa: E501 line too long
+        Invoked with: """
         + repr(np.array([7.0, 4.0, 1.0], dtype="float32"))
     )
 
@@ -221,9 +221,7 @@ def test_nonunit_stride_to_python():
     assert np.all(m.diagonal(ref) == ref.diagonal())
     assert np.all(m.diagonal_1(ref) == ref.diagonal(1))
     for i in range(-5, 7):
-        assert np.all(
-            m.diagonal_n(ref, i) == ref.diagonal(i)
-        ), "m.diagonal_n({})".format(i)
+        assert np.all(m.diagonal_n(ref, i) == ref.diagonal(i)), f"m.diagonal_n({i})"
 
     assert np.all(m.block(ref, 2, 1, 3, 3) == ref[2:5, 1:4])
     assert np.all(m.block(ref, 1, 4, 4, 2) == ref[1:, 4:])
@@ -236,7 +234,7 @@ def test_eigen_ref_to_python():
         mymat = chol(np.array([[1.0, 2, 4], [2, 13, 23], [4, 23, 77]]))
         assert np.all(
             mymat == np.array([[1, 0, 0], [2, 3, 0], [4, 5, 6]])
-        ), "cholesky{}".format(i)
+        ), f"cholesky{i}"
 
 
 def assign_both(a1, a2, r, c, v):
@@ -253,14 +251,14 @@ def array_copy_but_one(a, r, c, v):
 def test_eigen_return_references():
     """Tests various ways of returning references and non-referencing copies"""
 
-    master = np.ones((10, 10))
+    primary = np.ones((10, 10))
     a = m.ReturnTester()
     a_get1 = a.get()
     assert not a_get1.flags.owndata and a_get1.flags.writeable
-    assign_both(a_get1, master, 3, 3, 5)
+    assign_both(a_get1, primary, 3, 3, 5)
     a_get2 = a.get_ptr()
     assert not a_get2.flags.owndata and a_get2.flags.writeable
-    assign_both(a_get1, master, 2, 3, 6)
+    assign_both(a_get1, primary, 2, 3, 6)
 
     a_view1 = a.view()
     assert not a_view1.flags.owndata and not a_view1.flags.writeable
@@ -273,25 +271,25 @@ def test_eigen_return_references():
 
     a_copy1 = a.copy_get()
     assert a_copy1.flags.owndata and a_copy1.flags.writeable
-    np.testing.assert_array_equal(a_copy1, master)
+    np.testing.assert_array_equal(a_copy1, primary)
     a_copy1[7, 7] = -44  # Shouldn't affect anything else
-    c1want = array_copy_but_one(master, 7, 7, -44)
+    c1want = array_copy_but_one(primary, 7, 7, -44)
     a_copy2 = a.copy_view()
     assert a_copy2.flags.owndata and a_copy2.flags.writeable
-    np.testing.assert_array_equal(a_copy2, master)
+    np.testing.assert_array_equal(a_copy2, primary)
     a_copy2[4, 4] = -22  # Shouldn't affect anything else
-    c2want = array_copy_but_one(master, 4, 4, -22)
+    c2want = array_copy_but_one(primary, 4, 4, -22)
 
     a_ref1 = a.ref()
     assert not a_ref1.flags.owndata and a_ref1.flags.writeable
-    assign_both(a_ref1, master, 1, 1, 15)
+    assign_both(a_ref1, primary, 1, 1, 15)
     a_ref2 = a.ref_const()
     assert not a_ref2.flags.owndata and not a_ref2.flags.writeable
     with pytest.raises(ValueError):
         a_ref2[5, 5] = 33
     a_ref3 = a.ref_safe()
     assert not a_ref3.flags.owndata and a_ref3.flags.writeable
-    assign_both(a_ref3, master, 0, 7, 99)
+    assign_both(a_ref3, primary, 0, 7, 99)
     a_ref4 = a.ref_const_safe()
     assert not a_ref4.flags.owndata and not a_ref4.flags.writeable
     with pytest.raises(ValueError):
@@ -299,23 +297,23 @@ def test_eigen_return_references():
 
     a_copy3 = a.copy_ref()
     assert a_copy3.flags.owndata and a_copy3.flags.writeable
-    np.testing.assert_array_equal(a_copy3, master)
+    np.testing.assert_array_equal(a_copy3, primary)
     a_copy3[8, 1] = 11
-    c3want = array_copy_but_one(master, 8, 1, 11)
+    c3want = array_copy_but_one(primary, 8, 1, 11)
     a_copy4 = a.copy_ref_const()
     assert a_copy4.flags.owndata and a_copy4.flags.writeable
-    np.testing.assert_array_equal(a_copy4, master)
+    np.testing.assert_array_equal(a_copy4, primary)
     a_copy4[8, 4] = 88
-    c4want = array_copy_but_one(master, 8, 4, 88)
+    c4want = array_copy_but_one(primary, 8, 4, 88)
 
     a_block1 = a.block(3, 3, 2, 2)
     assert not a_block1.flags.owndata and a_block1.flags.writeable
     a_block1[0, 0] = 55
-    master[3, 3] = 55
+    primary[3, 3] = 55
     a_block2 = a.block_safe(2, 2, 3, 2)
     assert not a_block2.flags.owndata and a_block2.flags.writeable
     a_block2[2, 1] = -123
-    master[4, 3] = -123
+    primary[4, 3] = -123
     a_block3 = a.block_const(6, 7, 4, 3)
     assert not a_block3.flags.owndata and not a_block3.flags.writeable
     with pytest.raises(ValueError):
@@ -323,18 +321,18 @@ def test_eigen_return_references():
 
     a_copy5 = a.copy_block(2, 2, 2, 3)
     assert a_copy5.flags.owndata and a_copy5.flags.writeable
-    np.testing.assert_array_equal(a_copy5, master[2:4, 2:5])
+    np.testing.assert_array_equal(a_copy5, primary[2:4, 2:5])
     a_copy5[1, 1] = 777
-    c5want = array_copy_but_one(master[2:4, 2:5], 1, 1, 777)
+    c5want = array_copy_but_one(primary[2:4, 2:5], 1, 1, 777)
 
     a_corn1 = a.corners()
     assert not a_corn1.flags.owndata and a_corn1.flags.writeable
     a_corn1 *= 50
     a_corn1[1, 1] = 999
-    master[0, 0] = 50
-    master[0, 9] = 50
-    master[9, 0] = 50
-    master[9, 9] = 999
+    primary[0, 0] = 50
+    primary[0, 9] = 50
+    primary[9, 0] = 50
+    primary[9, 9] = 999
     a_corn2 = a.corners_const()
     assert not a_corn2.flags.owndata and not a_corn2.flags.writeable
     with pytest.raises(ValueError):
@@ -342,22 +340,22 @@ def test_eigen_return_references():
 
     # All of the changes made all the way along should be visible everywhere
     # now (except for the copies, of course)
-    np.testing.assert_array_equal(a_get1, master)
-    np.testing.assert_array_equal(a_get2, master)
-    np.testing.assert_array_equal(a_view1, master)
-    np.testing.assert_array_equal(a_view2, master)
-    np.testing.assert_array_equal(a_ref1, master)
-    np.testing.assert_array_equal(a_ref2, master)
-    np.testing.assert_array_equal(a_ref3, master)
-    np.testing.assert_array_equal(a_ref4, master)
-    np.testing.assert_array_equal(a_block1, master[3:5, 3:5])
-    np.testing.assert_array_equal(a_block2, master[2:5, 2:4])
-    np.testing.assert_array_equal(a_block3, master[6:10, 7:10])
+    np.testing.assert_array_equal(a_get1, primary)
+    np.testing.assert_array_equal(a_get2, primary)
+    np.testing.assert_array_equal(a_view1, primary)
+    np.testing.assert_array_equal(a_view2, primary)
+    np.testing.assert_array_equal(a_ref1, primary)
+    np.testing.assert_array_equal(a_ref2, primary)
+    np.testing.assert_array_equal(a_ref3, primary)
+    np.testing.assert_array_equal(a_ref4, primary)
+    np.testing.assert_array_equal(a_block1, primary[3:5, 3:5])
+    np.testing.assert_array_equal(a_block2, primary[2:5, 2:4])
+    np.testing.assert_array_equal(a_block3, primary[6:10, 7:10])
     np.testing.assert_array_equal(
-        a_corn1, master[0 :: master.shape[0] - 1, 0 :: master.shape[1] - 1]
+        a_corn1, primary[0 :: primary.shape[0] - 1, 0 :: primary.shape[1] - 1]
     )
     np.testing.assert_array_equal(
-        a_corn2, master[0 :: master.shape[0] - 1, 0 :: master.shape[1] - 1]
+        a_corn2, primary[0 :: primary.shape[0] - 1, 0 :: primary.shape[1] - 1]
     )
 
     np.testing.assert_array_equal(a_copy1, c1want)
@@ -723,13 +721,13 @@ def test_sparse_signature(doc):
         doc(m.sparse_copy_r)
         == """
         sparse_copy_r(arg0: scipy.sparse.csr_matrix[numpy.float32]) -> scipy.sparse.csr_matrix[numpy.float32]
-    """  # noqa: E501 line too long
+    """
     )
     assert (
         doc(m.sparse_copy_c)
         == """
         sparse_copy_c(arg0: scipy.sparse.csc_matrix[numpy.float32]) -> scipy.sparse.csc_matrix[numpy.float32]
-    """  # noqa: E501 line too long
+    """
     )
 
 
@@ -746,6 +744,13 @@ def test_issue738():
     )
 
 
+@pytest.mark.parametrize("func", [m.iss738_f1, m.iss738_f2])
+@pytest.mark.parametrize("sizes", [(0, 2), (2, 0)])
+def test_zero_length(func, sizes):
+    """Ignore strides on a length-0 dimension (even if they would be incompatible length > 1)"""
+    assert np.all(func(np.zeros(sizes)) == np.zeros(sizes))
+
+
 def test_issue1105():
     """Issue 1105: 1xN or Nx1 input arrays weren't accepted for eigen
     compile-time row vectors or column vector"""
diff --git a/3rdparty/pybind11/tests/test_embed/CMakeLists.txt b/3rdparty/pybind11/tests/test_embed/CMakeLists.txt
index fabcb24ea8..09a3693999 100644
--- a/3rdparty/pybind11/tests/test_embed/CMakeLists.txt
+++ b/3rdparty/pybind11/tests/test_embed/CMakeLists.txt
@@ -1,10 +1,13 @@
+possibly_uninitialized(PYTHON_MODULE_EXTENSION Python_INTERPRETER_ID)
+
 if("${PYTHON_MODULE_EXTENSION}" MATCHES "pypy" OR "${Python_INTERPRETER_ID}" STREQUAL "PyPy")
+  message(STATUS "Skipping embed test on PyPy")
   add_custom_target(cpptest) # Dummy target on PyPy. Embedding is not supported.
   set(_suppress_unused_variable_warning "${DOWNLOAD_CATCH}")
   return()
 endif()
 
-find_package(Catch 2.13.2)
+find_package(Catch 2.13.9)
 
 if(CATCH_FOUND)
   message(STATUS "Building interpreter tests using Catch v${CATCH_VERSION}")
@@ -22,12 +25,13 @@ pybind11_enable_warnings(test_embed)
 target_link_libraries(test_embed PRIVATE pybind11::embed Catch2::Catch2 Threads::Threads)
 
 if(NOT CMAKE_CURRENT_SOURCE_DIR STREQUAL CMAKE_CURRENT_BINARY_DIR)
-  file(COPY test_interpreter.py DESTINATION "${CMAKE_CURRENT_BINARY_DIR}")
+  file(COPY test_interpreter.py test_trampoline.py DESTINATION "${CMAKE_CURRENT_BINARY_DIR}")
 endif()
 
 add_custom_target(
   cpptest
   COMMAND "$<TARGET_FILE:test_embed>"
+  DEPENDS test_embed
   WORKING_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}")
 
 pybind11_add_module(external_module THIN_LTO external_module.cpp)
diff --git a/3rdparty/pybind11/tests/test_embed/catch.cpp b/3rdparty/pybind11/tests/test_embed/catch.cpp
index dd137385cb..a03a8b37c4 100644
--- a/3rdparty/pybind11/tests/test_embed/catch.cpp
+++ b/3rdparty/pybind11/tests/test_embed/catch.cpp
@@ -4,9 +4,14 @@
 #include <pybind11/embed.h>
 
 #ifdef _MSC_VER
-// Silence MSVC C++17 deprecation warning from Catch regarding std::uncaught_exceptions (up to catch
-// 2.0.1; this should be fixed in the next catch release after 2.0.1).
-#  pragma warning(disable: 4996)
+// Silence MSVC C++17 deprecation warning from Catch regarding std::uncaught_exceptions (up to
+// catch 2.0.1; this should be fixed in the next catch release after 2.0.1).
+#    pragma warning(disable : 4996)
+#endif
+
+// Catch uses _ internally, which breaks gettext style defines
+#ifdef _
+#    undef _
 #endif
 
 #define CATCH_CONFIG_RUNNER
@@ -15,7 +20,25 @@
 namespace py = pybind11;
 
 int main(int argc, char *argv[]) {
+    // Setup for TEST_CASE in test_interpreter.cpp, tagging on a large random number:
+    std::string updated_pythonpath("pybind11_test_embed_PYTHONPATH_2099743835476552");
+    const char *preexisting_pythonpath = getenv("PYTHONPATH");
+    if (preexisting_pythonpath != nullptr) {
+#if defined(_WIN32)
+        updated_pythonpath += ';';
+#else
+        updated_pythonpath += ':';
+#endif
+        updated_pythonpath += preexisting_pythonpath;
+    }
+#if defined(_WIN32)
+    _putenv_s("PYTHONPATH", updated_pythonpath.c_str());
+#else
+    setenv("PYTHONPATH", updated_pythonpath.c_str(), /*replace=*/1);
+#endif
+
     py::scoped_interpreter guard{};
+
     auto result = Catch::Session().run(argc, argv);
 
     return result < 0xff ? result : 0xff;
diff --git a/3rdparty/pybind11/tests/test_embed/external_module.cpp b/3rdparty/pybind11/tests/test_embed/external_module.cpp
index e9a6058b17..5c482fe061 100644
--- a/3rdparty/pybind11/tests/test_embed/external_module.cpp
+++ b/3rdparty/pybind11/tests/test_embed/external_module.cpp
@@ -9,15 +9,12 @@ namespace py = pybind11;
 PYBIND11_MODULE(external_module, m) {
     class A {
     public:
-        A(int value) : v{value} {};
+        explicit A(int value) : v{value} {};
         int v;
     };
 
-    py::class_<A>(m, "A")
-        .def(py::init<int>())
-        .def_readwrite("value", &A::v);
+    py::class_<A>(m, "A").def(py::init<int>()).def_readwrite("value", &A::v);
 
-    m.def("internals_at", []() {
-        return reinterpret_cast<uintptr_t>(&py::detail::get_internals());
-    });
+    m.def("internals_at",
+          []() { return reinterpret_cast<uintptr_t>(&py::detail::get_internals()); });
 }
diff --git a/3rdparty/pybind11/tests/test_embed/test_interpreter.cpp b/3rdparty/pybind11/tests/test_embed/test_interpreter.cpp
index 944334ce66..6299293b91 100644
--- a/3rdparty/pybind11/tests/test_embed/test_interpreter.cpp
+++ b/3rdparty/pybind11/tests/test_embed/test_interpreter.cpp
@@ -1,27 +1,29 @@
 #include <pybind11/embed.h>
 
 #ifdef _MSC_VER
-// Silence MSVC C++17 deprecation warning from Catch regarding std::uncaught_exceptions (up to catch
-// 2.0.1; this should be fixed in the next catch release after 2.0.1).
-#  pragma warning(disable: 4996)
+// Silence MSVC C++17 deprecation warning from Catch regarding std::uncaught_exceptions (up to
+// catch 2.0.1; this should be fixed in the next catch release after 2.0.1).
+#    pragma warning(disable : 4996)
 #endif
 
 #include <catch.hpp>
-
-#include <thread>
+#include <cstdlib>
 #include <fstream>
 #include <functional>
+#include <thread>
+#include <utility>
 
 namespace py = pybind11;
 using namespace py::literals;
 
 class Widget {
 public:
-    Widget(std::string message) : message(message) { }
+    explicit Widget(std::string message) : message(std::move(message)) {}
     virtual ~Widget() = default;
 
     std::string the_message() const { return message; }
     virtual int the_answer() const = 0;
+    virtual std::string argv0() const = 0;
 
 private:
     std::string message;
@@ -31,6 +33,23 @@ class PyWidget final : public Widget {
     using Widget::Widget;
 
     int the_answer() const override { PYBIND11_OVERRIDE_PURE(int, Widget, the_answer); }
+    std::string argv0() const override { PYBIND11_OVERRIDE_PURE(std::string, Widget, argv0); }
+};
+
+class test_override_cache_helper {
+
+public:
+    virtual int func() { return 0; }
+
+    test_override_cache_helper() = default;
+    virtual ~test_override_cache_helper() = default;
+    // Non-copyable
+    test_override_cache_helper &operator=(test_override_cache_helper const &Right) = delete;
+    test_override_cache_helper(test_override_cache_helper const &Copy) = delete;
+};
+
+class test_override_cache_helper_trampoline : public test_override_cache_helper {
+    int func() override { PYBIND11_OVERRIDE(int, test_override_cache_helper, func); }
 };
 
 PYBIND11_EMBEDDED_MODULE(widget_module, m) {
@@ -41,24 +60,39 @@ PYBIND11_EMBEDDED_MODULE(widget_module, m) {
     m.def("add", [](int i, int j) { return i + j; });
 }
 
-PYBIND11_EMBEDDED_MODULE(throw_exception, ) {
-    throw std::runtime_error("C++ Error");
+PYBIND11_EMBEDDED_MODULE(trampoline_module, m) {
+    py::class_<test_override_cache_helper,
+               test_override_cache_helper_trampoline,
+               std::shared_ptr<test_override_cache_helper>>(m, "test_override_cache_helper")
+        .def(py::init_alias<>())
+        .def("func", &test_override_cache_helper::func);
 }
 
+PYBIND11_EMBEDDED_MODULE(throw_exception, ) { throw std::runtime_error("C++ Error"); }
+
 PYBIND11_EMBEDDED_MODULE(throw_error_already_set, ) {
     auto d = py::dict();
     d["missing"].cast<py::object>();
 }
 
+TEST_CASE("PYTHONPATH is used to update sys.path") {
+    // The setup for this TEST_CASE is in catch.cpp!
+    auto sys_path = py::str(py::module_::import("sys").attr("path")).cast<std::string>();
+    REQUIRE_THAT(sys_path,
+                 Catch::Matchers::Contains("pybind11_test_embed_PYTHONPATH_2099743835476552"));
+}
+
 TEST_CASE("Pass classes and data between modules defined in C++ and Python") {
     auto module_ = py::module_::import("test_interpreter");
     REQUIRE(py::hasattr(module_, "DerivedWidget"));
 
-    auto locals = py::dict("hello"_a="Hello, World!", "x"_a=5, **module_.attr("__dict__"));
+    auto locals = py::dict("hello"_a = "Hello, World!", "x"_a = 5, **module_.attr("__dict__"));
     py::exec(R"(
         widget = DerivedWidget("{} - {}".format(hello, x))
         message = widget.the_message
-    )", py::globals(), locals);
+    )",
+             py::globals(),
+             locals);
     REQUIRE(locals["message"].cast<std::string>() == "Hello, World! - 5");
 
     auto py_widget = module_.attr("DerivedWidget")("The question");
@@ -69,12 +103,51 @@ TEST_CASE("Pass classes and data between modules defined in C++ and Python") {
     REQUIRE(cpp_widget.the_answer() == 42);
 }
 
+TEST_CASE("Override cache") {
+    auto module_ = py::module_::import("test_trampoline");
+    REQUIRE(py::hasattr(module_, "func"));
+    REQUIRE(py::hasattr(module_, "func2"));
+
+    auto locals = py::dict(**module_.attr("__dict__"));
+
+    int i = 0;
+    for (; i < 1500; ++i) {
+        std::shared_ptr<test_override_cache_helper> p_obj;
+        std::shared_ptr<test_override_cache_helper> p_obj2;
+
+        py::object loc_inst = locals["func"]();
+        p_obj = py::cast<std::shared_ptr<test_override_cache_helper>>(loc_inst);
+
+        int ret = p_obj->func();
+
+        REQUIRE(ret == 42);
+
+        loc_inst = locals["func2"]();
+
+        p_obj2 = py::cast<std::shared_ptr<test_override_cache_helper>>(loc_inst);
+
+        p_obj2->func();
+    }
+}
+
 TEST_CASE("Import error handling") {
     REQUIRE_NOTHROW(py::module_::import("widget_module"));
-    REQUIRE_THROWS_WITH(py::module_::import("throw_exception"),
-                        "ImportError: C++ Error");
+    REQUIRE_THROWS_WITH(py::module_::import("throw_exception"), "ImportError: C++ Error");
     REQUIRE_THROWS_WITH(py::module_::import("throw_error_already_set"),
-                        Catch::Contains("ImportError: KeyError"));
+                        Catch::Contains("ImportError: initialization failed"));
+
+    auto locals = py::dict("is_keyerror"_a = false, "message"_a = "not set");
+    py::exec(R"(
+        try:
+            import throw_error_already_set
+        except ImportError as e:
+            is_keyerror = type(e.__cause__) == KeyError
+            message = str(e.__cause__)
+    )",
+             py::globals(),
+             locals);
+    REQUIRE(locals["is_keyerror"].cast<bool>() == true);
+    REQUIRE(locals["message"].cast<std::string>() == "'missing'");
 }
 
 TEST_CASE("There can be only one interpreter") {
@@ -102,7 +175,7 @@ bool has_pybind11_internals_builtin() {
 
 bool has_pybind11_internals_static() {
     auto **&ipp = py::detail::get_internals_pp();
-    return ipp && *ipp;
+    return (ipp != nullptr) && (*ipp != nullptr);
 }
 
 TEST_CASE("Restart the interpreter") {
@@ -110,11 +183,12 @@ TEST_CASE("Restart the interpreter") {
     REQUIRE(py::module_::import("widget_module").attr("add")(1, 2).cast<int>() == 3);
     REQUIRE(has_pybind11_internals_builtin());
     REQUIRE(has_pybind11_internals_static());
-    REQUIRE(py::module_::import("external_module").attr("A")(123).attr("value").cast<int>() == 123);
+    REQUIRE(py::module_::import("external_module").attr("A")(123).attr("value").cast<int>()
+            == 123);
 
     // local and foreign module internals should point to the same internals:
-    REQUIRE(reinterpret_cast<uintptr_t>(*py::detail::get_internals_pp()) ==
-            py::module_::import("external_module").attr("internals_at")().cast<uintptr_t>());
+    REQUIRE(reinterpret_cast<uintptr_t>(*py::detail::get_internals_pp())
+            == py::module_::import("external_module").attr("internals_at")().cast<uintptr_t>());
 
     // Restart the interpreter.
     py::finalize_interpreter();
@@ -129,16 +203,19 @@ TEST_CASE("Restart the interpreter") {
     pybind11::detail::get_internals();
     REQUIRE(has_pybind11_internals_builtin());
     REQUIRE(has_pybind11_internals_static());
-    REQUIRE(reinterpret_cast<uintptr_t>(*py::detail::get_internals_pp()) ==
-            py::module_::import("external_module").attr("internals_at")().cast<uintptr_t>());
+    REQUIRE(reinterpret_cast<uintptr_t>(*py::detail::get_internals_pp())
+            == py::module_::import("external_module").attr("internals_at")().cast<uintptr_t>());
 
     // Make sure that an interpreter with no get_internals() created until finalize still gets the
     // internals destroyed
     py::finalize_interpreter();
     py::initialize_interpreter();
     bool ran = false;
-    py::module_::import("__main__").attr("internals_destroy_test") =
-        py::capsule(&ran, [](void *ran) { py::detail::get_internals(); *static_cast<bool *>(ran) = true; });
+    py::module_::import("__main__").attr("internals_destroy_test")
+        = py::capsule(&ran, [](void *ran) {
+              py::detail::get_internals();
+              *static_cast<bool *>(ran) = true;
+          });
     REQUIRE_FALSE(has_pybind11_internals_builtin());
     REQUIRE_FALSE(has_pybind11_internals_static());
     REQUIRE_FALSE(ran);
@@ -171,8 +248,8 @@ TEST_CASE("Subinterpreter") {
     REQUIRE(has_pybind11_internals_static());
 
     /// Create and switch to a subinterpreter.
-    auto main_tstate = PyThreadState_Get();
-    auto sub_tstate = Py_NewInterpreter();
+    auto *main_tstate = PyThreadState_Get();
+    auto *sub_tstate = Py_NewInterpreter();
 
     // Subinterpreters get their own copy of builtins. detail::get_internals() still
     // works by returning from the static variable, i.e. all interpreters share a single
@@ -212,7 +289,7 @@ TEST_CASE("Threads") {
     REQUIRE_FALSE(has_pybind11_internals_static());
 
     constexpr auto num_threads = 10;
-    auto locals = py::dict("count"_a=0);
+    auto locals = py::dict("count"_a = 0);
 
     {
         py::gil_scoped_release gil_release{};
@@ -238,7 +315,11 @@ TEST_CASE("Threads") {
 struct scope_exit {
     std::function<void()> f_;
     explicit scope_exit(std::function<void()> f) noexcept : f_(std::move(f)) {}
-    ~scope_exit() { if (f_) f_(); }
+    ~scope_exit() {
+        if (f_) {
+            f_();
+        }
+    }
 };
 
 TEST_CASE("Reload module from file") {
@@ -249,9 +330,8 @@ TEST_CASE("Reload module from file") {
     bool dont_write_bytecode = sys.attr("dont_write_bytecode").cast<bool>();
     sys.attr("dont_write_bytecode") = true;
     // Reset the value at scope exit
-    scope_exit reset_dont_write_bytecode([&]() {
-        sys.attr("dont_write_bytecode") = dont_write_bytecode;
-    });
+    scope_exit reset_dont_write_bytecode(
+        [&]() { sys.attr("dont_write_bytecode") = dont_write_bytecode; });
 
     std::string module_name = "test_module_reload";
     std::string module_file = module_name + ".py";
@@ -262,9 +342,7 @@ TEST_CASE("Reload module from file") {
     test_module << "    return 1\n";
     test_module.close();
     // Delete the file at scope exit
-    scope_exit delete_module_file([&]() {
-        std::remove(module_file.c_str());
-    });
+    scope_exit delete_module_file([&]() { std::remove(module_file.c_str()); });
 
     // Import the module from file
     auto module_ = py::module_::import(module_name.c_str());
@@ -282,3 +360,43 @@ TEST_CASE("Reload module from file") {
     result = module_.attr("test")().cast<int>();
     REQUIRE(result == 2);
 }
+
+TEST_CASE("sys.argv gets initialized properly") {
+    py::finalize_interpreter();
+    {
+        py::scoped_interpreter default_scope;
+        auto module = py::module::import("test_interpreter");
+        auto py_widget = module.attr("DerivedWidget")("The question");
+        const auto &cpp_widget = py_widget.cast<const Widget &>();
+        REQUIRE(cpp_widget.argv0().empty());
+    }
+
+    {
+        char *argv[] = {strdup("a.out")};
+        py::scoped_interpreter argv_scope(true, 1, argv);
+        std::free(argv[0]);
+        auto module = py::module::import("test_interpreter");
+        auto py_widget = module.attr("DerivedWidget")("The question");
+        const auto &cpp_widget = py_widget.cast<const Widget &>();
+        REQUIRE(cpp_widget.argv0() == "a.out");
+    }
+    py::initialize_interpreter();
+}
+
+TEST_CASE("make_iterator can be called before then after finalizing an interpreter") {
+    // Reproduction of issue #2101 (https://github.com/pybind/pybind11/issues/2101)
+    py::finalize_interpreter();
+
+    std::vector<int> container;
+    {
+        pybind11::scoped_interpreter g;
+        auto iter = pybind11::make_iterator(container.begin(), container.end());
+    }
+
+    REQUIRE_NOTHROW([&]() {
+        pybind11::scoped_interpreter g;
+        auto iter = pybind11::make_iterator(container.begin(), container.end());
+    }());
+
+    py::initialize_interpreter();
+}
diff --git a/3rdparty/pybind11/tests/test_embed/test_interpreter.py b/3rdparty/pybind11/tests/test_embed/test_interpreter.py
index 6174ede446..f279449722 100644
--- a/3rdparty/pybind11/tests/test_embed/test_interpreter.py
+++ b/3rdparty/pybind11/tests/test_embed/test_interpreter.py
@@ -1,10 +1,14 @@
-# -*- coding: utf-8 -*-
+import sys
+
 from widget_module import Widget
 
 
 class DerivedWidget(Widget):
     def __init__(self, message):
-        super(DerivedWidget, self).__init__(message)
+        super().__init__(message)
 
     def the_answer(self):
         return 42
+
+    def argv0(self):
+        return sys.argv[0]
diff --git a/3rdparty/pybind11/tests/test_embed/test_trampoline.py b/3rdparty/pybind11/tests/test_embed/test_trampoline.py
new file mode 100644
index 0000000000..8e14e8ef0b
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_embed/test_trampoline.py
@@ -0,0 +1,16 @@
+import trampoline_module
+
+
+def func():
+    class Test(trampoline_module.test_override_cache_helper):
+        def func(self):
+            return 42
+
+    return Test()
+
+
+def func2():
+    class Test(trampoline_module.test_override_cache_helper):
+        pass
+
+    return Test()
diff --git a/3rdparty/pybind11/tests/test_enum.cpp b/3rdparty/pybind11/tests/test_enum.cpp
index 3153089208..2597b275ef 100644
--- a/3rdparty/pybind11/tests/test_enum.cpp
+++ b/3rdparty/pybind11/tests/test_enum.cpp
@@ -11,11 +11,7 @@
 
 TEST_SUBMODULE(enums, m) {
     // test_unscoped_enum
-    enum UnscopedEnum {
-        EOne = 1,
-        ETwo,
-        EThree
-    };
+    enum UnscopedEnum { EOne = 1, ETwo, EThree };
     py::enum_<UnscopedEnum>(m, "UnscopedEnum", py::arithmetic(), "An unscoped enumeration")
         .value("EOne", EOne, "Docstring for EOne")
         .value("ETwo", ETwo, "Docstring for ETwo")
@@ -23,10 +19,7 @@ TEST_SUBMODULE(enums, m) {
         .export_values();
 
     // test_scoped_enum
-    enum class ScopedEnum {
-        Two = 2,
-        Three
-    };
+    enum class ScopedEnum { Two = 2, Three };
     py::enum_<ScopedEnum>(m, "ScopedEnum", py::arithmetic())
         .value("Two", ScopedEnum::Two)
         .value("Three", ScopedEnum::Three);
@@ -36,11 +29,7 @@ TEST_SUBMODULE(enums, m) {
     });
 
     // test_binary_operators
-    enum Flags {
-        Read = 4,
-        Write = 2,
-        Execute = 1
-    };
+    enum Flags { Read = 4, Write = 2, Execute = 1 };
     py::enum_<Flags>(m, "Flags", py::arithmetic())
         .value("Read", Flags::Read)
         .value("Write", Flags::Write)
@@ -50,14 +39,9 @@ TEST_SUBMODULE(enums, m) {
     // test_implicit_conversion
     class ClassWithUnscopedEnum {
     public:
-        enum EMode {
-            EFirstMode = 1,
-            ESecondMode
-        };
-
-        static EMode test_function(EMode mode) {
-            return mode;
-        }
+        enum EMode { EFirstMode = 1, ESecondMode };
+
+        static EMode test_function(EMode mode) { return mode; }
     };
     py::class_<ClassWithUnscopedEnum> exenum_class(m, "ClassWithUnscopedEnum");
     exenum_class.def_static("test_function", &ClassWithUnscopedEnum::test_function);
@@ -67,21 +51,83 @@ TEST_SUBMODULE(enums, m) {
         .export_values();
 
     // test_enum_to_int
-    m.def("test_enum_to_int", [](int) { });
-    m.def("test_enum_to_uint", [](uint32_t) { });
-    m.def("test_enum_to_long_long", [](long long) { });
+    m.def("test_enum_to_int", [](int) {});
+    m.def("test_enum_to_uint", [](uint32_t) {});
+    m.def("test_enum_to_long_long", [](long long) {});
 
     // test_duplicate_enum_name
-    enum SimpleEnum
-    {
-        ONE, TWO, THREE
-    };
+    enum SimpleEnum { ONE, TWO, THREE };
 
     m.def("register_bad_enum", [m]() {
         py::enum_<SimpleEnum>(m, "SimpleEnum")
-            .value("ONE", SimpleEnum::ONE)          //NOTE: all value function calls are called with the same first parameter value
+            .value("ONE", SimpleEnum::ONE) // NOTE: all value function calls are called with the
+                                           // same first parameter value
             .value("ONE", SimpleEnum::TWO)
             .value("ONE", SimpleEnum::THREE)
             .export_values();
     });
+
+    // test_enum_scalar
+    enum UnscopedUCharEnum : unsigned char {};
+    enum class ScopedShortEnum : short {};
+    enum class ScopedLongEnum : long {};
+    enum UnscopedUInt64Enum : std::uint64_t {};
+    static_assert(
+        py::detail::all_of<
+            std::is_same<py::enum_<UnscopedUCharEnum>::Scalar, unsigned char>,
+            std::is_same<py::enum_<ScopedShortEnum>::Scalar, short>,
+            std::is_same<py::enum_<ScopedLongEnum>::Scalar, long>,
+            std::is_same<py::enum_<UnscopedUInt64Enum>::Scalar, std::uint64_t>>::value,
+        "Error during the deduction of enum's scalar type with normal integer underlying");
+
+    // test_enum_scalar_with_char_underlying
+    enum class ScopedCharEnum : char { Zero, Positive };
+    enum class ScopedWCharEnum : wchar_t { Zero, Positive };
+    enum class ScopedChar32Enum : char32_t { Zero, Positive };
+    enum class ScopedChar16Enum : char16_t { Zero, Positive };
+
+    // test the scalar of char type enums according to chapter 'Character types'
+    // from https://en.cppreference.com/w/cpp/language/types
+    static_assert(
+        py::detail::any_of<
+            std::is_same<py::enum_<ScopedCharEnum>::Scalar, signed char>,  // e.g. gcc on x86
+            std::is_same<py::enum_<ScopedCharEnum>::Scalar, unsigned char> // e.g. arm linux
+            >::value,
+        "char should be cast to either signed char or unsigned char");
+    static_assert(sizeof(py::enum_<ScopedWCharEnum>::Scalar) == 2
+                      || sizeof(py::enum_<ScopedWCharEnum>::Scalar) == 4,
+                  "wchar_t should be either 16 bits (Windows) or 32 (everywhere else)");
+    static_assert(
+        py::detail::all_of<
+            std::is_same<py::enum_<ScopedChar32Enum>::Scalar, std::uint_least32_t>,
+            std::is_same<py::enum_<ScopedChar16Enum>::Scalar, std::uint_least16_t>>::value,
+        "char32_t, char16_t (and char8_t)'s size, signedness, and alignment is determined");
+#if defined(PYBIND11_HAS_U8STRING)
+    enum class ScopedChar8Enum : char8_t { Zero, Positive };
+    static_assert(std::is_same<py::enum_<ScopedChar8Enum>::Scalar, unsigned char>::value);
+#endif
+
+    // test_char_underlying_enum
+    py::enum_<ScopedCharEnum>(m, "ScopedCharEnum")
+        .value("Zero", ScopedCharEnum::Zero)
+        .value("Positive", ScopedCharEnum::Positive);
+    py::enum_<ScopedWCharEnum>(m, "ScopedWCharEnum")
+        .value("Zero", ScopedWCharEnum::Zero)
+        .value("Positive", ScopedWCharEnum::Positive);
+    py::enum_<ScopedChar32Enum>(m, "ScopedChar32Enum")
+        .value("Zero", ScopedChar32Enum::Zero)
+        .value("Positive", ScopedChar32Enum::Positive);
+    py::enum_<ScopedChar16Enum>(m, "ScopedChar16Enum")
+        .value("Zero", ScopedChar16Enum::Zero)
+        .value("Positive", ScopedChar16Enum::Positive);
+
+    // test_bool_underlying_enum
+    enum class ScopedBoolEnum : bool { FALSE, TRUE };
+
+    // bool is unsigned (std::is_signed returns false) and 1-byte long, so represented with u8
+    static_assert(std::is_same<py::enum_<ScopedBoolEnum>::Scalar, std::uint8_t>::value, "");
+
+    py::enum_<ScopedBoolEnum>(m, "ScopedBoolEnum")
+        .value("FALSE", ScopedBoolEnum::FALSE)
+        .value("TRUE", ScopedBoolEnum::TRUE);
 }
diff --git a/3rdparty/pybind11/tests/test_enum.py b/3rdparty/pybind11/tests/test_enum.py
index f6b24fc233..f14a72398f 100644
--- a/3rdparty/pybind11/tests/test_enum.py
+++ b/3rdparty/pybind11/tests/test_enum.py
@@ -1,5 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
+
 from pybind11_tests import enums as m
 
 
@@ -13,15 +13,24 @@ def test_unscoped_enum():
 
     # name property
     assert m.UnscopedEnum.EOne.name == "EOne"
+    assert m.UnscopedEnum.EOne.value == 1
     assert m.UnscopedEnum.ETwo.name == "ETwo"
-    assert m.EOne.name == "EOne"
-    # name readonly
+    assert m.UnscopedEnum.ETwo.value == 2
+    assert m.EOne is m.UnscopedEnum.EOne
+    # name, value readonly
     with pytest.raises(AttributeError):
         m.UnscopedEnum.EOne.name = ""
-    # name returns a copy
-    foo = m.UnscopedEnum.EOne.name
-    foo = "bar"
+    with pytest.raises(AttributeError):
+        m.UnscopedEnum.EOne.value = 10
+    # name, value returns a copy
+    # TODO: Neither the name nor value tests actually check against aliasing.
+    # Use a mutable type that has reference semantics.
+    nonaliased_name = m.UnscopedEnum.EOne.name
+    nonaliased_name = "bar"  # noqa: F841
     assert m.UnscopedEnum.EOne.name == "EOne"
+    nonaliased_value = m.UnscopedEnum.EOne.value
+    nonaliased_value = 10  # noqa: F841
+    assert m.UnscopedEnum.EOne.value == 1
 
     # __members__ property
     assert m.UnscopedEnum.__members__ == {
@@ -33,8 +42,8 @@ def test_unscoped_enum():
     with pytest.raises(AttributeError):
         m.UnscopedEnum.__members__ = {}
     # __members__ returns a copy
-    foo = m.UnscopedEnum.__members__
-    foo["bar"] = "baz"
+    nonaliased_members = m.UnscopedEnum.__members__
+    nonaliased_members["bar"] = "baz"
     assert m.UnscopedEnum.__members__ == {
         "EOne": m.UnscopedEnum.EOne,
         "ETwo": m.UnscopedEnum.ETwo,
@@ -73,16 +82,16 @@ def test_unscoped_enum():
     assert not (y == "2")
 
     with pytest.raises(TypeError):
-        y < object()
+        y < object()  # noqa: B015
 
     with pytest.raises(TypeError):
-        y <= object()
+        y <= object()  # noqa: B015
 
     with pytest.raises(TypeError):
-        y > object()
+        y > object()  # noqa: B015
 
     with pytest.raises(TypeError):
-        y >= object()
+        y >= object()  # noqa: B015
 
     with pytest.raises(TypeError):
         y | object()
@@ -134,13 +143,13 @@ def test_scoped_enum():
     assert not (z == object())
     # Scoped enums will *NOT* accept >, <, >= and <= int comparisons (Will throw exceptions)
     with pytest.raises(TypeError):
-        z > 3
+        z > 3  # noqa: B015
     with pytest.raises(TypeError):
-        z < 3
+        z < 3  # noqa: B015
     with pytest.raises(TypeError):
-        z >= 3
+        z >= 3  # noqa: B015
     with pytest.raises(TypeError):
-        z <= 3
+        z <= 3  # noqa: B015
 
     # order
     assert m.ScopedEnum.Two < m.ScopedEnum.Three
@@ -208,10 +217,16 @@ def test_binary_operators():
 def test_enum_to_int():
     m.test_enum_to_int(m.Flags.Read)
     m.test_enum_to_int(m.ClassWithUnscopedEnum.EMode.EFirstMode)
+    m.test_enum_to_int(m.ScopedCharEnum.Positive)
+    m.test_enum_to_int(m.ScopedBoolEnum.TRUE)
     m.test_enum_to_uint(m.Flags.Read)
     m.test_enum_to_uint(m.ClassWithUnscopedEnum.EMode.EFirstMode)
+    m.test_enum_to_uint(m.ScopedCharEnum.Positive)
+    m.test_enum_to_uint(m.ScopedBoolEnum.TRUE)
     m.test_enum_to_long_long(m.Flags.Read)
     m.test_enum_to_long_long(m.ClassWithUnscopedEnum.EMode.EFirstMode)
+    m.test_enum_to_long_long(m.ScopedCharEnum.Positive)
+    m.test_enum_to_long_long(m.ScopedBoolEnum.TRUE)
 
 
 def test_duplicate_enum_name():
@@ -220,6 +235,28 @@ def test_duplicate_enum_name():
     assert str(excinfo.value) == 'SimpleEnum: element "ONE" already exists!'
 
 
+def test_char_underlying_enum():  # Issue #1331/PR #1334:
+    assert type(m.ScopedCharEnum.Positive.__int__()) is int
+    assert int(m.ScopedChar16Enum.Zero) == 0
+    assert hash(m.ScopedChar32Enum.Positive) == 1
+    assert type(m.ScopedCharEnum.Positive.__getstate__()) is int
+    assert m.ScopedWCharEnum(1) == m.ScopedWCharEnum.Positive
+    with pytest.raises(TypeError):
+        # Even if the underlying type is char, only an int can be used to construct the enum:
+        m.ScopedCharEnum("0")
+
+
+def test_bool_underlying_enum():
+    assert type(m.ScopedBoolEnum.TRUE.__int__()) is int
+    assert int(m.ScopedBoolEnum.FALSE) == 0
+    assert hash(m.ScopedBoolEnum.TRUE) == 1
+    assert type(m.ScopedBoolEnum.TRUE.__getstate__()) is int
+    assert m.ScopedBoolEnum(1) == m.ScopedBoolEnum.TRUE
+    # Enum could construct with a bool
+    # (bool is a strict subclass of int, and False will be converted to 0)
+    assert m.ScopedBoolEnum(False) == m.ScopedBoolEnum.FALSE
+
+
 def test_docstring_signatures():
     for enum_type in [m.ScopedEnum, m.UnscopedEnum]:
         for attr in enum_type.__dict__.values():
diff --git a/3rdparty/pybind11/tests/test_eval.cpp b/3rdparty/pybind11/tests/test_eval.cpp
index 5416c2ec4d..cd2903f0ab 100644
--- a/3rdparty/pybind11/tests/test_eval.cpp
+++ b/3rdparty/pybind11/tests/test_eval.cpp
@@ -7,10 +7,12 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-
 #include <pybind11/eval.h>
+
 #include "pybind11_tests.h"
 
+#include <utility>
+
 TEST_SUBMODULE(eval_, m) {
     // test_evals
 
@@ -18,16 +20,13 @@ TEST_SUBMODULE(eval_, m) {
 
     m.def("test_eval_statements", [global]() {
         auto local = py::dict();
-        local["call_test"] = py::cpp_function([&]() -> int {
-            return 42;
-        });
+        local["call_test"] = py::cpp_function([&]() -> int { return 42; });
 
         // Regular string literal
-        py::exec(
-            "message = 'Hello World!'\n"
-            "x = call_test()",
-            global, local
-        );
+        py::exec("message = 'Hello World!'\n"
+                 "x = call_test()",
+                 global,
+                 local);
 
         // Multi-line raw string literal
         py::exec(R"(
@@ -35,8 +34,9 @@ TEST_SUBMODULE(eval_, m) {
                 print(message)
             else:
                 raise RuntimeError
-            )", global, local
-        );
+            )",
+                 global,
+                 local);
         auto x = local["x"].cast<int>();
 
         return x == 42;
@@ -51,9 +51,7 @@ TEST_SUBMODULE(eval_, m) {
 
     m.def("test_eval_single_statement", []() {
         auto local = py::dict();
-        local["call_test"] = py::cpp_function([&]() -> int {
-            return 42;
-        });
+        local["call_test"] = py::cpp_function([&]() -> int { return 42; });
 
         auto result = py::eval<py::eval_single_statement>("x = call_test()", py::dict(), local);
         auto x = local["x"].cast<int>();
@@ -64,10 +62,10 @@ TEST_SUBMODULE(eval_, m) {
         auto local = py::dict();
         local["y"] = py::int_(43);
 
-        int val_out;
+        int val_out = 0;
         local["call_test2"] = py::cpp_function([&](int value) { val_out = value; });
 
-        auto result = py::eval_file(filename, global, local);
+        auto result = py::eval_file(std::move(filename), global, local);
         return val_out == 43 && result.is_none();
     });
 
@@ -91,9 +89,30 @@ TEST_SUBMODULE(eval_, m) {
 
     // test_eval_empty_globals
     m.def("eval_empty_globals", [](py::object global) {
-        if (global.is_none())
+        if (global.is_none()) {
             global = py::dict();
+        }
         auto int_class = py::eval("isinstance(42, int)", global);
         return global;
     });
+
+    // test_eval_closure
+    m.def("test_eval_closure", []() {
+        py::dict global;
+        global["closure_value"] = 42;
+        py::dict local;
+        local["closure_value"] = 0;
+        py::exec(R"(
+            local_value = closure_value
+
+            def func_global():
+                return closure_value
+
+            def func_local():
+                return local_value
+            )",
+                 global,
+                 local);
+        return std::make_pair(global, local);
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_eval.py b/3rdparty/pybind11/tests/test_eval.py
index 1bb05af05e..51b6b796b4 100644
--- a/3rdparty/pybind11/tests/test_eval.py
+++ b/3rdparty/pybind11/tests/test_eval.py
@@ -1,10 +1,8 @@
-# -*- coding: utf-8 -*-
 import os
 
 import pytest
 
 import env  # noqa: F401
-
 from pybind11_tests import eval_ as m
 
 
@@ -19,7 +17,7 @@ def test_evals(capture):
     assert m.test_eval_failure()
 
 
-@pytest.mark.xfail("env.PYPY and not env.PY2", raises=RuntimeError)
+@pytest.mark.xfail("env.PYPY", raises=RuntimeError)
 def test_eval_file():
     filename = os.path.join(os.path.dirname(__file__), "test_eval_call.py")
     assert m.test_eval_file(filename)
@@ -33,3 +31,20 @@ def test_eval_empty_globals():
     g = {}
     assert "__builtins__" in m.eval_empty_globals(g)
     assert "__builtins__" in g
+
+
+def test_eval_closure():
+    global_, local = m.test_eval_closure()
+
+    assert global_["closure_value"] == 42
+    assert local["closure_value"] == 0
+
+    assert "local_value" not in global_
+    assert local["local_value"] == 0
+
+    assert "func_global" not in global_
+    assert local["func_global"]() == 42
+
+    assert "func_local" not in global_
+    with pytest.raises(NameError):
+        local["func_local"]()
diff --git a/3rdparty/pybind11/tests/test_eval_call.py b/3rdparty/pybind11/tests/test_eval_call.py
index 373b67bac8..fd1da2a5cc 100644
--- a/3rdparty/pybind11/tests/test_eval_call.py
+++ b/3rdparty/pybind11/tests/test_eval_call.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 # This file is called from 'test_eval.py'
 
 if "call_test2" in locals():
diff --git a/3rdparty/pybind11/tests/test_exceptions.cpp b/3rdparty/pybind11/tests/test_exceptions.cpp
index e27c16dfef..3583f22a50 100644
--- a/3rdparty/pybind11/tests/test_exceptions.cpp
+++ b/3rdparty/pybind11/tests/test_exceptions.cpp
@@ -6,14 +6,21 @@
     All rights reserved. Use of this source code is governed by a
     BSD-style license that can be found in the LICENSE file.
 */
+#include "test_exceptions.h"
 
+#include "local_bindings.h"
 #include "pybind11_tests.h"
 
+#include <exception>
+#include <stdexcept>
+#include <utility>
+
 // A type that should be raised as an exception in Python
 class MyException : public std::exception {
 public:
-    explicit MyException(const char * m) : message{m} {}
-    const char * what() const noexcept override {return message.c_str();}
+    explicit MyException(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
 private:
     std::string message = "";
 };
@@ -21,8 +28,9 @@ class MyException : public std::exception {
 // A type that should be translated to a standard Python exception
 class MyException2 : public std::exception {
 public:
-    explicit MyException2(const char * m) : message{m} {}
-    const char * what() const noexcept override {return message.c_str();}
+    explicit MyException2(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
 private:
     std::string message = "";
 };
@@ -30,13 +38,13 @@ class MyException2 : public std::exception {
 // A type that is not derived from std::exception (and is thus unknown)
 class MyException3 {
 public:
-    explicit MyException3(const char * m) : message{m} {}
-    virtual const char * what() const noexcept {return message.c_str();}
+    explicit MyException3(const char *m) : message{m} {}
+    virtual const char *what() const noexcept { return message.c_str(); }
     // Rule of 5 BEGIN: to preempt compiler warnings.
-    MyException3(const MyException3&) = default;
-    MyException3(MyException3&&) = default;
-    MyException3& operator=(const MyException3&) = default;
-    MyException3& operator=(MyException3&&) = default;
+    MyException3(const MyException3 &) = default;
+    MyException3(MyException3 &&) = default;
+    MyException3 &operator=(const MyException3 &) = default;
+    MyException3 &operator=(MyException3 &&) = default;
     virtual ~MyException3() = default;
     // Rule of 5 END.
 private:
@@ -47,13 +55,13 @@ class MyException3 {
 // and delegated to its exception translator
 class MyException4 : public std::exception {
 public:
-    explicit MyException4(const char * m) : message{m} {}
-    const char * what() const noexcept override {return message.c_str();}
+    explicit MyException4(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
 private:
     std::string message = "";
 };
 
-
 // Like the above, but declared via the helper function
 class MyException5 : public std::logic_error {
 public:
@@ -65,24 +73,31 @@ class MyException5_1 : public MyException5 {
     using MyException5::MyException5;
 };
 
+// Exception that will be caught via the module local translator.
+class MyException6 : public std::exception {
+public:
+    explicit MyException6(const char *m) : message{m} {}
+    const char *what() const noexcept override { return message.c_str(); }
+
+private:
+    std::string message = "";
+};
+
 struct PythonCallInDestructor {
-    PythonCallInDestructor(const py::dict &d) : d(d) {}
+    explicit PythonCallInDestructor(const py::dict &d) : d(d) {}
     ~PythonCallInDestructor() { d["good"] = true; }
 
     py::dict d;
 };
 
-
-
 struct PythonAlreadySetInDestructor {
-    PythonAlreadySetInDestructor(const py::str &s) : s(s) {}
+    explicit PythonAlreadySetInDestructor(const py::str &s) : s(s) {}
     ~PythonAlreadySetInDestructor() {
         py::dict foo;
         try {
             // Assign to a py::object to force read access of nonexistent dict entry
             py::object o = foo["bar"];
-        }
-        catch (py::error_already_set& ex) {
+        } catch (py::error_already_set &ex) {
             ex.discard_as_unraisable(s);
         }
     }
@@ -90,17 +105,22 @@ struct PythonAlreadySetInDestructor {
     py::str s;
 };
 
+std::string error_already_set_what(const py::object &exc_type, const py::object &exc_value) {
+    PyErr_SetObject(exc_type.ptr(), exc_value.ptr());
+    return py::error_already_set().what();
+}
 
 TEST_SUBMODULE(exceptions, m) {
-    m.def("throw_std_exception", []() {
-        throw std::runtime_error("This exception was intentionally thrown.");
-    });
+    m.def("throw_std_exception",
+          []() { throw std::runtime_error("This exception was intentionally thrown."); });
 
     // make a new custom exception and use it as a translation target
     static py::exception<MyException> ex(m, "MyException");
     py::register_exception_translator([](std::exception_ptr p) {
         try {
-            if (p) std::rethrow_exception(p);
+            if (p) {
+                std::rethrow_exception(p);
+            }
         } catch (const MyException &e) {
             // Set MyException as the active python error
             ex(e.what());
@@ -112,7 +132,9 @@ TEST_SUBMODULE(exceptions, m) {
     // never by visible from Python
     py::register_exception_translator([](std::exception_ptr p) {
         try {
-            if (p) std::rethrow_exception(p);
+            if (p) {
+                std::rethrow_exception(p);
+            }
         } catch (const MyException2 &e) {
             // Translate this exception to a standard RuntimeError
             PyErr_SetString(PyExc_RuntimeError, e.what());
@@ -124,7 +146,9 @@ TEST_SUBMODULE(exceptions, m) {
     // translator for MyException by throwing a new exception
     py::register_exception_translator([](std::exception_ptr p) {
         try {
-            if (p) std::rethrow_exception(p);
+            if (p) {
+                std::rethrow_exception(p);
+            }
         } catch (const MyException4 &e) {
             throw MyException(e.what());
         }
@@ -135,22 +159,42 @@ TEST_SUBMODULE(exceptions, m) {
     // A slightly more complicated one that declares MyException5_1 as a subclass of MyException5
     py::register_exception<MyException5_1>(m, "MyException5_1", ex5.ptr());
 
+    // py::register_local_exception<LocalSimpleException>(m, "LocalSimpleException")
+
+    py::register_local_exception_translator([](std::exception_ptr p) {
+        try {
+            if (p) {
+                std::rethrow_exception(p);
+            }
+        } catch (const MyException6 &e) {
+            PyErr_SetString(PyExc_RuntimeError, e.what());
+        }
+    });
+
     m.def("throws1", []() { throw MyException("this error should go to a custom type"); });
-    m.def("throws2", []() { throw MyException2("this error should go to a standard Python exception"); });
+    m.def("throws2",
+          []() { throw MyException2("this error should go to a standard Python exception"); });
     m.def("throws3", []() { throw MyException3("this error cannot be translated"); });
     m.def("throws4", []() { throw MyException4("this error is rethrown"); });
-    m.def("throws5", []() { throw MyException5("this is a helper-defined translated exception"); });
+    m.def("throws5",
+          []() { throw MyException5("this is a helper-defined translated exception"); });
     m.def("throws5_1", []() { throw MyException5_1("MyException5 subclass"); });
-    m.def("throws_logic_error", []() { throw std::logic_error("this error should fall through to the standard handler"); });
-    m.def("throws_overflow_error", []() {throw std::overflow_error(""); });
+    m.def("throws6", []() { throw MyException6("MyException6 only handled in this module"); });
+    m.def("throws_logic_error", []() {
+        throw std::logic_error("this error should fall through to the standard handler");
+    });
+    m.def("throws_overflow_error", []() { throw std::overflow_error(""); });
+    m.def("throws_local_error", []() { throw LocalException("never caught"); });
+    m.def("throws_local_simple_error", []() { throw LocalSimpleException("this mod"); });
     m.def("exception_matches", []() {
         py::dict foo;
         try {
             // Assign to a py::object to force read access of nonexistent dict entry
             py::object o = foo["bar"];
-        }
-        catch (py::error_already_set& ex) {
-            if (!ex.matches(PyExc_KeyError)) throw;
+        } catch (py::error_already_set &ex) {
+            if (!ex.matches(PyExc_KeyError)) {
+                throw;
+            }
             return true;
         }
         return false;
@@ -160,9 +204,10 @@ TEST_SUBMODULE(exceptions, m) {
         try {
             // Assign to a py::object to force read access of nonexistent dict entry
             py::object o = foo["bar"];
-        }
-        catch (py::error_already_set &ex) {
-            if (!ex.matches(PyExc_Exception)) throw;
+        } catch (py::error_already_set &ex) {
+            if (!ex.matches(PyExc_Exception)) {
+                throw;
+            }
             return true;
         }
         return false;
@@ -171,61 +216,132 @@ TEST_SUBMODULE(exceptions, m) {
         try {
             // On Python >= 3.6, this raises a ModuleNotFoundError, a subclass of ImportError
             py::module_::import("nonexistent");
-        }
-        catch (py::error_already_set &ex) {
-            if (!ex.matches(PyExc_ImportError)) throw;
+        } catch (py::error_already_set &ex) {
+            if (!ex.matches(PyExc_ImportError)) {
+                throw;
+            }
             return true;
         }
         return false;
     });
 
     m.def("throw_already_set", [](bool err) {
-        if (err)
+        if (err) {
             PyErr_SetString(PyExc_ValueError, "foo");
+        }
         try {
             throw py::error_already_set();
-        } catch (const std::runtime_error& e) {
-            if ((err && e.what() != std::string("ValueError: foo")) ||
-                (!err && e.what() != std::string("Unknown internal error occurred")))
-            {
+        } catch (const std::runtime_error &e) {
+            if ((err && e.what() != std::string("ValueError: foo"))
+                || (!err
+                    && e.what()
+                           != std::string("Internal error: pybind11::error_already_set called "
+                                          "while Python error indicator not set."))) {
                 PyErr_Clear();
                 throw std::runtime_error("error message mismatch");
             }
         }
         PyErr_Clear();
-        if (err)
+        if (err) {
             PyErr_SetString(PyExc_ValueError, "foo");
+        }
         throw py::error_already_set();
     });
 
-    m.def("python_call_in_destructor", [](py::dict d) {
+    m.def("python_call_in_destructor", [](const py::dict &d) {
+        bool retval = false;
         try {
             PythonCallInDestructor set_dict_in_destructor(d);
             PyErr_SetString(PyExc_ValueError, "foo");
             throw py::error_already_set();
-        } catch (const py::error_already_set&) {
-            return true;
+        } catch (const py::error_already_set &) {
+            retval = true;
         }
-        return false;
+        return retval;
     });
 
-    m.def("python_alreadyset_in_destructor", [](py::str s) {
+    m.def("python_alreadyset_in_destructor", [](const py::str &s) {
         PythonAlreadySetInDestructor alreadyset_in_destructor(s);
         return true;
     });
 
     // test_nested_throws
-    m.def("try_catch", [m](py::object exc_type, py::function f, py::args args) {
-        try { f(*args); }
-        catch (py::error_already_set &ex) {
-            if (ex.matches(exc_type))
-                py::print(ex.what());
-            else
-                throw;
+    m.def("try_catch",
+          [m](const py::object &exc_type, const py::function &f, const py::args &args) {
+              try {
+                  f(*args);
+              } catch (py::error_already_set &ex) {
+                  if (ex.matches(exc_type)) {
+                      py::print(ex.what());
+                  } else {
+                      // Simply `throw;` also works and is better, but using `throw ex;`
+                      // here to cover that situation (as observed in the wild).
+                      throw ex; // Invokes the copy ctor.
+                  }
+              }
+          });
+
+    // Test repr that cannot be displayed
+    m.def("simple_bool_passthrough", [](bool x) { return x; });
+
+    m.def("throw_should_be_translated_to_key_error", []() { throw shared_exception(); });
+
+    m.def("raise_from", []() {
+        PyErr_SetString(PyExc_ValueError, "inner");
+        py::raise_from(PyExc_ValueError, "outer");
+        throw py::error_already_set();
+    });
+
+    m.def("raise_from_already_set", []() {
+        try {
+            PyErr_SetString(PyExc_ValueError, "inner");
+            throw py::error_already_set();
+        } catch (py::error_already_set &e) {
+            py::raise_from(e, PyExc_ValueError, "outer");
+            throw py::error_already_set();
         }
     });
 
-    // Test repr that cannot be displayed
-    m.def("simple_bool_passthrough", [](bool x) {return x;});
+    m.def("throw_nested_exception", []() {
+        try {
+            throw std::runtime_error("Inner Exception");
+        } catch (const std::runtime_error &) {
+            std::throw_with_nested(std::runtime_error("Outer Exception"));
+        }
+    });
+
+    m.def("error_already_set_what", [](const py::object &exc_type, const py::object &exc_value) {
+        PyErr_SetObject(exc_type.ptr(), exc_value.ptr());
+        std::string what = py::error_already_set().what();
+        bool py_err_set_after_what = (PyErr_Occurred() != nullptr);
+        PyErr_Clear();
+        return py::make_tuple(std::move(what), py_err_set_after_what);
+    });
+
+    m.def("test_cross_module_interleaved_error_already_set", []() {
+        auto cm = py::module_::import("cross_module_interleaved_error_already_set");
+        auto interleaved_error_already_set
+            = reinterpret_cast<void (*)()>(PyLong_AsVoidPtr(cm.attr("funcaddr").ptr()));
+        interleaved_error_already_set();
+    });
+
+    m.def("test_error_already_set_double_restore", [](bool dry_run) {
+        PyErr_SetString(PyExc_ValueError, "Random error.");
+        py::error_already_set e;
+        e.restore();
+        PyErr_Clear();
+        if (!dry_run) {
+            e.restore();
+        }
+    });
 
+    // https://github.com/pybind/pybind11/issues/4075
+    m.def("test_pypy_oserror_normalization", []() {
+        try {
+            py::module_::import("io").attr("open")("this_filename_must_not_exist", "r");
+        } catch (const py::error_already_set &e) {
+            return py::str(e.what()); // str must be built before e goes out of scope.
+        }
+        return py::str("UNEXPECTED");
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_exceptions.h b/3rdparty/pybind11/tests/test_exceptions.h
new file mode 100644
index 0000000000..03684b89fa
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_exceptions.h
@@ -0,0 +1,13 @@
+#pragma once
+#include "pybind11_tests.h"
+
+#include <stdexcept>
+
+// shared exceptions for cross_module_tests
+
+class PYBIND11_EXPORT_EXCEPTION shared_exception : public pybind11::builtin_exception {
+public:
+    using builtin_exception::builtin_exception;
+    explicit shared_exception() : shared_exception("") {}
+    void set_error() const override { PyErr_SetString(PyExc_RuntimeError, what()); }
+};
diff --git a/3rdparty/pybind11/tests/test_exceptions.py b/3rdparty/pybind11/tests/test_exceptions.py
index 95eac70928..70b6ffea95 100644
--- a/3rdparty/pybind11/tests/test_exceptions.py
+++ b/3rdparty/pybind11/tests/test_exceptions.py
@@ -1,10 +1,10 @@
-# -*- coding: utf-8 -*-
 import sys
 
 import pytest
 
-from pybind11_tests import exceptions as m
+import env
 import pybind11_cross_module_tests as cm
+from pybind11_tests import exceptions as m
 
 
 def test_std_exception(msg):
@@ -16,14 +16,31 @@ def test_std_exception(msg):
 def test_error_already_set(msg):
     with pytest.raises(RuntimeError) as excinfo:
         m.throw_already_set(False)
-    assert msg(excinfo.value) == "Unknown internal error occurred"
+    assert (
+        msg(excinfo.value)
+        == "Internal error: pybind11::error_already_set called while Python error indicator not set."
+    )
 
     with pytest.raises(ValueError) as excinfo:
         m.throw_already_set(True)
     assert msg(excinfo.value) == "foo"
 
 
-def test_cross_module_exceptions():
+def test_raise_from(msg):
+    with pytest.raises(ValueError) as excinfo:
+        m.raise_from()
+    assert msg(excinfo.value) == "outer"
+    assert msg(excinfo.value.__cause__) == "inner"
+
+
+def test_raise_from_already_set(msg):
+    with pytest.raises(ValueError) as excinfo:
+        m.raise_from_already_set()
+    assert msg(excinfo.value) == "outer"
+    assert msg(excinfo.value.__cause__) == "inner"
+
+
+def test_cross_module_exceptions(msg):
     with pytest.raises(RuntimeError) as excinfo:
         cm.raise_runtime_error()
     assert str(excinfo.value) == "My runtime error"
@@ -43,6 +60,27 @@ def test_cross_module_exceptions():
     with pytest.raises(StopIteration) as excinfo:
         cm.throw_stop_iteration()
 
+    with pytest.raises(cm.LocalSimpleException) as excinfo:
+        cm.throw_local_simple_error()
+    assert msg(excinfo.value) == "external mod"
+
+    with pytest.raises(KeyError) as excinfo:
+        cm.throw_local_error()
+    # KeyError is a repr of the key, so it has an extra set of quotes
+    assert str(excinfo.value) == "'just local'"
+
+
+# TODO: FIXME
+@pytest.mark.xfail(
+    "env.PYPY and env.MACOS",
+    raises=RuntimeError,
+    reason="Expected failure with PyPy and libc++ (Issue #2847 & PR #2999)",
+)
+def test_cross_module_exception_translator():
+    with pytest.raises(KeyError):
+        # translator registered in cross_module_tests
+        m.throw_should_be_translated_to_key_error()
+
 
 def test_python_call_in_catch():
     d = {}
@@ -50,18 +88,32 @@ def test_python_call_in_catch():
     assert d["good"] is True
 
 
+def ignore_pytest_unraisable_warning(f):
+    unraisable = "PytestUnraisableExceptionWarning"
+    if hasattr(pytest, unraisable):  # Python >= 3.8 and pytest >= 6
+        dec = pytest.mark.filterwarnings(f"ignore::pytest.{unraisable}")
+        return dec(f)
+    else:
+        return f
+
+
+# TODO: find out why this fails on PyPy, https://foss.heptapod.net/pypy/pypy/-/issues/3583
+@pytest.mark.xfail(env.PYPY, reason="Failure on PyPy 3.8 (7.3.7)", strict=False)
+@ignore_pytest_unraisable_warning
 def test_python_alreadyset_in_destructor(monkeypatch, capsys):
     hooked = False
-    triggered = [False]  # mutable, so Python 2.7 closure can modify it
+    triggered = False
 
     if hasattr(sys, "unraisablehook"):  # Python 3.8+
         hooked = True
-        default_hook = sys.unraisablehook
+        # Don't take `sys.unraisablehook`, as that's overwritten by pytest
+        default_hook = sys.__unraisablehook__
 
         def hook(unraisable_hook_args):
             exc_type, exc_value, exc_tb, err_msg, obj = unraisable_hook_args
             if obj == "already_set demo":
-                triggered[0] = True
+                nonlocal triggered
+                triggered = True
             default_hook(unraisable_hook_args)
             return
 
@@ -70,11 +122,11 @@ def hook(unraisable_hook_args):
 
     assert m.python_alreadyset_in_destructor("already_set demo") is True
     if hooked:
-        assert triggered[0] is True
+        assert triggered is True
 
     _, captured_stderr = capsys.readouterr()
-    # Error message is different in Python 2 and 3, check for words that appear in both
-    assert "ignored" in captured_stderr and "already_set demo" in captured_stderr
+    assert captured_stderr.startswith("Exception ignored in: 'already_set demo'")
+    assert captured_stderr.rstrip().endswith("KeyError: 'bar'")
 
 
 def test_exception_matches():
@@ -133,8 +185,8 @@ def test_custom(msg):
     with pytest.raises(m.MyException5) as excinfo:
         try:
             m.throws5()
-        except m.MyException5_1:
-            raise RuntimeError("Exception error: caught child from parent")
+        except m.MyException5_1 as err:
+            raise RuntimeError("Exception error: caught child from parent") from err
     assert msg(excinfo.value) == "this is a helper-defined translated exception"
 
 
@@ -188,11 +240,129 @@ def pycatch(exctype, f, *args):
     assert str(excinfo.value) == "this is a helper-defined translated exception"
 
 
+def test_throw_nested_exception():
+    with pytest.raises(RuntimeError) as excinfo:
+        m.throw_nested_exception()
+    assert str(excinfo.value) == "Outer Exception"
+    assert str(excinfo.value.__cause__) == "Inner Exception"
+
+
 # This can often happen if you wrap a pybind11 class in a Python wrapper
 def test_invalid_repr():
-    class MyRepr(object):
+    class MyRepr:
         def __repr__(self):
             raise AttributeError("Example error")
 
     with pytest.raises(TypeError):
         m.simple_bool_passthrough(MyRepr())
+
+
+def test_local_translator(msg):
+    """Tests that a local translator works and that the local translator from
+    the cross module is not applied"""
+    with pytest.raises(RuntimeError) as excinfo:
+        m.throws6()
+    assert msg(excinfo.value) == "MyException6 only handled in this module"
+
+    with pytest.raises(RuntimeError) as excinfo:
+        m.throws_local_error()
+    assert not isinstance(excinfo.value, KeyError)
+    assert msg(excinfo.value) == "never caught"
+
+    with pytest.raises(Exception) as excinfo:
+        m.throws_local_simple_error()
+    assert not isinstance(excinfo.value, cm.LocalSimpleException)
+    assert msg(excinfo.value) == "this mod"
+
+
+class FlakyException(Exception):
+    def __init__(self, failure_point):
+        if failure_point == "failure_point_init":
+            raise ValueError("triggered_failure_point_init")
+        self.failure_point = failure_point
+
+    def __str__(self):
+        if self.failure_point == "failure_point_str":
+            raise ValueError("triggered_failure_point_str")
+        return "FlakyException.__str__"
+
+
+@pytest.mark.parametrize(
+    "exc_type, exc_value, expected_what",
+    (
+        (ValueError, "plain_str", "ValueError: plain_str"),
+        (ValueError, ("tuple_elem",), "ValueError: tuple_elem"),
+        (FlakyException, ("happy",), "FlakyException: FlakyException.__str__"),
+    ),
+)
+def test_error_already_set_what_with_happy_exceptions(
+    exc_type, exc_value, expected_what
+):
+    what, py_err_set_after_what = m.error_already_set_what(exc_type, exc_value)
+    assert not py_err_set_after_what
+    assert what == expected_what
+
+
+@pytest.mark.skipif("env.PYPY", reason="PyErr_NormalizeException Segmentation fault")
+def test_flaky_exception_failure_point_init():
+    with pytest.raises(RuntimeError) as excinfo:
+        m.error_already_set_what(FlakyException, ("failure_point_init",))
+    lines = str(excinfo.value).splitlines()
+    # PyErr_NormalizeException replaces the original FlakyException with ValueError:
+    assert lines[:3] == [
+        "pybind11::error_already_set: MISMATCH of original and normalized active exception types:"
+        " ORIGINAL FlakyException REPLACED BY ValueError: triggered_failure_point_init",
+        "",
+        "At:",
+    ]
+    # Checking the first two lines of the traceback as formatted in error_string():
+    assert "test_exceptions.py(" in lines[3]
+    assert lines[3].endswith("): __init__")
+    assert lines[4].endswith("): test_flaky_exception_failure_point_init")
+
+
+def test_flaky_exception_failure_point_str():
+    what, py_err_set_after_what = m.error_already_set_what(
+        FlakyException, ("failure_point_str",)
+    )
+    assert not py_err_set_after_what
+    lines = what.splitlines()
+    if env.PYPY and len(lines) == 3:
+        n = 3  # Traceback is missing.
+    else:
+        n = 5
+    assert (
+        lines[:n]
+        == [
+            "FlakyException: <MESSAGE UNAVAILABLE DUE TO ANOTHER EXCEPTION>",
+            "",
+            "MESSAGE UNAVAILABLE DUE TO EXCEPTION: ValueError: triggered_failure_point_str",
+            "",
+            "At:",
+        ][:n]
+    )
+
+
+def test_cross_module_interleaved_error_already_set():
+    with pytest.raises(RuntimeError) as excinfo:
+        m.test_cross_module_interleaved_error_already_set()
+    assert str(excinfo.value) in (
+        "2nd error.",  # Almost all platforms.
+        "RuntimeError: 2nd error.",  # Some PyPy builds (seen under macOS).
+    )
+
+
+def test_error_already_set_double_restore():
+    m.test_error_already_set_double_restore(True)  # dry_run
+    with pytest.raises(RuntimeError) as excinfo:
+        m.test_error_already_set_double_restore(False)
+    assert str(excinfo.value) == (
+        "Internal error: pybind11::detail::error_fetch_and_normalize::restore()"
+        " called a second time. ORIGINAL ERROR: ValueError: Random error."
+    )
+
+
+def test_pypy_oserror_normalization():
+    # https://github.com/pybind/pybind11/issues/4075
+    what = m.test_pypy_oserror_normalization()
+    assert "this_filename_must_not_exist" in what
diff --git a/3rdparty/pybind11/tests/test_factory_constructors.cpp b/3rdparty/pybind11/tests/test_factory_constructors.cpp
index f42d1f29b9..a387cd2e76 100644
--- a/3rdparty/pybind11/tests/test_factory_constructors.cpp
+++ b/3rdparty/pybind11/tests/test_factory_constructors.cpp
@@ -8,35 +8,45 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 #include <cmath>
 #include <new>
+#include <utility>
 
 // Classes for testing python construction via C++ factory function:
 // Not publicly constructible, copyable, or movable:
 class TestFactory1 {
     friend class TestFactoryHelper;
     TestFactory1() : value("(empty)") { print_default_created(this); }
-    TestFactory1(int v) : value(std::to_string(v)) { print_created(this, value); }
-    TestFactory1(std::string v) : value(std::move(v)) { print_created(this, value); }
+    explicit TestFactory1(int v) : value(std::to_string(v)) { print_created(this, value); }
+    explicit TestFactory1(std::string v) : value(std::move(v)) { print_created(this, value); }
+
+public:
+    std::string value;
     TestFactory1(TestFactory1 &&) = delete;
     TestFactory1(const TestFactory1 &) = delete;
     TestFactory1 &operator=(TestFactory1 &&) = delete;
     TestFactory1 &operator=(const TestFactory1 &) = delete;
-public:
-    std::string value;
     ~TestFactory1() { print_destroyed(this); }
 };
 // Non-public construction, but moveable:
 class TestFactory2 {
     friend class TestFactoryHelper;
     TestFactory2() : value("(empty2)") { print_default_created(this); }
-    TestFactory2(int v) : value(std::to_string(v)) { print_created(this, value); }
-    TestFactory2(std::string v) : value(std::move(v)) { print_created(this, value); }
+    explicit TestFactory2(int v) : value(std::to_string(v)) { print_created(this, value); }
+    explicit TestFactory2(std::string v) : value(std::move(v)) { print_created(this, value); }
+
 public:
-    TestFactory2(TestFactory2 &&m) { value = std::move(m.value); print_move_created(this); }
-    TestFactory2 &operator=(TestFactory2 &&m) { value = std::move(m.value); print_move_assigned(this); return *this; }
+    TestFactory2(TestFactory2 &&m) noexcept : value{std::move(m.value)} {
+        print_move_created(this);
+    }
+    TestFactory2 &operator=(TestFactory2 &&m) noexcept {
+        value = std::move(m.value);
+        print_move_assigned(this);
+        return *this;
+    }
     std::string value;
     ~TestFactory2() { print_destroyed(this); }
 };
@@ -45,11 +55,18 @@ class TestFactory3 {
 protected:
     friend class TestFactoryHelper;
     TestFactory3() : value("(empty3)") { print_default_created(this); }
-    TestFactory3(int v) : value(std::to_string(v)) { print_created(this, value); }
+    explicit TestFactory3(int v) : value(std::to_string(v)) { print_created(this, value); }
+
 public:
-    TestFactory3(std::string v) : value(std::move(v)) { print_created(this, value); }
-    TestFactory3(TestFactory3 &&m) { value = std::move(m.value); print_move_created(this); }
-    TestFactory3 &operator=(TestFactory3 &&m) { value = std::move(m.value); print_move_assigned(this); return *this; }
+    explicit TestFactory3(std::string v) : value(std::move(v)) { print_created(this, value); }
+    TestFactory3(TestFactory3 &&m) noexcept : value{std::move(m.value)} {
+        print_move_created(this);
+    }
+    TestFactory3 &operator=(TestFactory3 &&m) noexcept {
+        value = std::move(m.value);
+        print_move_assigned(this);
+        return *this;
+    }
     std::string value;
     virtual ~TestFactory3() { print_destroyed(this); }
 };
@@ -57,13 +74,13 @@ class TestFactory3 {
 class TestFactory4 : public TestFactory3 {
 public:
     TestFactory4() : TestFactory3() { print_default_created(this); }
-    TestFactory4(int v) : TestFactory3(v) { print_created(this, v); }
+    explicit TestFactory4(int v) : TestFactory3(v) { print_created(this, v); }
     ~TestFactory4() override { print_destroyed(this); }
 };
 // Another class for an invalid downcast test
 class TestFactory5 : public TestFactory3 {
 public:
-    TestFactory5(int i) : TestFactory3(i) { print_created(this, i); }
+    explicit TestFactory5(int i) : TestFactory3(i) { print_created(this, i); }
     ~TestFactory5() override { print_destroyed(this); }
 };
 
@@ -71,23 +88,45 @@ class TestFactory6 {
 protected:
     int value;
     bool alias = false;
+
 public:
-    TestFactory6(int i) : value{i} { print_created(this, i); }
-    TestFactory6(TestFactory6 &&f) { print_move_created(this); value = f.value; alias = f.alias; }
-    TestFactory6(const TestFactory6 &f) { print_copy_created(this); value = f.value; alias = f.alias; }
+    explicit TestFactory6(int i) : value{i} { print_created(this, i); }
+    TestFactory6(TestFactory6 &&f) noexcept {
+        print_move_created(this);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = f.value;
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        alias = f.alias;
+    }
+    TestFactory6(const TestFactory6 &f) {
+        print_copy_created(this);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = f.value;
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        alias = f.alias;
+    }
     virtual ~TestFactory6() { print_destroyed(this); }
     virtual int get() { return value; }
-    bool has_alias() { return alias; }
+    bool has_alias() const { return alias; }
 };
 class PyTF6 : public TestFactory6 {
 public:
     // Special constructor that allows the factory to construct a PyTF6 from a TestFactory6 only
     // when an alias is needed:
-    PyTF6(TestFactory6 &&base) : TestFactory6(std::move(base)) { alias = true; print_created(this, "move", value); }
-    PyTF6(int i) : TestFactory6(i) { alias = true; print_created(this, i); }
-    PyTF6(PyTF6 &&f) : TestFactory6(std::move(f)) { print_move_created(this); }
+    explicit PyTF6(TestFactory6 &&base) : TestFactory6(std::move(base)) {
+        alias = true;
+        print_created(this, "move", value);
+    }
+    explicit PyTF6(int i) : TestFactory6(i) {
+        alias = true;
+        print_created(this, i);
+    }
+    PyTF6(PyTF6 &&f) noexcept : TestFactory6(std::move(f)) { print_move_created(this); }
     PyTF6(const PyTF6 &f) : TestFactory6(f) { print_copy_created(this); }
-    PyTF6(std::string s) : TestFactory6((int) s.size()) { alias = true; print_created(this, s); }
+    explicit PyTF6(std::string s) : TestFactory6((int) s.size()) {
+        alias = true;
+        print_created(this, s);
+    }
     ~PyTF6() override { print_destroyed(this); }
     int get() override { PYBIND11_OVERRIDE(int, TestFactory6, get, /*no args*/); }
 };
@@ -96,56 +135,80 @@ class TestFactory7 {
 protected:
     int value;
     bool alias = false;
+
 public:
-    TestFactory7(int i) : value{i} { print_created(this, i); }
-    TestFactory7(TestFactory7 &&f) { print_move_created(this); value = f.value; alias = f.alias; }
-    TestFactory7(const TestFactory7 &f) { print_copy_created(this); value = f.value; alias = f.alias; }
+    explicit TestFactory7(int i) : value{i} { print_created(this, i); }
+    TestFactory7(TestFactory7 &&f) noexcept {
+        print_move_created(this);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = f.value;
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        alias = f.alias;
+    }
+    TestFactory7(const TestFactory7 &f) {
+        print_copy_created(this);
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        value = f.value;
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        alias = f.alias;
+    }
     virtual ~TestFactory7() { print_destroyed(this); }
     virtual int get() { return value; }
-    bool has_alias() { return alias; }
+    bool has_alias() const { return alias; }
 };
 class PyTF7 : public TestFactory7 {
 public:
-    PyTF7(int i) : TestFactory7(i) { alias = true; print_created(this, i); }
-    PyTF7(PyTF7 &&f) : TestFactory7(std::move(f)) { print_move_created(this); }
+    explicit PyTF7(int i) : TestFactory7(i) {
+        // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
+        alias = true;
+        print_created(this, i);
+    }
+    PyTF7(PyTF7 &&f) noexcept : TestFactory7(std::move(f)) { print_move_created(this); }
     PyTF7(const PyTF7 &f) : TestFactory7(f) { print_copy_created(this); }
     ~PyTF7() override { print_destroyed(this); }
     int get() override { PYBIND11_OVERRIDE(int, TestFactory7, get, /*no args*/); }
 };
 
-
 class TestFactoryHelper {
 public:
     // Non-movable, non-copyable type:
     // Return via pointer:
     static TestFactory1 *construct1() { return new TestFactory1(); }
     // Holder:
-    static std::unique_ptr<TestFactory1> construct1(int a) { return std::unique_ptr<TestFactory1>(new TestFactory1(a)); }
+    static std::unique_ptr<TestFactory1> construct1(int a) {
+        return std::unique_ptr<TestFactory1>(new TestFactory1(a));
+    }
     // pointer again
-    static TestFactory1 *construct1_string(std::string a) { return new TestFactory1(a); }
+    static TestFactory1 *construct1_string(std::string a) {
+        return new TestFactory1(std::move(a));
+    }
 
     // Moveable type:
     // pointer:
     static TestFactory2 *construct2() { return new TestFactory2(); }
     // holder:
-    static std::unique_ptr<TestFactory2> construct2(int a) { return std::unique_ptr<TestFactory2>(new TestFactory2(a)); }
+    static std::unique_ptr<TestFactory2> construct2(int a) {
+        return std::unique_ptr<TestFactory2>(new TestFactory2(a));
+    }
     // by value moving:
-    static TestFactory2 construct2(std::string a) { return TestFactory2(a); }
+    static TestFactory2 construct2(std::string a) { return TestFactory2(std::move(a)); }
 
     // shared_ptr holder type:
     // pointer:
     static TestFactory3 *construct3() { return new TestFactory3(); }
     // holder:
-    static std::shared_ptr<TestFactory3> construct3(int a) { return std::shared_ptr<TestFactory3>(new TestFactory3(a)); }
+    static std::shared_ptr<TestFactory3> construct3(int a) {
+        return std::shared_ptr<TestFactory3>(new TestFactory3(a));
+    }
 };
 
 TEST_SUBMODULE(factory_constructors, m) {
 
     // Define various trivial types to allow simpler overload resolution:
     py::module_ m_tag = m.def_submodule("tag");
-#define MAKE_TAG_TYPE(Name) \
-    struct Name##_tag {}; \
-    py::class_<Name##_tag>(m_tag, #Name "_tag").def(py::init<>()); \
+#define MAKE_TAG_TYPE(Name)                                                                       \
+    struct Name##_tag {};                                                                         \
+    py::class_<Name##_tag>(m_tag, #Name "_tag").def(py::init<>());                                \
     m_tag.attr(#Name) = py::cast(Name##_tag{})
     MAKE_TAG_TYPE(pointer);
     MAKE_TAG_TYPE(unique_ptr);
@@ -168,40 +231,50 @@ TEST_SUBMODULE(factory_constructors, m) {
         .def(py::init([](unique_ptr_tag, int v) { return TestFactoryHelper::construct1(v); }))
         .def(py::init(&TestFactoryHelper::construct1_string)) // raw function pointer
         .def(py::init([](pointer_tag) { return TestFactoryHelper::construct1(); }))
-        .def(py::init([](py::handle, int v, py::handle) { return TestFactoryHelper::construct1(v); }))
-        .def_readwrite("value", &TestFactory1::value)
-        ;
+        .def(py::init(
+            [](py::handle, int v, py::handle) { return TestFactoryHelper::construct1(v); }))
+        .def_readwrite("value", &TestFactory1::value);
     py::class_<TestFactory2>(m, "TestFactory2")
         .def(py::init([](pointer_tag, int v) { return TestFactoryHelper::construct2(v); }))
-        .def(py::init([](unique_ptr_tag, std::string v) { return TestFactoryHelper::construct2(v); }))
+        .def(py::init([](unique_ptr_tag, std::string v) {
+            return TestFactoryHelper::construct2(std::move(v));
+        }))
         .def(py::init([](move_tag) { return TestFactoryHelper::construct2(); }))
-        .def_readwrite("value", &TestFactory2::value)
-        ;
+        .def_readwrite("value", &TestFactory2::value);
 
     // Stateful & reused:
     int c = 1;
-    auto c4a = [c](pointer_tag, TF4_tag, int a) { (void) c; return new TestFactory4(a);};
+    auto c4a = [c](pointer_tag, TF4_tag, int a) {
+        (void) c;
+        return new TestFactory4(a);
+    };
 
     // test_init_factory_basic, test_init_factory_casting
-    py::class_<TestFactory3, std::shared_ptr<TestFactory3>>(m, "TestFactory3")
+    py::class_<TestFactory3, std::shared_ptr<TestFactory3>> pyTestFactory3(m, "TestFactory3");
+    pyTestFactory3
         .def(py::init([](pointer_tag, int v) { return TestFactoryHelper::construct3(v); }))
-        .def(py::init([](shared_ptr_tag) { return TestFactoryHelper::construct3(); }))
-        .def("__init__", [](TestFactory3 &self, std::string v) { new (&self) TestFactory3(v); }) // placement-new ctor
-
+        .def(py::init([](shared_ptr_tag) { return TestFactoryHelper::construct3(); }));
+    ignoreOldStyleInitWarnings([&pyTestFactory3]() {
+        pyTestFactory3.def("__init__", [](TestFactory3 &self, std::string v) {
+            new (&self) TestFactory3(std::move(v));
+        }); // placement-new ctor
+    });
+    pyTestFactory3
         // factories returning a derived type:
         .def(py::init(c4a)) // derived ptr
         .def(py::init([](pointer_tag, TF5_tag, int a) { return new TestFactory5(a); }))
         // derived shared ptr:
-        .def(py::init([](shared_ptr_tag, TF4_tag, int a) { return std::make_shared<TestFactory4>(a); }))
-        .def(py::init([](shared_ptr_tag, TF5_tag, int a) { return std::make_shared<TestFactory5>(a); }))
+        .def(py::init(
+            [](shared_ptr_tag, TF4_tag, int a) { return std::make_shared<TestFactory4>(a); }))
+        .def(py::init(
+            [](shared_ptr_tag, TF5_tag, int a) { return std::make_shared<TestFactory5>(a); }))
 
         // Returns nullptr:
         .def(py::init([](null_ptr_tag) { return (TestFactory3 *) nullptr; }))
         .def(py::init([](null_unique_ptr_tag) { return std::unique_ptr<TestFactory3>(); }))
         .def(py::init([](null_shared_ptr_tag) { return std::shared_ptr<TestFactory3>(); }))
 
-        .def_readwrite("value", &TestFactory3::value)
-        ;
+        .def_readwrite("value", &TestFactory3::value);
 
     // test_init_factory_casting
     py::class_<TestFactory4, TestFactory3, std::shared_ptr<TestFactory4>>(m, "TestFactory4")
@@ -216,58 +289,60 @@ TEST_SUBMODULE(factory_constructors, m) {
     py::class_<TestFactory6, PyTF6>(m, "TestFactory6")
         .def(py::init([](base_tag, int i) { return TestFactory6(i); }))
         .def(py::init([](alias_tag, int i) { return PyTF6(i); }))
-        .def(py::init([](alias_tag, std::string s) { return PyTF6(s); }))
+        .def(py::init([](alias_tag, std::string s) { return PyTF6(std::move(s)); }))
         .def(py::init([](alias_tag, pointer_tag, int i) { return new PyTF6(i); }))
         .def(py::init([](base_tag, pointer_tag, int i) { return new TestFactory6(i); }))
-        .def(py::init([](base_tag, alias_tag, pointer_tag, int i) { return (TestFactory6 *) new PyTF6(i); }))
+        .def(py::init(
+            [](base_tag, alias_tag, pointer_tag, int i) { return (TestFactory6 *) new PyTF6(i); }))
 
         .def("get", &TestFactory6::get)
         .def("has_alias", &TestFactory6::has_alias)
 
-        .def_static("get_cstats", &ConstructorStats::get<TestFactory6>, py::return_value_policy::reference)
-        .def_static("get_alias_cstats", &ConstructorStats::get<PyTF6>, py::return_value_policy::reference)
-        ;
+        .def_static(
+            "get_cstats", &ConstructorStats::get<TestFactory6>, py::return_value_policy::reference)
+        .def_static(
+            "get_alias_cstats", &ConstructorStats::get<PyTF6>, py::return_value_policy::reference);
 
     // test_init_factory_dual
     // Separate alias constructor testing
     py::class_<TestFactory7, PyTF7, std::shared_ptr<TestFactory7>>(m, "TestFactory7")
-        .def(py::init(
-            [](int i) { return TestFactory7(i); },
-            [](int i) { return PyTF7(i); }))
-        .def(py::init(
-            [](pointer_tag, int i) { return new TestFactory7(i); },
-            [](pointer_tag, int i) { return new PyTF7(i); }))
-        .def(py::init(
-            [](mixed_tag, int i) { return new TestFactory7(i); },
-            [](mixed_tag, int i) { return PyTF7(i); }))
-        .def(py::init(
-            [](mixed_tag, std::string s) { return TestFactory7((int) s.size()); },
-            [](mixed_tag, std::string s) { return new PyTF7((int) s.size()); }))
-        .def(py::init(
-            [](base_tag, pointer_tag, int i) { return new TestFactory7(i); },
-            [](base_tag, pointer_tag, int i) { return (TestFactory7 *) new PyTF7(i); }))
-        .def(py::init(
-            [](alias_tag, pointer_tag, int i) { return new PyTF7(i); },
-            [](alias_tag, pointer_tag, int i) { return new PyTF7(10*i); }))
+        .def(py::init([](int i) { return TestFactory7(i); }, [](int i) { return PyTF7(i); }))
+        .def(py::init([](pointer_tag, int i) { return new TestFactory7(i); },
+                      [](pointer_tag, int i) { return new PyTF7(i); }))
+        .def(py::init([](mixed_tag, int i) { return new TestFactory7(i); },
+                      [](mixed_tag, int i) { return PyTF7(i); }))
+        .def(py::init([](mixed_tag, const std::string &s) { return TestFactory7((int) s.size()); },
+                      [](mixed_tag, const std::string &s) { return new PyTF7((int) s.size()); }))
+        .def(py::init([](base_tag, pointer_tag, int i) { return new TestFactory7(i); },
+                      [](base_tag, pointer_tag, int i) { return (TestFactory7 *) new PyTF7(i); }))
+        .def(py::init([](alias_tag, pointer_tag, int i) { return new PyTF7(i); },
+                      [](alias_tag, pointer_tag, int i) { return new PyTF7(10 * i); }))
         .def(py::init(
             [](shared_ptr_tag, base_tag, int i) { return std::make_shared<TestFactory7>(i); },
-            [](shared_ptr_tag, base_tag, int i) { auto *p = new PyTF7(i); return std::shared_ptr<TestFactory7>(p); }))
-        .def(py::init(
-            [](shared_ptr_tag, invalid_base_tag, int i) { return std::make_shared<TestFactory7>(i); },
-            [](shared_ptr_tag, invalid_base_tag, int i) { return std::make_shared<TestFactory7>(i); })) // <-- invalid alias factory
+            [](shared_ptr_tag, base_tag, int i) {
+                auto *p = new PyTF7(i);
+                return std::shared_ptr<TestFactory7>(p);
+            }))
+        .def(py::init([](shared_ptr_tag,
+                         invalid_base_tag,
+                         int i) { return std::make_shared<TestFactory7>(i); },
+                      [](shared_ptr_tag, invalid_base_tag, int i) {
+                          return std::make_shared<TestFactory7>(i);
+                      })) // <-- invalid alias factory
 
         .def("get", &TestFactory7::get)
         .def("has_alias", &TestFactory7::has_alias)
 
-        .def_static("get_cstats", &ConstructorStats::get<TestFactory7>, py::return_value_policy::reference)
-        .def_static("get_alias_cstats", &ConstructorStats::get<PyTF7>, py::return_value_policy::reference)
-        ;
+        .def_static(
+            "get_cstats", &ConstructorStats::get<TestFactory7>, py::return_value_policy::reference)
+        .def_static(
+            "get_alias_cstats", &ConstructorStats::get<PyTF7>, py::return_value_policy::reference);
 
     // test_placement_new_alternative
     // Class with a custom new operator but *without* a placement new operator (issue #948)
     class NoPlacementNew {
     public:
-        NoPlacementNew(int i) : i(i) { }
+        explicit NoPlacementNew(int i) : i(i) {}
         static void *operator new(std::size_t s) {
             auto *p = ::operator new(s);
             py::print("operator new called, returning", reinterpret_cast<uintptr_t>(p));
@@ -283,50 +358,62 @@ TEST_SUBMODULE(factory_constructors, m) {
     py::class_<NoPlacementNew>(m, "NoPlacementNew")
         .def(py::init<int>())
         .def(py::init([]() { return new NoPlacementNew(100); }))
-        .def_readwrite("i", &NoPlacementNew::i)
-        ;
-
+        .def_readwrite("i", &NoPlacementNew::i);
 
     // test_reallocations
     // Class that has verbose operator_new/operator_delete calls
     struct NoisyAlloc {
         NoisyAlloc(const NoisyAlloc &) = default;
-        NoisyAlloc(int i) { py::print(py::str("NoisyAlloc(int {})").format(i)); }
-        NoisyAlloc(double d) { py::print(py::str("NoisyAlloc(double {})").format(d)); }
+        explicit NoisyAlloc(int i) { py::print(py::str("NoisyAlloc(int {})").format(i)); }
+        explicit NoisyAlloc(double d) { py::print(py::str("NoisyAlloc(double {})").format(d)); }
         ~NoisyAlloc() { py::print("~NoisyAlloc()"); }
 
-        static void *operator new(size_t s) { py::print("noisy new"); return ::operator new(s); }
-        static void *operator new(size_t, void *p) { py::print("noisy placement new"); return p; }
-        static void operator delete(void *p, size_t) { py::print("noisy delete"); ::operator delete(p); }
+        static void *operator new(size_t s) {
+            py::print("noisy new");
+            return ::operator new(s);
+        }
+        static void *operator new(size_t, void *p) {
+            py::print("noisy placement new");
+            return p;
+        }
+        static void operator delete(void *p, size_t) {
+            py::print("noisy delete");
+            ::operator delete(p);
+        }
         static void operator delete(void *, void *) { py::print("noisy placement delete"); }
-#if defined(_MSC_VER) && _MSC_VER < 1910
-        // MSVC 2015 bug: the above "noisy delete" isn't invoked (fixed in MSVC 2017)
-        static void operator delete(void *p) { py::print("noisy delete"); ::operator delete(p); }
-#endif
     };
-    py::class_<NoisyAlloc>(m, "NoisyAlloc")
-        // Since these overloads have the same number of arguments, the dispatcher will try each of
-        // them until the arguments convert.  Thus we can get a pre-allocation here when passing a
-        // single non-integer:
-        .def("__init__", [](NoisyAlloc *a, int i) { new (a) NoisyAlloc(i); }) // Regular constructor, runs first, requires preallocation
-        .def(py::init([](double d) { return new NoisyAlloc(d); }))
-
-        // The two-argument version: first the factory pointer overload.
-        .def(py::init([](int i, int) { return new NoisyAlloc(i); }))
-        // Return-by-value:
-        .def(py::init([](double d, int) { return NoisyAlloc(d); }))
-        // Old-style placement new init; requires preallocation
-        .def("__init__", [](NoisyAlloc &a, double d, double) { new (&a) NoisyAlloc(d); })
-        // Requires deallocation of previous overload preallocated value:
-        .def(py::init([](int i, double) { return new NoisyAlloc(i); }))
-        // Regular again: requires yet another preallocation
-        .def("__init__", [](NoisyAlloc &a, int i, std::string) { new (&a) NoisyAlloc(i); })
-        ;
-
-
-
 
-    // static_assert testing (the following def's should all fail with appropriate compilation errors):
+    py::class_<NoisyAlloc> pyNoisyAlloc(m, "NoisyAlloc");
+    // Since these overloads have the same number of arguments, the dispatcher will try each of
+    // them until the arguments convert.  Thus we can get a pre-allocation here when passing a
+    // single non-integer:
+    ignoreOldStyleInitWarnings([&pyNoisyAlloc]() {
+        pyNoisyAlloc.def("__init__", [](NoisyAlloc *a, int i) {
+            new (a) NoisyAlloc(i);
+        }); // Regular constructor, runs first, requires preallocation
+    });
+
+    pyNoisyAlloc.def(py::init([](double d) { return new NoisyAlloc(d); }));
+
+    // The two-argument version: first the factory pointer overload.
+    pyNoisyAlloc.def(py::init([](int i, int) { return new NoisyAlloc(i); }));
+    // Return-by-value:
+    pyNoisyAlloc.def(py::init([](double d, int) { return NoisyAlloc(d); }));
+    // Old-style placement new init; requires preallocation
+    ignoreOldStyleInitWarnings([&pyNoisyAlloc]() {
+        pyNoisyAlloc.def("__init__",
+                         [](NoisyAlloc &a, double d, double) { new (&a) NoisyAlloc(d); });
+    });
+    // Requires deallocation of previous overload preallocated value:
+    pyNoisyAlloc.def(py::init([](int i, double) { return new NoisyAlloc(i); }));
+    // Regular again: requires yet another preallocation
+    ignoreOldStyleInitWarnings([&pyNoisyAlloc]() {
+        pyNoisyAlloc.def(
+            "__init__", [](NoisyAlloc &a, int i, const std::string &) { new (&a) NoisyAlloc(i); });
+    });
+
+    // static_assert testing (the following def's should all fail with appropriate compilation
+    // errors):
 #if 0
     struct BadF1Base {};
     struct BadF1 : BadF1Base {};
diff --git a/3rdparty/pybind11/tests/test_factory_constructors.py b/3rdparty/pybind11/tests/test_factory_constructors.py
index ffcce6fd4d..120a587c45 100644
--- a/3rdparty/pybind11/tests/test_factory_constructors.py
+++ b/3rdparty/pybind11/tests/test_factory_constructors.py
@@ -1,12 +1,10 @@
-# -*- coding: utf-8 -*-
-import pytest
 import re
 
-import env  # noqa: F401
+import pytest
 
+from pybind11_tests import ConstructorStats
 from pybind11_tests import factory_constructors as m
 from pybind11_tests.factory_constructors import tag
-from pybind11_tests import ConstructorStats
 
 
 def test_init_factory_basic():
@@ -82,7 +80,7 @@ def test_init_factory_signature(msg):
             4. m.factory_constructors.TestFactory1(arg0: handle, arg1: int, arg2: handle)
 
         Invoked with: 'invalid', 'constructor', 'arguments'
-    """  # noqa: E501 line too long
+    """
     )
 
     assert (
@@ -465,12 +463,10 @@ def test_reallocation_g(capture, msg):
     )
 
 
-@pytest.mark.skipif("env.PY2")
 def test_invalid_self():
-    """Tests invocation of the pybind-registered base class with an invalid `self` argument.  You
-    can only actually do this on Python 3: Python 2 raises an exception itself if you try."""
+    """Tests invocation of the pybind-registered base class with an invalid `self` argument."""
 
-    class NotPybindDerived(object):
+    class NotPybindDerived:
         pass
 
     # Attempts to initialize with an invalid type passed as `self`:
@@ -486,7 +482,9 @@ def __init__(self, bad):
     # Same as above, but for a class with an alias:
     class BrokenTF6(m.TestFactory6):
         def __init__(self, bad):
-            if bad == 1:
+            if bad == 0:
+                m.TestFactory6.__init__()
+            elif bad == 1:
                 a = m.TestFactory2(tag.pointer, 1)
                 m.TestFactory6.__init__(a, tag.base, 1)
             elif bad == 2:
@@ -506,13 +504,13 @@ def __init__(self, bad):
             BrokenTF1(arg)
         assert (
             str(excinfo.value)
-            == "__init__(self, ...) called with invalid `self` argument"
+            == "__init__(self, ...) called with invalid or missing `self` argument"
         )
 
-    for arg in (1, 2, 3, 4):
+    for arg in (0, 1, 2, 3, 4):
         with pytest.raises(TypeError) as excinfo:
             BrokenTF6(arg)
         assert (
             str(excinfo.value)
-            == "__init__(self, ...) called with invalid `self` argument"
+            == "__init__(self, ...) called with invalid or missing `self` argument"
         )
diff --git a/3rdparty/pybind11/tests/test_gil_scoped.cpp b/3rdparty/pybind11/tests/test_gil_scoped.cpp
index b6a45a5f03..97efdc1616 100644
--- a/3rdparty/pybind11/tests/test_gil_scoped.cpp
+++ b/3rdparty/pybind11/tests/test_gil_scoped.cpp
@@ -7,48 +7,41 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/functional.h>
 
+#include "pybind11_tests.h"
 
-class VirtClass  {
+class VirtClass {
 public:
     virtual ~VirtClass() = default;
     VirtClass() = default;
-    VirtClass(const VirtClass&) = delete;
+    VirtClass(const VirtClass &) = delete;
     virtual void virtual_func() {}
     virtual void pure_virtual_func() = 0;
 };
 
 class PyVirtClass : public VirtClass {
-    void virtual_func() override {
-        PYBIND11_OVERRIDE(void, VirtClass, virtual_func,);
-    }
+    void virtual_func() override { PYBIND11_OVERRIDE(void, VirtClass, virtual_func, ); }
     void pure_virtual_func() override {
-        PYBIND11_OVERRIDE_PURE(void, VirtClass, pure_virtual_func,);
+        PYBIND11_OVERRIDE_PURE(void, VirtClass, pure_virtual_func, );
     }
 };
 
 TEST_SUBMODULE(gil_scoped, m) {
-  py::class_<VirtClass, PyVirtClass>(m, "VirtClass")
-      .def(py::init<>())
-      .def("virtual_func", &VirtClass::virtual_func)
-      .def("pure_virtual_func", &VirtClass::pure_virtual_func);
-
-    m.def("test_callback_py_obj",
-          [](py::object func) { func(); });
-    m.def("test_callback_std_func",
-          [](const std::function<void()> &func) { func(); });
-    m.def("test_callback_virtual_func",
-          [](VirtClass &virt) { virt.virtual_func(); });
-    m.def("test_callback_pure_virtual_func",
-          [](VirtClass &virt) { virt.pure_virtual_func(); });
-    m.def("test_cross_module_gil",
-          []() {
-              auto cm = py::module_::import("cross_module_gil_utils");
-              auto gil_acquire = reinterpret_cast<void (*)()>(
-                  PyLong_AsVoidPtr(cm.attr("gil_acquire_funcaddr").ptr()));
-              py::gil_scoped_release gil_release;
-              gil_acquire();
-          });
+    py::class_<VirtClass, PyVirtClass>(m, "VirtClass")
+        .def(py::init<>())
+        .def("virtual_func", &VirtClass::virtual_func)
+        .def("pure_virtual_func", &VirtClass::pure_virtual_func);
+
+    m.def("test_callback_py_obj", [](py::object &func) { func(); });
+    m.def("test_callback_std_func", [](const std::function<void()> &func) { func(); });
+    m.def("test_callback_virtual_func", [](VirtClass &virt) { virt.virtual_func(); });
+    m.def("test_callback_pure_virtual_func", [](VirtClass &virt) { virt.pure_virtual_func(); });
+    m.def("test_cross_module_gil", []() {
+        auto cm = py::module_::import("cross_module_gil_utils");
+        auto gil_acquire = reinterpret_cast<void (*)()>(
+            PyLong_AsVoidPtr(cm.attr("gil_acquire_funcaddr").ptr()));
+        py::gil_scoped_release gil_release;
+        gil_acquire();
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_gil_scoped.py b/3rdparty/pybind11/tests/test_gil_scoped.py
index 0a1d62747d..52374b0cce 100644
--- a/3rdparty/pybind11/tests/test_gil_scoped.py
+++ b/3rdparty/pybind11/tests/test_gil_scoped.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import multiprocessing
 import threading
 
diff --git a/3rdparty/pybind11/tests/test_iostream.cpp b/3rdparty/pybind11/tests/test_iostream.cpp
index e9161505ca..421eaa2dd8 100644
--- a/3rdparty/pybind11/tests/test_iostream.cpp
+++ b/3rdparty/pybind11/tests/test_iostream.cpp
@@ -7,67 +7,120 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-
 #include <pybind11/iostream.h>
+
 #include "pybind11_tests.h"
-#include <iostream>
 
+#include <atomic>
+#include <iostream>
+#include <mutex>
+#include <string>
+#include <thread>
 
-void noisy_function(std::string msg, bool flush) {
+void noisy_function(const std::string &msg, bool flush) {
 
     std::cout << msg;
-    if (flush)
+    if (flush) {
         std::cout << std::flush;
+    }
 }
 
-void noisy_funct_dual(std::string msg, std::string emsg) {
+void noisy_funct_dual(const std::string &msg, const std::string &emsg) {
     std::cout << msg;
     std::cerr << emsg;
 }
 
+// object to manage C++ thread
+// simply repeatedly write to std::cerr until stopped
+// redirect is called at some point to test the safety of scoped_estream_redirect
+struct TestThread {
+    TestThread() : stop_{false} {
+        auto thread_f = [this] {
+            static std::mutex cout_mutex;
+            while (!stop_) {
+                {
+                    // #HelpAppreciated: Work on iostream.h thread safety.
+                    // Without this lock, the clang ThreadSanitizer (tsan) reliably reports a
+                    // data race, and this test is predictably flakey on Windows.
+                    // For more background see the discussion under
+                    // https://github.com/pybind/pybind11/pull/2982 and
+                    // https://github.com/pybind/pybind11/pull/2995.
+                    const std::lock_guard<std::mutex> lock(cout_mutex);
+                    std::cout << "x" << std::flush;
+                }
+                std::this_thread::sleep_for(std::chrono::microseconds(50));
+            }
+        };
+        t_ = new std::thread(std::move(thread_f));
+    }
+
+    ~TestThread() { delete t_; }
+
+    void stop() { stop_ = true; }
+
+    void join() const {
+        py::gil_scoped_release gil_lock;
+        t_->join();
+    }
+
+    void sleep() {
+        py::gil_scoped_release gil_lock;
+        std::this_thread::sleep_for(std::chrono::milliseconds(50));
+    }
+
+    std::thread *t_{nullptr};
+    std::atomic<bool> stop_;
+};
+
 TEST_SUBMODULE(iostream, m) {
 
     add_ostream_redirect(m);
 
     // test_evals
 
-    m.def("captured_output_default", [](std::string msg) {
+    m.def("captured_output_default", [](const std::string &msg) {
         py::scoped_ostream_redirect redir;
         std::cout << msg << std::flush;
     });
 
-    m.def("captured_output", [](std::string msg) {
+    m.def("captured_output", [](const std::string &msg) {
         py::scoped_ostream_redirect redir(std::cout, py::module_::import("sys").attr("stdout"));
         std::cout << msg << std::flush;
     });
 
-    m.def("guard_output", &noisy_function,
-            py::call_guard<py::scoped_ostream_redirect>(),
-            py::arg("msg"), py::arg("flush")=true);
+    m.def("guard_output",
+          &noisy_function,
+          py::call_guard<py::scoped_ostream_redirect>(),
+          py::arg("msg"),
+          py::arg("flush") = true);
 
-    m.def("captured_err", [](std::string msg) {
+    m.def("captured_err", [](const std::string &msg) {
         py::scoped_ostream_redirect redir(std::cerr, py::module_::import("sys").attr("stderr"));
         std::cerr << msg << std::flush;
     });
 
     m.def("noisy_function", &noisy_function, py::arg("msg"), py::arg("flush") = true);
 
-    m.def("dual_guard", &noisy_funct_dual,
-            py::call_guard<py::scoped_ostream_redirect, py::scoped_estream_redirect>(),
-            py::arg("msg"), py::arg("emsg"));
+    m.def("dual_guard",
+          &noisy_funct_dual,
+          py::call_guard<py::scoped_ostream_redirect, py::scoped_estream_redirect>(),
+          py::arg("msg"),
+          py::arg("emsg"));
 
-    m.def("raw_output", [](std::string msg) {
-        std::cout << msg << std::flush;
-    });
+    m.def("raw_output", [](const std::string &msg) { std::cout << msg << std::flush; });
 
-    m.def("raw_err", [](std::string msg) {
-        std::cerr << msg << std::flush;
-    });
+    m.def("raw_err", [](const std::string &msg) { std::cerr << msg << std::flush; });
 
-    m.def("captured_dual", [](std::string msg, std::string emsg) {
+    m.def("captured_dual", [](const std::string &msg, const std::string &emsg) {
         py::scoped_ostream_redirect redirout(std::cout, py::module_::import("sys").attr("stdout"));
         py::scoped_ostream_redirect redirerr(std::cerr, py::module_::import("sys").attr("stderr"));
         std::cout << msg << std::flush;
         std::cerr << emsg << std::flush;
     });
+
+    py::class_<TestThread>(m, "TestThread")
+        .def(py::init<>())
+        .def("stop", &TestThread::stop)
+        .def("join", &TestThread::join)
+        .def("sleep", &TestThread::sleep);
 }
diff --git a/3rdparty/pybind11/tests/test_iostream.py b/3rdparty/pybind11/tests/test_iostream.py
index 506db42ec1..5bbdf6955d 100644
--- a/3rdparty/pybind11/tests/test_iostream.py
+++ b/3rdparty/pybind11/tests/test_iostream.py
@@ -1,43 +1,7 @@
-# -*- coding: utf-8 -*-
+from contextlib import redirect_stderr, redirect_stdout
+from io import StringIO
+
 from pybind11_tests import iostream as m
-import sys
-
-from contextlib import contextmanager
-
-try:
-    # Python 3
-    from io import StringIO
-except ImportError:
-    # Python 2
-    try:
-        from cStringIO import StringIO
-    except ImportError:
-        from StringIO import StringIO
-
-try:
-    # Python 3.4
-    from contextlib import redirect_stdout
-except ImportError:
-
-    @contextmanager
-    def redirect_stdout(target):
-        original = sys.stdout
-        sys.stdout = target
-        yield
-        sys.stdout = original
-
-
-try:
-    # Python 3.5
-    from contextlib import redirect_stderr
-except ImportError:
-
-    @contextmanager
-    def redirect_stderr(target):
-        original = sys.stderr
-        sys.stderr = target
-        yield
-        sys.stderr = original
 
 
 def test_captured(capsys):
@@ -69,6 +33,96 @@ def test_captured_large_string(capsys):
     assert stderr == ""
 
 
+def test_captured_utf8_2byte_offset0(capsys):
+    msg = "\u07FF"
+    msg = "" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_2byte_offset1(capsys):
+    msg = "\u07FF"
+    msg = "1" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_3byte_offset0(capsys):
+    msg = "\uFFFF"
+    msg = "" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_3byte_offset1(capsys):
+    msg = "\uFFFF"
+    msg = "1" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_3byte_offset2(capsys):
+    msg = "\uFFFF"
+    msg = "12" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_4byte_offset0(capsys):
+    msg = "\U0010FFFF"
+    msg = "" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_4byte_offset1(capsys):
+    msg = "\U0010FFFF"
+    msg = "1" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_4byte_offset2(capsys):
+    msg = "\U0010FFFF"
+    msg = "12" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
+def test_captured_utf8_4byte_offset3(capsys):
+    msg = "\U0010FFFF"
+    msg = "123" + msg * (1024 // len(msg) + 1)
+
+    m.captured_output_default(msg)
+    stdout, stderr = capsys.readouterr()
+    assert stdout == msg
+    assert stderr == ""
+
+
 def test_guard_capture(capsys):
     msg = "I've been redirected to Python, I hope!"
     m.guard_output(msg)
@@ -216,3 +270,26 @@ def test_redirect_both(capfd):
     assert stderr == ""
     assert stream.getvalue() == msg
     assert stream2.getvalue() == msg2
+
+
+def test_threading():
+    with m.ostream_redirect(stdout=True, stderr=False):
+        # start some threads
+        threads = []
+
+        # start some threads
+        for _j in range(20):
+            threads.append(m.TestThread())
+
+        # give the threads some time to fail
+        threads[0].sleep()
+
+        # stop all the threads
+        for t in threads:
+            t.stop()
+
+        for t in threads:
+            t.join()
+
+        # if a thread segfaults, we don't get here
+        assert True
diff --git a/3rdparty/pybind11/tests/test_kwargs_and_defaults.cpp b/3rdparty/pybind11/tests/test_kwargs_and_defaults.cpp
index 627a79690e..2f3cabaf0f 100644
--- a/3rdparty/pybind11/tests/test_kwargs_and_defaults.cpp
+++ b/3rdparty/pybind11/tests/test_kwargs_and_defaults.cpp
@@ -7,136 +7,276 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/stl.h>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
+#include <utility>
+
 TEST_SUBMODULE(kwargs_and_defaults, m) {
-    auto kw_func = [](int x, int y) { return "x=" + std::to_string(x) + ", y=" + std::to_string(y); };
+    auto kw_func
+        = [](int x, int y) { return "x=" + std::to_string(x) + ", y=" + std::to_string(y); };
 
     // test_named_arguments
     m.def("kw_func0", kw_func);
     m.def("kw_func1", kw_func, py::arg("x"), py::arg("y"));
     m.def("kw_func2", kw_func, py::arg("x") = 100, py::arg("y") = 200);
-    m.def("kw_func3", [](const char *) { }, py::arg("data") = std::string("Hello world!"));
+    m.def(
+        "kw_func3", [](const char *) {}, py::arg("data") = std::string("Hello world!"));
 
     /* A fancier default argument */
     std::vector<int> list{{13, 17}};
-    m.def("kw_func4", [](const std::vector<int> &entries) {
-        std::string ret = "{";
-        for (int i : entries)
-            ret += std::to_string(i) + " ";
-        ret.back() = '}';
-        return ret;
-    }, py::arg("myList") = list);
+    m.def(
+        "kw_func4",
+        [](const std::vector<int> &entries) {
+            std::string ret = "{";
+            for (int i : entries) {
+                ret += std::to_string(i) + " ";
+            }
+            ret.back() = '}';
+            return ret;
+        },
+        py::arg("myList") = list);
 
-    m.def("kw_func_udl", kw_func, "x"_a, "y"_a=300);
-    m.def("kw_func_udl_z", kw_func, "x"_a, "y"_a=0);
+    m.def("kw_func_udl", kw_func, "x"_a, "y"_a = 300);
+    m.def("kw_func_udl_z", kw_func, "x"_a, "y"_a = 0);
 
     // test_args_and_kwargs
     m.def("args_function", [](py::args args) -> py::tuple {
-        return std::move(args);
+#ifdef PYBIND11_DETECTED_CLANG_WITH_MISLEADING_CALL_STD_MOVE_EXPLICITLY_WARNING
+#    pragma clang diagnostic push
+#    pragma clang diagnostic ignored "-Wreturn-std-move"
+#endif
+        return args;
+#ifdef PYBIND11_DETECTED_CLANG_WITH_MISLEADING_CALL_STD_MOVE_EXPLICITLY_WARNING
+#    pragma clang diagnostic pop
+#endif
     });
-    m.def("args_kwargs_function", [](py::args args, py::kwargs kwargs) {
+    m.def("args_kwargs_function", [](const py::args &args, const py::kwargs &kwargs) {
         return py::make_tuple(args, kwargs);
     });
 
     // test_mixed_args_and_kwargs
-    m.def("mixed_plus_args", [](int i, double j, py::args args) {
-        return py::make_tuple(i, j, args);
-    });
-    m.def("mixed_plus_kwargs", [](int i, double j, py::kwargs kwargs) {
-        return py::make_tuple(i, j, kwargs);
-    });
-    auto mixed_plus_both = [](int i, double j, py::args args, py::kwargs kwargs) {
+    m.def("mixed_plus_args",
+          [](int i, double j, const py::args &args) { return py::make_tuple(i, j, args); });
+    m.def("mixed_plus_kwargs",
+          [](int i, double j, const py::kwargs &kwargs) { return py::make_tuple(i, j, kwargs); });
+    auto mixed_plus_both = [](int i, double j, const py::args &args, const py::kwargs &kwargs) {
         return py::make_tuple(i, j, args, kwargs);
     };
     m.def("mixed_plus_args_kwargs", mixed_plus_both);
 
-    m.def("mixed_plus_args_kwargs_defaults", mixed_plus_both,
-            py::arg("i") = 1, py::arg("j") = 3.14159);
-
-    // test_args_refcount
-    // PyPy needs a garbage collection to get the reference count values to match CPython's behaviour
-    #ifdef PYPY_VERSION
-    #define GC_IF_NEEDED ConstructorStats::gc()
-    #else
-    #define GC_IF_NEEDED
-    #endif
-    m.def("arg_refcount_h", [](py::handle h) { GC_IF_NEEDED; return h.ref_count(); });
-    m.def("arg_refcount_h", [](py::handle h, py::handle, py::handle) { GC_IF_NEEDED; return h.ref_count(); });
-    m.def("arg_refcount_o", [](py::object o) { GC_IF_NEEDED; return o.ref_count(); });
+    m.def("mixed_plus_args_kwargs_defaults",
+          mixed_plus_both,
+          py::arg("i") = 1,
+          py::arg("j") = 3.14159);
+
+    m.def(
+        "args_kwonly",
+        [](int i, double j, const py::args &args, int z) { return py::make_tuple(i, j, args, z); },
+        "i"_a,
+        "j"_a,
+        "z"_a);
+    m.def(
+        "args_kwonly_kwargs",
+        [](int i, double j, const py::args &args, int z, const py::kwargs &kwargs) {
+            return py::make_tuple(i, j, args, z, kwargs);
+        },
+        "i"_a,
+        "j"_a,
+        py::kw_only{},
+        "z"_a);
+    m.def(
+        "args_kwonly_kwargs_defaults",
+        [](int i, double j, const py::args &args, int z, const py::kwargs &kwargs) {
+            return py::make_tuple(i, j, args, z, kwargs);
+        },
+        "i"_a = 1,
+        "j"_a = 3.14159,
+        "z"_a = 42);
+    m.def(
+        "args_kwonly_full_monty",
+        [](int h, int i, double j, const py::args &args, int z, const py::kwargs &kwargs) {
+            return py::make_tuple(h, i, j, args, z, kwargs);
+        },
+        py::arg() = 1,
+        py::arg() = 2,
+        py::pos_only{},
+        "j"_a = 3.14159,
+        "z"_a = 42);
+
+// test_args_refcount
+// PyPy needs a garbage collection to get the reference count values to match CPython's behaviour
+#ifdef PYPY_VERSION
+#    define GC_IF_NEEDED ConstructorStats::gc()
+#else
+#    define GC_IF_NEEDED
+#endif
+    m.def("arg_refcount_h", [](py::handle h) {
+        GC_IF_NEEDED;
+        return h.ref_count();
+    });
+    m.def("arg_refcount_h", [](py::handle h, py::handle, py::handle) {
+        GC_IF_NEEDED;
+        return h.ref_count();
+    });
+    m.def("arg_refcount_o", [](const py::object &o) {
+        GC_IF_NEEDED;
+        return o.ref_count();
+    });
     m.def("args_refcount", [](py::args a) {
         GC_IF_NEEDED;
         py::tuple t(a.size());
-        for (size_t i = 0; i < a.size(); i++)
+        for (size_t i = 0; i < a.size(); i++) {
             // Use raw Python API here to avoid an extra, intermediate incref on the tuple item:
             t[i] = (int) Py_REFCNT(PyTuple_GET_ITEM(a.ptr(), static_cast<py::ssize_t>(i)));
+        }
         return t;
     });
-    m.def("mixed_args_refcount", [](py::object o, py::args a) {
+    m.def("mixed_args_refcount", [](const py::object &o, py::args a) {
         GC_IF_NEEDED;
         py::tuple t(a.size() + 1);
         t[0] = o.ref_count();
-        for (size_t i = 0; i < a.size(); i++)
+        for (size_t i = 0; i < a.size(); i++) {
             // Use raw Python API here to avoid an extra, intermediate incref on the tuple item:
             t[i + 1] = (int) Py_REFCNT(PyTuple_GET_ITEM(a.ptr(), static_cast<py::ssize_t>(i)));
+        }
         return t;
     });
 
     // pybind11 won't allow these to be bound: args and kwargs, if present, must be at the end.
     // Uncomment these to test that the static_assert is indeed working:
-//    m.def("bad_args1", [](py::args, int) {});
-//    m.def("bad_args2", [](py::kwargs, int) {});
-//    m.def("bad_args3", [](py::kwargs, py::args) {});
-//    m.def("bad_args4", [](py::args, int, py::kwargs) {});
-//    m.def("bad_args5", [](py::args, py::kwargs, int) {});
-//    m.def("bad_args6", [](py::args, py::args) {});
-//    m.def("bad_args7", [](py::kwargs, py::kwargs) {});
+    //    m.def("bad_args1", [](py::args, int) {});
+    //    m.def("bad_args2", [](py::kwargs, int) {});
+    //    m.def("bad_args3", [](py::kwargs, py::args) {});
+    //    m.def("bad_args4", [](py::args, int, py::kwargs) {});
+    //    m.def("bad_args5", [](py::args, py::kwargs, int) {});
+    //    m.def("bad_args6", [](py::args, py::args) {});
+    //    m.def("bad_args7", [](py::kwargs, py::kwargs) {});
 
     // test_keyword_only_args
-    m.def("kw_only_all", [](int i, int j) { return py::make_tuple(i, j); },
-            py::kw_only(), py::arg("i"), py::arg("j"));
-    m.def("kw_only_some", [](int i, int j, int k) { return py::make_tuple(i, j, k); },
-            py::arg(), py::kw_only(), py::arg("j"), py::arg("k"));
-    m.def("kw_only_with_defaults", [](int i, int j, int k, int z) { return py::make_tuple(i, j, k, z); },
-            py::arg() = 3, "j"_a = 4, py::kw_only(), "k"_a = 5, "z"_a);
-    m.def("kw_only_mixed", [](int i, int j) { return py::make_tuple(i, j); },
-            "i"_a, py::kw_only(), "j"_a);
-    m.def("kw_only_plus_more", [](int i, int j, int k, py::kwargs kwargs) {
-            return py::make_tuple(i, j, k, kwargs); },
-            py::arg() /* positional */, py::arg("j") = -1 /* both */, py::kw_only(), py::arg("k") /* kw-only */);
+    m.def(
+        "kw_only_all",
+        [](int i, int j) { return py::make_tuple(i, j); },
+        py::kw_only(),
+        py::arg("i"),
+        py::arg("j"));
+    m.def(
+        "kw_only_some",
+        [](int i, int j, int k) { return py::make_tuple(i, j, k); },
+        py::arg(),
+        py::kw_only(),
+        py::arg("j"),
+        py::arg("k"));
+    m.def(
+        "kw_only_with_defaults",
+        [](int i, int j, int k, int z) { return py::make_tuple(i, j, k, z); },
+        py::arg() = 3,
+        "j"_a = 4,
+        py::kw_only(),
+        "k"_a = 5,
+        "z"_a);
+    m.def(
+        "kw_only_mixed",
+        [](int i, int j) { return py::make_tuple(i, j); },
+        "i"_a,
+        py::kw_only(),
+        "j"_a);
+    m.def(
+        "kw_only_plus_more",
+        [](int i, int j, int k, const py::kwargs &kwargs) {
+            return py::make_tuple(i, j, k, kwargs);
+        },
+        py::arg() /* positional */,
+        py::arg("j") = -1 /* both */,
+        py::kw_only(),
+        py::arg("k") /* kw-only */);
 
     m.def("register_invalid_kw_only", [](py::module_ m) {
-        m.def("bad_kw_only", [](int i, int j) { return py::make_tuple(i, j); },
-                py::kw_only(), py::arg() /* invalid unnamed argument */, "j"_a);
+        m.def(
+            "bad_kw_only",
+            [](int i, int j) { return py::make_tuple(i, j); },
+            py::kw_only(),
+            py::arg() /* invalid unnamed argument */,
+            "j"_a);
     });
 
     // test_positional_only_args
-    m.def("pos_only_all", [](int i, int j) { return py::make_tuple(i, j); },
-            py::arg("i"), py::arg("j"), py::pos_only());
-    m.def("pos_only_mix", [](int i, int j) { return py::make_tuple(i, j); },
-            py::arg("i"), py::pos_only(), py::arg("j"));
-    m.def("pos_kw_only_mix", [](int i, int j, int k) { return py::make_tuple(i, j, k); },
-            py::arg("i"), py::pos_only(), py::arg("j"), py::kw_only(), py::arg("k"));
-    m.def("pos_only_def_mix", [](int i, int j, int k) { return py::make_tuple(i, j, k); },
-            py::arg("i"), py::arg("j") = 2, py::pos_only(), py::arg("k") = 3);
-
+    m.def(
+        "pos_only_all",
+        [](int i, int j) { return py::make_tuple(i, j); },
+        py::arg("i"),
+        py::arg("j"),
+        py::pos_only());
+    m.def(
+        "pos_only_mix",
+        [](int i, int j) { return py::make_tuple(i, j); },
+        py::arg("i"),
+        py::pos_only(),
+        py::arg("j"));
+    m.def(
+        "pos_kw_only_mix",
+        [](int i, int j, int k) { return py::make_tuple(i, j, k); },
+        py::arg("i"),
+        py::pos_only(),
+        py::arg("j"),
+        py::kw_only(),
+        py::arg("k"));
+    m.def(
+        "pos_only_def_mix",
+        [](int i, int j, int k) { return py::make_tuple(i, j, k); },
+        py::arg("i"),
+        py::arg("j") = 2,
+        py::pos_only(),
+        py::arg("k") = 3);
 
     // These should fail to compile:
+#ifdef PYBIND11_NEVER_DEFINED_EVER
     // argument annotations are required when using kw_only
-//    m.def("bad_kw_only1", [](int) {}, py::kw_only());
+    m.def(
+        "bad_kw_only1", [](int) {}, py::kw_only());
     // can't specify both `py::kw_only` and a `py::args` argument
-//    m.def("bad_kw_only2", [](int i, py::args) {}, py::kw_only(), "i"_a);
+    m.def(
+        "bad_kw_only2", [](int i, py::args) {}, py::kw_only(), "i"_a);
+#endif
 
     // test_function_signatures (along with most of the above)
-    struct KWClass { void foo(int, float) {} };
+    struct KWClass {
+        void foo(int, float) {}
+    };
     py::class_<KWClass>(m, "KWClass")
         .def("foo0", &KWClass::foo)
         .def("foo1", &KWClass::foo, "x"_a, "y"_a);
 
     // Make sure a class (not an instance) can be used as a default argument.
     // The return value doesn't matter, only that the module is importable.
-    m.def("class_default_argument", [](py::object a) { return py::repr(a); },
+    m.def(
+        "class_default_argument",
+        [](py::object a) { return py::repr(std::move(a)); },
         "a"_a = py::module_::import("decimal").attr("Decimal"));
+
+    // Initial implementation of kw_only was broken when used on a method/constructor before any
+    // other arguments
+    // https://github.com/pybind/pybind11/pull/3402#issuecomment-963341987
+
+    struct first_arg_kw_only {};
+    py::class_<first_arg_kw_only>(m, "first_arg_kw_only")
+        .def(py::init([](int) { return first_arg_kw_only(); }),
+             py::kw_only(), // This being before any args was broken
+             py::arg("i") = 0)
+        .def(
+            "method",
+            [](first_arg_kw_only &, int, int) {},
+            py::kw_only(), // and likewise here
+            py::arg("i") = 1,
+            py::arg("j") = 2)
+        // Closely related: pos_only marker didn't show up properly when it was before any other
+        // arguments (although that is fairly useless in practice).
+        .def(
+            "pos_only",
+            [](first_arg_kw_only &, int, int) {},
+            py::pos_only{},
+            py::arg("i"),
+            py::arg("j"));
 }
diff --git a/3rdparty/pybind11/tests/test_kwargs_and_defaults.py b/3rdparty/pybind11/tests/test_kwargs_and_defaults.py
index 12fe705b4d..ab7017886e 100644
--- a/3rdparty/pybind11/tests/test_kwargs_and_defaults.py
+++ b/3rdparty/pybind11/tests/test_kwargs_and_defaults.py
@@ -1,8 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
 
-import env  # noqa: F401
-
 from pybind11_tests import kwargs_and_defaults as m
 
 
@@ -83,7 +80,7 @@ def test_mixed_args_and_kwargs(msg):
             1. (arg0: int, arg1: float, *args) -> tuple
 
         Invoked with: 1
-    """  # noqa: E501 line too long
+    """
     )
     with pytest.raises(TypeError) as excinfo:
         assert mpa()
@@ -94,7 +91,7 @@ def test_mixed_args_and_kwargs(msg):
             1. (arg0: int, arg1: float, *args) -> tuple
 
         Invoked with:
-    """  # noqa: E501 line too long
+    """
     )
 
     assert mpk(-2, 3.5, pi=3.14159, e=2.71828) == (
@@ -128,7 +125,7 @@ def test_mixed_args_and_kwargs(msg):
             1. (i: int = 1, j: float = 3.14159, *args, **kwargs) -> tuple
 
         Invoked with: 1; kwargs: i=1
-    """  # noqa: E501 line too long
+    """
     )
     with pytest.raises(TypeError) as excinfo:
         assert mpakd(1, 2, j=1)
@@ -139,9 +136,56 @@ def test_mixed_args_and_kwargs(msg):
             1. (i: int = 1, j: float = 3.14159, *args, **kwargs) -> tuple
 
         Invoked with: 1, 2; kwargs: j=1
-    """  # noqa: E501 line too long
+    """
+    )
+
+    # Arguments after a py::args are automatically keyword-only (pybind 2.9+)
+    assert m.args_kwonly(2, 2.5, z=22) == (2, 2.5, (), 22)
+    assert m.args_kwonly(2, 2.5, "a", "b", "c", z=22) == (2, 2.5, ("a", "b", "c"), 22)
+    assert m.args_kwonly(z=22, i=4, j=16) == (4, 16, (), 22)
+
+    with pytest.raises(TypeError) as excinfo:
+        assert m.args_kwonly(2, 2.5, 22)  # missing z= keyword
+    assert (
+        msg(excinfo.value)
+        == """
+        args_kwonly(): incompatible function arguments. The following argument types are supported:
+            1. (i: int, j: float, *args, z: int) -> tuple
+
+        Invoked with: 2, 2.5, 22
+    """
     )
 
+    assert m.args_kwonly_kwargs(i=1, k=4, j=10, z=-1, y=9) == (
+        1,
+        10,
+        (),
+        -1,
+        {"k": 4, "y": 9},
+    )
+    assert m.args_kwonly_kwargs(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, z=11, y=12) == (
+        1,
+        2,
+        (3, 4, 5, 6, 7, 8, 9, 10),
+        11,
+        {"y": 12},
+    )
+    assert (
+        m.args_kwonly_kwargs.__doc__
+        == "args_kwonly_kwargs(i: int, j: float, *args, z: int, **kwargs) -> tuple\n"
+    )
+
+    assert (
+        m.args_kwonly_kwargs_defaults.__doc__
+        == "args_kwonly_kwargs_defaults(i: int = 1, j: float = 3.14159, *args, z: int = 42, **kwargs) -> tuple\n"  # noqa: E501 line too long
+    )
+    assert m.args_kwonly_kwargs_defaults() == (1, 3.14159, (), 42, {})
+    assert m.args_kwonly_kwargs_defaults(2) == (2, 3.14159, (), 42, {})
+    assert m.args_kwonly_kwargs_defaults(z=-99) == (1, 3.14159, (), -99, {})
+    assert m.args_kwonly_kwargs_defaults(5, 6, 7, 8) == (5, 6, (7, 8), 42, {})
+    assert m.args_kwonly_kwargs_defaults(5, 6, 7, m=8) == (5, 6, (7,), 42, {"m": 8})
+    assert m.args_kwonly_kwargs_defaults(5, 6, 7, m=8, z=9) == (5, 6, (7,), 9, {"m": 8})
+
 
 def test_keyword_only_args(msg):
     assert m.kw_only_all(i=1, j=2) == (1, 2)
@@ -179,10 +223,23 @@ def test_keyword_only_args(msg):
     assert (
         msg(excinfo.value)
         == """
-        arg(): cannot specify an unnamed argument after an kw_only() annotation
+        arg(): cannot specify an unnamed argument after a kw_only() annotation or args() argument
     """
     )
 
+    # https://github.com/pybind/pybind11/pull/3402#issuecomment-963341987
+    x = m.first_arg_kw_only(i=1)
+    x.method()
+    x.method(i=1, j=2)
+    assert (
+        m.first_arg_kw_only.__init__.__doc__
+        == "__init__(self: pybind11_tests.kwargs_and_defaults.first_arg_kw_only, *, i: int = 0) -> None\n"  # noqa: E501 line too long
+    )
+    assert (
+        m.first_arg_kw_only.method.__doc__
+        == "method(self: pybind11_tests.kwargs_and_defaults.first_arg_kw_only, *, i: int = 1, j: int = 2) -> None\n"  # noqa: E501 line too long
+    )
+
 
 def test_positional_only_args(msg):
     assert m.pos_only_all(1, 2) == (1, 2)
@@ -223,6 +280,55 @@ def test_positional_only_args(msg):
         m.pos_only_def_mix(1, j=4)
     assert "incompatible function arguments" in str(excinfo.value)
 
+    # Mix it with args and kwargs:
+    assert (
+        m.args_kwonly_full_monty.__doc__
+        == "args_kwonly_full_monty(arg0: int = 1, arg1: int = 2, /, j: float = 3.14159, *args, z: int = 42, **kwargs) -> tuple\n"  # noqa: E501 line too long
+    )
+    assert m.args_kwonly_full_monty() == (1, 2, 3.14159, (), 42, {})
+    assert m.args_kwonly_full_monty(8) == (8, 2, 3.14159, (), 42, {})
+    assert m.args_kwonly_full_monty(8, 9) == (8, 9, 3.14159, (), 42, {})
+    assert m.args_kwonly_full_monty(8, 9, 10) == (8, 9, 10.0, (), 42, {})
+    assert m.args_kwonly_full_monty(3, 4, 5, 6, 7, m=8, z=9) == (
+        3,
+        4,
+        5.0,
+        (
+            6,
+            7,
+        ),
+        9,
+        {"m": 8},
+    )
+    assert m.args_kwonly_full_monty(3, 4, 5, 6, 7, m=8, z=9) == (
+        3,
+        4,
+        5.0,
+        (
+            6,
+            7,
+        ),
+        9,
+        {"m": 8},
+    )
+    assert m.args_kwonly_full_monty(5, j=7, m=8, z=9) == (5, 2, 7.0, (), 9, {"m": 8})
+    assert m.args_kwonly_full_monty(i=5, j=7, m=8, z=9) == (
+        1,
+        2,
+        7.0,
+        (),
+        9,
+        {"i": 5, "m": 8},
+    )
+
+    # pos_only at the beginning of the argument list was "broken" in how it was displayed (though
+    # this is fairly useless in practice).  Related to:
+    # https://github.com/pybind/pybind11/pull/3402#issuecomment-963341987
+    assert (
+        m.first_arg_kw_only.pos_only.__doc__
+        == "pos_only(self: pybind11_tests.kwargs_and_defaults.first_arg_kw_only, /, i: int, j: int) -> None\n"  # noqa: E501 line too long
+    )
+
 
 def test_signatures():
     assert "kw_only_all(*, i: int, j: int) -> tuple\n" == m.kw_only_all.__doc__
@@ -235,7 +341,6 @@ def test_signatures():
     )
 
 
-@pytest.mark.xfail("env.PYPY and env.PY2", reason="PyPy2 doesn't double count")
 def test_args_refcount():
     """Issue/PR #1216 - py::args elements get double-inc_ref()ed when combined with regular
     arguments"""
diff --git a/3rdparty/pybind11/tests/test_local_bindings.cpp b/3rdparty/pybind11/tests/test_local_bindings.cpp
index c61e388833..1373677447 100644
--- a/3rdparty/pybind11/tests/test_local_bindings.cpp
+++ b/3rdparty/pybind11/tests/test_local_bindings.cpp
@@ -8,11 +8,14 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "local_bindings.h"
 #include <pybind11/stl.h>
 #include <pybind11/stl_bind.h>
+
+#include "local_bindings.h"
+#include "pybind11_tests.h"
+
 #include <numeric>
+#include <utility>
 
 TEST_SUBMODULE(local_bindings, m) {
     // test_load_external
@@ -21,9 +24,9 @@ TEST_SUBMODULE(local_bindings, m) {
 
     // test_local_bindings
     // Register a class with py::module_local:
-    bind_local<LocalType, -1>(m, "LocalType", py::module_local())
-        .def("get3", [](LocalType &t) { return t.i + 3; })
-        ;
+    bind_local<LocalType, -1>(m, "LocalType", py::module_local()).def("get3", [](LocalType &t) {
+        return t.i + 3;
+    });
 
     m.def("local_value", [](LocalType &l) { return l.i; });
 
@@ -32,20 +35,21 @@ TEST_SUBMODULE(local_bindings, m) {
     // one, in pybind11_cross_module_tests.cpp, is designed to fail):
     bind_local<NonLocalType, 0>(m, "NonLocalType")
         .def(py::init<int>())
-        .def("get", [](LocalType &i) { return i.i; })
-        ;
+        .def("get", [](LocalType &i) { return i.i; });
 
     // test_duplicate_local
-    // py::module_local declarations should be visible across compilation units that get linked together;
-    // this tries to register a duplicate local.  It depends on a definition in test_class.cpp and
-    // should raise a runtime error from the duplicate definition attempt.  If test_class isn't
-    // available it *also* throws a runtime error (with "test_class not enabled" as value).
+    // py::module_local declarations should be visible across compilation units that get linked
+    // together; this tries to register a duplicate local.  It depends on a definition in
+    // test_class.cpp and should raise a runtime error from the duplicate definition attempt.  If
+    // test_class isn't available it *also* throws a runtime error (with "test_class not enabled"
+    // as value).
     m.def("register_local_external", [m]() {
         auto main = py::module_::import("pybind11_tests");
         if (py::hasattr(main, "class_")) {
             bind_local<LocalExternal, 7>(m, "LocalExternal", py::module_local());
+        } else {
+            throw std::runtime_error("test_class not enabled");
         }
-        else throw std::runtime_error("test_class not enabled");
     });
 
     // test_stl_bind_local
@@ -75,23 +79,24 @@ TEST_SUBMODULE(local_bindings, m) {
     m.def("get_mixed_lg", [](int i) { return MixedLocalGlobal(i); });
 
     // test_internal_locals_differ
-    m.def("local_cpp_types_addr", []() { return (uintptr_t) &py::detail::registered_local_types_cpp(); });
+    m.def("local_cpp_types_addr",
+          []() { return (uintptr_t) &py::detail::get_local_internals().registered_types_cpp; });
 
     // test_stl_caster_vs_stl_bind
-    m.def("load_vector_via_caster", [](std::vector<int> v) {
-        return std::accumulate(v.begin(), v.end(), 0);
-    });
+    m.def("load_vector_via_caster",
+          [](std::vector<int> v) { return std::accumulate(v.begin(), v.end(), 0); });
 
     // test_cross_module_calls
     m.def("return_self", [](LocalVec *v) { return v; });
     m.def("return_copy", [](const LocalVec &v) { return LocalVec(v); });
 
-    class Cat : public pets::Pet { public: Cat(std::string name) : Pet(name) {}; };
-    py::class_<pets::Pet>(m, "Pet", py::module_local())
-        .def("get_name", &pets::Pet::name);
+    class Cat : public pets::Pet {
+    public:
+        explicit Cat(std::string name) : Pet(std::move(name)) {}
+    };
+    py::class_<pets::Pet>(m, "Pet", py::module_local()).def("get_name", &pets::Pet::name);
     // Binding for local extending class:
-    py::class_<Cat, pets::Pet>(m, "Cat")
-        .def(py::init<std::string>());
+    py::class_<Cat, pets::Pet>(m, "Cat").def(py::init<std::string>());
     m.def("pet_name", [](pets::Pet &p) { return p.name(); });
 
     py::class_<MixGL>(m, "MixGL").def(py::init<int>());
diff --git a/3rdparty/pybind11/tests/test_local_bindings.py b/3rdparty/pybind11/tests/test_local_bindings.py
index d23c467528..654d96d490 100644
--- a/3rdparty/pybind11/tests/test_local_bindings.py
+++ b/3rdparty/pybind11/tests/test_local_bindings.py
@@ -1,8 +1,6 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
-
 from pybind11_tests import local_bindings as m
 
 
@@ -193,7 +191,7 @@ def test_stl_caster_vs_stl_bind(msg):
     v2 = [1, 2, 3]
     assert m.load_vector_via_caster(v2) == 6
     with pytest.raises(TypeError) as excinfo:
-        cm.load_vector_via_binding(v2) == 6
+        cm.load_vector_via_binding(v2)
     assert (
         msg(excinfo.value)
         == """
@@ -201,7 +199,7 @@ def test_stl_caster_vs_stl_bind(msg):
         1. (arg0: pybind11_cross_module_tests.VectorInt) -> int
 
     Invoked with: [1, 2, 3]
-    """  # noqa: E501 line too long
+    """
     )
 
 
diff --git a/3rdparty/pybind11/tests/test_methods_and_attributes.cpp b/3rdparty/pybind11/tests/test_methods_and_attributes.cpp
index 6a2cfb6f7a..815dd5e98a 100644
--- a/3rdparty/pybind11/tests/test_methods_and_attributes.cpp
+++ b/3rdparty/pybind11/tests/test_methods_and_attributes.cpp
@@ -8,8 +8,8 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include "constructor_stats.h"
+#include "pybind11_tests.h"
 
 #if !defined(PYBIND11_OVERLOAD_CAST)
 template <typename... Args>
@@ -19,55 +19,61 @@ using overload_cast_ = pybind11::detail::overload_cast_impl<Args...>;
 class ExampleMandA {
 public:
     ExampleMandA() { print_default_created(this); }
-    ExampleMandA(int value) : value(value) { print_created(this, value); }
+    explicit ExampleMandA(int value) : value(value) { print_created(this, value); }
     ExampleMandA(const ExampleMandA &e) : value(e.value) { print_copy_created(this); }
-    ExampleMandA(std::string&&) {}
-    ExampleMandA(ExampleMandA &&e) : value(e.value) { print_move_created(this); }
+    explicit ExampleMandA(std::string &&) {}
+    ExampleMandA(ExampleMandA &&e) noexcept : value(e.value) { print_move_created(this); }
     ~ExampleMandA() { print_destroyed(this); }
 
-    std::string toString() {
-        return "ExampleMandA[value=" + std::to_string(value) + "]";
-    }
+    std::string toString() const { return "ExampleMandA[value=" + std::to_string(value) + "]"; }
 
-    void operator=(const ExampleMandA &e) { print_copy_assigned(this); value = e.value; }
-    void operator=(ExampleMandA &&e) { print_move_assigned(this); value = e.value; }
+    void operator=(const ExampleMandA &e) {
+        print_copy_assigned(this);
+        value = e.value;
+    }
+    void operator=(ExampleMandA &&e) noexcept {
+        print_move_assigned(this);
+        value = e.value;
+    }
 
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
     void add1(ExampleMandA other) { value += other.value; }         // passing by value
     void add2(ExampleMandA &other) { value += other.value; }        // passing by reference
     void add3(const ExampleMandA &other) { value += other.value; }  // passing by const reference
     void add4(ExampleMandA *other) { value += other->value; }       // passing by pointer
     void add5(const ExampleMandA *other) { value += other->value; } // passing by const pointer
 
-    void add6(int other) { value += other; }                        // passing by value
-    void add7(int &other) { value += other; }                       // passing by reference
-    void add8(const int &other) { value += other; }                 // passing by const reference
-    void add9(int *other) { value += *other; }                      // passing by pointer
-    void add10(const int *other) { value += *other; }               // passing by const pointer
-
-    void consume_str(std::string&&) {}
-
-    ExampleMandA self1() { return *this; }                          // return by value
-    ExampleMandA &self2() { return *this; }                         // return by reference
-    const ExampleMandA &self3() { return *this; }                   // return by const reference
-    ExampleMandA *self4() { return this; }                          // return by pointer
-    const ExampleMandA *self5() { return this; }                    // return by const pointer
-
-    int internal1() { return value; }                               // return by value
-    int &internal2() { return value; }                              // return by reference
-    const int &internal3() { return value; }                        // return by const reference
-    int *internal4() { return &value; }                             // return by pointer
-    const int *internal5() { return &value; }                       // return by const pointer
-
-    py::str overloaded()             { return "()"; }
-    py::str overloaded(int)          { return "(int)"; }
-    py::str overloaded(int, float)   { return "(int, float)"; }
-    py::str overloaded(float, int)   { return "(float, int)"; }
-    py::str overloaded(int, int)     { return "(int, int)"; }
+    void add6(int other) { value += other; }        // passing by value
+    void add7(int &other) { value += other; }       // passing by reference
+    void add8(const int &other) { value += other; } // passing by const reference
+    // NOLINTNEXTLINE(readability-non-const-parameter) Deliberately non-const for testing
+    void add9(int *other) { value += *other; }        // passing by pointer
+    void add10(const int *other) { value += *other; } // passing by const pointer
+
+    void consume_str(std::string &&) {}
+
+    ExampleMandA self1() { return *this; }              // return by value
+    ExampleMandA &self2() { return *this; }             // return by reference
+    const ExampleMandA &self3() const { return *this; } // return by const reference
+    ExampleMandA *self4() { return this; }              // return by pointer
+    const ExampleMandA *self5() const { return this; }  // return by const pointer
+
+    int internal1() const { return value; }        // return by value
+    int &internal2() { return value; }             // return by reference
+    const int &internal3() const { return value; } // return by const reference
+    int *internal4() { return &value; }            // return by pointer
+    const int *internal5() { return &value; }      // return by const pointer
+
+    py::str overloaded() { return "()"; }
+    py::str overloaded(int) { return "(int)"; }
+    py::str overloaded(int, float) { return "(int, float)"; }
+    py::str overloaded(float, int) { return "(float, int)"; }
+    py::str overloaded(int, int) { return "(int, int)"; }
     py::str overloaded(float, float) { return "(float, float)"; }
-    py::str overloaded(int)          const { return "(int) const"; }
-    py::str overloaded(int, float)   const { return "(int, float) const"; }
-    py::str overloaded(float, int)   const { return "(float, int) const"; }
-    py::str overloaded(int, int)     const { return "(int, int) const"; }
+    py::str overloaded(int) const { return "(int) const"; }
+    py::str overloaded(int, float) const { return "(int, float) const"; }
+    py::str overloaded(float, int) const { return "(float, int) const"; }
+    py::str overloaded(int, int) const { return "(int, int) const"; }
     py::str overloaded(float, float) const { return "(float, float) const"; }
 
     static py::str overloaded(float) { return "static float"; }
@@ -109,25 +115,40 @@ UserType TestPropRVP::sv1(1);
 UserType TestPropRVP::sv2(1);
 
 // Test None-allowed py::arg argument policy
-class NoneTester { public: int answer = 42; };
+class NoneTester {
+public:
+    int answer = 42;
+};
 int none1(const NoneTester &obj) { return obj.answer; }
 int none2(NoneTester *obj) { return obj ? obj->answer : -1; }
 int none3(std::shared_ptr<NoneTester> &obj) { return obj ? obj->answer : -1; }
 int none4(std::shared_ptr<NoneTester> *obj) { return obj && *obj ? (*obj)->answer : -1; }
-int none5(std::shared_ptr<NoneTester> obj) { return obj ? obj->answer : -1; }
+int none5(const std::shared_ptr<NoneTester> &obj) { return obj ? obj->answer : -1; }
+
+// Issue #2778: implicit casting from None to object (not pointer)
+class NoneCastTester {
+public:
+    int answer = -1;
+    NoneCastTester() = default;
+    explicit NoneCastTester(int v) : answer(v) {}
+};
 
 struct StrIssue {
     int val = -1;
 
     StrIssue() = default;
-    StrIssue(int i) : val{i} {}
+    explicit StrIssue(int i) : val{i} {}
 };
 
-// Issues #854, #910: incompatible function args when member function/pointer is in unregistered base class
+// Issues #854, #910: incompatible function args when member function/pointer is in unregistered
+// base class
 class UnregisteredBase {
 public:
     void do_nothing() const {}
-    void increase_value() { rw_value++; ro_value += 0.25; }
+    void increase_value() {
+        rw_value++;
+        ro_value += 0.25;
+    }
     void set_int(int v) { rw_value = v; }
     int get_int() const { return rw_value; }
     double get_double() const { return ro_value; }
@@ -148,13 +169,21 @@ struct RefQualified {
     int constRefQualified(int other) const & { return value + other; }
 };
 
+// Test rvalue ref param
+struct RValueRefParam {
+    std::size_t func1(std::string &&s) { return s.size(); }
+    std::size_t func2(std::string &&s) const { return s.size(); }
+    std::size_t func3(std::string &&s) & { return s.size(); }
+    std::size_t func4(std::string &&s) const & { return s.size(); }
+};
+
 TEST_SUBMODULE(methods_and_attributes, m) {
     // test_methods_and_attributes
     py::class_<ExampleMandA> emna(m, "ExampleMandA");
     emna.def(py::init<>())
         .def(py::init<int>())
-        .def(py::init<std::string&&>())
-        .def(py::init<const ExampleMandA&>())
+        .def(py::init<std::string &&>())
+        .def(py::init<const ExampleMandA &>())
         .def("add1", &ExampleMandA::add1)
         .def("add2", &ExampleMandA::add2)
         .def("add3", &ExampleMandA::add3)
@@ -179,16 +208,20 @@ TEST_SUBMODULE(methods_and_attributes, m) {
 #if defined(PYBIND11_OVERLOAD_CAST)
         .def("overloaded", py::overload_cast<>(&ExampleMandA::overloaded))
         .def("overloaded", py::overload_cast<int>(&ExampleMandA::overloaded))
-        .def("overloaded", py::overload_cast<int,   float>(&ExampleMandA::overloaded))
-        .def("overloaded", py::overload_cast<float,   int>(&ExampleMandA::overloaded))
-        .def("overloaded", py::overload_cast<int,     int>(&ExampleMandA::overloaded))
+        .def("overloaded", py::overload_cast<int, float>(&ExampleMandA::overloaded))
+        .def("overloaded", py::overload_cast<float, int>(&ExampleMandA::overloaded))
+        .def("overloaded", py::overload_cast<int, int>(&ExampleMandA::overloaded))
         .def("overloaded", py::overload_cast<float, float>(&ExampleMandA::overloaded))
         .def("overloaded_float", py::overload_cast<float, float>(&ExampleMandA::overloaded))
-        .def("overloaded_const", py::overload_cast<int         >(&ExampleMandA::overloaded, py::const_))
-        .def("overloaded_const", py::overload_cast<int,   float>(&ExampleMandA::overloaded, py::const_))
-        .def("overloaded_const", py::overload_cast<float,   int>(&ExampleMandA::overloaded, py::const_))
-        .def("overloaded_const", py::overload_cast<int,     int>(&ExampleMandA::overloaded, py::const_))
-        .def("overloaded_const", py::overload_cast<float, float>(&ExampleMandA::overloaded, py::const_))
+        .def("overloaded_const", py::overload_cast<int>(&ExampleMandA::overloaded, py::const_))
+        .def("overloaded_const",
+             py::overload_cast<int, float>(&ExampleMandA::overloaded, py::const_))
+        .def("overloaded_const",
+             py::overload_cast<float, int>(&ExampleMandA::overloaded, py::const_))
+        .def("overloaded_const",
+             py::overload_cast<int, int>(&ExampleMandA::overloaded, py::const_))
+        .def("overloaded_const",
+             py::overload_cast<float, float>(&ExampleMandA::overloaded, py::const_))
 #else
         // Use both the traditional static_cast method and the C++11 compatible overload_cast_
         .def("overloaded", overload_cast_<>()(&ExampleMandA::overloaded))
@@ -206,16 +239,29 @@ TEST_SUBMODULE(methods_and_attributes, m) {
 #endif
         // test_no_mixed_overloads
         // Raise error if trying to mix static/non-static overloads on the same name:
-        .def_static("add_mixed_overloads1", []() {
-            auto emna = py::reinterpret_borrow<py::class_<ExampleMandA>>(py::module_::import("pybind11_tests.methods_and_attributes").attr("ExampleMandA"));
-            emna.def       ("overload_mixed1", static_cast<py::str (ExampleMandA::*)(int, int)>(&ExampleMandA::overloaded))
-                .def_static("overload_mixed1", static_cast<py::str (              *)(float   )>(&ExampleMandA::overloaded));
-        })
-        .def_static("add_mixed_overloads2", []() {
-            auto emna = py::reinterpret_borrow<py::class_<ExampleMandA>>(py::module_::import("pybind11_tests.methods_and_attributes").attr("ExampleMandA"));
-            emna.def_static("overload_mixed2", static_cast<py::str (              *)(float   )>(&ExampleMandA::overloaded))
-                .def       ("overload_mixed2", static_cast<py::str (ExampleMandA::*)(int, int)>(&ExampleMandA::overloaded));
-        })
+        .def_static("add_mixed_overloads1",
+                    []() {
+                        auto emna = py::reinterpret_borrow<py::class_<ExampleMandA>>(
+                            py::module_::import("pybind11_tests.methods_and_attributes")
+                                .attr("ExampleMandA"));
+                        emna.def("overload_mixed1",
+                                 static_cast<py::str (ExampleMandA::*)(int, int)>(
+                                     &ExampleMandA::overloaded))
+                            .def_static(
+                                "overload_mixed1",
+                                static_cast<py::str (*)(float)>(&ExampleMandA::overloaded));
+                    })
+        .def_static("add_mixed_overloads2",
+                    []() {
+                        auto emna = py::reinterpret_borrow<py::class_<ExampleMandA>>(
+                            py::module_::import("pybind11_tests.methods_and_attributes")
+                                .attr("ExampleMandA"));
+                        emna.def_static("overload_mixed2",
+                                        static_cast<py::str (*)(float)>(&ExampleMandA::overloaded))
+                            .def("overload_mixed2",
+                                 static_cast<py::str (ExampleMandA::*)(int, int)>(
+                                     &ExampleMandA::overloaded));
+                    })
         .def("__str__", &ExampleMandA::toString)
         .def_readwrite("value", &ExampleMandA::value);
 
@@ -228,36 +274,41 @@ TEST_SUBMODULE(methods_and_attributes, m) {
         .def(py::init<>())
         .def_readonly("def_readonly", &TestProperties::value)
         .def_readwrite("def_readwrite", &TestProperties::value)
-        .def_property("def_writeonly", nullptr,
-                      [](TestProperties& s,int v) { s.value = v; } )
+        .def_property("def_writeonly", nullptr, [](TestProperties &s, int v) { s.value = v; })
         .def_property("def_property_writeonly", nullptr, &TestProperties::set)
         .def_property_readonly("def_property_readonly", &TestProperties::get)
         .def_property("def_property", &TestProperties::get, &TestProperties::set)
         .def_property("def_property_impossible", nullptr, nullptr)
         .def_readonly_static("def_readonly_static", &TestProperties::static_value)
         .def_readwrite_static("def_readwrite_static", &TestProperties::static_value)
-        .def_property_static("def_writeonly_static", nullptr,
-                             [](py::object, int v) { TestProperties::static_value = v; })
-        .def_property_readonly_static("def_property_readonly_static",
-                                      [](py::object) { return TestProperties::static_get(); })
-        .def_property_static("def_property_writeonly_static", nullptr,
-                             [](py::object, int v) { return TestProperties::static_set(v); })
-        .def_property_static("def_property_static",
-                             [](py::object) { return TestProperties::static_get(); },
-                             [](py::object, int v) { TestProperties::static_set(v); })
-        .def_property_static("static_cls",
-                             [](py::object cls) { return cls; },
-                             [](py::object cls, py::function f) { f(cls); });
+        .def_property_static("def_writeonly_static",
+                             nullptr,
+                             [](const py::object &, int v) { TestProperties::static_value = v; })
+        .def_property_readonly_static(
+            "def_property_readonly_static",
+            [](const py::object &) { return TestProperties::static_get(); })
+        .def_property_static(
+            "def_property_writeonly_static",
+            nullptr,
+            [](const py::object &, int v) { return TestProperties::static_set(v); })
+        .def_property_static(
+            "def_property_static",
+            [](const py::object &) { return TestProperties::static_get(); },
+            [](const py::object &, int v) { TestProperties::static_set(v); })
+        .def_property_static(
+            "static_cls",
+            [](py::object cls) { return cls; },
+            [](const py::object &cls, const py::function &f) { f(cls); });
 
     py::class_<TestPropertiesOverride, TestProperties>(m, "TestPropertiesOverride")
         .def(py::init<>())
         .def_readonly("def_readonly", &TestPropertiesOverride::value)
         .def_readonly_static("def_readonly_static", &TestPropertiesOverride::static_value);
 
-    auto static_get1 = [](py::object) -> const UserType & { return TestPropRVP::sv1; };
-    auto static_get2 = [](py::object) -> const UserType & { return TestPropRVP::sv2; };
-    auto static_set1 = [](py::object, int v) { TestPropRVP::sv1.set(v); };
-    auto static_set2 = [](py::object, int v) { TestPropRVP::sv2.set(v); };
+    auto static_get1 = [](const py::object &) -> const UserType & { return TestPropRVP::sv1; };
+    auto static_get2 = [](const py::object &) -> const UserType & { return TestPropRVP::sv2; };
+    auto static_set1 = [](const py::object &, int v) { TestPropRVP::sv1.set(v); };
+    auto static_set2 = [](const py::object &, int v) { TestPropRVP::sv2.set(v); };
     auto rvp_copy = py::return_value_policy::copy;
 
     // test_property_return_value_policies
@@ -268,85 +319,104 @@ TEST_SUBMODULE(methods_and_attributes, m) {
         .def_property_readonly("ro_func", py::cpp_function(&TestPropRVP::get2, rvp_copy))
         .def_property("rw_ref", &TestPropRVP::get1, &TestPropRVP::set1)
         .def_property("rw_copy", &TestPropRVP::get2, &TestPropRVP::set2, rvp_copy)
-        .def_property("rw_func", py::cpp_function(&TestPropRVP::get2, rvp_copy), &TestPropRVP::set2)
+        .def_property(
+            "rw_func", py::cpp_function(&TestPropRVP::get2, rvp_copy), &TestPropRVP::set2)
         .def_property_readonly_static("static_ro_ref", static_get1)
         .def_property_readonly_static("static_ro_copy", static_get2, rvp_copy)
         .def_property_readonly_static("static_ro_func", py::cpp_function(static_get2, rvp_copy))
         .def_property_static("static_rw_ref", static_get1, static_set1)
         .def_property_static("static_rw_copy", static_get2, static_set2, rvp_copy)
-        .def_property_static("static_rw_func", py::cpp_function(static_get2, rvp_copy), static_set2)
+        .def_property_static(
+            "static_rw_func", py::cpp_function(static_get2, rvp_copy), static_set2)
         // test_property_rvalue_policy
         .def_property_readonly("rvalue", &TestPropRVP::get_rvalue)
-        .def_property_readonly_static("static_rvalue", [](py::object) { return UserType(1); });
+        .def_property_readonly_static("static_rvalue",
+                                      [](const py::object &) { return UserType(1); });
 
     // test_metaclass_override
-    struct MetaclassOverride { };
+    struct MetaclassOverride {};
     py::class_<MetaclassOverride>(m, "MetaclassOverride", py::metaclass((PyObject *) &PyType_Type))
-        .def_property_readonly_static("readonly", [](py::object) { return 1; });
+        .def_property_readonly_static("readonly", [](const py::object &) { return 1; });
 
     // test_overload_ordering
-    m.def("overload_order", [](std::string) { return 1; });
-    m.def("overload_order", [](std::string) { return 2; });
+    m.def("overload_order", [](const std::string &) { return 1; });
+    m.def("overload_order", [](const std::string &) { return 2; });
     m.def("overload_order", [](int) { return 3; });
-    m.def("overload_order", [](int) { return 4; }, py::prepend{});
+    m.def(
+        "overload_order", [](int) { return 4; }, py::prepend{});
 
 #if !defined(PYPY_VERSION)
     // test_dynamic_attributes
     class DynamicClass {
     public:
         DynamicClass() { print_default_created(this); }
-        DynamicClass(const DynamicClass&) = delete;
+        DynamicClass(const DynamicClass &) = delete;
         ~DynamicClass() { print_destroyed(this); }
     };
-    py::class_<DynamicClass>(m, "DynamicClass", py::dynamic_attr())
-        .def(py::init());
+    py::class_<DynamicClass>(m, "DynamicClass", py::dynamic_attr()).def(py::init());
 
-    class CppDerivedDynamicClass : public DynamicClass { };
-    py::class_<CppDerivedDynamicClass, DynamicClass>(m, "CppDerivedDynamicClass")
-        .def(py::init());
+    class CppDerivedDynamicClass : public DynamicClass {};
+    py::class_<CppDerivedDynamicClass, DynamicClass>(m, "CppDerivedDynamicClass").def(py::init());
 #endif
 
     // test_bad_arg_default
     // Issue/PR #648: bad arg default debugging output
-#if !defined(NDEBUG)
-    m.attr("debug_enabled") = true;
+#if defined(PYBIND11_DETAILED_ERROR_MESSAGES)
+    m.attr("detailed_error_messages_enabled") = true;
 #else
-    m.attr("debug_enabled") = false;
+    m.attr("detailed_error_messages_enabled") = false;
 #endif
-    m.def("bad_arg_def_named", []{
+    m.def("bad_arg_def_named", [] {
         auto m = py::module_::import("pybind11_tests");
-        m.def("should_fail", [](int, UnregisteredType) {}, py::arg(), py::arg("a") = UnregisteredType());
+        m.def(
+            "should_fail",
+            [](int, UnregisteredType) {},
+            py::arg(),
+            py::arg("a") = UnregisteredType());
     });
-    m.def("bad_arg_def_unnamed", []{
+    m.def("bad_arg_def_unnamed", [] {
         auto m = py::module_::import("pybind11_tests");
-        m.def("should_fail", [](int, UnregisteredType) {}, py::arg(), py::arg() = UnregisteredType());
+        m.def(
+            "should_fail",
+            [](int, UnregisteredType) {},
+            py::arg(),
+            py::arg() = UnregisteredType());
     });
 
+    // [workaround(intel)] ICC 20/21 breaks with py::arg().stuff, using py::arg{}.stuff works.
+
     // test_accepts_none
-    py::class_<NoneTester, std::shared_ptr<NoneTester>>(m, "NoneTester")
-        .def(py::init<>());
-    m.def("no_none1", &none1, py::arg().none(false));
-    m.def("no_none2", &none2, py::arg().none(false));
-    m.def("no_none3", &none3, py::arg().none(false));
-    m.def("no_none4", &none4, py::arg().none(false));
-    m.def("no_none5", &none5, py::arg().none(false));
+    py::class_<NoneTester, std::shared_ptr<NoneTester>>(m, "NoneTester").def(py::init<>());
+    m.def("no_none1", &none1, py::arg{}.none(false));
+    m.def("no_none2", &none2, py::arg{}.none(false));
+    m.def("no_none3", &none3, py::arg{}.none(false));
+    m.def("no_none4", &none4, py::arg{}.none(false));
+    m.def("no_none5", &none5, py::arg{}.none(false));
     m.def("ok_none1", &none1);
-    m.def("ok_none2", &none2, py::arg().none(true));
+    m.def("ok_none2", &none2, py::arg{}.none(true));
     m.def("ok_none3", &none3);
-    m.def("ok_none4", &none4, py::arg().none(true));
+    m.def("ok_none4", &none4, py::arg{}.none(true));
     m.def("ok_none5", &none5);
 
-    m.def("no_none_kwarg", &none2, py::arg("a").none(false));
-    m.def("no_none_kwarg_kw_only", &none2, py::kw_only(), py::arg("a").none(false));
+    m.def("no_none_kwarg", &none2, "a"_a.none(false));
+    m.def("no_none_kwarg_kw_only", &none2, py::kw_only(), "a"_a.none(false));
+
+    // test_casts_none
+    // Issue #2778: implicit casting from None to object (not pointer)
+    py::class_<NoneCastTester>(m, "NoneCastTester")
+        .def(py::init<>())
+        .def(py::init<int>())
+        .def(py::init([](py::none const &) { return NoneCastTester{}; }));
+    py::implicitly_convertible<py::none, NoneCastTester>();
+    m.def("ok_obj_or_none", [](NoneCastTester const &foo) { return foo.answer; });
 
     // test_str_issue
     // Issue #283: __str__ called on uninitialized instance when constructor arguments invalid
     py::class_<StrIssue>(m, "StrIssue")
         .def(py::init<int>())
         .def(py::init<>())
-        .def("__str__", [](const StrIssue &si) {
-            return "StrIssue[" + std::to_string(si.val) + "]"; }
-        );
+        .def("__str__",
+             [](const StrIssue &si) { return "StrIssue[" + std::to_string(si.val) + "]"; });
 
     // test_unregistered_base_implementations
     //
@@ -360,16 +430,17 @@ TEST_SUBMODULE(methods_and_attributes, m) {
         .def("increase_value", &RegisteredDerived::increase_value)
         .def_readwrite("rw_value", &RegisteredDerived::rw_value)
         .def_readonly("ro_value", &RegisteredDerived::ro_value)
-        // These should trigger a static_assert if uncommented
-        //.def_readwrite("fails", &UserType::value) // should trigger a static_assert if uncommented
-        //.def_readonly("fails", &UserType::value) // should trigger a static_assert if uncommented
+        // Uncommenting the next line should trigger a static_assert:
+        // .def_readwrite("fails", &UserType::value)
+        // Uncommenting the next line should trigger a static_assert:
+        // .def_readonly("fails", &UserType::value)
         .def_property("rw_value_prop", &RegisteredDerived::get_int, &RegisteredDerived::set_int)
         .def_property_readonly("ro_value_prop", &RegisteredDerived::get_double)
         // This one is in the registered class:
-        .def("sum", &RegisteredDerived::sum)
-        ;
+        .def("sum", &RegisteredDerived::sum);
 
-    using Adapted = decltype(py::method_adaptor<RegisteredDerived>(&RegisteredDerived::do_nothing));
+    using Adapted
+        = decltype(py::method_adaptor<RegisteredDerived>(&RegisteredDerived::do_nothing));
     static_assert(std::is_same<Adapted, void (RegisteredDerived::*)() const>::value, "");
 
     // test_methods_and_attributes
@@ -378,4 +449,11 @@ TEST_SUBMODULE(methods_and_attributes, m) {
         .def_readonly("value", &RefQualified::value)
         .def("refQualified", &RefQualified::refQualified)
         .def("constRefQualified", &RefQualified::constRefQualified);
+
+    py::class_<RValueRefParam>(m, "RValueRefParam")
+        .def(py::init<>())
+        .def("func1", &RValueRefParam::func1)
+        .def("func2", &RValueRefParam::func2)
+        .def("func3", &RValueRefParam::func3)
+        .def("func4", &RValueRefParam::func4);
 }
diff --git a/3rdparty/pybind11/tests/test_methods_and_attributes.py b/3rdparty/pybind11/tests/test_methods_and_attributes.py
index 2aaf9331fd..0a2ae1239a 100644
--- a/3rdparty/pybind11/tests/test_methods_and_attributes.py
+++ b/3rdparty/pybind11/tests/test_methods_and_attributes.py
@@ -1,10 +1,20 @@
-# -*- coding: utf-8 -*-
+import sys
+
 import pytest
 
 import env  # noqa: F401
-
-from pybind11_tests import methods_and_attributes as m
 from pybind11_tests import ConstructorStats
+from pybind11_tests import methods_and_attributes as m
+
+NO_GETTER_MSG = (
+    "unreadable attribute" if sys.version_info < (3, 11) else "object has no getter"
+)
+NO_SETTER_MSG = (
+    "can't set attribute" if sys.version_info < (3, 11) else "object has no setter"
+)
+NO_DELETER_MSG = (
+    "can't delete attribute" if sys.version_info < (3, 11) else "object has no deleter"
+)
 
 
 def test_methods_and_attributes():
@@ -103,33 +113,33 @@ def test_properties():
     assert instance.def_property == 3
 
     with pytest.raises(AttributeError) as excinfo:
-        dummy = instance.def_property_writeonly  # noqa: F841 unused var
-    assert "unreadable attribute" in str(excinfo.value)
+        dummy = instance.def_property_writeonly  # unused var
+    assert NO_GETTER_MSG in str(excinfo.value)
 
     instance.def_property_writeonly = 4
     assert instance.def_property_readonly == 4
 
     with pytest.raises(AttributeError) as excinfo:
         dummy = instance.def_property_impossible  # noqa: F841 unused var
-    assert "unreadable attribute" in str(excinfo.value)
+    assert NO_GETTER_MSG in str(excinfo.value)
 
     with pytest.raises(AttributeError) as excinfo:
         instance.def_property_impossible = 5
-    assert "can't set attribute" in str(excinfo.value)
+    assert NO_SETTER_MSG in str(excinfo.value)
 
 
 def test_static_properties():
     assert m.TestProperties.def_readonly_static == 1
     with pytest.raises(AttributeError) as excinfo:
         m.TestProperties.def_readonly_static = 2
-    assert "can't set attribute" in str(excinfo.value)
+    assert NO_SETTER_MSG in str(excinfo.value)
 
     m.TestProperties.def_readwrite_static = 2
     assert m.TestProperties.def_readwrite_static == 2
 
     with pytest.raises(AttributeError) as excinfo:
-        dummy = m.TestProperties.def_writeonly_static  # noqa: F841 unused var
-    assert "unreadable attribute" in str(excinfo.value)
+        dummy = m.TestProperties.def_writeonly_static  # unused var
+    assert NO_GETTER_MSG in str(excinfo.value)
 
     m.TestProperties.def_writeonly_static = 3
     assert m.TestProperties.def_readonly_static == 3
@@ -137,14 +147,14 @@ def test_static_properties():
     assert m.TestProperties.def_property_readonly_static == 3
     with pytest.raises(AttributeError) as excinfo:
         m.TestProperties.def_property_readonly_static = 99
-    assert "can't set attribute" in str(excinfo.value)
+    assert NO_SETTER_MSG in str(excinfo.value)
 
     m.TestProperties.def_property_static = 4
     assert m.TestProperties.def_property_static == 4
 
     with pytest.raises(AttributeError) as excinfo:
         dummy = m.TestProperties.def_property_writeonly_static
-    assert "unreadable attribute" in str(excinfo.value)
+    assert NO_GETTER_MSG in str(excinfo.value)
 
     m.TestProperties.def_property_writeonly_static = 5
     assert m.TestProperties.def_property_static == 5
@@ -162,7 +172,7 @@ def test_static_properties():
 
     with pytest.raises(AttributeError) as excinfo:
         dummy = instance.def_property_writeonly_static  # noqa: F841 unused var
-    assert "unreadable attribute" in str(excinfo.value)
+    assert NO_GETTER_MSG in str(excinfo.value)
 
     instance.def_property_writeonly_static = 4
     assert instance.def_property_static == 4
@@ -182,7 +192,7 @@ def test_static_properties():
     properties_override = m.TestPropertiesOverride()
     with pytest.raises(AttributeError) as excinfo:
         del properties_override.def_readonly
-    assert "can't delete attribute" in str(excinfo.value)
+    assert NO_DELETER_MSG in str(excinfo.value)
 
 
 def test_static_cls():
@@ -218,15 +228,15 @@ def test_metaclass_override():
 
 
 def test_no_mixed_overloads():
-    from pybind11_tests import debug_enabled
+    from pybind11_tests import detailed_error_messages_enabled
 
     with pytest.raises(RuntimeError) as excinfo:
         m.ExampleMandA.add_mixed_overloads1()
     assert str(
         excinfo.value
     ) == "overloading a method with both static and instance methods is not supported; " + (
-        "compile in debug mode for more details"
-        if not debug_enabled
+        "#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for more details"
+        if not detailed_error_messages_enabled
         else "error while attempting to bind static method ExampleMandA.overload_mixed1"
         "(arg0: float) -> str"
     )
@@ -236,8 +246,8 @@ def test_no_mixed_overloads():
     assert str(
         excinfo.value
     ) == "overloading a method with both static and instance methods is not supported; " + (
-        "compile in debug mode for more details"
-        if not debug_enabled
+        "#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for more details"
+        if not detailed_error_messages_enabled
         else "error while attempting to bind instance method ExampleMandA.overload_mixed2"
         "(self: pybind11_tests.methods_and_attributes.ExampleMandA, arg0: int, arg1: int)"
         " -> str"
@@ -346,16 +356,16 @@ def test_cyclic_gc():
 
 
 def test_bad_arg_default(msg):
-    from pybind11_tests import debug_enabled
+    from pybind11_tests import detailed_error_messages_enabled
 
     with pytest.raises(RuntimeError) as excinfo:
         m.bad_arg_def_named()
     assert msg(excinfo.value) == (
         "arg(): could not convert default argument 'a: UnregisteredType' in function "
         "'should_fail' into a Python object (type not registered yet?)"
-        if debug_enabled
+        if detailed_error_messages_enabled
         else "arg(): could not convert default argument into a Python object (type not registered "
-        "yet?). Compile in debug mode for more information."
+        "yet?). #define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for more information."
     )
 
     with pytest.raises(RuntimeError) as excinfo:
@@ -363,9 +373,9 @@ def test_bad_arg_default(msg):
     assert msg(excinfo.value) == (
         "arg(): could not convert default argument 'UnregisteredType' in function "
         "'should_fail' into a Python object (type not registered yet?)"
-        if debug_enabled
+        if detailed_error_messages_enabled
         else "arg(): could not convert default argument into a Python object (type not registered "
-        "yet?). Compile in debug mode for more information."
+        "yet?). #define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for more information."
     )
 
 
@@ -431,6 +441,17 @@ def test_accepts_none(msg):
     assert "incompatible function arguments" in str(excinfo.value)
 
 
+def test_casts_none():
+    """#2778: implicit casting from None to object (not pointer)"""
+    a = m.NoneCastTester()
+    assert m.ok_obj_or_none(a) == -1
+    a = m.NoneCastTester(4)
+    assert m.ok_obj_or_none(a) == 4
+    a = m.NoneCastTester(None)
+    assert m.ok_obj_or_none(a) == -1
+    assert m.ok_obj_or_none(None) == -1
+
+
 def test_str_issue(msg):
     """#283: __str__ called on uninitialized instance when constructor arguments invalid"""
 
@@ -484,24 +505,23 @@ def test_overload_ordering():
     assert m.overload_order("string") == 1
     assert m.overload_order(0) == 4
 
-    # Different for Python 2 vs. 3
-    uni_name = type(u"").__name__
-
     assert "1. overload_order(arg0: int) -> int" in m.overload_order.__doc__
-    assert (
-        "2. overload_order(arg0: {}) -> int".format(uni_name)
-        in m.overload_order.__doc__
-    )
-    assert (
-        "3. overload_order(arg0: {}) -> int".format(uni_name)
-        in m.overload_order.__doc__
-    )
+    assert "2. overload_order(arg0: str) -> int" in m.overload_order.__doc__
+    assert "3. overload_order(arg0: str) -> int" in m.overload_order.__doc__
     assert "4. overload_order(arg0: int) -> int" in m.overload_order.__doc__
 
     with pytest.raises(TypeError) as err:
         m.overload_order(1.1)
 
     assert "1. (arg0: int) -> int" in str(err.value)
-    assert "2. (arg0: {}) -> int".format(uni_name) in str(err.value)
-    assert "3. (arg0: {}) -> int".format(uni_name) in str(err.value)
+    assert "2. (arg0: str) -> int" in str(err.value)
+    assert "3. (arg0: str) -> int" in str(err.value)
     assert "4. (arg0: int) -> int" in str(err.value)
+
+
+def test_rvalue_ref_param():
+    r = m.RValueRefParam()
+    assert r.func1("123") == 3
+    assert r.func2("1234") == 4
+    assert r.func3("12345") == 5
+    assert r.func4("123456") == 6
diff --git a/3rdparty/pybind11/tests/test_modules.cpp b/3rdparty/pybind11/tests/test_modules.cpp
index 67387e809b..18a7ec74cc 100644
--- a/3rdparty/pybind11/tests/test_modules.cpp
+++ b/3rdparty/pybind11/tests/test_modules.cpp
@@ -8,8 +8,8 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include "constructor_stats.h"
+#include "pybind11_tests.h"
 
 TEST_SUBMODULE(modules, m) {
     // test_nested_modules
@@ -20,24 +20,32 @@ TEST_SUBMODULE(modules, m) {
     // test_reference_internal
     class A {
     public:
-        A(int v) : v(v) { print_created(this, v); }
+        explicit A(int v) : v(v) { print_created(this, v); }
         ~A() { print_destroyed(this); }
-        A(const A&) { print_copy_created(this); }
-        A& operator=(const A &copy) { print_copy_assigned(this); v = copy.v; return *this; }
-        std::string toString() { return "A[" + std::to_string(v) + "]"; }
+        A(const A &) { print_copy_created(this); }
+        A &operator=(const A &copy) {
+            print_copy_assigned(this);
+            v = copy.v;
+            return *this;
+        }
+        std::string toString() const { return "A[" + std::to_string(v) + "]"; }
+
     private:
         int v;
     };
-    py::class_<A>(m_sub, "A")
-        .def(py::init<int>())
-        .def("__repr__", &A::toString);
+    py::class_<A>(m_sub, "A").def(py::init<int>()).def("__repr__", &A::toString);
 
     class B {
     public:
         B() { print_default_created(this); }
         ~B() { print_destroyed(this); }
-        B(const B&) { print_copy_created(this); }
-        B& operator=(const B &copy) { print_copy_assigned(this); a1 = copy.a1; a2 = copy.a2; return *this; }
+        B(const B &) { print_copy_created(this); }
+        B &operator=(const B &copy) {
+            print_copy_assigned(this);
+            a1 = copy.a1;
+            a2 = copy.a2;
+            return *this;
+        }
         A &get_a1() { return a1; }
         A &get_a2() { return a2; }
 
@@ -46,9 +54,16 @@ TEST_SUBMODULE(modules, m) {
     };
     py::class_<B>(m_sub, "B")
         .def(py::init<>())
-        .def("get_a1", &B::get_a1, "Return the internal A 1", py::return_value_policy::reference_internal)
-        .def("get_a2", &B::get_a2, "Return the internal A 2", py::return_value_policy::reference_internal)
-        .def_readwrite("a1", &B::a1)  // def_readonly uses an internal reference return policy by default
+        .def("get_a1",
+             &B::get_a1,
+             "Return the internal A 1",
+             py::return_value_policy::reference_internal)
+        .def("get_a2",
+             &B::get_a2,
+             "Return the internal A 2",
+             py::return_value_policy::reference_internal)
+        .def_readwrite("a1", &B::a1) // def_readonly uses an internal
+                                     // reference return policy by default
         .def_readwrite("a2", &B::a2);
 
     // This is intentionally "py::module" to verify it still can be used in place of "py::module_"
@@ -57,13 +72,14 @@ TEST_SUBMODULE(modules, m) {
     // test_duplicate_registration
     // Registering two things with the same name
     m.def("duplicate_registration", []() {
-        class Dupe1 { };
-        class Dupe2 { };
-        class Dupe3 { };
-        class DupeException { };
+        class Dupe1 {};
+        class Dupe2 {};
+        class Dupe3 {};
+        class DupeException {};
 
         // Go ahead and leak, until we have a non-leaking py::module_ constructor
-        auto dm = py::module_::create_extension_module("dummy", nullptr, new py::module_::module_def);
+        auto dm
+            = py::module_::create_extension_module("dummy", nullptr, new py::module_::module_def);
         auto failures = py::list();
 
         py::class_<Dupe1>(dm, "Dupe1");
@@ -74,28 +90,36 @@ TEST_SUBMODULE(modules, m) {
         try {
             py::class_<Dupe1>(dm, "Dupe1");
             failures.append("Dupe1 class");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
         try {
             dm.def("Dupe1", []() { return Dupe1(); });
             failures.append("Dupe1 function");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
         try {
             py::class_<Dupe3>(dm, "dupe1_factory");
             failures.append("dupe1_factory");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
         try {
             py::exception<Dupe3>(dm, "Dupe2");
             failures.append("Dupe2");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
         try {
             dm.def("DupeException", []() { return 30; });
             failures.append("DupeException1");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
         try {
             py::class_<DupeException>(dm, "DupeException");
             failures.append("DupeException2");
-        } catch (std::runtime_error &) {}
+        } catch (std::runtime_error &) {
+        }
 
         return failures;
     });
+
+    m.def("def_submodule", [](py::module_ m, const char *name) { return m.def_submodule(name); });
 }
diff --git a/3rdparty/pybind11/tests/test_modules.py b/3rdparty/pybind11/tests/test_modules.py
index 5630ccf9b3..e11d68e78e 100644
--- a/3rdparty/pybind11/tests/test_modules.py
+++ b/3rdparty/pybind11/tests/test_modules.py
@@ -1,7 +1,9 @@
-# -*- coding: utf-8 -*-
+import pytest
+
+import env
+from pybind11_tests import ConstructorStats
 from pybind11_tests import modules as m
 from pybind11_tests.modules import subsubmodule as ms
-from pybind11_tests import ConstructorStats
 
 
 def test_nested_modules():
@@ -54,18 +56,20 @@ def test_reference_internal():
 
 
 def test_importing():
-    from pybind11_tests.modules import OD
     from collections import OrderedDict
 
+    from pybind11_tests.modules import OD
+
     assert OD is OrderedDict
     assert str(OD([(1, "a"), (2, "b")])) == "OrderedDict([(1, 'a'), (2, 'b')])"
 
 
 def test_pydoc():
     """Pydoc needs to be able to provide help() for everything inside a pybind11 module"""
-    import pybind11_tests
     import pydoc
 
+    import pybind11_tests
+
     assert pybind11_tests.__name__ == "pybind11_tests"
     assert pybind11_tests.__doc__ == "pybind11 test module"
     assert pydoc.text.docmodule(pybind11_tests)
@@ -75,3 +79,43 @@ def test_duplicate_registration():
     """Registering two things with the same name"""
 
     assert m.duplicate_registration() == []
+
+
+def test_builtin_key_type():
+    """Test that all the keys in the builtin modules have type str.
+
+    Previous versions of pybind11 would add a unicode key in python 2.
+    """
+    if hasattr(__builtins__, "keys"):
+        keys = __builtins__.keys()
+    else:  # this is to make pypy happy since builtins is different there.
+        keys = __builtins__.__dict__.keys()
+
+    assert {type(k) for k in keys} == {str}
+
+
+@pytest.mark.xfail("env.PYPY", reason="PyModule_GetName()")
+def test_def_submodule_failures():
+    sm = m.def_submodule(m, b"ScratchSubModuleName")  # Using bytes to show it works.
+    assert sm.__name__ == m.__name__ + "." + "ScratchSubModuleName"
+    malformed_utf8 = b"\x80"
+    if env.PYPY:
+        # It is not worth the effort finding a trigger for a failure when running with PyPy.
+        pytest.skip("Sufficiently exercised on platforms other than PyPy.")
+    else:
+        # Meant to trigger PyModule_GetName() failure:
+        sm_name_orig = sm.__name__
+        sm.__name__ = malformed_utf8
+        try:
+            with pytest.raises(Exception):
+                # Seen with Python 3.9: SystemError: nameless module
+                # But we do not want to exercise the internals of PyModule_GetName(), which could
+                # change in future versions of Python, but a bad __name__ is very likely to cause
+                # some kind of failure indefinitely.
+                m.def_submodule(sm, b"SubSubModuleName")
+        finally:
+            # Clean up to ensure nothing gets upset by a module with an invalid __name__.
+            sm.__name__ = sm_name_orig  # Purely precautionary.
+    # Meant to trigger PyImport_AddModule() failure:
+    with pytest.raises(UnicodeDecodeError):
+        m.def_submodule(sm, malformed_utf8)
diff --git a/3rdparty/pybind11/tests/test_multiple_inheritance.cpp b/3rdparty/pybind11/tests/test_multiple_inheritance.cpp
index e67200809d..5916ae9010 100644
--- a/3rdparty/pybind11/tests/test_multiple_inheritance.cpp
+++ b/3rdparty/pybind11/tests/test_multiple_inheritance.cpp
@@ -8,13 +8,16 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include "constructor_stats.h"
+#include "pybind11_tests.h"
+
+namespace {
 
 // Many bases for testing that multiple inheritance from many classes (i.e. requiring extra
 // space for holder constructed flags) works.
-template <int N> struct BaseN {
-    BaseN(int i) : i(i) { }
+template <int N>
+struct BaseN {
+    explicit BaseN(int i) : i(i) {}
     int i;
 };
 
@@ -43,103 +46,139 @@ int WithStatic2::static_value2 = 2;
 int VanillaStaticMix1::static_value = 12;
 int VanillaStaticMix2::static_value = 12;
 
+// test_multiple_inheritance_virtbase
+struct Base1a {
+    explicit Base1a(int i) : i(i) {}
+    int foo() const { return i; }
+    int i;
+};
+struct Base2a {
+    explicit Base2a(int i) : i(i) {}
+    int bar() const { return i; }
+    int i;
+};
+struct Base12a : Base1a, Base2a {
+    Base12a(int i, int j) : Base1a(i), Base2a(j) {}
+};
+
+// test_mi_unaligned_base
+// test_mi_base_return
+struct I801B1 {
+    int a = 1;
+    I801B1() = default;
+    I801B1(const I801B1 &) = default;
+    virtual ~I801B1() = default;
+};
+struct I801B2 {
+    int b = 2;
+    I801B2() = default;
+    I801B2(const I801B2 &) = default;
+    virtual ~I801B2() = default;
+};
+struct I801C : I801B1, I801B2 {};
+struct I801D : I801C {}; // Indirect MI
+
+} // namespace
+
 TEST_SUBMODULE(multiple_inheritance, m) {
+    // Please do not interleave `struct` and `class` definitions with bindings code,
+    // but implement `struct`s and `class`es in the anonymous namespace above.
+    // This helps keeping the smart_holder branch in sync with master.
 
     // test_multiple_inheritance_mix1
     // test_multiple_inheritance_mix2
     struct Base1 {
-        Base1(int i) : i(i) { }
-        int foo() { return i; }
+        explicit Base1(int i) : i(i) {}
+        int foo() const { return i; }
         int i;
     };
     py::class_<Base1> b1(m, "Base1");
-    b1.def(py::init<int>())
-      .def("foo", &Base1::foo);
+    b1.def(py::init<int>()).def("foo", &Base1::foo);
 
     struct Base2 {
-        Base2(int i) : i(i) { }
-        int bar() { return i; }
+        explicit Base2(int i) : i(i) {}
+        int bar() const { return i; }
         int i;
     };
     py::class_<Base2> b2(m, "Base2");
-    b2.def(py::init<int>())
-      .def("bar", &Base2::bar);
-
+    b2.def(py::init<int>()).def("bar", &Base2::bar);
 
     // test_multiple_inheritance_cpp
     struct Base12 : Base1, Base2 {
-        Base12(int i, int j) : Base1(i), Base2(j) { }
+        Base12(int i, int j) : Base1(i), Base2(j) {}
     };
     struct MIType : Base12 {
-        MIType(int i, int j) : Base12(i, j) { }
+        MIType(int i, int j) : Base12(i, j) {}
     };
     py::class_<Base12, Base1, Base2>(m, "Base12");
-    py::class_<MIType, Base12>(m, "MIType")
-        .def(py::init<int, int>());
-
+    py::class_<MIType, Base12>(m, "MIType").def(py::init<int, int>());
 
     // test_multiple_inheritance_python_many_bases
-    #define PYBIND11_BASEN(N) py::class_<BaseN<N>>(m, "BaseN" #N).def(py::init<int>()).def("f" #N, [](BaseN<N> &b) { return b.i + N; })
-    PYBIND11_BASEN( 1); PYBIND11_BASEN( 2); PYBIND11_BASEN( 3); PYBIND11_BASEN( 4);
-    PYBIND11_BASEN( 5); PYBIND11_BASEN( 6); PYBIND11_BASEN( 7); PYBIND11_BASEN( 8);
-    PYBIND11_BASEN( 9); PYBIND11_BASEN(10); PYBIND11_BASEN(11); PYBIND11_BASEN(12);
-    PYBIND11_BASEN(13); PYBIND11_BASEN(14); PYBIND11_BASEN(15); PYBIND11_BASEN(16);
+#define PYBIND11_BASEN(N)                                                                         \
+    py::class_<BaseN<(N)>>(m, "BaseN" #N).def(py::init<int>()).def("f" #N, [](BaseN<N> &b) {      \
+        return b.i + (N);                                                                         \
+    })
+    PYBIND11_BASEN(1);
+    PYBIND11_BASEN(2);
+    PYBIND11_BASEN(3);
+    PYBIND11_BASEN(4);
+    PYBIND11_BASEN(5);
+    PYBIND11_BASEN(6);
+    PYBIND11_BASEN(7);
+    PYBIND11_BASEN(8);
+    PYBIND11_BASEN(9);
+    PYBIND11_BASEN(10);
+    PYBIND11_BASEN(11);
+    PYBIND11_BASEN(12);
+    PYBIND11_BASEN(13);
+    PYBIND11_BASEN(14);
+    PYBIND11_BASEN(15);
+    PYBIND11_BASEN(16);
     PYBIND11_BASEN(17);
 
     // Uncommenting this should result in a compile time failure (MI can only be specified via
-    // template parameters because pybind has to know the types involved; see discussion in #742 for
-    // details).
-//    struct Base12v2 : Base1, Base2 {
-//        Base12v2(int i, int j) : Base1(i), Base2(j) { }
-//    };
-//    py::class_<Base12v2>(m, "Base12v2", b1, b2)
-//        .def(py::init<int, int>());
-
+    // template parameters because pybind has to know the types involved; see discussion in #742
+    // for details).
+    //    struct Base12v2 : Base1, Base2 {
+    //        Base12v2(int i, int j) : Base1(i), Base2(j) { }
+    //    };
+    //    py::class_<Base12v2>(m, "Base12v2", b1, b2)
+    //        .def(py::init<int, int>());
 
     // test_multiple_inheritance_virtbase
     // Test the case where not all base classes are specified, and where pybind11 requires the
     // py::multiple_inheritance flag to perform proper casting between types.
-    struct Base1a {
-        Base1a(int i) : i(i) { }
-        int foo() { return i; }
-        int i;
-    };
     py::class_<Base1a, std::shared_ptr<Base1a>>(m, "Base1a")
         .def(py::init<int>())
         .def("foo", &Base1a::foo);
 
-    struct Base2a {
-        Base2a(int i) : i(i) { }
-        int bar() { return i; }
-        int i;
-    };
     py::class_<Base2a, std::shared_ptr<Base2a>>(m, "Base2a")
         .def(py::init<int>())
         .def("bar", &Base2a::bar);
 
-    struct Base12a : Base1a, Base2a {
-        Base12a(int i, int j) : Base1a(i), Base2a(j) { }
-    };
-    py::class_<Base12a, /* Base1 missing */ Base2a,
-               std::shared_ptr<Base12a>>(m, "Base12a", py::multiple_inheritance())
+    py::class_<Base12a, /* Base1 missing */ Base2a, std::shared_ptr<Base12a>>(
+        m, "Base12a", py::multiple_inheritance())
         .def(py::init<int, int>());
 
     m.def("bar_base2a", [](Base2a *b) { return b->bar(); });
-    m.def("bar_base2a_sharedptr", [](std::shared_ptr<Base2a> b) { return b->bar(); });
+    m.def("bar_base2a_sharedptr", [](const std::shared_ptr<Base2a> &b) { return b->bar(); });
 
     // test_mi_unaligned_base
     // test_mi_base_return
     // Issue #801: invalid casting to derived type with MI bases
-    struct I801B1 { int a = 1; I801B1() = default; I801B1(const I801B1 &) = default; virtual ~I801B1() = default; };
-    struct I801B2 { int b = 2; I801B2() = default; I801B2(const I801B2 &) = default; virtual ~I801B2() = default; };
-    struct I801C : I801B1, I801B2 {};
-    struct I801D : I801C {}; // Indirect MI
     // Unregistered classes:
-    struct I801B3 { int c = 3; virtual ~I801B3() = default; };
+    struct I801B3 {
+        int c = 3;
+        virtual ~I801B3() = default;
+    };
     struct I801E : I801B3, I801D {};
 
-    py::class_<I801B1, std::shared_ptr<I801B1>>(m, "I801B1").def(py::init<>()).def_readonly("a", &I801B1::a);
-    py::class_<I801B2, std::shared_ptr<I801B2>>(m, "I801B2").def(py::init<>()).def_readonly("b", &I801B2::b);
+    py::class_<I801B1, std::shared_ptr<I801B1>>(m, "I801B1")
+        .def(py::init<>())
+        .def_readonly("a", &I801B1::a);
+    py::class_<I801B2, std::shared_ptr<I801B2>>(m, "I801B2")
+        .def(py::init<>())
+        .def_readonly("b", &I801B2::b);
     py::class_<I801C, I801B1, I801B2, std::shared_ptr<I801C>>(m, "I801C").def(py::init<>());
     py::class_<I801D, I801C, std::shared_ptr<I801D>>(m, "I801D").def(py::init<>());
 
@@ -164,11 +203,8 @@ TEST_SUBMODULE(multiple_inheritance, m) {
     m.def("i801e_c", []() -> I801C * { return new I801E(); });
     m.def("i801e_b2", []() -> I801B2 * { return new I801E(); });
 
-
     // test_mi_static_properties
-    py::class_<Vanilla>(m, "Vanilla")
-        .def(py::init<>())
-        .def("vanilla", &Vanilla::vanilla);
+    py::class_<Vanilla>(m, "Vanilla").def(py::init<>()).def("vanilla", &Vanilla::vanilla);
 
     py::class_<WithStatic1>(m, "WithStatic1")
         .def(py::init<>())
@@ -180,22 +216,19 @@ TEST_SUBMODULE(multiple_inheritance, m) {
         .def_static("static_func2", &WithStatic2::static_func2)
         .def_readwrite_static("static_value2", &WithStatic2::static_value2);
 
-    py::class_<VanillaStaticMix1, Vanilla, WithStatic1, WithStatic2>(
-        m, "VanillaStaticMix1")
+    py::class_<VanillaStaticMix1, Vanilla, WithStatic1, WithStatic2>(m, "VanillaStaticMix1")
         .def(py::init<>())
         .def_static("static_func", &VanillaStaticMix1::static_func)
         .def_readwrite_static("static_value", &VanillaStaticMix1::static_value);
 
-    py::class_<VanillaStaticMix2, WithStatic1, Vanilla, WithStatic2>(
-        m, "VanillaStaticMix2")
+    py::class_<VanillaStaticMix2, WithStatic1, Vanilla, WithStatic2>(m, "VanillaStaticMix2")
         .def(py::init<>())
         .def_static("static_func", &VanillaStaticMix2::static_func)
         .def_readwrite_static("static_value", &VanillaStaticMix2::static_value);
 
-
-    struct WithDict { };
-    struct VanillaDictMix1 : Vanilla, WithDict { };
-    struct VanillaDictMix2 : WithDict, Vanilla { };
+    struct WithDict {};
+    struct VanillaDictMix1 : Vanilla, WithDict {};
+    struct VanillaDictMix2 : WithDict, Vanilla {};
     py::class_<WithDict>(m, "WithDict", py::dynamic_attr()).def(py::init<>());
     py::class_<VanillaDictMix1, Vanilla, WithDict>(m, "VanillaDictMix1").def(py::init<>());
     py::class_<VanillaDictMix2, WithDict, Vanilla>(m, "VanillaDictMix2").def(py::init<>());
@@ -203,16 +236,106 @@ TEST_SUBMODULE(multiple_inheritance, m) {
     // test_diamond_inheritance
     // Issue #959: segfault when constructing diamond inheritance instance
     // All of these have int members so that there will be various unequal pointers involved.
-    struct B { int b; B() = default; B(const B&) = default; virtual ~B() = default; };
-    struct C0 : public virtual B { int c0; };
-    struct C1 : public virtual B { int c1; };
-    struct D : public C0, public C1 { int d; };
-    py::class_<B>(m, "B")
-        .def("b", [](B *self) { return self; });
-    py::class_<C0, B>(m, "C0")
-        .def("c0", [](C0 *self) { return self; });
-    py::class_<C1, B>(m, "C1")
-        .def("c1", [](C1 *self) { return self; });
-    py::class_<D, C0, C1>(m, "D")
-        .def(py::init<>());
+    struct B {
+        int b;
+        B() = default;
+        B(const B &) = default;
+        virtual ~B() = default;
+    };
+    struct C0 : public virtual B {
+        int c0;
+    };
+    struct C1 : public virtual B {
+        int c1;
+    };
+    struct D : public C0, public C1 {
+        int d;
+    };
+    py::class_<B>(m, "B").def("b", [](B *self) { return self; });
+    py::class_<C0, B>(m, "C0").def("c0", [](C0 *self) { return self; });
+    py::class_<C1, B>(m, "C1").def("c1", [](C1 *self) { return self; });
+    py::class_<D, C0, C1>(m, "D").def(py::init<>());
+
+    // test_pr3635_diamond_*
+    // - functions are get_{base}_{var}, return {var}
+    struct MVB {
+        MVB() = default;
+        MVB(const MVB &) = default;
+        virtual ~MVB() = default;
+
+        int b = 1;
+        int get_b_b() const { return b; }
+    };
+    struct MVC : virtual MVB {
+        int c = 2;
+        int get_c_b() const { return b; }
+        int get_c_c() const { return c; }
+    };
+    struct MVD0 : virtual MVC {
+        int d0 = 3;
+        int get_d0_b() const { return b; }
+        int get_d0_c() const { return c; }
+        int get_d0_d0() const { return d0; }
+    };
+    struct MVD1 : virtual MVC {
+        int d1 = 4;
+        int get_d1_b() const { return b; }
+        int get_d1_c() const { return c; }
+        int get_d1_d1() const { return d1; }
+    };
+    struct MVE : virtual MVD0, virtual MVD1 {
+        int e = 5;
+        int get_e_b() const { return b; }
+        int get_e_c() const { return c; }
+        int get_e_d0() const { return d0; }
+        int get_e_d1() const { return d1; }
+        int get_e_e() const { return e; }
+    };
+    struct MVF : virtual MVE {
+        int f = 6;
+        int get_f_b() const { return b; }
+        int get_f_c() const { return c; }
+        int get_f_d0() const { return d0; }
+        int get_f_d1() const { return d1; }
+        int get_f_e() const { return e; }
+        int get_f_f() const { return f; }
+    };
+    py::class_<MVB>(m, "MVB")
+        .def(py::init<>())
+        .def("get_b_b", &MVB::get_b_b)
+        .def_readwrite("b", &MVB::b);
+    py::class_<MVC, MVB>(m, "MVC")
+        .def(py::init<>())
+        .def("get_c_b", &MVC::get_c_b)
+        .def("get_c_c", &MVC::get_c_c)
+        .def_readwrite("c", &MVC::c);
+    py::class_<MVD0, MVC>(m, "MVD0")
+        .def(py::init<>())
+        .def("get_d0_b", &MVD0::get_d0_b)
+        .def("get_d0_c", &MVD0::get_d0_c)
+        .def("get_d0_d0", &MVD0::get_d0_d0)
+        .def_readwrite("d0", &MVD0::d0);
+    py::class_<MVD1, MVC>(m, "MVD1")
+        .def(py::init<>())
+        .def("get_d1_b", &MVD1::get_d1_b)
+        .def("get_d1_c", &MVD1::get_d1_c)
+        .def("get_d1_d1", &MVD1::get_d1_d1)
+        .def_readwrite("d1", &MVD1::d1);
+    py::class_<MVE, MVD0, MVD1>(m, "MVE")
+        .def(py::init<>())
+        .def("get_e_b", &MVE::get_e_b)
+        .def("get_e_c", &MVE::get_e_c)
+        .def("get_e_d0", &MVE::get_e_d0)
+        .def("get_e_d1", &MVE::get_e_d1)
+        .def("get_e_e", &MVE::get_e_e)
+        .def_readwrite("e", &MVE::e);
+    py::class_<MVF, MVE>(m, "MVF")
+        .def(py::init<>())
+        .def("get_f_b", &MVF::get_f_b)
+        .def("get_f_c", &MVF::get_f_c)
+        .def("get_f_d0", &MVF::get_f_d0)
+        .def("get_f_d1", &MVF::get_f_d1)
+        .def("get_f_e", &MVF::get_f_e)
+        .def("get_f_f", &MVF::get_f_f)
+        .def_readwrite("f", &MVF::f);
 }
diff --git a/3rdparty/pybind11/tests/test_multiple_inheritance.py b/3rdparty/pybind11/tests/test_multiple_inheritance.py
index e6a7f9762b..3a1d88d711 100644
--- a/3rdparty/pybind11/tests/test_multiple_inheritance.py
+++ b/3rdparty/pybind11/tests/test_multiple_inheritance.py
@@ -1,8 +1,6 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
-
 from pybind11_tests import ConstructorStats
 from pybind11_tests import multiple_inheritance as m
 
@@ -14,8 +12,7 @@ def test_multiple_inheritance_cpp():
     assert mt.bar() == 4
 
 
-@pytest.mark.skipif("env.PYPY and env.PY2")
-@pytest.mark.xfail("env.PYPY and not env.PY2")
+@pytest.mark.xfail("env.PYPY")
 def test_multiple_inheritance_mix1():
     class Base1:
         def __init__(self, i):
@@ -54,15 +51,14 @@ def __init__(self, i, j):
     assert mt.bar() == 4
 
 
-@pytest.mark.skipif("env.PYPY and env.PY2")
-@pytest.mark.xfail("env.PYPY and not env.PY2")
+@pytest.mark.xfail("env.PYPY")
 def test_multiple_inheritance_python():
     class MI1(m.Base1, m.Base2):
         def __init__(self, i, j):
             m.Base1.__init__(self, i)
             m.Base2.__init__(self, j)
 
-    class B1(object):
+    class B1:
         def v(self):
             return 1
 
@@ -97,7 +93,7 @@ class B2(B1):
         def v(self):
             return 2
 
-    class B3(object):
+    class B3:
         def v(self):
             return 3
 
@@ -359,3 +355,139 @@ def test_diamond_inheritance():
     assert d is d.c0().b()
     assert d is d.c1().b()
     assert d is d.c0().c1().b().c0().b()
+
+
+def test_pr3635_diamond_b():
+    o = m.MVB()
+    assert o.b == 1
+
+    assert o.get_b_b() == 1
+
+
+def test_pr3635_diamond_c():
+    o = m.MVC()
+    assert o.b == 1
+    assert o.c == 2
+
+    assert o.get_b_b() == 1
+    assert o.get_c_b() == 1
+
+    assert o.get_c_c() == 2
+
+
+def test_pr3635_diamond_d0():
+    o = m.MVD0()
+    assert o.b == 1
+    assert o.c == 2
+    assert o.d0 == 3
+
+    assert o.get_b_b() == 1
+    assert o.get_c_b() == 1
+    assert o.get_d0_b() == 1
+
+    assert o.get_c_c() == 2
+    assert o.get_d0_c() == 2
+
+    assert o.get_d0_d0() == 3
+
+
+def test_pr3635_diamond_d1():
+    o = m.MVD1()
+    assert o.b == 1
+    assert o.c == 2
+    assert o.d1 == 4
+
+    assert o.get_b_b() == 1
+    assert o.get_c_b() == 1
+    assert o.get_d1_b() == 1
+
+    assert o.get_c_c() == 2
+    assert o.get_d1_c() == 2
+
+    assert o.get_d1_d1() == 4
+
+
+def test_pr3635_diamond_e():
+    o = m.MVE()
+    assert o.b == 1
+    assert o.c == 2
+    assert o.d0 == 3
+    assert o.d1 == 4
+    assert o.e == 5
+
+    assert o.get_b_b() == 1
+    assert o.get_c_b() == 1
+    assert o.get_d0_b() == 1
+    assert o.get_d1_b() == 1
+    assert o.get_e_b() == 1
+
+    assert o.get_c_c() == 2
+    assert o.get_d0_c() == 2
+    assert o.get_d1_c() == 2
+    assert o.get_e_c() == 2
+
+    assert o.get_d0_d0() == 3
+    assert o.get_e_d0() == 3
+
+    assert o.get_d1_d1() == 4
+    assert o.get_e_d1() == 4
+
+    assert o.get_e_e() == 5
+
+
+def test_pr3635_diamond_f():
+    o = m.MVF()
+    assert o.b == 1
+    assert o.c == 2
+    assert o.d0 == 3
+    assert o.d1 == 4
+    assert o.e == 5
+    assert o.f == 6
+
+    assert o.get_b_b() == 1
+    assert o.get_c_b() == 1
+    assert o.get_d0_b() == 1
+    assert o.get_d1_b() == 1
+    assert o.get_e_b() == 1
+    assert o.get_f_b() == 1
+
+    assert o.get_c_c() == 2
+    assert o.get_d0_c() == 2
+    assert o.get_d1_c() == 2
+    assert o.get_e_c() == 2
+    assert o.get_f_c() == 2
+
+    assert o.get_d0_d0() == 3
+    assert o.get_e_d0() == 3
+    assert o.get_f_d0() == 3
+
+    assert o.get_d1_d1() == 4
+    assert o.get_e_d1() == 4
+    assert o.get_f_d1() == 4
+
+    assert o.get_e_e() == 5
+    assert o.get_f_e() == 5
+
+    assert o.get_f_f() == 6
+
+
+def test_python_inherit_from_mi():
+    """Tests extending a Python class from a single inheritor of a MI class"""
+
+    class PyMVF(m.MVF):
+        g = 7
+
+        def get_g_g(self):
+            return self.g
+
+    o = PyMVF()
+
+    assert o.b == 1
+    assert o.c == 2
+    assert o.d0 == 3
+    assert o.d1 == 4
+    assert o.e == 5
+    assert o.f == 6
+    assert o.g == 7
+
+    assert o.get_g_g() == 7
diff --git a/3rdparty/pybind11/tests/test_numpy_array.cpp b/3rdparty/pybind11/tests/test_numpy_array.cpp
index a84de77f8e..69ddbe1ef2 100644
--- a/3rdparty/pybind11/tests/test_numpy_array.cpp
+++ b/3rdparty/pybind11/tests/test_numpy_array.cpp
@@ -7,12 +7,13 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-
 #include <pybind11/numpy.h>
 #include <pybind11/stl.h>
 
+#include "pybind11_tests.h"
+
 #include <cstdint>
+#include <utility>
 
 // Size / dtype checks.
 struct DtypeCheck {
@@ -21,7 +22,7 @@ struct DtypeCheck {
 };
 
 template <typename T>
-DtypeCheck get_dtype_check(const char* name) {
+DtypeCheck get_dtype_check(const char *name) {
     py::module_ np = py::module_::import("numpy");
     DtypeCheck check{};
     check.numpy = np.attr("dtype")(np.attr(name));
@@ -30,17 +31,15 @@ DtypeCheck get_dtype_check(const char* name) {
 }
 
 std::vector<DtypeCheck> get_concrete_dtype_checks() {
-    return {
-        // Normalization
-        get_dtype_check<std::int8_t>("int8"),
-        get_dtype_check<std::uint8_t>("uint8"),
-        get_dtype_check<std::int16_t>("int16"),
-        get_dtype_check<std::uint16_t>("uint16"),
-        get_dtype_check<std::int32_t>("int32"),
-        get_dtype_check<std::uint32_t>("uint32"),
-        get_dtype_check<std::int64_t>("int64"),
-        get_dtype_check<std::uint64_t>("uint64")
-    };
+    return {// Normalization
+            get_dtype_check<std::int8_t>("int8"),
+            get_dtype_check<std::uint8_t>("uint8"),
+            get_dtype_check<std::int16_t>("int16"),
+            get_dtype_check<std::uint16_t>("uint16"),
+            get_dtype_check<std::int32_t>("int32"),
+            get_dtype_check<std::uint32_t>("uint32"),
+            get_dtype_check<std::int64_t>("int64"),
+            get_dtype_check<std::uint64_t>("uint64")};
 }
 
 struct DtypeSizeCheck {
@@ -79,43 +78,71 @@ using arr = py::array;
 using arr_t = py::array_t<uint16_t, 0>;
 static_assert(std::is_same<arr_t::value_type, uint16_t>::value, "");
 
-template<typename... Ix> arr data(const arr& a, Ix... index) {
+template <typename... Ix>
+arr data(const arr &a, Ix... index) {
     return arr(a.nbytes() - a.offset_at(index...), (const uint8_t *) a.data(index...));
 }
 
-template<typename... Ix> arr data_t(const arr_t& a, Ix... index) {
+template <typename... Ix>
+arr data_t(const arr_t &a, Ix... index) {
     return arr(a.size() - a.index_at(index...), a.data(index...));
 }
 
-template<typename... Ix> arr& mutate_data(arr& a, Ix... index) {
-    auto ptr = (uint8_t *) a.mutable_data(index...);
-    for (py::ssize_t i = 0; i < a.nbytes() - a.offset_at(index...); i++)
+template <typename... Ix>
+arr &mutate_data(arr &a, Ix... index) {
+    auto *ptr = (uint8_t *) a.mutable_data(index...);
+    for (py::ssize_t i = 0; i < a.nbytes() - a.offset_at(index...); i++) {
         ptr[i] = (uint8_t) (ptr[i] * 2);
+    }
     return a;
 }
 
-template<typename... Ix> arr_t& mutate_data_t(arr_t& a, Ix... index) {
+template <typename... Ix>
+arr_t &mutate_data_t(arr_t &a, Ix... index) {
     auto ptr = a.mutable_data(index...);
-    for (py::ssize_t i = 0; i < a.size() - a.index_at(index...); i++)
+    for (py::ssize_t i = 0; i < a.size() - a.index_at(index...); i++) {
         ptr[i]++;
+    }
+    return a;
+}
+
+template <typename... Ix>
+py::ssize_t index_at(const arr &a, Ix... idx) {
+    return a.index_at(idx...);
+}
+template <typename... Ix>
+py::ssize_t index_at_t(const arr_t &a, Ix... idx) {
+    return a.index_at(idx...);
+}
+template <typename... Ix>
+py::ssize_t offset_at(const arr &a, Ix... idx) {
+    return a.offset_at(idx...);
+}
+template <typename... Ix>
+py::ssize_t offset_at_t(const arr_t &a, Ix... idx) {
+    return a.offset_at(idx...);
+}
+template <typename... Ix>
+py::ssize_t at_t(const arr_t &a, Ix... idx) {
+    return a.at(idx...);
+}
+template <typename... Ix>
+arr_t &mutate_at_t(arr_t &a, Ix... idx) {
+    a.mutable_at(idx...)++;
     return a;
 }
 
-template<typename... Ix> py::ssize_t index_at(const arr& a, Ix... idx) { return a.index_at(idx...); }
-template<typename... Ix> py::ssize_t index_at_t(const arr_t& a, Ix... idx) { return a.index_at(idx...); }
-template<typename... Ix> py::ssize_t offset_at(const arr& a, Ix... idx) { return a.offset_at(idx...); }
-template<typename... Ix> py::ssize_t offset_at_t(const arr_t& a, Ix... idx) { return a.offset_at(idx...); }
-template<typename... Ix> py::ssize_t at_t(const arr_t& a, Ix... idx) { return a.at(idx...); }
-template<typename... Ix> arr_t& mutate_at_t(arr_t& a, Ix... idx) { a.mutable_at(idx...)++; return a; }
-
-#define def_index_fn(name, type) \
-    sm.def(#name, [](type a) { return name(a); }); \
-    sm.def(#name, [](type a, int i) { return name(a, i); }); \
-    sm.def(#name, [](type a, int i, int j) { return name(a, i, j); }); \
+#define def_index_fn(name, type)                                                                  \
+    sm.def(#name, [](type a) { return name(a); });                                                \
+    sm.def(#name, [](type a, int i) { return name(a, i); });                                      \
+    sm.def(#name, [](type a, int i, int j) { return name(a, i, j); });                            \
     sm.def(#name, [](type a, int i, int j, int k) { return name(a, i, j, k); });
 
-template <typename T, typename T2> py::handle auxiliaries(T &&r, T2 &&r2) {
-    if (r.ndim() != 2) throw std::domain_error("error: ndim != 2");
+template <typename T, typename T2>
+py::handle auxiliaries(T &&r, T2 &&r2) {
+    if (r.ndim() != 2) {
+        throw std::domain_error("error: ndim != 2");
+    }
     py::list l;
     l.append(*r.data(0, 0));
     l.append(*r2.mutable_data(0, 0));
@@ -133,16 +160,18 @@ template <typename T, typename T2> py::handle auxiliaries(T &&r, T2 &&r2) {
 static int data_i = 42;
 
 TEST_SUBMODULE(numpy_array, sm) {
-    try { py::module_::import("numpy"); }
-    catch (...) { return; }
+    try {
+        py::module_::import("numpy");
+    } catch (const py::error_already_set &) {
+        return;
+    }
 
     // test_dtypes
     py::class_<DtypeCheck>(sm, "DtypeCheck")
         .def_readonly("numpy", &DtypeCheck::numpy)
         .def_readonly("pybind11", &DtypeCheck::pybind11)
-        .def("__repr__", [](const DtypeCheck& self) {
-            return py::str("<DtypeCheck numpy={} pybind11={}>").format(
-                self.numpy, self.pybind11);
+        .def("__repr__", [](const DtypeCheck &self) {
+            return py::str("<DtypeCheck numpy={} pybind11={}>").format(self.numpy, self.pybind11);
         });
     sm.def("get_concrete_dtype_checks", &get_concrete_dtype_checks);
 
@@ -150,41 +179,41 @@ TEST_SUBMODULE(numpy_array, sm) {
         .def_readonly("name", &DtypeSizeCheck::name)
         .def_readonly("size_cpp", &DtypeSizeCheck::size_cpp)
         .def_readonly("size_numpy", &DtypeSizeCheck::size_numpy)
-        .def("__repr__", [](const DtypeSizeCheck& self) {
-            return py::str("<DtypeSizeCheck name='{}' size_cpp={} size_numpy={} dtype={}>").format(
-                self.name, self.size_cpp, self.size_numpy, self.dtype);
+        .def("__repr__", [](const DtypeSizeCheck &self) {
+            return py::str("<DtypeSizeCheck name='{}' size_cpp={} size_numpy={} dtype={}>")
+                .format(self.name, self.size_cpp, self.size_numpy, self.dtype);
         });
     sm.def("get_platform_dtype_size_checks", &get_platform_dtype_size_checks);
 
     // test_array_attributes
-    sm.def("ndim", [](const arr& a) { return a.ndim(); });
-    sm.def("shape", [](const arr& a) { return arr(a.ndim(), a.shape()); });
-    sm.def("shape", [](const arr& a, py::ssize_t dim) { return a.shape(dim); });
-    sm.def("strides", [](const arr& a) { return arr(a.ndim(), a.strides()); });
-    sm.def("strides", [](const arr& a, py::ssize_t dim) { return a.strides(dim); });
-    sm.def("writeable", [](const arr& a) { return a.writeable(); });
-    sm.def("size", [](const arr& a) { return a.size(); });
-    sm.def("itemsize", [](const arr& a) { return a.itemsize(); });
-    sm.def("nbytes", [](const arr& a) { return a.nbytes(); });
-    sm.def("owndata", [](const arr& a) { return a.owndata(); });
+    sm.def("ndim", [](const arr &a) { return a.ndim(); });
+    sm.def("shape", [](const arr &a) { return arr(a.ndim(), a.shape()); });
+    sm.def("shape", [](const arr &a, py::ssize_t dim) { return a.shape(dim); });
+    sm.def("strides", [](const arr &a) { return arr(a.ndim(), a.strides()); });
+    sm.def("strides", [](const arr &a, py::ssize_t dim) { return a.strides(dim); });
+    sm.def("writeable", [](const arr &a) { return a.writeable(); });
+    sm.def("size", [](const arr &a) { return a.size(); });
+    sm.def("itemsize", [](const arr &a) { return a.itemsize(); });
+    sm.def("nbytes", [](const arr &a) { return a.nbytes(); });
+    sm.def("owndata", [](const arr &a) { return a.owndata(); });
 
     // test_index_offset
-    def_index_fn(index_at, const arr&);
-    def_index_fn(index_at_t, const arr_t&);
-    def_index_fn(offset_at, const arr&);
-    def_index_fn(offset_at_t, const arr_t&);
+    def_index_fn(index_at, const arr &);
+    def_index_fn(index_at_t, const arr_t &);
+    def_index_fn(offset_at, const arr &);
+    def_index_fn(offset_at_t, const arr_t &);
     // test_data
-    def_index_fn(data, const arr&);
-    def_index_fn(data_t, const arr_t&);
+    def_index_fn(data, const arr &);
+    def_index_fn(data_t, const arr_t &);
     // test_mutate_data, test_mutate_readonly
-    def_index_fn(mutate_data, arr&);
-    def_index_fn(mutate_data_t, arr_t&);
-    def_index_fn(at_t, const arr_t&);
-    def_index_fn(mutate_at_t, arr_t&);
+    def_index_fn(mutate_data, arr &);
+    def_index_fn(mutate_data_t, arr_t &);
+    def_index_fn(at_t, const arr_t &);
+    def_index_fn(mutate_at_t, arr_t &);
 
     // test_make_c_f_array
-    sm.def("make_f_array", [] { return py::array_t<float>({ 2, 2 }, { 4, 8 }); });
-    sm.def("make_c_array", [] { return py::array_t<float>({ 2, 2 }, { 8, 4 }); });
+    sm.def("make_f_array", [] { return py::array_t<float>({2, 2}, {4, 8}); });
+    sm.def("make_c_array", [] { return py::array_t<float>({2, 2}, {8, 4}); });
 
     // test_empty_shaped_array
     sm.def("make_empty_shaped_array", [] { return py::array(py::dtype("f"), {}, {}); });
@@ -192,19 +221,17 @@ TEST_SUBMODULE(numpy_array, sm) {
     sm.def("scalar_int", []() { return py::array(py::dtype("i"), {}, {}, &data_i); });
 
     // test_wrap
-    sm.def("wrap", [](py::array a) {
-        return py::array(
-            a.dtype(),
-            {a.shape(), a.shape() + a.ndim()},
-            {a.strides(), a.strides() + a.ndim()},
-            a.data(),
-            a
-        );
+    sm.def("wrap", [](const py::array &a) {
+        return py::array(a.dtype(),
+                         {a.shape(), a.shape() + a.ndim()},
+                         {a.strides(), a.strides() + a.ndim()},
+                         a.data(),
+                         a);
     });
 
     // test_numpy_view
     struct ArrayClass {
-        int data[2] = { 1, 2 };
+        int data[2] = {1, 2};
         ArrayClass() { py::print("ArrayClass()"); }
         ~ArrayClass() { py::print("~ArrayClass()"); }
     };
@@ -212,103 +239,121 @@ TEST_SUBMODULE(numpy_array, sm) {
         .def(py::init<>())
         .def("numpy_view", [](py::object &obj) {
             py::print("ArrayClass::numpy_view()");
-            auto &a = obj.cast<ArrayClass&>();
+            auto &a = obj.cast<ArrayClass &>();
             return py::array_t<int>({2}, {4}, a.data, obj);
-        }
-    );
+        });
 
     // test_cast_numpy_int64_to_uint64
-    sm.def("function_taking_uint64", [](uint64_t) { });
+    sm.def("function_taking_uint64", [](uint64_t) {});
 
     // test_isinstance
     sm.def("isinstance_untyped", [](py::object yes, py::object no) {
-        return py::isinstance<py::array>(yes) && !py::isinstance<py::array>(no);
+        return py::isinstance<py::array>(std::move(yes))
+               && !py::isinstance<py::array>(std::move(no));
     });
-    sm.def("isinstance_typed", [](py::object o) {
+    sm.def("isinstance_typed", [](const py::object &o) {
         return py::isinstance<py::array_t<double>>(o) && !py::isinstance<py::array_t<int>>(o);
     });
 
     // test_constructors
     sm.def("default_constructors", []() {
-        return py::dict(
-            "array"_a=py::array(),
-            "array_t<int32>"_a=py::array_t<std::int32_t>(),
-            "array_t<double>"_a=py::array_t<double>()
-        );
+        return py::dict("array"_a = py::array(),
+                        "array_t<int32>"_a = py::array_t<std::int32_t>(),
+                        "array_t<double>"_a = py::array_t<double>());
     });
-    sm.def("converting_constructors", [](py::object o) {
-        return py::dict(
-            "array"_a=py::array(o),
-            "array_t<int32>"_a=py::array_t<std::int32_t>(o),
-            "array_t<double>"_a=py::array_t<double>(o)
-        );
+    sm.def("converting_constructors", [](const py::object &o) {
+        return py::dict("array"_a = py::array(o),
+                        "array_t<int32>"_a = py::array_t<std::int32_t>(o),
+                        "array_t<double>"_a = py::array_t<double>(o));
     });
 
     // test_overload_resolution
-    sm.def("overloaded", [](py::array_t<double>) { return "double"; });
-    sm.def("overloaded", [](py::array_t<float>) { return "float"; });
-    sm.def("overloaded", [](py::array_t<int>) { return "int"; });
-    sm.def("overloaded", [](py::array_t<unsigned short>) { return "unsigned short"; });
-    sm.def("overloaded", [](py::array_t<long long>) { return "long long"; });
-    sm.def("overloaded", [](py::array_t<std::complex<double>>) { return "double complex"; });
-    sm.def("overloaded", [](py::array_t<std::complex<float>>) { return "float complex"; });
-
-    sm.def("overloaded2", [](py::array_t<std::complex<double>>) { return "double complex"; });
-    sm.def("overloaded2", [](py::array_t<double>) { return "double"; });
-    sm.def("overloaded2", [](py::array_t<std::complex<float>>) { return "float complex"; });
-    sm.def("overloaded2", [](py::array_t<float>) { return "float"; });
+    sm.def("overloaded", [](const py::array_t<double> &) { return "double"; });
+    sm.def("overloaded", [](const py::array_t<float> &) { return "float"; });
+    sm.def("overloaded", [](const py::array_t<int> &) { return "int"; });
+    sm.def("overloaded", [](const py::array_t<unsigned short> &) { return "unsigned short"; });
+    sm.def("overloaded", [](const py::array_t<long long> &) { return "long long"; });
+    sm.def("overloaded",
+           [](const py::array_t<std::complex<double>> &) { return "double complex"; });
+    sm.def("overloaded", [](const py::array_t<std::complex<float>> &) { return "float complex"; });
+
+    sm.def("overloaded2",
+           [](const py::array_t<std::complex<double>> &) { return "double complex"; });
+    sm.def("overloaded2", [](const py::array_t<double> &) { return "double"; });
+    sm.def("overloaded2",
+           [](const py::array_t<std::complex<float>> &) { return "float complex"; });
+    sm.def("overloaded2", [](const py::array_t<float> &) { return "float"; });
+
+    // [workaround(intel)] ICC 20/21 breaks with py::arg().stuff, using py::arg{}.stuff works.
 
     // Only accept the exact types:
-    sm.def("overloaded3", [](py::array_t<int>) { return "int"; }, py::arg().noconvert());
-    sm.def("overloaded3", [](py::array_t<double>) { return "double"; }, py::arg().noconvert());
+    sm.def(
+        "overloaded3", [](const py::array_t<int> &) { return "int"; }, py::arg{}.noconvert());
+    sm.def(
+        "overloaded3",
+        [](const py::array_t<double> &) { return "double"; },
+        py::arg{}.noconvert());
 
     // Make sure we don't do unsafe coercion (e.g. float to int) when not using forcecast, but
     // rather that float gets converted via the safe (conversion to double) overload:
-    sm.def("overloaded4", [](py::array_t<long long, 0>) { return "long long"; });
-    sm.def("overloaded4", [](py::array_t<double, 0>) { return "double"; });
+    sm.def("overloaded4", [](const py::array_t<long long, 0> &) { return "long long"; });
+    sm.def("overloaded4", [](const py::array_t<double, 0> &) { return "double"; });
 
     // But we do allow conversion to int if forcecast is enabled (but only if no overload matches
     // without conversion)
-    sm.def("overloaded5", [](py::array_t<unsigned int>) { return "unsigned int"; });
-    sm.def("overloaded5", [](py::array_t<double>) { return "double"; });
+    sm.def("overloaded5", [](const py::array_t<unsigned int> &) { return "unsigned int"; });
+    sm.def("overloaded5", [](const py::array_t<double> &) { return "double"; });
 
     // test_greedy_string_overload
     // Issue 685: ndarray shouldn't go to std::string overload
-    sm.def("issue685", [](std::string) { return "string"; });
-    sm.def("issue685", [](py::array) { return "array"; });
-    sm.def("issue685", [](py::object) { return "other"; });
+    sm.def("issue685", [](const std::string &) { return "string"; });
+    sm.def("issue685", [](const py::array &) { return "array"; });
+    sm.def("issue685", [](const py::object &) { return "other"; });
 
     // test_array_unchecked_fixed_dims
-    sm.def("proxy_add2", [](py::array_t<double> a, double v) {
-        auto r = a.mutable_unchecked<2>();
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
-            for (py::ssize_t j = 0; j < r.shape(1); j++)
-                r(i, j) += v;
-    }, py::arg().noconvert(), py::arg());
+    sm.def(
+        "proxy_add2",
+        [](py::array_t<double> a, double v) {
+            auto r = a.mutable_unchecked<2>();
+            for (py::ssize_t i = 0; i < r.shape(0); i++) {
+                for (py::ssize_t j = 0; j < r.shape(1); j++) {
+                    r(i, j) += v;
+                }
+            }
+        },
+        py::arg{}.noconvert(),
+        py::arg());
 
     sm.def("proxy_init3", [](double start) {
-        py::array_t<double, py::array::c_style> a({ 3, 3, 3 });
+        py::array_t<double, py::array::c_style> a({3, 3, 3});
         auto r = a.mutable_unchecked<3>();
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
-        for (py::ssize_t j = 0; j < r.shape(1); j++)
-        for (py::ssize_t k = 0; k < r.shape(2); k++)
-            r(i, j, k) = start++;
+        for (py::ssize_t i = 0; i < r.shape(0); i++) {
+            for (py::ssize_t j = 0; j < r.shape(1); j++) {
+                for (py::ssize_t k = 0; k < r.shape(2); k++) {
+                    r(i, j, k) = start++;
+                }
+            }
+        }
         return a;
     });
     sm.def("proxy_init3F", [](double start) {
-        py::array_t<double, py::array::f_style> a({ 3, 3, 3 });
+        py::array_t<double, py::array::f_style> a({3, 3, 3});
         auto r = a.mutable_unchecked<3>();
-        for (py::ssize_t k = 0; k < r.shape(2); k++)
-        for (py::ssize_t j = 0; j < r.shape(1); j++)
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
-            r(i, j, k) = start++;
+        for (py::ssize_t k = 0; k < r.shape(2); k++) {
+            for (py::ssize_t j = 0; j < r.shape(1); j++) {
+                for (py::ssize_t i = 0; i < r.shape(0); i++) {
+                    r(i, j, k) = start++;
+                }
+            }
+        }
         return a;
     });
-    sm.def("proxy_squared_L2_norm", [](py::array_t<double> a) {
+    sm.def("proxy_squared_L2_norm", [](const py::array_t<double> &a) {
         auto r = a.unchecked<1>();
         double sumsq = 0;
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
+        for (py::ssize_t i = 0; i < r.shape(0); i++) {
             sumsq += r[i] * r(i); // Either notation works for a 1D array
+        }
         return sumsq;
     });
 
@@ -332,51 +377,69 @@ TEST_SUBMODULE(numpy_array, sm) {
 
     // test_array_unchecked_dyn_dims
     // Same as the above, but without a compile-time dimensions specification:
-    sm.def("proxy_add2_dyn", [](py::array_t<double> a, double v) {
-        auto r = a.mutable_unchecked();
-        if (r.ndim() != 2) throw std::domain_error("error: ndim != 2");
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
-            for (py::ssize_t j = 0; j < r.shape(1); j++)
-                r(i, j) += v;
-    }, py::arg().noconvert(), py::arg());
+    sm.def(
+        "proxy_add2_dyn",
+        [](py::array_t<double> a, double v) {
+            auto r = a.mutable_unchecked();
+            if (r.ndim() != 2) {
+                throw std::domain_error("error: ndim != 2");
+            }
+            for (py::ssize_t i = 0; i < r.shape(0); i++) {
+                for (py::ssize_t j = 0; j < r.shape(1); j++) {
+                    r(i, j) += v;
+                }
+            }
+        },
+        py::arg{}.noconvert(),
+        py::arg());
     sm.def("proxy_init3_dyn", [](double start) {
-        py::array_t<double, py::array::c_style> a({ 3, 3, 3 });
+        py::array_t<double, py::array::c_style> a({3, 3, 3});
         auto r = a.mutable_unchecked();
-        if (r.ndim() != 3) throw std::domain_error("error: ndim != 3");
-        for (py::ssize_t i = 0; i < r.shape(0); i++)
-        for (py::ssize_t j = 0; j < r.shape(1); j++)
-        for (py::ssize_t k = 0; k < r.shape(2); k++)
-            r(i, j, k) = start++;
+        if (r.ndim() != 3) {
+            throw std::domain_error("error: ndim != 3");
+        }
+        for (py::ssize_t i = 0; i < r.shape(0); i++) {
+            for (py::ssize_t j = 0; j < r.shape(1); j++) {
+                for (py::ssize_t k = 0; k < r.shape(2); k++) {
+                    r(i, j, k) = start++;
+                }
+            }
+        }
         return a;
     });
     sm.def("proxy_auxiliaries2_dyn", [](py::array_t<double> a) {
         return auxiliaries(a.unchecked(), a.mutable_unchecked());
     });
 
-    sm.def("array_auxiliaries2", [](py::array_t<double> a) {
-        return auxiliaries(a, a);
-    });
+    sm.def("array_auxiliaries2", [](py::array_t<double> a) { return auxiliaries(a, a); });
 
     // test_array_failures
-    // Issue #785: Uninformative "Unknown internal error" exception when constructing array from empty object:
+    // Issue #785: Uninformative "Unknown internal error" exception when constructing array from
+    // empty object:
     sm.def("array_fail_test", []() { return py::array(py::object()); });
     sm.def("array_t_fail_test", []() { return py::array_t<double>(py::object()); });
     // Make sure the error from numpy is being passed through:
-    sm.def("array_fail_test_negative_size", []() { int c = 0; return py::array(-1, &c); });
+    sm.def("array_fail_test_negative_size", []() {
+        int c = 0;
+        return py::array(-1, &c);
+    });
 
     // test_initializer_list
     // Issue (unnumbered; reported in #788): regression: initializer lists can be ambiguous
-    sm.def("array_initializer_list1", []() { return py::array_t<float>(1); }); // { 1 } also works, but clang warns about it
-    sm.def("array_initializer_list2", []() { return py::array_t<float>({ 1, 2 }); });
-    sm.def("array_initializer_list3", []() { return py::array_t<float>({ 1, 2, 3 }); });
-    sm.def("array_initializer_list4", []() { return py::array_t<float>({ 1, 2, 3, 4 }); });
+    sm.def("array_initializer_list1", []() { return py::array_t<float>(1); });
+    // { 1 } also works for the above, but clang warns about it
+    sm.def("array_initializer_list2", []() { return py::array_t<float>({1, 2}); });
+    sm.def("array_initializer_list3", []() { return py::array_t<float>({1, 2, 3}); });
+    sm.def("array_initializer_list4", []() { return py::array_t<float>({1, 2, 3, 4}); });
 
     // test_array_resize
     // reshape array to 2D without changing size
     sm.def("array_reshape2", [](py::array_t<double> a) {
-        const auto dim_sz = (py::ssize_t)std::sqrt(a.size());
-        if (dim_sz * dim_sz != a.size())
-            throw std::domain_error("array_reshape2: input array total size is not a squared integer");
+        const auto dim_sz = (py::ssize_t) std::sqrt(a.size());
+        if (dim_sz * dim_sz != a.size()) {
+            throw std::domain_error(
+                "array_reshape2: input array total size is not a squared integer");
+        }
         a.resize({dim_sz, dim_sz});
     });
 
@@ -394,45 +457,68 @@ TEST_SUBMODULE(numpy_array, sm) {
         return a;
     });
 
-    sm.def("index_using_ellipsis", [](py::array a) {
-        return a[py::make_tuple(0, py::ellipsis(), 0)];
+    sm.def("array_view",
+           [](py::array_t<uint8_t> a, const std::string &dtype) { return a.view(dtype); });
+
+    sm.def("reshape_initializer_list", [](py::array_t<int> a, size_t N, size_t M, size_t O) {
+        return a.reshape({N, M, O});
+    });
+    sm.def("reshape_tuple", [](py::array_t<int> a, const std::vector<int> &new_shape) {
+        return a.reshape(new_shape);
     });
 
+    sm.def("index_using_ellipsis",
+           [](const py::array &a) { return a[py::make_tuple(0, py::ellipsis(), 0)]; });
+
     // test_argument_conversions
-    sm.def("accept_double",
-           [](py::array_t<double, 0>) {},
-           py::arg("a"));
-    sm.def("accept_double_forcecast",
-           [](py::array_t<double, py::array::forcecast>) {},
-           py::arg("a"));
-    sm.def("accept_double_c_style",
-           [](py::array_t<double, py::array::c_style>) {},
-           py::arg("a"));
-    sm.def("accept_double_c_style_forcecast",
-           [](py::array_t<double, py::array::forcecast | py::array::c_style>) {},
-           py::arg("a"));
-    sm.def("accept_double_f_style",
-           [](py::array_t<double, py::array::f_style>) {},
-           py::arg("a"));
-    sm.def("accept_double_f_style_forcecast",
-           [](py::array_t<double, py::array::forcecast | py::array::f_style>) {},
-           py::arg("a"));
-    sm.def("accept_double_noconvert",
-           [](py::array_t<double, 0>) {},
-           py::arg("a").noconvert());
-    sm.def("accept_double_forcecast_noconvert",
-           [](py::array_t<double, py::array::forcecast>) {},
-           py::arg("a").noconvert());
-    sm.def("accept_double_c_style_noconvert",
-           [](py::array_t<double, py::array::c_style>) {},
-           py::arg("a").noconvert());
-    sm.def("accept_double_c_style_forcecast_noconvert",
-           [](py::array_t<double, py::array::forcecast | py::array::c_style>) {},
-           py::arg("a").noconvert());
-    sm.def("accept_double_f_style_noconvert",
-           [](py::array_t<double, py::array::f_style>) {},
-           py::arg("a").noconvert());
-    sm.def("accept_double_f_style_forcecast_noconvert",
-           [](py::array_t<double, py::array::forcecast | py::array::f_style>) {},
-           py::arg("a").noconvert());
+    sm.def(
+        "accept_double", [](const py::array_t<double, 0> &) {}, py::arg("a"));
+    sm.def(
+        "accept_double_forcecast",
+        [](const py::array_t<double, py::array::forcecast> &) {},
+        py::arg("a"));
+    sm.def(
+        "accept_double_c_style",
+        [](const py::array_t<double, py::array::c_style> &) {},
+        py::arg("a"));
+    sm.def(
+        "accept_double_c_style_forcecast",
+        [](const py::array_t<double, py::array::forcecast | py::array::c_style> &) {},
+        py::arg("a"));
+    sm.def(
+        "accept_double_f_style",
+        [](const py::array_t<double, py::array::f_style> &) {},
+        py::arg("a"));
+    sm.def(
+        "accept_double_f_style_forcecast",
+        [](const py::array_t<double, py::array::forcecast | py::array::f_style> &) {},
+        py::arg("a"));
+    sm.def(
+        "accept_double_noconvert", [](const py::array_t<double, 0> &) {}, "a"_a.noconvert());
+    sm.def(
+        "accept_double_forcecast_noconvert",
+        [](const py::array_t<double, py::array::forcecast> &) {},
+        "a"_a.noconvert());
+    sm.def(
+        "accept_double_c_style_noconvert",
+        [](const py::array_t<double, py::array::c_style> &) {},
+        "a"_a.noconvert());
+    sm.def(
+        "accept_double_c_style_forcecast_noconvert",
+        [](const py::array_t<double, py::array::forcecast | py::array::c_style> &) {},
+        "a"_a.noconvert());
+    sm.def(
+        "accept_double_f_style_noconvert",
+        [](const py::array_t<double, py::array::f_style> &) {},
+        "a"_a.noconvert());
+    sm.def(
+        "accept_double_f_style_forcecast_noconvert",
+        [](const py::array_t<double, py::array::forcecast | py::array::f_style> &) {},
+        "a"_a.noconvert());
+
+    // Check that types returns correct npy format descriptor
+    sm.def("test_fmt_desc_float", [](const py::array_t<float> &) {});
+    sm.def("test_fmt_desc_double", [](const py::array_t<double> &) {});
+    sm.def("test_fmt_desc_const_float", [](const py::array_t<const float> &) {});
+    sm.def("test_fmt_desc_const_double", [](const py::array_t<const double> &) {});
 }
diff --git a/3rdparty/pybind11/tests/test_numpy_array.py b/3rdparty/pybind11/tests/test_numpy_array.py
index 02f3ecfc0e..504963b166 100644
--- a/3rdparty/pybind11/tests/test_numpy_array.py
+++ b/3rdparty/pybind11/tests/test_numpy_array.py
@@ -1,8 +1,6 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
-
 from pybind11_tests import numpy_array as m
 
 np = pytest.importorskip("numpy")
@@ -20,9 +18,7 @@ def test_dtypes():
         assert check.numpy == check.pybind11, check
         if check.numpy.num != check.pybind11.num:
             print(
-                "NOTE: typenum mismatch for {}: {} != {}".format(
-                    check, check.numpy.num, check.pybind11.num
-                )
+                f"NOTE: typenum mismatch for {check}: {check.numpy.num} != {check.pybind11.num}"
             )
 
 
@@ -118,9 +114,7 @@ def test_at_fail(arr, dim):
     for func in m.at_t, m.mutate_at_t:
         with pytest.raises(IndexError) as excinfo:
             func(arr, *([0] * dim))
-        assert str(excinfo.value) == "index dimension mismatch: {} (ndim = 2)".format(
-            dim
-        )
+        assert str(excinfo.value) == f"index dimension mismatch: {dim} (ndim = 2)"
 
 
 def test_at(arr):
@@ -194,8 +188,6 @@ def test_make_empty_shaped_array():
 
 def test_wrap():
     def assert_references(a, b, base=None):
-        from distutils.version import LooseVersion
-
         if base is None:
             base = a
         assert a is not b
@@ -206,7 +198,8 @@ def assert_references(a, b, base=None):
         assert a.flags.f_contiguous == b.flags.f_contiguous
         assert a.flags.writeable == b.flags.writeable
         assert a.flags.aligned == b.flags.aligned
-        if LooseVersion(np.__version__) >= LooseVersion("1.14.0"):
+        # 1.13 supported Python 3.6
+        if tuple(int(x) for x in np.__version__.split(".")[:2]) >= (1, 14):
             assert a.flags.writebackifcopy == b.flags.writebackifcopy
         else:
             assert a.flags.updateifcopy == b.flags.updateifcopy
@@ -412,7 +405,7 @@ def test_array_unchecked_fixed_dims(msg):
     assert m.proxy_auxiliaries2_const_ref(z1)
 
 
-def test_array_unchecked_dyn_dims(msg):
+def test_array_unchecked_dyn_dims():
     z1 = np.array([[1, 2], [3, 4]], dtype="float64")
     m.proxy_add2_dyn(z1, 10)
     assert np.all(z1 == [[11, 12], [13, 14]])
@@ -445,7 +438,7 @@ def test_initializer_list():
     assert m.array_initializer_list4().shape == (1, 2, 3, 4)
 
 
-def test_array_resize(msg):
+def test_array_resize():
     a = np.array([1, 2, 3, 4, 5, 6, 7, 8, 9], dtype="float64")
     m.array_reshape2(a)
     assert a.size == 9
@@ -471,17 +464,70 @@ def test_array_resize(msg):
 
 
 @pytest.mark.xfail("env.PYPY")
-def test_array_create_and_resize(msg):
+def test_array_create_and_resize():
     a = m.create_and_resize(2)
     assert a.size == 4
     assert np.all(a == 42.0)
 
 
+def test_array_view():
+    a = np.ones(100 * 4).astype("uint8")
+    a_float_view = m.array_view(a, "float32")
+    assert a_float_view.shape == (100 * 1,)  # 1 / 4 bytes = 8 / 32
+
+    a_int16_view = m.array_view(a, "int16")  # 1 / 2 bytes = 16 / 32
+    assert a_int16_view.shape == (100 * 2,)
+
+
+def test_array_view_invalid():
+    a = np.ones(100 * 4).astype("uint8")
+    with pytest.raises(TypeError):
+        m.array_view(a, "deadly_dtype")
+
+
+def test_reshape_initializer_list():
+    a = np.arange(2 * 7 * 3) + 1
+    x = m.reshape_initializer_list(a, 2, 7, 3)
+    assert x.shape == (2, 7, 3)
+    assert list(x[1][4]) == [34, 35, 36]
+    with pytest.raises(ValueError) as excinfo:
+        m.reshape_initializer_list(a, 1, 7, 3)
+    assert str(excinfo.value) == "cannot reshape array of size 42 into shape (1,7,3)"
+
+
+def test_reshape_tuple():
+    a = np.arange(3 * 7 * 2) + 1
+    x = m.reshape_tuple(a, (3, 7, 2))
+    assert x.shape == (3, 7, 2)
+    assert list(x[1][4]) == [23, 24]
+    y = m.reshape_tuple(x, (x.size,))
+    assert y.shape == (42,)
+    with pytest.raises(ValueError) as excinfo:
+        m.reshape_tuple(a, (3, 7, 1))
+    assert str(excinfo.value) == "cannot reshape array of size 42 into shape (3,7,1)"
+    with pytest.raises(ValueError) as excinfo:
+        m.reshape_tuple(a, ())
+    assert str(excinfo.value) == "cannot reshape array of size 42 into shape ()"
+
+
 def test_index_using_ellipsis():
     a = m.index_using_ellipsis(np.zeros((5, 6, 7)))
     assert a.shape == (6,)
 
 
+@pytest.mark.parametrize(
+    "test_func",
+    [
+        m.test_fmt_desc_float,
+        m.test_fmt_desc_double,
+        m.test_fmt_desc_const_float,
+        m.test_fmt_desc_const_double,
+    ],
+)
+def test_format_descriptors_for_floating_point_types(test_func):
+    assert "numpy.ndarray[numpy.float" in test_func.__doc__
+
+
 @pytest.mark.parametrize("forcecast", [False, True])
 @pytest.mark.parametrize("contiguity", [None, "C", "F"])
 @pytest.mark.parametrize("noconvert", [False, True])
diff --git a/3rdparty/pybind11/tests/test_numpy_dtypes.cpp b/3rdparty/pybind11/tests/test_numpy_dtypes.cpp
index b2e5e60756..6654f9ed8f 100644
--- a/3rdparty/pybind11/tests/test_numpy_dtypes.cpp
+++ b/3rdparty/pybind11/tests/test_numpy_dtypes.cpp
@@ -7,13 +7,14 @@
   BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/numpy.h>
 
+#include "pybind11_tests.h"
+
 #ifdef __GNUC__
-#define PYBIND11_PACKED(cls) cls __attribute__((__packed__))
+#    define PYBIND11_PACKED(cls) cls __attribute__((__packed__))
 #else
-#define PYBIND11_PACKED(cls) __pragma(pack(push, 1)) cls __pragma(pack(pop))
+#    define PYBIND11_PACKED(cls) __pragma(pack(push, 1)) cls __pragma(pack(pop))
 #endif
 
 namespace py = pybind11;
@@ -25,7 +26,7 @@ struct SimpleStruct {
     long double ldbl_;
 };
 
-std::ostream& operator<<(std::ostream& os, const SimpleStruct& v) {
+std::ostream &operator<<(std::ostream &os, const SimpleStruct &v) {
     return os << "s:" << v.bool_ << "," << v.uint_ << "," << v.float_ << "," << v.ldbl_;
 }
 
@@ -43,7 +44,7 @@ PYBIND11_PACKED(struct PackedStruct {
     long double ldbl_;
 });
 
-std::ostream& operator<<(std::ostream& os, const PackedStruct& v) {
+std::ostream &operator<<(std::ostream &os, const PackedStruct &v) {
     return os << "p:" << v.bool_ << "," << v.uint_ << "," << v.float_ << "," << v.ldbl_;
 }
 
@@ -52,7 +53,7 @@ PYBIND11_PACKED(struct NestedStruct {
     PackedStruct b;
 });
 
-std::ostream& operator<<(std::ostream& os, const NestedStruct& v) {
+std::ostream &operator<<(std::ostream &os, const NestedStruct &v) {
     return os << "n:a=" << v.a << ";b=" << v.b;
 }
 
@@ -70,7 +71,7 @@ struct PartialNestedStruct {
     uint64_t dummy2;
 };
 
-struct UnboundStruct { };
+struct UnboundStruct {};
 
 struct StringStruct {
     char a[3];
@@ -82,7 +83,7 @@ struct ComplexStruct {
     std::complex<double> cdbl;
 };
 
-std::ostream& operator<<(std::ostream& os, const ComplexStruct& v) {
+std::ostream &operator<<(std::ostream &os, const ComplexStruct &v) {
     return os << "c:" << v.cflt << "," << v.cdbl;
 }
 
@@ -106,57 +107,65 @@ PYBIND11_PACKED(struct EnumStruct {
     E2 e2;
 });
 
-std::ostream& operator<<(std::ostream& os, const StringStruct& v) {
+std::ostream &operator<<(std::ostream &os, const StringStruct &v) {
     os << "a='";
-    for (size_t i = 0; i < 3 && v.a[i]; i++) os << v.a[i];
+    for (size_t i = 0; i < 3 && (v.a[i] != 0); i++) {
+        os << v.a[i];
+    }
     os << "',b='";
-    for (size_t i = 0; i < 3 && v.b[i]; i++) os << v.b[i];
+    for (size_t i = 0; i < 3 && (v.b[i] != 0); i++) {
+        os << v.b[i];
+    }
     return os << "'";
 }
 
-std::ostream& operator<<(std::ostream& os, const ArrayStruct& v) {
+std::ostream &operator<<(std::ostream &os, const ArrayStruct &v) {
     os << "a={";
     for (int i = 0; i < 3; i++) {
-        if (i > 0)
+        if (i > 0) {
             os << ',';
+        }
         os << '{';
-        for (int j = 0; j < 3; j++)
+        for (int j = 0; j < 3; j++) {
             os << v.a[i][j] << ',';
+        }
         os << v.a[i][3] << '}';
     }
     os << "},b={" << v.b[0] << ',' << v.b[1];
     os << "},c={" << int(v.c[0]) << ',' << int(v.c[1]) << ',' << int(v.c[2]);
     os << "},d={";
     for (int i = 0; i < 4; i++) {
-        if (i > 0)
+        if (i > 0) {
             os << ',';
+        }
         os << '{' << v.d[i][0] << ',' << v.d[i][1] << '}';
     }
     return os << '}';
 }
 
-std::ostream& operator<<(std::ostream& os, const EnumStruct& v) {
+std::ostream &operator<<(std::ostream &os, const EnumStruct &v) {
     return os << "e1=" << (v.e1 == E1::A ? "A" : "B") << ",e2=" << (v.e2 == E2::X ? "X" : "Y");
 }
 
 template <typename T>
 py::array mkarray_via_buffer(size_t n) {
-    return py::array(py::buffer_info(nullptr, sizeof(T),
-                                     py::format_descriptor<T>::format(),
-                                     1, { n }, { sizeof(T) }));
+    return py::array(py::buffer_info(
+        nullptr, sizeof(T), py::format_descriptor<T>::format(), 1, {n}, {sizeof(T)}));
 }
 
-#define SET_TEST_VALS(s, i) do { \
-    s.bool_ = (i) % 2 != 0; \
-    s.uint_ = (uint32_t) (i); \
-    s.float_ = (float) (i) * 1.5f; \
-    s.ldbl_ = (long double) (i) * -2.5L; } while (0)
+#define SET_TEST_VALS(s, i)                                                                       \
+    do {                                                                                          \
+        (s).bool_ = (i) % 2 != 0;                                                                 \
+        (s).uint_ = (uint32_t) (i);                                                               \
+        (s).float_ = (float) (i) *1.5f;                                                           \
+        (s).ldbl_ = (long double) (i) * -2.5L;                                                    \
+    } while (0)
 
 template <typename S>
 py::array_t<S, 0> create_recarray(size_t n) {
     auto arr = mkarray_via_buffer<S>(n);
     auto req = arr.request();
-    auto ptr = static_cast<S*>(req.ptr);
+    auto *ptr = static_cast<S *>(req.ptr);
     for (size_t i = 0; i < n; i++) {
         SET_TEST_VALS(ptr[i], i);
     }
@@ -166,7 +175,7 @@ py::array_t<S, 0> create_recarray(size_t n) {
 template <typename S>
 py::list print_recarray(py::array_t<S, 0> arr) {
     const auto req = arr.request();
-    const auto ptr = static_cast<S*>(req.ptr);
+    auto *const ptr = static_cast<S *>(req.ptr);
     auto l = py::list();
     for (py::ssize_t i = 0; i < req.size; i++) {
         std::stringstream ss;
@@ -179,12 +188,12 @@ py::list print_recarray(py::array_t<S, 0> arr) {
 py::array_t<int32_t, 0> test_array_ctors(int i) {
     using arr_t = py::array_t<int32_t, 0>;
 
-    std::vector<int32_t> data { 1, 2, 3, 4, 5, 6 };
-    std::vector<py::ssize_t> shape { 3, 2 };
-    std::vector<py::ssize_t> strides { 8, 4 };
+    std::vector<int32_t> data{1, 2, 3, 4, 5, 6};
+    std::vector<py::ssize_t> shape{3, 2};
+    std::vector<py::ssize_t> strides{8, 4};
 
-    auto ptr = data.data();
-    auto vptr = (void *) ptr;
+    auto *ptr = data.data();
+    auto *vptr = (void *) ptr;
     auto dtype = py::dtype("int32");
 
     py::buffer_info buf_ndim1(vptr, 4, "i", 6);
@@ -194,41 +203,69 @@ py::array_t<int32_t, 0> test_array_ctors(int i) {
 
     auto fill = [](py::array arr) {
         auto req = arr.request();
-        for (int i = 0; i < 6; i++) ((int32_t *) req.ptr)[i] = i + 1;
+        for (int i = 0; i < 6; i++) {
+            ((int32_t *) req.ptr)[i] = i + 1;
+        }
         return arr;
     };
 
     switch (i) {
-    // shape: (3, 2)
-    case 10: return arr_t(shape, strides, ptr);
-    case 11: return py::array(shape, strides, ptr);
-    case 12: return py::array(dtype, shape, strides, vptr);
-    case 13: return arr_t(shape, ptr);
-    case 14: return py::array(shape, ptr);
-    case 15: return py::array(dtype, shape, vptr);
-    case 16: return arr_t(buf_ndim2);
-    case 17: return py::array(buf_ndim2);
-    // shape: (3, 2) - post-fill
-    case 20: return fill(arr_t(shape, strides));
-    case 21: return py::array(shape, strides, ptr); // can't have nullptr due to templated ctor
-    case 22: return fill(py::array(dtype, shape, strides));
-    case 23: return fill(arr_t(shape));
-    case 24: return py::array(shape, ptr); // can't have nullptr due to templated ctor
-    case 25: return fill(py::array(dtype, shape));
-    case 26: return fill(arr_t(buf_ndim2_null));
-    case 27: return fill(py::array(buf_ndim2_null));
-    // shape: (6, )
-    case 30: return arr_t(6, ptr);
-    case 31: return py::array(6, ptr);
-    case 32: return py::array(dtype, 6, vptr);
-    case 33: return arr_t(buf_ndim1);
-    case 34: return py::array(buf_ndim1);
-    // shape: (6, )
-    case 40: return fill(arr_t(6));
-    case 41: return py::array(6, ptr);  // can't have nullptr due to templated ctor
-    case 42: return fill(py::array(dtype, 6));
-    case 43: return fill(arr_t(buf_ndim1_null));
-    case 44: return fill(py::array(buf_ndim1_null));
+        // shape: (3, 2)
+        case 10:
+            return arr_t(shape, strides, ptr);
+        case 11:
+            return py::array(shape, strides, ptr);
+        case 12:
+            return py::array(dtype, shape, strides, vptr);
+        case 13:
+            return arr_t(shape, ptr);
+        case 14:
+            return py::array(shape, ptr);
+        case 15:
+            return py::array(dtype, shape, vptr);
+        case 16:
+            return arr_t(buf_ndim2);
+        case 17:
+            return py::array(buf_ndim2);
+        // shape: (3, 2) - post-fill
+        case 20:
+            return fill(arr_t(shape, strides));
+        case 21:
+            return py::array(shape, strides, ptr); // can't have nullptr due to templated ctor
+        case 22:
+            return fill(py::array(dtype, shape, strides));
+        case 23:
+            return fill(arr_t(shape));
+        case 24:
+            return py::array(shape, ptr); // can't have nullptr due to templated ctor
+        case 25:
+            return fill(py::array(dtype, shape));
+        case 26:
+            return fill(arr_t(buf_ndim2_null));
+        case 27:
+            return fill(py::array(buf_ndim2_null));
+        // shape: (6, )
+        case 30:
+            return arr_t(6, ptr);
+        case 31:
+            return py::array(6, ptr);
+        case 32:
+            return py::array(dtype, 6, vptr);
+        case 33:
+            return arr_t(buf_ndim1);
+        case 34:
+            return py::array(buf_ndim1);
+        // shape: (6, )
+        case 40:
+            return fill(arr_t(6));
+        case 41:
+            return py::array(6, ptr); // can't have nullptr due to templated ctor
+        case 42:
+            return fill(py::array(dtype, 6));
+        case 43:
+            return fill(arr_t(buf_ndim1_null));
+        case 44:
+            return fill(py::array(buf_ndim1_null));
     }
     return arr_t();
 }
@@ -240,14 +277,21 @@ py::list test_dtype_ctors() {
     list.append(py::dtype::from_args(py::str("bool")));
     py::list names, offsets, formats;
     py::dict dict;
-    names.append(py::str("a")); names.append(py::str("b")); dict["names"] = names;
-    offsets.append(py::int_(1)); offsets.append(py::int_(10)); dict["offsets"] = offsets;
-    formats.append(py::dtype("int32")); formats.append(py::dtype("float64")); dict["formats"] = formats;
+    names.append(py::str("a"));
+    names.append(py::str("b"));
+    dict["names"] = names;
+    offsets.append(py::int_(1));
+    offsets.append(py::int_(10));
+    dict["offsets"] = offsets;
+    formats.append(py::dtype("int32"));
+    formats.append(py::dtype("float64"));
+    dict["formats"] = formats;
     dict["itemsize"] = py::int_(20);
     list.append(py::dtype::from_args(dict));
     list.append(py::dtype(names, formats, offsets, 20));
-    list.append(py::dtype(py::buffer_info((void *) 0, sizeof(unsigned int), "I", 1)));
-    list.append(py::dtype(py::buffer_info((void *) 0, 0, "T{i:a:f:b:}", 1)));
+    list.append(py::dtype(py::buffer_info((void *) nullptr, sizeof(unsigned int), "I", 1)));
+    list.append(py::dtype(py::buffer_info((void *) nullptr, 0, "T{i:a:f:b:}", 1)));
+    list.append(py::dtype(py::detail::npy_api::NPY_DOUBLE_));
     return list;
 }
 
@@ -255,8 +299,11 @@ struct A {};
 struct B {};
 
 TEST_SUBMODULE(numpy_dtypes, m) {
-    try { py::module_::import("numpy"); }
-    catch (...) { return; }
+    try {
+        py::module_::import("numpy");
+    } catch (const py::error_already_set &) {
+        return;
+    }
 
     // typeinfo may be registered before the dtype descriptor for scalar casts to work...
     py::class_<SimpleStruct>(m, "SimpleStruct")
@@ -266,18 +313,18 @@ TEST_SUBMODULE(numpy_dtypes, m) {
         .def_readwrite("uint_", &SimpleStruct::uint_)
         .def_readwrite("float_", &SimpleStruct::float_)
         .def_readwrite("ldbl_", &SimpleStruct::ldbl_)
-        .def("astuple", [](const SimpleStruct& self) {
-            return py::make_tuple(self.bool_, self.uint_, self.float_, self.ldbl_);
-        })
-        .def_static("fromtuple", [](const py::tuple tup) {
+        .def("astuple",
+             [](const SimpleStruct &self) {
+                 return py::make_tuple(self.bool_, self.uint_, self.float_, self.ldbl_);
+             })
+        .def_static("fromtuple", [](const py::tuple &tup) {
             if (py::len(tup) != 4) {
                 throw py::cast_error("Invalid size");
             }
-            return SimpleStruct{
-                tup[0].cast<bool>(),
-                tup[1].cast<uint32_t>(),
-                tup[2].cast<float>(),
-                tup[3].cast<long double>()};
+            return SimpleStruct{tup[0].cast<bool>(),
+                                tup[1].cast<uint32_t>(),
+                                tup[2].cast<float>(),
+                                tup[3].cast<long double>()};
         });
 
     PYBIND11_NUMPY_DTYPE(SimpleStruct, bool_, uint_, float_, ldbl_);
@@ -296,19 +343,21 @@ TEST_SUBMODULE(numpy_dtypes, m) {
 
     PYBIND11_NUMPY_DTYPE_EX(StructWithUglyNames, __x__, "x", __y__, "y");
 
-    // If uncommented, this should produce a static_assert failure telling the user that the struct
+#ifdef PYBIND11_NEVER_DEFINED_EVER
+    // If enabled, this should produce a static_assert failure telling the user that the struct
     // is not a POD type
-//    struct NotPOD { std::string v; NotPOD() : v("hi") {}; };
-//    PYBIND11_NUMPY_DTYPE(NotPOD, v);
+    struct NotPOD {
+        std::string v;
+        NotPOD() : v("hi"){};
+    };
+    PYBIND11_NUMPY_DTYPE(NotPOD, v);
+#endif
 
     // Check that dtypes can be registered programmatically, both from
     // initializer lists of field descriptors and from other containers.
-    py::detail::npy_format_descriptor<A>::register_dtype(
-        {}
-    );
+    py::detail::npy_format_descriptor<A>::register_dtype({});
     py::detail::npy_format_descriptor<B>::register_dtype(
-        std::vector<py::detail::field_descriptor>{}
-    );
+        std::vector<py::detail::field_descriptor>{});
 
     // test_recarray, test_scalar_conversion
     m.def("create_rec_simple", &create_recarray<SimpleStruct>);
@@ -316,7 +365,7 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     m.def("create_rec_nested", [](size_t n) { // test_signature
         py::array_t<NestedStruct, 0> arr = mkarray_via_buffer<NestedStruct>(n);
         auto req = arr.request();
-        auto ptr = static_cast<NestedStruct*>(req.ptr);
+        auto *ptr = static_cast<NestedStruct *>(req.ptr);
         for (size_t i = 0; i < n; i++) {
             SET_TEST_VALS(ptr[i].a, i);
             SET_TEST_VALS(ptr[i].b, i + 1);
@@ -327,7 +376,7 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     m.def("create_rec_partial_nested", [](size_t n) {
         py::array_t<PartialNestedStruct, 0> arr = mkarray_via_buffer<PartialNestedStruct>(n);
         auto req = arr.request();
-        auto ptr = static_cast<PartialNestedStruct*>(req.ptr);
+        auto *ptr = static_cast<PartialNestedStruct *>(req.ptr);
         for (size_t i = 0; i < n; i++) {
             SET_TEST_VALS(ptr[i].a, i);
         }
@@ -341,48 +390,95 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     m.def("get_format_unbound", []() { return py::format_descriptor<UnboundStruct>::format(); });
     m.def("print_format_descriptors", []() {
         py::list l;
-        for (const auto &fmt : {
-            py::format_descriptor<SimpleStruct>::format(),
-            py::format_descriptor<PackedStruct>::format(),
-            py::format_descriptor<NestedStruct>::format(),
-            py::format_descriptor<PartialStruct>::format(),
-            py::format_descriptor<PartialNestedStruct>::format(),
-            py::format_descriptor<StringStruct>::format(),
-            py::format_descriptor<ArrayStruct>::format(),
-            py::format_descriptor<EnumStruct>::format(),
-            py::format_descriptor<ComplexStruct>::format()
-        }) {
+        for (const auto &fmt : {py::format_descriptor<SimpleStruct>::format(),
+                                py::format_descriptor<PackedStruct>::format(),
+                                py::format_descriptor<NestedStruct>::format(),
+                                py::format_descriptor<PartialStruct>::format(),
+                                py::format_descriptor<PartialNestedStruct>::format(),
+                                py::format_descriptor<StringStruct>::format(),
+                                py::format_descriptor<ArrayStruct>::format(),
+                                py::format_descriptor<EnumStruct>::format(),
+                                py::format_descriptor<ComplexStruct>::format()}) {
             l.append(py::cast(fmt));
         }
         return l;
     });
 
     // test_dtype
+    std::vector<const char *> dtype_names{
+        "byte",    "short",   "intc",        "int_",  "longlong",   "ubyte",       "ushort",
+        "uintc",   "uint",    "ulonglong",   "half",  "single",     "double",      "longdouble",
+        "csingle", "cdouble", "clongdouble", "bool_", "datetime64", "timedelta64", "object_"};
+
     m.def("print_dtypes", []() {
         py::list l;
-        for (const py::handle &d : {
-            py::dtype::of<SimpleStruct>(),
-            py::dtype::of<PackedStruct>(),
-            py::dtype::of<NestedStruct>(),
-            py::dtype::of<PartialStruct>(),
-            py::dtype::of<PartialNestedStruct>(),
-            py::dtype::of<StringStruct>(),
-            py::dtype::of<ArrayStruct>(),
-            py::dtype::of<EnumStruct>(),
-            py::dtype::of<StructWithUglyNames>(),
-            py::dtype::of<ComplexStruct>()
-        })
+        for (const py::handle &d : {py::dtype::of<SimpleStruct>(),
+                                    py::dtype::of<PackedStruct>(),
+                                    py::dtype::of<NestedStruct>(),
+                                    py::dtype::of<PartialStruct>(),
+                                    py::dtype::of<PartialNestedStruct>(),
+                                    py::dtype::of<StringStruct>(),
+                                    py::dtype::of<ArrayStruct>(),
+                                    py::dtype::of<EnumStruct>(),
+                                    py::dtype::of<StructWithUglyNames>(),
+                                    py::dtype::of<ComplexStruct>()}) {
             l.append(py::str(d));
+        }
         return l;
     });
     m.def("test_dtype_ctors", &test_dtype_ctors);
+    m.def("test_dtype_kind", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).kind());
+        }
+        return list;
+    });
+    m.def("test_dtype_char_", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).char_());
+        }
+        return list;
+    });
+    m.def("test_dtype_num", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).num());
+        }
+        return list;
+    });
+    m.def("test_dtype_byteorder", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).byteorder());
+        }
+        return list;
+    });
+    m.def("test_dtype_alignment", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).alignment());
+        }
+        return list;
+    });
+    m.def("test_dtype_flags", [dtype_names]() {
+        py::list list;
+        for (const auto &dt_name : dtype_names) {
+            list.append(py::dtype(dt_name).flags());
+        }
+        return list;
+    });
     m.def("test_dtype_methods", []() {
         py::list list;
         auto dt1 = py::dtype::of<int32_t>();
         auto dt2 = py::dtype::of<SimpleStruct>();
-        list.append(dt1); list.append(dt2);
-        list.append(py::bool_(dt1.has_fields())); list.append(py::bool_(dt2.has_fields()));
-        list.append(py::int_(dt1.itemsize())); list.append(py::int_(dt2.itemsize()));
+        list.append(dt1);
+        list.append(dt2);
+        list.append(py::bool_(dt1.has_fields()));
+        list.append(py::bool_(dt2.has_fields()));
+        list.append(py::int_(dt1.itemsize()));
+        list.append(py::int_(dt2.itemsize()));
         return list;
     });
     struct TrailingPaddingStruct {
@@ -397,17 +493,24 @@ TEST_SUBMODULE(numpy_dtypes, m) {
         py::array_t<StringStruct, 0> arr = mkarray_via_buffer<StringStruct>(non_empty ? 4 : 0);
         if (non_empty) {
             auto req = arr.request();
-            auto ptr = static_cast<StringStruct*>(req.ptr);
-            for (py::ssize_t i = 0; i < req.size * req.itemsize; i++)
-                static_cast<char*>(req.ptr)[i] = 0;
-            ptr[1].a[0] = 'a'; ptr[1].b[0] = 'a';
-            ptr[2].a[0] = 'a'; ptr[2].b[0] = 'a';
-            ptr[3].a[0] = 'a'; ptr[3].b[0] = 'a';
-
-            ptr[2].a[1] = 'b'; ptr[2].b[1] = 'b';
-            ptr[3].a[1] = 'b'; ptr[3].b[1] = 'b';
-
-            ptr[3].a[2] = 'c'; ptr[3].b[2] = 'c';
+            auto *ptr = static_cast<StringStruct *>(req.ptr);
+            for (py::ssize_t i = 0; i < req.size * req.itemsize; i++) {
+                static_cast<char *>(req.ptr)[i] = 0;
+            }
+            ptr[1].a[0] = 'a';
+            ptr[1].b[0] = 'a';
+            ptr[2].a[0] = 'a';
+            ptr[2].b[0] = 'a';
+            ptr[3].a[0] = 'a';
+            ptr[3].b[0] = 'a';
+
+            ptr[2].a[1] = 'b';
+            ptr[2].b[1] = 'b';
+            ptr[3].a[1] = 'b';
+            ptr[3].b[1] = 'b';
+
+            ptr[3].a[2] = 'c';
+            ptr[3].b[2] = 'c';
         }
         return arr;
     });
@@ -416,18 +519,24 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     // test_array_array
     m.def("create_array_array", [](size_t n) {
         py::array_t<ArrayStruct, 0> arr = mkarray_via_buffer<ArrayStruct>(n);
-        auto ptr = (ArrayStruct *) arr.mutable_data();
+        auto *ptr = (ArrayStruct *) arr.mutable_data();
         for (size_t i = 0; i < n; i++) {
-            for (size_t j = 0; j < 3; j++)
-                for (size_t k = 0; k < 4; k++)
+            for (size_t j = 0; j < 3; j++) {
+                for (size_t k = 0; k < 4; k++) {
                     ptr[i].a[j][k] = char('A' + (i * 100 + j * 10 + k) % 26);
-            for (size_t j = 0; j < 2; j++)
+                }
+            }
+            for (size_t j = 0; j < 2; j++) {
                 ptr[i].b[j] = int32_t(i * 1000 + j);
-            for (size_t j = 0; j < 3; j++)
+            }
+            for (size_t j = 0; j < 3; j++) {
                 ptr[i].c[j] = uint8_t(i * 10 + j);
-            for (size_t j = 0; j < 4; j++)
-                for (size_t k = 0; k < 2; k++)
+            }
+            for (size_t j = 0; j < 4; j++) {
+                for (size_t k = 0; k < 2; k++) {
                     ptr[i].d[j][k] = float(i) * 100.0f + float(j) * 10.0f + float(k);
+                }
+            }
         }
         return arr;
     });
@@ -436,7 +545,7 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     // test_enum_array
     m.def("create_enum_array", [](size_t n) {
         py::array_t<EnumStruct, 0> arr = mkarray_via_buffer<EnumStruct>(n);
-        auto ptr = (EnumStruct *) arr.mutable_data();
+        auto *ptr = (EnumStruct *) arr.mutable_data();
         for (size_t i = 0; i < n; i++) {
             ptr[i].e1 = static_cast<E1>(-1 + ((int) i % 2) * 2);
             ptr[i].e2 = static_cast<E2>(1 + (i % 2));
@@ -448,7 +557,7 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     // test_complex_array
     m.def("create_complex_array", [](size_t n) {
         py::array_t<ComplexStruct, 0> arr = mkarray_via_buffer<ComplexStruct>(n);
-        auto ptr = (ComplexStruct *) arr.mutable_data();
+        auto *ptr = (ComplexStruct *) arr.mutable_data();
         for (size_t i = 0; i < n; i++) {
             ptr[i].cflt.real(float(i));
             ptr[i].cflt.imag(float(i) + 0.25f);
@@ -471,14 +580,19 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     PYBIND11_NUMPY_DTYPE(CompareStruct, x, y, z);
     m.def("compare_buffer_info", []() {
         py::list list;
-        list.append(py::bool_(py::detail::compare_buffer_info<float>::compare(py::buffer_info(nullptr, sizeof(float), "f", 1))));
-        list.append(py::bool_(py::detail::compare_buffer_info<unsigned>::compare(py::buffer_info(nullptr, sizeof(int), "I", 1))));
-        list.append(py::bool_(py::detail::compare_buffer_info<long>::compare(py::buffer_info(nullptr, sizeof(long), "l", 1))));
-        list.append(py::bool_(py::detail::compare_buffer_info<long>::compare(py::buffer_info(nullptr, sizeof(long), sizeof(long) == sizeof(int) ? "i" : "q", 1))));
-        list.append(py::bool_(py::detail::compare_buffer_info<CompareStruct>::compare(py::buffer_info(nullptr, sizeof(CompareStruct), "T{?:x:3xI:y:f:z:}", 1))));
+        list.append(py::bool_(py::detail::compare_buffer_info<float>::compare(
+            py::buffer_info(nullptr, sizeof(float), "f", 1))));
+        list.append(py::bool_(py::detail::compare_buffer_info<unsigned>::compare(
+            py::buffer_info(nullptr, sizeof(int), "I", 1))));
+        list.append(py::bool_(py::detail::compare_buffer_info<long>::compare(
+            py::buffer_info(nullptr, sizeof(long), "l", 1))));
+        list.append(py::bool_(py::detail::compare_buffer_info<long>::compare(
+            py::buffer_info(nullptr, sizeof(long), sizeof(long) == sizeof(int) ? "i" : "q", 1))));
+        list.append(py::bool_(py::detail::compare_buffer_info<CompareStruct>::compare(
+            py::buffer_info(nullptr, sizeof(CompareStruct), "T{?:x:3xI:y:f:z:}", 1))));
         return list;
     });
-    m.def("buffer_to_dtype", [](py::buffer& buf) { return py::dtype(buf.request()); });
+    m.def("buffer_to_dtype", [](py::buffer &buf) { return py::dtype(buf.request()); });
 
     // test_scalar_conversion
     auto f_simple = [](SimpleStruct s) { return s.uint_ * 10; };
@@ -492,8 +606,9 @@ TEST_SUBMODULE(numpy_dtypes, m) {
     m.def("f_simple_pass_thru_vectorized", py::vectorize(f_simple_pass_thru));
 
     // test_register_dtype
-    m.def("register_dtype", []() { PYBIND11_NUMPY_DTYPE(SimpleStruct, bool_, uint_, float_, ldbl_); });
+    m.def("register_dtype",
+          []() { PYBIND11_NUMPY_DTYPE(SimpleStruct, bool_, uint_, float_, ldbl_); });
 
     // test_str_leak
-    m.def("dtype_wrapper", [](py::object d) { return py::dtype::from_args(std::move(d)); });
+    m.def("dtype_wrapper", [](const py::object &d) { return py::dtype::from_args(d); });
 }
diff --git a/3rdparty/pybind11/tests/test_numpy_dtypes.py b/3rdparty/pybind11/tests/test_numpy_dtypes.py
index f56b776a40..fcfd587b18 100644
--- a/3rdparty/pybind11/tests/test_numpy_dtypes.py
+++ b/3rdparty/pybind11/tests/test_numpy_dtypes.py
@@ -1,10 +1,8 @@
-# -*- coding: utf-8 -*-
 import re
 
 import pytest
 
 import env  # noqa: F401
-
 from pybind11_tests import numpy_dtypes as m
 
 np = pytest.importorskip("numpy")
@@ -16,7 +14,7 @@ def simple_dtype():
     return np.dtype(
         {
             "names": ["bool_", "uint_", "float_", "ldbl_"],
-            "formats": ["?", "u4", "f4", "f{}".format(ld.itemsize)],
+            "formats": ["?", "u4", "f4", f"f{ld.itemsize}"],
             "offsets": [0, 4, 8, (16 if ld.alignment > 4 else 12)],
         }
     )
@@ -33,8 +31,8 @@ def dt_fmt():
     e = "<" if byteorder == "little" else ">"
     return (
         "{{'names':['bool_','uint_','float_','ldbl_'],"
-        " 'formats':['?','" + e + "u4','" + e + "f4','" + e + "f{}'],"
-        " 'offsets':[0,4,8,{}], 'itemsize':{}}}"
+        "'formats':['?','" + e + "u4','" + e + "f4','" + e + "f{}'],"
+        "'offsets':[0,4,8,{}],'itemsize':{}}}"
     )
 
 
@@ -47,7 +45,7 @@ def simple_dtype_fmt():
 def packed_dtype_fmt():
     from sys import byteorder
 
-    return "[('bool_', '?'), ('uint_', '{e}u4'), ('float_', '{e}f4'), ('ldbl_', '{e}f{}')]".format(
+    return "[('bool_','?'),('uint_','{e}u4'),('float_','{e}f4'),('ldbl_','{e}f{}')]".format(
         np.dtype("longdouble").itemsize, e="<" if byteorder == "little" else ">"
     )
 
@@ -64,15 +62,21 @@ def partial_ld_offset():
 def partial_dtype_fmt():
     ld = np.dtype("longdouble")
     partial_ld_off = partial_ld_offset()
-    return dt_fmt().format(ld.itemsize, partial_ld_off, partial_ld_off + ld.itemsize)
+    partial_size = partial_ld_off + ld.itemsize
+    partial_end_padding = partial_size % np.dtype("uint64").alignment
+    return dt_fmt().format(
+        ld.itemsize, partial_ld_off, partial_size + partial_end_padding
+    )
 
 
 def partial_nested_fmt():
     ld = np.dtype("longdouble")
     partial_nested_off = 8 + 8 * (ld.alignment > 8)
     partial_ld_off = partial_ld_offset()
-    partial_nested_size = partial_nested_off * 2 + partial_ld_off + ld.itemsize
-    return "{{'names':['a'], 'formats':[{}], 'offsets':[{}], 'itemsize':{}}}".format(
+    partial_size = partial_ld_off + ld.itemsize
+    partial_end_padding = partial_size % np.dtype("uint64").alignment
+    partial_nested_size = partial_nested_off * 2 + partial_size + partial_end_padding
+    return "{{'names':['a'],'formats':[{}],'offsets':[{}],'itemsize':{}}}".format(
         partial_dtype_fmt(), partial_nested_off, partial_nested_size
     )
 
@@ -92,10 +96,12 @@ def test_format_descriptors():
     ldbl_fmt = ("4x" if ld.alignment > 4 else "") + ld.char
     ss_fmt = "^T{?:bool_:3xI:uint_:f:float_:" + ldbl_fmt + ":ldbl_:}"
     dbl = np.dtype("double")
+    end_padding = ld.itemsize % np.dtype("uint64").alignment
     partial_fmt = (
         "^T{?:bool_:3xI:uint_:f:float_:"
         + str(4 * (dbl.alignment > 4) + dbl.itemsize + 8 * (ld.alignment > 8))
-        + "xg:ldbl_:}"
+        + "xg:ldbl_:"
+        + (str(end_padding) + "x}" if end_padding > 0 else "}")
     )
     nested_extra = str(max(8, ld.alignment))
     assert m.print_format_descriptors() == [
@@ -116,25 +122,25 @@ def test_dtype(simple_dtype):
 
     e = "<" if byteorder == "little" else ">"
 
-    assert m.print_dtypes() == [
+    assert [x.replace(" ", "") for x in m.print_dtypes()] == [
         simple_dtype_fmt(),
         packed_dtype_fmt(),
-        "[('a', {}), ('b', {})]".format(simple_dtype_fmt(), packed_dtype_fmt()),
+        f"[('a',{simple_dtype_fmt()}),('b',{packed_dtype_fmt()})]",
         partial_dtype_fmt(),
         partial_nested_fmt(),
-        "[('a', 'S3'), ('b', 'S3')]",
+        "[('a','S3'),('b','S3')]",
         (
-            "{{'names':['a','b','c','d'], "
-            + "'formats':[('S4', (3,)),('"
+            "{{'names':['a','b','c','d'],"
+            + "'formats':[('S4',(3,)),('"
             + e
-            + "i4', (2,)),('u1', (3,)),('"
+            + "i4',(2,)),('u1',(3,)),('"
             + e
-            + "f4', (4, 2))], "
-            + "'offsets':[0,12,20,24], 'itemsize':56}}"
+            + "f4',(4,2))],"
+            + "'offsets':[0,12,20,24],'itemsize':56}}"
         ).format(e=e),
-        "[('e1', '" + e + "i8'), ('e2', 'u1')]",
-        "[('x', 'i1'), ('y', '" + e + "u8')]",
-        "[('cflt', '" + e + "c8'), ('cdbl', '" + e + "c16')]",
+        "[('e1','" + e + "i8'),('e2','u1')]",
+        "[('x','i1'),('y','" + e + "u8')]",
+        "[('cflt','" + e + "c8'),('cdbl','" + e + "c16')]",
     ]
 
     d1 = np.dtype(
@@ -154,6 +160,7 @@ def test_dtype(simple_dtype):
         d1,
         np.dtype("uint32"),
         d2,
+        np.dtype("d"),
     ]
 
     assert m.test_dtype_methods() == [
@@ -169,6 +176,14 @@ def test_dtype(simple_dtype):
         np.zeros(1, m.trailing_padding_dtype())
     )
 
+    expected_chars = "bhilqBHILQefdgFDG?MmO"
+    assert m.test_dtype_kind() == list("iiiiiuuuuuffffcccbMmO")
+    assert m.test_dtype_char_() == list(expected_chars)
+    assert m.test_dtype_num() == [np.dtype(ch).num for ch in expected_chars]
+    assert m.test_dtype_byteorder() == [np.dtype(ch).byteorder for ch in expected_chars]
+    assert m.test_dtype_alignment() == [np.dtype(ch).alignment for ch in expected_chars]
+    assert m.test_dtype_flags() == [chr(np.dtype(ch).flags) for ch in expected_chars]
+
 
 def test_recarray(simple_dtype, packed_dtype):
     elements = [(False, 0, 0.0, -0.0), (True, 1, 1.5, -2.5), (False, 2, 3.0, -5.0)]
@@ -228,7 +243,7 @@ def test_recarray(simple_dtype, packed_dtype):
     ]
 
     arr = m.create_rec_partial(3)
-    assert str(arr.dtype) == partial_dtype_fmt()
+    assert str(arr.dtype).replace(" ", "") == partial_dtype_fmt()
     partial_dtype = arr.dtype
     assert "" not in arr.dtype.fields
     assert partial_dtype.itemsize > simple_dtype.itemsize
@@ -236,7 +251,7 @@ def test_recarray(simple_dtype, packed_dtype):
     assert_equal(arr, elements, packed_dtype)
 
     arr = m.create_rec_partial_nested(3)
-    assert str(arr.dtype) == partial_nested_fmt()
+    assert str(arr.dtype).replace(" ", "") == partial_nested_fmt()
     assert "" not in arr.dtype.fields
     assert "" not in arr.dtype.fields["a"][0].fields
     assert arr.dtype.itemsize > partial_dtype.itemsize
@@ -275,12 +290,12 @@ def test_array_array():
     e = "<" if byteorder == "little" else ">"
 
     arr = m.create_array_array(3)
-    assert str(arr.dtype) == (
-        "{{'names':['a','b','c','d'], "
-        + "'formats':[('S4', (3,)),('"
+    assert str(arr.dtype).replace(" ", "") == (
+        "{{'names':['a','b','c','d'],"
+        + "'formats':[('S4',(3,)),('"
         + e
-        + "i4', (2,)),('u1', (3,)),('{e}f4', (4, 2))], "
-        + "'offsets':[0,12,20,24], 'itemsize':56}}"
+        + "i4',(2,)),('u1',(3,)),('{e}f4',(4,2))],"
+        + "'offsets':[0,12,20,24],'itemsize':56}}"
     ).format(e=e)
     assert m.print_array_array(arr) == [
         "a={{A,B,C,D},{K,L,M,N},{U,V,W,X}},b={0,1},"
diff --git a/3rdparty/pybind11/tests/test_numpy_vectorize.cpp b/3rdparty/pybind11/tests/test_numpy_vectorize.cpp
index 274b7558a9..dcc4c6ac25 100644
--- a/3rdparty/pybind11/tests/test_numpy_vectorize.cpp
+++ b/3rdparty/pybind11/tests/test_numpy_vectorize.cpp
@@ -8,66 +8,80 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/numpy.h>
 
+#include "pybind11_tests.h"
+
+#include <utility>
+
 double my_func(int x, float y, double z) {
     py::print("my_func(x:int={}, y:float={:.0f}, z:float={:.0f})"_s.format(x, y, z));
-    return (float) x*y*z;
+    return (float) x * y * z;
 }
 
 TEST_SUBMODULE(numpy_vectorize, m) {
-    try { py::module_::import("numpy"); }
-    catch (...) { return; }
+    try {
+        py::module_::import("numpy");
+    } catch (const py::error_already_set &) {
+        return;
+    }
 
     // test_vectorize, test_docs, test_array_collapse
     // Vectorize all arguments of a function (though non-vector arguments are also allowed)
     m.def("vectorized_func", py::vectorize(my_func));
 
-    // Vectorize a lambda function with a capture object (e.g. to exclude some arguments from the vectorization)
-    m.def("vectorized_func2",
-        [](py::array_t<int> x, py::array_t<float> y, float z) {
-            return py::vectorize([z](int x, float y) { return my_func(x, y, z); })(x, y);
-        }
-    );
+    // Vectorize a lambda function with a capture object (e.g. to exclude some arguments from the
+    // vectorization)
+    m.def("vectorized_func2", [](py::array_t<int> x, py::array_t<float> y, float z) {
+        return py::vectorize([z](int x, float y) { return my_func(x, y, z); })(std::move(x),
+                                                                               std::move(y));
+    });
 
     // Vectorize a complex-valued function
-    m.def("vectorized_func3", py::vectorize(
-        [](std::complex<double> c) { return c * std::complex<double>(2.f); }
-    ));
+    m.def("vectorized_func3",
+          py::vectorize([](std::complex<double> c) { return c * std::complex<double>(2.f); }));
 
     // test_type_selection
     // NumPy function which only accepts specific data types
-    m.def("selective_func", [](py::array_t<int, py::array::c_style>) { return "Int branch taken."; });
-    m.def("selective_func", [](py::array_t<float, py::array::c_style>) { return "Float branch taken."; });
-    m.def("selective_func", [](py::array_t<std::complex<float>, py::array::c_style>) { return "Complex float branch taken."; });
-
+    // A lot of these no lints could be replaced with const refs, and probably should at some
+    // point.
+    m.def("selective_func",
+          [](const py::array_t<int, py::array::c_style> &) { return "Int branch taken."; });
+    m.def("selective_func",
+          [](const py::array_t<float, py::array::c_style> &) { return "Float branch taken."; });
+    m.def("selective_func", [](const py::array_t<std::complex<float>, py::array::c_style> &) {
+        return "Complex float branch taken.";
+    });
 
     // test_passthrough_arguments
-    // Passthrough test: references and non-pod types should be automatically passed through (in the
-    // function definition below, only `b`, `d`, and `g` are vectorized):
+    // Passthrough test: references and non-pod types should be automatically passed through (in
+    // the function definition below, only `b`, `d`, and `g` are vectorized):
     struct NonPODClass {
-        NonPODClass(int v) : value{v} {}
+        explicit NonPODClass(int v) : value{v} {}
         int value;
     };
     py::class_<NonPODClass>(m, "NonPODClass")
         .def(py::init<int>())
         .def_readwrite("value", &NonPODClass::value);
-    m.def("vec_passthrough", py::vectorize(
-        [](double *a, double b, py::array_t<double> c, const int &d, int &e, NonPODClass f, const double g) {
-            return *a + b + c.at(0) + d + e + f.value + g;
-        }
-    ));
+    m.def("vec_passthrough",
+          py::vectorize([](const double *a,
+                           double b,
+                           // Changing this broke things
+                           // NOLINTNEXTLINE(performance-unnecessary-value-param)
+                           py::array_t<double> c,
+                           const int &d,
+                           int &e,
+                           NonPODClass f,
+                           const double g) { return *a + b + c.at(0) + d + e + f.value + g; }));
 
     // test_method_vectorization
     struct VectorizeTestClass {
-        VectorizeTestClass(int v) : value{v} {};
-        float method(int x, float y) { return y + (float) (x + value); }
+        explicit VectorizeTestClass(int v) : value{v} {};
+        float method(int x, float y) const { return y + (float) (x + value); }
         int value = 0;
     };
     py::class_<VectorizeTestClass> vtc(m, "VectorizeTestClass");
-    vtc .def(py::init<int>())
-        .def_readwrite("value", &VectorizeTestClass::value);
+    vtc.def(py::init<int>()).def_readwrite("value", &VectorizeTestClass::value);
 
     // Automatic vectorizing of methods
     vtc.def("method", py::vectorize(&VectorizeTestClass::method));
@@ -78,16 +92,16 @@ TEST_SUBMODULE(numpy_vectorize, m) {
         .value("f_trivial", py::detail::broadcast_trivial::f_trivial)
         .value("c_trivial", py::detail::broadcast_trivial::c_trivial)
         .value("non_trivial", py::detail::broadcast_trivial::non_trivial);
-    m.def("vectorized_is_trivial", [](
-                py::array_t<int, py::array::forcecast> arg1,
-                py::array_t<float, py::array::forcecast> arg2,
-                py::array_t<double, py::array::forcecast> arg3
-                ) {
-        py::ssize_t ndim;
-        std::vector<py::ssize_t> shape;
-        std::array<py::buffer_info, 3> buffers {{ arg1.request(), arg2.request(), arg3.request() }};
-        return py::detail::broadcast(buffers, ndim, shape);
-    });
+    m.def("vectorized_is_trivial",
+          [](const py::array_t<int, py::array::forcecast> &arg1,
+             const py::array_t<float, py::array::forcecast> &arg2,
+             const py::array_t<double, py::array::forcecast> &arg3) {
+              py::ssize_t ndim = 0;
+              std::vector<py::ssize_t> shape;
+              std::array<py::buffer_info, 3> buffers{
+                  {arg1.request(), arg2.request(), arg3.request()}};
+              return py::detail::broadcast(buffers, ndim, shape);
+          });
 
-    m.def("add_to", py::vectorize([](NonPODClass& x, int a) { x.value += a; }));
+    m.def("add_to", py::vectorize([](NonPODClass &x, int a) { x.value += a; }));
 }
diff --git a/3rdparty/pybind11/tests/test_numpy_vectorize.py b/3rdparty/pybind11/tests/test_numpy_vectorize.py
index 4e6b2d1982..7e8c015c46 100644
--- a/3rdparty/pybind11/tests/test_numpy_vectorize.py
+++ b/3rdparty/pybind11/tests/test_numpy_vectorize.py
@@ -1,5 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
+
 from pybind11_tests import numpy_vectorize as m
 
 np = pytest.importorskip("numpy")
diff --git a/3rdparty/pybind11/tests/test_opaque_types.cpp b/3rdparty/pybind11/tests/test_opaque_types.cpp
index 5a23431635..0386dba03d 100644
--- a/3rdparty/pybind11/tests/test_opaque_types.cpp
+++ b/3rdparty/pybind11/tests/test_opaque_types.cpp
@@ -7,8 +7,10 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/stl.h>
+
+#include "pybind11_tests.h"
+
 #include <vector>
 
 // IMPORTANT: Disable internal pybind11 translation mechanisms for STL data structures
@@ -26,12 +28,13 @@ TEST_SUBMODULE(opaque_types, m) {
         .def(py::init<>())
         .def("pop_back", &StringList::pop_back)
         /* There are multiple versions of push_back(), etc. Select the right ones. */
-        .def("push_back", (void (StringList::*)(const std::string &)) &StringList::push_back)
-        .def("back", (std::string &(StringList::*)()) &StringList::back)
+        .def("push_back", (void(StringList::*)(const std::string &)) & StringList::push_back)
+        .def("back", (std::string & (StringList::*) ()) & StringList::back)
         .def("__len__", [](const StringList &v) { return v.size(); })
-        .def("__iter__", [](StringList &v) {
-           return py::make_iterator(v.begin(), v.end());
-        }, py::keep_alive<0, 1>());
+        .def(
+            "__iter__",
+            [](StringList &v) { return py::make_iterator(v.begin(), v.end()); },
+            py::keep_alive<0, 1>());
 
     class ClassWithSTLVecProperty {
     public:
@@ -44,9 +47,10 @@ TEST_SUBMODULE(opaque_types, m) {
     m.def("print_opaque_list", [](const StringList &l) {
         std::string ret = "Opaque list: [";
         bool first = true;
-        for (auto entry : l) {
-            if (!first)
+        for (const auto &entry : l) {
+            if (!first) {
                 ret += ", ";
+            }
             ret += entry;
             first = false;
         }
diff --git a/3rdparty/pybind11/tests/test_opaque_types.py b/3rdparty/pybind11/tests/test_opaque_types.py
index 773794634c..5d4f2a1bf4 100644
--- a/3rdparty/pybind11/tests/test_opaque_types.py
+++ b/3rdparty/pybind11/tests/test_opaque_types.py
@@ -1,7 +1,7 @@
-# -*- coding: utf-8 -*-
 import pytest
-from pybind11_tests import opaque_types as m
+
 from pybind11_tests import ConstructorStats, UserType
+from pybind11_tests import opaque_types as m
 
 
 def test_string_list():
@@ -12,7 +12,7 @@ def test_string_list():
     assert lst.back() == "Element 2"
 
     for i, k in enumerate(lst, start=1):
-        assert k == "Element {}".format(i)
+        assert k == f"Element {i}"
     lst.pop_back()
     assert m.print_opaque_list(lst) == "Opaque list: [Element 1]"
 
@@ -39,7 +39,7 @@ def test_pointers(msg):
             1. (arg0: capsule) -> int
 
         Invoked with: [1, 2, 3]
-    """  # noqa: E501 line too long
+    """
     )
 
     assert m.return_null_str() is None
diff --git a/3rdparty/pybind11/tests/test_operator_overloading.cpp b/3rdparty/pybind11/tests/test_operator_overloading.cpp
index 0a27bfd57b..a4b895a897 100644
--- a/3rdparty/pybind11/tests/test_operator_overloading.cpp
+++ b/3rdparty/pybind11/tests/test_operator_overloading.cpp
@@ -7,21 +7,40 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/operators.h>
+#include <pybind11/stl.h>
+
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 #include <functional>
 
 class Vector2 {
 public:
     Vector2(float x, float y) : x(x), y(y) { print_created(this, toString()); }
     Vector2(const Vector2 &v) : x(v.x), y(v.y) { print_copy_created(this); }
-    Vector2(Vector2 &&v) : x(v.x), y(v.y) { print_move_created(this); v.x = v.y = 0; }
-    Vector2 &operator=(const Vector2 &v) { x = v.x; y = v.y; print_copy_assigned(this); return *this; }
-    Vector2 &operator=(Vector2 &&v) { x = v.x; y = v.y; v.x = v.y = 0; print_move_assigned(this); return *this; }
+    Vector2(Vector2 &&v) noexcept : x(v.x), y(v.y) {
+        print_move_created(this);
+        v.x = v.y = 0;
+    }
+    Vector2 &operator=(const Vector2 &v) {
+        x = v.x;
+        y = v.y;
+        print_copy_assigned(this);
+        return *this;
+    }
+    Vector2 &operator=(Vector2 &&v) noexcept {
+        x = v.x;
+        y = v.y;
+        v.x = v.y = 0;
+        print_move_assigned(this);
+        return *this;
+    }
     ~Vector2() { print_destroyed(this); }
 
-    std::string toString() const { return "[" + std::to_string(x) + ", " + std::to_string(y) + "]"; }
+    std::string toString() const {
+        return "[" + std::to_string(x) + ", " + std::to_string(y) + "]";
+    }
 
     Vector2 operator-() const { return Vector2(-x, -y); }
     Vector2 operator+(const Vector2 &v) const { return Vector2(x + v.x, y + v.y); }
@@ -32,71 +51,104 @@ class Vector2 {
     Vector2 operator/(float value) const { return Vector2(x / value, y / value); }
     Vector2 operator*(const Vector2 &v) const { return Vector2(x * v.x, y * v.y); }
     Vector2 operator/(const Vector2 &v) const { return Vector2(x / v.x, y / v.y); }
-    Vector2& operator+=(const Vector2 &v) { x += v.x; y += v.y; return *this; }
-    Vector2& operator-=(const Vector2 &v) { x -= v.x; y -= v.y; return *this; }
-    Vector2& operator*=(float v) { x *= v; y *= v; return *this; }
-    Vector2& operator/=(float v) { x /= v; y /= v; return *this; }
-    Vector2& operator*=(const Vector2 &v) { x *= v.x; y *= v.y; return *this; }
-    Vector2& operator/=(const Vector2 &v) { x /= v.x; y /= v.y; return *this; }
+    Vector2 &operator+=(const Vector2 &v) {
+        x += v.x;
+        y += v.y;
+        return *this;
+    }
+    Vector2 &operator-=(const Vector2 &v) {
+        x -= v.x;
+        y -= v.y;
+        return *this;
+    }
+    Vector2 &operator*=(float v) {
+        x *= v;
+        y *= v;
+        return *this;
+    }
+    Vector2 &operator/=(float v) {
+        x /= v;
+        y /= v;
+        return *this;
+    }
+    Vector2 &operator*=(const Vector2 &v) {
+        x *= v.x;
+        y *= v.y;
+        return *this;
+    }
+    Vector2 &operator/=(const Vector2 &v) {
+        x /= v.x;
+        y /= v.y;
+        return *this;
+    }
 
     friend Vector2 operator+(float f, const Vector2 &v) { return Vector2(f + v.x, f + v.y); }
     friend Vector2 operator-(float f, const Vector2 &v) { return Vector2(f - v.x, f - v.y); }
     friend Vector2 operator*(float f, const Vector2 &v) { return Vector2(f * v.x, f * v.y); }
     friend Vector2 operator/(float f, const Vector2 &v) { return Vector2(f / v.x, f / v.y); }
 
-    bool operator==(const Vector2 &v) const {
-        return x == v.x && y == v.y;
-    }
-    bool operator!=(const Vector2 &v) const {
-        return x != v.x || y != v.y;
-    }
+    bool operator==(const Vector2 &v) const { return x == v.x && y == v.y; }
+    bool operator!=(const Vector2 &v) const { return x != v.x || y != v.y; }
+
 private:
     float x, y;
 };
 
-class C1 { };
-class C2 { };
+class C1 {};
+class C2 {};
 
 int operator+(const C1 &, const C1 &) { return 11; }
 int operator+(const C2 &, const C2 &) { return 22; }
 int operator+(const C2 &, const C1 &) { return 21; }
 int operator+(const C1 &, const C2 &) { return 12; }
 
+struct HashMe {
+    std::string member;
+};
+
+bool operator==(const HashMe &lhs, const HashMe &rhs) { return lhs.member == rhs.member; }
+
 // Note: Specializing explicit within `namespace std { ... }` is done due to a
 // bug in GCC<7. If you are supporting compilers later than this, consider
 // specializing `using template<> struct std::hash<...>` in the global
 // namespace instead, per this recommendation:
 // https://en.cppreference.com/w/cpp/language/extending_std#Adding_template_specializations
 namespace std {
-    template<>
-    struct hash<Vector2> {
-        // Not a good hash function, but easy to test
-        size_t operator()(const Vector2 &) { return 4; }
-    };
+template <>
+struct hash<Vector2> {
+    // Not a good hash function, but easy to test
+    size_t operator()(const Vector2 &) { return 4; }
+};
+
+// HashMe has a hash function in C++ but no `__hash__` for Python.
+template <>
+struct hash<HashMe> {
+    std::size_t operator()(const HashMe &selector) const {
+        return std::hash<std::string>()(selector.member);
+    }
+};
 } // namespace std
 
 // Not a good abs function, but easy to test.
-std::string abs(const Vector2&) {
-    return "abs(Vector2)";
-}
+std::string abs(const Vector2 &) { return "abs(Vector2)"; }
 
-// MSVC warns about unknown pragmas, and warnings are errors.
-#ifndef _MSC_VER
-  #pragma GCC diagnostic push
-  // clang 7.0.0 and Apple LLVM 10.0.1 introduce `-Wself-assign-overloaded` to
-  // `-Wall`, which is used here for overloading (e.g. `py::self += py::self `).
-  // Here, we suppress the warning using `#pragma diagnostic`.
-  // Taken from: https://github.com/RobotLocomotion/drake/commit/aaf84b46
-  // TODO(eric): This could be resolved using a function / functor (e.g. `py::self()`).
-  #if defined(__APPLE__) && defined(__clang__)
-    #if (__clang_major__ >= 10)
-      #pragma GCC diagnostic ignored "-Wself-assign-overloaded"
-    #endif
-  #elif defined(__clang__)
-    #if (__clang_major__ >= 7)
-      #pragma GCC diagnostic ignored "-Wself-assign-overloaded"
-    #endif
-  #endif
+// MSVC & Intel warns about unknown pragmas, and warnings are errors.
+#if !defined(_MSC_VER) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic push
+// clang 7.0.0 and Apple LLVM 10.0.1 introduce `-Wself-assign-overloaded` to
+// `-Wall`, which is used here for overloading (e.g. `py::self += py::self `).
+// Here, we suppress the warning using `#pragma diagnostic`.
+// Taken from: https://github.com/RobotLocomotion/drake/commit/aaf84b46
+// TODO(eric): This could be resolved using a function / functor (e.g. `py::self()`).
+#    if defined(__APPLE__) && defined(__clang__)
+#        if (__clang_major__ >= 10)
+#            pragma GCC diagnostic ignored "-Wself-assign-overloaded"
+#        endif
+#    elif defined(__clang__)
+#        if (__clang_major__ >= 7)
+#            pragma GCC diagnostic ignored "-Wself-assign-overloaded"
+#        endif
+#    endif
 #endif
 
 TEST_SUBMODULE(operators, m) {
@@ -130,46 +182,52 @@ TEST_SUBMODULE(operators, m) {
         .def(py::hash(py::self))
         // N.B. See warning about usage of `py::detail::abs(py::self)` in
         // `operators.h`.
-        .def("__abs__", [](const Vector2& v) { return abs(v); })
-        ;
+        .def("__abs__", [](const Vector2 &v) { return abs(v); });
 
     m.attr("Vector") = m.attr("Vector2");
 
     // test_operators_notimplemented
     // #393: need to return NotSupported to ensure correct arithmetic operator behavior
-    py::class_<C1>(m, "C1")
-        .def(py::init<>())
-        .def(py::self + py::self);
+    py::class_<C1>(m, "C1").def(py::init<>()).def(py::self + py::self);
 
     py::class_<C2>(m, "C2")
         .def(py::init<>())
         .def(py::self + py::self)
-        .def("__add__", [](const C2& c2, const C1& c1) { return c2 + c1; })
-        .def("__radd__", [](const C2& c2, const C1& c1) { return c1 + c2; });
+        .def("__add__", [](const C2 &c2, const C1 &c1) { return c2 + c1; })
+        .def("__radd__", [](const C2 &c2, const C1 &c1) { return c1 + c2; });
 
     // test_nested
     // #328: first member in a class can't be used in operators
-    struct NestABase { int value = -2; };
+    struct NestABase {
+        int value = -2;
+    };
     py::class_<NestABase>(m, "NestABase")
         .def(py::init<>())
         .def_readwrite("value", &NestABase::value);
 
     struct NestA : NestABase {
         int value = 3;
-        NestA& operator+=(int i) { value += i; return *this; }
+        NestA &operator+=(int i) {
+            value += i;
+            return *this;
+        }
     };
     py::class_<NestA>(m, "NestA")
         .def(py::init<>())
         .def(py::self += int())
-        .def("as_base", [](NestA &a) -> NestABase& {
-            return (NestABase&) a;
-        }, py::return_value_policy::reference_internal);
+        .def(
+            "as_base",
+            [](NestA &a) -> NestABase & { return (NestABase &) a; },
+            py::return_value_policy::reference_internal);
     m.def("get_NestA", [](const NestA &a) { return a.value; });
 
     struct NestB {
         NestA a;
         int value = 4;
-        NestB& operator-=(int i) { value -= i; return *this; }
+        NestB &operator-=(int i) {
+            value -= i;
+            return *this;
+        }
     };
     py::class_<NestB>(m, "NestB")
         .def(py::init<>())
@@ -180,7 +238,10 @@ TEST_SUBMODULE(operators, m) {
     struct NestC {
         NestB b;
         int value = 5;
-        NestC& operator*=(int i) { value *= i; return *this; }
+        NestC &operator*=(int i) {
+            value *= i;
+            return *this;
+        }
     };
     py::class_<NestC>(m, "NestC")
         .def(py::init<>())
@@ -188,16 +249,15 @@ TEST_SUBMODULE(operators, m) {
         .def_readwrite("b", &NestC::b);
     m.def("get_NestC", [](const NestC &c) { return c.value; });
 
-
     // test_overriding_eq_reset_hash
     // #2191 Overriding __eq__ should set __hash__ to None
     struct Comparable {
         int value;
-        bool operator==(const Comparable& rhs) const {return value == rhs.value;}
+        bool operator==(const Comparable &rhs) const { return value == rhs.value; }
     };
 
     struct Hashable : Comparable {
-        explicit Hashable(int value): Comparable{value}{};
+        explicit Hashable(int value) : Comparable{value} {};
         size_t hash() const { return static_cast<size_t>(value); }
     };
 
@@ -205,9 +265,7 @@ TEST_SUBMODULE(operators, m) {
         using Hashable::Hashable;
     };
 
-    py::class_<Comparable>(m, "Comparable")
-        .def(py::init<int>())
-        .def(py::self == py::self);
+    py::class_<Comparable>(m, "Comparable").def(py::init<int>()).def(py::self == py::self);
 
     py::class_<Hashable>(m, "Hashable")
         .def(py::init<int>())
@@ -219,8 +277,12 @@ TEST_SUBMODULE(operators, m) {
         .def("__hash__", &Hashable::hash)
         .def(py::init<int>())
         .def(py::self == py::self);
-}
 
-#ifndef _MSC_VER
-  #pragma GCC diagnostic pop
+    // define __eq__ but not __hash__
+    py::class_<HashMe>(m, "HashMe").def(py::self == py::self);
+
+    m.def("get_unhashable_HashMe_set", []() { return std::unordered_set<HashMe>{{"one"}}; });
+}
+#if !defined(_MSC_VER) && !defined(__INTEL_COMPILER)
+#    pragma GCC diagnostic pop
 #endif
diff --git a/3rdparty/pybind11/tests/test_operator_overloading.py b/3rdparty/pybind11/tests/test_operator_overloading.py
index 5dbfb32c8a..b228da3cc3 100644
--- a/3rdparty/pybind11/tests/test_operator_overloading.py
+++ b/3rdparty/pybind11/tests/test_operator_overloading.py
@@ -1,7 +1,7 @@
-# -*- coding: utf-8 -*-
 import pytest
-from pybind11_tests import operators as m
+
 from pybind11_tests import ConstructorStats
+from pybind11_tests import operators as m
 
 
 def test_operator_overloading():
@@ -134,8 +134,9 @@ def test_overriding_eq_reset_hash():
     assert m.Comparable(15) is not m.Comparable(15)
     assert m.Comparable(15) == m.Comparable(15)
 
-    with pytest.raises(TypeError):
-        hash(m.Comparable(15))  # TypeError: unhashable type: 'm.Comparable'
+    with pytest.raises(TypeError) as excinfo:
+        hash(m.Comparable(15))
+    assert str(excinfo.value).startswith("unhashable type:")
 
     for hashable in (m.Hashable, m.Hashable2):
         assert hashable(15) is not hashable(15)
@@ -143,3 +144,9 @@ def test_overriding_eq_reset_hash():
 
         assert hash(hashable(15)) == 15
         assert hash(hashable(15)) == hash(hashable(15))
+
+
+def test_return_set_of_unhashable():
+    with pytest.raises(TypeError) as excinfo:
+        m.get_unhashable_HashMe_set()
+    assert str(excinfo.value.__cause__).startswith("unhashable type:")
diff --git a/3rdparty/pybind11/tests/test_pickling.cpp b/3rdparty/pybind11/tests/test_pickling.cpp
index 9dc63bda3b..e154bc483c 100644
--- a/3rdparty/pybind11/tests/test_pickling.cpp
+++ b/3rdparty/pybind11/tests/test_pickling.cpp
@@ -2,6 +2,7 @@
     tests/test_pickling.cpp -- pickle support
 
     Copyright (c) 2016 Wenzel Jakob <wenzel.jakob@epfl.ch>
+    Copyright (c) 2021 The Pybind Development Team.
 
     All rights reserved. Use of this source code is governed by a
     BSD-style license that can be found in the LICENSE file.
@@ -9,17 +10,70 @@
 
 #include "pybind11_tests.h"
 
+#include <memory>
+#include <stdexcept>
+#include <utility>
+
+namespace exercise_trampoline {
+
+struct SimpleBase {
+    int num = 0;
+    virtual ~SimpleBase() = default;
+
+    // For compatibility with old clang versions:
+    SimpleBase() = default;
+    SimpleBase(const SimpleBase &) = default;
+};
+
+struct SimpleBaseTrampoline : SimpleBase {};
+
+struct SimpleCppDerived : SimpleBase {};
+
+void wrap(py::module m) {
+    py::class_<SimpleBase, SimpleBaseTrampoline>(m, "SimpleBase")
+        .def(py::init<>())
+        .def_readwrite("num", &SimpleBase::num)
+        .def(py::pickle(
+            [](const py::object &self) {
+                py::dict d;
+                if (py::hasattr(self, "__dict__")) {
+                    d = self.attr("__dict__");
+                }
+                return py::make_tuple(self.attr("num"), d);
+            },
+            [](const py::tuple &t) {
+                if (t.size() != 2) {
+                    throw std::runtime_error("Invalid state!");
+                }
+                auto cpp_state = std::unique_ptr<SimpleBase>(new SimpleBaseTrampoline);
+                cpp_state->num = t[0].cast<int>();
+                auto py_state = t[1].cast<py::dict>();
+                return std::make_pair(std::move(cpp_state), py_state);
+            }));
+
+    m.def("make_SimpleCppDerivedAsBase",
+          []() { return std::unique_ptr<SimpleBase>(new SimpleCppDerived); });
+    m.def("check_dynamic_cast_SimpleCppDerived", [](const SimpleBase *base_ptr) {
+        return dynamic_cast<const SimpleCppDerived *>(base_ptr) != nullptr;
+    });
+}
+
+} // namespace exercise_trampoline
+
 TEST_SUBMODULE(pickling, m) {
+    m.def("simple_callable", []() { return 20220426; });
+
     // test_roundtrip
     class Pickleable {
     public:
-        Pickleable(const std::string &value) : m_value(value) { }
+        explicit Pickleable(const std::string &value) : m_value(value) {}
         const std::string &value() const { return m_value; }
 
         void setExtra1(int extra1) { m_extra1 = extra1; }
         void setExtra2(int extra2) { m_extra2 = extra2; }
         int extra1() const { return m_extra1; }
         int extra2() const { return m_extra2; }
+
     private:
         std::string m_value;
         int m_extra1 = 0;
@@ -31,8 +85,8 @@ TEST_SUBMODULE(pickling, m) {
         using Pickleable::Pickleable;
     };
 
-    py::class_<Pickleable>(m, "Pickleable")
-        .def(py::init<std::string>())
+    py::class_<Pickleable> pyPickleable(m, "Pickleable");
+    pyPickleable.def(py::init<std::string>())
         .def("value", &Pickleable::value)
         .def("extra1", &Pickleable::extra1)
         .def("extra2", &Pickleable::extra2)
@@ -43,10 +97,12 @@ TEST_SUBMODULE(pickling, m) {
         .def("__getstate__", [](const Pickleable &p) {
             /* Return a tuple that fully encodes the state of the object */
             return py::make_tuple(p.value(), p.extra1(), p.extra2());
-        })
-        .def("__setstate__", [](Pickleable &p, py::tuple t) {
-            if (t.size() != 3)
+        });
+    ignoreOldStyleInitWarnings([&pyPickleable]() {
+        pyPickleable.def("__setstate__", [](Pickleable &p, const py::tuple &t) {
+            if (t.size() != 3) {
                 throw std::runtime_error("Invalid state!");
+            }
             /* Invoke the constructor (need to use in-place version) */
             new (&p) Pickleable(t[0].cast<std::string>());
 
@@ -54,6 +110,7 @@ TEST_SUBMODULE(pickling, m) {
             p.setExtra1(t[1].cast<int>());
             p.setExtra2(t[2].cast<int>());
         });
+    });
 
     py::class_<PickleableNew, Pickleable>(m, "PickleableNew")
         .def(py::init<std::string>())
@@ -61,22 +118,22 @@ TEST_SUBMODULE(pickling, m) {
             [](const PickleableNew &p) {
                 return py::make_tuple(p.value(), p.extra1(), p.extra2());
             },
-            [](py::tuple t) {
-                if (t.size() != 3)
+            [](const py::tuple &t) {
+                if (t.size() != 3) {
                     throw std::runtime_error("Invalid state!");
+                }
                 auto p = PickleableNew(t[0].cast<std::string>());
 
                 p.setExtra1(t[1].cast<int>());
                 p.setExtra2(t[2].cast<int>());
                 return p;
-            }
-        ));
+            }));
 
 #if !defined(PYPY_VERSION)
     // test_roundtrip_with_dict
     class PickleableWithDict {
     public:
-        PickleableWithDict(const std::string &value) : value(value) { }
+        explicit PickleableWithDict(const std::string &value) : value(value) {}
 
         std::string value;
         int extra;
@@ -87,19 +144,22 @@ TEST_SUBMODULE(pickling, m) {
         using PickleableWithDict::PickleableWithDict;
     };
 
-    py::class_<PickleableWithDict>(m, "PickleableWithDict", py::dynamic_attr())
-        .def(py::init<std::string>())
+    py::class_<PickleableWithDict> pyPickleableWithDict(
+        m, "PickleableWithDict", py::dynamic_attr());
+    pyPickleableWithDict.def(py::init<std::string>())
         .def_readwrite("value", &PickleableWithDict::value)
         .def_readwrite("extra", &PickleableWithDict::extra)
-        .def("__getstate__", [](py::object self) {
+        .def("__getstate__", [](const py::object &self) {
             /* Also include __dict__ in state */
             return py::make_tuple(self.attr("value"), self.attr("extra"), self.attr("__dict__"));
-        })
-        .def("__setstate__", [](py::object self, py::tuple t) {
-            if (t.size() != 3)
+        });
+    ignoreOldStyleInitWarnings([&pyPickleableWithDict]() {
+        pyPickleableWithDict.def("__setstate__", [](const py::object &self, const py::tuple &t) {
+            if (t.size() != 3) {
                 throw std::runtime_error("Invalid state!");
+            }
             /* Cast and construct */
-            auto& p = self.cast<PickleableWithDict&>();
+            auto &p = self.cast<PickleableWithDict &>();
             new (&p) PickleableWithDict(t[0].cast<std::string>());
 
             /* Assign C++ state */
@@ -108,23 +168,27 @@ TEST_SUBMODULE(pickling, m) {
             /* Assign Python state */
             self.attr("__dict__") = t[2];
         });
+    });
 
     py::class_<PickleableWithDictNew, PickleableWithDict>(m, "PickleableWithDictNew")
         .def(py::init<std::string>())
         .def(py::pickle(
-            [](py::object self) {
-                return py::make_tuple(self.attr("value"), self.attr("extra"), self.attr("__dict__"));
+            [](const py::object &self) {
+                return py::make_tuple(
+                    self.attr("value"), self.attr("extra"), self.attr("__dict__"));
             },
             [](const py::tuple &t) {
-                if (t.size() != 3)
+                if (t.size() != 3) {
                     throw std::runtime_error("Invalid state!");
+                }
 
                 auto cpp_state = PickleableWithDictNew(t[0].cast<std::string>());
                 cpp_state.extra = t[1].cast<int>();
 
                 auto py_state = t[2].cast<py::dict>();
                 return std::make_pair(cpp_state, py_state);
-            }
-        ));
+            }));
 #endif
+
+    exercise_trampoline::wrap(m);
 }
diff --git a/3rdparty/pybind11/tests/test_pickling.py b/3rdparty/pybind11/tests/test_pickling.py
index 6b27a73a57..12361a661e 100644
--- a/3rdparty/pybind11/tests/test_pickling.py
+++ b/3rdparty/pybind11/tests/test_pickling.py
@@ -1,14 +1,24 @@
-# -*- coding: utf-8 -*-
-import pytest
+import pickle
+import re
 
-import env  # noqa: F401
+import pytest
 
+import env
 from pybind11_tests import pickling as m
 
-try:
-    import cPickle as pickle  # Use cPickle on Python 2.7
-except ImportError:
-    import pickle
+
+def test_pickle_simple_callable():
+    assert m.simple_callable() == 20220426
+    if env.PYPY:
+        serialized = pickle.dumps(m.simple_callable)
+        deserialized = pickle.loads(serialized)
+        assert deserialized() == 20220426
+    else:
+        # To document broken behavior: currently it fails universally with
+        # all C Python versions.
+        with pytest.raises(TypeError) as excinfo:
+            pickle.dumps(m.simple_callable)
+        assert re.search("can.*t pickle .*PyCapsule.* object", str(excinfo.value))
 
 
 @pytest.mark.parametrize("cls_name", ["Pickleable", "PickleableNew"])
@@ -45,3 +55,39 @@ def test_enum_pickle():
 
     data = pickle.dumps(e.EOne, 2)
     assert e.EOne == pickle.loads(data)
+
+
+#
+# exercise_trampoline
+#
+class SimplePyDerived(m.SimpleBase):
+    pass
+
+
+def test_roundtrip_simple_py_derived():
+    p = SimplePyDerived()
+    p.num = 202
+    p.stored_in_dict = 303
+    data = pickle.dumps(p, pickle.HIGHEST_PROTOCOL)
+    p2 = pickle.loads(data)
+    assert isinstance(p2, SimplePyDerived)
+    assert p2.num == 202
+    assert p2.stored_in_dict == 303
+
+
+def test_roundtrip_simple_cpp_derived():
+    p = m.make_SimpleCppDerivedAsBase()
+    assert m.check_dynamic_cast_SimpleCppDerived(p)
+    p.num = 404
+    if not env.PYPY:
+        # To ensure that this unit test is not accidentally invalidated.
+        with pytest.raises(AttributeError):
+            # Mimics the `setstate` C++ implementation.
+            setattr(p, "__dict__", {})  # noqa: B010
+    data = pickle.dumps(p, pickle.HIGHEST_PROTOCOL)
+    p2 = pickle.loads(data)
+    assert isinstance(p2, m.SimpleBase)
+    assert p2.num == 404
+    # Issue #3062: pickleable base C++ classes can incur object slicing
+    #              if derived typeid is not registered with pybind11
+    assert not m.check_dynamic_cast_SimpleCppDerived(p2)
diff --git a/3rdparty/pybind11/tests/test_pytypes.cpp b/3rdparty/pybind11/tests/test_pytypes.cpp
index 113cf5cbbc..da0dc8f6ba 100644
--- a/3rdparty/pybind11/tests/test_pytypes.cpp
+++ b/3rdparty/pybind11/tests/test_pytypes.cpp
@@ -9,15 +9,119 @@
 
 #include "pybind11_tests.h"
 
+#include <utility>
+
+namespace external {
+namespace detail {
+bool check(PyObject *o) { return PyFloat_Check(o) != 0; }
+
+PyObject *conv(PyObject *o) {
+    PyObject *ret = nullptr;
+    if (PyLong_Check(o)) {
+        double v = PyLong_AsDouble(o);
+        if (!(v == -1.0 && PyErr_Occurred())) {
+            ret = PyFloat_FromDouble(v);
+        }
+    } else {
+        PyErr_SetString(PyExc_TypeError, "Unexpected type");
+    }
+    return ret;
+}
+
+PyObject *default_constructed() { return PyFloat_FromDouble(0.0); }
+} // namespace detail
+class float_ : public py::object {
+    PYBIND11_OBJECT_CVT(float_, py::object, external::detail::check, external::detail::conv)
+
+    float_() : py::object(external::detail::default_constructed(), stolen_t{}) {}
+
+    double get_value() const { return PyFloat_AsDouble(this->ptr()); }
+};
+} // namespace external
+
+namespace implicit_conversion_from_0_to_handle {
+// Uncomment to trigger compiler error. Note: Before PR #4008 this used to compile successfully.
+// void expected_to_trigger_compiler_error() { py::handle(0); }
+} // namespace implicit_conversion_from_0_to_handle
+
+// Used to validate systematically that PR #4008 does/did NOT change the behavior.
+void pure_compile_tests_for_handle_from_PyObject_pointers() {
+    {
+        PyObject *ptr = Py_None;
+        py::handle{ptr};
+    }
+    {
+        PyObject *const ptr = Py_None;
+        py::handle{ptr};
+    }
+    // Uncomment to trigger compiler errors.
+    // PyObject const *               ptr = Py_None; py::handle{ptr};
+    // PyObject const *const          ptr = Py_None; py::handle{ptr};
+    // PyObject volatile *            ptr = Py_None; py::handle{ptr};
+    // PyObject volatile *const       ptr = Py_None; py::handle{ptr};
+    // PyObject const volatile *      ptr = Py_None; py::handle{ptr};
+    // PyObject const volatile *const ptr = Py_None; py::handle{ptr};
+}
+
+namespace handle_from_move_only_type_with_operator_PyObject {
+
+// Reduced from
+// https://github.com/pytorch/pytorch/blob/279634f384662b7c3a9f8bf7ccc3a6afd2f05657/torch/csrc/utils/object_ptr.h
+struct operator_ncnst {
+    operator_ncnst() = default;
+    operator_ncnst(operator_ncnst &&) = default;
+    operator PyObject *() /* */ { return Py_None; } // NOLINT(google-explicit-constructor)
+};
+
+struct operator_const {
+    operator_const() = default;
+    operator_const(operator_const &&) = default;
+    operator PyObject *() const { return Py_None; } // NOLINT(google-explicit-constructor)
+};
+
+bool from_ncnst() {
+    operator_ncnst obj;
+    auto h = py::handle(obj);  // Critical part of test: does this compile?
+    return h.ptr() == Py_None; // Just something.
+}
+
+bool from_const() {
+    operator_const obj;
+    auto h = py::handle(obj);  // Critical part of test: does this compile?
+    return h.ptr() == Py_None; // Just something.
+}
+
+void m_defs(py::module_ &m) {
+    m.def("handle_from_move_only_type_with_operator_PyObject_ncnst", from_ncnst);
+    m.def("handle_from_move_only_type_with_operator_PyObject_const", from_const);
+}
+
+} // namespace handle_from_move_only_type_with_operator_PyObject
 
 TEST_SUBMODULE(pytypes, m) {
+    handle_from_move_only_type_with_operator_PyObject::m_defs(m);
+
+    // test_bool
+    m.def("get_bool", [] { return py::bool_(false); });
     // test_int
-    m.def("get_int", []{return py::int_(0);});
+    m.def("get_int", [] { return py::int_(0); });
     // test_iterator
-    m.def("get_iterator", []{return py::iterator();});
+    m.def("get_iterator", [] { return py::iterator(); });
     // test_iterable
-    m.def("get_iterable", []{return py::iterable();});
+    m.def("get_iterable", [] { return py::iterable(); });
+    m.def("get_frozenset_from_iterable",
+          [](const py::iterable &iter) { return py::frozenset(iter); });
+    m.def("get_list_from_iterable", [](const py::iterable &iter) { return py::list(iter); });
+    m.def("get_set_from_iterable", [](const py::iterable &iter) { return py::set(iter); });
+    m.def("get_tuple_from_iterable", [](const py::iterable &iter) { return py::tuple(iter); });
+    // test_float
+    m.def("get_float", [] { return py::float_(0.0f); });
     // test_list
+    m.def("list_no_args", []() { return py::list{}; });
+    m.def("list_ssize_t", []() { return py::list{(py::ssize_t) 0}; });
+    m.def("list_size_t", []() { return py::list{(py::size_t) 0}; });
+    m.def("list_insert_ssize_t", [](py::list *l) { return l->insert((py::ssize_t) 1, 83); });
+    m.def("list_insert_size_t", [](py::list *l) { return l->insert((py::size_t) 3, 57); });
     m.def("get_list", []() {
         py::list list;
         list.append("value");
@@ -27,18 +131,17 @@ TEST_SUBMODULE(pytypes, m) {
         list.insert(2, "inserted-2");
         return list;
     });
-    m.def("print_list", [](py::list list) {
+    m.def("print_list", [](const py::list &list) {
         int index = 0;
-        for (auto item : list)
+        for (auto item : list) {
             py::print("list item {}: {}"_s.format(index++, item));
+        }
     });
     // test_none
-    m.def("get_none", []{return py::none();});
-    m.def("print_none", [](py::none none) {
-        py::print("none: {}"_s.format(none));
-    });
+    m.def("get_none", [] { return py::none(); });
+    m.def("print_none", [](const py::none &none) { py::print("none: {}"_s.format(none)); });
 
-    // test_set
+    // test_set, test_frozenset
     m.def("get_set", []() {
         py::set set;
         set.add(py::str("key1"));
@@ -46,58 +149,101 @@ TEST_SUBMODULE(pytypes, m) {
         set.add(std::string("key3"));
         return set;
     });
-    m.def("print_set", [](py::set set) {
-        for (auto item : set)
-            py::print("key:", item);
-    });
-    m.def("set_contains", [](py::set set, py::object key) {
-        return set.contains(key);
+    m.def("get_frozenset", []() {
+        py::set set;
+        set.add(py::str("key1"));
+        set.add("key2");
+        set.add(std::string("key3"));
+        return py::frozenset(set);
     });
-    m.def("set_contains", [](py::set set, const char* key) {
-        return set.contains(key);
+    m.def("print_anyset", [](const py::anyset &set) {
+        for (auto item : set) {
+            py::print("key:", item);
+        }
     });
+    m.def("anyset_size", [](const py::anyset &set) { return set.size(); });
+    m.def("anyset_empty", [](const py::anyset &set) { return set.empty(); });
+    m.def("anyset_contains",
+          [](const py::anyset &set, const py::object &key) { return set.contains(key); });
+    m.def("anyset_contains",
+          [](const py::anyset &set, const char *key) { return set.contains(key); });
+    m.def("set_add", [](py::set &set, const py::object &key) { set.add(key); });
+    m.def("set_clear", [](py::set &set) { set.clear(); });
 
     // test_dict
-    m.def("get_dict", []() { return py::dict("key"_a="value"); });
-    m.def("print_dict", [](py::dict dict) {
-        for (auto item : dict)
+    m.def("get_dict", []() { return py::dict("key"_a = "value"); });
+    m.def("print_dict", [](const py::dict &dict) {
+        for (auto item : dict) {
             py::print("key: {}, value={}"_s.format(item.first, item.second));
+        }
     });
     m.def("dict_keyword_constructor", []() {
-        auto d1 = py::dict("x"_a=1, "y"_a=2);
-        auto d2 = py::dict("z"_a=3, **d1);
+        auto d1 = py::dict("x"_a = 1, "y"_a = 2);
+        auto d2 = py::dict("z"_a = 3, **d1);
         return d2;
     });
-    m.def("dict_contains", [](py::dict dict, py::object val) {
-        return dict.contains(val);
-    });
-    m.def("dict_contains", [](py::dict dict, const char* val) {
-        return dict.contains(val);
+    m.def("dict_contains",
+          [](const py::dict &dict, py::object val) { return dict.contains(val); });
+    m.def("dict_contains",
+          [](const py::dict &dict, const char *val) { return dict.contains(val); });
+
+    // test_tuple
+    m.def("tuple_no_args", []() { return py::tuple{}; });
+    m.def("tuple_ssize_t", []() { return py::tuple{(py::ssize_t) 0}; });
+    m.def("tuple_size_t", []() { return py::tuple{(py::size_t) 0}; });
+    m.def("get_tuple", []() { return py::make_tuple(42, py::none(), "spam"); });
+
+    // test_simple_namespace
+    m.def("get_simple_namespace", []() {
+        auto ns = py::module_::import("types").attr("SimpleNamespace")(
+            "attr"_a = 42, "x"_a = "foo", "wrong"_a = 1);
+        py::delattr(ns, "wrong");
+        py::setattr(ns, "right", py::int_(2));
+        return ns;
     });
 
     // test_str
+    m.def("str_from_char_ssize_t", []() { return py::str{"red", (py::ssize_t) 3}; });
+    m.def("str_from_char_size_t", []() { return py::str{"blue", (py::size_t) 4}; });
     m.def("str_from_string", []() { return py::str(std::string("baz")); });
     m.def("str_from_bytes", []() { return py::str(py::bytes("boo", 3)); });
-    m.def("str_from_object", [](const py::object& obj) { return py::str(obj); });
-    m.def("repr_from_object", [](const py::object& obj) { return py::repr(obj); });
+    m.def("str_from_object", [](const py::object &obj) { return py::str(obj); });
+    m.def("repr_from_object", [](const py::object &obj) { return py::repr(obj); });
     m.def("str_from_handle", [](py::handle h) { return py::str(h); });
+    m.def("str_from_string_from_str",
+          [](const py::str &obj) { return py::str(static_cast<std::string>(obj)); });
 
     m.def("str_format", []() {
         auto s1 = "{} + {} = {}"_s.format(1, 2, 3);
-        auto s2 = "{a} + {b} = {c}"_s.format("a"_a=1, "b"_a=2, "c"_a=3);
+        auto s2 = "{a} + {b} = {c}"_s.format("a"_a = 1, "b"_a = 2, "c"_a = 3);
         return py::make_tuple(s1, s2);
     });
 
     // test_bytes
+    m.def("bytes_from_char_ssize_t", []() { return py::bytes{"green", (py::ssize_t) 5}; });
+    m.def("bytes_from_char_size_t", []() { return py::bytes{"purple", (py::size_t) 6}; });
     m.def("bytes_from_string", []() { return py::bytes(std::string("foo")); });
     m.def("bytes_from_str", []() { return py::bytes(py::str("bar", 3)); });
 
+    // test bytearray
+    m.def("bytearray_from_char_ssize_t", []() { return py::bytearray{"$%", (py::ssize_t) 2}; });
+    m.def("bytearray_from_char_size_t", []() { return py::bytearray{"@$!", (py::size_t) 3}; });
+    m.def("bytearray_from_string", []() { return py::bytearray(std::string("foo")); });
+    m.def("bytearray_size", []() { return py::bytearray("foo").size(); });
+
     // test_capsule
     m.def("return_capsule_with_destructor", []() {
         py::print("creating capsule");
-        return py::capsule([]() {
-            py::print("destructing capsule");
-        });
+        return py::capsule([]() { py::print("destructing capsule"); });
+    });
+
+    m.def("return_renamed_capsule_with_destructor", []() {
+        py::print("creating capsule");
+        auto cap = py::capsule([]() { py::print("destructing capsule"); });
+        static const char *capsule_name = "test_name1";
+        py::print("renaming capsule");
+        cap.set_name(capsule_name);
+        return cap;
     });
 
     m.def("return_capsule_with_destructor_2", []() {
@@ -107,33 +253,44 @@ TEST_SUBMODULE(pytypes, m) {
         });
     });
 
+    m.def("return_renamed_capsule_with_destructor_2", []() {
+        py::print("creating capsule");
+        auto cap = py::capsule((void *) 1234, [](void *ptr) {
+            py::print("destructing capsule: {}"_s.format((size_t) ptr));
+        });
+        static const char *capsule_name = "test_name2";
+        py::print("renaming capsule");
+        cap.set_name(capsule_name);
+        return cap;
+    });
+
     m.def("return_capsule_with_name_and_destructor", []() {
         auto capsule = py::capsule((void *) 12345, "pointer type description", [](PyObject *ptr) {
             if (ptr) {
-                auto name = PyCapsule_GetName(ptr);
+                const auto *name = PyCapsule_GetName(ptr);
                 py::print("destructing capsule ({}, '{}')"_s.format(
-                    (size_t) PyCapsule_GetPointer(ptr, name), name
-                ));
+                    (size_t) PyCapsule_GetPointer(ptr, name), name));
             }
         });
 
         capsule.set_pointer((void *) 1234);
 
         // Using get_pointer<T>()
-        void* contents1 = static_cast<void*>(capsule);
-        void* contents2 = capsule.get_pointer();
-        void* contents3 = capsule.get_pointer<void>();
+        void *contents1 = static_cast<void *>(capsule);
+        void *contents2 = capsule.get_pointer();
+        void *contents3 = capsule.get_pointer<void>();
 
         auto result1 = reinterpret_cast<size_t>(contents1);
         auto result2 = reinterpret_cast<size_t>(contents2);
         auto result3 = reinterpret_cast<size_t>(contents3);
 
-        py::print("created capsule ({}, '{}')"_s.format(result1 & result2 & result3, capsule.name()));
+        py::print(
+            "created capsule ({}, '{}')"_s.format(result1 & result2 & result3, capsule.name()));
         return capsule;
     });
 
     // test_accessors
-    m.def("accessor_api", [](py::object o) {
+    m.def("accessor_api", [](const py::object &o) {
         auto d = py::dict();
 
         d["basic_attr"] = o.attr("basic_attr");
@@ -174,7 +331,7 @@ TEST_SUBMODULE(pytypes, m) {
         return d;
     });
 
-    m.def("tuple_accessor", [](py::tuple existing_t) {
+    m.def("tuple_accessor", [](const py::tuple &existing_t) {
         try {
             existing_t[0] = 1;
         } catch (const py::error_already_set &) {
@@ -206,66 +363,118 @@ TEST_SUBMODULE(pytypes, m) {
         return d;
     });
 
+    m.def("accessor_moves", []() { // See PR #3970
+        py::list return_list;
+#ifdef PYBIND11_HANDLE_REF_DEBUG
+        py::int_ py_int_0(0);
+        py::int_ py_int_42(42);
+        py::str py_str_count("count");
+
+        auto tup = py::make_tuple(0);
+
+        py::sequence seq(tup);
+
+        py::list lst;
+        lst.append(0);
+
+#    define PYBIND11_LOCAL_DEF(...)                                                               \
+        {                                                                                         \
+            std::size_t inc_refs = py::handle::inc_ref_counter();                                 \
+            __VA_ARGS__;                                                                          \
+            inc_refs = py::handle::inc_ref_counter() - inc_refs;                                  \
+            return_list.append(inc_refs);                                                         \
+        }
+
+        PYBIND11_LOCAL_DEF(tup[py_int_0])    // l-value (to have a control)
+        PYBIND11_LOCAL_DEF(tup[py::int_(0)]) // r-value
+
+        PYBIND11_LOCAL_DEF(tup.attr(py_str_count))     // l-value
+        PYBIND11_LOCAL_DEF(tup.attr(py::str("count"))) // r-value
+
+        PYBIND11_LOCAL_DEF(seq[py_int_0])    // l-value
+        PYBIND11_LOCAL_DEF(seq[py::int_(0)]) // r-value
+
+        PYBIND11_LOCAL_DEF(seq.attr(py_str_count))     // l-value
+        PYBIND11_LOCAL_DEF(seq.attr(py::str("count"))) // r-value
+
+        PYBIND11_LOCAL_DEF(lst[py_int_0])    // l-value
+        PYBIND11_LOCAL_DEF(lst[py::int_(0)]) // r-value
+
+        PYBIND11_LOCAL_DEF(lst.attr(py_str_count))     // l-value
+        PYBIND11_LOCAL_DEF(lst.attr(py::str("count"))) // r-value
+
+        auto lst_acc = lst[py::int_(0)];
+        lst_acc = py::int_(42);                    // Detaches lst_acc from lst.
+        PYBIND11_LOCAL_DEF(lst_acc = py_int_42)    // l-value
+        PYBIND11_LOCAL_DEF(lst_acc = py::int_(42)) // r-value
+#    undef PYBIND11_LOCAL_DEF
+#endif
+        return return_list;
+    });
+
     // test_constructors
     m.def("default_constructors", []() {
-        return py::dict(
-            "bytes"_a=py::bytes(),
-            "str"_a=py::str(),
-            "bool"_a=py::bool_(),
-            "int"_a=py::int_(),
-            "float"_a=py::float_(),
-            "tuple"_a=py::tuple(),
-            "list"_a=py::list(),
-            "dict"_a=py::dict(),
-            "set"_a=py::set()
-        );
-    });
-
-    m.def("converting_constructors", [](py::dict d) {
-        return py::dict(
-            "bytes"_a=py::bytes(d["bytes"]),
-            "str"_a=py::str(d["str"]),
-            "bool"_a=py::bool_(d["bool"]),
-            "int"_a=py::int_(d["int"]),
-            "float"_a=py::float_(d["float"]),
-            "tuple"_a=py::tuple(d["tuple"]),
-            "list"_a=py::list(d["list"]),
-            "dict"_a=py::dict(d["dict"]),
-            "set"_a=py::set(d["set"]),
-            "memoryview"_a=py::memoryview(d["memoryview"])
-        );
-    });
-
-    m.def("cast_functions", [](py::dict d) {
+        return py::dict("bytes"_a = py::bytes(),
+                        "bytearray"_a = py::bytearray(),
+                        "str"_a = py::str(),
+                        "bool"_a = py::bool_(),
+                        "int"_a = py::int_(),
+                        "float"_a = py::float_(),
+                        "tuple"_a = py::tuple(),
+                        "list"_a = py::list(),
+                        "dict"_a = py::dict(),
+                        "set"_a = py::set());
+    });
+
+    m.def("converting_constructors", [](const py::dict &d) {
+        return py::dict("bytes"_a = py::bytes(d["bytes"]),
+                        "bytearray"_a = py::bytearray(d["bytearray"]),
+                        "str"_a = py::str(d["str"]),
+                        "bool"_a = py::bool_(d["bool"]),
+                        "int"_a = py::int_(d["int"]),
+                        "float"_a = py::float_(d["float"]),
+                        "tuple"_a = py::tuple(d["tuple"]),
+                        "list"_a = py::list(d["list"]),
+                        "dict"_a = py::dict(d["dict"]),
+                        "set"_a = py::set(d["set"]),
+                        "frozenset"_a = py::frozenset(d["frozenset"]),
+                        "memoryview"_a = py::memoryview(d["memoryview"]));
+    });
+
+    m.def("cast_functions", [](const py::dict &d) {
         // When converting between Python types, obj.cast<T>() should be the same as T(obj)
-        return py::dict(
-            "bytes"_a=d["bytes"].cast<py::bytes>(),
-            "str"_a=d["str"].cast<py::str>(),
-            "bool"_a=d["bool"].cast<py::bool_>(),
-            "int"_a=d["int"].cast<py::int_>(),
-            "float"_a=d["float"].cast<py::float_>(),
-            "tuple"_a=d["tuple"].cast<py::tuple>(),
-            "list"_a=d["list"].cast<py::list>(),
-            "dict"_a=d["dict"].cast<py::dict>(),
-            "set"_a=d["set"].cast<py::set>(),
-            "memoryview"_a=d["memoryview"].cast<py::memoryview>()
-        );
-    });
-
-    m.def("convert_to_pybind11_str", [](py::object o) { return py::str(o); });
-
-    m.def("nonconverting_constructor", [](std::string type, py::object value) -> py::object {
-        if (type == "bytes") {
-            return py::bytes(value);
-        }
-        else if (type == "none") {
-            return py::none(value);
-        }
-        else if (type == "ellipsis") {
-            return py::ellipsis(value);
-        }
-        throw std::runtime_error("Invalid type");
-    });
+        return py::dict("bytes"_a = d["bytes"].cast<py::bytes>(),
+                        "bytearray"_a = d["bytearray"].cast<py::bytearray>(),
+                        "str"_a = d["str"].cast<py::str>(),
+                        "bool"_a = d["bool"].cast<py::bool_>(),
+                        "int"_a = d["int"].cast<py::int_>(),
+                        "float"_a = d["float"].cast<py::float_>(),
+                        "tuple"_a = d["tuple"].cast<py::tuple>(),
+                        "list"_a = d["list"].cast<py::list>(),
+                        "dict"_a = d["dict"].cast<py::dict>(),
+                        "set"_a = d["set"].cast<py::set>(),
+                        "frozenset"_a = d["frozenset"].cast<py::frozenset>(),
+                        "memoryview"_a = d["memoryview"].cast<py::memoryview>());
+    });
+
+    m.def("convert_to_pybind11_str", [](const py::object &o) { return py::str(o); });
+
+    m.def("nonconverting_constructor",
+          [](const std::string &type, py::object value, bool move) -> py::object {
+              if (type == "bytes") {
+                  return move ? py::bytes(std::move(value)) : py::bytes(value);
+              }
+              if (type == "none") {
+                  return move ? py::none(std::move(value)) : py::none(value);
+              }
+              if (type == "ellipsis") {
+                  return move ? py::ellipsis(std::move(value)) : py::ellipsis(value);
+              }
+              if (type == "type") {
+                  return move ? py::type(std::move(value)) : py::type(value);
+              }
+              throw std::runtime_error("Invalid type");
+          });
 
     m.def("get_implicit_casting", []() {
         py::dict d;
@@ -298,10 +507,7 @@ TEST_SUBMODULE(pytypes, m) {
         l.append(py::cast(12));
         l.append(py::int_(15));
 
-        return py::dict(
-            "d"_a=d,
-            "l"_a=l
-        );
+        return py::dict("d"_a = d, "l"_a = l);
     });
 
     // test_print
@@ -309,23 +515,24 @@ TEST_SUBMODULE(pytypes, m) {
         py::print("Hello, World!");
         py::print(1, 2.0, "three", true, std::string("-- multiple args"));
         auto args = py::make_tuple("and", "a", "custom", "separator");
-        py::print("*args", *args, "sep"_a="-");
-        py::print("no new line here", "end"_a=" -- ");
+        py::print("*args", *args, "sep"_a = "-");
+        py::print("no new line here", "end"_a = " -- ");
         py::print("next print");
 
         auto py_stderr = py::module_::import("sys").attr("stderr");
-        py::print("this goes to stderr", "file"_a=py_stderr);
+        py::print("this goes to stderr", "file"_a = py_stderr);
 
-        py::print("flush", "flush"_a=true);
+        py::print("flush", "flush"_a = true);
 
-        py::print("{a} + {b} = {c}"_s.format("a"_a="py::print", "b"_a="str.format", "c"_a="this"));
+        py::print(
+            "{a} + {b} = {c}"_s.format("a"_a = "py::print", "b"_a = "str.format", "c"_a = "this"));
     });
 
     m.def("print_failure", []() { py::print(42, UnregisteredType()); });
 
-    m.def("hash_function", [](py::object obj) { return py::hash(obj); });
+    m.def("hash_function", [](py::object obj) { return py::hash(std::move(obj)); });
 
-    m.def("test_number_protocol", [](py::object a, py::object b) {
+    m.def("test_number_protocol", [](const py::object &a, const py::object &b) {
         py::list l;
         l.append(a.equal(b));
         l.append(a.not_equal(b));
@@ -345,9 +552,7 @@ TEST_SUBMODULE(pytypes, m) {
         return l;
     });
 
-    m.def("test_list_slicing", [](py::list a) {
-        return a[py::slice(0, -1, 2)];
-    });
+    m.def("test_list_slicing", [](const py::list &a) { return a[py::slice(0, -1, 2)]; });
 
     // See #2361
     m.def("issue2361_str_implicit_copy_none", []() {
@@ -359,55 +564,235 @@ TEST_SUBMODULE(pytypes, m) {
         return is_this_none;
     });
 
-    m.def("test_memoryview_object", [](py::buffer b) {
-        return py::memoryview(b);
-    });
+    m.def("test_memoryview_object", [](const py::buffer &b) { return py::memoryview(b); });
 
-    m.def("test_memoryview_buffer_info", [](py::buffer b) {
-        return py::memoryview(b.request());
-    });
+    m.def("test_memoryview_buffer_info",
+          [](const py::buffer &b) { return py::memoryview(b.request()); });
 
     m.def("test_memoryview_from_buffer", [](bool is_unsigned) {
-        static const int16_t si16[] = { 3, 1, 4, 1, 5 };
-        static const uint16_t ui16[] = { 2, 7, 1, 8 };
-        if (is_unsigned)
-            return py::memoryview::from_buffer(
-                ui16, { 4 }, { sizeof(uint16_t) });
-        else
-            return py::memoryview::from_buffer(
-                si16, { 5 }, { sizeof(int16_t) });
+        static const int16_t si16[] = {3, 1, 4, 1, 5};
+        static const uint16_t ui16[] = {2, 7, 1, 8};
+        if (is_unsigned) {
+            return py::memoryview::from_buffer(ui16, {4}, {sizeof(uint16_t)});
+        }
+        return py::memoryview::from_buffer(si16, {5}, {sizeof(int16_t)});
     });
 
     m.def("test_memoryview_from_buffer_nativeformat", []() {
-        static const char* format = "@i";
-        static const int32_t arr[] = { 4, 7, 5 };
-        return py::memoryview::from_buffer(
-            arr, sizeof(int32_t), format, { 3 }, { sizeof(int32_t) });
+        static const char *format = "@i";
+        static const int32_t arr[] = {4, 7, 5};
+        return py::memoryview::from_buffer(arr, sizeof(int32_t), format, {3}, {sizeof(int32_t)});
     });
 
     m.def("test_memoryview_from_buffer_empty_shape", []() {
-        static const char* buf = "";
-        return py::memoryview::from_buffer(buf, 1, "B", { }, { });
+        static const char *buf = "";
+        return py::memoryview::from_buffer(buf, 1, "B", {}, {});
     });
 
     m.def("test_memoryview_from_buffer_invalid_strides", []() {
-        static const char* buf = "\x02\x03\x04";
-        return py::memoryview::from_buffer(buf, 1, "B", { 3 }, { });
+        static const char *buf = "\x02\x03\x04";
+        return py::memoryview::from_buffer(buf, 1, "B", {3}, {});
     });
 
     m.def("test_memoryview_from_buffer_nullptr", []() {
-        return py::memoryview::from_buffer(
-            static_cast<void*>(nullptr), 1, "B", { }, { });
+        return py::memoryview::from_buffer(static_cast<void *>(nullptr), 1, "B", {}, {});
     });
 
-#if PY_MAJOR_VERSION >= 3
     m.def("test_memoryview_from_memory", []() {
-        const char* buf = "\xff\xe1\xab\x37";
-        return py::memoryview::from_memory(
-            buf, static_cast<py::ssize_t>(strlen(buf)));
+        const char *buf = "\xff\xe1\xab\x37";
+        return py::memoryview::from_memory(buf, static_cast<py::ssize_t>(strlen(buf)));
     });
-#endif
 
     // test_builtin_functions
     m.def("get_len", [](py::handle h) { return py::len(h); });
+
+#ifdef PYBIND11_STR_LEGACY_PERMISSIVE
+    m.attr("PYBIND11_STR_LEGACY_PERMISSIVE") = true;
+#endif
+
+    m.def("isinstance_pybind11_bytes",
+          [](py::object o) { return py::isinstance<py::bytes>(std::move(o)); });
+    m.def("isinstance_pybind11_str",
+          [](py::object o) { return py::isinstance<py::str>(std::move(o)); });
+
+    m.def("pass_to_pybind11_bytes", [](py::bytes b) { return py::len(std::move(b)); });
+    m.def("pass_to_pybind11_str", [](py::str s) { return py::len(std::move(s)); });
+    m.def("pass_to_std_string", [](const std::string &s) { return s.size(); });
+
+    // test_weakref
+    m.def("weakref_from_handle", [](py::handle h) { return py::weakref(h); });
+    m.def("weakref_from_handle_and_function",
+          [](py::handle h, py::function f) { return py::weakref(h, std::move(f)); });
+    m.def("weakref_from_object", [](const py::object &o) { return py::weakref(o); });
+    m.def("weakref_from_object_and_function",
+          [](py::object o, py::function f) { return py::weakref(std::move(o), std::move(f)); });
+
+// See PR #3263 for background (https://github.com/pybind/pybind11/pull/3263):
+// pytypes.h could be changed to enforce the "most correct" user code below, by removing
+// `const` from iterator `reference` using type aliases, but that will break existing
+// user code.
+#if (defined(__APPLE__) && defined(__clang__)) || defined(PYPY_VERSION)
+// This is "most correct" and enforced on these platforms.
+#    define PYBIND11_AUTO_IT auto it
+#else
+// This works on many platforms and is (unfortunately) reflective of existing user code.
+// NOLINTNEXTLINE(bugprone-macro-parentheses)
+#    define PYBIND11_AUTO_IT auto &it
+#endif
+
+    m.def("tuple_iterator", []() {
+        auto tup = py::make_tuple(5, 7);
+        int tup_sum = 0;
+        for (PYBIND11_AUTO_IT : tup) {
+            tup_sum += it.cast<int>();
+        }
+        return tup_sum;
+    });
+
+    m.def("dict_iterator", []() {
+        py::dict dct;
+        dct[py::int_(3)] = 5;
+        dct[py::int_(7)] = 11;
+        int kv_sum = 0;
+        for (PYBIND11_AUTO_IT : dct) {
+            kv_sum += it.first.cast<int>() * 100 + it.second.cast<int>();
+        }
+        return kv_sum;
+    });
+
+    m.def("passed_iterator", [](const py::iterator &py_it) {
+        int elem_sum = 0;
+        for (PYBIND11_AUTO_IT : py_it) {
+            elem_sum += it.cast<int>();
+        }
+        return elem_sum;
+    });
+
+#undef PYBIND11_AUTO_IT
+
+    // Tests below this line are for pybind11 IMPLEMENTATION DETAILS:
+
+    m.def("sequence_item_get_ssize_t", [](const py::object &o) {
+        return py::detail::accessor_policies::sequence_item::get(o, (py::ssize_t) 1);
+    });
+    m.def("sequence_item_set_ssize_t", [](const py::object &o) {
+        auto s = py::str{"peppa", 5};
+        py::detail::accessor_policies::sequence_item::set(o, (py::ssize_t) 1, s);
+    });
+    m.def("sequence_item_get_size_t", [](const py::object &o) {
+        return py::detail::accessor_policies::sequence_item::get(o, (py::size_t) 2);
+    });
+    m.def("sequence_item_set_size_t", [](const py::object &o) {
+        auto s = py::str{"george", 6};
+        py::detail::accessor_policies::sequence_item::set(o, (py::size_t) 2, s);
+    });
+    m.def("list_item_get_ssize_t", [](const py::object &o) {
+        return py::detail::accessor_policies::list_item::get(o, (py::ssize_t) 3);
+    });
+    m.def("list_item_set_ssize_t", [](const py::object &o) {
+        auto s = py::str{"rebecca", 7};
+        py::detail::accessor_policies::list_item::set(o, (py::ssize_t) 3, s);
+    });
+    m.def("list_item_get_size_t", [](const py::object &o) {
+        return py::detail::accessor_policies::list_item::get(o, (py::size_t) 4);
+    });
+    m.def("list_item_set_size_t", [](const py::object &o) {
+        auto s = py::str{"richard", 7};
+        py::detail::accessor_policies::list_item::set(o, (py::size_t) 4, s);
+    });
+    m.def("tuple_item_get_ssize_t", [](const py::object &o) {
+        return py::detail::accessor_policies::tuple_item::get(o, (py::ssize_t) 5);
+    });
+    m.def("tuple_item_set_ssize_t", []() {
+        auto s0 = py::str{"emely", 5};
+        auto s1 = py::str{"edmond", 6};
+        auto o = py::tuple{2};
+        py::detail::accessor_policies::tuple_item::set(o, (py::ssize_t) 0, s0);
+        py::detail::accessor_policies::tuple_item::set(o, (py::ssize_t) 1, s1);
+        return o;
+    });
+    m.def("tuple_item_get_size_t", [](const py::object &o) {
+        return py::detail::accessor_policies::tuple_item::get(o, (py::size_t) 6);
+    });
+    m.def("tuple_item_set_size_t", []() {
+        auto s0 = py::str{"candy", 5};
+        auto s1 = py::str{"cat", 3};
+        auto o = py::tuple{2};
+        py::detail::accessor_policies::tuple_item::set(o, (py::size_t) 1, s1);
+        py::detail::accessor_policies::tuple_item::set(o, (py::size_t) 0, s0);
+        return o;
+    });
+
+    m.def("square_float_", [](const external::float_ &x) -> double {
+        double v = x.get_value();
+        return v * v;
+    });
+
+    m.def("tuple_rvalue_getter", [](const py::tuple &tup) {
+        // tests accessing tuple object with rvalue int
+        for (size_t i = 0; i < tup.size(); i++) {
+            auto o = py::handle(tup[py::int_(i)]);
+            if (!o) {
+                throw py::value_error("tuple is malformed");
+            }
+        }
+        return tup;
+    });
+    m.def("list_rvalue_getter", [](const py::list &l) {
+        // tests accessing list with rvalue int
+        for (size_t i = 0; i < l.size(); i++) {
+            auto o = py::handle(l[py::int_(i)]);
+            if (!o) {
+                throw py::value_error("list is malformed");
+            }
+        }
+        return l;
+    });
+    m.def("populate_dict_rvalue", [](int population) {
+        auto d = py::dict();
+        for (int i = 0; i < population; i++) {
+            d[py::int_(i)] = py::int_(i);
+        }
+        return d;
+    });
+    m.def("populate_obj_str_attrs", [](py::object &o, int population) {
+        for (int i = 0; i < population; i++) {
+            o.attr(py::str(py::int_(i))) = py::str(py::int_(i));
+        }
+        return o;
+    });
+
+    // testing immutable object augmented assignment: #issue 3812
+    m.def("inplace_append", [](py::object &a, const py::object &b) {
+        a += b;
+        return a;
+    });
+    m.def("inplace_subtract", [](py::object &a, const py::object &b) {
+        a -= b;
+        return a;
+    });
+    m.def("inplace_multiply", [](py::object &a, const py::object &b) {
+        a *= b;
+        return a;
+    });
+    m.def("inplace_divide", [](py::object &a, const py::object &b) {
+        a /= b;
+        return a;
+    });
+    m.def("inplace_or", [](py::object &a, const py::object &b) {
+        a |= b;
+        return a;
+    });
+    m.def("inplace_and", [](py::object &a, const py::object &b) {
+        a &= b;
+        return a;
+    });
+    m.def("inplace_lshift", [](py::object &a, const py::object &b) {
+        a <<= b;
+        return a;
+    });
+    m.def("inplace_rshift", [](py::object &a, const py::object &b) {
+        a >>= b;
+        return a;
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_pytypes.py b/3rdparty/pybind11/tests/test_pytypes.py
index 9e5c302e56..a34eaa59e8 100644
--- a/3rdparty/pybind11/tests/test_pytypes.py
+++ b/3rdparty/pybind11/tests/test_pytypes.py
@@ -1,12 +1,21 @@
-# -*- coding: utf-8 -*-
-from __future__ import division
-import pytest
+import contextlib
 import sys
+import types
 
-import env  # noqa: F401
+import pytest
 
+import env
+from pybind11_tests import detailed_error_messages_enabled
 from pybind11_tests import pytypes as m
-from pybind11_tests import debug_enabled
+
+
+def test_handle_from_move_only_type_with_operator_PyObject():  # noqa: N802
+    assert m.handle_from_move_only_type_with_operator_PyObject_ncnst()
+    assert m.handle_from_move_only_type_with_operator_PyObject_const()
+
+
+def test_bool(doc):
+    assert doc(m.get_bool) == "get_bool() -> bool"
 
 
 def test_int(doc):
@@ -17,11 +26,40 @@ def test_iterator(doc):
     assert doc(m.get_iterator) == "get_iterator() -> Iterator"
 
 
+@pytest.mark.parametrize(
+    "pytype, from_iter_func",
+    [
+        (frozenset, m.get_frozenset_from_iterable),
+        (list, m.get_list_from_iterable),
+        (set, m.get_set_from_iterable),
+        (tuple, m.get_tuple_from_iterable),
+    ],
+)
+def test_from_iterable(pytype, from_iter_func):
+    my_iter = iter(range(10))
+    s = from_iter_func(my_iter)
+    assert type(s) == pytype
+    assert s == pytype(range(10))
+
+
 def test_iterable(doc):
     assert doc(m.get_iterable) == "get_iterable() -> Iterable"
 
 
+def test_float(doc):
+    assert doc(m.get_float) == "get_float() -> float"
+
+
 def test_list(capture, doc):
+    assert m.list_no_args() == []
+    assert m.list_ssize_t() == []
+    assert m.list_size_t() == []
+    lins = [1, 2]
+    m.list_insert_ssize_t(lins)
+    assert lins == [1, 83, 2]
+    m.list_insert_size_t(lins)
+    assert lins == [1, 83, 2, 57]
+
     with capture:
         lst = m.get_list()
         assert lst == ["inserted-0", "overwritten", "inserted-2"]
@@ -50,11 +88,12 @@ def test_none(capture, doc):
 
 def test_set(capture, doc):
     s = m.get_set()
+    assert isinstance(s, set)
     assert s == {"key1", "key2", "key3"}
 
+    s.add("key4")
     with capture:
-        s.add("key4")
-        m.print_set(s)
+        m.print_anyset(s)
     assert (
         capture.unordered
         == """
@@ -65,12 +104,43 @@ def test_set(capture, doc):
     """
     )
 
-    assert not m.set_contains(set([]), 42)
-    assert m.set_contains({42}, 42)
-    assert m.set_contains({"foo"}, "foo")
+    m.set_add(s, "key5")
+    assert m.anyset_size(s) == 5
 
-    assert doc(m.get_list) == "get_list() -> list"
-    assert doc(m.print_list) == "print_list(arg0: list) -> None"
+    m.set_clear(s)
+    assert m.anyset_empty(s)
+
+    assert not m.anyset_contains(set(), 42)
+    assert m.anyset_contains({42}, 42)
+    assert m.anyset_contains({"foo"}, "foo")
+
+    assert doc(m.get_set) == "get_set() -> set"
+    assert doc(m.print_anyset) == "print_anyset(arg0: anyset) -> None"
+
+
+def test_frozenset(capture, doc):
+    s = m.get_frozenset()
+    assert isinstance(s, frozenset)
+    assert s == frozenset({"key1", "key2", "key3"})
+
+    with capture:
+        m.print_anyset(s)
+    assert (
+        capture.unordered
+        == """
+        key: key1
+        key: key2
+        key: key3
+    """
+    )
+    assert m.anyset_size(s) == 3
+    assert not m.anyset_empty(s)
+
+    assert not m.anyset_contains(frozenset(), 42)
+    assert m.anyset_contains(frozenset({42}), 42)
+    assert m.anyset_contains(frozenset({"foo"}), "foo")
+
+    assert doc(m.get_frozenset) == "get_frozenset() -> frozenset"
 
 
 def test_dict(capture, doc):
@@ -98,13 +168,30 @@ def test_dict(capture, doc):
     assert m.dict_keyword_constructor() == {"x": 1, "y": 2, "z": 3}
 
 
+def test_tuple():
+    assert m.tuple_no_args() == ()
+    assert m.tuple_ssize_t() == ()
+    assert m.tuple_size_t() == ()
+    assert m.get_tuple() == (42, None, "spam")
+
+
+def test_simple_namespace():
+    ns = m.get_simple_namespace()
+    assert ns.attr == 42
+    assert ns.x == "foo"
+    assert ns.right == 2
+    assert not hasattr(ns, "wrong")
+
+
 def test_str(doc):
+    assert m.str_from_char_ssize_t().encode().decode() == "red"
+    assert m.str_from_char_size_t().encode().decode() == "blue"
     assert m.str_from_string().encode().decode() == "baz"
     assert m.str_from_bytes().encode().decode() == "boo"
 
     assert doc(m.str_from_bytes) == "str_from_bytes() -> str"
 
-    class A(object):
+    class A:
         def __str__(self):
             return "this is a str"
 
@@ -120,24 +207,32 @@ def __repr__(self):
     assert s1 == s2
 
     malformed_utf8 = b"\x80"
-    assert m.str_from_object(malformed_utf8) is malformed_utf8  # To be fixed; see #2380
-    if env.PY2:
-        # with pytest.raises(UnicodeDecodeError):
-        #     m.str_from_object(malformed_utf8)
-        with pytest.raises(UnicodeDecodeError):
-            m.str_from_handle(malformed_utf8)
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert m.str_from_object(malformed_utf8) is malformed_utf8
     else:
-        # assert m.str_from_object(malformed_utf8) == "b'\\x80'"
-        assert m.str_from_handle(malformed_utf8) == "b'\\x80'"
+        assert m.str_from_object(malformed_utf8) == "b'\\x80'"
+    assert m.str_from_handle(malformed_utf8) == "b'\\x80'"
+
+    assert m.str_from_string_from_str("this is a str") == "this is a str"
+    ucs_surrogates_str = "\udcc3"
+    with pytest.raises(UnicodeEncodeError):
+        m.str_from_string_from_str(ucs_surrogates_str)
 
 
 def test_bytes(doc):
+    assert m.bytes_from_char_ssize_t().decode() == "green"
+    assert m.bytes_from_char_size_t().decode() == "purple"
     assert m.bytes_from_string().decode() == "foo"
     assert m.bytes_from_str().decode() == "bar"
 
-    assert doc(m.bytes_from_str) == "bytes_from_str() -> {}".format(
-        "str" if env.PY2 else "bytes"
-    )
+    assert doc(m.bytes_from_str) == "bytes_from_str() -> bytes"
+
+
+def test_bytearray(doc):
+    assert m.bytearray_from_char_ssize_t().decode() == "$%"
+    assert m.bytearray_from_char_size_t().decode() == "@$!"
+    assert m.bytearray_from_string().decode() == "foo"
+    assert m.bytearray_size() == len("foo")
 
 
 def test_capsule(capture):
@@ -154,6 +249,19 @@ def test_capsule(capture):
     """
     )
 
+    with capture:
+        a = m.return_renamed_capsule_with_destructor()
+        del a
+        pytest.gc_collect()
+    assert (
+        capture.unordered
+        == """
+        creating capsule
+        renaming capsule
+        destructing capsule
+    """
+    )
+
     with capture:
         a = m.return_capsule_with_destructor_2()
         del a
@@ -166,6 +274,19 @@ def test_capsule(capture):
     """
     )
 
+    with capture:
+        a = m.return_renamed_capsule_with_destructor_2()
+        del a
+        pytest.gc_collect()
+    assert (
+        capture.unordered
+        == """
+        creating capsule
+        renaming capsule
+        destructing capsule: 1234
+    """
+    )
+
     with capture:
         a = m.return_capsule_with_name_and_destructor()
         del a
@@ -218,19 +339,23 @@ def func(self, x, *args):
     assert d["var"] == 99
 
 
+def test_accessor_moves():
+    inc_refs = m.accessor_moves()
+    if inc_refs:
+        assert inc_refs == [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+    else:
+        pytest.skip("Not defined: PYBIND11_HANDLE_REF_DEBUG")
+
+
 def test_constructors():
     """C++ default and converting constructors are equivalent to type calls in Python"""
-    types = [bytes, str, bool, int, float, tuple, list, dict, set]
+    types = [bytes, bytearray, str, bool, int, float, tuple, list, dict, set]
     expected = {t.__name__: t() for t in types}
-    if env.PY2:
-        # Note that bytes.__name__ == 'str' in Python 2.
-        # pybind11::str is unicode even under Python 2.
-        expected["bytes"] = bytes()
-        expected["str"] = unicode()  # noqa: F821
     assert m.default_constructors() == expected
 
     data = {
         bytes: b"41",  # Currently no supported or working conversions.
+        bytearray: bytearray(b"41"),
         str: 42,
         bool: "Not empty",
         int: "42",
@@ -239,15 +364,11 @@ def test_constructors():
         list: range(3),
         dict: [("two", 2), ("one", 1), ("three", 3)],
         set: [4, 4, 5, 6, 6, 6],
+        frozenset: [4, 4, 5, 6, 6, 6],
         memoryview: b"abc",
     }
     inputs = {k.__name__: v for k, v in data.items()}
     expected = {k.__name__: k(v) for k, v in data.items()}
-    if env.PY2:  # Similar to the above. See comments above.
-        inputs["bytes"] = b"41"
-        inputs["str"] = 42
-        expected["bytes"] = b"41"
-        expected["str"] = u"42"
 
     assert m.converting_constructors(inputs) == expected
     assert m.cast_functions(inputs) == expected
@@ -268,46 +389,54 @@ def test_non_converting_constructors():
         ("bytes", range(10)),
         ("none", 42),
         ("ellipsis", 42),
+        ("type", 42),
     ]
     for t, v in non_converting_test_cases:
-        with pytest.raises(TypeError) as excinfo:
-            m.nonconverting_constructor(t, v)
-        expected_error = "Object of type '{}' is not an instance of '{}'".format(
-            type(v).__name__, t
-        )
-        assert str(excinfo.value) == expected_error
+        for move in [True, False]:
+            with pytest.raises(TypeError) as excinfo:
+                m.nonconverting_constructor(t, v, move)
+            expected_error = (
+                f"Object of type '{type(v).__name__}' is not an instance of '{t}'"
+            )
+            assert str(excinfo.value) == expected_error
 
 
 def test_pybind11_str_raw_str():
     # specifically to exercise pybind11::str::raw_str
     cvt = m.convert_to_pybind11_str
-    assert cvt(u"Str") == u"Str"
-    assert cvt(b"Bytes") == u"Bytes" if env.PY2 else "b'Bytes'"
-    assert cvt(None) == u"None"
-    assert cvt(False) == u"False"
-    assert cvt(True) == u"True"
-    assert cvt(42) == u"42"
-    assert cvt(2 ** 65) == u"36893488147419103232"
-    assert cvt(-1.50) == u"-1.5"
-    assert cvt(()) == u"()"
-    assert cvt((18,)) == u"(18,)"
-    assert cvt([]) == u"[]"
-    assert cvt([28]) == u"[28]"
-    assert cvt({}) == u"{}"
-    assert cvt({3: 4}) == u"{3: 4}"
-    assert cvt(set()) == u"set([])" if env.PY2 else "set()"
-    assert cvt({3, 3}) == u"set([3])" if env.PY2 else "{3}"
-
-    valid_orig = u"DZ"
+    assert cvt("Str") == "Str"
+    assert cvt(b"Bytes") == "b'Bytes'"
+    assert cvt(None) == "None"
+    assert cvt(False) == "False"
+    assert cvt(True) == "True"
+    assert cvt(42) == "42"
+    assert cvt(2**65) == "36893488147419103232"
+    assert cvt(-1.50) == "-1.5"
+    assert cvt(()) == "()"
+    assert cvt((18,)) == "(18,)"
+    assert cvt([]) == "[]"
+    assert cvt([28]) == "[28]"
+    assert cvt({}) == "{}"
+    assert cvt({3: 4}) == "{3: 4}"
+    assert cvt(set()) == "set()"
+    assert cvt({3, 3}) == "{3}"
+
+    valid_orig = "DZ"
     valid_utf8 = valid_orig.encode("utf-8")
     valid_cvt = cvt(valid_utf8)
-    assert type(valid_cvt) == bytes  # Probably surprising.
-    assert valid_cvt == b"\xc7\xb1"
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert valid_cvt is valid_utf8
+    else:
+        assert type(valid_cvt) is str
+        assert valid_cvt == "b'\\xc7\\xb1'"
 
     malformed_utf8 = b"\x80"
-    malformed_cvt = cvt(malformed_utf8)
-    assert type(malformed_cvt) == bytes  # Probably surprising.
-    assert malformed_cvt == b"\x80"
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert cvt(malformed_utf8) is malformed_utf8
+    else:
+        malformed_cvt = cvt(malformed_utf8)
+        assert type(malformed_cvt) is str
+        assert malformed_cvt == "b'\\x80'"
 
 
 def test_implicit_casting():
@@ -348,22 +477,22 @@ def test_print(capture):
 
     with pytest.raises(RuntimeError) as excinfo:
         m.print_failure()
-    assert str(excinfo.value) == "make_tuple(): unable to convert " + (
-        "argument of type 'UnregisteredType' to Python object"
-        if debug_enabled
-        else "arguments to Python object (compile in debug mode for details)"
+    assert str(excinfo.value) == "Unable to convert call argument " + (
+        "'1' of type 'UnregisteredType' to Python object"
+        if detailed_error_messages_enabled
+        else "to Python object (#define PYBIND11_DETAILED_ERROR_MESSAGES or compile in debug mode for details)"
     )
 
 
 def test_hash():
-    class Hashable(object):
+    class Hashable:
         def __init__(self, value):
             self.value = value
 
         def __hash__(self):
             return self.value
 
-    class Unhashable(object):
+    class Unhashable:
         __hash__ = None
 
     assert m.hash_function(Hashable(42)) == 42
@@ -403,7 +532,8 @@ def test_issue2361():
     assert m.issue2361_str_implicit_copy_none() == "None"
     with pytest.raises(TypeError) as excinfo:
         assert m.issue2361_dict_implicit_copy_none()
-    assert "'NoneType' object is not iterable" in str(excinfo.value)
+    assert "NoneType" in str(excinfo.value)
+    assert "iterable" in str(excinfo.value)
 
 
 @pytest.mark.parametrize(
@@ -420,12 +550,7 @@ def test_memoryview(method, args, fmt, expected_view):
     view = method(*args)
     assert isinstance(view, memoryview)
     assert view.format == fmt
-    if isinstance(expected_view, bytes) or not env.PY2:
-        view_as_list = list(view)
-    else:
-        # Using max to pick non-zero byte (big-endian vs little-endian).
-        view_as_list = [max([ord(c) for c in s]) for s in view]
-    assert view_as_list == list(expected_view)
+    assert list(view) == list(expected_view)
 
 
 @pytest.mark.xfail("env.PYPY", reason="getrefcount is not available")
@@ -449,12 +574,7 @@ def test_memoryview_from_buffer_empty_shape():
     view = m.test_memoryview_from_buffer_empty_shape()
     assert isinstance(view, memoryview)
     assert view.format == "B"
-    if env.PY2:
-        # Python 2 behavior is weird, but Python 3 (the future) is fine.
-        # PyPy3 has <memoryview, while CPython 2 has <memory
-        assert bytes(view).startswith(b"<memory")
-    else:
-        assert bytes(view) == b""
+    assert bytes(view) == b""
 
 
 def test_test_memoryview_from_buffer_invalid_strides():
@@ -463,14 +583,10 @@ def test_test_memoryview_from_buffer_invalid_strides():
 
 
 def test_test_memoryview_from_buffer_nullptr():
-    if env.PY2:
+    with pytest.raises(ValueError):
         m.test_memoryview_from_buffer_nullptr()
-    else:
-        with pytest.raises(ValueError):
-            m.test_memoryview_from_buffer_nullptr()
 
 
-@pytest.mark.skipif("env.PY2")
 def test_memoryview_from_memory():
     view = m.test_memoryview_from_memory()
     assert isinstance(view, memoryview)
@@ -486,3 +602,228 @@ def test_builtin_functions():
         "object of type 'generator' has no len()",
         "'generator' has no length",
     ]  # PyPy
+
+
+def test_isinstance_string_types():
+    assert m.isinstance_pybind11_bytes(b"")
+    assert not m.isinstance_pybind11_bytes("")
+
+    assert m.isinstance_pybind11_str("")
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert m.isinstance_pybind11_str(b"")
+    else:
+        assert not m.isinstance_pybind11_str(b"")
+
+
+def test_pass_bytes_or_unicode_to_string_types():
+    assert m.pass_to_pybind11_bytes(b"Bytes") == 5
+    with pytest.raises(TypeError):
+        m.pass_to_pybind11_bytes("Str")
+
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert m.pass_to_pybind11_str(b"Bytes") == 5
+    else:
+        with pytest.raises(TypeError):
+            m.pass_to_pybind11_str(b"Bytes")
+    assert m.pass_to_pybind11_str("Str") == 3
+
+    assert m.pass_to_std_string(b"Bytes") == 5
+    assert m.pass_to_std_string("Str") == 3
+
+    malformed_utf8 = b"\x80"
+    if hasattr(m, "PYBIND11_STR_LEGACY_PERMISSIVE"):
+        assert m.pass_to_pybind11_str(malformed_utf8) == 1
+    else:
+        with pytest.raises(TypeError):
+            m.pass_to_pybind11_str(malformed_utf8)
+
+
+@pytest.mark.parametrize(
+    "create_weakref, create_weakref_with_callback",
+    [
+        (m.weakref_from_handle, m.weakref_from_handle_and_function),
+        (m.weakref_from_object, m.weakref_from_object_and_function),
+    ],
+)
+def test_weakref(create_weakref, create_weakref_with_callback):
+    from weakref import getweakrefcount
+
+    # Apparently, you cannot weakly reference an object()
+    class WeaklyReferenced:
+        pass
+
+    callback_called = False
+
+    def callback(wr):
+        nonlocal callback_called
+        callback_called = True
+
+    obj = WeaklyReferenced()
+    assert getweakrefcount(obj) == 0
+    wr = create_weakref(obj)
+    assert getweakrefcount(obj) == 1
+
+    obj = WeaklyReferenced()
+    assert getweakrefcount(obj) == 0
+    wr = create_weakref_with_callback(obj, callback)  # noqa: F841
+    assert getweakrefcount(obj) == 1
+    assert not callback_called
+    del obj
+    pytest.gc_collect()
+    assert callback_called
+
+
+@pytest.mark.parametrize(
+    "create_weakref, has_callback",
+    [
+        (m.weakref_from_handle, False),
+        (m.weakref_from_object, False),
+        (m.weakref_from_handle_and_function, True),
+        (m.weakref_from_object_and_function, True),
+    ],
+)
+def test_weakref_err(create_weakref, has_callback):
+    class C:
+        __slots__ = []
+
+    def callback(_):
+        pass
+
+    ob = C()
+    # Should raise TypeError on CPython
+    with pytest.raises(TypeError) if not env.PYPY else contextlib.nullcontext():
+        if has_callback:
+            _ = create_weakref(ob, callback)
+        else:
+            _ = create_weakref(ob)
+
+
+def test_cpp_iterators():
+    assert m.tuple_iterator() == 12
+    assert m.dict_iterator() == 305 + 711
+    assert m.passed_iterator(iter((-7, 3))) == -4
+
+
+def test_implementation_details():
+    lst = [39, 43, 92, 49, 22, 29, 93, 98, 26, 57, 8]
+    tup = tuple(lst)
+    assert m.sequence_item_get_ssize_t(lst) == 43
+    assert m.sequence_item_set_ssize_t(lst) is None
+    assert lst[1] == "peppa"
+    assert m.sequence_item_get_size_t(lst) == 92
+    assert m.sequence_item_set_size_t(lst) is None
+    assert lst[2] == "george"
+    assert m.list_item_get_ssize_t(lst) == 49
+    assert m.list_item_set_ssize_t(lst) is None
+    assert lst[3] == "rebecca"
+    assert m.list_item_get_size_t(lst) == 22
+    assert m.list_item_set_size_t(lst) is None
+    assert lst[4] == "richard"
+    assert m.tuple_item_get_ssize_t(tup) == 29
+    assert m.tuple_item_set_ssize_t() == ("emely", "edmond")
+    assert m.tuple_item_get_size_t(tup) == 93
+    assert m.tuple_item_set_size_t() == ("candy", "cat")
+
+
+def test_external_float_():
+    r1 = m.square_float_(2.0)
+    assert r1 == 4.0
+
+
+def test_tuple_rvalue_getter():
+    pop = 1000
+    tup = tuple(range(pop))
+    m.tuple_rvalue_getter(tup)
+
+
+def test_list_rvalue_getter():
+    pop = 1000
+    my_list = list(range(pop))
+    m.list_rvalue_getter(my_list)
+
+
+def test_populate_dict_rvalue():
+    pop = 1000
+    my_dict = {i: i for i in range(pop)}
+    assert m.populate_dict_rvalue(pop) == my_dict
+
+
+def test_populate_obj_str_attrs():
+    pop = 1000
+    o = types.SimpleNamespace(**{str(i): i for i in range(pop)})
+    new_o = m.populate_obj_str_attrs(o, pop)
+    new_attrs = {k: v for k, v in new_o.__dict__.items() if not k.startswith("_")}
+    assert all(isinstance(v, str) for v in new_attrs.values())
+    assert len(new_attrs) == pop
+
+
+@pytest.mark.parametrize(
+    "a,b", [("foo", "bar"), (1, 2), (1.0, 2.0), (list(range(3)), list(range(3, 6)))]
+)
+def test_inplace_append(a, b):
+    expected = a + b
+    assert m.inplace_append(a, b) == expected
+
+
+@pytest.mark.parametrize("a,b", [(3, 2), (3.0, 2.0), (set(range(3)), set(range(2)))])
+def test_inplace_subtract(a, b):
+    expected = a - b
+    assert m.inplace_subtract(a, b) == expected
+
+
+@pytest.mark.parametrize("a,b", [(3, 2), (3.0, 2.0), ([1], 3)])
+def test_inplace_multiply(a, b):
+    expected = a * b
+    assert m.inplace_multiply(a, b) == expected
+
+
+@pytest.mark.parametrize("a,b", [(6, 3), (6.0, 3.0)])
+def test_inplace_divide(a, b):
+    expected = a / b
+    assert m.inplace_divide(a, b) == expected
+
+
+@pytest.mark.parametrize(
+    "a,b",
+    [
+        (False, True),
+        (
+            set(),
+            {
+                1,
+            },
+        ),
+    ],
+)
+def test_inplace_or(a, b):
+    expected = a | b
+    assert m.inplace_or(a, b) == expected
+
+
+@pytest.mark.parametrize(
+    "a,b",
+    [
+        (True, False),
+        (
+            {1, 2, 3},
+            {
+                1,
+            },
+        ),
+    ],
+)
+def test_inplace_and(a, b):
+    expected = a & b
+    assert m.inplace_and(a, b) == expected
+
+
+@pytest.mark.parametrize("a,b", [(8, 1), (-3, 2)])
+def test_inplace_lshift(a, b):
+    expected = a << b
+    assert m.inplace_lshift(a, b) == expected
+
+
+@pytest.mark.parametrize("a,b", [(8, 1), (-2, 2)])
+def test_inplace_rshift(a, b):
+    expected = a >> b
+    assert m.inplace_rshift(a, b) == expected
diff --git a/3rdparty/pybind11/tests/test_sequences_and_iterators.cpp b/3rdparty/pybind11/tests/test_sequences_and_iterators.cpp
index d318052a48..b867f49a25 100644
--- a/3rdparty/pybind11/tests/test_sequences_and_iterators.cpp
+++ b/3rdparty/pybind11/tests/test_sequences_and_iterators.cpp
@@ -8,38 +8,91 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/operators.h>
 #include <pybind11/stl.h>
 
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 #include <algorithm>
+#include <utility>
+#include <vector>
 
-template<typename T>
+#ifdef PYBIND11_HAS_OPTIONAL
+#    include <optional>
+#endif // PYBIND11_HAS_OPTIONAL
+
+template <typename T>
 class NonZeroIterator {
-    const T* ptr_;
+    const T *ptr_;
+
 public:
-    NonZeroIterator(const T* ptr) : ptr_(ptr) {}
-    const T& operator*() const { return *ptr_; }
-    NonZeroIterator& operator++() { ++ptr_; return *this; }
+    explicit NonZeroIterator(const T *ptr) : ptr_(ptr) {}
+    const T &operator*() const { return *ptr_; }
+    NonZeroIterator &operator++() {
+        ++ptr_;
+        return *this;
+    }
 };
 
 class NonZeroSentinel {};
 
-template<typename A, typename B>
-bool operator==(const NonZeroIterator<std::pair<A, B>>& it, const NonZeroSentinel&) {
+template <typename A, typename B>
+bool operator==(const NonZeroIterator<std::pair<A, B>> &it, const NonZeroSentinel &) {
     return !(*it).first || !(*it).second;
 }
 
+/* Iterator where dereferencing returns prvalues instead of references. */
+template <typename T>
+class NonRefIterator {
+    const T *ptr_;
+
+public:
+    explicit NonRefIterator(const T *ptr) : ptr_(ptr) {}
+    T operator*() const { return T(*ptr_); }
+    NonRefIterator &operator++() {
+        ++ptr_;
+        return *this;
+    }
+    bool operator==(const NonRefIterator &other) const { return ptr_ == other.ptr_; }
+};
+
+class NonCopyableInt {
+public:
+    explicit NonCopyableInt(int value) : value_(value) {}
+    NonCopyableInt(const NonCopyableInt &) = delete;
+    NonCopyableInt(NonCopyableInt &&other) noexcept : value_(other.value_) {
+        other.value_ = -1; // detect when an unwanted move occurs
+    }
+    NonCopyableInt &operator=(const NonCopyableInt &) = delete;
+    NonCopyableInt &operator=(NonCopyableInt &&other) noexcept {
+        value_ = other.value_;
+        other.value_ = -1; // detect when an unwanted move occurs
+        return *this;
+    }
+    int get() const { return value_; }
+    void set(int value) { value_ = value; }
+    ~NonCopyableInt() = default;
+
+private:
+    int value_;
+};
+using NonCopyableIntPair = std::pair<NonCopyableInt, NonCopyableInt>;
+PYBIND11_MAKE_OPAQUE(std::vector<NonCopyableInt>);
+PYBIND11_MAKE_OPAQUE(std::vector<NonCopyableIntPair>);
+
 template <typename PythonType>
 py::list test_random_access_iterator(PythonType x) {
-    if (x.size() < 5)
+    if (x.size() < 5) {
         throw py::value_error("Please provide at least 5 elements for testing.");
+    }
 
     auto checks = py::list();
     auto assert_equal = [&checks](py::handle a, py::handle b) {
         auto result = PyObject_RichCompareBool(a.ptr(), b.ptr(), Py_EQ);
-        if (result == -1) { throw py::error_already_set(); }
+        if (result == -1) {
+            throw py::error_already_set();
+        }
         checks.append(result != 0);
     };
 
@@ -74,63 +127,83 @@ py::list test_random_access_iterator(PythonType x) {
 
 TEST_SUBMODULE(sequences_and_iterators, m) {
     // test_sliceable
-    class Sliceable{
+    class Sliceable {
     public:
-      Sliceable(int n): size(n) {}
-      int start,stop,step;
-      int size;
+        explicit Sliceable(int n) : size(n) {}
+        int start, stop, step;
+        int size;
     };
-    py::class_<Sliceable>(m,"Sliceable")
+    py::class_<Sliceable>(m, "Sliceable")
         .def(py::init<int>())
-        .def("__getitem__",[](const Sliceable &s, py::slice slice) {
-          py::ssize_t start, stop, step, slicelength;
-          if (!slice.compute(s.size, &start, &stop, &step, &slicelength))
-              throw py::error_already_set();
-          int istart = static_cast<int>(start);
-          int istop =  static_cast<int>(stop);
-          int istep =  static_cast<int>(step);
-          return std::make_tuple(istart,istop,istep);
-        })
-        ;
+        .def("__getitem__", [](const Sliceable &s, const py::slice &slice) {
+            py::ssize_t start = 0, stop = 0, step = 0, slicelength = 0;
+            if (!slice.compute(s.size, &start, &stop, &step, &slicelength)) {
+                throw py::error_already_set();
+            }
+            int istart = static_cast<int>(start);
+            int istop = static_cast<int>(stop);
+            int istep = static_cast<int>(step);
+            return std::make_tuple(istart, istop, istep);
+        });
+
+    m.def("make_forward_slice_size_t", []() { return py::slice(0, -1, 1); });
+    m.def("make_reversed_slice_object",
+          []() { return py::slice(py::none(), py::none(), py::int_(-1)); });
+#ifdef PYBIND11_HAS_OPTIONAL
+    m.attr("has_optional") = true;
+    m.def("make_reversed_slice_size_t_optional_verbose",
+          []() { return py::slice(std::nullopt, std::nullopt, -1); });
+    // Warning: The following spelling may still compile if optional<> is not present and give
+    // wrong answers. Please use with caution.
+    m.def("make_reversed_slice_size_t_optional", []() { return py::slice({}, {}, -1); });
+#else
+    m.attr("has_optional") = false;
+#endif
 
     // test_sequence
     class Sequence {
     public:
-        Sequence(size_t size) : m_size(size) {
+        explicit Sequence(size_t size) : m_size(size) {
             print_created(this, "of size", m_size);
+            // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
             m_data = new float[size];
             memset(m_data, 0, sizeof(float) * size);
         }
-        Sequence(const std::vector<float> &value) : m_size(value.size()) {
+        explicit Sequence(const std::vector<float> &value) : m_size(value.size()) {
             print_created(this, "of size", m_size, "from std::vector");
+            // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
             m_data = new float[m_size];
             memcpy(m_data, &value[0], sizeof(float) * m_size);
         }
         Sequence(const Sequence &s) : m_size(s.m_size) {
             print_copy_created(this);
+            // NOLINTNEXTLINE(cppcoreguidelines-prefer-member-initializer)
             m_data = new float[m_size];
-            memcpy(m_data, s.m_data, sizeof(float)*m_size);
+            memcpy(m_data, s.m_data, sizeof(float) * m_size);
         }
-        Sequence(Sequence &&s) : m_size(s.m_size), m_data(s.m_data) {
+        Sequence(Sequence &&s) noexcept : m_size(s.m_size), m_data(s.m_data) {
             print_move_created(this);
             s.m_size = 0;
             s.m_data = nullptr;
         }
 
-        ~Sequence() { print_destroyed(this); delete[] m_data; }
+        ~Sequence() {
+            print_destroyed(this);
+            delete[] m_data;
+        }
 
         Sequence &operator=(const Sequence &s) {
             if (&s != this) {
                 delete[] m_data;
                 m_size = s.m_size;
                 m_data = new float[m_size];
-                memcpy(m_data, s.m_data, sizeof(float)*m_size);
+                memcpy(m_data, s.m_data, sizeof(float) * m_size);
             }
             print_copy_assigned(this);
             return *this;
         }
 
-        Sequence &operator=(Sequence &&s) {
+        Sequence &operator=(Sequence &&s) noexcept {
             if (&s != this) {
                 delete[] m_data;
                 m_size = s.m_size;
@@ -143,10 +216,14 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
         }
 
         bool operator==(const Sequence &s) const {
-            if (m_size != s.size()) return false;
-            for (size_t i = 0; i < m_size; ++i)
-                if (m_data[i] != s[i])
+            if (m_size != s.size()) {
+                return false;
+            }
+            for (size_t i = 0; i < m_size; ++i) {
+                if (m_data[i] != s[i]) {
                     return false;
+                }
+            }
             return true;
         }
         bool operator!=(const Sequence &s) const { return !operator==(s); }
@@ -155,23 +232,26 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
         float &operator[](size_t index) { return m_data[index]; }
 
         bool contains(float v) const {
-            for (size_t i = 0; i < m_size; ++i)
-                if (v == m_data[i])
+            for (size_t i = 0; i < m_size; ++i) {
+                if (v == m_data[i]) {
                     return true;
+                }
+            }
             return false;
         }
 
         Sequence reversed() const {
             Sequence result(m_size);
-            for (size_t i = 0; i < m_size; ++i)
+            for (size_t i = 0; i < m_size; ++i) {
                 result[m_size - i - 1] = m_data[i];
+            }
             return result;
         }
 
         size_t size() const { return m_size; }
 
         const float *begin() const { return m_data; }
-        const float *end() const { return m_data+m_size; }
+        const float *end() const { return m_data + m_size; }
 
     private:
         size_t m_size;
@@ -179,43 +259,59 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
     };
     py::class_<Sequence>(m, "Sequence")
         .def(py::init<size_t>())
-        .def(py::init<const std::vector<float>&>())
+        .def(py::init<const std::vector<float> &>())
         /// Bare bones interface
-        .def("__getitem__", [](const Sequence &s, size_t i) {
-            if (i >= s.size()) throw py::index_error();
-            return s[i];
-        })
-        .def("__setitem__", [](Sequence &s, size_t i, float v) {
-            if (i >= s.size()) throw py::index_error();
-            s[i] = v;
-        })
+        .def("__getitem__",
+             [](const Sequence &s, size_t i) {
+                 if (i >= s.size()) {
+                     throw py::index_error();
+                 }
+                 return s[i];
+             })
+        .def("__setitem__",
+             [](Sequence &s, size_t i, float v) {
+                 if (i >= s.size()) {
+                     throw py::index_error();
+                 }
+                 s[i] = v;
+             })
         .def("__len__", &Sequence::size)
         /// Optional sequence protocol operations
-        .def("__iter__", [](const Sequence &s) { return py::make_iterator(s.begin(), s.end()); },
-                         py::keep_alive<0, 1>() /* Essential: keep object alive while iterator exists */)
+        .def(
+            "__iter__",
+            [](const Sequence &s) { return py::make_iterator(s.begin(), s.end()); },
+            py::keep_alive<0, 1>() /* Essential: keep object alive while iterator exists */)
         .def("__contains__", [](const Sequence &s, float v) { return s.contains(v); })
         .def("__reversed__", [](const Sequence &s) -> Sequence { return s.reversed(); })
         /// Slicing protocol (optional)
-        .def("__getitem__", [](const Sequence &s, py::slice slice) -> Sequence* {
-            size_t start, stop, step, slicelength;
-            if (!slice.compute(s.size(), &start, &stop, &step, &slicelength))
-                throw py::error_already_set();
-            auto *seq = new Sequence(slicelength);
-            for (size_t i = 0; i < slicelength; ++i) {
-                (*seq)[i] = s[start]; start += step;
-            }
-            return seq;
-        })
-        .def("__setitem__", [](Sequence &s, py::slice slice, const Sequence &value) {
-            size_t start, stop, step, slicelength;
-            if (!slice.compute(s.size(), &start, &stop, &step, &slicelength))
-                throw py::error_already_set();
-            if (slicelength != value.size())
-                throw std::runtime_error("Left and right hand size of slice assignment have different sizes!");
-            for (size_t i = 0; i < slicelength; ++i) {
-                s[start] = value[i]; start += step;
-            }
-        })
+        .def("__getitem__",
+             [](const Sequence &s, const py::slice &slice) -> Sequence * {
+                 size_t start = 0, stop = 0, step = 0, slicelength = 0;
+                 if (!slice.compute(s.size(), &start, &stop, &step, &slicelength)) {
+                     throw py::error_already_set();
+                 }
+                 auto *seq = new Sequence(slicelength);
+                 for (size_t i = 0; i < slicelength; ++i) {
+                     (*seq)[i] = s[start];
+                     start += step;
+                 }
+                 return seq;
+             })
+        .def("__setitem__",
+             [](Sequence &s, const py::slice &slice, const Sequence &value) {
+                 size_t start = 0, stop = 0, step = 0, slicelength = 0;
+                 if (!slice.compute(s.size(), &start, &stop, &step, &slicelength)) {
+                     throw py::error_already_set();
+                 }
+                 if (slicelength != value.size()) {
+                     throw std::runtime_error(
+                         "Left and right hand size of slice assignment have different sizes!");
+                 }
+                 for (size_t i = 0; i < slicelength; ++i) {
+                     s[start] = value[i];
+                     start += step;
+                 }
+             })
         /// Comparisons
         .def(py::self == py::self)
         .def(py::self != py::self)
@@ -223,19 +319,21 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
         ;
 
     // test_map_iterator
-    // Interface of a map-like object that isn't (directly) an unordered_map, but provides some basic
-    // map-like functionality.
+    // Interface of a map-like object that isn't (directly) an unordered_map, but provides some
+    // basic map-like functionality.
     class StringMap {
     public:
         StringMap() = default;
-        StringMap(std::unordered_map<std::string, std::string> init)
+        explicit StringMap(std::unordered_map<std::string, std::string> init)
             : map(std::move(init)) {}
 
-        void set(std::string key, std::string val) { map[key] = val; }
-        std::string get(std::string key) const { return map.at(key); }
+        void set(const std::string &key, std::string val) { map[key] = std::move(val); }
+        std::string get(const std::string &key) const { return map.at(key); }
         size_t size() const { return map.size(); }
+
     private:
         std::unordered_map<std::string, std::string> map;
+
     public:
         decltype(map.cbegin()) begin() const { return map.cbegin(); }
         decltype(map.cend()) end() const { return map.cend(); }
@@ -243,38 +341,142 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
     py::class_<StringMap>(m, "StringMap")
         .def(py::init<>())
         .def(py::init<std::unordered_map<std::string, std::string>>())
-        .def("__getitem__", [](const StringMap &map, std::string key) {
-                try { return map.get(key); }
-                catch (const std::out_of_range&) {
-                    throw py::key_error("key '" + key + "' does not exist");
-                }
-        })
+        .def("__getitem__",
+             [](const StringMap &map, const std::string &key) {
+                 try {
+                     return map.get(key);
+                 } catch (const std::out_of_range &) {
+                     throw py::key_error("key '" + key + "' does not exist");
+                 }
+             })
         .def("__setitem__", &StringMap::set)
         .def("__len__", &StringMap::size)
-        .def("__iter__", [](const StringMap &map) { return py::make_key_iterator(map.begin(), map.end()); },
-                py::keep_alive<0, 1>())
-        .def("items", [](const StringMap &map) { return py::make_iterator(map.begin(), map.end()); },
-                py::keep_alive<0, 1>())
-        ;
+        .def(
+            "__iter__",
+            [](const StringMap &map) { return py::make_key_iterator(map.begin(), map.end()); },
+            py::keep_alive<0, 1>())
+        .def(
+            "items",
+            [](const StringMap &map) { return py::make_iterator(map.begin(), map.end()); },
+            py::keep_alive<0, 1>())
+        .def(
+            "values",
+            [](const StringMap &map) { return py::make_value_iterator(map.begin(), map.end()); },
+            py::keep_alive<0, 1>());
 
     // test_generalized_iterators
     class IntPairs {
     public:
-        IntPairs(std::vector<std::pair<int, int>> data) : data_(std::move(data)) {}
-        const std::pair<int, int>* begin() const { return data_.data(); }
+        explicit IntPairs(std::vector<std::pair<int, int>> data) : data_(std::move(data)) {}
+        const std::pair<int, int> *begin() const { return data_.data(); }
+        // .end() only required for py::make_iterator(self) overload
+        const std::pair<int, int> *end() const { return data_.data() + data_.size(); }
+
     private:
         std::vector<std::pair<int, int>> data_;
     };
     py::class_<IntPairs>(m, "IntPairs")
         .def(py::init<std::vector<std::pair<int, int>>>())
-        .def("nonzero", [](const IntPairs& s) {
-                return py::make_iterator(NonZeroIterator<std::pair<int, int>>(s.begin()), NonZeroSentinel());
-        }, py::keep_alive<0, 1>())
-        .def("nonzero_keys", [](const IntPairs& s) {
-            return py::make_key_iterator(NonZeroIterator<std::pair<int, int>>(s.begin()), NonZeroSentinel());
-        }, py::keep_alive<0, 1>())
-        ;
-
+        .def(
+            "nonzero",
+            [](const IntPairs &s) {
+                return py::make_iterator(NonZeroIterator<std::pair<int, int>>(s.begin()),
+                                         NonZeroSentinel());
+            },
+            py::keep_alive<0, 1>())
+        .def(
+            "nonzero_keys",
+            [](const IntPairs &s) {
+                return py::make_key_iterator(NonZeroIterator<std::pair<int, int>>(s.begin()),
+                                             NonZeroSentinel());
+            },
+            py::keep_alive<0, 1>())
+        .def(
+            "nonzero_values",
+            [](const IntPairs &s) {
+                return py::make_value_iterator(NonZeroIterator<std::pair<int, int>>(s.begin()),
+                                               NonZeroSentinel());
+            },
+            py::keep_alive<0, 1>())
+
+        // test iterator that returns values instead of references
+        .def(
+            "nonref",
+            [](const IntPairs &s) {
+                return py::make_iterator(NonRefIterator<std::pair<int, int>>(s.begin()),
+                                         NonRefIterator<std::pair<int, int>>(s.end()));
+            },
+            py::keep_alive<0, 1>())
+        .def(
+            "nonref_keys",
+            [](const IntPairs &s) {
+                return py::make_key_iterator(NonRefIterator<std::pair<int, int>>(s.begin()),
+                                             NonRefIterator<std::pair<int, int>>(s.end()));
+            },
+            py::keep_alive<0, 1>())
+        .def(
+            "nonref_values",
+            [](const IntPairs &s) {
+                return py::make_value_iterator(NonRefIterator<std::pair<int, int>>(s.begin()),
+                                               NonRefIterator<std::pair<int, int>>(s.end()));
+            },
+            py::keep_alive<0, 1>())
+
+        // test single-argument make_iterator
+        .def(
+            "simple_iterator",
+            [](IntPairs &self) { return py::make_iterator(self); },
+            py::keep_alive<0, 1>())
+        .def(
+            "simple_keys",
+            [](IntPairs &self) { return py::make_key_iterator(self); },
+            py::keep_alive<0, 1>())
+        .def(
+            "simple_values",
+            [](IntPairs &self) { return py::make_value_iterator(self); },
+            py::keep_alive<0, 1>())
+
+        // Test iterator with an Extra (doesn't do anything useful, so not used
+        // at runtime, but tests need to be able to compile with the correct
+        // overload. See PR #3293.
+        .def(
+            "_make_iterator_extras",
+            [](IntPairs &self) { return py::make_iterator(self, py::call_guard<int>()); },
+            py::keep_alive<0, 1>())
+        .def(
+            "_make_key_extras",
+            [](IntPairs &self) { return py::make_key_iterator(self, py::call_guard<int>()); },
+            py::keep_alive<0, 1>())
+        .def(
+            "_make_value_extras",
+            [](IntPairs &self) { return py::make_value_iterator(self, py::call_guard<int>()); },
+            py::keep_alive<0, 1>());
+
+    // test_iterator_referencing
+    py::class_<NonCopyableInt>(m, "NonCopyableInt")
+        .def(py::init<int>())
+        .def("set", &NonCopyableInt::set)
+        .def("__int__", &NonCopyableInt::get);
+    py::class_<std::vector<NonCopyableInt>>(m, "VectorNonCopyableInt")
+        .def(py::init<>())
+        .def("append",
+             [](std::vector<NonCopyableInt> &vec, int value) { vec.emplace_back(value); })
+        .def("__iter__", [](std::vector<NonCopyableInt> &vec) {
+            return py::make_iterator(vec.begin(), vec.end());
+        });
+    py::class_<std::vector<NonCopyableIntPair>>(m, "VectorNonCopyableIntPair")
+        .def(py::init<>())
+        .def("append",
+             [](std::vector<NonCopyableIntPair> &vec, const std::pair<int, int> &value) {
+                 vec.emplace_back(NonCopyableInt(value.first), NonCopyableInt(value.second));
+             })
+        .def("keys",
+             [](std::vector<NonCopyableIntPair> &vec) {
+                 return py::make_key_iterator(vec.begin(), vec.end());
+             })
+        .def("values", [](std::vector<NonCopyableIntPair> &vec) {
+            return py::make_value_iterator(vec.begin(), vec.end());
+        });
 
 #if 0
     // Obsolete: special data structure for exposing custom iterator types to python
@@ -304,7 +506,7 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
 #endif
 
     // test_python_iterator_in_cpp
-    m.def("object_to_list", [](py::object o) {
+    m.def("object_to_list", [](const py::object &o) {
         auto l = py::list();
         for (auto item : o) {
             l.append(item);
@@ -322,22 +524,22 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
     });
 
     // test_sequence_length: check that Python sequences can be converted to py::sequence.
-    m.def("sequence_length", [](py::sequence seq) { return seq.size(); });
+    m.def("sequence_length", [](const py::sequence &seq) { return seq.size(); });
 
     // Make sure that py::iterator works with std algorithms
-    m.def("count_none", [](py::object o) {
+    m.def("count_none", [](const py::object &o) {
         return std::count_if(o.begin(), o.end(), [](py::handle h) { return h.is_none(); });
     });
 
-    m.def("find_none", [](py::object o) {
+    m.def("find_none", [](const py::object &o) {
         auto it = std::find_if(o.begin(), o.end(), [](py::handle h) { return h.is_none(); });
         return it->is_none();
     });
 
-    m.def("count_nonzeros", [](py::dict d) {
-       return std::count_if(d.begin(), d.end(), [](std::pair<py::handle, py::handle> p) {
-           return p.second.cast<int>() != 0;
-       });
+    m.def("count_nonzeros", [](const py::dict &d) {
+        return std::count_if(d.begin(), d.end(), [](std::pair<py::handle, py::handle> p) {
+            return p.second.cast<int>() != 0;
+        });
     });
 
     m.def("tuple_iterator", &test_random_access_iterator<py::tuple>);
@@ -352,7 +554,9 @@ TEST_SUBMODULE(sequences_and_iterators, m) {
 
     // test_iterator_rvp
     // #388: Can't make iterators via make_iterator() with different r/v policies
-    static std::vector<int> list = { 1, 2, 3 };
-    m.def("make_iterator_1", []() { return py::make_iterator<py::return_value_policy::copy>(list); });
-    m.def("make_iterator_2", []() { return py::make_iterator<py::return_value_policy::automatic>(list); });
+    static std::vector<int> list = {1, 2, 3};
+    m.def("make_iterator_1",
+          []() { return py::make_iterator<py::return_value_policy::copy>(list); });
+    m.def("make_iterator_2",
+          []() { return py::make_iterator<py::return_value_policy::automatic>(list); });
 }
diff --git a/3rdparty/pybind11/tests/test_sequences_and_iterators.py b/3rdparty/pybind11/tests/test_sequences_and_iterators.py
index c3b608c436..062e3b3d30 100644
--- a/3rdparty/pybind11/tests/test_sequences_and_iterators.py
+++ b/3rdparty/pybind11/tests/test_sequences_and_iterators.py
@@ -1,18 +1,19 @@
-# -*- coding: utf-8 -*-
 import pytest
-from pybind11_tests import sequences_and_iterators as m
+from pytest import approx
+
 from pybind11_tests import ConstructorStats
+from pybind11_tests import sequences_and_iterators as m
 
 
-def isclose(a, b, rel_tol=1e-05, abs_tol=0.0):
-    """Like math.isclose() from Python 3.5"""
-    return abs(a - b) <= max(rel_tol * max(abs(a), abs(b)), abs_tol)
+def test_slice_constructors():
+    assert m.make_forward_slice_size_t() == slice(0, -1, 1)
+    assert m.make_reversed_slice_object() == slice(None, None, -1)
 
 
-def allclose(a_list, b_list, rel_tol=1e-05, abs_tol=0.0):
-    return all(
-        isclose(a, b, rel_tol=rel_tol, abs_tol=abs_tol) for a, b in zip(a_list, b_list)
-    )
+@pytest.mark.skipif(not m.has_optional, reason="no <optional>")
+def test_slice_constructors_explicit_optional():
+    assert m.make_reversed_slice_size_t_optional() == slice(None, None, -1)
+    assert m.make_reversed_slice_size_t_optional_verbose() == slice(None, None, -1)
 
 
 def test_generalized_iterators():
@@ -24,6 +25,10 @@ def test_generalized_iterators():
     assert list(m.IntPairs([(1, 2), (2, 0), (0, 3), (4, 5)]).nonzero_keys()) == [1]
     assert list(m.IntPairs([(0, 3), (1, 2), (3, 4)]).nonzero_keys()) == []
 
+    assert list(m.IntPairs([(1, 2), (3, 4), (0, 5)]).nonzero_values()) == [2, 4]
+    assert list(m.IntPairs([(1, 2), (2, 0), (0, 3), (4, 5)]).nonzero_values()) == [2]
+    assert list(m.IntPairs([(0, 3), (1, 2), (3, 4)]).nonzero_values()) == []
+
     # __next__ must continue to raise StopIteration
     it = m.IntPairs([(0, 0)]).nonzero()
     for _ in range(3):
@@ -36,6 +41,47 @@ def test_generalized_iterators():
             next(it)
 
 
+def test_nonref_iterators():
+    pairs = m.IntPairs([(1, 2), (3, 4), (0, 5)])
+    assert list(pairs.nonref()) == [(1, 2), (3, 4), (0, 5)]
+    assert list(pairs.nonref_keys()) == [1, 3, 0]
+    assert list(pairs.nonref_values()) == [2, 4, 5]
+
+
+def test_generalized_iterators_simple():
+    assert list(m.IntPairs([(1, 2), (3, 4), (0, 5)]).simple_iterator()) == [
+        (1, 2),
+        (3, 4),
+        (0, 5),
+    ]
+    assert list(m.IntPairs([(1, 2), (3, 4), (0, 5)]).simple_keys()) == [1, 3, 0]
+    assert list(m.IntPairs([(1, 2), (3, 4), (0, 5)]).simple_values()) == [2, 4, 5]
+
+
+def test_iterator_referencing():
+    """Test that iterators reference rather than copy their referents."""
+    vec = m.VectorNonCopyableInt()
+    vec.append(3)
+    vec.append(5)
+    assert [int(x) for x in vec] == [3, 5]
+    # Increment everything to make sure the referents can be mutated
+    for x in vec:
+        x.set(int(x) + 1)
+    assert [int(x) for x in vec] == [4, 6]
+
+    vec = m.VectorNonCopyableIntPair()
+    vec.append([3, 4])
+    vec.append([5, 7])
+    assert [int(x) for x in vec.keys()] == [3, 5]
+    assert [int(x) for x in vec.values()] == [4, 7]
+    for x in vec.keys():
+        x.set(int(x) + 1)
+    for x in vec.values():
+        x.set(int(x) + 10)
+    assert [int(x) for x in vec.keys()] == [4, 6]
+    assert [int(x) for x in vec.values()] == [14, 17]
+
+
 def test_sliceable():
     sliceable = m.Sliceable(100)
     assert sliceable[::] == (0, 100, 1)
@@ -61,7 +107,8 @@ def test_sequence():
     assert 12.34 not in s
     s[0], s[3] = 12.34, 56.78
     assert 12.34 in s
-    assert isclose(s[0], 12.34) and isclose(s[3], 56.78)
+    assert s[0] == approx(12.34, rel=1e-05)
+    assert s[3] == approx(56.78, rel=1e-05)
 
     rev = reversed(s)
     assert cstats.values() == ["of size", "5"]
@@ -76,14 +123,14 @@ def test_sequence():
     assert cstats.values() == ["of size", "0"]
 
     expected = [0, 56.78, 0, 0, 12.34]
-    assert allclose(rev, expected)
-    assert allclose(rev2, expected)
+    assert rev == approx(expected, rel=1e-05)
+    assert rev2 == approx(expected, rel=1e-05)
     assert rev == rev2
 
     rev[0::2] = m.Sequence([2.0, 2.0, 2.0])
     assert cstats.values() == ["of size", "3", "from std::vector"]
 
-    assert allclose(rev, [2, 56.78, 2, 0, 2])
+    assert rev == approx([2, 56.78, 2, 0, 2], rel=1e-05)
 
     assert cstats.alive() == 4
     del it
@@ -104,7 +151,7 @@ def test_sequence():
 
 
 def test_sequence_length():
-    """#2076: Exception raised by len(arg) should be propagated """
+    """#2076: Exception raised by len(arg) should be propagated"""
 
     class BadLen(RuntimeError):
         pass
@@ -139,6 +186,7 @@ def test_map_iterator():
         assert sm[k] == expected[k]
     for k, v in sm.items():
         assert v == expected[k]
+    assert list(sm.values()) == [expected[k] for k in sm]
 
     it = iter(m.StringMap({}))
     for _ in range(3):  # __next__ must continue to raise StopIteration
@@ -187,7 +235,7 @@ def test_iterator_passthrough():
 
 
 def test_iterator_rvp():
-    """#388: Can't make iterators via make_iterator() with different r/v policies """
+    """#388: Can't make iterators via make_iterator() with different r/v policies"""
     import pybind11_tests.sequences_and_iterators as m
 
     assert list(m.make_iterator_1()) == [1, 2, 3]
diff --git a/3rdparty/pybind11/tests/test_smart_ptr.cpp b/3rdparty/pybind11/tests/test_smart_ptr.cpp
index 60c2e692e5..6d9efcedce 100644
--- a/3rdparty/pybind11/tests/test_smart_ptr.cpp
+++ b/3rdparty/pybind11/tests/test_smart_ptr.cpp
@@ -8,53 +8,34 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#if defined(_MSC_VER) && _MSC_VER < 1910
-#  pragma warning(disable: 4702) // unreachable code in system header
-#endif
-
-#include "pybind11_tests.h"
 #include "object.h"
+#include "pybind11_tests.h"
 
-// Make pybind aware of the ref-counted wrapper type (s):
-
-// ref<T> is a wrapper for 'Object' which uses intrusive reference counting
-// It is always possible to construct a ref<T> from an Object* pointer without
-// possible inconsistencies, hence the 'true' argument at the end.
-PYBIND11_DECLARE_HOLDER_TYPE(T, ref<T>, true);
-// Make pybind11 aware of the non-standard getter member function
-namespace pybind11 { namespace detail {
-    template <typename T>
-    struct holder_helper<ref<T>> {
-        static const T *get(const ref<T> &p) { return p.get_ptr(); }
-    };
-} // namespace detail
-} // namespace pybind11
-
-// The following is not required anymore for std::shared_ptr, but it should compile without error:
-PYBIND11_DECLARE_HOLDER_TYPE(T, std::shared_ptr<T>);
+namespace {
 
 // This is just a wrapper around unique_ptr, but with extra fields to deliberately bloat up the
-// holder size to trigger the non-simple-layout internal instance layout for single inheritance with
-// large holder type:
-template <typename T> class huge_unique_ptr {
+// holder size to trigger the non-simple-layout internal instance layout for single inheritance
+// with large holder type:
+template <typename T>
+class huge_unique_ptr {
     std::unique_ptr<T> ptr;
     uint64_t padding[10];
+
 public:
-    huge_unique_ptr(T *p) : ptr(p) {};
+    explicit huge_unique_ptr(T *p) : ptr(p) {}
     T *get() { return ptr.get(); }
 };
-PYBIND11_DECLARE_HOLDER_TYPE(T, huge_unique_ptr<T>);
 
 // Simple custom holder that works like unique_ptr
 template <typename T>
 class custom_unique_ptr {
     std::unique_ptr<T> impl;
+
 public:
-    custom_unique_ptr(T* p) : impl(p) { }
-    T* get() const { return impl.get(); }
-    T* release_ptr() { return impl.release(); }
+    explicit custom_unique_ptr(T *p) : impl(p) {}
+    T *get() const { return impl.get(); }
+    T *release_ptr() { return impl.release(); }
 };
-PYBIND11_DECLARE_HOLDER_TYPE(T, custom_unique_ptr<T>);
 
 // Simple custom holder that works like shared_ptr and has operator& overload
 // To obtain address of an instance of this holder pybind should use std::addressof
@@ -62,13 +43,13 @@ PYBIND11_DECLARE_HOLDER_TYPE(T, custom_unique_ptr<T>);
 template <typename T>
 class shared_ptr_with_addressof_operator {
     std::shared_ptr<T> impl;
+
 public:
-    shared_ptr_with_addressof_operator( ) = default;
-    shared_ptr_with_addressof_operator(T* p) : impl(p) { }
-    T* get() const { return impl.get(); }
-    T** operator&() { throw std::logic_error("Call of overloaded operator& is not expected"); }
+    shared_ptr_with_addressof_operator() = default;
+    explicit shared_ptr_with_addressof_operator(T *p) : impl(p) {}
+    T *get() const { return impl.get(); }
+    T **operator&() { throw std::logic_error("Call of overloaded operator& is not expected"); }
 };
-PYBIND11_DECLARE_HOLDER_TYPE(T, shared_ptr_with_addressof_operator<T>);
 
 // Simple custom holder that works like unique_ptr and has operator& overload
 // To obtain address of an instance of this holder pybind should use std::addressof
@@ -76,17 +57,237 @@ PYBIND11_DECLARE_HOLDER_TYPE(T, shared_ptr_with_addressof_operator<T>);
 template <typename T>
 class unique_ptr_with_addressof_operator {
     std::unique_ptr<T> impl;
+
 public:
     unique_ptr_with_addressof_operator() = default;
-    unique_ptr_with_addressof_operator(T* p) : impl(p) { }
-    T* get() const { return impl.get(); }
-    T* release_ptr() { return impl.release(); }
-    T** operator&() { throw std::logic_error("Call of overloaded operator& is not expected"); }
+    explicit unique_ptr_with_addressof_operator(T *p) : impl(p) {}
+    T *get() const { return impl.get(); }
+    T *release_ptr() { return impl.release(); }
+    T **operator&() { throw std::logic_error("Call of overloaded operator& is not expected"); }
+};
+
+// Custom object with builtin reference counting (see 'object.h' for the implementation)
+class MyObject1 : public Object {
+public:
+    explicit MyObject1(int value) : value(value) { print_created(this, toString()); }
+    std::string toString() const override { return "MyObject1[" + std::to_string(value) + "]"; }
+
+protected:
+    ~MyObject1() override { print_destroyed(this); }
+
+private:
+    int value;
+};
+
+// Object managed by a std::shared_ptr<>
+class MyObject2 {
+public:
+    MyObject2(const MyObject2 &) = default;
+    explicit MyObject2(int value) : value(value) { print_created(this, toString()); }
+    std::string toString() const { return "MyObject2[" + std::to_string(value) + "]"; }
+    virtual ~MyObject2() { print_destroyed(this); }
+
+private:
+    int value;
+};
+
+// Object managed by a std::shared_ptr<>, additionally derives from std::enable_shared_from_this<>
+class MyObject3 : public std::enable_shared_from_this<MyObject3> {
+public:
+    MyObject3(const MyObject3 &) = default;
+    explicit MyObject3(int value) : value(value) { print_created(this, toString()); }
+    std::string toString() const { return "MyObject3[" + std::to_string(value) + "]"; }
+    virtual ~MyObject3() { print_destroyed(this); }
+
+private:
+    int value;
+};
+
+// test_unique_nodelete
+// Object with a private destructor
+class MyObject4;
+std::unordered_set<MyObject4 *> myobject4_instances;
+class MyObject4 {
+public:
+    explicit MyObject4(int value) : value{value} {
+        print_created(this);
+        myobject4_instances.insert(this);
+    }
+    int value;
+
+    static void cleanupAllInstances() {
+        auto tmp = std::move(myobject4_instances);
+        myobject4_instances.clear();
+        for (auto *o : tmp) {
+            delete o;
+        }
+    }
+
+private:
+    ~MyObject4() {
+        myobject4_instances.erase(this);
+        print_destroyed(this);
+    }
+};
+
+// test_unique_deleter
+// Object with std::unique_ptr<T, D> where D is not matching the base class
+// Object with a protected destructor
+class MyObject4a;
+std::unordered_set<MyObject4a *> myobject4a_instances;
+class MyObject4a {
+public:
+    explicit MyObject4a(int i) : value{i} {
+        print_created(this);
+        myobject4a_instances.insert(this);
+    };
+    int value;
+
+    static void cleanupAllInstances() {
+        auto tmp = std::move(myobject4a_instances);
+        myobject4a_instances.clear();
+        for (auto *o : tmp) {
+            delete o;
+        }
+    }
+
+protected:
+    virtual ~MyObject4a() {
+        myobject4a_instances.erase(this);
+        print_destroyed(this);
+    }
+};
+
+// Object derived but with public destructor and no Deleter in default holder
+class MyObject4b : public MyObject4a {
+public:
+    explicit MyObject4b(int i) : MyObject4a(i) { print_created(this); }
+    ~MyObject4b() override { print_destroyed(this); }
+};
+
+// test_large_holder
+class MyObject5 { // managed by huge_unique_ptr
+public:
+    explicit MyObject5(int value) : value{value} { print_created(this); }
+    ~MyObject5() { print_destroyed(this); }
+    int value;
+};
+
+// test_shared_ptr_and_references
+struct SharedPtrRef {
+    struct A {
+        A() { print_created(this); }
+        A(const A &) { print_copy_created(this); }
+        A(A &&) noexcept { print_move_created(this); }
+        ~A() { print_destroyed(this); }
+    };
+
+    A value = {};
+    std::shared_ptr<A> shared = std::make_shared<A>();
 };
-PYBIND11_DECLARE_HOLDER_TYPE(T, unique_ptr_with_addressof_operator<T>);
 
+// test_shared_ptr_from_this_and_references
+struct SharedFromThisRef {
+    struct B : std::enable_shared_from_this<B> {
+        B() { print_created(this); }
+        // NOLINTNEXTLINE(bugprone-copy-constructor-init)
+        B(const B &) : std::enable_shared_from_this<B>() { print_copy_created(this); }
+        B(B &&) noexcept : std::enable_shared_from_this<B>() { print_move_created(this); }
+        ~B() { print_destroyed(this); }
+    };
+
+    B value = {};
+    std::shared_ptr<B> shared = std::make_shared<B>();
+};
+
+// Issue #865: shared_from_this doesn't work with virtual inheritance
+struct SharedFromThisVBase : std::enable_shared_from_this<SharedFromThisVBase> {
+    SharedFromThisVBase() = default;
+    SharedFromThisVBase(const SharedFromThisVBase &) = default;
+    virtual ~SharedFromThisVBase() = default;
+};
+struct SharedFromThisVirt : virtual SharedFromThisVBase {};
+
+// test_move_only_holder
+struct C {
+    C() { print_created(this); }
+    ~C() { print_destroyed(this); }
+};
+
+// test_holder_with_addressof_operator
+struct TypeForHolderWithAddressOf {
+    TypeForHolderWithAddressOf() { print_created(this); }
+    TypeForHolderWithAddressOf(const TypeForHolderWithAddressOf &) { print_copy_created(this); }
+    TypeForHolderWithAddressOf(TypeForHolderWithAddressOf &&) noexcept {
+        print_move_created(this);
+    }
+    ~TypeForHolderWithAddressOf() { print_destroyed(this); }
+    std::string toString() const {
+        return "TypeForHolderWithAddressOf[" + std::to_string(value) + "]";
+    }
+    int value = 42;
+};
+
+// test_move_only_holder_with_addressof_operator
+struct TypeForMoveOnlyHolderWithAddressOf {
+    explicit TypeForMoveOnlyHolderWithAddressOf(int value) : value{value} { print_created(this); }
+    ~TypeForMoveOnlyHolderWithAddressOf() { print_destroyed(this); }
+    std::string toString() const {
+        return "MoveOnlyHolderWithAddressOf[" + std::to_string(value) + "]";
+    }
+    int value;
+};
+
+// test_smart_ptr_from_default
+struct HeldByDefaultHolder {};
+
+// test_shared_ptr_gc
+// #187: issue involving std::shared_ptr<> return value policy & garbage collection
+struct ElementBase {
+    virtual ~ElementBase() = default; /* Force creation of virtual table */
+    ElementBase() = default;
+    ElementBase(const ElementBase &) = delete;
+};
+
+struct ElementA : ElementBase {
+    explicit ElementA(int v) : v(v) {}
+    int value() const { return v; }
+    int v;
+};
+
+struct ElementList {
+    void add(const std::shared_ptr<ElementBase> &e) { l.push_back(e); }
+    std::vector<std::shared_ptr<ElementBase>> l;
+};
+
+} // namespace
+
+// ref<T> is a wrapper for 'Object' which uses intrusive reference counting
+// It is always possible to construct a ref<T> from an Object* pointer without
+// possible inconsistencies, hence the 'true' argument at the end.
+// Make pybind11 aware of the non-standard getter member function
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <typename T>
+struct holder_helper<ref<T>> {
+    static const T *get(const ref<T> &p) { return p.get_ptr(); }
+};
+} // namespace detail
+} // namespace PYBIND11_NAMESPACE
+
+// Make pybind aware of the ref-counted wrapper type (s):
+PYBIND11_DECLARE_HOLDER_TYPE(T, ref<T>, true);
+// The following is not required anymore for std::shared_ptr, but it should compile without error:
+PYBIND11_DECLARE_HOLDER_TYPE(T, std::shared_ptr<T>);
+PYBIND11_DECLARE_HOLDER_TYPE(T, huge_unique_ptr<T>);
+PYBIND11_DECLARE_HOLDER_TYPE(T, custom_unique_ptr<T>);
+PYBIND11_DECLARE_HOLDER_TYPE(T, shared_ptr_with_addressof_operator<T>);
+PYBIND11_DECLARE_HOLDER_TYPE(T, unique_ptr_with_addressof_operator<T>);
 
 TEST_SUBMODULE(smart_ptr, m) {
+    // Please do not interleave `struct` and `class` definitions with bindings code,
+    // but implement `struct`s and `class`es in the anonymous namespace above.
+    // This helps keeping the smart_holder branch in sync with master.
 
     // test_smart_ptr
 
@@ -94,24 +295,13 @@ TEST_SUBMODULE(smart_ptr, m) {
     py::class_<Object, ref<Object>> obj(m, "Object");
     obj.def("getRefCount", &Object::getRefCount);
 
-    // Custom object with builtin reference counting (see 'object.h' for the implementation)
-    class MyObject1 : public Object {
-    public:
-        MyObject1(int value) : value(value) { print_created(this, toString()); }
-        std::string toString() const override { return "MyObject1[" + std::to_string(value) + "]"; }
-    protected:
-        ~MyObject1() override { print_destroyed(this); }
-    private:
-        int value;
-    };
-    py::class_<MyObject1, ref<MyObject1>>(m, "MyObject1", obj)
-        .def(py::init<int>());
+    py::class_<MyObject1, ref<MyObject1>>(m, "MyObject1", obj).def(py::init<int>());
     py::implicitly_convertible<py::int_, MyObject1>();
 
     m.def("make_object_1", []() -> Object * { return new MyObject1(1); });
-    m.def("make_object_2", []() -> ref<Object> { return new MyObject1(2); });
+    m.def("make_object_2", []() -> ref<Object> { return ref<Object>(new MyObject1(2)); });
     m.def("make_myobject1_1", []() -> MyObject1 * { return new MyObject1(4); });
-    m.def("make_myobject1_2", []() -> ref<MyObject1> { return new MyObject1(5); });
+    m.def("make_myobject1_2", []() -> ref<MyObject1> { return ref<MyObject1>(new MyObject1(5)); });
     m.def("print_object_1", [](const Object *obj) { py::print(obj->toString()); });
     m.def("print_object_2", [](ref<Object> obj) { py::print(obj->toString()); });
     m.def("print_object_3", [](const ref<Object> &obj) { py::print(obj->toString()); });
@@ -124,48 +314,31 @@ TEST_SUBMODULE(smart_ptr, m) {
     // Expose constructor stats for the ref type
     m.def("cstats_ref", &ConstructorStats::get<ref_tag>);
 
-
-    // Object managed by a std::shared_ptr<>
-    class MyObject2 {
-    public:
-        MyObject2(const MyObject2 &) = default;
-        MyObject2(int value) : value(value) { print_created(this, toString()); }
-        std::string toString() const { return "MyObject2[" + std::to_string(value) + "]"; }
-        virtual ~MyObject2() { print_destroyed(this); }
-    private:
-        int value;
-    };
-    py::class_<MyObject2, std::shared_ptr<MyObject2>>(m, "MyObject2")
-        .def(py::init<int>());
+    py::class_<MyObject2, std::shared_ptr<MyObject2>>(m, "MyObject2").def(py::init<int>());
     m.def("make_myobject2_1", []() { return new MyObject2(6); });
     m.def("make_myobject2_2", []() { return std::make_shared<MyObject2>(7); });
     m.def("print_myobject2_1", [](const MyObject2 *obj) { py::print(obj->toString()); });
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
     m.def("print_myobject2_2", [](std::shared_ptr<MyObject2> obj) { py::print(obj->toString()); });
-    m.def("print_myobject2_3", [](const std::shared_ptr<MyObject2> &obj) { py::print(obj->toString()); });
-    m.def("print_myobject2_4", [](const std::shared_ptr<MyObject2> *obj) { py::print((*obj)->toString()); });
-
-    // Object managed by a std::shared_ptr<>, additionally derives from std::enable_shared_from_this<>
-    class MyObject3 : public std::enable_shared_from_this<MyObject3> {
-    public:
-        MyObject3(const MyObject3 &) = default;
-        MyObject3(int value) : value(value) { print_created(this, toString()); }
-        std::string toString() const { return "MyObject3[" + std::to_string(value) + "]"; }
-        virtual ~MyObject3() { print_destroyed(this); }
-    private:
-        int value;
-    };
-    py::class_<MyObject3, std::shared_ptr<MyObject3>>(m, "MyObject3")
-        .def(py::init<int>());
+    m.def("print_myobject2_3",
+          [](const std::shared_ptr<MyObject2> &obj) { py::print(obj->toString()); });
+    m.def("print_myobject2_4",
+          [](const std::shared_ptr<MyObject2> *obj) { py::print((*obj)->toString()); });
+
+    py::class_<MyObject3, std::shared_ptr<MyObject3>>(m, "MyObject3").def(py::init<int>());
     m.def("make_myobject3_1", []() { return new MyObject3(8); });
     m.def("make_myobject3_2", []() { return std::make_shared<MyObject3>(9); });
     m.def("print_myobject3_1", [](const MyObject3 *obj) { py::print(obj->toString()); });
+    // NOLINTNEXTLINE(performance-unnecessary-value-param)
     m.def("print_myobject3_2", [](std::shared_ptr<MyObject3> obj) { py::print(obj->toString()); });
-    m.def("print_myobject3_3", [](const std::shared_ptr<MyObject3> &obj) { py::print(obj->toString()); });
-    m.def("print_myobject3_4", [](const std::shared_ptr<MyObject3> *obj) { py::print((*obj)->toString()); });
+    m.def("print_myobject3_3",
+          [](const std::shared_ptr<MyObject3> &obj) { py::print(obj->toString()); });
+    m.def("print_myobject3_4",
+          [](const std::shared_ptr<MyObject3> *obj) { py::print((*obj)->toString()); });
 
     // test_smart_ptr_refcounting
     m.def("test_object1_refcounting", []() {
-        ref<MyObject1> o = new MyObject1(0);
+        auto o = ref<MyObject1>(new MyObject1(0));
         bool good = o->getRefCount() == 1;
         py::object o2 = py::cast(o, py::return_value_policy::reference);
         // always request (partial) ownership for objects with intrusive
@@ -175,196 +348,123 @@ TEST_SUBMODULE(smart_ptr, m) {
     });
 
     // test_unique_nodelete
-    // Object with a private destructor
-    class MyObject4 {
-    public:
-        MyObject4(int value) : value{value} { print_created(this); }
-        int value;
-    private:
-        ~MyObject4() { print_destroyed(this); }
-    };
     py::class_<MyObject4, std::unique_ptr<MyObject4, py::nodelete>>(m, "MyObject4")
         .def(py::init<int>())
-        .def_readwrite("value", &MyObject4::value);
+        .def_readwrite("value", &MyObject4::value)
+        .def_static("cleanup_all_instances", &MyObject4::cleanupAllInstances);
 
     // test_unique_deleter
-    // Object with std::unique_ptr<T, D> where D is not matching the base class
-    // Object with a protected destructor
-    class MyObject4a {
-    public:
-        MyObject4a(int i) {
-            value = i;
-            print_created(this);
-        };
-        int value;
-    protected:
-        virtual ~MyObject4a() { print_destroyed(this); }
-    };
     py::class_<MyObject4a, std::unique_ptr<MyObject4a, py::nodelete>>(m, "MyObject4a")
         .def(py::init<int>())
-        .def_readwrite("value", &MyObject4a::value);
+        .def_readwrite("value", &MyObject4a::value)
+        .def_static("cleanup_all_instances", &MyObject4a::cleanupAllInstances);
 
-    // Object derived but with public destructor and no Deleter in default holder
-    class MyObject4b : public MyObject4a {
-    public:
-        MyObject4b(int i) : MyObject4a(i) { print_created(this); }
-        ~MyObject4b() override { print_destroyed(this); }
-    };
-    py::class_<MyObject4b, MyObject4a>(m, "MyObject4b")
+    py::class_<MyObject4b, MyObject4a, std::unique_ptr<MyObject4b>>(m, "MyObject4b")
         .def(py::init<int>());
 
     // test_large_holder
-    class MyObject5 { // managed by huge_unique_ptr
-    public:
-        MyObject5(int value) : value{value} { print_created(this); }
-        ~MyObject5() { print_destroyed(this); }
-        int value;
-    };
     py::class_<MyObject5, huge_unique_ptr<MyObject5>>(m, "MyObject5")
         .def(py::init<int>())
         .def_readwrite("value", &MyObject5::value);
 
     // test_shared_ptr_and_references
-    struct SharedPtrRef {
-        struct A {
-            A() { print_created(this); }
-            A(const A &) { print_copy_created(this); }
-            A(A &&) { print_move_created(this); }
-            ~A() { print_destroyed(this); }
-        };
-
-        A value = {};
-        std::shared_ptr<A> shared = std::make_shared<A>();
-    };
     using A = SharedPtrRef::A;
     py::class_<A, std::shared_ptr<A>>(m, "A");
-    py::class_<SharedPtrRef>(m, "SharedPtrRef")
+    py::class_<SharedPtrRef, std::unique_ptr<SharedPtrRef>>(m, "SharedPtrRef")
         .def(py::init<>())
         .def_readonly("ref", &SharedPtrRef::value)
-        .def_property_readonly("copy", [](const SharedPtrRef &s) { return s.value; },
-                               py::return_value_policy::copy)
+        .def_property_readonly(
+            "copy", [](const SharedPtrRef &s) { return s.value; }, py::return_value_policy::copy)
         .def_readonly("holder_ref", &SharedPtrRef::shared)
-        .def_property_readonly("holder_copy", [](const SharedPtrRef &s) { return s.shared; },
-                               py::return_value_policy::copy)
+        .def_property_readonly(
+            "holder_copy",
+            [](const SharedPtrRef &s) { return s.shared; },
+            py::return_value_policy::copy)
         .def("set_ref", [](SharedPtrRef &, const A &) { return true; })
+        // NOLINTNEXTLINE(performance-unnecessary-value-param)
         .def("set_holder", [](SharedPtrRef &, std::shared_ptr<A>) { return true; });
 
     // test_shared_ptr_from_this_and_references
-    struct SharedFromThisRef {
-        struct B : std::enable_shared_from_this<B> {
-            B() { print_created(this); }
-            B(const B &) : std::enable_shared_from_this<B>() { print_copy_created(this); }
-            B(B &&) : std::enable_shared_from_this<B>() { print_move_created(this); }
-            ~B() { print_destroyed(this); }
-        };
-
-        B value = {};
-        std::shared_ptr<B> shared = std::make_shared<B>();
-    };
     using B = SharedFromThisRef::B;
     py::class_<B, std::shared_ptr<B>>(m, "B");
-    py::class_<SharedFromThisRef>(m, "SharedFromThisRef")
+    py::class_<SharedFromThisRef, std::unique_ptr<SharedFromThisRef>>(m, "SharedFromThisRef")
         .def(py::init<>())
         .def_readonly("bad_wp", &SharedFromThisRef::value)
-        .def_property_readonly("ref", [](const SharedFromThisRef &s) -> const B & { return *s.shared; })
-        .def_property_readonly("copy", [](const SharedFromThisRef &s) { return s.value; },
-                               py::return_value_policy::copy)
+        .def_property_readonly("ref",
+                               [](const SharedFromThisRef &s) -> const B & { return *s.shared; })
+        .def_property_readonly(
+            "copy",
+            [](const SharedFromThisRef &s) { return s.value; },
+            py::return_value_policy::copy)
         .def_readonly("holder_ref", &SharedFromThisRef::shared)
-        .def_property_readonly("holder_copy", [](const SharedFromThisRef &s) { return s.shared; },
-                               py::return_value_policy::copy)
+        .def_property_readonly(
+            "holder_copy",
+            [](const SharedFromThisRef &s) { return s.shared; },
+            py::return_value_policy::copy)
         .def("set_ref", [](SharedFromThisRef &, const B &) { return true; })
+        // NOLINTNEXTLINE(performance-unnecessary-value-param)
         .def("set_holder", [](SharedFromThisRef &, std::shared_ptr<B>) { return true; });
 
     // Issue #865: shared_from_this doesn't work with virtual inheritance
-    struct SharedFromThisVBase : std::enable_shared_from_this<SharedFromThisVBase> {
-        SharedFromThisVBase() = default;
-        SharedFromThisVBase(const SharedFromThisVBase &) = default;
-        virtual ~SharedFromThisVBase() = default;
-    };
-    struct SharedFromThisVirt : virtual SharedFromThisVBase {};
     static std::shared_ptr<SharedFromThisVirt> sft(new SharedFromThisVirt());
     py::class_<SharedFromThisVirt, std::shared_ptr<SharedFromThisVirt>>(m, "SharedFromThisVirt")
         .def_static("get", []() { return sft.get(); });
 
     // test_move_only_holder
-    struct C {
-        C() { print_created(this); }
-        ~C() { print_destroyed(this); }
-    };
     py::class_<C, custom_unique_ptr<C>>(m, "TypeWithMoveOnlyHolder")
         .def_static("make", []() { return custom_unique_ptr<C>(new C); })
         .def_static("make_as_object", []() { return py::cast(custom_unique_ptr<C>(new C)); });
 
     // test_holder_with_addressof_operator
-    struct TypeForHolderWithAddressOf {
-        TypeForHolderWithAddressOf() { print_created(this); }
-        TypeForHolderWithAddressOf(const TypeForHolderWithAddressOf &) { print_copy_created(this); }
-        TypeForHolderWithAddressOf(TypeForHolderWithAddressOf &&) { print_move_created(this); }
-        ~TypeForHolderWithAddressOf() { print_destroyed(this); }
-        std::string toString() const {
-            return "TypeForHolderWithAddressOf[" + std::to_string(value) + "]";
-        }
-        int value = 42;
-    };
     using HolderWithAddressOf = shared_ptr_with_addressof_operator<TypeForHolderWithAddressOf>;
     py::class_<TypeForHolderWithAddressOf, HolderWithAddressOf>(m, "TypeForHolderWithAddressOf")
         .def_static("make", []() { return HolderWithAddressOf(new TypeForHolderWithAddressOf); })
         .def("get", [](const HolderWithAddressOf &self) { return self.get(); })
-        .def("print_object_1", [](const TypeForHolderWithAddressOf *obj) { py::print(obj->toString()); })
+        .def("print_object_1",
+             [](const TypeForHolderWithAddressOf *obj) { py::print(obj->toString()); })
+        // NOLINTNEXTLINE(performance-unnecessary-value-param)
         .def("print_object_2", [](HolderWithAddressOf obj) { py::print(obj.get()->toString()); })
-        .def("print_object_3", [](const HolderWithAddressOf &obj) { py::print(obj.get()->toString()); })
-        .def("print_object_4", [](const HolderWithAddressOf *obj) { py::print((*obj).get()->toString()); });
+        .def("print_object_3",
+             [](const HolderWithAddressOf &obj) { py::print(obj.get()->toString()); })
+        .def("print_object_4",
+             [](const HolderWithAddressOf *obj) { py::print((*obj).get()->toString()); });
 
     // test_move_only_holder_with_addressof_operator
-    struct TypeForMoveOnlyHolderWithAddressOf {
-        TypeForMoveOnlyHolderWithAddressOf(int value) : value{value} { print_created(this); }
-        ~TypeForMoveOnlyHolderWithAddressOf() { print_destroyed(this); }
-        std::string toString() const {
-            return "MoveOnlyHolderWithAddressOf[" + std::to_string(value) + "]";
-        }
-        int value;
-    };
-    using MoveOnlyHolderWithAddressOf = unique_ptr_with_addressof_operator<TypeForMoveOnlyHolderWithAddressOf>;
-    py::class_<TypeForMoveOnlyHolderWithAddressOf, MoveOnlyHolderWithAddressOf>(m, "TypeForMoveOnlyHolderWithAddressOf")
-        .def_static("make", []() { return MoveOnlyHolderWithAddressOf(new TypeForMoveOnlyHolderWithAddressOf(0)); })
+    using MoveOnlyHolderWithAddressOf
+        = unique_ptr_with_addressof_operator<TypeForMoveOnlyHolderWithAddressOf>;
+    py::class_<TypeForMoveOnlyHolderWithAddressOf, MoveOnlyHolderWithAddressOf>(
+        m, "TypeForMoveOnlyHolderWithAddressOf")
+        .def_static("make",
+                    []() {
+                        return MoveOnlyHolderWithAddressOf(
+                            new TypeForMoveOnlyHolderWithAddressOf(0));
+                    })
         .def_readwrite("value", &TypeForMoveOnlyHolderWithAddressOf::value)
-        .def("print_object", [](const TypeForMoveOnlyHolderWithAddressOf *obj) { py::print(obj->toString()); });
+        .def("print_object",
+             [](const TypeForMoveOnlyHolderWithAddressOf *obj) { py::print(obj->toString()); });
 
     // test_smart_ptr_from_default
-    struct HeldByDefaultHolder { };
-    py::class_<HeldByDefaultHolder>(m, "HeldByDefaultHolder")
+    py::class_<HeldByDefaultHolder, std::unique_ptr<HeldByDefaultHolder>>(m, "HeldByDefaultHolder")
         .def(py::init<>())
+        // NOLINTNEXTLINE(performance-unnecessary-value-param)
         .def_static("load_shared_ptr", [](std::shared_ptr<HeldByDefaultHolder>) {});
 
     // test_shared_ptr_gc
     // #187: issue involving std::shared_ptr<> return value policy & garbage collection
-    struct ElementBase {
-        virtual ~ElementBase() = default; /* Force creation of virtual table */
-        ElementBase() = default;
-        ElementBase(const ElementBase&) = delete;
-    };
     py::class_<ElementBase, std::shared_ptr<ElementBase>>(m, "ElementBase");
 
-    struct ElementA : ElementBase {
-        ElementA(int v) : v(v) { }
-        int value() { return v; }
-        int v;
-    };
     py::class_<ElementA, ElementBase, std::shared_ptr<ElementA>>(m, "ElementA")
         .def(py::init<int>())
         .def("value", &ElementA::value);
 
-    struct ElementList {
-        void add(std::shared_ptr<ElementBase> e) { l.push_back(e); }
-        std::vector<std::shared_ptr<ElementBase>> l;
-    };
     py::class_<ElementList, std::shared_ptr<ElementList>>(m, "ElementList")
         .def(py::init<>())
         .def("add", &ElementList::add)
         .def("get", [](ElementList &el) {
             py::list list;
-            for (auto &e : el.l)
+            for (auto &e : el.l) {
                 list.append(py::cast(e));
+            }
             return list;
         });
 }
diff --git a/3rdparty/pybind11/tests/test_smart_ptr.py b/3rdparty/pybind11/tests/test_smart_ptr.py
index c55bffba07..2f204e01b1 100644
--- a/3rdparty/pybind11/tests/test_smart_ptr.py
+++ b/3rdparty/pybind11/tests/test_smart_ptr.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 m = pytest.importorskip("pybind11_tests.smart_ptr")
@@ -16,7 +15,7 @@ def test_smart_ptr(capture):
             m.print_object_2(o)
             m.print_object_3(o)
             m.print_object_4(o)
-        assert capture == "MyObject1[{i}]\n".format(i=i) * 4
+        assert capture == f"MyObject1[{i}]\n" * 4
 
     for i, o in enumerate(
         [m.make_myobject1_1(), m.make_myobject1_2(), m.MyObject1(6), 7], start=4
@@ -34,13 +33,11 @@ def test_smart_ptr(capture):
             m.print_myobject1_4(o)
 
         times = 4 if isinstance(o, int) else 8
-        assert capture == "MyObject1[{i}]\n".format(i=i) * times
+        assert capture == f"MyObject1[{i}]\n" * times
 
     cstats = ConstructorStats.get(m.MyObject1)
     assert cstats.alive() == 0
-    expected_values = ["MyObject1[{}]".format(i) for i in range(1, 7)] + [
-        "MyObject1[7]"
-    ] * 4
+    expected_values = [f"MyObject1[{i}]" for i in range(1, 7)] + ["MyObject1[7]"] * 4
     assert cstats.values() == expected_values
     assert cstats.default_constructions == 0
     assert cstats.copy_constructions == 0
@@ -58,7 +55,7 @@ def test_smart_ptr(capture):
             m.print_myobject2_2(o)
             m.print_myobject2_3(o)
             m.print_myobject2_4(o)
-        assert capture == "MyObject2[{i}]\n".format(i=i) * 4
+        assert capture == f"MyObject2[{i}]\n" * 4
 
     cstats = ConstructorStats.get(m.MyObject2)
     assert cstats.alive() == 1
@@ -81,7 +78,7 @@ def test_smart_ptr(capture):
             m.print_myobject3_2(o)
             m.print_myobject3_3(o)
             m.print_myobject3_4(o)
-        assert capture == "MyObject3[{i}]\n".format(i=i) * 4
+        assert capture == f"MyObject3[{i}]\n" * 4
 
     cstats = ConstructorStats.get(m.MyObject3)
     assert cstats.alive() == 1
@@ -125,7 +122,9 @@ def test_unique_nodelete():
     cstats = ConstructorStats.get(m.MyObject4)
     assert cstats.alive() == 1
     del o
-    assert cstats.alive() == 1  # Leak, but that's intentional
+    assert cstats.alive() == 1
+    m.MyObject4.cleanup_all_instances()
+    assert cstats.alive() == 0
 
 
 def test_unique_nodelete4a():
@@ -134,19 +133,25 @@ def test_unique_nodelete4a():
     cstats = ConstructorStats.get(m.MyObject4a)
     assert cstats.alive() == 1
     del o
-    assert cstats.alive() == 1  # Leak, but that's intentional
+    assert cstats.alive() == 1
+    m.MyObject4a.cleanup_all_instances()
+    assert cstats.alive() == 0
 
 
 def test_unique_deleter():
+    m.MyObject4a(0)
     o = m.MyObject4b(23)
     assert o.value == 23
     cstats4a = ConstructorStats.get(m.MyObject4a)
-    assert cstats4a.alive() == 2  # Two because of previous test
+    assert cstats4a.alive() == 2
     cstats4b = ConstructorStats.get(m.MyObject4b)
     assert cstats4b.alive() == 1
     del o
-    assert cstats4a.alive() == 1  # Should now only be one leftover from previous test
+    assert cstats4a.alive() == 1  # Should now only be one leftover
     assert cstats4b.alive() == 0  # Should be deleted
+    m.MyObject4a.cleanup_all_instances()
+    assert cstats4a.alive() == 0
+    assert cstats4b.alive() == 0
 
 
 def test_large_holder():
diff --git a/3rdparty/pybind11/tests/test_stl.cpp b/3rdparty/pybind11/tests/test_stl.cpp
index 0590162770..d45465d681 100644
--- a/3rdparty/pybind11/tests/test_stl.cpp
+++ b/3rdparty/pybind11/tests/test_stl.cpp
@@ -7,22 +7,44 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/stl.h>
 
-#include <vector>
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
+#ifndef PYBIND11_HAS_FILESYSTEM_IS_OPTIONAL
+#    define PYBIND11_HAS_FILESYSTEM_IS_OPTIONAL
+#endif
+#include <pybind11/stl/filesystem.h>
+
 #include <string>
+#include <vector>
+
+#if defined(PYBIND11_TEST_BOOST)
+#    include <boost/optional.hpp>
+
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <typename T>
+struct type_caster<boost::optional<T>> : optional_caster<boost::optional<T>> {};
+
+template <>
+struct type_caster<boost::none_t> : void_caster<boost::none_t> {};
+} // namespace detail
+} // namespace PYBIND11_NAMESPACE
+#endif
 
 // Test with `std::variant` in C++17 mode, or with `boost::variant` in C++11/14
 #if defined(PYBIND11_HAS_VARIANT)
 using std::variant;
-#elif defined(PYBIND11_TEST_BOOST) && (!defined(_MSC_VER) || _MSC_VER >= 1910)
-#  include <boost/variant.hpp>
-#  define PYBIND11_HAS_VARIANT 1
+#    define PYBIND11_TEST_VARIANT 1
+#elif defined(PYBIND11_TEST_BOOST)
+#    include <boost/variant.hpp>
+#    define PYBIND11_TEST_VARIANT 1
 using boost::variant;
 
-namespace pybind11 { namespace detail {
+namespace PYBIND11_NAMESPACE {
+namespace detail {
 template <typename... Ts>
 struct type_caster<boost::variant<Ts...>> : variant_caster<boost::variant<Ts...>> {};
 
@@ -33,33 +55,117 @@ struct visit_helper<boost::variant> {
         return boost::apply_visitor(args...);
     }
 };
-}} // namespace pybind11::detail
+} // namespace detail
+} // namespace PYBIND11_NAMESPACE
 #endif
 
 PYBIND11_MAKE_OPAQUE(std::vector<std::string, std::allocator<std::string>>);
 
 /// Issue #528: templated constructor
 struct TplCtorClass {
-    template <typename T> TplCtorClass(const T &) { }
+    template <typename T>
+    explicit TplCtorClass(const T &) {}
     bool operator==(const TplCtorClass &) const { return true; }
 };
 
 namespace std {
-    template <>
-    struct hash<TplCtorClass> { size_t operator()(const TplCtorClass &) const { return 0; } };
+template <>
+struct hash<TplCtorClass> {
+    size_t operator()(const TplCtorClass &) const { return 0; }
+};
 } // namespace std
 
-
 template <template <typename> class OptionalImpl, typename T>
-struct OptionalHolder
-{
-    OptionalHolder() = default;
-    bool member_initialized() const {
-        return member && member->initialized;
-    }
+struct OptionalHolder {
+    // NOLINTNEXTLINE(modernize-use-equals-default): breaks GCC 4.8
+    OptionalHolder(){};
+    bool member_initialized() const { return member && member->initialized; }
     OptionalImpl<T> member = T{};
 };
 
+enum class EnumType {
+    kSet = 42,
+    kUnset = 85,
+};
+
+// This is used to test that return-by-ref and return-by-copy policies are
+// handled properly for optional types. This is a regression test for a dangling
+// reference issue. The issue seemed to require the enum value type to
+// reproduce - it didn't seem to happen if the value type is just an integer.
+template <template <typename> class OptionalImpl>
+class OptionalProperties {
+public:
+    using OptionalEnumValue = OptionalImpl<EnumType>;
+
+    OptionalProperties() : value(EnumType::kSet) {}
+    ~OptionalProperties() {
+        // Reset value to detect use-after-destruction.
+        // This is set to a specific value rather than nullopt to ensure that
+        // the memory that contains the value gets re-written.
+        value = EnumType::kUnset;
+    }
+
+    OptionalEnumValue &access_by_ref() { return value; }
+    OptionalEnumValue access_by_copy() { return value; }
+
+private:
+    OptionalEnumValue value;
+};
+
+// This type mimics aspects of boost::optional from old versions of Boost,
+// which exposed a dangling reference bug in Pybind11. Recent versions of
+// boost::optional, as well as libstdc++'s std::optional, don't seem to be
+// affected by the same issue. This is meant to be a minimal implementation
+// required to reproduce the issue, not fully standard-compliant.
+// See issue #3330 for more details.
+template <typename T>
+class ReferenceSensitiveOptional {
+public:
+    using value_type = T;
+
+    ReferenceSensitiveOptional() = default;
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    ReferenceSensitiveOptional(const T &value) : storage{value} {}
+    // NOLINTNEXTLINE(google-explicit-constructor)
+    ReferenceSensitiveOptional(T &&value) : storage{std::move(value)} {}
+    ReferenceSensitiveOptional &operator=(const T &value) {
+        storage = {value};
+        return *this;
+    }
+    ReferenceSensitiveOptional &operator=(T &&value) {
+        storage = {std::move(value)};
+        return *this;
+    }
+
+    template <typename... Args>
+    T &emplace(Args &&...args) {
+        storage.clear();
+        storage.emplace_back(std::forward<Args>(args)...);
+        return storage.back();
+    }
+
+    const T &value() const noexcept {
+        assert(!storage.empty());
+        return storage[0];
+    }
+
+    const T &operator*() const noexcept { return value(); }
+
+    const T *operator->() const noexcept { return &value(); }
+
+    explicit operator bool() const noexcept { return !storage.empty(); }
+
+private:
+    std::vector<T> storage;
+};
+
+namespace PYBIND11_NAMESPACE {
+namespace detail {
+template <typename T>
+struct type_caster<ReferenceSensitiveOptional<T>>
+    : optional_caster<ReferenceSensitiveOptional<T>> {};
+} // namespace detail
+} // namespace PYBIND11_NAMESPACE
 
 TEST_SUBMODULE(stl, m) {
     // test_vector
@@ -67,24 +173,29 @@ TEST_SUBMODULE(stl, m) {
     m.def("load_vector", [](const std::vector<int> &v) { return v.at(0) == 1 && v.at(1) == 2; });
     // `std::vector<bool>` is special because it returns proxy objects instead of references
     m.def("cast_bool_vector", []() { return std::vector<bool>{true, false}; });
-    m.def("load_bool_vector", [](const std::vector<bool> &v) {
-        return v.at(0) == true && v.at(1) == false;
-    });
+    m.def("load_bool_vector",
+          [](const std::vector<bool> &v) { return v.at(0) == true && v.at(1) == false; });
     // Unnumbered regression (caused by #936): pointers to stl containers aren't castable
-    static std::vector<RValueCaster> lvv{2};
-    m.def("cast_ptr_vector", []() { return &lvv; });
+    m.def(
+        "cast_ptr_vector",
+        []() {
+            // Using no-destructor idiom to side-step warnings from overzealous compilers.
+            static auto *v = new std::vector<RValueCaster>{2};
+            return v;
+        },
+        py::return_value_policy::reference);
 
     // test_deque
     m.def("cast_deque", []() { return std::deque<int>{1}; });
     m.def("load_deque", [](const std::deque<int> &v) { return v.at(0) == 1 && v.at(1) == 2; });
 
     // test_array
-    m.def("cast_array", []() { return std::array<int, 2> {{1 , 2}}; });
+    m.def("cast_array", []() { return std::array<int, 2>{{1, 2}}; });
     m.def("load_array", [](const std::array<int, 2> &a) { return a[0] == 1 && a[1] == 2; });
 
     // test_valarray
     m.def("cast_valarray", []() { return std::valarray<int>{1, 4, 9}; });
-    m.def("load_valarray", [](const std::valarray<int>& v) {
+    m.def("load_valarray", [](const std::valarray<int> &v) {
         return v.size() == 3 && v[0] == 1 && v[1] == 4 && v[2] == 9;
     });
 
@@ -97,7 +208,7 @@ TEST_SUBMODULE(stl, m) {
     // test_set
     m.def("cast_set", []() { return std::set<std::string>{"key1", "key2"}; });
     m.def("load_set", [](const std::set<std::string> &set) {
-        return set.count("key1") && set.count("key2") && set.count("key3");
+        return (set.count("key1") != 0u) && (set.count("key2") != 0u) && (set.count("key3") != 0u);
     });
 
     // test_recursive_casting
@@ -106,10 +217,12 @@ TEST_SUBMODULE(stl, m) {
     // NB: map and set keys are `const`, so while we technically do move them (as `const Type &&`),
     // casters don't typically do anything with that, which means they fall to the `const Type &`
     // caster.
-    m.def("cast_rv_map", []() { return std::unordered_map<std::string, RValueCaster>{{"a", RValueCaster{}}}; });
+    m.def("cast_rv_map", []() {
+        return std::unordered_map<std::string, RValueCaster>{{"a", RValueCaster{}}};
+    });
     m.def("cast_rv_nested", []() {
         std::vector<std::array<std::list<std::unordered_map<std::string, RValueCaster>>, 2>> v;
-        v.emplace_back(); // add an array
+        v.emplace_back();           // add an array
         v.back()[0].emplace_back(); // add a map to the array
         v.back()[0].back().emplace("b", RValueCaster{});
         v.back()[0].back().emplace("c", RValueCaster{});
@@ -118,15 +231,18 @@ TEST_SUBMODULE(stl, m) {
         return v;
     });
     static std::array<RValueCaster, 2> lva;
-    static std::unordered_map<std::string, RValueCaster> lvm{{"a", RValueCaster{}}, {"b", RValueCaster{}}};
-    static std::unordered_map<std::string, std::vector<std::list<std::array<RValueCaster, 2>>>> lvn;
-    lvn["a"].emplace_back(); // add a list
+    static std::unordered_map<std::string, RValueCaster> lvm{{"a", RValueCaster{}},
+                                                             {"b", RValueCaster{}}};
+    static std::unordered_map<std::string, std::vector<std::list<std::array<RValueCaster, 2>>>>
+        lvn;
+    lvn["a"].emplace_back();        // add a list
     lvn["a"].back().emplace_back(); // add an array
-    lvn["a"].emplace_back(); // another list
+    lvn["a"].emplace_back();        // another list
     lvn["a"].back().emplace_back(); // add an array
-    lvn["b"].emplace_back(); // add a list
+    lvn["b"].emplace_back();        // add a list
     lvn["b"].back().emplace_back(); // add an array
     lvn["b"].back().emplace_back(); // add another array
+    static std::vector<RValueCaster> lvv{2};
     m.def("cast_lv_vector", []() -> const decltype(lvv) & { return lvv; });
     m.def("cast_lv_array", []() -> const decltype(lva) & { return lva; });
     m.def("cast_lv_map", []() -> const decltype(lvm) & { return lvm; });
@@ -139,9 +255,15 @@ TEST_SUBMODULE(stl, m) {
         return v;
     });
 
+    pybind11::enum_<EnumType>(m, "EnumType")
+        .value("kSet", EnumType::kSet)
+        .value("kUnset", EnumType::kUnset);
+
     // test_move_out_container
     struct MoveOutContainer {
-        struct Value { int value; };
+        struct Value {
+            int value;
+        };
         std::list<Value> move_list() const { return {{0}, {1}, {2}}; }
     };
     py::class_<MoveOutContainer::Value>(m, "MoveOutContainerValue")
@@ -154,7 +276,7 @@ TEST_SUBMODULE(stl, m) {
     struct NoAssign {
         int value;
 
-        explicit NoAssign(int value = 0) : value(value) { }
+        explicit NoAssign(int value = 0) : value(value) {}
         NoAssign(const NoAssign &) = default;
         NoAssign(NoAssign &&) = default;
 
@@ -165,13 +287,10 @@ TEST_SUBMODULE(stl, m) {
         .def(py::init<>())
         .def(py::init<int>());
 
-
-    struct MoveOutDetector
-    {
+    struct MoveOutDetector {
         MoveOutDetector() = default;
-        MoveOutDetector(const MoveOutDetector&) = default;
-        MoveOutDetector(MoveOutDetector&& other) noexcept
-         : initialized(other.initialized) {
+        MoveOutDetector(const MoveOutDetector &) = default;
+        MoveOutDetector(MoveOutDetector &&other) noexcept : initialized(other.initialized) {
             // steal underlying resource
             other.initialized = false;
         }
@@ -181,34 +300,37 @@ TEST_SUBMODULE(stl, m) {
         .def(py::init<>())
         .def_readonly("initialized", &MoveOutDetector::initialized);
 
-
 #ifdef PYBIND11_HAS_OPTIONAL
     // test_optional
     m.attr("has_optional") = true;
 
     using opt_int = std::optional<int>;
     using opt_no_assign = std::optional<NoAssign>;
-    m.def("double_or_zero", [](const opt_int& x) -> int {
-        return x.value_or(0) * 2;
-    });
-    m.def("half_or_none", [](int x) -> opt_int {
-        return x ? opt_int(x / 2) : opt_int();
-    });
-    m.def("test_nullopt", [](opt_int x) {
-        return x.value_or(42);
-    }, py::arg_v("x", std::nullopt, "None"));
-    m.def("test_no_assign", [](const opt_no_assign &x) {
-        return x ? x->value : 42;
-    }, py::arg_v("x", std::nullopt, "None"));
+    m.def("double_or_zero", [](const opt_int &x) -> int { return x.value_or(0) * 2; });
+    m.def("half_or_none", [](int x) -> opt_int { return x != 0 ? opt_int(x / 2) : opt_int(); });
+    m.def(
+        "test_nullopt",
+        [](opt_int x) { return x.value_or(42); },
+        py::arg_v("x", std::nullopt, "None"));
+    m.def(
+        "test_no_assign",
+        [](const opt_no_assign &x) { return x ? x->value : 42; },
+        py::arg_v("x", std::nullopt, "None"));
 
     m.def("nodefer_none_optional", [](std::optional<int>) { return true; });
-    m.def("nodefer_none_optional", [](py::none) { return false; });
+    m.def("nodefer_none_optional", [](const py::none &) { return false; });
 
     using opt_holder = OptionalHolder<std::optional, MoveOutDetector>;
     py::class_<opt_holder>(m, "OptionalHolder", "Class with optional member")
         .def(py::init<>())
         .def_readonly("member", &opt_holder::member)
         .def("member_initialized", &opt_holder::member_initialized);
+
+    using opt_props = OptionalProperties<std::optional>;
+    pybind11::class_<opt_props>(m, "OptionalProperties")
+        .def(pybind11::init<>())
+        .def_property_readonly("access_by_ref", &opt_props::access_by_ref)
+        .def_property_readonly("access_by_copy", &opt_props::access_by_copy);
 #endif
 
 #ifdef PYBIND11_HAS_EXP_OPTIONAL
@@ -217,27 +339,100 @@ TEST_SUBMODULE(stl, m) {
 
     using exp_opt_int = std::experimental::optional<int>;
     using exp_opt_no_assign = std::experimental::optional<NoAssign>;
-    m.def("double_or_zero_exp", [](const exp_opt_int& x) -> int {
-        return x.value_or(0) * 2;
-    });
-    m.def("half_or_none_exp", [](int x) -> exp_opt_int {
-        return x ? exp_opt_int(x / 2) : exp_opt_int();
-    });
-    m.def("test_nullopt_exp", [](exp_opt_int x) {
-        return x.value_or(42);
-    }, py::arg_v("x", std::experimental::nullopt, "None"));
-    m.def("test_no_assign_exp", [](const exp_opt_no_assign &x) {
-        return x ? x->value : 42;
-    }, py::arg_v("x", std::experimental::nullopt, "None"));
+    m.def("double_or_zero_exp", [](const exp_opt_int &x) -> int { return x.value_or(0) * 2; });
+    m.def("half_or_none_exp",
+          [](int x) -> exp_opt_int { return x ? exp_opt_int(x / 2) : exp_opt_int(); });
+    m.def(
+        "test_nullopt_exp",
+        [](exp_opt_int x) { return x.value_or(42); },
+        py::arg_v("x", std::experimental::nullopt, "None"));
+    m.def(
+        "test_no_assign_exp",
+        [](const exp_opt_no_assign &x) { return x ? x->value : 42; },
+        py::arg_v("x", std::experimental::nullopt, "None"));
 
     using opt_exp_holder = OptionalHolder<std::experimental::optional, MoveOutDetector>;
     py::class_<opt_exp_holder>(m, "OptionalExpHolder", "Class with optional member")
         .def(py::init<>())
         .def_readonly("member", &opt_exp_holder::member)
         .def("member_initialized", &opt_exp_holder::member_initialized);
+
+    using opt_exp_props = OptionalProperties<std::experimental::optional>;
+    pybind11::class_<opt_exp_props>(m, "OptionalExpProperties")
+        .def(pybind11::init<>())
+        .def_property_readonly("access_by_ref", &opt_exp_props::access_by_ref)
+        .def_property_readonly("access_by_copy", &opt_exp_props::access_by_copy);
+#endif
+
+#if defined(PYBIND11_TEST_BOOST)
+    // test_boost_optional
+    m.attr("has_boost_optional") = true;
+
+    using boost_opt_int = boost::optional<int>;
+    using boost_opt_no_assign = boost::optional<NoAssign>;
+    m.def("double_or_zero_boost", [](const boost_opt_int &x) -> int { return x.value_or(0) * 2; });
+    m.def("half_or_none_boost",
+          [](int x) -> boost_opt_int { return x != 0 ? boost_opt_int(x / 2) : boost_opt_int(); });
+    m.def(
+        "test_nullopt_boost",
+        [](boost_opt_int x) { return x.value_or(42); },
+        py::arg_v("x", boost::none, "None"));
+    m.def(
+        "test_no_assign_boost",
+        [](const boost_opt_no_assign &x) { return x ? x->value : 42; },
+        py::arg_v("x", boost::none, "None"));
+
+    using opt_boost_holder = OptionalHolder<boost::optional, MoveOutDetector>;
+    py::class_<opt_boost_holder>(m, "OptionalBoostHolder", "Class with optional member")
+        .def(py::init<>())
+        .def_readonly("member", &opt_boost_holder::member)
+        .def("member_initialized", &opt_boost_holder::member_initialized);
+
+    using opt_boost_props = OptionalProperties<boost::optional>;
+    pybind11::class_<opt_boost_props>(m, "OptionalBoostProperties")
+        .def(pybind11::init<>())
+        .def_property_readonly("access_by_ref", &opt_boost_props::access_by_ref)
+        .def_property_readonly("access_by_copy", &opt_boost_props::access_by_copy);
+#endif
+
+    // test_refsensitive_optional
+    using refsensitive_opt_int = ReferenceSensitiveOptional<int>;
+    using refsensitive_opt_no_assign = ReferenceSensitiveOptional<NoAssign>;
+    m.def("double_or_zero_refsensitive",
+          [](const refsensitive_opt_int &x) -> int { return (x ? x.value() : 0) * 2; });
+    m.def("half_or_none_refsensitive", [](int x) -> refsensitive_opt_int {
+        return x != 0 ? refsensitive_opt_int(x / 2) : refsensitive_opt_int();
+    });
+    m.def(
+        "test_nullopt_refsensitive",
+        // NOLINTNEXTLINE(performance-unnecessary-value-param)
+        [](refsensitive_opt_int x) { return x ? x.value() : 42; },
+        py::arg_v("x", refsensitive_opt_int(), "None"));
+    m.def(
+        "test_no_assign_refsensitive",
+        [](const refsensitive_opt_no_assign &x) { return x ? x->value : 42; },
+        py::arg_v("x", refsensitive_opt_no_assign(), "None"));
+
+    using opt_refsensitive_holder = OptionalHolder<ReferenceSensitiveOptional, MoveOutDetector>;
+    py::class_<opt_refsensitive_holder>(
+        m, "OptionalRefSensitiveHolder", "Class with optional member")
+        .def(py::init<>())
+        .def_readonly("member", &opt_refsensitive_holder::member)
+        .def("member_initialized", &opt_refsensitive_holder::member_initialized);
+
+    using opt_refsensitive_props = OptionalProperties<ReferenceSensitiveOptional>;
+    pybind11::class_<opt_refsensitive_props>(m, "OptionalRefSensitiveProperties")
+        .def(pybind11::init<>())
+        .def_property_readonly("access_by_ref", &opt_refsensitive_props::access_by_ref)
+        .def_property_readonly("access_by_copy", &opt_refsensitive_props::access_by_copy);
+
+#ifdef PYBIND11_HAS_FILESYSTEM
+    // test_fs_path
+    m.attr("has_filesystem") = true;
+    m.def("parent_path", [](const std::filesystem::path &p) { return p.parent_path(); });
 #endif
 
-#ifdef PYBIND11_HAS_VARIANT
+#ifdef PYBIND11_TEST_VARIANT
     static_assert(std::is_same<py::detail::variant_caster_visitor::result_type, py::handle>::value,
                   "visitor::result_type is required by boost::variant in C++11 mode");
 
@@ -245,13 +440,16 @@ TEST_SUBMODULE(stl, m) {
         using result_type = const char *;
 
         result_type operator()(int) { return "int"; }
-        result_type operator()(std::string) { return "std::string"; }
+        result_type operator()(const std::string &) { return "std::string"; }
         result_type operator()(double) { return "double"; }
         result_type operator()(std::nullptr_t) { return "std::nullptr_t"; }
+#    if defined(PYBIND11_HAS_VARIANT)
+        result_type operator()(std::monostate) { return "std::monostate"; }
+#    endif
     };
 
     // test_variant
-    m.def("load_variant", [](variant<int, std::string, double, std::nullptr_t> v) {
+    m.def("load_variant", [](const variant<int, std::string, double, std::nullptr_t> &v) {
         return py::detail::visit_helper<variant>::call(visitor(), v);
     });
     m.def("load_variant_2pass", [](variant<double, int> v) {
@@ -261,6 +459,18 @@ TEST_SUBMODULE(stl, m) {
         using V = variant<int, std::string>;
         return py::make_tuple(V(5), V("Hello"));
     });
+
+#    if defined(PYBIND11_HAS_VARIANT)
+    // std::monostate tests.
+    m.def("load_monostate_variant",
+          [](const variant<std::monostate, int, std::string> &v) -> const char * {
+              return py::detail::visit_helper<variant>::call(visitor(), v);
+          });
+    m.def("cast_monostate_variant", []() {
+        using V = variant<std::monostate, int, std::string>;
+        return py::make_tuple(V{}, V(5), V("Hello"));
+    });
+#    endif
 #endif
 
     // #528: templated constructor
@@ -270,26 +480,32 @@ TEST_SUBMODULE(stl, m) {
     m.def("tpl_ctor_set", [](std::unordered_set<TplCtorClass> &) {});
 #if defined(PYBIND11_HAS_OPTIONAL)
     m.def("tpl_constr_optional", [](std::optional<TplCtorClass> &) {});
-#elif defined(PYBIND11_HAS_EXP_OPTIONAL)
-    m.def("tpl_constr_optional", [](std::experimental::optional<TplCtorClass> &) {});
+#endif
+#if defined(PYBIND11_HAS_EXP_OPTIONAL)
+    m.def("tpl_constr_optional_exp", [](std::experimental::optional<TplCtorClass> &) {});
+#endif
+#if defined(PYBIND11_TEST_BOOST)
+    m.def("tpl_constr_optional_boost", [](boost::optional<TplCtorClass> &) {});
 #endif
 
     // test_vec_of_reference_wrapper
     // #171: Can't return STL structures containing reference wrapper
     m.def("return_vec_of_reference_wrapper", [](std::reference_wrapper<UserType> p4) {
         static UserType p1{1}, p2{2}, p3{3};
-        return std::vector<std::reference_wrapper<UserType>> {
-            std::ref(p1), std::ref(p2), std::ref(p3), p4
-        };
+        return std::vector<std::reference_wrapper<UserType>>{
+            std::ref(p1), std::ref(p2), std::ref(p3), p4};
     });
 
     // test_stl_pass_by_pointer
-    m.def("stl_pass_by_pointer", [](std::vector<int>* v) { return *v; }, "v"_a=nullptr);
+    m.def(
+        "stl_pass_by_pointer", [](std::vector<int> *v) { return *v; }, "v"_a = nullptr);
 
     // #1258: pybind11/stl.h converts string to vector<string>
-    m.def("func_with_string_or_vector_string_arg_overload", [](std::vector<std::string>) { return 1; });
-    m.def("func_with_string_or_vector_string_arg_overload", [](std::list<std::string>) { return 2; });
-    m.def("func_with_string_or_vector_string_arg_overload", [](std::string) { return 3; });
+    m.def("func_with_string_or_vector_string_arg_overload",
+          [](const std::vector<std::string> &) { return 1; });
+    m.def("func_with_string_or_vector_string_arg_overload",
+          [](const std::list<std::string> &) { return 2; });
+    m.def("func_with_string_or_vector_string_arg_overload", [](const std::string &) { return 3; });
 
     class Placeholder {
     public:
@@ -300,19 +516,24 @@ TEST_SUBMODULE(stl, m) {
     py::class_<Placeholder>(m, "Placeholder");
 
     /// test_stl_vector_ownership
-    m.def("test_stl_ownership",
-          []() {
-              std::vector<Placeholder *> result;
-              result.push_back(new Placeholder());
-              return result;
-          },
-          py::return_value_policy::take_ownership);
+    m.def(
+        "test_stl_ownership",
+        []() {
+            std::vector<Placeholder *> result;
+            result.push_back(new Placeholder());
+            return result;
+        },
+        py::return_value_policy::take_ownership);
 
     m.def("array_cast_sequence", [](std::array<int, 3> x) { return x; });
 
     /// test_issue_1561
-    struct Issue1561Inner { std::string data; };
-    struct Issue1561Outer { std::vector<Issue1561Inner> list; };
+    struct Issue1561Inner {
+        std::string data;
+    };
+    struct Issue1561Outer {
+        std::vector<Issue1561Inner> list;
+    };
 
     py::class_<Issue1561Inner>(m, "Issue1561Inner")
         .def(py::init<std::string>())
@@ -321,4 +542,10 @@ TEST_SUBMODULE(stl, m) {
     py::class_<Issue1561Outer>(m, "Issue1561Outer")
         .def(py::init<>())
         .def_readwrite("list", &Issue1561Outer::list);
+
+    m.def(
+        "return_vector_bool_raw_ptr",
+        []() { return new std::vector<bool>(4513); },
+        // Without explicitly specifying `take_ownership`, this function leaks.
+        py::return_value_policy::take_ownership);
 }
diff --git a/3rdparty/pybind11/tests/test_stl.py b/3rdparty/pybind11/tests/test_stl.py
index 330017544d..d30c382113 100644
--- a/3rdparty/pybind11/tests/test_stl.py
+++ b/3rdparty/pybind11/tests/test_stl.py
@@ -1,9 +1,7 @@
-# -*- coding: utf-8 -*-
 import pytest
 
+from pybind11_tests import ConstructorStats, UserType
 from pybind11_tests import stl as m
-from pybind11_tests import UserType
-from pybind11_tests import ConstructorStats
 
 
 def test_vector(doc):
@@ -16,6 +14,7 @@ def test_vector(doc):
 
     assert m.cast_bool_vector() == [True, False]
     assert m.load_bool_vector([True, False])
+    assert m.load_bool_vector(tuple([True, False]))
 
     assert doc(m.cast_vector) == "cast_vector() -> List[int]"
     assert doc(m.load_vector) == "load_vector(arg0: List[int]) -> bool"
@@ -38,6 +37,7 @@ def test_array(doc):
     lst = m.cast_array()
     assert lst == [1, 2]
     assert m.load_array(lst)
+    assert m.load_array(tuple(lst))
 
     assert doc(m.cast_array) == "cast_array() -> List[int[2]]"
     assert doc(m.load_array) == "load_array(arg0: List[int[2]]) -> bool"
@@ -48,6 +48,7 @@ def test_valarray(doc):
     lst = m.cast_valarray()
     assert lst == [1, 4, 9]
     assert m.load_valarray(lst)
+    assert m.load_valarray(tuple(lst))
 
     assert doc(m.cast_valarray) == "cast_valarray() -> List[int]"
     assert doc(m.load_valarray) == "load_valarray(arg0: List[int]) -> bool"
@@ -72,6 +73,7 @@ def test_set(doc):
     assert s == {"key1", "key2"}
     s.add("key3")
     assert m.load_set(s)
+    assert m.load_set(frozenset(s))
 
     assert doc(m.cast_set) == "cast_set() -> Set[str]"
     assert doc(m.load_set) == "load_set(arg0: Set[str]) -> bool"
@@ -133,6 +135,10 @@ def test_optional():
     assert mvalue.initialized
     assert holder.member_initialized()
 
+    props = m.OptionalProperties()
+    assert int(props.access_by_ref) == 42
+    assert int(props.access_by_copy) == 42
+
 
 @pytest.mark.skipif(
     not hasattr(m, "has_exp_optional"), reason="no <experimental/optional>"
@@ -161,6 +167,88 @@ def test_exp_optional():
     assert mvalue.initialized
     assert holder.member_initialized()
 
+    props = m.OptionalExpProperties()
+    assert int(props.access_by_ref) == 42
+    assert int(props.access_by_copy) == 42
+
+
+@pytest.mark.skipif(not hasattr(m, "has_boost_optional"), reason="no <boost/optional>")
+def test_boost_optional():
+    assert m.double_or_zero_boost(None) == 0
+    assert m.double_or_zero_boost(42) == 84
+    pytest.raises(TypeError, m.double_or_zero_boost, "foo")
+
+    assert m.half_or_none_boost(0) is None
+    assert m.half_or_none_boost(42) == 21
+    pytest.raises(TypeError, m.half_or_none_boost, "foo")
+
+    assert m.test_nullopt_boost() == 42
+    assert m.test_nullopt_boost(None) == 42
+    assert m.test_nullopt_boost(42) == 42
+    assert m.test_nullopt_boost(43) == 43
+
+    assert m.test_no_assign_boost() == 42
+    assert m.test_no_assign_boost(None) == 42
+    assert m.test_no_assign_boost(m.NoAssign(43)) == 43
+    pytest.raises(TypeError, m.test_no_assign_boost, 43)
+
+    holder = m.OptionalBoostHolder()
+    mvalue = holder.member
+    assert mvalue.initialized
+    assert holder.member_initialized()
+
+    props = m.OptionalBoostProperties()
+    assert int(props.access_by_ref) == 42
+    assert int(props.access_by_copy) == 42
+
+
+def test_reference_sensitive_optional():
+    assert m.double_or_zero_refsensitive(None) == 0
+    assert m.double_or_zero_refsensitive(42) == 84
+    pytest.raises(TypeError, m.double_or_zero_refsensitive, "foo")
+
+    assert m.half_or_none_refsensitive(0) is None
+    assert m.half_or_none_refsensitive(42) == 21
+    pytest.raises(TypeError, m.half_or_none_refsensitive, "foo")
+
+    assert m.test_nullopt_refsensitive() == 42
+    assert m.test_nullopt_refsensitive(None) == 42
+    assert m.test_nullopt_refsensitive(42) == 42
+    assert m.test_nullopt_refsensitive(43) == 43
+
+    assert m.test_no_assign_refsensitive() == 42
+    assert m.test_no_assign_refsensitive(None) == 42
+    assert m.test_no_assign_refsensitive(m.NoAssign(43)) == 43
+    pytest.raises(TypeError, m.test_no_assign_refsensitive, 43)
+
+    holder = m.OptionalRefSensitiveHolder()
+    mvalue = holder.member
+    assert mvalue.initialized
+    assert holder.member_initialized()
+
+    props = m.OptionalRefSensitiveProperties()
+    assert int(props.access_by_ref) == 42
+    assert int(props.access_by_copy) == 42
+
+
+@pytest.mark.skipif(not hasattr(m, "has_filesystem"), reason="no <filesystem>")
+def test_fs_path():
+    from pathlib import Path
+
+    class PseudoStrPath:
+        def __fspath__(self):
+            return "foo/bar"
+
+    class PseudoBytesPath:
+        def __fspath__(self):
+            return b"foo/bar"
+
+    assert m.parent_path(Path("foo/bar")) == Path("foo")
+    assert m.parent_path("foo/bar") == Path("foo")
+    assert m.parent_path(b"foo/bar") == Path("foo")
+    assert m.parent_path(PseudoStrPath()) == Path("foo")
+    assert m.parent_path(PseudoBytesPath()) == Path("foo")
+
 
 @pytest.mark.skipif(not hasattr(m, "load_variant"), reason="no <variant>")
 def test_variant(doc):
@@ -179,6 +267,22 @@ def test_variant(doc):
     )
 
 
+@pytest.mark.skipif(
+    not hasattr(m, "load_monostate_variant"), reason="no std::monostate"
+)
+def test_variant_monostate(doc):
+    assert m.load_monostate_variant(None) == "std::monostate"
+    assert m.load_monostate_variant(1) == "int"
+    assert m.load_monostate_variant("1") == "std::string"
+
+    assert m.cast_monostate_variant() == (None, 5, "Hello")
+
+    assert (
+        doc(m.load_monostate_variant)
+        == "load_monostate_variant(arg0: Union[None, int, str]) -> str"
+    )
+
+
 def test_vec_of_reference_wrapper():
     """#171: Can't return reference wrappers (or STL structures containing them)"""
     assert (
@@ -198,7 +302,7 @@ def test_stl_pass_by_pointer(msg):
             1. (v: List[int] = None) -> List[int]
 
         Invoked with:
-    """  # noqa: E501 line too long
+    """
     )
 
     with pytest.raises(TypeError) as excinfo:
@@ -210,7 +314,7 @@ def test_stl_pass_by_pointer(msg):
             1. (v: List[int] = None) -> List[int]
 
         Invoked with: None
-    """  # noqa: E501 line too long
+    """
     )
 
     assert m.stl_pass_by_pointer([1, 2, 3]) == [1, 2, 3]
@@ -259,8 +363,15 @@ def test_array_cast_sequence():
 
 
 def test_issue_1561():
-    """ check fix for issue #1561 """
+    """check fix for issue #1561"""
     bar = m.Issue1561Outer()
     bar.list = [m.Issue1561Inner("bar")]
     bar.list
     assert bar.list[0].data == "bar"
+
+
+def test_return_vector_bool_raw_ptr():
+    # Add `while True:` for manual leak checking.
+    v = m.return_vector_bool_raw_ptr()
+    assert isinstance(v, list)
+    assert len(v) == 4513
diff --git a/3rdparty/pybind11/tests/test_stl_binders.cpp b/3rdparty/pybind11/tests/test_stl_binders.cpp
index 1c0df984d8..ca9630bd19 100644
--- a/3rdparty/pybind11/tests/test_stl_binders.cpp
+++ b/3rdparty/pybind11/tests/test_stl_binders.cpp
@@ -7,23 +7,24 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
+#include <pybind11/numpy.h>
+#include <pybind11/stl_bind.h>
+
 #include "pybind11_tests.h"
 
-#include <pybind11/stl_bind.h>
-#include <pybind11/numpy.h>
-#include <map>
 #include <deque>
+#include <map>
 #include <unordered_map>
 
 class El {
 public:
     El() = delete;
-    El(int v) : a(v) { }
+    explicit El(int v) : a(v) {}
 
     int a;
 };
 
-std::ostream & operator<<(std::ostream &s, El const&v) {
+std::ostream &operator<<(std::ostream &s, El const &v) {
     s << "El{" << v.a << '}';
     return s;
 }
@@ -40,25 +41,32 @@ class E_nc {
     int value;
 };
 
-template <class Container> Container *one_to_n(int n) {
-    auto v = new Container();
-    for (int i = 1; i <= n; i++)
+template <class Container>
+Container *one_to_n(int n) {
+    auto *v = new Container();
+    for (int i = 1; i <= n; i++) {
         v->emplace_back(i);
+    }
     return v;
 }
 
-template <class Map> Map *times_ten(int n) {
-    auto m = new Map();
-    for (int i = 1; i <= n; i++)
-        m->emplace(int(i), E_nc(10*i));
+template <class Map>
+Map *times_ten(int n) {
+    auto *m = new Map();
+    for (int i = 1; i <= n; i++) {
+        m->emplace(int(i), E_nc(10 * i));
+    }
     return m;
 }
 
-template <class NestMap> NestMap *times_hundred(int n) {
-    auto m = new NestMap();
-    for (int i = 1; i <= n; i++)
-        for (int j = 1; j <= n; j++)
-            (*m)[i].emplace(int(j*10), E_nc(100*j));
+template <class NestMap>
+NestMap *times_hundred(int n) {
+    auto *m = new NestMap();
+    for (int i = 1; i <= n; i++) {
+        for (int j = 1; j <= n; j++) {
+            (*m)[i].emplace(int(j * 10), E_nc(100 * j));
+        }
+    }
     return m;
 }
 
@@ -67,8 +75,7 @@ TEST_SUBMODULE(stl_binders, m) {
     py::bind_vector<std::vector<unsigned int>>(m, "VectorInt", py::buffer_protocol());
 
     // test_vector_custom
-    py::class_<El>(m, "El")
-        .def(py::init<int>());
+    py::class_<El>(m, "El").def(py::init<int>());
     py::bind_vector<std::vector<El>>(m, "VectorEl");
     py::bind_vector<std::vector<std::vector<El>>>(m, "VectorVectorEl");
 
@@ -78,52 +85,68 @@ TEST_SUBMODULE(stl_binders, m) {
 
     // test_map_string_double_const
     py::bind_map<std::map<std::string, double const>>(m, "MapStringDoubleConst");
-    py::bind_map<std::unordered_map<std::string, double const>>(m, "UnorderedMapStringDoubleConst");
+    py::bind_map<std::unordered_map<std::string, double const>>(m,
+                                                                "UnorderedMapStringDoubleConst");
 
-    py::class_<E_nc>(m, "ENC")
-        .def(py::init<int>())
-        .def_readwrite("value", &E_nc::value);
+    py::class_<E_nc>(m, "ENC").def(py::init<int>()).def_readwrite("value", &E_nc::value);
 
     // test_noncopyable_containers
     py::bind_vector<std::vector<E_nc>>(m, "VectorENC");
-    m.def("get_vnc", &one_to_n<std::vector<E_nc>>, py::return_value_policy::reference);
+    m.def("get_vnc", &one_to_n<std::vector<E_nc>>);
     py::bind_vector<std::deque<E_nc>>(m, "DequeENC");
-    m.def("get_dnc", &one_to_n<std::deque<E_nc>>, py::return_value_policy::reference);
+    m.def("get_dnc", &one_to_n<std::deque<E_nc>>);
     py::bind_map<std::map<int, E_nc>>(m, "MapENC");
-    m.def("get_mnc", &times_ten<std::map<int, E_nc>>, py::return_value_policy::reference);
+    m.def("get_mnc", &times_ten<std::map<int, E_nc>>);
     py::bind_map<std::unordered_map<int, E_nc>>(m, "UmapENC");
-    m.def("get_umnc", &times_ten<std::unordered_map<int, E_nc>>, py::return_value_policy::reference);
+    m.def("get_umnc", &times_ten<std::unordered_map<int, E_nc>>);
     // Issue #1885: binding nested std::map<X, Container<E>> with E non-copyable
     py::bind_map<std::map<int, std::vector<E_nc>>>(m, "MapVecENC");
-    m.def("get_nvnc", [](int n)
-        {
-            auto m = new std::map<int, std::vector<E_nc>>();
-            for (int i = 1; i <= n; i++)
-                for (int j = 1; j <= n; j++)
-                    (*m)[i].emplace_back(j);
-            return m;
-        }, py::return_value_policy::reference);
+    m.def("get_nvnc", [](int n) {
+        auto *m = new std::map<int, std::vector<E_nc>>();
+        for (int i = 1; i <= n; i++) {
+            for (int j = 1; j <= n; j++) {
+                (*m)[i].emplace_back(j);
+            }
+        }
+        return m;
+    });
     py::bind_map<std::map<int, std::map<int, E_nc>>>(m, "MapMapENC");
-    m.def("get_nmnc", &times_hundred<std::map<int, std::map<int, E_nc>>>, py::return_value_policy::reference);
+    m.def("get_nmnc", &times_hundred<std::map<int, std::map<int, E_nc>>>);
     py::bind_map<std::unordered_map<int, std::unordered_map<int, E_nc>>>(m, "UmapUmapENC");
-    m.def("get_numnc", &times_hundred<std::unordered_map<int, std::unordered_map<int, E_nc>>>, py::return_value_policy::reference);
+    m.def("get_numnc", &times_hundred<std::unordered_map<int, std::unordered_map<int, E_nc>>>);
 
     // test_vector_buffer
     py::bind_vector<std::vector<unsigned char>>(m, "VectorUChar", py::buffer_protocol());
     // no dtype declared for this version:
-    struct VUndeclStruct { bool w; uint32_t x; double y; bool z; };
-    m.def("create_undeclstruct", [m] () mutable {
-        py::bind_vector<std::vector<VUndeclStruct>>(m, "VectorUndeclStruct", py::buffer_protocol());
+    struct VUndeclStruct {
+        bool w;
+        uint32_t x;
+        double y;
+        bool z;
+    };
+    m.def("create_undeclstruct", [m]() mutable {
+        py::bind_vector<std::vector<VUndeclStruct>>(
+            m, "VectorUndeclStruct", py::buffer_protocol());
     });
 
     // The rest depends on numpy:
-    try { py::module_::import("numpy"); }
-    catch (...) { return; }
+    try {
+        py::module_::import("numpy");
+    } catch (...) {
+        return;
+    }
 
     // test_vector_buffer_numpy
-    struct VStruct { bool w; uint32_t x; double y; bool z; };
+    struct VStruct {
+        bool w;
+        uint32_t x;
+        double y;
+        bool z;
+    };
     PYBIND11_NUMPY_DTYPE(VStruct, w, x, y, z);
     py::class_<VStruct>(m, "VStruct").def_readwrite("x", &VStruct::x);
     py::bind_vector<std::vector<VStruct>>(m, "VectorStruct", py::buffer_protocol());
-    m.def("get_vectorstruct", [] {return std::vector<VStruct> {{0, 5, 3.0, 1}, {1, 30, -1e4, 0}};});
+    m.def("get_vectorstruct", [] {
+        return std::vector<VStruct>{{false, 5, 3.0, true}, {true, 30, -1e4, false}};
+    });
 }
diff --git a/3rdparty/pybind11/tests/test_stl_binders.py b/3rdparty/pybind11/tests/test_stl_binders.py
index 84132a2b4f..d5e9ccced7 100644
--- a/3rdparty/pybind11/tests/test_stl_binders.py
+++ b/3rdparty/pybind11/tests/test_stl_binders.py
@@ -1,8 +1,5 @@
-# -*- coding: utf-8 -*-
 import pytest
 
-import env  # noqa: F401
-
 from pybind11_tests import stl_binders as m
 
 
@@ -75,18 +72,13 @@ def test_vector_buffer():
     assert v[1] == 2
     v[2] = 5
     mv = memoryview(v)  # We expose the buffer interface
-    if not env.PY2:
-        assert mv[2] == 5
-        mv[2] = 6
-    else:
-        assert mv[2] == "\x05"
-        mv[2] = "\x06"
+    assert mv[2] == 5
+    mv[2] = 6
     assert v[2] == 6
 
-    if not env.PY2:
-        mv = memoryview(b)
-        v = m.VectorUChar(mv[::2])
-        assert v[1] == 3
+    mv = memoryview(b)
+    v = m.VectorUChar(mv[::2])
+    assert v[1] == 3
 
     with pytest.raises(RuntimeError) as excinfo:
         m.create_undeclstruct()  # Undeclared struct contents, no buffer interface
@@ -161,15 +153,43 @@ def test_map_string_double():
     mm["b"] = 2.5
 
     assert list(mm) == ["a", "b"]
-    assert list(mm.items()) == [("a", 1), ("b", 2.5)]
     assert str(mm) == "MapStringDouble{a: 1, b: 2.5}"
+    assert "b" in mm
+    assert "c" not in mm
+    assert 123 not in mm
+
+    # Check that keys, values, items are views, not merely iterable
+    keys = mm.keys()
+    values = mm.values()
+    items = mm.items()
+    assert list(keys) == ["a", "b"]
+    assert len(keys) == 2
+    assert "a" in keys
+    assert "c" not in keys
+    assert 123 not in keys
+    assert list(items) == [("a", 1), ("b", 2.5)]
+    assert len(items) == 2
+    assert ("b", 2.5) in items
+    assert "hello" not in items
+    assert ("b", 2.5, None) not in items
+    assert list(values) == [1, 2.5]
+    assert len(values) == 2
+    assert 1 in values
+    assert 2 not in values
+    # Check that views update when the map is updated
+    mm["c"] = -1
+    assert list(keys) == ["a", "b", "c"]
+    assert list(values) == [1, 2.5, -1]
+    assert list(items) == [("a", 1), ("b", 2.5), ("c", -1)]
 
     um = m.UnorderedMapStringDouble()
     um["ua"] = 1.1
     um["ub"] = 2.6
 
     assert sorted(list(um)) == ["ua", "ub"]
+    assert list(um.keys()) == list(um)
     assert sorted(list(um.items())) == [("ua", 1.1), ("ub", 2.6)]
+    assert list(zip(um.keys(), um.values())) == list(um.items())
     assert "UnorderedMapStringDouble" in str(um)
 
 
diff --git a/3rdparty/pybind11/tests/test_tagbased_polymorphic.cpp b/3rdparty/pybind11/tests/test_tagbased_polymorphic.cpp
index 838a168d2b..12ba6532f3 100644
--- a/3rdparty/pybind11/tests/test_tagbased_polymorphic.cpp
+++ b/3rdparty/pybind11/tests/test_tagbased_polymorphic.cpp
@@ -7,11 +7,11 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
 #include <pybind11/stl.h>
 
-struct Animal
-{
+#include "pybind11_tests.h"
+
+struct Animal {
     // Make this type also a "standard" polymorphic type, to confirm that
     // specializing polymorphic_type_hook using enable_if_t still works
     // (https://github.com/pybind/pybind11/pull/2016/).
@@ -20,55 +20,54 @@ struct Animal
     // Enum for tag-based polymorphism.
     enum class Kind {
         Unknown = 0,
-        Dog = 100, Labrador, Chihuahua, LastDog = 199,
-        Cat = 200, Panther, LastCat = 299
+        Dog = 100,
+        Labrador,
+        Chihuahua,
+        LastDog = 199,
+        Cat = 200,
+        Panther,
+        LastCat = 299
     };
-    static const std::type_info* type_of_kind(Kind kind);
+    static const std::type_info *type_of_kind(Kind kind);
     static std::string name_of_kind(Kind kind);
 
     const Kind kind;
     const std::string name;
 
-  protected:
-    Animal(const std::string& _name, Kind _kind)
-        : kind(_kind), name(_name)
-    {}
+protected:
+    Animal(const std::string &_name, Kind _kind) : kind(_kind), name(_name) {}
 };
 
-struct Dog : Animal
-{
-    Dog(const std::string& _name, Kind _kind = Kind::Dog) : Animal(_name, _kind) {}
+struct Dog : Animal {
+    explicit Dog(const std::string &_name, Kind _kind = Kind::Dog) : Animal(_name, _kind) {}
     std::string bark() const { return name_of_kind(kind) + " " + name + " goes " + sound; }
     std::string sound = "WOOF!";
 };
 
-struct Labrador : Dog
-{
-    Labrador(const std::string& _name, int _excitement = 9001)
+struct Labrador : Dog {
+    explicit Labrador(const std::string &_name, int _excitement = 9001)
         : Dog(_name, Kind::Labrador), excitement(_excitement) {}
     int excitement;
 };
 
-struct Chihuahua : Dog
-{
-    Chihuahua(const std::string& _name) : Dog(_name, Kind::Chihuahua) { sound = "iyiyiyiyiyi"; }
+struct Chihuahua : Dog {
+    explicit Chihuahua(const std::string &_name) : Dog(_name, Kind::Chihuahua) {
+        sound = "iyiyiyiyiyi";
+    }
     std::string bark() const { return Dog::bark() + " and runs in circles"; }
 };
 
-struct Cat : Animal
-{
-    Cat(const std::string& _name, Kind _kind = Kind::Cat) : Animal(_name, _kind) {}
+struct Cat : Animal {
+    explicit Cat(const std::string &_name, Kind _kind = Kind::Cat) : Animal(_name, _kind) {}
     std::string purr() const { return "mrowr"; }
 };
 
-struct Panther : Cat
-{
-    Panther(const std::string& _name) : Cat(_name, Kind::Panther) {}
+struct Panther : Cat {
+    explicit Panther(const std::string &_name) : Cat(_name, Kind::Panther) {}
     std::string purr() const { return "mrrrRRRRRR"; }
 };
 
-std::vector<std::unique_ptr<Animal>> create_zoo()
-{
+std::vector<std::unique_ptr<Animal>> create_zoo() {
     std::vector<std::unique_ptr<Animal>> ret;
     ret.emplace_back(new Labrador("Fido", 15000));
 
@@ -83,45 +82,53 @@ std::vector<std::unique_ptr<Animal>> create_zoo()
     return ret;
 }
 
-const std::type_info* Animal::type_of_kind(Kind kind)
-{
+const std::type_info *Animal::type_of_kind(Kind kind) {
     switch (kind) {
-        case Kind::Unknown: break;
-
-        case Kind::Dog: break;
-        case Kind::Labrador: return &typeid(Labrador);
-        case Kind::Chihuahua: return &typeid(Chihuahua);
-        case Kind::LastDog: break;
-
-        case Kind::Cat: break;
-        case Kind::Panther: return &typeid(Panther);
-        case Kind::LastCat: break;
+        case Kind::Unknown:
+        case Kind::Dog:
+            break;
+
+        case Kind::Labrador:
+            return &typeid(Labrador);
+        case Kind::Chihuahua:
+            return &typeid(Chihuahua);
+
+        case Kind::LastDog:
+        case Kind::Cat:
+            break;
+        case Kind::Panther:
+            return &typeid(Panther);
+        case Kind::LastCat:
+            break;
     }
 
-    if (kind >= Kind::Dog && kind <= Kind::LastDog) return &typeid(Dog);
-    if (kind >= Kind::Cat && kind <= Kind::LastCat) return &typeid(Cat);
+    if (kind >= Kind::Dog && kind <= Kind::LastDog) {
+        return &typeid(Dog);
+    }
+    if (kind >= Kind::Cat && kind <= Kind::LastCat) {
+        return &typeid(Cat);
+    }
     return nullptr;
 }
 
-std::string Animal::name_of_kind(Kind kind)
-{
+std::string Animal::name_of_kind(Kind kind) {
     std::string raw_name = type_of_kind(kind)->name();
     py::detail::clean_type_id(raw_name);
     return raw_name;
 }
 
-namespace pybind11 {
-    template <typename itype>
-    struct polymorphic_type_hook<itype, detail::enable_if_t<std::is_base_of<Animal, itype>::value>>
-    {
-        static const void *get(const itype *src, const std::type_info*& type)
-        { type = src ? Animal::type_of_kind(src->kind) : nullptr; return src; }
-    };
-} // namespace pybind11
+namespace PYBIND11_NAMESPACE {
+template <typename itype>
+struct polymorphic_type_hook<itype, detail::enable_if_t<std::is_base_of<Animal, itype>::value>> {
+    static const void *get(const itype *src, const std::type_info *&type) {
+        type = src ? Animal::type_of_kind(src->kind) : nullptr;
+        return src;
+    }
+};
+} // namespace PYBIND11_NAMESPACE
 
 TEST_SUBMODULE(tagbased_polymorphic, m) {
-    py::class_<Animal>(m, "Animal")
-        .def_readonly("name", &Animal::name);
+    py::class_<Animal>(m, "Animal").def_readonly("name", &Animal::name);
     py::class_<Dog, Animal>(m, "Dog")
         .def(py::init<std::string>())
         .def_readwrite("sound", &Dog::sound)
@@ -132,9 +139,7 @@ TEST_SUBMODULE(tagbased_polymorphic, m) {
     py::class_<Chihuahua, Dog>(m, "Chihuahua")
         .def(py::init<std::string>())
         .def("bark", &Chihuahua::bark);
-    py::class_<Cat, Animal>(m, "Cat")
-        .def(py::init<std::string>())
-        .def("purr", &Cat::purr);
+    py::class_<Cat, Animal>(m, "Cat").def(py::init<std::string>()).def("purr", &Cat::purr);
     py::class_<Panther, Cat>(m, "Panther")
         .def(py::init<std::string>())
         .def("purr", &Panther::purr);
diff --git a/3rdparty/pybind11/tests/test_tagbased_polymorphic.py b/3rdparty/pybind11/tests/test_tagbased_polymorphic.py
index 64eb8a3c1b..84f0ea7178 100644
--- a/3rdparty/pybind11/tests/test_tagbased_polymorphic.py
+++ b/3rdparty/pybind11/tests/test_tagbased_polymorphic.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 from pybind11_tests import tagbased_polymorphic as m
 
 
diff --git a/3rdparty/pybind11/tests/test_thread.cpp b/3rdparty/pybind11/tests/test_thread.cpp
new file mode 100644
index 0000000000..1536503b6b
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_thread.cpp
@@ -0,0 +1,66 @@
+/*
+    tests/test_thread.cpp -- call pybind11 bound methods in threads
+
+    Copyright (c) 2021 Laramie Leavitt (Google LLC) <lar@google.com>
+
+    All rights reserved. Use of this source code is governed by a
+    BSD-style license that can be found in the LICENSE file.
+*/
+
+#include <pybind11/cast.h>
+#include <pybind11/pybind11.h>
+
+#include "pybind11_tests.h"
+
+#include <chrono>
+#include <thread>
+
+namespace py = pybind11;
+
+namespace {
+
+struct IntStruct {
+    explicit IntStruct(int v) : value(v){};
+    ~IntStruct() { value = -value; }
+    IntStruct(const IntStruct &) = default;
+    IntStruct &operator=(const IntStruct &) = default;
+
+    int value;
+};
+
+} // namespace
+
+TEST_SUBMODULE(thread, m) {
+
+    py::class_<IntStruct>(m, "IntStruct").def(py::init([](const int i) { return IntStruct(i); }));
+
+    // implicitly_convertible uses loader_life_support when an implicit
+    // conversion is required in order to lifetime extend the reference.
+    //
+    // This test should be run with ASAN for better effectiveness.
+    py::implicitly_convertible<int, IntStruct>();
+
+    m.def("test", [](int expected, const IntStruct &in) {
+        {
+            py::gil_scoped_release release;
+            std::this_thread::sleep_for(std::chrono::milliseconds(5));
+        }
+
+        if (in.value != expected) {
+            throw std::runtime_error("Value changed!!");
+        }
+    });
+
+    m.def(
+        "test_no_gil",
+        [](int expected, const IntStruct &in) {
+            std::this_thread::sleep_for(std::chrono::milliseconds(5));
+            if (in.value != expected) {
+                throw std::runtime_error("Value changed!!");
+            }
+        },
+        py::call_guard<py::gil_scoped_release>());
+
+    // NOTE: std::string_view also uses loader_life_support to ensure that
+    // the string contents remain alive, but that's a C++ 17 feature.
+}
diff --git a/3rdparty/pybind11/tests/test_thread.py b/3rdparty/pybind11/tests/test_thread.py
new file mode 100644
index 0000000000..e89991f9d6
--- /dev/null
+++ b/3rdparty/pybind11/tests/test_thread.py
@@ -0,0 +1,42 @@
+import threading
+
+from pybind11_tests import thread as m
+
+
+class Thread(threading.Thread):
+    def __init__(self, fn):
+        super().__init__()
+        self.fn = fn
+        self.e = None
+
+    def run(self):
+        try:
+            for i in range(10):
+                self.fn(i, i)
+        except Exception as e:
+            self.e = e
+
+    def join(self):
+        super().join()
+        if self.e:
+            raise self.e
+
+
+def test_implicit_conversion():
+    a = Thread(m.test)
+    b = Thread(m.test)
+    c = Thread(m.test)
+    for x in [a, b, c]:
+        x.start()
+    for x in [c, b, a]:
+        x.join()
+
+
+def test_implicit_conversion_no_gil():
+    a = Thread(m.test_no_gil)
+    b = Thread(m.test_no_gil)
+    c = Thread(m.test_no_gil)
+    for x in [a, b, c]:
+        x.start()
+    for x in [c, b, a]:
+        x.join()
diff --git a/3rdparty/pybind11/tests/test_union.py b/3rdparty/pybind11/tests/test_union.py
index 2a2c12fb48..e1866e701d 100644
--- a/3rdparty/pybind11/tests/test_union.py
+++ b/3rdparty/pybind11/tests/test_union.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 from pybind11_tests import union_ as m
 
 
diff --git a/3rdparty/pybind11/tests/test_virtual_functions.cpp b/3rdparty/pybind11/tests/test_virtual_functions.cpp
index 685d64a7ca..323aa0d22d 100644
--- a/3rdparty/pybind11/tests/test_virtual_functions.cpp
+++ b/3rdparty/pybind11/tests/test_virtual_functions.cpp
@@ -7,22 +7,28 @@
     BSD-style license that can be found in the LICENSE file.
 */
 
-#include "pybind11_tests.h"
-#include "constructor_stats.h"
 #include <pybind11/functional.h>
+
+#include "constructor_stats.h"
+#include "pybind11_tests.h"
+
 #include <thread>
 
 /* This is an example class that we'll want to be able to extend from Python */
-class ExampleVirt  {
+class ExampleVirt {
 public:
-    ExampleVirt(int state) : state(state) { print_created(this, state); }
+    explicit ExampleVirt(int state) : state(state) { print_created(this, state); }
     ExampleVirt(const ExampleVirt &e) : state(e.state) { print_copy_created(this); }
-    ExampleVirt(ExampleVirt &&e) : state(e.state) { print_move_created(this); e.state = 0; }
+    ExampleVirt(ExampleVirt &&e) noexcept : state(e.state) {
+        print_move_created(this);
+        e.state = 0;
+    }
     virtual ~ExampleVirt() { print_destroyed(this); }
 
     virtual int run(int value) {
         py::print("Original implementation of "
-                  "ExampleVirt::run(state={}, value={}, str1={}, str2={})"_s.format(state, value, get_string1(), *get_string2()));
+                  "ExampleVirt::run(state={}, value={}, str1={}, str2={})"_s.format(
+                      state, value, get_string1(), *get_string2()));
         return state + value;
     }
 
@@ -30,8 +36,8 @@ class ExampleVirt  {
     virtual void pure_virtual() = 0;
 
     // Returning a reference/pointer to a type converted from python (numbers, strings, etc.) is a
-    // bit trickier, because the actual int& or std::string& or whatever only exists temporarily, so
-    // we have to handle it specially in the trampoline class (see below).
+    // bit trickier, because the actual int& or std::string& or whatever only exists temporarily,
+    // so we have to handle it specially in the trampoline class (see below).
     virtual const std::string &get_string1() { return str1; }
     virtual const std::string *get_string2() { return &str2; }
 
@@ -47,66 +53,63 @@ class PyExampleVirt : public ExampleVirt {
 
     int run(int value) override {
         /* Generate wrapping code that enables native function overloading */
-        PYBIND11_OVERRIDE(
-            int,         /* Return type */
-            ExampleVirt, /* Parent class */
-            run,         /* Name of function */
-            value        /* Argument(s) */
+        PYBIND11_OVERRIDE(int,         /* Return type */
+                          ExampleVirt, /* Parent class */
+                          run,         /* Name of function */
+                          value        /* Argument(s) */
         );
     }
 
     bool run_bool() override {
-        PYBIND11_OVERRIDE_PURE(
-            bool,         /* Return type */
-            ExampleVirt,  /* Parent class */
-            run_bool,     /* Name of function */
-                          /* This function has no arguments. The trailing comma
-                             in the previous line is needed for some compilers */
+        PYBIND11_OVERRIDE_PURE(bool,        /* Return type */
+                               ExampleVirt, /* Parent class */
+                               run_bool,    /* Name of function */
+                                            /* This function has no arguments. The trailing comma
+                                               in the previous line is needed for some compilers */
         );
     }
 
     void pure_virtual() override {
-        PYBIND11_OVERRIDE_PURE(
-            void,         /* Return type */
-            ExampleVirt,  /* Parent class */
-            pure_virtual, /* Name of function */
-                          /* This function has no arguments. The trailing comma
-                             in the previous line is needed for some compilers */
+        PYBIND11_OVERRIDE_PURE(void,         /* Return type */
+                               ExampleVirt,  /* Parent class */
+                               pure_virtual, /* Name of function */
+                                             /* This function has no arguments. The trailing comma
+                                                in the previous line is needed for some compilers */
         );
     }
 
     // We can return reference types for compatibility with C++ virtual interfaces that do so, but
     // note they have some significant limitations (see the documentation).
     const std::string &get_string1() override {
-        PYBIND11_OVERRIDE(
-            const std::string &, /* Return type */
-            ExampleVirt,         /* Parent class */
-            get_string1,         /* Name of function */
-                                 /* (no arguments) */
+        PYBIND11_OVERRIDE(const std::string &, /* Return type */
+                          ExampleVirt,         /* Parent class */
+                          get_string1,         /* Name of function */
+                                               /* (no arguments) */
         );
     }
 
     const std::string *get_string2() override {
-        PYBIND11_OVERRIDE(
-            const std::string *, /* Return type */
-            ExampleVirt,         /* Parent class */
-            get_string2,         /* Name of function */
-                                 /* (no arguments) */
+        PYBIND11_OVERRIDE(const std::string *, /* Return type */
+                          ExampleVirt,         /* Parent class */
+                          get_string2,         /* Name of function */
+                                               /* (no arguments) */
         );
     }
-
 };
 
 class NonCopyable {
 public:
-    NonCopyable(int a, int b) : value{new int(a*b)} { print_created(this, a, b); }
-    NonCopyable(NonCopyable &&o) { value = std::move(o.value); print_move_created(this); }
+    NonCopyable(int a, int b) : value{new int(a * b)} { print_created(this, a, b); }
+    NonCopyable(NonCopyable &&o) noexcept : value{std::move(o.value)} { print_move_created(this); }
     NonCopyable(const NonCopyable &) = delete;
     NonCopyable() = delete;
     void operator=(const NonCopyable &) = delete;
     void operator=(NonCopyable &&) = delete;
     std::string get_value() const {
-        if (value) return std::to_string(*value); else return "(null)";
+        if (value) {
+            return std::to_string(*value);
+        }
+        return "(null)";
     }
     ~NonCopyable() { print_destroyed(this); }
 
@@ -118,11 +121,12 @@ class NonCopyable {
 // when it is not referenced elsewhere, but copied if it is still referenced.
 class Movable {
 public:
-    Movable(int a, int b) : value{a+b} { print_created(this, a, b); }
-    Movable(const Movable &m) { value = m.value; print_copy_created(this); }
-    Movable(Movable &&m) { value = std::move(m.value); print_move_created(this); }
+    Movable(int a, int b) : value{a + b} { print_created(this, a, b); }
+    Movable(const Movable &m) : value{m.value} { print_copy_created(this); }
+    Movable(Movable &&m) noexcept : value{m.value} { print_move_created(this); }
     std::string get_value() const { return std::to_string(value); }
     ~Movable() { print_destroyed(this); }
+
 private:
     int value;
 };
@@ -131,7 +135,7 @@ class NCVirt {
 public:
     virtual ~NCVirt() = default;
     NCVirt() = default;
-    NCVirt(const NCVirt&) = delete;
+    NCVirt(const NCVirt &) = delete;
     virtual NonCopyable get_noncopyable(int a, int b) { return NonCopyable(a, b); }
     virtual Movable get_movable(int a, int b) = 0;
 
@@ -150,11 +154,10 @@ class NCVirtTrampoline : public NCVirt {
 };
 
 struct Base {
-    /* for some reason MSVC2015 can't compile this if the function is pure virtual */
-    virtual std::string dispatch() const { return {}; };
+    virtual std::string dispatch() const = 0;
     virtual ~Base() = default;
     Base() = default;
-    Base(const Base&) = delete;
+    Base(const Base &) = delete;
 };
 
 struct DispatchIssue : Base {
@@ -163,18 +166,37 @@ struct DispatchIssue : Base {
     }
 };
 
+// An abstract adder class that uses visitor pattern to add two data
+// objects and send the result to the visitor functor
+struct AdderBase {
+    struct Data {};
+    using DataVisitor = std::function<void(const Data &)>;
+
+    virtual void
+    operator()(const Data &first, const Data &second, const DataVisitor &visitor) const = 0;
+    virtual ~AdderBase() = default;
+    AdderBase() = default;
+    AdderBase(const AdderBase &) = delete;
+};
+
+struct Adder : AdderBase {
+    void
+    operator()(const Data &first, const Data &second, const DataVisitor &visitor) const override {
+        PYBIND11_OVERRIDE_PURE_NAME(
+            void, AdderBase, "__call__", operator(), first, second, visitor);
+    }
+};
+
 static void test_gil() {
     {
         py::gil_scoped_acquire lock;
         py::print("1st lock acquired");
-
     }
 
     {
         py::gil_scoped_acquire lock;
         py::print("2nd lock acquired");
     }
-
 }
 
 static void test_gil_from_thread() {
@@ -184,9 +206,28 @@ static void test_gil_from_thread() {
     t.join();
 }
 
+class test_override_cache_helper {
+
+public:
+    virtual int func() { return 0; }
+
+    test_override_cache_helper() = default;
+    virtual ~test_override_cache_helper() = default;
+    // Non-copyable
+    test_override_cache_helper &operator=(test_override_cache_helper const &Right) = delete;
+    test_override_cache_helper(test_override_cache_helper const &Copy) = delete;
+};
+
+class test_override_cache_helper_trampoline : public test_override_cache_helper {
+    int func() override { PYBIND11_OVERRIDE(int, test_override_cache_helper, func); }
+};
 
-// Forward declaration (so that we can put the main tests here; the inherited virtual approaches are
-// rather long).
+inline int test_override_cache(std::shared_ptr<test_override_cache_helper> const &instance) {
+    return instance->func();
+}
+
+// Forward declaration (so that we can put the main tests here; the inherited virtual approaches
+// are rather long).
 void initialize_inherited_virtuals(py::module_ &m);
 
 TEST_SUBMODULE(virtual_functions, m) {
@@ -198,11 +239,9 @@ TEST_SUBMODULE(virtual_functions, m) {
         .def("run_bool", &ExampleVirt::run_bool)
         .def("pure_virtual", &ExampleVirt::pure_virtual);
 
-    py::class_<NonCopyable>(m, "NonCopyable")
-        .def(py::init<int, int>());
+    py::class_<NonCopyable>(m, "NonCopyable").def(py::init<int, int>());
 
-    py::class_<Movable>(m, "Movable")
-        .def(py::init<int, int>());
+    py::class_<Movable>(m, "Movable").def(py::init<int, int>());
 
     // test_move_support
 #if !defined(__INTEL_COMPILER) && !defined(__CUDACC__) && !defined(__PGIC__)
@@ -215,7 +254,7 @@ TEST_SUBMODULE(virtual_functions, m) {
 #endif
 
     m.def("runExampleVirt", [](ExampleVirt *ex, int value) { return ex->run(value); });
-    m.def("runExampleVirtBool", [](ExampleVirt* ex) { return ex->run_bool(); });
+    m.def("runExampleVirtBool", [](ExampleVirt *ex) { return ex->run_bool(); });
     m.def("runExampleVirtVirtual", [](ExampleVirt *ex) { ex->pure_virtual(); });
 
     m.def("cstats_debug", &ConstructorStats::get<ExampleVirt>);
@@ -226,27 +265,25 @@ TEST_SUBMODULE(virtual_functions, m) {
     // that were not extended on the Python side
     struct A {
         A() = default;
-        A(const A&) = delete;
+        A(const A &) = delete;
         virtual ~A() = default;
         virtual void f() { py::print("A.f()"); }
     };
 
     struct PyA : A {
         PyA() { py::print("PyA.PyA()"); }
-        PyA(const PyA&) = delete;
+        PyA(const PyA &) = delete;
         ~PyA() override { py::print("PyA.~PyA()"); }
 
         void f() override {
             py::print("PyA.f()");
-            // This convolution just gives a `void`, but tests that PYBIND11_TYPE() works to protect
-            // a type containing a ,
+            // This convolution just gives a `void`, but tests that PYBIND11_TYPE() works to
+            // protect a type containing a ,
             PYBIND11_OVERRIDE(PYBIND11_TYPE(typename std::enable_if<true, void>::type), A, f);
         }
     };
 
-    py::class_<A, PyA>(m, "A")
-        .def(py::init<>())
-        .def("f", &A::f);
+    py::class_<A, PyA>(m, "A").def(py::init<>()).def("f", &A::f);
 
     m.def("call_f", [](A *a) { a->f(); });
 
@@ -254,14 +291,14 @@ TEST_SUBMODULE(virtual_functions, m) {
     // ... unless we explicitly request it, as in this example:
     struct A2 {
         A2() = default;
-        A2(const A2&) = delete;
+        A2(const A2 &) = delete;
         virtual ~A2() = default;
         virtual void f() { py::print("A2.f()"); }
     };
 
     struct PyA2 : A2 {
         PyA2() { py::print("PyA2.PyA2()"); }
-        PyA2(const PyA2&) = delete;
+        PyA2(const PyA2 &) = delete;
         ~PyA2() override { py::print("PyA2.~PyA2()"); }
         void f() override {
             py::print("PyA2.f()");
@@ -282,18 +319,46 @@ TEST_SUBMODULE(virtual_functions, m) {
         .def(py::init<>())
         .def("dispatch", &Base::dispatch);
 
-    m.def("dispatch_issue_go", [](const Base * b) { return b->dispatch(); });
+    m.def("dispatch_issue_go", [](const Base *b) { return b->dispatch(); });
+
+    // test_recursive_dispatch_issue
+    // #3357: Recursive dispatch fails to find python function override
+    pybind11::class_<AdderBase, Adder>(m, "Adder")
+        .def(pybind11::init<>())
+        .def("__call__", &AdderBase::operator());
+
+    pybind11::class_<AdderBase::Data>(m, "Data").def(pybind11::init<>());
+
+    m.def("add2",
+          [](const AdderBase::Data &first,
+             const AdderBase::Data &second,
+             const AdderBase &adder,
+             const AdderBase::DataVisitor &visitor) { adder(first, second, visitor); });
+
+    m.def("add3",
+          [](const AdderBase::Data &first,
+             const AdderBase::Data &second,
+             const AdderBase::Data &third,
+             const AdderBase &adder,
+             const AdderBase::DataVisitor &visitor) {
+              adder(first, second, [&](const AdderBase::Data &first_plus_second) {
+                  // NOLINTNEXTLINE(readability-suspicious-call-argument)
+                  adder(first_plus_second, third, visitor);
+              });
+          });
 
     // test_override_ref
     // #392/397: overriding reference-returning functions
     class OverrideTest {
     public:
-        struct A { std::string value = "hi"; };
+        struct A {
+            std::string value = "hi";
+        };
         std::string v;
         A a;
         explicit OverrideTest(const std::string &v) : v{v} {}
         OverrideTest() = default;
-        OverrideTest(const OverrideTest&) = delete;
+        OverrideTest(const OverrideTest &) = delete;
         virtual std::string str_value() { return v; }
         virtual std::string &str_ref() { return v; }
         virtual A A_value() { return a; }
@@ -304,14 +369,22 @@ TEST_SUBMODULE(virtual_functions, m) {
     class PyOverrideTest : public OverrideTest {
     public:
         using OverrideTest::OverrideTest;
-        std::string str_value() override { PYBIND11_OVERRIDE(std::string, OverrideTest, str_value); }
-        // Not allowed (uncommenting should hit a static_assert failure): we can't get a reference
-        // to a python numeric value, since we only copy values in the numeric type caster:
-//      std::string &str_ref() override { PYBIND11_OVERRIDE(std::string &, OverrideTest, str_ref); }
+        std::string str_value() override {
+            PYBIND11_OVERRIDE(std::string, OverrideTest, str_value);
+        }
+        // Not allowed (enabling the below should hit a static_assert failure): we can't get a
+        // reference to a python numeric value, since we only copy values in the numeric type
+        // caster:
+#ifdef PYBIND11_NEVER_DEFINED_EVER
+        std::string &str_ref() override {
+            PYBIND11_OVERRIDE(std::string &, OverrideTest, str_ref);
+        }
+#endif
         // But we can work around it like this:
     private:
         std::string _tmp;
         std::string str_ref_helper() { PYBIND11_OVERRIDE(std::string, OverrideTest, str_ref); }
+
     public:
         std::string &str_ref() override { return _tmp = str_ref_helper(); }
 
@@ -324,11 +397,20 @@ TEST_SUBMODULE(virtual_functions, m) {
     py::class_<OverrideTest, PyOverrideTest>(m, "OverrideTest")
         .def(py::init<const std::string &>())
         .def("str_value", &OverrideTest::str_value)
-//      .def("str_ref", &OverrideTest::str_ref)
+#ifdef PYBIND11_NEVER_DEFINED_EVER
+        .def("str_ref", &OverrideTest::str_ref)
+#endif
         .def("A_value", &OverrideTest::A_value)
         .def("A_ref", &OverrideTest::A_ref);
-}
 
+    py::class_<test_override_cache_helper,
+               test_override_cache_helper_trampoline,
+               std::shared_ptr<test_override_cache_helper>>(m, "test_override_cache_helper")
+        .def(py::init_alias<>())
+        .def("func", &test_override_cache_helper::func);
+
+    m.def("test_override_cache", test_override_cache);
+}
 
 // Inheriting virtual methods.  We do two versions here: the repeat-everything version and the
 // templated trampoline versions mentioned in docs/advanced.rst.
@@ -338,94 +420,107 @@ TEST_SUBMODULE(virtual_functions, m) {
 // properly (pybind11, sensibly, doesn't allow us to bind the same C++ class to
 // multiple python classes).
 class A_Repeat {
-#define A_METHODS \
-public: \
-    virtual int unlucky_number() = 0; \
-    virtual std::string say_something(unsigned times) { \
-        std::string s = ""; \
-        for (unsigned i = 0; i < times; ++i) \
-            s += "hi"; \
-        return s; \
-    } \
-    std::string say_everything() { \
-        return say_something(1) + " " + std::to_string(unlucky_number()); \
+#define A_METHODS                                                                                 \
+public:                                                                                           \
+    virtual int unlucky_number() = 0;                                                             \
+    virtual std::string say_something(unsigned times) {                                           \
+        std::string s = "";                                                                       \
+        for (unsigned i = 0; i < times; ++i)                                                      \
+            s += "hi";                                                                            \
+        return s;                                                                                 \
+    }                                                                                             \
+    std::string say_everything() {                                                                \
+        return say_something(1) + " " + std::to_string(unlucky_number());                         \
     }
-A_METHODS
+    A_METHODS
     A_Repeat() = default;
-    A_Repeat(const A_Repeat&) = delete;
+    A_Repeat(const A_Repeat &) = delete;
     virtual ~A_Repeat() = default;
 };
 class B_Repeat : public A_Repeat {
-#define B_METHODS \
-public: \
-    int unlucky_number() override { return 13; } \
-    std::string say_something(unsigned times) override { \
-        return "B says hi " + std::to_string(times) + " times"; \
-    } \
+#define B_METHODS                                                                                 \
+public:                                                                                           \
+    int unlucky_number() override { return 13; }                                                  \
+    std::string say_something(unsigned times) override {                                          \
+        return "B says hi " + std::to_string(times) + " times";                                   \
+    }                                                                                             \
     virtual double lucky_number() { return 7.0; }
-B_METHODS
+    B_METHODS
 };
 class C_Repeat : public B_Repeat {
-#define C_METHODS \
-public: \
-    int unlucky_number() override { return 4444; } \
+#define C_METHODS                                                                                 \
+public:                                                                                           \
+    int unlucky_number() override { return 4444; }                                                \
     double lucky_number() override { return 888; }
-C_METHODS
+    C_METHODS
 };
 class D_Repeat : public C_Repeat {
 #define D_METHODS // Nothing overridden.
-D_METHODS
+    D_METHODS
 };
 
 // Base classes for templated inheritance trampolines.  Identical to the repeat-everything version:
 class A_Tpl {
     A_METHODS;
     A_Tpl() = default;
-    A_Tpl(const A_Tpl&) = delete;
+    A_Tpl(const A_Tpl &) = delete;
     virtual ~A_Tpl() = default;
 };
-class B_Tpl : public A_Tpl { B_METHODS };
-class C_Tpl : public B_Tpl { C_METHODS };
-class D_Tpl : public C_Tpl { D_METHODS };
-
+class B_Tpl : public A_Tpl {
+    B_METHODS
+};
+class C_Tpl : public B_Tpl {
+    C_METHODS
+};
+class D_Tpl : public C_Tpl {
+    D_METHODS
+};
 
 // Inheritance approach 1: each trampoline gets every virtual method (11 in total)
 class PyA_Repeat : public A_Repeat {
 public:
     using A_Repeat::A_Repeat;
     int unlucky_number() override { PYBIND11_OVERRIDE_PURE(int, A_Repeat, unlucky_number, ); }
-    std::string say_something(unsigned times) override { PYBIND11_OVERRIDE(std::string, A_Repeat, say_something, times); }
+    std::string say_something(unsigned times) override {
+        PYBIND11_OVERRIDE(std::string, A_Repeat, say_something, times);
+    }
 };
 class PyB_Repeat : public B_Repeat {
 public:
     using B_Repeat::B_Repeat;
     int unlucky_number() override { PYBIND11_OVERRIDE(int, B_Repeat, unlucky_number, ); }
-    std::string say_something(unsigned times) override { PYBIND11_OVERRIDE(std::string, B_Repeat, say_something, times); }
+    std::string say_something(unsigned times) override {
+        PYBIND11_OVERRIDE(std::string, B_Repeat, say_something, times);
+    }
     double lucky_number() override { PYBIND11_OVERRIDE(double, B_Repeat, lucky_number, ); }
 };
 class PyC_Repeat : public C_Repeat {
 public:
     using C_Repeat::C_Repeat;
     int unlucky_number() override { PYBIND11_OVERRIDE(int, C_Repeat, unlucky_number, ); }
-    std::string say_something(unsigned times) override { PYBIND11_OVERRIDE(std::string, C_Repeat, say_something, times); }
+    std::string say_something(unsigned times) override {
+        PYBIND11_OVERRIDE(std::string, C_Repeat, say_something, times);
+    }
     double lucky_number() override { PYBIND11_OVERRIDE(double, C_Repeat, lucky_number, ); }
 };
 class PyD_Repeat : public D_Repeat {
 public:
     using D_Repeat::D_Repeat;
     int unlucky_number() override { PYBIND11_OVERRIDE(int, D_Repeat, unlucky_number, ); }
-    std::string say_something(unsigned times) override { PYBIND11_OVERRIDE(std::string, D_Repeat, say_something, times); }
+    std::string say_something(unsigned times) override {
+        PYBIND11_OVERRIDE(std::string, D_Repeat, say_something, times);
+    }
     double lucky_number() override { PYBIND11_OVERRIDE(double, D_Repeat, lucky_number, ); }
 };
 
 // Inheritance approach 2: templated trampoline classes.
 //
 // Advantages:
-// - we have only 2 (template) class and 4 method declarations (one per virtual method, plus one for
-//   any override of a pure virtual method), versus 4 classes and 6 methods (MI) or 4 classes and 11
-//   methods (repeat).
-// - Compared to MI, we also don't have to change the non-trampoline inheritance to virtual, and can
-//   properly inherit constructors.
+// - we have only 2 (template) class and 4 method declarations (one per virtual method, plus one
+//   for any override of a pure virtual method), versus 4 classes and 6 methods (MI) or 4 classes
+//   and 11 methods (repeat).
+// - Compared to MI, we also don't have to change the non-trampoline inheritance to virtual, and
+//   can properly inherit constructors.
 //
 // Disadvantage:
 // - the compiler must still generate and compile 14 different methods (more, even, than the 11
@@ -437,17 +532,20 @@ class PyA_Tpl : public Base {
 public:
     using Base::Base; // Inherit constructors
     int unlucky_number() override { PYBIND11_OVERRIDE_PURE(int, Base, unlucky_number, ); }
-    std::string say_something(unsigned times) override { PYBIND11_OVERRIDE(std::string, Base, say_something, times); }
+    std::string say_something(unsigned times) override {
+        PYBIND11_OVERRIDE(std::string, Base, say_something, times);
+    }
 };
 template <class Base = B_Tpl>
 class PyB_Tpl : public PyA_Tpl<Base> {
 public:
     using PyA_Tpl<Base>::PyA_Tpl; // Inherit constructors (via PyA_Tpl's inherited constructors)
+    // NOLINTNEXTLINE(bugprone-parent-virtual-call)
     int unlucky_number() override { PYBIND11_OVERRIDE(int, Base, unlucky_number, ); }
     double lucky_number() override { PYBIND11_OVERRIDE(double, Base, lucky_number, ); }
 };
-// Since C_Tpl and D_Tpl don't declare any new virtual methods, we don't actually need these (we can
-// use PyB_Tpl<C_Tpl> and PyB_Tpl<D_Tpl> for the trampoline classes instead):
+// Since C_Tpl and D_Tpl don't declare any new virtual methods, we don't actually need these
+// (we can use PyB_Tpl<C_Tpl> and PyB_Tpl<D_Tpl> for the trampoline classes instead):
 /*
 template <class Base = C_Tpl> class PyC_Tpl : public PyB_Tpl<Base> {
 public:
@@ -471,10 +569,8 @@ void initialize_inherited_virtuals(py::module_ &m) {
     py::class_<B_Repeat, A_Repeat, PyB_Repeat>(m, "B_Repeat")
         .def(py::init<>())
         .def("lucky_number", &B_Repeat::lucky_number);
-    py::class_<C_Repeat, B_Repeat, PyC_Repeat>(m, "C_Repeat")
-        .def(py::init<>());
-    py::class_<D_Repeat, C_Repeat, PyD_Repeat>(m, "D_Repeat")
-        .def(py::init<>());
+    py::class_<C_Repeat, B_Repeat, PyC_Repeat>(m, "C_Repeat").def(py::init<>());
+    py::class_<D_Repeat, C_Repeat, PyD_Repeat>(m, "D_Repeat").def(py::init<>());
 
     // test_
     // Method 2: Templated trampolines
@@ -486,11 +582,8 @@ void initialize_inherited_virtuals(py::module_ &m) {
     py::class_<B_Tpl, A_Tpl, PyB_Tpl<>>(m, "B_Tpl")
         .def(py::init<>())
         .def("lucky_number", &B_Tpl::lucky_number);
-    py::class_<C_Tpl, B_Tpl, PyB_Tpl<C_Tpl>>(m, "C_Tpl")
-        .def(py::init<>());
-    py::class_<D_Tpl, C_Tpl, PyB_Tpl<D_Tpl>>(m, "D_Tpl")
-        .def(py::init<>());
-
+    py::class_<C_Tpl, B_Tpl, PyB_Tpl<C_Tpl>>(m, "C_Tpl").def(py::init<>());
+    py::class_<D_Tpl, C_Tpl, PyB_Tpl<D_Tpl>>(m, "D_Tpl").def(py::init<>());
 
     // Fix issue #1454 (crash when acquiring/releasing GIL on another thread in Python 2.7)
     m.def("test_gil", &test_gil);
diff --git a/3rdparty/pybind11/tests/test_virtual_functions.py b/3rdparty/pybind11/tests/test_virtual_functions.py
index ae19930164..4d00d3690d 100644
--- a/3rdparty/pybind11/tests/test_virtual_functions.py
+++ b/3rdparty/pybind11/tests/test_virtual_functions.py
@@ -1,4 +1,3 @@
-# -*- coding: utf-8 -*-
 import pytest
 
 import env  # noqa: F401
@@ -10,12 +9,12 @@
 def test_override(capture, msg):
     class ExtendedExampleVirt(m.ExampleVirt):
         def __init__(self, state):
-            super(ExtendedExampleVirt, self).__init__(state + 1)
+            super().__init__(state + 1)
             self.data = "Hello world"
 
         def run(self, value):
-            print("ExtendedExampleVirt::run(%i), calling parent.." % value)
-            return super(ExtendedExampleVirt, self).run(value + 1)
+            print(f"ExtendedExampleVirt::run({value}), calling parent..")
+            return super().run(value + 1)
 
         def run_bool(self):
             print("ExtendedExampleVirt::run_bool()")
@@ -25,11 +24,11 @@ def get_string1(self):
             return "override1"
 
         def pure_virtual(self):
-            print("ExtendedExampleVirt::pure_virtual(): %s" % self.data)
+            print(f"ExtendedExampleVirt::pure_virtual(): {self.data}")
 
     class ExtendedExampleVirt2(ExtendedExampleVirt):
         def __init__(self, state):
-            super(ExtendedExampleVirt2, self).__init__(state + 1)
+            super().__init__(state + 1)
 
         def get_string2(self):
             return "override2"
@@ -41,7 +40,7 @@ def get_string2(self):
         capture
         == """
         Original implementation of ExampleVirt::run(state=10, value=20, str1=default1, str2=default2)
-    """  # noqa: E501 line too long
+    """
     )
 
     with pytest.raises(RuntimeError) as excinfo:
@@ -59,7 +58,7 @@ def get_string2(self):
         == """
         ExtendedExampleVirt::run(20), calling parent..
         Original implementation of ExampleVirt::run(state=11, value=21, str1=override1, str2=default2)
-    """  # noqa: E501 line too long
+    """
     )
     with capture:
         assert m.runExampleVirtBool(ex12p) is False
@@ -76,7 +75,7 @@ def get_string2(self):
         == """
         ExtendedExampleVirt::run(50), calling parent..
         Original implementation of ExampleVirt::run(state=17, value=51, str1=override1, str2=override2)
-    """  # noqa: E501 line too long
+    """
     )
 
     cstats = ConstructorStats.get(m.ExampleVirt)
@@ -97,7 +96,7 @@ def test_alias_delay_initialization1(capture):
 
     class B(m.A):
         def __init__(self):
-            super(B, self).__init__()
+            super().__init__()
 
         def f(self):
             print("In python f()")
@@ -137,7 +136,7 @@ class such as defining local variables and performing construction/destruction.
 
     class B2(m.A2):
         def __init__(self):
-            super(B2, self).__init__()
+            super().__init__()
 
         def f(self):
             print("In python B2.f()")
@@ -245,19 +244,51 @@ def dispatch(self):
     class PyClass2(m.DispatchIssue):
         def dispatch(self):
             with pytest.raises(RuntimeError) as excinfo:
-                super(PyClass2, self).dispatch()
+                super().dispatch()
             assert (
                 msg(excinfo.value)
                 == 'Tried to call pure virtual function "Base::dispatch"'
             )
 
-            p = PyClass1()
-            return m.dispatch_issue_go(p)
+            return m.dispatch_issue_go(PyClass1())
 
     b = PyClass2()
     assert m.dispatch_issue_go(b) == "Yay.."
 
 
+def test_recursive_dispatch_issue(msg):
+    """#3357: Recursive dispatch fails to find python function override"""
+
+    class Data(m.Data):
+        def __init__(self, value):
+            super().__init__()
+            self.value = value
+
+    class Adder(m.Adder):
+        def __call__(self, first, second, visitor):
+            # lambda is a workaround, which adds extra frame to the
+            # current CPython thread. Removing lambda reveals the bug
+            # [https://github.com/pybind/pybind11/issues/3357]
+            (lambda: visitor(Data(first.value + second.value)))()
+
+    class StoreResultVisitor:
+        def __init__(self):
+            self.result = None
+
+        def __call__(self, data):
+            self.result = data.value
+
+    store = StoreResultVisitor()
+
+    m.add2(Data(1), Data(2), Adder(), store)
+    assert store.result == 3
+
+    # without lambda in Adder class, this function fails with
+    # RuntimeError: Tried to call pure virtual function "AdderBase::__call__"
+    m.add3(Data(1), Data(2), Data(3), Adder(), store)
+    assert store.result == 6
+
+
 def test_override_ref():
     """#392/397: overriding reference-returning functions"""
     o = m.OverrideTest("asdf")
@@ -407,3 +438,22 @@ def test_issue_1454():
     # Fix issue #1454 (crash when acquiring/releasing GIL on another thread in Python 2.7)
     m.test_gil()
     m.test_gil_from_thread()
+
+
+def test_python_override():
+    def func():
+        class Test(m.test_override_cache_helper):
+            def func(self):
+                return 42
+
+        return Test()
+
+    def func2():
+        class Test(m.test_override_cache_helper):
+            pass
+
+        return Test()
+
+    for _ in range(1500):
+        assert m.test_override_cache(func()) == 42
+        assert m.test_override_cache(func2()) == 0
diff --git a/3rdparty/pybind11/tests/valgrind-numpy-scipy.supp b/3rdparty/pybind11/tests/valgrind-numpy-scipy.supp
new file mode 100644
index 0000000000..16db302c17
--- /dev/null
+++ b/3rdparty/pybind11/tests/valgrind-numpy-scipy.supp
@@ -0,0 +1,140 @@
+# Valgrind suppression file for NumPy & SciPy errors and leaks in pybind11 tests
+#
+# On updating a dependency, to get a list of "default" leaks in e.g. NumPy, run
+# `PYTHONMALLOC=malloc valgrind --leak-check=full --show-leak-kinds=definite,indirect python3.9-dbg -c "import numpy"`
+# To use these suppression files, add e.g. `--suppressions=valgrind-numpy-scipy.supp`
+
+{
+   Leaks when importing NumPy
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_GC_Alloc
+   fun:_PyObject_GC_Malloc
+   fun:_PyObject_GC_NewVar
+   fun:tuple_alloc
+   fun:PyTuple_Pack
+   ...
+   fun:__pyx_pymod_exec_*
+}
+
+{
+   Leaks when importing NumPy (bis)
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_New
+   fun:PyCode_NewWithPosOnlyArgs
+   fun:PyCode_New
+   ...
+   fun:__pyx_pymod_exec_*
+}
+
+{
+   Leaks when importing NumPy (ter)
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_GC_Alloc
+   fun:_PyObject_GC_Malloc
+   fun:_PyObject_GC_NewVar
+   fun:tuple_alloc
+   fun:_PyTuple_FromArray
+   fun:_PyObject_MakeTpCall
+   fun:_PyObject_VectorcallTstate
+   fun:PyObject_Vectorcall
+   fun:call_function
+   fun:_PyEval_EvalFrameDefault
+   fun:_PyEval_EvalFrame
+   fun:function_code_fastcall
+   fun:_PyFunction_Vectorcall
+}
+
+{
+   Leaks when importing NumPy (quater)
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_GC_Alloc
+   fun:_PyObject_GC_Malloc
+   fun:_PyObject_GC_NewVar
+   fun:tuple_alloc
+   fun:_PyTuple_FromArray
+   fun:_PyObject_MakeTpCall
+   fun:_PyObject_VectorcallTstate
+   fun:_PyObject_CallFunctionVa
+   fun:PyObject_CallFunction
+   fun:PyImport_Import
+}
+
+{
+   Leaks when importing NumPy (quinquies)
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_GC_Alloc
+   fun:_PyObject_GC_Malloc
+   fun:_PyObject_GC_NewVar
+   fun:tuple_alloc
+   fun:PyTuple_New
+   fun:r_object
+   fun:r_object
+   fun:r_object
+   fun:r_object
+}
+
+{
+   Leaks when importing NumPy (sexies)
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyObject_Malloc
+   fun:_PyObject_GC_Alloc
+   fun:_PyObject_GC_Malloc
+   fun:_PyObject_GC_NewVar
+   fun:tuple_alloc
+   fun:PyTuple_New
+   fun:dictiter_iternextitem
+   fun:list_extend
+   fun:_PyList_Extend
+   fun:PySequence_List
+}
+
+{
+   Leak when importing scipy.fft
+   Memcheck:Leak
+   fun:_Znwm
+   fun:PyInit_pypocketfft
+   fun:_PyImport_LoadDynamicModuleWithSpec
+   fun:_imp_create_dynamic_impl*
+   fun:_imp_create_dynamic
+   fun:cfunction_vectorcall_FASTCALL
+   fun:PyVectorcall_Call
+   fun:_PyObject_Call
+   fun:PyObject_Call
+   fun:do_call_core
+   fun:_PyEval_EvalFrameDefault
+   fun:_PyEval_EvalFrame
+   fun:_PyEval_EvalCode
+}
+
+{
+   NumPy leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   ...
+   fun:_buffer_get_info
+   fun:array_getbuffer
+   fun:PyObject_GetBuffer
+   fun:__Pyx__GetBufferAndValidate*
+   fun:__pyx_f_5numpy_6random_13bit_generator_12SeedSequence_mix_entropy
+   fun:__pyx_pw_5numpy_6random_13bit_generator_12SeedSequence_1__init__
+   fun:type_call
+   fun:__Pyx__PyObject_CallOneArg
+   fun:__pyx_pw_5numpy_6random_13bit_generator_12BitGenerator_1__init__
+}
diff --git a/3rdparty/pybind11/tests/valgrind-python.supp b/3rdparty/pybind11/tests/valgrind-python.supp
new file mode 100644
index 0000000000..d77d5e5c5c
--- /dev/null
+++ b/3rdparty/pybind11/tests/valgrind-python.supp
@@ -0,0 +1,117 @@
+# Valgrind suppression file for CPython errors and leaks in pybind11 tests
+
+# Taken verbatim from https://github.com/python/cpython/blob/3.9/Misc/valgrind-python.supp#L266-L272
+{
+   Uninitialised byte(s) false alarm, see bpo-35561
+   Memcheck:Param
+   epoll_ctl(event)
+   fun:epoll_ctl
+   fun:pyepoll_internal_ctl
+}
+
+{
+   Python leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyMem_RawMalloc
+   fun:PyThread_allocate_lock
+   fun:_PyEval_InitState
+   fun:PyInterpreterState_New
+   ...
+   fun:pyinit_core*
+   fun:Py_InitializeFromConfig
+   fun:pymain_init
+   fun:pymain_main
+}
+
+{
+   Python leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:_PyMem_DebugRawAlloc
+   fun:_PyMem_DebugRawMalloc
+   fun:PyMem_RawMalloc
+   fun:PyThread_allocate_lock
+   fun:_PyRuntimeState_Init_impl
+   fun:_PyRuntimeState_Init
+   fun:_PyRuntime_Initialize
+   fun:pymain_init
+   fun:pymain_main
+   fun:Py_BytesMain
+}
+
+{
+   Python leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyMem_RawMalloc
+   fun:PyThread_allocate_lock
+   fun:_PyImport_AcquireLock
+   fun:_imp_acquire_lock_impl*
+   fun:_imp_acquire_lock
+   fun:cfunction_vectorcall_NOARGS
+   fun:_PyObject_VectorcallTstate
+   fun:PyObject_Vectorcall
+   fun:call_function
+   fun:_PyEval_EvalFrameDefault
+   fun:_PyEval_EvalFrame
+   fun:function_code_fastcall
+}
+
+{
+   Python leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyMem_RawMalloc
+   fun:PyThread_allocate_lock
+   fun:newlockobject
+   ...
+   fun:cfunction_vectorcall_NOARGS
+   fun:_PyObject_VectorcallTstate
+   fun:PyObject_Vectorcall
+   fun:call_function
+   fun:_PyEval_EvalFrameDefault
+   fun:_PyEval_EvalFrame
+   fun:function_code_fastcall
+   fun:_PyFunction_Vectorcall
+}
+
+{
+   Python leaks when spawning a subprocess
+   Memcheck:Leak
+   fun:malloc
+   fun:_PyMem_RawMalloc
+   fun:PyMem_RawMalloc
+   fun:PyThread_allocate_lock
+   fun:rlock_new
+   fun:type_call
+   fun:_PyObject_Call
+   fun:PyObject_Call
+   fun:do_call_core
+   fun:_PyEval_EvalFrameDefault
+   fun:_PyEval_EvalFrame
+   fun:_PyEval_EvalCode
+   fun:_PyFunction_Vectorcall
+}
+
+# Not really CPython-specific, see link
+{
+   dlopen leak (https://stackoverflow.com/questions/1542457/memory-leak-reported-by-valgrind-in-dlopen)
+   Memcheck:Leak
+   fun:malloc
+   ...
+   fun:dl_open_worker
+   fun:_dl_catch_exception
+   fun:_dl_open
+   fun:dlopen_doit
+   fun:_dl_catch_exception
+   fun:_dl_catch_error
+   fun:_dlerror_run
+   fun:dlopen@@GLIBC_2.2.5
+   fun:_PyImport_FindSharedFuncptr
+   fun:_PyImport_LoadDynamicModuleWithSpec
+}
diff --git a/3rdparty/pybind11/tools/FindCatch.cmake b/3rdparty/pybind11/tools/FindCatch.cmake
index 4d6bffcf68..57bba58b30 100644
--- a/3rdparty/pybind11/tools/FindCatch.cmake
+++ b/3rdparty/pybind11/tools/FindCatch.cmake
@@ -9,6 +9,8 @@
 #  CATCH_INCLUDE_DIR      - path to catch.hpp
 #  CATCH_VERSION          - version number
 
+option(DOWNLOAD_CATCH "Download catch2 if not found")
+
 if(NOT Catch_FIND_VERSION)
   message(FATAL_ERROR "A version number must be specified.")
 elseif(Catch_FIND_REQUIRED)
diff --git a/3rdparty/pybind11/tools/FindEigen3.cmake b/3rdparty/pybind11/tools/FindEigen3.cmake
index 98ab43d9e6..83625d92e0 100644
--- a/3rdparty/pybind11/tools/FindEigen3.cmake
+++ b/3rdparty/pybind11/tools/FindEigen3.cmake
@@ -64,6 +64,9 @@ if(EIGEN3_INCLUDE_DIR)
   set(EIGEN3_FOUND ${EIGEN3_VERSION_OK})
 
 else(EIGEN3_INCLUDE_DIR)
+  if(NOT DEFINED KDE4_INCLUDE_DIR)
+    set(KDE4_INCLUDE_DIR "")
+  endif()
 
   find_path(
     EIGEN3_INCLUDE_DIR
diff --git a/3rdparty/pybind11/tools/FindPythonLibsNew.cmake b/3rdparty/pybind11/tools/FindPythonLibsNew.cmake
index b7125912c8..a5a628fd7a 100644
--- a/3rdparty/pybind11/tools/FindPythonLibsNew.cmake
+++ b/3rdparty/pybind11/tools/FindPythonLibsNew.cmake
@@ -57,6 +57,8 @@ endif()
 
 if(PythonLibsNew_FIND_QUIETLY)
   set(_pythonlibs_quiet QUIET)
+else()
+  set(_pythonlibs_quiet "")
 endif()
 
 if(PythonLibsNew_FIND_REQUIRED)
@@ -90,7 +92,7 @@ endif()
 
 # Use the Python interpreter to find the libs.
 if(NOT PythonLibsNew_FIND_VERSION)
-  set(PythonLibsNew_FIND_VERSION "")
+  set(PythonLibsNew_FIND_VERSION "3.6")
 endif()
 
 find_package(PythonInterp ${PythonLibsNew_FIND_VERSION} ${_pythonlibs_required}
@@ -110,12 +112,26 @@ endif()
 # VERSION. VERSION will typically be like "2.7" on unix, and "27" on windows.
 execute_process(
   COMMAND
-    "${PYTHON_EXECUTABLE}" "-c" "from distutils import sysconfig as s;import sys;import struct;
+    "${PYTHON_EXECUTABLE}" "-c" "
+import sys;import struct;
+import sysconfig as s
+USE_SYSCONFIG = sys.version_info >= (3, 10)
+if not USE_SYSCONFIG:
+    from distutils import sysconfig as ds
 print('.'.join(str(v) for v in sys.version_info));
 print(sys.prefix);
-print(s.get_python_inc(plat_specific=True));
-print(s.get_python_lib(plat_specific=True));
-print(s.get_config_var('EXT_SUFFIX') or s.get_config_var('SO'));
+if USE_SYSCONFIG:
+    scheme = s.get_default_scheme()
+    if scheme == 'posix_local':
+        # Debian's default scheme installs to /usr/local/ but we want to find headers in /usr/
+        scheme = 'posix_prefix'
+    print(s.get_path('platinclude', scheme))
+    print(s.get_path('platlib'))
+    print(s.get_config_var('EXT_SUFFIX') or s.get_config_var('SO'))
+else:
+    print(ds.get_python_inc(plat_specific=True));
+    print(ds.get_python_lib(plat_specific=True));
+    print(ds.get_config_var('EXT_SUFFIX') or ds.get_config_var('SO'));
 print(hasattr(sys, 'gettotalrefcount')+0);
 print(struct.calcsize('@P'));
 print(s.get_config_var('LDVERSION') or s.get_config_var('VERSION'));
@@ -135,26 +151,36 @@ if(NOT _PYTHON_SUCCESS MATCHES 0)
   return()
 endif()
 
+# Can manually set values when cross-compiling
+macro(_PYBIND11_GET_IF_UNDEF lst index name)
+  if(NOT DEFINED "${name}")
+    list(GET "${lst}" "${index}" "${name}")
+  endif()
+endmacro()
+
 # Convert the process output into a list
 if(WIN32)
   string(REGEX REPLACE "\\\\" "/" _PYTHON_VALUES ${_PYTHON_VALUES})
 endif()
 string(REGEX REPLACE ";" "\\\\;" _PYTHON_VALUES ${_PYTHON_VALUES})
 string(REGEX REPLACE "\n" ";" _PYTHON_VALUES ${_PYTHON_VALUES})
-list(GET _PYTHON_VALUES 0 _PYTHON_VERSION_LIST)
-list(GET _PYTHON_VALUES 1 PYTHON_PREFIX)
-list(GET _PYTHON_VALUES 2 PYTHON_INCLUDE_DIR)
-list(GET _PYTHON_VALUES 3 PYTHON_SITE_PACKAGES)
-list(GET _PYTHON_VALUES 4 PYTHON_MODULE_EXTENSION)
-list(GET _PYTHON_VALUES 5 PYTHON_IS_DEBUG)
-list(GET _PYTHON_VALUES 6 PYTHON_SIZEOF_VOID_P)
-list(GET _PYTHON_VALUES 7 PYTHON_LIBRARY_SUFFIX)
-list(GET _PYTHON_VALUES 8 PYTHON_LIBDIR)
-list(GET _PYTHON_VALUES 9 PYTHON_MULTIARCH)
+_pybind11_get_if_undef(_PYTHON_VALUES 0 _PYTHON_VERSION_LIST)
+_pybind11_get_if_undef(_PYTHON_VALUES 1 PYTHON_PREFIX)
+_pybind11_get_if_undef(_PYTHON_VALUES 2 PYTHON_INCLUDE_DIR)
+_pybind11_get_if_undef(_PYTHON_VALUES 3 PYTHON_SITE_PACKAGES)
+_pybind11_get_if_undef(_PYTHON_VALUES 4 PYTHON_MODULE_EXTENSION)
+_pybind11_get_if_undef(_PYTHON_VALUES 5 PYTHON_IS_DEBUG)
+_pybind11_get_if_undef(_PYTHON_VALUES 6 PYTHON_SIZEOF_VOID_P)
+_pybind11_get_if_undef(_PYTHON_VALUES 7 PYTHON_LIBRARY_SUFFIX)
+_pybind11_get_if_undef(_PYTHON_VALUES 8 PYTHON_LIBDIR)
+_pybind11_get_if_undef(_PYTHON_VALUES 9 PYTHON_MULTIARCH)
 
 # Make sure the Python has the same pointer-size as the chosen compiler
 # Skip if CMAKE_SIZEOF_VOID_P is not defined
-if(CMAKE_SIZEOF_VOID_P AND (NOT "${PYTHON_SIZEOF_VOID_P}" STREQUAL "${CMAKE_SIZEOF_VOID_P}"))
+# This should be skipped for (non-Apple) cross-compiles (like EMSCRIPTEN)
+if(NOT CMAKE_CROSSCOMPILING
+   AND CMAKE_SIZEOF_VOID_P
+   AND (NOT "${PYTHON_SIZEOF_VOID_P}" STREQUAL "${CMAKE_SIZEOF_VOID_P}"))
   if(PythonLibsNew_FIND_REQUIRED)
     math(EXPR _PYTHON_BITS "${PYTHON_SIZEOF_VOID_P} * 8")
     math(EXPR _CMAKE_BITS "${CMAKE_SIZEOF_VOID_P} * 8")
diff --git a/3rdparty/pybind11/tools/JoinPaths.cmake b/3rdparty/pybind11/tools/JoinPaths.cmake
new file mode 100644
index 0000000000..c68d91b84d
--- /dev/null
+++ b/3rdparty/pybind11/tools/JoinPaths.cmake
@@ -0,0 +1,23 @@
+# This module provides function for joining paths
+# known from most languages
+#
+# SPDX-License-Identifier: (MIT OR CC0-1.0)
+# Copyright 2020 Jan Tojnar
+# https://github.com/jtojnar/cmake-snips
+#
+# Modelled after Python’s os.path.join
+# https://docs.python.org/3.7/library/os.path.html#os.path.join
+# Windows not supported
+function(join_paths joined_path first_path_segment)
+    set(temp_path "${first_path_segment}")
+    foreach(current_segment IN LISTS ARGN)
+        if(NOT ("${current_segment}" STREQUAL ""))
+            if(IS_ABSOLUTE "${current_segment}")
+                set(temp_path "${current_segment}")
+            else()
+                set(temp_path "${temp_path}/${current_segment}")
+            endif()
+        endif()
+    endforeach()
+    set(${joined_path} "${temp_path}" PARENT_SCOPE)
+endfunction()
diff --git a/3rdparty/pybind11/tools/check-style.sh b/3rdparty/pybind11/tools/check-style.sh
index f7af2a4169..6d832523a7 100755
--- a/3rdparty/pybind11/tools/check-style.sh
+++ b/3rdparty/pybind11/tools/check-style.sh
@@ -16,11 +16,11 @@ check_style_errors=0
 IFS=$'\n'
 
 
-found="$(grep '\<\(if\|for\|while\|catch\)(\|){' $@ -rn --color=always)"
+found="$(grep '\<\(if\|for\|while\|catch\)(\|){' "$@" -rn --color=always)"
 if [ -n "$found" ]; then
     echo -e '\033[31;01mError: found the following coding style problems:\033[0m'
     check_style_errors=1
-    echo "$found" | sed -e 's/^/    /'
+    echo "${found//^/    /}"
 fi
 
 found="$(awk '
@@ -34,7 +34,7 @@ last && /^\s*{/ {
     last=""
 }
 { last = /(if|for|while|catch|switch)\s*\(.*\)\s*$/ ? $0 : "" }
-' $(find include -type f) $@)"
+' "$(find include -type f)" "$@")"
 if [ -n "$found" ]; then
     check_style_errors=1
     echo -e '\033[31;01mError: braces should occur on the same line as the if/while/.. statement. Found issues in the following files:\033[0m'
diff --git a/3rdparty/pybind11/tools/codespell_ignore_lines_from_errors.py b/3rdparty/pybind11/tools/codespell_ignore_lines_from_errors.py
new file mode 100644
index 0000000000..5403ec3ad0
--- /dev/null
+++ b/3rdparty/pybind11/tools/codespell_ignore_lines_from_errors.py
@@ -0,0 +1,35 @@
+"""Simple script for rebuilding .codespell-ignore-lines
+
+Usage:
+
+cat < /dev/null > .codespell-ignore-lines
+pre-commit run --all-files codespell >& /tmp/codespell_errors.txt
+python3 tools/codespell_ignore_lines_from_errors.py /tmp/codespell_errors.txt > .codespell-ignore-lines
+
+git diff to review changes, then commit, push.
+"""
+
+import sys
+from typing import List
+
+
+def run(args: List[str]) -> None:
+    assert len(args) == 1, "codespell_errors.txt"
+    cache = {}
+    done = set()
+    for line in sorted(open(args[0]).read().splitlines()):
+        i = line.find(" ==> ")
+        if i > 0:
+            flds = line[:i].split(":")
+            if len(flds) >= 2:
+                filename, line_num = flds[:2]
+                if filename not in cache:
+                    cache[filename] = open(filename).read().splitlines()
+                supp = cache[filename][int(line_num) - 1]
+                if supp not in done:
+                    print(supp)
+                    done.add(supp)
+
+
+if __name__ == "__main__":
+    run(args=sys.argv[1:])
diff --git a/3rdparty/pybind11/tools/libsize.py b/3rdparty/pybind11/tools/libsize.py
index 589c317f0d..1ac9afbe81 100644
--- a/3rdparty/pybind11/tools/libsize.py
+++ b/3rdparty/pybind11/tools/libsize.py
@@ -1,5 +1,3 @@
-# -*- coding: utf-8 -*-
-from __future__ import print_function, division
 import os
 import sys
 
@@ -15,7 +13,7 @@
 save = sys.argv[2]
 
 if not os.path.exists(lib):
-    sys.exit("Error: requested file ({}) does not exist".format(lib))
+    sys.exit(f"Error: requested file ({lib}) does not exist")
 
 libsize = os.path.getsize(lib)
 
@@ -30,7 +28,7 @@
         if change == 0:
             print(" (no change)")
         else:
-            print(" (change of {:+} bytes = {:+.2%})".format(change, change / oldsize))
+            print(f" (change of {change:+} bytes = {change / oldsize:+.2%})")
 else:
     print()
 
diff --git a/3rdparty/pybind11/tools/make_changelog.py b/3rdparty/pybind11/tools/make_changelog.py
new file mode 100755
index 0000000000..839040a938
--- /dev/null
+++ b/3rdparty/pybind11/tools/make_changelog.py
@@ -0,0 +1,63 @@
+#!/usr/bin/env python3
+
+import re
+
+import ghapi.all
+from rich import print
+from rich.syntax import Syntax
+
+ENTRY = re.compile(
+    r"""
+    Suggested \s changelog \s entry:
+    .*
+    ```rst
+    \s*
+    (.*?)
+    \s*
+    ```
+""",
+    re.DOTALL | re.VERBOSE,
+)
+
+print()
+
+
+api = ghapi.all.GhApi(owner="pybind", repo="pybind11")
+
+issues_pages = ghapi.page.paged(
+    api.issues.list_for_repo, labels="needs changelog", state="closed"
+)
+issues = (issue for page in issues_pages for issue in page)
+missing = []
+
+for issue in issues:
+    changelog = ENTRY.findall(issue.body)
+    if changelog:
+        (msg,) = changelog
+        if not msg.startswith("* "):
+            msg = "* " + msg
+        if not msg.endswith("."):
+            msg += "."
+
+        msg += f"\n  `#{issue.number} <{issue.html_url}>`_"
+
+        print(Syntax(msg, "rst", theme="ansi_light", word_wrap=True))
+        print()
+
+    else:
+        missing.append(issue)
+
+if missing:
+    print()
+    print("[blue]" + "-" * 30)
+    print()
+
+    for issue in missing:
+        print(f"[red bold]Missing:[/red bold][red] {issue.title}")
+        print(f"[red]  {issue.html_url}\n")
+
+    print("[bold]Template:\n")
+    msg = "## Suggested changelog entry:\n\n```rst\n\n```"
+    print(Syntax(msg, "md", theme="ansi_light"))
+
+print()
diff --git a/3rdparty/pybind11/tools/pybind11.pc.in b/3rdparty/pybind11/tools/pybind11.pc.in
new file mode 100644
index 0000000000..402f0b357d
--- /dev/null
+++ b/3rdparty/pybind11/tools/pybind11.pc.in
@@ -0,0 +1,7 @@
+prefix=@prefix_for_pc_file@
+includedir=@includedir_for_pc_file@
+
+Name: @PROJECT_NAME@
+Description: Seamless operability between C++11 and Python
+Version: @PROJECT_VERSION@
+Cflags: -I${includedir}
diff --git a/3rdparty/pybind11/tools/pybind11Common.cmake b/3rdparty/pybind11/tools/pybind11Common.cmake
index 3c05c682dd..e1fb601acc 100644
--- a/3rdparty/pybind11/tools/pybind11Common.cmake
+++ b/3rdparty/pybind11/tools/pybind11Common.cmake
@@ -8,7 +8,6 @@ Adds the following targets::
     pybind11::lto - Link time optimizations (manual selection)
     pybind11::thin_lto - Link time optimizations (manual selection)
     pybind11::python_link_helper - Adds link to Python libraries
-    pybind11::python2_no_register - Avoid warning/error with Python 2 + C++14/7
     pybind11::windows_extras - MSVC bigobj and mp for building multithreaded
     pybind11::opt_size - avoid optimizations that increase code size
 
@@ -20,6 +19,7 @@ Adds the following functions::
 #]======================================================]
 
 # CMake 3.10 has an include_guard command, but we can't use that yet
+# include_guard(global) (pre-CMake 3.10)
 if(TARGET pybind11::lto)
   return()
 endif()
@@ -65,31 +65,6 @@ set_property(
   APPEND
   PROPERTY INTERFACE_LINK_LIBRARIES pybind11::pybind11)
 
-# ----------------------- no register ----------------------
-
-# Workaround for Python 2.7 and C++17 (C++14 as a warning) incompatibility
-# This adds the flags -Wno-register and -Wno-deprecated-register if the compiler
-# is Clang 3.9+ or AppleClang and the compile language is CXX, or /wd5033 for MSVC (all languages,
-# since MSVC didn't recognize COMPILE_LANGUAGE until CMake 3.11+).
-
-add_library(pybind11::python2_no_register INTERFACE IMPORTED ${optional_global})
-set(clang_4plus
-    "$<AND:$<CXX_COMPILER_ID:Clang>,$<NOT:$<VERSION_LESS:$<CXX_COMPILER_VERSION>,3.9>>>")
-set(no_register "$<OR:${clang_4plus},$<CXX_COMPILER_ID:AppleClang>>")
-
-if(MSVC AND CMAKE_VERSION VERSION_LESS 3.11)
-  set(cxx_no_register "${no_register}")
-else()
-  set(cxx_no_register "$<AND:$<COMPILE_LANGUAGE:CXX>,${no_register}>")
-endif()
-
-set(msvc "$<CXX_COMPILER_ID:MSVC>")
-
-set_property(
-  TARGET pybind11::python2_no_register
-  PROPERTY INTERFACE_COMPILE_OPTIONS
-           "$<${cxx_no_register}:-Wno-register;-Wno-deprecated-register>" "$<${msvc}:/wd5033>")
-
 # --------------------------- link helper ---------------------------
 
 add_library(pybind11::python_link_helper IMPORTED INTERFACE ${optional_global})
@@ -115,28 +90,32 @@ endif()
 
 add_library(pybind11::windows_extras IMPORTED INTERFACE ${optional_global})
 
-if(MSVC)
-  # /MP enables multithreaded builds (relevant when there are many files), /bigobj is
-  # needed for bigger binding projects due to the limit to 64k addressable sections
+if(MSVC) # That's also clang-cl
+  # /bigobj is needed for bigger binding projects due to the limit to 64k
+  # addressable sections
   set_property(
     TARGET pybind11::windows_extras
     APPEND
-    PROPERTY INTERFACE_COMPILE_OPTIONS /bigobj)
+    PROPERTY INTERFACE_COMPILE_OPTIONS $<$<COMPILE_LANGUAGE:CXX>:/bigobj>)
 
-  if(CMAKE_VERSION VERSION_LESS 3.11)
-    set_property(
-      TARGET pybind11::windows_extras
-      APPEND
-      PROPERTY INTERFACE_COMPILE_OPTIONS $<$<NOT:$<CONFIG:Debug>>:/MP>)
-  else()
-    # Only set these options for C++ files.  This is important so that, for
-    # instance, projects that include other types of source files like CUDA
-    # .cu files don't get these options propagated to nvcc since that would
-    # cause the build to fail.
-    set_property(
-      TARGET pybind11::windows_extras
-      APPEND
-      PROPERTY INTERFACE_COMPILE_OPTIONS $<$<NOT:$<CONFIG:Debug>>:$<$<COMPILE_LANGUAGE:CXX>:/MP>>)
+  # /MP enables multithreaded builds (relevant when there are many files) for MSVC
+  if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") # no Clang no Intel
+    if(CMAKE_VERSION VERSION_LESS 3.11)
+      set_property(
+        TARGET pybind11::windows_extras
+        APPEND
+        PROPERTY INTERFACE_COMPILE_OPTIONS $<$<NOT:$<CONFIG:Debug>>:/MP>)
+    else()
+      # Only set these options for C++ files.  This is important so that, for
+      # instance, projects that include other types of source files like CUDA
+      # .cu files don't get these options propagated to nvcc since that would
+      # cause the build to fail.
+      set_property(
+        TARGET pybind11::windows_extras
+        APPEND
+        PROPERTY INTERFACE_COMPILE_OPTIONS
+                 $<$<NOT:$<CONFIG:Debug>>:$<$<COMPILE_LANGUAGE:CXX>:/MP>>)
+    endif()
   endif()
 endif()
 
@@ -298,23 +277,36 @@ function(_pybind11_return_if_cxx_and_linker_flags_work result cxxflags linkerfla
 endfunction()
 
 function(_pybind11_generate_lto target prefer_thin_lto)
+  if(MINGW)
+    message(STATUS "${target} disabled (problems with undefined symbols for MinGW for now)")
+    return()
+  endif()
+
   if(CMAKE_CXX_COMPILER_ID MATCHES "GNU|Clang")
     set(cxx_append "")
     set(linker_append "")
     if(CMAKE_CXX_COMPILER_ID MATCHES "Clang" AND NOT APPLE)
       # Clang Gold plugin does not support -Os; append -O3 to MinSizeRel builds to override it
       set(linker_append ";$<$<CONFIG:MinSizeRel>:-O3>")
-    elseif(CMAKE_CXX_COMPILER_ID MATCHES "GNU")
+    elseif(CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND NOT MINGW)
       set(cxx_append ";-fno-fat-lto-objects")
     endif()
 
-    if(CMAKE_CXX_COMPILER_ID MATCHES "Clang" AND prefer_thin_lto)
+    if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le" OR CMAKE_SYSTEM_PROCESSOR MATCHES "mips64")
+      set(NO_FLTO_ARCH TRUE)
+    else()
+      set(NO_FLTO_ARCH FALSE)
+    endif()
+
+    if(CMAKE_CXX_COMPILER_ID MATCHES "Clang"
+       AND prefer_thin_lto
+       AND NOT NO_FLTO_ARCH)
       _pybind11_return_if_cxx_and_linker_flags_work(
         HAS_FLTO_THIN "-flto=thin${cxx_append}" "-flto=thin${linker_append}"
         PYBIND11_LTO_CXX_FLAGS PYBIND11_LTO_LINKER_FLAGS)
     endif()
 
-    if(NOT HAS_FLTO_THIN)
+    if(NOT HAS_FLTO_THIN AND NOT NO_FLTO_ARCH)
       _pybind11_return_if_cxx_and_linker_flags_work(
         HAS_FLTO "-flto${cxx_append}" "-flto${linker_append}" PYBIND11_LTO_CXX_FLAGS
         PYBIND11_LTO_LINKER_FLAGS)
diff --git a/3rdparty/pybind11/tools/pybind11Config.cmake.in b/3rdparty/pybind11/tools/pybind11Config.cmake.in
index 9808f3d255..9383e8c671 100644
--- a/3rdparty/pybind11/tools/pybind11Config.cmake.in
+++ b/3rdparty/pybind11/tools/pybind11Config.cmake.in
@@ -13,7 +13,7 @@ This module sets the following variables in your project:
 ``pybind11_VERSION``
   pybind11 version in format Major.Minor.Release
 ``pybind11_VERSION_TYPE``
-  pybind11 version type (dev, release)
+  pybind11 version type (``dev*`` or empty for a release)
 ``pybind11_INCLUDE_DIRS``
   Directories where pybind11 and python headers are located.
 ``pybind11_INCLUDE_DIR``
@@ -51,8 +51,6 @@ complex applications, and they are available in all modes:
   Python headers too.
 ``pybind11::python_link_helper``
   Just the "linking" part of ``pybind11:module``, for CMake < 3.15.
-``pybind11::python2_no_register``
-  Quiets the warning/error when mixing C++14+ and Python 2, also included in ``pybind11::module``.
 ``pybind11::thin_lto``
   An alternative to ``INTERPROCEDURAL_OPTIMIZATION``.
 ``pybind11::lto``
@@ -87,8 +85,8 @@ you can either use the basic targets, or use the FindPython tools:
   target_link_libraries(MyModule2 pybind11::headers)
   set_target_properties(MyModule2 PROPERTIES
                                   INTERPROCEDURAL_OPTIMIZATION ON
-                                  CXX__VISIBILITY_PRESET ON
-                                  VISIBLITY_INLINES_HIDDEN ON)
+                                  CXX_VISIBILITY_PRESET ON
+                                  VISIBILITY_INLINES_HIDDEN ON)
 
 If you build targets yourself, you may be interested in stripping the output
 for reduced size; this is the one other feature that the helper function gives you.
@@ -139,7 +137,7 @@ This module defines the following commands to assist with creating Python module
 
   pybind11_add_module(<target>
     [STATIC|SHARED|MODULE]
-    [THIN_LTO] [OPT_SIZE] [NO_EXTRAS] [WITHOUT_SOBAI]
+    [THIN_LTO] [OPT_SIZE] [NO_EXTRAS] [WITHOUT_SOABI]
     <files>...
     )
 
@@ -147,7 +145,7 @@ Add a module and setup all helpers. You can select the type of the library; the
 default is ``MODULE``. There are several options:
 
 ``OPT_SIZE``
-  Optimize for size, even if the ``CMAKE_BUILD_TYPE`` is not ``RelSize``.
+  Optimize for size, even if the ``CMAKE_BUILD_TYPE`` is not ``MinSizeRel``.
 ``THIN_LTO``
   Use thin TLO instead of regular if there's a choice (pybind11's selection
   is disabled if ``CMAKE_INTERPROCEDURAL_OPTIMIZATIONS`` is set).
@@ -195,13 +193,14 @@ Using ``find_package`` with version info is not recommended except for release v
 .. code-block:: cmake
 
   find_package(pybind11 CONFIG)
-  find_package(pybind11 2.0 EXACT CONFIG REQUIRED)
+  find_package(pybind11 2.9 EXACT CONFIG REQUIRED)
 
 #]=============================================================================]
 @PACKAGE_INIT@
 
 # Location of pybind11/pybind11.h
-set(pybind11_INCLUDE_DIR "${PACKAGE_PREFIX_DIR}/@CMAKE_INSTALL_INCLUDEDIR@")
+# This will be relative unless explicitly set as absolute
+set(pybind11_INCLUDE_DIR "@pybind11_INCLUDEDIR@")
 
 set(pybind11_LIBRARY "")
 set(pybind11_DEFINITIONS USING_pybind11)
@@ -227,6 +226,6 @@ include("${CMAKE_CURRENT_LIST_DIR}/pybind11Common.cmake")
 if(NOT pybind11_FIND_QUIETLY)
   message(
     STATUS
-      "Found pybind11: ${pybind11_INCLUDE_DIR} (found version \"${pybind11_VERSION}\" ${pybind11_VERSION_TYPE})"
+      "Found pybind11: ${pybind11_INCLUDE_DIR} (found version \"${pybind11_VERSION}${pybind11_VERSION_TYPE}\")"
   )
 endif()
diff --git a/3rdparty/pybind11/tools/pybind11NewTools.cmake b/3rdparty/pybind11/tools/pybind11NewTools.cmake
index 357cc61c13..9e13daf1a1 100644
--- a/3rdparty/pybind11/tools/pybind11NewTools.cmake
+++ b/3rdparty/pybind11/tools/pybind11NewTools.cmake
@@ -5,6 +5,12 @@
 # All rights reserved. Use of this source code is governed by a
 # BSD-style license that can be found in the LICENSE file.
 
+if(CMAKE_VERSION VERSION_LESS 3.12)
+  message(FATAL_ERROR "You cannot use the new FindPython module with CMake < 3.12")
+endif()
+
+include_guard(GLOBAL)
+
 get_property(
   is_config
   TARGET pybind11::headers
@@ -12,15 +18,11 @@ get_property(
 
 if(pybind11_FIND_QUIETLY)
   set(_pybind11_quiet QUIET)
+else()
+  set(_pybind11_quiet "")
 endif()
 
-if(CMAKE_VERSION VERSION_LESS 3.12)
-  message(FATAL_ERROR "You cannot use the new FindPython module with CMake < 3.12")
-endif()
-
-if(NOT Python_FOUND
-   AND NOT Python3_FOUND
-   AND NOT Python2_FOUND)
+if(NOT Python_FOUND AND NOT Python3_FOUND)
   if(NOT DEFINED Python_FIND_IMPLEMENTATIONS)
     set(Python_FIND_IMPLEMENTATIONS CPython PyPy)
   endif()
@@ -30,7 +32,7 @@ if(NOT Python_FOUND
     set(Python_ROOT_DIR "$ENV{pythonLocation}")
   endif()
 
-  find_package(Python REQUIRED COMPONENTS Interpreter Development ${_pybind11_quiet})
+  find_package(Python 3.6 REQUIRED COMPONENTS Interpreter Development ${_pybind11_quiet})
 
   # If we are in submodule mode, export the Python targets to global targets.
   # If this behavior is not desired, FindPython _before_ pybind11.
@@ -47,19 +49,10 @@ if(Python_FOUND)
   set(_Python
       Python
       CACHE INTERNAL "" FORCE)
-elseif(Python3_FOUND AND NOT Python2_FOUND)
+elseif(Python3_FOUND)
   set(_Python
       Python3
       CACHE INTERNAL "" FORCE)
-elseif(Python2_FOUND AND NOT Python3_FOUND)
-  set(_Python
-      Python2
-      CACHE INTERNAL "" FORCE)
-else()
-  message(AUTHOR_WARNING "Python2 and Python3 both present, pybind11 in "
-                         "PYBIND11_NOPYTHON mode (manually activate to silence warning)")
-  set(_pybind11_nopython ON)
-  return()
 endif()
 
 if(PYBIND11_MASTER_PROJECT)
@@ -80,6 +73,15 @@ if(NOT DEFINED ${_Python}_EXECUTABLE)
 
 endif()
 
+if(NOT ${_Python}_EXECUTABLE STREQUAL PYBIND11_PYTHON_EXECUTABLE_LAST)
+  # Detect changes to the Python version/binary in subsequent CMake runs, and refresh config if needed
+  unset(PYTHON_IS_DEBUG CACHE)
+  unset(PYTHON_MODULE_EXTENSION CACHE)
+  set(PYBIND11_PYTHON_EXECUTABLE_LAST
+      "${${_Python}_EXECUTABLE}"
+      CACHE INTERNAL "Python executable during the last CMake run")
+endif()
+
 if(NOT DEFINED PYTHON_IS_DEBUG)
   # Debug check - see https://stackoverflow.com/questions/646518/python-how-to-detect-debug-Interpreter
   execute_process(
@@ -97,7 +99,7 @@ if(NOT DEFINED PYTHON_MODULE_EXTENSION)
   execute_process(
     COMMAND
       "${${_Python}_EXECUTABLE}" "-c"
-      "from distutils import sysconfig as s;print(s.get_config_var('EXT_SUFFIX') or s.get_config_var('SO'))"
+      "import sys, importlib; s = importlib.import_module('distutils.sysconfig' if sys.version_info < (3, 10) else 'sysconfig'); print(s.get_config_var('EXT_SUFFIX') or s.get_config_var('SO'))"
     OUTPUT_VARIABLE _PYTHON_MODULE_EXTENSION
     ERROR_VARIABLE _PYTHON_MODULE_EXTENSION_ERR
     OUTPUT_STRIP_TRAILING_WHITESPACE)
@@ -124,31 +126,34 @@ if(PYTHON_IS_DEBUG)
     PROPERTY INTERFACE_COMPILE_DEFINITIONS Py_DEBUG)
 endif()
 
-# Check on every access - since Python2 and Python3 could have been used - do nothing in that case.
+# Check on every access - since Python can change - do nothing in that case.
 
 if(DEFINED ${_Python}_INCLUDE_DIRS)
+  # Only add Python for build - must be added during the import for config
+  # since it has to be re-discovered.
+  #
+  # This needs to be a target to be included after the local pybind11
+  # directory, just in case there there is an installed pybind11 sitting
+  # next to Python's includes. It also ensures Python is a SYSTEM library.
+  add_library(pybind11::python_headers INTERFACE IMPORTED)
+  set_property(
+    TARGET pybind11::python_headers PROPERTY INTERFACE_INCLUDE_DIRECTORIES
+                                             "$<BUILD_INTERFACE:${${_Python}_INCLUDE_DIRS}>")
   set_property(
     TARGET pybind11::pybind11
     APPEND
-    PROPERTY INTERFACE_INCLUDE_DIRECTORIES $<BUILD_INTERFACE:${${_Python}_INCLUDE_DIRS}>)
+    PROPERTY INTERFACE_LINK_LIBRARIES pybind11::python_headers)
   set(pybind11_INCLUDE_DIRS
       "${pybind11_INCLUDE_DIR}" "${${_Python}_INCLUDE_DIRS}"
       CACHE INTERNAL "Directories where pybind11 and possibly Python headers are located")
 endif()
 
-if(DEFINED ${_Python}_VERSION AND ${_Python}_VERSION VERSION_LESS 3)
-  set_property(
-    TARGET pybind11::pybind11
-    APPEND
-    PROPERTY INTERFACE_LINK_LIBRARIES pybind11::python2_no_register)
-endif()
-
 # In CMake 3.18+, you can find these separately, so include an if
-if(TARGET ${_Python}::${_Python})
+if(TARGET ${_Python}::Python)
   set_property(
     TARGET pybind11::embed
     APPEND
-    PROPERTY INTERFACE_LINK_LIBRARIES ${_Python}::${_Python})
+    PROPERTY INTERFACE_LINK_LIBRARIES ${_Python}::Python)
 endif()
 
 # CMake 3.15+ has this
@@ -170,27 +175,25 @@ function(pybind11_add_module target_name)
   cmake_parse_arguments(PARSE_ARGV 1 ARG
                         "STATIC;SHARED;MODULE;THIN_LTO;OPT_SIZE;NO_EXTRAS;WITHOUT_SOABI" "" "")
 
-  if(ARG_ADD_LIBRARY_STATIC)
-    set(type STATIC)
-  elseif(ARG_ADD_LIBRARY_SHARED)
-    set(type SHARED)
+  if(ARG_STATIC)
+    set(lib_type STATIC)
+  elseif(ARG_SHARED)
+    set(lib_type SHARED)
   else()
-    set(type MODULE)
+    set(lib_type MODULE)
   endif()
 
   if("${_Python}" STREQUAL "Python")
-    python_add_library(${target_name} ${type} ${ARG_UNPARSED_ARGUMENTS})
+    python_add_library(${target_name} ${lib_type} ${ARG_UNPARSED_ARGUMENTS})
   elseif("${_Python}" STREQUAL "Python3")
-    python3_add_library(${target_name} ${type} ${ARG_UNPARSED_ARGUMENTS})
-  elseif("${_Python}" STREQUAL "Python2")
-    python2_add_library(${target_name} ${type} ${ARG_UNPARSED_ARGUMENTS})
+    python3_add_library(${target_name} ${lib_type} ${ARG_UNPARSED_ARGUMENTS})
   else()
     message(FATAL_ERROR "Cannot detect FindPython version: ${_Python}")
   endif()
 
   target_link_libraries(${target_name} PRIVATE pybind11::headers)
 
-  if(type STREQUAL "MODULE")
+  if(lib_type STREQUAL "MODULE")
     target_link_libraries(${target_name} PRIVATE pybind11::module)
   else()
     target_link_libraries(${target_name} PRIVATE pybind11::embed)
@@ -200,16 +203,21 @@ function(pybind11_add_module target_name)
     target_link_libraries(${target_name} PRIVATE pybind11::windows_extras)
   endif()
 
-  if(DEFINED ${_Python}_VERSION AND ${_Python}_VERSION VERSION_LESS 3)
-    target_link_libraries(${target_name} PRIVATE pybind11::python2_no_register)
+  # -fvisibility=hidden is required to allow multiple modules compiled against
+  # different pybind versions to work properly, and for some features (e.g.
+  # py::module_local).  We force it on everything inside the `pybind11`
+  # namespace; also turning it on for a pybind module compilation here avoids
+  # potential warnings or issues from having mixed hidden/non-hidden types.
+  if(NOT DEFINED CMAKE_CXX_VISIBILITY_PRESET)
+    set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET "hidden")
   endif()
 
-  set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET "hidden"
-                                                  CUDA_VISIBILITY_PRESET "hidden")
+  if(NOT DEFINED CMAKE_CUDA_VISIBILITY_PRESET)
+    set_target_properties(${target_name} PROPERTIES CUDA_VISIBILITY_PRESET "hidden")
+  endif()
 
   # If we don't pass a WITH_SOABI or WITHOUT_SOABI, use our own default handling of extensions
-  if("${type}" STREQUAL "MODULE" AND (NOT ARG_WITHOUT_SOABI OR NOT "WITH_SOABI" IN_LIST
-                                                               ARG_UNPARSED_ARGUMENTS))
+  if(NOT ARG_WITHOUT_SOABI AND NOT "WITH_SOABI" IN_LIST ARG_UNPARSED_ARGUMENTS)
     pybind11_extension(${target_name})
   endif()
 
@@ -225,7 +233,9 @@ function(pybind11_add_module target_name)
     endif()
   endif()
 
-  if(NOT MSVC AND NOT ${CMAKE_BUILD_TYPE} MATCHES Debug|RelWithDebInfo)
+  # Use case-insensitive comparison to match the result of $<CONFIG:cfgs>
+  string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE)
+  if(NOT MSVC AND NOT ${uppercase_CMAKE_BUILD_TYPE} MATCHES DEBUG|RELWITHDEBINFO)
     # Strip unnecessary sections of the binary on Linux/macOS
     pybind11_strip(${target_name})
   endif()
diff --git a/3rdparty/pybind11/tools/pybind11Tools.cmake b/3rdparty/pybind11/tools/pybind11Tools.cmake
index 23cff98e89..0dc61d3996 100644
--- a/3rdparty/pybind11/tools/pybind11Tools.cmake
+++ b/3rdparty/pybind11/tools/pybind11Tools.cmake
@@ -5,11 +5,18 @@
 # All rights reserved. Use of this source code is governed by a
 # BSD-style license that can be found in the LICENSE file.
 
+# include_guard(global) (pre-CMake 3.10)
+if(TARGET pybind11::python_headers)
+  return()
+endif()
+
 # Built-in in CMake 3.5+
 include(CMakeParseArguments)
 
 if(pybind11_FIND_QUIETLY)
   set(_pybind11_quiet QUIET)
+else()
+  set(_pybind11_quiet "")
 endif()
 
 # If this is the first run, PYTHON_VERSION can stand in for PYBIND11_PYTHON_VERSION
@@ -22,47 +29,46 @@ if(NOT DEFINED PYBIND11_PYTHON_VERSION AND DEFINED PYTHON_VERSION)
       CACHE STRING "Python version to use for compiling modules")
   unset(PYTHON_VERSION)
   unset(PYTHON_VERSION CACHE)
-else()
-  # If this is set as a normal variable, promote it, otherwise, make an empty cache variable.
+elseif(DEFINED PYBIND11_PYTHON_VERSION)
+  # If this is set as a normal variable, promote it
   set(PYBIND11_PYTHON_VERSION
       "${PYBIND11_PYTHON_VERSION}"
       CACHE STRING "Python version to use for compiling modules")
+else()
+  # Make an empty cache variable.
+  set(PYBIND11_PYTHON_VERSION
+      ""
+      CACHE STRING "Python version to use for compiling modules")
 endif()
 
 # A user can set versions manually too
 set(Python_ADDITIONAL_VERSIONS
-    "3.9;3.8;3.7;3.6;3.5;3.4"
+    "3.11;3.10;3.9;3.8;3.7;3.6"
     CACHE INTERNAL "")
 
 list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}")
 find_package(PythonLibsNew ${PYBIND11_PYTHON_VERSION} MODULE REQUIRED ${_pybind11_quiet})
 list(REMOVE_AT CMAKE_MODULE_PATH -1)
 
+# Makes a normal variable a cached variable
+macro(_PYBIND11_PROMOTE_TO_CACHE NAME)
+  set(_tmp_ptc "${${NAME}}")
+  # CMake 3.21 complains if a cached variable is shadowed by a normal one
+  unset(${NAME})
+  set(${NAME}
+      "${_tmp_ptc}"
+      CACHE INTERNAL "")
+endmacro()
+
 # Cache variables so pybind11_add_module can be used in parent projects
-set(PYTHON_INCLUDE_DIRS
-    ${PYTHON_INCLUDE_DIRS}
-    CACHE INTERNAL "")
-set(PYTHON_LIBRARIES
-    ${PYTHON_LIBRARIES}
-    CACHE INTERNAL "")
-set(PYTHON_MODULE_PREFIX
-    ${PYTHON_MODULE_PREFIX}
-    CACHE INTERNAL "")
-set(PYTHON_MODULE_EXTENSION
-    ${PYTHON_MODULE_EXTENSION}
-    CACHE INTERNAL "")
-set(PYTHON_VERSION_MAJOR
-    ${PYTHON_VERSION_MAJOR}
-    CACHE INTERNAL "")
-set(PYTHON_VERSION_MINOR
-    ${PYTHON_VERSION_MINOR}
-    CACHE INTERNAL "")
-set(PYTHON_VERSION
-    ${PYTHON_VERSION}
-    CACHE INTERNAL "")
-set(PYTHON_IS_DEBUG
-    "${PYTHON_IS_DEBUG}"
-    CACHE INTERNAL "")
+_pybind11_promote_to_cache(PYTHON_INCLUDE_DIRS)
+_pybind11_promote_to_cache(PYTHON_LIBRARIES)
+_pybind11_promote_to_cache(PYTHON_MODULE_PREFIX)
+_pybind11_promote_to_cache(PYTHON_MODULE_EXTENSION)
+_pybind11_promote_to_cache(PYTHON_VERSION_MAJOR)
+_pybind11_promote_to_cache(PYTHON_VERSION_MINOR)
+_pybind11_promote_to_cache(PYTHON_VERSION)
+_pybind11_promote_to_cache(PYTHON_IS_DEBUG)
 
 if(PYBIND11_MASTER_PROJECT)
   if(PYTHON_MODULE_EXTENSION MATCHES "pypy")
@@ -81,11 +87,19 @@ if(PYBIND11_MASTER_PROJECT)
   endif()
 endif()
 
-# Only add Python for build - must be added during the import for config since it has to be re-discovered.
+# Only add Python for build - must be added during the import for config since
+# it has to be re-discovered.
+#
+# This needs to be an target to it is included after the local pybind11
+# directory, just in case there are multiple versions of pybind11, we want the
+# one we expect.
+add_library(pybind11::python_headers INTERFACE IMPORTED)
+set_property(TARGET pybind11::python_headers PROPERTY INTERFACE_INCLUDE_DIRECTORIES
+                                                      "$<BUILD_INTERFACE:${PYTHON_INCLUDE_DIRS}>")
 set_property(
   TARGET pybind11::pybind11
   APPEND
-  PROPERTY INTERFACE_INCLUDE_DIRECTORIES $<BUILD_INTERFACE:${PYTHON_INCLUDE_DIRS}>)
+  PROPERTY INTERFACE_LINK_LIBRARIES pybind11::python_headers)
 
 set(pybind11_INCLUDE_DIRS
     "${pybind11_INCLUDE_DIR}" "${PYTHON_INCLUDE_DIRS}"
@@ -101,25 +115,37 @@ if(PYTHON_IS_DEBUG)
     PROPERTY INTERFACE_COMPILE_DEFINITIONS Py_DEBUG)
 endif()
 
-set_property(
-  TARGET pybind11::module
-  APPEND
-  PROPERTY
-    INTERFACE_LINK_LIBRARIES pybind11::python_link_helper
-    "$<$<OR:$<PLATFORM_ID:Windows>,$<PLATFORM_ID:Cygwin>>:$<BUILD_INTERFACE:${PYTHON_LIBRARIES}>>")
+# The <3.11 code here does not support release/debug builds at the same time, like on vcpkg
+if(CMAKE_VERSION VERSION_LESS 3.11)
+  set_property(
+    TARGET pybind11::module
+    APPEND
+    PROPERTY
+      INTERFACE_LINK_LIBRARIES
+      pybind11::python_link_helper
+      "$<$<OR:$<PLATFORM_ID:Windows>,$<PLATFORM_ID:Cygwin>>:$<BUILD_INTERFACE:${PYTHON_LIBRARIES}>>"
+  )
 
-if(PYTHON_VERSION VERSION_LESS 3)
   set_property(
-    TARGET pybind11::pybind11
+    TARGET pybind11::embed
     APPEND
-    PROPERTY INTERFACE_LINK_LIBRARIES pybind11::python2_no_register)
+    PROPERTY INTERFACE_LINK_LIBRARIES pybind11::pybind11 $<BUILD_INTERFACE:${PYTHON_LIBRARIES}>)
+else()
+  # The IMPORTED INTERFACE library here is to ensure that "debug" and "release" get processed outside
+  # of a generator expression - https://gitlab.kitware.com/cmake/cmake/-/issues/18424, as they are
+  # target_link_library keywords rather than real libraries.
+  add_library(pybind11::_ClassicPythonLibraries IMPORTED INTERFACE)
+  target_link_libraries(pybind11::_ClassicPythonLibraries INTERFACE ${PYTHON_LIBRARIES})
+  target_link_libraries(
+    pybind11::module
+    INTERFACE
+      pybind11::python_link_helper
+      "$<$<OR:$<PLATFORM_ID:Windows>,$<PLATFORM_ID:Cygwin>>:pybind11::_ClassicPythonLibraries>")
+
+  target_link_libraries(pybind11::embed INTERFACE pybind11::pybind11
+                                                  pybind11::_ClassicPythonLibraries)
 endif()
 
-set_property(
-  TARGET pybind11::embed
-  APPEND
-  PROPERTY INTERFACE_LINK_LIBRARIES pybind11::pybind11 $<BUILD_INTERFACE:${PYTHON_LIBRARIES}>)
-
 function(pybind11_extension name)
   # The prefix and extension are provided by FindPythonLibsNew.cmake
   set_target_properties(${name} PROPERTIES PREFIX "${PYTHON_MODULE_PREFIX}"
@@ -166,8 +192,13 @@ function(pybind11_add_module target_name)
   # py::module_local).  We force it on everything inside the `pybind11`
   # namespace; also turning it on for a pybind module compilation here avoids
   # potential warnings or issues from having mixed hidden/non-hidden types.
-  set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET "hidden"
-                                                  CUDA_VISIBILITY_PRESET "hidden")
+  if(NOT DEFINED CMAKE_CXX_VISIBILITY_PRESET)
+    set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET "hidden")
+  endif()
+
+  if(NOT DEFINED CMAKE_CUDA_VISIBILITY_PRESET)
+    set_target_properties(${target_name} PROPERTIES CUDA_VISIBILITY_PRESET "hidden")
+  endif()
 
   if(ARG_NO_EXTRAS)
     return()
@@ -181,7 +212,9 @@ function(pybind11_add_module target_name)
     endif()
   endif()
 
-  if(NOT MSVC AND NOT ${CMAKE_BUILD_TYPE} MATCHES Debug|RelWithDebInfo)
+  # Use case-insensitive comparison to match the result of $<CONFIG:cfgs>
+  string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE)
+  if(NOT MSVC AND NOT ${uppercase_CMAKE_BUILD_TYPE} MATCHES DEBUG|RELWITHDEBINFO)
     pybind11_strip(${target_name})
   endif()
 
diff --git a/3rdparty/pybind11/tools/setup_global.py.in b/3rdparty/pybind11/tools/setup_global.py.in
index 4cf040b2d8..d91468c10c 100644
--- a/3rdparty/pybind11/tools/setup_global.py.in
+++ b/3rdparty/pybind11/tools/setup_global.py.in
@@ -1,17 +1,11 @@
-#!/usr/bin/env python
-# -*- coding: utf-8 -*-
+#!/usr/bin/env python3
 
 # Setup script for pybind11-global (in the sdist or in tools/setup_global.py in the repository)
 # This package is targeted for easy use from CMake.
 
-import contextlib
 import glob
 import os
 import re
-import shutil
-import subprocess
-import sys
-import tempfile
 
 # Setuptools has to be before distutils
 from setuptools import setup
@@ -33,8 +27,10 @@ class InstallHeadersNested(install_headers):
 
 main_headers = glob.glob("pybind11/include/pybind11/*.h")
 detail_headers = glob.glob("pybind11/include/pybind11/detail/*.h")
+stl_headers = glob.glob("pybind11/include/pybind11/stl/*.h")
 cmake_files = glob.glob("pybind11/share/cmake/pybind11/*.cmake")
-headers = main_headers + detail_headers
+pkgconfig_files = glob.glob("pybind11/share/pkgconfig/*.pc")
+headers = main_headers + detail_headers + stl_headers
 
 cmdclass = {"install_headers": InstallHeadersNested}
 $extra_cmd
@@ -56,8 +52,10 @@ setup(
     headers=headers,
     data_files=[
         (base + "share/cmake/pybind11", cmake_files),
+        (base + "share/pkgconfig", pkgconfig_files),
         (base + "include/pybind11", main_headers),
         (base + "include/pybind11/detail", detail_headers),
+        (base + "include/pybind11/stl", stl_headers),
     ],
     cmdclass=cmdclass,
 )
diff --git a/3rdparty/pybind11/tools/setup_main.py.in b/3rdparty/pybind11/tools/setup_main.py.in
index 2231a08fdc..65198bdb66 100644
--- a/3rdparty/pybind11/tools/setup_main.py.in
+++ b/3rdparty/pybind11/tools/setup_main.py.in
@@ -1,5 +1,4 @@
-#!/usr/bin/env python
-# -*- coding: utf-8 -*-
+#!/usr/bin/env python3
 
 # Setup script (in the sdist or in tools/setup_main.py in the repository)
 
@@ -16,13 +15,17 @@ setup(
         "pybind11",
         "pybind11.include.pybind11",
         "pybind11.include.pybind11.detail",
+        "pybind11.include.pybind11.stl",
         "pybind11.share.cmake.pybind11",
+        "pybind11.share.pkgconfig",
     ],
     package_data={
-        "pybind11": ["py.typed", "*.pyi"],
+        "pybind11": ["py.typed"],
         "pybind11.include.pybind11": ["*.h"],
         "pybind11.include.pybind11.detail": ["*.h"],
+        "pybind11.include.pybind11.stl": ["*.h"],
         "pybind11.share.cmake.pybind11": ["*.cmake"],
+        "pybind11.share.pkgconfig": ["*.pc"],
     },
     extras_require={
         "global": ["pybind11_global==$version"]
@@ -30,6 +33,9 @@ setup(
     entry_points={
         "console_scripts": [
              "pybind11-config = pybind11.__main__:main",
+        ],
+        "pipx.run": [
+             "pybind11 = pybind11.__main__:main",
         ]
     },
     cmdclass=cmdclass

From 7ca3ba3835ee6083b441d693a30ef7530a7e2eed Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 15 Sep 2022 12:27:36 +0200
Subject: [PATCH 187/712] nexus: Add ES2 device names and --list-devices

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.cc | 36 +++++++++++++++++++++++++++++++++++-
 nexus/arch.h  |  2 ++
 nexus/main.cc |  5 +++++
 3 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index c2d3b6e41c..274c5ad373 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -58,7 +58,9 @@ Arch::Arch(ArchArgs args) : args(args)
         log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());
     device = args.device.substr(0, last_sep);
     speed = args.device.substr(last_sep + 1, 1);
-    auto package_end = args.device.find_last_of("0123456789");
+    auto package_end = args.device.find_last_of("0123456789", args.device.substr(args.device.size() - 3) == "ES2"
+                                                                      ? args.device.size() - 3
+                                                                      : std::string::npos);
     if (package_end == std::string::npos || package_end < last_sep)
         log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());
     package = args.device.substr(last_sep + 2, (package_end - (last_sep + 2)) + 1);
@@ -67,6 +69,9 @@ Arch::Arch(ArchArgs args) : args(args)
     // Check for 'ES' part
     if (rating.size() > 1 && rating.substr(1) == "ES") {
         variant = "ES";
+    } else if (rating.size() > 1 && rating.substr(1) == "ES2") {
+        // ES2 devices are production-equivalent from nextpnr's and bitstream point of view
+        variant = "";
     } else {
         variant = "";
     }
@@ -194,6 +199,35 @@ Arch::Arch(ArchArgs args) : args(args)
     }
 }
 
+void Arch::list_devices()
+{
+    std::vector<std::string> families{
+            "LIFCL",
+    };
+    log("Supported devices: \n");
+    for (auto fam : families) {
+        std::string chipdb = stringf("nexus/chipdb-%s.bin", fam.c_str());
+        auto db_ptr = reinterpret_cast<const RelPtr<DatabasePOD> *>(get_chipdb(chipdb));
+        if (!db_ptr)
+            continue; // chipdb not available
+        // enumerate chips
+        for (auto &chip : db_ptr->get()->chips) {
+            // enumerate packages
+            for (auto &pkg : chip.packages) {
+                // enumerate suffices
+                for (auto speedgrade : {"7", "8", "9"}) { // TODO: these might depend on family
+                    for (auto rating : {"I", "C"}) {
+                        for (auto suffix : {"", "ES", "ES2"}) {
+                            log("    %s-%s%s%s%s\n", chip.device_name.get(), speedgrade, pkg.short_name.get(), rating,
+                                suffix);
+                        }
+                    }
+                }
+            }
+        }
+    }
+}
+
 // -----------------------------------------------------------------------
 
 std::string Arch::getChipName() const { return args.device; }
diff --git a/nexus/arch.h b/nexus/arch.h
index 4a28dfb704..df4f976aca 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1522,6 +1522,8 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
     void write_fasm(std::ostream &out) const;
+    // -------------------------------------------------
+    static void list_devices();
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/nexus/main.cc b/nexus/main.cc
index bca6661f66..cfa06b745b 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -48,6 +48,7 @@ po::options_description NexusCommandHandler::getArchOptions()
 {
     po::options_description specific("Architecture specific options");
     specific.add_options()("device", po::value<std::string>(), "device name");
+    specific.add_options()("list-devices", "list all supported device names");
     specific.add_options()("fasm", po::value<std::string>(), "fasm file to write");
     specific.add_options()("pdc", po::value<std::string>(), "physical constraints file");
     specific.add_options()("no-post-place-opt", "disable post-place repacking (debugging use only)");
@@ -73,6 +74,10 @@ void NexusCommandHandler::customBitstream(Context *ctx)
 std::unique_ptr<Context> NexusCommandHandler::createContext(dict<std::string, Property> &values)
 {
     ArchArgs chipArgs;
+    if (vm.count("list-devices")) {
+        Arch::list_devices();
+        exit(0);
+    }
     if (!vm.count("device")) {
         log_error("device must be specified on the command line (e.g. --device LIFCL-40-9BG400CES)\n");
     }

From 9e272810d88ab765164fd3a10487845da1eb47c6 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 15 Sep 2022 13:28:43 +0200
Subject: [PATCH 188/712] ecp5: Split bitstream generation into more functions

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/bitstream.cc | 2749 +++++++++++++++++++++++----------------------
 1 file changed, 1402 insertions(+), 1347 deletions(-)

diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 37883bdad6..8987fefb70 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -46,1506 +46,1561 @@ void config_empty_lfe5um5g_45f(ChipConfig &cc);
 void config_empty_lfe5um5g_85f(ChipConfig &cc);
 } // namespace BaseConfigs
 
-// Convert an absolute wire name to a relative Trellis one
-static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
+namespace {
+struct ECP5Bitgen
 {
-    std::string basename = ctx->loc_info(wire)->wire_data[wire.index].name.get();
-    std::string prefix2 = basename.substr(0, 2);
-    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
-        return basename;
-    if (loc == wire.location)
-        return basename;
-    std::string rel_prefix;
-    if (wire.location.y < loc.y)
-        rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
-    if (wire.location.y > loc.y)
-        rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
-    if (wire.location.x > loc.x)
-        rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
-    if (wire.location.x < loc.x)
-        rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
-    return rel_prefix + "_" + basename;
-}
-
-static std::vector<bool> int_to_bitvector(int val, int size)
-{
-    std::vector<bool> bv;
-    for (int i = 0; i < size; i++) {
-        bv.push_back((val & (1 << i)) != 0);
-    }
-    return bv;
-}
-
-static std::vector<bool> str_to_bitvector(std::string str, int size)
-{
-    std::vector<bool> bv;
-    bv.resize(size, 0);
-    if (str.substr(0, 2) != "0b")
-        log_error("error parsing value '%s', expected 0b prefix\n", str.c_str());
-    for (int i = 0; i < int(str.size()) - 2; i++) {
-        char c = str.at((str.size() - i) - 1);
-        NPNR_ASSERT(c == '0' || c == '1');
-        bv.at(i) = (c == '1');
+    explicit ECP5Bitgen(Context *ctx) : ctx(ctx){};
+    Context *ctx;
+    ChipConfig cc;
+    std::string get_trellis_wirename(Location loc, WireId wire)
+    {
+        std::string basename = ctx->loc_info(wire)->wire_data[wire.index].name.get();
+        std::string prefix2 = basename.substr(0, 2);
+        if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
+            return basename;
+        if (loc == wire.location)
+            return basename;
+        std::string rel_prefix;
+        if (wire.location.y < loc.y)
+            rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
+        if (wire.location.y > loc.y)
+            rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
+        if (wire.location.x > loc.x)
+            rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
+        if (wire.location.x < loc.x)
+            rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
+        return rel_prefix + "_" + basename;
     }
-    return bv;
-}
-
-// Tie a wire using the CIB ties
-static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value)
-{
-    static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
-    std::queue<WireId> signals;
-    signals.push(wire);
-    WireId cibsig;
-    std::string basename;
-    while (true) {
-        NPNR_ASSERT(!signals.empty());
-        NPNR_ASSERT(signals.size() < 100);
-        cibsig = signals.front();
-        basename = ctx->get_wire_basename(cibsig).str(ctx);
-        signals.pop();
-        if (std::regex_match(basename, cib_re))
-            break;
-        for (auto pip : ctx->getPipsUphill(cibsig))
-            signals.push(ctx->getPipSrcWire(pip));
+    std::vector<bool> int_to_bitvector(int val, int size)
+    {
+        std::vector<bool> bv;
+        for (int i = 0; i < size; i++) {
+            bv.push_back((val & (1 << i)) != 0);
+        }
+        return bv;
     }
-
-    bool out_value = value;
-    if (basename.substr(0, 3) == "JCE")
-        NPNR_ASSERT(value);
-    if (basename.substr(0, 4) == "JCLK" || basename.substr(0, 4) == "JLSR") {
-        NPNR_ASSERT(value);
-        out_value = 0;
+    std::vector<bool> str_to_bitvector(std::string str, int size)
+    {
+        std::vector<bool> bv;
+        bv.resize(size, 0);
+        if (str.substr(0, 2) != "0b")
+            log_error("error parsing value '%s', expected 0b prefix\n", str.c_str());
+        for (int i = 0; i < int(str.size()) - 2; i++) {
+            char c = str.at((str.size() - i) - 1);
+            NPNR_ASSERT(c == '0' || c == '1');
+            bv.at(i) = (c == '1');
+        }
+        return bv;
     }
 
-    for (const auto &tile : ctx->get_tiles_at_loc(cibsig.location.y, cibsig.location.x)) {
-        if (tile.second.substr(0, 3) == "CIB" || tile.second.substr(0, 4) == "VCIB") {
+    // Tie a wire using the CIB ties
+    void tie_cib_signal(WireId wire, bool value)
+    {
+        static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
+        std::queue<WireId> signals;
+        signals.push(wire);
+        WireId cibsig;
+        std::string basename;
+        while (true) {
+            NPNR_ASSERT(!signals.empty());
+            NPNR_ASSERT(signals.size() < 100);
+            cibsig = signals.front();
+            basename = ctx->get_wire_basename(cibsig).str(ctx);
+            signals.pop();
+            if (std::regex_match(basename, cib_re))
+                break;
+            for (auto pip : ctx->getPipsUphill(cibsig))
+                signals.push(ctx->getPipSrcWire(pip));
+        }
 
-            cc.tiles[tile.first].add_enum("CIB." + basename + "MUX", out_value ? "1" : "0");
-            return;
+        bool out_value = value;
+        if (basename.substr(0, 3) == "JCE")
+            NPNR_ASSERT(value);
+        if (basename.substr(0, 4) == "JCLK" || basename.substr(0, 4) == "JLSR") {
+            NPNR_ASSERT(value);
+            out_value = 0;
         }
-    }
-    NPNR_ASSERT_FALSE("CIB tile not found at location");
-}
 
-inline int chtohex(char c)
-{
-    static const std::string hex = "0123456789ABCDEF";
-    return hex.find(std::toupper(c));
-}
+        for (const auto &tile : ctx->get_tiles_at_loc(cibsig.location.y, cibsig.location.x)) {
+            if (tile.second.substr(0, 3) == "CIB" || tile.second.substr(0, 4) == "VCIB") {
 
-std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)
-{
-    // Parse a string that may be binary or hex
-    std::vector<bool> result;
-    result.resize(length, false);
-    if (p.is_string) {
-        std::string str = p.as_string();
-        NPNR_ASSERT(str.substr(0, 2) == "0x");
-        // Lattice style hex string
-        if (int(str.length()) > (2 + ((length + 3) / 4)))
-            log_error("hex string value too long, expected up to %d chars and found %d.\n", (2 + ((length + 3) / 4)),
-                      int(str.length()));
-        for (int i = 0; i < int(str.length()) - 2; i++) {
-            char c = str.at((str.size() - i) - 1);
-            int nibble = chtohex(c);
-            if (nibble == (int)std::string::npos)
-                log_error("hex string has invalid char '%c' at position %d.\n", c, i);
-            result.at(i * 4) = nibble & 0x1;
-            if (i * 4 + 1 < length)
-                result.at(i * 4 + 1) = nibble & 0x2;
-            if (i * 4 + 2 < length)
-                result.at(i * 4 + 2) = nibble & 0x4;
-            if (i * 4 + 3 < length)
-                result.at(i * 4 + 3) = nibble & 0x8;
+                cc.tiles[tile.first].add_enum("CIB." + basename + "MUX", out_value ? "1" : "0");
+                return;
+            }
         }
-    } else {
-        result = p.as_bits();
-        result.resize(length, false);
+        NPNR_ASSERT_FALSE("CIB tile not found at location");
     }
-    return result;
-}
 
-inline uint16_t bit_reverse(uint16_t x, int size)
-{
-    uint16_t y = 0;
-    for (int i = 0; i < size; i++)
-        if (x & (1 << i))
-            y |= (1 << ((size - 1) - i));
-    return y;
-}
+    inline int chtohex(char c)
+    {
+        static const std::string hex = "0123456789ABCDEF";
+        return hex.find(std::toupper(c));
+    }
 
-// Get the PIO tile corresponding to a PIO bel
-static std::string get_pio_tile(Context *ctx, BelId bel)
-{
-    static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
-    static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
-    static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
-    static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
-
-    std::string pio_name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-    if (bel.location.y == 0) {
-        if (pio_name == "PIOA") {
-            return ctx->get_tile_by_type_loc(0, bel.location.x, "PIOT0");
-        } else if (pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1");
-        } else {
-            NPNR_ASSERT_FALSE("bad PIO location");
-        }
-    } else if (bel.location.y == ctx->chip_info->height - 1) {
-        if (pio_name == "PIOA") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pioa_b);
-        } else if (pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x + 1, piob_b);
+    std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)
+    {
+        // Parse a string that may be binary or hex
+        std::vector<bool> result;
+        result.resize(length, false);
+        if (p.is_string) {
+            std::string str = p.as_string();
+            NPNR_ASSERT(str.substr(0, 2) == "0x");
+            // Lattice style hex string
+            if (int(str.length()) > (2 + ((length + 3) / 4)))
+                log_error("hex string value too long, expected up to %d chars and found %d.\n",
+                          (2 + ((length + 3) / 4)), int(str.length()));
+            for (int i = 0; i < int(str.length()) - 2; i++) {
+                char c = str.at((str.size() - i) - 1);
+                int nibble = chtohex(c);
+                if (nibble == (int)std::string::npos)
+                    log_error("hex string has invalid char '%c' at position %d.\n", c, i);
+                result.at(i * 4) = nibble & 0x1;
+                if (i * 4 + 1 < length)
+                    result.at(i * 4 + 1) = nibble & 0x2;
+                if (i * 4 + 2 < length)
+                    result.at(i * 4 + 2) = nibble & 0x4;
+                if (i * 4 + 3 < length)
+                    result.at(i * 4 + 3) = nibble & 0x8;
+            }
         } else {
-            NPNR_ASSERT_FALSE("bad PIO location");
+            result = p.as_bits();
+            result.resize(length, false);
         }
-    } else if (bel.location.x == 0) {
-        return ctx->get_tile_by_type_loc(bel.location.y + 1, bel.location.x, pioabcd_l);
-    } else if (bel.location.x == ctx->chip_info->width - 1) {
-        return ctx->get_tile_by_type_loc(bel.location.y + 1, bel.location.x, pioabcd_r);
-    } else {
-        NPNR_ASSERT_FALSE("bad PIO location");
+        return result;
     }
-}
 
-// Get the PIC tile corresponding to a PIO bel
-static std::string get_pic_tile(Context *ctx, BelId bel)
-{
-    static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
-    static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
-    static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"};
-    static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"};
-
-    static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
-    static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
-
-    std::string pio_name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-    if (bel.location.y == 0) {
-        if (pio_name == "PIOA") {
-            return ctx->get_tile_by_type_loc(1, bel.location.x, "PICT0");
-        } else if (pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1");
-        } else {
-            NPNR_ASSERT_FALSE("bad PIO location");
-        }
-    } else if (bel.location.y == ctx->chip_info->height - 1) {
-        if (pio_name == "PIOA") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pica_b);
-        } else if (pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x + 1, picb_b);
-        } else {
-            NPNR_ASSERT_FALSE("bad PIO location");
-        }
-    } else if (bel.location.x == 0) {
-        if (pio_name == "PIOA" || pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, picab_l);
-        } else if (pio_name == "PIOC" || pio_name == "PIOD") {
-            return ctx->get_tile_by_type_loc(bel.location.y + 2, bel.location.x, piccd_l);
+    inline uint16_t bit_reverse(uint16_t x, int size)
+    {
+        uint16_t y = 0;
+        for (int i = 0; i < size; i++)
+            if (x & (1 << i))
+                y |= (1 << ((size - 1) - i));
+        return y;
+    }
+
+    // Get the PIO tile corresponding to a PIO bel
+    std::string get_pio_tile(BelId bel)
+    {
+        static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
+        static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
+        static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
+        static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
+
+        std::string pio_name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+        if (bel.location.y == 0) {
+            if (pio_name == "PIOA") {
+                return ctx->get_tile_by_type_loc(0, bel.location.x, "PIOT0");
+            } else if (pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1");
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
+        } else if (bel.location.y == ctx->chip_info->height - 1) {
+            if (pio_name == "PIOA") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pioa_b);
+            } else if (pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x + 1, piob_b);
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
+        } else if (bel.location.x == 0) {
+            return ctx->get_tile_by_type_loc(bel.location.y + 1, bel.location.x, pioabcd_l);
+        } else if (bel.location.x == ctx->chip_info->width - 1) {
+            return ctx->get_tile_by_type_loc(bel.location.y + 1, bel.location.x, pioabcd_r);
         } else {
             NPNR_ASSERT_FALSE("bad PIO location");
         }
-    } else if (bel.location.x == ctx->chip_info->width - 1) {
-        if (pio_name == "PIOA" || pio_name == "PIOB") {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, picab_r);
-        } else if (pio_name == "PIOC" || pio_name == "PIOD") {
-            return ctx->get_tile_by_type_loc(bel.location.y + 2, bel.location.x, piccd_r);
+    }
+
+    // Get the PIC tile corresponding to a PIO bel
+    std::string get_pic_tile(BelId bel)
+    {
+        static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
+        static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
+        static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"};
+        static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"};
+
+        static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
+        static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
+
+        std::string pio_name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+        if (bel.location.y == 0) {
+            if (pio_name == "PIOA") {
+                return ctx->get_tile_by_type_loc(1, bel.location.x, "PICT0");
+            } else if (pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1");
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
+        } else if (bel.location.y == ctx->chip_info->height - 1) {
+            if (pio_name == "PIOA") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pica_b);
+            } else if (pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x + 1, picb_b);
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
+        } else if (bel.location.x == 0) {
+            if (pio_name == "PIOA" || pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, picab_l);
+            } else if (pio_name == "PIOC" || pio_name == "PIOD") {
+                return ctx->get_tile_by_type_loc(bel.location.y + 2, bel.location.x, piccd_l);
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
+        } else if (bel.location.x == ctx->chip_info->width - 1) {
+            if (pio_name == "PIOA" || pio_name == "PIOB") {
+                return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, picab_r);
+            } else if (pio_name == "PIOC" || pio_name == "PIOD") {
+                return ctx->get_tile_by_type_loc(bel.location.y + 2, bel.location.x, piccd_r);
+            } else {
+                NPNR_ASSERT_FALSE("bad PIO location");
+            }
         } else {
             NPNR_ASSERT_FALSE("bad PIO location");
         }
-    } else {
-        NPNR_ASSERT_FALSE("bad PIO location");
     }
-}
 
-// Get the complement PIC and PIO tiles for a pseudo differential IO
-static std::string get_comp_pio_tile(Context *ctx, BelId bel)
-{
-    NPNR_ASSERT(bel.location.y == 0);
-    return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1");
-}
-static std::string get_comp_pic_tile(Context *ctx, BelId bel)
-{
-    NPNR_ASSERT(bel.location.y == 0);
-    return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1");
-}
-
-// Get the list of tiles corresponding to a blockram
-std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel)
-{
-    std::vector<std::string> tiles;
-    Loc loc = ctx->getBelLocation(bel);
-
-    static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"};
-    static const std::set<std::string> ebr8 = {"MIB_EBR8",      "EBR_SPINE_UL1",   "EBR_SPINE_UR1", "EBR_SPINE_LL1",
-                                               "EBR_CMUX_UL",   "EBR_SPINE_LL0",   "EBR_CMUX_LL",   "EBR_SPINE_LR0",
-                                               "EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0",
-                                               "EBR_SPINE_UR2", "EBR_SPINE_LL2",   "EBR_SPINE_LR2", "EBR_SPINE_UR0"};
-
-    switch (loc.z) {
-    case 0:
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR1"));
-        break;
-    case 1:
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR2"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR3"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_EBR4"));
-        break;
-    case 2:
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR4"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR5"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_EBR6"));
-        break;
-    case 3:
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR6"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR7"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, ebr8));
-        break;
-    default:
-        NPNR_ASSERT_FALSE("bad EBR z loc");
+    // Get the complement PIC and PIO tiles for a pseudo differential IO
+    std::string get_comp_pio_tile(BelId bel)
+    {
+        NPNR_ASSERT(bel.location.y == 0);
+        return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1");
+    }
+    std::string get_comp_pic_tile(BelId bel)
+    {
+        NPNR_ASSERT(bel.location.y == 0);
+        return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1");
     }
-    return tiles;
-}
 
-// Get the list of tiles corresponding to a DSP
-std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
-{
-    std::vector<std::string> tiles;
-    Loc loc = ctx->getBelLocation(bel);
+    // Get the list of tiles corresponding to a blockram
+    std::vector<std::string> get_bram_tiles(BelId bel)
+    {
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+
+        static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"};
+        static const std::set<std::string> ebr8 = {
+                "MIB_EBR8",      "EBR_SPINE_UL1", "EBR_SPINE_UR1", "EBR_SPINE_LL1",   "EBR_CMUX_UL",   "EBR_SPINE_LL0",
+                "EBR_CMUX_LL",   "EBR_SPINE_LR0", "EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0",
+                "EBR_SPINE_UR2", "EBR_SPINE_LL2", "EBR_SPINE_LR2", "EBR_SPINE_UR0"};
 
-    static const std::set<std::string> dsp8 = {"MIB_DSP8", "DSP_SPINE_UL0", "DSP_SPINE_UR0", "DSP_SPINE_UR1"};
-    if (ctx->getBelType(bel) == id_MULT18X18D) {
         switch (loc.z) {
         case 0:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB2_DSP4"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR1"));
             break;
         case 1:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP4"));
-            break;
-        case 4:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, dsp8));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB2_DSP8"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR2"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR3"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_EBR4"));
             break;
-        case 5:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, dsp8));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP8"));
+        case 2:
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR4"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR5"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_EBR6"));
             break;
-        default:
-            NPNR_ASSERT_FALSE("bad MULT z loc");
-        }
-    } else if (ctx->getBelType(bel) == id_ALU54B) {
-        switch (loc.z) {
         case 3:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB2_DSP0"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB2_DSP1"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP2"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP3"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP4"));
-            break;
-        case 7:
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB2_DSP4"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB2_DSP5"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP6"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP7"));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, dsp8));
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP8"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_EBR6"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_EBR7"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, ebr8));
             break;
         default:
-            NPNR_ASSERT_FALSE("bad ALU z loc");
+            NPNR_ASSERT_FALSE("bad EBR z loc");
         }
+        return tiles;
     }
-    return tiles;
-}
 
-// Get the list of tiles corresponding to a DCU
-std::vector<std::string> get_dcu_tiles(Context *ctx, BelId bel)
-{
-    std::vector<std::string> tiles;
-    Loc loc = ctx->getBelLocation(bel);
-    for (int i = 0; i < 9; i++)
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + i, "DCU" + std::to_string(i)));
-    return tiles;
-}
+    // Get the list of tiles corresponding to a DSP
+    std::vector<std::string> get_dsp_tiles(BelId bel)
+    {
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+
+        static const std::set<std::string> dsp8 = {"MIB_DSP8", "DSP_SPINE_UL0", "DSP_SPINE_UR0", "DSP_SPINE_UR1"};
+        if (ctx->getBelType(bel) == id_MULT18X18D) {
+            switch (loc.z) {
+            case 0:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB2_DSP4"));
+                break;
+            case 1:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP4"));
+                break;
+            case 4:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, dsp8));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 4, "MIB2_DSP8"));
+                break;
+            case 5:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, "MIB2_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, dsp8));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 3, "MIB2_DSP8"));
+                break;
+            default:
+                NPNR_ASSERT_FALSE("bad MULT z loc");
+            }
+        } else if (ctx->getBelType(bel) == id_ALU54B) {
+            switch (loc.z) {
+            case 3:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB2_DSP0"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB2_DSP1"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP2"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP3"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP4"));
+                break;
+            case 7:
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 3, "MIB2_DSP4"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 2, "MIB2_DSP5"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "MIB2_DSP6"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "MIB2_DSP7"));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, dsp8));
+                tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "MIB2_DSP8"));
+                break;
+            default:
+                NPNR_ASSERT_FALSE("bad ALU z loc");
+            }
+        }
+        return tiles;
+    }
 
-// Get the list of tiles corresponding to a PLL
-std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
-{
-    std::string name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-    std::vector<std::string> tiles;
-    Loc loc = ctx->getBelLocation(bel);
-    static const std::set<std::string> pll1_lr = {"PLL1_LR", "BANKREF4"};
-
-    if (name == "EHXPLL_UL") {
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "PLL0_UL"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, "PLL1_UL"));
-    } else if (name == "EHXPLL_LL") {
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "PLL0_LL"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x + 1, "BANKREF8"));
-    } else if (name == "EHXPLL_LR") {
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "PLL0_LR"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, pll1_lr));
-    } else if (name == "EHXPLL_UR") {
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "PLL0_UR"));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x + 1, "PLL1_UR"));
-    } else {
-        NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+    // Get the list of tiles corresponding to a DCU
+    std::vector<std::string> get_dcu_tiles(BelId bel)
+    {
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+        for (int i = 0; i < 9; i++)
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + i, "DCU" + std::to_string(i)));
+        return tiles;
     }
-    return tiles;
-}
 
-void fix_tile_names(Context *ctx, ChipConfig &cc)
-{
-    // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
-    if (ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
-        ctx->args.type == ArchArgs::LFE5U_45F || ctx->args.type == ArchArgs::LFE5U_85F) {
-        std::map<std::string, std::string> tiletype_xform;
-        for (const auto &tile : cc.tiles) {
-            std::string newname = tile.first;
-            auto cibdcu = tile.first.find("CIB_DCU");
-            if (cibdcu != std::string::npos) {
-                // Add the V
-                if (newname.at(cibdcu - 1) != 'V') {
-                    newname.insert(cibdcu, 1, 'V');
+    // Get the list of tiles corresponding to a PLL
+    std::vector<std::string> get_pll_tiles(BelId bel)
+    {
+        std::string name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+        static const std::set<std::string> pll1_lr = {"PLL1_LR", "BANKREF4"};
+
+        if (name == "EHXPLL_UL") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x - 1, "PLL0_UL"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, "PLL1_UL"));
+        } else if (name == "EHXPLL_LL") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "PLL0_LL"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x + 1, "BANKREF8"));
+        } else if (name == "EHXPLL_LR") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "PLL0_LR"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, pll1_lr));
+        } else if (name == "EHXPLL_UR") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "PLL0_UR"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x + 1, "PLL1_UR"));
+        } else {
+            NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+        }
+        return tiles;
+    }
+
+    void fix_tile_names()
+    {
+        // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
+        if (ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
+            ctx->args.type == ArchArgs::LFE5U_45F || ctx->args.type == ArchArgs::LFE5U_85F) {
+            std::map<std::string, std::string> tiletype_xform;
+            for (const auto &tile : cc.tiles) {
+                std::string newname = tile.first;
+                auto cibdcu = tile.first.find("CIB_DCU");
+                if (cibdcu != std::string::npos) {
+                    // Add the V
+                    if (newname.at(cibdcu - 1) != 'V') {
+                        newname.insert(cibdcu, 1, 'V');
+                        tiletype_xform[tile.first] = newname;
+                    }
+                } else if (boost::ends_with(tile.first, "BMID_0H")) {
+                    newname.back() = 'V';
+                    tiletype_xform[tile.first] = newname;
+                } else if (boost::ends_with(tile.first, "BMID_2")) {
+                    newname.push_back('V');
                     tiletype_xform[tile.first] = newname;
                 }
-            } else if (boost::ends_with(tile.first, "BMID_0H")) {
-                newname.back() = 'V';
-                tiletype_xform[tile.first] = newname;
-            } else if (boost::ends_with(tile.first, "BMID_2")) {
-                newname.push_back('V');
-                tiletype_xform[tile.first] = newname;
             }
-        }
-        // Apply the name changes
-        for (auto xform : tiletype_xform) {
-            auto &existing = cc.tiles.at(xform.first);
-            for (const auto &carc : existing.carcs)
-                cc.tiles[xform.second].carcs.push_back(carc);
-            for (const auto &cenum : existing.cenums)
-                cc.tiles[xform.second].cenums.push_back(cenum);
-            for (const auto &cword : existing.cwords)
-                cc.tiles[xform.second].cwords.push_back(cword);
-            for (const auto &cunknown : existing.cunknowns)
-                cc.tiles[xform.second].cunknowns.push_back(cunknown);
-            cc.tiles.erase(xform.first);
-        }
-        for (auto &tg : cc.tilegroups) {
-            for (auto &t : tg.tiles) {
-                if (boost::ends_with(t, "BMID_0H"))
-                    t.back() = 'V';
-                else if (boost::ends_with(t, "BMID_2"))
-                    t.push_back('V');
+            // Apply the name changes
+            for (auto xform : tiletype_xform) {
+                auto &existing = cc.tiles.at(xform.first);
+                for (const auto &carc : existing.carcs)
+                    cc.tiles[xform.second].carcs.push_back(carc);
+                for (const auto &cenum : existing.cenums)
+                    cc.tiles[xform.second].cenums.push_back(cenum);
+                for (const auto &cword : existing.cwords)
+                    cc.tiles[xform.second].cwords.push_back(cword);
+                for (const auto &cunknown : existing.cunknowns)
+                    cc.tiles[xform.second].cunknowns.push_back(cunknown);
+                cc.tiles.erase(xform.first);
+            }
+            for (auto &tg : cc.tilegroups) {
+                for (auto &t : tg.tiles) {
+                    if (boost::ends_with(t, "BMID_0H"))
+                        t.back() = 'V';
+                    else if (boost::ends_with(t, "BMID_2"))
+                        t.push_back('V');
+                }
             }
         }
     }
-}
 
-void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
-{
-    for (auto port : ci->ports) {
-        if (port.second.net == nullptr && port.second.type == PORT_IN) {
-            if (port.first.str(ctx).substr(0, 3) == "CLK" || port.first.str(ctx).substr(0, 2) == "CE" ||
-                port.first.str(ctx).substr(0, 3) == "RST" || port.first.str(ctx).substr(0, 3) == "SRO" ||
-                port.first.str(ctx).substr(0, 3) == "SRI" || port.first.str(ctx).substr(0, 2) == "RO" ||
-                port.first.str(ctx).substr(0, 2) == "MA" || port.first.str(ctx).substr(0, 2) == "MB" ||
-                port.first.str(ctx).substr(0, 3) == "CFB" || port.first.str(ctx).substr(0, 3) == "CIN" ||
-                port.first.str(ctx).substr(0, 6) == "SOURCE" || port.first.str(ctx).substr(0, 6) == "SIGNED" ||
-                port.first.str(ctx).substr(0, 2) == "OP")
-                continue;
-            bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
-            tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
+    void tieoff_dsp_ports(CellInfo *ci)
+    {
+        for (auto port : ci->ports) {
+            if (port.second.net == nullptr && port.second.type == PORT_IN) {
+                if (port.first.str(ctx).substr(0, 3) == "CLK" || port.first.str(ctx).substr(0, 2) == "CE" ||
+                    port.first.str(ctx).substr(0, 3) == "RST" || port.first.str(ctx).substr(0, 3) == "SRO" ||
+                    port.first.str(ctx).substr(0, 3) == "SRI" || port.first.str(ctx).substr(0, 2) == "RO" ||
+                    port.first.str(ctx).substr(0, 2) == "MA" || port.first.str(ctx).substr(0, 2) == "MB" ||
+                    port.first.str(ctx).substr(0, 3) == "CFB" || port.first.str(ctx).substr(0, 3) == "CIN" ||
+                    port.first.str(ctx).substr(0, 6) == "SOURCE" || port.first.str(ctx).substr(0, 6) == "SIGNED" ||
+                    port.first.str(ctx).substr(0, 2) == "OP")
+                    continue;
+                bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
+                tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
+            }
         }
     }
-}
 
-void tieoff_dcu_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
-{
-    for (auto port : ci->ports) {
-        if (port.second.net == nullptr && port.second.type == PORT_IN) {
-            if (port.first.str(ctx).find("CLK") != std::string::npos ||
-                port.first.str(ctx).find("HDIN") != std::string::npos ||
-                port.first.str(ctx).find("HDOUT") != std::string::npos)
-                continue;
-            bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
-            tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
+    void tieoff_dcu_ports(CellInfo *ci)
+    {
+        for (auto port : ci->ports) {
+            if (port.second.net == nullptr && port.second.type == PORT_IN) {
+                if (port.first.str(ctx).find("CLK") != std::string::npos ||
+                    port.first.str(ctx).find("HDIN") != std::string::npos ||
+                    port.first.str(ctx).find("HDOUT") != std::string::npos)
+                    continue;
+                bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
+                tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
+            }
         }
     }
-}
 
-static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
-{
-    std::string tile = ctx->get_pip_tilename(pip);
-    std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
-    std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
-    cc.tiles[tile].add_arc(sink, source);
-}
+    void set_pip(PipId pip)
+    {
+        std::string tile = ctx->get_pip_tilename(pip);
+        std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
+        std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip));
+        cc.tiles[tile].add_arc(sink, source);
+    }
 
-static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
-{
-    std::array<std::vector<unsigned>, 4> phys_to_log;
-    const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
-    for (unsigned i = 0; i < 4; i++) {
-        WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
-        for (PipId pip : ctx->getPipsUphill(pin_wire)) {
-            if (!ctx->getBoundPipNet(pip))
-                continue;
-            unsigned lp = ctx->loc_info(pip)->pip_data[pip.index].lutperm_flags;
-            if (!is_lutperm_pip(lp)) { // non-permuting
-                phys_to_log[i].push_back(i);
-            } else { // permuting
-                unsigned from_pin = lutperm_in(lp);
-                unsigned to_pin = lutperm_out(lp);
-                NPNR_ASSERT(to_pin == i);
-                phys_to_log[from_pin].push_back(i);
+    unsigned permute_lut(CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
+    {
+        std::array<std::vector<unsigned>, 4> phys_to_log;
+        const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
+        for (unsigned i = 0; i < 4; i++) {
+            WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
+            for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+                if (!ctx->getBoundPipNet(pip))
+                    continue;
+                unsigned lp = ctx->loc_info(pip)->pip_data[pip.index].lutperm_flags;
+                if (!is_lutperm_pip(lp)) { // non-permuting
+                    phys_to_log[i].push_back(i);
+                } else { // permuting
+                    unsigned from_pin = lutperm_in(lp);
+                    unsigned to_pin = lutperm_out(lp);
+                    NPNR_ASSERT(to_pin == i);
+                    phys_to_log[from_pin].push_back(i);
+                }
             }
         }
-    }
-    for (unsigned i = 0; i < 4; i++)
-        if (!phys_to_log.at(i).empty())
-            used_phys_pins.insert(ports.at(i));
-    if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
-        // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
-        for (unsigned i = 0; i < 4; i++) {
+        for (unsigned i = 0; i < 4; i++)
             if (!phys_to_log.at(i).empty())
-                continue;
-            for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
-                if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
-                    phys_to_log.at(i).push_back(j);
+                used_phys_pins.insert(ports.at(i));
+        if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
+            // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
+            for (unsigned i = 0; i < 4; i++) {
+                if (!phys_to_log.at(i).empty())
+                    continue;
+                for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
+                    if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
+                        phys_to_log.at(i).push_back(j);
+                }
             }
         }
-    }
-    unsigned permuted_init = 0;
-    for (unsigned i = 0; i < 16; i++) {
-        unsigned log_idx = 0;
-        for (unsigned j = 0; j < 4; j++) {
-            if ((i >> j) & 0x1) {
-                for (auto log_pin : phys_to_log[j])
-                    log_idx |= (1 << log_pin);
+        unsigned permuted_init = 0;
+        for (unsigned i = 0; i < 16; i++) {
+            unsigned log_idx = 0;
+            for (unsigned j = 0; j < 4; j++) {
+                if ((i >> j) & 0x1) {
+                    for (auto log_pin : phys_to_log[j])
+                        log_idx |= (1 << log_pin);
+                }
             }
+            if ((orig_init >> log_idx) & 0x1)
+                permuted_init |= (1 << i);
         }
-        if ((orig_init >> log_idx) & 0x1)
-            permuted_init |= (1 << i);
+        return permuted_init;
     }
-    return permuted_init;
-}
 
-static std::vector<bool> parse_config_str(const Property &p, int length)
-{
-    std::vector<bool> word;
-    if (p.is_string) {
-        std::string str = p.as_string();
-        // For DCU config which might be bin, hex or dec using prefixes accordingly
-        std::string base = str.substr(0, 2);
-        word.resize(length, false);
-        if (base == "0b") {
-            for (int i = 0; i < int(str.length()) - 2; i++) {
-                char c = str.at((str.size() - 1) - i);
-                if (!(c == '0' || c == '1'))
-                    log_error("binary string has invalid char '%c' at position %d.\n", c, i);
-                word.at(i) = (c == '1');
-            }
-        } else if (base == "0x") {
-            for (int i = 0; i < int(str.length()) - 2; i++) {
-                char c = str.at((str.size() - i) - 1);
-                int nibble = chtohex(c);
-                if (nibble == (int)std::string::npos)
-                    log_error("hex string has invalid char '%c' at position %d.\n", c, i);
-                word.at(i * 4) = nibble & 0x1;
-                if (i * 4 + 1 < length)
-                    word.at(i * 4 + 1) = nibble & 0x2;
-                if (i * 4 + 2 < length)
-                    word.at(i * 4 + 2) = nibble & 0x4;
-                if (i * 4 + 3 < length)
-                    word.at(i * 4 + 3) = nibble & 0x8;
+    std::vector<bool> parse_config_str(const Property &p, int length)
+    {
+        std::vector<bool> word;
+        if (p.is_string) {
+            std::string str = p.as_string();
+            // For DCU config which might be bin, hex or dec using prefixes accordingly
+            std::string base = str.substr(0, 2);
+            word.resize(length, false);
+            if (base == "0b") {
+                for (int i = 0; i < int(str.length()) - 2; i++) {
+                    char c = str.at((str.size() - 1) - i);
+                    if (!(c == '0' || c == '1'))
+                        log_error("binary string has invalid char '%c' at position %d.\n", c, i);
+                    word.at(i) = (c == '1');
+                }
+            } else if (base == "0x") {
+                for (int i = 0; i < int(str.length()) - 2; i++) {
+                    char c = str.at((str.size() - i) - 1);
+                    int nibble = chtohex(c);
+                    if (nibble == (int)std::string::npos)
+                        log_error("hex string has invalid char '%c' at position %d.\n", c, i);
+                    word.at(i * 4) = nibble & 0x1;
+                    if (i * 4 + 1 < length)
+                        word.at(i * 4 + 1) = nibble & 0x2;
+                    if (i * 4 + 2 < length)
+                        word.at(i * 4 + 2) = nibble & 0x4;
+                    if (i * 4 + 3 < length)
+                        word.at(i * 4 + 3) = nibble & 0x8;
+                }
+            } else if (base == "0d") {
+                NPNR_ASSERT(length < 64);
+                unsigned long long value = std::stoull(str.substr(2));
+                for (int i = 0; i < length; i++)
+                    if (value & (1 << i))
+                        word.at(i) = true;
+            } else {
+                NPNR_ASSERT(length < 64);
+                unsigned long long value = std::stoull(str);
+                for (int i = 0; i < length; i++)
+                    if (value & (1 << i))
+                        word.at(i) = true;
             }
-        } else if (base == "0d") {
-            NPNR_ASSERT(length < 64);
-            unsigned long long value = std::stoull(str.substr(2));
-            for (int i = 0; i < length; i++)
-                if (value & (1 << i))
-                    word.at(i) = true;
         } else {
-            NPNR_ASSERT(length < 64);
-            unsigned long long value = std::stoull(str);
-            for (int i = 0; i < length; i++)
-                if (value & (1 << i))
-                    word.at(i) = true;
+            word = p.as_bits();
+            word.resize(length, 0);
         }
-    } else {
-        word = p.as_bits();
-        word.resize(length, 0);
-    }
-
-    return word;
-}
 
-std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString &key, std::string def = "0")
-{
-    auto found = ct.find(key);
-    if (found == ct.end())
-        return def;
-    else {
-        if (found->second.is_string)
-            return found->second.as_string();
-        else
-            return std::to_string(found->second.as_int64());
+        return word;
     }
-};
-
-void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
-{
-    ChipConfig cc;
-
-    std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
 
-    if (!base_config_file.empty()) {
-        std::ifstream config_file(base_config_file);
-        if (!config_file) {
-            log_error("failed to open base config file '%s'\n", base_config_file.c_str());
-        }
-        config_file >> cc;
-    } else {
-        switch (ctx->args.type) {
-        case ArchArgs::LFE5U_12F:
-            BaseConfigs::config_empty_lfe5u_25f(cc);
-            cc.chip_name = "LFE5U-12F";
-            break;
-        case ArchArgs::LFE5U_25F:
-            BaseConfigs::config_empty_lfe5u_25f(cc);
-            break;
-        case ArchArgs::LFE5U_45F:
-            BaseConfigs::config_empty_lfe5u_45f(cc);
-            break;
-        case ArchArgs::LFE5U_85F:
-            BaseConfigs::config_empty_lfe5u_85f(cc);
-            break;
-        case ArchArgs::LFE5UM_25F:
-            BaseConfigs::config_empty_lfe5um_25f(cc);
-            break;
-        case ArchArgs::LFE5UM_45F:
-            BaseConfigs::config_empty_lfe5um_45f(cc);
-            break;
-        case ArchArgs::LFE5UM_85F:
-            BaseConfigs::config_empty_lfe5um_85f(cc);
-            break;
-        case ArchArgs::LFE5UM5G_25F:
-            BaseConfigs::config_empty_lfe5um5g_25f(cc);
-            break;
-        case ArchArgs::LFE5UM5G_45F:
-            BaseConfigs::config_empty_lfe5um5g_45f(cc);
-            break;
-        case ArchArgs::LFE5UM5G_85F:
-            BaseConfigs::config_empty_lfe5um5g_85f(cc);
-            break;
-        default:
-            NPNR_ASSERT_FALSE("Unsupported device type");
+    std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString &key, std::string def = "0")
+    {
+        auto found = ct.find(key);
+        if (found == ct.end())
+            return def;
+        else {
+            if (found->second.is_string)
+                return found->second.as_string();
+            else
+                return std::to_string(found->second.as_int64());
         }
-    }
-
-    cc.metadata.push_back("Part: " + ctx->get_full_chip_name());
+    };
 
-    // Clear out DCU tieoffs in base config if DCU used
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->type == id_DCUA) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            for (int i = 0; i < 12; i++) {
-                auto tiles = ctx->get_tiles_at_loc(loc.y - 1, loc.x + i);
-                for (const auto &tile : tiles) {
-                    auto cc_tile = cc.tiles.find(tile.first);
-                    if (cc_tile != cc.tiles.end()) {
-                        cc_tile->second.cenums.clear();
-                        cc_tile->second.cunknowns.clear();
+    dict<int, IOVoltage> bankVcc;
+    dict<int, bool> bankLvds, bankVref, bankDiff;
+    void init_io_banks()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) {
+                int bank = ctx->get_pio_bel_bank(ci->bel);
+                std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+                std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+
+                if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
+                    IOVoltage vcc = get_vccio(ioType_from_str(iotype));
+                    if (bankVcc.find(bank) != bankVcc.end()) {
+                        // TODO: strong and weak constraints
+                        if (bankVcc[bank] != vcc) {
+                            log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
+                                      cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
+                                      iovoltage_to_str(vcc).c_str(), bank);
+                        }
+                    } else {
+                        bankVcc[bank] = vcc;
                     }
                 }
+
+                if (iotype == "LVDS")
+                    bankLvds[bank] = true;
+                if ((dir == "INPUT" || dir == "BIDIR") && is_differential(ioType_from_str(iotype)))
+                    bankDiff[bank] = true;
+                if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
+                    bankVref[bank] = true;
             }
         }
-    }
-    // Add all set, configurable pips to the config
-    for (auto pip : ctx->getPips()) {
-        if (ctx->getBoundPipNet(pip) != nullptr) {
-            if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
-                std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
-                if (source.find("CLKI_PLL") != std::string::npos) {
-                    // Special case - must set pip in all relevant tiles
-                    for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
-                        if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
-                            set_pip(ctx, cc, equiv_pip);
+
+        // Set all bankref tiles to appropriate VccIO
+        for (int y = 0; y < ctx->getGridDimY(); y++) {
+            for (int x = 0; x < ctx->getGridDimX(); x++) {
+                auto tiles = ctx->get_tiles_at_loc(y, x);
+                for (auto tile : tiles) {
+                    std::string type = tile.second;
+                    if (type.find("BANKREF") != std::string::npos) {
+                        int bank = std::stoi(type.substr(7));
+                        if (bank == 8 && ctx->settings.count(ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"))) {
+                            std::string vcc = str_or_default(ctx->settings, ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"));
+                            vcc.at(1) = 'V';
+                            cc.tiles[tile.first].add_enum("BANK.VCCIO", vcc);
+                        } else if (bankVcc.find(bank) != bankVcc.end()) {
+                            if (bankVcc[bank] == IOVoltage::VCC_1V35)
+                                cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
+                            else
+                                cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+                        }
+                        if (bankLvds[bank]) {
+                            cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                            cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
+                        }
+                        if (bankDiff[bank]) {
+                            cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                        }
+                        if (bankVref[bank]) {
+                            cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                            cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
+                        }
                     }
-                } else {
-                    set_pip(ctx, cc, pip);
                 }
             }
         }
-    }
-    // Find bank voltages
-    dict<int, IOVoltage> bankVcc;
-    dict<int, bool> bankLvds, bankVref, bankDiff;
 
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) {
-            int bank = ctx->get_pio_bel_bank(ci->bel);
-            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
-            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
-
-            if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
-                IOVoltage vcc = get_vccio(ioType_from_str(iotype));
-                if (bankVcc.find(bank) != bankVcc.end()) {
-                    // TODO: strong and weak constraints
-                    if (bankVcc[bank] != vcc) {
-                        log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
-                                  cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
-                                  iovoltage_to_str(vcc).c_str(), bank);
-                    }
-                } else {
-                    bankVcc[bank] = vcc;
-                }
+        // Create dummy outputs used as Vref input buffer for banks where Vref is used
+        for (auto bv : bankVref) {
+            if (!bv.second)
+                continue;
+            BelId vrefIO = ctx->get_pio_by_function_name(fmt_str("VREF1_" << bv.first));
+            if (vrefIO == BelId())
+                log_error("unable to find VREF input for bank %d\n", bv.first);
+            if (!ctx->checkBelAvail(vrefIO)) {
+                CellInfo *bound = ctx->getBoundBelCell(vrefIO);
+                if (bound != nullptr)
+                    log_error("VREF pin %s of bank %d is occupied by IO '%s'\n",
+                              ctx->get_bel_package_pin(vrefIO).c_str(), bv.first, bound->name.c_str(ctx));
+                else
+                    log_error("VREF pin %s of bank %d is unavailable\n", ctx->get_bel_package_pin(vrefIO).c_str(),
+                              bv.first);
+            }
+            log_info("Using pin %s as VREF for bank %d\n", ctx->get_bel_package_pin(vrefIO).c_str(), bv.first);
+            std::string pio_tile = get_pio_tile(vrefIO);
+
+            std::string iotype;
+            switch (bankVcc[bv.first]) {
+            case IOVoltage::VCC_1V2:
+                iotype = "HSUL12";
+                break;
+            case IOVoltage::VCC_1V35:
+                iotype = "SSTL18_I";
+                break;
+            case IOVoltage::VCC_1V5:
+                iotype = "SSTL18_I";
+                break;
+            case IOVoltage::VCC_1V8:
+                iotype = "SSTL18_I";
+                break;
+            default:
+                log_error("Referenced inputs are not supported with bank VccIO of %s.\n",
+                          iovoltage_to_str(bankVcc[bv.first]).c_str());
             }
 
-            if (iotype == "LVDS")
-                bankLvds[bank] = true;
-            if ((dir == "INPUT" || dir == "BIDIR") && is_differential(ioType_from_str(iotype)))
-                bankDiff[bank] = true;
-            if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
-                bankVref[bank] = true;
+            std::string pio = ctx->loc_info(vrefIO)->bel_data[vrefIO.index].name.get();
+            cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
+            cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
         }
     }
 
-    // Set all bankref tiles to appropriate VccIO
-    for (int y = 0; y < ctx->getGridDimY(); y++) {
-        for (int x = 0; x < ctx->getGridDimX(); x++) {
-            auto tiles = ctx->get_tiles_at_loc(y, x);
-            for (auto tile : tiles) {
-                std::string type = tile.second;
-                if (type.find("BANKREF") != std::string::npos) {
-                    int bank = std::stoi(type.substr(7));
-                    if (bank == 8 && ctx->settings.count(ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"))) {
-                        std::string vcc = str_or_default(ctx->settings, ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"));
-                        vcc.at(1) = 'V';
-                        cc.tiles[tile.first].add_enum("BANK.VCCIO", vcc);
-                    } else if (bankVcc.find(bank) != bankVcc.end()) {
-                        if (bankVcc[bank] == IOVoltage::VCC_1V35)
-                            cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
-                        else
-                            cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
-                    }
-                    if (bankLvds[bank]) {
-                        cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
-                        cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
-                    }
-                    if (bankDiff[bank]) {
-                        cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
-                    }
-                    if (bankVref[bank]) {
-                        cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
-                        cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
-                    }
-                }
+    void write_comb(CellInfo *ci)
+    {
+        pool<IdString> used_phys_pins;
+        BelId bel = ci->bel;
+        std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+        int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+        std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+        std::string lc = std::to_string(z % 2);
+        std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+        if (mode == "RAMW_BLOCK")
+            return;
+        int lut_init = int_or_default(ci->params, id_INITVAL);
+        cc.tiles[tname].add_enum(slice + ".MODE", mode);
+        cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
+                                 int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
+        if (mode == "CCU2") {
+            cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
+        } else {
+            // Don't interfere with cascade mux wiring
+            cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
+        }
+        if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
+            cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
+            std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+            wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
+            cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+        }
+        for (auto input : {id_A, id_B, id_C, id_D}) {
+            if (!used_phys_pins.count(input)) {
+                cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + lc + "MUX", "1");
             }
         }
     }
 
-    // Create dummy outputs used as Vref input buffer for banks where Vref is used
-    for (auto bv : bankVref) {
-        if (!bv.second)
-            continue;
-        BelId vrefIO = ctx->get_pio_by_function_name(fmt_str("VREF1_" << bv.first));
-        if (vrefIO == BelId())
-            log_error("unable to find VREF input for bank %d\n", bv.first);
-        if (!ctx->checkBelAvail(vrefIO)) {
-            CellInfo *bound = ctx->getBoundBelCell(vrefIO);
-            if (bound != nullptr)
-                log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->get_bel_package_pin(vrefIO).c_str(),
-                          bv.first, bound->name.c_str(ctx));
-            else
-                log_error("VREF pin %s of bank %d is unavailable\n", ctx->get_bel_package_pin(vrefIO).c_str(),
-                          bv.first);
+    void write_ff(CellInfo *ci)
+    {
+        BelId bel = ci->bel;
+        std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+        int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+        std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+        std::string lc = std::to_string(z % 2);
+
+        cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+        cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
+        cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+        cc.tiles[tname].add_enum(slice + ".REG" + lc + ".LSRMODE", str_or_default(ci->params, id_LSRMODE, "LSR"));
+
+        cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+
+        NetInfo *lsrnet = ci->getPort(id_LSR);
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
+            cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+            cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
         }
-        log_info("Using pin %s as VREF for bank %d\n", ctx->get_bel_package_pin(vrefIO).c_str(), bv.first);
-        std::string pio_tile = get_pio_tile(ctx, vrefIO);
-
-        std::string iotype;
-        switch (bankVcc[bv.first]) {
-        case IOVoltage::VCC_1V2:
-            iotype = "HSUL12";
-            break;
-        case IOVoltage::VCC_1V35:
-            iotype = "SSTL18_I";
-            break;
-        case IOVoltage::VCC_1V5:
-            iotype = "SSTL18_I";
-            break;
-        case IOVoltage::VCC_1V8:
-            iotype = "SSTL18_I";
-            break;
-        default:
-            log_error("Referenced inputs are not supported with bank VccIO of %s.\n",
-                      iovoltage_to_str(bankVcc[bv.first]).c_str());
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
+            cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+            cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
         }
 
-        std::string pio = ctx->loc_info(vrefIO)->bel_data[vrefIO.index].name.get();
-        cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
-        cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+        NetInfo *clknet = ci->getPort(id_CLK);
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
+            cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
+        }
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
+            cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
+        }
     }
 
-    // Configure slices
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->bel == BelId()) {
-            log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
-        }
+    std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
+
+    void write_io(CellInfo *ci)
+    {
         BelId bel = ci->bel;
-        if (ci->type == id_TRELLIS_COMB) {
-            pool<IdString> used_phys_pins;
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
-            int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-            std::string lc = std::to_string(z % 2);
-            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
-            if (mode == "RAMW_BLOCK")
-                continue;
-            int lut_init = int_or_default(ci->params, id_INITVAL);
-            cc.tiles[tname].add_enum(slice + ".MODE", mode);
-            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
-                                     int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16));
-            if (mode == "CCU2") {
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc,
-                                         str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
+        std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+        std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+        std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+        std::string pio_tile = get_pio_tile(bel);
+        std::string pic_tile = get_pic_tile(bel);
+        cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+        cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+        if (is_differential(ioType_from_str(iotype))) {
+            if (bel.location.y == 0) {
+                // Pseudo differential top IO
+                if (dir != "OUTPUT")
+                    log_error("Pseudo-differential IO '%s' must be output\n", ctx->nameOf(ci));
+                if (pio != "PIOA")
+                    log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n", ctx->nameOf(ci));
+                std::string cpio_tile = get_comp_pio_tile(bel);
+                std::string cpic_tile = get_comp_pic_tile(bel);
+                cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+                cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
             } else {
-                // Don't interfere with cascade mux wiring
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
-            }
-            if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
-                cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
-                std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
-                wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
-                cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
-            }
-            for (auto input : {id_A, id_B, id_C, id_D}) {
-                if (!used_phys_pins.count(input)) {
-                    cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + lc + "MUX", "1");
-                }
-            }
-        } else if (ci->type == id_TRELLIS_FF) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
-            int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-            std::string lc = std::to_string(z % 2);
-
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".LSRMODE", str_or_default(ci->params, id_LSRMODE, "LSR"));
-
-            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
-
-            NetInfo *lsrnet = ci->getPort(id_LSR);
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-                cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-                cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-            }
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-                cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-                cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+                // Explicitly disable other pair
+                std::string other;
+                if (pio == "PIOA")
+                    other = "PIOB";
+                else if (pio == "PIOC")
+                    other = "PIOD";
+                else
+                    log_error("cannot place differential IO at location %s\n", pio.c_str());
+                // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+                // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+                cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
+                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
             }
 
-            NetInfo *clknet = ci->getPort(id_CLK);
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-                cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
-            }
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-                cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
-            }
-        } else if (ci->type == id_TRELLIS_RAMW) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
-            cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
-            cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
-            cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
-        } else if (ci->type == id_TRELLIS_IO) {
-            std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
-            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
-            std::string pio_tile = get_pio_tile(ctx, bel);
-            std::string pic_tile = get_pic_tile(ctx, bel);
-            cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-            cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-            if (is_differential(ioType_from_str(iotype))) {
+        } else if (is_referenced(ioType_from_str(iotype))) {
+            cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+        }
+        if (dir != "INPUT" && (ci->ports.find(id_T) == ci->ports.end() || ci->ports.at(id_T).net == nullptr) &&
+            (ci->ports.find(id_IOLTO) == ci->ports.end() || ci->ports.at(id_IOLTO).net == nullptr)) {
+            // Tie tristate low if unconnected for outputs or bidir
+            WireId jpt_wire = ctx->get_wire_by_loc_basename(bel.location, fmt_str("JPADDT" << pio.back()));
+            PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
+            WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
+            std::string cib_tile = ctx->get_tile_by_type_loc(cib_wire.location.y, cib_wire.location.x, cib_tiles);
+            std::string cib_wirename = ctx->loc_info(cib_wire)->wire_data[cib_wire.index].name.get();
+            cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
+        }
+        if ((dir == "INPUT" || dir == "BIDIR") && !is_differential(ioType_from_str(iotype)) &&
+            !is_referenced(ioType_from_str(iotype))) {
+            cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", str_or_default(ci->attrs, id_HYSTERESIS, "ON"));
+        }
+        if (ci->attrs.count(id_SLEWRATE) && !is_referenced(ioType_from_str(iotype)))
+            cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, id_SLEWRATE, "SLOW"));
+        if (ci->attrs.count(id_PULLMODE))
+            cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, id_PULLMODE, "NONE"));
+        if (ci->attrs.count(id_DIFFRESISTOR))
+            cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", str_or_default(ci->attrs, id_DIFFRESISTOR, "OFF"));
+        if (ci->attrs.count(id_CLAMP))
+            cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, id_CLAMP, "OFF"));
+
+        if (ci->attrs.count(id_DRIVE)) {
+            static bool drive_3v3_warning_done = false;
+            if (iotype == "LVCMOS33") {
+                cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "8"));
+            } else if (iotype == "LVCMOS33D") {
                 if (bel.location.y == 0) {
                     // Pseudo differential top IO
-                    if (dir != "OUTPUT")
-                        log_error("Pseudo-differential IO '%s' must be output\n", ctx->nameOf(ci));
-                    if (pio != "PIOA")
-                        log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n",
-                                  ctx->nameOf(ci));
-                    std::string cpio_tile = get_comp_pio_tile(ctx, bel);
-                    std::string cpic_tile = get_comp_pic_tile(ctx, bel);
-                    cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-                    cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+                    NPNR_ASSERT(dir == "OUTPUT");
+                    NPNR_ASSERT(pio == "PIOA");
+                    std::string cpio_tile = get_comp_pio_tile(bel);
+                    cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+                    cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
                 } else {
-                    // Explicitly disable other pair
                     std::string other;
                     if (pio == "PIOA")
                         other = "PIOB";
                     else if (pio == "PIOC")
                         other = "PIOD";
                     else
-                        log_error("cannot place differential IO at location %s\n", pio.c_str());
-                    // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
-                    // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
-                    cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
-                    cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
-                }
-
-            } else if (is_referenced(ioType_from_str(iotype))) {
-                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
-            }
-            if (dir != "INPUT" && (ci->ports.find(id_T) == ci->ports.end() || ci->ports.at(id_T).net == nullptr) &&
-                (ci->ports.find(id_IOLTO) == ci->ports.end() || ci->ports.at(id_IOLTO).net == nullptr)) {
-                // Tie tristate low if unconnected for outputs or bidir
-                WireId jpt_wire = ctx->get_wire_by_loc_basename(bel.location, fmt_str("JPADDT" << pio.back()));
-                PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
-                WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
-                std::string cib_tile = ctx->get_tile_by_type_loc(cib_wire.location.y, cib_wire.location.x, cib_tiles);
-                std::string cib_wirename = ctx->loc_info(cib_wire)->wire_data[cib_wire.index].name.get();
-                cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
-            }
-            if ((dir == "INPUT" || dir == "BIDIR") && !is_differential(ioType_from_str(iotype)) &&
-                !is_referenced(ioType_from_str(iotype))) {
-                cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", str_or_default(ci->attrs, id_HYSTERESIS, "ON"));
-            }
-            if (ci->attrs.count(id_SLEWRATE) && !is_referenced(ioType_from_str(iotype)))
-                cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, id_SLEWRATE, "SLOW"));
-            if (ci->attrs.count(id_PULLMODE))
-                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, id_PULLMODE, "NONE"));
-            if (ci->attrs.count(id_DIFFRESISTOR))
-                cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", str_or_default(ci->attrs, id_DIFFRESISTOR, "OFF"));
-            if (ci->attrs.count(id_CLAMP))
-                cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, id_CLAMP, "OFF"));
-
-            if (ci->attrs.count(id_DRIVE)) {
-                static bool drive_3v3_warning_done = false;
-                if (iotype == "LVCMOS33") {
-                    cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "8"));
-                } else if (iotype == "LVCMOS33D") {
-                    if (bel.location.y == 0) {
-                        // Pseudo differential top IO
-                        NPNR_ASSERT(dir == "OUTPUT");
-                        NPNR_ASSERT(pio == "PIOA");
-                        std::string cpio_tile = get_comp_pio_tile(ctx, bel);
-                        cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
-                        cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
-                    } else {
-                        std::string other;
-                        if (pio == "PIOA")
-                            other = "PIOB";
-                        else if (pio == "PIOC")
-                            other = "PIOD";
-                        else
-                            log_error("cannot set DRIVE on differential IO at location %s\n", pio.c_str());
-                        cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
-                        cc.tiles[pio_tile].add_enum(other + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
-                    }
-                } else {
-                    if (!drive_3v3_warning_done)
-                        log_warning("Trellis limitation: DRIVE can only be set on 3V3 IO pins.\n");
-                    drive_3v3_warning_done = true;
+                        log_error("cannot set DRIVE on differential IO at location %s\n", pio.c_str());
+                    cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+                    cc.tiles[pio_tile].add_enum(other + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
                 }
+            } else {
+                if (!drive_3v3_warning_done)
+                    log_warning("Trellis limitation: DRIVE can only be set on 3V3 IO pins.\n");
+                drive_3v3_warning_done = true;
             }
-            if (ci->attrs.count(id_TERMINATION)) {
-                auto vccio = get_vccio(ioType_from_str(iotype));
-                switch (vccio) {
-                case IOVoltage::VCC_1V8:
-                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
-                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
-                    break;
-                case IOVoltage::VCC_1V5:
-                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
-                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
-                    break;
-                case IOVoltage::VCC_1V35:
-                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
-                                                str_or_default(ci->attrs, id_TERMINATION, "OFF"));
-                    break;
-                default:
-                    log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
-                              iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
-                }
+        }
+        if (ci->attrs.count(id_TERMINATION)) {
+            auto vccio = get_vccio(ioType_from_str(iotype));
+            switch (vccio) {
+            case IOVoltage::VCC_1V8:
+                cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8", str_or_default(ci->attrs, id_TERMINATION, "OFF"));
+                break;
+            case IOVoltage::VCC_1V5:
+                cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5", str_or_default(ci->attrs, id_TERMINATION, "OFF"));
+                break;
+            case IOVoltage::VCC_1V35:
+                cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
+                                            str_or_default(ci->attrs, id_TERMINATION, "OFF"));
+                break;
+            default:
+                log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n", iovoltage_to_str(vccio).c_str(),
+                          ci->name.c_str(ctx));
             }
-            if (ci->attrs.count(id_OPENDRAIN)) {
-                cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
-                if (is_differential(ioType_from_str(iotype))) {
-                    std::string other;
-                    if (pio == "PIOA")
-                        other = "PIOB";
-                    else if (pio == "PIOC")
-                        other = "PIOD";
-                    else
-                        log_error("cannot set OPENDRAIN on differential IO at location %s\n", pio.c_str());
-                    cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
-                }
+        }
+        if (ci->attrs.count(id_OPENDRAIN)) {
+            cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
+            if (is_differential(ioType_from_str(iotype))) {
+                std::string other;
+                if (pio == "PIOA")
+                    other = "PIOB";
+                else if (pio == "PIOC")
+                    other = "PIOD";
+                else
+                    log_error("cannot set OPENDRAIN on differential IO at location %s\n", pio.c_str());
+                cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
             }
+        }
 
-            std::string datamux_oddr = str_or_default(ci->params, id_DATAMUX_ODDR, "PADDO");
-            if (datamux_oddr != "PADDO")
-                cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
-            std::string datamux_oreg = str_or_default(ci->params, id_DATAMUX_OREG, "PADDO");
-            if (datamux_oreg != "PADDO")
-                cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
-            std::string datamux_mddr = str_or_default(ci->params, id_DATAMUX_MDDR, "PADDO");
-            if (datamux_mddr != "PADDO")
-                cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
-            std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT");
-            if (trimux_tsreg != "PADDT")
-                cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
-        } else if (ci->type == id_DCCA) {
-            const NetInfo *cen = ci->getPort(id_CE);
-            if (cen != nullptr) {
-                std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-                Loc loc = ctx->getBelLocation(bel);
-                TileGroup tg;
-                switch (belname[0]) {
-                case 'B':
-                    tg.tiles.push_back(
-                            ctx->get_tile_by_type_loc(loc.y, loc.x, std::set<std::string>{"BMID_0H", "BMID_0V"}));
-                    tg.tiles.push_back(
-                            ctx->get_tile_by_type_loc(loc.y, loc.x + 1, std::set<std::string>{"BMID_2", "BMID_2V"}));
-                    break;
-                case 'T':
-                    tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "TMID_0"));
-                    tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "TMID_1"));
-                    break;
-                case 'L':
-                    tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "LMID_0"));
-                    break;
-                case 'R':
-                    tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "RMID_0"));
-                    break;
-                default:
-                    NPNR_ASSERT_FALSE("bad DCC for gating");
-                    break;
-                }
-                tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
-                cc.tilegroups.push_back(tg);
-            }
-        } else if (ci->type == id_DCSC) {
-            std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
-            std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles);
-            std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
-        } else if (ci->type == id_DP16KD) {
-            TileGroup tg;
-            Loc loc = ctx->getBelLocation(ci->bel);
-            tg.tiles = get_bram_tiles(ctx, ci->bel);
-            std::string ebr = "EBR" + std::to_string(loc.z);
+        std::string datamux_oddr = str_or_default(ci->params, id_DATAMUX_ODDR, "PADDO");
+        if (datamux_oddr != "PADDO")
+            cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
+        std::string datamux_oreg = str_or_default(ci->params, id_DATAMUX_OREG, "PADDO");
+        if (datamux_oreg != "PADDO")
+            cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
+        std::string datamux_mddr = str_or_default(ci->params, id_DATAMUX_MDDR, "PADDO");
+        if (datamux_mddr != "PADDO")
+            cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
+        std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT");
+        if (trimux_tsreg != "PADDT")
+            cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
+    }
 
-            if (ci->ramInfo.is_pdp) {
-                tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
-                tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R",
-                                   intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
-            } else {
-                tg.config.add_enum(ebr + ".MODE", "DP16KD");
-                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
-                tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
-                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
-                tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
+    void write_dcc(CellInfo *ci)
+    {
+        const NetInfo *cen = ci->getPort(id_CE);
+        if (cen != nullptr) {
+            std::string belname = ctx->loc_info(ci->bel)->bel_data[ci->bel.index].name.get();
+            Loc loc = ctx->getBelLocation(ci->bel);
+            TileGroup tg;
+            switch (belname[0]) {
+            case 'B':
+                tg.tiles.push_back(
+                        ctx->get_tile_by_type_loc(loc.y, loc.x, std::set<std::string>{"BMID_0H", "BMID_0V"}));
+                tg.tiles.push_back(
+                        ctx->get_tile_by_type_loc(loc.y, loc.x + 1, std::set<std::string>{"BMID_2", "BMID_2V"}));
+                break;
+            case 'T':
+                tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "TMID_0"));
+                tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, "TMID_1"));
+                break;
+            case 'L':
+                tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "LMID_0"));
+                break;
+            case 'R':
+                tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "RMID_0"));
+                break;
+            default:
+                NPNR_ASSERT_FALSE("bad DCC for gating");
+                break;
             }
+            tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
+            cc.tilegroups.push_back(tg);
+        }
+    }
 
-            auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
-                 csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
+    void write_bram(CellInfo *ci)
+    {
+        TileGroup tg;
+        Loc loc = ctx->getBelLocation(ci->bel);
+        tg.tiles = get_bram_tiles(ci->bel);
+        std::string ebr = "EBR" + std::to_string(loc.z);
 
-            tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
-            tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
+        if (ci->ramInfo.is_pdp) {
+            tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
+            tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R", intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
+        } else {
+            tg.config.add_enum(ebr + ".MODE", "DP16KD");
+            tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
+            tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
+            tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
+            tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
+        }
 
-            tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
-            tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE",
-                               str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
-            tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+        auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
+             csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
 
-            tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9));
+        tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
+        tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
 
-            // Tie signals as appropriate
-            for (auto port : ci->ports) {
-                if (ci->ramInfo.is_pdp && (port.first.in(id_WEA, id_WEB, id_ADA4)))
-                    continue;
-                if (port.second.net == nullptr && port.second.type == PORT_IN) {
-                    if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) {
-                        // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
-                        // If MUX doesn't exist, set to INV to emulate default 0
-                        tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
-                        if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
-                            ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
-                    } else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) {
-                        // CIB CE. Tie to "1" in CIB
-                        // If MUX doesn't exist, set to passthru to emulate default 1
-                        tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
-                        if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
-                            ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
-                    } else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) {
-                        // CIB CE. Tie to "1" in CIB.
-                        // If MUX doesn't exist, set to INV to emulate default 0
-                        tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
-                        if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
-                            ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
-                    } else {
-                        // CIB ABCD signal
-                        // Tie signals low unless explicit MUX param specified
-                        bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
-                        tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
-                    }
+        tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
+        tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE", str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
+        tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+
+        tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9));
+
+        // Tie signals as appropriate
+        for (auto port : ci->ports) {
+            if (ci->ramInfo.is_pdp && (port.first.in(id_WEA, id_WEB, id_ADA4)))
+                continue;
+            if (port.second.net == nullptr && port.second.type == PORT_IN) {
+                if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) {
+                    // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
+                    // If MUX doesn't exist, set to INV to emulate default 0
+                    tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
+                    if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+                        ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
+                } else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) {
+                    // CIB CE. Tie to "1" in CIB
+                    // If MUX doesn't exist, set to passthru to emulate default 1
+                    tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
+                    if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+                        ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
+                } else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) {
+                    // CIB CE. Tie to "1" in CIB.
+                    // If MUX doesn't exist, set to INV to emulate default 0
+                    tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
+                    if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+                        ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
+                } else {
+                    // CIB ABCD signal
+                    // Tie signals low unless explicit MUX param specified
+                    bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
+                    tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
                 }
             }
+        }
 
-            // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
-            for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
-                for (int bit = 0; bit < 3; bit++) {
-                    std::string sig = port.first + std::to_string(bit);
-                    if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
-                        port.second.at(bit) = !port.second.at(bit);
-                }
+        // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
+        for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
+            for (int bit = 0; bit < 3; bit++) {
+                std::string sig = port.first + std::to_string(bit);
+                if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
+                    port.second.at(bit) = !port.second.at(bit);
             }
+        }
 
-            tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, id_CLKAMUX, "CLKA"));
-            tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, id_CLKBMUX, "CLKB"));
+        tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, id_CLKAMUX, "CLKA"));
+        tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, id_CLKBMUX, "CLKB"));
 
-            tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
-            tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
-            if (!ci->ramInfo.is_pdp) {
-                tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
-                tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
-            }
-            tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
-            tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
-            tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, id_OCEAMUX, "OCEA"));
-            tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, id_OCEBMUX, "OCEB"));
-
-            std::reverse(csd_a.begin(), csd_a.end());
-            std::reverse(csd_b.begin(), csd_b.end());
-
-            tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
-            tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
-
-            std::vector<uint16_t> init_data;
-            init_data.resize(2048, 0x0);
-            // INIT_00 .. INIT_3F
-            for (int i = 0; i <= 0x3F; i++) {
-                IdString param = ctx->id("INITVAL_" +
-                                         fmt_str(std::hex << std::uppercase << std::setw(2) << std::setfill('0') << i));
-                auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
-                for (int j = 0; j < 16; j++) {
-                    // INIT parameter consists of 16 18-bit words with 2-bit padding
-                    int ofs = 20 * j;
-                    for (int k = 0; k < 18; k++) {
-                        if (value.at(ofs + k))
-                            init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
-                    }
+        tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
+        tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
+        if (!ci->ramInfo.is_pdp) {
+            tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
+            tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
+        }
+        tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
+        tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
+        tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, id_OCEAMUX, "OCEA"));
+        tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, id_OCEBMUX, "OCEB"));
+
+        std::reverse(csd_a.begin(), csd_a.end());
+        std::reverse(csd_b.begin(), csd_b.end());
+
+        tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
+        tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
+
+        std::vector<uint16_t> init_data;
+        init_data.resize(2048, 0x0);
+        // INIT_00 .. INIT_3F
+        for (int i = 0; i <= 0x3F; i++) {
+            IdString param = ctx->idf("INITVAL_%02X", i);
+            auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
+            for (int j = 0; j < 16; j++) {
+                // INIT parameter consists of 16 18-bit words with 2-bit padding
+                int ofs = 20 * j;
+                for (int k = 0; k < 18; k++) {
+                    if (value.at(ofs + k))
+                        init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
                 }
             }
-            int wid = int_or_default(ci->attrs, id_WID, 0);
-            NPNR_ASSERT(!cc.bram_data.count(wid));
-            cc.bram_data[wid] = init_data;
-            cc.tilegroups.push_back(tg);
-        } else if (ci->type == id_MULT18X18D) {
-            TileGroup tg;
-            Loc loc = ctx->getBelLocation(ci->bel);
-            tg.tiles = get_dsp_tiles(ctx, ci->bel);
-            std::string dsp = "MULT18_" + std::to_string(loc.z);
-            tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, id_REG_INPUTA_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, id_REG_INPUTB_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, id_REG_INPUTB_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, id_REG_INPUTB_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, id_REG_INPUTC_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_CLK", str_or_default(ci->params, id_REG_PIPELINE_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, id_REG_PIPELINE_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_PIPELINE_RST", str_or_default(ci->params, id_REG_PIPELINE_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE"));
-            if (dsp == "MULT18_0" || dsp == "MULT18_4")
-                tg.config.add_enum(dsp + ".REG_OUTPUT_RST", str_or_default(ci->params, id_REG_OUTPUT_RST, "RST0"));
-
-            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, id_SOURCEB_MODE, "B_SHIFT"));
-            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
-
-            tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
-            if (str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE") == "NONE" && ci->cluster == ClusterId())
-                tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
-
-            if (loc.z < 4)
-                tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
-            else
-                tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
+        }
+        int wid = int_or_default(ci->attrs, id_WID, 0);
+        NPNR_ASSERT(!cc.bram_data.count(wid));
+        cc.bram_data[wid] = init_data;
+        cc.tilegroups.push_back(tg);
+    }
 
-            // Some muxes default to INV, make all pass-thru
-            for (auto port : {"CLK", "CE", "RST"}) {
-                for (int i = 0; i < 4; i++) {
-                    std::string sig = port + std::to_string(i);
-                    tg.config.add_enum(dsp + "." + sig + "MUX", sig);
-                }
+    void write_mult18(CellInfo *ci)
+    {
+        TileGroup tg;
+        Loc loc = ctx->getBelLocation(ci->bel);
+        tg.tiles = get_dsp_tiles(ci->bel);
+        std::string dsp = "MULT18_" + std::to_string(loc.z);
+        tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, id_REG_INPUTA_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, id_REG_INPUTB_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, id_REG_INPUTB_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, id_REG_INPUTB_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, id_REG_INPUTC_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_PIPELINE_CLK", str_or_default(ci->params, id_REG_PIPELINE_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, id_REG_PIPELINE_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_PIPELINE_RST", str_or_default(ci->params, id_REG_PIPELINE_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE"));
+        if (dsp == "MULT18_0" || dsp == "MULT18_4")
+            tg.config.add_enum(dsp + ".REG_OUTPUT_RST", str_or_default(ci->params, id_REG_OUTPUT_RST, "RST0"));
+
+        tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+        tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, id_SOURCEB_MODE, "B_SHIFT"));
+        tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
+
+        tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
+        if (str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE") == "NONE" && ci->cluster == ClusterId())
+            tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
+
+        if (loc.z < 4)
+            tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
+        else
+            tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
+
+        // Some muxes default to INV, make all pass-thru
+        for (auto port : {"CLK", "CE", "RST"}) {
+            for (int i = 0; i < 4; i++) {
+                std::string sig = port + std::to_string(i);
+                tg.config.add_enum(dsp + "." + sig + "MUX", sig);
             }
+        }
 
-            tieoff_dsp_ports(ctx, cc, ci);
-            cc.tilegroups.push_back(tg);
+        tieoff_dsp_ports(ci);
+        cc.tilegroups.push_back(tg);
+    }
 
-        } else if (ci->type == id_ALU54B) {
-            TileGroup tg;
-            Loc loc = ctx->getBelLocation(ci->bel);
-            tg.tiles = get_dsp_tiles(ctx, ci->bel);
-            std::string dsp = "ALU54_" + std::to_string(loc.z);
-            tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK",
-                               str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST",
-                               str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK",
-                               str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
-                               str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK",
-                               str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST",
-                               str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK", str_or_default(ci->params, id_REG_OPCODEIN_1_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE", str_or_default(ci->params, id_REG_OPCODEIN_1_CE, "CE0"));
-            tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST", str_or_default(ci->params, id_REG_OPCODEIN_1_RST, "RST0"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK", str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK", str_or_default(ci->params, id_REG_OUTPUT1_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE"));
-            tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC"));
-            tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC"));
-            tg.config.add_word(
-                    dsp + ".MASK01",
-                    parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"), 56, ci->name.c_str(ctx)));
-            tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
-            tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
-            tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"),
-                                                              56, ci->name.c_str(ctx)));
-            tg.config.add_word(dsp + ".MASKPAT",
-                               parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"), 56,
-                                              ci->name.c_str(ctx)));
-            tg.config.add_word(
-                    dsp + ".RNDPAT",
-                    parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"), 56, ci->name.c_str(ctx)));
-            tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
-            tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
-                               str_or_default(ci->params, id_FORCE_ZERO_BARREL_SHIFT, "DISABLED"));
-            tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, id_LEGACY, "DISABLED"));
-
-            tg.config.add_enum(dsp + ".MODE", "ALU54B");
-
-            if (loc.z < 4)
-                tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
-            else
-                tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
-            if (str_or_default(ci->params, id_REG_FLAG_CLK, "NONE") == "NONE") {
-                if (dsp == "ALU54_7") {
-                    tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
-                } else if (dsp == "ALU54_3") {
-                    tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
-                }
+    void write_alu54(CellInfo *ci)
+    {
+        TileGroup tg;
+        Loc loc = ctx->getBelLocation(ci->bel);
+        tg.tiles = get_dsp_tiles(ci->bel);
+        std::string dsp = "ALU54_" + std::to_string(loc.z);
+        tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK", str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST", str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK", str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK", str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK", str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST", str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK", str_or_default(ci->params, id_REG_OPCODEIN_1_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE", str_or_default(ci->params, id_REG_OPCODEIN_1_CE, "CE0"));
+        tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST", str_or_default(ci->params, id_REG_OPCODEIN_1_RST, "RST0"));
+        tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK", str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK", str_or_default(ci->params, id_REG_OUTPUT1_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE"));
+        tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC"));
+        tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC"));
+        tg.config.add_word(dsp + ".MASK01", parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"),
+                                                           56, ci->name.c_str(ctx)));
+        tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+        tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+        tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"), 56,
+                                                          ci->name.c_str(ctx)));
+        tg.config.add_word(dsp + ".MASKPAT", parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"),
+                                                            56, ci->name.c_str(ctx)));
+        tg.config.add_word(dsp + ".RNDPAT", parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"),
+                                                           56, ci->name.c_str(ctx)));
+        tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+        tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
+        tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
+                           str_or_default(ci->params, id_FORCE_ZERO_BARREL_SHIFT, "DISABLED"));
+        tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, id_LEGACY, "DISABLED"));
+
+        tg.config.add_enum(dsp + ".MODE", "ALU54B");
+
+        if (loc.z < 4)
+            tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
+        else
+            tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
+        if (str_or_default(ci->params, id_REG_FLAG_CLK, "NONE") == "NONE") {
+            if (dsp == "ALU54_7") {
+                tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
+            } else if (dsp == "ALU54_3") {
+                tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
             }
-            if (str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE") == "NONE") {
-                if (dsp == "ALU54_7") {
-                    tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
-                } else if (dsp == "ALU54_3") {
-                    tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON");
-                }
+        }
+        if (str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE") == "NONE") {
+            if (dsp == "ALU54_7") {
+                tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
+            } else if (dsp == "ALU54_3") {
+                tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON");
             }
-            tieoff_dsp_ports(ctx, cc, ci);
-            cc.tilegroups.push_back(tg);
-        } else if (ci->type == id_EHXPLLL) {
-            TileGroup tg;
-            tg.tiles = get_pll_tiles(ctx, ci->bel);
+        }
+        tieoff_dsp_ports(ci);
+        cc.tilegroups.push_back(tg);
+    }
+
+    void write_pll(CellInfo *ci)
+    {
+        TileGroup tg;
+        tg.tiles = get_pll_tiles(ci->bel);
+
+        tg.config.add_enum("MODE", "EHXPLLL");
 
-            tg.config.add_enum("MODE", "EHXPLLL");
+        tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKI_DIV, 1) - 1, 7));
+        tg.config.add_word("CLKFB_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKFB_DIV, 1) - 1, 7));
 
-            tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKI_DIV, 1) - 1, 7));
-            tg.config.add_word("CLKFB_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKFB_DIV, 1) - 1, 7));
+        tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, id_CLKOP_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, id_CLKOS_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, id_CLKOS2_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, id_CLKOS3_ENABLE, "ENABLED"));
 
-            tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, id_CLKOP_ENABLE, "ENABLED"));
-            tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, id_CLKOS_ENABLE, "ENABLED"));
-            tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, id_CLKOS2_ENABLE, "ENABLED"));
-            tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, id_CLKOS3_ENABLE, "ENABLED"));
+        for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
+            tg.config.add_word(out + "_DIV",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
+            tg.config.add_word(out + "_CPHASE",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
+            tg.config.add_word(out + "_FPHASE",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+        }
+
+        tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP"));
+        tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, id_CLKOP_TRIM_POL, "RISING"));
+
+        tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOP_TRIM_DELAY, "0"));
+
+        tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, id_CLKOS_TRIM_POL, "RISING"));
+
+        tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
+
+        tg.config.add_enum("OUTDIVIDER_MUXA",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXA, ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXB",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXB, ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXC",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXC, ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXD",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXD, ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK"));
+
+        tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
+
+        tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, id_STDBY_ENABLE, "DISABLED"));
+        tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, id_REFIN_RESET, "DISABLED"));
+        tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, id_SYNC_ENABLE, "DISABLED"));
+        tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, id_INT_LOCK_STICKY, "ENABLED"));
+        tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, id_DPHASE_SOURCE, "DISABLED"));
+        tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
+        tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, id_INTFB_WAKE, "DISABLED"));
+
+        tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, id_KVCO, 0), 3));
+        tg.config.add_word("LPF_CAPACITOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_CAPACITOR, 0), 2));
+        tg.config.add_word("LPF_RESISTOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_RESISTOR, 0), 7));
+        tg.config.add_word("ICP_CURRENT", int_to_bitvector(int_or_default(ci->attrs, id_ICP_CURRENT, 0), 5));
+        tg.config.add_word("FREQ_LOCK_ACCURACY",
+                           int_to_bitvector(int_or_default(ci->attrs, id_FREQ_LOCK_ACCURACY, 0), 2));
+
+        tg.config.add_word("MFG_GMC_GAIN", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_GAIN, 0), 3));
+        tg.config.add_word("MFG_GMC_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_TEST, 14), 4));
+        tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG1_TEST, 0), 3));
+        tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG2_TEST, 0), 3));
+
+        tg.config.add_word("MFG_FORCE_VFILTER",
+                           int_to_bitvector(int_or_default(ci->attrs, id_MFG_FORCE_VFILTER, 0), 1));
+        tg.config.add_word("MFG_ICP_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_ICP_TEST, 0), 1));
+        tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_EN_UP, 0), 1));
+        tg.config.add_word("MFG_FLOAT_ICP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_FLOAT_ICP, 0), 1));
+        tg.config.add_word("MFG_GMC_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_PRESET, 0), 1));
+        tg.config.add_word("MFG_LF_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_PRESET, 0), 1));
+        tg.config.add_word("MFG_GMC_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_RESET, 0), 1));
+        tg.config.add_word("MFG_LF_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESET, 0), 1));
+        tg.config.add_word("MFG_LF_RESGRND", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESGRND, 0), 1));
+        tg.config.add_word("MFG_GMCREF_SEL", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMCREF_SEL, 0), 2));
+        tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
+                           int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
+
+        cc.tilegroups.push_back(tg);
+    }
+
+    void write_iol(CellInfo *ci)
+    {
+        Loc pio_loc = ctx->getBelLocation(ci->bel);
+        pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4;
+        std::string pic_tile = get_pic_tile(ctx->getBelByLocation(pio_loc));
+        std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z];
+        for (auto &param : ci->params) {
+            if (param.first == ctx->id("DELAY.DEL_VALUE"))
+                cc.tiles[pic_tile].add_word(prim + "." + param.first.str(ctx),
+                                            int_to_bitvector(param.second.as_int64(), 7));
+            else
+                cc.tiles[pic_tile].add_enum(prim + "." + param.first.str(ctx), param.second.as_string());
+        }
+        if (ci->getPort(id_LOADN) != nullptr) {
+            cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN");
+        }
+    }
+
+    void write_dcu(CellInfo *ci)
+    {
+        TileGroup tg;
+        tg.tiles = get_dcu_tiles(ci->bel);
+        tg.config.add_enum("DCU.MODE", "DCUA");
+#include "dcu_bitstream.h"
+        cc.tilegroups.push_back(tg);
+        tieoff_dcu_ports(ci);
+    }
 
-            for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
-                tg.config.add_word(out + "_DIV",
-                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
-                tg.config.add_word(out + "_CPHASE",
-                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
-                tg.config.add_word(out + "_FPHASE",
-                                   int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+    void write_dqsbuf(CellInfo *ci)
+    {
+        Loc loc = ctx->getBelLocation(ci->bel);
+        bool l = loc.x < 10;
+        std::string pic = l ? "PICL" : "PICR";
+        TileGroup tg;
+        tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 2, loc.x, pic + "1_DQS0"));
+        tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 1, loc.x, pic + "2_DQS1"));
+        tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, pic + "0_DQS2"));
+        tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, pic + "1_DQS3"));
+        tg.config.add_enum("DQS.MODE", "DQSBUFM");
+        tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS"));
+        tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS"));
+        int li_del_value = int_or_default(ci->params, id_DQS_LI_DEL_VAL, 0);
+        if (str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS") == "MINUS")
+            li_del_value = (256 - li_del_value) & 0xFF;
+        int lo_del_value = int_or_default(ci->params, id_DQS_LO_DEL_VAL, 0);
+        if (str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS") == "MINUS")
+            lo_del_value = (256 - lo_del_value) & 0xFF;
+        tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
+        tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
+        tg.config.add_enum("DQS.WRLOADN_USED", ci->getPort(id_WRLOADN) != nullptr ? "YES" : "NO");
+        tg.config.add_enum("DQS.RDLOADN_USED", ci->getPort(id_RDLOADN) != nullptr ? "YES" : "NO");
+        tg.config.add_enum("DQS.PAUSE_USED", ci->getPort(id_PAUSE) != nullptr ? "YES" : "NO");
+        tg.config.add_enum("DQS.READ_USED",
+                           (ci->getPort(id_READ0) != nullptr || ci->getPort(id_READ1) != nullptr) ? "YES" : "NO");
+        tg.config.add_enum("DQS.DDRDEL", ci->getPort(id_DDRDEL) != nullptr ? "DDRDEL" : "0");
+        tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+        cc.tilegroups.push_back(tg);
+    }
+
+    void run(const std::string &base_config_file)
+    {
+        if (!base_config_file.empty()) {
+            std::ifstream config_file(base_config_file);
+            if (!config_file) {
+                log_error("failed to open base config file '%s'\n", base_config_file.c_str());
+            }
+            config_file >> cc;
+        } else {
+            switch (ctx->args.type) {
+            case ArchArgs::LFE5U_12F:
+                BaseConfigs::config_empty_lfe5u_25f(cc);
+                cc.chip_name = "LFE5U-12F";
+                break;
+            case ArchArgs::LFE5U_25F:
+                BaseConfigs::config_empty_lfe5u_25f(cc);
+                break;
+            case ArchArgs::LFE5U_45F:
+                BaseConfigs::config_empty_lfe5u_45f(cc);
+                break;
+            case ArchArgs::LFE5U_85F:
+                BaseConfigs::config_empty_lfe5u_85f(cc);
+                break;
+            case ArchArgs::LFE5UM_25F:
+                BaseConfigs::config_empty_lfe5um_25f(cc);
+                break;
+            case ArchArgs::LFE5UM_45F:
+                BaseConfigs::config_empty_lfe5um_45f(cc);
+                break;
+            case ArchArgs::LFE5UM_85F:
+                BaseConfigs::config_empty_lfe5um_85f(cc);
+                break;
+            case ArchArgs::LFE5UM5G_25F:
+                BaseConfigs::config_empty_lfe5um5g_25f(cc);
+                break;
+            case ArchArgs::LFE5UM5G_45F:
+                BaseConfigs::config_empty_lfe5um5g_45f(cc);
+                break;
+            case ArchArgs::LFE5UM5G_85F:
+                BaseConfigs::config_empty_lfe5um5g_85f(cc);
+                break;
+            default:
+                NPNR_ASSERT_FALSE("Unsupported device type");
+            }
+        }
+
+        cc.metadata.push_back("Part: " + ctx->get_full_chip_name());
+
+        // Clear out DCU tieoffs in base config if DCU used
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_DCUA) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                for (int i = 0; i < 12; i++) {
+                    auto tiles = ctx->get_tiles_at_loc(loc.y - 1, loc.x + i);
+                    for (const auto &tile : tiles) {
+                        auto cc_tile = cc.tiles.find(tile.first);
+                        if (cc_tile != cc.tiles.end()) {
+                            cc_tile->second.cenums.clear();
+                            cc_tile->second.cunknowns.clear();
+                        }
+                    }
+                }
+            }
+        }
+        // Add all set, configurable pips to the config
+        for (auto pip : ctx->getPips()) {
+            if (ctx->getBoundPipNet(pip) != nullptr) {
+                if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
+                    std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
+                    if (source.find("CLKI_PLL") != std::string::npos) {
+                        // Special case - must set pip in all relevant tiles
+                        for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
+                            if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
+                                set_pip(equiv_pip);
+                        }
+                    } else {
+                        set_pip(pip);
+                    }
+                }
             }
+        }
 
-            tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP"));
-            tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, id_CLKOP_TRIM_POL, "RISING"));
-
-            tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOP_TRIM_DELAY, "0"));
-
-            tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, id_CLKOS_TRIM_POL, "RISING"));
-
-            tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
-
-            tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, id_OUTDIVIDER_MUXA,
-                                                                 ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, id_OUTDIVIDER_MUXB,
-                                                                 ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, id_OUTDIVIDER_MUXC,
-                                                                 ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK"));
-            tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, id_OUTDIVIDER_MUXD,
-                                                                 ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK"));
-
-            tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
-
-            tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, id_STDBY_ENABLE, "DISABLED"));
-            tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, id_REFIN_RESET, "DISABLED"));
-            tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, id_SYNC_ENABLE, "DISABLED"));
-            tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, id_INT_LOCK_STICKY, "ENABLED"));
-            tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, id_DPHASE_SOURCE, "DISABLED"));
-            tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
-            tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, id_INTFB_WAKE, "DISABLED"));
-
-            tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, id_KVCO, 0), 3));
-            tg.config.add_word("LPF_CAPACITOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_CAPACITOR, 0), 2));
-            tg.config.add_word("LPF_RESISTOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_RESISTOR, 0), 7));
-            tg.config.add_word("ICP_CURRENT", int_to_bitvector(int_or_default(ci->attrs, id_ICP_CURRENT, 0), 5));
-            tg.config.add_word("FREQ_LOCK_ACCURACY",
-                               int_to_bitvector(int_or_default(ci->attrs, id_FREQ_LOCK_ACCURACY, 0), 2));
-
-            tg.config.add_word("MFG_GMC_GAIN", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_GAIN, 0), 3));
-            tg.config.add_word("MFG_GMC_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_TEST, 14), 4));
-            tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG1_TEST, 0), 3));
-            tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG2_TEST, 0), 3));
-
-            tg.config.add_word("MFG_FORCE_VFILTER",
-                               int_to_bitvector(int_or_default(ci->attrs, id_MFG_FORCE_VFILTER, 0), 1));
-            tg.config.add_word("MFG_ICP_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_ICP_TEST, 0), 1));
-            tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_EN_UP, 0), 1));
-            tg.config.add_word("MFG_FLOAT_ICP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_FLOAT_ICP, 0), 1));
-            tg.config.add_word("MFG_GMC_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_PRESET, 0), 1));
-            tg.config.add_word("MFG_LF_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_PRESET, 0), 1));
-            tg.config.add_word("MFG_GMC_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_RESET, 0), 1));
-            tg.config.add_word("MFG_LF_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESET, 0), 1));
-            tg.config.add_word("MFG_LF_RESGRND", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESGRND, 0), 1));
-            tg.config.add_word("MFG_GMCREF_SEL", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMCREF_SEL, 0), 2));
-            tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
-                               int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
+        init_io_banks();
 
-            cc.tilegroups.push_back(tg);
-        } else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) {
-            Loc pio_loc = ctx->getBelLocation(ci->bel);
-            pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4;
-            std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc));
-            std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z];
-            for (auto &param : ci->params) {
-                if (param.first == ctx->id("DELAY.DEL_VALUE"))
-                    cc.tiles[pic_tile].add_word(prim + "." + param.first.str(ctx),
-                                                int_to_bitvector(param.second.as_int64(), 7));
-                else
-                    cc.tiles[pic_tile].add_enum(prim + "." + param.first.str(ctx), param.second.as_string());
+        // Configure cells
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->bel == BelId()) {
+                log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
             }
-            if (ci->getPort(id_LOADN) != nullptr) {
-                cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN");
+            BelId bel = ci->bel;
+            if (ci->type == id_TRELLIS_COMB) {
+                write_comb(ci);
+            } else if (ci->type == id_TRELLIS_FF) {
+                write_ff(ci);
+            } else if (ci->type == id_TRELLIS_RAMW) {
+                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+                cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
+                cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
+                cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
+            } else if (ci->type == id_TRELLIS_IO) {
+                write_io(ci);
+            } else if (ci->type == id_DCCA) {
+                write_dcc(ci);
+            } else if (ci->type == id_DCSC) {
+                std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
+                std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles);
+                std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+                cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
+            } else if (ci->type == id_DP16KD) {
+                write_bram(ci);
+            } else if (ci->type == id_MULT18X18D) {
+                write_mult18(ci);
+            } else if (ci->type == id_ALU54B) {
+                write_alu54(ci);
+            } else if (ci->type == id_EHXPLLL) {
+                write_pll(ci);
+            } else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) {
+                write_iol(ci);
+            } else if (ci->type == id_DCUA) {
+                write_dcu(ci);
+            } else if (ci->type == id_EXTREFB) {
+                TileGroup tg;
+                tg.tiles = get_dcu_tiles(ci->bel);
+                tg.config.add_word("EXTREF.REFCK_DCBIAS_EN",
+                                   parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
+                tg.config.add_word("EXTREF.REFCK_RTERM",
+                                   parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
+                tg.config.add_word("EXTREF.REFCK_PWDNB",
+                                   parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
+                cc.tilegroups.push_back(tg);
+            } else if (ci->type == id_PCSCLKDIV) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
+                cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
+                                         str_or_default(ci->params, id_GSR, "ENABLED"));
+            } else if (ci->type == id_DTR) {
+                cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
+            } else if (ci->type == id_OSCG) {
+                int div = int_or_default(ci->params, id_DIV, 128);
+                if (div == 128)
+                    div = 127;
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
+                cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div));
+                cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
+                cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
+            } else if (ci->type == id_USRMCLK) {
+                if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
+                    log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
+                cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
+            } else if (ci->type == id_GSR) {
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
+                        "GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
+                cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
+                                                                    str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
+            } else if (ci->type == id_JTAGG) {
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
+                                                                       str_or_default(ci->params, id_ER1, "ENABLED"));
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
+                                                                       str_or_default(ci->params, id_ER2, "ENABLED"));
+            } else if (ci->type == id_CLKDIVF) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                bool r = loc.x > 5;
+                std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
+                std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
+                cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
+                cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+            } else if (ci->type == id_TRELLIS_ECLKBUF) {
+            } else if (ci->type == id_DQSBUFM) {
+                write_dqsbuf(ci);
+            } else if (ci->type == id_ECLKSYNCB) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                bool r = loc.x > 5;
+                std::string eclksync = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+                std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
+                if (ci->getPort(id_STOP) != nullptr)
+                    cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
+            } else if (ci->type == id_ECLKBRIDGECS) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                bool r = loc.x > 5;
+                std::string eclkb = ctx->loc_info(bel)->bel_data[bel.index].name.get();
+                std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
+                if (ci->getPort(id_STOP) != nullptr)
+                    cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
+            } else if (ci->type == id_DDRDLL) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                bool u = loc.y<15, r = loc.x> 15;
+                std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
+                if ((ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
+                     ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F) &&
+                    u)
+                    tiletype += "A";
+                std::string tile = ctx->get_tile_by_type(tiletype);
+                cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
+                cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+                cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY", str_or_default(ci->params, id_FORCE_MAX_DELAY, "NO"));
+            } else {
+                NPNR_ASSERT_FALSE("unsupported cell type");
             }
-        } else if (ci->type == id_DCUA) {
-            TileGroup tg;
-            tg.tiles = get_dcu_tiles(ctx, ci->bel);
-            tg.config.add_enum("DCU.MODE", "DCUA");
-#include "dcu_bitstream.h"
-            cc.tilegroups.push_back(tg);
-            tieoff_dcu_ports(ctx, cc, ci);
-        } else if (ci->type == id_EXTREFB) {
-            TileGroup tg;
-            tg.tiles = get_dcu_tiles(ctx, ci->bel);
-            tg.config.add_word("EXTREF.REFCK_DCBIAS_EN",
-                               parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
-            tg.config.add_word("EXTREF.REFCK_RTERM",
-                               parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
-            tg.config.add_word("EXTREF.REFCK_PWDNB",
-                               parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
-            cc.tilegroups.push_back(tg);
-        } else if (ci->type == id_PCSCLKDIV) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
-            cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
-                                     str_or_default(ci->params, id_GSR, "ENABLED"));
-        } else if (ci->type == id_DTR) {
-            cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
-        } else if (ci->type == id_OSCG) {
-            int div = int_or_default(ci->params, id_DIV, 128);
-            if (div == 128)
-                div = 127;
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
-            cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div));
-            cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
-            cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
-        } else if (ci->type == id_USRMCLK) {
-            if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
-                log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
-            cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
-        } else if (ci->type == id_GSR) {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("GSR.GSRMODE",
-                                                                   str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
-            cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
-                                                                str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
-        } else if (ci->type == id_JTAGG) {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
-                                                                   str_or_default(ci->params, id_ER1, "ENABLED"));
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
-                                                                   str_or_default(ci->params, id_ER2, "ENABLED"));
-        } else if (ci->type == id_CLKDIVF) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            bool r = loc.x > 5;
-            std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
-            std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
-            cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
-        } else if (ci->type == id_TRELLIS_ECLKBUF) {
-        } else if (ci->type == id_DQSBUFM) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            bool l = loc.x < 10;
-            std::string pic = l ? "PICL" : "PICR";
-            TileGroup tg;
-            tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 2, loc.x, pic + "1_DQS0"));
-            tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 1, loc.x, pic + "2_DQS1"));
-            tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, pic + "0_DQS2"));
-            tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, pic + "1_DQS3"));
-            tg.config.add_enum("DQS.MODE", "DQSBUFM");
-            tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS"));
-            tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS"));
-            int li_del_value = int_or_default(ci->params, id_DQS_LI_DEL_VAL, 0);
-            if (str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS") == "MINUS")
-                li_del_value = (256 - li_del_value) & 0xFF;
-            int lo_del_value = int_or_default(ci->params, id_DQS_LO_DEL_VAL, 0);
-            if (str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS") == "MINUS")
-                lo_del_value = (256 - lo_del_value) & 0xFF;
-            tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
-            tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
-            tg.config.add_enum("DQS.WRLOADN_USED", ci->getPort(id_WRLOADN) != nullptr ? "YES" : "NO");
-            tg.config.add_enum("DQS.RDLOADN_USED", ci->getPort(id_RDLOADN) != nullptr ? "YES" : "NO");
-            tg.config.add_enum("DQS.PAUSE_USED", ci->getPort(id_PAUSE) != nullptr ? "YES" : "NO");
-            tg.config.add_enum("DQS.READ_USED",
-                               (ci->getPort(id_READ0) != nullptr || ci->getPort(id_READ1) != nullptr) ? "YES" : "NO");
-            tg.config.add_enum("DQS.DDRDEL", ci->getPort(id_DDRDEL) != nullptr ? "DDRDEL" : "0");
-            tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
-            cc.tilegroups.push_back(tg);
-        } else if (ci->type == id_ECLKSYNCB) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            bool r = loc.x > 5;
-            std::string eclksync = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            if (ci->getPort(id_STOP) != nullptr)
-                cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
-        } else if (ci->type == id_ECLKBRIDGECS) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            bool r = loc.x > 5;
-            std::string eclkb = ctx->loc_info(bel)->bel_data[bel.index].name.get();
-            std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
-            if (ci->getPort(id_STOP) != nullptr)
-                cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
-        } else if (ci->type == id_DDRDLL) {
-            Loc loc = ctx->getBelLocation(ci->bel);
-            bool u = loc.y<15, r = loc.x> 15;
-            std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
-            if ((ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
-                 ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F) &&
-                u)
-                tiletype += "A";
-            std::string tile = ctx->get_tile_by_type(tiletype);
-            cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
-            cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
-            cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY", str_or_default(ci->params, id_FORCE_MAX_DELAY, "NO"));
-        } else {
-            NPNR_ASSERT_FALSE("unsupported cell type");
         }
-    }
 
-    // Add some SYSCONFIG settings
-    const std::string prefix = "arch.sysconfig.";
-    for (auto &setting : ctx->settings) {
-        std::string key = setting.first.str(ctx);
-        if (key.substr(0, prefix.length()) != prefix)
-            continue;
-        key = key.substr(prefix.length());
-        std::string value = setting.second.as_string();
-        if (key == "SLAVE_SPI_PORT" || key == "DONE_EX") {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
-            cc.tiles[ctx->get_tile_by_type("EFB2_PICB0")].add_enum("SYSCONFIG." + key, value);
-        } else if (key == "SLAVE_PARALLEL_PORT" || key == "BACKGROUND_RECONFIG" || key == "WAKE_UP") {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
-        } else if (key == "MASTER_SPI_PORT") {
-            cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
-        } else if (key == "TRANSFR") {
-            cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
-            cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
-        } else {
-            cc.sysconfig[key] = value;
+        // Add some SYSCONFIG settings
+        const std::string prefix = "arch.sysconfig.";
+        for (auto &setting : ctx->settings) {
+            std::string key = setting.first.str(ctx);
+            if (key.substr(0, prefix.length()) != prefix)
+                continue;
+            key = key.substr(prefix.length());
+            std::string value = setting.second.as_string();
+            if (key == "SLAVE_SPI_PORT" || key == "DONE_EX") {
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
+                cc.tiles[ctx->get_tile_by_type("EFB2_PICB0")].add_enum("SYSCONFIG." + key, value);
+            } else if (key == "SLAVE_PARALLEL_PORT" || key == "BACKGROUND_RECONFIG" || key == "WAKE_UP") {
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
+            } else if (key == "MASTER_SPI_PORT") {
+                cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
+            } else if (key == "TRANSFR") {
+                cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
+                cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
+            } else {
+                cc.sysconfig[key] = value;
+            }
         }
+
+        // Fixup tile names
+        fix_tile_names();
     }
+};
+} // namespace
+
+void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
+{
+    ECP5Bitgen bitgen(ctx);
+    bitgen.run(base_config_file);
 
-    // Fixup tile names
-    fix_tile_names(ctx, cc);
     // Configure chip
     if (!text_config_file.empty()) {
         std::ofstream out_config(text_config_file);
-        out_config << cc;
+        out_config << bitgen.cc;
     }
 }
 

From 376cedd558f6aaf7fa460c4560cb5e45d41f0a62 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 16 Sep 2022 09:32:15 +0200
Subject: [PATCH 189/712] fabulous: fix, but disable, IO configuration

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fasm.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index 1405766e49..e47255556f 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -127,9 +127,12 @@ struct FabFasmWriter
 
     void write_io(const CellInfo *io)
     {
+#if 0
+        prefix = format_name(ctx->getBelName(io->bel)) + ".";
         write_bool(io, "INPUT_USED");
         write_bool(io, "OUTPUT_USED");
         write_bool(io, "ENABLE_USED");
+#endif
     }
 
     void write_generic_cell(const CellInfo *ci)

From 415c097df8db5693c7acd171a4ee6cb5d7b23b94 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 20 Sep 2022 13:42:51 +0200
Subject: [PATCH 190/712] router2: Reserve source wire, too

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/route/router2.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index d054c9efbd..ed1a6fe0ab 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -453,6 +453,13 @@ struct Router2
     {
         bool did_something = false;
         WireId src = ctx->getNetinfoSourceWire(net);
+        {
+            auto &src_wd = wire_data(src);
+            if (src_wd.reserved_net != -1 && src_wd.reserved_net != net->udata)
+                log_error("attempting to reserve src wire '%s' for nets '%s' and '%s'\n", ctx->nameOfWire(src),
+                          ctx->nameOf(nets_by_udata.at(src_wd.reserved_net)), ctx->nameOf(net));
+            src_wd.reserved_net = net->udata;
+        }
         auto &usr = net->users.at(i);
         for (auto sink : ctx->getNetinfoSinkWires(net, usr)) {
             pool<WireId> rsv;

From a920ffcf70dad54596c84079c30a66542022ccda Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 20 Sep 2022 14:15:10 +0200
Subject: [PATCH 191/712] ice40: implement checkPipAvailForNet

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/arch.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/ice40/arch.h b/ice40/arch.h
index 3563baad2a..5ed2347d91 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -680,6 +680,16 @@ struct Arch : BaseArch<ArchRanges>
         return switches_locked[pi.switch_index] == WireId();
     }
 
+    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    {
+        if (ice40_pip_hard_unavail(pip))
+            return false;
+
+        auto &pi = chip_info->pip_data[pip.index];
+        auto swl = switches_locked[pi.switch_index];
+        return swl == WireId() || (swl == getPipDstWire(pip) && wire_to_net[swl.index] == net);
+    }
+
     NetInfo *getBoundPipNet(PipId pip) const override
     {
         NPNR_ASSERT(pip != PipId());

From 9000c41c4b5935d7d03d9d42e9c37b0a9f17fa88 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 20 Sep 2022 12:06:25 +0200
Subject: [PATCH 192/712] Added the --ignore-rel-clk option to control timing
 checks for cross-domain paths, formatted code

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 common/kernel/command.cc |   5 +
 common/kernel/timing.cc  | 214 +++++++++++++++++++--------------------
 common/kernel/timing.h   |   4 +-
 3 files changed, 108 insertions(+), 115 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 00f900b375..c548509f7f 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -172,6 +172,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("no-pack", "process design without packing");
 
     general.add_options()("ignore-loops", "ignore combinational loops in timing analysis");
+    general.add_options()("ignore-rel-clk", "ignore clock-to-clock relations in timing checks");
 
     general.add_options()("version,V", "show version");
     general.add_options()("test", "check architecture database integrity");
@@ -270,6 +271,10 @@ void CommandHandler::setupContext(Context *ctx)
         ctx->settings[ctx->id("timing/ignoreLoops")] = true;
     }
 
+    if (vm.count("ignore-rel-clk")) {
+        ctx->settings[ctx->id("timing/ignoreRelClk")] = true;
+    }
+
     if (vm.count("timing-allow-fail")) {
         ctx->settings[ctx->id("timing/allowFail")] = true;
     }
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index b7b979fc08..df0c3b5eb1 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -285,81 +285,81 @@ void TimingAnalyser::setup_port_domains()
     }
 }
 
-void TimingAnalyser::identify_related_domains() {
+void TimingAnalyser::identify_related_domains()
+{
 
     // Identify clock nets
     pool<IdString> clock_nets;
-    for (const auto& domain : domains) {
+    for (const auto &domain : domains) {
         clock_nets.insert(domain.key.clock);
     }
 
     // For each clock net identify all nets that can possibly drive it. Compute
     // cumulative delays to each of them.
-    std::function<void(const NetInfo*, dict<IdString, delay_t>&, delay_t)> find_net_drivers =
-        [&] (const NetInfo* ni, dict<IdString, delay_t>& drivers, delay_t delay_acc)
-    {
-        // Get driving cell and port
-        const CellInfo* cell = ni->driver.cell;
-        const IdString  port = ni->driver.port;
-
-        bool didGoUpstream = false;
-
-        // The cell has only one port
-        if (cell->ports.size() == 1) {
-            drivers[ni->name] = delay_acc;
-            return;
-        }
+    std::function<void(const NetInfo *, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
+            [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
+                // Get driving cell and port
+                const CellInfo *cell = ni->driver.cell;
+                const IdString port = ni->driver.port;
+
+                bool didGoUpstream = false;
+
+                // The cell has only one port
+                if (cell->ports.size() == 1) {
+                    drivers[ni->name] = delay_acc;
+                    return;
+                }
 
-        // Get the driver timing class
-        int  info_count = 0;
-        auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
+                // Get the driver timing class
+                int info_count = 0;
+                auto timing_class = ctx->getPortTimingClass(cell, port, info_count);
 
-        // The driver must be a combinational output
-        if (timing_class != TMG_COMB_OUTPUT) {
-            drivers[ni->name] = delay_acc;
-            return;
-        }
+                // The driver must be a combinational output
+                if (timing_class != TMG_COMB_OUTPUT) {
+                    drivers[ni->name] = delay_acc;
+                    return;
+                }
 
-        // Recurse upstream through all input ports that have combinational
-        // paths to this driver
-        for (const auto& it : cell->ports) {
-            const auto& pi = it.second;
+                // Recurse upstream through all input ports that have combinational
+                // paths to this driver
+                for (const auto &it : cell->ports) {
+                    const auto &pi = it.second;
 
-            // Only connected inputs
-            if (pi.type != PORT_IN) {
-                continue;
-            }
-            if (pi.net == nullptr) {
-                continue;
-            }
+                    // Only connected inputs
+                    if (pi.type != PORT_IN) {
+                        continue;
+                    }
+                    if (pi.net == nullptr) {
+                        continue;
+                    }
 
-            // The input must be a combinational input
-            timing_class = ctx->getPortTimingClass(cell, pi.name, info_count);
-            if (timing_class != TMG_COMB_INPUT) {
-                continue;
-            }
-            // There must be a combinational arc
-            DelayQuad delay;
-            if (!ctx->getCellDelay(cell, pi.name, port, delay)) {
-                continue;
-            }
+                    // The input must be a combinational input
+                    timing_class = ctx->getPortTimingClass(cell, pi.name, info_count);
+                    if (timing_class != TMG_COMB_INPUT) {
+                        continue;
+                    }
+                    // There must be a combinational arc
+                    DelayQuad delay;
+                    if (!ctx->getCellDelay(cell, pi.name, port, delay)) {
+                        continue;
+                    }
 
-            // Recurse
-            find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay());
-            didGoUpstream = true;
-        }
+                    // Recurse
+                    find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay());
+                    didGoUpstream = true;
+                }
 
-        // Did not propagate upstream through the cell, mark the net as driver
-        if (!didGoUpstream) {
-            drivers[ni->name] = delay_acc;
-        }
-    };
+                // Did not propagate upstream through the cell, mark the net as driver
+                if (!didGoUpstream) {
+                    drivers[ni->name] = delay_acc;
+                }
+            };
 
     // Identify possible drivers for each clock domain
     dict<IdString, dict<IdString, delay_t>> clock_drivers;
-    for (const auto& domain : domains) {
+    for (const auto &domain : domains) {
 
-        const NetInfo* ni = ctx->nets.at(domain.key.clock).get();
+        const NetInfo *ni = ctx->nets.at(domain.key.clock).get();
         dict<IdString, delay_t> drivers;
         find_net_drivers(ni, drivers, 0);
 
@@ -367,21 +367,18 @@ void TimingAnalyser::identify_related_domains() {
 
         if (ctx->debug) {
             log("Clock '%s' can be driven by:\n", domain.key.clock.str(ctx).c_str());
-            for (const auto& it : drivers) {
-                const NetInfo* net = ctx->nets.at(it.first).get();
-                log(" %s.%s delay %.3fns\n",
-                    net->driver.cell->name.str(ctx).c_str(),
-                    net->driver.port.str(ctx).c_str(),
-                    ctx->getDelayNS(it.second)
-                );
+            for (const auto &it : drivers) {
+                const NetInfo *net = ctx->nets.at(it.first).get();
+                log(" %s.%s delay %.3fns\n", net->driver.cell->name.str(ctx).c_str(), net->driver.port.str(ctx).c_str(),
+                    ctx->getDelayNS(it.second));
             }
         }
     }
 
     // Identify related clocks. For simplicity do it both for A->B and B->A
     // cases.
-    for (const auto& c1 : clock_drivers) {
-        for (const auto& c2 : clock_drivers) {
+    for (const auto &c1 : clock_drivers) {
+        for (const auto &c2 : clock_drivers) {
 
             if (c1 == c2) {
                 continue;
@@ -389,14 +386,14 @@ void TimingAnalyser::identify_related_domains() {
 
             // Make an intersection of the two drivers sets
             pool<IdString> common_drivers;
-            for (const auto& it : c1.second) {
+            for (const auto &it : c1.second) {
                 common_drivers.insert(it.first);
             }
-            for (const auto& it : c2.second) {
+            for (const auto &it : c2.second) {
                 common_drivers.insert(it.first);
             }
 
-            for (auto it=common_drivers.begin(); it!=common_drivers.end();) {
+            for (auto it = common_drivers.begin(); it != common_drivers.end();) {
                 if (!c1.second.count(*it) || !c2.second.count(*it)) {
                     it = common_drivers.erase(it);
                 } else {
@@ -406,21 +403,17 @@ void TimingAnalyser::identify_related_domains() {
 
             if (ctx->debug) {
 
-                log("Possible common driver(s) for clocks '%s' and '%s'\n",
-                    c1.first.str(ctx).c_str(), c2.first.str(ctx).c_str());
-
-                for (const auto& it : common_drivers) {
-    
-                    const NetInfo* ni = ctx->nets.at(it).get();
-                    const CellInfo* cell = ni->driver.cell;
-                    const IdString  port = ni->driver.port;
-    
-                    log(" net '%s', cell %s (%s), port %s\n", 
-                        it.str(ctx).c_str(),
-                        cell->name.str(ctx).c_str(),
-                        cell->type.str(ctx).c_str(),
-                        port.str(ctx).c_str()
-                    );
+                log("Possible common driver(s) for clocks '%s' and '%s'\n", c1.first.str(ctx).c_str(),
+                    c2.first.str(ctx).c_str());
+
+                for (const auto &it : common_drivers) {
+
+                    const NetInfo *ni = ctx->nets.at(it).get();
+                    const CellInfo *cell = ni->driver.cell;
+                    const IdString port = ni->driver.port;
+
+                    log(" net '%s', cell %s (%s), port %s\n", it.str(ctx).c_str(), cell->name.str(ctx).c_str(),
+                        cell->type.str(ctx).c_str(), port.str(ctx).c_str());
                 }
             }
 
@@ -432,7 +425,7 @@ void TimingAnalyser::identify_related_domains() {
 
             // Compute delay from c1 to c2 and store it
             auto driver = *common_drivers.begin();
-            auto delay  = c2.second.at(driver) - c1.second.at(driver);
+            auto delay = c2.second.at(driver) - c1.second.at(driver);
             clock_delays[std::make_pair(c1.first, c2.first)] = delay;
         }
     }
@@ -626,8 +619,8 @@ void TimingAnalyser::compute_slack()
             auto &dp = domain_pairs.at(pdp.first);
 
             // Get clock names
-            const auto& launch_clock = domains.at(dp.key.launch).key.clock;
-            const auto& capture_clock = domains.at(dp.key.capture).key.clock;
+            const auto &launch_clock = domains.at(dp.key.launch).key.clock;
+            const auto &capture_clock = domains.at(dp.key.capture).key.clock;
 
             // Get clock-to-clock delay if any
             delay_t clock_to_clock = 0;
@@ -727,12 +720,9 @@ void TimingAnalyser::print_report()
 
     print_fmax();
 
-    for (const auto& it : clock_delays) {
-        log_info("Clock-to-clock %s -> %s: %0.02f ns\n",
-            it.first.first.str(ctx).c_str(),
-            it.first.second.str(ctx).c_str(),
-            ctx->getDelayNS(it.second)
-        );
+    for (const auto &it : clock_delays) {
+        log_info("Clock-to-clock %s -> %s: %0.02f ns\n", it.first.first.str(ctx).c_str(),
+                 it.first.second.str(ctx).c_str(), ctx->getDelayNS(it.second));
     }
 }
 
@@ -1393,7 +1383,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     timing.walk_paths();
 
     // Use TimingAnalyser to determine clock-to-clock relations
-    TimingAnalyser timingAnalyser (ctx);
+    TimingAnalyser timingAnalyser(ctx);
     timingAnalyser.setup();
 
     bool report_critical_paths = print_path || print_fmax || update_results;
@@ -1628,13 +1618,13 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
         log_break();
 
         // All clock to clock delays
-        const auto& clock_delays = timingAnalyser.get_clock_delays();
+        const auto &clock_delays = timingAnalyser.get_clock_delays();
 
         // Clock to clock delays for xpaths
         dict<ClockPair, delay_t> xclock_delays;
         for (auto &report : xclock_reports) {
-            const auto& clock1_name = report.clock_pair.start.clock;
-            const auto& clock2_name = report.clock_pair.end.clock;
+            const auto &clock1_name = report.clock_pair.start.clock;
+            const auto &clock2_name = report.clock_pair.end.clock;
 
             const auto key = std::make_pair(clock1_name, clock2_name);
             if (clock_delays.count(key)) {
@@ -1646,14 +1636,14 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
         unsigned max_width_xcb = 0;
         for (auto &report : xclock_reports) {
             max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
-            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(),   max_width_xcb);
+            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
         }
 
         // Check and report xpath delays for related clocks
         if (!xclock_reports.empty()) {
             for (auto &report : xclock_reports) {
-                const auto& clock_a = report.clock_pair.start.clock;
-                const auto& clock_b = report.clock_pair.end.clock;
+                const auto &clock_a = report.clock_pair.start.clock;
+                const auto &clock_b = report.clock_pair.end.clock;
 
                 const auto key = std::make_pair(clock_a, clock_b);
                 if (!clock_delays.count(key)) {
@@ -1685,28 +1675,27 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                 float target;
                 if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
                     target = clock_fmax.at(clock_a).constraint;
-                }
-                else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
+                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
                     target = clock_fmax.at(clock_b).constraint;
-                }
-                else {
+                } else {
                     target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
                 }
 
                 bool passed = target < fmax;
 
                 auto ev_a = format_event(report.clock_pair.start, max_width_xca);
-                auto ev_b = format_event(report.clock_pair.end,   max_width_xcb);
+                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
 
                 if (!warn_on_failure || passed)
-                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
-                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
-                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
-                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
+                             fmax, passed ? "PASS" : "FAIL", target);
+                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
+                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
                 else
-                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n",
-                        ev_a.c_str(), ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
             }
             log_break();
         }
@@ -1722,7 +1711,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                     delay /= 2;
                 }
 
-                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(delay));
+                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
+                         ctx->getDelayNS(delay));
             }
 
             log_break();
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 9562ba9347..6c7a696c8d 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -92,9 +92,7 @@ struct TimingAnalyser
         return slack;
     }
 
-    auto get_clock_delays () const {
-        return clock_delays;
-    }
+    auto get_clock_delays() const { return clock_delays; }
 
     bool setup_only = false;
     bool verbose_mode = false;

From 78f67ae5bcf62138445cf25d5f1e21dd3f7caf66 Mon Sep 17 00:00:00 2001
From: airskywater <96818686+airskywater@users.noreply.github.com>
Date: Sat, 24 Sep 2022 11:35:40 +0800
Subject: [PATCH 193/712] fix runtime segmentation fault

disable null pointer dereference!
---
 common/kernel/timing.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index df0c3b5eb1..66de8dfcaa 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -300,6 +300,8 @@ void TimingAnalyser::identify_related_domains()
             [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
                 // Get driving cell and port
                 const CellInfo *cell = ni->driver.cell;
+                if (nullptr == cell) return;
+        
                 const IdString port = ni->driver.port;
 
                 bool didGoUpstream = false;
@@ -360,6 +362,9 @@ void TimingAnalyser::identify_related_domains()
     for (const auto &domain : domains) {
 
         const NetInfo *ni = ctx->nets.at(domain.key.clock).get();
+        if (nullptr == ni) continue;
+        if (nullptr == ni->driver.cell) continue;
+        
         dict<IdString, delay_t> drivers;
         find_net_drivers(ni, drivers, 0);
 

From c702e15a3fc9299499d7e362b180bc3ba778bbb4 Mon Sep 17 00:00:00 2001
From: airskywater <96818686+airskywater@users.noreply.github.com>
Date: Sat, 24 Sep 2022 12:03:44 +0800
Subject: [PATCH 194/712] Add more sanity check for pointers

---
 common/kernel/timing.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 66de8dfcaa..a9f64afafe 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -299,6 +299,7 @@ void TimingAnalyser::identify_related_domains()
     std::function<void(const NetInfo *, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
             [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
                 // Get driving cell and port
+                if (nullptr == ni) return;
                 const CellInfo *cell = ni->driver.cell;
                 if (nullptr == cell) return;
         

From 9572f6f03222188915633f0ab32de6d11a9a7622 Mon Sep 17 00:00:00 2001
From: airskywater <96818686+airskywater@users.noreply.github.com>
Date: Sat, 24 Sep 2022 14:46:35 +0800
Subject: [PATCH 195/712] Modify code to meet the code style preferences

---
 common/kernel/timing.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index a9f64afafe..f046ba7da6 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -299,9 +299,9 @@ void TimingAnalyser::identify_related_domains()
     std::function<void(const NetInfo *, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
             [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
                 // Get driving cell and port
-                if (nullptr == ni) return;
+                if (ni == nullptr) return;
                 const CellInfo *cell = ni->driver.cell;
-                if (nullptr == cell) return;
+                if (cell == nullptr) return;
         
                 const IdString port = ni->driver.port;
 
@@ -363,8 +363,8 @@ void TimingAnalyser::identify_related_domains()
     for (const auto &domain : domains) {
 
         const NetInfo *ni = ctx->nets.at(domain.key.clock).get();
-        if (nullptr == ni) continue;
-        if (nullptr == ni->driver.cell) continue;
+        if (ni == nullptr) continue;
+        if (ni->driver.cell == nullptr) continue;
         
         dict<IdString, delay_t> drivers;
         find_net_drivers(ni, drivers, 0);

From a16d184956506422f598d068c61115800feedc32 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 26 Sep 2022 09:33:38 +0200
Subject: [PATCH 196/712] ice40: Fix handling of carry out route-thru via 25,14

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/bitstream.cc | 36 +++++++++++++++++++++---------------
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 2e1a6d4e21..c8ad93d819 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -829,24 +829,30 @@ void write_asc(const Context *ctx, std::ostream &out)
             // Weird UltraPlus bits
             if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 ||
                 tile == TILE_IPCON) {
+                auto set_ipcon = [&](int lc_idx) {
+                    static const std::vector<int> ip_dsp_lut_perm = {
+                            4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
+                    };
+                    for (int i = 0; i < 16; i++)
+                        set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4),
+                                   ip_dsp_lut_perm.at(i));
+                    if (tile == TILE_IPCON)
+                        set_config(ti, config.at(y).at(x), "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5",
+                                   true);
+                    else
+                        set_config(ti, config.at(y).at(x),
+                                   "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
+                                           std::to_string(lc_idx) + "_inmux02_5",
+                                   true);
+                };
                 if ((ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) && x == 25 && y == 14) {
-                    // Mystery bits not set in this one tile
+                    // Mystery bits not set in this one tile, other than to route through the DSP carry out if used
+                    if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(25, 10, 0)))) {
+                        set_ipcon(0);
+                    }
                 } else {
                     for (int lc_idx = 0; lc_idx < 8; lc_idx++) {
-                        static const std::vector<int> ip_dsp_lut_perm = {
-                                4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
-                        };
-                        for (int i = 0; i < 16; i++)
-                            set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4),
-                                       ip_dsp_lut_perm.at(i));
-                        if (tile == TILE_IPCON)
-                            set_config(ti, config.at(y).at(x),
-                                       "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
-                        else
-                            set_config(ti, config.at(y).at(x),
-                                       "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
-                                               std::to_string(lc_idx) + "_inmux02_5",
-                                       true);
+                        set_ipcon(lc_idx);
                     }
                 }
             }

From 124c0fc8121f0ac1e7d9823f3f1576e5fa2c087b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 30 Sep 2022 12:03:16 +0200
Subject: [PATCH 197/712] fabulous: Add split MUX bels

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc | 10 +++++++
 generic/viaduct/fabulous/fabulous.cc  | 41 ++++++++++++++++++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index c46d5e6d39..1339635859 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -14,6 +14,7 @@ X(OutPass4_frame_config)
 X(RegFile_32x4)
 X(MULADD)
 X(MUX8LUT_frame_config)
+X(MUX8LUT_frame_config_mux)
 
 X(CLK)
 X(I)
@@ -86,3 +87,12 @@ X(BelBegin)
 X(BelEnd)
 X(GlobalClk)
 X(CFG)
+
+X(FABULOUS_MUX2)
+X(FABULOUS_MUX4)
+X(FABULOUS_MUX8)
+
+X(M_AB)
+X(M_AD)
+X(M_EF)
+X(M_AH)
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index e2adb8947c..287d7e5149 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -293,12 +293,48 @@ struct FabulousImpl : ViaductAPI
         postprocess_bels();
     }
 
+    void generate_split_mux8(BelId bel)
+    {
+        // _don't_ take a reference here because it might be invalidated by adding bels
+        auto data = ctx->bel_info(bel);
+        const std::array<IdString, 4> mux_outs{id_M_AB, id_M_AD, id_M_EF, id_M_AH};
+        for (unsigned k = 1; k <= 3; k++) {
+            // create MUX2 through 8
+            unsigned m = (1U << k);
+            for (unsigned i = 0; i < 8; i += m) {
+                // mux indexing scheme
+                //  - MUX2s are at (z % 2) == 0
+                //  - MUX4s are at (z % 4) == 1
+                //  - MUX8s are at (z % 8) == 7
+                int idx = (m == 2) ? i : (m == 4) ? (i + 1) : (i + 7);
+                BelId mux =
+                        ctx->addBel(IdStringList::concat(data.name[0], ctx->idf("MUX%d_%d", m, i)),
+                                    ctx->idf("FABULOUS_MUX%d", m), Loc(data.x, data.y, data.z + 1 + idx), false, false);
+                blk_trk->set_bel_type(mux, BelFlags::BLOCK_CLB, BelFlags::FUNC_MUX, idx);
+                // M data inputs
+                for (unsigned j = 0; j < m; j++) {
+                    ctx->addBelInput(mux, ctx->idf("I%d", j), data.pins.at(ctx->idf("%c", char('A' + i + j))).wire);
+                }
+                // K select inputs
+                for (unsigned j = 0; j < k; j++) {
+                    ctx->addBelInput(mux, ctx->idf("S%d", j), data.pins.at(ctx->idf("S%d",
+                        (m == 8 && j == 2) ? 3 : ((i / m) * k + j)
+                    )).wire);
+                }
+                // Output
+                IdString output = (m == 2) ? mux_outs.at(i / m) : (m == 4) ? mux_outs.at((i / m) * k + 1) : mux_outs.at(3);
+                ctx->addBelOutput(mux, id_O, data.pins.at(output).wire);
+            }
+        }
+    }
+
     void postprocess_bels()
     {
         // This does some post-processing on bels to make them useful for nextpnr place-and-route regardless of the code
         // path that creates them. In the future, splitting muxes and creating split LCs would be done here, too
         for (auto bel : ctx->getBels()) {
-            auto &data = ctx->bel_info(bel);
+            // _don't_ take a reference here because it might be invalidated by adding bels
+            auto data = ctx->bel_info(bel);
             if (data.type == id_FABULOUS_LC) {
                 if (!data.pins.count(id_Q)) {
                     // Add a Q pseudo-pin and pseudo-pip from Q to O
@@ -309,6 +345,9 @@ struct FabulousImpl : ViaductAPI
                     // Pseudo-pip for FF mode
                     add_pseudo_pip(q_wire, o_wire, id_O2Q);
                 }
+            } else if (data.type.in(id_MUX8LUT_frame_config, id_MUX8LUT_frame_config_mux)) {
+                generate_split_mux8(bel);
+                ctx->bel_info(bel).hidden = true;
             } else if (data.type == id_IO_1_bidirectional_frame_config_pass) {
                 if (!data.pins.count(id_PAD)) {
                     // Add a PAD pseudo-pin for the top level

From 3826a31ad3667d691d95ae027bd0ce66c5596f73 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 30 Sep 2022 13:27:51 +0200
Subject: [PATCH 198/712] fabulous: Pack, validity check and FASM support for
 muxes

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabulous.cc       |  9 ++--
 generic/viaduct/fabulous/fasm.cc           | 11 ++++-
 generic/viaduct/fabulous/pack.cc           | 48 ++++++++++++++++++++++
 generic/viaduct/fabulous/validity_check.cc | 21 ++++++++++
 4 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 287d7e5149..9cb7e74f17 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -317,12 +317,13 @@ struct FabulousImpl : ViaductAPI
                 }
                 // K select inputs
                 for (unsigned j = 0; j < k; j++) {
-                    ctx->addBelInput(mux, ctx->idf("S%d", j), data.pins.at(ctx->idf("S%d",
-                        (m == 8 && j == 2) ? 3 : ((i / m) * k + j)
-                    )).wire);
+                    ctx->addBelInput(mux, ctx->idf("S%d", j),
+                                     data.pins.at(ctx->idf("S%d", (m == 8 && j == 2) ? 3 : ((i / m) * k + j))).wire);
                 }
                 // Output
-                IdString output = (m == 2) ? mux_outs.at(i / m) : (m == 4) ? mux_outs.at((i / m) * k + 1) : mux_outs.at(3);
+                IdString output = (m == 2)   ? mux_outs.at(i / m)
+                                  : (m == 4) ? mux_outs.at((i / m) * k + 1)
+                                             : mux_outs.at(3);
                 ctx->addBelOutput(mux, id_O, data.pins.at(output).wire);
             }
         }
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index e47255556f..e4b95f6296 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -123,6 +123,14 @@ struct FabFasmWriter
             write_bool(lc, "NEG_SR");
             write_bool(lc, "ASYNC_SR");
         }
+        if (lc->type.in(id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
+            // TODO: don't hardcode prefix
+            out << prefix << "I.c0" << std::endl;
+        }
+        if (lc->type == id_FABULOUS_MUX8) {
+            // TODO: don't hardcode prefix
+            out << prefix << "I.c1" << std::endl;
+        }
     }
 
     void write_io(const CellInfo *io)
@@ -161,7 +169,8 @@ struct FabFasmWriter
     void write_cell(const CellInfo *ci)
     {
         out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl;
-        if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC))
+        if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC, id_FABULOUS_MUX2, id_FABULOUS_MUX4,
+                        id_FABULOUS_MUX8))
             write_logic(ci);
         else if (ci->type == id_IO_1_bidirectional_frame_config_pass)
             write_io(ci);
diff --git a/generic/viaduct/fabulous/pack.cc b/generic/viaduct/fabulous/pack.cc
index 0273a28a59..56a6f8559f 100644
--- a/generic/viaduct/fabulous/pack.cc
+++ b/generic/viaduct/fabulous/pack.cc
@@ -132,6 +132,53 @@ struct FabulousPacker
         }
     }
 
+    void pack_muxes()
+    {
+        // TODO: don't hardcode z-offset -- we should come up with our own constraint structure
+        int lut_muxes_dz = 9;
+        int lut_lut_dz = 1;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            unsigned k = 0;
+            if (ci->type == id_FABULOUS_MUX2)
+                k = 1;
+            else if (ci->type == id_FABULOUS_MUX4)
+                k = 2;
+            else if (ci->type == id_FABULOUS_MUX8)
+                k = 3;
+            else
+                continue;
+            unsigned m = (1U << k);
+            std::vector<CellInfo *> luts;
+            for (unsigned i = 0; i < m; i++) {
+                NetInfo *ii = ci->getPort(ctx->idf("I%d", i));
+                if (!ii || !ii->driver.cell || !ii->driver.cell->type.in(id_FABULOUS_LC, id_FABULOUS_COMB) ||
+                    ii->driver.port != id_O)
+                    log_error("mux %s input I%d net %s is not driven by a LUT!\n", ctx->nameOf(ci), i, ctx->nameOf(ii));
+                CellInfo *lut = ii->driver.cell;
+                NPNR_ASSERT(lut->cluster == ClusterId());
+                luts.push_back(lut);
+            }
+            luts.at(0)->cluster = luts.at(0)->name;
+            for (unsigned i = 0; i < m; i++) {
+                luts.at(i)->cluster = luts.at(0)->name;
+                luts.at(i)->constr_x = 0;
+                luts.at(i)->constr_y = 0;
+                luts.at(i)->constr_z = i * lut_lut_dz;
+                luts.at(i)->constr_abs_z = false;
+                if (i > 0)
+                    luts.at(0)->constr_children.push_back(luts.at(i));
+            }
+            int extra_mux_dz = (m == 8) ? 7 : (m == 4) ? 1 : 0;
+            ci->cluster = luts.at(0)->name;
+            ci->constr_x = 0;
+            ci->constr_y = 0;
+            ci->constr_z = lut_muxes_dz + extra_mux_dz;
+            ci->constr_abs_z = false;
+            luts.at(0)->constr_children.push_back(ci);
+        }
+    }
+
     void pack_ffs()
     {
         pool<IdString> to_delete;
@@ -238,6 +285,7 @@ struct FabulousPacker
         handle_constants();
         handle_io();
         pack_luts();
+        pack_muxes();
         prepare_ffs();
         pack_ffs();
     }
diff --git a/generic/viaduct/fabulous/validity_check.cc b/generic/viaduct/fabulous/validity_check.cc
index 91dba689c6..30b21f2990 100644
--- a/generic/viaduct/fabulous/validity_check.cc
+++ b/generic/viaduct/fabulous/validity_check.cc
@@ -33,6 +33,7 @@ CLBState::CLBState(const LogicConfig &cfg)
     if (cfg.split_lc) {
         ff = std::make_unique<CellInfo *[]>(cfg.lc_per_clb * cfg.ff_per_lc);
     }
+    mux = std::make_unique<CellInfo *[]>(cfg.lc_per_clb);
     // TODO: mux
 }
 
@@ -173,6 +174,26 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
             }
         }
     }
+    // don't allow mixed MUX types in the classic fabulous arch where ctrl sigs are shared
+    int tile_mux_type = 0;
+    for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
+        const CellInfo *m = mux[z];
+        if (!m)
+            continue;
+        int this_mux = 0;
+        if (m->type == id_FABULOUS_MUX2)
+            this_mux = 2;
+        else if (m->type == id_FABULOUS_MUX4)
+            this_mux = 4;
+        else if (m->type == id_FABULOUS_MUX8)
+            this_mux = 8;
+        else
+            NPNR_ASSERT_FALSE("unknown mux type");
+        if (tile_mux_type == 0)
+            tile_mux_type = this_mux;
+        else if (tile_mux_type != this_mux)
+            return false;
+    }
     // TODO: other checks...
     return true;
 }

From 1602774d27bc68fb291886276ff7cc409405717a Mon Sep 17 00:00:00 2001
From: David Lattimore <dml@google.com>
Date: Wed, 5 Oct 2022 14:33:06 +1100
Subject: [PATCH 199/712] nexus: Transform registered output parameters

Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
---
 nexus/constids.inc | 5 +++++
 nexus/pack.cc      | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/nexus/constids.inc b/nexus/constids.inc
index 8731fad7b3..596d064cb5 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -446,6 +446,11 @@ X(FBK_MMD_DIG)
 X(CLKMUX_FB)
 
 X(LRAM_CORE)
+X(OUTREG_A)
+X(OUTREG_B)
+X(OUTREG)
+X(OUT_REGMODE_A)
+X(OUT_REGMODE_B)
 
 X(EBR_SP_EN)
 X(ECC_BYTE_SEL)
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 3d293f6903..cd042485cf 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1111,6 +1111,7 @@ struct NexusPacker
         lram_rules[id_SP512K_MODE].port_xform[id_WE] = id_WEA;
         lram_rules[id_SP512K_MODE].port_xform[id_RSTOUT] = id_RSTA;
         lram_rules[id_SP512K_MODE].port_xform[id_CEOUT] = id_OCEA;
+        lram_rules[id_SP512K_MODE].param_xform[id_OUTREG] = id_OUT_REGMODE_A;
         add_bus_xform(lram_rules[id_SP512K_MODE], "DI", "DIA", 32);
         add_bus_xform(lram_rules[id_SP512K_MODE], "DO", "DOA", 32);
         add_bus_xform(lram_rules[id_SP512K_MODE], "AD", "ADA", 14);
@@ -1123,6 +1124,7 @@ struct NexusPacker
         lram_rules[id_PDPSC512K_MODE].port_xform[id_CSR] = id_CSB;
         lram_rules[id_PDPSC512K_MODE].port_xform[id_WE] = id_WEA;
         lram_rules[id_PDPSC512K_MODE].port_xform[id_RSTR] = id_RSTB;
+        lram_rules[id_PDPSC512K_MODE].param_xform[id_OUTREG] = id_OUT_REGMODE_B;
         add_bus_xform(lram_rules[id_PDPSC512K_MODE], "DI", "DIA", 32);
         add_bus_xform(lram_rules[id_PDPSC512K_MODE], "DO", "DOB", 32);
         add_bus_xform(lram_rules[id_PDPSC512K_MODE], "ADW", "ADA", 14);
@@ -1132,6 +1134,8 @@ struct NexusPacker
         lram_rules[id_DPSC512K_MODE].new_type = id_LRAM_CORE;
         lram_rules[id_DPSC512K_MODE].port_xform[id_CEOUTA] = id_OCEA;
         lram_rules[id_DPSC512K_MODE].port_xform[id_CEOUTB] = id_OCEB;
+        lram_rules[id_DPSC512K_MODE].param_xform[id_OUTREG_A] = id_OUT_REGMODE_A;
+        lram_rules[id_DPSC512K_MODE].param_xform[id_OUTREG_B] = id_OUT_REGMODE_B;
 
         log_info("Packing LRAM...\n");
         generic_xform(lram_rules, true);

From a7acda95f09a117a912bb3d1c327e854cd45acc8 Mon Sep 17 00:00:00 2001
From: Lushay Labs <107283894+lushaylabs@users.noreply.github.com>
Date: Sun, 9 Oct 2022 23:47:09 +0300
Subject: [PATCH 200/712] support windows line endings

---
 gowin/arch.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index e33a904ac1..00050f4471 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -876,12 +876,12 @@ void Arch::read_cst(std::istream &in)
     // If two locations are specified separated by commas (for differential I/O buffers),
     // only the first location is actually recognized and used.
     // And pin A will be Positive and pin B will be Negative in any case.
-    std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ,;]+)(, *[^ ;]+)? *;.*");
-    std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*");
+    std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ,;]+)(, *[^ ;]+)? *;.*[\\s\\S]*");
+    std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*[\\s\\S]*");
     std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
     std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
-    std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
-    std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*");
+    std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
+    std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*[\\s\\S]*");
     std::smatch match, match_attr, match_pinloc;
     std::string line, pinline;
     enum

From 613d84fb720df2144293c468dfe8ab2d2faa624a Mon Sep 17 00:00:00 2001
From: Tyler <tyler274port@gmail.com>
Date: Mon, 17 Oct 2022 01:19:51 -0700
Subject: [PATCH 201/712] Correct Not Equal operator implementation in ice40

I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
---
 ice40/archdefs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ice40/archdefs.h b/ice40/archdefs.h
index 07b209f137..87924df082 100644
--- a/ice40/archdefs.h
+++ b/ice40/archdefs.h
@@ -97,7 +97,7 @@ struct GroupId
     int8_t x = 0, y = 0;
 
     bool operator==(const GroupId &other) const { return (type == other.type) && (x == other.x) && (y == other.y); }
-    bool operator!=(const GroupId &other) const { return (type != other.type) || (x != other.x) || (y == other.y); }
+    bool operator!=(const GroupId &other) const { return (type != other.type) || (x != other.x) || (y != other.y); }
     unsigned int hash() const { return mkhash(mkhash(x, y), int(type)); }
 };
 

From 445d32497d4059bcd4d39d9163b24bd7161255df Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 17 Oct 2022 12:35:02 +0200
Subject: [PATCH 202/712] run clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/timing.cc | 16 ++++++++++------
 gowin/arch.cc           |  3 ++-
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index f046ba7da6..47235789a2 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -299,10 +299,12 @@ void TimingAnalyser::identify_related_domains()
     std::function<void(const NetInfo *, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
             [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
                 // Get driving cell and port
-                if (ni == nullptr) return;
+                if (ni == nullptr)
+                    return;
                 const CellInfo *cell = ni->driver.cell;
-                if (cell == nullptr) return;
-        
+                if (cell == nullptr)
+                    return;
+
                 const IdString port = ni->driver.port;
 
                 bool didGoUpstream = false;
@@ -363,9 +365,11 @@ void TimingAnalyser::identify_related_domains()
     for (const auto &domain : domains) {
 
         const NetInfo *ni = ctx->nets.at(domain.key.clock).get();
-        if (ni == nullptr) continue;
-        if (ni->driver.cell == nullptr) continue;
-        
+        if (ni == nullptr)
+            continue;
+        if (ni->driver.cell == nullptr)
+            continue;
+
         dict<IdString, delay_t> drivers;
         find_net_drivers(ni, drivers, 0);
 
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 00050f4471..f00dfb0a33 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -880,7 +880,8 @@ void Arch::read_cst(std::istream &in)
     std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*[\\s\\S]*");
     std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
     std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
-    std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
+    std::regex inslocre =
+            std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
     std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*[\\s\\S]*");
     std::smatch match, match_attr, match_pinloc;
     std::string line, pinline;

From 010b2e5ecf53fd1a8bbcfe208dca1d07bd4d5507 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 24 Oct 2022 09:28:34 +0200
Subject: [PATCH 203/712] Update CI script

---
 .github/workflows/arch_ci.yml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 5bf83630d5..dfeb2f9fec 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -20,11 +20,11 @@ jobs:
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.2a4
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
       with:
         submodules: recursive
 
-    - uses: actions/setup-python@v2
+    - uses: actions/setup-python@v4
 
     - name: Install
       run: |
@@ -32,7 +32,7 @@ jobs:
         sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qt5-default iverilog
 
     - name: Cache yosys installation
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-yosys
       with:
         path: .yosys
@@ -45,7 +45,7 @@ jobs:
       if: steps.cache-yosys.outputs.cache-hit != 'true'
 
     - name: Cache icestorm installation
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-icestorm
       with:
         path: .icestorm
@@ -59,7 +59,7 @@ jobs:
       if: matrix.arch == 'ice40' && steps.cache-icestorm.outputs.cache-hit != 'true'
 
     - name: Cache trellis installation
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-trellis
       with:
         path: .trellis
@@ -73,7 +73,7 @@ jobs:
       if: (matrix.arch == 'ecp5' || matrix.arch == 'machxo2') && steps.cache-trellis.outputs.cache-hit != 'true'
 
     - name: Cache prjoxide installation
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-prjoxide
       with:
         path: .prjoxide

From 4ffa47d897ec1a9d5482e73e9397c048299013fe Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 24 Oct 2022 09:42:16 +0200
Subject: [PATCH 204/712] Fix python version in CI

---
 .github/workflows/arch_ci.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index dfeb2f9fec..459a770c63 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -25,7 +25,8 @@ jobs:
         submodules: recursive
 
     - uses: actions/setup-python@v4
-
+      with:
+        python-version: '3.10'
     - name: Install
       run: |
         sudo apt-get update

From a84ded4793ce66b0f4854349c929afae334d1e56 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 10 Nov 2022 19:14:41 +1000
Subject: [PATCH 205/712] gowin: add initial PLL support

The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.

Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 40 ++++++++++++++++++++++++++
 gowin/arch.h       |  4 ++-
 gowin/cells.cc     | 64 +++++++++++++++++++++++++++++++++++++++++
 gowin/cells.h      |  4 +++
 gowin/constids.inc | 44 ++++++++++++++++++++++++++++
 gowin/pack.cc      | 72 ++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 227 insertions(+), 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index f00dfb0a33..54e38c0f67 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1071,6 +1071,26 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
     }
 }
 
+void Arch::add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col)
+{
+    IdString portname;
+    char buf[40];
+
+    for (int pid : {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5,
+                    ID_IDSEL0,  ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,
+                    ID_ODSEL2,  ID_ODSEL3,  ID_ODSEL4,  ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0,
+                    ID_DUTYDA1, ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3}) {
+        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
+        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+        addBelInput(belname, IdString(pid), id(buf));
+    }
+    for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
+        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
+        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+        addBelOutput(belname, IdString(pid), id(buf));
+    }
+}
+
 Arch::Arch(ArchArgs args) : args(args)
 {
     family = args.family;
@@ -1222,6 +1242,26 @@ Arch::Arch(ArchArgs args) : args(args)
             bool dff = true;
             bool oddrc = false;
             switch (static_cast<ConstIds>(bel->type_id)) {
+            case ID_RPLLA: {
+                snprintf(buf, 32, "R%dC%d_RPLLA", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_RPLLA, Loc(col, row, BelZ::pll_z), false);
+                add_plla_ports(bel, belname, row, col);
+            } break;
+            case ID_RPLLB:
+                snprintf(buf, 32, "R%dC%d_RPLLB", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_RPLLB, Loc(col, row, BelZ::pll_z), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_RESET, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET_P)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_RESET_P, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_ODSEL5)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_ODSEL5, id(buf));
+                break;
             case ID_BUFS7:
                 z++; /* fall-through*/
             case ID_BUFS6:
diff --git a/gowin/arch.h b/gowin/arch.h
index a1fc25ae7a..994b6d98ce 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -468,6 +468,7 @@ struct Arch : BaseArch<ArchRanges>
     void pre_pack(Context *ctx);
     void post_pack(Context *ctx);
     void auto_longwires();
+    void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col);
 
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
@@ -507,7 +508,8 @@ enum
     gnd_0_z = 278,    // virtual VSS bel Z
     osc_z = 280,      // Z for the oscillator bels
     bufs_0_z = 281,   // Z for long wire buffer bel
-    free_z = 289      // Must be the last, one can use z starting from this value, adjust accordingly.
+    pll_z = 289,      // PLL
+    free_z = 290      // Must be the last, one can use z starting from this value, adjust accordingly.
 };
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index fc5e7388c1..c1026bb587 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -79,6 +79,23 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
     } else if (type == id_BUFS) {
         new_cell->addInput(id_I);
         new_cell->addOutput(id_O);
+    } else if (type == id_RPLLB) {
+        new_cell->addInput(id_RESET);
+        new_cell->addInput(id_RESET_P);
+        new_cell->addInput(id_ODSEL5);
+    } else if (type == id_RPLLA) {
+        for (IdString iid :
+             {id_CLKIN,   id_CLKFB,   id_FBDSEL0, id_FBDSEL1, id_FBDSEL2, id_FBDSEL3, id_FBDSEL4, id_FBDSEL5,
+              id_IDSEL0,  id_IDSEL1,  id_IDSEL2,  id_IDSEL3,  id_IDSEL4,  id_IDSEL5,  id_ODSEL0,  id_ODSEL1,
+              id_ODSEL2,  id_ODSEL3,  id_ODSEL4,  id_PSDA0,   id_PSDA1,   id_PSDA2,   id_PSDA3,   id_DUTYDA0,
+              id_DUTYDA1, id_DUTYDA2, id_DUTYDA3, id_FDLY0,   id_FDLY1,   id_FDLY2,   id_FDLY3}) {
+            new_cell->addInput(iid);
+        }
+        new_cell->addOutput(id_CLKOUT);
+        new_cell->addOutput(id_CLKOUTP);
+        new_cell->addOutput(id_CLKOUTD);
+        new_cell->addOutput(id_CLKOUTD3);
+        new_cell->addOutput(id_LOCK);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
@@ -176,6 +193,53 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
     }
 }
 
+void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *plla)
+{
+    pll->movePortTo(id_CLKIN, plla, id_CLKIN);
+    pll->movePortTo(id_CLKFB, plla, id_CLKFB);
+    pll->movePortTo(ctx->id("FBDSEL[0]"), plla, id_FBDSEL0);
+    pll->movePortTo(ctx->id("FBDSEL[1]"), plla, id_FBDSEL1);
+    pll->movePortTo(ctx->id("FBDSEL[2]"), plla, id_FBDSEL2);
+    pll->movePortTo(ctx->id("FBDSEL[3]"), plla, id_FBDSEL3);
+    pll->movePortTo(ctx->id("FBDSEL[4]"), plla, id_FBDSEL4);
+    pll->movePortTo(ctx->id("FBDSEL[5]"), plla, id_FBDSEL5);
+    pll->movePortTo(ctx->id("IDSEL[0]"), plla, id_IDSEL0);
+    pll->movePortTo(ctx->id("IDSEL[1]"), plla, id_IDSEL1);
+    pll->movePortTo(ctx->id("IDSEL[2]"), plla, id_IDSEL2);
+    pll->movePortTo(ctx->id("IDSEL[3]"), plla, id_IDSEL3);
+    pll->movePortTo(ctx->id("IDSEL[4]"), plla, id_IDSEL4);
+    pll->movePortTo(ctx->id("IDSEL[5]"), plla, id_IDSEL5);
+    pll->movePortTo(ctx->id("ODSEL[0]"), plla, id_ODSEL0);
+    pll->movePortTo(ctx->id("ODSEL[1]"), plla, id_ODSEL1);
+    pll->movePortTo(ctx->id("ODSEL[2]"), plla, id_ODSEL2);
+    pll->movePortTo(ctx->id("ODSEL[3]"), plla, id_ODSEL3);
+    pll->movePortTo(ctx->id("ODSEL[4]"), plla, id_ODSEL4);
+    pll->movePortTo(ctx->id("PSDA[0]"), plla, id_PSDA0);
+    pll->movePortTo(ctx->id("PSDA[1]"), plla, id_PSDA1);
+    pll->movePortTo(ctx->id("PSDA[2]"), plla, id_PSDA2);
+    pll->movePortTo(ctx->id("PSDA[3]"), plla, id_PSDA3);
+    pll->movePortTo(ctx->id("DUTYDA[0]"), plla, id_DUTYDA0);
+    pll->movePortTo(ctx->id("DUTYDA[1]"), plla, id_DUTYDA1);
+    pll->movePortTo(ctx->id("DUTYDA[2]"), plla, id_DUTYDA2);
+    pll->movePortTo(ctx->id("DUTYDA[3]"), plla, id_DUTYDA3);
+    pll->movePortTo(ctx->id("FDLY[0]"), plla, id_FDLY0);
+    pll->movePortTo(ctx->id("FDLY[1]"), plla, id_FDLY1);
+    pll->movePortTo(ctx->id("FDLY[2]"), plla, id_FDLY2);
+    pll->movePortTo(ctx->id("FDLY[3]"), plla, id_FDLY3);
+    pll->movePortTo(id_CLKOUT, plla, id_CLKOUT);
+    pll->movePortTo(id_CLKOUTP, plla, id_CLKOUTP);
+    pll->movePortTo(id_CLKOUTD, plla, id_CLKOUTD);
+    pll->movePortTo(id_CLKOUTD3, plla, id_CLKOUTD3);
+    pll->movePortTo(id_LOCK, plla, id_LOCK);
+}
+
+void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb)
+{
+    pll->movePortTo(id_RESET, pllb, id_RESET);
+    pll->movePortTo(id_RESET_P, pllb, id_RESET_P);
+    pll->movePortTo(ctx->id("ODSEL[5]"), pllb, id_ODSEL5);
+}
+
 void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
 {
     if (ramw->hierpath == IdString())
diff --git a/gowin/cells.h b/gowin/cells.h
index 3a570f9740..227206c822 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -119,6 +119,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 // Convert a Gowin IO buffer to a IOB bel
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
 
+// Reconnect rPLL signals (B)
+void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *pllb);
+void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb);
+
 // Convert RAM16 to write port
 void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
 
diff --git a/gowin/constids.inc b/gowin/constids.inc
index ec1137fc59..59f364e7f4 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -851,6 +851,11 @@ X(OSCZ)
 X(OSCH)
 X(OSCF)
 
+// PLLs
+X(rPLL)
+X(RPLLA)
+X(RPLLB)
+
 // primitive attributes
 X(INIT)
 X(FF_USED)
@@ -861,6 +866,7 @@ X(ENABLE_USED)
 X(BEL)
 X(DIFF)
 X(DIFF_TYPE)
+X(DEVICE)
 
 // ports
 X(EN)
@@ -886,6 +892,44 @@ X(V)
 X(G)
 X(OSCOUT)
 X(OSCEN)
+X(RESET_P)
+X(CLKFB)
+X(FBDSEL0)
+X(FBDSEL1)
+X(FBDSEL2)
+X(FBDSEL3)
+X(FBDSEL4)
+X(FBDSEL5)
+X(IDSEL0)
+X(IDSEL1)
+X(IDSEL2)
+X(IDSEL3)
+X(IDSEL4)
+X(IDSEL5)
+X(ODSEL0)
+X(ODSEL1)
+X(ODSEL2)
+X(ODSEL3)
+X(ODSEL4)
+X(ODSEL5)
+X(PSDA0)
+X(PSDA1)
+X(PSDA2)
+X(PSDA3)
+X(DUTYDA0)
+X(DUTYDA1)
+X(DUTYDA2)
+X(DUTYDA3)
+X(FDLY0)
+X(FDLY1)
+X(FDLY2)
+X(FDLY3)
+X(CLKIN)
+X(CLKOUT)
+X(CLKOUTP)
+X(CLKOUTD)
+X(CLKOUTD3)
+X(LOCK)
 
 // timing
 X(X0)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index d978ac408a..5260dda554 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -986,6 +986,77 @@ static void pack_diff_io(Context *ctx)
     }
 }
 
+static bool is_pll(const Context *ctx, const CellInfo *cell)
+{
+    switch (cell->type.hash()) {
+    case ID_rPLL:
+        return true;
+    default:
+        return false;
+    }
+}
+
+// Pack PLLs
+static void pack_plls(Context *ctx)
+{
+    pool<IdString> packed_cells;
+    pool<IdString> delete_nets;
+
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    log_info("Packing PLLs..\n");
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+        if (is_pll(ctx, ci)) {
+            std::string parm_device = str_or_default(ci->params, id_DEVICE, "GW1N-1");
+            if (parm_device != ctx->device) {
+                log_error("Wrong PLL device:%s vs %s\n", parm_device.c_str(), ctx->device.c_str());
+                continue;
+            }
+
+            switch (ci->type.hash()) {
+            case ID_rPLL: {
+                if (parm_device == "GW1N-1") {
+                    // B half
+                    std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
+                    reconnect_rpllb(ctx, ci, cell.get());
+                    new_cells.push_back(std::move(cell));
+                    auto pllb_cell = new_cells.back().get();
+                    // A half
+                    cell = create_generic_cell(ctx, id_RPLLA, ci->name.str(ctx) + "$rplla");
+                    reconnect_rplla(ctx, ci, cell.get());
+                    new_cells.push_back(std::move(cell));
+                    auto plla_cell = new_cells.back().get();
+
+                    // need params for gowin_pack
+                    for (auto &parm : ci->params) {
+                        plla_cell->setParam(parm.first, parm.second);
+                        pllb_cell->setParam(parm.first, parm.second);
+                    }
+                    packed_cells.insert(ci->name);
+                } else {
+                    log_error("PLL isn't supported for %s\n", ctx->device.c_str());
+                }
+            } break;
+            default:
+                break;
+            }
+        }
+    }
+
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto dnet : delete_nets) {
+        ctx->nets.erase(dnet);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
 // Pack IO buffers
 static void pack_io(Context *ctx)
 {
@@ -1108,6 +1179,7 @@ bool Arch::pack()
         pack_alus(ctx);
         pack_lut_lutffs(ctx);
         pack_nonlut_ffs(ctx);
+        pack_plls(ctx);
         post_pack(ctx);
         ctx->settings[id_pack] = 1;
         ctx->assignArchInfo();

From 6930ab3acd6be88c0533785691f24ef5460000c6 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 10 Nov 2022 10:55:37 +0100
Subject: [PATCH 206/712] fabulous: Tweak delay estimate

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabulous.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 9cb7e74f17..3c6f025ff0 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -69,6 +69,7 @@ struct FabulousImpl : ViaductAPI
         blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
         is_new_fab ? init_bels_v2() : init_bels_v1();
         init_pips();
+        ctx->setDelayScaling(0.25, 0.5);
     }
 
     void pack() override { fabulous_pack(ctx, cfg); }

From 8a69bd0735dcdce0d19f999725ec132236011833 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 10 Nov 2022 10:57:41 +0100
Subject: [PATCH 207/712] Fix "implicit copy constructor for 'Property' is
 deprecated"

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/property.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/kernel/property.h b/common/kernel/property.h
index 814b2cac28..2ff085ec1a 100644
--- a/common/kernel/property.h
+++ b/common/kernel/property.h
@@ -46,6 +46,7 @@ struct Property
     Property(const std::string &strval);
     Property(State bit);
     Property &operator=(const Property &other) = default;
+    Property(const Property &other) = default;
 
     bool is_string;
 

From 9013b2de5020ea94fd34b04cbb255b4bad8cbfab Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 11 Nov 2022 09:19:16 +1000
Subject: [PATCH 208/712] gowin: use ctx->idf() a bit

Replacing snprintf() with ctx->idf() in PLL commit, but not yet a
complete overhaul.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc  | 10 +++-------
 gowin/cells.cc | 48 ++++++++++++++----------------------------------
 2 files changed, 17 insertions(+), 41 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 54e38c0f67..e6eeced372 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -236,8 +236,7 @@ bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
     }
 
     // old driver -> bufs LW input net
-    snprintf(buf, sizeof(buf), "$PACKER_BUFS_%c", longwire + 'A');
-    auto net = std::make_unique<NetInfo>(id(buf));
+    auto net = std::make_unique<NetInfo>(idf("$PACKER_BUFS_%c", longwire + 'A'));
     NetInfo *bufs_net = net.get();
     nets[net->name] = std::move(net);
 
@@ -1074,20 +1073,17 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
 void Arch::add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col)
 {
     IdString portname;
-    char buf[40];
 
     for (int pid : {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5,
                     ID_IDSEL0,  ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,
                     ID_ODSEL2,  ID_ODSEL3,  ID_ODSEL4,  ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0,
                     ID_DUTYDA1, ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
-        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-        addBelInput(belname, IdString(pid), id(buf));
+        addBelInput(belname, IdString(pid), idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
     }
     for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
-        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-        addBelOutput(belname, IdString(pid), id(buf));
+        addBelOutput(belname, IdString(pid), idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
     }
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index c1026bb587..a76ea1d8ac 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -197,35 +197,18 @@ void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *plla)
 {
     pll->movePortTo(id_CLKIN, plla, id_CLKIN);
     pll->movePortTo(id_CLKFB, plla, id_CLKFB);
-    pll->movePortTo(ctx->id("FBDSEL[0]"), plla, id_FBDSEL0);
-    pll->movePortTo(ctx->id("FBDSEL[1]"), plla, id_FBDSEL1);
-    pll->movePortTo(ctx->id("FBDSEL[2]"), plla, id_FBDSEL2);
-    pll->movePortTo(ctx->id("FBDSEL[3]"), plla, id_FBDSEL3);
-    pll->movePortTo(ctx->id("FBDSEL[4]"), plla, id_FBDSEL4);
-    pll->movePortTo(ctx->id("FBDSEL[5]"), plla, id_FBDSEL5);
-    pll->movePortTo(ctx->id("IDSEL[0]"), plla, id_IDSEL0);
-    pll->movePortTo(ctx->id("IDSEL[1]"), plla, id_IDSEL1);
-    pll->movePortTo(ctx->id("IDSEL[2]"), plla, id_IDSEL2);
-    pll->movePortTo(ctx->id("IDSEL[3]"), plla, id_IDSEL3);
-    pll->movePortTo(ctx->id("IDSEL[4]"), plla, id_IDSEL4);
-    pll->movePortTo(ctx->id("IDSEL[5]"), plla, id_IDSEL5);
-    pll->movePortTo(ctx->id("ODSEL[0]"), plla, id_ODSEL0);
-    pll->movePortTo(ctx->id("ODSEL[1]"), plla, id_ODSEL1);
-    pll->movePortTo(ctx->id("ODSEL[2]"), plla, id_ODSEL2);
-    pll->movePortTo(ctx->id("ODSEL[3]"), plla, id_ODSEL3);
-    pll->movePortTo(ctx->id("ODSEL[4]"), plla, id_ODSEL4);
-    pll->movePortTo(ctx->id("PSDA[0]"), plla, id_PSDA0);
-    pll->movePortTo(ctx->id("PSDA[1]"), plla, id_PSDA1);
-    pll->movePortTo(ctx->id("PSDA[2]"), plla, id_PSDA2);
-    pll->movePortTo(ctx->id("PSDA[3]"), plla, id_PSDA3);
-    pll->movePortTo(ctx->id("DUTYDA[0]"), plla, id_DUTYDA0);
-    pll->movePortTo(ctx->id("DUTYDA[1]"), plla, id_DUTYDA1);
-    pll->movePortTo(ctx->id("DUTYDA[2]"), plla, id_DUTYDA2);
-    pll->movePortTo(ctx->id("DUTYDA[3]"), plla, id_DUTYDA3);
-    pll->movePortTo(ctx->id("FDLY[0]"), plla, id_FDLY0);
-    pll->movePortTo(ctx->id("FDLY[1]"), plla, id_FDLY1);
-    pll->movePortTo(ctx->id("FDLY[2]"), plla, id_FDLY2);
-    pll->movePortTo(ctx->id("FDLY[3]"), plla, id_FDLY3);
+    for (int i = 0; i < 6; ++i) {
+        pll->movePortTo(ctx->idf("FBDSEL[%d]", i), plla, ctx->idf("FBDSEL%d", i));
+        pll->movePortTo(ctx->idf("IDSEL[%d]", i), plla, ctx->idf("IDSEL%d", i));
+        if (i < 5) {
+            pll->movePortTo(ctx->idf("ODSEL[%d]", i), plla, ctx->idf("ODSEL%d", i));
+        }
+        if (i < 4) {
+            pll->movePortTo(ctx->idf("PSDA[%d]", i), plla, ctx->idf("PSDA%d", i));
+            pll->movePortTo(ctx->idf("DUTYDA[%d]", i), plla, ctx->idf("DUTYDA%d", i));
+            pll->movePortTo(ctx->idf("FDLY[%d]", i), plla, ctx->idf("FDLY%d", i));
+        }
+    }
     pll->movePortTo(id_CLKOUT, plla, id_CLKOUT);
     pll->movePortTo(id_CLKOUTP, plla, id_CLKOUTP);
     pll->movePortTo(id_CLKOUTD, plla, id_CLKOUTD);
@@ -260,15 +243,12 @@ void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
 
 void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index)
 {
-    char buf1[32];
     if (slice->hierpath == IdString())
         slice->hierpath = slice->hierpath;
 
-    snprintf(buf1, 32, "INIT_%d", index);
-    slice->params[id_INIT] = ram->params[ctx->id(buf1)];
+    slice->params[id_INIT] = ram->params[ctx->idf("INIT_%d", index)];
 
-    snprintf(buf1, 32, "DO[%d]", index);
-    ram->movePortTo(ctx->id(buf1), slice, id_F);
+    ram->movePortTo(ctx->idf("DO[%d]", index), slice, id_F);
 
     ram->copyPortTo(ctx->id("RAD[0]"), slice, id_A);
     ram->copyPortTo(ctx->id("RAD[1]"), slice, id_B);

From d4642d918c84f18b6f17b57e619c95ea7a413d3f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 12 Nov 2022 10:12:43 +1000
Subject: [PATCH 209/712] gowin: add support for a more common chip

The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index 5260dda554..dc0b1461ad 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1018,7 +1018,7 @@ static void pack_plls(Context *ctx)
 
             switch (ci->type.hash()) {
             case ID_rPLL: {
-                if (parm_device == "GW1N-1") {
+                if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") {
                     // B half
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
                     reconnect_rpllb(ctx, ci, cell.get());

From 378ca60a2f29b7984c80f8ad9f665b5786fa524e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 20 Nov 2022 22:04:09 +1000
Subject: [PATCH 210/712] gowin: mark the PLL ports that are not in use

Unused ports are deactivated by special fuse combinations, rather than
being left dangling in the air.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/constids.inc | 8 ++++++++
 gowin/pack.cc      | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/gowin/constids.inc b/gowin/constids.inc
index 59f364e7f4..e0b37b49c8 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -931,6 +931,14 @@ X(CLKOUTD)
 X(CLKOUTD3)
 X(LOCK)
 
+// PLL parameters
+X(CLKOUTPS)
+X(CLKOUTDIV)
+X(CLKOUTDIV3)
+X(PWDEN)
+X(RSTEN)
+X(FLOCK)
+
 // timing
 X(X0)
 X(FX1)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index dc0b1461ad..1e0380c160 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1019,6 +1019,14 @@ static void pack_plls(Context *ctx)
             switch (ci->type.hash()) {
             case ID_rPLL: {
                 if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") {
+                    // Unused ports will be disabled during image generation. Here we add flags for such ports.
+                    Property pr_enable("ENABLE"), pr_disable("DISABLE");
+                    IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS},    {id_CLKOUTD, id_CLKOUTDIV},
+                                           {id_CLKOUTD3, id_CLKOUTDIV3}, {id_LOCK, id_FLOCK},
+                                           {id_RESET_P, id_PWDEN},       {id_RESET, id_RSTEN}};
+                    for (int i = 0; i < 6; ++i) {
+                        ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable);
+                    }
                     // B half
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
                     reconnect_rpllb(ctx, ci, cell.get());

From ec53ae0c3ba7778f41274f05f4561a335a4b0b90 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 25 Nov 2022 20:49:26 +1000
Subject: [PATCH 211/712] gowin: add information about pin configurations

Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 15 +++++++++++++--
 gowin/arch.h  | 11 +++++++++--
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index e6eeced372..756580e0b6 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -666,6 +666,17 @@ const PairPOD *pairLookup(const PairPOD *list, const size_t len, const int dest)
     return nullptr;
 }
 
+const PinPOD *pinLookup(const PinPOD *list, const size_t len, const int idx)
+{
+    for (size_t i = 0; i < len; i++) {
+        const PinPOD *pin = &list[i];
+        if (pin->index_id == idx) {
+            return pin;
+        }
+    }
+    return nullptr;
+}
+
 bool aliasCompare(GlobalAliasPOD i, GlobalAliasPOD j)
 {
     return (i.dest_row < j.dest_row) || (i.dest_row == j.dest_row && i.dest_col < j.dest_col) ||
@@ -947,9 +958,9 @@ void Arch::read_cst(std::istream &in)
         case ioloc: { // IO_LOC name pin
             IdString pinname = id(match[2]);
             pinline = match[2];
-            const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index);
+            const PinPOD *belname = pinLookup(package->pins.get(), package->num_pins, pinname.index);
             if (belname != nullptr) {
-                std::string bel = IdString(belname->src_id).str(this);
+                std::string bel = IdString(belname->loc_id).str(this);
                 it->second->setAttr(IdString(ID_BEL), bel);
             } else {
                 if (std::regex_match(pinline, match_pinloc, iobelre)) {
diff --git a/gowin/arch.h b/gowin/arch.h
index 994b6d98ce..0591e41a75 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -140,10 +140,17 @@ NPNR_PACKED_STRUCT(struct PartnumberPOD {
     uint32_t speed_id;
 });
 
+NPNR_PACKED_STRUCT(struct PinPOD {
+    uint16_t index_id;
+    uint16_t loc_id;
+    uint32_t num_cfgs;
+    RelPtr<uint32_t> cfgs;
+});
+
 NPNR_PACKED_STRUCT(struct PackagePOD {
     uint32_t name_id;
     uint32_t num_pins;
-    RelPtr<PairPOD> pins;
+    RelPtr<PinPOD> pins;
 });
 
 NPNR_PACKED_STRUCT(struct VariantPOD {
@@ -475,7 +482,7 @@ struct Arch : BaseArch<ArchRanges>
     void route_gowin_globals(Context *ctx);
 
     // chip db version
-    unsigned int const chipdb_version = 1;
+    unsigned int const chipdb_version = 2;
 
     std::vector<IdString> cell_types;
 

From 6ee3daf06a4f1d1f26c2bf9a328bff726e5a12ea Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 28 Nov 2022 09:00:41 +0100
Subject: [PATCH 212/712] ecp5: Fix Python bindings for pip iterators

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch_pybindings.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc
index 1621eda55a..a4a58d4c48 100644
--- a/ecp5/arch_pybindings.cc
+++ b/ecp5/arch_pybindings.cc
@@ -54,8 +54,8 @@ void arch_wrap_python(py::module &m)
     readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
     readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
 
-    typedef const PipRange UphillPipRange;
-    typedef const PipRange DownhillPipRange;
+    typedef PipRange UphillPipRange;
+    typedef PipRange DownhillPipRange;
 
     typedef const std::vector<BelBucketId> &BelBucketRange;
     typedef const std::vector<BelId> &BelRangeForBelBucket;

From b0791a01c9f78856c3168528f256a14ab9bbd67d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 2 Dec 2022 08:49:56 +1000
Subject: [PATCH 213/712] gowin: update the apicula version

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 459a770c63..63255a5bd3 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -18,7 +18,7 @@ jobs:
       TRELLIS_REVISION: 48486ebd1e03e4ac42c96299e881adf9d43bc241
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
-      APYCULA_REVISION: 0.2a4
+      APYCULA_REVISION: 0.5.1a1
     steps:
     - uses: actions/checkout@v3
       with:

From c62a947a2804c3027471b20815c7544e0fd698d0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 2 Dec 2022 14:20:39 +0100
Subject: [PATCH 214/712] api: Make NetInfo* of checkPipAvailForNet const

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_api.h  | 2 +-
 common/kernel/base_arch.h | 2 +-
 docs/archapi.md           | 2 +-
 ecp5/arch.h               | 2 +-
 fpga_interchange/arch.cc  | 2 +-
 fpga_interchange/arch.h   | 2 +-
 generic/arch.cc           | 2 +-
 generic/arch.h            | 2 +-
 generic/viaduct_api.h     | 2 +-
 ice40/arch.h              | 2 +-
 mistral/arch.h            | 2 +-
 nexus/arch.h              | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 14a30652ad..49be489b57 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -93,7 +93,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) = 0;
     virtual void unbindPip(PipId pip) = 0;
     virtual bool checkPipAvail(PipId pip) const = 0;
-    virtual bool checkPipAvailForNet(PipId pip, NetInfo *net) const = 0;
+    virtual bool checkPipAvailForNet(PipId pip, const NetInfo *net) const = 0;
     virtual NetInfo *getBoundPipNet(PipId pip) const = 0;
     virtual WireId getConflictingPipWire(PipId pip) const = 0;
     virtual NetInfo *getConflictingPipNet(PipId pip) const = 0;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 3055619dad..55fcf2803a 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -274,7 +274,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
         p2n_entry = nullptr;
     }
     virtual bool checkPipAvail(PipId pip) const override { return getBoundPipNet(pip) == nullptr; }
-    virtual bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    virtual bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
     {
         NetInfo *bound_net = getBoundPipNet(pip);
         return bound_net == nullptr || bound_net == net;
diff --git a/docs/archapi.md b/docs/archapi.md
index 3fc30cdb5b..efd833d222 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -402,7 +402,7 @@ pip to a net.
 
 *BaseArch default: returns `getBoundPipNet(pip) == nullptr`*
 
-### bool checkPipAvailForNet(PipId pip, NetInfo *net) const
+### bool checkPipAvailForNet(PipId pip, const NetInfo *net) const
 
 Returns true if the given pip is available to be bound to a net, or if the
 pip is already bound to that net.
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 12f043b786..8650452000 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -847,7 +847,7 @@ struct Arch : BaseArch<ArchRanges>
         return false;
     }
     bool checkPipAvail(PipId pip) const override { return (getBoundPipNet(pip) == nullptr) && !is_pip_blocked(pip); }
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
     {
         NetInfo *bound_net = getBoundPipNet(pip);
         return (bound_net == nullptr || bound_net == net) && !is_pip_blocked(pip);
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 3ce9f79e4a..4fc5d48d0a 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1743,7 +1743,7 @@ void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
     refreshUiWire(wire);
 }
 
-bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
+bool Arch::checkPipAvailForNet(PipId pip, const NetInfo *net) const
 {
     NPNR_ASSERT(pip != PipId());
     auto pip_iter = pip_to_net.find(pip);
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index aeb5578f87..04f583d4bd 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -596,7 +596,7 @@ struct Arch : ArchAPI<ArchRanges>
     void unbindPip(PipId pip) final;
 
     bool checkPipAvail(PipId pip) const final;
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const final;
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const final;
 
     NetInfo *getBoundPipNet(PipId pip) const final
     {
diff --git a/generic/arch.cc b/generic/arch.cc
index 9992e1cd2e..a1d98200a3 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -468,7 +468,7 @@ bool Arch::checkPipAvail(PipId pip) const
     return (!uarch || uarch->checkPipAvail(pip)) && (pip_info(pip).bound_net == nullptr);
 }
 
-bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
+bool Arch::checkPipAvailForNet(PipId pip, const NetInfo *net) const
 {
     if (uarch && !uarch->checkPipAvailForNet(pip, net))
         return false;
diff --git a/generic/arch.h b/generic/arch.h
index 688392da2d..6b34c28941 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -294,7 +294,7 @@ struct Arch : BaseArch<ArchRanges>
     void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override;
     void unbindPip(PipId pip) override;
     bool checkPipAvail(PipId pip) const override;
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override;
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override;
     NetInfo *getBoundPipNet(PipId pip) const override;
     WireId getConflictingPipWire(PipId pip) const override;
     NetInfo *getConflictingPipNet(PipId pip) const override;
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
index bc9b4311ce..6f8adb3e25 100644
--- a/generic/viaduct_api.h
+++ b/generic/viaduct_api.h
@@ -77,7 +77,7 @@ struct ViaductAPI
     // it's bound (which the base arch will deal with)
     virtual bool checkWireAvail(WireId wire) const { return true; }
     virtual bool checkPipAvail(PipId pip) const { return true; }
-    virtual bool checkPipAvailForNet(PipId pip, NetInfo *net) const { return checkPipAvail(pip); };
+    virtual bool checkPipAvailForNet(PipId pip, const NetInfo *net) const { return checkPipAvail(pip); };
 
     // --- Route lookahead ---
     virtual delay_t estimateDelay(WireId src, WireId dst) const;
diff --git a/ice40/arch.h b/ice40/arch.h
index 5ed2347d91..498a8b719b 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -680,7 +680,7 @@ struct Arch : BaseArch<ArchRanges>
         return switches_locked[pi.switch_index] == WireId();
     }
 
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
     {
         if (ice40_pip_hard_unavail(pip))
             return false;
diff --git a/mistral/arch.h b/mistral/arch.h
index 8fcea2915d..5ceda53c9f 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -408,7 +408,7 @@ struct Arch : BaseArch<ArchRanges>
         return BaseArch::checkPipAvail(pip);
     }
 
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
     {
         if (is_pip_blocked(pip))
             return false;
diff --git a/nexus/arch.h b/nexus/arch.h
index df4f976aca..41c54cd8fa 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1018,7 +1018,7 @@ struct Arch : BaseArch<ArchRanges>
         return getBoundPipNet(pip) == nullptr;
     }
 
-    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
     {
         if (disabled_pips.count(pip))
             return false;

From 91454515f4a0d87f42af7cd61cdf925c8fdb9229 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 2 Dec 2022 14:23:09 +0100
Subject: [PATCH 215/712] Unbreak CI

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/arch_ci.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 63255a5bd3..345ff456fc 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -30,14 +30,14 @@ jobs:
     - name: Install
       run: |
         sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qt5-default iverilog
+        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools iverilog
 
     - name: Cache yosys installation
       uses: actions/cache@v3
       id: cache-yosys
       with:
         path: .yosys
-        key: cache-yosys-${{ env.YOSYS_REVISION }}-r2
+        key: cache-yosys-${{ env.YOSYS_REVISION }}-r3
 
     - name: Build yosys
       run: |
@@ -50,7 +50,7 @@ jobs:
       id: cache-icestorm
       with:
         path: .icestorm
-        key: cache-icestorm-${{ env.ICESTORM_REVISION }}
+        key: cache-icestorm-${{ env.ICESTORM_REVISION }}-r3
       if: matrix.arch == 'ice40'
 
     - name: Build icestorm
@@ -64,7 +64,7 @@ jobs:
       id: cache-trellis
       with:
         path: .trellis
-        key: cache-trellis-${{ env.TRELLIS_REVISION }}
+        key: cache-trellis-${{ env.TRELLIS_REVISION }}-r3
       if: matrix.arch == 'ecp5' || matrix.arch == 'machxo2'
 
     - name: Build trellis
@@ -78,7 +78,7 @@ jobs:
       id: cache-prjoxide
       with:
         path: .prjoxide
-        key: cache-prjoxide-${{ env.PRJOXIDE_REVISION }}
+        key: cache-prjoxide-${{ env.PRJOXIDE_REVISION }}-r3
       if: matrix.arch == 'nexus'
 
     - name: Build prjoxide

From 2e68962a025999ec85276f6362540c13ccfcd752 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 4 Dec 2022 15:06:44 +1000
Subject: [PATCH 216/712] gowin: add PLL pins processing

Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.

The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 123 +++++++++++++++++++++++++++++++++++++++++++--
 gowin/arch.h       |   4 ++
 gowin/cells.h      |   2 +
 gowin/constids.inc |   3 ++
 gowin/pack.cc      |  11 ++--
 5 files changed, 133 insertions(+), 10 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 756580e0b6..ccfe2c4b9f 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -23,6 +23,7 @@
 #include <iostream>
 #include <math.h>
 #include <regex>
+#include "design_utils.h"
 #include "embed.h"
 #include "gfx.h"
 #include "nextpnr.h"
@@ -1575,6 +1576,24 @@ Arch::Arch(ArchArgs args) : args(args)
             }
         }
     }
+
+    // IO pin configs
+    for (unsigned int i = 0; i < package->num_pins; i++) {
+        const PinPOD *pin = &package->pins[i];
+        if (pin->num_cfgs == 0) {
+            continue;
+        }
+        auto b = bels.find(IdString(pin->loc_id));
+        if (b == bels.end()) {
+            // Not all pins are transmitted, e.g. MODE, DONE etc.
+            continue;
+        }
+        std::vector<IdString> &cfgs = b->second.pin_cfgs;
+        for (unsigned int j = 0; j < pin->num_cfgs; ++j) {
+            cfgs.push_back(IdString(pin->cfgs[j]));
+        }
+    }
+
     // setup pips
     for (int i = 0; i < db->rows * db->cols; i++) {
         int row = i / db->cols;
@@ -1958,26 +1977,122 @@ bool Arch::place()
     return retVal;
 }
 
+static bool is_spec_iob(const Context *ctx, const CellInfo *cell, IdString pin_name)
+{
+    if (!is_iob(ctx, cell)) {
+        return false;
+    }
+    std::vector<IdString> const &cfgs = ctx->bels.at(cell->bel).pin_cfgs;
+    bool have_pin = std::find(cfgs.begin(), cfgs.end(), pin_name) != cfgs.end();
+    return have_pin;
+}
+
+static bool is_PLL_T_IN_iob(const Context *ctx, const CellInfo *cell)
+{
+    return is_spec_iob(ctx, cell, ctx->id("RPLL_T_IN"));
+}
+
+static bool is_PLL_T_FB_iob(const Context *ctx, const CellInfo *cell)
+{
+    return is_spec_iob(ctx, cell, ctx->id("RPLL_T_FB"));
+}
+
+// If the PLL input can be connected using a direct wire, then do so,
+// bypassing conventional routing.
+void Arch::fix_pll_nets(Context *ctx)
+{
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_RPLLA) {
+            continue;
+        }
+        // *** CLKIN
+        do {
+            if (!port_used(ci, id_CLKIN)) {
+                ci->setParam(id_INSEL, Property("UNKNOWN"));
+                break;
+            }
+            NetInfo *net = ci->getPort(id_CLKIN);
+            if (net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
+                ci->setParam(id_INSEL, Property("UNKNOWN"));
+                break;
+            }
+            if (net_driven_by(ctx, net, is_PLL_T_IN_iob, id_O) != nullptr) {
+                ci->disconnectPort(id_CLKIN);
+                ci->setParam(id_INSEL, Property("CLKIN0"));
+                break;
+            }
+            // XXX do special bels (HCLK etc)
+            // This is general routing through CLK0 pip
+            ci->setParam(id_INSEL, Property("CLKIN1"));
+        } while (0);
+
+        do {
+            // *** CLKFB
+            if (str_or_default(ci->params, id_CLKFB_SEL, "internal") == "internal") {
+                ci->setParam(id_FBSEL, Property("CLKFB3"));
+                continue;
+            }
+            if (!port_used(ci, id_CLKFB)) {
+                ci->setParam(id_FBSEL, Property("UNKNOWN"));
+                continue;
+            }
+            NetInfo *net = ci->getPort(id_CLKFB);
+            if (net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
+                ci->setParam(id_FBSEL, Property("UNKNOWN"));
+                continue;
+            }
+            if (net_driven_by(ctx, net, is_PLL_T_FB_iob, id_O) != nullptr) {
+                ci->disconnectPort(id_CLKFB);
+                ci->setParam(id_FBSEL, Property("CLKFB2"));
+                break;
+            }
+            // XXX do special bels (HCLK etc)
+            // This is general routing through CLK2 pip
+            ci->setParam(id_FBSEL, Property("CLKFB0"));
+        } while (0);
+
+        // resets
+        Property pr_enable("ENABLE"), pr_disable("DISABLE");
+        NetInfo *net = ci->getPort(id_RESET);
+        ci->setParam(id_RSTEN, pr_enable);
+        if (!port_used(ci, id_RESET) || net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
+            ci->setParam(id_RSTEN, pr_disable);
+        }
+        ci->setParam(id_PWDEN, pr_enable);
+        net = ci->getPort(id_RESET_P);
+        if (!port_used(ci, id_RESET_P) || net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
+            ci->setParam(id_PWDEN, pr_disable);
+        }
+    }
+}
+
+void Arch::pre_route(Context *ctx) { fix_pll_nets(ctx); }
+
+void Arch::post_route(Context *ctx) { fix_longwire_bels(); }
+
 bool Arch::route()
 {
     std::string router = str_or_default(settings, id_router, defaultRouter);
+    Context *ctx = getCtx();
 
+    pre_route(ctx);
     if (bool_or_default(settings, id("arch.enable-globals"))) {
-        route_gowin_globals(getCtx());
+        route_gowin_globals(ctx);
     }
 
     bool result;
     if (router == "router1") {
-        result = router1(getCtx(), Router1Cfg(getCtx()));
+        result = router1(ctx, Router1Cfg(ctx));
     } else if (router == "router2") {
-        router2(getCtx(), Router2Cfg(getCtx()));
+        router2(ctx, Router2Cfg(ctx));
         result = true;
     } else {
         log_error("Gowin architecture does not support router '%s'\n", router.c_str());
     }
     getCtx()->settings[id_route] = 1;
     archInfoToAttributes();
-    fix_longwire_bels();
+    post_route(ctx);
     return result;
 }
 
diff --git a/gowin/arch.h b/gowin/arch.h
index 0591e41a75..3e614ebabb 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -227,6 +227,7 @@ struct BelInfo
     std::map<IdString, std::string> attrs;
     CellInfo *bound_cell;
     dict<IdString, PinInfo> pins;
+    std::vector<IdString> pin_cfgs;
     DecalXY decalxy_active, decalxy_inactive;
     int x, y, z;
     bool gb;
@@ -474,8 +475,11 @@ struct Arch : BaseArch<ArchRanges>
     void fix_longwire_bels();
     void pre_pack(Context *ctx);
     void post_pack(Context *ctx);
+    void pre_route(Context *ctx);
+    void post_route(Context *ctx);
     void auto_longwires();
     void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col);
+    void fix_pll_nets(Context *ctx);
 
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
diff --git a/gowin/cells.h b/gowin/cells.h
index 227206c822..ae475b774f 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -105,6 +105,8 @@ inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 
 inline bool is_sram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_RAM16SDP4; }
 
+inline bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); }
+
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
 // can be reconnected
diff --git a/gowin/constids.inc b/gowin/constids.inc
index e0b37b49c8..610755bb01 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -938,6 +938,9 @@ X(CLKOUTDIV3)
 X(PWDEN)
 X(RSTEN)
 X(FLOCK)
+X(INSEL)
+X(FBSEL)
+X(CLKFB_SEL)
 
 // timing
 X(X0)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 1e0380c160..c36a47574b 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -820,8 +820,6 @@ static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
     }
 }
 
-static bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); }
-
 // Pack IO logic
 static void pack_iologic(Context *ctx)
 {
@@ -1021,10 +1019,11 @@ static void pack_plls(Context *ctx)
                 if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") {
                     // Unused ports will be disabled during image generation. Here we add flags for such ports.
                     Property pr_enable("ENABLE"), pr_disable("DISABLE");
-                    IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS},    {id_CLKOUTD, id_CLKOUTDIV},
-                                           {id_CLKOUTD3, id_CLKOUTDIV3}, {id_LOCK, id_FLOCK},
-                                           {id_RESET_P, id_PWDEN},       {id_RESET, id_RSTEN}};
-                    for (int i = 0; i < 6; ++i) {
+                    IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS},
+                                           {id_CLKOUTD, id_CLKOUTDIV},
+                                           {id_CLKOUTD3, id_CLKOUTDIV3},
+                                           {id_LOCK, id_FLOCK}};
+                    for (int i = 0; i < 4; ++i) {
                         ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable);
                     }
                     // B half

From 3a61bb4119c4eedf3f5b61b2d6494718eea244be Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 6 Dec 2022 10:04:59 +0100
Subject: [PATCH 217/712] viaduct: Fix constant connectivity

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct_helpers.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
index 53df625cf9..cd246aa36b 100644
--- a/generic/viaduct_helpers.cc
+++ b/generic/viaduct_helpers.cc
@@ -158,6 +158,9 @@ void ViaductHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd
     NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC"));
     NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND"));
 
+    vcc_drv->connectPort(vcc_driver.port, vcc_net);
+    gnd_drv->connectPort(gnd_driver.port, gnd_net);
+
     std::vector<IdString> trim_cells;
     std::vector<IdString> trim_nets;
     for (auto &net : ctx->nets) {

From 150a482b77877bac6943d8554cd6283837bf7308 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 6 Dec 2022 23:07:01 +1000
Subject: [PATCH 218/712] gowin: change the way networks are handled

Until a comprehensive clock router is developed, the order in which
private cases are handled is important.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index ccfe2c4b9f..4d73268067 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2067,7 +2067,13 @@ void Arch::fix_pll_nets(Context *ctx)
     }
 }
 
-void Arch::pre_route(Context *ctx) { fix_pll_nets(ctx); }
+void Arch::pre_route(Context *ctx)
+{
+    fix_pll_nets(ctx);
+    if (bool_or_default(settings, id("arch.enable-globals"))) {
+        mark_gowin_globals(ctx);
+    }
+}
 
 void Arch::post_route(Context *ctx) { fix_longwire_bels(); }
 
@@ -2289,11 +2295,6 @@ void Arch::pre_pack(Context *ctx)
     }
 }
 
-void Arch::post_pack(Context *ctx)
-{
-    if (bool_or_default(settings, id("arch.enable-globals"))) {
-        mark_gowin_globals(ctx);
-    }
-}
+void Arch::post_pack(Context *ctx) {}
 
 NEXTPNR_NAMESPACE_END

From e260ac33abdd175f38ea5d8367c52a154b486648 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 7 Dec 2022 10:00:53 +0100
Subject: [PATCH 219/712] refactor: ArcBounds -> BoundingBox

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_api.h               |  4 ++--
 common/kernel/base_arch.h              |  6 +++---
 common/kernel/nextpnr_base_types.h     |  6 +++---
 common/route/router2.cc                | 30 +++++++++++++-------------
 docs/archapi.md                        |  4 ++--
 ecp5/arch.cc                           |  4 ++--
 ecp5/arch.h                            |  2 +-
 fpga_interchange/arch.cc               |  2 +-
 fpga_interchange/arch.h                |  4 ++--
 fpga_interchange/arch_pack_clusters.cc |  4 ++--
 fpga_interchange/cost_map.cc           |  4 ++--
 fpga_interchange/cost_map.h            |  2 +-
 generic/arch.cc                        |  4 ++--
 generic/arch.h                         |  2 +-
 generic/viaduct_api.cc                 |  4 ++--
 generic/viaduct_api.h                  |  2 +-
 gowin/arch.cc                          |  4 ++--
 gowin/arch.h                           |  2 +-
 ice40/arch.cc                          |  4 ++--
 ice40/arch.h                           |  2 +-
 machxo2/arch.cc                        |  4 ++--
 machxo2/arch.h                         |  2 +-
 mistral/arch.cc                        |  4 ++--
 mistral/arch.h                         |  2 +-
 nexus/arch.cc                          |  4 ++--
 nexus/arch.h                           |  2 +-
 26 files changed, 57 insertions(+), 57 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 49be489b57..94a8833870 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -118,7 +118,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual uint32_t getDelayChecksum(delay_t v) const = 0;
     virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
     virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
-    virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const = 0;
+    virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const = 0;
     // Decal methods
     virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId decal) const = 0;
     virtual DecalXY getBelDecal(BelId bel) const = 0;
@@ -141,7 +141,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual typename R::BucketBelRangeT getBelsInBucket(BelBucketId bucket) const = 0;
     // Cluster methods
     virtual CellInfo *getClusterRootCell(ClusterId cluster) const = 0;
-    virtual ArcBounds getClusterBounds(ClusterId cluster) const = 0;
+    virtual BoundingBox getClusterBounds(ClusterId cluster) const = 0;
     virtual Loc getClusterOffset(const CellInfo *cell) const = 0;
     virtual bool isClusterStrict(const CellInfo *cell) const = 0;
     virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 55fcf2803a..53e28652bc 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -377,10 +377,10 @@ template <typename R> struct BaseArch : ArchAPI<R>
     // Cluster methods
     virtual CellInfo *getClusterRootCell(ClusterId cluster) const override { return get_cluster_root(this, cluster); }
 
-    virtual ArcBounds getClusterBounds(ClusterId cluster) const override
+    virtual BoundingBox getClusterBounds(ClusterId cluster) const override
     {
-        return if_using_basecluster<ArcBounds>(get_cluster_root(this, cluster), [](const BaseClusterInfo *cluster) {
-            ArcBounds bounds(0, 0, 0, 0);
+        return if_using_basecluster<BoundingBox>(get_cluster_root(this, cluster), [](const BaseClusterInfo *cluster) {
+            BoundingBox bounds(0, 0, 0, 0);
             for (auto child : cluster->constr_children) {
                 if_using_basecluster<void>(child, [&](const BaseClusterInfo *child) {
                     bounds.x0 = std::min(bounds.x0, child->constr_x);
diff --git a/common/kernel/nextpnr_base_types.h b/common/kernel/nextpnr_base_types.h
index 944bf0b8b5..80a0e24ee1 100644
--- a/common/kernel/nextpnr_base_types.h
+++ b/common/kernel/nextpnr_base_types.h
@@ -95,12 +95,12 @@ struct Loc
     unsigned int hash() const { return mkhash(x, mkhash(y, z)); }
 };
 
-struct ArcBounds
+struct BoundingBox
 {
     int x0 = -1, y0 = -1, x1 = -1, y1 = -1;
 
-    ArcBounds() {}
-    ArcBounds(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1){};
+    BoundingBox() {}
+    BoundingBox(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1){};
 
     int distance(Loc loc) const
     {
diff --git a/common/route/router2.cc b/common/route/router2.cc
index ed1a6fe0ab..cdd98b6ea5 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -51,7 +51,7 @@ struct Router2
     struct PerArcData
     {
         WireId sink_wire;
-        ArcBounds bb;
+        BoundingBox bb;
         bool routed = false;
     };
 
@@ -62,7 +62,7 @@ struct Router2
         WireId src_wire;
         dict<WireId, std::pair<PipId, int>> wires;
         std::vector<std::vector<PerArcData>> arcs;
-        ArcBounds bb;
+        BoundingBox bb;
         // Coordinates of the center of the net, used for the weight-to-average
         int cx, cy, hpwl;
         int total_route_us = 0;
@@ -206,7 +206,7 @@ struct Router2
                 }
             }
 
-            ArcBounds wire_loc = ctx->getRouteBoundingBox(wire, wire);
+            BoundingBox wire_loc = ctx->getRouteBoundingBox(wire, wire);
             pwd.x = (wire_loc.x0 + wire_loc.x1) / 2;
             pwd.y = (wire_loc.y0 + wire_loc.y1) / 2;
 
@@ -249,7 +249,7 @@ struct Router2
         };
     };
 
-    bool hit_test_pip(ArcBounds &bb, Loc l) { return l.x >= bb.x0 && l.x <= bb.x1 && l.y >= bb.y0 && l.y <= bb.y1; }
+    bool hit_test_pip(BoundingBox &bb, Loc l) { return l.x >= bb.x0 && l.x <= bb.x1 && l.y >= bb.y0 && l.y <= bb.y1; }
 
     double curr_cong_weight, hist_cong_weight, estimate_weight;
 
@@ -269,7 +269,7 @@ struct Router2
         std::vector<int> dirty_wires;
 
         // Thread bounding box
-        ArcBounds bb;
+        BoundingBox bb;
 
         DeterministicRNG rng;
 
@@ -1217,7 +1217,7 @@ struct Router2
         if (route_queue.size() < 200) {
             ThreadContext st;
             st.rng.rngseed(ctx->rng64());
-            st.bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
+            st.bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
             for (size_t j = 0; j < route_queue.size(); j++) {
                 route_net(st, nets_by_udata[route_queue[j]], false);
             }
@@ -1234,19 +1234,19 @@ struct Router2
         int le_y = mid_y;
         int rs_y = mid_y;
         // Set up thread bounding boxes
-        tcs.at(0).bb = ArcBounds(0, 0, mid_x, mid_y);
-        tcs.at(1).bb = ArcBounds(mid_x + 1, 0, std::numeric_limits<int>::max(), le_y);
-        tcs.at(2).bb = ArcBounds(0, mid_y + 1, mid_x, std::numeric_limits<int>::max());
+        tcs.at(0).bb = BoundingBox(0, 0, mid_x, mid_y);
+        tcs.at(1).bb = BoundingBox(mid_x + 1, 0, std::numeric_limits<int>::max(), le_y);
+        tcs.at(2).bb = BoundingBox(0, mid_y + 1, mid_x, std::numeric_limits<int>::max());
         tcs.at(3).bb =
-                ArcBounds(mid_x + 1, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
+                BoundingBox(mid_x + 1, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
 
-        tcs.at(4).bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), mid_y);
-        tcs.at(5).bb = ArcBounds(0, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
+        tcs.at(4).bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), mid_y);
+        tcs.at(5).bb = BoundingBox(0, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
 
-        tcs.at(6).bb = ArcBounds(0, 0, mid_x, std::numeric_limits<int>::max());
-        tcs.at(7).bb = ArcBounds(mid_x + 1, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
+        tcs.at(6).bb = BoundingBox(0, 0, mid_x, std::numeric_limits<int>::max());
+        tcs.at(7).bb = BoundingBox(mid_x + 1, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
 
-        tcs.at(8).bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
+        tcs.at(8).bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
 
         for (auto n : route_queue) {
             auto &nd = nets.at(n);
diff --git a/docs/archapi.md b/docs/archapi.md
index efd833d222..39b2a6a98d 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -333,7 +333,7 @@ Get a list of all wires on the device.
 
 Get a list of all bel pins attached to a given wire.
 
-### ArcBounds getRouteBoundingBox(WireId src, WireId dst) const
+### BoundingBox getRouteBoundingBox(WireId src, WireId dst) const
 
 Get the bounding box required to route an arc, assuming an uncongested
 chip. There may be significant performance impacts if routing regularly
@@ -732,7 +732,7 @@ Cluster Methods
 
 Gets the root cell of a cluster, which is used as a datum point when placing the cluster.
 
-### ArcBounds getClusterBounds(ClusterId cluster) const
+### BoundingBox getClusterBounds(ClusterId cluster) const
 
 Gets an approximate bounding box of the cluster. This is intended for area allocation in the placer and is permitted to occasionally give incorrect estimates, for example due to irregularities in the fabric depending on cluster placement. `getClusterPlacement` should always be used to get exact locations.
 
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index f031c9044e..eb87470433 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -504,9 +504,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
            (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
 
     bb.x0 = src.location.x;
     bb.y0 = src.location.y;
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 8650452000..a40719c13b 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -968,7 +968,7 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override;
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 4fc5d48d0a..d20fe253f5 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -730,7 +730,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
 
 // -----------------------------------------------------------------------
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
     int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 04f583d4bd..7e373a568b 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -701,7 +701,7 @@ struct Arch : ArchAPI<ArchRanges>
     // -------------------------------------------------
     delay_t estimateDelay(WireId src, WireId dst) const final;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const final;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const final;
     delay_t getDelayEpsilon() const final { return 20; }
     delay_t getRipupDelayPenalty() const final { return 120; }
     float getDelayNS(delay_t v) const final { return v * 0.001; }
@@ -896,7 +896,7 @@ struct Arch : ArchAPI<ArchRanges>
     }
 
     CellInfo *getClusterRootCell(ClusterId cluster) const override;
-    ArcBounds getClusterBounds(ClusterId cluster) const override;
+    BoundingBox getClusterBounds(ClusterId cluster) const override;
     Loc getClusterOffset(const CellInfo *cell) const override;
     bool isClusterStrict(const CellInfo *cell) const override;
     bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc
index 97a3e1a595..0dc75192a8 100644
--- a/fpga_interchange/arch_pack_clusters.cc
+++ b/fpga_interchange/arch_pack_clusters.cc
@@ -419,10 +419,10 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
     }
 }
 
-ArcBounds Arch::getClusterBounds(ClusterId cluster) const
+BoundingBox Arch::getClusterBounds(ClusterId cluster) const
 {
     // TODO: Implement this
-    ArcBounds bounds(0, 0, 0, 0);
+    BoundingBox bounds(0, 0, 0, 0);
     return bounds;
 }
 
diff --git a/fpga_interchange/cost_map.cc b/fpga_interchange/cost_map.cc
index c20ba11b44..d960c7cf04 100644
--- a/fpga_interchange/cost_map.cc
+++ b/fpga_interchange/cost_map.cc
@@ -184,7 +184,7 @@ static void assign_min_entry(delay_t *dst, const delay_t &src)
 }
 
 std::pair<delay_t, int> CostMap::get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
-                                                       const ArcBounds &bounds)
+                                                       const BoundingBox &bounds)
 {
 #ifdef DEBUG_FILL
     log_info("Filling %d, %d within (%d, %d, %d, %d)\n", cx, cy, bounds.x0, bounds.y0, bounds.x1, bounds.y1);
@@ -249,7 +249,7 @@ void CostMap::fill_holes(const Context *ctx, const TypeWirePair &type_pair, boos
     // find missing cost entries and fill them in by copying a nearby cost entry
     std::vector<std::tuple<unsigned, unsigned, delay_t>> missing;
     bool couldnt_fill = false;
-    auto shifted_bounds = ArcBounds(0, 0, matrix.shape()[0] - 1, matrix.shape()[1] - 1);
+    auto shifted_bounds = BoundingBox(0, 0, matrix.shape()[0] - 1, matrix.shape()[1] - 1);
     int max_fill = 0;
     for (unsigned ix = 0; ix < matrix.shape()[0]; ix++) {
         for (unsigned iy = 0; iy < matrix.shape()[1]; iy++) {
diff --git a/fpga_interchange/cost_map.h b/fpga_interchange/cost_map.h
index 88fb97e4e4..dfde29f9b2 100644
--- a/fpga_interchange/cost_map.h
+++ b/fpga_interchange/cost_map.h
@@ -58,7 +58,7 @@ class CostMap
                     delay_t delay_penality);
 
     std::pair<delay_t, int> get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
-                                                  const ArcBounds &bounds);
+                                                  const BoundingBox &bounds);
     delay_t get_penalty(const boost::multi_array<delay_t, 2> &matrix) const;
 };
 
diff --git a/generic/arch.cc b/generic/arch.cc
index a1d98200a3..c60c76747e 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -548,11 +548,11 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     if (uarch)
         return uarch->getRouteBoundingBox(src, dst);
-    ArcBounds bb;
+    BoundingBox bb;
 
     int src_x = wire_info(src).x;
     int src_y = wire_info(src).y;
diff --git a/generic/arch.h b/generic/arch.h
index 6b34c28941..a27dc78ee0 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -325,7 +325,7 @@ struct Arch : BaseArch<ArchRanges>
     uint32_t getDelayChecksum(delay_t v) const override { return 0; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     bool pack() override;
     bool place() override;
diff --git a/generic/viaduct_api.cc b/generic/viaduct_api.cc
index 8a7b631395..626150c28a 100644
--- a/generic/viaduct_api.cc
+++ b/generic/viaduct_api.cc
@@ -61,9 +61,9 @@ delay_t ViaductAPI::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel,
     int dy = abs(sink_loc.y - driver_loc.y);
     return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
 }
-ArcBounds ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
     int src_x = ctx->wire_info(src).x;
     int src_y = ctx->wire_info(src).y;
     int dst_x = ctx->wire_info(dst).x;
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
index 6f8adb3e25..6887f56c51 100644
--- a/generic/viaduct_api.h
+++ b/generic/viaduct_api.h
@@ -82,7 +82,7 @@ struct ViaductAPI
     // --- Route lookahead ---
     virtual delay_t estimateDelay(WireId src, WireId dst) const;
     virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const;
-    virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
+    virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const;
 
     // --- Flow hooks ---
     virtual void pack(){}; // replaces the pack function
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 756580e0b6..05b093639c 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1890,9 +1890,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
 
     int src_x = wires.at(src).x;
     int src_y = wires.at(src).y;
diff --git a/gowin/arch.h b/gowin/arch.h
index 0591e41a75..231fae6ee7 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -446,7 +446,7 @@ struct Arch : BaseArch<ArchRanges>
     uint32_t getDelayChecksum(delay_t v) const override { return 0; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     bool pack() override;
     bool place() override;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index c9c99d3aa4..6a80a6ff5f 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -1265,9 +1265,9 @@ void Arch::assignCellInfo(CellInfo *cell)
     }
 }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
 
     int src_x = chip_info->wire_data[src.index].x;
     int src_y = chip_info->wire_data[src.index].y;
diff --git a/ice40/arch.h b/ice40/arch.h
index 498a8b719b..9d10cddf3b 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -802,7 +802,7 @@ struct Arch : BaseArch<ArchRanges>
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     // -------------------------------------------------
 
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index b1a4a62a99..93eb4e6016 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -400,9 +400,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
            (0.01 + 0.01);
 }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
     bb.x0 = std::min(src.location.x, dst.location.x);
     bb.y0 = std::min(src.location.y, dst.location.y);
     bb.x1 = std::max(src.location.x, dst.location.x);
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 347f4edec3..ddcb9264d3 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -635,7 +635,7 @@ struct Arch : BaseArch<ArchRanges>
 
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
 
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     // Flow
     bool pack() override;
diff --git a/mistral/arch.cc b/mistral/arch.cc
index 4023f5c317..ce4f93fbd2 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -435,9 +435,9 @@ void Arch::assignArchInfo()
     }
 }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bounds;
+    BoundingBox bounds;
     int src_x = CycloneV::rn2x(src.node);
     int src_y = CycloneV::rn2y(src.node);
     int dst_x = CycloneV::rn2x(dst.node);
diff --git a/mistral/arch.h b/mistral/arch.h
index 5ceda53c9f..54a397718e 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -425,7 +425,7 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000.0f); };
     uint32_t getDelayChecksum(delay_t v) const override { return v; };
 
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port,
                                        int &clockInfoCount) const override;                                // delay.cc
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 5b1e8c1677..187e531286 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -702,9 +702,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
 
-ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
-    ArcBounds bb;
+    BoundingBox bb;
 
     int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width;
     int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;
diff --git a/nexus/arch.h b/nexus/arch.h
index 41c54cd8fa..5ac16f2825 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1300,7 +1300,7 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
-    ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     // for better DSP bounding boxes
     void pre_routing();

From d1afd6c0f1f8452d7461bbf33c84dbfd59236d03 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 7 Dec 2022 10:02:16 +0100
Subject: [PATCH 220/712] heap: Remove custom bounding-box type

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_heap.cc | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index bd8cd37def..8da4ee2e23 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -377,12 +377,6 @@ class HeAPPlacer
 
     TimingAnalyser tmg;
 
-    struct BoundingBox
-    {
-        // Actual bounding box
-        int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
-    };
-
     dict<IdString, BoundingBox> constraint_region_bounds;
 
     // In some cases, we can't use bindBel because we allow overlap in the earlier stages. So we use this custom

From 603b60da8dcadf23eec8609ffc128f8f191c1122 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 7 Dec 2022 10:27:58 +0100
Subject: [PATCH 221/712] api: add explain_invalid option to isBelLocationValid

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_api.h               | 2 +-
 common/kernel/arch_pybindings_shared.h | 4 ++--
 common/kernel/base_arch.h              | 2 +-
 common/place/placer1.cc                | 4 ++--
 common/place/placer_heap.cc            | 4 ++--
 docs/archapi.md                        | 6 +++++-
 docs/viaduct.md                        | 2 +-
 ecp5/arch.h                            | 2 +-
 ecp5/arch_place.cc                     | 2 +-
 fpga_interchange/arch.h                | 2 +-
 generic/arch.cc                        | 4 ++--
 generic/arch.h                         | 2 +-
 generic/viaduct/example/example.cc     | 2 +-
 generic/viaduct/fabulous/fabulous.cc   | 5 ++++-
 generic/viaduct/okami/okami.cc         | 2 +-
 generic/viaduct_api.h                  | 2 +-
 gowin/arch.cc                          | 2 +-
 gowin/arch.h                           | 2 +-
 ice40/arch.h                           | 2 +-
 ice40/arch_place.cc                    | 2 +-
 machxo2/arch.cc                        | 2 +-
 machxo2/arch.h                         | 2 +-
 mistral/arch.cc                        | 2 +-
 mistral/arch.h                         | 2 +-
 nexus/arch.h                           | 2 +-
 nexus/arch_place.cc                    | 2 +-
 26 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 94a8833870..56c5cf0a7a 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -135,7 +135,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual BelBucketId getBelBucketByName(IdString name) const = 0;
     virtual BelBucketId getBelBucketForBel(BelId bel) const = 0;
     virtual BelBucketId getBelBucketForCellType(IdString cell_type) const = 0;
-    virtual bool isBelLocationValid(BelId bel) const = 0;
+    virtual bool isBelLocationValid(BelId bel, bool explain_invalid = false) const = 0;
     virtual typename R::CellTypeRangeT getCellTypes() const = 0;
     virtual typename R::BelBucketRangeT getBelBuckets() const = 0;
     virtual typename R::BucketBelRangeT getBelsInBucket(BelBucketId bucket) const = 0;
diff --git a/common/kernel/arch_pybindings_shared.h b/common/kernel/arch_pybindings_shared.h
index d78d240c90..ac0eda072c 100644
--- a/common/kernel/arch_pybindings_shared.h
+++ b/common/kernel/arch_pybindings_shared.h
@@ -127,8 +127,8 @@ fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str
 fn_wrapper_2a_v<Context, decltype(&Context::writeSVG), &Context::writeSVG, pass_through<std::string>,
                 pass_through<std::string>>::def_wrap(ctx_cls, "writeSVG");
 
-fn_wrapper_1a<Context, decltype(&Context::isBelLocationValid), &Context::isBelLocationValid, pass_through<bool>,
-              conv_from_str<BelId>>::def_wrap(ctx_cls, "isBelLocationValid");
+fn_wrapper_2a<Context, decltype(&Context::isBelLocationValid), &Context::isBelLocationValid, pass_through<bool>,
+              conv_from_str<BelId>, pass_through<bool>>::def_wrap(ctx_cls, "isBelLocationValid");
 
 // const\_range\<BelBucketId\> getBelBuckets() const
 fn_wrapper_0a<Context, decltype(&Context::getBelBuckets), &Context::getBelBuckets,
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 53e28652bc..609d937888 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -357,7 +357,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
     {
         return getBelBucketByName(cell_type);
     };
-    virtual bool isBelLocationValid(BelId bel) const override { return true; }
+    virtual bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override { return true; }
     virtual typename R::CellTypeRangeT getCellTypes() const override
     {
         NPNR_ASSERT(cell_types_initialised);
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index 23264ce2d5..e37d3daf45 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -173,7 +173,7 @@ class SAPlacer
                     }
 
                     ctx->bindBel(bel, cell, STRENGTH_USER);
-                    if (!ctx->isBelLocationValid(bel)) {
+                    if (!ctx->isBelLocationValid(bel, /* explain_invalid */ true)) {
                         IdString bel_type = ctx->getBelType(bel);
                         log_error("Bel \'%s\' of type \'%s\' is not valid for cell "
                                   "\'%s\' of type \'%s\'\n",
@@ -404,7 +404,7 @@ class SAPlacer
         ctx->yield();
         for (auto bel : ctx->getBels()) {
             CellInfo *cell = ctx->getBoundBelCell(bel);
-            if (!ctx->isBelLocationValid(bel)) {
+            if (!ctx->isBelLocationValid(bel, /* explain_invalid */ true)) {
                 std::string cell_text = "no cell";
                 if (cell != nullptr)
                     cell_text = std::string("cell '") + ctx->nameOf(cell) + "'";
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 8da4ee2e23..0dfc29e63d 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -327,7 +327,7 @@ class HeAPPlacer
         bool any_bad_placements = false;
         for (auto bel : ctx->getBels()) {
             CellInfo *cell = ctx->getBoundBelCell(bel);
-            if (!ctx->isBelLocationValid(bel)) {
+            if (!ctx->isBelLocationValid(bel, /* explain_invalid */ true)) {
                 std::string cell_text = "no cell";
                 if (cell != nullptr)
                     cell_text = std::string("cell '") + ctx->nameOf(cell) + "'";
@@ -434,7 +434,7 @@ class HeAPPlacer
                 }
 
                 ctx->bindBel(bel, cell, STRENGTH_USER);
-                if (!ctx->isBelLocationValid(bel)) {
+                if (!ctx->isBelLocationValid(bel, /* explain_invalid */ true)) {
                     IdString bel_type = ctx->getBelType(bel);
                     log_error("Bel \'%s\' of type \'%s\' is not valid for cell "
                               "\'%s\' of type \'%s\'\n",
diff --git a/docs/archapi.md b/docs/archapi.md
index 39b2a6a98d..3a7994de7e 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -698,11 +698,15 @@ return the same value regardless if other cells are placed within the fabric.
 
 *BaseArch default: returns `cell_type == getBelType(bel)`*
 
-### bool isBelLocationValid(BelId bel) const
+### bool isBelLocationValid(BelId bel, bool explain_invalid = false) const
 
 Returns true if a bel in the current configuration is legal (for example,
 a flipflop's clock signal is correctly shared with all bels in a slice.)
 
+If and only if `explain_invalid` is set to true, then a message using
+`log_nonfatal_error` should be printed explaining why the placement is invalid
+to the end user.
+
 *BaseArch default: returns true*
 
 ### static const std::string defaultPlacer
diff --git a/docs/viaduct.md b/docs/viaduct.md
index a59310f14d..88398a05a4 100644
--- a/docs/viaduct.md
+++ b/docs/viaduct.md
@@ -64,7 +64,7 @@ X(F)
 ```c++
 bool checkBelAvail(BelId bel) const;
 bool isValidBelForCellType(IdString cell_type, BelId bel) const;
-bool isBelLocationValid(BelId bel) const;
+bool isBelLocationValid(BelId bel, bool explain_invalid = false) const;
 bool checkWireAvail(WireId wire) const;
 bool checkPipAvail(PipId pip) const;
 bool checkPipAvailForNet(PipId pip, NetInfo *net) const;
diff --git a/ecp5/arch.h b/ecp5/arch.h
index a40719c13b..6ce3c4ce67 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -1010,7 +1010,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
     // Placement validity checks
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     // Helper function for above
     bool slices_compatible(LogicTileStatus *lts) const;
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index fed9c055d3..3151cc3ea0 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -178,7 +178,7 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
     return true;
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     IdString bel_type = getBelType(bel);
     if (bel_type.in(id_TRELLIS_COMB, id_TRELLIS_FF, id_TRELLIS_RAMW)) {
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 7e373a568b..a44c7c21bc 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -851,7 +851,7 @@ struct Arch : ArchAPI<ArchRanges>
     }
 
     // Return true whether all Bels at a given location are valid
-    bool isBelLocationValid(BelId bel) const final
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const final
     {
         auto iter = tileStatus.find(bel.tile);
         if (iter == tileStatus.end()) {
diff --git a/generic/arch.cc b/generic/arch.cc
index c60c76747e..579140b901 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -693,10 +693,10 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     return tmg.clockingInfo.at(port).at(index);
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     if (uarch)
-        return uarch->isBelLocationValid(bel);
+        return uarch->isBelLocationValid(bel, explain_invalid);
     std::vector<const CellInfo *> cells;
     Loc loc = getBelLocation(bel);
     for (auto tbel : getBelsByTile(loc.x, loc.y)) {
diff --git a/generic/arch.h b/generic/arch.h
index a27dc78ee0..2a177be957 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -386,7 +386,7 @@ struct Arch : BaseArch<ArchRanges>
     {
         return uarch ? uarch->isValidBelForCellType(cell_type, bel) : cell_type == getBelType(bel);
     }
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
index 987c323697..7a61a59493 100644
--- a/generic/viaduct/example/example.cc
+++ b/generic/viaduct/example/example.cc
@@ -62,7 +62,7 @@ struct ExampleImpl : ViaductAPI
 
     void prePlace() override { assign_cell_info(); }
 
-    bool isBelLocationValid(BelId bel) const override
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
     {
         Loc l = ctx->getBelLocation(bel);
         if (is_io(l.x, l.y)) {
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 3c6f025ff0..e2fe1b74b5 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -81,7 +81,10 @@ struct FabulousImpl : ViaductAPI
     }
 
     void prePlace() override { assign_cell_info(); }
-    bool isBelLocationValid(BelId bel) const override { return blk_trk->check_validity(bel, cfg, cell_tags); }
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
+    {
+        return blk_trk->check_validity(bel, cfg, cell_tags);
+    }
 
   private:
     FabricConfig cfg; // TODO: non-default config
diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc
index 8142756fec..4ff97cb336 100644
--- a/generic/viaduct/okami/okami.cc
+++ b/generic/viaduct/okami/okami.cc
@@ -64,7 +64,7 @@ struct OkamiImpl : ViaductAPI
 
     void prePlace() override { assign_cell_info(); }
 
-    bool isBelLocationValid(BelId bel) const override
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
     {
         Loc l = ctx->getBelLocation(bel);
         if (is_io(l.x, l.y)) {
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
index 6887f56c51..3caa0ba19d 100644
--- a/generic/viaduct_api.h
+++ b/generic/viaduct_api.h
@@ -67,7 +67,7 @@ struct ViaductAPI
     virtual BelBucketId getBelBucketForBel(BelId bel) const;
     virtual BelBucketId getBelBucketForCellType(IdString cell_type) const;
     virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const;
-    virtual bool isBelLocationValid(BelId bel) const { return true; }
+    virtual bool isBelLocationValid(BelId bel, bool explain_invalid = false) const { return true; }
 
     // --- Wire and pip functions ---
     // Called when a wire/pip is placed/unplaced (with net=nullptr for a unbind)
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 05b093639c..28c0cb1e18 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2028,7 +2028,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     return tmg.clockingInfo.at(port).at(index);
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     Loc loc = getBelLocation(bel);
 
diff --git a/gowin/arch.h b/gowin/arch.h
index 231fae6ee7..a929ef00b7 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -458,7 +458,7 @@ struct Arch : BaseArch<ArchRanges>
     // Get the TimingClockingInfo of a port
     TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
 
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
diff --git a/ice40/arch.h b/ice40/arch.h
index 9d10cddf3b..d80d6f649e 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -840,7 +840,7 @@ struct Arch : BaseArch<ArchRanges>
     // implemented in arch_place.cc)
 
     // Return true whether all Bels at a given location are valid
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     // Helper function for above
     bool logic_cells_compatible(const CellInfo **it, const size_t size) const;
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 5c3fa3c5c1..d8232571c3 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -82,7 +82,7 @@ static inline bool _io_pintype_need_clk_en(unsigned pin_type)
     return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type);
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     if (getBelType(bel) == id_ICESTORM_LC) {
         std::array<const CellInfo *, 8> bel_cells;
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 93eb4e6016..d85921bcd8 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -451,7 +451,7 @@ bool Arch::route()
 
 // ---------------------------------------------------------------
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     // FIXME: Same deal as isValidBelForCell.
     return true;
diff --git a/machxo2/arch.h b/machxo2/arch.h
index ddcb9264d3..489a44ab1d 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -643,7 +643,7 @@ struct Arch : BaseArch<ArchRanges>
     bool route() override;
 
     // Placer
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
diff --git a/mistral/arch.cc b/mistral/arch.cc
index ce4f93fbd2..f3e385d12a 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -182,7 +182,7 @@ IdStringList Arch::getBelName(BelId bel) const
     return IdStringList(ids);
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     auto &data = bel_data(bel);
     if (data.type.in(id_MISTRAL_COMB, id_MISTRAL_MCOMB)) {
diff --git a/mistral/arch.h b/mistral/arch.h
index 54a397718e..aabe10c667 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -333,7 +333,7 @@ struct Arch : BaseArch<ArchRanges>
     PortType getBelPinType(BelId bel, IdString pin) const override { return bel_data(bel).pins.at(pin).dir; }
     std::vector<IdString> getBelPins(BelId bel) const override;
 
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
     {
diff --git a/nexus/arch.h b/nexus/arch.h
index 5ac16f2825..eb3059a59d 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1322,7 +1322,7 @@ struct Arch : BaseArch<ArchRanges>
     // implemented in arch_place.cc)
 
     // Return true whether all Bels at a given location are valid
-    bool isBelLocationValid(BelId bel) const override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     // -------------------------------------------------
 
diff --git a/nexus/arch_place.cc b/nexus/arch_place.cc
index 7b2c08ee4c..0bed30b486 100644
--- a/nexus/arch_place.cc
+++ b/nexus/arch_place.cc
@@ -96,7 +96,7 @@ bool Arch::nexus_logic_tile_valid(LogicTileStatus &lts) const
     return true;
 }
 
-bool Arch::isBelLocationValid(BelId bel) const
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     if (bel_tile_is(bel, LOC_LOGIC)) {
         LogicTileStatus *lts = tileStatus[bel.tile].lts;

From df99b4ff6c5ce88ce1a731dc8682ab1875b8c237 Mon Sep 17 00:00:00 2001
From: Sean Anderson <seanga2@gmail.com>
Date: Sun, 30 Oct 2022 19:21:41 -0400
Subject: [PATCH 222/712] ice40: Add debugs to isBelLocationValid for SB_IO

When there is a constraint conflict while placing IOs, the user gets an
error message such as

ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO'

While this identifies the problematic cell, it does not explain why
there is a problem. Add some verbose messages to allow users to
determine where the problem is. This can result in something like

Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin'

which provides something actionable.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
 ice40/arch_place.cc | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index d8232571c3..1d69d62f42 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -124,6 +124,8 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
                         return true;
 
                     // Conflict
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' conflicts with PLL cell '%s'\n", nameOf(cell), nameOf(pll_cell));
                     return false;
                 }
             }
@@ -135,18 +137,29 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
             // Check LVDS pairing
             if (cell->ioInfo.lvds) {
                 // Check correct z and complement location is free
-                if (ioLoc.z != 0)
+                if (ioLoc.z != 0) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Bel '%s' can't be used for LVDS\n", getCtx()->nameOfBel(bel));
                     return false;
+                }
                 BelId compBel = getBelByLocation(compLoc);
                 CellInfo *compCell = getBoundBelCell(compBel);
-                if (compCell)
+                if (compCell) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' LVDS complement occupied by cell '%s'\n", nameOf(cell),
+                                           nameOf(compCell));
                     return false;
+                }
             } else {
                 // Check LVDS IO is not placed at complement location
                 BelId compBel = getBelByLocation(compLoc);
                 const CellInfo *compCell = getBoundBelCell(compBel);
-                if (compCell && compCell->ioInfo.lvds)
+                if (compCell && compCell->ioInfo.lvds) {
+                    if (explain_invalid)
+                        log_nonfatal_error("Cell '%s' can't occupy LVDS complement of cell '%s'\n", nameOf(cell),
+                                           nameOf(compCell));
                     return false;
+                }
 
                 // Check for conflicts on shared nets
                 // - CLOCK_ENABLE
@@ -168,8 +181,13 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
                     };
 
                     for (int i = 0; i < 6; i++)
-                        if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr)))
+                        if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) {
+                            if (explain_invalid)
+                                log_nonfatal_error("Net '%s' for cell '%s' conflicts with net '%s' for '%s'\n",
+                                                   nameOf(nets[i]), nameOf(cell), nameOf(nets[i ^ 1]),
+                                                   nameOf(compCell));
                             return false;
+                        }
                 }
             }
 

From aa8359c73e47ca3fed620dbab9ef7ce8d4a6732c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 9 Dec 2022 12:55:22 +1000
Subject: [PATCH 223/712] gowin: BUGFIX: Correctly handle resets

When a single primitive occupies several cells, care must be taken when
manipulating the parameters of that primitive: when creating cells, each
cell must receive a copy of all the parameters and not modify them
unnecessarily.  That is, if possible, it is better to make all parameter
changes before dividing the primitive into cells.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 13 -------------
 gowin/pack.cc | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 04cf7af552..461b64c867 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2051,19 +2051,6 @@ void Arch::fix_pll_nets(Context *ctx)
             // This is general routing through CLK2 pip
             ci->setParam(id_FBSEL, Property("CLKFB0"));
         } while (0);
-
-        // resets
-        Property pr_enable("ENABLE"), pr_disable("DISABLE");
-        NetInfo *net = ci->getPort(id_RESET);
-        ci->setParam(id_RSTEN, pr_enable);
-        if (!port_used(ci, id_RESET) || net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
-            ci->setParam(id_RSTEN, pr_disable);
-        }
-        ci->setParam(id_PWDEN, pr_enable);
-        net = ci->getPort(id_RESET_P);
-        if (!port_used(ci, id_RESET_P) || net->name == id("$PACKER_VCC_NET") || net->name == id("$PACKER_GND_NET")) {
-            ci->setParam(id_PWDEN, pr_disable);
-        }
     }
 }
 
diff --git a/gowin/pack.cc b/gowin/pack.cc
index c36a47574b..e1119dde94 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1026,6 +1026,20 @@ static void pack_plls(Context *ctx)
                     for (int i = 0; i < 4; ++i) {
                         ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable);
                     }
+                    // resets
+                    NetInfo *net = ci->getPort(id_RESET);
+                    ci->setParam(id_RSTEN, pr_enable);
+                    if (!port_used(ci, id_RESET) || net->name == ctx->id("$PACKER_VCC_NET") ||
+                        net->name == ctx->id("$PACKER_GND_NET")) {
+                        ci->setParam(id_RSTEN, pr_disable);
+                    }
+                    ci->setParam(id_PWDEN, pr_enable);
+                    net = ci->getPort(id_RESET_P);
+                    if (!port_used(ci, id_RESET_P) || net->name == ctx->id("$PACKER_VCC_NET") ||
+                        net->name == ctx->id("$PACKER_GND_NET")) {
+                        ci->setParam(id_PWDEN, pr_disable);
+                    }
+
                     // B half
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
                     reconnect_rpllb(ctx, ci, cell.get());

From bc3d9f31088b2c8c41e5796c6f239cef54deea62 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 14 Dec 2022 15:35:55 +1000
Subject: [PATCH 224/712] gowin: not crush on unknown clock tap's sources

As preparation for possible changes to the clock wiring system.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/gfx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index 048ae62efa..5abb139990 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -4971,7 +4971,7 @@ void gfxSetPipDefaultDecal(Arch *arch, PipInfo &pip)
         // clock?
         if (dst_loc_id.in(id_GT00, id_GT10)) {
             WireInfo &wi = arch->wire_info(pip.srcWire);
-            if (wi.type.str(arch).substr(0, 3) != "UNK") {
+            if (wi.type.str(arch).substr(0, 5) == "SPINE") {
                 // create pip
                 GraphicElement el;
                 el.type = GraphicElement::TYPE_LOCAL_LINE;

From bc18d18a95d476b7d32bb5244a33fffaa637893f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 17 Dec 2022 10:37:15 +0000
Subject: [PATCH 225/712] ecp5: Only write bitstream if --textcfg passed

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/main.cc | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/ecp5/main.cc b/ecp5/main.cc
index f143d583c7..6abea4a9f7 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -111,11 +111,10 @@ void ECP5CommandHandler::customBitstream(Context *ctx)
         log_error("bitstream generation is not available in out-of-context mode (use --write to create a post-PnR JSON "
                   "design)\n");
 
-    std::string textcfg;
-    if (vm.count("textcfg"))
-        textcfg = vm["textcfg"].as<std::string>();
-
-    write_bitstream(ctx, basecfg, textcfg);
+    if (vm.count("textcfg")) {
+        std::string textcfg = vm["textcfg"].as<std::string>();
+        write_bitstream(ctx, basecfg, textcfg);
+    }
 }
 
 static std::string speedString(ArchArgs::SpeedGrade speed)

From ccb573298c28d84f3d1dc468ae5a701bb7ee3cf0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 17 Dec 2022 10:49:51 +0000
Subject: [PATCH 226/712] heap: encourage more spreading of heterogenous chains

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_heap.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 0dfc29e63d..339b88e7bd 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -663,7 +663,7 @@ class HeAPPlacer
             if (cell->cluster != ClusterId()) {
                 const auto base = cell_locs[cell->name];
                 for (auto child : cluster2cells.at(cell->cluster)) {
-                    if (child->type == cell->type && child != cell)
+                    if (child != cell)
                         chain_size[cell->name]++;
                     Loc offset = ctx->getClusterOffset(child);
                     cell_locs[child->name].x = std::max(0, std::min(max_x, base.x + offset.x));
@@ -856,7 +856,7 @@ class HeAPPlacer
             // Was now placed, ignore
             if (ci->bel != BelId())
                 continue;
-            // log_info("   Legalising %s (%s)\n", top.second.c_str(ctx), ci->type.c_str(ctx));
+            // log_info("   Legalising %s (%s) %d\n", top.second.c_str(ctx), ci->type.c_str(ctx), top.first);
             FastBels::FastBelsData *fb;
             fast_bels.getBelsForCellType(ci->type, &fb);
             int radius = 0;

From 6e0311efcaea8020d3e137e2708ec188eef8a74c Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@oxide.computer>
Date: Sat, 17 Dec 2022 15:50:14 -0800
Subject: [PATCH 227/712] Timeout when legal placement can't be found for cell

---
 common/place/placer_heap.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 0dfc29e63d..22b97a6cc0 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -862,6 +862,7 @@ class HeAPPlacer
             int radius = 0;
             int iter = 0;
             int iter_at_radius = 0;
+            int total_iters_for_cell = 0;
             bool placed = false;
             BelId bestBel;
             int best_inp_len = std::numeric_limits<int>::max();
@@ -880,9 +881,9 @@ class HeAPPlacer
             while (!placed) {
 
                 // Set a conservative timeout
-                if (iter > std::max(10000, 3 * int(ctx->cells.size())))
-                    log_error("Unable to find legal placement for cell '%s', check constraints and utilisation.\n",
-                              ctx->nameOf(ci));
+                if (total_iters_for_cell > std::max(10000, 3 * int(ctx->cells.size())))
+                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation.\n",
+                              ctx->nameOf(ci), total_iters_for_cell);
 
                 // Determine a search radius around the solver location (which increases over time) that is clamped to
                 // the region constraint for the cell (if applicable)
@@ -1084,6 +1085,8 @@ class HeAPPlacer
                         break;
                     }
                 }
+
+                total_iters_for_cell++;
             }
         }
         auto endt = std::chrono::high_resolution_clock::now();

From 2712cbf6e4289eb9c1830e367d68072e3d1f7564 Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@oxide.computer>
Date: Mon, 19 Dec 2022 14:00:19 -0800
Subject: [PATCH 228/712] Increase timeout

---
 common/place/placer_heap.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 22b97a6cc0..4ee9b909c3 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -879,9 +879,11 @@ class HeAPPlacer
             }
 
             while (!placed) {
+                // Set a conservative timeout. This is a rather large number and could probably be
+                // shaved down, but for now it will keep the process from running indefinite.
+                int timeout_limit = (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1;
 
-                // Set a conservative timeout
-                if (total_iters_for_cell > std::max(10000, 3 * int(ctx->cells.size())))
+                if (total_iters_for_cell > std::max(10000, timeout_limit))
                     log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation.\n",
                               ctx->nameOf(ci), total_iters_for_cell);
 

From d5299f144f0dc8cdcca9195d8ffbbd5a77cff77e Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@oxide.computer>
Date: Mon, 19 Dec 2022 22:58:52 -0800
Subject: [PATCH 229/712] Add --no-placer-timeout flag to override timeout
 during refinement

---
 common/kernel/command.cc    |  4 ++++
 common/place/placer_heap.cc | 12 +++++++-----
 common/place/placer_heap.h  |  1 +
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index c548509f7f..2200029950 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -189,6 +189,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("placer-heap-critexp", po::value<int>(),
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
+    general.add_options()("no-placer-timeout", "allow the placer to attempt placement without timeout");
 
 #if !defined(__wasm)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
@@ -328,6 +329,9 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("placer-heap-timingweight"))
         ctx->settings[ctx->id("placerHeap/timingWeight")] = std::to_string(vm["placer-heap-timingweight"].as<int>());
 
+    if (vm.count("no-placer-timeout"))
+        ctx->settings[ctx->id("placerHeap/noTimeout")] = true;
+
     if (vm.count("parallel-refine"))
         ctx->settings[ctx->id("placerHeap/parallelRefine")] = true;
 
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 4ee9b909c3..69edd3259b 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -828,6 +828,11 @@ class HeAPPlacer
     // Strict placement legalisation, performed after the initial HeAP spreading
     void legalise_placement_strict(bool require_validity = false)
     {
+        int placement_timeout = cfg.no_placement_timeout ? 0 :
+            // Set a conservative timeout. This is a rather large number and could probably be
+            // shaved down, but for now it will keep the process from running indefinite.
+            std::max(10000, (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1);
+
         auto startt = std::chrono::high_resolution_clock::now();
 
         // Unbind all cells placed in this solution
@@ -879,11 +884,7 @@ class HeAPPlacer
             }
 
             while (!placed) {
-                // Set a conservative timeout. This is a rather large number and could probably be
-                // shaved down, but for now it will keep the process from running indefinite.
-                int timeout_limit = (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1;
-
-                if (total_iters_for_cell > std::max(10000, timeout_limit))
+                if (placement_timeout > 0 && total_iters_for_cell > placement_timeout)
                     log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation.\n",
                               ctx->nameOf(ci), total_iters_for_cell);
 
@@ -1818,6 +1819,7 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
     timing_driven = ctx->setting<bool>("timing_driven");
     solverTolerance = 1e-5;
     placeAllAtOnce = false;
+    no_placement_timeout = ctx->setting<bool>("placerHeap/noTimeout", false);
 
     hpwl_scale_x = 1;
     hpwl_scale_y = 1;
diff --git a/common/place/placer_heap.h b/common/place/placer_heap.h
index 9c62869e9d..680e1dc718 100644
--- a/common/place/placer_heap.h
+++ b/common/place/placer_heap.h
@@ -42,6 +42,7 @@ struct PlacerHeapCfg
     float solverTolerance;
     bool placeAllAtOnce;
     bool parallelRefine;
+    bool no_placement_timeout;
 
     int hpwl_scale_x, hpwl_scale_y;
     int spread_scale_x, spread_scale_y;

From 923458a2c90ee295cf6502a83ca6182d1d281f48 Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@oxide.computer>
Date: Tue, 20 Dec 2022 11:15:06 -0800
Subject: [PATCH 230/712] Allow setting cell placement timeout

---
 common/kernel/command.cc    |  8 +++++---
 common/place/placer_heap.cc | 19 ++++++++++---------
 common/place/placer_heap.h  |  2 +-
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 2200029950..6d2dc9393f 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -189,7 +189,8 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("placer-heap-critexp", po::value<int>(),
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
-    general.add_options()("no-placer-timeout", "allow the placer to attempt placement without timeout");
+    general.add_options()("placer-heap-cell-placement-timeout", po::value<int>(),
+            "allow placer to attempt up to the given number of iterations to place the cell (int, default: design size^2 / 8, 0 for no timeout)");
 
 #if !defined(__wasm)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
@@ -329,8 +330,9 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("placer-heap-timingweight"))
         ctx->settings[ctx->id("placerHeap/timingWeight")] = std::to_string(vm["placer-heap-timingweight"].as<int>());
 
-    if (vm.count("no-placer-timeout"))
-        ctx->settings[ctx->id("placerHeap/noTimeout")] = true;
+    if (vm.count("placer-heap-cell-placement-timeout"))
+        ctx->settings[ctx->id("placerHeap/cellPlacementTimeout")] =
+            std::to_string(std::max(0, vm["placer-heap-cell-placement-timeout"].as<int>()));
 
     if (vm.count("parallel-refine"))
         ctx->settings[ctx->id("placerHeap/parallelRefine")] = true;
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 69edd3259b..ae04118bc9 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -218,7 +218,10 @@ class HeAPPlacer
 
         heap_runs.push_back(all_buckets);
         // The main HeAP placer loop
-        log_info("Running main analytical placer.\n");
+        if (cfg.cell_placement_timeout > 0)
+            log_info("Running main analytical placer, max placement attempts per cell = %d.\n", cfg.cell_placement_timeout);
+        else
+            log_info("Running main analytical placer.\n");
         while (stalled < 5 && (solved_hpwl <= legal_hpwl * 0.8)) {
             // Alternate between particular bel types and all bels
             for (auto &run : heap_runs) {
@@ -828,11 +831,6 @@ class HeAPPlacer
     // Strict placement legalisation, performed after the initial HeAP spreading
     void legalise_placement_strict(bool require_validity = false)
     {
-        int placement_timeout = cfg.no_placement_timeout ? 0 :
-            // Set a conservative timeout. This is a rather large number and could probably be
-            // shaved down, but for now it will keep the process from running indefinite.
-            std::max(10000, (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1);
-
         auto startt = std::chrono::high_resolution_clock::now();
 
         // Unbind all cells placed in this solution
@@ -884,8 +882,8 @@ class HeAPPlacer
             }
 
             while (!placed) {
-                if (placement_timeout > 0 && total_iters_for_cell > placement_timeout)
-                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation.\n",
+                if (cfg.cell_placement_timeout > 0 && total_iters_for_cell > cfg.cell_placement_timeout)
+                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of attempts.\n",
                               ctx->nameOf(ci), total_iters_for_cell);
 
                 // Determine a search radius around the solver location (which increases over time) that is clamped to
@@ -1819,7 +1817,10 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
     timing_driven = ctx->setting<bool>("timing_driven");
     solverTolerance = 1e-5;
     placeAllAtOnce = false;
-    no_placement_timeout = ctx->setting<bool>("placerHeap/noTimeout", false);
+    cell_placement_timeout = ctx->setting<int>("placerHeap/cellPlacementTimeout",
+            // Set a conservative default. This is a rather large number and could probably
+            // be shaved down, but for now it will keep the process from running indefinite.
+            std::max(10000, (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1));
 
     hpwl_scale_x = 1;
     hpwl_scale_y = 1;
diff --git a/common/place/placer_heap.h b/common/place/placer_heap.h
index 680e1dc718..e554a8e01c 100644
--- a/common/place/placer_heap.h
+++ b/common/place/placer_heap.h
@@ -42,7 +42,7 @@ struct PlacerHeapCfg
     float solverTolerance;
     bool placeAllAtOnce;
     bool parallelRefine;
-    bool no_placement_timeout;
+    int cell_placement_timeout;
 
     int hpwl_scale_x, hpwl_scale_y;
     int spread_scale_x, spread_scale_y;

From be1f700b0b3099dd7762bf8cbe23ecca4b77fe5b Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@oxide.computer>
Date: Tue, 20 Dec 2022 13:10:37 -0800
Subject: [PATCH 231/712] Set divisor instead of absolute value

---
 common/kernel/command.cc    |  2 +-
 common/place/placer_heap.cc | 13 +++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 6d2dc9393f..65aa0299f7 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -190,7 +190,7 @@ po::options_description CommandHandler::getGeneralOptions()
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
     general.add_options()("placer-heap-cell-placement-timeout", po::value<int>(),
-            "allow placer to attempt up to the given number of iterations to place the cell (int, default: design size^2 / 8, 0 for no timeout)");
+            "allow placer to attempt up to max(10000, total cells^2 / N) iterations to place a cell (int N, default: 8, 0 for no timeout)");
 
 #if !defined(__wasm)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index ae04118bc9..781a764616 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -1817,10 +1817,15 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
     timing_driven = ctx->setting<bool>("timing_driven");
     solverTolerance = 1e-5;
     placeAllAtOnce = false;
-    cell_placement_timeout = ctx->setting<int>("placerHeap/cellPlacementTimeout",
-            // Set a conservative default. This is a rather large number and could probably
-            // be shaved down, but for now it will keep the process from running indefinite.
-            std::max(10000, (int(ctx->cells.size()) * int(ctx->cells.size()) / 8) + 1));
+
+    int timeout_divisor = ctx->setting<int>("placerHeap/cellPlacementTimeout", 8);
+    if (timeout_divisor > 0) {
+        // Set a conservative default. This is a rather large number and could probably
+        // be shaved down, but for now it will keep the process from running indefinite.
+        cell_placement_timeout = std::max(10000, (int(ctx->cells.size()) * int(ctx->cells.size()) / timeout_divisor));
+    } else {
+        cell_placement_timeout = 0;
+    }
 
     hpwl_scale_x = 1;
     hpwl_scale_y = 1;

From d6cbe4b7f83a083ac174d7f8b0dd26eca61ebe53 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 21 Dec 2022 16:13:08 +1000
Subject: [PATCH 232/712] gowin: fix build for wasm

A large number of global variables are not suitable for WASM, so
completely disable the graphics part where the main array of them is
used.  For other architectures GUI is still possible.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 8 ++++++++
 gowin/gfx.cc  | 2 ++
 gowin/gfx.h   | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 461b64c867..8c908b0412 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -523,6 +523,7 @@ void Arch::setBelDecal(BelId bel, DecalXY active, DecalXY inactive)
 
 void Arch::setDefaultDecals(void)
 {
+#ifndef NO_GUI
     for (BelId bel : getBels()) {
         gfxSetBelDefaultDecal(this, bel_info(bel));
     }
@@ -533,6 +534,7 @@ void Arch::setDefaultDecals(void)
         gfxSetWireDefaultDecal(this, wire_info(wire));
     }
     fixClockSpineDecals();
+#endif
 }
 
 void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
@@ -1125,8 +1127,10 @@ Arch::Arch(ArchArgs args) : args(args)
     addDecalGraphic(IdString(), GraphicElement());
 
     if (args.gui) {
+#ifndef NO_GUI
         // decals
         gfxCreateBelDecals(this);
+#endif
     }
 
     // setup package
@@ -1216,11 +1220,13 @@ Arch::Arch(ArchArgs args) : args(args)
         int col = i % db->cols;
         const TilePOD *tile = db->grid[i].get();
         if (args.gui) {
+#ifndef NO_GUI
             // CRU decal
             snprintf(buf, 32, "R%dC%d_CRU", row + 1, col + 1);
             grpname = id(buf);
             addGroup(grpname);
             setGroupDecal(grpname, gfxGetCruGroupDecalXY(col, row));
+#endif
         }
         // setup wires
         const PairPOD *pips[2] = {tile->pips.get(), tile->clock_pips.get()};
@@ -1420,8 +1426,10 @@ Arch::Arch(ArchArgs args) : args(args)
                     snprintf(buf, 32, "R%dC%d_LUT_GRP%d", row + 1, col + 1, z);
                     grpname = id(buf);
                     if (args.gui) {
+#ifndef NO_GUI
                         addGroup(grpname);
                         setGroupDecal(grpname, gfxGetLutGroupDecalXY(col, row, z >> 1));
+#endif
                     }
                 }
                 break;
diff --git a/gowin/gfx.cc b/gowin/gfx.cc
index 5abb139990..a06df6f8f3 100644
--- a/gowin/gfx.cc
+++ b/gowin/gfx.cc
@@ -24,6 +24,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+#ifndef NO_GUI
 // LUTs
 const float lut_w = 0.6732 - 0.6386;
 const float lut_h = 0.9392 - 0.9074;
@@ -5824,5 +5825,6 @@ DecalXY gfxGetCruGroupDecalXY(int x, int y)
     decalxy.y = y;
     return decalxy;
 }
+#endif // NO_GUI
 
 NEXTPNR_NAMESPACE_END
diff --git a/gowin/gfx.h b/gowin/gfx.h
index 623b9fb20e..4c798ed901 100644
--- a/gowin/gfx.h
+++ b/gowin/gfx.h
@@ -24,6 +24,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+#ifndef NO_GUI
 void gfxCreateBelDecals(Arch *arch);
 void gfxSetBelDefaultDecal(Arch *arch, BelInfo &bel);
 void gfxSetIOBWireDecals(Arch *arch, BelInfo &bel);
@@ -32,6 +33,7 @@ void gfxSetPipDefaultDecal(Arch *arch, PipInfo &pip);
 void gfxSetWireDefaultDecal(Arch *arch, WireInfo &wire);
 DecalXY gfxGetLutGroupDecalXY(int x, int y, int z);
 DecalXY gfxGetCruGroupDecalXY(int x, int y);
+#endif
 
 NEXTPNR_NAMESPACE_END
 

From bd628ce5918129ae37b64abf897bf8270c97b11b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Dec 2022 15:26:39 +0100
Subject: [PATCH 233/712] Remove deprecated functions

---
 common/kernel/design_utils.h |  3 ---
 common/kernel/timing.cc      |  8 ++++----
 common/kernel/util.h         | 19 -------------------
 ecp5/pack.cc                 |  6 +++---
 4 files changed, 7 insertions(+), 29 deletions(-)

diff --git a/common/kernel/design_utils.h b/common/kernel/design_utils.h
index 069600b548..c290a35be7 100644
--- a/common/kernel/design_utils.h
+++ b/common/kernel/design_utils.h
@@ -31,9 +31,6 @@ NEXTPNR_NAMESPACE_BEGIN
 Utilities for design manipulation, intended for use inside packing algorithms
  */
 
-// Disconnect a net (if connected) from old, and connect it to rep
-void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdString rep_name);
-
 // If a net drives a given port of a cell matching a predicate (in many
 // cases more than one cell type, e.g. SB_DFFxx so a predicate is used), return
 // the first instance of that cell (otherwise nullptr). If exclusive is set to
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 47235789a2..924f336c62 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -707,7 +707,7 @@ void TimingAnalyser::print_critical_path(CellPortKey endpoint, domain_id_t domai
         ctx->getDelayNS(ports.at(cursor).domain_pairs.at(domain_pair).setup_slack));
     while (cursor != CellPortKey()) {
         log("        %s.%s (net %s)\n", ctx->nameOf(cursor.cell), ctx->nameOf(cursor.port),
-            ctx->nameOf(get_net_or_empty(ctx->cells.at(cursor.cell).get(), cursor.port)));
+            ctx->nameOf(ctx->cells.at(cursor.cell)->getPort(cursor.port)));
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
         cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
@@ -865,7 +865,7 @@ struct Timing
                     topological_order.emplace_back(o->net);
                     for (int i = 0; i < clocks; i++) {
                         TimingClockingInfo clkInfo = ctx->getPortClockingInfo(cell.second.get(), o->name, i);
-                        const NetInfo *clknet = get_net_or_empty(cell.second.get(), clkInfo.clock_port);
+                        const NetInfo *clknet = cell.second->getPort(clkInfo.clock_port);
                         IdString clksig = clknet ? clknet->name : async_clock;
                         net_data[o->net][ClockEvent{clksig, clknet ? clkInfo.edge : RISING_EDGE}] =
                                 TimingData{clkInfo.clockToQ.maxDelay()};
@@ -1125,7 +1125,7 @@ struct Timing
                         if (portClass == TMG_REGISTER_INPUT) {
                             for (int i = 0; i < port_clocks; i++) {
                                 TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, i);
-                                const NetInfo *clknet = get_net_or_empty(usr.cell, clkInfo.clock_port);
+                                const NetInfo *clknet = usr.cell->getPort(clkInfo.clock_port);
                                 IdString clksig = clknet ? clknet->name : async_clock;
                                 process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, clkInfo.setup.maxDelay());
                             }
@@ -1295,7 +1295,7 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
     if (portClass == TMG_REGISTER_OUTPUT) {
         for (int i = 0; i < port_clocks; i++) {
             TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
-            const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
+            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
             if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
                 last_port = clockInfo.clock_port;
                 clock_start = i;
diff --git a/common/kernel/util.h b/common/kernel/util.h
index c10abb72da..f04a956bd5 100644
--- a/common/kernel/util.h
+++ b/common/kernel/util.h
@@ -102,25 +102,6 @@ bool bool_or_default(const Container &ct, const KeyType &key, bool def = false)
     return bool(int_or_default(ct, key, int(def)));
 };
 
-// Return a net if port exists, or nullptr
-inline const NetInfo *get_net_or_empty(const CellInfo *cell, const IdString port)
-{
-    auto found = cell->ports.find(port);
-    if (found != cell->ports.end())
-        return found->second.net;
-    else
-        return nullptr;
-}
-
-inline NetInfo *get_net_or_empty(CellInfo *cell, const IdString port)
-{
-    auto found = cell->ports.find(port);
-    if (found != cell->ports.end())
-        return found->second.net;
-    else
-        return nullptr;
-}
-
 // Get only value from a forward iterator begin/end pair.
 //
 // Generates assertion failure if std::distance(begin, end) != 1.
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 4c8ceee83f..f542934d0e 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -219,7 +219,7 @@ class Ecp5Packer
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (is_ff(ctx, ci)) {
-                NetInfo *di = get_net_or_empty(ci, id_DI);
+                NetInfo *di = ci->getPort(id_DI);
                 if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
                     CellInfo *comb = di->driver.cell;
                     if (comb->cluster != ClusterId()) {
@@ -306,7 +306,7 @@ class Ecp5Packer
 
         // Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
         auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
-            NetInfo *f1 = get_net_or_empty(lut5, id_F1);
+            NetInfo *f1 = lut5->getPort(id_F1);
             NPNR_ASSERT(f1 != nullptr);
             NPNR_ASSERT(f1->driver.cell != nullptr);
             return f1->driver.cell;
@@ -2806,7 +2806,7 @@ bool Arch::pack()
 void Arch::assign_arch_info_for_cell(CellInfo *ci)
 {
     auto get_port_net = [&](CellInfo *ci, IdString p) {
-        NetInfo *n = get_net_or_empty(ci, p);
+        NetInfo *n = ci->getPort(p);
         return n ? n->name : IdString();
     };
     if (ci->type == id_TRELLIS_COMB) {

From 4af8964069c2e250bbbb80851272a9e10ab206f6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Dec 2022 16:11:10 +0100
Subject: [PATCH 234/712] propagate netShareWeight

---
 common/place/placer_heap.cc | 6 +++++-
 common/place/placer_heap.h  | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 7fa27206d0..fd722d151c 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -362,7 +362,11 @@ class HeAPPlacer
         } else
 #endif
         {
-            if (!placer1_refine(ctx, Placer1Cfg(ctx))) {
+            auto placer1_cfg = Placer1Cfg(ctx);
+            placer1_cfg.hpwl_scale_x = cfg.hpwl_scale_x;
+            placer1_cfg.hpwl_scale_y = cfg.hpwl_scale_y;
+            placer1_cfg.netShareWeight = cfg.netShareWeight;
+            if (!placer1_refine(ctx, placer1_cfg)) {
                 return false;
             }
         }
diff --git a/common/place/placer_heap.h b/common/place/placer_heap.h
index e554a8e01c..c79e3dfc15 100644
--- a/common/place/placer_heap.h
+++ b/common/place/placer_heap.h
@@ -41,6 +41,7 @@ struct PlacerHeapCfg
     bool timing_driven;
     float solverTolerance;
     bool placeAllAtOnce;
+    float netShareWeight;
     bool parallelRefine;
     int cell_placement_timeout;
 

From 64f7306b24ac26bf05a3009b2f4b54489739ab28 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Dec 2022 20:16:13 +0100
Subject: [PATCH 235/712] initialize netShareWeight

---
 common/place/placer_heap.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index fd722d151c..efc04df501 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -1817,6 +1817,7 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
     criticalityExponent = ctx->setting<int>("placerHeap/criticalityExponent");
     timingWeight = ctx->setting<int>("placerHeap/timingWeight");
     parallelRefine = ctx->setting<bool>("placerHeap/parallelRefine", false);
+    netShareWeight = ctx->setting<float>("placerHeap/netShareWeight", 0);
 
     timing_driven = ctx->setting<bool>("timing_driven");
     solverTolerance = 1e-5;

From 2e5c799566bb3e588db3ef3411a63eb58cb5733a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 23 Dec 2022 17:14:26 +1000
Subject: [PATCH 236/712] doc: fix a mistype

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 docs/netlist.md | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/docs/netlist.md b/docs/netlist.md
index 43a96dde04..6cff4a25ca 100644
--- a/docs/netlist.md
+++ b/docs/netlist.md
@@ -42,8 +42,7 @@ It also implements functions for getting timing data, mirroring that of the Arch
 
 ## NetInfo
 
-`NetInfo` instances have the following fields:\
-
+`NetInfo` instances have the following fields:
  - `name` is the IdString name of the net - for nets with multiple names, one name is chosen according to a set of rules by the JSON frontend
  - `hierpath` is name of the hierarchical cell containing the instance, for designs with hierarchy
  - `driver` refers to the source of the net using `PortRef`; `driver.cell == nullptr` means that the net is undriven. Nets must have zero or one driver only. The corresponding cell port must be an output and its `PortInfo::net` must refer back to this net.

From 8424dc79d2555ce6b070371c9a5fb11aa76e950d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 29 Dec 2022 11:17:45 +1000
Subject: [PATCH 237/712] gowin: correct the delay calculation

And do a full enumeration when searching for a delay because it is not
yet clear whether the orderliness of the vector is guaranteed.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8c908b0412..40570af72a 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -698,17 +698,28 @@ template <class T, class C> const T *genericLookup(const T *first, int len, cons
     }
 }
 
+template <class T, class C> const T *timingLookup(const T *first, int len, const T val, C compare)
+{
+    for (int i = 0; i < len; ++i) {
+        auto res = &first[i];
+        if (!(compare(*res, val) || compare(val, *res))) {
+            return res;
+        }
+    }
+    return nullptr;
+}
+
 DelayQuad delayLookup(const TimingPOD *first, int len, IdString name)
 {
     TimingPOD needle;
     needle.name_id = name.index;
-    const TimingPOD *timing = genericLookup(first, len, needle, timingCompare);
+    const TimingPOD *timing = timingLookup(first, len, needle, timingCompare);
     DelayQuad delay;
     if (timing != nullptr) {
-        delay.fall.max_delay = std::max(timing->ff, timing->rf) / 1000;
-        delay.fall.min_delay = std::min(timing->ff, timing->rf) / 1000;
-        delay.rise.max_delay = std::max(timing->rr, timing->fr) / 1000;
-        delay.rise.min_delay = std::min(timing->rr, timing->fr) / 1000;
+        delay.fall.max_delay = std::max(timing->ff, timing->rf) / 1000.;
+        delay.fall.min_delay = std::min(timing->ff, timing->rf) / 1000.;
+        delay.rise.max_delay = std::max(timing->rr, timing->fr) / 1000.;
+        delay.rise.min_delay = std::min(timing->rr, timing->fr) / 1000.;
     } else {
         delay = DelayQuad(0);
     }

From b8ab3116b223648af19c190c392c1fe36844907b Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 30 Dec 2022 11:55:39 +1000
Subject: [PATCH 238/712] gowin: improve clock wire routing

The dedicated router for clock wires now understands not only the IO
pins but also the rPLL outputs as clock sources.

This simple router sets an optimal route, so it is now the default
router. It can be disabled with the --disable-globals command line flag
if desired, but this is not recommended due to possible clock skew.

Still for GW1N-4C there is no good router for clock wires as there
external quartz resonator is connected via PLL.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc    | 10 +++++++
 gowin/arch.h     |  1 +
 gowin/globals.cc | 73 ++++++++++++++++++++++++++++--------------------
 gowin/globals.h  | 20 ++++++-------
 gowin/main.cc    | 10 +++----
 5 files changed, 69 insertions(+), 45 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 40570af72a..33f25405b8 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2016,6 +2016,16 @@ static bool is_PLL_T_FB_iob(const Context *ctx, const CellInfo *cell)
     return is_spec_iob(ctx, cell, ctx->id("RPLL_T_FB"));
 }
 
+bool Arch::is_GCLKT_iob(const CellInfo *cell)
+{
+    for (int i = 0; i < 6; ++i) {
+        if (is_spec_iob(getCtx(), cell, idf("GCLKT_%d", i))) {
+            return true;
+        }
+    }
+    return false;
+}
+
 // If the PLL input can be connected using a direct wire, then do so,
 // bypassing conventional routing.
 void Arch::fix_pll_nets(Context *ctx)
diff --git a/gowin/arch.h b/gowin/arch.h
index bbaf3e607a..a5c339cc5b 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -480,6 +480,7 @@ struct Arch : BaseArch<ArchRanges>
     void auto_longwires();
     void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col);
     void fix_pll_nets(Context *ctx);
+    bool is_GCLKT_iob(const CellInfo *cell);
 
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
diff --git a/gowin/globals.cc b/gowin/globals.cc
index 21ee722ab8..785a011196 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -38,22 +38,28 @@ bool GowinGlobalRouter::is_clock_port(PortRef const &user)
     return false;
 }
 
-std::pair<WireId, BelId> GowinGlobalRouter::clock_io(Context *ctx, PortRef const &driver)
+std::pair<WireId, BelId> GowinGlobalRouter::clock_src(Context *ctx, PortRef const &driver)
 {
-    // XXX normally all alternative functions of the pins should be passed
-    // in the chip database, but at the moment we find them from aliases/pips
-    // XXX check diff inputs too
-    if (driver.cell == nullptr || driver.cell->type != id_IOB || !driver.cell->attrs.count(id_BEL)) {
+    if (driver.cell == nullptr) {
         return std::make_pair(WireId(), BelId());
     }
-    // clock IOs have pips output->SPINExx
 
-    BelInfo &bel = ctx->bel_info(ctx->id(driver.cell->attrs[id_BEL].as_string()));
-    WireId wire = bel.pins[id_O].wire;
-    for (auto const pip : ctx->getPipsDownhill(wire)) {
-        if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
+    BelInfo &bel = ctx->bel_info(driver.cell->bel);
+    WireId wire;
+    if (driver.cell->type == id_IOB) {
+        if (ctx->is_GCLKT_iob(driver.cell)) {
+            wire = bel.pins[id_O].wire;
             return std::make_pair(wire, bel.name);
         }
+        return std::make_pair(WireId(), BelId());
+    }
+    if (driver.cell->type == id_RPLLA) {
+        if (driver.port == id_CLKOUT || driver.port == id_CLKOUTP || driver.port == id_CLKOUTD ||
+            driver.port == id_CLKOUTD3) {
+            wire = bel.pins[driver.port].wire;
+            return std::make_pair(wire, bel.name);
+        }
+        return std::make_pair(WireId(), BelId());
     }
     return std::make_pair(WireId(), BelId());
 }
@@ -64,12 +70,12 @@ void GowinGlobalRouter::gather_clock_nets(Context *ctx, std::vector<globalnet_t>
     for (auto const &net : ctx->nets) {
         NetInfo const *ni = net.second.get();
         auto new_clock = clock_nets.end();
-        auto clock_wire_bel = clock_io(ctx, ni->driver);
+        auto clock_wire_bel = clock_src(ctx, ni->driver);
         if (clock_wire_bel.first != WireId()) {
             clock_nets.emplace_back(net.first);
             new_clock = --clock_nets.end();
-            new_clock->clock_io_wire = clock_wire_bel.first;
-            new_clock->clock_io_bel = clock_wire_bel.second;
+            new_clock->clock_wire = clock_wire_bel.first;
+            new_clock->clock_bel = clock_wire_bel.second;
         }
         for (auto const &user : ni->users) {
             if (is_clock_port(user)) {
@@ -86,8 +92,8 @@ void GowinGlobalRouter::gather_clock_nets(Context *ctx, std::vector<globalnet_t>
 
     if (ctx->verbose) {
         for (auto const &net : clock_nets) {
-            log_info("  Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
-                     net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
+            log_info("  Net:%s, ports:%d, clock source:%s\n", net.name.c_str(ctx), net.clock_ports,
+                     net.clock_wire == WireId() ? "No" : net.clock_wire.c_str(ctx));
         }
     }
 }
@@ -238,33 +244,35 @@ void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
         }
         used_pips.insert(spine_pip_id);
 
-        // >>> SPINExx <- IO
+        // >>> SPINExx <- Src
         dstWire = ctx->getPipSrcWire(spine_pip_id);
         dstWireInfo = ctx->wire_info(dstWire);
-        PipId io_pip_id = PipId();
+        PipId src_pip_id = PipId();
         for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
-            if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
-                io_pip_id = uphill_pip;
+            if (ctx->getPipSrcWire(uphill_pip) == net.clock_wire) {
+                src_pip_id = uphill_pip;
             }
         }
-        NPNR_ASSERT(io_pip_id != PipId());
+        NPNR_ASSERT(src_pip_id != PipId());
         if (ctx->verbose) {
-            log_info("       IO Pip:%s\n", io_pip_id.c_str(ctx));
+            log_info("       Src Pip:%s\n", src_pip_id.c_str(ctx));
         }
         // if already routed
-        if (used_pips.count(io_pip_id)) {
+        if (used_pips.count(src_pip_id)) {
             if (ctx->verbose) {
                 log_info("      ^routed already^\n");
             }
             continue;
         }
-        used_pips.insert(io_pip_id);
+        used_pips.insert(src_pip_id);
     }
     log_info("  Net %s is routed.\n", net.name.c_str(ctx));
-    for (auto const pip : used_pips) {
-        ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
+    if (!ctx->net_info(net.name).users.empty()) {
+        for (auto const pip : used_pips) {
+            ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
+        }
+        ctx->bindWire(net.clock_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
     }
-    ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
 }
 
 void GowinGlobalRouter::route_globals(Context *ctx)
@@ -289,16 +297,21 @@ void GowinGlobalRouter::mark_globals(Context *ctx)
     int max_clock = 3, cur_clock = -1;
     for (auto &net : clock_nets) {
         // XXX only IO clock for now
-        if (net.clock_io_wire == WireId()) {
-            log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
+        if (net.clock_wire == WireId()) {
+            log_info(" Non clock source, skip %s.\n", net.name.c_str(ctx));
             continue;
         }
         if (++cur_clock >= max_clock) {
             log_info(" No more clock wires left, skip the remaining nets.\n");
             break;
         }
-        net.clock = cur_clock;
-        BelInfo &bi = ctx->bel_info(net.clock_io_bel);
+        if (ctx->net_info(net.name).users.empty()) {
+            --cur_clock;
+            net.clock = -1;
+        } else {
+            net.clock = cur_clock;
+        }
+        BelInfo &bi = ctx->bel_info(net.clock_bel);
         bi.gb = true;
         nets.emplace_back(net);
     }
diff --git a/gowin/globals.h b/gowin/globals.h
index 69232d7c88..307a1a2c2b 100644
--- a/gowin/globals.h
+++ b/gowin/globals.h
@@ -39,32 +39,32 @@ class GowinGlobalRouter
     {
         IdString name;
         int clock_ports;
-        BelId clock_io_bel;
-        WireId clock_io_wire; // IO wire if there is one
-        int clock;            // clock #
+        BelId clock_bel;
+        WireId clock_wire; // clock wire if there is one
+        int clock;         // clock #
 
         globalnet_t()
         {
             name = IdString();
             clock_ports = 0;
-            clock_io_bel = BelId();
-            clock_io_wire = WireId();
+            clock_bel = BelId();
+            clock_wire = WireId();
             clock = -1;
         }
         globalnet_t(IdString _name)
         {
             name = _name;
             clock_ports = 0;
-            clock_io_bel = BelId();
-            clock_io_wire = WireId();
+            clock_bel = BelId();
+            clock_wire = WireId();
             clock = -1;
         }
 
         // sort
         bool operator<(const globalnet_t &other) const
         {
-            if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
-                return !(clock_io_wire != WireId());
+            if ((clock_wire != WireId()) ^ (other.clock_wire != WireId())) {
+                return !(clock_wire != WireId());
             }
             return clock_ports < other.clock_ports;
         }
@@ -76,7 +76,7 @@ class GowinGlobalRouter
     std::vector<globalnet_t> nets;
 
     bool is_clock_port(PortRef const &user);
-    std::pair<WireId, BelId> clock_io(Context *ctx, PortRef const &driver);
+    std::pair<WireId, BelId> clock_src(Context *ctx, PortRef const &driver);
     void gather_clock_nets(Context *ctx, std::vector<globalnet_t> &clock_nets);
     IdString route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock, pool<IdString> &used_pips,
                                      pool<IdString> &undo_wires);
diff --git a/gowin/main.cc b/gowin/main.cc
index 36bd865669..ccf4d19027 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -51,7 +51,8 @@ po::options_description GowinCommandHandler::getArchOptions()
     specific.add_options()("device", po::value<std::string>(), "device name");
     specific.add_options()("family", po::value<std::string>(), "family name");
     specific.add_options()("cst", po::value<std::string>(), "physical constraints file");
-    specific.add_options()("enable-globals", "separate routing of the clocks");
+    specific.add_options()("enable-globals", "enable separate routing of the clocks");
+    specific.add_options()("disable-globals", "disable separate routing of the clocks");
     specific.add_options()("enable-auto-longwires", "automatic detection and routing of long wires");
     return specific;
 }
@@ -84,11 +85,10 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
 
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     // routing options
-    // the default values will change in the future
-    ctx->settings[ctx->id("arch.enable-globals")] = 0;
+    ctx->settings[ctx->id("arch.enable-globals")] = 1;
     ctx->settings[ctx->id("arch.enable-auto-longwires")] = 0;
-    if (vm.count("enable-globals")) {
-        ctx->settings[ctx->id("arch.enable-globals")] = 1;
+    if (vm.count("disable-globals")) {
+        ctx->settings[ctx->id("arch.enable-globals")] = 0;
     }
     if (vm.count("enable-auto-longwires")) {
         ctx->settings[ctx->id("arch.enable-auto-longwires")] = 1;

From 7c4f44c7836de9b9ad735468f1b370f5ee1325de Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 1 Jan 2023 10:26:28 +1000
Subject: [PATCH 239/712] doc: fix the list format

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 docs/coding.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/coding.md b/docs/coding.md
index db2ec079b6..e25165ae03 100644
--- a/docs/coding.md
+++ b/docs/coding.md
@@ -78,9 +78,9 @@ Placers might want to create their own indices of bels (for example, bels by typ
 As nextpnr allows arbitrary constraints on bels for more advanced packer-free flows and complex real-world architectures; placements must be checked for legality using `isBelLocationValid` (after placement) and the placement rejected if invalid. For analytical placement algorithms; after creating a spread-out AP solution the legality of placing each cell needs to be checked. In practice, the cost of this is fairly low as the architecture should ensure these functions are as fast as possible.
 
 There are several routes for timing information in the placer:
-    - sink `PortRef`s have a `budget` value annotated by calling `assign_budget` which is an estimate of the maximum delay that an arc may have
-    - sink ports can have a criticality (value between 0 and 1 where 1 is the critical path) associated with them by using `get_criticalities` and a `NetCriticalityMap`
-    - `predictDelay` and its derivative `predictArcDelay` returns an estimated delay for a sink port based on placement information
+ - sink `PortRef`s have a `budget` value annotated by calling `assign_budget` which is an estimate of the maximum delay that an arc may have
+ - sink ports can have a criticality (value between 0 and 1 where 1 is the critical path) associated with them by using `get_criticalities` and a `NetCriticalityMap`
+ - `predictDelay` and its derivative `predictArcDelay` returns an estimated delay for a sink port based on placement information
 
 
 ### Bel Buckets

From d210a5adeda40ac1b63b033e4a9f8c7c2217f2ef Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 2 Jan 2023 08:39:00 +0100
Subject: [PATCH 240/712] ecp5: Improve error handling for missing end-"

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/lpf.cc | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 70ebfe81c3..4f02d22d7d 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -44,21 +44,22 @@ bool Arch::apply_lpf(std::string filename, std::istream &in)
     auto isempty = [](const std::string &str) {
         return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c) || c == '\r' || c == '\n'; });
     };
-    auto strip_quotes = [](const std::string &str) {
-        if (str.at(0) == '"') {
-            NPNR_ASSERT(str.back() == '"');
-            return str.substr(1, str.size() - 2);
-        } else {
-            return str;
-        }
-    };
-
     try {
         if (!in)
             log_error("failed to open LPF file\n");
         std::string line;
         std::string linebuf;
         int lineno = 0;
+        auto strip_quotes = [&](const std::string &str) {
+            if (str.at(0) == '"') {
+                if (str.back() != '"') {
+                    log_error("expected '\"' at end of string '%s' (on line %d)\n", str.c_str(), lineno);
+                }
+                return str.substr(1, str.size() - 2);
+            } else {
+                return str;
+            }
+        };
         while (std::getline(in, line)) {
             ++lineno;
             size_t cstart = line.find('#');

From f89b959b5f56ba8d91e1e7f8a645b267a5a7bb89 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 2 Jan 2023 09:33:11 +0100
Subject: [PATCH 241/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/command.cc    | 5 +++--
 common/place/placer_heap.cc | 7 +++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 65aa0299f7..bf78514847 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -190,7 +190,8 @@ po::options_description CommandHandler::getGeneralOptions()
                           "placer heap criticality exponent (int, default: 2)");
     general.add_options()("placer-heap-timingweight", po::value<int>(), "placer heap timing weight (int, default: 10)");
     general.add_options()("placer-heap-cell-placement-timeout", po::value<int>(),
-            "allow placer to attempt up to max(10000, total cells^2 / N) iterations to place a cell (int N, default: 8, 0 for no timeout)");
+                          "allow placer to attempt up to max(10000, total cells^2 / N) iterations to place a cell (int "
+                          "N, default: 8, 0 for no timeout)");
 
 #if !defined(__wasm)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
@@ -332,7 +333,7 @@ void CommandHandler::setupContext(Context *ctx)
 
     if (vm.count("placer-heap-cell-placement-timeout"))
         ctx->settings[ctx->id("placerHeap/cellPlacementTimeout")] =
-            std::to_string(std::max(0, vm["placer-heap-cell-placement-timeout"].as<int>()));
+                std::to_string(std::max(0, vm["placer-heap-cell-placement-timeout"].as<int>()));
 
     if (vm.count("parallel-refine"))
         ctx->settings[ctx->id("placerHeap/parallelRefine")] = true;
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index efc04df501..8ba5a70db5 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -219,7 +219,8 @@ class HeAPPlacer
         heap_runs.push_back(all_buckets);
         // The main HeAP placer loop
         if (cfg.cell_placement_timeout > 0)
-            log_info("Running main analytical placer, max placement attempts per cell = %d.\n", cfg.cell_placement_timeout);
+            log_info("Running main analytical placer, max placement attempts per cell = %d.\n",
+                     cfg.cell_placement_timeout);
         else
             log_info("Running main analytical placer.\n");
         while (stalled < 5 && (solved_hpwl <= legal_hpwl * 0.8)) {
@@ -887,7 +888,9 @@ class HeAPPlacer
 
             while (!placed) {
                 if (cfg.cell_placement_timeout > 0 && total_iters_for_cell > cfg.cell_placement_timeout)
-                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of attempts.\n",
+                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and "
+                              "utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of "
+                              "attempts.\n",
                               ctx->nameOf(ci), total_iters_for_cell);
 
                 // Determine a search radius around the solver location (which increases over time) that is clamped to

From 174848b4b3bb84883c1623315ad10fdb5eb5185c Mon Sep 17 00:00:00 2001
From: Adam Greig <adam@adamgreig.com>
Date: Wed, 9 Nov 2022 02:44:37 +0000
Subject: [PATCH 242/712] Include ALU54B in cell types with wire location
 overrides

---
 ecp5/arch_place.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 3151cc3ea0..30ae9b1b47 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -203,7 +203,7 @@ void Arch::setup_wire_locations()
         CellInfo *ci = cell.second.get();
         if (ci->bel == BelId())
             continue;
-        if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
+        if (ci->type.in(id_ALU54B, id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
             for (auto &port : ci->ports) {
                 if (port.second.net == nullptr)
                     continue;

From 8d8c244e007a5f2d937c569365785ae066c4ce5f Mon Sep 17 00:00:00 2001
From: Adam Greig <adam@adamgreig.com>
Date: Wed, 9 Nov 2022 02:47:00 +0000
Subject: [PATCH 243/712] Add remapping of DSP clk/ce/rst signals in a block.

Each DSP block contains two slices, and each slice contains multiple
MULT18X18D and ALU54B units. Each unit configures each register to use
any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are
connected per unit (so for example, two MULTs in the same block could
connect their CLK0s to different external signals). However, the
hardware only has one actual port per block, so it's required that
all CLK0 signals within a block are the same.

Because the packer is in general allowed to combine two unrelated units
into one block, it may end up combining units that use different signals
for the same port, which would eventually have caused a router failure.

This commit adds validity checks which ensure only unique signals are
used per block, and adds remapping so that conflicting signals are
automatically reassigned when possible and required.
---
 ecp5/arch.cc       |   4 +
 ecp5/arch.h        |   6 ++
 ecp5/arch_place.cc | 253 +++++++++++++++++++++++++++++++++++++++++++++
 ecp5/constids.inc  |  17 +++
 4 files changed, 280 insertions(+)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index eb87470433..a7041e0405 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -634,6 +634,10 @@ bool Arch::place()
         for (auto &cell : cells)
             cell.second->belStrength = STRENGTH_LOCKED;
 
+    // Once placement is complete, DSP slices sharing a block may need
+    // CLK/CE/RST ports remapped to avoid conflicting assignments.
+    remap_dsp_blocks();
+
     getCtx()->settings[id_place] = 1;
 
     archInfoToAttributes();
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 6ce3c4ce67..40b931d612 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -1085,6 +1085,12 @@ struct Arch : BaseArch<ArchRanges>
     std::vector<BelBucketId> buckets;
 
     mutable std::vector<TileStatus> tile_status;
+
+    // -------------------------------------------------
+    bool is_dsp_location_valid(CellInfo* cell) const;
+    void remap_dsp_blocks();
+    void remap_dsp_cell(CellInfo* ci, const std::array<IdString, 4> &ports,
+                        std::array<NetInfo*, 4> &assigned_nets);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 30ae9b1b47..2bb601c251 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -190,12 +190,265 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
         } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
             return args.type != ArchArgs::LFE5U_25F && args.type != ArchArgs::LFE5U_45F &&
                    args.type != ArchArgs::LFE5U_85F;
+        } else if (cell->type.in(id_MULT18X18D, id_ALU54B)) {
+            return is_dsp_location_valid(cell);
         } else {
             return true;
         }
     }
 }
 
+// Check if this DSP cell placement would result in more than four distinct
+// CLK/CE/RST signals per block of two DSP slices.
+bool Arch::is_dsp_location_valid(CellInfo* cell) const
+{
+    // Find the location of the DSP0 tile.
+    int block_x = cell->getLocation().x - cell->getLocation().z;
+    int block_y = cell->getLocation().y;
+
+    const std::array<std::array<IdString, 4>, 3> block_ports = {{
+        {id_CLK0, id_CLK1, id_CLK2, id_CLK3},
+        {id_CE0, id_CE1, id_CE2, id_CE3},
+        {id_RST0, id_RST1, id_RST2, id_RST3}
+    }};
+    const std::array<const char*, 3> port_names = {"CLK", "CE", "RST"};
+    std::array<std::set<NetInfo*>, 3> block_nets = {};
+    bool cells_locked = true;
+
+    // Count the number of distinct CLK, CE, and RST signals used by
+    // all the MULT18X18D and ALU54B bels in the DSP block.
+    for (int dx : {0, 1, 3, 4, 5, 7}) {
+        BelId dsp_bel = getBelByLocation(Loc(block_x + dx, block_y, dx));
+        CellInfo* dsp_cell = getBoundBelCell(dsp_bel);
+        if (dsp_cell == nullptr)
+            continue;
+
+        if (dsp_cell->belStrength < STRENGTH_LOCKED)
+            cells_locked = false;
+
+        for (size_t i = 0; i < block_ports.size(); i++) {
+            auto nets = &block_nets[i];
+            for (IdString port : block_ports[i]) {
+                NetInfo *net = dsp_cell->ports.at(port).net;
+                if (net == nullptr)
+                    continue;
+                nets->insert(net);
+                if (nets->size() > 4) {
+                    // When all cells considered so far are locked or manually
+                    // placed, the placer cannot fix this problem, so report
+                    // a specific error message.
+                    if (cells_locked) {
+                        log_error("DSP block containing %s '%s' has more than "
+                                  "four distinct %s signals.\n",
+                                  dsp_cell->type.c_str(getCtx()),
+                                  dsp_cell->name.c_str(getCtx()),
+                                  port_names[i]);
+                    }
+                    return false;
+                }
+            }
+        }
+    }
+    return true;
+}
+
+// Check all cells in the design to locate used DSP blocks, then remap
+// CLK, CE, and RST port and attribute assignments to ensure each port
+// is connected to the same net throughout each block.
+void Arch::remap_dsp_blocks()
+{
+    std::set<Location> processed_blocks;
+
+    const std::array<std::array<IdString, 4>, 3> block_ports = {{
+        {id_CLK0, id_CLK1, id_CLK2, id_CLK3},
+        {id_CE0, id_CE1, id_CE2, id_CE3},
+        {id_RST0, id_RST1, id_RST2, id_RST3},
+    }};
+
+    for (auto &cell: cells) {
+        CellInfo *ci = cell.second.get();
+        if (!ci->type.in(id_MULT18X18D, id_ALU54B))
+            continue;
+
+        // Locate DSP0 tile for block containing this cell.
+        Loc loc = ci->getLocation();
+        Location block_loc(loc.x - loc.z, loc.y);
+        if (processed_blocks.count(block_loc) == 1)
+            continue;
+        processed_blocks.insert(block_loc);
+
+        for (auto &ports : block_ports) {
+            // Store assigned nets for each port.
+            std::array<NetInfo*, 4> assigned_nets = {};
+
+            // Process each possible MULT18X18D or ALU54B in this block.
+            for (int dx : {0, 1, 3, 4, 5, 7}) {
+                Loc dsp_loc = Loc(block_loc.x + dx, block_loc.y, dx);
+                BelId dsp_bel = getBelByLocation(dsp_loc);
+                CellInfo* dsp_cell = getBoundBelCell(dsp_bel);
+                if (dsp_cell == nullptr)
+                    continue;
+                remap_dsp_cell(dsp_cell, ports, assigned_nets);
+            }
+        }
+    }
+}
+
+// Remap CLK/CE/RST ports in a DSP cell so that:
+// * if a port's slot in assigned_nets already matches its net, no action
+//   is taken.
+// * if a port's slot in assigned_nets is empty and that port's net isn't in
+//   assigned_nets, the slot is set to that port's current net and no remapping
+//   is performed.
+// * if a port's currently connected net is already present in a different slot
+//   to that port, then remap references to that port to the already assigned
+//   port instead.
+// * if a port's slot in assigned_nets refers to a different net than the one
+//   the port is currently connected to, and the currently connected net isn't
+//   present elsewhere in assigned_nets, then allocate a new port for this net
+//   and remap references to the old port to refer to the new port.
+// This method is called with the same assigned_nets array for each cell
+// inside a single DSP block. The end result is to ensure that for all cells
+// in a single DSP block, all CLK/CE/RST ports are connected to the same net.
+//
+// ports: array of port names to remap, either CLK0-3 or CE0-3 or RST0-3
+// assigned_nets: array of final net assignments to those four ports for
+//                the block this cell is in.
+void Arch::remap_dsp_cell(
+    CellInfo* ci,
+    const std::array<IdString, 4> &ports,
+    std::array<NetInfo*, 4> &assigned_nets
+) {
+    // New names to use in attributes that used to refer to an old port name.
+    std::array<IdString, 4> remap_ports = {};
+
+    // Parameters that might need updating when ports are remapped.
+    const std::array<IdString, 48> remap_params = {
+        id_REG_INPUTA_CLK, id_REG_INPUTA_CE, id_REG_INPUTA_RST,
+        id_REG_INPUTB_CLK, id_REG_INPUTB_CE, id_REG_INPUTB_RST,
+        id_REG_INPUTC_CLK, id_REG_INPUTC_CE, id_REG_INPUTC_RST,
+        id_REG_PIPELINE_CLK, id_REG_PIPELINE_CE, id_REG_PIPELINE_RST,
+        id_REG_OUTPUT_CLK, id_REG_OUTPUT_CE, id_REG_OUTPUT_RST,
+        id_REG_INPUTC0_CLK, id_REG_INPUTC0_CE, id_REG_INPUTC0_RST,
+        id_REG_INPUTC1_CLK, id_REG_INPUTC1_CE, id_REG_INPUTC1_RST,
+        id_REG_OPCODEOP0_0_CLK, id_REG_OPCODEOP0_0_CE, id_REG_OPCODEOP0_0_RST,
+        id_REG_OPCODEOP1_0_CLK,
+        id_REG_OPCODEOP0_1_CLK, id_REG_OPCODEOP0_1_CE, id_REG_OPCODEOP0_1_RST,
+        id_REG_OPCODEOP1_1_CLK,
+        id_REG_OPCODEIN_0_CLK, id_REG_OPCODEIN_0_CE, id_REG_OPCODEIN_0_RST,
+        id_REG_OPCODEIN_1_CLK, id_REG_OPCODEIN_1_CE, id_REG_OPCODEIN_1_RST,
+        id_REG_OUTPUT0_CLK, id_REG_OUTPUT0_CE, id_REG_OUTPUT0_RST,
+        id_REG_OUTPUT1_CLK, id_REG_OUTPUT1_CE, id_REG_OUTPUT1_RST,
+        id_REG_FLAG_CLK, id_REG_FLAG_CE, id_REG_FLAG_RST,
+        id_REG_INPUTCFB_CLK, id_REG_INPUTCFB_CE, id_REG_INPUTCFB_RST,
+        id_HIGHSPEED_CLK,
+    };
+
+    // First, go through each port and determine which new port to assign
+    // its net to, and what to remap any parmeters that reference it.
+    for (size_t i = 0; i < ports.size(); i++) {
+        IdString port = ports[i];
+        NetInfo *net = ci->ports.at(port).net;
+        if (net == nullptr)
+            continue;
+        auto assigned = std::find(assigned_nets.cbegin(), assigned_nets.cend(), net);
+        if (assigned == assigned_nets.cend()) {
+            if (assigned_nets[i] == nullptr) {
+                // If neither the net nor the port have been assigned
+                // yet, we can simply assign the net to its original
+                // port and don't need to change any params.
+                assigned_nets[i] = net;
+            } else {
+                // If the net hasn't been assigned but the port has,
+                // we need to assign the net to a different port and
+                // update any attributes that refer to it, while
+                // ensuring the net at the new port is preserved.
+                size_t j = std::distance(
+                    assigned_nets.cbegin(),
+                    std::find(assigned_nets.cbegin(), assigned_nets.cend(), nullptr));
+                if (j == assigned_nets.size()) {
+                    log_error("DSP block containing %s '%s': no unused ports "
+                              "to remap %s to; too many distinct signals in "
+                              "block.\n",
+                              ci->type.c_str(getCtx()),
+                              ci->name.c_str(getCtx()),
+                              port.c_str(getCtx()));
+                }
+                assigned_nets[j] = net;
+                remap_ports[i] = ports[j];
+                log_info("DSP: %s '%s': Connection to %s remapped to %s\n",
+                         ci->type.c_str(getCtx()), ci->name.c_str(getCtx()),
+                         ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
+            }
+        } else if (*assigned != assigned_nets[i]) {
+            // If the net has been assigned already and to a different
+            // port than this one, we'll remap the port and attributes
+            // to point to the already-assigned port.
+            size_t j = std::distance(assigned_nets.cbegin(), assigned);
+            remap_ports[i] = ports[j];
+            log_info("DSP: %s '%s': Connection to %s remapped to %s\n",
+                     ci->type.c_str(getCtx()), ci->name.c_str(getCtx()),
+                     ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
+        }
+    }
+
+    // Second, connect each port to its assigned net.
+    for (size_t i = 0; i < ports.size(); i++) {
+        IdString port = ports[i];
+        ci->disconnectPort(port);
+        if (assigned_nets[i] != nullptr) {
+            ci->connectPort(port, assigned_nets[i]);
+        }
+    }
+
+    // Third, remap any parameters that refer to old ports to refer to the
+    // new port instead.
+    for (auto remap_param : remap_params) {
+        auto param = ci->params.find(remap_param);
+        if (param == ci->params.end())
+            continue;
+        for (size_t i = 0; i < remap_ports.size(); i++) {
+            Property &prop = param->second;
+            if (remap_ports[i] != IdString()
+                && prop.is_string
+                && prop.str == ports[i].str(getCtx())
+            ) {
+                prop = Property(remap_ports[i].str(getCtx()));
+                break;
+            }
+        }
+    }
+
+    // Finally, only when remapping CLK ports, also move any `CLKn_DIV`
+    // to the new clock port.
+    const std::array<IdString, 4> clk_div_params = {
+        id_CLK0_DIV, id_CLK1_DIV, id_CLK2_DIV, id_CLK3_DIV};
+    std::array<Property, 4> new_clk_div_props = {};
+    if (ports[0] == id_CLK0) {
+        for (size_t i = 0; i < 4; i++) {
+            if (remap_ports[i] == IdString())
+                continue;
+            auto param = ci->params.find(clk_div_params[i]);
+            if (param == ci->params.end())
+                continue;
+            size_t j = std::distance(
+                ports.cbegin(),
+                std::find(ports.cbegin(), ports.cend(), remap_ports[i]));
+            if (j != ports.size()) {
+                new_clk_div_props[j] = param->second;
+            }
+        }
+
+        for (size_t i = 0; i < 4; i++) {
+            if (new_clk_div_props[i] != Property()) {
+                ci->params[clk_div_params[i]] = new_clk_div_props[i];
+            } else {
+                ci->params.erase(clk_div_params[i]);
+            }
+        }
+    }
+}
+
 void Arch::setup_wire_locations()
 {
     wire_loc_overrides.clear();
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index c161f94f98..6445b098f8 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1769,6 +1769,8 @@ X(REGMODE_A)
 X(REGMODE_B)
 X(REGSET)
 X(REG_FLAG_CLK)
+X(REG_FLAG_CE)
+X(REG_FLAG_RST)
 X(REG_INPUTA_CE)
 X(REG_INPUTA_CLK)
 X(REG_INPUTA_RST)
@@ -1776,8 +1778,17 @@ X(REG_INPUTB_CE)
 X(REG_INPUTB_CLK)
 X(REG_INPUTB_RST)
 X(REG_INPUTC0_CLK)
+X(REG_INPUTC0_CE)
+X(REG_INPUTC0_RST)
 X(REG_INPUTC1_CLK)
+X(REG_INPUTC1_CE)
+X(REG_INPUTC1_RST)
 X(REG_INPUTC_CLK)
+X(REG_INPUTC_CE)
+X(REG_INPUTC_RST)
+X(REG_INPUTCFB_CLK)
+X(REG_INPUTCFB_CE)
+X(REG_INPUTCFB_RST)
 X(REG_OPCODEIN_0_CE)
 X(REG_OPCODEIN_0_CLK)
 X(REG_OPCODEIN_0_RST)
@@ -1793,12 +1804,18 @@ X(REG_OPCODEOP0_1_RST)
 X(REG_OPCODEOP1_0_CLK)
 X(REG_OPCODEOP1_1_CLK)
 X(REG_OUTPUT0_CLK)
+X(REG_OUTPUT0_CE)
+X(REG_OUTPUT0_RST)
 X(REG_OUTPUT1_CLK)
+X(REG_OUTPUT1_CE)
+X(REG_OUTPUT1_RST)
 X(REG_OUTPUT_CLK)
+X(REG_OUTPUT_CE)
 X(REG_OUTPUT_RST)
 X(REG_PIPELINE_CE)
 X(REG_PIPELINE_CLK)
 X(REG_PIPELINE_RST)
+X(HIGHSPEED_CLK)
 X(RESETMODE)
 X(RNDPAT)
 X(RSTAMUX)

From b22eebac30124a4fc550ff5c9cd9767de266d481 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 18 Jan 2023 19:18:02 +1000
Subject: [PATCH 244/712] gowin: add a PLL primitive for the GW1NS-4 series

  * both instances of the new PLLVR type are supported;
  * primitive placement is optimized for the use of dedicated PLL clock
    pins;
  * all 4 outputs of each primitive can use the clock nets (only 5 lines
    in total at the same time so far).

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 118 +++++++++++++++++++++++++++++++++++++++++----
 gowin/arch.h       |   7 ++-
 gowin/cells.cc     |  37 ++++++++++++++
 gowin/cells.h      |   3 +-
 gowin/constids.inc |   2 +
 gowin/globals.cc   |   4 +-
 gowin/pack.cc      |  69 +++++++++++++++++---------
 7 files changed, 202 insertions(+), 38 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 33f25405b8..a924f0005f 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -384,6 +384,9 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi
     pi.delay = delay;
     pi.loc = loc;
 
+    // log_info("addpip %s->%s %.6f | %s name:%s\n" , srcWire.c_str(this), dstWire.c_str(this),
+    // getDelayNS(delay.maxDelay()), srcWire.c_str(this), name.c_str(this));
+
     wire_info(srcWire).downhill.push_back(name);
     wire_info(dstWire).uphill.push_back(name);
     pip_ids.push_back(name);
@@ -1112,10 +1115,46 @@ void Arch::add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col
     }
 }
 
+void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col)
+{
+    IdString portname;
+
+    for (int pid :
+         {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5, ID_IDSEL0,
+          ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,  ID_ODSEL2,  ID_ODSEL3,
+          ID_ODSEL4,  ID_ODSEL5,  ID_VREN,    ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0, ID_DUTYDA1,
+          ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3,   ID_RESET,   ID_RESET_P}) {
+        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
+        IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+        if (wires.count(wire) == 0) {
+            GlobalAliasPOD alias;
+            alias.dest_col = col;
+            alias.dest_row = row;
+            alias.dest_id = portname.hash();
+            auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+            NPNR_ASSERT(alias_src != nullptr);
+            int srcrow = alias_src->src_row;
+            int srccol = alias_src->src_col;
+            IdString srcid = IdString(alias_src->src_id);
+            wire = wireToGlobal(srcrow, srccol, db, srcid);
+            // addWire(wire, portname, srccol, srcrow);
+        }
+        addBelInput(belname, IdString(pid), wire);
+    }
+    for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
+        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
+        addBelOutput(belname, IdString(pid), idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+    }
+}
 Arch::Arch(ArchArgs args) : args(args)
 {
     family = args.family;
 
+    max_clock = 5;
+    if (family == "GW1NZ-1") {
+        max_clock = 3;
+    }
+
     // Load database
     std::string chipdb = stringf("gowin/chipdb-%s.bin", family.c_str());
     auto db = reinterpret_cast<const DatabasePOD *>(get_chipdb(chipdb));
@@ -1267,12 +1306,17 @@ Arch::Arch(ArchArgs args) : args(args)
             bool dff = true;
             bool oddrc = false;
             switch (static_cast<ConstIds>(bel->type_id)) {
-            case ID_RPLLA: {
+            case ID_PLLVR:
+                belname = idf("R%dC%d_PLLVR", row + 1, col + 1);
+                addBel(belname, id_PLLVR, Loc(col, row, BelZ::pllvr_z), false);
+                add_pllvr_ports(db, bel, belname, row, col);
+                break;
+            case ID_RPLLA:
                 snprintf(buf, 32, "R%dC%d_RPLLA", row + 1, col + 1);
                 belname = id(buf);
                 addBel(belname, id_RPLLA, Loc(col, row, BelZ::pll_z), false);
                 add_plla_ports(bel, belname, row, col);
-            } break;
+                break;
             case ID_RPLLB:
                 snprintf(buf, 32, "R%dC%d_RPLLB", row + 1, col + 1);
                 belname = id(buf);
@@ -2006,16 +2050,26 @@ static bool is_spec_iob(const Context *ctx, const CellInfo *cell, IdString pin_n
     return have_pin;
 }
 
-static bool is_PLL_T_IN_iob(const Context *ctx, const CellInfo *cell)
+static bool is_RPLL_T_IN_iob(const Context *ctx, const CellInfo *cell)
 {
     return is_spec_iob(ctx, cell, ctx->id("RPLL_T_IN"));
 }
 
-static bool is_PLL_T_FB_iob(const Context *ctx, const CellInfo *cell)
+static bool is_LPLL_T_IN_iob(const Context *ctx, const CellInfo *cell)
+{
+    return is_spec_iob(ctx, cell, ctx->id("LPLL_T_IN"));
+}
+
+static bool is_RPLL_T_FB_iob(const Context *ctx, const CellInfo *cell)
 {
     return is_spec_iob(ctx, cell, ctx->id("RPLL_T_FB"));
 }
 
+static bool is_LPLL_T_FB_iob(const Context *ctx, const CellInfo *cell)
+{
+    return is_spec_iob(ctx, cell, ctx->id("LPLL_T_FB"));
+}
+
 bool Arch::is_GCLKT_iob(const CellInfo *cell)
 {
     for (int i = 0; i < 6; ++i) {
@@ -2032,7 +2086,7 @@ void Arch::fix_pll_nets(Context *ctx)
 {
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
-        if (ci->type != id_RPLLA) {
+        if (ci->type != id_RPLLA && ci->type != id_PLLVR) {
             continue;
         }
         // *** CLKIN
@@ -2046,10 +2100,54 @@ void Arch::fix_pll_nets(Context *ctx)
                 ci->setParam(id_INSEL, Property("UNKNOWN"));
                 break;
             }
-            if (net_driven_by(ctx, net, is_PLL_T_IN_iob, id_O) != nullptr) {
-                ci->disconnectPort(id_CLKIN);
-                ci->setParam(id_INSEL, Property("CLKIN0"));
-                break;
+            if (net_driven_by(ctx, net, is_RPLL_T_IN_iob, id_O) != nullptr) {
+                if (ci->type == id_RPLLA) {
+                    ci->disconnectPort(id_CLKIN);
+                    ci->setParam(id_INSEL, Property("CLKIN0"));
+                    break;
+                }
+                BelId bel = id("R1C37_PLLVR");
+                if (ci->type == id_PLLVR) {
+                    if (checkBelAvail(bel) || ci->belStrength != STRENGTH_LOCKED) {
+                        if (ci->bel == bel) {
+                            unbindBel(bel);
+                        } else {
+                            if (!checkBelAvail(bel) && ci->belStrength != STRENGTH_LOCKED) {
+                                CellInfo *other_ci = getBoundBelCell(bel);
+                                unbindBel(bel);
+                                BelId our_bel = ci->bel;
+                                unbindBel(our_bel);
+                                bindBel(our_bel, other_ci, STRENGTH_LOCKED);
+                            }
+                        }
+                        ci->disconnectPort(id_CLKIN);
+                        ci->setParam(id_INSEL, Property("CLKIN0"));
+                        bindBel(bel, ci, STRENGTH_LOCKED);
+                        break;
+                    }
+                }
+            }
+            if (net_driven_by(ctx, net, is_LPLL_T_IN_iob, id_O) != nullptr) {
+                BelId bel = id("R1C28_PLLVR");
+                if (ci->type == id_PLLVR) {
+                    if (checkBelAvail(bel) || ci->belStrength != STRENGTH_LOCKED) {
+                        if (ci->bel == bel) {
+                            unbindBel(bel);
+                        } else {
+                            if (!checkBelAvail(bel) && ci->belStrength != STRENGTH_LOCKED) {
+                                CellInfo *other_ci = getBoundBelCell(bel);
+                                unbindBel(bel);
+                                BelId our_bel = ci->bel;
+                                unbindBel(our_bel);
+                                bindBel(our_bel, other_ci, STRENGTH_LOCKED);
+                            }
+                        }
+                        ci->disconnectPort(id_CLKIN);
+                        ci->setParam(id_INSEL, Property("CLKIN0"));
+                        bindBel(bel, ci, STRENGTH_LOCKED);
+                        break;
+                    }
+                }
             }
             // XXX do special bels (HCLK etc)
             // This is general routing through CLK0 pip
@@ -2071,7 +2169,7 @@ void Arch::fix_pll_nets(Context *ctx)
                 ci->setParam(id_FBSEL, Property("UNKNOWN"));
                 continue;
             }
-            if (net_driven_by(ctx, net, is_PLL_T_FB_iob, id_O) != nullptr) {
+            if (net_driven_by(ctx, net, is_RPLL_T_FB_iob, id_O) != nullptr) {
                 ci->disconnectPort(id_CLKFB);
                 ci->setParam(id_FBSEL, Property("CLKFB2"));
                 break;
diff --git a/gowin/arch.h b/gowin/arch.h
index a5c339cc5b..0dd5a62b17 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -479,6 +479,7 @@ struct Arch : BaseArch<ArchRanges>
     void post_route(Context *ctx);
     void auto_longwires();
     void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col);
+    void add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col);
     void fix_pll_nets(Context *ctx);
     bool is_GCLKT_iob(const CellInfo *cell);
 
@@ -507,6 +508,9 @@ struct Arch : BaseArch<ArchRanges>
 
     // Permissible combinations of modes in a single slice
     std::map<const IdString, IdString> dff_comp_mode;
+
+    // max global clock wires
+    int max_clock;
 };
 
 // Bels Z range
@@ -521,7 +525,8 @@ enum
     osc_z = 280,      // Z for the oscillator bels
     bufs_0_z = 281,   // Z for long wire buffer bel
     pll_z = 289,      // PLL
-    free_z = 290      // Must be the last, one can use z starting from this value, adjust accordingly.
+    pllvr_z = 290,    // PLLVR
+    free_z = 291      // Must be the last, one can use z starting from this value, adjust accordingly.
 };
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index a76ea1d8ac..ae4201608e 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -96,6 +96,19 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_CLKOUTD);
         new_cell->addOutput(id_CLKOUTD3);
         new_cell->addOutput(id_LOCK);
+    } else if (type == id_PLLVR) {
+        for (IdString iid :
+             {id_CLKIN,   id_CLKFB,  id_FBDSEL0, id_FBDSEL1, id_FBDSEL2, id_FBDSEL3, id_FBDSEL4, id_FBDSEL5, id_IDSEL0,
+              id_IDSEL1,  id_IDSEL2, id_IDSEL3,  id_IDSEL4,  id_IDSEL5,  id_ODSEL0,  id_ODSEL1,  id_ODSEL2,  id_ODSEL3,
+              id_ODSEL4,  id_ODSEL5, id_PSDA0,   id_PSDA1,   id_PSDA2,   id_PSDA3,   id_DUTYDA0, id_DUTYDA1, id_DUTYDA2,
+              id_DUTYDA3, id_FDLY0,  id_FDLY1,   id_FDLY2,   id_FDLY3,   id_RESET,   id_RESET_P, id_VREN}) {
+            new_cell->addInput(iid);
+        }
+        new_cell->addOutput(id_CLKOUT);
+        new_cell->addOutput(id_CLKOUTP);
+        new_cell->addOutput(id_CLKOUTD);
+        new_cell->addOutput(id_CLKOUTD3);
+        new_cell->addOutput(id_LOCK);
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
@@ -223,6 +236,30 @@ void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb)
     pll->movePortTo(ctx->id("ODSEL[5]"), pllb, id_ODSEL5);
 }
 
+void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *new_pll)
+{
+    pll->movePortTo(id_CLKIN, new_pll, id_CLKIN);
+    pll->movePortTo(id_VREN, new_pll, id_VREN);
+    pll->movePortTo(id_CLKFB, new_pll, id_CLKFB);
+    pll->movePortTo(id_RESET, new_pll, id_RESET);
+    pll->movePortTo(id_RESET_P, new_pll, id_RESET_P);
+    for (int i = 0; i < 6; ++i) {
+        pll->movePortTo(ctx->idf("FBDSEL[%d]", i), new_pll, ctx->idf("FBDSEL%d", i));
+        pll->movePortTo(ctx->idf("IDSEL[%d]", i), new_pll, ctx->idf("IDSEL%d", i));
+        pll->movePortTo(ctx->idf("ODSEL[%d]", i), new_pll, ctx->idf("ODSEL%d", i));
+        if (i < 4) {
+            pll->movePortTo(ctx->idf("PSDA[%d]", i), new_pll, ctx->idf("PSDA%d", i));
+            pll->movePortTo(ctx->idf("DUTYDA[%d]", i), new_pll, ctx->idf("DUTYDA%d", i));
+            pll->movePortTo(ctx->idf("FDLY[%d]", i), new_pll, ctx->idf("FDLY%d", i));
+        }
+    }
+    pll->movePortTo(id_CLKOUT, new_pll, id_CLKOUT);
+    pll->movePortTo(id_CLKOUTP, new_pll, id_CLKOUTP);
+    pll->movePortTo(id_CLKOUTD, new_pll, id_CLKOUTD);
+    pll->movePortTo(id_CLKOUTD3, new_pll, id_CLKOUTD3);
+    pll->movePortTo(id_LOCK, new_pll, id_LOCK);
+}
+
 void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
 {
     if (ramw->hierpath == IdString())
diff --git a/gowin/cells.h b/gowin/cells.h
index ae475b774f..78a746f32a 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -121,7 +121,8 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 // Convert a Gowin IO buffer to a IOB bel
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
 
-// Reconnect rPLL signals (B)
+// Reconnect PLL signals (B)
+void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *pllb);
 void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *pllb);
 void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb);
 
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 610755bb01..e3e451a192 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -313,6 +313,7 @@ X(COUT2)
 X(COUT3)
 X(COUT4)
 X(COUT5)
+X(VREN)
 
 // wires
 // SN
@@ -855,6 +856,7 @@ X(OSCF)
 X(rPLL)
 X(RPLLA)
 X(RPLLB)
+X(PLLVR)
 
 // primitive attributes
 X(INIT)
diff --git a/gowin/globals.cc b/gowin/globals.cc
index 785a011196..6ed8f77011 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -53,7 +53,7 @@ std::pair<WireId, BelId> GowinGlobalRouter::clock_src(Context *ctx, PortRef cons
         }
         return std::make_pair(WireId(), BelId());
     }
-    if (driver.cell->type == id_RPLLA) {
+    if (driver.cell->type == id_RPLLA || driver.cell->type == id_PLLVR) {
         if (driver.port == id_CLKOUT || driver.port == id_CLKOUTP || driver.port == id_CLKOUTD ||
             driver.port == id_CLKOUTD3) {
             wire = bel.pins[driver.port].wire;
@@ -294,7 +294,7 @@ void GowinGlobalRouter::mark_globals(Context *ctx)
     gather_clock_nets(ctx, clock_nets);
     // XXX we need to use the list of indexes of clocks from the database
     // use 6 clocks (XXX 3 for GW1NZ-1)
-    int max_clock = 3, cur_clock = -1;
+    int max_clock = ctx->max_clock, cur_clock = -1;
     for (auto &net : clock_nets) {
         // XXX only IO clock for now
         if (net.clock_wire == WireId()) {
diff --git a/gowin/pack.cc b/gowin/pack.cc
index e1119dde94..e1372c4794 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -989,11 +989,37 @@ static bool is_pll(const Context *ctx, const CellInfo *cell)
     switch (cell->type.hash()) {
     case ID_rPLL:
         return true;
+    case ID_PLLVR:
+        return true;
     default:
         return false;
     }
 }
 
+static void pll_disable_unused_ports(Context *ctx, CellInfo *ci)
+{
+    // Unused ports will be disabled during image generation. Here we add flags for such ports.
+    Property pr_enable("ENABLE"), pr_disable("DISABLE");
+    IdString ports[][2] = {
+            {id_CLKOUTP, id_CLKOUTPS}, {id_CLKOUTD, id_CLKOUTDIV}, {id_CLKOUTD3, id_CLKOUTDIV3}, {id_LOCK, id_FLOCK}};
+    for (int i = 0; i < 4; ++i) {
+        ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable);
+    }
+    // resets
+    NetInfo *net = ci->getPort(id_RESET);
+    ci->setParam(id_RSTEN, pr_enable);
+    if (!port_used(ci, id_RESET) || net->name == ctx->id("$PACKER_VCC_NET") ||
+        net->name == ctx->id("$PACKER_GND_NET")) {
+        ci->setParam(id_RSTEN, pr_disable);
+    }
+    ci->setParam(id_PWDEN, pr_enable);
+    net = ci->getPort(id_RESET_P);
+    if (!port_used(ci, id_RESET_P) || net->name == ctx->id("$PACKER_VCC_NET") ||
+        net->name == ctx->id("$PACKER_GND_NET")) {
+        ci->setParam(id_PWDEN, pr_disable);
+    }
+}
+
 // Pack PLLs
 static void pack_plls(Context *ctx)
 {
@@ -1010,36 +1036,14 @@ static void pack_plls(Context *ctx)
         if (is_pll(ctx, ci)) {
             std::string parm_device = str_or_default(ci->params, id_DEVICE, "GW1N-1");
             if (parm_device != ctx->device) {
-                log_error("Wrong PLL device:%s vs %s\n", parm_device.c_str(), ctx->device.c_str());
+                log_error("Wrong PLL device:%s instead of %s\n", parm_device.c_str(), ctx->device.c_str());
                 continue;
             }
 
             switch (ci->type.hash()) {
             case ID_rPLL: {
                 if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") {
-                    // Unused ports will be disabled during image generation. Here we add flags for such ports.
-                    Property pr_enable("ENABLE"), pr_disable("DISABLE");
-                    IdString ports[][2] = {{id_CLKOUTP, id_CLKOUTPS},
-                                           {id_CLKOUTD, id_CLKOUTDIV},
-                                           {id_CLKOUTD3, id_CLKOUTDIV3},
-                                           {id_LOCK, id_FLOCK}};
-                    for (int i = 0; i < 4; ++i) {
-                        ci->setParam(ports[i][1], port_used(ci, ports[i][0]) ? pr_enable : pr_disable);
-                    }
-                    // resets
-                    NetInfo *net = ci->getPort(id_RESET);
-                    ci->setParam(id_RSTEN, pr_enable);
-                    if (!port_used(ci, id_RESET) || net->name == ctx->id("$PACKER_VCC_NET") ||
-                        net->name == ctx->id("$PACKER_GND_NET")) {
-                        ci->setParam(id_RSTEN, pr_disable);
-                    }
-                    ci->setParam(id_PWDEN, pr_enable);
-                    net = ci->getPort(id_RESET_P);
-                    if (!port_used(ci, id_RESET_P) || net->name == ctx->id("$PACKER_VCC_NET") ||
-                        net->name == ctx->id("$PACKER_GND_NET")) {
-                        ci->setParam(id_PWDEN, pr_disable);
-                    }
-
+                    pll_disable_unused_ports(ctx, ci);
                     // B half
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
                     reconnect_rpllb(ctx, ci, cell.get());
@@ -1061,6 +1065,23 @@ static void pack_plls(Context *ctx)
                     log_error("PLL isn't supported for %s\n", ctx->device.c_str());
                 }
             } break;
+            case ID_PLLVR: {
+                if (parm_device == "GW1NSR-4C") {
+                    pll_disable_unused_ports(ctx, ci);
+                    std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_PLLVR, ci->name.str(ctx) + "$pllvr");
+                    reconnect_pllvr(ctx, ci, cell.get());
+                    new_cells.push_back(std::move(cell));
+                    auto pll_cell = new_cells.back().get();
+
+                    // need params for gowin_pack
+                    for (auto &parm : ci->params) {
+                        pll_cell->setParam(parm.first, parm.second);
+                    }
+                    packed_cells.insert(ci->name);
+                } else {
+                    log_error("PLL isn't supported for %s\n", ctx->device.c_str());
+                }
+            } break;
             default:
                 break;
             }

From 60793266334639144a9a5f8b7b0855c811ccd087 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 18 Jan 2023 16:28:33 +0100
Subject: [PATCH 245/712] context: Add getNetinfoRouteDelayQuad

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/context.cc | 47 ++++++++++++++++++++++++++++++++++++++++
 common/kernel/context.h  |  1 +
 common/kernel/sdf.cc     |  2 +-
 3 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index 014394a60d..821ad822c4 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -157,6 +157,53 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
     return max_delay;
 }
 
+DelayQuad Context::getNetinfoRouteDelayQuad(const NetInfo *net_info, const PortRef &user_info) const
+{
+#ifdef ARCH_ECP5
+    if (net_info->is_global)
+        return DelayQuad(0);
+#endif
+
+    if (net_info->wires.empty())
+        return DelayQuad(predictArcDelay(net_info, user_info));
+
+    WireId src_wire = getNetinfoSourceWire(net_info);
+    if (src_wire == WireId())
+        return DelayQuad(0);
+
+    DelayQuad result(std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest());
+
+    for (auto dst_wire : getNetinfoSinkWires(net_info, user_info)) {
+        WireId cursor = dst_wire;
+        DelayQuad delay{0};
+
+        while (cursor != WireId() && cursor != src_wire) {
+            auto it = net_info->wires.find(cursor);
+
+            if (it == net_info->wires.end())
+                break;
+
+            PipId pip = it->second.pip;
+            if (pip == PipId())
+                break;
+
+            delay = delay + getPipDelay(pip);
+            delay = delay + getWireDelay(cursor);
+            cursor = getPipSrcWire(pip);
+        }
+
+        if (cursor == src_wire)
+            delay = delay + getWireDelay(src_wire);
+        else
+            delay = DelayQuad(predictArcDelay(net_info, user_info)); // unrouted
+        result.rise.min_delay = std::min(result.rise.min_delay, delay.rise.min_delay);
+        result.rise.max_delay = std::max(result.rise.max_delay, delay.rise.max_delay);
+        result.fall.min_delay = std::min(result.fall.min_delay, delay.fall.min_delay);
+        result.fall.max_delay = std::max(result.fall.max_delay, delay.fall.max_delay);
+    }
+    return result;
+}
+
 static uint32_t xorshift32(uint32_t x)
 {
     x ^= x << 13;
diff --git a/common/kernel/context.h b/common/kernel/context.h
index 4a5667d039..b4e7920d29 100644
--- a/common/kernel/context.h
+++ b/common/kernel/context.h
@@ -58,6 +58,7 @@ struct Context : Arch, DeterministicRNG
     size_t getNetinfoSinkWireCount(const NetInfo *net_info, const PortRef &sink) const;
     WireId getNetinfoSinkWire(const NetInfo *net_info, const PortRef &sink, size_t phys_idx) const;
     delay_t getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &sink) const;
+    DelayQuad getNetinfoRouteDelayQuad(const NetInfo *net_info, const PortRef &sink) const;
 
     // provided by router1.cc
     bool checkRoutedDesign() const;
diff --git a/common/kernel/sdf.cc b/common/kernel/sdf.cc
index acff56eddb..eb547ff22a 100644
--- a/common/kernel/sdf.cc
+++ b/common/kernel/sdf.cc
@@ -324,7 +324,7 @@ void Context::writeSDF(std::ostream &out, bool cvc_mode) const
             ic.to.cell = usr.cell->name.str(this);
             ic.to.port = usr.port.str(this);
             // FIXME: min/max routing delay
-            ic.delay = convert_delay(DelayQuad(getNetinfoRouteDelay(ni, usr)));
+            ic.delay = convert_delay(getNetinfoRouteDelayQuad(ni, usr));
             wr.conn.push_back(ic);
         }
     }

From ba4d7b1e9a233d701eb0ab39d21596a56de75726 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 19 Jan 2023 06:31:55 +1000
Subject: [PATCH 246/712] gowin: to use the FB network detection function

The chip used in tangnano4k does not have such pins, but we call the
function anyway in the expectation of other chips.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index a924f0005f..f43cc00a70 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2169,11 +2169,17 @@ void Arch::fix_pll_nets(Context *ctx)
                 ci->setParam(id_FBSEL, Property("UNKNOWN"));
                 continue;
             }
+            // XXX Redesign for chips other than N-1 and NS-4
             if (net_driven_by(ctx, net, is_RPLL_T_FB_iob, id_O) != nullptr) {
                 ci->disconnectPort(id_CLKFB);
                 ci->setParam(id_FBSEL, Property("CLKFB2"));
                 break;
             }
+            if (net_driven_by(ctx, net, is_LPLL_T_FB_iob, id_O) != nullptr) {
+                ci->disconnectPort(id_CLKFB);
+                ci->setParam(id_FBSEL, Property("CLKFB2"));
+                break;
+            }
             // XXX do special bels (HCLK etc)
             // This is general routing through CLK2 pip
             ci->setParam(id_FBSEL, Property("CLKFB0"));

From cc45f5ec48ff90b9685ac0bc7cc9309188a582ff Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 19 Jan 2023 07:12:39 +1000
Subject: [PATCH 247/712] gowin: improve error message

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/pack.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index e1372c4794..1ebd53151e 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1036,7 +1036,8 @@ static void pack_plls(Context *ctx)
         if (is_pll(ctx, ci)) {
             std::string parm_device = str_or_default(ci->params, id_DEVICE, "GW1N-1");
             if (parm_device != ctx->device) {
-                log_error("Wrong PLL device:%s instead of %s\n", parm_device.c_str(), ctx->device.c_str());
+                log_error("Cell '%s': wrong PLL device:%s instead of %s\n", ctx->nameOf(ci), parm_device.c_str(),
+                          ctx->device.c_str());
                 continue;
             }
 

From 7845b665125074d6cc9d7b71d1d69f8c261c1d50 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 20 Jan 2023 09:04:41 +0100
Subject: [PATCH 248/712] Add missing <set> includes

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/command.cc | 2 ++
 common/route/router2.cc  | 1 +
 ecp5/arch.h              | 5 ++---
 ecp5/config.cc           | 2 ++
 fpga_interchange/arch.cc | 1 +
 machxo2/arch.h           | 1 +
 machxo2/config.cc        | 2 ++
 nexus/fasm.cc            | 1 +
 nexus/pack.cc            | 1 +
 9 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index bf78514847..842d8a71b3 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -34,6 +34,8 @@
 #include <fstream>
 #include <iostream>
 #include <random>
+#include <set>
+
 #include "command.h"
 #include "design_utils.h"
 #include "json_frontend.h"
diff --git a/common/route/router2.cc b/common/route/router2.cc
index cdd98b6ea5..bb545003b8 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -34,6 +34,7 @@
 #include <deque>
 #include <fstream>
 #include <queue>
+#include <set>
 
 #include "log.h"
 #include "nextpnr.h"
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 40b931d612..56ba3e7b51 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -1087,10 +1087,9 @@ struct Arch : BaseArch<ArchRanges>
     mutable std::vector<TileStatus> tile_status;
 
     // -------------------------------------------------
-    bool is_dsp_location_valid(CellInfo* cell) const;
+    bool is_dsp_location_valid(CellInfo *cell) const;
     void remap_dsp_blocks();
-    void remap_dsp_cell(CellInfo* ci, const std::array<IdString, 4> &ports,
-                        std::array<NetInfo*, 4> &assigned_nets);
+    void remap_dsp_cell(CellInfo *ci, const std::array<IdString, 4> &ports, std::array<NetInfo *, 4> &assigned_nets);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/config.cc b/ecp5/config.cc
index e44326be42..ea9ece0dc3 100644
--- a/ecp5/config.cc
+++ b/ecp5/config.cc
@@ -20,7 +20,9 @@
 #include "config.h"
 #include <boost/range/adaptor/reversed.hpp>
 #include <iomanip>
+#include <set>
 #include "log.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 #define fmt(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index d20fe253f5..a1651c8106 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -28,6 +28,7 @@
 #include <cmath>
 #include <cstring>
 #include <queue>
+#include <set>
 
 #include "constraints.impl.h"
 #include "fpga_interchange.h"
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 489a44ab1d..214d8bb230 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -22,6 +22,7 @@
 #define MACHXO2_ARCH_H
 
 #include <cstdint>
+#include <set>
 
 #include "base_arch.h"
 #include "nextpnr_namespaces.h"
diff --git a/machxo2/config.cc b/machxo2/config.cc
index 0c5b074152..34c4954e8c 100644
--- a/machxo2/config.cc
+++ b/machxo2/config.cc
@@ -21,7 +21,9 @@
 #include "config.h"
 #include <boost/range/adaptor/reversed.hpp>
 #include <iomanip>
+#include <set>
 #include "log.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 #define fmt(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 81208c0f20..a725e7b11d 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -24,6 +24,7 @@
 
 #include <boost/range/adaptor/reversed.hpp>
 #include <queue>
+#include <set>
 
 NEXTPNR_NAMESPACE_BEGIN
 namespace {
diff --git a/nexus/pack.cc b/nexus/pack.cc
index cd042485cf..4b39542d81 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -25,6 +25,7 @@
 
 #include <boost/algorithm/string.hpp>
 #include <queue>
+#include <set>
 
 NEXTPNR_NAMESPACE_BEGIN
 

From 4c7e805f183ae74384737fb7caf7f7c13969bafb Mon Sep 17 00:00:00 2001
From: Dan Callaghan <dcallagh@google.com>
Date: Tue, 24 Jan 2023 13:11:50 +1100
Subject: [PATCH 249/712] use eigen as an IMPORTED target in CMake

Eigen considers the EIGEN3_INCLUDE_DIRS and EIGEN3_DEFINITIONS variables
to be deprecated and they will no longer be exported in the next release
after 3.4.0:
https://gitlab.com/libeigen/eigen/-/commit/f2984cd0778dd0a1d7e74216d826eaff2bc6bfab

Use the IMPORTED target instead, which seems to be the preferred way of
consuming third-party CMake libraries.
---
 CMakeLists.txt | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 269e90eb5e..4d15f7243d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -225,8 +225,7 @@ include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3
 
 if(BUILD_HEAP)
     find_package (Eigen3 REQUIRED NO_MODULE)
-    include_directories(${EIGEN3_INCLUDE_DIRS})
-    add_definitions(${EIGEN3_DEFINITIONS})
+    link_libraries(Eigen3::Eigen)
     add_definitions(-DWITH_HEAP)
 endif()
 

From c8cb0636562c276879ad617b6d35ec7e00b52fef Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 25 Jan 2023 09:26:12 +0100
Subject: [PATCH 250/712] ecp5: Improve IOFF CE handling robustness

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index f542934d0e..79d1688fc4 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -2230,13 +2230,21 @@ class Ecp5Packer
                         // Handle CLK and CE muxes
                         if (str_or_default(ci->params, id_CLKMUX) == "INV")
                             iol->params[id_CLKIMUX] = std::string("INV");
-                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE" ||
+                            str_or_default(ci->params, id_CEMUX, "CE") == "INV") {
                             iol->params[id_CEIMUX] = std::string("CEMUX");
-                            iol->params[id_CEMUX] = std::string("CE");
-                            if (ci->getPort(id_CE) == nullptr)
+                            if (iol->getPort(id_CE) == nullptr) {
+                                iol->params[id_CEMUX] = str_or_default(ci->params, id_CEMUX, "CE");
                                 ci->movePortTo(id_CE, iol, id_CE);
-                            else
+                            } else {
+                                if (iol->getPort(id_CE) != ci->getPort(id_CE) ||
+                                    str_or_default(ci->params, id_CEMUX, "CE") !=
+                                            str_or_default(iol->params, id_CEMUX, "CE"))
+                                    log_error("CE signal or polarity mismatch for IO flipflop %s with other IOFFs at "
+                                              "location.\n",
+                                              ctx->nameOf(ci));
                                 ci->disconnectPort(id_CE);
+                            }
                         } else {
                             iol->params[id_CEIMUX] = std::string("1");
                         }
@@ -2288,13 +2296,21 @@ class Ecp5Packer
                         // Handle CLK and CE muxes
                         if (str_or_default(ci->params, id_CLKMUX) == "INV")
                             iol->params[id_CLKOMUX] = std::string("INV");
-                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+                        if (str_or_default(ci->params, id_CEMUX, "CE") == "CE" ||
+                            str_or_default(ci->params, id_CEMUX, "CE") == "INV") {
                             iol->params[id_CEOMUX] = std::string("CEMUX");
-                            iol->params[id_CEMUX] = std::string("CE");
-                            if (ci->getPort(id_CE) == nullptr)
+                            if (iol->getPort(id_CE) == nullptr) {
+                                iol->params[id_CEMUX] = str_or_default(ci->params, id_CEMUX, "CE");
                                 ci->movePortTo(id_CE, iol, id_CE);
-                            else
+                            } else {
+                                if (iol->getPort(id_CE) != ci->getPort(id_CE) ||
+                                    str_or_default(ci->params, id_CEMUX, "CE") !=
+                                            str_or_default(iol->params, id_CEMUX, "CE"))
+                                    log_error("CE signal or polarity mismatch for IO flipflop %s with other IOFFs at "
+                                              "location.\n",
+                                              ctx->nameOf(ci));
                                 ci->disconnectPort(id_CE);
+                            }
                         } else {
                             iol->params[id_CEOMUX] = std::string("1");
                         }

From 9b5e5f124c186942652e6be03c356cf0edf88124 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 25 Jan 2023 10:29:32 +0100
Subject: [PATCH 251/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/exclusive_state_groups.h |   5 +-
 ecp5/arch_place.cc                     | 100 ++++++++++---------------
 fpga_interchange/arch.cc               |   6 +-
 fpga_interchange/luts.cc               |   2 +-
 fpga_interchange/pseudo_pip_model.cc   |   2 +-
 5 files changed, 47 insertions(+), 68 deletions(-)

diff --git a/common/kernel/exclusive_state_groups.h b/common/kernel/exclusive_state_groups.h
index 68ce7c4eb6..7d447ffe1d 100644
--- a/common/kernel/exclusive_state_groups.h
+++ b/common/kernel/exclusive_state_groups.h
@@ -125,7 +125,10 @@ template <size_t StateCount, typename StateType = int8_t, typename CountType = u
         }
     }
 
-    template <typename StateRange> bool requires(const StateRange &state_range) const
+    template <typename StateRange>
+    bool
+        requires(const StateRange &state_range)
+    const
     {
         if (state < 0) {
             return false;
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 2bb601c251..e89e8fb4cc 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -200,26 +200,24 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 
 // Check if this DSP cell placement would result in more than four distinct
 // CLK/CE/RST signals per block of two DSP slices.
-bool Arch::is_dsp_location_valid(CellInfo* cell) const
+bool Arch::is_dsp_location_valid(CellInfo *cell) const
 {
     // Find the location of the DSP0 tile.
     int block_x = cell->getLocation().x - cell->getLocation().z;
     int block_y = cell->getLocation().y;
 
-    const std::array<std::array<IdString, 4>, 3> block_ports = {{
-        {id_CLK0, id_CLK1, id_CLK2, id_CLK3},
-        {id_CE0, id_CE1, id_CE2, id_CE3},
-        {id_RST0, id_RST1, id_RST2, id_RST3}
-    }};
-    const std::array<const char*, 3> port_names = {"CLK", "CE", "RST"};
-    std::array<std::set<NetInfo*>, 3> block_nets = {};
+    const std::array<std::array<IdString, 4>, 3> block_ports = {{{id_CLK0, id_CLK1, id_CLK2, id_CLK3},
+                                                                 {id_CE0, id_CE1, id_CE2, id_CE3},
+                                                                 {id_RST0, id_RST1, id_RST2, id_RST3}}};
+    const std::array<const char *, 3> port_names = {"CLK", "CE", "RST"};
+    std::array<std::set<NetInfo *>, 3> block_nets = {};
     bool cells_locked = true;
 
     // Count the number of distinct CLK, CE, and RST signals used by
     // all the MULT18X18D and ALU54B bels in the DSP block.
     for (int dx : {0, 1, 3, 4, 5, 7}) {
         BelId dsp_bel = getBelByLocation(Loc(block_x + dx, block_y, dx));
-        CellInfo* dsp_cell = getBoundBelCell(dsp_bel);
+        CellInfo *dsp_cell = getBoundBelCell(dsp_bel);
         if (dsp_cell == nullptr)
             continue;
 
@@ -240,9 +238,7 @@ bool Arch::is_dsp_location_valid(CellInfo* cell) const
                     if (cells_locked) {
                         log_error("DSP block containing %s '%s' has more than "
                                   "four distinct %s signals.\n",
-                                  dsp_cell->type.c_str(getCtx()),
-                                  dsp_cell->name.c_str(getCtx()),
-                                  port_names[i]);
+                                  dsp_cell->type.c_str(getCtx()), dsp_cell->name.c_str(getCtx()), port_names[i]);
                     }
                     return false;
                 }
@@ -260,12 +256,12 @@ void Arch::remap_dsp_blocks()
     std::set<Location> processed_blocks;
 
     const std::array<std::array<IdString, 4>, 3> block_ports = {{
-        {id_CLK0, id_CLK1, id_CLK2, id_CLK3},
-        {id_CE0, id_CE1, id_CE2, id_CE3},
-        {id_RST0, id_RST1, id_RST2, id_RST3},
+            {id_CLK0, id_CLK1, id_CLK2, id_CLK3},
+            {id_CE0, id_CE1, id_CE2, id_CE3},
+            {id_RST0, id_RST1, id_RST2, id_RST3},
     }};
 
-    for (auto &cell: cells) {
+    for (auto &cell : cells) {
         CellInfo *ci = cell.second.get();
         if (!ci->type.in(id_MULT18X18D, id_ALU54B))
             continue;
@@ -279,13 +275,13 @@ void Arch::remap_dsp_blocks()
 
         for (auto &ports : block_ports) {
             // Store assigned nets for each port.
-            std::array<NetInfo*, 4> assigned_nets = {};
+            std::array<NetInfo *, 4> assigned_nets = {};
 
             // Process each possible MULT18X18D or ALU54B in this block.
             for (int dx : {0, 1, 3, 4, 5, 7}) {
                 Loc dsp_loc = Loc(block_loc.x + dx, block_loc.y, dx);
                 BelId dsp_bel = getBelByLocation(dsp_loc);
-                CellInfo* dsp_cell = getBoundBelCell(dsp_bel);
+                CellInfo *dsp_cell = getBoundBelCell(dsp_bel);
                 if (dsp_cell == nullptr)
                     continue;
                 remap_dsp_cell(dsp_cell, ports, assigned_nets);
@@ -314,34 +310,25 @@ void Arch::remap_dsp_blocks()
 // ports: array of port names to remap, either CLK0-3 or CE0-3 or RST0-3
 // assigned_nets: array of final net assignments to those four ports for
 //                the block this cell is in.
-void Arch::remap_dsp_cell(
-    CellInfo* ci,
-    const std::array<IdString, 4> &ports,
-    std::array<NetInfo*, 4> &assigned_nets
-) {
+void Arch::remap_dsp_cell(CellInfo *ci, const std::array<IdString, 4> &ports, std::array<NetInfo *, 4> &assigned_nets)
+{
     // New names to use in attributes that used to refer to an old port name.
     std::array<IdString, 4> remap_ports = {};
 
     // Parameters that might need updating when ports are remapped.
     const std::array<IdString, 48> remap_params = {
-        id_REG_INPUTA_CLK, id_REG_INPUTA_CE, id_REG_INPUTA_RST,
-        id_REG_INPUTB_CLK, id_REG_INPUTB_CE, id_REG_INPUTB_RST,
-        id_REG_INPUTC_CLK, id_REG_INPUTC_CE, id_REG_INPUTC_RST,
-        id_REG_PIPELINE_CLK, id_REG_PIPELINE_CE, id_REG_PIPELINE_RST,
-        id_REG_OUTPUT_CLK, id_REG_OUTPUT_CE, id_REG_OUTPUT_RST,
-        id_REG_INPUTC0_CLK, id_REG_INPUTC0_CE, id_REG_INPUTC0_RST,
-        id_REG_INPUTC1_CLK, id_REG_INPUTC1_CE, id_REG_INPUTC1_RST,
-        id_REG_OPCODEOP0_0_CLK, id_REG_OPCODEOP0_0_CE, id_REG_OPCODEOP0_0_RST,
-        id_REG_OPCODEOP1_0_CLK,
-        id_REG_OPCODEOP0_1_CLK, id_REG_OPCODEOP0_1_CE, id_REG_OPCODEOP0_1_RST,
-        id_REG_OPCODEOP1_1_CLK,
-        id_REG_OPCODEIN_0_CLK, id_REG_OPCODEIN_0_CE, id_REG_OPCODEIN_0_RST,
-        id_REG_OPCODEIN_1_CLK, id_REG_OPCODEIN_1_CE, id_REG_OPCODEIN_1_RST,
-        id_REG_OUTPUT0_CLK, id_REG_OUTPUT0_CE, id_REG_OUTPUT0_RST,
-        id_REG_OUTPUT1_CLK, id_REG_OUTPUT1_CE, id_REG_OUTPUT1_RST,
-        id_REG_FLAG_CLK, id_REG_FLAG_CE, id_REG_FLAG_RST,
-        id_REG_INPUTCFB_CLK, id_REG_INPUTCFB_CE, id_REG_INPUTCFB_RST,
-        id_HIGHSPEED_CLK,
+            id_REG_INPUTA_CLK,      id_REG_INPUTA_CE,       id_REG_INPUTA_RST,     id_REG_INPUTB_CLK,
+            id_REG_INPUTB_CE,       id_REG_INPUTB_RST,      id_REG_INPUTC_CLK,     id_REG_INPUTC_CE,
+            id_REG_INPUTC_RST,      id_REG_PIPELINE_CLK,    id_REG_PIPELINE_CE,    id_REG_PIPELINE_RST,
+            id_REG_OUTPUT_CLK,      id_REG_OUTPUT_CE,       id_REG_OUTPUT_RST,     id_REG_INPUTC0_CLK,
+            id_REG_INPUTC0_CE,      id_REG_INPUTC0_RST,     id_REG_INPUTC1_CLK,    id_REG_INPUTC1_CE,
+            id_REG_INPUTC1_RST,     id_REG_OPCODEOP0_0_CLK, id_REG_OPCODEOP0_0_CE, id_REG_OPCODEOP0_0_RST,
+            id_REG_OPCODEOP1_0_CLK, id_REG_OPCODEOP0_1_CLK, id_REG_OPCODEOP0_1_CE, id_REG_OPCODEOP0_1_RST,
+            id_REG_OPCODEOP1_1_CLK, id_REG_OPCODEIN_0_CLK,  id_REG_OPCODEIN_0_CE,  id_REG_OPCODEIN_0_RST,
+            id_REG_OPCODEIN_1_CLK,  id_REG_OPCODEIN_1_CE,   id_REG_OPCODEIN_1_RST, id_REG_OUTPUT0_CLK,
+            id_REG_OUTPUT0_CE,      id_REG_OUTPUT0_RST,     id_REG_OUTPUT1_CLK,    id_REG_OUTPUT1_CE,
+            id_REG_OUTPUT1_RST,     id_REG_FLAG_CLK,        id_REG_FLAG_CE,        id_REG_FLAG_RST,
+            id_REG_INPUTCFB_CLK,    id_REG_INPUTCFB_CE,     id_REG_INPUTCFB_RST,   id_HIGHSPEED_CLK,
     };
 
     // First, go through each port and determine which new port to assign
@@ -363,22 +350,18 @@ void Arch::remap_dsp_cell(
                 // we need to assign the net to a different port and
                 // update any attributes that refer to it, while
                 // ensuring the net at the new port is preserved.
-                size_t j = std::distance(
-                    assigned_nets.cbegin(),
-                    std::find(assigned_nets.cbegin(), assigned_nets.cend(), nullptr));
+                size_t j = std::distance(assigned_nets.cbegin(),
+                                         std::find(assigned_nets.cbegin(), assigned_nets.cend(), nullptr));
                 if (j == assigned_nets.size()) {
                     log_error("DSP block containing %s '%s': no unused ports "
                               "to remap %s to; too many distinct signals in "
                               "block.\n",
-                              ci->type.c_str(getCtx()),
-                              ci->name.c_str(getCtx()),
-                              port.c_str(getCtx()));
+                              ci->type.c_str(getCtx()), ci->name.c_str(getCtx()), port.c_str(getCtx()));
                 }
                 assigned_nets[j] = net;
                 remap_ports[i] = ports[j];
-                log_info("DSP: %s '%s': Connection to %s remapped to %s\n",
-                         ci->type.c_str(getCtx()), ci->name.c_str(getCtx()),
-                         ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
+                log_info("DSP: %s '%s': Connection to %s remapped to %s\n", ci->type.c_str(getCtx()),
+                         ci->name.c_str(getCtx()), ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
             }
         } else if (*assigned != assigned_nets[i]) {
             // If the net has been assigned already and to a different
@@ -386,9 +369,8 @@ void Arch::remap_dsp_cell(
             // to point to the already-assigned port.
             size_t j = std::distance(assigned_nets.cbegin(), assigned);
             remap_ports[i] = ports[j];
-            log_info("DSP: %s '%s': Connection to %s remapped to %s\n",
-                     ci->type.c_str(getCtx()), ci->name.c_str(getCtx()),
-                     ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
+            log_info("DSP: %s '%s': Connection to %s remapped to %s\n", ci->type.c_str(getCtx()),
+                     ci->name.c_str(getCtx()), ports[i].c_str(getCtx()), ports[j].c_str(getCtx()));
         }
     }
 
@@ -409,10 +391,7 @@ void Arch::remap_dsp_cell(
             continue;
         for (size_t i = 0; i < remap_ports.size(); i++) {
             Property &prop = param->second;
-            if (remap_ports[i] != IdString()
-                && prop.is_string
-                && prop.str == ports[i].str(getCtx())
-            ) {
+            if (remap_ports[i] != IdString() && prop.is_string && prop.str == ports[i].str(getCtx())) {
                 prop = Property(remap_ports[i].str(getCtx()));
                 break;
             }
@@ -421,8 +400,7 @@ void Arch::remap_dsp_cell(
 
     // Finally, only when remapping CLK ports, also move any `CLKn_DIV`
     // to the new clock port.
-    const std::array<IdString, 4> clk_div_params = {
-        id_CLK0_DIV, id_CLK1_DIV, id_CLK2_DIV, id_CLK3_DIV};
+    const std::array<IdString, 4> clk_div_params = {id_CLK0_DIV, id_CLK1_DIV, id_CLK2_DIV, id_CLK3_DIV};
     std::array<Property, 4> new_clk_div_props = {};
     if (ports[0] == id_CLK0) {
         for (size_t i = 0; i < 4; i++) {
@@ -431,9 +409,7 @@ void Arch::remap_dsp_cell(
             auto param = ci->params.find(clk_div_params[i]);
             if (param == ci->params.end())
                 continue;
-            size_t j = std::distance(
-                ports.cbegin(),
-                std::find(ports.cbegin(), ports.cend(), remap_ports[i]));
+            size_t j = std::distance(ports.cbegin(), std::find(ports.cbegin(), ports.cend(), remap_ports[i]));
             if (j != ports.size()) {
                 new_clk_div_props[j] = param->second;
             }
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index a1651c8106..2682010ffc 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -46,9 +46,9 @@
 // scope of the header.
 #include <tcl.h>
 
-//#define DEBUG_BINDING
-//#define USE_LOOKAHEAD
-//#define DEBUG_CELL_PIN_MAPPING
+// #define DEBUG_BINDING
+// #define USE_LOOKAHEAD
+// #define DEBUG_CELL_PIN_MAPPING
 
 // Define to enable some idempotent sanity checks for some important
 // operations prior to placement and routing.
diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
index 2a84725316..009b601e72 100644
--- a/fpga_interchange/luts.cc
+++ b/fpga_interchange/luts.cc
@@ -24,7 +24,7 @@
 
 #include "site_lut_mapping_cache.h"
 
-//#define DEBUG_LUT_ROTATION
+// #define DEBUG_LUT_ROTATION
 
 NEXTPNR_NAMESPACE_BEGIN
 
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc
index 7f2427c4f4..0b76736922 100644
--- a/fpga_interchange/pseudo_pip_model.cc
+++ b/fpga_interchange/pseudo_pip_model.cc
@@ -22,7 +22,7 @@
 
 #include "context.h"
 
-//#define DEBUG_PSEUDO_PIP
+// #define DEBUG_PSEUDO_PIP
 
 NEXTPNR_NAMESPACE_BEGIN
 

From 2d45d57b3246814ad20988c6ecf941180faf58a6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 26 Jan 2023 20:26:05 +1000
Subject: [PATCH 252/712] gowin: Add PLL support for the GW1NR-9C chip

This chip is used in the Tangnano9k board.

  * all parameters of the rPLL primitive are supported;
  * all PLL outputs are treated as clock sources and optimized routing
    is applied to them;
  * primitive rPLL on different chips has a completely different
    structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
    as many as four, despite this unification was carried out and
    different chips are processed by the same functions, but this led to
    the fact that you can not use the PLL chip GW1N-1 with the old
    apicula bases - will issue a warning and refuse to encode primitive.
    In other cases compatibility is supported.
  * Cosmetic change: the usage report shows the rPLL names without any
    service bels.
  * I use ctx->idf() on occasion, it's not a total redesign.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 98 +++++++++++++++++++++++++++++-----------------
 gowin/arch.h       |  2 +-
 gowin/cells.cc     | 57 +++++++++++----------------
 gowin/cells.h      |  5 +--
 gowin/constids.inc |  1 -
 gowin/globals.cc   | 42 +++++++++++++-------
 gowin/pack.cc      | 24 +++++-------
 7 files changed, 125 insertions(+), 104 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index f43cc00a70..88b9f42f55 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1098,16 +1098,33 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
     }
 }
 
-void Arch::add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col)
+void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col)
 {
     IdString portname;
 
-    for (int pid : {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5,
-                    ID_IDSEL0,  ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,
-                    ID_ODSEL2,  ID_ODSEL3,  ID_ODSEL4,  ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0,
-                    ID_DUTYDA1, ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3}) {
+    for (int pid :
+         {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5, ID_IDSEL0,
+          ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,  ID_ODSEL2,  ID_ODSEL3,
+          ID_ODSEL4,  ID_ODSEL5,  ID_VREN,    ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0, ID_DUTYDA1,
+          ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3,   ID_RESET,   ID_RESET_P}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
-        addBelInput(belname, IdString(pid), idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+        IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+        if (wires.count(wire) == 0) {
+            GlobalAliasPOD alias;
+            alias.dest_col = col;
+            alias.dest_row = row;
+            alias.dest_id = portname.hash();
+            auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+            NPNR_ASSERT(alias_src != nullptr);
+            int srcrow = alias_src->src_row;
+            int srccol = alias_src->src_col;
+            IdString srcid = IdString(alias_src->src_id);
+            wire = wireToGlobal(srcrow, srccol, db, srcid);
+            if (wires.count(wire) == 0) {
+                addWire(wire, srcid, srccol, srcrow);
+            }
+        }
+        addBelInput(belname, IdString(pid), wire);
     }
     for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
@@ -1115,16 +1132,23 @@ void Arch::add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col
     }
 }
 
-void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col)
+void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col)
 {
     IdString portname;
 
     for (int pid :
-         {ID_CLKIN,   ID_CLKFB,   ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5, ID_IDSEL0,
-          ID_IDSEL1,  ID_IDSEL2,  ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,  ID_ODSEL2,  ID_ODSEL3,
-          ID_ODSEL4,  ID_ODSEL5,  ID_VREN,    ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0, ID_DUTYDA1,
-          ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3,   ID_RESET,   ID_RESET_P}) {
-        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
+         {ID_CLKIN,   ID_CLKFB,  ID_FBDSEL0, ID_FBDSEL1, ID_FBDSEL2, ID_FBDSEL3, ID_FBDSEL4, ID_FBDSEL5, ID_IDSEL0,
+          ID_IDSEL1,  ID_IDSEL2, ID_IDSEL3,  ID_IDSEL4,  ID_IDSEL5,  ID_ODSEL0,  ID_ODSEL1,  ID_ODSEL2,  ID_ODSEL3,
+          ID_ODSEL4,  ID_ODSEL5, ID_PSDA0,   ID_PSDA1,   ID_PSDA2,   ID_PSDA3,   ID_DUTYDA0, ID_DUTYDA1, ID_DUTYDA2,
+          ID_DUTYDA3, ID_FDLY0,  ID_FDLY1,   ID_FDLY2,   ID_FDLY3,   ID_RESET,   ID_RESET_P}) {
+        const PairPOD *port = pairLookup(bel->ports.get(), bel->num_ports, pid);
+        // old base
+        if (port == nullptr) {
+            log_warning("When building nextpnr, obsolete old apicula bases were used. Probably not working properly "
+                        "with PLL.\n");
+            return;
+        }
+        portname = IdString(port->src_id);
         IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
         if (wires.count(wire) == 0) {
             GlobalAliasPOD alias;
@@ -1137,20 +1161,39 @@ void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString b
             int srccol = alias_src->src_col;
             IdString srcid = IdString(alias_src->src_id);
             wire = wireToGlobal(srcrow, srccol, db, srcid);
-            // addWire(wire, portname, srccol, srcrow);
+            if (wires.count(wire) == 0) {
+                addWire(wire, srcid, srccol, srcrow);
+            }
         }
         addBelInput(belname, IdString(pid), wire);
     }
     for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
-        addBelOutput(belname, IdString(pid), idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+        IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+        if (wires.count(wire) == 0) {
+            GlobalAliasPOD alias;
+            alias.dest_col = col;
+            alias.dest_row = row;
+            alias.dest_id = portname.hash();
+            auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+            NPNR_ASSERT(alias_src != nullptr);
+            int srcrow = alias_src->src_row;
+            int srccol = alias_src->src_col;
+            IdString srcid = IdString(alias_src->src_id);
+            wire = wireToGlobal(srcrow, srccol, db, srcid);
+            if (wires.count(wire) == 0) {
+                addWire(wire, srcid, srccol, srcrow);
+            }
+        }
+        addBelOutput(belname, IdString(pid), wire);
     }
 }
+
 Arch::Arch(ArchArgs args) : args(args)
 {
     family = args.family;
 
-    max_clock = 5;
+    max_clock = 6;
     if (family == "GW1NZ-1") {
         max_clock = 3;
     }
@@ -1312,24 +1355,9 @@ Arch::Arch(ArchArgs args) : args(args)
                 add_pllvr_ports(db, bel, belname, row, col);
                 break;
             case ID_RPLLA:
-                snprintf(buf, 32, "R%dC%d_RPLLA", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_RPLLA, Loc(col, row, BelZ::pll_z), false);
-                add_plla_ports(bel, belname, row, col);
-                break;
-            case ID_RPLLB:
-                snprintf(buf, 32, "R%dC%d_RPLLB", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_RPLLB, Loc(col, row, BelZ::pll_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_RESET, id(buf));
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET_P)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_RESET_P, id(buf));
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_ODSEL5)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_ODSEL5, id(buf));
+                belname = idf("R%dC%d_rPLL", row + 1, col + 1);
+                addBel(belname, id_rPLL, Loc(col, row, BelZ::pll_z), false);
+                add_rpll_ports(db, bel, belname, row, col);
                 break;
             case ID_BUFS7:
                 z++; /* fall-through*/
@@ -2086,7 +2114,7 @@ void Arch::fix_pll_nets(Context *ctx)
 {
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
-        if (ci->type != id_RPLLA && ci->type != id_PLLVR) {
+        if (ci->type != id_rPLL && ci->type != id_PLLVR) {
             continue;
         }
         // *** CLKIN
@@ -2101,7 +2129,7 @@ void Arch::fix_pll_nets(Context *ctx)
                 break;
             }
             if (net_driven_by(ctx, net, is_RPLL_T_IN_iob, id_O) != nullptr) {
-                if (ci->type == id_RPLLA) {
+                if (ci->type == id_rPLL) {
                     ci->disconnectPort(id_CLKIN);
                     ci->setParam(id_INSEL, Property("CLKIN0"));
                     break;
diff --git a/gowin/arch.h b/gowin/arch.h
index 0dd5a62b17..f060165aea 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -478,8 +478,8 @@ struct Arch : BaseArch<ArchRanges>
     void pre_route(Context *ctx);
     void post_route(Context *ctx);
     void auto_longwires();
-    void add_plla_ports(BelsPOD const *bel, IdString belname, int row, int col);
     void add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col);
+    void add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col);
     void fix_pll_nets(Context *ctx);
     bool is_GCLKT_iob(const CellInfo *cell);
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index ae4201608e..c30a470630 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -79,16 +79,12 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
     } else if (type == id_BUFS) {
         new_cell->addInput(id_I);
         new_cell->addOutput(id_O);
-    } else if (type == id_RPLLB) {
-        new_cell->addInput(id_RESET);
-        new_cell->addInput(id_RESET_P);
-        new_cell->addInput(id_ODSEL5);
-    } else if (type == id_RPLLA) {
+    } else if (type == id_rPLL) {
         for (IdString iid :
-             {id_CLKIN,   id_CLKFB,   id_FBDSEL0, id_FBDSEL1, id_FBDSEL2, id_FBDSEL3, id_FBDSEL4, id_FBDSEL5,
-              id_IDSEL0,  id_IDSEL1,  id_IDSEL2,  id_IDSEL3,  id_IDSEL4,  id_IDSEL5,  id_ODSEL0,  id_ODSEL1,
-              id_ODSEL2,  id_ODSEL3,  id_ODSEL4,  id_PSDA0,   id_PSDA1,   id_PSDA2,   id_PSDA3,   id_DUTYDA0,
-              id_DUTYDA1, id_DUTYDA2, id_DUTYDA3, id_FDLY0,   id_FDLY1,   id_FDLY2,   id_FDLY3}) {
+             {id_CLKIN,   id_CLKFB,  id_FBDSEL0, id_FBDSEL1, id_FBDSEL2, id_FBDSEL3, id_FBDSEL4, id_FBDSEL5, id_IDSEL0,
+              id_IDSEL1,  id_IDSEL2, id_IDSEL3,  id_IDSEL4,  id_IDSEL5,  id_ODSEL0,  id_ODSEL1,  id_ODSEL2,  id_ODSEL3,
+              id_ODSEL4,  id_ODSEL5, id_PSDA0,   id_PSDA1,   id_PSDA2,   id_PSDA3,   id_DUTYDA0, id_DUTYDA1, id_DUTYDA2,
+              id_DUTYDA3, id_FDLY0,  id_FDLY1,   id_FDLY2,   id_FDLY3,   id_RESET,   id_RESET_P}) {
             new_cell->addInput(iid);
         }
         new_cell->addOutput(id_CLKOUT);
@@ -206,40 +202,33 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
     }
 }
 
-void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *plla)
+void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *new_pll)
 {
-    pll->movePortTo(id_CLKIN, plla, id_CLKIN);
-    pll->movePortTo(id_CLKFB, plla, id_CLKFB);
+    pll->movePortTo(id_CLKIN, new_pll, id_CLKIN);
+    pll->movePortTo(id_VREN, new_pll, id_VREN);
+    pll->movePortTo(id_CLKFB, new_pll, id_CLKFB);
+    pll->movePortTo(id_RESET, new_pll, id_RESET);
+    pll->movePortTo(id_RESET_P, new_pll, id_RESET_P);
     for (int i = 0; i < 6; ++i) {
-        pll->movePortTo(ctx->idf("FBDSEL[%d]", i), plla, ctx->idf("FBDSEL%d", i));
-        pll->movePortTo(ctx->idf("IDSEL[%d]", i), plla, ctx->idf("IDSEL%d", i));
-        if (i < 5) {
-            pll->movePortTo(ctx->idf("ODSEL[%d]", i), plla, ctx->idf("ODSEL%d", i));
-        }
+        pll->movePortTo(ctx->idf("FBDSEL[%d]", i), new_pll, ctx->idf("FBDSEL%d", i));
+        pll->movePortTo(ctx->idf("IDSEL[%d]", i), new_pll, ctx->idf("IDSEL%d", i));
+        pll->movePortTo(ctx->idf("ODSEL[%d]", i), new_pll, ctx->idf("ODSEL%d", i));
         if (i < 4) {
-            pll->movePortTo(ctx->idf("PSDA[%d]", i), plla, ctx->idf("PSDA%d", i));
-            pll->movePortTo(ctx->idf("DUTYDA[%d]", i), plla, ctx->idf("DUTYDA%d", i));
-            pll->movePortTo(ctx->idf("FDLY[%d]", i), plla, ctx->idf("FDLY%d", i));
+            pll->movePortTo(ctx->idf("PSDA[%d]", i), new_pll, ctx->idf("PSDA%d", i));
+            pll->movePortTo(ctx->idf("DUTYDA[%d]", i), new_pll, ctx->idf("DUTYDA%d", i));
+            pll->movePortTo(ctx->idf("FDLY[%d]", i), new_pll, ctx->idf("FDLY%d", i));
         }
     }
-    pll->movePortTo(id_CLKOUT, plla, id_CLKOUT);
-    pll->movePortTo(id_CLKOUTP, plla, id_CLKOUTP);
-    pll->movePortTo(id_CLKOUTD, plla, id_CLKOUTD);
-    pll->movePortTo(id_CLKOUTD3, plla, id_CLKOUTD3);
-    pll->movePortTo(id_LOCK, plla, id_LOCK);
-}
-
-void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb)
-{
-    pll->movePortTo(id_RESET, pllb, id_RESET);
-    pll->movePortTo(id_RESET_P, pllb, id_RESET_P);
-    pll->movePortTo(ctx->id("ODSEL[5]"), pllb, id_ODSEL5);
+    pll->movePortTo(id_CLKOUT, new_pll, id_CLKOUT);
+    pll->movePortTo(id_CLKOUTP, new_pll, id_CLKOUTP);
+    pll->movePortTo(id_CLKOUTD, new_pll, id_CLKOUTD);
+    pll->movePortTo(id_CLKOUTD3, new_pll, id_CLKOUTD3);
+    pll->movePortTo(id_LOCK, new_pll, id_LOCK);
 }
 
-void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *new_pll)
+void reconnect_rpll(Context *ctx, CellInfo *pll, CellInfo *new_pll)
 {
     pll->movePortTo(id_CLKIN, new_pll, id_CLKIN);
-    pll->movePortTo(id_VREN, new_pll, id_VREN);
     pll->movePortTo(id_CLKFB, new_pll, id_CLKFB);
     pll->movePortTo(id_RESET, new_pll, id_RESET);
     pll->movePortTo(id_RESET_P, new_pll, id_RESET_P);
diff --git a/gowin/cells.h b/gowin/cells.h
index 78a746f32a..7aba480531 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -122,9 +122,8 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
 
 // Reconnect PLL signals (B)
-void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *pllb);
-void reconnect_rplla(Context *ctx, CellInfo *pll, CellInfo *pllb);
-void reconnect_rpllb(Context *ctx, CellInfo *pll, CellInfo *pllb);
+void reconnect_pllvr(Context *ctx, CellInfo *pll, CellInfo *new_pll);
+void reconnect_rpll(Context *ctx, CellInfo *pll, CellInfo *new_pll);
 
 // Convert RAM16 to write port
 void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
diff --git a/gowin/constids.inc b/gowin/constids.inc
index e3e451a192..dac84a1e08 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -855,7 +855,6 @@ X(OSCF)
 // PLLs
 X(rPLL)
 X(RPLLA)
-X(RPLLB)
 X(PLLVR)
 
 // primitive attributes
diff --git a/gowin/globals.cc b/gowin/globals.cc
index 6ed8f77011..3273191c10 100644
--- a/gowin/globals.cc
+++ b/gowin/globals.cc
@@ -53,7 +53,7 @@ std::pair<WireId, BelId> GowinGlobalRouter::clock_src(Context *ctx, PortRef cons
         }
         return std::make_pair(WireId(), BelId());
     }
-    if (driver.cell->type == id_RPLLA || driver.cell->type == id_PLLVR) {
+    if (driver.cell->type == id_rPLL || driver.cell->type == id_PLLVR) {
         if (driver.port == id_CLKOUT || driver.port == id_CLKOUTP || driver.port == id_CLKOUTD ||
             driver.port == id_CLKOUTD3) {
             wire = bel.pins[driver.port].wire;
@@ -103,12 +103,20 @@ void GowinGlobalRouter::gather_clock_nets(Context *ctx, std::vector<globalnet_t>
 IdString GowinGlobalRouter::route_to_non_clock_port(Context *ctx, WireId const dstWire, int clock,
                                                     pool<IdString> &used_pips, pool<IdString> &undo_wires)
 {
-    static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
-    char buf[40];
+    static std::vector<IdString> one_hop_0 = {id_W111, id_W121, id_E111, id_E121};
+    static std::vector<IdString> one_hop_4 = {id_S111, id_S121, id_N111, id_N121};
     // uphill pips
     for (auto const uphill : ctx->getPipsUphill(dstWire)) {
         WireId srcWire = ctx->getPipSrcWire(uphill);
-        if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) != one_hop.end()) {
+        bool found;
+        if (clock < 4) {
+            found = find(one_hop_0.begin(), one_hop_0.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
+                    one_hop_0.end();
+        } else {
+            found = find(one_hop_4.begin(), one_hop_4.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
+                    one_hop_4.end();
+        }
+        if (found) {
             // found one hop pip
             if (used_wires.count(srcWire)) {
                 if (used_wires[srcWire] != clock) {
@@ -117,8 +125,13 @@ IdString GowinGlobalRouter::route_to_non_clock_port(Context *ctx, WireId const d
             }
             WireInfo wi = ctx->wire_info(srcWire);
             std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
-            snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
-            IdString gb = ctx->id(buf);
+            IdString gb = ctx->idf("R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
+            if (ctx->verbose) {
+                log_info("    1-hop gb:%s\n", gb.c_str(ctx));
+            }
+            // sanity
+            NPNR_ASSERT(find(ctx->getPipsUphill(srcWire).begin(), ctx->getPipsUphill(srcWire).end(), gb) !=
+                        ctx->getPipsUphill(srcWire).end());
             auto up_pips = ctx->getPipsUphill(srcWire);
             if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
                 if (!used_wires.count(srcWire)) {
@@ -154,11 +167,10 @@ void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
 
         char buf[30];
         PipId gb_pip_id;
-        if (user.port == id_CLK) {
+        if (user.port == id_CLK || user.port == id_CLKIN) {
             WireInfo const wi = ctx->wire_info(dstWire);
-            snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, net.clock,
-                     ctx->wire_info(dstWire).type.c_str(ctx));
-            gb_pip_id = ctx->id(buf);
+            gb_pip_id =
+                    ctx->idf("R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, net.clock, ctx->wire_info(dstWire).type.c_str(ctx));
             // sanity
             NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
                         ctx->getPipsUphill(dstWire).end());
@@ -192,11 +204,10 @@ void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
         dstWire = ctx->getPipSrcWire(gb_pip_id);
         WireInfo dstWireInfo = ctx->wire_info(dstWire);
         int branch_tap_idx = net.clock > 3 ? 1 : 0;
-        snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
-                 branch_tap_idx);
-        PipId gt_pip_id = ctx->id(buf);
+        PipId gt_pip_id =
+                ctx->idf("R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx, branch_tap_idx);
         if (ctx->verbose) {
-            log_info("     GT Pip:%s\n", buf);
+            log_info("     GT Pip:%s\n", gt_pip_id.c_str(ctx));
         }
         // sanity
         NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
@@ -251,12 +262,13 @@ void GowinGlobalRouter::route_net(Context *ctx, globalnet_t const &net)
         for (auto const uphill_pip : ctx->getPipsUphill(dstWire)) {
             if (ctx->getPipSrcWire(uphill_pip) == net.clock_wire) {
                 src_pip_id = uphill_pip;
+                break;
             }
         }
-        NPNR_ASSERT(src_pip_id != PipId());
         if (ctx->verbose) {
             log_info("       Src Pip:%s\n", src_pip_id.c_str(ctx));
         }
+        NPNR_ASSERT(src_pip_id != PipId());
         // if already routed
         if (used_pips.count(src_pip_id)) {
             if (ctx->verbose) {
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 1ebd53151e..cb24ac02c2 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1034,7 +1034,7 @@ static void pack_plls(Context *ctx)
         if (ctx->verbose)
             log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
         if (is_pll(ctx, ci)) {
-            std::string parm_device = str_or_default(ci->params, id_DEVICE, "GW1N-1");
+            std::string parm_device = str_or_default(ci->params, id_DEVICE, ctx->device.c_str());
             if (parm_device != ctx->device) {
                 log_error("Cell '%s': wrong PLL device:%s instead of %s\n", ctx->nameOf(ci), parm_device.c_str(),
                           ctx->device.c_str());
@@ -1043,27 +1043,21 @@ static void pack_plls(Context *ctx)
 
             switch (ci->type.hash()) {
             case ID_rPLL: {
-                if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1") {
+                if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C") {
                     pll_disable_unused_ports(ctx, ci);
-                    // B half
-                    std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_RPLLB, ci->name.str(ctx) + "$rpllb");
-                    reconnect_rpllb(ctx, ci, cell.get());
+                    // A cell
+                    std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_rPLL, ci->name.str(ctx) + "$rpll");
+                    reconnect_rpll(ctx, ci, cell.get());
                     new_cells.push_back(std::move(cell));
-                    auto pllb_cell = new_cells.back().get();
-                    // A half
-                    cell = create_generic_cell(ctx, id_RPLLA, ci->name.str(ctx) + "$rplla");
-                    reconnect_rplla(ctx, ci, cell.get());
-                    new_cells.push_back(std::move(cell));
-                    auto plla_cell = new_cells.back().get();
+                    auto pll_cell = new_cells.back().get();
 
                     // need params for gowin_pack
                     for (auto &parm : ci->params) {
-                        plla_cell->setParam(parm.first, parm.second);
-                        pllb_cell->setParam(parm.first, parm.second);
+                        pll_cell->setParam(parm.first, parm.second);
                     }
                     packed_cells.insert(ci->name);
                 } else {
-                    log_error("PLL isn't supported for %s\n", ctx->device.c_str());
+                    log_error("rPLL isn't supported for %s\n", ctx->device.c_str());
                 }
             } break;
             case ID_PLLVR: {
@@ -1080,7 +1074,7 @@ static void pack_plls(Context *ctx)
                     }
                     packed_cells.insert(ci->name);
                 } else {
-                    log_error("PLL isn't supported for %s\n", ctx->device.c_str());
+                    log_error("PLLVR isn't supported for %s\n", ctx->device.c_str());
                 }
             } break;
             default:

From 0cf5006e3bbad476616f09bf1baf8a2953e1c616 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sun, 29 Jan 2023 21:11:54 +0100
Subject: [PATCH 253/712] ice40: Rework pull-up attribute copy to SB_IO blocks

We try to copy the attribute only when there is a chance for
the output driver to not be active.

Note that this can _also_ happen when a port is specified as
output but has a TBUF, which the previous code wasn't handling.

We could copy the attribute "all-the-time" but this would
mean if a user specified a `-pullup yes` in the PCF for a
permanently driven output pin, we'd be burning power for
nothing.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 ice40/cells.cc | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/ice40/cells.cc b/ice40/cells.cc
index fc24caaf4f..5e3bd1391e 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -404,25 +404,23 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 
 void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells)
 {
+    bool pull_up_attr = false;
+
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
         sbio->params[id_PIN_TYPE] = 1;
-        auto pu_attr = nxio->attrs.find(id_PULLUP);
-        if (pu_attr != nxio->attrs.end())
-            sbio->params[id_PULLUP] = pu_attr->second;
         nxio->movePortTo(id_O, sbio, id_D_IN_0);
+        pull_up_attr = true;
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
         sbio->params[id_PIN_TYPE] = 25;
         nxio->movePortTo(id_I, sbio, id_D_OUT_0);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
         NetInfo *i = nxio->getPort(id_I);
-        if (i == nullptr || i->driver.cell == nullptr)
+        if (i == nullptr || i->driver.cell == nullptr) {
             sbio->params[id_PIN_TYPE] = 1;
-        else
+            pull_up_attr = true;
+        } else
             sbio->params[id_PIN_TYPE] = 25;
-        auto pu_attr = nxio->attrs.find(id_PULLUP);
-        if (pu_attr != nxio->attrs.end())
-            sbio->params[id_PULLUP] = pu_attr->second;
         nxio->movePortTo(id_I, sbio, id_D_OUT_0);
         nxio->movePortTo(id_O, sbio, id_D_IN_0);
     } else {
@@ -465,6 +463,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         sbio->params[id_PIN_TYPE] = 41;
         tbuf->movePortTo(id_A, sbio, id_D_OUT_0);
         tbuf->movePortTo(id_E, sbio, id_OUTPUT_ENABLE);
+        pull_up_attr = true;
 
         if (donet->users.entries() > 1) {
             for (auto user : donet->users)
@@ -476,6 +475,13 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         ctx->nets.erase(donet->name);
         todelete_cells.insert(tbuf->name);
     }
+
+    // Copy pull-up attribute if there's any chance output driver isn't active
+    if (pull_up_attr) {
+        auto pu_attr = nxio->attrs.find(id_PULLUP);
+        if (pu_attr != nxio->attrs.end())
+            sbio->params[id_PULLUP] = pu_attr->second;
+    }
 }
 
 uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell)

From f50d4c1ed13142471505e0233e7985052d868ac2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sun, 29 Jan 2023 22:04:13 +0100
Subject: [PATCH 254/712] ice40: Support for undriven / unconnected output
 ports

If a port specified as output (and thus had a $nextpnr_obuf inserted)
is undriven (const `z` or const `x`), we make sure to not enable
the output driver. Also enable pull-ups if it was requested by the user.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 ice40/cells.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/ice40/cells.cc b/ice40/cells.cc
index 5e3bd1391e..10964f3caf 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -411,7 +411,12 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &to
         nxio->movePortTo(id_O, sbio, id_D_IN_0);
         pull_up_attr = true;
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
-        sbio->params[id_PIN_TYPE] = 25;
+        NetInfo *i = nxio->getPort(id_I);
+        if (i == nullptr || i->driver.cell == nullptr) {
+            sbio->params[id_PIN_TYPE] = 1;
+            pull_up_attr = true;
+        } else
+            sbio->params[id_PIN_TYPE] = 25;
         nxio->movePortTo(id_I, sbio, id_D_OUT_0);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below

From 6a1212a1e14d19bda114317e9f544b534cbf2841 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 30 Jan 2023 12:49:57 +1000
Subject: [PATCH 255/712] gowin: Add PLL support for the GW1NR-9 chip

And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 90 +++++++++++++++++++++++++--------------------------
 gowin/arch.h  |  9 ++++++
 gowin/pack.cc |  3 +-
 3 files changed, 56 insertions(+), 46 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 88b9f42f55..5ef83fbb8c 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2108,6 +2108,47 @@ bool Arch::is_GCLKT_iob(const CellInfo *cell)
     return false;
 }
 
+void Arch::bind_pll_to_bel(CellInfo *ci, int loc)
+{
+    BelId bel;
+    switch (ci->type.hash()) {
+    case ID_PLLVR:
+        bel = loc == PLL::left ? id("R1C28_PLLVR") : id("R1C37_PLLVR");
+        break;
+    case ID_rPLL:
+        if (family == "GW1N-1" || family == "GW1NZ-1") {
+            if (loc == PLL::left) {
+                return;
+            }
+            bel = id("R1C18_rPLL");
+            break;
+        }
+        if (family == "GW1NR-9C" || family == "GW1NR-9") {
+            bel = loc == PLL::left ? id("R10C1_rPLL") : id("R10C47_rPLL");
+            break;
+        }
+        break;
+    default:
+        return;
+    }
+    if (checkBelAvail(bel) || ci->belStrength != STRENGTH_LOCKED) {
+        if (ci->bel == bel) {
+            unbindBel(bel);
+        } else {
+            if (!checkBelAvail(bel) && ci->belStrength != STRENGTH_LOCKED) {
+                CellInfo *other_ci = getBoundBelCell(bel);
+                unbindBel(bel);
+                BelId our_bel = ci->bel;
+                unbindBel(our_bel);
+                bindBel(our_bel, other_ci, STRENGTH_LOCKED);
+            }
+        }
+        ci->disconnectPort(id_CLKIN);
+        ci->setParam(id_INSEL, Property("CLKIN0"));
+        bindBel(bel, ci, STRENGTH_LOCKED);
+    }
+}
+
 // If the PLL input can be connected using a direct wire, then do so,
 // bypassing conventional routing.
 void Arch::fix_pll_nets(Context *ctx)
@@ -2129,53 +2170,12 @@ void Arch::fix_pll_nets(Context *ctx)
                 break;
             }
             if (net_driven_by(ctx, net, is_RPLL_T_IN_iob, id_O) != nullptr) {
-                if (ci->type == id_rPLL) {
-                    ci->disconnectPort(id_CLKIN);
-                    ci->setParam(id_INSEL, Property("CLKIN0"));
-                    break;
-                }
-                BelId bel = id("R1C37_PLLVR");
-                if (ci->type == id_PLLVR) {
-                    if (checkBelAvail(bel) || ci->belStrength != STRENGTH_LOCKED) {
-                        if (ci->bel == bel) {
-                            unbindBel(bel);
-                        } else {
-                            if (!checkBelAvail(bel) && ci->belStrength != STRENGTH_LOCKED) {
-                                CellInfo *other_ci = getBoundBelCell(bel);
-                                unbindBel(bel);
-                                BelId our_bel = ci->bel;
-                                unbindBel(our_bel);
-                                bindBel(our_bel, other_ci, STRENGTH_LOCKED);
-                            }
-                        }
-                        ci->disconnectPort(id_CLKIN);
-                        ci->setParam(id_INSEL, Property("CLKIN0"));
-                        bindBel(bel, ci, STRENGTH_LOCKED);
-                        break;
-                    }
-                }
+                bind_pll_to_bel(ci, PLL::right);
+                break;
             }
             if (net_driven_by(ctx, net, is_LPLL_T_IN_iob, id_O) != nullptr) {
-                BelId bel = id("R1C28_PLLVR");
-                if (ci->type == id_PLLVR) {
-                    if (checkBelAvail(bel) || ci->belStrength != STRENGTH_LOCKED) {
-                        if (ci->bel == bel) {
-                            unbindBel(bel);
-                        } else {
-                            if (!checkBelAvail(bel) && ci->belStrength != STRENGTH_LOCKED) {
-                                CellInfo *other_ci = getBoundBelCell(bel);
-                                unbindBel(bel);
-                                BelId our_bel = ci->bel;
-                                unbindBel(our_bel);
-                                bindBel(our_bel, other_ci, STRENGTH_LOCKED);
-                            }
-                        }
-                        ci->disconnectPort(id_CLKIN);
-                        ci->setParam(id_INSEL, Property("CLKIN0"));
-                        bindBel(bel, ci, STRENGTH_LOCKED);
-                        break;
-                    }
-                }
+                bind_pll_to_bel(ci, PLL::left);
+                break;
             }
             // XXX do special bels (HCLK etc)
             // This is general routing through CLK0 pip
diff --git a/gowin/arch.h b/gowin/arch.h
index f060165aea..6f76d5772b 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -482,6 +482,7 @@ struct Arch : BaseArch<ArchRanges>
     void add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col);
     void fix_pll_nets(Context *ctx);
     bool is_GCLKT_iob(const CellInfo *cell);
+    void bind_pll_to_bel(CellInfo *ci, int loc);
 
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
@@ -530,6 +531,14 @@ enum
 };
 }
 
+namespace PLL { // fixed PLL locations
+enum
+{
+    left = 0,
+    right = 1
+};
+}
+
 NEXTPNR_NAMESPACE_END
 
 #endif /* GOWIN_ARCH_H */
diff --git a/gowin/pack.cc b/gowin/pack.cc
index cb24ac02c2..09e5c88080 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1043,7 +1043,8 @@ static void pack_plls(Context *ctx)
 
             switch (ci->type.hash()) {
             case ID_rPLL: {
-                if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C") {
+                if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C" ||
+                    parm_device == "GW1NR-9") {
                     pll_disable_unused_ports(ctx, ci);
                     // A cell
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_rPLL, ci->name.str(ctx) + "$rpll");

From 2829a7d70af7a4cc32173cced2ebd5cb5e46cb93 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 30 Jan 2023 18:59:09 +1000
Subject: [PATCH 256/712] gowin: Proper use of the C++ mechanisms

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc |  2 +-
 gowin/arch.h  | 16 +++++++---------
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 5ef83fbb8c..1574eee31b 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2108,7 +2108,7 @@ bool Arch::is_GCLKT_iob(const CellInfo *cell)
     return false;
 }
 
-void Arch::bind_pll_to_bel(CellInfo *ci, int loc)
+void Arch::bind_pll_to_bel(CellInfo *ci, PLL loc)
 {
     BelId bel;
     switch (ci->type.hash()) {
diff --git a/gowin/arch.h b/gowin/arch.h
index 6f76d5772b..822cdfc167 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -283,6 +283,12 @@ struct ArchRanges : BaseArchRanges
     using GroupGroupsRangeT = const std::vector<GroupId> &;
 };
 
+enum class PLL // fixed PLL locations
+{
+    left,
+    right
+};
+
 struct Arch : BaseArch<ArchRanges>
 {
     std::string family;
@@ -482,7 +488,7 @@ struct Arch : BaseArch<ArchRanges>
     void add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString belname, int row, int col);
     void fix_pll_nets(Context *ctx);
     bool is_GCLKT_iob(const CellInfo *cell);
-    void bind_pll_to_bel(CellInfo *ci, int loc);
+    void bind_pll_to_bel(CellInfo *ci, PLL loc);
 
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
@@ -531,14 +537,6 @@ enum
 };
 }
 
-namespace PLL { // fixed PLL locations
-enum
-{
-    left = 0,
-    right = 1
-};
-}
-
 NEXTPNR_NAMESPACE_END
 
 #endif /* GOWIN_ARCH_H */

From aac36ecf3f5869498876fda03d9e5f0a2ab9f2a3 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 31 Jan 2023 08:58:33 +1000
Subject: [PATCH 257/712] gowin: Add PLL support for GW1NR-4 chips

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 6 +++++-
 gowin/pack.cc | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 1574eee31b..734ff9110d 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2123,11 +2123,15 @@ void Arch::bind_pll_to_bel(CellInfo *ci, PLL loc)
             bel = id("R1C18_rPLL");
             break;
         }
+        if (family == "GW1N-4") {
+            bel = loc == PLL::left ? id("R1C10_rPLL") : id("R1C28_rPLL");
+            break;
+        }
         if (family == "GW1NR-9C" || family == "GW1NR-9") {
             bel = loc == PLL::left ? id("R10C1_rPLL") : id("R10C47_rPLL");
             break;
         }
-        break;
+        return;
     default:
         return;
     }
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 09e5c88080..bed0a8df17 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1044,7 +1044,7 @@ static void pack_plls(Context *ctx)
             switch (ci->type.hash()) {
             case ID_rPLL: {
                 if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C" ||
-                    parm_device == "GW1NR-9") {
+                    parm_device == "GW1NR-9" || parm_device == "GW1N-4") {
                     pll_disable_unused_ports(ctx, ci);
                     // A cell
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_rPLL, ci->name.str(ctx) + "$rpll");

From 5d5ea57e2123a6d66aa63bf82ac6110713ab8bc7 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 31 Jan 2023 18:46:38 +1000
Subject: [PATCH 258/712] gowin: Add PLL support for the GW1NS-2C chip

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 7 +++++++
 gowin/pack.cc | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 734ff9110d..fbe26cdd9a 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2123,6 +2123,13 @@ void Arch::bind_pll_to_bel(CellInfo *ci, PLL loc)
             bel = id("R1C18_rPLL");
             break;
         }
+        if (family == "GW1NS-2") {
+            if (loc == PLL::left) {
+                return;
+            }
+            bel = id("R10C20_rPLL");
+            break;
+        }
         if (family == "GW1N-4") {
             bel = loc == PLL::left ? id("R1C10_rPLL") : id("R1C28_rPLL");
             break;
diff --git a/gowin/pack.cc b/gowin/pack.cc
index bed0a8df17..fc8708901b 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -1044,7 +1044,7 @@ static void pack_plls(Context *ctx)
             switch (ci->type.hash()) {
             case ID_rPLL: {
                 if (parm_device == "GW1N-1" || parm_device == "GW1NZ-1" || parm_device == "GW1NR-9C" ||
-                    parm_device == "GW1NR-9" || parm_device == "GW1N-4") {
+                    parm_device == "GW1NR-9" || parm_device == "GW1N-4" || parm_device == "GW1NS-2C") {
                     pll_disable_unused_ports(ctx, ci);
                     // A cell
                     std::unique_ptr<CellInfo> cell = create_generic_cell(ctx, id_rPLL, ci->name.str(ctx) + "$rpll");

From 803c57d0529089bab71e203e7bc7e3e5be15285a Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Tue, 31 Jan 2023 21:00:21 +0100
Subject: [PATCH 259/712] ecp5: LOCATE in LPF works on singleton vector

---
 ecp5/lpf.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 4f02d22d7d..2e34f54a40 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -131,9 +131,16 @@ bool Arch::apply_lpf(std::string filename, std::istream &in)
                         std::string cell = strip_quotes(words.at(2));
                         if (words.at(3) != "SITE")
                             log_error("expected 'SITE' after 'LOCATE COMP %s' (on line %d)\n", cell.c_str(), lineno);
-                        auto fnd_cell = cells.find(id(cell));
                         if (words.size() > 5)
                             log_error("unexpected input following LOCATE clause (on line %d)\n", lineno);
+                        auto fnd_cell = cells.find(id(cell));
+                        // 1-bit wires are treated as scalar by nextpnr.
+                        // In HDL they might have been a singleton vector.
+                        if (fnd_cell == cells.end() && cell.size() >= 3 && cell.substr(cell.size() - 3) == "[0]") {
+                            cell = cell.substr(0, cell.size() - 3);
+                            fnd_cell = cells.find(id(cell));
+                        }
+
                         if (fnd_cell != cells.end()) {
                             fnd_cell->second->attrs[id_LOC] = strip_quotes(words.at(4));
                         }

From 49ae4953443951bcd9679689e76c56411a3c9385 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Wed, 1 Feb 2023 11:41:16 +0100
Subject: [PATCH 260/712] ice40: Add support for PLL ICEGATE function

Technically you can enable it independently on CORE and GLOBAL
output, but this is not exposed in the classic primitive, so
we do the same as icecube2 and enable/disable it for both output
path depending on the argument

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 ice40/bitstream.cc | 27 ++++++++++++++-------------
 ice40/cells.cc     |  3 +++
 ice40/constids.inc |  2 ++
 3 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index c8ad93d819..6794ecca00 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -423,6 +423,18 @@ void write_asc(const Context *ctx, std::ostream &out)
             // If this is a PAD PLL, and this is the 'PLLOUT_A' port, then the same SB_IO is also PAD
             if (port == id_PLLOUT_A && is_sb_pll40_pad(ctx, cell.second.get()))
                 sb_io_used_by_pll_pad.insert(io_bel_loc);
+
+            // Configure the SB_IO that the clock outputs are going through.
+            // note: PINTYPE[1:0] must be set property to passes the PLL through to the fabric.
+            //       "01" if ICEGATE is disabed for that port and "11" if it's enabled
+            const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
+            bool icegate_ena = get_param_or_def(
+                    ctx, cell.second.get(), (port == id_PLLOUT_A) ? id_ENABLE_ICEGATE_PORTA : id_ENABLE_ICEGATE_PORTB);
+
+            set_config(ti, config.at(io_bel_loc.y).at(io_bel_loc.x),
+                       "IOB_" + std::to_string(io_bel_loc.z) + ".PINTYPE_1", icegate_ena);
+            set_config(ti, config.at(io_bel_loc.y).at(io_bel_loc.x),
+                       "IOB_" + std::to_string(io_bel_loc.z) + ".PINTYPE_0", true);
         }
     }
 
@@ -724,6 +736,8 @@ void write_asc(const Context *ctx, std::ostream &out)
                                                                          {"DIVF", 7},
                                                                          {"DIVQ", 3},
                                                                          {"DIVR", 4},
+                                                                         {"ENABLE_ICEGATE_PORTA", 1},
+                                                                         {"ENABLE_ICEGATE_PORTB", 1},
                                                                          {"FDA_FEEDBACK", 4},
                                                                          {"FDA_RELATIVE", 4},
                                                                          {"FEEDBACK_PATH", 3},
@@ -734,19 +748,6 @@ void write_asc(const Context *ctx, std::ostream &out)
                                                                          {"SHIFTREG_DIV_MODE", 2},
                                                                          {"TEST_MODE", 1}};
             configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL."));
-
-            // Configure the SB_IOs that the clock outputs are going through.
-            for (auto &io_bel_loc : sb_io_used_by_pll_out) {
-                // Write config.
-                const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-
-                // PINTYPE[1:0] == "01" passes the PLL through to the fabric.
-                set_config(ti, config.at(io_bel_loc.y).at(io_bel_loc.x),
-                           "IOB_" + std::to_string(io_bel_loc.z) + ".PINTYPE_1", false);
-                set_config(ti, config.at(io_bel_loc.y).at(io_bel_loc.x),
-                           "IOB_" + std::to_string(io_bel_loc.z) + ".PINTYPE_0", true);
-            }
-
         } else {
             NPNR_ASSERT(false);
         }
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 10964f3caf..d304a68f75 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -216,6 +216,9 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         new_cell->params[id_PLLOUT_SELECT_A] = Property(0, 2);
         new_cell->params[id_PLLOUT_SELECT_B] = Property(0, 2);
 
+        new_cell->params[id_ENABLE_ICEGATE_PORTA] = Property::State::S0;
+        new_cell->params[id_ENABLE_ICEGATE_PORTB] = Property::State::S0;
+
         new_cell->params[id_PLLTYPE] = Property(0, 3);
         new_cell->params[id_SHIFTREG_DIVMODE] = Property::State::S0;
         new_cell->params[id_TEST_MODE] = Property::State::S0;
diff --git a/ice40/constids.inc b/ice40/constids.inc
index 8bad9e2547..5575053dee 100644
--- a/ice40/constids.inc
+++ b/ice40/constids.inc
@@ -480,6 +480,8 @@ X(DIVQ)
 X(DIVR)
 X(D_REG)
 X(E)
+X(ENABLE_ICEGATE_PORTA)
+X(ENABLE_ICEGATE_PORTB)
 X(FDA_FEEDBACK)
 X(FDA_RELATIVE)
 X(FEEDBACK_PATH)

From 582410629bb45a55aa1a3b8258bd466e71b3a972 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Wed, 1 Feb 2023 15:00:44 +0100
Subject: [PATCH 261/712] ice40: Don't assert on unknown extra_config bits if
 they are 0

Bits are 0 by default anyway, so if they are unknown (because icestorm
is too od) but we want them at 0 ... it's not much of an issue.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 ice40/bitstream.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 6794ecca00..72343d75a1 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -153,7 +153,11 @@ static void set_ec_cbit(chipconfig_t &config, const Context *ctx, const BelConfi
             return;
         }
     }
-    NPNR_ASSERT_FALSE_STR("failed to config extra cell config bit " + name);
+    if (value)
+        NPNR_ASSERT_FALSE_STR("failed to config extra cell config bit " + name);
+    else
+        log_warning("failed to config extra cell config bit %s to zero (ignored, maybe update icestorm ?)\n",
+                    name.c_str());
 }
 
 void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *cell,

From a38ee0786a66f91a702c3eeeed4efd76ad04aec9 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 1 Feb 2023 18:41:12 +0100
Subject: [PATCH 262/712] ecp5: Propagate clock constraints through DSCS

---
 ecp5/pack.cc | 119 +++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 107 insertions(+), 12 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 79d1688fc4..1146181be5 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -2602,6 +2602,15 @@ class Ecp5Packer
         auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
 
         auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
+        auto equals_epsilon_pair = [&](DelayPair& a, DelayPair& b) {
+            return equals_epsilon(a.min_delay, b.min_delay)
+                && equals_epsilon(a.max_delay, b.max_delay);
+        };
+        auto equals_epsilon_constr = [&](ClockConstraint& a, ClockConstraint& b) {
+            return equals_epsilon_pair(a.high, b.high)
+                && equals_epsilon_pair(a.low, b.low)
+                && equals_epsilon_pair(a.period, b.period);
+        };
 
         pool<IdString> user_constrained, changed_nets;
         for (auto &net : ctx->nets) {
@@ -2619,24 +2628,30 @@ class Ecp5Packer
             return true;
         };
 
-        auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
+        auto simple_clk_contraint = [&](delay_t period) {
+            auto constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+            constr->low = DelayPair(period / 2);
+            constr->high = DelayPair(period / 2);
+            constr->period = DelayPair(period);
+
+            return constr;
+        };
+
+        auto set_constraint = [&](CellInfo *ci, IdString port, std::unique_ptr<ClockConstraint> constr) {
             if (!ci->ports.count(port))
                 return;
             NetInfo *to = ci->ports.at(port).net;
             if (to == nullptr)
                 return;
             if (to->clkconstr != nullptr) {
-                if (!equals_epsilon(to->clkconstr->period.minDelay(), period) && user_constrained.count(to->name))
+                if (!equals_epsilon_constr(*to->clkconstr, *constr) && user_constrained.count(to->name))
                     log_warning(
                             "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
                             "%.1f MHz.\n",
-                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
+                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(constr->period.min_delay));
                 return;
             }
-            to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-            to->clkconstr->low = DelayPair(period / 2);
-            to->clkconstr->high = DelayPair(period / 2);
-            to->clkconstr->period = DelayPair(period);
+            to->clkconstr = std::move(constr);
             log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);
@@ -2706,6 +2721,86 @@ class Ecp5Packer
                     copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
                 } else if (ci->type == id_DCCA) {
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
+                } else if (ci->type == id_DCSC) {
+                    if ((!ci->ports.count(id_CLK0) && !ci->ports.count(id_CLK1)) || !ci->ports.count(id_DCSOUT))
+                        continue;
+                    auto mode = str_or_default(ci->params, id_DCSMODE, "POS");
+
+                    // TODO: We can do this simplification if we know
+                    // MODESEL is tied to 0. I don't know how I can check this
+                    // if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
+                    //     copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
+                    //     continue;
+                    // } else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
+                    //     copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
+                    //     continue;
+                    // } else if (mode == "LOW" || mode == "HIGH") {
+                    //     continue;
+                    // }
+
+                    std::unique_ptr<ClockConstraint> derived_constr = nullptr;
+                    std::vector<NetInfo*> in_ports = {
+                        ci->ports.at(id_CLK0).net,
+                        ci->ports.at(id_CLK1).net,
+                    };
+
+                    for (auto p : in_ports) { 
+                        if (p == nullptr || p->clkconstr == nullptr) {
+                            derived_constr = nullptr;
+                            break;
+                        }
+
+                        if (derived_constr == nullptr) {
+                            derived_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint ());
+                            derived_constr->low = p->clkconstr->low;
+                            derived_constr->high = p->clkconstr->high;
+                            derived_constr->period = p->clkconstr->period;
+                            continue;
+                        }
+
+                        auto& c1 = p->clkconstr;
+                        auto& c2 = derived_constr;
+
+                        if (mode == "NEG") {
+                            derived_constr->low = DelayPair(
+                                std::min(c1->low.min_delay, c2->low.min_delay),
+                                std::max(
+                                    c1->low.max_delay + c2->period.max_delay,
+                                    c2->low.max_delay + c1->period.max_delay
+                                )
+                            );
+                        } else {
+                            derived_constr->low = DelayPair(
+                                std::min(c1->low.min_delay, c2->low.min_delay),
+                                std::max(c1->low.max_delay, c2->low.max_delay)
+                            );
+                        }
+
+                        if (mode == "POS") {
+                            derived_constr->high = DelayPair(
+                                std::min(c1->high.min_delay, c2->high.min_delay),
+                                std::max(
+                                    c1->high.max_delay + c2->period.max_delay,
+                                    c2->high.max_delay + c1->period.max_delay
+                                )
+                            );
+                        } else {
+                            derived_constr->high = DelayPair(
+                                std::min(c1->high.min_delay, c2->high.min_delay),
+                                std::max(c1->high.max_delay, c2->high.max_delay)
+                            );
+                        }
+
+                        derived_constr->period = DelayPair(
+                            std::min(c1->period.min_delay, c2->period.min_delay),
+                            std::max(c1->period.max_delay, c2->period.max_delay)
+                        );
+                    }
+
+                    if (derived_constr != nullptr) {
+                        set_constraint(ci, id_DCSOUT, std::move(derived_constr));
+                    }
+
                 } else if (ci->type == id_EHXPLLL) {
                     delay_t period_in;
                     if (!get_period(ci, id_CLKI, period_in))
@@ -2734,13 +2829,13 @@ class Ecp5Packer
                         log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
                                  "800MHz]\n",
                                  vco_freq, ci->name.c_str(ctx));
-                    set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1));
-                    set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1));
-                    set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1));
-                    set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1));
+                    set_constraint(ci, id_CLKOP, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
+                    set_constraint(ci, id_CLKOS, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
+                    set_constraint(ci, id_CLKOS2, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
+                    set_constraint(ci, id_CLKOS3, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
                 } else if (ci->type == id_OSCG) {
                     int div = int_or_default(ci->params, id_DIV, 128);
-                    set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
+                    set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));
                 }
             }
         }

From d2bf44ba45370af601e1db9fe1cb02d3e58c8e27 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Mon, 6 Feb 2023 15:40:28 +0100
Subject: [PATCH 263/712] ecp5: DSCS clock propagation if modesel is 0 constant

---
 ecp5/pack.cc | 151 +++++++++++++++++++++++++++++++++------------------
 1 file changed, 99 insertions(+), 52 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 1146181be5..7033319f7e 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -36,6 +36,18 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
            cell->type == ctx->id("$nextpnr_iobuf");
 }
 
+static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
+{
+    if (net == nullptr)
+        return false;
+    if (net->name == ctx->id("$PACKER_GND_NET") || net->name == ctx->id("$PACKER_VCC_NET")) {
+        value = (net->name == ctx->id("$PACKER_VCC_NET"));
+        return true;
+    } else {
+        return false;
+    }
+}
+
 class Ecp5Packer
 {
   public:
@@ -2724,19 +2736,22 @@ class Ecp5Packer
                 } else if (ci->type == id_DCSC) {
                     if ((!ci->ports.count(id_CLK0) && !ci->ports.count(id_CLK1)) || !ci->ports.count(id_DCSOUT))
                         continue;
+
                     auto mode = str_or_default(ci->params, id_DCSMODE, "POS");
+                    bool mode_constant = false;
+                    auto mode_is_constant = net_is_constant(ctx, ci->ports.at(id_MODESEL).net, mode_constant);
 
-                    // TODO: We can do this simplification if we know
-                    // MODESEL is tied to 0. I don't know how I can check this
-                    // if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
-                    //     copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
-                    //     continue;
-                    // } else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
-                    //     copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
-                    //     continue;
-                    // } else if (mode == "LOW" || mode == "HIGH") {
-                    //     continue;
-                    // }
+                    if (mode_is_constant && mode_constant == false) {
+                        if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
+                            copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
+                            continue;
+                        } else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
+                            copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
+                            continue;
+                        } else if (mode == "LOW" || mode == "HIGH") {
+                            continue;
+                        }
+                    }
 
                     std::unique_ptr<ClockConstraint> derived_constr = nullptr;
                     std::vector<NetInfo*> in_ports = {
@@ -2744,63 +2759,95 @@ class Ecp5Packer
                         ci->ports.at(id_CLK1).net,
                     };
 
-                    for (auto p : in_ports) { 
-                        if (p == nullptr || p->clkconstr == nullptr) {
+                    // Generate all unique clock pairs find the worst
+                    // constraint from switching between them and merge them
+                    // into the final output constraint.
+                    for (size_t i = 0; i < in_ports.size(); ++i) {
+                        auto p1 = in_ports[i];
+                        if (p1 == nullptr || p1->clkconstr == nullptr) {
                             derived_constr = nullptr;
                             break;
                         }
+                        for (size_t j = i + 1; j < in_ports.size(); ++j) {
+                            auto p2 = in_ports[j];
+                            if (p2 == nullptr || p2->clkconstr == nullptr) {
+                                break;
+                            }
+                            auto& c1 = p1->clkconstr;
+                            auto& c2 = p2->clkconstr;
+
+                            auto merged_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+
+                            if (mode == "NEG") {
+                                merged_constr->low = DelayPair(
+                                    std::min(c1->low.min_delay, c2->low.min_delay),
+                                    std::max(
+                                        c1->low.max_delay + c2->period.max_delay,
+                                        c2->low.max_delay + c1->period.max_delay
+                                    )
+                                );
+                            } else {
+                                merged_constr->low = DelayPair(
+                                    std::min(c1->low.min_delay, c2->low.min_delay),
+                                    std::max(c1->low.max_delay, c2->low.max_delay)
+                                );
+                            }
 
-                        if (derived_constr == nullptr) {
-                            derived_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint ());
-                            derived_constr->low = p->clkconstr->low;
-                            derived_constr->high = p->clkconstr->high;
-                            derived_constr->period = p->clkconstr->period;
-                            continue;
-                        }
+                            if (mode == "POS") {
+                                merged_constr->high = DelayPair(
+                                    std::min(c1->high.min_delay, c2->high.min_delay),
+                                    std::max(
+                                        c1->high.max_delay + c2->period.max_delay,
+                                        c2->high.max_delay + c1->period.max_delay
+                                    )
+                                );
+                            } else {
+                                merged_constr->high = DelayPair(
+                                    std::min(c1->high.min_delay, c2->high.min_delay),
+                                    std::max(c1->high.max_delay, c2->high.max_delay)
+                                );
+                            }
 
-                        auto& c1 = p->clkconstr;
-                        auto& c2 = derived_constr;
+                            merged_constr->period = DelayPair(
+                                std::min(c1->period.min_delay, c2->period.min_delay),
+                                std::max(c1->period.max_delay, c2->period.max_delay)
+                            );
+
+                            if (derived_constr == nullptr) {
+                                derived_constr = std::move(merged_constr);
+                                continue;
+                            }
 
-                        if (mode == "NEG") {
-                            derived_constr->low = DelayPair(
-                                std::min(c1->low.min_delay, c2->low.min_delay),
-                                std::max(
-                                    c1->low.max_delay + c2->period.max_delay,
-                                    c2->low.max_delay + c1->period.max_delay
-                                )
+                            derived_constr->period.min_delay = std::min(
+                                derived_constr->period.min_delay,
+                                merged_constr->period.min_delay
                             );
-                        } else {
-                            derived_constr->low = DelayPair(
-                                std::min(c1->low.min_delay, c2->low.min_delay),
-                                std::max(c1->low.max_delay, c2->low.max_delay)
+                            derived_constr->period.max_delay = std::max(
+                                derived_constr->period.max_delay,
+                                merged_constr->period.max_delay
                             );
-                        }
-
-                        if (mode == "POS") {
-                            derived_constr->high = DelayPair(
-                                std::min(c1->high.min_delay, c2->high.min_delay),
-                                std::max(
-                                    c1->high.max_delay + c2->period.max_delay,
-                                    c2->high.max_delay + c1->period.max_delay
-                                )
+                            derived_constr->low.min_delay = std::min(
+                                derived_constr->low.min_delay,
+                                merged_constr->low.min_delay
                             );
-                        } else {
-                            derived_constr->high = DelayPair(
-                                std::min(c1->high.min_delay, c2->high.min_delay),
-                                std::max(c1->high.max_delay, c2->high.max_delay)
+                            derived_constr->low.max_delay = std::max(
+                                derived_constr->low.max_delay,
+                                merged_constr->low.max_delay
+                            );
+                            derived_constr->high.min_delay = std::min(
+                                derived_constr->high.min_delay,
+                                merged_constr->high.min_delay
+                            );
+                            derived_constr->high.max_delay = std::max(
+                                derived_constr->high.max_delay,
+                                merged_constr->high.max_delay
                             );
                         }
-
-                        derived_constr->period = DelayPair(
-                            std::min(c1->period.min_delay, c2->period.min_delay),
-                            std::max(c1->period.max_delay, c2->period.max_delay)
-                        );
                     }
 
                     if (derived_constr != nullptr) {
                         set_constraint(ci, id_DCSOUT, std::move(derived_constr));
                     }
-
                 } else if (ci->type == id_EHXPLLL) {
                     delay_t period_in;
                     if (!get_period(ci, id_CLKI, period_in))

From 9e8f8b7b45b4060531190259b2cfaae4d18819f1 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Mon, 6 Feb 2023 17:04:30 +0100
Subject: [PATCH 264/712] streamline constant_net detection

---
 ecp5/pack.cc  | 6 ++++--
 ice40/pack.cc | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 7033319f7e..a6f316567a 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -38,10 +38,12 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 
 static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
 {
+    auto gnd = ctx->id("$PACKER_GND_NET");
+    auto vcc = ctx->id("$PACKER_VCC_NET");
     if (net == nullptr)
         return false;
-    if (net->name == ctx->id("$PACKER_GND_NET") || net->name == ctx->id("$PACKER_VCC_NET")) {
-        value = (net->name == ctx->id("$PACKER_VCC_NET"));
+    if (net->name.in(gnd, vcc)) {
+        value = (net->name == vcc);
         return true;
     } else {
         return false;
diff --git a/ice40/pack.cc b/ice40/pack.cc
index c981172175..f8944685f8 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -132,10 +132,12 @@ static void pack_nonlut_ffs(Context *ctx)
 
 static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
 {
+    auto gnd = ctx->id("$PACKER_GND_NET");
+    auto vcc = ctx->id("$PACKER_VCC_NET");
     if (net == nullptr)
         return false;
-    if (net->name == ctx->id("$PACKER_GND_NET") || net->name == ctx->id("$PACKER_VCC_NET")) {
-        value = (net->name == ctx->id("$PACKER_VCC_NET"));
+    if (net->name.in(gnd, vcc)) {
+        value = (net->name == vcc);
         return true;
     } else {
         return false;

From 69fe654f02fcc18fae0e285f7e87319a2522221f Mon Sep 17 00:00:00 2001
From: uis <uis9936@gmail.com>
Date: Mon, 6 Feb 2023 21:32:04 +0000
Subject: [PATCH 265/712] gowin: Add bels for new types of oscillator

---
 gowin/arch.cc      | 19 +++++++++++++++++++
 gowin/constids.inc |  2 ++
 2 files changed, 21 insertions(+)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index fbe26cdd9a..1629d653bf 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1430,6 +1430,25 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OSCEN, id(buf));
                 break;
+            case ID_OSCW:
+                snprintf(buf, 32, "R%dC%d_OSCW", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSCW, Loc(col, row, BelZ::osc_z), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                break;
+            case ID_OSCO:
+                snprintf(buf, 32, "R%dC%d_OSCO", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_OSCO, Loc(col, row, BelZ::osc_z), false);
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelOutput(belname, id_OSCOUT, id(buf));
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
+                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                addBelInput(belname, id_OSCEN, id(buf));
+                break;
             case ID_RAM16:
                 snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
                 belname = id(buf);
diff --git a/gowin/constids.inc b/gowin/constids.inc
index dac84a1e08..b678cc7747 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -851,6 +851,8 @@ X(OSC)
 X(OSCZ)
 X(OSCH)
 X(OSCF)
+X(OSCW)
+X(OSCO)
 
 // PLLs
 X(rPLL)

From a8a88d4813b63d8ec1ed93eaedc27ec2c8e14c7c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 9 Feb 2023 11:12:15 +0100
Subject: [PATCH 266/712] ecp5: Handle the case where both CE are the same
 constant

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 79d1688fc4..23d3a1ae27 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -1508,6 +1508,10 @@ class Ecp5Packer
     // Check if two nets have identical constant drivers
     bool equal_constant(NetInfo *a, NetInfo *b)
     {
+        if (a == nullptr && b == nullptr)
+            return true;
+        if ((a == nullptr) != (b == nullptr))
+            return false;
         if (a->driver.cell == nullptr || b->driver.cell == nullptr)
             return (a->driver.cell == nullptr && b->driver.cell == nullptr);
         if (a->driver.cell->type != id_GND && a->driver.cell->type != id_VCC)
@@ -2237,7 +2241,8 @@ class Ecp5Packer
                                 iol->params[id_CEMUX] = str_or_default(ci->params, id_CEMUX, "CE");
                                 ci->movePortTo(id_CE, iol, id_CE);
                             } else {
-                                if (iol->getPort(id_CE) != ci->getPort(id_CE) ||
+                                if ((iol->getPort(id_CE) != ci->getPort(id_CE) &&
+                                     !equal_constant(iol->getPort(id_CE), ci->getPort(id_CE))) ||
                                     str_or_default(ci->params, id_CEMUX, "CE") !=
                                             str_or_default(iol->params, id_CEMUX, "CE"))
                                     log_error("CE signal or polarity mismatch for IO flipflop %s with other IOFFs at "
@@ -2303,7 +2308,8 @@ class Ecp5Packer
                                 iol->params[id_CEMUX] = str_or_default(ci->params, id_CEMUX, "CE");
                                 ci->movePortTo(id_CE, iol, id_CE);
                             } else {
-                                if (iol->getPort(id_CE) != ci->getPort(id_CE) ||
+                                if ((iol->getPort(id_CE) != ci->getPort(id_CE) &&
+                                     !equal_constant(iol->getPort(id_CE), ci->getPort(id_CE))) ||
                                     str_or_default(ci->params, id_CEMUX, "CE") !=
                                             str_or_default(iol->params, id_CEMUX, "CE"))
                                     log_error("CE signal or polarity mismatch for IO flipflop %s with other IOFFs at "

From eb70e950796ccb6b1d44fff2240fe30da5eecf7b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 10 Feb 2023 13:23:31 +0100
Subject: [PATCH 267/712] fabulous: Improve names for BRAM bels

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabric_parsing.h | 14 ++++++++++++++
 generic/viaduct/fabulous/fabulous.cc      | 17 +++++++++++------
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/generic/viaduct/fabulous/fabric_parsing.h b/generic/viaduct/fabulous/fabric_parsing.h
index 3fa263ca5d..841b246550 100644
--- a/generic/viaduct/fabulous/fabric_parsing.h
+++ b/generic/viaduct/fabulous/fabric_parsing.h
@@ -68,6 +68,14 @@ struct parser_view
         return npos;
     }
 
+    size_t rfind(char tok) const
+    {
+        for (size_t i = m_length; i > 0; i--)
+            if (m_ptr[i - 1] == tok)
+                return i - 1;
+        return npos;
+    }
+
     IdString to_id(const BaseCtx *ctx)
     {
         // This isn't really ideal, let's hope one day we can move to C++20 and have proper string_views instead :3
@@ -133,6 +141,12 @@ struct parser_view
         NPNR_ASSERT(pos != npos);
         return std::make_pair(parser_view(m_ptr, pos), parser_view(m_ptr + pos + 1, m_length - (pos + 1)));
     }
+    std::pair<parser_view, parser_view> rsplit(char delim) const
+    {
+        size_t pos = rfind(delim);
+        NPNR_ASSERT(pos != npos);
+        return std::make_pair(parser_view(m_ptr, pos), parser_view(m_ptr + pos + 1, m_length - (pos + 1)));
+    }
 };
 
 struct CsvParser
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index e2fe1b74b5..7dad0c66da 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -237,6 +237,16 @@ struct FabulousImpl : ViaductAPI
             NPNR_ASSERT(bel_idx.size() == 1);
             int bel_z = bel_idx[0] - 'A';
             NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
+            std::vector<parser_view> ports;
+            parser_view port;
+            while (!(port = csv.next_field()).empty()) {
+                ports.push_back(port);
+            }
+            IdString bel_name = bel_idx.to_id(ctx);
+            if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) {
+                // Assign BRAM IO a nicer name than just a letter
+                bel_name = ports.front().rsplit('_').first.to_id(ctx);
+            }
             /*
             In the future we will need to handle optionally splitting SLICEs into separate LUT/COMB and FF bels
             This is the preferred approach in nextpnr for arches where the LUT and FF can be used separately of
@@ -245,12 +255,7 @@ struct FabulousImpl : ViaductAPI
             While this isn't yet the standard fabulous SLICE, it should be considered as a future option in fabulous.
             */
             Loc loc(bel_x, bel_y, bel_z);
-            BelId bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type, loc, false, false);
-            std::vector<parser_view> ports;
-            parser_view port;
-            while (!(port = csv.next_field()).empty()) {
-                ports.push_back(port);
-            }
+            BelId bel = ctx->addBel(IdStringList::concat(tile, bel_name), bel_type, loc, false, false);
             handle_bel_ports(bel, tile, bel_type, ports);
         }
         postprocess_bels();

From 3608c3eb029daf888000350872d81128c2f296ff Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Mon, 6 Feb 2023 16:08:35 +0100
Subject: [PATCH 268/712] common: Implement Werror flag

---
 common/kernel/command.cc |  5 +++++
 common/kernel/log.cc     | 32 +++++++++++++++++++++++---------
 common/kernel/log.h      |  1 +
 3 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 842d8a71b3..2fb4ee53c8 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -105,6 +105,10 @@ bool CommandHandler::executeBeforeContext()
         log_streams.push_back(std::make_pair(&std::cerr, LogLevel::LOG_MSG));
     }
 
+    if (vm.count("Werror")) {
+        log_warn_as_error = true;
+    }
+
     if (vm.count("log")) {
         std::string logfilename = vm["log"].as<std::string>();
         logfile.open(logfilename);
@@ -121,6 +125,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("help,h", "show help");
     general.add_options()("verbose,v", "verbose output");
     general.add_options()("quiet,q", "quiet mode, only errors and warnings displayed");
+    general.add_options()("Werror", "Turn warnings into errors");
     general.add_options()("log,l", po::value<std::string>(),
                           "log file, all log messages are written to this file regardless of -q");
     general.add_options()("debug", "debug output");
diff --git a/common/kernel/log.cc b/common/kernel/log.cc
index 8b1ad43b19..a0bdd64eb1 100644
--- a/common/kernel/log.cc
+++ b/common/kernel/log.cc
@@ -41,6 +41,7 @@ void (*log_error_atexit)() = NULL;
 dict<LogLevel, int, loglevel_hash_ops> message_count_by_level;
 static int log_newline_count = 0;
 bool had_nonfatal_error = false;
+bool log_warn_as_error = false;
 
 std::string stringf(const char *fmt, ...)
 {
@@ -128,6 +129,22 @@ void logv_prefixed(const char *prefix, const char *format, va_list ap, LogLevel
     log_flush();
 }
 
+void logv_nonfatal_error(const char *format, va_list ap)
+{
+    logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
+    had_nonfatal_error = true;
+}
+
+void logv_error(const char *format, va_list ap)
+{
+    logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
+
+    if (log_error_atexit)
+        log_error_atexit();
+
+    throw log_execution_error_exception();
+}
+
 void log_always(const char *format, ...)
 {
     va_list ap;
@@ -156,7 +173,10 @@ void log_warning(const char *format, ...)
 {
     va_list ap;
     va_start(ap, format);
-    logv_prefixed("Warning: ", format, ap, LogLevel::WARNING_MSG);
+    if (log_warn_as_error)
+        logv_nonfatal_error(format, ap);
+    else
+        logv_prefixed("Warning: ", format, ap, LogLevel::WARNING_MSG);
     va_end(ap);
 }
 
@@ -164,12 +184,7 @@ void log_error(const char *format, ...)
 {
     va_list ap;
     va_start(ap, format);
-    logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
-
-    if (log_error_atexit)
-        log_error_atexit();
-
-    throw log_execution_error_exception();
+    logv_error(format, ap);
 }
 
 void log_break()
@@ -184,9 +199,8 @@ void log_nonfatal_error(const char *format, ...)
 {
     va_list ap;
     va_start(ap, format);
-    logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
+    logv_nonfatal_error(format, ap);
     va_end(ap);
-    had_nonfatal_error = true;
 }
 
 void log_flush()
diff --git a/common/kernel/log.h b/common/kernel/log.h
index 0ac4edf52c..cba539f4b9 100644
--- a/common/kernel/log.h
+++ b/common/kernel/log.h
@@ -63,6 +63,7 @@ extern log_write_type log_write_function;
 extern std::string log_last_error;
 extern void (*log_error_atexit)();
 extern bool had_nonfatal_error;
+extern bool log_warn_as_error;
 extern dict<LogLevel, int, loglevel_hash_ops> message_count_by_level;
 
 std::string stringf(const char *fmt, ...);

From 52b02f7377a1fc88a7e1678e57af803f4d1bcc0c Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 13 Feb 2023 12:49:00 +0000
Subject: [PATCH 269/712] machxo2: Fix Python bindings for pip iterators

---
 machxo2/arch_pybindings.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/machxo2/arch_pybindings.cc b/machxo2/arch_pybindings.cc
index 2ed686971a..3fcf721db6 100644
--- a/machxo2/arch_pybindings.cc
+++ b/machxo2/arch_pybindings.cc
@@ -54,8 +54,8 @@ void arch_wrap_python(py::module &m)
     readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
     readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
 
-    typedef const PipRange UphillPipRange;
-    typedef const PipRange DownhillPipRange;
+    typedef PipRange UphillPipRange;
+    typedef PipRange DownhillPipRange;
 
     typedef const std::vector<BelBucketId> &BelBucketRange;
     typedef const std::vector<BelId> &BelRangeForBelBucket;

From 57693bcb7f9140fc8587295e6af76be9b43b073c Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Tue, 14 Feb 2023 05:47:16 +0000
Subject: [PATCH 270/712] Update links to IceStorm in README

Fixes #1099.
---
 README.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 957be8899a..47201dc5bb 100644
--- a/README.md
+++ b/README.md
@@ -5,7 +5,7 @@ nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route
 tool.
 
 Currently nextpnr supports:
- * Lattice iCE40 devices supported by [Project IceStorm](http://bygone.clairexen.net/icestorm/)
+ * Lattice iCE40 devices supported by [Project IceStorm](https://github.com/YosysHQ/icestorm)
  * Lattice ECP5 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
  * Lattice Nexus devices supported by [Project Oxide](https://github.com/gatecat/prjoxide)
  * Gowin LittleBee devices supported by [Project Apicula](https://github.com/YosysHQ/apicula)
@@ -54,7 +54,7 @@ Getting started
 
 ### nextpnr-ice40
 
-For iCE40 support, install [Project IceStorm](http://bygone.clairexen.net/icestorm/) to `/usr/local` or another location, which should be passed as `-DICESTORM_INSTALL_PREFIX=/usr` to CMake. Then build and install `nextpnr-ice40` using the following commands:
+For iCE40 support, install [Project IceStorm](https://github.com/YosysHQ/icestorm) to `/usr/local` or another location, which should be passed as `-DICESTORM_INSTALL_PREFIX=/usr` to CMake. Then build and install `nextpnr-ice40` using the following commands:
 
 ```
 cmake . -DARCH=ice40
@@ -252,7 +252,7 @@ Links and references
 
 ### FPGA bitstream documentation (and tools) projects
 
-- [Project IceStorm (Lattice iCE40)](http://bygone.clairexen.net/icestorm/)
+- [Project IceStorm (Lattice iCE40)](https://github.com/YosysHQ/icestorm)
 - [Project Trellis (Lattice ECP5)](https://yosyshq.github.io/prjtrellis-db/)
 - [Project X-Ray (Xilinx 7-Series)](https://symbiflow.github.io/prjxray-db/)
 - [Project Chibi (Intel MAX-V)](https://github.com/rqou/project-chibi)

From 06b675b345ec0685fbef651d17cd0577df642e71 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 Feb 2023 11:10:51 +0100
Subject: [PATCH 271/712] fabulous: Add fake timings

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/arch.h                       |  7 +++--
 generic/viaduct/fabulous/fabulous.cc | 45 +++++++++++++++++++++++++---
 2 files changed, 46 insertions(+), 6 deletions(-)

diff --git a/generic/arch.h b/generic/arch.h
index 2a177be957..19a0a07805 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -316,8 +316,8 @@ struct Arch : BaseArch<ArchRanges>
 
     delay_t estimateDelay(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
-    delay_t getDelayEpsilon() const override { return 0.001; }
-    delay_t getRipupDelayPenalty() const override { return 0.015; }
+    delay_t getDelayEpsilon() const override { return delay_epsilon; }
+    delay_t getRipupDelayPenalty() const override { return ripup_penalty; }
     float getDelayNS(delay_t v) const override { return v; }
 
     delay_t getDelayFromNS(float ns) const override { return ns; }
@@ -397,6 +397,9 @@ struct Arch : BaseArch<ArchRanges>
     // Internal usage
     void assignArchInfo() override;
     bool cellsCompatible(const CellInfo **cells, int count) const;
+
+    float delay_epsilon = 0.001;
+    float ripup_penalty = 0.015;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 7dad0c66da..d3bfb4e272 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -69,7 +69,35 @@ struct FabulousImpl : ViaductAPI
         blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
         is_new_fab ? init_bels_v2() : init_bels_v1();
         init_pips();
-        ctx->setDelayScaling(0.25, 0.5);
+        ctx->setDelayScaling(2.0, 5.0);
+        ctx->delay_epsilon = 0.5;
+        ctx->ripup_penalty = 1.5;
+    }
+
+    void update_cell_timing(Context *ctx)
+    {
+        // These timings are not realistic. They just make sure nextpnr does some timing-driven optimisation...
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_FABULOUS_LC) {
+                auto &lct = cell_tags.get(ci);
+                if (lct.ff.ff_used) {
+                    ctx->addCellTimingClock(ci->name, id_CLK);
+                    for (unsigned i = 0; i < cfg.clb.lut_k; i++)
+                        ctx->addCellTimingSetupHold(ci->name, ctx->idf("I%d", i), id_CLK, 2.5, 0.1);
+                    ctx->addCellTimingClockToOut(ci->name, id_Q, id_CLK, 1.0);
+                } else {
+                    for (unsigned i = 0; i < cfg.clb.lut_k; i++)
+                        ctx->addCellTimingDelay(ci->name, ctx->idf("I%d", i), id_O, 3.0);
+                }
+            } else if (ci->type == id_OutPass4_frame_config) {
+                for (unsigned i = 0; i < 4; i++)
+                    ctx->addCellTimingSetupHold(ci->name, ctx->idf("I%d", i), id_CLK, 2.5, 0.1);
+            } else if (ci->type == id_InPass4_frame_config) {
+                for (unsigned i = 0; i < 4; i++)
+                    ctx->addCellTimingClockToOut(ci->name, ctx->idf("O%d", i), id_CLK, 2.5);
+            }
+        }
     }
 
     void pack() override { fabulous_pack(ctx, cfg); }
@@ -80,7 +108,11 @@ struct FabulousImpl : ViaductAPI
             fabulous_write_fasm(ctx, cfg, fasm_file);
     }
 
-    void prePlace() override { assign_cell_info(); }
+    void prePlace() override
+    {
+        assign_cell_info();
+        update_cell_timing(ctx);
+    }
     bool isBelLocationValid(BelId bel, bool explain_invalid) const override
     {
         return blk_trk->check_validity(bel, cfg, cell_tags);
@@ -122,7 +154,7 @@ struct FabulousImpl : ViaductAPI
     {
         const auto &src_data = ctx->wire_info(src);
         IdStringList pip_name = IdStringList::concat(ctx->getWireName(src), ctx->getWireName(dst));
-        ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(0.05), Loc(src_data.x, src_data.y, 0));
+        ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(1.0), Loc(src_data.x, src_data.y, 0));
     }
 
     void handle_bel_ports(BelId bel, IdString tile, IdString bel_type, const std::vector<parser_view> &ports)
@@ -138,6 +170,11 @@ struct FabulousImpl : ViaductAPI
                 ctx->addBelPin(bel, pin, port_wire, pin.in(id_I, id_T) ? PORT_IN : PORT_OUT);
             }
         } else if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) {
+            WireId clk_wire = get_wire(tile, id_CLK, id_REG_CLK);
+            if (ctx->wires.at(clk_wire.index).uphill.empty()) {
+                add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
+            }
+            ctx->addBelInput(bel, id_CLK, clk_wire);
             for (parser_view p : ports) {
                 IdString port_id = p.to_id(ctx);
                 WireId port_wire = get_wire(tile, port_id, port_id);
@@ -382,7 +419,7 @@ struct FabulousImpl : ViaductAPI
             WireId src_wire = get_wire(src_tile, src_port, src_port);
             WireId dst_wire = get_wire(dst_tile, dst_port, dst_port);
             ctx->addPip(IdStringList::concat(src_tile, pip_name), pip_name, src_wire, dst_wire,
-                        ctx->getDelayFromNS(0.01 * delay), tile_loc(src_tile));
+                        ctx->getDelayFromNS(0.05 * delay), tile_loc(src_tile));
         }
     }
 

From 32e818204eb73c77e333d1b07efa4db41a4f1183 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 16 Feb 2023 12:02:00 +0100
Subject: [PATCH 272/712] common: Print out generated seed value

---
 common/kernel/command.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 2fb4ee53c8..5f40ffab58 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -263,7 +263,9 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("randomize-seed")) {
         std::random_device randDev{};
         std::uniform_int_distribution<int> distrib{1};
-        ctx->rngseed(distrib(randDev));
+        auto seed = distrib(randDev);
+        ctx->rngseed(seed);
+        log_info("Generated random seed: %d\n", seed);
     }
 
     if (vm.count("slack_redist_iter")) {

From 16bcc51ffb8b3e4e8b7e81841a279d1d709f5479 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 Feb 2023 15:53:15 +0100
Subject: [PATCH 273/712] fabulous: Further tweak magic numbers

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabulous.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index d3bfb4e272..e58cf79285 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -69,9 +69,9 @@ struct FabulousImpl : ViaductAPI
         blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
         is_new_fab ? init_bels_v2() : init_bels_v1();
         init_pips();
-        ctx->setDelayScaling(2.0, 5.0);
-        ctx->delay_epsilon = 0.5;
-        ctx->ripup_penalty = 1.5;
+        ctx->setDelayScaling(3.0, 3.0);
+        ctx->delay_epsilon = 0.25;
+        ctx->ripup_penalty = 0.5;
     }
 
     void update_cell_timing(Context *ctx)

From 825d646196584a99818a408ad6155166a50c4c30 Mon Sep 17 00:00:00 2001
From: Thomas W Rodgers <rodgert@twrodgers.com>
Date: Sat, 18 Feb 2023 10:26:01 -0800
Subject: [PATCH 274/712] Include <cstdint> in common/kernel/hashlib.h

The definitions for uint32_t, uint64_t report as undefined when
compiling under GCC13. They were previously found by transitive
includes, but this is not guaranteed to work, and GCC13 forced
the issue.
---
 common/kernel/hashlib.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/kernel/hashlib.h b/common/kernel/hashlib.h
index 2f7357e25c..a3fcd4cabc 100644
--- a/common/kernel/hashlib.h
+++ b/common/kernel/hashlib.h
@@ -14,6 +14,7 @@
 
 #include <algorithm>
 #include <array>
+#include <cstdint>
 #include <stdexcept>
 #include <string>
 #include <vector>

From 61021a22ee37b5a4ae467017dddb0677a74ad6dc Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 21 Feb 2023 11:18:35 +0100
Subject: [PATCH 275/712] nexus: Check IO-bank compatibility

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/pack.cc | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 4b39542d81..4ebe68d1f1 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -607,6 +607,16 @@ struct NexusPacker
                 // Get IO type for reporting purposes
                 std::string io_type = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
 
+                bool is_wr_bel = (ctx->getBelType(bel) == id_SEIO33_CORE);
+                if (!ctx->io_types.count(io_type))
+                    log_error("IO '%s' has an unsupported IO type '%s'\n", ctx->nameOf(ci), io_type.c_str());
+                bool is_wr_io = (ctx->io_types.at(io_type).style & IOBANK_WR);
+                if (is_wr_io != is_wr_bel) {
+                    log_error("%s IO '%s' requires a %s bank but is placed on pin %s in a %s bank.\n", io_type.c_str(),
+                              ctx->nameOf(ci), (is_wr_io ? "wide-range" : "high-performance"), loc.c_str(),
+                              (is_wr_bel ? "wide-range" : "high-performance"));
+                }
+
                 if (ctx->is_io_type_diff(io_type)) {
                     // Convert from SEIO18 to DIFFIO18
                     if (ctx->getBelType(bel) != id_SEIO18_CORE)

From 0ed964247e8f3efba4a2569ddf7131b54736b632 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 21 Feb 2023 14:21:30 +0100
Subject: [PATCH 276/712] fabulous: Add support for packing carry chains

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc |   3 +
 generic/viaduct/fabulous/fasm.cc      |   4 +
 generic/viaduct/fabulous/pack.cc      | 125 +++++++++++++++++++++++---
 3 files changed, 122 insertions(+), 10 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index 1339635859..21c4746375 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -82,6 +82,7 @@ X(EN)
 X(BEL)
 X(PAD)
 X(LUT1)
+X(LUT4_HA)
 
 X(BelBegin)
 X(BelEnd)
@@ -96,3 +97,5 @@ X(M_AB)
 X(M_AD)
 X(M_EF)
 X(M_AH)
+
+X(I0MUX)
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index e4b95f6296..047ffcbd04 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -107,11 +107,15 @@ struct FabFasmWriter
         }
     }
 
+    void add_feature(const std::string &name) { out << prefix << name << std::endl; }
+
     void write_logic(const CellInfo *lc)
     {
         prefix = format_name(ctx->getBelName(lc->bel)) + ".";
         if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_COMB)) {
             write_int_vector_param(lc, "INIT", 0U, 1U << cfg.clb.lut_k); // todo lut depermute and thru
+            if (bool_or_default(lc->params, id_I0MUX, false))
+                add_feature("IOmux"); // typo in FABulous?
         }
         if (lc->type == id_FABULOUS_LC) {
             write_bool(lc, "FF");
diff --git a/generic/viaduct/fabulous/pack.cc b/generic/viaduct/fabulous/pack.cc
index 56a6f8559f..1040201659 100644
--- a/generic/viaduct/fabulous/pack.cc
+++ b/generic/viaduct/fabulous/pack.cc
@@ -25,6 +25,8 @@
 #include "viaduct_constids.h"
 #include "viaduct_helpers.h"
 
+#include "validity_check.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
@@ -36,6 +38,7 @@ struct FabulousPacker
 
     dict<IdString, unsigned> lut_types;
     std::vector<IdString> lut_inputs;
+    CellTagger cell_tags;
 
     FabulousPacker(Context *ctx, const FabricConfig &cfg) : ctx(ctx), cfg(cfg)
     {
@@ -44,6 +47,8 @@ struct FabulousPacker
             lut_types[ctx->idf("LUT%d", i + 1)] = i + 1;
             lut_inputs.push_back(ctx->idf("I%d", i));
         }
+        if (cfg.clb.lut_k == 4)
+            lut_types[id_LUT4_HA] = 4; // special case for now
         h.init(ctx);
     }
 
@@ -77,6 +82,16 @@ struct FabulousPacker
         }
     }
 
+    void assign_lc_info()
+    {
+        int flat_index = 0;
+        for (auto &cell : ctx->cells) {
+            cell.second->flat_index = flat_index++;
+            if (cell.second->type == id_FABULOUS_LC)
+                cell_tags.assign_for(ctx, cfg, cell.second.get());
+        }
+    }
+
     // Two-stage flipflop packing. First convert all the random primitives into a much easier-to-handle FABULOUS_FF
     // Then for split-LC mode, cluster it to connected LUTs; separate-LC mode, pack it into a connected or new LC
 
@@ -179,9 +194,34 @@ struct FabulousPacker
         }
     }
 
+    bool check_cluster_legality(CellInfo *lc) {
+        if (lc->cluster == ClusterId())
+            return true;
+        CLBState test_clb(cfg.clb);
+        auto process_cluster_cell = [&](CellInfo *ci) {
+            if (ci->constr_y != lc->constr_y)
+                return;
+            if (ci->type == id_FABULOUS_LC) {
+                NPNR_ASSERT(ci->constr_z >= 0 && ci->constr_z < int(cfg.clb.lc_per_clb));
+                test_clb.lc_comb[ci->constr_z] = ci;
+            }  else if (ci->type.in(id_FABULOUS_MUX2, id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
+                int mux_z = (ci->constr_z - cfg.clb.lc_per_clb - 1);
+                NPNR_ASSERT(mux_z >= 0 && mux_z < int(cfg.clb.lc_per_clb));
+                test_clb.mux[mux_z] = ci;
+            }
+            // TODO: non-split MODE
+        };
+        CellInfo *root = ctx->getClusterRootCell(lc->cluster);
+        process_cluster_cell(root);
+        for (auto child : root->constr_children)
+            process_cluster_cell(child);
+        return test_clb.check_validity(cfg.clb, cell_tags);
+    }
+
     void pack_ffs()
     {
         pool<IdString> to_delete;
+        assign_lc_info();
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type != id_FABULOUS_FF)
@@ -194,30 +234,43 @@ struct FabulousPacker
                 continue;
             if (!cfg.clb.split_lc && d->users.entries() > 1)
                 continue; // TODO: could also resolve by duplicating LUT
-            if (drv->cluster != ClusterId()) {
-                // TODO: actually we can pack these often, we just have to be more careful to check control sets
-                continue;
-            }
             // we can pack them together
             if (cfg.clb.split_lc) {
                 // create/modify cluster and add constraints. copy from an arch where we do this already...
                 NPNR_ASSERT_FALSE("unimplemented");
             } else {
-                to_delete.insert(ci->name);
-                // this connection is packed inside the LC
-                ci->disconnectPort(id_D);
-                drv->disconnectPort(id_O);
-                // move other ports/params
+                // move config ports/params, these affect control set for the legality set
                 ci->movePortTo(id_CLK, drv, id_CLK);
                 ci->movePortTo(id_SR, drv, id_SR);
                 ci->movePortTo(id_EN, drv, id_EN);
-                ci->movePortTo(id_O, drv, id_Q);
                 drv->params[id_NEG_CLK] = ci->params[id_NEG_CLK];
                 drv->params[id_ASYNC_SR] = ci->params[id_ASYNC_SR];
                 drv->params[id_SET_NORESET] = ci->params[id_SET_NORESET];
                 drv->params[id_FF] = 1;
+                // update tags for this cluster checks
+                cell_tags.assign_for(ctx, cfg, drv);
+                if (drv->cluster != ClusterId()) {
+                    if (!check_cluster_legality(drv)) {
+                        // If packing wasn't legal; revert half-finished move
+                        for (auto p : {id_NEG_CLK, id_SR, id_EN, id_FF})
+                            drv->params.erase(p);
+                        drv->movePortTo(id_CLK, ci, id_CLK);
+                        drv->movePortTo(id_SR, ci, id_SR);
+                        drv->movePortTo(id_EN, ci, id_EN);
+                        // revert tag changes too for this cluster checks
+                        cell_tags.assign_for(ctx, cfg, drv);
+                        continue;
+                    }
+                }
+                // this connection is packed inside the LC
+                to_delete.insert(ci->name);
+                ci->movePortTo(id_O, drv, id_Q);
+                ci->disconnectPort(id_D);
+                drv->disconnectPort(id_O);
                 for (auto &attr : ci->attrs)
                     drv->attrs[attr.first] = attr.second;
+                // update tags for future cluster checks
+                cell_tags.assign_for(ctx, cfg, drv);
             }
         }
         for (auto del : to_delete)
@@ -279,6 +332,57 @@ struct FabulousPacker
         h.remove_nextpnr_iobs(top_ports);
     }
 
+    void constrain_carries()
+    {
+        std::vector<CellInfo *> carry_roots;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (!ci->type.in(id_FABULOUS_LC, id_FABULOUS_COMB))
+                continue;
+            if (!ci->getPort(id_Ci) && ci->getPort(id_Co))
+                carry_roots.push_back(ci);
+            else if (ci->getPort(id_Ci) && ci->getPort(id_Ci)->driver.cell) {
+                auto &drv = ci->getPort(id_Ci)->driver;
+                if (drv.port != id_Co || !drv.cell->type.in(id_FABULOUS_LC, id_FABULOUS_COMB))
+                    log_error("Carry cell '%s' has Ci driven by illegal port '%s.%s'\n", ctx->nameOf(ci),
+                              ctx->nameOf(drv.cell), ctx->nameOf(drv.port));
+            }
+        }
+        for (auto root : carry_roots) {
+            CellInfo *cursor = root;
+            int dy = 0, dz = 0;
+            while (true) {
+                // create cluster
+                cursor->cluster = root->name;
+                cursor->constr_z = dz;
+                cursor->constr_abs_z = true;
+                if (cursor != root) {
+                    cursor->constr_x = 0;
+                    cursor->constr_y = -dy;
+                    root->constr_children.push_back(cursor);
+                }
+                NetInfo *co = cursor->getPort(id_Co);
+                if (co && !co->users.empty()) {
+                    if (co->users.entries() > 1)
+                        log_error("Carry cell '%s' has illegal multiple fanout on Co net '%s'\n", ctx->nameOf(cursor),
+                                  ctx->nameOf(co));
+                    auto &usr = *(co->users.begin());
+                    if (usr.port != id_Ci || !usr.cell->type.in(id_FABULOUS_LC, id_FABULOUS_COMB))
+                        log_error("Carry cell '%s' has illegal fanout '%s.%s' on Co net '%s'\n", ctx->nameOf(cursor),
+                                  ctx->nameOf(usr.cell), ctx->nameOf(usr.port), ctx->nameOf(co));
+                    cursor = usr.cell;
+                } else {
+                    break;
+                }
+                ++dz;
+                if (dz == int(cfg.clb.lc_per_clb)) {
+                    dz = 0;
+                    ++dy;
+                }
+            }
+        }
+    }
+
     void run()
     {
         update_bel_attrs();
@@ -287,6 +391,7 @@ struct FabulousPacker
         pack_luts();
         pack_muxes();
         prepare_ffs();
+        constrain_carries();
         pack_ffs();
     }
 };

From 4b4f4a7da11f5fb105b570741184e4fd559df5b9 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 23 Feb 2023 02:32:19 +0000
Subject: [PATCH 277/712] common: add missing includes for libc++.

---
 common/kernel/archcheck.cc | 2 ++
 common/kernel/embed.cc     | 1 +
 2 files changed, 3 insertions(+)

diff --git a/common/kernel/archcheck.cc b/common/kernel/archcheck.cc
index 23ec7aee26..06282f4318 100644
--- a/common/kernel/archcheck.cc
+++ b/common/kernel/archcheck.cc
@@ -17,6 +17,8 @@
  *
  */
 
+#include <list>
+
 #include "log.h"
 #include "nextpnr.h"
 
diff --git a/common/kernel/embed.cc b/common/kernel/embed.cc
index 70bbc6fbe3..6beb157be6 100644
--- a/common/kernel/embed.cc
+++ b/common/kernel/embed.cc
@@ -1,3 +1,4 @@
+#include <map>
 #if defined(WIN32)
 #include <windows.h>
 #endif

From 088c822e289cafaf1af991243d77522d0ee934c9 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 23 Feb 2023 02:37:47 +0000
Subject: [PATCH 278/712] CMake: check if warning flag is supported before use.

Clang 11 is failing on -Wno-format-truncation.
---
 CMakeLists.txt | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4d15f7243d..4fba12191f 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,6 +1,8 @@
 cmake_minimum_required(VERSION 3.13)
 project(nextpnr CXX C)
 
+include(CheckCXXCompilerFlag)
+
 # Allow family.cmake add additional dependencies to gui_${family}.
 cmake_policy(SET CMP0079 NEW)
 
@@ -134,7 +136,13 @@ if (MSVC)
     set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996 /wd4127")
 else()
     # N.B. the -Wno-array-bounds is to work around a false positive in GCC 9
-    set(WARN_FLAGS "-Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers -Wno-array-bounds -Wno-format-truncation")
+    set(WARN_FLAGS "-Wall -Wextra")
+    foreach(TRY_WARN_FLAG no-unused-parameter no-missing-field-initializers no-array-bounds no-format-truncation)
+        check_cxx_compiler_flag("-W${TRY_WARN_FLAG}" HAS_W${TRY_WARN_FLAG})
+        if (HAS_W${TRY_WARN_FLAG})
+            set(WARN_FLAGS "${WARN_FLAGS} -W${TRY_WARN_FLAG}")
+        endif()
+    endforeach()
     if (WERROR)
         set(WARN_FLAGS "${WARN_FLAGS} -Werror")
     endif()

From 8f0731edc99c828ffa850207c80cfb99651b6ae4 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 23 Feb 2023 03:14:42 +0000
Subject: [PATCH 279/712] common: update deprecated use of
 `boost::filesystem::basename`.

---
 common/kernel/command.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 5f40ffab58..8c8b5950b5 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -86,14 +86,14 @@ bool CommandHandler::parseOptions()
 bool CommandHandler::executeBeforeContext()
 {
     if (vm.count("help") || argc == 1) {
-        std::cerr << boost::filesystem::basename(argv[0])
+        std::cerr << boost::filesystem::path(argv[0]).stem()
                   << " -- Next Generation Place and Route (Version " GIT_DESCRIBE_STR ")\n";
         std::cerr << options << "\n";
         return argc != 1;
     }
 
     if (vm.count("version")) {
-        std::cerr << boost::filesystem::basename(argv[0])
+        std::cerr << boost::filesystem::path(argv[0]).stem()
                   << " -- Next Generation Place and Route (Version " GIT_DESCRIBE_STR ")\n";
         return true;
     }

From ebbaf8c08dbde251aa4f2809f296b20a7a2266a8 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 23 Feb 2023 03:25:48 +0000
Subject: [PATCH 280/712] common: disable parallel refinement only without
 threads.

Previously it was always disabled on WebAssembly builds.
---
 common/kernel/command.cc          | 2 +-
 common/place/detail_place_core.cc | 6 +++---
 common/place/detail_place_core.h  | 4 ++--
 common/place/parallel_refine.cc   | 4 ++--
 common/place/placer_heap.cc       | 2 +-
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 8c8b5950b5..68066af6cf 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -200,7 +200,7 @@ po::options_description CommandHandler::getGeneralOptions()
                           "allow placer to attempt up to max(10000, total cells^2 / N) iterations to place a cell (int "
                           "N, default: 8, 0 for no timeout)");
 
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
 #endif
 
diff --git a/common/place/detail_place_core.cc b/common/place/detail_place_core.cc
index 18118fc873..f21d6afdf7 100644
--- a/common/place/detail_place_core.cc
+++ b/common/place/detail_place_core.cc
@@ -219,7 +219,7 @@ bool DetailPlacerThreadState::bounds_check(BelId bel)
 
 bool DetailPlacerThreadState::bind_move()
 {
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
     std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
 #endif
     for (auto &entry : moved_cells) {
@@ -240,7 +240,7 @@ bool DetailPlacerThreadState::bind_move()
 
 bool DetailPlacerThreadState::check_validity()
 {
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
     std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
 #endif
     bool result = true;
@@ -263,7 +263,7 @@ void DetailPlacerThreadState::revert_move()
 {
     if (arch_state_dirty) {
         // If changes to the arch state were made, revert them by restoring original cell bindings
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
         std::unique_lock<std::shared_timed_mutex> l(g.archapi_mutex);
 #endif
         for (auto &entry : moved_cells) {
diff --git a/common/place/detail_place_core.h b/common/place/detail_place_core.h
index 1c280f24b7..aaca82f900 100644
--- a/common/place/detail_place_core.h
+++ b/common/place/detail_place_core.h
@@ -52,7 +52,7 @@ aborts the entire move transaction.
 
 #include <queue>
 
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
 #include <shared_mutex>
 #endif
 
@@ -98,7 +98,7 @@ struct DetailPlacerState
     wirelen_t total_wirelen = 0;
     double total_timing_cost = 0;
 
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
     std::shared_timed_mutex archapi_mutex;
 #endif
 
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index 0fb99be52b..da8ed4fc15 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -20,7 +20,7 @@
 #include "parallel_refine.h"
 #include "log.h"
 
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
 
 #include "detail_place_core.h"
 #include "scope_lock.h"
@@ -519,7 +519,7 @@ bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
 
 NEXTPNR_NAMESPACE_END
 
-#else /* !defined(__wasm) */
+#else /* !defined(NPNR_DISABLE_THREADS) */
 
 NEXTPNR_NAMESPACE_BEGIN
 
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 8ba5a70db5..2958405fe9 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -355,7 +355,7 @@ class HeAPPlacer
         ctx->check();
         lock.unlock_early();
 
-#if !defined(__wasm)
+#if !defined(NPNR_DISABLE_THREADS)
         if (cfg.parallelRefine) {
             if (!parallel_refine(ctx, ParallelRefineCfg(ctx))) {
                 return false;

From 1809e18c7bb23d88ddb716482d72b3ce195a1b35 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 23 Feb 2023 07:59:45 +0000
Subject: [PATCH 281/712] CMake: detect platform support for threads

---
 CMakeLists.txt | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4fba12191f..f48a894cee 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -44,28 +44,27 @@ endif()
 
 set(Boost_NO_BOOST_CMAKE ON)
 
+find_package(Threads)
+if (Threads_FOUND)
+    find_package(TBB QUIET)
+    if (TBB_FOUND)
+        add_definitions(-DNEXTPNR_USE_TBB)
+    endif()
+else()
+    add_definitions(-DNPNR_DISABLE_THREADS)
+endif()
+
 if(WASI)
     set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -lwasi-emulated-mman")
-    set(USE_THREADS OFF)
     add_definitions(
         -DBOOST_EXCEPTION_DISABLE
         -DBOOST_NO_EXCEPTIONS
-        -DBOOST_SP_NO_ATOMIC_ACCESS
-        -DBOOST_AC_DISABLE_THREADS
-        -DBOOST_NO_CXX11_HDR_MUTEX
     )
-else()
-    set(USE_THREADS ON)
-    find_package(TBB QUIET)
-    if (TBB_FOUND)
-        add_definitions(-DNEXTPNR_USE_TBB)
+    if (NOT Threads_FOUND)
+        add_definitions(-DBOOST_NO_CXX11_HDR_MUTEX)
     endif()
 endif()
 
-if (NOT USE_THREADS)
-    add_definitions(-DNPNR_DISABLE_THREADS)
-endif()
-
 set(link_param "")
 if (STATIC_BUILD)
     set(Boost_USE_STATIC_LIBS   ON)
@@ -168,7 +167,7 @@ find_package(Sanitizers)
 
 # List of Boost libraries to include
 set(boost_libs filesystem program_options iostreams system)
-if (USE_THREADS)
+if (Threads_FOUND)
     list(APPEND boost_libs thread)
 endif()
 

From 14050f991bc2e4ce2c6e7f431fe2acd4f0cf2a70 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 22 Feb 2023 14:51:51 +0100
Subject: [PATCH 282/712] fabulous: Global constant wires scheme

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc     | 10 +++
 generic/viaduct/fabulous/fabulous.cc      | 94 ++++++++++++++++++++++-
 generic/viaduct/fabulous/fasm.cc          | 25 ++++--
 generic/viaduct/fabulous/fasm.h           |  4 +-
 generic/viaduct/fabulous/pack.cc          |  9 +--
 generic/viaduct/fabulous/validity_check.h | 13 ++++
 6 files changed, 140 insertions(+), 15 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index 21c4746375..4299f4833f 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -99,3 +99,13 @@ X(M_EF)
 X(M_AH)
 
 X(I0MUX)
+
+X(GND0)
+X(GND)
+X(VCC0)
+X(VCC)
+X(VDD0)
+X(VDD)
+
+X(_CONST0_DRV)
+X(_CONST1_DRV)
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index e58cf79285..529d9ad08c 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -69,6 +69,7 @@ struct FabulousImpl : ViaductAPI
         blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
         is_new_fab ? init_bels_v2() : init_bels_v1();
         init_pips();
+        init_pseudo_constant_wires();
         ctx->setDelayScaling(3.0, 3.0);
         ctx->delay_epsilon = 0.25;
         ctx->ripup_penalty = 0.5;
@@ -105,7 +106,7 @@ struct FabulousImpl : ViaductAPI
     void postRoute() override
     {
         if (!fasm_file.empty())
-            fabulous_write_fasm(ctx, cfg, fasm_file);
+            fabulous_write_fasm(ctx, cfg, pp_tags, fasm_file);
     }
 
     void prePlace() override
@@ -150,11 +151,18 @@ struct FabulousImpl : ViaductAPI
 
     pool<IdString> warned_beltypes;
 
-    void add_pseudo_pip(WireId src, WireId dst, IdString pip_type)
+    std::vector<PseudoPipTags> pp_tags;
+
+    void add_pseudo_pip(WireId src, WireId dst, IdString pip_type, float delay = 1.0,
+                        PseudoPipTags tags = PseudoPipTags())
     {
         const auto &src_data = ctx->wire_info(src);
         IdStringList pip_name = IdStringList::concat(ctx->getWireName(src), ctx->getWireName(dst));
-        ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(1.0), Loc(src_data.x, src_data.y, 0));
+        PipId idx =
+                ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(delay), Loc(src_data.x, src_data.y, 0));
+        if (idx.index >= int(pp_tags.size()))
+            pp_tags.resize(idx.index + 1);
+        pp_tags.at(idx.index) = tags;
     }
 
     void handle_bel_ports(BelId bel, IdString tile, IdString bel_type, const std::vector<parser_view> &ports)
@@ -405,6 +413,7 @@ struct FabulousImpl : ViaductAPI
         }
     }
 
+    int max_x = 0, max_y = 0;
     void init_pips()
     {
         std::ifstream in = open_data_rel(is_new_fab ? "/.FABulous/pips.txt" : "/npnroutput/pips.txt");
@@ -418,8 +427,11 @@ struct FabulousImpl : ViaductAPI
             IdString pip_name = csv.next_field().to_id(ctx);
             WireId src_wire = get_wire(src_tile, src_port, src_port);
             WireId dst_wire = get_wire(dst_tile, dst_port, dst_port);
+            Loc loc = tile_loc(src_tile);
+            max_x = std::max(loc.x, max_x);
+            max_y = std::max(loc.y, max_y);
             ctx->addPip(IdStringList::concat(src_tile, pip_name), pip_name, src_wire, dst_wire,
-                        ctx->getDelayFromNS(0.05 * delay), tile_loc(src_tile));
+                        ctx->getDelayFromNS(0.05 * delay), loc);
         }
     }
 
@@ -455,6 +467,67 @@ struct FabulousImpl : ViaductAPI
         return ctx->addWire(wire_name, type, loc.x, loc.y);
     }
 
+    void init_pseudo_constant_wires()
+    {
+        for (int y = 0; y <= max_y; y++) {
+            for (int x = 0; x <= max_x; x++) {
+                for (int c = 0; c <= 1; c++) {
+                    IdString name = ctx->idf("$CONST%d", c);
+                    IdString tile = ctx->idf("X%dY%d", x, y);
+                    WireId const_wire = get_wire(tile, name, name);
+                    // Driver bel; always at 0;0
+                    if (x == 0 && y == 0) {
+                        int z = 0;
+                        while (ctx->bel_by_loc.count(Loc(x, y, z)))
+                            z++;
+                        BelId const_driver = ctx->addBel(IdStringList::concat(tile, ctx->idf("_CONST%d_DRV", c)),
+                                                         ctx->idf("_CONST%d_DRV", c), Loc(x, y, z), true, true);
+                        ctx->addBelInput(const_driver, id_O, const_wire);
+                    }
+                    if (x > 0) {
+                        // 'right' pip
+                        WireId prev_wire = get_wire(ctx->idf("X%dY%d", 0, y), name, name);
+                        add_pseudo_pip(prev_wire, const_wire, name, 0.1);
+                    }
+                    if (y > 0) {
+                        // 'down' pip
+                        WireId prev_wire = get_wire(ctx->idf("X%dY%d", x, 0), name, name);
+                        add_pseudo_pip(prev_wire, const_wire, name, 0.1);
+                    }
+                }
+            }
+        }
+        // LUTs can act as constant drivers if they aren't used.
+        // To avoid an exorbitant number of pips, only do this for the first LUT in a tile
+        // This pip will only be enabled if the LUT isn't used
+        for (BelId bel : ctx->getBels()) {
+            if (!ctx->getBelType(bel).in(id_FABULOUS_LC, id_FABULOUS_COMB))
+                continue;
+            Loc loc = ctx->getBelLocation(bel);
+            WireId o = ctx->getBelPinWire(bel, id_O);
+            for (int c = 0; c <= 1; c++) {
+                IdString const_name = ctx->idf("$CONST%d", c);
+                WireId const_wire = get_wire(ctx->idf("X%dY%d", loc.x, loc.y), const_name, const_name);
+                add_pseudo_pip(const_wire, o, const_name, 0.1, PseudoPipTags(PseudoPipTags::LUT_CONST, bel, c));
+            }
+        }
+        // We can also have dedicated constant wires in the fabric
+        for (WireId wire : ctx->getWires()) {
+            auto &wire_data = ctx->wire_info(wire);
+            IdString name_suffix = wire_data.name[1];
+            int const_val = -1;
+            if (name_suffix.in(id_GND, id_GND0))
+                const_val = 0;
+            else if (name_suffix.in(id_VCC, id_VCC0, id_VDD, id_VDD0))
+                const_val = 1;
+            else
+                continue;
+            IdString const_name = ctx->idf("$CONST%d", const_val);
+            WireId const_wire = get_wire(ctx->idf("X%dY%d", wire_data.x, wire_data.y), const_name, const_name);
+            add_pseudo_pip(const_wire, wire, const_name, 0.1);
+        }
+    }
+
     CellTagger cell_tags;
     void assign_cell_info()
     {
@@ -467,6 +540,19 @@ struct FabulousImpl : ViaductAPI
         CellInfo *old = ctx->getBoundBelCell(bel);
         blk_trk->update_bel(bel, old, cell);
     }
+
+    bool checkPipAvail(PipId pip) const override
+    {
+        if (pip.index >= int(pp_tags.size()))
+            return true;
+        const auto &tags = pp_tags.at(pip.index);
+        if (tags.type == PseudoPipTags::LUT_CONST) {
+            return ctx->checkBelAvail(tags.bel);
+        } else {
+            // TODO: LUT permuation pseudopips
+            return true;
+        }
+    }
 };
 
 struct FabulousArch : ViaductArch
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index 047ffcbd04..4d09d53778 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -34,8 +34,9 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace {
 struct FabFasmWriter
 {
-    FabFasmWriter(const Context *ctx, const FabricConfig &cfg, const std::string &filename)
-            : ctx(ctx), cfg(cfg), out(filename)
+    FabFasmWriter(const Context *ctx, const FabricConfig &cfg, const std::vector<PseudoPipTags> &pip_tags,
+                  const std::string &filename)
+            : ctx(ctx), cfg(cfg), pip_tags(pip_tags), out(filename)
     {
         if (!out)
             log_error("failed to open fasm file '%s' for writing\n", filename.c_str());
@@ -53,7 +54,19 @@ struct FabFasmWriter
     void write_pip(PipId pip)
     {
         auto &data = ctx->pip_info(pip);
-        if (data.type.in(id_global_clock, id_O2Q))
+        if (pip.index < int(pip_tags.size()) && pip_tags.at(pip.index).type != PseudoPipTags::NONE) {
+            // pseudo PIP
+            const auto &tag = pip_tags.at(pip.index);
+            if (tag.type == PseudoPipTags::LUT_CONST) {
+                NPNR_ASSERT(ctx->checkBelAvail(tag.bel));
+                prefix = format_name(ctx->getBelName(tag.bel)) + ".";
+                write_int_vector(stringf("INIT[%d:0]", (1U << cfg.clb.lut_k) - 1), 0, 1U << cfg.clb.lut_k,
+                                 (tag.data & 0x1));
+                prefix = "";
+            }
+            return;
+        }
+        if (data.type.in(id_global_clock, id_O2Q) || data.type.c_str(ctx)[0] == '$')
             return; // pseudo-pips with no underlying bitstream bits
         // write pip name but with '.' instead of '/' for separator
         out << format_name(data.name) << std::endl;
@@ -194,13 +207,15 @@ struct FabFasmWriter
 
     const Context *ctx;
     const FabricConfig &cfg;
+    const std::vector<PseudoPipTags> &pip_tags;
     std::ofstream out;
 };
 } // namespace
 
-void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::string &filename)
+void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::vector<PseudoPipTags> &pip_tags,
+                         const std::string &filename)
 {
-    FabFasmWriter wr(ctx, cfg, filename);
+    FabFasmWriter wr(ctx, cfg, pip_tags, filename);
     wr.write_fasm();
 }
 
diff --git a/generic/viaduct/fabulous/fasm.h b/generic/viaduct/fabulous/fasm.h
index 0f152c64cc..90b10f2ab5 100644
--- a/generic/viaduct/fabulous/fasm.h
+++ b/generic/viaduct/fabulous/fasm.h
@@ -22,10 +22,12 @@
 
 #include "fab_cfg.h"
 #include "nextpnr.h"
+#include "validity_check.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::string &filename);
+void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::vector<PseudoPipTags> &pip_tags,
+                         const std::string &filename);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/generic/viaduct/fabulous/pack.cc b/generic/viaduct/fabulous/pack.cc
index 1040201659..629b000e49 100644
--- a/generic/viaduct/fabulous/pack.cc
+++ b/generic/viaduct/fabulous/pack.cc
@@ -194,7 +194,8 @@ struct FabulousPacker
         }
     }
 
-    bool check_cluster_legality(CellInfo *lc) {
+    bool check_cluster_legality(CellInfo *lc)
+    {
         if (lc->cluster == ClusterId())
             return true;
         CLBState test_clb(cfg.clb);
@@ -204,7 +205,7 @@ struct FabulousPacker
             if (ci->type == id_FABULOUS_LC) {
                 NPNR_ASSERT(ci->constr_z >= 0 && ci->constr_z < int(cfg.clb.lc_per_clb));
                 test_clb.lc_comb[ci->constr_z] = ci;
-            }  else if (ci->type.in(id_FABULOUS_MUX2, id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
+            } else if (ci->type.in(id_FABULOUS_MUX2, id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
                 int mux_z = (ci->constr_z - cfg.clb.lc_per_clb - 1);
                 NPNR_ASSERT(mux_z >= 0 && mux_z < int(cfg.clb.lc_per_clb));
                 test_clb.mux[mux_z] = ci;
@@ -317,9 +318,7 @@ struct FabulousPacker
 
     void handle_constants()
     {
-        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0x3, 2)}};
-        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0, 2)}};
-        h.replace_constants(CellTypePort(id_LUT1, id_O), CellTypePort(id_LUT1, id_O), vcc_params, gnd_params);
+        h.replace_constants(CellTypePort(id__CONST1_DRV, id_O), CellTypePort(id__CONST0_DRV, id_O), {}, {});
     }
 
     void handle_io()
diff --git a/generic/viaduct/fabulous/validity_check.h b/generic/viaduct/fabulous/validity_check.h
index 43291f6eec..1f21e07b58 100644
--- a/generic/viaduct/fabulous/validity_check.h
+++ b/generic/viaduct/fabulous/validity_check.h
@@ -122,6 +122,19 @@ struct BlockTracker
     bool check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data);
 };
 
+struct PseudoPipTags
+{
+    BelId bel;
+    enum PPType : uint16_t
+    {
+        NONE,
+        LUT_CONST,
+        LUT_PERM,
+    } type;
+    uint16_t data;
+    PseudoPipTags(PPType type = NONE, BelId bel = BelId(), uint16_t data = 0x0) : bel(bel), type(type), data(data) {}
+};
+
 NEXTPNR_NAMESPACE_END
 
 #endif

From 26fcf349ad9ef65e4f0758c7bb4a24d5a8b45bf7 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 23 Feb 2023 15:19:00 +0100
Subject: [PATCH 283/712] fabulous: LUT permutation support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc      |  3 ++
 generic/viaduct/fabulous/fabulous.cc       | 57 ++++++++++++++++++++++
 generic/viaduct/fabulous/fasm.cc           | 42 +++++++++++++++-
 generic/viaduct/fabulous/validity_check.cc |  2 +-
 4 files changed, 102 insertions(+), 2 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index 4299f4833f..7c8c340078 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -109,3 +109,6 @@ X(VDD)
 
 X(_CONST0_DRV)
 X(_CONST1_DRV)
+
+X(_LUT_PERM)
+X(_LUT_PERM_IN)
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 529d9ad08c..3400be9ac8 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -70,6 +70,7 @@ struct FabulousImpl : ViaductAPI
         is_new_fab ? init_bels_v2() : init_bels_v1();
         init_pips();
         init_pseudo_constant_wires();
+        setup_lut_permutation();
         ctx->setDelayScaling(3.0, 3.0);
         ctx->delay_epsilon = 0.25;
         ctx->ripup_penalty = 0.5;
@@ -435,6 +436,46 @@ struct FabulousImpl : ViaductAPI
         }
     }
 
+    void remove_bel_pin(BelId bel, IdString pin)
+    {
+        auto &bel_data = ctx->bel_info(bel);
+        auto &wire_data = ctx->wire_info(ctx->getBelPinWire(bel, pin));
+        std::vector<BelPin> new_wire_pins;
+        for (const auto &wire_pin : wire_data.bel_pins) {
+            if (wire_pin.bel == bel && wire_pin.pin == pin)
+                continue;
+            new_wire_pins.push_back(wire_pin);
+        }
+        wire_data.bel_pins = new_wire_pins;
+        bel_data.pins.erase(pin);
+    }
+
+    void setup_lut_permutation()
+    {
+        for (auto bel : ctx->getBels()) {
+            auto &bel_data = ctx->bel_info(bel);
+            if (!bel_data.type.in(id_FABULOUS_LC, id_FABULOUS_COMB))
+                continue;
+            std::vector<WireId> orig_inputs, new_inputs;
+            for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
+                // Rewire the LUT input to a permutation pseudo-wire
+                IdString pin = ctx->idf("I%d", i);
+                orig_inputs.push_back(ctx->getBelPinWire(bel, pin));
+                remove_bel_pin(bel, pin);
+                WireId in_wire = get_wire(bel_data.name[0], ctx->idf("%s_PERM_I%d", bel_data.name[1].c_str(ctx), i),
+                                          id__LUT_PERM_IN);
+                ctx->addBelInput(bel, pin, in_wire);
+                new_inputs.push_back(in_wire);
+            }
+            for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
+                for (unsigned j = 0; j < cfg.clb.lut_k; j++) {
+                    add_pseudo_pip(orig_inputs.at(i), new_inputs.at(j), id__LUT_PERM, 0.1,
+                                   PseudoPipTags(PseudoPipTags::LUT_PERM, bel, ((i << 4) | j)));
+                }
+            }
+        }
+    }
+
     // Fast lookup of tile names to XY pairs
     dict<IdString, Loc> tile2loc;
     Loc tile_loc(IdString tile)
@@ -548,6 +589,22 @@ struct FabulousImpl : ViaductAPI
         const auto &tags = pp_tags.at(pip.index);
         if (tags.type == PseudoPipTags::LUT_CONST) {
             return ctx->checkBelAvail(tags.bel);
+        } else if (tags.type == PseudoPipTags::LUT_PERM) {
+            uint8_t from = (tags.data >> 4) & 0xF, to = (tags.data & 0xF);
+            if (from == to)
+                return true;
+            const CellInfo *lut = ctx->getBoundBelCell(tags.bel);
+            if (!lut)
+                return true;
+            bool is_carry = cell_tags.get(lut).comb.carry_used;
+            if (is_carry) {
+                // Because you have to make sure you route _something_ to each HA input in this mode (undefined I1/I2 inputs aren't OK)
+                // and you also can't swap I0 because it's fixed internally
+                // LUT permutation in carry mode is just more trouble than it's worth.
+                return false;
+            } else {
+                return true; // TODO: other cases where perm illegal; e.g. LUTRAM
+            }
         } else {
             // TODO: LUT permuation pseudopips
             return true;
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index 4d09d53778..159bb8ff0b 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -122,11 +122,51 @@ struct FabFasmWriter
 
     void add_feature(const std::string &name) { out << prefix << name << std::endl; }
 
+    uint64_t depermute_lut(const CellInfo *lut)
+    {
+        uint64_t orig_init = int_or_default(lut->params, id_INIT, 0);
+        std::vector<std::vector<unsigned>> phys_to_log;
+        phys_to_log.resize(cfg.clb.lut_k);
+        for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
+            WireId pin_wire = ctx->getBelPinWire(lut->bel, ctx->idf("I%d", i));
+            for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+                if (!ctx->getBoundPipNet(pip))
+                    continue;
+                unsigned pip_data = pip_tags.at(pip.index).data;
+                unsigned from_pin = (pip_data >> 4) & 0xF;
+                unsigned to_pin = (pip_data)&0xF;
+                NPNR_ASSERT(to_pin == i);
+                phys_to_log[from_pin].push_back(i);
+            }
+        }
+        if (bool_or_default(lut->params, id_I0MUX, false)) // internal, hardcoded
+            phys_to_log[0].push_back(0);
+        for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
+            for (auto j : phys_to_log.at(i))
+                out << stringf(" # permute phys %d log %d\n", i, j);
+        }
+        uint64_t permuted_init = 0;
+        for (unsigned i = 0; i < (1U << cfg.clb.lut_k); i++) {
+            unsigned log_idx = 0;
+            for (unsigned j = 0; j < cfg.clb.lut_k; j++) {
+                if ((i >> j) & 0x1) {
+                    for (auto log_pin : phys_to_log[j])
+                        log_idx |= (1 << log_pin);
+                }
+            }
+            if ((orig_init >> log_idx) & 0x1)
+                permuted_init |= (uint64_t(1U) << i);
+        }
+        return permuted_init;
+    }
+
     void write_logic(const CellInfo *lc)
     {
         prefix = format_name(ctx->getBelName(lc->bel)) + ".";
         if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_COMB)) {
-            write_int_vector_param(lc, "INIT", 0U, 1U << cfg.clb.lut_k); // todo lut depermute and thru
+            uint64_t init = depermute_lut(lc);
+            unsigned width = 1U << cfg.clb.lut_k;
+            write_int_vector(stringf("INIT[%d:0]", width - 1), init, width); // todo lut depermute and thru
             if (bool_or_default(lc->params, id_I0MUX, false))
                 add_feature("IOmux"); // typo in FABulous?
         }
diff --git a/generic/viaduct/fabulous/validity_check.cc b/generic/viaduct/fabulous/validity_check.cc
index 30b21f2990..81f057c8f6 100644
--- a/generic/viaduct/fabulous/validity_check.cc
+++ b/generic/viaduct/fabulous/validity_check.cc
@@ -53,7 +53,7 @@ void CellTagger::assign_for(const Context *ctx, const FabricConfig &cfg, const C
             const NetInfo *sig = ci->getPort(ctx->idf("I%d", i));
             t.comb.lut_inputs[i] = sig ? sig->name : IdString();
         }
-        t.comb.carry_used = false; // TODO
+        t.comb.carry_used = ci->getPort(id_Ci) || ci->getPort(id_Co); // TODO
         t.comb.lut_out = ci->getPort(id_O);
     }
     if (ci->type.in(id_FABULOUS_FF, id_FABULOUS_LC)) {

From 5d0aa7786173d698433c2b89634156e2c3928923 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 23 Feb 2023 15:36:28 +0100
Subject: [PATCH 284/712] fabulous: Add timing model for carries

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabulous.cc | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 3400be9ac8..f3d0878c1d 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -83,14 +83,21 @@ struct FabulousImpl : ViaductAPI
             CellInfo *ci = cell.second.get();
             if (ci->type == id_FABULOUS_LC) {
                 auto &lct = cell_tags.get(ci);
+                if (lct.comb.carry_used) {
+                    ctx->addCellTimingDelay(ci->name, id_Ci, id_Co, 1.0);
+                }
                 if (lct.ff.ff_used) {
                     ctx->addCellTimingClock(ci->name, id_CLK);
                     for (unsigned i = 0; i < cfg.clb.lut_k; i++)
                         ctx->addCellTimingSetupHold(ci->name, ctx->idf("I%d", i), id_CLK, 2.5, 0.1);
                     ctx->addCellTimingClockToOut(ci->name, id_Q, id_CLK, 1.0);
+                    if (bool_or_default(ci->params, id_I0MUX))
+                        ctx->addCellTimingSetupHold(ci->name, id_Ci, id_CLK, 2.5, 0.1);
                 } else {
                     for (unsigned i = 0; i < cfg.clb.lut_k; i++)
                         ctx->addCellTimingDelay(ci->name, ctx->idf("I%d", i), id_O, 3.0);
+                    if (bool_or_default(ci->params, id_I0MUX))
+                        ctx->addCellTimingDelay(ci->name, id_Ci, id_O, 3.0);
                 }
             } else if (ci->type == id_OutPass4_frame_config) {
                 for (unsigned i = 0; i < 4; i++)
@@ -610,6 +617,19 @@ struct FabulousImpl : ViaductAPI
             return true;
         }
     }
+
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override
+    {
+        if (src_pin == id_Ci && dst_pin == id_Co)
+            return 0.5;
+
+        auto driver_loc = ctx->getBelLocation(src_bel);
+        auto sink_loc = ctx->getBelLocation(dst_bel);
+
+        int dx = abs(sink_loc.x - driver_loc.x);
+        int dy = abs(sink_loc.y - driver_loc.y);
+        return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
+    }
 };
 
 struct FabulousArch : ViaductArch

From 1dcc2f777d644e1013a89da521f5d4c0d909e486 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 28 Feb 2023 18:27:13 +0100
Subject: [PATCH 285/712] ice40: Add python binding for write_bitstream

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/arch_pybindings.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 24e901328e..09fcff3c95 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -21,11 +21,23 @@
 #ifndef NO_PYTHON
 
 #include "arch_pybindings.h"
+#include "bitstream.h"
+#include "log.h"
 #include "nextpnr.h"
 #include "pybindings.h"
 
+#include <fstream>
+
 NEXTPNR_NAMESPACE_BEGIN
 
+static void write_bitstream(const Context *ctx, std::string asc_file)
+{
+    std::ofstream out(asc_file);
+    if (!out)
+        log_error("Failed to open output file %s\n", asc_file.c_str());
+    write_asc(ctx, out);
+}
+
 void arch_wrap_python(py::module &m)
 {
     using namespace PythonConversion;
@@ -85,6 +97,8 @@ void arch_wrap_python(py::module &m)
     WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
     WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
     WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
+
+    m.def("write_bitstream", &write_bitstream);
 }
 
 NEXTPNR_NAMESPACE_END

From cdd7bb676fbb060c63ed2d0e285b3bdf324a5107 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 27 Feb 2023 09:04:11 +0100
Subject: [PATCH 286/712] fabulous: Support for complex flops in PnR

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc      |  3 +++
 generic/viaduct/fabulous/fab_cfg.h         |  3 ++-
 generic/viaduct/fabulous/fabulous.cc       | 24 +++++++++++++++++++---
 generic/viaduct/fabulous/validity_check.cc | 11 ++++++++++
 4 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index 7c8c340078..b7fe721d22 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -110,5 +110,8 @@ X(VDD)
 X(_CONST0_DRV)
 X(_CONST1_DRV)
 
+X(_CONST0)
+X(_CONST1)
+
 X(_LUT_PERM)
 X(_LUT_PERM_IN)
diff --git a/generic/viaduct/fabulous/fab_cfg.h b/generic/viaduct/fabulous/fab_cfg.h
index dc487fbddd..17f066cc54 100644
--- a/generic/viaduct/fabulous/fab_cfg.h
+++ b/generic/viaduct/fabulous/fab_cfg.h
@@ -43,8 +43,9 @@ struct ControlSetConfig
     signal can drive for a CLB with 8 FFs and 2 clocks split at halfway, the first entry would be 0x0F and the second
     0xF0
     */
-    std::vector<route_mask_t> routing = {0b11111111}; // default 1 shared between all
+    std::vector<route_mask_t> routing; // default 1 shared between all
     bool have_signal = true;
+    int can_mask = -1;
     bool can_invert = false;
 };
 
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index f3d0878c1d..d658ce2460 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -52,6 +52,7 @@ struct FabulousImpl : ViaductAPI
                 log_error("unrecognised fabulous option '%s'\n", a.first.c_str());
         }
     }
+
     ~FabulousImpl(){};
     void init(Context *ctx) override
     {
@@ -64,6 +65,7 @@ struct FabulousImpl : ViaductAPI
         else
             is_new_fab = false;
         log_info("Detected FABulous %s format project.\n", is_new_fab ? "2.0" : "1.0");
+        init_default_ctrlset_cfg();
         // To consider: a faster serialised form of the device data (like bba that other arches use) so we don't have to
         // go through the whole csv parsing malarkey each time
         blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
@@ -76,6 +78,22 @@ struct FabulousImpl : ViaductAPI
         ctx->ripup_penalty = 0.5;
     }
 
+    void init_default_ctrlset_cfg()
+    {
+        // TODO: loading from file or something
+        uint64_t default_routing = (1ULL << (cfg.clb.lc_per_clb * cfg.clb.ff_per_lc)) - 1;
+        auto setup_cfg = [&](ControlSetConfig &ctrl, int mask) {
+            ctrl.routing.clear();
+            ctrl.routing.push_back(default_routing);
+            ctrl.can_mask = mask;
+            ctrl.can_invert = false;
+        };
+
+        setup_cfg(cfg.clb.clk, -1);
+        setup_cfg(cfg.clb.en, 1);
+        setup_cfg(cfg.clb.sr, 0);
+    }
+
     void update_cell_timing(Context *ctx)
     {
         // These timings are not realistic. They just make sure nextpnr does some timing-driven optimisation...
@@ -605,9 +623,9 @@ struct FabulousImpl : ViaductAPI
                 return true;
             bool is_carry = cell_tags.get(lut).comb.carry_used;
             if (is_carry) {
-                // Because you have to make sure you route _something_ to each HA input in this mode (undefined I1/I2 inputs aren't OK)
-                // and you also can't swap I0 because it's fixed internally
-                // LUT permutation in carry mode is just more trouble than it's worth.
+                // Because you have to make sure you route _something_ to each HA input in this mode (undefined I1/I2
+                // inputs aren't OK) and you also can't swap I0 because it's fixed internally LUT permutation in carry
+                // mode is just more trouble than it's worth.
                 return false;
             } else {
                 return true; // TODO: other cases where perm illegal; e.g. LUTRAM
diff --git a/generic/viaduct/fabulous/validity_check.cc b/generic/viaduct/fabulous/validity_check.cc
index 81f057c8f6..10b67c3e92 100644
--- a/generic/viaduct/fabulous/validity_check.cc
+++ b/generic/viaduct/fabulous/validity_check.cc
@@ -62,6 +62,10 @@ void CellTagger::assign_for(const Context *ctx, const FabricConfig &cfg, const C
             auto get_ctrlsig = [&](IdString name) {
                 const NetInfo *sig = ci->getPort(name);
                 bool invert = sig && bool_or_default(ci->params, ctx->idf("NEG_%s", name.c_str(ctx)));
+                if (sig && sig->driver.cell && sig->driver.cell->type.in(id__CONST0_DRV, id__CONST1_DRV)) {
+                    return ControlSig(((sig->driver.cell->type == id__CONST1_DRV) ^ invert) ? id__CONST1 : id__CONST0,
+                                      false);
+                }
                 return ControlSig(sig ? sig->name : id___disconnected, invert);
             };
             t.ff.clk = get_ctrlsig(id_CLK);
@@ -132,6 +136,13 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
             used_en(cfg.en.routing.size());
     auto check_ctrlsig = [&](unsigned idx, ControlSig actual, const ControlSetConfig &ctrl,
                              SSOArray<ControlSig, 2> &used) {
+        if (ctrl.can_mask != -1) {
+            // Using the per-entry control signal masking
+            if (actual.net == id___disconnected || (actual.net == id__CONST0 && ctrl.can_mask == 0) ||
+                (actual.net == id__CONST1 && ctrl.can_mask == 0)) {
+                return true;
+            }
+        }
         // see if we have an already-matching signal available
         for (unsigned i = 0; i < ctrl.routing.size(); i++) {
             // doesn't route to this pin

From 2f509734dff676b7543a574b64a46be4224a5aa4 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 27 Feb 2023 10:38:25 +0100
Subject: [PATCH 287/712] fabulous: Misc improvements

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc |  1 +
 generic/viaduct/fabulous/fabulous.cc  |  6 ++++--
 generic/viaduct/fabulous/fasm.cc      | 19 +++++++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index b7fe721d22..861eedf2bf 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -115,3 +115,4 @@ X(_CONST1)
 
 X(_LUT_PERM)
 X(_LUT_PERM_IN)
+X(I_reg)
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index d658ce2460..00c8909b9b 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -102,7 +102,9 @@ struct FabulousImpl : ViaductAPI
             if (ci->type == id_FABULOUS_LC) {
                 auto &lct = cell_tags.get(ci);
                 if (lct.comb.carry_used) {
-                    ctx->addCellTimingDelay(ci->name, id_Ci, id_Co, 1.0);
+                    ctx->addCellTimingDelay(ci->name, id_Ci, id_Co, 0.2);
+                    ctx->addCellTimingDelay(ci->name, ctx->id("I1"), id_Co, 1.0);
+                    ctx->addCellTimingDelay(ci->name, ctx->id("I2"), id_Co, 1.0);
                 }
                 if (lct.ff.ff_used) {
                     ctx->addCellTimingClock(ci->name, id_CLK);
@@ -638,7 +640,7 @@ struct FabulousImpl : ViaductAPI
 
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override
     {
-        if (src_pin == id_Ci && dst_pin == id_Co)
+        if (src_pin == id_Co && dst_pin == id_Ci)
             return 0.5;
 
         auto driver_loc = ctx->getBelLocation(src_bel);
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index 159bb8ff0b..f1c0c64858 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -223,6 +223,23 @@ struct FabFasmWriter
         }
     }
 
+    void write_iopass(const CellInfo *ci)
+    {
+        Loc loc = ctx->getBelLocation(ci->bel);
+        // We use 'nice' names based on function for the IOPass bels inside nextpnr
+        // but in the bitstream we need to use character names
+        NPNR_ASSERT(loc.z <= 26);
+        prefix = stringf("X%dY%d.%c.", loc.x, loc.y, 'A' + loc.z);
+        if (ci->params.count(id_I_reg)) {
+            uint64_t regval = int_or_default(ci->params, id_I_reg);
+            for (unsigned i = 0; i < 4; i++) {
+                if (regval & (1 << i))
+                    out << prefix << stringf("I%d_reg", i) << std::endl;
+            }
+        }
+        prefix = "";
+    }
+
     void write_cell(const CellInfo *ci)
     {
         out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl;
@@ -231,6 +248,8 @@ struct FabFasmWriter
             write_logic(ci);
         else if (ci->type == id_IO_1_bidirectional_frame_config_pass)
             write_io(ci);
+        else if (ci->type.in(id_InPass4_frame_config, id_OutPass4_frame_config))
+            write_iopass(ci);
         else
             write_generic_cell(ci);
         // TODO: other cell types

From 132a98a91db2771efd8cba40399950bcb0fb5f07 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 6 Mar 2023 09:07:42 +0100
Subject: [PATCH 288/712] router1: Add error when dest port has no wire

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/route/router1.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/common/route/router1.cc b/common/route/router1.cc
index 981321163f..0f1f0fcfdd 100644
--- a/common/route/router1.cc
+++ b/common/route/router1.cc
@@ -401,6 +401,10 @@ struct Router1
                     arc.user_idx = user.index;
                     arc.phys_idx = phys_idx++;
 
+                    if (dst_wire == WireId())
+                        log_error("No wire found for port %s on destination cell %s.\n", ctx->nameOf(user.value.port),
+                                  ctx->nameOf(user.value.cell));
+
                     if (dst_to_arc.count(dst_wire)) {
                         if (dst_to_arc.at(dst_wire).net_info == net_info)
                             continue;

From 39b6584274d9e7703099dea849b6d1ffd366a3c0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 Mar 2023 11:27:08 +0100
Subject: [PATCH 289/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 108 ++++++++++++++++++++-------------------------------
 1 file changed, 42 insertions(+), 66 deletions(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 0c95b66c0c..d605b4a394 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -2622,14 +2622,12 @@ class Ecp5Packer
         auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
 
         auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
-        auto equals_epsilon_pair = [&](DelayPair& a, DelayPair& b) {
-            return equals_epsilon(a.min_delay, b.min_delay)
-                && equals_epsilon(a.max_delay, b.max_delay);
+        auto equals_epsilon_pair = [&](DelayPair &a, DelayPair &b) {
+            return equals_epsilon(a.min_delay, b.min_delay) && equals_epsilon(a.max_delay, b.max_delay);
         };
-        auto equals_epsilon_constr = [&](ClockConstraint& a, ClockConstraint& b) {
-            return equals_epsilon_pair(a.high, b.high)
-                && equals_epsilon_pair(a.low, b.low)
-                && equals_epsilon_pair(a.period, b.period);
+        auto equals_epsilon_constr = [&](ClockConstraint &a, ClockConstraint &b) {
+            return equals_epsilon_pair(a.high, b.high) && equals_epsilon_pair(a.low, b.low) &&
+                   equals_epsilon_pair(a.period, b.period);
         };
 
         pool<IdString> user_constrained, changed_nets;
@@ -2762,9 +2760,9 @@ class Ecp5Packer
                     }
 
                     std::unique_ptr<ClockConstraint> derived_constr = nullptr;
-                    std::vector<NetInfo*> in_ports = {
-                        ci->ports.at(id_CLK0).net,
-                        ci->ports.at(id_CLK1).net,
+                    std::vector<NetInfo *> in_ports = {
+                            ci->ports.at(id_CLK0).net,
+                            ci->ports.at(id_CLK1).net,
                     };
 
                     // Generate all unique clock pairs find the worst
@@ -2781,75 +2779,49 @@ class Ecp5Packer
                             if (p2 == nullptr || p2->clkconstr == nullptr) {
                                 break;
                             }
-                            auto& c1 = p1->clkconstr;
-                            auto& c2 = p2->clkconstr;
+                            auto &c1 = p1->clkconstr;
+                            auto &c2 = p2->clkconstr;
 
                             auto merged_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
 
                             if (mode == "NEG") {
-                                merged_constr->low = DelayPair(
-                                    std::min(c1->low.min_delay, c2->low.min_delay),
-                                    std::max(
-                                        c1->low.max_delay + c2->period.max_delay,
-                                        c2->low.max_delay + c1->period.max_delay
-                                    )
-                                );
+                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
+                                                               std::max(c1->low.max_delay + c2->period.max_delay,
+                                                                        c2->low.max_delay + c1->period.max_delay));
                             } else {
-                                merged_constr->low = DelayPair(
-                                    std::min(c1->low.min_delay, c2->low.min_delay),
-                                    std::max(c1->low.max_delay, c2->low.max_delay)
-                                );
+                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
+                                                               std::max(c1->low.max_delay, c2->low.max_delay));
                             }
 
                             if (mode == "POS") {
-                                merged_constr->high = DelayPair(
-                                    std::min(c1->high.min_delay, c2->high.min_delay),
-                                    std::max(
-                                        c1->high.max_delay + c2->period.max_delay,
-                                        c2->high.max_delay + c1->period.max_delay
-                                    )
-                                );
+                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
+                                                                std::max(c1->high.max_delay + c2->period.max_delay,
+                                                                         c2->high.max_delay + c1->period.max_delay));
                             } else {
-                                merged_constr->high = DelayPair(
-                                    std::min(c1->high.min_delay, c2->high.min_delay),
-                                    std::max(c1->high.max_delay, c2->high.max_delay)
-                                );
+                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
+                                                                std::max(c1->high.max_delay, c2->high.max_delay));
                             }
 
-                            merged_constr->period = DelayPair(
-                                std::min(c1->period.min_delay, c2->period.min_delay),
-                                std::max(c1->period.max_delay, c2->period.max_delay)
-                            );
+                            merged_constr->period = DelayPair(std::min(c1->period.min_delay, c2->period.min_delay),
+                                                              std::max(c1->period.max_delay, c2->period.max_delay));
 
                             if (derived_constr == nullptr) {
                                 derived_constr = std::move(merged_constr);
                                 continue;
                             }
 
-                            derived_constr->period.min_delay = std::min(
-                                derived_constr->period.min_delay,
-                                merged_constr->period.min_delay
-                            );
-                            derived_constr->period.max_delay = std::max(
-                                derived_constr->period.max_delay,
-                                merged_constr->period.max_delay
-                            );
-                            derived_constr->low.min_delay = std::min(
-                                derived_constr->low.min_delay,
-                                merged_constr->low.min_delay
-                            );
-                            derived_constr->low.max_delay = std::max(
-                                derived_constr->low.max_delay,
-                                merged_constr->low.max_delay
-                            );
-                            derived_constr->high.min_delay = std::min(
-                                derived_constr->high.min_delay,
-                                merged_constr->high.min_delay
-                            );
-                            derived_constr->high.max_delay = std::max(
-                                derived_constr->high.max_delay,
-                                merged_constr->high.max_delay
-                            );
+                            derived_constr->period.min_delay =
+                                    std::min(derived_constr->period.min_delay, merged_constr->period.min_delay);
+                            derived_constr->period.max_delay =
+                                    std::max(derived_constr->period.max_delay, merged_constr->period.max_delay);
+                            derived_constr->low.min_delay =
+                                    std::min(derived_constr->low.min_delay, merged_constr->low.min_delay);
+                            derived_constr->low.max_delay =
+                                    std::max(derived_constr->low.max_delay, merged_constr->low.max_delay);
+                            derived_constr->high.min_delay =
+                                    std::min(derived_constr->high.min_delay, merged_constr->high.min_delay);
+                            derived_constr->high.max_delay =
+                                    std::max(derived_constr->high.max_delay, merged_constr->high.max_delay);
                         }
                     }
 
@@ -2884,10 +2856,14 @@ class Ecp5Packer
                         log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
                                  "800MHz]\n",
                                  vco_freq, ci->name.c_str(ctx));
-                    set_constraint(ci, id_CLKOP, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
-                    set_constraint(ci, id_CLKOS, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
-                    set_constraint(ci, id_CLKOS2, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
-                    set_constraint(ci, id_CLKOS3, simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
+                    set_constraint(ci, id_CLKOP,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
+                    set_constraint(ci, id_CLKOS,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
+                    set_constraint(ci, id_CLKOS2,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
+                    set_constraint(ci, id_CLKOS3,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
                 } else if (ci->type == id_OSCG) {
                     int div = int_or_default(ci->params, id_DIV, 128);
                     set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));

From ff14547601394e758a1b1a82340c83e00ad676b2 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 Mar 2023 10:06:37 +0100
Subject: [PATCH 290/712] ecp5: Update GUI rendering to match arch changes

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/gfx.cc | 106 +++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 81 insertions(+), 25 deletions(-)

diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc
index b1f3d4dd7a..ae1de86a58 100644
--- a/ecp5/gfx.cc
+++ b/ecp5/gfx.cc
@@ -23,13 +23,19 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 const float slice_x1 = 0.92;
-const float slice_x2_comb = 0.927;
-const float slice_x1_ff = 0.933;
 const float slice_x2 = 0.94;
 const float slice_x2_wide = 0.97;
 const float slice_y1 = 0.71;
-const float slice_y2 = 0.7275 + 0.0068 / 2;
-const float slice_pitch = (0.0374 + 0.0068) / 2;
+const float slice_y2 = 0.745 + 0.0068;
+const float slice_pitch = 0.0374 + 0.0068;
+
+const float slice_comb_dx1 = 0.002;
+const float slice_comb_w = 0.007;
+const float slice_ff_dx1 = 0.011;
+const float slice_ff_w = 0.007;
+const float slice_comb_dy1 = 0.002;
+const float slice_comb_h = 0.014;
+const float slice_comb_dy2 = 0.021;
 
 const float io_cell_v_x1 = 0.76;
 const float io_cell_v_x2 = 0.95;
@@ -42,6 +48,7 @@ const float io_cell_h_y2 = 0.24;
 const float wire_distance = 0.0017f;
 const float wire_distance_small = 0.00085f;
 
+const float wire_length_lut = 0.01f;
 const float wire_length = 0.005f;
 const float wire_length_long = 0.015f;
 
@@ -57,33 +64,51 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
     el.type = GraphicElement::TYPE_BOX;
     el.style = style;
     if (bel_type == id_TRELLIS_COMB) {
-        el.x1 = x + slice_x1;
-        el.x2 = x + slice_x2_comb;
-        el.y1 = y + slice_y1 + (z >> Arch::lc_idx_shift) * slice_pitch;
-        el.y2 = y + slice_y2 + (z >> Arch::lc_idx_shift) * slice_pitch;
+        int lc = (z >> Arch::lc_idx_shift);
+
+        el.x1 = x + slice_x1 + slice_comb_dx1;
+        el.x2 = el.x1 + slice_comb_w;
+        el.y1 = y + slice_y1 + (lc / 2) * slice_pitch + ((lc % 2) ? slice_comb_dy2 : slice_comb_dy1);
+        el.y2 = el.y1 + slice_comb_h;
         g.push_back(el);
 
         el.style = GraphicElement::STYLE_FRAME;
-        el.x1 = x + slice_x2_comb + 15 * wire_distance;
-        el.x2 = el.x1 + wire_distance;
-        el.y1 = y + slice_y2 - wire_distance * (TILE_WIRE_CLK3_SLICE - TILE_WIRE_DUMMY_D2 + 5 + (3 - z) * 26) +
-                3 * slice_pitch - 0.0007f;
-        el.y2 = el.y1 + wire_distance * 5;
+
+        if ((lc % 2) == 0) {
+            // SLICE frame
+            el.x1 = x + slice_x1;
+            el.x2 = x + slice_x2;
+            el.y1 = y + slice_y1 + (lc / 2) * slice_pitch;
+            el.y2 = y + slice_y2 + (lc / 2) * slice_pitch;
+            g.push_back(el);
+
+            // SLICE control set switchbox
+            el.x1 = x + slice_x2 + 15 * wire_distance;
+            el.x2 = el.x1 + wire_distance;
+            el.y1 = y + slice_y2 -
+                    wire_distance * (TILE_WIRE_CLK3_SLICE - TILE_WIRE_DUMMY_D2 + 5 + (3 - (lc / 2)) * 26) +
+                    3 * slice_pitch - 0.0007f;
+            el.y2 = el.y1 + wire_distance * 5;
+            g.push_back(el);
+        }
+
+        // LUT permutation switchbox
+        el.x1 = x + slice_x1 - wire_length_lut;
+        el.x2 = x + slice_x1 - wire_length;
+        int start_wire = (TILE_WIRE_D7 + 24 * (lc / 2) + 4 * (lc % 2));
+        el.y2 = y + slice_y2 - wire_distance * (start_wire - TILE_WIRE_FCO + 1 + (lc / 2) * 2) + 3 * slice_pitch +
+                0.25 * wire_distance;
+        el.y1 = el.y2 - 3.5 * wire_distance;
         g.push_back(el);
+
     } else if (bel_type == id_TRELLIS_FF) {
-        el.x1 = x + slice_x1_ff;
-        el.x2 = x + slice_x2;
-        el.y1 = y + slice_y1 + (z >> Arch::lc_idx_shift) * slice_pitch;
-        el.y2 = y + slice_y2 + (z >> Arch::lc_idx_shift) * slice_pitch;
+        int lc = (z >> Arch::lc_idx_shift);
+        el.x1 = x + slice_x1 + slice_ff_dx1;
+        el.x2 = el.x1 + slice_ff_w;
+        el.y1 = y + slice_y1 + (lc / 2) * slice_pitch + ((lc % 2) ? slice_comb_dy2 : slice_comb_dy1);
+        el.y2 = el.y1 + slice_comb_h;
         g.push_back(el);
 
-        el.style = GraphicElement::STYLE_FRAME;
-        el.x1 = x + slice_x2 + 15 * wire_distance;
-        el.x2 = el.x1 + wire_distance;
-        el.y1 = y + slice_y2 - wire_distance * (TILE_WIRE_CLK3_SLICE - TILE_WIRE_DUMMY_D2 + 5 + (3 - z) * 26) +
-                3 * slice_pitch - 0.0007f;
-        el.y2 = el.y1 + wire_distance * 5;
-        g.push_back(el);
     } else if (bel_type.in(id_TRELLIS_IO, id_IOLOGIC, id_SIOLOGIC, id_DQSBUFM)) {
         bool top_bottom = (y == 0 || y == (h - 1));
         if (top_bottom) {
@@ -492,8 +517,14 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS
 
         else if (tilewire >= TILE_WIRE_FCO && tilewire <= TILE_WIRE_FCI) {
             int gap = (tilewire - TILE_WIRE_FCO) / 24;
+            int purpose = (tilewire - TILE_WIRE_FCO) % 24;
             el.x1 = x + switchbox_x2;
-            el.x2 = x + slice_x1 - wire_length;
+            if (purpose >= (TILE_WIRE_D7 - TILE_WIRE_FCO) && purpose <= (TILE_WIRE_A6 - TILE_WIRE_FCO)) {
+                // Space for the LUT permutation switchbox
+                el.x2 = x + slice_x1 - wire_length_lut;
+            } else {
+                el.x2 = x + slice_x1 - wire_length;
+            }
             el.y1 = y + slice_y2 - wire_distance * (tilewire - TILE_WIRE_FCO + 1 + gap * 2) + 3 * slice_pitch;
             el.y2 = el.y1;
             g.push_back(el);
@@ -1166,6 +1197,17 @@ void straightLine(std::vector<GraphicElement> &g, GraphicElement &el, int x, int
     g.push_back(el);
 }
 
+void lutPermPip(std::vector<GraphicElement> &g, GraphicElement &el, int x, int y, int w, int h, WireId src,
+                IdString src_type, GfxTileWireId src_id, WireId dst, IdString dst_type, GfxTileWireId dst_id)
+{
+    int gap = (src_id - TILE_WIRE_FCO) / 24;
+    el.x1 = src.location.x + slice_x1 - wire_length_lut;
+    el.y1 = src.location.y + slice_y2 - wire_distance * (src_id - TILE_WIRE_FCO + 1 + gap * 2) + 3 * slice_pitch;
+    el.x2 = src.location.x + slice_x1 - wire_length;
+    el.y2 = src.location.y + slice_y2 - wire_distance * (dst_id - TILE_WIRE_FCO_SLICE + 1 + gap * 2) + 3 * slice_pitch;
+    g.push_back(el);
+}
+
 void toSameSideHor(std::vector<GraphicElement> &g, GraphicElement &el, int x, int y, int w, int h, WireId src,
                    IdString src_type, GfxTileWireId src_id, WireId dst, IdString dst_type, GfxTileWireId dst_id,
                    GraphicElement::style_t style, int idx)
@@ -1474,6 +1516,20 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire
         toSameSideVer(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id, style, src_id - TILE_WIRE_JCE0);
     }
 
+    if (dst_type == id_WIRE_TYPE_SLICE && src_type == id_WIRE_TYPE_NONE) {
+        if (src_id >= TILE_WIRE_FCO && src_id <= TILE_WIRE_FCI && dst_id >= TILE_WIRE_FCO_SLICE &&
+            dst_id <= TILE_WIRE_FCI_SLICE) {
+            // LUT permutation pseudo-pip
+            int src_purpose = (src_id - TILE_WIRE_FCO) % 24;
+            int dst_purpose = (dst_id - TILE_WIRE_FCO_SLICE) % 24;
+            if (src_purpose >= (TILE_WIRE_D7 - TILE_WIRE_FCO) && src_purpose <= (TILE_WIRE_A6 - TILE_WIRE_FCO) &&
+                dst_purpose >= (TILE_WIRE_D7_SLICE - TILE_WIRE_FCO_SLICE) &&
+                dst_purpose <= (TILE_WIRE_A6_SLICE - TILE_WIRE_FCO_SLICE)) {
+                lutPermPip(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id);
+            }
+        }
+    }
+
     if (src_type == id_WIRE_TYPE_NONE &&
         (dst_type.in(id_WIRE_TYPE_PLL, id_WIRE_TYPE_GSR, id_WIRE_TYPE_JTAG, id_WIRE_TYPE_OSC, id_WIRE_TYPE_SED,
                      id_WIRE_TYPE_DTR, id_WIRE_TYPE_EXTREF, id_WIRE_TYPE_DCU, id_WIRE_TYPE_PCSCLKDIV,

From 12911a7470c8cfa6de7dca953033a3141fc18dae Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Mar 2023 11:08:36 +0100
Subject: [PATCH 291/712] Remove anoying warning from cmake

---
 3rdparty/QtPropertyBrowser/CMakeLists.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/3rdparty/QtPropertyBrowser/CMakeLists.txt b/3rdparty/QtPropertyBrowser/CMakeLists.txt
index 952581bc43..a86b5c6b29 100644
--- a/3rdparty/QtPropertyBrowser/CMakeLists.txt
+++ b/3rdparty/QtPropertyBrowser/CMakeLists.txt
@@ -1,4 +1,5 @@
-CMAKE_MINIMUM_REQUIRED(VERSION 2.8.11)
+CMAKE_MINIMUM_REQUIRED(VERSION 3.13)
+
 PROJECT(QtPropertyBrowser)
 
 ##################### Look for required libraries ######################

From 18ad718e53daa836e15eaa3f61da428f286fbd54 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Mar 2023 11:50:06 +0100
Subject: [PATCH 292/712] Expand list of possible devices

---
 machxo2/CMakeLists.txt   |  3 +--
 machxo2/facade_import.py | 30 ++++++++++++++++++++++++++++--
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/machxo2/CMakeLists.txt b/machxo2/CMakeLists.txt
index f772f80124..4d54f2fa6f 100644
--- a/machxo2/CMakeLists.txt
+++ b/machxo2/CMakeLists.txt
@@ -1,8 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-machxo2 NONE)
 
-# set(ALL_MACHXO2_DEVICES 256 640 1200 2000 4000 7000)
-set(ALL_MACHXO2_DEVICES 1200)
+set(ALL_MACHXO2_DEVICES 256X 640X 1200X 2280X 256 640 1200 2000 4000 7000)
 set(MACHXO2_DEVICES 1200 CACHE STRING
     "Include support for these MachXO2 devices (available: ${ALL_MACHXO2_DEVICES})")
 message(STATUS "Enabled MachXO2 devices: ${MACHXO2_DEVICES}")
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 5bb2d78b01..4a33c2109f 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -92,7 +92,7 @@ def get_bel_index(rg, loc, name):
 pindata = []
 
 def process_pio_db(rg, device):
-    piofile = path.join(database.get_db_root(), "MachXO2", dev_names[device], "iodb.json")
+    piofile = path.join(database.get_db_root(), dev_family[device], dev_names[device], "iodb.json")
     with open(piofile, 'r') as f:
         piodb = json.load(f)
         for pkgname, pkgdata in sorted(piodb["packages"].items()):
@@ -330,7 +330,33 @@ def get_wire_name(loc, idx):
     bba.pop()
 
 
-dev_names = {"1200": "LCMXO2-1200HC"}
+dev_family = {
+    "256X": "MachXO",
+    "640X": "MachXO",
+    "1200X":"MachXO",
+    "2280X":"MachXO",
+
+    "256":  "MachXO2",
+    "640":  "MachXO2",
+    "1200": "MachXO2",
+    "2000": "MachXO2",
+    "4000": "MachXO2",
+    "7000": "MachXO2"
+}
+
+dev_names = {
+    "256X": "LCMXO256",
+    "640X": "LCMXO640",
+    "1200X":"LCMXO1200",
+    "2280X":"LCMXO2280",
+
+    "256":  "LCMXO2-256",
+    "640":  "LCMXO2-640",
+    "1200": "LCMXO2-1200",
+    "2000": "LCMXO2-2000",
+    "4000": "LCMXO2-4000",
+    "7000": "LCMXO2-7000"
+}
 
 def main():
     global max_row, max_col, const_id_count

From 26f23e31212d41c713127d20e561d00260c80408 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Mar 2023 11:54:53 +0100
Subject: [PATCH 293/712] Make small GUI changes

---
 gui/machxo2/mainwindow.cc             |  78 +++++++++++++++++++++-----
 gui/machxo2/mainwindow.h              |   8 ++-
 gui/machxo2/nextpnr.qrc               |   5 ++
 gui/machxo2/resources/open_base.png   | Bin 0 -> 2175 bytes
 gui/machxo2/resources/open_lpf.png    | Bin 0 -> 2117 bytes
 gui/machxo2/resources/save_config.png | Bin 0 -> 1645 bytes
 6 files changed, 77 insertions(+), 14 deletions(-)
 create mode 100644 gui/machxo2/resources/open_base.png
 create mode 100644 gui/machxo2/resources/open_lpf.png
 create mode 100644 gui/machxo2/resources/save_config.png

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 6302d9fa2a..2ecba9101f 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -18,16 +18,13 @@
  */
 
 #include "mainwindow.h"
-#include <QAction>
+#include <fstream>
+#include "bitstream.h"
+#include "log.h"
+
 #include <QFileDialog>
-#include <QFileInfo>
-#include <QIcon>
 #include <QInputDialog>
 #include <QLineEdit>
-#include <QSet>
-#include <fstream>
-#include "design_utils.h"
-#include "log.h"
 
 static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
 
@@ -38,7 +35,7 @@ MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler
 {
     initMainResource();
 
-    std::string title = "nextpnr-xo2 - [EMPTY]";
+    std::string title = "nextpnr-machxo2 - [EMPTY]";
     setWindowTitle(title.c_str());
 
     connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
@@ -48,11 +45,35 @@ MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler
 
 MainWindow::~MainWindow() {}
 
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-machxo2 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
+    setWindowTitle(title.c_str());
+}
+
 void MainWindow::createMenu()
 {
     // Add arch specific actions
+    actionLoadLPF = new QAction("Open LPF", this);
+    actionLoadLPF->setIcon(QIcon(":/icons/resources/open_lpf.png"));
+    actionLoadLPF->setStatusTip("Open LPF file");
+    actionLoadLPF->setEnabled(false);
+    connect(actionLoadLPF, &QAction::triggered, this, &MainWindow::open_lpf);
+
+    actionSaveConfig = new QAction("Save Bitstream", this);
+    actionSaveConfig->setIcon(QIcon(":/icons/resources/save_config.png"));
+    actionSaveConfig->setStatusTip("Save Bitstream config file");
+    actionSaveConfig->setEnabled(false);
+    connect(actionSaveConfig, &QAction::triggered, this, &MainWindow::save_config);
 
     // Add actions in menus
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionLoadLPF);
+    mainActionBar->addAction(actionSaveConfig);
+
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionLoadLPF);
+    menuDesign->addAction(actionSaveConfig);
 }
 
 void MainWindow::new_proj()
@@ -94,14 +115,45 @@ void MainWindow::new_proj()
     }
 }
 
-void MainWindow::newContext(Context *ctx)
+void MainWindow::open_lpf()
 {
-    std::string title = "nextpnr-xo2 - " + ctx->getChipName();
-    setWindowTitle(title.c_str());
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open LPF"), QString(), QString("*.lpf"));
+    if (!fileName.isEmpty()) {
+        /*std::ifstream in(fileName.toStdString());
+        if (ctx->apply_lpf(fileName.toStdString(), in)) {
+            log("Loading LPF successful.\n");
+            actionPack->setEnabled(true);
+            actionLoadLPF->setEnabled(false);
+        } else {
+            actionLoadLPF->setEnabled(true);
+            log("Loading LPF failed.\n");
+        }*/
+    }
 }
 
-void MainWindow::onDisableActions() {}
+void MainWindow::save_config()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save Bitstream"), QString(), QString("*.config"));
+    if (!fileName.isEmpty()) {
+        std::string fn = fileName.toStdString();
+        disableActions();
+        write_bitstream(ctx.get(), fileName.toStdString());
+        log("Saving Bitstream successful.\n");
+    }
+}
 
-void MainWindow::onUpdateActions() {}
+void MainWindow::onDisableActions()
+{
+    actionLoadLPF->setEnabled(false);
+    actionSaveConfig->setEnabled(false);
+}
+
+void MainWindow::onUpdateActions()
+{
+    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
+        actionLoadLPF->setEnabled(true);
+    if (ctx->settings.find(ctx->id("route")) != ctx->settings.end())
+        actionSaveConfig->setEnabled(true);
+}
 
 NEXTPNR_NAMESPACE_END
diff --git a/gui/machxo2/mainwindow.h b/gui/machxo2/mainwindow.h
index 2dcd052f26..20d72c6854 100644
--- a/gui/machxo2/mainwindow.h
+++ b/gui/machxo2/mainwindow.h
@@ -35,13 +35,19 @@ class MainWindow : public BaseMainWindow
   public:
     void createMenu();
 
+  protected:
     void onDisableActions() override;
     void onUpdateActions() override;
 
   protected Q_SLOTS:
     void new_proj() override;
-
     void newContext(Context *ctx);
+    void open_lpf();
+    void save_config();
+
+  private:
+    QAction *actionLoadLPF;
+    QAction *actionSaveConfig;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/gui/machxo2/nextpnr.qrc b/gui/machxo2/nextpnr.qrc
index 03585ec030..ca7e5b1a26 100644
--- a/gui/machxo2/nextpnr.qrc
+++ b/gui/machxo2/nextpnr.qrc
@@ -1,2 +1,7 @@
 <RCC>
+    <qresource prefix="/icons">
+        <file>resources/open_lpf.png</file> 
+        <file>resources/open_base.png</file>
+        <file>resources/save_config.png</file>
+    </qresource>
 </RCC>
diff --git a/gui/machxo2/resources/open_base.png b/gui/machxo2/resources/open_base.png
new file mode 100644
index 0000000000000000000000000000000000000000..b60cf25a109b1e2488b211be1e7bb7a7bc01e04f
GIT binary patch
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diff --git a/gui/machxo2/resources/open_lpf.png b/gui/machxo2/resources/open_lpf.png
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GIT binary patch
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From 4396a646a7c10d4748c8b2ae105b100b7f1fedb7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Mar 2023 12:17:37 +0100
Subject: [PATCH 294/712] Add simple BEL graphics

---
 machxo2/arch.cc    | 74 ++++++++++++++++++++++++++++++++++
 machxo2/arch.h     |  7 ++++
 machxo2/archdefs.h | 25 +++++++++++-
 machxo2/gfx.cc     | 98 ++++++++++++++++++++++++++++++++++++++++++++++
 machxo2/gfx.h      | 42 ++++++++++++++++++++
 5 files changed, 245 insertions(+), 1 deletion(-)
 create mode 100644 machxo2/gfx.cc
 create mode 100644 machxo2/gfx.h

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index d85921bcd8..350b08cb67 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -21,6 +21,7 @@
 #include <iostream>
 #include <math.h>
 #include "embed.h"
+#include "gfx.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
@@ -449,6 +450,79 @@ bool Arch::route()
     return result;
 }
 
+// -----------------------------------------------------------------------
+
+std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
+{
+    std::vector<GraphicElement> ret;
+    if (decal.type == DecalId::TYPE_WIRE) {
+        WireId wire;
+        wire.index = decal.z;
+        wire.location = decal.location;
+        auto wire_type = getWireType(wire);
+        int x = decal.location.x;
+        int y = decal.location.y;
+        GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+        GfxTileWireId tilewire = GfxTileWireId(tile_info(wire)->wire_data[wire.index].tile_wire);
+        gfxTileWire(ret, x, y, chip_info->width, chip_info->height, wire_type, tilewire, style);
+    } else if (decal.type == DecalId::TYPE_PIP) {
+        PipId pip;
+        pip.index = decal.z;
+        pip.location = decal.location;
+        WireId src_wire = getPipSrcWire(pip);
+        WireId dst_wire = getPipDstWire(pip);
+        int x = decal.location.x;
+        int y = decal.location.y;
+        GfxTileWireId src_id = GfxTileWireId(tile_info(src_wire)->wire_data[src_wire.index].tile_wire);
+        GfxTileWireId dst_id = GfxTileWireId(tile_info(dst_wire)->wire_data[dst_wire.index].tile_wire);
+        GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
+        gfxTilePip(ret, x, y, chip_info->width, chip_info->height, src_wire, getWireType(src_wire), src_id, dst_wire,
+                   getWireType(dst_wire), dst_id, style);
+    } else if (decal.type == DecalId::TYPE_BEL) {
+        BelId bel;
+        bel.index = decal.z;
+        bel.location = decal.location;
+        auto bel_type = getBelType(bel);
+        int x = decal.location.x;
+        int y = decal.location.y;
+        int z = tile_info(bel)->bel_data[bel.index].z;
+        GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+        gfxTileBel(ret, x, y, z, chip_info->width, chip_info->height, bel_type, style);
+    }
+
+    return ret;
+}
+
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+    DecalXY decalxy;
+    decalxy.decal.type = DecalId::TYPE_BEL;
+    decalxy.decal.location = bel.location;
+    decalxy.decal.z = bel.index;
+    decalxy.decal.active = getBoundBelCell(bel) != nullptr;
+    return decalxy;
+}
+
+DecalXY Arch::getWireDecal(WireId wire) const
+{
+    DecalXY decalxy;
+    decalxy.decal.type = DecalId::TYPE_WIRE;
+    decalxy.decal.location = wire.location;
+    decalxy.decal.z = wire.index;
+    decalxy.decal.active = getBoundWireNet(wire) != nullptr;
+    return decalxy;
+}
+
+DecalXY Arch::getPipDecal(PipId pip) const
+{
+    DecalXY decalxy;
+    decalxy.decal.type = DecalId::TYPE_PIP;
+    decalxy.decal.location = pip.location;
+    decalxy.decal.z = pip.index;
+    decalxy.decal.active = getBoundPipNet(pip) != nullptr;
+    return decalxy;
+};
+
 // ---------------------------------------------------------------
 
 bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 214d8bb230..26e8a9efe8 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -643,6 +643,13 @@ struct Arch : BaseArch<ArchRanges>
     bool place() override;
     bool route() override;
 
+    // Graphics
+    std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
+
+    DecalXY getBelDecal(BelId bel) const override;
+    DecalXY getWireDecal(WireId wire) const override;
+    DecalXY getPipDecal(PipId pip) const override;
+
     // Placer
     bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
index 87f9c98a64..1520f0c33d 100644
--- a/machxo2/archdefs.h
+++ b/machxo2/archdefs.h
@@ -107,8 +107,31 @@ struct PipId
     unsigned int hash() const { return mkhash(location.hash(), index); }
 };
 
+struct DecalId
+{
+    enum
+    {
+        TYPE_NONE,
+        TYPE_BEL,
+        TYPE_WIRE,
+        TYPE_PIP,
+        TYPE_GROUP
+    } type = TYPE_NONE;
+    Location location;
+    uint32_t z = 0;
+    bool active = false;
+    bool operator==(const DecalId &other) const
+    {
+        return type == other.type && location == other.location && z == other.z && active == other.active;
+    }
+    bool operator!=(const DecalId &other) const
+    {
+        return type != other.type || location != other.location || z != other.z || active != other.active;
+    }
+    unsigned int hash() const { return mkhash(location.hash(), mkhash(z, int(type))); }
+};
+
 typedef IdString GroupId;
-typedef IdString DecalId;
 typedef IdString BelBucketId;
 typedef IdString ClusterId;
 
diff --git a/machxo2/gfx.cc b/machxo2/gfx.cc
new file mode 100644
index 0000000000..97876ad202
--- /dev/null
+++ b/machxo2/gfx.cc
@@ -0,0 +1,98 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "gfx.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const float slice_x1 = 0.800;
+const float slice_x2_comb = 0.927;
+//const float slice_x1_ff = 0.933;
+const float slice_x2 = 0.94;
+const float slice_y1 = 0.60;
+const float slice_y2 = 0.65 + 0.1 / 4;
+const float slice_pitch = 0.1;
+
+const float io_cell_v_x1 = 0.76;
+const float io_cell_v_x2 = 0.95;
+const float io_cell_v_y1 = 0.05;
+const float io_cell_gap = 0.10;
+const float io_cell_h_x1 = 0.05;
+const float io_cell_h_y1 = 0.05;
+const float io_cell_h_y2 = 0.24;
+
+
+void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int h, IdString bel_type,
+                GraphicElement::style_t style)
+{
+    GraphicElement el;
+    el.type = GraphicElement::TYPE_BOX;
+    el.style = style;
+    if (bel_type == id_FACADE_SLICE) {
+        el.x1 = x + slice_x1;
+        el.x2 = x + slice_x2_comb;
+        el.y1 = y + slice_y1 + z * slice_pitch;
+        el.y2 = y + slice_y2 + z * slice_pitch;
+        g.push_back(el);
+/*    } else if (bel_type == id_FACADE_FF) {
+        el.x1 = x + slice_x1_ff;
+        el.x2 = x + slice_x2;
+        el.y1 = y + slice_y1 + z * slice_pitch;
+        el.y2 = y + slice_y2 + z * slice_pitch;
+        g.push_back(el);*/
+    } else if (bel_type.in(id_FACADE_IO)) {
+        bool top_bottom = (y == 0 || y == (h - 1));
+        if (top_bottom) {
+            el.x1 = x + io_cell_h_x1 + (z + 2) * io_cell_gap;
+            el.x2 = x + io_cell_h_x1 + (z + 2) * io_cell_gap + 0.08f;
+            if (y == h - 1) {
+                el.y1 = y + 1 - io_cell_h_y1;
+                el.y2 = y + 1 - io_cell_h_y2;
+            } else {
+                el.y1 = y + io_cell_h_y1;
+                el.y2 = y + io_cell_h_y2;
+            }
+        } else {
+            if (x == 0) {
+                el.x1 = x + 1 - io_cell_v_x1;
+                el.x2 = x + 1 - io_cell_v_x2;
+            } else {
+                el.x1 = x + io_cell_v_x1;
+                el.x2 = x + io_cell_v_x2;
+            }
+            el.y1 = y + io_cell_v_y1 + z * io_cell_gap;
+            el.y2 = y + io_cell_v_y1 + z * io_cell_gap + 0.08f;
+        }
+        g.push_back(el);
+    }
+}
+
+void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdString wire_type, GfxTileWireId tilewire,
+                 GraphicElement::style_t style)
+{
+}
+
+
+void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, WireId src, IdString src_type,
+                GfxTileWireId src_id, WireId dst, IdString dst_type, GfxTileWireId dst_id,
+                GraphicElement::style_t style)
+{
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/machxo2/gfx.h b/machxo2/gfx.h
new file mode 100644
index 0000000000..2914844fbd
--- /dev/null
+++ b/machxo2/gfx.h
@@ -0,0 +1,42 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MACHXO2_GFX_H
+#define MACHXO2_GFX_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+enum GfxTileWireId
+{
+    TILE_WIRE_NONE,
+};
+
+void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int h, IdString bel_type,
+                GraphicElement::style_t style);
+void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdString wire_type, GfxTileWireId tilewire,
+                 GraphicElement::style_t style);
+void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, WireId src, IdString src_type,
+                GfxTileWireId src_id, WireId dst, IdString dst_type, GfxTileWireId dst_id,
+                GraphicElement::style_t style);
+
+NEXTPNR_NAMESPACE_END
+
+#endif

From d5b5f7e4b2573444081ab30d400c3db5d9e278d8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 Mar 2023 11:03:44 +0100
Subject: [PATCH 295/712] add new field handling in chip config format

---
 machxo2/config.cc | 3 +++
 machxo2/config.h  | 1 +
 2 files changed, 4 insertions(+)

diff --git a/machxo2/config.cc b/machxo2/config.cc
index 34c4954e8c..8021369d74 100644
--- a/machxo2/config.cc
+++ b/machxo2/config.cc
@@ -268,6 +268,7 @@ bool TileConfig::empty() const { return carcs.empty() && cwords.empty() && cenum
 std::ostream &operator<<(std::ostream &out, const ChipConfig &cc)
 {
     out << ".device " << cc.chip_name << std::endl << std::endl;
+    out << ".variant " << cc.chip_variant << std::endl << std::endl;
     for (const auto &meta : cc.metadata)
         out << ".comment " << meta << std::endl;
     for (const auto &sc : cc.sysconfig)
@@ -312,6 +313,8 @@ std::istream &operator>>(std::istream &in, ChipConfig &cc)
         in >> verb;
         if (verb == ".device") {
             in >> cc.chip_name;
+        } else if (verb == ".variant") {
+            in >> cc.chip_variant;
         } else if (verb == ".comment") {
             std::string line;
             getline(in, line);
diff --git a/machxo2/config.h b/machxo2/config.h
index a71b29a88b..141409bcb1 100644
--- a/machxo2/config.h
+++ b/machxo2/config.h
@@ -112,6 +112,7 @@ class ChipConfig
 {
   public:
     std::string chip_name;
+    std::string chip_variant;
     std::vector<std::string> metadata;
     std::map<std::string, TileConfig> tiles;
     std::vector<TileGroup> tilegroups;

From 7ad9914e519d465cfb36e0114a644e2d03c6f4fa Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 Mar 2023 11:04:38 +0100
Subject: [PATCH 296/712] Extend chipdb with metadata

---
 gui/machxo2/mainwindow.cc  |  17 +---
 machxo2/arch.cc            | 156 +++++++++++++------------------------
 machxo2/arch.h             |  69 +++++++---------
 machxo2/arch_pybindings.cc |   2 +-
 machxo2/available.h.in     |   1 +
 machxo2/bitstream.cc       |  20 +++--
 machxo2/constids.inc       |   6 --
 machxo2/facade_import.py   |  83 ++++++++++++++++++++
 machxo2/family.cmake       |   3 +
 machxo2/main.cc            |  49 +++---------
 machxo2/pack.cc            |   2 +-
 11 files changed, 192 insertions(+), 216 deletions(-)
 create mode 100644 machxo2/available.h.in

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 2ecba9101f..b92f752c6a 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -47,7 +47,7 @@ MainWindow::~MainWindow() {}
 
 void MainWindow::newContext(Context *ctx)
 {
-    std::string title = "nextpnr-machxo2 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
+    std::string title = "nextpnr-machxo2 - " + std::string(ctx->device_name) + " (" + std::string(ctx->package_name) + ") - Part : " + ctx->getChipName();
     setWindowTitle(title.c_str());
 }
 
@@ -78,19 +78,7 @@ void MainWindow::createMenu()
 
 void MainWindow::new_proj()
 {
-    QMap<QString, int> arch;
-    if (Arch::is_available(ArchArgs::LCMXO2_256HC))
-        arch.insert("LCMXO2-256HC", ArchArgs::LCMXO2_256HC);
-    if (Arch::is_available(ArchArgs::LCMXO2_640HC))
-        arch.insert("LCMXO2-640HC", ArchArgs::LCMXO2_640HC);
-    if (Arch::is_available(ArchArgs::LCMXO2_1200HC))
-        arch.insert("LCMXO2-1200HC", ArchArgs::LCMXO2_1200HC);
-    if (Arch::is_available(ArchArgs::LCMXO2_2000HC))
-        arch.insert("LCMXO2-2000HC", ArchArgs::LCMXO2_2000HC);
-    if (Arch::is_available(ArchArgs::LCMXO2_4000HC))
-        arch.insert("LCMXO2-4000HC", ArchArgs::LCMXO2_4000HC);
-    if (Arch::is_available(ArchArgs::LCMXO2_7000HC))
-        arch.insert("LCMXO2-7000HC", ArchArgs::LCMXO2_7000HC);
+/*  QMap<QString, int> arch;
     bool ok;
     QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
     if (ok && !item.isEmpty()) {
@@ -113,6 +101,7 @@ void MainWindow::new_proj()
             Q_EMIT contextChanged(ctx.get());
         }
     }
+*/
 }
 
 void MainWindow::open_lpf()
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 350b08cb67..481d15eecf 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -28,6 +28,7 @@
 #include "router1.h"
 #include "router2.h"
 #include "util.h"
+#include "chipdb/available.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -44,51 +45,53 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 
 // ---------------------------------------------------------------
 
-static const ChipInfoPOD *get_chip_info(ArchArgs::ArchArgsTypes chip)
+static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info, const char **device_name, const char **package_name)
 {
-    std::string chipdb;
-    if (chip == ArchArgs::LCMXO2_256HC) {
-        chipdb = "machxo2/chipdb-256.bin";
-    } else if (chip == ArchArgs::LCMXO2_640HC) {
-        chipdb = "machxo2/chipdb-640.bin";
-    } else if (chip == ArchArgs::LCMXO2_1200HC) {
-        chipdb = "machxo2/chipdb-1200.bin";
-    } else if (chip == ArchArgs::LCMXO2_2000HC) {
-        chipdb = "machxo2/chipdb-2000.bin";
-    } else if (chip == ArchArgs::LCMXO2_4000HC) {
-        chipdb = "machxo2/chipdb-4000.bin";
-    } else if (chip == ArchArgs::LCMXO2_7000HC) {
-        chipdb = "machxo2/chipdb-7000.bin";
-    } else {
-        log_error("Unknown chip\n");
+    std::stringstream ss(available_devices);
+    std::string name;
+    while(getline(ss, name, ';')){ 
+        std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
+        auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
+        if (!db_ptr)
+            continue; // chipdb not available
+        for (auto &chip : db_ptr->get()->variants) {
+            for (auto &pkg : chip.packages) {
+                for (auto &speedgrade : chip.speed_grades) {
+                    for (auto &rating : chip.suffixes) {
+                        std::string name = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        if (device == name) {
+                            *chip_info = db_ptr->get();
+                            *package_info = nullptr;
+                            *package_name = pkg.name.get();
+                            *device_name = chip.name.get();
+                            for (int i = 0; i < (*chip_info)->num_packages; i++) {
+                                if (pkg.name.get() == (*chip_info)->package_info[i].name.get()) {
+                                    *package_info = &((*chip_info)->package_info[i]);
+                                    break;
+                                }
+                            }
+                            return;
+                        }
+                    }
+                }
+            }
+        }
     }
-
-    auto ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
-    if (ptr == nullptr)
-        return nullptr;
-    return ptr->get();
 }
 
 // ---------------------------------------------------------------
 
 Arch::Arch(ArchArgs args) : args(args)
 {
-    chip_info = get_chip_info(args.type);
+    get_chip_info(args.device, &chip_info, &package_info, &device_name, &package_name);
     if (chip_info == nullptr)
         log_error("Unsupported MachXO2 chip type.\n");
     if (chip_info->const_id_count != DB_CONST_ID_COUNT)
         log_error("Chip database 'bba' and nextpnr code are out of sync; please rebuild (or contact distribution "
                   "maintainer)!\n");
 
-    package_info = nullptr;
-    for (int i = 0; i < chip_info->num_packages; i++) {
-        if (args.package == chip_info->package_info[i].name.get()) {
-            package_info = &(chip_info->package_info[i]);
-            break;
-        }
-    }
     if (!package_info)
-        log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
+        log_error("Unsupported package '%s' for '%s'.\n", package_name, getChipName().c_str());
 
     BaseArch::init_cell_types();
     BaseArch::init_bel_buckets();
@@ -110,83 +113,32 @@ Arch::Arch(ArchArgs args) : args(args)
     }
 }
 
-bool Arch::is_available(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; }
-
-std::vector<std::string> Arch::get_supported_packages(ArchArgs::ArchArgsTypes chip)
-{
-    const ChipInfoPOD *chip_info = get_chip_info(chip);
-    std::vector<std::string> pkgs;
-    for (int i = 0; i < chip_info->num_packages; i++) {
-        pkgs.push_back(chip_info->package_info[i].name.get());
-    }
-    return pkgs;
-}
-
-std::string Arch::getChipName() const
+void Arch::list_devices()
 {
-    if (args.type == ArchArgs::LCMXO2_256HC) {
-        return "LCMXO2-256HC";
-    } else if (args.type == ArchArgs::LCMXO2_640HC) {
-        return "LCMXO2-640HC";
-    } else if (args.type == ArchArgs::LCMXO2_1200HC) {
-        return "LCMXO2-1200HC";
-    } else if (args.type == ArchArgs::LCMXO2_2000HC) {
-        return "LCMXO2-2000HC";
-    } else if (args.type == ArchArgs::LCMXO2_4000HC) {
-        return "LCMXO2-4000HC";
-    } else if (args.type == ArchArgs::LCMXO2_7000HC) {
-        return "LCMXO2-7000HC";
-    } else {
-        log_error("Unknown chip\n");
-    }
-}
-
-std::string Arch::get_full_chip_name() const
-{
-    std::string name = getChipName();
-    name += "-";
-    switch (args.speed) {
-    case ArchArgs::SPEED_1:
-        name += "1";
-        break;
-    case ArchArgs::SPEED_2:
-        name += "2";
-        break;
-    case ArchArgs::SPEED_3:
-        name += "3";
-        break;
-    case ArchArgs::SPEED_4:
-        name += "4";
-        break;
-    case ArchArgs::SPEED_5:
-        name += "5";
-        break;
-    case ArchArgs::SPEED_6:
-        name += "6";
-        break;
+    log("Supported devices: \n");
+    std::stringstream ss(available_devices);
+    std::string name;
+    while(getline(ss, name, ';')){ 
+        std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
+        auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
+        if (!db_ptr)
+            continue; // chipdb not available
+        for (auto &chip : db_ptr->get()->variants) {
+            for (auto &pkg : chip.packages) {
+                for (auto &speedgrade : chip.speed_grades) {
+                    for (auto &rating : chip.suffixes) {
+                        log("    %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                    }
+                }
+            }
+        }
     }
-    name += args.package;
-    return name;
 }
 
-IdString Arch::archArgsToId(ArchArgs args) const
-{
-    if (args.type == ArchArgs::LCMXO2_256HC) {
-        return id_lcmxo2_256hc;
-    } else if (args.type == ArchArgs::LCMXO2_640HC) {
-        return id_lcmxo2_640hc;
-    } else if (args.type == ArchArgs::LCMXO2_1200HC) {
-        return id_lcmxo2_1200hc;
-    } else if (args.type == ArchArgs::LCMXO2_2000HC) {
-        return id_lcmxo2_2000hc;
-    } else if (args.type == ArchArgs::LCMXO2_4000HC) {
-        return id_lcmxo2_4000hc;
-    } else if (args.type == ArchArgs::LCMXO2_7000HC) {
-        return id_lcmxo2_7000hc;
-    }
+// -----------------------------------------------------------------------
 
-    return IdString();
-}
+std::string Arch::getChipName() const { return args.device; }
+IdString Arch::archArgsToId(ArchArgs args) const { return id(args.device); }
 
 // ---------------------------------------------------------------
 
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 26e8a9efe8..4e0ed2fd15 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -25,31 +25,13 @@
 #include <set>
 
 #include "base_arch.h"
-#include "nextpnr_namespaces.h"
 #include "nextpnr_types.h"
+#include "relptr.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
 /**** Everything in this section must be kept in sync with chipdb.py ****/
 
-template <typename T> struct RelPtr
-{
-    int32_t offset;
-
-    // void set(const T *ptr) {
-    //     offset = reinterpret_cast<const char*>(ptr) -
-    //              reinterpret_cast<const char*>(this);
-    // }
-
-    const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
-
-    const T &operator[](std::size_t index) const { return get()[index]; }
-
-    const T &operator*() const { return *(get()); }
-
-    const T *operator->() const { return get(); }
-};
-
 // FIXME: All "rel locs" are actually absolute, naming typo in facade_import.
 // Does not affect runtime functionality.
 
@@ -141,7 +123,29 @@ NPNR_PACKED_STRUCT(struct TileInfoPOD {
     RelPtr<TileNamePOD> tile_names;
 });
 
+NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
+    RelPtr<char> name;
+    RelPtr<char> short_name;
+});
+
+NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD {
+    RelPtr<char> suffix;
+});
+
+NPNR_PACKED_STRUCT(struct SpeedSupportedPOD {
+    int32_t speed;
+});
+
+NPNR_PACKED_STRUCT(struct VariantInfoPOD {
+    RelPtr<char> name;
+    RelSlice<PackageSupportedPOD> packages;
+    RelSlice<SpeedSupportedPOD> speed_grades;
+    RelSlice<SuffixeSupportedPOD> suffixes;
+});
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
+    RelPtr<char> family;
+    RelPtr<char> device_name;
     int32_t width, height;
     int32_t num_tiles;
     int32_t num_packages, num_pios;
@@ -151,6 +155,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<PackageInfoPOD> package_info;
     RelPtr<PIOInfoPOD> pio_info;
     RelPtr<TileInfoPOD> tile_info;
+    RelSlice<VariantInfoPOD> variants;
 });
 
 /************************ End of chipdb section. ************************/
@@ -361,26 +366,7 @@ struct PipRange
 
 struct ArchArgs
 {
-    enum ArchArgsTypes
-    {
-        NONE,
-        LCMXO2_256HC,
-        LCMXO2_640HC,
-        LCMXO2_1200HC,
-        LCMXO2_2000HC,
-        LCMXO2_4000HC,
-        LCMXO2_7000HC,
-    } type = NONE;
-    std::string package;
-    enum SpeedGrade
-    {
-        SPEED_1 = 0,
-        SPEED_2,
-        SPEED_3,
-        SPEED_4,
-        SPEED_5,
-        SPEED_6,
-    } speed = SPEED_4;
+    std::string device;
 };
 
 struct ArchRanges : BaseArchRanges
@@ -403,6 +389,8 @@ struct Arch : BaseArch<ArchRanges>
 {
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info;
+    const char *package_name;
+    const char *device_name;
 
     mutable dict<IdStringList, PipId> pip_by_name;
 
@@ -429,8 +417,7 @@ struct Arch : BaseArch<ArchRanges>
     ArchArgs args;
     Arch(ArchArgs args);
 
-    static bool is_available(ArchArgs::ArchArgsTypes chip);
-    static std::vector<std::string> get_supported_packages(ArchArgs::ArchArgsTypes chip);
+    static void list_devices();
 
     std::string getChipName() const override;
     // Extra helper
diff --git a/machxo2/arch_pybindings.cc b/machxo2/arch_pybindings.cc
index 3fcf721db6..6bd31ff7f2 100644
--- a/machxo2/arch_pybindings.cc
+++ b/machxo2/arch_pybindings.cc
@@ -30,7 +30,7 @@ NEXTPNR_NAMESPACE_BEGIN
 void arch_wrap_python(py::module &m)
 {
     using namespace PythonConversion;
-    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("type", &ArchArgs::type);
+    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("device", &ArchArgs::device);
 
     py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
 
diff --git a/machxo2/available.h.in b/machxo2/available.h.in
new file mode 100644
index 0000000000..dce650ee2c
--- /dev/null
+++ b/machxo2/available.h.in
@@ -0,0 +1 @@
+static const char *available_devices = "@MACHXO2_DEVICES@";
\ No newline at end of file
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 9a711cbe45..c04df52e97 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -30,10 +30,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 // These seem simple enough to do inline for now.
 namespace BaseConfigs {
-void config_empty_lcmxo2_1200hc(ChipConfig &cc)
+void config_empty_lcmxo2_1200(ChipConfig &cc)
 {
-    cc.chip_name = "LCMXO2-1200HC";
-
     cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
@@ -196,16 +194,16 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
 void write_bitstream(Context *ctx, std::string text_config_file)
 {
     ChipConfig cc;
-
-    switch (ctx->args.type) {
-    case ArchArgs::LCMXO2_1200HC:
-        BaseConfigs::config_empty_lcmxo2_1200hc(cc);
-        break;
-    default:
+    IdString base_id = ctx->id(ctx->chip_info->device_name.get());
+    //IdString device_id = ctx->id(ctx->device_name);
+    if (base_id == ctx->id("LCMXO2-1200"))
+        BaseConfigs::config_empty_lcmxo2_1200(cc);
+    else
         NPNR_ASSERT_FALSE("Unsupported device type");
-    }
+    cc.chip_name = ctx->chip_info->device_name.get();
+    cc.chip_variant = ctx->device_name;
 
-    cc.metadata.push_back("Part: " + ctx->get_full_chip_name());
+    cc.metadata.push_back("Part: " + ctx->getChipName());
 
     // Add all set, configurable pips to the config
     for (auto pip : ctx->getPips()) {
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index b216f8b4d1..58319e4551 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -123,12 +123,6 @@ X(IO_TYPE)
 X(LOC)
 X(NOM_FREQ)
 X(VCC)
-X(lcmxo2_1200hc)
-X(lcmxo2_2000hc)
-X(lcmxo2_256hc)
-X(lcmxo2_4000hc)
-X(lcmxo2_640hc)
-X(lcmxo2_7000hc)
 X(machxo2)
 X(pack)
 X(place)
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 4a33c2109f..9a001e4e42 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -25,6 +25,49 @@ def get_tiletype_index(name):
     tiletype_names[name] = idx
     return idx
 
+def package_shortname(long_name, family):
+    if long_name.startswith("CABGA"):
+        if (family == "MachXO"):
+            return "B" + long_name[5:]
+        else:
+            return "BG" + long_name[5:]
+    elif long_name.startswith("CSBGA"):
+        if (family == "MachXO"):
+            return "M" + long_name[5:]
+        else:
+            return "MG" + long_name[5:]
+    elif long_name.startswith("CSFBGA"):
+        return "MG" + long_name[6:]
+    elif long_name.startswith("UCBGA"):
+        return "UMG" + long_name[5:]
+    elif long_name.startswith("FPBGA"):
+        return "FG" + long_name[5:]
+    elif long_name.startswith("FTBGA"):
+        if (family == "MachXO"):
+            return "FT" + long_name[5:]
+        else:
+            return "FTG" + long_name[5:]
+    elif long_name.startswith("WLCSP"):
+        if (family == "MachXO3D"):
+            return "UTG" + long_name[5:]
+        else:
+            return "UWG" + long_name[5:]
+    elif long_name.startswith("TQFP"):
+        if (family == "MachXO"):
+            return "T" + long_name[4:]
+        else:
+            return "TG" + long_name[4:]
+    elif long_name.startswith("QFN"):
+        if (family == "MachXO3D"):
+            return "SG" + long_name[3:]
+        else:
+            if long_name[3]=="8":
+                return "QN" + long_name[3:]
+            else:
+                return "SG" + long_name[3:]
+    else:
+        print("unknown package name " + long_name)
+        sys.exit(-1)
 
 constids = dict()
 
@@ -42,17 +85,27 @@ def r(self, name, comment):
         else:
             print("ref %s %s" % (name, comment))
 
+    def r_slice(self, name, length, comment):
+        if comment is None:
+            print("ref %s" % (name,))
+        else:
+            print("ref %s %s" % (name, comment))
+        print ("u32 %d" % (length, ))
+
     def s(self, s, comment):
         assert "|" not in s
         print("str |%s| %s" % (s, comment))
 
     def u8(self, v, comment):
+        assert -128 <= int(v) <= 127
         if comment is None:
             print("u8 %d" % (v,))
         else:
             print("u8 %d %s" % (v, comment))
 
     def u16(self, v, comment):
+        # is actually used as signed 16 bit
+        assert -32768 <= int(v) <= 32767
         if comment is None:
             print("u16 %d" % (v,))
         else:
@@ -90,6 +143,14 @@ def get_bel_index(rg, loc, name):
 
 packages = {}
 pindata = []
+variants = {}
+
+def process_devices_db(family, device):
+    devicefile = path.join(database.get_db_root(), "devices.json")
+    with open(devicefile, 'r') as f:
+        devicedb = json.load(f)
+        for varname, vardata in sorted(devicedb["families"][family]["devices"][device]["variants"].items()):
+            variants[varname] = vardata
 
 def process_pio_db(rg, device):
     piofile = path.join(database.get_db_root(), dev_family[device], dev_names[device], "iodb.json")
@@ -312,8 +373,28 @@ def get_wire_name(loc, idx):
     for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
         bba.s(tt, "name")
 
+    for name, var_data in sorted(variants.items()):
+        bba.l("supported_packages_%s" % name, "PackageSupportedPOD")
+        for package in var_data["packages"]:
+            bba.s(package, "name")
+            bba.s(package_shortname(package, chip.info.family), "short_name")
+        bba.l("supported_speed_grades_%s" % name, "SpeedSupportedPOD")
+        for speed in var_data["speeds"]:
+            bba.u32(speed, "speed")
+        bba.l("supported_suffixes_%s" % name, "SuffixeSupportedPOD")
+        for suffix in var_data["suffixes"]:
+            bba.s(suffix, "suffix")
+
+    bba.l("variant_data", "VariantInfoPOD")
+    for name, var_data in sorted(variants.items()):
+        bba.s(name, "variant_name")
+        bba.r_slice("supported_packages_%s" % name, len(var_data["packages"]), "supported_packages")
+        bba.r_slice("supported_speed_grades_%s" % name, len(var_data["speeds"]), "supported_speed_grades")
+        bba.r_slice("supported_suffixes_%s" % name, len(var_data["suffixes"]), "supported_suffixes")
 
     bba.l("chip_info")
+    bba.s(chip.info.family, "family")
+    bba.s(chip.info.name, "device_name")
     bba.u32(max_col + 1, "width")
     bba.u32(max_row + 1, "height")
     bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
@@ -326,6 +407,7 @@ def get_wire_name(loc, idx):
     bba.r("package_data", "package_info")
     bba.r("pio_info", "pio_info")
     bba.r("tiles_info", "tile_info")
+    bba.r_slice("variant_data", len(variants), "variant_info")
 
     bba.pop()
 
@@ -386,6 +468,7 @@ def main():
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_pio_db(rg, args.device)
+    process_devices_db(chip.info.family, chip.info.name)
     bba = write_database(args.device, chip, rg, "le")
 
 
diff --git a/machxo2/family.cmake b/machxo2/family.cmake
index 76c5df939a..43b1a9b220 100644
--- a/machxo2/family.cmake
+++ b/machxo2/family.cmake
@@ -48,6 +48,9 @@ target_compile_options(chipdb-${family} PRIVATE -g0 -O0 -w)
 target_compile_definitions(chipdb-${family} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
 target_include_directories(chipdb-${family} PRIVATE ${family})
 
+configure_file(${family}/available.h.in ${family}/chipdb/available.h)
+
 foreach(family_target ${family_targets})
     target_sources(${family_target} PRIVATE $<TARGET_OBJECTS:chipdb-${family}>)
+    target_sources(${family_target} PRIVATE ${family}/chipdb/available.h)
 endforeach()
diff --git a/machxo2/main.cc b/machxo2/main.cc
index e29e117b45..e5b8176a58 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -47,26 +47,9 @@ MachXO2CommandHandler::MachXO2CommandHandler(int argc, char **argv) : CommandHan
 po::options_description MachXO2CommandHandler::getArchOptions()
 {
     po::options_description specific("Architecture specific options");
-    if (Arch::is_available(ArchArgs::LCMXO2_256HC))
-        specific.add_options()("256", "set device type to LCMXO2-256HC");
-    if (Arch::is_available(ArchArgs::LCMXO2_640HC))
-        specific.add_options()("640", "set device type to LCMXO2-640HC");
-    if (Arch::is_available(ArchArgs::LCMXO2_1200HC))
-        specific.add_options()("1200", "set device type to LCMXO2-1200HC");
-    if (Arch::is_available(ArchArgs::LCMXO2_2000HC))
-        specific.add_options()("2000", "set device type to LCMXO2-2000HC");
-    if (Arch::is_available(ArchArgs::LCMXO2_4000HC))
-        specific.add_options()("4000", "set device type to LCMXO2-4000HC");
-    if (Arch::is_available(ArchArgs::LCMXO2_7000HC))
-        specific.add_options()("7000", "set device type to LCMXO2-7000HC");
-
-    specific.add_options()("package", po::value<std::string>(), "select device package");
-    specific.add_options()("speed", po::value<int>(), "select device speedgrade (1 to 6 inclusive)");
-
-    specific.add_options()("override-basecfg", po::value<std::string>(),
-                           "base chip configuration in Trellis text format");
+    specific.add_options()("device", po::value<std::string>(), "device name");
+    specific.add_options()("list-devices", "list all supported device names");
     specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
-
     // specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
 
     return specific;
@@ -84,28 +67,14 @@ void MachXO2CommandHandler::customBitstream(Context *ctx)
 std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string, Property> &values)
 {
     ArchArgs chipArgs;
-    chipArgs.type = ArchArgs::NONE;
-    if (vm.count("256"))
-        chipArgs.type = ArchArgs::LCMXO2_256HC;
-    if (vm.count("640"))
-        chipArgs.type = ArchArgs::LCMXO2_640HC;
-    if (vm.count("1200"))
-        chipArgs.type = ArchArgs::LCMXO2_1200HC;
-    if (vm.count("2000"))
-        chipArgs.type = ArchArgs::LCMXO2_2000HC;
-    if (vm.count("4000"))
-        chipArgs.type = ArchArgs::LCMXO2_4000HC;
-    if (vm.count("7000"))
-        chipArgs.type = ArchArgs::LCMXO2_7000HC;
-    if (vm.count("package"))
-        chipArgs.package = vm["package"].as<std::string>();
-
-    if (values.find("arch.name") != values.end()) {
-        std::string arch_name = values["arch.name"].as_string();
-        if (arch_name != "machxo2")
-            log_error("Unsuported architecture '%s'.\n", arch_name.c_str());
+    if (vm.count("list-devices")) {
+        Arch::list_devices();
+        exit(0);
     }
-
+    if (!vm.count("device")) {
+        log_error("device must be specified on the command line (e.g. --device LCMXO2-7000HC-4TG144I)\n");
+    }
+    chipArgs.device = vm["device"].as<std::string>();
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     return ctx;
 }
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 56efb63fe5..a9ca00f28d 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -308,7 +308,7 @@ static void pack_io(Context *ctx)
                 BelId pinBel = ctx->getPackagePinBel(pin);
                 if (pinBel == BelId()) {
                     log_error("IO buffer '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
-                              ci->name.c_str(ctx), pin.c_str(), ctx->args.package.c_str());
+                              ci->name.c_str(ctx), pin.c_str(), ctx->package_name);
                 } else {
                     log_info("pin '%s' constrained to Bel '%s'.\n", ci->name.c_str(ctx), ctx->nameOfBel(pinBel));
                 }

From 26798038fe5dc3f9063cd1cc11e67f64df582c3a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 Mar 2023 11:05:20 +0100
Subject: [PATCH 297/712] Fix examples

---
 machxo2/examples/demo-vhdl.sh | 2 +-
 machxo2/examples/demo.sh      | 4 ++--
 machxo2/examples/mitertest.sh | 2 +-
 machxo2/examples/simple.sh    | 2 +-
 machxo2/examples/simtest.sh   | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/machxo2/examples/demo-vhdl.sh b/machxo2/examples/demo-vhdl.sh
index ed1f7d8044..054b8585dd 100644
--- a/machxo2/examples/demo-vhdl.sh
+++ b/machxo2/examples/demo-vhdl.sh
@@ -19,6 +19,6 @@ set -ex
 ${YOSYS:-yosys} -p "ghdl --std=08 prims.vhd ${1}.vhd -e;
                     attrmap -tocase LOC
                     synth_machxo2 -json ${1}-vhdl.json"
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --json $1-vhdl.json --textcfg $1-vhdl.txt
+${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1-vhdl.json --textcfg $1-vhdl.txt
 ecppack --compress $DB_ARG $1-vhdl.txt $1-vhdl.bit
 tinyproga -b $1-vhdl.bit
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
index 634fbb4dfd..8e8a49a6d0 100644
--- a/machxo2/examples/demo.sh
+++ b/machxo2/examples/demo.sh
@@ -16,7 +16,7 @@ fi
 
 set -ex
 
-${YOSYS:-yosys} -p "synth_machxo2 -json $1.json" $1.v
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --json $1.json --textcfg $1.txt
+${YOSYS:-yosys} -p "read_verilog  $1.v; synth_machxo2 -json $1.json"
+${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1.json --textcfg $1.txt
 ecppack --compress $DB_ARG $1.txt $1.bit
 tinyproga -b $1.bit
diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index b7ec2695d0..161eaa8861 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -73,7 +73,7 @@ set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 69706b9c3f..4037fa6f1c 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -26,7 +26,7 @@ set -ex
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json
                     show -format png -prefix ${1}"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index 0adf175163..eb97719bdd 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -30,7 +30,7 @@ set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -json ${1}.json"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --json ${1}.json --write ${2}${1}.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge

From 1f115ddd320dc5e2f9c69e32ee2e40b758285f6e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 9 Mar 2023 11:34:15 +0100
Subject: [PATCH 298/712] Basic GUI part selection

---
 gui/machxo2/mainwindow.cc | 53 ++++++++++++++++++++++++---------------
 machxo2/arch.cc           |  4 +--
 machxo2/main.cc           |  2 +-
 3 files changed, 36 insertions(+), 23 deletions(-)

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index b92f752c6a..851caacf2e 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -21,6 +21,8 @@
 #include <fstream>
 #include "bitstream.h"
 #include "log.h"
+#include "embed.h"
+#include "chipdb/available.h"
 
 #include <QFileDialog>
 #include <QInputDialog>
@@ -78,30 +80,41 @@ void MainWindow::createMenu()
 
 void MainWindow::new_proj()
 {
-/*  QMap<QString, int> arch;
+    QList<QString> arch;
+
+    std::stringstream ss(available_devices);
+    std::string name;
+    while(getline(ss, name, ';')){ 
+        std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
+        auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
+        if (!db_ptr)
+            continue; // chipdb not available
+        for (auto &chip : db_ptr->get()->variants) {
+            for (auto &pkg : chip.packages) {
+                for (auto &speedgrade : chip.speed_grades) {
+                    for (auto &rating : chip.suffixes) {
+                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        arch.append(QString::fromLocal8Bit(devname.c_str()));
+                    }
+                }
+            }
+        }
+    }
+
     bool ok;
-    QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
+    QString item = QInputDialog::getItem(this, "Select new context", "Part:", arch, 0, false, &ok);
     if (ok && !item.isEmpty()) {
         ArchArgs chipArgs;
-        chipArgs.type = (ArchArgs::ArchArgsTypes)arch.value(item);
-
-        QStringList packages;
-        for (auto package : Arch::get_supported_packages(chipArgs.type))
-            packages.append(QLatin1String(package.data(), package.size()));
-        QString package = QInputDialog::getItem(this, "Select package", "Package:", packages, 0, false, &ok);
-
-        if (ok && !item.isEmpty()) {
-            handler->clear();
-            currentProj = "";
-            disableActions();
-            chipArgs.package = package.toStdString().c_str();
-            ctx = std::unique_ptr<Context>(new Context(chipArgs));
-            actionLoadJSON->setEnabled(true);
-
-            Q_EMIT contextChanged(ctx.get());
-        }
+        chipArgs.device = item.toUtf8().constData();;
+
+        handler->clear();
+        currentProj = "";
+        disableActions();
+        ctx = std::unique_ptr<Context>(new Context(chipArgs));
+        actionLoadJSON->setEnabled(true);
+
+        Q_EMIT contextChanged(ctx.get());
     }
-*/
 }
 
 void MainWindow::open_lpf()
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 481d15eecf..385b776f2d 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -58,8 +58,8 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
             for (auto &pkg : chip.packages) {
                 for (auto &speedgrade : chip.speed_grades) {
                     for (auto &rating : chip.suffixes) {
-                        std::string name = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
-                        if (device == name) {
+                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        if (device == devname) {
                             *chip_info = db_ptr->get();
                             *package_info = nullptr;
                             *package_name = pkg.name.get();
diff --git a/machxo2/main.cc b/machxo2/main.cc
index e5b8176a58..283bc59c16 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -72,7 +72,7 @@ std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string,
         exit(0);
     }
     if (!vm.count("device")) {
-        log_error("device must be specified on the command line (e.g. --device LCMXO2-7000HC-4TG144I)\n");
+        log_error("device must be specified on the command line (e.g. --device LCMXO2-1200HC-4SG32C)\n");
     }
     chipArgs.device = vm["device"].as<std::string>();
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));

From 6eb5f2a77e23a89d0876dd041ebe5871ff6b65ce Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 10 Mar 2023 15:29:59 +0100
Subject: [PATCH 299/712] Enable wires and add dummy wire type for now

---
 gui/designwidget.cc      |  5 +++++
 machxo2/CMakeLists.txt   |  2 ++
 machxo2/arch.h           |  3 ++-
 machxo2/constids.inc     |  3 +++
 machxo2/facade_import.py | 31 +++++++++++++++++++++++++------
 5 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index bd2578de66..57591bbfe7 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -318,6 +318,11 @@ void DesignWidget::newContext(Context *ctx)
                 wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
             }
 #endif
+#ifdef ARCH_MACHXO2
+            for (const auto &wire : ctx->getWires()) {
+                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
+            }
+#endif
 #ifdef ARCH_GOWIN
             for (const auto &wire : ctx->getWires()) {
                 WireInfo wi = ctx->wire_info(wire);
diff --git a/machxo2/CMakeLists.txt b/machxo2/CMakeLists.txt
index 4d54f2fa6f..414c6571ca 100644
--- a/machxo2/CMakeLists.txt
+++ b/machxo2/CMakeLists.txt
@@ -62,6 +62,7 @@ else()
                 -L ${TRELLIS_DATADIR}/util/common
                 -L ${TRELLIS_DATADIR}/timing/util
                 -p ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+                -g ${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
                 ${device}
                 > ${device_bba}.new
             # atomically update
@@ -69,6 +70,7 @@ else()
             DEPENDS
                 ${CMAKE_CURRENT_SOURCE_DIR}/facade_import.py
                 ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+                ${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
                 ${PREVIOUS_CHIPDB_TARGET}
             VERBATIM)
         list(APPEND all_device_bbas ${device_bba})
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 4e0ed2fd15..3eaa068411 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -74,7 +74,8 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
 
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
-    int32_t tile_wire;
+    int16_t type;
+    int16_t tile_wire;
     int32_t num_uphill;
     int32_t num_downhill;
     RelPtr<PipLocatorPOD> pips_uphill;
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 58319e4551..40d96fb838 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -123,6 +123,9 @@ X(IO_TYPE)
 X(LOC)
 X(NOM_FREQ)
 X(VCC)
+
+X(WIRE_TYPE_NONE)
+
 X(machxo2)
 X(pack)
 X(place)
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 9a001e4e42..b83f547d31 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -5,6 +5,8 @@
 from os import path
 
 tiletype_names = dict()
+gfx_wire_ids = dict()
+gfx_wire_names = list()
 
 parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
 parser.add_argument("device", type=str, help="target device")
@@ -17,6 +19,24 @@
 import pytrellis
 import database
 
+with open(args.gfxh) as f:
+    state = 0
+    for line in f:
+        if state == 0 and line.startswith("enum GfxTileWireId"):
+            state = 1
+        elif state == 1 and line.startswith("};"):
+            state = 0
+        elif state == 1 and (line.startswith("{") or line.strip() == ""):
+            pass
+        elif state == 1:
+            idx = len(gfx_wire_ids)
+            name = line.strip().rstrip(",")
+            gfx_wire_ids[name] = idx
+            gfx_wire_names.append(name)
+
+def wire_type(name):
+    return "WIRE_TYPE_NONE"
+
 # Get the index for a tiletype
 def get_tiletype_index(name):
     if name in tiletype_names:
@@ -283,12 +303,11 @@ def get_wire_name(loc, idx):
             for wire_idx in range(len(t.wires)):
                 wire = t.wires[wire_idx]
                 bba.s(rg.to_str(wire.name), "name")
-                # TODO: Padding until GUI support is added.
-                # bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
-                # if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
-                #     bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
-                # else:
-                bba.u32(0, "tile_wire")
+                bba.u16(constids[wire_type(rg.to_str(wire.name))], "type")
+                if ("TILE_WIRE_" + rg.to_str(wire.name)) in gfx_wire_ids:
+                    bba.u16(gfx_wire_ids["TILE_WIRE_" + rg.to_str(wire.name)], "tile_wire")
+                else:
+                    bba.u16(0, "tile_wire")
                 bba.u32(len(wire.arcsUphill), "num_uphill")
                 bba.u32(len(wire.arcsDownhill), "num_downhill")
                 bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")

From f008d7c4d802b3806f0a1fb2dab32e73ef7ff0ed Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 13 Mar 2023 12:45:12 +0100
Subject: [PATCH 300/712] Let top tiles be on top

---
 machxo2/arch.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 385b776f2d..75566aed19 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -416,7 +416,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         int y = decal.location.y;
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
         GfxTileWireId tilewire = GfxTileWireId(tile_info(wire)->wire_data[wire.index].tile_wire);
-        gfxTileWire(ret, x, y, chip_info->width, chip_info->height, wire_type, tilewire, style);
+        gfxTileWire(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, wire_type, tilewire, style);
     } else if (decal.type == DecalId::TYPE_PIP) {
         PipId pip;
         pip.index = decal.z;
@@ -428,7 +428,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         GfxTileWireId src_id = GfxTileWireId(tile_info(src_wire)->wire_data[src_wire.index].tile_wire);
         GfxTileWireId dst_id = GfxTileWireId(tile_info(dst_wire)->wire_data[dst_wire.index].tile_wire);
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
-        gfxTilePip(ret, x, y, chip_info->width, chip_info->height, src_wire, getWireType(src_wire), src_id, dst_wire,
+        gfxTilePip(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, src_wire, getWireType(src_wire), src_id, dst_wire,
                    getWireType(dst_wire), dst_id, style);
     } else if (decal.type == DecalId::TYPE_BEL) {
         BelId bel;
@@ -439,7 +439,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         int y = decal.location.y;
         int z = tile_info(bel)->bel_data[bel.index].z;
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
-        gfxTileBel(ret, x, y, z, chip_info->width, chip_info->height, bel_type, style);
+        gfxTileBel(ret, x, chip_info->height - y - 1, z, chip_info->width, chip_info->height, bel_type, style);
     }
 
     return ret;

From 11a90aff838ced1cea5c78cea8ed0c6ddcfd6cbd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 Mar 2023 07:43:56 +0100
Subject: [PATCH 301/712] Fix out of tree builds  and place h in generated

---
 gui/machxo2/mainwindow.cc                          | 2 +-
 machxo2/arch.cc                                    | 2 +-
 machxo2/family.cmake                               | 4 ++--
 machxo2/{available.h.in => machxo2_available.h.in} | 0
 4 files changed, 4 insertions(+), 4 deletions(-)
 rename machxo2/{available.h.in => machxo2_available.h.in} (100%)

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 851caacf2e..4a7ffeafa3 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -22,7 +22,7 @@
 #include "bitstream.h"
 #include "log.h"
 #include "embed.h"
-#include "chipdb/available.h"
+#include "machxo2_available.h"
 
 #include <QFileDialog>
 #include <QInputDialog>
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 75566aed19..e0ddd0d564 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -28,7 +28,7 @@
 #include "router1.h"
 #include "router2.h"
 #include "util.h"
-#include "chipdb/available.h"
+#include "machxo2_available.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
diff --git a/machxo2/family.cmake b/machxo2/family.cmake
index 43b1a9b220..604c91f396 100644
--- a/machxo2/family.cmake
+++ b/machxo2/family.cmake
@@ -48,9 +48,9 @@ target_compile_options(chipdb-${family} PRIVATE -g0 -O0 -w)
 target_compile_definitions(chipdb-${family} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
 target_include_directories(chipdb-${family} PRIVATE ${family})
 
-configure_file(${family}/available.h.in ${family}/chipdb/available.h)
+configure_file(${family}/machxo2_available.h.in ${CMAKE_CURRENT_BINARY_DIR}/generated/machxo2_available.h)
 
 foreach(family_target ${family_targets})
     target_sources(${family_target} PRIVATE $<TARGET_OBJECTS:chipdb-${family}>)
-    target_sources(${family_target} PRIVATE ${family}/chipdb/available.h)
+    target_sources(${family_target} PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/generated/machxo2_available.h)
 endforeach()
diff --git a/machxo2/available.h.in b/machxo2/machxo2_available.h.in
similarity index 100%
rename from machxo2/available.h.in
rename to machxo2/machxo2_available.h.in

From d337ab93e6147703b73db1998f3e0048d8974565 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 Mar 2023 13:02:29 +0100
Subject: [PATCH 302/712] Update to latest prjtrellis

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 345ff456fc..5c46d92ff5 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: 48486ebd1e03e4ac42c96299e881adf9d43bc241
+      TRELLIS_REVISION: ce6b1f75801dc93dd7490f28cc3bb8d9f644720f
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1

From 656bfdb8199c9b36e7a064d7dd8d287069142287 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 Mar 2023 14:54:21 +0100
Subject: [PATCH 303/712] Update prjtrellis to latest

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 5c46d92ff5..9cb65f122b 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: ce6b1f75801dc93dd7490f28cc3bb8d9f644720f
+      TRELLIS_REVISION: 6280c4d1e73b50935b61b24dbaaf2a6a355be001
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1

From 4111cc25d653bde9fbda72b9cf9dc13a876e214a Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Mar 2023 09:31:38 +0100
Subject: [PATCH 304/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 gui/machxo2/mainwindow.cc | 13 ++++++++-----
 machxo2/arch.cc           | 19 +++++++++++--------
 machxo2/arch.h            |  8 ++------
 machxo2/bitstream.cc      |  2 +-
 machxo2/gfx.cc            | 16 +++++++---------
 5 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 4a7ffeafa3..9b7cfb17bc 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -20,8 +20,8 @@
 #include "mainwindow.h"
 #include <fstream>
 #include "bitstream.h"
-#include "log.h"
 #include "embed.h"
+#include "log.h"
 #include "machxo2_available.h"
 
 #include <QFileDialog>
@@ -49,7 +49,8 @@ MainWindow::~MainWindow() {}
 
 void MainWindow::newContext(Context *ctx)
 {
-    std::string title = "nextpnr-machxo2 - " + std::string(ctx->device_name) + " (" + std::string(ctx->package_name) + ") - Part : " + ctx->getChipName();
+    std::string title = "nextpnr-machxo2 - " + std::string(ctx->device_name) + " (" + std::string(ctx->package_name) +
+                        ") - Part : " + ctx->getChipName();
     setWindowTitle(title.c_str());
 }
 
@@ -84,7 +85,7 @@ void MainWindow::new_proj()
 
     std::stringstream ss(available_devices);
     std::string name;
-    while(getline(ss, name, ';')){ 
+    while (getline(ss, name, ';')) {
         std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
         auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
         if (!db_ptr)
@@ -93,7 +94,8 @@ void MainWindow::new_proj()
             for (auto &pkg : chip.packages) {
                 for (auto &speedgrade : chip.speed_grades) {
                     for (auto &rating : chip.suffixes) {
-                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
+                                                      pkg.short_name.get(), rating.suffix.get());
                         arch.append(QString::fromLocal8Bit(devname.c_str()));
                     }
                 }
@@ -105,7 +107,8 @@ void MainWindow::new_proj()
     QString item = QInputDialog::getItem(this, "Select new context", "Part:", arch, 0, false, &ok);
     if (ok && !item.isEmpty()) {
         ArchArgs chipArgs;
-        chipArgs.device = item.toUtf8().constData();;
+        chipArgs.device = item.toUtf8().constData();
+        ;
 
         handler->clear();
         currentProj = "";
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index e0ddd0d564..60e2203cb8 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -22,13 +22,13 @@
 #include <math.h>
 #include "embed.h"
 #include "gfx.h"
+#include "machxo2_available.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
 #include "router1.h"
 #include "router2.h"
 #include "util.h"
-#include "machxo2_available.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -45,11 +45,12 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 
 // ---------------------------------------------------------------
 
-static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info, const char **device_name, const char **package_name)
+static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
+                          const char **device_name, const char **package_name)
 {
     std::stringstream ss(available_devices);
     std::string name;
-    while(getline(ss, name, ';')){ 
+    while (getline(ss, name, ';')) {
         std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
         auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
         if (!db_ptr)
@@ -58,7 +59,8 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
             for (auto &pkg : chip.packages) {
                 for (auto &speedgrade : chip.speed_grades) {
                     for (auto &rating : chip.suffixes) {
-                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
+                                                      pkg.short_name.get(), rating.suffix.get());
                         if (device == devname) {
                             *chip_info = db_ptr->get();
                             *package_info = nullptr;
@@ -118,7 +120,7 @@ void Arch::list_devices()
     log("Supported devices: \n");
     std::stringstream ss(available_devices);
     std::string name;
-    while(getline(ss, name, ';')){ 
+    while (getline(ss, name, ';')) {
         std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
         auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
         if (!db_ptr)
@@ -127,7 +129,8 @@ void Arch::list_devices()
             for (auto &pkg : chip.packages) {
                 for (auto &speedgrade : chip.speed_grades) {
                     for (auto &rating : chip.suffixes) {
-                        log("    %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(), rating.suffix.get());
+                        log("    %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(),
+                            rating.suffix.get());
                     }
                 }
             }
@@ -428,8 +431,8 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         GfxTileWireId src_id = GfxTileWireId(tile_info(src_wire)->wire_data[src_wire.index].tile_wire);
         GfxTileWireId dst_id = GfxTileWireId(tile_info(dst_wire)->wire_data[dst_wire.index].tile_wire);
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
-        gfxTilePip(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, src_wire, getWireType(src_wire), src_id, dst_wire,
-                   getWireType(dst_wire), dst_id, style);
+        gfxTilePip(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, src_wire,
+                   getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire), dst_id, style);
     } else if (decal.type == DecalId::TYPE_BEL) {
         BelId bel;
         bel.index = decal.z;
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 3eaa068411..efb5ee418f 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -129,13 +129,9 @@ NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
     RelPtr<char> short_name;
 });
 
-NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD {
-    RelPtr<char> suffix;
-});
+NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr<char> suffix; });
 
-NPNR_PACKED_STRUCT(struct SpeedSupportedPOD {
-    int32_t speed;
-});
+NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { int32_t speed; });
 
 NPNR_PACKED_STRUCT(struct VariantInfoPOD {
     RelPtr<char> name;
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index c04df52e97..232598f3a8 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -195,7 +195,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
 {
     ChipConfig cc;
     IdString base_id = ctx->id(ctx->chip_info->device_name.get());
-    //IdString device_id = ctx->id(ctx->device_name);
+    // IdString device_id = ctx->id(ctx->device_name);
     if (base_id == ctx->id("LCMXO2-1200"))
         BaseConfigs::config_empty_lcmxo2_1200(cc);
     else
diff --git a/machxo2/gfx.cc b/machxo2/gfx.cc
index 97876ad202..08b2e01d1b 100644
--- a/machxo2/gfx.cc
+++ b/machxo2/gfx.cc
@@ -23,7 +23,7 @@ NEXTPNR_NAMESPACE_BEGIN
 
 const float slice_x1 = 0.800;
 const float slice_x2_comb = 0.927;
-//const float slice_x1_ff = 0.933;
+// const float slice_x1_ff = 0.933;
 const float slice_x2 = 0.94;
 const float slice_y1 = 0.60;
 const float slice_y2 = 0.65 + 0.1 / 4;
@@ -37,7 +37,6 @@ const float io_cell_h_x1 = 0.05;
 const float io_cell_h_y1 = 0.05;
 const float io_cell_h_y2 = 0.24;
 
-
 void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int h, IdString bel_type,
                 GraphicElement::style_t style)
 {
@@ -50,12 +49,12 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
         el.y1 = y + slice_y1 + z * slice_pitch;
         el.y2 = y + slice_y2 + z * slice_pitch;
         g.push_back(el);
-/*    } else if (bel_type == id_FACADE_FF) {
-        el.x1 = x + slice_x1_ff;
-        el.x2 = x + slice_x2;
-        el.y1 = y + slice_y1 + z * slice_pitch;
-        el.y2 = y + slice_y2 + z * slice_pitch;
-        g.push_back(el);*/
+        /*    } else if (bel_type == id_FACADE_FF) {
+                el.x1 = x + slice_x1_ff;
+                el.x2 = x + slice_x2;
+                el.y1 = y + slice_y1 + z * slice_pitch;
+                el.y2 = y + slice_y2 + z * slice_pitch;
+                g.push_back(el);*/
     } else if (bel_type.in(id_FACADE_IO)) {
         bool top_bottom = (y == 0 || y == (h - 1));
         if (top_bottom) {
@@ -88,7 +87,6 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS
 {
 }
 
-
 void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, WireId src, IdString src_type,
                 GfxTileWireId src_id, WireId dst, IdString dst_type, GfxTileWireId dst_id,
                 GraphicElement::style_t style)

From e4fcd3740dd8a650922903db6e15f4eaff25b5ee Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Mar 2023 09:27:36 +0100
Subject: [PATCH 305/712] cmake: Make HeAP placer always-enabled

Signed-off-by: gatecat <gatecat@ds0.me>
---
 CMakeLists.txt              |  8 ++------
 README.md                   |  2 +-
 common/place/placer_heap.cc | 21 ---------------------
 ecp5/arch.cc                | 12 ++----------
 fpga_interchange/arch.cc    | 10 +---------
 generic/arch.cc             | 12 ++----------
 gowin/arch.cc               | 10 +---------
 ice40/arch.cc               | 12 ++----------
 machxo2/README.md           |  2 +-
 machxo2/arch.cc             | 12 ++----------
 mistral/arch.cc             | 12 ++----------
 nexus/arch.cc               | 11 +----------
 12 files changed, 17 insertions(+), 107 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index f48a894cee..4018cc3efe 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -14,7 +14,6 @@ check_ipo_supported(RESULT ipo_supported)
 option(BUILD_GUI "Build GUI" OFF)
 option(BUILD_PYTHON "Build Python Integration" ON)
 option(BUILD_TESTS "Build tests" OFF)
-option(BUILD_HEAP "Build HeAP analytic placer" ON)
 option(USE_OPENMP "Use OpenMP to accelerate analytic placer" OFF)
 option(COVERAGE "Add code coverage info" OFF)
 option(STATIC_BUILD "Create static build" OFF)
@@ -230,11 +229,8 @@ endif()
 
 include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${Python3_INCLUDE_DIRS})
 
-if(BUILD_HEAP)
-    find_package (Eigen3 REQUIRED NO_MODULE)
-    link_libraries(Eigen3::Eigen)
-    add_definitions(-DWITH_HEAP)
-endif()
+find_package (Eigen3 REQUIRED NO_MODULE)
+link_libraries(Eigen3::Eigen)
 
 aux_source_directory(common/kernel/ KERNEL_SRC_FILES)
 aux_source_directory(common/place/ PLACE_SRC_FILES)
diff --git a/README.md b/README.md
index 47201dc5bb..ca0ef1e50b 100644
--- a/README.md
+++ b/README.md
@@ -195,7 +195,7 @@ Additional notes for building nextpnr
 The following runs a debug build of the iCE40 architecture without GUI, without Python support, without the HeAP analytic placer and only HX1K support:
 
 ```
-cmake . -DARCH=ice40 -DCMAKE_BUILD_TYPE=Debug -DBUILD_PYTHON=OFF  -DBUILD_HEAP=OFF -DICE40_HX1K_ONLY=1
+cmake . -DARCH=ice40 -DCMAKE_BUILD_TYPE=Debug -DBUILD_PYTHON=OFF -DICE40_HX1K_ONLY=1
 make -j$(nproc)
 ```
 
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 2958405fe9..1ed7142692 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -31,8 +31,6 @@
  *   - To make the placer timing-driven, the bound2bound weights are multiplied by (1 + 10 * crit^2)
  */
 
-#ifdef WITH_HEAP
-
 #include "placer_heap.h"
 #include <Eigen/Core>
 #include <Eigen/IterativeLinearSolvers>
@@ -1842,22 +1840,3 @@ PlacerHeapCfg::PlacerHeapCfg(Context *ctx)
 }
 
 NEXTPNR_NAMESPACE_END
-
-#else
-
-#include "log.h"
-#include "nextpnr.h"
-#include "placer_heap.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-bool placer_heap(Context *ctx, PlacerHeapCfg cfg)
-{
-    log_error("nextpnr was built without the HeAP placer\n");
-    return false;
-}
-
-PlacerHeapCfg::PlacerHeapCfg(Context *ctx) {}
-
-NEXTPNR_NAMESPACE_END
-
-#endif
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index a7041e0405..11429eb46e 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -1238,17 +1238,9 @@ WireId Arch::get_bank_eclk(int bank, int eclk)
     return get_wire_by_loc_basename(Location(0, 0), "G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(eclk));
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
-
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 2682010ffc..5af07f043c 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1116,17 +1116,9 @@ std::string Arch::get_part() const
 
 // -----------------------------------------------------------------------
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
 
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router2";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/generic/arch.cc b/generic/arch.cc
index 579140b901..c0575b87df 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -707,17 +707,9 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
     return cellsCompatible(cells.data(), int(cells.size()));
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
-
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 1629d653bf..042e7a62c3 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2341,17 +2341,9 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
     return cellsCompatible(cells.data(), int(cells.size()));
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
 
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 6a80a6ff5f..e977008a02 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -1289,17 +1289,9 @@ BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
     return bb;
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
-
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/machxo2/README.md b/machxo2/README.md
index 55cc5763d7..37dfb991e0 100644
--- a/machxo2/README.md
+++ b/machxo2/README.md
@@ -81,7 +81,7 @@ git clone git@github.com:cr1901/nextpnr.git
 cd nextpnr
 git checkout machxo2
 git submodule update --init --recursive
-cmake . -DARCH=machxo2 -DBUILD_GUI=OFF  -DTRELLIS_INSTALL_PREFIX=/usr -DBUILD_PYTHON=OFF -DBUILD_HEAP=OFF
+cmake . -DARCH=machxo2 -DBUILD_GUI=OFF  -DTRELLIS_INSTALL_PREFIX=/usr -DBUILD_PYTHON=OFF 
 make
 ```
 
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 60e2203cb8..82dd51fd9b 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -486,17 +486,9 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
     return true;
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
-
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/mistral/arch.cc b/mistral/arch.cc
index f3e385d12a..05d780f304 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -499,17 +499,9 @@ bool Arch::route()
     return result;
 }
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
-
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-};
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router2";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 187e531286..4818906d05 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -1122,18 +1122,9 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
 
 // -----------------------------------------------------------------------
 
-#ifdef WITH_HEAP
 const std::string Arch::defaultPlacer = "heap";
-#else
-const std::string Arch::defaultPlacer = "sa";
-#endif
 
-const std::vector<std::string> Arch::availablePlacers = {"sa",
-#ifdef WITH_HEAP
-                                                         "heap"
-#endif
-
-};
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
 const std::string Arch::defaultRouter = "router2";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};

From ad5f6fccaa4484eb02d3fa6d420ff39517b524e6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 17 Mar 2023 18:58:04 +0100
Subject: [PATCH 306/712] Use RelSlice, make more in line with ecp5 arch

---
 machxo2/arch.cc          |  76 ++++++++++-------------
 machxo2/arch.h           | 129 ++++++++++++++++++---------------------
 machxo2/bitstream.cc     |  12 ++--
 machxo2/facade_import.py |  42 +++++--------
 4 files changed, 113 insertions(+), 146 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 82dd51fd9b..639f6c6b6c 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -66,9 +66,9 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
                             *package_info = nullptr;
                             *package_name = pkg.name.get();
                             *device_name = chip.name.get();
-                            for (int i = 0; i < (*chip_info)->num_packages; i++) {
-                                if (pkg.name.get() == (*chip_info)->package_info[i].name.get()) {
-                                    *package_info = &((*chip_info)->package_info[i]);
+                            for (auto &pi : db_ptr->get()->package_info) {
+                                if (pkg.name.get() == pi.name.get()) {
+                                    *package_info = &pi;
                                     break;
                                 }
                             }
@@ -155,7 +155,7 @@ BelId Arch::getBelByName(IdStringList name) const
     loc.y = id_to_y.at(name[1]);
     ret.location = loc;
     const TileTypePOD *loci = tile_info(ret);
-    for (int i = 0; i < loci->num_bels; i++) {
+    for (int i = 0; i < loci->bel_data.ssize(); i++) {
         if (std::strcmp(loci->bel_data[i].name.get(), name[2].c_str(this)) == 0) {
             ret.index = i;
             return ret;
@@ -174,9 +174,9 @@ BelId Arch::getBelByLocation(Loc loc) const
     ret.location.x = loc.x;
     ret.location.y = loc.y;
 
-    const TileTypePOD *tilei = tile_info(ret);
-    for (int i = 0; i < tilei->num_bels; i++) {
-        if (tilei->bel_data[i].z == loc.z) {
+    const TileTypePOD *loci = tile_info(ret);
+    for (int i = 0; i < loci->bel_data.ssize(); i++) {
+        if (loci->bel_data[i].z == loc.z) {
             ret.index = i;
             return ret;
         }
@@ -192,7 +192,7 @@ BelRange Arch::getBelsByTile(int x, int y) const
     br.b.cursor_tile = y * chip_info->width + x;
     br.e.cursor_tile = y * chip_info->width + x;
     br.b.cursor_index = 0;
-    br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].num_bels - 1;
+    br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].bel_data.ssize() - 1;
     br.b.chip = chip_info;
     br.e.chip = chip_info;
     if (br.e.cursor_index == -1)
@@ -208,16 +208,13 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
 {
     NPNR_ASSERT(bel != BelId());
 
-    int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires;
-    const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires;
-
-    for (int i = 0; i < num_bel_wires; i++)
-        if (bel_wires[i].port == pin.index) {
+    for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
+        if (bw.port == pin.index) {
             WireId ret;
 
-            ret.location.x = bel_wires[i].rel_wire_loc.x;
-            ret.location.y = bel_wires[i].rel_wire_loc.y;
-            ret.index = bel_wires[i].wire_index;
+            ret.location.x = bw.rel_wire_loc.x;
+            ret.location.y = bw.rel_wire_loc.y;
+            ret.index = bw.wire_index;
 
             return ret;
         }
@@ -229,12 +226,9 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
 {
     NPNR_ASSERT(bel != BelId());
 
-    int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires;
-    const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires;
-
-    for (int i = 0; i < num_bel_wires; i++)
-        if (bel_wires[i].port == pin.index)
-            return PortType(bel_wires[i].dir);
+    for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
+        if (bw.port == pin.index)
+            return PortType(bw.type);
 
     return PORT_INOUT;
 }
@@ -244,11 +238,9 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
     std::vector<IdString> ret;
     NPNR_ASSERT(bel != BelId());
 
-    int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires;
-    const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires;
-
-    for (int i = 0; i < num_bel_wires; i++) {
-        IdString id(bel_wires[i].port);
+    for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
+        IdString id;
+        id.index = bw.port;
         ret.push_back(id);
     }
 
@@ -259,11 +251,11 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
 
 BelId Arch::getPackagePinBel(const std::string &pin) const
 {
-    for (int i = 0; i < package_info->num_pins; i++) {
-        if (package_info->pin_data[i].name.get() == pin) {
+    for (auto &ppin : package_info->pin_data) {
+        if (ppin.name.get() == pin) {
             BelId bel;
-            bel.location = package_info->pin_data[i].abs_loc;
-            bel.index = package_info->pin_data[i].bel_index;
+            bel.location = ppin.abs_loc;
+            bel.index = ppin.bel_index;
             return bel;
         }
     }
@@ -282,7 +274,7 @@ WireId Arch::getWireByName(IdStringList name) const
     loc.y = id_to_y.at(name[1]);
     ret.location = loc;
     const TileTypePOD *loci = tile_info(ret);
-    for (int i = 0; i < loci->num_wires; i++) {
+    for (int i = 0; i < loci->wire_data.ssize(); i++) {
         if (std::strcmp(loci->wire_data[i].name.get(), name[2].c_str(this)) == 0) {
             ret.index = i;
             return ret;
@@ -308,7 +300,7 @@ PipId Arch::getPipByName(IdStringList name) const
     loc.y = id_to_y.at(name[1]);
     ret.location = loc;
     const TileTypePOD *loci = tile_info(ret);
-    for (int i = 0; i < loci->num_pips; i++) {
+    for (int i = 0; i < loci->pip_data.ssize(); i++) {
         PipId curr;
         curr.location = loc;
         curr.index = i;
@@ -321,13 +313,11 @@ PipId Arch::getPipByName(IdStringList name) const
 
 IdStringList Arch::getPipName(PipId pip) const
 {
-    auto &pip_data = tile_info(pip)->pips_data[pip.index];
+    auto &pip_data = tile_info(pip)->pip_data[pip.index];
     WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
-    const char *src_name = tile_info(src)->wire_data[src.index].name.get();
-    const char *dst_name = tile_info(dst)->wire_data[dst.index].name.get();
-    std::string pip_name =
-            stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x - pip.location.x, pip_data.src.y - pip.location.y, src_name,
-                    pip_data.dst.x - pip.location.x, pip_data.dst.y - pip.location.y, dst_name);
+    std::string pip_name = stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x, pip_data.src.y,
+                                   get_wire_basename(src).c_str(this), pip_data.dst.x, pip_data.dst.y,
+                                   get_wire_basename(dst).c_str(this));
 
     std::array<IdString, 3> ids{x_ids.at(pip.location.x), y_ids.at(pip.location.y), id(pip_name)};
     return IdStringList(ids);
@@ -495,13 +485,13 @@ const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
 bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; }
 
-std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_location(int row, int col)
+std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row, int col)
 {
     std::vector<std::pair<std::string, std::string>> ret;
     auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
-    for (int i = 0; i < tileloc.num_tiles; i++) {
-        ret.push_back(std::make_pair(tileloc.tile_names[i].name.get(),
-                                     chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()));
+    for (auto &tn : tileloc.tile_names) {
+        ret.push_back(std::make_pair(tn.name.get(),
+                                     chip_info->tiletype_names[tn.type_idx].get()));
     }
     return ret;
 }
diff --git a/machxo2/arch.h b/machxo2/arch.h
index efb5ee418f..8cb8accc93 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -39,20 +39,14 @@ NPNR_PACKED_STRUCT(struct BelWirePOD {
     LocationPOD rel_wire_loc;
     int32_t wire_index;
     int32_t port;
-    int32_t dir; // FIXME: Corresponds to "type" in ECP5.
+    int32_t type;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
     RelPtr<char> name;
     int32_t type;
     int32_t z;
-    int32_t num_bel_wires;
-    RelPtr<BelWirePOD> bel_wires;
-});
-
-NPNR_PACKED_STRUCT(struct PipLocatorPOD {
-    LocationPOD rel_loc;
-    int32_t index;
+    RelSlice<BelWirePOD> bel_wires;
 });
 
 NPNR_PACKED_STRUCT(struct BelPortPOD {
@@ -62,35 +56,39 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 });
 
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
-    LocationPOD src;
-    LocationPOD dst;
-    int32_t src_idx;
-    int32_t dst_idx;
+    LocationPOD src, dst;
+    int32_t src_idx, dst_idx;
     int32_t timing_class;
     int16_t tile_type;
     int8_t pip_type;
     int8_t padding;
 });
 
+NPNR_PACKED_STRUCT(struct PipLocatorPOD {
+    LocationPOD rel_loc;
+    int32_t index;
+});
+
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
     int16_t type;
     int16_t tile_wire;
-    int32_t num_uphill;
-    int32_t num_downhill;
-    RelPtr<PipLocatorPOD> pips_uphill;
-    RelPtr<PipLocatorPOD> pips_downhill;
-    int32_t num_bel_pins;
-    RelPtr<BelPortPOD> bel_pins;
+    RelSlice<PipLocatorPOD> pips_uphill, pips_downhill;
+    RelSlice<BelPortPOD> bel_pins;
 });
 
 NPNR_PACKED_STRUCT(struct TileTypePOD {
-    int32_t num_bels;
-    int32_t num_wires;
-    int32_t num_pips;
-    RelPtr<BelInfoPOD> bel_data;
-    RelPtr<WireInfoPOD> wire_data;
-    RelPtr<PipInfoPOD> pips_data;
+    RelSlice<BelInfoPOD> bel_data;
+    RelSlice<WireInfoPOD> wire_data;
+    RelSlice<PipInfoPOD> pip_data;
+});
+
+NPNR_PACKED_STRUCT(struct PIOInfoPOD {
+    LocationPOD abs_loc;
+    int32_t bel_index;
+    RelPtr<char> function_name;
+    int16_t bank;
+    int16_t dqsgroup;
 });
 
 NPNR_PACKED_STRUCT(struct PackagePinPOD {
@@ -101,16 +99,7 @@ NPNR_PACKED_STRUCT(struct PackagePinPOD {
 
 NPNR_PACKED_STRUCT(struct PackageInfoPOD {
     RelPtr<char> name;
-    int32_t num_pins;
-    RelPtr<PackagePinPOD> pin_data;
-});
-
-NPNR_PACKED_STRUCT(struct PIOInfoPOD {
-    LocationPOD abs_loc;
-    int32_t bel_index;
-    RelPtr<char> function_name;
-    int16_t bank;
-    int16_t dqsgroup;
+    RelSlice<PackagePinPOD> pin_data;
 });
 
 NPNR_PACKED_STRUCT(struct TileNamePOD {
@@ -119,10 +108,7 @@ NPNR_PACKED_STRUCT(struct TileNamePOD {
     int16_t padding;
 });
 
-NPNR_PACKED_STRUCT(struct TileInfoPOD {
-    int32_t num_tiles;
-    RelPtr<TileNamePOD> tile_names;
-});
+NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice<TileNamePOD> tile_names; });
 
 NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
     RelPtr<char> name;
@@ -145,13 +131,12 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<char> device_name;
     int32_t width, height;
     int32_t num_tiles;
-    int32_t num_packages, num_pios;
     int32_t const_id_count;
-    RelPtr<TileTypePOD> tiles;
-    RelPtr<RelPtr<char>> tiletype_names;
-    RelPtr<PackageInfoPOD> package_info;
-    RelPtr<PIOInfoPOD> pio_info;
-    RelPtr<TileInfoPOD> tile_info;
+    RelSlice<TileTypePOD> tiles;
+    RelSlice<RelPtr<char>> tiletype_names;
+    RelSlice<PackageInfoPOD> package_info;
+    RelSlice<PIOInfoPOD> pio_info;
+    RelSlice<TileInfoPOD> tile_info;
     RelSlice<VariantInfoPOD> variants;
 });
 
@@ -168,7 +153,7 @@ struct BelIterator
     BelIterator operator++()
     {
         cursor_index++;
-        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_bels) {
+        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].bel_data.ssize()) {
             cursor_index = 0;
             cursor_tile++;
         }
@@ -243,7 +228,7 @@ struct WireIterator
     WireIterator operator++()
     {
         cursor_index++;
-        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_wires) {
+        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].wire_data.ssize()) {
             cursor_index = 0;
             cursor_tile++;
         }
@@ -293,7 +278,7 @@ struct AllPipIterator
     AllPipIterator operator++()
     {
         cursor_index++;
-        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_pips) {
+        while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].pip_data.ssize()) {
             cursor_index = 0;
             cursor_tile++;
         }
@@ -518,13 +503,15 @@ struct Arch : BaseArch<ArchRanges>
     {
         BelPinRange range;
         NPNR_ASSERT(wire != WireId());
-        range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.get();
+        range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin();
         range.b.wire_loc = wire.location;
-        range.e.ptr = range.b.ptr + tile_info(wire)->wire_data[wire.index].num_bel_pins;
+        range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end();
         range.e.wire_loc = wire.location;
         return range;
     }
 
+    IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); }
+
     // Pips
     PipId getPipByName(IdStringList name) const override;
     IdStringList getPipName(PipId pip) const override;
@@ -558,8 +545,8 @@ struct Arch : BaseArch<ArchRanges>
     {
         WireId wire;
         NPNR_ASSERT(pip != PipId());
-        wire.index = tile_info(pip)->pips_data[pip.index].src_idx;
-        wire.location = tile_info(pip)->pips_data[pip.index].src;
+        wire.index = tile_info(pip)->pip_data[pip.index].src_idx;
+        wire.location = tile_info(pip)->pip_data[pip.index].src;
         return wire;
     }
 
@@ -567,8 +554,8 @@ struct Arch : BaseArch<ArchRanges>
     {
         WireId wire;
         NPNR_ASSERT(pip != PipId());
-        wire.index = tile_info(pip)->pips_data[pip.index].dst_idx;
-        wire.location = tile_info(pip)->pips_data[pip.index].dst;
+        wire.index = tile_info(pip)->pip_data[pip.index].dst_idx;
+        wire.location = tile_info(pip)->pip_data[pip.index].dst;
         return wire;
     }
 
@@ -580,7 +567,7 @@ struct Arch : BaseArch<ArchRanges>
         NPNR_ASSERT(wire != WireId());
         range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_downhill.get();
         range.b.wire_loc = wire.location;
-        range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_downhill;
+        range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_downhill.size();
         range.e.wire_loc = wire.location;
         return range;
     }
@@ -591,20 +578,20 @@ struct Arch : BaseArch<ArchRanges>
         NPNR_ASSERT(wire != WireId());
         range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_uphill.get();
         range.b.wire_loc = wire.location;
-        range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_uphill;
+        range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_uphill.size();
         range.e.wire_loc = wire.location;
         return range;
     }
 
     // Extra Pip helpers.
-    int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pips_data[pip.index].pip_type; }
+    int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
 
     std::string get_pip_tilename(PipId pip) const
     {
         auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
-        for (int i = 0; i < tileloc.num_tiles; i++) {
-            if (tileloc.tile_names[i].type_idx == tile_info(pip)->pips_data[pip.index].tile_type)
-                return tileloc.tile_names[i].name.get();
+        for (auto &tn : tileloc.tile_names) {
+            if (tn.type_idx == tile_info(pip)->pip_data[pip.index].tile_type)
+                return tn.name.get();
         }
         NPNR_ASSERT_FALSE("failed to find Pip tile");
     }
@@ -646,24 +633,24 @@ struct Arch : BaseArch<ArchRanges>
     // Internal usage
     bool cells_compatible(const CellInfo **cells, int count) const;
 
-    std::vector<std::pair<std::string, std::string>> get_tiles_at_location(int row, int col);
-    std::string get_tile_by_type_and_loc(int row, int col, std::string type) const
+    std::vector<std::pair<std::string, std::string>> get_tiles_at_loc(int row, int col);
+    std::string get_tile_by_type_loc(int row, int col, std::string type) const
     {
         auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
-        for (int i = 0; i < tileloc.num_tiles; i++) {
-            if (chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get() == type)
-                return tileloc.tile_names[i].name.get();
+        for (auto &tn : tileloc.tile_names) {
+            if (chip_info->tiletype_names[tn.type_idx].get() == type)
+                return tn.name.get();
         }
         NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " +
                               type);
     }
 
-    std::string get_tile_by_type_and_loc(int row, int col, const std::set<std::string> &type) const
+    std::string get_tile_by_type_loc(int row, int col, const std::set<std::string> &type) const
     {
         auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
-        for (int i = 0; i < tileloc.num_tiles; i++) {
-            if (type.count(chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()))
-                return tileloc.tile_names[i].name.get();
+        for (auto &tn : tileloc.tile_names) {
+            if (type.count(chip_info->tiletype_names[tn.type_idx].get()))
+                return tn.name.get();
         }
         NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set");
     }
@@ -672,9 +659,9 @@ struct Arch : BaseArch<ArchRanges>
     {
         for (int i = 0; i < chip_info->height * chip_info->width; i++) {
             auto &tileloc = chip_info->tile_info[i];
-            for (int j = 0; j < tileloc.num_tiles; j++)
-                if (chip_info->tiletype_names[tileloc.tile_names[j].type_idx].get() == type)
-                    return tileloc.tile_names[j].name.get();
+            for (auto &tn : tileloc.tile_names)
+                if (chip_info->tiletype_names[tn.type_idx].get() == type)
+                    return tn.name.get();
         }
         NPNR_ASSERT_FALSE_STR("no tile with type " + type);
     }
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 232598f3a8..8cfc408d5b 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -132,7 +132,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
 static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
 {
     std::string tile = ctx->get_pip_tilename(pip);
-    std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pips_data[pip.index].tile_type].get();
+    std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
     std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
     std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
     cc.tiles[tile].add_arc(sink, source);
@@ -179,13 +179,13 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
 
     std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
     if (bel.location.y == 0) {
-        return ctx->get_tile_by_type_and_loc(0, bel.location.x, "PIC_T0");
+        return ctx->get_tile_by_type_loc(0, bel.location.x, "PIC_T0");
     } else if (bel.location.y == ctx->chip_info->height - 1) {
-        return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PIC_B0");
+        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PIC_B0");
     } else if (bel.location.x == 0) {
-        return ctx->get_tile_by_type_and_loc(bel.location.y, 0, pio_l);
+        return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
     } else if (bel.location.x == ctx->chip_info->width - 1) {
-        return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, pio_r);
+        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r);
     } else {
         NPNR_ASSERT_FALSE("bad PIO location");
     }
@@ -226,7 +226,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
         }
         BelId bel = ci->bel;
         if (ci->type == id_FACADE_SLICE) {
-            std::string tname = ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PLC");
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
             std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get();
 
             NPNR_ASSERT(slice.substr(0, 5) == "SLICE");
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index b83f547d31..327d3418c1 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -308,12 +308,9 @@ def get_wire_name(loc, idx):
                     bba.u16(gfx_wire_ids["TILE_WIRE_" + rg.to_str(wire.name)], "tile_wire")
                 else:
                     bba.u16(0, "tile_wire")
-                bba.u32(len(wire.arcsUphill), "num_uphill")
-                bba.u32(len(wire.arcsDownhill), "num_downhill")
-                bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
-                bba.r("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
-                bba.u32(len(wire.belPins), "num_bel_pins")
-                bba.r("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
+                bba.r_slice("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, len(wire.arcsUphill), "pips_uphill")
+                bba.r_slice("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, len(wire.arcsDownhill), "pips_downhill")
+                bba.r_slice("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, len(wire.belPins), "bel_pins")
 
         if len(t.bels) > 0:
             for bel_idx in range(len(t.bels)):
@@ -323,15 +320,14 @@ def get_wire_name(loc, idx):
                     write_loc(pin.wire.rel, "rel_wire_loc")
                     bba.u32(pin.wire.id, "wire_index")
                     bba.u32(constids[rg.to_str(pin.pin)], "port")
-                    bba.u32(int(pin.dir), "dir")
+                    bba.u32(int(pin.dir), "type")
             bba.l("loc%d_%d_bels" % (l.y, l.x), "BelInfoPOD")
             for bel_idx in range(len(t.bels)):
                 bel = t.bels[bel_idx]
                 bba.s(rg.to_str(bel.name), "name")
                 bba.u32(constids[rg.to_str(bel.type)], "type")
                 bba.u32(bel.z, "z")
-                bba.u32(len(bel.wires), "num_bel_wires")
-                bba.r("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), "bel_wires")
+                bba.r_slice("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), len(bel.wires), "bel_wires")
 
     bba.l("tiles", "TileTypePOD")
     for l in loc_iter:
@@ -340,12 +336,9 @@ def get_wire_name(loc, idx):
         if (l.y, l.x) == (-2, -2):
             continue
 
-        bba.u32(len(t.bels), "num_bels")
-        bba.u32(len(t.wires), "num_wires")
-        bba.u32(len(t.arcs), "num_pips")
-        bba.r("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, "bel_data")
-        bba.r("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, "wire_data")
-        bba.r("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, "pips_data")
+        bba.r_slice("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, len(t.bels), "bel_data")
+        bba.r_slice("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, len(t.wires), "wire_data")
+        bba.r_slice("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, len(t.arcs), "pips_data")
 
     for y in range(0, max_row+1):
         for x in range(0, max_col+1):
@@ -358,8 +351,7 @@ def get_wire_name(loc, idx):
     bba.l("tiles_info", "TileInfoPOD")
     for y in range(0, max_row+1):
         for x in range(0, max_col+1):
-            bba.u32(len(chip.get_tiles_by_position(y, x)), "num_tiles")
-            bba.r("tile_info_%d_%d" % (x, y), "tile_names")
+            bba.r_slice("tile_info_%d_%d" % (x, y), len(chip.get_tiles_by_position(y, x)), "tile_names")
 
     for package, pkgdata in sorted(packages.items()):
         bba.l("package_data_%s" % package, "PackagePinPOD")
@@ -372,8 +364,7 @@ def get_wire_name(loc, idx):
     bba.l("package_data", "PackageInfoPOD")
     for package, pkgdata in sorted(packages.items()):
         bba.s(package, "name")
-        bba.u32(len(pkgdata), "num_pins")
-        bba.r("package_data_%s" % package, "pin_data")
+        bba.r_slice("package_data_%s" % package, len(pkgdata), "pin_data")
 
     bba.l("pio_info", "PIOInfoPOD")
     for pin in pindata:
@@ -417,18 +408,17 @@ def get_wire_name(loc, idx):
     bba.u32(max_col + 1, "width")
     bba.u32(max_row + 1, "height")
     bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
-    bba.u32(len(packages), "num_packages")
-    bba.u32(len(pindata), "num_pios")
     bba.u32(const_id_count, "const_id_count")
 
-    bba.r("tiles", "tiles")
-    bba.r("tiletype_names", "tiletype_names")
-    bba.r("package_data", "package_info")
-    bba.r("pio_info", "pio_info")
-    bba.r("tiles_info", "tile_info")
+    bba.r_slice("tiles", (max_col + 1) * (max_row + 1), "tiles")
+    bba.r_slice("tiletype_names", len(tiletype_names), "tiletype_names")
+    bba.r_slice("package_data", len(packages), "package_info")
+    bba.r_slice("pio_info", len(pindata), "pio_info")
+    bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info")
     bba.r_slice("variant_data", len(variants), "variant_info")
 
     bba.pop()
+    return bba
 
 
 dev_family = {

From 0ce72e1a3103d52d036f822b98e511d9c4f1e71b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 17 Mar 2023 19:00:05 +0100
Subject: [PATCH 307/712] Use TRELLIS primitives

---
 machxo2/arch.cc          |  2 +-
 machxo2/bitstream.cc     |  4 ++--
 machxo2/cells.cc         |  6 +++---
 machxo2/cells.h          |  6 +++---
 machxo2/constids.inc     |  7 +++----
 machxo2/facade_import.py |  6 +++---
 machxo2/gfx.cc           |  6 +++---
 machxo2/pack.cc          | 42 ++++++++++++++++++++--------------------
 8 files changed, 39 insertions(+), 40 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 639f6c6b6c..f2c87888ec 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -368,7 +368,7 @@ bool Arch::place()
         return retVal;
     } else if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
-        cfg.ioBufTypes.insert(id_FACADE_IO);
+        cfg.ioBufTypes.insert(id_TRELLIS_IO);
         bool retVal = placer_heap(getCtx(), cfg);
         getCtx()->settings[id_place] = 1;
         archInfoToAttributes();
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 8cfc408d5b..6ae4ffacec 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -225,7 +225,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
             continue;
         }
         BelId bel = ci->bel;
-        if (ci->type == id_FACADE_SLICE) {
+        if (ci->type == id_TRELLIS_SLICE) {
             std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
             std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get();
 
@@ -253,7 +253,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
             cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
             cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
             cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
-        } else if (ci->type == id_FACADE_IO) {
+        } else if (ci->type == id_TRELLIS_IO) {
             std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
             std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
             std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index c546489201..5f277d17a4 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -32,7 +32,7 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
             name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
     auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
 
-    if (type == id_FACADE_SLICE) {
+    if (type == id_TRELLIS_SLICE) {
         new_cell->params[id_MODE] = std::string("LOGIC");
         new_cell->params[id_GSR] = std::string("ENABLED");
         new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
@@ -101,11 +101,11 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_WADO1);
         new_cell->addOutput(id_WADO2);
         new_cell->addOutput(id_WADO3);
-    } else if (type == id_FACADE_IO) {
+    } else if (type == id_TRELLIS_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
         new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
 
-        new_cell->addInout(id_PAD);
+        new_cell->addInout(id_B);
         new_cell->addInput(id_I);
         new_cell->addInput(id_EN);
         new_cell->addOutput(id_O);
diff --git a/machxo2/cells.h b/machxo2/cells.h
index 7a9bab9267..753d7f119c 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -26,7 +26,7 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 // When packing DFFs, we need context of how it's connected to a LUT to
-// properly map DFF ports to FACADE_SLICEs; DI0 input muxes F0 and OFX0,
+// properly map DFF ports to TRELLIS_SLICEs; DI0 input muxes F0 and OFX0,
 // and a DFF inside a slice can use either DI0 or M0 as an input.
 enum class LutType
 {
@@ -43,9 +43,9 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
 inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
 
 // Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_FF; }
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_SLICE; }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
 
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 40d96fb838..d527c28f3d 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -1,4 +1,4 @@
-X(FACADE_SLICE)
+X(TRELLIS_SLICE)
 X(A0)
 X(B0)
 X(C0)
@@ -60,15 +60,14 @@ X(CCU2_INJECT1_1)
 X(WREMUX)
 
 
-X(FACADE_FF)
+X(TRELLIS_FF)
 X(DI)
 X(Q)
 
 X(REGSET)
 
 
-X(FACADE_IO)
-X(PAD)
+X(TRELLIS_IO)
 X(I)
 X(EN)
 X(O)
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 327d3418c1..93e07775b4 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -469,11 +469,11 @@ def main():
             constids[line[1]] = idx
             const_id_count += 1
 
-    constids["SLICE"] = constids["FACADE_SLICE"]
-    constids["PIO"] = constids["FACADE_IO"]
+    constids["SLICE"] = constids["TRELLIS_SLICE"]
+    constids["PIO"] = constids["TRELLIS_IO"]
 
     chip = pytrellis.Chip(dev_names[args.device])
-    rg = pytrellis.make_optimized_chipdb(chip)
+    rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=False)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_pio_db(rg, args.device)
diff --git a/machxo2/gfx.cc b/machxo2/gfx.cc
index 08b2e01d1b..19da68e17a 100644
--- a/machxo2/gfx.cc
+++ b/machxo2/gfx.cc
@@ -43,19 +43,19 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
     GraphicElement el;
     el.type = GraphicElement::TYPE_BOX;
     el.style = style;
-    if (bel_type == id_FACADE_SLICE) {
+    if (bel_type == id_TRELLIS_SLICE) {
         el.x1 = x + slice_x1;
         el.x2 = x + slice_x2_comb;
         el.y1 = y + slice_y1 + z * slice_pitch;
         el.y2 = y + slice_y2 + z * slice_pitch;
         g.push_back(el);
-        /*    } else if (bel_type == id_FACADE_FF) {
+        /*    } else if (bel_type == id_TRELLIS_FF) {
                 el.x1 = x + slice_x1_ff;
                 el.x2 = x + slice_x2;
                 el.y1 = y + slice_y1 + z * slice_pitch;
                 el.y2 = y + slice_y2 + z * slice_pitch;
                 g.push_back(el);*/
-    } else if (bel_type.in(id_FACADE_IO)) {
+    } else if (bel_type.in(id_TRELLIS_IO)) {
         bool top_bottom = (y == 0 || y == (h - 1));
         if (top_bottom) {
             el.x1 = x + io_cell_h_x1 + (z + 2) * io_cell_gap;
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index a9ca00f28d..5f895cf98e 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -39,7 +39,7 @@ static void pack_lut_lutffs(Context *ctx)
         if (ctx->verbose)
             log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
         if (is_lut(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_FACADE_SLICE, ci->name.str(ctx) + "_LC");
+            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_LC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
 
@@ -100,7 +100,7 @@ static void pack_remaining_ffs(Context *ctx)
             if (ctx->verbose)
                 log_info("cell '%s' of type '%s remains unpacked'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
 
-            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_FACADE_SLICE, ci->name.str(ctx) + "_LC");
+            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_LC");
             for (auto &attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
 
@@ -141,10 +141,10 @@ static void set_net_constant(Context *ctx, NetInfo *orig, NetInfo *constnet, boo
             if (ctx->verbose)
                 log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
 
-            if (uc->type == id_FACADE_FF && user.port == id_DI) {
-                log_info("FACADE_FF %s is driven by a constant\n", uc->name.c_str(ctx));
+            if (uc->type == id_TRELLIS_FF && user.port == id_DI) {
+                log_info("TRELLIS_FF %s is driven by a constant\n", uc->name.c_str(ctx));
 
-                std::unique_ptr<CellInfo> lc = create_machxo2_cell(ctx, id_FACADE_SLICE, uc->name.str(ctx) + "_CONST");
+                std::unique_ptr<CellInfo> lc = create_machxo2_cell(ctx, id_TRELLIS_SLICE, uc->name.str(ctx) + "_CONST");
                 for (auto &attr : uc->attrs)
                     lc->attrs[attr.first] = attr.second;
 
@@ -179,7 +179,7 @@ static void pack_constants(Context *ctx)
 {
     log_info("Packing constants..\n");
 
-    std::unique_ptr<CellInfo> const_cell = create_machxo2_cell(ctx, id_FACADE_SLICE, "$PACKER_CONST");
+    std::unique_ptr<CellInfo> const_cell = create_machxo2_cell(ctx, id_TRELLIS_SLICE, "$PACKER_CONST");
     const_cell->params[id_LUT0_INITVAL] = Property(0, 16);
     const_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
 
@@ -224,9 +224,9 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
            cell->type == ctx->id("$nextpnr_iobuf");
 }
 
-static bool is_facade_iob(const Context *ctx, const CellInfo *cell) { return cell->type == id_FACADE_IO; }
+static bool is_trellis_iob(const Context *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
-static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, NetInfo *&top)
+static bool nextpnr_iob_connects_only_trellis_iob(Context *ctx, CellInfo *iob, NetInfo *&top)
 {
     NPNR_ASSERT(is_nextpnr_iob(ctx, iob));
 
@@ -234,18 +234,18 @@ static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, Ne
         NetInfo *o = iob->ports.at(id_O).net;
         top = o;
 
-        CellInfo *fio = net_only_drives(ctx, o, is_facade_iob, id_PAD, true);
+        CellInfo *fio = net_only_drives(ctx, o, is_trellis_iob, id_B, true);
         return fio != nullptr;
     } else if (iob->type == ctx->id("$nextpnr_obuf")) {
         NetInfo *i = iob->ports.at(id_I).net;
         top = i;
 
-        // If connected to a FACADE_IO PAD, the net attached to an I port of an
+        // If connected to a TRELLIS_IO PAD, the net attached to an I port of an
         // $nextpnr_obuf will not have a driver, only users; an inout port
         // like PAD cannot be a driver in nextpnr. So net_driven_by won't
         // return anything. We exclude the IOB as one of the two users because
         // we already know that the net drives the $nextpnr_obuf.
-        CellInfo *fio = net_only_drives(ctx, i, is_facade_iob, id_PAD, true, iob);
+        CellInfo *fio = net_only_drives(ctx, i, is_trellis_iob, id_B, true, iob);
         return fio != nullptr;
     } else if (iob->type == ctx->id("$nextpnr_iobuf")) {
         NetInfo *o = iob->ports.at(id_O).net;
@@ -254,10 +254,10 @@ static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, Ne
         // When split_io is enabled in a frontend (it is for JSON), the I and O
         // ports of a $nextpnr_iobuf are split; the I port connects to the
         // driver of the original net before IOB insertion, and the O port
-        // connects everything else. Because FACADE_IO PADs cannot be a driver
+        // connects everything else. Because TRELLIS_IO PADs cannot be a driver
         // in nextpnr, the we can safely ignore the I port of an $nextpnr_iobuf
         // for any JSON input we're interested in accepting.
-        CellInfo *fio_o = net_only_drives(ctx, o, is_facade_iob, id_PAD, true);
+        CellInfo *fio_o = net_only_drives(ctx, o, is_trellis_iob, id_B, true);
         return fio_o != nullptr;
     }
 
@@ -266,7 +266,7 @@ static bool nextpnr_iob_connects_only_facade_iob(Context *ctx, CellInfo *iob, Ne
 }
 
 // Pack IO buffers- Right now, all this does is remove $nextpnr_[io]buf cells.
-// User is expected to manually instantiate FACADE_IO with BEL/IO_TYPE
+// User is expected to manually instantiate TRELLIS_IO with BEL/IO_TYPE
 // attributes.
 static void pack_io(Context *ctx)
 {
@@ -279,8 +279,8 @@ static void pack_io(Context *ctx)
         if (is_nextpnr_iob(ctx, ci)) {
             NetInfo *top;
 
-            if (!nextpnr_iob_connects_only_facade_iob(ctx, ci, top))
-                log_error("Top level net '%s' is not connected to a FACADE_IO PAD port.\n", top->name.c_str(ctx));
+            if (!nextpnr_iob_connects_only_trellis_iob(ctx, ci, top))
+                log_error("Top level net '%s' is not connected to a TRELLIS_IO PAD port.\n", top->name.c_str(ctx));
 
             if (ctx->verbose)
                 log_info("Removing top-level IOBUF '%s' of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
@@ -288,11 +288,11 @@ static void pack_io(Context *ctx)
             for (auto &p : ci->ports)
                 ci->disconnectPort(p.first);
             packed_cells.insert(ci->name);
-        } else if (is_facade_iob(ctx, ci)) {
-            // If FACADE_IO has LOC attribute, convert the LOC (pin) to a BEL
-            // attribute and place FACADE_IO at resulting BEL location. A BEL
-            // attribute already on a FACADE_IO is an error. Attributes on
-            // the pin attached to the PAD of FACADE_IO are ignored by this
+        } else if (is_trellis_iob(ctx, ci)) {
+            // If TRELLIS_IO has LOC attribute, convert the LOC (pin) to a BEL
+            // attribute and place TRELLIS_IO at resulting BEL location. A BEL
+            // attribute already on a TRELLIS_IO is an error. Attributes on
+            // the pin attached to the PAD of TRELLIS_IO are ignored by this
             // packing phase.
             auto loc_attr_cell = ci->attrs.find(id_LOC);
             auto bel_attr_cell = ci->attrs.find(id_BEL);

From 3f4c8d15d9038d86d2840e3e5ae4fa2cf0128a6a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Mar 2023 13:53:27 +0100
Subject: [PATCH 308/712] Use unified io location data

---
 machxo2/facade_import.py | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 93e07775b4..fdb0f72318 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -181,14 +181,7 @@ def process_pio_db(rg, device):
             for name, pinloc in sorted(pkgdata.items()):
                 x = pinloc["col"]
                 y = pinloc["row"]
-                if x == 0 or x == max_col:
-                    # FIXME: Oversight in read_pinout.py. We use 0-based
-                    # columns for 0 and max row, but we otherwise extract
-                    # the names from the CSV, and...
-                    loc = pytrellis.Location(x, y)
-                else:
-                    # Lattice uses 1-based columns!
-                    loc = pytrellis.Location(x - 1, y)
+                loc = pytrellis.Location(x, y)
                 pio = "PIO" + pinloc["pio"]
                 bel_idx = get_bel_index(rg, loc, pio)
                 if bel_idx is not None:
@@ -197,10 +190,7 @@ def process_pio_db(rg, device):
         for metaitem in piodb["pio_metadata"]:
             x = metaitem["col"]
             y = metaitem["row"]
-            if x == 0 or x == max_col:
-                loc = pytrellis.Location(x, y)
-            else:
-                loc = pytrellis.Location(x - 1, y)
+            loc = pytrellis.Location(x, y)
             pio = "PIO" + metaitem["pio"]
             bank = metaitem["bank"]
             if "function" in metaitem:

From 35eeaa7cc505b5e7689875dab30b01f05bfc5b4c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 20 Mar 2023 09:13:20 +0100
Subject: [PATCH 309/712] Add ramaining PIO tiles

---
 machxo2/bitstream.cc | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 6ae4ffacec..e6b1bb1704 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -174,14 +174,21 @@ std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString
 // Get the PIC tile corresponding to a PIO bel
 static std::string get_pic_tile(Context *ctx, BelId bel)
 {
-    static const std::set<std::string> pio_l = {"PIC_L0", "PIC_LS0", "PIC_L0_VREF3"};
-    static const std::set<std::string> pio_r = {"PIC_R0", "PIC_RS0"};
+    static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
+    static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
+    static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
+                                                "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
+                                                "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
+                                                "PIC_L2_VREF4", "PIC_L2_VREF5",
+                                                "PIC_L3_VREF4", "PIC_L3_VREF5"};
+    static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
+                                                "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
 
     std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
     if (bel.location.y == 0) {
-        return ctx->get_tile_by_type_loc(0, bel.location.x, "PIC_T0");
+        return ctx->get_tile_by_type_loc(0, bel.location.x, pio_t);
     } else if (bel.location.y == ctx->chip_info->height - 1) {
-        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PIC_B0");
+        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_b);
     } else if (bel.location.x == 0) {
         return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
     } else if (bel.location.x == ctx->chip_info->width - 1) {

From d7e450b7b61ccb35515956c4d68f708a39552e49 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 20 Mar 2023 09:30:05 +0100
Subject: [PATCH 310/712] Update prjtrellis

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 9cb65f122b..0b015575fc 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: 6280c4d1e73b50935b61b24dbaaf2a6a355be001
+      TRELLIS_REVISION: e894ae9e459788cdd7be4056df766e7da000be64
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1

From b3c33bd0ab3cd123aa73e9cb46dea41baadf6dd5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 20 Mar 2023 09:10:02 +0100
Subject: [PATCH 311/712] ice40: Fix BRAM NegClk bitstream logic

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/bitstream.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 72343d75a1..533f310a23 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -636,12 +636,12 @@ void write_asc(const Context *ctx, std::ostream &out)
             bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W);
             int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE);
             int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE);
-            if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
-                set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r);
-                set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w);
-            } else {
+            if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
                 set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
                 set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
+            } else {
+                set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r);
+                set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w);
             }
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1);
             set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);

From 95ace0fade44633db7ea6d3d65702dc8a2d1d488 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 22 Mar 2023 17:15:17 +1000
Subject: [PATCH 312/712] gowin: Add support for OSER primitives

* placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
  GW1NR-9, GW1NR-9C chips;
* the initial support for special HCLK clock wires is implemented to the
  extent necessary for OSER primitives to function;
* output to both regular IO and TLVDS_OBUF is supported;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
  chips are taken into account;
* various edits, such as using idf() instead of the local buffer.

Compatible with old apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 159 +++++++++++++++++++++++++++++++++++++++------
 gowin/arch.h       |  29 ++++++---
 gowin/cells.cc     |   4 ++
 gowin/cells.h      |   2 +-
 gowin/constids.inc |  25 +++++++
 gowin/pack.cc      | 159 ++++++++++++++++++++++++++++++++++++++++++---
 6 files changed, 338 insertions(+), 40 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 042e7a62c3..53bf890ff0 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -384,9 +384,6 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi
     pi.delay = delay;
     pi.loc = loc;
 
-    // log_info("addpip %s->%s %.6f | %s name:%s\n" , srcWire.c_str(this), dstWire.c_str(this),
-    // getDelayNS(delay.maxDelay()), srcWire.c_str(this), name.c_str(this));
-
     wire_info(srcWire).downhill.push_back(name);
     wire_info(dstWire).uphill.push_back(name);
     pip_ids.push_back(name);
@@ -597,19 +594,33 @@ void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock,
 
 // ---------------------------------------------------------------
 
+IdString Arch::apply_local_aliases(int row, int col, const DatabasePOD *db, IdString &wire)
+{
+    const TilePOD *tile = db->grid[row * db->cols + col].get();
+    auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, wire.index);
+    IdString res_wire = IdString();
+    if (local_alias != nullptr) {
+        wire = IdString(local_alias->src_id);
+        res_wire = idf("R%dC%d_%s", row + 1, col + 1, wire.c_str(this));
+    }
+    return res_wire;
+}
+
 // TODO represent wires more intelligently.
 IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString &wire)
 {
     const std::string &wirename = wire.str(this);
-    char buf[32];
     if (wirename == "VCC" || wirename == "VSS") {
         row = 0;
         col = 0;
         return wire;
     }
     if (!isdigit(wirename[1]) || !isdigit(wirename[2]) || !isdigit(wirename[3])) {
-        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, wirename.c_str());
-        return id(buf);
+        IdString res_wire = apply_local_aliases(row, col, db, wire);
+        if (res_wire == IdString()) {
+            return idf("R%dC%d_%s", row + 1, col + 1, wirename.c_str());
+        }
+        return res_wire;
     }
     char direction = wirename[0];
     int num = std::stoi(wirename.substr(1, 2));
@@ -628,8 +639,7 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
         col += segment;
         break;
     default:
-        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, wirename.c_str());
-        return id(buf);
+        return idf("R%dC%d_%s", row + 1, col + 1, wirename.c_str());
         break;
     }
     // wires wrap around the edges
@@ -647,18 +657,13 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
         col = 2 * db->cols - 1 - col;
         direction = 'E';
     }
-    snprintf(buf, 32, "%c%d0", direction, num);
-    wire = id(buf);
+    wire = idf("%c%d0", direction, num);
     // local aliases
-    const TilePOD *tile = db->grid[row * db->cols + col].get();
-    auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, wire.index);
-    if (local_alias != nullptr) {
-        wire = IdString(local_alias->src_id);
-        snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, wire.c_str(this));
-    } else {
-        snprintf(buf, 32, "R%dC%d_%c%d", row + 1, col + 1, direction, num);
+    IdString res_wire = apply_local_aliases(row, col, db, wire);
+    if (res_wire == IdString()) {
+        res_wire = idf("R%dC%d_%c%d", row + 1, col + 1, direction, num);
     }
-    return id(buf);
+    return res_wire;
 }
 
 const PairPOD *pairLookup(const PairPOD *list, const size_t len, const int dest)
@@ -1581,6 +1586,10 @@ Arch::Arch(ArchArgs args) : args(args)
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                     addBelInput(belname, id_XXX_VSS1, id(buf));
                 }
+                if (!z && device_id == id("GW1NR-9C")) {
+                    addBelInput(belname, id_XXX_0, idf("R%dC%d_C6", row + 1, col + 1));
+                    addBelInput(belname, id_XXX_1, idf("R%dC%d_D6", row + 1, col + 1));
+                }
             } break;
                 // Simplified IO
             case ID_IOBJS:
@@ -1627,7 +1636,7 @@ Arch::Arch(ArchArgs args) : args(args)
             case ID_ODDRA: {
                 snprintf(buf, 32, "R%dC%d_ODDR%s%c", row + 1, col + 1, oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
                 belname = id(buf);
-                addBel(belname, id_ODDR, Loc(col, row, BelZ::iologic_0_z + z), false);
+                addBel(belname, id_ODDR, Loc(col, row, BelZ::oddr_0_z + z), false);
 
                 portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_D0)->src_id);
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
@@ -1681,6 +1690,64 @@ Arch::Arch(ArchArgs args) : args(args)
                     addWire(q1_name, id_q1, row, col);
                 addBelOutput(belname, id_Q1, q1_name);
             } break;
+            case ID_IOLOGICB:
+                z++; /* fall-through*/
+            case ID_IOLOGICA: {
+                belname = idf("R%dC%d_IOLOGIC%c", row + 1, col + 1, 'A' + z);
+                addBel(belname, id_IOLOGIC, Loc(col, row, BelZ::iologic_z + z), false);
+
+                for (int i = 0; i < 10; ++i) {
+                    if (i < 4) {
+                        // TX
+                        IdString const tx[] = {id_TX0, id_TX1, id_TX2, id_TX3};
+                        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, tx[i].hash())->src_id);
+                        addBelInput(belname, tx[i], idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    }
+                    // D
+                    IdString const d[] = {id_D0, id_D1, id_D2, id_D3, id_D4, id_D5, id_D6, id_D7, id_D8, id_D9};
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, d[i].hash())->src_id);
+                    addBelInput(belname, d[i], idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                }
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_PCLK)->src_id);
+                addBelInput(belname, id_PCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                auto fclk = pairLookup(bel->ports.get(), bel->num_ports, ID_FCLK);
+                // XXX as long as there is no special processing of the pins
+                if (fclk != nullptr) {
+                    portname = IdString(fclk->src_id);
+                    IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    if (wires.count(wire) == 0) {
+                        GlobalAliasPOD alias;
+                        alias.dest_col = col;
+                        alias.dest_row = row;
+                        alias.dest_id = portname.hash();
+                        auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+                        if (alias_src != nullptr) {
+                            int srcrow = alias_src->src_row;
+                            int srccol = alias_src->src_col;
+                            IdString srcid = IdString(alias_src->src_id);
+                            wire = wireToGlobal(srcrow, srccol, db, srcid);
+                            if (wires.count(wire) == 0) {
+                                addWire(wire, srcid, srccol, srcrow);
+                            }
+                            addBelInput(belname, id_FCLK, wire);
+                        }
+                        // XXX here we are creating an
+                        // IOLOGIC with a missing FCLK input. This is so
+                        // because bels with the same type can be placed in
+                        // on the chip where there is no pin, so no
+                        // IOLOGIC makes sense. But since each type is
+                        // described only once in the database we can't really
+                        // mark these special bel somehow.
+                        // By creating an IOLOGIC without an FCLK input we
+                        // create a routing error later, so that "bad"
+                        // locations are handled.
+                    } else {
+                        addBelInput(belname, id_FCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    }
+                }
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET)->src_id);
+                addBelInput(belname, id_RESET, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+            } break;
             default:
                 break;
             }
@@ -2245,6 +2312,54 @@ void Arch::fix_pll_nets(Context *ctx)
     }
 }
 
+// mark with hclk is used
+void Arch::mark_used_hclk(Context *ctx)
+{
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_IOLOGIC) {
+            continue;
+        }
+        if (ci->attrs.count(id_IOLOGIC_FCLK)) {
+            continue;
+        }
+        // if it's an aux cell
+        if (ci->attrs.count(id_IOLOGIC_MASTER_CELL)) {
+            continue;
+        }
+        ci->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
+
+        // *** FCLK
+        if (port_used(ci, id_FCLK)) {
+            NetInfo const *net = ci->getPort(id_FCLK);
+            for (auto const &user : net->users) {
+                if (user.cell != ci) {
+                    continue;
+                }
+                if (user.port != id_FCLK) {
+                    continue;
+                }
+                WireId dstWire = ctx->getNetinfoSinkWire(net, user, 0);
+                if (ctx->verbose) {
+                    log_info("   Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(this), user.port.c_str(this),
+                             dstWire.c_str(this));
+                }
+                for (PipId const &pip : getPipsUphill(dstWire)) {
+                    if (!checkPipAvail(pip)) {
+                        WireId src_wire = getPipSrcWire(pip);
+                        ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));
+                        if (ci->attrs.count(id_IOLOGIC_AUX_CELL)) {
+                            IdString aux_cell_name = ctx->id(ci->attrs[id_IOLOGIC_AUX_CELL].as_string());
+                            ctx->cells[aux_cell_name]->setAttr(id_IOLOGIC_FCLK,
+                                                               Property(wire_info(src_wire).type.str(this)));
+                        }
+                    }
+                }
+            }
+        }
+    }
+}
+
 void Arch::pre_route(Context *ctx)
 {
     fix_pll_nets(ctx);
@@ -2253,7 +2368,11 @@ void Arch::pre_route(Context *ctx)
     }
 }
 
-void Arch::post_route(Context *ctx) { fix_longwire_bels(); }
+void Arch::post_route(Context *ctx)
+{
+    fix_longwire_bels();
+    mark_used_hclk(ctx);
+}
 
 bool Arch::route()
 {
diff --git a/gowin/arch.h b/gowin/arch.h
index 822cdfc167..595c82a06e 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -401,6 +401,11 @@ struct Arch : BaseArch<ArchRanges>
     PortType getBelPinType(BelId bel, IdString pin) const override;
     std::vector<IdString> getBelPins(BelId bel) const override;
     std::array<IdString, 1> getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override;
+    // Placement validity checks
+    virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        return cell_type == id_DUMMY_CELL || cell_type == this->getBelType(bel);
+    }
 
     WireId getWireByName(IdStringList name) const override;
     IdStringList getWireName(WireId wire) const override;
@@ -490,6 +495,9 @@ struct Arch : BaseArch<ArchRanges>
     bool is_GCLKT_iob(const CellInfo *cell);
     void bind_pll_to_bel(CellInfo *ci, PLL loc);
 
+    void mark_used_hclk(Context *ctx);
+    IdString apply_local_aliases(int row, int col, const DatabasePOD *db, IdString &wire);
+
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
     void route_gowin_globals(Context *ctx);
@@ -524,16 +532,17 @@ struct Arch : BaseArch<ArchRanges>
 namespace BelZ {
 enum
 {
-    mux_0_z = 10,     // start Z for the MUX2LUT5 bels
-    iologic_0_z = 20, // start Z for the IOLOGIC bels
-    lutram_0_z = 30,  // start Z for the IOLOGIC bels
-    vcc_0_z = 277,    // virtual VCC bel Z
-    gnd_0_z = 278,    // virtual VSS bel Z
-    osc_z = 280,      // Z for the oscillator bels
-    bufs_0_z = 281,   // Z for long wire buffer bel
-    pll_z = 289,      // PLL
-    pllvr_z = 290,    // PLLVR
-    free_z = 291      // Must be the last, one can use z starting from this value, adjust accordingly.
+    mux_0_z = 10,    // start Z for the MUX2LUT5 bels
+    oddr_0_z = 20,   // XXX start Z for the ODDR bels
+    lutram_0_z = 30, // start Z for the LUTRAM bels
+    vcc_0_z = 277,   // virtual VCC bel Z
+    gnd_0_z = 278,   // virtual VSS bel Z
+    osc_z = 280,     // Z for the oscillator bels
+    bufs_0_z = 281,  // Z for long wire buffer bel
+    pll_z = 289,     // PLL
+    pllvr_z = 290,   // PLLVR
+    iologic_z = 291, // IOLOGIC
+    free_z = 293     // Must be the last, one can use z starting from this value, adjust accordingly.
 };
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index c30a470630..436b4766b6 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -105,6 +105,10 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_CLKOUTD);
         new_cell->addOutput(id_CLKOUTD3);
         new_cell->addOutput(id_LOCK);
+    } else if (type == id_IOLOGIC) {
+        new_cell->addInput(id_PCLK);
+        new_cell->addInput(id_RESET);
+    } else if (type == id_DUMMY_CELL) {
     } else {
         log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
     }
diff --git a/gowin/cells.h b/gowin/cells.h
index 7aba480531..4cabe086b6 100644
--- a/gowin/cells.h
+++ b/gowin/cells.h
@@ -105,7 +105,7 @@ inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 
 inline bool is_sram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_RAM16SDP4; }
 
-inline bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type.index == ID_IOB); }
+inline bool is_iob(const Context *ctx, const CellInfo *cell) { return (cell->type == id_IOB || cell->type == id_IOBS); }
 
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
diff --git a/gowin/constids.inc b/gowin/constids.inc
index b678cc7747..afe3bc1570 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -667,6 +667,9 @@ X(IOBH)
 X(IOBI)
 X(IOBJ)
 
+// misc
+X(DUMMY_CELL)
+
 // simplified iobs
 X(IOBS)
 X(IOBAS)
@@ -757,10 +760,18 @@ X(LWO7)
 
 // IOLOGIC
 X(TX)
+X(TX0)
+X(TX1)
+X(TX2)
+X(TX3)
+X(FCLK)
+X(PCLK)
 X(XXX_VSS)
 X(XXX_VCC)
 X(XXX_VSS0)
 X(XXX_VSS1)
+X(XXX_0)
+X(XXX_1)
 X(OBUF_TYPE)
 X(SBUF)
 X(DBUF)
@@ -770,6 +781,20 @@ X(ODDRA)
 X(ODDRB)
 X(ODDRCA)
 X(ODDRCB)
+X(OSER4)
+X(OSER8)
+X(OSER10)
+X(OVIDEO)
+X(OSER16)
+X(IOLOGIC)
+X(IOLOGICA)
+X(IOLOGICB)
+X(IOLOGIC_TYPE)
+X(IOLOGIC_FCLK)
+X(IOLOGIC_MASTER_CELL)
+X(IOLOGIC_AUX_CELL)
+X(D8)
+X(D9)
 
 // Wide LUTs
 X(MUX2_LUT5)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index fc8708901b..6e875a8c57 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -812,8 +812,12 @@ static bool is_gowin_diff_iob(const Context *ctx, const CellInfo *cell)
 static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
 {
     switch (cell->type.index) {
-    case ID_ODDR: /* fall-through*/
-    case ID_ODDRC:
+    case ID_ODDR:   /* fall-through*/
+    case ID_ODDRC:  /* fall-through*/
+    case ID_OSER4:  /* fall-through*/
+    case ID_OSER8:  /* fall-through*/
+    case ID_OSER10: /* fall-through*/
+    case ID_OVIDEO:
         return true;
     default:
         return false;
@@ -836,7 +840,7 @@ static void pack_iologic(Context *ctx)
         if (is_gowin_iologic(ctx, ci)) {
             CellInfo *q0_dst = nullptr;
             CellInfo *q1_dst = nullptr;
-            switch (ci->type.index) {
+            switch (ci->type.hash()) {
             case ID_ODDRC: /* fall-through*/
             case ID_ODDR: {
                 q0_dst = net_only_drives(ctx, ci->ports.at(id_Q0).net, is_iob, id_I);
@@ -851,7 +855,7 @@ static void pack_iologic(Context *ctx)
                 if (iob_bel != q0_dst->attrs.end()) {
                     // already know there to place, no need of any cluster stuff
                     Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
-                    loc.z += BelZ::iologic_0_z;
+                    loc.z += BelZ::oddr_0_z;
                     ci->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
                 } else {
                     // make cluster from ODDR and OBUF
@@ -864,7 +868,7 @@ static void pack_iologic(Context *ctx)
                     q0_dst->cluster = ci->name;
                     q0_dst->constr_x = 0;
                     q0_dst->constr_y = 0;
-                    q0_dst->constr_z = -BelZ::iologic_0_z;
+                    q0_dst->constr_z = -BelZ::oddr_0_z;
                     q0_dst->constr_abs_z = false;
                 }
 
@@ -891,13 +895,142 @@ static void pack_iologic(Context *ctx)
                     ci->addInput(id_XXX_VCC);
                     ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 }
-                if (ctx->gw1n9_quirk && iob_bel != q0_dst->attrs.end()) {
-                    bool have_XXX_VSS0 =
-                            ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_VSS0);
-                    if (have_XXX_VSS0) {
+                if (iob_bel != q0_dst->attrs.end()) {
+                    IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
+                    if (ctx->gw1n9_quirk && ctx->bels[io_bel_name].pins.count(id_XXX_VSS0)) {
                         q0_dst->disconnectPort(id_XXX_VSS0);
                         q0_dst->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                     }
+                    if (ctx->bels[io_bel_name].pins.count(id_XXX_1)) {
+                        q0_dst->disconnectPort(id_XXX_1);
+                        q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    }
+                }
+            } break;
+            case ID_OSER4:  /* fall-through */
+            case ID_OSER8:  /* fall-through */
+            case ID_OSER10: /* fall-through */
+            case ID_OVIDEO: {
+                IdString output = id_Q;
+                IdString output_1 = IdString();
+                if (ci->type == id_OSER4 || ci->type == id_OSER8) {
+                    output = id_Q0;
+                    output_1 = id_Q1;
+                }
+                q0_dst = net_only_drives(ctx, ci->ports.at(output).net, is_iob, id_I);
+                NPNR_ASSERT(q0_dst != nullptr);
+
+                auto iob_bel = q0_dst->attrs.find(id_BEL);
+                if (iob_bel == q0_dst->attrs.end()) {
+                    log_info("No constraints for %s\n", ctx->nameOf(q0_dst));
+                    NPNR_ASSERT_FALSE("The pins for IDES/OSER must be specified explicitly.");
+                }
+
+                Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
+                loc.z += BelZ::iologic_z;
+                ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                BelId bel = ctx->getBelByLocation(loc);
+                if (bel == BelId()) {
+                    log_info("No bel for %s at %s\n", ctx->nameOf(ci), iob_bel->second.as_string().c_str());
+                    NPNR_ASSERT_FALSE("Can't place IDES/OSER here");
+                }
+
+                std::string out_mode;
+                switch (ci->type.hash()) {
+                case ID_OSER4:
+                    out_mode = "ODDRX2";
+                    break;
+                case ID_OSER8:
+                    out_mode = "ODDRX4";
+                    break;
+                case ID_OSER10:
+                    out_mode = "ODDRX5";
+                    break;
+                case ID_OVIDEO:
+                    out_mode = "VIDEORX";
+                    break;
+                }
+                ci->setParam(ctx->id("OUTMODE"), out_mode);
+                bool use_diff_io = false;
+                if (q0_dst->attrs.count(id_DIFF_TYPE)) {
+                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    use_diff_io = true;
+                } else {
+                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                }
+
+                // disconnect Q output: it is wired internally
+                delete_nets.insert(ci->ports.at(output).net->name);
+                q0_dst->disconnectPort(id_I);
+                ci->disconnectPort(output);
+                bool have_XXX = ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_1);
+                if (have_XXX) {
+                    q0_dst->disconnectPort(id_XXX_1);
+                    q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                }
+
+                // if Q1 is connected then disconnet it too
+                if (output_1 != IdString() && port_used(ci, output_1)) {
+                    q1_dst = net_only_drives(ctx, ci->ports.at(output_1).net, is_iob, id_OEN);
+                    if (q1_dst != nullptr) {
+                        delete_nets.insert(ci->ports.at(output_1).net->name);
+                        q0_dst->disconnectPort(id_OEN);
+                        ci->disconnectPort(output_1);
+                        ci->setAttr(id_IOBUF, 1);
+                    }
+                } else {
+                    // force OEN = 0 in order to enable output
+                    // XXX check for IOBUF and TBUF
+                    if (ci->type == id_OSER4 || ci->type == id_OSER8) {
+                        int port_num = ci->type == id_OSER4 ? 2 : 4;
+                        for (int i = 0; i < port_num; ++i) {
+                            IdString port = ctx->idf("TX%d", i);
+                            ci->disconnectPort(port);
+                            ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                        }
+                    }
+                }
+
+                ci->setAttr(id_IOBUF, 0);
+                ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
+
+                if (ci->type == id_OSER4) {
+                    ci->type = id_IOLOGIC;
+                    // two OSER4 share FCLK, check it
+                    Loc other_loc = loc;
+                    other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
+                    BelId other_bel = ctx->getBelByLocation(other_loc);
+                    CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
+                    if (other_cell != nullptr) {
+                        NPNR_ASSERT(other_cell->type == id_OSER4);
+                        if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
+                            log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci), ctx->nameOf(other_cell));
+                        }
+                    }
+                } else {
+                    std::unique_ptr<CellInfo> dummy =
+                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_DUMMY_IOLOGIC_IO");
+                    loc.z = 1 - loc.z + BelZ::iologic_z;
+                    if (!use_diff_io) {
+                        dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                        new_cells.push_back(std::move(dummy));
+                    }
+                    loc.z += BelZ::iologic_z;
+
+                    std::unique_ptr<CellInfo> aux_cell =
+                            create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
+                    ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
+                    aux_cell->setParam(ctx->id("OUTMODE"), std::string("DDRENABLE"));
+                    aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
+                    aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    if (port_used(ci, id_RESET)) {
+                        aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                    }
+                    if (port_used(ci, id_PCLK)) {
+                        aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                    }
+                    new_cells.push_back(std::move(aux_cell));
+                    ci->type = id_IOLOGIC;
                 }
             } break;
             default:
@@ -1139,6 +1272,7 @@ static void pack_io(Context *ctx)
             IdString new_cell_type = id_IOB;
             std::string constr_bel_name = std::string("");
             bool have_xxx_port = false;
+            bool have_xxx0_port = false;
             // check whether the given IO is limited to simplified IO cells
             auto constr_bel = ci->attrs.find(id_BEL);
             if (constr_bel != ci->attrs.end()) {
@@ -1157,6 +1291,7 @@ static void pack_io(Context *ctx)
                     if (ctx->gw1n9_quirk) {
                         have_xxx_port = ctx->bels[constr_bel].pins.count(id_XXX_VSS0) != 0;
                     }
+                    have_xxx0_port = ctx->bels[constr_bel].pins.count(id_XXX_0) != 0;
                 }
             }
 
@@ -1172,6 +1307,12 @@ static void pack_io(Context *ctx)
                 gwiob->addInput(id_XXX_VSS1);
                 gwiob->connectPort(id_XXX_VSS1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
             }
+            if (have_xxx0_port && ci->type != id_IBUF) {
+                gwiob->addInput(id_XXX_0);
+                gwiob->connectPort(id_XXX_0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_XXX_1);
+                gwiob->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+            }
 
             packed_cells.insert(ci->name);
             if (iob != nullptr) {

From 38eb1f05ff2baaab8e7d83f4a5747eae7f5cddcb Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 22 Mar 2023 18:08:38 +1000
Subject: [PATCH 313/712] gowin: Change the way errors are processed

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/pack.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index 6e875a8c57..e335241a45 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -922,8 +922,8 @@ static void pack_iologic(Context *ctx)
 
                 auto iob_bel = q0_dst->attrs.find(id_BEL);
                 if (iob_bel == q0_dst->attrs.end()) {
-                    log_info("No constraints for %s\n", ctx->nameOf(q0_dst));
-                    NPNR_ASSERT_FALSE("The pins for IDES/OSER must be specified explicitly.");
+                    log_error("No constraints for %s. The pins for IDES/OSER must be specified explicitly.\n",
+                              ctx->nameOf(q0_dst));
                 }
 
                 Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
@@ -931,8 +931,8 @@ static void pack_iologic(Context *ctx)
                 ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
                 BelId bel = ctx->getBelByLocation(loc);
                 if (bel == BelId()) {
-                    log_info("No bel for %s at %s\n", ctx->nameOf(ci), iob_bel->second.as_string().c_str());
-                    NPNR_ASSERT_FALSE("Can't place IDES/OSER here");
+                    log_info("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
+                             iob_bel->second.as_string().c_str());
                 }
 
                 std::string out_mode;

From c52906e8bca2dd399fd5a37ca50326c2b913d128 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 22 Mar 2023 18:35:45 +1000
Subject: [PATCH 314/712] gowin: Rename questionable ports

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 40 +++++++++++++++++++-------------------
 gowin/constids.inc | 12 ++++++------
 gowin/pack.cc      | 48 +++++++++++++++++++++++-----------------------
 3 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 53bf890ff0..de25233880 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -420,7 +420,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
 {
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
-    BelInfo &bi = bels[name];
+    BelInfo &bi = bels.at(name);
     bi.name = name;
     bi.type = type;
     bi.x = loc.x;
@@ -1572,23 +1572,23 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OEN, id(buf));
                 // GW1NR-9 quirk
-                const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS0);
-                if (xxx_port != nullptr) {
+                const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW0);
+                if (quirk_port != nullptr) {
                     gw1n9_quirk = true;
-                    portname = IdString(xxx_port->src_id);
+                    portname = IdString(quirk_port->src_id);
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_XXX_VSS0, id(buf));
+                    addBelInput(belname, id_GW9_ALWAYS_LOW0, id(buf));
                 }
-                xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS1);
-                if (xxx_port != nullptr) {
+                quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW1);
+                if (quirk_port != nullptr) {
                     gw1n9_quirk = true;
-                    portname = IdString(xxx_port->src_id);
+                    portname = IdString(quirk_port->src_id);
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_XXX_VSS1, id(buf));
+                    addBelInput(belname, id_GW9_ALWAYS_LOW1, id(buf));
                 }
                 if (!z && device_id == id("GW1NR-9C")) {
-                    addBelInput(belname, id_XXX_0, idf("R%dC%d_C6", row + 1, col + 1));
-                    addBelInput(belname, id_XXX_1, idf("R%dC%d_D6", row + 1, col + 1));
+                    addBelInput(belname, id_GW9C_ALWAYS_LOW0, idf("R%dC%d_C6", row + 1, col + 1));
+                    addBelInput(belname, id_GW9C_ALWAYS_LOW1, idf("R%dC%d_D6", row + 1, col + 1));
                 }
             } break;
                 // Simplified IO
@@ -1654,19 +1654,19 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_CLK, id(buf));
 
-                const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS);
-                if (xxx_port != nullptr) {
+                const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_LOW);
+                if (quirk_port != nullptr) {
                     ddr_has_extra_inputs = true;
-                    portname = IdString(xxx_port->src_id);
+                    portname = IdString(quirk_port->src_id);
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_XXX_VSS, id(buf));
+                    addBelInput(belname, id_ODDR_ALWAYS_LOW, id(buf));
                 }
-                xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC);
-                if (xxx_port != nullptr) {
+                quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_HIGH);
+                if (quirk_port != nullptr) {
                     ddr_has_extra_inputs = true;
-                    portname = IdString(xxx_port->src_id);
+                    portname = IdString(quirk_port->src_id);
                     snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_XXX_VCC, id(buf));
+                    addBelInput(belname, id_ODDR_ALWAYS_HIGH, id(buf));
                 }
 
                 if (oddrc) {
@@ -2344,7 +2344,7 @@ void Arch::mark_used_hclk(Context *ctx)
                     log_info("   Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(this), user.port.c_str(this),
                              dstWire.c_str(this));
                 }
-                for (PipId const &pip : getPipsUphill(dstWire)) {
+                for (PipId pip : getPipsUphill(dstWire)) {
                     if (!checkPipAvail(pip)) {
                         WireId src_wire = getPipSrcWire(pip);
                         ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));
diff --git a/gowin/constids.inc b/gowin/constids.inc
index afe3bc1570..e861275f67 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -766,12 +766,12 @@ X(TX2)
 X(TX3)
 X(FCLK)
 X(PCLK)
-X(XXX_VSS)
-X(XXX_VCC)
-X(XXX_VSS0)
-X(XXX_VSS1)
-X(XXX_0)
-X(XXX_1)
+X(ODDR_ALWAYS_LOW)
+X(ODDR_ALWAYS_HIGH)
+X(GW9_ALWAYS_LOW0)
+X(GW9_ALWAYS_LOW1)
+X(GW9C_ALWAYS_LOW0)
+X(GW9C_ALWAYS_LOW1)
 X(OBUF_TYPE)
 X(SBUF)
 X(DBUF)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index e335241a45..aa12325bbb 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -890,20 +890,20 @@ static void pack_iologic(Context *ctx)
                 }
                 // if have XXX_ inputs connect them
                 if (ctx->ddr_has_extra_inputs) {
-                    ci->addInput(id_XXX_VSS);
-                    ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
-                    ci->addInput(id_XXX_VCC);
-                    ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    ci->addInput(id_ODDR_ALWAYS_LOW);
+                    ci->connectPort(id_ODDR_ALWAYS_LOW, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                    ci->addInput(id_ODDR_ALWAYS_HIGH);
+                    ci->connectPort(id_ODDR_ALWAYS_HIGH, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 }
                 if (iob_bel != q0_dst->attrs.end()) {
                     IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
-                    if (ctx->gw1n9_quirk && ctx->bels[io_bel_name].pins.count(id_XXX_VSS0)) {
-                        q0_dst->disconnectPort(id_XXX_VSS0);
-                        q0_dst->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    if (ctx->gw1n9_quirk && ctx->bels.at(io_bel_name).pins.count(id_GW9_ALWAYS_LOW0)) {
+                        q0_dst->disconnectPort(id_GW9_ALWAYS_LOW0);
+                        q0_dst->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                     }
-                    if (ctx->bels[io_bel_name].pins.count(id_XXX_1)) {
-                        q0_dst->disconnectPort(id_XXX_1);
-                        q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    if (ctx->bels.at(io_bel_name).pins.count(id_GW9C_ALWAYS_LOW1)) {
+                        q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
+                        q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                     }
                 }
             } break;
@@ -963,10 +963,10 @@ static void pack_iologic(Context *ctx)
                 delete_nets.insert(ci->ports.at(output).net->name);
                 q0_dst->disconnectPort(id_I);
                 ci->disconnectPort(output);
-                bool have_XXX = ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_1);
+                bool have_XXX = ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
                 if (have_XXX) {
-                    q0_dst->disconnectPort(id_XXX_1);
-                    q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                    q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
+                    q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 }
 
                 // if Q1 is connected then disconnet it too
@@ -1287,11 +1287,11 @@ static void pack_io(Context *ctx)
             if (!constr_bel_name.empty()) {
                 BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
                 if (constr_bel != BelId()) {
-                    new_cell_type = ctx->bels[constr_bel].type;
+                    new_cell_type = ctx->bels.at(constr_bel).type;
                     if (ctx->gw1n9_quirk) {
-                        have_xxx_port = ctx->bels[constr_bel].pins.count(id_XXX_VSS0) != 0;
+                        have_xxx_port = ctx->bels.at(constr_bel).pins.count(id_GW9_ALWAYS_LOW0) != 0;
                     }
-                    have_xxx0_port = ctx->bels[constr_bel].pins.count(id_XXX_0) != 0;
+                    have_xxx0_port = ctx->bels.at(constr_bel).pins.count(id_GW9C_ALWAYS_LOW0) != 0;
                 }
             }
 
@@ -1302,16 +1302,16 @@ static void pack_io(Context *ctx)
             auto gwiob = new_cells.back().get();
             // XXX GW1NR-9 quirks
             if (have_xxx_port && ci->type != id_IBUF) {
-                gwiob->addInput(id_XXX_VSS0);
-                gwiob->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
-                gwiob->addInput(id_XXX_VSS1);
-                gwiob->connectPort(id_XXX_VSS1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_GW9_ALWAYS_LOW0);
+                gwiob->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_GW9_ALWAYS_LOW1);
+                gwiob->connectPort(id_GW9_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
             }
             if (have_xxx0_port && ci->type != id_IBUF) {
-                gwiob->addInput(id_XXX_0);
-                gwiob->connectPort(id_XXX_0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
-                gwiob->addInput(id_XXX_1);
-                gwiob->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_GW9C_ALWAYS_LOW0);
+                gwiob->connectPort(id_GW9C_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                gwiob->addInput(id_GW9C_ALWAYS_LOW1);
+                gwiob->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
             }
 
             packed_cells.insert(ci->name);

From b36e8a3013ac70a9fbe71d2163f660dafe3b8b2f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 22 Mar 2023 18:57:14 +1000
Subject: [PATCH 315/712] gowin: bugfix

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 2 +-
 gowin/pack.cc | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index de25233880..9f091a5dc4 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -420,7 +420,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
 {
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
-    BelInfo &bi = bels.at(name);
+    BelInfo &bi = bels[name];
     bi.name = name;
     bi.type = type;
     bi.x = loc.x;
diff --git a/gowin/pack.cc b/gowin/pack.cc
index aa12325bbb..49d428a82f 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -963,7 +963,8 @@ static void pack_iologic(Context *ctx)
                 delete_nets.insert(ci->ports.at(output).net->name);
                 q0_dst->disconnectPort(id_I);
                 ci->disconnectPort(output);
-                bool have_XXX = ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
+                bool have_XXX =
+                        ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
                 if (have_XXX) {
                     q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
                     q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());

From 20b7f760d925c0c102f5a4d03adeb3f3af4ca6f6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 4 Apr 2023 09:50:48 +1000
Subject: [PATCH 316/712] gowin: Add support for IDES primitives

* placement of IDES4, IVIDEO, IDES8 and IDES10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
  GW1NR-9, GW1NR-9C chips;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
  chips are taken into account;

Compatible with old apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      |  27 ++++-----
 gowin/constids.inc |  10 ++++
 gowin/pack.cc      | 138 ++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 159 insertions(+), 16 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 9f091a5dc4..8292e3227b 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1696,20 +1696,19 @@ Arch::Arch(ArchArgs args) : args(args)
                 belname = idf("R%dC%d_IOLOGIC%c", row + 1, col + 1, 'A' + z);
                 addBel(belname, id_IOLOGIC, Loc(col, row, BelZ::iologic_z + z), false);
 
-                for (int i = 0; i < 10; ++i) {
-                    if (i < 4) {
-                        // TX
-                        IdString const tx[] = {id_TX0, id_TX1, id_TX2, id_TX3};
-                        portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, tx[i].hash())->src_id);
-                        addBelInput(belname, tx[i], idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
-                    }
-                    // D
-                    IdString const d[] = {id_D0, id_D1, id_D2, id_D3, id_D4, id_D5, id_D6, id_D7, id_D8, id_D9};
-                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, d[i].hash())->src_id);
-                    addBelInput(belname, d[i], idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                IdString const iologic_in_ports[] = {id_TX0,  id_TX1, id_TX2, id_TX3, id_RESET, id_CALIB,
+                                                     id_PCLK, id_D,   id_D0,  id_D1,  id_D2,    id_D3,
+                                                     id_D4,   id_D5,  id_D6,  id_D7,  id_D8,    id_D9};
+                for (IdString port : iologic_in_ports) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+                    addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                }
+                IdString const iologic_out_ports[] = {id_Q,  id_Q0, id_Q1, id_Q2, id_Q3, id_Q4,
+                                                      id_Q5, id_Q6, id_Q7, id_Q8, id_Q9};
+                for (IdString port : iologic_out_ports) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+                    addBelOutput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
                 }
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_PCLK)->src_id);
-                addBelInput(belname, id_PCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
                 auto fclk = pairLookup(bel->ports.get(), bel->num_ports, ID_FCLK);
                 // XXX as long as there is no special processing of the pins
                 if (fclk != nullptr) {
@@ -1745,8 +1744,6 @@ Arch::Arch(ArchArgs args) : args(args)
                         addBelInput(belname, id_FCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
                     }
                 }
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_RESET)->src_id);
-                addBelInput(belname, id_RESET, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
             } break;
             default:
                 break;
diff --git a/gowin/constids.inc b/gowin/constids.inc
index e861275f67..5bd2aa4640 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -766,6 +766,9 @@ X(TX2)
 X(TX3)
 X(FCLK)
 X(PCLK)
+X(CALIB)
+X(Q8)
+X(Q9)
 X(ODDR_ALWAYS_LOW)
 X(ODDR_ALWAYS_HIGH)
 X(GW9_ALWAYS_LOW0)
@@ -776,7 +779,9 @@ X(OBUF_TYPE)
 X(SBUF)
 X(DBUF)
 X(ODDR)
+X(IDDR)
 X(ODDRC)
+X(IDDRC)
 X(ODDRA)
 X(ODDRB)
 X(ODDRCA)
@@ -786,6 +791,11 @@ X(OSER8)
 X(OSER10)
 X(OVIDEO)
 X(OSER16)
+X(IDES4)
+X(IDES8)
+X(IDES10)
+X(IVIDEO)
+X(IDES16)
 X(IOLOGIC)
 X(IOLOGICA)
 X(IOLOGICB)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 49d428a82f..c7da985f1d 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -817,13 +817,53 @@ static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
     case ID_OSER4:  /* fall-through*/
     case ID_OSER8:  /* fall-through*/
     case ID_OSER10: /* fall-through*/
-    case ID_OVIDEO:
+    case ID_OVIDEO: /* fall-through*/
+    case ID_IDDR:   /* fall-through*/
+    case ID_IDDRC:  /* fall-through*/
+    case ID_IDES4:  /* fall-through*/
+    case ID_IDES8:  /* fall-through*/
+    case ID_IDES10: /* fall-through*/
+    case ID_IVIDEO:
         return true;
     default:
         return false;
     }
 }
 
+// IDES has different outputs
+static void reconnect_ides_outs(CellInfo *ci)
+{
+    switch (ci->type.hash()) {
+    case ID_IDES4:
+        ci->renamePort(id_Q3, id_Q9);
+        ci->renamePort(id_Q2, id_Q8);
+        ci->renamePort(id_Q1, id_Q7);
+        ci->renamePort(id_Q0, id_Q6);
+        break;
+    case ID_IVIDEO:
+        ci->renamePort(id_Q6, id_Q9);
+        ci->renamePort(id_Q5, id_Q8);
+        ci->renamePort(id_Q4, id_Q7);
+        ci->renamePort(id_Q3, id_Q6);
+        ci->renamePort(id_Q2, id_Q5);
+        ci->renamePort(id_Q1, id_Q4);
+        ci->renamePort(id_Q0, id_Q3);
+        break;
+    case ID_IDES8:
+        ci->renamePort(id_Q7, id_Q9);
+        ci->renamePort(id_Q6, id_Q8);
+        ci->renamePort(id_Q5, id_Q7);
+        ci->renamePort(id_Q4, id_Q6);
+        ci->renamePort(id_Q3, id_Q5);
+        ci->renamePort(id_Q2, id_Q4);
+        ci->renamePort(id_Q1, id_Q3);
+        ci->renamePort(id_Q0, id_Q2);
+        break;
+    default:
+        break;
+    }
+}
+
 // Pack IO logic
 static void pack_iologic(Context *ctx)
 {
@@ -1034,6 +1074,102 @@ static void pack_iologic(Context *ctx)
                     ci->type = id_IOLOGIC;
                 }
             } break;
+            case ID_IDDR:   /* fall-through */
+            case ID_IDES4:  /* fall-through */
+            case ID_IDES8:  /* fall-through */
+            case ID_IDES10: /* fall-through */
+            case ID_IVIDEO: {
+                CellInfo *d_src = net_driven_by(ctx, ci->getPort(id_D), is_iob, id_O);
+                NPNR_ASSERT(d_src != nullptr);
+
+                auto iob_bel = d_src->attrs.find(id_BEL);
+                if (iob_bel == d_src->attrs.end()) {
+                    log_error("No constraints for %s. The pins for IDES/OSER must be specified explicitly.\n",
+                              ctx->nameOf(d_src));
+                }
+
+                Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
+                loc.z += BelZ::iologic_z;
+                ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                BelId bel = ctx->getBelByLocation(loc);
+                if (bel == BelId()) {
+                    log_info("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
+                             iob_bel->second.as_string().c_str());
+                }
+                std::string in_mode;
+                switch (ci->type.hash()) {
+                case ID_IDES4:
+                    in_mode = "IDDRX2";
+                    break;
+                case ID_IDES8:
+                    in_mode = "IDDRX4";
+                    break;
+                case ID_IDES10:
+                    in_mode = "IDDRX5";
+                    break;
+                case ID_IVIDEO:
+                    in_mode = "VIDEORX";
+                    break;
+                }
+                ci->setParam(ctx->id("INMODE"), in_mode);
+                bool use_diff_io = false;
+                if (d_src->attrs.count(id_DIFF_TYPE)) {
+                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    use_diff_io = true;
+                } else {
+                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                }
+
+                // disconnect D input: it is wired internally
+                delete_nets.insert(ci->getPort(id_D)->name);
+                d_src->disconnectPort(id_O);
+                ci->disconnectPort(id_D);
+
+                // XXX place for -9 and -9C oddity
+
+                ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
+                reconnect_ides_outs(ci);
+
+                // common clock inputs
+                if (ci->type == id_IDES4) {
+                    ci->type = id_IOLOGIC;
+                    // two IDER4 share FCLK, check it
+                    Loc other_loc = loc;
+                    other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
+                    BelId other_bel = ctx->getBelByLocation(other_loc);
+                    CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
+                    if (other_cell != nullptr) {
+                        NPNR_ASSERT(other_cell->type == id_IDES4);
+                        if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
+                            log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci), ctx->nameOf(other_cell));
+                        }
+                    }
+                } else {
+                    std::unique_ptr<CellInfo> dummy =
+                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_DUMMY_IOLOGIC_IO");
+                    loc.z = 1 - loc.z + BelZ::iologic_z;
+                    if (!use_diff_io) {
+                        dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                        new_cells.push_back(std::move(dummy));
+                    }
+                    loc.z += BelZ::iologic_z;
+
+                    std::unique_ptr<CellInfo> aux_cell =
+                            create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
+                    ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
+                    aux_cell->setParam(ctx->id("INMODE"), std::string("DDRENABLE"));
+                    aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
+                    aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    if (port_used(ci, id_RESET)) {
+                        aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                    }
+                    if (port_used(ci, id_PCLK)) {
+                        aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                    }
+                    new_cells.push_back(std::move(aux_cell));
+                    ci->type = id_IOLOGIC;
+                }
+            } break;
             default:
                 break;
             }

From 23f2877ddee51e7e69fdf2b1caaa0337e2459ce9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 5 Apr 2023 14:33:07 +0200
Subject: [PATCH 317/712] fabulous: Fix bel names for pass bels in v2 format

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/constids.inc |  2 ++
 generic/viaduct/fabulous/fabulous.cc  | 14 ++++++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/generic/viaduct/fabulous/constids.inc b/generic/viaduct/fabulous/constids.inc
index 861eedf2bf..69b2e4f98d 100644
--- a/generic/viaduct/fabulous/constids.inc
+++ b/generic/viaduct/fabulous/constids.inc
@@ -11,6 +11,8 @@ X(LATCH_NOFF)
 X(IO_1_bidirectional_frame_config_pass)
 X(InPass4_frame_config)
 X(OutPass4_frame_config)
+X(InPass4_frame_config_mux)
+X(OutPass4_frame_config_mux)
 X(RegFile_32x4)
 X(MULADD)
 X(MUX8LUT_frame_config)
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 00c8909b9b..6141974e20 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -349,9 +349,19 @@ struct FabulousImpl : ViaductAPI
                 NPNR_ASSERT(bel_idx.size() == 1);
                 int bel_z = bel_idx[0] - 'A';
                 NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
+                IdString bel_name = bel_idx.to_id(ctx);
+                if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config, id_InPass4_frame_config_mux,
+                                id_OutPass4_frame_config_mux)) {
+                    // Assign BRAM IO a nicer name than just a letter
+                    auto prefix = csv.next_field();
+                    if (prefix.empty()) {
+                        log_error("Bel definition missing field; please update FABulous!\n");
+                    }
+                    bel_name = prefix.rsplit('_').first.to_id(ctx);
+                }
                 Loc loc = tile_loc(tile);
-                curr_bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type,
-                                       Loc(loc.x, loc.y, bel_z), false, false);
+                curr_bel = ctx->addBel(IdStringList::concat(tile, bel_name), bel_type, Loc(loc.x, loc.y, bel_z), false,
+                                       false);
             } else if (cmd.in(id_I, id_O)) {
                 IdString port = csv.next_field().to_id(ctx);
                 auto wire_name = csv.next_field().split('.');

From 9bcefe46a89a1fb55ab86f2e0a3319baf1b92807 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 5 Apr 2023 20:32:44 +1000
Subject: [PATCH 318/712] gowin: Add implementation of IDDR and IDDRC
 primitives

Simple deserialization primitives are implemented for all supported boards.

Compatible with older apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc |  6 +++---
 gowin/pack.cc | 41 +++++++++++++++++++++++++++--------------
 2 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8292e3227b..ce893f1b81 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1696,9 +1696,9 @@ Arch::Arch(ArchArgs args) : args(args)
                 belname = idf("R%dC%d_IOLOGIC%c", row + 1, col + 1, 'A' + z);
                 addBel(belname, id_IOLOGIC, Loc(col, row, BelZ::iologic_z + z), false);
 
-                IdString const iologic_in_ports[] = {id_TX0,  id_TX1, id_TX2, id_TX3, id_RESET, id_CALIB,
-                                                     id_PCLK, id_D,   id_D0,  id_D1,  id_D2,    id_D3,
-                                                     id_D4,   id_D5,  id_D6,  id_D7,  id_D8,    id_D9};
+                IdString const iologic_in_ports[] = {id_TX0, id_TX1, id_TX2, id_TX3, id_RESET, id_CALIB, id_PCLK,
+                                                     id_D,   id_D0,  id_D1,  id_D2,  id_D3,    id_D4,    id_D5,
+                                                     id_D6,  id_D7,  id_D8,  id_D9,  id_CLK,   id_CLEAR};
                 for (IdString port : iologic_in_ports) {
                     portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
                     addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
diff --git a/gowin/pack.cc b/gowin/pack.cc
index c7da985f1d..d40913b657 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -834,6 +834,11 @@ static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
 static void reconnect_ides_outs(CellInfo *ci)
 {
     switch (ci->type.hash()) {
+    case ID_IDDR: /* fall-through*/
+    case ID_IDDRC:
+        ci->renamePort(id_Q1, id_Q9);
+        ci->renamePort(id_Q0, id_Q8);
+        break;
     case ID_IDES4:
         ci->renamePort(id_Q3, id_Q9);
         ci->renamePort(id_Q2, id_Q8);
@@ -1036,7 +1041,6 @@ static void pack_iologic(Context *ctx)
                 ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
 
                 if (ci->type == id_OSER4) {
-                    ci->type = id_IOLOGIC;
                     // two OSER4 share FCLK, check it
                     Loc other_loc = loc;
                     other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
@@ -1061,6 +1065,7 @@ static void pack_iologic(Context *ctx)
                     std::unique_ptr<CellInfo> aux_cell =
                             create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
                     ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
+                    aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
                     aux_cell->setParam(ctx->id("OUTMODE"), std::string("DDRENABLE"));
                     aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
                     aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
@@ -1071,10 +1076,11 @@ static void pack_iologic(Context *ctx)
                         aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
                     }
                     new_cells.push_back(std::move(aux_cell));
-                    ci->type = id_IOLOGIC;
                 }
+                ci->type = id_IOLOGIC;
             } break;
             case ID_IDDR:   /* fall-through */
+            case ID_IDDRC:  /* fall-through */
             case ID_IDES4:  /* fall-through */
             case ID_IDES8:  /* fall-through */
             case ID_IDES10: /* fall-through */
@@ -1098,6 +1104,10 @@ static void pack_iologic(Context *ctx)
                 }
                 std::string in_mode;
                 switch (ci->type.hash()) {
+                case ID_IDDR: /* fall-through */
+                case ID_IDDRC:
+                    in_mode = "IDDRX1";
+                    break;
                 case ID_IDES4:
                     in_mode = "IDDRX2";
                     break;
@@ -1131,17 +1141,19 @@ static void pack_iologic(Context *ctx)
                 reconnect_ides_outs(ci);
 
                 // common clock inputs
-                if (ci->type == id_IDES4) {
-                    ci->type = id_IOLOGIC;
-                    // two IDER4 share FCLK, check it
-                    Loc other_loc = loc;
-                    other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
-                    BelId other_bel = ctx->getBelByLocation(other_loc);
-                    CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
-                    if (other_cell != nullptr) {
-                        NPNR_ASSERT(other_cell->type == id_IDES4);
-                        if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
-                            log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci), ctx->nameOf(other_cell));
+                if (ci->type == id_IDES4 || ci->type == id_IDDR || ci->type == id_IDDRC) {
+                    if (ci->type == id_IDES4) {
+                        // two IDER4 share FCLK, check it
+                        Loc other_loc = loc;
+                        other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
+                        BelId other_bel = ctx->getBelByLocation(other_loc);
+                        CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
+                        if (other_cell != nullptr) {
+                            NPNR_ASSERT(other_cell->type == id_IDES4);
+                            if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
+                                log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci),
+                                          ctx->nameOf(other_cell));
+                            }
                         }
                     }
                 } else {
@@ -1157,6 +1169,7 @@ static void pack_iologic(Context *ctx)
                     std::unique_ptr<CellInfo> aux_cell =
                             create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
                     ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
+                    aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
                     aux_cell->setParam(ctx->id("INMODE"), std::string("DDRENABLE"));
                     aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
                     aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
@@ -1167,8 +1180,8 @@ static void pack_iologic(Context *ctx)
                         aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
                     }
                     new_cells.push_back(std::move(aux_cell));
-                    ci->type = id_IOLOGIC;
                 }
+                ci->type = id_IOLOGIC;
             } break;
             default:
                 break;

From 6455b5dd2661fd76bccc32a42577fecd4e43752d Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 11 Apr 2023 10:05:33 +0200
Subject: [PATCH 319/712] viaduct: Add support for GUIs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 docs/generic.md                    | 10 ++---
 generic/arch.cc                    | 60 ++++++++++++++++++++++--------
 generic/arch.h                     | 10 ++---
 generic/arch_pybindings.cc         | 44 +++++++++++-----------
 generic/archdefs.h                 | 12 +++++-
 generic/main.cc                    |  4 ++
 generic/viaduct/example/example.cc | 28 ++++++++++++++
 generic/viaduct_api.h              |  1 +
 gui/generic/mainwindow.cc          |  7 ++--
 machxo2/arch.cc                    |  9 ++---
 machxo2/bitstream.cc               | 11 +++---
 11 files changed, 135 insertions(+), 61 deletions(-)

diff --git a/docs/generic.md b/docs/generic.md
index 108d41d72d..acd7ca4e4e 100644
--- a/docs/generic.md
+++ b/docs/generic.md
@@ -56,14 +56,14 @@ Adds an input, output or inout pin to a bel, with an associated wire. Note that
 
 Add a bel, wire, pip or subgroup to a group, which will be created if it doesn't already exist. Groups are purely for visual presentation purposes in the user interface and are not used by any place-and-route algorithms.
 
-### void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
+### void addDecalGraphic(IdStringList decal, const GraphicElement &graphic);
 
 Add a graphic element to a _decal_, a reusable drawing that may be used to represent multiple wires, pips, bels or groups in the UI (with different offsets). The decal will be created if it doesn't already exist
 
-### void setWireDecal(WireId wire, DecalXY decalxy);
-### void setPipDecal(PipId pip, DecalXY decalxy);
-### void setBelDecal(BelId bel, DecalXY decalxy);
-### void setGroupDecal(GroupId group, DecalXY decalxy);
+### void setWireDecal(WireId wire, float x, float y, IdStringList decal);
+### void setPipDecal(PipId pip, float x, float y, IdStringList decal);
+### void setBelDecal(BelId bel, float x, float y, IdStringList decal);
+### void setGroupDecal(GroupId group, float x, float y, IdStringList decal);
 
 Sets the decal ID and offset for a wire, bel, pip or group in the UI.
 
diff --git a/generic/arch.cc b/generic/arch.cc
index c0575b87df..238fb9fc96 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -161,33 +161,47 @@ void Arch::addGroupPip(IdStringList group, PipId pip) { groups[group].pips.push_
 
 void Arch::addGroupGroup(IdStringList group, IdStringList grp) { groups[group].groups.push_back(grp); }
 
-void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
+void Arch::addDecalGraphic(IdStringList decal, const GraphicElement &graphic)
 {
-    decal_graphics[decal].push_back(graphic);
+    decal_graphics[DecalId(decal, false)].push_back(graphic); // inactive variant
+    decal_graphics[DecalId(decal, true)].push_back(graphic);  // active variant
+
+    GraphicElement &active = decal_graphics[DecalId(decal, true)].back();
+    if (active.style == GraphicElement::STYLE_INACTIVE)
+        active.style = GraphicElement::STYLE_ACTIVE;
+
     refreshUi();
 }
 
-void Arch::setWireDecal(WireId wire, DecalXY decalxy)
+void Arch::setWireDecal(WireId wire, float x, float y, IdStringList decal)
 {
-    wires.at(wire.index).decalxy = decalxy;
+    wires.at(wire.index).decalxy.x = x;
+    wires.at(wire.index).decalxy.y = y;
+    wires.at(wire.index).decalxy.decal = DecalId(decal, false);
     refreshUiWire(wire);
 }
 
-void Arch::setPipDecal(PipId pip, DecalXY decalxy)
+void Arch::setPipDecal(PipId pip, float x, float y, IdStringList decal)
 {
-    pips.at(pip.index).decalxy = decalxy;
+    pips.at(pip.index).decalxy.x = x;
+    pips.at(pip.index).decalxy.y = y;
+    pips.at(pip.index).decalxy.decal = DecalId(decal, false);
     refreshUiPip(pip);
 }
 
-void Arch::setBelDecal(BelId bel, DecalXY decalxy)
+void Arch::setBelDecal(BelId bel, float x, float y, IdStringList decal)
 {
-    bels.at(bel.index).decalxy = decalxy;
+    bels.at(bel.index).decalxy.x = x;
+    bels.at(bel.index).decalxy.y = y;
+    bels.at(bel.index).decalxy.decal = DecalId(decal, false);
     refreshUiBel(bel);
 }
 
-void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
+void Arch::setGroupDecal(GroupId group, float x, float y, IdStringList decal)
 {
-    groups[group].decalxy = decalxy;
+    groups.at(group).decalxy.x = x;
+    groups.at(group).decalxy.y = y;
+    groups.at(group).decalxy.decal = DecalId(decal, false);
     refreshUiGroup(group);
 }
 
@@ -248,7 +262,8 @@ void Arch::addCellBelPinMapping(IdString cell, IdString cell_pin, IdString bel_p
 Arch::Arch(ArchArgs args) : chipName("generic"), args(args)
 {
     // Dummy for empty decals
-    decal_graphics[DecalId()];
+    decal_graphics[DecalId(IdStringList(), false)];
+    decal_graphics[DecalId(IdStringList(), true)];
 }
 
 void IdString::initialize_arch(const BaseCtx *ctx) {}
@@ -643,16 +658,31 @@ bool Arch::route()
 const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
 {
     if (!decal_graphics.count(decal)) {
-        std::cerr << "No decal named " << decal.str(getCtx()) << std::endl;
+        std::cerr << "No decal named " << decal.name.str(getCtx()) << std::endl;
     }
     return decal_graphics.at(decal);
 }
 
-DecalXY Arch::getBelDecal(BelId bel) const { return bel_info(bel).decalxy; }
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+    DecalXY result = bel_info(bel).decalxy;
+    result.decal.active = getBoundBelCell(bel) != nullptr;
+    return result;
+}
 
-DecalXY Arch::getWireDecal(WireId wire) const { return wire_info(wire).decalxy; }
+DecalXY Arch::getWireDecal(WireId wire) const
+{
+    DecalXY result = wire_info(wire).decalxy;
+    result.decal.active = getBoundWireNet(wire) != nullptr;
+    return result;
+}
 
-DecalXY Arch::getPipDecal(PipId pip) const { return pip_info(pip).decalxy; }
+DecalXY Arch::getPipDecal(PipId pip) const
+{
+    DecalXY result = pip_info(pip).decalxy;
+    result.decal.active = getBoundPipNet(pip) != nullptr;
+    return result;
+}
 
 DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
 
diff --git a/generic/arch.h b/generic/arch.h
index 19a0a07805..40994ad093 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -211,11 +211,11 @@ struct Arch : BaseArch<ArchRanges>
     void addGroupPip(IdStringList group, PipId pip);
     void addGroupGroup(IdStringList group, IdStringList grp);
 
-    void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
-    void setWireDecal(WireId wire, DecalXY decalxy);
-    void setPipDecal(PipId pip, DecalXY decalxy);
-    void setBelDecal(BelId bel, DecalXY decalxy);
-    void setGroupDecal(GroupId group, DecalXY decalxy);
+    void addDecalGraphic(IdStringList decal, const GraphicElement &graphic);
+    void setWireDecal(WireId wire, float x, float y, IdStringList decal);
+    void setPipDecal(PipId pip, float x, float y, IdStringList decal);
+    void setBelDecal(BelId bel, float x, float y, IdStringList decal);
+    void setGroupDecal(GroupId group, float x, float y, IdStringList decal);
 
     void setWireAttr(WireId wire, IdString key, const std::string &value);
     void setPipAttr(PipId pip, IdString key, const std::string &value);
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index a5a0bed94c..f067936c0e 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -55,14 +55,6 @@ void arch_wrap_python(py::module &m)
 
     auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
 
-    auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
-    readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>,
-                      conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal");
-    readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap(
-            dxy_cls, "x");
-    readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap(
-            dxy_cls, "y");
-
     auto ctx_cls = py::class_<Context, Arch>(m, "Context")
                            .def("checksum", &Context::checksum)
                            .def("pack", &Context::pack)
@@ -72,9 +64,6 @@ void arch_wrap_python(py::module &m)
     auto belpin_cls =
             py::class_<BelPin>(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
 
-    fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
-                  conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
-
     typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap;
     typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap;
     typedef dict<IdString, HierarchicalCell> HierarchyMap;
@@ -121,16 +110,29 @@ void arch_wrap_python(py::module &m)
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupGroup, conv_from_str<IdStringList>,
                     conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
 
-    fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
-                    pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic"));
-    fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<WireId>,
-                    unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", "wire"_a, "decalxy"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<PipId>,
-                    unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", "pip"_a, "decalxy"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<BelId>,
-                    unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", "bel"_a, "decalxy"_a);
-    fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
-                    unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", "group"_a, "decalxy"_a);
+    fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic,
+                    conv_from_str<IdStringList>, pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic",
+                                                                                         (py::arg("decal"), "graphic"));
+    fn_wrapper_4a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<WireId>,
+                    pass_through<float>, pass_through<float>, conv_from_str<IdStringList>>::def_wrap(ctx_cls,
+                                                                                                     "setWireDecal",
+                                                                                                     "wire"_a, "x"_a,
+                                                                                                     "y"_a, "decal"_a);
+    fn_wrapper_4a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<PipId>,
+                    pass_through<float>, pass_through<float>, conv_from_str<IdStringList>>::def_wrap(ctx_cls,
+                                                                                                     "setPipDecal",
+                                                                                                     "pip"_a, "x"_a,
+                                                                                                     "y"_a, "decal"_a);
+    fn_wrapper_4a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<BelId>,
+                    pass_through<float>, pass_through<float>, conv_from_str<IdStringList>>::def_wrap(ctx_cls,
+                                                                                                     "setBelDecal",
+                                                                                                     "bel"_a, "x"_a,
+                                                                                                     "y"_a, "decal"_a);
+    fn_wrapper_4a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<GroupId>,
+                    pass_through<float>, pass_through<float>, conv_from_str<IdStringList>>::def_wrap(ctx_cls,
+                                                                                                     "setGroupDecal",
+                                                                                                     "group"_a, "x"_a,
+                                                                                                     "y"_a, "decal"_a);
 
     fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<WireId>,
                     conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", "wire"_a,
diff --git a/generic/archdefs.h b/generic/archdefs.h
index 4e91ffd3ab..374ddeb0fb 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -64,8 +64,18 @@ struct PipId
     unsigned int hash() const { return index; }
 };
 
+struct DecalId
+{
+    IdStringList name;
+    bool active = false;
+    DecalId() : name(), active(false){};
+    DecalId(IdStringList name, bool active) : name(name), active(active){};
+    bool operator==(const DecalId &other) const { return name == other.name && active == other.active; }
+    bool operator!=(const DecalId &other) const { return name != other.name || active != other.active; }
+    unsigned int hash() const { return mkhash(name.hash(), active); }
+};
+
 typedef IdStringList GroupId;
-typedef IdStringList DecalId;
 typedef IdString BelBucketId;
 typedef IdString ClusterId;
 
diff --git a/generic/main.cc b/generic/main.cc
index 3ee1c790fa..7aece56999 100644
--- a/generic/main.cc
+++ b/generic/main.cc
@@ -86,9 +86,13 @@ std::unique_ptr<Context> GenericCommandHandler::createContext(dict<std::string,
             log_error("Unknown viaduct uarch '%s'; available options: '%s'\n", uarch_name.c_str(), all_uarches.c_str());
         }
         ctx->uarch = std::move(uarch);
+        if (vm.count("gui"))
+            ctx->uarch->with_gui = true;
         ctx->uarch->init(ctx.get());
     } else if (vm.count("vopt")) {
         log_error("Viaduct options passed in non-viaduct mode!\n");
+    } else if (vm.count("gui")) {
+        log_error("nextpnr-generic GUI only supported in viaduct mode!\n");
     }
     return ctx;
 }
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
index 7a61a59493..7de0404bb7 100644
--- a/generic/viaduct/example/example.cc
+++ b/generic/viaduct/example/example.cc
@@ -38,6 +38,8 @@ struct ExampleImpl : ViaductAPI
         init_uarch_constids(ctx);
         ViaductAPI::init(ctx);
         h.init(ctx);
+        if (with_gui)
+            init_bel_decals();
         init_wires();
         init_bels();
         init_pips();
@@ -150,6 +152,28 @@ struct ExampleImpl : ViaductAPI
         IdStringList name = IdStringList::concat(ctx->getWireName(dst), ctx->getWireName(src));
         return ctx->addPip(name, ctx->id("PIP"), src, dst, delay, loc);
     }
+
+    static constexpr float lut_x1 = 0.8f;
+    static constexpr float lut_w = 0.07f;
+    static constexpr float ff_x1 = 0.9f;
+    static constexpr float ff_w = 0.05f;
+    static constexpr float bel_y1 = 0.2f;
+    static constexpr float bel_h = 0.03f;
+    static constexpr float bel_dy = 0.05f;
+    void init_bel_decals()
+    {
+        for (int z = 0; z < N; z++) {
+            float y1 = bel_y1 + z * bel_dy;
+            float y2 = y1 + bel_h;
+            ctx->addDecalGraphic(IdStringList(ctx->idf("LUT%d", z)),
+                                 GraphicElement(GraphicElement::TYPE_BOX, GraphicElement::STYLE_INACTIVE, lut_x1, y1,
+                                                lut_x1 + lut_w, y2, 10.0));
+            ctx->addDecalGraphic(IdStringList(ctx->idf("FF%d", z)),
+                                 GraphicElement(GraphicElement::TYPE_BOX, GraphicElement::STYLE_INACTIVE, ff_x1, y1,
+                                                ff_x1 + ff_w, y2, 10.0));
+        }
+    }
+
     // Create LUT and FF bels in a logic tile
     void add_slice_bels(int x, int y)
     {
@@ -169,6 +193,10 @@ struct ExampleImpl : ViaductAPI
             ctx->addBelInput(dff, id_CLK, w.clk.at(z));
             ctx->addBelInput(dff, id_D, w.d.at(z));
             ctx->addBelOutput(dff, id_Q, w.q.at(z));
+            if (with_gui) {
+                ctx->setBelDecal(lut, x, y, IdStringList(ctx->idf("LUT%d", z)));
+                ctx->setBelDecal(dff, x, y, IdStringList(ctx->idf("FF%d", z)));
+            }
         }
     }
     // Create bels according to tile type
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
index 3caa0ba19d..6d6423b66e 100644
--- a/generic/viaduct_api.h
+++ b/generic/viaduct_api.h
@@ -55,6 +55,7 @@ struct ViaductAPI
 {
     virtual void init(Context *ctx);
     Context *ctx;
+    bool with_gui = false;
 
     // --- Bel functions ---
     // Called when a bel is placed/unplaced (with cell=nullptr for a unbind)
diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc
index 5697718cae..aeb5c04be2 100644
--- a/gui/generic/mainwindow.cc
+++ b/gui/generic/mainwindow.cc
@@ -30,8 +30,6 @@ MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler
         : BaseMainWindow(std::move(context), handler, parent)
 {
     initMainResource();
-    QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-generic");
-    std::exit(1);
 }
 
 MainWindow::~MainWindow() {}
@@ -44,6 +42,9 @@ void MainWindow::newContext(Context *ctx)
 
 void MainWindow::createMenu() {}
 
-void MainWindow::new_proj() {}
+void MainWindow::new_proj() {
+    QMessageBox::critical(0, "Error", "Creating a new project not supported in Viaduct mode, please re-start from command line.");
+    std::exit(1);   
+}
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index f2c87888ec..022fb8ffb7 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -315,9 +315,9 @@ IdStringList Arch::getPipName(PipId pip) const
 {
     auto &pip_data = tile_info(pip)->pip_data[pip.index];
     WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
-    std::string pip_name = stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x, pip_data.src.y,
-                                   get_wire_basename(src).c_str(this), pip_data.dst.x, pip_data.dst.y,
-                                   get_wire_basename(dst).c_str(this));
+    std::string pip_name =
+            stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x, pip_data.src.y, get_wire_basename(src).c_str(this),
+                    pip_data.dst.x, pip_data.dst.y, get_wire_basename(dst).c_str(this));
 
     std::array<IdString, 3> ids{x_ids.at(pip.location.x), y_ids.at(pip.location.y), id(pip_name)};
     return IdStringList(ids);
@@ -490,8 +490,7 @@ std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row,
     std::vector<std::pair<std::string, std::string>> ret;
     auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
     for (auto &tn : tileloc.tile_names) {
-        ret.push_back(std::make_pair(tn.name.get(),
-                                     chip_info->tiletype_names[tn.type_idx].get()));
+        ret.push_back(std::make_pair(tn.name.get(), chip_info->tiletype_names[tn.type_idx].get()));
     }
     return ret;
 }
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index e6b1bb1704..5b0e8664b5 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -176,12 +176,11 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
 {
     static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
     static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
-    static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
-                                                "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
-                                                "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
-                                                "PIC_L2_VREF4", "PIC_L2_VREF5",
-                                                "PIC_L3_VREF4", "PIC_L3_VREF5"};
-    static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
+    static const std::set<std::string> pio_l = {"PIC_L0",       "PIC_L1",       "PIC_L2",       "PIC_L3",
+                                                "PIC_LS0",      "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
+                                                "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5", "PIC_L2_VREF4",
+                                                "PIC_L2_VREF5", "PIC_L3_VREF4", "PIC_L3_VREF5"};
+    static const std::set<std::string> pio_r = {"PIC_R0",     "PIC_R1",     "PIC_RS0",
                                                 "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
 
     std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();

From 7557d33dc670f0863c5a085e1d755ff693e05fbf Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 11 Apr 2023 11:16:40 +0200
Subject: [PATCH 320/712] ecp5: Fix invalid accesses during certain IO packing
 cases

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index d605b4a394..3b56daa92f 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -552,11 +552,13 @@ class Ecp5Packer
                     if (ionet != nullptr) {
                         ctx->nets.erase(ionet->name);
                         tp.cell->ports.at(tp.port).net = nullptr;
+                        ci->ports.at(ci->type == ctx->id("$nextpnr_obuf") ? id_I : id_O).net = nullptr;
                     }
                     if (ci->type == ctx->id("$nextpnr_iobuf")) {
                         NetInfo *net2 = ci->ports.at(id_I).net;
                         if (net2 != nullptr) {
                             ctx->nets.erase(net2->name);
+                            ci->ports.at(id_I).net = nullptr;
                         }
                     }
                 } else {

From fddacb3dc1dd4c977d48bd91fc73b8177e44a632 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 12 Apr 2023 13:42:16 +1000
Subject: [PATCH 321/712] gowin: implement IDES16 and OSER16 primitives

These are very cumbersome primitives that take up two cells and
consequently 4 IOLOGIC bels.
The primitives are implemented for the chips that contain them and are
supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      | 162 ++++++++++++++++++++++++-
 gowin/arch.h       |   6 +-
 gowin/cells.cc     |   1 +
 gowin/constids.inc |  17 ++-
 gowin/pack.cc      | 287 +++++++++++++++++++++++++++++++++++++++++++--
 5 files changed, 454 insertions(+), 19 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index ce893f1b81..8033048f4a 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1194,6 +1194,70 @@ void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString be
     }
 }
 
+static bool skip_aux_oser16(std::string device, int row, int col)
+{
+    if (device == "GW1NSR-4C") {
+        switch (col) {
+        case 2:  /* fall-through*/
+        case 4:  /* fall-through*/
+        case 6:  /* fall-through*/
+        case 8:  /* fall-through*/
+        case 9:  /* fall-through*/
+        case 11: /* fall-through*/
+        case 13: /* fall-through*/
+        case 15: /* fall-through*/
+        case 17: /* fall-through*/
+        case 18: /* fall-through*/
+        case 20: /* fall-through*/
+        case 22: /* fall-through*/
+        case 24: /* fall-through*/
+        case 26: /* fall-through*/
+        case 27: /* fall-through*/
+        case 29: /* fall-through*/
+        case 31: /* fall-through*/
+        case 33: /* fall-through*/
+        case 35:
+            return true;
+        default:
+            break;
+        }
+    }
+    if (device == "GW1NR-9" || device == "GW1NR-9C") {
+        switch (col) {
+        case 2:  /* fall-through*/
+        case 4:  /* fall-through*/
+        case 6:  /* fall-through*/
+        case 8:  /* fall-through*/
+        case 9:  /* fall-through*/
+        case 11: /* fall-through*/
+        case 13: /* fall-through*/
+        case 15: /* fall-through*/
+        case 17: /* fall-through*/
+        case 18: /* fall-through*/
+        case 19: /* fall-through*/
+        case 21: /* fall-through*/
+        case 23: /* fall-through*/
+        case 25: /* fall-through*/
+        case 27: /* fall-through*/
+        case 28: /* fall-through*/
+        case 29: /* fall-through*/
+        case 31: /* fall-through*/
+        case 33: /* fall-through*/
+        case 35: /* fall-through*/
+        case 36: /* fall-through*/
+        case 37: /* fall-through*/
+        case 39: /* fall-through*/
+        case 41: /* fall-through*/
+        case 43: /* fall-through*/
+        case 45:
+            return true;
+        default:
+            break;
+        }
+    }
+    return false;
+}
+
 Arch::Arch(ArchArgs args) : args(args)
 {
     family = args.family;
@@ -1745,6 +1809,92 @@ Arch::Arch(ArchArgs args) : args(args)
                     }
                 }
             } break;
+            case ID_OSER16: {
+                if (skip_aux_oser16(device, row, col)) {
+                    break;
+                }
+                belname = idf("R%dC%d_OSER16", row + 1, col + 1);
+                addBel(belname, id_OSER16, Loc(col, row, BelZ::oser16_z), false);
+
+                IdString const oser16_in_ports[] = {id_RESET, id_PCLK, id_D0,  id_D1,  id_D2,  id_D3,
+                                                    id_D4,    id_D5,   id_D6,  id_D7,  id_D8,  id_D9,
+                                                    id_D10,   id_D11,  id_D12, id_D13, id_D14, id_D15};
+                for (IdString port : oser16_in_ports) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+                    addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                }
+                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, id_Q0.hash())->src_id);
+                addBelOutput(belname, id_Q, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                auto fclk = pairLookup(bel->ports.get(), bel->num_ports, ID_FCLK);
+                // XXX as long as there is no special processing of the pins
+                if (fclk != nullptr) {
+                    portname = IdString(fclk->src_id);
+                    IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    if (wires.count(wire) == 0) {
+                        GlobalAliasPOD alias;
+                        alias.dest_col = col;
+                        alias.dest_row = row;
+                        alias.dest_id = portname.hash();
+                        auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+                        if (alias_src != nullptr) {
+                            int srcrow = alias_src->src_row;
+                            int srccol = alias_src->src_col;
+                            IdString srcid = IdString(alias_src->src_id);
+                            wire = wireToGlobal(srcrow, srccol, db, srcid);
+                            if (wires.count(wire) == 0) {
+                                addWire(wire, srcid, srccol, srcrow);
+                            }
+                            addBelInput(belname, id_FCLK, wire);
+                        }
+                    } else {
+                        addBelInput(belname, id_FCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    }
+                }
+            } break;
+            case ID_IDES16: {
+                if (skip_aux_oser16(device, row, col)) {
+                    break;
+                }
+                belname = idf("R%dC%d_IDES16", row + 1, col + 1);
+                addBel(belname, id_IDES16, Loc(col, row, BelZ::ides16_z), false);
+
+                IdString const ides16_in_ports[] = {id_RESET, id_PCLK, id_CALIB, id_D};
+                for (IdString port : ides16_in_ports) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+                    addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                }
+                IdString const ides16_out_ports[] = {id_Q0, id_Q1, id_Q2,  id_Q3,  id_Q4,  id_Q5,  id_Q6,  id_Q7,
+                                                     id_Q8, id_Q9, id_Q10, id_Q11, id_Q12, id_Q13, id_Q14, id_Q15};
+                for (IdString port : ides16_out_ports) {
+                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+                    addBelOutput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                }
+                auto fclk = pairLookup(bel->ports.get(), bel->num_ports, ID_FCLK);
+                // XXX as long as there is no special processing of the pins
+                if (fclk != nullptr) {
+                    portname = IdString(fclk->src_id);
+                    IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
+                    if (wires.count(wire) == 0) {
+                        GlobalAliasPOD alias;
+                        alias.dest_col = col;
+                        alias.dest_row = row;
+                        alias.dest_id = portname.hash();
+                        auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+                        if (alias_src != nullptr) {
+                            int srcrow = alias_src->src_row;
+                            int srccol = alias_src->src_col;
+                            IdString srcid = IdString(alias_src->src_id);
+                            wire = wireToGlobal(srcrow, srccol, db, srcid);
+                            if (wires.count(wire) == 0) {
+                                addWire(wire, srcid, srccol, srcrow);
+                            }
+                            addBelInput(belname, id_FCLK, wire);
+                        }
+                    } else {
+                        addBelInput(belname, id_FCLK, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    }
+                }
+            } break;
             default:
                 break;
             }
@@ -2312,6 +2462,7 @@ void Arch::fix_pll_nets(Context *ctx)
 // mark with hclk is used
 void Arch::mark_used_hclk(Context *ctx)
 {
+    pool<IdString> aux_cells;
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (ci->type != id_IOLOGIC) {
@@ -2322,6 +2473,7 @@ void Arch::mark_used_hclk(Context *ctx)
         }
         // if it's an aux cell
         if (ci->attrs.count(id_IOLOGIC_MASTER_CELL)) {
+            aux_cells.insert(ci->name);
             continue;
         }
         ci->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
@@ -2345,16 +2497,16 @@ void Arch::mark_used_hclk(Context *ctx)
                     if (!checkPipAvail(pip)) {
                         WireId src_wire = getPipSrcWire(pip);
                         ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));
-                        if (ci->attrs.count(id_IOLOGIC_AUX_CELL)) {
-                            IdString aux_cell_name = ctx->id(ci->attrs[id_IOLOGIC_AUX_CELL].as_string());
-                            ctx->cells[aux_cell_name]->setAttr(id_IOLOGIC_FCLK,
-                                                               Property(wire_info(src_wire).type.str(this)));
-                        }
                     }
                 }
             }
         }
     }
+    for (auto acell : aux_cells) {
+        IdString main_cell = ctx->id(ctx->cells.at(acell)->attrs.at(id_IOLOGIC_MASTER_CELL).as_string());
+        Property &fclk = ctx->cells.at(main_cell)->attrs.at(id_IOLOGIC_FCLK);
+        ctx->cells.at(acell)->setAttr(id_IOLOGIC_FCLK, fclk);
+    }
 }
 
 void Arch::pre_route(Context *ctx)
diff --git a/gowin/arch.h b/gowin/arch.h
index 595c82a06e..23da366149 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -532,6 +532,8 @@ struct Arch : BaseArch<ArchRanges>
 namespace BelZ {
 enum
 {
+    ioba_z = 0,      // IOBA
+    iobb_z = 1,      // IOBB
     mux_0_z = 10,    // start Z for the MUX2LUT5 bels
     oddr_0_z = 20,   // XXX start Z for the ODDR bels
     lutram_0_z = 30, // start Z for the LUTRAM bels
@@ -542,7 +544,9 @@ enum
     pll_z = 289,     // PLL
     pllvr_z = 290,   // PLLVR
     iologic_z = 291, // IOLOGIC
-    free_z = 293     // Must be the last, one can use z starting from this value, adjust accordingly.
+    oser16_z = 293,  // OSER16
+    ides16_z = 294,  // IDES16
+    free_z = 295     // Must be the last, one can use z starting from this value, adjust accordingly.
 };
 }
 
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 436b4766b6..c2d77e224b 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -106,6 +106,7 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_CLKOUTD3);
         new_cell->addOutput(id_LOCK);
     } else if (type == id_IOLOGIC) {
+        new_cell->addInput(id_FCLK);
         new_cell->addInput(id_PCLK);
         new_cell->addInput(id_RESET);
     } else if (type == id_DUMMY_CELL) {
diff --git a/gowin/constids.inc b/gowin/constids.inc
index 5bd2aa4640..daedb8a66c 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -767,8 +767,6 @@ X(TX3)
 X(FCLK)
 X(PCLK)
 X(CALIB)
-X(Q8)
-X(Q9)
 X(ODDR_ALWAYS_LOW)
 X(ODDR_ALWAYS_HIGH)
 X(GW9_ALWAYS_LOW0)
@@ -776,6 +774,7 @@ X(GW9_ALWAYS_LOW1)
 X(GW9C_ALWAYS_LOW0)
 X(GW9C_ALWAYS_LOW1)
 X(OBUF_TYPE)
+X(IBUF_TYPE)
 X(SBUF)
 X(DBUF)
 X(ODDR)
@@ -805,6 +804,20 @@ X(IOLOGIC_MASTER_CELL)
 X(IOLOGIC_AUX_CELL)
 X(D8)
 X(D9)
+X(D10)
+X(D11)
+X(D12)
+X(D13)
+X(D14)
+X(D15)
+X(Q8)
+X(Q9)
+X(Q10)
+X(Q11)
+X(Q12)
+X(Q13)
+X(Q14)
+X(Q15)
 
 // Wide LUTs
 X(MUX2_LUT5)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index d40913b657..2ff42e55e9 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -817,12 +817,14 @@ static bool is_gowin_iologic(const Context *ctx, const CellInfo *cell)
     case ID_OSER4:  /* fall-through*/
     case ID_OSER8:  /* fall-through*/
     case ID_OSER10: /* fall-through*/
+    case ID_OSER16: /* fall-through*/
     case ID_OVIDEO: /* fall-through*/
     case ID_IDDR:   /* fall-through*/
     case ID_IDDRC:  /* fall-through*/
     case ID_IDES4:  /* fall-through*/
     case ID_IDES8:  /* fall-through*/
     case ID_IDES10: /* fall-through*/
+    case ID_IDES16: /* fall-through*/
     case ID_IVIDEO:
         return true;
     default:
@@ -869,6 +871,21 @@ static void reconnect_ides_outs(CellInfo *ci)
     }
 }
 
+static void get_next_oser16_loc(std::string device, Loc &loc)
+{
+    if (device == "GW1NSR-4C") {
+        if (loc.y == 0) {
+            ++loc.x;
+        } else {
+            ++loc.y;
+        }
+    } else {
+        if (device == "GW1NR-9" || device == "GW1NR-9C") {
+            ++loc.x;
+        }
+    }
+}
+
 // Pack IO logic
 static void pack_iologic(Context *ctx)
 {
@@ -1054,7 +1071,7 @@ static void pack_iologic(Context *ctx)
                     }
                 } else {
                     std::unique_ptr<CellInfo> dummy =
-                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_DUMMY_IOLOGIC_IO");
+                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO");
                     loc.z = 1 - loc.z + BelZ::iologic_z;
                     if (!use_diff_io) {
                         dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
@@ -1064,7 +1081,6 @@ static void pack_iologic(Context *ctx)
 
                     std::unique_ptr<CellInfo> aux_cell =
                             create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
-                    ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
                     aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
                     aux_cell->setParam(ctx->id("OUTMODE"), std::string("DDRENABLE"));
                     aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
@@ -1099,8 +1115,8 @@ static void pack_iologic(Context *ctx)
                 ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
                 BelId bel = ctx->getBelByLocation(loc);
                 if (bel == BelId()) {
-                    log_info("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
-                             iob_bel->second.as_string().c_str());
+                    log_error("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
+                              iob_bel->second.as_string().c_str());
                 }
                 std::string in_mode;
                 switch (ci->type.hash()) {
@@ -1124,19 +1140,16 @@ static void pack_iologic(Context *ctx)
                 ci->setParam(ctx->id("INMODE"), in_mode);
                 bool use_diff_io = false;
                 if (d_src->attrs.count(id_DIFF_TYPE)) {
-                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF"));
                     use_diff_io = true;
                 } else {
-                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF"));
                 }
 
                 // disconnect D input: it is wired internally
                 delete_nets.insert(ci->getPort(id_D)->name);
                 d_src->disconnectPort(id_O);
                 ci->disconnectPort(id_D);
-
-                // XXX place for -9 and -9C oddity
-
                 ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
                 reconnect_ides_outs(ci);
 
@@ -1158,7 +1171,7 @@ static void pack_iologic(Context *ctx)
                     }
                 } else {
                     std::unique_ptr<CellInfo> dummy =
-                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_DUMMY_IOLOGIC_IO");
+                            create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO");
                     loc.z = 1 - loc.z + BelZ::iologic_z;
                     if (!use_diff_io) {
                         dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
@@ -1168,7 +1181,6 @@ static void pack_iologic(Context *ctx)
 
                     std::unique_ptr<CellInfo> aux_cell =
                             create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX");
-                    ci->setAttr(ctx->id("IOLOGIC_AUX_CELL"), ci->name.str(ctx) + "_AUX");
                     aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
                     aux_cell->setParam(ctx->id("INMODE"), std::string("DDRENABLE"));
                     aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), ci->name.str(ctx));
@@ -1183,6 +1195,259 @@ static void pack_iologic(Context *ctx)
                 }
                 ci->type = id_IOLOGIC;
             } break;
+            case ID_OSER16: {
+                IdString output = id_Q;
+                q0_dst = net_only_drives(ctx, ci->ports.at(output).net, is_iob, id_I);
+                NPNR_ASSERT(q0_dst != nullptr);
+
+                auto iob_bel = q0_dst->attrs.find(id_BEL);
+                if (iob_bel == q0_dst->attrs.end()) {
+                    log_error("No constraints for %s. The pins for IDES/OSER must be specified explicitly.\n",
+                              ctx->nameOf(q0_dst));
+                }
+
+                Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
+                if (loc.z != BelZ::ioba_z) {
+                    log_error("IDES16/OSER16 %s must be an A pin.\n", ctx->nameOf(ci));
+                }
+
+                loc.z = BelZ::oser16_z;
+                ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                BelId bel = ctx->getBelByLocation(loc);
+                if (bel == BelId()) {
+                    log_error("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
+                              iob_bel->second.as_string().c_str());
+                }
+
+                bool use_diff_io = false;
+                if (q0_dst->attrs.count(id_DIFF_TYPE)) {
+                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    use_diff_io = true;
+                } else {
+                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                }
+
+                // disconnect Q output: it is wired internally
+                delete_nets.insert(ci->ports.at(output).net->name);
+                q0_dst->disconnectPort(id_I);
+                ci->disconnectPort(output);
+                loc.z = BelZ::ioba_z;
+                if (ctx->bels.at(ctx->getBelByLocation(loc)).pins.count(id_GW9C_ALWAYS_LOW1)) {
+                    q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
+                    q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                }
+                if (ctx->bels.at(ctx->getBelByLocation(loc)).pins.count(id_GW9_ALWAYS_LOW0)) {
+                    q0_dst->disconnectPort(id_GW9_ALWAYS_LOW0);
+                    q0_dst->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                }
+
+                // make aux cells
+                std::unique_ptr<CellInfo> dummy =
+                        create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO");
+                loc.z = BelZ::iobb_z;
+                if (!use_diff_io) {
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+                loc.z = BelZ::iologic_z;
+
+                // main iologic cell
+                std::string master_name = ci->name.str(ctx) + "_MAIN";
+
+                // aux cells
+                std::unique_ptr<CellInfo> aux_cell = create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX0");
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("OSER16"));
+                aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), master_name);
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("OUTMODE"), std::string("ODDRX8"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                new_cells.push_back(std::move(aux_cell));
+
+                // aux iologic cells
+                loc.z = BelZ::iologic_z + 1;
+                aux_cell = create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX1");
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
+                aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), master_name);
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("OUTMODE"), std::string("DDRENABLE16"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                new_cells.push_back(std::move(aux_cell));
+
+                // master
+                get_next_oser16_loc(ctx->device, loc);
+                loc.z = BelZ::iologic_z;
+                aux_cell = create_generic_cell(ctx, id_IOLOGIC, master_name);
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("OUTMODE"), std::string("DDRENABLE16"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                ci->movePortTo(id_FCLK, aux_cell.get(), id_FCLK);
+                ci->movePortTo(id_D12, aux_cell.get(), id_D0);
+                ci->movePortTo(id_D13, aux_cell.get(), id_D1);
+                ci->movePortTo(id_D14, aux_cell.get(), id_D2);
+                ci->movePortTo(id_D15, aux_cell.get(), id_D3);
+                new_cells.push_back(std::move(aux_cell));
+
+                // bottom row is special and may need two additional ports
+                loc.z = BelZ::ioba_z;
+                if (ctx->getBelByLocation(loc) != BelId()) {
+                    dummy = create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO0");
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+
+                // XXX Prohibit the use of 4th IO and IOLOGIC
+                loc.z = BelZ::iobb_z;
+                if (ctx->getBelByLocation(loc) != BelId()) {
+                    dummy = create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO1");
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+                master_name = ci->name.str(ctx) + "_AUX2";
+                loc.z = BelZ::iologic_z + 1;
+                dummy = create_generic_cell(ctx, id_DUMMY_CELL, master_name);
+                dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                new_cells.push_back(std::move(dummy));
+            } break;
+            case ID_IDES16: {
+                CellInfo *d_src = net_driven_by(ctx, ci->getPort(id_D), is_iob, id_O);
+                NPNR_ASSERT(d_src != nullptr);
+
+                auto iob_bel = d_src->attrs.find(id_BEL);
+                if (iob_bel == d_src->attrs.end()) {
+                    log_error("No constraints for %s. The pins for IDES/OSER must be specified explicitly.\n",
+                              ctx->nameOf(d_src));
+                }
+                Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
+                if (loc.z != BelZ::ioba_z) {
+                    log_error("IDES16/OSER16 %s must be an A pin.\n", ctx->nameOf(ci));
+                }
+
+                loc.z += BelZ::ides16_z;
+                ci->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                BelId bel = ctx->getBelByLocation(loc);
+                if (bel == BelId()) {
+                    log_error("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
+                              iob_bel->second.as_string().c_str());
+                }
+
+                bool use_diff_io = false;
+                if (d_src->attrs.count(id_DIFF_TYPE)) {
+                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF"));
+                    use_diff_io = true;
+                } else {
+                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF"));
+                }
+                // disconnect D input: it is wired internally
+                delete_nets.insert(ci->getPort(id_D)->name);
+                d_src->disconnectPort(id_O);
+                ci->disconnectPort(id_D);
+                ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
+
+                // make aux cells
+                std::unique_ptr<CellInfo> dummy =
+                        create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO");
+                loc.z = BelZ::iobb_z;
+                if (!use_diff_io) {
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+                loc.z = BelZ::iologic_z;
+
+                // main iologic cell
+                std::string master_name = ci->name.str(ctx) + "_MAIN";
+
+                // aux cells
+                std::unique_ptr<CellInfo> aux_cell = create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX0");
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("IDES16"));
+                aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), master_name);
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("INMODE"), std::string("IDDRX8"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                new_cells.push_back(std::move(aux_cell));
+
+                // aux iologic cells
+                loc.z = BelZ::iologic_z + 1;
+                aux_cell = create_generic_cell(ctx, id_IOLOGIC, ci->name.str(ctx) + "_AUX1");
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
+                aux_cell->setAttr(ctx->id("IOLOGIC_MASTER_CELL"), master_name);
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("INMODE"), std::string("DDRENABLE16"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                new_cells.push_back(std::move(aux_cell));
+
+                // master
+                get_next_oser16_loc(ctx->device, loc);
+                loc.z = BelZ::iologic_z;
+                aux_cell = create_generic_cell(ctx, id_IOLOGIC, master_name);
+                aux_cell->setAttr(id_IOLOGIC_TYPE, std::string("DUMMY"));
+                aux_cell->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                aux_cell->setParam(ctx->id("INMODE"), std::string("DDRENABLE16"));
+                aux_cell->setParam(ctx->id("UPDATE"), std::string("SAME"));
+                if (port_used(ci, id_RESET)) {
+                    aux_cell->connectPort(id_RESET, ci->ports.at(id_RESET).net);
+                }
+                if (port_used(ci, id_PCLK)) {
+                    aux_cell->connectPort(id_PCLK, ci->ports.at(id_PCLK).net);
+                }
+                ci->movePortTo(id_FCLK, aux_cell.get(), id_FCLK);
+                ci->movePortTo(id_Q0, aux_cell.get(), id_Q6);
+                ci->movePortTo(id_Q1, aux_cell.get(), id_Q7);
+                ci->movePortTo(id_Q2, aux_cell.get(), id_Q8);
+                ci->movePortTo(id_Q3, aux_cell.get(), id_Q9);
+                new_cells.push_back(std::move(aux_cell));
+
+                // bottom row is special and may need two additional ports
+                loc.z = BelZ::ioba_z;
+                if (ctx->getBelByLocation(loc) != BelId()) {
+                    dummy = create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO0");
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+
+                // XXX Prohibit the use of 4th IO and IOLOGIC
+                loc.z = BelZ::iobb_z;
+                if (ctx->getBelByLocation(loc) != BelId()) {
+                    dummy = create_generic_cell(ctx, id_DUMMY_CELL, ci->name.str(ctx) + "_IOLOGIC_IO1");
+                    dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                    new_cells.push_back(std::move(dummy));
+                }
+                master_name = ci->name.str(ctx) + "_AUX2";
+                loc.z = BelZ::iologic_z + 1;
+                dummy = create_generic_cell(ctx, id_DUMMY_CELL, master_name);
+                dummy->setAttr(id_BEL, ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx));
+                new_cells.push_back(std::move(dummy));
+            } break;
             default:
                 break;
             }

From 62b8baa9595aacc4373bd47af479157322ffa85a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 12 Apr 2023 18:18:16 +1000
Subject: [PATCH 322/712] gowin: Fix style

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8033048f4a..0278cd8fb4 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1816,7 +1816,7 @@ Arch::Arch(ArchArgs args) : args(args)
                 belname = idf("R%dC%d_OSER16", row + 1, col + 1);
                 addBel(belname, id_OSER16, Loc(col, row, BelZ::oser16_z), false);
 
-                IdString const oser16_in_ports[] = {id_RESET, id_PCLK, id_D0,  id_D1,  id_D2,  id_D3,
+                const IdString oser16_in_ports[] = {id_RESET, id_PCLK, id_D0,  id_D1,  id_D2,  id_D3,
                                                     id_D4,    id_D5,   id_D6,  id_D7,  id_D8,  id_D9,
                                                     id_D10,   id_D11,  id_D12, id_D13, id_D14, id_D15};
                 for (IdString port : oser16_in_ports) {

From b0a78de78f213d6cb169a22e38179c48f3dc02fc Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 12 Apr 2023 17:16:49 +0200
Subject: [PATCH 323/712] fabulous: Support for configurable LUT size

Signed-off-by: gatecat <gatecat@ds0.me>
---
 generic/viaduct/fabulous/fabulous.cc | 2 ++
 generic/viaduct/fabulous/fasm.cc     | 6 ++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index 6141974e20..ed528b0bb9 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -48,6 +48,8 @@ struct FabulousImpl : ViaductAPI
         for (auto a : args) {
             if (a.first == "fasm")
                 fasm_file = a.second;
+            else if (a.first == "lut_k")
+                cfg.clb.lut_k = std::stoi(a.second);
             else
                 log_error("unrecognised fabulous option '%s'\n", a.first.c_str());
         }
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index f1c0c64858..0ec6f02d58 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -99,7 +99,7 @@ struct FabFasmWriter
     {
         std::vector<bool> bits(width, false);
         for (int i = 0; i < width; i++)
-            bits[i] = (value & (1ULL << i)) != 0;
+            bits[i] = (value & (1ULL << unsigned(i))) != 0;
         write_vector(name, bits, invert);
     }
     // Write an int vector param
@@ -124,7 +124,9 @@ struct FabFasmWriter
 
     uint64_t depermute_lut(const CellInfo *lut)
     {
-        uint64_t orig_init = int_or_default(lut->params, id_INIT, 0);
+        uint64_t orig_init = 0;
+        if (lut->params.count(id_INIT))
+            orig_init = lut->params.at(id_INIT).as_int64();
         std::vector<std::vector<unsigned>> phys_to_log;
         phys_to_log.resize(cfg.clb.lut_k);
         for (unsigned i = 0; i < cfg.clb.lut_k; i++) {

From 71192dc7a3b8dfae1f76f48412dd906bfb0783e7 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 14 Apr 2023 16:54:08 +1000
Subject: [PATCH 324/712] gowin: Remove inherited code for ODDR(c)

Implement ODDR(c) as part of IOLOGIC and remove all old code associated
with those primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc      |  79 ++++----------------------------
 gowin/arch.h       |   1 -
 gowin/constids.inc |   4 +-
 gowin/pack.cc      | 109 ++++++++++++---------------------------------
 4 files changed, 40 insertions(+), 153 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 0278cd8fb4..6756bf9f2d 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1416,7 +1416,6 @@ Arch::Arch(ArchArgs args) : args(args)
             IdString portname;
             int z = 0;
             bool dff = true;
-            bool oddrc = false;
             switch (static_cast<ConstIds>(bel->type_id)) {
             case ID_PLLVR:
                 belname = idf("R%dC%d_PLLVR", row + 1, col + 1);
@@ -1690,82 +1689,22 @@ Arch::Arch(ArchArgs args) : args(args)
                 break;
 
                 // IO logic
-            case ID_ODDRCB:
-                z++; /* fall-through*/
-            case ID_ODDRCA:
-                oddrc = true;
-                z++; /* fall-through*/
-            case ID_ODDRB:
-                z++; /* fall-through*/
-            case ID_ODDRA: {
-                snprintf(buf, 32, "R%dC%d_ODDR%s%c", row + 1, col + 1, oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
-                belname = id(buf);
-                addBel(belname, id_ODDR, Loc(col, row, BelZ::oddr_0_z + z), false);
-
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_D0)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_D0, id(buf));
-
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_D1)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_D1, id(buf));
-
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_TX)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_TX, id(buf));
-
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CLK)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_CLK, id(buf));
-
-                const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_LOW);
-                if (quirk_port != nullptr) {
-                    ddr_has_extra_inputs = true;
-                    portname = IdString(quirk_port->src_id);
-                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_ODDR_ALWAYS_LOW, id(buf));
-                }
-                quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_HIGH);
-                if (quirk_port != nullptr) {
-                    ddr_has_extra_inputs = true;
-                    portname = IdString(quirk_port->src_id);
-                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_ODDR_ALWAYS_HIGH, id(buf));
-                }
-
-                if (oddrc) {
-                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CE)->src_id);
-                    snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    addBelInput(belname, id_CE, id(buf));
-                }
-
-                // dummy wires
-                snprintf(buf, 32, "ODDR%s%c_Q0", oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
-                IdString id_q0 = id(buf);
-                IdString q0_name = wireToGlobal(row, col, db, id_q0);
-                if (wires.count(q0_name) == 0)
-                    addWire(q0_name, id_q0, row, col);
-                addBelOutput(belname, id_Q0, q0_name);
-
-                snprintf(buf, 32, "ODDR%s%c_Q1", oddrc ? "C" : "", 'A' + z - (oddrc ? 2 : 0));
-                IdString id_q1 = id(buf);
-                IdString q1_name = wireToGlobal(row, col, db, id_q1);
-                if (wires.count(q1_name) == 0)
-                    addWire(q1_name, id_q1, row, col);
-                addBelOutput(belname, id_Q1, q1_name);
-            } break;
             case ID_IOLOGICB:
                 z++; /* fall-through*/
             case ID_IOLOGICA: {
                 belname = idf("R%dC%d_IOLOGIC%c", row + 1, col + 1, 'A' + z);
                 addBel(belname, id_IOLOGIC, Loc(col, row, BelZ::iologic_z + z), false);
 
-                IdString const iologic_in_ports[] = {id_TX0, id_TX1, id_TX2, id_TX3, id_RESET, id_CALIB, id_PCLK,
-                                                     id_D,   id_D0,  id_D1,  id_D2,  id_D3,    id_D4,    id_D5,
-                                                     id_D6,  id_D7,  id_D8,  id_D9,  id_CLK,   id_CLEAR};
+                IdString const iologic_in_ports[] = {id_TX,    id_TX0,  id_TX1,   id_TX2,    id_TX3,   id_RESET,
+                                                     id_CALIB, id_PCLK, id_D,     id_D0,     id_D1,    id_D2,
+                                                     id_D3,    id_D4,   id_D5,    id_D6,     id_D7,    id_D8,
+                                                     id_D9,    id_CLK,  id_CLEAR, id_DAADJ0, id_DAADJ1};
                 for (IdString port : iologic_in_ports) {
-                    portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
-                    addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    const PairPOD *portid = pairLookup(bel->ports.get(), bel->num_ports, port.hash());
+                    if (portid != nullptr) {
+                        portname = IdString(portid->src_id);
+                        addBelInput(belname, port, idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this)));
+                    }
                 }
                 IdString const iologic_out_ports[] = {id_Q,  id_Q0, id_Q1, id_Q2, id_Q3, id_Q4,
                                                       id_Q5, id_Q6, id_Q7, id_Q8, id_Q9};
diff --git a/gowin/arch.h b/gowin/arch.h
index 23da366149..c3e1e7dd98 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -535,7 +535,6 @@ enum
     ioba_z = 0,      // IOBA
     iobb_z = 1,      // IOBB
     mux_0_z = 10,    // start Z for the MUX2LUT5 bels
-    oddr_0_z = 20,   // XXX start Z for the ODDR bels
     lutram_0_z = 30, // start Z for the LUTRAM bels
     vcc_0_z = 277,   // virtual VCC bel Z
     gnd_0_z = 278,   // virtual VSS bel Z
diff --git a/gowin/constids.inc b/gowin/constids.inc
index daedb8a66c..3a4b0dd244 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -767,8 +767,8 @@ X(TX3)
 X(FCLK)
 X(PCLK)
 X(CALIB)
-X(ODDR_ALWAYS_LOW)
-X(ODDR_ALWAYS_HIGH)
+X(DAADJ0)
+X(DAADJ1)
 X(GW9_ALWAYS_LOW0)
 X(GW9_ALWAYS_LOW1)
 X(GW9C_ALWAYS_LOW0)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 2ff42e55e9..c9ca635b41 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -903,79 +903,15 @@ static void pack_iologic(Context *ctx)
             CellInfo *q0_dst = nullptr;
             CellInfo *q1_dst = nullptr;
             switch (ci->type.hash()) {
-            case ID_ODDRC: /* fall-through*/
-            case ID_ODDR: {
-                q0_dst = net_only_drives(ctx, ci->ports.at(id_Q0).net, is_iob, id_I);
-                NPNR_ASSERT(q0_dst != nullptr);
-
-                auto iob_bel = q0_dst->attrs.find(id_BEL);
-                if (q0_dst->attrs.count(id_DIFF_TYPE)) {
-                    ci->attrs[id_OBUF_TYPE] = std::string("DBUF");
-                } else {
-                    ci->attrs[id_OBUF_TYPE] = std::string("SBUF");
-                }
-                if (iob_bel != q0_dst->attrs.end()) {
-                    // already know there to place, no need of any cluster stuff
-                    Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(iob_bel->second.as_string()));
-                    loc.z += BelZ::oddr_0_z;
-                    ci->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
-                } else {
-                    // make cluster from ODDR and OBUF
-                    ci->cluster = ci->name;
-                    ci->constr_x = 0;
-                    ci->constr_y = 0;
-                    ci->constr_z = 0;
-                    ci->constr_abs_z = false;
-                    ci->constr_children.push_back(q0_dst);
-                    q0_dst->cluster = ci->name;
-                    q0_dst->constr_x = 0;
-                    q0_dst->constr_y = 0;
-                    q0_dst->constr_z = -BelZ::oddr_0_z;
-                    q0_dst->constr_abs_z = false;
-                }
-
-                // disconnect Q0 output: it is wired internally
-                delete_nets.insert(ci->ports.at(id_Q0).net->name);
-                q0_dst->disconnectPort(id_I);
-                ci->disconnectPort(id_Q0);
-
-                ci->attrs[id_IOBUF] = 0;
-                // if Q1 is conected then disconnet it too
-                if (port_used(ci, id_Q1)) {
-                    q1_dst = net_only_drives(ctx, ci->ports.at(id_Q1).net, is_iob, id_OEN);
-                    if (q1_dst != nullptr) {
-                        delete_nets.insert(ci->ports.at(id_Q1).net->name);
-                        q0_dst->disconnectPort(id_OEN);
-                        ci->disconnectPort(id_Q1);
-                        ci->attrs[id_IOBUF] = 1;
-                    }
-                }
-                // if have XXX_ inputs connect them
-                if (ctx->ddr_has_extra_inputs) {
-                    ci->addInput(id_ODDR_ALWAYS_LOW);
-                    ci->connectPort(id_ODDR_ALWAYS_LOW, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
-                    ci->addInput(id_ODDR_ALWAYS_HIGH);
-                    ci->connectPort(id_ODDR_ALWAYS_HIGH, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
-                }
-                if (iob_bel != q0_dst->attrs.end()) {
-                    IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
-                    if (ctx->gw1n9_quirk && ctx->bels.at(io_bel_name).pins.count(id_GW9_ALWAYS_LOW0)) {
-                        q0_dst->disconnectPort(id_GW9_ALWAYS_LOW0);
-                        q0_dst->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
-                    }
-                    if (ctx->bels.at(io_bel_name).pins.count(id_GW9C_ALWAYS_LOW1)) {
-                        q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
-                        q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
-                    }
-                }
-            } break;
+            case ID_ODDR:   /* fall-through */
+            case ID_ODDRC:  /* fall-through */
             case ID_OSER4:  /* fall-through */
             case ID_OSER8:  /* fall-through */
             case ID_OSER10: /* fall-through */
             case ID_OVIDEO: {
                 IdString output = id_Q;
                 IdString output_1 = IdString();
-                if (ci->type == id_OSER4 || ci->type == id_OSER8) {
+                if (ci->type == id_ODDR || ci->type == id_ODDRC || ci->type == id_OSER4 || ci->type == id_OSER8) {
                     output = id_Q0;
                     output_1 = id_Q1;
                 }
@@ -999,6 +935,10 @@ static void pack_iologic(Context *ctx)
 
                 std::string out_mode;
                 switch (ci->type.hash()) {
+                case ID_ODDR:
+                case ID_ODDRC:
+                    out_mode = "ODDRX1";
+                    break;
                 case ID_OSER4:
                     out_mode = "ODDRX2";
                     break;
@@ -1025,12 +965,18 @@ static void pack_iologic(Context *ctx)
                 delete_nets.insert(ci->ports.at(output).net->name);
                 q0_dst->disconnectPort(id_I);
                 ci->disconnectPort(output);
-                bool have_XXX =
-                        ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
-                if (have_XXX) {
+                if (ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1)) {
                     q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
                     q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
                 }
+                if (ctx->bels.at(ctx->getBelByLocation(loc)).pins.count(id_DAADJ0)) {
+                    ci->addInput(id_DAADJ0);
+                    ci->connectPort(id_DAADJ0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                }
+                if (ctx->bels.at(ctx->getBelByLocation(loc)).pins.count(id_DAADJ1)) {
+                    ci->addInput(id_DAADJ1);
+                    ci->connectPort(id_DAADJ1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+                }
 
                 // if Q1 is connected then disconnet it too
                 if (output_1 != IdString() && port_used(ci, output_1)) {
@@ -1057,16 +1003,19 @@ static void pack_iologic(Context *ctx)
                 ci->setAttr(id_IOBUF, 0);
                 ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
 
-                if (ci->type == id_OSER4) {
-                    // two OSER4 share FCLK, check it
-                    Loc other_loc = loc;
-                    other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
-                    BelId other_bel = ctx->getBelByLocation(other_loc);
-                    CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
-                    if (other_cell != nullptr) {
-                        NPNR_ASSERT(other_cell->type == id_OSER4);
-                        if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
-                            log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci), ctx->nameOf(other_cell));
+                if (ci->type == id_OSER4 || ci->type == id_ODDR || ci->type == id_ODDRC) {
+                    if (ci->type == id_OSER4) {
+                        // two OSER4 share FCLK, check it
+                        Loc other_loc = loc;
+                        other_loc.z = 1 - loc.z + 2 * BelZ::iologic_z;
+                        BelId other_bel = ctx->getBelByLocation(other_loc);
+                        CellInfo *other_cell = ctx->getBoundBelCell(other_bel);
+                        if (other_cell != nullptr) {
+                            NPNR_ASSERT(other_cell->type == id_OSER4);
+                            if (ci->ports.at(id_FCLK).net != other_cell->ports.at(id_FCLK).net) {
+                                log_error("%s and %s have differnet FCLK nets\n", ctx->nameOf(ci),
+                                          ctx->nameOf(other_cell));
+                            }
                         }
                     }
                 } else {

From fdc2769259903f791db6f9d86fb0fdf8cbbe9bb6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 18 Apr 2023 20:10:36 +1000
Subject: [PATCH 325/712] gowin: add a common mechanism for placing ports

If the port is in a different cell than the primitive, then use the alias mechanism.
Considerably compact code for OSC as an example.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 86 ++++++++++++++++++++-------------------------------
 gowin/arch.h  |  2 ++
 2 files changed, 35 insertions(+), 53 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index 6756bf9f2d..cf2f7a85e9 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1258,6 +1258,28 @@ static bool skip_aux_oser16(std::string device, int row, int col)
     return false;
 }
 
+WireId Arch::get_make_port_wire(const DatabasePOD *db, const BelsPOD *bel, int row, int col, IdString port)
+{
+    IdString wirename = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
+    IdString wire = idf("R%dC%d_%s", row + 1, col + 1, wirename.c_str(this));
+    if (wires.count(wire) == 0) {
+        GlobalAliasPOD alias;
+        alias.dest_col = col;
+        alias.dest_row = row;
+        alias.dest_id = port.hash();
+        auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
+        NPNR_ASSERT(alias_src != nullptr);
+        int srcrow = alias_src->src_row;
+        int srccol = alias_src->src_col;
+        IdString srcid = IdString(alias_src->src_id);
+        wire = wireToGlobal(srcrow, srccol, db, srcid);
+        if (wires.count(wire) == 0) {
+            addWire(wire, srcid, srccol, srcrow);
+        }
+    }
+    return wire;
+}
+
 Arch::Arch(ArchArgs args) : args(args)
 {
     family = args.family;
@@ -1460,62 +1482,20 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_GSRI, id(buf));
                 break;
-            case ID_OSC:
-                snprintf(buf, 32, "R%dC%d_OSC", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSC, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
-                break;
-            case ID_OSCH:
-                snprintf(buf, 32, "R%dC%d_OSCH", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSCH, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
-                break;
-            case ID_OSCF:
-                snprintf(buf, 32, "R%dC%d_OSCF", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSCF, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_OSCEN, id(buf));
-                break;
-            case ID_OSCZ:
-                snprintf(buf, 32, "R%dC%d_OSCZ", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSCZ, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_OSCEN, id(buf));
-                break;
+            case ID_OSC:  /* fall-through*/
+            case ID_OSCH: /* fall-through*/
             case ID_OSCW:
-                snprintf(buf, 32, "R%dC%d_OSCW", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSCW, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
+                belname = idf("R%dC%d_%s", row + 1, col + 1, IdString(bel->type_id).c_str(this));
+                addBel(belname, IdString(bel->type_id), Loc(col, row, BelZ::osc_z), false);
+                addBelOutput(belname, id_OSCOUT, get_make_port_wire(db, bel, row, col, id_OSCOUT));
                 break;
+            case ID_OSCF: /* fall-through*/
+            case ID_OSCZ: /* fall-through*/
             case ID_OSCO:
-                snprintf(buf, 32, "R%dC%d_OSCO", row + 1, col + 1);
-                belname = id(buf);
-                addBel(belname, id_OSCO, Loc(col, row, BelZ::osc_z), false);
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCOUT)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelOutput(belname, id_OSCOUT, id(buf));
-                portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_OSCEN)->src_id);
-                snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                addBelInput(belname, id_OSCEN, id(buf));
+                belname = idf("R%dC%d_%s", row + 1, col + 1, IdString(bel->type_id).c_str(this));
+                addBel(belname, IdString(bel->type_id), Loc(col, row, BelZ::osc_z), false);
+                addBelOutput(belname, id_OSCOUT, get_make_port_wire(db, bel, row, col, id_OSCOUT));
+                addBelInput(belname, id_OSCEN, get_make_port_wire(db, bel, row, col, id_OSCEN));
                 break;
             case ID_RAM16:
                 snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
diff --git a/gowin/arch.h b/gowin/arch.h
index c3e1e7dd98..ff8905acbf 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -498,6 +498,8 @@ struct Arch : BaseArch<ArchRanges>
     void mark_used_hclk(Context *ctx);
     IdString apply_local_aliases(int row, int col, const DatabasePOD *db, IdString &wire);
 
+    WireId get_make_port_wire(const DatabasePOD *db, const BelsPOD *bel, int row, int col, IdString port);
+
     GowinGlobalRouter globals_router;
     void mark_gowin_globals(Context *ctx);
     void route_gowin_globals(Context *ctx);

From 729757d55ebea66e8c7995b9c2e0089ab53e4700 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 18 Apr 2023 21:12:16 +1000
Subject: [PATCH 326/712] gowin: fix style

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index cf2f7a85e9..a1230acf28 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -1273,7 +1273,7 @@ WireId Arch::get_make_port_wire(const DatabasePOD *db, const BelsPOD *bel, int r
         int srccol = alias_src->src_col;
         IdString srcid = IdString(alias_src->src_id);
         wire = wireToGlobal(srcrow, srccol, db, srcid);
-        if (wires.count(wire) == 0) {
+        if (!wires.count(wire)) {
             addWire(wire, srcid, srccol, srcrow);
         }
     }

From 051bdb12b3b695d74a829a231f3e3bf4d0a26323 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 18 Apr 2023 21:22:51 +1000
Subject: [PATCH 327/712] gowin: fix style

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/arch.cc | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/gowin/arch.cc b/gowin/arch.cc
index a1230acf28..4a50a2cb4f 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -353,7 +353,7 @@ NetInfo &Arch::net_info(IdString net)
 
 void Arch::addWire(IdString name, IdString type, int x, int y)
 {
-    NPNR_ASSERT(wires.count(name) == 0);
+    NPNR_ASSERT(!wires.count(name));
     WireInfo &wi = wires[name];
     wi.name = name;
     wi.type = type;
@@ -1114,7 +1114,7 @@ void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString b
           ID_DUTYDA2, ID_DUTYDA3, ID_FDLY0,   ID_FDLY1,   ID_FDLY2,   ID_FDLY3,   ID_RESET,   ID_RESET_P}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
         IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-        if (wires.count(wire) == 0) {
+        if (!wires.count(wire)) {
             GlobalAliasPOD alias;
             alias.dest_col = col;
             alias.dest_row = row;
@@ -1125,7 +1125,7 @@ void Arch::add_pllvr_ports(DatabasePOD const *db, BelsPOD const *bel, IdString b
             int srccol = alias_src->src_col;
             IdString srcid = IdString(alias_src->src_id);
             wire = wireToGlobal(srcrow, srccol, db, srcid);
-            if (wires.count(wire) == 0) {
+            if (!wires.count(wire)) {
                 addWire(wire, srcid, srccol, srcrow);
             }
         }
@@ -1155,7 +1155,7 @@ void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString be
         }
         portname = IdString(port->src_id);
         IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-        if (wires.count(wire) == 0) {
+        if (!wires.count(wire)) {
             GlobalAliasPOD alias;
             alias.dest_col = col;
             alias.dest_row = row;
@@ -1166,7 +1166,7 @@ void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString be
             int srccol = alias_src->src_col;
             IdString srcid = IdString(alias_src->src_id);
             wire = wireToGlobal(srcrow, srccol, db, srcid);
-            if (wires.count(wire) == 0) {
+            if (!wires.count(wire)) {
                 addWire(wire, srcid, srccol, srcrow);
             }
         }
@@ -1175,7 +1175,7 @@ void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString be
     for (int pid : {ID_LOCK, ID_CLKOUT, ID_CLKOUTP, ID_CLKOUTD, ID_CLKOUTD3}) {
         portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, pid)->src_id);
         IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-        if (wires.count(wire) == 0) {
+        if (!wires.count(wire)) {
             GlobalAliasPOD alias;
             alias.dest_col = col;
             alias.dest_row = row;
@@ -1186,7 +1186,7 @@ void Arch::add_rpll_ports(DatabasePOD const *db, BelsPOD const *bel, IdString be
             int srccol = alias_src->src_col;
             IdString srcid = IdString(alias_src->src_id);
             wire = wireToGlobal(srcrow, srccol, db, srcid);
-            if (wires.count(wire) == 0) {
+            if (!wires.count(wire)) {
                 addWire(wire, srcid, srccol, srcrow);
             }
         }
@@ -1262,7 +1262,7 @@ WireId Arch::get_make_port_wire(const DatabasePOD *db, const BelsPOD *bel, int r
 {
     IdString wirename = IdString(pairLookup(bel->ports.get(), bel->num_ports, port.hash())->src_id);
     IdString wire = idf("R%dC%d_%s", row + 1, col + 1, wirename.c_str(this));
-    if (wires.count(wire) == 0) {
+    if (!wires.count(wire)) {
         GlobalAliasPOD alias;
         alias.dest_col = col;
         alias.dest_row = row;
@@ -1422,13 +1422,13 @@ Arch::Arch(ArchArgs args) : args(args)
                 int destcol = col;
                 IdString destid(pip.dest_id), gdestid(pip.dest_id);
                 IdString gdestname = wireToGlobal(destrow, destcol, db, gdestid);
-                if (wires.count(gdestname) == 0)
+                if (!wires.count(gdestname))
                     addWire(gdestname, destid, destcol, destrow);
                 int srcrow = row;
                 int srccol = col;
                 IdString srcid(pip.src_id), gsrcid(pip.src_id);
                 IdString gsrcname = wireToGlobal(srcrow, srccol, db, gsrcid);
-                if (wires.count(gsrcname) == 0)
+                if (!wires.count(gsrcname))
                     addWire(gsrcname, srcid, srccol, srcrow);
             }
         }
@@ -1697,7 +1697,7 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (fclk != nullptr) {
                     portname = IdString(fclk->src_id);
                     IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    if (wires.count(wire) == 0) {
+                    if (!wires.count(wire)) {
                         GlobalAliasPOD alias;
                         alias.dest_col = col;
                         alias.dest_row = row;
@@ -1708,7 +1708,7 @@ Arch::Arch(ArchArgs args) : args(args)
                             int srccol = alias_src->src_col;
                             IdString srcid = IdString(alias_src->src_id);
                             wire = wireToGlobal(srcrow, srccol, db, srcid);
-                            if (wires.count(wire) == 0) {
+                            if (!wires.count(wire)) {
                                 addWire(wire, srcid, srccol, srcrow);
                             }
                             addBelInput(belname, id_FCLK, wire);
@@ -1749,7 +1749,7 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (fclk != nullptr) {
                     portname = IdString(fclk->src_id);
                     IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    if (wires.count(wire) == 0) {
+                    if (!wires.count(wire)) {
                         GlobalAliasPOD alias;
                         alias.dest_col = col;
                         alias.dest_row = row;
@@ -1760,7 +1760,7 @@ Arch::Arch(ArchArgs args) : args(args)
                             int srccol = alias_src->src_col;
                             IdString srcid = IdString(alias_src->src_id);
                             wire = wireToGlobal(srcrow, srccol, db, srcid);
-                            if (wires.count(wire) == 0) {
+                            if (!wires.count(wire)) {
                                 addWire(wire, srcid, srccol, srcrow);
                             }
                             addBelInput(belname, id_FCLK, wire);
@@ -1793,7 +1793,7 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (fclk != nullptr) {
                     portname = IdString(fclk->src_id);
                     IdString wire = idf("R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
-                    if (wires.count(wire) == 0) {
+                    if (!wires.count(wire)) {
                         GlobalAliasPOD alias;
                         alias.dest_col = col;
                         alias.dest_row = row;
@@ -1804,7 +1804,7 @@ Arch::Arch(ArchArgs args) : args(args)
                             int srccol = alias_src->src_col;
                             IdString srcid = IdString(alias_src->src_id);
                             wire = wireToGlobal(srcrow, srccol, db, srcid);
-                            if (wires.count(wire) == 0) {
+                            if (!wires.count(wire)) {
                                 addWire(wire, srcid, srccol, srcrow);
                             }
                             addBelInput(belname, id_FCLK, wire);

From 80705e9bbba4028077ae9abfdb86ba6b4b06a5eb Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 Mar 2023 17:34:52 +0100
Subject: [PATCH 328/712] Support enabling XO3 and XO3D

---
 machxo2/CMakeLists.txt   | 10 +++++-----
 machxo2/facade_import.py | 22 ++++++++++++++++++++--
 machxo2/family.cmake     |  2 +-
 3 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/machxo2/CMakeLists.txt b/machxo2/CMakeLists.txt
index 414c6571ca..7cfe5b33bb 100644
--- a/machxo2/CMakeLists.txt
+++ b/machxo2/CMakeLists.txt
@@ -1,10 +1,10 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-machxo2 NONE)
 
-set(ALL_MACHXO2_DEVICES 256X 640X 1200X 2280X 256 640 1200 2000 4000 7000)
-set(MACHXO2_DEVICES 1200 CACHE STRING
-    "Include support for these MachXO2 devices (available: ${ALL_MACHXO2_DEVICES})")
-message(STATUS "Enabled MachXO2 devices: ${MACHXO2_DEVICES}")
+set(ALL_MACHXO2_DEVICES 256X 640X 1200X 2280X 256 640 1200 2000 4000 7000 1300 2100 4300 6900 9400 4300D 9400D)
+set(MACHXO2_DEVICES 1200 6900 CACHE STRING
+    "Include support for these MachXO2/XO3 devices (available: ${ALL_MACHXO2_DEVICES})")
+message(STATUS "Enabled MachXO2/XO3 devices: ${MACHXO2_DEVICES}")
 
 if(DEFINED MACHXO2_CHIPDB)
     add_custom_target(chipdb-machxo2-bbas ALL)
@@ -51,7 +51,7 @@ else()
     file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
     foreach(device ${MACHXO2_DEVICES})
         if(NOT device IN_LIST ALL_MACHXO2_DEVICES)
-            message(FATAL_ERROR "Device ${device} is not a supported MachXO2 device")
+            message(FATAL_ERROR "Device ${device} is not a supported MachXO2/XO3 device")
         endif()
 
         set(device_bba chipdb/chipdb-${device}.bba)
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index fdb0f72318..9d0b5ed98b 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -422,7 +422,16 @@ def get_wire_name(loc, idx):
     "1200": "MachXO2",
     "2000": "MachXO2",
     "4000": "MachXO2",
-    "7000": "MachXO2"
+    "7000": "MachXO2",
+
+    "1300": "MachXO3",
+    "2100": "MachXO3",
+    "4300": "MachXO3",
+    "6900": "MachXO3",
+    "9400": "MachXO3",
+
+    "4300D": "MachXO3D",
+    "9400D": "MachXO3D"
 }
 
 dev_names = {
@@ -436,7 +445,16 @@ def get_wire_name(loc, idx):
     "1200": "LCMXO2-1200",
     "2000": "LCMXO2-2000",
     "4000": "LCMXO2-4000",
-    "7000": "LCMXO2-7000"
+    "7000": "LCMXO2-7000",
+
+    "1300": "LCMXO3-1300",
+    "2100": "LCMXO3-2100",
+    "4300": "LCMXO3-4300",
+    "6900": "LCMXO3-6900",
+    "9400": "LCMXO3-9400",
+
+    "4300D": "LCMXO3D-4300",
+    "9400D": "LCMXO3D-9400"
 }
 
 def main():
diff --git a/machxo2/family.cmake b/machxo2/family.cmake
index 604c91f396..30fd42ba12 100644
--- a/machxo2/family.cmake
+++ b/machxo2/family.cmake
@@ -1,5 +1,5 @@
 add_subdirectory(${family})
-message(STATUS "Using MachXO2 chipdb: ${MACHXO2_CHIPDB}")
+message(STATUS "Using MachXO2/XO3 chipdb: ${MACHXO2_CHIPDB}")
 
 set(chipdb_sources)
 set(chipdb_binaries)

From 89c71bc8acca8ddaed01b9bfcd0aca5dea680881 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 16 Mar 2023 17:52:59 +0100
Subject: [PATCH 329/712] bitstream fixes for xo3

---
 machxo2/bitstream.cc | 53 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 5b0e8664b5..09c9381101 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -32,13 +32,58 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace BaseConfigs {
 void config_empty_lcmxo2_1200(ChipConfig &cc)
 {
+    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_6900(ChipConfig &cc)
+{
+    cc.tiles["CENTER20:CENTER_EBR_CIB_SP"].add_unknown(23, 1);
+
+    cc.tiles["CIB_R20C36:CIB_EBR0"].add_unknown(26, 30);
+
+    cc.tiles["CIB_R20C40:CIB_EBR1"].add_unknown(26, 30);
+
+    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PR16:PIC_R1"].add_unknown(16, 52);
 
     cc.tiles["PT4:CFG0"].add_unknown(5, 30);
     cc.tiles["PT4:CFG0"].add_unknown(5, 32);
@@ -204,6 +249,8 @@ void write_bitstream(Context *ctx, std::string text_config_file)
     // IdString device_id = ctx->id(ctx->device_name);
     if (base_id == ctx->id("LCMXO2-1200"))
         BaseConfigs::config_empty_lcmxo2_1200(cc);
+    else if (base_id == ctx->id("LCMXO3-6900"))
+        BaseConfigs::config_empty_lcmxo3_6900(cc);
     else
         NPNR_ASSERT_FALSE("Unsupported device type");
     cc.chip_name = ctx->chip_info->device_name.get();

From b033b915a6dd1d7b445ede62890e570da3144c84 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 16 Mar 2023 17:54:26 +0100
Subject: [PATCH 330/712] Add bitgen for the rest of XO2 and XO3

---
 machxo2/bitstream.cc | 246 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 241 insertions(+), 5 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 09c9381101..c67408ddbf 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -30,6 +30,27 @@ NEXTPNR_NAMESPACE_BEGIN
 
 // These seem simple enough to do inline for now.
 namespace BaseConfigs {
+void config_empty_lcmxo2_256(ChipConfig &cc)
+{
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
+
+    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_640(ChipConfig &cc)
+{
+    cc.tiles["EBR_R0C14:EBR1_640"].add_unknown(0, 12);
+    cc.tiles["EBR_R0C17:EBR1_640"].add_unknown(0, 12);
+
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
+
+    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
+}
+
 void config_empty_lcmxo2_1200(ChipConfig &cc)
 {
     cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
@@ -47,13 +68,144 @@ void config_empty_lcmxo2_1200(ChipConfig &cc)
     cc.tiles["PT7:CFG3"].add_unknown(5, 18);
 }
 
+void config_empty_lcmxo2_2000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_4000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_7000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_1300(ChipConfig &cc)
+{
+    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_2100(ChipConfig &cc)
+{
+    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_4300(ChipConfig &cc)
+{
+    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
 void config_empty_lcmxo3_6900(ChipConfig &cc)
 {
+    // TODO: This block is probably clock routing
     cc.tiles["CENTER20:CENTER_EBR_CIB_SP"].add_unknown(23, 1);
-
     cc.tiles["CIB_R20C36:CIB_EBR0"].add_unknown(26, 30);
-
     cc.tiles["CIB_R20C40:CIB_EBR1"].add_unknown(26, 30);
+    cc.tiles["PR16:PIC_R1"].add_unknown(16, 52);
 
     cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
@@ -83,7 +235,65 @@ void config_empty_lcmxo3_6900(ChipConfig &cc)
     cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
 
-    cc.tiles["PR16:PIC_R1"].add_unknown(16, 52);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_9400(ChipConfig &cc)
+{
+    cc.tiles["EBR_R15C2:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C5:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C8:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C11:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C14:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C17:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C20:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C23:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C27:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C30:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C33:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C36:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C39:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C42:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C45:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C48:EBR1_10K"].add_unknown(0, 12);
+   
+    cc.tiles["EBR_R8C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C20:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C23:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C27:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C30:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C33:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C36:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C39:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C42:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C45:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C48:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R22C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C20:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C23:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C27:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C30:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C33:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C36:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C39:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C42:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C45:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C48:EBR1"].add_unknown(0, 12);
 
     cc.tiles["PT4:CFG0"].add_unknown(5, 30);
     cc.tiles["PT4:CFG0"].add_unknown(5, 32);
@@ -246,11 +456,28 @@ void write_bitstream(Context *ctx, std::string text_config_file)
 {
     ChipConfig cc;
     IdString base_id = ctx->id(ctx->chip_info->device_name.get());
-    // IdString device_id = ctx->id(ctx->device_name);
-    if (base_id == ctx->id("LCMXO2-1200"))
+    if (base_id == ctx->id("LCMXO2-256"))
+        BaseConfigs::config_empty_lcmxo2_256(cc);
+    else if (base_id == ctx->id("LCMXO2-640"))
+        BaseConfigs::config_empty_lcmxo2_640(cc);
+    else if (base_id == ctx->id("LCMXO2-1200"))
         BaseConfigs::config_empty_lcmxo2_1200(cc);
+    else if (base_id == ctx->id("LCMXO2-2000"))
+        BaseConfigs::config_empty_lcmxo2_2000(cc);
+    else if (base_id == ctx->id("LCMXO2-4000"))
+        BaseConfigs::config_empty_lcmxo2_4000(cc);
+    else if (base_id == ctx->id("LCMXO2-7000"))
+        BaseConfigs::config_empty_lcmxo2_7000(cc);
+    else if (base_id == ctx->id("LCMXO3-1300"))
+        BaseConfigs::config_empty_lcmxo3_1300(cc);
+    else if (base_id == ctx->id("LCMXO3-2100"))
+        BaseConfigs::config_empty_lcmxo3_2100(cc);
+    else if (base_id == ctx->id("LCMXO3-4300") || base_id == ctx->id("LCMXO3D-4300"))
+        BaseConfigs::config_empty_lcmxo3_4300(cc);
     else if (base_id == ctx->id("LCMXO3-6900"))
         BaseConfigs::config_empty_lcmxo3_6900(cc);
+    else if (base_id == ctx->id("LCMXO3-9400") || base_id == ctx->id("LCMXO3D-9400"))
+        BaseConfigs::config_empty_lcmxo3_9400(cc);
     else
         NPNR_ASSERT_FALSE("Unsupported device type");
     cc.chip_name = ctx->chip_info->device_name.get();
@@ -258,6 +485,15 @@ void write_bitstream(Context *ctx, std::string text_config_file)
 
     cc.metadata.push_back("Part: " + ctx->getChipName());
 
+    if (cc.chip_variant.find("LCMXO3L-") != std::string::npos) {
+        // XO3L have this set but not XO3LF
+        cc.tiles["PT5:CFG1"].add_unknown(5, 36);
+    }
+    if (cc.chip_variant.find("LCMXO3D-") != std::string::npos) {
+        cc.tiles["PT5:CFG1"].add_unknown(5, 36);
+        cc.tiles["PT6:CFG2"].add_unknown(5, 37);
+    }
+
     // Add all set, configurable pips to the config
     for (auto pip : ctx->getPips()) {
         if (ctx->getBoundPipNet(pip) != nullptr) {

From 235a5752675db4949b16f555d4fba2730fb5c48a Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 27 Mar 2023 18:40:55 +0100
Subject: [PATCH 331/712] port ecp5 split slice to machxo2

---
 machxo2/arch.cc          |   20 +-
 machxo2/arch.h           |   43 ++
 machxo2/archdefs.h       |   51 ++
 machxo2/cells.cc         |  303 +++++++--
 machxo2/cells.h          |   16 +-
 machxo2/constids.inc     |   31 +
 machxo2/facade_import.py |    2 +-
 machxo2/pack.cc          | 1334 +++++++++++++++++++++++++++++++-------
 8 files changed, 1492 insertions(+), 308 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 022fb8ffb7..32b188e652 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -95,6 +95,20 @@ Arch::Arch(ArchArgs args) : args(args)
     if (!package_info)
         log_error("Unsupported package '%s' for '%s'.\n", package_name, getChipName().c_str());
 
+    tile_status.resize(chip_info->num_tiles);
+    for (int i = 0; i < chip_info->num_tiles; i++) {
+        auto &ts = tile_status.at(i);
+        auto &tile_data = chip_info->tile_info[i];
+        ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr);
+        for (auto &name : tile_data.tile_names) {
+            if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) {
+                // Is a logic tile
+                ts.lts = new LogicTileStatus();
+                break;
+            }
+        }
+    }
+
     BaseArch::init_cell_types();
     BaseArch::init_bel_buckets();
 
@@ -470,12 +484,6 @@ DecalXY Arch::getPipDecal(PipId pip) const
 
 // ---------------------------------------------------------------
 
-bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
-{
-    // FIXME: Same deal as isValidBelForCell.
-    return true;
-}
-
 const std::string Arch::defaultPlacer = "heap";
 
 const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 8cb8accc93..1eab9d1f96 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -381,6 +381,38 @@ struct Arch : BaseArch<ArchRanges>
     // inverse of the above for name->object mapping
     dict<IdString, int> id_to_x, id_to_y;
 
+    enum LogicBELType
+    {
+        BEL_COMB = 0,
+        BEL_FF = 1,
+        BEL_RAMW = 2
+    };
+    static const int lc_idx_shift = 2;
+
+    struct LogicTileStatus
+    {
+        // Per-SLICE valid and dirty bits
+        struct SliceStatus
+        {
+            bool valid = true, dirty = true;
+        } slices[4];
+        // Per-tile legality check for control set legality
+        bool tile_valid = true;
+        bool tile_dirty = true;
+        // Fast index from z-pos to cell
+        std::array<CellInfo *, 8 * (1 << lc_idx_shift)> cells;
+    };
+
+    struct TileStatus
+    {
+        std::vector<CellInfo *> boundcells;
+        LogicTileStatus *lts = nullptr;
+        // TODO: use similar mechanism for DSP legality checking
+        ~TileStatus() { delete lts; }
+    };
+
+    mutable std::vector<TileStatus> tile_status;
+
     // Helpers
     template <typename Id> const TileTypePOD *tile_info(Id &id) const
     {
@@ -392,6 +424,11 @@ struct Arch : BaseArch<ArchRanges>
         return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
     }
 
+    template <typename Id> inline int tile_index(Id id) const
+    {
+        return id.location.y * chip_info->width + id.location.x;
+    }
+
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
 
@@ -624,6 +661,12 @@ struct Arch : BaseArch<ArchRanges>
     // Placer
     bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
+    // Helper function for above
+    bool slices_compatible(LogicTileStatus *lts) const;
+
+    void assign_arch_info_for_cell(CellInfo *ci);
+    void assignArchInfo() override;
+
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
     static const std::string defaultRouter;
diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
index 1520f0c33d..4809324a4f 100644
--- a/machxo2/archdefs.h
+++ b/machxo2/archdefs.h
@@ -143,6 +143,57 @@ struct NetInfo;
 
 struct ArchCellInfo : BaseClusterInfo
 {
+    enum CombFlags : uint8_t
+    {
+        COMB_NONE = 0x00,
+        COMB_CARRY = 0x01,
+        COMB_LUTRAM = 0x02,
+        COMB_MUX5 = 0x04,
+        COMB_MUX6 = 0x08,
+        COMB_RAM_WCKINV = 0x10,
+        COMB_RAM_WREINV = 0x20,
+        COMB_RAMW_BLOCK = 0x40,
+    };
+
+    enum FFFlags : uint8_t
+    {
+        FF_NONE = 0x00,
+        FF_CLKINV = 0x01,
+        FF_CEINV = 0x02,
+        FF_CECONST = 0x04,
+        FF_LSRINV = 0x08,
+        FF_GSREN = 0x10,
+        FF_ASYNC = 0x20,
+        FF_M_USED = 0x40,
+    };
+
+    struct
+    {
+        uint8_t flags;
+        IdString ram_wck, ram_wre;
+        CellInfo *mux_fxad;
+    } combInfo;
+    struct
+    {
+        uint8_t flags;
+        IdString clk_sig, lsr_sig, ce_sig, di_sig;
+    } ffInfo;
+    struct
+    {
+        bool is_pdp;
+        // Are the outputs from a DP16KD registered (OUTREG)
+        // or non-registered (NOREG)
+        bool is_output_a_registered;
+        bool is_output_b_registered;
+        // Which timing information to use for a DP16KD. Depends on registering
+        // configuration.
+        IdString regmode_timing_id;
+    } ramInfo;
+    struct
+    {
+        bool is_clocked;
+        IdString timing_id;
+    } multInfo;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index 5f277d17a4..edd9f816d0 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -32,51 +32,28 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
             name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
     auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
 
-    if (type == id_TRELLIS_SLICE) {
+    if (type == id_TRELLIS_COMB) {
         new_cell->params[id_MODE] = std::string("LOGIC");
-        new_cell->params[id_GSR] = std::string("ENABLED");
-        new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
-        new_cell->params[id_CEMUX] = std::string("1");
-        new_cell->params[id_CLKMUX] = std::string("0");
-        new_cell->params[id_LSRMUX] = std::string("LSR");
-        new_cell->params[id_LSRONMUX] = std::string("LSRMUX");
-        new_cell->params[id_LUT0_INITVAL] = Property(0xFFFF, 16);
-        new_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
-        new_cell->params[id_REGMODE] = std::string("FF");
-        new_cell->params[id_REG0_SD] = std::string("1");
-        new_cell->params[id_REG1_SD] = std::string("1");
-        new_cell->params[id_REG0_REGSET] = std::string("SET");
-        new_cell->params[id_REG1_REGSET] = std::string("SET");
-        new_cell->params[id_CCU2_INJECT1_0] = std::string("YES");
-        new_cell->params[id_CCU2_INJECT1_1] = std::string("YES");
-        new_cell->params[id_WREMUX] = std::string("INV");
+        new_cell->params[id_INITVAL] = Property(0, 16);
+        new_cell->params[id_CCU2_INJECT1] = std::string("NO");
+        new_cell->params[id_WREMUX] = std::string("WRE");
 
-        new_cell->addInput(id_A0);
-        new_cell->addInput(id_B0);
-        new_cell->addInput(id_C0);
-        new_cell->addInput(id_D0);
-
-        new_cell->addInput(id_A1);
-        new_cell->addInput(id_B1);
-        new_cell->addInput(id_C1);
-        new_cell->addInput(id_D1);
+        new_cell->addInput(id_A);
+        new_cell->addInput(id_B);
+        new_cell->addInput(id_C);
+        new_cell->addInput(id_D);
 
-        new_cell->addInput(id_M0);
-        new_cell->addInput(id_M1);
+        new_cell->addInput(id_M);
 
+        new_cell->addInput(id_F1);
         new_cell->addInput(id_FCI);
         new_cell->addInput(id_FXA);
         new_cell->addInput(id_FXB);
 
-        new_cell->addInput(id_CLK);
-        new_cell->addInput(id_LSR);
-        new_cell->addInput(id_CE);
-
         new_cell->addInput(id_DI0);
         new_cell->addInput(id_DI1);
 
-        new_cell->addInput(id_WD0);
-        new_cell->addInput(id_WD1);
+        new_cell->addInput(id_WD);
         new_cell->addInput(id_WAD0);
         new_cell->addInput(id_WAD1);
         new_cell->addInput(id_WAD2);
@@ -84,31 +61,29 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_WRE);
         new_cell->addInput(id_WCK);
 
-        new_cell->addOutput(id_F0);
-        new_cell->addOutput(id_Q0);
-        new_cell->addOutput(id_F1);
-        new_cell->addOutput(id_Q1);
+        new_cell->addOutput(id_F);
 
         new_cell->addOutput(id_FCO);
-        new_cell->addOutput(id_OFX0);
-        new_cell->addOutput(id_OFX1);
-
-        new_cell->addOutput(id_WDO0);
-        new_cell->addOutput(id_WDO1);
-        new_cell->addOutput(id_WDO2);
-        new_cell->addOutput(id_WDO3);
-        new_cell->addOutput(id_WADO0);
-        new_cell->addOutput(id_WADO1);
-        new_cell->addOutput(id_WADO2);
-        new_cell->addOutput(id_WADO3);
+        new_cell->addOutput(id_OFX);
+    } else if (type == id_TRELLIS_RAMW) {
+        for (auto i : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1})
+            new_cell->addInput(i);
+        for (auto o : {id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3})
+            new_cell->addOutput(o);
     } else if (type == id_TRELLIS_IO) {
         new_cell->params[id_DIR] = std::string("INPUT");
         new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
+        new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO");
+        new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO");
 
         new_cell->addInout(id_B);
         new_cell->addInput(id_I);
-        new_cell->addInput(id_EN);
+        new_cell->addInput(id_T);
         new_cell->addOutput(id_O);
+
+        new_cell->addInput(id_IOLDO);
+        new_cell->addInput(id_IOLTO);
+
     } else if (type == id_LUT4) {
         new_cell->params[id_INIT] = Property(0, 16);
 
@@ -117,6 +92,27 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_C);
         new_cell->addInput(id_D);
         new_cell->addOutput(id_Z);
+    } else if (type == id_CCU2C) {
+        new_cell->params[id_INIT0] = Property(0, 16);
+        new_cell->params[id_INIT1] = Property(0, 16);
+        new_cell->params[id_INJECT1_0] = std::string("YES");
+        new_cell->params[id_INJECT1_1] = std::string("YES");
+
+        new_cell->addInput(id_CIN);
+
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addOutput(id_S0);
+        new_cell->addOutput(id_S1);
+        new_cell->addOutput(id_COUT);
     } else {
         log_error("unable to create MachXO2 cell of type %s", type.c_str(ctx));
     }
@@ -124,6 +120,135 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
     return new_cell;
 }
 
+static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
+{
+    auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
+    NPNR_ASSERT(!init_prop.is_string);
+    const std::string &idata = init_prop.str;
+    NPNR_ASSERT(idata.length() == 64);
+    unsigned value = 0;
+    for (int i = 0; i < 16; i++) {
+        char c = idata.at(4 * i + bit);
+        if (c == '1')
+            value |= (1 << i);
+        else
+            NPNR_ASSERT(c == '0' || c == 'x');
+    }
+    return value;
+}
+
+void lut_to_comb(Context *ctx, CellInfo *lut)
+{
+    lut->type = id_TRELLIS_COMB;
+    lut->params[id_INITVAL] = get_or_default(lut->params, id_INIT, Property(0, 16));
+    lut->params.erase(id_INIT);
+    lut->renamePort(id_Z, id_F);
+}
+
+void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
+{
+    if (ramw->hierpath == IdString())
+        ramw->hierpath = ramw->hierpath;
+    ram->movePortTo(ctx->id("WAD[0]"), ramw, id_D0);
+    ram->movePortTo(ctx->id("WAD[1]"), ramw, id_B0);
+    ram->movePortTo(ctx->id("WAD[2]"), ramw, id_C0);
+    ram->movePortTo(ctx->id("WAD[3]"), ramw, id_A0);
+
+    ram->movePortTo(ctx->id("DI[0]"), ramw, id_C1);
+    ram->movePortTo(ctx->id("DI[1]"), ramw, id_A1);
+    ram->movePortTo(ctx->id("DI[2]"), ramw, id_D1);
+    ram->movePortTo(ctx->id("DI[3]"), ramw, id_B1);
+}
+
+void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i)
+{
+    std::string ii = std::to_string(i);
+    if (comb->hierpath == IdString())
+        comb->hierpath = ccu->hierpath;
+
+    comb->params[id_MODE] = std::string("CCU2");
+    comb->params[id_INITVAL] = get_or_default(ccu->params, ctx->id("INIT" + ii), Property(0, 16));
+    comb->params[id_CCU2_INJECT1] = str_or_default(ccu->params, ctx->id("INJECT1_" + ii), "YES");
+
+    ccu->movePortTo(ctx->id("A" + ii), comb, id_A);
+    ccu->movePortTo(ctx->id("B" + ii), comb, id_B);
+    ccu->movePortTo(ctx->id("C" + ii), comb, id_C);
+    ccu->movePortTo(ctx->id("D" + ii), comb, id_D);
+
+    ccu->movePortTo(ctx->id("S" + ii), comb, id_F);
+
+    if (i == 0) {
+        ccu->movePortTo(id_CIN, comb, id_FCI);
+        comb->connectPort(id_FCO, internal_carry);
+    } else if (i == 1) {
+        comb->connectPort(id_FCI, internal_carry);
+        ccu->movePortTo(id_COUT, comb, id_FCO);
+    } else {
+        NPNR_ASSERT_FALSE("bad carry index!");
+    }
+
+    for (auto &attr : ccu->attrs)
+        comb->attrs[attr.first] = attr.second;
+}
+
+void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index)
+{
+    if (comb->hierpath == IdString())
+        comb->hierpath = ram->hierpath;
+    comb->params[id_MODE] = std::string("DPRAM");
+    comb->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
+    comb->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
+
+    unsigned permuted_init = 0;
+    unsigned init = get_dram_init(ctx, ram, index);
+
+    for (int i = 0; i < 16; i++) {
+        int permuted_addr = 0;
+        if (i & 1)
+            permuted_addr |= 8;
+        if (i & 2)
+            permuted_addr |= 2;
+        if (i & 4)
+            permuted_addr |= 4;
+        if (i & 8)
+            permuted_addr |= 1;
+        if (init & (1 << permuted_addr))
+            permuted_init |= (1 << i);
+    }
+
+    comb->params[ctx->id("INITVAL")] = Property(permuted_init, 16);
+
+    if (ram->ports.count(ctx->id("RAD[0]")))
+        comb->connectPort(id_D, ram->ports.at(ctx->id("RAD[0]")).net);
+
+    if (ram->ports.count(ctx->id("RAD[1]")))
+        comb->connectPort(id_B, ram->ports.at(ctx->id("RAD[1]")).net);
+
+    if (ram->ports.count(ctx->id("RAD[2]")))
+        comb->connectPort(id_C, ram->ports.at(ctx->id("RAD[2]")).net);
+
+    if (ram->ports.count(ctx->id("RAD[3]")))
+        comb->connectPort(id_A, ram->ports.at(ctx->id("RAD[3]")).net);
+
+    if (ram->ports.count(id_WRE))
+        comb->connectPort(id_WRE, ram->ports.at(id_WRE).net);
+    if (ram->ports.count(id_WCK))
+        comb->connectPort(id_WCK, ram->ports.at(id_WCK).net);
+
+    ramw->connectPorts(id_WADO0, comb, id_WAD0);
+    ramw->connectPorts(id_WADO1, comb, id_WAD1);
+    ramw->connectPorts(id_WADO2, comb, id_WAD2);
+    ramw->connectPorts(id_WADO3, comb, id_WAD3);
+
+    NPNR_ASSERT(index < 4);
+    std::string ii = std::to_string(index);
+    ramw->connectPorts(ctx->id("WDO" + ii), comb, id_WD);
+    ram->movePortTo(ctx->id("DO[" + ii + "]"), comb, id_F);
+
+    for (auto &attr : ram->attrs)
+        comb->attrs[attr.first] = attr.second;
+}
+
 void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 {
     lc->params[id_LUT0_INITVAL] = lut->params[id_INIT];
@@ -165,6 +290,82 @@ void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
     }
 }
 
-void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells) {}
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+                pool<IdString> &todelete_cells)
+{
+    if (nxio->type == ctx->id("$nextpnr_ibuf")) {
+        trio->params[id_DIR] = std::string("INPUT");
+        nxio->movePortTo(id_O, trio, id_O);
+    } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
+        trio->params[id_DIR] = std::string("OUTPUT");
+        nxio->movePortTo(id_I, trio, id_I);
+    } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
+        // N.B. tristate will be dealt with below
+        NetInfo *i = nxio->getPort(id_I);
+        if (i == nullptr || i->driver.cell == nullptr)
+            trio->params[id_DIR] = std::string("INPUT");
+        else {
+            log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+            trio->params[id_DIR] = std::string("BIDIR");
+        }
+        nxio->movePortTo(id_I, trio, id_I);
+        nxio->movePortTo(id_O, trio, id_O);
+    } else {
+        NPNR_ASSERT(false);
+    }
+    NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net;
+
+    // Rename I/O nets to avoid conflicts
+    if (donet != nullptr && donet->name == nxio->name)
+        if (donet)
+            ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT"));
+    if (dinet != nullptr && dinet->name == nxio->name)
+        if (dinet)
+            ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
+
+    if (ctx->nets.count(nxio->name)) {
+        int i = 0;
+        IdString new_name;
+        do {
+            new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
+        } while (ctx->nets.count(new_name));
+        if (ctx->nets.at(nxio->name).get())
+            ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name);
+    }
+
+    // Create a new top port net for accurate IO timing analysis and simulation netlists
+    if (ctx->ports.count(nxio->name)) {
+        IdString tn_netname = nxio->name;
+        NPNR_ASSERT(!ctx->nets.count(tn_netname));
+        ctx->net_aliases.erase(tn_netname);
+        NetInfo *toplevel_net = ctx->createNet(tn_netname);
+        toplevel_net->name = tn_netname;
+        trio->connectPort(id_B, toplevel_net);
+        ctx->ports[nxio->name].net = toplevel_net;
+    }
+
+    CellInfo *tbuf = net_driven_by(
+            ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
+            id_Y);
+    if (tbuf) {
+        tbuf->movePortTo(id_A, trio, id_I);
+        // Need to invert E to form T
+        std::unique_ptr<CellInfo> inv_lut = create_machxo2_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
+        tbuf->movePortTo(id_E, inv_lut.get(), id_A);
+        inv_lut->params[id_INIT] = Property(21845, 16);
+        inv_lut->connectPorts(id_Z, trio, id_T);
+        created_cells.push_back(std::move(inv_lut));
+
+        if (donet->users.entries() > 1) {
+            for (auto user : donet->users)
+                log_info("     remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
+            log_error("unsupported tristate IO pattern for IO buffer '%s', "
+                      "instantiate SB_IO manually to ensure correct behaviour\n",
+                      nxio->name.c_str(ctx));
+        }
+        ctx->nets.erase(donet->name);
+        todelete_cells.insert(tbuf->name);
+    }
+}
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/cells.h b/machxo2/cells.h
index 753d7f119c..cc64b52e2e 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -41,12 +41,13 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
 
 // Return true if a cell is a LUT
 inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
+inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
+inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
-
 // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
 // as needed. Set no_dff if a DFF is not being used, so that the output
 // can be reconnected
@@ -58,8 +59,15 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = tr
 // ignored
 void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type = LutType::Normal);
 
-// Convert a nextpnr IO buffer to a GENERIC_IOB
-void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, pool<IdString> &todelete_cells);
+// Convert a nextpnr IO buffer to a TRELLIS_IO
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+                pool<IdString> &todelete_cells);
+
+void lut_to_comb(Context *ctx, CellInfo *lut);
+void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
+void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i);
+void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index);
+
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index d527c28f3d..0f5c2e10ef 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -15,6 +15,8 @@ X(FXB)
 X(CLK)
 X(LSR)
 X(CE)
+X(CEA)
+X(CEW)
 X(DI0)
 X(DI1)
 X(WD0)
@@ -131,3 +133,32 @@ X(place)
 X(placer)
 X(route)
 X(router)
+
+
+X(TRELLIS_COMB)
+X(TRELLIS_RAMW)
+X(WD)
+X(OFX)
+X(F)
+X(M)
+
+X(CCU2C)
+X(CCU2_INJECT1)
+X(INJECT1_0)
+X(INJECT1_1)
+X(TRELLIS_DPR16X4)
+X(INITVAL)
+X(INIT0)
+X(INIT1)
+
+X(DATAMUX_ODDR)
+X(DATAMUX_MDDR)
+X(CIN)
+X(S0)
+X(S1)
+X(COUT)
+
+X(E)
+X(Y)
+
+X(WCKMUX)
\ No newline at end of file
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 9d0b5ed98b..e4822f23d3 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -481,7 +481,7 @@ def main():
     constids["PIO"] = constids["TRELLIS_IO"]
 
     chip = pytrellis.Chip(dev_names[args.device])
-    rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=False)
+    rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=True)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_pio_db(rg, args.device)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 5f895cf98e..b6aa8be684 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1,8 +1,7 @@
 /*
  *  nextpnr -- Next Generation Place and Route
  *
- *  Copyright (C) 2018-19  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  William D. Jones <wjones@wdj-consulting.com>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -19,326 +18,1169 @@
  */
 
 #include <algorithm>
+#include <boost/optional.hpp>
 #include <iterator>
+#include <queue>
 #include "cells.h"
+#include "chain_utils.h"
 #include "design_utils.h"
 #include "log.h"
+#include "timing.h"
 #include "util.h"
-
 NEXTPNR_NAMESPACE_BEGIN
 
-// Pack LUTs and LUT-FF pairs
-static void pack_lut_lutffs(Context *ctx)
+static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 {
-    log_info("Packing LUT-FFs..\n");
+    return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
+           cell->type == ctx->id("$nextpnr_iobuf");
+}
 
-    pool<IdString> packed_cells;
-    std::vector<std::unique_ptr<CellInfo>> new_cells;
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (ctx->verbose)
-            log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
-        if (is_lut(ctx, ci)) {
-            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_LC");
-            for (auto &attr : ci->attrs)
-                packed->attrs[attr.first] = attr.second;
-
-            packed_cells.insert(ci->name);
-            if (ctx->verbose)
-                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
-            // See if we can pack into a DFF. Both LUT4 and FF outputs are
-            // available for a given slice, so we can pack a FF even if the
-            // LUT4 drives more than one FF.
-            NetInfo *o = ci->ports.at(id_Z).net;
-            CellInfo *dff = net_only_drives(ctx, o, is_ff, id_DI, false);
-            auto lut_bel = ci->attrs.find(id_BEL);
-            bool packed_dff = false;
-
-            if (dff) {
-                if (ctx->verbose)
-                    log_info("found attached dff %s\n", dff->name.c_str(ctx));
-                auto dff_bel = dff->attrs.find(id_BEL);
-                if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
-                    // Locations don't match, can't pack
-                } else {
-                    lut_to_lc(ctx, ci, packed.get(), false);
-                    dff_to_lc(ctx, dff, packed.get(), LutType::Normal);
-                    if (dff_bel != dff->attrs.end())
-                        packed->attrs[id_BEL] = dff_bel->second;
-                    packed_cells.insert(dff->name);
-                    if (ctx->verbose)
-                        log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
-                    packed_dff = true;
-                }
+static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
+{
+    auto gnd = ctx->id("$PACKER_GND_NET");
+    auto vcc = ctx->id("$PACKER_VCC_NET");
+    if (net == nullptr)
+        return false;
+    if (net->name.in(gnd, vcc)) {
+        value = (net->name == vcc);
+        return true;
+    } else {
+        return false;
+    }
+}
+
+class Ecp5Packer
+{
+  public:
+    Ecp5Packer(Context *ctx) : ctx(ctx){};
+
+  private:
+    // Process the contents of packed_cells and new_cells
+    void flush_cells()
+    {
+        for (auto pcell : packed_cells) {
+            ctx->cells.erase(pcell);
+        }
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+        packed_cells.clear();
+        new_cells.clear();
+    }
+
+    // Print logic usage
+    void print_logic_usage()
+    {
+        int total_luts = 0, total_ffs = 0;
+        int total_ramluts = 0, total_ramwluts = 0;
+        for (auto bel : ctx->getBels()) {
+            if (ctx->getBelType(bel) == id_TRELLIS_COMB) {
+                total_luts += 1;
+                Loc l = ctx->getBelLocation(bel);
+                if (l.z <= 3)
+                    total_ramluts += 1;
             }
-            if (!packed_dff) {
-                lut_to_lc(ctx, ci, packed.get(), true);
+            if (ctx->getBelType(bel) == id_TRELLIS_FF)
+                total_ffs += 1;
+            if (ctx->getBelType(bel) == id_TRELLIS_RAMW)
+                total_ramwluts += 2;
+        }
+        int used_lgluts = 0, used_cyluts = 0, used_ramluts = 0, used_ramwluts = 0, used_ffs = 0;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_lut(ctx, ci))
+                ++used_lgluts;
+            if (is_carry(ctx, ci))
+                used_cyluts += 2;
+            if (is_dpram(ctx, ci)) {
+                used_ramluts += 4;
+                used_ramwluts += 2;
             }
-            new_cells.push_back(std::move(packed));
+            if (is_ff(ctx, ci))
+                ++used_ffs;
         }
+        log_info("Logic utilisation before packing:\n");
+        auto pc = [](int used, int total) { return 100 * used / total; };
+        int used_luts = used_lgluts + used_cyluts + used_ramluts + used_ramwluts;
+        log_info("    Total LUT4s:     %5d/%5d %5d%%\n", used_luts, total_luts, pc(used_luts, total_luts));
+        log_info("        logic LUTs:  %5d/%5d %5d%%\n", used_lgluts, total_luts, pc(used_lgluts, total_luts));
+        log_info("        carry LUTs:  %5d/%5d %5d%%\n", used_cyluts, total_luts, pc(used_cyluts, total_luts));
+        log_info("          RAM LUTs:  %5d/%5d %5d%%\n", used_ramluts, total_ramluts, pc(used_ramluts, total_ramluts));
+        log_info("         RAMW LUTs:  %5d/%5d %5d%%\n", used_ramwluts, total_ramwluts,
+                 pc(used_ramwluts, total_ramwluts));
+        log_break();
+        log_info("     Total DFFs:     %5d/%5d %5d%%\n", used_ffs, total_ffs, pc(used_ffs, total_ffs));
+        log_break();
     }
 
-    for (auto pcell : packed_cells) {
-        ctx->cells.erase(pcell);
+    // Pack LUTs
+    void pack_luts()
+    {
+        log_info("Packing LUTs...\n");
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_lut(ctx, ci))
+                lut_to_comb(ctx, ci);
+        }
     }
-    for (auto &ncell : new_cells) {
-        ctx->cells[ncell->name] = std::move(ncell);
+
+    // Gets the z-position of a cell in a macro
+    int get_macro_cell_z(const CellInfo *ci)
+    {
+        if (ci->constr_abs_z)
+            return ci->constr_z;
+        else if (ci->cluster != ClusterId() && ctx->getClusterRootCell(ci->cluster) != ci)
+            return ci->constr_z + get_macro_cell_z(ctx->getClusterRootCell(ci->cluster));
+        else
+            return 0;
     }
-}
 
-static void pack_remaining_ffs(Context *ctx)
-{
-    log_info("Packing remaining FFs..\n");
+    // Gets the relative xy-position of a cell in a macro
+    std::pair<int, int> get_macro_cell_xy(const CellInfo *ci)
+    {
+        if (ci->cluster != ClusterId())
+            return {ci->constr_x, ci->constr_y};
+        else
+            return {0, 0};
+    }
 
-    pool<IdString> packed_cells;
-    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    // Relatively constrain one cell to another
+    void rel_constr_cells(CellInfo *a, CellInfo *b, int dz)
+    {
+        if (a->cluster != ClusterId() && ctx->getClusterRootCell(a->cluster) != a) {
+            NPNR_ASSERT(b->cluster == ClusterId());
+            NPNR_ASSERT(b->constr_children.empty());
+            CellInfo *root = ctx->getClusterRootCell(a->cluster);
+            root->constr_children.push_back(b);
+            b->cluster = root->cluster;
+            b->constr_x = a->constr_x;
+            b->constr_y = a->constr_y;
+            b->constr_z = get_macro_cell_z(a) + dz;
+            b->constr_abs_z = a->constr_abs_z;
+        } else if (b->cluster != ClusterId() && ctx->getClusterRootCell(b->cluster) != b) {
+            NPNR_ASSERT(a->constr_children.empty());
+            CellInfo *root = ctx->getClusterRootCell(b->cluster);
+            root->constr_children.push_back(a);
+            a->cluster = root->cluster;
+            a->constr_x = b->constr_x;
+            a->constr_y = b->constr_y;
+            a->constr_z = get_macro_cell_z(b) - dz;
+            a->constr_abs_z = b->constr_abs_z;
+        } else if (!b->constr_children.empty()) {
+            NPNR_ASSERT(a->constr_children.empty());
+            b->constr_children.push_back(a);
+            a->cluster = b->cluster;
+            a->constr_x = 0;
+            a->constr_y = 0;
+            a->constr_z = get_macro_cell_z(b) - dz;
+            a->constr_abs_z = b->constr_abs_z;
+        } else {
+            NPNR_ASSERT(a->cluster == ClusterId() || ctx->getClusterRootCell(a->cluster) == a);
+            a->constr_children.push_back(b);
+            a->cluster = a->name;
+            b->cluster = a->name;
+            b->constr_x = 0;
+            b->constr_y = 0;
+            b->constr_z = get_macro_cell_z(a) + dz;
+            b->constr_abs_z = a->constr_abs_z;
+        }
+    }
 
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
+    // Check if it is legal to add a FF to a macro
+    // This reuses the tile validity code
+    bool can_add_flipflop_to_macro(CellInfo *comb, CellInfo *ff)
+    {
+        Arch::LogicTileStatus lts;
+        std::fill(lts.cells.begin(), lts.cells.end(), nullptr);
+        lts.tile_dirty = true;
+        for (auto &sl : lts.slices)
+            sl.dirty = true;
+
+        auto process_cell = [&](CellInfo *ci) {
+            if (get_macro_cell_xy(ci) != get_macro_cell_xy(comb))
+                return;
+            int z = get_macro_cell_z(ci);
+            auto &slot = lts.cells.at(z);
+            NPNR_ASSERT(slot == nullptr);
+            slot = ci;
+            // Make sure fields needed for validity checking are set correctly
+            ctx->assign_arch_info_for_cell(ci);
+        };
+
+        if (comb->cluster != ClusterId()) {
+            CellInfo *root = ctx->getClusterRootCell(comb->cluster);
+            process_cell(root);
+            for (auto &ch : root->constr_children)
+                process_cell(ch);
+        } else {
+            process_cell(comb);
+            for (auto &ch : comb->constr_children)
+                process_cell(ch);
+        }
+        int ff_z = get_macro_cell_z(comb) + (Arch::BEL_FF - Arch::BEL_COMB);
+        if (lts.cells.at(ff_z) != nullptr)
+            return false;
+        ctx->assign_arch_info_for_cell(ff);
+        lts.cells.at(ff_z) = ff;
+        return ctx->slices_compatible(&lts);
+    }
 
-        if (is_ff(ctx, ci)) {
-            if (ctx->verbose)
-                log_info("cell '%s' of type '%s remains unpacked'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
+    void pack_ffs()
+    {
+        log_info("Packing FFs...\n");
+        int pairs = 0;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_ff(ctx, ci)) {
+                NetInfo *di = ci->getPort(id_DI);
+                if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
+                    CellInfo *comb = di->driver.cell;
+                    if (comb->cluster != ClusterId()) {
+                        // Special procedure where the comb cell is part of an existing macro
+                        // Need to make sure that CLK, CE, SR, etc are shared correctly, or
+                        // the design will not be routeable
+                        if (can_add_flipflop_to_macro(comb, ci)) {
+                            ci->params[id_SD] = std::string("1");
+                            rel_constr_cells(comb, ci, (Arch::BEL_FF - Arch::BEL_COMB));
+                            // Packed successfully
+                            ++pairs;
+                            continue;
+                        }
+                    } else {
+                        // LUT/COMB is not part of a macro, this is the easy case
+                        // Constrain FF and LUT together, no need to rewire
+                        ci->params[id_SD] = std::string("1");
+                        comb->constr_children.push_back(ci);
+                        ci->cluster = comb->name;
+                        comb->cluster = comb->name;
+                        ci->constr_x = 0;
+                        ci->constr_y = 0;
+                        ci->constr_z = (Arch::BEL_FF - Arch::BEL_COMB);
+                        ci->constr_abs_z = false;
+                        // Packed successfully
+                        ++pairs;
+                        continue;
+                    }
+                }
+                {
+                    // Didn't manage to pack it with a driving combinational cell
+                    // Rewire to use general routing
+                    ci->params[id_SD] = std::string("0");
+                    ci->renamePort(id_DI, id_M);
+                }
+            }
+        }
+        log_info("    %d FFs paired with LUTs.\n", pairs);
+    }
 
-            std::unique_ptr<CellInfo> packed = create_machxo2_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_LC");
-            for (auto &attr : ci->attrs)
-                packed->attrs[attr.first] = attr.second;
+    // Return true if an port is a top level port that provides its own IOBUF
+    bool is_top_port(PortRef &port)
+    {
+        return false;
+    }
 
-            auto dff_bel = ci->attrs.find(id_BEL);
+    // Return true if a net only drives a top port
+    bool drives_top_port(NetInfo *net, PortRef &tp)
+    {
+        if (net == nullptr)
+            return false;
+        for (auto user : net->users) {
+            if (is_top_port(user)) {
+                if (net->users.entries() > 1)
+                    log_error("   port %s.%s must be connected to (and only to) a top level pin\n",
+                              user.cell->name.c_str(ctx), user.port.c_str(ctx));
+                tp = user;
+                return true;
+            }
+        }
+        if (net->driver.cell != nullptr && is_top_port(net->driver)) {
+            if (net->users.entries() > 1)
+                log_error("   port %s.%s must be connected to (and only to) a top level pin\n",
+                          net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
+            tp = net->driver;
+            return true;
+        }
+        return false;
+    }
 
-            dff_to_lc(ctx, ci, packed.get(), LutType::None);
+    // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
+    void pack_io()
+    {
+        log_info("Packing IOs..\n");
 
-            if (dff_bel != ci->attrs.end())
-                packed->attrs[id_BEL] = dff_bel->second;
-            packed_cells.insert(ci->name);
-            if (ctx->verbose)
-                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_nextpnr_iob(ctx, ci)) {
+                CellInfo *trio = nullptr;
+                NetInfo *ionet = nullptr;
+                PortRef tp;
+                if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
+                    ionet = ci->ports.at(id_O).net;
+                    trio = net_only_drives(ctx, ionet, is_trellis_io, id_B, true, ci);
 
-            new_cells.push_back(std::move(packed));
+                } else if (ci->type == ctx->id("$nextpnr_obuf")) {
+                    ionet = ci->ports.at(id_I).net;
+                    trio = net_only_drives(ctx, ci->ports.at(id_I).net, is_trellis_io, id_B, true, ci);
+                }
+                if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
+                    // No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
+                    // and leave the top level port
+                    for (auto &port : ci->ports)
+                        ci->disconnectPort(port.first);
+                } else if (trio != nullptr) {
+                    // Trivial case, TRELLIS_IO used. Just remove the IOBUF
+                    log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
+                             ci->type.c_str(ctx), ci->name.c_str(ctx));
+
+                    NetInfo *net = trio->ports.at(id_B).net;
+                    if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
+                         net->users.entries() > 1) ||
+                        (ci->type == ctx->id("$nextpnr_obuf") &&
+                         (net->users.entries() > 2 || net->driver.cell != nullptr)) ||
+                        (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(id_I).net != nullptr &&
+                         ci->ports.at(id_I).net->driver.cell != nullptr))
+                        log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
+                                  trio->type.c_str(ctx), trio->name.c_str(ctx));
+                    if (net != nullptr) {
+                        if (net->clkconstr != nullptr && trio->ports.count(id_O)) {
+                            NetInfo *onet = trio->ports.at(id_O).net;
+                            if (onet != nullptr && !onet->clkconstr) {
+                                // Move clock constraint from IO pad to input buffer output
+                                std::swap(net->clkconstr, onet->clkconstr);
+                            }
+                        }
+                    }
+                } else if (drives_top_port(ionet, tp)) {
+                    log_info("%s feeds %s %s.%s, removing %s %s.\n", ci->name.c_str(ctx), tp.cell->type.c_str(ctx),
+                             tp.cell->name.c_str(ctx), tp.port.c_str(ctx), ci->type.c_str(ctx), ci->name.c_str(ctx));
+                    if (ionet != nullptr) {
+                        ctx->nets.erase(ionet->name);
+                        tp.cell->ports.at(tp.port).net = nullptr;
+                    }
+                    if (ci->type == ctx->id("$nextpnr_iobuf")) {
+                        NetInfo *net2 = ci->ports.at(id_I).net;
+                        if (net2 != nullptr) {
+                            ctx->nets.erase(net2->name);
+                        }
+                    }
+                } else {
+                    // Create a TRELLIS_IO buffer
+                    std::unique_ptr<CellInfo> tr_cell =
+                            create_machxo2_cell(ctx, id_TRELLIS_IO, ci->name.str(ctx) + "$tr_io");
+                    nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
+                    new_cells.push_back(std::move(tr_cell));
+                    trio = new_cells.back().get();
+                }
+                for (auto port : ci->ports)
+                    ci->disconnectPort(port.first);
+                packed_cells.insert(ci->name);
+                if (trio != nullptr) {
+                    for (const auto &attr : ci->attrs)
+                        trio->attrs[attr.first] = attr.second;
+
+                    auto loc_attr = trio->attrs.find(id_LOC);
+                    if (loc_attr != trio->attrs.end()) {
+                        std::string pin = loc_attr->second.as_string();
+                        BelId pinBel = ctx->getPackagePinBel(pin);
+                        if (pinBel == BelId()) {
+                            log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
+                                      trio->name.c_str(ctx), pin.c_str(), ctx->package_name);
+                        } else {
+                            log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
+                                     ctx->nameOfBel(pinBel));
+                        }
+                        trio->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
+                    }
+                }
+            }
         }
+        flush_cells();
     }
 
-    for (auto pcell : packed_cells) {
-        ctx->cells.erase(pcell);
+    // Create a feed in to the carry chain
+    CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
+    {
+        std::unique_ptr<CellInfo> feedin = create_machxo2_cell(ctx, id_CCU2C);
+
+        feedin->params[id_INIT0] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedin->params[id_INIT1] = Property(65535, 16);
+        feedin->params[id_INJECT1_0] = std::string("NO");
+        feedin->params[id_INJECT1_1] = std::string("YES");
+
+        carry->users.remove(chain_in.cell->ports.at(chain_in.port).user_idx);
+        feedin->connectPort(id_A0, carry);
+
+        NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
+        feedin->connectPort(id_COUT, new_carry);
+        chain_in.cell->ports[chain_in.port].net = nullptr;
+        chain_in.cell->ports[chain_in.port].user_idx = {};
+
+        chain_in.cell->connectPort(chain_in.port, new_carry);
+
+        CellInfo *feedin_ptr = feedin.get();
+        IdString feedin_name = feedin->name;
+        ctx->cells[feedin_name] = std::move(feedin);
+        return feedin_ptr;
     }
-    for (auto &ncell : new_cells) {
-        ctx->cells[ncell->name] = std::move(ncell);
+
+    // Create a feed out and loop through from the carry chain
+    CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
+    {
+        std::unique_ptr<CellInfo> feedout = create_machxo2_cell(ctx, id_CCU2C);
+
+        feedout->params[id_INIT0] = Property(0, 16);
+        feedout->params[id_INIT1] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedout->params[id_INJECT1_0] = std::string("NO");
+        feedout->params[id_INJECT1_1] = std::string("NO");
+
+        PortRef carry_drv = carry->driver;
+        carry->driver.cell = nullptr;
+        feedout->connectPort(id_S0, carry);
+
+        NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
+        new_cin->driver = carry_drv;
+        carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
+        feedout->connectPort(id_CIN, new_cin);
+
+        if (chain_next) {
+            // Loop back into LUT4_1 for feedthrough
+            feedout->connectPort(id_A1, carry);
+            if (chain_next->cell && chain_next->cell->ports.at(chain_next->port).user_idx)
+                carry->users.remove(chain_next->cell->ports.at(chain_next->port).user_idx);
+
+            NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
+            feedout->connectPort(id_COUT, new_cout);
+
+            chain_next->cell->ports[chain_next->port].net = nullptr;
+            chain_next->cell->connectPort(chain_next->port, new_cout);
+        }
+
+        CellInfo *feedout_ptr = feedout.get();
+        IdString feedout_name = feedout->name;
+        ctx->cells[feedout_name] = std::move(feedout);
+
+        return feedout_ptr;
     }
-}
 
-// Merge a net into a constant net
-static void set_net_constant(Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
-{
-    (void)constval;
+    // Split a carry chain into multiple legal chains
+    std::vector<CellChain> split_carry_chain(CellChain &carryc)
+    {
+        bool start_of_chain = true;
+        std::vector<CellChain> chains;
+        const int max_length = (ctx->chip_info->width - 4) * 4 - 2;
+        auto curr_cell = carryc.cells.begin();
+        while (curr_cell != carryc.cells.end()) {
+            CellInfo *cell = *curr_cell;
+            if (start_of_chain) {
+                chains.emplace_back();
+                start_of_chain = false;
+                if (cell->ports.at(id_CIN).net) {
+                    // CIN is not constant and not part of a chain. Must feed in from fabric
+                    PortRef inport;
+                    inport.cell = cell;
+                    inport.port = id_CIN;
+                    CellInfo *feedin = make_carry_feed_in(cell->ports.at(id_CIN).net, inport);
+                    chains.back().cells.push_back(feedin);
+                }
+            }
+            chains.back().cells.push_back(cell);
+            bool split_chain = int(chains.back().cells.size()) > max_length;
+            if (split_chain) {
+                CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net);
+                chains.back().cells.back() = passout;
+                start_of_chain = true;
+            } else {
+                NetInfo *carry_net = cell->ports.at(id_COUT).net;
+                bool at_end = (curr_cell == carryc.cells.end() - 1);
+                if (carry_net != nullptr && (carry_net->users.entries() > 1 || at_end)) {
+                    boost::optional<PortRef> nextport;
+                    if (!at_end) {
+                        auto next_cell = *(curr_cell + 1);
+                        PortRef nextpr;
+                        nextpr.cell = next_cell;
+                        nextpr.port = id_CIN;
+                        nextport = nextpr;
+                    }
+                    CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net, nextport);
+                    chains.back().cells.push_back(passout);
+                }
+                ++curr_cell;
+            }
+        }
+        return chains;
+    }
 
-    pool<IdString> packed_cells;
-    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    // Pack carries and set up appropriate relative constraints
+    void pack_carries()
+    {
+        log_info("Packing carries...\n");
+        // Find all chains (including single carry cells)
+        auto carry_chains = find_chains(
+                ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
+                [](const Context *ctx, const CellInfo *cell) {
+                    return net_driven_by(ctx, cell->ports.at(id_CIN).net, is_carry, id_COUT);
+                },
+                [](const Context *ctx, const CellInfo *cell) {
+                    return net_only_drives(ctx, cell->ports.at(id_COUT).net, is_carry, id_CIN, false);
+                },
+                1);
+        std::vector<CellChain> all_chains;
+
+        // Chain splitting
+        for (auto &base_chain : carry_chains) {
+            if (ctx->verbose) {
+                log_info("Found carry chain: \n");
+                for (auto entry : base_chain.cells)
+                    log_info("     %s\n", entry->name.c_str(ctx));
+                log_info("\n");
+            }
+            std::vector<CellChain> split_chains = split_carry_chain(base_chain);
+            for (auto &chain : split_chains) {
+                all_chains.push_back(chain);
+            }
+        }
+
+        std::vector<std::vector<CellInfo *>> packed_chains;
+
+        // Chain packing
+        std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
+        for (auto &chain : all_chains) {
+            int cell_count = 0;
+            std::vector<CellInfo *> packed_chain;
+            for (auto &cell : chain.cells) {
+                std::unique_ptr<CellInfo> comb0 =
+                        create_machxo2_cell(ctx, id_TRELLIS_COMB, cell->name.str(ctx) + "$CCU2_COMB0");
+                std::unique_ptr<CellInfo> comb1 =
+                        create_machxo2_cell(ctx, id_TRELLIS_COMB, cell->name.str(ctx) + "$CCU2_COMB1");
+                NetInfo *carry_net = ctx->createNet(ctx->id(cell->name.str(ctx) + "$CCU2_FCI_INT"));
 
-    orig->driver.cell = nullptr;
-    for (auto user : orig->users) {
-        if (user.cell != nullptr) {
-            CellInfo *uc = user.cell;
-            if (ctx->verbose)
-                log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
+                ccu2_to_comb(ctx, cell, comb0.get(), carry_net, 0);
+                ccu2_to_comb(ctx, cell, comb1.get(), carry_net, 1);
 
-            if (uc->type == id_TRELLIS_FF && user.port == id_DI) {
-                log_info("TRELLIS_FF %s is driven by a constant\n", uc->name.c_str(ctx));
+                packed_chain.push_back(comb0.get());
+                packed_chain.push_back(comb1.get());
 
-                std::unique_ptr<CellInfo> lc = create_machxo2_cell(ctx, id_TRELLIS_SLICE, uc->name.str(ctx) + "_CONST");
-                for (auto &attr : uc->attrs)
-                    lc->attrs[attr.first] = attr.second;
+                new_cells.push_back(std::move(comb0));
+                new_cells.push_back(std::move(comb1));
+                packed_cells.insert(cell->name);
+                cell_count++;
+            }
+            packed_chains.push_back(packed_chain);
+        }
+
+        // Relative chain placement
+        for (auto &chain : packed_chains) {
+            chain.at(0)->constr_abs_z = true;
+            chain.at(0)->constr_z = 0;
+            chain.at(0)->cluster = chain.at(0)->name;
+            for (int i = 1; i < int(chain.size()); i++) {
+                chain.at(i)->constr_x = (i / 8);
+                chain.at(i)->constr_y = 0;
+                chain.at(i)->constr_z = (i % 8) << ctx->lc_idx_shift | Arch::BEL_COMB;
+                chain.at(i)->constr_abs_z = true;
+                chain.at(i)->cluster = chain.at(0)->name;
+                chain.at(0)->constr_children.push_back(chain.at(i));
+            }
+        }
+
+        flush_cells();
+    }
 
-                dff_to_lc(ctx, uc, lc.get(), LutType::PassThru);
-                packed_cells.insert(uc->name);
+    // Pack distributed RAM
+    void pack_dram()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_dpram(ctx, ci)) {
 
-                lc->ports[id_A0].net = constnet;
-                user.cell = lc.get();
-                user.port = id_A0;
+                // Create RAMW slice
+                std::unique_ptr<CellInfo> ramw_slice =
+                        create_machxo2_cell(ctx, id_TRELLIS_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
+                dram_to_ramw_split(ctx, ci, ramw_slice.get());
 
-                new_cells.push_back(std::move(lc));
+                // Create actual RAM slices
+                std::unique_ptr<CellInfo> ram_comb[4];
+                for (int i = 0; i < 4; i++) {
+                    ram_comb[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB,
+                                                   ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i));
+                    dram_to_comb(ctx, ci, ram_comb[i].get(), ramw_slice.get(), i);
+                }
+                // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
+                std::unique_ptr<CellInfo> ramw_block[2];
+                for (int i = 0; i < 2; i++) {
+                    ramw_block[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB,
+                                                     ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
+                    ramw_block[i]->params[id_MODE] = std::string("RAMW_BLOCK");
+                }
+
+                // Disconnect ports of original cell after packing
+                ci->disconnectPort(id_WCK);
+                ci->disconnectPort(id_WRE);
+
+                for (int i = 0; i < 4; i++)
+                    ci->disconnectPort(ctx->idf("RAD[%d]", i));
+
+                // Setup placement constraints
+                // Use the 0th bit as an anchor
+                ram_comb[0]->constr_abs_z = true;
+                ram_comb[0]->constr_z = Arch::BEL_COMB;
+                ram_comb[0]->cluster = ram_comb[0]->name;
+                for (int i = 1; i < 4; i++) {
+                    ram_comb[i]->cluster = ram_comb[0]->name;
+                    ram_comb[i]->constr_abs_z = true;
+                    ram_comb[i]->constr_x = 0;
+                    ram_comb[i]->constr_y = 0;
+                    ram_comb[i]->constr_z = (i << ctx->lc_idx_shift) | Arch::BEL_COMB;
+                    ram_comb[0]->constr_children.push_back(ram_comb[i].get());
+                }
+                for (int i = 0; i < 2; i++) {
+                    ramw_block[i]->cluster = ram_comb[0]->name;
+                    ramw_block[i]->constr_abs_z = true;
+                    ramw_block[i]->constr_x = 0;
+                    ramw_block[i]->constr_y = 0;
+                    ramw_block[i]->constr_z = ((i + 4) << ctx->lc_idx_shift) | Arch::BEL_COMB;
+                    ram_comb[0]->constr_children.push_back(ramw_block[i].get());
+                }
+
+                ramw_slice->cluster = ram_comb[0]->name;
+                ramw_slice->constr_abs_z = true;
+                ramw_slice->constr_x = 0;
+                ramw_slice->constr_y = 0;
+                ramw_slice->constr_z = (4 << ctx->lc_idx_shift) | Arch::BEL_RAMW;
+                ram_comb[0]->constr_children.push_back(ramw_slice.get());
+
+                for (int i = 0; i < 4; i++)
+                    new_cells.push_back(std::move(ram_comb[i]));
+                for (int i = 0; i < 2; i++)
+                    new_cells.push_back(std::move(ramw_block[i]));
+                new_cells.push_back(std::move(ramw_slice));
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+    }
+
+    int make_init_with_const_input(int init, int input, bool value)
+    {
+        int new_init = 0;
+        for (int i = 0; i < 16; i++) {
+            if (((i >> input) & 0x1) != value) {
+                int other_i = (i & (~(1 << input))) | (value << input);
+                if ((init >> other_i) & 0x1)
+                    new_init |= (1 << i);
             } else {
-                uc->ports[user.port].net = constnet;
+                if ((init >> i) & 0x1)
+                    new_init |= (1 << i);
+            }
+        }
+        return new_init;
+    }
+
+    void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
+    {
+        int index = std::string("ABCD").find(input.str(ctx));
+        int init = int_or_default(cell->params, id_INIT);
+        int new_init = make_init_with_const_input(init, index, value);
+        cell->params[id_INIT] = Property(new_init, 16);
+        cell->ports.at(input).net = nullptr;
+    }
+
+    void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value)
+    {
+        std::string input_str = input.str(ctx);
+        int lut = std::stoi(input_str.substr(1));
+        int index = std::string("ABCD").find(input_str[0]);
+        int init = int_or_default(cell->params, ctx->id("INIT" + std::to_string(lut)));
+        int new_init = make_init_with_const_input(init, index, value);
+        cell->params[ctx->id("INIT" + std::to_string(lut))] = Property(new_init, 16);
+        cell->ports.at(input).net = nullptr;
+    }
+
+    bool is_ccu2c_port_high(CellInfo *cell, IdString input)
+    {
+        if (!cell->ports.count(input))
+            return true; // disconnected port is high
+        if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
+            return true; // disconnected or tied-high port
+        if (cell->ports.at(input).net->driver.cell != nullptr && cell->ports.at(input).net->driver.cell->type == id_VCC)
+            return true; // pre-pack high
+        return false;
+    }
+
+    // Merge a net into a constant net
+    void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
+    {
+        orig->driver.cell = nullptr;
+        for (auto user : orig->users) {
+            if (user.cell != nullptr) {
+                CellInfo *uc = user.cell;
+                if (ctx->verbose)
+                    log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
+                if (is_lut(ctx, uc)) {
+                    set_lut_input_constant(uc, user.port, constval);
+                } else if (is_ff(ctx, uc) && user.port == id_CE) {
+                    uc->params[id_CEMUX] = std::string(constval ? "1" : "0");
+                    uc->ports[user.port].net = nullptr;
+                } else if (is_carry(ctx, uc)) {
+                    if (constval && (user.port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))) {
+                        // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
+                        uc->ports[user.port].net = nullptr;
+                    } else if (!constval) {
+                        if (user.port.in(id_A0, id_A1, id_B0, id_B1)) {
+                            // These inputs can be switched to tie-high without consequence
+                            set_ccu2c_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
+                            // Partner must be tied high
+                            set_ccu2c_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) {
+                            // Partner must be tied high
+                            set_ccu2c_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) {
+                            // Partner must be tied high
+                            set_ccu2c_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) {
+                            // Partner must be tied high
+                            set_ccu2c_input_constant(uc, user.port, constval);
+                        } else {
+                            // Not allowed to change to a tie-high
+                            uc->ports[user.port].net = constnet;
+                            uc->ports[user.port].user_idx = constnet->users.add(user);
+                        }
+                    } else {
+                        uc->ports[user.port].net = constnet;
+                        uc->ports[user.port].user_idx = constnet->users.add(user);
+                    }
+                } else if (is_ff(ctx, uc) && user.port == id_LSR &&
+                           ((!constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "LSR") ||
+                            (constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "INV"))) {
+                    uc->ports[user.port].net = nullptr;
+                } else {
+                    uc->ports[user.port].net = constnet;
+                    uc->ports[user.port].user_idx = constnet->users.add(user);
+                }
+            }
+        }
+        orig->users.clear();
+    }
+
+    // Pack constants (simple implementation)
+    void pack_constants()
+    {
+        log_info("Packing constants..\n");
+
+        std::unique_ptr<CellInfo> gnd_cell = create_machxo2_cell(ctx, id_LUT4, "$PACKER_GND");
+        gnd_cell->params[id_INIT] = Property(0, 16);
+        auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
+        gnd_net->driver.cell = gnd_cell.get();
+        gnd_net->driver.port = id_Z;
+        gnd_cell->ports.at(id_Z).net = gnd_net.get();
+
+        std::unique_ptr<CellInfo> vcc_cell = create_machxo2_cell(ctx, id_LUT4, "$PACKER_VCC");
+        vcc_cell->params[id_INIT] = Property(65535, 16);
+        auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
+        vcc_net->driver.cell = vcc_cell.get();
+        vcc_net->driver.port = id_Z;
+        vcc_cell->ports.at(id_Z).net = vcc_net.get();
+
+        std::vector<IdString> dead_nets;
+
+        bool gnd_used = false, vcc_used = false;
+
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
+                IdString drv_cell = ni->driver.cell->name;
+                set_net_constant(ctx, ni, gnd_net.get(), false);
+                gnd_used = true;
+                dead_nets.push_back(net.first);
+                ctx->cells.erase(drv_cell);
+            } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
+                IdString drv_cell = ni->driver.cell->name;
+                set_net_constant(ctx, ni, vcc_net.get(), true);
+                vcc_used = true;
+                dead_nets.push_back(net.first);
+                ctx->cells.erase(drv_cell);
             }
+        }
 
-            user.cell->ports.at(user.port).user_idx = constnet->users.add(user);
+        if (gnd_used) {
+            ctx->cells[gnd_cell->name] = std::move(gnd_cell);
+            ctx->nets[gnd_net->name] = std::move(gnd_net);
+        }
+        if (vcc_used) {
+            ctx->cells[vcc_cell->name] = std::move(vcc_cell);
+            ctx->nets[vcc_net->name] = std::move(vcc_net);
+        }
+
+        for (auto dn : dead_nets) {
+            ctx->nets.erase(dn);
         }
     }
-    orig->users.clear();
 
-    for (auto pcell : packed_cells) {
-        ctx->cells.erase(pcell);
+    void autocreate_empty_port(CellInfo *cell, IdString port)
+    {
+        if (!cell->ports.count(port)) {
+            cell->ports[port].name = port;
+            cell->ports[port].net = nullptr;
+            cell->ports[port].type = PORT_IN;
+        }
     }
-    for (auto &ncell : new_cells) {
-        ctx->cells[ncell->name] = std::move(ncell);
+
+    // Check if two nets have identical constant drivers
+    bool equal_constant(NetInfo *a, NetInfo *b)
+    {
+        if (a == nullptr && b == nullptr)
+            return true;
+        if ((a == nullptr) != (b == nullptr))
+            return false;
+        if (a->driver.cell == nullptr || b->driver.cell == nullptr)
+            return (a->driver.cell == nullptr && b->driver.cell == nullptr);
+        if (a->driver.cell->type != id_GND && a->driver.cell->type != id_VCC)
+            return false;
+        return a->driver.cell->type == b->driver.cell->type;
     }
-}
 
-// Pack constants (based on simple implementation in generic).
-// VCC/GND cells provided by nextpnr automatically.
-static void pack_constants(Context *ctx)
-{
-    log_info("Packing constants..\n");
-
-    std::unique_ptr<CellInfo> const_cell = create_machxo2_cell(ctx, id_TRELLIS_SLICE, "$PACKER_CONST");
-    const_cell->params[id_LUT0_INITVAL] = Property(0, 16);
-    const_cell->params[id_LUT1_INITVAL] = Property(0xFFFF, 16);
-
-    NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
-    gnd_net->driver.cell = const_cell.get();
-    gnd_net->driver.port = id_F0;
-    const_cell->ports.at(id_F0).net = gnd_net;
-
-    NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
-    vcc_net->name = ctx->id("$PACKER_VCC_NET");
-    vcc_net->driver.cell = const_cell.get();
-    vcc_net->driver.port = id_F1;
-    const_cell->ports.at(id_F1).net = vcc_net;
-
-    std::vector<IdString> dead_nets;
-
-    for (auto &net : ctx->nets) {
-        NetInfo *ni = net.second.get();
-        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
-            IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, gnd_net, false);
-            dead_nets.push_back(net.first);
-            ctx->cells.erase(drv_cell);
-        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
-            IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, vcc_net, true);
-            dead_nets.push_back(net.first);
-            ctx->cells.erase(drv_cell);
+    struct EdgeClockInfo
+    {
+        CellInfo *buffer = nullptr;
+        NetInfo *unbuf = nullptr;
+        NetInfo *buf = nullptr;
+    };
+
+    std::map<std::pair<int, int>, EdgeClockInfo> eclks;
+    std::map<NetInfo *, int> bridge_side_hint;
+
+    void tie_zero(CellInfo *ci, IdString port)
+    {
+
+        if (!ci->ports.count(port)) {
+            ci->ports[port].name = port;
+            ci->ports[port].type = PORT_IN;
         }
+        IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
+
+        auto zero_cell = std::make_unique<CellInfo>(ctx, name, id_GND);
+        NetInfo *zero_net = ctx->createNet(name);
+        zero_cell->addOutput(id_GND);
+        zero_cell->connectPort(id_GND, zero_net);
+        ci->connectPort(port, zero_net);
+        new_cells.push_back(std::move(zero_cell));
     }
 
-    ctx->cells[const_cell->name] = std::move(const_cell);
+    int lookup_delay(const std::string &del_mode)
+    {
+        if (del_mode == "USER_DEFINED")
+            return 0;
+        else if (del_mode == "DQS_ALIGNED_X2")
+            return 6;
+        else if (del_mode == "DQS_CMD_CLK")
+            return 9;
+        else if (del_mode == "ECLK_ALIGNED")
+            return 21;
+        else if (del_mode == "ECLK_CENTERED")
+            return 11;
+        else if (del_mode == "ECLKBRIDGE_ALIGNED")
+            return 39;
+        else if (del_mode == "ECLKBRIDGE_CENTERED")
+            return 29;
+        else if (del_mode == "SCLK_ALIGNED")
+            return 50;
+        else if (del_mode == "SCLK_CENTERED")
+            return 39;
+        else if (del_mode == "SCLK_ZEROHOLD")
+            return 59;
+        else
+            log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
+    }
 
-    for (auto dn : dead_nets) {
-        ctx->nets.erase(dn);
+    void prepack_checks()
+    {
+        // Check for legacy-style JSON (use CEMUX as a clue) and error out, avoiding a confusing assertion failure
+        // later
+        for (auto &cell : ctx->cells) {
+            if (is_ff(ctx, cell.second.get()) && cell.second->params.count(id_CEMUX) &&
+                !cell.second->params[id_CEMUX].is_string)
+                log_error("Found netlist using legacy-style JSON parameter values, please update your Yosys.\n");
+        }
     }
-}
 
-static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
+  public:
+    void pack()
+    {
+        prepack_checks();
+        print_logic_usage();
+        pack_io();
+        pack_constants();
+        pack_dram();
+        pack_carries();
+        pack_luts();
+        pack_ffs();
+        ctx->fixupHierarchy();
+        ctx->check();
+    }
+
+  private:
+    Context *ctx;
+
+    pool<IdString> packed_cells;
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+    struct SliceUsage
+    {
+        bool lut0_used = false, lut1_used = false;
+        bool ccu2_used = false, dpram_used = false, ramw_used = false;
+        bool ff0_used = false, ff1_used = false;
+        bool mux5_used = false, muxx_used = false;
+    };
+
+    dict<IdString, SliceUsage> sliceUsage;
+    dict<IdString, IdString> lutffPairs;
+    dict<IdString, IdString> fflutPairs;
+    dict<IdString, IdString> lutPairs;
+};
+// Main pack function
+bool Arch::pack()
 {
-    return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
-           cell->type == ctx->id("$nextpnr_iobuf");
+    Context *ctx = getCtx();
+    try {
+        log_break();
+        Ecp5Packer(ctx).pack();
+        log_info("Checksum: 0x%08x\n", ctx->checksum());
+        assignArchInfo();
+        ctx->settings[id_pack] = 1;
+        archInfoToAttributes();
+        return true;
+    } catch (log_execution_error_exception) {
+        assignArchInfo();
+        return false;
+    }
 }
 
-static bool is_trellis_iob(const Context *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
+void Arch::assign_arch_info_for_cell(CellInfo *ci)
+{
+    auto get_port_net = [&](CellInfo *ci, IdString p) {
+        NetInfo *n = ci->getPort(p);
+        return n ? n->name : IdString();
+    };
+    if (ci->type == id_TRELLIS_COMB) {
+        std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+        ci->combInfo.flags = ArchCellInfo::COMB_NONE;
+        if (mode == "CCU2")
+            ci->combInfo.flags |= ArchCellInfo::COMB_CARRY;
+        if (mode == "DPRAM") {
+            ci->combInfo.flags |= ArchCellInfo::COMB_LUTRAM;
+            std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+            if (wckmux == "INV")
+                ci->combInfo.flags |= ArchCellInfo::COMB_RAM_WCKINV;
+            std::string wremux = str_or_default(ci->params, id_WREMUX, "WRE");
+            if (wremux == "INV" || wremux == "0")
+                ci->combInfo.flags |= ArchCellInfo::COMB_RAM_WREINV;
+            ci->combInfo.ram_wck = get_port_net(ci, id_WCK);
+            ci->combInfo.ram_wre = get_port_net(ci, id_WRE);
+        }
+        if (mode == "RAMW_BLOCK")
+            ci->combInfo.flags |= ArchCellInfo::COMB_RAMW_BLOCK;
+        if (ci->getPort(id_F1) != nullptr)
+            ci->combInfo.flags |= ArchCellInfo::COMB_MUX5;
+        if (ci->getPort(id_FXA) != nullptr || ci->getPort(id_FXB) != nullptr) {
+            ci->combInfo.flags |= ArchCellInfo::COMB_MUX6;
+            NetInfo *fxa = ci->getPort(id_FXA);
+            if (fxa != nullptr)
+                ci->combInfo.mux_fxad = fxa->driver.cell;
+        }
+    } else if (ci->type == id_TRELLIS_FF) {
+        ci->ffInfo.flags = ArchCellInfo::FF_NONE;
+        if (str_or_default(ci->params, id_GSR, "ENABLED") == "ENABLED")
+            ci->ffInfo.flags |= ArchCellInfo::FF_GSREN;
+        if (str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE") == "ASYNC")
+            ci->ffInfo.flags |= ArchCellInfo::FF_ASYNC;
+        if (ci->getPort(id_M) != nullptr)
+            ci->ffInfo.flags |= ArchCellInfo::FF_M_USED;
+        std::string clkmux = str_or_default(ci->params, id_CLKMUX, "CLK");
+        std::string cemux = str_or_default(ci->params, id_CEMUX, "CE");
+        std::string lsrmux = str_or_default(ci->params, id_LSRMUX, "LSR");
+        if (clkmux == "INV" || clkmux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CLKINV;
+        if (cemux == "INV" || cemux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CEINV;
+        if (cemux == "1" || cemux == "0")
+            ci->ffInfo.flags |= ArchCellInfo::FF_CECONST;
+        if (lsrmux == "INV")
+            ci->ffInfo.flags |= ArchCellInfo::FF_LSRINV;
+        ci->ffInfo.clk_sig = get_port_net(ci, id_CLK);
+        ci->ffInfo.ce_sig = get_port_net(ci, id_CE);
+        ci->ffInfo.lsr_sig = get_port_net(ci, id_LSR);
+    }
+}
 
-static bool nextpnr_iob_connects_only_trellis_iob(Context *ctx, CellInfo *iob, NetInfo *&top)
+void Arch::assignArchInfo()
 {
-    NPNR_ASSERT(is_nextpnr_iob(ctx, iob));
-
-    if (iob->type == ctx->id("$nextpnr_ibuf")) {
-        NetInfo *o = iob->ports.at(id_O).net;
-        top = o;
-
-        CellInfo *fio = net_only_drives(ctx, o, is_trellis_iob, id_B, true);
-        return fio != nullptr;
-    } else if (iob->type == ctx->id("$nextpnr_obuf")) {
-        NetInfo *i = iob->ports.at(id_I).net;
-        top = i;
-
-        // If connected to a TRELLIS_IO PAD, the net attached to an I port of an
-        // $nextpnr_obuf will not have a driver, only users; an inout port
-        // like PAD cannot be a driver in nextpnr. So net_driven_by won't
-        // return anything. We exclude the IOB as one of the two users because
-        // we already know that the net drives the $nextpnr_obuf.
-        CellInfo *fio = net_only_drives(ctx, i, is_trellis_iob, id_B, true, iob);
-        return fio != nullptr;
-    } else if (iob->type == ctx->id("$nextpnr_iobuf")) {
-        NetInfo *o = iob->ports.at(id_O).net;
-        top = o;
-
-        // When split_io is enabled in a frontend (it is for JSON), the I and O
-        // ports of a $nextpnr_iobuf are split; the I port connects to the
-        // driver of the original net before IOB insertion, and the O port
-        // connects everything else. Because TRELLIS_IO PADs cannot be a driver
-        // in nextpnr, the we can safely ignore the I port of an $nextpnr_iobuf
-        // for any JSON input we're interested in accepting.
-        CellInfo *fio_o = net_only_drives(ctx, o, is_trellis_iob, id_B, true);
-        return fio_o != nullptr;
-    }
-
-    // Unreachable!
-    NPNR_ASSERT(false);
+    for (auto &cell : cells) {
+        CellInfo *ci = cell.second.get();
+        assign_arch_info_for_cell(ci);
+    }
 }
 
-// Pack IO buffers- Right now, all this does is remove $nextpnr_[io]buf cells.
-// User is expected to manually instantiate TRELLIS_IO with BEL/IO_TYPE
-// attributes.
-static void pack_io(Context *ctx)
+inline NetInfo *port_or_nullptr(const CellInfo *cell, IdString name)
 {
-    pool<IdString> packed_cells;
+    auto found = cell->ports.find(name);
+    if (found == cell->ports.end())
+        return nullptr;
+    return found->second.net;
+}
 
-    log_info("Packing IOs..\n");
+bool Arch::slices_compatible(LogicTileStatus *lts) const
+{
+    if (lts == nullptr)
+        return true;
+    for (int sl = 0; sl < 4; sl++) {
+        if (!lts->slices[sl].dirty) {
+            if (!lts->slices[sl].valid)
+                return false;
+            continue;
+        }
+        lts->slices[sl].dirty = false;
+        lts->slices[sl].valid = false;
+        bool found_ff = false;
+        uint8_t last_ff_flags = 0;
+        IdString last_ce_sig;
+        bool ramw_used = false;
+        if (sl == 2 && lts->cells[((sl * 2) << lc_idx_shift) | BEL_RAMW] != nullptr)
+            ramw_used = true;
+        for (int l = 0; l < 2; l++) {
+            bool comb_m_used = false;
+            CellInfo *comb = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_COMB];
+            if (comb != nullptr) {
+                uint8_t flags = comb->combInfo.flags;
+                if (ramw_used && !(flags & ArchCellInfo::COMB_RAMW_BLOCK))
+                    return false;
+                if (flags & ArchCellInfo::COMB_MUX5) {
+                    // MUX5 uses M signal and must be in LC 0
+                    comb_m_used = true;
+                    if (l != 0)
+                        return false;
+                }
+                if (flags & ArchCellInfo::COMB_MUX6) {
+                    // MUX6+ uses M signal and must be in LC 1
+                    comb_m_used = true;
+                    if (l != 1)
+                        return false;
+                    if (comb->combInfo.mux_fxad != nullptr &&
+                        (comb->combInfo.mux_fxad->combInfo.flags & ArchCellInfo::COMB_MUX5)) {
+                        // LUT6 structure must be rooted at SLICE 0 or 2
+                        if (sl != 0 && sl != 2)
+                            return false;
+                    }
+                }
+                // LUTRAM must be in bottom two SLICEs only
+                if ((flags & ArchCellInfo::COMB_LUTRAM) && (sl > 1))
+                    return false;
+                if (l == 1) {
+                    // Carry usage must be the same for LCs 0 and 1 in a SLICE
+                    CellInfo *comb0 = lts->cells[((sl * 2 + 0) << lc_idx_shift) | BEL_COMB];
+                    if (comb0 &&
+                        ((comb0->combInfo.flags & ArchCellInfo::COMB_CARRY) != (flags & ArchCellInfo::COMB_CARRY)))
+                        return false;
+                }
+            }
 
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (is_nextpnr_iob(ctx, ci)) {
-            NetInfo *top;
-
-            if (!nextpnr_iob_connects_only_trellis_iob(ctx, ci, top))
-                log_error("Top level net '%s' is not connected to a TRELLIS_IO PAD port.\n", top->name.c_str(ctx));
-
-            if (ctx->verbose)
-                log_info("Removing top-level IOBUF '%s' of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
-
-            for (auto &p : ci->ports)
-                ci->disconnectPort(p.first);
-            packed_cells.insert(ci->name);
-        } else if (is_trellis_iob(ctx, ci)) {
-            // If TRELLIS_IO has LOC attribute, convert the LOC (pin) to a BEL
-            // attribute and place TRELLIS_IO at resulting BEL location. A BEL
-            // attribute already on a TRELLIS_IO is an error. Attributes on
-            // the pin attached to the PAD of TRELLIS_IO are ignored by this
-            // packing phase.
-            auto loc_attr_cell = ci->attrs.find(id_LOC);
-            auto bel_attr_cell = ci->attrs.find(id_BEL);
-
-            if (loc_attr_cell != ci->attrs.end()) {
-                if (bel_attr_cell != ci->attrs.end()) {
-                    log_error("IO buffer %s has both a BEL attribute and LOC attribute.\n", ci->name.c_str(ctx));
+            CellInfo *ff = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                uint8_t flags = ff->ffInfo.flags;
+                if (comb_m_used && (flags & ArchCellInfo::FF_M_USED))
+                    return false;
+                if (found_ff) {
+                    if ((flags & ArchCellInfo::FF_GSREN) != (last_ff_flags & ArchCellInfo::FF_GSREN))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CECONST) != (last_ff_flags & ArchCellInfo::FF_CECONST))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CEINV) != (last_ff_flags & ArchCellInfo::FF_CEINV))
+                        return false;
+                    if (ff->ffInfo.ce_sig != last_ce_sig)
+                        return false;
+                } else {
+                    found_ff = true;
+                    last_ff_flags = flags;
+                    last_ce_sig = ff->ffInfo.ce_sig;
                 }
+            }
+        }
+
+        lts->slices[sl].valid = true;
+    }
+    if (lts->tile_dirty) {
+        bool found_global_ff = false;
+        bool found_global_dpram = false;
+        bool global_lsrinv = false;
+        bool global_clkinv = false;
+        bool global_async = false;
 
-                log_info("found LOC attribute on IO buffer %s.\n", ci->name.c_str(ctx));
-                std::string pin = loc_attr_cell->second.as_string();
+        IdString clk_sig, lsr_sig;
+
+        lts->tile_dirty = false;
+        lts->tile_valid = false;
+
+#define CHECK_EQUAL(x, y)                                                                                              \
+    do {                                                                                                               \
+        if ((x) != (y))                                                                                                \
+            return false;                                                                                              \
+    } while (0)
+        for (int i = 0; i < 8; i++) {
+            if (i < 4) {
+                // DPRAM
+                CellInfo *comb = lts->cells[(i << lc_idx_shift) | BEL_COMB];
+                if (comb != nullptr && (comb->combInfo.flags & ArchCellInfo::COMB_LUTRAM)) {
+                    if (found_global_dpram) {
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV), global_clkinv);
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV), global_lsrinv);
+                    } else {
+                        global_clkinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV);
+                        global_lsrinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV);
+                        found_global_dpram = true;
+                    }
+                }
+            }
+            // FF
+            CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                if (found_global_dpram) {
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                }
+                if (found_global_ff) {
+                    CHECK_EQUAL(ff->ffInfo.clk_sig, clk_sig);
+                    CHECK_EQUAL(ff->ffInfo.lsr_sig, lsr_sig);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC), global_async);
 
-                BelId pinBel = ctx->getPackagePinBel(pin);
-                if (pinBel == BelId()) {
-                    log_error("IO buffer '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
-                              ci->name.c_str(ctx), pin.c_str(), ctx->package_name);
                 } else {
-                    log_info("pin '%s' constrained to Bel '%s'.\n", ci->name.c_str(ctx), ctx->nameOfBel(pinBel));
+                    clk_sig = ff->ffInfo.clk_sig;
+                    lsr_sig = ff->ffInfo.lsr_sig;
+                    global_clkinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV);
+                    global_lsrinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV);
+                    global_async = bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC);
+                    found_global_ff = true;
                 }
-                ci->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
             }
         }
+#undef CHECK_EQUAL
+        lts->tile_valid = true;
+    } else {
+        if (!lts->tile_valid)
+            return false;
     }
 
-    for (auto pcell : packed_cells) {
-        ctx->cells.erase(pcell);
-    }
+    return true;
 }
 
-// Main pack function
-bool Arch::pack()
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
-    Context *ctx = getCtx();
-    try {
-        log_break();
-        pack_constants(ctx);
-        pack_io(ctx);
-        pack_lut_lutffs(ctx);
-        pack_remaining_ffs(ctx);
-        ctx->settings[id_pack] = 1;
-        ctx->assignArchInfo();
-        log_info("Checksum: 0x%08x\n", ctx->checksum());
-        return true;
-    } catch (log_execution_error_exception) {
-        return false;
+    IdString bel_type = getBelType(bel);
+    if (bel_type.in(id_TRELLIS_COMB, id_TRELLIS_FF, id_TRELLIS_RAMW)) {
+        return slices_compatible(tile_status.at(tile_index(bel)).lts);
     }
+    return true;
 }
 
 NEXTPNR_NAMESPACE_END

From 398b2ab569f5dee85ad7e2c2071267245fe99786 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 30 Mar 2023 03:24:03 +0100
Subject: [PATCH 332/712] bitstream emission update

---
 machxo2/arch.h       | 13 ++++++++
 machxo2/bitstream.cc | 79 +++++++++++++++++++++++++++++++-------------
 2 files changed, 69 insertions(+), 23 deletions(-)

diff --git a/machxo2/arch.h b/machxo2/arch.h
index 1eab9d1f96..18580a6dea 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -549,6 +549,19 @@ struct Arch : BaseArch<ArchRanges>
 
     IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); }
 
+    WireId get_wire_by_loc_basename(Location loc, std::string basename) const
+    {
+        WireId wireId;
+        wireId.location = loc;
+        for (int i = 0; i < tile_info(wireId)->wire_data.ssize(); i++) {
+            if (tile_info(wireId)->wire_data[i].name.get() == basename) {
+                wireId.index = i;
+                return wireId;
+            }
+        }
+        return WireId();
+    }
+
     // Pips
     PipId getPipByName(IdStringList name) const override;
     IdStringList getPipName(PipId pip) const override;
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index c67408ddbf..b2297be630 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -514,34 +514,67 @@ void write_bitstream(Context *ctx, std::string text_config_file)
             continue;
         }
         BelId bel = ci->bel;
-        if (ci->type == id_TRELLIS_SLICE) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-            std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get();
 
-            NPNR_ASSERT(slice.substr(0, 5) == "SLICE");
-            int int_index = slice[5] - 'A';
-            NPNR_ASSERT(int_index >= 0 && int_index < 4);
+        if (ci->type == id_TRELLIS_COMB) {
+            pool<IdString> used_phys_pins;
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+            int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+            std::string lc = std::to_string(z % 2);
+            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+            if (mode == "RAMW_BLOCK")
+                return;
+            int lut_init = int_or_default(ci->params, id_INITVAL);
+            cc.tiles[tname].add_enum(slice + ".MODE", mode);
+            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT", int_to_bitvector(lut_init, 16));
+            if (mode == "CCU2") {
+                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
+            } else {
+                // Don't interfere with cascade mux wiring
+                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
+            }
+            if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
+                cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
+                std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+                wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
+                cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+            }
+        } else if (ci->type == id_TRELLIS_FF) {
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+            int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+            std::string lc = std::to_string(z % 2);
 
-            int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
-            int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
-            cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
-            cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
             cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
             cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".SRMODE",
-                                     str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
-            cc.tiles[tname].add_enum(slice + ".CEMUX", intstr_or_default(ci->params, id_CEMUX, "1"));
-            cc.tiles[tname].add_enum("CLK" + std::to_string(int_index) + ".CLKMUX",
-                                     intstr_or_default(ci->params, id_CLKMUX, "0"));
-            cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRMUX",
-                                     str_or_default(ci->params, id_LSRMUX, "LSR"));
-            cc.tiles[tname].add_enum("LSR" + std::to_string(int_index) + ".LSRONMUX",
-                                     intstr_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
             cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
-            cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
-            cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
+            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
+            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+
+            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+
+            NetInfo *lsrnet = ci->getPort(id_LSR);
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
+                cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+                cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+            }
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
+                cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+                cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+            }
+
+            NetInfo *clknet = ci->getPort(id_CLK);
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
+                cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+            }
+            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
+                cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+            }
+        } else if (ci->type == id_TRELLIS_RAMW) {
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+            cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
+            cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
+            cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
         } else if (ci->type == id_TRELLIS_IO) {
             std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
             std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");

From 442142a47afd4005f15832bf40d35d3b2e6063d1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 13:17:37 +0200
Subject: [PATCH 333/712] typo fixes

---
 machxo2/arch.cc      | 2 +-
 machxo2/bitstream.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 32b188e652..5b6f6cae42 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -101,7 +101,7 @@ Arch::Arch(ArchArgs args) : args(args)
         auto &tile_data = chip_info->tile_info[i];
         ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr);
         for (auto &name : tile_data.tile_names) {
-            if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) {
+            if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC") == 0) {
                 // Is a logic tile
                 ts.lts = new LogicTileStatus();
                 break;
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index b2297be630..57eb87da3b 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -571,7 +571,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
                 cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
             }
         } else if (ci->type == id_TRELLIS_RAMW) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
+            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
             cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
             cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
             cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));

From 7f8518d9381fb847d9cf6e1f80f68b4a93c6c3c3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 13:38:02 +0200
Subject: [PATCH 334/712] Import lutperm data

---
 machxo2/arch.h           | 2 ++
 machxo2/facade_import.py | 6 ++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/machxo2/arch.h b/machxo2/arch.h
index 18580a6dea..ec5dd831ed 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -62,6 +62,8 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
     int16_t tile_type;
     int8_t pip_type;
     int8_t padding;
+    int16_t lutperm_flags;
+    int16_t padding2;
 });
 
 NPNR_PACKED_STRUCT(struct PipLocatorPOD {
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index e4822f23d3..e07c19213e 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -11,7 +11,7 @@
 parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
 parser.add_argument("device", type=str, help="target device")
 parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
-parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h (unused)")
+parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
 parser.add_argument("-L", "--libdir", type=str, action="append", help="extra Python library path")
 args = parser.parse_args()
 
@@ -268,6 +268,8 @@ def get_wire_name(loc, idx):
                 cls = arc.cls
                 bba.u8(arc.cls, "pip_type")
                 bba.u8(0, "padding")
+                bba.u16(arc.lutperm_flags, "lutperm_flags")
+                bba.u16(0, "padding2")
 
         if len(t.wires) > 0:
             for wire_idx in range(len(t.wires)):
@@ -481,7 +483,7 @@ def main():
     constids["PIO"] = constids["TRELLIS_IO"]
 
     chip = pytrellis.Chip(dev_names[args.device])
-    rg = pytrellis.make_optimized_chipdb(chip, split_slice_mode=True)
+    rg = pytrellis.make_optimized_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_pio_db(rg, args.device)

From 62ace582047c115ef59728cdc491e0920ec2207a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 15:24:53 +0200
Subject: [PATCH 335/712] add missing bind and lutperm

---
 machxo2/arch.cc      |  38 +++++++
 machxo2/arch.h       | 233 +++++++++++++++++++++++++++++++++++++++++++
 machxo2/bitstream.cc |  52 +++++++++-
 machxo2/constids.inc |   1 +
 machxo2/main.cc      |   3 +
 5 files changed, 326 insertions(+), 1 deletion(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 5b6f6cae42..9e638cbf8f 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -127,6 +127,29 @@ Arch::Arch(ArchArgs args) : args(args)
         y_ids.push_back(y_id);
         id_to_y[y_id] = i;
     }
+
+    wire_tile_vecidx.resize(chip_info->num_tiles, -1);
+    int n_wires = 0;
+    for (auto e : getWires()) {
+        if (e.index == 0) {
+            wire_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_wires;
+        }
+        n_wires++;
+    }
+    wire2net.resize(n_wires, nullptr);
+    wire_fanout.resize(n_wires, 0);
+
+    pip_tile_vecidx.resize(chip_info->num_tiles, -1);
+    int n_pips = 0;
+    for (auto e : getPips()) {
+        if (e.index == 0) {
+            pip_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_pips;
+        }
+        n_pips++;
+    }
+    pip2net.resize(n_pips, nullptr);
+
+    lutperm_allowed.resize(chip_info->width * chip_info->height * 4);
 }
 
 void Arch::list_devices()
@@ -395,6 +418,9 @@ bool Arch::place()
 bool Arch::route()
 {
     std::string router = str_or_default(settings, id_router, defaultRouter);
+
+    disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
+
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
@@ -503,4 +529,16 @@ std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row,
     return ret;
 }
 
+// -----------------------------------------------------------------------
+
+std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
+{
+    std::vector<std::pair<IdString, std::string>> ret;
+    auto &wi = tile_info(wire)->wire_data[wire.index];
+
+    ret.push_back(std::make_pair(id_TILE_WIRE_ID, stringf("%d", wi.tile_wire)));
+
+    return ret;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/arch.h b/machxo2/arch.h
index ec5dd831ed..2be987b741 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -66,6 +66,11 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
     int16_t padding2;
 });
 
+inline bool is_lutperm_pip(int16_t flags) { return flags & 0x4000; }
+inline uint8_t lutperm_lut(int16_t flags) { return (flags >> 4) & 0x7; }
+inline uint8_t lutperm_out(int16_t flags) { return (flags >> 2) & 0x3; }
+inline uint8_t lutperm_in(int16_t flags) { return flags & 0x3; }
+
 NPNR_PACKED_STRUCT(struct PipLocatorPOD {
     LocationPOD rel_loc;
     int32_t index;
@@ -383,6 +388,15 @@ struct Arch : BaseArch<ArchRanges>
     // inverse of the above for name->object mapping
     dict<IdString, int> id_to_x, id_to_y;
 
+    enum class LutPermRule
+    {
+        NONE,
+        CARRY,
+        ALL,
+    };
+    std::vector<LutPermRule> lutperm_allowed;
+    bool disable_router_lutperm = false;
+
     enum LogicBELType
     {
         BEL_COMB = 0,
@@ -415,6 +429,17 @@ struct Arch : BaseArch<ArchRanges>
 
     mutable std::vector<TileStatus> tile_status;
 
+    // faster replacements for base_pip2net, base_wire2net
+    // indexed by get_pip_vecidx()
+    std::vector<NetInfo *> pip2net;
+    // indexed by get_wire_vecidx()
+    std::vector<NetInfo *> wire2net;
+    std::vector<int> wire_fanout;
+    // We record the index=0 offset into pip2net for each tile, allowing us to
+    // calculate any PipId's offset from pip.index and pip.location
+    std::vector<int32_t> pip_tile_vecidx;
+    std::vector<int32_t> wire_tile_vecidx;
+
     // Helpers
     template <typename Id> const TileTypePOD *tile_info(Id &id) const
     {
@@ -470,6 +495,62 @@ struct Arch : BaseArch<ArchRanges>
         return IdStringList(ids);
     }
 
+    uint32_t getBelChecksum(BelId bel) const override { return bel.index; }
+
+    int get_slice_index(int x, int y, int slice) const
+    {
+        NPNR_ASSERT(slice >= 0 && slice < 4);
+        return (y * chip_info->width + x) * 4 + slice;
+    }
+
+    void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
+    {
+        CellInfo *act_cell = (old_cell == nullptr) ? new_cell : old_cell;
+        if (act_cell->type.in(id_TRELLIS_FF, id_TRELLIS_COMB, id_TRELLIS_RAMW)) {
+            LogicTileStatus *lts = tile_status.at(tile_index(bel)).lts;
+            NPNR_ASSERT(lts != nullptr);
+            int z = tile_info(bel)->bel_data[bel.index].z;
+            lts->slices[(z >> lc_idx_shift) / 2].dirty = true;
+            if (act_cell->type == id_TRELLIS_FF)
+                lts->tile_dirty = true; // because FF CLK/LSR signals are tile-wide
+            if (act_cell->type == id_TRELLIS_COMB && (act_cell->combInfo.flags & ArchCellInfo::COMB_LUTRAM))
+                lts->tile_dirty = true; // because RAM shares CLK/LSR signals with FFs
+            lts->cells[z] = new_cell;
+        }
+    }
+
+    void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(bel != BelId());
+        auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        NPNR_ASSERT(slot == nullptr);
+        slot = cell;
+        cell->bel = bel;
+        cell->belStrength = strength;
+        if (getBelType(bel) == id_TRELLIS_COMB) {
+            int flags = cell->combInfo.flags;
+            lutperm_allowed.at(
+                    get_slice_index(bel.location.x, bel.location.y, (getBelLocation(bel).z >> lc_idx_shift) / 2)) =
+                    (((flags & ArchCellInfo::COMB_LUTRAM) || (flags & ArchCellInfo::COMB_RAMW_BLOCK))
+                             ? LutPermRule::NONE
+                             : ((flags & ArchCellInfo::COMB_CARRY) ? LutPermRule::CARRY : LutPermRule::ALL));
+        }
+        update_bel(bel, nullptr, cell);
+        refreshUiBel(bel);
+    }
+
+    void unbindBel(BelId bel) override
+    {
+        NPNR_ASSERT(bel != BelId());
+        auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        NPNR_ASSERT(slot != nullptr);
+        update_bel(bel, slot, nullptr);
+        slot->bel = BelId();
+        slot->belStrength = STRENGTH_NONE;
+        slot = nullptr;
+        refreshUiBel(bel);
+    }
+
     Loc getBelLocation(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
@@ -484,6 +565,27 @@ struct Arch : BaseArch<ArchRanges>
     BelRange getBelsByTile(int x, int y) const override;
     bool getBelGlobalBuf(BelId bel) const override;
 
+    bool checkBelAvail(BelId bel) const override
+    {
+        NPNR_ASSERT(bel != BelId());
+        const CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot == nullptr;
+    }
+
+    CellInfo *getBoundBelCell(BelId bel) const override
+    {
+        NPNR_ASSERT(bel != BelId());
+        CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot;
+    }
+
+    CellInfo *getConflictingBelCell(BelId bel) const override
+    {
+        NPNR_ASSERT(bel != BelId());
+        CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
+        return slot;
+    }
+
     BelRange getBels() const override
     {
         BelRange range;
@@ -523,6 +625,60 @@ struct Arch : BaseArch<ArchRanges>
         return IdStringList(ids);
     }
 
+    IdString getWireType(WireId wire) const override
+    {
+        NPNR_ASSERT(wire != WireId());
+        IdString id;
+        id.index = tile_info(wire)->wire_data[wire.index].type;
+        return id;
+    }
+
+    std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const override;
+
+    uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
+
+    uint32_t get_wire_vecidx(const WireId &e) const
+    {
+        uint32_t tile = e.location.y * chip_info->width + e.location.x;
+        int32_t base = wire_tile_vecidx.at(tile);
+        NPNR_ASSERT(base != -1);
+        int32_t i = base + e.index;
+        return i;
+    }
+
+    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(wire != WireId());
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
+        NPNR_ASSERT(w2n_entry == nullptr);
+        net->wires[wire].pip = PipId();
+        net->wires[wire].strength = strength;
+        w2n_entry = net;
+        this->refreshUiWire(wire);
+    }
+    void unbindWire(WireId wire) override
+    {
+        NPNR_ASSERT(wire != WireId());
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
+        NPNR_ASSERT(w2n_entry != nullptr);
+
+        auto &net_wires = w2n_entry->wires;
+        auto it = net_wires.find(wire);
+        NPNR_ASSERT(it != net_wires.end());
+
+        auto pip = it->second.pip;
+        if (pip != PipId()) {
+            pip2net.at(get_pip_vecidx(pip)) = nullptr;
+            wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
+        }
+
+        net_wires.erase(it);
+        w2n_entry = nullptr;
+        this->refreshUiWire(wire);
+    }
+    virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
+    NetInfo *getBoundWireNet(WireId wire) const override { return wire2net.at(get_wire_vecidx(wire)); }
+
     DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0.01); }
 
     WireRange getWires() const override
@@ -568,6 +724,78 @@ struct Arch : BaseArch<ArchRanges>
     PipId getPipByName(IdStringList name) const override;
     IdStringList getPipName(PipId pip) const override;
 
+    uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
+
+    uint32_t get_pip_vecidx(const PipId &e) const
+    {
+        uint32_t tile = e.location.y * chip_info->width + e.location.x;
+        int32_t base = pip_tile_vecidx.at(tile);
+        NPNR_ASSERT(base != -1);
+        int32_t i = base + e.index;
+        return i;
+    }
+
+    void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
+    {
+        NPNR_ASSERT(pip != PipId());
+        wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]++;
+
+        auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
+        NPNR_ASSERT(p2n_entry == nullptr);
+        p2n_entry = net;
+
+        WireId dst = this->getPipDstWire(pip);
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
+        NPNR_ASSERT(w2n_entry == nullptr);
+        w2n_entry = net;
+        net->wires[dst].pip = pip;
+        net->wires[dst].strength = strength;
+    }
+
+    void unbindPip(PipId pip) override
+    {
+        NPNR_ASSERT(pip != PipId());
+        wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
+
+        auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
+        NPNR_ASSERT(p2n_entry != nullptr);
+        WireId dst = this->getPipDstWire(pip);
+
+        auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
+        NPNR_ASSERT(w2n_entry != nullptr);
+        w2n_entry = nullptr;
+
+        p2n_entry->wires.erase(dst);
+        p2n_entry = nullptr;
+    }
+    bool is_pip_blocked(PipId pip) const
+    {
+        auto &pip_data = tile_info(pip)->pip_data[pip.index];
+        int lp = pip_data.lutperm_flags;
+        if (is_lutperm_pip(lp)) {
+            if (disable_router_lutperm)
+                return true;
+            auto rule = lutperm_allowed.at(get_slice_index(pip.location.x, pip.location.y, lutperm_lut(lp) / 2));
+            if (rule == LutPermRule::NONE) {
+                // Permutation not allowed
+                return true;
+            } else if (rule == LutPermRule::CARRY) {
+                // Can swap A/B and C/D only
+                int i = lutperm_out(lp), j = lutperm_in(lp);
+                if ((i / 2) != (j / 2))
+                    return true;
+            }
+        }
+        return false;
+    }
+    bool checkPipAvail(PipId pip) const override { return (getBoundPipNet(pip) == nullptr) && !is_pip_blocked(pip); }
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
+    {
+        NetInfo *bound_net = getBoundPipNet(pip);
+        return (bound_net == nullptr || bound_net == net) && !is_pip_blocked(pip);
+    }
+    NetInfo *getBoundPipNet(PipId pip) const override { return pip2net.at(get_pip_vecidx(pip)); }
+
     AllPipRange getPips() const override
     {
         AllPipRange range;
@@ -648,6 +876,11 @@ struct Arch : BaseArch<ArchRanges>
         NPNR_ASSERT_FALSE("failed to find Pip tile");
     }
 
+    std::string get_pip_tiletype(PipId pip) const
+    {
+        return chip_info->tiletype_names[tile_info(pip)->pip_data[pip.index].tile_type].get();
+    }
+
     // Delay
     delay_t estimateDelay(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 57eb87da3b..529c5cc984 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -404,6 +404,55 @@ static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
     }
 }
 
+static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
+{
+    std::array<std::vector<unsigned>, 4> phys_to_log;
+    const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
+    for (unsigned i = 0; i < 4; i++) {
+        WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
+        for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+            if (!ctx->getBoundPipNet(pip))
+                continue;
+            unsigned lp = ctx->tile_info(pip)->pip_data[pip.index].lutperm_flags;
+            if (!is_lutperm_pip(lp)) { // non-permuting
+                phys_to_log[i].push_back(i);
+            } else { // permuting
+                unsigned from_pin = lutperm_in(lp);
+                unsigned to_pin = lutperm_out(lp);
+                NPNR_ASSERT(to_pin == i);
+                phys_to_log[from_pin].push_back(i);
+            }
+        }
+    }
+    for (unsigned i = 0; i < 4; i++)
+        if (!phys_to_log.at(i).empty())
+            used_phys_pins.insert(ports.at(i));
+    if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
+        // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
+        for (unsigned i = 0; i < 4; i++) {
+            if (!phys_to_log.at(i).empty())
+                continue;
+            for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
+                if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
+                    phys_to_log.at(i).push_back(j);
+            }
+        }
+    }
+    unsigned permuted_init = 0;
+    for (unsigned i = 0; i < 16; i++) {
+        unsigned log_idx = 0;
+        for (unsigned j = 0; j < 4; j++) {
+            if ((i >> j) & 0x1) {
+                for (auto log_pin : phys_to_log[j])
+                    log_idx |= (1 << log_pin);
+            }
+        }
+        if ((orig_init >> log_idx) & 0x1)
+            permuted_init |= (1 << i);
+    }
+    return permuted_init;
+}
+
 static std::vector<bool> int_to_bitvector(int val, int size)
 {
     std::vector<bool> bv;
@@ -526,7 +575,8 @@ void write_bitstream(Context *ctx, std::string text_config_file)
                 return;
             int lut_init = int_or_default(ci->params, id_INITVAL);
             cc.tiles[tname].add_enum(slice + ".MODE", mode);
-            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT", int_to_bitvector(lut_init, 16));
+            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
+                                    int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16));
             if (mode == "CCU2") {
                 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
             } else {
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 0f5c2e10ef..adb7254d35 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -126,6 +126,7 @@ X(NOM_FREQ)
 X(VCC)
 
 X(WIRE_TYPE_NONE)
+X(TILE_WIRE_ID)
 
 X(machxo2)
 X(pack)
diff --git a/machxo2/main.cc b/machxo2/main.cc
index 283bc59c16..f21f8c3bc7 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -51,6 +51,7 @@ po::options_description MachXO2CommandHandler::getArchOptions()
     specific.add_options()("list-devices", "list all supported device names");
     specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
     // specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+    specific.add_options()("disable-router-lutperm", "don't allow the router to permute LUT inputs");
 
     return specific;
 }
@@ -76,6 +77,8 @@ std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string,
     }
     chipArgs.device = vm["device"].as<std::string>();
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
+    if (vm.count("disable-router-lutperm"))
+        ctx->settings[ctx->id("arch.disable_router_lutperm")] = 1;
     return ctx;
 }
 

From ca3d32e5acc22695f7d75787f6f4fb21a056f368 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 18:18:52 +0200
Subject: [PATCH 336/712] make source more inline with ecp5

---
 machxo2/arch.cc    | 209 ++++++++++++++++++++++++++++++---------------
 machxo2/arch.h     | 189 +++++++++++++++++++++-------------------
 machxo2/archdefs.h |  26 ++++--
 machxo2/pack.cc    |   2 +-
 4 files changed, 263 insertions(+), 163 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 9e638cbf8f..be6d81a15b 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -201,27 +201,6 @@ BelId Arch::getBelByName(IdStringList name) const
     return BelId();
 }
 
-BelId Arch::getBelByLocation(Loc loc) const
-{
-    BelId ret;
-
-    if (loc.x >= chip_info->width || loc.y >= chip_info->height)
-        return BelId();
-
-    ret.location.x = loc.x;
-    ret.location.y = loc.y;
-
-    const TileTypePOD *loci = tile_info(ret);
-    for (int i = 0; i < loci->bel_data.ssize(); i++) {
-        if (loci->bel_data[i].z == loc.z) {
-            ret.index = i;
-            return ret;
-        }
-    }
-
-    return BelId();
-}
-
 BelRange Arch::getBelsByTile(int x, int y) const
 {
     BelRange br;
@@ -239,24 +218,21 @@ BelRange Arch::getBelsByTile(int x, int y) const
     return br;
 }
 
-bool Arch::getBelGlobalBuf(BelId bel) const { return false; }
-
 WireId Arch::getBelPinWire(BelId bel, IdString pin) const
 {
+    WireId ret;
+
     NPNR_ASSERT(bel != BelId());
 
     for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
         if (bw.port == pin.index) {
-            WireId ret;
-
             ret.location.x = bw.rel_wire_loc.x;
             ret.location.y = bw.rel_wire_loc.y;
             ret.index = bw.wire_index;
-
-            return ret;
+            break;
         }
 
-    return WireId();
+    return ret;
 }
 
 PortType Arch::getBelPinType(BelId bel, IdString pin) const
@@ -270,35 +246,6 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
     return PORT_INOUT;
 }
 
-std::vector<IdString> Arch::getBelPins(BelId bel) const
-{
-    std::vector<IdString> ret;
-    NPNR_ASSERT(bel != BelId());
-
-    for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
-        IdString id;
-        id.index = bw.port;
-        ret.push_back(id);
-    }
-
-    return ret;
-}
-
-// ---------------------------------------------------------------
-
-BelId Arch::getPackagePinBel(const std::string &pin) const
-{
-    for (auto &ppin : package_info->pin_data) {
-        if (ppin.name.get() == pin) {
-            BelId bel;
-            bel.location = ppin.abs_loc;
-            bel.index = ppin.bel_index;
-            return bel;
-        }
-    }
-    return BelId();
-}
-
 // ---------------------------------------------------------------
 
 WireId Arch::getWireByName(IdStringList name) const
@@ -362,6 +309,56 @@ IdStringList Arch::getPipName(PipId pip) const
 
 // ---------------------------------------------------------------
 
+BelId Arch::get_package_pin_bel(const std::string &pin) const
+{
+    for (auto &ppin : package_info->pin_data) {
+        if (ppin.name.get() == pin) {
+            BelId bel;
+            bel.location = ppin.abs_loc;
+            bel.index = ppin.bel_index;
+            return bel;
+        }
+    }
+    return BelId();
+}
+
+std::vector<IdString> Arch::getBelPins(BelId bel) const
+{
+    std::vector<IdString> ret;
+    NPNR_ASSERT(bel != BelId());
+
+    for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
+        IdString id;
+        id.index = bw.port;
+        ret.push_back(id);
+    }
+
+    return ret;
+}
+
+BelId Arch::getBelByLocation(Loc loc) const
+{
+    BelId ret;
+
+    if (loc.x >= chip_info->width || loc.y >= chip_info->height)
+        return BelId();
+
+    ret.location.x = loc.x;
+    ret.location.y = loc.y;
+
+    const TileTypePOD *loci = tile_info(ret);
+    for (int i = 0; i < loci->bel_data.ssize(); i++) {
+        if (loci->bel_data[i].z == loc.z) {
+            ret.index = i;
+            return ret;
+        }
+    }
+
+    return BelId();
+}
+
+// ---------------------------------------------------------------
+
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     // Taxicab distance multiplied by pipDelay (0.01) and fake wireDelay (0.01).
@@ -370,6 +367,16 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
 }
 
+BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
+{
+    BoundingBox bb;
+    bb.x0 = std::min(src.location.x, dst.location.x);
+    bb.y0 = std::min(src.location.y, dst.location.y);
+    bb.x1 = std::max(src.location.x, dst.location.x);
+    bb.y1 = std::max(src.location.y, dst.location.y);
+    return bb;
+}
+
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
     NPNR_UNUSED(src_pin);
@@ -383,16 +390,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
            (0.01 + 0.01);
 }
 
-BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
-{
-    BoundingBox bb;
-    bb.x0 = std::min(src.location.x, dst.location.x);
-    bb.y0 = std::min(src.location.y, dst.location.y);
-    bb.x1 = std::max(src.location.x, dst.location.x);
-    bb.y1 = std::max(src.location.y, dst.location.y);
-    return bb;
-}
-
 // ---------------------------------------------------------------
 
 bool Arch::place()
@@ -508,6 +505,16 @@ DecalXY Arch::getPipDecal(PipId pip) const
     return decalxy;
 };
 
+DecalXY Arch::getGroupDecal(GroupId group) const
+{
+    DecalXY decalxy;
+    decalxy.decal.type = DecalId::TYPE_GROUP;
+    decalxy.decal.location = group.location;
+    decalxy.decal.z = group.type;
+    decalxy.decal.active = true;
+    return decalxy;
+}
+
 // ---------------------------------------------------------------
 
 const std::string Arch::defaultPlacer = "heap";
@@ -517,8 +524,6 @@ const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
-bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; }
-
 std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row, int col)
 {
     std::vector<std::pair<std::string, std::string>> ret;
@@ -531,6 +536,72 @@ std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row,
 
 // -----------------------------------------------------------------------
 
+GroupId Arch::getGroupByName(IdStringList name) const
+{
+    for (auto g : getGroups())
+        if (getGroupName(g) == name)
+            return g;
+    return GroupId();
+}
+
+IdStringList Arch::getGroupName(GroupId group) const
+{
+    std::string suffix;
+
+    switch (group.type) {
+    case GroupId::TYPE_SWITCHBOX:
+        suffix = "switchbox";
+        break;
+    default:
+        return IdStringList();
+    }
+
+    std::array<IdString, 3> ids{x_ids.at(group.location.x), y_ids.at(group.location.y), id(suffix)};
+    return IdStringList(ids);
+}
+
+std::vector<GroupId> Arch::getGroups() const
+{
+    std::vector<GroupId> ret;
+
+    for (int y = 1; y < chip_info->height - 1; y++) {
+        for (int x = 1; x < chip_info->width - 1; x++) {
+            GroupId group;
+            group.type = GroupId::TYPE_SWITCHBOX;
+            group.location.x = x;
+            group.location.y = y;
+            ret.push_back(group);
+        }
+    }
+    return ret;
+}
+
+std::vector<BelId> Arch::getGroupBels(GroupId group) const
+{
+    std::vector<BelId> ret;
+    return ret;
+}
+
+std::vector<WireId> Arch::getGroupWires(GroupId group) const
+{
+    std::vector<WireId> ret;
+    return ret;
+}
+
+std::vector<PipId> Arch::getGroupPips(GroupId group) const
+{
+    std::vector<PipId> ret;
+    return ret;
+}
+
+std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
+{
+    std::vector<GroupId> ret;
+    return ret;
+}
+
+// -----------------------------------------------------------------------
+
 std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 2be987b741..1615016894 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -149,8 +149,6 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
 
 /************************ End of chipdb section. ************************/
 
-// Iterators
-// Iterate over Bels across tiles.
 struct BelIterator
 {
     const ChipInfoPOD *chip;
@@ -200,7 +198,8 @@ struct BelRange
     BelIterator end() const { return e; }
 };
 
-// Iterate over Downstream/Upstream Bels for a Wire.
+// -----------------------------------------------------------------------
+
 struct BelPinIterator
 {
     const BelPortPOD *ptr = nullptr;
@@ -225,7 +224,8 @@ struct BelPinRange
     BelPinIterator end() const { return e; }
 };
 
-// Iterator over Wires across tiles.
+// -----------------------------------------------------------------------
+
 struct WireIterator
 {
     const ChipInfoPOD *chip;
@@ -275,7 +275,8 @@ struct WireRange
     WireIterator end() const { return e; }
 };
 
-// Iterator over Pips across tiles.
+// -----------------------------------------------------------------------
+
 struct AllPipIterator
 {
     const ChipInfoPOD *chip;
@@ -325,7 +326,8 @@ struct AllPipRange
     AllPipIterator end() const { return e; }
 };
 
-// Iterate over Downstream/Upstream Pips for a Wire.
+// -----------------------------------------------------------------------
+
 struct PipIterator
 {
 
@@ -383,11 +385,6 @@ struct Arch : BaseArch<ArchRanges>
 
     mutable dict<IdStringList, PipId> pip_by_name;
 
-    // fast access to  X and Y IdStrings for building object names
-    std::vector<IdString> x_ids, y_ids;
-    // inverse of the above for name->object mapping
-    dict<IdString, int> id_to_x, id_to_y;
-
     enum class LutPermRule
     {
         NONE,
@@ -397,6 +394,9 @@ struct Arch : BaseArch<ArchRanges>
     std::vector<LutPermRule> lutperm_allowed;
     bool disable_router_lutperm = false;
 
+    // For fast, incremental validity checking of split SLICE
+
+    // BEL z-position lookup, x-ored with (index in tile) << 2
     enum LogicBELType
     {
         BEL_COMB = 0,
@@ -427,8 +427,6 @@ struct Arch : BaseArch<ArchRanges>
         ~TileStatus() { delete lts; }
     };
 
-    mutable std::vector<TileStatus> tile_status;
-
     // faster replacements for base_pip2net, base_wire2net
     // indexed by get_pip_vecidx()
     std::vector<NetInfo *> pip2net;
@@ -440,53 +438,49 @@ struct Arch : BaseArch<ArchRanges>
     std::vector<int32_t> pip_tile_vecidx;
     std::vector<int32_t> wire_tile_vecidx;
 
-    // Helpers
-    template <typename Id> const TileTypePOD *tile_info(Id &id) const
-    {
-        return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
-    }
-
-    int get_bel_flat_index(BelId bel) const
-    {
-        return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
-    }
-
-    template <typename Id> inline int tile_index(Id id) const
-    {
-        return id.location.y * chip_info->width + id.location.x;
-    }
-
-    // ---------------------------------------------------------------
-    // Common Arch API. Every arch must provide the following methods.
+    // fast access to  X and Y IdStrings for building object names
+    std::vector<IdString> x_ids, y_ids;
+    // inverse of the above for name->object mapping
+    dict<IdString, int> id_to_x, id_to_y;
 
-    // General
     ArchArgs args;
     Arch(ArchArgs args);
 
     static void list_devices();
 
     std::string getChipName() const override;
-    // Extra helper
     std::string get_full_chip_name() const;
 
     IdString archId() const override { return id_machxo2; }
     ArchArgs archArgs() const override { return args; }
     IdString archArgsToId(ArchArgs args) const override;
 
-    static const int max_loc_bels = 20;
+    // -------------------------------------------------
 
-    int getGridDimX() const override { return chip_info->width; }
-    int getGridDimY() const override { return chip_info->height; }
-    int getTileBelDimZ(int x, int y) const override { return max_loc_bels; }
+    static const int max_loc_bels = 32;
+
+    int getGridDimX() const override { return chip_info->width; };
+    int getGridDimY() const override { return chip_info->height; };
+    int getTileBelDimZ(int, int) const override { return max_loc_bels; };
     // TODO: Make more precise? The CENTER MUX having config bits across
     // tiles can complicate this?
-    int getTilePipDimZ(int x, int y) const override { return 2; }
-
+    int getTilePipDimZ(int, int) const override { return 2; };
     char getNameDelimiter() const override { return '/'; }
 
-    // Bels
+    // -------------------------------------------------
+
     BelId getBelByName(IdStringList name) const override;
 
+    template <typename Id> const TileTypePOD *tile_info(Id &id) const
+    {
+        return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
+    }
+
+    template <typename Id> inline int tile_index(Id id) const
+    {
+        return id.location.y * chip_info->width + id.location.x;
+    }
+
     IdStringList getBelName(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
@@ -563,7 +557,8 @@ struct Arch : BaseArch<ArchRanges>
 
     BelId getBelByLocation(Loc loc) const override;
     BelRange getBelsByTile(int x, int y) const override;
-    bool getBelGlobalBuf(BelId bel) const override;
+
+    bool getBelGlobalBuf(BelId bel) const override { return false; }
 
     bool checkBelAvail(BelId bel) const override
     {
@@ -608,13 +603,22 @@ struct Arch : BaseArch<ArchRanges>
     }
 
     WireId getBelPinWire(BelId bel, IdString pin) const override;
-    PortType getBelPinType(BelId bel, IdString pin) const override;
+
+    BelPinRange getWireBelPins(WireId wire) const override
+    {
+        BelPinRange range;
+        NPNR_ASSERT(wire != WireId());
+        range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin();
+        range.b.wire_loc = wire.location;
+        range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end();
+        range.e.wire_loc = wire.location;
+        return range;
+    }
+
     std::vector<IdString> getBelPins(BelId bel) const override;
 
-    // Package
-    BelId getPackagePinBel(const std::string &pin) const;
+    // -------------------------------------------------
 
-    // Wires
     WireId getWireByName(IdStringList name) const override;
 
     IdStringList getWireName(WireId wire) const override
@@ -694,17 +698,6 @@ struct Arch : BaseArch<ArchRanges>
         return range;
     }
 
-    BelPinRange getWireBelPins(WireId wire) const override
-    {
-        BelPinRange range;
-        NPNR_ASSERT(wire != WireId());
-        range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin();
-        range.b.wire_loc = wire.location;
-        range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end();
-        range.e.wire_loc = wire.location;
-        return range;
-    }
-
     IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); }
 
     WireId get_wire_by_loc_basename(Location loc, std::string basename) const
@@ -720,7 +713,8 @@ struct Arch : BaseArch<ArchRanges>
         return WireId();
     }
 
-    // Pips
+    // -------------------------------------------------
+
     PipId getPipByName(IdStringList name) const override;
     IdStringList getPipName(PipId pip) const override;
 
@@ -809,18 +803,6 @@ struct Arch : BaseArch<ArchRanges>
         return range;
     }
 
-    Loc getPipLocation(PipId pip) const override
-    {
-        Loc loc;
-        loc.x = pip.location.x;
-        loc.y = pip.location.y;
-
-        // FIXME: Some Pip's config bits span across tiles. Will Z
-        // be affected by this?
-        loc.z = 0;
-        return loc;
-    }
-
     WireId getPipSrcWire(PipId pip) const override
     {
         WireId wire;
@@ -863,9 +845,6 @@ struct Arch : BaseArch<ArchRanges>
         return range;
     }
 
-    // Extra Pip helpers.
-    int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
-
     std::string get_pip_tilename(PipId pip) const
     {
         auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
@@ -881,32 +860,65 @@ struct Arch : BaseArch<ArchRanges>
         return chip_info->tiletype_names[tile_info(pip)->pip_data[pip.index].tile_type].get();
     }
 
-    // Delay
+    Loc getPipLocation(PipId pip) const override
+    {
+        Loc loc;
+        loc.x = pip.location.x;
+        loc.y = pip.location.y;
+        loc.z = 0;
+        return loc;
+    }
+
+    int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
+
+    BelId get_package_pin_bel(const std::string &pin) const;
+    //std::string get_bel_package_pin(BelId bel) const;
+    //int get_pio_bel_bank(BelId bel) const;
+    // For getting GCLK, PLL, Vref, etc, pins
+    //std::string get_pio_function_name(BelId bel) const;
+    //BelId get_pio_by_function_name(const std::string &name) const;
+
+    PortType getBelPinType(BelId bel, IdString pin) const override;
+
+    // -------------------------------------------------
+
+    GroupId getGroupByName(IdStringList name) const override;
+    IdStringList getGroupName(GroupId group) const override;
+    std::vector<GroupId> getGroups() const override;
+    std::vector<BelId> getGroupBels(GroupId group) const override;
+    std::vector<WireId> getGroupWires(GroupId group) const override;
+    std::vector<PipId> getGroupPips(GroupId group) const override;
+    std::vector<GroupId> getGroupGroups(GroupId group) const override;
+
+    // -------------------------------------------------
+
     delay_t estimateDelay(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
     delay_t getDelayEpsilon() const override { return 0.001; }
     delay_t getRipupDelayPenalty() const override { return 0.015; }
     float getDelayNS(delay_t v) const override { return v; }
-
     delay_t getDelayFromNS(float ns) const override { return ns; }
-
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
+    //bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
-    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
+    // -------------------------------------------------
 
-    // Flow
     bool pack() override;
     bool place() override;
     bool route() override;
 
-    // Graphics
+    // -------------------------------------------------
+
     std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
 
     DecalXY getBelDecal(BelId bel) const override;
     DecalXY getWireDecal(WireId wire) const override;
     DecalXY getPipDecal(PipId pip) const override;
+    DecalXY getGroupDecal(GroupId group) const override;
 
-    // Placer
+    // -------------------------------------------------
+    // Placement validity checks
     bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
 
     // Helper function for above
@@ -915,15 +927,6 @@ struct Arch : BaseArch<ArchRanges>
     void assign_arch_info_for_cell(CellInfo *ci);
     void assignArchInfo() override;
 
-    static const std::string defaultPlacer;
-    static const std::vector<std::string> availablePlacers;
-    static const std::string defaultRouter;
-    static const std::vector<std::string> availableRouters;
-
-    // ---------------------------------------------------------------
-    // Internal usage
-    bool cells_compatible(const CellInfo **cells, int count) const;
-
     std::vector<std::pair<std::string, std::string>> get_tiles_at_loc(int row, int col);
     std::string get_tile_by_type_loc(int row, int col, std::string type) const
     {
@@ -956,6 +959,16 @@ struct Arch : BaseArch<ArchRanges>
         }
         NPNR_ASSERT_FALSE_STR("no tile with type " + type);
     }
+
+    static const std::string defaultPlacer;
+    static const std::vector<std::string> availablePlacers;
+    static const std::string defaultRouter;
+    static const std::vector<std::string> availableRouters;
+
+    mutable std::vector<TileStatus> tile_status;
+
+    // -------------------------------------------------
+
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
index 4809324a4f..0152b7ac01 100644
--- a/machxo2/archdefs.h
+++ b/machxo2/archdefs.h
@@ -30,6 +30,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 typedef float delay_t;
 
+// -----------------------------------------------------------------------
+
 // https://bugreports.qt.io/browse/QTBUG-80789
 
 #ifndef Q_MOC_RUN
@@ -107,6 +109,22 @@ struct PipId
     unsigned int hash() const { return mkhash(location.hash(), index); }
 };
 
+typedef IdString BelBucketId;
+
+struct GroupId
+{
+    enum : int8_t
+    {
+        TYPE_NONE,
+        TYPE_SWITCHBOX
+    } type = TYPE_NONE;
+    Location location;
+
+    bool operator==(const GroupId &other) const { return (type == other.type) && (location == other.location); }
+    bool operator!=(const GroupId &other) const { return (type != other.type) || (location != other.location); }
+    unsigned int hash() const { return mkhash(location.hash(), int(type)); }
+};
+
 struct DecalId
 {
     enum
@@ -131,14 +149,13 @@ struct DecalId
     unsigned int hash() const { return mkhash(location.hash(), mkhash(z, int(type))); }
 };
 
-typedef IdString GroupId;
-typedef IdString BelBucketId;
-typedef IdString ClusterId;
-
 struct ArchNetInfo
 {
 };
 
+typedef IdString ClusterId;
+
+struct CellInfo;
 struct NetInfo;
 
 struct ArchCellInfo : BaseClusterInfo
@@ -197,5 +214,4 @@ struct ArchCellInfo : BaseClusterInfo
 };
 
 NEXTPNR_NAMESPACE_END
-
 #endif /* MACHXO2_ARCHDEFS_H */
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index b6aa8be684..78becc189c 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -381,7 +381,7 @@ class Ecp5Packer
                     auto loc_attr = trio->attrs.find(id_LOC);
                     if (loc_attr != trio->attrs.end()) {
                         std::string pin = loc_attr->second.as_string();
-                        BelId pinBel = ctx->getPackagePinBel(pin);
+                        BelId pinBel = ctx->get_package_pin_bel(pin);
                         if (pinBel == BelId()) {
                             log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
                                       trio->name.c_str(ctx), pin.c_str(), ctx->package_name);

From 153144022f12d2c4d9232a9d1107083c2f379121 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 19:04:11 +0200
Subject: [PATCH 337/712] More of making it inline

---
 machxo2/arch.cc       |  34 ++--
 machxo2/arch_place.cc | 190 +++++++++++++++++++++++
 machxo2/cells.cc      |  41 -----
 machxo2/cells.h       |  37 ++---
 machxo2/pack.cc       | 349 ++++++++++++++++++++++--------------------
 5 files changed, 413 insertions(+), 238 deletions(-)
 create mode 100644 machxo2/arch_place.cc

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index be6d81a15b..55d3a8459d 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -395,21 +395,33 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 bool Arch::place()
 {
     std::string placer = str_or_default(settings, id_placer, defaultPlacer);
-    if (placer == "sa") {
-        bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
-        getCtx()->settings[id_place] = 1;
-        archInfoToAttributes();
-        return retVal;
-    } else if (placer == "heap") {
+
+    if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
+        cfg.criticalityExponent = 4;
         cfg.ioBufTypes.insert(id_TRELLIS_IO);
-        bool retVal = placer_heap(getCtx(), cfg);
-        getCtx()->settings[id_place] = 1;
-        archInfoToAttributes();
-        return retVal;
+
+        cfg.cellGroups.emplace_back();
+        cfg.cellGroups.back().insert(id_TRELLIS_COMB);
+        cfg.cellGroups.back().insert(id_TRELLIS_FF);
+        cfg.cellGroups.back().insert(id_TRELLIS_RAMW);
+        cfg.placeAllAtOnce = true;
+
+        cfg.beta = 0.75;
+
+        if (!placer_heap(getCtx(), cfg))
+            return false;
+    } else if (placer == "sa") {
+        if (!placer1(getCtx(), Placer1Cfg(getCtx())))
+            return false;
     } else {
         log_error("MachXO2 architecture does not support placer '%s'\n", placer.c_str());
     }
+
+    getCtx()->settings[id_place] = 1;
+
+    archInfoToAttributes();
+    return true;
 }
 
 bool Arch::route()
@@ -418,6 +430,8 @@ bool Arch::route()
 
     disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
 
+    assignArchInfo();
+
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
new file mode 100644
index 0000000000..1ffb99105a
--- /dev/null
+++ b/machxo2/arch_place.cc
@@ -0,0 +1,190 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "cells.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "timing.h"
+#include "util.h"
+NEXTPNR_NAMESPACE_BEGIN
+
+inline NetInfo *port_or_nullptr(const CellInfo *cell, IdString name)
+{
+    auto found = cell->ports.find(name);
+    if (found == cell->ports.end())
+        return nullptr;
+    return found->second.net;
+}
+
+bool Arch::slices_compatible(LogicTileStatus *lts) const
+{
+    if (lts == nullptr)
+        return true;
+    for (int sl = 0; sl < 4; sl++) {
+        if (!lts->slices[sl].dirty) {
+            if (!lts->slices[sl].valid)
+                return false;
+            continue;
+        }
+        lts->slices[sl].dirty = false;
+        lts->slices[sl].valid = false;
+        bool found_ff = false;
+        uint8_t last_ff_flags = 0;
+        IdString last_ce_sig;
+        bool ramw_used = false;
+        if (sl == 2 && lts->cells[((sl * 2) << lc_idx_shift) | BEL_RAMW] != nullptr)
+            ramw_used = true;
+        for (int l = 0; l < 2; l++) {
+            bool comb_m_used = false;
+            CellInfo *comb = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_COMB];
+            if (comb != nullptr) {
+                uint8_t flags = comb->combInfo.flags;
+                if (ramw_used && !(flags & ArchCellInfo::COMB_RAMW_BLOCK))
+                    return false;
+                if (flags & ArchCellInfo::COMB_MUX5) {
+                    // MUX5 uses M signal and must be in LC 0
+                    comb_m_used = true;
+                    if (l != 0)
+                        return false;
+                }
+                if (flags & ArchCellInfo::COMB_MUX6) {
+                    // MUX6+ uses M signal and must be in LC 1
+                    comb_m_used = true;
+                    if (l != 1)
+                        return false;
+                    if (comb->combInfo.mux_fxad != nullptr &&
+                        (comb->combInfo.mux_fxad->combInfo.flags & ArchCellInfo::COMB_MUX5)) {
+                        // LUT6 structure must be rooted at SLICE 0 or 2
+                        if (sl != 0 && sl != 2)
+                            return false;
+                    }
+                }
+                // LUTRAM must be in bottom two SLICEs only
+                if ((flags & ArchCellInfo::COMB_LUTRAM) && (sl > 1))
+                    return false;
+                if (l == 1) {
+                    // Carry usage must be the same for LCs 0 and 1 in a SLICE
+                    CellInfo *comb0 = lts->cells[((sl * 2 + 0) << lc_idx_shift) | BEL_COMB];
+                    if (comb0 &&
+                        ((comb0->combInfo.flags & ArchCellInfo::COMB_CARRY) != (flags & ArchCellInfo::COMB_CARRY)))
+                        return false;
+                }
+            }
+
+            CellInfo *ff = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                uint8_t flags = ff->ffInfo.flags;
+                if (comb_m_used && (flags & ArchCellInfo::FF_M_USED))
+                    return false;
+                if (found_ff) {
+                    if ((flags & ArchCellInfo::FF_GSREN) != (last_ff_flags & ArchCellInfo::FF_GSREN))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CECONST) != (last_ff_flags & ArchCellInfo::FF_CECONST))
+                        return false;
+                    if ((flags & ArchCellInfo::FF_CEINV) != (last_ff_flags & ArchCellInfo::FF_CEINV))
+                        return false;
+                    if (ff->ffInfo.ce_sig != last_ce_sig)
+                        return false;
+                } else {
+                    found_ff = true;
+                    last_ff_flags = flags;
+                    last_ce_sig = ff->ffInfo.ce_sig;
+                }
+            }
+        }
+
+        lts->slices[sl].valid = true;
+    }
+    if (lts->tile_dirty) {
+        bool found_global_ff = false;
+        bool found_global_dpram = false;
+        bool global_lsrinv = false;
+        bool global_clkinv = false;
+        bool global_async = false;
+
+        IdString clk_sig, lsr_sig;
+
+        lts->tile_dirty = false;
+        lts->tile_valid = false;
+
+#define CHECK_EQUAL(x, y)                                                                                              \
+    do {                                                                                                               \
+        if ((x) != (y))                                                                                                \
+            return false;                                                                                              \
+    } while (0)
+        for (int i = 0; i < 8; i++) {
+            if (i < 4) {
+                // DPRAM
+                CellInfo *comb = lts->cells[(i << lc_idx_shift) | BEL_COMB];
+                if (comb != nullptr && (comb->combInfo.flags & ArchCellInfo::COMB_LUTRAM)) {
+                    if (found_global_dpram) {
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV), global_clkinv);
+                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV), global_lsrinv);
+                    } else {
+                        global_clkinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV);
+                        global_lsrinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV);
+                        found_global_dpram = true;
+                    }
+                }
+            }
+            // FF
+            CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
+            if (ff != nullptr) {
+                if (found_global_dpram) {
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                }
+                if (found_global_ff) {
+                    CHECK_EQUAL(ff->ffInfo.clk_sig, clk_sig);
+                    CHECK_EQUAL(ff->ffInfo.lsr_sig, lsr_sig);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
+                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC), global_async);
+
+                } else {
+                    clk_sig = ff->ffInfo.clk_sig;
+                    lsr_sig = ff->ffInfo.lsr_sig;
+                    global_clkinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV);
+                    global_lsrinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV);
+                    global_async = bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC);
+                    found_global_ff = true;
+                }
+            }
+        }
+#undef CHECK_EQUAL
+        lts->tile_valid = true;
+    } else {
+        if (!lts->tile_valid)
+            return false;
+    }
+
+    return true;
+}
+
+bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
+{
+    IdString bel_type = getBelType(bel);
+    if (bel_type.in(id_TRELLIS_COMB, id_TRELLIS_FF, id_TRELLIS_RAMW)) {
+        return slices_compatible(tile_status.at(tile_index(bel)).lts);
+    }
+    return true;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index edd9f816d0..22930297b6 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -249,47 +249,6 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i
         comb->attrs[attr.first] = attr.second;
 }
 
-void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
-{
-    lc->params[id_LUT0_INITVAL] = lut->params[id_INIT];
-
-    for (std::string i : {"A", "B", "C", "D"}) {
-        IdString lut_port = ctx->id(i);
-        IdString lc_port = ctx->id(i + "0");
-        lut->movePortTo(lut_port, lc, lc_port);
-    }
-
-    lut->movePortTo(id_Z, lc, id_F0);
-}
-
-void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type)
-{
-    // FIXME: This will have to change once we support FFs with reset value of 1.
-    lc->params[id_REG0_REGSET] = std::string("RESET");
-
-    dff->movePortTo(id_CLK, lc, id_CLK);
-    dff->movePortTo(id_LSR, lc, id_LSR);
-    dff->movePortTo(id_Q, lc, id_Q0);
-
-    if (lut_type == LutType::PassThru) {
-        // If a register's DI port is fed by a constant, options for placing are
-        // limited. Use the LUT to get around this.
-        // LUT output will go to F0, which will feed back to DI0 input.
-        lc->params[id_LUT0_INITVAL] = Property(0xAAAA, 16);
-        dff->movePortTo(id_DI, lc, id_A0);
-        lc->connectPorts(id_F0, lc, id_DI0);
-    } else if (lut_type == LutType::None) {
-        // If there is no LUT, use the M0 input because DI0 requires
-        // going through the LUTs.
-        lc->params[id_REG0_SD] = std::string("0");
-        dff->movePortTo(id_DI, lc, id_M0);
-    } else {
-        // Otherwise, there's a LUT being used in the slice and mapping DI to
-        // DI0 input is fine.
-        dff->movePortTo(id_DI, lc, id_DI0);
-    }
-}
-
 void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
                 pool<IdString> &todelete_cells)
 {
diff --git a/machxo2/cells.h b/machxo2/cells.h
index cc64b52e2e..43411019fa 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -25,49 +25,36 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-// When packing DFFs, we need context of how it's connected to a LUT to
-// properly map DFF ports to TRELLIS_SLICEs; DI0 input muxes F0 and OFX0,
-// and a DFF inside a slice can use either DI0 or M0 as an input.
-enum class LutType
-{
-    None,
-    Normal,
-    PassThru,
-};
-
 // Create a MachXO2 arch cell and return it
 // Name will be automatically assigned if not specified
 std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
 inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
-inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
-inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
 
-// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
-// as needed. Set no_dff if a DFF is not being used, so that the output
-// can be reconnected
-void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
 
-// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
-// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
-// be configured as pass through and D connected to I0, otherwise D will be
-// ignored
-void dff_to_lc(Context *ctx, CellInfo *dff, CellInfo *lc, LutType lut_type = LutType::Normal);
+inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
-// Convert a nextpnr IO buffer to a TRELLIS_IO
-void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
-                pool<IdString> &todelete_cells);
+inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
+
+inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_PFUMX; }
+
+inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_L6MUX21; }
 
 void lut_to_comb(Context *ctx, CellInfo *lut);
 void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw);
 void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i);
 void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, int index);
 
+// Convert a nextpnr IO buffer to a TRELLIS_IO
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+                pool<IdString> &todelete_cells);
+
+
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 78becc189c..e0ea62eafc 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -303,6 +303,192 @@ class Ecp5Packer
         return false;
     }
 
+    // Pass to pack LUT5s into a newly created slice
+    void pack_lut5xs()
+    {
+        log_info("Packing LUT5-7s...\n");
+
+        // Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
+        auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
+            NetInfo *f1 = lut5->getPort(id_F1);
+            NPNR_ASSERT(f1 != nullptr);
+            NPNR_ASSERT(f1->driver.cell != nullptr);
+            return f1->driver.cell;
+        };
+
+        dict<IdString, std::pair<CellInfo *, CellInfo *>> lut5_roots, lut6_roots, lut7_roots;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_pfumx(ctx, ci)) {
+                NetInfo *f0 = ci->ports.at(id_BLUT).net;
+
+                if (f0 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
+                NetInfo *f1 = ci->ports.at(id_ALUT).net;
+                if (f1 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
+
+                CellInfo *lut0 =
+                        (f0->driver.cell && f0->driver.cell->type == id_TRELLIS_COMB && f0->driver.port == id_F)
+                                ? f0->driver.cell
+                                : nullptr;
+                CellInfo *lut1 =
+                        (f1->driver.cell && f1->driver.cell->type == id_TRELLIS_COMB && f1->driver.port == id_F)
+                                ? f1->driver.cell
+                                : nullptr;
+                if (lut0 == nullptr || lut0->cluster != ClusterId())
+                    log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                if (lut1 == nullptr || lut1->cluster != ClusterId())
+                    log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                lut0->addInput(id_F1);
+                lut0->addInput(id_M);
+                lut0->addOutput(id_OFX);
+
+                ci->movePortTo(id_Z, lut0, id_OFX);
+                ci->movePortTo(id_ALUT, lut0, id_F1);
+                ci->movePortTo(id_C0, lut0, id_M);
+                ci->disconnectPort(id_BLUT);
+
+                lut5_roots[lut0->name] = {lut0, lut1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT6s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
+                if (ofx0_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
+                if (ofx0_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb0 = (ofx0_0->driver.cell && ofx0_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_0->driver.port == id_OFX)
+                                          ? ofx0_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb1 = (ofx0_1->driver.cell && ofx0_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_1->driver.port == id_OFX)
+                                          ? ofx0_1->driver.cell
+                                          : nullptr;
+                if (comb0 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb0->name))
+                    continue;
+
+                if (comb1 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb1->name))
+                    continue;
+                if (ctx->verbose)
+                    log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
+                comb0 = get_comb1_from_lut5(comb0);
+                comb1 = get_comb1_from_lut5(comb1);
+
+                comb1->addInput(id_FXA);
+                comb1->addInput(id_FXB);
+                comb1->addInput(id_M);
+                comb1->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb1, id_FXA);
+                ci->movePortTo(id_D1, comb1, id_FXB);
+                ci->movePortTo(id_SD, comb1, id_M);
+                ci->movePortTo(id_Z, comb1, id_OFX);
+                lut6_roots[comb1->name] = {comb0, comb1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT7s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
+                if (ofx1_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
+                if (ofx1_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb1 = (ofx1_0->driver.cell && ofx1_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_0->driver.port == id_OFX)
+                                          ? ofx1_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb3 = (ofx1_1->driver.cell && ofx1_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_1->driver.port == id_OFX)
+                                          ? ofx1_1->driver.cell
+                                          : nullptr;
+                if (comb1 == nullptr)
+                    log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
+                              ofx1_0->driver.port.c_str(ctx));
+                if (comb3 == nullptr)
+                    log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
+                              ofx1_1->driver.port.c_str(ctx));
+
+                NetInfo *fxa_0 = comb1->ports.at(id_FXA).net;
+                if (fxa_0 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb1->name.c_str(ctx));
+                NetInfo *fxa_1 = comb3->ports.at(id_FXA).net;
+                if (fxa_1 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb3->name.c_str(ctx));
+
+                CellInfo *comb2 = net_driven_by(
+                        ctx, fxa_1,
+                        [](const Context *ctx, const CellInfo *ci) {
+                            (void)ctx;
+                            return ci->type == id_TRELLIS_COMB;
+                        },
+                        id_OFX);
+                if (comb2 == nullptr)
+                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
+                              comb3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
+                              fxa_1->driver.port.c_str(ctx));
+                comb2 = get_comb1_from_lut5(comb2);
+                comb2->addInput(id_FXA);
+                comb2->addInput(id_FXB);
+                comb2->addInput(id_M);
+                comb2->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb2, id_FXA);
+                ci->movePortTo(id_D1, comb2, id_FXB);
+                ci->movePortTo(id_SD, comb2, id_M);
+                ci->movePortTo(id_Z, comb2, id_OFX);
+
+                lut7_roots[comb2->name] = {comb1, comb3};
+                packed_cells.insert(ci->name);
+            }
+        }
+
+        for (auto &root : lut7_roots) {
+            auto &cells = root.second;
+            cells.second->cluster = cells.second->name;
+            cells.second->constr_abs_z = true;
+            cells.second->constr_z = (1 << Arch::lc_idx_shift) | Arch::BEL_COMB;
+            rel_constr_cells(cells.second, cells.first, (4 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut6_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.second, cells.first, (2 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut5_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.first, cells.second, (1 << Arch::lc_idx_shift));
+        }
+        flush_cells();
+    }
+
     // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
     void pack_io()
     {
@@ -914,6 +1100,7 @@ class Ecp5Packer
         pack_dram();
         pack_carries();
         pack_luts();
+        pack_lut5xs();
         pack_ffs();
         ctx->fixupHierarchy();
         ctx->check();
@@ -1021,166 +1208,4 @@ void Arch::assignArchInfo()
     }
 }
 
-inline NetInfo *port_or_nullptr(const CellInfo *cell, IdString name)
-{
-    auto found = cell->ports.find(name);
-    if (found == cell->ports.end())
-        return nullptr;
-    return found->second.net;
-}
-
-bool Arch::slices_compatible(LogicTileStatus *lts) const
-{
-    if (lts == nullptr)
-        return true;
-    for (int sl = 0; sl < 4; sl++) {
-        if (!lts->slices[sl].dirty) {
-            if (!lts->slices[sl].valid)
-                return false;
-            continue;
-        }
-        lts->slices[sl].dirty = false;
-        lts->slices[sl].valid = false;
-        bool found_ff = false;
-        uint8_t last_ff_flags = 0;
-        IdString last_ce_sig;
-        bool ramw_used = false;
-        if (sl == 2 && lts->cells[((sl * 2) << lc_idx_shift) | BEL_RAMW] != nullptr)
-            ramw_used = true;
-        for (int l = 0; l < 2; l++) {
-            bool comb_m_used = false;
-            CellInfo *comb = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_COMB];
-            if (comb != nullptr) {
-                uint8_t flags = comb->combInfo.flags;
-                if (ramw_used && !(flags & ArchCellInfo::COMB_RAMW_BLOCK))
-                    return false;
-                if (flags & ArchCellInfo::COMB_MUX5) {
-                    // MUX5 uses M signal and must be in LC 0
-                    comb_m_used = true;
-                    if (l != 0)
-                        return false;
-                }
-                if (flags & ArchCellInfo::COMB_MUX6) {
-                    // MUX6+ uses M signal and must be in LC 1
-                    comb_m_used = true;
-                    if (l != 1)
-                        return false;
-                    if (comb->combInfo.mux_fxad != nullptr &&
-                        (comb->combInfo.mux_fxad->combInfo.flags & ArchCellInfo::COMB_MUX5)) {
-                        // LUT6 structure must be rooted at SLICE 0 or 2
-                        if (sl != 0 && sl != 2)
-                            return false;
-                    }
-                }
-                // LUTRAM must be in bottom two SLICEs only
-                if ((flags & ArchCellInfo::COMB_LUTRAM) && (sl > 1))
-                    return false;
-                if (l == 1) {
-                    // Carry usage must be the same for LCs 0 and 1 in a SLICE
-                    CellInfo *comb0 = lts->cells[((sl * 2 + 0) << lc_idx_shift) | BEL_COMB];
-                    if (comb0 &&
-                        ((comb0->combInfo.flags & ArchCellInfo::COMB_CARRY) != (flags & ArchCellInfo::COMB_CARRY)))
-                        return false;
-                }
-            }
-
-            CellInfo *ff = lts->cells[((sl * 2 + l) << lc_idx_shift) | BEL_FF];
-            if (ff != nullptr) {
-                uint8_t flags = ff->ffInfo.flags;
-                if (comb_m_used && (flags & ArchCellInfo::FF_M_USED))
-                    return false;
-                if (found_ff) {
-                    if ((flags & ArchCellInfo::FF_GSREN) != (last_ff_flags & ArchCellInfo::FF_GSREN))
-                        return false;
-                    if ((flags & ArchCellInfo::FF_CECONST) != (last_ff_flags & ArchCellInfo::FF_CECONST))
-                        return false;
-                    if ((flags & ArchCellInfo::FF_CEINV) != (last_ff_flags & ArchCellInfo::FF_CEINV))
-                        return false;
-                    if (ff->ffInfo.ce_sig != last_ce_sig)
-                        return false;
-                } else {
-                    found_ff = true;
-                    last_ff_flags = flags;
-                    last_ce_sig = ff->ffInfo.ce_sig;
-                }
-            }
-        }
-
-        lts->slices[sl].valid = true;
-    }
-    if (lts->tile_dirty) {
-        bool found_global_ff = false;
-        bool found_global_dpram = false;
-        bool global_lsrinv = false;
-        bool global_clkinv = false;
-        bool global_async = false;
-
-        IdString clk_sig, lsr_sig;
-
-        lts->tile_dirty = false;
-        lts->tile_valid = false;
-
-#define CHECK_EQUAL(x, y)                                                                                              \
-    do {                                                                                                               \
-        if ((x) != (y))                                                                                                \
-            return false;                                                                                              \
-    } while (0)
-        for (int i = 0; i < 8; i++) {
-            if (i < 4) {
-                // DPRAM
-                CellInfo *comb = lts->cells[(i << lc_idx_shift) | BEL_COMB];
-                if (comb != nullptr && (comb->combInfo.flags & ArchCellInfo::COMB_LUTRAM)) {
-                    if (found_global_dpram) {
-                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV), global_clkinv);
-                        CHECK_EQUAL(bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV), global_lsrinv);
-                    } else {
-                        global_clkinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV);
-                        global_lsrinv = bool(comb->combInfo.flags & ArchCellInfo::COMB_RAM_WREINV);
-                        found_global_dpram = true;
-                    }
-                }
-            }
-            // FF
-            CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
-            if (ff != nullptr) {
-                if (found_global_dpram) {
-                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
-                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
-                }
-                if (found_global_ff) {
-                    CHECK_EQUAL(ff->ffInfo.clk_sig, clk_sig);
-                    CHECK_EQUAL(ff->ffInfo.lsr_sig, lsr_sig);
-                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
-                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
-                    CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC), global_async);
-
-                } else {
-                    clk_sig = ff->ffInfo.clk_sig;
-                    lsr_sig = ff->ffInfo.lsr_sig;
-                    global_clkinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV);
-                    global_lsrinv = bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV);
-                    global_async = bool(ff->ffInfo.flags & ArchCellInfo::FF_ASYNC);
-                    found_global_ff = true;
-                }
-            }
-        }
-#undef CHECK_EQUAL
-        lts->tile_valid = true;
-    } else {
-        if (!lts->tile_valid)
-            return false;
-    }
-
-    return true;
-}
-
-bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
-{
-    IdString bel_type = getBelType(bel);
-    if (bel_type.in(id_TRELLIS_COMB, id_TRELLIS_FF, id_TRELLIS_RAMW)) {
-        return slices_compatible(tile_status.at(tile_index(bel)).lts);
-    }
-    return true;
-}
-
 NEXTPNR_NAMESPACE_END

From 6508a0c267ece1f237500c11f85f33bce4f94fc7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 20:06:18 +0200
Subject: [PATCH 338/712] This should not be here

---
 machxo2/bitstream.cc | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 529c5cc984..34a29c7603 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -201,12 +201,6 @@ void config_empty_lcmxo3_4300(ChipConfig &cc)
 
 void config_empty_lcmxo3_6900(ChipConfig &cc)
 {
-    // TODO: This block is probably clock routing
-    cc.tiles["CENTER20:CENTER_EBR_CIB_SP"].add_unknown(23, 1);
-    cc.tiles["CIB_R20C36:CIB_EBR0"].add_unknown(26, 30);
-    cc.tiles["CIB_R20C40:CIB_EBR1"].add_unknown(26, 30);
-    cc.tiles["PR16:PIC_R1"].add_unknown(16, 52);
-
     cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);

From 3624fe90b2884d846e84ad737a9c8e7d52025962 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 30 Mar 2023 20:56:22 +0200
Subject: [PATCH 339/712] one step closer

---
 machxo2/baseconfigs.cc | 272 +++++++++++++
 machxo2/bitstream.cc   | 890 +++++++++++++++--------------------------
 2 files changed, 597 insertions(+), 565 deletions(-)
 create mode 100644 machxo2/baseconfigs.cc

diff --git a/machxo2/baseconfigs.cc b/machxo2/baseconfigs.cc
new file mode 100644
index 0000000000..29c12c7261
--- /dev/null
+++ b/machxo2/baseconfigs.cc
@@ -0,0 +1,272 @@
+#include "config.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+namespace BaseConfigs {
+void config_empty_lcmxo2_256(ChipConfig &cc)
+{
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
+
+    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_640(ChipConfig &cc)
+{
+    cc.tiles["EBR_R0C14:EBR1_640"].add_unknown(0, 12);
+    cc.tiles["EBR_R0C17:EBR1_640"].add_unknown(0, 12);
+
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
+    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
+
+    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_1200(ChipConfig &cc)
+{
+    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_2000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_4000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo2_7000(ChipConfig &cc)
+{
+    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_1300(ChipConfig &cc)
+{
+    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_2100(ChipConfig &cc)
+{
+    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_4300(ChipConfig &cc)
+{
+    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_6900(ChipConfig &cc)
+{
+    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+
+void config_empty_lcmxo3_9400(ChipConfig &cc)
+{
+    cc.tiles["EBR_R15C2:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C5:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C8:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C11:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C14:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C17:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C20:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C23:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C27:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C30:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C33:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C36:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C39:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C42:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C45:EBR1_10K"].add_unknown(0, 12);
+    cc.tiles["EBR_R15C48:EBR1_10K"].add_unknown(0, 12);
+   
+    cc.tiles["EBR_R8C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C20:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C23:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C27:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C30:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C33:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C36:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C39:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C42:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C45:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R8C48:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["EBR_R22C2:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C5:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C8:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C11:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C14:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C17:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C20:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C23:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C27:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C30:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C33:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C36:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C39:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C42:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C45:EBR1"].add_unknown(0, 12);
+    cc.tiles["EBR_R22C48:EBR1"].add_unknown(0, 12);
+
+    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
+    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
+
+    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
+}
+} // namespace BaseConfigs
+NEXTPNR_NAMESPACE_END
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 34a29c7603..3d28e5b47a 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -30,613 +30,373 @@ NEXTPNR_NAMESPACE_BEGIN
 
 // These seem simple enough to do inline for now.
 namespace BaseConfigs {
-void config_empty_lcmxo2_256(ChipConfig &cc)
-{
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
-
-    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo2_640(ChipConfig &cc)
-{
-    cc.tiles["EBR_R0C14:EBR1_640"].add_unknown(0, 12);
-    cc.tiles["EBR_R0C17:EBR1_640"].add_unknown(0, 12);
-
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 41);
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 43);
-    cc.tiles["PT1:CFG0_ENDL"].add_unknown(5, 47);
-
-    cc.tiles["PT4:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo2_1200(ChipConfig &cc)
-{
-    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo2_2000(ChipConfig &cc)
-{
-    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo2_4000(ChipConfig &cc)
-{
-    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo2_7000(ChipConfig &cc)
-{
-    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo3_1300(ChipConfig &cc)
-{
-    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo3_2100(ChipConfig &cc)
-{
-    cc.tiles["EBR_R8C3:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C6:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C9:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C12:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C16:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C19:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C25:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo3_4300(ChipConfig &cc)
-{
-    cc.tiles["EBR_R11C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C19:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R11C31:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo3_6900(ChipConfig &cc)
-{
-    cc.tiles["EBR_R13C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C31:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C34:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C37:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R13C40:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["EBR_R20C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C22:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C25:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C28:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C31:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C34:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C37:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R20C40:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
-
-void config_empty_lcmxo3_9400(ChipConfig &cc)
-{
-    cc.tiles["EBR_R15C2:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C5:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C8:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C11:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C14:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C17:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C20:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C23:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C27:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C30:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C33:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C36:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C39:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C42:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C45:EBR1_10K"].add_unknown(0, 12);
-    cc.tiles["EBR_R15C48:EBR1_10K"].add_unknown(0, 12);
-   
-    cc.tiles["EBR_R8C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C20:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C23:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C27:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C30:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C33:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C36:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C39:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C42:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C45:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R8C48:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["EBR_R22C2:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C5:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C8:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C11:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C14:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C17:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C20:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C23:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C27:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C30:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C33:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C36:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C39:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C42:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C45:EBR1"].add_unknown(0, 12);
-    cc.tiles["EBR_R22C48:EBR1"].add_unknown(0, 12);
-
-    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
-    cc.tiles["PT4:CFG0"].add_unknown(5, 36);
-
-    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
-}
+void config_empty_lcmxo2_256(ChipConfig &cc);
+void config_empty_lcmxo2_640(ChipConfig &cc);
+void config_empty_lcmxo2_1200(ChipConfig &cc);
+void config_empty_lcmxo2_2000(ChipConfig &cc);
+void config_empty_lcmxo2_4000(ChipConfig &cc);
+void config_empty_lcmxo2_7000(ChipConfig &cc);
+void config_empty_lcmxo3_1300(ChipConfig &cc);
+void config_empty_lcmxo3_2100(ChipConfig &cc);
+void config_empty_lcmxo3_4300(ChipConfig &cc);
+void config_empty_lcmxo3_6900(ChipConfig &cc);
+void config_empty_lcmxo3_9400(ChipConfig &cc);
 } // namespace BaseConfigs
 
-// Convert an absolute wire name to a relative Trellis one
-static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
+namespace {
+struct MachXO2Bitgen
 {
-    std::string basename = ctx->tile_info(wire)->wire_data[wire.index].name.get();
-    std::string prefix2 = basename.substr(0, 2);
-    std::string prefix7 = basename.substr(0, 7);
-    int max_col = ctx->chip_info->width - 1;
-
-    // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose
-    // relative coords push them outside the bounds of the chip.
-    // Indents are based on wires proximity/purpose.
-    auto is_pio_wire = [](std::string name) {
-        // clang-format off
-        return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
-                    name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
-                    name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
-                // JCE0-3, JCLK0-3, JLSR0-3 connect to PIO wires named JCEA-D, JCLKA-D, JLSRA-D.
-                name.find("JCEA") != std::string::npos || name.find("JCEB") != std::string::npos ||
-                    name.find("JCEC") != std::string::npos || name.find("JCED") != std::string::npos ||
-                    name.find("JCLKA") != std::string::npos || name.find("JCLKB") != std::string::npos ||
-                    name.find("JCLKC") != std::string::npos || name.find("JCLKD") != std::string::npos ||
-                    name.find("JLSRA") != std::string::npos || name.find("JLSRB") != std::string::npos ||
-                    name.find("JLSRC") != std::string::npos || name.find("JLSRD") != std::string::npos ||
-                name.find("JONEG") != std::string::npos || name.find("JOPOS") != std::string::npos ||
-                    name.find("JTS") != std::string::npos ||
-                name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
-                // Connections to global mux
-                name.find("JINCK") != std::string::npos);
-        // clang-format on
-    };
-
-    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
-        return basename;
-
-    if (prefix2 == "U_" || prefix2 == "D_") {
-        // We needded to keep U_ and D_ prefixes to generate the routing
-        // graph connections properly, but in truth they are not relevant
-        // outside of the center row of tiles as far as the database is
-        // concerned. So convert U_/D_ prefixes back to G_ if not in the
-        // center row.
-
-        // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
-        // add a center row/col field to chipdb?
-        if (loc.y == 6)
+    explicit MachXO2Bitgen(Context *ctx) : ctx(ctx){};
+    Context *ctx;
+    ChipConfig cc;
+    // Convert an absolute wire name to a relative Trellis one
+    std::string get_trellis_wirename(Location loc, WireId wire)
+    {
+        std::string basename = ctx->tile_info(wire)->wire_data[wire.index].name.get();
+        std::string prefix2 = basename.substr(0, 2);
+        std::string prefix7 = basename.substr(0, 7);
+        int max_col = ctx->chip_info->width - 1;
+
+        // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose
+        // relative coords push them outside the bounds of the chip.
+        // Indents are based on wires proximity/purpose.
+        auto is_pio_wire = [](std::string name) {
+            // clang-format off
+            return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
+                        name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
+                        name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
+                    // JCE0-3, JCLK0-3, JLSR0-3 connect to PIO wires named JCEA-D, JCLKA-D, JLSRA-D.
+                    name.find("JCEA") != std::string::npos || name.find("JCEB") != std::string::npos ||
+                        name.find("JCEC") != std::string::npos || name.find("JCED") != std::string::npos ||
+                        name.find("JCLKA") != std::string::npos || name.find("JCLKB") != std::string::npos ||
+                        name.find("JCLKC") != std::string::npos || name.find("JCLKD") != std::string::npos ||
+                        name.find("JLSRA") != std::string::npos || name.find("JLSRB") != std::string::npos ||
+                        name.find("JLSRC") != std::string::npos || name.find("JLSRD") != std::string::npos ||
+                    name.find("JONEG") != std::string::npos || name.find("JOPOS") != std::string::npos ||
+                        name.find("JTS") != std::string::npos ||
+                    name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
+                    // Connections to global mux
+                    name.find("JINCK") != std::string::npos);
+            // clang-format on
+        };
+
+        if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
             return basename;
-        else
-            return "G_" + basename.substr(2);
-    }
 
-    if (loc == wire.location) {
-        // TODO: JINCK is not currently handled by this.
-        if (is_pio_wire(basename)) {
-            if (wire.location.x == 0) {
-                std::string pio_name = "W1_" + basename;
-                if (ctx->verbose)
-                    log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
-                             pio_name.c_str());
-                return pio_name;
-            } else if (wire.location.x == max_col) {
-                std::string pio_name = "E1_" + basename;
-                if (ctx->verbose)
-                    log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
-                             pio_name.c_str());
-                return pio_name;
-            }
+        if (prefix2 == "U_" || prefix2 == "D_") {
+            // We needded to keep U_ and D_ prefixes to generate the routing
+            // graph connections properly, but in truth they are not relevant
+            // outside of the center row of tiles as far as the database is
+            // concerned. So convert U_/D_ prefixes back to G_ if not in the
+            // center row.
+
+            // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
+            // add a center row/col field to chipdb?
+            if (loc.y == 6)
+                return basename;
+            else
+                return "G_" + basename.substr(2);
         }
-        return basename;
-    }
-
-    std::string rel_prefix;
-    if (wire.location.y < loc.y)
-        rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
-    if (wire.location.y > loc.y)
-        rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
-    if (wire.location.x > loc.x)
-        rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
-    if (wire.location.x < loc.x)
-        rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
-    return rel_prefix + "_" + basename;
-}
-
-static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
-{
-    std::string tile = ctx->get_pip_tilename(pip);
-    std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
-    std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
-    std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
-    cc.tiles[tile].add_arc(sink, source);
 
-    // Special case pips whose config bits are spread across tiles.
-    if (source == "G_PCLKCIBVIQT0" && sink == "G_VPRXCLKI0") {
-        if (tile_type == "CENTER7") {
-            cc.tiles[ctx->get_tile_by_type("CENTER8")].add_arc(sink, source);
-        } else if (tile_type == "CENTER8") {
-            cc.tiles[ctx->get_tile_by_type("CENTER7")].add_arc(sink, source);
-        } else {
-            NPNR_ASSERT_FALSE("Tile does not contain special-cased pip");
+        if (loc == wire.location) {
+            // TODO: JINCK is not currently handled by this.
+            if (is_pio_wire(basename)) {
+                if (wire.location.x == 0) {
+                    std::string pio_name = "W1_" + basename;
+                    if (ctx->verbose)
+                        log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
+                                pio_name.c_str());
+                    return pio_name;
+                } else if (wire.location.x == max_col) {
+                    std::string pio_name = "E1_" + basename;
+                    if (ctx->verbose)
+                        log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
+                                pio_name.c_str());
+                    return pio_name;
+                }
+            }
+            return basename;
         }
+
+        std::string rel_prefix;
+        if (wire.location.y < loc.y)
+            rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
+        if (wire.location.y > loc.y)
+            rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
+        if (wire.location.x > loc.x)
+            rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
+        if (wire.location.x < loc.x)
+            rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
+        return rel_prefix + "_" + basename;
     }
-}
 
-static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
-{
-    std::array<std::vector<unsigned>, 4> phys_to_log;
-    const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
-    for (unsigned i = 0; i < 4; i++) {
-        WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
-        for (PipId pip : ctx->getPipsUphill(pin_wire)) {
-            if (!ctx->getBoundPipNet(pip))
-                continue;
-            unsigned lp = ctx->tile_info(pip)->pip_data[pip.index].lutperm_flags;
-            if (!is_lutperm_pip(lp)) { // non-permuting
-                phys_to_log[i].push_back(i);
-            } else { // permuting
-                unsigned from_pin = lutperm_in(lp);
-                unsigned to_pin = lutperm_out(lp);
-                NPNR_ASSERT(to_pin == i);
-                phys_to_log[from_pin].push_back(i);
+    void set_pip(ChipConfig &cc, PipId pip)
+    {
+        std::string tile = ctx->get_pip_tilename(pip);
+        std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
+        std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
+        std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip));
+        cc.tiles[tile].add_arc(sink, source);
+
+        // Special case pips whose config bits are spread across tiles.
+        if (source == "G_PCLKCIBVIQT0" && sink == "G_VPRXCLKI0") {
+            if (tile_type == "CENTER7") {
+                cc.tiles[ctx->get_tile_by_type("CENTER8")].add_arc(sink, source);
+            } else if (tile_type == "CENTER8") {
+                cc.tiles[ctx->get_tile_by_type("CENTER7")].add_arc(sink, source);
+            } else {
+                NPNR_ASSERT_FALSE("Tile does not contain special-cased pip");
             }
         }
     }
-    for (unsigned i = 0; i < 4; i++)
-        if (!phys_to_log.at(i).empty())
-            used_phys_pins.insert(ports.at(i));
-    if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
-        // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
+
+    unsigned permute_lut(CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
+    {
+        std::array<std::vector<unsigned>, 4> phys_to_log;
+        const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
         for (unsigned i = 0; i < 4; i++) {
+            WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
+            for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+                if (!ctx->getBoundPipNet(pip))
+                    continue;
+                unsigned lp = ctx->tile_info(pip)->pip_data[pip.index].lutperm_flags;
+                if (!is_lutperm_pip(lp)) { // non-permuting
+                    phys_to_log[i].push_back(i);
+                } else { // permuting
+                    unsigned from_pin = lutperm_in(lp);
+                    unsigned to_pin = lutperm_out(lp);
+                    NPNR_ASSERT(to_pin == i);
+                    phys_to_log[from_pin].push_back(i);
+                }
+            }
+        }
+        for (unsigned i = 0; i < 4; i++)
             if (!phys_to_log.at(i).empty())
-                continue;
-            for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
-                if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
-                    phys_to_log.at(i).push_back(j);
+                used_phys_pins.insert(ports.at(i));
+        if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
+            // Insert dummy entries to ensure we keep the split between the two halves of a CCU2
+            for (unsigned i = 0; i < 4; i++) {
+                if (!phys_to_log.at(i).empty())
+                    continue;
+                for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
+                    if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
+                        phys_to_log.at(i).push_back(j);
+                }
             }
         }
-    }
-    unsigned permuted_init = 0;
-    for (unsigned i = 0; i < 16; i++) {
-        unsigned log_idx = 0;
-        for (unsigned j = 0; j < 4; j++) {
-            if ((i >> j) & 0x1) {
-                for (auto log_pin : phys_to_log[j])
-                    log_idx |= (1 << log_pin);
+        unsigned permuted_init = 0;
+        for (unsigned i = 0; i < 16; i++) {
+            unsigned log_idx = 0;
+            for (unsigned j = 0; j < 4; j++) {
+                if ((i >> j) & 0x1) {
+                    for (auto log_pin : phys_to_log[j])
+                        log_idx |= (1 << log_pin);
+                }
             }
+            if ((orig_init >> log_idx) & 0x1)
+                permuted_init |= (1 << i);
         }
-        if ((orig_init >> log_idx) & 0x1)
-            permuted_init |= (1 << i);
+        return permuted_init;
     }
-    return permuted_init;
-}
 
-static std::vector<bool> int_to_bitvector(int val, int size)
-{
-    std::vector<bool> bv;
-    for (int i = 0; i < size; i++) {
-        bv.push_back((val & (1 << i)) != 0);
-    }
-    return bv;
-}
-
-std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString &key, std::string def = "0")
-{
-    auto found = ct.find(key);
-    if (found == ct.end())
-        return def;
-    else {
-        if (found->second.is_string)
-            return found->second.as_string();
-        else
-            return std::to_string(found->second.as_int64());
+    std::vector<bool> int_to_bitvector(int val, int size)
+    {
+        std::vector<bool> bv;
+        for (int i = 0; i < size; i++) {
+            bv.push_back((val & (1 << i)) != 0);
+        }
+        return bv;
     }
-};
 
-// Get the PIC tile corresponding to a PIO bel
-static std::string get_pic_tile(Context *ctx, BelId bel)
-{
-    static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
-    static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
-    static const std::set<std::string> pio_l = {"PIC_L0",       "PIC_L1",       "PIC_L2",       "PIC_L3",
-                                                "PIC_LS0",      "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
-                                                "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5", "PIC_L2_VREF4",
-                                                "PIC_L2_VREF5", "PIC_L3_VREF4", "PIC_L3_VREF5"};
-    static const std::set<std::string> pio_r = {"PIC_R0",     "PIC_R1",     "PIC_RS0",
-                                                "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
+    std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString &key, std::string def = "0")
+    {
+        auto found = ct.find(key);
+        if (found == ct.end())
+            return def;
+        else {
+            if (found->second.is_string)
+                return found->second.as_string();
+            else
+                return std::to_string(found->second.as_int64());
+        }
+    };
 
-    std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-    if (bel.location.y == 0) {
-        return ctx->get_tile_by_type_loc(0, bel.location.x, pio_t);
-    } else if (bel.location.y == ctx->chip_info->height - 1) {
-        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_b);
-    } else if (bel.location.x == 0) {
-        return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
-    } else if (bel.location.x == ctx->chip_info->width - 1) {
-        return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r);
-    } else {
-        NPNR_ASSERT_FALSE("bad PIO location");
+    // Get the PIC tile corresponding to a PIO bel
+    std::string get_pic_tile(BelId bel)
+    {
+        static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
+        static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
+        static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
+                                                    "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
+                                                    "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
+                                                    "PIC_L2_VREF4", "PIC_L2_VREF5",
+                                                    "PIC_L3_VREF4", "PIC_L3_VREF5"};
+        static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
+                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
+
+        std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
+        if (bel.location.y == 0) {
+            return ctx->get_tile_by_type_loc(0, bel.location.x, pio_t);
+        } else if (bel.location.y == ctx->chip_info->height - 1) {
+            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_b);
+        } else if (bel.location.x == 0) {
+            return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
+        } else if (bel.location.x == ctx->chip_info->width - 1) {
+            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r);
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
     }
-}
 
-void write_bitstream(Context *ctx, std::string text_config_file)
-{
-    ChipConfig cc;
-    IdString base_id = ctx->id(ctx->chip_info->device_name.get());
-    if (base_id == ctx->id("LCMXO2-256"))
-        BaseConfigs::config_empty_lcmxo2_256(cc);
-    else if (base_id == ctx->id("LCMXO2-640"))
-        BaseConfigs::config_empty_lcmxo2_640(cc);
-    else if (base_id == ctx->id("LCMXO2-1200"))
-        BaseConfigs::config_empty_lcmxo2_1200(cc);
-    else if (base_id == ctx->id("LCMXO2-2000"))
-        BaseConfigs::config_empty_lcmxo2_2000(cc);
-    else if (base_id == ctx->id("LCMXO2-4000"))
-        BaseConfigs::config_empty_lcmxo2_4000(cc);
-    else if (base_id == ctx->id("LCMXO2-7000"))
-        BaseConfigs::config_empty_lcmxo2_7000(cc);
-    else if (base_id == ctx->id("LCMXO3-1300"))
-        BaseConfigs::config_empty_lcmxo3_1300(cc);
-    else if (base_id == ctx->id("LCMXO3-2100"))
-        BaseConfigs::config_empty_lcmxo3_2100(cc);
-    else if (base_id == ctx->id("LCMXO3-4300") || base_id == ctx->id("LCMXO3D-4300"))
-        BaseConfigs::config_empty_lcmxo3_4300(cc);
-    else if (base_id == ctx->id("LCMXO3-6900"))
-        BaseConfigs::config_empty_lcmxo3_6900(cc);
-    else if (base_id == ctx->id("LCMXO3-9400") || base_id == ctx->id("LCMXO3D-9400"))
-        BaseConfigs::config_empty_lcmxo3_9400(cc);
-    else
-        NPNR_ASSERT_FALSE("Unsupported device type");
-    cc.chip_name = ctx->chip_info->device_name.get();
-    cc.chip_variant = ctx->device_name;
+    void run()
+    {
+        ChipConfig cc;
+        IdString base_id = ctx->id(ctx->chip_info->device_name.get());
+        if (base_id == ctx->id("LCMXO2-256"))
+            BaseConfigs::config_empty_lcmxo2_256(cc);
+        else if (base_id == ctx->id("LCMXO2-640"))
+            BaseConfigs::config_empty_lcmxo2_640(cc);
+        else if (base_id == ctx->id("LCMXO2-1200"))
+            BaseConfigs::config_empty_lcmxo2_1200(cc);
+        else if (base_id == ctx->id("LCMXO2-2000"))
+            BaseConfigs::config_empty_lcmxo2_2000(cc);
+        else if (base_id == ctx->id("LCMXO2-4000"))
+            BaseConfigs::config_empty_lcmxo2_4000(cc);
+        else if (base_id == ctx->id("LCMXO2-7000"))
+            BaseConfigs::config_empty_lcmxo2_7000(cc);
+        else if (base_id == ctx->id("LCMXO3-1300"))
+            BaseConfigs::config_empty_lcmxo3_1300(cc);
+        else if (base_id == ctx->id("LCMXO3-2100"))
+            BaseConfigs::config_empty_lcmxo3_2100(cc);
+        else if (base_id == ctx->id("LCMXO3-4300") || base_id == ctx->id("LCMXO3D-4300"))
+            BaseConfigs::config_empty_lcmxo3_4300(cc);
+        else if (base_id == ctx->id("LCMXO3-6900"))
+            BaseConfigs::config_empty_lcmxo3_6900(cc);
+        else if (base_id == ctx->id("LCMXO3-9400") || base_id == ctx->id("LCMXO3D-9400"))
+            BaseConfigs::config_empty_lcmxo3_9400(cc);
+        else
+            NPNR_ASSERT_FALSE("Unsupported device type");
+        cc.chip_name = ctx->chip_info->device_name.get();
+        cc.chip_variant = ctx->device_name;
 
-    cc.metadata.push_back("Part: " + ctx->getChipName());
+        cc.metadata.push_back("Part: " + ctx->getChipName());
 
-    if (cc.chip_variant.find("LCMXO3L-") != std::string::npos) {
-        // XO3L have this set but not XO3LF
-        cc.tiles["PT5:CFG1"].add_unknown(5, 36);
-    }
-    if (cc.chip_variant.find("LCMXO3D-") != std::string::npos) {
-        cc.tiles["PT5:CFG1"].add_unknown(5, 36);
-        cc.tiles["PT6:CFG2"].add_unknown(5, 37);
-    }
-
-    // Add all set, configurable pips to the config
-    for (auto pip : ctx->getPips()) {
-        if (ctx->getBoundPipNet(pip) != nullptr) {
-            if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
-                set_pip(ctx, cc, pip);
-            }
+        if (cc.chip_variant.find("LCMXO3L-") != std::string::npos) {
+            // XO3L have this set but not XO3LF
+            cc.tiles["PT5:CFG1"].add_unknown(5, 36);
         }
-    }
-
-    // TODO: Bank Voltages
-
-    // Configure slices
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->bel == BelId()) {
-            log_warning("found unplaced cell '%s' during bitstream gen. Not writing to bitstream.\n",
-                        ci->name.c_str(ctx));
-            continue;
+        if (cc.chip_variant.find("LCMXO3D-") != std::string::npos) {
+            cc.tiles["PT5:CFG1"].add_unknown(5, 36);
+            cc.tiles["PT6:CFG2"].add_unknown(5, 37);
         }
-        BelId bel = ci->bel;
 
-        if (ci->type == id_TRELLIS_COMB) {
-            pool<IdString> used_phys_pins;
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-            int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-            std::string lc = std::to_string(z % 2);
-            std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
-            if (mode == "RAMW_BLOCK")
-                return;
-            int lut_init = int_or_default(ci->params, id_INITVAL);
-            cc.tiles[tname].add_enum(slice + ".MODE", mode);
-            cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
-                                    int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16));
-            if (mode == "CCU2") {
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
-            } else {
-                // Don't interfere with cascade mux wiring
-                cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
-            }
-            if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
-                cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
-                std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
-                wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
-                cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+        // Add all set, configurable pips to the config
+        for (auto pip : ctx->getPips()) {
+            if (ctx->getBoundPipNet(pip) != nullptr) {
+                if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
+                    set_pip(cc, pip);
+                }
             }
-        } else if (ci->type == id_TRELLIS_FF) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-            int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-            std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-            std::string lc = std::to_string(z % 2);
-
-            cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
-            cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-            cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
-            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
-            cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+        }
 
-            cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+        // TODO: Bank Voltages
 
-            NetInfo *lsrnet = ci->getPort(id_LSR);
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-                cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
-            }
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-                cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
-            }
-
-            NetInfo *clknet = ci->getPort(id_CLK);
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-                cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+        // Configure slices
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->bel == BelId()) {
+                log_warning("found unplaced cell '%s' during bitstream gen. Not writing to bitstream.\n",
+                            ci->name.c_str(ctx));
+                continue;
             }
-            if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-                cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+            BelId bel = ci->bel;
+
+            if (ci->type == id_TRELLIS_COMB) {
+                pool<IdString> used_phys_pins;
+                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+                int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+                std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+                std::string lc = std::to_string(z % 2);
+                std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+                if (mode == "RAMW_BLOCK")
+                    return;
+                int lut_init = int_or_default(ci->params, id_INITVAL);
+                cc.tiles[tname].add_enum(slice + ".MODE", mode);
+                cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
+                                        int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
+                if (mode == "CCU2") {
+                    cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
+                } else {
+                    // Don't interfere with cascade mux wiring
+                    cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
+                }
+                if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
+                    cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
+                    std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+                    wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
+                    cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+                }
+            } else if (ci->type == id_TRELLIS_FF) {
+                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+                int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+                std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+                std::string lc = std::to_string(z % 2);
+
+                cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+                cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+                cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
+                cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
+                cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+
+                cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+
+                NetInfo *lsrnet = ci->getPort(id_LSR);
+                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
+                    cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+                    cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+                }
+                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
+                    cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+                    cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+                }
+
+                NetInfo *clknet = ci->getPort(id_CLK);
+                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
+                    cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+                }
+                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
+                    cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+                }
+            } else if (ci->type == id_TRELLIS_RAMW) {
+                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+                cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
+                cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
+                cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
+            } else if (ci->type == id_TRELLIS_IO) {
+                std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
+                std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+                std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+                std::string pic_tile = get_pic_tile(bel);
+                cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+            } else if (ci->type == id_OSCH) {
+                std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
+                cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
+                cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
             }
-        } else if (ci->type == id_TRELLIS_RAMW) {
-            std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-            cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
-            cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
-            cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
-        } else if (ci->type == id_TRELLIS_IO) {
-            std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-            std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
-            std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
-            std::string pic_tile = get_pic_tile(ctx, bel);
-            cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
-        } else if (ci->type == id_OSCH) {
-            std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
-            cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
-            cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
         }
     }
+};
+} // namespace
+
+void write_bitstream(Context *ctx, std::string text_config_file)
+{
+    MachXO2Bitgen bitgen(ctx);
+    bitgen.run();
 
     // Configure chip
     if (!text_config_file.empty()) {
         std::ofstream out_config(text_config_file);
-        out_config << cc;
+        out_config << bitgen.cc;
     }
 }
-
 NEXTPNR_NAMESPACE_END

From 6f85053b03fdddbc553ef7d23adf4a285c99fe12 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 31 Mar 2023 07:57:32 +0200
Subject: [PATCH 340/712] more like ecp5

---
 machxo2/bitstream.cc | 225 +++++++++++++++++++++++++------------------
 1 file changed, 131 insertions(+), 94 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 3d28e5b47a..53dfbded69 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -18,14 +18,20 @@
  *
  */
 
-#include <fstream>
-#include <iostream>
-
 #include "bitstream.h"
+
+#include <boost/algorithm/string/predicate.hpp>
+#include <fstream>
+#include <iomanip>
+#include <queue>
+#include <regex>
+#include <streambuf>
 #include "config.h"
-#include "nextpnr.h"
+#include "log.h"
 #include "util.h"
 
+#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
+
 NEXTPNR_NAMESPACE_BEGIN
 
 // These seem simple enough to do inline for now.
@@ -129,6 +135,54 @@ struct MachXO2Bitgen
             rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
         return rel_prefix + "_" + basename;
     }
+    std::vector<bool> int_to_bitvector(int val, int size)
+    {
+        std::vector<bool> bv;
+        for (int i = 0; i < size; i++) {
+            bv.push_back((val & (1 << i)) != 0);
+        }
+        return bv;
+    }
+    std::vector<bool> str_to_bitvector(std::string str, int size)
+    {
+        std::vector<bool> bv;
+        bv.resize(size, 0);
+        if (str.substr(0, 2) != "0b")
+            log_error("error parsing value '%s', expected 0b prefix\n", str.c_str());
+        for (int i = 0; i < int(str.size()) - 2; i++) {
+            char c = str.at((str.size() - i) - 1);
+            NPNR_ASSERT(c == '0' || c == '1');
+            bv.at(i) = (c == '1');
+        }
+        return bv;
+    }
+
+    // Get the PIC tile corresponding to a PIO bel
+    std::string get_pic_tile(BelId bel)
+    {
+        static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
+        static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
+        static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
+                                                    "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
+                                                    "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
+                                                    "PIC_L2_VREF4", "PIC_L2_VREF5",
+                                                    "PIC_L3_VREF4", "PIC_L3_VREF5"};
+        static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
+                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
+
+        std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
+        if (bel.location.y == 0) {
+            return ctx->get_tile_by_type_loc(0, bel.location.x, pio_t);
+        } else if (bel.location.y == ctx->chip_info->height - 1) {
+            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_b);
+        } else if (bel.location.x == 0) {
+            return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
+        } else if (bel.location.x == ctx->chip_info->width - 1) {
+            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r);
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    }
 
     void set_pip(ChipConfig &cc, PipId pip)
     {
@@ -199,15 +253,6 @@ struct MachXO2Bitgen
         return permuted_init;
     }
 
-    std::vector<bool> int_to_bitvector(int val, int size)
-    {
-        std::vector<bool> bv;
-        for (int i = 0; i < size; i++) {
-            bv.push_back((val & (1 << i)) != 0);
-        }
-        return bv;
-    }
-
     std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString &key, std::string def = "0")
     {
         auto found = ct.find(key);
@@ -221,33 +266,80 @@ struct MachXO2Bitgen
         }
     };
 
-    // Get the PIC tile corresponding to a PIO bel
-    std::string get_pic_tile(BelId bel)
+    void write_comb(CellInfo *ci)
     {
-        static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
-        static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
-        static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
-                                                    "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
-                                                    "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
-                                                    "PIC_L2_VREF4", "PIC_L2_VREF5",
-                                                    "PIC_L3_VREF4", "PIC_L3_VREF5"};
-        static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
-                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
-
-        std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-        if (bel.location.y == 0) {
-            return ctx->get_tile_by_type_loc(0, bel.location.x, pio_t);
-        } else if (bel.location.y == ctx->chip_info->height - 1) {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_b);
-        } else if (bel.location.x == 0) {
-            return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l);
-        } else if (bel.location.x == ctx->chip_info->width - 1) {
-            return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r);
+        pool<IdString> used_phys_pins;
+        BelId bel = ci->bel;
+        std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+        int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+        std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+        std::string lc = std::to_string(z % 2);
+        std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
+        if (mode == "RAMW_BLOCK")
+            return;
+        int lut_init = int_or_default(ci->params, id_INITVAL);
+        cc.tiles[tname].add_enum(slice + ".MODE", mode);
+        cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
+                                int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
+        if (mode == "CCU2") {
+            cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
         } else {
-            NPNR_ASSERT_FALSE("bad PIO location");
+            // Don't interfere with cascade mux wiring
+            cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
+        }
+        if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
+            cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
+            std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
+            wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
+            cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
         }
     }
 
+    void write_ff(CellInfo *ci)
+    {
+        BelId bel = ci->bel;
+        std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
+        int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
+        std::string slice = std::string("SLICE") + "ABCD"[z / 2];
+        std::string lc = std::to_string(z % 2);
+
+        cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+        cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+        cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
+        cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
+        cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
+
+        cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
+
+        NetInfo *lsrnet = ci->getPort(id_LSR);
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
+            cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+            cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+        }
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
+            cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+            cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+        }
+
+        NetInfo *clknet = ci->getPort(id_CLK);
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
+            cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+        }
+        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
+            cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+        }
+    }
+
+    void write_io(CellInfo *ci)
+    {
+        BelId bel = ci->bel;
+        std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
+        std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+        std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+        std::string pic_tile = get_pic_tile(bel);
+        cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+    }
+
     void run()
     {
         ChipConfig cc;
@@ -312,72 +404,16 @@ struct MachXO2Bitgen
             BelId bel = ci->bel;
 
             if (ci->type == id_TRELLIS_COMB) {
-                pool<IdString> used_phys_pins;
-                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-                int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-                std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-                std::string lc = std::to_string(z % 2);
-                std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
-                if (mode == "RAMW_BLOCK")
-                    return;
-                int lut_init = int_or_default(ci->params, id_INITVAL);
-                cc.tiles[tname].add_enum(slice + ".MODE", mode);
-                cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
-                                        int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
-                if (mode == "CCU2") {
-                    cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
-                } else {
-                    // Don't interfere with cascade mux wiring
-                    cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
-                }
-                if (mode == "DPRAM" && slice == "SLICEA" && lc == "0") {
-                    cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
-                    std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
-                    wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
-                    cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
-                }
+                write_comb(ci);
             } else if (ci->type == id_TRELLIS_FF) {
-                std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
-                int z = ctx->tile_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
-                std::string slice = std::string("SLICE") + "ABCD"[z / 2];
-                std::string lc = std::to_string(z % 2);
-
-                cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
-                cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
-                cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
-                cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
-                cc.tiles[tname].add_enum(slice + ".REG" + lc + ".REGSET", str_or_default(ci->params, id_REGSET, "RESET"));
-
-                cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
-
-                NetInfo *lsrnet = ci->getPort(id_LSR);
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                    cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
-                }
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-                    cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-                    cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
-                }
-
-                NetInfo *clknet = ci->getPort(id_CLK);
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
-                }
-                if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-                    cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
-                }
+                write_ff(ci);
             } else if (ci->type == id_TRELLIS_RAMW) {
                 std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
                 cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
                 cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
                 cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
             } else if (ci->type == id_TRELLIS_IO) {
-                std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get();
-                std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
-                std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
-                std::string pic_tile = get_pic_tile(bel);
-                cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+                write_io(ci);
             } else if (ci->type == id_OSCH) {
                 std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
@@ -399,4 +435,5 @@ void write_bitstream(Context *ctx, std::string text_config_file)
         out_config << bitgen.cc;
     }
 }
+
 NEXTPNR_NAMESPACE_END

From a00f8100930dbd9e60f9de3f554d4bf82ec8f177 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 31 Mar 2023 09:03:04 +0200
Subject: [PATCH 341/712] fix

---
 machxo2/bitstream.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 53dfbded69..7e62b927cb 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -342,7 +342,6 @@ struct MachXO2Bitgen
 
     void run()
     {
-        ChipConfig cc;
         IdString base_id = ctx->id(ctx->chip_info->device_name.get());
         if (base_id == ctx->id("LCMXO2-256"))
             BaseConfigs::config_empty_lcmxo2_256(cc);

From aacb36bf15a3eda2d484f94ed38082a8534723b4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 31 Mar 2023 14:37:01 +0200
Subject: [PATCH 342/712] Use CCU2D cell

---
 machxo2/cells.cc     |  2 +-
 machxo2/cells.h      |  2 +-
 machxo2/constids.inc |  2 +-
 machxo2/pack.cc      | 26 +++++++++++++-------------
 4 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index 22930297b6..f97a16a000 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -92,7 +92,7 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std::
         new_cell->addInput(id_C);
         new_cell->addInput(id_D);
         new_cell->addOutput(id_Z);
-    } else if (type == id_CCU2C) {
+    } else if (type == id_CCU2D) {
         new_cell->params[id_INIT0] = Property(0, 16);
         new_cell->params[id_INIT1] = Property(0, 16);
         new_cell->params[id_INJECT1_0] = std::string("YES");
diff --git a/machxo2/cells.h b/machxo2/cells.h
index 43411019fa..dd59e073bc 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -35,7 +35,7 @@ inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 // Return true if a cell is a flipflop
 inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
 
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2D; }
 
 inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
 
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index adb7254d35..0debca1856 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -143,7 +143,7 @@ X(OFX)
 X(F)
 X(M)
 
-X(CCU2C)
+X(CCU2D)
 X(CCU2_INJECT1)
 X(INJECT1_0)
 X(INJECT1_1)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index e0ea62eafc..fd4fb43eef 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -586,7 +586,7 @@ class Ecp5Packer
     // Create a feed in to the carry chain
     CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
     {
-        std::unique_ptr<CellInfo> feedin = create_machxo2_cell(ctx, id_CCU2C);
+        std::unique_ptr<CellInfo> feedin = create_machxo2_cell(ctx, id_CCU2D);
 
         feedin->params[id_INIT0] = Property(10, 16); // LUT4 = 0; LUT2 = A
         feedin->params[id_INIT1] = Property(65535, 16);
@@ -612,7 +612,7 @@ class Ecp5Packer
     // Create a feed out and loop through from the carry chain
     CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
     {
-        std::unique_ptr<CellInfo> feedout = create_machxo2_cell(ctx, id_CCU2C);
+        std::unique_ptr<CellInfo> feedout = create_machxo2_cell(ctx, id_CCU2D);
 
         feedout->params[id_INIT0] = Property(0, 16);
         feedout->params[id_INIT1] = Property(10, 16); // LUT4 = 0; LUT2 = A
@@ -871,7 +871,7 @@ class Ecp5Packer
         cell->ports.at(input).net = nullptr;
     }
 
-    void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value)
+    void set_ccu2d_input_constant(CellInfo *cell, IdString input, bool value)
     {
         std::string input_str = input.str(ctx);
         int lut = std::stoi(input_str.substr(1));
@@ -882,7 +882,7 @@ class Ecp5Packer
         cell->ports.at(input).net = nullptr;
     }
 
-    bool is_ccu2c_port_high(CellInfo *cell, IdString input)
+    bool is_ccu2d_port_high(CellInfo *cell, IdString input)
     {
         if (!cell->ports.count(input))
             return true; // disconnected port is high
@@ -914,19 +914,19 @@ class Ecp5Packer
                     } else if (!constval) {
                         if (user.port.in(id_A0, id_A1, id_B0, id_B1)) {
                             // These inputs can be switched to tie-high without consequence
-                            set_ccu2c_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
+                            set_ccu2d_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_C0 && is_ccu2d_port_high(uc, id_D0)) {
                             // Partner must be tied high
-                            set_ccu2c_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) {
+                            set_ccu2d_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_D0 && is_ccu2d_port_high(uc, id_C0)) {
                             // Partner must be tied high
-                            set_ccu2c_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) {
+                            set_ccu2d_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_C1 && is_ccu2d_port_high(uc, id_D1)) {
                             // Partner must be tied high
-                            set_ccu2c_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) {
+                            set_ccu2d_input_constant(uc, user.port, constval);
+                        } else if (user.port == id_D1 && is_ccu2d_port_high(uc, id_C1)) {
                             // Partner must be tied high
-                            set_ccu2c_input_constant(uc, user.port, constval);
+                            set_ccu2d_input_constant(uc, user.port, constval);
                         } else {
                             // Not allowed to change to a tie-high
                             uc->ports[user.port].net = constnet;

From a0ba9afcbadfed38edb82922f96b037444cd0a4d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 1 Apr 2023 10:43:53 +0200
Subject: [PATCH 343/712] CCU2D is auto tied low

---
 machxo2/pack.cc | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index fd4fb43eef..4dbafd72d9 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -588,7 +588,7 @@ class Ecp5Packer
     {
         std::unique_ptr<CellInfo> feedin = create_machxo2_cell(ctx, id_CCU2D);
 
-        feedin->params[id_INIT0] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedin->params[id_INIT0] = Property(20480, 16);
         feedin->params[id_INIT1] = Property(65535, 16);
         feedin->params[id_INJECT1_0] = std::string("NO");
         feedin->params[id_INJECT1_1] = std::string("YES");
@@ -615,7 +615,7 @@ class Ecp5Packer
         std::unique_ptr<CellInfo> feedout = create_machxo2_cell(ctx, id_CCU2D);
 
         feedout->params[id_INIT0] = Property(0, 16);
-        feedout->params[id_INIT1] = Property(10, 16); // LUT4 = 0; LUT2 = A
+        feedout->params[id_INIT1] = Property(20480, 16);
         feedout->params[id_INJECT1_0] = std::string("NO");
         feedout->params[id_INJECT1_1] = std::string("NO");
 
@@ -882,14 +882,14 @@ class Ecp5Packer
         cell->ports.at(input).net = nullptr;
     }
 
-    bool is_ccu2d_port_high(CellInfo *cell, IdString input)
+    bool is_ccu2d_port_zero(CellInfo *cell, IdString input)
     {
         if (!cell->ports.count(input))
-            return true; // disconnected port is high
-        if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
-            return true; // disconnected or tied-high port
-        if (cell->ports.at(input).net->driver.cell != nullptr && cell->ports.at(input).net->driver.cell->type == id_VCC)
-            return true; // pre-pack high
+            return true; // disconnected port is low
+        if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_GND_NET"))
+            return true; // disconnected or tied-high low
+        if (cell->ports.at(input).net->driver.cell != nullptr && cell->ports.at(input).net->driver.cell->type == id_GND)
+            return true; // pre-pack low
         return false;
     }
 
@@ -908,27 +908,27 @@ class Ecp5Packer
                     uc->params[id_CEMUX] = std::string(constval ? "1" : "0");
                     uc->ports[user.port].net = nullptr;
                 } else if (is_carry(ctx, uc)) {
-                    if (constval && (user.port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))) {
-                        // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
+                    if (!constval && (user.port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))) {
+                        // Input tied low, nothing special to do (bitstream gen will auto-enable tie-low)
                         uc->ports[user.port].net = nullptr;
-                    } else if (!constval) {
+                    } else if (constval) {
                         if (user.port.in(id_A0, id_A1, id_B0, id_B1)) {
-                            // These inputs can be switched to tie-high without consequence
+                            // These inputs can be switched to tie-low without consequence
                             set_ccu2d_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_C0 && is_ccu2d_port_high(uc, id_D0)) {
-                            // Partner must be tied high
+                        } else if (user.port == id_C0 && is_ccu2d_port_zero(uc, id_D0)) {
+                            // Partner must be tied low
                             set_ccu2d_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_D0 && is_ccu2d_port_high(uc, id_C0)) {
-                            // Partner must be tied high
+                        } else if (user.port == id_D0 && is_ccu2d_port_zero(uc, id_C0)) {
+                            // Partner must be tied low
                             set_ccu2d_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_C1 && is_ccu2d_port_high(uc, id_D1)) {
-                            // Partner must be tied high
+                        } else if (user.port == id_C1 && is_ccu2d_port_zero(uc, id_D1)) {
+                            // Partner must be tied low
                             set_ccu2d_input_constant(uc, user.port, constval);
-                        } else if (user.port == id_D1 && is_ccu2d_port_high(uc, id_C1)) {
-                            // Partner must be tied high
+                        } else if (user.port == id_D1 && is_ccu2d_port_zero(uc, id_C1)) {
+                            // Partner must be tied low
                             set_ccu2d_input_constant(uc, user.port, constval);
                         } else {
-                            // Not allowed to change to a tie-high
+                            // Not allowed to change to a tie-low
                             uc->ports[user.port].net = constnet;
                             uc->ports[user.port].user_idx = constnet->users.add(user);
                         }

From 05a191a01492fd954d1b9ef0a9db182abdd5a44b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 1 Apr 2023 19:45:36 +0200
Subject: [PATCH 344/712] Added LPF support

---
 gui/machxo2/mainwindow.cc |   4 +-
 machxo2/arch.h            |   3 +
 machxo2/lpf.cc            | 186 ++++++++++++++++++++++++++++++++++++++
 machxo2/main.cc           |  36 +++++++-
 4 files changed, 226 insertions(+), 3 deletions(-)
 create mode 100644 machxo2/lpf.cc

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 9b7cfb17bc..179bf8e18c 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -124,7 +124,7 @@ void MainWindow::open_lpf()
 {
     QString fileName = QFileDialog::getOpenFileName(this, QString("Open LPF"), QString(), QString("*.lpf"));
     if (!fileName.isEmpty()) {
-        /*std::ifstream in(fileName.toStdString());
+        std::ifstream in(fileName.toStdString());
         if (ctx->apply_lpf(fileName.toStdString(), in)) {
             log("Loading LPF successful.\n");
             actionPack->setEnabled(true);
@@ -132,7 +132,7 @@ void MainWindow::open_lpf()
         } else {
             actionLoadLPF->setEnabled(true);
             log("Loading LPF failed.\n");
-        }*/
+        }
     }
 }
 
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 1615016894..e761458267 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -960,6 +960,9 @@ struct Arch : BaseArch<ArchRanges>
         NPNR_ASSERT_FALSE_STR("no tile with type " + type);
     }
 
+    // Apply LPF constraints to the context
+    bool apply_lpf(std::string filename, std::istream &in);
+
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
     static const std::string defaultRouter;
diff --git a/machxo2/lpf.cc b/machxo2/lpf.cc
new file mode 100644
index 0000000000..2e34f54a40
--- /dev/null
+++ b/machxo2/lpf.cc
@@ -0,0 +1,186 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <sstream>
+
+#include "arch.h"
+#include "log.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+static const pool<std::string> sysconfig_keys = {
+        "SLAVE_SPI_PORT",      "MASTER_SPI_PORT", "SLAVE_PARALLEL_PORT",
+        "BACKGROUND_RECONFIG", "DONE_EX",         "DONE_OD",
+        "DONE_PULL",           "MCCLK_FREQ",      "TRANSFR",
+        "CONFIG_IOVOLTAGE",    "CONFIG_SECURE",   "WAKE_UP",
+        "COMPRESS_CONFIG",     "CONFIG_MODE",     "INBUF",
+};
+
+static const pool<std::string> iobuf_keys = {
+        "IO_TYPE", "BANK",      "BANK_VCC",     "VREF",      "PULLMODE",   "DRIVE",       "SLEWRATE",
+        "CLAMP",   "OPENDRAIN", "DIFFRESISTOR", "DIFFDRIVE", "HYSTERESIS", "TERMINATION",
+};
+
+bool Arch::apply_lpf(std::string filename, std::istream &in)
+{
+    auto isempty = [](const std::string &str) {
+        return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c) || c == '\r' || c == '\n'; });
+    };
+    try {
+        if (!in)
+            log_error("failed to open LPF file\n");
+        std::string line;
+        std::string linebuf;
+        int lineno = 0;
+        auto strip_quotes = [&](const std::string &str) {
+            if (str.at(0) == '"') {
+                if (str.back() != '"') {
+                    log_error("expected '\"' at end of string '%s' (on line %d)\n", str.c_str(), lineno);
+                }
+                return str.substr(1, str.size() - 2);
+            } else {
+                return str;
+            }
+        };
+        while (std::getline(in, line)) {
+            ++lineno;
+            size_t cstart = line.find('#');
+            if (cstart != std::string::npos)
+                line = line.substr(0, cstart);
+            cstart = line.find("//");
+            if (cstart != std::string::npos)
+                line = line.substr(0, cstart);
+            if (isempty(line))
+                continue;
+            linebuf += line;
+            // Look for a command up to a semicolon
+            size_t scpos = linebuf.find(';');
+            while (scpos != std::string::npos) {
+                std::string command = linebuf.substr(0, scpos);
+                // Split command into words
+                std::stringstream ss(command);
+                std::vector<std::string> words;
+                std::string tmp;
+                while (ss >> tmp)
+                    words.push_back(tmp);
+                if (words.size() > 0) {
+                    std::string verb = words.at(0);
+                    if (verb == "BLOCK") {
+                        if (words.size() != 2 || (words.at(1) != "ASYNCPATHS" && words.at(1) != "RESETPATHS"))
+                            log_warning("    ignoring unsupported LPF command '%s' (on line %d)\n", command.c_str(),
+                                        lineno);
+                    } else if (verb == "SYSCONFIG") {
+                        for (size_t i = 1; i < words.size(); i++) {
+                            std::string setting = words.at(i);
+                            size_t eqpos = setting.find('=');
+                            if (eqpos == std::string::npos)
+                                log_error("expected syntax 'SYSCONFIG <attr>=<value>...' (on line %d)\n", lineno);
+                            std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1);
+                            if (!sysconfig_keys.count(key))
+                                log_error("unexpected SYSCONFIG key '%s' (on line %d)\n", key.c_str(), lineno);
+                            settings[id("arch.sysconfig." + key)] = value;
+                        }
+                    } else if (verb == "FREQUENCY") {
+                        if (words.size() < 2)
+                            log_error("expected object type after FREQUENCY (on line %d)\n", lineno);
+                        std::string etype = words.at(1);
+                        if (etype == "PORT" || etype == "NET") {
+                            if (words.size() < 4)
+                                log_error("expected frequency value and unit after 'FREQUENCY %s' (on line %d)\n",
+                                          etype.c_str(), lineno);
+                            std::string target = strip_quotes(words.at(2));
+                            float freq = std::stof(words.at(3));
+                            std::string unit = words.at(4);
+                            boost::algorithm::to_upper(unit);
+                            if (unit == "MHZ")
+                                ;
+                            else if (unit == "KHZ")
+                                freq /= 1.0e3;
+                            else if (unit == "HZ")
+                                freq /= 1.0e6;
+                            else
+                                log_error("unsupported frequency unit '%s' (on line %d)\n", unit.c_str(), lineno);
+                            addClock(id(target), freq);
+                        } else {
+                            log_warning("    ignoring unsupported LPF command '%s %s' (on line %d)\n", command.c_str(),
+                                        etype.c_str(), lineno);
+                        }
+                    } else if (verb == "LOCATE") {
+                        if (words.size() < 5)
+                            log_error("expected syntax 'LOCATE COMP <port name> SITE <pin>' (on line %d)\n", lineno);
+                        if (words.at(1) != "COMP")
+                            log_error("expected 'COMP' after 'LOCATE' (on line %d)\n", lineno);
+                        std::string cell = strip_quotes(words.at(2));
+                        if (words.at(3) != "SITE")
+                            log_error("expected 'SITE' after 'LOCATE COMP %s' (on line %d)\n", cell.c_str(), lineno);
+                        if (words.size() > 5)
+                            log_error("unexpected input following LOCATE clause (on line %d)\n", lineno);
+                        auto fnd_cell = cells.find(id(cell));
+                        // 1-bit wires are treated as scalar by nextpnr.
+                        // In HDL they might have been a singleton vector.
+                        if (fnd_cell == cells.end() && cell.size() >= 3 && cell.substr(cell.size() - 3) == "[0]") {
+                            cell = cell.substr(0, cell.size() - 3);
+                            fnd_cell = cells.find(id(cell));
+                        }
+
+                        if (fnd_cell != cells.end()) {
+                            fnd_cell->second->attrs[id_LOC] = strip_quotes(words.at(4));
+                        }
+                    } else if (verb == "IOBUF") {
+                        if (words.size() < 3)
+                            log_error("expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n",
+                                      lineno);
+                        if (words.at(1) != "PORT")
+                            log_error("expected 'PORT' after 'IOBUF' (on line %d)\n", lineno);
+                        std::string cell = strip_quotes(words.at(2));
+                        auto fnd_cell = cells.find(id(cell));
+                        if (fnd_cell != cells.end()) {
+                            for (size_t i = 3; i < words.size(); i++) {
+                                std::string setting = words.at(i);
+                                size_t eqpos = setting.find('=');
+                                if (eqpos == std::string::npos)
+                                    log_error(
+                                            "expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n",
+                                            lineno);
+                                std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1);
+                                if (!iobuf_keys.count(key))
+                                    log_warning("IOBUF '%s' attribute '%s' is not recognised (on line %d)\n",
+                                                cell.c_str(), key.c_str(), lineno);
+                                fnd_cell->second->attrs[id(key)] = value;
+                            }
+                        }
+                    }
+                }
+
+                linebuf = linebuf.substr(scpos + 1);
+                scpos = linebuf.find(';');
+            }
+        }
+        if (!isempty(linebuf))
+            log_error("unexpected end of LPF file\n");
+        settings[id("input/lpf")] = filename;
+        return true;
+    } catch (log_execution_error_exception) {
+        return false;
+    }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/machxo2/main.cc b/machxo2/main.cc
index f21f8c3bc7..ff72ace372 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -36,6 +36,7 @@ class MachXO2CommandHandler : public CommandHandler
     virtual ~MachXO2CommandHandler(){};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
     void setupArchContext(Context *ctx) override{};
+    void customAfterLoad(Context *ctx) override;
     void customBitstream(Context *ctx) override;
 
   protected:
@@ -50,7 +51,10 @@ po::options_description MachXO2CommandHandler::getArchOptions()
     specific.add_options()("device", po::value<std::string>(), "device name");
     specific.add_options()("list-devices", "list all supported device names");
     specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
-    // specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+
+    specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+    specific.add_options()("lpf-allow-unconstrained", "don't require LPF file(s) to constrain all IO");
+
     specific.add_options()("disable-router-lutperm", "don't allow the router to permute LUT inputs");
 
     return specific;
@@ -82,6 +86,36 @@ std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string,
     return ctx;
 }
 
+void MachXO2CommandHandler::customAfterLoad(Context *ctx)
+{
+    if (vm.count("lpf")) {
+        std::vector<std::string> files = vm["lpf"].as<std::vector<std::string>>();
+        for (const auto &filename : files) {
+            std::ifstream in(filename);
+            if (!in)
+                log_error("failed to open LPF file '%s'\n", filename.c_str());
+            if (!ctx->apply_lpf(filename, in))
+                log_error("failed to parse LPF file '%s'\n", filename.c_str());
+        }
+
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") ||
+                ci->type == ctx->id("$nextpnr_iobuf")) {
+                if (!ci->attrs.count(id_LOC)) {
+                    if (vm.count("lpf-allow-unconstrained"))
+                        log_warning("IO '%s' is unconstrained in LPF and will be automatically placed\n",
+                                    cell.first.c_str(ctx));
+                    else
+                        log_error("IO '%s' is unconstrained in LPF (override this error with "
+                                  "--lpf-allow-unconstrained)\n",
+                                  cell.first.c_str(ctx));
+                }
+            }
+        }
+    }
+}
+
 int main(int argc, char *argv[])
 {
     MachXO2CommandHandler handler(argc, argv);

From 80c461bddd4b9233211b6b88403c462f8157fc51 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 2 Apr 2023 12:13:10 +0200
Subject: [PATCH 345/712] add write_bitstream to pybindings

---
 machxo2/arch_pybindings.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/machxo2/arch_pybindings.cc b/machxo2/arch_pybindings.cc
index 6bd31ff7f2..a834c52226 100644
--- a/machxo2/arch_pybindings.cc
+++ b/machxo2/arch_pybindings.cc
@@ -1,4 +1,3 @@
-
 /*
  *  nextpnr -- Next Generation Place and Route
  *
@@ -22,6 +21,7 @@
 #ifndef NO_PYTHON
 
 #include "arch_pybindings.h"
+#include "bitstream.h"
 #include "nextpnr.h"
 #include "pybindings.h"
 
@@ -70,6 +70,8 @@ void arch_wrap_python(py::module &m)
     WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
     WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
     WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
+
+    m.def("write_bitstream", &write_bitstream);
 }
 
 NEXTPNR_NAMESPACE_END

From b6bb0cd5b8740bd77b97f5628125f230687c88bd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 2 Apr 2023 12:21:26 +0200
Subject: [PATCH 346/712] Update CMakeList for machxo2

---
 machxo2/CMakeLists.txt | 32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/machxo2/CMakeLists.txt b/machxo2/CMakeLists.txt
index 7cfe5b33bb..c4f25baff6 100644
--- a/machxo2/CMakeLists.txt
+++ b/machxo2/CMakeLists.txt
@@ -25,15 +25,39 @@ else()
         "Trellis install prefix")
     message(STATUS "Trellis install prefix: ${TRELLIS_INSTALL_PREFIX}")
 
-    if(NOT DEFINED TRELLIS_LIBDIR)
+    if(NOT TRELLIS_LIBDIR)
+        # The pytrellis library isn't a normal shared library, but rather a native Python library;
+        # it does not follow the normal platform conventions for shared libraries, so we can't just
+        # use find_library() here. Instead, we emulate the useful parts of the find_library() logic
+        # for use with find_path().
+        set(pytrellis_paths)
+        foreach(prefix_path ${CMAKE_PREFIX_PATH})
+            list(APPEND pytrellis_paths ${prefix_path}/lib)
+            if(CMAKE_LIBRARY_ARCHITECTURE)
+                list(APPEND pytrellis_paths ${prefix_path}/lib/${CMAKE_LIBRARY_ARCHITECTURE})
+            endif()
+        endforeach()
+        list(APPEND pytrellis_paths ${CMAKE_LIBRARY_PATH})
+        if(NOT NO_CMAKE_SYSTEM_PATH)
+            foreach(prefix_path ${CMAKE_SYSTEM_PREFIX_PATH})
+                list(APPEND pytrellis_paths ${prefix_path}/lib)
+                if(CMAKE_LIBRARY_ARCHITECTURE)
+                    list(APPEND pytrellis_paths ${prefix_path}/lib/${CMAKE_LIBRARY_ARCHITECTURE})
+                endif()
+            endforeach()
+            list(APPEND pytrellis_paths ${CMAKE_SYSTEM_LIBRARY_PATH})
+        endif()
+        message(STATUS "Searching for pytrellis in: ${pytrellis_paths}")
+
         if(WIN32)
             set(pytrellis_lib pytrellis.pyd)
         else()
-            set(pytrellis_lib pytrellis${CMAKE_SHARED_LIBRARY_SUFFIX})
+            set(pytrellis_lib pytrellis${CMAKE_SHARED_MODULE_SUFFIX})
         endif()
+
         find_path(TRELLIS_LIBDIR ${pytrellis_lib}
             HINTS ${TRELLIS_INSTALL_PREFIX}/lib/${TRELLIS_PROGRAM_PREFIX}trellis
-            PATHS ${CMAKE_SYSTEM_LIBRARY_PATH} ${CMAKE_LIBRARY_PATH}
+            PATHS ${pytrellis_paths}
             PATH_SUFFIXES ${TRELLIS_PROGRAM_PREFIX}trellis
             DOC "Location of the pytrellis library")
         if(NOT TRELLIS_LIBDIR)
@@ -42,7 +66,7 @@ else()
     endif()
     message(STATUS "Trellis library directory: ${TRELLIS_LIBDIR}")
 
-    if(NOT DEFINED TRELLIS_DATADIR)
+    if(NOT TRELLIS_DATADIR)
         set(TRELLIS_DATADIR ${TRELLIS_INSTALL_PREFIX}/share/${TRELLIS_PROGRAM_PREFIX}trellis)
     endif()
     message(STATUS "Trellis data directory: ${TRELLIS_DATADIR}")

From 510d92e01bf2a494680ef75c0fa8ef9be4056d03 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Apr 2023 10:17:57 +0200
Subject: [PATCH 347/712] cleanup FF and made DPRAM work in simple case

---
 machxo2/bitstream.cc | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 7e62b927cb..24c466b0b8 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -291,7 +291,7 @@ struct MachXO2Bitgen
             cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
             std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
             wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
-            cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+            cc.tiles[tname].add_enum("CLK2.CLKMUX", wckmux);
         }
     }
 
@@ -303,7 +303,6 @@ struct MachXO2Bitgen
         std::string slice = std::string("SLICE") + "ABCD"[z / 2];
         std::string lc = std::to_string(z % 2);
 
-        cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
         cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
         cc.tiles[tname].add_enum(slice + ".REGMODE", str_or_default(ci->params, id_REGMODE, "FF"));
         cc.tiles[tname].add_enum(slice + ".REG" + lc + ".SD", intstr_or_default(ci->params, id_SD, "0"));
@@ -311,22 +310,15 @@ struct MachXO2Bitgen
 
         cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
 
-        NetInfo *lsrnet = ci->getPort(id_LSR);
-        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
-            cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-            cc.tiles[tname].add_enum("LSR0.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+        if (ci->getPort(id_LSR)) {
+            std::string lsr = std::string("LSR") + "0123"[z / 2];
+            cc.tiles[tname].add_enum(lsr + ".LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
+            cc.tiles[tname].add_enum(lsr + ".SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+            cc.tiles[tname].add_enum(lsr + ".LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
         }
-        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
-            cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
-            cc.tiles[tname].add_enum("LSR1.LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
-        }
-
-        NetInfo *clknet = ci->getPort(id_CLK);
-        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
-            cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
-        }
-        if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
-            cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
+        if (ci->getPort(id_CLK)) {
+            std::string clk = std::string("CLK") + "0123"[z / 2];
+            cc.tiles[tname].add_enum(clk + ".CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
         }
     }
 

From 6ec3423405f93670d7ac8ac36b9cdf591cb09cd4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Apr 2023 11:35:57 +0200
Subject: [PATCH 348/712] LSRONMUX disable if not used by FF

---
 machxo2/bitstream.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 24c466b0b8..5ede2ff6a7 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -310,11 +310,13 @@ struct MachXO2Bitgen
 
         cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
 
+        std::string lsr = std::string("LSR") + "0123"[z / 2];
         if (ci->getPort(id_LSR)) {
-            std::string lsr = std::string("LSR") + "0123"[z / 2];
             cc.tiles[tname].add_enum(lsr + ".LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
             cc.tiles[tname].add_enum(lsr + ".SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
             cc.tiles[tname].add_enum(lsr + ".LSRONMUX", str_or_default(ci->params, id_LSRONMUX, "LSRMUX"));
+        } else {
+            cc.tiles[tname].add_enum(lsr + ".LSRONMUX", "0");
         }
         if (ci->getPort(id_CLK)) {
             std::string clk = std::string("CLK") + "0123"[z / 2];

From 55518011e335477fcb4bfa5c2e881d961c2cc9a5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Apr 2023 13:53:04 +0200
Subject: [PATCH 349/712] ramw and dram changes according to @gatecat

---
 machxo2/cells.cc | 33 +++++++++------------------------
 1 file changed, 9 insertions(+), 24 deletions(-)

diff --git a/machxo2/cells.cc b/machxo2/cells.cc
index f97a16a000..d89edde8fa 100644
--- a/machxo2/cells.cc
+++ b/machxo2/cells.cc
@@ -149,15 +149,15 @@ void dram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
 {
     if (ramw->hierpath == IdString())
         ramw->hierpath = ramw->hierpath;
-    ram->movePortTo(ctx->id("WAD[0]"), ramw, id_D0);
+    ram->movePortTo(ctx->id("WAD[0]"), ramw, id_A0);
     ram->movePortTo(ctx->id("WAD[1]"), ramw, id_B0);
     ram->movePortTo(ctx->id("WAD[2]"), ramw, id_C0);
-    ram->movePortTo(ctx->id("WAD[3]"), ramw, id_A0);
+    ram->movePortTo(ctx->id("WAD[3]"), ramw, id_D0);
 
-    ram->movePortTo(ctx->id("DI[0]"), ramw, id_C1);
-    ram->movePortTo(ctx->id("DI[1]"), ramw, id_A1);
-    ram->movePortTo(ctx->id("DI[2]"), ramw, id_D1);
-    ram->movePortTo(ctx->id("DI[3]"), ramw, id_B1);
+    ram->movePortTo(ctx->id("DI[0]"), ramw, id_A1);
+    ram->movePortTo(ctx->id("DI[1]"), ramw, id_B1);
+    ram->movePortTo(ctx->id("DI[2]"), ramw, id_C1);
+    ram->movePortTo(ctx->id("DI[3]"), ramw, id_D1);
 }
 
 void ccu2_to_comb(Context *ctx, CellInfo *ccu, CellInfo *comb, NetInfo *internal_carry, int i)
@@ -199,27 +199,12 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i
     comb->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
     comb->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
 
-    unsigned permuted_init = 0;
     unsigned init = get_dram_init(ctx, ram, index);
 
-    for (int i = 0; i < 16; i++) {
-        int permuted_addr = 0;
-        if (i & 1)
-            permuted_addr |= 8;
-        if (i & 2)
-            permuted_addr |= 2;
-        if (i & 4)
-            permuted_addr |= 4;
-        if (i & 8)
-            permuted_addr |= 1;
-        if (init & (1 << permuted_addr))
-            permuted_init |= (1 << i);
-    }
-
-    comb->params[ctx->id("INITVAL")] = Property(permuted_init, 16);
+    comb->params[ctx->id("INITVAL")] = Property(init, 16);
 
     if (ram->ports.count(ctx->id("RAD[0]")))
-        comb->connectPort(id_D, ram->ports.at(ctx->id("RAD[0]")).net);
+        comb->connectPort(id_A, ram->ports.at(ctx->id("RAD[0]")).net);
 
     if (ram->ports.count(ctx->id("RAD[1]")))
         comb->connectPort(id_B, ram->ports.at(ctx->id("RAD[1]")).net);
@@ -228,7 +213,7 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i
         comb->connectPort(id_C, ram->ports.at(ctx->id("RAD[2]")).net);
 
     if (ram->ports.count(ctx->id("RAD[3]")))
-        comb->connectPort(id_A, ram->ports.at(ctx->id("RAD[3]")).net);
+        comb->connectPort(id_D, ram->ports.at(ctx->id("RAD[3]")).net);
 
     if (ram->ports.count(id_WRE))
         comb->connectPort(id_WRE, ram->ports.at(id_WRE).net);

From 5e3fe3a4dc62b6b1865d526742f465d813675d6a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Apr 2023 13:55:19 +0200
Subject: [PATCH 350/712] do not support FF on slice C when there is dpram

---
 machxo2/arch_place.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
index 1ffb99105a..9aab7b7fa6 100644
--- a/machxo2/arch_place.cc
+++ b/machxo2/arch_place.cc
@@ -148,6 +148,7 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
             CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
             if (ff != nullptr) {
                 if (found_global_dpram) {
+                    if (i==4 || i==5) return false;
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
                 }

From 9121880c5f3544ede3d1a1e1d33d2b10b4c5948f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Apr 2023 16:20:42 +0200
Subject: [PATCH 351/712] added a comment for constraining FF location

---
 machxo2/arch_place.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
index 9aab7b7fa6..6307fdb633 100644
--- a/machxo2/arch_place.cc
+++ b/machxo2/arch_place.cc
@@ -148,6 +148,7 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
             CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
             if (ff != nullptr) {
                 if (found_global_dpram) {
+                    // Do not allow SLICEC to have FF if there is already RAMW in it
                     if (i==4 || i==5) return false;
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);

From c04c9619498505bd314832dbb2e3713c5ef400c7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 6 Apr 2023 12:29:42 +0200
Subject: [PATCH 352/712] Import spine data

---
 machxo2/arch.cc          | 9 +++++++++
 machxo2/arch.h           | 4 ++++
 machxo2/facade_import.py | 6 ++++++
 3 files changed, 19 insertions(+)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 55d3a8459d..a69f97cb47 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -626,4 +626,13 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     return ret;
 }
 
+// -----------------------------------------------------------------------
+bool Arch::is_spine_row(int row) const
+{
+    for (auto &spine : chip_info->spines) {
+        if (row==spine.row) return true;
+    }
+    return false;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/arch.h b/machxo2/arch.h
index e761458267..1ef91ebce6 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -133,6 +133,8 @@ NPNR_PACKED_STRUCT(struct VariantInfoPOD {
     RelSlice<SuffixeSupportedPOD> suffixes;
 });
 
+NPNR_PACKED_STRUCT(struct SpineInfoPOD { int32_t row; });
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<char> family;
     RelPtr<char> device_name;
@@ -145,6 +147,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelSlice<PIOInfoPOD> pio_info;
     RelSlice<TileInfoPOD> tile_info;
     RelSlice<VariantInfoPOD> variants;
+    RelSlice<SpineInfoPOD> spines;
 });
 
 /************************ End of chipdb section. ************************/
@@ -960,6 +963,7 @@ struct Arch : BaseArch<ArchRanges>
         NPNR_ASSERT_FALSE_STR("no tile with type " + type);
     }
 
+    bool is_spine_row(int row) const;
     // Apply LPF constraints to the context
     bool apply_lpf(std::string filename, std::istream &in);
 
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index e07c19213e..04b16b31be 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -394,6 +394,11 @@ def get_wire_name(loc, idx):
         bba.r_slice("supported_speed_grades_%s" % name, len(var_data["speeds"]), "supported_speed_grades")
         bba.r_slice("supported_suffixes_%s" % name, len(var_data["suffixes"]), "supported_suffixes")
 
+    bba.l("spine_info", "SpineInfoPOD")
+    spines = chip.global_data_machxo2.spines
+    for spine in spines:
+        bba.u32(spine.row, "row")
+
     bba.l("chip_info")
     bba.s(chip.info.family, "family")
     bba.s(chip.info.name, "device_name")
@@ -408,6 +413,7 @@ def get_wire_name(loc, idx):
     bba.r_slice("pio_info", len(pindata), "pio_info")
     bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info")
     bba.r_slice("variant_data", len(variants), "variant_info")
+    bba.r_slice("spine_info", len(spines), "spine_info")
 
     bba.pop()
     return bba

From 4b3ae70ca8c57e28ae23d1b31c1e8c3f0d5831e6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 6 Apr 2023 12:30:17 +0200
Subject: [PATCH 353/712] support DCC and use spine data

---
 machxo2/bitstream.cc | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 5ede2ff6a7..2f63fa4549 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -95,10 +95,7 @@ struct MachXO2Bitgen
             // outside of the center row of tiles as far as the database is
             // concerned. So convert U_/D_ prefixes back to G_ if not in the
             // center row.
-
-            // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
-            // add a center row/col field to chipdb?
-            if (loc.y == 6)
+            if (ctx->is_spine_row(loc.y))
                 return basename;
             else
                 return "G_" + basename.substr(2);
@@ -334,6 +331,17 @@ struct MachXO2Bitgen
         cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
     }
 
+    void write_dcc(CellInfo *ci)
+    {
+        static const std::set<std::string> dcc = {"CENTERB", "CENTER4", "CENTER9"};
+        const NetInfo *cen = ci->getPort(id_CE);
+        if (cen != nullptr) {
+            std::string belname = ctx->tile_info(ci->bel)->bel_data[ci->bel.index].name.get();
+            std::string dcc_tile = ctx->get_tile_by_type_loc(ci->bel.location.y - 2, ci->bel.location.x, dcc);
+            cc.tiles[dcc_tile].add_enum(belname + ".MODE", "DCCA");
+        }
+    }
+
     void run()
     {
         IdString base_id = ctx->id(ctx->chip_info->device_name.get());
@@ -411,6 +419,8 @@ struct MachXO2Bitgen
                 std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
+            } else if (ci->type == id_DCCA) {
+                write_dcc(ci);
             }
         }
     }

From a79c2f32098cd35d7d24b0485b54c97fa2e4c326 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 6 Apr 2023 13:49:36 +0200
Subject: [PATCH 354/712] Add additional pic tiles

---
 machxo2/bitstream.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 2f63fa4549..ed4f785dd3 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -163,9 +163,12 @@ struct MachXO2Bitgen
                                                     "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
                                                     "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
                                                     "PIC_L2_VREF4", "PIC_L2_VREF5",
-                                                    "PIC_L3_VREF4", "PIC_L3_VREF5"};
+                                                    "PIC_L3_VREF4", "PIC_L3_VREF5",
+                                                    "LLC0PIC", "LLC1PIC", 
+                                                    "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"};
         static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
-                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256"};
+                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256",
+                                                    "LRC1PIC1", "LRC1PIC2", "URC1PIC"};
 
         std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
         if (bel.location.y == 0) {

From 1b3283fb7cff0e08ddfa12d939b9a4cedf2156b5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Apr 2023 10:18:18 +0200
Subject: [PATCH 355/712] Add constants for new bels

---
 machxo2/constids.inc | 200 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 198 insertions(+), 2 deletions(-)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 0debca1856..6d763a58fe 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -102,7 +102,6 @@ X(IOLTO)
 
 
 X(OSCH)
-X(STDBY)
 X(OSC)
 X(SEDSTDBY)
 
@@ -162,4 +161,201 @@ X(COUT)
 X(E)
 X(Y)
 
-X(WCKMUX)
\ No newline at end of file
+X(WCKMUX)
+
+X(EHXPLLJ)
+X(CLKFB)
+X(PHASESEL1)
+X(PHASESEL0)
+X(PHASEDIR)
+X(PHASESTEP)
+X(LOADREG)
+X(STDBY)
+X(PLLWAKESYNC)
+X(RST)
+X(ENCLKOP)
+X(ENCLKOS)
+X(ENCLKOS2)
+X(ENCLKOS3)
+X(CLKOP)
+X(CLKOS)
+X(CLKOS2)
+X(CLKOS3)
+X(LOCK)
+X(INTLOCK)
+X(REFCLK)
+X(CLKINTFB)
+
+X(DP8KC)
+X(DIA0)
+X(DIA1)
+X(DIA2)
+X(DIA3)
+X(DIA4)
+X(DIA5)
+X(DIA6)
+X(DIA7)
+X(DIA8)
+X(ADA0)
+X(ADA1)
+X(ADA2)
+X(ADA3)
+X(ADA4)
+X(ADA5)
+X(ADA6)
+X(ADA7)
+X(ADA8)
+X(ADA9)
+X(ADA10)
+X(ADA11)
+X(ADA12)
+X(OCEA)
+X(CLKA)
+X(WEA)
+X(CSA2)
+X(CSA1)
+X(CSA0)
+X(RSTA)
+X(DIB0)
+X(DIB1)
+X(DIB2)
+X(DIB3)
+X(DIB4)
+X(DIB5)
+X(DIB6)
+X(DIB7)
+X(DIB8)
+X(ADB0)
+X(ADB1)
+X(ADB2)
+X(ADB3)
+X(ADB4)
+X(ADB5)
+X(ADB6)
+X(ADB7)
+X(ADB8)
+X(ADB9)
+X(ADB10)
+X(ADB11)
+X(ADB12)
+X(CEB)
+X(OCEB)
+X(CLKB)
+X(WEB)
+X(CSB2)
+X(CSB1)
+X(CSB0)
+X(RSTB)
+X(DOA0)
+X(DOA1)
+X(DOA2)
+X(DOA3)
+X(DOA4)
+X(DOA5)
+X(DOA6)
+X(DOA7)
+X(DOA8)
+X(DOB0)
+X(DOB1)
+X(DOB2)
+X(DOB3)
+X(DOB4)
+X(DOB5)
+X(DOB6)
+X(DOB7)
+X(DOB8)
+X(AE)
+X(AF)
+X(EF)
+X(FF)
+X(WID)
+
+
+X(CLKI_DIV)
+X(CLKFB_DIV)
+X(CLKOP_DIV)
+X(CLKOS_DIV)
+X(CLKOS2_DIV)
+X(CLKOS3_DIV)
+X(CLOCK_ENABLE_PORTS)
+X(CLKOP_ENABLE)
+X(CLKOS_ENABLE)
+X(CLKOS2_ENABLE)
+X(CLKOS3_ENABLE)
+X(VCO_BYPASS_A0)
+X(VCO_BYPASS_B0)
+X(VCO_BYPASS_C0)
+X(VCO_BYPASS_D0)
+X(CLKOP_CPHASE)
+X(CLKOS_CPHASE)
+X(CLKOS2_CPHASE)
+X(CLKOS3_CPHASE)
+X(CLKOP_FPHASE)
+X(CLKOS_FPHASE)
+X(CLKOS2_FPHASE)
+X(CLKOS3_FPHASE)
+X(FEEDBK_PATH)
+X(KVCO)
+X(LPF_CAPACITOR)
+X(LPF_RESISTOR)
+X(ICP_CURRENT)
+X(FRACN_ENABLE)
+X(FRACN_DIV)
+X(FRACN_ORDER)
+X(CLKOP_TRIM_POL)
+X(CLKOP_TRIM_DELAY)
+X(CLKOS_TRIM_POL)
+X(CLKOS_TRIM_DELAY)
+X(PLL_EXPERT)
+X(PLL_USE_WB)
+X(PREDIVIDER_MUXA1)
+X(PREDIVIDER_MUXB1)
+X(PREDIVIDER_MUXC1)
+X(PREDIVIDER_MUXD1)
+X(OUTDIVIDER_MUXA2)
+X(OUTDIVIDER_MUXB2)
+X(OUTDIVIDER_MUXC2)
+X(OUTDIVIDER_MUXD2)
+X(FREQ_LOCK_ACCURACY)
+X(PLL_LOCK_MODE)
+X(PLL_LOCK_DELAY)
+X(GMC_GAIN)
+X(GMC_TEST)
+X(MFG1_TEST)
+X(MFG2_TEST)
+X(MFG_FORCE_VFILTER)
+X(MFG_ICP_TEST)
+X(MFG_EN_UP)
+X(MFG_FLOAT_ICP)
+X(MFG_GMC_PRESET)
+X(MFG_LF_PRESET)
+X(MFG_GMC_RESET)
+X(MFG_LF_RESET)
+X(MFG_LF_RESGRND)
+X(MFG_GMCREF_SEL)
+X(MFG_ENABLE_FILTEROPAMP)
+X(STDBY_ENABLE)
+X(REFIN_RESET)
+X(SYNC_ENABLE)
+X(INT_LOCK_STICKY)
+X(DPHASE_SOURCE)
+X(INTFB_WAKE)
+X(PLLRST_ENA)
+X(MRST_ENA)
+X(DCRST_ENA)
+X(DDRST_ENA)
+
+X(DATA_WIDTH_A)
+X(DATA_WIDTH_B)
+X(WRITEMODE_A)
+X(WRITEMODE_B)
+X(CSDECODE_A)
+X(CSDECODE_B)
+X(REGMODE_A)
+X(REGMODE_B)
+X(RESETMODE)
+X(ASYNC_RESET_RELEASE)
+X(RSTAMUX)
+X(RSTBMUX)
+X(WEAMUX)
+X(WEBMUX)

From 19176ab597fc5543661652148fe3eae1cf6b0089 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Apr 2023 10:21:13 +0200
Subject: [PATCH 356/712] Made PLL to work

---
 machxo2/arch.cc      |   2 +
 machxo2/bitstream.cc | 121 ++++++++++++++++
 machxo2/pack.cc      | 319 ++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 439 insertions(+), 3 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index a69f97cb47..d381b6c3ca 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -28,6 +28,7 @@
 #include "placer_heap.h"
 #include "router1.h"
 #include "router2.h"
+#include "timing.h"
 #include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -431,6 +432,7 @@ bool Arch::route()
     disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
 
     assignArchInfo();
+    assign_budget(getCtx(), true);
 
     bool result;
     if (router == "router1") {
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index ed4f785dd3..92e5e73251 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -184,6 +184,24 @@ struct MachXO2Bitgen
         }
     }
 
+    // Get the list of tiles corresponding to a PLL
+    std::vector<std::string> get_pll_tiles(BelId bel)
+    {
+        std::string name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+
+        if (name == "EHXPLL_L") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y-1, loc.x-1, "GPLL_L0"));
+            //tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "CIB_PIC_T_DUMMY"));
+        } else if (name == "EHXPLL_R") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y+1, loc.x-1, "GPLL_R0"));
+        } else {
+            NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+        }
+        return tiles;
+    }
+
     void set_pip(ChipConfig &cc, PipId pip)
     {
         std::string tile = ctx->get_pip_tilename(pip);
@@ -345,6 +363,107 @@ struct MachXO2Bitgen
         }
     }
 
+    void write_pll(CellInfo *ci)
+    {
+        TileGroup tg;
+        tg.tiles = get_pll_tiles(ci->bel);
+
+        tg.config.add_enum("MODE", "EHXPLLJ");
+
+        tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKI_DIV, 1) - 1, 7));
+        tg.config.add_word("CLKFB_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKFB_DIV, 1) - 1, 7));
+
+        tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, id_CLKOP_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, id_CLKOS_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, id_CLKOS2_ENABLE, "ENABLED"));
+        tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, id_CLKOS3_ENABLE, "ENABLED"));
+
+        for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
+            tg.config.add_word(out + "_DIV",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
+            tg.config.add_word(out + "_CPHASE",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
+            tg.config.add_word(out + "_FPHASE",
+                               int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+        }
+
+        tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP"));
+        tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, id_CLKOP_TRIM_POL, "RISING"));
+
+        tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOP_TRIM_DELAY, "0"));
+
+        tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, id_CLKOS_TRIM_POL, "RISING"));
+
+        tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
+
+        tg.config.add_enum("VCO_BYPASS_A0", str_or_default(ci->params, id_VCO_BYPASS_A0, "DISABLED"));
+        tg.config.add_enum("VCO_BYPASS_B0", str_or_default(ci->params, id_VCO_BYPASS_B0, "DISABLED"));
+        tg.config.add_enum("VCO_BYPASS_C0", str_or_default(ci->params, id_VCO_BYPASS_C0, "DISABLED"));
+        tg.config.add_enum("VCO_BYPASS_D0", str_or_default(ci->params, id_VCO_BYPASS_D0, "DISABLED"));
+
+        tg.config.add_word("PREDIVIDER_MUXA1", int_to_bitvector(int_or_default(ci->attrs, id_PREDIVIDER_MUXA1, 0), 2));
+        tg.config.add_word("PREDIVIDER_MUXB1", int_to_bitvector(int_or_default(ci->attrs, id_PREDIVIDER_MUXB1, 0), 2));
+        tg.config.add_word("PREDIVIDER_MUXC1", int_to_bitvector(int_or_default(ci->attrs, id_PREDIVIDER_MUXC1, 0), 2));
+        tg.config.add_word("PREDIVIDER_MUXD1", int_to_bitvector(int_or_default(ci->attrs, id_PREDIVIDER_MUXD1, 0), 2));
+        tg.config.add_enum("OUTDIVIDER_MUXA2",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXA2, ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXB2",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXB2, ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXC2",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXC2, ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK"));
+        tg.config.add_enum("OUTDIVIDER_MUXD2",
+                           str_or_default(ci->params, id_OUTDIVIDER_MUXD2, ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK"));
+
+        tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
+
+        tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, id_STDBY_ENABLE, "DISABLED"));
+        tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, id_REFIN_RESET, "DISABLED"));
+        tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, id_SYNC_ENABLE, "DISABLED"));
+        tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, id_INT_LOCK_STICKY, "ENABLED"));
+        tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, id_DPHASE_SOURCE, "DISABLED"));
+        tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
+        tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, id_INTFB_WAKE, "DISABLED"));
+        tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
+        tg.config.add_enum("MRST_ENA", str_or_default(ci->params, id_MRST_ENA, "DISABLED"));
+        tg.config.add_enum("DCRST_ENA", str_or_default(ci->params, id_DCRST_ENA, "DISABLED"));
+        tg.config.add_enum("DDRST_ENA", str_or_default(ci->params, id_DDRST_ENA, "DISABLED"));
+
+        tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, id_KVCO, 0), 3));
+        tg.config.add_word("LPF_CAPACITOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_CAPACITOR, 0), 2));
+        tg.config.add_word("LPF_RESISTOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_RESISTOR, 0), 7));
+        tg.config.add_word("ICP_CURRENT", int_to_bitvector(int_or_default(ci->attrs, id_ICP_CURRENT, 0), 5));
+        tg.config.add_word("FREQ_LOCK_ACCURACY",
+                           int_to_bitvector(int_or_default(ci->attrs, id_FREQ_LOCK_ACCURACY, 0), 2));
+
+        tg.config.add_word("GMC_GAIN", int_to_bitvector(int_or_default(ci->attrs, id_GMC_GAIN, 0), 3));
+        tg.config.add_word("GMC_TEST", int_to_bitvector(int_or_default(ci->attrs, id_GMC_TEST, 14), 4));
+        tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG1_TEST, 0), 3));
+        tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG2_TEST, 0), 3));
+
+        tg.config.add_word("MFG_FORCE_VFILTER",
+                           int_to_bitvector(int_or_default(ci->attrs, id_MFG_FORCE_VFILTER, 0), 1));
+        tg.config.add_word("MFG_ICP_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_ICP_TEST, 0), 1));
+        tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_EN_UP, 0), 1));
+        tg.config.add_word("MFG_FLOAT_ICP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_FLOAT_ICP, 0), 1));
+        tg.config.add_word("MFG_GMC_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_PRESET, 0), 1));
+        tg.config.add_word("MFG_LF_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_PRESET, 0), 1));
+        tg.config.add_word("MFG_GMC_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_RESET, 0), 1));
+        tg.config.add_word("MFG_LF_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESET, 0), 1));
+        tg.config.add_word("MFG_LF_RESGRND", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESGRND, 0), 1));
+        tg.config.add_word("MFG_GMCREF_SEL", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMCREF_SEL, 0), 2));
+        tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
+                           int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
+
+        tg.config.add_enum("CLOCK_ENABLE_PORTS", str_or_default(ci->params, id_DDRST_ENA, "DISABLED"));
+        tg.config.add_enum("PLL_EXPERT", str_or_default(ci->params, id_PLL_EXPERT, "DISABLED"));
+        tg.config.add_enum("PLL_USE_WB", str_or_default(ci->params, id_PLL_USE_WB, "DISABLED"));
+
+        tg.config.add_enum("FRACN_ENABLE", str_or_default(ci->params, id_FRACN_ENABLE, "DISABLED"));
+        tg.config.add_word("FRACN_DIV", int_to_bitvector(int_or_default(ci->attrs, id_FRACN_DIV, 0), 16));
+        tg.config.add_word("FRACN_ORDER", int_to_bitvector(int_or_default(ci->attrs, id_FRACN_ORDER, 0), 2));
+        cc.tilegroups.push_back(tg);
+    }
+
     void run()
     {
         IdString base_id = ctx->id(ctx->chip_info->device_name.get());
@@ -424,6 +543,8 @@ struct MachXO2Bitgen
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
             } else if (ci->type == id_DCCA) {
                 write_dcc(ci);
+            } else if (ci->type == id_EHXPLLJ) {
+                write_pll(ci);
             }
         }
     }
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 4dbafd72d9..9f87ba0f4f 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -49,10 +49,10 @@ static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
     }
 }
 
-class Ecp5Packer
+class MachXO2Packer
 {
   public:
-    Ecp5Packer(Context *ctx) : ctx(ctx){};
+    MachXO2Packer(Context *ctx) : ctx(ctx){};
 
   private:
     // Process the contents of packed_cells and new_cells
@@ -1012,6 +1012,60 @@ class Ecp5Packer
         }
     }
 
+    // Preplace PLL
+    void preplace_plls()
+    {
+        std::set<BelId> available_plls;
+        for (auto bel : ctx->getBels()) {
+            if (ctx->getBelType(bel) == id_EHXPLLJ && ctx->checkBelAvail(bel))
+                available_plls.insert(bel);
+        }
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_EHXPLLJ && ci->attrs.count(id_BEL))
+                available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(id_BEL).as_string()));
+        }
+        // Place PLL connected to fixed drivers such as IO close to their source
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_EHXPLLJ && !ci->attrs.count(id_BEL)) {
+                const NetInfo *drivernet = ci->getPort(id_CLKI);
+                if (drivernet == nullptr || drivernet->driver.cell == nullptr)
+                    continue;
+                const CellInfo *drivercell = drivernet->driver.cell;
+                if (!drivercell->attrs.count(id_BEL))
+                    continue;
+                BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(id_BEL).as_string());
+                Loc drvloc = ctx->getBelLocation(drvbel);
+                BelId closest_pll;
+                int closest_distance = std::numeric_limits<int>::max();
+                for (auto bel : available_plls) {
+                    Loc pllloc = ctx->getBelLocation(bel);
+                    int distance = std::abs(drvloc.x - pllloc.x) + std::abs(drvloc.y - pllloc.y);
+                    if (distance < closest_distance) {
+                        closest_pll = bel;
+                        closest_distance = distance;
+                    }
+                }
+                if (closest_pll == BelId())
+                    log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
+                available_plls.erase(closest_pll);
+                ci->attrs[id_BEL] = ctx->getBelName(closest_pll).str(ctx);
+            }
+        }
+        // Place PLLs driven by logic, etc, randomly
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_EHXPLLJ && !ci->attrs.count(id_BEL)) {
+                if (available_plls.empty())
+                    log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
+                BelId next_pll = *(available_plls.begin());
+                available_plls.erase(next_pll);
+                ci->attrs[id_BEL] = ctx->getBelName(next_pll).str(ctx);
+            }
+        }
+    }
+
     // Check if two nets have identical constant drivers
     bool equal_constant(NetInfo *a, NetInfo *b)
     {
@@ -1079,6 +1133,263 @@ class Ecp5Packer
             log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
     }
 
+    void generate_constraints()
+    {
+        log_info("Generating derived timing constraints...\n");
+        auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
+
+        auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
+        auto equals_epsilon_pair = [&](DelayPair &a, DelayPair &b) {
+            return equals_epsilon(a.min_delay, b.min_delay) && equals_epsilon(a.max_delay, b.max_delay);
+        };
+        auto equals_epsilon_constr = [&](ClockConstraint &a, ClockConstraint &b) {
+            return equals_epsilon_pair(a.high, b.high) && equals_epsilon_pair(a.low, b.low) &&
+                   equals_epsilon_pair(a.period, b.period);
+        };
+
+        pool<IdString> user_constrained, changed_nets;
+        for (auto &net : ctx->nets) {
+            if (net.second->clkconstr != nullptr)
+                user_constrained.insert(net.first);
+            changed_nets.insert(net.first);
+        }
+        auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
+            if (!ci->ports.count(port))
+                return false;
+            NetInfo *from = ci->ports.at(port).net;
+            if (from == nullptr || from->clkconstr == nullptr)
+                return false;
+            period = from->clkconstr->period.minDelay();
+            return true;
+        };
+
+        auto simple_clk_contraint = [&](delay_t period) {
+            auto constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+            constr->low = DelayPair(period / 2);
+            constr->high = DelayPair(period / 2);
+            constr->period = DelayPair(period);
+
+            return constr;
+        };
+
+        auto set_constraint = [&](CellInfo *ci, IdString port, std::unique_ptr<ClockConstraint> constr) {
+            if (!ci->ports.count(port))
+                return;
+            NetInfo *to = ci->ports.at(port).net;
+            if (to == nullptr)
+                return;
+            if (to->clkconstr != nullptr) {
+                if (!equals_epsilon_constr(*to->clkconstr, *constr) && user_constrained.count(to->name))
+                    log_warning(
+                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+                            "%.1f MHz.\n",
+                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(constr->period.min_delay));
+                return;
+            }
+            to->clkconstr = std::move(constr);
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
+                     to->name.c_str(ctx));
+            changed_nets.insert(to->name);
+        };
+
+        auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
+            if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
+                return;
+            NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
+            if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
+                return;
+            if (to->clkconstr != nullptr) {
+                if (!equals_epsilon(to->clkconstr->period.minDelay(),
+                                    delay_t(from->clkconstr->period.minDelay() / ratio)) &&
+                    user_constrained.count(to->name))
+                    log_warning(
+                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+                            "%.1f MHz.\n",
+                            MHz(to->clkconstr->period.minDelay()), to->name.c_str(ctx),
+                            MHz(delay_t(from->clkconstr->period.minDelay() / ratio)));
+                return;
+            }
+            to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+            to->clkconstr->low =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio));
+            to->clkconstr->high =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio));
+            to->clkconstr->period =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio));
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
+                     to->name.c_str(ctx));
+            changed_nets.insert(to->name);
+        };
+
+        // Run in a loop while constraints are changing to deal with dependencies
+        // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc)
+        int iter = 0;
+        const int itermax = 5000;
+        while (!changed_nets.empty() && iter < itermax) {
+            ++iter;
+            pool<IdString> changed_cells;
+            for (auto net : changed_nets) {
+                for (auto &user : ctx->nets.at(net)->users)
+                    if (user.port.in(id_CLKI, /*id_ECLKI,*/ id_CLK0, id_CLK1))
+                        changed_cells.insert(user.cell->name);
+                auto &drv = ctx->nets.at(net)->driver;
+                if (iter == 1 && drv.cell != nullptr && drv.port == id_OSC)
+                    changed_cells.insert(drv.cell->name);
+            }
+            changed_nets.clear();
+            for (auto cell : changed_cells) {
+                CellInfo *ci = ctx->cells.at(cell).get();
+/*                if (ci->type == id_CLKDIVF) {
+                    std::string div = str_or_default(ci->params, id_DIV, "2.0");
+                    double ratio;
+                    if (div == "2.0")
+                        ratio = 1 / 2.0;
+                    else if (div == "3.5")
+                        ratio = 1 / 3.5;
+                    else
+                        log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
+                    copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
+                } else if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) {
+                    copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
+                } else if (ci->type == id_ECLKBRIDGECS) {
+                    copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
+                    copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
+                } else */
+                if (ci->type == id_DCCA) {
+                    copy_constraint(ci, id_CLKI, id_CLKO, 1);
+                /*} else if (ci->type == id_DCSC) {
+                    if ((!ci->ports.count(id_CLK0) && !ci->ports.count(id_CLK1)) || !ci->ports.count(id_DCSOUT))
+                        continue;
+
+                    auto mode = str_or_default(ci->params, id_DCSMODE, "POS");
+                    bool mode_constant = false;
+                    auto mode_is_constant = net_is_constant(ctx, ci->ports.at(id_MODESEL).net, mode_constant);
+
+                    if (mode_is_constant && mode_constant == false) {
+                        if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
+                            copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
+                            continue;
+                        } else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
+                            copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
+                            continue;
+                        } else if (mode == "LOW" || mode == "HIGH") {
+                            continue;
+                        }
+                    }
+
+                    std::unique_ptr<ClockConstraint> derived_constr = nullptr;
+                    std::vector<NetInfo *> in_ports = {
+                            ci->ports.at(id_CLK0).net,
+                            ci->ports.at(id_CLK1).net,
+                    };
+
+                    // Generate all unique clock pairs find the worst
+                    // constraint from switching between them and merge them
+                    // into the final output constraint.
+                    for (size_t i = 0; i < in_ports.size(); ++i) {
+                        auto p1 = in_ports[i];
+                        if (p1 == nullptr || p1->clkconstr == nullptr) {
+                            derived_constr = nullptr;
+                            break;
+                        }
+                        for (size_t j = i + 1; j < in_ports.size(); ++j) {
+                            auto p2 = in_ports[j];
+                            if (p2 == nullptr || p2->clkconstr == nullptr) {
+                                break;
+                            }
+                            auto &c1 = p1->clkconstr;
+                            auto &c2 = p2->clkconstr;
+
+                            auto merged_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+
+                            if (mode == "NEG") {
+                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
+                                                               std::max(c1->low.max_delay + c2->period.max_delay,
+                                                                        c2->low.max_delay + c1->period.max_delay));
+                            } else {
+                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
+                                                               std::max(c1->low.max_delay, c2->low.max_delay));
+                            }
+
+                            if (mode == "POS") {
+                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
+                                                                std::max(c1->high.max_delay + c2->period.max_delay,
+                                                                         c2->high.max_delay + c1->period.max_delay));
+                            } else {
+                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
+                                                                std::max(c1->high.max_delay, c2->high.max_delay));
+                            }
+
+                            merged_constr->period = DelayPair(std::min(c1->period.min_delay, c2->period.min_delay),
+                                                              std::max(c1->period.max_delay, c2->period.max_delay));
+
+                            if (derived_constr == nullptr) {
+                                derived_constr = std::move(merged_constr);
+                                continue;
+                            }
+
+                            derived_constr->period.min_delay =
+                                    std::min(derived_constr->period.min_delay, merged_constr->period.min_delay);
+                            derived_constr->period.max_delay =
+                                    std::max(derived_constr->period.max_delay, merged_constr->period.max_delay);
+                            derived_constr->low.min_delay =
+                                    std::min(derived_constr->low.min_delay, merged_constr->low.min_delay);
+                            derived_constr->low.max_delay =
+                                    std::max(derived_constr->low.max_delay, merged_constr->low.max_delay);
+                            derived_constr->high.min_delay =
+                                    std::min(derived_constr->high.min_delay, merged_constr->high.min_delay);
+                            derived_constr->high.max_delay =
+                                    std::max(derived_constr->high.max_delay, merged_constr->high.max_delay);
+                        }
+                    }
+
+                    if (derived_constr != nullptr) {
+                        set_constraint(ci, id_DCSOUT, std::move(derived_constr));
+                    }*/
+                } else if (ci->type == id_EHXPLLJ) {
+                    delay_t period_in;
+                    if (!get_period(ci, id_CLKI, period_in))
+                        continue;
+                    log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
+                             MHz(period_in));
+                    double period_in_div = period_in * int_or_default(ci->params, id_CLKI_DIV, 1);
+                    std::string path = str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP");
+                    int feedback_div = int_or_default(ci->params, id_CLKFB_DIV, 1);
+                    if (path == "CLKOP" || path == "INT_OP")
+                        feedback_div *= int_or_default(ci->params, id_CLKOP_DIV, 1);
+                    else if (path == "CLKOS" || path == "INT_OS")
+                        feedback_div *= int_or_default(ci->params, id_CLKOS_DIV, 1);
+                    else if (path == "CLKOS2" || path == "INT_OS2")
+                        feedback_div *= int_or_default(ci->params, id_CLKOS2_DIV, 1);
+                    else if (path == "CLKOS3" || path == "INT_OS3")
+                        feedback_div *= int_or_default(ci->params, id_CLKOS3_DIV, 1);
+                    else {
+                        log_info("     Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
+                                 ci->name.c_str(ctx), path.c_str());
+                        continue;
+                    }
+                    double vco_period = period_in_div / feedback_div;
+                    double vco_freq = MHz(vco_period);
+                    if (vco_freq < 400 || vco_freq > 800)
+                        log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
+                                 "800MHz]\n",
+                                 vco_freq, ci->name.c_str(ctx));
+                    set_constraint(ci, id_CLKOP,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
+                    set_constraint(ci, id_CLKOS,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
+                    set_constraint(ci, id_CLKOS2,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
+                    set_constraint(ci, id_CLKOS3,
+                                   simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
+                }/* else if (ci->type == id_OSCH) {
+                    int div = int_or_default(ci->params, id_DIV, 128);
+                    set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));
+                }*/
+            }
+        }
+    }
+
     void prepack_checks()
     {
         // Check for legacy-style JSON (use CEMUX as a clue) and error out, avoiding a confusing assertion failure
@@ -1096,12 +1407,14 @@ class Ecp5Packer
         prepack_checks();
         print_logic_usage();
         pack_io();
+        preplace_plls();
         pack_constants();
         pack_dram();
         pack_carries();
         pack_luts();
         pack_lut5xs();
         pack_ffs();
+        generate_constraints();
         ctx->fixupHierarchy();
         ctx->check();
     }
@@ -1131,7 +1444,7 @@ bool Arch::pack()
     Context *ctx = getCtx();
     try {
         log_break();
-        Ecp5Packer(ctx).pack();
+        MachXO2Packer(ctx).pack();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         assignArchInfo();
         ctx->settings[id_pack] = 1;

From 3a7770dca257392259204377e3bf0b77b41f7626 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Apr 2023 11:16:57 +0200
Subject: [PATCH 357/712] Add missing bel pins

---
 machxo2/constids.inc | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 6d763a58fe..3c756607ca 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -165,18 +165,38 @@ X(WCKMUX)
 
 X(EHXPLLJ)
 X(CLKFB)
-X(PHASESEL1)
 X(PHASESEL0)
+X(PHASESEL1)
 X(PHASEDIR)
 X(PHASESTEP)
 X(LOADREG)
 X(STDBY)
 X(PLLWAKESYNC)
 X(RST)
+X(RESETM)
+X(RESETC)
+X(RESETD)
 X(ENCLKOP)
 X(ENCLKOS)
 X(ENCLKOS2)
 X(ENCLKOS3)
+X(PLLCLK)
+X(PLLRST)
+X(PLLSTB)
+X(PLLWE)
+X(PLLDATI0)
+X(PLLDATI1)
+X(PLLDATI2)
+X(PLLDATI3)
+X(PLLDATI4)
+X(PLLDATI5)
+X(PLLDATI6)
+X(PLLDATI7)
+X(PLLADDR0)
+X(PLLADDR1)
+X(PLLADDR2)
+X(PLLADDR3)
+X(PLLADDR4)
 X(CLKOP)
 X(CLKOS)
 X(CLKOS2)
@@ -185,6 +205,16 @@ X(LOCK)
 X(INTLOCK)
 X(REFCLK)
 X(CLKINTFB)
+X(DPHSRC)
+X(PLLDATO0)
+X(PLLDATO1)
+X(PLLDATO2)
+X(PLLDATO3)
+X(PLLDATO4)
+X(PLLDATO5)
+X(PLLDATO6)
+X(PLLDATO7)
+X(PLLACK)
 
 X(DP8KC)
 X(DIA0)

From 8c38e7ba6170e2d1d35afbeb65650322fabf52ce Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 10 Apr 2023 14:27:36 +0200
Subject: [PATCH 358/712] Working BRAM

---
 machxo2/bitstream.cc | 136 +++++++++++++++++++++++++++++++++++++++++++
 machxo2/pack.cc      | 114 ++++++++++++++++++++++++++++++++++++
 2 files changed, 250 insertions(+)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 92e5e73251..3b44785d3d 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -154,6 +154,53 @@ struct MachXO2Bitgen
         return bv;
     }
 
+    inline int chtohex(char c)
+    {
+        static const std::string hex = "0123456789ABCDEF";
+        return hex.find(std::toupper(c));
+    }
+
+    std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)
+    {
+        // Parse a string that may be binary or hex
+        std::vector<bool> result;
+        result.resize(length, false);
+        if (p.is_string) {
+            std::string str = p.as_string();
+            NPNR_ASSERT(str.substr(0, 2) == "0x");
+            // Lattice style hex string
+            if (int(str.length()) > (2 + ((length + 3) / 4)))
+                log_error("hex string value too long, expected up to %d chars and found %d.\n",
+                          (2 + ((length + 3) / 4)), int(str.length()));
+            for (int i = 0; i < int(str.length()) - 2; i++) {
+                char c = str.at((str.size() - i) - 1);
+                int nibble = chtohex(c);
+                if (nibble == (int)std::string::npos)
+                    log_error("hex string has invalid char '%c' at position %d.\n", c, i);
+                result.at(i * 4) = nibble & 0x1;
+                if (i * 4 + 1 < length)
+                    result.at(i * 4 + 1) = nibble & 0x2;
+                if (i * 4 + 2 < length)
+                    result.at(i * 4 + 2) = nibble & 0x4;
+                if (i * 4 + 3 < length)
+                    result.at(i * 4 + 3) = nibble & 0x8;
+            }
+        } else {
+            result = p.as_bits();
+            result.resize(length, false);
+        }
+        return result;
+    }
+
+    inline uint16_t bit_reverse(uint16_t x, int size)
+    {
+        uint16_t y = 0;
+        for (int i = 0; i < size; i++)
+            if (x & (1 << i))
+                y |= (1 << ((size - 1) - i));
+        return y;
+    }
+
     // Get the PIC tile corresponding to a PIO bel
     std::string get_pic_tile(BelId bel)
     {
@@ -184,6 +231,21 @@ struct MachXO2Bitgen
         }
     }
 
+    // Get the list of tiles corresponding to a blockram
+    std::vector<std::string> get_bram_tiles(BelId bel)
+    {
+        std::vector<std::string> tiles;
+        Loc loc = ctx->getBelLocation(bel);
+
+        static const std::set<std::string> ebr0 = {"EBR0", "EBR0_END", "EBR0_10K", "EBR0_END_10K"};
+        static const std::set<std::string> ebr1 = {"EBR1", "EBR1_10K"};
+        static const std::set<std::string> ebr2 = {"EBR2", "EBR2_END", "EBR2_10K", "EBR2_END_10K"};
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, ebr1));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, ebr2));
+        return tiles;
+    }
+
     // Get the list of tiles corresponding to a PLL
     std::vector<std::string> get_pll_tiles(BelId bel)
     {
@@ -363,6 +425,78 @@ struct MachXO2Bitgen
         }
     }
 
+    void write_bram(CellInfo *ci)
+    {
+        TileGroup tg;
+        tg.tiles = get_bram_tiles(ci->bel);
+        std::string ebr = "EBR";
+
+        if (ci->ramInfo.is_pdp) {
+            tg.config.add_enum(ebr + ".MODE", "PDPW8KC");
+            tg.config.add_enum(ebr + ".PDPW8KC.DATA_WIDTH_R", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
+            tg.config.add_enum(ebr + ".FIFO8KB.DATA_WIDTH_W", "18"); // default for PDPW8KC
+        } else {
+            tg.config.add_enum(ebr + ".MODE", "DP8KC");
+            tg.config.add_enum(ebr + ".DP8KC.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
+            tg.config.add_enum(ebr + ".DP8KC.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
+            tg.config.add_enum(ebr + ".DP8KC.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
+            tg.config.add_enum(ebr + ".DP8KC.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
+        }
+
+        auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
+             csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
+
+        tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
+        tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
+
+        tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
+        tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE", str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
+        tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+
+        tg.config.add_word(ebr + ".WID", int_to_bitvector(int_or_default(ci->attrs, id_WID, 0), 9));
+
+       // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
+        for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
+            for (int bit = 0; bit < 3; bit++) {
+                std::string sig = port.first + std::to_string(bit);
+                if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
+                    port.second.at(bit) = !port.second.at(bit);
+            }
+        }
+        tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
+        tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
+        if (!ci->ramInfo.is_pdp) {
+            tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
+            tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
+
+        }
+        std::reverse(csd_a.begin(), csd_a.end());
+        std::reverse(csd_b.begin(), csd_b.end());
+
+        tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
+        tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
+
+        std::vector<uint16_t> init_data;
+        init_data.resize(1024, 0x0);
+        // INIT_00 .. INIT_1F
+        for (int i = 0; i <= 0x1F; i++) {
+            IdString param = ctx->idf("INITVAL_%02X", i);
+            auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
+            for (int j = 0; j < 16; j++) {
+                // INIT parameter consists of 16 18-bit words with 2-bit padding
+                int ofs = 20 * j;
+                for (int k = 0; k < 18; k++) {
+                    if (value.at(ofs + k))
+                        init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
+                }
+            }
+        }
+        int wid = int_or_default(ci->attrs, id_WID, 0);
+        NPNR_ASSERT(!cc.bram_data.count(wid));
+        cc.bram_data[wid] = init_data;
+        cc.tilegroups.push_back(tg);
+    }
+
     void write_pll(CellInfo *ci)
     {
         TileGroup tg;
@@ -543,6 +677,8 @@ struct MachXO2Bitgen
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
             } else if (ci->type == id_DCCA) {
                 write_dcc(ci);
+            } else if (ci->type == id_DP8KC) {
+                write_bram(ci);
             } else if (ci->type == id_EHXPLLJ) {
                 write_pll(ci);
             }
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 9f87ba0f4f..6728e41dfa 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1012,6 +1012,107 @@ class MachXO2Packer
         }
     }
 
+    // Pack EBR
+    void pack_ebr()
+    {
+        // Autoincrement WID (starting from 3 seems to match vendor behaviour?)
+        int wid = 3;
+        auto rename_bus = [&](CellInfo *c, const std::string &oldname, const std::string &newname, int width,
+                              int oldoffset, int newoffset) {
+            for (int i = 0; i < width; i++)
+                c->renamePort(ctx->id(oldname + std::to_string(i + oldoffset)),
+                              ctx->id(newname + std::to_string(i + newoffset)));
+        };
+        auto rename_param = [&](CellInfo *c, const std::string &oldname, const std::string &newname) {
+            IdString o = ctx->id(oldname), n = ctx->id(newname);
+            if (!c->params.count(o))
+                return;
+            c->params[n] = c->params[o];
+            c->params.erase(o);
+        };
+        /*for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            // Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
+            if (ci->type == id_PDPW8KC) {
+                ci->params[id_DATA_WIDTH_A] = 18; // force PDP mode
+                ci->params.erase(id_DATA_WIDTH_W);
+                rename_bus(ci, "BE", "ADA", 4, 0, 0);
+                rename_bus(ci, "ADW", "ADA", 9, 0, 5);
+                rename_bus(ci, "ADR", "ADB", 14, 0, 0);
+                rename_bus(ci, "CSW", "CSA", 3, 0, 0);
+                rename_bus(ci, "CSR", "CSB", 3, 0, 0);
+                rename_bus(ci, "DI", "DIA", 18, 0, 0);
+                rename_bus(ci, "DI", "DIB", 18, 18, 0);
+                rename_bus(ci, "DO", "DOA", 18, 18, 0);
+                rename_bus(ci, "DO", "DOB", 18, 0, 0);
+                ci->renamePort(id_CLKW, id_CLKA);
+                ci->renamePort(id_CLKR, id_CLKB);
+                ci->renamePort(id_CEW, id_CEA);
+                ci->renamePort(id_CER, id_CEB);
+                ci->renamePort(id_OCER, id_OCEB);
+                rename_param(ci, "CLKWMUX", "CLKAMUX");
+                if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
+                    ci->params[id_CLKAMUX] = std::string("CLKA");
+                rename_param(ci, "CLKRMUX", "CLKBMUX");
+                if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
+                    ci->params[id_CLKBMUX] = std::string("CLKB");
+                rename_param(ci, "CSDECODE_W", "CSDECODE_A");
+                rename_param(ci, "CSDECODE_R", "CSDECODE_B");
+                std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
+                ci->params[id_REGMODE_A] = outreg;
+                ci->params[id_REGMODE_B] = outreg;
+                ci->params.erase(id_REGMODE);
+                rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
+                if (ci->ports.count(id_RST)) {
+                    autocreate_empty_port(ci, id_RSTA);
+                    autocreate_empty_port(ci, id_RSTB);
+                    NetInfo *rst = ci->ports.at(id_RST).net;
+                    ci->connectPort(id_RSTA, rst);
+                    ci->connectPort(id_RSTB, rst);
+                    ci->disconnectPort(id_RST);
+                    ci->ports.erase(id_RST);
+                }
+                ci->type = id_DP8KC;
+            }
+        }*/
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_DP8KC) {
+                // Add ports, even if disconnected, to ensure correct tie-offs
+                for (int i = 0; i < 13; i++) {
+                    autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i)));
+                    autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i)));
+                }
+                for (int i = 0; i < 9; i++) {
+                    autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i)));
+                    autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i)));
+                }
+                for (int i = 0; i < 3; i++) {
+                    autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
+                    autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
+                }
+                for (int i = 0; i < 3; i++) {
+                    autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
+                    autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
+                }
+
+                autocreate_empty_port(ci, id_CLKA);
+                autocreate_empty_port(ci, id_CEA);
+                autocreate_empty_port(ci, id_OCEA);
+                autocreate_empty_port(ci, id_WEA);
+                autocreate_empty_port(ci, id_RSTA);
+
+                autocreate_empty_port(ci, id_CLKB);
+                autocreate_empty_port(ci, id_CEB);
+                autocreate_empty_port(ci, id_OCEB);
+                autocreate_empty_port(ci, id_WEB);
+                autocreate_empty_port(ci, id_RSTB);
+
+                ci->attrs[id_WID] = wid++;
+            }
+        }
+    }
+
     // Preplace PLL
     void preplace_plls()
     {
@@ -1408,6 +1509,7 @@ class MachXO2Packer
         print_logic_usage();
         pack_io();
         preplace_plls();
+        pack_ebr();
         pack_constants();
         pack_dram();
         pack_carries();
@@ -1510,6 +1612,18 @@ void Arch::assign_arch_info_for_cell(CellInfo *ci)
         ci->ffInfo.clk_sig = get_port_net(ci, id_CLK);
         ci->ffInfo.ce_sig = get_port_net(ci, id_CE);
         ci->ffInfo.lsr_sig = get_port_net(ci, id_LSR);
+    } else if (ci->type == id_DP8KC) {
+        ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 18);
+
+        // Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
+        std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
+        if (regmode_a != "NOREG" && regmode_a != "OUTREG")
+            log_error("DP8KC %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this), regmode_a.c_str());
+        std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
+        if (regmode_b != "NOREG" && regmode_b != "OUTREG")
+            log_error("DP8KC %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this), regmode_b.c_str());
+        ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
+        ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
     }
 }
 

From 437b57a510122a805a4c0b924bd8cb05a157416f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 11 Apr 2023 09:18:46 +0200
Subject: [PATCH 359/712] Added getBelGlobalBuf

---
 machxo2/arch.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/arch.h b/machxo2/arch.h
index 1ef91ebce6..fbb1d3b5bf 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -561,7 +561,7 @@ struct Arch : BaseArch<ArchRanges>
     BelId getBelByLocation(Loc loc) const override;
     BelRange getBelsByTile(int x, int y) const override;
 
-    bool getBelGlobalBuf(BelId bel) const override { return false; }
+    bool getBelGlobalBuf(BelId bel) const override { return getBelType(bel) == id_DCCA; }
 
     bool checkBelAvail(BelId bel) const override
     {

From 3281ca6717ffb6bbb7dd0e81726203b969b5eeff Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 13 Apr 2023 17:25:29 +0200
Subject: [PATCH 360/712] Add missing muxes for BRAM

---
 machxo2/bitstream.cc | 14 ++++++++++++++
 machxo2/constids.inc |  7 ++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 3b44785d3d..fb48fe6ed6 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -243,6 +243,12 @@ struct MachXO2Bitgen
         tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
         tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, ebr1));
         tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, ebr2));
+        static const std::set<std::string> cib_ebr0 = {"CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3", "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"};
+        static const std::set<std::string> cib_ebr1 = {"CIB_EBR1", "CIB_EBR1_10K"};
+        static const std::set<std::string> cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0", "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"};
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, cib_ebr0));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, cib_ebr1));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, cib_ebr2));
         return tiles;
     }
 
@@ -463,6 +469,9 @@ struct MachXO2Bitgen
                     port.second.at(bit) = !port.second.at(bit);
             }
         }
+        tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, id_CLKAMUX, "CLKA"));
+        tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, id_CLKBMUX, "CLKB"));
+
         tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
         tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
         if (!ci->ramInfo.is_pdp) {
@@ -470,6 +479,11 @@ struct MachXO2Bitgen
             tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
 
         }
+        tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
+        tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
+        tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, id_OCEAMUX, "OCEA"));
+        tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, id_OCEBMUX, "OCEB"));
+
         std::reverse(csd_a.begin(), csd_a.end());
         std::reverse(csd_b.begin(), csd_b.end());
 
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 3c756607ca..1f2e8d248e 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -299,7 +299,12 @@ X(AF)
 X(EF)
 X(FF)
 X(WID)
-
+X(CLKAMUX)
+X(CLKBMUX)
+X(CEAMUX)
+X(CEBMUX)
+X(OCEAMUX)
+X(OCEBMUX)
 
 X(CLKI_DIV)
 X(CLKFB_DIV)

From c6f1f124f2bbf631cbcdb2478d92b929f66b5ea4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 13 Apr 2023 20:10:47 +0200
Subject: [PATCH 361/712] removed commented and not used code

---
 machxo2/arch.cc |   1 -
 machxo2/pack.cc | 155 +-----------------------------------------------
 2 files changed, 1 insertion(+), 155 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index d381b6c3ca..6092d9bde1 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -432,7 +432,6 @@ bool Arch::route()
     disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
 
     assignArchInfo();
-    assign_budget(getCtx(), true);
 
     bool result;
     if (router == "router1") {
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 6728e41dfa..98d29854e5 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1030,51 +1030,6 @@ class MachXO2Packer
             c->params[n] = c->params[o];
             c->params.erase(o);
         };
-        /*for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            // Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
-            if (ci->type == id_PDPW8KC) {
-                ci->params[id_DATA_WIDTH_A] = 18; // force PDP mode
-                ci->params.erase(id_DATA_WIDTH_W);
-                rename_bus(ci, "BE", "ADA", 4, 0, 0);
-                rename_bus(ci, "ADW", "ADA", 9, 0, 5);
-                rename_bus(ci, "ADR", "ADB", 14, 0, 0);
-                rename_bus(ci, "CSW", "CSA", 3, 0, 0);
-                rename_bus(ci, "CSR", "CSB", 3, 0, 0);
-                rename_bus(ci, "DI", "DIA", 18, 0, 0);
-                rename_bus(ci, "DI", "DIB", 18, 18, 0);
-                rename_bus(ci, "DO", "DOA", 18, 18, 0);
-                rename_bus(ci, "DO", "DOB", 18, 0, 0);
-                ci->renamePort(id_CLKW, id_CLKA);
-                ci->renamePort(id_CLKR, id_CLKB);
-                ci->renamePort(id_CEW, id_CEA);
-                ci->renamePort(id_CER, id_CEB);
-                ci->renamePort(id_OCER, id_OCEB);
-                rename_param(ci, "CLKWMUX", "CLKAMUX");
-                if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
-                    ci->params[id_CLKAMUX] = std::string("CLKA");
-                rename_param(ci, "CLKRMUX", "CLKBMUX");
-                if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
-                    ci->params[id_CLKBMUX] = std::string("CLKB");
-                rename_param(ci, "CSDECODE_W", "CSDECODE_A");
-                rename_param(ci, "CSDECODE_R", "CSDECODE_B");
-                std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
-                ci->params[id_REGMODE_A] = outreg;
-                ci->params[id_REGMODE_B] = outreg;
-                ci->params.erase(id_REGMODE);
-                rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
-                if (ci->ports.count(id_RST)) {
-                    autocreate_empty_port(ci, id_RSTA);
-                    autocreate_empty_port(ci, id_RSTB);
-                    NetInfo *rst = ci->ports.at(id_RST).net;
-                    ci->connectPort(id_RSTA, rst);
-                    ci->connectPort(id_RSTB, rst);
-                    ci->disconnectPort(id_RST);
-                    ci->ports.erase(id_RST);
-                }
-                ci->type = id_DP8KC;
-            }
-        }*/
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_DP8KC) {
@@ -1340,113 +1295,8 @@ class MachXO2Packer
             changed_nets.clear();
             for (auto cell : changed_cells) {
                 CellInfo *ci = ctx->cells.at(cell).get();
-/*                if (ci->type == id_CLKDIVF) {
-                    std::string div = str_or_default(ci->params, id_DIV, "2.0");
-                    double ratio;
-                    if (div == "2.0")
-                        ratio = 1 / 2.0;
-                    else if (div == "3.5")
-                        ratio = 1 / 3.5;
-                    else
-                        log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
-                    copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
-                } else if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) {
-                    copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
-                } else if (ci->type == id_ECLKBRIDGECS) {
-                    copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
-                    copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
-                } else */
                 if (ci->type == id_DCCA) {
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
-                /*} else if (ci->type == id_DCSC) {
-                    if ((!ci->ports.count(id_CLK0) && !ci->ports.count(id_CLK1)) || !ci->ports.count(id_DCSOUT))
-                        continue;
-
-                    auto mode = str_or_default(ci->params, id_DCSMODE, "POS");
-                    bool mode_constant = false;
-                    auto mode_is_constant = net_is_constant(ctx, ci->ports.at(id_MODESEL).net, mode_constant);
-
-                    if (mode_is_constant && mode_constant == false) {
-                        if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
-                            copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
-                            continue;
-                        } else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
-                            copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
-                            continue;
-                        } else if (mode == "LOW" || mode == "HIGH") {
-                            continue;
-                        }
-                    }
-
-                    std::unique_ptr<ClockConstraint> derived_constr = nullptr;
-                    std::vector<NetInfo *> in_ports = {
-                            ci->ports.at(id_CLK0).net,
-                            ci->ports.at(id_CLK1).net,
-                    };
-
-                    // Generate all unique clock pairs find the worst
-                    // constraint from switching between them and merge them
-                    // into the final output constraint.
-                    for (size_t i = 0; i < in_ports.size(); ++i) {
-                        auto p1 = in_ports[i];
-                        if (p1 == nullptr || p1->clkconstr == nullptr) {
-                            derived_constr = nullptr;
-                            break;
-                        }
-                        for (size_t j = i + 1; j < in_ports.size(); ++j) {
-                            auto p2 = in_ports[j];
-                            if (p2 == nullptr || p2->clkconstr == nullptr) {
-                                break;
-                            }
-                            auto &c1 = p1->clkconstr;
-                            auto &c2 = p2->clkconstr;
-
-                            auto merged_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-
-                            if (mode == "NEG") {
-                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
-                                                               std::max(c1->low.max_delay + c2->period.max_delay,
-                                                                        c2->low.max_delay + c1->period.max_delay));
-                            } else {
-                                merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
-                                                               std::max(c1->low.max_delay, c2->low.max_delay));
-                            }
-
-                            if (mode == "POS") {
-                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
-                                                                std::max(c1->high.max_delay + c2->period.max_delay,
-                                                                         c2->high.max_delay + c1->period.max_delay));
-                            } else {
-                                merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
-                                                                std::max(c1->high.max_delay, c2->high.max_delay));
-                            }
-
-                            merged_constr->period = DelayPair(std::min(c1->period.min_delay, c2->period.min_delay),
-                                                              std::max(c1->period.max_delay, c2->period.max_delay));
-
-                            if (derived_constr == nullptr) {
-                                derived_constr = std::move(merged_constr);
-                                continue;
-                            }
-
-                            derived_constr->period.min_delay =
-                                    std::min(derived_constr->period.min_delay, merged_constr->period.min_delay);
-                            derived_constr->period.max_delay =
-                                    std::max(derived_constr->period.max_delay, merged_constr->period.max_delay);
-                            derived_constr->low.min_delay =
-                                    std::min(derived_constr->low.min_delay, merged_constr->low.min_delay);
-                            derived_constr->low.max_delay =
-                                    std::max(derived_constr->low.max_delay, merged_constr->low.max_delay);
-                            derived_constr->high.min_delay =
-                                    std::min(derived_constr->high.min_delay, merged_constr->high.min_delay);
-                            derived_constr->high.max_delay =
-                                    std::max(derived_constr->high.max_delay, merged_constr->high.max_delay);
-                        }
-                    }
-
-                    if (derived_constr != nullptr) {
-                        set_constraint(ci, id_DCSOUT, std::move(derived_constr));
-                    }*/
                 } else if (ci->type == id_EHXPLLJ) {
                     delay_t period_in;
                     if (!get_period(ci, id_CLKI, period_in))
@@ -1483,10 +1333,7 @@ class MachXO2Packer
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
                     set_constraint(ci, id_CLKOS3,
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
-                }/* else if (ci->type == id_OSCH) {
-                    int div = int_or_default(ci->params, id_DIV, 128);
-                    set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));
-                }*/
+                }
             }
         }
     }

From 2a35f0292a9f1eec55d0e00d403ea9a70a14b32c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 19 Apr 2023 13:54:21 +0200
Subject: [PATCH 362/712] add constants for new primitives

---
 machxo2/constids.inc | 234 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 217 insertions(+), 17 deletions(-)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 1f2e8d248e..c2daae540c 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -45,6 +45,7 @@ X(WADO3)
 
 X(MODE)
 X(GSR)
+X(SGSR)
 X(SRMODE)
 X(CEMUX)
 X(CLKMUX)
@@ -100,23 +101,6 @@ X(T)
 X(IOLDO)
 X(IOLTO)
 
-
-X(OSCH)
-X(OSC)
-X(SEDSTDBY)
-
-
-X(DCCA)
-X(CLKI)
-X(CLKO)
-
-
-X(DCMA)
-X(CLK0)
-X(CLK1)
-X(SEL)
-X(DCMOUT)
-
 X(BEL)
 X(GND)
 X(IO_TYPE)
@@ -394,3 +378,219 @@ X(RSTAMUX)
 X(RSTBMUX)
 X(WEAMUX)
 X(WEBMUX)
+X(DATA_WIDTH_W)
+X(DATA_WIDTH_R)
+X(CSDECODE_W)
+X(CSDECODE_R)
+X(CSDECODE)
+X(AEPOINTER)
+X(AEPOINTER1)
+X(AFPOINTER)
+X(AFPOINTER1)
+X(FULLPOINTER)
+X(FULLPOINTER1)
+
+X(OSCH)
+X(OSC)
+X(SEDSTDBY)
+
+X(DCCA)
+X(CLKI)
+X(CLKO)
+
+X(DCMA)
+X(CLK0)
+X(CLK1)
+X(SEL)
+X(DCMOUT)
+
+X(EFB)
+X(WBCUFMIRQ)
+X(WBACKO)
+X(WBDATO0)
+X(WBDATO1)
+X(WBDATO2)
+X(WBDATO3)
+X(WBDATO4)
+X(WBDATO5)
+X(WBDATO6)
+X(WBDATO7)
+X(WBDATI0)
+X(WBDATI1)
+X(WBDATI2)
+X(WBDATI3)
+X(WBDATI4)
+X(WBDATI5)
+X(WBDATI6)
+X(WBDATI7)
+X(WBADRI0)
+X(WBADRI1)
+X(WBADRI2)
+X(WBADRI3)
+X(WBADRI4)
+X(WBADRI5)
+X(WBADRI6)
+X(WBADRI7)
+X(WBWEI)
+X(WBSTBI)
+X(WBCYCI)
+X(WBRSTI)
+X(WBCLKI)
+X(CFGWAKE)
+X(CFGSTDBY)
+X(UFMSN)
+X(PLL0ACKI)
+X(PLL0STBO)
+X(PLL0DATI0)
+X(PLL0DATI1)
+X(PLL0DATI2)
+X(PLL0DATI3)
+X(PLL0DATI4)
+X(PLL0DATI5)
+X(PLL0DATI6)
+X(PLL0DATI7)
+X(PLL1ACKI)
+X(PLL1STBO)
+X(PLL1DATI0)
+X(PLL1DATI1)
+X(PLL1DATI2)
+X(PLL1DATI3)
+X(PLL1DATI4)
+X(PLL1DATI5)
+X(PLL1DATI6)
+X(PLL1DATI7)
+X(PLLADRO0)
+X(PLLADRO1)
+X(PLLADRO2)
+X(PLLADRO3)
+X(PLLADRO4)
+X(PLLWEO)
+X(PLLRSTO)
+X(PLLCLKO)
+X(TCOC)
+X(TCINT)
+X(TCIC)
+X(TCRSTN)
+X(TCCLKI)
+X(SPIIRQO)
+X(SPISCSN)
+X(SPICSNEN)
+X(SPIMOSIEN)
+X(SPIMOSIO)
+X(SPIMOSII)
+X(SPIMISOEN)
+X(SPIMISOO)
+X(SPIMISOI)
+X(SPISCKEN)
+X(SPISCKO)
+X(SPISCKI)
+X(SPIMCSN0)
+X(SPIMCSN1)
+X(SPIMCSN2)
+X(SPIMCSN3)
+X(SPIMCSN4)
+X(SPIMCSN5)
+X(SPIMCSN6)
+X(SPIMCSN7)
+X(I2C1IRQO)
+X(I2C1SDAOEN)
+X(I2C1SDAO)
+X(I2C1SDAI)
+X(I2C1SCLOEN)
+X(I2C1SCLO)
+X(I2C1SCLI)
+X(I2C2IRQO)
+X(I2C2SDAOEN)
+X(I2C2SDAO)
+X(I2C2SDAI)
+X(I2C2SCLOEN)
+X(I2C2SCLO)
+X(I2C2SCLI)
+
+X(JTAGF)
+X(TCK)
+X(TMS)
+X(TDI)
+X(JTDO2)
+X(JTDO1)
+X(TDO)
+X(JTDI)
+X(JTCK)
+X(JRTI2)
+X(JRTI1)
+X(JSHIFT)
+X(JUPDATE)
+X(JRSTN)
+X(JCE2)
+X(JCE1)
+X(ER1)
+X(ER2)
+
+X(PCNTR)
+X(CLRFLAG)
+X(USERSTDBY)
+X(USERTIMEOUT)
+X(SFLAG)
+X(STOP)
+
+X(SEDFA)
+X(SEDENABLE)
+X(SEDSTART)
+X(SEDFRCERR)
+X(SEDEXCLK)
+X(SEDERR)
+X(SEDDONE)
+X(SEDINPROG)
+X(AUTODONE)
+
+X(SYNCMODE)
+
+X(START)
+X(STARTCLK)
+
+X(TSALL)
+X(TSALLI)
+
+X(CLKDIVC)
+X(ALIGNWD)
+X(CDIV1)
+X(CDIVX)
+
+X(ECLKSYNCA)
+X(ECLKI)
+X(ECLKO)
+
+X(ECLKBRIDGECS)
+X(ECSOUT)
+
+
+X(RST_PULSE)
+X(DIV)
+X(SED_CLK_FREQ)
+X(CHECKALWAYS)
+X(DEV_DENSITY)
+X(DEL_ADJ)
+X(DEL_VAL)
+X(LOCK_SENSITIVITY)
+X(FIN)
+X(FORCE_MAX_DELAY)
+X(DEL_MODE)
+X(DEL_VALUE)
+X(STDBYOPT)
+X(TIMEOUT)
+X(WAKEUP)
+X(POROFF)
+X(BGOFF)
+X(BANKID)
+
+X(DLLDELC)
+X(DQSDEL)
+
+X(PLLCSOUT)
+X(PLLREFCS)
+
+X(CLKFBBUF)
+
+X(DQSDLLC)
+X(UDDCNTLN)
+X(FREEZE)

From 7ac3d0d9016b5198184810fe13a086cb3885c5ef Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 19 Apr 2023 13:54:51 +0200
Subject: [PATCH 363/712] basic support for few small primitives

---
 machxo2/bitstream.cc | 32 +++++++++++++++++++++++++++++---
 machxo2/pack.cc      | 21 +++++++++++++++++++++
 2 files changed, 50 insertions(+), 3 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index fb48fe6ed6..cbd3bdeadc 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -259,10 +259,9 @@ struct MachXO2Bitgen
         std::vector<std::string> tiles;
         Loc loc = ctx->getBelLocation(bel);
 
-        if (name == "EHXPLL_L") {
+        if (name == "LPLL") {
             tiles.push_back(ctx->get_tile_by_type_loc(loc.y-1, loc.x-1, "GPLL_L0"));
-            //tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, "CIB_PIC_T_DUMMY"));
-        } else if (name == "EHXPLL_R") {
+       } else if (name == "RPLL") {
             tiles.push_back(ctx->get_tile_by_type_loc(loc.y+1, loc.x-1, "GPLL_R0"));
         } else {
             NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
@@ -695,6 +694,33 @@ struct MachXO2Bitgen
                 write_bram(ci);
             } else if (ci->type == id_EHXPLLJ) {
                 write_pll(ci);
+            } else if (ci->type == id_GSR) {
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
+                         "GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.SYNCMODE",
+                                                                 str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
+            } else if (ci->type == id_JTAGF) {
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("JTAG.ER1",
+                                                                 str_or_default(ci->params, id_ER1, "ENABLED"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("JTAG.ER2",
+                                                                 str_or_default(ci->params, id_ER2, "ENABLED"));
+            } else if (ci->type == id_TSALL) {
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
+                         "TSALL.MODE", str_or_default(ci->params, id_MODE, "TSALL"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
+                         "TSALL.TSALL", str_or_default(ci->params, id_TSALL, "TSALL"));
+            } else if (ci->type == id_START) {
+                cc.tiles[ctx->get_tile_by_type("CIB_CFG0")].add_enum(
+                         "START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK"));
+            } else if (ci->type == id_CLKDIVC) {
+                Loc loc = ctx->getBelLocation(ci->bel);
+                bool t = loc.y < 2;
+                std::string clkdiv = (t ? "T": "B") + std::string("CLKDIV") + std::to_string(loc.z);
+                std::string tile = ctx->get_tile_by_type(t ? "PIC_T_DUMMY_VIQ" : "PIC_B_DUMMY_VIQ_VREF");
+                cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
+                cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+            } else {
+                NPNR_ASSERT_FALSE("unsupported cell type");
             }
         }
     }
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 98d29854e5..74d15056e0 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1068,6 +1068,26 @@ class MachXO2Packer
         }
     }
 
+    // Miscellaneous packer tasks
+    void pack_misc()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type.in(id_GSR, id_SGSR)) {
+                ci->params[id_MODE] = std::string("ACTIVE_LOW");
+                ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC");
+                ci->type = id_GSR;
+                for (BelId bel : ctx->getBels()) {
+                    if (ctx->getBelType(bel) != id_GSR)
+                        continue;
+                    ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
+                }
+            } else if (ci->type.in(id_TSALL)) {
+                ci->renamePort(id_TSALL, id_TSALLI);
+            }
+        }
+    }
+
     // Preplace PLL
     void preplace_plls()
     {
@@ -1357,6 +1377,7 @@ class MachXO2Packer
         pack_io();
         preplace_plls();
         pack_ebr();
+        pack_misc();
         pack_constants();
         pack_dram();
         pack_carries();

From 8c19e6f83a7835713f21c8b5ff68869e9b8a9e32 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 20 Apr 2023 13:17:40 +0200
Subject: [PATCH 364/712] clangformat

---
 gui/generic/mainwindow.cc |  8 +++--
 machxo2/arch.cc           |  3 +-
 machxo2/arch.h            | 13 ++++----
 machxo2/arch_place.cc     |  3 +-
 machxo2/baseconfigs.cc    |  3 +-
 machxo2/bitstream.cc      | 66 +++++++++++++++++++--------------------
 machxo2/cells.h           |  2 --
 machxo2/pack.cc           |  9 ++----
 8 files changed, 52 insertions(+), 55 deletions(-)

diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc
index aeb5c04be2..54fe6f3e1e 100644
--- a/gui/generic/mainwindow.cc
+++ b/gui/generic/mainwindow.cc
@@ -42,9 +42,11 @@ void MainWindow::newContext(Context *ctx)
 
 void MainWindow::createMenu() {}
 
-void MainWindow::new_proj() {
-    QMessageBox::critical(0, "Error", "Creating a new project not supported in Viaduct mode, please re-start from command line.");
-    std::exit(1);   
+void MainWindow::new_proj()
+{
+    QMessageBox::critical(0, "Error",
+                          "Creating a new project not supported in Viaduct mode, please re-start from command line.");
+    std::exit(1);
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6092d9bde1..6aadd2d17f 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -631,7 +631,8 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
 bool Arch::is_spine_row(int row) const
 {
     for (auto &spine : chip_info->spines) {
-        if (row==spine.row) return true;
+        if (row == spine.row)
+            return true;
     }
     return false;
 }
diff --git a/machxo2/arch.h b/machxo2/arch.h
index fbb1d3b5bf..222390e8be 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -875,11 +875,11 @@ struct Arch : BaseArch<ArchRanges>
     int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
 
     BelId get_package_pin_bel(const std::string &pin) const;
-    //std::string get_bel_package_pin(BelId bel) const;
-    //int get_pio_bel_bank(BelId bel) const;
-    // For getting GCLK, PLL, Vref, etc, pins
-    //std::string get_pio_function_name(BelId bel) const;
-    //BelId get_pio_by_function_name(const std::string &name) const;
+    // std::string get_bel_package_pin(BelId bel) const;
+    // int get_pio_bel_bank(BelId bel) const;
+    //  For getting GCLK, PLL, Vref, etc, pins
+    // std::string get_pio_function_name(BelId bel) const;
+    // BelId get_pio_by_function_name(const std::string &name) const;
 
     PortType getBelPinType(BelId bel, IdString pin) const override;
 
@@ -903,7 +903,7 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v; }
     delay_t getDelayFromNS(float ns) const override { return ns; }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    //bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
+    // bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     // -------------------------------------------------
 
@@ -975,7 +975,6 @@ struct Arch : BaseArch<ArchRanges>
     mutable std::vector<TileStatus> tile_status;
 
     // -------------------------------------------------
-
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
index 6307fdb633..97f7226fea 100644
--- a/machxo2/arch_place.cc
+++ b/machxo2/arch_place.cc
@@ -149,7 +149,8 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
             if (ff != nullptr) {
                 if (found_global_dpram) {
                     // Do not allow SLICEC to have FF if there is already RAMW in it
-                    if (i==4 || i==5) return false;
+                    if (i == 4 || i == 5)
+                        return false;
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
                 }
diff --git a/machxo2/baseconfigs.cc b/machxo2/baseconfigs.cc
index 29c12c7261..7346ed8255 100644
--- a/machxo2/baseconfigs.cc
+++ b/machxo2/baseconfigs.cc
@@ -148,7 +148,6 @@ void config_empty_lcmxo3_2100(ChipConfig &cc)
     cc.tiles["PT4:CFG0"].add_unknown(5, 32);
     cc.tiles["PT4:CFG0"].add_unknown(5, 36);
 
-
     cc.tiles["PT7:CFG3"].add_unknown(5, 18);
 }
 
@@ -227,7 +226,7 @@ void config_empty_lcmxo3_9400(ChipConfig &cc)
     cc.tiles["EBR_R15C42:EBR1_10K"].add_unknown(0, 12);
     cc.tiles["EBR_R15C45:EBR1_10K"].add_unknown(0, 12);
     cc.tiles["EBR_R15C48:EBR1_10K"].add_unknown(0, 12);
-   
+
     cc.tiles["EBR_R8C2:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R8C5:EBR1"].add_unknown(0, 12);
     cc.tiles["EBR_R8C8:EBR1"].add_unknown(0, 12);
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index cbd3bdeadc..98af4866b4 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -108,13 +108,13 @@ struct MachXO2Bitgen
                     std::string pio_name = "W1_" + basename;
                     if (ctx->verbose)
                         log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
-                                pio_name.c_str());
+                                 pio_name.c_str());
                     return pio_name;
                 } else if (wire.location.x == max_col) {
                     std::string pio_name = "E1_" + basename;
                     if (ctx->verbose)
                         log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", ctx->nameOfWire(wire),
-                                pio_name.c_str());
+                                 pio_name.c_str());
                     return pio_name;
                 }
             }
@@ -206,16 +206,13 @@ struct MachXO2Bitgen
     {
         static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
         static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
-        static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
-                                                    "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
-                                                    "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
-                                                    "PIC_L2_VREF4", "PIC_L2_VREF5",
-                                                    "PIC_L3_VREF4", "PIC_L3_VREF5",
-                                                    "LLC0PIC", "LLC1PIC", 
-                                                    "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"};
-        static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
-                                                    "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256",
-                                                    "LRC1PIC1", "LRC1PIC2", "URC1PIC"};
+        static const std::set<std::string> pio_l = {"PIC_L0",       "PIC_L1",        "PIC_L2",        "PIC_L3",
+                                                    "PIC_LS0",      "PIC_L0_VREF3",  "PIC_L0_VREF4",  "PIC_L0_VREF5",
+                                                    "PIC_L1_VREF3", "PIC_L1_VREF4",  "PIC_L1_VREF5",  "PIC_L2_VREF4",
+                                                    "PIC_L2_VREF5", "PIC_L3_VREF4",  "PIC_L3_VREF5",  "LLC0PIC",
+                                                    "LLC1PIC",      "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"};
+        static const std::set<std::string> pio_r = {"PIC_R0",      "PIC_R1",   "PIC_RS0",  "PIC_R0_256", "PIC_R1_640",
+                                                    "PIC_RS0_256", "LRC1PIC1", "LRC1PIC2", "URC1PIC"};
 
         std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
         if (bel.location.y == 0) {
@@ -241,14 +238,17 @@ struct MachXO2Bitgen
         static const std::set<std::string> ebr1 = {"EBR1", "EBR1_10K"};
         static const std::set<std::string> ebr2 = {"EBR2", "EBR2_END", "EBR2_10K", "EBR2_END_10K"};
         tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, ebr1));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, ebr2));
-        static const std::set<std::string> cib_ebr0 = {"CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3", "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"};
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, ebr1));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, ebr2));
+        static const std::set<std::string> cib_ebr0 = {
+                "CIB_EBR0",           "CIB_EBR0_10K",  "CIB_EBR0_END0",      "CIB_EBR0_END0_10K",  "CIB_EBR0_END0_DLL3",
+                "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"};
         static const std::set<std::string> cib_ebr1 = {"CIB_EBR1", "CIB_EBR1_10K"};
-        static const std::set<std::string> cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0", "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"};
+        static const std::set<std::string> cib_ebr2 = {"CIB_EBR2",      "CIB_EBR2_10K",      "CIB_EBR2_END0",
+                                                       "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"};
         tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, cib_ebr0));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, cib_ebr1));
-        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, cib_ebr2));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, cib_ebr1));
+        tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, cib_ebr2));
         return tiles;
     }
 
@@ -260,9 +260,9 @@ struct MachXO2Bitgen
         Loc loc = ctx->getBelLocation(bel);
 
         if (name == "LPLL") {
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y-1, loc.x-1, "GPLL_L0"));
-       } else if (name == "RPLL") {
-            tiles.push_back(ctx->get_tile_by_type_loc(loc.y+1, loc.x-1, "GPLL_R0"));
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 1, loc.x - 1, "GPLL_L0"));
+        } else if (name == "RPLL") {
+            tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, "GPLL_R0"));
         } else {
             NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
         }
@@ -272,7 +272,8 @@ struct MachXO2Bitgen
     void set_pip(ChipConfig &cc, PipId pip)
     {
         std::string tile = ctx->get_pip_tilename(pip);
-        std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
+        std::string tile_type =
+                ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
         std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
         std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip));
         cc.tiles[tile].add_arc(sink, source);
@@ -365,7 +366,7 @@ struct MachXO2Bitgen
         int lut_init = int_or_default(ci->params, id_INITVAL);
         cc.tiles[tname].add_enum(slice + ".MODE", mode);
         cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
-                                int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
+                                 int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
         if (mode == "CCU2") {
             cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
         } else {
@@ -460,7 +461,7 @@ struct MachXO2Bitgen
 
         tg.config.add_word(ebr + ".WID", int_to_bitvector(int_or_default(ci->attrs, id_WID, 0), 9));
 
-       // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
+        // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
         for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
             for (int bit = 0; bit < 3; bit++) {
                 std::string sig = port.first + std::to_string(bit);
@@ -476,7 +477,6 @@ struct MachXO2Bitgen
         if (!ci->ramInfo.is_pdp) {
             tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
             tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
-
         }
         tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
         tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
@@ -695,8 +695,8 @@ struct MachXO2Bitgen
             } else if (ci->type == id_EHXPLLJ) {
                 write_pll(ci);
             } else if (ci->type == id_GSR) {
-                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
-                         "GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.GSRMODE",
+                                                                 str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
                 cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.SYNCMODE",
                                                                  str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
             } else if (ci->type == id_JTAGF) {
@@ -705,17 +705,17 @@ struct MachXO2Bitgen
                 cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("JTAG.ER2",
                                                                  str_or_default(ci->params, id_ER2, "ENABLED"));
             } else if (ci->type == id_TSALL) {
-                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
-                         "TSALL.MODE", str_or_default(ci->params, id_MODE, "TSALL"));
-                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
-                         "TSALL.TSALL", str_or_default(ci->params, id_TSALL, "TSALL"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.MODE",
+                                                                 str_or_default(ci->params, id_MODE, "TSALL"));
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.TSALL",
+                                                                 str_or_default(ci->params, id_TSALL, "TSALL"));
             } else if (ci->type == id_START) {
                 cc.tiles[ctx->get_tile_by_type("CIB_CFG0")].add_enum(
-                         "START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK"));
+                        "START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK"));
             } else if (ci->type == id_CLKDIVC) {
                 Loc loc = ctx->getBelLocation(ci->bel);
                 bool t = loc.y < 2;
-                std::string clkdiv = (t ? "T": "B") + std::string("CLKDIV") + std::to_string(loc.z);
+                std::string clkdiv = (t ? "T" : "B") + std::string("CLKDIV") + std::to_string(loc.z);
                 std::string tile = ctx->get_tile_by_type(t ? "PIC_T_DUMMY_VIQ" : "PIC_B_DUMMY_VIQ_VREF");
                 cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
                 cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
diff --git a/machxo2/cells.h b/machxo2/cells.h
index dd59e073bc..498fabaa21 100644
--- a/machxo2/cells.h
+++ b/machxo2/cells.h
@@ -54,8 +54,6 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i
 void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
                 pool<IdString> &todelete_cells);
 
-
-
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 74d15056e0..f6f7027e7a 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -274,10 +274,7 @@ class MachXO2Packer
     }
 
     // Return true if an port is a top level port that provides its own IOBUF
-    bool is_top_port(PortRef &port)
-    {
-        return false;
-    }
+    bool is_top_port(PortRef &port) { return false; }
 
     // Return true if a net only drives a top port
     bool drives_top_port(NetInfo *net, PortRef &tp)
@@ -788,14 +785,14 @@ class MachXO2Packer
                 std::unique_ptr<CellInfo> ram_comb[4];
                 for (int i = 0; i < 4; i++) {
                     ram_comb[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB,
-                                                   ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i));
+                                                      ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i));
                     dram_to_comb(ctx, ci, ram_comb[i].get(), ramw_slice.get(), i);
                 }
                 // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW
                 std::unique_ptr<CellInfo> ramw_block[2];
                 for (int i = 0; i < 2; i++) {
                     ramw_block[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB,
-                                                     ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
+                                                        ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i));
                     ramw_block[i]->params[id_MODE] = std::string("RAMW_BLOCK");
                 }
 

From d7c2eb3fae3464ecfea6d1ac5f57457049f9823b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 20 Apr 2023 13:40:27 +0200
Subject: [PATCH 365/712] Fix warning

---
 bba/main.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bba/main.cc b/bba/main.cc
index 1b3ca68308..70fc346088 100644
--- a/bba/main.cc
+++ b/bba/main.cc
@@ -447,7 +447,7 @@ int main(int argc, char **argv)
             fprintf(fileOut, "%s\n", s.c_str());
 
         fprintf(fileOut, "const char %s[%d] =\n", streams[0].name.c_str(), int(data.size()) + 1);
-        fprintf(fileOut, "#embed_str \"%s\"\n", boost::filesystem::basename(files.at(2)).c_str());
+        fprintf(fileOut, "#embed_str \"%s\"\n", boost::filesystem::path(files.at(2)).stem().c_str());
         fprintf(fileOut, ";\n");
 
         for (auto &s : postText)

From 01c631870eff2431f8a55bbecff34605e0adea64 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 24 Apr 2023 10:11:39 +0200
Subject: [PATCH 366/712] pio and iologic missing constants

---
 machxo2/constids.inc | 48 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index c2daae540c..1a90d8fb0c 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -100,6 +100,9 @@ X(SD)
 X(T)
 X(IOLDO)
 X(IOLTO)
+X(PG)
+X(INRD)
+X(LVDS)
 
 X(BEL)
 X(GND)
@@ -594,3 +597,48 @@ X(CLKFBBUF)
 X(DQSDLLC)
 X(UDDCNTLN)
 X(FREEZE)
+
+X(IOLOGIC)
+X(BIOLOGIC)
+X(BSIOLOGIC)
+X(TIOLOGIC)
+X(TSIOLOGIC)
+X(RIOLOGIC)
+
+X(PADDI)
+X(INDD)
+X(TDX0)
+X(TDX1)
+X(TDX2)
+X(TDX3)
+X(TDX4)
+X(TDX5)
+X(TDX6)
+X(TDX7)
+X(DEL0)
+X(DEL1)
+X(DEL2)
+X(DEL3)
+X(DEL4)
+X(ONEG)
+X(OPOS)
+X(TS)
+X(ECLK)
+X(SLIP)
+X(DDRCLKPOL)
+X(DQSR90)
+X(DQSW90)
+X(IN)
+X(IP)
+X(RXD0)
+X(RXD1)
+X(RXD2)
+X(RXD3)
+X(RXDA0)
+X(RXDA1)
+X(RXDA2)
+X(RXDA3)
+X(RXDA4)
+X(RXDA5)
+X(RXDA6)
+X(RXDA7)

From a2d08dc79e9231c2cb152ef1e55356fd3b1e4623 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 25 Apr 2023 09:19:17 +0200
Subject: [PATCH 367/712] Made PDPW8KC to work

---
 machxo2/constids.inc |  7 +++++++
 machxo2/pack.cc      | 45 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 1a90d8fb0c..6bc2b33f46 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -204,6 +204,9 @@ X(PLLDATO7)
 X(PLLACK)
 
 X(DP8KC)
+X(PDPW8KC)
+X(FIFO8KB)
+
 X(DIA0)
 X(DIA1)
 X(DIA2)
@@ -392,6 +395,10 @@ X(AFPOINTER)
 X(AFPOINTER1)
 X(FULLPOINTER)
 X(FULLPOINTER1)
+X(CLKW)
+X(CLKR)
+X(CER)
+X(OCER)
 
 X(OSCH)
 X(OSC)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index f6f7027e7a..7689a3aebd 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1027,6 +1027,51 @@ class MachXO2Packer
             c->params[n] = c->params[o];
             c->params.erase(o);
         };
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            // Convert 18-bit PDP RAMs to regular 9-bit DP ones that match the Bel
+            if (ci->type == id_PDPW8KC) {
+                ci->params[id_DATA_WIDTH_A] = 18; // force PDP mode
+                ci->params.erase(id_DATA_WIDTH_W);
+                rename_bus(ci, "BE", "ADA", 2, 0, 0);
+                rename_bus(ci, "ADW", "ADA", 9, 0, 4);
+                rename_bus(ci, "ADR", "ADB", 13, 0, 0);
+                rename_bus(ci, "CSW", "CSA", 3, 0, 0);
+                rename_bus(ci, "CSR", "CSB", 3, 0, 0);
+                rename_bus(ci, "DI", "DIA", 9, 0, 0);
+                rename_bus(ci, "DI", "DIB", 9, 9, 0);
+                rename_bus(ci, "DO", "DOA", 9, 9, 0);
+                rename_bus(ci, "DO", "DOB", 9, 0, 0);
+                ci->renamePort(id_CLKW, id_CLKA);
+                ci->renamePort(id_CLKR, id_CLKB);
+                ci->renamePort(id_CEW, id_CEA);
+                ci->renamePort(id_CER, id_CEB);
+                ci->renamePort(id_OCER, id_OCEB);
+                rename_param(ci, "CLKWMUX", "CLKAMUX");
+                if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
+                    ci->params[id_CLKAMUX] = std::string("CLKA");
+                rename_param(ci, "CLKRMUX", "CLKBMUX");
+                if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
+                    ci->params[id_CLKBMUX] = std::string("CLKB");
+                rename_param(ci, "CSDECODE_W", "CSDECODE_A");
+                rename_param(ci, "CSDECODE_R", "CSDECODE_B");
+                std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
+                ci->params[id_REGMODE_A] = outreg;
+                ci->params[id_REGMODE_B] = outreg;
+                ci->params.erase(id_REGMODE);
+                rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
+                if (ci->ports.count(id_RST)) {
+                    autocreate_empty_port(ci, id_RSTA);
+                    autocreate_empty_port(ci, id_RSTB);
+                    NetInfo *rst = ci->ports.at(id_RST).net;
+                    ci->connectPort(id_RSTA, rst);
+                    ci->connectPort(id_RSTB, rst);
+                    ci->disconnectPort(id_RST);
+                    ci->ports.erase(id_RST);
+                }
+                ci->type = id_DP8KC;
+            }
+        }
         for (auto &cell : ctx->cells) {
             CellInfo *ci = cell.second.get();
             if (ci->type == id_DP8KC) {

From 90a6578c533fc03402fba7b37c6f7bbac6e81c30 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 25 Apr 2023 12:38:36 +0200
Subject: [PATCH 368/712] handle VLO and VHI

---
 machxo2/pack.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 7689a3aebd..1f064c1dd4 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -951,6 +951,15 @@ class MachXO2Packer
     {
         log_info("Packing constants..\n");
 
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type.in(ctx->id("VLO"))) {
+                ci->type = id_GND;
+            } else if (ci->type.in(ctx->id("VHI"))) {
+                ci->type = id_VCC;
+            }
+        }
+
         std::unique_ptr<CellInfo> gnd_cell = create_machxo2_cell(ctx, id_LUT4, "$PACKER_GND");
         gnd_cell->params[id_INIT] = Property(0, 16);
         auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));

From 909917cb61f17269cdf81ee8ab0cee52a29561eb Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 25 Apr 2023 13:42:49 +0200
Subject: [PATCH 369/712] Add clock constraints for new primitives

---
 machxo2/pack.cc | 43 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 1f064c1dd4..4396b312cd 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1357,7 +1357,7 @@ class MachXO2Packer
             pool<IdString> changed_cells;
             for (auto net : changed_nets) {
                 for (auto &user : ctx->nets.at(net)->users)
-                    if (user.port.in(id_CLKI, /*id_ECLKI,*/ id_CLK0, id_CLK1))
+                    if (user.port.in(id_CLKI, id_ECLKI, id_CLK0, id_CLK1))
                         changed_cells.insert(user.cell->name);
                 auto &drv = ctx->nets.at(net)->driver;
                 if (iter == 1 && drv.cell != nullptr && drv.port == id_OSC)
@@ -1366,7 +1366,24 @@ class MachXO2Packer
             changed_nets.clear();
             for (auto cell : changed_cells) {
                 CellInfo *ci = ctx->cells.at(cell).get();
-                if (ci->type == id_DCCA) {
+                if (ci->type == id_CLKDIVC) {
+                    std::string div = str_or_default(ci->params, id_DIV, "2.0");
+                    double ratio;
+                    if (div == "2.0")
+                        ratio = 1 / 2.0;
+                    else if (div == "3.5")
+                        ratio = 1 / 3.5;
+                    else if (div == "4.0")
+                        ratio = 1 / 4.0;
+                    else
+                        log_error("Unsupported divider ratio '%s' on CLKDIVC '%s'\n", div.c_str(), ci->name.c_str(ctx));
+                    copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
+                } else if (ci->type.in(id_ECLKSYNCA /*, id_TRELLIS_ECLKBUF*/)) {
+                    copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
+                } else if (ci->type == id_ECLKBRIDGECS) {
+                    copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
+                    copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
+                } else if (ci->type == id_DCCA) {
                     copy_constraint(ci, id_CLKI, id_CLKO, 1);
                 } else if (ci->type == id_EHXPLLJ) {
                     delay_t period_in;
@@ -1404,6 +1421,28 @@ class MachXO2Packer
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
                     set_constraint(ci, id_CLKOS3,
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
+                } else if (ci->type == id_OSCH) {
+                    static std::string const osch_freq[] = {
+                        "2.08", "2.15", "2.22", "2.29", "2.38", "2.46", "2.56", "2.66",
+                        "2.77", "2.89", "3.02", "3.17", "3.33", "3.50", "3.69", "3.91",
+                        "4.16", "4.29", "4.43", "4.59", "4.75", "4.93", "5.12", "5.32",
+                        "5.54", "5.78", "6.05", "6.33", "6.65", "7.00", "7.39", "7.82",
+                        "8.31", "8.58", "8.87", "9.17", "9.50", "9.85", "10.23", "10.64",
+                        "11.08", "11.57", "12.09", "12.67", "13.30", "14.00", "14.78", "15.65",
+                        "15.65", "16.63", "17.73", "19.00", "20.46", "22.17", "24.18", "26.60",
+                        "29.56", "33.25", "38.00", "44.33", "53.20", "66.50", "88.67", "133.00" };
+
+                    std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
+                    bool found = false;
+                    for (int i=0;i<64;i++) {
+                        if (osch_freq[i] == freq) {
+                            found = true;
+                            set_constraint(ci, id_OSC, simple_clk_contraint(delay_t(1000.0 / std::stof(freq))));
+                            break;
+                        }
+                    }
+                    if (!found)
+                        log_error("Unsupported frequency '%s' on OSCH '%s'\n", freq.c_str(), ci->name.c_str(ctx));
                 }
             }
         }

From 582cd526ac9e1bcbd6afe2f1037b74a129b40429 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 25 Apr 2023 13:43:58 +0200
Subject: [PATCH 370/712] display freq with two digits after decimal point

---
 machxo2/pack.cc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 4396b312cd..84b310c444 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1308,13 +1308,13 @@ class MachXO2Packer
             if (to->clkconstr != nullptr) {
                 if (!equals_epsilon_constr(*to->clkconstr, *constr) && user_constrained.count(to->name))
                     log_warning(
-                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
-                            "%.1f MHz.\n",
+                            "    Overriding derived constraint of %.2f MHz on net %s with user-specified constraint of "
+                            "%.2f MHz.\n",
                             MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(constr->period.min_delay));
                 return;
             }
             to->clkconstr = std::move(constr);
-            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
+            log_info("    Derived frequency constraint of %.2f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);
         };
@@ -1330,8 +1330,8 @@ class MachXO2Packer
                                     delay_t(from->clkconstr->period.minDelay() / ratio)) &&
                     user_constrained.count(to->name))
                     log_warning(
-                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
-                            "%.1f MHz.\n",
+                            "    Overriding derived constraint of %.2f MHz on net %s with user-specified constraint of "
+                            "%.2f MHz.\n",
                             MHz(to->clkconstr->period.minDelay()), to->name.c_str(ctx),
                             MHz(delay_t(from->clkconstr->period.minDelay() / ratio)));
                 return;
@@ -1343,7 +1343,7 @@ class MachXO2Packer
                     DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio));
             to->clkconstr->period =
                     DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio));
-            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
+            log_info("    Derived frequency constraint of %.2f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);
         };
@@ -1389,7 +1389,7 @@ class MachXO2Packer
                     delay_t period_in;
                     if (!get_period(ci, id_CLKI, period_in))
                         continue;
-                    log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
+                    log_info("    Input frequency of PLL '%s' is constrained to %.2f MHz\n", ci->name.c_str(ctx),
                              MHz(period_in));
                     double period_in_div = period_in * int_or_default(ci->params, id_CLKI_DIV, 1);
                     std::string path = str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP");
@@ -1410,7 +1410,7 @@ class MachXO2Packer
                     double vco_period = period_in_div / feedback_div;
                     double vco_freq = MHz(vco_period);
                     if (vco_freq < 400 || vco_freq > 800)
-                        log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
+                        log_info("    Derived VCO frequency %.2f MHz of PLL '%s' is out of legal range [400MHz, "
                                  "800MHz]\n",
                                  vco_freq, ci->name.c_str(ctx));
                     set_constraint(ci, id_CLKOP,

From 655aee1f9d685f5e8a66056f06b976e061a7e2f5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 25 Apr 2023 15:58:28 +0200
Subject: [PATCH 371/712] Fix invalid accesses during certain IO packing cases

---
 machxo2/pack.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 84b310c444..991995dd8c 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -539,11 +539,13 @@ class MachXO2Packer
                     if (ionet != nullptr) {
                         ctx->nets.erase(ionet->name);
                         tp.cell->ports.at(tp.port).net = nullptr;
+                        ci->ports.at(ci->type == ctx->id("$nextpnr_obuf") ? id_I : id_O).net = nullptr;
                     }
                     if (ci->type == ctx->id("$nextpnr_iobuf")) {
                         NetInfo *net2 = ci->ports.at(id_I).net;
                         if (net2 != nullptr) {
                             ctx->nets.erase(net2->name);
+                            ci->ports.at(id_I).net = nullptr;
                         }
                     }
                 } else {

From 8fd4735292b6ebf5df7f8471a11fd2aa7eb9bd7d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 25 Apr 2023 16:18:28 +0200
Subject: [PATCH 372/712] handle some SYSCONFIG

---
 machxo2/bitstream.cc | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 98af4866b4..bf7d13a761 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -723,6 +723,23 @@ struct MachXO2Bitgen
                 NPNR_ASSERT_FALSE("unsupported cell type");
             }
         }
+
+        // Add some SYSCONFIG settings
+        const std::string prefix = "arch.sysconfig.";
+        for (auto &setting : ctx->settings) {
+            std::string key = setting.first.str(ctx);
+            if (key.substr(0, prefix.length()) != prefix)
+                continue;
+            key = key.substr(prefix.length());
+            std::string value = setting.second.as_string();
+            if (key == "BACKGROUND_RECONFIG" || key == "ENABLE_TRANSFR" || key == "SDM_PORT") {
+                cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("SYSCONFIG." + key, value);
+            } else if (key == "I2C_PORT" || key == "MASTER_SPI_PORT" || key == "SLAVE_SPI_PORT") {
+                cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("SYSCONFIG." + key, value);
+            } else {
+                cc.sysconfig[key] = value;
+            }
+        }
     }
 };
 } // namespace

From e012f7b4f8fdec2ff1f4d6a7e7bd9c710565f708 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 2 May 2023 15:42:47 +0200
Subject: [PATCH 373/712] update prjtrellis version

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 0b015575fc..670464c8ff 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: e894ae9e459788cdd7be4056df766e7da000be64
+      TRELLIS_REVISION: 6e5818c6538f7c3b391d8140f3979213cfc2e3d6
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1

From 10595726c11243c99a3d2c461a659e502732f601 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 2 May 2023 16:04:54 +0200
Subject: [PATCH 374/712] fix warning

---
 machxo2/pack.cc | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 991995dd8c..3b48e084f5 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -35,20 +35,6 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
            cell->type == ctx->id("$nextpnr_iobuf");
 }
 
-static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
-{
-    auto gnd = ctx->id("$PACKER_GND_NET");
-    auto vcc = ctx->id("$PACKER_VCC_NET");
-    if (net == nullptr)
-        return false;
-    if (net->name.in(gnd, vcc)) {
-        value = (net->name == vcc);
-        return true;
-    } else {
-        return false;
-    }
-}
-
 class MachXO2Packer
 {
   public:

From 0067bcc615e45f8f678865ab9ba42fc6f62a65b3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 3 May 2023 08:22:47 +0200
Subject: [PATCH 375/712] use latest trellis and add arch tests

---
 .github/ci/build_machxo2.sh   | 5 ++++-
 .github/workflows/arch_ci.yml | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/.github/ci/build_machxo2.sh b/.github/ci/build_machxo2.sh
index c81a538ba6..f8c33e451d 100644
--- a/.github/ci/build_machxo2.sh
+++ b/.github/ci/build_machxo2.sh
@@ -17,5 +17,8 @@ function run_tests {
 }
 
 function run_archcheck {
-    :
+    pushd build
+    ./nextpnr-machxo2 --device LCMXO2-1200HC-4SG32C --test
+    ./nextpnr-machxo2 --device LCMXO3LF-6900C-6BG256C --test
+    popd
 }
diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 670464c8ff..13abb52f3e 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: 6e5818c6538f7c3b391d8140f3979213cfc2e3d6
+      TRELLIS_REVISION: c99b22d35e4109333e7549e56cec139569a17392
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1

From 91771895b698804439257e85e2afda83b81f074c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 3 May 2023 15:51:19 +0200
Subject: [PATCH 376/712] Removed not tested/used code

---
 machxo2/pack.cc | 213 ------------------------------------------------
 1 file changed, 213 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 3b48e084f5..3a99b256b6 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -286,192 +286,6 @@ class MachXO2Packer
         return false;
     }
 
-    // Pass to pack LUT5s into a newly created slice
-    void pack_lut5xs()
-    {
-        log_info("Packing LUT5-7s...\n");
-
-        // Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
-        auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
-            NetInfo *f1 = lut5->getPort(id_F1);
-            NPNR_ASSERT(f1 != nullptr);
-            NPNR_ASSERT(f1->driver.cell != nullptr);
-            return f1->driver.cell;
-        };
-
-        dict<IdString, std::pair<CellInfo *, CellInfo *>> lut5_roots, lut6_roots, lut7_roots;
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_pfumx(ctx, ci)) {
-                NetInfo *f0 = ci->ports.at(id_BLUT).net;
-
-                if (f0 == nullptr)
-                    log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
-                NetInfo *f1 = ci->ports.at(id_ALUT).net;
-                if (f1 == nullptr)
-                    log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
-
-                CellInfo *lut0 =
-                        (f0->driver.cell && f0->driver.cell->type == id_TRELLIS_COMB && f0->driver.port == id_F)
-                                ? f0->driver.cell
-                                : nullptr;
-                CellInfo *lut1 =
-                        (f1->driver.cell && f1->driver.cell->type == id_TRELLIS_COMB && f1->driver.port == id_F)
-                                ? f1->driver.cell
-                                : nullptr;
-                if (lut0 == nullptr || lut0->cluster != ClusterId())
-                    log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
-                if (lut1 == nullptr || lut1->cluster != ClusterId())
-                    log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
-                lut0->addInput(id_F1);
-                lut0->addInput(id_M);
-                lut0->addOutput(id_OFX);
-
-                ci->movePortTo(id_Z, lut0, id_OFX);
-                ci->movePortTo(id_ALUT, lut0, id_F1);
-                ci->movePortTo(id_C0, lut0, id_M);
-                ci->disconnectPort(id_BLUT);
-
-                lut5_roots[lut0->name] = {lut0, lut1};
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-        // Pack LUT6s
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
-                if (ofx0_0 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
-                if (ofx0_1 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *comb0 = (ofx0_0->driver.cell && ofx0_0->driver.cell->type == id_TRELLIS_COMB &&
-                                   ofx0_0->driver.port == id_OFX)
-                                          ? ofx0_0->driver.cell
-                                          : nullptr;
-                CellInfo *comb1 = (ofx0_1->driver.cell && ofx0_1->driver.cell->type == id_TRELLIS_COMB &&
-                                   ofx0_1->driver.port == id_OFX)
-                                          ? ofx0_1->driver.cell
-                                          : nullptr;
-                if (comb0 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z))
-                        log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
-                                  "('%s.%s')\n",
-                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
-                                  ofx0_0->driver.port.c_str(ctx));
-                    continue;
-                }
-                if (lut6_roots.count(comb0->name))
-                    continue;
-
-                if (comb1 == nullptr) {
-                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z))
-                        log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
-                                  "('%s.%s')\n",
-                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
-                                  ofx0_0->driver.port.c_str(ctx));
-                    continue;
-                }
-                if (lut6_roots.count(comb1->name))
-                    continue;
-                if (ctx->verbose)
-                    log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
-                comb0 = get_comb1_from_lut5(comb0);
-                comb1 = get_comb1_from_lut5(comb1);
-
-                comb1->addInput(id_FXA);
-                comb1->addInput(id_FXB);
-                comb1->addInput(id_M);
-                comb1->addOutput(id_OFX);
-                ci->movePortTo(id_D0, comb1, id_FXA);
-                ci->movePortTo(id_D1, comb1, id_FXB);
-                ci->movePortTo(id_SD, comb1, id_M);
-                ci->movePortTo(id_Z, comb1, id_OFX);
-                lut6_roots[comb1->name] = {comb0, comb1};
-                packed_cells.insert(ci->name);
-            }
-        }
-        flush_cells();
-        // Pack LUT7s
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (is_l6mux(ctx, ci)) {
-                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
-                if (ofx1_0 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
-                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
-                if (ofx1_1 == nullptr)
-                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
-                CellInfo *comb1 = (ofx1_0->driver.cell && ofx1_0->driver.cell->type == id_TRELLIS_COMB &&
-                                   ofx1_0->driver.port == id_OFX)
-                                          ? ofx1_0->driver.cell
-                                          : nullptr;
-                CellInfo *comb3 = (ofx1_1->driver.cell && ofx1_1->driver.cell->type == id_TRELLIS_COMB &&
-                                   ofx1_1->driver.port == id_OFX)
-                                          ? ofx1_1->driver.cell
-                                          : nullptr;
-                if (comb1 == nullptr)
-                    log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
-                              ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
-                              ofx1_0->driver.port.c_str(ctx));
-                if (comb3 == nullptr)
-                    log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
-                              ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
-                              ofx1_1->driver.port.c_str(ctx));
-
-                NetInfo *fxa_0 = comb1->ports.at(id_FXA).net;
-                if (fxa_0 == nullptr)
-                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb1->name.c_str(ctx));
-                NetInfo *fxa_1 = comb3->ports.at(id_FXA).net;
-                if (fxa_1 == nullptr)
-                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb3->name.c_str(ctx));
-
-                CellInfo *comb2 = net_driven_by(
-                        ctx, fxa_1,
-                        [](const Context *ctx, const CellInfo *ci) {
-                            (void)ctx;
-                            return ci->type == id_TRELLIS_COMB;
-                        },
-                        id_OFX);
-                if (comb2 == nullptr)
-                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
-                              comb3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
-                              fxa_1->driver.port.c_str(ctx));
-                comb2 = get_comb1_from_lut5(comb2);
-                comb2->addInput(id_FXA);
-                comb2->addInput(id_FXB);
-                comb2->addInput(id_M);
-                comb2->addOutput(id_OFX);
-                ci->movePortTo(id_D0, comb2, id_FXA);
-                ci->movePortTo(id_D1, comb2, id_FXB);
-                ci->movePortTo(id_SD, comb2, id_M);
-                ci->movePortTo(id_Z, comb2, id_OFX);
-
-                lut7_roots[comb2->name] = {comb1, comb3};
-                packed_cells.insert(ci->name);
-            }
-        }
-
-        for (auto &root : lut7_roots) {
-            auto &cells = root.second;
-            cells.second->cluster = cells.second->name;
-            cells.second->constr_abs_z = true;
-            cells.second->constr_z = (1 << Arch::lc_idx_shift) | Arch::BEL_COMB;
-            rel_constr_cells(cells.second, cells.first, (4 << Arch::lc_idx_shift));
-        }
-        for (auto &root : lut6_roots) {
-            auto &cells = root.second;
-            rel_constr_cells(cells.second, cells.first, (2 << Arch::lc_idx_shift));
-        }
-        for (auto &root : lut5_roots) {
-            auto &cells = root.second;
-            rel_constr_cells(cells.first, cells.second, (1 << Arch::lc_idx_shift));
-        }
-        flush_cells();
-    }
-
     // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
     void pack_io()
     {
@@ -1222,32 +1036,6 @@ class MachXO2Packer
         new_cells.push_back(std::move(zero_cell));
     }
 
-    int lookup_delay(const std::string &del_mode)
-    {
-        if (del_mode == "USER_DEFINED")
-            return 0;
-        else if (del_mode == "DQS_ALIGNED_X2")
-            return 6;
-        else if (del_mode == "DQS_CMD_CLK")
-            return 9;
-        else if (del_mode == "ECLK_ALIGNED")
-            return 21;
-        else if (del_mode == "ECLK_CENTERED")
-            return 11;
-        else if (del_mode == "ECLKBRIDGE_ALIGNED")
-            return 39;
-        else if (del_mode == "ECLKBRIDGE_CENTERED")
-            return 29;
-        else if (del_mode == "SCLK_ALIGNED")
-            return 50;
-        else if (del_mode == "SCLK_CENTERED")
-            return 39;
-        else if (del_mode == "SCLK_ZEROHOLD")
-            return 59;
-        else
-            log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
-    }
-
     void generate_constraints()
     {
         log_info("Generating derived timing constraints...\n");
@@ -1460,7 +1248,6 @@ class MachXO2Packer
         pack_dram();
         pack_carries();
         pack_luts();
-        pack_lut5xs();
         pack_ffs();
         generate_constraints();
         ctx->fixupHierarchy();

From e3529d335617cadca0d9d2a5ce5f5b5cdca09a3e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 5 May 2023 10:48:34 +0200
Subject: [PATCH 377/712] machxo2: Global placement and clock routing from
 nexus

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/arch_ci.yml |   2 +-
 machxo2/arch.cc               |   2 +
 machxo2/arch.h                |   3 +
 machxo2/bitstream.cc          |   7 +-
 machxo2/globals.cc            | 178 +++++++++++++++++++
 machxo2/pack.cc               | 324 +++++++++++++++++++++++++++-------
 6 files changed, 450 insertions(+), 66 deletions(-)
 create mode 100644 machxo2/globals.cc

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 13abb52f3e..db13c4cb11 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: c99b22d35e4109333e7549e56cec139569a17392
+      TRELLIS_REVISION: f1e5710099313d2e1862d4ef2582293f6b7ee122
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.5.1a1
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6aadd2d17f..3c135e8f87 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -433,6 +433,8 @@ bool Arch::route()
 
     assignArchInfo();
 
+    route_globals();
+
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 222390e8be..855b39df70 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -967,6 +967,9 @@ struct Arch : BaseArch<ArchRanges>
     // Apply LPF constraints to the context
     bool apply_lpf(std::string filename, std::istream &in);
 
+    // Global clock routing
+    void route_globals();
+
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
     static const std::string defaultRouter;
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index bf7d13a761..652152bd4d 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -86,9 +86,14 @@ struct MachXO2Bitgen
             // clang-format on
         };
 
-        if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
+        if (prefix2 == "G_" || prefix7 == "BRANCH_")
             return basename;
 
+        if (prefix2 == "L_" || prefix2 == "R_") {
+            if (loc.x == 0 || loc.x == (ctx->getGridDimX() - 1))
+                return "G_" + basename.substr(2);
+            return basename;
+        }
         if (prefix2 == "U_" || prefix2 == "D_") {
             // We needded to keep U_ and D_ prefixes to generate the routing
             // graph connections properly, but in truth they are not relevant
diff --git a/machxo2/globals.cc b/machxo2/globals.cc
new file mode 100644
index 0000000000..bef4628d82
--- /dev/null
+++ b/machxo2/globals.cc
@@ -0,0 +1,178 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020-23  gatecat <gatecat@ds0.me>
+ *
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include <queue>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct MachxoGlobalRouter
+{
+    Context *ctx;
+
+    MachxoGlobalRouter(Context *ctx) : ctx(ctx){};
+
+    // When routing globals; we allow global->local for some tricky cases but never local->local
+    bool global_pip_filter(PipId pip) const
+    {
+        WireId src = ctx->getPipSrcWire(pip);
+        const char *s = ctx->tile_info(src)->wire_data[src.index].name.get();
+        if ((s[0] == 'H' || s[0] == 'V') && s[1] == '0')
+            return false;
+        return true;
+    }
+
+    // Dedicated backwards BFS routing for global networks
+    template <typename Tfilt>
+    bool backwards_bfs_route(NetInfo *net, store_index<PortRef> user_idx, int iter_limit, bool strict, Tfilt pip_filter)
+    {
+        // Queue of wires to visit
+        std::queue<WireId> visit;
+        // Wire -> upstream pip
+        dict<WireId, PipId> backtrace;
+
+        // Lookup source and destination wires
+        WireId src = ctx->getNetinfoSourceWire(net);
+        WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(user_idx), 0);
+
+        if (src == WireId())
+            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
+                      ctx->nameOf(net->driver.port));
+
+        if (dst == WireId())
+            log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
+                      ctx->nameOf(net->users.at(user_idx).cell), ctx->nameOf(net->users.at(user_idx).port));
+
+        if (ctx->getBoundWireNet(src) != net)
+            ctx->bindWire(src, net, STRENGTH_LOCKED);
+
+        if (src == dst) {
+            // Nothing more to do
+            return true;
+        }
+
+        visit.push(dst);
+        backtrace[dst] = PipId();
+
+        int iter = 0;
+
+        while (!visit.empty() && (iter++ < iter_limit)) {
+            WireId cursor = visit.front();
+            visit.pop();
+            // Search uphill pips
+            for (PipId pip : ctx->getPipsUphill(cursor)) {
+                // Skip pip if unavailable, and not because it's already used for this net
+                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net)
+                    continue;
+                WireId prev = ctx->getPipSrcWire(pip);
+                // Ditto for the upstream wire
+                if (!ctx->checkWireAvail(prev) && ctx->getBoundWireNet(prev) != net)
+                    continue;
+                // Skip already visited wires
+                if (backtrace.count(prev))
+                    continue;
+                // Apply our custom pip filter
+                if (!pip_filter(pip))
+                    continue;
+                // Add to the queue
+                visit.push(prev);
+                backtrace[prev] = pip;
+                // Check if we are done yet
+                if (prev == src)
+                    goto done;
+            }
+            if (false) {
+            done:
+                break;
+            }
+        }
+
+        if (backtrace.count(src)) {
+            WireId cursor = src;
+            std::vector<PipId> pips;
+            // Create a list of pips on the routed path
+            while (true) {
+                PipId pip = backtrace.at(cursor);
+                if (pip == PipId())
+                    break;
+                pips.push_back(pip);
+                cursor = ctx->getPipDstWire(pip);
+            }
+            // Reverse that list
+            std::reverse(pips.begin(), pips.end());
+            // Bind pips until we hit already-bound routing
+            for (PipId pip : pips) {
+                WireId dst = ctx->getPipDstWire(pip);
+                if (ctx->getBoundWireNet(dst) == net)
+                    break;
+                ctx->bindPip(pip, net, STRENGTH_LOCKED);
+            }
+            return true;
+        } else {
+            if (strict)
+                log_error("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
+                          ctx->nameOfWire(src), ctx->nameOfWire(dst));
+            return false;
+        }
+    }
+
+    bool is_relaxed_sink(const PortRef &sink) const
+    {
+        // Cases where global clocks are driving fabric
+        if ((sink.cell->type == id_TRELLIS_COMB && sink.port != id_WCK) ||
+            (sink.cell->type == id_TRELLIS_FF && sink.port != id_CLK))
+            return true;
+        return false;
+    }
+
+    void route_clk_net(NetInfo *net)
+    {
+        for (auto usr : net->users.enumerate())
+            backwards_bfs_route(net, usr.index, 1000000, true,
+                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
+        log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+    }
+
+    void operator()()
+    {
+        log_info("Routing globals...\n");
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            CellInfo *drv = ni->driver.cell;
+            if (drv == nullptr)
+                continue;
+            if (drv->type.in(id_DCCA, id_DCMA)) {
+                route_clk_net(ni);
+                continue;
+            }
+        }
+    }
+};
+
+void Arch::route_globals()
+{
+    MachxoGlobalRouter glb_router(getCtx());
+    glb_router();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 3a99b256b6..22ca51c475 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -941,60 +941,6 @@ class MachXO2Packer
         }
     }
 
-    // Preplace PLL
-    void preplace_plls()
-    {
-        std::set<BelId> available_plls;
-        for (auto bel : ctx->getBels()) {
-            if (ctx->getBelType(bel) == id_EHXPLLJ && ctx->checkBelAvail(bel))
-                available_plls.insert(bel);
-        }
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLJ && ci->attrs.count(id_BEL))
-                available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(id_BEL).as_string()));
-        }
-        // Place PLL connected to fixed drivers such as IO close to their source
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLJ && !ci->attrs.count(id_BEL)) {
-                const NetInfo *drivernet = ci->getPort(id_CLKI);
-                if (drivernet == nullptr || drivernet->driver.cell == nullptr)
-                    continue;
-                const CellInfo *drivercell = drivernet->driver.cell;
-                if (!drivercell->attrs.count(id_BEL))
-                    continue;
-                BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(id_BEL).as_string());
-                Loc drvloc = ctx->getBelLocation(drvbel);
-                BelId closest_pll;
-                int closest_distance = std::numeric_limits<int>::max();
-                for (auto bel : available_plls) {
-                    Loc pllloc = ctx->getBelLocation(bel);
-                    int distance = std::abs(drvloc.x - pllloc.x) + std::abs(drvloc.y - pllloc.y);
-                    if (distance < closest_distance) {
-                        closest_pll = bel;
-                        closest_distance = distance;
-                    }
-                }
-                if (closest_pll == BelId())
-                    log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
-                available_plls.erase(closest_pll);
-                ci->attrs[id_BEL] = ctx->getBelName(closest_pll).str(ctx);
-            }
-        }
-        // Place PLLs driven by logic, etc, randomly
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (ci->type == id_EHXPLLJ && !ci->attrs.count(id_BEL)) {
-                if (available_plls.empty())
-                    log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
-                BelId next_pll = *(available_plls.begin());
-                available_plls.erase(next_pll);
-                ci->attrs[id_BEL] = ctx->getBelName(next_pll).str(ctx);
-            }
-        }
-    }
-
     // Check if two nets have identical constant drivers
     bool equal_constant(NetInfo *a, NetInfo *b)
     {
@@ -1199,18 +1145,17 @@ class MachXO2Packer
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
                 } else if (ci->type == id_OSCH) {
                     static std::string const osch_freq[] = {
-                        "2.08", "2.15", "2.22", "2.29", "2.38", "2.46", "2.56", "2.66",
-                        "2.77", "2.89", "3.02", "3.17", "3.33", "3.50", "3.69", "3.91",
-                        "4.16", "4.29", "4.43", "4.59", "4.75", "4.93", "5.12", "5.32",
-                        "5.54", "5.78", "6.05", "6.33", "6.65", "7.00", "7.39", "7.82",
-                        "8.31", "8.58", "8.87", "9.17", "9.50", "9.85", "10.23", "10.64",
-                        "11.08", "11.57", "12.09", "12.67", "13.30", "14.00", "14.78", "15.65",
-                        "15.65", "16.63", "17.73", "19.00", "20.46", "22.17", "24.18", "26.60",
-                        "29.56", "33.25", "38.00", "44.33", "53.20", "66.50", "88.67", "133.00" };
+                            "2.08",  "2.15",  "2.22",  "2.29",  "2.38",  "2.46",  "2.56",  "2.66",  "2.77",  "2.89",
+                            "3.02",  "3.17",  "3.33",  "3.50",  "3.69",  "3.91",  "4.16",  "4.29",  "4.43",  "4.59",
+                            "4.75",  "4.93",  "5.12",  "5.32",  "5.54",  "5.78",  "6.05",  "6.33",  "6.65",  "7.00",
+                            "7.39",  "7.82",  "8.31",  "8.58",  "8.87",  "9.17",  "9.50",  "9.85",  "10.23", "10.64",
+                            "11.08", "11.57", "12.09", "12.67", "13.30", "14.00", "14.78", "15.65", "15.65", "16.63",
+                            "17.73", "19.00", "20.46", "22.17", "24.18", "26.60", "29.56", "33.25", "38.00", "44.33",
+                            "53.20", "66.50", "88.67", "133.00"};
 
                     std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
                     bool found = false;
-                    for (int i=0;i<64;i++) {
+                    for (int i = 0; i < 64; i++) {
                         if (osch_freq[i] == freq) {
                             found = true;
                             set_constraint(ci, id_OSC, simple_clk_contraint(delay_t(1000.0 / std::stof(freq))));
@@ -1235,13 +1180,262 @@ class MachXO2Packer
         }
     }
 
+    BelId get_bel_attr(const CellInfo *ci)
+    {
+        if (!ci->attrs.count(id_BEL))
+            return BelId();
+        return ctx->getBelByNameStr(ci->attrs.at(id_BEL).as_string());
+    }
+
+    // Using a BFS, search for bels of a given type either upstream or downstream of another cell
+    void find_connected_bels(const CellInfo *cell, IdString port, IdString dest_type, IdString dest_pin, int iter_limit,
+                             std::vector<BelId> &candidates)
+    {
+        int iter = 0;
+        std::queue<WireId> visit;
+        pool<WireId> seen_wires;
+        pool<BelId> seen_bels;
+
+        BelId bel = get_bel_attr(cell);
+        if (bel == BelId())
+            return;
+        WireId start_wire = ctx->getBelPinWire(bel, port);
+        NPNR_ASSERT(start_wire != WireId());
+        PortType dir = ctx->getBelPinType(bel, port);
+
+        visit.push(start_wire);
+
+        while (!visit.empty() && (iter++ < iter_limit)) {
+            WireId cursor = visit.front();
+            visit.pop();
+            // Check to see if we have reached a valid bel pin
+            for (auto bp : ctx->getWireBelPins(cursor)) {
+                if (ctx->getBelType(bp.bel) != dest_type)
+                    continue;
+                if (dest_pin != IdString() && bp.pin != dest_pin)
+                    continue;
+                if (seen_bels.count(bp.bel))
+                    continue;
+                seen_bels.insert(bp.bel);
+                candidates.push_back(bp.bel);
+            }
+            // Search in the appropriate direction up/downstream of the cursor
+            if (dir == PORT_OUT) {
+                for (PipId p : ctx->getPipsDownhill(cursor))
+                    if (ctx->checkPipAvail(p)) {
+                        WireId dst = ctx->getPipDstWire(p);
+                        if (seen_wires.count(dst))
+                            continue;
+                        seen_wires.insert(dst);
+                        visit.push(dst);
+                    }
+            } else {
+                for (PipId p : ctx->getPipsUphill(cursor))
+                    if (ctx->checkPipAvail(p)) {
+                        WireId src = ctx->getPipSrcWire(p);
+                        if (seen_wires.count(src))
+                            continue;
+                        seen_wires.insert(src);
+                        visit.push(src);
+                    }
+            }
+        }
+    }
+
+    // Find the nearest bel of a given type; matching a closure predicate
+    template <typename Tpred> BelId find_nearest_bel(const CellInfo *cell, IdString dest_type, Tpred predicate)
+    {
+        BelId origin = get_bel_attr(cell);
+        if (origin == BelId())
+            return BelId();
+        Loc origin_loc = ctx->getBelLocation(origin);
+        int best_distance = std::numeric_limits<int>::max();
+        BelId best_bel = BelId();
+
+        for (BelId bel : ctx->getBels()) {
+            if (ctx->getBelType(bel) != dest_type)
+                continue;
+            if (!predicate(bel))
+                continue;
+            Loc bel_loc = ctx->getBelLocation(bel);
+            int dist = std::abs(origin_loc.x - bel_loc.x) + std::abs(origin_loc.y - bel_loc.y);
+            if (dist < best_distance) {
+                best_distance = dist;
+                best_bel = bel;
+            }
+        }
+        return best_bel;
+    }
+
+    pool<BelId> used_bels;
+    // Pre-place a primitive based on routeability first and distance second
+    bool preplace_prim(CellInfo *cell, IdString pin, bool strict_routing)
+    {
+        std::vector<BelId> routeability_candidates;
+
+        if (cell->attrs.count(id_BEL))
+            return false;
+
+        NetInfo *pin_net = cell->getPort(pin);
+        if (pin_net == nullptr)
+            return false;
+
+        CellInfo *pin_drv = pin_net->driver.cell;
+        if (pin_drv == nullptr)
+            return false;
+
+        // Check based on routeability
+        find_connected_bels(pin_drv, pin_net->driver.port, cell->type, pin, 25000, routeability_candidates);
+
+        for (BelId cand : routeability_candidates) {
+            if (used_bels.count(cand))
+                continue;
+            log_info("    constraining %s '%s' to bel '%s' based on dedicated routing\n", ctx->nameOf(cell),
+                     ctx->nameOf(cell->type), ctx->nameOfBel(cand));
+            cell->attrs[id_BEL] = ctx->getBelName(cand).str(ctx);
+            used_bels.insert(cand);
+            return true;
+        }
+
+        // Unless in strict mode; check based on simple distance too
+        BelId nearest = find_nearest_bel(pin_drv, cell->type, [&](BelId bel) { return !used_bels.count(bel); });
+
+        if (nearest != BelId()) {
+            log_info("    constraining %s '%s' to bel '%s'\n", ctx->nameOf(cell), ctx->nameOf(cell->type),
+                     ctx->nameOfBel(nearest));
+            cell->attrs[id_BEL] = ctx->getBelName(nearest).str(ctx);
+            used_bels.insert(nearest);
+            return true;
+        }
+
+        return false;
+    }
+
+    // Pre-place a singleton primitive; so decisions can be made on routeability downstream of it
+    bool preplace_singleton(CellInfo *cell)
+    {
+        if (cell->attrs.count(id_BEL))
+            return false;
+        bool did_something = false;
+        for (BelId bel : ctx->getBels()) {
+            if (ctx->getBelType(bel) != cell->type)
+                continue;
+            // Check that the bel really is a singleton...
+            NPNR_ASSERT(!cell->attrs.count(id_BEL));
+            cell->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
+            log_info("    constraining %s '%s' to bel '%s'\n", ctx->nameOf(cell), ctx->nameOf(cell->type),
+                     ctx->nameOfBel(bel));
+            did_something = true;
+        }
+        return did_something;
+    }
+
+    // Insert a buffer primitive in a signal; moving all users that match a predicate behind it
+    template <typename Tpred>
+    CellInfo *insert_buffer(NetInfo *net, IdString buffer_type, std::string name_postfix, IdString i, IdString o,
+                            Tpred pred)
+    {
+        // Create the buffered net
+        NetInfo *buffered_net = ctx->createNet(ctx->idf("%s$%s", ctx->nameOf(net), name_postfix.c_str()));
+        // Create the buffer cell
+        CellInfo *buffer = ctx->createCell(ctx->idf("%s$drv_%s", ctx->nameOf(buffered_net), ctx->nameOf(buffer_type)),
+                                           buffer_type);
+        buffer->addInput(i);
+        buffer->addOutput(o);
+        // Drive the buffered net with the buffer
+        buffer->connectPort(o, buffered_net);
+        // Filter users
+        std::vector<PortRef> remaining_users;
+
+        for (auto &usr : net->users) {
+            if (pred(usr)) {
+                usr.cell->ports[usr.port].net = buffered_net;
+                usr.cell->ports[usr.port].user_idx = buffered_net->users.add(usr);
+            } else {
+                remaining_users.push_back(usr);
+            }
+        }
+
+        net->users.clear();
+        for (auto &usr : remaining_users)
+            usr.cell->ports.at(usr.port).user_idx = net->users.add(usr);
+
+        // Connect buffer input to original net
+        buffer->connectPort(i, net);
+
+        return buffer;
+    }
+
+    // Insert global buffers
+    void promote_globals()
+    {
+        std::vector<std::pair<int, IdString>> clk_fanout;
+        int available_globals = 8;
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            // Skip undriven nets; and nets that are already global
+            if (ni->driver.cell == nullptr)
+                continue;
+            if (ni->name.in(ctx->id("$PACKER_GND_NET"), ctx->id("$PACKER_VCC_NET")))
+                continue;
+            if (ni->driver.cell->type == id_DCMA) {
+                continue;
+            }
+            if (ni->driver.cell->type == id_DCCA) {
+                --available_globals;
+                continue;
+            }
+            // Count the number of clock ports
+            int clk_count = 0;
+            for (const auto &usr : ni->users) {
+                if (usr.cell->type == id_TRELLIS_FF && usr.port == id_CLK)
+                    clk_count++;
+                if (usr.cell->type == id_DP8KC && usr.port.in(id_CLKA, id_CLKB))
+                    clk_count++;
+            }
+            if (clk_count > 0)
+                clk_fanout.emplace_back(clk_count, ni->name);
+        }
+        if (available_globals <= 0)
+            return;
+        // Sort clocks by max fanout
+        std::sort(clk_fanout.begin(), clk_fanout.end(), std::greater<std::pair<int, IdString>>());
+        log_info("Promoting globals...\n");
+        // Promote the N highest fanout clocks
+        for (size_t i = 0; i < std::min<size_t>(clk_fanout.size(), available_globals); i++) {
+            NetInfo *net = ctx->nets.at(clk_fanout.at(i).second).get();
+            log_info("     promoting clock net '%s'\n", ctx->nameOf(net));
+            insert_buffer(net, id_DCCA, "glb_clk", id_CLKI, id_CLKO,
+                          [&](const PortRef &port) { return port.cell->type != id_DCCA; });
+        }
+    }
+
+    // Place certain global cells
+    void place_globals()
+    {
+        // Keep running until we reach a fixed point
+        log_info("Placing globals...\n");
+        bool did_something = true;
+        while (did_something) {
+            did_something = false;
+            for (auto &cell : ctx->cells) {
+                CellInfo *ci = cell.second.get();
+                if (ci->type == id_OSCH)
+                    did_something |= preplace_singleton(ci);
+                else if (ci->type == id_DCCA)
+                    did_something |= preplace_prim(ci, id_CLKI, false);
+                else if (ci->type == id_EHXPLLJ)
+                    did_something |= preplace_prim(ci, id_CLKI, false);
+            }
+        }
+    }
+
   public:
     void pack()
     {
         prepack_checks();
         print_logic_usage();
         pack_io();
-        preplace_plls();
         pack_ebr();
         pack_misc();
         pack_constants();
@@ -1249,6 +1443,8 @@ class MachXO2Packer
         pack_carries();
         pack_luts();
         pack_ffs();
+        promote_globals();
+        place_globals();
         generate_constraints();
         ctx->fixupHierarchy();
         ctx->check();

From 57b923a6031f28f5d5a2c48d733cd86a3bcf2737 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 20 Apr 2023 19:49:36 +0200
Subject: [PATCH 378/712] =?UTF-8?q?himb=C3=A4chel:=20Initial=20implementat?=
 =?UTF-8?q?ion?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/ci/build_himbaechel.sh               |  27 +
 .github/workflows/arch_ci.yml                |   4 +-
 CMakeLists.txt                               |   4 +-
 docs/himbaechel.md                           |  26 +
 gui/himbaechel/family.cmake                  |   0
 gui/himbaechel/mainwindow.cpp                |  52 ++
 gui/himbaechel/mainwindow.h                  |  45 ++
 gui/himbaechel/nextpnr.qrc                   |   2 +
 himbaechel/.gitignore                        |   1 +
 himbaechel/arch.cc                           | 264 +++++++
 himbaechel/arch.h                            | 682 +++++++++++++++++++
 himbaechel/arch_pybindings.cc                |  73 ++
 himbaechel/arch_pybindings.h                 |  98 +++
 himbaechel/archdefs.h                        | 106 +++
 himbaechel/chipdb.h                          | 235 +++++++
 himbaechel/family.cmake                      |   7 +
 himbaechel/himbaechel_api.cc                 | 105 +++
 himbaechel/himbaechel_api.h                  | 127 ++++
 himbaechel/himbaechel_constids.h             |  74 ++
 himbaechel/himbaechel_dbgen/bba.py           |  26 +
 himbaechel/himbaechel_dbgen/chip.py          | 519 ++++++++++++++
 himbaechel/himbaechel_helpers.cc             | 141 ++++
 himbaechel/himbaechel_helpers.h              |  75 ++
 himbaechel/main.cc                           |  97 +++
 himbaechel/uarch/example/blinky.v            |  16 +
 himbaechel/uarch/example/constids.inc        |  14 +
 himbaechel/uarch/example/example.cc          | 144 ++++
 himbaechel/uarch/example/example_arch_gen.py | 216 ++++++
 28 files changed, 3176 insertions(+), 4 deletions(-)
 create mode 100644 .github/ci/build_himbaechel.sh
 create mode 100644 docs/himbaechel.md
 create mode 100644 gui/himbaechel/family.cmake
 create mode 100644 gui/himbaechel/mainwindow.cpp
 create mode 100644 gui/himbaechel/mainwindow.h
 create mode 100644 gui/himbaechel/nextpnr.qrc
 create mode 100644 himbaechel/.gitignore
 create mode 100644 himbaechel/arch.cc
 create mode 100644 himbaechel/arch.h
 create mode 100644 himbaechel/arch_pybindings.cc
 create mode 100644 himbaechel/arch_pybindings.h
 create mode 100644 himbaechel/archdefs.h
 create mode 100644 himbaechel/chipdb.h
 create mode 100644 himbaechel/family.cmake
 create mode 100644 himbaechel/himbaechel_api.cc
 create mode 100644 himbaechel/himbaechel_api.h
 create mode 100644 himbaechel/himbaechel_constids.h
 create mode 100644 himbaechel/himbaechel_dbgen/bba.py
 create mode 100644 himbaechel/himbaechel_dbgen/chip.py
 create mode 100644 himbaechel/himbaechel_helpers.cc
 create mode 100644 himbaechel/himbaechel_helpers.h
 create mode 100644 himbaechel/main.cc
 create mode 100644 himbaechel/uarch/example/blinky.v
 create mode 100644 himbaechel/uarch/example/constids.inc
 create mode 100644 himbaechel/uarch/example/example.cc
 create mode 100644 himbaechel/uarch/example/example_arch_gen.py

diff --git a/.github/ci/build_himbaechel.sh b/.github/ci/build_himbaechel.sh
new file mode 100644
index 0000000000..e8adaf8d79
--- /dev/null
+++ b/.github/ci/build_himbaechel.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+function get_dependencies {
+    :
+}
+
+function build_nextpnr {
+    mkdir build
+    pushd build
+    cmake .. -DARCH=himbaechel
+    make nextpnr-himbaechel bbasm -j`nproc`
+    # We'd ideally use pypy3 for speed (as works locally), but the version
+    # our CI Ubuntu provides doesn't like some of the typing stuff
+    python3 ../himbaechel/uarch/example/example_arch_gen.py ./example.bba
+    ./bba/bbasm --l ./example.bba ./example.bin
+    popd
+}
+
+function run_tests {
+    :
+}
+
+function run_archcheck {
+    pushd build
+    ./nextpnr-himbaechel --uarch example --chipdb ./example.bin --test
+    popd
+}
diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index db13c4cb11..72150bc6ae 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -9,7 +9,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        arch: [mistral, ice40, ecp5, generic, nexus, machxo2, gowin]
+        arch: [mistral, ice40, ecp5, generic, nexus, machxo2, gowin, himbaechel]
     runs-on: ubuntu-latest
     env:
       DEPS_PATH: ${{ github.workspace }}/deps
@@ -30,7 +30,7 @@ jobs:
     - name: Install
       run: |
         sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools iverilog
+        sudo apt-get install git make cmake libboost-all-dev python3-dev pypy3 libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools iverilog
 
     - name: Cache yosys installation
       uses: actions/cache@v3
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4018cc3efe..b2e8f00693 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -94,9 +94,9 @@ endif()
 set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
 
 # List of families to build
-set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2 mistral)
+set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2 mistral himbaechel)
 set(STABLE_FAMILIES generic ice40 ecp5)
-set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2 mistral)
+set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2 mistral himbaechel)
 
 set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
 set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
diff --git a/docs/himbaechel.md b/docs/himbaechel.md
new file mode 100644
index 0000000000..aec222b95b
--- /dev/null
+++ b/docs/himbaechel.md
@@ -0,0 +1,26 @@
+# Himbächel - a series of bigger arches
+
+[Viaduct](./viaduct.md) enables custom architectures to be easily prototyped using a C++ API to build in-memory databases; with most of the flexibility of nextpnr's validity checking capabilities to hand. This is the recommended way to get started quickly with FPGAs up to about 20k logic elements, where no other particularly unusal requirements exist.
+
+However, building the routing graph in-memory at every startup and storing it flat doesn't scale at all well with larger FPGAs (say, 100k LEs or bigger).
+So, we take advantage of nextpnr's support for complex, non-flat routing graph structures and define a deduplication approach that's designed to work better even for very large fabrics - the database size is unlikely to exceed about 100MB even for million-LUT scale devices, compared to multiple gigabytes for a flat database.
+
+Python scripting is defined that allows the user to describe a semi-flattened routing graph and build the deduplicated database binary _at compile time_. Pips - routing switches - are described per tile type rather than flat; however, the connectivity between tiles ("nodes") are described flat and automatically deduplicated during database build.
+
+## Getting Started
+
+Most of what's written in the [viaduct docs](./viaduct.md) also applies to bootstrapping a Himbächel arch - this also provides a migration path for an existing Viaduct architecture. Just replace `viaduct` with `himbaechel` and `ViaductAPI` with `HimbaechelAPI` - the set of validity checking and custom flow "hooks" that you have access to is designed to be otherwise as close as possible.
+
+However, the key difference is that you will need to generate a "binary blob" chip database. `himbaechel_dbgen/bba.py` provides a framework for this. The typical steps for using this API would be as follows:
+ - Create a `Chip` instance
+ - For each unique "tile type" in the design (e.g. logic, BRAM, IO - in some cases multiple variants of these may be multiple tile types):
+     - Create it using `Chip.create_tile_type`
+     - Add local wires (connectivity between tiles is dealt with later) using `TileType.create_wire`
+     - Add bels (like LUTs and FFs) using `TileType.create_bel`, and pins to those bels using `TileType.add_bel_pin`
+     - Add pips using `TileType.create_pip`
+ - For each grid location, use `Chip.set_tile_type` to set its tile type. Every location must have a tile type set, even if it's just an empty "NULL" tile
+ - Whenever wires span multiple tiles (i.e. all wires with a length greater than zero), combine the per-tile local wires into a single node using `Chip.add_node` for each case. 
+ - Write out the `.bba` file using `Chip.write_bba`
+ - Compile it into a binary that nextpnr can load using `./bba/bbasm --l my_chipdb.bba my_chipdb.bin`
+
+An example Python generator to copy from is located in `uarch/example/example_arch_gen.py`.
diff --git a/gui/himbaechel/family.cmake b/gui/himbaechel/family.cmake
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/gui/himbaechel/mainwindow.cpp b/gui/himbaechel/mainwindow.cpp
new file mode 100644
index 0000000000..e9d280eb98
--- /dev/null
+++ b/gui/himbaechel/mainwindow.cpp
@@ -0,0 +1,52 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+
+#include <QMessageBox>
+#include <cstdlib>
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-himbächel - " + ctx->getChipName();
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::createMenu() {}
+
+void MainWindow::new_proj()
+{
+    QMessageBox::critical(0, "Error",
+                          "Creating a new project not supported in himbächel mode, please re-start from command line.");
+    std::exit(1);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/himbaechel/mainwindow.h b/gui/himbaechel/mainwindow.h
new file mode 100644
index 0000000000..7cdb238b06
--- /dev/null
+++ b/gui/himbaechel/mainwindow.h
@@ -0,0 +1,45 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected Q_SLOTS:
+    void new_proj() override;
+    void newContext(Context *ctx);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/himbaechel/nextpnr.qrc b/gui/himbaechel/nextpnr.qrc
new file mode 100644
index 0000000000..03585ec030
--- /dev/null
+++ b/gui/himbaechel/nextpnr.qrc
@@ -0,0 +1,2 @@
+<RCC>
+</RCC>
diff --git a/himbaechel/.gitignore b/himbaechel/.gitignore
new file mode 100644
index 0000000000..bee8a64b79
--- /dev/null
+++ b/himbaechel/.gitignore
@@ -0,0 +1 @@
+__pycache__
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
new file mode 100644
index 0000000000..6f5b303eed
--- /dev/null
+++ b/himbaechel/arch.cc
@@ -0,0 +1,264 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "arch.h"
+#include "archdefs.h"
+#include "chipdb.h"
+#include "log.h"
+#include "nextpnr.h"
+
+#include "util.h"
+#include "placer1.h"
+#include "placer_heap.h"
+#include "router1.h"
+#include "router2.h"
+
+
+
+NEXTPNR_NAMESPACE_BEGIN
+
+static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
+
+Arch::Arch(ArchArgs args)
+{
+    try {
+        blob_file.open(args.chipdb);
+        if (args.chipdb.empty() || !blob_file.is_open())
+            log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
+        const char *blob = reinterpret_cast<const char *>(blob_file.data());
+        chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(blob));
+    } catch (...) {
+        log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
+    }
+    // Check consistency of blob
+    if (chip_info->magic != 0x00ca7ca7)
+        log_error("chipdb %s does not look like a valid himbächel database!\n", args.chipdb.c_str());
+    std::string blob_uarch(chip_info->uarch.get());
+    if (blob_uarch != args.uarch)
+        log_error("database device uarch '%s' does not match selected device uarch '%s'.\n", blob_uarch.c_str(),
+                  args.uarch.c_str());
+    // Load uarch
+    uarch = HimbaechelArch::create(args.uarch, args.options);
+    if (!uarch) {
+        std::string available = HimbaechelArch::list();
+        log_error("unable to load device uarch '%s', available options: %s\n", args.uarch.c_str(), available.c_str());
+    }
+    uarch->init_constids(this);
+    // Setup constids from database
+    for (int i = 0; i < chip_info->extra_constids->bba_ids.ssize(); i++) {
+        IdString::initialize_add(this, chip_info->extra_constids->bba_ids[i].get(),
+                                 i + chip_info->extra_constids->known_id_count);
+    }
+    init_tiles();
+}
+
+void Arch::init_tiles()
+{
+    for (int y = 0; y < chip_info->height; y++) {
+        for (int x = 0; x < chip_info->width; x++) {
+            int tile = y * chip_info->width + x;
+            auto &inst = chip_info->tile_insts[tile];
+            IdString name = idf("%sX%dY%d", IdString(inst.name_prefix).c_str(this), x, y);
+            NPNR_ASSERT(int(tile_name.size()) == tile);
+            tile_name.push_back(name);
+            tile_name2idx[name] = tile;
+        }
+    }
+}
+
+void Arch::late_init()
+{
+    BaseArch::init_cell_types();
+    BaseArch::init_bel_buckets();
+}
+
+BelId Arch::getBelByName(IdStringList name) const
+{
+    NPNR_ASSERT(name.size() == 2);
+    int tile = tile_name2idx.at(name[0]);
+    const auto &tdata = chip_tile_info(chip_info, tile);
+    for (int bel = 0; bel < tdata.bels.ssize(); bel++) {
+        if (IdString(tdata.bels[bel].name) == name[1])
+            return BelId(tile, bel);
+    }
+    return BelId();
+}
+
+IdStringList Arch::getBelName(BelId bel) const
+{
+    return IdStringList::concat(tile_name.at(bel.tile), IdString(chip_bel_info(chip_info, bel).name));
+}
+
+WireId Arch::getBelPinWire(BelId bel, IdString pin) const
+{
+    // TODO: binary search
+    auto &info = chip_bel_info(chip_info, bel);
+    for (auto &bel_pin : info.pins) {
+        if (IdString(bel_pin.name) == pin)
+            return normalise_wire(bel.tile, bel_pin.wire);
+    }
+    return WireId();
+}
+
+PortType Arch::getBelPinType(BelId bel, IdString pin) const
+{
+    auto &info = chip_bel_info(chip_info, bel);
+    for (auto &bel_pin : info.pins) {
+        if (IdString(bel_pin.name) == pin)
+            return PortType(bel_pin.type);
+    }
+    NPNR_ASSERT_FALSE("bel pin not found");
+}
+
+std::vector<IdString> Arch::getBelPins(BelId bel) const
+{
+    std::vector<IdString> result;
+    auto &info = chip_bel_info(chip_info, bel);
+    result.reserve(info.pins.size());
+    for (auto &bel_pin : info.pins)
+        result.emplace_back(bel_pin.name);
+    return result;
+}
+
+bool Arch::pack()
+{
+    log_break();
+    uarch->pack();
+    getCtx()->assignArchInfo();
+    getCtx()->settings[id("pack")] = 1;
+    log_info("Checksum: 0x%08x\n", getCtx()->checksum());
+    return true;
+}
+
+bool Arch::place()
+{
+    bool retVal = false;
+    uarch->prePlace();
+    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+    if (placer == "heap") {
+        PlacerHeapCfg cfg(getCtx());
+        uarch->configurePlacerHeap(cfg);
+        cfg.ioBufTypes.insert(id("GENERIC_IOB"));
+        retVal = placer_heap(getCtx(), cfg);
+    } else if (placer == "sa") {
+        retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
+    } else {
+        log_error("Himbächel architecture does not support placer '%s'\n", placer.c_str());
+    }
+    uarch->postPlace();
+    getCtx()->settings[getCtx()->id("place")] = 1;
+    archInfoToAttributes();
+    return retVal;
+}
+
+bool Arch::route()
+{
+    uarch->preRoute();
+    std::string router = str_or_default(settings, id("router"), defaultRouter);
+    bool result;
+    if (router == "router1") {
+        result = router1(getCtx(), Router1Cfg(getCtx()));
+    } else if (router == "router2") {
+        router2(getCtx(), Router2Cfg(getCtx()));
+        result = true;
+    } else {
+        log_error("Himbächel architecture does not support router '%s'\n", router.c_str());
+    }
+    uarch->postRoute();
+    getCtx()->settings[getCtx()->id("route")] = 1;
+    archInfoToAttributes();
+    return result;
+}
+
+void Arch::assignArchInfo()
+{
+    int cell_idx = 0, net_idx = 0;
+    for (auto &cell : cells) {
+        CellInfo *ci = cell.second.get();
+        ci->flat_index = cell_idx++;
+        for (auto &port : ci->ports) {
+            // Default 1:1 cell:bel mapping
+            if (!ci->cell_bel_pins.count(port.first))
+                ci->cell_bel_pins[port.first].push_back(port.first);
+        }
+    }
+    for (auto &net : nets) {
+        net.second->flat_index = net_idx++;
+    }
+}
+
+WireId Arch::getWireByName(IdStringList name) const
+{
+    NPNR_ASSERT(name.size() == 2);
+    int tile = tile_name2idx.at(name[0]);
+    const auto &tdata = chip_tile_info(chip_info, tile);
+    for (int wire = 0; wire < tdata.wires.ssize(); wire++) {
+        if (IdString(tdata.wires[wire].name) == name[1])
+            return WireId(tile, wire);
+    }
+    return WireId();
+}
+
+IdStringList Arch::getWireName(WireId wire) const
+{
+    return IdStringList::concat(tile_name.at(wire.tile), IdString(chip_wire_info(chip_info, wire).name));
+}
+
+PipId Arch::getPipByName(IdStringList name) const
+{
+    NPNR_ASSERT(name.size() == 3);
+    int tile = tile_name2idx.at(name[0]);
+    const auto &tdata = chip_tile_info(chip_info, tile);
+    for (int pip = 0; pip < tdata.pips.ssize(); pip++) {
+        if (IdString(tdata.wires[tdata.pips[pip].dst_wire].name) == name[1] &&
+            IdString(tdata.wires[tdata.pips[pip].src_wire].name) == name[2])
+            return PipId(tile, pip);
+    }
+    return PipId();
+}
+
+IdStringList Arch::getPipName(PipId pip) const
+{
+    auto &tdata = chip_tile_info(chip_info, pip.tile);
+    auto &pdata = tdata.pips[pip.index];
+    return IdStringList::concat(tile_name.at(pip.tile),
+                                IdStringList::concat(IdString(tdata.wires[pdata.dst_wire].name),
+                                                     IdString(tdata.wires[pdata.src_wire].name)));
+}
+
+IdString Arch::getPipType(PipId pip) const { return IdString(); }
+
+std::string Arch::getChipName() const { return chip_info->name.get(); }
+
+IdString Arch::archArgsToId(ArchArgs args) const
+{
+    // TODO
+    return IdString();
+}
+
+void IdString::initialize_arch(const BaseCtx *ctx) {}
+
+const std::string Arch::defaultPlacer = "heap";
+
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
+
+const std::string Arch::defaultRouter = "router1";
+const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
new file mode 100644
index 0000000000..e5a4541826
--- /dev/null
+++ b/himbaechel/arch.h
@@ -0,0 +1,682 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-2023  gatecat <gatecat@ds0.me>
+ *
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_ARCH_H
+#define HIMBAECHEL_ARCH_H
+
+#include <boost/iostreams/device/mapped_file.hpp>
+#include <iostream>
+
+#include "base_arch.h"
+#include "chipdb.h"
+#include "himbaechel_api.h"
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+inline const TileTypePOD &chip_tile_info(const ChipInfoPOD *chip, int tile)
+{
+    return chip->tile_types[chip->tile_insts[tile].type];
+}
+inline const BelDataPOD &chip_bel_info(const ChipInfoPOD *chip, BelId bel)
+{
+    return chip_tile_info(chip, bel.tile).bels[bel.index];
+}
+inline const TileWireDataPOD &chip_wire_info(const ChipInfoPOD *chip, WireId wire)
+{
+    return chip_tile_info(chip, wire.tile).wires[wire.index];
+}
+inline const PipDataPOD &chip_pip_info(const ChipInfoPOD *chip, PipId pip)
+{
+    return chip_tile_info(chip, pip.tile).pips[pip.index];
+}
+inline const TileRoutingShapePOD &chip_tile_shape(const ChipInfoPOD *chip, int tile)
+{
+    return chip->tile_shapes[chip->tile_insts[tile].shape];
+}
+inline uint32_t node_shape_idx(const RelNodeRefPOD &node_entry)
+{
+    return uint16_t(node_entry.dy) | (uint32_t(node_entry.wire) << 16);
+}
+inline const NodeShapePOD &chip_node_shape(const ChipInfoPOD *chip, int tile, int node)
+{
+    auto &node_entry = chip->tile_shapes[chip->tile_insts[tile].shape].wire_to_node[node];
+    NPNR_ASSERT(node_entry.dx_mode == RelNodeRefPOD::MODE_IS_ROOT);
+    uint32_t node_shape = node_shape_idx(node_entry);
+    return chip->node_shapes[node_shape];
+}
+inline void tile_xy(const ChipInfoPOD *chip, int tile, int &x, int &y)
+{
+    x = tile % chip->width;
+    y = tile / chip->width;
+}
+inline int tile_by_xy(const ChipInfoPOD *chip, int x, int y) { return y * chip->width + x; }
+inline int rel_tile(const ChipInfoPOD *chip, int base, int dx, int dy)
+{
+    int x = base % chip->width;
+    int y = base / chip->width;
+    if (dx == RelNodeRefPOD::MODE_ROW_CONST) {
+        return y * chip->width;
+    } else if (dx == RelNodeRefPOD::MODE_GLB_CONST) {
+        return 0;
+    } else {
+        return (x + dx) + (y + dy) * chip->width;
+    }
+}
+
+inline bool is_root_wire(const ChipInfoPOD *chip, int tile, int index)
+{
+    auto &shape = chip_tile_shape(chip, tile);
+    if (index >= shape.wire_to_node.ssize())
+        return true;
+    auto &node_entry = shape.wire_to_node[index];
+    return (node_entry.dx_mode == RelNodeRefPOD::MODE_IS_ROOT || node_entry.dx_mode == RelNodeRefPOD::MODE_TILE_WIRE);
+}
+
+inline bool is_nodal_wire(const ChipInfoPOD *chip, int tile, int index)
+{
+    auto &shape = chip_tile_shape(chip, tile);
+    if (index >= shape.wire_to_node.ssize())
+        return false;
+    auto &node_entry = shape.wire_to_node[index];
+    return (node_entry.dx_mode == RelNodeRefPOD::MODE_IS_ROOT);
+}
+
+// Shared code between bel and pip iterators
+template <typename Tid, typename Tdata, RelSlice<Tdata> TileTypePOD::*ptr> struct TileObjIterator
+{
+    const ChipInfoPOD *chip;
+    int cursor_tile;
+    int cursor_index;
+    bool single_tile;
+
+    TileObjIterator(const ChipInfoPOD *chip, int tile, int index, bool single_tile = false)
+            : chip(chip), cursor_tile(tile), cursor_index(index), single_tile(single_tile)
+    {
+    }
+
+    TileObjIterator operator++()
+    {
+        cursor_index++;
+        if (!single_tile) {
+            while (cursor_tile < chip->tile_insts.ssize() &&
+                   cursor_index >= (chip_tile_info(chip, cursor_tile).*ptr).ssize()) {
+                cursor_index = 0;
+                cursor_tile++;
+            }
+        }
+        return *this;
+    }
+    TileObjIterator operator++(int)
+    {
+        TileObjIterator prior(*this);
+        ++(*this);
+        return prior;
+    }
+
+    bool operator!=(const TileObjIterator<Tid, Tdata, ptr> &other) const
+    {
+        return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
+    }
+
+    bool operator==(const TileObjIterator<Tid, Tdata, ptr> &other) const
+    {
+        return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
+    }
+
+    Tid operator*() const
+    {
+        Tid ret;
+        ret.tile = cursor_tile;
+        ret.index = cursor_index;
+        return ret;
+    }
+};
+
+template <typename Tid, typename Tdata, RelSlice<Tdata> TileTypePOD::*ptr> struct TileObjRange
+{
+    using iterator = TileObjIterator<Tid, Tdata, ptr>;
+    explicit TileObjRange(const ChipInfoPOD *chip) : b(chip, 0, -1), e(chip, chip->tile_insts.size(), 0)
+    {
+        // this deals with the case of no objects in tile 0
+        ++b;
+    }
+    TileObjRange(const ChipInfoPOD *chip, int tile)
+            : b(chip, tile, 0, true), e(chip, tile, (chip_tile_info(chip, tile).*ptr).ssize(), true)
+    {
+    }
+
+    iterator b, e;
+    iterator begin() const { return b; }
+    iterator end() const { return e; }
+};
+
+struct TileWireIterator
+{
+    const ChipInfoPOD *chip;
+    WireId base;
+    int node_shape;
+    int cursor;
+
+    TileWireIterator(const ChipInfoPOD *chip, WireId base, int node_shape, int cursor)
+            : chip(chip), base(base), node_shape(node_shape), cursor(cursor){};
+
+    void operator++() { cursor++; }
+    bool operator!=(const TileWireIterator &other) const { return cursor != other.cursor; }
+
+    // Returns a *denormalised* identifier always pointing to a tile wire rather than a node
+    WireId operator*() const
+    {
+        if (node_shape != -1) {
+            WireId tw;
+            const auto &node_wire = chip->node_shapes[node_shape].tile_wires[cursor];
+            tw.tile = rel_tile(chip, base.tile, node_wire.dx, node_wire.dy);
+            tw.index = node_wire.wire;
+            return tw;
+        } else {
+            return base;
+        }
+    }
+};
+
+struct TileWireRange
+{
+    // is nodal
+    TileWireRange(const ChipInfoPOD *chip, WireId base, int node_shape)
+            : b(chip, base, node_shape, -1), e(chip, base, node_shape, chip->node_shapes[node_shape].tile_wires.ssize())
+    {
+        // this deals with more complex iteration possibilities simpler, like the first entry being empty
+        NPNR_ASSERT(node_shape != -1);
+        ++b;
+    };
+
+    // is not nodal
+    explicit TileWireRange(WireId w) : b(nullptr, w, -1, 0), e(nullptr, w, -1, 1){};
+
+    TileWireIterator b, e;
+    TileWireIterator begin() const { return b; }
+    TileWireIterator end() const { return e; }
+};
+
+struct WireIterator
+{
+    const ChipInfoPOD *chip;
+    int cursor_tile = 0;
+    int cursor_index = -1;
+
+    WireIterator(const ChipInfoPOD *chip, int tile, int index) : chip(chip), cursor_tile(tile), cursor_index(index){};
+
+    WireIterator operator++()
+    {
+        // Iterate over tile wires, skipping wires that aren't normalised (i.e. they are part of another wire's node)
+        do {
+            cursor_index++;
+            while (cursor_tile < chip->tile_insts.ssize() &&
+                   cursor_index >= chip_tile_info(chip, cursor_tile).wires.ssize()) {
+                cursor_index = 0;
+                cursor_tile++;
+            }
+
+        } while (cursor_tile < chip->tile_insts.ssize() && !is_root_wire(chip, cursor_tile, cursor_index));
+
+        return *this;
+    }
+    WireIterator operator++(int)
+    {
+        WireIterator prior(*this);
+        ++(*this);
+        return prior;
+    }
+
+    bool operator!=(const WireIterator &other) const
+    {
+        return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
+    }
+
+    bool operator==(const WireIterator &other) const
+    {
+        return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
+    }
+
+    WireId operator*() const
+    {
+        WireId ret;
+        ret.tile = cursor_tile;
+        ret.index = cursor_index;
+        return ret;
+    }
+};
+
+struct WireRange
+{
+    explicit WireRange(const ChipInfoPOD *chip) : b(chip, 0, -1), e(chip, chip->tile_insts.ssize(), 0)
+    {
+        // covers the case of no wires in tile 0
+        ++b;
+    }
+    WireIterator b, e;
+    WireIterator begin() const { return b; }
+    WireIterator end() const { return e; }
+};
+
+// -----------------------------------------------------------------------
+
+template <RelSlice<int32_t> TileWireDataPOD::*ptr> struct UpdownhillPipIterator
+{
+    const ChipInfoPOD *chip;
+    TileWireIterator twi, twi_end;
+    int cursor = -1;
+
+    UpdownhillPipIterator(const ChipInfoPOD *chip, TileWireIterator twi, TileWireIterator twi_end, int cursor)
+            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor){};
+
+    void operator++()
+    {
+        cursor++;
+        while (true) {
+            if (!(twi != twi_end))
+                break;
+            WireId w = *twi;
+            if (cursor < (chip_wire_info(chip, w).*ptr).ssize())
+                break;
+            ++twi;
+            cursor = 0;
+        }
+    }
+    bool operator!=(const UpdownhillPipIterator<ptr> &other) const
+    {
+        return twi != other.twi || cursor != other.cursor;
+    }
+
+    PipId operator*() const
+    {
+        PipId ret;
+        WireId w = *twi;
+        ret.tile = w.tile;
+        ret.index = (chip_wire_info(chip, w).*ptr)[cursor];
+        return ret;
+    }
+};
+
+template <RelSlice<int32_t> TileWireDataPOD::*ptr> struct UpDownhillPipRange
+{
+    using iterator = UpdownhillPipIterator<ptr>;
+    UpDownhillPipRange(const ChipInfoPOD *chip, const TileWireRange &twr)
+            : b(chip, twr.begin(), twr.end(), -1), e(chip, twr.end(), twr.end(), 0)
+    {
+        ++b;
+    }
+    iterator b, e;
+    iterator begin() const { return b; }
+    iterator end() const { return e; }
+};
+
+// -----------------------------------------------------------------------
+
+struct BelPinIterator
+{
+    const ChipInfoPOD *chip;
+    TileWireIterator twi, twi_end;
+    int cursor = -1;
+
+    BelPinIterator(const ChipInfoPOD *chip, TileWireIterator twi, TileWireIterator twi_end, int cursor)
+            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor){};
+
+    void operator++()
+    {
+        cursor++;
+        while (true) {
+            if (!(twi != twi_end))
+                break;
+            WireId w = *twi;
+            if (cursor < chip_wire_info(chip, w).bel_pins.ssize())
+                break;
+            ++twi;
+            cursor = 0;
+        }
+    }
+    bool operator!=(const BelPinIterator &other) const { return twi != other.twi || cursor != other.cursor; }
+
+    BelPin operator*() const
+    {
+        BelPin ret;
+        WireId w = *twi;
+        auto &bp_data = chip_wire_info(chip, w).bel_pins[cursor];
+        ret.bel.tile = w.tile;
+        ret.bel.index = bp_data.bel;
+        ret.pin = IdString(bp_data.pin);
+        return ret;
+    }
+};
+
+struct BelPinRange
+{
+    using iterator = BelPinIterator;
+    BelPinRange(const ChipInfoPOD *chip, const TileWireRange &twr)
+            : b(chip, twr.begin(), twr.end(), -1), e(chip, twr.end(), twr.end(), 0)
+    {
+        ++b;
+    }
+    iterator b, e;
+    iterator begin() const { return b; }
+    iterator end() const { return e; }
+};
+
+}; // namespace
+
+struct ArchArgs
+{
+    std::string uarch;
+    std::string chipdb;
+    std::string device;
+    dict<std::string, std::string> options;
+};
+
+typedef TileObjRange<BelId, BelDataPOD, &TileTypePOD::bels> BelRange;
+typedef TileObjRange<PipId, PipDataPOD, &TileTypePOD::pips> AllPipRange;
+
+typedef UpDownhillPipRange<&TileWireDataPOD::pips_uphill> UphillPipRange;
+typedef UpDownhillPipRange<&TileWireDataPOD::pips_downhill> DownhillPipRange;
+
+struct ArchRanges : BaseArchRanges
+{
+    using ArchArgsT = ArchArgs;
+    // Bels
+    using AllBelsRangeT = BelRange;
+    using TileBelsRangeT = BelRange;
+    using BelPinsRangeT = std::vector<IdString>;
+    using CellBelPinRangeT = const std::vector<IdString> &;
+    // Wires
+    using AllWiresRangeT = WireRange;
+    using DownhillPipRangeT = DownhillPipRange;
+    using UphillPipRangeT = UphillPipRange;
+    using WireBelPinRangeT = BelPinRange;
+    // Pips
+    using AllPipsRangeT = AllPipRange;
+};
+
+struct Arch : BaseArch<ArchRanges>
+{
+    ArchArgs args;
+    Arch(ArchArgs args);
+    ~Arch(){};
+
+    void late_init();
+
+    // Database references
+    boost::iostreams::mapped_file_source blob_file;
+    const ChipInfoPOD *chip_info;
+    const PackageInfoPOD *package_info = nullptr;
+
+    // Unlike Viaduct, we are not -generic based and therefore uarch must be non-nullptr
+    std::unique_ptr<HimbaechelAPI> uarch;
+
+    std::string getChipName() const override;
+    ArchArgs archArgs() const override { return args; }
+    IdString archArgsToId(ArchArgs args) const override;
+    // -------------------------------------------------
+
+    int getGridDimX() const override { return chip_info->width; }
+    int getGridDimY() const override { return chip_info->height; }
+    int getTileBelDimZ(int, int) const override { return 1024; } // TODO ?
+    int getTilePipDimZ(int, int) const override { return 1; }    // TODO ?
+    char getNameDelimiter() const override { return '/'; }       // TODO ?
+
+    // -------------------------------------------------
+
+    BelId getBelByName(IdStringList name) const override;
+    IdStringList getBelName(BelId bel) const override;
+    BelRange getBels() const override { return BelRange(chip_info); }
+    Loc getBelLocation(BelId bel) const override
+    {
+        Loc loc;
+        tile_xy(chip_info, bel.tile, loc.x, loc.y);
+        loc.z = chip_bel_info(chip_info, bel).z;
+        return loc;
+    }
+    BelId getBelByLocation(Loc loc) const override
+    {
+        int tile = tile_by_xy(chip_info, loc.x, loc.y);
+        auto &tile_data = chip_tile_info(chip_info, tile);
+        for (size_t i = 0; i < tile_data.bels.size(); i++) {
+            if (tile_data.bels[i].z == loc.z)
+                return BelId(tile, i);
+        }
+        return BelId();
+    }
+    BelRange getBelsByTile(int x, int y) const override { return BelRange(chip_info, tile_by_xy(chip_info, x, y)); }
+    bool getBelGlobalBuf(BelId bel) const override
+    {
+        return chip_bel_info(chip_info, bel).flags & BelDataPOD::FLAG_GLOBAL;
+    }
+    IdString getBelType(BelId bel) const override { return IdString(chip_bel_info(chip_info, bel).bel_type); }
+
+    WireId getBelPinWire(BelId bel, IdString pin) const override;
+    PortType getBelPinType(BelId bel, IdString pin) const override;
+    std::vector<IdString> getBelPins(BelId bel) const override;
+
+    bool getBelHidden(BelId bel) const final { return chip_bel_info(chip_info, bel).flags & BelDataPOD::FLAG_HIDDEN; }
+
+    // -------------------------------------------------
+
+    WireId getWireByName(IdStringList name) const override;
+    IdStringList getWireName(WireId wire) const override;
+    IdString getWireType(WireId wire) const override { return IdString(chip_wire_info(chip_info, wire).wire_type); }
+    DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); } // TODO
+    BelPinRange getWireBelPins(WireId wire) const override { return BelPinRange(chip_info, get_tile_wire_range(wire)); }
+    WireRange getWires() const override { return WireRange(chip_info); }
+    bool checkWireAvail(WireId wire) const override
+    {
+        if (!uarch->checkWireAvail(wire))
+            return false;
+        return BaseArch::checkWireAvail(wire);
+    }
+    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
+    {
+        uarch->notifyWireChange(wire, net);
+        BaseArch::bindWire(wire, net, strength);
+    }
+    void unbindWire(WireId wire) override
+    {
+        uarch->notifyWireChange(wire, nullptr);
+        BaseArch::unbindWire(wire);
+    }
+
+    // -------------------------------------------------
+
+    PipId getPipByName(IdStringList name) const override;
+    IdStringList getPipName(PipId pip) const override;
+    AllPipRange getPips() const override { return AllPipRange(chip_info); }
+    Loc getPipLocation(PipId pip) const override
+    {
+        Loc loc;
+        tile_xy(chip_info, pip.tile, loc.x, loc.y);
+        loc.z = 0;
+        return loc;
+    }
+    IdString getPipType(PipId pip) const override;
+    WireId getPipSrcWire(PipId pip) const override
+    {
+        return normalise_wire(pip.tile, chip_pip_info(chip_info, pip).src_wire);
+    }
+    WireId getPipDstWire(PipId pip) const override
+    {
+        return normalise_wire(pip.tile, chip_pip_info(chip_info, pip).dst_wire);
+    }
+    DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(100); }
+    DownhillPipRange getPipsDownhill(WireId wire) const override
+    {
+        return DownhillPipRange(chip_info, get_tile_wire_range(wire));
+    }
+    UphillPipRange getPipsUphill(WireId wire) const override
+    {
+        return UphillPipRange(chip_info, get_tile_wire_range(wire));
+    }
+
+    bool checkPipAvail(PipId pip) const override
+    {
+        if (!uarch->checkPipAvail(pip))
+            return false;
+        return BaseArch::checkPipAvail(pip);
+    }
+
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
+    {
+        if (!uarch->checkPipAvailForNet(pip, net))
+            return false;
+        return BaseArch::checkPipAvailForNet(pip, net);
+    }
+    void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
+    {
+        uarch->notifyPipChange(pip, net);
+        BaseArch::bindPip(pip, net, strength);
+    }
+    void unbindPip(PipId pip) override
+    {
+        uarch->notifyPipChange(pip, nullptr);
+        BaseArch::unbindPip(pip);
+    }
+
+    // -------------------------------------------------
+
+    delay_t estimateDelay(WireId src, WireId dst) const override { return uarch->estimateDelay(src, dst); }
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override
+    {
+        return uarch->predictDelay(src_bel, src_pin, dst_bel, dst_pin);
+    }
+    delay_t getDelayEpsilon() const override { return 20; }       // TODO
+    delay_t getRipupDelayPenalty() const override { return 120; } // TODO
+    float getDelayNS(delay_t v) const override { return v * 0.001; }
+    delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
+    uint32_t getDelayChecksum(delay_t v) const override { return v; }
+    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override
+    {
+        return false;
+    }
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override
+    {
+        return uarch->getRouteBoundingBox(src, dst);
+    }
+
+    // -------------------------------------------------
+
+    void assignArchInfo() override;
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override
+    {
+        return uarch->isBelLocationValid(bel, explain_invalid);
+    }
+
+    // ------------------------------------------------
+
+    const std::vector<IdString> &getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override
+    {
+        return cell_info->cell_bel_pins.at(pin);
+    }
+    void update_cell_bel_pins(CellInfo *cell);
+
+    // ------------------------------------------------
+
+    void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
+    {
+        uarch->notifyBelChange(bel, cell);
+        BaseArch::bindBel(bel, cell, strength); // TODO: faster?
+    }
+
+    void unbindBel(BelId bel) override
+    {
+        uarch->notifyBelChange(bel, nullptr);
+        BaseArch::unbindBel(bel); // TODO: faster?
+        // TODO: fast tile status and bind
+    }
+
+    bool checkBelAvail(BelId bel) const override
+    {
+        // TODO: fast tile status and bind
+        if (!uarch->checkBelAvail(bel))
+            return false;
+        return BaseArch::checkBelAvail(bel);
+    }
+
+    // getBoundBelCell: BaseArch
+
+    // ------------------------------------------------
+
+    BelBucketId getBelBucketForCellType(IdString cell_type) const override
+    {
+        return uarch->getBelBucketForCellType(cell_type);
+    }
+    BelBucketId getBelBucketForBel(BelId bel) const override { return uarch->getBelBucketForBel(bel); }
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        return uarch->isValidBelForCellType(cell_type, bel);
+    }
+
+    // ------------------------------------------------
+
+    // clusters: BaseArch; for now
+    // ------------------------------------------------
+
+    bool pack() override;
+    bool place() override;
+    bool route() override;
+
+    static const std::string defaultPlacer;
+    static const std::vector<std::string> availablePlacers;
+    static const std::string defaultRouter;
+    static const std::vector<std::string> availableRouters;
+
+    // -------------------------------------------------
+
+    WireId normalise_wire(int32_t tile, int32_t wire) const
+    {
+        auto &ts = chip_tile_shape(chip_info, tile);
+        if (wire >= ts.wire_to_node.ssize())
+            return WireId(tile, wire);
+        auto &w2n = ts.wire_to_node[wire];
+        if (w2n.dx_mode == RelNodeRefPOD::MODE_TILE_WIRE || w2n.dx_mode == RelNodeRefPOD::MODE_IS_ROOT)
+            return WireId(tile, wire);
+        return WireId(rel_tile(chip_info, tile, w2n.dx_mode, w2n.dy), w2n.wire);
+    }
+
+    TileWireRange get_tile_wire_range(WireId wire) const
+    {
+        auto &ts = chip_tile_shape(chip_info, wire.tile);
+        if (wire.index >= ts.wire_to_node.ssize())
+            return TileWireRange(wire);
+        auto &w2n = ts.wire_to_node[wire.index];
+        if (w2n.dx_mode != RelNodeRefPOD::MODE_TILE_WIRE) {
+            NPNR_ASSERT(w2n.dx_mode == RelNodeRefPOD::MODE_IS_ROOT);
+            return TileWireRange(chip_info, wire, node_shape_idx(w2n));
+        } else {
+            return TileWireRange(wire);
+        }
+    }
+
+    // -------------------------------------------------
+    void init_tiles();
+    std::vector<IdString> tile_name;
+    dict<IdString, int> tile_name2idx;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/arch_pybindings.cc b/himbaechel/arch_pybindings.cc
new file mode 100644
index 0000000000..246adcd9dc
--- /dev/null
+++ b/himbaechel/arch_pybindings.cc
@@ -0,0 +1,73 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020-23  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef NO_PYTHON
+
+#include "arch_pybindings.h"
+#include "nextpnr.h"
+#include "pybindings.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void arch_wrap_python(py::module &m)
+{
+    using namespace PythonConversion;
+    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb);
+
+    py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
+
+    py::class_<WireId>(m, "WireId").def_readwrite("index", &WireId::index);
+
+    py::class_<PipId>(m, "PipId").def_readwrite("index", &PipId::index);
+
+    auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
+    auto ctx_cls = py::class_<Context, Arch>(m, "Context")
+                           .def("checksum", &Context::checksum)
+                           .def("pack", &Context::pack)
+                           .def("place", &Context::place)
+                           .def("route", &Context::route);
+
+    typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap;
+    typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap;
+    typedef dict<IdString, IdString> AliasMap;
+    typedef dict<IdString, HierarchicalCell> HierarchyMap;
+
+    auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
+    readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
+    readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
+
+    typedef const std::vector<BelBucketId> &BelBucketRange;
+    typedef const std::vector<BelId> &BelRangeForBelBucket;
+#include "arch_pybindings_shared.h"
+
+    WRAP_RANGE(m, Bel, conv_to_str<BelId>);
+    WRAP_RANGE(m, Wire, conv_to_str<WireId>);
+    WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
+    WRAP_RANGE(m, UphillPip, conv_to_str<PipId>);
+    WRAP_RANGE(m, DownhillPip, conv_to_str<PipId>);
+    WRAP_RANGE(m, BelPin, wrap_context<BelPin>);
+
+    WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
+    WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
+    WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
+}
+
+NEXTPNR_NAMESPACE_END
+
+#endif // NO_PYTHON
diff --git a/himbaechel/arch_pybindings.h b/himbaechel/arch_pybindings.h
new file mode 100644
index 0000000000..c0dc6a8134
--- /dev/null
+++ b/himbaechel/arch_pybindings.h
@@ -0,0 +1,98 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020-23  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ARCH_PYBINDINGS_H
+#define ARCH_PYBINDINGS_H
+#ifndef NO_PYTHON
+
+#include "nextpnr.h"
+#include "pybindings.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace PythonConversion {
+
+template <> struct string_converter<BelId>
+{
+    BelId from_str(Context *ctx, std::string name) { return ctx->getBelByName(IdStringList::parse(ctx, name)); }
+
+    std::string to_str(Context *ctx, BelId id)
+    {
+        if (id == BelId())
+            throw bad_wrap();
+        return ctx->getBelName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<WireId>
+{
+    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
+
+    std::string to_str(Context *ctx, WireId id)
+    {
+        if (id == WireId())
+            throw bad_wrap();
+        return ctx->getWireName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<const WireId>
+{
+    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
+
+    std::string to_str(Context *ctx, WireId id)
+    {
+        if (id == WireId())
+            throw bad_wrap();
+        return ctx->getWireName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<PipId>
+{
+    PipId from_str(Context *ctx, std::string name) { return ctx->getPipByName(IdStringList::parse(ctx, name)); }
+
+    std::string to_str(Context *ctx, PipId id)
+    {
+        if (id == PipId())
+            throw bad_wrap();
+        return ctx->getPipName(id).str(ctx);
+    }
+};
+
+template <> struct string_converter<BelPin>
+{
+    BelPin from_str(Context *ctx, std::string name)
+    {
+        NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
+    }
+
+    std::string to_str(Context *ctx, BelPin pin)
+    {
+        if (pin.bel == BelId())
+            throw bad_wrap();
+        return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
+    }
+};
+
+} // namespace PythonConversion
+
+NEXTPNR_NAMESPACE_END
+#endif
+#endif
diff --git a/himbaechel/archdefs.h b/himbaechel/archdefs.h
new file mode 100644
index 0000000000..b3ede1e25f
--- /dev/null
+++ b/himbaechel/archdefs.h
@@ -0,0 +1,106 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023 gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_ARCHDEFS_H
+#define HIMBAECHEL_ARCHDEFS_H
+
+#include <array>
+#include <cstdint>
+
+#include "base_clusterinfo.h"
+#include "hashlib.h"
+#include "idstring.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+typedef int32_t delay_t;
+
+struct BelId
+{
+    int32_t tile = -1;
+    // PIP index in tile
+    int32_t index = -1;
+
+    BelId() = default;
+    BelId(int32_t tile, int32_t index) : tile(tile), index(index){};
+
+    bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
+    bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
+    bool operator<(const BelId &other) const
+    {
+        return tile < other.tile || (tile == other.tile && index < other.index);
+    }
+    unsigned int hash() const { return mkhash(tile, index); }
+};
+
+struct WireId
+{
+    int32_t tile = -1;
+    int32_t index = -1;
+
+    WireId() = default;
+    WireId(int32_t tile, int32_t index) : tile(tile), index(index){};
+
+    bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
+    bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
+    bool operator<(const WireId &other) const
+    {
+        return tile < other.tile || (tile == other.tile && index < other.index);
+    }
+    unsigned int hash() const { return mkhash(tile, index); }
+};
+
+struct PipId
+{
+    int32_t tile = -1;
+    // PIP index in tile
+    int32_t index = -1;
+
+    PipId() = default;
+    PipId(int32_t tile, int32_t index) : tile(tile), index(index){};
+
+    bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
+    bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
+    bool operator<(const PipId &other) const
+    {
+        return tile < other.tile || (tile == other.tile && index < other.index);
+    }
+    unsigned int hash() const { return mkhash(tile, index); }
+};
+
+typedef IdString DecalId;
+typedef IdString GroupId;
+typedef IdString BelBucketId;
+typedef IdString ClusterId;
+
+struct ArchNetInfo
+{
+    int flat_index;
+};
+
+struct ArchCellInfo : BaseClusterInfo
+{
+    int flat_index;
+    dict<IdString, std::vector<IdString>> cell_bel_pins;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
new file mode 100644
index 0000000000..07cf09ae23
--- /dev/null
+++ b/himbaechel/chipdb.h
@@ -0,0 +1,235 @@
+
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_CHIPDB_H
+#define HIMBAECHEL_CHIPDB_H
+
+#include "archdefs.h"
+#include "nextpnr_namespaces.h"
+#include "relptr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+NPNR_PACKED_STRUCT(struct BelPinPOD {
+    int32_t name;
+    int32_t wire;
+    int32_t type;
+});
+
+NPNR_PACKED_STRUCT(struct BelDataPOD {
+    int32_t name;
+    int32_t bel_type;
+
+    // General placement
+    int16_t z;
+    int16_t padding;
+
+    // flags [7..0] are for himbaechel use, [31..8] are for user use
+    uint32_t flags;
+    static constexpr uint32_t FLAG_GLOBAL = 0x01;
+    static constexpr uint32_t FLAG_HIDDEN = 0x02;
+
+    // These are really 64-bits of general data, with some names intended to be vaguely helpful...
+    int32_t site;
+    int32_t checker_idx;
+
+    RelSlice<BelPinPOD> pins;
+    RelPtr<uint8_t> extra_data;
+});
+
+NPNR_PACKED_STRUCT(struct BelPinRefPOD {
+    int32_t bel;
+    int32_t pin;
+});
+
+NPNR_PACKED_STRUCT(struct TileWireDataPOD {
+    int32_t name;
+    int32_t wire_type;
+    int32_t flags; // 32 bits of arbitrary data
+    RelSlice<int32_t> pips_uphill;
+    RelSlice<int32_t> pips_downhill;
+    RelSlice<BelPinRefPOD> bel_pins;
+});
+
+NPNR_PACKED_STRUCT(struct PipDataPOD {
+    int32_t src_wire;
+    int32_t dst_wire;
+
+    uint32_t type;
+    uint32_t flags;
+    int32_t timing_idx;
+});
+
+NPNR_PACKED_STRUCT(struct RelTileWireRefPOD {
+    int16_t dx;
+    int16_t dy;
+    int16_t wire;
+});
+
+NPNR_PACKED_STRUCT(struct NodeShapePOD {
+    RelSlice<RelTileWireRefPOD> tile_wires;
+    int32_t timing_index;
+});
+
+NPNR_PACKED_STRUCT(struct TileTypePOD {
+    int32_t type_name;
+    RelSlice<BelDataPOD> bels;
+    RelSlice<TileWireDataPOD> wires;
+    RelSlice<PipDataPOD> pips;
+    RelPtr<uint8_t> extra_data;
+});
+
+NPNR_PACKED_STRUCT(struct RelNodeRefPOD {
+    // wire is entirely internal to a single tile
+    static constexpr int16_t MODE_TILE_WIRE = 0x7000;
+    // where this is the root {wire, dy} form the node shape index
+    static constexpr int16_t MODE_IS_ROOT = 0x7001;
+    // special cases for the global constant nets
+    static constexpr int16_t MODE_ROW_CONST = 0x7002;
+    static constexpr int16_t MODE_GLB_CONST = 0x7003;
+    // special cases where the user needs to outsmart the deduplication [0x7010, 0x7FFF]
+    static constexpr int16_t MODE_USR_BEGIN = 0x7010;
+    int16_t dx_mode; // relative X-coord, or a special value
+    int16_t dy;      // normally, relative Y-coord
+    uint16_t wire;   // normally, node index in tile (x+dx, y+dy)
+});
+
+NPNR_PACKED_STRUCT(struct TileRoutingShapePOD {
+    RelSlice<RelNodeRefPOD> wire_to_node;
+    int32_t timing_index;
+});
+
+NPNR_PACKED_STRUCT(struct PadInfoPOD {
+    // package pin name
+    int32_t package_pin;
+    // reference to corresponding bel
+    int32_t tile;
+    int32_t bel;
+    // function name
+    int32_t pad_function;
+    // index of pin bank
+    int32_t pad_bank;
+    // extra pad flags
+    uint32_t flags;
+    RelPtr<uint8_t> extra_data;
+});
+
+NPNR_PACKED_STRUCT(struct PackageInfoPOD {
+    int32_t name;
+    RelSlice<PadInfoPOD> pads;
+});
+
+NPNR_PACKED_STRUCT(struct TileInstPOD {
+    int32_t name_prefix;
+    int32_t type;
+    int32_t shape;
+
+    RelPtr<uint8_t> extra_data;
+});
+
+NPNR_PACKED_STRUCT(struct TimingValue {
+    int32_t fast_min;
+    int32_t fast_max;
+    int32_t slow_min;
+    int32_t slow_max;
+});
+
+NPNR_PACKED_STRUCT(struct BelPinTimingPOD {
+    TimingValue in_cap;
+    TimingValue drive_res;
+    TimingValue delay;
+});
+
+NPNR_PACKED_STRUCT(struct PipTimingPOD {
+    TimingValue int_delay;
+    TimingValue in_cap;
+    TimingValue out_res;
+    uint32_t flags;
+    static const uint32_t UNBUFFERED = 0x1;
+});
+
+NPNR_PACKED_STRUCT(struct NodeTimingPOD {
+    TimingValue cap;
+    TimingValue res;
+    TimingValue delay;
+});
+
+NPNR_PACKED_STRUCT(struct CellPinRegArcPOD {
+    int32_t clock;
+    int32_t edge;
+    TimingValue setup;
+    TimingValue hold;
+    TimingValue clk_q;
+});
+
+NPNR_PACKED_STRUCT(struct CellPinCombArcPOD {
+    int32_t input;
+    TimingValue delay;
+});
+
+NPNR_PACKED_STRUCT(struct CellPinTimingPOD {
+    int32_t pin;
+    RelSlice<CellPinCombArcPOD> comb_arcs;
+    RelSlice<CellPinRegArcPOD> reg_arcs;
+});
+
+NPNR_PACKED_STRUCT(struct CellTimingPOD {
+    int32_t type;
+    int32_t variant;
+    RelSlice<CellPinTimingPOD> pins;
+});
+
+NPNR_PACKED_STRUCT(struct SpeedGradePOD {
+    int32_t name;
+    RelSlice<BelPinTimingPOD> bel_pin_classes;
+    RelSlice<PipTimingPOD> pip_classes;
+    RelSlice<NodeTimingPOD> node_classes;
+    RelSlice<CellTimingPOD> cell_types;
+});
+
+NPNR_PACKED_STRUCT(struct ConstIDDataPOD {
+    int32_t known_id_count;
+    RelSlice<RelPtr<char>> bba_ids;
+});
+
+NPNR_PACKED_STRUCT(struct ChipInfoPOD {
+    int32_t magic;
+    int32_t version;
+    int32_t width, height;
+
+    RelPtr<char> uarch;
+    RelPtr<char> name;
+    RelPtr<char> generator;
+
+    RelSlice<TileTypePOD> tile_types;
+    RelSlice<TileInstPOD> tile_insts;
+    RelSlice<NodeShapePOD> node_shapes;
+    RelSlice<TileRoutingShapePOD> tile_shapes;
+
+    RelSlice<PackageInfoPOD> packages;
+    RelSlice<SpeedGradePOD> speed_grades;
+
+    RelPtr<ConstIDDataPOD> extra_constids;
+
+    RelPtr<uint8_t> extra_data;
+});
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake
new file mode 100644
index 0000000000..00524623e2
--- /dev/null
+++ b/himbaechel/family.cmake
@@ -0,0 +1,7 @@
+set(HIMBAECHEL_UARCHES "example")
+foreach(uarch ${HIMBAECHEL_UARCHES})
+    aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES)
+    foreach(target ${family_targets})
+        target_sources(${target} PRIVATE ${HM_UARCH_FILES})
+    endforeach()
+endforeach(uarch)
diff --git a/himbaechel/himbaechel_api.cc b/himbaechel/himbaechel_api.cc
new file mode 100644
index 0000000000..e8d403e3a3
--- /dev/null
+++ b/himbaechel/himbaechel_api.cc
@@ -0,0 +1,105 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-23  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void HimbaechelAPI::init(Context *ctx) { this->ctx = ctx; }
+
+void HimbaechelAPI::init_constids(Arch *arch) {}
+
+std::vector<IdString> HimbaechelAPI::getCellTypes() const
+{
+    std::vector<IdString> result;
+    // TODO
+    return result;
+}
+
+BelBucketId HimbaechelAPI::getBelBucketForBel(BelId bel) const { return ctx->getBelType(bel); }
+
+BelBucketId HimbaechelAPI::getBelBucketForCellType(IdString cell_type) const { return cell_type; }
+
+bool HimbaechelAPI::isValidBelForCellType(IdString cell_type, BelId bel) const
+{
+    return ctx->getBelType(bel) == cell_type;
+}
+
+delay_t HimbaechelAPI::estimateDelay(WireId src, WireId dst) const
+{
+    // TODO: configurable lookahead
+    int sx, sy, dx, dy;
+    tile_xy(ctx->chip_info, src.tile, sx, sy);
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    return 100 * (std::abs(dx - sx) + std::abs(dy - sy) + 2);
+}
+
+delay_t HimbaechelAPI::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
+{
+    Loc src_loc = ctx->getBelLocation(src_bel), dst_loc = ctx->getBelLocation(dst_bel);
+    return 100 * (std::abs(dst_loc.x - src_loc.x) + std::abs(dst_loc.y - src_loc.y));
+}
+
+BoundingBox HimbaechelAPI::getRouteBoundingBox(WireId src, WireId dst) const
+{
+    BoundingBox bb;
+    int sx, sy, dx, dy;
+    tile_xy(ctx->chip_info, src.tile, sx, sy);
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    bb.x0 = std::min(sx, dx);
+    bb.y0 = std::min(sy, dy);
+    bb.x1 = std::max(sx, dx);
+    bb.y1 = std::max(sy, dy);
+    return bb;
+}
+
+HimbaechelArch *HimbaechelArch::list_head;
+HimbaechelArch::HimbaechelArch(const std::string &name) : name(name)
+{
+    list_next = HimbaechelArch::list_head;
+    HimbaechelArch::list_head = this;
+}
+std::string HimbaechelArch::list()
+{
+    std::string result;
+    HimbaechelArch *cursor = HimbaechelArch::list_head;
+    while (cursor) {
+        if (!result.empty())
+            result += ", ";
+        result += cursor->name;
+        cursor = cursor->list_next;
+    }
+    return result;
+}
+std::unique_ptr<HimbaechelAPI> HimbaechelArch::create(const std::string &name,
+                                                      const dict<std::string, std::string> &args)
+{
+    HimbaechelArch *cursor = HimbaechelArch::list_head;
+    while (cursor) {
+        if (cursor->name != name) {
+            cursor = cursor->list_next;
+            continue;
+        }
+        return cursor->create(args);
+    }
+    return {};
+}
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
new file mode 100644
index 0000000000..be62be2af8
--- /dev/null
+++ b/himbaechel/himbaechel_api.h
@@ -0,0 +1,127 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-23  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_API_H
+#define HIMBAECHEL_API_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Himbaechel -- a series of bigger arches
+
+Himbaechel extends on the existing Viaduct API in nextpnr-generic for smaller, lower-impact architectures by a
+deduplicated BBA chipdb format as well as API hooks more suited to such size and complexity devices.
+
+It allows an arch to programmatically build a set of bels (placement locations) and a routing graph at compile time into
+a space-efficient (both disk and runtime RAM) deduplicated database with fast lookups; and then hook into nextpnr's flow
+and validity checking rules at runtime with custom C++ code.
+
+To create a Himbaechel 'uarch', the following are required:
+ - an implementation of HimbaechelAPI. This should define things like rules for how LUTs and FFs can be placed together
+in a SLICE.
+ - "ahead-of-time" Python scripts to programmatically build a routing graph for the device as well as list of placement
+locations, in a way that will become space-efficient
+ - an instance of a struct deriving from HimbaechelArch - this is how the uarch is discovered. Override create(args) to
+create an instance of your HimabaechelAPI implementation.
+ - these should be within C++ files in a new subfolder of 'himbaechel/uarches/'. Add the name of this subfolder to the
+list of HIMBAECHEL_UARCHES in family.cmake if building in-tree.
+
+For an example of how these pieces fit together; see 'himbaechel/uarches/example' which implements a small synthetic
+architecture using this framework.
+
+*/
+
+struct Arch;
+struct Context;
+
+struct PlacerHeapCfg;
+
+struct HimbaechelAPI
+{
+    virtual void init(Context *ctx);
+    // If constids are being used, this is used to set them up early before loading the db blob
+    virtual void init_constids(Arch *arch);
+    Context *ctx;
+    bool with_gui = false;
+
+    // --- Bel functions ---
+    // Called when a bel is placed/unplaced (with cell=nullptr for a unbind)
+    virtual void notifyBelChange(BelId bel, CellInfo *cell) {}
+    // This only needs to return false if a bel is disabled for a microarch-specific reason and not just because it's
+    // bound (which the base generic will deal with)
+    virtual bool checkBelAvail(BelId bel) const { return true; }
+    // Mirror the ArchAPI functions - see archapi.md
+    virtual std::vector<IdString> getCellTypes() const;
+    virtual BelBucketId getBelBucketForBel(BelId bel) const;
+    virtual BelBucketId getBelBucketForCellType(IdString cell_type) const;
+    virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const;
+    virtual bool isBelLocationValid(BelId bel, bool explain_invalid = false) const { return true; }
+
+    // --- Wire and pip functions ---
+    // Called when a wire/pip is placed/unplaced (with net=nullptr for a unbind)
+    virtual void notifyWireChange(WireId wire, NetInfo *net) {}
+    virtual void notifyPipChange(PipId pip, NetInfo *net) {}
+    // These only need to return false if a wire/pip is disabled for a microarch-specific reason and not just because
+    // it's bound (which the base arch will deal with)
+    virtual bool checkWireAvail(WireId wire) const { return true; }
+    virtual bool checkPipAvail(PipId pip) const { return true; }
+    virtual bool checkPipAvailForNet(PipId pip, const NetInfo *net) const { return checkPipAvail(pip); };
+
+    // --- Route lookahead ---
+    virtual delay_t estimateDelay(WireId src, WireId dst) const;
+    virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const;
+    virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const;
+
+    // Cell->bel pin mapping
+    virtual bool map_cell_bel_pins(CellInfo *cell) const { return false; }
+
+    // --- Flow hooks ---
+    virtual void pack(){}; // replaces the pack function
+    // Called before and after main placement and routing
+    virtual void prePlace(){};
+    virtual void postPlace(){};
+    virtual void preRoute(){};
+    virtual void postRoute(){};
+
+    // For custom placer configuration
+    virtual void configurePlacerHeap(PlacerHeapCfg &cfg){};
+
+    virtual ~HimbaechelAPI(){};
+};
+
+struct HimbaechelArch
+{
+    static HimbaechelArch *list_head;
+    HimbaechelArch *list_next = nullptr;
+
+    std::string name;
+    HimbaechelArch(const std::string &name);
+    ~HimbaechelArch(){};
+    virtual std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args) = 0;
+
+    static std::string list();
+    static std::unique_ptr<HimbaechelAPI> create(const std::string &name, const dict<std::string, std::string> &args);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/himbaechel_constids.h b/himbaechel/himbaechel_constids.h
new file mode 100644
index 0000000000..3a5ec2548f
--- /dev/null
+++ b/himbaechel/himbaechel_constids.h
@@ -0,0 +1,74 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_CONSTIDS_H
+#define HIMBAECHEL_CONSTIDS_H
+
+/*
+This enables use of 'constids' similar to a 'true' nextpnr arch in a HIMBAECHEL uarch.
+To use:
+    - create a 'constids.inc' file in your uarch folder containing one ID per line; inside X( )
+    - set the HIMBAECHEL_CONSTIDS macro to the path to this file relative to the generic arch base
+    - in your main file; also define GEN_INIT_CONSTIDS to create init_uarch_constids(Context*) which you should call in
+init
+    - include this file
+*/
+
+#include "nextpnr_namespaces.h"
+
+#ifdef HIMBAECHEL_MAIN
+#include "idstring.h"
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+#ifndef Q_MOC_RUN
+enum ConstIds
+{
+    ID_NONE
+#define X(t) , ID_##t
+#include HIMBAECHEL_CONSTIDS
+#undef X
+    ,
+};
+
+#define X(t) static constexpr auto id_##t = IdString(ID_##t);
+#include HIMBAECHEL_CONSTIDS
+#undef X
+#endif
+
+#ifdef GEN_INIT_CONSTIDS
+
+void init_uarch_constids(Arch *arch)
+{
+#define X(t) IdString::initialize_add(arch, #t, ID_##t);
+
+#include HIMBAECHEL_CONSTIDS
+
+#undef X
+}
+
+#endif
+
+} // namespace
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/himbaechel_dbgen/bba.py b/himbaechel/himbaechel_dbgen/bba.py
new file mode 100644
index 0000000000..de9dca31db
--- /dev/null
+++ b/himbaechel/himbaechel_dbgen/bba.py
@@ -0,0 +1,26 @@
+class BBAWriter:
+	def __init__(self, f):
+		self.f = f
+	def pre(self, s):
+		print(f"pre {s}", file=self.f)
+	def post(self, s):
+		print(f"post {s}", file=self.f)
+	def push(self, s):
+		print(f"push {s}", file=self.f)
+	def ref(self, r, comment=""):
+		print(f"ref {r} {comment}", file=self.f)
+	def slice(self, r, size, comment=""):
+		print(f"ref {r} {comment}", file=self.f)
+		print(f"u32 {size}", file=self.f)
+	def str(self, s, comment=""):
+		print(f"str |{s}| {comment}", file=self.f)
+	def label(self, s):
+		print(f"label {s}", file=self.f)
+	def u8(self, n, comment=""):
+		print(f"u8 {n} {comment}", file=self.f)
+	def u16(self, n, comment=""):
+		print(f"u16 {n} {comment}", file=self.f)
+	def u32(self, n, comment=""):
+		print(f"u32 {n} {comment}", file=self.f)
+	def pop(self):
+		print("pop", file=self.f)
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
new file mode 100644
index 0000000000..c3e4a8ae0d
--- /dev/null
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -0,0 +1,519 @@
+from dataclasses import dataclass, field
+from .bba import BBAWriter
+from enum import Enum
+from typing import Optional
+import abc
+import struct, hashlib
+
+"""
+This provides a semi-flattened routing graph that is built into a deduplicated one.
+
+There are two key elements:
+ - Tile Types:
+      these represent a unique kind of grid location in terms of its contents:
+       - bels (logic functionality like LUTs, FFs, IOs, IP, etc)
+       - internal wires (excluding connectivity to other tiles)
+       - pips that switch internal wires
+ - Nodes
+      these merge tile-internal wires across wires to create inter-tile connectivity
+      so, for example, a length-4 wire might connect (x, y, "E4AI") and (x+3, y, "E4AO")
+"""
+
+class BBAStruct(abc.ABC):
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        pass
+
+@dataclass(eq=True, frozen=True)
+class IdString:
+    index: int = 0
+
+class StringPool:
+    def __init__(self):
+        self.strs = {"": 0}
+        self.known_id_count = 1
+
+    def read_constids(self, file: str):
+        idx = 1
+        with open(file, "r") as f:
+            for line in f:
+                l = line.strip()
+                if not l.startswith("X("):
+                    continue
+                l = l[2:]
+                assert l.endswith(")"), l
+                l = l[:-1].strip()
+                i = self.id(l)
+                assert i.index == idx, (i, idx, l)
+                idx += 1
+        self.known_id_count = idx
+
+    def id(self, val: str):
+        if val in self.strs:
+            return IdString(self.strs[val])
+        else:
+            idx = len(self.strs)
+            self.strs[val] = idx
+            return IdString(idx)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_strs")
+        for s, idx in sorted(self.strs.items(), key=lambda x: x[1]): # sort by index
+            if idx < self.known_id_count:
+                continue
+            bba.str(s)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.known_id_count)
+        bba.slice(f"{context}_strs", len(self.strs) - self.known_id_count)
+
+@dataclass
+class PinType(Enum):
+    INPUT = 0
+    OUTPUT = 1
+    INOUT = 2
+
+@dataclass
+class BelPin(BBAStruct):
+    name: IdString
+    wire: int
+    dir: PinType
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u32(self.wire)
+        bba.u32(self.dir.value)
+
+BEL_FLAG_GLOBAL = 0x01
+BEL_FLAG_HIDDEN = 0x02
+
+@dataclass
+class BelData(BBAStruct):
+    index: int
+    name: IdString
+    bel_type: IdString
+    z: int
+
+    flags: int = 0
+    site: int = 0
+    checker_idx: int = 0
+
+    pins: list[BelPin] = field(default_factory=list)
+    extra_data: object = None
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        # sort pins for fast binary search lookups
+        self.pins.sort(key=lambda p: p.name.index)
+        # write pins array
+        bba.label(f"{context}_pins")
+        for i, pin in enumerate(self.pins):
+            pin.serialise(f"{context}_pin{i}", bba)
+        # extra data (optional)
+        if self.extra_data is not None:
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u32(self.bel_type.index)
+        bba.u16(self.z)
+        bba.u16(0)
+        bba.u32(self.flags)
+        bba.u32(self.site)
+        bba.u32(self.checker_idx)
+        bba.slice(f"{context}_pins", len(self.pins))
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
+
+@dataclass
+class BelPinRef(BBAStruct):
+    bel: int
+    pin: IdString
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.bel)
+        bba.u32(self.pin.index)
+
+@dataclass
+class TileWireData:
+    index: int
+    name: IdString
+    wire_type: IdString
+    flags: int = 0
+
+    # not serialised, but used to build the global constant networks
+    const_val: int = -1
+
+    # these crossreferences will be updated by finalise(), no need to manually update
+    pips_uphill: list[int] = field(default_factory=list)
+    pips_downhill: list[int] = field(default_factory=list)
+    bel_pins: list[BelPinRef] = field(default_factory=list)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_pips_uh")
+        for pip_idx in self.pips_uphill:
+            bba.u32(pip_idx)
+        bba.label(f"{context}_pips_dh")
+        for pip_idx in self.pips_downhill:
+            bba.u32(pip_idx)
+        bba.label(f"{context}_bel_pins")
+        for i, bel_pin in enumerate(self.bel_pins):
+            bel_pin.serialise(f"{context}_bp{i}", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u32(self.wire_type.index)
+        bba.u32(self.flags)
+        bba.slice(f"{context}_pips_uh", len(self.pips_uphill))
+        bba.slice(f"{context}_pips_dh", len(self.pips_downhill))
+        bba.slice(f"{context}_bel_pins", len(self.bel_pins))
+
+@dataclass
+class PipData(BBAStruct):
+    index: int
+    src_wire: int
+    dst_wire: int
+    pip_type: IdString = field(default_factory=IdString)
+    flags: int = 0
+    timing_idx: int = -1
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.src_wire)
+        bba.u32(self.dst_wire)
+        bba.u32(self.pip_type.index)
+        bba.u32(self.flags)
+        bba.u32(self.timing_idx)
+
+@dataclass
+class TileType(BBAStruct):
+    strs: StringPool
+    type_name: IdString
+    bels: list[BelData] = field(default_factory=list)
+    pips: list[PipData] = field(default_factory=list)
+    wires: list[TileWireData] = field(default_factory=list)
+
+    _wire2idx: dict[IdString, int] = field(default_factory=dict)
+
+    extra_data: object = None
+
+    def create_bel(self, name: str, type: str, z: int):
+        # Create a new bel of a given name, type and z (index within the tile) in the tile type
+        bel = BelData(index=len(self.bels),
+            name=self.strs.id(name),
+            bel_type=self.strs.id(type),
+            z=z)
+        self.bels.append(bel)
+        return bel
+    def add_bel_pin(self, bel: BelData, pin: str, wire: str, dir: PinType):
+        # Add a pin with associated wire to a bel. The wire should exist already.
+        pin_id = self.strs.id(pin)
+        wire_idx = self._wire2idx[self.strs.id(wire)]
+        bel.pins.append(BelPin(pin_id, wire_idx, dir))
+        self.wires[wire_idx].bel_pins.append(BelPinRef(bel.index, pin_id))
+
+    def create_wire(self, name: str, type: str=""):
+        # Create a new tile wire of a given name and type (optional) in the tile type
+        wire = TileWireData(index=len(self.wires),
+            name=self.strs.id(name),
+            wire_type=self.strs.id(type))
+        self._wire2idx[wire.name] = wire.index
+        self.wires.append(wire)
+        return wire
+    def create_pip(self, src: str, dst: str):
+        # Create a pip between two tile wires in the tile type. Both wires should exist already.
+        src_idx = self._wire2idx[self.strs.id(src)]
+        dst_idx = self._wire2idx[self.strs.id(dst)]
+        pip = PipData(index=len(self.pips), src_wire=src_idx, dst_wire=dst_idx)
+        self.wires[src_idx].pips_downhill.append(pip.index)
+        self.wires[dst_idx].pips_uphill.append(pip.index)
+        self.pips.append(pip)
+        return pip
+    def has_wire(self, wire: str):
+        # Check if a wire has already been created
+        return self.strs.id(wire) in self._wire2idx
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        # list children of members
+        for i, bel in enumerate(self.bels):
+            bel.serialise_lists(f"{context}_bel{i}", bba)
+        for i, wire in enumerate(self.wires):
+            wire.serialise_lists(f"{context}_wire{i}", bba)
+        for i, pip in enumerate(self.pips):
+            pip.serialise_lists(f"{context}_pip{i}", bba)
+        # lists of members
+        bba.label(f"{context}_bels")
+        for i, bel in enumerate(self.bels):
+            bel.serialise(f"{context}_bel{i}", bba)
+        bba.label(f"{context}_wires")
+        for i, wire in enumerate(self.wires):
+            wire.serialise(f"{context}_wire{i}", bba)
+        bba.label(f"{context}_pips")
+        for i, pip in enumerate(self.pips):
+            pip.serialise(f"{context}_pip{i}", bba)
+        # extra data (optional)
+        if self.extra_data is not None:
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.type_name.index)
+        bba.slice(f"{context}_bels", len(self.bels))
+        bba.slice(f"{context}_wires", len(self.wires))
+        bba.slice(f"{context}_pips", len(self.pips))
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
+
+# Pre deduplication (nodes flattened, absolute coords)
+@dataclass
+class NodeWire:
+    x: int
+    y: int
+    wire: str
+
+# Post deduplication (node shapes merged, relative coords)
+@dataclass
+class TileWireRef(BBAStruct):
+    dx: int
+    dy: int
+    wire: int
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u16(self.dx)
+        bba.u16(self.dy)
+        bba.u16(self.wire)
+
+@dataclass
+class NodeShape(BBAStruct):
+    wires: list[TileWireRef] = field(default_factory=list)
+    def key(self):
+        m = hashlib.sha1()
+        for wire in self.wires:
+            m.update(wire.dx.to_bytes(2, 'little', signed=True))
+            m.update(wire.dy.to_bytes(2, 'little', signed=True))
+            m.update(wire.wire.to_bytes(2, 'little'))
+        return m.digest()
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_wires")
+        for i, w in enumerate(self.wires):
+            w.serialise(f"{context}_w{i}", bba)
+        if len(self.wires) % 2 != 0:
+            bba.u16(0) # alignment
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.slice(f"{context}_wires", len(self.wires))
+        bba.u32(-1) # timing index (not yet used)
+
+MODE_TILE_WIRE = 0x7000
+MODE_IS_ROOT = 0x7001
+MODE_ROW_CONST = 0x7002
+MODE_GLB_CONST = 0x7003
+
+@dataclass
+class RelNodeRef(BBAStruct):
+    dx_mode: int = MODE_TILE_WIRE
+    dy: int = 0
+    wire: int = 0
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u16(self.dx_mode)
+        bba.u16(self.dy)
+        bba.u16(self.wire)
+
+@dataclass
+class TileRoutingShape(BBAStruct):
+    wire_to_node: list[RelNodeRef] = field(default_factory=list)
+    def key(self):
+        m = hashlib.sha1()
+        for wire in self.wire_to_node:
+            m.update(wire.dx_mode.to_bytes(2, 'little', signed=True))
+            m.update(wire.dy.to_bytes(2, 'little', signed=(wire.dy < 0)))
+            m.update(wire.wire.to_bytes(2, 'little', signed=True))
+        return m.digest()
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_w2n")
+        for i, w in enumerate(self.wire_to_node):
+            w.serialise(f"{context}_w{i}", bba)
+        if len(self.wire_to_node) % 2 != 0:
+            bba.u16(0) # alignment
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.slice(f"{context}_w2n", len(self.wire_to_node))
+        bba.u32(-1) # timing index
+
+@dataclass
+class TileInst(BBAStruct):
+    x: int
+    y: int
+    type_idx: Optional[int] = None
+    name_prefix: IdString = field(default_factory=IdString)
+    loc_type: int = 0
+    shape: TileRoutingShape = field(default_factory=TileRoutingShape)
+    shape_idx: int = -1
+    extra_data: object = None
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name_prefix.index)
+        bba.u32(self.type_idx)
+        bba.u32(self.shape_idx)
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
+class Chip:
+    def __init__(self, uarch: str, name: str, width: int, height: int):
+        self.strs = StringPool()
+        self.uarch = uarch
+        self.name = name
+        self.width = width
+        self.height = height
+        self.tile_types = []
+        self.tiles = [[TileInst(x, y) for x in range(width)] for y in range(height)]
+        self.tile_type_idx = dict()
+        self.node_shapes = []
+        self.node_shape_idx = dict()
+        self.tile_shapes = []
+        self.tile_shapes_idx = dict()
+        self.extra_data = None
+    def create_tile_type(self, name: str):
+        tt = TileType(self.strs, self.strs.id(name))
+        self.tile_type_idx[name] = len(self.tile_types)
+        self.tile_types.append(tt)
+        return tt
+    def set_tile_type(self, x: int, y: int, type: str):
+        self.tiles[y][x].type_idx = self.tile_type_idx[type]
+    def tile_type_at(self, x: int, y: int):
+        assert self.tiles[y][x].type_idx is not None, f"tile type at ({x}, {y}) must be set"
+        return self.tile_types[self.tiles[y][x].type_idx]
+    def add_node(self, wires: list[NodeWire]):
+        # add a node - joining between multiple tile wires into a single connection (from nextpnr's point of view)
+        # all the tile wires must exist, and the tile types must be set, first
+        x0 = wires[0].x
+        y0 = wires[0].y
+        # compute node shape
+        shape = NodeShape()
+        for w in wires:
+            wire_id = w.wire if w.wire is IdString else self.strs.id(w.wire)
+            shape.wires.append(TileWireRef(
+                dx=w.x-x0, dy=w.y-y0,
+                wire=self.tile_type_at(w.x, w.y)._wire2idx[wire_id]
+            ))
+        # deduplicate node shapes
+        key = shape.key()
+        if key in self.node_shape_idx:
+            shape_idx = self.node_shape_idx[key]
+        else:
+            shape_idx = len(self.node_shapes)
+            self.node_shape_idx[key] = shape_idx
+            self.node_shapes.append(shape)
+        # update tile wire to node ref
+        for i, w in enumerate(wires):
+            inst = self.tiles[w.y][w.x]
+            wire_idx = shape.wires[i].wire
+            # make sure there's actually enough space; first
+            if wire_idx >= len(inst.shape.wire_to_node):
+                inst.shape.wire_to_node += [RelNodeRef() for k in range(len(inst.shape.wire_to_node), wire_idx+1)]
+            if i == 0:
+                # root of the node. we don't need to back-reference anything because the node is based here
+                # so we re-use the structure to store the index of the node shape, instead
+                assert inst.shape.wire_to_node[wire_idx].dx_mode == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
+                inst.shape.wire_to_node[wire_idx] = RelNodeRef(MODE_IS_ROOT, (shape_idx & 0xFFFF), ((shape_idx >> 16) & 0xFFFF))
+            else:
+                # back-reference to the root of the node
+                dx = x0 - w.x
+                dy = y0 - w.y
+                assert dx < MODE_TILE_WIRE, "dx range causes overlap with magic values!"
+                assert inst.shape.wire_to_node[wire_idx].dx_mode == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
+                inst.shape.wire_to_node[wire_idx] = RelNodeRef(dx, dy, shape.wires[0].wire)
+
+    def flatten_tile_shapes(self):
+        for row in self.tiles:
+            for tile in row:
+                key = tile.shape.key()
+                if key in self.tile_shapes_idx:
+                    tile.shape_idx = self.tile_shapes_idx[key]
+                else:
+                    tile.shape_idx = len(self.tile_shapes)
+                    self.tile_shapes.append(tile.shape)
+                    self.tile_shapes_idx[key] = tile.shape_idx
+        print(f"{len(self.tile_shapes)} unique tile routing shapes")
+
+    def serialise(self, bba: BBAWriter):
+        self.flatten_tile_shapes()
+        # TODO: preface, etc
+        # Lists that make up the database
+        for i, tt in enumerate(self.tile_types):
+            tt.serialise_lists(f"tt{i}", bba)
+        for i, shp in enumerate(self.node_shapes):
+            shp.serialise_lists(f"nshp{i}", bba)
+        for i, tsh in enumerate(self.tile_shapes):
+            tsh.serialise_lists(f"tshp{i}", bba)
+        for y, row in enumerate(self.tiles):
+            for x, tinst in enumerate(row):
+                tinst.serialise_lists(f"tinst_{x}_{y}", bba)
+
+        self.strs.serialise_lists(f"constids", bba)
+
+        bba.label(f"tile_types")
+        for i, tt in enumerate(self.tile_types):
+            tt.serialise(f"tt{i}", bba)
+        bba.label(f"node_shapes")
+        for i, shp in enumerate(self.node_shapes):
+            shp.serialise(f"nshp{i}", bba)
+        bba.label(f"tile_shapes")
+        for i, tsh in enumerate(self.tile_shapes):
+            tsh.serialise(f"tshp{i}", bba)
+        bba.label(f"tile_insts")
+        for y, row in enumerate(self.tiles):
+            for x, tinst in enumerate(row):
+                tinst.serialise(f"tinst_{x}_{y}", bba)
+
+        bba.label(f"constids")
+        self.strs.serialise(f"constids", bba)
+
+        bba.label("chip_info")
+        bba.u32(0x00ca7ca7) # magic
+        bba.u32(1) # version (TODO)
+        bba.u32(self.width)
+        bba.u32(self.height)
+
+        bba.str(self.uarch)
+        bba.str(self.name)
+        bba.str("python_dbgen") # generator
+
+        bba.slice("tile_types", len(self.tile_types))
+        bba.slice("tile_insts", self.width*self.height)
+        bba.slice("node_shapes", len(self.node_shapes))
+        bba.slice("tile_shapes", len(self.tile_shapes))
+        # packages: not yet used
+        bba.u32(0)
+        bba.u32(0)
+        # speed grades: not yet used
+        bba.u32(0)
+        bba.u32(0)
+        # db-defined constids
+        bba.ref("constids")
+        # extra data: not yet used
+        bba.u32(0)
+
+    def write_bba(self, filename):
+        with open(filename, "w") as f:
+            bba = BBAWriter(f)
+            bba.pre('#include \"nextpnr.h\"')
+            bba.pre('NEXTPNR_NAMESPACE_BEGIN')
+            bba.post('NEXTPNR_NAMESPACE_END')
+            bba.push('chipdb_blob')
+            bba.ref('chip_info')
+            self.serialise(bba)
+            bba.pop()
diff --git a/himbaechel/himbaechel_helpers.cc b/himbaechel/himbaechel_helpers.cc
new file mode 100644
index 0000000000..4ce478bf86
--- /dev/null
+++ b/himbaechel/himbaechel_helpers.cc
@@ -0,0 +1,141 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "himbaechel_helpers.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void HimbaechelHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
+{
+    std::vector<IdString> to_remove;
+    for (auto &cell : ctx->cells) {
+        auto &ci = *cell.second;
+        if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
+            continue;
+        NetInfo *i = ci.getPort(ctx->id("I"));
+        if (i && i->driver.cell) {
+            if (!top_ports.count(CellTypePort(i->driver)))
+                log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
+                          ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+        }
+        NetInfo *o = ci.getPort(ctx->id("O"));
+        if (o) {
+            for (auto &usr : o->users) {
+                if (!top_ports.count(CellTypePort(usr)))
+                    log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
+                              ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
+            }
+        }
+        ci.disconnectPort(ctx->id("I"));
+        ci.disconnectPort(ctx->id("O"));
+        to_remove.push_back(ci.name);
+    }
+    for (IdString cell_name : to_remove)
+        ctx->cells.erase(cell_name);
+}
+
+int HimbaechelHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports,
+                                            int delta_z, bool allow_fanout)
+{
+    int constrained = 0;
+    for (auto &cell : ctx->cells) {
+        auto &ci = *cell.second;
+        if (ci.cluster != ClusterId())
+            continue; // don't constrain already-constrained cells
+        bool done = false;
+        for (auto &port : ci.ports) {
+            // look for starting source ports
+            if (port.second.type != PORT_OUT || !port.second.net)
+                continue;
+            if (!src_ports.count(CellTypePort(ci.type, port.first)))
+                continue;
+            if (!allow_fanout && port.second.net->users.entries() > 1)
+                continue;
+            for (auto &usr : port.second.net->users) {
+                if (!sink_ports.count(CellTypePort(usr)))
+                    continue;
+                if (usr.cell->cluster != ClusterId())
+                    continue;
+                // Add the constraint
+                ci.cluster = ci.name;
+                ci.constr_abs_z = false;
+                ci.constr_children.push_back(usr.cell);
+                usr.cell->cluster = ci.name;
+                usr.cell->constr_x = 0;
+                usr.cell->constr_y = 0;
+                usr.cell->constr_z = delta_z;
+                usr.cell->constr_abs_z = false;
+                ++constrained;
+                done = true;
+                break;
+            }
+            if (done)
+                break;
+        }
+    }
+    return constrained;
+}
+
+void HimbaechelHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+                                          const dict<IdString, Property> &vcc_params,
+                                          const dict<IdString, Property> &gnd_params)
+{
+    CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), vcc_driver.cell_type);
+    vcc_drv->addOutput(vcc_driver.port);
+    for (auto &p : vcc_params)
+        vcc_drv->params[p.first] = p.second;
+
+    CellInfo *gnd_drv = ctx->createCell(ctx->id("$PACKER_GND_DRV"), gnd_driver.cell_type);
+    gnd_drv->addOutput(gnd_driver.port);
+    for (auto &p : gnd_params)
+        gnd_drv->params[p.first] = p.second;
+
+    NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC"));
+    NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND"));
+
+    vcc_drv->connectPort(vcc_driver.port, vcc_net);
+    gnd_drv->connectPort(gnd_driver.port, gnd_net);
+
+    std::vector<IdString> trim_cells;
+    std::vector<IdString> trim_nets;
+    for (auto &net : ctx->nets) {
+        auto &ni = *net.second;
+        if (!ni.driver.cell)
+            continue;
+        if (ni.driver.cell->type != ctx->id("GND") && ni.driver.cell->type != ctx->id("VCC"))
+            continue;
+        NetInfo *replace = (ni.driver.cell->type == ctx->id("VCC")) ? vcc_net : gnd_net;
+        for (auto &usr : ni.users) {
+            usr.cell->ports.at(usr.port).net = replace;
+            usr.cell->ports.at(usr.port).user_idx = replace->users.add(usr);
+        }
+        trim_cells.push_back(ni.driver.cell->name);
+        trim_nets.push_back(ni.name);
+    }
+    for (IdString cell_name : trim_cells)
+        ctx->cells.erase(cell_name);
+    for (IdString net_name : trim_nets)
+        ctx->nets.erase(net_name);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/himbaechel_helpers.h b/himbaechel/himbaechel_helpers.h
new file mode 100644
index 0000000000..b2a41b656c
--- /dev/null
+++ b/himbaechel/himbaechel_helpers.h
@@ -0,0 +1,75 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_HELPERS_H
+#define HIMBAECHEL_HELPERS_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Himbächel -- a series of small arches
+
+See himbaechel_api.h for more background.
+
+himbaechel_helpers provides some features for building up arches using the himbächel API
+*/
+
+// Used to configure various generic pack functions
+struct CellTypePort
+{
+    CellTypePort() : cell_type(), port(){};
+    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port){};
+    explicit CellTypePort(const PortRef &net_port)
+            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port){};
+    inline bool operator==(const CellTypePort &other) const
+    {
+        return cell_type == other.cell_type && port == other.port;
+    }
+    inline bool operator!=(const CellTypePort &other) const
+    {
+        return cell_type != other.cell_type || port != other.port;
+    }
+    inline unsigned hash() const { return mkhash(cell_type.hash(), port.hash()); }
+    IdString cell_type, port;
+};
+
+struct HimbaechelHelpers
+{
+    HimbaechelHelpers(){};
+    Context *ctx;
+    void init(Context *ctx) { this->ctx = ctx; }
+    // Common packing functions
+    // Remove nextpnr-inserted IO buffers; where IO buffer insertion is done in synthesis
+    // expects a set of top-level port types
+    void remove_nextpnr_iobs(const pool<CellTypePort> &top_ports);
+    // Constrain cells with certain port connection patterns together with a fixed z-offset
+    int constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports, int delta_z,
+                             bool allow_fanout = true);
+    // Replace constants with given driving cells
+    void replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+                           const dict<IdString, Property> &vcc_params = {},
+                           const dict<IdString, Property> &gnd_params = {});
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/main.cc b/himbaechel/main.cc
new file mode 100644
index 0000000000..64c2c0f3f8
--- /dev/null
+++ b/himbaechel/main.cc
@@ -0,0 +1,97 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifdef MAIN_EXECUTABLE
+
+#include <fstream>
+#include "command.h"
+#include "design_utils.h"
+#include "log.h"
+#include "timing.h"
+
+USING_NEXTPNR_NAMESPACE
+
+class HimbaechelCommandHandler : public CommandHandler
+{
+  public:
+    HimbaechelCommandHandler(int argc, char **argv);
+    virtual ~HimbaechelCommandHandler(){};
+    std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
+    void setupArchContext(Context *ctx) override{};
+    void customBitstream(Context *ctx) override;
+
+  protected:
+    po::options_description getArchOptions() override;
+};
+
+HimbaechelCommandHandler::HimbaechelCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
+
+po::options_description HimbaechelCommandHandler::getArchOptions()
+{
+    std::string all_uarches = HimbaechelArch::list();
+    std::string uarch_help = stringf("himbächel micro-arch to use (available: %s)", all_uarches.c_str());
+    po::options_description specific("Architecture specific options");
+    specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
+    specific.add_options()("chipdb", po::value<std::string>(), "path to chip database file");
+    specific.add_options()("vopt,o", po::value<std::vector<std::string>>(), "options to pass to the himbächel uarch");
+
+    return specific;
+}
+
+void HimbaechelCommandHandler::customBitstream(Context *ctx) {}
+
+std::unique_ptr<Context> HimbaechelCommandHandler::createContext(dict<std::string, Property> &values)
+{
+    ArchArgs chipArgs;
+    if (values.find("arch.name") != values.end()) {
+        std::string arch_name = values["arch.name"].as_string();
+        if (arch_name != "himbaechel")
+            log_error("Unsupported architecture '%s'.\n", arch_name.c_str());
+    }
+    if (!vm.count("uarch"))
+        log_error("uarch must be specified\n");
+    if (!vm.count("chipdb"))
+        log_error("chip database path must be specified.\n");
+    chipArgs.uarch = vm["uarch"].as<std::string>();
+    chipArgs.chipdb = vm["chipdb"].as<std::string>();
+    if (vm.count("vopt")) {
+        std::vector<std::string> options = vm["vopt"].as<std::vector<std::string>>();
+        for (const auto &opt : options) {
+            size_t epos = opt.find('=');
+            if (epos == std::string::npos)
+                chipArgs.options[opt] = "";
+            else
+                chipArgs.options[opt.substr(0, epos)] = opt.substr(epos + 1);
+        }
+    }
+    auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
+    if (vm.count("gui"))
+        ctx->uarch->with_gui = true;
+    ctx->uarch->init(ctx.get());
+    ctx->late_init();
+    return ctx;
+}
+
+int main(int argc, char *argv[])
+{
+    HimbaechelCommandHandler handler(argc, argv);
+    return handler.exec();
+}
+
+#endif
diff --git a/himbaechel/uarch/example/blinky.v b/himbaechel/uarch/example/blinky.v
new file mode 100644
index 0000000000..e26c2fae56
--- /dev/null
+++ b/himbaechel/uarch/example/blinky.v
@@ -0,0 +1,16 @@
+module top(input rst, output reg [7:0] leds);
+
+wire clk;
+
+(* BEL="X1Y0/IO0" *) INBUF ib_i (.O(clk));
+
+reg [7:0] ctr;
+always @(posedge clk)
+	if (rst)
+		ctr <= 8'h00;
+	else
+		ctr <= ctr + 1'b1;
+
+assign leds = ctr;
+
+endmodule
diff --git a/himbaechel/uarch/example/constids.inc b/himbaechel/uarch/example/constids.inc
new file mode 100644
index 0000000000..b40d5be8a0
--- /dev/null
+++ b/himbaechel/uarch/example/constids.inc
@@ -0,0 +1,14 @@
+X(LUT4)
+X(DFF)
+X(CLK)
+X(D)
+X(F)
+X(Q)
+X(INBUF)
+X(OUTBUF)
+X(I)
+X(EN)
+X(O)
+X(IOB)
+X(PAD)
+X(INIT)
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
new file mode 100644
index 0000000000..5f5d1087dc
--- /dev/null
+++ b/himbaechel/uarch/example/example.cc
@@ -0,0 +1,144 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "himbaechel_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/example/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct ExampleImpl : HimbaechelAPI
+{
+
+    static constexpr int K = 4;
+
+    ~ExampleImpl(){};
+    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init(Context *ctx) override
+    {
+        h.init(ctx);
+        HimbaechelAPI::init(ctx);
+    }
+
+    void prePlace() override { assign_cell_info(); }
+
+    void pack() override
+    {
+        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_INBUF, id_PAD),
+                CellTypePort(id_OUTBUF, id_PAD),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+        // Replace constants with LUTs
+        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
+        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
+        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+        // Constrain directly connected LUTs and FFs together to use dedicated resources
+        int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        log_info("Constrained %d LUTFF pairs.\n", lutffs);
+    }
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
+    {
+        Loc l = ctx->getBelLocation(bel);
+        if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
+            return slice_valid(l.x, l.y, l.z / 2);
+        } else {
+            return true;
+        }
+    }
+
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override
+    {
+        if (cell_type.in(id_INBUF, id_OUTBUF))
+            return id_IOB;
+        return cell_type;
+    }
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        IdString bel_type = ctx->getBelType(bel);
+        if (bel_type == id_IOB)
+            return cell_type.in(id_INBUF, id_OUTBUF);
+        else
+            return (bel_type == cell_type);
+    }
+
+  private:
+    HimbaechelHelpers h;
+
+    // Validity checking
+    struct ExampleCellInfo
+    {
+        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+        bool lut_i3_used = false;
+    };
+    std::vector<ExampleCellInfo> fast_cell_info;
+    void assign_cell_info()
+    {
+        fast_cell_info.resize(ctx->cells.size());
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto &fc = fast_cell_info.at(ci->flat_index);
+            if (ci->type == id_LUT4) {
+                fc.lut_f = ci->getPort(id_F);
+                fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr);
+            } else if (ci->type == id_DFF) {
+                fc.ff_d = ci->getPort(id_D);
+            }
+        }
+    }
+    bool slice_valid(int x, int y, int z) const
+    {
+        const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+        const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+        if (!lut || !ff)
+            return true; // always valid if only LUT or FF used
+        const auto &lut_data = fast_cell_info.at(lut->flat_index);
+        const auto &ff_data = fast_cell_info.at(ff->flat_index);
+        // In our example arch; the FF D can either be driven from LUT F or LUT I3
+        // so either; FF D must equal LUT F or LUT I3 must be unused
+        if (ff_data.ff_d == lut_data.lut_f)
+            return true;
+        if (lut_data.lut_i3_used)
+            return false;
+        return true;
+    }
+};
+
+struct ExampleArch : HimbaechelArch
+{
+    ExampleArch() : HimbaechelArch("example"){};
+    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<ExampleImpl>();
+    }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
new file mode 100644
index 0000000000..026c2551aa
--- /dev/null
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -0,0 +1,216 @@
+from os import path
+import sys
+sys.path.append(path.join(path.dirname(__file__), "../.."))
+from himbaechel_dbgen.chip import *
+
+# Grid size including IOBs at edges
+X = 100
+Y = 100
+# LUT input count
+K = 4
+# SLICEs per tile
+N = 8
+# number of local wires
+Wl = N * (K + 1) + 16
+# 1/Fc for bel input wire pips; local wire pips and neighbour pips
+Si = 6
+Sq = 6
+Sl = 1
+
+dirs = [ # name, dx, dy
+    ("N", 0, -1),
+    ("NE", 1, -1),
+    ("E", 1, 0),
+    ("SE", 1, 1),
+    ("S", 0, 1),
+    ("SW", -1, 1),
+    ("W", -1, 0),
+    ("NW", -1, -1)
+]
+
+def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
+    # FIXME: terrible routing matrix, just for a toy example...
+    # switch wires
+    for i in range(Wl):
+        tt.create_wire(f"SWITCH{i}", "SWITCH")
+    # neighbor wires
+    for i in range(Wl):
+        for d, dx, dy in dirs:
+            tt.create_wire(f"{d}{i}", f"NEIGH_{d}")
+    # input pips
+    for i, w in enumerate(inputs):
+        for j in range((i % Si), Wl, Si):
+            tt.create_pip(f"SWITCH{j}", w)
+    # output pips
+    for i, w in enumerate(outputs):
+        for j in range((i % Sq), Wl, Sq):
+            tt.create_pip(w, f"SWITCH{j}")
+    # neighbour local pips
+    for i in range(Wl):
+        for j, (d, dx, dy) in enumerate(dirs):
+            tt.create_pip(f"{d}{(i + j) % Wl}", f"SWITCH{i}")
+    # clock "ladder"
+    if not tt.has_wire("CLK"):
+        tt.create_wire(f"CLK", "TILE_CLK")
+    tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
+    tt.create_pip(f"CLK_PREV", f"CLK")
+
+def create_logic_tiletype(chip: Chip):
+    tt = chip.create_tile_type("LOGIC")
+    # setup wires
+    inputs = []
+    outputs = []
+    for i in range(N):
+        for j in range(K):
+            inputs.append(f"L{i}_I{j}")
+            tt.create_wire(f"L{i}_I{j}", "LUT_INPUT")
+        tt.create_wire(f"L{i}_D", "FF_DATA")
+        tt.create_wire(f"L{i}_O", "LUT_OUT")
+        tt.create_wire(f"L{i}_Q", "FF_OUT")
+        outputs += [f"L{i}_O", f"L{i}_Q"]
+    tt.create_wire(f"CLK", "TILE_CLK")
+    # create logic cells
+    for i in range(N):
+        # LUT
+        lut = tt.create_bel(f"L{i}_LUT", "LUT4", z=(i*2 + 0))
+        for j in range(K):
+            tt.add_bel_pin(lut, f"I[{j}]", f"L{i}_I{j}", PinType.INPUT)
+        tt.add_bel_pin(lut, "F", f"L{i}_O", PinType.OUTPUT)
+        # FF data can come from LUT output or LUT I3
+        tt.create_pip(f"L{i}_O", f"L{i}_D")
+        tt.create_pip(f"L{i}_I{K-1}", f"L{i}_D")
+        # FF
+        ff = tt.create_bel(f"L{i}_FF", "DFF", z=(i*2 + 1))
+        tt.add_bel_pin(ff, "D", f"L{i}_D", PinType.INPUT)
+        tt.add_bel_pin(ff, "CLK", "CLK", PinType.INPUT)
+        tt.add_bel_pin(ff, "Q", f"L{i}_Q", PinType.OUTPUT)
+    create_switch_matrix(tt, inputs, outputs)
+    return tt
+
+N_io = 2
+
+def create_io_tiletype(chip: Chip):
+    tt = chip.create_tile_type("IO")
+     # setup wires
+    inputs = []
+    outputs = []
+    for i in range(N_io):
+        tt.create_wire(f"IO{i}_T", "IO_T")
+        tt.create_wire(f"IO{i}_I", "IO_I")
+        tt.create_wire(f"IO{i}_O", "IO_O")
+        tt.create_wire(f"IO{i}_PAD", "IO_PAD")
+        inputs += [f"IO{i}_T", f"IO{i}_I"]
+        outputs += [f"IO{i}_O", ]
+    tt.create_wire(f"CLK", "TILE_CLK")
+    for i in range(N_io):
+        io = tt.create_bel(f"IO{i}", "IOB", z=i)
+        tt.add_bel_pin(io, "I", f"IO{i}_I", PinType.INPUT)
+        tt.add_bel_pin(io, "T", f"IO{i}_T", PinType.INPUT)
+        tt.add_bel_pin(io, "O", f"IO{i}_O", PinType.OUTPUT)
+        tt.add_bel_pin(io, "PAD", f"IO{i}_PAD", PinType.INOUT)
+    # Actually used in top left IO only
+    tt.create_wire("GCLK_OUT", "GCLK")
+    tt.create_pip("IO0_O", "GCLK_OUT")
+    create_switch_matrix(tt, inputs, outputs)
+    return tt
+
+def create_bram_tiletype(chip: Chip):
+    Aw = 9
+    Dw = 16
+
+    tt = chip.create_tile_type("BRAM")
+    inputs = [f"RAM_WA{i}" for i in range(Aw)]
+    inputs += [f"RAM_RA{i}" for i in range(Aw)]
+    inputs += [f"RAM_WE{i}" for i in range(Dw // 8)]
+    inputs += [f"RAM_DI{i}" for i in range(Dw)]
+    outputs = [f"RAM_DO{i}" for i in range(Dw)]
+    for w in inputs:
+        tt.create_wire(w, "RAM_IN")
+    for w in outputs:
+        tt.create_wire(w, "RAM_OUT")
+    tt.create_wire(f"CLK", "TILE_CLK")
+    ram = tt.create_bel(f"RAM", F"BRAM_{2**Aw}X{Dw}", z=0)
+    tt.add_bel_pin(ram, "CLK", f"CLK", PinType.INPUT)
+    for i in range(Aw):
+        tt.add_bel_pin(ram, f"WA[{i}]", f"RAM_WA{i}", PinType.INPUT)
+        tt.add_bel_pin(ram, f"RA[{i}]", f"RAM_RA{i}", PinType.INPUT)
+    for i in range(Dw//8):
+        tt.add_bel_pin(ram, f"WE[{i}]", f"RAM_WE{i}", PinType.INPUT)
+    for i in range(Dw):
+        tt.add_bel_pin(ram, f"DI[{i}]", f"RAM_DI{i}", PinType.INPUT)
+        tt.add_bel_pin(ram, f"DO[{i}]", f"RAM_DO{i}", PinType.OUTPUT)
+    create_switch_matrix(tt, inputs, outputs)
+    return tt
+
+def create_corner_tiletype(ch):
+    tt = ch.create_tile_type("NULL")
+    tt.create_wire(f"CLK", "TILE_CLK")
+    tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
+    tt.create_pip(f"CLK_PREV", f"CLK")
+    return tt
+
+def is_corner(x, y):
+    return ((x == 0) or (x == (X-1))) and ((y == 0) or (y == (Y-1)))
+
+def create_nodes(ch):
+    for y in range(Y):
+        print(f"generating nodes for row {y}")
+        for x in range(X):
+            if not is_corner(x, y):
+                # connect up actual neighbours
+                local_nodes = [[NodeWire(x, y, f"SWITCH{i}")] for i in range(Wl)]
+                for d, dx, dy in dirs:
+                    x1 = x - dx
+                    y1 = y - dy
+                    if x1 < 0 or x1 >= X or y1 < 0 or y1 >= Y or is_corner(x1, y1):
+                        continue
+                    for i in range(Wl):
+                        local_nodes[i].append(NodeWire(x1, y1, f"{d}{i}"))
+                for n in local_nodes:
+                    ch.add_node(n)
+            # connect up clock ladder (not intended to be a sensible clock structure)
+            if y != 1: # special case where the node has 3 wires
+                if y == 0:
+                    if x == 0:
+                        # clock source: IO
+                        clk_node = [NodeWire(1, 0, "GCLK_OUT")]
+                    else:
+                        # clock source: left
+                        clk_node = [NodeWire(x-1, y, "CLK")]
+                else:
+                    # clock source: above
+                    clk_node = [NodeWire(x, y-1, "CLK")]
+                clk_node.append(NodeWire(x, y, "CLK_PREV"))
+                if y == 0:
+                    clk_node.append(NodeWire(x, y+1, "CLK_PREV"))
+                ch.add_node(clk_node)
+
+
+
+def main():
+    ch = Chip("example", "EX1", X, Y)
+    # Init constant ids
+    ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
+    logic = create_logic_tiletype(ch)
+    io = create_io_tiletype(ch)
+    bram = create_bram_tiletype(ch)
+    null = create_corner_tiletype(ch)
+    # Setup tile grid
+    for x in range(X):
+        for y in range(Y):
+            if x == 0 or x == X-1: # left/right side IO
+                if y == 0 or y == Y-1: # corner
+                    ch.set_tile_type(x, y, "NULL")
+                else:
+                    ch.set_tile_type(x, y, "IO")
+            elif y == 0 or y == Y-1: # top/bottom side IO
+                ch.set_tile_type(x, y, "IO")
+            elif (y % 15) == 7: # BRAM
+                ch.set_tile_type(x, y, "BRAM")
+            else:
+                ch.set_tile_type(x, y, "LOGIC")
+    # Create nodes between tiles
+    create_nodes(ch)
+    ch.write_bba(sys.argv[1])
+if __name__ == '__main__':
+    main()

From ca2e328a5fa7c538c5dad843558c66822bc4d5af Mon Sep 17 00:00:00 2001
From: Nathaniel Quillin <1446767+nqbit@users.noreply.github.com>
Date: Tue, 16 May 2023 03:38:02 +0000
Subject: [PATCH 379/712]  rename c++20 keyword s/requires/requires_range.

 See https://en.cppreference.com/w/cpp/language/requires for more details.
---
 common/kernel/constraints.impl.h            | 2 +-
 common/kernel/exclusive_state_groups.h      | 2 +-
 common/kernel/exclusive_state_groups.impl.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/kernel/constraints.impl.h b/common/kernel/constraints.impl.h
index 9c978411e1..145aff5be4 100644
--- a/common/kernel/constraints.impl.h
+++ b/common/kernel/constraints.impl.h
@@ -92,7 +92,7 @@ bool Constraints<StateCount, StateType, CountType>::isValidBelForCellType(const
             }
             break;
         case CONSTRAINT_TAG_REQUIRES:
-            if (!tags[constraint.tag()].requires(constraint.states())) {
+            if (!tags[constraint.tag()].requires_range(constraint.states())) {
                 return false;
             }
             break;
diff --git a/common/kernel/exclusive_state_groups.h b/common/kernel/exclusive_state_groups.h
index 7d447ffe1d..b99876bad1 100644
--- a/common/kernel/exclusive_state_groups.h
+++ b/common/kernel/exclusive_state_groups.h
@@ -127,7 +127,7 @@ template <size_t StateCount, typename StateType = int8_t, typename CountType = u
 
     template <typename StateRange>
     bool
-        requires(const StateRange &state_range)
+        requires_range(const StateRange &state_range)
     const
     {
         if (state < 0) {
diff --git a/common/kernel/exclusive_state_groups.impl.h b/common/kernel/exclusive_state_groups.impl.h
index f3ddb5fd38..6934a02871 100644
--- a/common/kernel/exclusive_state_groups.impl.h
+++ b/common/kernel/exclusive_state_groups.impl.h
@@ -70,7 +70,7 @@ void ExclusiveStateGroup<StateCount, StateType, CountType>::explain_requires(con
                                                                              const Definition &definition, BelId bel,
                                                                              const StateRange state_range) const
 {
-    if (requires(state_range)) {
+    if (requires_range(state_range)) {
         log_info("Placing cell %s at bel %s does not violate %s.%s\n", cell.c_str(ctx), ctx->nameOfBel(bel),
                  object.c_str(ctx), definition.prefix.c_str(ctx));
     } else {

From bc7b8b63ed6c8e855ca0256a2fde2b8c5885fd79 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 16 May 2023 16:38:16 +0200
Subject: [PATCH 380/712] mistral: Add a basic global clock router

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/arch.cc    |   2 +
 mistral/arch.h     |   1 +
 mistral/globals.cc | 149 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 152 insertions(+)

diff --git a/mistral/arch.cc b/mistral/arch.cc
index 05d780f304..da75ad924c 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -484,6 +484,8 @@ bool Arch::route()
 
     lab_pre_route();
 
+    route_globals();
+
     std::string router = str_or_default(settings, id_router, defaultRouter);
     bool result;
     if (router == "router1") {
diff --git a/mistral/arch.h b/mistral/arch.h
index aabe10c667..7cdc9f6bf8 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -503,6 +503,7 @@ struct Arch : BaseArch<ArchRanges>
     // -------------------------------------------------
 
     bool is_clkbuf_cell(IdString cell_type) const; // globals.cc
+    void route_globals();                          // globals.cc
 
     // -------------------------------------------------
 
diff --git a/mistral/globals.cc b/mistral/globals.cc
index bdd835a7e0..cb00b635ea 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -21,6 +21,8 @@
 #include "nextpnr.h"
 #include "util.h"
 
+#include <queue>
+
 NEXTPNR_NAMESPACE_BEGIN
 
 void Arch::create_clkbuf(int x, int y)
@@ -60,4 +62,151 @@ void Arch::create_control(int x, int y)
     add_bel_pin(oscillator_bel, id_clkout1, PORT_OUT, get_port(CycloneV::CTRL, x, y, -1, CycloneV::CLK_OUT1, -1));
 }
 
+struct MistralGlobalRouter
+{
+    Context *ctx;
+
+    MistralGlobalRouter(Context *ctx) : ctx(ctx){};
+
+    // When routing globals; we allow global->local for some tricky cases but never local->local
+    bool global_pip_filter(PipId pip) const
+    {
+        auto src_type = CycloneV::rn2t(pip.src);
+        return src_type != CycloneV::H14 && src_type != CycloneV::H6 && src_type != CycloneV::H3 &&
+               src_type != CycloneV::V12 && src_type != CycloneV::V2 && src_type != CycloneV::V4 &&
+               src_type != CycloneV::WM;
+    }
+
+    // Dedicated backwards BFS routing for global networks
+    template <typename Tfilt>
+    bool backwards_bfs_route(NetInfo *net, store_index<PortRef> user_idx, int iter_limit, bool strict, Tfilt pip_filter)
+    {
+        // Queue of wires to visit
+        std::queue<WireId> visit;
+        // Wire -> upstream pip
+        dict<WireId, PipId> backtrace;
+
+        // Lookup source and destination wires
+        WireId src = ctx->getNetinfoSourceWire(net);
+        WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(user_idx), 0);
+
+        if (src == WireId())
+            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
+                      ctx->nameOf(net->driver.port));
+
+        if (dst == WireId())
+            log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
+                      ctx->nameOf(net->users.at(user_idx).cell), ctx->nameOf(net->users.at(user_idx).port));
+
+        if (ctx->getBoundWireNet(src) != net)
+            ctx->bindWire(src, net, STRENGTH_LOCKED);
+
+        if (src == dst) {
+            // Nothing more to do
+            return true;
+        }
+
+        visit.push(dst);
+        backtrace[dst] = PipId();
+
+        int iter = 0;
+
+        while (!visit.empty() && (iter++ < iter_limit)) {
+            WireId cursor = visit.front();
+            visit.pop();
+            // Search uphill pips
+            for (PipId pip : ctx->getPipsUphill(cursor)) {
+                // Skip pip if unavailable, and not because it's already used for this net
+                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net)
+                    continue;
+                WireId prev = ctx->getPipSrcWire(pip);
+                // Ditto for the upstream wire
+                if (!ctx->checkWireAvail(prev) && ctx->getBoundWireNet(prev) != net)
+                    continue;
+                // Skip already visited wires
+                if (backtrace.count(prev))
+                    continue;
+                // Apply our custom pip filter
+                if (!pip_filter(pip))
+                    continue;
+                // Add to the queue
+                visit.push(prev);
+                backtrace[prev] = pip;
+                // Check if we are done yet
+                if (prev == src)
+                    goto done;
+            }
+            if (false) {
+            done:
+                break;
+            }
+        }
+
+        if (backtrace.count(src)) {
+            WireId cursor = src;
+            std::vector<PipId> pips;
+            // Create a list of pips on the routed path
+            while (true) {
+                PipId pip = backtrace.at(cursor);
+                if (pip == PipId())
+                    break;
+                pips.push_back(pip);
+                cursor = ctx->getPipDstWire(pip);
+            }
+            // Reverse that list
+            std::reverse(pips.begin(), pips.end());
+            // Bind pips until we hit already-bound routing
+            for (PipId pip : pips) {
+                WireId dst = ctx->getPipDstWire(pip);
+                if (ctx->getBoundWireNet(dst) == net)
+                    break;
+                ctx->bindPip(pip, net, STRENGTH_LOCKED);
+            }
+            return true;
+        } else {
+            if (strict)
+                log_error("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
+                          ctx->nameOfWire(src), ctx->nameOfWire(dst));
+            return false;
+        }
+    }
+
+    bool is_relaxed_sink(const PortRef &sink) const
+    {
+        // Cases where global clocks are driving fabric
+        if (sink.cell->type == id_MISTRAL_FF && sink.port != id_CLK)
+            return true;
+        return false;
+    }
+
+    void route_clk_net(NetInfo *net)
+    {
+        for (auto usr : net->users.enumerate())
+            backwards_bfs_route(net, usr.index, 1000000, true,
+                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
+        log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+    }
+
+    void operator()()
+    {
+        log_info("Routing globals...\n");
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            CellInfo *drv = ni->driver.cell;
+            if (drv == nullptr)
+                continue;
+            if (drv->type.in(id_MISTRAL_CLKENA, id_MISTRAL_CLKBUF)) {
+                route_clk_net(ni);
+                continue;
+            }
+        }
+    }
+};
+
+void Arch::route_globals()
+{
+    MistralGlobalRouter router(getCtx());
+    router();
+}
+
 NEXTPNR_NAMESPACE_END

From 98121308e09e39f56a1e61ae9ede31eaa963f47b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 17 May 2023 10:00:09 +0200
Subject: [PATCH 381/712] mistral: Don't allow route-through LUTs in carry-mode
 ALMs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/arch.h |  1 +
 mistral/lab.cc | 13 +++++++++----
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/mistral/arch.h b/mistral/arch.h
index 7cdc9f6bf8..a9d10808ef 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -48,6 +48,7 @@ struct ALMInfo
     std::array<BelId, 4> ff_bels;
 
     bool l6_mode = false;
+    bool carry_mode = false;
 
     // Which CLK/ENA and ACLR is chosen for each half
     std::array<int, 2> clk_ena_idx, aclr_idx;
diff --git a/mistral/lab.cc b/mistral/lab.cc
index d65ccf537f..8bcde3e355 100644
--- a/mistral/lab.cc
+++ b/mistral/lab.cc
@@ -425,7 +425,7 @@ bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
             return false;
     }
 
-    bool carry_mode = false;
+    bool carry_mode = (luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry);
 
     // No mixing of carry and non-carry
     if (luts[0] && luts[1] && luts[0]->combInfo.is_carry != luts[1]->combInfo.is_carry)
@@ -811,6 +811,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
     // This function should also insert route-through LUTs to legalise flipflop inputs as needed.
     auto &alm_data = labs.at(lab).alms.at(alm);
     alm_data.l6_mode = false;
+    alm_data.carry_mode = false;
     std::array<CellInfo *, 2> luts{getBoundBelCell(alm_data.lut_bels[0]), getBoundBelCell(alm_data.lut_bels[1])};
     std::array<CellInfo *, 4> ffs{getBoundBelCell(alm_data.ff_bels[0]), getBoundBelCell(alm_data.ff_bels[1]),
                                   getBoundBelCell(alm_data.ff_bels[2]), getBoundBelCell(alm_data.ff_bels[3])};
@@ -820,6 +821,8 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
         // Currently we treat LUT6s and MLABs as a special case, as they never share inputs or have fixed mappings
         if (!luts[i])
             continue;
+        if (luts[i]->combInfo.is_carry)
+            alm_data.carry_mode = true;
         if (luts[i]->type == id_MISTRAL_ALUT6) {
             alm_data.l6_mode = true;
             NPNR_ASSERT(luts[1 - i] == nullptr); // only allow one LUT6 per ALM and no other LUTs
@@ -916,7 +919,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
             continue;
         for (int j = 0; j < 2; j++) {
             CellInfo *ff = ffs[i * 2 + j];
-            if (!ff || !ff->ffInfo.datain || alm_data.l6_mode)
+            if (!ff || !ff->ffInfo.datain || alm_data.l6_mode || alm_data.carry_mode)
                 continue;
             CellInfo *rt_lut = createCell(idf("%s$ROUTETHRU", nameOf(ff)), id_MISTRAL_BUF);
             rt_lut->addInput(id_A);
@@ -1045,10 +1048,12 @@ uint64_t Arch::compute_lut_mask(uint32_t lab, uint8_t alm)
                     }
                 }
                 CellPinState state = lut->get_pin_state(log_pin);
-                if (state == PIN_0)
+                if (state == PIN_0) {
                     continue;
-                else if (state == PIN_1)
+                } else if (state == PIN_1) {
                     index |= (1 << init_idx);
+                    continue;
+                }
                 // Ignore if no associated physical pin
                 if (lut->getPort(log_pin) == nullptr || lut->pin_data.at(log_pin).bel_pins.empty())
                     continue;

From ea925f39fb0989705450c48f90e058f9707e0125 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 17 May 2023 10:31:39 +0200
Subject: [PATCH 382/712] archapi: Add getArcDelayOverride

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_api.h  |  1 +
 common/kernel/base_arch.h |  4 ++++
 common/kernel/context.cc  | 11 +++++++++++
 docs/archapi.md           |  8 ++++++++
 fpga_interchange/arch.h   |  5 +++++
 5 files changed, 29 insertions(+)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 56c5cf0a7a..c2de19e689 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -119,6 +119,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
     virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
     virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const = 0;
+    virtual bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const = 0;
     // Decal methods
     virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId decal) const = 0;
     virtual DecalXY getBelDecal(BelId bel) const = 0;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 609d937888..4da9498932 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -317,6 +317,10 @@ template <typename R> struct BaseArch : ArchAPI<R>
     {
         return false;
     }
+    virtual bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override
+    {
+        return false;
+    }
 
     // Decal methods
     virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId decal) const override
diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index 821ad822c4..7048be5987 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -128,6 +128,12 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
     if (src_wire == WireId())
         return 0;
 
+    DelayQuad quad_result;
+    if (getArcDelayOverride(net_info, user_info, quad_result)) {
+        // Arch overrides delay
+        return quad_result.maxDelay();
+    }
+
     delay_t max_delay = 0;
 
     for (auto dst_wire : getNetinfoSinkWires(net_info, user_info)) {
@@ -173,6 +179,11 @@ DelayQuad Context::getNetinfoRouteDelayQuad(const NetInfo *net_info, const PortR
 
     DelayQuad result(std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest());
 
+    if (getArcDelayOverride(net_info, user_info, result)) {
+        // Arch overrides delay
+        return result;
+    }
+
     for (auto dst_wire : getNetinfoSinkWires(net_info, user_info)) {
         WireId cursor = dst_wire;
         DelayQuad delay{0};
diff --git a/docs/archapi.md b/docs/archapi.md
index 3a7994de7e..062bd9467e 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -551,6 +551,14 @@ Overwrite or modify (in-place) the timing budget for a given arc. Returns a bool
 
 *BaseArch default: returns false*
 
+### bool getArcDelayOverride(const NetInfo \*net_info, const PortRef &sink, DelayQuad &delay) const
+
+This allows an arch to provide a more precise method for calculating the delay for a routed arc than
+summing wire and pip delays; for example a SPICE simulation. If available, `delay` should be set and
+`true` returned.
+
+*BaseArch default: returns false*
+
 Flow Methods
 ------------
 
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index a44c7c21bc..74473e63b8 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -709,6 +709,11 @@ struct Arch : ArchAPI<ArchRanges>
     uint32_t getDelayChecksum(delay_t v) const final { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const final;
 
+    bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const final
+    {
+        return false;
+    }
+
     // -------------------------------------------------
 
     void place_iobufs(WireId pad_wire, NetInfo *net,

From 7a827b1c787edb2362fffea8f072a95e331fe976 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 May 2023 16:39:44 +0100
Subject: [PATCH 383/712] mistral: improve timing calculation

---
 mistral/arch.cc      |   4 ++
 mistral/arch.h       |   4 ++
 mistral/bitstream.cc |  12 ++++
 mistral/delay.cc     | 162 ++++++++++++++++++++++++++++++++++++++-----
 4 files changed, 164 insertions(+), 18 deletions(-)

diff --git a/mistral/arch.cc b/mistral/arch.cc
index da75ad924c..7b8adfd4a7 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -462,6 +462,10 @@ bool Arch::place()
         cfg.cellGroups.back().insert({id_MISTRAL_COMB});
         cfg.cellGroups.back().insert({id_MISTRAL_FF});
 
+        // The Cyclone V is asymmetrical enough that it's somewhat beneficial to prefer connecting things horizontally.
+        cfg.hpwl_scale_x = 1;
+        cfg.hpwl_scale_y = 2;
+
         cfg.beta = 0.5; // TODO: find a good value of beta for sensible ALM spreading
         cfg.criticalityExponent = 7;
         if (!placer_heap(getCtx(), cfg))
diff --git a/mistral/arch.h b/mistral/arch.h
index a9d10808ef..eb0093fb1d 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -289,6 +289,9 @@ struct Arch : BaseArch<ArchRanges>
     ArchArgs args;
     mistral::CycloneV *cyclonev;
 
+    // Mistral needs the bitstream configuring before it can use the simulator.
+    bool bitstream_configured = false;
+
     Arch(ArchArgs args);
     ArchArgs archArgs() const override { return args; }
 
@@ -434,6 +437,7 @@ struct Arch : BaseArch<ArchRanges>
     bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
                       DelayQuad &delay) const override; // delay.cc
     DelayQuad getPipDelay(PipId pip) const override;    // delay.cc
+    bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override; // delay.cc
 
     // -------------------------------------------------
 
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index 3e1b8b6642..f9cb40ff34 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -20,6 +20,7 @@
 #include "log.h"
 #include "nextpnr.h"
 #include "util.h"
+#include "timing.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 namespace {
@@ -379,6 +380,7 @@ struct MistralBitgen
         write_routing();
         write_cells();
         write_labs();
+        ctx->bitstream_configured = true;
     }
 };
 } // namespace
@@ -387,6 +389,16 @@ void Arch::build_bitstream()
 {
     MistralBitgen gen(getCtx());
     gen.run();
+
+    // This is a hack to run timing analysis yet again after the bitstream is
+    // configured in Mistral, because the analogue simulator won't work until
+    // it has a bitstream in the library.
+    //
+    // A better solution would be to move a lot of this bitstream code to
+    // {un,}bind{Bel, Pip} and friends, but we're not there yet.
+    log_info("Running signoff timing analysis...\n");
+
+    timing_analysis(getCtx(), true, true, true, true, true);
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/mistral/delay.cc b/mistral/delay.cc
index c40ac3f095..7d999b0179 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -246,43 +246,167 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
 DelayQuad Arch::getPipDelay(PipId pip) const
 {
     WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
-    if ((src.is_nextpnr_created() && dst.is_nextpnr_created()) || dst.is_nextpnr_created())
+
+    if (src.is_nextpnr_created() || dst.is_nextpnr_created())
         return DelayQuad{20};
 
     // This is guesswork based on average of (interconnect delay / number of pips)
-    auto dst_type = CycloneV::rn2t(dst.node);
+    auto src_type = CycloneV::rn2t(src.node);
 
-    switch (dst_type) {
+    switch (src_type) {
+    case CycloneV::rnode_type_t::SCLK:
+        return DelayQuad{136, 136, 139, 139};
+    case CycloneV::rnode_type_t::SCLKB1:
+        return DelayQuad{296, 296, 370, 370};
+    case CycloneV::rnode_type_t::SCLKB2:
+        return DelayQuad{71, 71, 83, 83};
+    case CycloneV::rnode_type_t::HCLK:
+        return DelayQuad{183, 183, 239, 239};
+    case CycloneV::rnode_type_t::HCLKB:
+        return DelayQuad{165, 165, 244, 244};
+    case CycloneV::rnode_type_t::XCLKB1:
+        return DelayQuad{97, 97, 125, 125};
+    case CycloneV::rnode_type_t::GIN:
+        return DelayQuad{100};
     case CycloneV::rnode_type_t::H14:
-        return DelayQuad{254};
+        return DelayQuad{273, 286, 288, 291};
     case CycloneV::rnode_type_t::H3:
-        return DelayQuad{214};
+        return DelayQuad{196, 226, 163, 173};
     case CycloneV::rnode_type_t::H6:
-        return DelayQuad{298};
+        return DelayQuad{220, 275, 199, 217};
+    case CycloneV::rnode_type_t::V12:
+        return DelayQuad{361, 374, 337, 340};
     case CycloneV::rnode_type_t::V2:
-        return DelayQuad{210};
+        return DelayQuad{214, 231, 163, 175};
     case CycloneV::rnode_type_t::V4:
-        return DelayQuad{262};
-    case CycloneV::rnode_type_t::DCMUX:
+        return DelayQuad{290, 294, 243, 245};
+    case CycloneV::rnode_type_t::WM:
+        // WM explicitly has zero delay.
         return DelayQuad{0};
-    case CycloneV::rnode_type_t::GIN:
-        return DelayQuad{83}; // need to check with Sarayan
-    case CycloneV::rnode_type_t::GOUT:
-        return DelayQuad{123};
-    case CycloneV::rnode_type_t::TCLK:
-        return DelayQuad{46};
+    case CycloneV::rnode_type_t::TD:
+        return DelayQuad{208, 208, 177, 177};
     default:
-        return DelayQuad{308};
+        return DelayQuad{0};
     }
 }
 
+bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const
+{
+    if (!this->bitstream_configured)
+        return false;
+
+    WireId src_wire = getCtx()->getNetinfoSourceWire(net_info);
+    WireId dst_wire = getCtx()->getNetinfoSinkWire(net_info, sink, 0);
+    NPNR_ASSERT(src_wire != WireId());
+
+    bool inverted = false;
+    mistral::AnalogSim::wave input_wave[2], output_wave[2];
+    mistral::AnalogSim::time_interval output_delays[2];
+    mistral::AnalogSim::time_interval output_delay_sum[2];
+    std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs;
+    auto temp = mistral::CycloneV::T_100;
+    auto est = mistral::CycloneV::EST_SLOW;
+
+    output_delay_sum[0].mi = 0;
+    output_delay_sum[0].mx = 0;
+    output_delay_sum[1].mi = 0;
+    output_delay_sum[1].mx = 0;
+
+    // Mistral's analogue simulator propagates from source to destination,
+    // but nextpnr finds paths from destination to source, so some slight
+    // contortions are necessary.
+
+    std::vector<PipId> pips;
+
+    WireId cursor = dst_wire;
+    while (cursor != WireId() && cursor != src_wire) {
+        auto it = net_info->wires.find(cursor);
+
+        if (it == net_info->wires.end())
+            break;
+
+        PipId pip = it->second.pip;
+        if (pip == PipId())
+            break;
+
+        pips.push_back(pip);
+        cursor = getPipSrcWire(pip);
+    }
+
+    for (auto it = pips.rbegin(); it != pips.rend(); it++) {
+        PipId pip = *it;
+        auto src = getPipSrcWire(pip);
+        auto dst = getPipDstWire(pip);
+
+        if (src.is_nextpnr_created())
+            continue;
+
+        if (dst.is_nextpnr_created())
+            dst.node = 0;
+
+        auto mode = cyclonev->rnode_timing_get_mode(src.node);
+        NPNR_ASSERT(mode != mistral::CycloneV::RTM_UNSUPPORTED);
+
+        auto inverting = cyclonev->rnode_is_inverting(src.node);
+
+        if (mode == mistral::CycloneV::RTM_P2P) {
+            if (inverting == mistral::CycloneV::INV_YES || inverting == mistral::CycloneV::INV_PROGRAMMABLE)
+                inverted = !inverted;
+            continue;
+        }
+
+        if (mode == mistral::CycloneV::RTM_NO_DELAY) {
+            if (inverting)
+                inverted = !inverted;
+            continue;
+        }
+
+        if (input_wave[0].empty()) {
+            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE, est, input_wave[0]);
+            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, est, input_wave[1]);
+            NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() && !input_wave[mistral::CycloneV::RF_FALL].empty());
+        }
+
+        for (int edge = 0; edge != 2; edge++) {
+            auto actual_edge = edge ? inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL : inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE;
+            mistral::AnalogSim sim;
+            int input = -1;
+            std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs;
+            cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs);
+
+            sim.set_input_wave(input, input_wave[edge]);
+            auto o = std::find_if(outputs.begin(), outputs.end(), [&](std::pair<mistral::CycloneV::rnode_t, int> output) {
+                return output.first == dst.node;
+            });
+            NPNR_ASSERT(o != outputs.end());
+
+            output_wave[edge].clear();
+            sim.set_output_wave(o->second, output_wave[edge], output_delays[edge]);
+            sim.run();
+            cyclonev->rnode_timing_trim_wave(temp, CycloneV::DELAY_MAX, output_wave[edge], input_wave[edge]);
+
+            output_delay_sum[edge].mi += output_delays[edge].mi;
+            output_delay_sum[edge].mx += output_delays[edge].mx;
+        }
+
+        if (inverting == mistral::CycloneV::INV_YES || inverting == mistral::CycloneV::INV_PROGRAMMABLE)
+            inverted = !inverted;
+    }
+
+    delay = DelayQuad{delay_t(output_delay_sum[0].mi*1e12), delay_t(output_delay_sum[0].mx*1e12), delay_t(output_delay_sum[1].mi*1e12), delay_t(output_delay_sum[1].mx*1e12)};
+
+    return true;
+}
+
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
     NPNR_UNUSED(src_pin);
     NPNR_UNUSED(dst_pin);
     Loc src_loc = getBelLocation(src_bel);
     Loc dst_loc = getBelLocation(dst_bel);
-    return std::abs(dst_loc.y - src_loc.y) * 100 + std::abs(dst_loc.x - src_loc.x) * 100 + 100;
+    int x_diff = std::abs(dst_loc.x - src_loc.x);
+    int y_diff = std::abs(dst_loc.y - src_loc.y);
+    return 43*x_diff + 114*y_diff + 470;
 }
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
@@ -291,7 +415,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     int y0 = CycloneV::rn2y(src.node);
     int x1 = CycloneV::rn2x(dst.node);
     int y1 = CycloneV::rn2y(dst.node);
-    return 300 * std::abs(y1 - y0) + 300 * std::abs(x1 - x0) + 300;
+    int x_diff = std::abs(x1 - x0);
+    int y_diff = std::abs(y1 - y0);
+    return 43*x_diff + 114*y_diff + 470;
 }
 
 NEXTPNR_NAMESPACE_END

From 354b7daf128e0665ef0283adbdd295cf107734ae Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 19 May 2023 16:59:19 +1000
Subject: [PATCH 384/712] gowin: implement differential IO primitives (#1159)

* gowin: implement differential IO primitives

Adds missing TLVDS_IBUF/IOBUF/TBUF primitives, as well as all kinds of
LVDS emulation primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* gowin: fix build

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* gowin: support as differential not only pins A and B

The GW1N-1 and GW1NZ-1 chips have cells with pins up to I, we provide
support for such pins.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/constids.inc |   9 ++
 gowin/pack.cc      | 227 ++++++++++++++++++++++++++++++++++++---------
 2 files changed, 194 insertions(+), 42 deletions(-)

diff --git a/gowin/constids.inc b/gowin/constids.inc
index 3a4b0dd244..230abc09cd 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -638,6 +638,7 @@ X(O)
 X(IO)
 X(OE)
 X(OB)
+X(IB)
 
 // bels
 X(DFF0)
@@ -888,6 +889,13 @@ X(OBUF)
 X(IOBUF)
 X(TBUF)
 X(TLVDS_OBUF)
+X(TLVDS_TBUF)
+X(TLVDS_IBUF)
+X(TLVDS_IOBUF)
+X(ELVDS_OBUF)
+X(ELVDS_TBUF)
+X(ELVDS_IBUF)
+X(ELVDS_IOBUF)
 
 // global set/reset
 X(GSR)
@@ -918,6 +926,7 @@ X(BEL)
 X(DIFF)
 X(DIFF_TYPE)
 X(DEVICE)
+X(IOLOGIC_IOB)
 
 // ports
 X(EN)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index c9ca635b41..d316d66c9b 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -30,6 +30,46 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+static bool check_availability(const Context *ctx, IdString type)
+{
+    switch (type.hash()) {
+    case ID_ELVDS_IBUF:
+        if (ctx->device != "GW1NZ-1") {
+            return true;
+        }
+        break;
+    case ID_ELVDS_IOBUF:
+        if (ctx->device == "GW1NZ-1") {
+            return true;
+        }
+        break;
+    case ID_TLVDS_IBUF:
+        if (ctx->device != "GW1NZ-1") {
+            return true;
+        }
+        break;
+    case ID_TLVDS_OBUF:
+        if (ctx->device != "GW1NZ-1" && ctx->device != "GW1N-1") {
+            return true;
+        }
+        break;
+    case ID_TLVDS_TBUF:
+        if (ctx->device != "GW1NZ-1" && ctx->device != "GW1N-1") {
+            return true;
+        }
+        break;
+    case ID_TLVDS_IOBUF:
+        if (ctx->device == "GW1N-4") {
+            return true;
+        }
+        break;
+    default:
+        return true;
+    }
+    log_info("%s is not supported for device %s.\n", type.c_str(ctx), ctx->device.c_str());
+    return false;
+}
+
 static void make_dummy_alu(Context *ctx, int alu_idx, CellInfo *ci, CellInfo *packed_head,
                            std::vector<std::unique_ptr<CellInfo>> &new_cells)
 {
@@ -803,6 +843,13 @@ static bool is_gowin_diff_iob(const Context *ctx, const CellInfo *cell)
 {
     switch (cell->type.index) {
     case ID_TLVDS_OBUF:
+    case ID_TLVDS_TBUF:
+    case ID_TLVDS_IBUF:
+    case ID_TLVDS_IOBUF:
+    case ID_ELVDS_OBUF:
+    case ID_ELVDS_TBUF:
+    case ID_ELVDS_IBUF:
+    case ID_ELVDS_IOBUF:
         return true;
     default:
         return false;
@@ -886,6 +933,26 @@ static void get_next_oser16_loc(std::string device, Loc &loc)
     }
 }
 
+// create IOB connections for gowin_pack
+static void make_iob_nets(Context *ctx, CellInfo *iob)
+{
+    for (const auto &port : iob->ports) {
+        const NetInfo *net = iob->getPort(port.first);
+        std::string connected_net = "NET";
+        if (net != nullptr) {
+            if (ctx->verbose) {
+                log_info("%s: %s - %s\n", ctx->nameOf(iob), port.first.c_str(ctx), ctx->nameOf(net));
+            }
+            if (net->name == ctx->id("$PACKER_VCC_NET")) {
+                connected_net = "VCC";
+            } else if (net->name == ctx->id("$PACKER_GND_NET")) {
+                connected_net = "GND";
+            }
+            iob->setParam(ctx->idf("NET_%s", port.first.c_str(ctx)), connected_net);
+        }
+    }
+}
+
 // Pack IO logic
 static void pack_iologic(Context *ctx)
 {
@@ -899,6 +966,9 @@ static void pack_iologic(Context *ctx)
         CellInfo *ci = cell.second.get();
         if (ctx->verbose)
             log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+        if (ci->type == id_IOB) {
+            make_iob_nets(ctx, ci);
+        }
         if (is_gowin_iologic(ctx, ci)) {
             CellInfo *q0_dst = nullptr;
             CellInfo *q1_dst = nullptr;
@@ -953,12 +1023,18 @@ static void pack_iologic(Context *ctx)
                     break;
                 }
                 ci->setParam(ctx->id("OUTMODE"), out_mode);
+
+                // mark IOB as used by IOLOGIC
+                q0_dst->setParam(id_IOLOGIC_IOB, 1);
+
                 bool use_diff_io = false;
                 if (q0_dst->attrs.count(id_DIFF_TYPE)) {
-                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF")); // XXX compatibility
+                    ci->setParam(id_OBUF_TYPE, std::string("DBUF"));
                     use_diff_io = true;
                 } else {
-                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF")); // XXX compatibility
+                    ci->setParam(id_OBUF_TYPE, std::string("SBUF"));
                 }
 
                 // disconnect Q output: it is wired internally
@@ -987,19 +1063,7 @@ static void pack_iologic(Context *ctx)
                         ci->disconnectPort(output_1);
                         ci->setAttr(id_IOBUF, 1);
                     }
-                } else {
-                    // force OEN = 0 in order to enable output
-                    // XXX check for IOBUF and TBUF
-                    if (ci->type == id_OSER4 || ci->type == id_OSER8) {
-                        int port_num = ci->type == id_OSER4 ? 2 : 4;
-                        for (int i = 0; i < port_num; ++i) {
-                            IdString port = ctx->idf("TX%d", i);
-                            ci->disconnectPort(port);
-                            ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
-                        }
-                    }
                 }
-
                 ci->setAttr(id_IOBUF, 0);
                 ci->setAttr(id_IOLOGIC_TYPE, ci->type.str(ctx));
 
@@ -1087,12 +1151,18 @@ static void pack_iologic(Context *ctx)
                     break;
                 }
                 ci->setParam(ctx->id("INMODE"), in_mode);
+
+                // mark IOB as used by IOLOGIC
+                d_src->setParam(id_IOLOGIC_IOB, 1);
+
                 bool use_diff_io = false;
                 if (d_src->attrs.count(id_DIFF_TYPE)) {
-                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF")); // XXX compatibility
+                    ci->setParam(id_IBUF_TYPE, std::string("DBUF"));
                     use_diff_io = true;
                 } else {
-                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF")); // XXX compatibility
+                    ci->setParam(id_IBUF_TYPE, std::string("SBUF"));
                 }
 
                 // disconnect D input: it is wired internally
@@ -1168,12 +1238,17 @@ static void pack_iologic(Context *ctx)
                               iob_bel->second.as_string().c_str());
                 }
 
+                // mark IOB as used by IOLOGIC
+                q0_dst->setParam(id_IOLOGIC_IOB, 1);
+
                 bool use_diff_io = false;
                 if (q0_dst->attrs.count(id_DIFF_TYPE)) {
-                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF"));
+                    ci->setAttr(id_OBUF_TYPE, std::string("DBUF")); // compatibility
+                    ci->setParam(id_OBUF_TYPE, std::string("DBUF"));
                     use_diff_io = true;
                 } else {
-                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF"));
+                    ci->setAttr(id_OBUF_TYPE, std::string("SBUF")); // compatibility
+                    ci->setParam(id_OBUF_TYPE, std::string("SBUF"));
                 }
 
                 // disconnect Q output: it is wired internally
@@ -1297,13 +1372,17 @@ static void pack_iologic(Context *ctx)
                     log_error("No bel for %s at %s. Can't place IDES/OSER here\n", ctx->nameOf(ci),
                               iob_bel->second.as_string().c_str());
                 }
+                // mark IOB as used by IOLOGIC
+                d_src->setParam(id_IOLOGIC_IOB, 1);
 
                 bool use_diff_io = false;
                 if (d_src->attrs.count(id_DIFF_TYPE)) {
-                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("DBUF")); // XXX compatibility
+                    ci->setParam(id_IBUF_TYPE, std::string("DBUF"));
                     use_diff_io = true;
                 } else {
-                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF"));
+                    ci->setAttr(id_IBUF_TYPE, std::string("SBUF")); // XXX compatibility
+                    ci->setParam(id_IBUF_TYPE, std::string("SBUF"));
                 }
                 // disconnect D input: it is wired internally
                 delete_nets.insert(ci->getPort(id_D)->name);
@@ -1430,39 +1509,103 @@ static void pack_diff_io(Context *ctx)
             CellInfo *iob_p = nullptr;
             CellInfo *iob_n = nullptr;
             switch (ci->type.index) {
+            case ID_ELVDS_IOBUF: /* fall-through*/
+            case ID_ELVDS_IBUF:  /* fall-through*/
+            case ID_ELVDS_TBUF:  /* fall-through*/
+            case ID_ELVDS_OBUF:  /* fall-through*/
+            case ID_TLVDS_IOBUF: /* fall-through*/
+            case ID_TLVDS_IBUF:  /* fall-through*/
+            case ID_TLVDS_TBUF:  /* fall-through*/
             case ID_TLVDS_OBUF: {
-                iob_p = net_only_drives(ctx, ci->ports.at(id_O).net, is_iob, id_I);
-                iob_n = net_only_drives(ctx, ci->ports.at(id_OB).net, is_iob, id_I);
+                NPNR_ASSERT(check_availability(ctx, ci->type));
+                if (ci->type.in(id_TLVDS_TBUF, id_TLVDS_OBUF, id_TLVDS_IOBUF, id_ELVDS_TBUF, id_ELVDS_OBUF,
+                                id_ELVDS_IOBUF)) {
+                    iob_p = net_only_drives(ctx, ci->ports.at(id_O).net, is_iob, id_I);
+                    iob_n = net_only_drives(ctx, ci->ports.at(id_OB).net, is_iob, id_I);
+                } else {
+                    iob_p = net_driven_by(ctx, ci->ports.at(id_I).net, is_iob, id_O);
+                    iob_n = net_driven_by(ctx, ci->ports.at(id_IB).net, is_iob, id_O);
+                }
                 NPNR_ASSERT(iob_p != nullptr);
                 NPNR_ASSERT(iob_n != nullptr);
                 auto iob_p_bel_a = iob_p->attrs.find(id_BEL);
                 if (iob_p_bel_a == iob_p->attrs.end()) {
                     log_error("LVDS '%s' must be restricted.\n", ctx->nameOf(ci));
-                    continue;
                 }
                 BelId iob_p_bel = ctx->getBelByNameStr(iob_p_bel_a->second.as_string());
                 Loc loc_p = ctx->getBelLocation(iob_p_bel);
-                if (loc_p.z != 0) {
-                    log_error("LVDS '%s' positive pin is not A.\n", ctx->nameOf(ci));
-                    continue;
-                }
                 // restrict the N buffer
-                loc_p.z = 1;
-                iob_n->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc_p)).str(ctx);
+                ++loc_p.z;
+                BelId n_bel = ctx->getBelByLocation(loc_p);
+                if (n_bel == BelId()) {
+                    log_error("Invalid pin for '%s'.\n", ctx->nameOf(ci));
+                }
+                iob_n->attrs[id_BEL] = ctx->getBelName(n_bel).str(ctx);
+                iob_n->type = iob_p->type;
                 // mark IOBs as part of DS pair
-                iob_n->attrs[id_DIFF] = std::string("N");
-                iob_n->attrs[id_DIFF_TYPE] = std::string("TLVDS_OBUF");
-                iob_p->attrs[id_DIFF] = std::string("P");
-                iob_p->attrs[id_DIFF_TYPE] = std::string("TLVDS_OBUF");
-                // disconnect N input: it is wired internally
-                delete_nets.insert(iob_n->ports.at(id_I).net->name);
-                iob_n->disconnectPort(id_I);
-                ci->disconnectPort(id_OB);
-                // disconnect P output
-                delete_nets.insert(ci->ports.at(id_O).net->name);
-                ci->disconnectPort(id_O);
-                // connect TLVDS input to P input
-                ci->movePortTo(id_I, iob_p, id_I);
+                std::string io_type = ci->type.c_str(ctx);
+                // XXX compatibility
+                iob_n->setAttr(id_DIFF, std::string("N"));
+                iob_n->setAttr(id_DIFF_TYPE, io_type);
+                iob_p->setAttr(id_DIFF, std::string("P"));
+                iob_p->setAttr(id_DIFF_TYPE, io_type);
+
+                iob_n->setParam(id_DIFF, std::string("N"));
+                iob_n->setParam(id_DIFF_TYPE, io_type);
+                iob_p->setParam(id_DIFF, std::string("P"));
+                iob_p->setParam(id_DIFF_TYPE, io_type);
+
+                if (ci->type.in(id_TLVDS_TBUF, id_TLVDS_OBUF, id_ELVDS_TBUF, id_ELVDS_OBUF)) {
+                    // disconnect N input: it is wired internally
+                    delete_nets.insert(iob_n->ports.at(id_I).net->name);
+                    iob_n->disconnectPort(id_I);
+                    ci->disconnectPort(id_OB);
+                    // disconnect P output
+                    delete_nets.insert(ci->ports.at(id_O).net->name);
+                    ci->disconnectPort(id_O);
+                    // connect TLVDS input to P input
+                    ci->movePortTo(id_I, iob_p, id_I);
+                    if (ci->type.in(id_TLVDS_TBUF, id_ELVDS_TBUF)) {
+                        if (iob_p->type == id_IOBS) {
+                            iob_p->disconnectPort(id_OEN);
+                            iob_n->disconnectPort(id_OEN);
+                        }
+                        ci->movePortTo(id_OEN, iob_p, id_OEN);
+                    }
+                }
+                if (ci->type.in(id_TLVDS_IBUF, id_ELVDS_IBUF)) {
+                    // disconnect N input: it is wired internally
+                    delete_nets.insert(iob_n->ports.at(id_O).net->name);
+                    iob_n->disconnectPort(id_O);
+                    ci->disconnectPort(id_IB);
+                    // disconnect P input
+                    delete_nets.insert(ci->ports.at(id_I).net->name);
+                    ci->disconnectPort(id_I);
+                    // connect TLVDS output to P output
+                    ci->movePortTo(id_O, iob_p, id_O);
+                }
+                if (ci->type.in(id_TLVDS_IOBUF, id_ELVDS_IOBUF)) {
+                    // disconnect N io: it is wired internally
+                    // O port is missing after iopadmap so leave it as is
+                    delete_nets.insert(iob_n->getPort(id_I)->name);
+                    iob_n->disconnectPort(id_I);
+                    iob_n->disconnectPort(id_OEN);
+                    ci->disconnectPort(id_IOB);
+
+                    // disconnect P io
+                    delete_nets.insert(ci->getPort(id_IO)->name);
+                    iob_p->disconnectPort(id_I);
+                    iob_p->disconnectPort(id_OEN);
+                    ci->disconnectPort(id_IO);
+                    ci->movePortTo(id_I, iob_p, id_I);
+                    ci->movePortTo(id_O, iob_p, id_O);
+                    // OEN
+                    if (iob_p->type == id_IOBS) {
+                        iob_p->disconnectPort(id_OEN);
+                        iob_n->disconnectPort(id_OEN);
+                    }
+                    ci->movePortTo(id_OEN, iob_p, id_OEN);
+                }
                 packed_cells.insert(ci->name);
             } break;
             default:

From 1d3e5151ba5ccbb344e04b7024d4d270cb4acfba Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 19 May 2023 09:00:31 +0200
Subject: [PATCH 385/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/exclusive_state_groups.h |  5 +----
 himbaechel/arch.cc                     |  4 +---
 mistral/arch.h                         |  4 ++--
 mistral/bitstream.cc                   |  2 +-
 mistral/delay.cc                       | 28 +++++++++++++++++---------
 5 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/common/kernel/exclusive_state_groups.h b/common/kernel/exclusive_state_groups.h
index b99876bad1..508e94dd33 100644
--- a/common/kernel/exclusive_state_groups.h
+++ b/common/kernel/exclusive_state_groups.h
@@ -125,10 +125,7 @@ template <size_t StateCount, typename StateType = int8_t, typename CountType = u
         }
     }
 
-    template <typename StateRange>
-    bool
-        requires_range(const StateRange &state_range)
-    const
+    template <typename StateRange> bool requires_range(const StateRange &state_range) const
     {
         if (state < 0) {
             return false;
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 6f5b303eed..f7ca2357ee 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -23,13 +23,11 @@
 #include "log.h"
 #include "nextpnr.h"
 
-#include "util.h"
 #include "placer1.h"
 #include "placer_heap.h"
 #include "router1.h"
 #include "router2.h"
-
-
+#include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
diff --git a/mistral/arch.h b/mistral/arch.h
index eb0093fb1d..bc950566a8 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -435,8 +435,8 @@ struct Arch : BaseArch<ArchRanges>
                                        int &clockInfoCount) const override;                                // delay.cc
     TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override; // delay.cc
     bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
-                      DelayQuad &delay) const override; // delay.cc
-    DelayQuad getPipDelay(PipId pip) const override;    // delay.cc
+                      DelayQuad &delay) const override;                                                      // delay.cc
+    DelayQuad getPipDelay(PipId pip) const override;                                                         // delay.cc
     bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override; // delay.cc
 
     // -------------------------------------------------
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index f9cb40ff34..c7fe7ccbb0 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -19,8 +19,8 @@
 
 #include "log.h"
 #include "nextpnr.h"
-#include "util.h"
 #include "timing.h"
+#include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 namespace {
diff --git a/mistral/delay.cc b/mistral/delay.cc
index 7d999b0179..896e518bfb 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -362,22 +362,29 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
         }
 
         if (input_wave[0].empty()) {
-            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE, est, input_wave[0]);
-            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, est, input_wave[1]);
-            NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() && !input_wave[mistral::CycloneV::RF_FALL].empty());
+            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
+                                                    inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE,
+                                                    est, input_wave[0]);
+            cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
+                                                    inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL,
+                                                    est, input_wave[1]);
+            NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() &&
+                        !input_wave[mistral::CycloneV::RF_FALL].empty());
         }
 
         for (int edge = 0; edge != 2; edge++) {
-            auto actual_edge = edge ? inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL : inverted ? mistral::CycloneV::RF_FALL : mistral::CycloneV::RF_RISE;
+            auto actual_edge = edge       ? inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL
+                               : inverted ? mistral::CycloneV::RF_FALL
+                                          : mistral::CycloneV::RF_RISE;
             mistral::AnalogSim sim;
             int input = -1;
             std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs;
             cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs);
 
             sim.set_input_wave(input, input_wave[edge]);
-            auto o = std::find_if(outputs.begin(), outputs.end(), [&](std::pair<mistral::CycloneV::rnode_t, int> output) {
-                return output.first == dst.node;
-            });
+            auto o = std::find_if(
+                    outputs.begin(), outputs.end(),
+                    [&](std::pair<mistral::CycloneV::rnode_t, int> output) { return output.first == dst.node; });
             NPNR_ASSERT(o != outputs.end());
 
             output_wave[edge].clear();
@@ -393,7 +400,8 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
             inverted = !inverted;
     }
 
-    delay = DelayQuad{delay_t(output_delay_sum[0].mi*1e12), delay_t(output_delay_sum[0].mx*1e12), delay_t(output_delay_sum[1].mi*1e12), delay_t(output_delay_sum[1].mx*1e12)};
+    delay = DelayQuad{delay_t(output_delay_sum[0].mi * 1e12), delay_t(output_delay_sum[0].mx * 1e12),
+                      delay_t(output_delay_sum[1].mi * 1e12), delay_t(output_delay_sum[1].mx * 1e12)};
 
     return true;
 }
@@ -406,7 +414,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     Loc dst_loc = getBelLocation(dst_bel);
     int x_diff = std::abs(dst_loc.x - src_loc.x);
     int y_diff = std::abs(dst_loc.y - src_loc.y);
-    return 43*x_diff + 114*y_diff + 470;
+    return 43 * x_diff + 114 * y_diff + 470;
 }
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
@@ -417,7 +425,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     int y1 = CycloneV::rn2y(dst.node);
     int x_diff = std::abs(x1 - x0);
     int y_diff = std::abs(y1 - y0);
-    return 43*x_diff + 114*y_diff + 470;
+    return 43 * x_diff + 114 * y_diff + 470;
 }
 
 NEXTPNR_NAMESPACE_END

From f03da6568b8696fc25e29b91177e95b68386694d Mon Sep 17 00:00:00 2001
From: Meinhard Kissich <privat@meinhard-kissich.at>
Date: Mon, 22 May 2023 09:39:05 +0200
Subject: [PATCH 386/712] Fix segfault when clocking a FF from a ring
 oscillator (#1160)

* fix segfault when clocking a FF from a ring osc

* Change std::set to pool

Co-authored-by: Lofty <dan.ravensloft@gmail.com>

---------

Co-authored-by: Meinhard Kissich <meinhard.kissich@tugraz.at>
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
---
 common/kernel/timing.cc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 924f336c62..dc2bfad147 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -296,8 +296,8 @@ void TimingAnalyser::identify_related_domains()
 
     // For each clock net identify all nets that can possibly drive it. Compute
     // cumulative delays to each of them.
-    std::function<void(const NetInfo *, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
-            [&](const NetInfo *ni, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
+    std::function<void(const NetInfo *, pool<IdString> &, dict<IdString, delay_t> &, delay_t)> find_net_drivers =
+            [&](const NetInfo *ni, pool<IdString> &net_trace, dict<IdString, delay_t> &drivers, delay_t delay_acc) {
                 // Get driving cell and port
                 if (ni == nullptr)
                     return;
@@ -309,6 +309,13 @@ void TimingAnalyser::identify_related_domains()
 
                 bool didGoUpstream = false;
 
+                // Ring oscillator driving the net
+                if (net_trace.find(ni->name) != net_trace.end()) {
+                    drivers[ni->name] = delay_acc;
+                    return;
+                }
+                net_trace.insert(ni->name);
+
                 // The cell has only one port
                 if (cell->ports.size() == 1) {
                     drivers[ni->name] = delay_acc;
@@ -350,7 +357,7 @@ void TimingAnalyser::identify_related_domains()
                     }
 
                     // Recurse
-                    find_net_drivers(pi.net, drivers, delay_acc + delay.maxDelay());
+                    find_net_drivers(pi.net, net_trace, drivers, delay_acc + delay.maxDelay());
                     didGoUpstream = true;
                 }
 
@@ -371,7 +378,8 @@ void TimingAnalyser::identify_related_domains()
             continue;
 
         dict<IdString, delay_t> drivers;
-        find_net_drivers(ni, drivers, 0);
+        pool<IdString> net_trace;
+        find_net_drivers(ni, net_trace, drivers, 0);
 
         clock_drivers[domain.key.clock] = drivers;
 

From 7dafd4da58fd3dcbd55e0e4c8489958b9ad6b837 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 22 May 2023 09:44:38 +0200
Subject: [PATCH 387/712] mistral: Fix uninitialised comb_out for plain LUTs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 mistral/lab.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/mistral/lab.cc b/mistral/lab.cc
index 8bcde3e355..692197fda1 100644
--- a/mistral/lab.cc
+++ b/mistral/lab.cc
@@ -319,6 +319,7 @@ void Arch::assign_comb_info(CellInfo *cell) const
         }
 
     } else {
+        cell->combInfo.comb_out = cell->getPort(id_Q);
         cell->combInfo.lut_input_count = 0;
         switch (cell->type.index) {
         case ID_MISTRAL_ALUT6:

From 7912a61ce3b7a64b872326bd0fdf8e7c472cb035 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 22 May 2023 12:01:20 +0100
Subject: [PATCH 388/712] mistral: rework delay estimate (#1161)

---
 mistral/delay.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mistral/delay.cc b/mistral/delay.cc
index 896e518bfb..5b13820f8b 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -414,7 +414,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     Loc dst_loc = getBelLocation(dst_bel);
     int x_diff = std::abs(dst_loc.x - src_loc.x);
     int y_diff = std::abs(dst_loc.y - src_loc.y);
-    return 43 * x_diff + 114 * y_diff + 470;
+    return 75 * x_diff + 200 * y_diff;
 }
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
@@ -425,7 +425,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
     int y1 = CycloneV::rn2y(dst.node);
     int x_diff = std::abs(x1 - x0);
     int y_diff = std::abs(y1 - y0);
-    return 43 * x_diff + 114 * y_diff + 470;
+    return 75 * x_diff + 200 * y_diff;
 }
 
 NEXTPNR_NAMESPACE_END

From 5936464967852d2df3833df571ca79f47cea17c3 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 25 May 2023 09:47:10 +0100
Subject: [PATCH 389/712] router2: add alternate weight option (#1162)

---
 common/kernel/command.cc |  5 +++++
 common/route/router2.cc  | 17 ++++++++++++-----
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 68066af6cf..4619c00e58 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -211,6 +211,8 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("router2-tmg-ripup",
                           "enable experimental timing-driven ripup in router (deprecated; use --tmg-ripup instead)");
 
+    general.add_options()("router2-alt-weights", "use alternate router2 weights");
+
     general.add_options()("report", po::value<std::string>(),
                           "write timing and utilization report in JSON format to file");
     general.add_options()("detailed-timing-report", "Append detailed net timing data to the JSON report");
@@ -352,6 +354,9 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("tmg-ripup") || vm.count("router2-tmg-ripup"))
         ctx->settings[ctx->id("router/tmg_ripup")] = true;
 
+    if (vm.count("router2-alt-weights"))
+        ctx->settings[ctx->id("router2/alt-weights")] = true;
+
     // Setting default values
     if (ctx->settings.find(ctx->id("target_freq")) == ctx->settings.end())
         ctx->settings[ctx->id("target_freq")] = std::to_string(12e6);
diff --git a/common/route/router2.cc b/common/route/router2.cc
index bb545003b8..bed8041e2c 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -1423,7 +1423,7 @@ struct Router2
             int tmgfail = 0;
             if (timing_driven)
                 tmg.run(false);
-            if (timing_driven_ripup && iter < 500) {
+            if (timing_driven_ripup && iter < 1500) {
                 for (size_t i = 0; i < nets_by_udata.size(); i++) {
                     NetInfo *ni = nets_by_udata.at(i);
                     for (auto usr : ni->users.enumerate()) {
@@ -1492,10 +1492,17 @@ Router2Cfg::Router2Cfg(Context *ctx)
     bb_margin_y = ctx->setting<int>("router2/bbMargin/y", 3);
     ipin_cost_adder = ctx->setting<float>("router2/ipinCostAdder", 0.0f);
     bias_cost_factor = ctx->setting<float>("router2/biasCostFactor", 0.25f);
-    init_curr_cong_weight = ctx->setting<float>("router2/initCurrCongWeight", 0.5f);
-    hist_cong_weight = ctx->setting<float>("router2/histCongWeight", 1.0f);
-    curr_cong_mult = ctx->setting<float>("router2/currCongWeightMult", 2.0f);
-    estimate_weight = ctx->setting<float>("router2/estimateWeight", 1.25f);
+    if (ctx->settings.count(ctx->id("router2/alt-weights"))) {
+        init_curr_cong_weight = ctx->setting<float>("router2/initCurrCongWeight", 5.0f);
+        hist_cong_weight = ctx->setting<float>("router2/histCongWeight", 0.5f);
+        curr_cong_mult = ctx->setting<float>("router2/currCongWeightMult", 0.0f);
+        estimate_weight = ctx->setting<float>("router2/estimateWeight", 1.0f);
+    } else {
+        init_curr_cong_weight = ctx->setting<float>("router2/initCurrCongWeight", 0.5f);
+        hist_cong_weight = ctx->setting<float>("router2/histCongWeight", 1.0f);
+        curr_cong_mult = ctx->setting<float>("router2/currCongWeightMult", 2.0f);
+        estimate_weight = ctx->setting<float>("router2/estimateWeight", 1.25f);
+    }
     perf_profile = ctx->setting<bool>("router2/perfProfile", false);
     if (ctx->settings.count(ctx->id("router2/heatmap")))
         heatmap = ctx->settings.at(ctx->id("router2/heatmap")).as_string();

From e5a5de53c1e0146582742202e702e98748899b75 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 25 May 2023 17:53:45 +0100
Subject: [PATCH 390/712] mistral: fallback to guess if simulator has no
 waveform

---
 mistral/delay.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/mistral/delay.cc b/mistral/delay.cc
index 5b13820f8b..19fa2237e8 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -368,8 +368,9 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
             cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
                                                     inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL,
                                                     est, input_wave[1]);
-            NPNR_ASSERT(!input_wave[mistral::CycloneV::RF_RISE].empty() &&
-                        !input_wave[mistral::CycloneV::RF_FALL].empty());
+            if (input_wave[mistral::CycloneV::RF_RISE].empty() ||
+                    input_wave[mistral::CycloneV::RF_FALL].empty())
+                return false;
         }
 
         for (int edge = 0; edge != 2; edge++) {

From c5666c47fe6f576cb2473069772be76e2b947f6c Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 29 May 2023 01:36:05 +0100
Subject: [PATCH 391/712] mistral: fix corner cases related to 13x1-bit M10Ks

---
 mistral/pack.cc | 31 ++++++++++++++++++++++---------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/mistral/pack.cc b/mistral/pack.cc
index 709479a294..51ad0aeb50 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -393,6 +393,9 @@ struct MistralPacker
             auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
             NPNR_ASSERT(abits >= 7 && abits <= 13);
             NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
+            NPNR_ASSERT((1 << abits) * dbits <= 10240);
+
+            log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str());
 
             // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
 
@@ -409,16 +412,18 @@ struct MistralPacker
             // Enables left unconnected.
 
             // Address lines.
-            int addr_offset = std::max(12 - std::max(abits, int64_t{9}), 0l);
-            int bit_offset = 0;
+
+            // One could remove the std::max here and the `- bit_offset`s here,
+            // because they would cancel out, but I think this way is less confusing.
+            int addr_offset = std::max(12 - std::max(abits, 9L), 0L);
+            int bit_offset = (abits == 13);
             if (abits == 13) {
                 ci->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
                 ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
-                bit_offset = 1;
             }
             for (int bit = bit_offset; bit < abits; bit++) {
-                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset)};
-                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset)};
+                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
+                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
             }
 
             // Data lines
@@ -447,15 +452,23 @@ struct MistralPacker
                 offsets.push_back(16);
                 offsets.push_back(18);
             }
+
+            // In this corner case the pin name does not have indexing
+            // because it's a single bit wide...
+            if (abits == 13 && dbits == 1) {
+                for (int offset : offsets)
+                    ci->pin_data[ctx->idf("A1DATA")].bel_pins.push_back(ctx->idf("DATAAIN[%d]", offset));
+                ci->pin_data[ctx->idf("B1DATA")].bel_pins = {ctx->idf("DATABOUT[0]")};
+                continue;
+            }
+
             for (int bit = 0; bit < dbits; bit++) {
-                for (int offset : offsets) {
+                for (int offset : offsets)
                     ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset));
-                }
             }
 
-            for (int bit = 0; bit < dbits; bit++) {
+            for (int bit = 0; bit < dbits; bit++)
                 ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit)};
-            }
         }
     }
 

From 119b47acf3be0c7bd5b75f736ac07fdc81f74c2a Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 29 May 2023 05:39:28 +0100
Subject: [PATCH 392/712] mistral: add 8x40-bit M10K addressing mode

---
 mistral/bitstream.cc | 18 ++++++++++--------
 mistral/pack.cc      | 31 +++++++++++++++++++++++--------
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index c7fe7ccbb0..e326881071 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -126,9 +126,11 @@ struct MistralBitgen
         // Notes:
         // DATA_FLOW_THRU is probably transparent reads.
 
+        auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
+
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, dbits);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, dbits == 40 ? CycloneV::SLOW : CycloneV::FAST);
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2);
@@ -136,8 +138,8 @@ struct MistralBitgen
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
-        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, dbits);
+        cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, dbits == 40 ? CycloneV::SLOW : CycloneV::FAST);
         cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::ASYNC);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2);
@@ -145,10 +147,10 @@ struct MistralBitgen
         cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b);
 
         cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1);
-        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1);
-        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1);
-        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, dbits != 40);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, dbits != 40);
+        cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, dbits != 40);
+        cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, dbits != 40);
 
         cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 0);
 
diff --git a/mistral/pack.cc b/mistral/pack.cc
index 51ad0aeb50..c0a71e3312 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -392,7 +392,7 @@ struct MistralPacker
             auto abits = ci->params.at(id_CFG_ABITS).as_int64();
             auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
             NPNR_ASSERT(abits >= 7 && abits <= 13);
-            NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
+            NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40);
             NPNR_ASSERT((1 << abits) * dbits <= 10240);
 
             log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str());
@@ -402,8 +402,11 @@ struct MistralPacker
             // It *does* generate ACLR[01] but leaves them unconnected if unused.
 
             // Enables.
-            // RDEN[1] and WREN[0] are left unconnected.
-            ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")};
+            // RDEN[1] is left unconnected.
+            if (dbits == 40)
+                ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[0]")};
+            else
+                ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")};
             ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("RDEN[0]")};
 
             // Clocks.
@@ -415,7 +418,7 @@ struct MistralPacker
 
             // One could remove the std::max here and the `- bit_offset`s here,
             // because they would cancel out, but I think this way is less confusing.
-            int addr_offset = std::max(12 - std::max(abits, 9L), 0L);
+            int addr_offset = std::max(12 - std::max(abits, dbits == 40 ? 8L : 9L), 0L);
             int bit_offset = (abits == 13);
             if (abits == 13) {
                 ci->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
@@ -462,13 +465,25 @@ struct MistralPacker
                 continue;
             }
 
-            for (int bit = 0; bit < dbits; bit++) {
+            // 40-bit data mode causes some headaches...
+            bit_offset = dbits == 40 ? 20 : 0;
+
+            // Write port
+            for (int bit = 0; bit < std::min(dbits, 20L); bit++)
                 for (int offset : offsets)
                     ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset));
-            }
 
-            for (int bit = 0; bit < dbits; bit++)
-                ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit)};
+            if (dbits == 40)
+                for (int bit = bit_offset; bit < dbits; bit++)
+                    ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATABIN[%d]", bit - bit_offset));
+
+            // Read port
+            if (dbits == 40)
+                for (int bit = 0; bit < 20; bit++)
+                    ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATAAOUT[%d]", bit)};
+
+            for (int bit = bit_offset; bit < dbits; bit++)
+                ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit - bit_offset)};
         }
     }
 

From 5b958c4d80e791d924c80bca48a1c41a8037e1d8 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Fri, 9 Jun 2023 08:01:47 +0200
Subject: [PATCH 393/712] Analyse async paths in TimingAnalyser (#1171)

---
 common/kernel/timing.cc | 107 ++++++++++++++++++++++++++++------------
 common/kernel/timing.h  |   8 ++-
 2 files changed, 82 insertions(+), 33 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index dc2bfad147..7888e34a2f 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -30,9 +30,24 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
-const char *edge_name(ClockEdge edge) { return (edge == FALLING_EDGE) ? "negedge" : "posedge"; }
+std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
+    std::string value;
+    if (dom.is_async())
+        value = "<async>";
+    else
+        value = (dom.edge == FALLING_EDGE ? "negedge " : "posedge ") + dom.clock.str(ctx);
+    
+    return value;
+}
 } // namespace
 
+TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) {
+    ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE};
+    domain_to_id.emplace(key, 0);
+    domains.emplace_back(key);
+    async_clock_id = 0;
+};
+
 void TimingAnalyser::setup()
 {
     init_ports();
@@ -69,6 +84,8 @@ void TimingAnalyser::init_ports()
 
 void TimingAnalyser::get_cell_delays()
 {
+    auto async_clk_key = domains.at(async_clock_id);
+
     for (auto &port : ports) {
         CellInfo *ci = cell_info(port.first);
         auto &pi = port_info(port.first);
@@ -81,8 +98,7 @@ void TimingAnalyser::get_cell_delays()
         pd.cell_arcs.clear();
         int clkInfoCount = 0;
         TimingPortClass cls = ctx->getPortTimingClass(ci, name, clkInfoCount);
-        if (cls == TMG_STARTPOINT || cls == TMG_ENDPOINT || cls == TMG_CLOCK_INPUT || cls == TMG_GEN_CLOCK ||
-            cls == TMG_IGNORE)
+        if (cls == TMG_CLOCK_INPUT || cls == TMG_GEN_CLOCK || cls == TMG_IGNORE)
             continue;
         if (pi.type == PORT_IN) {
             // Input ports might have setup/hold relationships
@@ -98,15 +114,21 @@ void TimingAnalyser::get_cell_delays()
                 }
             }
             // Combinational delays through cell
-            for (auto &other_port : ci->ports) {
-                auto &op = other_port.second;
-                // ignore dangling ports and non-outputs
-                if (op.net == nullptr || op.type != PORT_OUT)
-                    continue;
-                DelayQuad delay;
-                bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
-                if (is_path)
-                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            else if (cls == TMG_COMB_INPUT) {
+                for (auto &other_port : ci->ports) {
+                    auto &op = other_port.second;
+                    // ignore dangling ports and non-outputs
+                    if (op.net == nullptr || op.type != PORT_OUT)
+                        continue;
+                    DelayQuad delay;
+                    bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
+                    if (is_path)
+                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+                }
+            }
+            // asynchronous endpoint
+            else if (cls == TMG_ENDPOINT) {
+                pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {});
             }
         } else if (pi.type == PORT_OUT) {
             // Output ports might have clk-to-q relationships
@@ -119,15 +141,21 @@ void TimingAnalyser::get_cell_delays()
                 }
             }
             // Combinational delays through cell
-            for (auto &other_port : ci->ports) {
-                auto &op = other_port.second;
-                // ignore dangling ports and non-inputs
-                if (op.net == nullptr || op.type != PORT_IN)
-                    continue;
-                DelayQuad delay;
-                bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
-                if (is_path)
-                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            else if (cls == TMG_COMB_OUTPUT) {
+                for (auto &other_port : ci->ports) {
+                    auto &op = other_port.second;
+                    // ignore dangling ports and non-inputs
+                    if (op.net == nullptr || op.type != PORT_IN)
+                        continue;
+                    DelayQuad delay;
+                    bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
+                    if (is_path)
+                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+                }
+            }
+            // Asynchronous startpoint
+            else if (cls == TMG_STARTPOINT) {
+                pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {});
             }
         }
     }
@@ -194,9 +222,9 @@ void TimingAnalyser::setup_port_domains()
         d.startpoints.clear();
         d.endpoints.clear();
     }
-    // Go forward through the topological order (domains from the PoV of arrival time)
     bool first_iter = true;
     do {
+        // Go forward through the topological order (domains from the PoV of arrival time)
         updated_domains = false;
         for (auto port : topological_order) {
             auto &pd = ports.at(port);
@@ -204,10 +232,14 @@ void TimingAnalyser::setup_port_domains()
             if (pi.type == PORT_OUT) {
                 if (first_iter) {
                     for (auto &fanin : pd.cell_arcs) {
-                        if (fanin.type != CellArc::CLK_TO_Q)
-                            continue;
+                        domain_id_t dom;
                         // registered outputs are startpoints
-                        auto dom = domain_id(port.cell, fanin.other_port, fanin.edge);
+                        if (fanin.type == CellArc::CLK_TO_Q)
+                            dom = domain_id(port.cell, fanin.other_port, fanin.edge);
+                        else if (fanin.type == CellArc::STARTPOINT)
+                            dom = async_clock_id;
+                        else
+                            continue;
                         // create per-domain data
                         pd.arrival[dom];
                         domains.at(dom).startpoints.emplace_back(port, fanin.other_port);
@@ -240,10 +272,14 @@ void TimingAnalyser::setup_port_domains()
             } else {
                 if (first_iter) {
                     for (auto &fanout : pd.cell_arcs) {
-                        if (fanout.type != CellArc::SETUP)
-                            continue;
+                        domain_id_t dom;
                         // registered inputs are endpoints
-                        auto dom = domain_id(port.cell, fanout.other_port, fanout.edge);
+                        if (fanout.type == CellArc::SETUP)
+                            dom = domain_id(port.cell, fanout.other_port, fanout.edge);
+                        else if (fanout.type == CellArc::ENDPOINT)
+                            dom = async_clock_id;
+                        else
+                            continue;
                         // create per-domain data
                         pd.required[dom];
                         domains.at(dom).endpoints.emplace_back(port, fanout.other_port);
@@ -254,7 +290,7 @@ void TimingAnalyser::setup_port_domains()
                     copy_domains(port, CellPortKey(pi.net->driver), true);
             }
         }
-        // Iterate over ports and find domain paris
+        // Iterate over ports and find domain pairs
         for (auto port : topological_order) {
             auto &pd = ports.at(port);
             for (auto &arr : pd.arrival)
@@ -370,6 +406,8 @@ void TimingAnalyser::identify_related_domains()
     // Identify possible drivers for each clock domain
     dict<IdString, dict<IdString, delay_t>> clock_drivers;
     for (const auto &domain : domains) {
+        if (domain.key.is_async())
+            continue;
 
         const NetInfo *ni = ctx->nets.at(domain.key.clock).get();
         if (ni == nullptr)
@@ -613,6 +651,8 @@ void TimingAnalyser::print_fmax()
         auto &pd = ports.at(p);
         for (auto &req : pd.required) {
             if (pd.arrival.count(req.first)) {
+                if (domains.at(req.first).key.is_async())
+                    continue;
                 auto &arr = pd.arrival.at(req.first);
                 double fmax = 1000.0 / ctx->getDelayNS(arr.value.maxDelay() - req.second.value.minDelay());
                 if (!domain_fmax.count(req.first) || domain_fmax.at(req.first) > fmax)
@@ -670,6 +710,10 @@ void TimingAnalyser::compute_criticality()
         auto &pd = ports.at(p);
         for (auto &pdp : pd.domain_pairs) {
             auto &dp = domain_pairs.at(pdp.first);
+            // Do not set criticality for asynchronous paths
+            if (domains.at(dp.key.launch).key.is_async() || domains.at(dp.key.capture).key.is_async())
+                continue;
+
             float crit =
                     1.0f - (float(pdp.second.setup_slack) - float(dp.worst_setup_slack)) / float(-dp.worst_setup_slack);
             crit = std::min(crit, 1.0f);
@@ -728,8 +772,9 @@ void TimingAnalyser::print_report()
         auto &dp = domain_pairs.at(i);
         auto &launch = domains.at(dp.key.launch);
         auto &capture = domains.at(dp.key.capture);
-        log("Worst endpoints for %s %s -> %s %s\n", edge_name(launch.key.edge), ctx->nameOf(launch.key.clock),
-            edge_name(capture.key.edge), ctx->nameOf(capture.key.clock));
+
+        log("Worst endpoints for %s -> %s\n", clock_event_name(ctx, launch.key).c_str(),
+            clock_event_name(ctx, capture.key).c_str());
         auto failing_eps = get_failing_eps(i, 5);
         for (auto &ep : failing_eps)
             print_critical_path(ep, i);
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 6c7a696c8d..3f47fd6e79 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -73,7 +73,7 @@ struct ClockDomainPairKey
 struct TimingAnalyser
 {
   public:
-    TimingAnalyser(Context *ctx) : ctx(ctx){};
+    TimingAnalyser(Context *ctx);
     void setup();
     void run(bool update_route_delays = true);
     void print_report();
@@ -157,7 +157,9 @@ struct TimingAnalyser
             COMBINATIONAL,
             SETUP,
             HOLD,
-            CLK_TO_Q
+            CLK_TO_Q,
+            STARTPOINT,
+            ENDPOINT,
         } type;
 
         IdString other_port;
@@ -224,6 +226,8 @@ struct TimingAnalyser
 
     std::vector<CellPortKey> topological_order;
 
+    domain_id_t async_clock_id;
+
     Context *ctx;
 };
 

From 0f947ee693b9afe4787efe9c145de7e533fa44de Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Mon, 12 Jun 2023 10:25:01 +0200
Subject: [PATCH 394/712] Timing: Fix combinational paths through all ports
 (#1175)

Fixes https://github.com/YosysHQ/nextpnr/issues/1174
---
 common/kernel/timing.cc | 48 +++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7888e34a2f..df159c7913 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -113,23 +113,21 @@ void TimingAnalyser::get_cell_delays()
                                               info.edge);
                 }
             }
-            // Combinational delays through cell
-            else if (cls == TMG_COMB_INPUT) {
-                for (auto &other_port : ci->ports) {
-                    auto &op = other_port.second;
-                    // ignore dangling ports and non-outputs
-                    if (op.net == nullptr || op.type != PORT_OUT)
-                        continue;
-                    DelayQuad delay;
-                    bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
-                    if (is_path)
-                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
-                }
-            }
             // asynchronous endpoint
             else if (cls == TMG_ENDPOINT) {
                 pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {});
             }
+            // Combinational delays through cell
+            for (auto &other_port : ci->ports) {
+                auto &op = other_port.second;
+                // ignore dangling ports and non-outputs
+                if (op.net == nullptr || op.type != PORT_OUT)
+                    continue;
+                DelayQuad delay;
+                bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
+                if (is_path)
+                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            }
         } else if (pi.type == PORT_OUT) {
             // Output ports might have clk-to-q relationships
             if (cls == TMG_REGISTER_OUTPUT) {
@@ -140,23 +138,21 @@ void TimingAnalyser::get_cell_delays()
                     pd.cell_arcs.emplace_back(CellArc::CLK_TO_Q, info.clock_port, info.clockToQ, info.edge);
                 }
             }
-            // Combinational delays through cell
-            else if (cls == TMG_COMB_OUTPUT) {
-                for (auto &other_port : ci->ports) {
-                    auto &op = other_port.second;
-                    // ignore dangling ports and non-inputs
-                    if (op.net == nullptr || op.type != PORT_IN)
-                        continue;
-                    DelayQuad delay;
-                    bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
-                    if (is_path)
-                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
-                }
-            }
             // Asynchronous startpoint
             else if (cls == TMG_STARTPOINT) {
                 pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {});
             }
+            // Combinational delays through cell
+            for (auto &other_port : ci->ports) {
+                auto &op = other_port.second;
+                // ignore dangling ports and non-inputs
+                if (op.net == nullptr || op.type != PORT_IN)
+                    continue;
+                DelayQuad delay;
+                bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
+                if (is_path)
+                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            }
         }
     }
 }

From cb4846a58d5a7f718fdc05e00d1cd22f15427a77 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 7 Jun 2023 17:11:39 +0200
Subject: [PATCH 395/712] build: push INSTALL_PREFIX from env to cmake var

---
 ecp5/CMakeLists.txt  | 8 +++++++-
 ice40/CMakeLists.txt | 2 ++
 nexus/CMakeLists.txt | 7 ++++++-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/ecp5/CMakeLists.txt b/ecp5/CMakeLists.txt
index 115e0ce896..758b7f903f 100644
--- a/ecp5/CMakeLists.txt
+++ b/ecp5/CMakeLists.txt
@@ -21,7 +21,13 @@ else()
         message(STATUS "Trellis program prefix: ${TRELLIS_PROGRAM_PREFIX}")
     endif()
 
-    set(TRELLIS_INSTALL_PREFIX ${CMAKE_INSTALL_PREFIX} CACHE STRING
+    IF(DEFINED ENV{TRELLIS_INSTALL_PREFIX})
+        set(trellis_default_install_prefix $ENV{TRELLIS_INSTALL_PREFIX})
+    ELSE()
+        set(trellis_default_install_prefix ${CMAKE_INSTALL_PREFIX})
+    ENDIF()
+
+    set(TRELLIS_INSTALL_PREFIX ${trellis_default_install_prefix} CACHE STRING
         "Trellis install prefix")
     message(STATUS "Trellis install prefix: ${TRELLIS_INSTALL_PREFIX}")
 
diff --git a/ice40/CMakeLists.txt b/ice40/CMakeLists.txt
index 3bdfa26de2..7d18097c90 100644
--- a/ice40/CMakeLists.txt
+++ b/ice40/CMakeLists.txt
@@ -22,6 +22,8 @@ else()
         get_filename_component(dir ${ICEBOX_ROOT} DIRECTORY)
         get_filename_component(dir ${dir} DIRECTORY)
         set(icestorm_default_install_prefix ${dir})
+    elseif(DEFINED ENV{ICESTORM_INSTALL_PREFIX})
+        set(icestorm_default_install_prefix $ENV{ICESTORM_INSTALL_PREFIX})
     endif()
     set(ICESTORM_INSTALL_PREFIX ${icestorm_default_install_prefix} CACHE STRING
         "IceStorm install prefix")
diff --git a/nexus/CMakeLists.txt b/nexus/CMakeLists.txt
index d58bd6892a..22e785f74b 100644
--- a/nexus/CMakeLists.txt
+++ b/nexus/CMakeLists.txt
@@ -13,7 +13,12 @@ if(DEFINED NEXUS_CHIPDB)
     add_custom_target(chipdb-nexus-bbas ALL)
 else()
     # shared among all families
-    set(OXIDE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}" CACHE STRING
+    IF(DEFINED ENV{OXIDE_INSTALL_PREFIX})
+        set(oxide_default_install_prefix $ENV{OXIDE_INSTALL_PREFIX})
+    ELSE()
+        set(oxide_default_install_prefix ${CMAKE_INSTALL_PREFIX})
+    ENDIF()
+    set(OXIDE_INSTALL_PREFIX "${oxide_default_install_prefix}" CACHE STRING
         "prjoxide install prefix")
     message(STATUS "prjoxide install prefix: ${OXIDE_INSTALL_PREFIX}")
 

From 8a79a3522c2d31bfa1b7c972cbbdd06ac726d14a Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 7 Jun 2023 17:12:17 +0200
Subject: [PATCH 396/712] build: Flatten include dirs when building comp db

---
 CMakeLists.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index b2e8f00693..09eb818730 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -6,6 +6,14 @@ include(CheckCXXCompilerFlag)
 # Allow family.cmake add additional dependencies to gui_${family}.
 cmake_policy(SET CMP0079 NEW)
 
+# We want to explictly include all include directories when generating the
+# compilation database as not all clang/gcc share the same implicit includes
+# leading to essentially non-working compile_commands.json
+if(CMAKE_EXPORT_COMPILE_COMMANDS)
+  set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES 
+      ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
+endif()
+
 # Enable IPO support.
 cmake_policy(SET CMP0069 NEW)
 include(CheckIPOSupported)

From 68a2b2710f8283e603ed4c6eec2b0c95790fc286 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 7 Jun 2023 17:17:44 +0200
Subject: [PATCH 397/712] Add nix shell

---
 shell.nix | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 shell.nix

diff --git a/shell.nix b/shell.nix
new file mode 100644
index 0000000000..084e318092
--- /dev/null
+++ b/shell.nix
@@ -0,0 +1,48 @@
+{ pkgs ? import (fetchTarball https://github.com/NixOS/nixpkgs/archive/23.05.tar.gz) {} }:
+
+let
+  pythonPkgs = pkgs.python3Packages;
+  boostPython = pkgs.boost.override { python = pythonPkgs.python; enablePython = true; };
+  vscode = pkgs.vscode-with-extensions.override {
+    vscodeExtensions = with pkgs.vscode-extensions; [
+      bbenoist.nix
+      ms-vscode.cpptools
+      ms-vscode.cmake-tools
+      twxs.cmake
+      usernamehw.errorlens
+      llvm-vs-code-extensions.vscode-clangd
+    ] ++ pkgs.vscode-utils.extensionsFromVscodeMarketplace [
+      {
+        name = "VerilogHDL";
+        publisher = "mshr-h";
+        version = "1.11.4";
+        sha256 = "sha256-4JY0eaN2IkwHv8u8X6ejDXk6vT1qB4vJjWdIy8b/jj4=";
+      }
+    ];
+  };
+in pkgs.mkShell {
+  buildInputs = with pkgs; [
+    cmake
+    eigen
+    boostPython
+    pythonPkgs.python
+    pythonPkgs.apycula
+    libsForQt5.qt5.qtbase
+    llvmPackages.openmp
+    icestorm
+    trellis
+    mold
+    yosys
+    clang
+    valgrind
+    cling
+    gdb
+    vscode
+  ];
+
+  shellHook = ''
+    export TRELLIS_INSTALL_PREFIX=${pkgs.trellis}
+    export ICESTORM_INSTALL_PREFIX=${pkgs.icestorm}
+    export QT_QPA_PLATFORM_PLUGIN_PATH="${pkgs.libsForQt5.qt5.qtbase.bin}/lib/qt-${pkgs.libsForQt5.qt5.qtbase.version}/plugins";
+  '';
+}

From 863ad4cee865a0b66c66b7204216c9879f5673e9 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 7 Jun 2023 17:18:56 +0200
Subject: [PATCH 398/712] Add .cache used by clangd to gitignore

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 1c6e2034b9..7051a9c0f4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@
 /nextpnr-fpga_interchange*
 /nextpnr-gowin*
 /nextpnr-machxo2*
+.cache
 cmake-build-*/
 Makefile
 cmake_install.cmake

From 8935c1867f25732bb2a5a060a618d57a54e44e6e Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 13 Jun 2023 00:47:07 +0100
Subject: [PATCH 399/712] router2: revisit nodes with lower cost

---
 common/route/router2.cc | 51 ++++++++++++++++++++++-------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index bed8041e2c..2981454d9a 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -94,6 +94,7 @@ struct Router2
         // Visit data
         PipId pip_fwd, pip_bwd;
         bool visited_fwd = false, visited_bwd = false;
+        float cost_fwd = 0.0, cost_bwd = 0.0;
     };
 
     Context *ctx;
@@ -522,6 +523,8 @@ struct Router2
             flat_wires[w].pip_bwd = PipId();
             flat_wires[w].visited_fwd = false;
             flat_wires[w].visited_bwd = false;
+            flat_wires[w].cost_fwd = 0.0;
+            flat_wires[w].cost_bwd = 0.0;
         }
         t.dirty_wires.clear();
     }
@@ -559,25 +562,27 @@ struct Router2
     }
 
     // Functions for marking wires as visited, and checking if they have already been visited
-    void set_visited_fwd(ThreadContext &t, int wire, PipId pip)
+    void set_visited_fwd(ThreadContext &t, int wire, PipId pip, float cost)
     {
         auto &wd = flat_wires.at(wire);
         if (!wd.visited_fwd && !wd.visited_bwd)
             t.dirty_wires.push_back(wire);
         wd.pip_fwd = pip;
         wd.visited_fwd = true;
+        wd.cost_fwd = cost;
     }
-    void set_visited_bwd(ThreadContext &t, int wire, PipId pip)
+    void set_visited_bwd(ThreadContext &t, int wire, PipId pip, float cost)
     {
         auto &wd = flat_wires.at(wire);
         if (!wd.visited_fwd && !wd.visited_bwd)
             t.dirty_wires.push_back(wire);
         wd.pip_bwd = pip;
         wd.visited_bwd = true;
+        wd.cost_bwd = cost;
     }
 
-    bool was_visited_fwd(int wire) { return flat_wires.at(wire).visited_fwd; }
-    bool was_visited_bwd(int wire) { return flat_wires.at(wire).visited_bwd; }
+    bool was_visited_fwd(int wire, float cost) { return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; }
+    bool was_visited_bwd(int wire, float cost) { return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; }
 
     float get_arc_crit(NetInfo *net, store_index<PortRef> i)
     {
@@ -652,7 +657,7 @@ struct Router2
                 int wire_idx = wire_to_idx.at(wire);
                 base_score.togo_cost = get_togo_cost(net, i, wire_idx, dst_wire, false, crit_weight);
                 t.fwd_queue.push(QueuedWire(wire_idx, base_score));
-                set_visited_fwd(t, wire_idx, PipId());
+                set_visited_fwd(t, wire_idx, PipId(), 0.0);
             };
             auto &dst_data = flat_wires.at(dst_wire_idx);
             // Look for nearby existing routing
@@ -674,7 +679,7 @@ struct Router2
                 // Seed forwards with the source wire, if less than 8 existing wires added
                 seed_queue_fwd(src_wire);
             } else {
-                set_visited_fwd(t, src_wire_idx, PipId());
+                set_visited_fwd(t, src_wire_idx, PipId(), 0.0);
             }
             auto seed_queue_bwd = [&](WireId wire) {
                 WireScore base_score;
@@ -682,7 +687,7 @@ struct Router2
                 int wire_idx = wire_to_idx.at(wire);
                 base_score.togo_cost = get_togo_cost(net, i, wire_idx, src_wire, true, crit_weight);
                 t.bwd_queue.push(QueuedWire(wire_idx, base_score));
-                set_visited_bwd(t, wire_idx, PipId());
+                set_visited_bwd(t, wire_idx, PipId(), 0.0);
             };
 
             // Seed backwards with the dest wire
@@ -701,7 +706,7 @@ struct Router2
                     auto curr = t.fwd_queue.top();
                     t.fwd_queue.pop();
                     ++explored;
-                    if (was_visited_bwd(curr.wire)) {
+                    if (was_visited_bwd(curr.wire, FLT_MAX)) {
                         // Meet in the middle; done
                         midpoint_wire = curr.wire;
                         break;
@@ -715,7 +720,11 @@ struct Router2
                             continue;
                         WireId next = ctx->getPipDstWire(dh);
                         int next_idx = wire_to_idx.at(next);
-                        if (was_visited_fwd(next_idx)) {
+                        WireScore next_score;
+                        next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, dh, crit_weight);
+                        next_score.togo_cost =
+                                cfg.estimate_weight * get_togo_cost(net, i, next_idx, dst_wire, false, crit_weight);
+                        if (was_visited_fwd(next_idx, next_score.cost)) {
                             // Don't expand the same node twice.
                             continue;
                         }
@@ -731,11 +740,7 @@ struct Router2
                             continue;
                         if (!thread_test_wire(t, nwd))
                             continue; // thread safety issue
-                        WireScore next_score;
-                        next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, dh, crit_weight);
-                        next_score.togo_cost =
-                                cfg.estimate_weight * get_togo_cost(net, i, next_idx, dst_wire, false, crit_weight);
-                        set_visited_fwd(t, next_idx, dh);
+                        set_visited_fwd(t, next_idx, dh, next_score.cost);
                         t.fwd_queue.push(QueuedWire(next_idx, next_score, t.rng.rng()));
                     }
                 }
@@ -744,7 +749,7 @@ struct Router2
                     auto curr = t.bwd_queue.top();
                     t.bwd_queue.pop();
                     ++explored;
-                    if (was_visited_fwd(curr.wire)) {
+                    if (was_visited_fwd(curr.wire, FLT_MAX)) {
                         // Meet in the middle; done
                         midpoint_wire = curr.wire;
                         break;
@@ -765,7 +770,11 @@ struct Router2
                             continue;
                         WireId next = ctx->getPipSrcWire(uh);
                         int next_idx = wire_to_idx.at(next);
-                        if (was_visited_bwd(next_idx)) {
+                        WireScore next_score;
+                        next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
+                        next_score.togo_cost =
+                                cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
+                        if (was_visited_bwd(next_idx, next_score.cost)) {
                             // Don't expand the same node twice.
                             continue;
                         }
@@ -777,11 +786,7 @@ struct Router2
                             continue;
                         if (!thread_test_wire(t, nwd))
                             continue; // thread safety issue
-                        WireScore next_score;
-                        next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
-                        next_score.togo_cost =
-                                cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
-                        set_visited_bwd(t, next_idx, uh);
+                        set_visited_bwd(t, next_idx, uh, next_score.cost);
                         t.bwd_queue.push(QueuedWire(next_idx, next_score, t.rng.rng()));
                     }
                 }
@@ -793,7 +798,7 @@ struct Router2
         if (midpoint_wire != -1) {
             ROUTE_LOG_DBG("   Routed (explored %d wires): ", explored);
             int cursor_bwd = midpoint_wire;
-            while (was_visited_fwd(cursor_bwd)) {
+            while (was_visited_fwd(cursor_bwd, FLT_MAX)) {
                 PipId pip = flat_wires.at(cursor_bwd).pip_fwd;
                 if (pip == PipId() && cursor_bwd != src_wire_idx)
                     break;
@@ -832,7 +837,7 @@ struct Router2
             NPNR_ASSERT(cursor_bwd == src_wire_idx);
 
             int cursor_fwd = midpoint_wire;
-            while (was_visited_bwd(cursor_fwd)) {
+            while (was_visited_bwd(cursor_fwd, FLT_MAX)) {
                 PipId pip = flat_wires.at(cursor_fwd).pip_bwd;
                 if (pip == PipId()) {
                     break;

From 71a6b99633cde46c90baf91018a5a175bfafe39d Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 13 Jun 2023 01:06:48 +0100
Subject: [PATCH 400/712] router2: revisit nodes with lower delay

---
 common/route/router2.cc | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index 2981454d9a..4641205f07 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -73,6 +73,7 @@ struct Router2
 
     struct WireScore
     {
+        float delay;
         float cost;
         float togo_cost;
         float total() const { return cost + togo_cost; }
@@ -651,9 +652,10 @@ struct Router2
             ROUTE_LOG_DBG("src_wire = %s -> dst_wire = %s\n", ctx->nameOfWire(src_wire), ctx->nameOfWire(dst_wire));
 
             // Add 'forward' direction startpoints to queue
-            auto seed_queue_fwd = [&](WireId wire, float wire_cost = 0) {
+            auto seed_queue_fwd = [&](WireId wire) {
                 WireScore base_score;
-                base_score.cost = wire_cost;
+                base_score.delay = 0;
+                base_score.cost = 0;
                 int wire_idx = wire_to_idx.at(wire);
                 base_score.togo_cost = get_togo_cost(net, i, wire_idx, dst_wire, false, crit_weight);
                 t.fwd_queue.push(QueuedWire(wire_idx, base_score));
@@ -683,6 +685,7 @@ struct Router2
             }
             auto seed_queue_bwd = [&](WireId wire) {
                 WireScore base_score;
+                base_score.delay = 0;
                 base_score.cost = 0;
                 int wire_idx = wire_to_idx.at(wire);
                 base_score.togo_cost = get_togo_cost(net, i, wire_idx, src_wire, true, crit_weight);
@@ -721,10 +724,11 @@ struct Router2
                         WireId next = ctx->getPipDstWire(dh);
                         int next_idx = wire_to_idx.at(next);
                         WireScore next_score;
+                        next_score.delay = curr.score.delay + cfg.get_base_cost(ctx, next, dh, crit_weight);
                         next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, dh, crit_weight);
                         next_score.togo_cost =
                                 cfg.estimate_weight * get_togo_cost(net, i, next_idx, dst_wire, false, crit_weight);
-                        if (was_visited_fwd(next_idx, next_score.cost)) {
+                        if (was_visited_fwd(next_idx, next_score.delay)) {
                             // Don't expand the same node twice.
                             continue;
                         }
@@ -740,7 +744,7 @@ struct Router2
                             continue;
                         if (!thread_test_wire(t, nwd))
                             continue; // thread safety issue
-                        set_visited_fwd(t, next_idx, dh, next_score.cost);
+                        set_visited_fwd(t, next_idx, dh, next_score.delay);
                         t.fwd_queue.push(QueuedWire(next_idx, next_score, t.rng.rng()));
                     }
                 }
@@ -771,10 +775,11 @@ struct Router2
                         WireId next = ctx->getPipSrcWire(uh);
                         int next_idx = wire_to_idx.at(next);
                         WireScore next_score;
+                        next_score.delay = curr.score.delay + cfg.get_base_cost(ctx, next, uh, crit_weight);
                         next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
                         next_score.togo_cost =
                                 cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
-                        if (was_visited_bwd(next_idx, next_score.cost)) {
+                        if (was_visited_bwd(next_idx, next_score.delay)) {
                             // Don't expand the same node twice.
                             continue;
                         }
@@ -786,7 +791,7 @@ struct Router2
                             continue;
                         if (!thread_test_wire(t, nwd))
                             continue; // thread safety issue
-                        set_visited_bwd(t, next_idx, uh, next_score.cost);
+                        set_visited_bwd(t, next_idx, uh, next_score.delay);
                         t.bwd_queue.push(QueuedWire(next_idx, next_score, t.rng.rng()));
                     }
                 }

From 787fac764921c587e94d55d58d30049eeb86ab2a Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 14 Jun 2023 03:19:42 +0100
Subject: [PATCH 401/712] router2: fix 8935c186

---
 common/route/router2.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index 4641205f07..ba48f1b437 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -31,6 +31,7 @@
 #include <algorithm>
 #include <boost/container/flat_map.hpp>
 #include <chrono>
+#include <cmath>
 #include <deque>
 #include <fstream>
 #include <queue>

From bbe9ea9d650a9ae57be42dcef6a35292f8ade5ba Mon Sep 17 00:00:00 2001
From: Meinhard Kissich <privat@meinhard-kissich.at>
Date: Thu, 15 Jun 2023 19:49:48 +0200
Subject: [PATCH 402/712] gowin: fixes default networks

---
 gowin/pack.cc | 42 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index d316d66c9b..ae0da403e3 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -636,7 +636,45 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
             CellInfo *uc = user.cell;
             if (ctx->verbose)
                 log_info("%s user %s\n", ctx->nameOf(orig), ctx->nameOf(uc));
-            if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
+
+            if ((is_lut(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
+                auto it_param = uc->params.find(id_INIT);
+                if (it_param == uc->params.end())
+                    log_error("No initialization for lut found.\n");
+                
+                int64_t uc_init = it_param->second.intval;
+                int64_t mask = 0;
+                uint8_t amt = 0;
+
+                if (user.port == id_I0) {
+                    mask = 0x5555;
+                    amt = 1;
+                } else if (user.port == id_I1) {
+                    mask = 0x3333;
+                    amt = 2;
+                } else if (user.port == id_I2) {
+                    mask = 0x0F0F;
+                    amt = 4;
+                } else if (user.port == id_I3) {
+                    mask = 0x00FF;
+                    amt = 8;
+                } else {
+                    log_error("Port number invalid.\n");
+                }
+
+                if ((constnet->name == ctx->id("$PACKER_GND_NET"))) {
+                    uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
+                } else {
+                    uc_init = (uc_init & (mask<<amt)) | ((uc_init & (mask<<amt)) >> amt);  
+                }
+
+                size_t uc_init_len = it_param->second.to_string().length();
+                uc_init &= (1LL << uc_init_len) - 1;
+
+                if (ctx->verbose)
+                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, uc_init);
+
+                it_param->second = Property(uc_init, uc_init_len); 
                 uc->ports[user.port].net = nullptr;
                 uc->ports[user.port].user_idx = {};
             } else {
@@ -679,7 +717,7 @@ static void pack_constants(Context *ctx)
             ctx->cells.erase(drv_cell);
         } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, vcc_net.get(), true);
+            set_net_constant(ctx, ni, vcc_net.get(), false);
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
         }

From 6c0b4443d5fbcdc0d33db3b38e031a65174c6019 Mon Sep 17 00:00:00 2001
From: Meinhard Kissich <privat@meinhard-kissich.at>
Date: Thu, 15 Jun 2023 20:38:37 +0200
Subject: [PATCH 403/712] Removes unnecessary argument

---
 gowin/pack.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index ae0da403e3..5e481196d7 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -628,7 +628,7 @@ static void pack_nonlut_ffs(Context *ctx)
 }
 
 // Merge a net into a constant net
-static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
+static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet)
 {
     orig->driver.cell = nullptr;
     for (auto user : orig->users) {
@@ -637,7 +637,7 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
             if (ctx->verbose)
                 log_info("%s user %s\n", ctx->nameOf(orig), ctx->nameOf(uc));
 
-            if ((is_lut(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
+            if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I')) {
                 auto it_param = uc->params.find(id_INIT);
                 if (it_param == uc->params.end())
                     log_error("No initialization for lut found.\n");
@@ -711,13 +711,13 @@ static void pack_constants(Context *ctx)
         NetInfo *ni = net.second.get();
         if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
             IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, gnd_net.get(), false);
+            set_net_constant(ctx, ni, gnd_net.get());
             gnd_used = true;
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
         } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
             IdString drv_cell = ni->driver.cell->name;
-            set_net_constant(ctx, ni, vcc_net.get(), false);
+            set_net_constant(ctx, ni, vcc_net.get());
             dead_nets.push_back(net.first);
             ctx->cells.erase(drv_cell);
         }

From cbd6496d35127b447f2db5d42c2d99558c9cfa38 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 19 Jun 2023 11:19:42 +0100
Subject: [PATCH 404/712] router2: fix 8935c186 (again)

---
 common/route/router2.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index ba48f1b437..17eef7006b 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -31,9 +31,9 @@
 #include <algorithm>
 #include <boost/container/flat_map.hpp>
 #include <chrono>
-#include <cmath>
 #include <deque>
 #include <fstream>
+#include <limits>
 #include <queue>
 #include <set>
 
@@ -710,7 +710,7 @@ struct Router2
                     auto curr = t.fwd_queue.top();
                     t.fwd_queue.pop();
                     ++explored;
-                    if (was_visited_bwd(curr.wire, FLT_MAX)) {
+                    if (was_visited_bwd(curr.wire, std::numeric_limits<float>::max())) {
                         // Meet in the middle; done
                         midpoint_wire = curr.wire;
                         break;
@@ -754,7 +754,7 @@ struct Router2
                     auto curr = t.bwd_queue.top();
                     t.bwd_queue.pop();
                     ++explored;
-                    if (was_visited_fwd(curr.wire, FLT_MAX)) {
+                    if (was_visited_fwd(curr.wire, std::numeric_limits<float>::max())) {
                         // Meet in the middle; done
                         midpoint_wire = curr.wire;
                         break;
@@ -804,7 +804,7 @@ struct Router2
         if (midpoint_wire != -1) {
             ROUTE_LOG_DBG("   Routed (explored %d wires): ", explored);
             int cursor_bwd = midpoint_wire;
-            while (was_visited_fwd(cursor_bwd, FLT_MAX)) {
+            while (was_visited_fwd(cursor_bwd, std::numeric_limits<float>::max())) {
                 PipId pip = flat_wires.at(cursor_bwd).pip_fwd;
                 if (pip == PipId() && cursor_bwd != src_wire_idx)
                     break;
@@ -843,7 +843,7 @@ struct Router2
             NPNR_ASSERT(cursor_bwd == src_wire_idx);
 
             int cursor_fwd = midpoint_wire;
-            while (was_visited_bwd(cursor_fwd, FLT_MAX)) {
+            while (was_visited_bwd(cursor_fwd, std::numeric_limits<float>::max())) {
                 PipId pip = flat_wires.at(cursor_fwd).pip_bwd;
                 if (pip == PipId()) {
                     break;

From 1260f2f7d7deba283f7c775c6aab8899925b0cf8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 17 Jun 2023 20:31:04 +1000
Subject: [PATCH 405/712] gowin: Add support for GW2A series chips

* Limited to Tangprimer 20k or GW2A-LV18PG256C8/I7 chip.
* Clock lines are disabled.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 gowin/CMakeLists.txt |  2 +-
 gowin/main.cc        | 30 ++++++++++++++++++++++--------
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/gowin/CMakeLists.txt b/gowin/CMakeLists.txt
index ab6f4ee42e..92ff1c0859 100644
--- a/gowin/CMakeLists.txt
+++ b/gowin/CMakeLists.txt
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 project(chipdb-gowin NONE)
 
-set(ALL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-2 GW1NS-4)
+set(ALL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-2 GW1NS-4 GW2A-18)
 set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
 message(STATUS "Enabled Gowin devices: ${GOWIN_DEVICES}")
diff --git a/gowin/main.cc b/gowin/main.cc
index ccf4d19027..15b1914d86 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -66,7 +66,9 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
     std::smatch match;
     std::string device = vm["device"].as<std::string>();
-    if (!std::regex_match(device, match, devicere)) {
+    bool GW2 = device == "GW2A-LV18PG256C8/I7";
+
+    if (!GW2 && !std::regex_match(device, match, devicere)) {
         log_error("Invalid device %s\n", device.c_str());
     }
     ArchArgs chipArgs;
@@ -74,14 +76,22 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     if (vm.count("family")) {
         chipArgs.family = vm["family"].as<std::string>();
     } else {
-        char buf[36];
-        // GW1N and GW1NR variants share the same database.
-        // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
-        // However, it appears that the S series with embedded ARM core are unique silicon.
-        snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
-        chipArgs.family = buf;
+        if (!GW2) {
+            char buf[36];
+            // GW1N and GW1NR variants share the same database.
+            // Most Gowin devices are a System in Package with some SDRAM wirebonded to a GPIO bank.
+            // However, it appears that the S series with embedded ARM core are unique silicon.
+            snprintf(buf, 36, "GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
+            chipArgs.family = buf;
+        } else {
+            chipArgs.family = "GW2A-18";
+        }
+    }
+    if (!GW2) {
+        chipArgs.partnumber = match[0];
+    } else {
+        chipArgs.partnumber = device;
     }
-    chipArgs.partnumber = match[0];
 
     auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
     // routing options
@@ -93,6 +103,10 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(dict<std::string, Pr
     if (vm.count("enable-auto-longwires")) {
         ctx->settings[ctx->id("arch.enable-auto-longwires")] = 1;
     }
+    // XXX disable clock lines for now
+    if (GW2) {
+        ctx->settings[ctx->id("arch.enable-globals")] = 0;
+    }
     return ctx;
 }
 

From 77afaf23a5547799a5e883f68d28034918dfa793 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 20 Jun 2023 05:13:29 +1000
Subject: [PATCH 406/712] gowin: use the correct version of apicula

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 72150bc6ae..ca97889957 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -18,7 +18,7 @@ jobs:
       TRELLIS_REVISION: f1e5710099313d2e1862d4ef2582293f6b7ee122
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
-      APYCULA_REVISION: 0.5.1a1
+      APYCULA_REVISION: 0.8.2a1
     steps:
     - uses: actions/checkout@v3
       with:

From 914999673cfb1d03f1751523c1381bd07d8cd5c4 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 11 May 2023 11:23:32 +0200
Subject: [PATCH 407/712] Rip out budgets

---
 common/kernel/arch_api.h      |  1 -
 common/kernel/base_arch.h     |  4 --
 common/kernel/command.cc      |  5 ---
 common/kernel/context.cc      |  2 -
 common/kernel/nextpnr_types.h |  5 ---
 common/kernel/pybindings.cc   |  2 -
 common/kernel/report.cc       |  6 +--
 common/kernel/timing.cc       | 85 ++++-------------------------------
 common/kernel/timing.h        |  4 --
 common/place/place_common.cc  |  2 +-
 common/place/placer1.cc       | 26 +++--------
 common/place/placer1.h        |  1 -
 common/route/router1.cc       |  1 -
 docs/archapi.md               |  8 ----
 docs/coding.md                |  2 -
 docs/python.md                |  2 -
 ecp5/arch.cc                  | 14 ------
 ecp5/arch.h                   |  1 -
 fpga_interchange/arch.cc      |  2 -
 fpga_interchange/arch.h       |  1 -
 generic/arch.cc               |  2 -
 generic/arch.h                |  1 -
 gowin/arch.cc                 |  2 -
 gowin/arch.h                  |  1 -
 gui/basewindow.cc             | 33 --------------
 gui/basewindow.h              |  3 --
 gui/designwidget.cc           |  2 -
 gui/gowin/mainwindow.cc       |  5 ---
 gui/worker.cc                 | 14 ------
 gui/worker.h                  |  4 --
 himbaechel/arch.h             |  4 --
 ice40/arch.cc                 | 41 -----------------
 ice40/arch.h                  |  1 -
 machxo2/arch.h                |  1 -
 mistral/arch.cc               |  2 -
 nexus/arch.cc                 |  4 --
 nexus/arch.h                  |  1 -
 37 files changed, 16 insertions(+), 279 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index c2de19e689..0bfaaf2dcb 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -116,7 +116,6 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual float getDelayNS(delay_t v) const = 0;
     virtual delay_t getDelayFromNS(float ns) const = 0;
     virtual uint32_t getDelayChecksum(delay_t v) const = 0;
-    virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
     virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
     virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const = 0;
     virtual bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const = 0;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 4da9498932..a27e261d1f 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -313,10 +313,6 @@ template <typename R> struct BaseArch : ArchAPI<R>
     };
 
     // Delay methods
-    virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override
-    {
-        return false;
-    }
     virtual bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override
     {
         return false;
diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 4619c00e58..6e94b3009f 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -171,7 +171,6 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("slack_redist_iter", po::value<int>(), "number of iterations between slack redistribution");
     general.add_options()("cstrweight", po::value<float>(), "placer weighting for relative constraint satisfaction");
     general.add_options()("starttemp", po::value<float>(), "placer SA start temperature");
-    general.add_options()("placer-budgets", "use budget rather than criticality in placer timing weights");
 
     general.add_options()("pack-only", "pack design only without placement or routing");
     general.add_options()("no-route", "process design without routing");
@@ -318,9 +317,6 @@ void CommandHandler::setupContext(Context *ctx)
         ctx->settings[ctx->id("placer1/startTemp")] = std::to_string(vm["starttemp"].as<float>());
     }
 
-    if (vm.count("placer-budgets")) {
-        ctx->settings[ctx->id("placer1/budgetBased")] = true;
-    }
     if (vm.count("freq")) {
         auto freq = vm["freq"].as<double>();
         if (freq > 0)
@@ -457,7 +453,6 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
             if (!ctx->pack() && !ctx->force)
                 log_error("Packing design failed.\n");
         }
-        assign_budget(ctx.get());
         ctx->check();
         print_utilisation(ctx.get());
 
diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index 7048be5987..b194675d4e 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -236,13 +236,11 @@ uint32_t Context::checksum() const
         if (ni.driver.cell)
             x = xorshift32(x + xorshift32(ni.driver.cell->name.index));
         x = xorshift32(x + xorshift32(ni.driver.port.index));
-        x = xorshift32(x + xorshift32(getDelayChecksum(ni.driver.budget)));
 
         for (auto &u : ni.users) {
             if (u.cell)
                 x = xorshift32(x + xorshift32(u.cell->name.index));
             x = xorshift32(x + xorshift32(u.port.index));
-            x = xorshift32(x + xorshift32(getDelayChecksum(u.budget)));
         }
 
         uint32_t attr_x_sum = 0;
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 2a9062fd2a..b7f1e0b081 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -75,7 +75,6 @@ struct PortRef
 {
     CellInfo *cell = nullptr;
     IdString port;
-    delay_t budget = 0;
 };
 
 // minimum and maximum delay
@@ -326,8 +325,6 @@ struct CriticalPath
         std::pair<IdString, IdString> to;
         // Segment delay
         delay_t delay;
-        // Segment budget (routing only)
-        delay_t budget;
     };
 
     // Clock pair
@@ -349,8 +346,6 @@ struct NetSinkTiming
     std::pair<IdString, IdString> cell_port;
     // Delay
     delay_t delay;
-    // Delay budget
-    delay_t budget;
 };
 
 struct TimingResult
diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index f738f081a2..cea9a8be67 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -239,8 +239,6 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
                                                                                                             "cell");
     readonly_wrapper<PortRef, decltype(&PortRef::port), &PortRef::port, conv_to_str<IdString>>::def_wrap(pr_cls,
                                                                                                          "port");
-    readonly_wrapper<PortRef, decltype(&PortRef::budget), &PortRef::budget, pass_through<delay_t>>::def_wrap(pr_cls,
-                                                                                                             "budget");
 
     auto pm_cls = py::class_<ContextualWrapper<PipMap &>>(m, "PipMap");
     readwrite_wrapper<PipMap &, decltype(&PipMap::pip), &PipMap::pip, conv_to_str<PipId>,
diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index 8f583b33e2..38cf9d0ab1 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -90,7 +90,6 @@ static Json::array report_critical_paths(const Context *ctx)
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
                 segmentJson["type"] = "routing";
                 segmentJson["net"] = segment.net.c_str(ctx);
-                segmentJson["budget"] = ctx->getDelayNS(segment.budget);
             }
 
             pathJson.push_back(segmentJson);
@@ -134,8 +133,7 @@ static Json::array report_detailed_net_timings(const Context *ctx)
             auto endpointJson = Json::object({{"cell", sink_timing.cell_port.first.c_str(ctx)},
                                               {"port", sink_timing.cell_port.second.c_str(ctx)},
                                               {"event", clock_event_name(ctx, sink_timing.clock_pair.end)},
-                                              {"delay", ctx->getDelayNS(sink_timing.delay)},
-                                              {"budget", ctx->getDelayNS(sink_timing.budget)}});
+                                              {"delay", ctx->getDelayNS(sink_timing.delay)}});
             endpointsJson.push_back(endpointJson);
         }
 
@@ -194,7 +192,6 @@ Report JSON structure:
           "type": <path segment type "clk-to-q", "source", "logic", "routing" or "setup">,
           "net": <net name (for routing only!)>,
           "delay": <segment delay [ns]>,
-          "budget": <segment delay budget [ns] (for routing only!)>,
         }
         ...
       ]
@@ -213,7 +210,6 @@ Report JSON structure:
           "port": <sink cell port name>,
           "event": <destination clock event name>,
           "delay": <delay [ns]>,
-          "budget": <delay budget [ns]>,
         }
         ...
       ]
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index df159c7913..6a6ac2c1df 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -36,7 +36,7 @@ std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
         value = "<async>";
     else
         value = (dom.edge == FALLING_EDGE ? "negedge " : "posedge ") + dom.clock.str(ctx);
-    
+
     return value;
 }
 } // namespace
@@ -501,7 +501,6 @@ void TimingAnalyser::reset_times()
             dp.second.hold_slack = std::numeric_limits<delay_t>::max();
             dp.second.max_path_length = 0;
             dp.second.criticality = 0;
-            dp.second.budget = 0;
         }
         port.second.worst_crit = 0;
         port.second.worst_setup_slack = std::numeric_limits<delay_t>::max();
@@ -1060,7 +1059,6 @@ struct Timing
                     if (portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || portClass == TMG_CLOCK_INPUT) {
                         // Skip
                     } else {
-                        auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
                         // Iterate over all output ports on the same cell as the sink
                         for (auto port : usr.cell->ports) {
                             if (port.second.type != PORT_OUT || !port.second.net)
@@ -1073,12 +1071,8 @@ struct Timing
                             auto &data = net_data[port.second.net][start_clk];
                             auto &arrival = data.max_arrival;
                             arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
-                            if (!budget_override) { // Do not increment path length if budget overridden since it
-                                                    // doesn't
-                                // require a share of the slack
-                                auto &path_length = data.max_path_length;
-                                path_length = std::max(path_length, net_length_plus_one);
-                            }
+                            auto &path_length = data.max_path_length;
+                            path_length = std::max(path_length, net_length_plus_one);
                         }
                     }
                 }
@@ -1102,7 +1096,6 @@ struct Timing
                 auto &net_min_remaining_budget = nd.min_remaining_budget;
                 for (auto &usr : net->users) {
                     auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
-                    auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
                     int port_clocks;
                     TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
                     if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
@@ -1133,8 +1126,7 @@ struct Timing
                             auto path_budget = period - endpoint_arrival;
 
                             if (update) {
-                                auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
-                                usr.budget = std::min(usr.budget, net_delay + budget_share);
+                                auto budget_share = path_budget / net_length_plus_one;
                                 net_min_remaining_budget =
                                         std::min(net_min_remaining_budget, path_budget - budget_share);
                             }
@@ -1156,7 +1148,6 @@ struct Timing
                                 sink_timing.clock_pair = clockPair;
                                 sink_timing.cell_port = std::make_pair(usr.cell->name, usr.port);
                                 sink_timing.delay = endpoint_arrival;
-                                sink_timing.budget = period;
 
                                 (*detailed_net_timings)[net->name].push_back(sink_timing);
                             }
@@ -1196,8 +1187,7 @@ struct Timing
                                 net_data.at(port.second.net).count(startdomain.first)) {
                                 auto path_budget =
                                         net_data.at(port.second.net).at(startdomain.first).min_remaining_budget;
-                                auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
-                                usr.budget = std::min(usr.budget, net_delay + budget_share);
+                                auto budget_share = path_budget / net_length_plus_one;
                                 net_min_remaining_budget =
                                         std::min(net_min_remaining_budget, path_budget - budget_share);
                             }
@@ -1265,64 +1255,8 @@ struct Timing
         }
         return min_slack;
     }
-
-    void assign_budget()
-    {
-        // Clear delays to a very high value first
-        for (auto &net : ctx->nets) {
-            for (auto &usr : net.second->users) {
-                usr.budget = std::numeric_limits<delay_t>::max();
-            }
-        }
-
-        walk_paths();
-    }
 };
 
-void assign_budget(Context *ctx, bool quiet)
-{
-    if (!quiet) {
-        log_break();
-        log_info("Annotating ports with timing budgets for target frequency %.2f MHz\n",
-                 ctx->setting<float>("target_freq") / 1e6);
-    }
-
-    Timing timing(ctx, ctx->setting<int>("slack_redist_iter") > 0 /* net_delays */, true /* update */);
-    timing.assign_budget();
-
-    if (!quiet || ctx->verbose) {
-        for (auto &net : ctx->nets) {
-            for (auto &user : net.second->users) {
-                // Post-update check
-                if (!ctx->setting<bool>("auto_freq") && user.budget < 0)
-                    log_info("port %s.%s, connected to net '%s', has negative "
-                             "timing budget of %fns\n",
-                             user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
-                             ctx->getDelayNS(user.budget));
-                else if (ctx->debug)
-                    log_info("port %s.%s, connected to net '%s', has "
-                             "timing budget of %fns\n",
-                             user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
-                             ctx->getDelayNS(user.budget));
-            }
-        }
-    }
-
-    // For slack redistribution, if user has not specified a frequency dynamically adjust the target frequency to be the
-    // currently achieved maximum
-    if (ctx->setting<bool>("auto_freq") && ctx->setting<int>("slack_redist_iter") > 0) {
-        delay_t default_slack = delay_t((1.0e9 / ctx->getDelayNS(1)) / ctx->setting<float>("target_freq"));
-        ctx->settings[ctx->id("target_freq")] =
-                std::to_string(1.0e9 / ctx->getDelayNS(default_slack - timing.min_slack));
-        if (ctx->verbose)
-            log_info("minimum slack for this assign = %.2f ns, target Fmax for next "
-                     "update = %.2f MHz\n",
-                     ctx->getDelayNS(timing.min_slack), ctx->setting<float>("target_freq") / 1e6);
-    }
-
-    if (!quiet)
-        log_info("Checksum: 0x%08x\n", ctx->checksum());
-}
 
 CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
 {
@@ -1378,7 +1312,6 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
         }
 
         seg_logic.delay = comb_delay.maxDelay();
-        seg_logic.budget = 0;
         seg_logic.from = std::make_pair(last_cell->name, last_port);
         seg_logic.to = std::make_pair(driver_cell->name, driver.port);
         seg_logic.net = IdString();
@@ -1389,7 +1322,6 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
         CriticalPath::Segment seg_route;
         seg_route.type = CriticalPath::Segment::Type::ROUTING;
         seg_route.delay = net_delay;
-        seg_route.budget = sink->budget;
         seg_route.from = std::make_pair(driver_cell->name, driver.port);
         seg_route.to = std::make_pair(sink_cell->name, sink->port);
         seg_route.net = net->name;
@@ -1408,7 +1340,6 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
         CriticalPath::Segment seg_logic;
         seg_logic.type = CriticalPath::Segment::Type::SETUP;
         seg_logic.delay = setup;
-        seg_logic.budget = 0;
         seg_logic.from = std::make_pair(last_cell->name, last_port);
         seg_logic.to = seg_logic.from;
         seg_logic.net = IdString();
@@ -1582,8 +1513,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                     auto driver_loc = ctx->getBelLocation(driver->bel);
                     auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                    log_info("%4.1f %4.1f    Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                             ctx->getDelayNS(total), segment.net.c_str(ctx), ctx->getDelayNS(segment.budget),
+                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
+                             ctx->getDelayNS(total), segment.net.c_str(ctx),
                              driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
                     log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
 
@@ -1594,7 +1525,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                         PortRef sink_ref;
                         sink_ref.cell = sink.get();
                         sink_ref.port = segment.to.second;
-                        sink_ref.budget = segment.budget;
 
                         auto driver_wire = ctx->getNetinfoSourceWire(net);
                         auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
@@ -1842,6 +1772,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
 
         results.detailed_net_timings = std::move(detailed_net_timings);
     }
+
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 3f47fd6e79..8b85af3393 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -143,7 +143,6 @@ struct TimingAnalyser
     struct PortDomainPairData
     {
         delay_t setup_slack = std::numeric_limits<delay_t>::max(), hold_slack = std::numeric_limits<delay_t>::max();
-        delay_t budget = std::numeric_limits<delay_t>::max();
         int max_path_length = 0;
         float criticality = 0;
     };
@@ -231,9 +230,6 @@ struct TimingAnalyser
     Context *ctx;
 };
 
-// Evenly redistribute the total path slack amongst all sinks on each path
-void assign_budget(Context *ctx, bool quiet = false);
-
 // Perform timing analysis and print out the fmax, and optionally the
 //    critical path
 void timing_analysis(Context *ctx, bool slack_histogram = true, bool print_fmax = true, bool print_path = false,
diff --git a/common/place/place_common.cc b/common/place/place_common.cc
index c2fc3b7db4..8218b9fedf 100644
--- a/common/place/place_common.cc
+++ b/common/place/place_common.cc
@@ -51,7 +51,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
             continue;
         if (timing_driven) {
             delay_t net_delay = ctx->predictArcDelay(net, load);
-            auto slack = load.budget - net_delay;
+            auto slack = -net_delay;
             if (slack < 0)
                 negative_slack += slack;
             worst_slack = std::min(slack, worst_slack);
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index e37d3daf45..df52471b1c 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -211,8 +211,6 @@ class SAPlacer
             if ((placed_cells - constr_placed_cells) % 500 != 0)
                 log_info("  initial placement placed %d/%d cells\n", int(placed_cells - constr_placed_cells),
                          int(autoplaced.size()));
-            if (cfg.budgetBased && cfg.slack_redist_iter > 0)
-                assign_budget(ctx);
             ctx->yield();
             auto iplace_end = std::chrono::high_resolution_clock::now();
             log_info("Initial placement time %.02fs\n",
@@ -240,8 +238,7 @@ class SAPlacer
 
         // Invoke timing analysis to obtain criticalities
         tmg.setup_only = true;
-        if (!cfg.budgetBased)
-            tmg.setup();
+        tmg.setup();
 
         // Calculate costs after initial placement
         setup_costs();
@@ -368,18 +365,12 @@ class SAPlacer
                     // temp = post_legalise_temp;
                     // diameter = std::min<int>(M, diameter * post_legalise_dia_scale);
                     ctx->shuffle(autoplaced);
-
-                    // Legalisation is a big change so force a slack redistribution here
-                    if (cfg.slack_redist_iter > 0 && cfg.budgetBased)
-                        assign_budget(ctx, true /* quiet */);
                 }
                 require_legal = false;
-            } else if (cfg.budgetBased && cfg.slack_redist_iter > 0 && iter % cfg.slack_redist_iter == 0) {
-                assign_budget(ctx, true /* quiet */);
             }
 
             // Invoke timing analysis to obtain criticalities
-            if (!cfg.budgetBased && cfg.timing_driven)
+            if (cfg.timing_driven)
                 tmg.run();
             // Need to rebuild costs after criticalities change
             setup_costs();
@@ -870,14 +861,10 @@ class SAPlacer
             return 0;
         if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
             return 0;
-        if (cfg.budgetBased) {
-            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
-            return std::min(10.0, std::exp(delay - ctx->getDelayNS(user.budget) / 10));
-        } else {
-            float crit = tmg.get_criticality(CellPortKey(user));
-            double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
-            return delay * std::pow(crit, crit_exp);
-        }
+        
+        float crit = tmg.get_criticality(CellPortKey(user));
+        double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
+        return delay * std::pow(crit, crit_exp);
     }
 
     // Set up the cost maps
@@ -1267,7 +1254,6 @@ Placer1Cfg::Placer1Cfg(Context *ctx)
     constraintWeight = ctx->setting<float>("placer1/constraintWeight", 10);
     netShareWeight = ctx->setting<float>("placer1/netShareWeight", 0);
     minBelsForGridPick = ctx->setting<int>("placer1/minBelsForGridPick", 64);
-    budgetBased = ctx->setting<bool>("placer1/budgetBased", false);
     startTemp = ctx->setting<float>("placer1/startTemp", 1);
     timingFanoutThresh = std::numeric_limits<int>::max();
     timing_driven = ctx->setting<bool>("timing_driven");
diff --git a/common/place/placer1.h b/common/place/placer1.h
index 9dfb0b0df5..7b65a1a50d 100644
--- a/common/place/placer1.h
+++ b/common/place/placer1.h
@@ -29,7 +29,6 @@ struct Placer1Cfg
     Placer1Cfg(Context *ctx);
     float constraintWeight, netShareWeight;
     int minBelsForGridPick;
-    bool budgetBased;
     float startTemp;
     int timingFanoutThresh;
     bool timing_driven;
diff --git a/common/route/router1.cc b/common/route/router1.cc
index 0f1f0fcfdd..e4b2937210 100644
--- a/common/route/router1.cc
+++ b/common/route/router1.cc
@@ -730,7 +730,6 @@ struct Router1
             log("  final route delay:   %8.2f\n", ctx->getDelayNS(visited[dst_wire].delay));
             log("  final route penalty: %8.2f\n", ctx->getDelayNS(visited[dst_wire].penalty));
             log("  final route bonus:   %8.2f\n", ctx->getDelayNS(visited[dst_wire].bonus));
-            log("  arc budget:      %12.2f\n", ctx->getDelayNS(net_info->users[user_idx].budget));
         }
 
         // bind resulting route (and maybe unroute other nets)
diff --git a/docs/archapi.md b/docs/archapi.md
index 062bd9467e..cde69a150c 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -545,12 +545,6 @@ Convert a real-world delay in nanoseconds to a `delay_t`.
 
 Convert a `delay_t` to an integer for checksum calculations.
 
-### bool getBudgetOverride(const NetInfo \*net\_info, const PortRef &sink, delay\_t &budget) const
-
-Overwrite or modify (in-place) the timing budget for a given arc. Returns a bool to indicate whether this was done.
-
-*BaseArch default: returns false*
-
 ### bool getArcDelayOverride(const NetInfo \*net_info, const PortRef &sink, DelayQuad &delay) const
 
 This allows an arch to provide a more precise method for calculating the delay for a routed arc than
@@ -763,5 +757,3 @@ Returns `true` if the cell **must** be placed according to the cluster; for exam
 Gets an exact placement of the cluster, with the root cell placed on or near `root_bel` (and always within the same tile). Returns false if no placement is viable, otherwise returns `true` and populates `placement` with a list of cells inside the cluster and bels they should be placed at.
 
 This approach of allowing architectures to define cluster placements enables easier handling of irregular fabrics than requiring strict and constant x, y and z offsets.
-
-
diff --git a/docs/coding.md b/docs/coding.md
index e25165ae03..4f4c098bb7 100644
--- a/docs/coding.md
+++ b/docs/coding.md
@@ -78,7 +78,6 @@ Placers might want to create their own indices of bels (for example, bels by typ
 As nextpnr allows arbitrary constraints on bels for more advanced packer-free flows and complex real-world architectures; placements must be checked for legality using `isBelLocationValid` (after placement) and the placement rejected if invalid. For analytical placement algorithms; after creating a spread-out AP solution the legality of placing each cell needs to be checked. In practice, the cost of this is fairly low as the architecture should ensure these functions are as fast as possible.
 
 There are several routes for timing information in the placer:
- - sink `PortRef`s have a `budget` value annotated by calling `assign_budget` which is an estimate of the maximum delay that an arc may have
  - sink ports can have a criticality (value between 0 and 1 where 1 is the critical path) associated with them by using `get_criticalities` and a `NetCriticalityMap`
  - `predictDelay` and its derivative `predictArcDelay` returns an estimated delay for a sink port based on placement information
 
@@ -98,4 +97,3 @@ together, see the "cellGroups" field.
 The job of the router is to ensure that the `wires` map for each net contains a complete routing tree; populated using the Arch functions to bind wires and pips. The ripup invariants in the [FAQ](faq.md) are important to bear in mind; as there may be complex constraints on the usage of wires and pips in some architectures.
 
 `estimateDelay` is intended for use as an A* metric to guide routing.
-
diff --git a/docs/python.md b/docs/python.md
index d850300d19..ea3eb9c4d6 100644
--- a/docs/python.md
+++ b/docs/python.md
@@ -38,7 +38,6 @@ There is a dictionary `ctx.nets` that provides access to all of the nets in a de
 A `PortRef` has three fields:
     - `cell`: a reference to the cell the port is on
     - `port`: the name of the port
-    - `budget`: the timing budget of the port
 
 ### Accessing cells
 
@@ -84,4 +83,3 @@ The value given to `setParam` and `setAttr` should be a string of `[01xz]*` for
 ## Constraints
 
 See the [constraints documentation](constraints.md)
-
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 11429eb46e..a0b2644ca5 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -582,19 +582,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
            (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
-{
-    if (net_info->driver.port == id_FCO && sink.port == id_FCI) {
-        budget = 0;
-        return true;
-    } else if (sink.port.in(id_FXA, id_FXB)) {
-        budget = 0;
-        return true;
-    } else {
-        return false;
-    }
-}
-
 delay_t Arch::getRipupDelayPenalty() const { return 400; }
 
 // -----------------------------------------------------------------------
@@ -653,7 +640,6 @@ bool Arch::route()
     setup_wire_locations();
     route_ecp5_globals(getCtx());
     assignArchInfo();
-    assign_budget(getCtx(), true);
 
     bool result;
     if (router == "router1") {
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 56ba3e7b51..9b1061ee90 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -975,7 +975,6 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v * 0.001; }
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     // -------------------------------------------------
 
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 5af07f043c..bf7e9ff108 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -763,8 +763,6 @@ BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
     return {x0, y0, x1, y1};
 }
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
-
 // -----------------------------------------------------------------------
 
 bool Arch::pack()
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 74473e63b8..caabe6a3ae 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -707,7 +707,6 @@ struct Arch : ArchAPI<ArchRanges>
     float getDelayNS(delay_t v) const final { return v * 0.001; }
     delay_t getDelayFromNS(float ns) const final { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const final { return v; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const final;
 
     bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const final
     {
diff --git a/generic/arch.cc b/generic/arch.cc
index 238fb9fc96..91be118a22 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -561,8 +561,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     return (dx + dy) * args.delayScale + args.delayOffset;
 }
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
-
 BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     if (uarch)
diff --git a/generic/arch.h b/generic/arch.h
index 40994ad093..f4977e1e19 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -323,7 +323,6 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayFromNS(float ns) const override { return ns; }
 
     uint32_t getDelayChecksum(delay_t v) const override { return 0; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 4a50a2cb4f..b69c6afc96 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2150,8 +2150,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     return (dx + dy) * args.delayScale + args.delayOffset;
 }
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
-
 BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     BoundingBox bb;
diff --git a/gowin/arch.h b/gowin/arch.h
index ff8905acbf..ee687c266d 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -456,7 +456,6 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayFromNS(float ns) const override { return ns; }
 
     uint32_t getDelayChecksum(delay_t v) const override { return 0; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
diff --git a/gui/basewindow.cc b/gui/basewindow.cc
index 2ebbe2b9b4..4ea88a138a 100644
--- a/gui/basewindow.cc
+++ b/gui/basewindow.cc
@@ -91,7 +91,6 @@ BaseMainWindow::BaseMainWindow(std::unique_ptr<Context> context, CommandHandler
     // Connect Worker
     connect(task, &TaskManager::log, this, &BaseMainWindow::writeInfo);
     connect(task, &TaskManager::pack_finished, this, &BaseMainWindow::pack_finished);
-    connect(task, &TaskManager::budget_finish, this, &BaseMainWindow::budget_finish);
     connect(task, &TaskManager::place_finished, this, &BaseMainWindow::place_finished);
     connect(task, &TaskManager::route_finished, this, &BaseMainWindow::route_finished);
     connect(task, &TaskManager::taskCanceled, this, &BaseMainWindow::taskCanceled);
@@ -178,12 +177,6 @@ void BaseMainWindow::createMenusAndBars()
     actionPack->setEnabled(false);
     connect(actionPack, &QAction::triggered, task, &TaskManager::pack);
 
-    actionAssignBudget = new QAction("Assign Budget", this);
-    actionAssignBudget->setIcon(QIcon(":/icons/resources/time_add.png"));
-    actionAssignBudget->setStatusTip("Assign timing budget for current design");
-    actionAssignBudget->setEnabled(false);
-    connect(actionAssignBudget, &QAction::triggered, this, &BaseMainWindow::budget);
-
     actionPlace = new QAction("Place", this);
     actionPlace->setIcon(QIcon(":/icons/resources/place.png"));
     actionPlace->setStatusTip("Place current design");
@@ -307,7 +300,6 @@ void BaseMainWindow::createMenusAndBars()
 
     // Add Design menu actions
     menuDesign->addAction(actionPack);
-    menuDesign->addAction(actionAssignBudget);
     menuDesign->addAction(actionPlace);
     menuDesign->addAction(actionRoute);
     menuDesign->addSeparator();
@@ -324,7 +316,6 @@ void BaseMainWindow::createMenusAndBars()
     mainActionBar->addAction(actionSaveJSON);
     mainActionBar->addSeparator();
     mainActionBar->addAction(actionPack);
-    mainActionBar->addAction(actionAssignBudget);
     mainActionBar->addAction(actionPlace);
     mainActionBar->addAction(actionRoute);
     mainActionBar->addAction(actionExecutePy);
@@ -471,17 +462,6 @@ void BaseMainWindow::pack_finished(bool status)
     }
 }
 
-void BaseMainWindow::budget_finish(bool status)
-{
-    disableActions();
-    if (status) {
-        log("Assigning timing budget successful.\n");
-        updateActions();
-    } else {
-        log("Assigning timing budget failed.\n");
-    }
-}
-
 void BaseMainWindow::place_finished(bool status)
 {
     disableActions();
@@ -524,24 +504,12 @@ void BaseMainWindow::taskPaused()
     actionStop->setEnabled(true);
 }
 
-void BaseMainWindow::budget()
-{
-    bool ok;
-    double freq = QInputDialog::getDouble(this, "Assign timing budget", "Frequency [MHz]:", 50, 0, 250, 2, &ok);
-    if (ok) {
-        freq *= 1e6;
-        timing_driven = true;
-        Q_EMIT task->budget(freq);
-    }
-}
-
 void BaseMainWindow::place() { Q_EMIT task->place(timing_driven); }
 
 void BaseMainWindow::disableActions()
 {
     actionLoadJSON->setEnabled(true);
     actionPack->setEnabled(false);
-    actionAssignBudget->setEnabled(false);
     actionPlace->setEnabled(false);
     actionRoute->setEnabled(false);
 
@@ -559,7 +527,6 @@ void BaseMainWindow::updateActions()
     if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
         actionPack->setEnabled(true);
     else if (ctx->settings.find(ctx->id("place")) == ctx->settings.end()) {
-        actionAssignBudget->setEnabled(true);
         actionPlace->setEnabled(true);
     } else if (ctx->settings.find(ctx->id("route")) == ctx->settings.end())
         actionRoute->setEnabled(true);
diff --git a/gui/basewindow.h b/gui/basewindow.h
index 4e3cdcb8cc..053bb8e6e6 100644
--- a/gui/basewindow.h
+++ b/gui/basewindow.h
@@ -69,13 +69,11 @@ class BaseMainWindow : public QMainWindow
 
     void open_json();
     void save_json();
-    void budget();
     void place();
 
     void execute_python();
 
     void pack_finished(bool status);
-    void budget_finish(bool status);
     void place_finished(bool status);
     void route_finished(bool status);
 
@@ -120,7 +118,6 @@ class BaseMainWindow : public QMainWindow
     QAction *actionSaveJSON;
 
     QAction *actionPack;
-    QAction *actionAssignBudget;
     QAction *actionPlace;
     QAction *actionRoute;
 
diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index 57591bbfe7..fb9086ddce 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -751,7 +751,6 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
 
         QtProperty *driverItem = addSubGroup(topItem, "Driver");
         addProperty(driverItem, QVariant::String, "Port", net->driver.port.c_str(ctx));
-        addProperty(driverItem, QVariant::Double, "Budget", net->driver.budget);
         if (net->driver.cell)
             addProperty(driverItem, QVariant::String, "Cell", net->driver.cell->name.c_str(ctx), ElementType::CELL);
         else
@@ -762,7 +761,6 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
             QtProperty *portItem = addSubGroup(usersItem, item.port.c_str(ctx));
 
             addProperty(portItem, QVariant::String, "Port", item.port.c_str(ctx));
-            addProperty(portItem, QVariant::Double, "Budget", item.budget);
             if (item.cell)
                 addProperty(portItem, QVariant::String, "Cell", item.cell->name.c_str(ctx), ElementType::CELL);
             else
diff --git a/gui/gowin/mainwindow.cc b/gui/gowin/mainwindow.cc
index 8593bb4be4..c7ba44ab60 100644
--- a/gui/gowin/mainwindow.cc
+++ b/gui/gowin/mainwindow.cc
@@ -74,9 +74,6 @@ void MainWindow::createMenu()
 
     menuDesign->addSeparator();
     menuDesign->addAction(actionLoadCST);
-
-    // XXX
-    actionAssignBudget->setEnabled(false);
 }
 
 void MainWindow::new_proj() {}
@@ -102,7 +99,5 @@ void MainWindow::onUpdateActions()
     if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
         actionLoadCST->setEnabled(false);
     }
-    // XXX
-    actionAssignBudget->setEnabled(false);
 }
 NEXTPNR_NAMESPACE_END
diff --git a/gui/worker.cc b/gui/worker.cc
index dacd9e6161..c71bddd327 100644
--- a/gui/worker.cc
+++ b/gui/worker.cc
@@ -64,18 +64,6 @@ void Worker::pack()
     }
 }
 
-void Worker::budget(double freq)
-{
-    Q_EMIT taskStarted();
-    try {
-        ctx->settings[ctx->id("target_freq")] = std::to_string(freq);
-        assign_budget(ctx);
-        Q_EMIT budget_finish(true);
-    } catch (WorkerInterruptionRequested) {
-        Q_EMIT taskCanceled();
-    }
-}
-
 void Worker::place(bool timing_driven)
 {
     Q_EMIT taskStarted();
@@ -105,7 +93,6 @@ TaskManager::TaskManager() : toTerminate(false), toPause(false)
     connect(&workerThread, &QThread::finished, worker, &QObject::deleteLater);
 
     connect(this, &TaskManager::pack, worker, &Worker::pack);
-    connect(this, &TaskManager::budget, worker, &Worker::budget);
     connect(this, &TaskManager::place, worker, &Worker::place);
     connect(this, &TaskManager::route, worker, &Worker::route);
 
@@ -113,7 +100,6 @@ TaskManager::TaskManager() : toTerminate(false), toPause(false)
 
     connect(worker, &Worker::log, this, &TaskManager::info);
     connect(worker, &Worker::pack_finished, this, &TaskManager::pack_finished);
-    connect(worker, &Worker::budget_finish, this, &TaskManager::budget_finish);
     connect(worker, &Worker::place_finished, this, &TaskManager::place_finished);
     connect(worker, &Worker::route_finished, this, &TaskManager::route_finished);
 
diff --git a/gui/worker.h b/gui/worker.h
index 176fc28aab..bb78772a56 100644
--- a/gui/worker.h
+++ b/gui/worker.h
@@ -36,13 +36,11 @@ class Worker : public QObject
   public Q_SLOTS:
     void newContext(Context *);
     void pack();
-    void budget(double freq);
     void place(bool timing_driven);
     void route();
   Q_SIGNALS:
     void log(const std::string &text);
     void pack_finished(bool status);
-    void budget_finish(bool status);
     void place_finished(bool status);
     void route_finished(bool status);
     void taskCanceled();
@@ -73,14 +71,12 @@ class TaskManager : public QObject
     void contextChanged(Context *ctx);
     void terminate();
     void pack();
-    void budget(double freq);
     void place(bool timing_driven);
     void route();
 
     // redirected signals
     void log(const std::string &text);
     void pack_finished(bool status);
-    void budget_finish(bool status);
     void place_finished(bool status);
     void route_finished(bool status);
     void taskCanceled();
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index e5a4541826..9a664b17e6 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -568,10 +568,6 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v * 0.001; }
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override
-    {
-        return false;
-    }
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override
     {
         return uarch->getRouteBoundingBox(src, dst);
diff --git a/ice40/arch.cc b/ice40/arch.cc
index e977008a02..28791b95fa 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -639,47 +639,6 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
-{
-    const auto &driver = net_info->driver;
-    if (driver.port == id_COUT) {
-        NPNR_ASSERT(sink.port.in(id_CIN, id_I3));
-        NPNR_ASSERT(driver.cell->constr_abs_z);
-        bool cin = sink.port == id_CIN;
-        bool same_y = driver.cell->constr_z < 7;
-        if (cin && same_y)
-            budget = 0;
-        else {
-            switch (args.type) {
-            case ArchArgs::HX8K:
-            case ArchArgs::HX4K:
-            case ArchArgs::HX1K:
-                budget = cin ? 190 : (same_y ? 260 : 560);
-                break;
-            case ArchArgs::LP384:
-            case ArchArgs::LP1K:
-            case ArchArgs::LP4K:
-            case ArchArgs::LP8K:
-                budget = cin ? 290 : (same_y ? 380 : 670);
-                break;
-            case ArchArgs::UP3K:
-            case ArchArgs::UP5K:
-            case ArchArgs::U1K:
-            case ArchArgs::U2K:
-            case ArchArgs::U4K:
-                budget = cin ? 560 : (same_y ? 660 : 1220);
-                break;
-            default:
-                log_error("Unsupported iCE40 chip type.\n");
-            }
-        }
-        return true;
-    }
-    return false;
-}
-
-// -----------------------------------------------------------------------
-
 bool Arch::place()
 {
     std::string placer = str_or_default(settings, id_placer, defaultPlacer);
diff --git a/ice40/arch.h b/ice40/arch.h
index d80d6f649e..e1009ddc5e 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -800,7 +800,6 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v * 0.001; }
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 855b39df70..4792c79db4 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -903,7 +903,6 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v; }
     delay_t getDelayFromNS(float ns) const override { return ns; }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    // bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
     // -------------------------------------------------
 
diff --git a/mistral/arch.cc b/mistral/arch.cc
index 7b8adfd4a7..9dd2e81bf0 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -484,8 +484,6 @@ bool Arch::place()
 
 bool Arch::route()
 {
-    assign_budget(getCtx(), true);
-
     lab_pre_route();
 
     route_globals();
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 4818906d05..e6ff2e13f4 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -700,8 +700,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
     return 100 * dist_x + 100 * dist_y + 250;
 }
 
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
-
 BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     BoundingBox bb;
@@ -811,8 +809,6 @@ float router2_base_cost(Context *ctx, WireId wire, PipId pip, float crit_weight)
 
 bool Arch::route()
 {
-    assign_budget(getCtx(), true);
-
     pre_routing();
 
     route_globals();
diff --git a/nexus/arch.h b/nexus/arch.h
index eb3059a59d..2cb8c08ee3 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1299,7 +1299,6 @@ struct Arch : BaseArch<ArchRanges>
     float getDelayNS(delay_t v) const override { return v * 0.001; }
     delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
-    bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
 
     // for better DSP bounding boxes

From 54b2045726fc3fe77857c05c81a5ab77e98ba851 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 20 Jun 2023 10:58:18 +0200
Subject: [PATCH 408/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/timing.cc | 16 ++++++++--------
 common/place/placer1.cc |  2 +-
 common/route/router2.cc | 10 ++++++++--
 gowin/pack.cc           |  9 +++++----
 mistral/delay.cc        |  3 +--
 mistral/pack.cc         | 12 ++++++++----
 6 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 6a6ac2c1df..6ef227dc41 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -30,7 +30,8 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
-std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
+std::string clock_event_name(const Context *ctx, ClockDomainKey &dom)
+{
     std::string value;
     if (dom.is_async())
         value = "<async>";
@@ -41,7 +42,8 @@ std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
 }
 } // namespace
 
-TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) {
+TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
+{
     ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE};
     domain_to_id.emplace(key, 0);
     domains.emplace_back(key);
@@ -115,7 +117,7 @@ void TimingAnalyser::get_cell_delays()
             }
             // asynchronous endpoint
             else if (cls == TMG_ENDPOINT) {
-                pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {});
+                pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad{});
             }
             // Combinational delays through cell
             for (auto &other_port : ci->ports) {
@@ -140,7 +142,7 @@ void TimingAnalyser::get_cell_delays()
             }
             // Asynchronous startpoint
             else if (cls == TMG_STARTPOINT) {
-                pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {});
+                pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad{});
             }
             // Combinational delays through cell
             for (auto &other_port : ci->ports) {
@@ -1257,7 +1259,6 @@ struct Timing
     }
 };
 
-
 CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
 {
 
@@ -1514,8 +1515,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                     auto sink_loc = ctx->getBelLocation(sink->bel);
 
                     log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                             ctx->getDelayNS(total), segment.net.c_str(ctx),
-                             driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
+                             ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
+                             sink_loc.y);
                     log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
 
                     const NetInfo *net = ctx->nets.at(segment.net).get();
@@ -1772,7 +1773,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
 
         results.detailed_net_timings = std::move(detailed_net_timings);
     }
-
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index df52471b1c..4ecf3a7707 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -861,7 +861,7 @@ class SAPlacer
             return 0;
         if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
             return 0;
-        
+
         float crit = tmg.get_criticality(CellPortKey(user));
         double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
         return delay * std::pow(crit, crit_exp);
diff --git a/common/route/router2.cc b/common/route/router2.cc
index 17eef7006b..a54c58c92a 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -583,8 +583,14 @@ struct Router2
         wd.cost_bwd = cost;
     }
 
-    bool was_visited_fwd(int wire, float cost) { return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; }
-    bool was_visited_bwd(int wire, float cost) { return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; }
+    bool was_visited_fwd(int wire, float cost)
+    {
+        return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost;
+    }
+    bool was_visited_bwd(int wire, float cost)
+    {
+        return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost;
+    }
 
     float get_arc_crit(NetInfo *net, store_index<PortRef> i)
     {
diff --git a/gowin/pack.cc b/gowin/pack.cc
index 5e481196d7..00b5fee253 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -641,7 +641,7 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 auto it_param = uc->params.find(id_INIT);
                 if (it_param == uc->params.end())
                     log_error("No initialization for lut found.\n");
-                
+
                 int64_t uc_init = it_param->second.intval;
                 int64_t mask = 0;
                 uint8_t amt = 0;
@@ -665,16 +665,17 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 if ((constnet->name == ctx->id("$PACKER_GND_NET"))) {
                     uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
                 } else {
-                    uc_init = (uc_init & (mask<<amt)) | ((uc_init & (mask<<amt)) >> amt);  
+                    uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
                 }
 
                 size_t uc_init_len = it_param->second.to_string().length();
                 uc_init &= (1LL << uc_init_len) - 1;
 
                 if (ctx->verbose)
-                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, uc_init);
+                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
+                             uc_init);
 
-                it_param->second = Property(uc_init, uc_init_len); 
+                it_param->second = Property(uc_init, uc_init_len);
                 uc->ports[user.port].net = nullptr;
                 uc->ports[user.port].user_idx = {};
             } else {
diff --git a/mistral/delay.cc b/mistral/delay.cc
index 19fa2237e8..1ef9be6bef 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -368,8 +368,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
             cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
                                                     inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL,
                                                     est, input_wave[1]);
-            if (input_wave[mistral::CycloneV::RF_RISE].empty() ||
-                    input_wave[mistral::CycloneV::RF_FALL].empty())
+            if (input_wave[mistral::CycloneV::RF_RISE].empty() || input_wave[mistral::CycloneV::RF_FALL].empty())
                 return false;
         }
 
diff --git a/mistral/pack.cc b/mistral/pack.cc
index c0a71e3312..a298c5d6a4 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -395,7 +395,8 @@ struct MistralPacker
             NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40);
             NPNR_ASSERT((1 << abits) * dbits <= 10240);
 
-            log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str());
+            log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits,
+                     ci->name.str(ctx).c_str());
 
             // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
 
@@ -425,8 +426,10 @@ struct MistralPacker
                 ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
             }
             for (int bit = bit_offset; bit < abits; bit++) {
-                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
-                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
+                ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {
+                        ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
+                ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {
+                        ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
             }
 
             // Data lines
@@ -475,7 +478,8 @@ struct MistralPacker
 
             if (dbits == 40)
                 for (int bit = bit_offset; bit < dbits; bit++)
-                    ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATABIN[%d]", bit - bit_offset));
+                    ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(
+                            ctx->idf("DATABIN[%d]", bit - bit_offset));
 
             // Read port
             if (dbits == 40)

From 679b662a2b870ef49779fd0c3698e6e9a356d9f0 Mon Sep 17 00:00:00 2001
From: Aki Van Ness <aki@lethalbit.net>
Date: Tue, 8 Aug 2023 07:43:48 -0700
Subject: [PATCH 409/712] Added a code of conduct, which was taken from the
 YosysHQ/yosys repo

---
 CODE_OF_CONDUCT | 72 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 CODE_OF_CONDUCT

diff --git a/CODE_OF_CONDUCT b/CODE_OF_CONDUCT
new file mode 100644
index 0000000000..d0bf6a907d
--- /dev/null
+++ b/CODE_OF_CONDUCT
@@ -0,0 +1,72 @@
+Contributor Covenant Code of Conduct
+
+Our Pledge
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our project and
+our community a harassment-free experience for everyone, regardless of age, body
+size, disability, ethnicity, gender identity and expression, level of experience,
+nationality, personal appearance, race, religion, or sexual identity and
+orientation.
+
+Our Standards
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+* Using welcoming and inclusive language
+* Being respectful of differing viewpoints and experiences
+* Gracefully accepting constructive criticism
+* Focusing on what is best for the community
+* Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+* The use of sexualized language or imagery and unwelcome sexual attention or
+  advances
+* Trolling, insulting/derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or electronic
+  address, without explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+Our Responsibilities
+
+Project maintainers are responsible for clarifying the standards of acceptable
+behavior and are expected to take appropriate and fair corrective action in
+response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit, or
+reject comments, commits, code, wiki edits, issues, and other contributions
+that are not aligned to this Code of Conduct, or to ban temporarily or
+permanently any contributor for other behaviors that they deem inappropriate,
+threatening, offensive, or harmful.
+
+Scope
+
+This Code of Conduct applies both within project spaces and in public spaces
+when an individual is representing the project or its community. Examples of
+representing a project or community include using an official project e-mail
+address, posting via an official social media account, or acting as an appointed
+representative at an online or offline event. Representation of a project may be
+further defined and clarified by project maintainers.
+
+Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported by contacting the project team at contact@yosyshq.com and/or
+gatecat@ds0.me. All complaints will be reviewed and investigated and
+will result in a response that is deemed necessary and appropriate to the
+circumstances. The project team is obligated to maintain confidentiality with
+regard to the reporter of an incident.  Further details of specific enforcement
+policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in good
+faith may face temporary or permanent repercussions as determined by other
+members of the project's leadership.
+
+Attribution
+
+This Code of Conduct is adapted from the Contributor Covenant, version 1.4,
+available at http://contributor-covenant.org/version/1/4/

From 83f65169a3fad10ee1781de526f12ee00bba805a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 May 2023 14:28:15 +0200
Subject: [PATCH 410/712] different oscilator for XO3D

---
 machxo2/bitstream.cc | 4 ++++
 machxo2/constids.inc | 3 +++
 machxo2/pack.cc      | 8 ++++----
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 652152bd4d..6ad03541f0 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -693,6 +693,10 @@ struct MachXO2Bitgen
                 std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH");
                 cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
+            } else if (ci->type == id_OSCJ) {
+                std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
+                cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCJ.MODE", "OSCJ");
+                cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCJ.NOM_FREQ", freq);
             } else if (ci->type == id_DCCA) {
                 write_dcc(ci);
             } else if (ci->type == id_DP8KC) {
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 6bc2b33f46..1401b840a8 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -649,3 +649,6 @@ X(RXDA4)
 X(RXDA5)
 X(RXDA6)
 X(RXDA7)
+
+X(OSCJ)
+X(OSCESB)
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 22ca51c475..b9cf6fe904 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1143,8 +1143,8 @@ class MachXO2Packer
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
                     set_constraint(ci, id_CLKOS3,
                                    simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
-                } else if (ci->type == id_OSCH) {
-                    static std::string const osch_freq[] = {
+                } else if (ci->type == id_OSCH || ci->type == id_OSCJ) {
+                    static std::string const osc_freq[] = {
                             "2.08",  "2.15",  "2.22",  "2.29",  "2.38",  "2.46",  "2.56",  "2.66",  "2.77",  "2.89",
                             "3.02",  "3.17",  "3.33",  "3.50",  "3.69",  "3.91",  "4.16",  "4.29",  "4.43",  "4.59",
                             "4.75",  "4.93",  "5.12",  "5.32",  "5.54",  "5.78",  "6.05",  "6.33",  "6.65",  "7.00",
@@ -1156,14 +1156,14 @@ class MachXO2Packer
                     std::string freq = str_or_default(ci->params, id_NOM_FREQ, "2.08");
                     bool found = false;
                     for (int i = 0; i < 64; i++) {
-                        if (osch_freq[i] == freq) {
+                        if (osc_freq[i] == freq) {
                             found = true;
                             set_constraint(ci, id_OSC, simple_clk_contraint(delay_t(1000.0 / std::stof(freq))));
                             break;
                         }
                     }
                     if (!found)
-                        log_error("Unsupported frequency '%s' on OSCH '%s'\n", freq.c_str(), ci->name.c_str(ctx));
+                        log_error("Unsupported frequency '%s' on %s '%s'\n", freq.c_str(), ci->type == id_OSCH ? "OSCH" : "OSCJ", ci->name.c_str(ctx));
                 }
             }
         }

From adacaf65f4d407172f2eae138a6757b6e2dc34a0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 25 May 2023 15:27:02 +0200
Subject: [PATCH 411/712] additional new constants

---
 machxo2/constids.inc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 1401b840a8..3abeab14f8 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -652,3 +652,17 @@ X(RXDA7)
 
 X(OSCJ)
 X(OSCESB)
+
+X(EFBB)
+X(TAMPERDET)
+X(TAMPERTYPE0)
+X(TAMPERTYPE1)
+X(TAMPERSRC0)
+X(TAMPERSRC1)
+X(TAMPERDETEN)
+X(TAMPERLOCKSRC)
+X(TAMPERDETCLK)
+
+X(RESEN)
+X(PULLUPEN)
+X(SLEWRATE)

From 053d89570fde0a8298375f5d83c1a2f7bb056ae8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 26 May 2023 13:13:41 +0200
Subject: [PATCH 412/712] Use type name directly

---
 machxo2/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index b9cf6fe904..e31d506620 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1163,7 +1163,7 @@ class MachXO2Packer
                         }
                     }
                     if (!found)
-                        log_error("Unsupported frequency '%s' on %s '%s'\n", freq.c_str(), ci->type == id_OSCH ? "OSCH" : "OSCJ", ci->name.c_str(ctx));
+                        log_error("Unsupported frequency '%s' on %s '%s'\n", freq.c_str(), ci->type.c_str(ctx), ci->name.c_str(ctx));
                 }
             }
         }

From 88714c54ec9cf556af0da7c6b5cb6ad0e9e30032 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 17 Aug 2023 11:42:29 +0200
Subject: [PATCH 413/712] ecp5: Fix TQFP144 package import

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/trellis_import.py | 62 ++++++++++++++++++++++++------------------
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 1554ea1a0c..11b6e94a65 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -242,11 +242,15 @@ def get_bel_index(ddrg, loc, name):
 packages = {}
 pindata = []
 
-def process_pio_db(ddrg, device):
-    piofile = path.join(database.get_db_root(), "ECP5", dev_names[device], "iodb.json")
+def process_pio_db(ddrg, device, package_filter=None):
+    piofile = path.join(database.get_db_root(), "ECP5", device, "iodb.json")
     with open(piofile, 'r') as f:
         piodb = json.load(f)
         for pkgname, pkgdata in sorted(piodb["packages"].items()):
+            if package_filter is not None and pkgname not in package_filter:
+                # we need to get the TQ144 package only out of the non-SERDES device
+                # everything else comes from the SERDES device
+                continue
             pins = []
             for name, pinloc in sorted(pkgdata.items()):
                 x = pinloc["col"]
@@ -257,30 +261,31 @@ def process_pio_db(ddrg, device):
                 if bel_idx is not None:
                     pins.append((name, loc, bel_idx))
             packages[pkgname] = pins
-        for metaitem in piodb["pio_metadata"]:
-            x = metaitem["col"]
-            y = metaitem["row"]
-            loc = pytrellis.Location(x, y)
-            pio = "PIO" + metaitem["pio"]
-            bank = metaitem["bank"]
-            if "function" in metaitem:
-                pinfunc = metaitem["function"]
-            else:
-                pinfunc = None
-            dqs = -1
-            if "dqs" in metaitem:
-                tdqs = metaitem["dqs"]
-                if tdqs[0] == "L":
-                    dqs = 0
-                elif tdqs[0] == "R":
-                    dqs = 2048
-                suffix_size = 0
-                while tdqs[-(suffix_size+1)].isdigit():
-                    suffix_size += 1
-                dqs |= int(tdqs[-suffix_size:])
-            bel_idx = get_bel_index(ddrg, loc, pio)
-            if bel_idx is not None:
-                pindata.append((loc, bel_idx, bank, pinfunc, dqs))
+        if package_filter is None:
+            for metaitem in piodb["pio_metadata"]:
+                x = metaitem["col"]
+                y = metaitem["row"]
+                loc = pytrellis.Location(x, y)
+                pio = "PIO" + metaitem["pio"]
+                bank = metaitem["bank"]
+                if "function" in metaitem:
+                    pinfunc = metaitem["function"]
+                else:
+                    pinfunc = None
+                dqs = -1
+                if "dqs" in metaitem:
+                    tdqs = metaitem["dqs"]
+                    if tdqs[0] == "L":
+                        dqs = 0
+                    elif tdqs[0] == "R":
+                        dqs = 2048
+                    suffix_size = 0
+                    while tdqs[-(suffix_size+1)].isdigit():
+                        suffix_size += 1
+                    dqs |= int(tdqs[-suffix_size:])
+                bel_idx = get_bel_index(ddrg, loc, pio)
+                if bel_idx is not None:
+                    pindata.append((loc, bel_idx, bank, pinfunc, dqs))
 
 global_data = {}
 quadrants = ["UL", "UR", "LL", "LR"]
@@ -690,7 +695,10 @@ def main():
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
     process_timing_data()
-    process_pio_db(ddrg, args.device)
+    process_pio_db(ddrg, dev_names[args.device])
+    # add TQFP144 package from non-SERDES device if appropriate
+    if args.device == "25k": process_pio_db(ddrg, "LFE5U-25F", {"TQFP144", })
+    if args.device == "45k": process_pio_db(ddrg, "LFE5U-45F", {"TQFP144", })
     process_loc_globals(chip)
     # print("{} unique location types".format(len(ddrg.locationTypes)))
     bba = write_database(args.device, chip, ddrg, "le")

From d9f009b57052d88fbcf244aa8286ea78f0fe08ff Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 11 May 2023 11:10:50 +0200
Subject: [PATCH 414/712] Split timing into old and new code

---
 common/kernel/timing.cc     | 953 ----------------------------------
 common/kernel/timing_old.cc | 983 ++++++++++++++++++++++++++++++++++++
 2 files changed, 983 insertions(+), 953 deletions(-)
 create mode 100644 common/kernel/timing_old.cc

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 6ef227dc41..1eb414d5db 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -822,957 +822,4 @@ CellInfo *TimingAnalyser::cell_info(const CellPortKey &key) { return ctx->cells.
 
 PortInfo &TimingAnalyser::port_info(const CellPortKey &key) { return ctx->cells.at(key.cell)->ports.at(key.port); }
 
-/** LEGACY CODE BEGIN **/
-
-typedef std::vector<const PortRef *> PortRefVector;
-typedef std::map<int, unsigned> DelayFrequency;
-
-struct CriticalPathData
-{
-    PortRefVector ports;
-    delay_t path_delay;
-    delay_t path_period;
-};
-
-typedef dict<ClockPair, CriticalPathData> CriticalPathDataMap;
-
-typedef dict<IdString, std::vector<NetSinkTiming>> DetailedNetTimings;
-
-struct Timing
-{
-    Context *ctx;
-    bool net_delays;
-    bool update;
-    delay_t min_slack;
-    CriticalPathDataMap *crit_path;
-    DelayFrequency *slack_histogram;
-    DetailedNetTimings *detailed_net_timings;
-    IdString async_clock;
-
-    struct TimingData
-    {
-        TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
-        TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
-        delay_t max_arrival;
-        unsigned max_path_length = 0;
-        delay_t min_remaining_budget;
-        bool false_startpoint = false;
-        std::vector<delay_t> min_required;
-        dict<ClockEvent, delay_t> arrival_time;
-    };
-
-    Timing(Context *ctx, bool net_delays, bool update, CriticalPathDataMap *crit_path = nullptr,
-           DelayFrequency *slack_histogram = nullptr, DetailedNetTimings *detailed_net_timings = nullptr)
-            : ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->setting<float>("target_freq")),
-              crit_path(crit_path), slack_histogram(slack_histogram), detailed_net_timings(detailed_net_timings),
-              async_clock(ctx->id("$async$"))
-    {
-    }
-
-    delay_t walk_paths()
-    {
-        const auto clk_period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
-
-        // First, compute the topological order of nets to walk through the circuit, assuming it is a _acyclic_ graph
-        // TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
-        std::vector<NetInfo *> topological_order;
-        dict<const NetInfo *, dict<ClockEvent, TimingData>, hash_ptr_ops> net_data;
-        // In lieu of deleting edges from the graph, simply count the number of fanins to each output port
-        dict<const PortInfo *, unsigned, hash_ptr_ops> port_fanin;
-
-        std::vector<IdString> input_ports;
-        std::vector<const PortInfo *> output_ports;
-
-        pool<IdString> ooc_port_nets;
-
-        // In out-of-context mode, top-level inputs look floating but aren't
-        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
-            for (auto &p : ctx->ports) {
-                if (p.second.type != PORT_IN || p.second.net == nullptr)
-                    continue;
-                ooc_port_nets.insert(p.second.net->name);
-            }
-        }
-
-        for (auto &cell : ctx->cells) {
-            input_ports.clear();
-            output_ports.clear();
-            for (auto &port : cell.second->ports) {
-                if (!port.second.net)
-                    continue;
-                if (port.second.type == PORT_OUT)
-                    output_ports.push_back(&port.second);
-                else
-                    input_ports.push_back(port.first);
-            }
-
-            for (auto o : output_ports) {
-                int clocks = 0;
-                TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clocks);
-                // If output port is influenced by a clock (e.g. FF output) then add it to the ordering as a timing
-                // start-point
-                if (portClass == TMG_REGISTER_OUTPUT) {
-                    topological_order.emplace_back(o->net);
-                    for (int i = 0; i < clocks; i++) {
-                        TimingClockingInfo clkInfo = ctx->getPortClockingInfo(cell.second.get(), o->name, i);
-                        const NetInfo *clknet = cell.second->getPort(clkInfo.clock_port);
-                        IdString clksig = clknet ? clknet->name : async_clock;
-                        net_data[o->net][ClockEvent{clksig, clknet ? clkInfo.edge : RISING_EDGE}] =
-                                TimingData{clkInfo.clockToQ.maxDelay()};
-                    }
-
-                } else {
-                    if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) {
-                        topological_order.emplace_back(o->net);
-                        TimingData td;
-                        td.false_startpoint = (portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE);
-                        td.max_arrival = 0;
-                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
-                    }
-
-                    // Don't analyse paths from a clock input to other pins - they will be considered by the
-                    // special-case handling register input/output class ports
-                    if (portClass == TMG_CLOCK_INPUT)
-                        continue;
-
-                    // Otherwise, for all driven input ports on this cell, if a timing arc exists between the input and
-                    // the current output port, increment fanin counter
-                    for (auto i : input_ports) {
-                        DelayQuad comb_delay;
-                        NetInfo *i_net = cell.second->ports[i].net;
-                        if (i_net->driver.cell == nullptr && !ooc_port_nets.count(i_net->name))
-                            continue;
-                        bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
-                        if (is_path)
-                            port_fanin[o]++;
-                    }
-                    // If there is no fanin, add the port as a false startpoint
-                    if (!port_fanin.count(o) && !net_data.count(o->net)) {
-                        topological_order.emplace_back(o->net);
-                        TimingData td;
-                        td.false_startpoint = true;
-                        td.max_arrival = 0;
-                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
-                    }
-                }
-            }
-        }
-
-        // In out-of-context mode, handle top-level ports correctly
-        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
-            for (auto &p : ctx->ports) {
-                if (p.second.type != PORT_IN || p.second.net == nullptr)
-                    continue;
-                topological_order.emplace_back(p.second.net);
-            }
-        }
-
-        std::deque<NetInfo *> queue(topological_order.begin(), topological_order.end());
-        // Now walk the design, from the start points identified previously, building up a topological order
-        while (!queue.empty()) {
-            const auto net = queue.front();
-            queue.pop_front();
-
-            for (auto &usr : net->users) {
-                int user_clocks;
-                TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, user_clocks);
-                if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
-                    continue;
-                for (auto &port : usr.cell->ports) {
-                    if (port.second.type != PORT_OUT || !port.second.net)
-                        continue;
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, port_clocks);
-
-                    // Skip if this is a clocked output (but allow non-clocked ones)
-                    if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
-                        portClass == TMG_GEN_CLOCK)
-                        continue;
-                    DelayQuad comb_delay;
-                    bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                    if (!is_path)
-                        continue;
-                    // Decrement the fanin count, and only add to topological order if all its fanins have already
-                    // been visited
-                    auto it = port_fanin.find(&port.second);
-                    if (it == port_fanin.end())
-                        log_error("Timing counted negative fanin count for port %s.%s (net %s), please report this "
-                                  "error.\n",
-                                  ctx->nameOf(usr.cell), ctx->nameOf(port.first), ctx->nameOf(port.second.net));
-                    if (--it->second == 0) {
-                        topological_order.emplace_back(port.second.net);
-                        queue.emplace_back(port.second.net);
-                        port_fanin.erase(it);
-                    }
-                }
-            }
-        }
-
-        // Sanity check to ensure that all ports where fanins were recorded were indeed visited
-        if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) {
-            for (auto fanin : port_fanin) {
-                NetInfo *net = fanin.first->net;
-                if (net != nullptr) {
-                    log_info("   remaining fanin includes %s (net %s)\n", fanin.first->name.c_str(ctx),
-                             net->name.c_str(ctx));
-                    if (net->driver.cell != nullptr)
-                        log_info("        driver = %s.%s\n", net->driver.cell->name.c_str(ctx),
-                                 net->driver.port.c_str(ctx));
-                    for (auto net_user : net->users)
-                        log_info("        user: %s.%s\n", net_user.cell->name.c_str(ctx), net_user.port.c_str(ctx));
-                } else {
-                    log_info("   remaining fanin includes %s (no net)\n", fanin.first->name.c_str(ctx));
-                }
-            }
-            if (ctx->force)
-                log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification "
-                            "of timing ports, etc.\n");
-            else
-                log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of "
-                          "timing ports, etc.\n");
-        }
-
-        // Go forwards topologically to find the maximum arrival time and max path length for each net
-        std::vector<ClockEvent> startdomains;
-        for (auto net : topological_order) {
-            if (!net_data.count(net))
-                continue;
-            // Updates later on might invalidate a reference taken here to net_data, so iterate over a list of domains
-            // instead
-            startdomains.clear();
-            {
-                auto &nd_map = net_data.at(net);
-                for (auto &startdomain : nd_map)
-                    startdomains.push_back(startdomain.first);
-            }
-            for (auto &start_clk : startdomains) {
-                auto &nd = net_data.at(net).at(start_clk);
-                if (nd.false_startpoint)
-                    continue;
-                const auto net_arrival = nd.max_arrival;
-                const auto net_length_plus_one = nd.max_path_length + 1;
-                nd.min_remaining_budget = clk_period;
-                for (auto &usr : net->users) {
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
-                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
-                    auto usr_arrival = net_arrival + net_delay;
-
-                    if (portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || portClass == TMG_CLOCK_INPUT) {
-                        // Skip
-                    } else {
-                        // Iterate over all output ports on the same cell as the sink
-                        for (auto port : usr.cell->ports) {
-                            if (port.second.type != PORT_OUT || !port.second.net)
-                                continue;
-                            DelayQuad comb_delay;
-                            // Look up delay through this path
-                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                            if (!is_path)
-                                continue;
-                            auto &data = net_data[port.second.net][start_clk];
-                            auto &arrival = data.max_arrival;
-                            arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
-                            auto &path_length = data.max_path_length;
-                            path_length = std::max(path_length, net_length_plus_one);
-                        }
-                    }
-                }
-            }
-        }
-
-        dict<ClockPair, std::pair<delay_t, NetInfo *>> crit_nets;
-
-        // Now go backwards topologically to determine the minimum path slack, and to distribute all path slack evenly
-        // between all nets on the path
-        for (auto net : boost::adaptors::reverse(topological_order)) {
-            if (!net_data.count(net))
-                continue;
-            auto &nd_map = net_data.at(net);
-            for (auto &startdomain : nd_map) {
-                auto &nd = startdomain.second;
-                // Ignore false startpoints
-                if (nd.false_startpoint)
-                    continue;
-                const delay_t net_length_plus_one = nd.max_path_length + 1;
-                auto &net_min_remaining_budget = nd.min_remaining_budget;
-                for (auto &usr : net->users) {
-                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
-                    if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
-                        auto process_endpoint = [&](IdString clksig, ClockEdge edge, delay_t setup) {
-                            const auto net_arrival = nd.max_arrival;
-                            const auto endpoint_arrival = net_arrival + net_delay + setup;
-                            delay_t period;
-                            // Set default period
-                            if (edge == startdomain.first.edge) {
-                                period = clk_period;
-                            } else {
-                                period = clk_period / 2;
-                            }
-                            if (clksig != async_clock) {
-                                if (ctx->nets.at(clksig)->clkconstr) {
-                                    if (edge == startdomain.first.edge) {
-                                        // same edge
-                                        period = ctx->nets.at(clksig)->clkconstr->period.minDelay();
-                                    } else if (edge == RISING_EDGE) {
-                                        // falling -> rising
-                                        period = ctx->nets.at(clksig)->clkconstr->low.minDelay();
-                                    } else if (edge == FALLING_EDGE) {
-                                        // rising -> falling
-                                        period = ctx->nets.at(clksig)->clkconstr->high.minDelay();
-                                    }
-                                }
-                            }
-                            auto path_budget = period - endpoint_arrival;
-
-                            if (update) {
-                                auto budget_share = path_budget / net_length_plus_one;
-                                net_min_remaining_budget =
-                                        std::min(net_min_remaining_budget, path_budget - budget_share);
-                            }
-
-                            if (path_budget < min_slack)
-                                min_slack = path_budget;
-
-                            if (slack_histogram) {
-                                int slack_ps = ctx->getDelayNS(path_budget) * 1000;
-                                (*slack_histogram)[slack_ps]++;
-                            }
-                            ClockEvent dest_ev{clksig, edge};
-                            ClockPair clockPair{startdomain.first, dest_ev};
-                            nd.arrival_time[dest_ev] = std::max(nd.arrival_time[dest_ev], endpoint_arrival);
-
-                            // Store the detailed timing for each net and user (a.k.a. sink)
-                            if (detailed_net_timings) {
-                                NetSinkTiming sink_timing;
-                                sink_timing.clock_pair = clockPair;
-                                sink_timing.cell_port = std::make_pair(usr.cell->name, usr.port);
-                                sink_timing.delay = endpoint_arrival;
-
-                                (*detailed_net_timings)[net->name].push_back(sink_timing);
-                            }
-
-                            if (crit_path) {
-                                if (!crit_nets.count(clockPair) || crit_nets.at(clockPair).first < endpoint_arrival) {
-                                    crit_nets[clockPair] = std::make_pair(endpoint_arrival, net);
-                                    (*crit_path)[clockPair].path_delay = endpoint_arrival;
-                                    (*crit_path)[clockPair].path_period = period;
-                                    (*crit_path)[clockPair].ports.clear();
-                                    (*crit_path)[clockPair].ports.push_back(&usr);
-                                }
-                            }
-                        };
-                        if (portClass == TMG_REGISTER_INPUT) {
-                            for (int i = 0; i < port_clocks; i++) {
-                                TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, i);
-                                const NetInfo *clknet = usr.cell->getPort(clkInfo.clock_port);
-                                IdString clksig = clknet ? clknet->name : async_clock;
-                                process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, clkInfo.setup.maxDelay());
-                            }
-                        } else {
-                            process_endpoint(async_clock, RISING_EDGE, 0);
-                        }
-
-                    } else if (update) {
-
-                        // Iterate over all output ports on the same cell as the sink
-                        for (const auto &port : usr.cell->ports) {
-                            if (port.second.type != PORT_OUT || !port.second.net)
-                                continue;
-                            DelayQuad comb_delay;
-                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                            if (!is_path)
-                                continue;
-                            if (net_data.count(port.second.net) &&
-                                net_data.at(port.second.net).count(startdomain.first)) {
-                                auto path_budget =
-                                        net_data.at(port.second.net).at(startdomain.first).min_remaining_budget;
-                                auto budget_share = path_budget / net_length_plus_one;
-                                net_min_remaining_budget =
-                                        std::min(net_min_remaining_budget, path_budget - budget_share);
-                            }
-                        }
-                    }
-                }
-            }
-        }
-
-        if (crit_path) {
-            // Walk backwards from the most critical net
-            for (auto crit_pair : crit_nets) {
-                NetInfo *crit_net = crit_pair.second.second;
-                auto &cp_ports = (*crit_path)[crit_pair.first].ports;
-                while (crit_net) {
-                    const PortInfo *crit_ipin = nullptr;
-                    delay_t max_arrival = std::numeric_limits<delay_t>::min();
-                    // Look at all input ports on its driving cell
-                    for (const auto &port : crit_net->driver.cell->ports) {
-                        if (port.second.type != PORT_IN || !port.second.net)
-                            continue;
-                        DelayQuad comb_delay;
-                        bool is_path =
-                                ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
-                        if (!is_path)
-                            continue;
-                        // If input port is influenced by a clock, skip
-                        int port_clocks;
-                        TimingPortClass portClass =
-                                ctx->getPortTimingClass(crit_net->driver.cell, port.first, port_clocks);
-                        if (portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE)
-                            continue;
-                        // And find the fanin net with the latest arrival time
-                        if (net_data.count(port.second.net) &&
-                            net_data.at(port.second.net).count(crit_pair.first.start)) {
-                            auto net_arrival = net_data.at(port.second.net).at(crit_pair.first.start).max_arrival;
-                            if (net_delays) {
-                                for (auto &user : port.second.net->users)
-                                    if (user.port == port.first && user.cell == crit_net->driver.cell) {
-                                        net_arrival += ctx->getNetinfoRouteDelay(port.second.net, user);
-                                        break;
-                                    }
-                            }
-                            net_arrival += comb_delay.maxDelay();
-                            if (net_arrival > max_arrival) {
-                                max_arrival = net_arrival;
-                                crit_ipin = &port.second;
-                            }
-                        }
-                    }
-
-                    if (!crit_ipin)
-                        break;
-                    // Now convert PortInfo* into a PortRef*
-                    for (auto &usr : crit_ipin->net->users) {
-                        if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
-                            cp_ports.push_back(&usr);
-                            break;
-                        }
-                    }
-                    crit_net = crit_ipin->net;
-                }
-                std::reverse(cp_ports.begin(), cp_ports.end());
-            }
-        }
-        return min_slack;
-    }
-};
-
-CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
-{
-
-    CriticalPath report;
-    report.clock_pair = clocks;
-
-    auto &front = crit_path.front();
-    auto &front_port = front->cell->ports.at(front->port);
-    auto &front_driver = front_port.net->driver;
-
-    int port_clocks;
-    auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
-
-    const CellInfo *last_cell = front->cell;
-    IdString last_port = front_driver.port;
-
-    int clock_start = -1;
-    if (portClass == TMG_REGISTER_OUTPUT) {
-        for (int i = 0; i < port_clocks; i++) {
-            TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
-            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
-            if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
-                last_port = clockInfo.clock_port;
-                clock_start = i;
-                break;
-            }
-        }
-    }
-
-    for (auto sink : crit_path) {
-        auto sink_cell = sink->cell;
-        auto &port = sink_cell->ports.at(sink->port);
-        auto net = port.net;
-        auto &driver = net->driver;
-        auto driver_cell = driver.cell;
-
-        CriticalPath::Segment seg_logic;
-
-        DelayQuad comb_delay;
-        if (clock_start != -1) {
-            auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
-            comb_delay = clockInfo.clockToQ;
-            clock_start = -1;
-            seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
-        } else if (last_port == driver.port) {
-            // Case where we start with a STARTPOINT etc
-            comb_delay = DelayQuad(0);
-            seg_logic.type = CriticalPath::Segment::Type::SOURCE;
-        } else {
-            ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
-            seg_logic.type = CriticalPath::Segment::Type::LOGIC;
-        }
-
-        seg_logic.delay = comb_delay.maxDelay();
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
-        seg_logic.to = std::make_pair(driver_cell->name, driver.port);
-        seg_logic.net = IdString();
-        report.segments.push_back(seg_logic);
-
-        auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
-
-        CriticalPath::Segment seg_route;
-        seg_route.type = CriticalPath::Segment::Type::ROUTING;
-        seg_route.delay = net_delay;
-        seg_route.from = std::make_pair(driver_cell->name, driver.port);
-        seg_route.to = std::make_pair(sink_cell->name, sink->port);
-        seg_route.net = net->name;
-        report.segments.push_back(seg_route);
-
-        last_cell = sink_cell;
-        last_port = sink->port;
-    }
-
-    int clockCount = 0;
-    auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
-    if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
-        auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
-        delay_t setup = sinkClockInfo.setup.maxDelay();
-
-        CriticalPath::Segment seg_logic;
-        seg_logic.type = CriticalPath::Segment::Type::SETUP;
-        seg_logic.delay = setup;
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
-        seg_logic.to = seg_logic.from;
-        seg_logic.net = IdString();
-        report.segments.push_back(seg_logic);
-    }
-
-    return report;
-}
-
-void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure,
-                     bool update_results)
-{
-    auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
-        std::string value;
-        if (e.clock == ctx->id("$async$"))
-            value = std::string("<async>");
-        else
-            value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
-        if (int(value.length()) < field_width)
-            value.insert(value.length(), field_width - int(value.length()), ' ');
-        return value;
-    };
-
-    CriticalPathDataMap crit_paths;
-    DelayFrequency slack_histogram;
-    DetailedNetTimings detailed_net_timings;
-
-    Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
-                  print_histogram ? &slack_histogram : nullptr,
-                  (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
-    timing.walk_paths();
-
-    // Use TimingAnalyser to determine clock-to-clock relations
-    TimingAnalyser timingAnalyser(ctx);
-    timingAnalyser.setup();
-
-    bool report_critical_paths = print_path || print_fmax || update_results;
-
-    dict<IdString, CriticalPath> clock_reports;
-    std::vector<CriticalPath> xclock_reports;
-    dict<IdString, ClockFmax> clock_fmax;
-    std::set<IdString> empty_clocks; // set of clocks with no interior paths
-
-    if (report_critical_paths) {
-
-        for (auto path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            empty_clocks.insert(a.clock);
-            empty_clocks.insert(b.clock);
-        }
-        for (auto path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            if (a.clock != b.clock || a.clock == ctx->id("$async$"))
-                continue;
-            double Fmax;
-            empty_clocks.erase(a.clock);
-            if (a.edge == b.edge)
-                Fmax = 1000 / ctx->getDelayNS(path.second.path_delay);
-            else
-                Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
-            if (!clock_fmax.count(a.clock) || Fmax < clock_fmax.at(a.clock).achieved) {
-                clock_fmax[a.clock].achieved = Fmax;
-                clock_fmax[a.clock].constraint = 0.0f; // Will be filled later
-                clock_reports[a.clock] = build_critical_path_report(ctx, path.first, path.second.ports);
-                clock_reports[a.clock].period = path.second.path_period;
-            }
-        }
-
-        for (auto &path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            if (a.clock == b.clock && a.clock != ctx->id("$async$"))
-                continue;
-
-            auto &crit_path = crit_paths.at(path.first).ports;
-            xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
-            xclock_reports.back().period = path.second.path_period;
-        }
-
-        if (clock_reports.empty() && xclock_reports.empty()) {
-            log_info("No Fmax available; no interior timing paths found in design.\n");
-        }
-
-        std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPath &ra, const CriticalPath &rb) {
-            const auto &a = ra.clock_pair;
-            const auto &b = rb.clock_pair;
-
-            if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
-                return true;
-            if (a.start.clock.str(ctx) > b.start.clock.str(ctx))
-                return false;
-            if (a.start.edge < b.start.edge)
-                return true;
-            if (a.start.edge > b.start.edge)
-                return false;
-            if (a.end.clock.str(ctx) < b.end.clock.str(ctx))
-                return true;
-            if (a.end.clock.str(ctx) > b.end.clock.str(ctx))
-                return false;
-            if (a.end.edge < b.end.edge)
-                return true;
-            return false;
-        });
-
-        for (auto &clock : clock_reports) {
-            float target = ctx->setting<float>("target_freq") / 1e6;
-            if (ctx->nets.at(clock.first)->clkconstr)
-                target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
-            clock_fmax[clock.first].constraint = target;
-        }
-    }
-
-    // Print critical paths
-    if (print_path) {
-
-        static auto print_net_source = [ctx](const NetInfo *net) {
-            // Check if this net is annotated with a source list
-            auto sources = net->attrs.find(ctx->id("src"));
-            if (sources == net->attrs.end()) {
-                // No sources for this net, can't print anything
-                return;
-            }
-
-            // Sources are separated by pipe characters.
-            // There is no guaranteed ordering on sources, so we just print all
-            auto sourcelist = sources->second.as_string();
-            std::vector<std::string> source_entries;
-            size_t current = 0, prev = 0;
-            while ((current = sourcelist.find("|", prev)) != std::string::npos) {
-                source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-                prev = current + 1;
-            }
-            // Ensure we emplace the final entry
-            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-
-            // Iterate and print our source list at the correct indentation level
-            log_info("               Defined in:\n");
-            for (auto entry : source_entries) {
-                log_info("                 %s\n", entry.c_str());
-            }
-        };
-
-        // A helper function for reporting one critical path
-        auto print_path_report = [ctx](const CriticalPath &path) {
-            delay_t total = 0, logic_total = 0, route_total = 0;
-
-            log_info("curr total\n");
-            for (const auto &segment : path.segments) {
-
-                total += segment.delay;
-
-                if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
-                    segment.type == CriticalPath::Segment::Type::SOURCE ||
-                    segment.type == CriticalPath::Segment::Type::LOGIC ||
-                    segment.type == CriticalPath::Segment::Type::SETUP) {
-                    logic_total += segment.delay;
-
-                    const std::string type_name =
-                            (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
-
-                    log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
-                             type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-                } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
-                    route_total += segment.delay;
-
-                    const auto &driver = ctx->cells.at(segment.from.first);
-                    const auto &sink = ctx->cells.at(segment.to.first);
-
-                    auto driver_loc = ctx->getBelLocation(driver->bel);
-                    auto sink_loc = ctx->getBelLocation(sink->bel);
-
-                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                             ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
-                             sink_loc.y);
-                    log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-
-                    const NetInfo *net = ctx->nets.at(segment.net).get();
-
-                    if (ctx->verbose) {
-
-                        PortRef sink_ref;
-                        sink_ref.cell = sink.get();
-                        sink_ref.port = segment.to.second;
-
-                        auto driver_wire = ctx->getNetinfoSourceWire(net);
-                        auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
-                        log_info("                 prediction: %f ns estimate: %f ns\n",
-                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
-                                 ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
-                        auto cursor = sink_wire;
-                        delay_t delay;
-                        while (driver_wire != cursor) {
-#ifdef ARCH_ECP5
-                            if (net->is_global)
-                                break;
-#endif
-                            auto it = net->wires.find(cursor);
-                            assert(it != net->wires.end());
-                            auto pip = it->second.pip;
-                            NPNR_ASSERT(pip != PipId());
-                            delay = ctx->getPipDelay(pip).maxDelay();
-                            log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
-                            cursor = ctx->getPipSrcWire(pip);
-                        }
-                    }
-
-                    if (!ctx->disable_critical_path_source_print) {
-                        print_net_source(net);
-                    }
-                }
-            }
-            log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
-        };
-
-        // Single domain paths
-        for (auto &clock : clock_reports) {
-            log_break();
-            std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
-                                                                                   : std::string("posedge");
-            std::string end =
-                    clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
-            log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
-                     end.c_str());
-            auto &report = clock.second;
-            print_path_report(report);
-        }
-
-        // Cross-domain paths
-        for (auto &report : xclock_reports) {
-            log_break();
-            std::string start = format_event(report.clock_pair.start);
-            std::string end = format_event(report.clock_pair.end);
-            log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
-            print_path_report(report);
-        }
-    }
-
-    if (print_fmax) {
-        log_break();
-
-        unsigned max_width = 0;
-        for (auto &clock : clock_reports)
-            max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
-
-        for (auto &clock : clock_reports) {
-            const auto &clock_name = clock.first.str(ctx);
-            const int width = max_width - clock_name.size();
-
-            float fmax = clock_fmax[clock.first].achieved;
-            float target = clock_fmax[clock.first].constraint;
-            bool passed = target < fmax;
-
-            if (!warn_on_failure || passed)
-                log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                         clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
-                log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                            clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else
-                log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                                   clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-        }
-        log_break();
-
-        // All clock to clock delays
-        const auto &clock_delays = timingAnalyser.get_clock_delays();
-
-        // Clock to clock delays for xpaths
-        dict<ClockPair, delay_t> xclock_delays;
-        for (auto &report : xclock_reports) {
-            const auto &clock1_name = report.clock_pair.start.clock;
-            const auto &clock2_name = report.clock_pair.end.clock;
-
-            const auto key = std::make_pair(clock1_name, clock2_name);
-            if (clock_delays.count(key)) {
-                xclock_delays[report.clock_pair] = clock_delays.at(key);
-            }
-        }
-
-        unsigned max_width_xca = 0;
-        unsigned max_width_xcb = 0;
-        for (auto &report : xclock_reports) {
-            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
-            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
-        }
-
-        // Check and report xpath delays for related clocks
-        if (!xclock_reports.empty()) {
-            for (auto &report : xclock_reports) {
-                const auto &clock_a = report.clock_pair.start.clock;
-                const auto &clock_b = report.clock_pair.end.clock;
-
-                const auto key = std::make_pair(clock_a, clock_b);
-                if (!clock_delays.count(key)) {
-                    continue;
-                }
-
-                delay_t path_delay = 0;
-                for (const auto &segment : report.segments) {
-                    path_delay += segment.delay;
-                }
-
-                // Compensate path delay for clock-to-clock delay. If the
-                // result is negative then only the latter matters. Otherwise
-                // the compensated path delay is taken.
-                auto clock_delay = clock_delays.at(key);
-                path_delay -= clock_delay;
-
-                float fmax = std::numeric_limits<float>::infinity();
-                if (path_delay < 0) {
-                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
-                } else if (path_delay > 0) {
-                    fmax = 1e3f / ctx->getDelayNS(path_delay);
-                }
-
-                // Both clocks are related so they should have the same
-                // frequency. However, they may get different constraints from
-                // user input. In case of only one constraint preset take it,
-                // otherwise get the worst case (min.)
-                float target;
-                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_a).constraint;
-                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_b).constraint;
-                } else {
-                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
-                }
-
-                bool passed = target < fmax;
-
-                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
-                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
-
-                if (!warn_on_failure || passed)
-                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
-                             fmax, passed ? "PASS" : "FAIL", target);
-                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
-                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
-                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-                else
-                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            }
-            log_break();
-        }
-
-        // Report clock delays for xpaths
-        if (!clock_delays.empty()) {
-            for (auto &pair : xclock_delays) {
-                auto ev_a = format_event(pair.first.start, max_width_xca);
-                auto ev_b = format_event(pair.first.end, max_width_xcb);
-
-                delay_t delay = pair.second;
-                if (pair.first.start.edge != pair.first.end.edge) {
-                    delay /= 2;
-                }
-
-                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
-                         ctx->getDelayNS(delay));
-            }
-
-            log_break();
-        }
-
-        for (auto &eclock : empty_clocks) {
-            if (eclock != ctx->id("$async$"))
-                log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
-        }
-        log_break();
-
-        int start_field_width = 0, end_field_width = 0;
-        for (auto &report : xclock_reports) {
-            start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
-            end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
-        }
-
-        for (auto &report : xclock_reports) {
-            const ClockEvent &a = report.clock_pair.start;
-            const ClockEvent &b = report.clock_pair.end;
-            delay_t path_delay = 0;
-            for (const auto &segment : report.segments) {
-                path_delay += segment.delay;
-            }
-            auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
-            log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
-        }
-        log_break();
-    }
-
-    if (print_histogram && slack_histogram.size() > 0) {
-        unsigned num_bins = 20;
-        unsigned bar_width = 60;
-        auto min_slack = slack_histogram.begin()->first;
-        auto max_slack = slack_histogram.rbegin()->first;
-        auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
-        std::vector<unsigned> bins(num_bins);
-        unsigned max_freq = 0;
-        for (const auto &i : slack_histogram) {
-            int bin_idx = int((i.first - min_slack) / bin_size);
-            if (bin_idx < 0)
-                bin_idx = 0;
-            else if (bin_idx >= int(num_bins))
-                bin_idx = num_bins - 1;
-            auto &bin = bins.at(bin_idx);
-            bin += i.second;
-            max_freq = std::max(max_freq, bin);
-        }
-        bar_width = std::min(bar_width, max_freq);
-
-        log_break();
-        log_info("Slack histogram:\n");
-        log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
-        log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
-        for (unsigned i = 0; i < num_bins; ++i)
-            log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
-                     std::string(bins[i] * bar_width / max_freq, '*').c_str(),
-                     (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
-    }
-
-    // Update timing results in the context
-    if (update_results) {
-        auto &results = ctx->timing_result;
-
-        results.clock_fmax = std::move(clock_fmax);
-        results.clock_paths = std::move(clock_reports);
-        results.xclock_paths = std::move(xclock_reports);
-
-        results.detailed_net_timings = std::move(detailed_net_timings);
-    }
-}
-
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
new file mode 100644
index 0000000000..49e6a53f32
--- /dev/null
+++ b/common/kernel/timing_old.cc
@@ -0,0 +1,983 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2018  Eddie Hung <eddieh@ece.ubc.ca>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "timing.h"
+#include <algorithm>
+#include <boost/range/adaptor/reversed.hpp>
+#include <deque>
+#include <map>
+#include <utility>
+#include "log.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+typedef std::vector<const PortRef *> PortRefVector;
+typedef std::map<int, unsigned> DelayFrequency;
+
+struct CriticalPathData
+{
+    PortRefVector ports;
+    delay_t path_delay;
+    delay_t path_period;
+};
+
+typedef dict<ClockPair, CriticalPathData> CriticalPathDataMap;
+
+typedef dict<IdString, std::vector<NetSinkTiming>> DetailedNetTimings;
+
+struct Timing
+{
+    Context *ctx;
+    bool net_delays;
+    bool update;
+    delay_t min_slack;
+    CriticalPathDataMap *crit_path;
+    DelayFrequency *slack_histogram;
+    DetailedNetTimings *detailed_net_timings;
+    IdString async_clock;
+
+    struct TimingData
+    {
+        TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
+        TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
+        delay_t max_arrival;
+        unsigned max_path_length = 0;
+        delay_t min_remaining_budget;
+        bool false_startpoint = false;
+        std::vector<delay_t> min_required;
+        dict<ClockEvent, delay_t> arrival_time;
+    };
+
+    Timing(Context *ctx, bool net_delays, bool update, CriticalPathDataMap *crit_path = nullptr,
+           DelayFrequency *slack_histogram = nullptr, DetailedNetTimings *detailed_net_timings = nullptr)
+            : ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->setting<float>("target_freq")),
+              crit_path(crit_path), slack_histogram(slack_histogram), detailed_net_timings(detailed_net_timings),
+              async_clock(ctx->id("$async$"))
+    {
+    }
+
+    delay_t walk_paths()
+    {
+        const auto clk_period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
+
+        // First, compute the topological order of nets to walk through the circuit, assuming it is a _acyclic_ graph
+        // TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
+        std::vector<NetInfo *> topological_order;
+        dict<const NetInfo *, dict<ClockEvent, TimingData>, hash_ptr_ops> net_data;
+        // In lieu of deleting edges from the graph, simply count the number of fanins to each output port
+        dict<const PortInfo *, unsigned, hash_ptr_ops> port_fanin;
+
+        std::vector<IdString> input_ports;
+        std::vector<const PortInfo *> output_ports;
+
+        pool<IdString> ooc_port_nets;
+
+        // In out-of-context mode, top-level inputs look floating but aren't
+        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
+            for (auto &p : ctx->ports) {
+                if (p.second.type != PORT_IN || p.second.net == nullptr)
+                    continue;
+                ooc_port_nets.insert(p.second.net->name);
+            }
+        }
+
+        for (auto &cell : ctx->cells) {
+            input_ports.clear();
+            output_ports.clear();
+            for (auto &port : cell.second->ports) {
+                if (!port.second.net)
+                    continue;
+                if (port.second.type == PORT_OUT)
+                    output_ports.push_back(&port.second);
+                else
+                    input_ports.push_back(port.first);
+            }
+
+            for (auto o : output_ports) {
+                int clocks = 0;
+                TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clocks);
+                // If output port is influenced by a clock (e.g. FF output) then add it to the ordering as a timing
+                // start-point
+                if (portClass == TMG_REGISTER_OUTPUT) {
+                    topological_order.emplace_back(o->net);
+                    for (int i = 0; i < clocks; i++) {
+                        TimingClockingInfo clkInfo = ctx->getPortClockingInfo(cell.second.get(), o->name, i);
+                        const NetInfo *clknet = cell.second->getPort(clkInfo.clock_port);
+                        IdString clksig = clknet ? clknet->name : async_clock;
+                        net_data[o->net][ClockEvent{clksig, clknet ? clkInfo.edge : RISING_EDGE}] =
+                                TimingData{clkInfo.clockToQ.maxDelay()};
+                    }
+
+                } else {
+                    if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) {
+                        topological_order.emplace_back(o->net);
+                        TimingData td;
+                        td.false_startpoint = (portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE);
+                        td.max_arrival = 0;
+                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
+                    }
+
+                    // Don't analyse paths from a clock input to other pins - they will be considered by the
+                    // special-case handling register input/output class ports
+                    if (portClass == TMG_CLOCK_INPUT)
+                        continue;
+
+                    // Otherwise, for all driven input ports on this cell, if a timing arc exists between the input and
+                    // the current output port, increment fanin counter
+                    for (auto i : input_ports) {
+                        DelayQuad comb_delay;
+                        NetInfo *i_net = cell.second->ports[i].net;
+                        if (i_net->driver.cell == nullptr && !ooc_port_nets.count(i_net->name))
+                            continue;
+                        bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
+                        if (is_path)
+                            port_fanin[o]++;
+                    }
+                    // If there is no fanin, add the port as a false startpoint
+                    if (!port_fanin.count(o) && !net_data.count(o->net)) {
+                        topological_order.emplace_back(o->net);
+                        TimingData td;
+                        td.false_startpoint = true;
+                        td.max_arrival = 0;
+                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
+                    }
+                }
+            }
+        }
+
+        // In out-of-context mode, handle top-level ports correctly
+        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
+            for (auto &p : ctx->ports) {
+                if (p.second.type != PORT_IN || p.second.net == nullptr)
+                    continue;
+                topological_order.emplace_back(p.second.net);
+            }
+        }
+
+        std::deque<NetInfo *> queue(topological_order.begin(), topological_order.end());
+        // Now walk the design, from the start points identified previously, building up a topological order
+        while (!queue.empty()) {
+            const auto net = queue.front();
+            queue.pop_front();
+
+            for (auto &usr : net->users) {
+                int user_clocks;
+                TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, user_clocks);
+                if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
+                    continue;
+                for (auto &port : usr.cell->ports) {
+                    if (port.second.type != PORT_OUT || !port.second.net)
+                        continue;
+                    int port_clocks;
+                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, port_clocks);
+
+                    // Skip if this is a clocked output (but allow non-clocked ones)
+                    if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
+                        portClass == TMG_GEN_CLOCK)
+                        continue;
+                    DelayQuad comb_delay;
+                    bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
+                    if (!is_path)
+                        continue;
+                    // Decrement the fanin count, and only add to topological order if all its fanins have already
+                    // been visited
+                    auto it = port_fanin.find(&port.second);
+                    if (it == port_fanin.end())
+                        log_error("Timing counted negative fanin count for port %s.%s (net %s), please report this "
+                                  "error.\n",
+                                  ctx->nameOf(usr.cell), ctx->nameOf(port.first), ctx->nameOf(port.second.net));
+                    if (--it->second == 0) {
+                        topological_order.emplace_back(port.second.net);
+                        queue.emplace_back(port.second.net);
+                        port_fanin.erase(it);
+                    }
+                }
+            }
+        }
+
+        // Sanity check to ensure that all ports where fanins were recorded were indeed visited
+        if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) {
+            for (auto fanin : port_fanin) {
+                NetInfo *net = fanin.first->net;
+                if (net != nullptr) {
+                    log_info("   remaining fanin includes %s (net %s)\n", fanin.first->name.c_str(ctx),
+                             net->name.c_str(ctx));
+                    if (net->driver.cell != nullptr)
+                        log_info("        driver = %s.%s\n", net->driver.cell->name.c_str(ctx),
+                                 net->driver.port.c_str(ctx));
+                    for (auto net_user : net->users)
+                        log_info("        user: %s.%s\n", net_user.cell->name.c_str(ctx), net_user.port.c_str(ctx));
+                } else {
+                    log_info("   remaining fanin includes %s (no net)\n", fanin.first->name.c_str(ctx));
+                }
+            }
+            if (ctx->force)
+                log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification "
+                            "of timing ports, etc.\n");
+            else
+                log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of "
+                          "timing ports, etc.\n");
+        }
+
+        // Go forwards topologically to find the maximum arrival time and max path length for each net
+        std::vector<ClockEvent> startdomains;
+        for (auto net : topological_order) {
+            if (!net_data.count(net))
+                continue;
+            // Updates later on might invalidate a reference taken here to net_data, so iterate over a list of domains
+            // instead
+            startdomains.clear();
+            {
+                auto &nd_map = net_data.at(net);
+                for (auto &startdomain : nd_map)
+                    startdomains.push_back(startdomain.first);
+            }
+            for (auto &start_clk : startdomains) {
+                auto &nd = net_data.at(net).at(start_clk);
+                if (nd.false_startpoint)
+                    continue;
+                const auto net_arrival = nd.max_arrival;
+                const auto net_length_plus_one = nd.max_path_length + 1;
+                nd.min_remaining_budget = clk_period;
+                for (auto &usr : net->users) {
+                    int port_clocks;
+                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
+                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
+                    auto usr_arrival = net_arrival + net_delay;
+
+                    if (portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || portClass == TMG_CLOCK_INPUT) {
+                        // Skip
+                    } else {
+                        // Iterate over all output ports on the same cell as the sink
+                        for (auto port : usr.cell->ports) {
+                            if (port.second.type != PORT_OUT || !port.second.net)
+                                continue;
+                            DelayQuad comb_delay;
+                            // Look up delay through this path
+                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
+                            if (!is_path)
+                                continue;
+                            auto &data = net_data[port.second.net][start_clk];
+                            auto &arrival = data.max_arrival;
+                            arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
+                            auto &path_length = data.max_path_length;
+                            path_length = std::max(path_length, net_length_plus_one);
+                        }
+                    }
+                }
+            }
+        }
+
+        dict<ClockPair, std::pair<delay_t, NetInfo *>> crit_nets;
+
+        // Now go backwards topologically to determine the minimum path slack, and to distribute all path slack evenly
+        // between all nets on the path
+        for (auto net : boost::adaptors::reverse(topological_order)) {
+            if (!net_data.count(net))
+                continue;
+            auto &nd_map = net_data.at(net);
+            for (auto &startdomain : nd_map) {
+                auto &nd = startdomain.second;
+                // Ignore false startpoints
+                if (nd.false_startpoint)
+                    continue;
+                const delay_t net_length_plus_one = nd.max_path_length + 1;
+                auto &net_min_remaining_budget = nd.min_remaining_budget;
+                for (auto &usr : net->users) {
+                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
+                    int port_clocks;
+                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
+                    if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
+                        auto process_endpoint = [&](IdString clksig, ClockEdge edge, delay_t setup) {
+                            const auto net_arrival = nd.max_arrival;
+                            const auto endpoint_arrival = net_arrival + net_delay + setup;
+                            delay_t period;
+                            // Set default period
+                            if (edge == startdomain.first.edge) {
+                                period = clk_period;
+                            } else {
+                                period = clk_period / 2;
+                            }
+                            if (clksig != async_clock) {
+                                if (ctx->nets.at(clksig)->clkconstr) {
+                                    if (edge == startdomain.first.edge) {
+                                        // same edge
+                                        period = ctx->nets.at(clksig)->clkconstr->period.minDelay();
+                                    } else if (edge == RISING_EDGE) {
+                                        // falling -> rising
+                                        period = ctx->nets.at(clksig)->clkconstr->low.minDelay();
+                                    } else if (edge == FALLING_EDGE) {
+                                        // rising -> falling
+                                        period = ctx->nets.at(clksig)->clkconstr->high.minDelay();
+                                    }
+                                }
+                            }
+                            auto path_budget = period - endpoint_arrival;
+
+                            if (update) {
+                                auto budget_share = path_budget / net_length_plus_one;
+                                net_min_remaining_budget =
+                                        std::min(net_min_remaining_budget, path_budget - budget_share);
+                            }
+
+                            if (path_budget < min_slack)
+                                min_slack = path_budget;
+
+                            if (slack_histogram) {
+                                int slack_ps = ctx->getDelayNS(path_budget) * 1000;
+                                (*slack_histogram)[slack_ps]++;
+                            }
+                            ClockEvent dest_ev{clksig, edge};
+                            ClockPair clockPair{startdomain.first, dest_ev};
+                            nd.arrival_time[dest_ev] = std::max(nd.arrival_time[dest_ev], endpoint_arrival);
+
+                            // Store the detailed timing for each net and user (a.k.a. sink)
+                            if (detailed_net_timings) {
+                                NetSinkTiming sink_timing;
+                                sink_timing.clock_pair = clockPair;
+                                sink_timing.cell_port = std::make_pair(usr.cell->name, usr.port);
+                                sink_timing.delay = endpoint_arrival;
+
+                                (*detailed_net_timings)[net->name].push_back(sink_timing);
+                            }
+
+                            if (crit_path) {
+                                if (!crit_nets.count(clockPair) || crit_nets.at(clockPair).first < endpoint_arrival) {
+                                    crit_nets[clockPair] = std::make_pair(endpoint_arrival, net);
+                                    (*crit_path)[clockPair].path_delay = endpoint_arrival;
+                                    (*crit_path)[clockPair].path_period = period;
+                                    (*crit_path)[clockPair].ports.clear();
+                                    (*crit_path)[clockPair].ports.push_back(&usr);
+                                }
+                            }
+                        };
+                        if (portClass == TMG_REGISTER_INPUT) {
+                            for (int i = 0; i < port_clocks; i++) {
+                                TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, i);
+                                const NetInfo *clknet = usr.cell->getPort(clkInfo.clock_port);
+                                IdString clksig = clknet ? clknet->name : async_clock;
+                                process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, clkInfo.setup.maxDelay());
+                            }
+                        } else {
+                            process_endpoint(async_clock, RISING_EDGE, 0);
+                        }
+
+                    } else if (update) {
+
+                        // Iterate over all output ports on the same cell as the sink
+                        for (const auto &port : usr.cell->ports) {
+                            if (port.second.type != PORT_OUT || !port.second.net)
+                                continue;
+                            DelayQuad comb_delay;
+                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
+                            if (!is_path)
+                                continue;
+                            if (net_data.count(port.second.net) &&
+                                net_data.at(port.second.net).count(startdomain.first)) {
+                                auto path_budget =
+                                        net_data.at(port.second.net).at(startdomain.first).min_remaining_budget;
+                                auto budget_share = path_budget / net_length_plus_one;
+                                net_min_remaining_budget =
+                                        std::min(net_min_remaining_budget, path_budget - budget_share);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        if (crit_path) {
+            // Walk backwards from the most critical net
+            for (auto crit_pair : crit_nets) {
+                NetInfo *crit_net = crit_pair.second.second;
+                auto &cp_ports = (*crit_path)[crit_pair.first].ports;
+                while (crit_net) {
+                    const PortInfo *crit_ipin = nullptr;
+                    delay_t max_arrival = std::numeric_limits<delay_t>::min();
+                    // Look at all input ports on its driving cell
+                    for (const auto &port : crit_net->driver.cell->ports) {
+                        if (port.second.type != PORT_IN || !port.second.net)
+                            continue;
+                        DelayQuad comb_delay;
+                        bool is_path =
+                                ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
+                        if (!is_path)
+                            continue;
+                        // If input port is influenced by a clock, skip
+                        int port_clocks;
+                        TimingPortClass portClass =
+                                ctx->getPortTimingClass(crit_net->driver.cell, port.first, port_clocks);
+                        if (portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE)
+                            continue;
+                        // And find the fanin net with the latest arrival time
+                        if (net_data.count(port.second.net) &&
+                            net_data.at(port.second.net).count(crit_pair.first.start)) {
+                            auto net_arrival = net_data.at(port.second.net).at(crit_pair.first.start).max_arrival;
+                            if (net_delays) {
+                                for (auto &user : port.second.net->users)
+                                    if (user.port == port.first && user.cell == crit_net->driver.cell) {
+                                        net_arrival += ctx->getNetinfoRouteDelay(port.second.net, user);
+                                        break;
+                                    }
+                            }
+                            net_arrival += comb_delay.maxDelay();
+                            if (net_arrival > max_arrival) {
+                                max_arrival = net_arrival;
+                                crit_ipin = &port.second;
+                            }
+                        }
+                    }
+
+                    if (!crit_ipin)
+                        break;
+                    // Now convert PortInfo* into a PortRef*
+                    for (auto &usr : crit_ipin->net->users) {
+                        if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
+                            cp_ports.push_back(&usr);
+                            break;
+                        }
+                    }
+                    crit_net = crit_ipin->net;
+                }
+                std::reverse(cp_ports.begin(), cp_ports.end());
+            }
+        }
+        return min_slack;
+    }
+};
+
+CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
+{
+
+    CriticalPath report;
+    report.clock_pair = clocks;
+
+    auto &front = crit_path.front();
+    auto &front_port = front->cell->ports.at(front->port);
+    auto &front_driver = front_port.net->driver;
+
+    int port_clocks;
+    auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
+
+    const CellInfo *last_cell = front->cell;
+    IdString last_port = front_driver.port;
+
+    int clock_start = -1;
+    if (portClass == TMG_REGISTER_OUTPUT) {
+        for (int i = 0; i < port_clocks; i++) {
+            TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
+            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
+            if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
+                last_port = clockInfo.clock_port;
+                clock_start = i;
+                break;
+            }
+        }
+    }
+
+    for (auto sink : crit_path) {
+        auto sink_cell = sink->cell;
+        auto &port = sink_cell->ports.at(sink->port);
+        auto net = port.net;
+        auto &driver = net->driver;
+        auto driver_cell = driver.cell;
+
+        CriticalPath::Segment seg_logic;
+
+        DelayQuad comb_delay;
+        if (clock_start != -1) {
+            auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
+            comb_delay = clockInfo.clockToQ;
+            clock_start = -1;
+            seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
+        } else if (last_port == driver.port) {
+            // Case where we start with a STARTPOINT etc
+            comb_delay = DelayQuad(0);
+            seg_logic.type = CriticalPath::Segment::Type::SOURCE;
+        } else {
+            ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
+            seg_logic.type = CriticalPath::Segment::Type::LOGIC;
+        }
+
+        seg_logic.delay = comb_delay.maxDelay();
+        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.to = std::make_pair(driver_cell->name, driver.port);
+        seg_logic.net = IdString();
+        report.segments.push_back(seg_logic);
+
+        auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
+
+        CriticalPath::Segment seg_route;
+        seg_route.type = CriticalPath::Segment::Type::ROUTING;
+        seg_route.delay = net_delay;
+        seg_route.from = std::make_pair(driver_cell->name, driver.port);
+        seg_route.to = std::make_pair(sink_cell->name, sink->port);
+        seg_route.net = net->name;
+        report.segments.push_back(seg_route);
+
+        last_cell = sink_cell;
+        last_port = sink->port;
+    }
+
+    int clockCount = 0;
+    auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
+    if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
+        auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
+        delay_t setup = sinkClockInfo.setup.maxDelay();
+
+        CriticalPath::Segment seg_logic;
+        seg_logic.type = CriticalPath::Segment::Type::SETUP;
+        seg_logic.delay = setup;
+        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.to = seg_logic.from;
+        seg_logic.net = IdString();
+        report.segments.push_back(seg_logic);
+    }
+
+    return report;
+}
+
+void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure,
+                     bool update_results)
+{
+    auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
+        std::string value;
+        if (e.clock == ctx->id("$async$"))
+            value = std::string("<async>");
+        else
+            value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
+        if (int(value.length()) < field_width)
+            value.insert(value.length(), field_width - int(value.length()), ' ');
+        return value;
+    };
+
+    CriticalPathDataMap crit_paths;
+    DelayFrequency slack_histogram;
+    DetailedNetTimings detailed_net_timings;
+
+    Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
+                  print_histogram ? &slack_histogram : nullptr,
+                  (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
+    timing.walk_paths();
+
+    // Use TimingAnalyser to determine clock-to-clock relations
+    TimingAnalyser timingAnalyser(ctx);
+    timingAnalyser.setup();
+
+    bool report_critical_paths = print_path || print_fmax || update_results;
+
+    dict<IdString, CriticalPath> clock_reports;
+    std::vector<CriticalPath> xclock_reports;
+    dict<IdString, ClockFmax> clock_fmax;
+    std::set<IdString> empty_clocks; // set of clocks with no interior paths
+
+    if (report_critical_paths) {
+
+        for (auto path : crit_paths) {
+            const ClockEvent &a = path.first.start;
+            const ClockEvent &b = path.first.end;
+            empty_clocks.insert(a.clock);
+            empty_clocks.insert(b.clock);
+        }
+        for (auto path : crit_paths) {
+            const ClockEvent &a = path.first.start;
+            const ClockEvent &b = path.first.end;
+            if (a.clock != b.clock || a.clock == ctx->id("$async$"))
+                continue;
+            double Fmax;
+            empty_clocks.erase(a.clock);
+            if (a.edge == b.edge)
+                Fmax = 1000 / ctx->getDelayNS(path.second.path_delay);
+            else
+                Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
+            if (!clock_fmax.count(a.clock) || Fmax < clock_fmax.at(a.clock).achieved) {
+                clock_fmax[a.clock].achieved = Fmax;
+                clock_fmax[a.clock].constraint = 0.0f; // Will be filled later
+                clock_reports[a.clock] = build_critical_path_report(ctx, path.first, path.second.ports);
+                clock_reports[a.clock].period = path.second.path_period;
+            }
+        }
+
+        for (auto &path : crit_paths) {
+            const ClockEvent &a = path.first.start;
+            const ClockEvent &b = path.first.end;
+            if (a.clock == b.clock && a.clock != ctx->id("$async$"))
+                continue;
+
+            auto &crit_path = crit_paths.at(path.first).ports;
+            xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
+            xclock_reports.back().period = path.second.path_period;
+        }
+
+        if (clock_reports.empty() && xclock_reports.empty()) {
+            log_info("No Fmax available; no interior timing paths found in design.\n");
+        }
+
+        std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPath &ra, const CriticalPath &rb) {
+            const auto &a = ra.clock_pair;
+            const auto &b = rb.clock_pair;
+
+            if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
+                return true;
+            if (a.start.clock.str(ctx) > b.start.clock.str(ctx))
+                return false;
+            if (a.start.edge < b.start.edge)
+                return true;
+            if (a.start.edge > b.start.edge)
+                return false;
+            if (a.end.clock.str(ctx) < b.end.clock.str(ctx))
+                return true;
+            if (a.end.clock.str(ctx) > b.end.clock.str(ctx))
+                return false;
+            if (a.end.edge < b.end.edge)
+                return true;
+            return false;
+        });
+
+        for (auto &clock : clock_reports) {
+            float target = ctx->setting<float>("target_freq") / 1e6;
+            if (ctx->nets.at(clock.first)->clkconstr)
+                target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
+            clock_fmax[clock.first].constraint = target;
+        }
+    }
+
+    // Print critical paths
+    if (print_path) {
+
+        static auto print_net_source = [ctx](const NetInfo *net) {
+            // Check if this net is annotated with a source list
+            auto sources = net->attrs.find(ctx->id("src"));
+            if (sources == net->attrs.end()) {
+                // No sources for this net, can't print anything
+                return;
+            }
+
+            // Sources are separated by pipe characters.
+            // There is no guaranteed ordering on sources, so we just print all
+            auto sourcelist = sources->second.as_string();
+            std::vector<std::string> source_entries;
+            size_t current = 0, prev = 0;
+            while ((current = sourcelist.find("|", prev)) != std::string::npos) {
+                source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+                prev = current + 1;
+            }
+            // Ensure we emplace the final entry
+            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+
+            // Iterate and print our source list at the correct indentation level
+            log_info("               Defined in:\n");
+            for (auto entry : source_entries) {
+                log_info("                 %s\n", entry.c_str());
+            }
+        };
+
+        // A helper function for reporting one critical path
+        auto print_path_report = [ctx](const CriticalPath &path) {
+            delay_t total = 0, logic_total = 0, route_total = 0;
+
+            log_info("curr total\n");
+            for (const auto &segment : path.segments) {
+
+                total += segment.delay;
+
+                if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
+                    segment.type == CriticalPath::Segment::Type::SOURCE ||
+                    segment.type == CriticalPath::Segment::Type::LOGIC ||
+                    segment.type == CriticalPath::Segment::Type::SETUP) {
+                    logic_total += segment.delay;
+
+                    const std::string type_name =
+                            (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
+
+                    log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
+                             type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+                } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
+                    route_total += segment.delay;
+
+                    const auto &driver = ctx->cells.at(segment.from.first);
+                    const auto &sink = ctx->cells.at(segment.to.first);
+
+                    auto driver_loc = ctx->getBelLocation(driver->bel);
+                    auto sink_loc = ctx->getBelLocation(sink->bel);
+
+                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
+                             ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
+                             sink_loc.y);
+                    log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+
+                    const NetInfo *net = ctx->nets.at(segment.net).get();
+
+                    if (ctx->verbose) {
+
+                        PortRef sink_ref;
+                        sink_ref.cell = sink.get();
+                        sink_ref.port = segment.to.second;
+
+                        auto driver_wire = ctx->getNetinfoSourceWire(net);
+                        auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
+                        log_info("                 prediction: %f ns estimate: %f ns\n",
+                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
+                                 ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
+                        auto cursor = sink_wire;
+                        delay_t delay;
+                        while (driver_wire != cursor) {
+#ifdef ARCH_ECP5
+                            if (net->is_global)
+                                break;
+#endif
+                            auto it = net->wires.find(cursor);
+                            assert(it != net->wires.end());
+                            auto pip = it->second.pip;
+                            NPNR_ASSERT(pip != PipId());
+                            delay = ctx->getPipDelay(pip).maxDelay();
+                            log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
+                            cursor = ctx->getPipSrcWire(pip);
+                        }
+                    }
+
+                    if (!ctx->disable_critical_path_source_print) {
+                        print_net_source(net);
+                    }
+                }
+            }
+            log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
+        };
+
+        // Single domain paths
+        for (auto &clock : clock_reports) {
+            log_break();
+            std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
+                                                                                   : std::string("posedge");
+            std::string end =
+                    clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
+            log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
+                     end.c_str());
+            auto &report = clock.second;
+            print_path_report(report);
+        }
+
+        // Cross-domain paths
+        for (auto &report : xclock_reports) {
+            log_break();
+            std::string start = format_event(report.clock_pair.start);
+            std::string end = format_event(report.clock_pair.end);
+            log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
+            print_path_report(report);
+        }
+    }
+
+    if (print_fmax) {
+        log_break();
+
+        unsigned max_width = 0;
+        for (auto &clock : clock_reports)
+            max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
+
+        for (auto &clock : clock_reports) {
+            const auto &clock_name = clock.first.str(ctx);
+            const int width = max_width - clock_name.size();
+
+            float fmax = clock_fmax[clock.first].achieved;
+            float target = clock_fmax[clock.first].constraint;
+            bool passed = target < fmax;
+
+            if (!warn_on_failure || passed)
+                log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                         clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+                log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                            clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            else
+                log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                                   clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+        }
+        log_break();
+
+        // All clock to clock delays
+        const auto &clock_delays = timingAnalyser.get_clock_delays();
+
+        // Clock to clock delays for xpaths
+        dict<ClockPair, delay_t> xclock_delays;
+        for (auto &report : xclock_reports) {
+            const auto &clock1_name = report.clock_pair.start.clock;
+            const auto &clock2_name = report.clock_pair.end.clock;
+
+            const auto key = std::make_pair(clock1_name, clock2_name);
+            if (clock_delays.count(key)) {
+                xclock_delays[report.clock_pair] = clock_delays.at(key);
+            }
+        }
+
+        unsigned max_width_xca = 0;
+        unsigned max_width_xcb = 0;
+        for (auto &report : xclock_reports) {
+            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
+            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
+        }
+
+        // Check and report xpath delays for related clocks
+        if (!xclock_reports.empty()) {
+            for (auto &report : xclock_reports) {
+                const auto &clock_a = report.clock_pair.start.clock;
+                const auto &clock_b = report.clock_pair.end.clock;
+
+                const auto key = std::make_pair(clock_a, clock_b);
+                if (!clock_delays.count(key)) {
+                    continue;
+                }
+
+                delay_t path_delay = 0;
+                for (const auto &segment : report.segments) {
+                    path_delay += segment.delay;
+                }
+
+                // Compensate path delay for clock-to-clock delay. If the
+                // result is negative then only the latter matters. Otherwise
+                // the compensated path delay is taken.
+                auto clock_delay = clock_delays.at(key);
+                path_delay -= clock_delay;
+
+                float fmax = std::numeric_limits<float>::infinity();
+                if (path_delay < 0) {
+                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
+                } else if (path_delay > 0) {
+                    fmax = 1e3f / ctx->getDelayNS(path_delay);
+                }
+
+                // Both clocks are related so they should have the same
+                // frequency. However, they may get different constraints from
+                // user input. In case of only one constraint preset take it,
+                // otherwise get the worst case (min.)
+                float target;
+                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_a).constraint;
+                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_b).constraint;
+                } else {
+                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
+                }
+
+                bool passed = target < fmax;
+
+                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
+                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
+
+                if (!warn_on_failure || passed)
+                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
+                             fmax, passed ? "PASS" : "FAIL", target);
+                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
+                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                else
+                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            }
+            log_break();
+        }
+
+        // Report clock delays for xpaths
+        if (!clock_delays.empty()) {
+            for (auto &pair : xclock_delays) {
+                auto ev_a = format_event(pair.first.start, max_width_xca);
+                auto ev_b = format_event(pair.first.end, max_width_xcb);
+
+                delay_t delay = pair.second;
+                if (pair.first.start.edge != pair.first.end.edge) {
+                    delay /= 2;
+                }
+
+                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
+                         ctx->getDelayNS(delay));
+            }
+
+            log_break();
+        }
+
+        for (auto &eclock : empty_clocks) {
+            if (eclock != ctx->id("$async$"))
+                log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
+        }
+        log_break();
+
+        int start_field_width = 0, end_field_width = 0;
+        for (auto &report : xclock_reports) {
+            start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
+            end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
+        }
+
+        for (auto &report : xclock_reports) {
+            const ClockEvent &a = report.clock_pair.start;
+            const ClockEvent &b = report.clock_pair.end;
+            delay_t path_delay = 0;
+            for (const auto &segment : report.segments) {
+                path_delay += segment.delay;
+            }
+            auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
+            log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
+        }
+        log_break();
+    }
+
+    if (print_histogram && slack_histogram.size() > 0) {
+        unsigned num_bins = 20;
+        unsigned bar_width = 60;
+        auto min_slack = slack_histogram.begin()->first;
+        auto max_slack = slack_histogram.rbegin()->first;
+        auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
+        std::vector<unsigned> bins(num_bins);
+        unsigned max_freq = 0;
+        for (const auto &i : slack_histogram) {
+            int bin_idx = int((i.first - min_slack) / bin_size);
+            if (bin_idx < 0)
+                bin_idx = 0;
+            else if (bin_idx >= int(num_bins))
+                bin_idx = num_bins - 1;
+            auto &bin = bins.at(bin_idx);
+            bin += i.second;
+            max_freq = std::max(max_freq, bin);
+        }
+        bar_width = std::min(bar_width, max_freq);
+
+        log_break();
+        log_info("Slack histogram:\n");
+        log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
+        log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
+        for (unsigned i = 0; i < num_bins; ++i)
+            log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
+                     std::string(bins[i] * bar_width / max_freq, '*').c_str(),
+                     (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
+    }
+
+    // Update timing results in the context
+    if (update_results) {
+        auto &results = ctx->timing_result;
+
+        results.clock_fmax = std::move(clock_fmax);
+        results.clock_paths = std::move(clock_reports);
+        results.xclock_paths = std::move(xclock_reports);
+
+        results.detailed_net_timings = std::move(detailed_net_timings);
+    }
+}
+
+NEXTPNR_NAMESPACE_END

From 8b51674a6b6e95a500b9005664792e6014d468d7 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 25 May 2023 23:03:16 +0200
Subject: [PATCH 415/712] Add critical path report to modern timing engine

---
 common/kernel/timing.cc     | 583 ++++++++++++++++++++++++++++++++++--
 common/kernel/timing.h      |   7 +-
 common/kernel/timing_old.cc |  49 ++-
 3 files changed, 608 insertions(+), 31 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 1eb414d5db..505683835d 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -640,10 +640,9 @@ void TimingAnalyser::walk_backward()
     }
 }
 
-void TimingAnalyser::print_fmax()
+dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain()
 {
-    // Temporary testing code for comparison only
-    dict<int, double> domain_fmax;
+    dict<domain_id_t, delay_t> domain_delay;
     for (auto p : topological_order) {
         auto &pd = ports.at(p);
         for (auto &req : pd.required) {
@@ -651,15 +650,14 @@ void TimingAnalyser::print_fmax()
                 if (domains.at(req.first).key.is_async())
                     continue;
                 auto &arr = pd.arrival.at(req.first);
-                double fmax = 1000.0 / ctx->getDelayNS(arr.value.maxDelay() - req.second.value.minDelay());
-                if (!domain_fmax.count(req.first) || domain_fmax.at(req.first) > fmax)
-                    domain_fmax[req.first] = fmax;
+                delay_t delay = arr.value.maxDelay() - req.second.value.minDelay();
+                if (!domain_delay.count(req.first) || domain_delay.at(req.first) < delay)
+                    domain_delay[req.first] = delay;
             }
         }
     }
-    for (auto &fm : domain_fmax) {
-        log_info("Domain %s Worst Fmax %.02f\n", ctx->nameOf(domains.at(fm.first).key.clock), fm.second);
-    }
+
+    return domain_delay;
 }
 
 void TimingAnalyser::compute_slack()
@@ -748,41 +746,570 @@ std::vector<CellPortKey> TimingAnalyser::get_failing_eps(domain_id_t domain_pair
     return failing_eps;
 }
 
-void TimingAnalyser::print_critical_path(CellPortKey endpoint, domain_id_t domain_pair)
+std::string tgp_to_string2(TimingPortClass c) {
+    switch (c) {
+        case TMG_CLOCK_INPUT:
+            return "TMG_CLOCK_INPUT";
+        case TMG_GEN_CLOCK:
+            return "TMG_GEN_CLOCK";
+        case TMG_REGISTER_INPUT:
+            return "TMG_REGISTER_INPUT";
+        case TMG_REGISTER_OUTPUT:
+            return "TMG_REGISTER_OUTPUT";
+        case TMG_COMB_INPUT:
+            return "TMG_COMB_INPUT";
+        case TMG_COMB_OUTPUT:
+            return "TMG_COMB_OUTPUT";
+        case TMG_STARTPOINT:
+            return "TMG_STARTPOINT";
+        case TMG_ENDPOINT:
+            return "TMG_ENDPOINT";
+        case TMG_IGNORE:
+            return "TMG_IGNORE";
+    }
+
+    return "UNKNOWN";
+}
+
+CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
 {
-    CellPortKey cursor = endpoint;
+    CriticalPath report;
+
     auto &dp = domain_pairs.at(domain_pair);
-    log("    endpoint %s.%s (slack %.02fns):\n", ctx->nameOf(cursor.cell), ctx->nameOf(cursor.port),
-        ctx->getDelayNS(ports.at(cursor).domain_pairs.at(domain_pair).setup_slack));
+    auto &launch = domains.at(dp.key.launch).key;
+    auto &capture = domains.at(dp.key.capture).key;
+
+    report.clock_pair = ClockPair {
+        .start = ClockEvent {
+            .clock = launch.clock,
+            .edge = launch.edge
+        },
+        .end = ClockEvent {
+            .clock = capture.clock,
+            .edge = capture.edge
+        }
+    };
+
+    report.period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
+    if (launch.edge != capture.edge) {
+        report.period = report.period / 2;
+    }
+
+    if (!launch.is_async() && ctx->nets.at(launch.clock)->clkconstr) {
+        if (launch.edge == capture.edge) {
+            report.period = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
+        } else if (capture.edge == RISING_EDGE) {
+            report.period = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
+        } else if (capture.edge == FALLING_EDGE) {
+            report.period = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
+        }
+    }
+
+    std::vector<PortRef> crit_path_rev;
+    auto cursor = endpoint;
     while (cursor != CellPortKey()) {
-        log("        %s.%s (net %s)\n", ctx->nameOf(cursor.cell), ctx->nameOf(cursor.port),
-            ctx->nameOf(ctx->cells.at(cursor.cell)->getPort(cursor.port)));
+        auto cell = cell_info(cursor);
+        auto& port = port_info(cursor);
+
+        int port_clocks;
+        auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
+
+        if (portClass != TMG_CLOCK_INPUT &&
+            portClass != TMG_ENDPOINT &&
+            portClass != TMG_IGNORE &&
+            port.type == PortType::PORT_IN)
+        {
+            crit_path_rev.emplace_back(PortRef { cell, port.name });        
+        }
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
+
         cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
     }
+
+    auto crit_path = boost::adaptors::reverse(crit_path_rev);
+
+    auto &front = crit_path.front();
+    auto &front_port = front.cell->ports.at(front.port);
+    auto &front_driver = front_port.net->driver;
+
+    int port_clocks;
+    auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
+
+    const CellInfo *last_cell = front.cell;
+    IdString last_port = front_driver.port;
+
+    int clock_start = -1;
+    if (portClass == TMG_REGISTER_OUTPUT) {
+        for (int i = 0; i < port_clocks; i++) {
+            TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
+            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
+            if (clknet != nullptr && clknet->name == launch.clock && clockInfo.edge == launch.edge) {
+                last_port = clockInfo.clock_port;
+                clock_start = i;
+                break;
+            }
+        }
+    }
+
+    log_info("building critical path report for clocks: %s -> %s\n", launch.clock.c_str(ctx), capture.clock.c_str(ctx));
+
+    for (auto sink : crit_path) {
+        auto sink_cell = sink.cell;
+        auto &port = sink_cell->ports.at(sink.port);
+        auto net = port.net;
+        auto &driver = net->driver;
+        auto driver_cell = driver.cell;
+
+        auto clockInfo0 = ctx->getPortTimingClass(driver_cell, driver.port, clock_start);
+
+        log_info("\t%s.%s, tmgPortClass: %s\n", sink_cell->name.c_str(ctx), port.name.c_str(ctx), tgp_to_string2(clockInfo0).c_str());
+
+        CriticalPath::Segment seg_logic;
+
+        DelayQuad comb_delay;
+        if (clock_start != -1) {
+            auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
+            comb_delay = clockInfo.clockToQ;
+            clock_start = -1;
+            seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
+        } else if (last_port == driver.port) {
+            // Case where we start with a STARTPOINT etc
+            comb_delay = DelayQuad(0);
+            seg_logic.type = CriticalPath::Segment::Type::SOURCE;
+        } else {
+            ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
+            seg_logic.type = CriticalPath::Segment::Type::LOGIC;
+        }
+
+        seg_logic.delay = comb_delay.maxDelay();
+        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.to = std::make_pair(driver_cell->name, driver.port);
+        seg_logic.net = IdString();
+        report.segments.push_back(seg_logic);
+
+        auto net_delay = ctx->getNetinfoRouteDelay(net, sink);
+
+        CriticalPath::Segment seg_route;
+        seg_route.type = CriticalPath::Segment::Type::ROUTING;
+        seg_route.delay = net_delay;
+        seg_route.from = std::make_pair(driver_cell->name, driver.port);
+        seg_route.to = std::make_pair(sink_cell->name, sink.port);
+        seg_route.net = net->name;
+        report.segments.push_back(seg_route);
+
+        last_cell = sink_cell;
+        last_port = sink.port;
+    }
+
+    int clockCount = 0;
+    auto sinkClass = ctx->getPortTimingClass(crit_path.back().cell, crit_path.back().port, clockCount);
+    if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
+        auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back().cell, crit_path.back().port, 0);
+        delay_t setup = sinkClockInfo.setup.maxDelay();
+
+        CriticalPath::Segment seg_logic;
+        seg_logic.type = CriticalPath::Segment::Type::SETUP;
+        seg_logic.delay = setup;
+        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.to = seg_logic.from;
+        seg_logic.net = IdString();
+        report.segments.push_back(seg_logic);
+    }
+
+    return report;
 }
 
 void TimingAnalyser::print_report()
 {
+    dict<IdString, CriticalPath> clock_reports;
+    std::vector<CriticalPath> xclock_reports;
+    dict<IdString, ClockFmax> clock_fmax;
+    std::set<IdString> empty_clocks;
+
+    auto delay_by_domain = max_delay_by_domain();
+
     for (int i = 0; i < int(domain_pairs.size()); i++) {
         auto &dp = domain_pairs.at(i);
-        auto &launch = domains.at(dp.key.launch);
-        auto &capture = domains.at(dp.key.capture);
-
-        log("Worst endpoints for %s -> %s\n", clock_event_name(ctx, launch.key).c_str(),
-            clock_event_name(ctx, capture.key).c_str());
-        auto failing_eps = get_failing_eps(i, 5);
-        for (auto &ep : failing_eps)
-            print_critical_path(ep, i);
-        log_break();
+        auto &launch = domains.at(dp.key.launch).key;
+        auto &capture = domains.at(dp.key.capture).key;
+        
+        empty_clocks.insert(launch.clock);
+        empty_clocks.insert(capture.clock);
+    }
+
+    for (int i = 0; i < int(domain_pairs.size()); i++) {
+        auto &dp = domain_pairs.at(i);
+        auto &launch = domains.at(dp.key.launch).key;
+        auto &capture = domains.at(dp.key.capture).key;
+
+        if (launch.clock != capture.clock || launch.clock == ctx->id("$async$"))
+            continue;
+
+        auto path_delay = delay_by_domain.at(dp.key.launch);
+
+        double Fmax;
+        empty_clocks.erase(launch.clock);
+
+        if (launch.edge == capture.edge)
+            Fmax = 1000 / ctx->getDelayNS(path_delay);
+        else
+            Fmax = 500 / ctx->getDelayNS(path_delay);
+        
+        if (!clock_fmax.count(launch.clock) || Fmax < clock_fmax.at(launch.clock).achieved) {
+            clock_fmax[launch.clock].achieved = Fmax;
+            clock_fmax[launch.clock].constraint = 0.0f; // Will be filled later
+            auto worst_endpoint = get_failing_eps(i, 1).at(0);
+            clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint);
+        }
+    }
+
+    for (int i = 0; i < int(domain_pairs.size()); i++) {
+        auto &dp = domain_pairs.at(i);
+        auto &launch = domains.at(dp.key.launch).key;
+        auto &capture = domains.at(dp.key.capture).key;
+
+        if (launch.clock == capture.clock && launch.clock == ctx->id("$async$"))
+            continue;
+
+        auto worst_endpoint = get_failing_eps(i, 1).at(0);
+        xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint));
+    }
+
+    if (clock_reports.empty() && xclock_reports.empty()) {
+        log_info("No Fmax available; no interior timing paths found in design.\n");
+    }
+
+    std::sort(xclock_reports.begin(), xclock_reports.end(), [&](const CriticalPath &ra, const CriticalPath &rb) {
+        const auto &a = ra.clock_pair;
+        const auto &b = rb.clock_pair;
+
+        if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
+            return true;
+        if (a.start.clock.str(ctx) > b.start.clock.str(ctx))
+            return false;
+        if (a.start.edge < b.start.edge)
+            return true;
+        if (a.start.edge > b.start.edge)
+            return false;
+        if (a.end.clock.str(ctx) < b.end.clock.str(ctx))
+            return true;
+        if (a.end.clock.str(ctx) > b.end.clock.str(ctx))
+            return false;
+        if (a.end.edge < b.end.edge)
+            return true;
+        return false;
+    });
+
+    for (auto &clock : clock_reports) {
+        float target = ctx->setting<float>("target_freq") / 1e6;
+        if (ctx->nets.at(clock.first)->clkconstr)
+            target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
+        clock_fmax[clock.first].constraint = target;
+    }
+
+
+    auto print_path = true;
+    auto print_fmax =true;
+
+    auto format_event = [&](const ClockEvent &e, int field_width = 0) {
+        std::string value;
+        if (e.clock == ctx->id("$async$"))
+            value = std::string("<async>");
+        else
+            value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
+        if (int(value.length()) < field_width)
+            value.insert(value.length(), field_width - int(value.length()), ' ');
+        return value;
+    };
+
+        // Print critical paths
+    if (print_path) {
+        if (ctx->idstring_str_to_idx == nullptr) {
+            log_info("global: ctx->idstring_str_to_idx is nullptr\n");
+        } else {
+            for (const auto& kv : *ctx->idstring_str_to_idx) {
+                log_info("global: %s -> %d\n", kv.first.c_str(), kv.second);
+            }
+        }
+
+        static auto print_net_source = [](Context* ctx, const NetInfo *net) {
+            // Check if this net is annotated with a source list
+            auto sources = net->attrs.find(ctx->id("src"));
+            if (sources == net->attrs.end()) {
+                // No sources for this net, can't print anything
+                return;
+            }
+
+            // Sources are separated by pipe characters.
+            // There is no guaranteed ordering on sources, so we just print all
+            auto sourcelist = sources->second.as_string();
+            std::vector<std::string> source_entries;
+            size_t current = 0, prev = 0;
+            while ((current = sourcelist.find("|", prev)) != std::string::npos) {
+                source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+                prev = current + 1;
+            }
+            // Ensure we emplace the final entry
+            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+
+            // Iterate and print our source list at the correct indentation level
+            log_info("               Defined in:\n");
+            for (auto entry : source_entries) {
+                log_info("                 %s\n", entry.c_str());
+            }
+        };
+
+        // A helper function for reporting one critical path
+        auto print_path_report = [](Context* ctx, const CriticalPath &path) {
+            delay_t total = 0, logic_total = 0, route_total = 0;
+
+            log_info("curr total\n");
+
+            for (const auto &segment : path.segments) {
+
+                // log_info("processing segment %s\n", segment.net.c_str(ctx));
+
+                total += segment.delay;
+
+                if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
+                    segment.type == CriticalPath::Segment::Type::SOURCE ||
+                    segment.type == CriticalPath::Segment::Type::LOGIC ||
+                    segment.type == CriticalPath::Segment::Type::SETUP) {
+                
+                    logic_total += segment.delay;
+
+                    const std::string type_name =
+                            (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
+
+                    log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
+                             type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+                } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
+                    route_total += segment.delay;
+
+                    const auto &driver = ctx->cells.at(segment.from.first);
+                    const auto &sink = ctx->cells.at(segment.to.first);
+
+                    auto driver_loc = ctx->getBelLocation(driver->bel);
+                    auto sink_loc = ctx->getBelLocation(sink->bel);
+
+                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
+                             ctx->getDelayNS(total), segment.net.c_str(ctx),
+                             driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
+                    log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+
+                    const NetInfo *net = ctx->nets.at(segment.net).get();
+
+                    if (ctx->verbose) {
+                        PortRef sink_ref;
+                        sink_ref.cell = sink.get();
+                        sink_ref.port = segment.to.second;
+
+                        auto driver_wire = ctx->getNetinfoSourceWire(net);
+                        auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
+                        log_info("                 prediction: %f ns estimate: %f ns\n",
+                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
+                                 ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
+                        auto cursor = sink_wire;
+                        delay_t delay;
+                        while (driver_wire != cursor) {
+#ifdef ARCH_ECP5
+                            if (net->is_global)
+                                break;
+#endif
+                            auto it = net->wires.find(cursor);
+                            assert(it != net->wires.end());
+                            auto pip = it->second.pip;
+                            NPNR_ASSERT(pip != PipId());
+                            delay = ctx->getPipDelay(pip).maxDelay();
+                            log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
+                            cursor = ctx->getPipSrcWire(pip);
+                        }
+                    }
+
+                    if (!ctx->disable_critical_path_source_print) {
+                        print_net_source(ctx, net);
+                    }
+                }
+            }
+
+            log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
+        };
+
+        // Single domain paths
+        for (auto &clock : clock_reports) {
+            log_break();
+            std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
+                                                                                   : std::string("posedge");
+            std::string end =
+                    clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
+            log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
+                     end.c_str());
+            auto &report = clock.second;
+            print_path_report(ctx, report);
+        }
+
+        // Cross-domain paths
+        for (auto &report : xclock_reports) {
+            log_break();
+            std::string start = format_event(report.clock_pair.start);
+            std::string end = format_event(report.clock_pair.end);
+            log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
+            print_path_report(ctx, report);
+        }
     }
 
-    print_fmax();
+    if (print_fmax) {
+        log_break();
+
+        unsigned max_width = 0;
+        for (auto &clock : clock_reports)
+            max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
+
+        for (auto &clock : clock_reports) {
+            const auto &clock_name = clock.first.str(ctx);
+            const int width = max_width - clock_name.size();
+
+            float fmax = clock_fmax[clock.first].achieved;
+            float target = clock_fmax[clock.first].constraint;
+            bool passed = target < fmax;
+
+            if (passed)
+                log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                         clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+                log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                            clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            else
+                log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                                   clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+        }
+        log_break();
+
+        // All clock to clock delays
+        const auto &clock_delays = get_clock_delays();
+
+        // Clock to clock delays for xpaths
+        dict<ClockPair, delay_t> xclock_delays;
+        for (auto &report : xclock_reports) {
+            const auto &clock1_name = report.clock_pair.start.clock;
+            const auto &clock2_name = report.clock_pair.end.clock;
+
+            const auto key = std::make_pair(clock1_name, clock2_name);
+            if (clock_delays.count(key)) {
+                xclock_delays[report.clock_pair] = clock_delays.at(key);
+            }
+        }
+
+        unsigned max_width_xca = 0;
+        unsigned max_width_xcb = 0;
+        for (auto &report : xclock_reports) {
+            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
+            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
+        }
+
+        // Check and report xpath delays for related clocks
+        if (!xclock_reports.empty()) {
+            for (auto &report : xclock_reports) {
+                const auto &clock_a = report.clock_pair.start.clock;
+                const auto &clock_b = report.clock_pair.end.clock;
+
+                const auto key = std::make_pair(clock_a, clock_b);
+                if (!clock_delays.count(key)) {
+                    continue;
+                }
+
+                delay_t path_delay = 0;
+                for (const auto &segment : report.segments) {
+                    path_delay += segment.delay;
+                }
+
+                // Compensate path delay for clock-to-clock delay. If the
+                // result is negative then only the latter matters. Otherwise
+                // the compensated path delay is taken.
+                auto clock_delay = clock_delays.at(key);
+                path_delay -= clock_delay;
+
+                float fmax = std::numeric_limits<float>::infinity();
+                if (path_delay < 0) {
+                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
+                } else if (path_delay > 0) {
+                    fmax = 1e3f / ctx->getDelayNS(path_delay);
+                }
+
+                // Both clocks are related so they should have the same
+                // frequency. However, they may get different constraints from
+                // user input. In case of only one constraint preset take it,
+                // otherwise get the worst case (min.)
+                float target;
+                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_a).constraint;
+                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
+                    target = clock_fmax.at(clock_b).constraint;
+                } else {
+                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
+                }
+
+                bool passed = target < fmax;
+
+                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
+                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
+
+                if (passed)
+                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
+                             fmax, passed ? "PASS" : "FAIL", target);
+                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
+                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                else
+                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            }
+            log_break();
+        }
 
-    for (const auto &it : clock_delays) {
-        log_info("Clock-to-clock %s -> %s: %0.02f ns\n", it.first.first.str(ctx).c_str(),
-                 it.first.second.str(ctx).c_str(), ctx->getDelayNS(it.second));
+        // Report clock delays for xpaths
+        if (!clock_delays.empty()) {
+            for (auto &pair : xclock_delays) {
+                auto ev_a = format_event(pair.first.start, max_width_xca);
+                auto ev_b = format_event(pair.first.end, max_width_xcb);
+
+                delay_t delay = pair.second;
+                if (pair.first.start.edge != pair.first.end.edge) {
+                    delay /= 2;
+                }
+
+                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
+                         ctx->getDelayNS(delay));
+            }
+
+            log_break();
+        }
+
+        for (auto &eclock : empty_clocks) {
+            if (eclock != ctx->id("$async$"))
+                log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
+        }
+        log_break();
+
+        int start_field_width = 0, end_field_width = 0;
+        for (auto &report : xclock_reports) {
+            start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
+            end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
+        }
+
+        for (auto &report : xclock_reports) {
+            const ClockEvent &a = report.clock_pair.start;
+            const ClockEvent &b = report.clock_pair.end;
+            delay_t path_delay = 0;
+            for (const auto &segment : report.segments) {
+                path_delay += segment.delay;
+            }
+            auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
+            log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
+        }
+        log_break();
     }
 }
 
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 8b85af3393..0fe9556060 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -115,12 +115,17 @@ struct TimingAnalyser
     void compute_slack();
     void compute_criticality();
 
-    void print_fmax();
+    dict<domain_id_t, delay_t> max_delay_by_domain();
+
     // get the N most failing endpoints for a given domain pair
     std::vector<CellPortKey> get_failing_eps(domain_id_t domain_pair, int count);
     // print the critical path for an endpoint and domain pair
     void print_critical_path(CellPortKey endpoint, domain_id_t domain_pair);
 
+    // Build up CriticalPathData
+    // Build critical path report
+    CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
+
     const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
 
     // Set arrival/required times if more/less than the current value
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
index 49e6a53f32..0171b526ac 100644
--- a/common/kernel/timing_old.cc
+++ b/common/kernel/timing_old.cc
@@ -18,13 +18,13 @@
  *
  */
 
-#include "timing.h"
 #include <algorithm>
 #include <boost/range/adaptor/reversed.hpp>
 #include <deque>
 #include <map>
 #include <utility>
 #include "log.h"
+#include "timing.h"
 #include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -409,6 +409,8 @@ struct Timing
             for (auto crit_pair : crit_nets) {
                 NetInfo *crit_net = crit_pair.second.second;
                 auto &cp_ports = (*crit_path)[crit_pair.first].ports;
+                log_info("// Walk backwards from the most critical net, start point: %s.%s\n",
+                         cp_ports.at(0)->cell->name.c_str(ctx), cp_ports.at(0)->port.c_str(ctx));
                 while (crit_net) {
                     const PortInfo *crit_ipin = nullptr;
                     delay_t max_arrival = std::numeric_limits<delay_t>::min();
@@ -450,7 +452,9 @@ struct Timing
                         break;
                     // Now convert PortInfo* into a PortRef*
                     for (auto &usr : crit_ipin->net->users) {
+                        log_info("critical pin user: %s.%s\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx));
                         if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
+                            log_info("Adding %s.%s to critical path\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx));
                             cp_ports.push_back(&usr);
                             break;
                         }
@@ -464,9 +468,34 @@ struct Timing
     }
 };
 
-CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
+std::string tgp_to_string(TimingPortClass c)
 {
+    switch (c) {
+    case TMG_CLOCK_INPUT:
+        return "TMG_CLOCK_INPUT";
+    case TMG_GEN_CLOCK:
+        return "TMG_GEN_CLOCK";
+    case TMG_REGISTER_INPUT:
+        return "TMG_REGISTER_INPUT";
+    case TMG_REGISTER_OUTPUT:
+        return "TMG_REGISTER_OUTPUT";
+    case TMG_COMB_INPUT:
+        return "TMG_COMB_INPUT";
+    case TMG_COMB_OUTPUT:
+        return "TMG_COMB_OUTPUT";
+    case TMG_STARTPOINT:
+        return "TMG_STARTPOINT";
+    case TMG_ENDPOINT:
+        return "TMG_ENDPOINT";
+    case TMG_IGNORE:
+        return "TMG_IGNORE";
+    }
 
+    return "UNKNOWN";
+}
+
+CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
+{
     CriticalPath report;
     report.clock_pair = clocks;
 
@@ -493,7 +522,11 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
         }
     }
 
+    log_info("building critical path report for clocks: %s -> %s\n", clocks.start.clock.c_str(ctx),
+             clocks.end.clock.c_str(ctx));
+
     for (auto sink : crit_path) {
+
         auto sink_cell = sink->cell;
         auto &port = sink_cell->ports.at(sink->port);
         auto net = port.net;
@@ -582,6 +615,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     TimingAnalyser timingAnalyser(ctx);
     timingAnalyser.setup();
 
+    log("start timingAnalyser.print_report();\n\n");
+    timingAnalyser.print_report();
+    log("end timingAnalyser.print_report();\n\n");
+
     bool report_critical_paths = print_path || print_fmax || update_results;
 
     dict<IdString, CriticalPath> clock_reports;
@@ -968,6 +1005,14 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                      (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
     }
 
+    log_info("segments");
+    for (auto &r : clock_reports) {
+        log_info("clock: %s\n", r.first.c_str(ctx));
+        for (const auto &segment : r.second.segments) {
+            log_info("processing segment %s\n", segment.net.c_str(ctx));
+        }
+    }
+
     // Update timing results in the context
     if (update_results) {
         auto &results = ctx->timing_result;

From 596873c3020dacc7bced700b37738d95dcd47f6d Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 1 Jun 2023 18:00:35 +0200
Subject: [PATCH 416/712] tmg: Add net_timings, crit path and slack hist

---
 common/kernel/nextpnr_types.h |   5 +
 common/kernel/timing.cc       | 494 ++++++++++------------------------
 common/kernel/timing.h        |  20 +-
 common/kernel/timing_old.cc   |  23 +-
 4 files changed, 174 insertions(+), 368 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index b7f1e0b081..c88dcc9c1f 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -356,9 +356,14 @@ struct TimingResult
     dict<IdString, CriticalPath> clock_paths;
     // Cross-domain critical paths
     std::vector<CriticalPath> xclock_paths;
+    // Domains with no interior paths
+    pool<IdString> empty_paths;
 
     // Detailed net timing data
     dict<IdString, std::vector<NetSinkTiming>> detailed_net_timings;
+
+    // Histogram of delays
+    dict<int, unsigned> delay_frequency;
 };
 
 // Represents the contents of a non-leaf cell in a design
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 505683835d..b0c7980e09 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -50,17 +50,17 @@ TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
     async_clock_id = 0;
 };
 
-void TimingAnalyser::setup()
+void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
 {
     init_ports();
     get_cell_delays();
     topo_sort();
     setup_port_domains();
     identify_related_domains();
-    run();
+    run(update_net_timings, update_histogram, update_crit_paths, update_route_delays);
 }
 
-void TimingAnalyser::run(bool update_route_delays)
+void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
 {
     reset_times();
     if (update_route_delays)
@@ -69,6 +69,25 @@ void TimingAnalyser::run(bool update_route_delays)
     walk_backward();
     compute_slack();
     compute_criticality();
+
+    // Ensure we clear all timing results if any of them has been marked as
+    // as to be updated. This is done so we ensure it's not possible to have
+    // timing_result which contains mixed reports
+    if (update_net_timings || update_histogram || update_crit_paths) {
+        ctx->timing_result = TimingResult();
+    }
+
+    if (update_net_timings) {
+        build_detailed_net_timing_report();
+    }
+
+    if (update_histogram) {
+        build_slack_histogram_report();
+    }
+
+    if (update_crit_paths) {
+        build_crit_path_reports();
+    }
 }
 
 void TimingAnalyser::init_ports()
@@ -640,19 +659,21 @@ void TimingAnalyser::walk_backward()
     }
 }
 
-dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain()
+dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 {
     dict<domain_id_t, delay_t> domain_delay;
     for (auto p : topological_order) {
         auto &pd = ports.at(p);
         for (auto &req : pd.required) {
-            if (pd.arrival.count(req.first)) {
-                if (domains.at(req.first).key.is_async())
-                    continue;
-                auto &arr = pd.arrival.at(req.first);
-                delay_t delay = arr.value.maxDelay() - req.second.value.minDelay();
-                if (!domain_delay.count(req.first) || domain_delay.at(req.first) < delay)
-                    domain_delay[req.first] = delay;
+            auto &capture = req.first;
+            for (auto &arr : pd.arrival) {
+                auto &launch = arr.first;
+
+                auto dp = domain_pair_id(launch, capture);
+
+                delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
+                if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
+                    domain_delay[dp] = delay;
             }
         }
     }
@@ -703,6 +724,7 @@ void TimingAnalyser::compute_criticality()
 {
     for (auto p : topological_order) {
         auto &pd = ports.at(p);
+
         for (auto &pdp : pd.domain_pairs) {
             auto &dp = domain_pairs.at(pdp.first);
             // Do not set criticality for asynchronous paths
@@ -719,13 +741,51 @@ void TimingAnalyser::compute_criticality()
     }
 }
 
-std::vector<CellPortKey> TimingAnalyser::get_failing_eps(domain_id_t domain_pair, int count)
+void TimingAnalyser::build_detailed_net_timing_report()
+{
+    auto &net_timings = ctx->timing_result.detailed_net_timings;
+
+    for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
+        auto &dom = domains.at(dom_id);
+        for (auto &ep : dom.endpoints) {
+            auto &pd = ports.at(ep.first);
+            const NetInfo *net = port_info(ep.first).net;
+
+            for (auto &arr : pd.arrival) {
+                auto &launch = domains.at(arr.first).key;
+                for (auto &req : pd.required) {
+                    auto &capture = domains.at(req.first).key;
+
+                    NetSinkTiming sink_timing;
+                    sink_timing.clock_pair = ClockPair {
+                        .start = ClockEvent {
+                            .clock = launch.clock,
+                            .edge = launch.edge
+                        },
+                        .end = ClockEvent {
+                            .clock = capture.clock,
+                            .edge = capture.edge
+                        }
+                    };
+                    sink_timing.cell_port = std::make_pair(pd.cell_port.cell, pd.cell_port.port);
+                    sink_timing.delay = arr.second.value.max_delay;
+
+                    log_info("update net_timings: %s: %f\n", net->name.c_str(ctx), (float) sink_timing.delay);
+
+                    net_timings[net->name].push_back(sink_timing);
+                }
+            }
+        }
+    }
+}
+
+std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair, int count)
 {
-    std::vector<CellPortKey> failing_eps;
+    std::vector<CellPortKey> worst_eps;
     delay_t last_slack = std::numeric_limits<delay_t>::min();
     auto &dp = domain_pairs.at(domain_pair);
     auto &cap_d = domains.at(dp.key.capture);
-    while (int(failing_eps.size()) < count) {
+    while (int(worst_eps.size()) < count) {
         CellPortKey next;
         delay_t next_slack = std::numeric_limits<delay_t>::max();
         for (auto ep : cap_d.endpoints) {
@@ -740,35 +800,10 @@ std::vector<CellPortKey> TimingAnalyser::get_failing_eps(domain_id_t domain_pair
         }
         if (next == CellPortKey())
             break;
-        failing_eps.push_back(next);
+        worst_eps.push_back(next);
         last_slack = next_slack;
     }
-    return failing_eps;
-}
-
-std::string tgp_to_string2(TimingPortClass c) {
-    switch (c) {
-        case TMG_CLOCK_INPUT:
-            return "TMG_CLOCK_INPUT";
-        case TMG_GEN_CLOCK:
-            return "TMG_GEN_CLOCK";
-        case TMG_REGISTER_INPUT:
-            return "TMG_REGISTER_INPUT";
-        case TMG_REGISTER_OUTPUT:
-            return "TMG_REGISTER_OUTPUT";
-        case TMG_COMB_INPUT:
-            return "TMG_COMB_INPUT";
-        case TMG_COMB_OUTPUT:
-            return "TMG_COMB_OUTPUT";
-        case TMG_STARTPOINT:
-            return "TMG_STARTPOINT";
-        case TMG_ENDPOINT:
-            return "TMG_ENDPOINT";
-        case TMG_IGNORE:
-            return "TMG_IGNORE";
-    }
-
-    return "UNKNOWN";
+    return worst_eps;
 }
 
 CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
@@ -819,7 +854,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
             portClass != TMG_IGNORE &&
             port.type == PortType::PORT_IN)
         {
-            crit_path_rev.emplace_back(PortRef { cell, port.name });        
+            crit_path_rev.emplace_back(PortRef { cell, port.name });
         }
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
@@ -852,8 +887,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     }
 
-    log_info("building critical path report for clocks: %s -> %s\n", launch.clock.c_str(ctx), capture.clock.c_str(ctx));
-
     for (auto sink : crit_path) {
         auto sink_cell = sink.cell;
         auto &port = sink_cell->ports.at(sink.port);
@@ -861,10 +894,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         auto &driver = net->driver;
         auto driver_cell = driver.cell;
 
-        auto clockInfo0 = ctx->getPortTimingClass(driver_cell, driver.port, clock_start);
-
-        log_info("\t%s.%s, tmgPortClass: %s\n", sink_cell->name.c_str(ctx), port.name.c_str(ctx), tgp_to_string2(clockInfo0).c_str());
-
         CriticalPath::Segment seg_logic;
 
         DelayQuad comb_delay;
@@ -920,22 +949,25 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     return report;
 }
 
-void TimingAnalyser::print_report()
+void TimingAnalyser::build_crit_path_reports()
 {
-    dict<IdString, CriticalPath> clock_reports;
-    std::vector<CriticalPath> xclock_reports;
-    dict<IdString, ClockFmax> clock_fmax;
-    std::set<IdString> empty_clocks;
+    auto &clock_reports = ctx->timing_result.clock_paths;
+    auto &xclock_reports = ctx->timing_result.xclock_paths;
+    auto &clock_fmax = ctx->timing_result.clock_fmax;
+    auto &empty_clocks = ctx->timing_result.empty_paths;
+    auto &clock_delays_ctx = ctx->timing_result.clock_delays;
 
-    auto delay_by_domain = max_delay_by_domain();
+    auto delay_by_domain = max_delay_by_domain_pairs();
+
+    auto uq_doms = ctx->timing_result.empty_paths;
+    auto clock_pairs = std::vector<std::pair<ClockDomainKey, ClockDomainKey>>();
 
     for (int i = 0; i < int(domain_pairs.size()); i++) {
         auto &dp = domain_pairs.at(i);
         auto &launch = domains.at(dp.key.launch).key;
         auto &capture = domains.at(dp.key.capture).key;
-        
-        empty_clocks.insert(launch.clock);
-        empty_clocks.insert(capture.clock);
+
+        clock_pairs.emplace_back(std::make_pair(launch, capture));
     }
 
     for (int i = 0; i < int(domain_pairs.size()); i++) {
@@ -943,7 +975,7 @@ void TimingAnalyser::print_report()
         auto &launch = domains.at(dp.key.launch).key;
         auto &capture = domains.at(dp.key.capture).key;
 
-        if (launch.clock != capture.clock || launch.clock == ctx->id("$async$"))
+        if (launch.clock != capture.clock || launch.is_async())
             continue;
 
         auto path_delay = delay_by_domain.at(dp.key.launch);
@@ -955,11 +987,15 @@ void TimingAnalyser::print_report()
             Fmax = 1000 / ctx->getDelayNS(path_delay);
         else
             Fmax = 500 / ctx->getDelayNS(path_delay);
-        
+
         if (!clock_fmax.count(launch.clock) || Fmax < clock_fmax.at(launch.clock).achieved) {
+            float target = ctx->setting<float>("target_freq") / 1e6;
+            if (ctx->nets.at(launch.clock)->clkconstr)
+                target = 1000 / ctx->getDelayNS(ctx->nets.at(launch.clock)->clkconstr->period.minDelay());
+
             clock_fmax[launch.clock].achieved = Fmax;
-            clock_fmax[launch.clock].constraint = 0.0f; // Will be filled later
-            auto worst_endpoint = get_failing_eps(i, 1).at(0);
+            clock_fmax[launch.clock].constraint = target;
+            auto worst_endpoint = get_worst_eps(i, 1).at(0);
             clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint);
         }
     }
@@ -969,17 +1005,13 @@ void TimingAnalyser::print_report()
         auto &launch = domains.at(dp.key.launch).key;
         auto &capture = domains.at(dp.key.capture).key;
 
-        if (launch.clock == capture.clock && launch.clock == ctx->id("$async$"))
+        if (launch.clock == capture.clock)
             continue;
 
-        auto worst_endpoint = get_failing_eps(i, 1).at(0);
+        auto worst_endpoint = get_worst_eps(i, 1).at(0);
         xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint));
     }
 
-    if (clock_reports.empty() && xclock_reports.empty()) {
-        log_info("No Fmax available; no interior timing paths found in design.\n");
-    }
-
     std::sort(xclock_reports.begin(), xclock_reports.end(), [&](const CriticalPath &ra, const CriticalPath &rb) {
         const auto &a = ra.clock_pair;
         const auto &b = rb.clock_pair;
@@ -1008,308 +1040,54 @@ void TimingAnalyser::print_report()
         clock_fmax[clock.first].constraint = target;
     }
 
+    clock_delays_ctx = clock_delays;
+}
 
-    auto print_path = true;
-    auto print_fmax =true;
-
-    auto format_event = [&](const ClockEvent &e, int field_width = 0) {
-        std::string value;
-        if (e.clock == ctx->id("$async$"))
-            value = std::string("<async>");
-        else
-            value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
-        if (int(value.length()) < field_width)
-            value.insert(value.length(), field_width - int(value.length()), ' ');
-        return value;
-    };
-
-        // Print critical paths
-    if (print_path) {
-        if (ctx->idstring_str_to_idx == nullptr) {
-            log_info("global: ctx->idstring_str_to_idx is nullptr\n");
-        } else {
-            for (const auto& kv : *ctx->idstring_str_to_idx) {
-                log_info("global: %s -> %d\n", kv.first.c_str(), kv.second);
-            }
-        }
-
-        static auto print_net_source = [](Context* ctx, const NetInfo *net) {
-            // Check if this net is annotated with a source list
-            auto sources = net->attrs.find(ctx->id("src"));
-            if (sources == net->attrs.end()) {
-                // No sources for this net, can't print anything
-                return;
-            }
-
-            // Sources are separated by pipe characters.
-            // There is no guaranteed ordering on sources, so we just print all
-            auto sourcelist = sources->second.as_string();
-            std::vector<std::string> source_entries;
-            size_t current = 0, prev = 0;
-            while ((current = sourcelist.find("|", prev)) != std::string::npos) {
-                source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-                prev = current + 1;
-            }
-            // Ensure we emplace the final entry
-            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-
-            // Iterate and print our source list at the correct indentation level
-            log_info("               Defined in:\n");
-            for (auto entry : source_entries) {
-                log_info("                 %s\n", entry.c_str());
-            }
-        };
-
-        // A helper function for reporting one critical path
-        auto print_path_report = [](Context* ctx, const CriticalPath &path) {
-            delay_t total = 0, logic_total = 0, route_total = 0;
-
-            log_info("curr total\n");
-
-            for (const auto &segment : path.segments) {
-
-                // log_info("processing segment %s\n", segment.net.c_str(ctx));
-
-                total += segment.delay;
-
-                if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
-                    segment.type == CriticalPath::Segment::Type::SOURCE ||
-                    segment.type == CriticalPath::Segment::Type::LOGIC ||
-                    segment.type == CriticalPath::Segment::Type::SETUP) {
-                
-                    logic_total += segment.delay;
-
-                    const std::string type_name =
-                            (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
-
-                    log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
-                             type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-                } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
-                    route_total += segment.delay;
-
-                    const auto &driver = ctx->cells.at(segment.from.first);
-                    const auto &sink = ctx->cells.at(segment.to.first);
-
-                    auto driver_loc = ctx->getBelLocation(driver->bel);
-                    auto sink_loc = ctx->getBelLocation(sink->bel);
-
-                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                             ctx->getDelayNS(total), segment.net.c_str(ctx),
-                             driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
-                    log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-
-                    const NetInfo *net = ctx->nets.at(segment.net).get();
-
-                    if (ctx->verbose) {
-                        PortRef sink_ref;
-                        sink_ref.cell = sink.get();
-                        sink_ref.port = segment.to.second;
-
-                        auto driver_wire = ctx->getNetinfoSourceWire(net);
-                        auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
-                        log_info("                 prediction: %f ns estimate: %f ns\n",
-                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
-                                 ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
-                        auto cursor = sink_wire;
-                        delay_t delay;
-                        while (driver_wire != cursor) {
-#ifdef ARCH_ECP5
-                            if (net->is_global)
-                                break;
-#endif
-                            auto it = net->wires.find(cursor);
-                            assert(it != net->wires.end());
-                            auto pip = it->second.pip;
-                            NPNR_ASSERT(pip != PipId());
-                            delay = ctx->getPipDelay(pip).maxDelay();
-                            log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
-                            cursor = ctx->getPipSrcWire(pip);
-                        }
-                    }
-
-                    if (!ctx->disable_critical_path_source_print) {
-                        print_net_source(ctx, net);
-                    }
-                }
-            }
-
-            log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
-        };
-
-        // Single domain paths
-        for (auto &clock : clock_reports) {
-            log_break();
-            std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
-                                                                                   : std::string("posedge");
-            std::string end =
-                    clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
-            log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
-                     end.c_str());
-            auto &report = clock.second;
-            print_path_report(ctx, report);
-        }
-
-        // Cross-domain paths
-        for (auto &report : xclock_reports) {
-            log_break();
-            std::string start = format_event(report.clock_pair.start);
-            std::string end = format_event(report.clock_pair.end);
-            log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
-            print_path_report(ctx, report);
-        }
-    }
-
-    if (print_fmax) {
-        log_break();
-
-        unsigned max_width = 0;
-        for (auto &clock : clock_reports)
-            max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
-
-        for (auto &clock : clock_reports) {
-            const auto &clock_name = clock.first.str(ctx);
-            const int width = max_width - clock_name.size();
-
-            float fmax = clock_fmax[clock.first].achieved;
-            float target = clock_fmax[clock.first].constraint;
-            bool passed = target < fmax;
-
-            if (passed)
-                log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                         clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
-                log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                            clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else
-                log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                                   clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-        }
-        log_break();
-
-        // All clock to clock delays
-        const auto &clock_delays = get_clock_delays();
-
-        // Clock to clock delays for xpaths
-        dict<ClockPair, delay_t> xclock_delays;
-        for (auto &report : xclock_reports) {
-            const auto &clock1_name = report.clock_pair.start.clock;
-            const auto &clock2_name = report.clock_pair.end.clock;
-
-            const auto key = std::make_pair(clock1_name, clock2_name);
-            if (clock_delays.count(key)) {
-                xclock_delays[report.clock_pair] = clock_delays.at(key);
-            }
-        }
-
-        unsigned max_width_xca = 0;
-        unsigned max_width_xcb = 0;
-        for (auto &report : xclock_reports) {
-            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
-            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
-        }
+static std::string clock_event_name(const Context *ctx, const ClockDomainKey &e, int field_width = 0)
+{
+    std::string value;
+    if (e.clock == IdString() || e.clock == ctx->id("$async$"))
+        value = std::string("<async>");
+    else
+        value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
+    if (int(value.length()) < field_width)
+        value.insert(value.length(), field_width - int(value.length()), ' ');
+    return value;
+};
 
-        // Check and report xpath delays for related clocks
-        if (!xclock_reports.empty()) {
-            for (auto &report : xclock_reports) {
-                const auto &clock_a = report.clock_pair.start.clock;
-                const auto &clock_b = report.clock_pair.end.clock;
+void TimingAnalyser::build_slack_histogram_report()
+{
+    auto& slack_histogram = ctx->timing_result.slack_histogram;
 
-                const auto key = std::make_pair(clock_a, clock_b);
-                if (!clock_delays.count(key)) {
-                    continue;
-                }
+    for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
+        for (auto &ep : domains.at(dom_id).endpoints) {
+            auto &pd = ports.at(ep.first);
 
-                delay_t path_delay = 0;
-                for (const auto &segment : report.segments) {
-                    path_delay += segment.delay;
-                }
+            for (auto &req : pd.required) {
+                auto &capture = domains.at(req.first).key;
+                for (auto &arr : pd.arrival) {
+                    auto &launch = domains.at(arr.first).key;
 
-                // Compensate path delay for clock-to-clock delay. If the
-                // result is negative then only the latter matters. Otherwise
-                // the compensated path delay is taken.
-                auto clock_delay = clock_delays.at(key);
-                path_delay -= clock_delay;
-
-                float fmax = std::numeric_limits<float>::infinity();
-                if (path_delay < 0) {
-                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
-                } else if (path_delay > 0) {
-                    fmax = 1e3f / ctx->getDelayNS(path_delay);
-                }
+                    // @gatecat: old timing analysis includes async path
+                    // The slack doesn' make much sense so I filter it out.
+                    if (launch.clock != capture.clock || launch.is_async())
+                        continue;
 
-                // Both clocks are related so they should have the same
-                // frequency. However, they may get different constraints from
-                // user input. In case of only one constraint preset take it,
-                // otherwise get the worst case (min.)
-                float target;
-                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_a).constraint;
-                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_b).constraint;
-                } else {
-                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
-                }
+                    float clk_period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
+                    if (ctx->nets.at(launch.clock)->clkconstr)
+                        clk_period = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
 
-                bool passed = target < fmax;
-
-                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
-                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
-
-                if (passed)
-                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
-                             fmax, passed ? "PASS" : "FAIL", target);
-                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
-                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
-                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-                else
-                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            }
-            log_break();
-        }
+                    if (launch.edge != capture.edge)
+                        clk_period = clk_period / 2;
 
-        // Report clock delays for xpaths
-        if (!clock_delays.empty()) {
-            for (auto &pair : xclock_delays) {
-                auto ev_a = format_event(pair.first.start, max_width_xca);
-                auto ev_b = format_event(pair.first.end, max_width_xcb);
+                    delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
+                    delay_t slack = clk_period - delay;
 
-                delay_t delay = pair.second;
-                if (pair.first.start.edge != pair.first.end.edge) {
-                    delay /= 2;
+                    int slack_ps = ctx->getDelayNS(slack) * 1000;
+                    slack_histogram[slack_ps]++;
                 }
-
-                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
-                         ctx->getDelayNS(delay));
             }
-
-            log_break();
         }
-
-        for (auto &eclock : empty_clocks) {
-            if (eclock != ctx->id("$async$"))
-                log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
-        }
-        log_break();
-
-        int start_field_width = 0, end_field_width = 0;
-        for (auto &report : xclock_reports) {
-            start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
-            end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
-        }
-
-        for (auto &report : xclock_reports) {
-            const ClockEvent &a = report.clock_pair.start;
-            const ClockEvent &b = report.clock_pair.end;
-            delay_t path_delay = 0;
-            for (const auto &segment : report.segments) {
-                path_delay += segment.delay;
-            }
-            auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
-            log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
-        }
-        log_break();
     }
 }
 
@@ -1317,6 +1095,7 @@ domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockE
 {
     return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);
 }
+
 domain_id_t TimingAnalyser::domain_id(const NetInfo *net, ClockEdge edge)
 {
     NPNR_ASSERT(net != nullptr);
@@ -1327,6 +1106,7 @@ domain_id_t TimingAnalyser::domain_id(const NetInfo *net, ClockEdge edge)
     }
     return inserted.first->second;
 }
+
 domain_id_t TimingAnalyser::domain_pair_id(domain_id_t launch, domain_id_t capture)
 {
     ClockDomainPairKey key{launch, capture};
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 0fe9556060..5b59ac2983 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -74,9 +74,8 @@ struct TimingAnalyser
 {
   public:
     TimingAnalyser(Context *ctx);
-    void setup();
-    void run(bool update_route_delays = true);
-    void print_report();
+    void setup(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
+    void run(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
 
     // This is used when routers etc are not actually binding detailed routing (due to congestion or an abstracted
     // model), but want to re-run STA with their own calculated delays
@@ -115,17 +114,20 @@ struct TimingAnalyser
     void compute_slack();
     void compute_criticality();
 
-    dict<domain_id_t, delay_t> max_delay_by_domain();
+    void build_detailed_net_timing_report();
+    // Build up CriticalPathData
+    CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
+    void build_crit_path_reports();
+    void build_slack_histogram_report();
+
+
+    dict<domain_id_t, delay_t> max_delay_by_domain_pairs();
 
     // get the N most failing endpoints for a given domain pair
-    std::vector<CellPortKey> get_failing_eps(domain_id_t domain_pair, int count);
+    std::vector<CellPortKey> get_worst_eps(domain_id_t domain_pair, int count);
     // print the critical path for an endpoint and domain pair
     void print_critical_path(CellPortKey endpoint, domain_id_t domain_pair);
 
-    // Build up CriticalPathData
-    // Build critical path report
-    CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
-
     const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
 
     // Set arrival/required times if more/less than the current value
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
index 0171b526ac..080bbf59c8 100644
--- a/common/kernel/timing_old.cc
+++ b/common/kernel/timing_old.cc
@@ -26,6 +26,8 @@
 #include "log.h"
 #include "timing.h"
 #include "util.h"
+#include <fstream>
+#include <iostream>
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -606,6 +608,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     DelayFrequency slack_histogram;
     DetailedNetTimings detailed_net_timings;
 
+    print_path = true;
+    update_results = true;
+    print_histogram = true;
+
     Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
                   print_histogram ? &slack_histogram : nullptr,
                   (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
@@ -613,12 +619,18 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
 
     // Use TimingAnalyser to determine clock-to-clock relations
     TimingAnalyser timingAnalyser(ctx);
-    timingAnalyser.setup();
+    timingAnalyser.setup(true, true, true, true);
 
     log("start timingAnalyser.print_report();\n\n");
-    timingAnalyser.print_report();
+    // timingAnalyser.print_report();
     log("end timingAnalyser.print_report();\n\n");
 
+    std::string filename = "timingAnalyser.json";
+    std::ofstream f(filename);
+    if (!f)
+        log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
+    ctx->writeReport(f);
+
     bool report_critical_paths = print_path || print_fmax || update_results;
 
     dict<IdString, CriticalPath> clock_reports;
@@ -633,6 +645,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             const ClockEvent &b = path.first.end;
             empty_clocks.insert(a.clock);
             empty_clocks.insert(b.clock);
+            log_info("timing_old: clock pair: %s -> %s\n", a.clock.c_str(ctx), b.clock.c_str(ctx));
         }
         for (auto path : crit_paths) {
             const ClockEvent &a = path.first.start;
@@ -1023,6 +1036,12 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
 
         results.detailed_net_timings = std::move(detailed_net_timings);
     }
+
+    std::string filename2 = "timing_old.json";
+    std::ofstream f2(filename2);
+    if (!f)
+        log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
+    ctx->writeReport(f2);
 }
 
 NEXTPNR_NAMESPACE_END

From cfd3a52a3c25580741b1d03fd59028b8eab8e6d6 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Fri, 16 Jun 2023 13:20:36 +0200
Subject: [PATCH 417/712] tmg: add timing_report

---
 common/kernel/command.cc                    |   2 +-
 common/kernel/context.h                     |   7 +-
 common/kernel/nextpnr_types.h               |   5 +-
 common/kernel/{report.cc => report_json.cc} |  15 +-
 common/kernel/timing.cc                     |  12 -
 common/kernel/timing_old.cc                 |  10 +-
 common/kernel/timing_report.cc              | 365 ++++++++++++++++++++
 7 files changed, 389 insertions(+), 27 deletions(-)
 rename common/kernel/{report.cc => report_json.cc} (94%)
 create mode 100644 common/kernel/timing_report.cc

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 6e94b3009f..aa0704505e 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -505,7 +505,7 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
         std::ofstream f(filename);
         if (!f)
             log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
-        ctx->writeReport(f);
+        ctx->writeJsonReport(f);
     }
 
 #ifndef NO_PYTHON
diff --git a/common/kernel/context.h b/common/kernel/context.h
index b4e7920d29..1a5529ceae 100644
--- a/common/kernel/context.h
+++ b/common/kernel/context.h
@@ -99,8 +99,11 @@ struct Context : Arch, DeterministicRNG
 
     // --------------------------------------------------------------
 
-    // provided by report.cc
-    void writeReport(std::ostream &out) const;
+    // provided by report_json.cc
+    void writeJsonReport(std::ostream &out) const;
+
+    // provided by timing_report.cc
+    void log_timing_results(bool print_histogram, bool print_path, bool warn_on_failure);
     // --------------------------------------------------------------
 
     uint32_t checksum() const;
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index c88dcc9c1f..3b053f6151 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -362,8 +362,11 @@ struct TimingResult
     // Detailed net timing data
     dict<IdString, std::vector<NetSinkTiming>> detailed_net_timings;
 
+    // clock to clock delays
+    dict<std::pair<IdString, IdString>, delay_t> clock_delays;
+
     // Histogram of delays
-    dict<int, unsigned> delay_frequency;
+    dict<int, unsigned> slack_histogram;
 };
 
 // Represents the contents of a non-leaf cell in a design
diff --git a/common/kernel/report.cc b/common/kernel/report_json.cc
similarity index 94%
rename from common/kernel/report.cc
rename to common/kernel/report_json.cc
index 38cf9d0ab1..f95dad791c 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report_json.cc
@@ -44,14 +44,14 @@ dict<IdString, std::pair<int, int>> get_utilization(const Context *ctx)
 static std::string clock_event_name(const Context *ctx, const ClockEvent &e)
 {
     std::string value;
-    if (e.clock == ctx->id("$async$"))
+    if (e.clock == IdString() || e.clock == ctx->id("$async$"))
         value = std::string("<async>");
     else
         value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
     return value;
 };
 
-static Json::array report_critical_paths(const Context *ctx)
+static Json::array json_report_critical_paths(const Context *ctx)
 {
 
     auto report_critical_path = [ctx](const CriticalPath &report) {
@@ -118,7 +118,7 @@ static Json::array report_critical_paths(const Context *ctx)
     return critPathsJson;
 }
 
-static Json::array report_detailed_net_timings(const Context *ctx)
+static Json::array json_report_detailed_net_timings(const Context *ctx)
 {
     auto detailedNetTimingsJson = Json::array();
 
@@ -219,7 +219,7 @@ Report JSON structure:
 }
 */
 
-void Context::writeReport(std::ostream &out) const
+void Context::writeJsonReport(std::ostream &out) const
 {
     auto util = get_utilization(this);
     dict<std::string, Json> util_json;
@@ -238,10 +238,13 @@ void Context::writeReport(std::ostream &out) const
     }
 
     Json::object jsonRoot{
-            {"utilization", util_json}, {"fmax", fmax_json}, {"critical_paths", report_critical_paths(this)}};
+      { "utilization", util_json },
+      { "fmax", fmax_json },
+      { "critical_paths", json_report_critical_paths(this) }
+    };
 
     if (detailed_timing_report) {
-        jsonRoot["detailed_net_timings"] = report_detailed_net_timings(this);
+        jsonRoot["detailed_net_timings"] = json_report_detailed_net_timings(this);
     }
 
     out << Json(jsonRoot).dump() << std::endl;
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index b0c7980e09..9cfc397f10 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -1043,18 +1043,6 @@ void TimingAnalyser::build_crit_path_reports()
     clock_delays_ctx = clock_delays;
 }
 
-static std::string clock_event_name(const Context *ctx, const ClockDomainKey &e, int field_width = 0)
-{
-    std::string value;
-    if (e.clock == IdString() || e.clock == ctx->id("$async$"))
-        value = std::string("<async>");
-    else
-        value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
-    if (int(value.length()) < field_width)
-        value.insert(value.length(), field_width - int(value.length()), ' ');
-    return value;
-};
-
 void TimingAnalyser::build_slack_histogram_report()
 {
     auto& slack_histogram = ctx->timing_result.slack_histogram;
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
index 080bbf59c8..5632203b54 100644
--- a/common/kernel/timing_old.cc
+++ b/common/kernel/timing_old.cc
@@ -21,13 +21,13 @@
 #include <algorithm>
 #include <boost/range/adaptor/reversed.hpp>
 #include <deque>
+#include <fstream>
+#include <iostream>
 #include <map>
 #include <utility>
 #include "log.h"
 #include "timing.h"
 #include "util.h"
-#include <fstream>
-#include <iostream>
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -622,14 +622,14 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     timingAnalyser.setup(true, true, true, true);
 
     log("start timingAnalyser.print_report();\n\n");
-    // timingAnalyser.print_report();
+    ctx->log_timing_results(true, true, true);
     log("end timingAnalyser.print_report();\n\n");
 
     std::string filename = "timingAnalyser.json";
     std::ofstream f(filename);
     if (!f)
         log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
-    ctx->writeReport(f);
+    ctx->writeJsonReport(f);
 
     bool report_critical_paths = print_path || print_fmax || update_results;
 
@@ -1041,7 +1041,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
     std::ofstream f2(filename2);
     if (!f)
         log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
-    ctx->writeReport(f2);
+    ctx->writeJsonReport(f2);
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/timing_report.cc b/common/kernel/timing_report.cc
new file mode 100644
index 0000000000..969e848c66
--- /dev/null
+++ b/common/kernel/timing_report.cc
@@ -0,0 +1,365 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  rowanG077 <goemansrowan@gmail.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+static std::string clock_event_name(const Context *ctx, const ClockEvent &e, int field_width = 0)
+{
+    std::string value;
+    if (e.clock == IdString() || e.clock == ctx->id("$async$"))
+        value = std::string("<async>");
+    else
+        value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
+    if (int(value.length()) < field_width)
+        value.insert(value.length(), field_width - int(value.length()), ' ');
+    return value;
+};
+
+static void log_crit_paths(const Context *ctx)
+{
+    static auto print_net_source = [ctx](const NetInfo *net) {
+        // Check if this net is annotated with a source list
+        auto sources = net->attrs.find(ctx->id("src"));
+        if (sources == net->attrs.end()) {
+            // No sources for this net, can't print anything
+            return;
+        }
+
+        // Sources are separated by pipe characters.
+        // There is no guaranteed ordering on sources, so we just print all
+        auto sourcelist = sources->second.as_string();
+        std::vector<std::string> source_entries;
+        size_t current = 0, prev = 0;
+        while ((current = sourcelist.find("|", prev)) != std::string::npos) {
+            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+            prev = current + 1;
+        }
+        // Ensure we emplace the final entry
+        source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+
+        // Iterate and print our source list at the correct indentation level
+        log_info("               Defined in:\n");
+        for (auto entry : source_entries) {
+            log_info("                 %s\n", entry.c_str());
+        }
+    };
+
+    // A helper function for reporting one critical path
+    auto print_path_report = [ctx](const CriticalPath &path) {
+        delay_t total = 0, logic_total = 0, route_total = 0;
+
+        log_info("curr total\n");
+        for (const auto &segment : path.segments) {
+
+            total += segment.delay;
+
+            if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
+                segment.type == CriticalPath::Segment::Type::SOURCE ||
+                segment.type == CriticalPath::Segment::Type::LOGIC ||
+                segment.type == CriticalPath::Segment::Type::SETUP) {
+                logic_total += segment.delay;
+
+                const std::string type_name =
+                        (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
+
+                log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
+                            type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+            } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
+                route_total += segment.delay;
+
+                const auto &driver = ctx->cells.at(segment.from.first);
+                const auto &sink = ctx->cells.at(segment.to.first);
+
+                auto driver_loc = ctx->getBelLocation(driver->bel);
+                auto sink_loc = ctx->getBelLocation(sink->bel);
+
+                log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
+                            ctx->getDelayNS(total), segment.net.c_str(ctx),
+                            driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
+                log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+
+                const NetInfo *net = ctx->nets.at(segment.net).get();
+
+                if (ctx->verbose) {
+
+                    PortRef sink_ref;
+                    sink_ref.cell = sink.get();
+                    sink_ref.port = segment.to.second;
+
+                    auto driver_wire = ctx->getNetinfoSourceWire(net);
+                    auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
+                    log_info("                 prediction: %f ns estimate: %f ns\n",
+                                ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
+                                ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
+                    auto cursor = sink_wire;
+                    delay_t delay;
+                    while (driver_wire != cursor) {
+#ifdef ARCH_ECP5
+                        if (net->is_global)
+                            break;
+#endif
+                        auto it = net->wires.find(cursor);
+                        assert(it != net->wires.end());
+                        auto pip = it->second.pip;
+                        NPNR_ASSERT(pip != PipId());
+                        delay = ctx->getPipDelay(pip).maxDelay();
+                        log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
+                        cursor = ctx->getPipSrcWire(pip);
+                    }
+                }
+
+                if (!ctx->disable_critical_path_source_print) {
+                    print_net_source(net);
+                }
+            }
+        }
+        log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
+    };
+
+    // Single domain paths
+    for (auto &clock : ctx->timing_result.clock_paths) {
+        log_break();
+        std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
+                                                                                : std::string("posedge");
+        std::string end =
+                clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
+        log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
+                    end.c_str());
+        auto &report = clock.second;
+        print_path_report(report);
+    }
+
+    // Cross-domain paths
+    for (auto &report : ctx->timing_result.xclock_paths) {
+        log_break();
+        std::string start = clock_event_name(ctx, report.clock_pair.start);
+        std::string end = clock_event_name(ctx, report.clock_pair.end);
+        log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
+        print_path_report(report);
+    }
+};
+
+static void log_fmax(Context *ctx, bool warn_on_failure)
+{
+    log_break();
+
+    unsigned max_width = 0;
+    for (auto &clock : ctx->timing_result.clock_paths)
+        max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
+
+    for (auto &clock : ctx->timing_result.clock_paths) {
+        const auto &clock_name = clock.first.str(ctx);
+        const int width = max_width - clock_name.size();
+
+        float fmax = ctx->timing_result.clock_fmax[clock.first].achieved;
+        float target = ctx->timing_result.clock_fmax[clock.first].constraint;
+        bool passed = target < fmax;
+
+        if (!warn_on_failure || passed)
+            log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                        clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+        else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+            log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                        clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+        else
+            log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+                                clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+    }
+    log_break();
+
+
+    // Clock to clock delays for xpaths
+    dict<ClockPair, delay_t> xclock_delays;
+    for (auto &report : ctx->timing_result.xclock_paths) {
+        const auto &clock1_name = report.clock_pair.start.clock;
+        const auto &clock2_name = report.clock_pair.end.clock;
+
+        const auto key = std::make_pair(clock1_name, clock2_name);
+        if (ctx->timing_result.clock_delays.count(key)) {
+            xclock_delays[report.clock_pair] = ctx->timing_result.clock_delays.at(key);
+        }
+    }
+
+    unsigned max_width_xca = 0;
+    unsigned max_width_xcb = 0;
+    for (auto &report : ctx->timing_result.xclock_paths) {
+        max_width_xca = std::max((unsigned)clock_event_name(ctx, report.clock_pair.start).length(), max_width_xca);
+        max_width_xcb = std::max((unsigned)clock_event_name(ctx, report.clock_pair.end).length(), max_width_xcb);
+    }
+
+    // Check and report xpath delays for related clocks
+    if (!ctx->timing_result.xclock_paths.empty()) {
+        for (auto &report : ctx->timing_result.xclock_paths) {
+            const auto &clock_a = report.clock_pair.start.clock;
+            const auto &clock_b = report.clock_pair.end.clock;
+
+            const auto key = std::make_pair(clock_a, clock_b);
+            if (!ctx->timing_result.clock_delays.count(key)) {
+                continue;
+            }
+
+            delay_t path_delay = 0;
+            for (const auto &segment : report.segments) {
+                path_delay += segment.delay;
+            }
+
+            // Compensate path delay for clock-to-clock delay. If the
+            // result is negative then only the latter matters. Otherwise
+            // the compensated path delay is taken.
+            auto clock_delay = ctx->timing_result.clock_delays.at(key);
+            path_delay -= clock_delay;
+
+            float fmax = std::numeric_limits<float>::infinity();
+            if (path_delay < 0) {
+                fmax = 1e3f / ctx->getDelayNS(clock_delay);
+            } else if (path_delay > 0) {
+                fmax = 1e3f / ctx->getDelayNS(path_delay);
+            }
+
+            // Both clocks are related so they should have the same
+            // frequency. However, they may get different constraints from
+            // user input. In case of only one constraint preset take it,
+            // otherwise get the worst case (min.)
+            float target;
+            auto &clock_fmax = ctx->timing_result.clock_fmax;
+            if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
+                target = clock_fmax.at(clock_a).constraint;
+            } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
+                target = clock_fmax.at(clock_b).constraint;
+            } else {
+                target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
+            }
+
+            bool passed = target < fmax;
+
+            auto ev_a = clock_event_name(ctx, report.clock_pair.start, max_width_xca);
+            auto ev_b = clock_event_name(ctx, report.clock_pair.end, max_width_xcb);
+
+            if (!warn_on_failure || passed)
+                log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
+                            fmax, passed ? "PASS" : "FAIL", target);
+            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
+                        bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+                log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                            ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            else
+                log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
+                                    ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+        }
+        log_break();
+    }
+
+    // Report clock delays for xpaths
+    if (!ctx->timing_result.clock_delays.empty()) {
+        for (auto &pair : xclock_delays) {
+            auto ev_a = clock_event_name(ctx, pair.first.start, max_width_xca);
+            auto ev_b = clock_event_name(ctx, pair.first.end, max_width_xcb);
+
+            delay_t delay = pair.second;
+            if (pair.first.start.edge != pair.first.end.edge) {
+                delay /= 2;
+            }
+
+            log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
+                        ctx->getDelayNS(delay));
+        }
+
+        log_break();
+    }
+
+    for (auto &eclock : ctx->timing_result.empty_paths) {
+        if (eclock != IdString())
+            log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
+    }
+    log_break();
+
+    int start_field_width = 0, end_field_width = 0;
+    for (auto &report : ctx->timing_result.xclock_paths) {
+        start_field_width = std::max((int)clock_event_name(ctx, report.clock_pair.start).length(), start_field_width);
+        end_field_width = std::max((int)clock_event_name(ctx, report.clock_pair.end).length(), end_field_width);
+    }
+
+    for (auto &report : ctx->timing_result.xclock_paths) {
+        const ClockEvent &a = report.clock_pair.start;
+        const ClockEvent &b = report.clock_pair.end;
+        delay_t path_delay = 0;
+        for (const auto &segment : report.segments) {
+            path_delay += segment.delay;
+        }
+        auto ev_a = clock_event_name(ctx, a, start_field_width), ev_b = clock_event_name(ctx, b, end_field_width);
+        log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
+    }
+    log_break();
+}
+
+static void log_histogram(Context *ctx) {
+    unsigned num_bins = 20;
+    unsigned bar_width = 60;
+
+    int min_slack = INT_MAX;
+    int max_slack = INT_MIN;
+
+    for (const auto &i : ctx->timing_result.slack_histogram) {
+        if (i.first < min_slack)
+            min_slack = i.first;
+        if (i.first > max_slack)
+            max_slack = i.first;
+    }
+
+    auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
+    std::vector<unsigned> bins(num_bins);
+    unsigned max_freq = 0;
+    for (const auto &i : ctx->timing_result.slack_histogram) {
+        int bin_idx = int((i.first - min_slack) / bin_size);
+        if (bin_idx < 0)
+            bin_idx = 0;
+        else if (bin_idx >= int(num_bins))
+            bin_idx = num_bins - 1;
+        auto &bin = bins.at(bin_idx);
+        bin += i.second;
+        max_freq = std::max(max_freq, bin);
+    }
+    bar_width = std::min(bar_width, max_freq);
+
+    log_break();
+    log_info("Slack histogram:\n");
+    log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
+    log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
+    for (unsigned i = 0; i < num_bins; ++i)
+        log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
+                    std::string(bins[i] * bar_width / max_freq, '*').c_str(),
+                    (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
+}
+
+void Context::log_timing_results(bool print_histogram, bool print_path, bool warn_on_failure)
+{
+    if (print_path)
+        log_crit_paths(this);
+
+    log_fmax(this, warn_on_failure);
+
+    if (print_histogram)
+        log_histogram(this);
+}
+
+NEXTPNR_NAMESPACE_END

From b0820eeaaad6f1883d95e468a84b265a4b2a3950 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 21 Jun 2023 18:09:38 +0200
Subject: [PATCH 418/712] Formatting and display async path in json report

---
 common/kernel/timing.cc        | 96 +++++++++++++++++++---------------
 common/kernel/timing_old.cc    | 42 ---------------
 common/kernel/timing_report.cc | 62 ++++++++++++----------
 3 files changed, 87 insertions(+), 113 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 9cfc397f10..f44adfa6de 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -48,9 +48,12 @@ TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
     domain_to_id.emplace(key, 0);
     domains.emplace_back(key);
     async_clock_id = 0;
+
+    domain_pair_id(async_clock_id, async_clock_id);
 };
 
-void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
+void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths,
+                           bool update_route_delays)
 {
     init_ports();
     get_cell_delays();
@@ -60,7 +63,8 @@ void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool
     run(update_net_timings, update_histogram, update_crit_paths, update_route_delays);
 }
 
-void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
+void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths,
+                         bool update_route_delays)
 {
     reset_times();
     if (update_route_delays)
@@ -757,21 +761,11 @@ void TimingAnalyser::build_detailed_net_timing_report()
                     auto &capture = domains.at(req.first).key;
 
                     NetSinkTiming sink_timing;
-                    sink_timing.clock_pair = ClockPair {
-                        .start = ClockEvent {
-                            .clock = launch.clock,
-                            .edge = launch.edge
-                        },
-                        .end = ClockEvent {
-                            .clock = capture.clock,
-                            .edge = capture.edge
-                        }
-                    };
+                    sink_timing.clock_pair = ClockPair{.start = ClockEvent{.clock = launch.clock, .edge = launch.edge},
+                                                       .end = ClockEvent{.clock = capture.clock, .edge = capture.edge}};
                     sink_timing.cell_port = std::make_pair(pd.cell_port.cell, pd.cell_port.port);
                     sink_timing.delay = arr.second.value.max_delay;
 
-                    log_info("update net_timings: %s: %f\n", net->name.c_str(ctx), (float) sink_timing.delay);
-
                     net_timings[net->name].push_back(sink_timing);
                 }
             }
@@ -806,6 +800,32 @@ std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair,
     return worst_eps;
 }
 
+static std::string tgp_to_string(TimingPortClass c)
+{
+    switch (c) {
+    case TMG_CLOCK_INPUT:
+        return "TMG_CLOCK_INPUT";
+    case TMG_GEN_CLOCK:
+        return "TMG_GEN_CLOCK";
+    case TMG_REGISTER_INPUT:
+        return "TMG_REGISTER_INPUT";
+    case TMG_REGISTER_OUTPUT:
+        return "TMG_REGISTER_OUTPUT";
+    case TMG_COMB_INPUT:
+        return "TMG_COMB_INPUT";
+    case TMG_COMB_OUTPUT:
+        return "TMG_COMB_OUTPUT";
+    case TMG_STARTPOINT:
+        return "TMG_STARTPOINT";
+    case TMG_ENDPOINT:
+        return "TMG_ENDPOINT";
+    case TMG_IGNORE:
+        return "TMG_IGNORE";
+    }
+
+    return "UNKNOWN";
+}
+
 CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
 {
     CriticalPath report;
@@ -814,16 +834,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto &launch = domains.at(dp.key.launch).key;
     auto &capture = domains.at(dp.key.capture).key;
 
-    report.clock_pair = ClockPair {
-        .start = ClockEvent {
-            .clock = launch.clock,
-            .edge = launch.edge
-        },
-        .end = ClockEvent {
-            .clock = capture.clock,
-            .edge = capture.edge
-        }
-    };
+    report.clock_pair = ClockPair{.start = ClockEvent{.clock = launch.clock, .edge = launch.edge},
+                                  .end = ClockEvent{.clock = capture.clock, .edge = capture.edge}};
 
     report.period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
     if (launch.edge != capture.edge) {
@@ -842,19 +854,20 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
+
+    log_info("Analyzing %s -> %s\n", clock_event_name(ctx, launch).c_str(), clock_event_name(ctx, capture).c_str());
     while (cursor != CellPortKey()) {
         auto cell = cell_info(cursor);
-        auto& port = port_info(cursor);
+        auto &port = port_info(cursor);
 
         int port_clocks;
         auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
 
-        if (portClass != TMG_CLOCK_INPUT &&
-            portClass != TMG_ENDPOINT &&
-            portClass != TMG_IGNORE &&
-            port.type == PortType::PORT_IN)
-        {
-            crit_path_rev.emplace_back(PortRef { cell, port.name });
+        log_info("\tcursor at %s.%s tmg: %s, port dir: %s\n", cell->name.c_str(ctx), port.name.c_str(ctx),
+                 tgp_to_string(portClass).c_str(), port.type == PortType::PORT_IN ? "PORT_IN" : "PORT_X");
+
+        if (portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN) {
+            crit_path_rev.emplace_back(PortRef{cell, port.name});
         }
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
@@ -959,15 +972,8 @@ void TimingAnalyser::build_crit_path_reports()
 
     auto delay_by_domain = max_delay_by_domain_pairs();
 
-    auto uq_doms = ctx->timing_result.empty_paths;
-    auto clock_pairs = std::vector<std::pair<ClockDomainKey, ClockDomainKey>>();
-
-    for (int i = 0; i < int(domain_pairs.size()); i++) {
-        auto &dp = domain_pairs.at(i);
-        auto &launch = domains.at(dp.key.launch).key;
-        auto &capture = domains.at(dp.key.capture).key;
-
-        clock_pairs.emplace_back(std::make_pair(launch, capture));
+    for (int i = 0; i < int(domains.size()); i++) {
+        empty_clocks.insert(domains.at(i).key.clock);
     }
 
     for (int i = 0; i < int(domain_pairs.size()); i++) {
@@ -1005,9 +1011,15 @@ void TimingAnalyser::build_crit_path_reports()
         auto &launch = domains.at(dp.key.launch).key;
         auto &capture = domains.at(dp.key.capture).key;
 
-        if (launch.clock == capture.clock)
+        log_info("testin testing %s -> %s\n", clock_event_name(ctx, launch).c_str(),
+                 clock_event_name(ctx, capture).c_str());
+
+        if (launch.clock == capture.clock && !launch.is_async())
             continue;
 
+        log_info("testin testing2 %s -> %s\n", clock_event_name(ctx, launch).c_str(),
+                 clock_event_name(ctx, capture).c_str());
+
         auto worst_endpoint = get_worst_eps(i, 1).at(0);
         xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint));
     }
@@ -1045,7 +1057,7 @@ void TimingAnalyser::build_crit_path_reports()
 
 void TimingAnalyser::build_slack_histogram_report()
 {
-    auto& slack_histogram = ctx->timing_result.slack_histogram;
+    auto &slack_histogram = ctx->timing_result.slack_histogram;
 
     for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
         for (auto &ep : domains.at(dom_id).endpoints) {
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
index 5632203b54..5e7232b413 100644
--- a/common/kernel/timing_old.cc
+++ b/common/kernel/timing_old.cc
@@ -411,8 +411,6 @@ struct Timing
             for (auto crit_pair : crit_nets) {
                 NetInfo *crit_net = crit_pair.second.second;
                 auto &cp_ports = (*crit_path)[crit_pair.first].ports;
-                log_info("// Walk backwards from the most critical net, start point: %s.%s\n",
-                         cp_ports.at(0)->cell->name.c_str(ctx), cp_ports.at(0)->port.c_str(ctx));
                 while (crit_net) {
                     const PortInfo *crit_ipin = nullptr;
                     delay_t max_arrival = std::numeric_limits<delay_t>::min();
@@ -454,9 +452,7 @@ struct Timing
                         break;
                     // Now convert PortInfo* into a PortRef*
                     for (auto &usr : crit_ipin->net->users) {
-                        log_info("critical pin user: %s.%s\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx));
                         if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
-                            log_info("Adding %s.%s to critical path\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx));
                             cp_ports.push_back(&usr);
                             break;
                         }
@@ -470,32 +466,6 @@ struct Timing
     }
 };
 
-std::string tgp_to_string(TimingPortClass c)
-{
-    switch (c) {
-    case TMG_CLOCK_INPUT:
-        return "TMG_CLOCK_INPUT";
-    case TMG_GEN_CLOCK:
-        return "TMG_GEN_CLOCK";
-    case TMG_REGISTER_INPUT:
-        return "TMG_REGISTER_INPUT";
-    case TMG_REGISTER_OUTPUT:
-        return "TMG_REGISTER_OUTPUT";
-    case TMG_COMB_INPUT:
-        return "TMG_COMB_INPUT";
-    case TMG_COMB_OUTPUT:
-        return "TMG_COMB_OUTPUT";
-    case TMG_STARTPOINT:
-        return "TMG_STARTPOINT";
-    case TMG_ENDPOINT:
-        return "TMG_ENDPOINT";
-    case TMG_IGNORE:
-        return "TMG_IGNORE";
-    }
-
-    return "UNKNOWN";
-}
-
 CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
 {
     CriticalPath report;
@@ -524,9 +494,6 @@ CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const P
         }
     }
 
-    log_info("building critical path report for clocks: %s -> %s\n", clocks.start.clock.c_str(ctx),
-             clocks.end.clock.c_str(ctx));
-
     for (auto sink : crit_path) {
 
         auto sink_cell = sink->cell;
@@ -645,7 +612,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
             const ClockEvent &b = path.first.end;
             empty_clocks.insert(a.clock);
             empty_clocks.insert(b.clock);
-            log_info("timing_old: clock pair: %s -> %s\n", a.clock.c_str(ctx), b.clock.c_str(ctx));
         }
         for (auto path : crit_paths) {
             const ClockEvent &a = path.first.start;
@@ -1018,14 +984,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
                      (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
     }
 
-    log_info("segments");
-    for (auto &r : clock_reports) {
-        log_info("clock: %s\n", r.first.c_str(ctx));
-        for (const auto &segment : r.second.segments) {
-            log_info("processing segment %s\n", segment.net.c_str(ctx));
-        }
-    }
-
     // Update timing results in the context
     if (update_results) {
         auto &results = ctx->timing_result;
diff --git a/common/kernel/timing_report.cc b/common/kernel/timing_report.cc
index 969e848c66..4956a72b16 100644
--- a/common/kernel/timing_report.cc
+++ b/common/kernel/timing_report.cc
@@ -79,11 +79,10 @@ static void log_crit_paths(const Context *ctx)
                 segment.type == CriticalPath::Segment::Type::SETUP) {
                 logic_total += segment.delay;
 
-                const std::string type_name =
-                        (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
+                const std::string type_name = (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
 
                 log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
-                            type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+                         type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
                 route_total += segment.delay;
 
@@ -94,8 +93,8 @@ static void log_crit_paths(const Context *ctx)
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
                 log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                            ctx->getDelayNS(total), segment.net.c_str(ctx),
-                            driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
+                         ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
+                         sink_loc.y);
                 log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
 
                 const NetInfo *net = ctx->nets.at(segment.net).get();
@@ -109,8 +108,8 @@ static void log_crit_paths(const Context *ctx)
                     auto driver_wire = ctx->getNetinfoSourceWire(net);
                     auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
                     log_info("                 prediction: %f ns estimate: %f ns\n",
-                                ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
-                                ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
+                             ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
+                             ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
                     auto cursor = sink_wire;
                     delay_t delay;
                     while (driver_wire != cursor) {
@@ -139,12 +138,12 @@ static void log_crit_paths(const Context *ctx)
     // Single domain paths
     for (auto &clock : ctx->timing_result.clock_paths) {
         log_break();
-        std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
-                                                                                : std::string("posedge");
+        std::string start =
+                clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
         std::string end =
                 clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
         log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
-                    end.c_str());
+                 end.c_str());
         auto &report = clock.second;
         print_path_report(report);
     }
@@ -176,18 +175,17 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
         bool passed = target < fmax;
 
         if (!warn_on_failure || passed)
-            log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                        clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(),
+                     fmax, passed ? "PASS" : "FAIL", target);
         else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
-            log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                        clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+            log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(),
+                        fmax, passed ? "PASS" : "FAIL", target);
         else
             log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                                clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                               clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
     }
     log_break();
 
-
     // Clock to clock delays for xpaths
     dict<ClockPair, delay_t> xclock_delays;
     for (auto &report : ctx->timing_result.xclock_paths) {
@@ -256,15 +254,15 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
             auto ev_b = clock_event_name(ctx, report.clock_pair.end, max_width_xcb);
 
             if (!warn_on_failure || passed)
-                log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
-                            fmax, passed ? "PASS" : "FAIL", target);
+                log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(), fmax,
+                         passed ? "PASS" : "FAIL", target);
             else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
-                        bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
-                log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                            ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                     bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+                log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
+                            fmax, passed ? "PASS" : "FAIL", target);
             else
                 log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                    ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
+                                   ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
         }
         log_break();
     }
@@ -280,8 +278,7 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
                 delay /= 2;
             }
 
-            log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
-                        ctx->getDelayNS(delay));
+            log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(delay));
         }
 
         log_break();
@@ -312,7 +309,16 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
     log_break();
 }
 
-static void log_histogram(Context *ctx) {
+static void log_histogram(Context *ctx)
+{
+    log_break();
+    log_info("Slack histogram:\n");
+
+    if (ctx->timing_result.slack_histogram.empty()) {
+        log_info(" No slack figures available\n");
+        return;
+    }
+
     unsigned num_bins = 20;
     unsigned bar_width = 60;
 
@@ -341,14 +347,12 @@ static void log_histogram(Context *ctx) {
     }
     bar_width = std::min(bar_width, max_freq);
 
-    log_break();
-    log_info("Slack histogram:\n");
     log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
     log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
     for (unsigned i = 0; i < num_bins; ++i)
         log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
-                    std::string(bins[i] * bar_width / max_freq, '*').c_str(),
-                    (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
+                 std::string(bins[i] * bar_width / max_freq, '*').c_str(),
+                 (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
 }
 
 void Context::log_timing_results(bool print_histogram, bool print_path, bool warn_on_failure)

From d2a489d5e91b58b33a24b1a378fe918997621485 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 22 Jun 2023 15:18:57 +0200
Subject: [PATCH 419/712] Remove old timing analyser

---
 common/kernel/context.h                       |    7 +-
 common/kernel/nextpnr_types.h                 |    2 +-
 common/kernel/{report_json.cc => report.cc}   |    5 +-
 common/kernel/timing.cc                       |  122 +-
 common/kernel/timing.h                        |   22 +-
 .../{timing_report.cc => timing_log.cc}       |   77 +-
 common/kernel/timing_old.cc                   | 1005 -----------------
 7 files changed, 103 insertions(+), 1137 deletions(-)
 rename common/kernel/{report_json.cc => report.cc} (98%)
 rename common/kernel/{timing_report.cc => timing_log.cc} (88%)
 delete mode 100644 common/kernel/timing_old.cc

diff --git a/common/kernel/context.h b/common/kernel/context.h
index 1a5529ceae..5543a2cf27 100644
--- a/common/kernel/context.h
+++ b/common/kernel/context.h
@@ -99,11 +99,12 @@ struct Context : Arch, DeterministicRNG
 
     // --------------------------------------------------------------
 
-    // provided by report_json.cc
+    // provided by report.cc
     void writeJsonReport(std::ostream &out) const;
 
-    // provided by timing_report.cc
-    void log_timing_results(bool print_histogram, bool print_path, bool warn_on_failure);
+    // provided by timing_log.cc
+    void log_timing_results(TimingResult &result, bool print_histogram, bool print_fmax, bool print_path,
+                            bool warn_on_failure);
     // --------------------------------------------------------------
 
     uint32_t checksum() const;
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 3b053f6151..a5e240a283 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -365,7 +365,7 @@ struct TimingResult
     // clock to clock delays
     dict<std::pair<IdString, IdString>, delay_t> clock_delays;
 
-    // Histogram of delays
+    // Histogram of slack
     dict<int, unsigned> slack_histogram;
 };
 
diff --git a/common/kernel/report_json.cc b/common/kernel/report.cc
similarity index 98%
rename from common/kernel/report_json.cc
rename to common/kernel/report.cc
index f95dad791c..5fa51b6f59 100644
--- a/common/kernel/report_json.cc
+++ b/common/kernel/report.cc
@@ -238,10 +238,7 @@ void Context::writeJsonReport(std::ostream &out) const
     }
 
     Json::object jsonRoot{
-      { "utilization", util_json },
-      { "fmax", fmax_json },
-      { "critical_paths", json_report_critical_paths(this) }
-    };
+            {"utilization", util_json}, {"fmax", fmax_json}, {"critical_paths", json_report_critical_paths(this)}};
 
     if (detailed_timing_report) {
         jsonRoot["detailed_net_timings"] = json_report_detailed_net_timings(this);
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index f44adfa6de..aec9feaf16 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
  *  Copyright (C) 2018  Eddie Hung <eddieh@ece.ubc.ca>
+ *  Copyright (C) 2023  rowanG077 <goemansrowan@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -29,38 +30,22 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-namespace {
-std::string clock_event_name(const Context *ctx, ClockDomainKey &dom)
-{
-    std::string value;
-    if (dom.is_async())
-        value = "<async>";
-    else
-        value = (dom.edge == FALLING_EDGE ? "negedge " : "posedge ") + dom.clock.str(ctx);
-
-    return value;
-}
-} // namespace
-
 TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
 {
     ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE};
     domain_to_id.emplace(key, 0);
     domains.emplace_back(key);
     async_clock_id = 0;
-
-    domain_pair_id(async_clock_id, async_clock_id);
 };
 
-void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths,
-                           bool update_route_delays)
+void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths)
 {
     init_ports();
     get_cell_delays();
     topo_sort();
     setup_port_domains();
     identify_related_domains();
-    run(update_net_timings, update_histogram, update_crit_paths, update_route_delays);
+    run(update_net_timings, update_histogram, update_crit_paths, true);
 }
 
 void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths,
@@ -78,7 +63,7 @@ void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool up
     // as to be updated. This is done so we ensure it's not possible to have
     // timing_result which contains mixed reports
     if (update_net_timings || update_histogram || update_crit_paths) {
-        ctx->timing_result = TimingResult();
+        result = TimingResult();
     }
 
     if (update_net_timings) {
@@ -666,6 +651,7 @@ void TimingAnalyser::walk_backward()
 dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 {
     dict<domain_id_t, delay_t> domain_delay;
+
     for (auto p : topological_order) {
         auto &pd = ports.at(p);
         for (auto &req : pd.required) {
@@ -675,6 +661,9 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 
                 auto dp = domain_pair_id(launch, capture);
 
+                auto l = domains.at(launch);
+                auto c = domains.at(capture);
+
                 delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
                 if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
                     domain_delay[dp] = delay;
@@ -728,7 +717,6 @@ void TimingAnalyser::compute_criticality()
 {
     for (auto p : topological_order) {
         auto &pd = ports.at(p);
-
         for (auto &pdp : pd.domain_pairs) {
             auto &dp = domain_pairs.at(pdp.first);
             // Do not set criticality for asynchronous paths
@@ -747,7 +735,7 @@ void TimingAnalyser::compute_criticality()
 
 void TimingAnalyser::build_detailed_net_timing_report()
 {
-    auto &net_timings = ctx->timing_result.detailed_net_timings;
+    auto &net_timings = result.detailed_net_timings;
 
     for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
         auto &dom = domains.at(dom_id);
@@ -800,32 +788,6 @@ std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair,
     return worst_eps;
 }
 
-static std::string tgp_to_string(TimingPortClass c)
-{
-    switch (c) {
-    case TMG_CLOCK_INPUT:
-        return "TMG_CLOCK_INPUT";
-    case TMG_GEN_CLOCK:
-        return "TMG_GEN_CLOCK";
-    case TMG_REGISTER_INPUT:
-        return "TMG_REGISTER_INPUT";
-    case TMG_REGISTER_OUTPUT:
-        return "TMG_REGISTER_OUTPUT";
-    case TMG_COMB_INPUT:
-        return "TMG_COMB_INPUT";
-    case TMG_COMB_OUTPUT:
-        return "TMG_COMB_OUTPUT";
-    case TMG_STARTPOINT:
-        return "TMG_STARTPOINT";
-    case TMG_ENDPOINT:
-        return "TMG_ENDPOINT";
-    case TMG_IGNORE:
-        return "TMG_IGNORE";
-    }
-
-    return "UNKNOWN";
-}
-
 CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
 {
     CriticalPath report;
@@ -855,7 +817,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
-    log_info("Analyzing %s -> %s\n", clock_event_name(ctx, launch).c_str(), clock_event_name(ctx, capture).c_str());
     while (cursor != CellPortKey()) {
         auto cell = cell_info(cursor);
         auto &port = port_info(cursor);
@@ -863,9 +824,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         int port_clocks;
         auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
 
-        log_info("\tcursor at %s.%s tmg: %s, port dir: %s\n", cell->name.c_str(ctx), port.name.c_str(ctx),
-                 tgp_to_string(portClass).c_str(), port.type == PortType::PORT_IN ? "PORT_IN" : "PORT_X");
-
         if (portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN) {
             crit_path_rev.emplace_back(PortRef{cell, port.name});
         }
@@ -964,11 +922,11 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
 void TimingAnalyser::build_crit_path_reports()
 {
-    auto &clock_reports = ctx->timing_result.clock_paths;
-    auto &xclock_reports = ctx->timing_result.xclock_paths;
-    auto &clock_fmax = ctx->timing_result.clock_fmax;
-    auto &empty_clocks = ctx->timing_result.empty_paths;
-    auto &clock_delays_ctx = ctx->timing_result.clock_delays;
+    auto &clock_reports = result.clock_paths;
+    auto &xclock_reports = result.xclock_paths;
+    auto &clock_fmax = result.clock_fmax;
+    auto &empty_clocks = result.empty_paths;
+    auto &clock_delays_ctx = result.clock_delays;
 
     auto delay_by_domain = max_delay_by_domain_pairs();
 
@@ -984,10 +942,9 @@ void TimingAnalyser::build_crit_path_reports()
         if (launch.clock != capture.clock || launch.is_async())
             continue;
 
-        auto path_delay = delay_by_domain.at(dp.key.launch);
+        auto path_delay = delay_by_domain.at(i);
 
         double Fmax;
-        empty_clocks.erase(launch.clock);
 
         if (launch.edge == capture.edge)
             Fmax = 1000 / ctx->getDelayNS(path_delay);
@@ -999,10 +956,16 @@ void TimingAnalyser::build_crit_path_reports()
             if (ctx->nets.at(launch.clock)->clkconstr)
                 target = 1000 / ctx->getDelayNS(ctx->nets.at(launch.clock)->clkconstr->period.minDelay());
 
+            auto worst_endpoint = get_worst_eps(i, 1);
+            if (worst_endpoint.empty())
+                continue;
+
             clock_fmax[launch.clock].achieved = Fmax;
             clock_fmax[launch.clock].constraint = target;
-            auto worst_endpoint = get_worst_eps(i, 1).at(0);
-            clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint);
+
+            clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint.at(0));
+
+            empty_clocks.erase(launch.clock);
         }
     }
 
@@ -1011,20 +974,17 @@ void TimingAnalyser::build_crit_path_reports()
         auto &launch = domains.at(dp.key.launch).key;
         auto &capture = domains.at(dp.key.capture).key;
 
-        log_info("testin testing %s -> %s\n", clock_event_name(ctx, launch).c_str(),
-                 clock_event_name(ctx, capture).c_str());
-
         if (launch.clock == capture.clock && !launch.is_async())
             continue;
 
-        log_info("testin testing2 %s -> %s\n", clock_event_name(ctx, launch).c_str(),
-                 clock_event_name(ctx, capture).c_str());
+        auto worst_endpoint = get_worst_eps(i, 1);
+        if (worst_endpoint.empty())
+            continue;
 
-        auto worst_endpoint = get_worst_eps(i, 1).at(0);
-        xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint));
+        xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint.at(0)));
     }
 
-    std::sort(xclock_reports.begin(), xclock_reports.end(), [&](const CriticalPath &ra, const CriticalPath &rb) {
+    auto cmp_crit_path = [&](const CriticalPath &ra, const CriticalPath &rb) {
         const auto &a = ra.clock_pair;
         const auto &b = rb.clock_pair;
 
@@ -1043,21 +1003,16 @@ void TimingAnalyser::build_crit_path_reports()
         if (a.end.edge < b.end.edge)
             return true;
         return false;
-    });
+    };
 
-    for (auto &clock : clock_reports) {
-        float target = ctx->setting<float>("target_freq") / 1e6;
-        if (ctx->nets.at(clock.first)->clkconstr)
-            target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
-        clock_fmax[clock.first].constraint = target;
-    }
+    std::sort(xclock_reports.begin(), xclock_reports.end(), cmp_crit_path);
 
     clock_delays_ctx = clock_delays;
 }
 
 void TimingAnalyser::build_slack_histogram_report()
 {
-    auto &slack_histogram = ctx->timing_result.slack_histogram;
+    auto &slack_histogram = result.slack_histogram;
 
     for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
         for (auto &ep : domains.at(dom_id).endpoints) {
@@ -1069,7 +1024,7 @@ void TimingAnalyser::build_slack_histogram_report()
                     auto &launch = domains.at(arr.first).key;
 
                     // @gatecat: old timing analysis includes async path
-                    // The slack doesn' make much sense so I filter it out.
+                    // The slack doesn't make much sense so I filter it out.
                     if (launch.clock != capture.clock || launch.is_async())
                         continue;
 
@@ -1129,4 +1084,17 @@ CellInfo *TimingAnalyser::cell_info(const CellPortKey &key) { return ctx->cells.
 
 PortInfo &TimingAnalyser::port_info(const CellPortKey &key) { return ctx->cells.at(key.cell)->ports.at(key.port); }
 
+void timing_analysis(Context *ctx, bool print_slack_histogram, bool print_fmax, bool print_path, bool warn_on_failure,
+                     bool update_results)
+{
+    TimingAnalyser tmg(ctx);
+    tmg.setup(ctx->detailed_timing_report, print_slack_histogram, print_path || print_fmax);
+
+    auto &result = tmg.get_timing_result();
+    ctx->log_timing_results(result, print_slack_histogram, print_fmax, print_path, warn_on_failure);
+
+    if (update_results)
+        ctx->timing_result = result;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 5b59ac2983..0a0f3eee71 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2023  rowanG077 <goemansrowan@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -74,8 +75,10 @@ struct TimingAnalyser
 {
   public:
     TimingAnalyser(Context *ctx);
-    void setup(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
-    void run(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
+
+    void setup(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false);
+    void run(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false,
+             bool update_route_delays = true);
 
     // This is used when routers etc are not actually binding detailed routing (due to congestion or an abstracted
     // model), but want to re-run STA with their own calculated delays
@@ -91,7 +94,9 @@ struct TimingAnalyser
         return slack;
     }
 
-    auto get_clock_delays() const { return clock_delays; }
+    dict<std::pair<IdString, IdString>, delay_t> get_clock_delays() const { return clock_delays; }
+
+    TimingResult &get_timing_result() { return result; }
 
     bool setup_only = false;
     bool verbose_mode = false;
@@ -115,18 +120,14 @@ struct TimingAnalyser
     void compute_criticality();
 
     void build_detailed_net_timing_report();
-    // Build up CriticalPathData
     CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
     void build_crit_path_reports();
     void build_slack_histogram_report();
 
-
     dict<domain_id_t, delay_t> max_delay_by_domain_pairs();
 
-    // get the N most failing endpoints for a given domain pair
+    // get the N worst endpoints for a given domain pair
     std::vector<CellPortKey> get_worst_eps(domain_id_t domain_pair, int count);
-    // print the critical path for an endpoint and domain pair
-    void print_critical_path(CellPortKey endpoint, domain_id_t domain_pair);
 
     const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
 
@@ -235,10 +236,11 @@ struct TimingAnalyser
     domain_id_t async_clock_id;
 
     Context *ctx;
+
+    TimingResult result;
 };
 
-// Perform timing analysis and print out the fmax, and optionally the
-//    critical path
+// Perform timing analysis and optionaly print out slack histogram, fmax and critical paths
 void timing_analysis(Context *ctx, bool slack_histogram = true, bool print_fmax = true, bool print_path = false,
                      bool warn_on_failure = false, bool update_results = false);
 
diff --git a/common/kernel/timing_report.cc b/common/kernel/timing_log.cc
similarity index 88%
rename from common/kernel/timing_report.cc
rename to common/kernel/timing_log.cc
index 4956a72b16..dd2814a9df 100644
--- a/common/kernel/timing_report.cc
+++ b/common/kernel/timing_log.cc
@@ -1,6 +1,8 @@
 /*
  *  nextpnr -- Next Generation Place and Route
  *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2018  Eddie Hung <eddieh@ece.ubc.ca>
  *  Copyright (C) 2023  rowanG077 <goemansrowan@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
@@ -35,7 +37,7 @@ static std::string clock_event_name(const Context *ctx, const ClockEvent &e, int
     return value;
 };
 
-static void log_crit_paths(const Context *ctx)
+static void log_crit_paths(const Context *ctx, TimingResult &result)
 {
     static auto print_net_source = [ctx](const NetInfo *net) {
         // Check if this net is annotated with a source list
@@ -136,7 +138,7 @@ static void log_crit_paths(const Context *ctx)
     };
 
     // Single domain paths
-    for (auto &clock : ctx->timing_result.clock_paths) {
+    for (auto &clock : result.clock_paths) {
         log_break();
         std::string start =
                 clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
@@ -149,7 +151,7 @@ static void log_crit_paths(const Context *ctx)
     }
 
     // Cross-domain paths
-    for (auto &report : ctx->timing_result.xclock_paths) {
+    for (auto &report : result.xclock_paths) {
         log_break();
         std::string start = clock_event_name(ctx, report.clock_pair.start);
         std::string end = clock_event_name(ctx, report.clock_pair.end);
@@ -158,20 +160,25 @@ static void log_crit_paths(const Context *ctx)
     }
 };
 
-static void log_fmax(Context *ctx, bool warn_on_failure)
+static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
 {
     log_break();
 
+    if (result.clock_paths.empty() && result.clock_paths.empty()) {
+        log_info("No Fmax available; no interior timing paths found in design.\n");
+        return;
+    }
+
     unsigned max_width = 0;
-    for (auto &clock : ctx->timing_result.clock_paths)
+    for (auto &clock : result.clock_paths)
         max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
 
-    for (auto &clock : ctx->timing_result.clock_paths) {
+    for (auto &clock : result.clock_paths) {
         const auto &clock_name = clock.first.str(ctx);
         const int width = max_width - clock_name.size();
 
-        float fmax = ctx->timing_result.clock_fmax[clock.first].achieved;
-        float target = ctx->timing_result.clock_fmax[clock.first].constraint;
+        float fmax = result.clock_fmax[clock.first].achieved;
+        float target = result.clock_fmax[clock.first].constraint;
         bool passed = target < fmax;
 
         if (!warn_on_failure || passed)
@@ -188,31 +195,31 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
 
     // Clock to clock delays for xpaths
     dict<ClockPair, delay_t> xclock_delays;
-    for (auto &report : ctx->timing_result.xclock_paths) {
+    for (auto &report : result.xclock_paths) {
         const auto &clock1_name = report.clock_pair.start.clock;
         const auto &clock2_name = report.clock_pair.end.clock;
 
         const auto key = std::make_pair(clock1_name, clock2_name);
-        if (ctx->timing_result.clock_delays.count(key)) {
-            xclock_delays[report.clock_pair] = ctx->timing_result.clock_delays.at(key);
+        if (result.clock_delays.count(key)) {
+            xclock_delays[report.clock_pair] = result.clock_delays.at(key);
         }
     }
 
     unsigned max_width_xca = 0;
     unsigned max_width_xcb = 0;
-    for (auto &report : ctx->timing_result.xclock_paths) {
+    for (auto &report : result.xclock_paths) {
         max_width_xca = std::max((unsigned)clock_event_name(ctx, report.clock_pair.start).length(), max_width_xca);
         max_width_xcb = std::max((unsigned)clock_event_name(ctx, report.clock_pair.end).length(), max_width_xcb);
     }
 
     // Check and report xpath delays for related clocks
-    if (!ctx->timing_result.xclock_paths.empty()) {
-        for (auto &report : ctx->timing_result.xclock_paths) {
+    if (!result.xclock_paths.empty()) {
+        for (auto &report : result.xclock_paths) {
             const auto &clock_a = report.clock_pair.start.clock;
             const auto &clock_b = report.clock_pair.end.clock;
 
             const auto key = std::make_pair(clock_a, clock_b);
-            if (!ctx->timing_result.clock_delays.count(key)) {
+            if (!result.clock_delays.count(key)) {
                 continue;
             }
 
@@ -224,7 +231,7 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
             // Compensate path delay for clock-to-clock delay. If the
             // result is negative then only the latter matters. Otherwise
             // the compensated path delay is taken.
-            auto clock_delay = ctx->timing_result.clock_delays.at(key);
+            auto clock_delay = result.clock_delays.at(key);
             path_delay -= clock_delay;
 
             float fmax = std::numeric_limits<float>::infinity();
@@ -239,7 +246,7 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
             // user input. In case of only one constraint preset take it,
             // otherwise get the worst case (min.)
             float target;
-            auto &clock_fmax = ctx->timing_result.clock_fmax;
+            auto &clock_fmax = result.clock_fmax;
             if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
                 target = clock_fmax.at(clock_a).constraint;
             } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
@@ -268,7 +275,7 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
     }
 
     // Report clock delays for xpaths
-    if (!ctx->timing_result.clock_delays.empty()) {
+    if (!result.clock_delays.empty()) {
         for (auto &pair : xclock_delays) {
             auto ev_a = clock_event_name(ctx, pair.first.start, max_width_xca);
             auto ev_b = clock_event_name(ctx, pair.first.end, max_width_xcb);
@@ -284,19 +291,19 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
         log_break();
     }
 
-    for (auto &eclock : ctx->timing_result.empty_paths) {
+    for (auto &eclock : result.empty_paths) {
         if (eclock != IdString())
             log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
     }
     log_break();
 
     int start_field_width = 0, end_field_width = 0;
-    for (auto &report : ctx->timing_result.xclock_paths) {
+    for (auto &report : result.xclock_paths) {
         start_field_width = std::max((int)clock_event_name(ctx, report.clock_pair.start).length(), start_field_width);
         end_field_width = std::max((int)clock_event_name(ctx, report.clock_pair.end).length(), end_field_width);
     }
 
-    for (auto &report : ctx->timing_result.xclock_paths) {
+    for (auto &report : result.xclock_paths) {
         const ClockEvent &a = report.clock_pair.start;
         const ClockEvent &b = report.clock_pair.end;
         delay_t path_delay = 0;
@@ -309,23 +316,15 @@ static void log_fmax(Context *ctx, bool warn_on_failure)
     log_break();
 }
 
-static void log_histogram(Context *ctx)
+static void log_histogram(Context *ctx, TimingResult &result)
 {
-    log_break();
-    log_info("Slack histogram:\n");
-
-    if (ctx->timing_result.slack_histogram.empty()) {
-        log_info(" No slack figures available\n");
-        return;
-    }
-
     unsigned num_bins = 20;
     unsigned bar_width = 60;
 
     int min_slack = INT_MAX;
     int max_slack = INT_MIN;
 
-    for (const auto &i : ctx->timing_result.slack_histogram) {
+    for (const auto &i : result.slack_histogram) {
         if (i.first < min_slack)
             min_slack = i.first;
         if (i.first > max_slack)
@@ -335,7 +334,7 @@ static void log_histogram(Context *ctx)
     auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
     std::vector<unsigned> bins(num_bins);
     unsigned max_freq = 0;
-    for (const auto &i : ctx->timing_result.slack_histogram) {
+    for (const auto &i : result.slack_histogram) {
         int bin_idx = int((i.first - min_slack) / bin_size);
         if (bin_idx < 0)
             bin_idx = 0;
@@ -347,6 +346,8 @@ static void log_histogram(Context *ctx)
     }
     bar_width = std::min(bar_width, max_freq);
 
+    log_break();
+    log_info("Slack histogram:\n");
     log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
     log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
     for (unsigned i = 0; i < num_bins; ++i)
@@ -355,15 +356,17 @@ static void log_histogram(Context *ctx)
                  (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
 }
 
-void Context::log_timing_results(bool print_histogram, bool print_path, bool warn_on_failure)
+void Context::log_timing_results(TimingResult &result, bool print_histogram, bool print_fmax, bool print_path,
+                                 bool warn_on_failure)
 {
     if (print_path)
-        log_crit_paths(this);
+        log_crit_paths(this, result);
 
-    log_fmax(this, warn_on_failure);
+    if (print_fmax)
+        log_fmax(this, result, warn_on_failure);
 
-    if (print_histogram)
-        log_histogram(this);
+    if (print_histogram && !timing_result.slack_histogram.empty())
+        log_histogram(this, result);
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/timing_old.cc b/common/kernel/timing_old.cc
deleted file mode 100644
index 5e7232b413..0000000000
--- a/common/kernel/timing_old.cc
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2018  Eddie Hung <eddieh@ece.ubc.ca>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include <algorithm>
-#include <boost/range/adaptor/reversed.hpp>
-#include <deque>
-#include <fstream>
-#include <iostream>
-#include <map>
-#include <utility>
-#include "log.h"
-#include "timing.h"
-#include "util.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-typedef std::vector<const PortRef *> PortRefVector;
-typedef std::map<int, unsigned> DelayFrequency;
-
-struct CriticalPathData
-{
-    PortRefVector ports;
-    delay_t path_delay;
-    delay_t path_period;
-};
-
-typedef dict<ClockPair, CriticalPathData> CriticalPathDataMap;
-
-typedef dict<IdString, std::vector<NetSinkTiming>> DetailedNetTimings;
-
-struct Timing
-{
-    Context *ctx;
-    bool net_delays;
-    bool update;
-    delay_t min_slack;
-    CriticalPathDataMap *crit_path;
-    DelayFrequency *slack_histogram;
-    DetailedNetTimings *detailed_net_timings;
-    IdString async_clock;
-
-    struct TimingData
-    {
-        TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
-        TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
-        delay_t max_arrival;
-        unsigned max_path_length = 0;
-        delay_t min_remaining_budget;
-        bool false_startpoint = false;
-        std::vector<delay_t> min_required;
-        dict<ClockEvent, delay_t> arrival_time;
-    };
-
-    Timing(Context *ctx, bool net_delays, bool update, CriticalPathDataMap *crit_path = nullptr,
-           DelayFrequency *slack_histogram = nullptr, DetailedNetTimings *detailed_net_timings = nullptr)
-            : ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->setting<float>("target_freq")),
-              crit_path(crit_path), slack_histogram(slack_histogram), detailed_net_timings(detailed_net_timings),
-              async_clock(ctx->id("$async$"))
-    {
-    }
-
-    delay_t walk_paths()
-    {
-        const auto clk_period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
-
-        // First, compute the topological order of nets to walk through the circuit, assuming it is a _acyclic_ graph
-        // TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
-        std::vector<NetInfo *> topological_order;
-        dict<const NetInfo *, dict<ClockEvent, TimingData>, hash_ptr_ops> net_data;
-        // In lieu of deleting edges from the graph, simply count the number of fanins to each output port
-        dict<const PortInfo *, unsigned, hash_ptr_ops> port_fanin;
-
-        std::vector<IdString> input_ports;
-        std::vector<const PortInfo *> output_ports;
-
-        pool<IdString> ooc_port_nets;
-
-        // In out-of-context mode, top-level inputs look floating but aren't
-        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
-            for (auto &p : ctx->ports) {
-                if (p.second.type != PORT_IN || p.second.net == nullptr)
-                    continue;
-                ooc_port_nets.insert(p.second.net->name);
-            }
-        }
-
-        for (auto &cell : ctx->cells) {
-            input_ports.clear();
-            output_ports.clear();
-            for (auto &port : cell.second->ports) {
-                if (!port.second.net)
-                    continue;
-                if (port.second.type == PORT_OUT)
-                    output_ports.push_back(&port.second);
-                else
-                    input_ports.push_back(port.first);
-            }
-
-            for (auto o : output_ports) {
-                int clocks = 0;
-                TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clocks);
-                // If output port is influenced by a clock (e.g. FF output) then add it to the ordering as a timing
-                // start-point
-                if (portClass == TMG_REGISTER_OUTPUT) {
-                    topological_order.emplace_back(o->net);
-                    for (int i = 0; i < clocks; i++) {
-                        TimingClockingInfo clkInfo = ctx->getPortClockingInfo(cell.second.get(), o->name, i);
-                        const NetInfo *clknet = cell.second->getPort(clkInfo.clock_port);
-                        IdString clksig = clknet ? clknet->name : async_clock;
-                        net_data[o->net][ClockEvent{clksig, clknet ? clkInfo.edge : RISING_EDGE}] =
-                                TimingData{clkInfo.clockToQ.maxDelay()};
-                    }
-
-                } else {
-                    if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) {
-                        topological_order.emplace_back(o->net);
-                        TimingData td;
-                        td.false_startpoint = (portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE);
-                        td.max_arrival = 0;
-                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
-                    }
-
-                    // Don't analyse paths from a clock input to other pins - they will be considered by the
-                    // special-case handling register input/output class ports
-                    if (portClass == TMG_CLOCK_INPUT)
-                        continue;
-
-                    // Otherwise, for all driven input ports on this cell, if a timing arc exists between the input and
-                    // the current output port, increment fanin counter
-                    for (auto i : input_ports) {
-                        DelayQuad comb_delay;
-                        NetInfo *i_net = cell.second->ports[i].net;
-                        if (i_net->driver.cell == nullptr && !ooc_port_nets.count(i_net->name))
-                            continue;
-                        bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
-                        if (is_path)
-                            port_fanin[o]++;
-                    }
-                    // If there is no fanin, add the port as a false startpoint
-                    if (!port_fanin.count(o) && !net_data.count(o->net)) {
-                        topological_order.emplace_back(o->net);
-                        TimingData td;
-                        td.false_startpoint = true;
-                        td.max_arrival = 0;
-                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
-                    }
-                }
-            }
-        }
-
-        // In out-of-context mode, handle top-level ports correctly
-        if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
-            for (auto &p : ctx->ports) {
-                if (p.second.type != PORT_IN || p.second.net == nullptr)
-                    continue;
-                topological_order.emplace_back(p.second.net);
-            }
-        }
-
-        std::deque<NetInfo *> queue(topological_order.begin(), topological_order.end());
-        // Now walk the design, from the start points identified previously, building up a topological order
-        while (!queue.empty()) {
-            const auto net = queue.front();
-            queue.pop_front();
-
-            for (auto &usr : net->users) {
-                int user_clocks;
-                TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, user_clocks);
-                if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
-                    continue;
-                for (auto &port : usr.cell->ports) {
-                    if (port.second.type != PORT_OUT || !port.second.net)
-                        continue;
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, port_clocks);
-
-                    // Skip if this is a clocked output (but allow non-clocked ones)
-                    if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
-                        portClass == TMG_GEN_CLOCK)
-                        continue;
-                    DelayQuad comb_delay;
-                    bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                    if (!is_path)
-                        continue;
-                    // Decrement the fanin count, and only add to topological order if all its fanins have already
-                    // been visited
-                    auto it = port_fanin.find(&port.second);
-                    if (it == port_fanin.end())
-                        log_error("Timing counted negative fanin count for port %s.%s (net %s), please report this "
-                                  "error.\n",
-                                  ctx->nameOf(usr.cell), ctx->nameOf(port.first), ctx->nameOf(port.second.net));
-                    if (--it->second == 0) {
-                        topological_order.emplace_back(port.second.net);
-                        queue.emplace_back(port.second.net);
-                        port_fanin.erase(it);
-                    }
-                }
-            }
-        }
-
-        // Sanity check to ensure that all ports where fanins were recorded were indeed visited
-        if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) {
-            for (auto fanin : port_fanin) {
-                NetInfo *net = fanin.first->net;
-                if (net != nullptr) {
-                    log_info("   remaining fanin includes %s (net %s)\n", fanin.first->name.c_str(ctx),
-                             net->name.c_str(ctx));
-                    if (net->driver.cell != nullptr)
-                        log_info("        driver = %s.%s\n", net->driver.cell->name.c_str(ctx),
-                                 net->driver.port.c_str(ctx));
-                    for (auto net_user : net->users)
-                        log_info("        user: %s.%s\n", net_user.cell->name.c_str(ctx), net_user.port.c_str(ctx));
-                } else {
-                    log_info("   remaining fanin includes %s (no net)\n", fanin.first->name.c_str(ctx));
-                }
-            }
-            if (ctx->force)
-                log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification "
-                            "of timing ports, etc.\n");
-            else
-                log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of "
-                          "timing ports, etc.\n");
-        }
-
-        // Go forwards topologically to find the maximum arrival time and max path length for each net
-        std::vector<ClockEvent> startdomains;
-        for (auto net : topological_order) {
-            if (!net_data.count(net))
-                continue;
-            // Updates later on might invalidate a reference taken here to net_data, so iterate over a list of domains
-            // instead
-            startdomains.clear();
-            {
-                auto &nd_map = net_data.at(net);
-                for (auto &startdomain : nd_map)
-                    startdomains.push_back(startdomain.first);
-            }
-            for (auto &start_clk : startdomains) {
-                auto &nd = net_data.at(net).at(start_clk);
-                if (nd.false_startpoint)
-                    continue;
-                const auto net_arrival = nd.max_arrival;
-                const auto net_length_plus_one = nd.max_path_length + 1;
-                nd.min_remaining_budget = clk_period;
-                for (auto &usr : net->users) {
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
-                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
-                    auto usr_arrival = net_arrival + net_delay;
-
-                    if (portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || portClass == TMG_CLOCK_INPUT) {
-                        // Skip
-                    } else {
-                        // Iterate over all output ports on the same cell as the sink
-                        for (auto port : usr.cell->ports) {
-                            if (port.second.type != PORT_OUT || !port.second.net)
-                                continue;
-                            DelayQuad comb_delay;
-                            // Look up delay through this path
-                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                            if (!is_path)
-                                continue;
-                            auto &data = net_data[port.second.net][start_clk];
-                            auto &arrival = data.max_arrival;
-                            arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
-                            auto &path_length = data.max_path_length;
-                            path_length = std::max(path_length, net_length_plus_one);
-                        }
-                    }
-                }
-            }
-        }
-
-        dict<ClockPair, std::pair<delay_t, NetInfo *>> crit_nets;
-
-        // Now go backwards topologically to determine the minimum path slack, and to distribute all path slack evenly
-        // between all nets on the path
-        for (auto net : boost::adaptors::reverse(topological_order)) {
-            if (!net_data.count(net))
-                continue;
-            auto &nd_map = net_data.at(net);
-            for (auto &startdomain : nd_map) {
-                auto &nd = startdomain.second;
-                // Ignore false startpoints
-                if (nd.false_startpoint)
-                    continue;
-                const delay_t net_length_plus_one = nd.max_path_length + 1;
-                auto &net_min_remaining_budget = nd.min_remaining_budget;
-                for (auto &usr : net->users) {
-                    auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
-                    int port_clocks;
-                    TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks);
-                    if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
-                        auto process_endpoint = [&](IdString clksig, ClockEdge edge, delay_t setup) {
-                            const auto net_arrival = nd.max_arrival;
-                            const auto endpoint_arrival = net_arrival + net_delay + setup;
-                            delay_t period;
-                            // Set default period
-                            if (edge == startdomain.first.edge) {
-                                period = clk_period;
-                            } else {
-                                period = clk_period / 2;
-                            }
-                            if (clksig != async_clock) {
-                                if (ctx->nets.at(clksig)->clkconstr) {
-                                    if (edge == startdomain.first.edge) {
-                                        // same edge
-                                        period = ctx->nets.at(clksig)->clkconstr->period.minDelay();
-                                    } else if (edge == RISING_EDGE) {
-                                        // falling -> rising
-                                        period = ctx->nets.at(clksig)->clkconstr->low.minDelay();
-                                    } else if (edge == FALLING_EDGE) {
-                                        // rising -> falling
-                                        period = ctx->nets.at(clksig)->clkconstr->high.minDelay();
-                                    }
-                                }
-                            }
-                            auto path_budget = period - endpoint_arrival;
-
-                            if (update) {
-                                auto budget_share = path_budget / net_length_plus_one;
-                                net_min_remaining_budget =
-                                        std::min(net_min_remaining_budget, path_budget - budget_share);
-                            }
-
-                            if (path_budget < min_slack)
-                                min_slack = path_budget;
-
-                            if (slack_histogram) {
-                                int slack_ps = ctx->getDelayNS(path_budget) * 1000;
-                                (*slack_histogram)[slack_ps]++;
-                            }
-                            ClockEvent dest_ev{clksig, edge};
-                            ClockPair clockPair{startdomain.first, dest_ev};
-                            nd.arrival_time[dest_ev] = std::max(nd.arrival_time[dest_ev], endpoint_arrival);
-
-                            // Store the detailed timing for each net and user (a.k.a. sink)
-                            if (detailed_net_timings) {
-                                NetSinkTiming sink_timing;
-                                sink_timing.clock_pair = clockPair;
-                                sink_timing.cell_port = std::make_pair(usr.cell->name, usr.port);
-                                sink_timing.delay = endpoint_arrival;
-
-                                (*detailed_net_timings)[net->name].push_back(sink_timing);
-                            }
-
-                            if (crit_path) {
-                                if (!crit_nets.count(clockPair) || crit_nets.at(clockPair).first < endpoint_arrival) {
-                                    crit_nets[clockPair] = std::make_pair(endpoint_arrival, net);
-                                    (*crit_path)[clockPair].path_delay = endpoint_arrival;
-                                    (*crit_path)[clockPair].path_period = period;
-                                    (*crit_path)[clockPair].ports.clear();
-                                    (*crit_path)[clockPair].ports.push_back(&usr);
-                                }
-                            }
-                        };
-                        if (portClass == TMG_REGISTER_INPUT) {
-                            for (int i = 0; i < port_clocks; i++) {
-                                TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, i);
-                                const NetInfo *clknet = usr.cell->getPort(clkInfo.clock_port);
-                                IdString clksig = clknet ? clknet->name : async_clock;
-                                process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, clkInfo.setup.maxDelay());
-                            }
-                        } else {
-                            process_endpoint(async_clock, RISING_EDGE, 0);
-                        }
-
-                    } else if (update) {
-
-                        // Iterate over all output ports on the same cell as the sink
-                        for (const auto &port : usr.cell->ports) {
-                            if (port.second.type != PORT_OUT || !port.second.net)
-                                continue;
-                            DelayQuad comb_delay;
-                            bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
-                            if (!is_path)
-                                continue;
-                            if (net_data.count(port.second.net) &&
-                                net_data.at(port.second.net).count(startdomain.first)) {
-                                auto path_budget =
-                                        net_data.at(port.second.net).at(startdomain.first).min_remaining_budget;
-                                auto budget_share = path_budget / net_length_plus_one;
-                                net_min_remaining_budget =
-                                        std::min(net_min_remaining_budget, path_budget - budget_share);
-                            }
-                        }
-                    }
-                }
-            }
-        }
-
-        if (crit_path) {
-            // Walk backwards from the most critical net
-            for (auto crit_pair : crit_nets) {
-                NetInfo *crit_net = crit_pair.second.second;
-                auto &cp_ports = (*crit_path)[crit_pair.first].ports;
-                while (crit_net) {
-                    const PortInfo *crit_ipin = nullptr;
-                    delay_t max_arrival = std::numeric_limits<delay_t>::min();
-                    // Look at all input ports on its driving cell
-                    for (const auto &port : crit_net->driver.cell->ports) {
-                        if (port.second.type != PORT_IN || !port.second.net)
-                            continue;
-                        DelayQuad comb_delay;
-                        bool is_path =
-                                ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
-                        if (!is_path)
-                            continue;
-                        // If input port is influenced by a clock, skip
-                        int port_clocks;
-                        TimingPortClass portClass =
-                                ctx->getPortTimingClass(crit_net->driver.cell, port.first, port_clocks);
-                        if (portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE)
-                            continue;
-                        // And find the fanin net with the latest arrival time
-                        if (net_data.count(port.second.net) &&
-                            net_data.at(port.second.net).count(crit_pair.first.start)) {
-                            auto net_arrival = net_data.at(port.second.net).at(crit_pair.first.start).max_arrival;
-                            if (net_delays) {
-                                for (auto &user : port.second.net->users)
-                                    if (user.port == port.first && user.cell == crit_net->driver.cell) {
-                                        net_arrival += ctx->getNetinfoRouteDelay(port.second.net, user);
-                                        break;
-                                    }
-                            }
-                            net_arrival += comb_delay.maxDelay();
-                            if (net_arrival > max_arrival) {
-                                max_arrival = net_arrival;
-                                crit_ipin = &port.second;
-                            }
-                        }
-                    }
-
-                    if (!crit_ipin)
-                        break;
-                    // Now convert PortInfo* into a PortRef*
-                    for (auto &usr : crit_ipin->net->users) {
-                        if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
-                            cp_ports.push_back(&usr);
-                            break;
-                        }
-                    }
-                    crit_net = crit_ipin->net;
-                }
-                std::reverse(cp_ports.begin(), cp_ports.end());
-            }
-        }
-        return min_slack;
-    }
-};
-
-CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
-{
-    CriticalPath report;
-    report.clock_pair = clocks;
-
-    auto &front = crit_path.front();
-    auto &front_port = front->cell->ports.at(front->port);
-    auto &front_driver = front_port.net->driver;
-
-    int port_clocks;
-    auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
-
-    const CellInfo *last_cell = front->cell;
-    IdString last_port = front_driver.port;
-
-    int clock_start = -1;
-    if (portClass == TMG_REGISTER_OUTPUT) {
-        for (int i = 0; i < port_clocks; i++) {
-            TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
-            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
-            if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) {
-                last_port = clockInfo.clock_port;
-                clock_start = i;
-                break;
-            }
-        }
-    }
-
-    for (auto sink : crit_path) {
-
-        auto sink_cell = sink->cell;
-        auto &port = sink_cell->ports.at(sink->port);
-        auto net = port.net;
-        auto &driver = net->driver;
-        auto driver_cell = driver.cell;
-
-        CriticalPath::Segment seg_logic;
-
-        DelayQuad comb_delay;
-        if (clock_start != -1) {
-            auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
-            comb_delay = clockInfo.clockToQ;
-            clock_start = -1;
-            seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
-        } else if (last_port == driver.port) {
-            // Case where we start with a STARTPOINT etc
-            comb_delay = DelayQuad(0);
-            seg_logic.type = CriticalPath::Segment::Type::SOURCE;
-        } else {
-            ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
-            seg_logic.type = CriticalPath::Segment::Type::LOGIC;
-        }
-
-        seg_logic.delay = comb_delay.maxDelay();
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
-        seg_logic.to = std::make_pair(driver_cell->name, driver.port);
-        seg_logic.net = IdString();
-        report.segments.push_back(seg_logic);
-
-        auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
-
-        CriticalPath::Segment seg_route;
-        seg_route.type = CriticalPath::Segment::Type::ROUTING;
-        seg_route.delay = net_delay;
-        seg_route.from = std::make_pair(driver_cell->name, driver.port);
-        seg_route.to = std::make_pair(sink_cell->name, sink->port);
-        seg_route.net = net->name;
-        report.segments.push_back(seg_route);
-
-        last_cell = sink_cell;
-        last_port = sink->port;
-    }
-
-    int clockCount = 0;
-    auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
-    if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
-        auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
-        delay_t setup = sinkClockInfo.setup.maxDelay();
-
-        CriticalPath::Segment seg_logic;
-        seg_logic.type = CriticalPath::Segment::Type::SETUP;
-        seg_logic.delay = setup;
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
-        seg_logic.to = seg_logic.from;
-        seg_logic.net = IdString();
-        report.segments.push_back(seg_logic);
-    }
-
-    return report;
-}
-
-void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure,
-                     bool update_results)
-{
-    auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
-        std::string value;
-        if (e.clock == ctx->id("$async$"))
-            value = std::string("<async>");
-        else
-            value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
-        if (int(value.length()) < field_width)
-            value.insert(value.length(), field_width - int(value.length()), ' ');
-        return value;
-    };
-
-    CriticalPathDataMap crit_paths;
-    DelayFrequency slack_histogram;
-    DetailedNetTimings detailed_net_timings;
-
-    print_path = true;
-    update_results = true;
-    print_histogram = true;
-
-    Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
-                  print_histogram ? &slack_histogram : nullptr,
-                  (update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
-    timing.walk_paths();
-
-    // Use TimingAnalyser to determine clock-to-clock relations
-    TimingAnalyser timingAnalyser(ctx);
-    timingAnalyser.setup(true, true, true, true);
-
-    log("start timingAnalyser.print_report();\n\n");
-    ctx->log_timing_results(true, true, true);
-    log("end timingAnalyser.print_report();\n\n");
-
-    std::string filename = "timingAnalyser.json";
-    std::ofstream f(filename);
-    if (!f)
-        log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
-    ctx->writeJsonReport(f);
-
-    bool report_critical_paths = print_path || print_fmax || update_results;
-
-    dict<IdString, CriticalPath> clock_reports;
-    std::vector<CriticalPath> xclock_reports;
-    dict<IdString, ClockFmax> clock_fmax;
-    std::set<IdString> empty_clocks; // set of clocks with no interior paths
-
-    if (report_critical_paths) {
-
-        for (auto path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            empty_clocks.insert(a.clock);
-            empty_clocks.insert(b.clock);
-        }
-        for (auto path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            if (a.clock != b.clock || a.clock == ctx->id("$async$"))
-                continue;
-            double Fmax;
-            empty_clocks.erase(a.clock);
-            if (a.edge == b.edge)
-                Fmax = 1000 / ctx->getDelayNS(path.second.path_delay);
-            else
-                Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
-            if (!clock_fmax.count(a.clock) || Fmax < clock_fmax.at(a.clock).achieved) {
-                clock_fmax[a.clock].achieved = Fmax;
-                clock_fmax[a.clock].constraint = 0.0f; // Will be filled later
-                clock_reports[a.clock] = build_critical_path_report(ctx, path.first, path.second.ports);
-                clock_reports[a.clock].period = path.second.path_period;
-            }
-        }
-
-        for (auto &path : crit_paths) {
-            const ClockEvent &a = path.first.start;
-            const ClockEvent &b = path.first.end;
-            if (a.clock == b.clock && a.clock != ctx->id("$async$"))
-                continue;
-
-            auto &crit_path = crit_paths.at(path.first).ports;
-            xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
-            xclock_reports.back().period = path.second.path_period;
-        }
-
-        if (clock_reports.empty() && xclock_reports.empty()) {
-            log_info("No Fmax available; no interior timing paths found in design.\n");
-        }
-
-        std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPath &ra, const CriticalPath &rb) {
-            const auto &a = ra.clock_pair;
-            const auto &b = rb.clock_pair;
-
-            if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
-                return true;
-            if (a.start.clock.str(ctx) > b.start.clock.str(ctx))
-                return false;
-            if (a.start.edge < b.start.edge)
-                return true;
-            if (a.start.edge > b.start.edge)
-                return false;
-            if (a.end.clock.str(ctx) < b.end.clock.str(ctx))
-                return true;
-            if (a.end.clock.str(ctx) > b.end.clock.str(ctx))
-                return false;
-            if (a.end.edge < b.end.edge)
-                return true;
-            return false;
-        });
-
-        for (auto &clock : clock_reports) {
-            float target = ctx->setting<float>("target_freq") / 1e6;
-            if (ctx->nets.at(clock.first)->clkconstr)
-                target = 1000 / ctx->getDelayNS(ctx->nets.at(clock.first)->clkconstr->period.minDelay());
-            clock_fmax[clock.first].constraint = target;
-        }
-    }
-
-    // Print critical paths
-    if (print_path) {
-
-        static auto print_net_source = [ctx](const NetInfo *net) {
-            // Check if this net is annotated with a source list
-            auto sources = net->attrs.find(ctx->id("src"));
-            if (sources == net->attrs.end()) {
-                // No sources for this net, can't print anything
-                return;
-            }
-
-            // Sources are separated by pipe characters.
-            // There is no guaranteed ordering on sources, so we just print all
-            auto sourcelist = sources->second.as_string();
-            std::vector<std::string> source_entries;
-            size_t current = 0, prev = 0;
-            while ((current = sourcelist.find("|", prev)) != std::string::npos) {
-                source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-                prev = current + 1;
-            }
-            // Ensure we emplace the final entry
-            source_entries.emplace_back(sourcelist.substr(prev, current - prev));
-
-            // Iterate and print our source list at the correct indentation level
-            log_info("               Defined in:\n");
-            for (auto entry : source_entries) {
-                log_info("                 %s\n", entry.c_str());
-            }
-        };
-
-        // A helper function for reporting one critical path
-        auto print_path_report = [ctx](const CriticalPath &path) {
-            delay_t total = 0, logic_total = 0, route_total = 0;
-
-            log_info("curr total\n");
-            for (const auto &segment : path.segments) {
-
-                total += segment.delay;
-
-                if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
-                    segment.type == CriticalPath::Segment::Type::SOURCE ||
-                    segment.type == CriticalPath::Segment::Type::LOGIC ||
-                    segment.type == CriticalPath::Segment::Type::SETUP) {
-                    logic_total += segment.delay;
-
-                    const std::string type_name =
-                            (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
-
-                    log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
-                             type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-                } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
-                    route_total += segment.delay;
-
-                    const auto &driver = ctx->cells.at(segment.from.first);
-                    const auto &sink = ctx->cells.at(segment.to.first);
-
-                    auto driver_loc = ctx->getBelLocation(driver->bel);
-                    auto sink_loc = ctx->getBelLocation(sink->bel);
-
-                    log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                             ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
-                             sink_loc.y);
-                    log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-
-                    const NetInfo *net = ctx->nets.at(segment.net).get();
-
-                    if (ctx->verbose) {
-
-                        PortRef sink_ref;
-                        sink_ref.cell = sink.get();
-                        sink_ref.port = segment.to.second;
-
-                        auto driver_wire = ctx->getNetinfoSourceWire(net);
-                        auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
-                        log_info("                 prediction: %f ns estimate: %f ns\n",
-                                 ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
-                                 ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
-                        auto cursor = sink_wire;
-                        delay_t delay;
-                        while (driver_wire != cursor) {
-#ifdef ARCH_ECP5
-                            if (net->is_global)
-                                break;
-#endif
-                            auto it = net->wires.find(cursor);
-                            assert(it != net->wires.end());
-                            auto pip = it->second.pip;
-                            NPNR_ASSERT(pip != PipId());
-                            delay = ctx->getPipDelay(pip).maxDelay();
-                            log_info("                 %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
-                            cursor = ctx->getPipSrcWire(pip);
-                        }
-                    }
-
-                    if (!ctx->disable_critical_path_source_print) {
-                        print_net_source(net);
-                    }
-                }
-            }
-            log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
-        };
-
-        // Single domain paths
-        for (auto &clock : clock_reports) {
-            log_break();
-            std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
-                                                                                   : std::string("posedge");
-            std::string end =
-                    clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
-            log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
-                     end.c_str());
-            auto &report = clock.second;
-            print_path_report(report);
-        }
-
-        // Cross-domain paths
-        for (auto &report : xclock_reports) {
-            log_break();
-            std::string start = format_event(report.clock_pair.start);
-            std::string end = format_event(report.clock_pair.end);
-            log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
-            print_path_report(report);
-        }
-    }
-
-    if (print_fmax) {
-        log_break();
-
-        unsigned max_width = 0;
-        for (auto &clock : clock_reports)
-            max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
-
-        for (auto &clock : clock_reports) {
-            const auto &clock_name = clock.first.str(ctx);
-            const int width = max_width - clock_name.size();
-
-            float fmax = clock_fmax[clock.first].achieved;
-            float target = clock_fmax[clock.first].constraint;
-            bool passed = target < fmax;
-
-            if (!warn_on_failure || passed)
-                log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                         clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
-                log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                            clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            else
-                log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
-                                   clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-        }
-        log_break();
-
-        // All clock to clock delays
-        const auto &clock_delays = timingAnalyser.get_clock_delays();
-
-        // Clock to clock delays for xpaths
-        dict<ClockPair, delay_t> xclock_delays;
-        for (auto &report : xclock_reports) {
-            const auto &clock1_name = report.clock_pair.start.clock;
-            const auto &clock2_name = report.clock_pair.end.clock;
-
-            const auto key = std::make_pair(clock1_name, clock2_name);
-            if (clock_delays.count(key)) {
-                xclock_delays[report.clock_pair] = clock_delays.at(key);
-            }
-        }
-
-        unsigned max_width_xca = 0;
-        unsigned max_width_xcb = 0;
-        for (auto &report : xclock_reports) {
-            max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
-            max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
-        }
-
-        // Check and report xpath delays for related clocks
-        if (!xclock_reports.empty()) {
-            for (auto &report : xclock_reports) {
-                const auto &clock_a = report.clock_pair.start.clock;
-                const auto &clock_b = report.clock_pair.end.clock;
-
-                const auto key = std::make_pair(clock_a, clock_b);
-                if (!clock_delays.count(key)) {
-                    continue;
-                }
-
-                delay_t path_delay = 0;
-                for (const auto &segment : report.segments) {
-                    path_delay += segment.delay;
-                }
-
-                // Compensate path delay for clock-to-clock delay. If the
-                // result is negative then only the latter matters. Otherwise
-                // the compensated path delay is taken.
-                auto clock_delay = clock_delays.at(key);
-                path_delay -= clock_delay;
-
-                float fmax = std::numeric_limits<float>::infinity();
-                if (path_delay < 0) {
-                    fmax = 1e3f / ctx->getDelayNS(clock_delay);
-                } else if (path_delay > 0) {
-                    fmax = 1e3f / ctx->getDelayNS(path_delay);
-                }
-
-                // Both clocks are related so they should have the same
-                // frequency. However, they may get different constraints from
-                // user input. In case of only one constraint preset take it,
-                // otherwise get the worst case (min.)
-                float target;
-                if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_a).constraint;
-                } else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
-                    target = clock_fmax.at(clock_b).constraint;
-                } else {
-                    target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
-                }
-
-                bool passed = target < fmax;
-
-                auto ev_a = format_event(report.clock_pair.start, max_width_xca);
-                auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
-
-                if (!warn_on_failure || passed)
-                    log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
-                             fmax, passed ? "PASS" : "FAIL", target);
-                else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
-                         bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
-                    log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-                else
-                    log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
-                                       ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
-            }
-            log_break();
-        }
-
-        // Report clock delays for xpaths
-        if (!clock_delays.empty()) {
-            for (auto &pair : xclock_delays) {
-                auto ev_a = format_event(pair.first.start, max_width_xca);
-                auto ev_b = format_event(pair.first.end, max_width_xcb);
-
-                delay_t delay = pair.second;
-                if (pair.first.start.edge != pair.first.end.edge) {
-                    delay /= 2;
-                }
-
-                log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
-                         ctx->getDelayNS(delay));
-            }
-
-            log_break();
-        }
-
-        for (auto &eclock : empty_clocks) {
-            if (eclock != ctx->id("$async$"))
-                log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
-        }
-        log_break();
-
-        int start_field_width = 0, end_field_width = 0;
-        for (auto &report : xclock_reports) {
-            start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
-            end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
-        }
-
-        for (auto &report : xclock_reports) {
-            const ClockEvent &a = report.clock_pair.start;
-            const ClockEvent &b = report.clock_pair.end;
-            delay_t path_delay = 0;
-            for (const auto &segment : report.segments) {
-                path_delay += segment.delay;
-            }
-            auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
-            log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
-        }
-        log_break();
-    }
-
-    if (print_histogram && slack_histogram.size() > 0) {
-        unsigned num_bins = 20;
-        unsigned bar_width = 60;
-        auto min_slack = slack_histogram.begin()->first;
-        auto max_slack = slack_histogram.rbegin()->first;
-        auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
-        std::vector<unsigned> bins(num_bins);
-        unsigned max_freq = 0;
-        for (const auto &i : slack_histogram) {
-            int bin_idx = int((i.first - min_slack) / bin_size);
-            if (bin_idx < 0)
-                bin_idx = 0;
-            else if (bin_idx >= int(num_bins))
-                bin_idx = num_bins - 1;
-            auto &bin = bins.at(bin_idx);
-            bin += i.second;
-            max_freq = std::max(max_freq, bin);
-        }
-        bar_width = std::min(bar_width, max_freq);
-
-        log_break();
-        log_info("Slack histogram:\n");
-        log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
-        log_info("         + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
-        for (unsigned i = 0; i < num_bins; ++i)
-            log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
-                     std::string(bins[i] * bar_width / max_freq, '*').c_str(),
-                     (bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
-    }
-
-    // Update timing results in the context
-    if (update_results) {
-        auto &results = ctx->timing_result;
-
-        results.clock_fmax = std::move(clock_fmax);
-        results.clock_paths = std::move(clock_reports);
-        results.xclock_paths = std::move(xclock_reports);
-
-        results.detailed_net_timings = std::move(detailed_net_timings);
-    }
-
-    std::string filename2 = "timing_old.json";
-    std::ofstream f2(filename2);
-    if (!f)
-        log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
-    ctx->writeJsonReport(f2);
-}
-
-NEXTPNR_NAMESPACE_END

From 240f89081f9be873ecfbc8159955cb3efeab68a5 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Fri, 23 Jun 2023 14:14:12 +0200
Subject: [PATCH 420/712] Add back error/warning for combinational loops

---
 common/kernel/timing.cc | 23 +++++++++++++++--------
 common/kernel/timing.h  |  1 -
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index aec9feaf16..1d9deca568 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -206,8 +206,10 @@ void TimingAnalyser::topo_sort()
             }
         }
     }
+
+    bool ignore_loops = bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false);
     bool no_loops = topo.sort();
-    if (!no_loops && verbose_mode) {
+    if (!no_loops && !ignore_loops) {
         log_info("Found %d combinational loops:\n", int(topo.loops.size()));
         int i = 0;
         for (auto &loop : topo.loops) {
@@ -217,6 +219,11 @@ void TimingAnalyser::topo_sort()
                          ctx->nameOf(port_info(port).net));
             }
         }
+
+        if (ctx->force)
+            log_warning("Timing analysis failed due to combinational loops.\n");
+        else
+            log_error("Timing analysis failed due to combinational loops.\n");
     }
     have_loops = !no_loops;
     std::swap(topological_order, topo.sorted);
@@ -661,9 +668,6 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 
                 auto dp = domain_pair_id(launch, capture);
 
-                auto l = domains.at(launch);
-                auto c = domains.at(capture);
-
                 delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
                 if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
                     domain_delay[dp] = delay;
@@ -814,6 +818,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     }
 
+    pool<std::pair<IdString, IdString>> visited;
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
@@ -824,9 +829,13 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         int port_clocks;
         auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
 
-        if (portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN) {
+        // combinational loop
+        if (!visited.insert(std::make_pair(cell->name, port.name)).second)
+            break;
+
+        if (portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN)
             crit_path_rev.emplace_back(PortRef{cell, port.name});
-        }
+
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
 
@@ -1023,8 +1032,6 @@ void TimingAnalyser::build_slack_histogram_report()
                 for (auto &arr : pd.arrival) {
                     auto &launch = domains.at(arr.first).key;
 
-                    // @gatecat: old timing analysis includes async path
-                    // The slack doesn't make much sense so I filter it out.
                     if (launch.clock != capture.clock || launch.is_async())
                         continue;
 
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 0a0f3eee71..2610c618d9 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -99,7 +99,6 @@ struct TimingAnalyser
     TimingResult &get_timing_result() { return result; }
 
     bool setup_only = false;
-    bool verbose_mode = false;
     bool have_loops = false;
     bool updated_domains = false;
 

From 1fdd683344fd1a3c5e179f868d952e1b0733cdc7 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Sun, 25 Jun 2023 08:57:48 +0200
Subject: [PATCH 421/712] Do not use C++20 struct initilisation

---
 common/kernel/timing.cc | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 1d9deca568..368132657b 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -753,8 +753,10 @@ void TimingAnalyser::build_detailed_net_timing_report()
                     auto &capture = domains.at(req.first).key;
 
                     NetSinkTiming sink_timing;
-                    sink_timing.clock_pair = ClockPair{.start = ClockEvent{.clock = launch.clock, .edge = launch.edge},
-                                                       .end = ClockEvent{.clock = capture.clock, .edge = capture.edge}};
+                    sink_timing.clock_pair.start.clock = launch.clock;
+                    sink_timing.clock_pair.start.edge = launch.edge;
+                    sink_timing.clock_pair.end.clock = capture.clock;
+                    sink_timing.clock_pair.end.edge = capture.edge;
                     sink_timing.cell_port = std::make_pair(pd.cell_port.cell, pd.cell_port.port);
                     sink_timing.delay = arr.second.value.max_delay;
 
@@ -800,8 +802,10 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto &launch = domains.at(dp.key.launch).key;
     auto &capture = domains.at(dp.key.capture).key;
 
-    report.clock_pair = ClockPair{.start = ClockEvent{.clock = launch.clock, .edge = launch.edge},
-                                  .end = ClockEvent{.clock = capture.clock, .edge = capture.edge}};
+    report.clock_pair.start.clock = launch.clock;
+    report.clock_pair.start.edge = launch.edge;
+    report.clock_pair.end.clock = capture.clock;
+    report.clock_pair.end.edge = capture.edge;
 
     report.period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
     if (launch.edge != capture.edge) {

From 053dfc98f04699a51378f6238bae3afb877027d2 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Wed, 28 Jun 2023 09:06:22 +0200
Subject: [PATCH 422/712] use std::numeric_limits instead of macros

---
 common/kernel/timing_log.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index dd2814a9df..2a2137b5fc 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -321,8 +321,8 @@ static void log_histogram(Context *ctx, TimingResult &result)
     unsigned num_bins = 20;
     unsigned bar_width = 60;
 
-    int min_slack = INT_MAX;
-    int max_slack = INT_MIN;
+    int min_slack = std::numeric_limits<int>::max();
+    int max_slack = std::numeric_limits<int>::min();
 
     for (const auto &i : result.slack_histogram) {
         if (i.first < min_slack)

From a01e2c9068896ce7ed83449bed30b2da8ea1cbef Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 23 Aug 2023 10:46:46 +0200
Subject: [PATCH 423/712] nexus: Be robust to parameters shorter than expected

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/pack.cc | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 4ebe68d1f1..d41766dc51 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -82,19 +82,22 @@ Property Arch::parse_lattice_param(const Property &val, IdString prop, int width
             }
             temp = Property(ival);
         }
-
-        for (auto b : temp.str.substr(width)) {
-            if (b == Property::S1)
-                log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop), width);
+        if (int(temp.size()) > width) {
+            for (auto b : temp.str.substr(width)) {
+                if (b == Property::S1)
+                    log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop), width);
+            }
         }
         temp.update_intval();
         return temp.extract(0, width);
     } else {
-        for (auto b : val.str.substr(width)) {
-            if (b == Property::S1)
-                log_error("Found bitvector value for property %s.%s with width greater than %d - perhaps a string was "
-                          "converted to bits?\n",
-                          ci, nameOf(prop), width);
+        if (int(val.str.size()) > width) {
+            for (auto b : val.str.substr(width)) {
+                if (b == Property::S1)
+                    log_error("Found bitvector value for property %s.%s with width greater than %d - perhaps a string was "
+                              "converted to bits?\n",
+                              ci, nameOf(prop), width);
+            }
         }
         return val.extract(0, width);
     }

From 977180524a5130f432cba0f37f9b38d24563d3ff Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 23 Aug 2023 11:00:49 +0200
Subject: [PATCH 424/712] nexus: More DPHY clock ports that require general
 routing hop

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/constids.inc | 3 +++
 nexus/global.cc    | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/nexus/constids.inc b/nexus/constids.inc
index 596d064cb5..19f34523c8 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -510,6 +510,9 @@ X(U2END2)
 X(U3END3)
 X(UED0THEN)
 X(URXCKINE)
+X(UCENCK)
+X(U3TDE5CK)
+X(UTXCKE)
 
 X(GENERAL)
 
diff --git a/nexus/global.cc b/nexus/global.cc
index 0792715dbd..ec6f66a280 100644
--- a/nexus/global.cc
+++ b/nexus/global.cc
@@ -166,8 +166,8 @@ struct NexusGlobalRouter
 
     bool is_relaxed_sink(const PortRef &sink) const
     {
-        // This DPHY clock port can't be routed without going through some general routing
-        if (sink.cell->type == id_DPHY_CORE && sink.port == id_URXCKINE)
+        // These DPHY clock ports can't be routed without going through some general routing
+        if (sink.cell->type == id_DPHY_CORE && sink.port.in(id_URXCKINE, id_UCENCK, id_UTXCKE, id_U3TDE5CK))
             return true;
         // Cases where global clocks are driving fabric
         if ((sink.cell->type == id_OXIDE_COMB && sink.port != id_WCK) ||

From e08471dfaf49c1c0eb0ea53a85db5f42b5833a53 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 24 Aug 2023 08:55:53 +0200
Subject: [PATCH 425/712] router2: Improve robustness when critical nets
 conflict

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/route/router2.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index a54c58c92a..db8885d47f 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -626,7 +626,7 @@ struct Router2
         int dst_wire_idx = wire_to_idx.at(dst_wire);
         // Calculate a timing weight based on criticality
         float crit = get_arc_crit(net, i);
-        float crit_weight = (1.0f - std::pow(crit, 2));
+        float crit_weight = std::max<float>(0.05f, (1.0f - std::pow(crit, 2)));
         ROUTE_LOG_DBG("     crit=%.3f crit_weight=%.3f\n", crit, crit_weight);
         // Check if arc was already done _in this iteration_
         if (t.processed_sinks.count(dst_wire))

From 688f1ba983eb8d7fd29858ae7b7c313869ec2598 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 28 Aug 2023 15:05:04 +0200
Subject: [PATCH 426/712] widelut support for xo2/xo3/xo3d

---
 machxo2/pack.cc | 187 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 187 insertions(+)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index e31d506620..f20c9378a1 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -286,6 +286,192 @@ class MachXO2Packer
         return false;
     }
 
+    // Pass to pack LUT5s into a newly created slice
+    void pack_lut5xs()
+    {
+        log_info("Packing LUT5-7s...\n");
+
+        // Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
+        auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
+            NetInfo *f1 = lut5->getPort(id_F1);
+            NPNR_ASSERT(f1 != nullptr);
+            NPNR_ASSERT(f1->driver.cell != nullptr);
+            return f1->driver.cell;
+        };
+
+        dict<IdString, std::pair<CellInfo *, CellInfo *>> lut5_roots, lut6_roots, lut7_roots;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_pfumx(ctx, ci)) {
+                NetInfo *f0 = ci->ports.at(id_BLUT).net;
+
+                if (f0 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
+                NetInfo *f1 = ci->ports.at(id_ALUT).net;
+                if (f1 == nullptr)
+                    log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
+
+                CellInfo *lut0 =
+                        (f0->driver.cell && f0->driver.cell->type == id_TRELLIS_COMB && f0->driver.port == id_F)
+                                ? f0->driver.cell
+                                : nullptr;
+                CellInfo *lut1 =
+                        (f1->driver.cell && f1->driver.cell->type == id_TRELLIS_COMB && f1->driver.port == id_F)
+                                ? f1->driver.cell
+                                : nullptr;
+                if (lut0 == nullptr || lut0->cluster != ClusterId())
+                    log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                if (lut1 == nullptr || lut1->cluster != ClusterId())
+                    log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
+                lut0->addInput(id_F1);
+                lut0->addInput(id_M);
+                lut0->addOutput(id_OFX);
+
+                ci->movePortTo(id_Z, lut0, id_OFX);
+                ci->movePortTo(id_ALUT, lut0, id_F1);
+                ci->movePortTo(id_C0, lut0, id_M);
+                ci->disconnectPort(id_BLUT);
+
+                lut5_roots[lut0->name] = {lut0, lut1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT6s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
+                if (ofx0_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
+                if (ofx0_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb0 = (ofx0_0->driver.cell && ofx0_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_0->driver.port == id_OFX)
+                                          ? ofx0_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb1 = (ofx0_1->driver.cell && ofx0_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx0_1->driver.port == id_OFX)
+                                          ? ofx0_1->driver.cell
+                                          : nullptr;
+                if (comb0 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb0->name))
+                    continue;
+
+                if (comb1 == nullptr) {
+                    if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z))
+                        log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
+                                  "('%s.%s')\n",
+                                  ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
+                                  ofx0_0->driver.port.c_str(ctx));
+                    continue;
+                }
+                if (lut6_roots.count(comb1->name))
+                    continue;
+                if (ctx->verbose)
+                    log_info("   mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
+                comb0 = get_comb1_from_lut5(comb0);
+                comb1 = get_comb1_from_lut5(comb1);
+
+                comb1->addInput(id_FXA);
+                comb1->addInput(id_FXB);
+                comb1->addInput(id_M);
+                comb1->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb1, id_FXA);
+                ci->movePortTo(id_D1, comb1, id_FXB);
+                ci->movePortTo(id_SD, comb1, id_M);
+                ci->movePortTo(id_Z, comb1, id_OFX);
+                lut6_roots[comb1->name] = {comb0, comb1};
+                packed_cells.insert(ci->name);
+            }
+        }
+        flush_cells();
+        // Pack LUT7s
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_l6mux(ctx, ci)) {
+                NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
+                if (ofx1_0 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
+                NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
+                if (ofx1_1 == nullptr)
+                    log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
+                CellInfo *comb1 = (ofx1_0->driver.cell && ofx1_0->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_0->driver.port == id_OFX)
+                                          ? ofx1_0->driver.cell
+                                          : nullptr;
+                CellInfo *comb3 = (ofx1_1->driver.cell && ofx1_1->driver.cell->type == id_TRELLIS_COMB &&
+                                   ofx1_1->driver.port == id_OFX)
+                                          ? ofx1_1->driver.cell
+                                          : nullptr;
+                if (comb1 == nullptr)
+                    log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
+                              ofx1_0->driver.port.c_str(ctx));
+                if (comb3 == nullptr)
+                    log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
+                              ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
+                              ofx1_1->driver.port.c_str(ctx));
+
+                NetInfo *fxa_0 = comb1->ports.at(id_FXA).net;
+                if (fxa_0 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb1->name.c_str(ctx));
+                NetInfo *fxa_1 = comb3->ports.at(id_FXA).net;
+                if (fxa_1 == nullptr)
+                    log_error("SLICE '%s' has disconnected port 'FXA'\n", comb3->name.c_str(ctx));
+
+                CellInfo *comb2 = net_driven_by(
+                        ctx, fxa_1,
+                        [](const Context *ctx, const CellInfo *ci) {
+                            (void)ctx;
+                            return ci->type == id_TRELLIS_COMB;
+                        },
+                        id_OFX);
+                if (comb2 == nullptr)
+                    log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
+                              comb3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
+                              fxa_1->driver.port.c_str(ctx));
+                comb2 = get_comb1_from_lut5(comb2);
+                comb2->addInput(id_FXA);
+                comb2->addInput(id_FXB);
+                comb2->addInput(id_M);
+                comb2->addOutput(id_OFX);
+                ci->movePortTo(id_D0, comb2, id_FXA);
+                ci->movePortTo(id_D1, comb2, id_FXB);
+                ci->movePortTo(id_SD, comb2, id_M);
+                ci->movePortTo(id_Z, comb2, id_OFX);
+
+                lut7_roots[comb2->name] = {comb1, comb3};
+                packed_cells.insert(ci->name);
+            }
+        }
+
+        for (auto &root : lut7_roots) {
+            auto &cells = root.second;
+            cells.second->cluster = cells.second->name;
+            cells.second->constr_abs_z = true;
+            cells.second->constr_z = (1 << Arch::lc_idx_shift) | Arch::BEL_COMB;
+            rel_constr_cells(cells.second, cells.first, (4 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut6_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.second, cells.first, (2 << Arch::lc_idx_shift));
+        }
+        for (auto &root : lut5_roots) {
+            auto &cells = root.second;
+            rel_constr_cells(cells.first, cells.second, (1 << Arch::lc_idx_shift));
+        }
+        flush_cells();
+    }
+
     // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
     void pack_io()
     {
@@ -1442,6 +1628,7 @@ class MachXO2Packer
         pack_dram();
         pack_carries();
         pack_luts();
+        pack_lut5xs();
         pack_ffs();
         promote_globals();
         place_globals();

From 5497a37de11397c2a48a106f3d7754bd71b63abd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 29 Aug 2023 09:38:06 +0200
Subject: [PATCH 427/712] VLO,VHI support for ECP5

---
 ecp5/pack.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 3b56daa92f..4ef2e92a3e 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -991,6 +991,15 @@ class Ecp5Packer
     {
         log_info("Packing constants..\n");
 
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type.in(ctx->id("VLO"))) {
+                ci->type = id_GND;
+            } else if (ci->type.in(ctx->id("VHI"))) {
+                ci->type = id_VCC;
+            }
+        }
+
         std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, id_LUT4, "$PACKER_GND");
         gnd_cell->params[id_INIT] = Property(0, 16);
         auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));

From b9592093b54d6d0faa2e355d74f172bb857b791d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 30 Aug 2023 15:28:05 +0200
Subject: [PATCH 428/712] Update examples to synth_lattice

---
 machxo2/examples/README.md    | 6 +++---
 machxo2/examples/demo-vhdl.sh | 2 +-
 machxo2/examples/demo.sh      | 2 +-
 machxo2/examples/mitertest.sh | 8 ++++----
 machxo2/examples/simple.sh    | 4 ++--
 machxo2/examples/simtest.sh   | 6 +++---
 6 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index 545afd2649..7d3d3470c9 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -73,7 +73,7 @@ few reasons:
   2. To keep the `gold`/`gate` generation simpler, examples are currently
      assumed to _not_ instantiate MachXO2 simulation primitives directly
     (`FACADE_IO`, `FACADE_FF`, etc).
-  3. `synth_machxo2` runs `deminout` on `inouts` when generating the `gate`
+  3. `synth_lattice` runs `deminout` on `inouts` when generating the `gate`
      module. This is not handled yet when generating the `gold` module.
 
 ## Verilog Examples
@@ -101,9 +101,9 @@ few reasons:
   Defaults to the `nextpnr-machxo2` binary at the root of the `nextpnr` source
   tree. This should be set, for instance, if doing an out-of-tree build of
   `nextpnr-machxo2`.
-* `CELLS_SIM`- Set to the location of `machxo2/cells_sim.v` simulation models.
+* `CELLS_SIM`- Set to the location of `lattice/cells_sim_xo2.v` simulation models.
   Defaults to whatever `yosys-config` associated with the above `YOSYS` binary
-  returns. You may want to set this to `/path/to/yosys/src/share/machxo2/cells_sim.v`
+  returns. You may want to set this to `/path/to/yosys/src/share/lattice/cells_sim_xo2.v`
   if doing development; `yosys-config` cannot find these "before-installation"
   simulation models.
 * `TRELLIS_DB`- Set to the location of the Project Trellis database to use.
diff --git a/machxo2/examples/demo-vhdl.sh b/machxo2/examples/demo-vhdl.sh
index 054b8585dd..1258344912 100644
--- a/machxo2/examples/demo-vhdl.sh
+++ b/machxo2/examples/demo-vhdl.sh
@@ -18,7 +18,7 @@ set -ex
 
 ${YOSYS:-yosys} -p "ghdl --std=08 prims.vhd ${1}.vhd -e;
                     attrmap -tocase LOC
-                    synth_machxo2 -json ${1}-vhdl.json"
+                    synth_lattice -family xo2 -json ${1}-vhdl.json"
 ${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1-vhdl.json --textcfg $1-vhdl.txt
 ecppack --compress $DB_ARG $1-vhdl.txt $1-vhdl.bit
 tinyproga -b $1-vhdl.bit
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
index 8e8a49a6d0..d5c138720c 100644
--- a/machxo2/examples/demo.sh
+++ b/machxo2/examples/demo.sh
@@ -16,7 +16,7 @@ fi
 
 set -ex
 
-${YOSYS:-yosys} -p "read_verilog  $1.v; synth_machxo2 -json $1.json"
+${YOSYS:-yosys} -p "read_verilog  $1.v; synth_lattice -family xo2 -json $1.json"
 ${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1.json --textcfg $1.txt
 ecppack --compress $DB_ARG $1.txt $1.bit
 tinyproga -b $1.bit
diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index 161eaa8861..be01eae6de 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -44,7 +44,7 @@ do_sat() {
                         rename top gold
                         read_verilog ${2}${1}.v
                         rename top gate
-                        read_verilog +/machxo2/cells_sim.v
+                        read_verilog +/lattice/cells_sim_xo2.v
 
                         miter -equiv -make_assert -flatten gold gate ${2}${1}_miter
                         hierarchy -top ${2}${1}_miter
@@ -56,7 +56,7 @@ do_smt() {
                         rename top gold
                         read_verilog ${2}${1}.v
                         rename top gate
-                        read_verilog +/machxo2/cells_sim.v
+                        read_verilog +/lattice/cells_sim_xo2.v
 
                         miter -equiv -make_assert gold gate ${2}${1}_miter
                         hierarchy -top ${2}${1}_miter; proc;
@@ -72,9 +72,9 @@ do_smt() {
 set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
-                    synth_machxo2 -json ${1}.json"
+                    synth_lattice -family xo2 -json ${1}.json"
 ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
-${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v
                     read_json ${2}${1}.json
                     clean -purge
                     write_verilog -noattr -norename ${2}${1}.v"
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 4037fa6f1c..540e7fd286 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -24,10 +24,10 @@ esac
 set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
-                    synth_machxo2 -json ${1}.json
+                    synth_lattice -family xo2 -json ${1}.json
                     show -format png -prefix ${1}"
 ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
-${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v
                     read_json ${2}${1}.json
                     clean -purge
                     show -format png -prefix ${2}${1}
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index eb97719bdd..e50779798f 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -29,11 +29,11 @@ fi
 set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
-                    synth_machxo2 -json ${1}.json"
+                    synth_lattice -family xo2 -json ${1}.json"
 ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json
-${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v
                     read_json ${2}${1}.json
                     clean -purge
                     write_verilog -noattr -norename ${2}${1}.v"
-iverilog -o ${1}_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} ${1}_tb.v ${2}${1}.v
+iverilog -o ${1}_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/lattice/cells_sim_xo2.v`} ${1}_tb.v ${2}${1}.v
 vvp -N ./${1}_simtest

From bc7cd4f20ec7f6753d7170060d3fa53d5181c9eb Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 28 Jun 2023 10:16:29 +1000
Subject: [PATCH 429/712] wip start

---
 himbaechel/family.cmake                  |    2 +-
 himbaechel/uarch/gowin/constids.inc      | 1058 ++++++++++++++++++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py |  115 +++
 3 files changed, 1174 insertions(+), 1 deletion(-)
 create mode 100644 himbaechel/uarch/gowin/constids.inc
 create mode 100644 himbaechel/uarch/gowin/gowin_arch_gen.py

diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake
index 00524623e2..f4d59c0f4c 100644
--- a/himbaechel/family.cmake
+++ b/himbaechel/family.cmake
@@ -1,4 +1,4 @@
-set(HIMBAECHEL_UARCHES "example")
+set(HIMBAECHEL_UARCHES "example;gowin")
 foreach(uarch ${HIMBAECHEL_UARCHES})
     aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES)
     foreach(target ${family_targets})
diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
new file mode 100644
index 0000000000..230abc09cd
--- /dev/null
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -0,0 +1,1058 @@
+X(A0)
+X(B0)
+X(C0)
+X(D0)
+X(A1)
+X(B1)
+X(C1)
+X(D1)
+X(A2)
+X(B2)
+X(C2)
+X(D2)
+X(A3)
+X(B3)
+X(C3)
+X(D3)
+X(A4)
+X(B4)
+X(C4)
+X(D4)
+X(A5)
+X(B5)
+X(C5)
+X(D5)
+X(A6)
+X(B6)
+X(C6)
+X(D6)
+X(A7)
+X(B7)
+X(C7)
+X(D7)
+X(F0)
+X(F1)
+X(F2)
+X(F3)
+X(F4)
+X(F5)
+X(F6)
+X(F7)
+X(Q0)
+X(Q1)
+X(Q2)
+X(Q3)
+X(Q4)
+X(Q5)
+X(Q6)
+X(Q7)
+X(OF0)
+X(OF1)
+X(OF2)
+X(OF3)
+X(OF4)
+X(OF5)
+X(OF6)
+X(OF7)
+X(X01)
+X(X02)
+X(X03)
+X(X04)
+X(X05)
+X(X06)
+X(X07)
+X(X08)
+X(N100)
+X(SN10)
+X(SN20)
+X(N130)
+X(S100)
+X(S130)
+X(E100)
+X(EW10)
+X(EW20)
+X(E130)
+X(W100)
+X(W130)
+X(N200)
+X(N210)
+X(N220)
+X(N230)
+X(N240)
+X(N250)
+X(N260)
+X(N270)
+X(S200)
+X(S210)
+X(S220)
+X(S230)
+X(S240)
+X(S250)
+X(S260)
+X(S270)
+X(E200)
+X(E210)
+X(E220)
+X(E230)
+X(E240)
+X(E250)
+X(E260)
+X(E270)
+X(W200)
+X(W210)
+X(W220)
+X(W230)
+X(W240)
+X(W250)
+X(W260)
+X(W270)
+X(N800)
+X(N810)
+X(N820)
+X(N830)
+X(S800)
+X(S810)
+X(S820)
+X(S830)
+X(E800)
+X(E810)
+X(E820)
+X(E830)
+X(W800)
+X(W810)
+X(W820)
+X(W830)
+X(CLK0)
+X(CLK1)
+X(CLK2)
+X(LSR0)
+X(LSR1)
+X(LSR2)
+X(CE0)
+X(CE1)
+X(CE2)
+X(SEL0)
+X(SEL1)
+X(SEL2)
+X(SEL3)
+X(SEL4)
+X(SEL5)
+X(SEL6)
+X(SEL7)
+X(N101)
+X(N131)
+X(S101)
+X(S131)
+X(E101)
+X(E131)
+X(W101)
+X(W131)
+X(N201)
+X(N211)
+X(N221)
+X(N231)
+X(N241)
+X(N251)
+X(N261)
+X(N271)
+X(S201)
+X(S211)
+X(S221)
+X(S231)
+X(S241)
+X(S251)
+X(S261)
+X(S271)
+X(E201)
+X(E211)
+X(E221)
+X(E231)
+X(E241)
+X(E251)
+X(E261)
+X(E271)
+X(W201)
+X(W211)
+X(W221)
+X(W231)
+X(W241)
+X(W251)
+X(W261)
+X(W271)
+X(N202)
+X(N212)
+X(N222)
+X(N232)
+X(N242)
+X(N252)
+X(N262)
+X(N272)
+X(S202)
+X(S212)
+X(S222)
+X(S232)
+X(S242)
+X(S252)
+X(S262)
+X(S272)
+X(E202)
+X(E212)
+X(E222)
+X(E232)
+X(E242)
+X(E252)
+X(E262)
+X(E272)
+X(W202)
+X(W212)
+X(W222)
+X(W232)
+X(W242)
+X(W252)
+X(W262)
+X(W272)
+X(N804)
+X(N814)
+X(N824)
+X(N834)
+X(S804)
+X(S814)
+X(S824)
+X(S834)
+X(E804)
+X(E814)
+X(E824)
+X(E834)
+X(W804)
+X(W814)
+X(W824)
+X(W834)
+X(N808)
+X(N818)
+X(N828)
+X(N838)
+X(S808)
+X(S818)
+X(S828)
+X(S838)
+X(E808)
+X(E818)
+X(E828)
+X(E838)
+X(W808)
+X(W818)
+X(W828)
+X(W838)
+X(E110)
+X(W110)
+X(E120)
+X(W120)
+X(S110)
+X(N110)
+X(S120)
+X(N120)
+X(E111)
+X(W111)
+X(E121)
+X(W121)
+X(S111)
+X(N111)
+X(S121)
+X(N121)
+X(LB01)
+X(LB11)
+X(LB21)
+X(LB31)
+X(LB41)
+X(LB51)
+X(LB61)
+X(LB71)
+X(GB00)
+X(GB10)
+X(GB20)
+X(GB30)
+X(GB40)
+X(GB50)
+X(GB60)
+X(GB70)
+X(VCC)
+X(VSS)
+X(LT00)
+X(LT10)
+X(LT20)
+X(LT30)
+X(LT02)
+X(LT13)
+X(LT01)
+X(LT04)
+X(LBO0)
+X(LBO1)
+X(SS00)
+X(SS40)
+X(GT00)
+X(GT10)
+X(GBO0)
+X(GBO1)
+X(DI0)
+X(DI1)
+X(DI2)
+X(DI3)
+X(DI4)
+X(DI5)
+X(DI6)
+X(DI7)
+X(CIN0)
+X(CIN1)
+X(CIN2)
+X(CIN3)
+X(CIN4)
+X(CIN5)
+X(COUT0)
+X(COUT1)
+X(COUT2)
+X(COUT3)
+X(COUT4)
+X(COUT5)
+X(VREN)
+
+// wires
+// SN
+X(S10)
+X(S10_loop0)
+X(S13)
+X(S13_loop0)
+X(N10)
+X(N10_loop0)
+X(N13)
+X(N13_loop0)
+X(SN10_loop_n)
+X(SN10_loop_s)
+X(SN20_loop_n)
+X(SN20_loop_s)
+X(S20)
+X(S20_loop0)
+X(S20_loop1)
+X(S21)
+X(S21_loop0)
+X(S21_loop1)
+X(S22)
+X(S22_loop0)
+X(S22_loop1)
+X(S23)
+X(S23_loop0)
+X(S23_loop1)
+X(S24)
+X(S24_loop0)
+X(S24_loop1)
+X(S25)
+X(S25_loop0)
+X(S25_loop1)
+X(S26)
+X(S26_loop0)
+X(S26_loop1)
+X(S27)
+X(S27_loop0)
+X(S27_loop1)
+X(N20)
+X(N20_loop0)
+X(N20_loop1)
+X(N21)
+X(N21_loop0)
+X(N21_loop1)
+X(N22)
+X(N22_loop0)
+X(N22_loop1)
+X(N23)
+X(N23_loop0)
+X(N23_loop1)
+X(N24)
+X(N24_loop0)
+X(N24_loop1)
+X(N25)
+X(N25_loop0)
+X(N25_loop1)
+X(N26)
+X(N26_loop0)
+X(N26_loop1)
+X(N27)
+X(N27_loop0)
+X(N27_loop1)
+X(S80)
+X(S80_loop0)
+X(S80_loop1)
+X(S80_loop2)
+X(S80_loop3)
+X(S80_loop4)
+X(S80_loop5)
+X(S80_loop6)
+X(S80_loop7)
+X(N80)
+X(N80_loop0)
+X(N80_loop1)
+X(N80_loop2)
+X(N80_loop3)
+X(N80_loop4)
+X(N80_loop5)
+X(N80_loop6)
+X(N80_loop7)
+X(S81)
+X(S81_loop0)
+X(S81_loop1)
+X(S81_loop2)
+X(S81_loop3)
+X(S81_loop4)
+X(S81_loop5)
+X(S81_loop6)
+X(S81_loop7)
+X(N81)
+X(N81_loop0)
+X(N81_loop1)
+X(N81_loop2)
+X(N81_loop3)
+X(N81_loop4)
+X(N81_loop5)
+X(N81_loop6)
+X(N81_loop7)
+X(S82)
+X(S82_loop0)
+X(S82_loop1)
+X(S82_loop2)
+X(S82_loop3)
+X(S82_loop4)
+X(S82_loop5)
+X(S82_loop6)
+X(S82_loop7)
+X(N82)
+X(N82_loop0)
+X(N82_loop1)
+X(N82_loop2)
+X(N82_loop3)
+X(N82_loop4)
+X(N82_loop5)
+X(N82_loop6)
+X(N82_loop7)
+X(S83)
+X(S83_loop0)
+X(S83_loop1)
+X(S83_loop2)
+X(S83_loop3)
+X(S83_loop4)
+X(S83_loop5)
+X(S83_loop6)
+X(S83_loop7)
+X(N83)
+X(N83_loop0)
+X(N83_loop1)
+X(N83_loop2)
+X(N83_loop3)
+X(N83_loop4)
+X(N83_loop5)
+X(N83_loop6)
+X(N83_loop7)
+
+// WE
+X(E10)
+X(E10_loop0)
+X(E13)
+X(E13_loop0)
+X(W10)
+X(W10_loop0)
+X(W13)
+X(W13_loop0)
+X(EW10_loop_w)
+X(EW10_loop_e)
+X(EW20_loop_w)
+X(EW20_loop_e)
+// 
+X(E20)
+X(E20_loop0)
+X(E20_loop1)
+X(E21)
+X(E21_loop0)
+X(E21_loop1)
+X(E22)
+X(E22_loop0)
+X(E22_loop1)
+X(E23)
+X(E23_loop0)
+X(E23_loop1)
+X(E24)
+X(E24_loop0)
+X(E24_loop1)
+X(E25)
+X(E25_loop0)
+X(E25_loop1)
+X(E26)
+X(E26_loop0)
+X(E26_loop1)
+X(E27)
+X(E27_loop0)
+X(E27_loop1)
+X(W20)
+X(W20_loop0)
+X(W20_loop1)
+X(W21)
+X(W21_loop0)
+X(W21_loop1)
+X(W22)
+X(W22_loop0)
+X(W22_loop1)
+X(W23)
+X(W23_loop0)
+X(W23_loop1)
+X(W24)
+X(W24_loop0)
+X(W24_loop1)
+X(W25)
+X(W25_loop0)
+X(W25_loop1)
+X(W26)
+X(W26_loop0)
+X(W26_loop1)
+X(W27)
+X(W27_loop0)
+X(W27_loop1)
+//
+X(E80)
+X(E80_loop0)
+X(E80_loop1)
+X(E80_loop2)
+X(E80_loop3)
+X(E80_loop4)
+X(E80_loop5)
+X(E80_loop6)
+X(E80_loop7)
+X(W80)
+X(W80_loop0)
+X(W80_loop1)
+X(W80_loop2)
+X(W80_loop3)
+X(W80_loop4)
+X(W80_loop5)
+X(W80_loop6)
+X(W80_loop7)
+X(E81)
+X(E81_loop0)
+X(E81_loop1)
+X(E81_loop2)
+X(E81_loop3)
+X(E81_loop4)
+X(E81_loop5)
+X(E81_loop6)
+X(E81_loop7)
+X(W81)
+X(W81_loop0)
+X(W81_loop1)
+X(W81_loop2)
+X(W81_loop3)
+X(W81_loop4)
+X(W81_loop5)
+X(W81_loop6)
+X(W81_loop7)
+X(E82)
+X(E82_loop0)
+X(E82_loop1)
+X(E82_loop2)
+X(E82_loop3)
+X(E82_loop4)
+X(E82_loop5)
+X(E82_loop6)
+X(E82_loop7)
+X(W82)
+X(W82_loop0)
+X(W82_loop1)
+X(W82_loop2)
+X(W82_loop3)
+X(W82_loop4)
+X(W82_loop5)
+X(W82_loop6)
+X(W82_loop7)
+X(E83)
+X(E83_loop0)
+X(E83_loop1)
+X(E83_loop2)
+X(E83_loop3)
+X(E83_loop4)
+X(E83_loop5)
+X(E83_loop6)
+X(E83_loop7)
+X(W83)
+X(W83_loop0)
+X(W83_loop1)
+X(W83_loop2)
+X(W83_loop3)
+X(W83_loop4)
+X(W83_loop5)
+X(W83_loop6)
+X(W83_loop7)
+
+// spines
+X(SPINE0)
+X(SPINE1)
+X(SPINE2)
+X(SPINE3)
+X(SPINE4)
+X(SPINE5)
+X(SPINE6)
+X(SPINE7)
+X(SPINE8)
+X(SPINE9)
+X(SPINE10)
+X(SPINE11)
+X(SPINE12)
+X(SPINE13)
+X(SPINE14)
+X(SPINE15)
+X(SPINE16)
+X(SPINE17)
+X(SPINE18)
+X(SPINE19)
+X(SPINE20)
+X(SPINE21)
+X(SPINE22)
+X(SPINE23)
+X(SPINE24)
+X(SPINE25)
+X(SPINE26)
+X(SPINE27)
+X(SPINE28)
+X(SPINE29)
+X(SPINE30)
+X(SPINE31)
+
+// slice items
+X(SLICE)
+X(CLK)
+X(LSR)
+X(CE)
+X(Q)
+X(F)
+X(A)
+X(B)
+X(C)
+X(D)
+// iob items
+X(IOB)
+X(I)
+X(O)
+X(IO)
+X(OE)
+X(OB)
+X(IB)
+
+// bels
+X(DFF0)
+X(DFF1)
+X(DFF2)
+X(DFF3)
+X(DFF4)
+X(DFF5)
+
+X(LUT0)
+X(LUT1)
+X(LUT2)
+X(LUT3)
+X(LUT4)
+X(LUT5)
+X(LUT6)
+X(LUT7)
+
+X(IOBA)
+X(IOBB)
+X(IOBC)
+X(IOBD)
+X(IOBE)
+X(IOBF)
+X(IOBG)
+X(IOBH)
+X(IOBI)
+X(IOBJ)
+
+// misc
+X(DUMMY_CELL)
+
+// simplified iobs
+X(IOBS)
+X(IOBAS)
+X(IOBBS)
+X(IOBCS)
+X(IOBDS)
+X(IOBES)
+X(IOBFS)
+X(IOBGS)
+X(IOBHS)
+X(IOBIS)
+X(IOBJS)
+
+// long wires
+X(BUFS)
+X(BUFS0)
+X(BUFS1)
+X(BUFS2)
+X(BUFS3)
+X(BUFS4)
+X(BUFS5)
+X(BUFS6)
+X(BUFS7)
+X(LWT0)
+X(LWB0)
+X(LWT1)
+X(LWB1)
+X(LWT2)
+X(LWB2)
+X(LWT3)
+X(LWB3)
+X(LWT4)
+X(LWB4)
+X(LWT5)
+X(LWB5)
+X(LWT6)
+X(LWB6)
+X(LWT7)
+X(LWB7)
+X(LWSPINETL0)
+X(LWSPINETL1)
+X(LWSPINETL2)
+X(LWSPINETL3)
+X(LWSPINETL4)
+X(LWSPINETL5)
+X(LWSPINETL6)
+X(LWSPINETL7)
+X(LWSPINETR0)
+X(LWSPINETR1)
+X(LWSPINETR2)
+X(LWSPINETR3)
+X(LWSPINETR4)
+X(LWSPINETR5)
+X(LWSPINETR6)
+X(LWSPINETR7)
+X(LWSPINEBL0)
+X(LWSPINEBL1)
+X(LWSPINEBL2)
+X(LWSPINEBL3)
+X(LWSPINEBL4)
+X(LWSPINEBL5)
+X(LWSPINEBL6)
+X(LWSPINEBL7)
+X(LWSPINEBR0)
+X(LWSPINEBR1)
+X(LWSPINEBR2)
+X(LWSPINEBR3)
+X(LWSPINEBR4)
+X(LWSPINEBR5)
+X(LWSPINEBR6)
+X(LWSPINEBR7)
+X(LWI0)
+X(LWI1)
+X(LWI2)
+X(LWI3)
+X(LWI4)
+X(LWI5)
+X(LWI6)
+X(LWI7)
+X(LWO0)
+X(LWO1)
+X(LWO2)
+X(LWO3)
+X(LWO4)
+X(LWO5)
+X(LWO6)
+X(LWO7)
+
+// IOLOGIC
+X(TX)
+X(TX0)
+X(TX1)
+X(TX2)
+X(TX3)
+X(FCLK)
+X(PCLK)
+X(CALIB)
+X(DAADJ0)
+X(DAADJ1)
+X(GW9_ALWAYS_LOW0)
+X(GW9_ALWAYS_LOW1)
+X(GW9C_ALWAYS_LOW0)
+X(GW9C_ALWAYS_LOW1)
+X(OBUF_TYPE)
+X(IBUF_TYPE)
+X(SBUF)
+X(DBUF)
+X(ODDR)
+X(IDDR)
+X(ODDRC)
+X(IDDRC)
+X(ODDRA)
+X(ODDRB)
+X(ODDRCA)
+X(ODDRCB)
+X(OSER4)
+X(OSER8)
+X(OSER10)
+X(OVIDEO)
+X(OSER16)
+X(IDES4)
+X(IDES8)
+X(IDES10)
+X(IVIDEO)
+X(IDES16)
+X(IOLOGIC)
+X(IOLOGICA)
+X(IOLOGICB)
+X(IOLOGIC_TYPE)
+X(IOLOGIC_FCLK)
+X(IOLOGIC_MASTER_CELL)
+X(IOLOGIC_AUX_CELL)
+X(D8)
+X(D9)
+X(D10)
+X(D11)
+X(D12)
+X(D13)
+X(D14)
+X(D15)
+X(Q8)
+X(Q9)
+X(Q10)
+X(Q11)
+X(Q12)
+X(Q13)
+X(Q14)
+X(Q15)
+
+// Wide LUTs
+X(MUX2_LUT5)
+X(MUX2_LUT6)
+X(MUX2_LUT7)
+X(MUX2_LUT8)
+X(I0MUX0)
+X(I1MUX0)
+X(I0MUX1)
+X(I1MUX1)
+X(I0MUX2)
+X(I1MUX2)
+X(I0MUX3)
+X(I1MUX3)
+X(I0MUX4)
+X(I1MUX4)
+X(I0MUX5)
+X(I1MUX5)
+X(I0MUX6)
+X(I1MUX6)
+X(I0MUX7)
+X(I1MUX7)
+
+// ALU
+X(ALU)
+X(GND)
+X(ALU_MODE)
+
+// DFF types
+X(DFF)
+X(DFFE)
+X(DFFS)
+X(DFFSE)
+X(DFFR)
+X(DFFRE)
+X(DFFP)
+X(DFFPE)
+X(DFFC)
+X(DFFCE)
+X(DFFN)
+X(DFFNE)
+X(DFFNS)
+X(DFFNSE)
+X(DFFNR)
+X(DFFNRE)
+X(DFFNP)
+X(DFFNPE)
+X(DFFNC)
+X(DFFNCE)
+
+// Shadow RAM
+X(RAM16)
+X(RAMW)
+X(RAM16SDP4)
+X(WADA)
+X(WADB)
+X(WADC)
+X(WADD)
+X(DIA)
+X(DIB)
+X(DIC)
+X(DID)
+X(WRE)
+
+// IOB types
+X(IBUF)
+X(OBUF)
+X(IOBUF)
+X(TBUF)
+X(TLVDS_OBUF)
+X(TLVDS_TBUF)
+X(TLVDS_IBUF)
+X(TLVDS_IOBUF)
+X(ELVDS_OBUF)
+X(ELVDS_TBUF)
+X(ELVDS_IBUF)
+X(ELVDS_IOBUF)
+
+// global set/reset
+X(GSR)
+X(GSR0)
+X(GSRI)
+
+// Oscillators
+X(OSC)
+X(OSCZ)
+X(OSCH)
+X(OSCF)
+X(OSCW)
+X(OSCO)
+
+// PLLs
+X(rPLL)
+X(RPLLA)
+X(PLLVR)
+
+// primitive attributes
+X(INIT)
+X(FF_USED)
+X(FF_TYPE)
+X(INPUT_USED)
+X(OUTPUT_USED)
+X(ENABLE_USED)
+X(BEL)
+X(DIFF)
+X(DIFF_TYPE)
+X(DEVICE)
+X(IOLOGIC_IOB)
+
+// ports
+X(EN)
+X(E)
+X(Y)
+X(PAD)
+X(RESET)
+X(SET)
+X(PRESET)
+X(CLEAR)
+X(I0)
+X(I1)
+X(I2)
+X(I3)
+X(OEN)
+X(S0)
+X(SEL)
+X(SUM)
+X(CIN)
+X(COUT)
+X(OF)
+X(V)
+X(G)
+X(OSCOUT)
+X(OSCEN)
+X(RESET_P)
+X(CLKFB)
+X(FBDSEL0)
+X(FBDSEL1)
+X(FBDSEL2)
+X(FBDSEL3)
+X(FBDSEL4)
+X(FBDSEL5)
+X(IDSEL0)
+X(IDSEL1)
+X(IDSEL2)
+X(IDSEL3)
+X(IDSEL4)
+X(IDSEL5)
+X(ODSEL0)
+X(ODSEL1)
+X(ODSEL2)
+X(ODSEL3)
+X(ODSEL4)
+X(ODSEL5)
+X(PSDA0)
+X(PSDA1)
+X(PSDA2)
+X(PSDA3)
+X(DUTYDA0)
+X(DUTYDA1)
+X(DUTYDA2)
+X(DUTYDA3)
+X(FDLY0)
+X(FDLY1)
+X(FDLY2)
+X(FDLY3)
+X(CLKIN)
+X(CLKOUT)
+X(CLKOUTP)
+X(CLKOUTD)
+X(CLKOUTD3)
+X(LOCK)
+
+// PLL parameters
+X(CLKOUTPS)
+X(CLKOUTDIV)
+X(CLKOUTDIV3)
+X(PWDEN)
+X(RSTEN)
+X(FLOCK)
+X(INSEL)
+X(FBSEL)
+X(CLKFB_SEL)
+
+// timing
+X(X0)
+X(FX1)
+X(X2)
+X(X8)
+X(PIO_CENT_PCLK)
+X(CENT_SPINE_PCLK)
+X(SPINE_TAP_PCLK)
+X(TAP_BRANCH_PCLK)
+X(BRANCH_PCLK)
+X(CENT_SPINE_SCLK)
+X(SPINE_TAP_SCLK_0)
+X(SPINE_TAP_SCLK_1)
+X(TAP_BRANCH_SCLK)
+X(BRANCH_SCLK)
+X(clksetpos)
+X(clkholdpos)
+X(clk_qpos)
+X(a_f)
+X(b_f)
+X(c_f)
+X(d_f)
+X(fx_ofx1)
+X(I01)
+
+// GUI
+X(DECAL_LUT_ACTIVE)
+X(DECAL_LUT_INACTIVE)
+X(DECAL_LUTDFF_ACTIVE)
+X(DECAL_LUTDFF_INACTIVE)
+X(DECAL_LUT_UNUSED_DFF_ACTIVE)
+X(DECAL_GRP_LUT)
+X(DECAL_CRU)
+X(DECAL_MUXUPPER_INACTIVE)
+X(DECAL_MUXUPPER_ACTIVE)
+X(DECAL_MUXLOWER_INACTIVE)
+X(DECAL_MUXLOWER_ACTIVE)
+X(DECAL_IOB_INACTIVE)
+X(DECAL_IOB_ACTIVE)
+X(DECAL_IOBS_INACTIVE)
+X(DECAL_IOBS_ACTIVE)
+X(DECAL_ALU_ACTIVE)
+
+
+
+
+X(SINGLE_INPUT_MUX)
+X(cst)
+X(none)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
new file mode 100644
index 0000000000..5807248a64
--- /dev/null
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -0,0 +1,115 @@
+from os import path
+import sys
+
+import importlib.resources
+import pickle
+import gzip
+import argparse
+
+sys.path.append(path.join(path.dirname(__file__), "../.."))
+from himbaechel_dbgen.chip import *
+from apycula import chipdb
+
+def create_nodes(chip: Chip, db: chipdb):
+    return
+
+# About X and Y as parameters - in some cases, the type of manufacturer's tile
+# is not different, but some wires are not physically present, that is, routing
+# depends on the location of otherwise identical tiles. There are many options
+# for taking this into account, but for now we make a distinction here, by
+# coordinates.
+def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
+    pips = db.grid[y][x].pips
+    for dst, srcs in pips.items():
+        if not tt.has_wire(dst):
+            tt.create_wire(dst)
+        for src in srcs.keys():
+            if not tt.has_wire(src):
+                tt.create_wire(src)
+            tt.create_pip(dst, src)
+
+def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int):
+    tt = chip.create_tile_type(f"NULL{db.grid[y][x].ttyp}")
+
+# XXX 6 lut+dff only for now
+def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
+    N = 6
+    lut_inputs = {'A', 'B', 'C', 'D'}
+    tt = chip.create_tile_type(f"LOGIC{db.grid[y][x].ttyp}")
+    # setup wires
+    for i in range(N):
+        for inp_name in lut_inputs:
+            tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
+        tt.create_wire(f"F{i}", "LUT_OUT")
+        # experimental. the wire is false - it is assumed that DFF is always
+        # connected to the LUT's output F{i}, but we can place primitives
+        # arbitrarily and create a pass-through LUT afterwards.
+        # just out of curiosity
+        tt.create_wire(f"XD{i}", "FF_INPUT")
+        tt.create_wire(f"Q{i}", "FF_OUT")
+    for j in range(3):
+        tt.create_wire(f"CLK{j}", "TILE_CLK")
+
+    # create logic cells
+    for i in range(N):
+        # LUT
+        lut = tt.create_bel(f"LUT{i}", "LUT4", z=(i*2 + 0))
+        for j, inp_name in enumerate(lut_inputs):
+            tt.add_bel_pin(lut, f"I[{j}]", f"{inp_name}{i}", PinType.INPUT)
+        tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
+        # FF data can come from LUT output, but we pretend that we can use
+        # any LUT input
+        tt.create_pip(f"F{i}", f"XD{i}")
+        for inp_name in lut_inputs:
+            tt.create_pip(f"{inp_name}{i}", f"XD{i}")
+        # FF
+        ff = tt.create_bel(f"DFF{i}", "DFF", z=(i*2 + 1))
+        tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
+        tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
+        tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
+    create_switch_matrix(tt, db, x, y)
+
+def main():
+    parser = argparse.ArgumentParser(description='Make Gowin BBA')
+    parser.add_argument('-d', '--device', required=True)
+    parser.add_argument('-o', '--output', default="out.bba")
+
+    args = parser.parse_args()
+
+    device = args.device
+    with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
+        db = pickle.load(f)
+
+    X = db.cols;
+    Y = db.rows;
+
+    ch = Chip("gowin", device, X, Y)
+
+    # Init constant ids
+    ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
+
+    # The manufacturer distinguishes by externally identical tiles, so keep
+    # these differences (in case it turns out later that there is a slightly
+    # different routing or something like that).
+    created_tiletypes = set()
+    logic_tiletypes = {12, 13, 14, 15, 16, 17}
+    # Setup tile grid
+    for x in range(X):
+        for y in range(Y):
+            ttyp = db.grid[y][x].ttyp
+            if ttyp in logic_tiletypes:
+                if ttyp not in created_tiletypes:
+                    create_logic_tiletype(ch, db, x, y)
+                    created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"LOGIC{ttyp}")
+            else:
+                if ttyp not in created_tiletypes:
+                    create_null_tiletype(ch, db, x, y)
+                    created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"NULL{ttyp}")
+
+    # Create nodes between tiles
+    create_nodes(ch, db)
+    ch.write_bba(args.output)
+if __name__ == '__main__':
+    main()

From 24e1734999b291b63d79787a006684a06232f386 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 28 Jun 2023 16:32:53 +1000
Subject: [PATCH 430/712] generate bba

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 88 ++++++++++++++++++++++--
 1 file changed, 83 insertions(+), 5 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 5807248a64..716a6b6e11 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -4,14 +4,70 @@
 import importlib.resources
 import pickle
 import gzip
+import re
 import argparse
 
 sys.path.append(path.join(path.dirname(__file__), "../.."))
 from himbaechel_dbgen.chip import *
 from apycula import chipdb
 
+# XXX u-turn at the rim
+uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
+def uturn(db: chipdb, x: int, y: int, wire: str):
+    m = re.match(r"([NESW])([128]\d)(\d)", wire)
+    if m:
+        direction, num, segment = m.groups()
+        # wires wrap around the edges
+        # assumes 0-based indexes
+        if y < 0:
+            y = -1 - y
+            direction = uturnlut[direction]
+        if x < 0:
+            x = -1 - x
+            direction = uturnlut[direction]
+        if y > db.rows - 1:
+            y = 2 * db.rows - 1 - y
+            direction = uturnlut[direction]
+        if x > db.cols - 1:
+            x = 2 * db.cols - 1 - x
+            direction = uturnlut[direction]
+        wire = f'{direction}{num}{segment}'
+    return (x, y, wire)
+
 def create_nodes(chip: Chip, db: chipdb):
-    return
+    # : (x, y)
+    dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
+    X = db.cols
+    Y = db.rows
+    for y in range(Y):
+        for x in range(X):
+            nodes = []
+            # SN and EW
+            for i in [1, 2]:
+                nodes.append([NodeWire(x, y, f'SN{i}0'),
+                        NodeWire(*uturn(db, x, y - 1, f'N1{i}1')),
+                        NodeWire(*uturn(db, x, y + 1, f'S1{i}1'))])
+                nodes.append([NodeWire(x, y, f'EW{i}0'),
+                        NodeWire(*uturn(db, x - 1, y, f'W1{i}1')),
+                        NodeWire(*uturn(db, x + 1, y, f'E1{i}1'))])
+            for d, offs in dirs.items():
+                # 1-hop
+                for i in [0, 3]:
+                    nodes.append([NodeWire(x, y, f'{d}1{i}0'),
+                        NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}1{i}1'))])
+                # 2-hop
+                for i in range(8):
+                    nodes.append([NodeWire(x, y, f'{d}2{i}0'),
+                        NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}2{i}1')),
+                        NodeWire(*uturn(db, x + offs[0] * 2, y + offs[1] * 2, f'{d}2{i}2'))])
+                # 4-hop
+                for i in range(4):
+                    nodes.append([NodeWire(x, y, f'{d}8{i}0'),
+                        NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
+                        NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
+            for node in nodes:
+                print(node)
+                chip.add_node(node)
 
 # About X and Y as parameters - in some cases, the type of manufacturer's tile
 # is not different, but some wires are not physically present, that is, routing
@@ -29,13 +85,29 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
             tt.create_pip(dst, src)
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int):
-    tt = chip.create_tile_type(f"NULL{db.grid[y][x].ttyp}")
+    tt = chip.create_tile_type(f"NULL_{db.grid[y][x].ttyp}")
+    create_switch_matrix(tt, db, x, y)
+
+# simple IO - only A and B
+def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int):
+    tt = chip.create_tile_type(f"IO_{db.grid[y][x].ttyp}")
+    for i in range(2):
+        name = ['IOBA', 'IOBB'][i]
+        # wires
+        portmap = db.grid[y][x].bels[name].portmap
+        tt.create_wire(portmap['I'], "IO_I")
+        tt.create_wire(portmap['O'], "IO_I")
+        # bels
+        io = tt.create_bel(name, "IOB", z=i)
+        tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
+        tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
+    create_switch_matrix(tt, db, x, y)
 
 # XXX 6 lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
     N = 6
     lut_inputs = {'A', 'B', 'C', 'D'}
-    tt = chip.create_tile_type(f"LOGIC{db.grid[y][x].ttyp}")
+    tt = chip.create_tile_type(f"LOGIC_{db.grid[y][x].ttyp}")
     # setup wires
     for i in range(N):
         for inp_name in lut_inputs:
@@ -93,6 +165,7 @@ def main():
     # different routing or something like that).
     created_tiletypes = set()
     logic_tiletypes = {12, 13, 14, 15, 16, 17}
+    io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;)
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
@@ -101,12 +174,17 @@ def main():
                 if ttyp not in created_tiletypes:
                     create_logic_tiletype(ch, db, x, y)
                     created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"LOGIC{ttyp}")
+                ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
+            elif ttyp in io_tiletypes:
+                if ttyp not in created_tiletypes:
+                    create_io_tiletype(ch, db, x, y)
+                    created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"IO_{ttyp}")
             else:
                 if ttyp not in created_tiletypes:
                     create_null_tiletype(ch, db, x, y)
                     created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"NULL{ttyp}")
+                ch.set_tile_type(x, y, f"NULL_{ttyp}")
 
     # Create nodes between tiles
     create_nodes(ch, db)

From fb5f764b8596dc3bf974cb8d83b7b008c5b34a95 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 29 Jun 2023 06:50:16 +1000
Subject: [PATCH 431/712] gowin: Add himbaechel arch

- wires, nodes and whites are generated from bases - apicula;
- roting of SN and EW bidirectional wires is supported;
- supports "wrapping" the wires at the edges of the chip;
- LUT1-4 and two types of DFF(R) are supported;
- simple IO is supported.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   1 +
 himbaechel/uarch/gowin/gowin.cc          | 144 +++++++++++++++++++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py |   9 +-
 3 files changed, 150 insertions(+), 4 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/gowin.cc

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 230abc09cd..d92642fe80 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1056,3 +1056,4 @@ X(place)
 X(placer)
 X(route)
 X(router)
+
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
new file mode 100644
index 0000000000..9a389ae5ee
--- /dev/null
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -0,0 +1,144 @@
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "himbaechel_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct GowinImpl : HimbaechelAPI
+{
+
+    ~GowinImpl(){};
+    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init(Context *ctx) override
+    {
+        h.init(ctx);
+        HimbaechelAPI::init(ctx);
+    }
+
+    void prePlace() override {
+		ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X46Y14/IOBA"));
+		ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
+		ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
+		ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
+		ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
+		ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
+		ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
+		assign_cell_info();
+	}
+
+    void pack() override
+    {
+        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_IBUF, id_I),
+                CellTypePort(id_OBUF, id_O),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+        // Replace constants with LUTs
+        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
+        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
+        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+        // Constrain directly connected LUTs and FFs together to use dedicated resources
+        int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+        log_info("Constrained %d LUTFF pairs.\n", lutffs);
+    }
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
+    {
+        Loc l = ctx->getBelLocation(bel);
+        if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
+            return slice_valid(l.x, l.y, l.z / 2);
+        } else {
+            return true;
+        }
+    }
+
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override
+    {
+        if (cell_type.in(id_IBUF, id_OBUF)) {
+            return id_IOB;
+		}
+		if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+			return id_LUT4;
+		}
+        return cell_type;
+    }
+
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+    {
+        IdString bel_type = ctx->getBelType(bel);
+        if (bel_type == id_IOB) {
+            return cell_type.in(id_IBUF, id_OBUF);
+		}
+		if (bel_type == id_LUT4) {
+			return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+		}
+		if (bel_type == id_DFF) {
+			return cell_type.in(id_DFF, id_DFFR);
+		}
+        return (bel_type == cell_type);
+    }
+
+  private:
+    HimbaechelHelpers h;
+
+    // Validity checking
+    struct GowinCellInfo
+    {
+        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+    };
+    std::vector<GowinCellInfo> fast_cell_info;
+    void assign_cell_info()
+    {
+        fast_cell_info.resize(ctx->cells.size());
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto &fc = fast_cell_info.at(ci->flat_index);
+            if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+                fc.lut_f = ci->getPort(id_F);
+            } else if (ci->type.in(id_DFF, id_DFFR)) {
+                fc.ff_d = ci->getPort(id_D);
+            }
+        }
+    }
+    bool slice_valid(int x, int y, int z) const
+    {
+        const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+        const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+        if (!lut || !ff)
+            return true; // always valid if only LUT or FF used
+        const auto &lut_data = fast_cell_info.at(lut->flat_index);
+        const auto &ff_data = fast_cell_info.at(ff->flat_index);
+        if (ff_data.ff_d == lut_data.lut_f)
+            return true;
+        return false;
+    }
+};
+
+struct GowinArch : HimbaechelArch
+{
+    GowinArch() : HimbaechelArch("gowin"){};
+    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<GowinImpl>();
+    }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 716a6b6e11..50764b5b72 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -66,7 +66,6 @@ def create_nodes(chip: Chip, db: chipdb):
                         NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
                         NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
             for node in nodes:
-                print(node)
                 chip.add_node(node)
 
 # About X and Y as parameters - in some cases, the type of manufacturer's tile
@@ -82,7 +81,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
         for src in srcs.keys():
             if not tt.has_wire(src):
                 tt.create_wire(src)
-            tt.create_pip(dst, src)
+            tt.create_pip(src, dst)
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int):
     tt = chip.create_tile_type(f"NULL_{db.grid[y][x].ttyp}")
@@ -106,7 +105,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int):
 # XXX 6 lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
     N = 6
-    lut_inputs = {'A', 'B', 'C', 'D'}
+    lut_inputs = ['A', 'B', 'C', 'D']
     tt = chip.create_tile_type(f"LOGIC_{db.grid[y][x].ttyp}")
     # setup wires
     for i in range(N):
@@ -121,13 +120,14 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
         tt.create_wire(f"Q{i}", "FF_OUT")
     for j in range(3):
         tt.create_wire(f"CLK{j}", "TILE_CLK")
+        tt.create_wire(f"LSR{j}", "TILE_LSR")
 
     # create logic cells
     for i in range(N):
         # LUT
         lut = tt.create_bel(f"LUT{i}", "LUT4", z=(i*2 + 0))
         for j, inp_name in enumerate(lut_inputs):
-            tt.add_bel_pin(lut, f"I[{j}]", f"{inp_name}{i}", PinType.INPUT)
+            tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
         tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
         # FF data can come from LUT output, but we pretend that we can use
         # any LUT input
@@ -139,6 +139,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
         tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
         tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
         tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
+        tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
     create_switch_matrix(tt, db, x, y)
 
 def main():

From ae89430075138eaa537864f3b5a836bf4799fcd9 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 30 Jun 2023 17:18:14 +1000
Subject: [PATCH 432/712] gowin: add global VCC and VSS networks

- VSS and VCC sources in each cell are used;
- constant LUT inputs are disabled;
- putting the class declaration into a header file.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   7 +-
 himbaechel/uarch/gowin/gowin.cc          | 316 ++++++++++++++---------
 himbaechel/uarch/gowin/gowin.h           |  63 +++++
 himbaechel/uarch/gowin/gowin_arch_gen.py |  83 ++++--
 4 files changed, 317 insertions(+), 152 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/gowin.h

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index d92642fe80..1b47db91ae 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1045,9 +1045,6 @@ X(DECAL_IOBS_INACTIVE)
 X(DECAL_IOBS_ACTIVE)
 X(DECAL_ALU_ACTIVE)
 
-
-
-
 X(SINGLE_INPUT_MUX)
 X(cst)
 X(none)
@@ -1057,3 +1054,7 @@ X(placer)
 X(route)
 X(router)
 
+// misc
+X(GOWIN_GND)
+X(GOWIN_VCC)
+
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 9a389ae5ee..800a8c5f92 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -3,142 +3,200 @@
 #include "nextpnr.h"
 #include "util.h"
 
-#include "himbaechel_helpers.h"
-
-#define GEN_INIT_CONSTIDS
-#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
-#include "himbaechel_constids.h"
+#include "gowin.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-namespace {
-struct GowinImpl : HimbaechelAPI
-{
-
-    ~GowinImpl(){};
-    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
-    void init(Context *ctx) override
-    {
-        h.init(ctx);
-        HimbaechelAPI::init(ctx);
-    }
-
-    void prePlace() override {
-		ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X46Y14/IOBA"));
-		ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
-		ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
-		ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
-		ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
-		ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
-		ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
-		assign_cell_info();
+void GowinImpl::init(Context *ctx) {
+	h.init(ctx);
+	HimbaechelAPI::init(ctx);
+	// These fields go in the header of the output JSON file and can help
+	// gowin_pack support different architectures
+	ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
+	// XXX it would be nice to write chip/base name in the header as well,
+	// but maybe that will come up when there is clarity with
+	// Arch::archArgsToId
+}
+
+void GowinImpl::prePlace() {
+	ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
+	ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
+	ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
+	ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
+	ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
+	ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
+	ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
+	assign_cell_info();
+}
+
+void GowinImpl::pack() {
+	// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+	const pool<CellTypePort> top_ports{
+			CellTypePort(id_IBUF, id_I),
+			CellTypePort(id_OBUF, id_O),
+	};
+	h.remove_nextpnr_iobs(top_ports);
+	// Replace constants with LUTs
+	const dict<IdString, Property> vcc_params;
+	const dict<IdString, Property> gnd_params;
+	h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
+
+	// disconnect the constant LUT inputs
+	mod_lut_inputs();
+
+	// Constrain directly connected LUTs and FFs together to use dedicated resources
+	int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+	log_info("Constrained %d LUTFF pairs.\n", lutffs);
+}
+
+bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const {
+	Loc l = ctx->getBelLocation(bel);
+	if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
+		return slice_valid(l.x, l.y, l.z / 2);
+	} else {
+		return true;
 	}
+}
 
-    void pack() override
-    {
-        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
-        const pool<CellTypePort> top_ports{
-                CellTypePort(id_IBUF, id_I),
-                CellTypePort(id_OBUF, id_O),
-        };
-        h.remove_nextpnr_iobs(top_ports);
-        // Replace constants with LUTs
-        const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
-        const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
-        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
-        // Constrain directly connected LUTs and FFs together to use dedicated resources
-        int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-        lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-        log_info("Constrained %d LUTFF pairs.\n", lutffs);
-    }
-
-    bool isBelLocationValid(BelId bel, bool explain_invalid) const override
-    {
-        Loc l = ctx->getBelLocation(bel);
-        if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
-            return slice_valid(l.x, l.y, l.z / 2);
-        } else {
-            return true;
-        }
-    }
-
-    // Bel bucket functions
-    IdString getBelBucketForCellType(IdString cell_type) const override
-    {
-        if (cell_type.in(id_IBUF, id_OBUF)) {
-            return id_IOB;
-		}
-		if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
-			return id_LUT4;
-		}
-        return cell_type;
-    }
-
-    bool isValidBelForCellType(IdString cell_type, BelId bel) const override
-    {
-        IdString bel_type = ctx->getBelType(bel);
-        if (bel_type == id_IOB) {
-            return cell_type.in(id_IBUF, id_OBUF);
+// Bel bucket functions
+IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const {
+	if (cell_type.in(id_IBUF, id_OBUF)) {
+		return id_IOB;
+	}
+	if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+		return id_LUT4;
+	}
+	if (cell_type == id_GOWIN_GND) {
+		return id_GND;
+	}
+	if (cell_type == id_GOWIN_VCC) {
+		return id_VCC;
+	}
+	return cell_type;
+}
+
+bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const {
+	IdString bel_type = ctx->getBelType(bel);
+	if (bel_type == id_IOB) {
+		return cell_type.in(id_IBUF, id_OBUF);
+	}
+	if (bel_type == id_LUT4) {
+		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+	}
+	if (bel_type == id_DFF) {
+		return cell_type.in(id_DFF, id_DFFR);
+	}
+	if (bel_type == id_GND) {
+		return cell_type == id_GOWIN_GND;
+	}
+	if (bel_type == id_VCC) {
+		return cell_type == id_GOWIN_VCC;
+	}
+	return (bel_type == cell_type);
+}
+
+void GowinImpl::assign_cell_info() {
+	fast_cell_info.resize(ctx->cells.size());
+	for (auto &cell : ctx->cells) {
+		CellInfo *ci = cell.second.get();
+		auto &fc = fast_cell_info.at(ci->flat_index);
+		if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+			fc.lut_f = ci->getPort(id_F);
+		} else if (ci->type.in(id_DFF, id_DFFR)) {
+			fc.ff_d = ci->getPort(id_D);
 		}
-		if (bel_type == id_LUT4) {
-			return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+	}
+}
+
+bool GowinImpl::slice_valid(int x, int y, int z) const {
+	const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+	const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+	if (!lut || !ff)
+		return true; // always valid if only LUT or FF used
+	const auto &lut_data = fast_cell_info.at(lut->flat_index);
+	const auto &ff_data = fast_cell_info.at(ff->flat_index);
+	if (ff_data.ff_d == lut_data.lut_f)
+		return true;
+	return false;
+}
+
+// modify LUTs with constant inputs
+void GowinImpl::mod_lut_inputs(void) {
+	for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
+		auto net = ctx->nets.find(netname);
+		if (net == ctx->nets.end()) {
+			continue;
 		}
-		if (bel_type == id_DFF) {
-			return cell_type.in(id_DFF, id_DFFR);
+		NetInfo *constnet = net->second.get();
+		for (auto user : constnet->users) {
+			CellInfo *uc = user.cell;
+			if (ctx->verbose)
+				log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
+
+			if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I')) {
+				auto it_param = uc->params.find(id_INIT);
+				if (it_param == uc->params.end())
+					log_error("No initialization for lut found.\n");
+
+				int64_t uc_init = it_param->second.intval;
+				int64_t mask = 0;
+				uint8_t amt = 0;
+
+				if (user.port == id_I0) {
+					mask = 0x5555;
+					amt = 1;
+				} else if (user.port == id_I1) {
+					mask = 0x3333;
+					amt = 2;
+				} else if (user.port == id_I2) {
+					mask = 0x0F0F;
+					amt = 4;
+				} else if (user.port == id_I3) {
+					mask = 0x00FF;
+					amt = 8;
+				} else {
+					log_error("Port number invalid.\n");
+				}
+
+				if ((constnet->name == ctx->id("$PACKER_GND"))) {
+					uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
+				} else {
+					uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
+				}
+
+				size_t uc_init_len = it_param->second.to_string().length();
+				uc_init &= (1LL << uc_init_len) - 1;
+
+				if (ctx->verbose)
+					log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
+							 uc_init);
+
+				it_param->second = Property(uc_init, uc_init_len);
+				uc->disconnectPort(user.port);
+			}
 		}
-        return (bel_type == cell_type);
-    }
-
-  private:
-    HimbaechelHelpers h;
-
-    // Validity checking
-    struct GowinCellInfo
-    {
-        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
-    };
-    std::vector<GowinCellInfo> fast_cell_info;
-    void assign_cell_info()
-    {
-        fast_cell_info.resize(ctx->cells.size());
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            auto &fc = fast_cell_info.at(ci->flat_index);
-            if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
-                fc.lut_f = ci->getPort(id_F);
-            } else if (ci->type.in(id_DFF, id_DFFR)) {
-                fc.ff_d = ci->getPort(id_D);
-            }
-        }
-    }
-    bool slice_valid(int x, int y, int z) const
-    {
-        const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
-        const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-        if (!lut || !ff)
-            return true; // always valid if only LUT or FF used
-        const auto &lut_data = fast_cell_info.at(lut->flat_index);
-        const auto &ff_data = fast_cell_info.at(ff->flat_index);
-        if (ff_data.ff_d == lut_data.lut_f)
-            return true;
-        return false;
-    }
-};
-
-struct GowinArch : HimbaechelArch
-{
-    GowinArch() : HimbaechelArch("gowin"){};
-    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
-    {
-        return std::make_unique<GowinImpl>();
-    }
-} exampleArch;
-} // namespace
+	}
+}
+
+// Return true if a cell is a LUT
+bool GowinImpl::is_lut(const BaseCtx *ctx, const CellInfo *cell) const {
+	switch (cell->type.index) {
+	case ID_LUT1:
+	case ID_LUT2:
+	case ID_LUT3:
+	case ID_LUT4:
+		return true;
+	default:
+		return false;
+	}
+}
+
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
new file mode 100644
index 0000000000..76a513de16
--- /dev/null
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -0,0 +1,63 @@
+#ifndef GOWIN_H
+#define GOWIN_H
+
+#include "himbaechel_api.h"
+#include "himbaechel_helpers.h"
+#include "nextpnr.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct GowinImpl : HimbaechelAPI
+{
+
+    ~GowinImpl(){};
+    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init(Context *ctx) override;
+
+    void prePlace() override;
+	void pack() override;
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
+
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override;
+
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
+
+  private:
+    HimbaechelHelpers h;
+
+    // Validity checking
+    struct GowinCellInfo
+    {
+        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+    };
+    std::vector<GowinCellInfo> fast_cell_info;
+    void assign_cell_info();
+    bool slice_valid(int x, int y, int z) const;
+
+	// modify LUTs with constant inputs
+	void mod_lut_inputs(void);
+
+	// Return true if a cell is a LUT
+	bool is_lut(const BaseCtx *ctx, const CellInfo *cell) const;
+};
+
+struct GowinArch : HimbaechelArch
+{
+    GowinArch() : HimbaechelArch("gowin"){};
+    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<GowinImpl>();
+    }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
+#endif
+
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 50764b5b72..e6ddd433e7 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -11,7 +11,13 @@
 from himbaechel_dbgen.chip import *
 from apycula import chipdb
 
-# XXX u-turn at the rim
+# Z of the bels
+VCC_Z = 277
+GND_Z = 288
+
+created_tiletypes = set()
+
+# u-turn at the rim
 uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
 def uturn(db: chipdb, x: int, y: int, wire: str):
     m = re.match(r"([NESW])([128]\d)(\d)", wire)
@@ -39,6 +45,7 @@ def create_nodes(chip: Chip, db: chipdb):
     dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
     X = db.cols
     Y = db.rows
+    global_nodes = {}
     for y in range(Y):
         for x in range(X):
             nodes = []
@@ -67,6 +74,12 @@ def create_nodes(chip: Chip, db: chipdb):
                         NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
             for node in nodes:
                 chip.add_node(node)
+            # VCC and VSS sources in the all tiles
+            global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
+            global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
+
+    for node in global_nodes.values():
+        chip.add_node(node)
 
 # About X and Y as parameters - in some cases, the type of manufacturer's tile
 # is not different, but some wires are not physically present, that is, routing
@@ -83,13 +96,37 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
                 tt.create_wire(src)
             tt.create_pip(src, dst)
 
-def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int):
-    tt = chip.create_tile_type(f"NULL_{db.grid[y][x].ttyp}")
+def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp
+    tt = chip.create_tile_type(f"NULL_{ttyp}")
+    create_switch_matrix(tt, db, x, y)
+    return ttyp
+
+# responsible nodes, there will be IO banks, configuration, etc.
+def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp
+    tt = chip.create_tile_type(f"CORNER_{ttyp}")
+
+    if x == 0 and y == 0:
+        # GND is the logic low level generator
+        tt.create_wire('VSS', 'GND')
+        gnd = tt.create_bel('GND', 'GND', z = GND_Z)
+        tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
+        # VCC is the logic high level generator
+        tt.create_wire('VCC', 'VCC')
+        gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
+        tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
+
     create_switch_matrix(tt, db, x, y)
+    return ttyp
 
 # simple IO - only A and B
-def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int):
-    tt = chip.create_tile_type(f"IO_{db.grid[y][x].ttyp}")
+def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp
+    tt = chip.create_tile_type(f"IO_{ttyp}")
     for i in range(2):
         name = ['IOBA', 'IOBB'][i]
         # wires
@@ -97,16 +134,19 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int):
         tt.create_wire(portmap['I'], "IO_I")
         tt.create_wire(portmap['O'], "IO_I")
         # bels
-        io = tt.create_bel(name, "IOB", z=i)
+        io = tt.create_bel(name, "IOB", z = i)
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
         tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
     create_switch_matrix(tt, db, x, y)
+    return ttyp
 
 # XXX 6 lut+dff only for now
-def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
+def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     N = 6
     lut_inputs = ['A', 'B', 'C', 'D']
-    tt = chip.create_tile_type(f"LOGIC_{db.grid[y][x].ttyp}")
+    if ttyp in created_tiletypes:
+        return ttyp
+    tt = chip.create_tile_type(f"LOGIC_{ttyp}")
     # setup wires
     for i in range(N):
         for inp_name in lut_inputs:
@@ -125,7 +165,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
     # create logic cells
     for i in range(N):
         # LUT
-        lut = tt.create_bel(f"LUT{i}", "LUT4", z=(i*2 + 0))
+        lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
         for j, inp_name in enumerate(lut_inputs):
             tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
         tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
@@ -135,12 +175,13 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int):
         for inp_name in lut_inputs:
             tt.create_pip(f"{inp_name}{i}", f"XD{i}")
         # FF
-        ff = tt.create_bel(f"DFF{i}", "DFF", z=(i*2 + 1))
+        ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
         tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
         tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
         tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
         tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
     create_switch_matrix(tt, db, x, y)
+    return ttyp
 
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
@@ -164,27 +205,29 @@ def main():
     # The manufacturer distinguishes by externally identical tiles, so keep
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
-    created_tiletypes = set()
     logic_tiletypes = {12, 13, 14, 15, 16, 17}
     io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;)
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
             ttyp = db.grid[y][x].ttyp
+            if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
+                assert ttyp not in created_tiletypes, "Duplication of corner types"
+                ttyp = create_corner_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"CORNER_{ttyp}")
+                continue
             if ttyp in logic_tiletypes:
-                if ttyp not in created_tiletypes:
-                    create_logic_tiletype(ch, db, x, y)
-                    created_tiletypes.add(ttyp)
+                ttyp = create_logic_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
             elif ttyp in io_tiletypes:
-                if ttyp not in created_tiletypes:
-                    create_io_tiletype(ch, db, x, y)
-                    created_tiletypes.add(ttyp)
+                ttyp = create_io_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"IO_{ttyp}")
             else:
-                if ttyp not in created_tiletypes:
-                    create_null_tiletype(ch, db, x, y)
-                    created_tiletypes.add(ttyp)
+                ttyp = create_null_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"NULL_{ttyp}")
 
     # Create nodes between tiles

From e4d2e1bd855d3e83c54916d2b241854f020eea17 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 30 Jun 2023 22:44:19 +1000
Subject: [PATCH 433/712] gowin: add support for all DFF types

Himbaechel-gowin has learned how to place DFFs of all types by tracking
the compatibility of CLK, CE and LSR inputs, as well as placing mutually
compatible flip-flops in adjacent slices.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc          | 94 ++++++++++++++++--------
 himbaechel/uarch/gowin/gowin.h           | 21 +++++-
 himbaechel/uarch/gowin/gowin_arch_gen.py | 32 ++++----
 3 files changed, 102 insertions(+), 45 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 800a8c5f92..b030b62008 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -45,14 +45,13 @@ void GowinImpl::pack() {
 	mod_lut_inputs();
 
 	// Constrain directly connected LUTs and FFs together to use dedicated resources
-	int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+	int lutffs = h.constrain_cell_pairs(
+			pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
+			pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
+			  {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
+			  {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
+			  {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
+			  {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},1);
 	log_info("Constrained %d LUTFF pairs.\n", lutffs);
 }
 
@@ -70,9 +69,12 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const {
 	if (cell_type.in(id_IBUF, id_OBUF)) {
 		return id_IOB;
 	}
-	if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+	if (type_is_lut(cell_type)) {
 		return id_LUT4;
 	}
+	if (type_is_dff(cell_type)) {
+		return id_DFF;
+	}
 	if (cell_type == id_GOWIN_GND) {
 		return id_GND;
 	}
@@ -88,10 +90,10 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const {
 		return cell_type.in(id_IBUF, id_OBUF);
 	}
 	if (bel_type == id_LUT4) {
-		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+		return type_is_lut(cell_type);
 	}
 	if (bel_type == id_DFF) {
-		return cell_type.in(id_DFF, id_DFFR);
+		return type_is_dff(cell_type);
 	}
 	if (bel_type == id_GND) {
 		return cell_type == id_GOWIN_GND;
@@ -107,10 +109,18 @@ void GowinImpl::assign_cell_info() {
 	for (auto &cell : ctx->cells) {
 		CellInfo *ci = cell.second.get();
 		auto &fc = fast_cell_info.at(ci->flat_index);
-		if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+		if (is_lut(ci)) {
 			fc.lut_f = ci->getPort(id_F);
-		} else if (ci->type.in(id_DFF, id_DFFR)) {
+		} else if (is_dff(ci)) {
 			fc.ff_d = ci->getPort(id_D);
+			fc.ff_clk = ci->getPort(id_CLK);
+			fc.ff_ce = ci->getPort(id_CE);
+			for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+				fc.ff_lsr = ci->getPort(port);
+				if (fc.ff_lsr != nullptr) {
+					break;
+				}
+			}
 		}
 	}
 }
@@ -118,12 +128,48 @@ void GowinImpl::assign_cell_info() {
 bool GowinImpl::slice_valid(int x, int y, int z) const {
 	const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
 	const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-	if (!lut || !ff)
-		return true; // always valid if only LUT or FF used
-	const auto &lut_data = fast_cell_info.at(lut->flat_index);
+	if (!ff) {
+		return true; // always valid if only LUT used
+	}
 	const auto &ff_data = fast_cell_info.at(ff->flat_index);
-	if (ff_data.ff_d == lut_data.lut_f)
+	if (lut) {
+		const auto &lut_data = fast_cell_info.at(lut->flat_index);
+		if (ff_data.ff_d != lut_data.lut_f)
+			return false;
+	}
+	int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
+	const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
+	if (adj_ff == nullptr) {
 		return true;
+	}
+	// DFFs must be same type or compatible
+	if (ff->type != adj_ff->type &&
+			(   (ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR))
+			 || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS))
+			 || (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE))
+			 || (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE))
+			 || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC))
+			 || (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP))
+			 || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE))
+			 || (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE))
+			 || (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR))
+			 || (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS))
+			 || (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE))
+			 || (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE))
+			 || (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC))
+			 || (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP))
+			 || (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE))
+			 || (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE))
+			 )) {
+		return false;
+	}
+
+	// CE, LSR and CLK must match
+	const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
+	if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
+		return true;
+	}
+	//
 	return false;
 }
 
@@ -140,7 +186,7 @@ void GowinImpl::mod_lut_inputs(void) {
 			if (ctx->verbose)
 				log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
 
-			if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I')) {
+			if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
 				auto it_param = uc->params.find(id_INIT);
 				if (it_param == uc->params.end())
 					log_error("No initialization for lut found.\n");
@@ -185,18 +231,6 @@ void GowinImpl::mod_lut_inputs(void) {
 	}
 }
 
-// Return true if a cell is a LUT
-bool GowinImpl::is_lut(const BaseCtx *ctx, const CellInfo *cell) const {
-	switch (cell->type.index) {
-	case ID_LUT1:
-	case ID_LUT2:
-	case ID_LUT3:
-	case ID_LUT4:
-		return true;
-	default:
-		return false;
-	}
-}
 
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 76a513de16..d44a00d47c 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -35,7 +35,8 @@ struct GowinImpl : HimbaechelAPI
     // Validity checking
     struct GowinCellInfo
     {
-        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+        const NetInfo *lut_f = nullptr;
+		const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
     };
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
@@ -45,7 +46,23 @@ struct GowinImpl : HimbaechelAPI
 	void mod_lut_inputs(void);
 
 	// Return true if a cell is a LUT
-	bool is_lut(const BaseCtx *ctx, const CellInfo *cell) const;
+	inline bool type_is_lut(IdString cell_type) const {
+		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+	}
+	inline bool is_lut(const CellInfo *cell) const {
+		return type_is_lut(cell->type);
+	}
+	// Return true if a cell is a DFF
+	inline bool type_is_dff(IdString cell_type) const {
+		return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE,
+				     id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE,
+					 id_DFFR, id_DFFRE, id_DFFNR, id_DFFNRE,
+					 id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE,
+					 id_DFFC, id_DFFCE, id_DFFNC, id_DFFNCE);
+	}
+	inline bool is_dff(const CellInfo *cell) const {
+		return type_is_dff(cell->type);
+	}
 };
 
 struct GowinArch : HimbaechelArch
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index e6ddd433e7..a40c76aed3 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -140,9 +140,9 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     create_switch_matrix(tt, db, x, y)
     return ttyp
 
-# XXX 6 lut+dff only for now
+# XXX lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    N = 6
+    N = 8
     lut_inputs = ['A', 'B', 'C', 'D']
     if ttyp in created_tiletypes:
         return ttyp
@@ -161,6 +161,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     for j in range(3):
         tt.create_wire(f"CLK{j}", "TILE_CLK")
         tt.create_wire(f"LSR{j}", "TILE_LSR")
+        tt.create_wire(f"CE{j}",  "TILE_CE")
 
     # create logic cells
     for i in range(N):
@@ -169,17 +170,22 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         for j, inp_name in enumerate(lut_inputs):
             tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
         tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
-        # FF data can come from LUT output, but we pretend that we can use
-        # any LUT input
-        tt.create_pip(f"F{i}", f"XD{i}")
-        for inp_name in lut_inputs:
-            tt.create_pip(f"{inp_name}{i}", f"XD{i}")
-        # FF
-        ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
-        tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
-        tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
-        tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
-        tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
+        if i < 6:
+            # FF data can come from LUT output, but we pretend that we can use
+            # any LUT input
+            tt.create_pip(f"F{i}", f"XD{i}")
+            for inp_name in lut_inputs:
+                tt.create_pip(f"{inp_name}{i}", f"XD{i}")
+            # FF
+            ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
+            tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
+            tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
+            tt.add_bel_pin(ff, "SET", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
     create_switch_matrix(tt, db, x, y)
     return ttyp
 

From f7fbe0db04075f5ad87b3868495f6f5ea666d50e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 1 Jul 2023 19:09:27 +1000
Subject: [PATCH 434/712] gowin: Himbaechel, fix style

Run clang-format

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 416 ++++++++++++++++----------------
 himbaechel/uarch/gowin/gowin.h  |  38 ++-
 2 files changed, 225 insertions(+), 229 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index b030b62008..3c7ec55c5d 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -7,230 +7,234 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void GowinImpl::init(Context *ctx) {
-	h.init(ctx);
-	HimbaechelAPI::init(ctx);
-	// These fields go in the header of the output JSON file and can help
-	// gowin_pack support different architectures
-	ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
-	// XXX it would be nice to write chip/base name in the header as well,
-	// but maybe that will come up when there is clarity with
-	// Arch::archArgsToId
+void GowinImpl::init(Context *ctx)
+{
+    h.init(ctx);
+    HimbaechelAPI::init(ctx);
+    // These fields go in the header of the output JSON file and can help
+    // gowin_pack support different architectures
+    ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
+    // XXX it would be nice to write chip/base name in the header as well,
+    // but maybe that will come up when there is clarity with
+    // Arch::archArgsToId
 }
 
-void GowinImpl::prePlace() {
-	ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
-	ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
-	ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
-	ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
-	ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
-	ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
-	ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
-	assign_cell_info();
+void GowinImpl::prePlace()
+{
+    ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
+    ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
+    ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
+    ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
+    ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
+    ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
+    ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
+    assign_cell_info();
 }
 
-void GowinImpl::pack() {
-	// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
-	const pool<CellTypePort> top_ports{
-			CellTypePort(id_IBUF, id_I),
-			CellTypePort(id_OBUF, id_O),
-	};
-	h.remove_nextpnr_iobs(top_ports);
-	// Replace constants with LUTs
-	const dict<IdString, Property> vcc_params;
-	const dict<IdString, Property> gnd_params;
-	h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
-
-	// disconnect the constant LUT inputs
-	mod_lut_inputs();
-
-	// Constrain directly connected LUTs and FFs together to use dedicated resources
-	int lutffs = h.constrain_cell_pairs(
-			pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
-			pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
-			  {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
-			  {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
-			  {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
-			  {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},1);
-	log_info("Constrained %d LUTFF pairs.\n", lutffs);
+void GowinImpl::pack()
+{
+    // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+    const pool<CellTypePort> top_ports{
+            CellTypePort(id_IBUF, id_I),
+            CellTypePort(id_OBUF, id_O),
+    };
+    h.remove_nextpnr_iobs(top_ports);
+    // Replace constants with LUTs
+    const dict<IdString, Property> vcc_params;
+    const dict<IdString, Property> gnd_params;
+    h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
+
+    // disconnect the constant LUT inputs
+    mod_lut_inputs();
+
+    // Constrain directly connected LUTs and FFs together to use dedicated resources
+    int lutffs = h.constrain_cell_pairs(
+            pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
+            pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
+                               {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
+                               {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
+                               {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
+                               {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},
+            1);
+    log_info("Constrained %d LUTFF pairs.\n", lutffs);
 }
 
-bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const {
-	Loc l = ctx->getBelLocation(bel);
-	if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
-		return slice_valid(l.x, l.y, l.z / 2);
-	} else {
-		return true;
-	}
+bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
+{
+    Loc l = ctx->getBelLocation(bel);
+    if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
+        return slice_valid(l.x, l.y, l.z / 2);
+    } else {
+        return true;
+    }
 }
 
 // Bel bucket functions
-IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const {
-	if (cell_type.in(id_IBUF, id_OBUF)) {
-		return id_IOB;
-	}
-	if (type_is_lut(cell_type)) {
-		return id_LUT4;
-	}
-	if (type_is_dff(cell_type)) {
-		return id_DFF;
-	}
-	if (cell_type == id_GOWIN_GND) {
-		return id_GND;
-	}
-	if (cell_type == id_GOWIN_VCC) {
-		return id_VCC;
-	}
-	return cell_type;
+IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
+{
+    if (cell_type.in(id_IBUF, id_OBUF)) {
+        return id_IOB;
+    }
+    if (type_is_lut(cell_type)) {
+        return id_LUT4;
+    }
+    if (type_is_dff(cell_type)) {
+        return id_DFF;
+    }
+    if (cell_type == id_GOWIN_GND) {
+        return id_GND;
+    }
+    if (cell_type == id_GOWIN_VCC) {
+        return id_VCC;
+    }
+    return cell_type;
 }
 
-bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const {
-	IdString bel_type = ctx->getBelType(bel);
-	if (bel_type == id_IOB) {
-		return cell_type.in(id_IBUF, id_OBUF);
-	}
-	if (bel_type == id_LUT4) {
-		return type_is_lut(cell_type);
-	}
-	if (bel_type == id_DFF) {
-		return type_is_dff(cell_type);
-	}
-	if (bel_type == id_GND) {
-		return cell_type == id_GOWIN_GND;
-	}
-	if (bel_type == id_VCC) {
-		return cell_type == id_GOWIN_VCC;
-	}
-	return (bel_type == cell_type);
+bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
+{
+    IdString bel_type = ctx->getBelType(bel);
+    if (bel_type == id_IOB) {
+        return cell_type.in(id_IBUF, id_OBUF);
+    }
+    if (bel_type == id_LUT4) {
+        return type_is_lut(cell_type);
+    }
+    if (bel_type == id_DFF) {
+        return type_is_dff(cell_type);
+    }
+    if (bel_type == id_GND) {
+        return cell_type == id_GOWIN_GND;
+    }
+    if (bel_type == id_VCC) {
+        return cell_type == id_GOWIN_VCC;
+    }
+    return (bel_type == cell_type);
 }
 
-void GowinImpl::assign_cell_info() {
-	fast_cell_info.resize(ctx->cells.size());
-	for (auto &cell : ctx->cells) {
-		CellInfo *ci = cell.second.get();
-		auto &fc = fast_cell_info.at(ci->flat_index);
-		if (is_lut(ci)) {
-			fc.lut_f = ci->getPort(id_F);
-		} else if (is_dff(ci)) {
-			fc.ff_d = ci->getPort(id_D);
-			fc.ff_clk = ci->getPort(id_CLK);
-			fc.ff_ce = ci->getPort(id_CE);
-			for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
-				fc.ff_lsr = ci->getPort(port);
-				if (fc.ff_lsr != nullptr) {
-					break;
-				}
-			}
-		}
-	}
+void GowinImpl::assign_cell_info()
+{
+    fast_cell_info.resize(ctx->cells.size());
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        auto &fc = fast_cell_info.at(ci->flat_index);
+        if (is_lut(ci)) {
+            fc.lut_f = ci->getPort(id_F);
+        } else if (is_dff(ci)) {
+            fc.ff_d = ci->getPort(id_D);
+            fc.ff_clk = ci->getPort(id_CLK);
+            fc.ff_ce = ci->getPort(id_CE);
+            for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+                fc.ff_lsr = ci->getPort(port);
+                if (fc.ff_lsr != nullptr) {
+                    break;
+                }
+            }
+        }
+    }
 }
 
-bool GowinImpl::slice_valid(int x, int y, int z) const {
-	const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
-	const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-	if (!ff) {
-		return true; // always valid if only LUT used
-	}
-	const auto &ff_data = fast_cell_info.at(ff->flat_index);
-	if (lut) {
-		const auto &lut_data = fast_cell_info.at(lut->flat_index);
-		if (ff_data.ff_d != lut_data.lut_f)
-			return false;
-	}
-	int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
-	const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
-	if (adj_ff == nullptr) {
-		return true;
-	}
-	// DFFs must be same type or compatible
-	if (ff->type != adj_ff->type &&
-			(   (ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR))
-			 || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS))
-			 || (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE))
-			 || (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE))
-			 || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC))
-			 || (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP))
-			 || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE))
-			 || (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE))
-			 || (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR))
-			 || (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS))
-			 || (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE))
-			 || (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE))
-			 || (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC))
-			 || (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP))
-			 || (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE))
-			 || (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE))
-			 )) {
-		return false;
-	}
-
-	// CE, LSR and CLK must match
-	const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
-	if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
-		return true;
-	}
-	//
-	return false;
+bool GowinImpl::slice_valid(int x, int y, int z) const
+{
+    const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+    const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+    if (!ff) {
+        return true; // always valid if only LUT used
+    }
+    const auto &ff_data = fast_cell_info.at(ff->flat_index);
+    if (lut) {
+        const auto &lut_data = fast_cell_info.at(lut->flat_index);
+        if (ff_data.ff_d != lut_data.lut_f)
+            return false;
+    }
+    int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
+    const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
+    if (adj_ff == nullptr) {
+        return true;
+    }
+    // DFFs must be same type or compatible
+    if (ff->type != adj_ff->type &&
+        ((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
+         (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
+         (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
+         (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
+         (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
+         (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
+         (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
+         (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
+         (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
+         (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
+         (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
+         (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
+         (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
+        return false;
+    }
+
+    // CE, LSR and CLK must match
+    const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
+    if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
+        return true;
+    }
+    //
+    return false;
 }
 
 // modify LUTs with constant inputs
-void GowinImpl::mod_lut_inputs(void) {
-	for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
-		auto net = ctx->nets.find(netname);
-		if (net == ctx->nets.end()) {
-			continue;
-		}
-		NetInfo *constnet = net->second.get();
-		for (auto user : constnet->users) {
-			CellInfo *uc = user.cell;
-			if (ctx->verbose)
-				log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
-
-			if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
-				auto it_param = uc->params.find(id_INIT);
-				if (it_param == uc->params.end())
-					log_error("No initialization for lut found.\n");
-
-				int64_t uc_init = it_param->second.intval;
-				int64_t mask = 0;
-				uint8_t amt = 0;
-
-				if (user.port == id_I0) {
-					mask = 0x5555;
-					amt = 1;
-				} else if (user.port == id_I1) {
-					mask = 0x3333;
-					amt = 2;
-				} else if (user.port == id_I2) {
-					mask = 0x0F0F;
-					amt = 4;
-				} else if (user.port == id_I3) {
-					mask = 0x00FF;
-					amt = 8;
-				} else {
-					log_error("Port number invalid.\n");
-				}
-
-				if ((constnet->name == ctx->id("$PACKER_GND"))) {
-					uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
-				} else {
-					uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
-				}
-
-				size_t uc_init_len = it_param->second.to_string().length();
-				uc_init &= (1LL << uc_init_len) - 1;
-
-				if (ctx->verbose)
-					log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
-							 uc_init);
-
-				it_param->second = Property(uc_init, uc_init_len);
-				uc->disconnectPort(user.port);
-			}
-		}
-	}
+void GowinImpl::mod_lut_inputs(void)
+{
+    for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
+        auto net = ctx->nets.find(netname);
+        if (net == ctx->nets.end()) {
+            continue;
+        }
+        NetInfo *constnet = net->second.get();
+        for (auto user : constnet->users) {
+            CellInfo *uc = user.cell;
+            if (ctx->verbose)
+                log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
+
+            if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
+                auto it_param = uc->params.find(id_INIT);
+                if (it_param == uc->params.end())
+                    log_error("No initialization for lut found.\n");
+
+                int64_t uc_init = it_param->second.intval;
+                int64_t mask = 0;
+                uint8_t amt = 0;
+
+                if (user.port == id_I0) {
+                    mask = 0x5555;
+                    amt = 1;
+                } else if (user.port == id_I1) {
+                    mask = 0x3333;
+                    amt = 2;
+                } else if (user.port == id_I2) {
+                    mask = 0x0F0F;
+                    amt = 4;
+                } else if (user.port == id_I3) {
+                    mask = 0x00FF;
+                    amt = 8;
+                } else {
+                    log_error("Port number invalid.\n");
+                }
+
+                if ((constnet->name == ctx->id("$PACKER_GND"))) {
+                    uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
+                } else {
+                    uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
+                }
+
+                size_t uc_init_len = it_param->second.to_string().length();
+                uc_init &= (1LL << uc_init_len) - 1;
+
+                if (ctx->verbose)
+                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
+                             uc_init);
+
+                it_param->second = Property(uc_init, uc_init_len);
+                uc->disconnectPort(user.port);
+            }
+        }
+    }
 }
 
-
-
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index d44a00d47c..1fa7d9dedb 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -20,7 +20,7 @@ struct GowinImpl : HimbaechelAPI
     void init(Context *ctx) override;
 
     void prePlace() override;
-	void pack() override;
+    void pack() override;
 
     bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
 
@@ -36,33 +36,26 @@ struct GowinImpl : HimbaechelAPI
     struct GowinCellInfo
     {
         const NetInfo *lut_f = nullptr;
-		const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
+        const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
     };
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
     bool slice_valid(int x, int y, int z) const;
 
-	// modify LUTs with constant inputs
-	void mod_lut_inputs(void);
+    // modify LUTs with constant inputs
+    void mod_lut_inputs(void);
 
-	// Return true if a cell is a LUT
-	inline bool type_is_lut(IdString cell_type) const {
-		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
-	}
-	inline bool is_lut(const CellInfo *cell) const {
-		return type_is_lut(cell->type);
-	}
-	// Return true if a cell is a DFF
-	inline bool type_is_dff(IdString cell_type) const {
-		return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE,
-				     id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE,
-					 id_DFFR, id_DFFRE, id_DFFNR, id_DFFNRE,
-					 id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE,
-					 id_DFFC, id_DFFCE, id_DFFNC, id_DFFNCE);
-	}
-	inline bool is_dff(const CellInfo *cell) const {
-		return type_is_dff(cell->type);
-	}
+    // Return true if a cell is a LUT
+    inline bool type_is_lut(IdString cell_type) const { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
+    inline bool is_lut(const CellInfo *cell) const { return type_is_lut(cell->type); }
+    // Return true if a cell is a DFF
+    inline bool type_is_dff(IdString cell_type) const
+    {
+        return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR,
+                            id_DFFRE, id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE,
+                            id_DFFNC, id_DFFNCE);
+    }
+    inline bool is_dff(const CellInfo *cell) const { return type_is_dff(cell->type); }
 };
 
 struct GowinArch : HimbaechelArch
@@ -77,4 +70,3 @@ struct GowinArch : HimbaechelArch
 
 NEXTPNR_NAMESPACE_END
 #endif
-

From c82654d003a81a778f88e67e303dd47185dd44cb Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 2 Jul 2023 16:09:39 +1000
Subject: [PATCH 435/712] gowin: Himbaechel. Add a wideluts

- MUX2_LUT5, MUX2_LUT6, MUX2_LUT7 and MUX2_LUT8 support;
- storing a common class of files in extra_data;
- misc fixes.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc          | 127 +++++++++++++++++++----
 himbaechel/uarch/gowin/gowin.h           |  18 ++++
 himbaechel/uarch/gowin/gowin_arch_gen.py |  80 ++++++++++++--
 3 files changed, 196 insertions(+), 29 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 3c7ec55c5d..0489e0c4c4 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -19,17 +19,7 @@ void GowinImpl::init(Context *ctx)
     // Arch::archArgsToId
 }
 
-void GowinImpl::prePlace()
-{
-    ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
-    ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
-    ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
-    ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
-    ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
-    ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
-    ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
-    assign_cell_info();
-}
+void GowinImpl::prePlace() { assign_cell_info(); }
 
 void GowinImpl::pack()
 {
@@ -47,15 +37,17 @@ void GowinImpl::pack()
     // disconnect the constant LUT inputs
     mod_lut_inputs();
 
+    pack_wideluts();
+
     // Constrain directly connected LUTs and FFs together to use dedicated resources
-    int lutffs = h.constrain_cell_pairs(
-            pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
-            pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
-                               {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
-                               {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
-                               {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
-                               {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},
-            1);
+    auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
+    auto dff_ins = pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
+                                      {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
+                                      {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
+                                      {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
+                                      {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
+
+    int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
     log_info("Constrained %d LUTFF pairs.\n", lutffs);
 }
 
@@ -237,4 +229,101 @@ void GowinImpl::mod_lut_inputs(void)
     }
 }
 
+// make cluster from LUTs and MUXes
+void GowinImpl::pack_wideluts(void)
+{
+    // children's offsets
+    struct _children
+    {
+        IdString port;
+        int dx, dz;
+    } mux_inputs[4][2] = {{{id_I0, 1, -7}, {id_I1, 0, -7}},
+                          {{id_I0, 0, 4}, {id_I1, 0, -4}},
+                          {{id_I0, 0, 2}, {id_I1, 0, -2}},
+                          {{id_I0, 0, -BelZ::MUX20_Z}, {id_I1, 0, 2 - BelZ::MUX20_Z}}};
+    typedef std::function<void(CellInfo &, CellInfo *, int, int)> recurse_func_t;
+    recurse_func_t make_cluster = [&, this](CellInfo &ci_root, CellInfo *ci_cursor, int dx, int dz) {
+        _children *inputs;
+        if (is_lut(ci_cursor)) {
+            return;
+        }
+        switch (ci_cursor->type.hash()) {
+        case ID_MUX2_LUT8:
+            inputs = mux_inputs[0];
+            break;
+        case ID_MUX2_LUT7:
+            inputs = mux_inputs[1];
+            break;
+        case ID_MUX2_LUT6:
+            inputs = mux_inputs[2];
+            break;
+        case ID_MUX2_LUT5:
+            inputs = mux_inputs[3];
+            break;
+        default:
+            log_error("Bad MUX2 node:%s\n", ctx->nameOf(ci_cursor));
+        }
+        for (int i = 0; i < 2; ++i) {
+            // input src
+            NetInfo *in = ci_cursor->getPort(inputs[i].port);
+            NPNR_ASSERT(in && in->driver.cell);
+            int child_dx = dx + inputs[i].dx;
+            int child_dz = dz + inputs[i].dz;
+            ci_root.constr_children.push_back(in->driver.cell);
+            in->driver.cell->cluster = ci_root.name;
+            in->driver.cell->constr_abs_z = false;
+            in->driver.cell->constr_x = child_dx;
+            in->driver.cell->constr_y = 0;
+            in->driver.cell->constr_z = child_dz;
+            make_cluster(ci_root, in->driver.cell, child_dx, child_dz);
+        }
+    };
+
+    // look for MUX2
+    // MUX2_LUT8 create right away, collect others
+    std::vector<IdString> muxes[3];
+    int packed[4] = {0, 0, 0, 0};
+    for (auto &cell : ctx->cells) {
+        auto &ci = *cell.second;
+        if (ci.cluster != ClusterId()) {
+            continue;
+        }
+        if (ci.type == id_MUX2_LUT8) {
+            ci.cluster = ci.name;
+            ci.constr_abs_z = 0;
+            make_cluster(ci, &ci, 0, 0);
+            ++packed[0];
+            continue;
+        }
+        if (ci.type.in(id_MUX2_LUT7, id_MUX2_LUT6, id_MUX2_LUT5)) {
+            switch (ci.type.hash()) {
+            case ID_MUX2_LUT7:
+                muxes[0].push_back(cell.first);
+                break;
+            case ID_MUX2_LUT6:
+                muxes[1].push_back(cell.first);
+                break;
+            default: // ID_MUX2_LUT5
+                muxes[2].push_back(cell.first);
+                break;
+            }
+        }
+    }
+    // create others
+    for (int i = 0; i < 3; ++i) {
+        for (IdString cell_name : muxes[i]) {
+            auto &ci = *ctx->cells.at(cell_name);
+            if (ci.cluster != ClusterId()) {
+                continue;
+            }
+            ci.cluster = ci.name;
+            ci.constr_abs_z = 0;
+            make_cluster(ci, &ci, 0, 0);
+            ++packed[i + 1];
+        }
+    }
+    log_info("Packed MUX2_LUT8:%d, MUX2_LU7:%d, MUX2_LUT6:%d, MUX2_LUT5:%d\n", packed[0], packed[1], packed[2],
+             packed[3]);
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 1fa7d9dedb..ed18cdab36 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -45,6 +45,8 @@ struct GowinImpl : HimbaechelAPI
     // modify LUTs with constant inputs
     void mod_lut_inputs(void);
 
+    void pack_wideluts(void);
+
     // Return true if a cell is a LUT
     inline bool type_is_lut(IdString cell_type) const { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
     inline bool is_lut(const CellInfo *cell) const { return type_is_lut(cell->type); }
@@ -68,5 +70,21 @@ struct GowinArch : HimbaechelArch
 } exampleArch;
 } // namespace
 
+// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
+namespace BelZ {
+enum
+{
+    LUT0_Z = 0,
+    LUT7_Z = 14,
+    MUX20_Z = 16,
+    MUX21_Z = 18,
+    MUX23_Z = 22,
+    MUX27_Z = 29,
+
+    VCC_Z = 277,
+    VSS_Z = 278
+};
+}
+
 NEXTPNR_NAMESPACE_END
 #endif
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index a40c76aed3..08a1e5d8ef 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -12,8 +12,27 @@
 from apycula import chipdb
 
 # Z of the bels
-VCC_Z = 277
-GND_Z = 288
+# sync with C++ part!
+LUT0_Z  = 0       # z(DFFx) = z(LUTx) + 1
+LUT7_Z  = 14
+MUX20_Z = 16
+MUX21_Z = 18
+MUX23_Z = 22
+MUX27_Z = 29
+
+VCC_Z   = 277
+GND_Z   = 278
+
+@dataclass
+class TileExtraData(BBAStruct):
+    tile_class: IdString # The general functionality of the slightly different tiles,
+                         # let's say the behavior of LUT+DFF in the tiles are completely identical,
+                         # but one of them also contains clock-wire switches,
+                         # then we assign them to the same LOGIC class.
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.tile_class.index)
 
 created_tiletypes = set()
 
@@ -72,6 +91,10 @@ def create_nodes(chip: Chip, db: chipdb):
                     nodes.append([NodeWire(x, y, f'{d}8{i}0'),
                         NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
                         NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
+            # I0 for MUX2_LUT8
+            if x < X - 1 and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC') and  chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC'):
+                nodes.append([NodeWire(x, y, 'OF30'),
+                              NodeWire(x + 1, y, 'OF3')])
             for node in nodes:
                 chip.add_node(node)
             # VCC and VSS sources in the all tiles
@@ -99,7 +122,9 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
         return ttyp
-    tt = chip.create_tile_type(f"NULL_{ttyp}")
+    typename = "NULL"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
     create_switch_matrix(tt, db, x, y)
     return ttyp
 
@@ -107,7 +132,9 @@ def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
 def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
         return ttyp
-    tt = chip.create_tile_type(f"CORNER_{ttyp}")
+    typename = "CORNER"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     if x == 0 and y == 0:
         # GND is the logic low level generator
@@ -126,7 +153,10 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
 def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
         return ttyp
-    tt = chip.create_tile_type(f"IO_{ttyp}")
+    typename = "IO"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
     for i in range(2):
         name = ['IOBA', 'IOBB'][i]
         # wires
@@ -142,13 +172,15 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
 
 # XXX lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    N = 8
     lut_inputs = ['A', 'B', 'C', 'D']
     if ttyp in created_tiletypes:
         return ttyp
-    tt = chip.create_tile_type(f"LOGIC_{ttyp}")
+    typename = "LOGIC"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
     # setup wires
-    for i in range(N):
+    for i in range(8):
         for inp_name in lut_inputs:
             tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
         tt.create_wire(f"F{i}", "LUT_OUT")
@@ -162,9 +194,13 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.create_wire(f"CLK{j}", "TILE_CLK")
         tt.create_wire(f"LSR{j}", "TILE_LSR")
         tt.create_wire(f"CE{j}",  "TILE_CE")
+    for j in range(8):
+        tt.create_wire(f"OF{j}", "MUX_OUT")
+        tt.create_wire(f"SEL{j}", "MUX_SEL")
+    tt.create_wire("OF30", "MUX_OUT")
 
     # create logic cells
-    for i in range(N):
+    for i in range(8):
         # LUT
         lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
         for j, inp_name in enumerate(lut_inputs):
@@ -186,6 +222,30 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
             tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
+    # wide luts
+    for i in range(4):
+        ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
+        tt.add_bel_pin(ff, "I0", f"F{i * 2}", PinType.INPUT)
+        tt.add_bel_pin(ff, "I1", f"F{i * 2 + 1}", PinType.INPUT)
+        tt.add_bel_pin(ff, "O",  f"OF{i * 2}", PinType.OUTPUT)
+        tt.add_bel_pin(ff, "S0", f"SEL{i * 2}", PinType.INPUT)
+    for i in range(2):
+        ff = tt.create_bel(f"MUX{i * 4 + 1}", "MUX2_LUT6", z = MUX21_Z + i * 8)
+        tt.add_bel_pin(ff, "I0", f"OF{i * 4 + 2}", PinType.INPUT)
+        tt.add_bel_pin(ff, "I1", f"OF{i * 4}", PinType.INPUT)
+        tt.add_bel_pin(ff, "O",  f"OF{i * 4 + 1}", PinType.OUTPUT)
+        tt.add_bel_pin(ff, "S0", f"SEL{i * 4 + 1}", PinType.INPUT)
+    ff = tt.create_bel(f"MUX3", "MUX2_LUT7", z = MUX23_Z)
+    tt.add_bel_pin(ff, "I0", f"OF5", PinType.INPUT)
+    tt.add_bel_pin(ff, "I1", f"OF1", PinType.INPUT)
+    tt.add_bel_pin(ff, "O",  f"OF3", PinType.OUTPUT)
+    tt.add_bel_pin(ff, "S0", f"SEL3", PinType.INPUT)
+    ff = tt.create_bel(f"MUX7", "MUX2_LUT8", z = MUX27_Z)
+    tt.add_bel_pin(ff, "I0", f"OF30", PinType.INPUT)
+    tt.add_bel_pin(ff, "I1", f"OF3", PinType.INPUT)
+    tt.add_bel_pin(ff, "O",  f"OF7", PinType.OUTPUT)
+    tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
+
     create_switch_matrix(tt, db, x, y)
     return ttyp
 
@@ -212,7 +272,7 @@ def main():
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
     logic_tiletypes = {12, 13, 14, 15, 16, 17}
-    io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;)
+    io_tiletypes = {53, 55, 58, 59, 64, 65}
     # Setup tile grid
     for x in range(X):
         for y in range(Y):

From c9b23a01dbde9b287c73e1969e4d2b0643d2a4ce Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 5 Jul 2023 12:49:25 +1000
Subject: [PATCH 436/712] gowin: Himbaechel. Add ALU.

- Added support for ALU running in "2" ADDSUB mode, the mode that yosys generates for gowin;
- Supports specifying an arbitrary input carry as well as passing the output carry to logic;
- A small restructuring of the source files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc          | 348 ++++++++-----------
 himbaechel/uarch/gowin/gowin.h           |  75 +----
 himbaechel/uarch/gowin/gowin_arch_gen.py |  44 ++-
 himbaechel/uarch/gowin/pack.cc           | 409 +++++++++++++++++++++++
 himbaechel/uarch/gowin/pack.h            |  12 +
 5 files changed, 609 insertions(+), 279 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/pack.cc
 create mode 100644 himbaechel/uarch/gowin/pack.h

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 0489e0c4c4..9c691a8ece 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -1,12 +1,62 @@
 #include "himbaechel_api.h"
+#include "himbaechel_helpers.h"
 #include "log.h"
 #include "nextpnr.h"
-#include "util.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
 
 #include "gowin.h"
+#include "pack.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
+namespace {
+struct GowinImpl : HimbaechelAPI
+{
+
+    ~GowinImpl(){};
+    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init(Context *ctx) override;
+
+    void prePlace() override;
+    void postPlace() override;
+    void pack() override;
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
+
+    // Bel bucket functions
+    IdString getBelBucketForCellType(IdString cell_type) const override;
+
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
+
+  private:
+    HimbaechelHelpers h;
+
+    // Validity checking
+    struct GowinCellInfo
+    {
+        const NetInfo *lut_f = nullptr;
+        const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
+        const NetInfo *alu_sum = nullptr;
+    };
+    std::vector<GowinCellInfo> fast_cell_info;
+    void assign_cell_info();
+
+    // bel placement validation
+    bool slice_valid(int x, int y, int z) const;
+};
+
+struct GowinArch : HimbaechelArch
+{
+    GowinArch() : HimbaechelArch("gowin"){};
+    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<GowinImpl>();
+    }
+} gowinrArch;
+
 void GowinImpl::init(Context *ctx)
 {
     h.init(ctx);
@@ -21,44 +71,23 @@ void GowinImpl::init(Context *ctx)
 
 void GowinImpl::prePlace() { assign_cell_info(); }
 
-void GowinImpl::pack()
-{
-    // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
-    const pool<CellTypePort> top_ports{
-            CellTypePort(id_IBUF, id_I),
-            CellTypePort(id_OBUF, id_O),
-    };
-    h.remove_nextpnr_iobs(top_ports);
-    // Replace constants with LUTs
-    const dict<IdString, Property> vcc_params;
-    const dict<IdString, Property> gnd_params;
-    h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
-
-    // disconnect the constant LUT inputs
-    mod_lut_inputs();
-
-    pack_wideluts();
-
-    // Constrain directly connected LUTs and FFs together to use dedicated resources
-    auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
-    auto dff_ins = pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
-                                      {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
-                                      {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
-                                      {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
-                                      {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
-
-    int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
-    log_info("Constrained %d LUTFF pairs.\n", lutffs);
-}
+void GowinImpl::pack() { gowin_pack(ctx); }
 
 bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     Loc l = ctx->getBelLocation(bel);
-    if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
+    if (!ctx->getBoundBelCell(bel)) {
+        return true;
+    }
+    IdString bel_type = ctx->getBelType(bel);
+    if (bel_type.in(id_LUT4, id_DFF)) {
         return slice_valid(l.x, l.y, l.z / 2);
     } else {
-        return true;
+        if (bel_type == id_ALU) {
+            return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
+        }
     }
+    return true;
 }
 
 // Bel bucket functions
@@ -111,7 +140,9 @@ void GowinImpl::assign_cell_info()
         auto &fc = fast_cell_info.at(ci->flat_index);
         if (is_lut(ci)) {
             fc.lut_f = ci->getPort(id_F);
-        } else if (is_dff(ci)) {
+            continue;
+        }
+        if (is_dff(ci)) {
             fc.ff_d = ci->getPort(id_D);
             fc.ff_clk = ci->getPort(id_CLK);
             fc.ff_ce = ci->getPort(id_CE);
@@ -121,209 +152,100 @@ void GowinImpl::assign_cell_info()
                     break;
                 }
             }
+            continue;
+        }
+        if (is_alu(ci)) {
+            fc.alu_sum = ci->getPort(id_SUM);
+            continue;
         }
     }
 }
 
+// placement validation
 bool GowinImpl::slice_valid(int x, int y, int z) const
 {
     const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
     const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-    if (!ff) {
-        return true; // always valid if only LUT used
-    }
-    const auto &ff_data = fast_cell_info.at(ff->flat_index);
-    if (lut) {
-        const auto &lut_data = fast_cell_info.at(lut->flat_index);
-        if (ff_data.ff_d != lut_data.lut_f)
-            return false;
-    }
-    int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
-    const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
-    if (adj_ff == nullptr) {
-        return true;
-    }
-    // DFFs must be same type or compatible
-    if (ff->type != adj_ff->type &&
-        ((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
-         (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
-         (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
-         (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
-         (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
-         (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
-         (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
-         (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
-         (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
-         (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
-         (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
-         (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
-         (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
+    const CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z)));
+
+    if (alu && lut) {
         return false;
     }
 
-    // CE, LSR and CLK must match
-    const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
-    if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
-        return true;
+    // check for ALU/LUT in the adjacent cell
+    int adj_lut_z = (1 - (z & 1) * 2 + z) * 2;
+    int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
+    const CellInfo *adj_lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z)));
+    const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z + 1)));
+    const CellInfo *adj_alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)));
+
+    if ((alu && (adj_lut || (adj_ff && !adj_alu))) || ((lut || (ff && !alu)) && adj_alu)) {
+        return false;
     }
-    //
-    return false;
-}
 
-// modify LUTs with constant inputs
-void GowinImpl::mod_lut_inputs(void)
-{
-    for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
-        auto net = ctx->nets.find(netname);
-        if (net == ctx->nets.end()) {
-            continue;
+    // if there is DFF it must be connected to this LUT or ALU
+    if (ff) {
+        const auto &ff_data = fast_cell_info.at(ff->flat_index);
+        if (lut) {
+            const auto &lut_data = fast_cell_info.at(lut->flat_index);
+            if (ff_data.ff_d != lut_data.lut_f) {
+                return false;
+            }
         }
-        NetInfo *constnet = net->second.get();
-        for (auto user : constnet->users) {
-            CellInfo *uc = user.cell;
-            if (ctx->verbose)
-                log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
-
-            if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
-                auto it_param = uc->params.find(id_INIT);
-                if (it_param == uc->params.end())
-                    log_error("No initialization for lut found.\n");
-
-                int64_t uc_init = it_param->second.intval;
-                int64_t mask = 0;
-                uint8_t amt = 0;
-
-                if (user.port == id_I0) {
-                    mask = 0x5555;
-                    amt = 1;
-                } else if (user.port == id_I1) {
-                    mask = 0x3333;
-                    amt = 2;
-                } else if (user.port == id_I2) {
-                    mask = 0x0F0F;
-                    amt = 4;
-                } else if (user.port == id_I3) {
-                    mask = 0x00FF;
-                    amt = 8;
-                } else {
-                    log_error("Port number invalid.\n");
-                }
-
-                if ((constnet->name == ctx->id("$PACKER_GND"))) {
-                    uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
-                } else {
-                    uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
-                }
-
-                size_t uc_init_len = it_param->second.to_string().length();
-                uc_init &= (1LL << uc_init_len) - 1;
-
-                if (ctx->verbose)
-                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
-                             uc_init);
+        if (alu) {
+            const auto &alu_data = fast_cell_info.at(alu->flat_index);
+            if (ff_data.ff_d != alu_data.alu_sum) {
+                return false;
+            }
+        }
+        if (adj_ff) {
+            // DFFs must be same type or compatible
+            if (ff->type != adj_ff->type && ((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) ||
+                                             (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
+                                             (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
+                                             (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) ||
+                                             (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
+                                             (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) ||
+                                             (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
+                                             (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
+                                             (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
+                                             (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
+                                             (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
+                                             (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
+                                             (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
+                                             (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
+                                             (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
+                                             (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
+                return false;
+            }
 
-                it_param->second = Property(uc_init, uc_init_len);
-                uc->disconnectPort(user.port);
+            // CE, LSR and CLK must match
+            const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
+            if (adj_ff_data.ff_lsr != ff_data.ff_lsr) {
+                return false;
+            }
+            if (adj_ff_data.ff_clk != ff_data.ff_clk) {
+                return false;
+            }
+            if (adj_ff_data.ff_ce != ff_data.ff_ce) {
+                return false;
             }
         }
     }
+    return true;
 }
 
-// make cluster from LUTs and MUXes
-void GowinImpl::pack_wideluts(void)
+void GowinImpl::postPlace()
 {
-    // children's offsets
-    struct _children
-    {
-        IdString port;
-        int dx, dz;
-    } mux_inputs[4][2] = {{{id_I0, 1, -7}, {id_I1, 0, -7}},
-                          {{id_I0, 0, 4}, {id_I1, 0, -4}},
-                          {{id_I0, 0, 2}, {id_I1, 0, -2}},
-                          {{id_I0, 0, -BelZ::MUX20_Z}, {id_I1, 0, 2 - BelZ::MUX20_Z}}};
-    typedef std::function<void(CellInfo &, CellInfo *, int, int)> recurse_func_t;
-    recurse_func_t make_cluster = [&, this](CellInfo &ci_root, CellInfo *ci_cursor, int dx, int dz) {
-        _children *inputs;
-        if (is_lut(ci_cursor)) {
-            return;
-        }
-        switch (ci_cursor->type.hash()) {
-        case ID_MUX2_LUT8:
-            inputs = mux_inputs[0];
-            break;
-        case ID_MUX2_LUT7:
-            inputs = mux_inputs[1];
-            break;
-        case ID_MUX2_LUT6:
-            inputs = mux_inputs[2];
-            break;
-        case ID_MUX2_LUT5:
-            inputs = mux_inputs[3];
-            break;
-        default:
-            log_error("Bad MUX2 node:%s\n", ctx->nameOf(ci_cursor));
-        }
-        for (int i = 0; i < 2; ++i) {
-            // input src
-            NetInfo *in = ci_cursor->getPort(inputs[i].port);
-            NPNR_ASSERT(in && in->driver.cell);
-            int child_dx = dx + inputs[i].dx;
-            int child_dz = dz + inputs[i].dz;
-            ci_root.constr_children.push_back(in->driver.cell);
-            in->driver.cell->cluster = ci_root.name;
-            in->driver.cell->constr_abs_z = false;
-            in->driver.cell->constr_x = child_dx;
-            in->driver.cell->constr_y = 0;
-            in->driver.cell->constr_z = child_dz;
-            make_cluster(ci_root, in->driver.cell, child_dx, child_dz);
-        }
-    };
-
-    // look for MUX2
-    // MUX2_LUT8 create right away, collect others
-    std::vector<IdString> muxes[3];
-    int packed[4] = {0, 0, 0, 0};
-    for (auto &cell : ctx->cells) {
-        auto &ci = *cell.second;
-        if (ci.cluster != ClusterId()) {
-            continue;
-        }
-        if (ci.type == id_MUX2_LUT8) {
-            ci.cluster = ci.name;
-            ci.constr_abs_z = 0;
-            make_cluster(ci, &ci, 0, 0);
-            ++packed[0];
-            continue;
-        }
-        if (ci.type.in(id_MUX2_LUT7, id_MUX2_LUT6, id_MUX2_LUT5)) {
-            switch (ci.type.hash()) {
-            case ID_MUX2_LUT7:
-                muxes[0].push_back(cell.first);
-                break;
-            case ID_MUX2_LUT6:
-                muxes[1].push_back(cell.first);
-                break;
-            default: // ID_MUX2_LUT5
-                muxes[2].push_back(cell.first);
-                break;
-            }
-        }
-    }
-    // create others
-    for (int i = 0; i < 3; ++i) {
-        for (IdString cell_name : muxes[i]) {
-            auto &ci = *ctx->cells.at(cell_name);
-            if (ci.cluster != ClusterId()) {
-                continue;
-            }
-            ci.cluster = ci.name;
-            ci.constr_abs_z = 0;
-            make_cluster(ci, &ci, 0, 0);
-            ++packed[i + 1];
+    if (ctx->debug) {
+        log_info("================== Final Placement ===================\n");
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            IdStringList bel = ctx->getBelName(ci->bel);
+            log_info("%s -> %s\n", ctx->nameOf(ci), bel.str(ctx).c_str());
         }
     }
-    log_info("Packed MUX2_LUT8:%d, MUX2_LU7:%d, MUX2_LUT6:%d, MUX2_LUT5:%d\n", packed[0], packed[1], packed[2],
-             packed[3]);
 }
+} // namespace
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index ed18cdab36..9d2f736dc0 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -1,73 +1,25 @@
 #ifndef GOWIN_H
 #define GOWIN_H
 
-#include "himbaechel_api.h"
-#include "himbaechel_helpers.h"
 #include "nextpnr.h"
 
-#define GEN_INIT_CONSTIDS
-#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
-#include "himbaechel_constids.h"
-
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
-struct GowinImpl : HimbaechelAPI
+// Return true if a cell is a LUT
+inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
+inline bool is_lut(const CellInfo *cell) { return type_is_lut(cell->type); }
+// Return true if a cell is a DFF
+inline bool type_is_dff(IdString cell_type)
 {
-
-    ~GowinImpl(){};
-    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
-    void init(Context *ctx) override;
-
-    void prePlace() override;
-    void pack() override;
-
-    bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
-
-    // Bel bucket functions
-    IdString getBelBucketForCellType(IdString cell_type) const override;
-
-    bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
-
-  private:
-    HimbaechelHelpers h;
-
-    // Validity checking
-    struct GowinCellInfo
-    {
-        const NetInfo *lut_f = nullptr;
-        const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
-    };
-    std::vector<GowinCellInfo> fast_cell_info;
-    void assign_cell_info();
-    bool slice_valid(int x, int y, int z) const;
-
-    // modify LUTs with constant inputs
-    void mod_lut_inputs(void);
-
-    void pack_wideluts(void);
-
-    // Return true if a cell is a LUT
-    inline bool type_is_lut(IdString cell_type) const { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
-    inline bool is_lut(const CellInfo *cell) const { return type_is_lut(cell->type); }
-    // Return true if a cell is a DFF
-    inline bool type_is_dff(IdString cell_type) const
-    {
-        return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR,
-                            id_DFFRE, id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE,
-                            id_DFFNC, id_DFFNCE);
-    }
-    inline bool is_dff(const CellInfo *cell) const { return type_is_dff(cell->type); }
-};
-
-struct GowinArch : HimbaechelArch
-{
-    GowinArch() : HimbaechelArch("gowin"){};
-    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
-    {
-        return std::make_unique<GowinImpl>();
-    }
-} exampleArch;
+    return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR, id_DFFRE,
+                        id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE, id_DFFNC,
+                        id_DFFNCE);
+}
+inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
+// Return true if a cell is a ALU
+inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
+inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
 } // namespace
 
 // Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
@@ -80,6 +32,7 @@ enum
     MUX21_Z = 18,
     MUX23_Z = 22,
     MUX27_Z = 29,
+    ALU0_Z = 30, // :35, 6 ALU
 
     VCC_Z = 277,
     VSS_Z = 278
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 08a1e5d8ef..c3ec84aa23 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -19,6 +19,7 @@
 MUX21_Z = 18
 MUX23_Z = 22
 MUX27_Z = 29
+ALU0_Z  = 30 # : 35, 6 ALUs
 
 VCC_Z   = 277
 GND_Z   = 278
@@ -68,6 +69,7 @@ def create_nodes(chip: Chip, db: chipdb):
     for y in range(Y):
         for x in range(X):
             nodes = []
+            extra_tile_data = chip.tile_type_at(x, y).extra_data
             # SN and EW
             for i in [1, 2]:
                 nodes.append([NodeWire(x, y, f'SN{i}0'),
@@ -92,11 +94,25 @@ def create_nodes(chip: Chip, db: chipdb):
                         NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
                         NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
             # I0 for MUX2_LUT8
-            if x < X - 1 and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC') and  chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC'):
+            if (x < X - 1 and extra_tile_data.tile_class == chip.strs.id('LOGIC')
+                    and  chip.tile_type_at(x + 1, y).extra_data.tile_class == chip.strs.id('LOGIC')):
                 nodes.append([NodeWire(x, y, 'OF30'),
-                              NodeWire(x + 1, y, 'OF3')])
+                             NodeWire(x + 1, y, 'OF3')])
+
+            # ALU
+            if extra_tile_data.tile_class == chip.strs.id('LOGIC'):
+                # local carry chain
+                for i in range(5):
+                    nodes.append([NodeWire(x, y, f'COUT{i}'),
+                                  NodeWire(x, y, f'CIN{i + 1}')]);
+                # gobal carry chain
+                if x > 1 and chip.tile_type_at(x - 1, y).extra_data.tile_class == chip.strs.id('LOGIC'):
+                    nodes.append([NodeWire(x, y, f'CIN0'),
+                                  NodeWire(x - 1, y, f'COUT5')])
+
             for node in nodes:
                 chip.add_node(node)
+
             # VCC and VSS sources in the all tiles
             global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
             global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
@@ -170,16 +186,16 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     create_switch_matrix(tt, db, x, y)
     return ttyp
 
-# XXX lut+dff only for now
+# logic: luts, dffs, alu etc
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    lut_inputs = ['A', 'B', 'C', 'D']
     if ttyp in created_tiletypes:
         return ttyp
     typename = "LOGIC"
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
-    # setup wires
+    lut_inputs = ['A', 'B', 'C', 'D']
+    # setup LUT wires
     for i in range(8):
         for inp_name in lut_inputs:
             tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
@@ -190,14 +206,20 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         # just out of curiosity
         tt.create_wire(f"XD{i}", "FF_INPUT")
         tt.create_wire(f"Q{i}", "FF_OUT")
+    # setup DFF wires
     for j in range(3):
         tt.create_wire(f"CLK{j}", "TILE_CLK")
         tt.create_wire(f"LSR{j}", "TILE_LSR")
         tt.create_wire(f"CE{j}",  "TILE_CE")
+    # setup MUX2 wires
     for j in range(8):
         tt.create_wire(f"OF{j}", "MUX_OUT")
         tt.create_wire(f"SEL{j}", "MUX_SEL")
     tt.create_wire("OF30", "MUX_OUT")
+    # setup ALU wires
+    for j in range(6):
+        tt.create_wire(f"CIN{j}", "ALU_CIN")
+        tt.create_wire(f"COUT{j}", "ALU_COUT")
 
     # create logic cells
     for i in range(8):
@@ -222,6 +244,18 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
             tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
+
+            # ALU
+            ff = tt.create_bel(f"ALU{i}", "ALU", z = i + ALU0_Z)
+            tt.add_bel_pin(ff, "SUM", f"F{i}", PinType.OUTPUT)
+            tt.add_bel_pin(ff, "COUT", f"COUT{i}", PinType.OUTPUT)
+            tt.add_bel_pin(ff, "CIN", f"CIN{i}", PinType.INPUT)
+            # pinout for the ADDSUB ALU mode
+            tt.add_bel_pin(ff, "I0", f"A{i}", PinType.INPUT)
+            tt.add_bel_pin(ff, "I1", f"B{i}", PinType.INPUT)
+            tt.add_bel_pin(ff, "I2", f"C{i}", PinType.INPUT)
+            tt.add_bel_pin(ff, "I3", f"D{i}", PinType.INPUT)
+
     # wide luts
     for i in range(4):
         ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
new file mode 100644
index 0000000000..9989a4305e
--- /dev/null
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -0,0 +1,409 @@
+#include "log.h"
+#include "nextpnr.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+#include "himbaechel_helpers.h"
+
+#include "gowin.h"
+#include "pack.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct GowinPacker
+{
+    Context *ctx;
+    HimbaechelHelpers h;
+
+    GowinPacker(Context *ctx) : ctx(ctx) { h.init(ctx); }
+
+    // ===================================
+    // IO
+    // ===================================
+    void pack_iobs(void)
+    {
+        log_info("Pack IOBs...\n");
+        // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+        const pool<CellTypePort> top_ports{
+                CellTypePort(id_IBUF, id_I),
+                CellTypePort(id_OBUF, id_O),
+        };
+        h.remove_nextpnr_iobs(top_ports);
+    }
+
+    // ===================================
+    // Constant nets
+    // ===================================
+    void handle_constants(void)
+    {
+        log_info("Create constant nets...\n");
+        const dict<IdString, Property> vcc_params;
+        const dict<IdString, Property> gnd_params;
+        h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
+
+        // disconnect the constant LUT inputs
+        log_info("Modify LUTs...\n");
+        for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
+            auto net = ctx->nets.find(netname);
+            if (net == ctx->nets.end()) {
+                continue;
+            }
+            NetInfo *constnet = net->second.get();
+            for (auto user : constnet->users) {
+                CellInfo *uc = user.cell;
+                if (ctx->debug)
+                    log_info("%s user %s/%s\n", ctx->nameOf(constnet), ctx->nameOf(uc), user.port.c_str(ctx));
+
+                if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
+                    auto it_param = uc->params.find(id_INIT);
+                    if (it_param == uc->params.end())
+                        log_error("No initialization for lut found.\n");
+
+                    int64_t uc_init = it_param->second.intval;
+                    int64_t mask = 0;
+                    uint8_t amt = 0;
+
+                    if (user.port == id_I0) {
+                        mask = 0x5555;
+                        amt = 1;
+                    } else if (user.port == id_I1) {
+                        mask = 0x3333;
+                        amt = 2;
+                    } else if (user.port == id_I2) {
+                        mask = 0x0F0F;
+                        amt = 4;
+                    } else if (user.port == id_I3) {
+                        mask = 0x00FF;
+                        amt = 8;
+                    } else {
+                        log_error("Port number invalid.\n");
+                    }
+
+                    if ((constnet->name == ctx->id("$PACKER_GND"))) {
+                        uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
+                    } else {
+                        uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
+                    }
+
+                    size_t uc_init_len = it_param->second.to_string().length();
+                    uc_init &= (1LL << uc_init_len) - 1;
+
+                    if (ctx->verbose && it_param->second.intval != uc_init)
+                        log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc),
+                                 it_param->second.intval, uc_init);
+
+                    it_param->second = Property(uc_init, uc_init_len);
+                    uc->disconnectPort(user.port);
+                }
+            }
+        }
+    }
+
+    // ===================================
+    // Wideluts
+    // ===================================
+    void pack_wideluts(void)
+    {
+        log_info("Pack wide LUTs...\n");
+        // children's offsets
+        struct _children
+        {
+            IdString port;
+            int dx, dz;
+        } mux_inputs[4][2] = {{{id_I0, 1, -7}, {id_I1, 0, -7}},
+                              {{id_I0, 0, 4}, {id_I1, 0, -4}},
+                              {{id_I0, 0, 2}, {id_I1, 0, -2}},
+                              {{id_I0, 0, -BelZ::MUX20_Z}, {id_I1, 0, 2 - BelZ::MUX20_Z}}};
+        typedef std::function<void(CellInfo &, CellInfo *, int, int)> recurse_func_t;
+        recurse_func_t make_cluster = [&, this](CellInfo &ci_root, CellInfo *ci_cursor, int dx, int dz) {
+            _children *inputs;
+            if (is_lut(ci_cursor)) {
+                return;
+            }
+            switch (ci_cursor->type.hash()) {
+            case ID_MUX2_LUT8:
+                inputs = mux_inputs[0];
+                break;
+            case ID_MUX2_LUT7:
+                inputs = mux_inputs[1];
+                break;
+            case ID_MUX2_LUT6:
+                inputs = mux_inputs[2];
+                break;
+            case ID_MUX2_LUT5:
+                inputs = mux_inputs[3];
+                break;
+            default:
+                log_error("Bad MUX2 node:%s\n", ctx->nameOf(ci_cursor));
+            }
+            for (int i = 0; i < 2; ++i) {
+                // input src
+                NetInfo *in = ci_cursor->getPort(inputs[i].port);
+                NPNR_ASSERT(in && in->driver.cell);
+                int child_dx = dx + inputs[i].dx;
+                int child_dz = dz + inputs[i].dz;
+                ci_root.constr_children.push_back(in->driver.cell);
+                in->driver.cell->cluster = ci_root.name;
+                in->driver.cell->constr_abs_z = false;
+                in->driver.cell->constr_x = child_dx;
+                in->driver.cell->constr_y = 0;
+                in->driver.cell->constr_z = child_dz;
+                make_cluster(ci_root, in->driver.cell, child_dx, child_dz);
+            }
+        };
+
+        // look for MUX2
+        // MUX2_LUT8 create right away, collect others
+        std::vector<IdString> muxes[3];
+        int packed[4] = {0, 0, 0, 0};
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (ci.cluster != ClusterId()) {
+                continue;
+            }
+            if (ci.type == id_MUX2_LUT8) {
+                ci.cluster = ci.name;
+                ci.constr_abs_z = false;
+                make_cluster(ci, &ci, 0, 0);
+                ++packed[0];
+                continue;
+            }
+            if (ci.type.in(id_MUX2_LUT7, id_MUX2_LUT6, id_MUX2_LUT5)) {
+                switch (ci.type.hash()) {
+                case ID_MUX2_LUT7:
+                    muxes[0].push_back(cell.first);
+                    break;
+                case ID_MUX2_LUT6:
+                    muxes[1].push_back(cell.first);
+                    break;
+                default: // ID_MUX2_LUT5
+                    muxes[2].push_back(cell.first);
+                    break;
+                }
+            }
+        }
+        // create others
+        for (int i = 0; i < 3; ++i) {
+            for (IdString cell_name : muxes[i]) {
+                auto &ci = *ctx->cells.at(cell_name);
+                if (ci.cluster != ClusterId()) {
+                    continue;
+                }
+                ci.cluster = ci.name;
+                ci.constr_abs_z = false;
+                make_cluster(ci, &ci, 0, 0);
+                ++packed[i + 1];
+            }
+        }
+        log_info("Packed MUX2_LUT8:%d, MUX2_LU7:%d, MUX2_LUT6:%d, MUX2_LUT5:%d\n", packed[0], packed[1], packed[2],
+                 packed[3]);
+    }
+
+    // ===================================
+    // ALU
+    // ===================================
+    // create ALU CIN block
+    std::unique_ptr<CellInfo> alu_add_cin_block(Context *ctx, CellInfo *head, NetInfo *cin_net)
+    {
+        std::string name = head->name.str(ctx) + "_HEAD_ALULC";
+        IdString name_id = ctx->id(name);
+
+        NetInfo *cout_net = ctx->createNet(name_id);
+        head->disconnectPort(id_CIN);
+        head->connectPort(id_CIN, cout_net);
+
+        auto cin_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
+        cin_ci->addOutput(id_COUT);
+        cin_ci->connectPort(id_COUT, cout_net);
+
+        if (cin_net->name == ctx->id("$PACKER_GND")) {
+            cin_ci->params[id_ALU_MODE] = std::string("C2L");
+            return cin_ci;
+        }
+        if (cin_net->name == ctx->id("$PACKER_VCC")) {
+            cin_ci->params[id_ALU_MODE] = std::string("ONE2C");
+            return cin_ci;
+        }
+        // CIN from logic
+        cin_ci->addInput(id_I1);
+        cin_ci->addInput(id_I3);
+        cin_ci->addInput(id_I2);
+        cin_ci->connectPort(id_I1, cin_net);
+        cin_ci->connectPort(id_I3, cin_net);
+        cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+        cin_ci->params[id_ALU_MODE] = std::string("0"); // ADD
+        return cin_ci;
+    }
+
+    // create ALU COUT block
+    std::unique_ptr<CellInfo> alu_add_cout_block(Context *ctx, CellInfo *tail, NetInfo *cout_net)
+    {
+        std::string name = tail->name.str(ctx) + "_TAIL_ALULC";
+        IdString name_id = ctx->id(name);
+
+        NetInfo *cin_net = ctx->createNet(name_id);
+        tail->disconnectPort(id_COUT);
+        tail->connectPort(id_COUT, cin_net);
+
+        auto cout_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
+        cout_ci->addOutput(id_COUT); // may be needed for the ALU filler
+        cout_ci->addInput(id_CIN);
+        cout_ci->connectPort(id_CIN, cin_net);
+        cout_ci->addOutput(id_SUM);
+        cout_ci->connectPort(id_SUM, cout_net);
+
+        cout_ci->params[id_ALU_MODE] = std::string("C2L");
+        return cout_ci;
+    }
+
+    // create ALU filler block
+    std::unique_ptr<CellInfo> alu_add_dummy_block(Context *ctx, CellInfo *tail)
+    {
+        std::string name = tail->name.str(ctx) + "_DUMMY_ALULC";
+        IdString name_id = ctx->id(name);
+
+        auto dummy_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
+        dummy_ci->params[id_ALU_MODE] = std::string("C2L");
+        return dummy_ci;
+    }
+
+    // create ALU chain
+    void pack_alus(void)
+    {
+        static CellTypePort cell_alu_cout = CellTypePort(id_ALU, id_COUT);
+        static CellTypePort cell_alu_cin = CellTypePort(id_ALU, id_CIN);
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        log_info("Pack ALUs...\n");
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            if (ci->cluster != ClusterId()) {
+                continue;
+            }
+            if (is_alu(ci)) {
+                // The ALU head is when the input carry is not a dedicated wire from the previous ALU
+                NetInfo *cin_net = ci->getPort(id_CIN);
+                if (!cin_net || !cin_net->driver.cell) {
+                    log_error("CIN disconnected at ALU:%s\n", ctx->nameOf(ci));
+                }
+                if (CellTypePort(cin_net->driver) != cell_alu_cout || cin_net->users.entries() > 1) {
+                    if (ctx->debug) {
+                        log_info("ALU head found %s. CIN net is %s\n", ctx->nameOf(ci), ctx->nameOf(cin_net));
+                    }
+                    // always prepend first ALU with carry generator block
+                    // three cases: CIN == 0, CIN == 1 and CIN == ?
+                    new_cells.push_back(std::move(alu_add_cin_block(ctx, ci, cin_net)));
+                    CellInfo *cin_block_ci = new_cells.back().get();
+                    // CIN block is the cluster root and is always placed in ALU0
+                    // This is a possible place for further optimization
+                    cin_block_ci->cluster = cin_block_ci->name;
+                    cin_block_ci->constr_z = BelZ::ALU0_Z;
+                    cin_block_ci->constr_abs_z = true;
+
+                    int alu_chain_len = 1;
+                    while (true) {
+                        // add to cluster
+                        if (ctx->debug) {
+                            log_info("Add ALU to the chain (len:%d): %s\n", alu_chain_len, ctx->nameOf(ci));
+                        }
+                        cin_block_ci->constr_children.push_back(ci);
+                        ci->cluster = cin_block_ci->name;
+                        ci->constr_abs_z = false;
+                        ci->constr_x = alu_chain_len / 6;
+                        ci->constr_y = 0;
+                        ci->constr_z = alu_chain_len % 6;
+                        // XXX I2 is pin C which must be set to 1 for all ALU modes except MUL
+                        // we use only mode 2 ADDSUB so create and connect this pin
+                        ci->addInput(id_I2);
+                        ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+
+                        ++alu_chain_len;
+
+                        // check for the chain end
+                        NetInfo *cout_net = ci->getPort(id_COUT);
+                        if (!cout_net || cout_net->users.empty()) {
+                            break;
+                        }
+                        if (CellTypePort(*cout_net->users.begin()) != cell_alu_cin || cout_net->users.entries() > 1) {
+                            new_cells.push_back(std::move(alu_add_cout_block(ctx, ci, cout_net)));
+                            CellInfo *cout_block_ci = new_cells.back().get();
+                            cin_block_ci->constr_children.push_back(cout_block_ci);
+                            cout_block_ci->cluster = cin_block_ci->name;
+                            cout_block_ci->constr_abs_z = false;
+                            cout_block_ci->constr_x = alu_chain_len / 6;
+                            cout_block_ci->constr_y = 0;
+                            cout_block_ci->constr_z = alu_chain_len % 6;
+                            if (ctx->debug) {
+                                log_info("Add ALU carry out to the chain (len:%d): %s\n", alu_chain_len,
+                                         ctx->nameOf(cout_block_ci));
+                            }
+
+                            ++alu_chain_len;
+
+                            break;
+                        }
+                        ci = (*cout_net->users.begin()).cell;
+                    }
+                    // ALUs are always paired
+                    if (alu_chain_len & 1) {
+                        // create dummy cell
+                        new_cells.push_back(std::move(alu_add_dummy_block(ctx, ci)));
+                        CellInfo *dummy_block_ci = new_cells.back().get();
+                        cin_block_ci->constr_children.push_back(dummy_block_ci);
+                        dummy_block_ci->cluster = cin_block_ci->name;
+                        dummy_block_ci->constr_abs_z = false;
+                        dummy_block_ci->constr_x = alu_chain_len / 6;
+                        dummy_block_ci->constr_y = 0;
+                        dummy_block_ci->constr_z = alu_chain_len % 6;
+                        if (ctx->debug) {
+                            log_info("Add ALU dummy cell to the chain (len:%d): %s\n", alu_chain_len,
+                                     ctx->nameOf(dummy_block_ci));
+                        }
+                    }
+                }
+            }
+        }
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+    }
+
+    // ===================================
+    // glue LUT and FF
+    // ===================================
+    void constrain_lutffs(void)
+    {
+        // Constrain directly connected LUTs and FFs together to use dedicated resources
+        auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
+        auto dff_ins = pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
+                                          {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
+                                          {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
+                                          {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
+                                          {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
+
+        int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
+        log_info("Constrained %d LUTFF pairs.\n", lutffs);
+
+        log_info("Pack ALUs...\n");
+        pack_alus();
+    }
+
+    void run(void)
+    {
+        pack_iobs();
+        handle_constants();
+        pack_wideluts();
+        pack_alus();
+        constrain_lutffs();
+    }
+};
+} // namespace
+
+void gowin_pack(Context *ctx)
+{
+    GowinPacker packer(ctx);
+    packer.run();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/pack.h b/himbaechel/uarch/gowin/pack.h
new file mode 100644
index 0000000000..7d86c0243e
--- /dev/null
+++ b/himbaechel/uarch/gowin/pack.h
@@ -0,0 +1,12 @@
+#ifndef GOWIN_PACK_H
+#define GOWIN_PACK_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void gowin_pack(Context *ctx);
+
+NEXTPNR_NAMESPACE_END
+
+#endif

From c4b3268e90b252ef4f0bff5e12cf958eda28dfa6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 6 Jul 2023 14:48:44 +1000
Subject: [PATCH 437/712] gowin: Himbaechel. Add the LUTRAM

    - RAM16SDP1, RAM16SDP2 and RAM16SDP4 support;
    - Reading in these primitives is asynchronous, but we have taken
      measures so that DFF Bels remain unoccupied and they can be used
      to implement synchronous reading.
    - misc fixes.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  2 +
 himbaechel/uarch/gowin/gowin.cc          | 28 ++++++--
 himbaechel/uarch/gowin/gowin.h           |  5 ++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 55 +++++++++++----
 himbaechel/uarch/gowin/pack.cc           | 87 +++++++++++++++++++++++-
 5 files changed, 157 insertions(+), 20 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 1b47db91ae..1dd3052cdb 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -873,6 +873,8 @@ X(DFFNCE)
 X(RAM16)
 X(RAMW)
 X(RAM16SDP4)
+X(RAM16SDP2)
+X(RAM16SDP1)
 X(WADA)
 X(WADB)
 X(WADC)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 9c691a8ece..14a5cc0d86 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -80,12 +80,15 @@ bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
         return true;
     }
     IdString bel_type = ctx->getBelType(bel);
-    if (bel_type.in(id_LUT4, id_DFF)) {
+    switch (bel_type.hash()) {
+    case ID_LUT4: /* fall-through */
+    case ID_DFF:
         return slice_valid(l.x, l.y, l.z / 2);
-    } else {
-        if (bel_type == id_ALU) {
-            return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
-        }
+    case ID_ALU:
+        return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
+    case ID_RAM16SDP4:
+        // only slices 4 and 5 are critical for RAM
+        return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
     }
     return true;
 }
@@ -102,6 +105,9 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
     if (type_is_dff(cell_type)) {
         return id_DFF;
     }
+    if (type_is_ssram(cell_type)) {
+        return id_RAM16SDP4;
+    }
     if (cell_type == id_GOWIN_GND) {
         return id_GND;
     }
@@ -123,6 +129,9 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
     if (bel_type == id_DFF) {
         return type_is_dff(cell_type);
     }
+    if (bel_type == id_RAM16SDP4) {
+        return type_is_ssram(cell_type);
+    }
     if (bel_type == id_GND) {
         return cell_type == id_GOWIN_GND;
     }
@@ -167,11 +176,20 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
     const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
     const CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z)));
+    const CellInfo *ramw =
+            (z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
 
     if (alu && lut) {
         return false;
     }
 
+    if (ramw) {
+        if (alu || ff || lut) {
+            return false;
+        }
+        return true;
+    }
+
     // check for ALU/LUT in the adjacent cell
     int adj_lut_z = (1 - (z & 1) * 2 + z) * 2;
     int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 9d2f736dc0..e831303810 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -20,6 +20,10 @@ inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
 // Return true if a cell is a ALU
 inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
 inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
+
+// Return true if a cell is a SSRAM
+inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
+inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
 } // namespace
 
 // Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
@@ -33,6 +37,7 @@ enum
     MUX23_Z = 22,
     MUX27_Z = 29,
     ALU0_Z = 30, // :35, 6 ALU
+    RAMW_Z = 36, // RAM16SDP4
 
     VCC_Z = 277,
     VSS_Z = 278
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index c3ec84aa23..86e6f21604 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -20,6 +20,7 @@
 MUX23_Z = 22
 MUX27_Z = 29
 ALU0_Z  = 30 # : 35, 6 ALUs
+RAMW_Z  = 36 # RAM16SDP4
 
 VCC_Z   = 277
 GND_Z   = 278
@@ -137,17 +138,17 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
-        return ttyp
+        return ttyp, None
     typename = "NULL"
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
     create_switch_matrix(tt, db, x, y)
-    return ttyp
+    return (ttyp, tt)
 
 # responsible nodes, there will be IO banks, configuration, etc.
 def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
-        return ttyp
+        return ttyp, None
     typename = "CORNER"
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
@@ -163,12 +164,12 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
 
     create_switch_matrix(tt, db, x, y)
-    return ttyp
+    return (ttyp, tt)
 
 # simple IO - only A and B
 def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
-        return ttyp
+        return ttyp, None
     typename = "IO"
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
@@ -184,12 +185,12 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
         tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
     create_switch_matrix(tt, db, x, y)
-    return ttyp
+    return (ttyp, tt)
 
 # logic: luts, dffs, alu etc
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
-        return ttyp
+        return ttyp, None
     typename = "LOGIC"
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
@@ -281,7 +282,30 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
 
     create_switch_matrix(tt, db, x, y)
-    return ttyp
+    return (ttyp, tt)
+
+def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp, None
+    # SSRAM is LUT based, so it's logic-like
+    ttyp, tt = create_logic_tiletype(chip, db, x, y, ttyp)
+
+    lut_inputs = ['A', 'B', 'C', 'D']
+    ff = tt.create_bel(f"RAM16SDP4", "RAM16SDP4", z = RAMW_Z)
+    for i in range(4):
+        tt.add_bel_pin(ff, f"DI[{i}]", f"{lut_inputs[i]}5", PinType.INPUT)
+        tt.add_bel_pin(ff, f"WAD[{i}]", f"{lut_inputs[i]}4", PinType.INPUT)
+        # RAD[0] is RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
+        # for now we connect it only to A0, the others will be connected
+        # directly during packing. RAD[1...3] - similarly.
+        tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
+        tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
+
+
+    tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
+    tt.add_bel_pin(ff, f"CE",  "CE2", PinType.INPUT)
+    tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
+    return (ttyp, tt)
 
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
@@ -305,28 +329,33 @@ def main():
     # The manufacturer distinguishes by externally identical tiles, so keep
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
-    logic_tiletypes = {12, 13, 14, 15, 16, 17}
+    logic_tiletypes = {12, 13, 14, 15, 16}
     io_tiletypes = {53, 55, 58, 59, 64, 65}
+    ssram_tiletypes = {17, 18, 19}
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
             ttyp = db.grid[y][x].ttyp
             if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
                 assert ttyp not in created_tiletypes, "Duplication of corner types"
-                ttyp = create_corner_tiletype(ch, db, x, y, ttyp)
+                ttyp, _ = create_corner_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"CORNER_{ttyp}")
                 continue
             if ttyp in logic_tiletypes:
-                ttyp = create_logic_tiletype(ch, db, x, y, ttyp)
+                ttyp, _ = create_logic_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
+            elif ttyp in ssram_tiletypes:
+                ttyp, _ = create_ssram_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
             elif ttyp in io_tiletypes:
-                ttyp = create_io_tiletype(ch, db, x, y, ttyp)
+                ttyp, _ = create_io_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"IO_{ttyp}")
             else:
-                ttyp = create_null_tiletype(ch, db, x, y, ttyp)
+                ttyp, _ = create_null_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"NULL_{ttyp}")
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 9989a4305e..7be4966df8 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -384,9 +384,91 @@ struct GowinPacker
 
         int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
         log_info("Constrained %d LUTFF pairs.\n", lutffs);
+    }
 
-        log_info("Pack ALUs...\n");
-        pack_alus();
+    // ===================================
+    // SSRAM cluster
+    // ===================================
+    // create ALU filler block
+    std::unique_ptr<CellInfo> ssram_make_lut(Context *ctx, CellInfo *ci, int index)
+    {
+        IdString name_id = ctx->idf("%s_LUT%d", ci->name.c_str(ctx), index);
+        auto lut_ci = std::make_unique<CellInfo>(ctx, name_id, id_LUT4);
+        if (index) {
+            for (IdString port : {id_I0, id_I1, id_I2, id_I3}) {
+                lut_ci->addInput(port);
+            }
+        }
+        IdString init_name = ctx->idf("INIT_%d", index);
+        if (ci->params.count(init_name)) {
+            lut_ci->params[id_INIT] = ci->params.at(init_name);
+        } else {
+            lut_ci->params[id_INIT] = std::string("1111111111111111");
+        }
+        return lut_ci;
+    }
+
+    void pack_ram16sdp4(void)
+    {
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        log_info("Pack RAMs...\n");
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            if (ci->cluster != ClusterId()) {
+                continue;
+            }
+
+            if (is_ssram(ci)) {
+                // make cluster root
+                ci->cluster = ci->name;
+                ci->constr_abs_z = true;
+                ci->constr_x = 0;
+                ci->constr_y = 0;
+                ci->constr_z = BelZ::RAMW_Z;
+
+                ci->addInput(id_CE);
+                ci->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC")].get());
+
+                // RAD networks
+                NetInfo *rad[4];
+                for (int i = 0; i < 4; ++i) {
+                    rad[i] = ci->getPort(ctx->idf("RAD[%d]", i));
+                }
+
+                // active LUTs
+                int luts_num = 4;
+                if (ci->type == id_RAM16SDP1) {
+                    luts_num = 1;
+                } else {
+                    if (ci->type == id_RAM16SDP2) {
+                        luts_num = 2;
+                    }
+                }
+
+                // make actual storage cells
+                for (int i = 0; i < 4; ++i) {
+                    new_cells.push_back(std::move(ssram_make_lut(ctx, ci, i)));
+                    CellInfo *lut_ci = new_cells.back().get();
+                    ci->constr_children.push_back(lut_ci);
+                    lut_ci->cluster = ci->name;
+                    lut_ci->constr_abs_z = true;
+                    lut_ci->constr_x = 0;
+                    lut_ci->constr_y = 0;
+                    lut_ci->constr_z = i * 2;
+                    // inputs
+                    // LUT0 is already connected when generating the base
+                    if (i && i < luts_num) {
+                        for (int j = 0; j < 4; ++j) {
+                            lut_ci->connectPort(ctx->idf("I%d", j), rad[j]);
+                        }
+                    }
+                }
+            }
+        }
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
     }
 
     void run(void)
@@ -396,6 +478,7 @@ struct GowinPacker
         pack_wideluts();
         pack_alus();
         constrain_lutffs();
+        pack_ram16sdp4();
     }
 };
 } // namespace

From 2930d8062703c811d507a32badd7961e63f2587a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 12 Jul 2023 11:25:28 +1000
Subject: [PATCH 438/712] gowin: Himbaechel. Add a clock router.

Shamelessly adapted gatecat's router.
Very early version, not yet puzzled with recognizing clock sources and
controlling the type of wires involved.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  16 ++
 himbaechel/uarch/gowin/globals.cc        | 186 +++++++++++++++++++++++
 himbaechel/uarch/gowin/globals.h         |  12 ++
 himbaechel/uarch/gowin/gowin.cc          |  53 +++++--
 himbaechel/uarch/gowin/gowin_arch_gen.py |  38 ++++-
 5 files changed, 281 insertions(+), 24 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/globals.cc
 create mode 100644 himbaechel/uarch/gowin/globals.h

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 1dd3052cdb..5d9a1ed3e4 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1060,3 +1060,19 @@ X(router)
 X(GOWIN_GND)
 X(GOWIN_VCC)
 
+// wire types
+X(GLOBAL_CLK)
+X(TILE_CLK)
+X(TILE_LSR)
+X(TILE_CE)
+X(IO_I)
+X(IO_O)
+X(LUT_INPUT)
+X(LUT_OUT)
+X(FF_INPUT)
+X(FF_OUT)
+X(MUX_OUT)
+X(MUX_SEL)
+X(ALU_CIN)
+X(ALU_COUT)
+
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
new file mode 100644
index 0000000000..52dd58badb
--- /dev/null
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -0,0 +1,186 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include <queue>
+
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+#include "himbaechel_helpers.h"
+
+#include "globals.h"
+#include "gowin.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct GowinGlobalRouter
+{
+    Context *ctx;
+
+    GowinGlobalRouter(Context *ctx) : ctx(ctx){};
+
+    // allow io->global, global->global and global->tile clock
+    bool global_pip_filter(PipId pip) const
+    {
+        /*
+        IdString src_type = ctx->getWireType(ctx->getPipSrcWire(pip));
+        IdString dst_type = ctx->getWireType(ctx->getPipDstWire(pip));
+        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O);
+        bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK);
+        return src_valid && dst_valid;
+        */
+        return true;
+    }
+
+    bool is_relaxed_sink(const PortRef &sink) const { return false; }
+
+    // Dedicated backwards BFS routing for global networks
+    template <typename Tfilt>
+    bool backwards_bfs_route(NetInfo *net, store_index<PortRef> user_idx, int iter_limit, bool strict, Tfilt pip_filter)
+    {
+        // Queue of wires to visit
+        std::queue<WireId> visit;
+        // Wire -> upstream pip
+        dict<WireId, PipId> backtrace;
+
+        // Lookup source and destination wires
+        WireId src = ctx->getNetinfoSourceWire(net);
+        WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(user_idx), 0);
+
+        if (src == WireId())
+            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
+                      ctx->nameOf(net->driver.port));
+
+        if (dst == WireId())
+            log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
+                      ctx->nameOf(net->users.at(user_idx).cell), ctx->nameOf(net->users.at(user_idx).port));
+
+        if (ctx->getBoundWireNet(src) != net)
+            ctx->bindWire(src, net, STRENGTH_LOCKED);
+
+        if (src == dst) {
+            // Nothing more to do
+            return true;
+        }
+
+        visit.push(dst);
+        backtrace[dst] = PipId();
+
+        int iter = 0;
+
+        while (!visit.empty() && (iter++ < iter_limit)) {
+            WireId cursor = visit.front();
+            visit.pop();
+            // Search uphill pips
+            for (PipId pip : ctx->getPipsUphill(cursor)) {
+                // Skip pip if unavailable, and not because it's already used for this net
+                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net)
+                    continue;
+                WireId prev = ctx->getPipSrcWire(pip);
+                // Ditto for the upstream wire
+                if (!ctx->checkWireAvail(prev) && ctx->getBoundWireNet(prev) != net)
+                    continue;
+                // Skip already visited wires
+                if (backtrace.count(prev))
+                    continue;
+                // Apply our custom pip filter
+                if (!pip_filter(pip))
+                    continue;
+                // Add to the queue
+                visit.push(prev);
+                backtrace[prev] = pip;
+                // Check if we are done yet
+                if (prev == src)
+                    goto done;
+            }
+            if (false) {
+            done:
+                break;
+            }
+        }
+
+        if (backtrace.count(src)) {
+            WireId cursor = src;
+            std::vector<PipId> pips;
+            // Create a list of pips on the routed path
+            while (true) {
+                PipId pip = backtrace.at(cursor);
+                if (pip == PipId())
+                    break;
+                pips.push_back(pip);
+                cursor = ctx->getPipDstWire(pip);
+            }
+            // Reverse that list
+            std::reverse(pips.begin(), pips.end());
+            // Bind pips until we hit already-bound routing
+            for (PipId pip : pips) {
+                WireId dst = ctx->getPipDstWire(pip);
+                if (ctx->getBoundWireNet(dst) == net)
+                    break;
+                ctx->bindPip(pip, net, STRENGTH_LOCKED);
+            }
+            return true;
+        } else {
+            if (strict)
+                log_error("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
+                          ctx->nameOfWire(src), ctx->nameOfWire(dst));
+            return false;
+        }
+    }
+
+    void route_clk_net(NetInfo *net)
+    {
+        for (auto usr : net->users.enumerate())
+            backwards_bfs_route(net, usr.index, 1000000, true,
+                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
+        log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+    }
+
+    bool driver_is_clksrc(const PortRef &driver)
+    {
+        // XXX dedicated pins
+        return driver.port == id_O;
+    }
+
+    void run(void)
+    {
+        log_info("Routing globals...\n");
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            CellInfo *drv = ni->driver.cell;
+            if (drv == nullptr)
+                continue;
+            if (driver_is_clksrc(ni->driver)) {
+                route_clk_net(ni);
+                continue;
+            }
+        }
+    }
+};
+
+void gowin_route_globals(Context *ctx)
+{
+    GowinGlobalRouter router(ctx);
+    router.run();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/globals.h b/himbaechel/uarch/gowin/globals.h
new file mode 100644
index 0000000000..77e82769ee
--- /dev/null
+++ b/himbaechel/uarch/gowin/globals.h
@@ -0,0 +1,12 @@
+#ifndef GOWIN_GLOBALS_H
+#define GOWIN_GLOBALS_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void gowin_route_globals(Context *ctx);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 14a5cc0d86..082c098003 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -7,6 +7,7 @@
 #define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
 #include "himbaechel_constids.h"
 
+#include "globals.h"
 #include "gowin.h"
 #include "pack.h"
 
@@ -20,9 +21,10 @@ struct GowinImpl : HimbaechelAPI
     void init_constids(Arch *arch) override { init_uarch_constids(arch); }
     void init(Context *ctx) override;
 
+    void pack() override;
     void prePlace() override;
     void postPlace() override;
-    void pack() override;
+    void preRoute() override;
 
     bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
 
@@ -34,6 +36,9 @@ struct GowinImpl : HimbaechelAPI
   private:
     HimbaechelHelpers h;
 
+    IdString chip;
+    IdString partno;
+
     // Validity checking
     struct GowinCellInfo
     {
@@ -61,17 +66,44 @@ void GowinImpl::init(Context *ctx)
 {
     h.init(ctx);
     HimbaechelAPI::init(ctx);
+
+    const ArchArgs &args = ctx->getArchArgs();
     // These fields go in the header of the output JSON file and can help
     // gowin_pack support different architectures
     ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
-    // XXX it would be nice to write chip/base name in the header as well,
-    // but maybe that will come up when there is clarity with
-    // Arch::archArgsToId
+    ctx->settings[ctx->id("packer.chipdb")] = args.chipdb;
+
+    if (!args.options.count("partno")) {
+        log_error("Partnumber (like --vopt partno=GW1NR-LV9QN88PC6/I5) must be specified.\n");
+    }
+    ctx->settings[ctx->id("packer.partno")] = args.options.at("partno");
+
+    // GW1N-9C.xxx -> GW1N-9C
+    std::string chipdb = args.chipdb;
+    auto dot_pos = chipdb.find(".");
+    if (dot_pos != std::string::npos) {
+        chipdb.resize(dot_pos);
+    }
+    chip = ctx->id(chipdb);
+    partno = ctx->id(args.options.at("partno"));
 }
 
+void GowinImpl::pack() { gowin_pack(ctx); }
 void GowinImpl::prePlace() { assign_cell_info(); }
+void GowinImpl::postPlace()
+{
+    if (ctx->debug) {
+        log_info("================== Final Placement ===================\n");
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            IdStringList bel = ctx->getBelName(ci->bel);
+            log_info("%s -> %s\n", ctx->nameOf(ci), bel.str(ctx).c_str());
+        }
+        log_info("======================================================\n");
+    }
+}
 
-void GowinImpl::pack() { gowin_pack(ctx); }
+void GowinImpl::preRoute() { gowin_route_globals(ctx); }
 
 bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
@@ -253,17 +285,6 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     return true;
 }
 
-void GowinImpl::postPlace()
-{
-    if (ctx->debug) {
-        log_info("================== Final Placement ===================\n");
-        for (auto &cell : ctx->cells) {
-            auto ci = cell.second.get();
-            IdStringList bel = ctx->getBelName(ci->bel);
-            log_info("%s -> %s\n", ctx->nameOf(ci), bel.str(ctx).c_str());
-        }
-    }
-}
 } // namespace
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 86e6f21604..2c63190860 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -70,7 +70,8 @@ def create_nodes(chip: Chip, db: chipdb):
     for y in range(Y):
         for x in range(X):
             nodes = []
-            extra_tile_data = chip.tile_type_at(x, y).extra_data
+            tt = chip.tile_type_at(x, y)
+            extra_tile_data = tt.extra_data
             # SN and EW
             for i in [1, 2]:
                 nodes.append([NodeWire(x, y, f'SN{i}0'),
@@ -118,22 +119,43 @@ def create_nodes(chip: Chip, db: chipdb):
             global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
             global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
 
-    for node in global_nodes.values():
+    # add nodes from the apicula db
+    for node_name, node in db.nodes.items():
+        for y, x, wire in node:
+            new_node = NodeWire(x, y, wire)
+            gl_nodes = global_nodes.setdefault(node_name, [])
+            if new_node not in gl_nodes:
+                gl_nodes.append(NodeWire(x, y, wire))
+
+    for name, node in global_nodes.items():
         chip.add_node(node)
 
+
 # About X and Y as parameters - in some cases, the type of manufacturer's tile
 # is not different, but some wires are not physically present, that is, routing
 # depends on the location of otherwise identical tiles. There are many options
 # for taking this into account, but for now we make a distinction here, by
 # coordinates.
 def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
-    pips = db.grid[y][x].pips
-    for dst, srcs in pips.items():
+    def get_wire_type(name):
+        if name.startswith('GB') or name.startswith('GT'):
+            return "GLOBAL_CLK"
+        return ""
+
+    for dst, srcs in db.grid[y][x].pips.items():
+        if not tt.has_wire(dst):
+            tt.create_wire(dst, get_wire_type(dst))
+        for src in srcs.keys():
+            if not tt.has_wire(src):
+                tt.create_wire(src, get_wire_type(dst))
+            tt.create_pip(src, dst)
+    # clock wires
+    for dst, srcs in db.grid[y][x].clock_pips.items():
         if not tt.has_wire(dst):
-            tt.create_wire(dst)
+            tt.create_wire(dst, "GLOBAL_CLK")
         for src in srcs.keys():
             if not tt.has_wire(src):
-                tt.create_wire(src)
+                tt.create_wire(src, "GLOBAL_CLK")
             tt.create_pip(src, dst)
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
@@ -179,7 +201,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         # wires
         portmap = db.grid[y][x].bels[name].portmap
         tt.create_wire(portmap['I'], "IO_I")
-        tt.create_wire(portmap['O'], "IO_I")
+        tt.create_wire(portmap['O'], "IO_O")
         # bels
         io = tt.create_bel(name, "IOB", z = i)
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
@@ -330,7 +352,7 @@ def main():
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
     logic_tiletypes = {12, 13, 14, 15, 16}
-    io_tiletypes = {53, 55, 58, 59, 64, 65}
+    io_tiletypes = {53, 55, 58, 59, 64, 65, 66}
     ssram_tiletypes = {17, 18, 19}
     # Setup tile grid
     for x in range(X):

From 3d3039e25c2981a0d16e8cff079315da57c637c8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 12 Jul 2023 19:36:03 +1000
Subject: [PATCH 439/712] gowin: Himbaechel. Add bundle data generation.

The pin data is only being populated so far, but not used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/himbaechel_dbgen/chip.py      | 61 ++++++++++++++++++++++--
 himbaechel/uarch/gowin/gowin_arch_gen.py | 39 +++++++++++++++
 2 files changed, 97 insertions(+), 3 deletions(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index c3e4a8ae0d..4f16b831d6 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -371,6 +371,56 @@ def serialise(self, context: str, bba: BBAWriter):
             bba.ref(f"{context}_extra_data")
         else:
             bba.u32(0)
+
+@dataclass
+class PadInfo(BBAStruct):
+    # package pin name
+    package_pin: IdString
+    # reference to corresponding bel
+    tile: IdString
+    bel: IdString
+    # function name
+    pad_function: IdString
+    # index of pin bank
+    pad_bank: int
+    # extra pad flags
+    flags: int
+    extra_data: object = None
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.package_pin.index)
+        bba.u32(self.tile.index)
+        bba.u32(self.bel.index)
+        bba.u32(self.pad_function.index)
+        bba.u32(self.pad_bank)
+        bba.u32(self.flags)
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
+
+@dataclass
+class PackageInfo(BBAStruct):
+    strs: StringPool
+    name: IdString
+    pads: list[int] = field(default_factory=list)
+
+    def create_pad(self, package_pin: str, tile: str, bel: str, pad_function: str, pad_bank: int, flags: int = 0):
+        pad = PadInfo(package_pin = self.strs.id(package_pin), tile = self.strs.id(tile), bel = self.strs.id(bel),
+                pad_function = self.strs.id(pad_function), pad_bank = pad_bank, flags = flags)
+        self.pads.append(pad)
+        return pad
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        for i, pad in enumerate(self.pad):
+            bel.serialise_lists(f"{context}_pad{i}", pad)
+
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.slice(f"{context}_pads", len(self.pads))
+
 class Chip:
     def __init__(self, uarch: str, name: str, width: int, height: int):
         self.strs = StringPool()
@@ -385,6 +435,7 @@ def __init__(self, uarch: str, name: str, width: int, height: int):
         self.node_shape_idx = dict()
         self.tile_shapes = []
         self.tile_shapes_idx = dict()
+        self.packages = []
         self.extra_data = None
     def create_tile_type(self, name: str):
         tt = TileType(self.strs, self.strs.id(name))
@@ -449,6 +500,11 @@ def flatten_tile_shapes(self):
                     self.tile_shapes_idx[key] = tile.shape_idx
         print(f"{len(self.tile_shapes)} unique tile routing shapes")
 
+    def create_package(self, name: str):
+        pkg = PackageInfo(self.strs, self.strs.id(name))
+        self.packages.append(pkg)
+        return pkg
+
     def serialise(self, bba: BBAWriter):
         self.flatten_tile_shapes()
         # TODO: preface, etc
@@ -496,9 +552,8 @@ def serialise(self, bba: BBAWriter):
         bba.slice("tile_insts", self.width*self.height)
         bba.slice("node_shapes", len(self.node_shapes))
         bba.slice("tile_shapes", len(self.tile_shapes))
-        # packages: not yet used
-        bba.u32(0)
-        bba.u32(0)
+        # packages
+        bba.slice("packages", len(self.packages))
         # speed grades: not yet used
         bba.u32(0)
         bba.u32(0)
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 2c63190860..191268ce6b 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -329,6 +329,42 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
     return (ttyp, tt)
 
+_tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
+def create_packages(chip: Chip, db: chipdb):
+    def ioloc_to_tile_bel(ioloc):
+        side, num, bel_idx = _tbrlre.match(ioloc).groups()
+        if side == 'T':
+            row = 0
+            col = int(num) - 1
+        elif side == 'B':
+            row = db.rows - 1
+            col = int(num) - 1
+        elif side == 'L':
+            row = int(num) - 1
+            col = 0
+        elif side == 'R':
+            row = int(num) - 1
+            col = db.cols - 1
+        return (f'X{col}Y{row}', f'IOB{bel_idx}')
+
+    created_pkgs = set()
+    for partno_spd, partdata in db.packages.items():
+        pkgname, variant, spd = partdata
+        partno = partno_spd.removesuffix(spd) # drop SPEED like 'C7/I6'
+        if partno in created_pkgs:
+            continue
+        pkg = chip.create_package(partno)
+        print(partno)
+        for pinno, pininfo in db.pinout[variant][pkgname].items():
+            io_loc, cfgs = pininfo
+            tile, bel = ioloc_to_tile_bel(io_loc)
+            pad_func = ""
+            for cfg in cfgs:
+                pad_func += cfg + "/"
+            pad_func = pad_func.rstrip('/')
+            bank = int(db.pin_bank[io_loc])
+            pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
+
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
     parser.add_argument('-d', '--device', required=True)
@@ -348,6 +384,9 @@ def main():
     # Init constant ids
     ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
 
+    # packages from parntnumbers
+    create_packages(ch, db)
+
     # The manufacturer distinguishes by externally identical tiles, so keep
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).

From 6cac19c055600ad4827d12d8fba1e441b06851e8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 14 Jul 2023 18:57:20 +1000
Subject: [PATCH 440/712] gowin: Himbaechel. Add constraint file processing.

- minor fixes for pinout saving;
- CST parser taken from generic-based apicula;
- $nextpnr IOB detachment is copied here because it is necessary to copy
  attributes from deleted bels.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/himbaechel_dbgen/chip.py      |  17 +-
 himbaechel/uarch/gowin/cst.cc            | 191 +++++++++++++++++++++++
 himbaechel/uarch/gowin/cst.h             |  13 ++
 himbaechel/uarch/gowin/gowin.cc          |  61 +++++++-
 himbaechel/uarch/gowin/gowin_arch_gen.py |   4 +-
 himbaechel/uarch/gowin/pack.cc           |  32 +++-
 6 files changed, 307 insertions(+), 11 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/cst.cc
 create mode 100644 himbaechel/uarch/gowin/cst.h

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 4f16b831d6..857935df01 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -388,7 +388,10 @@ class PadInfo(BBAStruct):
     extra_data: object = None
 
     def serialise_lists(self, context: str, bba: BBAWriter):
-        pass
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.package_pin.index)
         bba.u32(self.tile.index)
@@ -414,8 +417,11 @@ def create_pad(self, package_pin: str, tile: str, bel: str, pad_function: str, p
         return pad
 
     def serialise_lists(self, context: str, bba: BBAWriter):
-        for i, pad in enumerate(self.pad):
-            bel.serialise_lists(f"{context}_pad{i}", pad)
+        for i, pad in enumerate(self.pads):
+            pad.serialise_lists(f"{context}_pad{i}", bba)
+        bba.label(f"{context}_pads")
+        for i, pad in enumerate(self.pads):
+            pad.serialise(f"{context}_pad{i}", bba)
 
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
@@ -515,6 +521,8 @@ def serialise(self, bba: BBAWriter):
             shp.serialise_lists(f"nshp{i}", bba)
         for i, tsh in enumerate(self.tile_shapes):
             tsh.serialise_lists(f"tshp{i}", bba)
+        for i, pkg in enumerate(self.packages):
+            pkg.serialise_lists(f"pkg{i}", bba)
         for y, row in enumerate(self.tiles):
             for x, tinst in enumerate(row):
                 tinst.serialise_lists(f"tinst_{x}_{y}", bba)
@@ -530,6 +538,9 @@ def serialise(self, bba: BBAWriter):
         bba.label(f"tile_shapes")
         for i, tsh in enumerate(self.tile_shapes):
             tsh.serialise(f"tshp{i}", bba)
+        bba.label(f"packages")
+        for i, pkg in enumerate(self.packages):
+            pkg.serialise(f"pkg{i}", bba)
         bba.label(f"tile_insts")
         for y, row in enumerate(self.tiles):
             for x, tinst in enumerate(row):
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
new file mode 100644
index 0000000000..5b9ddaaacc
--- /dev/null
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -0,0 +1,191 @@
+#include <boost/algorithm/string.hpp>
+#include <regex>
+#include <utility>
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+#include "himbaechel_helpers.h"
+
+#include "cst.h"
+#include "gowin.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct GowinCstReader
+{
+    Context *ctx;
+    std::istream &in;
+
+    GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in){};
+
+    const PadInfoPOD *pinLookup(const PadInfoPOD *list, const size_t len, const IdString idx)
+    {
+        for (size_t i = 0; i < len; i++) {
+            const PadInfoPOD *pin = &list[i];
+            if (IdString(pin->package_pin) == idx) {
+                return pin;
+            }
+        }
+        return nullptr;
+    }
+
+    Loc getLoc(std::smatch match, int maxX, int maxY)
+    {
+        int col = std::stoi(match[2]);
+        int row = 1; // Top
+        std::string side = match[1].str();
+        if (side == "R") {
+            row = col;
+            col = maxX;
+        } else if (side == "B") {
+            row = maxY;
+        } else if (side == "L") {
+            row = col;
+            col = 1;
+        }
+        int z = match[3].str()[0] - 'A';
+        return Loc(col - 1, row - 1, z);
+    }
+
+    bool run(void)
+    {
+        pool<std::pair<IdString, IdStringList>> constrained_cells;
+        auto debug_cell = [this, &constrained_cells](IdString cellId, IdStringList belId) {
+            if (ctx->debug) {
+                constrained_cells.insert(std::make_pair(cellId, belId));
+            }
+        };
+
+        log_info("Reading constraints...\n");
+        try {
+            // If two locations are specified separated by commas (for differential I/O buffers),
+            // only the first location is actually recognized and used.
+            // And pin A will be Positive and pin B will be Negative in any case.
+            std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ,;]+)(, *[^ ;]+)? *;.*[\\s\\S]*");
+            std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*[\\s\\S]*");
+            std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
+            std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
+            std::regex inslocre =
+                    std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
+            std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*[\\s\\S]*");
+            std::smatch match, match_attr, match_pinloc;
+            std::string line, pinline;
+            enum
+            {
+                ioloc,
+                ioport,
+                insloc,
+                clock
+            } cst_type;
+
+            while (!in.eof()) {
+                std::getline(in, line);
+                cst_type = ioloc;
+                if (!std::regex_match(line, match, iobre)) {
+                    if (std::regex_match(line, match, portre)) {
+                        cst_type = ioport;
+                    } else {
+                        if (std::regex_match(line, match, clockre)) {
+                            cst_type = clock;
+                        } else {
+                            if (std::regex_match(line, match, inslocre)) {
+                                cst_type = insloc;
+                            } else {
+                                if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
+                                    log_warning("Invalid constraint: %s\n", line.c_str());
+                                }
+                                continue;
+                            }
+                        }
+                    }
+                }
+
+                IdString net = ctx->id(match[1]);
+                auto it = ctx->cells.find(net);
+                if (cst_type != clock && it == ctx->cells.end()) {
+                    log_info("Cell %s not found\n", net.c_str(ctx));
+                    continue;
+                }
+                switch (cst_type) {
+                case clock: { // CLOCK name BUFG|S=#
+                    std::string which_clock = match[2];
+                    std::string lw = match[4];
+                    int lw_idx = -1;
+                    if (lw.length() > 0) {
+                        lw_idx = atoi(lw.c_str());
+                        log_info("lw_idx:%d\n", lw_idx);
+                    }
+                    if (which_clock.at(0) == 'S') {
+                        auto ni = ctx->nets.find(net);
+                        if (ni == ctx->nets.end()) {
+                            log_info("Net %s not found\n", net.c_str(ctx));
+                            continue;
+                        }
+                        // if (!allocate_longwire(ni->second.get(), lw_idx)) {
+                        log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(ctx));
+                        //}
+                    } else {
+                        log_info("BUFG isn't supported\n");
+                        continue;
+                    }
+                } break;
+                case ioloc: { // IO_LOC name pin
+                    IdString pinname = ctx->id(match[2]);
+                    pinline = match[2];
+
+                    const PadInfoPOD *belname =
+                            pinLookup(ctx->package_info->pads.get(), ctx->package_info->pads.ssize(), pinname);
+                    if (belname != nullptr) {
+                        IdStringList bel = IdStringList::concat(IdString(belname->tile), IdString(belname->bel));
+                        it->second->setAttr(IdString(ID_BEL), bel.str(ctx));
+                        debug_cell(it->second->name, bel);
+                    } else {
+                        if (std::regex_match(pinline, match_pinloc, iobelre)) {
+                            // may be it's IOx#[AB] style?
+                            Loc loc = getLoc(match_pinloc, ctx->getGridDimX(), ctx->getGridDimY());
+                            BelId bel = ctx->getBelByLocation(loc);
+                            if (bel == BelId()) {
+                                log_error("Pin %s not found (TRBL style). \n", pinline.c_str());
+                            }
+                            it->second->setAttr(IdString(ID_BEL), std::string(ctx->nameOfBel(bel)));
+                            debug_cell(it->second->name, ctx->getBelName(bel));
+                        } else {
+                            log_error("Pin %s not found (pin# style)\n", pinname.c_str(ctx));
+                        }
+                    }
+                } break;
+                default: { // IO_PORT attr=value
+                    std::string attr_val = match[2];
+                    while (std::regex_match(attr_val, match_attr, port_attrre)) {
+                        std::string attr = "&";
+                        attr += match_attr[1];
+                        boost::algorithm::to_upper(attr);
+                        it->second->setAttr(ctx->id(attr), 1);
+                        attr_val = match_attr[2];
+                    }
+                }
+                }
+            }
+            if (ctx->debug) {
+                for (auto &cell : constrained_cells) {
+                    log_info("Cell %s is constrained to %s\n", cell.first.c_str(ctx), cell.second.str(ctx).c_str());
+                }
+            }
+            return true;
+        } catch (log_execution_error_exception) {
+            return false;
+        }
+    }
+};
+
+bool gowin_apply_constraints(Context *ctx, std::istream &in)
+{
+    GowinCstReader reader(ctx, in);
+    return reader.run();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/cst.h b/himbaechel/uarch/gowin/cst.h
new file mode 100644
index 0000000000..255e57b035
--- /dev/null
+++ b/himbaechel/uarch/gowin/cst.h
@@ -0,0 +1,13 @@
+#ifndef GOWIN_CST_H
+#define GOWIN_CST_H
+
+#include <fstream>
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool gowin_apply_constraints(Context *ctx, std::istream &in);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 082c098003..416ccae2d0 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -1,3 +1,5 @@
+#include <regex>
+
 #include "himbaechel_api.h"
 #include "himbaechel_helpers.h"
 #include "log.h"
@@ -7,6 +9,7 @@
 #define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
 #include "himbaechel_constids.h"
 
+#include "cst.h"
 #include "globals.h"
 #include "gowin.h"
 #include "pack.h"
@@ -76,8 +79,6 @@ void GowinImpl::init(Context *ctx)
     if (!args.options.count("partno")) {
         log_error("Partnumber (like --vopt partno=GW1NR-LV9QN88PC6/I5) must be specified.\n");
     }
-    ctx->settings[ctx->id("packer.partno")] = args.options.at("partno");
-
     // GW1N-9C.xxx -> GW1N-9C
     std::string chipdb = args.chipdb;
     auto dot_pos = chipdb.find(".");
@@ -85,10 +86,60 @@ void GowinImpl::init(Context *ctx)
         chipdb.resize(dot_pos);
     }
     chip = ctx->id(chipdb);
-    partno = ctx->id(args.options.at("partno"));
+    std::string pn = args.options.at("partno");
+    partno = ctx->id(pn);
+    ctx->settings[ctx->id("packer.partno")] = pn;
+
+    std::regex speedre = std::regex("(.*)(C[0-9]/I[0-9])$");
+    std::smatch match;
+
+    IdString spd;
+    IdString package_idx;
+    if (std::regex_match(pn, match, speedre)) {
+        package_idx = ctx->id(match[1]);
+        spd = ctx->id(match[2]);
+    } else {
+        if (pn.length() > 2 && pn.compare(pn.length() - 2, 2, "ES")) {
+            package_idx = ctx->id(pn.substr(pn.length() - 2));
+            spd = ctx->id("ES");
+        }
+    }
+
+    if (ctx->debug) {
+        log_info("packages:%d\n", ctx->chip_info->packages.ssize());
+    }
+    for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
+        if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
+            if (ctx->debug) {
+                log_info("i:%d %s\n", i, package_idx.c_str(ctx));
+            }
+            ctx->package_info = &ctx->chip_info->packages[i];
+            break;
+        }
+    }
+    if (ctx->package_info == nullptr) {
+        log_error("No package for partnumber %s\n", partno.c_str(ctx));
+    }
+
+    if (args.options.count("cst")) {
+        ctx->settings[ctx->id("cst.filename")] = args.options.at("cst");
+    }
 }
 
-void GowinImpl::pack() { gowin_pack(ctx); }
+void GowinImpl::pack()
+{
+    if (ctx->settings.count(ctx->id("cst.filename"))) {
+        std::string filename = ctx->settings[ctx->id("cst.filename")].as_string();
+        std::ifstream in(filename);
+        if (!in) {
+            log_error("failed to open CST file '%s'\n", filename.c_str());
+        }
+        if (!gowin_apply_constraints(ctx, in)) {
+            log_error("failed to parse CST file '%s'\n", filename.c_str());
+        }
+    }
+    gowin_pack(ctx);
+}
 void GowinImpl::prePlace() { assign_cell_info(); }
 void GowinImpl::postPlace()
 {
@@ -99,7 +150,7 @@ void GowinImpl::postPlace()
             IdStringList bel = ctx->getBelName(ci->bel);
             log_info("%s -> %s\n", ctx->nameOf(ci), bel.str(ctx).c_str());
         }
-        log_info("======================================================\n");
+        log_break();
     }
 }
 
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 191268ce6b..3fe8137c43 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -353,8 +353,8 @@ def ioloc_to_tile_bel(ioloc):
         partno = partno_spd.removesuffix(spd) # drop SPEED like 'C7/I6'
         if partno in created_pkgs:
             continue
+        created_pkgs.add(partno)
         pkg = chip.create_package(partno)
-        print(partno)
         for pinno, pininfo in db.pinout[variant][pkgname].items():
             io_loc, cfgs = pininfo
             tile, bel = ioloc_to_tile_bel(io_loc)
@@ -391,7 +391,7 @@ def main():
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
     logic_tiletypes = {12, 13, 14, 15, 16}
-    io_tiletypes = {53, 55, 58, 59, 64, 65, 66}
+    io_tiletypes = {52, 53, 55, 58, 59, 64, 65, 66}
     ssram_tiletypes = {17, 18, 19}
     # Setup tile grid
     for x in range(X):
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 7be4966df8..06bc4290bb 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -29,7 +29,37 @@ struct GowinPacker
                 CellTypePort(id_IBUF, id_I),
                 CellTypePort(id_OBUF, id_O),
         };
-        h.remove_nextpnr_iobs(top_ports);
+        std::vector<IdString> to_remove;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
+                continue;
+            NetInfo *i = ci.getPort(ctx->id("I"));
+            if (i && i->driver.cell) {
+                if (!top_ports.count(CellTypePort(i->driver)))
+                    log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
+                              ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+                for (const auto &attr : ci.attrs) {
+                    i->driver.cell->attrs[attr.first] = attr.second;
+                }
+            }
+            NetInfo *o = ci.getPort(ctx->id("O"));
+            if (o) {
+                for (auto &usr : o->users) {
+                    if (!top_ports.count(CellTypePort(usr)))
+                        log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
+                                  ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
+                    for (const auto &attr : ci.attrs) {
+                        usr.cell->attrs[attr.first] = attr.second;
+                    }
+                }
+            }
+            ci.disconnectPort(ctx->id("I"));
+            ci.disconnectPort(ctx->id("O"));
+            to_remove.push_back(ci.name);
+        }
+        for (IdString cell_name : to_remove)
+            ctx->cells.erase(cell_name);
     }
 
     // ===================================

From b2ec06dfe842d52d7b879a1d32e65f8471825163 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 19 Jul 2023 13:29:18 +1000
Subject: [PATCH 441/712] gowin: Himbaechel. Implement the GSR primitive

On GW2A chips, the global set/reset is in its own cell.
Also corrections to ALU generation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  8 +++++
 himbaechel/uarch/gowin/gowin.cc          |  4 ++-
 himbaechel/uarch/gowin/gowin_arch_gen.py | 26 ++++++++++++++-
 himbaechel/uarch/gowin/pack.cc           | 41 ++++++++++++++++++++++++
 4 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 5d9a1ed3e4..e646f91b4f 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1076,3 +1076,11 @@ X(MUX_SEL)
 X(ALU_CIN)
 X(ALU_COUT)
 
+// fake dff inputs
+X(XD0)
+X(XD1)
+X(XD2)
+X(XD3)
+X(XD4)
+X(XD5)
+
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 416ccae2d0..5fe2a004f5 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -90,6 +90,7 @@ void GowinImpl::init(Context *ctx)
     partno = ctx->id(pn);
     ctx->settings[ctx->id("packer.partno")] = pn;
 
+    // package and speed class
     std::regex speedre = std::regex("(.*)(C[0-9]/I[0-9])$");
     std::smatch match;
 
@@ -106,7 +107,7 @@ void GowinImpl::init(Context *ctx)
     }
 
     if (ctx->debug) {
-        log_info("packages:%d\n", ctx->chip_info->packages.ssize());
+        log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
     }
     for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
         if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
@@ -121,6 +122,7 @@ void GowinImpl::init(Context *ctx)
         log_error("No package for partnumber %s\n", partno.c_str(ctx));
     }
 
+    // constraints
     if (args.options.count("cst")) {
         ctx->settings[ctx->id("cst.filename")] = args.options.at("cst");
     }
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 3fe8137c43..8a93588775 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -22,6 +22,7 @@
 ALU0_Z  = 30 # : 35, 6 ALUs
 RAMW_Z  = 36 # RAM16SDP4
 
+GSR_Z   = 276
 VCC_Z   = 277
 GND_Z   = 278
 
@@ -140,6 +141,8 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     def get_wire_type(name):
         if name.startswith('GB') or name.startswith('GT'):
             return "GLOBAL_CLK"
+        elif name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
+            return "X0"
         return ""
 
     for dst, srcs in db.grid[y][x].pips.items():
@@ -188,6 +191,22 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     create_switch_matrix(tt, db, x, y)
     return (ttyp, tt)
 
+# Global set/reset. GW2A series has special cell for it
+def create_gsr_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp, None
+    typename = "GSR"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
+    portmap = db.grid[y][x].bels['GSR'].portmap
+    tt.create_wire(portmap['GSRI'], "GSRI")
+    io = tt.create_bel("GSR", "GSR", z = GSR_Z)
+    tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
+
+    create_switch_matrix(tt, db, x, y)
+    return (ttyp, tt)
+
 # simple IO - only A and B
 def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     if ttyp in created_tiletypes:
@@ -393,6 +412,7 @@ def main():
     logic_tiletypes = {12, 13, 14, 15, 16}
     io_tiletypes = {52, 53, 55, 58, 59, 64, 65, 66}
     ssram_tiletypes = {17, 18, 19}
+    gsr_tiletypes = {1}
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
@@ -403,7 +423,11 @@ def main():
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"CORNER_{ttyp}")
                 continue
-            if ttyp in logic_tiletypes:
+            if ttyp in gsr_tiletypes:
+                ttyp, _ = create_gsr_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"GSR_{ttyp}")
+            elif ttyp in logic_tiletypes:
                 ttyp, _ = create_logic_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 06bc4290bb..07c84e2966 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -249,10 +249,14 @@ struct GowinPacker
 
         if (cin_net->name == ctx->id("$PACKER_GND")) {
             cin_ci->params[id_ALU_MODE] = std::string("C2L");
+            cin_ci->addInput(id_I2);
+            cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
             return cin_ci;
         }
         if (cin_net->name == ctx->id("$PACKER_VCC")) {
             cin_ci->params[id_ALU_MODE] = std::string("ONE2C");
+            cin_ci->addInput(id_I2);
+            cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
             return cin_ci;
         }
         // CIN from logic
@@ -501,10 +505,47 @@ struct GowinPacker
         }
     }
 
+    // Pack global set-reset
+    void pack_gsr(void)
+    {
+        log_info("Packing GSR..\n");
+
+        bool user_gsr = false;
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ctx->verbose)
+                log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
+            if (ci->type == id_GSR) {
+                user_gsr = true;
+                break;
+            }
+        }
+        if (!user_gsr) {
+            bool have_gsr_bel = false;
+            auto bels = ctx->getBels();
+            for (auto bid : bels) {
+                if (ctx->getBelType(bid) == id_GSR) {
+                    have_gsr_bel = true;
+                    break;
+                }
+            }
+            if (have_gsr_bel) {
+                // make default GSR
+                auto gsr_cell = std::make_unique<CellInfo>(ctx, id_GSR, id_GSR);
+                gsr_cell->addInput(id_GSRI);
+                gsr_cell->connectPort(id_GSRI, ctx->nets[ctx->id("$PACKER_VCC")].get());
+                ctx->cells[gsr_cell->name] = std::move(gsr_cell);
+            } else {
+                log_info("No GSR in the chip base\n");
+            }
+        }
+    }
+
     void run(void)
     {
         pack_iobs();
         handle_constants();
+        pack_gsr();
         pack_wideluts();
         pack_alus();
         constrain_lutffs();

From 6eeac1cabf5b98d9bbd74c6e7022390a84af7fb3 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 20 Jul 2023 12:09:14 +1000
Subject: [PATCH 442/712] gowin: Himbaechel. Use pin functions info

Use information about pin functions in the clock router.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc        | 18 ++++++++++++++---
 himbaechel/uarch/gowin/gowin.cc          |  4 ++++
 himbaechel/uarch/gowin/gowin_arch_gen.py |  1 +
 himbaechel/uarch/gowin/gowin_utils.cc    | 25 ++++++++++++++++++++++++
 himbaechel/uarch/gowin/gowin_utils.h     | 24 +++++++++++++++++++++++
 himbaechel/uarch/gowin/pack.cc           | 16 +++++++--------
 6 files changed, 77 insertions(+), 11 deletions(-)
 create mode 100644 himbaechel/uarch/gowin/gowin_utils.cc
 create mode 100644 himbaechel/uarch/gowin/gowin_utils.h

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 52dd58badb..bb2e2b0804 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -29,14 +29,16 @@
 
 #include "globals.h"
 #include "gowin.h"
+#include "gowin_utils.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
 struct GowinGlobalRouter
 {
     Context *ctx;
+    GowinUtils gwu;
 
-    GowinGlobalRouter(Context *ctx) : ctx(ctx){};
+    GowinGlobalRouter(Context *ctx) : ctx(ctx) { gwu.init(ctx); };
 
     // allow io->global, global->global and global->tile clock
     bool global_pip_filter(PipId pip) const
@@ -157,8 +159,18 @@ struct GowinGlobalRouter
 
     bool driver_is_clksrc(const PortRef &driver)
     {
-        // XXX dedicated pins
-        return driver.port == id_O;
+        // dedicated pins
+        if (CellTypePort(driver) == CellTypePort(id_IBUF, id_O)) {
+
+            NPNR_ASSERT(driver.cell->bel != BelId());
+            IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
+            for (size_t i = 0; i < pin_func.size(); ++i) {
+                if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
+                    return true;
+                }
+            }
+        }
+        return false;
     }
 
     void run(void)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 5fe2a004f5..6c836645fe 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -12,6 +12,7 @@
 #include "cst.h"
 #include "globals.h"
 #include "gowin.h"
+#include "gowin_utils.h"
 #include "pack.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -38,6 +39,7 @@ struct GowinImpl : HimbaechelAPI
 
   private:
     HimbaechelHelpers h;
+    GowinUtils gwu;
 
     IdString chip;
     IdString partno;
@@ -70,6 +72,8 @@ void GowinImpl::init(Context *ctx)
     h.init(ctx);
     HimbaechelAPI::init(ctx);
 
+    gwu.init(ctx);
+
     const ArchArgs &args = ctx->getArchArgs();
     // These fields go in the header of the output JSON file and can help
     // gowin_pack support different architectures
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 8a93588775..824e597732 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -348,6 +348,7 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
     return (ttyp, tt)
 
+# pinouts, packages...
 _tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
 def create_packages(chip: Chip, db: chipdb):
     def ioloc_to_tile_bel(ioloc):
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
new file mode 100644
index 0000000000..7cc82fed1e
--- /dev/null
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -0,0 +1,25 @@
+#include "gowin_utils.h"
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// pin functions: GCLKT_4, SSPI_CS, READY etc
+IdStringList GowinUtils::get_pin_funcs(BelId bel)
+{
+    IdStringList bel_name = ctx->getBelName(bel);
+
+    const PadInfoPOD *pins = ctx->package_info->pads.get();
+    size_t len = ctx->package_info->pads.ssize();
+    for (size_t i = 0; i < len; i++) {
+        const PadInfoPOD *pin = &pins[i];
+        if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
+            return IdStringList::parse(ctx, IdString(pin->pad_function).str(ctx));
+        }
+    }
+    return IdStringList();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
new file mode 100644
index 0000000000..ba5b738955
--- /dev/null
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -0,0 +1,24 @@
+#ifndef GOWIN_UTILS_H
+#define GOWIN_UTILS_H
+
+#include "idstringlist.h"
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct GowinUtils
+{
+    Context *ctx;
+
+    GowinUtils() {}
+
+    void init(Context *ctx) { this->ctx = ctx; }
+
+    // pin functions: GCLKT_4, SSPI_CS, READY etc
+    IdStringList get_pin_funcs(BelId bel);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 07c84e2966..79406698bc 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -305,8 +305,8 @@ struct GowinPacker
     // create ALU chain
     void pack_alus(void)
     {
-        static CellTypePort cell_alu_cout = CellTypePort(id_ALU, id_COUT);
-        static CellTypePort cell_alu_cin = CellTypePort(id_ALU, id_CIN);
+        const CellTypePort cell_alu_cout = CellTypePort(id_ALU, id_COUT);
+        const CellTypePort cell_alu_cin = CellTypePort(id_ALU, id_CIN);
         std::vector<std::unique_ptr<CellInfo>> new_cells;
 
         log_info("Pack ALUs...\n");
@@ -409,12 +409,12 @@ struct GowinPacker
     void constrain_lutffs(void)
     {
         // Constrain directly connected LUTs and FFs together to use dedicated resources
-        auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
-        auto dff_ins = pool<CellTypePort>{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
-                                          {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
-                                          {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
-                                          {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
-                                          {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
+        const pool<CellTypePort> lut_outs{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
+        const pool<CellTypePort> dff_ins{{id_DFF, id_D},  {id_DFFE, id_D},  {id_DFFN, id_D},  {id_DFFNE, id_D},
+                                         {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
+                                         {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
+                                         {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
+                                         {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
 
         int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
         log_info("Constrained %d LUTFF pairs.\n", lutffs);

From 49f8620ac99a3af95eacc4ad8f1f11c6b36dcd25 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 22 Jul 2023 10:01:35 +1000
Subject: [PATCH 443/712] gowin: Himbaechel. Implement PLLs

- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
  a need to unify all wires included in the node at the stage of node
  creation, when all wires have already been created.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/himbaechel_dbgen/chip.py      |  3 ++
 himbaechel/uarch/gowin/constids.inc      |  3 ++
 himbaechel/uarch/gowin/globals.cc        | 50 +++++++++++++++----
 himbaechel/uarch/gowin/gowin.h           |  2 +
 himbaechel/uarch/gowin/gowin_arch_gen.py | 61 ++++++++++++++++++++----
 himbaechel/uarch/gowin/pack.cc           | 38 +++++++++++++--
 6 files changed, 134 insertions(+), 23 deletions(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 857935df01..f392cb73ea 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -235,6 +235,9 @@ def create_pip(self, src: str, dst: str):
     def has_wire(self, wire: str):
         # Check if a wire has already been created
         return self.strs.id(wire) in self._wire2idx
+    def set_wire_type(self, wire: str, type: str):
+        # wire type change
+        self.wires[self._wire2idx[self.strs.id(wire)]].wire_type = self.strs.id(type)
     def serialise_lists(self, context: str, bba: BBAWriter):
         # list children of members
         for i, bel in enumerate(self.bels):
diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index e646f91b4f..6cec43f437 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1059,6 +1059,7 @@ X(router)
 // misc
 X(GOWIN_GND)
 X(GOWIN_VCC)
+X(PLL)
 
 // wire types
 X(GLOBAL_CLK)
@@ -1075,6 +1076,8 @@ X(MUX_OUT)
 X(MUX_SEL)
 X(ALU_CIN)
 X(ALU_COUT)
+X(PLL_O)
+X(PLL_I)
 
 // fake dff inputs
 X(XD0)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index bb2e2b0804..01ebaf8cf3 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -43,14 +43,21 @@ struct GowinGlobalRouter
     // allow io->global, global->global and global->tile clock
     bool global_pip_filter(PipId pip) const
     {
-        /*
+        auto is_local = [&](IdString wire_type) {
+            return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
+        };
+
         IdString src_type = ctx->getWireType(ctx->getPipSrcWire(pip));
         IdString dst_type = ctx->getWireType(ctx->getPipDstWire(pip));
-        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O);
-        bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK);
-        return src_valid && dst_valid;
-        */
-        return true;
+        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O);
+        bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I);
+
+        if (ctx->debug) {
+            log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
+                     ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
+                     src_type.c_str(ctx));
+        }
+        return (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
     }
 
     bool is_relaxed_sink(const PortRef &sink) const { return false; }
@@ -151,10 +158,19 @@ struct GowinGlobalRouter
 
     void route_clk_net(NetInfo *net)
     {
-        for (auto usr : net->users.enumerate())
-            backwards_bfs_route(net, usr.index, 1000000, true,
-                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
-        log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+        bool routed = false;
+        for (auto usr : net->users.enumerate()) {
+            routed = backwards_bfs_route(net, usr.index, 1000000, true, [&](PipId pip) {
+                return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
+            });
+            if (!routed) {
+                break;
+            }
+        }
+
+        if (routed) {
+            log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+        }
     }
 
     bool driver_is_clksrc(const PortRef &driver)
@@ -166,10 +182,24 @@ struct GowinGlobalRouter
             IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
             for (size_t i = 0; i < pin_func.size(); ++i) {
                 if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
+                    if (ctx->debug) {
+                        log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
+                                 pin_func[i].c_str(ctx));
+                    }
                     return true;
                 }
             }
         }
+        // PLL outputs
+        if (driver.cell->type.in(id_rPLL, id_PLLVR)) {
+            if (driver.port.in(id_CLKOUT, id_CLKOUTD, id_CLKOUTD3, id_CLKOUTP)) {
+                if (ctx->debug) {
+                    log_info("PLL out:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
+                             driver.port.c_str(ctx));
+                }
+                return true;
+            }
+        }
         return false;
     }
 
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index e831303810..fd3c6dd979 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -39,6 +39,8 @@ enum
     ALU0_Z = 30, // :35, 6 ALU
     RAMW_Z = 36, // RAM16SDP4
 
+    PLL_Z = 275,
+    GSR_Z = 276,
     VCC_Z = 277,
     VSS_Z = 278
 };
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 824e597732..38e8127551 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -22,6 +22,7 @@
 ALU0_Z  = 30 # : 35, 6 ALUs
 RAMW_Z  = 36 # RAM16SDP4
 
+PLL_Z   = 275
 GSR_Z   = 276
 VCC_Z   = 277
 GND_Z   = 278
@@ -121,8 +122,11 @@ def create_nodes(chip: Chip, db: chipdb):
             global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
 
     # add nodes from the apicula db
-    for node_name, node in db.nodes.items():
+    for node_name, node_hdr in db.nodes.items():
+        wire_type, node = node_hdr
         for y, x, wire in node:
+            if wire_type:
+                chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
             new_node = NodeWire(x, y, wire)
             gl_nodes = global_nodes.setdefault(node_name, [])
             if new_node not in gl_nodes:
@@ -139,9 +143,7 @@ def create_nodes(chip: Chip, db: chipdb):
 # coordinates.
 def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     def get_wire_type(name):
-        if name.startswith('GB') or name.startswith('GT'):
-            return "GLOBAL_CLK"
-        elif name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
+        if name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
             return "X0"
         return ""
 
@@ -150,7 +152,7 @@ def get_wire_type(name):
             tt.create_wire(dst, get_wire_type(dst))
         for src in srcs.keys():
             if not tt.has_wire(src):
-                tt.create_wire(src, get_wire_type(dst))
+                tt.create_wire(src, get_wire_type(src))
             tt.create_pip(src, dst)
     # clock wires
     for dst, srcs in db.grid[y][x].clock_pips.items():
@@ -336,18 +338,56 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     for i in range(4):
         tt.add_bel_pin(ff, f"DI[{i}]", f"{lut_inputs[i]}5", PinType.INPUT)
         tt.add_bel_pin(ff, f"WAD[{i}]", f"{lut_inputs[i]}4", PinType.INPUT)
-        # RAD[0] is RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
+        # RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
         # for now we connect it only to A0, the others will be connected
         # directly during packing. RAD[1...3] - similarly.
         tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
         tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
 
-
     tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
     tt.add_bel_pin(ff, f"CE",  "CE2", PinType.INPUT)
     tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
     return (ttyp, tt)
 
+# PLL main tile
+_pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
+        'FBDSEL4', 'FBDSEL5', 'IDSEL0', 'IDSEL1', 'IDSEL2', 'IDSEL3',
+        'IDSEL4', 'IDSEL5', 'ODSEL0', 'ODSEL1', 'ODSEL2', 'ODSEL3',
+        'ODSEL4', 'ODSEL5', 'RESET', 'RESET_P', 'PSDA0', 'PSDA1',
+        'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
+        'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
+_pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
+def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    if ttyp in created_tiletypes:
+        return ttyp, None
+    typename = "PLL"
+    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
+    # wires
+    if chip.name == 'GW1NS-4':
+        pll_name = 'PLLVR'
+        bel_type = 'PLLVR'
+    else:
+        pll_name = 'RPLLA'
+        bel_type = 'rPLL'
+    portmap = db.grid[y][x].bels[pll_name].portmap
+    pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
+    # Not sure how this will affect routing - PLLs are fixed and their outputs
+    # will be handled by a dedicated router
+    #pll.flags = BEL_FLAG_GLOBAL
+    for pin, wire in portmap.items():
+        if pin in _pll_inputs:
+            tt.create_wire(wire, "PLL_I")
+            tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
+        else:
+            assert pin in _pll_outputs, f"Unknown PLL pin{pin}"
+            tt.create_wire(wire, "PLL_O")
+            tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
+
+    create_switch_matrix(tt, db, x, y)
+    return (ttyp, tt)
+
 # pinouts, packages...
 _tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
 def create_packages(chip: Chip, db: chipdb):
@@ -411,9 +451,10 @@ def main():
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
     logic_tiletypes = {12, 13, 14, 15, 16}
-    io_tiletypes = {52, 53, 55, 58, 59, 64, 65, 66}
+    io_tiletypes = {52, 53, 54, 55, 58, 59, 64, 65, 66}
     ssram_tiletypes = {17, 18, 19}
     gsr_tiletypes = {1}
+    pll_tiletypes = {86, 87, 42, 45}
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
@@ -440,6 +481,10 @@ def main():
                 ttyp, _ = create_io_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
                 ch.set_tile_type(x, y, f"IO_{ttyp}")
+            elif ttyp in pll_tiletypes:
+                ttyp, _ = create_pll_tiletype(ch, db, x, y, ttyp)
+                created_tiletypes.add(ttyp)
+                ch.set_tile_type(x, y, f"PLL_{ttyp}")
             else:
                 ttyp, _ = create_null_tiletype(ch, db, x, y, ttyp)
                 created_tiletypes.add(ttyp)
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 79406698bc..ff9da757ab 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -505,17 +505,18 @@ struct GowinPacker
         }
     }
 
-    // Pack global set-reset
+    // ===================================
+    // Global set/reset
+    // ===================================
     void pack_gsr(void)
     {
         log_info("Packing GSR..\n");
 
         bool user_gsr = false;
         for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (ctx->verbose)
-                log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
-            if (ci->type == id_GSR) {
+            auto &ci = *cell.second;
+
+            if (ci.type == id_GSR) {
                 user_gsr = true;
                 break;
             }
@@ -541,6 +542,32 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // PLL
+    // ===================================
+    void pack_pll(void)
+    {
+        log_info("Packing PLL..\n");
+
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+
+            if (ci.type == id_rPLL) {
+                // pin renaming for compatibility
+                for (int i = 0; i < 6; ++i) {
+                    ci.renamePort(ctx->idf("FBDSEL[%d]", i), ctx->idf("FBDSEL%d", i));
+                    ci.renamePort(ctx->idf("IDSEL[%d]", i), ctx->idf("IDSEL%d", i));
+                    ci.renamePort(ctx->idf("ODSEL[%d]", i), ctx->idf("ODSEL%d", i));
+                    if (i < 4) {
+                        ci.renamePort(ctx->idf("PSDA[%d]", i), ctx->idf("PSDA%d", i));
+                        ci.renamePort(ctx->idf("DUTYDA[%d]", i), ctx->idf("DUTYDA%d", i));
+                        ci.renamePort(ctx->idf("FDLY[%d]", i), ctx->idf("FDLY%d", i));
+                    }
+                }
+            }
+        }
+    }
+
     void run(void)
     {
         pack_iobs();
@@ -549,6 +576,7 @@ struct GowinPacker
         pack_wideluts();
         pack_alus();
         constrain_lutffs();
+        pack_pll();
         pack_ram16sdp4();
     }
 };

From df131043841c64f34681eb06e3df01700c720105 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 23 Jul 2023 16:46:04 +1000
Subject: [PATCH 444/712]  gowin: Himbaechel. Add extra chip data

 To implement unusual IOs that have a dynamically changing configuration
 it is convenient to store the switching method in the additional chip
 data.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/himbaechel_dbgen/chip.py      | 11 ++++-
 himbaechel/uarch/gowin/constids.inc      |  2 +
 himbaechel/uarch/gowin/cst.cc            |  2 +-
 himbaechel/uarch/gowin/gowin.cc          |  1 +
 himbaechel/uarch/gowin/gowin.h           | 30 +++++++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 63 +++++++++++++++++++++++-
 himbaechel/uarch/gowin/pack.cc           | 62 +++++++++++++++++++++--
 7 files changed, 164 insertions(+), 7 deletions(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index f392cb73ea..9e4c7c25e7 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -531,6 +531,10 @@ def serialise(self, bba: BBAWriter):
                 tinst.serialise_lists(f"tinst_{x}_{y}", bba)
 
         self.strs.serialise_lists(f"constids", bba)
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists("extra_data", bba)
+            bba.label("extra_data")
+            self.extra_data.serialise("extra_data", bba)
 
         bba.label(f"tile_types")
         for i, tt in enumerate(self.tile_types):
@@ -573,8 +577,11 @@ def serialise(self, bba: BBAWriter):
         bba.u32(0)
         # db-defined constids
         bba.ref("constids")
-        # extra data: not yet used
-        bba.u32(0)
+        # extra data
+        if self.extra_data is not None:
+            bba.ref("extra_data")
+        else:
+            bba.u32(0)
 
     def write_bba(self, filename):
         with open(filename, "w") as f:
diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 6cec43f437..b5eb981bc7 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1060,6 +1060,8 @@ X(router)
 X(GOWIN_GND)
 X(GOWIN_VCC)
 X(PLL)
+X(BOTTOM_IO_PORT_A)
+X(BOTTOM_IO_PORT_B)
 
 // wire types
 X(GLOBAL_CLK)
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
index 5b9ddaaacc..8821eec8d8 100644
--- a/himbaechel/uarch/gowin/cst.cc
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -47,7 +47,7 @@ struct GowinCstReader
             row = col;
             col = 1;
         }
-        int z = match[3].str()[0] - 'A';
+        int z = match[3].str()[0] - 'A' + BelZ::IOBA_Z;
         return Loc(col - 1, row - 1, z);
     }
 
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 6c836645fe..4d12361ddc 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -146,6 +146,7 @@ void GowinImpl::pack()
     }
     gowin_pack(ctx);
 }
+
 void GowinImpl::prePlace() { assign_cell_info(); }
 void GowinImpl::postPlace()
 {
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index fd3c6dd979..2a93148031 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -24,6 +24,33 @@ inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
 // Return true if a cell is a SSRAM
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
+
+// extra data in the chip db
+NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
+    int32_t wire_a_net;
+    int32_t wire_b_net;
+});
+
+NPNR_PACKED_STRUCT(struct Bottom_io_POD {
+    // simple OBUF
+    static constexpr int8_t NORMAL = 0;
+    RelSlice<Bottom_io_cnd_POD> conditions;
+});
+
+NPNR_PACKED_STRUCT(struct Extra_chip_data_POD { Bottom_io_POD bottom_io; });
+
+inline IdString get_bottom_io_wire_a_net(const ChipInfoPOD *chip, int8_t condition)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
+    return IdString(extra->bottom_io.conditions[condition].wire_a_net);
+}
+
+inline IdString get_bottom_io_wire_b_net(const ChipInfoPOD *chip, int8_t condition)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
+    return IdString(extra->bottom_io.conditions[condition].wire_b_net);
+}
+
 } // namespace
 
 // Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
@@ -39,6 +66,9 @@ enum
     ALU0_Z = 30, // :35, 6 ALU
     RAMW_Z = 36, // RAM16SDP4
 
+    IOBA_Z = 50,
+    IOBB_Z = 51, // +IOBC...IOBL
+
     PLL_Z = 275,
     GSR_Z = 276,
     VCC_Z = 277,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 38e8127551..1fee760bdc 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -22,11 +22,17 @@
 ALU0_Z  = 30 # : 35, 6 ALUs
 RAMW_Z  = 36 # RAM16SDP4
 
+IOBA_Z  = 50
+IOBB_Z  = 51
+
 PLL_Z   = 275
 GSR_Z   = 276
 VCC_Z   = 277
 GND_Z   = 278
 
+# =======================================
+# Chipdb additional info
+# =======================================
 @dataclass
 class TileExtraData(BBAStruct):
     tile_class: IdString # The general functionality of the slightly different tiles,
@@ -38,6 +44,45 @@ def serialise_lists(self, context: str, bba: BBAWriter):
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.tile_class.index)
 
+@dataclass
+class BottomIOCnd(BBAStruct):
+    wire_a_net: IdString
+    wire_b_net: IdString
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.wire_a_net.index)
+        bba.u32(self.wire_b_net.index)
+
+@dataclass
+class BottomIO(BBAStruct):
+    conditions: list[BottomIOCnd] = field(default_factory = list)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_conditions")
+        for i, cnd in enumerate(self.conditions):
+            cnd.serialise(f"{context}_cnd{i}", bba)
+
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.slice(f"{context}_conditions", len(self.conditions))
+
+@dataclass
+class ChipExtraData(BBAStruct):
+    strs: StringPool
+    bottom_io: BottomIO
+
+    def create_bottom_io(self):
+        self.bottom_io = BottomIO()
+
+    def add_bottom_io_cnd(self, net_a: str, net_b: str):
+        self.bottom_io.conditions.append(BottomIOCnd(self.strs.id(net_a), self.strs.id(net_b)))
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        self.bottom_io.serialise_lists(f"{context}_bottom_io", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        self.bottom_io.serialise(f"{context}_bottom_io", bba)
+
 created_tiletypes = set()
 
 # u-turn at the rim
@@ -224,9 +269,17 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.create_wire(portmap['I'], "IO_I")
         tt.create_wire(portmap['O'], "IO_O")
         # bels
-        io = tt.create_bel(name, "IOB", z = i)
+        io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
         tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
+        # bottom io
+        if 'BOTTOM_IO_PORT_A' in portmap.keys():
+            if not tt.has_wire(portmap['BOTTOM_IO_PORT_A']):
+                tt.create_wire(portmap['BOTTOM_IO_PORT_A'], "IO_I")
+                tt.create_wire(portmap['BOTTOM_IO_PORT_B'], "IO_I")
+            tt.add_bel_pin(io, "BOTTOM_IO_PORT_A", portmap['BOTTOM_IO_PORT_A'], PinType.INPUT)
+            tt.add_bel_pin(io, "BOTTOM_IO_PORT_B", portmap['BOTTOM_IO_PORT_B'], PinType.INPUT)
+
     create_switch_matrix(tt, db, x, y)
     return (ttyp, tt)
 
@@ -425,6 +478,13 @@ def ioloc_to_tile_bel(ioloc):
             bank = int(db.pin_bank[io_loc])
             pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
 
+# Extra chip data
+def create_extra_data(chip: Chip, db: chipdb):
+    chip.extra_data = ChipExtraData(chip.strs, None)
+    chip.extra_data.create_bottom_io()
+    for net_a, net_b in db.bottom_io[2]:
+        chip.extra_data.add_bottom_io_cnd(net_a, net_b)
+
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
     parser.add_argument('-d', '--device', required=True)
@@ -492,6 +552,7 @@ def main():
 
     # Create nodes between tiles
     create_nodes(ch, db)
+    create_extra_data(ch, db)
     ch.write_bba(args.output)
 if __name__ == '__main__':
     main()
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ff9da757ab..c91763f5fd 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -21,9 +21,37 @@ struct GowinPacker
     // ===================================
     // IO
     // ===================================
-    void pack_iobs(void)
+    void config_bottom_row(CellInfo &ci, Loc loc, uint8_t cnd = Bottom_io_POD::NORMAL)
+    {
+        if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
+            return;
+        }
+        if (cnd == Bottom_io_POD::NORMAL && loc.z != BelZ::IOBA_Z) {
+            return;
+        }
+        auto connect_io_wire = [&](IdString port, IdString net_name) {
+            // XXX it is very convenient that nothing terrible happens in case
+            // of absence/presence of a port
+            ci.disconnectPort(port);
+            ci.addInput(port);
+            if (net_name == id_VSS) {
+                ci.connectPort(port, ctx->nets[ctx->id("$PACKER_GND")].get());
+            } else {
+                NPNR_ASSERT(net_name == id_VCC);
+                ci.connectPort(port, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            }
+        };
+
+        IdString wire_a_net = get_bottom_io_wire_a_net(ctx->chip_info, cnd);
+        connect_io_wire(id_BOTTOM_IO_PORT_A, wire_a_net);
+
+        IdString wire_b_net = get_bottom_io_wire_b_net(ctx->chip_info, cnd);
+        connect_io_wire(id_BOTTOM_IO_PORT_B, wire_b_net);
+    }
+
+    // Attributes of deleted cells are copied
+    void trim_nextpnr_iobs(void)
     {
-        log_info("Pack IOBs...\n");
         // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
         const pool<CellTypePort> top_ports{
                 CellTypePort(id_IBUF, id_I),
@@ -62,6 +90,34 @@ struct GowinPacker
             ctx->cells.erase(cell_name);
     }
 
+    BelId bind_io(CellInfo &ci)
+    {
+        BelId bel = ctx->getBelByName(IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()));
+        ci.unsetAttr(id_BEL);
+        ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+        return bel;
+    }
+
+    void pack_iobs(void)
+    {
+        log_info("Pack IOBs...\n");
+        trim_nextpnr_iobs();
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (!ci.type.in(id_IBUF, id_OBUF, id_IOBUF)) // XXX TBUF
+                continue;
+            if (ci.attrs.count(id_BEL) == 0) {
+                log_error("Unconstrained IO:%s\n", ctx->nameOf(&ci));
+            }
+            BelId io_bel = bind_io(ci);
+            Loc io_loc = ctx->getBelLocation(io_bel);
+            if (io_loc.y == ctx->getGridDimY() - 1) {
+                config_bottom_row(ci, io_loc);
+            }
+        }
+    }
+
     // ===================================
     // Constant nets
     // ===================================
@@ -570,8 +626,8 @@ struct GowinPacker
 
     void run(void)
     {
-        pack_iobs();
         handle_constants();
+        pack_iobs();
         pack_gsr();
         pack_wideluts();
         pack_alus();

From 03c413a27a93ad2f1b69a246ff9733e8b78a9842 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 25 Jul 2023 13:25:33 +1000
Subject: [PATCH 445/712] gowin: Himbaechel. Add simplified IO

Add processing IO located on the sides of some chips. These are IOBUF,
which are converted into IBUF and OBUF not by fuses, but by signaling to
OE.

Also added the creation of a Global Set / Reset for all chips, instead
of a list of tile types, information from the apicula database is used,
and minor fixes.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc        |  2 +-
 himbaechel/uarch/gowin/gowin.h           | 14 ++++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 38 ++++++++++++++++++----
 himbaechel/uarch/gowin/pack.cc           | 41 +++++++++++++++++++-----
 4 files changed, 79 insertions(+), 16 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 01ebaf8cf3..ecb99e43ff 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -52,7 +52,7 @@ struct GowinGlobalRouter
         bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O);
         bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I);
 
-        if (ctx->debug) {
+        if (ctx->debug && false) {
             log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
                      ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
                      src_type.c_str(ctx));
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 2a93148031..8f21c23a5b 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -5,6 +5,10 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+namespace BelFlags {
+static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
+}
+
 namespace {
 // Return true if a cell is a LUT
 inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
@@ -39,6 +43,12 @@ NPNR_PACKED_STRUCT(struct Bottom_io_POD {
 
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD { Bottom_io_POD bottom_io; });
 
+inline bool have_bottom_io_cnds(const ChipInfoPOD *chip)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
+    return extra->bottom_io.conditions.size() != 0;
+}
+
 inline IdString get_bottom_io_wire_a_net(const ChipInfoPOD *chip, int8_t condition)
 {
     const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
@@ -51,6 +61,10 @@ inline IdString get_bottom_io_wire_b_net(const ChipInfoPOD *chip, int8_t conditi
     return IdString(extra->bottom_io.conditions[condition].wire_b_net);
 }
 
+inline bool getBelSimpleIO(const ChipInfoPOD *chip, BelId bel)
+{
+    return chip_bel_info(chip, bel).flags & BelFlags::FLAG_SIMPLE_IO;
+}
 } // namespace
 
 // Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 1fee760bdc..d2482ad755 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -11,6 +11,9 @@
 from himbaechel_dbgen.chip import *
 from apycula import chipdb
 
+# Bel flags
+BEL_FLAG_SIMPLE_IO = 0x100
+
 # Z of the bels
 # sync with C++ part!
 LUT0_Z  = 0       # z(DFFx) = z(LUTx) + 1
@@ -171,7 +174,10 @@ def create_nodes(chip: Chip, db: chipdb):
         wire_type, node = node_hdr
         for y, x, wire in node:
             if wire_type:
-                chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
+                if not chip.tile_type_at(x, y).has_wire(wire):
+                    chip.tile_type_at(x, y).create_wire(wire, wire_type)
+                else:
+                    chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
             new_node = NodeWire(x, y, wire)
             gl_nodes = global_nodes.setdefault(node_name, [])
             if new_node not in gl_nodes:
@@ -200,7 +206,7 @@ def get_wire_type(name):
                 tt.create_wire(src, get_wire_type(src))
             tt.create_pip(src, dst)
     # clock wires
-    for dst, srcs in db.grid[y][x].clock_pips.items():
+    for dst, srcs in db.grid[y][x].pure_clock_pips.items():
         if not tt.has_wire(dst):
             tt.create_wire(dst, "GLOBAL_CLK")
         for src in srcs.keys():
@@ -234,6 +240,12 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.create_wire('VCC', 'VCC')
         gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
         tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
+        # also here may be GSR
+        if 'GSR' in db.grid[y][x].bels.keys():
+            portmap = db.grid[y][x].bels['GSR'].portmap
+            tt.create_wire(portmap['GSRI'], "GSRI")
+            io = tt.create_bel("GSR", "GSR", z = GSR_Z)
+            tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
 
     create_switch_matrix(tt, db, x, y)
     return (ttyp, tt)
@@ -262,15 +274,27 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt = chip.create_tile_type(f"{typename}_{ttyp}")
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
-    for i in range(2):
-        name = ['IOBA', 'IOBB'][i]
+    simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1'}
+    if simple_io:
+        rng = 10
+    else:
+        rng = 2
+    for i in range(rng):
+        name = 'IOB' + 'ABCDEFGHIJ'[i]
+        # XXX some IOBs excluded from generic chipdb for some reason
+        if name not in db.grid[y][x].bels.keys():
+            continue
         # wires
         portmap = db.grid[y][x].bels[name].portmap
         tt.create_wire(portmap['I'], "IO_I")
         tt.create_wire(portmap['O'], "IO_O")
+        tt.create_wire(portmap['OE'], "IO_OE")
         # bels
         io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
+        if simple_io:
+            io.flags |= BEL_FLAG_SIMPLE_IO
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
+        tt.add_bel_pin(io, "OE", portmap['OE'], PinType.INPUT)
         tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
         # bottom io
         if 'BOTTOM_IO_PORT_A' in portmap.keys():
@@ -510,11 +534,11 @@ def main():
     # The manufacturer distinguishes by externally identical tiles, so keep
     # these differences (in case it turns out later that there is a slightly
     # different routing or something like that).
-    logic_tiletypes = {12, 13, 14, 15, 16}
-    io_tiletypes = {52, 53, 54, 55, 58, 59, 64, 65, 66}
+    logic_tiletypes = db.tile_types['C']
+    io_tiletypes = db.tile_types['I']
     ssram_tiletypes = {17, 18, 19}
     gsr_tiletypes = {1}
-    pll_tiletypes = {86, 87, 42, 45}
+    pll_tiletypes = db.tile_types['P']
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index c91763f5fd..ec8816cf47 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -21,8 +21,26 @@ struct GowinPacker
     // ===================================
     // IO
     // ===================================
+    void config_simple_io(CellInfo &ci)
+    {
+        if (ci.type.in(id_TBUF, id_IOBUF)) {
+            return;
+        }
+        log_info("simple:%s\n", ctx->nameOf(&ci));
+        ci.addInput(id_OE);
+        if (ci.type == id_OBUF) {
+            ci.connectPort(id_OE, ctx->nets[ctx->id("$PACKER_GND")].get());
+        } else {
+            NPNR_ASSERT(ci.type == id_IBUF);
+            ci.connectPort(id_OE, ctx->nets[ctx->id("$PACKER_VCC")].get());
+        }
+    }
+
     void config_bottom_row(CellInfo &ci, Loc loc, uint8_t cnd = Bottom_io_POD::NORMAL)
     {
+        if (!have_bottom_io_cnds(ctx->chip_info)) {
+            return;
+        }
         if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
             return;
         }
@@ -93,6 +111,7 @@ struct GowinPacker
     BelId bind_io(CellInfo &ci)
     {
         BelId bel = ctx->getBelByName(IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()));
+        NPNR_ASSERT(bel != BelId());
         ci.unsetAttr(id_BEL);
         ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         return bel;
@@ -115,6 +134,9 @@ struct GowinPacker
             if (io_loc.y == ctx->getGridDimY() - 1) {
                 config_bottom_row(ci, io_loc);
             }
+            if (getBelSimpleIO(ctx->chip_info, io_bel)) {
+                config_simple_io(ci);
+            }
         }
     }
 
@@ -138,10 +160,11 @@ struct GowinPacker
             NetInfo *constnet = net->second.get();
             for (auto user : constnet->users) {
                 CellInfo *uc = user.cell;
-                if (ctx->debug)
-                    log_info("%s user %s/%s\n", ctx->nameOf(constnet), ctx->nameOf(uc), user.port.c_str(ctx));
-
                 if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
+                    if (ctx->debug) {
+                        log_info("%s user %s/%s\n", ctx->nameOf(constnet), ctx->nameOf(uc), user.port.c_str(ctx));
+                    }
+
                     auto it_param = uc->params.find(id_INIT);
                     if (it_param == uc->params.end())
                         log_error("No initialization for lut found.\n");
@@ -318,9 +341,9 @@ struct GowinPacker
         // CIN from logic
         cin_ci->addInput(id_I1);
         cin_ci->addInput(id_I3);
-        cin_ci->addInput(id_I2);
         cin_ci->connectPort(id_I1, cin_net);
         cin_ci->connectPort(id_I3, cin_net);
+        cin_ci->addInput(id_I2);
         cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
         cin_ci->params[id_ALU_MODE] = std::string("0"); // ADD
         return cin_ci;
@@ -342,6 +365,8 @@ struct GowinPacker
         cout_ci->connectPort(id_CIN, cin_net);
         cout_ci->addOutput(id_SUM);
         cout_ci->connectPort(id_SUM, cout_net);
+        cout_ci->addInput(id_I2);
+        cout_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
 
         cout_ci->params[id_ALU_MODE] = std::string("C2L");
         return cout_ci;
@@ -425,8 +450,8 @@ struct GowinPacker
                             cout_block_ci->constr_y = 0;
                             cout_block_ci->constr_z = alu_chain_len % 6;
                             if (ctx->debug) {
-                                log_info("Add ALU carry out to the chain (len:%d): %s\n", alu_chain_len,
-                                         ctx->nameOf(cout_block_ci));
+                                log_info("Add ALU carry out to the chain (len:%d): %s COUT-net: %s\n", alu_chain_len,
+                                         ctx->nameOf(cout_block_ci), ctx->nameOf(cout_net));
                             }
 
                             ++alu_chain_len;
@@ -566,7 +591,7 @@ struct GowinPacker
     // ===================================
     void pack_gsr(void)
     {
-        log_info("Packing GSR..\n");
+        log_info("Pack GSR..\n");
 
         bool user_gsr = false;
         for (auto &cell : ctx->cells) {
@@ -603,7 +628,7 @@ struct GowinPacker
     // ===================================
     void pack_pll(void)
     {
-        log_info("Packing PLL..\n");
+        log_info("Pack PLL..\n");
 
         for (auto &cell : ctx->cells) {
             auto &ci = *cell.second;

From 01044cc910cd97c670f79330104f53b01a8dc4a8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 27 Jul 2023 17:28:58 +1000
Subject: [PATCH 446/712] gowin: Himbaechel. Add redundant checks

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 2 +-
 himbaechel/uarch/gowin/pack.cc  | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 4d12361ddc..846ef18b19 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -155,7 +155,7 @@ void GowinImpl::postPlace()
         for (auto &cell : ctx->cells) {
             auto ci = cell.second.get();
             IdStringList bel = ctx->getBelName(ci->bel);
-            log_info("%s -> %s\n", ctx->nameOf(ci), bel.str(ctx).c_str());
+            log_info("%s: %s\n", bel.str(ctx).c_str(), ctx->nameOf(ci));
         }
         log_break();
     }
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ec8816cf47..cd79f31981 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -249,7 +249,7 @@ struct GowinPacker
             for (int i = 0; i < 2; ++i) {
                 // input src
                 NetInfo *in = ci_cursor->getPort(inputs[i].port);
-                NPNR_ASSERT(in && in->driver.cell);
+                NPNR_ASSERT(in && in->driver.cell && in->driver.cell->cluster == ClusterId());
                 int child_dx = dx + inputs[i].dx;
                 int child_dz = dz + inputs[i].dz;
                 ci_root.constr_children.push_back(in->driver.cell);
@@ -423,6 +423,7 @@ struct GowinPacker
                             log_info("Add ALU to the chain (len:%d): %s\n", alu_chain_len, ctx->nameOf(ci));
                         }
                         cin_block_ci->constr_children.push_back(ci);
+                        NPNR_ASSERT(ci->cluster == ClusterId());
                         ci->cluster = cin_block_ci->name;
                         ci->constr_abs_z = false;
                         ci->constr_x = alu_chain_len / 6;
@@ -444,6 +445,7 @@ struct GowinPacker
                             new_cells.push_back(std::move(alu_add_cout_block(ctx, ci, cout_net)));
                             CellInfo *cout_block_ci = new_cells.back().get();
                             cin_block_ci->constr_children.push_back(cout_block_ci);
+                            NPNR_ASSERT(cout_block_ci->cluster == ClusterId());
                             cout_block_ci->cluster = cin_block_ci->name;
                             cout_block_ci->constr_abs_z = false;
                             cout_block_ci->constr_x = alu_chain_len / 6;
@@ -466,6 +468,7 @@ struct GowinPacker
                         new_cells.push_back(std::move(alu_add_dummy_block(ctx, ci)));
                         CellInfo *dummy_block_ci = new_cells.back().get();
                         cin_block_ci->constr_children.push_back(dummy_block_ci);
+                        NPNR_ASSERT(dummy_block_ci->cluster == ClusterId());
                         dummy_block_ci->cluster = cin_block_ci->name;
                         dummy_block_ci->constr_abs_z = false;
                         dummy_block_ci->constr_x = alu_chain_len / 6;

From 5e9a96d358e287c35e29d25242188f0655ebdeaa Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 6 Aug 2023 20:56:08 +1000
Subject: [PATCH 447/712] gowin: Himbaechel. Add SERDES and differential IO

- experiment with notifyBelChange as an auxiliary cells reservation mechanism;
- since HCLK pips depend on the coordinates, and not on the tile type,
  the tile type is copied if necessary;
- information about supported types of differential IO primitives has
  been added to the extra information of the chip;

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   6 +
 himbaechel/uarch/gowin/globals.cc        |   7 +-
 himbaechel/uarch/gowin/gowin.cc          |  80 ++++++-
 himbaechel/uarch/gowin/gowin.h           |  34 ++-
 himbaechel/uarch/gowin/gowin_arch_gen.py | 187 +++++++++------
 himbaechel/uarch/gowin/pack.cc           | 285 ++++++++++++++++++++++-
 6 files changed, 512 insertions(+), 87 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index b5eb981bc7..883961edc4 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1089,3 +1089,9 @@ X(XD3)
 X(XD4)
 X(XD5)
 
+// HCLK wires
+X(HCLK_OUT0)
+X(HCLK_OUT1)
+X(HCLK_OUT2)
+X(HCLK_OUT3)
+
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index ecb99e43ff..365924fc19 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -52,12 +52,15 @@ struct GowinGlobalRouter
         bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O);
         bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I);
 
-        if (ctx->debug && false) {
+        bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        if (ctx->debug && res && false) {
             log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
                      ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
                      src_type.c_str(ctx));
+            // log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
+            // is_local(src_type), is_local(dst_type));
         }
-        return (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        return res;
     }
 
     bool is_relaxed_sink(const PortRef &sink) const { return false; }
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 846ef18b19..cebefa89a2 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -29,6 +29,7 @@ struct GowinImpl : HimbaechelAPI
     void prePlace() override;
     void postPlace() override;
     void preRoute() override;
+    void postRoute() override;
 
     bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
 
@@ -37,6 +38,10 @@ struct GowinImpl : HimbaechelAPI
 
     bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
 
+    // placer hits
+    void notifyBelChange(BelId bel, CellInfo *cell) override;
+    bool checkBelAvail(BelId bel) const override;
+
   private:
     HimbaechelHelpers h;
     GowinUtils gwu;
@@ -44,6 +49,8 @@ struct GowinImpl : HimbaechelAPI
     IdString chip;
     IdString partno;
 
+    std::set<BelId> inactive_bels;
+
     // Validity checking
     struct GowinCellInfo
     {
@@ -154,8 +161,11 @@ void GowinImpl::postPlace()
         log_info("================== Final Placement ===================\n");
         for (auto &cell : ctx->cells) {
             auto ci = cell.second.get();
-            IdStringList bel = ctx->getBelName(ci->bel);
-            log_info("%s: %s\n", bel.str(ctx).c_str(), ctx->nameOf(ci));
+            if (ci->bel != BelId()) {
+                log_info("%s: %s\n", ctx->nameOfBel(ci->bel), ctx->nameOf(ci));
+            } else {
+                log_info("unknown: %s\n", ctx->nameOf(ci));
+            }
         }
         log_break();
     }
@@ -163,6 +173,43 @@ void GowinImpl::postPlace()
 
 void GowinImpl::preRoute() { gowin_route_globals(ctx); }
 
+void GowinImpl::postRoute()
+{
+    std::set<IdString> visited_hclk_users;
+
+    for (auto &cell : ctx->cells) {
+        auto ci = cell.second.get();
+        if (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC)) {
+            if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
+                // mark FCLK<-HCLK connections
+                ci->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
+                const NetInfo *h_net = ci->getPort(id_FCLK);
+                if (h_net) {
+                    for (auto const &user : h_net->users) {
+                        if (user.port != id_FCLK) {
+                            continue;
+                        }
+                        visited_hclk_users.insert(user.cell->name);
+                        // XXX Based on the implementation, perhaps a function
+                        // is needed to get Pip from a Wire
+                        PipId up_pip = h_net->wires.at(ctx->getNetinfoSinkWire(h_net, user, 0)).pip;
+                        IdString up_wire_name = ctx->getWireName(ctx->getPipSrcWire(up_pip))[1];
+                        if (up_wire_name.in(id_HCLK_OUT0, id_HCLK_OUT1, id_HCLK_OUT2, id_HCLK_OUT3)) {
+                            ci->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
+                        }
+                        if (ctx->debug) {
+                            log_info("HCLK user cell:%s, port:%s, wire:%s, pip:%s, up wire:%s\n",
+                                     ctx->nameOf(user.cell), user.port.c_str(ctx),
+                                     ctx->nameOfWire(ctx->getNetinfoSinkWire(h_net, user, 0)), ctx->nameOfPip(up_pip),
+                                     ctx->nameOfWire(ctx->getPipSrcWire(up_pip)));
+                        }
+                    }
+                }
+            }
+        }
+    }
+}
+
 bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     Loc l = ctx->getBelLocation(bel);
@@ -198,6 +245,9 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
     if (type_is_ssram(cell_type)) {
         return id_RAM16SDP4;
     }
+    if (type_is_iologic(cell_type)) {
+        return id_IOLOGIC;
+    }
     if (cell_type == id_GOWIN_GND) {
         return id_GND;
     }
@@ -222,6 +272,9 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
     if (bel_type == id_RAM16SDP4) {
         return type_is_ssram(cell_type);
     }
+    if (bel_type == id_IOLOGIC) {
+        return type_is_iologic(cell_type);
+    }
     if (bel_type == id_GND) {
         return cell_type == id_GOWIN_GND;
     }
@@ -342,6 +395,29 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     }
     return true;
 }
+// placer hits
+void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
+{
+    if (cell != nullptr) {
+        // OSER8 took both IOLOGIC bels in the tile
+        if (cell->type == id_OSER8) {
+            Loc loc = ctx->getBelLocation(bel);
+            loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
+            inactive_bels.insert(ctx->getBelByLocation(loc));
+        }
+    } else {
+        // the unbind is about to happen
+        CellInfo *ci = ctx->getBoundBelCell(bel);
+        // OSER8 took both IOLOGIC bels in the tile
+        if (ci->type == id_OSER8) {
+            Loc loc = ctx->getBelLocation(bel);
+            loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
+            inactive_bels.erase(ctx->getBelByLocation(loc));
+        }
+    }
+}
+
+bool GowinImpl::checkBelAvail(BelId bel) const { return inactive_bels.find(bel) == inactive_bels.end(); }
 
 } // namespace
 
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 8f21c23a5b..4051b0754a 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -25,6 +25,16 @@ inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
 inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
 inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
 
+inline bool type_is_diffio(IdString cell_type)
+{
+    return cell_type.in(id_ELVDS_IOBUF, id_ELVDS_IBUF, id_ELVDS_TBUF, id_ELVDS_OBUF, id_TLVDS_IOBUF, id_TLVDS_IBUF,
+                        id_TLVDS_TBUF, id_TLVDS_OBUF);
+}
+inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type); }
+
+inline bool type_is_iologic(IdString cell_type) { return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8); }
+inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type); }
+
 // Return true if a cell is a SSRAM
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
@@ -38,10 +48,26 @@ NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
 NPNR_PACKED_STRUCT(struct Bottom_io_POD {
     // simple OBUF
     static constexpr int8_t NORMAL = 0;
+    // DDR
+    static constexpr int8_t DDR = 1;
     RelSlice<Bottom_io_cnd_POD> conditions;
 });
 
-NPNR_PACKED_STRUCT(struct Extra_chip_data_POD { Bottom_io_POD bottom_io; });
+NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
+    Bottom_io_POD bottom_io;
+    RelSlice<IdString> diff_io_types;
+});
+
+inline bool is_diff_io_supported(const ChipInfoPOD *chip, IdString type)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
+    for (auto &dtype : extra->diff_io_types) {
+        if (IdString(dtype) == type) {
+            return true;
+        }
+    }
+    return false;
+}
 
 inline bool have_bottom_io_cnds(const ChipInfoPOD *chip)
 {
@@ -61,10 +87,12 @@ inline IdString get_bottom_io_wire_b_net(const ChipInfoPOD *chip, int8_t conditi
     return IdString(extra->bottom_io.conditions[condition].wire_b_net);
 }
 
-inline bool getBelSimpleIO(const ChipInfoPOD *chip, BelId bel)
+// Bels and pips
+inline bool is_simple_io_bel(const ChipInfoPOD *chip, BelId bel)
 {
     return chip_bel_info(chip, bel).flags & BelFlags::FLAG_SIMPLE_IO;
 }
+
 } // namespace
 
 // Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
@@ -83,6 +111,8 @@ enum
     IOBA_Z = 50,
     IOBB_Z = 51, // +IOBC...IOBL
 
+    IOLOGICA_Z = 70,
+
     PLL_Z = 275,
     GSR_Z = 276,
     VCC_Z = 277,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index d2482ad755..2f38a960cd 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -28,6 +28,8 @@
 IOBA_Z  = 50
 IOBB_Z  = 51
 
+IOLOGICA_Z = 70
+
 PLL_Z   = 275
 GSR_Z   = 276
 VCC_Z   = 277
@@ -74,6 +76,7 @@ def serialise(self, context: str, bba: BBAWriter):
 class ChipExtraData(BBAStruct):
     strs: StringPool
     bottom_io: BottomIO
+    diff_io_types: list[IdString] = field(default_factory = list)
 
     def create_bottom_io(self):
         self.bottom_io = BottomIO()
@@ -81,12 +84,21 @@ def create_bottom_io(self):
     def add_bottom_io_cnd(self, net_a: str, net_b: str):
         self.bottom_io.conditions.append(BottomIOCnd(self.strs.id(net_a), self.strs.id(net_b)))
 
+    def add_diff_io_type(self, diff_type: str):
+        self.diff_io_types.append(self.strs.id(diff_type))
+
     def serialise_lists(self, context: str, bba: BBAWriter):
         self.bottom_io.serialise_lists(f"{context}_bottom_io", bba)
+        bba.label(f"{context}_diff_io_types")
+        for i, diff_io_type in enumerate(self.diff_io_types):
+            bba.u32(diff_io_type.index)
+
     def serialise(self, context: str, bba: BBAWriter):
         self.bottom_io.serialise(f"{context}_bottom_io", bba)
+        bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
 
-created_tiletypes = set()
+# { ttyp : {}}
+created_tiletypes = {}
 
 # u-turn at the rim
 uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
@@ -172,6 +184,8 @@ def create_nodes(chip: Chip, db: chipdb):
     # add nodes from the apicula db
     for node_name, node_hdr in db.nodes.items():
         wire_type, node = node_hdr
+        if len(node) < 2:
+            continue
         for y, x, wire in node:
             if wire_type:
                 if not chip.tile_type_at(x, y).has_wire(wire):
@@ -181,17 +195,11 @@ def create_nodes(chip: Chip, db: chipdb):
             new_node = NodeWire(x, y, wire)
             gl_nodes = global_nodes.setdefault(node_name, [])
             if new_node not in gl_nodes:
-                gl_nodes.append(NodeWire(x, y, wire))
+                    gl_nodes.append(NodeWire(x, y, wire))
 
     for name, node in global_nodes.items():
         chip.add_node(node)
 
-
-# About X and Y as parameters - in some cases, the type of manufacturer's tile
-# is not different, but some wires are not physically present, that is, routing
-# depends on the location of otherwise identical tiles. There are many options
-# for taking this into account, but for now we make a distinction here, by
-# coordinates.
 def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     def get_wire_type(name):
         if name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
@@ -205,6 +213,7 @@ def get_wire_type(name):
             if not tt.has_wire(src):
                 tt.create_wire(src, get_wire_type(src))
             tt.create_pip(src, dst)
+
     # clock wires
     for dst, srcs in db.grid[y][x].pure_clock_pips.items():
         if not tt.has_wire(dst):
@@ -214,21 +223,58 @@ def get_wire_type(name):
                 tt.create_wire(src, "GLOBAL_CLK")
             tt.create_pip(src, dst)
 
-def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
+    # hclk wires
+    for dst, srcs in db.hclk_pips[(y, x)].items():
+        if not tt.has_wire(dst):
+            tt.create_wire(dst, "HCLK")
+        for src in srcs.keys():
+            if not tt.has_wire(src):
+                tt.create_wire(src, "HCLK")
+            tt.create_pip(src, dst)
+
+extra_type_cnt = 1
+def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+    global extra_type_cnt
+    create_hclk_pips = False
+
+    # HCLK wires can be different in the same types of tiles, so if necessary, create a new type
     if ttyp in created_tiletypes:
-        return ttyp, None
+        # check if we have HCLK pips
+        if (y, x) in db.hclk_pips and created_tiletypes[ttyp]['hclk_pips'] != db.hclk_pips[y, x]:
+            create_hclk_pips = True
+            ttyp = 100 * ttyp + extra_type_cnt
+            extra_type_cnt += 1
+        else:
+            chip.set_tile_type(x, y, created_tiletypes[ttyp]['tiletype'])
+            return
+    elif (y, x) in db.hclk_pips:
+        create_hclk_pips = True
+    else:
+        created_tiletypes[ttyp] = {}
+    if create_hclk_pips:
+        created_tiletypes.setdefault(ttyp, {}).update({'hclk_pips': db.hclk_pips[y, x]})
+
+    tiletype, tt = create_func(chip, db, x, y, ttyp)
+
+    if create_hclk_pips:
+        create_hclk_switch_matrix(tt, db, x, y)
+    create_switch_matrix(tt, db, x, y)
+    chip.set_tile_type(x, y, tiletype)
+    created_tiletypes.setdefault(ttyp, {}).update({'tiletype': tiletype})
+
+def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     typename = "NULL"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
 # responsible nodes, there will be IO banks, configuration, etc.
 def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     typename = "CORNER"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     if x == 0 and y == 0:
@@ -241,21 +287,19 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
         tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
         # also here may be GSR
-        if 'GSR' in db.grid[y][x].bels.keys():
+        if 'GSR' in db.grid[y][x].bels:
             portmap = db.grid[y][x].bels['GSR'].portmap
             tt.create_wire(portmap['GSRI'], "GSRI")
             io = tt.create_bel("GSR", "GSR", z = GSR_Z)
             tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
 
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
 # Global set/reset. GW2A series has special cell for it
 def create_gsr_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     typename = "GSR"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     portmap = db.grid[y][x].bels['GSR'].portmap
@@ -263,15 +307,13 @@ def create_gsr_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     io = tt.create_bel("GSR", "GSR", z = GSR_Z)
     tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
 
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
-# simple IO - only A and B
+# IO
 def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     typename = "IO"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1'}
@@ -282,7 +324,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     for i in range(rng):
         name = 'IOB' + 'ABCDEFGHIJ'[i]
         # XXX some IOBs excluded from generic chipdb for some reason
-        if name not in db.grid[y][x].bels.keys():
+        if name not in db.grid[y][x].bels:
             continue
         # wires
         portmap = db.grid[y][x].bels[name].portmap
@@ -294,25 +336,39 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         if simple_io:
             io.flags |= BEL_FLAG_SIMPLE_IO
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
-        tt.add_bel_pin(io, "OE", portmap['OE'], PinType.INPUT)
+        tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)
         tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
         # bottom io
-        if 'BOTTOM_IO_PORT_A' in portmap.keys():
+        if 'BOTTOM_IO_PORT_A' in portmap:
             if not tt.has_wire(portmap['BOTTOM_IO_PORT_A']):
                 tt.create_wire(portmap['BOTTOM_IO_PORT_A'], "IO_I")
                 tt.create_wire(portmap['BOTTOM_IO_PORT_B'], "IO_I")
             tt.add_bel_pin(io, "BOTTOM_IO_PORT_A", portmap['BOTTOM_IO_PORT_A'], PinType.INPUT)
             tt.add_bel_pin(io, "BOTTOM_IO_PORT_B", portmap['BOTTOM_IO_PORT_B'], PinType.INPUT)
-
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    # create IOLOGIC bels if any
+    for idx, name in {(IOLOGICA_Z, 'IOLOGICA'), (IOLOGICA_Z + 1, 'IOLOGICB')}:
+        if name not in db.grid[y][x].bels:
+            continue
+        iol = tt.create_bel(name, "IOLOGIC", z = idx)
+        for port, wire in db.grid[y][x].bels[name].portmap.items():
+            if port == 'FCLK': # XXX compatibility
+                wire = f'FCLK{name[-1]}'
+            if not tt.has_wire(wire):
+                if port in {'CLK', 'PCLK'}:
+                    tt.create_wire(wire, "TILE_CLK")
+                else:
+                    tt.create_wire(wire, "IOL_PORT")
+            if port in {'Q', 'Q0', 'Q1', 'Q2', 'Q3', 'Q4', 'Q5', 'Q6', 'Q7', 'Q8', 'Q9', 'DF', 'LAG', 'LEAD'}:
+                tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
+            else:
+                tt.add_bel_pin(iol, port, wire, PinType.INPUT)
+    return (tiletype, tt)
 
 # logic: luts, dffs, alu etc
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     typename = "LOGIC"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     lut_inputs = ['A', 'B', 'C', 'D']
@@ -401,14 +457,11 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, "O",  f"OF7", PinType.OUTPUT)
     tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
 
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
 def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     # SSRAM is LUT based, so it's logic-like
-    ttyp, tt = create_logic_tiletype(chip, db, x, y, ttyp)
+    tiletype, tt = create_logic_tiletype(chip, db, x, y, ttyp)
 
     lut_inputs = ['A', 'B', 'C', 'D']
     ff = tt.create_bel(f"RAM16SDP4", "RAM16SDP4", z = RAMW_Z)
@@ -424,7 +477,7 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
     tt.add_bel_pin(ff, f"CE",  "CE2", PinType.INPUT)
     tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
 # PLL main tile
 _pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
@@ -435,10 +488,9 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
 _pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
 def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    if ttyp in created_tiletypes:
-        return ttyp, None
     typename = "PLL"
-    tt = chip.create_tile_type(f"{typename}_{ttyp}")
+    tiletype = f"{typename}_{ttyp}"
+    tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
     # wires
@@ -450,20 +502,16 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         bel_type = 'rPLL'
     portmap = db.grid[y][x].bels[pll_name].portmap
     pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
-    # Not sure how this will affect routing - PLLs are fixed and their outputs
-    # will be handled by a dedicated router
-    #pll.flags = BEL_FLAG_GLOBAL
+    pll.flags = BEL_FLAG_GLOBAL
     for pin, wire in portmap.items():
         if pin in _pll_inputs:
             tt.create_wire(wire, "PLL_I")
             tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
         else:
-            assert pin in _pll_outputs, f"Unknown PLL pin{pin}"
+            assert pin in _pll_outputs, f"Unknown PLL pin {pin}"
             tt.create_wire(wire, "PLL_O")
             tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
-
-    create_switch_matrix(tt, db, x, y)
-    return (ttyp, tt)
+    return (tiletype, tt)
 
 # pinouts, packages...
 _tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
@@ -508,6 +556,8 @@ def create_extra_data(chip: Chip, db: chipdb):
     chip.extra_data.create_bottom_io()
     for net_a, net_b in db.bottom_io[2]:
         chip.extra_data.add_bottom_io_cnd(net_a, net_b)
+    for diff_type in db.diff_io_types:
+        chip.extra_data.add_diff_io_type(diff_type)
 
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
@@ -536,43 +586,30 @@ def main():
     # different routing or something like that).
     logic_tiletypes = db.tile_types['C']
     io_tiletypes = db.tile_types['I']
-    ssram_tiletypes = {17, 18, 19}
+    ssram_tiletypes = db.tile_types['M']
     gsr_tiletypes = {1}
     pll_tiletypes = db.tile_types['P']
+
     # Setup tile grid
     for x in range(X):
         for y in range(Y):
             ttyp = db.grid[y][x].ttyp
             if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
                 assert ttyp not in created_tiletypes, "Duplication of corner types"
-                ttyp, _ = create_corner_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"CORNER_{ttyp}")
+                create_tiletype(create_corner_tiletype, ch, db, x, y, ttyp)
                 continue
             if ttyp in gsr_tiletypes:
-                ttyp, _ = create_gsr_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"GSR_{ttyp}")
+                create_tiletype(create_gsr_tiletype, ch, db, x, y, ttyp)
             elif ttyp in logic_tiletypes:
-                ttyp, _ = create_logic_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
+                create_tiletype(create_logic_tiletype, ch, db, x, y, ttyp)
             elif ttyp in ssram_tiletypes:
-                ttyp, _ = create_ssram_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
+                create_tiletype(create_ssram_tiletype, ch, db, x, y, ttyp)
             elif ttyp in io_tiletypes:
-                ttyp, _ = create_io_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"IO_{ttyp}")
+                create_tiletype(create_io_tiletype, ch, db, x, y, ttyp)
             elif ttyp in pll_tiletypes:
-                ttyp, _ = create_pll_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"PLL_{ttyp}")
+                create_tiletype(create_pll_tiletype, ch, db, x, y, ttyp)
             else:
-                ttyp, _ = create_null_tiletype(ch, db, x, y, ttyp)
-                created_tiletypes.add(ttyp)
-                ch.set_tile_type(x, y, f"NULL_{ttyp}")
+                create_tiletype(create_null_tiletype, ch, db, x, y, ttyp)
 
     # Create nodes between tiles
     create_nodes(ch, db)
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index cd79f31981..922134b09d 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1,3 +1,4 @@
+#include "design_utils.h"
 #include "log.h"
 #include "nextpnr.h"
 
@@ -21,18 +22,39 @@ struct GowinPacker
     // ===================================
     // IO
     // ===================================
+    // create IOB connections for gowin_pack
+    // can be called repeatedly when switching inputs, disabled outputs do not change
+    void make_iob_nets(CellInfo &iob)
+    {
+        for (const auto &port : iob.ports) {
+            const NetInfo *net = iob.getPort(port.first);
+            std::string connected_net = "NET";
+            if (net != nullptr) {
+                if (ctx->verbose) {
+                    log_info("%s: %s - %s\n", ctx->nameOf(&iob), port.first.c_str(ctx), ctx->nameOf(net));
+                }
+                if (net->name == ctx->id("$PACKER_VCC")) {
+                    connected_net = "VCC";
+                } else if (net->name == ctx->id("$PACKER_GND")) {
+                    connected_net = "GND";
+                }
+                iob.setParam(ctx->idf("NET_%s", port.first.c_str(ctx)), connected_net);
+            }
+        }
+    }
+
     void config_simple_io(CellInfo &ci)
     {
         if (ci.type.in(id_TBUF, id_IOBUF)) {
             return;
         }
         log_info("simple:%s\n", ctx->nameOf(&ci));
-        ci.addInput(id_OE);
+        ci.addInput(id_OEN);
         if (ci.type == id_OBUF) {
-            ci.connectPort(id_OE, ctx->nets[ctx->id("$PACKER_GND")].get());
+            ci.connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_GND")].get());
         } else {
             NPNR_ASSERT(ci.type == id_IBUF);
-            ci.connectPort(id_OE, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            ci.connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_VCC")].get());
         }
     }
 
@@ -44,7 +66,7 @@ struct GowinPacker
         if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
             return;
         }
-        if (cnd == Bottom_io_POD::NORMAL && loc.z != BelZ::IOBA_Z) {
+        if (loc.z != BelZ::IOBA_Z) {
             return;
         }
         auto connect_io_wire = [&](IdString port, IdString net_name) {
@@ -60,6 +82,7 @@ struct GowinPacker
             }
         };
 
+        log_info("cnd:%d\n", cnd);
         IdString wire_a_net = get_bottom_io_wire_a_net(ctx->chip_info, cnd);
         connect_io_wire(id_BOTTOM_IO_PORT_A, wire_a_net);
 
@@ -74,6 +97,8 @@ struct GowinPacker
         const pool<CellTypePort> top_ports{
                 CellTypePort(id_IBUF, id_I),
                 CellTypePort(id_OBUF, id_O),
+                CellTypePort(id_TBUF, id_O),
+                CellTypePort(id_IOBUF, id_IO),
         };
         std::vector<IdString> to_remove;
         for (auto &cell : ctx->cells) {
@@ -100,8 +125,18 @@ struct GowinPacker
                     }
                 }
             }
+            NetInfo *io = ci.getPort(ctx->id("IO"));
+            if (io && io->driver.cell) {
+                if (!top_ports.count(CellTypePort(io->driver)))
+                    log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
+                              ctx->nameOf(io->driver.cell), ctx->nameOf(io->driver.port));
+                for (const auto &attr : ci.attrs) {
+                    io->driver.cell->attrs[attr.first] = attr.second;
+                }
+            }
             ci.disconnectPort(ctx->id("I"));
             ci.disconnectPort(ctx->id("O"));
+            ci.disconnectPort(ctx->id("IO"));
             to_remove.push_back(ci.name);
         }
         for (IdString cell_name : to_remove)
@@ -124,7 +159,7 @@ struct GowinPacker
 
         for (auto &cell : ctx->cells) {
             CellInfo &ci = *cell.second;
-            if (!ci.type.in(id_IBUF, id_OBUF, id_IOBUF)) // XXX TBUF
+            if (!ci.type.in(id_IBUF, id_OBUF, id_TBUF, id_IOBUF))
                 continue;
             if (ci.attrs.count(id_BEL) == 0) {
                 log_error("Unconstrained IO:%s\n", ctx->nameOf(&ci));
@@ -134,9 +169,242 @@ struct GowinPacker
             if (io_loc.y == ctx->getGridDimY() - 1) {
                 config_bottom_row(ci, io_loc);
             }
-            if (getBelSimpleIO(ctx->chip_info, io_bel)) {
+            if (is_simple_io_bel(ctx->chip_info, io_bel)) {
                 config_simple_io(ci);
             }
+            make_iob_nets(ci);
+        }
+    }
+
+    // ===================================
+    // Differential IO
+    // ===================================
+    static bool is_iob(const Context *ctx, CellInfo *cell)
+    {
+        return (cell->type.in(id_IBUF, id_OBUF, id_TBUF, id_IOBUF));
+    }
+
+    std::pair<CellInfo *, CellInfo *> get_pn_cells(const CellInfo &ci)
+    {
+        CellInfo *p, *n;
+        switch (ci.type.hash()) {
+        case ID_ELVDS_TBUF: /* fall-through */
+        case ID_TLVDS_TBUF: /* fall-through */
+        case ID_ELVDS_OBUF: /* fall-through */
+        case ID_TLVDS_OBUF:
+            p = net_only_drives(ctx, ci.ports.at(id_O).net, is_iob, id_I, true);
+            n = net_only_drives(ctx, ci.ports.at(id_OB).net, is_iob, id_I, true);
+            break;
+        case ID_ELVDS_IBUF: /* fall-through */
+        case ID_TLVDS_IBUF:
+            p = net_driven_by(ctx, ci.ports.at(id_I).net, is_iob, id_O);
+            n = net_driven_by(ctx, ci.ports.at(id_IB).net, is_iob, id_O);
+            break;
+        case ID_ELVDS_IOBUF: /* fall-through */
+        case ID_TLVDS_IOBUF:
+            p = net_only_drives(ctx, ci.ports.at(id_IO).net, is_iob, id_I);
+            n = net_only_drives(ctx, ci.ports.at(id_IOB).net, is_iob, id_I);
+            break;
+        default:
+            log_error("Bad diff IO '%s' type '%s'\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+        }
+        return std::make_pair(p, n);
+    }
+
+    void mark_iobs_as_diff(CellInfo &ci, std::pair<CellInfo *, CellInfo *> &pn_cells)
+    {
+        pn_cells.first->setParam(id_DIFF, std::string("P"));
+        pn_cells.first->setParam(id_DIFF_TYPE, ci.type.str(ctx));
+        pn_cells.second->setParam(id_DIFF, std::string("N"));
+        pn_cells.second->setParam(id_DIFF_TYPE, ci.type.str(ctx));
+    }
+
+    void switch_diff_ports(CellInfo &ci, std::pair<CellInfo *, CellInfo *> &pn_cells,
+                           std::vector<IdString> &nets_to_remove)
+    {
+        CellInfo *iob_p = pn_cells.first;
+        CellInfo *iob_n = pn_cells.second;
+
+        if (ci.type.in(id_TLVDS_TBUF, id_TLVDS_OBUF, id_ELVDS_TBUF, id_ELVDS_OBUF)) {
+            nets_to_remove.push_back(ci.getPort(id_O)->name);
+            ci.disconnectPort(id_O);
+            nets_to_remove.push_back(ci.getPort(id_OB)->name);
+            ci.disconnectPort(id_OB);
+            nets_to_remove.push_back(iob_n->getPort(id_I)->name);
+            iob_n->disconnectPort(id_I);
+
+            if (ci.type.in(id_TLVDS_TBUF, id_ELVDS_TBUF)) {
+                nets_to_remove.push_back(iob_n->getPort(id_OEN)->name);
+                iob_n->disconnectPort(id_OEN);
+                iob_p->disconnectPort(id_OEN);
+                ci.movePortTo(id_OEN, iob_p, id_OEN);
+            }
+            iob_p->disconnectPort(id_I);
+            ci.movePortTo(id_I, iob_p, id_I);
+            return;
+        }
+        if (ci.type.in(id_TLVDS_IBUF, id_ELVDS_IBUF)) {
+            nets_to_remove.push_back(ci.getPort(id_I)->name);
+            ci.disconnectPort(id_I);
+            nets_to_remove.push_back(ci.getPort(id_IB)->name);
+            ci.disconnectPort(id_IB);
+            iob_n->disconnectPort(id_O);
+            iob_p->disconnectPort(id_O);
+            ci.movePortTo(id_O, iob_p, id_O);
+            return;
+        }
+        if (ci.type.in(id_TLVDS_IOBUF, id_ELVDS_IOBUF)) {
+            nets_to_remove.push_back(ci.getPort(id_IO)->name);
+            ci.disconnectPort(id_IO);
+            nets_to_remove.push_back(ci.getPort(id_IOB)->name);
+            ci.disconnectPort(id_IOB);
+            nets_to_remove.push_back(iob_n->getPort(id_I)->name);
+            iob_n->disconnectPort(id_I);
+            iob_n->disconnectPort(id_OEN);
+
+            iob_p->disconnectPort(id_OEN);
+            ci.movePortTo(id_OEN, iob_p, id_OEN);
+            iob_p->disconnectPort(id_I);
+            ci.movePortTo(id_I, iob_p, id_I);
+            iob_p->disconnectPort(id_O);
+            ci.movePortTo(id_O, iob_p, id_O);
+            return;
+        }
+    }
+
+    void pack_diff_iobs(void)
+    {
+        log_info("Pack diff IOBs...\n");
+        std::vector<IdString> cells_to_remove, nets_to_remove;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (!is_diffio(&ci)) {
+                continue;
+            }
+            if (!is_diff_io_supported(ctx->chip_info, ci.type)) {
+                log_error("%s is not supported\n", ci.type.c_str(ctx));
+            }
+            cells_to_remove.push_back(ci.name);
+            auto pn_cells = get_pn_cells(ci);
+            NPNR_ASSERT(pn_cells.first != nullptr && pn_cells.second != nullptr);
+
+            mark_iobs_as_diff(ci, pn_cells);
+            switch_diff_ports(ci, pn_cells, nets_to_remove);
+        }
+
+        for (auto cell : cells_to_remove) {
+            ctx->cells.erase(cell);
+        }
+        for (auto net : nets_to_remove) {
+            ctx->nets.erase(net);
+        }
+    }
+
+    // ===================================
+    // IO logic
+    // ===================================
+    // the functions of these two inputs are yet to be discovered, so we set as observed
+    // in the exemplary images
+    void set_daaj_nets(CellInfo &ci, BelId bel)
+    {
+        std::vector<IdString> pins = ctx->getBelPins(bel);
+        if (std::find(pins.begin(), pins.end(), id_DAADJ0) != pins.end()) {
+            ci.addInput(id_DAADJ0);
+            ci.connectPort(id_DAADJ0, ctx->nets[ctx->id("$PACKER_GND")].get());
+        }
+        if (std::find(pins.begin(), pins.end(), id_DAADJ1) != pins.end()) {
+            ci.addInput(id_DAADJ1);
+            ci.connectPort(id_DAADJ1, ctx->nets[ctx->id("$PACKER_VCC")].get());
+        }
+    }
+
+    BelId get_iologic_bel(CellInfo *iob)
+    {
+        NPNR_ASSERT(iob->bel != BelId());
+        Loc loc = ctx->getBelLocation(iob->bel);
+        loc.z = loc.z - BelZ::IOBA_Z + BelZ::IOLOGICA_Z;
+        return ctx->getBelByLocation(loc);
+    }
+
+    void pack_bi_output_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove, std::vector<IdString> &nets_to_remove)
+    {
+        // These primitives have an additional pin to control the tri-state iob - Q1.
+        IdString out_port = id_Q0;
+        IdString tx_port = id_Q1;
+
+        CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(out_port).net, is_iob, id_I);
+        NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
+        BelId iob_bel = out_iob->bel;
+
+        BelId l_bel = get_iologic_bel(out_iob);
+        if (l_bel == BelId()) {
+            log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
+        }
+
+        if (!ctx->checkBelAvail(l_bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
+                      ctx->nameOfBel(l_bel), ctx->nameOf(ctx->getBoundBelCell(l_bel)));
+        }
+        ctx->bindBel(l_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+        std::string out_mode;
+        switch (ci.type.hash()) {
+        case ID_ODDR:
+        case ID_ODDRC:
+            out_mode = "ODDRX1";
+            break;
+        case ID_OSER4:
+            out_mode = "ODDRX2";
+            break;
+        case ID_OSER8:
+            out_mode = "ODDRX4";
+            break;
+        }
+        ci.setParam(ctx->id("OUTMODE"), out_mode);
+
+        // mark IOB as used by IOLOGIC
+        out_iob->setParam(id_IOLOGIC_IOB, 1);
+        // disconnect Q output: it is wired internally
+        nets_to_remove.push_back(ci.getPort(out_port)->name);
+        out_iob->disconnectPort(id_I);
+        ci.disconnectPort(out_port);
+        set_daaj_nets(ci, iob_bel);
+        config_bottom_row(*out_iob, ctx->getBelLocation(iob_bel), Bottom_io_POD::DDR);
+
+        // if Q1 is connected then disconnect it too
+        if (port_used(&ci, tx_port)) {
+            NPNR_ASSERT(out_iob == net_only_drives(ctx, ci.ports.at(tx_port).net, is_iob, id_OEN));
+            nets_to_remove.push_back(ci.getPort(tx_port)->name);
+            out_iob->disconnectPort(id_OEN);
+            ci.disconnectPort(tx_port);
+        }
+        make_iob_nets(*out_iob);
+    }
+
+    void pack_iologic()
+    {
+        log_info("Pack IO logic...\n");
+        std::vector<IdString> cells_to_remove, nets_to_remove;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (!is_iologic(&ci)) {
+                continue;
+            }
+            if (ctx->debug) {
+                log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+            }
+            if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8)) {
+                pack_bi_output_iol(ci, cells_to_remove, nets_to_remove);
+                continue;
+            }
+        }
+
+        for (auto cell : cells_to_remove) {
+            ctx->cells.erase(cell);
+        }
+        for (auto net : nets_to_remove) {
+            ctx->nets.erase(net);
         }
     }
 
@@ -656,12 +924,17 @@ struct GowinPacker
     {
         handle_constants();
         pack_iobs();
+        pack_diff_iobs();
+        pack_iologic();
         pack_gsr();
         pack_wideluts();
         pack_alus();
         constrain_lutffs();
         pack_pll();
         pack_ram16sdp4();
+
+        ctx->fixupHierarchy();
+        ctx->check();
     }
 };
 } // namespace

From dfb701b5abe3d576d4410ee2a016d26c7dbe54c4 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 7 Aug 2023 18:20:08 +1000
Subject: [PATCH 448/712] gowin: Himbaechel. Add OSER8

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc |  1 +
 himbaechel/uarch/gowin/gowin.cc     | 10 +++---
 himbaechel/uarch/gowin/gowin.h      | 54 ++++++++++++++++-------------
 himbaechel/uarch/gowin/pack.cc      | 37 ++++++++++++++++++--
 4 files changed, 70 insertions(+), 32 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 883961edc4..ec5116ba56 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1062,6 +1062,7 @@ X(GOWIN_VCC)
 X(PLL)
 X(BOTTOM_IO_PORT_A)
 X(BOTTOM_IO_PORT_B)
+X(IOLOGIC_DUMMY)
 
 // wire types
 X(GLOBAL_CLK)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index cebefa89a2..538dc2940d 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -185,7 +185,7 @@ void GowinImpl::postRoute()
                 ci->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
                 const NetInfo *h_net = ci->getPort(id_FCLK);
                 if (h_net) {
-                    for (auto const &user : h_net->users) {
+                    for (auto &user : h_net->users) {
                         if (user.port != id_FCLK) {
                             continue;
                         }
@@ -195,7 +195,7 @@ void GowinImpl::postRoute()
                         PipId up_pip = h_net->wires.at(ctx->getNetinfoSinkWire(h_net, user, 0)).pip;
                         IdString up_wire_name = ctx->getWireName(ctx->getPipSrcWire(up_pip))[1];
                         if (up_wire_name.in(id_HCLK_OUT0, id_HCLK_OUT1, id_HCLK_OUT2, id_HCLK_OUT3)) {
-                            ci->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
+                            user.cell->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
                         }
                         if (ctx->debug) {
                             log_info("HCLK user cell:%s, port:%s, wire:%s, pip:%s, up wire:%s\n",
@@ -402,8 +402,7 @@ void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
         // OSER8 took both IOLOGIC bels in the tile
         if (cell->type == id_OSER8) {
             Loc loc = ctx->getBelLocation(bel);
-            loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
-            inactive_bels.insert(ctx->getBelByLocation(loc));
+            inactive_bels.insert(ctx->getBelByLocation(get_pair_iologic_bel(loc)));
         }
     } else {
         // the unbind is about to happen
@@ -411,8 +410,7 @@ void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
         // OSER8 took both IOLOGIC bels in the tile
         if (ci->type == id_OSER8) {
             Loc loc = ctx->getBelLocation(bel);
-            loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
-            inactive_bels.erase(ctx->getBelByLocation(loc));
+            inactive_bels.erase(ctx->getBelByLocation(get_pair_iologic_bel(loc)));
         }
     }
 }
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 4051b0754a..66da2d4ed1 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -5,6 +5,31 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
+namespace BelZ {
+enum
+{
+    LUT0_Z = 0,
+    LUT7_Z = 14,
+    MUX20_Z = 16,
+    MUX21_Z = 18,
+    MUX23_Z = 22,
+    MUX27_Z = 29,
+    ALU0_Z = 30, // :35, 6 ALU
+    RAMW_Z = 36, // RAM16SDP4
+
+    IOBA_Z = 50,
+    IOBB_Z = 51, // +IOBC...IOBL
+
+    IOLOGICA_Z = 70,
+
+    PLL_Z = 275,
+    GSR_Z = 276,
+    VCC_Z = 277,
+    VSS_Z = 278
+};
+}
+
 namespace BelFlags {
 static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
 }
@@ -93,32 +118,13 @@ inline bool is_simple_io_bel(const ChipInfoPOD *chip, BelId bel)
     return chip_bel_info(chip, bel).flags & BelFlags::FLAG_SIMPLE_IO;
 }
 
-} // namespace
-
-// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
-namespace BelZ {
-enum
+inline Loc get_pair_iologic_bel(Loc loc)
 {
-    LUT0_Z = 0,
-    LUT7_Z = 14,
-    MUX20_Z = 16,
-    MUX21_Z = 18,
-    MUX23_Z = 22,
-    MUX27_Z = 29,
-    ALU0_Z = 30, // :35, 6 ALU
-    RAMW_Z = 36, // RAM16SDP4
-
-    IOBA_Z = 50,
-    IOBB_Z = 51, // +IOBC...IOBL
-
-    IOLOGICA_Z = 70,
-
-    PLL_Z = 275,
-    GSR_Z = 276,
-    VCC_Z = 277,
-    VSS_Z = 278
-};
+    loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
+    return loc;
 }
 
+} // namespace
+
 NEXTPNR_NAMESPACE_END
 #endif
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 922134b09d..f6d6f07fbf 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -82,7 +82,6 @@ struct GowinPacker
             }
         };
 
-        log_info("cnd:%d\n", cnd);
         IdString wire_a_net = get_bottom_io_wire_a_net(ctx->chip_info, cnd);
         connect_io_wire(id_BOTTOM_IO_PORT_A, wire_a_net);
 
@@ -381,6 +380,40 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
+    IdString create_aux_iologic_name(IdString main_name, int idx = 0)
+    {
+        std::string sfx("");
+        if (idx) {
+            sfx = std::to_string(idx);
+        }
+        return ctx->id(main_name.str(ctx) + std::string("_aux") + sfx);
+    }
+
+    BelId get_aux_iologic_bel(const CellInfo &ci)
+    {
+        return ctx->getBelByLocation(get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
+    }
+
+    void create_aux_iologic_cells(CellInfo &ci)
+    {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4)) {
+            return;
+        }
+        IdString aux_name = create_aux_iologic_name(ci.name);
+        BelId bel = get_aux_iologic_bel(ci);
+        ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
+        CellInfo *aux = ctx->cells[aux_name].get();
+        aux->addInput(id_PCLK);
+        ci.copyPortTo(id_PCLK, ctx->cells.at(aux_name).get(), id_PCLK);
+        aux->addInput(id_FCLK);
+        ci.copyPortTo(id_FCLK, ctx->cells.at(aux_name).get(), id_FCLK);
+        aux->addInput(id_RESET);
+        ci.copyPortTo(id_RESET, ctx->cells.at(aux_name).get(), id_RESET);
+        ctx->cells.at(aux_name)->setParam(ctx->id("OUTMODE"), Property("DDRENABLE"));
+        ctx->cells.at(aux_name)->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ctx->bindBel(bel, aux, PlaceStrength::STRENGTH_LOCKED);
+    }
+
     void pack_iologic()
     {
         log_info("Pack IO logic...\n");
@@ -396,6 +429,7 @@ struct GowinPacker
             }
             if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8)) {
                 pack_bi_output_iol(ci, cells_to_remove, nets_to_remove);
+                create_aux_iologic_cells(ci);
                 continue;
             }
         }
@@ -407,7 +441,6 @@ struct GowinPacker
             ctx->nets.erase(net);
         }
     }
-
     // ===================================
     // Constant nets
     // ===================================

From 3a073540c26e9df7c13d5ccf95d8b409c65dab57 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 8 Aug 2023 10:57:45 +1000
Subject: [PATCH 449/712] gowin: Himbaechel. Add OSER10 and OVIDEO

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc   |   1 +
 himbaechel/uarch/gowin/globals.cc     |   4 +-
 himbaechel/uarch/gowin/gowin.cc       |  27 +------
 himbaechel/uarch/gowin/gowin.h        |  90 ++++++---------------
 himbaechel/uarch/gowin/gowin_utils.cc |  55 ++++++++++++-
 himbaechel/uarch/gowin/gowin_utils.h  |  14 ++++
 himbaechel/uarch/gowin/pack.cc        | 109 +++++++++++++++++++++++---
 7 files changed, 192 insertions(+), 108 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index ec5116ba56..d9a7ca2bec 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1091,6 +1091,7 @@ X(XD4)
 X(XD5)
 
 // HCLK wires
+X(HCLK)
 X(HCLK_OUT0)
 X(HCLK_OUT1)
 X(HCLK_OUT2)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 365924fc19..0a9ca691e0 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -49,8 +49,8 @@ struct GowinGlobalRouter
 
         IdString src_type = ctx->getWireType(ctx->getPipSrcWire(pip));
         IdString dst_type = ctx->getWireType(ctx->getPipDstWire(pip));
-        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O);
-        bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I);
+        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
+        bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
 
         bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
         if (ctx->debug && res && false) {
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 538dc2940d..2ff3555ff0 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -38,10 +38,6 @@ struct GowinImpl : HimbaechelAPI
 
     bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
 
-    // placer hits
-    void notifyBelChange(BelId bel, CellInfo *cell) override;
-    bool checkBelAvail(BelId bel) const override;
-
   private:
     HimbaechelHelpers h;
     GowinUtils gwu;
@@ -182,13 +178,13 @@ void GowinImpl::postRoute()
         if (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC)) {
             if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
                 // mark FCLK<-HCLK connections
-                ci->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
                 const NetInfo *h_net = ci->getPort(id_FCLK);
                 if (h_net) {
                     for (auto &user : h_net->users) {
                         if (user.port != id_FCLK) {
                             continue;
                         }
+                        user.cell->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
                         visited_hclk_users.insert(user.cell->name);
                         // XXX Based on the implementation, perhaps a function
                         // is needed to get Pip from a Wire
@@ -395,27 +391,6 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     }
     return true;
 }
-// placer hits
-void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
-{
-    if (cell != nullptr) {
-        // OSER8 took both IOLOGIC bels in the tile
-        if (cell->type == id_OSER8) {
-            Loc loc = ctx->getBelLocation(bel);
-            inactive_bels.insert(ctx->getBelByLocation(get_pair_iologic_bel(loc)));
-        }
-    } else {
-        // the unbind is about to happen
-        CellInfo *ci = ctx->getBoundBelCell(bel);
-        // OSER8 took both IOLOGIC bels in the tile
-        if (ci->type == id_OSER8) {
-            Loc loc = ctx->getBelLocation(bel);
-            inactive_bels.erase(ctx->getBelByLocation(get_pair_iologic_bel(loc)));
-        }
-    }
-}
-
-bool GowinImpl::checkBelAvail(BelId bel) const { return inactive_bels.find(bel) == inactive_bels.end(); }
 
 } // namespace
 
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 66da2d4ed1..233fc2ed0f 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -5,35 +5,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
-namespace BelZ {
-enum
-{
-    LUT0_Z = 0,
-    LUT7_Z = 14,
-    MUX20_Z = 16,
-    MUX21_Z = 18,
-    MUX23_Z = 22,
-    MUX27_Z = 29,
-    ALU0_Z = 30, // :35, 6 ALU
-    RAMW_Z = 36, // RAM16SDP4
-
-    IOBA_Z = 50,
-    IOBB_Z = 51, // +IOBC...IOBL
-
-    IOLOGICA_Z = 70,
-
-    PLL_Z = 275,
-    GSR_Z = 276,
-    VCC_Z = 277,
-    VSS_Z = 278
-};
-}
-
-namespace BelFlags {
-static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
-}
-
 namespace {
 // Return true if a cell is a LUT
 inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
@@ -57,7 +28,10 @@ inline bool type_is_diffio(IdString cell_type)
 }
 inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type); }
 
-inline bool type_is_iologic(IdString cell_type) { return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8); }
+inline bool type_is_iologic(IdString cell_type)
+{
+    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO);
+}
 inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type); }
 
 // Return true if a cell is a SSRAM
@@ -83,48 +57,32 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     RelSlice<IdString> diff_io_types;
 });
 
-inline bool is_diff_io_supported(const ChipInfoPOD *chip, IdString type)
-{
-    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
-    for (auto &dtype : extra->diff_io_types) {
-        if (IdString(dtype) == type) {
-            return true;
-        }
-    }
-    return false;
-}
-
-inline bool have_bottom_io_cnds(const ChipInfoPOD *chip)
-{
-    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
-    return extra->bottom_io.conditions.size() != 0;
-}
+} // namespace
 
-inline IdString get_bottom_io_wire_a_net(const ChipInfoPOD *chip, int8_t condition)
+// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
+namespace BelZ {
+enum
 {
-    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
-    return IdString(extra->bottom_io.conditions[condition].wire_a_net);
-}
+    LUT0_Z = 0,
+    LUT7_Z = 14,
+    MUX20_Z = 16,
+    MUX21_Z = 18,
+    MUX23_Z = 22,
+    MUX27_Z = 29,
+    ALU0_Z = 30, // :35, 6 ALU
+    RAMW_Z = 36, // RAM16SDP4
 
-inline IdString get_bottom_io_wire_b_net(const ChipInfoPOD *chip, int8_t condition)
-{
-    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
-    return IdString(extra->bottom_io.conditions[condition].wire_b_net);
-}
+    IOBA_Z = 50,
+    IOBB_Z = 51, // +IOBC...IOBL
 
-// Bels and pips
-inline bool is_simple_io_bel(const ChipInfoPOD *chip, BelId bel)
-{
-    return chip_bel_info(chip, bel).flags & BelFlags::FLAG_SIMPLE_IO;
-}
+    IOLOGICA_Z = 70,
 
-inline Loc get_pair_iologic_bel(Loc loc)
-{
-    loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
-    return loc;
+    PLL_Z = 275,
+    GSR_Z = 276,
+    VCC_Z = 277,
+    VSS_Z = 278
+};
 }
 
-} // namespace
-
 NEXTPNR_NAMESPACE_END
 #endif
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 7cc82fed1e..3c23be50e6 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -1,9 +1,14 @@
-#include "gowin_utils.h"
-
 #include "log.h"
 #include "nextpnr.h"
 #include "util.h"
 
+#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
+#include "himbaechel_constids.h"
+#include "himbaechel_helpers.h"
+
+#include "gowin.h"
+#include "gowin_utils.h"
+
 NEXTPNR_NAMESPACE_BEGIN
 
 // pin functions: GCLKT_4, SSPI_CS, READY etc
@@ -22,4 +27,50 @@ IdStringList GowinUtils::get_pin_funcs(BelId bel)
     return IdStringList();
 }
 
+bool GowinUtils::is_simple_io_bel(BelId bel)
+{
+    return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
+}
+
+Loc GowinUtils::get_pair_iologic_bel(Loc loc)
+{
+    loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
+    return loc;
+}
+
+BelId GowinUtils::get_io_bel_from_iologic(BelId bel)
+{
+    Loc loc = ctx->getBelLocation(bel);
+    loc.z = BelZ::IOBA_Z + loc.z - BelZ::IOLOGICA_Z;
+    return ctx->getBelByLocation(loc);
+}
+
+bool GowinUtils::is_diff_io_supported(IdString type)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    for (auto &dtype : extra->diff_io_types) {
+        if (IdString(dtype) == type) {
+            return true;
+        }
+    }
+    return false;
+}
+
+bool GowinUtils::have_bottom_io_cnds(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->bottom_io.conditions.size() != 0;
+}
+
+IdString GowinUtils::get_bottom_io_wire_a_net(int8_t condition)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return IdString(extra->bottom_io.conditions[condition].wire_a_net);
+}
+
+IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return IdString(extra->bottom_io.conditions[condition].wire_b_net);
+}
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index ba5b738955..5d544a7400 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -7,6 +7,10 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+namespace BelFlags {
+static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
+}
+
 struct GowinUtils
 {
     Context *ctx;
@@ -17,6 +21,16 @@ struct GowinUtils
 
     // pin functions: GCLKT_4, SSPI_CS, READY etc
     IdStringList get_pin_funcs(BelId bel);
+
+    // Bels and pips
+    bool is_simple_io_bel(BelId bel);
+    Loc get_pair_iologic_bel(Loc loc);
+    BelId get_io_bel_from_iologic(BelId bel);
+
+    bool is_diff_io_supported(IdString type);
+    bool have_bottom_io_cnds(void);
+    IdString get_bottom_io_wire_a_net(int8_t condition);
+    IdString get_bottom_io_wire_b_net(int8_t condition);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index f6d6f07fbf..064d3e3a98 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -7,6 +7,7 @@
 #include "himbaechel_helpers.h"
 
 #include "gowin.h"
+#include "gowin_utils.h"
 #include "pack.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -16,8 +17,13 @@ struct GowinPacker
 {
     Context *ctx;
     HimbaechelHelpers h;
+    GowinUtils gwu;
 
-    GowinPacker(Context *ctx) : ctx(ctx) { h.init(ctx); }
+    GowinPacker(Context *ctx) : ctx(ctx)
+    {
+        h.init(ctx);
+        gwu.init(ctx);
+    }
 
     // ===================================
     // IO
@@ -60,7 +66,7 @@ struct GowinPacker
 
     void config_bottom_row(CellInfo &ci, Loc loc, uint8_t cnd = Bottom_io_POD::NORMAL)
     {
-        if (!have_bottom_io_cnds(ctx->chip_info)) {
+        if (!gwu.have_bottom_io_cnds()) {
             return;
         }
         if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
@@ -82,10 +88,10 @@ struct GowinPacker
             }
         };
 
-        IdString wire_a_net = get_bottom_io_wire_a_net(ctx->chip_info, cnd);
+        IdString wire_a_net = gwu.get_bottom_io_wire_a_net(cnd);
         connect_io_wire(id_BOTTOM_IO_PORT_A, wire_a_net);
 
-        IdString wire_b_net = get_bottom_io_wire_b_net(ctx->chip_info, cnd);
+        IdString wire_b_net = gwu.get_bottom_io_wire_b_net(cnd);
         connect_io_wire(id_BOTTOM_IO_PORT_B, wire_b_net);
     }
 
@@ -168,7 +174,7 @@ struct GowinPacker
             if (io_loc.y == ctx->getGridDimY() - 1) {
                 config_bottom_row(ci, io_loc);
             }
-            if (is_simple_io_bel(ctx->chip_info, io_bel)) {
+            if (gwu.is_simple_io_bel(io_bel)) {
                 config_simple_io(ci);
             }
             make_iob_nets(ci);
@@ -281,7 +287,7 @@ struct GowinPacker
             if (!is_diffio(&ci)) {
                 continue;
             }
-            if (!is_diff_io_supported(ctx->chip_info, ci.type)) {
+            if (!gwu.is_diff_io_supported(ci.type)) {
                 log_error("%s is not supported\n", ci.type.c_str(ctx));
             }
             cells_to_remove.push_back(ci.name);
@@ -332,7 +338,7 @@ struct GowinPacker
         IdString out_port = id_Q0;
         IdString tx_port = id_Q1;
 
-        CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(out_port).net, is_iob, id_I);
+        CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(out_port).net, is_iob, id_I, true);
         NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
         BelId iob_bel = out_iob->bel;
 
@@ -368,11 +374,15 @@ struct GowinPacker
         out_iob->disconnectPort(id_I);
         ci.disconnectPort(out_port);
         set_daaj_nets(ci, iob_bel);
-        config_bottom_row(*out_iob, ctx->getBelLocation(iob_bel), Bottom_io_POD::DDR);
+
+        Loc io_loc = ctx->getBelLocation(iob_bel);
+        if (io_loc.y == ctx->getGridDimY() - 1) {
+            config_bottom_row(*out_iob, io_loc, Bottom_io_POD::DDR);
+        }
 
         // if Q1 is connected then disconnect it too
         if (port_used(&ci, tx_port)) {
-            NPNR_ASSERT(out_iob == net_only_drives(ctx, ci.ports.at(tx_port).net, is_iob, id_OEN));
+            NPNR_ASSERT(out_iob == net_only_drives(ctx, ci.ports.at(tx_port).net, is_iob, id_OEN, true));
             nets_to_remove.push_back(ci.getPort(tx_port)->name);
             out_iob->disconnectPort(id_OEN);
             ci.disconnectPort(tx_port);
@@ -380,6 +390,51 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
+    void pack_single_output_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove,
+                                std::vector<IdString> &nets_to_remove)
+    {
+        IdString out_port = id_Q;
+
+        CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(out_port).net, is_iob, id_I, true);
+        NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
+        BelId iob_bel = out_iob->bel;
+
+        BelId l_bel = get_iologic_bel(out_iob);
+        if (l_bel == BelId()) {
+            log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
+        }
+
+        if (!ctx->checkBelAvail(l_bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
+                      ctx->nameOfBel(l_bel), ctx->nameOf(ctx->getBoundBelCell(l_bel)));
+        }
+        ctx->bindBel(l_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+        std::string out_mode;
+        switch (ci.type.hash()) {
+        case ID_OVIDEO:
+            out_mode = "VIDEORX";
+            break;
+        case ID_OSER10:
+            out_mode = "ODDRX5";
+            break;
+        }
+        ci.setParam(ctx->id("OUTMODE"), out_mode);
+
+        // mark IOB as used by IOLOGIC
+        out_iob->setParam(id_IOLOGIC_IOB, 1);
+        // disconnect Q output: it is wired internally
+        nets_to_remove.push_back(ci.getPort(out_port)->name);
+        out_iob->disconnectPort(id_I);
+        ci.disconnectPort(out_port);
+        set_daaj_nets(ci, iob_bel);
+
+        Loc io_loc = ctx->getBelLocation(iob_bel);
+        if (io_loc.y == ctx->getGridDimY() - 1) {
+            config_bottom_row(*out_iob, io_loc, Bottom_io_POD::DDR);
+        }
+        make_iob_nets(*out_iob);
+    }
+
     IdString create_aux_iologic_name(IdString main_name, int idx = 0)
     {
         std::string sfx("");
@@ -391,9 +446,11 @@ struct GowinPacker
 
     BelId get_aux_iologic_bel(const CellInfo &ci)
     {
-        return ctx->getBelByLocation(get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
+        return ctx->getBelByLocation(gwu.get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
     }
 
+    bool is_diff_io(BelId bel) { return ctx->getBoundBelCell(bel)->attrs.count(id_DIFF_TYPE) != 0; }
+
     void create_aux_iologic_cells(CellInfo &ci)
     {
         if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4)) {
@@ -401,16 +458,23 @@ struct GowinPacker
         }
         IdString aux_name = create_aux_iologic_name(ci.name);
         BelId bel = get_aux_iologic_bel(ci);
+        BelId io_bel = gwu.get_io_bel_from_iologic(bel);
+        if (!ctx->checkBelAvail(io_bel)) {
+            if (!is_diff_io(io_bel)) {
+                log_error("Can't place %s at %s because of %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
+                          ctx->nameOf(ctx->getBoundBelCell(io_bel)));
+            }
+        }
+
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
         CellInfo *aux = ctx->cells[aux_name].get();
         aux->addInput(id_PCLK);
         ci.copyPortTo(id_PCLK, ctx->cells.at(aux_name).get(), id_PCLK);
-        aux->addInput(id_FCLK);
-        ci.copyPortTo(id_FCLK, ctx->cells.at(aux_name).get(), id_FCLK);
         aux->addInput(id_RESET);
         ci.copyPortTo(id_RESET, ctx->cells.at(aux_name).get(), id_RESET);
         ctx->cells.at(aux_name)->setParam(ctx->id("OUTMODE"), Property("DDRENABLE"));
         ctx->cells.at(aux_name)->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ctx->cells.at(aux_name)->setAttr(ctx->id("MAIN_CELL"), Property(ci.name.str(ctx)));
         ctx->bindBel(bel, aux, PlaceStrength::STRENGTH_LOCKED);
     }
 
@@ -432,6 +496,11 @@ struct GowinPacker
                 create_aux_iologic_cells(ci);
                 continue;
             }
+            if (ci.type.in(id_OVIDEO, id_OSER10)) {
+                pack_single_output_iol(ci, cells_to_remove, nets_to_remove);
+                create_aux_iologic_cells(ci);
+                continue;
+            }
         }
 
         for (auto cell : cells_to_remove) {
@@ -957,13 +1026,29 @@ struct GowinPacker
     {
         handle_constants();
         pack_iobs();
+        ctx->check();
+
         pack_diff_iobs();
+        ctx->check();
+
         pack_iologic();
+        ctx->check();
+
         pack_gsr();
+        ctx->check();
+
         pack_wideluts();
+        ctx->check();
+
         pack_alus();
+        ctx->check();
+
         constrain_lutffs();
+        ctx->check();
+
         pack_pll();
+        ctx->check();
+
         pack_ram16sdp4();
 
         ctx->fixupHierarchy();

From 87ae77fbc6bbf3412965ab61bca5143caff9be92 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 10 Aug 2023 21:24:30 +1000
Subject: [PATCH 450/712] gowin: Himbaechel. Add IDES primitives

As well as the implementation of all OSC primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.h           |   4 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  14 +++
 himbaechel/uarch/gowin/pack.cc           | 104 +++++++++++++++++++++--
 3 files changed, 116 insertions(+), 6 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 233fc2ed0f..239157ea20 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -30,7 +30,8 @@ inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type);
 
 inline bool type_is_iologic(IdString cell_type)
 {
-    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO);
+    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO, id_IDDR, id_IDDRC, id_IDES4,
+                        id_IDES8, id_IDES10, id_IVIDEO);
 }
 inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type); }
 
@@ -77,6 +78,7 @@ enum
 
     IOLOGICA_Z = 70,
 
+    OSC_Z = 274,
     PLL_Z = 275,
     GSR_Z = 276,
     VCC_Z = 277,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 2f38a960cd..4e44369be6 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -30,6 +30,7 @@
 
 IOLOGICA_Z = 70
 
+OSC_Z   = 274
 PLL_Z   = 275
 GSR_Z   = 276
 VCC_Z   = 277
@@ -292,6 +293,19 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
             tt.create_wire(portmap['GSRI'], "GSRI")
             io = tt.create_bel("GSR", "GSR", z = GSR_Z)
             tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
+    if (y, x) in db.extra_cell_func:
+        funcs = db.extra_cell_func[(y, x)]
+        if 'osc' in funcs:
+            osc_type = funcs['osc']['type']
+            portmap = db.grid[y][x].bels[osc_type].portmap
+            for port, wire in portmap.items():
+                tt.create_wire(wire, port)
+            io = tt.create_bel(osc_type, osc_type, z = OSC_Z)
+            for port, wire in portmap.items():
+                if 'OUT' in port:
+                    tt.add_bel_pin(io, port, wire, PinType.OUTPUT)
+                else:
+                    tt.add_bel_pin(io, port, wire, PinType.INPUT)
 
     return (tiletype, tt)
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 064d3e3a98..4ce9810669 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -451,9 +451,9 @@ struct GowinPacker
 
     bool is_diff_io(BelId bel) { return ctx->getBoundBelCell(bel)->attrs.count(id_DIFF_TYPE) != 0; }
 
-    void create_aux_iologic_cells(CellInfo &ci)
+    void create_aux_iologic_cells(CellInfo &ci, IdString mode)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4)) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
             return;
         }
         IdString aux_name = create_aux_iologic_name(ci.name);
@@ -472,12 +472,101 @@ struct GowinPacker
         ci.copyPortTo(id_PCLK, ctx->cells.at(aux_name).get(), id_PCLK);
         aux->addInput(id_RESET);
         ci.copyPortTo(id_RESET, ctx->cells.at(aux_name).get(), id_RESET);
-        ctx->cells.at(aux_name)->setParam(ctx->id("OUTMODE"), Property("DDRENABLE"));
+        ctx->cells.at(aux_name)->setParam(mode, Property("DDRENABLE"));
         ctx->cells.at(aux_name)->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
         ctx->cells.at(aux_name)->setAttr(ctx->id("MAIN_CELL"), Property(ci.name.str(ctx)));
         ctx->bindBel(bel, aux, PlaceStrength::STRENGTH_LOCKED);
     }
 
+    void reconnect_ides_outs(CellInfo *ci)
+    {
+        switch (ci->type.hash()) {
+        case ID_IDDR: /* fall-through*/
+        case ID_IDDRC:
+            ci->renamePort(id_Q1, id_Q9);
+            ci->renamePort(id_Q0, id_Q8);
+            break;
+        case ID_IDES4:
+            ci->renamePort(id_Q3, id_Q9);
+            ci->renamePort(id_Q2, id_Q8);
+            ci->renamePort(id_Q1, id_Q7);
+            ci->renamePort(id_Q0, id_Q6);
+            break;
+        case ID_IVIDEO:
+            ci->renamePort(id_Q6, id_Q9);
+            ci->renamePort(id_Q5, id_Q8);
+            ci->renamePort(id_Q4, id_Q7);
+            ci->renamePort(id_Q3, id_Q6);
+            ci->renamePort(id_Q2, id_Q5);
+            ci->renamePort(id_Q1, id_Q4);
+            ci->renamePort(id_Q0, id_Q3);
+            break;
+        case ID_IDES8:
+            ci->renamePort(id_Q7, id_Q9);
+            ci->renamePort(id_Q6, id_Q8);
+            ci->renamePort(id_Q5, id_Q7);
+            ci->renamePort(id_Q4, id_Q6);
+            ci->renamePort(id_Q3, id_Q5);
+            ci->renamePort(id_Q2, id_Q4);
+            ci->renamePort(id_Q1, id_Q3);
+            ci->renamePort(id_Q0, id_Q2);
+            break;
+        default:
+            break;
+        }
+    }
+
+    void pack_ides_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove, std::vector<IdString> &nets_to_remove)
+    {
+        IdString in_port = id_D;
+
+        CellInfo *in_iob = net_driven_by(ctx, ci.ports.at(in_port).net, is_iob, id_O);
+        NPNR_ASSERT(in_iob != nullptr && in_iob->bel != BelId());
+        BelId iob_bel = in_iob->bel;
+
+        BelId l_bel = get_iologic_bel(in_iob);
+        if (l_bel == BelId()) {
+            log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
+        }
+
+        if (!ctx->checkBelAvail(l_bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
+                      ctx->nameOfBel(l_bel), ctx->nameOf(ctx->getBoundBelCell(l_bel)));
+        }
+        ctx->bindBel(l_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+        std::string in_mode;
+        switch (ci.type.hash()) {
+        case ID_IDDR:
+        case ID_IDDRC:
+            in_mode = "IDDRX1";
+            break;
+        case ID_IDES4:
+            in_mode = "IDDRX2";
+            break;
+        case ID_IDES8:
+            in_mode = "IDDRX4";
+            break;
+        case ID_IDES10:
+            in_mode = "IDDRX5";
+            break;
+        case ID_IVIDEO:
+            in_mode = "VIDEORX";
+            break;
+        }
+        ci.setParam(ctx->id("INMODE"), in_mode);
+
+        // mark IOB as used by IOLOGIC
+        in_iob->setParam(id_IOLOGIC_IOB, 1);
+        // disconnect Q output: it is wired internally
+        nets_to_remove.push_back(ci.getPort(in_port)->name);
+        in_iob->disconnectPort(id_O);
+        ci.disconnectPort(in_port);
+        set_daaj_nets(ci, iob_bel);
+        reconnect_ides_outs(&ci);
+
+        make_iob_nets(*in_iob);
+    }
+
     void pack_iologic()
     {
         log_info("Pack IO logic...\n");
@@ -493,12 +582,17 @@ struct GowinPacker
             }
             if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8)) {
                 pack_bi_output_iol(ci, cells_to_remove, nets_to_remove);
-                create_aux_iologic_cells(ci);
+                create_aux_iologic_cells(ci, ctx->id("OUTMODE"));
                 continue;
             }
             if (ci.type.in(id_OVIDEO, id_OSER10)) {
                 pack_single_output_iol(ci, cells_to_remove, nets_to_remove);
-                create_aux_iologic_cells(ci);
+                create_aux_iologic_cells(ci, ctx->id("OUTMODE"));
+                continue;
+            }
+            if (ci.type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO)) {
+                pack_ides_iol(ci, cells_to_remove, nets_to_remove);
+                create_aux_iologic_cells(ci, ctx->id("INMODE"));
                 continue;
             }
         }

From a823543932af6cf2f4751086170f7010f2c9c1e1 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 12 Aug 2023 15:12:19 +1000
Subject: [PATCH 451/712] gowin: Himbaechel. Unify the creation of tail types

A single mechanism for creating a new type of tile if special functions
are found in the chip database that depend on the coordinates of the
tile.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 177 +++++++++++++----------
 himbaechel/uarch/gowin/pack.cc           |  25 ++--
 2 files changed, 114 insertions(+), 88 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 4e44369be6..805f99b716 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -98,7 +98,13 @@ def serialise(self, context: str, bba: BBAWriter):
         self.bottom_io.serialise(f"{context}_bottom_io", bba)
         bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
 
-# { ttyp : {}}
+# Unique features of the tiletype
+class TypeDesc:
+    def __init__(self, dups, tiletype = '', extra_func = None, sfx = 0):
+        self.tiletype = tiletype
+        self.extra_func = extra_func
+        self.dups = dups
+        self.sfx = sfx
 created_tiletypes = {}
 
 # u-turn at the rim
@@ -225,8 +231,10 @@ def get_wire_type(name):
             tt.create_pip(src, dst)
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
+    if (y, x) not in db.hclk_pips:
+        return
     # hclk wires
-    for dst, srcs in db.hclk_pips[(y, x)].items():
+    for dst, srcs in db.hclk_pips[y, x].items():
         if not tt.has_wire(dst):
             tt.create_wire(dst, "HCLK")
         for src in srcs.keys():
@@ -234,47 +242,95 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
                 tt.create_wire(src, "HCLK")
             tt.create_pip(src, dst)
 
-extra_type_cnt = 1
+def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
+    if (y, x) not in db.extra_func:
+        return
+    for func, desc in db.extra_func[(y, x)].items():
+        if func == 'osc':
+            osc_type = desc['type']
+            portmap = db.grid[y][x].bels[osc_type].portmap
+            for port, wire in portmap.items():
+                tt.create_wire(wire, port)
+            bel = tt.create_bel(osc_type, osc_type, z = OSC_Z)
+            for port, wire in portmap.items():
+                if 'OUT' in port:
+                    tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
+                else:
+                    tt.add_bel_pin(bel, port, wire, PinType.INPUT)
+        elif func == 'gsr':
+            wire = desc['wire']
+            tt.create_wire(wire, "GSRI")
+            bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
+            tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
+
 def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    global extra_type_cnt
-    create_hclk_pips = False
-
-    # HCLK wires can be different in the same types of tiles, so if necessary, create a new type
-    if ttyp in created_tiletypes:
-        # check if we have HCLK pips
-        if (y, x) in db.hclk_pips and created_tiletypes[ttyp]['hclk_pips'] != db.hclk_pips[y, x]:
-            create_hclk_pips = True
-            ttyp = 100 * ttyp + extra_type_cnt
-            extra_type_cnt += 1
+    has_extra_func = (y, x) in db.extra_func
+
+    # (found, TypeDesc)
+    def find_or_make_dup():
+        for d in created_tiletypes[ttyp].dups:
+            if has_extra_func and d.extra_func == db.extra_func[(y, x)]:
+                return (True, d)
+            elif not has_extra_func and not d.extra_func:
+                return (True, d)
+        sfx = len(created_tiletypes[ttyp].dups) + 1
+        if has_extra_func:
+            tdesc = TypeDesc(extra_func = db.extra_func[(y, x)], sfx = sfx, dups = [])
+        else:
+            tdesc = TypeDesc(sfx = sfx, dups = [])
+        created_tiletypes[ttyp].dups.append(tdesc)
+        return (False, tdesc)
+
+    old_type = False
+    if ttyp not in created_tiletypes:
+        # new type
+        if has_extra_func:
+            tdesc = TypeDesc(extra_func = db.extra_func[(y, x)], dups = [])
         else:
-            chip.set_tile_type(x, y, created_tiletypes[ttyp]['tiletype'])
-            return
-    elif (y, x) in db.hclk_pips:
-        create_hclk_pips = True
+            tdesc = TypeDesc(dups = [])
+        created_tiletypes.update({ttyp: tdesc})
     else:
-        created_tiletypes[ttyp] = {}
-    if create_hclk_pips:
-        created_tiletypes.setdefault(ttyp, {}).update({'hclk_pips': db.hclk_pips[y, x]})
+        # find similar
+        if has_extra_func:
+            if created_tiletypes[ttyp].extra_func == db.extra_func[(y, x)]:
+                tdesc = created_tiletypes[ttyp]
+                old_type = True
+            else:
+                old_type, tdesc = find_or_make_dup()
+        elif not created_tiletypes[ttyp].extra_func:
+                tdesc = created_tiletypes[ttyp]
+                old_type = True
+        else:
+                old_type, tdesc = find_or_make_dup()
+
+    if old_type:
+        chip.set_tile_type(x, y, tdesc.tiletype)
+        return
 
-    tiletype, tt = create_func(chip, db, x, y, ttyp)
+    tt = create_func(chip, db, x, y, ttyp, tdesc)
+    print(ttyp, tdesc.tiletype)
 
-    if create_hclk_pips:
-        create_hclk_switch_matrix(tt, db, x, y)
+    create_extra_funcs(tt, db, x, y)
+    create_hclk_switch_matrix(tt, db, x, y)
     create_switch_matrix(tt, db, x, y)
-    chip.set_tile_type(x, y, tiletype)
-    created_tiletypes.setdefault(ttyp, {}).update({'tiletype': tiletype})
+    chip.set_tile_type(x, y, tdesc.tiletype)
 
-def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "NULL"
     tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
-    return (tiletype, tt)
+    tdesc.tiletype = tiletype
+    return tt
 
 # responsible nodes, there will be IO banks, configuration, etc.
-def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "CORNER"
     tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
@@ -287,46 +343,17 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         tt.create_wire('VCC', 'VCC')
         gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
         tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
-        # also here may be GSR
-        if 'GSR' in db.grid[y][x].bels:
-            portmap = db.grid[y][x].bels['GSR'].portmap
-            tt.create_wire(portmap['GSRI'], "GSRI")
-            io = tt.create_bel("GSR", "GSR", z = GSR_Z)
-            tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
-    if (y, x) in db.extra_cell_func:
-        funcs = db.extra_cell_func[(y, x)]
-        if 'osc' in funcs:
-            osc_type = funcs['osc']['type']
-            portmap = db.grid[y][x].bels[osc_type].portmap
-            for port, wire in portmap.items():
-                tt.create_wire(wire, port)
-            io = tt.create_bel(osc_type, osc_type, z = OSC_Z)
-            for port, wire in portmap.items():
-                if 'OUT' in port:
-                    tt.add_bel_pin(io, port, wire, PinType.OUTPUT)
-                else:
-                    tt.add_bel_pin(io, port, wire, PinType.INPUT)
-
-    return (tiletype, tt)
-
-# Global set/reset. GW2A series has special cell for it
-def create_gsr_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    typename = "GSR"
-    tiletype = f"{typename}_{ttyp}"
-    tt = chip.create_tile_type(tiletype)
-    tt.extra_data = TileExtraData(chip.strs.id(typename))
 
-    portmap = db.grid[y][x].bels['GSR'].portmap
-    tt.create_wire(portmap['GSRI'], "GSRI")
-    io = tt.create_bel("GSR", "GSR", z = GSR_Z)
-    tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
+    tdesc.tiletype = tiletype
+    return tt
 
-    return (tiletype, tt)
 
 # IO
-def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "IO"
     tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
@@ -376,12 +403,15 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
                 tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
             else:
                 tt.add_bel_pin(iol, port, wire, PinType.INPUT)
-    return (tiletype, tt)
+    tdesc.tiletype = tiletype
+    return tt
 
 # logic: luts, dffs, alu etc
-def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "LOGIC"
     tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
@@ -471,11 +501,12 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, "O",  f"OF7", PinType.OUTPUT)
     tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
 
-    return (tiletype, tt)
+    tdesc.tiletype = tiletype
+    return tt
 
-def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     # SSRAM is LUT based, so it's logic-like
-    tiletype, tt = create_logic_tiletype(chip, db, x, y, ttyp)
+    tt = create_logic_tiletype(chip, db, x, y, ttyp, tdesc)
 
     lut_inputs = ['A', 'B', 'C', 'D']
     ff = tt.create_bel(f"RAM16SDP4", "RAM16SDP4", z = RAMW_Z)
@@ -491,7 +522,7 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
     tt.add_bel_pin(ff, f"CE",  "CE2", PinType.INPUT)
     tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
-    return (tiletype, tt)
+    return tt
 
 # PLL main tile
 _pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
@@ -501,9 +532,11 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
         'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
 _pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
-def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
+def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "PLL"
     tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
@@ -525,7 +558,8 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
             assert pin in _pll_outputs, f"Unknown PLL pin {pin}"
             tt.create_wire(wire, "PLL_O")
             tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
-    return (tiletype, tt)
+    tdesc.tiletype = tiletype
+    return tt
 
 # pinouts, packages...
 _tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
@@ -601,7 +635,6 @@ def main():
     logic_tiletypes = db.tile_types['C']
     io_tiletypes = db.tile_types['I']
     ssram_tiletypes = db.tile_types['M']
-    gsr_tiletypes = {1}
     pll_tiletypes = db.tile_types['P']
 
     # Setup tile grid
@@ -612,8 +645,6 @@ def main():
                 assert ttyp not in created_tiletypes, "Duplication of corner types"
                 create_tiletype(create_corner_tiletype, ch, db, x, y, ttyp)
                 continue
-            if ttyp in gsr_tiletypes:
-                create_tiletype(create_gsr_tiletype, ch, db, x, y, ttyp)
             elif ttyp in logic_tiletypes:
                 create_tiletype(create_logic_tiletype, ch, db, x, y, ttyp)
             elif ttyp in ssram_tiletypes:
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 4ce9810669..7907004018 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1070,22 +1070,17 @@ struct GowinPacker
             }
         }
         if (!user_gsr) {
-            bool have_gsr_bel = false;
-            auto bels = ctx->getBels();
-            for (auto bid : bels) {
-                if (ctx->getBelType(bid) == id_GSR) {
-                    have_gsr_bel = true;
-                    break;
-                }
-            }
-            if (have_gsr_bel) {
-                // make default GSR
-                auto gsr_cell = std::make_unique<CellInfo>(ctx, id_GSR, id_GSR);
-                gsr_cell->addInput(id_GSRI);
-                gsr_cell->connectPort(id_GSRI, ctx->nets[ctx->id("$PACKER_VCC")].get());
-                ctx->cells[gsr_cell->name] = std::move(gsr_cell);
+            // make default GSR
+            auto gsr_cell = std::make_unique<CellInfo>(ctx, id_GSR, id_GSR);
+            gsr_cell->addInput(id_GSRI);
+            gsr_cell->connectPort(id_GSRI, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            ctx->cells[gsr_cell->name] = std::move(gsr_cell);
+        }
+        if (ctx->verbose) {
+            if (user_gsr) {
+                log_info("Have user GSR\n");
             } else {
-                log_info("No GSR in the chip base\n");
+                log_info("No user GSR. Make one.\n");
             }
         }
     }

From 0994e11b73e0ff77c133b28faa45e72d7b1e103f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 13 Aug 2023 22:05:18 +1000
Subject: [PATCH 452/712] gowin: Himbaechel. Add OSER16 and IDES16

Information about what function (main or auxiliary) the cell performs in
these primitives is transmitted through the tile's extra data. And this
also allows us to remove the calculation of the coordinates of the
auxiliary cell on the go.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc          |   5 +-
 himbaechel/uarch/gowin/gowin.h           |  10 +
 himbaechel/uarch/gowin/gowin_arch_gen.py |  29 +++
 himbaechel/uarch/gowin/gowin_utils.cc    |  18 ++
 himbaechel/uarch/gowin/gowin_utils.h     |   4 +
 himbaechel/uarch/gowin/pack.cc           | 266 ++++++++++++++++++++---
 6 files changed, 300 insertions(+), 32 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 2ff3555ff0..2ce0550f9f 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -175,7 +175,7 @@ void GowinImpl::postRoute()
 
     for (auto &cell : ctx->cells) {
         auto ci = cell.second.get();
-        if (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC)) {
+        if (ci->type == id_IOLOGIC || (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
             if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
                 // mark FCLK<-HCLK connections
                 const NetInfo *h_net = ci->getPort(id_FCLK);
@@ -192,6 +192,9 @@ void GowinImpl::postRoute()
                         IdString up_wire_name = ctx->getWireName(ctx->getPipSrcWire(up_pip))[1];
                         if (up_wire_name.in(id_HCLK_OUT0, id_HCLK_OUT1, id_HCLK_OUT2, id_HCLK_OUT3)) {
                             user.cell->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
+                            if (ctx->debug) {
+                                log_info("set IOLOGIC_FCLK to %s\n", up_wire_name.c_str(ctx));
+                            }
                         }
                         if (ctx->debug) {
                             log_info("HCLK user cell:%s, port:%s, wire:%s, pip:%s, up wire:%s\n",
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 239157ea20..7086bfdec8 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -39,7 +39,15 @@ inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
 
+// ==========================================
 // extra data in the chip db
+// ==========================================
+NPNR_PACKED_STRUCT(struct Tile_extra_data_POD {
+    int32_t class_id;
+    int16_t io16_x_off;
+    int16_t io16_y_off;
+});
+
 NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
     int32_t wire_a_net;
     int32_t wire_b_net;
@@ -77,6 +85,8 @@ enum
     IOBB_Z = 51, // +IOBC...IOBL
 
     IOLOGICA_Z = 70,
+    IDES16_Z = 72,
+    OSER16_Z = 73,
 
     OSC_Z = 274,
     PLL_Z = 275,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 805f99b716..93dcc494f7 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -29,6 +29,8 @@
 IOBB_Z  = 51
 
 IOLOGICA_Z = 70
+IDES16_Z   = 72
+OSER16_Z   = 73
 
 OSC_Z   = 274
 PLL_Z   = 275
@@ -45,10 +47,15 @@ class TileExtraData(BBAStruct):
                          # let's say the behavior of LUT+DFF in the tiles are completely identical,
                          # but one of them also contains clock-wire switches,
                          # then we assign them to the same LOGIC class.
+    io16_x_off: int = 0  # OSER16/IDES16 offsets to the aux cell
+    io16_y_off: int = 0
+
     def serialise_lists(self, context: str, bba: BBAWriter):
         pass
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.tile_class.index)
+        bba.u16(self.io16_x_off)
+        bba.u16(self.io16_y_off)
 
 @dataclass
 class BottomIOCnd(BBAStruct):
@@ -262,6 +269,28 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
             tt.create_wire(wire, "GSRI")
             bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
             tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
+        if func == 'io16':
+            role = desc['role']
+            if role == 'MAIN':
+                y_off, x_off = desc['pair']
+                tt.extra_data.io16_x_off = x_off
+                tt.extra_data.io16_y_off = y_off
+
+            for io_type, z in {('IDES16', IDES16_Z), ('OSER16', OSER16_Z)}:
+                bel = tt.create_bel(io_type, io_type, z = z)
+                portmap = db.grid[y][x].bels[io_type].portmap
+                for port, wire in portmap.items():
+                    if port == 'FCLK': # XXX compatibility
+                        wire = 'FCLKA'
+                    if not tt.has_wire(wire):
+                        if port in {'CLK', 'PCLK'}:
+                            tt.create_wire(wire, "TILE_CLK")
+                        else:
+                            tt.create_wire(wire, "IOL_PORT")
+                    if 'OUT' in port:
+                        tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
+                    else:
+                        tt.add_bel_pin(bel, port, wire, PinType.INPUT)
 
 def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     has_extra_func = (y, x) in db.extra_func
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 3c23be50e6..16b39d474f 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -11,6 +11,24 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+// tile extra data
+IdString GowinUtils::get_tile_class(int x, int y)
+{
+    int tile = tile_by_xy(ctx->chip_info, x, y);
+    const Tile_extra_data_POD *extra =
+            reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
+    return IdString(extra->class_id);
+}
+
+// oser16/ides16 aux cell offsets
+Loc GowinUtils::get_tile_io16_offs(int x, int y)
+{
+    int tile = tile_by_xy(ctx->chip_info, x, y);
+    const Tile_extra_data_POD *extra =
+            reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
+    return Loc(extra->io16_x_off, extra->io16_y_off, 0);
+}
+
 // pin functions: GCLKT_4, SSPI_CS, READY etc
 IdStringList GowinUtils::get_pin_funcs(BelId bel)
 {
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 5d544a7400..b88e9b7ac8 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -19,6 +19,10 @@ struct GowinUtils
 
     void init(Context *ctx) { this->ctx = ctx; }
 
+    // tile
+    IdString get_tile_class(int x, int y);
+    Loc get_tile_io16_offs(int x, int y);
+
     // pin functions: GCLKT_4, SSPI_CS, READY etc
     IdStringList get_pin_funcs(BelId bel);
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 7907004018..1b6aa4c100 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -332,7 +332,19 @@ struct GowinPacker
         return ctx->getBelByLocation(loc);
     }
 
-    void pack_bi_output_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove, std::vector<IdString> &nets_to_remove)
+    void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
+    {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC) || diff) {
+            return;
+        }
+        BelId l_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOBA_Z + 1 - (iob_loc.z - BelZ::IOBA_Z)));
+        if (!ctx->checkBelAvail(l_bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
+                      ctx->nameOfBel(l_bel), ctx->nameOf(ctx->getBoundBelCell(l_bel)));
+        }
+    }
+
+    void pack_bi_output_iol(CellInfo &ci, std::vector<IdString> &nets_to_remove)
     {
         // These primitives have an additional pin to control the tri-state iob - Q1.
         IdString out_port = id_Q0;
@@ -346,6 +358,9 @@ struct GowinPacker
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
+        // mark IOB as used by IOLOGIC
+        out_iob->setParam(id_IOLOGIC_IOB, 1);
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->attrs.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -367,8 +382,6 @@ struct GowinPacker
         }
         ci.setParam(ctx->id("OUTMODE"), out_mode);
 
-        // mark IOB as used by IOLOGIC
-        out_iob->setParam(id_IOLOGIC_IOB, 1);
         // disconnect Q output: it is wired internally
         nets_to_remove.push_back(ci.getPort(out_port)->name);
         out_iob->disconnectPort(id_I);
@@ -390,8 +403,7 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
-    void pack_single_output_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove,
-                                std::vector<IdString> &nets_to_remove)
+    void pack_single_output_iol(CellInfo &ci, std::vector<IdString> &nets_to_remove)
     {
         IdString out_port = id_Q;
 
@@ -403,6 +415,9 @@ struct GowinPacker
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
+        // mark IOB as used by IOLOGIC
+        out_iob->setParam(id_IOLOGIC_IOB, 1);
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->attrs.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -420,8 +435,6 @@ struct GowinPacker
         }
         ci.setParam(ctx->id("OUTMODE"), out_mode);
 
-        // mark IOB as used by IOLOGIC
-        out_iob->setParam(id_IOLOGIC_IOB, 1);
         // disconnect Q output: it is wired internally
         nets_to_remove.push_back(ci.getPort(out_port)->name);
         out_iob->disconnectPort(id_I);
@@ -451,12 +464,12 @@ struct GowinPacker
 
     bool is_diff_io(BelId bel) { return ctx->getBoundBelCell(bel)->attrs.count(id_DIFF_TYPE) != 0; }
 
-    void create_aux_iologic_cells(CellInfo &ci, IdString mode)
+    CellInfo *create_aux_iologic_cell(CellInfo &ci, IdString mode, bool io16 = false, int idx = 0)
     {
         if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
-            return;
+            return nullptr;
         }
-        IdString aux_name = create_aux_iologic_name(ci.name);
+        IdString aux_name = create_aux_iologic_name(ci.name, idx);
         BelId bel = get_aux_iologic_bel(ci);
         BelId io_bel = gwu.get_io_bel_from_iologic(bel);
         if (!ctx->checkBelAvail(io_bel)) {
@@ -467,15 +480,18 @@ struct GowinPacker
         }
 
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
-        CellInfo *aux = ctx->cells[aux_name].get();
-        aux->addInput(id_PCLK);
-        ci.copyPortTo(id_PCLK, ctx->cells.at(aux_name).get(), id_PCLK);
-        aux->addInput(id_RESET);
-        ci.copyPortTo(id_RESET, ctx->cells.at(aux_name).get(), id_RESET);
-        ctx->cells.at(aux_name)->setParam(mode, Property("DDRENABLE"));
-        ctx->cells.at(aux_name)->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
-        ctx->cells.at(aux_name)->setAttr(ctx->id("MAIN_CELL"), Property(ci.name.str(ctx)));
+        CellInfo *aux = ctx->cells.at(aux_name).get();
+        ci.copyPortTo(id_PCLK, aux, id_PCLK);
+        ci.copyPortTo(id_RESET, aux, id_RESET);
+        if (io16) {
+            aux->setParam(mode, Property("DDRENABLE16"));
+        } else {
+            aux->setParam(mode, Property("DDRENABLE"));
+        }
+        aux->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(ci.name.str(ctx)));
         ctx->bindBel(bel, aux, PlaceStrength::STRENGTH_LOCKED);
+        return aux;
     }
 
     void reconnect_ides_outs(CellInfo *ci)
@@ -516,7 +532,7 @@ struct GowinPacker
         }
     }
 
-    void pack_ides_iol(CellInfo &ci, std::vector<IdString> &cells_to_remove, std::vector<IdString> &nets_to_remove)
+    void pack_ides_iol(CellInfo &ci, std::vector<IdString> &nets_to_remove)
     {
         IdString in_port = id_D;
 
@@ -528,6 +544,9 @@ struct GowinPacker
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
+        // mark IOB as used by IOLOGIC
+        in_iob->setParam(id_IOLOGIC_IOB, 1);
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), in_iob->attrs.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -555,9 +574,7 @@ struct GowinPacker
         }
         ci.setParam(ctx->id("INMODE"), in_mode);
 
-        // mark IOB as used by IOLOGIC
-        in_iob->setParam(id_IOLOGIC_IOB, 1);
-        // disconnect Q output: it is wired internally
+        // disconnect D input: it is wired internally
         nets_to_remove.push_back(ci.getPort(in_port)->name);
         in_iob->disconnectPort(id_O);
         ci.disconnectPort(in_port);
@@ -570,7 +587,7 @@ struct GowinPacker
     void pack_iologic()
     {
         log_info("Pack IO logic...\n");
-        std::vector<IdString> cells_to_remove, nets_to_remove;
+        std::vector<IdString> nets_to_remove;
 
         for (auto &cell : ctx->cells) {
             CellInfo &ci = *cell.second;
@@ -581,29 +598,213 @@ struct GowinPacker
                 log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
             }
             if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8)) {
-                pack_bi_output_iol(ci, cells_to_remove, nets_to_remove);
-                create_aux_iologic_cells(ci, ctx->id("OUTMODE"));
+                pack_bi_output_iol(ci, nets_to_remove);
+                create_aux_iologic_cell(ci, ctx->id("OUTMODE"));
                 continue;
             }
             if (ci.type.in(id_OVIDEO, id_OSER10)) {
-                pack_single_output_iol(ci, cells_to_remove, nets_to_remove);
-                create_aux_iologic_cells(ci, ctx->id("OUTMODE"));
+                pack_single_output_iol(ci, nets_to_remove);
+                create_aux_iologic_cell(ci, ctx->id("OUTMODE"));
                 continue;
             }
             if (ci.type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO)) {
-                pack_ides_iol(ci, cells_to_remove, nets_to_remove);
-                create_aux_iologic_cells(ci, ctx->id("INMODE"));
+                pack_ides_iol(ci, nets_to_remove);
+                create_aux_iologic_cell(ci, ctx->id("INMODE"));
                 continue;
             }
         }
 
-        for (auto cell : cells_to_remove) {
-            ctx->cells.erase(cell);
+        for (auto net : nets_to_remove) {
+            ctx->nets.erase(net);
+        }
+    }
+
+    // ===================================
+    // IDES16 / OSER16
+    // ===================================
+    void check_io16_placement(CellInfo &ci, Loc main_loc, Loc aux_off, int diff /* 1 - diff */)
+    {
+        int mod[][3] = {{0, 0, 1}, {1, 1, 0}, {1, 1, 1}};
+        for (int i = diff; i < 3; ++i) {
+            Loc aux_loc(main_loc.x + mod[i][0] * aux_off.x, main_loc.y + mod[i][1] * aux_off.y, main_loc.z + mod[i][2]);
+            BelId l_bel = ctx->getBelByLocation(aux_loc);
+            if (!ctx->checkBelAvail(l_bel)) {
+                log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
+                          ctx->nameOfBel(l_bel), ctx->nameOf(ctx->getBoundBelCell(l_bel)));
+            }
+        }
+    }
+
+    void pack_oser16(CellInfo &ci, std::vector<IdString> &nets_to_remove)
+    {
+        IdString out_port = id_Q;
+
+        CellInfo *out_iob = net_only_drives(ctx, ci.ports.at(out_port).net, is_iob, id_I, true);
+        NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
+        // mark IOB as used by IOLOGIC
+        out_iob->setParam(id_IOLOGIC_IOB, 1);
+
+        BelId iob_bel = out_iob->bel;
+
+        Loc iob_loc = ctx->getBelLocation(iob_bel);
+        Loc aux_offset = gwu.get_tile_io16_offs(iob_loc.x, iob_loc.y);
+
+        if (aux_offset.x == 0 && aux_offset.y == 0) {
+            log_error("OSER16 %s can not be placed here\n", ctx->nameOf(&ci));
+        }
+        check_io16_placement(ci, iob_loc, aux_offset, out_iob->attrs.count(id_DIFF_TYPE));
+
+        BelId main_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::OSER16_Z));
+        ctx->bindBel(main_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+
+        // disconnect Q output: it is wired internally
+        nets_to_remove.push_back(ci.getPort(out_port)->name);
+        out_iob->disconnectPort(id_I);
+        ci.disconnectPort(out_port);
+
+        // to simplify packaging, the parts of the OSER16 are presented as IOLOGIC cells
+        // and one of these aux cells is declared as main
+        IdString main_name = create_aux_iologic_name(ci.name);
+
+        IdString aux_name = create_aux_iologic_name(ci.name, 1);
+        ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
+        CellInfo *aux = ctx->cells.at(aux_name).get();
+
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        aux->setParam(ctx->id("OUTMODE"), Property("ODDRX8"));
+        aux->setParam(ctx->id("UPDATE"), Property("SAME"));
+        aux->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ci.copyPortTo(id_PCLK, aux, id_PCLK);
+        ci.copyPortTo(id_RESET, aux, id_RESET);
+        ctx->bindBel(ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOLOGICA_Z)), aux,
+                     PlaceStrength::STRENGTH_LOCKED);
+
+        // make aux cell in the first cell
+        aux = create_aux_iologic_cell(*aux, ctx->id("OUTMODE"), true, 2);
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        aux->setParam(ctx->id("UPDATE"), Property("SAME"));
+
+        // make cell in the next location
+        ctx->createCell(main_name, id_IOLOGIC);
+        aux = ctx->cells.at(main_name).get();
+
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        aux->setParam(ctx->id("OUTMODE"), Property("DDRENABLE16"));
+        aux->setParam(ctx->id("UPDATE"), Property("SAME"));
+        aux->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ci.copyPortTo(id_PCLK, aux, id_PCLK);
+        ci.copyPortTo(id_RESET, aux, id_RESET);
+        ci.movePortTo(id_FCLK, aux, id_FCLK);
+        ci.movePortTo(id_D12, aux, id_D0);
+        ci.movePortTo(id_D13, aux, id_D1);
+        ci.movePortTo(id_D14, aux, id_D2);
+        ci.movePortTo(id_D15, aux, id_D3);
+        Loc next_io16(iob_loc.x + aux_offset.x, iob_loc.y + aux_offset.y, BelZ::IOLOGICA_Z);
+        ctx->bindBel(ctx->getBelByLocation(next_io16), aux, PlaceStrength::STRENGTH_LOCKED);
+
+        Loc io_loc = ctx->getBelLocation(iob_bel);
+        if (io_loc.y == ctx->getGridDimY() - 1) {
+            config_bottom_row(*out_iob, io_loc, Bottom_io_POD::DDR);
+        }
+        make_iob_nets(*out_iob);
+    }
+
+    void pack_ides16(CellInfo &ci, std::vector<IdString> &nets_to_remove)
+    {
+        IdString in_port = id_D;
+
+        CellInfo *in_iob = net_driven_by(ctx, ci.ports.at(in_port).net, is_iob, id_O);
+        NPNR_ASSERT(in_iob != nullptr && in_iob->bel != BelId());
+        // mark IOB as used by IOLOGIC
+        in_iob->setParam(id_IOLOGIC_IOB, 1);
+
+        BelId iob_bel = in_iob->bel;
+
+        Loc iob_loc = ctx->getBelLocation(iob_bel);
+        Loc aux_offset = gwu.get_tile_io16_offs(iob_loc.x, iob_loc.y);
+
+        if (aux_offset.x == 0 && aux_offset.y == 0) {
+            log_error("IDES16 %s can not be placed here\n", ctx->nameOf(&ci));
+        }
+        check_io16_placement(ci, iob_loc, aux_offset, in_iob->attrs.count(id_DIFF_TYPE));
+
+        BelId main_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IDES16_Z));
+        ctx->bindBel(main_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+
+        // disconnect Q output: it is wired internally
+        nets_to_remove.push_back(ci.getPort(in_port)->name);
+        in_iob->disconnectPort(id_O);
+        ci.disconnectPort(in_port);
+
+        // to simplify packaging, the parts of the IDES16 are presented as IOLOGIC cells
+        // and one of these aux cells is declared as main
+        IdString main_name = create_aux_iologic_name(ci.name);
+
+        IdString aux_name = create_aux_iologic_name(ci.name, 1);
+        ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
+        CellInfo *aux = ctx->cells.at(aux_name).get();
+
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        aux->setParam(ctx->id("INMODE"), Property("IDDRX8"));
+        aux->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ci.copyPortTo(id_PCLK, aux, id_PCLK);
+        ci.copyPortTo(id_RESET, aux, id_RESET);
+        ctx->bindBel(ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOLOGICA_Z)), aux,
+                     PlaceStrength::STRENGTH_LOCKED);
+
+        // make aux cell in the first cell
+        aux = create_aux_iologic_cell(*aux, ctx->id("INMODE"), true, 2);
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        ci.copyPortTo(id_CALIB, aux, id_CALIB);
+
+        // make cell in the next location
+        ctx->createCell(main_name, id_IOLOGIC);
+        aux = ctx->cells.at(main_name).get();
+
+        aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
+        aux->setParam(ctx->id("INMODE"), Property("DDRENABLE16"));
+        aux->setAttr(ctx->id("IOLOGIC_TYPE"), Property("DUMMY"));
+        ci.copyPortTo(id_PCLK, aux, id_PCLK);
+        ci.copyPortTo(id_RESET, aux, id_RESET);
+        ci.copyPortTo(id_CALIB, aux, id_CALIB);
+        ci.movePortTo(id_FCLK, aux, id_FCLK);
+        ci.movePortTo(id_Q0, aux, id_Q6);
+        ci.movePortTo(id_Q1, aux, id_Q7);
+        ci.movePortTo(id_Q2, aux, id_Q8);
+        ci.movePortTo(id_Q3, aux, id_Q9);
+        Loc next_io16(iob_loc.x + aux_offset.x, iob_loc.y + aux_offset.y, BelZ::IOLOGICA_Z);
+        ctx->bindBel(ctx->getBelByLocation(next_io16), aux, PlaceStrength::STRENGTH_LOCKED);
+
+        make_iob_nets(*in_iob);
+    }
+
+    void pack_io16(void)
+    {
+        std::vector<IdString> nets_to_remove;
+        log_info("Pack DESER16 logic...\n");
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (ci.type == id_OSER16) {
+                if (ctx->debug) {
+                    log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+                }
+                pack_oser16(ci, nets_to_remove);
+                continue;
+            }
+            if (ci.type == id_IDES16) {
+                if (ctx->debug) {
+                    log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+                }
+                pack_ides16(ci, nets_to_remove);
+                continue;
+            }
         }
         for (auto net : nets_to_remove) {
             ctx->nets.erase(net);
         }
     }
+
     // ===================================
     // Constant nets
     // ===================================
@@ -1123,6 +1324,9 @@ struct GowinPacker
         pack_iologic();
         ctx->check();
 
+        pack_io16();
+        ctx->check();
+
         pack_gsr();
         ctx->check();
 

From 4d0afdfd60d3e95746146f637bbcbd93b10490ec Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 15 Aug 2023 13:14:29 +1000
Subject: [PATCH 453/712] gowin: Himbaechel. Add the GW1N-4 simple IOs

And also fix the clock router to allow (with a warning) non-dedicated
routing in case of false detection of clock wires.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc        | 20 +++++++++++++-------
 himbaechel/uarch/gowin/gowin_arch_gen.py |  5 ++---
 himbaechel/uarch/gowin/pack.cc           |  4 +++-
 3 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 0a9ca691e0..f13560ba65 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -53,12 +53,12 @@ struct GowinGlobalRouter
         bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
 
         bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
-        if (ctx->debug && res && false) {
+        if (ctx->debug && false /*&& res*/) {
             log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
                      ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
                      src_type.c_str(ctx));
-            // log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
-            // is_local(src_type), is_local(dst_type));
+            log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
+                     is_local(src_type), is_local(dst_type));
         }
         return res;
     }
@@ -86,8 +86,9 @@ struct GowinGlobalRouter
             log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
                       ctx->nameOf(net->users.at(user_idx).cell), ctx->nameOf(net->users.at(user_idx).port));
 
-        if (ctx->getBoundWireNet(src) != net)
+        if (ctx->getBoundWireNet(src) != net) {
             ctx->bindWire(src, net, STRENGTH_LOCKED);
+        }
 
         if (src == dst) {
             // Nothing more to do
@@ -152,10 +153,15 @@ struct GowinGlobalRouter
             }
             return true;
         } else {
-            if (strict)
+            if (strict) {
                 log_error("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
                           ctx->nameOfWire(src), ctx->nameOfWire(dst));
-            return false;
+            } else {
+                log_warning("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
+                            ctx->nameOfWire(src), ctx->nameOfWire(dst));
+                ctx->unbindWire(src);
+                return false;
+            }
         }
     }
 
@@ -163,7 +169,7 @@ struct GowinGlobalRouter
     {
         bool routed = false;
         for (auto usr : net->users.enumerate()) {
-            routed = backwards_bfs_route(net, usr.index, 1000000, true, [&](PipId pip) {
+            routed = backwards_bfs_route(net, usr.index, 1000000, false, [&](PipId pip) {
                 return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
             });
             if (!routed) {
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 93dcc494f7..7b0f37e30d 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -337,7 +337,6 @@ def find_or_make_dup():
         return
 
     tt = create_func(chip, db, x, y, ttyp, tdesc)
-    print(ttyp, tdesc.tiletype)
 
     create_extra_funcs(tt, db, x, y)
     create_hclk_switch_matrix(tt, db, x, y)
@@ -386,7 +385,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
-    simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1'}
+    simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1', 'GW1N-4'}
     if simple_io:
         rng = 10
     else:
@@ -559,7 +558,7 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
         'IDSEL4', 'IDSEL5', 'ODSEL0', 'ODSEL1', 'ODSEL2', 'ODSEL3',
         'ODSEL4', 'ODSEL5', 'RESET', 'RESET_P', 'PSDA0', 'PSDA1',
         'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
-        'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
+        'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN', 'VREN'}
 _pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
 def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "PLL"
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 1b6aa4c100..1b0410a0cd 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -151,7 +151,9 @@ struct GowinPacker
     BelId bind_io(CellInfo &ci)
     {
         BelId bel = ctx->getBelByName(IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()));
-        NPNR_ASSERT(bel != BelId());
+        if (bel == BelId()) {
+            log_error("No bel named %s\n", IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()).str(ctx).c_str());
+        }
         ci.unsetAttr(id_BEL);
         ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         return bel;

From e85bb1c28c938a8e2c47c4ce0a31835b2bd00037 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 17 Aug 2023 21:58:36 +1000
Subject: [PATCH 454/712] gowin: Himbaechel. Fix DESER and PLL

- OSER4 can be located in neighboring IOs;
- PLLVR also needs to rename the inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 1b0410a0cd..327bca8865 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -241,7 +241,10 @@ struct GowinPacker
             iob_n->disconnectPort(id_I);
 
             if (ci.type.in(id_TLVDS_TBUF, id_ELVDS_TBUF)) {
-                nets_to_remove.push_back(iob_n->getPort(id_OEN)->name);
+                NetInfo *oen_net = iob_n->getPort(id_OEN);
+                if (oen_net != nullptr) {
+                    nets_to_remove.push_back(oen_net->name);
+                }
                 iob_n->disconnectPort(id_OEN);
                 iob_p->disconnectPort(id_OEN);
                 ci.movePortTo(id_OEN, iob_p, id_OEN);
@@ -336,7 +339,7 @@ struct GowinPacker
 
     void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC) || diff) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4) || diff) {
             return;
         }
         BelId l_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOBA_Z + 1 - (iob_loc.z - BelZ::IOBA_Z)));
@@ -1298,7 +1301,7 @@ struct GowinPacker
         for (auto &cell : ctx->cells) {
             auto &ci = *cell.second;
 
-            if (ci.type == id_rPLL) {
+            if (ci.type.in(id_rPLL, id_PLLVR)) {
                 // pin renaming for compatibility
                 for (int i = 0; i < 6; ++i) {
                     ci.renamePort(ctx->idf("FBDSEL[%d]", i), ctx->idf("FBDSEL%d", i));

From 09b7cad7f19bb6845475105dcf55ee666e7e005f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 18 Aug 2023 06:40:31 +1000
Subject: [PATCH 455/712] gowin: Himbaechel. Refactor.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 34 ++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 2ce0550f9f..e364ea677c 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -312,6 +312,22 @@ void GowinImpl::assign_cell_info()
     }
 }
 
+// DFFs must be same type or compatible
+inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
+{
+    return ff->type != adj_ff->type &&
+           ((ff->type == id_DFFS && adj_ff->type != id_DFFR) || (ff->type == id_DFFR && adj_ff->type != id_DFFS) ||
+            (ff->type == id_DFFSE && adj_ff->type != id_DFFRE) || (ff->type == id_DFFRE && adj_ff->type != id_DFFSE) ||
+            (ff->type == id_DFFP && adj_ff->type != id_DFFC) || (ff->type == id_DFFC && adj_ff->type != id_DFFP) ||
+            (ff->type == id_DFFPE && adj_ff->type != id_DFFCE) || (ff->type == id_DFFCE && adj_ff->type != id_DFFPE) ||
+            (ff->type == id_DFFNS && adj_ff->type != id_DFFNR) || (ff->type == id_DFFNR && adj_ff->type != id_DFFNS) ||
+            (ff->type == id_DFFNSE && adj_ff->type != id_DFFNRE) ||
+            (ff->type == id_DFFNRE && adj_ff->type != id_DFFNSE) ||
+            (ff->type == id_DFFNP && adj_ff->type != id_DFFNC) || (ff->type == id_DFFNC && adj_ff->type != id_DFFNP) ||
+            (ff->type == id_DFFNPE && adj_ff->type != id_DFFNCE) ||
+            (ff->type == id_DFFNCE && adj_ff->type != id_DFFNPE));
+}
+
 // placement validation
 bool GowinImpl::slice_valid(int x, int y, int z) const
 {
@@ -359,23 +375,7 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
             }
         }
         if (adj_ff) {
-            // DFFs must be same type or compatible
-            if (ff->type != adj_ff->type && ((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) ||
-                                             (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
-                                             (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
-                                             (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) ||
-                                             (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
-                                             (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) ||
-                                             (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
-                                             (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
-                                             (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
-                                             (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
-                                             (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
-                                             (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
-                                             (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
-                                             (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
-                                             (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
-                                             (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
+            if (incompatible_ffs(ff, adj_ff)) {
                 return false;
             }
 

From 84a27c3ebf1273de55a17ddd01c07ddf3007757b Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 18 Aug 2023 09:33:05 +1000
Subject: [PATCH 456/712] gowin: Himbaechel. Improve error messages

OSER16/IDES16 placement issue reports now indicate which location is
having trouble.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 327bca8865..34a7e88db2 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -629,6 +629,11 @@ struct GowinPacker
     // ===================================
     void check_io16_placement(CellInfo &ci, Loc main_loc, Loc aux_off, int diff /* 1 - diff */)
     {
+        if (main_loc.z != BelZ::IOBA_Z) {
+            log_error("Can't place %s at %s because OSER16/IDES16 must be placed at A pin\n", ctx->nameOf(&ci),
+                      ctx->nameOfBel(ctx->getBelByLocation(main_loc)));
+        }
+
         int mod[][3] = {{0, 0, 1}, {1, 1, 0}, {1, 1, 1}};
         for (int i = diff; i < 3; ++i) {
             Loc aux_loc(main_loc.x + mod[i][0] * aux_off.x, main_loc.y + mod[i][1] * aux_off.y, main_loc.z + mod[i][2]);
@@ -655,7 +660,7 @@ struct GowinPacker
         Loc aux_offset = gwu.get_tile_io16_offs(iob_loc.x, iob_loc.y);
 
         if (aux_offset.x == 0 && aux_offset.y == 0) {
-            log_error("OSER16 %s can not be placed here\n", ctx->nameOf(&ci));
+            log_error("OSER16 %s can not be placed at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
         check_io16_placement(ci, iob_loc, aux_offset, out_iob->attrs.count(id_DIFF_TYPE));
 
@@ -729,7 +734,7 @@ struct GowinPacker
         Loc aux_offset = gwu.get_tile_io16_offs(iob_loc.x, iob_loc.y);
 
         if (aux_offset.x == 0 && aux_offset.y == 0) {
-            log_error("IDES16 %s can not be placed here\n", ctx->nameOf(&ci));
+            log_error("IDES16 %s can not be placed at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
         check_io16_placement(ci, iob_loc, aux_offset, in_iob->attrs.count(id_DIFF_TYPE));
 

From 1b926b2703c7fbd21a06acae6d45aaf969f2b87c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 19 Aug 2023 17:49:25 +1000
Subject: [PATCH 457/712] gowin: Himbaechel. Fix IO for GW1NZ-1

In these chips, the midline IOs are still simple, but are no longer just
IOBUF - that is, unlike the GW1N-1 IBUF and OBUF are not obtained by
applying a signal to the OEN input.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 2 +-
 himbaechel/uarch/gowin/pack.cc           | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 7b0f37e30d..0921c0895e 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -402,7 +402,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
         tt.create_wire(portmap['OE'], "IO_OE")
         # bels
         io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
-        if simple_io:
+        if simple_io and chip.name in {'GW1N-1'}:
             io.flags |= BEL_FLAG_SIMPLE_IO
         tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
         tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 34a7e88db2..e4a729bd28 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -154,6 +154,10 @@ struct GowinPacker
         if (bel == BelId()) {
             log_error("No bel named %s\n", IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()).str(ctx).c_str());
         }
+        if (!ctx->checkBelAvail(bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
+                      ctx->nameOf(ctx->getBoundBelCell(bel)));
+        }
         ci.unsetAttr(id_BEL);
         ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         return bel;

From fdd45d12fd4d8da08455342a99242a46668d848c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 20 Aug 2023 04:05:35 +1000
Subject: [PATCH 458/712] gowin: Himbaechel. Add rough CMake stuff

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/family.cmake                 |  1 +
 himbaechel/uarch/example/CMakeLists.txt |  2 ++
 himbaechel/uarch/gowin/CMakeLists.txt   | 32 +++++++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 himbaechel/uarch/example/CMakeLists.txt
 create mode 100644 himbaechel/uarch/gowin/CMakeLists.txt

diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake
index f4d59c0f4c..cf4477e351 100644
--- a/himbaechel/family.cmake
+++ b/himbaechel/family.cmake
@@ -1,5 +1,6 @@
 set(HIMBAECHEL_UARCHES "example;gowin")
 foreach(uarch ${HIMBAECHEL_UARCHES})
+	add_subdirectory(${family}/uarch/${uarch})
     aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES)
     foreach(target ${family_targets})
         target_sources(${target} PRIVATE ${HM_UARCH_FILES})
diff --git a/himbaechel/uarch/example/CMakeLists.txt b/himbaechel/uarch/example/CMakeLists.txt
new file mode 100644
index 0000000000..bc1c3b5953
--- /dev/null
+++ b/himbaechel/uarch/example/CMakeLists.txt
@@ -0,0 +1,2 @@
+message(STATUS "Configuring Himbaechel-Example uarch")
+
diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
new file mode 100644
index 0000000000..ff35ae2f2f
--- /dev/null
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -0,0 +1,32 @@
+message(STATUS "Configuring Himbaechel-Gowin uarch")
+cmake_minimum_required(VERSION 3.5)
+project(himbaechel-gowin-chipdb NONE)
+
+find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
+set(ALL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18)
+set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
+    "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
+message(STATUS "Enabled Himbaechel-Gowin devices: ${GOWIN_DEVICES}")
+
+set(chipdb_binaries)
+file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
+foreach(device ${GOWIN_DEVICES})
+    if(NOT device IN_LIST ALL_GOWIN_DEVICES)
+		message(FATAL_ERROR "Device ${device} is not a supported Gowin device")
+    endif()
+
+	set(device_bba chipdb/chipdb-${device}.bba)
+	set(device_bin chipdb/chipdb-${device}.bin)
+	add_custom_command(
+		OUTPUT ${device_bin}
+		COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py -d ${device} -o ${device_bba}
+		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}
+		DEPENDS
+			bbasm
+			${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py
+			${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+		VERBATIM)
+	list(APPEND chipdb_binaries ${device_bin})
+endforeach()
+
+add_custom_target(chipdb-himbaechel-gowin ALL DEPENDS ${chipdb_binaries})

From f42805984cefc4bd95a80390271f391958bd1ea8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 20 Aug 2023 07:32:30 +1000
Subject: [PATCH 459/712] gowin: Himbaechel. Improve CMake thing a little

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index ff35ae2f2f..7bf9573d69 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -20,7 +20,9 @@ foreach(device ${GOWIN_DEVICES})
 	add_custom_command(
 		OUTPUT ${device_bin}
 		COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py -d ${device} -o ${device_bba}
-		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}
+		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}.new
+        # atomically update
+        COMMAND ${CMAKE_COMMAND} -E rename ${device_bin}.new ${device_bin}
 		DEPENDS
 			bbasm
 			${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py

From 6513299126638b6a8d35d45a721e74f5fba9cf8d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 21 Aug 2023 19:52:38 +1000
Subject: [PATCH 460/712] gowin: Himbaechel. Handling of disabled units

Using  extra cell functions to mark disabled units using the PLL example.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc        | 4 ++++
 himbaechel/uarch/gowin/gowin.cc          | 8 ++------
 himbaechel/uarch/gowin/gowin_arch_gen.py | 9 +++++++++
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index f13560ba65..86c39e3410 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -190,6 +190,10 @@ struct GowinGlobalRouter
             NPNR_ASSERT(driver.cell->bel != BelId());
             IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
             for (size_t i = 0; i < pin_func.size(); ++i) {
+                if (ctx->debug) {
+                    log_info("bel:%s, pin func: %lu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
+                             pin_func[i].str(ctx).c_str());
+                }
                 if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
                     if (ctx->debug) {
                         log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index e364ea677c..bf898564cc 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -113,14 +113,10 @@ void GowinImpl::init(Context *ctx)
         }
     }
 
-    if (ctx->debug) {
-        log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
-    }
+    // log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
     for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
         if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
-            if (ctx->debug) {
-                log_info("i:%d %s\n", i, package_idx.c_str(ctx));
-            }
+            // log_info("i:%d %s\n", i, package_idx.c_str(ctx));
             ctx->package_info = &ctx->chip_info->packages[i];
             break;
         }
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 0921c0895e..a074685c46 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -565,9 +565,18 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
     tiletype = f"{typename}_{ttyp}"
     if tdesc.sfx != 0:
         tiletype += f"_{tdesc.sfx}"
+
+    # disabled PLLs
+    if tdesc.extra_func and 'disabled' in tdesc.extra_func and 'PLL' in tdesc.extra_func['disabled']:
+        tiletype += '_disabled'
+        tt = chip.create_tile_type(tiletype)
+        tt.extra_data = TileExtraData(chip.strs.id(typename))
+        tdesc.tiletype = tiletype
+        return tt
     tt = chip.create_tile_type(tiletype)
     tt.extra_data = TileExtraData(chip.strs.id(typename))
 
+
     # wires
     if chip.name == 'GW1NS-4':
         pll_name = 'PLLVR'

From aca14cc4208431482e61eec947a37e6c2365de6f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 23 Aug 2023 14:58:58 +1000
Subject: [PATCH 461/712] gowin: Himbaechel. Install bases

Install the Himbaechel gowin chipdb .bin files to
/usr/local/nextpnr/himbaehel/gowin

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index 7bf9573d69..70c121fb4e 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -3,15 +3,15 @@ cmake_minimum_required(VERSION 3.5)
 project(himbaechel-gowin-chipdb NONE)
 
 find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
-set(ALL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18)
-set(GOWIN_DEVICES ${ALL_GOWIN_DEVICES} CACHE STRING
-    "Include support for these Gowin devices (available: ${ALL_GOWIN_DEVICES})")
-message(STATUS "Enabled Himbaechel-Gowin devices: ${GOWIN_DEVICES}")
+set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
+set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES} CACHE STRING
+    "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
+message(STATUS "Enabled Himbaechel-Gowin devices: ${HIMBAECHEL_GOWIN_DEVICES}")
 
 set(chipdb_binaries)
 file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
-foreach(device ${GOWIN_DEVICES})
-    if(NOT device IN_LIST ALL_GOWIN_DEVICES)
+foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
+    if(NOT device IN_LIST ALL_HIMBAECHEL_GOWIN_DEVICES)
 		message(FATAL_ERROR "Device ${device} is not a supported Gowin device")
     endif()
 
@@ -32,3 +32,5 @@ foreach(device ${GOWIN_DEVICES})
 endforeach()
 
 add_custom_target(chipdb-himbaechel-gowin ALL DEPENDS ${chipdb_binaries})
+install(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb/ DESTINATION share/nextpnr/himbaechel/gowin
+	    PATTERN "*.bba" EXCLUDE)

From 3e0b9826b507b73a787b5ffa77d55aece3821038 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 25 Aug 2023 18:40:29 +1000
Subject: [PATCH 462/712] gowin: Himbaechel. Fix problems.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt |  1 +
 himbaechel/uarch/gowin/pack.cc        | 59 ++++++++++++---------------
 2 files changed, 26 insertions(+), 34 deletions(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index 70c121fb4e..28a4573621 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -4,6 +4,7 @@ project(himbaechel-gowin-chipdb NONE)
 
 find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
+set(ALL_HIMBAECHEL_GOWIN_DEVICES "")
 set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES} CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
 message(STATUS "Enabled Himbaechel-Gowin devices: ${HIMBAECHEL_GOWIN_DEVICES}")
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index e4a729bd28..3529c230e7 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -57,10 +57,10 @@ struct GowinPacker
         log_info("simple:%s\n", ctx->nameOf(&ci));
         ci.addInput(id_OEN);
         if (ci.type == id_OBUF) {
-            ci.connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_GND")].get());
+            ci.connectPort(id_OEN, ctx->nets.at(ctx->id("$PACKER_GND")).get());
         } else {
             NPNR_ASSERT(ci.type == id_IBUF);
-            ci.connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            ci.connectPort(id_OEN, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
         }
     }
 
@@ -81,10 +81,10 @@ struct GowinPacker
             ci.disconnectPort(port);
             ci.addInput(port);
             if (net_name == id_VSS) {
-                ci.connectPort(port, ctx->nets[ctx->id("$PACKER_GND")].get());
+                ci.connectPort(port, ctx->nets.at(ctx->id("$PACKER_GND")).get());
             } else {
                 NPNR_ASSERT(net_name == id_VCC);
-                ci.connectPort(port, ctx->nets[ctx->id("$PACKER_VCC")].get());
+                ci.connectPort(port, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             }
         };
 
@@ -325,11 +325,11 @@ struct GowinPacker
         std::vector<IdString> pins = ctx->getBelPins(bel);
         if (std::find(pins.begin(), pins.end(), id_DAADJ0) != pins.end()) {
             ci.addInput(id_DAADJ0);
-            ci.connectPort(id_DAADJ0, ctx->nets[ctx->id("$PACKER_GND")].get());
+            ci.connectPort(id_DAADJ0, ctx->nets.at(ctx->id("$PACKER_GND")).get());
         }
         if (std::find(pins.begin(), pins.end(), id_DAADJ1) != pins.end()) {
             ci.addInput(id_DAADJ1);
-            ci.connectPort(id_DAADJ1, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            ci.connectPort(id_DAADJ1, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
         }
     }
 
@@ -483,8 +483,8 @@ struct GowinPacker
         BelId io_bel = gwu.get_io_bel_from_iologic(bel);
         if (!ctx->checkBelAvail(io_bel)) {
             if (!is_diff_io(io_bel)) {
-                log_error("Can't place %s at %s because of %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
-                          ctx->nameOf(ctx->getBoundBelCell(io_bel)));
+                log_error("Can't place %s at %s because of a conflict with another IO %s\n", ctx->nameOf(&ci),
+                          ctx->nameOfBel(bel), ctx->nameOf(ctx->getBoundBelCell(io_bel)));
             }
         }
 
@@ -505,6 +505,7 @@ struct GowinPacker
 
     void reconnect_ides_outs(CellInfo *ci)
     {
+        IdString dest_ports[] = {id_Q9, id_Q8, id_Q7, id_Q6, id_Q5, id_Q4, id_Q3, id_Q2};
         switch (ci->type.hash()) {
         case ID_IDDR: /* fall-through*/
         case ID_IDDRC:
@@ -512,29 +513,19 @@ struct GowinPacker
             ci->renamePort(id_Q0, id_Q8);
             break;
         case ID_IDES4:
-            ci->renamePort(id_Q3, id_Q9);
-            ci->renamePort(id_Q2, id_Q8);
-            ci->renamePort(id_Q1, id_Q7);
-            ci->renamePort(id_Q0, id_Q6);
+            for (int i = 0; i < 4; ++i) {
+                ci->renamePort(ctx->idf("Q%d", 3 - i), dest_ports[i]);
+            }
             break;
         case ID_IVIDEO:
-            ci->renamePort(id_Q6, id_Q9);
-            ci->renamePort(id_Q5, id_Q8);
-            ci->renamePort(id_Q4, id_Q7);
-            ci->renamePort(id_Q3, id_Q6);
-            ci->renamePort(id_Q2, id_Q5);
-            ci->renamePort(id_Q1, id_Q4);
-            ci->renamePort(id_Q0, id_Q3);
+            for (int i = 0; i < 7; ++i) {
+                ci->renamePort(ctx->idf("Q%d", 6 - i), dest_ports[i]);
+            }
             break;
         case ID_IDES8:
-            ci->renamePort(id_Q7, id_Q9);
-            ci->renamePort(id_Q6, id_Q8);
-            ci->renamePort(id_Q5, id_Q7);
-            ci->renamePort(id_Q4, id_Q6);
-            ci->renamePort(id_Q3, id_Q5);
-            ci->renamePort(id_Q2, id_Q4);
-            ci->renamePort(id_Q1, id_Q3);
-            ci->renamePort(id_Q0, id_Q2);
+            for (int i = 0; i < 8; ++i) {
+                ci->renamePort(ctx->idf("Q%d", 7 - i), dest_ports[i]);
+            }
             break;
         default:
             break;
@@ -1008,13 +999,13 @@ struct GowinPacker
         if (cin_net->name == ctx->id("$PACKER_GND")) {
             cin_ci->params[id_ALU_MODE] = std::string("C2L");
             cin_ci->addInput(id_I2);
-            cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             return cin_ci;
         }
         if (cin_net->name == ctx->id("$PACKER_VCC")) {
             cin_ci->params[id_ALU_MODE] = std::string("ONE2C");
             cin_ci->addInput(id_I2);
-            cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             return cin_ci;
         }
         // CIN from logic
@@ -1023,7 +1014,7 @@ struct GowinPacker
         cin_ci->connectPort(id_I1, cin_net);
         cin_ci->connectPort(id_I3, cin_net);
         cin_ci->addInput(id_I2);
-        cin_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+        cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
         cin_ci->params[id_ALU_MODE] = std::string("0"); // ADD
         return cin_ci;
     }
@@ -1045,7 +1036,7 @@ struct GowinPacker
         cout_ci->addOutput(id_SUM);
         cout_ci->connectPort(id_SUM, cout_net);
         cout_ci->addInput(id_I2);
-        cout_ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+        cout_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
 
         cout_ci->params[id_ALU_MODE] = std::string("C2L");
         return cout_ci;
@@ -1111,7 +1102,7 @@ struct GowinPacker
                         // XXX I2 is pin C which must be set to 1 for all ALU modes except MUL
                         // we use only mode 2 ADDSUB so create and connect this pin
                         ci->addInput(id_I2);
-                        ci->connectPort(id_I2, ctx->nets[ctx->id("$PACKER_VCC")].get());
+                        ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
 
                         ++alu_chain_len;
 
@@ -1225,7 +1216,7 @@ struct GowinPacker
                 ci->constr_z = BelZ::RAMW_Z;
 
                 ci->addInput(id_CE);
-                ci->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC")].get());
+                ci->connectPort(id_CE, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
 
                 // RAD networks
                 NetInfo *rad[4];
@@ -1288,7 +1279,7 @@ struct GowinPacker
             // make default GSR
             auto gsr_cell = std::make_unique<CellInfo>(ctx, id_GSR, id_GSR);
             gsr_cell->addInput(id_GSRI);
-            gsr_cell->connectPort(id_GSRI, ctx->nets[ctx->id("$PACKER_VCC")].get());
+            gsr_cell->connectPort(id_GSRI, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             ctx->cells[gsr_cell->name] = std::move(gsr_cell);
         }
         if (ctx->verbose) {

From 98b09c369f08376ad1ee796e1bef57c8aa1f92a0 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 31 Aug 2023 17:12:04 +1000
Subject: [PATCH 463/712] gowin: Himbaechel. Fix the device selection

Slightly change the Gowin device selection mechanism for database generation.
By default, nothing is generated as before.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index 28a4573621..e21bf2ea11 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -4,8 +4,7 @@ project(himbaechel-gowin-chipdb NONE)
 
 find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
-set(ALL_HIMBAECHEL_GOWIN_DEVICES "")
-set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES} CACHE STRING
+set(HIMBAECHEL_GOWIN_DEVICES "" CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
 message(STATUS "Enabled Himbaechel-Gowin devices: ${HIMBAECHEL_GOWIN_DEVICES}")
 

From a9a9251e42f738ce6e1e347af858bf3c0f36bfae Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 31 Aug 2023 10:30:19 +0200
Subject: [PATCH 464/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 machxo2/pack.cc | 3 ++-
 nexus/pack.cc   | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index f20c9378a1..d3be47231c 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1349,7 +1349,8 @@ class MachXO2Packer
                         }
                     }
                     if (!found)
-                        log_error("Unsupported frequency '%s' on %s '%s'\n", freq.c_str(), ci->type.c_str(ctx), ci->name.c_str(ctx));
+                        log_error("Unsupported frequency '%s' on %s '%s'\n", freq.c_str(), ci->type.c_str(ctx),
+                                  ci->name.c_str(ctx));
                 }
             }
         }
diff --git a/nexus/pack.cc b/nexus/pack.cc
index d41766dc51..53f16033e7 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -94,7 +94,8 @@ Property Arch::parse_lattice_param(const Property &val, IdString prop, int width
         if (int(val.str.size()) > width) {
             for (auto b : val.str.substr(width)) {
                 if (b == Property::S1)
-                    log_error("Found bitvector value for property %s.%s with width greater than %d - perhaps a string was "
+                    log_error("Found bitvector value for property %s.%s with width greater than %d - perhaps a string "
+                              "was "
                               "converted to bits?\n",
                               ci, nameOf(prop), width);
             }

From 79c6840fefcf84d001b0c1b269cd0198ee9d3dba Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 1 Sep 2023 14:54:27 +0200
Subject: [PATCH 465/712] ecp5: Improve packer robustness to FF dangling M
 input

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/pack.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 4ef2e92a3e..df1398601b 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -234,6 +234,12 @@ class Ecp5Packer
             CellInfo *ci = cell.second.get();
             if (is_ff(ctx, ci)) {
                 NetInfo *di = ci->getPort(id_DI);
+                NetInfo *m = ci->getPort(id_M);
+                if (ci->ports.count(id_M) && (!m || !m->driver.cell)) {
+                    // M input is floating. Remove it, so renamePort doesn't hit trouble
+                    ci->disconnectPort(id_M);
+                    ci->ports.erase(id_M);
+                }
                 if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
                     CellInfo *comb = di->driver.cell;
                     if (comb->cluster != ClusterId()) {

From 9994ba1d19bb589900abfca28ecea23bf4d8a872 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 4 Sep 2023 15:49:07 +0200
Subject: [PATCH 466/712] json: Fix handling of offsets in backend

Signed-off-by: gatecat <gatecat@ds0.me>
---
 json/jsonwrite.cc | 33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/json/jsonwrite.cc b/json/jsonwrite.cc
index c35df4ae0b..b7294cb38a 100644
--- a/json/jsonwrite.cc
+++ b/json/jsonwrite.cc
@@ -60,8 +60,10 @@ void write_parameters(std::ostream &f, Context *ctx, const dict<IdString, Proper
 struct PortGroup
 {
     std::string name;
+    std::vector<std::pair<int, int>> grouped_bits; // (index, bit)
     std::vector<int> bits;
     PortType dir;
+    int offset = 0;
 };
 
 std::vector<PortGroup> group_ports(Context *ctx, const dict<IdString, PortInfo> &ports, bool is_cell = false)
@@ -71,9 +73,11 @@ std::vector<PortGroup> group_ports(Context *ctx, const dict<IdString, PortInfo>
     for (auto &pair : ports) {
         std::string name = pair.second.name.str(ctx);
         if ((name.back() != ']') || (name.find('[') == std::string::npos)) {
-            groups.push_back({name,
-                              {is_cell ? (pair.second.net ? pair.second.net->name.index : -1) : pair.first.index},
-                              pair.second.type});
+            groups.push_back(
+                    {name,
+                     {{0, (is_cell ? (pair.second.net ? pair.second.net->name.index : -1) : pair.first.index)}},
+                     {},
+                     pair.second.type});
         } else {
             int off1 = int(name.find_last_of('['));
             std::string basename = name.substr(0, off1);
@@ -81,14 +85,24 @@ std::vector<PortGroup> group_ports(Context *ctx, const dict<IdString, PortInfo>
 
             if (!base_to_group.count(basename)) {
                 base_to_group[basename] = groups.size();
-                groups.push_back({basename, std::vector<int>(index + 1, -1), pair.second.type});
+                groups.push_back({basename, {}, {}, pair.second.type});
             }
 
             auto &grp = groups.at(base_to_group[basename]);
-            if (int(grp.bits.size()) <= index)
-                grp.bits.resize(index + 1, -1);
-            NPNR_ASSERT(grp.bits.at(index) == -1);
-            grp.bits.at(index) = pair.second.net ? pair.second.net->name.index : (is_cell ? -1 : pair.first.index);
+            grp.grouped_bits.emplace_back(index, pair.second.net ? pair.second.net->name.index
+                                                                 : (is_cell ? -1 : pair.first.index));
+        }
+    }
+    for (auto &group : groups) {
+        NPNR_ASSERT(!group.grouped_bits.empty());
+        // find offset
+        group.offset = std::min_element(group.grouped_bits.begin(), group.grouped_bits.end())->first;
+        for (auto bit : group.grouped_bits) {
+            int vec_idx = bit.first - group.offset;
+            if (vec_idx >= int(group.bits.size()))
+                group.bits.resize(vec_idx + 1, -1);
+            NPNR_ASSERT(group.bits.at(vec_idx) == -1);
+            group.bits.at(vec_idx) = bit.second;
         }
     }
     return groups;
@@ -137,6 +151,9 @@ void write_module(std::ostream &f, Context *ctx)
         f << stringf("          \"direction\": \"%s\",\n", port.dir == PORT_IN      ? "input"
                                                            : port.dir == PORT_INOUT ? "inout"
                                                                                     : "output");
+        if (port.offset != 0) {
+            f << stringf("          \"offset\": %d,\n", port.offset);
+        }
         f << stringf("          \"bits\": %s\n", format_port_bits(port, dummy_idx).c_str());
         f << stringf("        }");
         first = false;

From 732b329e7dd3ce66dae3919537316975af4515e8 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 31 Aug 2023 17:50:45 +0000
Subject: [PATCH 467/712] himbaechel/gowin: recognize
 -DHIMBAECHEL_GOWIN_DEVICES=all.

---
 himbaechel/uarch/gowin/CMakeLists.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index e21bf2ea11..f8786626ee 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -6,6 +6,9 @@ find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
 set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
 set(HIMBAECHEL_GOWIN_DEVICES "" CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
+if(HIMBAECHEL_GOWIN_DEVICES STREQUAL "all")
+	set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES})
+endif()
 message(STATUS "Enabled Himbaechel-Gowin devices: ${HIMBAECHEL_GOWIN_DEVICES}")
 
 set(chipdb_binaries)

From eef5243fba587e2d80056ec6dd7f04de140a4a21 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Thu, 31 Aug 2023 17:52:05 +0000
Subject: [PATCH 468/712] himbaechel/gowin: recognize
 -DAPYCULA_INSTALL_PREFIX=.../virtualenv.

This option can be empty, in which case the virtualenv is left
exactly as it was in the build environment.
---
 himbaechel/uarch/gowin/CMakeLists.txt | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index f8786626ee..dc1250ce9e 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -11,6 +11,19 @@ if(HIMBAECHEL_GOWIN_DEVICES STREQUAL "all")
 endif()
 message(STATUS "Enabled Himbaechel-Gowin devices: ${HIMBAECHEL_GOWIN_DEVICES}")
 
+if(DEFINED ENV{APYCULA_INSTALL_PREFIX})
+    set(apycula_default_install_prefix $ENV{APYCULA_INSTALL_PREFIX})
+endif()
+set(APYCULA_INSTALL_PREFIX ${apycula_default_install_prefix} CACHE STRING
+    "Apycula install prefix (virtualenv directory)")
+if(NOT APYCULA_INSTALL_PREFIX STREQUAL "")
+	message(STATUS "Apycula install prefix: ${APYCULA_INSTALL_PREFIX}")
+	set(apycula_Python3_EXECUTABLE ${APYCULA_INSTALL_PREFIX}/bin/python)
+else()
+	message(STATUS "Apycula install prefix: (using system Python)")
+	set(apycula_Python3_EXECUTABLE ${Python3_EXECUTABLE})
+endif()
+
 set(chipdb_binaries)
 file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
 foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
@@ -22,7 +35,7 @@ foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
 	set(device_bin chipdb/chipdb-${device}.bin)
 	add_custom_command(
 		OUTPUT ${device_bin}
-		COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py -d ${device} -o ${device_bba}
+		COMMAND ${apycula_Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py -d ${device} -o ${device_bba}
 		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}.new
         # atomically update
         COMMAND ${CMAKE_COMMAND} -E rename ${device_bin}.new ${device_bin}

From f9825c31302fe2de8a67698b0dd9717c5e2baad1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 7 Sep 2023 11:01:56 +0200
Subject: [PATCH 469/712] ice40: only set/clear negclk bit if IO clock actually
 used

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/bitstream.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 533f310a23..97883f954a 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -540,7 +540,8 @@ void write_asc(const Context *ctx, std::ostream &out)
                 bool val = (pin_type >> i) & 0x01;
                 set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
             }
-            set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
+            if (cell.second->getPort(id_INPUT_CLK) || cell.second->getPort(id_OUTPUT_CLK))
+                set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
 
             bool input_en = false;
             if ((ctx->wire_to_net[ctx->getBelPinWire(bel, id_D_IN_0).index] != nullptr) ||

From 78ee20b5da11b25a3aee4b2b4e966b0582a976a6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 4 Sep 2023 22:20:08 +1000
Subject: [PATCH 470/712] gowin: Himbaechel. Extend clock router

Now the clock router can place a buffer into the specified network,
which divides the network into two parts: from the source to the buffer,
routing occurs through any available PIPs, and after the buffer to the
sink, only through a dedicated global clock network.

This is made specifically for the Tangnano20k where the external
oscillator is soldered to a regular non-clock pin. But it can be used
for other purposes, you just need to remember that the recipient must be
a CLK input or output pin.

The port/network to set the buffer to is specified in the .CST file:

CLOCK_LOC "name" BUFG;

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   4 +
 himbaechel/uarch/gowin/cst.cc            |  12 ++-
 himbaechel/uarch/gowin/globals.cc        | 129 ++++++++++++++++++-----
 himbaechel/uarch/gowin/gowin.h           |   2 +
 himbaechel/uarch/gowin/gowin_arch_gen.py |  14 +++
 himbaechel/uarch/gowin/pack.cc           |  62 +++++++++--
 6 files changed, 186 insertions(+), 37 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index d9a7ca2bec..57938b0a4f 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1097,3 +1097,7 @@ X(HCLK_OUT1)
 X(HCLK_OUT2)
 X(HCLK_OUT3)
 
+// BUFG, clock buffers stuff
+X(BUFG)
+X(CLOCK)
+
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
index 8821eec8d8..e4df3f6119 100644
--- a/himbaechel/uarch/gowin/cst.cc
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -129,8 +129,16 @@ struct GowinCstReader
                         log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(ctx));
                         //}
                     } else {
-                        log_info("BUFG isn't supported\n");
-                        continue;
+                        auto ni = ctx->nets.find(net);
+                        if (ni == ctx->nets.end()) {
+                            log_info("Net %s not found\n", net.c_str(ctx));
+                            continue;
+                        }
+                        if (ctx->debug) {
+                            log_info("Mark net '%s' as CLOCK\n", net.c_str(ctx));
+                        }
+                        // XXX YES for now. May be put the number here
+                        ni->second->attrs[id_CLOCK] = Property(std::string("YES"));
                     }
                 } break;
                 case ioloc: { // IO_LOC name pin
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 86c39e3410..a34d4253f6 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -67,29 +67,14 @@ struct GowinGlobalRouter
 
     // Dedicated backwards BFS routing for global networks
     template <typename Tfilt>
-    bool backwards_bfs_route(NetInfo *net, store_index<PortRef> user_idx, int iter_limit, bool strict, Tfilt pip_filter)
+    bool backwards_bfs_route(NetInfo *net, WireId src, WireId dst, int iter_limit, bool strict, Tfilt pip_filter)
     {
+        // log_info("%s:%s->%s\n", net->name.c_str(ctx), ctx->nameOfWire(src), ctx->nameOfWire(dst));
         // Queue of wires to visit
         std::queue<WireId> visit;
         // Wire -> upstream pip
         dict<WireId, PipId> backtrace;
 
-        // Lookup source and destination wires
-        WireId src = ctx->getNetinfoSourceWire(net);
-        WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(user_idx), 0);
-
-        if (src == WireId())
-            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
-                      ctx->nameOf(net->driver.port));
-
-        if (dst == WireId())
-            log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
-                      ctx->nameOf(net->users.at(user_idx).cell), ctx->nameOf(net->users.at(user_idx).port));
-
-        if (ctx->getBoundWireNet(src) != net) {
-            ctx->bindWire(src, net, STRENGTH_LOCKED);
-        }
-
         if (src == dst) {
             // Nothing more to do
             return true;
@@ -106,24 +91,29 @@ struct GowinGlobalRouter
             // Search uphill pips
             for (PipId pip : ctx->getPipsUphill(cursor)) {
                 // Skip pip if unavailable, and not because it's already used for this net
-                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net)
+                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net) {
                     continue;
+                }
                 WireId prev = ctx->getPipSrcWire(pip);
                 // Ditto for the upstream wire
-                if (!ctx->checkWireAvail(prev) && ctx->getBoundWireNet(prev) != net)
+                if (!ctx->checkWireAvail(prev) && ctx->getBoundWireNet(prev) != net) {
                     continue;
+                }
                 // Skip already visited wires
-                if (backtrace.count(prev))
+                if (backtrace.count(prev)) {
                     continue;
+                }
                 // Apply our custom pip filter
-                if (!pip_filter(pip))
+                if (!pip_filter(pip)) {
                     continue;
+                }
                 // Add to the queue
                 visit.push(prev);
                 backtrace[prev] = pip;
                 // Check if we are done yet
-                if (prev == src)
+                if (prev == src) {
                     goto done;
+                }
             }
             if (false) {
             done:
@@ -137,18 +127,22 @@ struct GowinGlobalRouter
             // Create a list of pips on the routed path
             while (true) {
                 PipId pip = backtrace.at(cursor);
-                if (pip == PipId())
+                if (pip == PipId()) {
                     break;
+                }
                 pips.push_back(pip);
                 cursor = ctx->getPipDstWire(pip);
+                // log_info(">> %s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(cursor));
             }
             // Reverse that list
             std::reverse(pips.begin(), pips.end());
             // Bind pips until we hit already-bound routing
             for (PipId pip : pips) {
                 WireId dst = ctx->getPipDstWire(pip);
-                if (ctx->getBoundWireNet(dst) == net)
+                // log_info("%s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(dst));
+                if (ctx->getBoundWireNet(dst) == net) {
                     break;
+                }
                 ctx->bindPip(pip, net, STRENGTH_LOCKED);
             }
             return true;
@@ -159,29 +153,90 @@ struct GowinGlobalRouter
             } else {
                 log_warning("Failed to route net '%s' from %s to %s using dedicated routing.\n", ctx->nameOf(net),
                             ctx->nameOfWire(src), ctx->nameOfWire(dst));
-                ctx->unbindWire(src);
                 return false;
             }
         }
     }
 
-    void route_clk_net(NetInfo *net)
+    bool route_direct_net(NetInfo *net)
     {
+        // Lookup source and destination wires
+        WireId src = ctx->getNetinfoSourceWire(net);
+        if (src == WireId())
+            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
+                      ctx->nameOf(net->driver.port));
+
+        if (ctx->getBoundWireNet(src) != net) {
+            ctx->bindWire(src, net, STRENGTH_LOCKED);
+        }
+
         bool routed = false;
         for (auto usr : net->users.enumerate()) {
-            routed = backwards_bfs_route(net, usr.index, 1000000, false, [&](PipId pip) {
+            WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
+            if (dst == WireId()) {
+                log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
+                          ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
+            }
+            routed = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
                 return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
             });
             if (!routed) {
                 break;
             }
         }
+        if (!routed) {
+            ctx->unbindWire(src);
+        }
+        return routed;
+    }
+
+    void route_buffered_net(NetInfo *net)
+    {
+        // a) route net after buf using the buf input as source
+        CellInfo *buf_ci = net->driver.cell;
+        WireId src = ctx->getBelPinWire(buf_ci->bel, id_I);
+
+        NetInfo *net_before_buf = buf_ci->getPort(id_I);
+        NPNR_ASSERT(net_before_buf != nullptr);
 
-        if (routed) {
+        if (src == WireId()) {
+            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
+                      ctx->nameOf(net->driver.port));
+        }
+        ctx->bindWire(src, net, STRENGTH_LOCKED);
+
+        for (auto usr : net->users.enumerate()) {
+            WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
+            if (dst == WireId()) {
+                log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
+                          ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
+            }
+            // log_info(" usr wire: %s\n", ctx->nameOfWire(dst));
+            backwards_bfs_route(net, src, dst, 1000000, true,
+                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
+        }
+
+        // b) route net before buf from whatever to the buf input
+        WireId dst = src;
+        CellInfo *true_src_ci = net_before_buf->driver.cell;
+        src = ctx->getBelPinWire(true_src_ci->bel, net_before_buf->driver.port);
+        ctx->bindWire(src, net, STRENGTH_LOCKED);
+        ctx->unbindWire(dst);
+        backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) { return true; });
+        // remove net
+        buf_ci->movePortTo(id_O, true_src_ci, net_before_buf->driver.port);
+        net_before_buf->driver.cell = nullptr;
+    }
+
+    void route_clk_net(NetInfo *net)
+    {
+        if (route_direct_net(net)) {
             log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
         }
     }
 
+    bool driver_is_buf(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_BUFG, id_O); }
+
     bool driver_is_clksrc(const PortRef &driver)
     {
         // dedicated pins
@@ -219,11 +274,27 @@ struct GowinGlobalRouter
     void run(void)
     {
         log_info("Routing globals...\n");
+        // buffered nets first
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            CellInfo *drv = ni->driver.cell;
+            if (drv == nullptr) {
+                continue;
+            }
+            if (driver_is_buf(ni->driver)) {
+                if (ctx->verbose) {
+                    log_info("route buffered net '%s'\n", ctx->nameOf(ni));
+                }
+                route_buffered_net(ni);
+                continue;
+            }
+        }
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
-            if (drv == nullptr)
+            if (drv == nullptr) {
                 continue;
+            }
             if (driver_is_clksrc(ni->driver)) {
                 route_clk_net(ni);
                 continue;
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 7086bfdec8..f92049a5a5 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -88,6 +88,8 @@ enum
     IDES16_Z = 72,
     OSER16_Z = 73,
 
+    BUFG_Z = 74, // : 81 reserve just in case
+
     OSC_Z = 274,
     PLL_Z = 275,
     GSR_Z = 276,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index a074685c46..be507f384e 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -32,6 +32,8 @@
 IDES16_Z   = 72
 OSER16_Z   = 73
 
+BUFG_Z  = 74 # : 81 reserve just in case
+
 OSC_Z   = 274
 PLL_Z   = 275
 GSR_Z   = 276
@@ -291,6 +293,18 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                         tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
                     else:
                         tt.add_bel_pin(bel, port, wire, PinType.INPUT)
+        if func == 'buf':
+            for buf_type, wires in desc.items():
+                for i, wire in enumerate(wires):
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "TILE_CLK")
+                    wire_out = f'{buf_type}{i}_O'
+                    tt.create_wire(wire_out, "TILE_CLK")
+                    # XXX make Z from buf_type
+                    bel = tt.create_bel(f'{buf_type}{i}', buf_type, z = BUFG_Z + i)
+                    bel.flags = BEL_FLAG_GLOBAL
+                    tt.add_bel_pin(bel, "I", wire, PinType.INPUT)
+                    tt.add_bel_pin(bel, "O", wire_out, PinType.OUTPUT)
 
 def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     has_extra_func = (y, x) in db.extra_func
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 3529c230e7..e8cfecc73d 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -110,7 +110,7 @@ struct GowinPacker
             auto &ci = *cell.second;
             if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
                 continue;
-            NetInfo *i = ci.getPort(ctx->id("I"));
+            NetInfo *i = ci.getPort(id_I);
             if (i && i->driver.cell) {
                 if (!top_ports.count(CellTypePort(i->driver)))
                     log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
@@ -119,7 +119,7 @@ struct GowinPacker
                     i->driver.cell->attrs[attr.first] = attr.second;
                 }
             }
-            NetInfo *o = ci.getPort(ctx->id("O"));
+            NetInfo *o = ci.getPort(id_O);
             if (o) {
                 for (auto &usr : o->users) {
                     if (!top_ports.count(CellTypePort(usr)))
@@ -128,9 +128,21 @@ struct GowinPacker
                     for (const auto &attr : ci.attrs) {
                         usr.cell->attrs[attr.first] = attr.second;
                     }
+                    // network/port attributes that can be set in the
+                    // restriction file and that need to be transferred to real
+                    // networks before nextpnr buffers are removed.
+                    NetInfo *dst_net = usr.cell->getPort(id_O);
+                    if (dst_net != nullptr) {
+                        for (const auto &attr : o->attrs) {
+                            if (!attr.first.in(id_CLOCK)) {
+                                continue;
+                            }
+                            dst_net->attrs[attr.first] = attr.second;
+                        }
+                    }
                 }
             }
-            NetInfo *io = ci.getPort(ctx->id("IO"));
+            NetInfo *io = ci.getPort(id_IO);
             if (io && io->driver.cell) {
                 if (!top_ports.count(CellTypePort(io->driver)))
                     log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
@@ -139,9 +151,9 @@ struct GowinPacker
                     io->driver.cell->attrs[attr.first] = attr.second;
                 }
             }
-            ci.disconnectPort(ctx->id("I"));
-            ci.disconnectPort(ctx->id("O"));
-            ci.disconnectPort(ctx->id("IO"));
+            ci.disconnectPort(id_I);
+            ci.disconnectPort(id_O);
+            ci.disconnectPort(id_IO);
             to_remove.push_back(ci.name);
         }
         for (IdString cell_name : to_remove)
@@ -1317,6 +1329,41 @@ struct GowinPacker
         }
     }
 
+    // =========================================
+    // Create entry points to the clock system
+    // =========================================
+    void pack_buffered_nets()
+    {
+        log_info("Pack buffered nets..\n");
+
+        for (auto &net : ctx->nets) {
+            auto &ni = *net.second;
+            if (ni.driver.cell == nullptr || ni.attrs.count(id_CLOCK) == 0 || ni.users.empty()) {
+                continue;
+            }
+
+            // make new BUF cell single user for the net driver
+            IdString buf_name = ctx->idf("%s_BUFG", net.first.c_str(ctx));
+            ctx->createCell(buf_name, id_BUFG);
+            CellInfo *buf_ci = ctx->cells.at(buf_name).get();
+            buf_ci->addInput(id_I);
+            auto s_net = std::make_unique<NetInfo>(ctx->idf("$PACKER_BUF_%s", net.first.c_str(ctx)));
+            NetInfo *buf_ni = s_net.get();
+            ctx->nets[s_net->name] = std::move(s_net);
+
+            if (ctx->verbose) {
+                log_info("Create buf '%s' with IN net '%s'\n", buf_name.c_str(ctx), buf_ni->name.c_str(ctx));
+            }
+            // move driver
+            CellInfo *driver_cell = ni.driver.cell;
+            IdString driver_port = ni.driver.port;
+
+            driver_cell->movePortTo(driver_port, buf_ci, id_O);
+            buf_ci->connectPort(id_I, buf_ni);
+            driver_cell->connectPort(driver_port, buf_ni);
+        }
+    }
+
     void run(void)
     {
         handle_constants();
@@ -1348,6 +1395,9 @@ struct GowinPacker
         ctx->check();
 
         pack_ram16sdp4();
+        ctx->check();
+
+        pack_buffered_nets();
 
         ctx->fixupHierarchy();
         ctx->check();

From 890d7f7617999e6ad154768169c252bcca29258f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 7 Sep 2023 19:04:42 +1000
Subject: [PATCH 471/712] gowin: Himbaechel. Use a more appropriate function

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index e8cfecc73d..55cc24422f 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1347,9 +1347,7 @@ struct GowinPacker
             ctx->createCell(buf_name, id_BUFG);
             CellInfo *buf_ci = ctx->cells.at(buf_name).get();
             buf_ci->addInput(id_I);
-            auto s_net = std::make_unique<NetInfo>(ctx->idf("$PACKER_BUF_%s", net.first.c_str(ctx)));
-            NetInfo *buf_ni = s_net.get();
-            ctx->nets[s_net->name] = std::move(s_net);
+            NetInfo *buf_ni = ctx->createNet(ctx->idf("$PACKER_BUF_%s", net.first.c_str(ctx)));
 
             if (ctx->verbose) {
                 log_info("Create buf '%s' with IN net '%s'\n", buf_name.c_str(ctx), buf_ni->name.c_str(ctx));

From 3e1e7838732d30bc2725f2196c4c3ae4af1ae159 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 25 Aug 2023 12:04:39 +0200
Subject: [PATCH 472/712] himbaechel: Initial timing support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .../viaduct/example/synth_viaduct_example.tcl |   2 +-
 himbaechel/arch.cc                            | 178 ++++++++++++
 himbaechel/arch.h                             |  97 ++++++-
 himbaechel/archdefs.h                         |   1 +
 himbaechel/chipdb.h                           |  17 +-
 himbaechel/himbaechel_dbgen/bba.py            |   3 +
 himbaechel/himbaechel_dbgen/chip.py           | 272 +++++++++++++++++-
 himbaechel/main.cc                            |   3 +
 himbaechel/uarch/example/example_arch_gen.py  |  38 ++-
 9 files changed, 586 insertions(+), 25 deletions(-)

diff --git a/generic/viaduct/example/synth_viaduct_example.tcl b/generic/viaduct/example/synth_viaduct_example.tcl
index a9d18f5612..051423b91c 100644
--- a/generic/viaduct/example/synth_viaduct_example.tcl
+++ b/generic/viaduct/example/synth_viaduct_example.tcl
@@ -2,7 +2,7 @@
 # tcl synth_viaduct_example.tcl {out.json}
 
 yosys read_verilog -lib [file dirname [file normalize $argv0]]/example_prims.v
-yosys hierarchy -check
+yosys hierarchy -check -top top
 yosys proc
 yosys flatten
 yosys tribuf -logic
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index f7ca2357ee..df576333d0 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -63,6 +63,35 @@ Arch::Arch(ArchArgs args)
         IdString::initialize_add(this, chip_info->extra_constids->bba_ids[i].get(),
                                  i + chip_info->extra_constids->known_id_count);
     }
+    // Select speed grade
+    if (args.speed.empty()) {
+        if (chip_info->speed_grades.ssize() == 0) {
+            // no timing information and no speed grade specified
+            speed_grade = nullptr;
+        } else if (chip_info->speed_grades.ssize() == 1) {
+            // speed grade not specified but only one available; use it
+            speed_grade = &(chip_info->speed_grades[0]);
+        } else {
+            std::string available_speeds = "";
+            for (const auto &speed_data : chip_info->speed_grades) {
+                if (!available_speeds.empty())
+                    available_speeds += ", ";
+                available_speeds += IdString(speed_data.name).c_str(this);
+            }
+            log_error("Speed grade must be specified using --speed (available options: %s).\n",
+                      available_speeds.c_str());
+        }
+    } else {
+        for (const auto &speed_data : chip_info->speed_grades) {
+            if (IdString(speed_data.name) == id(args.speed)) {
+                speed_grade = &speed_data;
+                break;
+            }
+        }
+        if (!speed_grade) {
+            log_error("Speed grade '%s' not found in database.\n", args.speed.c_str());
+        }
+    }
     init_tiles();
 }
 
@@ -167,6 +196,7 @@ bool Arch::place()
 
 bool Arch::route()
 {
+    set_fast_pip_delays(true);
     uarch->preRoute();
     std::string router = str_or_default(settings, id("router"), defaultRouter);
     bool result;
@@ -181,6 +211,7 @@ bool Arch::route()
     uarch->postRoute();
     getCtx()->settings[getCtx()->id("route")] = 1;
     archInfoToAttributes();
+    set_fast_pip_delays(false);
     return result;
 }
 
@@ -190,6 +221,8 @@ void Arch::assignArchInfo()
     for (auto &cell : cells) {
         CellInfo *ci = cell.second.get();
         ci->flat_index = cell_idx++;
+        if (speed_grade && ci->timing_index == -1)
+            ci->timing_index = get_cell_timing_idx(ci->type);
         for (auto &port : ci->ports) {
             // Default 1:1 cell:bel mapping
             if (!ci->cell_bel_pins.count(port.first))
@@ -259,4 +292,149 @@ const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
+void Arch::set_fast_pip_delays(bool fast_mode)
+{
+    if (fast_mode && !fast_pip_delays) {
+        // Have to rebuild these structures
+        drive_res.clear();
+        load_cap.clear();
+        for (auto &net : nets) {
+            for (auto &wire_pair : net.second->wires) {
+                PipId pip = wire_pair.second.pip;
+                if (pip == PipId())
+                    continue;
+                auto &pip_data = chip_pip_info(chip_info, pip);
+                auto pip_tmg = get_pip_timing(pip_data);
+                if (pip_tmg != nullptr) {
+                    WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
+                    load_cap[src] += pip_tmg->in_cap.slow_max;
+                    drive_res[dst] = (((pip_tmg->flags & 1) || !drive_res.count(src)) ? 0 : drive_res.at(src)) +
+                                     pip_tmg->out_res.slow_max;
+                }
+            }
+        }
+    }
+    fast_pip_delays = fast_mode;
+}
+
+// Helper for cell timing lookups
+namespace {
+template <typename Tres, typename Tgetter, typename Tkey>
+int db_binary_search(const RelSlice<Tres> &list, Tgetter key_getter, Tkey key)
+{
+    if (list.ssize() < 7) {
+        for (int i = 0; i < list.ssize(); i++) {
+            if (key_getter(list[i]) == key) {
+                return i;
+            }
+        }
+    } else {
+        int b = 0, e = list.ssize() - 1;
+        while (b <= e) {
+            int i = (b + e) / 2;
+            if (key_getter(list[i]) == key) {
+                return i;
+            }
+            if (key_getter(list[i]) > key)
+                e = i - 1;
+            else
+                b = i + 1;
+        }
+    }
+    return -1;
+}
+} // namespace
+
+int Arch::get_cell_timing_idx(IdString type_variant) const
+{
+    return db_binary_search(
+            speed_grade->cell_types, [](const CellTimingPOD &ct) { return ct.type_variant; }, type_variant.index);
+}
+
+bool Arch::lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayQuad &delay) const
+{
+    NPNR_ASSERT(type_idx != -1);
+    const auto &ct = speed_grade->cell_types[type_idx];
+    int to_pin_idx = db_binary_search(
+            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, to_port.index);
+    if (to_pin_idx == -1)
+        return false;
+    const auto &tp = ct.pins[to_pin_idx];
+    int arc_idx = db_binary_search(
+            tp.comb_arcs, [](const CellPinCombArcPOD &arc) { return arc.input; }, from_port.index);
+    if (arc_idx == -1)
+        return false;
+    delay = DelayQuad(tp.comb_arcs[arc_idx].delay.fast_min, tp.comb_arcs[arc_idx].delay.slow_max);
+    return true;
+}
+
+const RelSlice<CellPinRegArcPOD> *Arch::lookup_cell_seq_timings(int type_idx, IdString port) const
+{
+    NPNR_ASSERT(type_idx != -1);
+    const auto &ct = speed_grade->cell_types[type_idx];
+    int pin_idx = db_binary_search(
+            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
+    if (pin_idx == -1)
+        return nullptr;
+    return &ct.pins[pin_idx].reg_arcs;
+}
+
+TimingPortClass Arch::lookup_port_tmg_type(int type_idx, IdString port, PortType dir) const
+{
+
+    NPNR_ASSERT(type_idx != -1);
+    const auto &ct = speed_grade->cell_types[type_idx];
+    int pin_idx = db_binary_search(
+            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
+    if (pin_idx == -1)
+        return (dir == PORT_OUT) ? TMG_IGNORE : TMG_COMB_INPUT;
+    auto &pin = ct.pins[pin_idx];
+
+    if (dir == PORT_IN) {
+        if (pin.flags & CellPinTimingPOD::FLAG_CLK)
+            return TMG_CLOCK_INPUT;
+        return pin.reg_arcs.ssize() > 0 ? TMG_REGISTER_INPUT : TMG_COMB_INPUT;
+    } else {
+        // If a clock-to-out entry exists, then this is a register output
+        return pin.reg_arcs.ssize() > 0 ? TMG_REGISTER_OUTPUT : TMG_COMB_OUTPUT;
+    }
+}
+
+// TODO: adding uarch overrides for these?
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
+{
+    if (cell->timing_index == -1)
+        return false;
+    return lookup_cell_delay(cell->timing_index, fromPort, toPort, delay);
+}
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
+{
+    if (cell->timing_index == -1)
+        return TMG_IGNORE;
+    auto type = lookup_port_tmg_type(cell->timing_index, port, cell->ports.at(port).type);
+    clockInfoCount = 0;
+    if (type == TMG_REGISTER_INPUT || type == TMG_REGISTER_OUTPUT) {
+        auto reg_arcs = lookup_cell_seq_timings(cell->timing_index, port);
+        if (reg_arcs)
+            clockInfoCount = reg_arcs->ssize();
+    }
+    return type;
+}
+TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
+{
+    TimingClockingInfo result;
+    NPNR_ASSERT(cell->timing_index != -1);
+    auto reg_arcs = lookup_cell_seq_timings(cell->timing_index, port);
+    NPNR_ASSERT(reg_arcs);
+    const auto &arc = (*reg_arcs)[index];
+
+    result.clock_port = IdString(arc.clock);
+    result.edge = ClockEdge(arc.edge);
+    result.setup = DelayPair(arc.setup.fast_min, arc.setup.slow_max);
+    result.hold = DelayPair(arc.hold.fast_min, arc.hold.slow_max);
+    result.clockToQ = DelayQuad(arc.clk_q.fast_min, arc.clk_q.slow_max);
+
+    return result;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 9a664b17e6..d2e2e78d5c 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -388,6 +388,7 @@ struct ArchArgs
     std::string uarch;
     std::string chipdb;
     std::string device;
+    std::string speed;
     dict<std::string, std::string> options;
 };
 
@@ -426,6 +427,7 @@ struct Arch : BaseArch<ArchRanges>
     boost::iostreams::mapped_file_source blob_file;
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info = nullptr;
+    const SpeedGradePOD *speed_grade = nullptr;
 
     // Unlike Viaduct, we are not -generic based and therefore uarch must be non-nullptr
     std::unique_ptr<HimbaechelAPI> uarch;
@@ -522,7 +524,27 @@ struct Arch : BaseArch<ArchRanges>
     {
         return normalise_wire(pip.tile, chip_pip_info(chip_info, pip).dst_wire);
     }
-    DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(100); }
+    DelayQuad getPipDelay(PipId pip) const override
+    {
+        auto &pip_data = chip_pip_info(chip_info, pip);
+        auto pip_tmg = get_pip_timing(pip_data);
+        if (pip_tmg != nullptr) {
+            // TODO: multi corner analysis
+            WireId src = getPipSrcWire(pip);
+            uint64_t input_res = fast_pip_delays ? 0 : (drive_res.count(src) ? drive_res.at(src) : 0);
+            uint64_t input_cap = fast_pip_delays ? 0 : (load_cap.count(src) ? load_cap.at(src) : 0);
+            auto src_tmg = get_node_timing(src);
+            if (src_tmg != nullptr)
+                input_res += (src_tmg->res.slow_max / 2);
+            // Scale delay (fF * mOhm -> ps)
+            delay_t total_delay = (input_res * input_cap) / uint64_t(1e6);
+            total_delay += pip_tmg->int_delay.slow_max;
+            return DelayQuad(total_delay);
+        } else {
+            // Pip with no specified delay. Return a notional value so the router still has something to work with.
+            return DelayQuad(100);
+        }
+    }
     DownhillPipRange getPipsDownhill(WireId wire) const override
     {
         return DownhillPipRange(chip_info, get_tile_wire_range(wire));
@@ -547,11 +569,29 @@ struct Arch : BaseArch<ArchRanges>
     }
     void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
     {
+        if (!fast_pip_delays) {
+            auto &pip_data = chip_pip_info(chip_info, pip);
+            auto pip_tmg = get_pip_timing(pip_data);
+            if (pip_tmg != nullptr) {
+                WireId src = getPipSrcWire(pip);
+                load_cap[src] += pip_tmg->in_cap.slow_max;
+                drive_res[getPipDstWire(pip)] =
+                        (((pip_tmg->flags & 1) || !drive_res.count(src)) ? 0 : drive_res.at(src)) +
+                        pip_tmg->out_res.slow_max;
+            }
+        }
         uarch->notifyPipChange(pip, net);
         BaseArch::bindPip(pip, net, strength);
     }
     void unbindPip(PipId pip) override
     {
+        if (!fast_pip_delays) {
+            auto &pip_data = chip_pip_info(chip_info, pip);
+            auto pip_tmg = get_pip_timing(pip_data);
+            if (pip_tmg != nullptr) {
+                load_cap[getPipSrcWire(pip)] -= pip_tmg->in_cap.slow_max;
+            }
+        }
         uarch->notifyPipChange(pip, nullptr);
         BaseArch::unbindPip(pip);
     }
@@ -667,10 +707,65 @@ struct Arch : BaseArch<ArchRanges>
         }
     }
 
+    // -------------------------------------------------
+
+    const PipTimingPOD *get_pip_timing(const PipDataPOD &pip_data) const
+    {
+        int32_t idx = pip_data.timing_idx;
+        if (speed_grade && idx >= 0 && idx < speed_grade->pip_classes.ssize())
+            return &(speed_grade->pip_classes[idx]);
+        else
+            return nullptr;
+    }
+
+    const NodeTimingPOD *get_node_timing(WireId wire) const
+    {
+        int idx = -1;
+        if (!speed_grade)
+            return nullptr;
+        if (is_nodal_wire(chip_info, wire.tile, wire.index)) {
+            auto &shape = chip_node_shape(chip_info, wire.tile, wire.index);
+            idx = shape.timing_idx;
+        } else {
+            auto &wire_data = chip_wire_info(chip_info, wire);
+            idx = wire_data.timing_idx;
+        }
+        if (idx >= 0 && idx < speed_grade->node_classes.ssize())
+            return &(speed_grade->node_classes[idx]);
+        else
+            return nullptr;
+    }
+
+    // -------------------------------------------------
+
+    // Given cell type and variant, get the index inside the speed grade timing data
+    int get_cell_timing_idx(IdString type_variant) const;
+    // Return true and set delay if a comb path exists in a given cell timing index
+    bool lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayQuad &delay) const;
+    // Get setup and hold time and associated clock for a given cell timing index and signal
+    const RelSlice<CellPinRegArcPOD> *lookup_cell_seq_timings(int type_idx, IdString port) const;
+    // Attempt to look up port type based on timing database
+    TimingPortClass lookup_port_tmg_type(int type_idx, IdString port, PortType dir) const;
+
+    // -------------------------------------------------
+
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
+    // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
+    // Get the TimingClockingInfo of a port
+    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
+
     // -------------------------------------------------
     void init_tiles();
+    void set_fast_pip_delays(bool fast_mode);
     std::vector<IdString> tile_name;
     dict<IdString, int> tile_name2idx;
+
+    // Load capacitance and drive resistance for nodes
+    // TODO: does this `dict` hurt routing performance too much?
+    bool fast_pip_delays = false;
+    dict<WireId, uint64_t> drive_res;
+    dict<WireId, uint64_t> load_cap;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/archdefs.h b/himbaechel/archdefs.h
index b3ede1e25f..14c4b11fdc 100644
--- a/himbaechel/archdefs.h
+++ b/himbaechel/archdefs.h
@@ -98,6 +98,7 @@ struct ArchNetInfo
 struct ArchCellInfo : BaseClusterInfo
 {
     int flat_index;
+    int timing_index = -1;
     dict<IdString, std::vector<IdString>> cell_bel_pins;
 };
 
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 07cf09ae23..622486247d 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -62,7 +62,8 @@ NPNR_PACKED_STRUCT(struct BelPinRefPOD {
 NPNR_PACKED_STRUCT(struct TileWireDataPOD {
     int32_t name;
     int32_t wire_type;
-    int32_t flags; // 32 bits of arbitrary data
+    int32_t flags;      // 32 bits of arbitrary data
+    int32_t timing_idx; // used only when the wire is not part of a node, otherwise node idx applies
     RelSlice<int32_t> pips_uphill;
     RelSlice<int32_t> pips_downhill;
     RelSlice<BelPinRefPOD> bel_pins;
@@ -85,7 +86,7 @@ NPNR_PACKED_STRUCT(struct RelTileWireRefPOD {
 
 NPNR_PACKED_STRUCT(struct NodeShapePOD {
     RelSlice<RelTileWireRefPOD> tile_wires;
-    int32_t timing_index;
+    int32_t timing_idx;
 });
 
 NPNR_PACKED_STRUCT(struct TileTypePOD {
@@ -151,12 +152,6 @@ NPNR_PACKED_STRUCT(struct TimingValue {
     int32_t slow_max;
 });
 
-NPNR_PACKED_STRUCT(struct BelPinTimingPOD {
-    TimingValue in_cap;
-    TimingValue drive_res;
-    TimingValue delay;
-});
-
 NPNR_PACKED_STRUCT(struct PipTimingPOD {
     TimingValue int_delay;
     TimingValue in_cap;
@@ -186,19 +181,19 @@ NPNR_PACKED_STRUCT(struct CellPinCombArcPOD {
 
 NPNR_PACKED_STRUCT(struct CellPinTimingPOD {
     int32_t pin;
+    int32_t flags;
     RelSlice<CellPinCombArcPOD> comb_arcs;
     RelSlice<CellPinRegArcPOD> reg_arcs;
+    static constexpr int32_t FLAG_CLK = 1;
 });
 
 NPNR_PACKED_STRUCT(struct CellTimingPOD {
-    int32_t type;
-    int32_t variant;
+    int32_t type_variant;
     RelSlice<CellPinTimingPOD> pins;
 });
 
 NPNR_PACKED_STRUCT(struct SpeedGradePOD {
     int32_t name;
-    RelSlice<BelPinTimingPOD> bel_pin_classes;
     RelSlice<PipTimingPOD> pip_classes;
     RelSlice<NodeTimingPOD> node_classes;
     RelSlice<CellTimingPOD> cell_types;
diff --git a/himbaechel/himbaechel_dbgen/bba.py b/himbaechel/himbaechel_dbgen/bba.py
index de9dca31db..7a2de8265d 100644
--- a/himbaechel/himbaechel_dbgen/bba.py
+++ b/himbaechel/himbaechel_dbgen/bba.py
@@ -17,10 +17,13 @@ def str(self, s, comment=""):
 	def label(self, s):
 		print(f"label {s}", file=self.f)
 	def u8(self, n, comment=""):
+		assert isinstance(n, int), n
 		print(f"u8 {n} {comment}", file=self.f)
 	def u16(self, n, comment=""):
+		assert isinstance(n, int), n
 		print(f"u16 {n} {comment}", file=self.f)
 	def u32(self, n, comment=""):
+		assert isinstance(n, int), n
 		print(f"u32 {n} {comment}", file=self.f)
 	def pop(self):
 		print("pop", file=self.f)
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 9e4c7c25e7..d10118592e 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -25,7 +25,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
     def serialise(self, context: str, bba: BBAWriter):
         pass
 
-@dataclass(eq=True, frozen=True)
+@dataclass(eq=True, order=True, frozen=True)
 class IdString:
     index: int = 0
 
@@ -144,6 +144,7 @@ class TileWireData:
     name: IdString
     wire_type: IdString
     flags: int = 0
+    timing_idx: int = -1
 
     # not serialised, but used to build the global constant networks
     const_val: int = -1
@@ -167,6 +168,7 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
         bba.u32(self.wire_type.index)
         bba.u32(self.flags)
+        bba.u32(self.timing_idx)
         bba.slice(f"{context}_pips_uh", len(self.pips_uphill))
         bba.slice(f"{context}_pips_dh", len(self.pips_downhill))
         bba.slice(f"{context}_bel_pins", len(self.bel_pins))
@@ -191,6 +193,7 @@ def serialise(self, context: str, bba: BBAWriter):
 @dataclass
 class TileType(BBAStruct):
     strs: StringPool
+    tmg: "TimingPool"
     type_name: IdString
     bels: list[BelData] = field(default_factory=list)
     pips: list[PipData] = field(default_factory=list)
@@ -223,11 +226,12 @@ def create_wire(self, name: str, type: str=""):
         self._wire2idx[wire.name] = wire.index
         self.wires.append(wire)
         return wire
-    def create_pip(self, src: str, dst: str):
+    def create_pip(self, src: str, dst: str, timing_class: str=""):
         # Create a pip between two tile wires in the tile type. Both wires should exist already.
         src_idx = self._wire2idx[self.strs.id(src)]
         dst_idx = self._wire2idx[self.strs.id(dst)]
-        pip = PipData(index=len(self.pips), src_wire=src_idx, dst_wire=dst_idx)
+        pip = PipData(index=len(self.pips), src_wire=src_idx, dst_wire=dst_idx,
+            timing_idx=self.tmg.pip_class_idx(timing_class))
         self.wires[src_idx].pips_downhill.append(pip.index)
         self.wires[dst_idx].pips_uphill.append(pip.index)
         self.pips.append(pip)
@@ -294,6 +298,8 @@ def serialise(self, context: str, bba: BBAWriter):
 @dataclass
 class NodeShape(BBAStruct):
     wires: list[TileWireRef] = field(default_factory=list)
+    timing_index: int = -1
+
     def key(self):
         m = hashlib.sha1()
         for wire in self.wires:
@@ -310,7 +316,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
             bba.u16(0) # alignment
     def serialise(self, context: str, bba: BBAWriter):
         bba.slice(f"{context}_wires", len(self.wires))
-        bba.u32(-1) # timing index (not yet used)
+        bba.u32(self.timing_index) # timing index (not yet used)
 
 MODE_TILE_WIRE = 0x7000
 MODE_IS_ROOT = 0x7001
@@ -430,6 +436,247 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
         bba.slice(f"{context}_pads", len(self.pads))
 
+class TimingValue(BBAStruct):
+    def __init__(self, fast_min=0, fast_max=None, slow_min=None, slow_max=None):
+        self.fast_min = fast_min
+        self.fast_max = fast_max or fast_min
+        self.slow_min = slow_min or self.fast_min
+        self.slow_max = slow_max or self.fast_max
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+            bba.u32(self.fast_min)
+            bba.u32(self.fast_max)
+            bba.u32(self.slow_min)
+            bba.u32(self.slow_max)
+
+@dataclass
+class PipTiming(BBAStruct):
+    int_delay: TimingValue = field(default_factory=TimingValue) # internal fixed delay in ps
+    in_cap: TimingValue = field(default_factory=TimingValue) # internal capacitance in notional femtofarads
+    out_res: TimingValue = field(default_factory=TimingValue) # drive/output resistance in notional milliohms
+    flags: int = 0 # is_buffered etc
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        self.int_delay.serialise(context, bba)
+        self.in_cap.serialise(context, bba)
+        self.out_res.serialise(context, bba)
+        bba.u32(self.flags)
+
+@dataclass
+class NodeTiming(BBAStruct):
+    res: TimingValue = field(default_factory=TimingValue) # wire resistance in notional milliohms
+    cap: TimingValue = field(default_factory=TimingValue) # wire capacitance in notional femtofarads
+    delay: TimingValue = field(default_factory=TimingValue) # fixed wire delay in ps
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        self.res.serialise(context, bba)
+        self.cap.serialise(context, bba)
+        self.delay.serialise(context, bba)
+
+@dataclass
+class ClockEdge(Enum):
+    RISING = 0
+    FALLING = 1
+
+@dataclass
+class CellPinRegArc(BBAStruct):
+    clock: int
+    edge: ClockEdge
+    setup: TimingValue = field(default_factory=TimingValue) # setup time in ps
+    hold: TimingValue = field(default_factory=TimingValue) # hold time in ps
+    clk_q: TimingValue = field(default_factory=TimingValue) # clock to output time in ps
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.clock.index)
+        bba.u32(self.edge.value)
+        self.setup.serialise(context, bba)
+        self.hold.serialise(context, bba)
+        self.clk_q.serialise(context, bba)
+
+@dataclass
+class CellPinCombArc(BBAStruct):
+    from_pin: int
+    delay: TimingValue = field(default_factory=TimingValue)
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.from_pin.index)
+        self.delay.serialise(context, bba)
+
+@dataclass
+class CellPinTiming(BBAStruct):
+    pin: int
+    flags: int = 0
+    comb_arcs: list[CellPinCombArc] = field(default_factory=list) # sorted by from_pin ID index
+    reg_arcs: list[CellPinRegArc] = field(default_factory=list) # sorted by clock ID index
+
+    def set_clock(self):
+        self.flags |= 1
+
+    def finalise(self):
+        self.comb_arcs.sort(key=lambda a: a.from_pin)
+        self.reg_arcs.sort(key=lambda a: a.clock)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_comb")
+        for i, a in enumerate(self.comb_arcs):
+            a.serialise(f"{context}_comb{i}", bba)
+        bba.label(f"{context}_reg")
+        for i, a in enumerate(self.reg_arcs):
+            a.serialise(f"{context}_reg{i}", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.pin.index) # pin idstring
+        bba.u32(self.flags)
+        bba.slice(f"{context}_comb", len(self.comb_arcs))
+        bba.slice(f"{context}_reg", len(self.reg_arcs))
+
+class CellTiming(BBAStruct):
+    def __init__(self, strs: StringPool, type_variant: str):
+        self.strs = strs
+        self.type_variant = strs.id(type_variant)
+        self.pin_data = {}
+
+    # combinational timing through a cell (like a LUT delay)
+    def add_comb_arc(self, from_pin: str, to_pin: str, delay: TimingValue):
+        if to_pin not in self.pin_data:
+            self.pin_data[to_pin] = CellPinTiming(pin=self.strs.id(to_pin))
+        self.pin_data[to_pin].comb_arcs.append(CellPinCombArc(from_pin=self.strs.id(from_pin), delay=delay))
+
+    # register input style timing (like a DFF input)
+    def add_setup_hold(self, clock: str, input_pin: str, edge: ClockEdge, setup: TimingValue, hold: TimingValue):
+        if input_pin not in self.pin_data:
+            self.pin_data[input_pin] = CellPinTiming(pin=self.strs.id(input_pin))
+        if clock not in self.pin_data:
+            self.pin_data[clock] = CellPinTiming(pin=self.strs.id(clock))
+        self.pin_data[input_pin].reg_arcs.append(CellPinRegArc(clock=self.strs.id(clock), edge=edge, setup=setup, hold=hold))
+        self.pin_data[clock].set_clock()
+
+    # register output style timing (like a DFF output)
+    def add_clock_out(self, clock: str, output_pin: str, edge: ClockEdge, delay: TimingValue):
+        if output_pin not in self.pin_data:
+            self.pin_data[output_pin] = CellPinTiming(pin=self.strs.id(output_pin))
+        if clock not in self.pin_data:
+            self.pin_data[clock] = CellPinTiming(pin=self.strs.id(clock))
+        self.pin_data[output_pin].reg_arcs.append(CellPinRegArc(clock=self.strs.id(clock), edge=edge, clk_q=delay))
+        self.pin_data[clock].set_clock()
+
+    def finalise(self):
+        self.pins = list(self.pin_data.values())
+        self.pins.sort(key=lambda p: p.pin)
+        for pin in self.pins:
+            pin.finalise()
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        for i, p in enumerate(self.pins):
+            p.serialise_lists(f"{context}_pin{i}", bba)
+        bba.label(f"{context}_pins")
+        for i, p in enumerate(self.pins):
+            p.serialise(f"{context}_pin{i}", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.type_variant.index) # type idstring
+        bba.slice(f"{context}_pins", len(self.pins))
+
+@dataclass
+class SpeedGrade(BBAStruct):
+    name: int
+    pip_classes: list[PipTiming|None] = field(default_factory=list)
+    node_classes: list[NodeTiming|None] = field(default_factory=list)
+    cell_types: list[CellTiming] = field(default_factory=list) # sorted by (cell_type, variant) ID tuple
+
+    def finalise(self):
+        self.cell_types.sort(key=lambda ty: ty.type_variant)
+        for ty in self.cell_types:
+            ty.finalise()
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        for i, t in enumerate(self.cell_types):
+            t.serialise_lists(f"{context}_cellty{i}", bba)
+        bba.label(f"{context}_pip_classes")
+        for i, p in enumerate(self.pip_classes):
+            p.serialise(f"{context}_pipc{i}", bba)
+        bba.label(f"{context}_node_classes")
+        for i, n in enumerate(self.node_classes):
+            n.serialise(f"{context}_nodec{i}", bba)
+        bba.label(f"{context}_cell_types")
+        for i, t in enumerate(self.cell_types):
+            t.serialise(f"{context}_cellty{i}", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index) # speed grade idstring
+        bba.slice(f"{context}_pip_classes", len(self.pip_classes))
+        bba.slice(f"{context}_node_classes", len(self.node_classes))
+        bba.slice(f"{context}_cell_types", len(self.cell_types))
+
+class TimingPool(BBAStruct):
+    def __init__(self, strs: StringPool):
+        self.strs = strs
+        self.speed_grades = []
+        self.speed_grade_idx = {}
+        self.pip_classes = {}
+        self.node_classes = {}
+
+    def set_speed_grades(self, speed_grades: list):
+        assert len(self.speed_grades) == 0
+        self.speed_grades = [SpeedGrade(name=self.strs.id(g)) for g in speed_grades]
+        self.speed_grade_idx = {g: i for i, g in enumerate(speed_grades)}
+
+    def pip_class_idx(self, name: str):
+        if name == "":
+            return -1
+        elif name in self.pip_classes:
+            return self.pip_classes[name]
+        else:
+            idx = len(self.pip_classes)
+            self.pip_classes[name] = idx
+            return idx
+
+    def node_class_idx(self, name: str):
+        if name == "":
+            return -1
+        elif name in self.node_classes:
+            return self.node_classes[name]
+        else:
+            idx = len(self.node_classes)
+            self.node_classes[name] = idx
+            return idx
+
+    def set_pip_class(self, grade: str, name: str, delay: TimingValue,
+            in_cap: Optional[TimingValue]=None, out_res: Optional[TimingValue]=None,
+            is_buffered=True):
+        idx = self.pip_class_idx(name)
+        sg = self.speed_grades[self.speed_grade_idx[grade]]
+        if idx >= len(sg.pip_classes):
+            sg.pip_classes += [None for i in range(1 + idx - len(sg.pip_classes))]
+        assert sg.pip_classes[idx] is None, f"attempting to set pip class {name} in speed grade {grade} twice"
+        sg.pip_classes[idx] = PipTiming(int_delay=delay, in_cap=in_cap, out_res=out_res, flags=(1 if is_buffered else 0))
+
+    def set_bel_pin_class(self, grade: str, name: str, delay: TimingValue,
+            in_cap: Optional[TimingValue]=None, out_res: Optional[TimingValue]=None):
+        # bel pin classes are shared with pip classes, but this alias adds a bit of extra clarity
+        set_pip_class(self, grade, name, delay, in_cap, out_res, is_buffered=True)
+
+    def set_node_class(self, grade: str, name: str,  delay: TimingValue,
+            res: Optional[TimingValue]=None, cap: Optional[TimingValue]=None):
+        idx = self.node_class_idx(name)
+        sg = self.speed_grades[self.speed_grade_idx[grade]]
+        if idx >= len(sg.node_classes):
+            sg.node_classes += [None for i in range(1 + idx - len(sg.node_classes))]
+        assert sg.node_classes[idx] is None, f"attempting to set node class {name} in speed grade {grade} twice"
+        sg.node_classes[idx] = NodeTiming(delay=delay, res=res, cap=cap)
+
+    def add_cell_variant(self, speed_grade: str, name: str):
+        cell = CellTiming(self.strs, name)
+        self.speed_grades[self.speed_grade_idx[speed_grade]].cell_types.append(cell)
+        return cell
+
+    def finalise(self):
+        for sg in self.speed_grades:
+            sg.finalise()
+
 class Chip:
     def __init__(self, uarch: str, name: str, width: int, height: int):
         self.strs = StringPool()
@@ -446,8 +693,9 @@ def __init__(self, uarch: str, name: str, width: int, height: int):
         self.tile_shapes_idx = dict()
         self.packages = []
         self.extra_data = None
+        self.timing = TimingPool(self.strs)
     def create_tile_type(self, name: str):
-        tt = TileType(self.strs, self.strs.id(name))
+        tt = TileType(self.strs, self.timing, self.strs.id(name))
         self.tile_type_idx[name] = len(self.tile_types)
         self.tile_types.append(tt)
         return tt
@@ -456,6 +704,9 @@ def set_tile_type(self, x: int, y: int, type: str):
     def tile_type_at(self, x: int, y: int):
         assert self.tiles[y][x].type_idx is not None, f"tile type at ({x}, {y}) must be set"
         return self.tile_types[self.tiles[y][x].type_idx]
+    def set_speed_grades(self, speed_grades: list):
+        self.timing.set_speed_grades(speed_grades)
+        return self.timing
     def add_node(self, wires: list[NodeWire]):
         # add a node - joining between multiple tile wires into a single connection (from nextpnr's point of view)
         # all the tile wires must exist, and the tile types must be set, first
@@ -529,7 +780,8 @@ def serialise(self, bba: BBAWriter):
         for y, row in enumerate(self.tiles):
             for x, tinst in enumerate(row):
                 tinst.serialise_lists(f"tinst_{x}_{y}", bba)
-
+        for i, sg in enumerate(self.timing.speed_grades):
+            sg.serialise_lists(f"sg{i}", bba)
         self.strs.serialise_lists(f"constids", bba)
         if self.extra_data is not None:
             self.extra_data.serialise_lists("extra_data", bba)
@@ -552,7 +804,9 @@ def serialise(self, bba: BBAWriter):
         for y, row in enumerate(self.tiles):
             for x, tinst in enumerate(row):
                 tinst.serialise(f"tinst_{x}_{y}", bba)
-
+        bba.label(f"speed_grades")
+        for i, sg in enumerate(self.timing.speed_grades):
+            sg.serialise(f"sg{i}", bba)
         bba.label(f"constids")
         self.strs.serialise(f"constids", bba)
 
@@ -573,8 +827,7 @@ def serialise(self, bba: BBAWriter):
         # packages
         bba.slice("packages", len(self.packages))
         # speed grades: not yet used
-        bba.u32(0)
-        bba.u32(0)
+        bba.slice("speed_grades", len(self.timing.speed_grades))
         # db-defined constids
         bba.ref("constids")
         # extra data
@@ -584,6 +837,7 @@ def serialise(self, bba: BBAWriter):
             bba.u32(0)
 
     def write_bba(self, filename):
+        self.timing.finalise()
         with open(filename, "w") as f:
             bba = BBAWriter(f)
             bba.pre('#include \"nextpnr.h\"')
diff --git a/himbaechel/main.cc b/himbaechel/main.cc
index 64c2c0f3f8..d66b3d9c8d 100644
--- a/himbaechel/main.cc
+++ b/himbaechel/main.cc
@@ -49,6 +49,7 @@ po::options_description HimbaechelCommandHandler::getArchOptions()
     po::options_description specific("Architecture specific options");
     specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
     specific.add_options()("chipdb", po::value<std::string>(), "path to chip database file");
+    specific.add_options()("speed", po::value<std::string>(), "device speed grade");
     specific.add_options()("vopt,o", po::value<std::vector<std::string>>(), "options to pass to the himbächel uarch");
 
     return specific;
@@ -70,6 +71,8 @@ std::unique_ptr<Context> HimbaechelCommandHandler::createContext(dict<std::strin
         log_error("chip database path must be specified.\n");
     chipArgs.uarch = vm["uarch"].as<std::string>();
     chipArgs.chipdb = vm["chipdb"].as<std::string>();
+    if (vm.count("speed"))
+        chipArgs.speed = vm["speed"].as<std::string>();
     if (vm.count("vopt")) {
         std::vector<std::string> options = vm["vopt"].as<std::vector<std::string>>();
         for (const auto &opt : options) {
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
index 026c2551aa..81d5c7dc35 100644
--- a/himbaechel/uarch/example/example_arch_gen.py
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -40,15 +40,15 @@ def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
     # input pips
     for i, w in enumerate(inputs):
         for j in range((i % Si), Wl, Si):
-            tt.create_pip(f"SWITCH{j}", w)
+            tt.create_pip(f"SWITCH{j}", w, timing_class="SWINPUT")
     # output pips
     for i, w in enumerate(outputs):
         for j in range((i % Sq), Wl, Sq):
-            tt.create_pip(w, f"SWITCH{j}")
+            tt.create_pip(w, f"SWITCH{j}", timing_class="SWINPUT")
     # neighbour local pips
     for i in range(Wl):
         for j, (d, dx, dy) in enumerate(dirs):
-            tt.create_pip(f"{d}{(i + j) % Wl}", f"SWITCH{i}")
+            tt.create_pip(f"{d}{(i + j) % Wl}", f"SWITCH{i}", timing_class="SWNEIGH")
     # clock "ladder"
     if not tt.has_wire("CLK"):
         tt.create_wire(f"CLK", "TILE_CLK")
@@ -185,7 +185,37 @@ def create_nodes(ch):
                     clk_node.append(NodeWire(x, y+1, "CLK_PREV"))
                 ch.add_node(clk_node)
 
+def set_timings(ch):
+    speed = "DEFAULT"
+    tmg = ch.set_speed_grades([speed])
+    # --- Routing Delays ---
+    # Notes: A simpler timing model could just use intrinsic delay and ignore R and Cs.
+    # R and C values don't have to be physically realistic, just in agreement with themselves to provide
+    # a meaningful scaling of delay with fanout. Units are subject to change.
+    tmg.set_pip_class(grade=speed, name="SWINPUT",
+        delay=TimingValue(80), # 80ps intrinstic delay
+        in_cap=TimingValue(5000), # 5pF
+        out_res=TimingValue(1000), # 1ohm
+    )
+    tmg.set_pip_class(grade=speed, name="SWOUTPUT",
+        delay=TimingValue(100), # 100ps intrinstic delay
+        in_cap=TimingValue(5000), # 5pF
+        out_res=TimingValue(800), # 0.8ohm
+    )
+    tmg.set_pip_class(grade=speed, name="SWNEIGH",
+        delay=TimingValue(120), # 120ps intrinstic delay
+        in_cap=TimingValue(7000), # 7pF
+        out_res=TimingValue(1200), # 1.2ohm
+    )
+    # TODO: also support node/wire delays and add an example of them
 
+    # --- Cell delays ---
+    lut = ch.timing.add_cell_variant(speed, "LUT4")
+    for j in range(K):
+        lut.add_comb_arc(f"I[{j}]", "F", TimingValue(150 + j * 15))
+    dff = ch.timing.add_cell_variant(speed, "DFF")
+    dff.add_setup_hold("CLK", "D", ClockEdge.RISING, TimingValue(150), TimingValue(25))
+    dff.add_clock_out("CLK", "Q", ClockEdge.RISING, TimingValue(200))
 
 def main():
     ch = Chip("example", "EX1", X, Y)
@@ -211,6 +241,8 @@ def main():
                 ch.set_tile_type(x, y, "LOGIC")
     # Create nodes between tiles
     create_nodes(ch)
+    set_timings(ch)
     ch.write_bba(sys.argv[1])
+
 if __name__ == '__main__':
     main()

From 3cac90a30a82a30c1e23ac0e69487fe844daaa1b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 12 Sep 2023 09:24:20 +0200
Subject: [PATCH 473/712] himbaechel: Fix for Python 3.9

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/himbaechel_dbgen/chip.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index d10118592e..ebc6236927 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -584,8 +584,8 @@ def serialise(self, context: str, bba: BBAWriter):
 @dataclass
 class SpeedGrade(BBAStruct):
     name: int
-    pip_classes: list[PipTiming|None] = field(default_factory=list)
-    node_classes: list[NodeTiming|None] = field(default_factory=list)
+    pip_classes: list[Optional[PipTiming]] = field(default_factory=list)
+    node_classes: list[Optional[NodeTiming]] = field(default_factory=list)
     cell_types: list[CellTiming] = field(default_factory=list) # sorted by (cell_type, variant) ID tuple
 
     def finalise(self):

From 565927dfcc1be506aec4757c42e7c192a90f9246 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 12 Sep 2023 17:29:26 +0200
Subject: [PATCH 474/712] himbaechel: Add discovery of uarch and chipdb

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/ci/build_himbaechel.sh        |   5 +-
 common/kernel/command.cc              | 186 ++++++++++++++++++++++++++
 common/kernel/command.h               |   6 +
 himbaechel/arch.cc                    |  87 ++++++------
 himbaechel/arch.h                     |   6 +-
 himbaechel/arch_pybindings.cc         |   2 +-
 himbaechel/himbaechel_api.cc          |  12 +-
 himbaechel/himbaechel_api.h           |  11 +-
 himbaechel/main.cc                    |  32 +++--
 himbaechel/uarch/example/example.cc   |  11 +-
 himbaechel/uarch/gowin/CMakeLists.txt |   8 +-
 himbaechel/uarch/gowin/gowin.cc       |  60 ++++++---
 12 files changed, 332 insertions(+), 94 deletions(-)

diff --git a/.github/ci/build_himbaechel.sh b/.github/ci/build_himbaechel.sh
index e8adaf8d79..73db3b5700 100644
--- a/.github/ci/build_himbaechel.sh
+++ b/.github/ci/build_himbaechel.sh
@@ -12,7 +12,8 @@ function build_nextpnr {
     # We'd ideally use pypy3 for speed (as works locally), but the version
     # our CI Ubuntu provides doesn't like some of the typing stuff
     python3 ../himbaechel/uarch/example/example_arch_gen.py ./example.bba
-    ./bba/bbasm --l ./example.bba ./example.bin
+    mkdir -p share/himbaechel/example
+    ./bba/bbasm --l ./example.bba share/himbaechel/example/example.bin
     popd
 }
 
@@ -22,6 +23,6 @@ function run_tests {
 
 function run_archcheck {
     pushd build
-    ./nextpnr-himbaechel --uarch example --chipdb ./example.bin --test
+    ./nextpnr-himbaechel --device EXAMPLE --test
     popd
 }
diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index aa0704505e..ceb058c85d 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -45,8 +45,188 @@
 #include "util.h"
 #include "version.h"
 
+#if defined(_WIN32)
+#include <io.h>
+#include <windows.h>
+#elif defined(__APPLE__)
+#include <dirent.h>
+#include <mach-o/dyld.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#else
+#include <dirent.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+#endif
+
+#ifdef __FreeBSD__
+#include <sys/sysctl.h>
+#endif
+
 NEXTPNR_NAMESPACE_BEGIN
 
+static std::string npnr_share_dirname;
+
+#ifdef _WIN32
+bool check_file_exists(std::string filename, bool) { return _access(filename.c_str(), 0) == 0; }
+#else
+bool check_file_exists(std::string filename, bool is_exec)
+{
+    return access(filename.c_str(), is_exec ? X_OK : F_OK) == 0;
+}
+#endif
+
+#if defined(__linux__) || defined(__CYGWIN__)
+std::string proc_self_dirname()
+{
+    char path[PATH_MAX];
+    ssize_t buflen = readlink("/proc/self/exe", path, sizeof(path));
+    if (buflen < 0) {
+        log_error("readlink(\"/proc/self/exe\") failed: %s\n", strerror(errno));
+    }
+    while (buflen > 0 && path[buflen - 1] != '/')
+        buflen--;
+    return std::string(path, buflen);
+}
+#elif defined(__FreeBSD__)
+std::string proc_self_dirname()
+{
+    int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1};
+    size_t buflen;
+    char *buffer;
+    std::string path;
+    if (sysctl(mib, 4, NULL, &buflen, NULL, 0) != 0)
+        log_error("sysctl failed: %s\n", strerror(errno));
+    buffer = (char *)malloc(buflen);
+    if (buffer == NULL)
+        log_error("malloc failed: %s\n", strerror(errno));
+    if (sysctl(mib, 4, buffer, &buflen, NULL, 0) != 0)
+        log_error("sysctl failed: %s\n", strerror(errno));
+    while (buflen > 0 && buffer[buflen - 1] != '/')
+        buflen--;
+    path.assign(buffer, buflen);
+    free(buffer);
+    return path;
+}
+#elif defined(__APPLE__)
+std::string proc_self_dirname()
+{
+    char *path = NULL;
+    uint32_t buflen = 0;
+    while (_NSGetExecutablePath(path, &buflen) != 0)
+        path = (char *)realloc((void *)path, buflen);
+    while (buflen > 0 && path[buflen - 1] != '/')
+        buflen--;
+    std::string str(path, buflen);
+    free(path);
+    return str;
+}
+#elif defined(_WIN32)
+std::string proc_self_dirname()
+{
+    int i = 0;
+#ifdef __MINGW32__
+    char longpath[MAX_PATH + 1];
+    char shortpath[MAX_PATH + 1];
+#else
+    WCHAR longpath[MAX_PATH + 1];
+    TCHAR shortpath[MAX_PATH + 1];
+#endif
+    if (!GetModuleFileName(0, longpath, MAX_PATH + 1))
+        log_error("GetModuleFileName() failed.\n");
+    if (!GetShortPathName(longpath, shortpath, MAX_PATH + 1))
+        log_error("GetShortPathName() failed.\n");
+    while (shortpath[i] != 0)
+        i++;
+    while (i > 0 && shortpath[i - 1] != '/' && shortpath[i - 1] != '\\')
+        shortpath[--i] = 0;
+    std::string path;
+    for (i = 0; shortpath[i]; i++)
+        path += char(shortpath[i]);
+    return path;
+}
+#elif defined(EMSCRIPTEN) || defined(__wasm)
+std::string proc_self_dirname() { return "/"; }
+#elif defined(__OpenBSD__)
+char npnr_path[PATH_MAX];
+char *npnr_argv0;
+
+std::string proc_self_dirname(void)
+{
+    char buf[PATH_MAX + 1] = "", *path, *p;
+    // if case argv[0] contains a valid path, return it
+    if (strlen(npnr_path) > 0) {
+        p = strrchr(npnr_path, '/');
+        snprintf(buf, sizeof buf, "%*s/", (int)(npnr_path - p), npnr_path);
+        return buf;
+    }
+    // if argv[0] does not, reconstruct the path out of $PATH
+    path = strdup(getenv("PATH"));
+    if (!path)
+        log_error("getenv(\"PATH\") failed: %s\n", strerror(errno));
+    for (p = strtok(path, ":"); p; p = strtok(NULL, ":")) {
+        snprintf(buf, sizeof buf, "%s/%s", p, npnr_argv0);
+        if (access(buf, X_OK) == 0) {
+            *(strrchr(buf, '/') + 1) = '\0';
+            free(path);
+            return buf;
+        }
+    }
+    free(path);
+    log_error("Can't determine nextpnr executable path\n.");
+    return NULL;
+}
+#else
+#error "Don't know how to determine process executable base path!"
+#endif
+
+#if defined(EMSCRIPTEN) || defined(__wasm)
+void init_share_dirname() { npnr_share_dirname = "/share/"; }
+#else
+void init_share_dirname()
+{
+    std::string proc_self_path = proc_self_dirname();
+#if defined(_WIN32) && !defined(nextpnr_WIN32_UNIX_DIR)
+    std::string proc_share_path = proc_self_path + "share\\";
+    if (check_file_exists(proc_share_path, true)) {
+        npnr_share_dirname = proc_share_path;
+        return;
+    }
+    proc_share_path = proc_self_path + "..\\share\\";
+    if (check_file_exists(proc_share_path, true)) {
+        npnr_share_dirname = proc_share_path;
+        return;
+    }
+#else
+    std::string proc_share_path = proc_self_path + "share/";
+    if (check_file_exists(proc_share_path, true)) {
+        npnr_share_dirname = proc_share_path;
+        return;
+    }
+    proc_share_path = proc_self_path + "../share/" + "nextpnr/";
+    if (check_file_exists(proc_share_path, true)) {
+        npnr_share_dirname = proc_share_path;
+        return;
+    }
+#ifdef nextpnr_DATDIR
+    proc_share_path = nextpnr_DATDIR "/";
+    if (check_file_exists(proc_share_path, true)) {
+        npnr_share_dirname = proc_share_path;
+        return;
+    }
+#endif
+#endif
+}
+#endif
+
+std::string proc_share_dirname()
+{
+    if (npnr_share_dirname.empty())
+        log_error("init_share_dirname: unable to determine share/ directory!\n");
+    return npnr_share_dirname;
+}
+
 struct no_separator : std::numpunct<char>
 {
   protected:
@@ -62,6 +242,12 @@ CommandHandler::CommandHandler(int argc, char **argv) : argc(argc), argv(argv)
         // the locale is broken in this system, so leave it as it is
     }
     log_streams.clear();
+
+#if defined(__OpenBSD__)
+    // save the executable origin for proc_self_dirname()
+    npnr_argv0 = argv[0];
+    realpath(npnr_argv0, npnr_path);
+#endif
 }
 
 bool CommandHandler::parseOptions()
diff --git a/common/kernel/command.h b/common/kernel/command.h
index 6cce8c615f..8e0e886d73 100644
--- a/common/kernel/command.h
+++ b/common/kernel/command.h
@@ -69,6 +69,12 @@ class CommandHandler
     std::ofstream logfile;
 };
 
+// Relative directory functions from Yosys
+bool check_file_exists(std::string filename, bool is_exec);
+void init_share_dirname();
+std::string proc_self_dirname();
+std::string proc_share_dirname();
+
 NEXTPNR_NAMESPACE_END
 
 #endif // COMMAND_H
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index df576333d0..644dc21ea1 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -23,6 +23,7 @@
 #include "log.h"
 #include "nextpnr.h"
 
+#include "command.h"
 #include "placer1.h"
 #include "placer_heap.h"
 #include "router1.h"
@@ -33,66 +34,72 @@ NEXTPNR_NAMESPACE_BEGIN
 
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
-Arch::Arch(ArchArgs args)
+Arch::Arch(ArchArgs args) : args(args)
 {
+    HimbaechelArch *arch = HimbaechelArch::find_match(args.device);
+    if (!arch) {
+        std::string available = HimbaechelArch::list();
+        log_error("unable to load uarch for device '%s', included uarches: %s\n", args.device.c_str(),
+                  available.c_str());
+    }
+    log_info("Using uarch '%s' for device '%s'\n", arch->name.c_str(), args.device.c_str());
+    this->args.uarch = arch->name;
+    uarch = arch->create(args.device, args.options);
+    // Load uarch
+    uarch->init_database(this);
+    if (!chip_info)
+        log_error("uarch didn't load any chipdb, probably a load_chipdb call was missing\n");
+
+    init_tiles();
+}
+
+void Arch::load_chipdb(const std::string &path)
+{
+    std::string db_path;
+    if (!args.chipdb_override.empty()) {
+        db_path = args.chipdb_override;
+    } else {
+        db_path = proc_share_dirname();
+        db_path += "/himbaechel/";
+        db_path += path;
+    }
     try {
-        blob_file.open(args.chipdb);
-        if (args.chipdb.empty() || !blob_file.is_open())
-            log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
+        blob_file.open(db_path);
+        if (db_path.empty() || !blob_file.is_open())
+            log_error("Unable to read chipdb %s\n", db_path.c_str());
         const char *blob = reinterpret_cast<const char *>(blob_file.data());
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(blob));
     } catch (...) {
-        log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
+        log_error("Unable to read chipdb %s\n", db_path.c_str());
     }
     // Check consistency of blob
     if (chip_info->magic != 0x00ca7ca7)
-        log_error("chipdb %s does not look like a valid himbächel database!\n", args.chipdb.c_str());
+        log_error("chipdb %s does not look like a valid himbächel database!\n", db_path.c_str());
     std::string blob_uarch(chip_info->uarch.get());
     if (blob_uarch != args.uarch)
         log_error("database device uarch '%s' does not match selected device uarch '%s'.\n", blob_uarch.c_str(),
                   args.uarch.c_str());
-    // Load uarch
-    uarch = HimbaechelArch::create(args.uarch, args.options);
-    if (!uarch) {
-        std::string available = HimbaechelArch::list();
-        log_error("unable to load device uarch '%s', available options: %s\n", args.uarch.c_str(), available.c_str());
-    }
-    uarch->init_constids(this);
     // Setup constids from database
     for (int i = 0; i < chip_info->extra_constids->bba_ids.ssize(); i++) {
         IdString::initialize_add(this, chip_info->extra_constids->bba_ids[i].get(),
                                  i + chip_info->extra_constids->known_id_count);
     }
+}
+
+void Arch::set_speed_grade(const std::string &speed)
+{
+    if (speed.empty())
+        return;
     // Select speed grade
-    if (args.speed.empty()) {
-        if (chip_info->speed_grades.ssize() == 0) {
-            // no timing information and no speed grade specified
-            speed_grade = nullptr;
-        } else if (chip_info->speed_grades.ssize() == 1) {
-            // speed grade not specified but only one available; use it
-            speed_grade = &(chip_info->speed_grades[0]);
-        } else {
-            std::string available_speeds = "";
-            for (const auto &speed_data : chip_info->speed_grades) {
-                if (!available_speeds.empty())
-                    available_speeds += ", ";
-                available_speeds += IdString(speed_data.name).c_str(this);
-            }
-            log_error("Speed grade must be specified using --speed (available options: %s).\n",
-                      available_speeds.c_str());
-        }
-    } else {
-        for (const auto &speed_data : chip_info->speed_grades) {
-            if (IdString(speed_data.name) == id(args.speed)) {
-                speed_grade = &speed_data;
-                break;
-            }
-        }
-        if (!speed_grade) {
-            log_error("Speed grade '%s' not found in database.\n", args.speed.c_str());
+    for (const auto &speed_data : chip_info->speed_grades) {
+        if (IdString(speed_data.name) == id(speed)) {
+            speed_grade = &speed_data;
+            break;
         }
     }
-    init_tiles();
+    if (!speed_grade) {
+        log_error("Speed grade '%s' not found in database.\n", speed.c_str());
+    }
 }
 
 void Arch::init_tiles()
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index d2e2e78d5c..3507eb1b85 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -386,9 +386,8 @@ struct BelPinRange
 struct ArchArgs
 {
     std::string uarch;
-    std::string chipdb;
+    std::string chipdb_override;
     std::string device;
-    std::string speed;
     dict<std::string, std::string> options;
 };
 
@@ -421,6 +420,9 @@ struct Arch : BaseArch<ArchRanges>
     Arch(ArchArgs args);
     ~Arch(){};
 
+    void load_chipdb(const std::string &path);
+    void set_speed_grade(const std::string &speed);
+
     void late_init();
 
     // Database references
diff --git a/himbaechel/arch_pybindings.cc b/himbaechel/arch_pybindings.cc
index 246adcd9dc..3825670b0d 100644
--- a/himbaechel/arch_pybindings.cc
+++ b/himbaechel/arch_pybindings.cc
@@ -28,7 +28,7 @@ NEXTPNR_NAMESPACE_BEGIN
 void arch_wrap_python(py::module &m)
 {
     using namespace PythonConversion;
-    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb);
+    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("device", &ArchArgs::device);
 
     py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
 
diff --git a/himbaechel/himbaechel_api.cc b/himbaechel/himbaechel_api.cc
index e8d403e3a3..2a04a99a45 100644
--- a/himbaechel/himbaechel_api.cc
+++ b/himbaechel/himbaechel_api.cc
@@ -25,8 +25,6 @@ NEXTPNR_NAMESPACE_BEGIN
 
 void HimbaechelAPI::init(Context *ctx) { this->ctx = ctx; }
 
-void HimbaechelAPI::init_constids(Arch *arch) {}
-
 std::vector<IdString> HimbaechelAPI::getCellTypes() const
 {
     std::vector<IdString> result;
@@ -89,17 +87,17 @@ std::string HimbaechelArch::list()
     }
     return result;
 }
-std::unique_ptr<HimbaechelAPI> HimbaechelArch::create(const std::string &name,
-                                                      const dict<std::string, std::string> &args)
+
+HimbaechelArch *HimbaechelArch::find_match(const std::string &device)
 {
     HimbaechelArch *cursor = HimbaechelArch::list_head;
     while (cursor) {
-        if (cursor->name != name) {
+        if (!cursor->match_device(device)) {
             cursor = cursor->list_next;
             continue;
         }
-        return cursor->create(args);
+        return cursor;
     }
-    return {};
+    return nullptr;
 }
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index be62be2af8..eaf1a5ed84 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -58,8 +58,9 @@ struct PlacerHeapCfg;
 struct HimbaechelAPI
 {
     virtual void init(Context *ctx);
-    // If constids are being used, this is used to set them up early before loading the db blob
-    virtual void init_constids(Arch *arch);
+    // If constids are being used, this is used to set them up early
+    // then it is responsible for loading the db blob with arch->load_chipdb()
+    virtual void init_database(Arch *arch) = 0;
     Context *ctx;
     bool with_gui = false;
 
@@ -116,10 +117,12 @@ struct HimbaechelArch
     std::string name;
     HimbaechelArch(const std::string &name);
     ~HimbaechelArch(){};
-    virtual std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args) = 0;
+    virtual bool match_device(const std::string &device) = 0;
+    virtual std::unique_ptr<HimbaechelAPI> create(const std::string &device,
+                                                  const dict<std::string, std::string> &args) = 0;
 
     static std::string list();
-    static std::unique_ptr<HimbaechelAPI> create(const std::string &name, const dict<std::string, std::string> &args);
+    static HimbaechelArch *find_match(const std::string &device);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/main.cc b/himbaechel/main.cc
index d66b3d9c8d..26686f8370 100644
--- a/himbaechel/main.cc
+++ b/himbaechel/main.cc
@@ -40,16 +40,19 @@ class HimbaechelCommandHandler : public CommandHandler
     po::options_description getArchOptions() override;
 };
 
-HimbaechelCommandHandler::HimbaechelCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
+HimbaechelCommandHandler::HimbaechelCommandHandler(int argc, char **argv) : CommandHandler(argc, argv)
+{
+    init_share_dirname();
+}
 
 po::options_description HimbaechelCommandHandler::getArchOptions()
 {
     std::string all_uarches = HimbaechelArch::list();
     std::string uarch_help = stringf("himbächel micro-arch to use (available: %s)", all_uarches.c_str());
     po::options_description specific("Architecture specific options");
-    specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
-    specific.add_options()("chipdb", po::value<std::string>(), "path to chip database file");
-    specific.add_options()("speed", po::value<std::string>(), "device speed grade");
+    specific.add_options()("device", po::value<std::string>(), "name of device to use");
+    specific.add_options()("chipdb", po::value<std::string>(), "override path to chip database file");
+    specific.add_options()("list-uarch", "list included uarches");
     specific.add_options()("vopt,o", po::value<std::vector<std::string>>(), "options to pass to the himbächel uarch");
 
     return specific;
@@ -65,14 +68,19 @@ std::unique_ptr<Context> HimbaechelCommandHandler::createContext(dict<std::strin
         if (arch_name != "himbaechel")
             log_error("Unsupported architecture '%s'.\n", arch_name.c_str());
     }
-    if (!vm.count("uarch"))
-        log_error("uarch must be specified\n");
-    if (!vm.count("chipdb"))
-        log_error("chip database path must be specified.\n");
-    chipArgs.uarch = vm["uarch"].as<std::string>();
-    chipArgs.chipdb = vm["chipdb"].as<std::string>();
-    if (vm.count("speed"))
-        chipArgs.speed = vm["speed"].as<std::string>();
+    if (vm.count("list-uarch")) {
+        std::string uarches = HimbaechelArch::list();
+        log_info("Supported uarches: %s\n", uarches.c_str());
+        exit(0);
+    }
+    if (!vm.count("device"))
+        log_error("device must be specified\n");
+    chipArgs.device = vm["device"].as<std::string>();
+
+    if (vm.count("chipdb")) {
+        chipArgs.chipdb_override = vm["chipdb"].as<std::string>();
+    }
+
     if (vm.count("vopt")) {
         std::vector<std::string> options = vm["vopt"].as<std::vector<std::string>>();
         for (const auto &opt : options) {
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index 5f5d1087dc..c02280cdee 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -37,7 +37,13 @@ struct ExampleImpl : HimbaechelAPI
     static constexpr int K = 4;
 
     ~ExampleImpl(){};
-    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init_database(Arch *arch) override
+    {
+        init_uarch_constids(arch);
+        arch->load_chipdb("example/example.bin");
+        arch->set_speed_grade("DEFAULT");
+    }
+
     void init(Context *ctx) override
     {
         h.init(ctx);
@@ -134,7 +140,8 @@ struct ExampleImpl : HimbaechelAPI
 struct ExampleArch : HimbaechelArch
 {
     ExampleArch() : HimbaechelArch("example"){};
-    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+    bool match_device(const std::string &device) override { return device == "EXAMPLE"; }
+    std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
     {
         return std::make_unique<ExampleImpl>();
     }
diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index dc1250ce9e..d2b64e6e05 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -25,14 +25,14 @@ else()
 endif()
 
 set(chipdb_binaries)
-file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb)
+file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/gowin)
 foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
     if(NOT device IN_LIST ALL_HIMBAECHEL_GOWIN_DEVICES)
 		message(FATAL_ERROR "Device ${device} is not a supported Gowin device")
     endif()
 
-	set(device_bba chipdb/chipdb-${device}.bba)
-	set(device_bin chipdb/chipdb-${device}.bin)
+	set(device_bba ${CMAKE_BINARY_DIR}/share/himbaechel/gowin/chipdb-${device}.bba)
+	set(device_bin ${CMAKE_BINARY_DIR}/share/himbaechel/gowin/chipdb-${device}.bin)
 	add_custom_command(
 		OUTPUT ${device_bin}
 		COMMAND ${apycula_Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gowin_arch_gen.py -d ${device} -o ${device_bba}
@@ -48,5 +48,5 @@ foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
 endforeach()
 
 add_custom_target(chipdb-himbaechel-gowin ALL DEPENDS ${chipdb_binaries})
-install(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/chipdb/ DESTINATION share/nextpnr/himbaechel/gowin
+install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/gowin DESTINATION share/nextpnr/himbaechel/gowin
 	    PATTERN "*.bba" EXCLUDE)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index bf898564cc..f67e9b4e43 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -22,7 +22,7 @@ struct GowinImpl : HimbaechelAPI
 {
 
     ~GowinImpl(){};
-    void init_constids(Arch *arch) override { init_uarch_constids(arch); }
+    void init_database(Arch *arch) override;
     void init(Context *ctx) override;
 
     void pack() override;
@@ -64,12 +64,49 @@ struct GowinImpl : HimbaechelAPI
 struct GowinArch : HimbaechelArch
 {
     GowinArch() : HimbaechelArch("gowin"){};
-    std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
+
+    bool match_device(const std::string &device) override { return device.size() > 2 && device.substr(0, 2) == "GW"; }
+
+    std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
     {
         return std::make_unique<GowinImpl>();
     }
 } gowinrArch;
 
+void GowinImpl::init_database(Arch *arch)
+{
+    init_uarch_constids(arch);
+    const ArchArgs &args = arch->args;
+    std::string family;
+    if (args.options.count("family")) {
+        family = args.options.at("family");
+    } else {
+        bool GW2 = args.device == "GW2A-LV18PG256C8/I7";
+        if (GW2) {
+            family = "GW2A-18";
+        } else {
+            std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
+            std::smatch match;
+            if (!std::regex_match(args.device, match, devicere)) {
+                log_error("Invalid device %s\n", args.device.c_str());
+            }
+            family = stringf("GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
+        }
+    }
+
+    arch->load_chipdb(stringf("gowin/chipdb-%s.bin", family.c_str()));
+
+    // These fields go in the header of the output JSON file and can help
+    // gowin_pack support different architectures
+    arch->settings[arch->id("packer.arch")] = std::string("himbaechel/gowin");
+    arch->settings[arch->id("packer.chipdb")] = family;
+
+    chip = arch->id(family);
+    std::string pn = args.device;
+    partno = arch->id(pn);
+    arch->settings[arch->id("packer.partno")] = pn;
+}
+
 void GowinImpl::init(Context *ctx)
 {
     h.init(ctx);
@@ -78,24 +115,6 @@ void GowinImpl::init(Context *ctx)
     gwu.init(ctx);
 
     const ArchArgs &args = ctx->getArchArgs();
-    // These fields go in the header of the output JSON file and can help
-    // gowin_pack support different architectures
-    ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
-    ctx->settings[ctx->id("packer.chipdb")] = args.chipdb;
-
-    if (!args.options.count("partno")) {
-        log_error("Partnumber (like --vopt partno=GW1NR-LV9QN88PC6/I5) must be specified.\n");
-    }
-    // GW1N-9C.xxx -> GW1N-9C
-    std::string chipdb = args.chipdb;
-    auto dot_pos = chipdb.find(".");
-    if (dot_pos != std::string::npos) {
-        chipdb.resize(dot_pos);
-    }
-    chip = ctx->id(chipdb);
-    std::string pn = args.options.at("partno");
-    partno = ctx->id(pn);
-    ctx->settings[ctx->id("packer.partno")] = pn;
 
     // package and speed class
     std::regex speedre = std::regex("(.*)(C[0-9]/I[0-9])$");
@@ -103,6 +122,7 @@ void GowinImpl::init(Context *ctx)
 
     IdString spd;
     IdString package_idx;
+    std::string pn = args.device;
     if (std::regex_match(pn, match, speedre)) {
         package_idx = ctx->id(match[1]);
         spd = ctx->id(match[2]);

From 165e89f49af97550f5bdd5237e99320b865e2b31 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 16 Sep 2023 11:43:13 +1000
Subject: [PATCH 475/712] gowin: Himbaechel. Support DragonFlyBSD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We add support right here so that later I don’t have to make patches to the ports.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/kernel/command.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index ceb058c85d..cbd68e1673 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -148,7 +148,7 @@ std::string proc_self_dirname()
 }
 #elif defined(EMSCRIPTEN) || defined(__wasm)
 std::string proc_self_dirname() { return "/"; }
-#elif defined(__OpenBSD__)
+#elif defined(__OpenBSD__) || defined(__DragonFly__)
 char npnr_path[PATH_MAX];
 char *npnr_argv0;
 

From 8a54e5ec1ca1f89a232597bcc7600825322ab489 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 16 Sep 2023 13:01:53 +1000
Subject: [PATCH 476/712] gowin: Himbaechel. Support DragonFlyBSD

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/kernel/command.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index cbd68e1673..c7733674c3 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -243,7 +243,7 @@ CommandHandler::CommandHandler(int argc, char **argv) : argc(argc), argv(argv)
     }
     log_streams.clear();
 
-#if defined(__OpenBSD__)
+#if defined(__OpenBSD__) || defined(__DragonFly__)
     // save the executable origin for proc_self_dirname()
     npnr_argv0 = argv[0];
     realpath(npnr_argv0, npnr_path);

From f5996ff4a1f387c078ecf499ac4279b2300f878c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 16 Sep 2023 15:01:24 +1000
Subject: [PATCH 477/712] gowin: Himbaechel. Support DragonFlyBSD

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 common/kernel/command.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index c7733674c3..ac154cc6eb 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -156,8 +156,7 @@ std::string proc_self_dirname(void)
 {
     char buf[PATH_MAX + 1] = "", *path, *p;
     // if case argv[0] contains a valid path, return it
-    if (strlen(npnr_path) > 0) {
-        p = strrchr(npnr_path, '/');
+    if (strlen(npnr_path) > 0 && (p = strrchr(npnr_path, '/')) != NULL) {
         snprintf(buf, sizeof buf, "%*s/", (int)(npnr_path - p), npnr_path);
         return buf;
     }

From 682c91476f4919f8822a876d31a80dd9fd026cd1 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 16 Sep 2023 11:39:28 +1000
Subject: [PATCH 478/712] gowin: Himbaechel. Fix install path

Use himbaechel/gowin instead of himbaechel/gowin/gowin.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index d2b64e6e05..99eba6332a 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -48,5 +48,5 @@ foreach(device ${HIMBAECHEL_GOWIN_DEVICES})
 endforeach()
 
 add_custom_target(chipdb-himbaechel-gowin ALL DEPENDS ${chipdb_binaries})
-install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/gowin DESTINATION share/nextpnr/himbaechel/gowin
+install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/gowin/ DESTINATION share/nextpnr/himbaechel/gowin
 	    PATTERN "*.bba" EXCLUDE)

From 8e84006ee71ce941b4f089bd824ce139f4cefad5 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 16 Sep 2023 16:17:55 +1000
Subject: [PATCH 479/712] gowin: Himbaechel. Specify the chip variant.

For GW2A-18 and GW1N-9 you need to specify the family in addition to partno.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index f67e9b4e43..ed2c3fcc29 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -81,9 +81,9 @@ void GowinImpl::init_database(Arch *arch)
     if (args.options.count("family")) {
         family = args.options.at("family");
     } else {
-        bool GW2 = args.device == "GW2A-LV18PG256C8/I7";
+        bool GW2 = args.device.rfind("GW2A", 0) == 0;
         if (GW2) {
-            family = "GW2A-18";
+            log_error("For the GW2A series you need to specify -vopt family=GW2A-18 or -vopt family=GW2A-18C\n");
         } else {
             std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
             std::smatch match;
@@ -91,6 +91,9 @@ void GowinImpl::init_database(Arch *arch)
                 log_error("Invalid device %s\n", args.device.c_str());
             }
             family = stringf("GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
+            if (family.rfind("GW1N-9", 0) == 0) {
+                log_error("For the GW1N-9 series you need to specify -vopt family=GW1N-9 or -vopt family=GW1N-9C\n");
+            }
         }
     }
 

From 38d2a4b8444bd32e46cf135d1defe75b85280c46 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Mon, 25 Sep 2023 11:35:25 +0200
Subject: [PATCH 480/712] tmg: Fix argument order in run method

Router 2 expects "update_route_delays" to be the first argument to `tmg.run`.
---
 common/kernel/timing.cc | 6 +++---
 common/kernel/timing.h  | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 368132657b..7b66c52bf5 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -45,11 +45,11 @@ void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool
     topo_sort();
     setup_port_domains();
     identify_related_domains();
-    run(update_net_timings, update_histogram, update_crit_paths, true);
+    run(true, update_net_timings, update_histogram, update_crit_paths);
 }
 
-void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths,
-                         bool update_route_delays)
+void TimingAnalyser::run(bool update_route_delays, bool update_net_timings, bool update_histogram,
+                         bool update_crit_paths)
 {
     reset_times();
     if (update_route_delays)
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 2610c618d9..3dabe4f1d3 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -77,8 +77,8 @@ struct TimingAnalyser
     TimingAnalyser(Context *ctx);
 
     void setup(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false);
-    void run(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false,
-             bool update_route_delays = true);
+    void run(bool update_route_delays = true, bool update_net_timings = false, bool update_histogram = false,
+             bool update_crit_paths = false);
 
     // This is used when routers etc are not actually binding detailed routing (due to congestion or an abstracted
     // model), but want to re-run STA with their own calculated delays

From 3f2e550f51fe3d821a6ac845b3b6b1bb55c066b5 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Mon, 25 Sep 2023 11:37:11 +0200
Subject: [PATCH 481/712] tmg: Fix logging of slack histogram

---
 common/kernel/timing_log.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 2a2137b5fc..1bc1e1168a 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -365,7 +365,7 @@ void Context::log_timing_results(TimingResult &result, bool print_histogram, boo
     if (print_fmax)
         log_fmax(this, result, warn_on_failure);
 
-    if (print_histogram && !timing_result.slack_histogram.empty())
+    if (print_histogram && !result.slack_histogram.empty())
         log_histogram(this, result);
 }
 

From c07ca64ebefc9d796ae0e11dc83a2c11e96a8b8b Mon Sep 17 00:00:00 2001
From: Wanda <wanda@phinode.net>
Date: Wed, 27 Sep 2023 16:00:16 +0200
Subject: [PATCH 482/712] hashlib: Improve pool hash function.

---
 common/kernel/hashlib.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/hashlib.h b/common/kernel/hashlib.h
index a3fcd4cabc..008a581e53 100644
--- a/common/kernel/hashlib.h
+++ b/common/kernel/hashlib.h
@@ -1004,7 +1004,7 @@ template <typename K, typename OPS> class pool
 
     bool operator!=(const pool &other) const { return !operator==(other); }
 
-    bool hash() const
+    unsigned int hash() const
     {
         unsigned int hashval = mkhash_init;
         for (auto &it : entries)

From e8602fb56dce316be506fb69a12f6380eb113712 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Thu, 28 Sep 2023 14:26:13 +0200
Subject: [PATCH 483/712] std::numeric_limits<delay_t>::lowest() -> ::min()

---
 common/kernel/timing.cc      | 2 +-
 common/route/router1.cc      | 6 +++---
 fpga_interchange/cost_map.cc | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7b66c52bf5..7256ed1b18 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -770,7 +770,7 @@ void TimingAnalyser::build_detailed_net_timing_report()
 std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair, int count)
 {
     std::vector<CellPortKey> worst_eps;
-    delay_t last_slack = std::numeric_limits<delay_t>::min();
+    delay_t last_slack = std::numeric_limits<delay_t>::lowest();
     auto &dp = domain_pairs.at(domain_pair);
     auto &cap_d = domains.at(dp.key.capture);
     while (int(worst_eps.size()) < count) {
diff --git a/common/route/router1.cc b/common/route/router1.cc
index e4b2937210..e832177d2c 100644
--- a/common/route/router1.cc
+++ b/common/route/router1.cc
@@ -811,7 +811,7 @@ struct Router1
             for (auto &usr : ni->users) {
                 ++arc_count;
                 delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
-                if (slack == std::numeric_limits<delay_t>::min())
+                if (slack == std::numeric_limits<delay_t>::lowest())
                     continue;
                 if (slack < default_thresh)
                     ++failed_count;
@@ -829,7 +829,7 @@ struct Router1
                 continue;
             for (auto &usr : ni->users) {
                 delay_t slack = tmg.get_setup_slack(CellPortKey(usr));
-                if (slack == std::numeric_limits<delay_t>::min())
+                if (slack == std::numeric_limits<delay_t>::lowest())
                     continue;
                 slacks.push_back(slack);
             }
@@ -941,7 +941,7 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
                         continue;
                     for (auto &usr : ni->users) {
                         delay_t slack = router.tmg.get_setup_slack(CellPortKey(usr));
-                        if (slack == std::numeric_limits<delay_t>::min())
+                        if (slack == std::numeric_limits<delay_t>::lowest())
                             continue;
                         if (slack < 0) {
                             wns = std::min(wns, slack);
diff --git a/fpga_interchange/cost_map.cc b/fpga_interchange/cost_map.cc
index d960c7cf04..1062bfd6c9 100644
--- a/fpga_interchange/cost_map.cc
+++ b/fpga_interchange/cost_map.cc
@@ -318,7 +318,7 @@ void CostMap::fill_holes(const Context *ctx, const TypeWirePair &type_pair, boos
 delay_t CostMap::get_penalty(const boost::multi_array<delay_t, 2> &matrix) const
 {
     delay_t min_delay = std::numeric_limits<delay_t>::max();
-    delay_t max_delay = std::numeric_limits<delay_t>::min();
+    delay_t max_delay = std::numeric_limits<delay_t>::lowest();
 
     std::pair<int32_t, int32_t> min_location(0, 0), max_location(0, 0);
     for (unsigned ix = 0; ix < matrix.shape()[0]; ix++) {

From 58cb8a830a0ad690f659a85353c04d0568796657 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 20 Sep 2023 08:27:40 +0200
Subject: [PATCH 484/712] Load timing data

---
 machxo2/arch.cc          |   8 +-
 machxo2/arch.h           |  49 ++++++++-
 machxo2/constids.inc     |  30 +++++-
 machxo2/facade_import.py | 210 +++++++++++++++++++++++++++++++++++++--
 4 files changed, 279 insertions(+), 18 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 3c135e8f87..c6be48a243 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -47,6 +47,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 // ---------------------------------------------------------------
 
 static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
+                          const SpeedGradePOD **speed_grade,
                           const char **device_name, const char **package_name)
 {
     std::stringstream ss(available_devices);
@@ -58,7 +59,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
             continue; // chipdb not available
         for (auto &chip : db_ptr->get()->variants) {
             for (auto &pkg : chip.packages) {
-                for (auto &speedgrade : chip.speed_grades) {
+                for (auto &speedgrade : chip.speeds) {
                     for (auto &rating : chip.suffixes) {
                         std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
                                                       pkg.short_name.get(), rating.suffix.get());
@@ -67,6 +68,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
                             *package_info = nullptr;
                             *package_name = pkg.name.get();
                             *device_name = chip.name.get();
+                            *speed_grade = &(db_ptr->get()->speed_grades[speedgrade.index]);
                             for (auto &pi : db_ptr->get()->package_info) {
                                 if (pkg.name.get() == pi.name.get()) {
                                     *package_info = &pi;
@@ -86,7 +88,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
 
 Arch::Arch(ArchArgs args) : args(args)
 {
-    get_chip_info(args.device, &chip_info, &package_info, &device_name, &package_name);
+    get_chip_info(args.device, &chip_info, &package_info, &speed_grade, &device_name, &package_name);
     if (chip_info == nullptr)
         log_error("Unsupported MachXO2 chip type.\n");
     if (chip_info->const_id_count != DB_CONST_ID_COUNT)
@@ -165,7 +167,7 @@ void Arch::list_devices()
             continue; // chipdb not available
         for (auto &chip : db_ptr->get()->variants) {
             for (auto &pkg : chip.packages) {
-                for (auto &speedgrade : chip.speed_grades) {
+                for (auto &speedgrade : chip.speeds) {
                     for (auto &rating : chip.suffixes) {
                         log("    %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(),
                             rating.suffix.get());
diff --git a/machxo2/arch.h b/machxo2/arch.h
index 4792c79db4..df10d9b096 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -58,10 +58,9 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     LocationPOD src, dst;
     int32_t src_idx, dst_idx;
-    int32_t timing_class;
-    int16_t tile_type;
+    int16_t timing_class;
+    int8_t tile_type;
     int8_t pip_type;
-    int8_t padding;
     int16_t lutperm_flags;
     int16_t padding2;
 });
@@ -117,6 +116,40 @@ NPNR_PACKED_STRUCT(struct TileNamePOD {
 
 NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice<TileNamePOD> tile_names; });
 
+NPNR_PACKED_STRUCT(struct CellPropDelayPOD {
+    int32_t from_port;
+    int32_t to_port;
+    int32_t min_delay;
+    int32_t max_delay;
+});
+
+NPNR_PACKED_STRUCT(struct CellSetupHoldPOD {
+    int32_t sig_port;
+    int32_t clock_port;
+    int32_t min_setup;
+    int32_t max_setup;
+    int32_t min_hold;
+    int32_t max_hold;
+});
+
+NPNR_PACKED_STRUCT(struct CellTimingPOD {
+    int32_t cell_type;
+    RelSlice<CellPropDelayPOD> prop_delays;
+    RelSlice<CellSetupHoldPOD> setup_holds;
+});
+
+NPNR_PACKED_STRUCT(struct PipDelayPOD {
+    int32_t min_base_delay;
+    int32_t max_base_delay;
+    int32_t min_fanout_adder;
+    int32_t max_fanout_adder;
+});
+
+NPNR_PACKED_STRUCT(struct SpeedGradePOD {
+    RelSlice<CellTimingPOD> cell_timings;
+    RelSlice<PipDelayPOD> pip_classes;
+});
+
 NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
     RelPtr<char> name;
     RelPtr<char> short_name;
@@ -124,12 +157,15 @@ NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
 
 NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr<char> suffix; });
 
-NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { int32_t speed; });
+NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { 
+    int16_t speed; 
+    int16_t index;
+});
 
 NPNR_PACKED_STRUCT(struct VariantInfoPOD {
     RelPtr<char> name;
     RelSlice<PackageSupportedPOD> packages;
-    RelSlice<SpeedSupportedPOD> speed_grades;
+    RelSlice<SpeedSupportedPOD> speeds;
     RelSlice<SuffixeSupportedPOD> suffixes;
 });
 
@@ -148,6 +184,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelSlice<TileInfoPOD> tile_info;
     RelSlice<VariantInfoPOD> variants;
     RelSlice<SpineInfoPOD> spines;
+    RelSlice<SpeedGradePOD> speed_grades;
 });
 
 /************************ End of chipdb section. ************************/
@@ -383,6 +420,8 @@ struct Arch : BaseArch<ArchRanges>
 {
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info;
+    const SpeedGradePOD *speed_grade;
+
     const char *package_name;
     const char *device_name;
 
diff --git a/machxo2/constids.inc b/machxo2/constids.inc
index 3abeab14f8..6f074d90ca 100644
--- a/machxo2/constids.inc
+++ b/machxo2/constids.inc
@@ -1,3 +1,29 @@
+X(DP8KC_REGMODE_A_NOREG_REGMODE_B_NOREG)
+X(DP8KC_REGMODE_A_NOREG_REGMODE_B_OUTREG)
+X(DP8KC_REGMODE_A_OUTREG_REGMODE_B_NOREG)
+X(DP8KC_REGMODE_A_OUTREG_REGMODE_B_OUTREG)
+X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_NORMAL)
+X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_READBEFOREWRITE)
+X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_WRITETHROUGH)
+X(PIO_IOTYPE_LVCMOS12)
+X(PIO_IOTYPE_LVCMOS15)
+X(PIO_IOTYPE_LVCMOS18)
+X(PIO_IOTYPE_LVCMOS25)
+X(PIO_IOTYPE_LVCMOS33)
+X(PIO_IOTYPE_LVDS)
+X(PIO_IOTYPE_SSTL15_I)
+X(PIO_IOTYPE_SSTL15_II)
+X(PIO_IOTYPE_SSTL18_I)
+X(PIO_IOTYPE_SSTL18_II)
+X(PIO_IOTYPE_LVDS25)
+X(PIO_IOTYPE_LVPECL33)
+X(PIO_IOTYPE_LVTTL33)
+X(PIO_IOTYPE_MIPI)
+X(PAD)
+X(PADDI)
+X(PADDO)
+X(PADDT)
+
 X(TRELLIS_SLICE)
 X(A0)
 X(B0)
@@ -612,7 +638,6 @@ X(TIOLOGIC)
 X(TSIOLOGIC)
 X(RIOLOGIC)
 
-X(PADDI)
 X(INDD)
 X(TDX0)
 X(TDX1)
@@ -666,3 +691,6 @@ X(TAMPERDETCLK)
 X(RESEN)
 X(PULLUPEN)
 X(SLEWRATE)
+
+X(TRELLIS_COMB_CARRY0)
+X(TRELLIS_COMB_CARRY1)
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 04b16b31be..3747daeaad 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -18,6 +18,8 @@
 sys.path += args.libdir
 import pytrellis
 import database
+import pip_classes
+import timing_dbs
 
 with open(args.gfxh) as f:
     state = 0
@@ -213,7 +215,158 @@ def process_pio_db(rg, device):
             if bel_idx is not None:
                 pindata.append((loc, bel_idx, bank, pinfunc, dqs))
 
-def write_database(dev_name, chip, rg, endianness):
+
+speed_grade_names = { 
+    "MachXO2": ["1", "2", "3", "4", "5", "6"],
+    "MachXO3": ["5", "6"],
+    "MachXO3D": ["2", "3", "5", "6"]
+}
+speed_grade_cells = {}
+speed_grade_pips = {}
+
+pip_class_to_idx = {"default": 0, "zero": 1}
+
+timing_port_xform = {
+    "RAD0": "D0",
+    "RAD1": "B0",
+    "RAD2": "C0",
+    "RAD3": "A0",
+}
+
+
+delay_db = {}
+# Convert from Lattice-style grouped SLICE to new nextpnr split style SLICE
+def postprocess_timing_data(cells):
+    def delay_diff(x, y):
+        return (x[0] - y[0], x[1] - y[1])
+
+    split_cells = {}
+    comb_delays = {}
+    comb_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
+    comb_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
+    comb_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
+    comb_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
+    #comb_delays[("A", "OFX")] = delay_db["SLICE"][("A0", "OFX0")]
+    #comb_delays[("B", "OFX")] = delay_db["SLICE"][("B0", "OFX0")]
+    #comb_delays[("C", "OFX")] = delay_db["SLICE"][("C0", "OFX0")]
+    #comb_delays[("D", "OFX")] = delay_db["SLICE"][("D0", "OFX0")]
+    #comb_delays[("M", "OFX")] = delay_db["SLICE"][("M0", "OFX0")] # worst case
+    #comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLICE"][("A1", "OFX0")],
+    #                                        delay_db["SLICE"][("A1", "F1")])
+    #comb_delays[("FXA", "OFX")] = delay_db["SLICE"][("FXA", "OFX1")]
+    #comb_delays[("FXB", "OFX")] = delay_db["SLICE"][("FXB", "OFX1")]
+    split_cells["TRELLIS_COMB"] = comb_delays
+
+    carry0_delays = {}
+    carry0_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
+    carry0_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
+    carry0_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
+    carry0_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
+    #carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
+    #carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
+    #carry0_delays[("C", "FCO")] = delay_db["SLICE"][("C0", "FCO")]
+    #carry0_delays[("D", "FCO")] = delay_db["SLICE"][("D0", "FCO")]
+    #carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
+    #carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
+
+    split_cells["TRELLIS_COMB_CARRY0"] = carry0_delays
+
+    carry1_delays = {}
+    carry1_delays[("A", "F")] = delay_db["SLICE"][("A1", "F1")]
+    carry1_delays[("B", "F")] = delay_db["SLICE"][("B1", "F1")]
+    carry1_delays[("C", "F")] = delay_db["SLICE"][("C1", "F1")]
+    carry1_delays[("D", "F")] = delay_db["SLICE"][("D1", "F1")]
+    #carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
+    #carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
+    #carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
+    #carry1_delays[("D", "FCO")] = delay_db["SLICE"][("D1", "FCO")]
+    #carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
+    #carry1_delays[("FCI", "FCO")] = (0, 0)
+
+    split_cells["TRELLIS_COMB_CARRY1"] = carry1_delays
+
+    for celltype, celldelays in sorted(split_cells.items()):
+        delays = []
+        setupholds = []
+        for (from_pin, to_pin), (min_delay, max_delay) in sorted(celldelays.items()):
+            delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
+        cells.append((constids[celltype], delays, setupholds))
+
+def process_timing_data(family):
+    for grade in speed_grade_names[family]:
+        with open(timing_dbs.cells_db_path(family, grade)) as f:
+            cell_data = json.load(f)
+        cells = []
+        for cell, cdata in sorted(cell_data.items()):
+            celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
+            delays = []
+            setupholds = []
+            delay_db[cell] = {}
+            for entry in cdata:
+                if entry["type"] == "Width":
+                    continue
+                elif entry["type"] == "IOPath":
+                    from_pin = entry["from_pin"][1] if type(entry["from_pin"]) is list else entry["from_pin"]
+                    if from_pin in timing_port_xform:
+                        from_pin = timing_port_xform[from_pin]
+                    to_pin = entry["to_pin"]
+                    if to_pin in timing_port_xform:
+                        to_pin = timing_port_xform[to_pin]
+                    min_delay = min(entry["rising"][0], entry["falling"][0])
+                    max_delay = min(entry["rising"][2], entry["falling"][2])
+                    delay_db[cell][(from_pin, to_pin)] = (min_delay, max_delay)
+                    delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
+                elif entry["type"] == "SetupHold":
+                    if type(entry["pin"]) is list:
+                        continue
+                    pin = constids[entry["pin"]]
+                    clock = constids[entry["clock"][1]]
+                    min_setup = entry["setup"][0]
+                    max_setup = entry["setup"][2]
+                    min_hold = entry["hold"][0]
+                    max_hold = entry["hold"][2]
+                    setupholds.append((pin, clock, min_setup, max_setup, min_hold, max_hold))
+                else:
+                    assert False, entry["type"]
+            cells.append((celltype, delays, setupholds))
+        postprocess_timing_data(cells)
+        pip_class_delays = []
+        for i in range(len(pip_class_to_idx)):
+            pip_class_delays.append((50, 50, 0, 0))
+        pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
+        with open(timing_dbs.interconnect_db_path(family, grade)) as f:
+            interconn_data = json.load(f)
+        for pipclass, pipdata in sorted(interconn_data.items()):
+
+            min_delay = pipdata["delay"][0] * 1.1
+            max_delay = pipdata["delay"][2] * 1.1
+            min_fanout = pipdata["fanout"][0]
+            max_fanout = pipdata["fanout"][2]
+            if grade == "6":
+                pip_class_to_idx[pipclass] = len(pip_class_delays)
+                pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
+            else:
+                if pipclass in pip_class_to_idx:
+                    pip_class_delays[pip_class_to_idx[pipclass]] = (min_delay, max_delay, min_fanout, max_fanout)
+        speed_grade_cells[grade] = cells
+        speed_grade_pips[grade] = pip_class_delays
+
+
+def get_pip_class(wire_from, wire_to):
+
+    if "FCO" in wire_from or "FCI" in wire_to:
+        return pip_class_to_idx["zero"]
+    if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
+        return pip_class_to_idx["zero"]
+
+    class_name = pip_classes.get_pip_class(wire_from, wire_to)
+    if class_name is None or class_name not in pip_class_to_idx:
+        class_name = "default"
+    return pip_class_to_idx[class_name]
+
+
+
+def write_database(family, dev_name, chip, rg, endianness):
     def write_loc(loc, sym_name):
         bba.u16(loc.x, "%s.x" % sym_name)
         bba.u16(loc.y, "%s.y" % sym_name)
@@ -261,13 +414,10 @@ def get_wire_name(loc, idx):
                 bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
                 src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
                 snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
-                # TODO: ECP5 timing-model-specific. Reuse for MachXO2?
-                # bba.u32(get_pip_class(src_name, snk_name), "timing_class")
-                bba.u32(0, "timing_class")
-                bba.u16(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
+                bba.u16(get_pip_class(src_name, snk_name), "timing_class")
+                bba.u8(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
                 cls = arc.cls
-                bba.u8(arc.cls, "pip_type")
-                bba.u8(0, "padding")
+                bba.u8(cls, "pip_type")
                 bba.u16(arc.lutperm_flags, "lutperm_flags")
                 bba.u16(0, "padding2")
 
@@ -375,6 +525,45 @@ def get_wire_name(loc, idx):
     for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
         bba.s(tt, "name")
 
+    for grade in speed_grade_names[family]:
+        for cell in speed_grade_cells[grade]:
+            celltype, delays, setupholds = cell
+            if len(delays) > 0:
+                bba.l("cell_%d_delays_%s" % (celltype, grade))
+                for delay in delays:
+                    from_pin, to_pin, min_delay, max_delay = delay
+                    bba.u32(from_pin, "from_pin")
+                    bba.u32(to_pin, "to_pin")
+                    bba.u32(min_delay, "min_delay")
+                    bba.u32(max_delay, "max_delay")
+            if len(setupholds) > 0:
+                bba.l("cell_%d_setupholds_%s" % (celltype, grade))
+                for sh in setupholds:
+                    pin, clock, min_setup, max_setup, min_hold, max_hold = sh
+                    bba.u32(pin, "sig_port")
+                    bba.u32(clock, "clock_port")
+                    bba.u32(min_setup, "min_setup")
+                    bba.u32(max_setup, "max_setup")
+                    bba.u32(min_hold, "min_hold")
+                    bba.u32(max_hold, "max_hold")
+        bba.l("cell_timing_data_%s" % grade)
+        for cell in speed_grade_cells[grade]:
+            celltype, delays, setupholds = cell
+            bba.u32(celltype, "cell_type")
+            bba.r_slice("cell_%d_delays_%s" % (celltype, grade) if len(delays) > 0 else None, len(delays), "delays")
+            bba.r_slice("cell_%d_setupholds_%s" % (celltype, grade) if len(delays) > 0 else None, len(setupholds), "setupholds")
+        bba.l("pip_timing_data_%s" % grade)
+        for pipclass in speed_grade_pips[grade]:
+            min_delay, max_delay, min_fanout, max_fanout = pipclass
+            bba.u32(min_delay, "min_delay")
+            bba.u32(max_delay, "max_delay")
+            bba.u32(min_fanout, "min_fanout")
+            bba.u32(max_fanout, "max_fanout")
+    bba.l("speed_grade_data")
+    for grade in speed_grade_names[family]:
+        bba.r_slice("cell_timing_data_%s" % grade, len(speed_grade_cells[grade]), "cell_timings")
+        bba.r_slice("pip_timing_data_%s" % grade, len(speed_grade_pips[grade]), "pip_classes")
+
     for name, var_data in sorted(variants.items()):
         bba.l("supported_packages_%s" % name, "PackageSupportedPOD")
         for package in var_data["packages"]:
@@ -382,7 +571,8 @@ def get_wire_name(loc, idx):
             bba.s(package_shortname(package, chip.info.family), "short_name")
         bba.l("supported_speed_grades_%s" % name, "SpeedSupportedPOD")
         for speed in var_data["speeds"]:
-            bba.u32(speed, "speed")
+            bba.u16(speed, "speed")
+            bba.u16(speed_grade_names[family].index(str(speed)), "index")
         bba.l("supported_suffixes_%s" % name, "SuffixeSupportedPOD")
         for suffix in var_data["suffixes"]:
             bba.s(suffix, "suffix")
@@ -414,6 +604,7 @@ def get_wire_name(loc, idx):
     bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info")
     bba.r_slice("variant_data", len(variants), "variant_info")
     bba.r_slice("spine_info", len(spines), "spine_info")
+    bba.r_slice("speed_grade_data", len(speed_grade_names[family]), "speed_grades")
 
     bba.pop()
     return bba
@@ -492,9 +683,10 @@ def main():
     rg = pytrellis.make_optimized_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
     max_row = chip.get_max_row()
     max_col = chip.get_max_col()
+    process_timing_data(dev_family[args.device])
     process_pio_db(rg, args.device)
     process_devices_db(chip.info.family, chip.info.name)
-    bba = write_database(args.device, chip, rg, "le")
+    bba = write_database(dev_family[args.device],args.device, chip, rg, "le")
 
 
 

From 1edb44960183648041951a194f9141d83813cfa4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 20 Sep 2023 08:30:25 +0200
Subject: [PATCH 485/712] optimization/cleanup

---
 machxo2/arch.h           | 4 ++--
 machxo2/facade_import.py | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/machxo2/arch.h b/machxo2/arch.h
index df10d9b096..d05346f3cc 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -57,12 +57,12 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     LocationPOD src, dst;
-    int32_t src_idx, dst_idx;
+    int16_t src_idx, dst_idx;
     int16_t timing_class;
     int8_t tile_type;
     int8_t pip_type;
     int16_t lutperm_flags;
-    int16_t padding2;
+    int16_t padding;
 });
 
 inline bool is_lutperm_pip(int16_t flags) { return flags & 0x4000; }
diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 3747daeaad..8282e107e9 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -410,8 +410,8 @@ def get_wire_name(loc, idx):
             for arc in t.arcs:
                 write_loc(arc.srcWire.rel, "src")
                 write_loc(arc.sinkWire.rel, "dst")
-                bba.u32(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
-                bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
+                bba.u16(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
+                bba.u16(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
                 src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
                 snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
                 bba.u16(get_pip_class(src_name, snk_name), "timing_class")
@@ -419,7 +419,7 @@ def get_wire_name(loc, idx):
                 cls = arc.cls
                 bba.u8(cls, "pip_type")
                 bba.u16(arc.lutperm_flags, "lutperm_flags")
-                bba.u16(0, "padding2")
+                bba.u16(0, "padding")
 
         if len(t.wires) > 0:
             for wire_idx in range(len(t.wires)):

From 40313eacf0b33c7ac823a69c4f8539ea2856cdcf Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 20 Sep 2023 09:10:46 +0200
Subject: [PATCH 486/712] fix import

---
 machxo2/facade_import.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 8282e107e9..b33d3b05fe 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -342,7 +342,7 @@ def process_timing_data(family):
             max_delay = pipdata["delay"][2] * 1.1
             min_fanout = pipdata["fanout"][0]
             max_fanout = pipdata["fanout"][2]
-            if grade == "6":
+            if grade == speed_grade_names[family][0]:
                 pip_class_to_idx[pipclass] = len(pip_class_delays)
                 pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
             else:

From c2b75b355fd4adecb7c9f2a97c3040ddc1381b02 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 20 Sep 2023 11:40:31 +0200
Subject: [PATCH 487/712] use timing data

---
 machxo2/arch.cc       | 462 ++++++++++++++++++++++++++++++++++++++++--
 machxo2/arch.h        |  59 +++++-
 machxo2/arch_place.cc |  32 +++
 machxo2/pack.cc       |   1 +
 4 files changed, 531 insertions(+), 23 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index c6be48a243..6477c49b1f 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -18,6 +18,8 @@
  *
  */
 
+#include <boost/iostreams/device/mapped_file.hpp>
+#include <boost/range/adaptor/reversed.hpp>
 #include <iostream>
 #include <math.h>
 #include "embed.h"
@@ -48,7 +50,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 
 static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
                           const SpeedGradePOD **speed_grade,
-                          const char **device_name, const char **package_name)
+                          const char **device_name, const char **package_name, int *device_speed)
 {
     std::stringstream ss(available_devices);
     std::string name;
@@ -68,6 +70,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
                             *package_info = nullptr;
                             *package_name = pkg.name.get();
                             *device_name = chip.name.get();
+                            *device_speed = speedgrade.index;
                             *speed_grade = &(db_ptr->get()->speed_grades[speedgrade.index]);
                             for (auto &pi : db_ptr->get()->package_info) {
                                 if (pkg.name.get() == pi.name.get()) {
@@ -88,7 +91,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
 
 Arch::Arch(ArchArgs args) : args(args)
 {
-    get_chip_info(args.device, &chip_info, &package_info, &speed_grade, &device_name, &package_name);
+    get_chip_info(args.device, &chip_info, &package_info, &speed_grade, &device_name, &package_name, &device_speed);
     if (chip_info == nullptr)
         log_error("Unsupported MachXO2 chip type.\n");
     if (chip_info->const_id_count != DB_CONST_ID_COUNT)
@@ -364,35 +367,127 @@ BelId Arch::getBelByLocation(Loc loc) const
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
-    // Taxicab distance multiplied by pipDelay (0.01) and fake wireDelay (0.01).
-    // TODO: This function will not work well for entrance to global routing,
-    // as the entrances are located physically far from the DCCAs.
-    return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
+    int num_uh = tile_info(dst)->wire_data[dst.index].pips_uphill.size();
+    if (num_uh < 6) {
+        for (auto uh : getPipsUphill(dst)) {
+            if (getPipSrcWire(uh) == src)
+                return getPipDelay(uh).maxDelay();
+        }
+    }
+
+    auto est_location = [&](WireId w) -> std::pair<int, int> {
+        const auto &wire = tile_info(w)->wire_data[w.index];
+        if (w == gsrclk_wire) {
+            auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
+            return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
+        } else if (wire.bel_pins.size() > 0) {
+            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x,
+                                  wire.bel_pins[0].rel_bel_loc.y);
+        } else if (wire.pips_downhill.size() > 0) {
+            return std::make_pair(wire.pips_downhill[0].rel_loc.x,
+                                  wire.pips_downhill[0].rel_loc.y);
+        } else if (wire.pips_uphill.size() > 0) {
+            return std::make_pair(wire.pips_uphill[0].rel_loc.x,
+                                  wire.pips_uphill[0].rel_loc.y);
+        } else {
+            return std::make_pair(int(w.location.x), int(w.location.y));
+        }
+    };
+
+    auto src_loc = est_location(src);
+    std::pair<int, int> dst_loc;
+    if (wire_loc_overrides.count(dst)) {
+        dst_loc = wire_loc_overrides.at(dst);
+    } else {
+        dst_loc = est_location(dst);
+    }
+
+    int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
+
+    return (120 - 22 * device_speed) *
+           (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
 BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     BoundingBox bb;
-    bb.x0 = std::min(src.location.x, dst.location.x);
-    bb.y0 = std::min(src.location.y, dst.location.y);
-    bb.x1 = std::max(src.location.x, dst.location.x);
-    bb.y1 = std::max(src.location.y, dst.location.y);
+
+    bb.x0 = src.location.x;
+    bb.y0 = src.location.y;
+    bb.x1 = src.location.x;
+    bb.y1 = src.location.y;
+
+    auto extend = [&](int x, int y) {
+        bb.x0 = std::min(bb.x0, x);
+        bb.x1 = std::max(bb.x1, x);
+        bb.y0 = std::min(bb.y0, y);
+        bb.y1 = std::max(bb.y1, y);
+    };
+
+    auto est_location = [&](WireId w) -> std::pair<int, int> {
+        const auto &wire = tile_info(w)->wire_data[w.index];
+        if (w == gsrclk_wire) {
+            auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
+            return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
+        } else if (wire.bel_pins.size() > 0) {
+            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x,
+                                  wire.bel_pins[0].rel_bel_loc.y);
+        } else if (wire.pips_downhill.size() > 0) {
+            return std::make_pair(wire.pips_downhill[0].rel_loc.x,
+                                  wire.pips_downhill[0].rel_loc.y);
+        } else if (wire.pips_uphill.size() > 0) {
+            return std::make_pair(wire.pips_uphill[0].rel_loc.x,
+                                  wire.pips_uphill[0].rel_loc.y);
+        } else {
+            return std::make_pair(int(w.location.x), int(w.location.y));
+        }
+    };
+
+    auto src_loc = est_location(src);
+    extend(src_loc.first, src_loc.second);
+    if (wire_loc_overrides.count(src)) {
+        extend(wire_loc_overrides.at(src).first, wire_loc_overrides.at(src).second);
+    }
+    std::pair<int, int> dst_loc;
+    extend(dst.location.x, dst.location.y);
+    if (wire_loc_overrides.count(dst)) {
+        dst_loc = wire_loc_overrides.at(dst);
+    } else {
+        dst_loc = est_location(dst);
+    }
+    extend(dst_loc.first, dst_loc.second);
     return bb;
 }
 
 delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
 {
-    NPNR_UNUSED(src_pin);
-    NPNR_UNUSED(dst_pin);
+    if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin.in(id_FXA, id_FXB) || (src_pin == id_F && dst_pin == id_DI))
+        return 0;
+    auto driver_loc = getBelLocation(src_bel);
+    auto sink_loc = getBelLocation(dst_bel);
+    // Encourage use of direct interconnect
+    //   exact LUT input doesn't matter as they can be permuted by the router...
+    if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
+        if (dst_pin.in(id_A, id_B, id_C, id_D) && src_pin == id_Q) {
+            int lut = (sink_loc.z >> lc_idx_shift), ff = (driver_loc.z >> lc_idx_shift);
+            if (lut == ff)
+                return 0;
+        }
+        if (dst_pin.in(id_A, id_B, id_C, id_D) && src_pin == id_F) {
+            int l0 = (driver_loc.z >> lc_idx_shift);
+            if (l0 != 1 && l0 != 6)
+                return 0;
+        }
+    }
 
-    NPNR_ASSERT(src_bel != BelId());
-    NPNR_ASSERT(dst_bel != BelId());
+    int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
 
-    // TODO: Same deal applies here as with estimateDelay.
-    return (abs(dst_bel.location.x - src_bel.location.x) + abs(dst_bel.location.y - src_bel.location.y)) *
-           (0.01 + 0.01);
+    return (120 - 22 * device_speed) *
+           (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
+delay_t Arch::getRipupDelayPenalty() const { return 400; }
+
 // ---------------------------------------------------------------
 
 bool Arch::place()
@@ -433,6 +528,8 @@ bool Arch::route()
 
     disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
 
+    setup_wire_locations();
+
     assignArchInfo();
 
     route_globals();
@@ -534,6 +631,337 @@ DecalXY Arch::getGroupDecal(GroupId group) const
     return decalxy;
 }
 
+// -----------------------------------------------------------------------
+
+bool Arch::get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayQuad &delay) const
+{
+    auto fnd_dk = celldelay_cache.find({tctype, from, to});
+    if (fnd_dk != celldelay_cache.end()) {
+        delay = fnd_dk->second.second;
+        return fnd_dk->second.first;
+    }
+    for (auto &tc : speed_grade->cell_timings) {
+        if (tc.cell_type == tctype.index) {
+            for (auto &dly : tc.prop_delays) {
+                if (dly.from_port == from.index && dly.to_port == to.index) {
+                    delay = DelayQuad(dly.min_delay, dly.max_delay);
+                    celldelay_cache[{tctype, from, to}] = std::make_pair(true, delay);
+                    return true;
+                }
+            }
+            celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayQuad());
+            return false;
+        }
+    }
+    NPNR_ASSERT_FALSE("failed to find timing cell in db");
+}
+
+void Arch::get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayPair &setup,
+                                     DelayPair &hold) const
+{
+    for (auto &tc : speed_grade->cell_timings) {
+        if (tc.cell_type == tctype.index) {
+            for (auto &sh : tc.setup_holds) {
+                if (sh.clock_port == clock.index && sh.sig_port == port.index) {
+                    setup.max_delay = sh.max_setup;
+                    setup.min_delay = sh.min_setup;
+                    hold.max_delay = sh.max_hold;
+                    hold.min_delay = sh.min_hold;
+                    return;
+                }
+            }
+        }
+    }
+    NPNR_ASSERT_FALSE("failed to find timing cell in db");
+}
+
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
+{
+    // Data for -8 grade
+    if (cell->type == id_TRELLIS_COMB) {
+        bool has_carry = cell->combInfo.flags & ArchCellInfo::COMB_CARRY;
+        IdString tmg_type = has_carry ? (((cell->constr_z >> Arch::lc_idx_shift) % 2) ? id_TRELLIS_COMB_CARRY1
+                                                                                      : id_TRELLIS_COMB_CARRY0)
+                                      : id_TRELLIS_COMB;
+        if (fromPort.in(id_A, id_B, id_C, id_D, id_M, id_F1, id_FXA, id_FXB, id_FCI))
+            return get_delay_from_tmg_db(tmg_type, fromPort, toPort, delay);
+        else
+            return false;
+    } else if (cell->type == id_TRELLIS_FF) {
+        return false;
+    } else if (cell->type == id_TRELLIS_RAMW) {
+        if ((fromPort == id_A0 && toPort == id_WADO0) || (fromPort == id_A1 && toPort == id_WDO0) ||
+            (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO1) ||
+            (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO2) ||
+            (fromPort == id_D0 && toPort == id_WADO3) || (fromPort == id_D1 && toPort == id_WDO3)) {
+            delay = DelayQuad(0);
+            return true;
+        }
+        return false;
+    } else if (cell->type == id_DCCA) {
+        if (fromPort == id_CLKI && toPort == id_CLKO) {
+            delay = DelayQuad(0);
+            return true;
+        }
+        return false;
+    } else if (cell->type == id_DP8KC) {
+        return false;
+/*    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
+        return false;*/
+    } else {
+        return false;
+    }
+}
+
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
+{
+    auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
+    clockInfoCount = 0;
+    if (cell->type == id_TRELLIS_COMB) {
+        if (port == id_WCK)
+            return TMG_CLOCK_INPUT;
+        if (port.in(id_A, id_B, id_C, id_D, id_FCI, id_FXA, id_FXB, id_F1))
+            return TMG_COMB_INPUT;
+        if (port == id_F && disconnected(id_A) && disconnected(id_B) && disconnected(id_C) && disconnected(id_D) &&
+            disconnected(id_FCI))
+            return TMG_IGNORE; // LUT with no inputs is a constant
+        if (port.in(id_F, id_FCO, id_OFX))
+            return TMG_COMB_OUTPUT;
+        if (port == id_M)
+            return TMG_COMB_INPUT;
+        if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        }
+        return TMG_IGNORE;
+    } else if (cell->type == id_TRELLIS_FF) {
+        bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        if (port == id_DI || (using_m && (port == id_M)) || port.in(id_CE, id_LSR)) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        }
+        if (port == id_Q) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_OUTPUT;
+        }
+        return TMG_IGNORE;
+    } else if (cell->type == id_TRELLIS_RAMW) {
+        if (port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))
+            return TMG_COMB_INPUT;
+        if (port.in(id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3))
+            return TMG_COMB_OUTPUT;
+        return TMG_IGNORE;
+    } else if (cell->type == id_TRELLIS_IO) {
+        if (port.in(id_T, id_I))
+            return TMG_ENDPOINT;
+        if (port == id_O)
+            return TMG_STARTPOINT;
+        return TMG_IGNORE;
+    } else if (cell->type == id_DCCA) {
+        if (port == id_CLKI)
+            return TMG_COMB_INPUT;
+        if (port == id_CLKO)
+            return TMG_COMB_OUTPUT;
+        return TMG_IGNORE;
+/*    } else if (cell->type == id_DCSC) {
+        if (port.in(id_CLK0, id_CLK1))
+            return TMG_COMB_INPUT;
+        if (port == id_DCSOUT)
+            return TMG_COMB_OUTPUT;
+        return TMG_IGNORE;*/
+    } else if (cell->type == id_DP8KC) {
+        if (port.in(id_CLKA, id_CLKB))
+            return TMG_CLOCK_INPUT;
+        std::string port_name = port.str(this);
+        for (auto c : boost::adaptors::reverse(port_name)) {
+            if (std::isdigit(c))
+                continue;
+            if (c == 'A' || c == 'B')
+                clockInfoCount = 1;
+            else
+                NPNR_ASSERT_FALSE_STR("bad ram port");
+            return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
+        }
+        NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
+    } else if (cell->type == id_EHXPLLJ) {
+        return TMG_IGNORE;
+/*    } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
+        if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
+            return TMG_CLOCK_INPUT;
+        std::string prefix = port.str(this).substr(0, 9);
+        if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
+            clockInfoCount = 1;
+            return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
+        }
+        return TMG_IGNORE;
+    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
+        if (port.in(id_CLK, id_ECLK)) {
+            return TMG_CLOCK_INPUT;
+        } else if (port.in(id_IOLDO, id_IOLDOI, id_IOLDOD, id_IOLTO, id_PADDI, id_DQSR90, id_DQSW, id_DQSW270)) {
+            return TMG_IGNORE;
+        } else {
+            clockInfoCount = 1;
+            return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
+        }*/
+    } else if (cell->type.in(/*id_DTR, id_USRMCLK,*/ id_SEDFA, id_GSR, id_JTAGF)) {
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+    } else if (cell->type.in(id_OSCH,id_OSCJ)) {
+        if (port == id_OSC)
+            return TMG_GEN_CLOCK;
+        else
+            return TMG_IGNORE;
+    } else if (cell->type == id_CLKDIVC) {
+        if (port == id_CLKI)
+            return TMG_CLOCK_INPUT;
+        else if (port.in(id_RST, id_ALIGNWD))
+            return TMG_ENDPOINT;
+        else if (port == id_CDIVX)
+            return TMG_GEN_CLOCK;
+        else
+            NPNR_ASSERT_FALSE("bad clkdiv port");
+/*    } else if (cell->type == id_DQSBUFM) {
+        if (port.in(id_READ0, id_READ1)) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        } else if (port == id_DATAVALID) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_OUTPUT;
+        } else if (port.in(id_SCLK, id_ECLK, id_DQSI)) {
+            return TMG_CLOCK_INPUT;
+        } else if (port.in(id_DQSR90, id_DQSW, id_DQSW270)) {
+            return TMG_GEN_CLOCK;
+        }
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+    } else if (cell->type == id_DDRDLL) {
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+    } else if (cell->type == id_TRELLIS_ECLKBUF) {
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
+    } else if (cell->type == id_ECLKSYNCB) {
+        if (cell->ports.at(port).name == id_STOP)
+            return TMG_ENDPOINT;
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
+    } else if (cell->type == id_ECLKBRIDGECS) {
+        if (cell->ports.at(port).name == id_SEL)
+            return TMG_ENDPOINT;
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
+*/
+    } else {
+        log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
+                  cell->name.c_str(this));
+    }
+}
+
+TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
+{
+    TimingClockingInfo info;
+    info.setup = DelayPair(0);
+    info.hold = DelayPair(0);
+    info.clockToQ = DelayQuad(0);
+    if (cell->type == id_TRELLIS_COMB) {
+        if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) {
+            if (port == id_WD)
+                port = id_WD0;
+            info.edge = (cell->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV) ? FALLING_EDGE : RISING_EDGE;
+            info.clock_port = id_WCK;
+            get_setuphold_from_tmg_db(id_TRELLIS_SLICE, id_WCK, port, info.setup, info.hold);
+        }
+    } else if (cell->type == id_TRELLIS_FF) {
+        bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED);
+        if (port.in(id_DI, id_CE, id_LSR) || (using_m && port == id_M)) {
+            if (port == id_DI)
+                port = id_DI0;
+            if (port == id_M)
+                port = id_M0;
+            info.edge = (cell->ffInfo.flags & ArchCellInfo::FF_CLKINV) ? FALLING_EDGE : RISING_EDGE;
+            info.clock_port = id_CLK;
+            get_setuphold_from_tmg_db(id_TRELLIS_SLICE, id_CLK, port, info.setup, info.hold);
+        } else {
+            NPNR_ASSERT(port == id_Q);
+            port = id_Q0;
+            info.edge = (cell->ffInfo.flags & ArchCellInfo::FF_CLKINV) ? FALLING_EDGE : RISING_EDGE;
+            info.clock_port = id_CLK;
+            bool is_path = get_delay_from_tmg_db(id_TRELLIS_SLICE, id_CLK, port, info.clockToQ);
+            NPNR_ASSERT(is_path);
+        }
+    } else if (cell->type == id_DP8KC) {
+        std::string port_name = port.str(this);
+        IdString half_clock;
+        for (auto c : boost::adaptors::reverse(port_name)) {
+            if (std::isdigit(c))
+                continue;
+            if (c == 'A') {
+                half_clock = id_CLKA;
+                break;
+            } else if (c == 'B') {
+                half_clock = id_CLKB;
+                break;
+            } else
+                NPNR_ASSERT_FALSE_STR("bad ram port " + port.str(this));
+        }
+        if (cell->ramInfo.is_pdp) {
+            bool is_output = cell->ports.at(port).type == PORT_OUT;
+            // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain
+            if (is_output || port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11,
+                                     id_ADB12))
+                info.clock_port = id_CLKB;
+            else
+                info.clock_port = id_CLKA;
+        } else {
+            info.clock_port = half_clock;
+        }
+        info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id_CLKBMUX : id_CLKAMUX, "CLK") == "INV")
+                            ? FALLING_EDGE
+                            : RISING_EDGE;
+        if (cell->ports.at(port).type == PORT_OUT) {
+            bool is_path = get_delay_from_tmg_db(cell->ramInfo.regmode_timing_id, half_clock, port, info.clockToQ);
+            NPNR_ASSERT(is_path);
+        } else {
+            get_setuphold_from_tmg_db(cell->ramInfo.regmode_timing_id, half_clock, port, info.setup, info.hold);
+        }
+/*    } else if (cell->type == id_DCUA) {
+        std::string prefix = port.str(this).substr(0, 9);
+        info.edge = RISING_EDGE;
+        if (prefix == "CH0_FF_TX")
+            info.clock_port = id_CH0_FF_TXI_CLK;
+        else if (prefix == "CH0_FF_RX")
+            info.clock_port = id_CH0_FF_RXI_CLK;
+        else if (prefix == "CH1_FF_TX")
+            info.clock_port = id_CH1_FF_TXI_CLK;
+        else if (prefix == "CH1_FF_RX")
+            info.clock_port = id_CH1_FF_RXI_CLK;
+        if (cell->ports.at(port).type == PORT_OUT) {
+            info.clockToQ = DelayQuad(getDelayFromNS(0.7));
+        } else {
+            info.setup = DelayPair(getDelayFromNS(1));
+            info.hold = DelayPair(getDelayFromNS(0));
+        }
+    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
+        info.clock_port = id_CLK;
+        info.edge = RISING_EDGE;
+        if (cell->ports.at(port).type == PORT_OUT) {
+            info.clockToQ = DelayQuad(getDelayFromNS(0.5));
+        } else {
+            info.setup = DelayPair(getDelayFromNS(0.1));
+            info.hold = DelayPair(getDelayFromNS(0));
+        }
+    } else if (cell->type == id_DQSBUFM) {
+        info.clock_port = id_SCLK;
+        info.edge = RISING_EDGE;
+        if (port == id_DATAVALID) {
+            info.clockToQ = DelayQuad(getDelayFromNS(0.2));
+        } else if (port.in(id_READ0, id_READ1)) {
+            info.setup = DelayPair(getDelayFromNS(0.5));
+            info.hold = DelayPair(getDelayFromNS(-0.4));
+        } else {
+            NPNR_ASSERT_FALSE("unknown DQSBUFM register port");*/
+        }
+    return info;
+}
+
 // ---------------------------------------------------------------
 
 const std::string Arch::defaultPlacer = "heap";
diff --git a/machxo2/arch.h b/machxo2/arch.h
index d05346f3cc..a8172b8fac 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -400,6 +400,16 @@ struct ArchArgs
     std::string device;
 };
 
+struct DelayKey
+{
+    IdString celltype, from, to;
+    inline bool operator==(const DelayKey &other) const
+    {
+        return celltype == other.celltype && from == other.from && to == other.to;
+    }
+    unsigned int hash() const { return mkhash(celltype.hash(), mkhash(from.hash(), to.hash())); }
+};
+
 struct ArchRanges : BaseArchRanges
 {
     using ArchArgsT = ArchArgs;
@@ -424,6 +434,7 @@ struct Arch : BaseArch<ArchRanges>
 
     const char *package_name;
     const char *device_name;
+    int device_speed;
 
     mutable dict<IdStringList, PipId> pip_by_name;
 
@@ -725,7 +736,7 @@ struct Arch : BaseArch<ArchRanges>
     virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
     NetInfo *getBoundWireNet(WireId wire) const override { return wire2net.at(get_wire_vecidx(wire)); }
 
-    DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0.01); }
+    DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
 
     WireRange getWires() const override
     {
@@ -863,7 +874,18 @@ struct Arch : BaseArch<ArchRanges>
         return wire;
     }
 
-    DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0.01); }
+    DelayQuad getPipDelay(PipId pip) const override
+    {
+        NPNR_ASSERT(pip != PipId());
+        int fanout = wire_fanout[get_wire_vecidx(getPipSrcWire(pip))];
+        delay_t min_dly =
+                speed_grade->pip_classes[tile_info(pip)->pip_data[pip.index].timing_class].min_base_delay +
+                fanout * speed_grade->pip_classes[tile_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
+        delay_t max_dly =
+                speed_grade->pip_classes[tile_info(pip)->pip_data[pip.index].timing_class].max_base_delay +
+                fanout * speed_grade->pip_classes[tile_info(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
+        return DelayQuad(min_dly, max_dly);
+    }
 
     PipRange getPipsDownhill(WireId wire) const override
     {
@@ -937,10 +959,10 @@ struct Arch : BaseArch<ArchRanges>
     delay_t estimateDelay(WireId src, WireId dst) const override;
     BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
     delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
-    delay_t getDelayEpsilon() const override { return 0.001; }
-    delay_t getRipupDelayPenalty() const override { return 0.015; }
-    float getDelayNS(delay_t v) const override { return v; }
-    delay_t getDelayFromNS(float ns) const override { return ns; }
+    delay_t getDelayEpsilon() const override { return 20; }
+    delay_t getRipupDelayPenalty() const override;
+    float getDelayNS(delay_t v) const override { return v * 0.001; }
+    delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
 
     // -------------------------------------------------
@@ -958,6 +980,20 @@ struct Arch : BaseArch<ArchRanges>
     DecalXY getPipDecal(PipId pip) const override;
     DecalXY getGroupDecal(GroupId group) const override;
 
+    // -------------------------------------------------
+
+    // Get the delay through a cell from one port to another, returning false
+    // if no path exists
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
+    // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
+    // Get the TimingClockingInfo of a port
+    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
+
+    bool get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayQuad &delay) const;
+    void get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayPair &setup,
+                                   DelayPair &hold) const;
+
     // -------------------------------------------------
     // Placement validity checks
     bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
@@ -1005,6 +1041,17 @@ struct Arch : BaseArch<ArchRanges>
     // Apply LPF constraints to the context
     bool apply_lpf(std::string filename, std::istream &in);
 
+    // Special case for delay estimates due to its physical location
+    // being far from the logical location of its primitive
+    WireId gsrclk_wire;
+    // Improves directivity of routing to DSP inputs, avoids issues
+    // with different routes to the same physical reset wire causing
+    // conflicts and slow routing
+    dict<WireId, std::pair<int, int>> wire_loc_overrides;
+    void setup_wire_locations();
+
+    mutable dict<DelayKey, std::pair<bool, DelayQuad>> celldelay_cache;
+
     // Global clock routing
     void route_globals();
 
diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
index 97f7226fea..5a5f80cb54 100644
--- a/machxo2/arch_place.cc
+++ b/machxo2/arch_place.cc
@@ -190,4 +190,36 @@ bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
     return true;
 }
 
+void Arch::setup_wire_locations()
+{
+    wire_loc_overrides.clear();
+    for (auto &cell : cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->bel == BelId())
+            continue;
+        if (ci->type.in(/*id_ALU54B, id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM,*/ id_EHXPLLJ)) {
+            for (auto &port : ci->ports) {
+                if (port.second.net == nullptr)
+                    continue;
+                WireId pw = getBelPinWire(ci->bel, port.first);
+                if (pw == WireId())
+                    continue;
+                if (port.second.type == PORT_OUT) {
+                    for (auto dh : getPipsDownhill(pw)) {
+                        WireId pip_dst = getPipDstWire(dh);
+                        wire_loc_overrides[pw] = std::make_pair(pip_dst.location.x, pip_dst.location.y);
+                        break;
+                    }
+                } else {
+                    for (auto uh : getPipsUphill(pw)) {
+                        WireId pip_src = getPipSrcWire(uh);
+                        wire_loc_overrides[pw] = std::make_pair(pip_src.location.x, pip_src.location.y);
+                        break;
+                    }
+                }
+            }
+        }
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index d3be47231c..a9de6bee84 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1120,6 +1120,7 @@ class MachXO2Packer
                     if (ctx->getBelType(bel) != id_GSR)
                         continue;
                     ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
+                    ctx->gsrclk_wire = ctx->getBelPinWire(bel, id_CLK);
                 }
             } else if (ci->type.in(id_TSALL)) {
                 ci->renamePort(id_TSALL, id_TSALLI);

From 657d2898cfdcb1a62c585300cf12bd66f34dc760 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 21 Sep 2023 15:21:46 +0200
Subject: [PATCH 488/712] import proper data where possible

---
 machxo2/facade_import.py | 46 ++++++++++++++++++++--------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index b33d3b05fe..1f28910998 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -227,10 +227,10 @@ def process_pio_db(rg, device):
 pip_class_to_idx = {"default": 0, "zero": 1}
 
 timing_port_xform = {
-    "RAD0": "D0",
+    "RAD0": "A0",
     "RAD1": "B0",
     "RAD2": "C0",
-    "RAD3": "A0",
+    "RAD3": "D0",
 }
 
 
@@ -246,15 +246,15 @@ def delay_diff(x, y):
     comb_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
     comb_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
     comb_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
-    #comb_delays[("A", "OFX")] = delay_db["SLICE"][("A0", "OFX0")]
-    #comb_delays[("B", "OFX")] = delay_db["SLICE"][("B0", "OFX0")]
-    #comb_delays[("C", "OFX")] = delay_db["SLICE"][("C0", "OFX0")]
-    #comb_delays[("D", "OFX")] = delay_db["SLICE"][("D0", "OFX0")]
-    #comb_delays[("M", "OFX")] = delay_db["SLICE"][("M0", "OFX0")] # worst case
-    #comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLICE"][("A1", "OFX0")],
-    #                                        delay_db["SLICE"][("A1", "F1")])
-    #comb_delays[("FXA", "OFX")] = delay_db["SLICE"][("FXA", "OFX1")]
-    #comb_delays[("FXB", "OFX")] = delay_db["SLICE"][("FXB", "OFX1")]
+    comb_delays[("A", "OFX")] = delay_db["SLICE"][("A0", "OFX0")]
+    comb_delays[("B", "OFX")] = delay_db["SLICE"][("B0", "OFX0")]
+    comb_delays[("C", "OFX")] = delay_db["SLICE"][("C0", "OFX0")]
+    comb_delays[("D", "OFX")] = delay_db["SLICE"][("D0", "OFX0")]
+    comb_delays[("M", "OFX")] = delay_db["SLICE"][("M0", "OFX0")] # worst case
+    comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLICE"][("A1", "OFX0")],
+                                            delay_db["SLICE"][("A1", "F1")])
+    comb_delays[("FXA", "OFX")] = delay_db["SLICE"][("FXA", "OFX1")]
+    comb_delays[("FXB", "OFX")] = delay_db["SLICE"][("FXB", "OFX1")]
     split_cells["TRELLIS_COMB"] = comb_delays
 
     carry0_delays = {}
@@ -262,12 +262,12 @@ def delay_diff(x, y):
     carry0_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
     carry0_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
     carry0_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
-    #carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
-    #carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
-    #carry0_delays[("C", "FCO")] = delay_db["SLICE"][("C0", "FCO")]
-    #carry0_delays[("D", "FCO")] = delay_db["SLICE"][("D0", "FCO")]
-    #carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
-    #carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
+    carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
+    carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
+    carry0_delays[("C", "FCO")] = delay_db["SLICE"][("A0", "FCO")] # missing
+    carry0_delays[("D", "FCO")] = delay_db["SLICE"][("A0", "FCO")] # missing
+    carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
+    carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
 
     split_cells["TRELLIS_COMB_CARRY0"] = carry0_delays
 
@@ -276,12 +276,12 @@ def delay_diff(x, y):
     carry1_delays[("B", "F")] = delay_db["SLICE"][("B1", "F1")]
     carry1_delays[("C", "F")] = delay_db["SLICE"][("C1", "F1")]
     carry1_delays[("D", "F")] = delay_db["SLICE"][("D1", "F1")]
-    #carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
-    #carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
-    #carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
-    #carry1_delays[("D", "FCO")] = delay_db["SLICE"][("D1", "FCO")]
-    #carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
-    #carry1_delays[("FCI", "FCO")] = (0, 0)
+    carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
+    carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
+    carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
+    carry1_delays[("D", "FCO")] = delay_db["SLICE"][("C1", "FCO")] # missing
+    carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
+    carry1_delays[("FCI", "FCO")] = (0, 0)
 
     split_cells["TRELLIS_COMB_CARRY1"] = carry1_delays
 

From 72546a218649f249058381ba3c0837ce2caaba57 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Sep 2023 09:42:14 +0200
Subject: [PATCH 489/712] made delay_t int type

---
 machxo2/archdefs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
index 0152b7ac01..3a4ed21e95 100644
--- a/machxo2/archdefs.h
+++ b/machxo2/archdefs.h
@@ -28,7 +28,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-typedef float delay_t;
+typedef int delay_t;
 
 // -----------------------------------------------------------------------
 

From ed7064b2108230b49a893252466824a93ba059b0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Sep 2023 10:50:32 +0200
Subject: [PATCH 490/712] select proper signal

---
 machxo2/facade_import.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index 1f28910998..ac4ea96aae 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -358,7 +358,8 @@ def get_pip_class(wire_from, wire_to):
         return pip_class_to_idx["zero"]
     if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
         return pip_class_to_idx["zero"]
-
+    if "JCLK" in wire_from:
+        wire_from = wire_from.replace("JCLK","CLK")
     class_name = pip_classes.get_pip_class(wire_from, wire_to)
     if class_name is None or class_name not in pip_class_to_idx:
         class_name = "default"

From 1a92c83c3a2f203c857c97bc3a937b5f9471e921 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Sep 2023 11:25:08 +0200
Subject: [PATCH 491/712] properly assign latest fuzzed data

---
 machxo2/facade_import.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py
index ac4ea96aae..27f3af13ae 100644
--- a/machxo2/facade_import.py
+++ b/machxo2/facade_import.py
@@ -264,8 +264,8 @@ def delay_diff(x, y):
     carry0_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
     carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
     carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
-    carry0_delays[("C", "FCO")] = delay_db["SLICE"][("A0", "FCO")] # missing
-    carry0_delays[("D", "FCO")] = delay_db["SLICE"][("A0", "FCO")] # missing
+    carry0_delays[("C", "FCO")] = delay_db["SLICE"][("C0", "FCO")]
+    carry0_delays[("D", "FCO")] = delay_db["SLICE"][("D0", "FCO")]
     carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
     carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
 
@@ -279,7 +279,7 @@ def delay_diff(x, y):
     carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
     carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
     carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
-    carry1_delays[("D", "FCO")] = delay_db["SLICE"][("C1", "FCO")] # missing
+    carry1_delays[("D", "FCO")] = delay_db["SLICE"][("D1", "FCO")]
     carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
     carry1_delays[("FCI", "FCO")] = (0, 0)
 

From 1811c71438378a9ec3b927c411d1182bb9d75eea Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 28 Sep 2023 13:14:06 +0200
Subject: [PATCH 492/712] update trellis version

---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index ca97889957..63f7e4fa86 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -15,7 +15,7 @@ jobs:
       DEPS_PATH: ${{ github.workspace }}/deps
       YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
-      TRELLIS_REVISION: f1e5710099313d2e1862d4ef2582293f6b7ee122
+      TRELLIS_REVISION: 36c615d1740473cc3574464c7f0bed44da20e5b6
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.8.2a1

From c2e7d3d6112f560612bb4fac263e7da6d49f07a6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 28 Sep 2023 14:10:27 +0200
Subject: [PATCH 493/712] remove commented sections

---
 machxo2/arch.cc | 94 ++-----------------------------------------------
 1 file changed, 2 insertions(+), 92 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6477c49b1f..27abad5c8e 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -706,8 +706,6 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         return false;
     } else if (cell->type == id_DP8KC) {
         return false;
-/*    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
-        return false;*/
     } else {
         return false;
     }
@@ -765,12 +763,6 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         if (port == id_CLKO)
             return TMG_COMB_OUTPUT;
         return TMG_IGNORE;
-/*    } else if (cell->type == id_DCSC) {
-        if (port.in(id_CLK0, id_CLK1))
-            return TMG_COMB_INPUT;
-        if (port == id_DCSOUT)
-            return TMG_COMB_OUTPUT;
-        return TMG_IGNORE;*/
     } else if (cell->type == id_DP8KC) {
         if (port.in(id_CLKA, id_CLKB))
             return TMG_CLOCK_INPUT;
@@ -787,25 +779,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
     } else if (cell->type == id_EHXPLLJ) {
         return TMG_IGNORE;
-/*    } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
-        if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
-            return TMG_CLOCK_INPUT;
-        std::string prefix = port.str(this).substr(0, 9);
-        if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
-            clockInfoCount = 1;
-            return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
-        }
-        return TMG_IGNORE;
-    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
-        if (port.in(id_CLK, id_ECLK)) {
-            return TMG_CLOCK_INPUT;
-        } else if (port.in(id_IOLDO, id_IOLDOI, id_IOLDOD, id_IOLTO, id_PADDI, id_DQSR90, id_DQSW, id_DQSW270)) {
-            return TMG_IGNORE;
-        } else {
-            clockInfoCount = 1;
-            return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
-        }*/
-    } else if (cell->type.in(/*id_DTR, id_USRMCLK,*/ id_SEDFA, id_GSR, id_JTAGF)) {
+    } else if (cell->type.in(id_SEDFA, id_GSR, id_JTAGF)) {
         return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
     } else if (cell->type.in(id_OSCH,id_OSCJ)) {
         if (port == id_OSC)
@@ -821,34 +795,6 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_GEN_CLOCK;
         else
             NPNR_ASSERT_FALSE("bad clkdiv port");
-/*    } else if (cell->type == id_DQSBUFM) {
-        if (port.in(id_READ0, id_READ1)) {
-            clockInfoCount = 1;
-            return TMG_REGISTER_INPUT;
-        } else if (port == id_DATAVALID) {
-            clockInfoCount = 1;
-            return TMG_REGISTER_OUTPUT;
-        } else if (port.in(id_SCLK, id_ECLK, id_DQSI)) {
-            return TMG_CLOCK_INPUT;
-        } else if (port.in(id_DQSR90, id_DQSW, id_DQSW270)) {
-            return TMG_GEN_CLOCK;
-        }
-        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
-    } else if (cell->type == id_DDRDLL) {
-        if (port == id_CLK)
-            return TMG_CLOCK_INPUT;
-        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
-    } else if (cell->type == id_TRELLIS_ECLKBUF) {
-        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
-    } else if (cell->type == id_ECLKSYNCB) {
-        if (cell->ports.at(port).name == id_STOP)
-            return TMG_ENDPOINT;
-        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
-    } else if (cell->type == id_ECLKBRIDGECS) {
-        if (cell->ports.at(port).name == id_SEL)
-            return TMG_ENDPOINT;
-        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
-*/
     } else {
         log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
                   cell->name.c_str(this));
@@ -922,43 +868,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         } else {
             get_setuphold_from_tmg_db(cell->ramInfo.regmode_timing_id, half_clock, port, info.setup, info.hold);
         }
-/*    } else if (cell->type == id_DCUA) {
-        std::string prefix = port.str(this).substr(0, 9);
-        info.edge = RISING_EDGE;
-        if (prefix == "CH0_FF_TX")
-            info.clock_port = id_CH0_FF_TXI_CLK;
-        else if (prefix == "CH0_FF_RX")
-            info.clock_port = id_CH0_FF_RXI_CLK;
-        else if (prefix == "CH1_FF_TX")
-            info.clock_port = id_CH1_FF_TXI_CLK;
-        else if (prefix == "CH1_FF_RX")
-            info.clock_port = id_CH1_FF_RXI_CLK;
-        if (cell->ports.at(port).type == PORT_OUT) {
-            info.clockToQ = DelayQuad(getDelayFromNS(0.7));
-        } else {
-            info.setup = DelayPair(getDelayFromNS(1));
-            info.hold = DelayPair(getDelayFromNS(0));
-        }
-    } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) {
-        info.clock_port = id_CLK;
-        info.edge = RISING_EDGE;
-        if (cell->ports.at(port).type == PORT_OUT) {
-            info.clockToQ = DelayQuad(getDelayFromNS(0.5));
-        } else {
-            info.setup = DelayPair(getDelayFromNS(0.1));
-            info.hold = DelayPair(getDelayFromNS(0));
-        }
-    } else if (cell->type == id_DQSBUFM) {
-        info.clock_port = id_SCLK;
-        info.edge = RISING_EDGE;
-        if (port == id_DATAVALID) {
-            info.clockToQ = DelayQuad(getDelayFromNS(0.2));
-        } else if (port.in(id_READ0, id_READ1)) {
-            info.setup = DelayPair(getDelayFromNS(0.5));
-            info.hold = DelayPair(getDelayFromNS(-0.4));
-        } else {
-            NPNR_ASSERT_FALSE("unknown DQSBUFM register port");*/
-        }
+    }
     return info;
 }
 

From f0325730a8543ee98123117192c4680cd0a9b41d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 28 Sep 2023 14:16:34 +0200
Subject: [PATCH 494/712] made higher estimate and use proper speed

---
 machxo2/arch.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 27abad5c8e..17d56f96f3 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -70,7 +70,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
                             *package_info = nullptr;
                             *package_name = pkg.name.get();
                             *device_name = chip.name.get();
-                            *device_speed = speedgrade.index;
+                            *device_speed = speedgrade.speed;
                             *speed_grade = &(db_ptr->get()->speed_grades[speedgrade.index]);
                             for (auto &pi : db_ptr->get()->package_info) {
                                 if (pkg.name.get() == pi.name.get()) {
@@ -404,7 +404,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
 
     int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
 
-    return (120 - 22 * device_speed) *
+    return (500 - 22 * device_speed) *
            (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
@@ -482,7 +482,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
     int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
 
-    return (120 - 22 * device_speed) *
+    return (500 - 22 * device_speed) *
            (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 

From e4cb7ea337901b541a8d58232a9b5c97cd0dc19a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 2 Oct 2023 09:28:36 +0200
Subject: [PATCH 495/712] proper clock calc due after funcion change

---
 machxo2/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index a9de6bee84..8877ca321c 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1345,7 +1345,7 @@ class MachXO2Packer
                     for (int i = 0; i < 64; i++) {
                         if (osc_freq[i] == freq) {
                             found = true;
-                            set_constraint(ci, id_OSC, simple_clk_contraint(delay_t(1000.0 / std::stof(freq))));
+                            set_constraint(ci, id_OSC, simple_clk_contraint(delay_t(1.0e6 / std::stof(freq))));
                             break;
                         }
                     }

From 95e7598cc68a3c257ed318daa663306e067551ea Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 2 Oct 2023 10:47:59 +0200
Subject: [PATCH 496/712] Fix timing lookup for DP8KC

---
 machxo2/pack.cc | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 8877ca321c..51c0dae1df 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -1742,6 +1742,17 @@ void Arch::assign_arch_info_for_cell(CellInfo *ci)
             log_error("DP8KC %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this), regmode_b.c_str());
         ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
         ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
+
+        // Based on the REGMODE, we have different timing lookup tables.
+        if (!ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP8KC_REGMODE_A_NOREG_REGMODE_B_NOREG;
+        } else if (!ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP8KC_REGMODE_A_NOREG_REGMODE_B_OUTREG;
+        } else if (ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP8KC_REGMODE_A_OUTREG_REGMODE_B_NOREG;
+        } else if (ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
+            ci->ramInfo.regmode_timing_id = id_DP8KC_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
+        }
     }
 }
 

From 0eb9a9ad02c9427b27b496989f85dc24a4ab1191 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 25 Jan 2023 11:03:06 +0100
Subject: [PATCH 497/712] placer_static: Initial prototype

Signed-off-by: gatecat <gatecat@ds0.me>
---
 3rdparty/oourafft/fftsg.cc        | 3305 +++++++++++++++++++++++++++++
 3rdparty/oourafft/fftsg.h         |   24 +
 3rdparty/oourafft/fftsg2d.cc      | 1419 +++++++++++++
 3rdparty/oourafft/readme.txt      |  167 ++
 3rdparty/oourafft/readme2d.txt    |   77 +
 CMakeLists.txt                    |    5 +-
 common/kernel/array2d.h           |  148 ++
 common/kernel/deterministic_rng.h |    2 +
 common/place/placer_static.cc     | 1296 +++++++++++
 common/place/placer_static.h      |   70 +
 common/place/static_util.h        |  142 ++
 ecp5/arch.cc                      |   51 +-
 12 files changed, 6703 insertions(+), 3 deletions(-)
 create mode 100644 3rdparty/oourafft/fftsg.cc
 create mode 100644 3rdparty/oourafft/fftsg.h
 create mode 100644 3rdparty/oourafft/fftsg2d.cc
 create mode 100644 3rdparty/oourafft/readme.txt
 create mode 100644 3rdparty/oourafft/readme2d.txt
 create mode 100644 common/kernel/array2d.h
 create mode 100644 common/place/placer_static.cc
 create mode 100644 common/place/placer_static.h
 create mode 100644 common/place/static_util.h

diff --git a/3rdparty/oourafft/fftsg.cc b/3rdparty/oourafft/fftsg.cc
new file mode 100644
index 0000000000..d74fbb15a0
--- /dev/null
+++ b/3rdparty/oourafft/fftsg.cc
@@ -0,0 +1,3305 @@
+///////////////////////////////////////////////////////////////////////////////
+// BSD 3-Clause License
+//
+// Copyright (c) 2018-2020, The Regents of the University of California
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of source code must retain the above copyright notice, this
+//   list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+//
+// * Neither the name of the copyright holder nor the names of its
+//   contributors may be used to endorse or promote products derived from
+//   this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+///////////////////////////////////////////////////////////////////////////////
+
+/*
+Fast Fourier/Cosine/Sine Transform
+    dimension   :one
+    data length :power of 2
+    decimation  :frequency
+    radix       :split-radix
+    data        :inplace
+    table       :use
+functions
+    cdft: Complex Discrete Fourier Transform
+    rdft: Real Discrete Fourier Transform
+    ddct: Discrete Cosine Transform
+    ddst: Discrete Sine Transform
+    dfct: Cosine Transform of RDFT (Real Symmetric DFT)
+    dfst: Sine Transform of RDFT (Real Anti-symmetric DFT)
+function prototypes
+    void cdft(int, int, float   *, int *, float   *);
+    void rdft(int, int, float   *, int *, float   *);
+    void ddct(int, int, float   *, int *, float   *);
+    void ddst(int, int, float   *, int *, float   *);
+    void dfct(int, float   *, float   *, int *, float   *);
+    void dfst(int, float   *, float   *, int *, float   *);
+macro definitions
+    USE_CDFT_PTHREADS : default=not defined
+        CDFT_THREADS_BEGIN_N  : must be >= 512, default=8192
+        CDFT_4THREADS_BEGIN_N : must be >= 512, default=65536
+    USE_CDFT_WINTHREADS : default=not defined
+        CDFT_THREADS_BEGIN_N  : must be >= 512, default=32768
+        CDFT_4THREADS_BEGIN_N : must be >= 512, default=524288
+
+
+-------- Complex DFT (Discrete Fourier Transform) --------
+    [definition]
+        <case1>
+            X[k] = sum_j=0^n-1 x[j]*exp(2*pi*i*j*k/n), 0<=k<n
+        <case2>
+            X[k] = sum_j=0^n-1 x[j]*exp(-2*pi*i*j*k/n), 0<=k<n
+        (notes: sum_j=0^n-1 is a summation from j=0 to n-1)
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            cdft(2*n, 1, a, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            cdft(2*n, -1, a, ip, w);
+    [parameters]
+        2*n            :data length (int)
+                        n >= 1, n = power of 2
+        a[0...2*n-1]   :input/output data (float   *)
+                        input data
+                            a[2*j] = Re(x[j]),
+                            a[2*j+1] = Im(x[j]), 0<=j<n
+                        output data
+                            a[2*k] = Re(X[k]),
+                            a[2*k+1] = Im(X[k]), 0<=k<n
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n/2-1]   :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            cdft(2*n, -1, a, ip, w);
+        is
+            cdft(2*n, 1, a, ip, w);
+            for (j = 0; j <= 2 * n - 1; j++) {
+                a[j] *= 1.0 / n;
+            }
+        .
+
+
+-------- Real DFT / Inverse of Real DFT --------
+    [definition]
+        <case1> RDFT
+            R[k] = sum_j=0^n-1 a[j]*cos(2*pi*j*k/n), 0<=k<=n/2
+            I[k] = sum_j=0^n-1 a[j]*sin(2*pi*j*k/n), 0<k<n/2
+        <case2> IRDFT (excluding scale)
+            a[k] = (R[0] + R[n/2]*cos(pi*k))/2 +
+                   sum_j=1^n/2-1 R[j]*cos(2*pi*j*k/n) +
+                   sum_j=1^n/2-1 I[j]*sin(2*pi*j*k/n), 0<=k<n
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            rdft(n, 1, a, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            rdft(n, -1, a, ip, w);
+    [parameters]
+        n              :data length (int)
+                        n >= 2, n = power of 2
+        a[0...n-1]     :input/output data (float   *)
+                        <case1>
+                            output data
+                                a[2*k] = R[k], 0<=k<n/2
+                                a[2*k+1] = I[k], 0<k<n/2
+                                a[1] = R[n/2]
+                        <case2>
+                            input data
+                                a[2*j] = R[j], 0<=j<n/2
+                                a[2*j+1] = I[j], 0<j<n/2
+                                a[1] = R[n/2]
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n/2)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n/2+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n/2-1]   :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            rdft(n, 1, a, ip, w);
+        is
+            rdft(n, -1, a, ip, w);
+            for (j = 0; j <= n - 1; j++) {
+                a[j] *= 2.0 / n;
+            }
+        .
+
+
+-------- DCT (Discrete Cosine Transform) / Inverse of DCT --------
+    [definition]
+        <case1> IDCT (excluding scale)
+            C[k] = sum_j=0^n-1 a[j]*cos(pi*j*(k+1/2)/n), 0<=k<n
+        <case2> DCT
+            C[k] = sum_j=0^n-1 a[j]*cos(pi*(j+1/2)*k/n), 0<=k<n
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            ddct(n, 1, a, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            ddct(n, -1, a, ip, w);
+    [parameters]
+        n              :data length (int)
+                        n >= 2, n = power of 2
+        a[0...n-1]     :input/output data (float   *)
+                        output data
+                            a[k] = C[k], 0<=k<n
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n/2)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n/2+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n*5/4-1] :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            ddct(n, -1, a, ip, w);
+        is
+            a[0] *= 0.5;
+            ddct(n, 1, a, ip, w);
+            for (j = 0; j <= n - 1; j++) {
+                a[j] *= 2.0 / n;
+            }
+        .
+
+
+-------- DST (Discrete Sine Transform) / Inverse of DST --------
+    [definition]
+        <case1> IDST (excluding scale)
+            S[k] = sum_j=1^n A[j]*sin(pi*j*(k+1/2)/n), 0<=k<n
+        <case2> DST
+            S[k] = sum_j=0^n-1 a[j]*sin(pi*(j+1/2)*k/n), 0<k<=n
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            ddst(n, 1, a, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            ddst(n, -1, a, ip, w);
+    [parameters]
+        n              :data length (int)
+                        n >= 2, n = power of 2
+        a[0...n-1]     :input/output data (float   *)
+                        <case1>
+                            input data
+                                a[j] = A[j], 0<j<n
+                                a[0] = A[n]
+                            output data
+                                a[k] = S[k], 0<=k<n
+                        <case2>
+                            output data
+                                a[k] = S[k], 0<k<n
+                                a[0] = S[n]
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n/2)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n/2+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n*5/4-1] :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            ddst(n, -1, a, ip, w);
+        is
+            a[0] *= 0.5;
+            ddst(n, 1, a, ip, w);
+            for (j = 0; j <= n - 1; j++) {
+                a[j] *= 2.0 / n;
+            }
+        .
+
+
+-------- Cosine Transform of RDFT (Real Symmetric DFT) --------
+    [definition]
+        C[k] = sum_j=0^n a[j]*cos(pi*j*k/n), 0<=k<=n
+    [usage]
+        ip[0] = 0; // first time only
+        dfct(n, a, t, ip, w);
+    [parameters]
+        n              :data length - 1 (int)
+                        n >= 2, n = power of 2
+        a[0...n]       :input/output data (float   *)
+                        output data
+                            a[k] = C[k], 0<=k<=n
+        t[0...n/2]     :work area (float   *)
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n/4)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n/4+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n*5/8-1] :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            a[0] *= 0.5;
+            a[n] *= 0.5;
+            dfct(n, a, t, ip, w);
+        is
+            a[0] *= 0.5;
+            a[n] *= 0.5;
+            dfct(n, a, t, ip, w);
+            for (j = 0; j <= n; j++) {
+                a[j] *= 2.0 / n;
+            }
+        .
+
+
+-------- Sine Transform of RDFT (Real Anti-symmetric DFT) --------
+    [definition]
+        S[k] = sum_j=1^n-1 a[j]*sin(pi*j*k/n), 0<k<n
+    [usage]
+        ip[0] = 0; // first time only
+        dfst(n, a, t, ip, w);
+    [parameters]
+        n              :data length + 1 (int)
+                        n >= 2, n = power of 2
+        a[0...n-1]     :input/output data (float   *)
+                        output data
+                            a[k] = S[k], 0<k<n
+                        (a[0] is used for work area)
+        t[0...n/2-1]   :work area (float   *)
+        ip[0...*]      :work area for bit reversal (int *)
+                        length of ip >= 2+sqrt(n/4)
+                        strictly,
+                        length of ip >=
+                            2+(1<<(int)(log(n/4+0.5)/log(2))/2).
+                        ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...n*5/8-1] :cos/sin table (float   *)
+                        w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            dfst(n, a, t, ip, w);
+        is
+            dfst(n, a, t, ip, w);
+            for (j = 1; j <= n - 1; j++) {
+                a[j] *= 2.0 / n;
+            }
+        .
+
+
+Appendix :
+    The cos/sin table is recalculated when the larger table required.
+    w[] and ip[] are compatible with all routines.
+*/
+
+#include <cmath>
+#include <iostream>
+
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void cdft(int n, int isgn, float* a, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void cftbsub(int n, float* a, int* ip, int nw, float* w);
+  int nw;
+
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  if (isgn >= 0) {
+    cftfsub(n, a, ip, nw, w);
+  } else {
+    cftbsub(n, a, ip, nw, w);
+  }
+}
+
+void rdft(int n, int isgn, float* a, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void cftbsub(int n, float* a, int* ip, int nw, float* w);
+  void rftfsub(int n, float* a, int nc, float* c);
+  void rftbsub(int n, float* a, int nc, float* c);
+  int nw, nc;
+  float xi;
+
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > (nc << 2)) {
+    nc = n >> 2;
+    makect(nc, ip, w + nw);
+  }
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a, ip, nw, w);
+      rftfsub(n, a, nc, w + nw);
+    } else if (n == 4) {
+      cftfsub(n, a, ip, nw, w);
+    }
+    xi = a[0] - a[1];
+    a[0] += a[1];
+    a[1] = xi;
+  } else {
+    a[1] = 0.5 * (a[0] - a[1]);
+    a[0] -= a[1];
+    if (n > 4) {
+      rftbsub(n, a, nc, w + nw);
+      cftbsub(n, a, ip, nw, w);
+    } else if (n == 4) {
+      cftbsub(n, a, ip, nw, w);
+    }
+  }
+}
+
+void ddct(int n, int isgn, float* a, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void cftbsub(int n, float* a, int* ip, int nw, float* w);
+  void rftfsub(int n, float* a, int nc, float* c);
+  void rftbsub(int n, float* a, int nc, float* c);
+  void dctsub(int n, float* a, int nc, float* c);
+  int j, nw, nc;
+  float xr;
+
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  if (isgn < 0) {
+    xr = a[n - 1];
+
+    for (j = n - 2; j >= 2; j -= 2) {
+      a[j + 1] = a[j] - a[j - 1];
+      a[j] += a[j - 1];
+    }
+    a[1] = a[0] - xr;
+    a[0] += xr;
+    if (n > 4) {
+      rftbsub(n, a, nc, w + nw);
+      cftbsub(n, a, ip, nw, w);
+    } else if (n == 4) {
+      cftbsub(n, a, ip, nw, w);
+    }
+  }
+  dctsub(n, a, nc, w + nw);
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a, ip, nw, w);
+      rftfsub(n, a, nc, w + nw);
+    } else if (n == 4) {
+      cftfsub(n, a, ip, nw, w);
+    }
+    xr = a[0] - a[1];
+    a[0] += a[1];
+    for (j = 2; j < n; j += 2) {
+      a[j - 1] = a[j] - a[j + 1];
+      a[j] += a[j + 1];
+    }
+    a[n - 1] = xr;
+  }
+}
+
+void ddst(int n, int isgn, float* a, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void cftbsub(int n, float* a, int* ip, int nw, float* w);
+  void rftfsub(int n, float* a, int nc, float* c);
+  void rftbsub(int n, float* a, int nc, float* c);
+  void dstsub(int n, float* a, int nc, float* c);
+  int j, nw, nc;
+  float xr;
+
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  if (isgn < 0) {
+    xr = a[n - 1];
+    for (j = n - 2; j >= 2; j -= 2) {
+      a[j + 1] = -a[j] - a[j - 1];
+      a[j] -= a[j - 1];
+    }
+    a[1] = a[0] + xr;
+    a[0] -= xr;
+    if (n > 4) {
+      rftbsub(n, a, nc, w + nw);
+      cftbsub(n, a, ip, nw, w);
+    } else if (n == 4) {
+      cftbsub(n, a, ip, nw, w);
+    }
+  }
+  dstsub(n, a, nc, w + nw);
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a, ip, nw, w);
+      rftfsub(n, a, nc, w + nw);
+    } else if (n == 4) {
+      cftfsub(n, a, ip, nw, w);
+    }
+    xr = a[0] - a[1];
+    a[0] += a[1];
+    for (j = 2; j < n; j += 2) {
+      a[j - 1] = -a[j] - a[j + 1];
+      a[j] -= a[j + 1];
+    }
+    a[n - 1] = -xr;
+  }
+}
+
+void dfct(int n, float* a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void rftfsub(int n, float* a, int nc, float* c);
+  void dctsub(int n, float* a, int nc, float* c);
+  int j, k, l, m, mh, nw, nc;
+  float xr, xi, yr, yi;
+
+  nw = ip[0];
+  if (n > (nw << 3)) {
+    nw = n >> 3;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > (nc << 1)) {
+    nc = n >> 1;
+    makect(nc, ip, w + nw);
+  }
+  m = n >> 1;
+  yi = a[m];
+  xi = a[0] + a[n];
+  a[0] -= a[n];
+  t[0] = xi - yi;
+  t[m] = xi + yi;
+  if (n > 2) {
+    mh = m >> 1;
+    for (j = 1; j < mh; j++) {
+      k = m - j;
+      xr = a[j] - a[n - j];
+      xi = a[j] + a[n - j];
+      yr = a[k] - a[n - k];
+      yi = a[k] + a[n - k];
+      a[j] = xr;
+      a[k] = yr;
+      t[j] = xi - yi;
+      t[k] = xi + yi;
+    }
+    t[mh] = a[mh] + a[n - mh];
+    a[mh] -= a[n - mh];
+    dctsub(m, a, nc, w + nw);
+    if (m > 4) {
+      cftfsub(m, a, ip, nw, w);
+      rftfsub(m, a, nc, w + nw);
+    } else if (m == 4) {
+      cftfsub(m, a, ip, nw, w);
+    }
+    a[n - 1] = a[0] - a[1];
+    a[1] = a[0] + a[1];
+    for (j = m - 2; j >= 2; j -= 2) {
+      a[2 * j + 1] = a[j] + a[j + 1];
+      a[2 * j - 1] = a[j] - a[j + 1];
+    }
+    l = 2;
+    m = mh;
+    while (m >= 2) {
+      dctsub(m, t, nc, w + nw);
+      if (m > 4) {
+        cftfsub(m, t, ip, nw, w);
+        rftfsub(m, t, nc, w + nw);
+      } else if (m == 4) {
+        cftfsub(m, t, ip, nw, w);
+      }
+      a[n - l] = t[0] - t[1];
+      a[l] = t[0] + t[1];
+      k = 0;
+      for (j = 2; j < m; j += 2) {
+        k += l << 2;
+        a[k - l] = t[j] - t[j + 1];
+        a[k + l] = t[j] + t[j + 1];
+      }
+      l <<= 1;
+      mh = m >> 1;
+      for (j = 0; j < mh; j++) {
+        k = m - j;
+        t[j] = t[m + k] - t[m + j];
+        t[k] = t[m + k] + t[m + j];
+      }
+      t[mh] = t[m + mh];
+      m = mh;
+    }
+    a[l] = t[0];
+    a[n] = t[2] - t[1];
+    a[0] = t[2] + t[1];
+  } else {
+    a[1] = a[0];
+    a[2] = t[0];
+    a[0] = t[1];
+  }
+}
+
+void dfst(int n, float* a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void cftfsub(int n, float* a, int* ip, int nw, float* w);
+  void rftfsub(int n, float* a, int nc, float* c);
+  void dstsub(int n, float* a, int nc, float* c);
+  int j, k, l, m, mh, nw, nc;
+  float xr, xi, yr, yi;
+
+  nw = ip[0];
+  if (n > (nw << 3)) {
+    nw = n >> 3;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > (nc << 1)) {
+    nc = n >> 1;
+    makect(nc, ip, w + nw);
+  }
+  if (n > 2) {
+    m = n >> 1;
+    mh = m >> 1;
+    for (j = 1; j < mh; j++) {
+      k = m - j;
+      xr = a[j] + a[n - j];
+      xi = a[j] - a[n - j];
+      yr = a[k] + a[n - k];
+      yi = a[k] - a[n - k];
+      a[j] = xr;
+      a[k] = yr;
+      t[j] = xi + yi;
+      t[k] = xi - yi;
+    }
+    t[0] = a[mh] - a[n - mh];
+    a[mh] += a[n - mh];
+    a[0] = a[m];
+    dstsub(m, a, nc, w + nw);
+    if (m > 4) {
+      cftfsub(m, a, ip, nw, w);
+      rftfsub(m, a, nc, w + nw);
+    } else if (m == 4) {
+      cftfsub(m, a, ip, nw, w);
+    }
+    a[n - 1] = a[1] - a[0];
+    a[1] = a[0] + a[1];
+    for (j = m - 2; j >= 2; j -= 2) {
+      a[2 * j + 1] = a[j] - a[j + 1];
+      a[2 * j - 1] = -a[j] - a[j + 1];
+    }
+    l = 2;
+    m = mh;
+    while (m >= 2) {
+      dstsub(m, t, nc, w + nw);
+      if (m > 4) {
+        cftfsub(m, t, ip, nw, w);
+        rftfsub(m, t, nc, w + nw);
+      } else if (m == 4) {
+        cftfsub(m, t, ip, nw, w);
+      }
+      a[n - l] = t[1] - t[0];
+      a[l] = t[0] + t[1];
+      k = 0;
+      for (j = 2; j < m; j += 2) {
+        k += l << 2;
+        a[k - l] = -t[j] - t[j + 1];
+        a[k + l] = t[j] - t[j + 1];
+      }
+      l <<= 1;
+      mh = m >> 1;
+      for (j = 1; j < mh; j++) {
+        k = m - j;
+        t[j] = t[m + k] + t[m + j];
+        t[k] = t[m + k] - t[m + j];
+      }
+      t[0] = t[m + mh];
+      m = mh;
+    }
+    a[l] = t[0];
+  }
+  a[0] = 0;
+}
+
+/* -------- initializing routines -------- */
+
+void makewt(int nw, int* ip, float* w)
+{
+  void makeipt(int nw, int* ip);
+  int j, nwh, nw0, nw1;
+  float delta, wn4r, wk1r, wk1i, wk3r, wk3i;
+
+  ip[0] = nw;
+  ip[1] = 1;
+  if (nw > 2) {
+    nwh = nw >> 1;
+    delta = atan(1.0) / nwh;
+    wn4r = cos(delta * nwh);
+    w[0] = 1;
+    w[1] = wn4r;
+    if (nwh == 4) {
+      w[2] = cos(delta * 2);
+      w[3] = sin(delta * 2);
+    } else if (nwh > 4) {
+      makeipt(nw, ip);
+      w[2] = 0.5 / cos(delta * 2);
+      w[3] = 0.5 / cos(delta * 6);
+      for (j = 4; j < nwh; j += 4) {
+        w[j] = cos(delta * j);
+        w[j + 1] = sin(delta * j);
+        w[j + 2] = cos(3 * delta * j);
+        w[j + 3] = -sin(3 * delta * j);
+      }
+    }
+    nw0 = 0;
+    while (nwh > 2) {
+      nw1 = nw0 + nwh;
+      nwh >>= 1;
+      w[nw1] = 1;
+      w[nw1 + 1] = wn4r;
+      if (nwh == 4) {
+        wk1r = w[nw0 + 4];
+        wk1i = w[nw0 + 5];
+        w[nw1 + 2] = wk1r;
+        w[nw1 + 3] = wk1i;
+      } else if (nwh > 4) {
+        wk1r = w[nw0 + 4];
+        wk3r = w[nw0 + 6];
+        w[nw1 + 2] = 0.5 / wk1r;
+        w[nw1 + 3] = 0.5 / wk3r;
+        for (j = 4; j < nwh; j += 4) {
+          wk1r = w[nw0 + 2 * j];
+          wk1i = w[nw0 + 2 * j + 1];
+          wk3r = w[nw0 + 2 * j + 2];
+          wk3i = w[nw0 + 2 * j + 3];
+          w[nw1 + j] = wk1r;
+          w[nw1 + j + 1] = wk1i;
+          w[nw1 + j + 2] = wk3r;
+          w[nw1 + j + 3] = wk3i;
+        }
+      }
+      nw0 = nw1;
+    }
+  }
+}
+
+void makeipt(int nw, int* ip)
+{
+  int j, l, m, m2, p, q;
+
+  ip[2] = 0;
+  ip[3] = 16;
+  m = 2;
+  for (l = nw; l > 32; l >>= 2) {
+    m2 = m << 1;
+    q = m2 << 3;
+    for (j = m; j < m2; j++) {
+      p = ip[j] << 2;
+      ip[m + j] = p;
+      ip[m2 + j] = p + q;
+    }
+    m = m2;
+  }
+}
+
+void makect(int nc, int* ip, float* c)
+{
+  int j, nch;
+  float delta;
+
+  ip[1] = nc;
+  if (nc > 1) {
+    nch = nc >> 1;
+    delta = atan(1.0) / nch;
+    c[0] = cos(delta * nch);
+    c[nch] = 0.5 * c[0];
+    for (j = 1; j < nch; j++) {
+      c[j] = 0.5 * cos(delta * j);
+      c[nc - j] = 0.5 * sin(delta * j);
+    }
+  }
+}
+
+/* -------- child routines -------- */
+
+#ifdef USE_CDFT_PTHREADS
+#define USE_CDFT_THREADS
+#ifndef CDFT_THREADS_BEGIN_N
+#define CDFT_THREADS_BEGIN_N 8192
+#endif
+#ifndef CDFT_4THREADS_BEGIN_N
+#define CDFT_4THREADS_BEGIN_N 65536
+#endif
+#include <pthread.h>
+#include <stdio.h>
+#include <stdlib.h>
+#define cdft_thread_t pthread_t
+#define cdft_thread_create(thp, func, argp)                   \
+  {                                                           \
+    if (pthread_create(thp, NULL, func, (void*) argp) != 0) { \
+      fprintf(stderr, "cdft thread error\n");                 \
+      exit(1);                                                \
+    }                                                         \
+  }
+#define cdft_thread_wait(th)                  \
+  {                                           \
+    if (pthread_join(th, NULL) != 0) {        \
+      fprintf(stderr, "cdft thread error\n"); \
+      exit(1);                                \
+    }                                         \
+  }
+#endif /* USE_CDFT_PTHREADS */
+
+#ifdef USE_CDFT_WINTHREADS
+#define USE_CDFT_THREADS
+#ifndef CDFT_THREADS_BEGIN_N
+#define CDFT_THREADS_BEGIN_N 32768
+#endif
+#ifndef CDFT_4THREADS_BEGIN_N
+#define CDFT_4THREADS_BEGIN_N 524288
+#endif
+#include <stdio.h>
+#include <stdlib.h>
+#include <windows.h>
+#define cdft_thread_t HANDLE
+#define cdft_thread_create(thp, func, argp)                               \
+  {                                                                       \
+    DWORD thid;                                                           \
+    *(thp) = CreateThread(                                                \
+        NULL, 0, (LPTHREAD_START_ROUTINE) func, (LPVOID) argp, 0, &thid); \
+    if (*(thp) == 0) {                                                    \
+      fprintf(stderr, "cdft thread error\n");                             \
+      exit(1);                                                            \
+    }                                                                     \
+  }
+#define cdft_thread_wait(th)           \
+  {                                    \
+    WaitForSingleObject(th, INFINITE); \
+    CloseHandle(th);                   \
+  }
+#endif /* USE_CDFT_WINTHREADS */
+
+void cftfsub(int n, float* a, int* ip, int nw, float* w)
+{
+  void bitrv2(int n, int* ip, float* a);
+  void bitrv216(float* a);
+  void bitrv208(float* a);
+  void cftf1st(int n, float* a, float* w);
+  void cftrec4(int n, float* a, int nw, float* w);
+  void cftleaf(int n, int isplt, float* a, int nw, float* w);
+  void cftfx41(int n, float* a, int nw, float* w);
+  void cftf161(float* a, float* w);
+  void cftf081(float* a, float* w);
+  void cftf040(float* a);
+  void cftx020(float* a);
+#ifdef USE_CDFT_THREADS
+  void cftrec4_th(int n, float* a, int nw, float* w);
+#endif /* USE_CDFT_THREADS */
+
+  if (n > 8) {
+    if (n > 32) {
+      cftf1st(n, a, &w[nw - (n >> 2)]);
+#ifdef USE_CDFT_THREADS
+      if (n > CDFT_THREADS_BEGIN_N) {
+        cftrec4_th(n, a, nw, w);
+      } else
+#endif /* USE_CDFT_THREADS */
+        if (n > 512) {
+          cftrec4(n, a, nw, w);
+        } else if (n > 128) {
+          cftleaf(n, 1, a, nw, w);
+        } else {
+          cftfx41(n, a, nw, w);
+        }
+      bitrv2(n, ip, a);
+    } else if (n == 32) {
+      cftf161(a, &w[nw - 8]);
+      bitrv216(a);
+    } else {
+      cftf081(a, w);
+      bitrv208(a);
+    }
+  } else if (n == 8) {
+    cftf040(a);
+  } else if (n == 4) {
+    cftx020(a);
+  }
+}
+
+void cftbsub(int n, float* a, int* ip, int nw, float* w)
+{
+  void bitrv2conj(int n, int* ip, float* a);
+  void bitrv216neg(float* a);
+  void bitrv208neg(float* a);
+  void cftb1st(int n, float* a, float* w);
+  void cftrec4(int n, float* a, int nw, float* w);
+  void cftleaf(int n, int isplt, float* a, int nw, float* w);
+  void cftfx41(int n, float* a, int nw, float* w);
+  void cftf161(float* a, float* w);
+  void cftf081(float* a, float* w);
+  void cftb040(float* a);
+  void cftx020(float* a);
+#ifdef USE_CDFT_THREADS
+  void cftrec4_th(int n, float* a, int nw, float* w);
+#endif /* USE_CDFT_THREADS */
+
+  if (n > 8) {
+    if (n > 32) {
+      cftb1st(n, a, &w[nw - (n >> 2)]);
+#ifdef USE_CDFT_THREADS
+      if (n > CDFT_THREADS_BEGIN_N) {
+        cftrec4_th(n, a, nw, w);
+      } else
+#endif /* USE_CDFT_THREADS */
+        if (n > 512) {
+          cftrec4(n, a, nw, w);
+        } else if (n > 128) {
+          cftleaf(n, 1, a, nw, w);
+        } else {
+          cftfx41(n, a, nw, w);
+        }
+      bitrv2conj(n, ip, a);
+    } else if (n == 32) {
+      cftf161(a, &w[nw - 8]);
+      bitrv216neg(a);
+    } else {
+      cftf081(a, w);
+      bitrv208neg(a);
+    }
+  } else if (n == 8) {
+    cftb040(a);
+  } else if (n == 4) {
+    cftx020(a);
+  }
+}
+
+void bitrv2(int n, int* ip, float* a)
+{
+  int j, j1, k, k1, l, m, nh, nm;
+  float xr, xi, yr, yi;
+
+  m = 1;
+  for (l = n >> 2; l > 8; l >>= 2) {
+    m <<= 1;
+  }
+  nh = n >> 1;
+  nm = 4 * m;
+  if (l == 8) {
+    for (k = 0; k < m; k++) {
+      for (j = 0; j < k; j++) {
+        j1 = 4 * j + 2 * ip[m + k];
+        k1 = 4 * k + 2 * ip[m + j];
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nh;
+        k1 += 2;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += 2;
+        k1 += nh;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nh;
+        k1 -= 2;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+      }
+      k1 = 4 * k + 2 * ip[m + k];
+      j1 = k1 + 2;
+      k1 += nh;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nm;
+      k1 += 2 * nm;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nm;
+      k1 -= nm;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 -= 2;
+      k1 -= nh;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nh + 2;
+      k1 += nh + 2;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 -= nh - nm;
+      k1 += 2 * nm - 2;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+    }
+  } else {
+    for (k = 0; k < m; k++) {
+      for (j = 0; j < k; j++) {
+        j1 = 4 * j + ip[m + k];
+        k1 = 4 * k + ip[m + j];
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nh;
+        k1 += 2;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += 2;
+        k1 += nh;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nh;
+        k1 -= 2;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+      }
+      k1 = 4 * k + ip[m + k];
+      j1 = k1 + 2;
+      k1 += nh;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nm;
+      k1 += nm;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+    }
+  }
+}
+
+void bitrv2conj(int n, int* ip, float* a)
+{
+  int j, j1, k, k1, l, m, nh, nm;
+  float xr, xi, yr, yi;
+
+  m = 1;
+  for (l = n >> 2; l > 8; l >>= 2) {
+    m <<= 1;
+  }
+  nh = n >> 1;
+  nm = 4 * m;
+  if (l == 8) {
+    for (k = 0; k < m; k++) {
+      for (j = 0; j < k; j++) {
+        j1 = 4 * j + 2 * ip[m + k];
+        k1 = 4 * k + 2 * ip[m + j];
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nh;
+        k1 += 2;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += 2;
+        k1 += nh;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nh;
+        k1 -= 2;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= 2 * nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+      }
+      k1 = 4 * k + 2 * ip[m + k];
+      j1 = k1 + 2;
+      k1 += nh;
+      a[j1 - 1] = -a[j1 - 1];
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      a[k1 + 3] = -a[k1 + 3];
+      j1 += nm;
+      k1 += 2 * nm;
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nm;
+      k1 -= nm;
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 -= 2;
+      k1 -= nh;
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 += nh + 2;
+      k1 += nh + 2;
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      j1 -= nh - nm;
+      k1 += 2 * nm - 2;
+      a[j1 - 1] = -a[j1 - 1];
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      a[k1 + 3] = -a[k1 + 3];
+    }
+  } else {
+    for (k = 0; k < m; k++) {
+      for (j = 0; j < k; j++) {
+        j1 = 4 * j + ip[m + k];
+        k1 = 4 * k + ip[m + j];
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nh;
+        k1 += 2;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += 2;
+        k1 += nh;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += nm;
+        k1 += nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nh;
+        k1 -= 2;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 -= nm;
+        k1 -= nm;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+      }
+      k1 = 4 * k + ip[m + k];
+      j1 = k1 + 2;
+      k1 += nh;
+      a[j1 - 1] = -a[j1 - 1];
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      a[k1 + 3] = -a[k1 + 3];
+      j1 += nm;
+      k1 += nm;
+      a[j1 - 1] = -a[j1 - 1];
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      a[k1 + 3] = -a[k1 + 3];
+    }
+  }
+}
+
+void bitrv216(float* a)
+{
+  float x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x7r, x7i, x8r, x8i,
+      x10r, x10i, x11r, x11i, x12r, x12i, x13r, x13i, x14r, x14i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x7r = a[14];
+  x7i = a[15];
+  x8r = a[16];
+  x8i = a[17];
+  x10r = a[20];
+  x10i = a[21];
+  x11r = a[22];
+  x11i = a[23];
+  x12r = a[24];
+  x12i = a[25];
+  x13r = a[26];
+  x13i = a[27];
+  x14r = a[28];
+  x14i = a[29];
+  a[2] = x8r;
+  a[3] = x8i;
+  a[4] = x4r;
+  a[5] = x4i;
+  a[6] = x12r;
+  a[7] = x12i;
+  a[8] = x2r;
+  a[9] = x2i;
+  a[10] = x10r;
+  a[11] = x10i;
+  a[14] = x14r;
+  a[15] = x14i;
+  a[16] = x1r;
+  a[17] = x1i;
+  a[20] = x5r;
+  a[21] = x5i;
+  a[22] = x13r;
+  a[23] = x13i;
+  a[24] = x3r;
+  a[25] = x3i;
+  a[26] = x11r;
+  a[27] = x11i;
+  a[28] = x7r;
+  a[29] = x7i;
+}
+
+void bitrv216neg(float* a)
+{
+  float x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x6r, x6i, x7r, x7i,
+      x8r, x8i, x9r, x9i, x10r, x10i, x11r, x11i, x12r, x12i, x13r, x13i, x14r,
+      x14i, x15r, x15i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x6r = a[12];
+  x6i = a[13];
+  x7r = a[14];
+  x7i = a[15];
+  x8r = a[16];
+  x8i = a[17];
+  x9r = a[18];
+  x9i = a[19];
+  x10r = a[20];
+  x10i = a[21];
+  x11r = a[22];
+  x11i = a[23];
+  x12r = a[24];
+  x12i = a[25];
+  x13r = a[26];
+  x13i = a[27];
+  x14r = a[28];
+  x14i = a[29];
+  x15r = a[30];
+  x15i = a[31];
+  a[2] = x15r;
+  a[3] = x15i;
+  a[4] = x7r;
+  a[5] = x7i;
+  a[6] = x11r;
+  a[7] = x11i;
+  a[8] = x3r;
+  a[9] = x3i;
+  a[10] = x13r;
+  a[11] = x13i;
+  a[12] = x5r;
+  a[13] = x5i;
+  a[14] = x9r;
+  a[15] = x9i;
+  a[16] = x1r;
+  a[17] = x1i;
+  a[18] = x14r;
+  a[19] = x14i;
+  a[20] = x6r;
+  a[21] = x6i;
+  a[22] = x10r;
+  a[23] = x10i;
+  a[24] = x2r;
+  a[25] = x2i;
+  a[26] = x12r;
+  a[27] = x12i;
+  a[28] = x4r;
+  a[29] = x4i;
+  a[30] = x8r;
+  a[31] = x8i;
+}
+
+void bitrv208(float* a)
+{
+  float x1r, x1i, x3r, x3i, x4r, x4i, x6r, x6i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x6r = a[12];
+  x6i = a[13];
+  a[2] = x4r;
+  a[3] = x4i;
+  a[6] = x6r;
+  a[7] = x6i;
+  a[8] = x1r;
+  a[9] = x1i;
+  a[12] = x3r;
+  a[13] = x3i;
+}
+
+void bitrv208neg(float* a)
+{
+  float x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x6r, x6i, x7r, x7i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x6r = a[12];
+  x6i = a[13];
+  x7r = a[14];
+  x7i = a[15];
+  a[2] = x7r;
+  a[3] = x7i;
+  a[4] = x3r;
+  a[5] = x3i;
+  a[6] = x5r;
+  a[7] = x5i;
+  a[8] = x1r;
+  a[9] = x1i;
+  a[10] = x6r;
+  a[11] = x6i;
+  a[12] = x2r;
+  a[13] = x2i;
+  a[14] = x4r;
+  a[15] = x4i;
+}
+
+void cftf1st(int n, float* a, float* w)
+{
+  int j, j0, j1, j2, j3, k, m, mh;
+  float wn4r, csc1, csc3, wk1r, wk1i, wk3r, wk3i, wd1r, wd1i, wd3r, wd3i;
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r, y1i, y2r, y2i,
+      y3r, y3i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] + a[j2];
+  x0i = a[1] + a[j2 + 1];
+  x1r = a[0] - a[j2];
+  x1i = a[1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  a[j2] = x1r - x3i;
+  a[j2 + 1] = x1i + x3r;
+  a[j3] = x1r + x3i;
+  a[j3 + 1] = x1i - x3r;
+  wn4r = w[1];
+  csc1 = w[2];
+  csc3 = w[3];
+  wd1r = 1;
+  wd1i = 0;
+  wd3r = 1;
+  wd3i = 0;
+  k = 0;
+  for (j = 2; j < mh - 2; j += 4) {
+    k += 4;
+    wk1r = csc1 * (wd1r + w[k]);
+    wk1i = csc1 * (wd1i + w[k + 1]);
+    wk3r = csc3 * (wd3r + w[k + 2]);
+    wk3i = csc3 * (wd3i + w[k + 3]);
+    wd1r = w[k];
+    wd1i = w[k + 1];
+    wd3r = w[k + 2];
+    wd3i = w[k + 3];
+    j1 = j + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j] + a[j2];
+    x0i = a[j + 1] + a[j2 + 1];
+    x1r = a[j] - a[j2];
+    x1i = a[j + 1] - a[j2 + 1];
+    y0r = a[j + 2] + a[j2 + 2];
+    y0i = a[j + 3] + a[j2 + 3];
+    y1r = a[j + 2] - a[j2 + 2];
+    y1i = a[j + 3] - a[j2 + 3];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    y2r = a[j1 + 2] + a[j3 + 2];
+    y2i = a[j1 + 3] + a[j3 + 3];
+    y3r = a[j1 + 2] - a[j3 + 2];
+    y3i = a[j1 + 3] - a[j3 + 3];
+    a[j] = x0r + x2r;
+    a[j + 1] = x0i + x2i;
+    a[j + 2] = y0r + y2r;
+    a[j + 3] = y0i + y2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i - x2i;
+    a[j1 + 2] = y0r - y2r;
+    a[j1 + 3] = y0i - y2i;
+    x0r = x1r - x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1r * x0r - wk1i * x0i;
+    a[j2 + 1] = wk1r * x0i + wk1i * x0r;
+    x0r = y1r - y3i;
+    x0i = y1i + y3r;
+    a[j2 + 2] = wd1r * x0r - wd1i * x0i;
+    a[j2 + 3] = wd1r * x0i + wd1i * x0r;
+    x0r = x1r + x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3r * x0r + wk3i * x0i;
+    a[j3 + 1] = wk3r * x0i - wk3i * x0r;
+    x0r = y1r + y3i;
+    x0i = y1i - y3r;
+    a[j3 + 2] = wd3r * x0r + wd3i * x0i;
+    a[j3 + 3] = wd3r * x0i - wd3i * x0r;
+    j0 = m - j;
+    j1 = j0 + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j0] + a[j2];
+    x0i = a[j0 + 1] + a[j2 + 1];
+    x1r = a[j0] - a[j2];
+    x1i = a[j0 + 1] - a[j2 + 1];
+    y0r = a[j0 - 2] + a[j2 - 2];
+    y0i = a[j0 - 1] + a[j2 - 1];
+    y1r = a[j0 - 2] - a[j2 - 2];
+    y1i = a[j0 - 1] - a[j2 - 1];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    y2r = a[j1 - 2] + a[j3 - 2];
+    y2i = a[j1 - 1] + a[j3 - 1];
+    y3r = a[j1 - 2] - a[j3 - 2];
+    y3i = a[j1 - 1] - a[j3 - 1];
+    a[j0] = x0r + x2r;
+    a[j0 + 1] = x0i + x2i;
+    a[j0 - 2] = y0r + y2r;
+    a[j0 - 1] = y0i + y2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i - x2i;
+    a[j1 - 2] = y0r - y2r;
+    a[j1 - 1] = y0i - y2i;
+    x0r = x1r - x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1i * x0r - wk1r * x0i;
+    a[j2 + 1] = wk1i * x0i + wk1r * x0r;
+    x0r = y1r - y3i;
+    x0i = y1i + y3r;
+    a[j2 - 2] = wd1i * x0r - wd1r * x0i;
+    a[j2 - 1] = wd1i * x0i + wd1r * x0r;
+    x0r = x1r + x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3i * x0r + wk3r * x0i;
+    a[j3 + 1] = wk3i * x0i - wk3r * x0r;
+    x0r = y1r + y3i;
+    x0i = y1i - y3r;
+    a[j3 - 2] = wd3i * x0r + wd3r * x0i;
+    a[j3 - 1] = wd3i * x0i - wd3r * x0r;
+  }
+  wk1r = csc1 * (wd1r + wn4r);
+  wk1i = csc1 * (wd1i + wn4r);
+  wk3r = csc3 * (wd3r - wn4r);
+  wk3i = csc3 * (wd3i - wn4r);
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0 - 2] + a[j2 - 2];
+  x0i = a[j0 - 1] + a[j2 - 1];
+  x1r = a[j0 - 2] - a[j2 - 2];
+  x1i = a[j0 - 1] - a[j2 - 1];
+  x2r = a[j1 - 2] + a[j3 - 2];
+  x2i = a[j1 - 1] + a[j3 - 1];
+  x3r = a[j1 - 2] - a[j3 - 2];
+  x3i = a[j1 - 1] - a[j3 - 1];
+  a[j0 - 2] = x0r + x2r;
+  a[j0 - 1] = x0i + x2i;
+  a[j1 - 2] = x0r - x2r;
+  a[j1 - 1] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2 - 2] = wk1r * x0r - wk1i * x0i;
+  a[j2 - 1] = wk1r * x0i + wk1i * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3 - 2] = wk3r * x0r + wk3i * x0i;
+  a[j3 - 1] = wk3r * x0i - wk3i * x0r;
+  x0r = a[j0] + a[j2];
+  x0i = a[j0 + 1] + a[j2 + 1];
+  x1r = a[j0] - a[j2];
+  x1i = a[j0 + 1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[j0] = x0r + x2r;
+  a[j0 + 1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2] = wn4r * (x0r - x0i);
+  a[j2 + 1] = wn4r * (x0i + x0r);
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3] = -wn4r * (x0r + x0i);
+  a[j3 + 1] = -wn4r * (x0i - x0r);
+  x0r = a[j0 + 2] + a[j2 + 2];
+  x0i = a[j0 + 3] + a[j2 + 3];
+  x1r = a[j0 + 2] - a[j2 + 2];
+  x1i = a[j0 + 3] - a[j2 + 3];
+  x2r = a[j1 + 2] + a[j3 + 2];
+  x2i = a[j1 + 3] + a[j3 + 3];
+  x3r = a[j1 + 2] - a[j3 + 2];
+  x3i = a[j1 + 3] - a[j3 + 3];
+  a[j0 + 2] = x0r + x2r;
+  a[j0 + 3] = x0i + x2i;
+  a[j1 + 2] = x0r - x2r;
+  a[j1 + 3] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2 + 2] = wk1i * x0r - wk1r * x0i;
+  a[j2 + 3] = wk1i * x0i + wk1r * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3 + 2] = wk3i * x0r + wk3r * x0i;
+  a[j3 + 3] = wk3i * x0i - wk3r * x0r;
+}
+
+void cftb1st(int n, float* a, float* w)
+{
+  int j, j0, j1, j2, j3, k, m, mh;
+  float wn4r, csc1, csc3, wk1r, wk1i, wk3r, wk3i, wd1r, wd1i, wd3r, wd3i;
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r, y1i, y2r, y2i,
+      y3r, y3i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] + a[j2];
+  x0i = -a[1] - a[j2 + 1];
+  x1r = a[0] - a[j2];
+  x1i = -a[1] + a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[0] = x0r + x2r;
+  a[1] = x0i - x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i + x2i;
+  a[j2] = x1r + x3i;
+  a[j2 + 1] = x1i + x3r;
+  a[j3] = x1r - x3i;
+  a[j3 + 1] = x1i - x3r;
+  wn4r = w[1];
+  csc1 = w[2];
+  csc3 = w[3];
+  wd1r = 1;
+  wd1i = 0;
+  wd3r = 1;
+  wd3i = 0;
+  k = 0;
+  for (j = 2; j < mh - 2; j += 4) {
+    k += 4;
+    wk1r = csc1 * (wd1r + w[k]);
+    wk1i = csc1 * (wd1i + w[k + 1]);
+    wk3r = csc3 * (wd3r + w[k + 2]);
+    wk3i = csc3 * (wd3i + w[k + 3]);
+    wd1r = w[k];
+    wd1i = w[k + 1];
+    wd3r = w[k + 2];
+    wd3i = w[k + 3];
+    j1 = j + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j] + a[j2];
+    x0i = -a[j + 1] - a[j2 + 1];
+    x1r = a[j] - a[j2];
+    x1i = -a[j + 1] + a[j2 + 1];
+    y0r = a[j + 2] + a[j2 + 2];
+    y0i = -a[j + 3] - a[j2 + 3];
+    y1r = a[j + 2] - a[j2 + 2];
+    y1i = -a[j + 3] + a[j2 + 3];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    y2r = a[j1 + 2] + a[j3 + 2];
+    y2i = a[j1 + 3] + a[j3 + 3];
+    y3r = a[j1 + 2] - a[j3 + 2];
+    y3i = a[j1 + 3] - a[j3 + 3];
+    a[j] = x0r + x2r;
+    a[j + 1] = x0i - x2i;
+    a[j + 2] = y0r + y2r;
+    a[j + 3] = y0i - y2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i + x2i;
+    a[j1 + 2] = y0r - y2r;
+    a[j1 + 3] = y0i + y2i;
+    x0r = x1r + x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1r * x0r - wk1i * x0i;
+    a[j2 + 1] = wk1r * x0i + wk1i * x0r;
+    x0r = y1r + y3i;
+    x0i = y1i + y3r;
+    a[j2 + 2] = wd1r * x0r - wd1i * x0i;
+    a[j2 + 3] = wd1r * x0i + wd1i * x0r;
+    x0r = x1r - x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3r * x0r + wk3i * x0i;
+    a[j3 + 1] = wk3r * x0i - wk3i * x0r;
+    x0r = y1r - y3i;
+    x0i = y1i - y3r;
+    a[j3 + 2] = wd3r * x0r + wd3i * x0i;
+    a[j3 + 3] = wd3r * x0i - wd3i * x0r;
+    j0 = m - j;
+    j1 = j0 + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j0] + a[j2];
+    x0i = -a[j0 + 1] - a[j2 + 1];
+    x1r = a[j0] - a[j2];
+    x1i = -a[j0 + 1] + a[j2 + 1];
+    y0r = a[j0 - 2] + a[j2 - 2];
+    y0i = -a[j0 - 1] - a[j2 - 1];
+    y1r = a[j0 - 2] - a[j2 - 2];
+    y1i = -a[j0 - 1] + a[j2 - 1];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    y2r = a[j1 - 2] + a[j3 - 2];
+    y2i = a[j1 - 1] + a[j3 - 1];
+    y3r = a[j1 - 2] - a[j3 - 2];
+    y3i = a[j1 - 1] - a[j3 - 1];
+    a[j0] = x0r + x2r;
+    a[j0 + 1] = x0i - x2i;
+    a[j0 - 2] = y0r + y2r;
+    a[j0 - 1] = y0i - y2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i + x2i;
+    a[j1 - 2] = y0r - y2r;
+    a[j1 - 1] = y0i + y2i;
+    x0r = x1r + x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1i * x0r - wk1r * x0i;
+    a[j2 + 1] = wk1i * x0i + wk1r * x0r;
+    x0r = y1r + y3i;
+    x0i = y1i + y3r;
+    a[j2 - 2] = wd1i * x0r - wd1r * x0i;
+    a[j2 - 1] = wd1i * x0i + wd1r * x0r;
+    x0r = x1r - x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3i * x0r + wk3r * x0i;
+    a[j3 + 1] = wk3i * x0i - wk3r * x0r;
+    x0r = y1r - y3i;
+    x0i = y1i - y3r;
+    a[j3 - 2] = wd3i * x0r + wd3r * x0i;
+    a[j3 - 1] = wd3i * x0i - wd3r * x0r;
+  }
+  wk1r = csc1 * (wd1r + wn4r);
+  wk1i = csc1 * (wd1i + wn4r);
+  wk3r = csc3 * (wd3r - wn4r);
+  wk3i = csc3 * (wd3i - wn4r);
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0 - 2] + a[j2 - 2];
+  x0i = -a[j0 - 1] - a[j2 - 1];
+  x1r = a[j0 - 2] - a[j2 - 2];
+  x1i = -a[j0 - 1] + a[j2 - 1];
+  x2r = a[j1 - 2] + a[j3 - 2];
+  x2i = a[j1 - 1] + a[j3 - 1];
+  x3r = a[j1 - 2] - a[j3 - 2];
+  x3i = a[j1 - 1] - a[j3 - 1];
+  a[j0 - 2] = x0r + x2r;
+  a[j0 - 1] = x0i - x2i;
+  a[j1 - 2] = x0r - x2r;
+  a[j1 - 1] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2 - 2] = wk1r * x0r - wk1i * x0i;
+  a[j2 - 1] = wk1r * x0i + wk1i * x0r;
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3 - 2] = wk3r * x0r + wk3i * x0i;
+  a[j3 - 1] = wk3r * x0i - wk3i * x0r;
+  x0r = a[j0] + a[j2];
+  x0i = -a[j0 + 1] - a[j2 + 1];
+  x1r = a[j0] - a[j2];
+  x1i = -a[j0 + 1] + a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[j0] = x0r + x2r;
+  a[j0 + 1] = x0i - x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2] = wn4r * (x0r - x0i);
+  a[j2 + 1] = wn4r * (x0i + x0r);
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3] = -wn4r * (x0r + x0i);
+  a[j3 + 1] = -wn4r * (x0i - x0r);
+  x0r = a[j0 + 2] + a[j2 + 2];
+  x0i = -a[j0 + 3] - a[j2 + 3];
+  x1r = a[j0 + 2] - a[j2 + 2];
+  x1i = -a[j0 + 3] + a[j2 + 3];
+  x2r = a[j1 + 2] + a[j3 + 2];
+  x2i = a[j1 + 3] + a[j3 + 3];
+  x3r = a[j1 + 2] - a[j3 + 2];
+  x3i = a[j1 + 3] - a[j3 + 3];
+  a[j0 + 2] = x0r + x2r;
+  a[j0 + 3] = x0i - x2i;
+  a[j1 + 2] = x0r - x2r;
+  a[j1 + 3] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2 + 2] = wk1i * x0r - wk1r * x0i;
+  a[j2 + 3] = wk1i * x0i + wk1r * x0r;
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3 + 2] = wk3i * x0r + wk3r * x0i;
+  a[j3 + 3] = wk3i * x0i - wk3r * x0r;
+}
+
+#ifdef USE_CDFT_THREADS
+struct cdft_arg_st
+{
+  int n0;
+  int n;
+  float* a;
+  int nw;
+  float* w;
+};
+typedef struct cdft_arg_st cdft_arg_t;
+
+void cftrec4_th(int n, float* a, int nw, float* w)
+{
+  void* cftrec1_th(void* p);
+  void* cftrec2_th(void* p);
+  int i, idiv4, m, nthread;
+  cdft_thread_t th[4];
+  cdft_arg_t ag[4];
+
+  nthread = 2;
+  idiv4 = 0;
+  m = n >> 1;
+  if (n > CDFT_4THREADS_BEGIN_N) {
+    nthread = 4;
+    idiv4 = 1;
+    m >>= 1;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].n0 = n;
+    ag[i].n = m;
+    ag[i].a = &a[i * m];
+    ag[i].nw = nw;
+    ag[i].w = w;
+    if (i != idiv4) {
+      cdft_thread_create(&th[i], cftrec1_th, &ag[i]);
+    } else {
+      cdft_thread_create(&th[i], cftrec2_th, &ag[i]);
+    }
+  }
+  for (i = 0; i < nthread; i++) {
+    cdft_thread_wait(th[i]);
+  }
+}
+
+void* cftrec1_th(void* p)
+{
+  int cfttree(int n, int j, int k, float* a, int nw, float* w);
+  void cftleaf(int n, int isplt, float* a, int nw, float* w);
+  void cftmdl1(int n, float* a, float* w);
+  int isplt, j, k, m, n, n0, nw;
+  float *a, *w;
+
+  n0 = ((cdft_arg_t*) p)->n0;
+  n = ((cdft_arg_t*) p)->n;
+  a = ((cdft_arg_t*) p)->a;
+  nw = ((cdft_arg_t*) p)->nw;
+  w = ((cdft_arg_t*) p)->w;
+  m = n0;
+  while (m > 512) {
+    m >>= 2;
+    cftmdl1(m, &a[n - m], &w[nw - (m >> 1)]);
+  }
+  cftleaf(m, 1, &a[n - m], nw, w);
+  k = 0;
+  for (j = n - m; j > 0; j -= m) {
+    k++;
+    isplt = cfttree(m, j, k, a, nw, w);
+    cftleaf(m, isplt, &a[j - m], nw, w);
+  }
+  return (void*) 0;
+}
+
+void* cftrec2_th(void* p)
+{
+  int cfttree(int n, int j, int k, float* a, int nw, float* w);
+  void cftleaf(int n, int isplt, float* a, int nw, float* w);
+  void cftmdl2(int n, float* a, float* w);
+  int isplt, j, k, m, n, n0, nw;
+  float *a, *w;
+
+  n0 = ((cdft_arg_t*) p)->n0;
+  n = ((cdft_arg_t*) p)->n;
+  a = ((cdft_arg_t*) p)->a;
+  nw = ((cdft_arg_t*) p)->nw;
+  w = ((cdft_arg_t*) p)->w;
+  k = 1;
+  m = n0;
+  while (m > 512) {
+    m >>= 2;
+    k <<= 2;
+    cftmdl2(m, &a[n - m], &w[nw - m]);
+  }
+  cftleaf(m, 0, &a[n - m], nw, w);
+  k >>= 1;
+  for (j = n - m; j > 0; j -= m) {
+    k++;
+    isplt = cfttree(m, j, k, a, nw, w);
+    cftleaf(m, isplt, &a[j - m], nw, w);
+  }
+  return (void*) 0;
+}
+#endif /* USE_CDFT_THREADS */
+
+void cftrec4(int n, float* a, int nw, float* w)
+{
+  int cfttree(int n, int j, int k, float* a, int nw, float* w);
+  void cftleaf(int n, int isplt, float* a, int nw, float* w);
+  void cftmdl1(int n, float* a, float* w);
+  int isplt, j, k, m;
+
+  m = n;
+  while (m > 512) {
+    m >>= 2;
+    cftmdl1(m, &a[n - m], &w[nw - (m >> 1)]);
+  }
+  cftleaf(m, 1, &a[n - m], nw, w);
+  k = 0;
+  for (j = n - m; j > 0; j -= m) {
+    k++;
+    isplt = cfttree(m, j, k, a, nw, w);
+    cftleaf(m, isplt, &a[j - m], nw, w);
+  }
+}
+
+int cfttree(int n, int j, int k, float* a, int nw, float* w)
+{
+  void cftmdl1(int n, float* a, float* w);
+  void cftmdl2(int n, float* a, float* w);
+  int i, isplt, m;
+
+  if ((k & 3) != 0) {
+    isplt = k & 1;
+    if (isplt != 0) {
+      cftmdl1(n, &a[j - n], &w[nw - (n >> 1)]);
+    } else {
+      cftmdl2(n, &a[j - n], &w[nw - n]);
+    }
+  } else {
+    m = n;
+    for (i = k; (i & 3) == 0; i >>= 2) {
+      m <<= 2;
+    }
+    isplt = i & 1;
+    if (isplt != 0) {
+      while (m > 128) {
+        cftmdl1(m, &a[j - m], &w[nw - (m >> 1)]);
+        m >>= 2;
+      }
+    } else {
+      while (m > 128) {
+        cftmdl2(m, &a[j - m], &w[nw - m]);
+        m >>= 2;
+      }
+    }
+  }
+  return isplt;
+}
+
+void cftleaf(int n, int isplt, float* a, int nw, float* w)
+{
+  void cftmdl1(int n, float* a, float* w);
+  void cftmdl2(int n, float* a, float* w);
+  void cftf161(float* a, float* w);
+  void cftf162(float* a, float* w);
+  void cftf081(float* a, float* w);
+  void cftf082(float* a, float* w);
+
+  if (n == 512) {
+    cftmdl1(128, a, &w[nw - 64]);
+    cftf161(a, &w[nw - 8]);
+    cftf162(&a[32], &w[nw - 32]);
+    cftf161(&a[64], &w[nw - 8]);
+    cftf161(&a[96], &w[nw - 8]);
+    cftmdl2(128, &a[128], &w[nw - 128]);
+    cftf161(&a[128], &w[nw - 8]);
+    cftf162(&a[160], &w[nw - 32]);
+    cftf161(&a[192], &w[nw - 8]);
+    cftf162(&a[224], &w[nw - 32]);
+    cftmdl1(128, &a[256], &w[nw - 64]);
+    cftf161(&a[256], &w[nw - 8]);
+    cftf162(&a[288], &w[nw - 32]);
+    cftf161(&a[320], &w[nw - 8]);
+    cftf161(&a[352], &w[nw - 8]);
+    if (isplt != 0) {
+      cftmdl1(128, &a[384], &w[nw - 64]);
+      cftf161(&a[480], &w[nw - 8]);
+    } else {
+      cftmdl2(128, &a[384], &w[nw - 128]);
+      cftf162(&a[480], &w[nw - 32]);
+    }
+    cftf161(&a[384], &w[nw - 8]);
+    cftf162(&a[416], &w[nw - 32]);
+    cftf161(&a[448], &w[nw - 8]);
+  } else {
+    cftmdl1(64, a, &w[nw - 32]);
+    cftf081(a, &w[nw - 8]);
+    cftf082(&a[16], &w[nw - 8]);
+    cftf081(&a[32], &w[nw - 8]);
+    cftf081(&a[48], &w[nw - 8]);
+    cftmdl2(64, &a[64], &w[nw - 64]);
+    cftf081(&a[64], &w[nw - 8]);
+    cftf082(&a[80], &w[nw - 8]);
+    cftf081(&a[96], &w[nw - 8]);
+    cftf082(&a[112], &w[nw - 8]);
+    cftmdl1(64, &a[128], &w[nw - 32]);
+    cftf081(&a[128], &w[nw - 8]);
+    cftf082(&a[144], &w[nw - 8]);
+    cftf081(&a[160], &w[nw - 8]);
+    cftf081(&a[176], &w[nw - 8]);
+    if (isplt != 0) {
+      cftmdl1(64, &a[192], &w[nw - 32]);
+      cftf081(&a[240], &w[nw - 8]);
+    } else {
+      cftmdl2(64, &a[192], &w[nw - 64]);
+      cftf082(&a[240], &w[nw - 8]);
+    }
+    cftf081(&a[192], &w[nw - 8]);
+    cftf082(&a[208], &w[nw - 8]);
+    cftf081(&a[224], &w[nw - 8]);
+  }
+}
+
+void cftmdl1(int n, float* a, float* w)
+{
+  int j, j0, j1, j2, j3, k, m, mh;
+  float wn4r, wk1r, wk1i, wk3r, wk3i;
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] + a[j2];
+  x0i = a[1] + a[j2 + 1];
+  x1r = a[0] - a[j2];
+  x1i = a[1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  a[j2] = x1r - x3i;
+  a[j2 + 1] = x1i + x3r;
+  a[j3] = x1r + x3i;
+  a[j3 + 1] = x1i - x3r;
+  wn4r = w[1];
+  k = 0;
+  for (j = 2; j < mh; j += 2) {
+    k += 4;
+    wk1r = w[k];
+    wk1i = w[k + 1];
+    wk3r = w[k + 2];
+    wk3i = w[k + 3];
+    j1 = j + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j] + a[j2];
+    x0i = a[j + 1] + a[j2 + 1];
+    x1r = a[j] - a[j2];
+    x1i = a[j + 1] - a[j2 + 1];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    a[j] = x0r + x2r;
+    a[j + 1] = x0i + x2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i - x2i;
+    x0r = x1r - x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1r * x0r - wk1i * x0i;
+    a[j2 + 1] = wk1r * x0i + wk1i * x0r;
+    x0r = x1r + x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3r * x0r + wk3i * x0i;
+    a[j3 + 1] = wk3r * x0i - wk3i * x0r;
+    j0 = m - j;
+    j1 = j0 + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j0] + a[j2];
+    x0i = a[j0 + 1] + a[j2 + 1];
+    x1r = a[j0] - a[j2];
+    x1i = a[j0 + 1] - a[j2 + 1];
+    x2r = a[j1] + a[j3];
+    x2i = a[j1 + 1] + a[j3 + 1];
+    x3r = a[j1] - a[j3];
+    x3i = a[j1 + 1] - a[j3 + 1];
+    a[j0] = x0r + x2r;
+    a[j0 + 1] = x0i + x2i;
+    a[j1] = x0r - x2r;
+    a[j1 + 1] = x0i - x2i;
+    x0r = x1r - x3i;
+    x0i = x1i + x3r;
+    a[j2] = wk1i * x0r - wk1r * x0i;
+    a[j2 + 1] = wk1i * x0i + wk1r * x0r;
+    x0r = x1r + x3i;
+    x0i = x1i - x3r;
+    a[j3] = wk3i * x0r + wk3r * x0i;
+    a[j3 + 1] = wk3i * x0i - wk3r * x0r;
+  }
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0] + a[j2];
+  x0i = a[j0 + 1] + a[j2 + 1];
+  x1r = a[j0] - a[j2];
+  x1i = a[j0 + 1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[j0] = x0r + x2r;
+  a[j0 + 1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2] = wn4r * (x0r - x0i);
+  a[j2 + 1] = wn4r * (x0i + x0r);
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3] = -wn4r * (x0r + x0i);
+  a[j3 + 1] = -wn4r * (x0i - x0r);
+}
+
+void cftmdl2(int n, float* a, float* w)
+{
+  int j, j0, j1, j2, j3, k, kr, m, mh;
+  float wn4r, wk1r, wk1i, wk3r, wk3i, wd1r, wd1i, wd3r, wd3i;
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y2r, y2i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  wn4r = w[1];
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] - a[j2 + 1];
+  x0i = a[1] + a[j2];
+  x1r = a[0] + a[j2 + 1];
+  x1i = a[1] - a[j2];
+  x2r = a[j1] - a[j3 + 1];
+  x2i = a[j1 + 1] + a[j3];
+  x3r = a[j1] + a[j3 + 1];
+  x3i = a[j1 + 1] - a[j3];
+  y0r = wn4r * (x2r - x2i);
+  y0i = wn4r * (x2i + x2r);
+  a[0] = x0r + y0r;
+  a[1] = x0i + y0i;
+  a[j1] = x0r - y0r;
+  a[j1 + 1] = x0i - y0i;
+  y0r = wn4r * (x3r - x3i);
+  y0i = wn4r * (x3i + x3r);
+  a[j2] = x1r - y0i;
+  a[j2 + 1] = x1i + y0r;
+  a[j3] = x1r + y0i;
+  a[j3 + 1] = x1i - y0r;
+  k = 0;
+  kr = 2 * m;
+  for (j = 2; j < mh; j += 2) {
+    k += 4;
+    wk1r = w[k];
+    wk1i = w[k + 1];
+    wk3r = w[k + 2];
+    wk3i = w[k + 3];
+    kr -= 4;
+    wd1i = w[kr];
+    wd1r = w[kr + 1];
+    wd3i = w[kr + 2];
+    wd3r = w[kr + 3];
+    j1 = j + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j] - a[j2 + 1];
+    x0i = a[j + 1] + a[j2];
+    x1r = a[j] + a[j2 + 1];
+    x1i = a[j + 1] - a[j2];
+    x2r = a[j1] - a[j3 + 1];
+    x2i = a[j1 + 1] + a[j3];
+    x3r = a[j1] + a[j3 + 1];
+    x3i = a[j1 + 1] - a[j3];
+    y0r = wk1r * x0r - wk1i * x0i;
+    y0i = wk1r * x0i + wk1i * x0r;
+    y2r = wd1r * x2r - wd1i * x2i;
+    y2i = wd1r * x2i + wd1i * x2r;
+    a[j] = y0r + y2r;
+    a[j + 1] = y0i + y2i;
+    a[j1] = y0r - y2r;
+    a[j1 + 1] = y0i - y2i;
+    y0r = wk3r * x1r + wk3i * x1i;
+    y0i = wk3r * x1i - wk3i * x1r;
+    y2r = wd3r * x3r + wd3i * x3i;
+    y2i = wd3r * x3i - wd3i * x3r;
+    a[j2] = y0r + y2r;
+    a[j2 + 1] = y0i + y2i;
+    a[j3] = y0r - y2r;
+    a[j3 + 1] = y0i - y2i;
+    j0 = m - j;
+    j1 = j0 + m;
+    j2 = j1 + m;
+    j3 = j2 + m;
+    x0r = a[j0] - a[j2 + 1];
+    x0i = a[j0 + 1] + a[j2];
+    x1r = a[j0] + a[j2 + 1];
+    x1i = a[j0 + 1] - a[j2];
+    x2r = a[j1] - a[j3 + 1];
+    x2i = a[j1 + 1] + a[j3];
+    x3r = a[j1] + a[j3 + 1];
+    x3i = a[j1 + 1] - a[j3];
+    y0r = wd1i * x0r - wd1r * x0i;
+    y0i = wd1i * x0i + wd1r * x0r;
+    y2r = wk1i * x2r - wk1r * x2i;
+    y2i = wk1i * x2i + wk1r * x2r;
+    a[j0] = y0r + y2r;
+    a[j0 + 1] = y0i + y2i;
+    a[j1] = y0r - y2r;
+    a[j1 + 1] = y0i - y2i;
+    y0r = wd3i * x1r + wd3r * x1i;
+    y0i = wd3i * x1i - wd3r * x1r;
+    y2r = wk3i * x3r + wk3r * x3i;
+    y2i = wk3i * x3i - wk3r * x3r;
+    a[j2] = y0r + y2r;
+    a[j2 + 1] = y0i + y2i;
+    a[j3] = y0r - y2r;
+    a[j3 + 1] = y0i - y2i;
+  }
+  wk1r = w[m];
+  wk1i = w[m + 1];
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0] - a[j2 + 1];
+  x0i = a[j0 + 1] + a[j2];
+  x1r = a[j0] + a[j2 + 1];
+  x1i = a[j0 + 1] - a[j2];
+  x2r = a[j1] - a[j3 + 1];
+  x2i = a[j1 + 1] + a[j3];
+  x3r = a[j1] + a[j3 + 1];
+  x3i = a[j1 + 1] - a[j3];
+  y0r = wk1r * x0r - wk1i * x0i;
+  y0i = wk1r * x0i + wk1i * x0r;
+  y2r = wk1i * x2r - wk1r * x2i;
+  y2i = wk1i * x2i + wk1r * x2r;
+  a[j0] = y0r + y2r;
+  a[j0 + 1] = y0i + y2i;
+  a[j1] = y0r - y2r;
+  a[j1 + 1] = y0i - y2i;
+  y0r = wk1i * x1r - wk1r * x1i;
+  y0i = wk1i * x1i + wk1r * x1r;
+  y2r = wk1r * x3r - wk1i * x3i;
+  y2i = wk1r * x3i + wk1i * x3r;
+  a[j2] = y0r - y2r;
+  a[j2 + 1] = y0i - y2i;
+  a[j3] = y0r + y2r;
+  a[j3 + 1] = y0i + y2i;
+}
+
+void cftfx41(int n, float* a, int nw, float* w)
+{
+  void cftf161(float* a, float* w);
+  void cftf162(float* a, float* w);
+  void cftf081(float* a, float* w);
+  void cftf082(float* a, float* w);
+
+  if (n == 128) {
+    cftf161(a, &w[nw - 8]);
+    cftf162(&a[32], &w[nw - 32]);
+    cftf161(&a[64], &w[nw - 8]);
+    cftf161(&a[96], &w[nw - 8]);
+  } else {
+    cftf081(a, &w[nw - 8]);
+    cftf082(&a[16], &w[nw - 8]);
+    cftf081(&a[32], &w[nw - 8]);
+    cftf081(&a[48], &w[nw - 8]);
+  }
+}
+
+void cftf161(float* a, float* w)
+{
+  float wn4r, wk1r, wk1i, x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r,
+      y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i, y8r, y8i,
+      y9r, y9i, y10r, y10i, y11r, y11i, y12r, y12i, y13r, y13i, y14r, y14i,
+      y15r, y15i;
+
+  wn4r = w[1];
+  wk1r = w[2];
+  wk1i = w[3];
+  x0r = a[0] + a[16];
+  x0i = a[1] + a[17];
+  x1r = a[0] - a[16];
+  x1i = a[1] - a[17];
+  x2r = a[8] + a[24];
+  x2i = a[9] + a[25];
+  x3r = a[8] - a[24];
+  x3i = a[9] - a[25];
+  y0r = x0r + x2r;
+  y0i = x0i + x2i;
+  y4r = x0r - x2r;
+  y4i = x0i - x2i;
+  y8r = x1r - x3i;
+  y8i = x1i + x3r;
+  y12r = x1r + x3i;
+  y12i = x1i - x3r;
+  x0r = a[2] + a[18];
+  x0i = a[3] + a[19];
+  x1r = a[2] - a[18];
+  x1i = a[3] - a[19];
+  x2r = a[10] + a[26];
+  x2i = a[11] + a[27];
+  x3r = a[10] - a[26];
+  x3i = a[11] - a[27];
+  y1r = x0r + x2r;
+  y1i = x0i + x2i;
+  y5r = x0r - x2r;
+  y5i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y9r = wk1r * x0r - wk1i * x0i;
+  y9i = wk1r * x0i + wk1i * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y13r = wk1i * x0r - wk1r * x0i;
+  y13i = wk1i * x0i + wk1r * x0r;
+  x0r = a[4] + a[20];
+  x0i = a[5] + a[21];
+  x1r = a[4] - a[20];
+  x1i = a[5] - a[21];
+  x2r = a[12] + a[28];
+  x2i = a[13] + a[29];
+  x3r = a[12] - a[28];
+  x3i = a[13] - a[29];
+  y2r = x0r + x2r;
+  y2i = x0i + x2i;
+  y6r = x0r - x2r;
+  y6i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y10r = wn4r * (x0r - x0i);
+  y10i = wn4r * (x0i + x0r);
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y14r = wn4r * (x0r + x0i);
+  y14i = wn4r * (x0i - x0r);
+  x0r = a[6] + a[22];
+  x0i = a[7] + a[23];
+  x1r = a[6] - a[22];
+  x1i = a[7] - a[23];
+  x2r = a[14] + a[30];
+  x2i = a[15] + a[31];
+  x3r = a[14] - a[30];
+  x3i = a[15] - a[31];
+  y3r = x0r + x2r;
+  y3i = x0i + x2i;
+  y7r = x0r - x2r;
+  y7i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y11r = wk1i * x0r - wk1r * x0i;
+  y11i = wk1i * x0i + wk1r * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y15r = wk1r * x0r - wk1i * x0i;
+  y15i = wk1r * x0i + wk1i * x0r;
+  x0r = y12r - y14r;
+  x0i = y12i - y14i;
+  x1r = y12r + y14r;
+  x1i = y12i + y14i;
+  x2r = y13r - y15r;
+  x2i = y13i - y15i;
+  x3r = y13r + y15r;
+  x3i = y13i + y15i;
+  a[24] = x0r + x2r;
+  a[25] = x0i + x2i;
+  a[26] = x0r - x2r;
+  a[27] = x0i - x2i;
+  a[28] = x1r - x3i;
+  a[29] = x1i + x3r;
+  a[30] = x1r + x3i;
+  a[31] = x1i - x3r;
+  x0r = y8r + y10r;
+  x0i = y8i + y10i;
+  x1r = y8r - y10r;
+  x1i = y8i - y10i;
+  x2r = y9r + y11r;
+  x2i = y9i + y11i;
+  x3r = y9r - y11r;
+  x3i = y9i - y11i;
+  a[16] = x0r + x2r;
+  a[17] = x0i + x2i;
+  a[18] = x0r - x2r;
+  a[19] = x0i - x2i;
+  a[20] = x1r - x3i;
+  a[21] = x1i + x3r;
+  a[22] = x1r + x3i;
+  a[23] = x1i - x3r;
+  x0r = y5r - y7i;
+  x0i = y5i + y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  x0r = y5r + y7i;
+  x0i = y5i - y7r;
+  x3r = wn4r * (x0r - x0i);
+  x3i = wn4r * (x0i + x0r);
+  x0r = y4r - y6i;
+  x0i = y4i + y6r;
+  x1r = y4r + y6i;
+  x1i = y4i - y6r;
+  a[8] = x0r + x2r;
+  a[9] = x0i + x2i;
+  a[10] = x0r - x2r;
+  a[11] = x0i - x2i;
+  a[12] = x1r - x3i;
+  a[13] = x1i + x3r;
+  a[14] = x1r + x3i;
+  a[15] = x1i - x3r;
+  x0r = y0r + y2r;
+  x0i = y0i + y2i;
+  x1r = y0r - y2r;
+  x1i = y0i - y2i;
+  x2r = y1r + y3r;
+  x2i = y1i + y3i;
+  x3r = y1r - y3r;
+  x3i = y1i - y3i;
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[2] = x0r - x2r;
+  a[3] = x0i - x2i;
+  a[4] = x1r - x3i;
+  a[5] = x1i + x3r;
+  a[6] = x1r + x3i;
+  a[7] = x1i - x3r;
+}
+
+void cftf162(float* a, float* w)
+{
+  float wn4r, wk1r, wk1i, wk2r, wk2i, wk3r, wk3i, x0r, x0i, x1r, x1i, x2r, x2i,
+      y0r, y0i, y1r, y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r,
+      y7i, y8r, y8i, y9r, y9i, y10r, y10i, y11r, y11i, y12r, y12i, y13r, y13i,
+      y14r, y14i, y15r, y15i;
+
+  wn4r = w[1];
+  wk1r = w[4];
+  wk1i = w[5];
+  wk3r = w[6];
+  wk3i = -w[7];
+  wk2r = w[8];
+  wk2i = w[9];
+  x1r = a[0] - a[17];
+  x1i = a[1] + a[16];
+  x0r = a[8] - a[25];
+  x0i = a[9] + a[24];
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  y0r = x1r + x2r;
+  y0i = x1i + x2i;
+  y4r = x1r - x2r;
+  y4i = x1i - x2i;
+  x1r = a[0] + a[17];
+  x1i = a[1] - a[16];
+  x0r = a[8] + a[25];
+  x0i = a[9] - a[24];
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  y8r = x1r - x2i;
+  y8i = x1i + x2r;
+  y12r = x1r + x2i;
+  y12i = x1i - x2r;
+  x0r = a[2] - a[19];
+  x0i = a[3] + a[18];
+  x1r = wk1r * x0r - wk1i * x0i;
+  x1i = wk1r * x0i + wk1i * x0r;
+  x0r = a[10] - a[27];
+  x0i = a[11] + a[26];
+  x2r = wk3i * x0r - wk3r * x0i;
+  x2i = wk3i * x0i + wk3r * x0r;
+  y1r = x1r + x2r;
+  y1i = x1i + x2i;
+  y5r = x1r - x2r;
+  y5i = x1i - x2i;
+  x0r = a[2] + a[19];
+  x0i = a[3] - a[18];
+  x1r = wk3r * x0r - wk3i * x0i;
+  x1i = wk3r * x0i + wk3i * x0r;
+  x0r = a[10] + a[27];
+  x0i = a[11] - a[26];
+  x2r = wk1r * x0r + wk1i * x0i;
+  x2i = wk1r * x0i - wk1i * x0r;
+  y9r = x1r - x2r;
+  y9i = x1i - x2i;
+  y13r = x1r + x2r;
+  y13i = x1i + x2i;
+  x0r = a[4] - a[21];
+  x0i = a[5] + a[20];
+  x1r = wk2r * x0r - wk2i * x0i;
+  x1i = wk2r * x0i + wk2i * x0r;
+  x0r = a[12] - a[29];
+  x0i = a[13] + a[28];
+  x2r = wk2i * x0r - wk2r * x0i;
+  x2i = wk2i * x0i + wk2r * x0r;
+  y2r = x1r + x2r;
+  y2i = x1i + x2i;
+  y6r = x1r - x2r;
+  y6i = x1i - x2i;
+  x0r = a[4] + a[21];
+  x0i = a[5] - a[20];
+  x1r = wk2i * x0r - wk2r * x0i;
+  x1i = wk2i * x0i + wk2r * x0r;
+  x0r = a[12] + a[29];
+  x0i = a[13] - a[28];
+  x2r = wk2r * x0r - wk2i * x0i;
+  x2i = wk2r * x0i + wk2i * x0r;
+  y10r = x1r - x2r;
+  y10i = x1i - x2i;
+  y14r = x1r + x2r;
+  y14i = x1i + x2i;
+  x0r = a[6] - a[23];
+  x0i = a[7] + a[22];
+  x1r = wk3r * x0r - wk3i * x0i;
+  x1i = wk3r * x0i + wk3i * x0r;
+  x0r = a[14] - a[31];
+  x0i = a[15] + a[30];
+  x2r = wk1i * x0r - wk1r * x0i;
+  x2i = wk1i * x0i + wk1r * x0r;
+  y3r = x1r + x2r;
+  y3i = x1i + x2i;
+  y7r = x1r - x2r;
+  y7i = x1i - x2i;
+  x0r = a[6] + a[23];
+  x0i = a[7] - a[22];
+  x1r = wk1i * x0r + wk1r * x0i;
+  x1i = wk1i * x0i - wk1r * x0r;
+  x0r = a[14] + a[31];
+  x0i = a[15] - a[30];
+  x2r = wk3i * x0r - wk3r * x0i;
+  x2i = wk3i * x0i + wk3r * x0r;
+  y11r = x1r + x2r;
+  y11i = x1i + x2i;
+  y15r = x1r - x2r;
+  y15i = x1i - x2i;
+  x1r = y0r + y2r;
+  x1i = y0i + y2i;
+  x2r = y1r + y3r;
+  x2i = y1i + y3i;
+  a[0] = x1r + x2r;
+  a[1] = x1i + x2i;
+  a[2] = x1r - x2r;
+  a[3] = x1i - x2i;
+  x1r = y0r - y2r;
+  x1i = y0i - y2i;
+  x2r = y1r - y3r;
+  x2i = y1i - y3i;
+  a[4] = x1r - x2i;
+  a[5] = x1i + x2r;
+  a[6] = x1r + x2i;
+  a[7] = x1i - x2r;
+  x1r = y4r - y6i;
+  x1i = y4i + y6r;
+  x0r = y5r - y7i;
+  x0i = y5i + y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[8] = x1r + x2r;
+  a[9] = x1i + x2i;
+  a[10] = x1r - x2r;
+  a[11] = x1i - x2i;
+  x1r = y4r + y6i;
+  x1i = y4i - y6r;
+  x0r = y5r + y7i;
+  x0i = y5i - y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[12] = x1r - x2i;
+  a[13] = x1i + x2r;
+  a[14] = x1r + x2i;
+  a[15] = x1i - x2r;
+  x1r = y8r + y10r;
+  x1i = y8i + y10i;
+  x2r = y9r - y11r;
+  x2i = y9i - y11i;
+  a[16] = x1r + x2r;
+  a[17] = x1i + x2i;
+  a[18] = x1r - x2r;
+  a[19] = x1i - x2i;
+  x1r = y8r - y10r;
+  x1i = y8i - y10i;
+  x2r = y9r + y11r;
+  x2i = y9i + y11i;
+  a[20] = x1r - x2i;
+  a[21] = x1i + x2r;
+  a[22] = x1r + x2i;
+  a[23] = x1i - x2r;
+  x1r = y12r - y14i;
+  x1i = y12i + y14r;
+  x0r = y13r + y15i;
+  x0i = y13i - y15r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[24] = x1r + x2r;
+  a[25] = x1i + x2i;
+  a[26] = x1r - x2r;
+  a[27] = x1i - x2i;
+  x1r = y12r + y14i;
+  x1i = y12i - y14r;
+  x0r = y13r - y15i;
+  x0i = y13i + y15r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[28] = x1r - x2i;
+  a[29] = x1i + x2r;
+  a[30] = x1r + x2i;
+  a[31] = x1i - x2r;
+}
+
+void cftf081(float* a, float* w)
+{
+  float wn4r, x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r, y1i, y2r,
+      y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i;
+
+  wn4r = w[1];
+  x0r = a[0] + a[8];
+  x0i = a[1] + a[9];
+  x1r = a[0] - a[8];
+  x1i = a[1] - a[9];
+  x2r = a[4] + a[12];
+  x2i = a[5] + a[13];
+  x3r = a[4] - a[12];
+  x3i = a[5] - a[13];
+  y0r = x0r + x2r;
+  y0i = x0i + x2i;
+  y2r = x0r - x2r;
+  y2i = x0i - x2i;
+  y1r = x1r - x3i;
+  y1i = x1i + x3r;
+  y3r = x1r + x3i;
+  y3i = x1i - x3r;
+  x0r = a[2] + a[10];
+  x0i = a[3] + a[11];
+  x1r = a[2] - a[10];
+  x1i = a[3] - a[11];
+  x2r = a[6] + a[14];
+  x2i = a[7] + a[15];
+  x3r = a[6] - a[14];
+  x3i = a[7] - a[15];
+  y4r = x0r + x2r;
+  y4i = x0i + x2i;
+  y6r = x0r - x2r;
+  y6i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  x2r = x1r + x3i;
+  x2i = x1i - x3r;
+  y5r = wn4r * (x0r - x0i);
+  y5i = wn4r * (x0r + x0i);
+  y7r = wn4r * (x2r - x2i);
+  y7i = wn4r * (x2r + x2i);
+  a[8] = y1r + y5r;
+  a[9] = y1i + y5i;
+  a[10] = y1r - y5r;
+  a[11] = y1i - y5i;
+  a[12] = y3r - y7i;
+  a[13] = y3i + y7r;
+  a[14] = y3r + y7i;
+  a[15] = y3i - y7r;
+  a[0] = y0r + y4r;
+  a[1] = y0i + y4i;
+  a[2] = y0r - y4r;
+  a[3] = y0i - y4i;
+  a[4] = y2r - y6i;
+  a[5] = y2i + y6r;
+  a[6] = y2r + y6i;
+  a[7] = y2i - y6r;
+}
+
+void cftf082(float* a, float* w)
+{
+  float wn4r, wk1r, wk1i, x0r, x0i, x1r, x1i, y0r, y0i, y1r, y1i, y2r, y2i, y3r,
+      y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i;
+
+  wn4r = w[1];
+  wk1r = w[2];
+  wk1i = w[3];
+  y0r = a[0] - a[9];
+  y0i = a[1] + a[8];
+  y1r = a[0] + a[9];
+  y1i = a[1] - a[8];
+  x0r = a[4] - a[13];
+  x0i = a[5] + a[12];
+  y2r = wn4r * (x0r - x0i);
+  y2i = wn4r * (x0i + x0r);
+  x0r = a[4] + a[13];
+  x0i = a[5] - a[12];
+  y3r = wn4r * (x0r - x0i);
+  y3i = wn4r * (x0i + x0r);
+  x0r = a[2] - a[11];
+  x0i = a[3] + a[10];
+  y4r = wk1r * x0r - wk1i * x0i;
+  y4i = wk1r * x0i + wk1i * x0r;
+  x0r = a[2] + a[11];
+  x0i = a[3] - a[10];
+  y5r = wk1i * x0r - wk1r * x0i;
+  y5i = wk1i * x0i + wk1r * x0r;
+  x0r = a[6] - a[15];
+  x0i = a[7] + a[14];
+  y6r = wk1i * x0r - wk1r * x0i;
+  y6i = wk1i * x0i + wk1r * x0r;
+  x0r = a[6] + a[15];
+  x0i = a[7] - a[14];
+  y7r = wk1r * x0r - wk1i * x0i;
+  y7i = wk1r * x0i + wk1i * x0r;
+  x0r = y0r + y2r;
+  x0i = y0i + y2i;
+  x1r = y4r + y6r;
+  x1i = y4i + y6i;
+  a[0] = x0r + x1r;
+  a[1] = x0i + x1i;
+  a[2] = x0r - x1r;
+  a[3] = x0i - x1i;
+  x0r = y0r - y2r;
+  x0i = y0i - y2i;
+  x1r = y4r - y6r;
+  x1i = y4i - y6i;
+  a[4] = x0r - x1i;
+  a[5] = x0i + x1r;
+  a[6] = x0r + x1i;
+  a[7] = x0i - x1r;
+  x0r = y1r - y3i;
+  x0i = y1i + y3r;
+  x1r = y5r - y7r;
+  x1i = y5i - y7i;
+  a[8] = x0r + x1r;
+  a[9] = x0i + x1i;
+  a[10] = x0r - x1r;
+  a[11] = x0i - x1i;
+  x0r = y1r + y3i;
+  x0i = y1i - y3r;
+  x1r = y5r + y7r;
+  x1i = y5i + y7i;
+  a[12] = x0r - x1i;
+  a[13] = x0i + x1r;
+  a[14] = x0r + x1i;
+  a[15] = x0i - x1r;
+}
+
+void cftf040(float* a)
+{
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  x0r = a[0] + a[4];
+  x0i = a[1] + a[5];
+  x1r = a[0] - a[4];
+  x1i = a[1] - a[5];
+  x2r = a[2] + a[6];
+  x2i = a[3] + a[7];
+  x3r = a[2] - a[6];
+  x3i = a[3] - a[7];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[2] = x1r - x3i;
+  a[3] = x1i + x3r;
+  a[4] = x0r - x2r;
+  a[5] = x0i - x2i;
+  a[6] = x1r + x3i;
+  a[7] = x1i - x3r;
+}
+
+void cftb040(float* a)
+{
+  float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  x0r = a[0] + a[4];
+  x0i = a[1] + a[5];
+  x1r = a[0] - a[4];
+  x1i = a[1] - a[5];
+  x2r = a[2] + a[6];
+  x2i = a[3] + a[7];
+  x3r = a[2] - a[6];
+  x3i = a[3] - a[7];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[2] = x1r + x3i;
+  a[3] = x1i - x3r;
+  a[4] = x0r - x2r;
+  a[5] = x0i - x2i;
+  a[6] = x1r - x3i;
+  a[7] = x1i + x3r;
+}
+
+void cftx020(float* a)
+{
+  float x0r, x0i;
+
+  x0r = a[0] - a[2];
+  x0i = a[1] - a[3];
+  a[0] += a[2];
+  a[1] += a[3];
+  a[2] = x0r;
+  a[3] = x0i;
+}
+
+void rftfsub(int n, float* a, int nc, float* c)
+{
+  int j, k, kk, ks, m;
+  float wkr, wki, xr, xi, yr, yi;
+
+  m = n >> 1;
+  ks = 2 * nc / m;
+  kk = 0;
+  for (j = 2; j < m; j += 2) {
+    k = n - j;
+    kk += ks;
+    wkr = 0.5 - c[nc - kk];
+    wki = c[kk];
+    xr = a[j] - a[k];
+    xi = a[j + 1] + a[k + 1];
+    yr = wkr * xr - wki * xi;
+    yi = wkr * xi + wki * xr;
+    a[j] -= yr;
+    a[j + 1] -= yi;
+    a[k] += yr;
+    a[k + 1] -= yi;
+  }
+}
+
+void rftbsub(int n, float* a, int nc, float* c)
+{
+  int j, k, kk, ks, m;
+  float wkr, wki, xr, xi, yr, yi;
+
+  m = n >> 1;
+  ks = 2 * nc / m;
+  kk = 0;
+  for (j = 2; j < m; j += 2) {
+    k = n - j;
+    kk += ks;
+    wkr = 0.5 - c[nc - kk];
+    wki = c[kk];
+    xr = a[j] - a[k];
+    xi = a[j + 1] + a[k + 1];
+    yr = wkr * xr + wki * xi;
+    yi = wkr * xi - wki * xr;
+    a[j] -= yr;
+    a[j + 1] -= yi;
+    a[k] += yr;
+    a[k + 1] -= yi;
+  }
+}
+
+void dctsub(int n, float* a, int nc, float* c)
+{
+  int j, k, kk, ks, m;
+  float wkr, wki, xr;
+
+  m = n >> 1;
+  ks = nc / n;
+  kk = 0;
+  for (j = 1; j < m; j++) {
+    k = n - j;
+    kk += ks;
+    wkr = c[kk] - c[nc - kk];
+    wki = c[kk] + c[nc - kk];
+    xr = wki * a[j] - wkr * a[k];
+    a[j] = wkr * a[j] + wki * a[k];
+    a[k] = xr;
+  }
+  a[m] *= c[0];
+}
+
+void dstsub(int n, float* a, int nc, float* c)
+{
+  int j, k, kk, ks, m;
+  float wkr, wki, xr;
+
+  m = n >> 1;
+  ks = nc / n;
+  kk = 0;
+  for (j = 1; j < m; j++) {
+    k = n - j;
+    kk += ks;
+    wkr = c[kk] - c[nc - kk];
+    wki = c[kk] + c[nc - kk];
+    xr = wki * a[k] - wkr * a[j];
+    a[k] = wkr * a[k] + wki * a[j];
+    a[j] = xr;
+  }
+  a[m] *= c[0];
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/3rdparty/oourafft/fftsg.h b/3rdparty/oourafft/fftsg.h
new file mode 100644
index 0000000000..4add9311c1
--- /dev/null
+++ b/3rdparty/oourafft/fftsg.h
@@ -0,0 +1,24 @@
+#ifndef FFTSG_H
+#define FFTSG_H
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+//
+// The following FFT library came from
+// http://www.kurims.kyoto-u.ac.jp/~ooura/fft.html
+//
+//
+/// 1D FFT ////////////////////////////////////////////////////////////////
+void ddct(int n, int isgn, float *a, int *ip, float *w);
+void ddst(int n, int isgn, float *a, int *ip, float *w);
+
+/// 2D FFT ////////////////////////////////////////////////////////////////
+void ddct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w);
+void ddsct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w);
+void ddcst2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w);
+
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/3rdparty/oourafft/fftsg2d.cc b/3rdparty/oourafft/fftsg2d.cc
new file mode 100644
index 0000000000..2bbc242824
--- /dev/null
+++ b/3rdparty/oourafft/fftsg2d.cc
@@ -0,0 +1,1419 @@
+///////////////////////////////////////////////////////////////////////////////
+// BSD 3-Clause License
+//
+// Copyright (c) 2018-2020, The Regents of the University of California
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of source code must retain the above copyright notice, this
+//   list of conditions and the following disclaimer.
+//
+// * Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+//
+// * Neither the name of the copyright holder nor the names of its
+//   contributors may be used to endorse or promote products derived from
+//   this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+///////////////////////////////////////////////////////////////////////////////
+
+/*
+Fast Fourier/Cosine/Sine Transform
+    dimension   :two
+    data length :power of 2
+    decimation  :frequency
+    radix       :split-radix, row-column
+    data        :inplace
+    table       :use
+functions
+    cdft2d: Complex Discrete Fourier Transform
+    rdft2d: Real Discrete Fourier Transform
+    ddct2d: Discrete Cosine Transform
+    ddst2d: Discrete Sine Transform
+function prototypes
+    void cdft2d(int, int, int, float   **, float   *, int *, float   *);
+    void rdft2d(int, int, int, float   **, float   *, int *, float   *);
+    void rdft2dsort(int, int, int, float   **);
+    void ddct2d(int, int, int, float   **, float   *, int *, float   *);
+    void ddst2d(int, int, int, float   **, float   *, int *, float   *);
+necessary package
+    fftsg.c  : 1D-FFT package
+macro definitions
+    USE_FFT2D_PTHREADS : default=not defined
+        FFT2D_MAX_THREADS     : must be 2^N, default=4
+        FFT2D_THREADS_BEGIN_N : default=65536
+    USE_FFT2D_WINTHREADS : default=not defined
+        FFT2D_MAX_THREADS     : must be 2^N, default=4
+        FFT2D_THREADS_BEGIN_N : default=131072
+
+
+-------- Complex DFT (Discrete Fourier Transform) --------
+    [definition]
+        <case1>
+            X[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 x[j1][j2] *
+                            exp(2*pi*i*j1*k1/n1) *
+                            exp(2*pi*i*j2*k2/n2), 0<=k1<n1, 0<=k2<n2
+        <case2>
+            X[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 x[j1][j2] *
+                            exp(-2*pi*i*j1*k1/n1) *
+                            exp(-2*pi*i*j2*k2/n2), 0<=k1<n1, 0<=k2<n2
+        (notes: sum_j=0^n-1 is a summation from j=0 to n-1)
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            cdft2d(n1, 2*n2, 1, a, t, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            cdft2d(n1, 2*n2, -1, a, t, ip, w);
+    [parameters]
+        n1     :data length (int)
+                n1 >= 1, n1 = power of 2
+        2*n2   :data length (int)
+                n2 >= 1, n2 = power of 2
+        a[0...n1-1][0...2*n2-1]
+               :input/output data (float   **)
+                input data
+                    a[j1][2*j2] = Re(x[j1][j2]),
+                    a[j1][2*j2+1] = Im(x[j1][j2]),
+                    0<=j1<n1, 0<=j2<n2
+                output data
+                    a[k1][2*k2] = Re(X[k1][k2]),
+                    a[k1][2*k2+1] = Im(X[k1][k2]),
+                    0<=k1<n1, 0<=k2<n2
+        t[0...*]
+               :work area (float   *)
+                length of t >= 8*n1,                   if single thread,
+                length of t >= 8*n1*FFT2D_MAX_THREADS, if multi threads,
+                t is dynamically allocated, if t == NULL.
+        ip[0...*]
+               :work area for bit reversal (int *)
+                length of ip >= 2+sqrt(n)
+                (n = max(n1, n2))
+                ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...*]
+               :cos/sin table (float   *)
+                length of w >= max(n1/2, n2/2)
+                w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            cdft2d(n1, 2*n2, -1, a, t, ip, w);
+        is
+            cdft2d(n1, 2*n2, 1, a, t, ip, w);
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                for (j2 = 0; j2 <= 2 * n2 - 1; j2++) {
+                    a[j1][j2] *= 1.0 / n1 / n2;
+                }
+            }
+        .
+
+
+-------- Real DFT / Inverse of Real DFT --------
+    [definition]
+        <case1> RDFT
+            R[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 a[j1][j2] *
+                            cos(2*pi*j1*k1/n1 + 2*pi*j2*k2/n2),
+                            0<=k1<n1, 0<=k2<n2
+            I[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 a[j1][j2] *
+                            sin(2*pi*j1*k1/n1 + 2*pi*j2*k2/n2),
+                            0<=k1<n1, 0<=k2<n2
+        <case2> IRDFT (excluding scale)
+            a[k1][k2] = (1/2) * sum_j1=0^n1-1 sum_j2=0^n2-1
+                            (R[j1][j2] *
+                            cos(2*pi*j1*k1/n1 + 2*pi*j2*k2/n2) +
+                            I[j1][j2] *
+                            sin(2*pi*j1*k1/n1 + 2*pi*j2*k2/n2)),
+                            0<=k1<n1, 0<=k2<n2
+        (notes: R[n1-k1][n2-k2] = R[k1][k2],
+                I[n1-k1][n2-k2] = -I[k1][k2],
+                R[n1-k1][0] = R[k1][0],
+                I[n1-k1][0] = -I[k1][0],
+                R[0][n2-k2] = R[0][k2],
+                I[0][n2-k2] = -I[0][k2],
+                0<k1<n1, 0<k2<n2)
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            rdft2d(n1, n2, 1, a, t, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            rdft2d(n1, n2, -1, a, t, ip, w);
+    [parameters]
+        n1     :data length (int)
+                n1 >= 2, n1 = power of 2
+        n2     :data length (int)
+                n2 >= 2, n2 = power of 2
+        a[0...n1-1][0...n2-1]
+               :input/output data (float   **)
+                <case1>
+                    output data
+                        a[k1][2*k2] = R[k1][k2] = R[n1-k1][n2-k2],
+                        a[k1][2*k2+1] = I[k1][k2] = -I[n1-k1][n2-k2],
+                            0<k1<n1, 0<k2<n2/2,
+                        a[0][2*k2] = R[0][k2] = R[0][n2-k2],
+                        a[0][2*k2+1] = I[0][k2] = -I[0][n2-k2],
+                            0<k2<n2/2,
+                        a[k1][0] = R[k1][0] = R[n1-k1][0],
+                        a[k1][1] = I[k1][0] = -I[n1-k1][0],
+                        a[n1-k1][1] = R[k1][n2/2] = R[n1-k1][n2/2],
+                        a[n1-k1][0] = -I[k1][n2/2] = I[n1-k1][n2/2],
+                            0<k1<n1/2,
+                        a[0][0] = R[0][0],
+                        a[0][1] = R[0][n2/2],
+                        a[n1/2][0] = R[n1/2][0],
+                        a[n1/2][1] = R[n1/2][n2/2]
+                <case2>
+                    input data
+                        a[j1][2*j2] = R[j1][j2] = R[n1-j1][n2-j2],
+                        a[j1][2*j2+1] = I[j1][j2] = -I[n1-j1][n2-j2],
+                            0<j1<n1, 0<j2<n2/2,
+                        a[0][2*j2] = R[0][j2] = R[0][n2-j2],
+                        a[0][2*j2+1] = I[0][j2] = -I[0][n2-j2],
+                            0<j2<n2/2,
+                        a[j1][0] = R[j1][0] = R[n1-j1][0],
+                        a[j1][1] = I[j1][0] = -I[n1-j1][0],
+                        a[n1-j1][1] = R[j1][n2/2] = R[n1-j1][n2/2],
+                        a[n1-j1][0] = -I[j1][n2/2] = I[n1-j1][n2/2],
+                            0<j1<n1/2,
+                        a[0][0] = R[0][0],
+                        a[0][1] = R[0][n2/2],
+                        a[n1/2][0] = R[n1/2][0],
+                        a[n1/2][1] = R[n1/2][n2/2]
+                ---- output ordering ----
+                    rdft2d(n1, n2, 1, a, t, ip, w);
+                    rdft2dsort(n1, n2, 1, a);
+                    // stored data is a[0...n1-1][0...n2+1]:
+                    // a[k1][2*k2] = R[k1][k2],
+                    // a[k1][2*k2+1] = I[k1][k2],
+                    // 0<=k1<n1, 0<=k2<=n2/2.
+                    // the stored data is larger than the input data!
+                ---- input ordering ----
+                    rdft2dsort(n1, n2, -1, a);
+                    rdft2d(n1, n2, -1, a, t, ip, w);
+        t[0...*]
+               :work area (float   *)
+                length of t >= 8*n1,                   if single thread,
+                length of t >= 8*n1*FFT2D_MAX_THREADS, if multi threads,
+                t is dynamically allocated, if t == NULL.
+        ip[0...*]
+               :work area for bit reversal (int *)
+                length of ip >= 2+sqrt(n)
+                (n = max(n1, n2/2))
+                ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...*]
+               :cos/sin table (float   *)
+                length of w >= max(n1/2, n2/4) + n2/4
+                w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            rdft2d(n1, n2, 1, a, t, ip, w);
+        is
+            rdft2d(n1, n2, -1, a, t, ip, w);
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                for (j2 = 0; j2 <= n2 - 1; j2++) {
+                    a[j1][j2] *= 2.0 / n1 / n2;
+                }
+            }
+        .
+
+
+-------- DCT (Discrete Cosine Transform) / Inverse of DCT --------
+    [definition]
+        <case1> IDCT (excluding scale)
+            C[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 a[j1][j2] *
+                            cos(pi*j1*(k1+1/2)/n1) *
+                            cos(pi*j2*(k2+1/2)/n2),
+                            0<=k1<n1, 0<=k2<n2
+        <case2> DCT
+            C[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 a[j1][j2] *
+                            cos(pi*(j1+1/2)*k1/n1) *
+                            cos(pi*(j2+1/2)*k2/n2),
+                            0<=k1<n1, 0<=k2<n2
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            ddct2d(n1, n2, 1, a, t, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            ddct2d(n1, n2, -1, a, t, ip, w);
+    [parameters]
+        n1     :data length (int)
+                n1 >= 2, n1 = power of 2
+        n2     :data length (int)
+                n2 >= 2, n2 = power of 2
+        a[0...n1-1][0...n2-1]
+               :input/output data (float   **)
+                output data
+                    a[k1][k2] = C[k1][k2], 0<=k1<n1, 0<=k2<n2
+        t[0...*]
+               :work area (float   *)
+                length of t >= 4*n1,                   if single thread,
+                length of t >= 4*n1*FFT2D_MAX_THREADS, if multi threads,
+                t is dynamically allocated, if t == NULL.
+        ip[0...*]
+               :work area for bit reversal (int *)
+                length of ip >= 2+sqrt(n)
+                (n = max(n1/2, n2/2))
+                ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...*]
+               :cos/sin table (float   *)
+                length of w >= max(n1*3/2, n2*3/2)
+                w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            ddct2d(n1, n2, -1, a, t, ip, w);
+        is
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                a[j1][0] *= 0.5;
+            }
+            for (j2 = 0; j2 <= n2 - 1; j2++) {
+                a[0][j2] *= 0.5;
+            }
+            ddct2d(n1, n2, 1, a, t, ip, w);
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                for (j2 = 0; j2 <= n2 - 1; j2++) {
+                    a[j1][j2] *= 4.0 / n1 / n2;
+                }
+            }
+        .
+
+
+-------- DST (Discrete Sine Transform) / Inverse of DST --------
+    [definition]
+        <case1> IDST (excluding scale)
+            S[k1][k2] = sum_j1=1^n1 sum_j2=1^n2 A[j1][j2] *
+                            sin(pi*j1*(k1+1/2)/n1) *
+                            sin(pi*j2*(k2+1/2)/n2),
+                            0<=k1<n1, 0<=k2<n2
+        <case2> DST
+            S[k1][k2] = sum_j1=0^n1-1 sum_j2=0^n2-1 a[j1][j2] *
+                            sin(pi*(j1+1/2)*k1/n1) *
+                            sin(pi*(j2+1/2)*k2/n2),
+                            0<k1<=n1, 0<k2<=n2
+    [usage]
+        <case1>
+            ip[0] = 0; // first time only
+            ddst2d(n1, n2, 1, a, t, ip, w);
+        <case2>
+            ip[0] = 0; // first time only
+            ddst2d(n1, n2, -1, a, t, ip, w);
+    [parameters]
+        n1     :data length (int)
+                n1 >= 2, n1 = power of 2
+        n2     :data length (int)
+                n2 >= 2, n2 = power of 2
+        a[0...n1-1][0...n2-1]
+               :input/output data (float   **)
+                <case1>
+                    input data
+                        a[j1][j2] = A[j1][j2], 0<j1<n1, 0<j2<n2,
+                        a[j1][0] = A[j1][n2], 0<j1<n1,
+                        a[0][j2] = A[n1][j2], 0<j2<n2,
+                        a[0][0] = A[n1][n2]
+                        (i.e. A[j1][j2] = a[j1 % n1][j2 % n2])
+                    output data
+                        a[k1][k2] = S[k1][k2], 0<=k1<n1, 0<=k2<n2
+                <case2>
+                    output data
+                        a[k1][k2] = S[k1][k2], 0<k1<n1, 0<k2<n2,
+                        a[k1][0] = S[k1][n2], 0<k1<n1,
+                        a[0][k2] = S[n1][k2], 0<k2<n2,
+                        a[0][0] = S[n1][n2]
+                        (i.e. S[k1][k2] = a[k1 % n1][k2 % n2])
+        t[0...*]
+               :work area (float   *)
+                length of t >= 4*n1,                   if single thread,
+                length of t >= 4*n1*FFT2D_MAX_THREADS, if multi threads,
+                t is dynamically allocated, if t == NULL.
+        ip[0...*]
+               :work area for bit reversal (int *)
+                length of ip >= 2+sqrt(n)
+                (n = max(n1/2, n2/2))
+                ip[0],ip[1] are pointers of the cos/sin table.
+        w[0...*]
+               :cos/sin table (float   *)
+                length of w >= max(n1*3/2, n2*3/2)
+                w[],ip[] are initialized if ip[0] == 0.
+    [remark]
+        Inverse of
+            ddst2d(n1, n2, -1, a, t, ip, w);
+        is
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                a[j1][0] *= 0.5;
+            }
+            for (j2 = 0; j2 <= n2 - 1; j2++) {
+                a[0][j2] *= 0.5;
+            }
+            ddst2d(n1, n2, 1, a, t, ip, w);
+            for (j1 = 0; j1 <= n1 - 1; j1++) {
+                for (j2 = 0; j2 <= n2 - 1; j2++) {
+                    a[j1][j2] *= 4.0 / n1 / n2;
+                }
+            }
+        .
+*/
+
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#define fft2d_alloc_error_check(p)                        \
+  {                                                       \
+    if((p) == NULL) {                                     \
+      fprintf(stderr, "fft2d memory allocation error\n"); \
+      exit(1);                                            \
+    }                                                     \
+  }
+
+#ifdef USE_FFT2D_PTHREADS
+#define USE_FFT2D_THREADS
+#ifndef FFT2D_MAX_THREADS
+#define FFT2D_MAX_THREADS 4
+#endif
+#ifndef FFT2D_THREADS_BEGIN_N
+#define FFT2D_THREADS_BEGIN_N 65536
+#endif
+#include <pthread.h>
+#define fft2d_thread_t pthread_t
+#define fft2d_thread_create(thp, func, argp)                   \
+  {                                                            \
+    if(pthread_create(thp, NULL, func, (void *)(argp)) != 0) { \
+      fprintf(stderr, "fft2d thread error\n");                 \
+      exit(1);                                                 \
+    }                                                          \
+  }
+#define fft2d_thread_wait(th)                  \
+  {                                            \
+    if(pthread_join(th, NULL) != 0) {          \
+      fprintf(stderr, "fft2d thread error\n"); \
+      exit(1);                                 \
+    }                                          \
+  }
+#endif /* USE_FFT2D_PTHREADS */
+
+#ifdef USE_FFT2D_WINTHREADS
+#define USE_FFT2D_THREADS
+#ifndef FFT2D_MAX_THREADS
+#define FFT2D_MAX_THREADS 4
+#endif
+#ifndef FFT2D_THREADS_BEGIN_N
+#define FFT2D_THREADS_BEGIN_N 131072
+#endif
+#include <windows.h>
+#define fft2d_thread_t HANDLE
+#define fft2d_thread_create(thp, func, argp)                       \
+  {                                                                \
+    DWORD thid;                                                    \
+    *(thp) = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)(func), \
+                          (LPVOID)(argp), 0, &thid);               \
+    if(*(thp) == 0) {                                              \
+      fprintf(stderr, "fft2d thread error\n");                     \
+      exit(1);                                                     \
+    }                                                              \
+  }
+#define fft2d_thread_wait(th)          \
+  {                                    \
+    WaitForSingleObject(th, INFINITE); \
+    CloseHandle(th);                   \
+  }
+#endif /* USE_FFT2D_WINTHREADS */
+
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+
+void cdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void cdft(int n, int isgn, float* a, int* ip, float* w);
+  void cdft2d_sub(
+      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
+#ifdef USE_FFT2D_THREADS
+  void xdft2d0_subth(
+      int n1, int n2, int icr, int isgn, float** a, int* ip, float* w);
+  void cdft2d_subth(
+      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, itnull, nthread, nt, i;
+
+  n = n1 << 1;
+  if (n < n2) {
+    n = n2;
+  }
+  if (n > (ip[0] << 2)) {
+    makewt(n >> 2, ip, w);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 8 * nthread * n1;
+    if (n2 == 4 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 4 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    xdft2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    for (i = 0; i < n1; i++) {
+      cdft(n2, isgn, a[i], ip, w);
+    }
+    cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+void rdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void rdft(int n, int isgn, float* a, int* ip, float* w);
+  void cdft2d_sub(
+      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
+  void rdft2d_sub(int n1, int isgn, float** a);
+#ifdef USE_FFT2D_THREADS
+  void xdft2d0_subth(
+      int n1, int n2, int icr, int isgn, float** a, int* ip, float* w);
+  void cdft2d_subth(
+      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, nw, nc, itnull, nthread, nt, i;
+
+  n = n1 << 1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n2 > (nc << 2)) {
+    nc = n2 >> 2;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 8 * nthread * n1;
+    if (n2 == 4 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 4 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    if (isgn < 0) {
+      rdft2d_sub(n1, isgn, a);
+      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+    }
+    xdft2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    if (isgn >= 0) {
+      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+      rdft2d_sub(n1, isgn, a);
+    }
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    if (isgn < 0) {
+      rdft2d_sub(n1, isgn, a);
+      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      rdft(n2, isgn, a[i], ip, w);
+    }
+    if (isgn >= 0) {
+      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+      rdft2d_sub(n1, isgn, a);
+    }
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+void rdft2dsort(int n1, int n2, int isgn, float** a)
+{
+  int n1h, i;
+  float x, y;
+
+  n1h = n1 >> 1;
+  if (isgn < 0) {
+    for (i = n1h + 1; i < n1; i++) {
+      a[i][0] = a[i][n2 + 1];
+      a[i][1] = a[i][n2];
+    }
+    a[0][1] = a[0][n2];
+    a[n1h][1] = a[n1h][n2];
+  } else {
+    for (i = n1h + 1; i < n1; i++) {
+      y = a[i][0];
+      x = a[i][1];
+      a[i][n2] = x;
+      a[i][n2 + 1] = y;
+      a[n1 - i][n2] = x;
+      a[n1 - i][n2 + 1] = -y;
+      a[i][0] = a[n1 - i][0];
+      a[i][1] = -a[n1 - i][1];
+    }
+    a[0][n2] = a[0][1];
+    a[0][n2 + 1] = 0;
+    a[0][1] = 0;
+    a[n1h][n2] = a[n1h][1];
+    a[n1h][n2 + 1] = 0;
+    a[n1h][1] = 0;
+  }
+}
+
+void ddcst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  void ddxt2d_sub(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w);
+#ifdef USE_FFT2D_THREADS
+  void ddxt2d0_subth(
+      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
+  void ddxt2d_subth(int n1,
+                    int n2,
+                    int ics,
+                    int isgn,
+                    float** a,
+                    float* t,
+                    int* ip,
+                    float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, nw, nc, itnull, nthread, nt, i;
+
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    for (i = 0; i < n1; i++) {
+      ddst(n2, isgn, a[i], ip, w);
+    }
+    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+void ddsct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  void ddxt2d_sub(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w);
+#ifdef USE_FFT2D_THREADS
+  void ddxt2d0_subth(
+      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
+  void ddxt2d_subth(int n1,
+                    int n2,
+                    int ics,
+                    int isgn,
+                    float** a,
+                    float* t,
+                    int* ip,
+                    float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, nw, nc, itnull, nthread, nt, i;
+
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    for (i = 0; i < n1; i++) {
+      ddct(n2, isgn, a[i], ip, w);
+    }
+    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+void ddct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddxt2d_sub(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w);
+#ifdef USE_FFT2D_THREADS
+  void ddxt2d0_subth(
+      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
+  void ddxt2d_subth(int n1,
+                    int n2,
+                    int ics,
+                    int isgn,
+                    float** a,
+                    float* t,
+                    int* ip,
+                    float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, nw, nc, itnull, nthread, nt, i;
+
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    for (i = 0; i < n1; i++) {
+      ddct(n2, isgn, a[i], ip, w);
+    }
+    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+void ddst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+{
+  void makewt(int nw, int* ip, float* w);
+  void makect(int nc, int* ip, float* c);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  void ddxt2d_sub(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w);
+#ifdef USE_FFT2D_THREADS
+  void ddxt2d0_subth(
+      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
+  void ddxt2d_subth(int n1,
+                    int n2,
+                    int ics,
+                    int isgn,
+                    float** a,
+                    float* t,
+                    int* ip,
+                    float* w);
+#endif /* USE_FFT2D_THREADS */
+  int n, nw, nc, itnull, nthread, nt, i;
+
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
+#ifdef USE_FFT2D_THREADS
+    nthread = FFT2D_MAX_THREADS;
+#endif /* USE_FFT2D_THREADS */
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
+    }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
+#ifdef USE_FFT2D_THREADS
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+  } else
+#endif /* USE_FFT2D_THREADS */
+  {
+    for (i = 0; i < n1; i++) {
+      ddst(n2, isgn, a[i], ip, w);
+    }
+    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
+}
+
+/* -------- child routines -------- */
+
+void cdft2d_sub(int n1,
+                int n2,
+                int isgn,
+                float** a,
+                float* t,
+                int* ip,
+                float* w)
+{
+  void cdft(int n, int isgn, float* a, int* ip, float* w);
+  int i, j;
+
+  if (n2 > 4) {
+    for (j = 0; j < n2; j += 8) {
+      for (i = 0; i < n1; i++) {
+        t[2 * i] = a[i][j];
+        t[2 * i + 1] = a[i][j + 1];
+        t[2 * n1 + 2 * i] = a[i][j + 2];
+        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+        t[4 * n1 + 2 * i] = a[i][j + 4];
+        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+        t[6 * n1 + 2 * i] = a[i][j + 6];
+        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+      }
+      cdft(2 * n1, isgn, t, ip, w);
+      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[2 * i];
+        a[i][j + 1] = t[2 * i + 1];
+        a[i][j + 2] = t[2 * n1 + 2 * i];
+        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+        a[i][j + 4] = t[4 * n1 + 2 * i];
+        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+        a[i][j + 6] = t[6 * n1 + 2 * i];
+        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+      }
+    }
+  } else if (n2 == 4) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][0];
+      t[2 * i + 1] = a[i][1];
+      t[2 * n1 + 2 * i] = a[i][2];
+      t[2 * n1 + 2 * i + 1] = a[i][3];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[2 * i];
+      a[i][1] = t[2 * i + 1];
+      a[i][2] = t[2 * n1 + 2 * i];
+      a[i][3] = t[2 * n1 + 2 * i + 1];
+    }
+  } else if (n2 == 2) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][0];
+      t[2 * i + 1] = a[i][1];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[2 * i];
+      a[i][1] = t[2 * i + 1];
+    }
+  }
+}
+
+void rdft2d_sub(int n1, int isgn, float** a)
+{
+  int n1h, i, j;
+  float xi;
+
+  n1h = n1 >> 1;
+  if (isgn < 0) {
+    for (i = 1; i < n1h; i++) {
+      j = n1 - i;
+      xi = a[i][0] - a[j][0];
+      a[i][0] += a[j][0];
+      a[j][0] = xi;
+      xi = a[j][1] - a[i][1];
+      a[i][1] += a[j][1];
+      a[j][1] = xi;
+    }
+  } else {
+    for (i = 1; i < n1h; i++) {
+      j = n1 - i;
+      a[j][0] = 0.5 * (a[i][0] - a[j][0]);
+      a[i][0] -= a[j][0];
+      a[j][1] = 0.5 * (a[i][1] + a[j][1]);
+      a[i][1] -= a[j][1];
+    }
+  }
+}
+
+void ddxt2d_sub(int n1,
+                int n2,
+                int ics,
+                int isgn,
+                float** a,
+                float* t,
+                int* ip,
+                float* w)
+{
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  int i, j;
+
+  if (n2 > 2) {
+    for (j = 0; j < n2; j += 4) {
+      for (i = 0; i < n1; i++) {
+        t[i] = a[i][j];
+        t[n1 + i] = a[i][j + 1];
+        t[2 * n1 + i] = a[i][j + 2];
+        t[3 * n1 + i] = a[i][j + 3];
+      }
+      if (ics == 0) {
+        ddct(n1, isgn, t, ip, w);
+        ddct(n1, isgn, &t[n1], ip, w);
+        ddct(n1, isgn, &t[2 * n1], ip, w);
+        ddct(n1, isgn, &t[3 * n1], ip, w);
+      } else {
+        ddst(n1, isgn, t, ip, w);
+        ddst(n1, isgn, &t[n1], ip, w);
+        ddst(n1, isgn, &t[2 * n1], ip, w);
+        ddst(n1, isgn, &t[3 * n1], ip, w);
+      }
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[i];
+        a[i][j + 1] = t[n1 + i];
+        a[i][j + 2] = t[2 * n1 + i];
+        a[i][j + 3] = t[3 * n1 + i];
+      }
+    }
+  } else if (n2 == 2) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][0];
+      t[n1 + i] = a[i][1];
+    }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+      ddct(n1, isgn, &t[n1], ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+      ddst(n1, isgn, &t[n1], ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[i];
+      a[i][1] = t[n1 + i];
+    }
+  }
+}
+
+#ifdef USE_FFT2D_THREADS
+struct fft2d_arg_st
+{
+  int nthread;
+  int n0;
+  int n1;
+  int n2;
+  int ic;
+  int isgn;
+  float** a;
+  float* t;
+  int* ip;
+  float* w;
+};
+typedef struct fft2d_arg_st fft2d_arg_t;
+
+void xdft2d0_subth(int n1,
+                   int n2,
+                   int icr,
+                   int isgn,
+                   float** a,
+                   int* ip,
+                   float* w)
+{
+  void* xdft2d0_th(void* p);
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, i;
+
+  nthread = FFT2D_MAX_THREADS;
+  if (nthread > n1) {
+    nthread = n1;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = icr;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], xdft2d0_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
+}
+
+void cdft2d_subth(int n1,
+                  int n2,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w)
+{
+  void* cdft2d_th(void* p);
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, nt, i;
+
+  nthread = FFT2D_MAX_THREADS;
+  nt = 8 * n1;
+  if (n2 == 4 * FFT2D_MAX_THREADS) {
+    nt >>= 1;
+  } else if (n2 < 4 * FFT2D_MAX_THREADS) {
+    nthread = n2 >> 1;
+    nt >>= 2;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].t = &t[nt * i];
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], cdft2d_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
+}
+
+void ddxt2d0_subth(int n1,
+                   int n2,
+                   int ics,
+                   int isgn,
+                   float** a,
+                   int* ip,
+                   float* w)
+{
+  void* ddxt2d0_th(void* p);
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, i;
+
+  nthread = FFT2D_MAX_THREADS;
+  if (nthread > n1) {
+    nthread = n1;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = ics;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], ddxt2d0_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
+}
+
+void ddxt2d_subth(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w)
+{
+  void* ddxt2d_th(void* p);
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, nt, i;
+
+  nthread = FFT2D_MAX_THREADS;
+  nt = 4 * n1;
+  if (n2 == 2 * FFT2D_MAX_THREADS) {
+    nt >>= 1;
+  } else if (n2 < 2 * FFT2D_MAX_THREADS) {
+    nthread = n2;
+    nt >>= 2;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = ics;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].t = &t[nt * i];
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], ddxt2d_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
+}
+
+void* xdft2d0_th(void* p)
+{
+  void cdft(int n, int isgn, float* a, int* ip, float* w);
+  void rdft(int n, int isgn, float* a, int* ip, float* w);
+  int nthread, n0, n1, n2, icr, isgn, *ip, i;
+  float **a, *w;
+
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  icr = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (icr == 0) {
+    for (i = n0; i < n1; i += nthread) {
+      cdft(n2, isgn, a[i], ip, w);
+    }
+  } else {
+    for (i = n0; i < n1; i += nthread) {
+      rdft(n2, isgn, a[i], ip, w);
+    }
+  }
+  return (void*) 0;
+}
+
+void* cdft2d_th(void* p)
+{
+  void cdft(int n, int isgn, float* a, int* ip, float* w);
+  int nthread, n0, n1, n2, isgn, *ip, i, j;
+  float **a, *t, *w;
+
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  t = ((fft2d_arg_t*) p)->t;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (n2 > 4 * nthread) {
+    for (j = 8 * n0; j < n2; j += 8 * nthread) {
+      for (i = 0; i < n1; i++) {
+        t[2 * i] = a[i][j];
+        t[2 * i + 1] = a[i][j + 1];
+        t[2 * n1 + 2 * i] = a[i][j + 2];
+        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+        t[4 * n1 + 2 * i] = a[i][j + 4];
+        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+        t[6 * n1 + 2 * i] = a[i][j + 6];
+        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+      }
+      cdft(2 * n1, isgn, t, ip, w);
+      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[2 * i];
+        a[i][j + 1] = t[2 * i + 1];
+        a[i][j + 2] = t[2 * n1 + 2 * i];
+        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+        a[i][j + 4] = t[4 * n1 + 2 * i];
+        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+        a[i][j + 6] = t[6 * n1 + 2 * i];
+        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+      }
+    }
+  } else if (n2 == 4 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][4 * n0];
+      t[2 * i + 1] = a[i][4 * n0 + 1];
+      t[2 * n1 + 2 * i] = a[i][4 * n0 + 2];
+      t[2 * n1 + 2 * i + 1] = a[i][4 * n0 + 3];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][4 * n0] = t[2 * i];
+      a[i][4 * n0 + 1] = t[2 * i + 1];
+      a[i][4 * n0 + 2] = t[2 * n1 + 2 * i];
+      a[i][4 * n0 + 3] = t[2 * n1 + 2 * i + 1];
+    }
+  } else if (n2 == 2 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][2 * n0];
+      t[2 * i + 1] = a[i][2 * n0 + 1];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][2 * n0] = t[2 * i];
+      a[i][2 * n0 + 1] = t[2 * i + 1];
+    }
+  }
+  return (void*) 0;
+}
+
+void* ddxt2d0_th(void* p)
+{
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  int nthread, n0, n1, n2, ics, isgn, *ip, i;
+  float **a, *w;
+
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  ics = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (ics == 0) {
+    for (i = n0; i < n1; i += nthread) {
+      ddct(n2, isgn, a[i], ip, w);
+    }
+  } else {
+    for (i = n0; i < n1; i += nthread) {
+      ddst(n2, isgn, a[i], ip, w);
+    }
+  }
+  return (void*) 0;
+}
+
+void* ddxt2d_th(void* p)
+{
+  void ddct(int n, int isgn, float* a, int* ip, float* w);
+  void ddst(int n, int isgn, float* a, int* ip, float* w);
+  int nthread, n0, n1, n2, ics, isgn, *ip, i, j;
+  float **a, *t, *w;
+
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  ics = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  t = ((fft2d_arg_t*) p)->t;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (n2 > 2 * nthread) {
+    for (j = 4 * n0; j < n2; j += 4 * nthread) {
+      for (i = 0; i < n1; i++) {
+        t[i] = a[i][j];
+        t[n1 + i] = a[i][j + 1];
+        t[2 * n1 + i] = a[i][j + 2];
+        t[3 * n1 + i] = a[i][j + 3];
+      }
+      if (ics == 0) {
+        ddct(n1, isgn, t, ip, w);
+        ddct(n1, isgn, &t[n1], ip, w);
+        ddct(n1, isgn, &t[2 * n1], ip, w);
+        ddct(n1, isgn, &t[3 * n1], ip, w);
+      } else {
+        ddst(n1, isgn, t, ip, w);
+        ddst(n1, isgn, &t[n1], ip, w);
+        ddst(n1, isgn, &t[2 * n1], ip, w);
+        ddst(n1, isgn, &t[3 * n1], ip, w);
+      }
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[i];
+        a[i][j + 1] = t[n1 + i];
+        a[i][j + 2] = t[2 * n1 + i];
+        a[i][j + 3] = t[3 * n1 + i];
+      }
+    }
+  } else if (n2 == 2 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][2 * n0];
+      t[n1 + i] = a[i][2 * n0 + 1];
+    }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+      ddct(n1, isgn, &t[n1], ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+      ddst(n1, isgn, &t[n1], ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][2 * n0] = t[i];
+      a[i][2 * n0 + 1] = t[n1 + i];
+    }
+  } else if (n2 == nthread) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][n0];
+    }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][n0] = t[i];
+    }
+  }
+  return (void*) 0;
+}
+#endif /* USE_FFT2D_THREADS */
+
+NEXTPNR_NAMESPACE_END
diff --git a/3rdparty/oourafft/readme.txt b/3rdparty/oourafft/readme.txt
new file mode 100644
index 0000000000..145a081bd2
--- /dev/null
+++ b/3rdparty/oourafft/readme.txt
@@ -0,0 +1,167 @@
+General Purpose FFT (Fast Fourier/Cosine/Sine Transform) Package
+
+Description:
+    A package to calculate Discrete Fourier/Cosine/Sine Transforms of 
+    1-dimensional sequences of length 2^N.
+
+Files:
+    fft4g.c    : FFT Package in C       - Fast Version   I   (radix 4,2)
+    fft4g.f    : FFT Package in Fortran - Fast Version   I   (radix 4,2)
+    fft4g_h.c  : FFT Package in C       - Simple Version I   (radix 4,2)
+    fft8g.c    : FFT Package in C       - Fast Version   II  (radix 8,4,2)
+    fft8g.f    : FFT Package in Fortran - Fast Version   II  (radix 8,4,2)
+    fft8g_h.c  : FFT Package in C       - Simple Version II  (radix 8,4,2)
+    fftsg.c    : FFT Package in C       - Fast Version   III (Split-Radix)
+    fftsg.f    : FFT Package in Fortran - Fast Version   III (Split-Radix)
+    fftsg_h.c  : FFT Package in C       - Simple Version III (Split-Radix)
+    readme.txt : Readme File
+    sample1/   : Test Directory
+        Makefile    : for gcc, cc
+        Makefile.f77: for Fortran
+        testxg.c    : Test Program for "fft*g.c"
+        testxg.f    : Test Program for "fft*g.f"
+        testxg_h.c  : Test Program for "fft*g_h.c"
+    sample2/   : Benchmark Directory
+        Makefile    : for gcc, cc
+        Makefile.pth: POSIX Thread version
+        pi_fft.c    : PI(= 3.1415926535897932384626...) Calculation Program
+                      for a Benchmark Test for "fft*g.c"
+
+Difference of the Files:
+    C and Fortran versions are equal and 
+    the same routines are in each version.
+    "fft4g*.*" are optimized for most machines.
+    "fft8g*.*" are fast on the UltraSPARC.
+    "fftsg*.*" are optimized for the machines that 
+    have the multi-level (L1,L2,etc) cache.
+    The simple versions "fft*g_h.c" use no work area, but 
+    the fast versions "fft*g.*" use work areas.
+    The fast versions "fft*g.*" have the same specification.
+
+Routines in the Package:
+    cdft: Complex Discrete Fourier Transform
+    rdft: Real Discrete Fourier Transform
+    ddct: Discrete Cosine Transform
+    ddst: Discrete Sine Transform
+    dfct: Cosine Transform of RDFT (Real Symmetric DFT)
+    dfst: Sine Transform of RDFT (Real Anti-symmetric DFT)
+
+Usage:
+    Please refer to the comments in the "fft**.*" file which 
+    you want to use. Brief explanations are in the block 
+    comments of each package. The examples are also given in 
+    the test programs.
+
+Method:
+    -------- cdft --------
+    fft4g*.*, fft8g*.*:
+        A method of in-place, radix 2^M, Sande-Tukey (decimation in 
+        frequency). Index of the butterfly loop is in bit 
+        reverse order to keep continuous memory access.
+    fftsg*.*:
+        A method of in-place, Split-Radix, recursive fast 
+        algorithm.
+    -------- rdft --------
+    A method with a following butterfly operation appended to "cdft".
+    In forward transform :
+        A[k] = sum_j=0^n-1 a[j]*W(n)^(j*k), 0<=k<=n/2, 
+            W(n) = exp(2*pi*i/n), 
+    this routine makes an array x[] :
+        x[j] = a[2*j] + i*a[2*j+1], 0<=j<n/2
+    and calls "cdft" of length n/2 :
+        X[k] = sum_j=0^n/2-1 x[j] * W(n/2)^(j*k), 0<=k<n.
+    The result A[k] are :
+        A[k]     = X[k]     - (1+i*W(n)^k)/2 * (X[k]-conjg(X[n/2-k])), 
+        A[n/2-k] = X[n/2-k] + 
+                        conjg((1+i*W(n)^k)/2 * (X[k]-conjg(X[n/2-k]))), 
+            0<=k<=n/2
+        (notes: conjg() is a complex conjugate, X[n/2]=X[0]).
+    -------- ddct --------
+    A method with a following butterfly operation appended to "rdft".
+    In backward transform :
+        C[k] = sum_j=0^n-1 a[j]*cos(pi*j*(k+1/2)/n), 0<=k<n, 
+    this routine makes an array r[] :
+        r[0] = a[0], 
+        r[j]   = Re((a[j] - i*a[n-j]) * W(4*n)^j*(1+i)/2), 
+        r[n-j] = Im((a[j] - i*a[n-j]) * W(4*n)^j*(1+i)/2), 
+            0<j<=n/2
+    and calls "rdft" of length n :
+        A[k] = sum_j=0^n-1 r[j]*W(n)^(j*k), 0<=k<=n/2, 
+            W(n) = exp(2*pi*i/n).
+    The result C[k] are :
+        C[2*k]   =  Re(A[k] * (1-i)), 
+        C[2*k-1] = -Im(A[k] * (1-i)).
+    -------- ddst --------
+    A method with a following butterfly operation appended to "rdft".
+    In backward transform :
+        S[k] = sum_j=1^n A[j]*sin(pi*j*(k+1/2)/n), 0<=k<n, 
+    this routine makes an array r[] :
+        r[0] = a[0], 
+        r[j]   = Im((a[n-j] - i*a[j]) * W(4*n)^j*(1+i)/2), 
+        r[n-j] = Re((a[n-j] - i*a[j]) * W(4*n)^j*(1+i)/2), 
+            0<j<=n/2
+    and calls "rdft" of length n :
+        A[k] = sum_j=0^n-1 r[j]*W(n)^(j*k), 0<=k<=n/2, 
+            W(n) = exp(2*pi*i/n).
+    The result S[k] are :
+        S[2*k]   =  Re(A[k] * (1+i)), 
+        S[2*k-1] = -Im(A[k] * (1+i)).
+    -------- dfct --------
+    A method to split into "dfct" and "ddct" of half length.
+    The transform :
+        C[k] = sum_j=0^n a[j]*cos(pi*j*k/n), 0<=k<=n
+    is divided into :
+        C[2*k]   = sum'_j=0^n/2  (a[j]+a[n-j])*cos(pi*j*k/(n/2)), 
+        C[2*k+1] = sum_j=0^n/2-1 (a[j]-a[n-j])*cos(pi*j*(k+1/2)/(n/2))
+        (sum' is a summation whose last term multiplies 1/2).
+    This routine uses "ddct" recursively.
+    To keep the in-place operation, the data in fft*g_h.*
+    are sorted in bit reversal order.
+    -------- dfst --------
+    A method to split into "dfst" and "ddst" of half length.
+    The transform :
+        S[k] = sum_j=1^n-1 a[j]*sin(pi*j*k/n), 0<k<n
+    is divided into :
+        S[2*k]   = sum_j=1^n/2-1 (a[j]-a[n-j])*sin(pi*j*k/(n/2)), 
+        S[2*k+1] = sum'_j=1^n/2  (a[j]+a[n-j])*sin(pi*j*(k+1/2)/(n/2))
+        (sum' is a summation whose last term multiplies 1/2).
+    This routine uses "ddst" recursively.
+    To keep the in-place operation, the data in fft*g_h.*
+    are sorted in bit reversal order.
+
+Reference:
+    * Masatake MORI, Makoto NATORI, Tatuo TORII: Suchikeisan, 
+      Iwanamikouzajyouhoukagaku18, Iwanami, 1982 (Japanese)
+    * Henri J. Nussbaumer: Fast Fourier Transform and Convolution 
+      Algorithms, Springer Verlag, 1982
+    * C. S. Burrus, Notes on the FFT (with large FFT paper list)
+      http://www-dsp.rice.edu/research/fft/fftnote.asc
+
+Copyright:
+    Copyright(C) 1996-2001 Takuya OOURA
+    email: ooura@mmm.t.u-tokyo.ac.jp
+    download: http://momonga.t.u-tokyo.ac.jp/~ooura/fft.html
+    You may use, copy, modify this code for any purpose and 
+    without fee. You may distribute this ORIGINAL package.
+
+History:
+    ...
+    Dec. 1995  : Edit the General Purpose FFT
+    Mar. 1996  : Change the specification
+    Jun. 1996  : Change the method of trigonometric function table
+    Sep. 1996  : Modify the documents
+    Feb. 1997  : Change the butterfly loops
+    Dec. 1997  : Modify the documents
+    Dec. 1997  : Add "fft4g.*"
+    Jul. 1998  : Fix some bugs in the documents
+    Jul. 1998  : Add "fft8g.*" and delete "fft4f.*"
+    Jul. 1998  : Add a benchmark program "pi_fft.c"
+    Jul. 1999  : Add a simple version "fft*g_h.c"
+    Jul. 1999  : Add a Split-Radix FFT package "fftsg*.c"
+    Sep. 1999  : Reduce the memory operation (minor optimization)
+    Oct. 1999  : Change the butterfly structure of "fftsg*.c"
+    Oct. 1999  : Save the code size
+    Sep. 2001  : Add "fftsg.f"
+    Sep. 2001  : Add Pthread & Win32thread routines to "fftsg*.c"
+    Dec. 2006  : Fix a minor bug in "fftsg.f"
+
diff --git a/3rdparty/oourafft/readme2d.txt b/3rdparty/oourafft/readme2d.txt
new file mode 100644
index 0000000000..7cc4dfa0f9
--- /dev/null
+++ b/3rdparty/oourafft/readme2d.txt
@@ -0,0 +1,77 @@
+General Purpose 2D,3D FFT (Fast Fourier Transform) Package
+
+Files
+    alloc.c    : 2D-array Allocation
+    alloc.h    : 2D-array Allocation
+    fft4f2d.c  : 2D FFT Package in C       - Version I (radix 4, 2)
+    fft4f2d.f  : 2D FFT Package in Fortran - Version I (radix 4, 2)
+    fftsg.c    : 1D FFT Package in C       - Fast Version (Split-Radix)
+    fftsg.f    : 1D FFT Package in Fortran - Fast Version (Split-Radix)
+    fftsg2d.c  : 2D FFT Package in C       - Version II (Split-Radix)
+    fftsg2d.f  : 2D FFT Package in Fortran - Version II (Split-Radix)
+    fftsg3d.c  : 3D FFT Package in C       - Version II (Split-Radix)
+    fftsg3d.f  : 3D FFT Package in Fortran - Version II (Split-Radix)
+    shrtdct.c  : 8x8, 16x16 DCT Package
+    sample2d/
+        Makefile    : for gcc, cc
+        Makefile.f77: for Fortran
+        Makefile.pth: Pthread version
+        fft4f2dt.c  : Test Program for "fft4f2d.c"
+        fft4f2dt.f  : Test Program for "fft4f2d.f"
+        fftsg2dt.c  : Test Program for "fftsg2d.c"
+        fftsg2dt.f  : Test Program for "fftsg2d.f"
+        fftsg3dt.c  : Test Program for "fftsg3d.c"
+        fftsg3dt.f  : Test Program for "fftsg3d.f"
+        shrtdctt.c  : Test Program for "shrtdct.c"
+
+Difference of Files
+    C and Fortran versions are equal and 
+    the same routines are in each version.
+    ---- Difference between "fft4f2d.*" and "fftsg2d.*" ----
+    "fft4f2d.*" are optimized for the old machines that 
+    don't have the large size CPU cache.
+    "fftsg2d.*", "fftsg3d.*" use 1D FFT routines in "fftsg.*".
+    "fftsg2d.*", "fftsg3d.*" are optimized for the machines that 
+    have the multi-level (L1,L2,etc) cache.
+
+Routines in the Package
+    in fft4f2d.*, fftsg2d.*
+        cdft2d: 2-dim Complex Discrete Fourier Transform
+        rdft2d: 2-dim Real Discrete Fourier Transform
+        ddct2d: 2-dim Discrete Cosine Transform
+        ddst2d: 2-dim Discrete Sine Transform
+        rdft2dsort: rdft2d input/output ordering (fftsg2d.*)
+    in fftsg3d.*
+        cdft3d: 3-dim Complex Discrete Fourier Transform
+        rdft3d: 3-dim Real Discrete Fourier Transform
+        ddct3d: 3-dim Discrete Cosine Transform
+        ddst3d: 3-dim Discrete Sine Transform
+        rdft3dsort: rdft3d input/output ordering
+    in fftsg.*
+        cdft: 1-dim Complex Discrete Fourier Transform
+        rdft: 1-dim Real Discrete Fourier Transform
+        ddct: 1-dim Discrete Cosine Transform
+        ddst: 1-dim Discrete Sine Transform
+        dfct: 1-dim Real Symmetric DFT
+        dfst: 1-dim Real Anti-symmetric DFT
+        (these routines are called by fftsg2d.*, fftsg3d.*)
+    in shrtdct.c
+        ddct8x8s  : Normalized 8x8 DCT
+        ddct16x16s: Normalized 16x16 DCT
+        (faster than ddct2d())
+
+Usage
+    Brief explanations are in block comments of each packages.
+    The examples are given in the test programs.
+
+Copyright
+    Copyright(C) 1997,2001 Takuya OOURA (email: ooura@kurims.kyoto-u.ac.jp).
+    You may use, copy, modify this code for any purpose and 
+    without fee. You may distribute this ORIGINAL package.
+
+History
+    ...
+    Nov. 2001  : Add 3D-FFT routines
+    Dec. 2006  : Fix a documentation bug in "fftsg3d.*"
+    Dec. 2006  : Fix a minor bug in "fftsg.f"
+
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 09eb818730..adef332fb9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -235,7 +235,7 @@ if (NOT DEFINED PYBIND11_INCLUDE_DIR)
     set(PYBIND11_INCLUDE_DIR "3rdparty/pybind11/include")
 endif()
 
-include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/ ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${Python3_INCLUDE_DIRS})
+include_directories(common/kernel/ common/place/ common/route/ json/ frontend/ 3rdparty/json11/  3rdparty/oourafft ${PYBIND11_INCLUDE_DIR} ${Boost_INCLUDE_DIRS} ${Python3_INCLUDE_DIRS})
 
 find_package (Eigen3 REQUIRED NO_MODULE)
 link_libraries(Eigen3::Eigen)
@@ -246,9 +246,10 @@ aux_source_directory(common/route/ ROUTE_SRC_FILES)
 
 aux_source_directory(json/ JSON_PARSER_FILES)
 aux_source_directory(3rdparty/json11 EXT_JSON11_FILES)
+aux_source_directory(3rdparty/oourafft EXT_OOURAFFT_FILES)
 aux_source_directory(frontend/ FRONTEND_FILES)
 
-set(COMMON_FILES ${KERNEL_SRC_FILES} ${PLACE_SRC_FILES} ${ROUTE_SRC_FILES} ${EXT_JSON11_FILES} ${JSON_PARSER_FILES} ${FRONTEND_FILES})
+set(COMMON_FILES ${KERNEL_SRC_FILES} ${PLACE_SRC_FILES} ${ROUTE_SRC_FILES} ${EXT_JSON11_FILES} ${EXT_OOURAFFT_FILES} ${JSON_PARSER_FILES} ${FRONTEND_FILES})
 if( NOT CMAKE_BUILD_TYPE )
     set(CMAKE_BUILD_TYPE Release)
 endif()
diff --git a/common/kernel/array2d.h b/common/kernel/array2d.h
new file mode 100644
index 0000000000..bb1a150db6
--- /dev/null
+++ b/common/kernel/array2d.h
@@ -0,0 +1,148 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021-22  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ARRAY2D_H
+#define ARRAY2D_H
+
+#include <algorithm>
+#include <fstream>
+#include <limits>
+#include <string>
+#include <type_traits>
+#include <vector>
+
+#include "nextpnr_assertions.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+template <typename T> class array2d
+{
+  public:
+    array2d() : m_width(0), m_height(0), m_size(0), data(nullptr){};
+    array2d(int width, int height) : m_width(width), m_height(height), m_size(width * height)
+    {
+        data = new T[m_width * m_height]();
+    }
+    array2d(int width, int height, const T &init) : m_width(width), m_height(height), m_size(width * height)
+    {
+        data = new T[m_width * m_height];
+        std::fill(data, data + (m_width * m_height), init);
+    }
+    array2d(const array2d &other) : m_width(other.m_width), m_height(other.m_height), m_size(other.m_size)
+    {
+        data = new T[m_size]();
+        if (m_size > 0)
+            std::copy(other.data, other.data + (m_width * m_height), data);
+    }
+    array2d(array2d &&other) noexcept : m_width(other.m_width), m_height(other.m_height), m_size(other.m_size)
+    {
+        data = other.data;
+        other.data = nullptr;
+        other.m_size = 0;
+    }
+    void reset(int new_width, int new_height, const T &init = {})
+    {
+        if ((new_width * new_height) > m_size) {
+            delete[] data;
+            m_size = new_width * new_height;
+            data = new T[m_size];
+        }
+        m_width = new_width;
+        m_height = new_height;
+        std::fill(data, data + (m_width * m_height), init);
+    }
+
+    int width() const { return m_width; }
+    int height() const { return m_height; }
+    T &at(int x, int y)
+    {
+        NPNR_ASSERT(x >= 0 && x < m_width);
+        NPNR_ASSERT(y >= 0 && y < m_height);
+        return data[y * m_width + x];
+    }
+    T &at(const Loc &l) { return at(l.x, l.y); }
+    const T &at(int x, int y) const
+    {
+        NPNR_ASSERT(x >= 0 && x < m_width);
+        NPNR_ASSERT(y >= 0 && y < m_height);
+        return data[y * m_width + x];
+    }
+    const T &at(const Loc &l) const { return at(l.x, l.y); }
+    ~array2d() { delete[] data; }
+    struct entry
+    {
+        entry(int x, int y, T &value) : x(x), y(y), value(value){};
+        int x, y;
+        T &value;
+    };
+    struct iterator
+    {
+      public:
+        entry operator*() { return {x, y, base->at(x, y)}; }
+        inline iterator operator++()
+        {
+            ++x;
+            if (x >= base->width()) {
+                x = 0;
+                ++y;
+            }
+            return *this;
+        }
+        inline iterator operator++(int)
+        {
+            iterator prior(x, y, base);
+            ++x;
+            if (x >= base->width()) {
+                x = 0;
+                ++y;
+            }
+            return prior;
+        }
+        inline bool operator!=(const iterator &other) const { return other.x != x || other.y != y; }
+        inline bool operator==(const iterator &other) const { return other.x == x && other.y == y; }
+
+      private:
+        iterator(int x, int y, array2d<T> &base) : x(x), y(y), base(&base){};
+        int x, y;
+        array2d<T> *base;
+        friend class array2d;
+    };
+    iterator begin() { return {0, 0, *this}; }
+    iterator end() { return {0, m_height, *this}; }
+
+    void write_csv(const std::string &filename) const
+    {
+        std::ofstream out(filename);
+        NPNR_ASSERT(out);
+        for (int y = 0; y < m_height; y++) {
+            for (int x = 0; x < m_width; x++) {
+                out << at(x, y) << ",";
+            }
+            out << std::endl;
+        }
+    }
+
+  private:
+    int m_width, m_height, m_size;
+    T *data;
+};
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/common/kernel/deterministic_rng.h b/common/kernel/deterministic_rng.h
index 3aab5a4933..73a9ef784c 100644
--- a/common/kernel/deterministic_rng.h
+++ b/common/kernel/deterministic_rng.h
@@ -72,6 +72,8 @@ struct DeterministicRNG
         }
     }
 
+    float rngf(float n) { return float(rng64() & 0x3fffffff) * (n / float(0x3fffffff)); }
+
     void rngseed(uint64_t seed)
     {
         rngstate = seed ? seed : 0x3141592653589793;
diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
new file mode 100644
index 0000000000..3e105e4708
--- /dev/null
+++ b/common/place/placer_static.cc
@@ -0,0 +1,1296 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "placer_static.h"
+#include "static_util.h"
+
+#include <boost/optional.hpp>
+#include <chrono>
+#include <deque>
+#include <fstream>
+#include <numeric>
+#include <queue>
+#include <tuple>
+#include "array2d.h"
+#include "fast_bels.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "parallel_refine.h"
+#include "place_common.h"
+#include "placer1.h"
+#include "scope_lock.h"
+#include "timing.h"
+#include "util.h"
+
+#include "fftsg.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+using namespace StaticUtil;
+
+namespace {
+
+struct PlacerGroup
+{
+    int total_bels = 0;
+    double concrete_area = 0;
+    double dark_area = 0;
+    double total_area = 0;
+    array2d<float> loc_area;
+
+    float overlap = 0;
+
+    array2d<double> conc_density; // excludes fillers and dark nodes
+    array2d<double> density;
+    // FFT related data (TODO: should these be per group?)
+    FFTArray density_fft;
+    FFTArray electro_phi;
+    FFTArray electro_fx, electro_fy;
+};
+
+// Could be an actual concrete netlist cell; or just a spacer
+struct MoveCell
+{
+    StaticRect rect;
+    // TODO: multiple contiguous vectors is probably faster than an array of structs, but also messier
+    RealPair pos, ref_pos, last_pos, last_ref_pos;
+    RealPair ref_wl_grad, wl_grad, last_wl_grad;
+    RealPair ref_dens_grad, dens_grad, last_dens_grad;
+    RealPair ref_total_grad, total_grad, last_total_grad;
+    int32_t pin_count;
+    int16_t group;
+    int16_t bx, by; // bins
+    bool is_fixed : 1;
+    bool is_spacer : 1;
+    bool is_dark : 1;
+};
+
+// Extra data for cells that aren't spacers
+struct ConcreteCell
+{
+    CellInfo *base_cell;
+    // When cells are macros; we split them up into chunks
+    // based on dx/dy location
+    int32_t macro_idx = -1;
+    int16_t chunk_dx = 0, chunk_dy = 0;
+};
+
+struct ClusterGroupKey
+{
+    ClusterGroupKey(int dx = 0, int dy = 0, int group = -1) : dx(dx), dy(dy), group(group){};
+    bool operator==(const ClusterGroupKey &other) const
+    {
+        return dx == other.dx && dy == other.dy && group == other.group;
+    }
+    unsigned hash() const { return mkhash(mkhash(dx, dy), group); }
+    int16_t dx, dy, group;
+};
+
+struct PlacerMacro
+{
+    CellInfo *root;
+    std::vector<int32_t> conc_cells;
+    dict<ClusterGroupKey, std::vector<CellInfo *>> cells;
+};
+
+struct PlacerBin
+{
+    float density;
+    // ...
+};
+
+struct PlacerPort
+{
+    // for wirelength data
+    static constexpr float invalid = std::numeric_limits<float>::lowest();
+
+    PortRef ref;
+    RealPair max_exp{invalid, invalid};
+    RealPair min_exp{invalid, invalid};
+    bool has_max_exp(Axis axis) const { return max_exp.at(axis) != invalid; }
+    bool has_min_exp(Axis axis) const { return min_exp.at(axis) != invalid; }
+};
+
+struct PlacerNet
+{
+    NetInfo *ni;
+    bool skip = false;
+    RealPair b1, b0; // real bounding box
+    RealPair min_exp, x_min_exp;
+    RealPair max_exp, x_max_exp;
+    RealPair wa_wl;
+    // lines up with user indexes; plus one for driver
+    std::vector<PlacerPort> ports;
+    int hpwl() { return (b1.x - b0.x) + (b1.y - b0.y); }
+};
+
+class StaticPlacer
+{
+    Context *ctx;
+    PlacerStaticCfg cfg;
+
+    std::vector<MoveCell> mcells;
+    std::vector<ConcreteCell> ccells;
+    std::vector<PlacerMacro> macros;
+    std::vector<PlacerGroup> groups;
+    std::vector<PlacerNet> nets;
+    idict<ClusterId> cluster2idx;
+
+    FastBels fast_bels;
+    TimingAnalyser tmg;
+
+    int width, height;
+    int iter = 0;
+    bool fft_debug = false;
+
+    // legalisation queue
+    std::priority_queue<std::pair<int, IdString>> to_legalise;
+
+    void prepare_cells()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            ci->udata = -1;
+            // process legacy-ish bel attributes
+            if (ci->attrs.count(ctx->id("BEL")) && ci->bel == BelId()) {
+                std::string loc_name = ci->attrs.at(ctx->id("BEL")).as_string();
+                BelId bel = ctx->getBelByNameStr(loc_name);
+                NPNR_ASSERT(ctx->isValidBelForCellType(ci->type, bel));
+                NPNR_ASSERT(ctx->checkBelAvail(bel));
+                ctx->bindBel(bel, ci, STRENGTH_USER);
+            }
+        }
+    }
+
+    bool lookup_group(IdString type, int &group, StaticRect &rect)
+    {
+        for (size_t i = 0; i < cfg.cell_groups.size(); i++) {
+            const auto &g = cfg.cell_groups.at(i);
+            if (g.cell_area.count(type)) {
+                group = i;
+                rect = g.cell_area.at(type);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    void init_bels()
+    {
+        log_info("⌁ initialising bels...\n");
+        width = 0;
+        height = 0;
+        for (auto bel : ctx->getBels()) {
+            Loc loc = ctx->getBelLocation(bel);
+            width = std::max(width, loc.x + 1);
+            height = std::max(height, loc.y + 1);
+        }
+        dict<IdString, int> beltype2group;
+        for (int i = 0; i < int(groups.size()); i++) {
+            groups.at(i).loc_area.reset(width, height);
+            for (const auto &bel_type : cfg.cell_groups.at(i).cell_area)
+                beltype2group[bel_type.first] = i;
+        }
+        for (auto bel : ctx->getBels()) {
+            Loc loc = ctx->getBelLocation(bel);
+            IdString type = ctx->getBelType(bel);
+            auto fnd = beltype2group.find(type);
+            if (fnd == beltype2group.end())
+                continue;
+            auto size = cfg.cell_groups.at(fnd->second).bel_area.at(type); // TODO: do we care about dimensions too
+            auto &group = groups.at(fnd->second);
+            for (int dy = 0; dy <= int(size.h); dy++) {
+                for (int dx = 0; dx <= int(size.w); dx++) {
+                    float h = (dy == int(size.h)) ? (size.h - int(size.h)) : 1;
+                    float w = (dx == int(size.w)) ? (size.w - int(size.w)) : 1;
+                    group.loc_area.at(loc.x + dx, loc.y + dy) += w * h;
+                }
+            }
+            group.total_area += size.area();
+            group.total_bels += 1;
+        }
+    }
+
+    void init_nets()
+    {
+        nets.reserve(ctx->nets.size());
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            ni->udata = nets.size();
+            nets.emplace_back();
+
+            auto &nd = nets.back();
+            nd.ni = ni;
+            nd.skip = (ni->driver.cell == nullptr);    // (or global buffer?)
+            nd.ports.resize(ni->users.capacity() + 1); // +1 for the driver
+            nd.ports.back().ref = ni->driver;
+            for (auto usr : ni->users.enumerate()) {
+                nd.ports.at(usr.index.idx()).ref = usr.value;
+            }
+        }
+    }
+
+    int add_cell(StaticRect rect, int group, RealPair pos, CellInfo *ci = nullptr)
+    {
+        int idx = mcells.size();
+        mcells.emplace_back();
+        auto &m = mcells.back();
+        m.rect = rect;
+        m.group = group;
+        m.pos = pos;
+        if (ci) {
+            // Is a concrete cell (might be a macro, in which case ci is just one of them...)
+            // Can't add concrete cells once we have spacers (we define it such that indices line up between mcells and
+            // ccells; spacer cells only exist in mcells)
+            NPNR_ASSERT(idx == int(ccells.size()));
+            ccells.emplace_back();
+            auto &c = ccells.back();
+            c.base_cell = ci;
+            groups.at(group).concrete_area += rect.area();
+        } else {
+            // Is a spacer cell
+            m.is_spacer = true;
+        }
+        return idx;
+    }
+
+    const float pi = 3.141592653589793f;
+
+    RealPair rand_loc()
+    {
+        // Box-muller
+        float u1 = ctx->rngf(1.0f);
+        while (u1 < 1e-5)
+            u1 = ctx->rngf(1.0f);
+        float u2 = ctx->rngf(1.0f);
+        float m = std::sqrt(-2.f * std::log(u1));
+        float z0 = m * std::cos(2.f * pi * u2);
+        float z1 = m * std::sin(2.f * pi * u2);
+        float x = (width / 2.f) + (width / 50.f) * z0;
+        float y = (height / 2.f) + (height / 50.f) * z1;
+        x = std::min<float>(width - 1.f, std::max<float>(x, 0));
+        y = std::min<float>(height - 1.f, std::max<float>(y, 0));
+        return RealPair(x, y);
+    }
+
+    RealPair cell_loc(CellInfo *ci, bool ref)
+    {
+        if (ci->udata == -1) {
+            // not handled?
+            NPNR_ASSERT(ci->bel != BelId()); // already fixed
+            return RealPair(ctx->getBelLocation(ci->bel), 0.5f);
+        } else {
+            return ref ? mcells.at(ci->udata).ref_pos : mcells.at(ci->udata).pos;
+        }
+    }
+
+    void init_cells()
+    {
+        log_info("⌁ initialising cells...\n");
+        // Process non-clustered cells and find clusters
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            int cell_group;
+            StaticRect rect;
+            // Mismatched group case
+            if (!lookup_group(ci->type, cell_group, rect)) {
+                // TODO: what is the best thing to do here? singletons/odd cells we can probably mostly randomly place
+                continue;
+            }
+            if (ci->cluster != ClusterId()) {
+                // Defer processing of macro clusters
+                int c_idx = cluster2idx(ci->cluster);
+                if (c_idx >= int(macros.size())) {
+                    macros.emplace_back();
+                    macros.back().root = ctx->getClusterRootCell(ci->cluster);
+                }
+                auto &m = macros.at(c_idx);
+                Loc delta = ctx->getClusterOffset(ci);
+                m.cells[ClusterGroupKey(delta.x, delta.y, cell_group)].push_back(ci);
+            } else {
+                // Non-clustered cells can be processed already
+                int idx = add_cell(rect, cell_group, rand_loc(), ci);
+                ci->udata = idx;
+                auto &mc = mcells.at(idx);
+                mc.pin_count += int(ci->ports.size());
+                if (ci->bel != BelId()) {
+                    // Currently; treat all ready-placed cells as fixed (eventually we might do incremental ripups
+                    // here...)
+                    Loc loc = ctx->getBelLocation(ci->bel);
+                    mc.pos.x = loc.x + 0.5;
+                    mc.pos.y = loc.y + 0.5;
+                    mc.is_fixed = true;
+                }
+            }
+        }
+        // Process clustered cells
+        for (int i = 0; i < int(macros.size()); i++) {
+            auto &m = macros.at(i);
+            for (auto &kv : m.cells) {
+                const auto &g = cfg.cell_groups.at(kv.first.group);
+                // Only treat zero-area cells as zero-area; if this cluster also contains non-zero area cells
+                bool has_nonzero = std::any_of(kv.second.begin(), kv.second.end(),
+                                               [&](const CellInfo *ci) { return !g.zero_area_cells.count(ci->type); });
+                StaticRect cluster_size;
+                for (auto ci : kv.second) {
+                    if (has_nonzero && g.zero_area_cells.count(ci->type))
+                        continue;
+                    // Compute an equivalent-area stacked rectange for cells in this cluster group.
+                    // There are probably some ugly cases this handles badly.
+                    StaticRect r = g.cell_area.at(ci->type);
+                    if (r.w > r.h) {
+                        // Long and thin, "stack" vertically
+                        // Compute height we add to stack
+                        if (cluster_size.w < r.w) {
+                            cluster_size.h *= (cluster_size.w / r.w);
+                            cluster_size.w = r.w;
+                        }
+                        cluster_size.h += ((r.w * r.h) / cluster_size.w);
+                    } else {
+                        // "stack" horizontally
+                        if (cluster_size.h < r.h) {
+                            cluster_size.w *= (cluster_size.h / r.h);
+                            cluster_size.h = r.h;
+                        }
+                        cluster_size.w += ((r.w * r.h) / cluster_size.h);
+                    }
+                }
+                // Now add the moveable cell
+                if (cluster_size.area() > 0) {
+                    int idx = add_cell(cluster_size, kv.first.group, rand_loc(), kv.second.front());
+                    auto &mc = mcells.at(idx);
+                    if (kv.second.front()->bel != BelId()) {
+                        // Currently; treat all ready-placed cells as fixed (eventually we might do incremental ripups
+                        // here...)
+                        Loc loc = ctx->getBelLocation(kv.second.front()->bel);
+                        mc.pos.x = loc.x + 0.5;
+                        mc.pos.y = loc.y + 0.5;
+                        mc.is_fixed = true;
+                    }
+                    for (auto ci : kv.second) {
+                        ci->udata = idx;
+                        mc.pin_count += int(ci->ports.size());
+                    }
+                    auto &cc = ccells.at(idx);
+                    cc.macro_idx = i;
+                    cc.chunk_dx = kv.first.dx;
+                    cc.chunk_dy = kv.first.dy;
+                    m.conc_cells.push_back(idx);
+                }
+            }
+        }
+    }
+
+    const double target_util = 0.8;
+
+    void insert_dark()
+    {
+        log_info("⌁ inserting dark nodes...\n");
+        for (int group = 0; group < int(groups.size()); group++) {
+            auto &g = groups.at(group);
+            for (auto tile : g.loc_area) {
+                if (tile.value > 0.5f)
+                    continue;
+                StaticRect dark_area(1.0f, 1.0f - tile.value);
+                int cell_idx = add_cell(dark_area, group, RealPair(tile.x + 0.5f, tile.y + 0.5f), nullptr /*spacer*/);
+                mcells.at(cell_idx).is_dark = true;
+            }
+        }
+    }
+
+    void insert_spacer()
+    {
+        log_info("⌁ inserting spacers...\n");
+        int inserted_spacers = 0;
+        for (int group = 0; group < int(groups.size()); group++) {
+            const auto &cg = cfg.cell_groups.at(group);
+            const auto &g = groups.at(group);
+            double util = g.concrete_area / g.total_area;
+            log_info("⌁   group %s pre-spacer utilisation %.02f%% (target %.02f%%)\n", ctx->nameOf(cg.name),
+                     (util * 100.0), (target_util * 100.0));
+            // TODO: better computation of spacer size and placement?
+            int spacer_count = (g.total_area * target_util - g.concrete_area) / cg.spacer_rect.area();
+            if (spacer_count <= 0)
+                continue;
+            for (int i = 0; i < spacer_count; i++) {
+                add_cell(cg.spacer_rect, group, RealPair(ctx->rngf(width), ctx->rngf(height)), nullptr /*spacer*/);
+                ++inserted_spacers;
+            }
+        }
+        log_info("⌁   inserted a total of %d spacers\n", inserted_spacers);
+    }
+
+    // TODO: dark node insertion when we have obstructions or non-rectangular placement regions
+    int m;
+    double bin_w, bin_h;
+
+    std::vector<float> cs_table_fft;
+    std::vector<int> work_area_fft;
+
+    void prepare_density_bins()
+    {
+        // TODO: a m x m grid follows the paper and makes the DCTs easier, but is it actually ideal for non-square
+        // FPGAs?
+        m = 1 << int(std::ceil(std::log2(std::sqrt(mcells.size() / groups.size()))));
+        bin_w = double(width) / m;
+        bin_h = double(height) / m;
+
+        for (auto &g : groups) {
+            g.density.reset(m, m, 0);
+            g.density_fft.reset(m, m, 0);
+            g.electro_phi.reset(m, m, 0);
+            g.electro_fx.reset(m, m, 0);
+            g.electro_fy.reset(m, m, 0);
+        }
+        cs_table_fft.resize(m * 3 / 2, 0);
+        work_area_fft.resize(std::round(std::sqrt(m)) + 2, 0);
+        work_area_fft.at(0) = 0;
+    }
+
+    template <typename TFunc> void iter_slithers(RealPair pos, StaticRect rect, TFunc func)
+    {
+        // compute the stamp over bins (this could probably be more efficient?)
+
+        double width = rect.w, height = rect.h;
+        double scaled_density = 1.0;
+        if (width < bin_w) {
+            scaled_density *= (width / bin_w);
+            width = bin_w;
+        }
+        if (height < bin_h) {
+            scaled_density *= (height / bin_h);
+            height = bin_h;
+        }
+
+        double x0 = pos.x - (width / 2), x1 = pos.x + (width / 2);
+        double y0 = pos.y - (height / 2), y1 = pos.y + (height / 2);
+        for (int y = int(y0 / bin_h); y <= int(y1 / bin_h); y++) {
+            for (int x = int(x0 / bin_w); x <= int(x1 / bin_w); x++) {
+                int xb = std::max(0, std::min(x, m - 1));
+                int yb = std::max(0, std::min(y, m - 1));
+                double slither_w = 1.0, slither_h = 1.0;
+                if (yb == int(y0 / bin_h)) // y slithers
+                    slither_h = ((yb + 1) * bin_h) - y0;
+                else if (yb == int(y1 / bin_h))
+                    slither_h = (y1 - yb * bin_h);
+                if (xb == int(x0 / bin_w)) // x slithers
+                    slither_w = ((xb + 1) * bin_w) - x0;
+                else if (xb == int(x1 / bin_w))
+                    slither_w = (x1 - xb * bin_w);
+                func(xb, yb, scaled_density * slither_w * slither_h);
+            }
+        }
+    };
+
+    void compute_density(int group, bool ref)
+    {
+        auto &g = groups.at(group);
+        // reset
+        for (auto entry : g.density)
+            entry.value = 0;
+        // populate
+        for (int idx = 0; idx < int(mcells.size()); idx++) {
+            auto &mc = mcells.at(idx);
+            if (mc.group != group)
+                continue;
+            // scale width and height to be at least one bin (local density smoothing from the eplace paper)
+            // TODO: should we really do this every iteration?
+
+            auto pos = ref ? mc.ref_pos : mc.pos;
+            iter_slithers(pos, mc.rect, [&](int x, int y, float area) { g.density.at(x, y) += area; });
+        }
+    }
+
+    void compute_overlap()
+    {
+        // populate for concrete cells only
+        for (auto &g : groups)
+            g.conc_density.reset(m, m, 0);
+        for (int idx = 0; idx < int(ccells.size()); idx++) {
+            auto &mc = mcells.at(idx);
+            auto &g = groups.at(mc.group);
+            // scale width and height to be at least one bin (local density smoothing from the eplace paper)
+            // TODO: should we really do this every iteration?
+            auto loc = mc.pos;
+            auto size = mc.rect;
+
+            for (int dy = 0; dy <= int(size.h); dy++) {
+                for (int dx = 0; dx <= int(size.w); dx++) {
+                    float h = (dy == int(size.h)) ? (size.h - int(size.h)) : 1;
+                    float w = (dx == int(size.w)) ? (size.w - int(size.w)) : 1;
+                    g.conc_density.at(loc.x + dx, loc.y + dy) += w * h;
+                }
+            }
+        }
+        std::string overlap_str = "";
+        for (int idx = 0; idx < int(groups.size()); idx++) {
+            auto &g = groups.at(idx);
+            g.overlap = 0;
+            float total_area = 0;
+            for (auto tile : g.loc_area) {
+                // g.overlap += std::max<float>(0, g.conc_density.at(tile.x, tile.y) - tile.value);
+                g.overlap += std::max<float>(0, g.conc_density.at(tile.x, tile.y) - 1);
+                total_area += g.conc_density.at(tile.x, tile.y);
+            }
+            g.overlap /= std::max(1.0f, total_area);
+            if (!overlap_str.empty())
+                overlap_str += ", ";
+            overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap*100);
+            g.conc_density.write_csv(stringf("out_conc_density_%d_%d.csv", iter, idx));
+        }
+        log_info("overlap: %s\n", overlap_str.c_str());
+    }
+
+    void run_fft(int group)
+    {
+        // get data into form that fft wants
+        auto &g = groups.at(group);
+        for (auto entry : g.density)
+            g.density_fft.at(entry.x, entry.y) = entry.value;
+        if (fft_debug)
+            g.density_fft.write_csv(stringf("out_bin_density_%d_%d.csv", iter, group));
+        // Based on
+        // https://github.com/ALIGN-analoglayout/ALIGN-public/blob/master/PlaceRouteHierFlow/EA_placer/FFT/fft.cpp
+        // initial DCT for coefficients
+        ddct2d(m, m, -1, g.density_fft.data(), nullptr, work_area_fft.data(), cs_table_fft.data());
+        // postprocess coefficients
+        for (int x = 0; x < m; x++)
+            g.density_fft.at(x, 0) *= 0.5f;
+        for (int y = 0; y < m; y++)
+            g.density_fft.at(0, y) *= 0.5f;
+        for (int x = 0; x < m; x++)
+            for (int y = 0; y < m; y++)
+                g.density_fft.at(x, y) *= (4.0f / (m * m));
+        // scale inputs to IDCT for potentials and field
+        for (int x = 0; x < m; x++) {
+            float wx = pi * (x / float(m));
+            float wx2 = wx * wx;
+            for (int y = 0; y < m; y++) {
+                float wy = pi * (y / float(m));
+                float wy2 = wy * wy;
+
+                float dens = g.density_fft.at(x, y);
+                float phi = 0, ex = 0, ey = 0;
+
+                if (x != 0 || y != 0) { // avoid divide by zero...
+                    phi = dens / (wx2 + wy2);
+                    ex = phi * wx;
+                    ey = phi * wy;
+                }
+
+                g.electro_phi.at(x, y) = phi;
+                g.electro_fx.at(x, y) = ex;
+                g.electro_fy.at(x, y) = ey;
+            }
+        }
+        // IDCT for potential; 2D derivatives for field
+        ddct2d(m, m, 1, g.electro_phi.data(), nullptr, work_area_fft.data(), cs_table_fft.data());
+        ddsct2d(m, m, 1, g.electro_fx.data(), nullptr, work_area_fft.data(), cs_table_fft.data());
+        ddcst2d(m, m, 1, g.electro_fy.data(), nullptr, work_area_fft.data(), cs_table_fft.data());
+        if (fft_debug) {
+            g.electro_phi.write_csv(stringf("out_bin_phi_%d_%d.csv", iter, group));
+            g.electro_fx.write_csv(stringf("out_bin_ex_%d_%d.csv", iter, group));
+            g.electro_fy.write_csv(stringf("out_bin_ey_%d_%d.csv", iter, group));
+        }
+    }
+
+    void compute_bounds(PlacerNet &net, Axis axis, bool ref)
+    {
+        NetInfo *ni = net.ni;
+        auto drv_loc = cell_loc(ni->driver.cell, ref);
+        // seed with driver location
+        net.b1.at(axis) = net.b0.at(axis) = drv_loc.at(axis);
+        // iterate over users
+        for (auto &usr : ni->users) {
+            auto usr_loc = cell_loc(usr.cell, ref);
+            net.b1.at(axis) = std::max(net.b1.at(axis), usr_loc.at(axis));
+            net.b0.at(axis) = std::min(net.b0.at(axis), usr_loc.at(axis));
+        }
+    }
+
+    RealPair wl_coeff{0.5f, 0.5f};
+
+    void update_nets(Axis axis, bool ref)
+    {
+        static constexpr float min_wirelen_force = -300.f;
+        for (auto &net : nets) {
+            if (net.skip)
+                continue;
+            net.min_exp.at(axis) = 0;
+            net.x_min_exp.at(axis) = 0;
+            net.max_exp.at(axis) = 0;
+            net.x_max_exp.at(axis) = 0;
+            // update bounding box
+            compute_bounds(net, axis, ref);
+            // compute rough center to subtract from exponents to avoid FP issues (from replace)
+            float c = (net.b1.at(axis) + net.b0.at(axis)) / 2.f;
+            for (auto &port : net.ports) {
+                if (!port.ref.cell)
+                    continue;
+                RealPair loc = cell_loc(port.ref.cell, ref);
+                // update weighted-average model exponents
+                float emin = (c - loc.at(axis)) * wl_coeff.at(axis);
+                float emax = (loc.at(axis) - c) * wl_coeff.at(axis);
+
+                if (emin > min_wirelen_force) {
+                    port.min_exp.at(axis) = std::exp(emin);
+                    net.min_exp.at(axis) += port.min_exp.at(axis);
+                    net.x_min_exp.at(axis) += loc.at(axis) * port.min_exp.at(axis);
+                } else {
+                    port.min_exp.at(axis) = PlacerPort::invalid;
+                }
+                if (emax > min_wirelen_force) {
+                    port.max_exp.at(axis) = std::exp(emax);
+                    net.max_exp.at(axis) += port.max_exp.at(axis);
+                    net.x_max_exp.at(axis) += loc.at(axis) * port.max_exp.at(axis);
+                } else {
+                    port.max_exp.at(axis) = PlacerPort::invalid;
+                }
+            }
+            net.wa_wl.at(axis) =
+                    (net.x_max_exp.at(axis) / net.max_exp.at(axis)) - (net.x_min_exp.at(axis) / net.min_exp.at(axis));
+        }
+    }
+
+    float wirelen_grad(CellInfo *cell, Axis axis, bool ref)
+    {
+        float gradient = 0;
+        if (cell->udata == -1)
+            return 0;
+        RealPair loc = cell_loc(cell, ref);
+        for (auto &port : cell->ports) {
+            NetInfo *ni = port.second.net;
+            if (!ni)
+                continue;
+            auto &nd = nets.at(ni->udata);
+            if (nd.skip)
+                continue;
+            auto &pd = nd.ports.at(port.second.type == PORT_OUT ? (nd.ports.size() - 1) : port.second.user_idx.idx());
+            // From Replace
+            // TODO: check these derivatives on paper
+            float d_min = 0, d_max = 0;
+            if (pd.has_min_exp(axis)) {
+                float min_sum = nd.min_exp.at(axis), x_min_sum = nd.x_min_exp.at(axis);
+                d_min = (min_sum * (pd.min_exp.at(axis) * (1.0f - wl_coeff.at(axis) * loc.at(axis))) +
+                         wl_coeff.at(axis) * pd.min_exp.at(axis) * x_min_sum) /
+                        (min_sum * min_sum);
+            }
+            if (pd.has_max_exp(axis)) {
+                float max_sum = nd.max_exp.at(axis), x_max_sum = nd.x_max_exp.at(axis);
+                d_max = (max_sum * (pd.max_exp.at(axis) * (1.0f + wl_coeff.at(axis) * loc.at(axis))) -
+                         wl_coeff.at(axis) * pd.max_exp.at(axis) * x_max_sum) /
+                        (max_sum * max_sum);
+            }
+            gradient += (d_min - d_max);
+        }
+
+        return gradient;
+    }
+
+    float dens_penalty = 0.025f;
+    float nesterov_a = 1.0f;
+
+    void update_gradients(bool ref = true, bool set_prev = true, bool init_penalty = false)
+    {
+        // TODO: skip non-group cells more efficiently?
+        for (int group = 0; group < int(groups.size()); group++) {
+            compute_density(group, ref);
+            run_fft(group);
+        }
+        for (auto axis : {Axis::X, Axis::Y}) {
+            update_nets(axis, ref);
+        }
+        // First loop: back up gradients if required; set to zero; and compute density gradient
+        for (auto &cell : mcells) {
+            auto &g = groups.at(cell.group);
+            if (set_prev && ref) {
+                cell.last_wl_grad = cell.ref_wl_grad;
+                cell.last_dens_grad = cell.ref_dens_grad;
+                cell.last_total_grad = cell.ref_total_grad;
+            }
+            // wirelength gradient updated based on cell instances in next loop
+            (ref ? cell.ref_wl_grad : cell.wl_grad) = RealPair(0, 0);
+            // density grad based on bins - do we need to interpolate?
+            auto &grad = (ref ? cell.ref_dens_grad : cell.dens_grad);
+            grad = RealPair(0, 0);
+            iter_slithers((ref ? cell.ref_pos : cell.pos), cell.rect, [&](int x, int y, float area) {
+                grad += RealPair(g.electro_fx.at(x, y) * area, g.electro_fy.at(x, y) * area);
+            });
+            // total gradient computed at the end
+            (ref ? cell.ref_total_grad : cell.total_grad) = RealPair(0, 0);
+        }
+        // Second loop: sum up wirelength gradients across concrete cell instances
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->udata == -1)
+                continue;
+            auto &mc = mcells.at(ci->udata);
+            // TODO: exploit parallelism across axes
+            float wl_gx = wirelen_grad(ci, Axis::X, ref);
+            float wl_gy = wirelen_grad(ci, Axis::Y, ref);
+            (ref ? mc.ref_wl_grad : mc.wl_grad) += RealPair(wl_gx, wl_gy);
+        }
+        if (init_penalty) {
+            // set initial density penalty
+            float wirelen_sum = 0;
+            float force_sum = 0;
+            for (auto &cell : ctx->cells) {
+                CellInfo *ci = cell.second.get();
+                if (ci->udata == -1)
+                    continue;
+                auto &mc = mcells.at(ci->udata);
+                wirelen_sum += std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y);
+                force_sum += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
+            }
+            dens_penalty = wirelen_sum / force_sum;
+            log_info(" initial density penalty: %f\n", dens_penalty);
+        }
+        // Third loop: compute total gradient, and precondition
+        // TODO: ALM as well as simple penalty
+        for (auto &cell : mcells) {
+#if 0
+            if (!cell.is_spacer) {
+                printf("%d (%f, %f) wirelen_grad: (%f,%f) density_grad: (%f,%f)\n", iter, cell.ref_pos.x,
+                       cell.ref_pos.y, cell.ref_wl_grad.x, cell.ref_wl_grad.y, cell.ref_dens_grad.x,
+                       cell.ref_dens_grad.y);
+            }
+#endif
+            // Preconditioner from replace for now
+            float precond = std::max(1.0f, float(cell.pin_count) + dens_penalty * cell.rect.area());
+            (ref ? cell.ref_total_grad : cell.total_grad) =
+                    (((ref ? cell.ref_wl_grad : cell.wl_grad) * -1) -
+                     (ref ? cell.ref_dens_grad : cell.dens_grad) * dens_penalty) /
+                    precond;
+        }
+    }
+
+    float steplen = 0.01;
+
+    float get_steplen()
+    {
+        float coord_dist = 0;
+        float grad_dist = 0;
+        int n = 0;
+        for (auto &cell : mcells) {
+            coord_dist += (cell.ref_pos.x - cell.last_ref_pos.x) * (cell.ref_pos.x - cell.last_ref_pos.x);
+            coord_dist += (cell.ref_pos.y - cell.last_ref_pos.y) * (cell.ref_pos.y - cell.last_ref_pos.y);
+            grad_dist +=
+                    (cell.ref_total_grad.x - cell.last_total_grad.x) * (cell.ref_total_grad.x - cell.last_total_grad.x);
+            grad_dist +=
+                    (cell.ref_total_grad.y - cell.last_total_grad.y) * (cell.ref_total_grad.y - cell.last_total_grad.y);
+            // keep track of N separately, because we might exclude some cells
+            ++n;
+        }
+        coord_dist = std::sqrt(coord_dist / (2 * float(mcells.size())));
+        grad_dist = std::sqrt(grad_dist / (2 * float(mcells.size())));
+        log_info("coord_dist: %f grad_dist: %f\n", coord_dist, grad_dist);
+        return coord_dist / grad_dist;
+        // return 0.1;
+    }
+
+    float system_hpwl()
+    {
+        float hpwl = 0;
+        for (auto &net : nets) {
+            if (net.skip)
+                continue;
+            // update bounding box
+            compute_bounds(net, Axis::X, false);
+            compute_bounds(net, Axis::Y, false);
+            hpwl += net.b1.x - net.b0.x;
+            hpwl += net.b1.y - net.b0.y;
+        }
+        return hpwl;
+    }
+
+    float system_potential()
+    {
+        float pot = 0;
+        for (auto &cell : mcells) {
+            auto &g = groups.at(cell.group);
+            iter_slithers(cell.ref_pos, cell.rect,
+                          [&](int x, int y, float area) { pot += g.electro_phi.at(x, y) * area; });
+        }
+        return pot;
+    }
+
+    void initialise()
+    {
+        float initial_steplength = 0.01f;
+        // Update current and previous gradients with initial solution
+        for (auto &cell : mcells) {
+            cell.ref_pos = cell.pos;
+        }
+        while (true) {
+            update_gradients(true, true, /* init_penalty */ true);
+            // compute a "fake" previous position based on an arbitrary steplength and said gradients for nesterov
+            for (auto &cell : mcells) {
+                if (cell.is_fixed)
+                    continue;
+                // save current position in last_pos
+                cell.last_pos = cell.pos;
+                cell.last_ref_pos = cell.ref_pos;
+                // compute previous position; but store it in current for gradient computation
+                cell.ref_pos = cell.pos - cell.ref_total_grad * initial_steplength;
+            }
+            // Compute the previous gradients (albeit into the current state fields)
+            update_gradients(true);
+            // Now we have the fake previous state in the current state
+            for (auto &cell : mcells) {
+                std::swap(cell.last_ref_pos, cell.ref_pos);
+                std::swap(cell.ref_total_grad, cell.last_total_grad);
+                std::swap(cell.ref_wl_grad, cell.last_wl_grad);
+                std::swap(cell.ref_dens_grad, cell.last_dens_grad);
+            }
+            float next_steplen = get_steplen();
+            log_info("initial steplen=%f next steplen = %f\n", initial_steplength, next_steplen);
+            if (next_steplen != 0 && std::isfinite(next_steplen) && std::abs(next_steplen) < 1e10) {
+                break;
+            } else {
+                initial_steplength *= 10;
+            }
+        }
+    }
+
+    RealPair clamp_loc(RealPair loc)
+    {
+        return RealPair(std::max<float>(0, std::min<float>(width - 1, loc.x)),
+                        std::max<float>(0, std::min<float>(height - 1, loc.y)));
+    }
+
+    void update_chains()
+    {
+        // Move the post-solve position of a chain towards be the weighted average of its constituents
+        // The strength increases with iterations
+        float alpha = std::min<float>(std::pow(1.002f, iter) - 1, 1.0f);
+        for (int i = 0; i < int(macros.size()); i++) {
+            auto &macro = macros.at(i);
+            float total_area = 0;
+            const float area_epsilon = 0.05;
+            RealPair pos(0, 0), ref_pos(0, 0);
+            for (int c : macro.conc_cells) {
+                auto &mc = mcells.at(c);
+                float a = std::max(mc.rect.area(), area_epsilon);
+                pos += mc.pos * a;
+                ref_pos += mc.ref_pos * a;
+                total_area += a;
+            }
+            pos /= total_area;
+            ref_pos /= total_area;
+            for (int c : macro.conc_cells) {
+                auto &cc = ccells.at(c);
+                auto &mc = mcells.at(c);
+                mc.pos = mc.pos * (1-alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
+                mc.ref_pos = mc.ref_pos * (1 - alpha) + (ref_pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
+            }
+        }
+    }
+
+    void step()
+    {
+        // TODO: update penalties; wirelength factor; etc
+        steplen = get_steplen();
+        log_info("iter=%d steplen=%f a=%f\n", iter, steplen, nesterov_a);
+        float a_next = (1.0f + std::sqrt(4.0f * nesterov_a * nesterov_a + 1)) / 2.0f;
+        // Update positions according to trivial gradient descent (let's leave Nesterov's for later...)
+        for (auto &cell : mcells) {
+            if (cell.is_fixed || cell.is_dark)
+                continue;
+            // save current position in last_pos
+            cell.last_ref_pos = cell.ref_pos;
+            cell.last_pos = cell.pos;
+            // compute new position
+            cell.pos = clamp_loc(cell.ref_pos - cell.ref_total_grad * steplen);
+            // compute reference position
+            cell.ref_pos = clamp_loc(cell.pos + (cell.pos - cell.last_pos) * ((nesterov_a - 1) / a_next));
+        }
+        nesterov_a = a_next;
+        update_chains();
+        update_gradients(true);
+        log_info("   system potential: %f hpwl: %f\n", system_potential(), system_hpwl());
+        compute_overlap();
+    }
+
+    void legalise_step(bool dsp_bram) {
+        // assume DSP and BRAM are all groups 2+ for now
+        for (int i = 0; i < int(ccells.size()); i++) {
+            auto &mc = mcells.at(i);
+            auto &cc = ccells.at(i);
+            if (dsp_bram && mc.group < 2)
+                continue;
+            if (!dsp_bram && mc.group >= 2)
+                continue;
+            if (cc.macro_idx != -1 && i != macros.at(cc.macro_idx).root->udata)
+                continue; // not macro root
+            if (mc.is_fixed) { // already placed
+                NPNR_ASSERT(cc.base_cell->bel != BelId());
+                continue;
+            }
+            enqueue_legalise(i);
+        }
+        // in the DSP/BRAM step, also merge any cells outside of a group (global buffers, other random crud/singletons)
+        for (auto &cell : ctx->cells) {
+            if (cell.second->udata == -1)
+                enqueue_legalise(cell.second.get());
+        }
+        log_info("Strict legalising %d cells...\n", int(to_legalise.size()));
+        float pre_hpwl = system_hpwl();
+        legalise_placement_strict(true);
+        for (auto axis : {Axis::X, Axis::Y}) {
+            update_nets(axis, true);
+        }
+        float post_hpwl = system_hpwl();
+        log_info("HPWL after legalise: %f (delta: %f)\n", post_hpwl, post_hpwl - pre_hpwl);
+    }
+
+    void enqueue_legalise(int cell_idx) {
+        NPNR_ASSERT(cell_idx < int(ccells.size())); // we should never be legalising spacers or dark nodes
+        auto &ccell = ccells.at(cell_idx);
+        if (ccell.macro_idx != -1) {
+            // is a macro
+            auto &macro = macros.at(ccell.macro_idx);
+            to_legalise.emplace(int(macro.cells.size()), macro.root->name);
+        } else {
+            to_legalise.emplace(1, ccell.base_cell->name);
+        }
+    }
+
+    void enqueue_legalise(CellInfo *ci) {
+        if (ci->udata != -1) {
+            // managed by static
+            enqueue_legalise(ci->udata);
+        } else {
+            // special case
+            to_legalise.emplace(1, ci->name);
+        }
+    }
+    // Strict placement legalisation, performed after the initial HeAP spreading
+    void legalise_placement_strict(bool require_validity = true)
+    {
+        // At the moment we don't follow the full HeAP algorithm using cuts for legalisation, instead using
+        // the simple greedy largest-macro-first approach.
+        int ripup_radius = 2;
+        int total_iters = 0;
+        int total_iters_noreset = 0;
+        while (!to_legalise.empty()) {
+            auto top = to_legalise.top();
+            to_legalise.pop();
+
+            CellInfo *ci = ctx->cells.at(top.second).get();
+            // Was now placed, ignore
+            if (ci->bel != BelId())
+                continue;
+            // log_info("   Legalising %s (%s) %d\n", top.second.c_str(ctx), ci->type.c_str(ctx), top.first);
+            FastBels::FastBelsData *fb;
+            fast_bels.getBelsForCellType(ci->type, &fb);
+            int radius = 0;
+            int iter = 0;
+            int iter_at_radius = 0;
+            int total_iters_for_cell = 0;
+            bool placed = false;
+            BelId bestBel;
+            int best_inp_len = std::numeric_limits<int>::max();
+
+            total_iters++;
+            total_iters_noreset++;
+            if (total_iters > int(ccells.size())) {
+                total_iters = 0;
+                ripup_radius = std::max(std::max(width+1, height+1), ripup_radius * 2);
+            }
+
+            if (total_iters_noreset > std::max(5000, 8 * int(ctx->cells.size()))) {
+                log_error("Unable to find legal placement for all cells, design is probably at utilisation limit.\n");
+            }
+
+            while (!placed) {
+                // Determine a search radius around the solver location (which increases over time) that is clamped to
+                // the region constraint for the cell (if applicable)
+                int rx = radius, ry = radius;
+
+                // Pick a random X and Y location within our search radius
+                int cx, cy;
+                if (ci->udata == -1) {
+                    cx = width / 2;
+                    cy = height / 2;
+                } else {
+                    cx = int(mcells.at(ci->udata).pos.x);
+                    cy = int(mcells.at(ci->udata).pos.y);
+                }
+                int nx = ctx->rng(2 * rx + 1) + std::max(cx - rx, 0);
+                int ny = ctx->rng(2 * ry + 1) + std::max(cy - ry, 0);
+
+                iter++;
+                iter_at_radius++;
+                if (iter >= (10 * (radius + 1))) {
+                    // No luck yet, increase radius
+                    radius = std::min(std::max(width+1, height+1), radius + 1);
+                    while (radius < std::max(width+1, height+1)) {
+                        // Keep increasing the radius until it will actually increase the number of cells we are
+                        // checking (e.g. BRAM and DSP will not be in all cols/rows), so we don't waste effort
+                        for (int x = std::max(0, cx - radius);
+                             x <= std::min(width+1, cx + radius); x++) {
+                            if (x >= int(fb->size()))
+                                break;
+                            for (int y = std::max(0, cy - radius);
+                                 y <= std::min(height+1, cy + radius); y++) {
+                                if (y >= int(fb->at(x).size()))
+                                    break;
+                                if (fb->at(x).at(y).size() > 0)
+                                    goto notempty;
+                            }
+                        }
+                        radius = std::min(std::max(width+1, height+1), radius + 1);
+                    }
+                notempty:
+                    iter_at_radius = 0;
+                    iter = 0;
+                }
+                // If our randomly chosen cooridnate is out of bounds; or points to a tile with no relevant bels; ignore
+                // it
+                if (nx < 0 || nx > width+1)
+                    continue;
+                if (ny < 0 || ny > height+1)
+                    continue;
+
+                if (nx >= int(fb->size()))
+                    continue;
+                if (ny >= int(fb->at(nx).size()))
+                    continue;
+                if (fb->at(nx).at(ny).empty())
+                    continue;
+
+                // The number of attempts to find a location to try
+                int need_to_explore = 2 * radius;
+
+                // If we have found at least one legal location; and made enough attempts; assume it's good enough and
+                // finish
+                if (iter_at_radius >= need_to_explore && bestBel != BelId()) {
+                    CellInfo *bound = ctx->getBoundBelCell(bestBel);
+                    if (bound != nullptr) {
+                        ctx->unbindBel(bound->bel);
+                        enqueue_legalise(bound);
+                    }
+                    ctx->bindBel(bestBel, ci, STRENGTH_WEAK);
+                    placed = true;
+                    Loc loc = ctx->getBelLocation(bestBel);
+                    if (ci->udata != -1) {
+                        auto &mc = mcells.at(ci->udata);
+                        mc.pos = mc.ref_pos = RealPair(loc, 0.5);
+                        mc.is_fixed = true;
+                    }
+                    break;
+                }
+
+                if (ci->cluster == ClusterId()) {
+                    // The case where we have no relative constraints
+                    for (auto sz : fb->at(nx).at(ny)) {
+                        // Look through all bels in this tile; checking region constraint if applicable
+                        if (!ci->testRegion(sz))
+                            continue;
+                        // Prefer available bels; unless we are dealing with a wide radius (e.g. difficult control sets)
+                        // or occasionally trigger a tiebreaker
+                        if (ctx->checkBelAvail(sz) || (radius > ripup_radius || ctx->rng(20000) < 10)) {
+                            CellInfo *bound = ctx->getBoundBelCell(sz);
+                            if (bound != nullptr) {
+                                // Only rip up cells without constraints
+                                if (bound->cluster != ClusterId())
+                                    continue;
+                                ctx->unbindBel(bound->bel);
+                            }
+                            // Provisionally bind the bel
+                            ctx->bindBel(sz, ci, STRENGTH_WEAK);
+                            if (require_validity && !ctx->isBelLocationValid(sz)) {
+                                // New location is not legal; unbind the cell (and rebind the cell we ripped up if
+                                // applicable)
+                                ctx->unbindBel(sz);
+                                if (bound != nullptr)
+                                    ctx->bindBel(sz, bound, STRENGTH_WEAK);
+                            } else if (iter_at_radius < need_to_explore) {
+                                // It's legal, but we haven't tried enough locations yet
+                                ctx->unbindBel(sz);
+                                if (bound != nullptr)
+                                    ctx->bindBel(sz, bound, STRENGTH_WEAK);
+                                int input_len = 0;
+                                // Compute a fast input wirelength metric at this bel; and save if better than our last
+                                // try
+                                for (auto &port : ci->ports) {
+                                    auto &p = port.second;
+                                    if (p.type != PORT_IN || p.net == nullptr || p.net->driver.cell == nullptr)
+                                        continue;
+                                    CellInfo *drv = p.net->driver.cell;
+                                    if (drv->udata == -1)
+                                        continue;
+                                    auto drv_loc = mcells.at(drv->udata);
+                                    input_len += std::abs(int(drv_loc.pos.x) - nx) + std::abs(int(drv_loc.pos.y) - ny);
+                                }
+                                if (input_len < best_inp_len) {
+                                    best_inp_len = input_len;
+                                    bestBel = sz;
+                                }
+                                break;
+                            } else {
+                                // It's legal, and we've tried enough. Finish.
+                                if (bound != nullptr)
+                                    enqueue_legalise(bound);
+                                Loc loc = ctx->getBelLocation(sz);
+                                if (ci->udata != -1) {
+                                    auto &mc = mcells.at(ci->udata);
+                                    mc.pos = mc.ref_pos = RealPair(loc, 0.5);
+                                    mc.is_fixed = true;
+                                }
+                                placed = true;
+                                break;
+                            }
+                        }
+                    }
+                } else {
+                    // We do have relative constraints
+                    for (auto sz : fb->at(nx).at(ny)) {
+                        // List of cells and their destination
+                        std::vector<std::pair<CellInfo *, BelId>> targets;
+                        // List of bels we placed things at; and the cell that was there before if applicable
+                        std::vector<std::pair<BelId, CellInfo *>> swaps_made;
+
+                        if (!ctx->getClusterPlacement(ci->cluster, sz, targets))
+                            continue;
+
+                        for (auto &target : targets) {
+                            // Check it satisfies the region constraint if applicable
+                            if (!target.first->testRegion(target.second))
+                                goto fail;
+                            CellInfo *bound = ctx->getBoundBelCell(target.second);
+                            // Chains cannot overlap; so if we have to ripup a cell make sure it isn't part of a chain
+                            if (bound != nullptr)
+                                if (bound->cluster != ClusterId() || bound->belStrength > STRENGTH_WEAK)
+                                    goto fail;
+                        }
+                        // Actually perform the move; keeping track of the moves we make so we can revert them if needed
+                        for (auto &target : targets) {
+                            CellInfo *bound = ctx->getBoundBelCell(target.second);
+                            if (bound != nullptr)
+                                ctx->unbindBel(target.second);
+                            ctx->bindBel(target.second, target.first, STRENGTH_STRONG);
+                            swaps_made.emplace_back(target.second, bound);
+                        }
+                        // Check that the move we have made is legal
+                        for (auto &sm : swaps_made) {
+                            if (!ctx->isBelLocationValid(sm.first))
+                                goto fail;
+                        }
+
+                        if (false) {
+                        fail:
+                            // If the move turned out to be illegal; revert all the moves we made
+                            for (auto &swap : swaps_made) {
+                                ctx->unbindBel(swap.first);
+                                if (swap.second != nullptr)
+                                    ctx->bindBel(swap.first, swap.second, STRENGTH_WEAK);
+                            }
+                            continue;
+                        }
+                        for (auto &target : targets) {
+                            Loc loc = ctx->getBelLocation(target.second);
+                            if (ci->udata != -1) {
+                                auto &mc = mcells.at(target.first->udata);
+                                mc.pos = mc.ref_pos = RealPair(loc, 0.5);
+                                mc.is_fixed = true;
+                            }
+                            // log_info("%s %d %d %d\n", target.first->name.c_str(ctx), loc.x, loc.y, loc.z);
+                        }
+                        for (auto &swap : swaps_made) {
+                            // Where we have ripped up cells; add them to the queue
+                            if (swap.second != nullptr)
+                                enqueue_legalise(swap.second);
+                        }
+
+                        placed = true;
+                        break;
+                    }
+                }
+
+                total_iters_for_cell++;
+            }
+        }
+    }
+
+  public:
+    StaticPlacer(Context *ctx, PlacerStaticCfg cfg) : ctx(ctx), cfg(cfg), fast_bels(ctx, true, 8), tmg(ctx)
+    {
+        groups.resize(cfg.cell_groups.size());
+    };
+    void place()
+    {
+        log_info("Running Static placer...\n");
+        init_bels();
+        prepare_cells();
+        init_cells();
+        init_nets();
+        insert_dark();
+        insert_spacer();
+
+        prepare_density_bins();
+        initialise();
+        bool legalised_ip = false;
+        while (true) {
+            step();
+            dens_penalty *= 1.025;
+            if (!legalised_ip) {
+                float ip_overlap = 0;
+                for (int i = 2; i < int(groups.size()); i++)
+                    ip_overlap = std::max(ip_overlap, groups.at(i).overlap);
+                if (ip_overlap < 0.15) {
+                    legalise_step(true);
+                    legalised_ip = true;
+                }
+            } else {
+                float logic_overlap = 0;
+                for (int i = 0; i < 2; i++)
+                    logic_overlap = std::max(logic_overlap, groups.at(i).overlap);
+                if (logic_overlap < 0.1) {
+                    legalise_step(false);
+                    break;
+                }
+            }
+            ++iter;
+        }
+        {
+            auto placer1_cfg = Placer1Cfg(ctx);
+            placer1_cfg.hpwl_scale_x = cfg.hpwl_scale_x;
+            placer1_cfg.hpwl_scale_y = cfg.hpwl_scale_y;
+            placer1_refine(ctx, placer1_cfg);
+        }
+    }
+};
+}; // namespace
+
+bool placer_static(Context *ctx, PlacerStaticCfg cfg)
+{
+    StaticPlacer(ctx, cfg).place();
+    return true;
+}
+
+PlacerStaticCfg::PlacerStaticCfg(Context *ctx)
+{
+    timing_driven = ctx->setting<bool>("timing_driven");
+
+    hpwl_scale_x = 1;
+    hpwl_scale_y = 1;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/place/placer_static.h b/common/place/placer_static.h
new file mode 100644
index 0000000000..adce1f41ef
--- /dev/null
+++ b/common/place/placer_static.h
@@ -0,0 +1,70 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022-23  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *
+ */
+
+#ifndef PLACER_STATIC_H
+#define PLACER_STATIC_H
+#include "log.h"
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct StaticRect
+{
+    StaticRect() : w(0), h(0){};
+    StaticRect(float w, float h) : w(w), h(h){};
+    float w, h;
+    float area() const { return w * h; }
+};
+
+struct StaticCellGroupCfg
+{
+    // name of the group for debugging purposes
+    IdString name;
+    // bel buckets in this group
+    pool<BelBucketId> bel_buckets;
+    // cell & bel types in this group and the (normalised) area of that cell/bel type
+    dict<IdString, StaticRect> cell_area, bel_area;
+    // these cells (generally auxilliary CLB cells like RAMW; carry; MUX) are considered to have zero area when part of
+    // a macro with other non-zero-area cells
+    pool<IdString> zero_area_cells;
+    // size of spacers to insert
+    StaticRect spacer_rect{0.5, 0.5};
+};
+
+struct PlacerStaticCfg
+{
+    PlacerStaticCfg(Context *ctx);
+
+    // These cell types will be randomly locked to prevent singular matrices
+    pool<IdString> ioBufTypes;
+    int hpwl_scale_x = 1;
+    int hpwl_scale_y = 1;
+    bool timing_driven = false;
+    // for calculating timing estimates based on distance
+    // estimate = c + mx*dx + my * dy
+    delay_t timing_c = 100, timing_mx = 100, timing_my = 100;
+    // groups of cells that should be placed together.
+    // group 0 must be LUTs and group 1 must be FFs, further groups for BRAM/DSP/misc
+    std::vector<StaticCellGroupCfg> cell_groups;
+};
+
+extern bool placer_static(Context *ctx, PlacerStaticCfg cfg);
+NEXTPNR_NAMESPACE_END
+#endif
\ No newline at end of file
diff --git a/common/place/static_util.h b/common/place/static_util.h
new file mode 100644
index 0000000000..a3dc5c9368
--- /dev/null
+++ b/common/place/static_util.h
@@ -0,0 +1,142 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef STATIC_UTIL_H
+#define STATIC_UTIL_H
+
+#include <fstream>
+#include "nextpnr_assertions.h"
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace StaticUtil {
+
+enum class Axis
+{
+    X,
+    Y
+};
+
+struct RealPair
+{
+    RealPair() : x(0), y(0){};
+    RealPair(float x, float y) : x(x), y(y){};
+    explicit RealPair(Loc l, float bias = 0.0f) : x(l.x + bias), y(l.y + bias){};
+    float x, y;
+    RealPair &operator+=(const RealPair &other)
+    {
+        x += other.x;
+        y += other.y;
+        return *this;
+    }
+    RealPair &operator/=(float factor)
+    {
+        x /= factor;
+        y /= factor;
+        return *this;
+    }
+    friend RealPair operator+(RealPair a, RealPair b);
+    friend RealPair operator-(RealPair a, RealPair b);
+    RealPair operator*(float factor) const { return RealPair(x * factor, y * factor); }
+    RealPair operator/(float factor) const { return RealPair(x / factor, y / factor); }
+    // to simplify axis-generic code
+    inline float &at(Axis axis) { return (axis == Axis::Y) ? y : x; }
+    inline const float &at(Axis axis) const { return (axis == Axis::Y) ? y : x; }
+};
+inline RealPair operator+(RealPair a, RealPair b) { return RealPair(a.x + b.x, a.y + b.y); }
+inline RealPair operator-(RealPair a, RealPair b) { return RealPair(a.x - b.x, a.y - b.y); }
+
+// array2d; but as ourafft wants it
+struct FFTArray
+{
+    FFTArray(int width = 0, int height = 0) : m_width(width), m_height(height)
+    {
+        alloc();
+        fill(0);
+    }
+
+    void fill(float value)
+    {
+        for (int x = 0; x < m_width; x++)
+            for (int y = 0; y < m_height; y++)
+                m_data[x][y] = value;
+    }
+
+    void reset(int width, int height, float value = 0)
+    {
+        if (width != m_height || height != m_height) {
+            destroy();
+            m_width = width;
+            m_height = height;
+            alloc();
+        }
+        fill(value);
+    }
+
+    float &at(int x, int y)
+    {
+        NPNR_ASSERT(x >= 0 && x < m_width && y >= 0 && y < m_height);
+        return m_data[x][y];
+    }
+    float at(int x, int y) const
+    {
+        NPNR_ASSERT(x >= 0 && x < m_width && y >= 0 && y < m_height);
+        return m_data[x][y];
+    }
+    float **data() { return m_data; }
+
+    void write_csv(const std::string &filename) const
+    {
+        std::ofstream out(filename);
+        NPNR_ASSERT(out);
+        for (int y = 0; y < m_height; y++) {
+            for (int x = 0; x < m_width; x++) {
+                out << at(x, y) << ",";
+            }
+            out << std::endl;
+        }
+    }
+
+    ~FFTArray() { destroy(); }
+
+  private:
+    int m_width, m_height;
+    float **m_data = nullptr;
+    void alloc()
+    {
+        if (m_width == 0)
+            return;
+        m_data = new float *[m_width];
+        for (int x = 0; x < m_width; x++)
+            m_data[x] = (m_height > 0) ? (new float[m_height]) : nullptr;
+    }
+    void destroy()
+    {
+        for (int x = 0; x < m_width; x++)
+            delete[] m_data[x];
+        delete[] m_data;
+    }
+};
+
+}; // namespace StaticUtil
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index a0b2644ca5..5d46f881c9 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -30,6 +30,7 @@
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
+#include "placer_static.h"
 #include "router1.h"
 #include "router2.h"
 #include "timing.h"
@@ -586,6 +587,49 @@ delay_t Arch::getRipupDelayPenalty() const { return 400; }
 
 // -----------------------------------------------------------------------
 
+namespace {
+void configure_static(Arch *arch, PlacerStaticCfg &cfg)
+{
+    {
+        cfg.cell_groups.emplace_back();
+        auto &comb = cfg.cell_groups.back();
+        comb.name = arch->id("COMB");
+        comb.bel_area[id_TRELLIS_COMB] = StaticRect(1.0f, 0.125f);
+        comb.bel_area[id_TRELLIS_RAMW] = StaticRect(1.0f, 0.125f);
+        comb.cell_area[id_TRELLIS_COMB] = StaticRect(1.0f, 0.125f);
+        comb.cell_area[id_TRELLIS_RAMW] = StaticRect(1.0f, 0.125f);
+        comb.zero_area_cells.insert(id_TRELLIS_RAMW);
+        comb.spacer_rect = StaticRect(1.0f, 0.125f);
+    }
+
+    {
+        cfg.cell_groups.emplace_back();
+        auto &comb = cfg.cell_groups.back();
+        comb.name = arch->id("FF");
+        comb.cell_area[id_TRELLIS_FF] = StaticRect(1.0f, 0.125f);
+        comb.bel_area[id_TRELLIS_FF] = StaticRect(1.0f, 0.125f);
+        comb.spacer_rect = StaticRect(1.0f, 0.125f);
+    }
+
+    {
+        cfg.cell_groups.emplace_back();
+        auto &comb = cfg.cell_groups.back();
+        comb.name = arch->id("RAM");
+        comb.cell_area[id_DP16KD] = StaticRect(2.0f, 1.0f);
+        comb.bel_area[id_DP16KD] = StaticRect(2.0f, 1.0f);
+        comb.spacer_rect = StaticRect(2.0f, 1.0f);
+    }
+    {
+        cfg.cell_groups.emplace_back();
+        auto &comb = cfg.cell_groups.back();
+        comb.name = arch->id("MUL");
+        comb.cell_area[id_MULT18X18D] = StaticRect(2.0f, 1.0f);
+        comb.bel_area[id_MULT18X18D] = StaticRect(2.0f, 1.0f);
+        comb.spacer_rect = StaticRect(2.0f, 1.0f);
+    }
+}
+} // namespace
+
 bool Arch::place()
 {
     std::string placer = str_or_default(settings, id_placer, defaultPlacer);
@@ -609,6 +653,11 @@ bool Arch::place()
 
         if (!placer_heap(getCtx(), cfg))
             return false;
+    } else if (placer == "static") {
+        PlacerStaticCfg cfg(getCtx());
+        configure_static(this, cfg);
+        if (!placer_static(getCtx(), cfg))
+            return false;
     } else if (placer == "sa") {
         if (!placer1(getCtx(), Placer1Cfg(getCtx())))
             return false;
@@ -1226,7 +1275,7 @@ WireId Arch::get_bank_eclk(int bank, int eclk)
 
 const std::string Arch::defaultPlacer = "heap";
 
-const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap", "static"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};

From 5a2eff21201eea83a0c8f74cbb5f813271032d21 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 9 Oct 2023 09:00:27 +0200
Subject: [PATCH 498/712] compile fix

---
 gui/machxo2/mainwindow.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gui/machxo2/mainwindow.cc b/gui/machxo2/mainwindow.cc
index 179bf8e18c..823d80917e 100644
--- a/gui/machxo2/mainwindow.cc
+++ b/gui/machxo2/mainwindow.cc
@@ -92,7 +92,7 @@ void MainWindow::new_proj()
             continue; // chipdb not available
         for (auto &chip : db_ptr->get()->variants) {
             for (auto &pkg : chip.packages) {
-                for (auto &speedgrade : chip.speed_grades) {
+                for (auto &speedgrade : chip.speeds) {
                     for (auto &rating : chip.suffixes) {
                         std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
                                                       pkg.short_name.get(), rating.suffix.get());

From 4a7e58a9388971c96d7144f72a3692d1fbc6fdfd Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 14 Oct 2023 09:40:41 +0200
Subject: [PATCH 499/712] static/ecp5: zero bel area for RAMW because it's a
 zero-area cell

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 5d46f881c9..8bf5db9194 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -595,7 +595,7 @@ void configure_static(Arch *arch, PlacerStaticCfg &cfg)
         auto &comb = cfg.cell_groups.back();
         comb.name = arch->id("COMB");
         comb.bel_area[id_TRELLIS_COMB] = StaticRect(1.0f, 0.125f);
-        comb.bel_area[id_TRELLIS_RAMW] = StaticRect(1.0f, 0.125f);
+        comb.bel_area[id_TRELLIS_RAMW] = StaticRect(0.0f, 0.0f);
         comb.cell_area[id_TRELLIS_COMB] = StaticRect(1.0f, 0.125f);
         comb.cell_area[id_TRELLIS_RAMW] = StaticRect(1.0f, 0.125f);
         comb.zero_area_cells.insert(id_TRELLIS_RAMW);

From 1238b69d744e034a1a4593dd65ffcfc2b14167fb Mon Sep 17 00:00:00 2001
From: Justin Rajewski <justin@alchitry.com>
Date: Thu, 26 Oct 2023 10:29:44 -0600
Subject: [PATCH 500/712] Fixes for building on windows

---
 common/kernel/base_arch.h | 1 +
 common/kernel/command.cc  | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index a27e261d1f..ff906bfd7c 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -24,6 +24,7 @@
 #include <array>
 #include <vector>
 
+#define NOMINMAX
 #include "arch_api.h"
 #include "base_clusterinfo.h"
 #include "idstring.h"
diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index ac154cc6eb..565f5fc555 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -46,6 +46,7 @@
 #include "version.h"
 
 #if defined(_WIN32)
+#define NOMINMAX
 #include <io.h>
 #include <windows.h>
 #elif defined(__APPLE__)
@@ -126,7 +127,7 @@ std::string proc_self_dirname()
 std::string proc_self_dirname()
 {
     int i = 0;
-#ifdef __MINGW32__
+#ifdef _WIN32
     char longpath[MAX_PATH + 1];
     char shortpath[MAX_PATH + 1];
 #else

From 95f0a1939146725194ba02ca58d93f5852e1b1fc Mon Sep 17 00:00:00 2001
From: Justin Rajewski <justin@alchitry.com>
Date: Thu, 26 Oct 2023 10:49:13 -0600
Subject: [PATCH 501/712] Fixes for building on windows

---
 3rdparty/imgui/examples/imgui_impl_win32.cpp  |   1 +
 3rdparty/imgui/examples/libs/gl3w/GL/gl3w.c   |   1 +
 .../imgui/examples/libs/gl3w/GL/glcorearb.h   |   1 +
 .../libs/glfw/include/GLFW/glfw3native.h      |   3 +-
 3rdparty/imgui/imgui.cpp                      |   4 +-
 3rdparty/oourafft/fftsg.cc                    | 114 ++++++------------
 3rdparty/oourafft/fftsg2d.cc                  |   1 +
 .../pybind11/docs/advanced/cast/strings.rst   |   3 +-
 common/kernel/base_arch.h                     |   1 -
 common/kernel/command.cc                      |   2 +-
 common/kernel/embed.cc                        |   1 +
 gui/application.cc                            |   1 +
 12 files changed, 48 insertions(+), 85 deletions(-)

diff --git a/3rdparty/imgui/examples/imgui_impl_win32.cpp b/3rdparty/imgui/examples/imgui_impl_win32.cpp
index 6cf8d63069..ca230c3b4e 100644
--- a/3rdparty/imgui/examples/imgui_impl_win32.cpp
+++ b/3rdparty/imgui/examples/imgui_impl_win32.cpp
@@ -13,6 +13,7 @@
 #ifndef WIN32_LEAN_AND_MEAN
 #define WIN32_LEAN_AND_MEAN
 #endif
+#define NOMINMAX
 #include <windows.h>
 #include <tchar.h>
 
diff --git a/3rdparty/imgui/examples/libs/gl3w/GL/gl3w.c b/3rdparty/imgui/examples/libs/gl3w/GL/gl3w.c
index 464e017788..784c0969cf 100644
--- a/3rdparty/imgui/examples/libs/gl3w/GL/gl3w.c
+++ b/3rdparty/imgui/examples/libs/gl3w/GL/gl3w.c
@@ -7,6 +7,7 @@
 
 #ifdef _WIN32
 #define WIN32_LEAN_AND_MEAN 1
+#define NOMINMAX
 #include <windows.h>
 
 static HMODULE libgl;
diff --git a/3rdparty/imgui/examples/libs/gl3w/GL/glcorearb.h b/3rdparty/imgui/examples/libs/gl3w/GL/glcorearb.h
index 07cb03e13a..d8f6581c68 100644
--- a/3rdparty/imgui/examples/libs/gl3w/GL/glcorearb.h
+++ b/3rdparty/imgui/examples/libs/gl3w/GL/glcorearb.h
@@ -57,6 +57,7 @@ extern "C" {
 
 #if defined(_WIN32) && !defined(APIENTRY) && !defined(__CYGWIN__) && !defined(__SCITECH_SNAP__)
 #define WIN32_LEAN_AND_MEAN 1
+#define NOMINMAX
 #include <windows.h>
 #endif
 
diff --git a/3rdparty/imgui/examples/libs/glfw/include/GLFW/glfw3native.h b/3rdparty/imgui/examples/libs/glfw/include/GLFW/glfw3native.h
index 9fa955e942..bc35dde0d5 100644
--- a/3rdparty/imgui/examples/libs/glfw/include/GLFW/glfw3native.h
+++ b/3rdparty/imgui/examples/libs/glfw/include/GLFW/glfw3native.h
@@ -85,7 +85,8 @@ extern "C" {
  // example to allow applications to correctly declare a GL_ARB_debug_output
  // callback) but windows.h assumes no one will define APIENTRY before it does
  #undef APIENTRY
- #include <windows.h>
+ #define NOMINMAX
+#include <windows.h>
 #elif defined(GLFW_EXPOSE_NATIVE_COCOA)
  #include <ApplicationServices/ApplicationServices.h>
  #if defined(__OBJC__)
diff --git a/3rdparty/imgui/imgui.cpp b/3rdparty/imgui/imgui.cpp
index 26359924f9..04237f811a 100644
--- a/3rdparty/imgui/imgui.cpp
+++ b/3rdparty/imgui/imgui.cpp
@@ -8723,8 +8723,10 @@ static void SettingsHandlerWindow_WriteAll(ImGuiContext* imgui_ctx, ImGuiSetting
 #define WIN32_LEAN_AND_MEAN
 #endif
 #ifndef __MINGW32__
-#include <Windows.h>
+#define NOMINMAX
+#include <windows.h>
 #else
+#define NOMINMAX
 #include <windows.h>
 #endif
 #endif
diff --git a/3rdparty/oourafft/fftsg.cc b/3rdparty/oourafft/fftsg.cc
index d74fbb15a0..8ee2e1877c 100644
--- a/3rdparty/oourafft/fftsg.cc
+++ b/3rdparty/oourafft/fftsg.cc
@@ -321,11 +321,41 @@ Appendix :
 
 NEXTPNR_NAMESPACE_BEGIN
 
+void makewt(int nw, int* ip, float* w);
+void cftfsub(int n, float* a, int* ip, int nw, float* w);
+void cftbsub(int n, float* a, int* ip, int nw, float* w);
+void makect(int nc, int* ip, float* c);
+void rftfsub(int n, float* a, int nc, float* c);
+void rftbsub(int n, float* a, int nc, float* c);
+void dctsub(int n, float* a, int nc, float* c);
+void dstsub(int n, float* a, int nc, float* c);
+void bitrv2(int n, int* ip, float* a);
+void bitrv216(float* a);
+void bitrv208(float* a);
+void cftf1st(int n, float* a, float* w);
+void cftrec4(int n, float* a, int nw, float* w);
+void cftleaf(int n, int isplt, float* a, int nw, float* w);
+void cftfx41(int n, float* a, int nw, float* w);
+void cftf161(float* a, float* w);
+void cftf081(float* a, float* w);
+void cftf040(float* a);
+void cftx020(float* a);
+void bitrv2conj(int n, int* ip, float* a);
+void bitrv216neg(float* a);
+void bitrv208neg(float* a);
+void cftb1st(int n, float* a, float* w);
+void cftb040(float* a);
+void makeipt(int nw, int* ip);
+void cftf162(float* a, float* w);
+void cftf082(float* a, float* w);
+void cftmdl1(int n, float* a, float* w);
+void cftmdl2(int n, float* a, float* w);
+int cfttree(int n, int j, int k, float* a, int nw, float* w);
+void* cftrec1_th(void* p);
+void* cftrec2_th(void* p);
+
 void cdft(int n, int isgn, float* a, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void cftbsub(int n, float* a, int* ip, int nw, float* w);
   int nw;
 
   nw = ip[0];
@@ -342,12 +372,6 @@ void cdft(int n, int isgn, float* a, int* ip, float* w)
 
 void rdft(int n, int isgn, float* a, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void cftbsub(int n, float* a, int* ip, int nw, float* w);
-  void rftfsub(int n, float* a, int nc, float* c);
-  void rftbsub(int n, float* a, int nc, float* c);
   int nw, nc;
   float xi;
 
@@ -385,13 +409,6 @@ void rdft(int n, int isgn, float* a, int* ip, float* w)
 
 void ddct(int n, int isgn, float* a, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void cftbsub(int n, float* a, int* ip, int nw, float* w);
-  void rftfsub(int n, float* a, int nc, float* c);
-  void rftbsub(int n, float* a, int nc, float* c);
-  void dctsub(int n, float* a, int nc, float* c);
   int j, nw, nc;
   float xr;
 
@@ -441,13 +458,6 @@ void ddct(int n, int isgn, float* a, int* ip, float* w)
 
 void ddst(int n, int isgn, float* a, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void cftbsub(int n, float* a, int* ip, int nw, float* w);
-  void rftfsub(int n, float* a, int nc, float* c);
-  void rftbsub(int n, float* a, int nc, float* c);
-  void dstsub(int n, float* a, int nc, float* c);
   int j, nw, nc;
   float xr;
 
@@ -496,11 +506,6 @@ void ddst(int n, int isgn, float* a, int* ip, float* w)
 
 void dfct(int n, float* a, float* t, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void rftfsub(int n, float* a, int nc, float* c);
-  void dctsub(int n, float* a, int nc, float* c);
   int j, k, l, m, mh, nw, nc;
   float xr, xi, yr, yi;
 
@@ -588,11 +593,6 @@ void dfct(int n, float* a, float* t, int* ip, float* w)
 
 void dfst(int n, float* a, float* t, int* ip, float* w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void cftfsub(int n, float* a, int* ip, int nw, float* w);
-  void rftfsub(int n, float* a, int nc, float* c);
-  void dstsub(int n, float* a, int nc, float* c);
   int j, k, l, m, mh, nw, nc;
   float xr, xi, yr, yi;
 
@@ -673,7 +673,6 @@ void dfst(int n, float* a, float* t, int* ip, float* w)
 
 void makewt(int nw, int* ip, float* w)
 {
-  void makeipt(int nw, int* ip);
   int j, nwh, nw0, nw1;
   float delta, wn4r, wk1r, wk1i, wk3r, wk3i;
 
@@ -808,6 +807,7 @@ void makect(int nc, int* ip, float* c)
 #endif
 #include <stdio.h>
 #include <stdlib.h>
+#define NOMINMAX
 #include <windows.h>
 #define cdft_thread_t HANDLE
 #define cdft_thread_create(thp, func, argp)                               \
@@ -829,17 +829,6 @@ void makect(int nc, int* ip, float* c)
 
 void cftfsub(int n, float* a, int* ip, int nw, float* w)
 {
-  void bitrv2(int n, int* ip, float* a);
-  void bitrv216(float* a);
-  void bitrv208(float* a);
-  void cftf1st(int n, float* a, float* w);
-  void cftrec4(int n, float* a, int nw, float* w);
-  void cftleaf(int n, int isplt, float* a, int nw, float* w);
-  void cftfx41(int n, float* a, int nw, float* w);
-  void cftf161(float* a, float* w);
-  void cftf081(float* a, float* w);
-  void cftf040(float* a);
-  void cftx020(float* a);
 #ifdef USE_CDFT_THREADS
   void cftrec4_th(int n, float* a, int nw, float* w);
 #endif /* USE_CDFT_THREADS */
@@ -876,17 +865,6 @@ void cftfsub(int n, float* a, int* ip, int nw, float* w)
 
 void cftbsub(int n, float* a, int* ip, int nw, float* w)
 {
-  void bitrv2conj(int n, int* ip, float* a);
-  void bitrv216neg(float* a);
-  void bitrv208neg(float* a);
-  void cftb1st(int n, float* a, float* w);
-  void cftrec4(int n, float* a, int nw, float* w);
-  void cftleaf(int n, int isplt, float* a, int nw, float* w);
-  void cftfx41(int n, float* a, int nw, float* w);
-  void cftf161(float* a, float* w);
-  void cftf081(float* a, float* w);
-  void cftb040(float* a);
-  void cftx020(float* a);
 #ifdef USE_CDFT_THREADS
   void cftrec4_th(int n, float* a, int nw, float* w);
 #endif /* USE_CDFT_THREADS */
@@ -2221,8 +2199,6 @@ typedef struct cdft_arg_st cdft_arg_t;
 
 void cftrec4_th(int n, float* a, int nw, float* w)
 {
-  void* cftrec1_th(void* p);
-  void* cftrec2_th(void* p);
   int i, idiv4, m, nthread;
   cdft_thread_t th[4];
   cdft_arg_t ag[4];
@@ -2254,9 +2230,6 @@ void cftrec4_th(int n, float* a, int nw, float* w)
 
 void* cftrec1_th(void* p)
 {
-  int cfttree(int n, int j, int k, float* a, int nw, float* w);
-  void cftleaf(int n, int isplt, float* a, int nw, float* w);
-  void cftmdl1(int n, float* a, float* w);
   int isplt, j, k, m, n, n0, nw;
   float *a, *w;
 
@@ -2282,9 +2255,6 @@ void* cftrec1_th(void* p)
 
 void* cftrec2_th(void* p)
 {
-  int cfttree(int n, int j, int k, float* a, int nw, float* w);
-  void cftleaf(int n, int isplt, float* a, int nw, float* w);
-  void cftmdl2(int n, float* a, float* w);
   int isplt, j, k, m, n, n0, nw;
   float *a, *w;
 
@@ -2313,9 +2283,6 @@ void* cftrec2_th(void* p)
 
 void cftrec4(int n, float* a, int nw, float* w)
 {
-  int cfttree(int n, int j, int k, float* a, int nw, float* w);
-  void cftleaf(int n, int isplt, float* a, int nw, float* w);
-  void cftmdl1(int n, float* a, float* w);
   int isplt, j, k, m;
 
   m = n;
@@ -2334,8 +2301,6 @@ void cftrec4(int n, float* a, int nw, float* w)
 
 int cfttree(int n, int j, int k, float* a, int nw, float* w)
 {
-  void cftmdl1(int n, float* a, float* w);
-  void cftmdl2(int n, float* a, float* w);
   int i, isplt, m;
 
   if ((k & 3) != 0) {
@@ -2368,12 +2333,6 @@ int cfttree(int n, int j, int k, float* a, int nw, float* w)
 
 void cftleaf(int n, int isplt, float* a, int nw, float* w)
 {
-  void cftmdl1(int n, float* a, float* w);
-  void cftmdl2(int n, float* a, float* w);
-  void cftf161(float* a, float* w);
-  void cftf162(float* a, float* w);
-  void cftf081(float* a, float* w);
-  void cftf082(float* a, float* w);
 
   if (n == 512) {
     cftmdl1(128, a, &w[nw - 64]);
@@ -2674,11 +2633,6 @@ void cftmdl2(int n, float* a, float* w)
 
 void cftfx41(int n, float* a, int nw, float* w)
 {
-  void cftf161(float* a, float* w);
-  void cftf162(float* a, float* w);
-  void cftf081(float* a, float* w);
-  void cftf082(float* a, float* w);
-
   if (n == 128) {
     cftf161(a, &w[nw - 8]);
     cftf162(&a[32], &w[nw - 32]);
diff --git a/3rdparty/oourafft/fftsg2d.cc b/3rdparty/oourafft/fftsg2d.cc
index 2bbc242824..5d674ed81e 100644
--- a/3rdparty/oourafft/fftsg2d.cc
+++ b/3rdparty/oourafft/fftsg2d.cc
@@ -412,6 +412,7 @@ macro definitions
 #ifndef FFT2D_THREADS_BEGIN_N
 #define FFT2D_THREADS_BEGIN_N 131072
 #endif
+#define NOMINMAX
 #include <windows.h>
 #define fft2d_thread_t HANDLE
 #define fft2d_thread_create(thp, func, argp)                       \
diff --git a/3rdparty/pybind11/docs/advanced/cast/strings.rst b/3rdparty/pybind11/docs/advanced/cast/strings.rst
index e246c5219a..806b7a256b 100644
--- a/3rdparty/pybind11/docs/advanced/cast/strings.rst
+++ b/3rdparty/pybind11/docs/advanced/cast/strings.rst
@@ -174,7 +174,8 @@ decoded to Python ``str``.
 .. code-block:: c++
 
     #define UNICODE
-    #include <windows.h>
+    #define NOMINMAX
+#include <windows.h>
 
     m.def("set_window_text",
         [](HWND hwnd, std::wstring s) {
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index ff906bfd7c..a27e261d1f 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -24,7 +24,6 @@
 #include <array>
 #include <vector>
 
-#define NOMINMAX
 #include "arch_api.h"
 #include "base_clusterinfo.h"
 #include "idstring.h"
diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 565f5fc555..087af5b3a6 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -46,8 +46,8 @@
 #include "version.h"
 
 #if defined(_WIN32)
-#define NOMINMAX
 #include <io.h>
+#define NOMINMAX
 #include <windows.h>
 #elif defined(__APPLE__)
 #include <dirent.h>
diff --git a/common/kernel/embed.cc b/common/kernel/embed.cc
index 6beb157be6..de7f545c2d 100644
--- a/common/kernel/embed.cc
+++ b/common/kernel/embed.cc
@@ -1,5 +1,6 @@
 #include <map>
 #if defined(WIN32)
+#define NOMINMAX
 #include <windows.h>
 #endif
 #include <boost/filesystem.hpp>
diff --git a/gui/application.cc b/gui/application.cc
index d3260684f7..b04d4a2f21 100644
--- a/gui/application.cc
+++ b/gui/application.cc
@@ -34,6 +34,7 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 #ifdef _WIN32
+#define NOMINMAX
 #include <windows.h>
 BOOL WINAPI WinHandler(DWORD dwCtrlType)
 {

From 7cac0249a1a666d7efb132cd62a0541f151f2370 Mon Sep 17 00:00:00 2001
From: Justin Rajewski <justin@alchitry.com>
Date: Thu, 26 Oct 2023 10:56:19 -0600
Subject: [PATCH 502/712] Fixes for building on windows

---
 3rdparty/oourafft/fftsg2d.cc | 1631 +++++++++++++++-------------------
 1 file changed, 740 insertions(+), 891 deletions(-)

diff --git a/3rdparty/oourafft/fftsg2d.cc b/3rdparty/oourafft/fftsg2d.cc
index 5d674ed81e..999861968d 100644
--- a/3rdparty/oourafft/fftsg2d.cc
+++ b/3rdparty/oourafft/fftsg2d.cc
@@ -366,17 +366,15 @@ macro definitions
         .
 */
 
-
-
 #include <stdio.h>
 #include <stdlib.h>
-#define fft2d_alloc_error_check(p)                        \
-  {                                                       \
-    if((p) == NULL) {                                     \
-      fprintf(stderr, "fft2d memory allocation error\n"); \
-      exit(1);                                            \
-    }                                                     \
-  }
+#define fft2d_alloc_error_check(p)                                                                                     \
+    {                                                                                                                  \
+        if ((p) == NULL) {                                                                                             \
+            fprintf(stderr, "fft2d memory allocation error\n");                                                        \
+            exit(1);                                                                                                   \
+        }                                                                                                              \
+    }
 
 #ifdef USE_FFT2D_PTHREADS
 #define USE_FFT2D_THREADS
@@ -388,20 +386,20 @@ macro definitions
 #endif
 #include <pthread.h>
 #define fft2d_thread_t pthread_t
-#define fft2d_thread_create(thp, func, argp)                   \
-  {                                                            \
-    if(pthread_create(thp, NULL, func, (void *)(argp)) != 0) { \
-      fprintf(stderr, "fft2d thread error\n");                 \
-      exit(1);                                                 \
-    }                                                          \
-  }
-#define fft2d_thread_wait(th)                  \
-  {                                            \
-    if(pthread_join(th, NULL) != 0) {          \
-      fprintf(stderr, "fft2d thread error\n"); \
-      exit(1);                                 \
-    }                                          \
-  }
+#define fft2d_thread_create(thp, func, argp)                                                                           \
+    {                                                                                                                  \
+        if (pthread_create(thp, NULL, func, (void *)(argp)) != 0) {                                                    \
+            fprintf(stderr, "fft2d thread error\n");                                                                   \
+            exit(1);                                                                                                   \
+        }                                                                                                              \
+    }
+#define fft2d_thread_wait(th)                                                                                          \
+    {                                                                                                                  \
+        if (pthread_join(th, NULL) != 0) {                                                                             \
+            fprintf(stderr, "fft2d thread error\n");                                                                   \
+            exit(1);                                                                                                   \
+        }                                                                                                              \
+    }
 #endif /* USE_FFT2D_PTHREADS */
 
 #ifdef USE_FFT2D_WINTHREADS
@@ -415,1005 +413,856 @@ macro definitions
 #define NOMINMAX
 #include <windows.h>
 #define fft2d_thread_t HANDLE
-#define fft2d_thread_create(thp, func, argp)                       \
-  {                                                                \
-    DWORD thid;                                                    \
-    *(thp) = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)(func), \
-                          (LPVOID)(argp), 0, &thid);               \
-    if(*(thp) == 0) {                                              \
-      fprintf(stderr, "fft2d thread error\n");                     \
-      exit(1);                                                     \
-    }                                                              \
-  }
-#define fft2d_thread_wait(th)          \
-  {                                    \
-    WaitForSingleObject(th, INFINITE); \
-    CloseHandle(th);                   \
-  }
+#define fft2d_thread_create(thp, func, argp)                                                                           \
+    {                                                                                                                  \
+        DWORD thid;                                                                                                    \
+        *(thp) = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)(func), (LPVOID)(argp), 0, &thid);                      \
+        if (*(thp) == 0) {                                                                                             \
+            fprintf(stderr, "fft2d thread error\n");                                                                   \
+            exit(1);                                                                                                   \
+        }                                                                                                              \
+    }
+#define fft2d_thread_wait(th)                                                                                          \
+    {                                                                                                                  \
+        WaitForSingleObject(th, INFINITE);                                                                             \
+        CloseHandle(th);                                                                                               \
+    }
 #endif /* USE_FFT2D_WINTHREADS */
 
 #include "nextpnr_namespaces.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
+void ddct(int n, int isgn, float *a, int *ip, float *w);
+void ddst(int n, int isgn, float *a, int *ip, float *w);
+void cdft(int n, int isgn, float *a, int *ip, float *w);
+void *cdft2d_th(void *p);
+void *ddxt2d0_th(void *p);
+void *ddxt2d_th(void *p);
+void rdft(int n, int isgn, float *a, int *ip, float *w);
+void makewt(int nw, int *ip, float *w);
+void cdft2d_sub(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w);
+void makect(int nc, int *ip, float *c);
+void rdft2d_sub(int n1, int isgn, float **a);
+void ddxt2d_sub(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w);
 
-void cdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
-{
-  void makewt(int nw, int* ip, float* w);
-  void cdft(int n, int isgn, float* a, int* ip, float* w);
-  void cdft2d_sub(
-      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
 #ifdef USE_FFT2D_THREADS
-  void xdft2d0_subth(
-      int n1, int n2, int icr, int isgn, float** a, int* ip, float* w);
-  void cdft2d_subth(
-      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
+void xdft2d0_subth(int n1, int n2, int icr, int isgn, float **a, int *ip, float *w);
+void cdft2d_subth(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w);
+void ddxt2d0_subth(int n1, int n2, int ics, int isgn, float **a, int *ip, float *w);
+void ddxt2d_subth(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w);
 #endif /* USE_FFT2D_THREADS */
-  int n, itnull, nthread, nt, i;
 
-  n = n1 << 1;
-  if (n < n2) {
-    n = n2;
-  }
-  if (n > (ip[0] << 2)) {
-    makewt(n >> 2, ip, w);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
+void cdft2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+{
+    int n, itnull, nthread, nt, i;
+
+    n = n1 << 1;
+    if (n < n2) {
+        n = n2;
+    }
+    if (n > (ip[0] << 2)) {
+        makewt(n >> 2, ip, w);
+    }
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
 #ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-    nt = 8 * nthread * n1;
-    if (n2 == 4 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 4 * nthread) {
-      nt >>= 2;
+        nt = 8 * nthread * n1;
+        if (n2 == 4 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 4 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
 #ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    xdft2d0_subth(n1, n2, 0, isgn, a, ip, w);
-    cdft2d_subth(n1, n2, isgn, a, t, ip, w);
-  } else
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        xdft2d0_subth(n1, n2, 0, isgn, a, ip, w);
+        cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+    } else
 #endif /* USE_FFT2D_THREADS */
-  {
-    for (i = 0; i < n1; i++) {
-      cdft(n2, isgn, a[i], ip, w);
+    {
+        for (i = 0; i < n1; i++) {
+            cdft(n2, isgn, a[i], ip, w);
+        }
+        cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+    }
+    if (itnull != 0) {
+        free(t);
     }
-    cdft2d_sub(n1, n2, isgn, a, t, ip, w);
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
-void rdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+void rdft2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void rdft(int n, int isgn, float* a, int* ip, float* w);
-  void cdft2d_sub(
-      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
-  void rdft2d_sub(int n1, int isgn, float** a);
-#ifdef USE_FFT2D_THREADS
-  void xdft2d0_subth(
-      int n1, int n2, int icr, int isgn, float** a, int* ip, float* w);
-  void cdft2d_subth(
-      int n1, int n2, int isgn, float** a, float* t, int* ip, float* w);
-#endif /* USE_FFT2D_THREADS */
-  int n, nw, nc, itnull, nthread, nt, i;
+    int n, nw, nc, itnull, nthread, nt, i;
 
-  n = n1 << 1;
-  if (n < n2) {
-    n = n2;
-  }
-  nw = ip[0];
-  if (n > (nw << 2)) {
-    nw = n >> 2;
-    makewt(nw, ip, w);
-  }
-  nc = ip[1];
-  if (n2 > (nc << 2)) {
-    nc = n2 >> 2;
-    makect(nc, ip, w + nw);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
-#ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
-#endif /* USE_FFT2D_THREADS */
-    nt = 8 * nthread * n1;
-    if (n2 == 4 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 4 * nthread) {
-      nt >>= 2;
+    n = n1 << 1;
+    if (n < n2) {
+        n = n2;
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
-#ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    if (isgn < 0) {
-      rdft2d_sub(n1, isgn, a);
-      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+    nw = ip[0];
+    if (n > (nw << 2)) {
+        nw = n >> 2;
+        makewt(nw, ip, w);
     }
-    xdft2d0_subth(n1, n2, 1, isgn, a, ip, w);
-    if (isgn >= 0) {
-      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
-      rdft2d_sub(n1, isgn, a);
+    nc = ip[1];
+    if (n2 > (nc << 2)) {
+        nc = n2 >> 2;
+        makect(nc, ip, w + nw);
     }
-  } else
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
+#ifdef USE_FFT2D_THREADS
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-  {
-    if (isgn < 0) {
-      rdft2d_sub(n1, isgn, a);
-      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+        nt = 8 * nthread * n1;
+        if (n2 == 4 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 4 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    for (i = 0; i < n1; i++) {
-      rdft(n2, isgn, a[i], ip, w);
+#ifdef USE_FFT2D_THREADS
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        if (isgn < 0) {
+            rdft2d_sub(n1, isgn, a);
+            cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+        }
+        xdft2d0_subth(n1, n2, 1, isgn, a, ip, w);
+        if (isgn >= 0) {
+            cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+            rdft2d_sub(n1, isgn, a);
+        }
+    } else
+#endif /* USE_FFT2D_THREADS */
+    {
+        if (isgn < 0) {
+            rdft2d_sub(n1, isgn, a);
+            cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+        }
+        for (i = 0; i < n1; i++) {
+            rdft(n2, isgn, a[i], ip, w);
+        }
+        if (isgn >= 0) {
+            cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+            rdft2d_sub(n1, isgn, a);
+        }
     }
-    if (isgn >= 0) {
-      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
-      rdft2d_sub(n1, isgn, a);
+    if (itnull != 0) {
+        free(t);
     }
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
-void rdft2dsort(int n1, int n2, int isgn, float** a)
+void rdft2dsort(int n1, int n2, int isgn, float **a)
 {
-  int n1h, i;
-  float x, y;
+    int n1h, i;
+    float x, y;
 
-  n1h = n1 >> 1;
-  if (isgn < 0) {
-    for (i = n1h + 1; i < n1; i++) {
-      a[i][0] = a[i][n2 + 1];
-      a[i][1] = a[i][n2];
-    }
-    a[0][1] = a[0][n2];
-    a[n1h][1] = a[n1h][n2];
-  } else {
-    for (i = n1h + 1; i < n1; i++) {
-      y = a[i][0];
-      x = a[i][1];
-      a[i][n2] = x;
-      a[i][n2 + 1] = y;
-      a[n1 - i][n2] = x;
-      a[n1 - i][n2 + 1] = -y;
-      a[i][0] = a[n1 - i][0];
-      a[i][1] = -a[n1 - i][1];
+    n1h = n1 >> 1;
+    if (isgn < 0) {
+        for (i = n1h + 1; i < n1; i++) {
+            a[i][0] = a[i][n2 + 1];
+            a[i][1] = a[i][n2];
+        }
+        a[0][1] = a[0][n2];
+        a[n1h][1] = a[n1h][n2];
+    } else {
+        for (i = n1h + 1; i < n1; i++) {
+            y = a[i][0];
+            x = a[i][1];
+            a[i][n2] = x;
+            a[i][n2 + 1] = y;
+            a[n1 - i][n2] = x;
+            a[n1 - i][n2 + 1] = -y;
+            a[i][0] = a[n1 - i][0];
+            a[i][1] = -a[n1 - i][1];
+        }
+        a[0][n2] = a[0][1];
+        a[0][n2 + 1] = 0;
+        a[0][1] = 0;
+        a[n1h][n2] = a[n1h][1];
+        a[n1h][n2 + 1] = 0;
+        a[n1h][1] = 0;
     }
-    a[0][n2] = a[0][1];
-    a[0][n2 + 1] = 0;
-    a[0][1] = 0;
-    a[n1h][n2] = a[n1h][1];
-    a[n1h][n2 + 1] = 0;
-    a[n1h][1] = 0;
-  }
 }
 
-void ddcst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+void ddcst2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  void ddxt2d_sub(int n1,
-                  int n2,
-                  int ics,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w);
-#ifdef USE_FFT2D_THREADS
-  void ddxt2d0_subth(
-      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
-  void ddxt2d_subth(int n1,
-                    int n2,
-                    int ics,
-                    int isgn,
-                    float** a,
-                    float* t,
-                    int* ip,
-                    float* w);
-#endif /* USE_FFT2D_THREADS */
-  int n, nw, nc, itnull, nthread, nt, i;
+    int n, nw, nc, itnull, nthread, nt, i;
 
-  n = n1;
-  if (n < n2) {
-    n = n2;
-  }
-  nw = ip[0];
-  if (n > (nw << 2)) {
-    nw = n >> 2;
-    makewt(nw, ip, w);
-  }
-  nc = ip[1];
-  if (n > nc) {
-    nc = n;
-    makect(nc, ip, w + nw);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
+    n = n1;
+    if (n < n2) {
+        n = n2;
+    }
+    nw = ip[0];
+    if (n > (nw << 2)) {
+        nw = n >> 2;
+        makewt(nw, ip, w);
+    }
+    nc = ip[1];
+    if (n > nc) {
+        nc = n;
+        makect(nc, ip, w + nw);
+    }
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
 #ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-    nt = 4 * nthread * n1;
-    if (n2 == 2 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 2 * nthread) {
-      nt >>= 2;
+        nt = 4 * nthread * n1;
+        if (n2 == 2 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 2 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
 #ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
-    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
-  } else
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+        ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+    } else
 #endif /* USE_FFT2D_THREADS */
-  {
-    for (i = 0; i < n1; i++) {
-      ddst(n2, isgn, a[i], ip, w);
+    {
+        for (i = 0; i < n1; i++) {
+            ddst(n2, isgn, a[i], ip, w);
+        }
+        ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+    }
+    if (itnull != 0) {
+        free(t);
     }
-    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
-void ddsct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+void ddsct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  void ddxt2d_sub(int n1,
-                  int n2,
-                  int ics,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w);
-#ifdef USE_FFT2D_THREADS
-  void ddxt2d0_subth(
-      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
-  void ddxt2d_subth(int n1,
-                    int n2,
-                    int ics,
-                    int isgn,
-                    float** a,
-                    float* t,
-                    int* ip,
-                    float* w);
-#endif /* USE_FFT2D_THREADS */
-  int n, nw, nc, itnull, nthread, nt, i;
+    int n, nw, nc, itnull, nthread, nt, i;
 
-  n = n1;
-  if (n < n2) {
-    n = n2;
-  }
-  nw = ip[0];
-  if (n > (nw << 2)) {
-    nw = n >> 2;
-    makewt(nw, ip, w);
-  }
-  nc = ip[1];
-  if (n > nc) {
-    nc = n;
-    makect(nc, ip, w + nw);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
+    n = n1;
+    if (n < n2) {
+        n = n2;
+    }
+    nw = ip[0];
+    if (n > (nw << 2)) {
+        nw = n >> 2;
+        makewt(nw, ip, w);
+    }
+    nc = ip[1];
+    if (n > nc) {
+        nc = n;
+        makect(nc, ip, w + nw);
+    }
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
 #ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-    nt = 4 * nthread * n1;
-    if (n2 == 2 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 2 * nthread) {
-      nt >>= 2;
+        nt = 4 * nthread * n1;
+        if (n2 == 2 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 2 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
 #ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
-    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
-  } else
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+        ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+    } else
 #endif /* USE_FFT2D_THREADS */
-  {
-    for (i = 0; i < n1; i++) {
-      ddct(n2, isgn, a[i], ip, w);
+    {
+        for (i = 0; i < n1; i++) {
+            ddct(n2, isgn, a[i], ip, w);
+        }
+        ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+    }
+    if (itnull != 0) {
+        free(t);
     }
-    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
-void ddct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+void ddct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddxt2d_sub(int n1,
-                  int n2,
-                  int ics,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w);
-#ifdef USE_FFT2D_THREADS
-  void ddxt2d0_subth(
-      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
-  void ddxt2d_subth(int n1,
-                    int n2,
-                    int ics,
-                    int isgn,
-                    float** a,
-                    float* t,
-                    int* ip,
-                    float* w);
-#endif /* USE_FFT2D_THREADS */
-  int n, nw, nc, itnull, nthread, nt, i;
+    int n, nw, nc, itnull, nthread, nt, i;
 
-  n = n1;
-  if (n < n2) {
-    n = n2;
-  }
-  nw = ip[0];
-  if (n > (nw << 2)) {
-    nw = n >> 2;
-    makewt(nw, ip, w);
-  }
-  nc = ip[1];
-  if (n > nc) {
-    nc = n;
-    makect(nc, ip, w + nw);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
+    n = n1;
+    if (n < n2) {
+        n = n2;
+    }
+    nw = ip[0];
+    if (n > (nw << 2)) {
+        nw = n >> 2;
+        makewt(nw, ip, w);
+    }
+    nc = ip[1];
+    if (n > nc) {
+        nc = n;
+        makect(nc, ip, w + nw);
+    }
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
 #ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-    nt = 4 * nthread * n1;
-    if (n2 == 2 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 2 * nthread) {
-      nt >>= 2;
+        nt = 4 * nthread * n1;
+        if (n2 == 2 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 2 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
 #ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
-    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
-  } else
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+        ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+    } else
 #endif /* USE_FFT2D_THREADS */
-  {
-    for (i = 0; i < n1; i++) {
-      ddct(n2, isgn, a[i], ip, w);
+    {
+        for (i = 0; i < n1; i++) {
+            ddct(n2, isgn, a[i], ip, w);
+        }
+        ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+    }
+    if (itnull != 0) {
+        free(t);
     }
-    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
-void ddst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
+void ddst2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void makewt(int nw, int* ip, float* w);
-  void makect(int nc, int* ip, float* c);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  void ddxt2d_sub(int n1,
-                  int n2,
-                  int ics,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w);
-#ifdef USE_FFT2D_THREADS
-  void ddxt2d0_subth(
-      int n1, int n2, int ics, int isgn, float** a, int* ip, float* w);
-  void ddxt2d_subth(int n1,
-                    int n2,
-                    int ics,
-                    int isgn,
-                    float** a,
-                    float* t,
-                    int* ip,
-                    float* w);
-#endif /* USE_FFT2D_THREADS */
-  int n, nw, nc, itnull, nthread, nt, i;
+    int n, nw, nc, itnull, nthread, nt, i;
 
-  n = n1;
-  if (n < n2) {
-    n = n2;
-  }
-  nw = ip[0];
-  if (n > (nw << 2)) {
-    nw = n >> 2;
-    makewt(nw, ip, w);
-  }
-  nc = ip[1];
-  if (n > nc) {
-    nc = n;
-    makect(nc, ip, w + nw);
-  }
-  itnull = 0;
-  if (t == NULL) {
-    itnull = 1;
-    nthread = 1;
+    n = n1;
+    if (n < n2) {
+        n = n2;
+    }
+    nw = ip[0];
+    if (n > (nw << 2)) {
+        nw = n >> 2;
+        makewt(nw, ip, w);
+    }
+    nc = ip[1];
+    if (n > nc) {
+        nc = n;
+        makect(nc, ip, w + nw);
+    }
+    itnull = 0;
+    if (t == NULL) {
+        itnull = 1;
+        nthread = 1;
 #ifdef USE_FFT2D_THREADS
-    nthread = FFT2D_MAX_THREADS;
+        nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-    nt = 4 * nthread * n1;
-    if (n2 == 2 * nthread) {
-      nt >>= 1;
-    } else if (n2 < 2 * nthread) {
-      nt >>= 2;
+        nt = 4 * nthread * n1;
+        if (n2 == 2 * nthread) {
+            nt >>= 1;
+        } else if (n2 < 2 * nthread) {
+            nt >>= 2;
+        }
+        t = (float *)malloc(sizeof(float) * nt);
+        fft2d_alloc_error_check(t);
     }
-    t = (float*) malloc(sizeof(float) * nt);
-    fft2d_alloc_error_check(t);
-  }
 #ifdef USE_FFT2D_THREADS
-  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
-    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
-    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
-  } else
+    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
+        ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+        ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+    } else
 #endif /* USE_FFT2D_THREADS */
-  {
-    for (i = 0; i < n1; i++) {
-      ddst(n2, isgn, a[i], ip, w);
+    {
+        for (i = 0; i < n1; i++) {
+            ddst(n2, isgn, a[i], ip, w);
+        }
+        ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+    }
+    if (itnull != 0) {
+        free(t);
     }
-    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
-  }
-  if (itnull != 0) {
-    free(t);
-  }
 }
 
 /* -------- child routines -------- */
 
-void cdft2d_sub(int n1,
-                int n2,
-                int isgn,
-                float** a,
-                float* t,
-                int* ip,
-                float* w)
+void cdft2d_sub(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void cdft(int n, int isgn, float* a, int* ip, float* w);
-  int i, j;
+    int i, j;
 
-  if (n2 > 4) {
-    for (j = 0; j < n2; j += 8) {
-      for (i = 0; i < n1; i++) {
-        t[2 * i] = a[i][j];
-        t[2 * i + 1] = a[i][j + 1];
-        t[2 * n1 + 2 * i] = a[i][j + 2];
-        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
-        t[4 * n1 + 2 * i] = a[i][j + 4];
-        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
-        t[6 * n1 + 2 * i] = a[i][j + 6];
-        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
-      }
-      cdft(2 * n1, isgn, t, ip, w);
-      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
-      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
-      for (i = 0; i < n1; i++) {
-        a[i][j] = t[2 * i];
-        a[i][j + 1] = t[2 * i + 1];
-        a[i][j + 2] = t[2 * n1 + 2 * i];
-        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
-        a[i][j + 4] = t[4 * n1 + 2 * i];
-        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
-        a[i][j + 6] = t[6 * n1 + 2 * i];
-        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
-      }
-    }
-  } else if (n2 == 4) {
-    for (i = 0; i < n1; i++) {
-      t[2 * i] = a[i][0];
-      t[2 * i + 1] = a[i][1];
-      t[2 * n1 + 2 * i] = a[i][2];
-      t[2 * n1 + 2 * i + 1] = a[i][3];
-    }
-    cdft(2 * n1, isgn, t, ip, w);
-    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-    for (i = 0; i < n1; i++) {
-      a[i][0] = t[2 * i];
-      a[i][1] = t[2 * i + 1];
-      a[i][2] = t[2 * n1 + 2 * i];
-      a[i][3] = t[2 * n1 + 2 * i + 1];
-    }
-  } else if (n2 == 2) {
-    for (i = 0; i < n1; i++) {
-      t[2 * i] = a[i][0];
-      t[2 * i + 1] = a[i][1];
-    }
-    cdft(2 * n1, isgn, t, ip, w);
-    for (i = 0; i < n1; i++) {
-      a[i][0] = t[2 * i];
-      a[i][1] = t[2 * i + 1];
+    if (n2 > 4) {
+        for (j = 0; j < n2; j += 8) {
+            for (i = 0; i < n1; i++) {
+                t[2 * i] = a[i][j];
+                t[2 * i + 1] = a[i][j + 1];
+                t[2 * n1 + 2 * i] = a[i][j + 2];
+                t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+                t[4 * n1 + 2 * i] = a[i][j + 4];
+                t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+                t[6 * n1 + 2 * i] = a[i][j + 6];
+                t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+            }
+            cdft(2 * n1, isgn, t, ip, w);
+            cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+            cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+            cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+            for (i = 0; i < n1; i++) {
+                a[i][j] = t[2 * i];
+                a[i][j + 1] = t[2 * i + 1];
+                a[i][j + 2] = t[2 * n1 + 2 * i];
+                a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+                a[i][j + 4] = t[4 * n1 + 2 * i];
+                a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+                a[i][j + 6] = t[6 * n1 + 2 * i];
+                a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+            }
+        }
+    } else if (n2 == 4) {
+        for (i = 0; i < n1; i++) {
+            t[2 * i] = a[i][0];
+            t[2 * i + 1] = a[i][1];
+            t[2 * n1 + 2 * i] = a[i][2];
+            t[2 * n1 + 2 * i + 1] = a[i][3];
+        }
+        cdft(2 * n1, isgn, t, ip, w);
+        cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+        for (i = 0; i < n1; i++) {
+            a[i][0] = t[2 * i];
+            a[i][1] = t[2 * i + 1];
+            a[i][2] = t[2 * n1 + 2 * i];
+            a[i][3] = t[2 * n1 + 2 * i + 1];
+        }
+    } else if (n2 == 2) {
+        for (i = 0; i < n1; i++) {
+            t[2 * i] = a[i][0];
+            t[2 * i + 1] = a[i][1];
+        }
+        cdft(2 * n1, isgn, t, ip, w);
+        for (i = 0; i < n1; i++) {
+            a[i][0] = t[2 * i];
+            a[i][1] = t[2 * i + 1];
+        }
     }
-  }
 }
 
-void rdft2d_sub(int n1, int isgn, float** a)
+void rdft2d_sub(int n1, int isgn, float **a)
 {
-  int n1h, i, j;
-  float xi;
+    int n1h, i, j;
+    float xi;
 
-  n1h = n1 >> 1;
-  if (isgn < 0) {
-    for (i = 1; i < n1h; i++) {
-      j = n1 - i;
-      xi = a[i][0] - a[j][0];
-      a[i][0] += a[j][0];
-      a[j][0] = xi;
-      xi = a[j][1] - a[i][1];
-      a[i][1] += a[j][1];
-      a[j][1] = xi;
-    }
-  } else {
-    for (i = 1; i < n1h; i++) {
-      j = n1 - i;
-      a[j][0] = 0.5 * (a[i][0] - a[j][0]);
-      a[i][0] -= a[j][0];
-      a[j][1] = 0.5 * (a[i][1] + a[j][1]);
-      a[i][1] -= a[j][1];
+    n1h = n1 >> 1;
+    if (isgn < 0) {
+        for (i = 1; i < n1h; i++) {
+            j = n1 - i;
+            xi = a[i][0] - a[j][0];
+            a[i][0] += a[j][0];
+            a[j][0] = xi;
+            xi = a[j][1] - a[i][1];
+            a[i][1] += a[j][1];
+            a[j][1] = xi;
+        }
+    } else {
+        for (i = 1; i < n1h; i++) {
+            j = n1 - i;
+            a[j][0] = 0.5 * (a[i][0] - a[j][0]);
+            a[i][0] -= a[j][0];
+            a[j][1] = 0.5 * (a[i][1] + a[j][1]);
+            a[i][1] -= a[j][1];
+        }
     }
-  }
 }
 
-void ddxt2d_sub(int n1,
-                int n2,
-                int ics,
-                int isgn,
-                float** a,
-                float* t,
-                int* ip,
-                float* w)
+void ddxt2d_sub(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  int i, j;
+    int i, j;
 
-  if (n2 > 2) {
-    for (j = 0; j < n2; j += 4) {
-      for (i = 0; i < n1; i++) {
-        t[i] = a[i][j];
-        t[n1 + i] = a[i][j + 1];
-        t[2 * n1 + i] = a[i][j + 2];
-        t[3 * n1 + i] = a[i][j + 3];
-      }
-      if (ics == 0) {
-        ddct(n1, isgn, t, ip, w);
-        ddct(n1, isgn, &t[n1], ip, w);
-        ddct(n1, isgn, &t[2 * n1], ip, w);
-        ddct(n1, isgn, &t[3 * n1], ip, w);
-      } else {
-        ddst(n1, isgn, t, ip, w);
-        ddst(n1, isgn, &t[n1], ip, w);
-        ddst(n1, isgn, &t[2 * n1], ip, w);
-        ddst(n1, isgn, &t[3 * n1], ip, w);
-      }
-      for (i = 0; i < n1; i++) {
-        a[i][j] = t[i];
-        a[i][j + 1] = t[n1 + i];
-        a[i][j + 2] = t[2 * n1 + i];
-        a[i][j + 3] = t[3 * n1 + i];
-      }
-    }
-  } else if (n2 == 2) {
-    for (i = 0; i < n1; i++) {
-      t[i] = a[i][0];
-      t[n1 + i] = a[i][1];
-    }
-    if (ics == 0) {
-      ddct(n1, isgn, t, ip, w);
-      ddct(n1, isgn, &t[n1], ip, w);
-    } else {
-      ddst(n1, isgn, t, ip, w);
-      ddst(n1, isgn, &t[n1], ip, w);
-    }
-    for (i = 0; i < n1; i++) {
-      a[i][0] = t[i];
-      a[i][1] = t[n1 + i];
+    if (n2 > 2) {
+        for (j = 0; j < n2; j += 4) {
+            for (i = 0; i < n1; i++) {
+                t[i] = a[i][j];
+                t[n1 + i] = a[i][j + 1];
+                t[2 * n1 + i] = a[i][j + 2];
+                t[3 * n1 + i] = a[i][j + 3];
+            }
+            if (ics == 0) {
+                ddct(n1, isgn, t, ip, w);
+                ddct(n1, isgn, &t[n1], ip, w);
+                ddct(n1, isgn, &t[2 * n1], ip, w);
+                ddct(n1, isgn, &t[3 * n1], ip, w);
+            } else {
+                ddst(n1, isgn, t, ip, w);
+                ddst(n1, isgn, &t[n1], ip, w);
+                ddst(n1, isgn, &t[2 * n1], ip, w);
+                ddst(n1, isgn, &t[3 * n1], ip, w);
+            }
+            for (i = 0; i < n1; i++) {
+                a[i][j] = t[i];
+                a[i][j + 1] = t[n1 + i];
+                a[i][j + 2] = t[2 * n1 + i];
+                a[i][j + 3] = t[3 * n1 + i];
+            }
+        }
+    } else if (n2 == 2) {
+        for (i = 0; i < n1; i++) {
+            t[i] = a[i][0];
+            t[n1 + i] = a[i][1];
+        }
+        if (ics == 0) {
+            ddct(n1, isgn, t, ip, w);
+            ddct(n1, isgn, &t[n1], ip, w);
+        } else {
+            ddst(n1, isgn, t, ip, w);
+            ddst(n1, isgn, &t[n1], ip, w);
+        }
+        for (i = 0; i < n1; i++) {
+            a[i][0] = t[i];
+            a[i][1] = t[n1 + i];
+        }
     }
-  }
 }
 
 #ifdef USE_FFT2D_THREADS
 struct fft2d_arg_st
 {
-  int nthread;
-  int n0;
-  int n1;
-  int n2;
-  int ic;
-  int isgn;
-  float** a;
-  float* t;
-  int* ip;
-  float* w;
+    int nthread;
+    int n0;
+    int n1;
+    int n2;
+    int ic;
+    int isgn;
+    float **a;
+    float *t;
+    int *ip;
+    float *w;
 };
 typedef struct fft2d_arg_st fft2d_arg_t;
 
-void xdft2d0_subth(int n1,
-                   int n2,
-                   int icr,
-                   int isgn,
-                   float** a,
-                   int* ip,
-                   float* w)
+void xdft2d0_subth(int n1, int n2, int icr, int isgn, float **a, int *ip, float *w)
 {
-  void* xdft2d0_th(void* p);
-  fft2d_thread_t th[FFT2D_MAX_THREADS];
-  fft2d_arg_t ag[FFT2D_MAX_THREADS];
-  int nthread, i;
-
-  nthread = FFT2D_MAX_THREADS;
-  if (nthread > n1) {
-    nthread = n1;
-  }
-  for (i = 0; i < nthread; i++) {
-    ag[i].nthread = nthread;
-    ag[i].n0 = i;
-    ag[i].n1 = n1;
-    ag[i].n2 = n2;
-    ag[i].ic = icr;
-    ag[i].isgn = isgn;
-    ag[i].a = a;
-    ag[i].ip = ip;
-    ag[i].w = w;
-    fft2d_thread_create(&th[i], xdft2d0_th, &ag[i]);
-  }
-  for (i = 0; i < nthread; i++) {
-    fft2d_thread_wait(th[i]);
-  }
-}
+    void *xdft2d0_th(void *p);
+    fft2d_thread_t th[FFT2D_MAX_THREADS];
+    fft2d_arg_t ag[FFT2D_MAX_THREADS];
+    int nthread, i;
 
-void cdft2d_subth(int n1,
-                  int n2,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w)
-{
-  void* cdft2d_th(void* p);
-  fft2d_thread_t th[FFT2D_MAX_THREADS];
-  fft2d_arg_t ag[FFT2D_MAX_THREADS];
-  int nthread, nt, i;
-
-  nthread = FFT2D_MAX_THREADS;
-  nt = 8 * n1;
-  if (n2 == 4 * FFT2D_MAX_THREADS) {
-    nt >>= 1;
-  } else if (n2 < 4 * FFT2D_MAX_THREADS) {
-    nthread = n2 >> 1;
-    nt >>= 2;
-  }
-  for (i = 0; i < nthread; i++) {
-    ag[i].nthread = nthread;
-    ag[i].n0 = i;
-    ag[i].n1 = n1;
-    ag[i].n2 = n2;
-    ag[i].isgn = isgn;
-    ag[i].a = a;
-    ag[i].t = &t[nt * i];
-    ag[i].ip = ip;
-    ag[i].w = w;
-    fft2d_thread_create(&th[i], cdft2d_th, &ag[i]);
-  }
-  for (i = 0; i < nthread; i++) {
-    fft2d_thread_wait(th[i]);
-  }
+    nthread = FFT2D_MAX_THREADS;
+    if (nthread > n1) {
+        nthread = n1;
+    }
+    for (i = 0; i < nthread; i++) {
+        ag[i].nthread = nthread;
+        ag[i].n0 = i;
+        ag[i].n1 = n1;
+        ag[i].n2 = n2;
+        ag[i].ic = icr;
+        ag[i].isgn = isgn;
+        ag[i].a = a;
+        ag[i].ip = ip;
+        ag[i].w = w;
+        fft2d_thread_create(&th[i], xdft2d0_th, &ag[i]);
+    }
+    for (i = 0; i < nthread; i++) {
+        fft2d_thread_wait(th[i]);
+    }
 }
 
-void ddxt2d0_subth(int n1,
-                   int n2,
-                   int ics,
-                   int isgn,
-                   float** a,
-                   int* ip,
-                   float* w)
+void cdft2d_subth(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void* ddxt2d0_th(void* p);
-  fft2d_thread_t th[FFT2D_MAX_THREADS];
-  fft2d_arg_t ag[FFT2D_MAX_THREADS];
-  int nthread, i;
+    fft2d_thread_t th[FFT2D_MAX_THREADS];
+    fft2d_arg_t ag[FFT2D_MAX_THREADS];
+    int nthread, nt, i;
 
-  nthread = FFT2D_MAX_THREADS;
-  if (nthread > n1) {
-    nthread = n1;
-  }
-  for (i = 0; i < nthread; i++) {
-    ag[i].nthread = nthread;
-    ag[i].n0 = i;
-    ag[i].n1 = n1;
-    ag[i].n2 = n2;
-    ag[i].ic = ics;
-    ag[i].isgn = isgn;
-    ag[i].a = a;
-    ag[i].ip = ip;
-    ag[i].w = w;
-    fft2d_thread_create(&th[i], ddxt2d0_th, &ag[i]);
-  }
-  for (i = 0; i < nthread; i++) {
-    fft2d_thread_wait(th[i]);
-  }
+    nthread = FFT2D_MAX_THREADS;
+    nt = 8 * n1;
+    if (n2 == 4 * FFT2D_MAX_THREADS) {
+        nt >>= 1;
+    } else if (n2 < 4 * FFT2D_MAX_THREADS) {
+        nthread = n2 >> 1;
+        nt >>= 2;
+    }
+    for (i = 0; i < nthread; i++) {
+        ag[i].nthread = nthread;
+        ag[i].n0 = i;
+        ag[i].n1 = n1;
+        ag[i].n2 = n2;
+        ag[i].isgn = isgn;
+        ag[i].a = a;
+        ag[i].t = &t[nt * i];
+        ag[i].ip = ip;
+        ag[i].w = w;
+        fft2d_thread_create(&th[i], cdft2d_th, &ag[i]);
+    }
+    for (i = 0; i < nthread; i++) {
+        fft2d_thread_wait(th[i]);
+    }
 }
 
-void ddxt2d_subth(int n1,
-                  int n2,
-                  int ics,
-                  int isgn,
-                  float** a,
-                  float* t,
-                  int* ip,
-                  float* w)
+void ddxt2d0_subth(int n1, int n2, int ics, int isgn, float **a, int *ip, float *w)
 {
-  void* ddxt2d_th(void* p);
-  fft2d_thread_t th[FFT2D_MAX_THREADS];
-  fft2d_arg_t ag[FFT2D_MAX_THREADS];
-  int nthread, nt, i;
+    fft2d_thread_t th[FFT2D_MAX_THREADS];
+    fft2d_arg_t ag[FFT2D_MAX_THREADS];
+    int nthread, i;
 
-  nthread = FFT2D_MAX_THREADS;
-  nt = 4 * n1;
-  if (n2 == 2 * FFT2D_MAX_THREADS) {
-    nt >>= 1;
-  } else if (n2 < 2 * FFT2D_MAX_THREADS) {
-    nthread = n2;
-    nt >>= 2;
-  }
-  for (i = 0; i < nthread; i++) {
-    ag[i].nthread = nthread;
-    ag[i].n0 = i;
-    ag[i].n1 = n1;
-    ag[i].n2 = n2;
-    ag[i].ic = ics;
-    ag[i].isgn = isgn;
-    ag[i].a = a;
-    ag[i].t = &t[nt * i];
-    ag[i].ip = ip;
-    ag[i].w = w;
-    fft2d_thread_create(&th[i], ddxt2d_th, &ag[i]);
-  }
-  for (i = 0; i < nthread; i++) {
-    fft2d_thread_wait(th[i]);
-  }
+    nthread = FFT2D_MAX_THREADS;
+    if (nthread > n1) {
+        nthread = n1;
+    }
+    for (i = 0; i < nthread; i++) {
+        ag[i].nthread = nthread;
+        ag[i].n0 = i;
+        ag[i].n1 = n1;
+        ag[i].n2 = n2;
+        ag[i].ic = ics;
+        ag[i].isgn = isgn;
+        ag[i].a = a;
+        ag[i].ip = ip;
+        ag[i].w = w;
+        fft2d_thread_create(&th[i], ddxt2d0_th, &ag[i]);
+    }
+    for (i = 0; i < nthread; i++) {
+        fft2d_thread_wait(th[i]);
+    }
 }
 
-void* xdft2d0_th(void* p)
+void ddxt2d_subth(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w)
 {
-  void cdft(int n, int isgn, float* a, int* ip, float* w);
-  void rdft(int n, int isgn, float* a, int* ip, float* w);
-  int nthread, n0, n1, n2, icr, isgn, *ip, i;
-  float **a, *w;
+    fft2d_thread_t th[FFT2D_MAX_THREADS];
+    fft2d_arg_t ag[FFT2D_MAX_THREADS];
+    int nthread, nt, i;
 
-  nthread = ((fft2d_arg_t*) p)->nthread;
-  n0 = ((fft2d_arg_t*) p)->n0;
-  n1 = ((fft2d_arg_t*) p)->n1;
-  n2 = ((fft2d_arg_t*) p)->n2;
-  icr = ((fft2d_arg_t*) p)->ic;
-  isgn = ((fft2d_arg_t*) p)->isgn;
-  a = ((fft2d_arg_t*) p)->a;
-  ip = ((fft2d_arg_t*) p)->ip;
-  w = ((fft2d_arg_t*) p)->w;
-  if (icr == 0) {
-    for (i = n0; i < n1; i += nthread) {
-      cdft(n2, isgn, a[i], ip, w);
+    nthread = FFT2D_MAX_THREADS;
+    nt = 4 * n1;
+    if (n2 == 2 * FFT2D_MAX_THREADS) {
+        nt >>= 1;
+    } else if (n2 < 2 * FFT2D_MAX_THREADS) {
+        nthread = n2;
+        nt >>= 2;
+    }
+    for (i = 0; i < nthread; i++) {
+        ag[i].nthread = nthread;
+        ag[i].n0 = i;
+        ag[i].n1 = n1;
+        ag[i].n2 = n2;
+        ag[i].ic = ics;
+        ag[i].isgn = isgn;
+        ag[i].a = a;
+        ag[i].t = &t[nt * i];
+        ag[i].ip = ip;
+        ag[i].w = w;
+        fft2d_thread_create(&th[i], ddxt2d_th, &ag[i]);
     }
-  } else {
-    for (i = n0; i < n1; i += nthread) {
-      rdft(n2, isgn, a[i], ip, w);
+    for (i = 0; i < nthread; i++) {
+        fft2d_thread_wait(th[i]);
     }
-  }
-  return (void*) 0;
 }
 
-void* cdft2d_th(void* p)
+void *xdft2d0_th(void *p)
 {
-  void cdft(int n, int isgn, float* a, int* ip, float* w);
-  int nthread, n0, n1, n2, isgn, *ip, i, j;
-  float **a, *t, *w;
+    int nthread, n0, n1, n2, icr, isgn, *ip, i;
+    float **a, *w;
 
-  nthread = ((fft2d_arg_t*) p)->nthread;
-  n0 = ((fft2d_arg_t*) p)->n0;
-  n1 = ((fft2d_arg_t*) p)->n1;
-  n2 = ((fft2d_arg_t*) p)->n2;
-  isgn = ((fft2d_arg_t*) p)->isgn;
-  a = ((fft2d_arg_t*) p)->a;
-  t = ((fft2d_arg_t*) p)->t;
-  ip = ((fft2d_arg_t*) p)->ip;
-  w = ((fft2d_arg_t*) p)->w;
-  if (n2 > 4 * nthread) {
-    for (j = 8 * n0; j < n2; j += 8 * nthread) {
-      for (i = 0; i < n1; i++) {
-        t[2 * i] = a[i][j];
-        t[2 * i + 1] = a[i][j + 1];
-        t[2 * n1 + 2 * i] = a[i][j + 2];
-        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
-        t[4 * n1 + 2 * i] = a[i][j + 4];
-        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
-        t[6 * n1 + 2 * i] = a[i][j + 6];
-        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
-      }
-      cdft(2 * n1, isgn, t, ip, w);
-      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
-      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
-      for (i = 0; i < n1; i++) {
-        a[i][j] = t[2 * i];
-        a[i][j + 1] = t[2 * i + 1];
-        a[i][j + 2] = t[2 * n1 + 2 * i];
-        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
-        a[i][j + 4] = t[4 * n1 + 2 * i];
-        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
-        a[i][j + 6] = t[6 * n1 + 2 * i];
-        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
-      }
-    }
-  } else if (n2 == 4 * nthread) {
-    for (i = 0; i < n1; i++) {
-      t[2 * i] = a[i][4 * n0];
-      t[2 * i + 1] = a[i][4 * n0 + 1];
-      t[2 * n1 + 2 * i] = a[i][4 * n0 + 2];
-      t[2 * n1 + 2 * i + 1] = a[i][4 * n0 + 3];
-    }
-    cdft(2 * n1, isgn, t, ip, w);
-    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-    for (i = 0; i < n1; i++) {
-      a[i][4 * n0] = t[2 * i];
-      a[i][4 * n0 + 1] = t[2 * i + 1];
-      a[i][4 * n0 + 2] = t[2 * n1 + 2 * i];
-      a[i][4 * n0 + 3] = t[2 * n1 + 2 * i + 1];
-    }
-  } else if (n2 == 2 * nthread) {
-    for (i = 0; i < n1; i++) {
-      t[2 * i] = a[i][2 * n0];
-      t[2 * i + 1] = a[i][2 * n0 + 1];
-    }
-    cdft(2 * n1, isgn, t, ip, w);
-    for (i = 0; i < n1; i++) {
-      a[i][2 * n0] = t[2 * i];
-      a[i][2 * n0 + 1] = t[2 * i + 1];
+    nthread = ((fft2d_arg_t *)p)->nthread;
+    n0 = ((fft2d_arg_t *)p)->n0;
+    n1 = ((fft2d_arg_t *)p)->n1;
+    n2 = ((fft2d_arg_t *)p)->n2;
+    icr = ((fft2d_arg_t *)p)->ic;
+    isgn = ((fft2d_arg_t *)p)->isgn;
+    a = ((fft2d_arg_t *)p)->a;
+    ip = ((fft2d_arg_t *)p)->ip;
+    w = ((fft2d_arg_t *)p)->w;
+    if (icr == 0) {
+        for (i = n0; i < n1; i += nthread) {
+            cdft(n2, isgn, a[i], ip, w);
+        }
+    } else {
+        for (i = n0; i < n1; i += nthread) {
+            rdft(n2, isgn, a[i], ip, w);
+        }
     }
-  }
-  return (void*) 0;
+    return (void *)0;
 }
 
-void* ddxt2d0_th(void* p)
+void *cdft2d_th(void *p)
 {
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  int nthread, n0, n1, n2, ics, isgn, *ip, i;
-  float **a, *w;
+    int nthread, n0, n1, n2, isgn, *ip, i, j;
+    float **a, *t, *w;
 
-  nthread = ((fft2d_arg_t*) p)->nthread;
-  n0 = ((fft2d_arg_t*) p)->n0;
-  n1 = ((fft2d_arg_t*) p)->n1;
-  n2 = ((fft2d_arg_t*) p)->n2;
-  ics = ((fft2d_arg_t*) p)->ic;
-  isgn = ((fft2d_arg_t*) p)->isgn;
-  a = ((fft2d_arg_t*) p)->a;
-  ip = ((fft2d_arg_t*) p)->ip;
-  w = ((fft2d_arg_t*) p)->w;
-  if (ics == 0) {
-    for (i = n0; i < n1; i += nthread) {
-      ddct(n2, isgn, a[i], ip, w);
-    }
-  } else {
-    for (i = n0; i < n1; i += nthread) {
-      ddst(n2, isgn, a[i], ip, w);
+    nthread = ((fft2d_arg_t *)p)->nthread;
+    n0 = ((fft2d_arg_t *)p)->n0;
+    n1 = ((fft2d_arg_t *)p)->n1;
+    n2 = ((fft2d_arg_t *)p)->n2;
+    isgn = ((fft2d_arg_t *)p)->isgn;
+    a = ((fft2d_arg_t *)p)->a;
+    t = ((fft2d_arg_t *)p)->t;
+    ip = ((fft2d_arg_t *)p)->ip;
+    w = ((fft2d_arg_t *)p)->w;
+    if (n2 > 4 * nthread) {
+        for (j = 8 * n0; j < n2; j += 8 * nthread) {
+            for (i = 0; i < n1; i++) {
+                t[2 * i] = a[i][j];
+                t[2 * i + 1] = a[i][j + 1];
+                t[2 * n1 + 2 * i] = a[i][j + 2];
+                t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+                t[4 * n1 + 2 * i] = a[i][j + 4];
+                t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+                t[6 * n1 + 2 * i] = a[i][j + 6];
+                t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+            }
+            cdft(2 * n1, isgn, t, ip, w);
+            cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+            cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+            cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+            for (i = 0; i < n1; i++) {
+                a[i][j] = t[2 * i];
+                a[i][j + 1] = t[2 * i + 1];
+                a[i][j + 2] = t[2 * n1 + 2 * i];
+                a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+                a[i][j + 4] = t[4 * n1 + 2 * i];
+                a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+                a[i][j + 6] = t[6 * n1 + 2 * i];
+                a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+            }
+        }
+    } else if (n2 == 4 * nthread) {
+        for (i = 0; i < n1; i++) {
+            t[2 * i] = a[i][4 * n0];
+            t[2 * i + 1] = a[i][4 * n0 + 1];
+            t[2 * n1 + 2 * i] = a[i][4 * n0 + 2];
+            t[2 * n1 + 2 * i + 1] = a[i][4 * n0 + 3];
+        }
+        cdft(2 * n1, isgn, t, ip, w);
+        cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+        for (i = 0; i < n1; i++) {
+            a[i][4 * n0] = t[2 * i];
+            a[i][4 * n0 + 1] = t[2 * i + 1];
+            a[i][4 * n0 + 2] = t[2 * n1 + 2 * i];
+            a[i][4 * n0 + 3] = t[2 * n1 + 2 * i + 1];
+        }
+    } else if (n2 == 2 * nthread) {
+        for (i = 0; i < n1; i++) {
+            t[2 * i] = a[i][2 * n0];
+            t[2 * i + 1] = a[i][2 * n0 + 1];
+        }
+        cdft(2 * n1, isgn, t, ip, w);
+        for (i = 0; i < n1; i++) {
+            a[i][2 * n0] = t[2 * i];
+            a[i][2 * n0 + 1] = t[2 * i + 1];
+        }
     }
-  }
-  return (void*) 0;
+    return (void *)0;
 }
 
-void* ddxt2d_th(void* p)
+void *ddxt2d0_th(void *p)
 {
-  void ddct(int n, int isgn, float* a, int* ip, float* w);
-  void ddst(int n, int isgn, float* a, int* ip, float* w);
-  int nthread, n0, n1, n2, ics, isgn, *ip, i, j;
-  float **a, *t, *w;
+    int nthread, n0, n1, n2, ics, isgn, *ip, i;
+    float **a, *w;
 
-  nthread = ((fft2d_arg_t*) p)->nthread;
-  n0 = ((fft2d_arg_t*) p)->n0;
-  n1 = ((fft2d_arg_t*) p)->n1;
-  n2 = ((fft2d_arg_t*) p)->n2;
-  ics = ((fft2d_arg_t*) p)->ic;
-  isgn = ((fft2d_arg_t*) p)->isgn;
-  a = ((fft2d_arg_t*) p)->a;
-  t = ((fft2d_arg_t*) p)->t;
-  ip = ((fft2d_arg_t*) p)->ip;
-  w = ((fft2d_arg_t*) p)->w;
-  if (n2 > 2 * nthread) {
-    for (j = 4 * n0; j < n2; j += 4 * nthread) {
-      for (i = 0; i < n1; i++) {
-        t[i] = a[i][j];
-        t[n1 + i] = a[i][j + 1];
-        t[2 * n1 + i] = a[i][j + 2];
-        t[3 * n1 + i] = a[i][j + 3];
-      }
-      if (ics == 0) {
-        ddct(n1, isgn, t, ip, w);
-        ddct(n1, isgn, &t[n1], ip, w);
-        ddct(n1, isgn, &t[2 * n1], ip, w);
-        ddct(n1, isgn, &t[3 * n1], ip, w);
-      } else {
-        ddst(n1, isgn, t, ip, w);
-        ddst(n1, isgn, &t[n1], ip, w);
-        ddst(n1, isgn, &t[2 * n1], ip, w);
-        ddst(n1, isgn, &t[3 * n1], ip, w);
-      }
-      for (i = 0; i < n1; i++) {
-        a[i][j] = t[i];
-        a[i][j + 1] = t[n1 + i];
-        a[i][j + 2] = t[2 * n1 + i];
-        a[i][j + 3] = t[3 * n1 + i];
-      }
-    }
-  } else if (n2 == 2 * nthread) {
-    for (i = 0; i < n1; i++) {
-      t[i] = a[i][2 * n0];
-      t[n1 + i] = a[i][2 * n0 + 1];
-    }
-    if (ics == 0) {
-      ddct(n1, isgn, t, ip, w);
-      ddct(n1, isgn, &t[n1], ip, w);
-    } else {
-      ddst(n1, isgn, t, ip, w);
-      ddst(n1, isgn, &t[n1], ip, w);
-    }
-    for (i = 0; i < n1; i++) {
-      a[i][2 * n0] = t[i];
-      a[i][2 * n0 + 1] = t[n1 + i];
-    }
-  } else if (n2 == nthread) {
-    for (i = 0; i < n1; i++) {
-      t[i] = a[i][n0];
-    }
+    nthread = ((fft2d_arg_t *)p)->nthread;
+    n0 = ((fft2d_arg_t *)p)->n0;
+    n1 = ((fft2d_arg_t *)p)->n1;
+    n2 = ((fft2d_arg_t *)p)->n2;
+    ics = ((fft2d_arg_t *)p)->ic;
+    isgn = ((fft2d_arg_t *)p)->isgn;
+    a = ((fft2d_arg_t *)p)->a;
+    ip = ((fft2d_arg_t *)p)->ip;
+    w = ((fft2d_arg_t *)p)->w;
     if (ics == 0) {
-      ddct(n1, isgn, t, ip, w);
+        for (i = n0; i < n1; i += nthread) {
+            ddct(n2, isgn, a[i], ip, w);
+        }
     } else {
-      ddst(n1, isgn, t, ip, w);
+        for (i = n0; i < n1; i += nthread) {
+            ddst(n2, isgn, a[i], ip, w);
+        }
     }
-    for (i = 0; i < n1; i++) {
-      a[i][n0] = t[i];
+    return (void *)0;
+}
+
+void *ddxt2d_th(void *p)
+{
+    int nthread, n0, n1, n2, ics, isgn, *ip, i, j;
+    float **a, *t, *w;
+
+    nthread = ((fft2d_arg_t *)p)->nthread;
+    n0 = ((fft2d_arg_t *)p)->n0;
+    n1 = ((fft2d_arg_t *)p)->n1;
+    n2 = ((fft2d_arg_t *)p)->n2;
+    ics = ((fft2d_arg_t *)p)->ic;
+    isgn = ((fft2d_arg_t *)p)->isgn;
+    a = ((fft2d_arg_t *)p)->a;
+    t = ((fft2d_arg_t *)p)->t;
+    ip = ((fft2d_arg_t *)p)->ip;
+    w = ((fft2d_arg_t *)p)->w;
+    if (n2 > 2 * nthread) {
+        for (j = 4 * n0; j < n2; j += 4 * nthread) {
+            for (i = 0; i < n1; i++) {
+                t[i] = a[i][j];
+                t[n1 + i] = a[i][j + 1];
+                t[2 * n1 + i] = a[i][j + 2];
+                t[3 * n1 + i] = a[i][j + 3];
+            }
+            if (ics == 0) {
+                ddct(n1, isgn, t, ip, w);
+                ddct(n1, isgn, &t[n1], ip, w);
+                ddct(n1, isgn, &t[2 * n1], ip, w);
+                ddct(n1, isgn, &t[3 * n1], ip, w);
+            } else {
+                ddst(n1, isgn, t, ip, w);
+                ddst(n1, isgn, &t[n1], ip, w);
+                ddst(n1, isgn, &t[2 * n1], ip, w);
+                ddst(n1, isgn, &t[3 * n1], ip, w);
+            }
+            for (i = 0; i < n1; i++) {
+                a[i][j] = t[i];
+                a[i][j + 1] = t[n1 + i];
+                a[i][j + 2] = t[2 * n1 + i];
+                a[i][j + 3] = t[3 * n1 + i];
+            }
+        }
+    } else if (n2 == 2 * nthread) {
+        for (i = 0; i < n1; i++) {
+            t[i] = a[i][2 * n0];
+            t[n1 + i] = a[i][2 * n0 + 1];
+        }
+        if (ics == 0) {
+            ddct(n1, isgn, t, ip, w);
+            ddct(n1, isgn, &t[n1], ip, w);
+        } else {
+            ddst(n1, isgn, t, ip, w);
+            ddst(n1, isgn, &t[n1], ip, w);
+        }
+        for (i = 0; i < n1; i++) {
+            a[i][2 * n0] = t[i];
+            a[i][2 * n0 + 1] = t[n1 + i];
+        }
+    } else if (n2 == nthread) {
+        for (i = 0; i < n1; i++) {
+            t[i] = a[i][n0];
+        }
+        if (ics == 0) {
+            ddct(n1, isgn, t, ip, w);
+        } else {
+            ddst(n1, isgn, t, ip, w);
+        }
+        for (i = 0; i < n1; i++) {
+            a[i][n0] = t[i];
+        }
     }
-  }
-  return (void*) 0;
+    return (void *)0;
 }
 #endif /* USE_FFT2D_THREADS */
 

From 6bae89b8b76eb74862a93208af3c27ca92da6ae2 Mon Sep 17 00:00:00 2001
From: Justin Rajewski <justin@alchitry.com>
Date: Thu, 26 Oct 2023 11:05:19 -0600
Subject: [PATCH 503/712] Undid accidental formatting

---
 3rdparty/oourafft/fftsg2d.cc | 1485 +++++++++++++++++-----------------
 1 file changed, 763 insertions(+), 722 deletions(-)

diff --git a/3rdparty/oourafft/fftsg2d.cc b/3rdparty/oourafft/fftsg2d.cc
index 999861968d..462fc90052 100644
--- a/3rdparty/oourafft/fftsg2d.cc
+++ b/3rdparty/oourafft/fftsg2d.cc
@@ -366,15 +366,17 @@ macro definitions
         .
 */
 
+
+
 #include <stdio.h>
 #include <stdlib.h>
-#define fft2d_alloc_error_check(p)                                                                                     \
-    {                                                                                                                  \
-        if ((p) == NULL) {                                                                                             \
-            fprintf(stderr, "fft2d memory allocation error\n");                                                        \
-            exit(1);                                                                                                   \
-        }                                                                                                              \
-    }
+#define fft2d_alloc_error_check(p)                        \
+  {                                                       \
+    if((p) == NULL) {                                     \
+      fprintf(stderr, "fft2d memory allocation error\n"); \
+      exit(1);                                            \
+    }                                                     \
+  }
 
 #ifdef USE_FFT2D_PTHREADS
 #define USE_FFT2D_THREADS
@@ -386,20 +388,20 @@ macro definitions
 #endif
 #include <pthread.h>
 #define fft2d_thread_t pthread_t
-#define fft2d_thread_create(thp, func, argp)                                                                           \
-    {                                                                                                                  \
-        if (pthread_create(thp, NULL, func, (void *)(argp)) != 0) {                                                    \
-            fprintf(stderr, "fft2d thread error\n");                                                                   \
-            exit(1);                                                                                                   \
-        }                                                                                                              \
-    }
-#define fft2d_thread_wait(th)                                                                                          \
-    {                                                                                                                  \
-        if (pthread_join(th, NULL) != 0) {                                                                             \
-            fprintf(stderr, "fft2d thread error\n");                                                                   \
-            exit(1);                                                                                                   \
-        }                                                                                                              \
-    }
+#define fft2d_thread_create(thp, func, argp)                   \
+  {                                                            \
+    if(pthread_create(thp, NULL, func, (void *)(argp)) != 0) { \
+      fprintf(stderr, "fft2d thread error\n");                 \
+      exit(1);                                                 \
+    }                                                          \
+  }
+#define fft2d_thread_wait(th)                  \
+  {                                            \
+    if(pthread_join(th, NULL) != 0) {          \
+      fprintf(stderr, "fft2d thread error\n"); \
+      exit(1);                                 \
+    }                                          \
+  }
 #endif /* USE_FFT2D_PTHREADS */
 
 #ifdef USE_FFT2D_WINTHREADS
@@ -413,20 +415,21 @@ macro definitions
 #define NOMINMAX
 #include <windows.h>
 #define fft2d_thread_t HANDLE
-#define fft2d_thread_create(thp, func, argp)                                                                           \
-    {                                                                                                                  \
-        DWORD thid;                                                                                                    \
-        *(thp) = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)(func), (LPVOID)(argp), 0, &thid);                      \
-        if (*(thp) == 0) {                                                                                             \
-            fprintf(stderr, "fft2d thread error\n");                                                                   \
-            exit(1);                                                                                                   \
-        }                                                                                                              \
-    }
-#define fft2d_thread_wait(th)                                                                                          \
-    {                                                                                                                  \
-        WaitForSingleObject(th, INFINITE);                                                                             \
-        CloseHandle(th);                                                                                               \
-    }
+#define fft2d_thread_create(thp, func, argp)                       \
+  {                                                                \
+    DWORD thid;                                                    \
+    *(thp) = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)(func), \
+                          (LPVOID)(argp), 0, &thid);               \
+    if(*(thp) == 0) {                                              \
+      fprintf(stderr, "fft2d thread error\n");                     \
+      exit(1);                                                     \
+    }                                                              \
+  }
+#define fft2d_thread_wait(th)          \
+  {                                    \
+    WaitForSingleObject(th, INFINITE); \
+    CloseHandle(th);                   \
+  }
 #endif /* USE_FFT2D_WINTHREADS */
 
 #include "nextpnr_namespaces.h"
@@ -453,816 +456,854 @@ void ddxt2d0_subth(int n1, int n2, int ics, int isgn, float **a, int *ip, float
 void ddxt2d_subth(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w);
 #endif /* USE_FFT2D_THREADS */
 
-void cdft2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void cdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, itnull, nthread, nt, i;
+  int n, itnull, nthread, nt, i;
 
-    n = n1 << 1;
-    if (n < n2) {
-        n = n2;
-    }
-    if (n > (ip[0] << 2)) {
-        makewt(n >> 2, ip, w);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1 << 1;
+  if (n < n2) {
+    n = n2;
+  }
+  if (n > (ip[0] << 2)) {
+    makewt(n >> 2, ip, w);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 8 * nthread * n1;
-        if (n2 == 4 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 4 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 8 * nthread * n1;
+    if (n2 == 4 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 4 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        xdft2d0_subth(n1, n2, 0, isgn, a, ip, w);
-        cdft2d_subth(n1, n2, isgn, a, t, ip, w);
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    xdft2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        for (i = 0; i < n1; i++) {
-            cdft(n2, isgn, a[i], ip, w);
-        }
-        cdft2d_sub(n1, n2, isgn, a, t, ip, w);
-    }
-    if (itnull != 0) {
-        free(t);
+  {
+    for (i = 0; i < n1; i++) {
+      cdft(n2, isgn, a[i], ip, w);
     }
+    cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
-void rdft2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void rdft2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, nw, nc, itnull, nthread, nt, i;
+  int n, nw, nc, itnull, nthread, nt, i;
 
-    n = n1 << 1;
-    if (n < n2) {
-        n = n2;
-    }
-    nw = ip[0];
-    if (n > (nw << 2)) {
-        nw = n >> 2;
-        makewt(nw, ip, w);
-    }
-    nc = ip[1];
-    if (n2 > (nc << 2)) {
-        nc = n2 >> 2;
-        makect(nc, ip, w + nw);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1 << 1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n2 > (nc << 2)) {
+    nc = n2 >> 2;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 8 * nthread * n1;
-        if (n2 == 4 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 4 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 8 * nthread * n1;
+    if (n2 == 4 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 4 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        if (isgn < 0) {
-            rdft2d_sub(n1, isgn, a);
-            cdft2d_subth(n1, n2, isgn, a, t, ip, w);
-        }
-        xdft2d0_subth(n1, n2, 1, isgn, a, ip, w);
-        if (isgn >= 0) {
-            cdft2d_subth(n1, n2, isgn, a, t, ip, w);
-            rdft2d_sub(n1, isgn, a);
-        }
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    if (isgn < 0) {
+      rdft2d_sub(n1, isgn, a);
+      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+    }
+    xdft2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    if (isgn >= 0) {
+      cdft2d_subth(n1, n2, isgn, a, t, ip, w);
+      rdft2d_sub(n1, isgn, a);
+    }
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        if (isgn < 0) {
-            rdft2d_sub(n1, isgn, a);
-            cdft2d_sub(n1, n2, isgn, a, t, ip, w);
-        }
-        for (i = 0; i < n1; i++) {
-            rdft(n2, isgn, a[i], ip, w);
-        }
-        if (isgn >= 0) {
-            cdft2d_sub(n1, n2, isgn, a, t, ip, w);
-            rdft2d_sub(n1, isgn, a);
-        }
+  {
+    if (isgn < 0) {
+      rdft2d_sub(n1, isgn, a);
+      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
     }
-    if (itnull != 0) {
-        free(t);
+    for (i = 0; i < n1; i++) {
+      rdft(n2, isgn, a[i], ip, w);
     }
+    if (isgn >= 0) {
+      cdft2d_sub(n1, n2, isgn, a, t, ip, w);
+      rdft2d_sub(n1, isgn, a);
+    }
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
-void rdft2dsort(int n1, int n2, int isgn, float **a)
+void rdft2dsort(int n1, int n2, int isgn, float** a)
 {
-    int n1h, i;
-    float x, y;
+  int n1h, i;
+  float x, y;
 
-    n1h = n1 >> 1;
-    if (isgn < 0) {
-        for (i = n1h + 1; i < n1; i++) {
-            a[i][0] = a[i][n2 + 1];
-            a[i][1] = a[i][n2];
-        }
-        a[0][1] = a[0][n2];
-        a[n1h][1] = a[n1h][n2];
-    } else {
-        for (i = n1h + 1; i < n1; i++) {
-            y = a[i][0];
-            x = a[i][1];
-            a[i][n2] = x;
-            a[i][n2 + 1] = y;
-            a[n1 - i][n2] = x;
-            a[n1 - i][n2 + 1] = -y;
-            a[i][0] = a[n1 - i][0];
-            a[i][1] = -a[n1 - i][1];
-        }
-        a[0][n2] = a[0][1];
-        a[0][n2 + 1] = 0;
-        a[0][1] = 0;
-        a[n1h][n2] = a[n1h][1];
-        a[n1h][n2 + 1] = 0;
-        a[n1h][1] = 0;
+  n1h = n1 >> 1;
+  if (isgn < 0) {
+    for (i = n1h + 1; i < n1; i++) {
+      a[i][0] = a[i][n2 + 1];
+      a[i][1] = a[i][n2];
     }
+    a[0][1] = a[0][n2];
+    a[n1h][1] = a[n1h][n2];
+  } else {
+    for (i = n1h + 1; i < n1; i++) {
+      y = a[i][0];
+      x = a[i][1];
+      a[i][n2] = x;
+      a[i][n2 + 1] = y;
+      a[n1 - i][n2] = x;
+      a[n1 - i][n2 + 1] = -y;
+      a[i][0] = a[n1 - i][0];
+      a[i][1] = -a[n1 - i][1];
+    }
+    a[0][n2] = a[0][1];
+    a[0][n2 + 1] = 0;
+    a[0][1] = 0;
+    a[n1h][n2] = a[n1h][1];
+    a[n1h][n2 + 1] = 0;
+    a[n1h][1] = 0;
+  }
 }
 
-void ddcst2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void ddcst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, nw, nc, itnull, nthread, nt, i;
+  int n, nw, nc, itnull, nthread, nt, i;
 
-    n = n1;
-    if (n < n2) {
-        n = n2;
-    }
-    nw = ip[0];
-    if (n > (nw << 2)) {
-        nw = n >> 2;
-        makewt(nw, ip, w);
-    }
-    nc = ip[1];
-    if (n > nc) {
-        nc = n;
-        makect(nc, ip, w + nw);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 4 * nthread * n1;
-        if (n2 == 2 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 2 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
-        ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        for (i = 0; i < n1; i++) {
-            ddst(n2, isgn, a[i], ip, w);
-        }
-        ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
-    }
-    if (itnull != 0) {
-        free(t);
+  {
+    for (i = 0; i < n1; i++) {
+      ddst(n2, isgn, a[i], ip, w);
     }
+    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
-void ddsct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void ddsct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, nw, nc, itnull, nthread, nt, i;
+  int n, nw, nc, itnull, nthread, nt, i;
 
-    n = n1;
-    if (n < n2) {
-        n = n2;
-    }
-    nw = ip[0];
-    if (n > (nw << 2)) {
-        nw = n >> 2;
-        makewt(nw, ip, w);
-    }
-    nc = ip[1];
-    if (n > nc) {
-        nc = n;
-        makect(nc, ip, w + nw);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 4 * nthread * n1;
-        if (n2 == 2 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 2 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
-        ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        for (i = 0; i < n1; i++) {
-            ddct(n2, isgn, a[i], ip, w);
-        }
-        ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
-    }
-    if (itnull != 0) {
-        free(t);
+  {
+    for (i = 0; i < n1; i++) {
+      ddct(n2, isgn, a[i], ip, w);
     }
+    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
-void ddct2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void ddct2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, nw, nc, itnull, nthread, nt, i;
+  int n, nw, nc, itnull, nthread, nt, i;
 
-    n = n1;
-    if (n < n2) {
-        n = n2;
-    }
-    nw = ip[0];
-    if (n > (nw << 2)) {
-        nw = n >> 2;
-        makewt(nw, ip, w);
-    }
-    nc = ip[1];
-    if (n > nc) {
-        nc = n;
-        makect(nc, ip, w + nw);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 4 * nthread * n1;
-        if (n2 == 2 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 2 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
-        ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 0, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 0, isgn, a, t, ip, w);
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        for (i = 0; i < n1; i++) {
-            ddct(n2, isgn, a[i], ip, w);
-        }
-        ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
-    }
-    if (itnull != 0) {
-        free(t);
+  {
+    for (i = 0; i < n1; i++) {
+      ddct(n2, isgn, a[i], ip, w);
     }
+    ddxt2d_sub(n1, n2, 0, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
-void ddst2d(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void ddst2d(int n1, int n2, int isgn, float** a, float* t, int* ip, float* w)
 {
-    int n, nw, nc, itnull, nthread, nt, i;
+  int n, nw, nc, itnull, nthread, nt, i;
 
-    n = n1;
-    if (n < n2) {
-        n = n2;
-    }
-    nw = ip[0];
-    if (n > (nw << 2)) {
-        nw = n >> 2;
-        makewt(nw, ip, w);
-    }
-    nc = ip[1];
-    if (n > nc) {
-        nc = n;
-        makect(nc, ip, w + nw);
-    }
-    itnull = 0;
-    if (t == NULL) {
-        itnull = 1;
-        nthread = 1;
+  n = n1;
+  if (n < n2) {
+    n = n2;
+  }
+  nw = ip[0];
+  if (n > (nw << 2)) {
+    nw = n >> 2;
+    makewt(nw, ip, w);
+  }
+  nc = ip[1];
+  if (n > nc) {
+    nc = n;
+    makect(nc, ip, w + nw);
+  }
+  itnull = 0;
+  if (t == NULL) {
+    itnull = 1;
+    nthread = 1;
 #ifdef USE_FFT2D_THREADS
-        nthread = FFT2D_MAX_THREADS;
+    nthread = FFT2D_MAX_THREADS;
 #endif /* USE_FFT2D_THREADS */
-        nt = 4 * nthread * n1;
-        if (n2 == 2 * nthread) {
-            nt >>= 1;
-        } else if (n2 < 2 * nthread) {
-            nt >>= 2;
-        }
-        t = (float *)malloc(sizeof(float) * nt);
-        fft2d_alloc_error_check(t);
+    nt = 4 * nthread * n1;
+    if (n2 == 2 * nthread) {
+      nt >>= 1;
+    } else if (n2 < 2 * nthread) {
+      nt >>= 2;
     }
+    t = (float*) malloc(sizeof(float) * nt);
+    fft2d_alloc_error_check(t);
+  }
 #ifdef USE_FFT2D_THREADS
-    if ((float)n1 * n2 >= (float)FFT2D_THREADS_BEGIN_N) {
-        ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
-        ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
-    } else
+  if ((float) n1 * n2 >= (float) FFT2D_THREADS_BEGIN_N) {
+    ddxt2d0_subth(n1, n2, 1, isgn, a, ip, w);
+    ddxt2d_subth(n1, n2, 1, isgn, a, t, ip, w);
+  } else
 #endif /* USE_FFT2D_THREADS */
-    {
-        for (i = 0; i < n1; i++) {
-            ddst(n2, isgn, a[i], ip, w);
-        }
-        ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
-    }
-    if (itnull != 0) {
-        free(t);
+  {
+    for (i = 0; i < n1; i++) {
+      ddst(n2, isgn, a[i], ip, w);
     }
+    ddxt2d_sub(n1, n2, 1, isgn, a, t, ip, w);
+  }
+  if (itnull != 0) {
+    free(t);
+  }
 }
 
 /* -------- child routines -------- */
 
-void cdft2d_sub(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void cdft2d_sub(int n1,
+                int n2,
+                int isgn,
+                float** a,
+                float* t,
+                int* ip,
+                float* w)
 {
-    int i, j;
+  int i, j;
 
-    if (n2 > 4) {
-        for (j = 0; j < n2; j += 8) {
-            for (i = 0; i < n1; i++) {
-                t[2 * i] = a[i][j];
-                t[2 * i + 1] = a[i][j + 1];
-                t[2 * n1 + 2 * i] = a[i][j + 2];
-                t[2 * n1 + 2 * i + 1] = a[i][j + 3];
-                t[4 * n1 + 2 * i] = a[i][j + 4];
-                t[4 * n1 + 2 * i + 1] = a[i][j + 5];
-                t[6 * n1 + 2 * i] = a[i][j + 6];
-                t[6 * n1 + 2 * i + 1] = a[i][j + 7];
-            }
-            cdft(2 * n1, isgn, t, ip, w);
-            cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-            cdft(2 * n1, isgn, &t[4 * n1], ip, w);
-            cdft(2 * n1, isgn, &t[6 * n1], ip, w);
-            for (i = 0; i < n1; i++) {
-                a[i][j] = t[2 * i];
-                a[i][j + 1] = t[2 * i + 1];
-                a[i][j + 2] = t[2 * n1 + 2 * i];
-                a[i][j + 3] = t[2 * n1 + 2 * i + 1];
-                a[i][j + 4] = t[4 * n1 + 2 * i];
-                a[i][j + 5] = t[4 * n1 + 2 * i + 1];
-                a[i][j + 6] = t[6 * n1 + 2 * i];
-                a[i][j + 7] = t[6 * n1 + 2 * i + 1];
-            }
-        }
-    } else if (n2 == 4) {
-        for (i = 0; i < n1; i++) {
-            t[2 * i] = a[i][0];
-            t[2 * i + 1] = a[i][1];
-            t[2 * n1 + 2 * i] = a[i][2];
-            t[2 * n1 + 2 * i + 1] = a[i][3];
-        }
-        cdft(2 * n1, isgn, t, ip, w);
-        cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-        for (i = 0; i < n1; i++) {
-            a[i][0] = t[2 * i];
-            a[i][1] = t[2 * i + 1];
-            a[i][2] = t[2 * n1 + 2 * i];
-            a[i][3] = t[2 * n1 + 2 * i + 1];
-        }
-    } else if (n2 == 2) {
-        for (i = 0; i < n1; i++) {
-            t[2 * i] = a[i][0];
-            t[2 * i + 1] = a[i][1];
-        }
-        cdft(2 * n1, isgn, t, ip, w);
-        for (i = 0; i < n1; i++) {
-            a[i][0] = t[2 * i];
-            a[i][1] = t[2 * i + 1];
-        }
+  if (n2 > 4) {
+    for (j = 0; j < n2; j += 8) {
+      for (i = 0; i < n1; i++) {
+        t[2 * i] = a[i][j];
+        t[2 * i + 1] = a[i][j + 1];
+        t[2 * n1 + 2 * i] = a[i][j + 2];
+        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+        t[4 * n1 + 2 * i] = a[i][j + 4];
+        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+        t[6 * n1 + 2 * i] = a[i][j + 6];
+        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+      }
+      cdft(2 * n1, isgn, t, ip, w);
+      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[2 * i];
+        a[i][j + 1] = t[2 * i + 1];
+        a[i][j + 2] = t[2 * n1 + 2 * i];
+        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+        a[i][j + 4] = t[4 * n1 + 2 * i];
+        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+        a[i][j + 6] = t[6 * n1 + 2 * i];
+        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+      }
+    }
+  } else if (n2 == 4) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][0];
+      t[2 * i + 1] = a[i][1];
+      t[2 * n1 + 2 * i] = a[i][2];
+      t[2 * n1 + 2 * i + 1] = a[i][3];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[2 * i];
+      a[i][1] = t[2 * i + 1];
+      a[i][2] = t[2 * n1 + 2 * i];
+      a[i][3] = t[2 * n1 + 2 * i + 1];
     }
+  } else if (n2 == 2) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][0];
+      t[2 * i + 1] = a[i][1];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[2 * i];
+      a[i][1] = t[2 * i + 1];
+    }
+  }
 }
 
-void rdft2d_sub(int n1, int isgn, float **a)
+void rdft2d_sub(int n1, int isgn, float** a)
 {
-    int n1h, i, j;
-    float xi;
+  int n1h, i, j;
+  float xi;
 
-    n1h = n1 >> 1;
-    if (isgn < 0) {
-        for (i = 1; i < n1h; i++) {
-            j = n1 - i;
-            xi = a[i][0] - a[j][0];
-            a[i][0] += a[j][0];
-            a[j][0] = xi;
-            xi = a[j][1] - a[i][1];
-            a[i][1] += a[j][1];
-            a[j][1] = xi;
-        }
-    } else {
-        for (i = 1; i < n1h; i++) {
-            j = n1 - i;
-            a[j][0] = 0.5 * (a[i][0] - a[j][0]);
-            a[i][0] -= a[j][0];
-            a[j][1] = 0.5 * (a[i][1] + a[j][1]);
-            a[i][1] -= a[j][1];
-        }
+  n1h = n1 >> 1;
+  if (isgn < 0) {
+    for (i = 1; i < n1h; i++) {
+      j = n1 - i;
+      xi = a[i][0] - a[j][0];
+      a[i][0] += a[j][0];
+      a[j][0] = xi;
+      xi = a[j][1] - a[i][1];
+      a[i][1] += a[j][1];
+      a[j][1] = xi;
+    }
+  } else {
+    for (i = 1; i < n1h; i++) {
+      j = n1 - i;
+      a[j][0] = 0.5 * (a[i][0] - a[j][0]);
+      a[i][0] -= a[j][0];
+      a[j][1] = 0.5 * (a[i][1] + a[j][1]);
+      a[i][1] -= a[j][1];
     }
+  }
 }
 
-void ddxt2d_sub(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w)
+void ddxt2d_sub(int n1,
+                int n2,
+                int ics,
+                int isgn,
+                float** a,
+                float* t,
+                int* ip,
+                float* w)
 {
-    int i, j;
+  int i, j;
 
-    if (n2 > 2) {
-        for (j = 0; j < n2; j += 4) {
-            for (i = 0; i < n1; i++) {
-                t[i] = a[i][j];
-                t[n1 + i] = a[i][j + 1];
-                t[2 * n1 + i] = a[i][j + 2];
-                t[3 * n1 + i] = a[i][j + 3];
-            }
-            if (ics == 0) {
-                ddct(n1, isgn, t, ip, w);
-                ddct(n1, isgn, &t[n1], ip, w);
-                ddct(n1, isgn, &t[2 * n1], ip, w);
-                ddct(n1, isgn, &t[3 * n1], ip, w);
-            } else {
-                ddst(n1, isgn, t, ip, w);
-                ddst(n1, isgn, &t[n1], ip, w);
-                ddst(n1, isgn, &t[2 * n1], ip, w);
-                ddst(n1, isgn, &t[3 * n1], ip, w);
-            }
-            for (i = 0; i < n1; i++) {
-                a[i][j] = t[i];
-                a[i][j + 1] = t[n1 + i];
-                a[i][j + 2] = t[2 * n1 + i];
-                a[i][j + 3] = t[3 * n1 + i];
-            }
-        }
-    } else if (n2 == 2) {
-        for (i = 0; i < n1; i++) {
-            t[i] = a[i][0];
-            t[n1 + i] = a[i][1];
-        }
-        if (ics == 0) {
-            ddct(n1, isgn, t, ip, w);
-            ddct(n1, isgn, &t[n1], ip, w);
-        } else {
-            ddst(n1, isgn, t, ip, w);
-            ddst(n1, isgn, &t[n1], ip, w);
-        }
-        for (i = 0; i < n1; i++) {
-            a[i][0] = t[i];
-            a[i][1] = t[n1 + i];
-        }
+  if (n2 > 2) {
+    for (j = 0; j < n2; j += 4) {
+      for (i = 0; i < n1; i++) {
+        t[i] = a[i][j];
+        t[n1 + i] = a[i][j + 1];
+        t[2 * n1 + i] = a[i][j + 2];
+        t[3 * n1 + i] = a[i][j + 3];
+      }
+      if (ics == 0) {
+        ddct(n1, isgn, t, ip, w);
+        ddct(n1, isgn, &t[n1], ip, w);
+        ddct(n1, isgn, &t[2 * n1], ip, w);
+        ddct(n1, isgn, &t[3 * n1], ip, w);
+      } else {
+        ddst(n1, isgn, t, ip, w);
+        ddst(n1, isgn, &t[n1], ip, w);
+        ddst(n1, isgn, &t[2 * n1], ip, w);
+        ddst(n1, isgn, &t[3 * n1], ip, w);
+      }
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[i];
+        a[i][j + 1] = t[n1 + i];
+        a[i][j + 2] = t[2 * n1 + i];
+        a[i][j + 3] = t[3 * n1 + i];
+      }
+    }
+  } else if (n2 == 2) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][0];
+      t[n1 + i] = a[i][1];
     }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+      ddct(n1, isgn, &t[n1], ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+      ddst(n1, isgn, &t[n1], ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][0] = t[i];
+      a[i][1] = t[n1 + i];
+    }
+  }
 }
 
 #ifdef USE_FFT2D_THREADS
 struct fft2d_arg_st
 {
-    int nthread;
-    int n0;
-    int n1;
-    int n2;
-    int ic;
-    int isgn;
-    float **a;
-    float *t;
-    int *ip;
-    float *w;
+  int nthread;
+  int n0;
+  int n1;
+  int n2;
+  int ic;
+  int isgn;
+  float** a;
+  float* t;
+  int* ip;
+  float* w;
 };
 typedef struct fft2d_arg_st fft2d_arg_t;
 
-void xdft2d0_subth(int n1, int n2, int icr, int isgn, float **a, int *ip, float *w)
+void xdft2d0_subth(int n1,
+                   int n2,
+                   int icr,
+                   int isgn,
+                   float** a,
+                   int* ip,
+                   float* w)
 {
-    void *xdft2d0_th(void *p);
-    fft2d_thread_t th[FFT2D_MAX_THREADS];
-    fft2d_arg_t ag[FFT2D_MAX_THREADS];
-    int nthread, i;
+  void* xdft2d0_th(void* p);
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, i;
 
-    nthread = FFT2D_MAX_THREADS;
-    if (nthread > n1) {
-        nthread = n1;
-    }
-    for (i = 0; i < nthread; i++) {
-        ag[i].nthread = nthread;
-        ag[i].n0 = i;
-        ag[i].n1 = n1;
-        ag[i].n2 = n2;
-        ag[i].ic = icr;
-        ag[i].isgn = isgn;
-        ag[i].a = a;
-        ag[i].ip = ip;
-        ag[i].w = w;
-        fft2d_thread_create(&th[i], xdft2d0_th, &ag[i]);
-    }
-    for (i = 0; i < nthread; i++) {
-        fft2d_thread_wait(th[i]);
-    }
+  nthread = FFT2D_MAX_THREADS;
+  if (nthread > n1) {
+    nthread = n1;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = icr;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], xdft2d0_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
 }
 
-void cdft2d_subth(int n1, int n2, int isgn, float **a, float *t, int *ip, float *w)
+void cdft2d_subth(int n1,
+                  int n2,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w)
 {
-    fft2d_thread_t th[FFT2D_MAX_THREADS];
-    fft2d_arg_t ag[FFT2D_MAX_THREADS];
-    int nthread, nt, i;
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, nt, i;
 
-    nthread = FFT2D_MAX_THREADS;
-    nt = 8 * n1;
-    if (n2 == 4 * FFT2D_MAX_THREADS) {
-        nt >>= 1;
-    } else if (n2 < 4 * FFT2D_MAX_THREADS) {
-        nthread = n2 >> 1;
-        nt >>= 2;
-    }
-    for (i = 0; i < nthread; i++) {
-        ag[i].nthread = nthread;
-        ag[i].n0 = i;
-        ag[i].n1 = n1;
-        ag[i].n2 = n2;
-        ag[i].isgn = isgn;
-        ag[i].a = a;
-        ag[i].t = &t[nt * i];
-        ag[i].ip = ip;
-        ag[i].w = w;
-        fft2d_thread_create(&th[i], cdft2d_th, &ag[i]);
-    }
-    for (i = 0; i < nthread; i++) {
-        fft2d_thread_wait(th[i]);
-    }
+  nthread = FFT2D_MAX_THREADS;
+  nt = 8 * n1;
+  if (n2 == 4 * FFT2D_MAX_THREADS) {
+    nt >>= 1;
+  } else if (n2 < 4 * FFT2D_MAX_THREADS) {
+    nthread = n2 >> 1;
+    nt >>= 2;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].t = &t[nt * i];
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], cdft2d_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
 }
 
-void ddxt2d0_subth(int n1, int n2, int ics, int isgn, float **a, int *ip, float *w)
+void ddxt2d0_subth(int n1,
+                   int n2,
+                   int ics,
+                   int isgn,
+                   float** a,
+                   int* ip,
+                   float* w)
 {
-    fft2d_thread_t th[FFT2D_MAX_THREADS];
-    fft2d_arg_t ag[FFT2D_MAX_THREADS];
-    int nthread, i;
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, i;
 
-    nthread = FFT2D_MAX_THREADS;
-    if (nthread > n1) {
-        nthread = n1;
-    }
-    for (i = 0; i < nthread; i++) {
-        ag[i].nthread = nthread;
-        ag[i].n0 = i;
-        ag[i].n1 = n1;
-        ag[i].n2 = n2;
-        ag[i].ic = ics;
-        ag[i].isgn = isgn;
-        ag[i].a = a;
-        ag[i].ip = ip;
-        ag[i].w = w;
-        fft2d_thread_create(&th[i], ddxt2d0_th, &ag[i]);
-    }
-    for (i = 0; i < nthread; i++) {
-        fft2d_thread_wait(th[i]);
-    }
+  nthread = FFT2D_MAX_THREADS;
+  if (nthread > n1) {
+    nthread = n1;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = ics;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], ddxt2d0_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
 }
 
-void ddxt2d_subth(int n1, int n2, int ics, int isgn, float **a, float *t, int *ip, float *w)
+void ddxt2d_subth(int n1,
+                  int n2,
+                  int ics,
+                  int isgn,
+                  float** a,
+                  float* t,
+                  int* ip,
+                  float* w)
 {
-    fft2d_thread_t th[FFT2D_MAX_THREADS];
-    fft2d_arg_t ag[FFT2D_MAX_THREADS];
-    int nthread, nt, i;
+  fft2d_thread_t th[FFT2D_MAX_THREADS];
+  fft2d_arg_t ag[FFT2D_MAX_THREADS];
+  int nthread, nt, i;
 
-    nthread = FFT2D_MAX_THREADS;
-    nt = 4 * n1;
-    if (n2 == 2 * FFT2D_MAX_THREADS) {
-        nt >>= 1;
-    } else if (n2 < 2 * FFT2D_MAX_THREADS) {
-        nthread = n2;
-        nt >>= 2;
-    }
-    for (i = 0; i < nthread; i++) {
-        ag[i].nthread = nthread;
-        ag[i].n0 = i;
-        ag[i].n1 = n1;
-        ag[i].n2 = n2;
-        ag[i].ic = ics;
-        ag[i].isgn = isgn;
-        ag[i].a = a;
-        ag[i].t = &t[nt * i];
-        ag[i].ip = ip;
-        ag[i].w = w;
-        fft2d_thread_create(&th[i], ddxt2d_th, &ag[i]);
-    }
-    for (i = 0; i < nthread; i++) {
-        fft2d_thread_wait(th[i]);
-    }
+  nthread = FFT2D_MAX_THREADS;
+  nt = 4 * n1;
+  if (n2 == 2 * FFT2D_MAX_THREADS) {
+    nt >>= 1;
+  } else if (n2 < 2 * FFT2D_MAX_THREADS) {
+    nthread = n2;
+    nt >>= 2;
+  }
+  for (i = 0; i < nthread; i++) {
+    ag[i].nthread = nthread;
+    ag[i].n0 = i;
+    ag[i].n1 = n1;
+    ag[i].n2 = n2;
+    ag[i].ic = ics;
+    ag[i].isgn = isgn;
+    ag[i].a = a;
+    ag[i].t = &t[nt * i];
+    ag[i].ip = ip;
+    ag[i].w = w;
+    fft2d_thread_create(&th[i], ddxt2d_th, &ag[i]);
+  }
+  for (i = 0; i < nthread; i++) {
+    fft2d_thread_wait(th[i]);
+  }
 }
 
-void *xdft2d0_th(void *p)
+void* xdft2d0_th(void* p)
 {
-    int nthread, n0, n1, n2, icr, isgn, *ip, i;
-    float **a, *w;
+  int nthread, n0, n1, n2, icr, isgn, *ip, i;
+  float **a, *w;
 
-    nthread = ((fft2d_arg_t *)p)->nthread;
-    n0 = ((fft2d_arg_t *)p)->n0;
-    n1 = ((fft2d_arg_t *)p)->n1;
-    n2 = ((fft2d_arg_t *)p)->n2;
-    icr = ((fft2d_arg_t *)p)->ic;
-    isgn = ((fft2d_arg_t *)p)->isgn;
-    a = ((fft2d_arg_t *)p)->a;
-    ip = ((fft2d_arg_t *)p)->ip;
-    w = ((fft2d_arg_t *)p)->w;
-    if (icr == 0) {
-        for (i = n0; i < n1; i += nthread) {
-            cdft(n2, isgn, a[i], ip, w);
-        }
-    } else {
-        for (i = n0; i < n1; i += nthread) {
-            rdft(n2, isgn, a[i], ip, w);
-        }
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  icr = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (icr == 0) {
+    for (i = n0; i < n1; i += nthread) {
+      cdft(n2, isgn, a[i], ip, w);
     }
-    return (void *)0;
+  } else {
+    for (i = n0; i < n1; i += nthread) {
+      rdft(n2, isgn, a[i], ip, w);
+    }
+  }
+  return (void*) 0;
 }
 
-void *cdft2d_th(void *p)
+void* cdft2d_th(void* p)
 {
-    int nthread, n0, n1, n2, isgn, *ip, i, j;
-    float **a, *t, *w;
+  int nthread, n0, n1, n2, isgn, *ip, i, j;
+  float **a, *t, *w;
 
-    nthread = ((fft2d_arg_t *)p)->nthread;
-    n0 = ((fft2d_arg_t *)p)->n0;
-    n1 = ((fft2d_arg_t *)p)->n1;
-    n2 = ((fft2d_arg_t *)p)->n2;
-    isgn = ((fft2d_arg_t *)p)->isgn;
-    a = ((fft2d_arg_t *)p)->a;
-    t = ((fft2d_arg_t *)p)->t;
-    ip = ((fft2d_arg_t *)p)->ip;
-    w = ((fft2d_arg_t *)p)->w;
-    if (n2 > 4 * nthread) {
-        for (j = 8 * n0; j < n2; j += 8 * nthread) {
-            for (i = 0; i < n1; i++) {
-                t[2 * i] = a[i][j];
-                t[2 * i + 1] = a[i][j + 1];
-                t[2 * n1 + 2 * i] = a[i][j + 2];
-                t[2 * n1 + 2 * i + 1] = a[i][j + 3];
-                t[4 * n1 + 2 * i] = a[i][j + 4];
-                t[4 * n1 + 2 * i + 1] = a[i][j + 5];
-                t[6 * n1 + 2 * i] = a[i][j + 6];
-                t[6 * n1 + 2 * i + 1] = a[i][j + 7];
-            }
-            cdft(2 * n1, isgn, t, ip, w);
-            cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-            cdft(2 * n1, isgn, &t[4 * n1], ip, w);
-            cdft(2 * n1, isgn, &t[6 * n1], ip, w);
-            for (i = 0; i < n1; i++) {
-                a[i][j] = t[2 * i];
-                a[i][j + 1] = t[2 * i + 1];
-                a[i][j + 2] = t[2 * n1 + 2 * i];
-                a[i][j + 3] = t[2 * n1 + 2 * i + 1];
-                a[i][j + 4] = t[4 * n1 + 2 * i];
-                a[i][j + 5] = t[4 * n1 + 2 * i + 1];
-                a[i][j + 6] = t[6 * n1 + 2 * i];
-                a[i][j + 7] = t[6 * n1 + 2 * i + 1];
-            }
-        }
-    } else if (n2 == 4 * nthread) {
-        for (i = 0; i < n1; i++) {
-            t[2 * i] = a[i][4 * n0];
-            t[2 * i + 1] = a[i][4 * n0 + 1];
-            t[2 * n1 + 2 * i] = a[i][4 * n0 + 2];
-            t[2 * n1 + 2 * i + 1] = a[i][4 * n0 + 3];
-        }
-        cdft(2 * n1, isgn, t, ip, w);
-        cdft(2 * n1, isgn, &t[2 * n1], ip, w);
-        for (i = 0; i < n1; i++) {
-            a[i][4 * n0] = t[2 * i];
-            a[i][4 * n0 + 1] = t[2 * i + 1];
-            a[i][4 * n0 + 2] = t[2 * n1 + 2 * i];
-            a[i][4 * n0 + 3] = t[2 * n1 + 2 * i + 1];
-        }
-    } else if (n2 == 2 * nthread) {
-        for (i = 0; i < n1; i++) {
-            t[2 * i] = a[i][2 * n0];
-            t[2 * i + 1] = a[i][2 * n0 + 1];
-        }
-        cdft(2 * n1, isgn, t, ip, w);
-        for (i = 0; i < n1; i++) {
-            a[i][2 * n0] = t[2 * i];
-            a[i][2 * n0 + 1] = t[2 * i + 1];
-        }
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  t = ((fft2d_arg_t*) p)->t;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (n2 > 4 * nthread) {
+    for (j = 8 * n0; j < n2; j += 8 * nthread) {
+      for (i = 0; i < n1; i++) {
+        t[2 * i] = a[i][j];
+        t[2 * i + 1] = a[i][j + 1];
+        t[2 * n1 + 2 * i] = a[i][j + 2];
+        t[2 * n1 + 2 * i + 1] = a[i][j + 3];
+        t[4 * n1 + 2 * i] = a[i][j + 4];
+        t[4 * n1 + 2 * i + 1] = a[i][j + 5];
+        t[6 * n1 + 2 * i] = a[i][j + 6];
+        t[6 * n1 + 2 * i + 1] = a[i][j + 7];
+      }
+      cdft(2 * n1, isgn, t, ip, w);
+      cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[4 * n1], ip, w);
+      cdft(2 * n1, isgn, &t[6 * n1], ip, w);
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[2 * i];
+        a[i][j + 1] = t[2 * i + 1];
+        a[i][j + 2] = t[2 * n1 + 2 * i];
+        a[i][j + 3] = t[2 * n1 + 2 * i + 1];
+        a[i][j + 4] = t[4 * n1 + 2 * i];
+        a[i][j + 5] = t[4 * n1 + 2 * i + 1];
+        a[i][j + 6] = t[6 * n1 + 2 * i];
+        a[i][j + 7] = t[6 * n1 + 2 * i + 1];
+      }
+    }
+  } else if (n2 == 4 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][4 * n0];
+      t[2 * i + 1] = a[i][4 * n0 + 1];
+      t[2 * n1 + 2 * i] = a[i][4 * n0 + 2];
+      t[2 * n1 + 2 * i + 1] = a[i][4 * n0 + 3];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    cdft(2 * n1, isgn, &t[2 * n1], ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][4 * n0] = t[2 * i];
+      a[i][4 * n0 + 1] = t[2 * i + 1];
+      a[i][4 * n0 + 2] = t[2 * n1 + 2 * i];
+      a[i][4 * n0 + 3] = t[2 * n1 + 2 * i + 1];
     }
-    return (void *)0;
+  } else if (n2 == 2 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[2 * i] = a[i][2 * n0];
+      t[2 * i + 1] = a[i][2 * n0 + 1];
+    }
+    cdft(2 * n1, isgn, t, ip, w);
+    for (i = 0; i < n1; i++) {
+      a[i][2 * n0] = t[2 * i];
+      a[i][2 * n0 + 1] = t[2 * i + 1];
+    }
+  }
+  return (void*) 0;
 }
 
-void *ddxt2d0_th(void *p)
+void* ddxt2d0_th(void* p)
 {
-    int nthread, n0, n1, n2, ics, isgn, *ip, i;
-    float **a, *w;
+  int nthread, n0, n1, n2, ics, isgn, *ip, i;
+  float **a, *w;
 
-    nthread = ((fft2d_arg_t *)p)->nthread;
-    n0 = ((fft2d_arg_t *)p)->n0;
-    n1 = ((fft2d_arg_t *)p)->n1;
-    n2 = ((fft2d_arg_t *)p)->n2;
-    ics = ((fft2d_arg_t *)p)->ic;
-    isgn = ((fft2d_arg_t *)p)->isgn;
-    a = ((fft2d_arg_t *)p)->a;
-    ip = ((fft2d_arg_t *)p)->ip;
-    w = ((fft2d_arg_t *)p)->w;
-    if (ics == 0) {
-        for (i = n0; i < n1; i += nthread) {
-            ddct(n2, isgn, a[i], ip, w);
-        }
-    } else {
-        for (i = n0; i < n1; i += nthread) {
-            ddst(n2, isgn, a[i], ip, w);
-        }
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  ics = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (ics == 0) {
+    for (i = n0; i < n1; i += nthread) {
+      ddct(n2, isgn, a[i], ip, w);
+    }
+  } else {
+    for (i = n0; i < n1; i += nthread) {
+      ddst(n2, isgn, a[i], ip, w);
     }
-    return (void *)0;
+  }
+  return (void*) 0;
 }
 
-void *ddxt2d_th(void *p)
+void* ddxt2d_th(void* p)
 {
-    int nthread, n0, n1, n2, ics, isgn, *ip, i, j;
-    float **a, *t, *w;
+  int nthread, n0, n1, n2, ics, isgn, *ip, i, j;
+  float **a, *t, *w;
 
-    nthread = ((fft2d_arg_t *)p)->nthread;
-    n0 = ((fft2d_arg_t *)p)->n0;
-    n1 = ((fft2d_arg_t *)p)->n1;
-    n2 = ((fft2d_arg_t *)p)->n2;
-    ics = ((fft2d_arg_t *)p)->ic;
-    isgn = ((fft2d_arg_t *)p)->isgn;
-    a = ((fft2d_arg_t *)p)->a;
-    t = ((fft2d_arg_t *)p)->t;
-    ip = ((fft2d_arg_t *)p)->ip;
-    w = ((fft2d_arg_t *)p)->w;
-    if (n2 > 2 * nthread) {
-        for (j = 4 * n0; j < n2; j += 4 * nthread) {
-            for (i = 0; i < n1; i++) {
-                t[i] = a[i][j];
-                t[n1 + i] = a[i][j + 1];
-                t[2 * n1 + i] = a[i][j + 2];
-                t[3 * n1 + i] = a[i][j + 3];
-            }
-            if (ics == 0) {
-                ddct(n1, isgn, t, ip, w);
-                ddct(n1, isgn, &t[n1], ip, w);
-                ddct(n1, isgn, &t[2 * n1], ip, w);
-                ddct(n1, isgn, &t[3 * n1], ip, w);
-            } else {
-                ddst(n1, isgn, t, ip, w);
-                ddst(n1, isgn, &t[n1], ip, w);
-                ddst(n1, isgn, &t[2 * n1], ip, w);
-                ddst(n1, isgn, &t[3 * n1], ip, w);
-            }
-            for (i = 0; i < n1; i++) {
-                a[i][j] = t[i];
-                a[i][j + 1] = t[n1 + i];
-                a[i][j + 2] = t[2 * n1 + i];
-                a[i][j + 3] = t[3 * n1 + i];
-            }
-        }
-    } else if (n2 == 2 * nthread) {
-        for (i = 0; i < n1; i++) {
-            t[i] = a[i][2 * n0];
-            t[n1 + i] = a[i][2 * n0 + 1];
-        }
-        if (ics == 0) {
-            ddct(n1, isgn, t, ip, w);
-            ddct(n1, isgn, &t[n1], ip, w);
-        } else {
-            ddst(n1, isgn, t, ip, w);
-            ddst(n1, isgn, &t[n1], ip, w);
-        }
-        for (i = 0; i < n1; i++) {
-            a[i][2 * n0] = t[i];
-            a[i][2 * n0 + 1] = t[n1 + i];
-        }
-    } else if (n2 == nthread) {
-        for (i = 0; i < n1; i++) {
-            t[i] = a[i][n0];
-        }
-        if (ics == 0) {
-            ddct(n1, isgn, t, ip, w);
-        } else {
-            ddst(n1, isgn, t, ip, w);
-        }
-        for (i = 0; i < n1; i++) {
-            a[i][n0] = t[i];
-        }
+  nthread = ((fft2d_arg_t*) p)->nthread;
+  n0 = ((fft2d_arg_t*) p)->n0;
+  n1 = ((fft2d_arg_t*) p)->n1;
+  n2 = ((fft2d_arg_t*) p)->n2;
+  ics = ((fft2d_arg_t*) p)->ic;
+  isgn = ((fft2d_arg_t*) p)->isgn;
+  a = ((fft2d_arg_t*) p)->a;
+  t = ((fft2d_arg_t*) p)->t;
+  ip = ((fft2d_arg_t*) p)->ip;
+  w = ((fft2d_arg_t*) p)->w;
+  if (n2 > 2 * nthread) {
+    for (j = 4 * n0; j < n2; j += 4 * nthread) {
+      for (i = 0; i < n1; i++) {
+        t[i] = a[i][j];
+        t[n1 + i] = a[i][j + 1];
+        t[2 * n1 + i] = a[i][j + 2];
+        t[3 * n1 + i] = a[i][j + 3];
+      }
+      if (ics == 0) {
+        ddct(n1, isgn, t, ip, w);
+        ddct(n1, isgn, &t[n1], ip, w);
+        ddct(n1, isgn, &t[2 * n1], ip, w);
+        ddct(n1, isgn, &t[3 * n1], ip, w);
+      } else {
+        ddst(n1, isgn, t, ip, w);
+        ddst(n1, isgn, &t[n1], ip, w);
+        ddst(n1, isgn, &t[2 * n1], ip, w);
+        ddst(n1, isgn, &t[3 * n1], ip, w);
+      }
+      for (i = 0; i < n1; i++) {
+        a[i][j] = t[i];
+        a[i][j + 1] = t[n1 + i];
+        a[i][j + 2] = t[2 * n1 + i];
+        a[i][j + 3] = t[3 * n1 + i];
+      }
+    }
+  } else if (n2 == 2 * nthread) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][2 * n0];
+      t[n1 + i] = a[i][2 * n0 + 1];
+    }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+      ddct(n1, isgn, &t[n1], ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+      ddst(n1, isgn, &t[n1], ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][2 * n0] = t[i];
+      a[i][2 * n0 + 1] = t[n1 + i];
+    }
+  } else if (n2 == nthread) {
+    for (i = 0; i < n1; i++) {
+      t[i] = a[i][n0];
+    }
+    if (ics == 0) {
+      ddct(n1, isgn, t, ip, w);
+    } else {
+      ddst(n1, isgn, t, ip, w);
+    }
+    for (i = 0; i < n1; i++) {
+      a[i][n0] = t[i];
     }
-    return (void *)0;
+  }
+  return (void*) 0;
 }
 #endif /* USE_FFT2D_THREADS */
 

From 74d7ebc71f50e1722ade8f2129b5768b01d2fa31 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 28 Oct 2023 17:10:42 +0200
Subject: [PATCH 504/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 33 +++++++++++++++++----------------
 machxo2/arch.cc               | 28 +++++++++++-----------------
 machxo2/arch.h                |  4 ++--
 3 files changed, 30 insertions(+), 35 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 3e105e4708..729785bb34 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -551,7 +551,7 @@ class StaticPlacer
             g.overlap /= std::max(1.0f, total_area);
             if (!overlap_str.empty())
                 overlap_str += ", ";
-            overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap*100);
+            overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap * 100);
             g.conc_density.write_csv(stringf("out_conc_density_%d_%d.csv", iter, idx));
         }
         log_info("overlap: %s\n", overlap_str.c_str());
@@ -896,7 +896,7 @@ class StaticPlacer
             for (int c : macro.conc_cells) {
                 auto &cc = ccells.at(c);
                 auto &mc = mcells.at(c);
-                mc.pos = mc.pos * (1-alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
+                mc.pos = mc.pos * (1 - alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
                 mc.ref_pos = mc.ref_pos * (1 - alpha) + (ref_pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
             }
         }
@@ -927,7 +927,8 @@ class StaticPlacer
         compute_overlap();
     }
 
-    void legalise_step(bool dsp_bram) {
+    void legalise_step(bool dsp_bram)
+    {
         // assume DSP and BRAM are all groups 2+ for now
         for (int i = 0; i < int(ccells.size()); i++) {
             auto &mc = mcells.at(i);
@@ -937,7 +938,7 @@ class StaticPlacer
             if (!dsp_bram && mc.group >= 2)
                 continue;
             if (cc.macro_idx != -1 && i != macros.at(cc.macro_idx).root->udata)
-                continue; // not macro root
+                continue;      // not macro root
             if (mc.is_fixed) { // already placed
                 NPNR_ASSERT(cc.base_cell->bel != BelId());
                 continue;
@@ -959,7 +960,8 @@ class StaticPlacer
         log_info("HPWL after legalise: %f (delta: %f)\n", post_hpwl, post_hpwl - pre_hpwl);
     }
 
-    void enqueue_legalise(int cell_idx) {
+    void enqueue_legalise(int cell_idx)
+    {
         NPNR_ASSERT(cell_idx < int(ccells.size())); // we should never be legalising spacers or dark nodes
         auto &ccell = ccells.at(cell_idx);
         if (ccell.macro_idx != -1) {
@@ -971,7 +973,8 @@ class StaticPlacer
         }
     }
 
-    void enqueue_legalise(CellInfo *ci) {
+    void enqueue_legalise(CellInfo *ci)
+    {
         if (ci->udata != -1) {
             // managed by static
             enqueue_legalise(ci->udata);
@@ -1011,7 +1014,7 @@ class StaticPlacer
             total_iters_noreset++;
             if (total_iters > int(ccells.size())) {
                 total_iters = 0;
-                ripup_radius = std::max(std::max(width+1, height+1), ripup_radius * 2);
+                ripup_radius = std::max(std::max(width + 1, height + 1), ripup_radius * 2);
             }
 
             if (total_iters_noreset > std::max(5000, 8 * int(ctx->cells.size()))) {
@@ -1039,23 +1042,21 @@ class StaticPlacer
                 iter_at_radius++;
                 if (iter >= (10 * (radius + 1))) {
                     // No luck yet, increase radius
-                    radius = std::min(std::max(width+1, height+1), radius + 1);
-                    while (radius < std::max(width+1, height+1)) {
+                    radius = std::min(std::max(width + 1, height + 1), radius + 1);
+                    while (radius < std::max(width + 1, height + 1)) {
                         // Keep increasing the radius until it will actually increase the number of cells we are
                         // checking (e.g. BRAM and DSP will not be in all cols/rows), so we don't waste effort
-                        for (int x = std::max(0, cx - radius);
-                             x <= std::min(width+1, cx + radius); x++) {
+                        for (int x = std::max(0, cx - radius); x <= std::min(width + 1, cx + radius); x++) {
                             if (x >= int(fb->size()))
                                 break;
-                            for (int y = std::max(0, cy - radius);
-                                 y <= std::min(height+1, cy + radius); y++) {
+                            for (int y = std::max(0, cy - radius); y <= std::min(height + 1, cy + radius); y++) {
                                 if (y >= int(fb->at(x).size()))
                                     break;
                                 if (fb->at(x).at(y).size() > 0)
                                     goto notempty;
                             }
                         }
-                        radius = std::min(std::max(width+1, height+1), radius + 1);
+                        radius = std::min(std::max(width + 1, height + 1), radius + 1);
                     }
                 notempty:
                     iter_at_radius = 0;
@@ -1063,9 +1064,9 @@ class StaticPlacer
                 }
                 // If our randomly chosen cooridnate is out of bounds; or points to a tile with no relevant bels; ignore
                 // it
-                if (nx < 0 || nx > width+1)
+                if (nx < 0 || nx > width + 1)
                     continue;
-                if (ny < 0 || ny > height+1)
+                if (ny < 0 || ny > height + 1)
                     continue;
 
                 if (nx >= int(fb->size()))
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 17d56f96f3..f31de2a768 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -49,8 +49,8 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 // ---------------------------------------------------------------
 
 static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
-                          const SpeedGradePOD **speed_grade,
-                          const char **device_name, const char **package_name, int *device_speed)
+                          const SpeedGradePOD **speed_grade, const char **device_name, const char **package_name,
+                          int *device_speed)
 {
     std::stringstream ss(available_devices);
     std::string name;
@@ -381,14 +381,11 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
             auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
             return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
         } else if (wire.bel_pins.size() > 0) {
-            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x,
-                                  wire.bel_pins[0].rel_bel_loc.y);
+            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y);
         } else if (wire.pips_downhill.size() > 0) {
-            return std::make_pair(wire.pips_downhill[0].rel_loc.x,
-                                  wire.pips_downhill[0].rel_loc.y);
+            return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y);
         } else if (wire.pips_uphill.size() > 0) {
-            return std::make_pair(wire.pips_uphill[0].rel_loc.x,
-                                  wire.pips_uphill[0].rel_loc.y);
+            return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y);
         } else {
             return std::make_pair(int(w.location.x), int(w.location.y));
         }
@@ -430,14 +427,11 @@ BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
             auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
             return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
         } else if (wire.bel_pins.size() > 0) {
-            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x,
-                                  wire.bel_pins[0].rel_bel_loc.y);
+            return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y);
         } else if (wire.pips_downhill.size() > 0) {
-            return std::make_pair(wire.pips_downhill[0].rel_loc.x,
-                                  wire.pips_downhill[0].rel_loc.y);
+            return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y);
         } else if (wire.pips_uphill.size() > 0) {
-            return std::make_pair(wire.pips_uphill[0].rel_loc.x,
-                                  wire.pips_uphill[0].rel_loc.y);
+            return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y);
         } else {
             return std::make_pair(int(w.location.x), int(w.location.y));
         }
@@ -781,7 +775,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
         return TMG_IGNORE;
     } else if (cell->type.in(id_SEDFA, id_GSR, id_JTAGF)) {
         return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
-    } else if (cell->type.in(id_OSCH,id_OSCJ)) {
+    } else if (cell->type.in(id_OSCH, id_OSCJ)) {
         if (port == id_OSC)
             return TMG_GEN_CLOCK;
         else
@@ -851,8 +845,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         if (cell->ramInfo.is_pdp) {
             bool is_output = cell->ports.at(port).type == PORT_OUT;
             // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain
-            if (is_output || port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11,
-                                     id_ADB12))
+            if (is_output ||
+                port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11, id_ADB12))
                 info.clock_port = id_CLKB;
             else
                 info.clock_port = id_CLKA;
diff --git a/machxo2/arch.h b/machxo2/arch.h
index a8172b8fac..45233586ed 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -157,8 +157,8 @@ NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
 
 NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr<char> suffix; });
 
-NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { 
-    int16_t speed; 
+NPNR_PACKED_STRUCT(struct SpeedSupportedPOD {
+    int16_t speed;
     int16_t index;
 });
 

From d40c6e850d4e00e412f7d4c7ea14a5ba1c114693 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 28 Oct 2023 17:22:19 +0200
Subject: [PATCH 505/712] himbaechel: Generation speedup and improvements

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/arch.cc                  | 57 ++++++++++++++++++
 himbaechel/arch.h                   |  7 +++
 himbaechel/chipdb.h                 |  2 +
 himbaechel/himbaechel_dbgen/chip.py | 91 ++++++++++++++---------------
 4 files changed, 111 insertions(+), 46 deletions(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 644dc21ea1..3c0e2bcaa7 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -32,6 +32,8 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+static constexpr int database_version = 2;
+
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
 Arch::Arch(ArchArgs args) : args(args)
@@ -75,6 +77,10 @@ void Arch::load_chipdb(const std::string &path)
     // Check consistency of blob
     if (chip_info->magic != 0x00ca7ca7)
         log_error("chipdb %s does not look like a valid himbächel database!\n", db_path.c_str());
+    if (chip_info->version != database_version)
+        log_error(
+                "chipdb uses db version %d but nextpnr is expecting version %d (did you forget a database rebuild?).\n",
+                chip_info->version, database_version);
     std::string blob_uarch(chip_info->uarch.get());
     if (blob_uarch != args.uarch)
         log_error("database device uarch '%s' does not match selected device uarch '%s'.\n", blob_uarch.c_str(),
@@ -102,6 +108,22 @@ void Arch::set_speed_grade(const std::string &speed)
     }
 }
 
+void Arch::set_package(const std::string &package)
+{
+    if (package.empty())
+        return;
+    // Select speed grade
+    for (const auto &pkg_data : chip_info->packages) {
+        if (IdString(pkg_data.name) == id(package)) {
+            package_info = &pkg_data;
+            break;
+        }
+    }
+    if (!package_info) {
+        log_error("Package '%s' not found in database.\n", package.c_str());
+    }
+}
+
 void Arch::init_tiles()
 {
     for (int y = 0; y < chip_info->height; y++) {
@@ -444,4 +466,39 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     return result;
 }
 
+const PadInfoPOD *Arch::get_package_pin(IdString pin) const
+{
+    NPNR_ASSERT(package_info);
+    for (const auto &pad : package_info->pads) {
+        if (IdString(pad.package_pin) == pin)
+            return &pad;
+    }
+    return nullptr;
+}
+
+const PadInfoPOD *Arch::get_bel_package_pin(BelId bel) const
+{
+    IdStringList bel_name = getBelName(bel);
+    NPNR_ASSERT(package_info);
+    for (const auto &pad : package_info->pads) {
+        if (IdString(pad.tile) == bel_name[0] && IdString(pad.bel) == bel_name[1])
+            return &pad;
+    }
+    return nullptr;
+}
+
+BelId Arch::get_package_pin_bel(IdString pin) const
+{
+    auto pin_data = get_package_pin(pin);
+    if (!pin_data)
+        return BelId();
+    return getBelByName(IdStringList::concat(IdString(pin_data->tile), IdString(pin_data->bel)));
+}
+
+IdString Arch::get_tile_type(int tile) const
+{
+    auto &tile_data = chip_tile_info(chip_info, tile);
+    return IdString(tile_data.type_name);
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 3507eb1b85..55d709cabb 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -422,6 +422,7 @@ struct Arch : BaseArch<ArchRanges>
 
     void load_chipdb(const std::string &path);
     void set_speed_grade(const std::string &speed);
+    void set_package(const std::string &package);
 
     void late_init();
 
@@ -763,6 +764,12 @@ struct Arch : BaseArch<ArchRanges>
     std::vector<IdString> tile_name;
     dict<IdString, int> tile_name2idx;
 
+    // -------------------------------------------------
+    IdString get_tile_type(int tile) const;
+    const PadInfoPOD *get_package_pin(IdString pin) const;
+    const PadInfoPOD *get_bel_package_pin(BelId bel) const;
+    BelId get_package_pin_bel(IdString pin) const;
+
     // Load capacitance and drive resistance for nodes
     // TODO: does this `dict` hurt routing performance too much?
     bool fast_pip_delays = false;
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 622486247d..0e6d197251 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -76,6 +76,8 @@ NPNR_PACKED_STRUCT(struct PipDataPOD {
     uint32_t type;
     uint32_t flags;
     int32_t timing_idx;
+
+    RelPtr<uint8_t> extra_data;
 });
 
 NPNR_PACKED_STRUCT(struct RelTileWireRefPOD {
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index ebc6236927..f7e2af3cdb 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -112,6 +112,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
             pin.serialise(f"{context}_pin{i}", bba)
         # extra data (optional)
         if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
             bba.label(f"{context}_extra_data")
             self.extra_data.serialise(f"{context}_extra_data", bba)
     def serialise(self, context: str, bba: BBAWriter):
@@ -181,15 +182,24 @@ class PipData(BBAStruct):
     pip_type: IdString = field(default_factory=IdString)
     flags: int = 0
     timing_idx: int = -1
+    extra_data: object = None
+
     def serialise_lists(self, context: str, bba: BBAWriter):
-        pass
+        # extra data (optional)
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.src_wire)
         bba.u32(self.dst_wire)
         bba.u32(self.pip_type.index)
         bba.u32(self.flags)
         bba.u32(self.timing_idx)
-
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
 @dataclass
 class TileType(BBAStruct):
     strs: StringPool
@@ -262,6 +272,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
             pip.serialise(f"{context}_pip{i}", bba)
         # extra data (optional)
         if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
             bba.label(f"{context}_extra_data")
             self.extra_data.serialise(f"{context}_extra_data", bba)
     def serialise(self, context: str, bba: BBAWriter):
@@ -281,41 +292,25 @@ class NodeWire:
     y: int
     wire: str
 
-# Post deduplication (node shapes merged, relative coords)
-@dataclass
-class TileWireRef(BBAStruct):
-    dx: int
-    dy: int
-    wire: int
-
-    def serialise_lists(self, context: str, bba: BBAWriter):
-        pass
-    def serialise(self, context: str, bba: BBAWriter):
-        bba.u16(self.dx)
-        bba.u16(self.dy)
-        bba.u16(self.wire)
 
 @dataclass
 class NodeShape(BBAStruct):
-    wires: list[TileWireRef] = field(default_factory=list)
+    wires: list[int] = field(default_factory=list)
     timing_index: int = -1
 
     def key(self):
-        m = hashlib.sha1()
-        for wire in self.wires:
-            m.update(wire.dx.to_bytes(2, 'little', signed=True))
-            m.update(wire.dy.to_bytes(2, 'little', signed=True))
-            m.update(wire.wire.to_bytes(2, 'little'))
+        m = hashlib.md5()
+        m.update(struct.pack("h"*len(self.wires), *self.wires))
         return m.digest()
 
     def serialise_lists(self, context: str, bba: BBAWriter):
         bba.label(f"{context}_wires")
-        for i, w in enumerate(self.wires):
-            w.serialise(f"{context}_w{i}", bba)
+        for w in self.wires:
+            bba.u16(w)
         if len(self.wires) % 2 != 0:
             bba.u16(0) # alignment
     def serialise(self, context: str, bba: BBAWriter):
-        bba.slice(f"{context}_wires", len(self.wires))
+        bba.slice(f"{context}_wires", len(self.wires)//3)
         bba.u32(self.timing_index) # timing index (not yet used)
 
 MODE_TILE_WIRE = 0x7000
@@ -337,23 +332,20 @@ def serialise(self, context: str, bba: BBAWriter):
 
 @dataclass
 class TileRoutingShape(BBAStruct):
-    wire_to_node: list[RelNodeRef] = field(default_factory=list)
+    wire_to_node: list[int] = field(default_factory=list)
     def key(self):
-        m = hashlib.sha1()
-        for wire in self.wire_to_node:
-            m.update(wire.dx_mode.to_bytes(2, 'little', signed=True))
-            m.update(wire.dy.to_bytes(2, 'little', signed=(wire.dy < 0)))
-            m.update(wire.wire.to_bytes(2, 'little', signed=True))
+        m = hashlib.md5()
+        m.update(struct.pack("h"*len(self.wire_to_node), *self.wire_to_node))
         return m.digest()
 
     def serialise_lists(self, context: str, bba: BBAWriter):
         bba.label(f"{context}_w2n")
-        for i, w in enumerate(self.wire_to_node):
-            w.serialise(f"{context}_w{i}", bba)
+        for x in self.wire_to_node:
+            bba.u16(x)
         if len(self.wire_to_node) % 2 != 0:
             bba.u16(0) # alignment
     def serialise(self, context: str, bba: BBAWriter):
-        bba.slice(f"{context}_w2n", len(self.wire_to_node))
+        bba.slice(f"{context}_w2n", len(self.wire_to_node)//3)
         bba.u32(-1) # timing index
 
 @dataclass
@@ -701,6 +693,7 @@ def create_tile_type(self, name: str):
         return tt
     def set_tile_type(self, x: int, y: int, type: str):
         self.tiles[y][x].type_idx = self.tile_type_idx[type]
+        return self.tiles[y][x]
     def tile_type_at(self, x: int, y: int):
         assert self.tiles[y][x].type_idx is not None, f"tile type at ({x}, {y}) must be set"
         return self.tile_types[self.tiles[y][x].type_idx]
@@ -715,11 +708,12 @@ def add_node(self, wires: list[NodeWire]):
         # compute node shape
         shape = NodeShape()
         for w in wires:
-            wire_id = w.wire if w.wire is IdString else self.strs.id(w.wire)
-            shape.wires.append(TileWireRef(
-                dx=w.x-x0, dy=w.y-y0,
-                wire=self.tile_type_at(w.x, w.y)._wire2idx[wire_id]
-            ))
+            if isinstance(w.wire, int):
+                wire_index = w.wire
+            else:
+                wire_id = w.wire if w.wire is IdString else self.strs.id(w.wire)
+                wire_index = self.tile_type_at(w.x, w.y)._wire2idx[wire_id]
+            shape.wires += [w.x-x0, w.y-y0, wire_index]
         # deduplicate node shapes
         key = shape.key()
         if key in self.node_shape_idx:
@@ -731,24 +725,29 @@ def add_node(self, wires: list[NodeWire]):
         # update tile wire to node ref
         for i, w in enumerate(wires):
             inst = self.tiles[w.y][w.x]
-            wire_idx = shape.wires[i].wire
+            wire_idx = shape.wires[i*3+2]
             # make sure there's actually enough space; first
-            if wire_idx >= len(inst.shape.wire_to_node):
-                inst.shape.wire_to_node += [RelNodeRef() for k in range(len(inst.shape.wire_to_node), wire_idx+1)]
+            while 3*wire_idx >= len(inst.shape.wire_to_node):
+                inst.shape.wire_to_node += [MODE_TILE_WIRE, 0, 0]
             if i == 0:
                 # root of the node. we don't need to back-reference anything because the node is based here
                 # so we re-use the structure to store the index of the node shape, instead
-                assert inst.shape.wire_to_node[wire_idx].dx_mode == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
-                inst.shape.wire_to_node[wire_idx] = RelNodeRef(MODE_IS_ROOT, (shape_idx & 0xFFFF), ((shape_idx >> 16) & 0xFFFF))
+                assert inst.shape.wire_to_node[3*wire_idx+0] == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
+                inst.shape.wire_to_node[3*wire_idx+0] = MODE_IS_ROOT
+                inst.shape.wire_to_node[3*wire_idx+1] = (shape_idx & 0xFFFF)
+                inst.shape.wire_to_node[3*wire_idx+2] = ((shape_idx >> 16) & 0xFFFF)
             else:
                 # back-reference to the root of the node
                 dx = x0 - w.x
                 dy = y0 - w.y
                 assert dx < MODE_TILE_WIRE, "dx range causes overlap with magic values!"
-                assert inst.shape.wire_to_node[wire_idx].dx_mode == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
-                inst.shape.wire_to_node[wire_idx] = RelNodeRef(dx, dy, shape.wires[0].wire)
+                assert inst.shape.wire_to_node[3*wire_idx+0] == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
+                inst.shape.wire_to_node[3*wire_idx+0] = dx
+                inst.shape.wire_to_node[3*wire_idx+1] = dy
+                inst.shape.wire_to_node[3*wire_idx+2] = shape.wires[0*3+2]
 
     def flatten_tile_shapes(self):
+        print("Deduplicating tile shapes...")
         for row in self.tiles:
             for tile in row:
                 key = tile.shape.key()
@@ -812,7 +811,7 @@ def serialise(self, bba: BBAWriter):
 
         bba.label("chip_info")
         bba.u32(0x00ca7ca7) # magic
-        bba.u32(1) # version (TODO)
+        bba.u32(2) # version
         bba.u32(self.width)
         bba.u32(self.height)
 

From d6f54fd9df879643f795b3d96c25e6a84cf48a77 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Sun, 29 Oct 2023 06:54:53 +0000
Subject: [PATCH 506/712] ice40: add static placer support

---
 common/place/placer_static.cc |  2 +-
 ice40/arch.cc                 | 42 ++++++++++++++++++++++++++++++++++-
 2 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 729785bb34..779e2247b8 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -293,7 +293,7 @@ class StaticPlacer
     {
         if (ci->udata == -1) {
             // not handled?
-            NPNR_ASSERT(ci->bel != BelId()); // already fixed
+            NPNR_ASSERT_MSG(ci->bel != BelId(), stringf("Cell %s of type %s has no bel", ci->name.c_str(ctx), ci->type.c_str(ctx)).c_str()); // already fixed
             return RealPair(ctx->getBelLocation(ci->bel), 0.5f);
         } else {
             return ref ? mcells.at(ci->udata).ref_pos : mcells.at(ci->udata).pos;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 28791b95fa..9cc0dfe361 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -27,6 +27,7 @@
 #include "nextpnr.h"
 #include "placer1.h"
 #include "placer_heap.h"
+#include "placer_static.h"
 #include "router1.h"
 #include "router2.h"
 #include "timing_opt.h"
@@ -650,6 +651,45 @@ bool Arch::place()
     } else if (placer == "sa") {
         if (!placer1(getCtx(), Placer1Cfg(getCtx())))
             return false;
+    } else if (placer == "static") {
+        PlacerStaticCfg cfg(getCtx());
+        {
+            cfg.cell_groups.emplace_back();
+            auto &comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("COMB");
+            comb.cell_area[id_ICESTORM_LC] = StaticRect(1.0f, 0.125f);
+            comb.bel_area[id_ICESTORM_LC] = StaticRect(1.0f, 0.125f);
+            comb.spacer_rect = StaticRect(1.0f, 0.125f);
+        }
+
+        {
+            cfg.cell_groups.emplace_back();
+            auto &comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("RAM");
+            comb.cell_area[id_ICESTORM_RAM] = StaticRect(1.0f, 2.0f);
+            comb.bel_area[id_ICESTORM_RAM] = StaticRect(1.0f, 2.0f);
+            comb.spacer_rect = StaticRect(1.0f, 2.0f);
+        }
+
+        {
+            cfg.cell_groups.emplace_back();
+            auto &comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("GB");
+            comb.cell_area[id_SB_GB] = StaticRect(0.5f, 0.5f);
+            comb.bel_area[id_SB_GB] = StaticRect(0.5f, 0.5f);
+            comb.spacer_rect = StaticRect(0.5f, 0.5f);
+        }
+
+        {
+            cfg.cell_groups.emplace_back();
+            auto &comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("WARMBOOT");
+            comb.cell_area[id_SB_WARMBOOT] = StaticRect(1.0f, 1.0f);
+            comb.bel_area[id_SB_WARMBOOT] = StaticRect(1.0f, 1.0f);
+            comb.spacer_rect = StaticRect(1.0f, 1.0f);
+        }
+        if (!placer_static(getCtx(), cfg))
+            return false;
     } else {
         log_error("iCE40 architecture does not support placer '%s'\n", placer.c_str());
     }
@@ -1250,7 +1290,7 @@ BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
 
 const std::string Arch::defaultPlacer = "heap";
 
-const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
+const std::vector<std::string> Arch::availablePlacers = {"sa", "heap", "static"};
 
 const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};

From 214cc4315ec0fef28cac843dd16ce7af4a42fe86 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 6 Nov 2023 13:00:36 +0000
Subject: [PATCH 507/712] static: density multiplier should be a vector

---
 common/place/placer_static.cc | 38 +++++++++++++++++++++++------------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 779e2247b8..4db44f3f43 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -703,7 +703,7 @@ class StaticPlacer
         return gradient;
     }
 
-    float dens_penalty = 0.025f;
+    std::vector<float> dens_penalty;
     float nesterov_a = 1.0f;
 
     void update_gradients(bool ref = true, bool set_prev = true, bool init_penalty = false)
@@ -748,18 +748,27 @@ class StaticPlacer
         }
         if (init_penalty) {
             // set initial density penalty
-            float wirelen_sum = 0;
-            float force_sum = 0;
+            dict<int, float> wirelen_sum;
+            dict<int, float> force_sum;
             for (auto &cell : ctx->cells) {
                 CellInfo *ci = cell.second.get();
                 if (ci->udata == -1)
                     continue;
                 auto &mc = mcells.at(ci->udata);
-                wirelen_sum += std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y);
-                force_sum += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
+                auto res1 = wirelen_sum.insert({mc.group, std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y)});
+                if (!res1.second)
+                    res1.first->second += std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y);
+                auto res2 = force_sum.insert({mc.group, std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y)});
+                if (!res2.second)
+                    res2.first->second += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
+            }
+            dens_penalty = std::vector<float>(wirelen_sum.size(), 0.0);
+            for (auto& item : wirelen_sum) {
+                auto group = item.first;
+                auto wirelen = item.second;
+                dens_penalty[group] = wirelen / force_sum.at(group);
+                log_info(" initial density penalty for %s: %f\n", cfg.cell_groups.at(group).name.c_str(ctx), dens_penalty[group]);
             }
-            dens_penalty = wirelen_sum / force_sum;
-            log_info(" initial density penalty: %f\n", dens_penalty);
         }
         // Third loop: compute total gradient, and precondition
         // TODO: ALM as well as simple penalty
@@ -772,11 +781,13 @@ class StaticPlacer
             }
 #endif
             // Preconditioner from replace for now
-            float precond = std::max(1.0f, float(cell.pin_count) + dens_penalty * cell.rect.area());
-            (ref ? cell.ref_total_grad : cell.total_grad) =
-                    (((ref ? cell.ref_wl_grad : cell.wl_grad) * -1) -
-                     (ref ? cell.ref_dens_grad : cell.dens_grad) * dens_penalty) /
-                    precond;
+
+            float precond = std::max(1.0f, float(cell.pin_count) + dens_penalty[cell.group] * cell.rect.area());
+            if (ref) {
+                cell.ref_total_grad = ((cell.ref_wl_grad * -1) - cell.ref_dens_grad * dens_penalty[cell.group]) / precond;
+            } else {
+                cell.total_grad = ((cell.wl_grad * -1) - cell.dens_grad * dens_penalty[cell.group]) / precond;
+            }
         }
     }
 
@@ -1250,7 +1261,8 @@ class StaticPlacer
         bool legalised_ip = false;
         while (true) {
             step();
-            dens_penalty *= 1.025;
+            for (auto& penalty : dens_penalty)
+                penalty *= 1.025;
             if (!legalised_ip) {
                 float ip_overlap = 0;
                 for (int i = 2; i < int(groups.size()); i++)

From e3c44dd20a9166436261636835b9958bef7f35c2 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 6 Nov 2023 13:07:26 +0000
Subject: [PATCH 508/712] ice40: add IO group to static

---
 ice40/arch.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 9cc0dfe361..77261327ed 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -688,6 +688,15 @@ bool Arch::place()
             comb.bel_area[id_SB_WARMBOOT] = StaticRect(1.0f, 1.0f);
             comb.spacer_rect = StaticRect(1.0f, 1.0f);
         }
+
+        {
+            cfg.cell_groups.emplace_back();
+            auto &comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("IO");
+            comb.cell_area[id_SB_IO] = StaticRect(0.5f, 0.5f);
+            comb.bel_area[id_SB_IO] = StaticRect(0.5f, 0.5f);
+            comb.spacer_rect = StaticRect(1.0f, 1.0f);
+        }
         if (!placer_static(getCtx(), cfg))
             return false;
     } else {

From fe52840054636585bdab1c3c80941b4405ef8d3e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 18 Oct 2023 15:57:33 +0100
Subject: [PATCH 509/712] archapi: Add new API for global constant routing

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/arch_api.h      |   1 +
 common/kernel/base_arch.h     |   1 +
 common/kernel/nextpnr_types.h |   4 +
 common/route/router1.cc       | 361 +++++++++++++++++++++++++++++++---
 common/route/router2.cc       | 119 +++++------
 docs/archapi.md               |   8 +
 nexus/arch.h                  |   7 +
 nexus/pack.cc                 |   2 +
 8 files changed, 424 insertions(+), 79 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 0bfaaf2dcb..88582adde7 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -83,6 +83,7 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual WireId getConflictingWireWire(WireId wire) const = 0;
     virtual NetInfo *getConflictingWireNet(WireId wire) const = 0;
     virtual DelayQuad getWireDelay(WireId wire) const = 0;
+    virtual IdString getWireConstantValue(WireId wire) const = 0;
     // Pip methods
     virtual typename R::AllPipsRangeT getPips() const = 0;
     virtual PipId getPipByName(IdStringList name) const = 0;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index a27e261d1f..94f88af700 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -237,6 +237,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
     }
     virtual WireId getConflictingWireWire(WireId wire) const override { return wire; };
     virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); }
+    virtual IdString getWireConstantValue(WireId wire) const override { return {}; }
 
     // Pip methods
     virtual IdString getPipType(PipId pip) const override { return IdString(); }
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index a5e240a283..4c9dba600a 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -132,6 +132,10 @@ struct NetInfo : ArchNetInfo
     indexed_store<PortRef> users;
     dict<IdString, Property> attrs;
 
+    // If this is set to a non-empty ID, then the driver is ignored and it will be routed from any wire with a matching
+    // getWireConstantValue
+    IdString constant_value;
+
     // wire -> uphill_pip
     dict<WireId, PipMap> wires;
 
diff --git a/common/route/router1.cc b/common/route/router1.cc
index e832177d2c..a3ebdb60c1 100644
--- a/common/route/router1.cc
+++ b/common/route/router1.cc
@@ -133,8 +133,10 @@ struct Router1
         if (queued_arcs.count(arc))
             return;
 
-        delay_t pri = ctx->estimateDelay(src_wire, dst_wire) *
-                      (100 * tmg.get_criticality(CellPortKey(arc.net_info->users.at(arc.user_idx))));
+        delay_t pri = (arc.net_info->constant_value == IdString())
+                              ? (ctx->estimateDelay(src_wire, dst_wire) *
+                                 (100 * tmg.get_criticality(CellPortKey(arc.net_info->users.at(arc.user_idx)))))
+                              : 0;
 
         arc_entry entry;
         entry.arc = arc;
@@ -293,7 +295,7 @@ struct Router1
         if (net_info->is_global)
             return true;
 #endif
-        if (net_info->driver.cell == nullptr)
+        if (net_info->driver.cell == nullptr && net_info->constant_value == IdString())
             return true;
 
         return false;
@@ -380,7 +382,7 @@ struct Router1
 
             auto src_wire = ctx->getNetinfoSourceWire(net_info);
 
-            if (src_wire == WireId())
+            if (src_wire == WireId() && net_info->constant_value == IdString())
                 log_error("No wire found for port %s on source cell %s.\n", ctx->nameOf(net_info->driver.port),
                           ctx->nameOf(net_info->driver.cell));
 
@@ -430,7 +432,8 @@ struct Router1
                     wire_to_arcs[cursor].insert(arc);
                     arc_to_wires[arc].insert(cursor);
 
-                    while (src_wire != cursor) {
+                    while (src_wire != cursor && (net_info->constant_value == IdString() ||
+                                                  ctx->getWireConstantValue(cursor) != net_info->constant_value)) {
                         auto it = net_info->wires.find(cursor);
                         if (it == net_info->wires.end()) {
                             arc_queue_insert(arc, src_wire, dst_wire);
@@ -797,6 +800,298 @@ struct Router1
         return true;
     }
 
+    bool route_const_arc(const arc_key &arc, bool ripup)
+    {
+
+        NetInfo *net_info = arc.net_info;
+        auto user_idx = arc.user_idx;
+
+        auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx], arc.phys_idx);
+        ripup_flag = false;
+
+        if (ctx->debug) {
+            log("Routing constant arc %d on net %s (%d arcs total):\n", user_idx.idx(), ctx->nameOf(net_info),
+                int(net_info->users.capacity()));
+            log("  value ... %s\n", ctx->nameOf(net_info->constant_value));
+            log("  sink ..... %s\n", ctx->nameOfWire(dst_wire));
+        }
+
+        // unbind wires that are currently used exclusively by this arc
+
+        pool<WireId> old_arc_wires;
+        old_arc_wires.swap(arc_to_wires[arc]);
+
+        for (WireId wire : old_arc_wires) {
+            auto &arc_wires = wire_to_arcs.at(wire);
+            NPNR_ASSERT(arc_wires.count(arc));
+            arc_wires.erase(arc);
+            if (arc_wires.empty()) {
+                if (ctx->debug)
+                    log("  unbind %s\n", ctx->nameOfWire(wire));
+                ctx->unbindWire(wire);
+            }
+        }
+
+        // special case
+
+        if (ctx->getWireConstantValue(dst_wire) == net_info->constant_value) {
+            NetInfo *bound = ctx->getBoundWireNet(dst_wire);
+            if (bound != nullptr)
+                NPNR_ASSERT(bound == net_info);
+            else {
+                ctx->bindWire(dst_wire, net_info, STRENGTH_WEAK);
+            }
+            arc_to_wires[arc].insert(dst_wire);
+            wire_to_arcs[dst_wire].insert(arc);
+            return true;
+        }
+
+        // reset wire queue
+
+        if (!queue.empty()) {
+            std::priority_queue<QueuedWire, std::vector<QueuedWire>, QueuedWire::Greater> new_queue;
+            queue.swap(new_queue);
+        }
+        dict<WireId, QueuedWire> visited;
+
+        // A* main loop
+
+        int visitCnt = 0;
+        int maxVisitCnt = INT_MAX;
+        delay_t best_score = -1;
+        WireId best_src;
+
+        {
+            QueuedWire qw;
+            qw.wire = dst_wire;
+            qw.pip = PipId();
+            qw.delay = ctx->getWireDelay(qw.wire).maxDelay();
+            qw.penalty = 0;
+            qw.bonus = 0;
+            qw.randtag = ctx->rng();
+
+            queue.push(qw);
+            visited[qw.wire] = qw;
+        }
+
+        while (visitCnt++ < maxVisitCnt && !queue.empty()) {
+            QueuedWire qw = queue.top();
+            queue.pop();
+
+            for (auto pip : ctx->getPipsUphill(qw.wire)) {
+                delay_t next_delay = qw.delay + ctx->getPipDelay(pip).maxDelay();
+                delay_t next_penalty = qw.penalty;
+                delay_t next_bonus = qw.bonus;
+                delay_t penalty_delta = 0;
+
+                WireId next_wire = ctx->getPipSrcWire(pip);
+                next_delay += ctx->getWireDelay(next_wire).maxDelay();
+
+                WireId conflictWireWire = WireId(), conflictPipWire = WireId();
+                NetInfo *conflictWireNet = nullptr, *conflictPipNet = nullptr;
+
+                if (net_info->wires.count(qw.wire)) {
+                    if (net_info->wires.at(qw.wire).pip != pip)
+                        continue;
+                    next_bonus += cfg.reuseBonus;
+                } else {
+                    if (!ctx->checkWireAvail(next_wire)) {
+                        if (!ripup)
+                            continue;
+                        conflictWireWire = ctx->getConflictingWireWire(next_wire);
+                        if (conflictWireWire == WireId()) {
+                            conflictWireNet = ctx->getConflictingWireNet(next_wire);
+                            if (conflictWireNet == nullptr)
+                                continue;
+                            else {
+                                if (conflictWireNet->wires.count(next_wire) &&
+                                    conflictWireNet->wires.at(next_wire).strength > STRENGTH_STRONG)
+                                    continue;
+                            }
+                        } else {
+                            NetInfo *conflicting = ctx->getBoundWireNet(conflictWireWire);
+                            if (conflicting != nullptr) {
+                                if (conflicting->wires.count(conflictWireWire) &&
+                                    conflicting->wires.at(conflictWireWire).strength > STRENGTH_STRONG)
+                                    continue;
+                            }
+                        }
+                    }
+
+                    if (!ctx->checkPipAvail(pip)) {
+                        if (!ripup)
+                            continue;
+                        conflictPipWire = ctx->getConflictingPipWire(pip);
+                        if (conflictPipWire == WireId()) {
+                            conflictPipNet = ctx->getConflictingPipNet(pip);
+                            if (conflictPipNet == nullptr)
+                                continue;
+                            else {
+                                if (conflictPipNet->wires.count(next_wire) &&
+                                    conflictPipNet->wires.at(next_wire).strength > STRENGTH_STRONG)
+                                    continue;
+                            }
+                        } else {
+                            NetInfo *conflicting = ctx->getBoundWireNet(conflictPipWire);
+                            if (conflicting != nullptr) {
+                                if (conflicting->wires.count(conflictPipWire) &&
+                                    conflicting->wires.at(conflictPipWire).strength > STRENGTH_STRONG)
+                                    continue;
+                            }
+                        }
+                    }
+
+                    if (conflictWireNet != nullptr && conflictPipWire != WireId() &&
+                        conflictWireNet->wires.count(conflictPipWire))
+                        conflictPipWire = WireId();
+
+                    if (conflictPipNet != nullptr && conflictWireWire != WireId() &&
+                        conflictPipNet->wires.count(conflictWireWire))
+                        conflictWireWire = WireId();
+
+                    if (conflictWireWire == conflictPipWire)
+                        conflictWireWire = WireId();
+
+                    if (conflictWireNet == conflictPipNet)
+                        conflictWireNet = nullptr;
+
+                    if (conflictWireWire != WireId()) {
+                        auto scores_it = wireScores.find(conflictWireWire);
+                        if (scores_it != wireScores.end())
+                            penalty_delta += scores_it->second * cfg.wireRipupPenalty;
+                        penalty_delta += cfg.wireRipupPenalty;
+                    }
+
+                    if (conflictPipWire != WireId()) {
+                        auto scores_it = wireScores.find(conflictPipWire);
+                        if (scores_it != wireScores.end())
+                            penalty_delta += scores_it->second * cfg.wireRipupPenalty;
+                        penalty_delta += cfg.wireRipupPenalty;
+                    }
+
+                    if (conflictWireNet != nullptr) {
+                        auto scores_it = netScores.find(conflictWireNet);
+                        if (scores_it != netScores.end())
+                            penalty_delta += scores_it->second * cfg.netRipupPenalty;
+                        penalty_delta += cfg.netRipupPenalty;
+                        penalty_delta += conflictWireNet->wires.size() * cfg.wireRipupPenalty;
+                    }
+
+                    if (conflictPipNet != nullptr) {
+                        auto scores_it = netScores.find(conflictPipNet);
+                        if (scores_it != netScores.end())
+                            penalty_delta += scores_it->second * cfg.netRipupPenalty;
+                        penalty_delta += cfg.netRipupPenalty;
+                        penalty_delta += conflictPipNet->wires.size() * cfg.wireRipupPenalty;
+                    }
+                }
+
+                next_penalty += penalty_delta;
+
+                delay_t next_score = next_delay + next_penalty;
+                NPNR_ASSERT(next_score >= 0);
+
+                if ((best_score >= 0) && (next_score - next_bonus - cfg.estimatePrecision > best_score))
+                    continue;
+
+                auto old_visited_it = visited.find(next_wire);
+                if (old_visited_it != visited.end()) {
+                    continue;
+                }
+
+                QueuedWire next_qw;
+                next_qw.wire = next_wire;
+                next_qw.pip = pip;
+                next_qw.delay = next_delay;
+                next_qw.penalty = next_penalty;
+                next_qw.bonus = next_bonus;
+                next_qw.randtag = ctx->rng();
+
+                visited[next_qw.wire] = next_qw;
+                queue.push(next_qw);
+
+                if (ctx->getWireConstantValue(next_wire) == net_info->constant_value) {
+                    maxVisitCnt = std::min(maxVisitCnt, 2 * visitCnt + (next_qw.penalty > 0 ? 100 : 0));
+                    if (best_src == WireId() || next_score < best_score) {
+                        best_src = next_wire;
+                    }
+                    best_score = next_score - next_bonus;
+                }
+            }
+        }
+
+        if (ctx->debug)
+            log("  total number of visited nodes: %d\n", visitCnt);
+
+        if (best_src == WireId()) {
+            if (ctx->debug)
+                log("  no route found for this arc\n");
+            return false;
+        }
+
+        if (ctx->debug) {
+            log("  final route delay:   %8.2f\n", ctx->getDelayNS(visited[dst_wire].delay));
+            log("  final route penalty: %8.2f\n", ctx->getDelayNS(visited[dst_wire].penalty));
+            log("  final route bonus:   %8.2f\n", ctx->getDelayNS(visited[dst_wire].bonus));
+        }
+
+        // bind resulting route (and maybe unroute other nets)
+
+        pool<WireId> unassign_wires = arc_to_wires[arc];
+
+        WireId cursor = best_src;
+
+        if (!net_info->wires.count(cursor)) {
+            if (!ctx->checkWireAvail(cursor)) {
+                ripup_wire(cursor);
+                NPNR_ASSERT(ctx->checkWireAvail(cursor));
+            }
+            ctx->bindWire(cursor, net_info, STRENGTH_WEAK);
+        }
+
+        wire_to_arcs[cursor].insert(arc);
+        arc_to_wires[arc].insert(cursor);
+
+        while (1) {
+            auto pip = visited[cursor].pip;
+
+            if (pip == PipId()) {
+                NPNR_ASSERT(cursor == dst_wire);
+                break;
+            }
+
+            WireId next = ctx->getPipDstWire(pip);
+
+            if (!net_info->wires.count(next) || (net_info->wires.count(next) && net_info->wires.at(next).pip != pip)) {
+                if (!ctx->checkWireAvail(next)) {
+                    ripup_wire(next);
+                    NPNR_ASSERT(ctx->checkWireAvail(next));
+                }
+
+                if (!ctx->checkPipAvail(pip)) {
+                    ripup_pip(pip);
+                    NPNR_ASSERT(ctx->checkPipAvail(pip));
+                }
+
+                if (ctx->debug)
+                    log("    bind pip %s\n", ctx->nameOfPip(pip));
+                ctx->bindPip(pip, net_info, STRENGTH_WEAK);
+            }
+
+            wire_to_arcs[next].insert(arc);
+            arc_to_wires[arc].insert(next);
+
+            cursor = next;
+        }
+
+        if (ripup_flag)
+            arcs_with_ripup++;
+        else
+            arcs_without_ripup++;
+
+        return true;
+    }
+
     delay_t find_slack_thresh()
     {
         // If more than 5% of arcs have negative slack; use the 5% threshold as a ripup criteria
@@ -911,15 +1206,26 @@ bool router1(Context *ctx, const Router1Cfg &cfg)
                 log("-- %d --\n", iter_cnt);
 
             arc_key arc = router.arc_queue_pop();
-
-            if (!router.route_arc(arc, true)) {
-                log_warning("Failed to find a route for arc %d of net %s.\n", arc.user_idx.idx(),
-                            ctx->nameOf(arc.net_info));
+            if (arc.net_info->constant_value != IdString()) {
+                if (!router.route_const_arc(arc, true)) {
+                    log_warning("Failed to find a route for arc %d of net %s.\n", arc.user_idx.idx(),
+                                ctx->nameOf(arc.net_info));
 #ifndef NDEBUG
-                router.check();
-                ctx->check();
+                    router.check();
+                    ctx->check();
 #endif
-                return false;
+                    return false;
+                }
+            } else {
+                if (!router.route_arc(arc, true)) {
+                    log_warning("Failed to find a route for arc %d of net %s.\n", arc.user_idx.idx(),
+                                ctx->nameOf(arc.net_info));
+#ifndef NDEBUG
+                    router.check();
+                    ctx->check();
+#endif
+                    return false;
+                }
             }
             // Timing driven ripup
             if (timing_ripup && router.arc_queue.empty() && timing_fail_count < 50) {
@@ -1039,17 +1345,19 @@ bool Context::checkRoutedDesign() const
         }
 
         auto src_wire = ctx->getNetinfoSourceWire(net_info);
-        if (src_wire == WireId()) {
-            log_assert(net_info->driver.cell == nullptr);
-            if (ctx->debug)
-                log("  undriven and unrouted\n");
-            continue;
-        }
+        if (net_info->constant_value == IdString()) {
+            if (src_wire == WireId()) {
+                log_assert(net_info->driver.cell == nullptr);
+                if (ctx->debug)
+                    log("  undriven and unrouted\n");
+                continue;
+            }
 
-        if (net_info->wires.count(src_wire) == 0) {
-            if (ctx->debug)
-                log("  source (%s) not bound to net\n", ctx->nameOfWire(src_wire));
-            found_unrouted = true;
+            if (net_info->wires.count(src_wire) == 0) {
+                if (ctx->debug)
+                    log("  source (%s) not bound to net\n", ctx->nameOfWire(src_wire));
+                found_unrouted = true;
+            }
         }
 
         dict<WireId, store_index<PortRef>> dest_wires;
@@ -1100,7 +1408,14 @@ bool Context::checkRoutedDesign() const
             log("  driver: %s\n", ctx->nameOfWire(src_wire));
             logged_wires.insert(src_wire);
         }
-        setOrderNum(src_wire, 1);
+        if (net_info->constant_value != IdString()) {
+            for (const auto &wire : net_info->wires) {
+                if (wire.second.pip == PipId() && ctx->getWireConstantValue(wire.first) == net_info->constant_value)
+                    setOrderNum(wire.first, 1);
+            }
+        } else {
+            setOrderNum(src_wire, 1);
+        }
 
         pool<WireId> dangling_wires;
 
diff --git a/common/route/router2.cc b/common/route/router2.cc
index db8885d47f..49fe327a06 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -346,7 +346,8 @@ struct Router2
             return;
         WireId src = nets.at(net->udata).src_wire;
         WireId cursor = ad.sink_wire;
-        while (cursor != src) {
+        while (cursor != src &&
+               (net->constant_value == IdString() || ctx->getWireConstantValue(cursor) == net->constant_value)) {
             PipId pip = nd.wires.at(cursor).first;
             unbind_pip_internal(nd, user, cursor);
             cursor = ctx->getPipSrcWire(pip);
@@ -533,18 +534,11 @@ struct Router2
 
     // These nets have very-high-fanout pips and special rules must be followed (only working backwards) to avoid
     // crippling perf
-    bool is_pseudo_const_net(const NetInfo *net)
-    {
-#ifdef ARCH_NEXUS
-        if (net->driver.cell != nullptr && net->driver.cell->type == id_VCC_DRV)
-            return true;
-#endif
-        return false;
-    }
+    bool is_dedi_const_net(const NetInfo *net) { return net->constant_value != IdString(); }
 
     void update_wire_by_loc(ThreadContext &t, NetInfo *net, store_index<PortRef> i, size_t phys_pin, bool is_mt)
     {
-        if (is_pseudo_const_net(net))
+        if (is_dedi_const_net(net))
             return;
         auto &nd = nets.at(net->udata);
         auto &ad = nd.arcs.at(i.idx()).at(phys_pin);
@@ -613,16 +607,17 @@ struct Router2
         auto &nd = nets[net->udata];
         auto &ad = nd.arcs.at(i.idx()).at(phys_pin);
         auto &usr = net->users.at(i);
+        bool const_mode = is_dedi_const_net(net);
         ROUTE_LOG_DBG("Routing arc %d of net '%s' (%d, %d) -> (%d, %d)\n", i.idx(), ctx->nameOf(net), ad.bb.x0,
                       ad.bb.y0, ad.bb.x1, ad.bb.y1);
         WireId src_wire = ctx->getNetinfoSourceWire(net), dst_wire = ctx->getNetinfoSinkWire(net, usr, phys_pin);
-        if (src_wire == WireId())
+        if (src_wire == WireId() && !const_mode)
             ARC_LOG_ERR("No wire found for port %s on source cell %s.\n", ctx->nameOf(net->driver.port),
                         ctx->nameOf(net->driver.cell));
         if (dst_wire == WireId())
             ARC_LOG_ERR("No wire found for port %s on destination cell %s.\n", ctx->nameOf(usr.port),
                         ctx->nameOf(usr.cell));
-        int src_wire_idx = wire_to_idx.at(src_wire);
+        int src_wire_idx = const_mode ? -1 : wire_to_idx.at(src_wire);
         int dst_wire_idx = wire_to_idx.at(dst_wire);
         // Calculate a timing weight based on criticality
         float crit = get_arc_crit(net, i);
@@ -683,12 +678,13 @@ struct Router2
 
             if (mode == 0 && t.fwd_queue.size() < 4)
                 continue;
-
-            if (mode == 1 && !is_pseudo_const_net(net)) {
-                // Seed forwards with the source wire, if less than 8 existing wires added
-                seed_queue_fwd(src_wire);
-            } else {
-                set_visited_fwd(t, src_wire_idx, PipId(), 0.0);
+            if (!const_mode) {
+                if (mode == 1) {
+                    // Seed forwards with the source wire, if less than 8 existing wires added
+                    seed_queue_fwd(src_wire);
+                } else {
+                    set_visited_fwd(t, src_wire_idx, PipId(), 0.0);
+                }
             }
             auto seed_queue_bwd = [&](WireId wire) {
                 WireScore base_score;
@@ -711,7 +707,7 @@ struct Router2
                                 : (!t.fwd_queue.empty() || !t.bwd_queue.empty())) &&
                    (!is_bb || iter < toexplore)) {
                 ++iter;
-                if (!t.fwd_queue.empty()) {
+                if (!t.fwd_queue.empty() && !const_mode) {
                     // Explore forwards
                     auto curr = t.fwd_queue.top();
                     t.fwd_queue.pop();
@@ -760,12 +756,13 @@ struct Router2
                     auto curr = t.bwd_queue.top();
                     t.bwd_queue.pop();
                     ++explored;
-                    if (was_visited_fwd(curr.wire, std::numeric_limits<float>::max())) {
+                    auto &curr_data = flat_wires.at(curr.wire);
+                    if (was_visited_fwd(curr.wire, std::numeric_limits<float>::max()) ||
+                        (const_mode && ctx->getWireConstantValue(curr_data.w) == net->constant_value)) {
                         // Meet in the middle; done
                         midpoint_wire = curr.wire;
                         break;
                     }
-                    auto &curr_data = flat_wires.at(curr.wire);
                     // Don't allow the same wire to be bound to the same net with a different driving pip
                     PipId bound_pip;
                     auto fnd_wire = nd.wires.find(curr_data.w);
@@ -809,44 +806,48 @@ struct Router2
         ArcRouteResult result = ARC_SUCCESS;
         if (midpoint_wire != -1) {
             ROUTE_LOG_DBG("   Routed (explored %d wires): ", explored);
-            int cursor_bwd = midpoint_wire;
-            while (was_visited_fwd(cursor_bwd, std::numeric_limits<float>::max())) {
-                PipId pip = flat_wires.at(cursor_bwd).pip_fwd;
-                if (pip == PipId() && cursor_bwd != src_wire_idx)
-                    break;
-                bind_pip_internal(nd, i, cursor_bwd, pip);
-                if (ctx->debug && !is_mt) {
-                    auto &wd = flat_wires.at(cursor_bwd);
-                    ROUTE_LOG_DBG("      fwd wire: %s (curr %d hist %f share %d)\n", ctx->nameOfWire(wd.w),
-                                  wd.curr_cong - 1, wd.hist_cong_cost, nd.wires.at(wd.w).second);
-                }
-                if (pip == PipId()) {
-                    break;
+            if (const_mode) {
+                bind_pip_internal(nd, i, midpoint_wire, PipId());
+            } else {
+                int cursor_bwd = midpoint_wire;
+                while (was_visited_fwd(cursor_bwd, std::numeric_limits<float>::max())) {
+                    PipId pip = flat_wires.at(cursor_bwd).pip_fwd;
+                    if (pip == PipId() && cursor_bwd != src_wire_idx)
+                        break;
+                    bind_pip_internal(nd, i, cursor_bwd, pip);
+                    if (ctx->debug && !is_mt) {
+                        auto &wd = flat_wires.at(cursor_bwd);
+                        ROUTE_LOG_DBG("      fwd wire: %s (curr %d hist %f share %d)\n", ctx->nameOfWire(wd.w),
+                                      wd.curr_cong - 1, wd.hist_cong_cost, nd.wires.at(wd.w).second);
+                    }
+                    if (pip == PipId()) {
+                        break;
+                    }
+                    ROUTE_LOG_DBG("         fwd pip: %s (%d, %d)\n", ctx->nameOfPip(pip), ctx->getPipLocation(pip).x,
+                                  ctx->getPipLocation(pip).y);
+                    cursor_bwd = wire_to_idx.at(ctx->getPipSrcWire(pip));
                 }
-                ROUTE_LOG_DBG("         fwd pip: %s (%d, %d)\n", ctx->nameOfPip(pip), ctx->getPipLocation(pip).x,
-                              ctx->getPipLocation(pip).y);
-                cursor_bwd = wire_to_idx.at(ctx->getPipSrcWire(pip));
-            }
 
-            while (cursor_bwd != src_wire_idx) {
-                // Tack onto existing routing
-                WireId bwd_w = flat_wires.at(cursor_bwd).w;
-                if (!nd.wires.count(bwd_w))
-                    break;
-                auto &bound = nd.wires.at(bwd_w);
-                PipId pip = bound.first;
-                if (ctx->debug && !is_mt) {
-                    auto &wd = flat_wires.at(cursor_bwd);
-                    ROUTE_LOG_DBG("      ext wire: %s (curr %d hist %f share %d)\n", ctx->nameOfWire(wd.w),
-                                  wd.curr_cong - 1, wd.hist_cong_cost, bound.second);
+                while (cursor_bwd != src_wire_idx) {
+                    // Tack onto existing routing
+                    WireId bwd_w = flat_wires.at(cursor_bwd).w;
+                    if (!nd.wires.count(bwd_w))
+                        break;
+                    auto &bound = nd.wires.at(bwd_w);
+                    PipId pip = bound.first;
+                    if (ctx->debug && !is_mt) {
+                        auto &wd = flat_wires.at(cursor_bwd);
+                        ROUTE_LOG_DBG("      ext wire: %s (curr %d hist %f share %d)\n", ctx->nameOfWire(wd.w),
+                                      wd.curr_cong - 1, wd.hist_cong_cost, bound.second);
+                    }
+                    bind_pip_internal(nd, i, cursor_bwd, pip);
+                    if (pip == PipId())
+                        break;
+                    cursor_bwd = wire_to_idx.at(ctx->getPipSrcWire(pip));
                 }
-                bind_pip_internal(nd, i, cursor_bwd, pip);
-                if (pip == PipId())
-                    break;
-                cursor_bwd = wire_to_idx.at(ctx->getPipSrcWire(pip));
-            }
 
-            NPNR_ASSERT(cursor_bwd == src_wire_idx);
+                NPNR_ASSERT(cursor_bwd == src_wire_idx);
+            }
 
             int cursor_fwd = midpoint_wire;
             while (was_visited_bwd(cursor_fwd, std::numeric_limits<float>::max())) {
@@ -1029,7 +1030,7 @@ struct Router2
         auto &usr = net->users.at(usr_idx);
         WireId src = ctx->getNetinfoSourceWire(net);
         // Skip routes with no source
-        if (src == WireId())
+        if (src == WireId() && net->constant_value == IdString())
             return true;
         WireId dst = ctx->getNetinfoSinkWire(net, usr, phys_pin);
         if (dst == WireId())
@@ -1086,6 +1087,10 @@ struct Router2
                 break;
             }
             cursor = ctx->getPipSrcWire(p);
+            if (net->constant_value != IdString() && ctx->getWireConstantValue(cursor) == net->constant_value) {
+                src = cursor;
+                break;
+            }
         }
 
         if (success) {
@@ -1343,6 +1348,8 @@ struct Router2
     delay_t get_route_delay(int net, store_index<PortRef> usr_idx, int phys_idx)
     {
         auto &nd = nets.at(net);
+        if (nets_by_udata.at(net)->constant_value != IdString())
+            return 0;
         auto &ad = nd.arcs.at(usr_idx.idx()).at(phys_idx);
         WireId cursor = ad.sink_wire;
         if (cursor == WireId() || nd.src_wire == WireId())
diff --git a/docs/archapi.md b/docs/archapi.md
index cde69a150c..043f937b34 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -340,6 +340,14 @@ chip. There may be significant performance impacts if routing regularly
 exceeds these bounds by more than a small margin; so an over-estimate
 of the bounds is almost always better than an under-estimate.
 
+### IdString getWireConstantValue() const
+
+If not an empty string, indicate this wire can be used to source nets
+with their `constant_value` equal to its return value.
+
+*BaseArch default: returns `IdString()`*
+
+
 Pip Methods
 -----------
 
diff --git a/nexus/arch.h b/nexus/arch.h
index 2cb8c08ee3..5d08c66191 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1170,6 +1170,13 @@ struct Arch : BaseArch<ArchRanges>
     virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
     NetInfo *getBoundWireNet(WireId wire) const override { return tileStatus.at(wire.tile).boundwires.at(wire.index); }
 
+    IdString getWireConstantValue(WireId wire) const override
+    {
+        if (chip_wire_data(db, chip_info, wire).name == ID_LOCAL_VCC)
+            return id_VCC_DRV;
+        else
+            return {};
+    }
     // -------------------------------------------------
 
     PipId getPipByName(IdStringList name) const override;
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 53f16033e7..d5c7147e67 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -325,6 +325,8 @@ struct NexusPacker
         CellInfo *new_cell = ctx->createCell(ctx->idf("$CONST_%s_DRV_", type.c_str(ctx)), type);
         new_cell->addOutput(id_Z);
         new_cell->connectPort(id_Z, new_net);
+        if (type == id_VCC_DRV)
+            new_net->constant_value = id_VCC_DRV;
         return new_net;
     }
 

From cf647463e4f11ef972a54cdacd97471cf755c9a7 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 28 Oct 2023 17:09:37 +0200
Subject: [PATCH 510/712] himbaechel: Add support for new constants API

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/arch.cc                           |  2 +-
 himbaechel/arch.h                            |  4 ++++
 himbaechel/chipdb.h                          |  1 +
 himbaechel/himbaechel_dbgen/chip.py          | 12 ++++++------
 himbaechel/himbaechel_helpers.cc             |  6 +++++-
 himbaechel/himbaechel_helpers.h              |  3 ++-
 himbaechel/uarch/example/blinky.v            |  2 +-
 himbaechel/uarch/example/constids.inc        |  5 +++++
 himbaechel/uarch/example/example.cc          |  2 +-
 himbaechel/uarch/example/example_arch_gen.py | 16 ++++++++++++++++
 10 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 3c0e2bcaa7..1270934e02 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -32,7 +32,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static constexpr int database_version = 2;
+static constexpr int database_version = 3;
 
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 55d709cabb..8485908677 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -488,6 +488,10 @@ struct Arch : BaseArch<ArchRanges>
     IdString getWireType(WireId wire) const override { return IdString(chip_wire_info(chip_info, wire).wire_type); }
     DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); } // TODO
     BelPinRange getWireBelPins(WireId wire) const override { return BelPinRange(chip_info, get_tile_wire_range(wire)); }
+    IdString getWireConstantValue(WireId wire) const override
+    {
+        return IdString(chip_wire_info(chip_info, wire).const_value);
+    }
     WireRange getWires() const override { return WireRange(chip_info); }
     bool checkWireAvail(WireId wire) const override
     {
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 0e6d197251..2ac7f60b42 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -62,6 +62,7 @@ NPNR_PACKED_STRUCT(struct BelPinRefPOD {
 NPNR_PACKED_STRUCT(struct TileWireDataPOD {
     int32_t name;
     int32_t wire_type;
+    int32_t const_value;
     int32_t flags;      // 32 bits of arbitrary data
     int32_t timing_idx; // used only when the wire is not part of a node, otherwise node idx applies
     RelSlice<int32_t> pips_uphill;
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index f7e2af3cdb..e3708107a7 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -144,12 +144,10 @@ class TileWireData:
     index: int
     name: IdString
     wire_type: IdString
+    const_value: IdString = field(default_factory=list)
     flags: int = 0
     timing_idx: int = -1
 
-    # not serialised, but used to build the global constant networks
-    const_val: int = -1
-
     # these crossreferences will be updated by finalise(), no need to manually update
     pips_uphill: list[int] = field(default_factory=list)
     pips_downhill: list[int] = field(default_factory=list)
@@ -168,6 +166,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
         bba.u32(self.wire_type.index)
+        bba.u32(self.const_value.index)
         bba.u32(self.flags)
         bba.u32(self.timing_idx)
         bba.slice(f"{context}_pips_uh", len(self.pips_uphill))
@@ -228,11 +227,12 @@ def add_bel_pin(self, bel: BelData, pin: str, wire: str, dir: PinType):
         bel.pins.append(BelPin(pin_id, wire_idx, dir))
         self.wires[wire_idx].bel_pins.append(BelPinRef(bel.index, pin_id))
 
-    def create_wire(self, name: str, type: str=""):
+    def create_wire(self, name: str, type: str="", const_value: str=""):
         # Create a new tile wire of a given name and type (optional) in the tile type
         wire = TileWireData(index=len(self.wires),
             name=self.strs.id(name),
-            wire_type=self.strs.id(type))
+            wire_type=self.strs.id(type),
+            const_value=self.strs.id(const_value))
         self._wire2idx[wire.name] = wire.index
         self.wires.append(wire)
         return wire
@@ -811,7 +811,7 @@ def serialise(self, bba: BBAWriter):
 
         bba.label("chip_info")
         bba.u32(0x00ca7ca7) # magic
-        bba.u32(2) # version
+        bba.u32(3) # version
         bba.u32(self.width)
         bba.u32(self.height)
 
diff --git a/himbaechel/himbaechel_helpers.cc b/himbaechel/himbaechel_helpers.cc
index 4ce478bf86..773f7b76d7 100644
--- a/himbaechel/himbaechel_helpers.cc
+++ b/himbaechel/himbaechel_helpers.cc
@@ -98,7 +98,8 @@ int HimbaechelHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports,
 
 void HimbaechelHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
                                           const dict<IdString, Property> &vcc_params,
-                                          const dict<IdString, Property> &gnd_params)
+                                          const dict<IdString, Property> &gnd_params, IdString vcc_const_val,
+                                          IdString gnd_const_val)
 {
     CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), vcc_driver.cell_type);
     vcc_drv->addOutput(vcc_driver.port);
@@ -113,6 +114,9 @@ void HimbaechelHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort
     NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC"));
     NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND"));
 
+    vcc_net->constant_value = vcc_const_val;
+    gnd_net->constant_value = gnd_const_val;
+
     vcc_drv->connectPort(vcc_driver.port, vcc_net);
     gnd_drv->connectPort(gnd_driver.port, gnd_net);
 
diff --git a/himbaechel/himbaechel_helpers.h b/himbaechel/himbaechel_helpers.h
index b2a41b656c..369f41dcf4 100644
--- a/himbaechel/himbaechel_helpers.h
+++ b/himbaechel/himbaechel_helpers.h
@@ -67,7 +67,8 @@ struct HimbaechelHelpers
     // Replace constants with given driving cells
     void replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
                            const dict<IdString, Property> &vcc_params = {},
-                           const dict<IdString, Property> &gnd_params = {});
+                           const dict<IdString, Property> &gnd_params = {}, IdString vcc_const_val = IdString(),
+                           IdString gnd_const_val = IdString());
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/example/blinky.v b/himbaechel/uarch/example/blinky.v
index e26c2fae56..128a63d9c7 100644
--- a/himbaechel/uarch/example/blinky.v
+++ b/himbaechel/uarch/example/blinky.v
@@ -11,6 +11,6 @@ always @(posedge clk)
 	else
 		ctr <= ctr + 1'b1;
 
-assign leds = ctr;
+assign leds = {4'b1010, ctr[7:4]};
 
 endmodule
diff --git a/himbaechel/uarch/example/constids.inc b/himbaechel/uarch/example/constids.inc
index b40d5be8a0..900577e46c 100644
--- a/himbaechel/uarch/example/constids.inc
+++ b/himbaechel/uarch/example/constids.inc
@@ -12,3 +12,8 @@ X(O)
 X(IOB)
 X(PAD)
 X(INIT)
+
+X(GND)
+X(GND_DRV)
+X(VCC)
+X(VCC_DRV)
\ No newline at end of file
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index c02280cdee..4e8dff4a56 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -63,7 +63,7 @@ struct ExampleImpl : HimbaechelAPI
         // Replace constants with LUTs
         const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
         const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
-        h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+        h.replace_constants(CellTypePort(id_VCC_DRV, id_VCC), CellTypePort(id_GND_DRV, id_GND), {}, {}, id_VCC, id_GND);
         // Constrain directly connected LUTs and FFs together to use dedicated resources
         int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
         log_info("Constrained %d LUTFF pairs.\n", lutffs);
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
index 81d5c7dc35..d4d0496bc5 100644
--- a/himbaechel/uarch/example/example_arch_gen.py
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -30,6 +30,9 @@
 
 def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
     # FIXME: terrible routing matrix, just for a toy example...
+    # constant wires
+    tt.create_wire("GND", "GND", const_value="GND")
+    tt.create_wire("VCC", "VCC", const_value="VCC")
     # switch wires
     for i in range(Wl):
         tt.create_wire(f"SWITCH{i}", "SWITCH")
@@ -45,6 +48,10 @@ def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
     for i, w in enumerate(outputs):
         for j in range((i % Sq), Wl, Sq):
             tt.create_pip(w, f"SWITCH{j}", timing_class="SWINPUT")
+    # constant pips
+    for i in range(Wl):
+        tt.create_pip("GND", f"SWITCH{i}")
+        tt.create_pip("VCC", f"SWITCH{i}")
     # neighbour local pips
     for i in range(Wl):
         for j, (d, dx, dy) in enumerate(dirs):
@@ -147,6 +154,15 @@ def create_corner_tiletype(ch):
     tt.create_wire(f"CLK", "TILE_CLK")
     tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
     tt.create_pip(f"CLK_PREV", f"CLK")
+
+    tt.create_wire(f"GND", "GND", const_value="GND")
+    tt.create_wire(f"VCC", "VCC", const_value="VCC")
+
+    gnd = tt.create_bel(f"GND_DRV", f"GND_DRV", z=0)
+    tt.add_bel_pin(gnd, "GND", "GND", PinType.OUTPUT)
+    vcc = tt.create_bel(f"VCC_DRV", f"VCC_DRV", z=1)
+    tt.add_bel_pin(vcc, "VCC", "VCC", PinType.OUTPUT)
+
     return tt
 
 def is_corner(x, y):

From 7b0e082000f563af3627da6f6c5f693159d965c2 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 7 Nov 2023 09:02:35 +0100
Subject: [PATCH 511/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 4db44f3f43..ef60e47bcb 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -293,7 +293,9 @@ class StaticPlacer
     {
         if (ci->udata == -1) {
             // not handled?
-            NPNR_ASSERT_MSG(ci->bel != BelId(), stringf("Cell %s of type %s has no bel", ci->name.c_str(ctx), ci->type.c_str(ctx)).c_str()); // already fixed
+            NPNR_ASSERT_MSG(ci->bel != BelId(),
+                            stringf("Cell %s of type %s has no bel", ci->name.c_str(ctx), ci->type.c_str(ctx))
+                                    .c_str()); // already fixed
             return RealPair(ctx->getBelLocation(ci->bel), 0.5f);
         } else {
             return ref ? mcells.at(ci->udata).ref_pos : mcells.at(ci->udata).pos;
@@ -763,11 +765,12 @@ class StaticPlacer
                     res2.first->second += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
             }
             dens_penalty = std::vector<float>(wirelen_sum.size(), 0.0);
-            for (auto& item : wirelen_sum) {
+            for (auto &item : wirelen_sum) {
                 auto group = item.first;
                 auto wirelen = item.second;
                 dens_penalty[group] = wirelen / force_sum.at(group);
-                log_info(" initial density penalty for %s: %f\n", cfg.cell_groups.at(group).name.c_str(ctx), dens_penalty[group]);
+                log_info(" initial density penalty for %s: %f\n", cfg.cell_groups.at(group).name.c_str(ctx),
+                         dens_penalty[group]);
             }
         }
         // Third loop: compute total gradient, and precondition
@@ -784,7 +787,8 @@ class StaticPlacer
 
             float precond = std::max(1.0f, float(cell.pin_count) + dens_penalty[cell.group] * cell.rect.area());
             if (ref) {
-                cell.ref_total_grad = ((cell.ref_wl_grad * -1) - cell.ref_dens_grad * dens_penalty[cell.group]) / precond;
+                cell.ref_total_grad =
+                        ((cell.ref_wl_grad * -1) - cell.ref_dens_grad * dens_penalty[cell.group]) / precond;
             } else {
                 cell.total_grad = ((cell.wl_grad * -1) - cell.dens_grad * dens_penalty[cell.group]) / precond;
             }
@@ -1261,7 +1265,7 @@ class StaticPlacer
         bool legalised_ip = false;
         while (true) {
             step();
-            for (auto& penalty : dens_penalty)
+            for (auto &penalty : dens_penalty)
                 penalty *= 1.025;
             if (!legalised_ip) {
                 float ip_overlap = 0;

From 4c6003ac0b60a25811d764a6c70e6ef5f7af28f9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 7 Nov 2023 15:25:42 +0100
Subject: [PATCH 512/712] router2: Don't use estimates for constant nets

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/route/router2.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/route/router2.cc b/common/route/router2.cc
index 49fe327a06..d592dcb8da 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -782,7 +782,7 @@ struct Router2
                         next_score.delay = curr.score.delay + cfg.get_base_cost(ctx, next, uh, crit_weight);
                         next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
                         next_score.togo_cost =
-                                cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
+                                const_mode ? 0 : cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
                         if (was_visited_bwd(next_idx, next_score.delay)) {
                             // Don't expand the same node twice.
                             continue;

From 506d5f9422f57642a78008b71fd0c0434154d648 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 9 Nov 2023 01:29:50 +0000
Subject: [PATCH 513/712] machxo2: less pessimistic delay prediction

---
 machxo2/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index f31de2a768..2a71c774af 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -476,7 +476,7 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
     int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
 
-    return (500 - 22 * device_speed) *
+    return (250 - 22 * device_speed) *
            (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 

From 0106c3d2999ecf97f2c94db36c6ea8c508d6c20a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 13 Nov 2023 10:44:53 +1000
Subject: [PATCH 514/712] gowin: Himbaechel. Diff io BUGFIX.

Fixed incorrect use of attributes instead of parameters.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 55cc24422f..83975af29a 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -381,7 +381,7 @@ struct GowinPacker
         }
         // mark IOB as used by IOLOGIC
         out_iob->setParam(id_IOLOGIC_IOB, 1);
-        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->attrs.count(id_DIFF_TYPE));
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->params.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -438,7 +438,7 @@ struct GowinPacker
         }
         // mark IOB as used by IOLOGIC
         out_iob->setParam(id_IOLOGIC_IOB, 1);
-        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->attrs.count(id_DIFF_TYPE));
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), out_iob->params.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -483,7 +483,7 @@ struct GowinPacker
         return ctx->getBelByLocation(gwu.get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
     }
 
-    bool is_diff_io(BelId bel) { return ctx->getBoundBelCell(bel)->attrs.count(id_DIFF_TYPE) != 0; }
+    bool is_diff_io(BelId bel) { return ctx->getBoundBelCell(bel)->params.count(id_DIFF_TYPE) != 0; }
 
     CellInfo *create_aux_iologic_cell(CellInfo &ci, IdString mode, bool io16 = false, int idx = 0)
     {
@@ -558,7 +558,7 @@ struct GowinPacker
         }
         // mark IOB as used by IOLOGIC
         in_iob->setParam(id_IOLOGIC_IOB, 1);
-        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), in_iob->attrs.count(id_DIFF_TYPE));
+        check_iologic_placement(ci, ctx->getBelLocation(iob_bel), in_iob->params.count(id_DIFF_TYPE));
 
         if (!ctx->checkBelAvail(l_bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
@@ -669,7 +669,7 @@ struct GowinPacker
         if (aux_offset.x == 0 && aux_offset.y == 0) {
             log_error("OSER16 %s can not be placed at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
-        check_io16_placement(ci, iob_loc, aux_offset, out_iob->attrs.count(id_DIFF_TYPE));
+        check_io16_placement(ci, iob_loc, aux_offset, out_iob->params.count(id_DIFF_TYPE));
 
         BelId main_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::OSER16_Z));
         ctx->bindBel(main_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
@@ -743,7 +743,7 @@ struct GowinPacker
         if (aux_offset.x == 0 && aux_offset.y == 0) {
             log_error("IDES16 %s can not be placed at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
-        check_io16_placement(ci, iob_loc, aux_offset, in_iob->attrs.count(id_DIFF_TYPE));
+        check_io16_placement(ci, iob_loc, aux_offset, in_iob->params.count(id_DIFF_TYPE));
 
         BelId main_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IDES16_Z));
         ctx->bindBel(main_bel, &ci, PlaceStrength::STRENGTH_LOCKED);

From a4d2244300ac0cc0293968aabd56d477beb3ebd7 Mon Sep 17 00:00:00 2001
From: uis <uis9936@gmail.com>
Date: Sat, 11 Nov 2023 17:37:20 +0300
Subject: [PATCH 515/712] Fix printf formats

---
 gowin/pack.cc                     | 3 ++-
 himbaechel/uarch/gowin/globals.cc | 2 +-
 himbaechel/uarch/gowin/pack.cc    | 4 +++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/gowin/pack.cc b/gowin/pack.cc
index 00b5fee253..d89992cc42 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -21,6 +21,7 @@
 #include <algorithm>
 #include <iostream>
 #include <iterator>
+#include <cinttypes>
 #include "cells.h"
 #include "design_utils.h"
 #include "log.h"
@@ -672,7 +673,7 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 uc_init &= (1LL << uc_init_len) - 1;
 
                 if (ctx->verbose)
-                    log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
+                    log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc), it_param->second.intval,
                              uc_init);
 
                 it_param->second = Property(uc_init, uc_init_len);
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index a34d4253f6..c818f762a3 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -246,7 +246,7 @@ struct GowinGlobalRouter
             IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
             for (size_t i = 0; i < pin_func.size(); ++i) {
                 if (ctx->debug) {
-                    log_info("bel:%s, pin func: %lu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
+                    log_info("bel:%s, pin func: %zu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
                              pin_func[i].str(ctx).c_str());
                 }
                 if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 83975af29a..621c7fff8f 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -10,6 +10,8 @@
 #include "gowin_utils.h"
 #include "pack.h"
 
+#include <cinttypes>
+
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
@@ -881,7 +883,7 @@ struct GowinPacker
                     uc_init &= (1LL << uc_init_len) - 1;
 
                     if (ctx->verbose && it_param->second.intval != uc_init)
-                        log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc),
+                        log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc),
                                  it_param->second.intval, uc_init);
 
                     it_param->second = Property(uc_init, uc_init_len);

From a32ad13a86a24013c1570f020de71bbb4df89180 Mon Sep 17 00:00:00 2001
From: laanwj <126646+laanwj@users.noreply.github.com>
Date: Tue, 14 Nov 2023 11:06:25 +0100
Subject: [PATCH 516/712] ecp5: Don't segfault while packing FFs when DI port
 of TRELLIS_FF unconnected

Currently a segfault happens when the DI port is not specified. Leaving
it unconnected is probably incorrect, but it shouldn't crash the placer.
Fix by adding a check.
---
 ecp5/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index df1398601b..69d7ccf8df 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -240,7 +240,7 @@ class Ecp5Packer
                     ci->disconnectPort(id_M);
                     ci->ports.erase(id_M);
                 }
-                if (di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
+                if (di && di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
                     CellInfo *comb = di->driver.cell;
                     if (comb->cluster != ClusterId()) {
                         // Special procedure where the comb cell is part of an existing macro

From 5bfe0dd1b137e43d8ed85485552e126a6b7ee978 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 16 Oct 2023 14:06:41 +0200
Subject: [PATCH 517/712] himbaechel: Adding a xilinx uarch for xc7 with
 prjxray

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .gitmodules                                   |    3 +
 himbaechel/arch.cc                            |    2 +-
 himbaechel/arch.h                             |    9 +
 himbaechel/family.cmake                       |    2 +-
 himbaechel/himbaechel_dbgen/chip.py           |   13 +-
 himbaechel/uarch/xilinx/CMakeLists.txt        |   37 +
 himbaechel/uarch/xilinx/cells.cc              |  197 ++
 himbaechel/uarch/xilinx/constids.inc          |  740 ++++++++
 himbaechel/uarch/xilinx/examples/.gitignore   |    6 +
 .../uarch/xilinx/examples/arty-a35/arty.xdc   |   52 +
 .../uarch/xilinx/examples/arty-a35/blinky.sh  |    5 +
 .../uarch/xilinx/examples/arty-a35/blinky.v   |   21 +
 .../uarch/xilinx/examples/bitgen_xray.sh      |   34 +
 himbaechel/uarch/xilinx/extra_data.h          |  107 ++
 himbaechel/uarch/xilinx/fasm.cc               | 1664 +++++++++++++++++
 himbaechel/uarch/xilinx/gen/filters.py        |  106 ++
 himbaechel/uarch/xilinx/gen/parse_sdf.py      |  134 ++
 himbaechel/uarch/xilinx/gen/tileconn.py       |   38 +
 himbaechel/uarch/xilinx/gen/xilinx_device.py  |  544 ++++++
 himbaechel/uarch/xilinx/gen/xilinx_gen.py     |  371 ++++
 himbaechel/uarch/xilinx/meta                  |    1 +
 himbaechel/uarch/xilinx/pack.cc               |  750 ++++++++
 himbaechel/uarch/xilinx/pack.h                |  218 +++
 himbaechel/uarch/xilinx/pack_carry.cc         |  405 ++++
 himbaechel/uarch/xilinx/pack_clocking.cc      |  350 ++++
 himbaechel/uarch/xilinx/pack_dram.cc          |  477 +++++
 himbaechel/uarch/xilinx/pack_io.cc            |  497 +++++
 himbaechel/uarch/xilinx/pins.cc               |  480 +++++
 himbaechel/uarch/xilinx/pins.h                |   34 +
 himbaechel/uarch/xilinx/xdc.cc                |  200 ++
 himbaechel/uarch/xilinx/xilinx.cc             |  557 ++++++
 himbaechel/uarch/xilinx/xilinx.h              |  180 ++
 himbaechel/uarch/xilinx/xilinx_place.cc       |  640 +++++++
 33 files changed, 8868 insertions(+), 6 deletions(-)
 create mode 100644 himbaechel/uarch/xilinx/CMakeLists.txt
 create mode 100644 himbaechel/uarch/xilinx/cells.cc
 create mode 100644 himbaechel/uarch/xilinx/constids.inc
 create mode 100644 himbaechel/uarch/xilinx/examples/.gitignore
 create mode 100644 himbaechel/uarch/xilinx/examples/arty-a35/arty.xdc
 create mode 100755 himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
 create mode 100644 himbaechel/uarch/xilinx/examples/arty-a35/blinky.v
 create mode 100755 himbaechel/uarch/xilinx/examples/bitgen_xray.sh
 create mode 100644 himbaechel/uarch/xilinx/extra_data.h
 create mode 100644 himbaechel/uarch/xilinx/fasm.cc
 create mode 100644 himbaechel/uarch/xilinx/gen/filters.py
 create mode 100644 himbaechel/uarch/xilinx/gen/parse_sdf.py
 create mode 100644 himbaechel/uarch/xilinx/gen/tileconn.py
 create mode 100644 himbaechel/uarch/xilinx/gen/xilinx_device.py
 create mode 100644 himbaechel/uarch/xilinx/gen/xilinx_gen.py
 create mode 160000 himbaechel/uarch/xilinx/meta
 create mode 100644 himbaechel/uarch/xilinx/pack.cc
 create mode 100644 himbaechel/uarch/xilinx/pack.h
 create mode 100644 himbaechel/uarch/xilinx/pack_carry.cc
 create mode 100644 himbaechel/uarch/xilinx/pack_clocking.cc
 create mode 100644 himbaechel/uarch/xilinx/pack_dram.cc
 create mode 100644 himbaechel/uarch/xilinx/pack_io.cc
 create mode 100644 himbaechel/uarch/xilinx/pins.cc
 create mode 100644 himbaechel/uarch/xilinx/pins.h
 create mode 100644 himbaechel/uarch/xilinx/xdc.cc
 create mode 100644 himbaechel/uarch/xilinx/xilinx.cc
 create mode 100644 himbaechel/uarch/xilinx/xilinx.h
 create mode 100644 himbaechel/uarch/xilinx/xilinx_place.cc

diff --git a/.gitmodules b/.gitmodules
index a22fbc419e..fde861f7ff 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
 [submodule "fpga-interchange-schema"]
 	path = 3rdparty/fpga-interchange-schema
 	url = https://github.com/SymbiFlow/fpga-interchange-schema.git
+[submodule "himbaechel/uarch/xilinx/meta"]
+	path = himbaechel/uarch/xilinx/meta
+	url = https://github.com/gatecat/nextpnr-xilinx-meta
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 1270934e02..44b79b620a 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -318,7 +318,7 @@ const std::string Arch::defaultPlacer = "heap";
 
 const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
-const std::string Arch::defaultRouter = "router1";
+const std::string Arch::defaultRouter = "router2";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
 void Arch::set_fast_pip_delays(bool fast_mode)
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 8485908677..5590ef9929 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -546,6 +546,15 @@ struct Arch : BaseArch<ArchRanges>
             // Scale delay (fF * mOhm -> ps)
             delay_t total_delay = (input_res * input_cap) / uint64_t(1e6);
             total_delay += pip_tmg->int_delay.slow_max;
+
+            WireId dst = getPipDstWire(pip);
+            auto dst_tmg = get_node_timing(dst);
+            if (dst_tmg != nullptr) {
+                total_delay +=
+                        ((pip_tmg->out_res.slow_max + uint64_t(dst_tmg->res.slow_max) / 2) * dst_tmg->cap.slow_max) /
+                        uint64_t(1e6);
+            }
+
             return DelayQuad(total_delay);
         } else {
             // Pip with no specified delay. Return a notional value so the router still has something to work with.
diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake
index cf4477e351..88a52b339a 100644
--- a/himbaechel/family.cmake
+++ b/himbaechel/family.cmake
@@ -1,4 +1,4 @@
-set(HIMBAECHEL_UARCHES "example;gowin")
+set(HIMBAECHEL_UARCHES "example;gowin;xilinx")
 foreach(uarch ${HIMBAECHEL_UARCHES})
 	add_subdirectory(${family}/uarch/${uarch})
     aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES)
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index e3708107a7..26741a3162 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -301,6 +301,7 @@ class NodeShape(BBAStruct):
     def key(self):
         m = hashlib.md5()
         m.update(struct.pack("h"*len(self.wires), *self.wires))
+        m.update(struct.pack("i", self.timing_index))
         return m.digest()
 
     def serialise_lists(self, context: str, bba: BBAWriter):
@@ -644,7 +645,11 @@ def set_pip_class(self, grade: str, name: str, delay: TimingValue,
         if idx >= len(sg.pip_classes):
             sg.pip_classes += [None for i in range(1 + idx - len(sg.pip_classes))]
         assert sg.pip_classes[idx] is None, f"attempting to set pip class {name} in speed grade {grade} twice"
-        sg.pip_classes[idx] = PipTiming(int_delay=delay, in_cap=in_cap, out_res=out_res, flags=(1 if is_buffered else 0))
+        sg.pip_classes[idx] = PipTiming(int_delay=delay,
+            in_cap=in_cap or TimingValue(),
+            out_res=out_res or TimingValue(),
+            flags=(1 if is_buffered else 0)
+        )
 
     def set_bel_pin_class(self, grade: str, name: str, delay: TimingValue,
             in_cap: Optional[TimingValue]=None, out_res: Optional[TimingValue]=None):
@@ -658,7 +663,7 @@ def set_node_class(self, grade: str, name: str,  delay: TimingValue,
         if idx >= len(sg.node_classes):
             sg.node_classes += [None for i in range(1 + idx - len(sg.node_classes))]
         assert sg.node_classes[idx] is None, f"attempting to set node class {name} in speed grade {grade} twice"
-        sg.node_classes[idx] = NodeTiming(delay=delay, res=res, cap=cap)
+        sg.node_classes[idx] = NodeTiming(delay=delay, res=res or TimingValue(), cap=cap or TimingValue())
 
     def add_cell_variant(self, speed_grade: str, name: str):
         cell = CellTiming(self.strs, name)
@@ -700,13 +705,13 @@ def tile_type_at(self, x: int, y: int):
     def set_speed_grades(self, speed_grades: list):
         self.timing.set_speed_grades(speed_grades)
         return self.timing
-    def add_node(self, wires: list[NodeWire]):
+    def add_node(self, wires: list[NodeWire], timing_class=""):
         # add a node - joining between multiple tile wires into a single connection (from nextpnr's point of view)
         # all the tile wires must exist, and the tile types must be set, first
         x0 = wires[0].x
         y0 = wires[0].y
         # compute node shape
-        shape = NodeShape()
+        shape = NodeShape(timing_index=self.timing.node_class_idx(timing_class))
         for w in wires:
             if isinstance(w.wire, int):
                 wire_index = w.wire
diff --git a/himbaechel/uarch/xilinx/CMakeLists.txt b/himbaechel/uarch/xilinx/CMakeLists.txt
new file mode 100644
index 0000000000..62d68f0513
--- /dev/null
+++ b/himbaechel/uarch/xilinx/CMakeLists.txt
@@ -0,0 +1,37 @@
+message(STATUS "Configuring Xilinx uarch")
+cmake_minimum_required(VERSION 3.5)
+project(himbaechel-xilinx-chipdb NONE)
+
+set(HIMBAECHEL_XILINX_DEVICES "" CACHE STRING
+    "Include support for these Xilinx devices via himbaechel")
+set(HIMBAECHEL_PRJXRAY_DB "" CACHE STRING
+    "Path to a project x-ray database")
+message(STATUS "Enabled Himbaechel-Xilinx devices: ${HIMBAECHEL_XILINX_DEVICES}")
+
+
+set(chipdb_binaries)
+file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/xilinx)
+foreach(device ${HIMBAECHEL_XILINX_DEVICES})
+	if("${HIMBAECHEL_PRJXRAY_DB}" STREQUAL "")
+		message(SEND_ERROR "HIMBAECHEL_PRJXRAY_DB must be set to a prjxray database checkout")
+	endif()
+
+	set(device_bba ${CMAKE_BINARY_DIR}/share/himbaechel/xilinx/chipdb-${device}.bba)
+	set(device_bin ${CMAKE_BINARY_DIR}/share/himbaechel/xilinx/chipdb-${device}.bin)
+	add_custom_command(
+		OUTPUT ${device_bin}
+		COMMAND pypy3 ${CMAKE_CURRENT_SOURCE_DIR}/gen/xilinx_gen.py --xray ${HIMBAECHEL_PRJXRAY_DB}/artix7 --device ${device} --bba ${device_bba}
+		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}.new
+        # atomically update
+        COMMAND ${CMAKE_COMMAND} -E rename ${device_bin}.new ${device_bin}
+		DEPENDS
+			bbasm
+			${CMAKE_CURRENT_SOURCE_DIR}/gen/xilinx_gen.py
+			${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+		VERBATIM)
+	list(APPEND chipdb_binaries ${device_bin})
+endforeach()
+
+add_custom_target(chipdb-himbaechel-xilinx ALL DEPENDS ${chipdb_binaries})
+install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/xilinx/ DESTINATION share/nextpnr/himbaechel/xilinx
+	    PATTERN "*.bba" EXCLUDE)
diff --git a/himbaechel/uarch/xilinx/cells.cc b/himbaechel/uarch/xilinx/cells.cc
new file mode 100644
index 0000000000..218d1f4877
--- /dev/null
+++ b/himbaechel/uarch/xilinx/cells.cc
@@ -0,0 +1,197 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+#include "pack.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+CellInfo *XilinxPacker::create_cell(IdString type, IdString name)
+{
+    CellInfo *cell = ctx->createCell(name, type);
+
+    auto add_port = [&](const std::string &name, PortType dir) {
+        IdString id = ctx->id(name);
+        cell->ports[id].name = id;
+        cell->ports[id].type = dir;
+    };
+    if (type == id_SLICE_LUTX) {
+        for (int i = 1; i <= 6; i++)
+            add_port("A" + std::to_string(i), PORT_IN);
+        for (int i = 1; i <= 9; i++)
+            add_port("WA" + std::to_string(i), PORT_IN);
+        add_port("DI1", PORT_IN);
+        add_port("DI2", PORT_IN);
+        add_port("CLK", PORT_IN);
+        add_port("WE", PORT_IN);
+        add_port("SIN", PORT_IN);
+        add_port("O5", PORT_OUT);
+        add_port("O6", PORT_OUT);
+        add_port("MC31", PORT_OUT);
+    } else if (type == id_SLICE_FFX) {
+        add_port("D", PORT_IN);
+        add_port("SR", PORT_IN);
+        add_port("CE", PORT_IN);
+        add_port("CLK", PORT_IN);
+        add_port("Q", PORT_OUT);
+    } else if (type == id_RAMD64E) {
+        for (int i = 0; i < 6; i++)
+            add_port("RADR" + std::to_string(i), PORT_IN);
+        for (int i = 0; i < 8; i++)
+            add_port("WADR" + std::to_string(i), PORT_IN);
+        add_port("CLK", PORT_IN);
+        add_port("I", PORT_IN);
+        add_port("WE", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_RAMD32) {
+        for (int i = 0; i < 5; i++)
+            add_port("RADR" + std::to_string(i), PORT_IN);
+        for (int i = 0; i < 5; i++)
+            add_port("WADR" + std::to_string(i), PORT_IN);
+        add_port("CLK", PORT_IN);
+        add_port("I", PORT_IN);
+        add_port("WE", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type.in(id_MUXF7, id_MUXF8, id_MUXF9)) {
+        add_port("I0", PORT_IN);
+        add_port("I1", PORT_IN);
+        add_port("S", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_CARRY8) {
+        add_port("CI", PORT_IN);
+        add_port("CI_TOP", PORT_IN);
+
+        for (int i = 0; i < 8; i++) {
+            add_port("DI[" + std::to_string(i) + "]", PORT_IN);
+            add_port("S[" + std::to_string(i) + "]", PORT_IN);
+            add_port("CO[" + std::to_string(i) + "]", PORT_OUT);
+            add_port("O[" + std::to_string(i) + "]", PORT_OUT);
+        }
+    } else if (type == id_MUXCY) {
+        add_port("CI", PORT_IN);
+        add_port("DI", PORT_IN);
+        add_port("S", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_XORCY) {
+        add_port("CI", PORT_IN);
+        add_port("LI", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_PAD) {
+        add_port("PAD", PORT_INOUT);
+    } else if (type == id_INBUF) {
+        add_port("VREF", PORT_IN);
+        add_port("PAD", PORT_IN);
+        add_port("OSC_EN", PORT_IN);
+        for (int i = 0; i < 4; i++)
+            add_port("OSC[" + std::to_string(i) + "]", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IBUFCTRL) {
+        add_port("I", PORT_IN);
+        add_port("IBUFDISABLE", PORT_IN);
+        add_port("T", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type.in(id_OBUF, id_IBUF)) {
+        add_port("I", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_OBUFT) {
+        add_port("I", PORT_IN);
+        add_port("T", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IOBUF) {
+        add_port("I", PORT_IN);
+        add_port("T", PORT_IN);
+        add_port("O", PORT_OUT);
+        add_port("IO", PORT_INOUT);
+    } else if (type == id_OBUFT_DCIEN) {
+        add_port("I", PORT_IN);
+        add_port("T", PORT_IN);
+        add_port("DCITERMDISABLE", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_DIFFINBUF) {
+        add_port("DIFF_IN_P", PORT_IN);
+        add_port("DIFF_IN_N", PORT_IN);
+        add_port("OSC_EN[0]", PORT_IN);
+        add_port("OSC_EN[1]", PORT_IN);
+        for (int i = 0; i < 4; i++)
+            add_port("OSC[" + std::to_string(i) + "]", PORT_IN);
+        add_port("VREF", PORT_IN);
+        add_port("O", PORT_OUT);
+        add_port("O_B", PORT_OUT);
+    } else if (type == id_HPIO_VREF) {
+        for (int i = 0; i < 7; i++)
+            add_port("FABRIC_VREF_TUNE[" + std::to_string(i) + "]", PORT_IN);
+        add_port("VREF", PORT_OUT);
+    } else if (type == id_INV) {
+        add_port("I", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IDELAYCTRL) {
+        add_port("REFCLK", PORT_IN);
+        add_port("RST", PORT_IN);
+        add_port("RDY", PORT_OUT);
+    } else if (type == id_IBUF) {
+        add_port("I", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IBUF_INTERMDISABLE) {
+        add_port("I", PORT_IN);
+        add_port("IBUFDISABLE", PORT_IN);
+        add_port("INTERMDISABLE", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IBUFDS) {
+        add_port("I", PORT_IN);
+        add_port("IB", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_IBUFDS_INTERMDISABLE_INT) {
+        add_port("I", PORT_IN);
+        add_port("IB", PORT_IN);
+        add_port("IBUFDISABLE", PORT_IN);
+        add_port("INTERMDISABLE", PORT_IN);
+        add_port("O", PORT_OUT);
+    } else if (type == id_CARRY4) {
+        add_port("CI", PORT_IN);
+        add_port("CYINIT", PORT_IN);
+        for (int i = 0; i < 4; i++) {
+            add_port("DI[" + std::to_string(i) + "]", PORT_IN);
+            add_port("S[" + std::to_string(i) + "]", PORT_IN);
+            add_port("CO[" + std::to_string(i) + "]", PORT_OUT);
+            add_port("O[" + std::to_string(i) + "]", PORT_OUT);
+        }
+    }
+    return cell;
+}
+
+CellInfo *XilinxPacker::create_lut(const std::string &name, const std::vector<NetInfo *> &inputs, NetInfo *output,
+                                   const Property &init)
+{
+    CellInfo *cell = ctx->createCell(ctx->id(name), ctx->idf("LUT%d", int(inputs.size())));
+    for (size_t i = 0; i < inputs.size(); i++) {
+        IdString ip = ctx->idf("I%d", int(i));
+        cell->addInput(ip);
+        cell->connectPort(ip, inputs.at(i));
+    }
+    cell->addOutput(id_O);
+    cell->connectPort(id_O, output);
+    cell->params[id_INIT] = init;
+    return cell;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/constids.inc b/himbaechel/uarch/xilinx/constids.inc
new file mode 100644
index 0000000000..d4db03b2da
--- /dev/null
+++ b/himbaechel/uarch/xilinx/constids.inc
@@ -0,0 +1,740 @@
+X(SLICE_LUTX)
+X(SLICE_FFX)
+X(F7MUX)
+X(F8MUX)
+X(F9MUX)
+X(CARRY4)
+X(CARRY8)
+X(CLEL_L)
+X(CLEL_R)
+X(CLEM)
+X(CLEM_R)
+X(CLBLL_L)
+X(CLBLL_R)
+X(CLBLM_L)
+X(CLBLM_R)
+
+X(A1)
+X(A2)
+X(A3)
+X(A4)
+X(A5)
+X(A6)
+X(CLK)
+X(DI1)
+X(DI2)
+X(SIN)
+X(WA1)
+X(WA2)
+X(WA3)
+X(WA4)
+X(WA5)
+X(WA6)
+X(WA7)
+X(WA8)
+X(WA9)
+X(WE)
+X(MC31)
+X(O5)
+X(O6)
+
+X(CE)
+X(CK)
+X(D)
+X(SR)
+X(Q)
+
+X(AX)
+X(BX)
+X(CIN)
+X(CX)
+X(DI0)
+X(DI3)
+X(DI4)
+X(DI5)
+X(DI6)
+X(DI7)
+X(DX)
+X(EX)
+X(FX)
+X(HX)
+X(S0)
+X(S1)
+X(S2)
+X(S3)
+X(S4)
+X(S5)
+X(S6)
+X(S7)
+X(CO0)
+X(CO1)
+X(CO2)
+X(CO3)
+X(CO4)
+X(CO5)
+X(CO6)
+X(CO7)
+X(O0)
+X(O1)
+X(O2)
+X(O3)
+X(O4)
+X(O7)
+
+X(OUT)
+
+X(PSEUDO_GND)
+X(PSEUDO_VCC)
+X(HARD0)
+X(Y)
+
+X(BRAM)
+X(RAMBFIFO36)
+X(RAMBFIFO18)
+
+X(RAMBFIFO18E2_RAMBFIFO18E2)
+X(RAMB18E2_RAMB18E2)
+X(FIFO18E2_FIFO18E2)
+
+X(RAMBFIFO36E2_RAMBFIFO36E2)
+X(RAMB36E2_RAMB36E2)
+X(FIFO36E2_FIFO36E2)
+
+X(BRAM_L)
+X(BRAM_R)
+
+X(RAMB18E1_RAMB18E1)
+X(FIFO18E1_FIFO18E1)
+
+X(RAMBFIFO36E1_RAMBFIFO36E1)
+X(RAMB36E1_RAMB36E1)
+X(FIFO36E1_FIFO36E1)
+
+X(URAM288)
+X(BEL_URAM288)
+X(URAM_URAM_FT)
+X(URAM_URAM_DELAY_FT)
+
+X(DSP)
+X(DSP48E2)
+X(DSP_PREADD)
+X(DSP_PREADD_DATA)
+X(DSP_A_B_DATA)
+X(DSP_MULTIPLIER)
+X(DSP_M_DATA)
+X(DSP_ALU)
+X(DSP_OUTPUT)
+X(DSP_C_DATA)
+
+X(DSP_L)
+X(DSP_R)
+X(DSP48E1)
+X(DSP48E1_DSP48E1)
+
+X(HPIO_L)
+X(XIPHY_BYTE_L)
+
+X(BITSLICE_COMPONENT_RX_TX)
+X(OUT_FF)
+X(ODELAYE3)
+X(OSERDESE3)
+X(IDELAYE3)
+X(ISERDESE3)
+X(IN_FF)
+
+X(LIOB33)
+X(RIOB33)
+
+X(IOB33M)
+X(IOB33S)
+X(IOB33)
+X(IPAD)
+
+X(PAD)
+X(IOB33M_OUTBUF)
+X(IOB33S_OUTBUF)
+X(IOB33_OUTBUF)
+X(IOB33M_INBUF_EN)
+X(IOB33S_INBUF_EN)
+X(IOB33_INBUF_EN)
+X(IOB33M_TERM_OVERRIDE)
+X(IOB33S_TERM_OVERRIDE)
+X(IOB33_TERM_OVERRIDE)
+X(PULL_OR_KEEP1)
+
+X(IDELAYE2)
+X(IDELAYE2_IDELAYE2)
+X(OLOGICE3)
+X(OLOGICE3_TFF)
+X(OLOGICE3_OUTFF)
+X(OLOGICE3_MISR)
+X(OSERDESE2)
+X(OSERDESE2_OSERDESE2)
+
+X(ILOGICE3)
+X(ILOGICE3_IFF)
+X(ILOGICE3_ZHOLD_DELAY)
+X(ISERDESE2)
+X(ISERDESE2_ISERDESE2)
+
+X(BUFR_BUFR)
+X(BUFIO_BUFIO)
+X(IDELAYCTRL_IDELAYCTRL)
+
+X(PLL_SELECT_BEL)
+
+X(PLL)
+X(PLL_PLL_TOP)
+X(MMCM)
+X(MMCM_MMCM_TOP)
+X(BUFGCE)
+X(BUFGCE_DIV)
+X(BUFCE_BUFG_PS)
+X(CMT_L)
+
+X(INTENT_DEFAULT)
+X(NODE_OUTPUT)
+X(NODE_DEDICATED)
+X(NODE_GLOBAL_VDISTR)
+X(NODE_GLOBAL_HROUTE)
+X(NODE_GLOBAL_HDISTR)
+X(NODE_PINFEED)
+X(NODE_PINBOUNCE)
+X(NODE_LOCAL)
+X(NODE_HLONG)
+X(NODE_SINGLE)
+X(NODE_DOUBLE)
+X(NODE_HQUAD)
+X(NODE_VLONG)
+X(NODE_VQUAD)
+X(NODE_OPTDELAY)
+X(NODE_GLOBAL_VROUTE)
+X(NODE_GLOBAL_LEAF)
+X(NODE_GLOBAL_BUFG)
+
+X(NODE_LAGUNA_DATA)
+X(NODE_CLE_OUTPUT)
+X(NODE_INT_INTERFACE)
+X(NODE_LAGUNA_OUTPUT)
+
+X(BENTQUAD)
+X(BOUNCEACROSS)
+X(BOUNCEIN)
+X(BUFGROUT)
+X(BUFINP2OUT)
+X(CLKPIN)
+X(DOUBLE)
+X(GENERIC)
+X(GLOBAL)
+X(HLONG)
+X(HQUAD)
+X(HVCCGNDOUT)
+X(INPUT)
+X(IOBIN2OUT)
+X(IOBINPUT)
+X(IOBOUTPUT)
+X(LUTINPUT)
+X(OPTDELAY)
+X(OUTBOUND)
+X(OUTPUT)
+X(PADINPUT)
+X(PADOUTPUT)
+X(PINBOUNCE)
+X(PINFEED)
+X(PINFEEDR)
+X(REFCLK)
+X(SINGLE)
+X(SLOWSINGLE)
+X(SVLONG)
+X(VLONG)
+X(VLONG12)
+X(VQUAD)
+
+X(INTENT_SITE_WIRE)
+X(INTENT_SITE_GND)
+
+X(IOB_IBUFCTRL)
+X(IOB_INBUF)
+X(IOB_OUTBUF)
+X(IOB_PAD)
+X(TRIBUF)
+
+X(BUFGCTRL)
+X(BUFGCE_DIV_BUFGCE_DIV)
+X(BUFCE_BUFCE)
+
+X(PS7)
+X(PS7_PS7)
+
+X(0)
+X(1)
+X(A)
+X(A0)
+X(ADDRARDADDRL15)
+X(ADDRATIEHIGH0)
+X(ADDRATIEHIGH1)
+X(ADDRBTIEHIGH0)
+X(ADDRBTIEHIGH1)
+X(ADDRBWRADDRL15)
+X(AREG)
+X(BEL)
+X(BITSLICE_CONTROL_BEL)
+X(BREG)
+X(BUFG)
+X(BUFG_BUFG)
+X(BUFG_PS)
+X(BUFHCE)
+X(BUFMRCE)
+X(C)
+X(CARRYIN)
+X(CARRY_TYPE)
+X(CB)
+X(CDDCREQ)
+X(CE0)
+X(CE1)
+X(CEA1)
+X(CEA2)
+X(CEAD)
+X(CEALUMODE)
+X(CEB1)
+X(CEB2)
+X(CEC)
+X(CECARRYIN)
+X(CECTRL)
+X(CED)
+X(CEINMODE)
+X(CEM)
+X(CEP)
+X(CFGLUT5)
+X(CI)
+X(CINVCTRL)
+X(CINVCTRL_SEL)
+X(CKB)
+X(CK_C)
+X(CLKARDCLK)
+X(CLKB)
+X(CLKBWRCLK)
+X(CLKDIV)
+X(CLKDIVP)
+X(CLKFBIN)
+X(CLKIN)
+X(CLKIN1)
+X(CLKIN2)
+X(CLKINSEL)
+X(CLKRSVD0)
+X(CLKRSVD1)
+X(CLK_B)
+X(CLK_EXT)
+X(CLR)
+X(COMPENSATION)
+X(CONVSTCLK)
+X(CPLLLOCKDETCLK)
+X(CYINIT)
+X(D1)
+X(D2)
+X(D3)
+X(D4)
+X(D5)
+X(D6)
+X(D7)
+X(D8)
+X(DATAOUT)
+X(DATA_RATE)
+X(DATA_RATE_OQ)
+X(DATA_RATE_TQ)
+X(DATA_WIDTH)
+X(DCITERMDISABLE)
+X(DCLK)
+X(DDLY)
+X(DDR_CLK_EDGE)
+X(DELAY_SRC)
+X(DEN)
+X(DI)
+X(DIADI0)
+X(DIADI1)
+X(DIBDI0)
+X(DIBDI1)
+X(DIFFINBUF)
+X(DIFFI_IN)
+X(DIFF_IN_N)
+X(DIFF_IN_P)
+X(DIPADIP0)
+X(DIPADIP1)
+X(DIPBDIP0)
+X(DIPBDIP1)
+X(DLY_TEST_IN)
+X(DMONITORCLK)
+X(DOA_REG)
+X(DOB_REG)
+X(DPO)
+X(DRIVE)
+X(DRPCLK)
+X(DWE)
+X(E)
+X(ECCPIPECE)
+X(ECCPIPECEL)
+X(ENARDEN)
+X(ENBWREN)
+X(EN_A)
+X(EN_B)
+X(EN_VTC)
+X(FDCE)
+X(FDCE_1)
+X(FDPE)
+X(FDPE_1)
+X(FDRE)
+X(FDRE_1)
+X(FDSE)
+X(FDSE_1)
+X(FIFO18E1)
+X(FIFO18E2)
+X(FIFO36E1)
+X(FIFO36E2)
+X(G)
+X(GND)
+X(GTGREFCLK)
+X(GTGREFCLK0)
+X(GTGREFCLK1)
+X(GTHE2_CHANNEL)
+X(GTHE2_COMMON)
+X(GTPE2_CHANNEL)
+X(GTPE2_COMMON)
+X(GTXE2_CHANNEL)
+X(GTXE2_COMMON)
+X(HARD_SYNC)
+X(HCLK_IOI)
+X(HCLK_IOI3)
+X(HIGH_PERFORMANCE_MODE)
+X(HPIO_OUTINV)
+X(HPIO_RIGHT)
+X(HPIO_VREF)
+X(I)
+X(I0)
+X(I1)
+X(I2)
+X(I3)
+X(I4)
+X(I5)
+X(IB)
+X(IBUF)
+X(IBUFCTRL)
+X(IBUFDISABLE)
+X(IBUFDS)
+X(IBUFDSE3)
+X(IBUFDS_DIFF_OUT)
+X(IBUFDS_DIFF_OUT_IBUFDISABLE)
+X(IBUFDS_DIFF_OUT_INTERMDISABLE)
+X(IBUFDS_GTE3)
+X(IBUFDS_GTE4)
+X(IBUFDS_INTERMDISABLE)
+X(IBUFDS_INTERMDISABLE_INT)
+X(IBUFE3)
+X(IBUF_ANALOG)
+X(IBUF_IBUFDISABLE)
+X(IBUF_INTERMDISABLE)
+X(IDATAIN)
+X(IDDR)
+X(IDDRE1)
+X(IDDR_2CLK)
+X(IDELAYCTRL)
+X(IDELAY_TYPE)
+X(IDELAY_VALUE)
+X(IFD_CE)
+X(IGNORE0)
+X(IGNORE1)
+X(IN)
+X(INBUF)
+X(INIT)
+X(INIT_OQ)
+X(INIT_OUT)
+X(INIT_Q1)
+X(INIT_Q2)
+X(INIT_TQ)
+X(INJECTDBITERR)
+X(INJECTSBITERR)
+X(INTENT)
+X(INTERFACE_TYPE)
+X(INTERMDISABLE)
+X(INV)
+X(INVERTER)
+X(IN_TERM)
+X(IO)
+X(IOB)
+X(IOB18M_OUTBUF_DCIEN)
+X(IOB18_INBUF_DCIEN)
+X(IOB18_OUTBUF_DCIEN)
+X(IOBDELAY)
+X(IOBUF)
+X(IOBUFDS)
+X(IOBUFDSE3)
+X(IOBUFDS_DCIEN)
+X(IOBUFDS_DIFF_OUT)
+X(IOBUFDS_DIFF_OUT_DCIEN)
+X(IOBUFDS_DIFF_OUT_INTERMDISABLE)
+X(IOBUFE3)
+X(IOBUF_DCIEN)
+X(IOBUF_INTERMDISABLE)
+X(IOB_DIFFINBUF)
+X(IOB_DIFFI_IN0)
+X(IOB_O0)
+X(IOB_O_IN1)
+X(IOB_O_OUT0)
+X(IOB_PADOUT1)
+X(IOB_T0)
+X(IOB_T_IN1)
+X(IOB_T_OUT0)
+X(IOL_IDDR)
+X(IOL_OPTFF)
+X(IOSTANDARD)
+X(IS_CARRYIN_INVERTED)
+X(IS_CE0_INVERTED)
+X(IS_CE1_INVERTED)
+X(IS_CLKINSEL_INVERTED)
+X(IS_CLK_INVERTED)
+X(IS_CLR_INVERTED)
+X(IS_C_INVERTED)
+X(IS_DATAIN_INVERTED)
+X(IS_D_INVERTED)
+X(IS_IDATAIN_INVERTED)
+X(IS_IGNORE0_INVERTED)
+X(IS_IGNORE1_INVERTED)
+X(IS_OCLK_INVERTED)
+X(IS_ODATAIN_INVERTED)
+X(IS_PRE_INVERTED)
+X(IS_PWRDWN_INVERTED)
+X(IS_RST_INVERTED)
+X(IS_R_INVERTED)
+X(IS_S0_INVERTED)
+X(IS_S1_INVERTED)
+X(IS_SR_INVERTED)
+X(IS_S_INVERTED)
+X(IS_WCLK_INVERTED)
+X(LDCE)
+X(LDPE)
+X(LDPIPEEN)
+X(LI)
+X(LOAD)
+X(LOC)
+X(LUT1)
+X(LUT2)
+X(LUT3)
+X(LUT4)
+X(LUT5)
+X(LUT6)
+X(LUT6_2)
+X(LUT_OR_MEM5LRAM)
+X(LUT_OR_MEM6LRAM)
+X(MMCME2_ADV)
+X(MMCME2_ADV_MMCME2_ADV)
+X(MMCME2_BASE)
+X(MMCME3_ADV)
+X(MMCME3_BASE)
+X(MMCME4_ADV)
+X(MMCME4_BASIC)
+X(MUXCY)
+X(MUXF7)
+X(MUXF8)
+X(MUXF9)
+X(MUX_TREE_ROOT)
+X(NUM_CE)
+X(O)
+X(OB)
+X(OBUF)
+X(OBUFDS)
+X(OBUFDS_GTE3)
+X(OBUFDS_GTE3_ADV)
+X(OBUFDS_GTE4)
+X(OBUFDS_GTE4_ADV)
+X(OBUFT)
+X(OBUFTDS)
+X(OBUFT_DCIEN)
+X(OCE)
+X(OCLK)
+X(OCLKB)
+X(ODATAIN)
+X(ODDR)
+X(ODDRE1)
+X(ODDR_MODE)
+X(ODELAYE2)
+X(ODELAYE2_ODELAYE2)
+X(ODELAY_TYPE)
+X(ODELAY_VALUE)
+X(OFB)
+X(OFD_CE)
+X(OLOGICE2_TFF)
+X(OLOGICE2_OUTFF)
+X(OQ)
+X(OR2L)
+X(OSC_EN)
+X(OSERDES_T_BYPASS)
+X(O_B)
+X(PACKAGE_PIN)
+X(PHASER_IN)
+X(PHASER_IN_PHY)
+X(PHASER_OUT)
+X(PHASER_OUT_PHY)
+X(PHASER_REF)
+X(PIP)
+X(PIPE_SEL)
+X(PLL0LOCKDETCLK)
+X(PLL1LOCKDETCLK)
+X(PLLE2_ADV)
+X(PLLE2_ADV_PLLE2_ADV)
+X(PLLE2_BASE)
+X(PLLE3_ADV)
+X(PLLE3_BASE)
+X(PLLE4_ADV)
+X(PLLE4_BASIC)
+X(PRE)
+X(PS8)
+X(PSCLK)
+X(PSEN)
+X(PSEUDO_GND_WIRE_GLBL)
+X(PSEUDO_GND_WIRE_ROW)
+X(PSEUDO_VCC_WIRE_GLBL)
+X(PSEUDO_VCC_WIRE_ROW)
+X(PSINCDEC)
+X(PSS_ALTO_CORE)
+X(PULLTYPE)
+X(PWRDWN)
+X(Q0)
+X(Q1)
+X(Q2)
+X(QPLLLOCKDETCLK)
+X(R)
+X(RADR0)
+X(RADR1)
+X(RADR2)
+X(RADR3)
+X(RADR4)
+X(RADR5)
+X(RAM128X1D)
+X(RAM128X1S)
+X(RAM256X1D)
+X(RAM256X1S)
+X(RAM32M)
+X(RAM32M16)
+X(RAM32X1D)
+X(RAM32X1S)
+X(RAM32X2S)
+X(RAM512X1D)
+X(RAM512X1S)
+X(RAM64M)
+X(RAM64M8)
+X(RAM64X1D)
+X(RAM64X1S)
+X(RAM64X8SW)
+X(RAMB18E1)
+X(RAMB18E2)
+X(RAMB36E1)
+X(RAMB36E2)
+X(RAMD32)
+X(RAMD64E)
+X(RDB_WR_A)
+X(RDB_WR_B)
+X(RDCLK)
+X(RDEN)
+X(RDY)
+X(REGCEAREGCE)
+X(REGCEB)
+X(REGRST)
+X(RIU_NIBBLE_SEL)
+X(RST)
+X(RSTA)
+X(RSTALLCARRYIN)
+X(RSTALUMODE)
+X(RSTB)
+X(RSTC)
+X(RSTCTRL)
+X(RSTD)
+X(RSTINMODE)
+X(RSTM)
+X(RSTP)
+X(RSTRAMARSTRAM)
+X(RSTRAMB)
+X(RSTREG)
+X(RSTREGARSTREG)
+X(RSTREGB)
+X(RST_A)
+X(RST_B)
+X(RST_DLY)
+X(RST_DLY_EXT)
+X(RXTX_BITSLICE)
+X(RXUSRCLK)
+X(RXUSRCLK2)
+X(RX_BITSLICE)
+X(RX_CLK)
+X(RX_RST)
+X(RX_RST_DLY)
+X(S)
+X(SELMUX2_1)
+X(SERDES_MODE)
+X(SIGVALIDCLK)
+X(SLEEP)
+X(SLEW)
+X(SPO)
+X(SRI)
+X(SRL16E)
+X(SRLC32E)
+X(SRTYPE)
+X(SRVAL_OQ)
+X(SRVAL_TQ)
+X(SYSMONE1)
+X(SYSMONE4)
+X(T)
+X(T1)
+X(T2)
+X(T3)
+X(T4)
+X(TBYTE_IN0)
+X(TBYTE_IN1)
+X(TBYTE_IN2)
+X(TBYTE_IN3)
+X(TCE)
+X(TQ)
+X(TRI)
+X(TXPHDLYTSTCLK)
+X(TXUSRCLK)
+X(TXUSRCLK2)
+X(TX_BITSLICE)
+X(TX_BITSLICE_TRI)
+X(TX_BIT_CTRL_OUT0)
+X(TX_CLK)
+X(TX_RST)
+X(TX_RST_DLY)
+X(T_OUT)
+X(URAM288_BASE)
+X(USE_DPORT)
+X(VCC)
+X(VREF)
+X(VTC_RDY)
+X(WCLK)
+X(WEA0)
+X(WEA1)
+X(WEA2)
+X(WEA3)
+X(WRCLK)
+X(WREN)
+X(WRITE_WIDTH_A)
+X(WRITE_WIDTH_B)
+X(XADC)
+X(XORCY)
+X(X_FFSYNC)
+X(X_FF_AS_LATCH)
+X(X_IOB_SITE_TYPE)
+X(X_IO_BEL)
+X(X_IO_DIR)
+X(X_LUT_AS_DRAM)
+X(X_LUT_AS_SRL)
+X(X_ORIG_MACRO_PRIM)
+X(X_ORIG_PORT_DIADI1)
+X(X_ORIG_PORT_DIBDI1)
+X(X_ORIG_PORT_O5)
+X(X_ORIG_PORT_O6)
+X(X_ORIG_PORT_SR)
+X(X_ORIG_TYPE)
+X(placer)
+X(route)
+X(router)
+X(step)
+X(xilinx)
diff --git a/himbaechel/uarch/xilinx/examples/.gitignore b/himbaechel/uarch/xilinx/examples/.gitignore
new file mode 100644
index 0000000000..f0927398d7
--- /dev/null
+++ b/himbaechel/uarch/xilinx/examples/.gitignore
@@ -0,0 +1,6 @@
+*.bin
+*.json
+*.log
+*.frames
+*.fasm
+abc.history
diff --git a/himbaechel/uarch/xilinx/examples/arty-a35/arty.xdc b/himbaechel/uarch/xilinx/examples/arty-a35/arty.xdc
new file mode 100644
index 0000000000..cdfbb57003
--- /dev/null
+++ b/himbaechel/uarch/xilinx/examples/arty-a35/arty.xdc
@@ -0,0 +1,52 @@
+# R
+set_property LOC G6 [get_ports led[0]]
+set_property LOC G3 [get_ports led[1]]
+set_property LOC J3 [get_ports led[2]]
+set_property LOC K1 [get_ports led[3]]
+# G
+set_property LOC F6 [get_ports led[4]]
+set_property LOC J4 [get_ports led[5]]
+set_property LOC J2 [get_ports led[6]]
+set_property LOC H6 [get_ports led[7]]
+# B
+set_property LOC E1 [get_ports led[8]]
+set_property LOC G4 [get_ports led[9]]
+set_property LOC H4 [get_ports led[10]]
+set_property LOC K2 [get_ports led[11]]
+
+# second row
+# set_property LOC H5 [get_ports led[12]]
+# set_property LOC J5 [get_ports led[13]]
+# set_property LOC T9 [get_ports led[14]]
+# set_property LOC T10 [get_ports led[15]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[15]]
+
+
+set_property LOC A8 [get_ports sw[0]]
+set_property LOC C11 [get_ports sw[1]]
+set_property LOC C10 [get_ports sw[2]]
+set_property LOC A10 [get_ports sw[3]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
+
+set_property LOC E3 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
diff --git a/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
new file mode 100755
index 0000000000..96f61b7a77
--- /dev/null
+++ b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+set -ex
+yosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top top; write_json blinky.json" blinky.v
+nextpnr-himbaechel --device xc7a35tcsg324-1 -o xdc=arty.xdc --json blinky.json -o fasm=blinky.fasm
+../bitgen_xray.sh xc7a35tcsg324-1 blinky.fasm blinky.bit
diff --git a/himbaechel/uarch/xilinx/examples/arty-a35/blinky.v b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.v
new file mode 100644
index 0000000000..a5b50c53ff
--- /dev/null
+++ b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.v
@@ -0,0 +1,21 @@
+module top (input clk, input [3:0] sw, output [11:0] led);
+
+    // assign led = {8'b0, ~(&sw), ^sw, &sw, |sw};
+
+    reg clkdiv;
+    reg [22:0] ctr;
+
+    always @(posedge clk) {clkdiv, ctr} <= ctr + 1'b1;
+
+    reg [5:0] led_r = 4'b0000;
+
+    always @(posedge clk) begin
+        if (clkdiv)
+            led_r <= led_r + 1'b1;
+    end
+
+    wire [11:0] led_s = led_r[3:0] << (4 * led_r[5:4]);
+
+    assign led = (&(led_r[5:4]) ? {3{led_r[3:0]}} : led_s) ^ {3{sw}};
+
+endmodule
diff --git a/himbaechel/uarch/xilinx/examples/bitgen_xray.sh b/himbaechel/uarch/xilinx/examples/bitgen_xray.sh
new file mode 100755
index 0000000000..60fe0bb5ef
--- /dev/null
+++ b/himbaechel/uarch/xilinx/examples/bitgen_xray.sh
@@ -0,0 +1,34 @@
+#!/usr/bin/env bash
+set -e
+
+if [ -z "$PRJXRAY" ]; then
+	echo "\$PRJXRAY must be set to a path to the prjxray repo"
+	exit 2
+fi
+if [ -z "$PRJXRAY_DB" ]; then
+	echo "\$PRJXRAY_DB must be set to a path to the prjxray-db repo"
+	exit 2
+fi
+
+if [ -z "$1" ] || [ -z "$2" ] || [ -z "$3" ]; then
+	echo "Usage: bitgen_xray.sh <device> <design.fasm> <design.bit>"
+	exit 2
+fi
+
+DEVICE="$1"
+
+FRAMES="$3.frames"
+
+if [[ "$DEVICE" =~ xc7a.* ]]; then
+	FAMILY=artix7
+elif [[ "$DEVICE" =~ xc7z.* ]]; then
+	FAMILY=zynq7
+elif [[ "$DEVICE" =~ xc7k.* ]]; then
+	FAMILY=kintex7
+else
+	echo "Unknown device $DEVICE"
+	exit 2
+fi
+
+python3 ${PRJXRAY}/utils/fasm2frames.py --part "${DEVICE}" --db-root "${PRJXRAY_DB}/${FAMILY}" "$2" "$FRAMES"
+${PRJXRAY}/build/tools/xc7frames2bit --part_file "${PRJXRAY_DB}/${FAMILY}/${DEVICE}/part.yaml" --part_name ${DEVICE} --frm_file "$FRAMES" --output_file "$3"
diff --git a/himbaechel/uarch/xilinx/extra_data.h b/himbaechel/uarch/xilinx/extra_data.h
new file mode 100644
index 0000000000..8b41bf23e6
--- /dev/null
+++ b/himbaechel/uarch/xilinx/extra_data.h
@@ -0,0 +1,107 @@
+#ifndef XILINX_EXTRA_DATA_H
+#define XILINX_EXTRA_DATA_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+NPNR_PACKED_STRUCT(struct XlnxBelExtraDataPOD { int32_t name_in_site; });
+
+struct BelSiteKey
+{
+    int16_t site;
+    int16_t site_variant;
+    inline static BelSiteKey unpack(uint32_t s)
+    {
+        BelSiteKey result;
+        result.site_variant = (s & 0xFF);
+        result.site = (s >> 8) & 0xFFFF;
+        return result;
+    };
+};
+
+enum XlnxPipType
+{
+    PIP_TILE_ROUTING = 0,
+    PIP_SITE_ENTRY = 1,
+    PIP_SITE_EXIT = 2,
+    PIP_SITE_INTERNAL = 3,
+    PIP_LUT_PERMUTATION = 4,
+    PIP_LUT_ROUTETHRU = 5,
+    PIP_CONST_DRIVER = 6,
+};
+
+NPNR_PACKED_STRUCT(struct XlnxPipExtraDataPOD {
+    int32_t site_key;
+    int32_t bel_name;
+    int32_t pip_config;
+});
+
+enum class PipClass
+{
+    PIP_TILE_ROUTING = 0,
+    PIP_SITE_ENTRY = 1,
+    PIP_SITE_EXIT = 2,
+    PIP_SITE_INTERNAL = 3,
+    PIP_LUT_PERMUTATION = 4,
+    PIP_LUT_ROUTETHRU = 5,
+    PIP_CONST_DRIVER = 6,
+};
+
+NPNR_PACKED_STRUCT(struct SiteInstPOD {
+    int32_t name_prefix;
+    int16_t site_x, site_y; // absolute site coords
+    int16_t rel_x, rel_y;   // coords in tiles
+    int16_t int_x, int_y;   // associated interconnect coords
+    RelSlice<int32_t> variants;
+});
+
+NPNR_PACKED_STRUCT(struct XlnxTileInstExtraDataPOD {
+    int32_t name_prefix;
+    int16_t tile_x, tile_y;
+    RelSlice<SiteInstPOD> sites;
+});
+
+// LSnibble of Z: function
+// MSnibble of Z: index in CLB (A-H)
+enum LogicBelTypeZ
+{
+    BEL_6LUT = 0x0,
+    BEL_5LUT = 0x1,
+    BEL_FF = 0x2,
+    BEL_FF2 = 0x3,
+    BEL_FFMUX1 = 0x4,
+    BEL_FFMUX2 = 0x5,
+    BEL_OUTMUX = 0x6,
+    BEL_F7MUX = 0x7,
+    BEL_F8MUX = 0x8,
+    BEL_F9MUX = 0x9,
+    BEL_CARRY8 = 0xA,
+    BEL_CLKINV = 0xB,
+    BEL_RSTINV = 0xC,
+    BEL_HARD0 = 0xD,
+    BEL_CARRY4 = 0xF
+};
+
+enum BRAMBelTypeZ
+{
+    BEL_RAMFIFO36 = 0,
+    BEL_RAM36 = 1,
+    BEL_FIFO36 = 2,
+
+    BEL_RAM18_U = 5,
+
+    BEL_RAMFIFO18_L = 8,
+    BEL_RAM18_L = 9,
+    BEL_FIFO18_L = 10,
+};
+
+enum DSP48E1BelTypeZ
+{
+    BEL_LOWER_DSP = 6,
+    BEL_UPPER_DSP = 25,
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc
new file mode 100644
index 0000000000..2c9dced7a0
--- /dev/null
+++ b/himbaechel/uarch/xilinx/fasm.cc
@@ -0,0 +1,1664 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-2023  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2023  Hans Baier <hansfbaier@gmail.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <boost/range/adaptor/reversed.hpp>
+
+#include <fstream>
+#include <regex>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pins.h"
+#include "util.h"
+
+#include "xilinx.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+namespace {
+struct FasmBackend
+{
+    Context *ctx;
+    XilinxImpl *uarch;
+    std::ostream &out;
+    std::vector<std::string> fasm_ctx;
+    dict<int, std::vector<PipId>> pips_by_tile;
+
+    dict<IdString, pool<IdString>> invertible_pins;
+
+    FasmBackend(Context *ctx, XilinxImpl *uarch, std::ostream &out) : ctx(ctx), uarch(uarch), out(out){};
+
+    void push(const std::string &x) { fasm_ctx.push_back(x); }
+
+    void pop() { fasm_ctx.pop_back(); }
+
+    void pop(int N)
+    {
+        for (int i = 0; i < N; i++)
+            fasm_ctx.pop_back();
+    }
+    bool last_was_blank = true;
+    void blank()
+    {
+        if (!last_was_blank)
+            out << std::endl;
+        last_was_blank = true;
+    }
+
+    void write_prefix()
+    {
+        for (auto &x : fasm_ctx)
+            out << x << ".";
+        last_was_blank = false;
+    }
+
+    void write_bit(const std::string &name, bool value = true)
+    {
+        if (value) {
+            write_prefix();
+            out << name << std::endl;
+        }
+    }
+
+    void write_vector(const std::string &name, const std::vector<bool> &value, bool invert = false)
+    {
+        write_prefix();
+        out << name << " = " << int(value.size()) << "'b";
+        for (auto bit : boost::adaptors::reverse(value))
+            out << ((bit ^ invert) ? '1' : '0');
+        out << std::endl;
+    }
+
+    void write_int_vector(const std::string &name, uint64_t value, int width, bool invert = false)
+    {
+        std::vector<bool> bits(width, false);
+        for (int i = 0; i < width; i++)
+            bits[i] = (value & (1ULL << i)) != 0;
+        write_vector(name, bits, invert);
+    }
+
+    struct PseudoPipKey
+    {
+        IdString tileType;
+        IdString dest;
+        IdString source;
+
+        bool operator==(const PseudoPipKey &b) const
+        {
+            return std::tie(this->tileType, this->dest, this->source) == std::tie(b.tileType, b.dest, b.source);
+        }
+
+        unsigned int hash() const { return mkhash(mkhash(tileType.hash(), source.hash()), dest.hash()); }
+    };
+
+    dict<PseudoPipKey, std::vector<std::string>> pp_config;
+    void get_pseudo_pip_data()
+    {
+        /*
+         * Create the mapping from pseudo pip tile type, dest wire, and source wire, to
+         * the config bits set when that pseudo pip is used
+         */
+        for (std::string s : {"L", "R"})
+            for (std::string s2 : {"", "_TBYTESRC", "_TBYTETERM", "_SING"})
+                for (std::string i :
+                     (s2 == "_SING") ? std::vector<std::string>{"", "0", "1"} : std::vector<std::string>{"0", "1"}) {
+                    pp_config[{ctx->id(s + "IOI3" + s2), ctx->id(s + "IOI_OLOGIC" + i + "_OQ"),
+                               ctx->id("IOI_OLOGIC" + i + "_D1")}] = {"OLOGIC_Y" + i + ".OMUX.D1",
+                                                                      "OLOGIC_Y" + i + ".OQUSED",
+                                                                      "OLOGIC_Y" + i + ".OSERDES.DATA_RATE_TQ.BUF"};
+                    pp_config[{ctx->id(s + "IOI3" + s2), ctx->id("IOI_ILOGIC" + i + "_O"),
+                               ctx->id(s + "IOI_ILOGIC" + i + "_D")}] = {"IDELAY_Y" + i + ".IDELAY_TYPE_FIXED",
+                                                                         "ILOGIC_Y" + i + ".ZINV_D"};
+                    pp_config[{ctx->id(s + "IOI3" + s2), ctx->id("IOI_ILOGIC" + i + "_O"),
+                               ctx->id(s + "IOI_ILOGIC" + i + "_DDLY")}] = {"ILOGIC_Y" + i + ".IDELMUXE3.P0",
+                                                                            "ILOGIC_Y" + i + ".ZINV_D"};
+                    pp_config[{ctx->id(s + "IOI3" + s2), ctx->id(s + "IOI_OLOGIC" + i + "_TQ"),
+                               ctx->id("IOI_OLOGIC" + i + "_T1")}] = {"OLOGIC_Y" + i + ".ZINV_T1"};
+                    if (i == "0") {
+                        pp_config[{ctx->id(s + "IOB33" + s2), id_IOB_O_IN1, id_IOB_O_OUT0}] = {};
+                        pp_config[{ctx->id(s + "IOB33" + s2), id_IOB_O_OUT0, id_IOB_O0}] = {};
+                        pp_config[{ctx->id(s + "IOB33" + s2), id_IOB_T_IN1, id_IOB_T_OUT0}] = {};
+                        pp_config[{ctx->id(s + "IOB33" + s2), id_IOB_T_OUT0, id_IOB_T0}] = {};
+                        pp_config[{ctx->id(s + "IOB33" + s2), id_IOB_DIFFI_IN0, id_IOB_PADOUT1}] = {};
+                    }
+                }
+
+        for (std::string s2 : {"", "_TBYTESRC", "_TBYTETERM", "_SING"})
+            for (std::string i : (s2 == "_SING") ? std::vector<std::string>{"0"} : std::vector<std::string>{"0", "1"}) {
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_OLOGIC" + i + "_OQ"),
+                           ctx->id("IOI_OLOGIC" + i + "_D1")}] = {"OLOGIC_Y" + i + ".OMUX.D1",
+                                                                  "OLOGIC_Y" + i + ".OQUSED",
+                                                                  "OLOGIC_Y" + i + ".OSERDES.DATA_RATE_TQ.BUF"};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_OLOGIC" + i + "_OFB"),
+                           ctx->id("RIOI_OLOGIC" + i + "_OQ")}] = {};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_O" + i), ctx->id("RIOI_ODELAY" + i + "_DATAOUT")}] = {};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_OLOGIC" + i + "_OFB"),
+                           ctx->id("IOI_OLOGIC" + i + "_D1")}] = {"OLOGIC_Y" + i + ".OMUX.D1",
+                                                                  "OLOGIC_Y" + i + ".OSERDES.DATA_RATE_TQ.BUF"};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("IOI_ILOGIC" + i + "_O"), ctx->id("RIOI_ILOGIC" + i + "_D")}] =
+                        {"ILOGIC_Y" + i + ".ZINV_D"};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("IOI_ILOGIC" + i + "_O"),
+                           ctx->id("RIOI_ILOGIC" + i + "_DDLY")}] = {"ILOGIC_Y" + i + ".IDELMUXE3.P0",
+                                                                     "ILOGIC_Y" + i + ".ZINV_D"};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_OLOGIC" + i + "_TQ"),
+                           ctx->id("IOI_OLOGIC" + i + "_T1")}] = {"OLOGIC_Y" + i + ".ZINV_T1"};
+                pp_config[{ctx->id("RIOI" + s2), ctx->id("RIOI_OLOGIC" + i + "_OFB"),
+                           ctx->id("RIOI_ODELAY" + i + "_ODATAIN")}] = {"OLOGIC_Y" + i + ".ZINV_ODATAIN"};
+                if (i == "0") {
+                    pp_config[{ctx->id("RIOB18" + s2), id_IOB_O_IN1, id_IOB_O_OUT0}] = {};
+                    pp_config[{ctx->id("RIOB18" + s2), id_IOB_O_OUT0, id_IOB_O0}] = {};
+                    pp_config[{ctx->id("RIOB18" + s2), id_IOB_T_IN1, id_IOB_T_OUT0}] = {};
+                    pp_config[{ctx->id("RIOB18" + s2), id_IOB_T_OUT0, id_IOB_T0}] = {};
+                    pp_config[{ctx->id("RIOB18" + s2), id_IOB_DIFFI_IN0, id_IOB_PADOUT1}] = {};
+                }
+            }
+
+        for (std::string s1 : {"TOP", "BOT"}) {
+            for (std::string s2 : {"L", "R"}) {
+                for (int i = 0; i < 12; i++) {
+                    std::string ii = std::to_string(i);
+                    std::string hck = s2 + ii;
+                    std::string buf = std::string((s2 == "R") ? "X1Y" : "X0Y") + ii;
+                    pp_config[{ctx->id("CLK_HROW_" + s1 + "_R"), ctx->id("CLK_HROW_CK_HCLK_OUT_" + hck),
+                               ctx->id("CLK_HROW_CK_MUX_OUT_" + hck)}] = {"BUFHCE.BUFHCE_" + buf + ".IN_USE",
+                                                                          "BUFHCE.BUFHCE_" + buf + ".ZINV_CE"};
+                }
+            }
+
+            for (int i = 0; i < 16; i++) {
+                std::string ii = std::to_string(i);
+                pp_config[{ctx->id("CLK_BUFG_" + s1 + "_R"), ctx->id("CLK_BUFG_BUFGCTRL" + ii + "_O"),
+                           ctx->id("CLK_BUFG_BUFGCTRL" + ii + "_I0")}] = {
+                        "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".IN_USE", "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".IS_IGNORE1_INVERTED",
+                        "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".ZINV_CE0", "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".ZINV_S0"};
+                pp_config[{ctx->id("CLK_BUFG_" + s1 + "_R"), ctx->id("CLK_BUFG_BUFGCTRL" + ii + "_O"),
+                           ctx->id("CLK_BUFG_BUFGCTRL" + ii + "_I1")}] = {
+                        "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".IN_USE", "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".IS_IGNORE0_INVERTED",
+                        "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".ZINV_CE1", "BUFGCTRL.BUFGCTRL_X0Y" + ii + ".ZINV_S1"};
+            }
+        }
+
+        int rclk_y_to_i[4] = {2, 3, 0, 1};
+        for (int y = 0; y < 4; y++) {
+            std::string yy = std::to_string(y);
+            std::string ii = std::to_string(rclk_y_to_i[y]);
+            pp_config[{id_HCLK_IOI3, ctx->id("HCLK_IOI_RCLK_OUT" + ii), ctx->id("HCLK_IOI_RCLK_BEFORE_DIV" + ii)}] = {
+                    "BUFR_Y" + yy + ".IN_USE", "BUFR_Y" + yy + ".BUFR_DIVIDE.BYPASS"};
+            pp_config[{id_HCLK_IOI, ctx->id("HCLK_IOI_RCLK_OUT" + ii), ctx->id("HCLK_IOI_RCLK_BEFORE_DIV" + ii)}] = {
+                    "BUFR_Y" + yy + ".IN_USE", "BUFR_Y" + yy + ".BUFR_DIVIDE.BYPASS"};
+        }
+
+        // FIXME: shouldn't these be in the X-RAY ppips database?
+        for (char c : {'L', 'R'}) {
+            for (int i = 0; i < 24; i++) {
+                pp_config[{ctx->idf("INT_INTERFACE_%c", c), ctx->idf("INT_INTERFACE_LOGIC_OUTS_%c%d", c, i),
+                           ctx->idf("INT_INTERFACE_LOGIC_OUTS_%c_B%d", c, i)}];
+            }
+        }
+    }
+
+    void write_pip(PipId pip, NetInfo *net)
+    {
+
+        pips_by_tile[pip.tile].push_back(pip);
+
+        auto dst_intent = ctx->getWireType(ctx->getPipDstWire(pip));
+        if (dst_intent == id_PSEUDO_GND || dst_intent == id_PSEUDO_VCC)
+            return;
+
+        auto &pd = chip_pip_info(ctx->chip_info, pip);
+        const auto &extra_data = *reinterpret_cast<const XlnxPipExtraDataPOD *>(pd.extra_data.get());
+        unsigned pip_type = pd.flags;
+
+        if (pip_type != PIP_TILE_ROUTING && pip_type != PIP_SITE_INTERNAL)
+            return;
+
+        IdString src = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
+        IdString dst = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.dst_wire].name);
+
+        // handle certain site internal pips:
+        // this is necessary, because in tristate outputs, the
+        // ZINV_T1 bit needs to be set, because in the OLOGIC tiles the
+        // tristate control signals are inverted if this bit is not set
+        // this only applies to router1, because router2 does not generate
+        // site internal pips here.
+        if (pip_type == PIP_SITE_INTERNAL) {
+            if (src.str(ctx) == "T1" && dst.str(ctx) == "T1INV_OUT") {
+                auto srcwire_uphill_iter = ctx->getPipsUphill(ctx->getPipSrcWire(pip));
+                auto uphill = srcwire_uphill_iter.begin();
+                if (uphill != srcwire_uphill_iter.end()) {
+                    // source wire should be like: LIOI3_X0Y73/IOI_OLOGIC1_T1
+                    auto loc = ctx->getWireName(ctx->getPipSrcWire(*uphill)).str(ctx);
+                    boost::replace_all(loc, "/", ".");
+                    boost::erase_all(loc, "_T1");
+                    boost::replace_all(loc, "IOI_OLOGIC", "OLOGIC_Y");
+                    // the replacements transformed it into : LIOI3_X0Y73.OLOGIC_Y1
+                    out << loc << "."
+                        << "ZINV_T1" << std::endl;
+                }
+            }
+            return;
+        }
+
+        // handle tile routing pips
+        IdString tile_type = IdString(chip_tile_info(ctx->chip_info, pip.tile).type_name);
+        PseudoPipKey ppk{tile_type, dst, src};
+
+        if (pp_config.count(ppk)) {
+            auto &pp = pp_config.at(ppk);
+            std::string tile_name = uarch->tile_name(pip.tile);
+            for (auto c : pp) {
+                if (boost::starts_with(tile_name, "RIOI3_SING") || boost::starts_with(tile_name, "LIOI3_SING") ||
+                    boost::starts_with(tile_name, "RIOI_SING")) {
+                    // Need to flip for top HCLK
+                    bool is_top_sing = pip.tile < uarch->hclk_for_ioi(pip.tile);
+                    if (is_top_sing) {
+                        auto y0pos = c.find("Y0");
+                        if (y0pos != std::string::npos)
+                            c.replace(y0pos, 2, "Y1");
+                    }
+                }
+                out << tile_name << "." << c << std::endl;
+            }
+            if (!pp.empty())
+                last_was_blank = false;
+        } else {
+            if (extra_data.pip_config == 1)
+                log_warning("Unprocessed route-thru %s.%s.%s\n!", tile_type.c_str(ctx), src.c_str(ctx), dst.c_str(ctx));
+
+            std::string tile_name = uarch->tile_name(pip.tile);
+            std::string dst_name = dst.str(ctx);
+            std::string src_name = src.str(ctx);
+
+            if (boost::starts_with(tile_name, "DSP_L") || boost::starts_with(tile_name, "DSP_R")) {
+                // FIXME: PPIPs missing for DSPs
+                return;
+            }
+            std::string orig_dst_name = dst_name;
+            if (boost::starts_with(tile_name, "RIOI3_SING") || boost::starts_with(tile_name, "LIOI3_SING") ||
+                boost::starts_with(tile_name, "RIOI_SING")) {
+                // FIXME: PPIPs missing for SING IOI3s
+                if ((boost::contains(src_name, "IMUX") || boost::contains(src_name, "CTRL0")) &&
+                    !boost::contains(dst_name, "CLK"))
+                    return;
+                auto spos = src_name.find("_SING_");
+                if (spos != std::string::npos)
+                    src_name.erase(spos, 5);
+                // Need to flip for top HCLK
+                // TODO
+
+                bool is_top_sing = pip.tile < uarch->hclk_for_ioi(pip.tile);
+                if (is_top_sing) {
+                    auto us0pos = dst_name.find("_0");
+                    if (us0pos != std::string::npos)
+                        dst_name.replace(us0pos, 2, "_1");
+                    auto ol0pos = dst_name.find("OLOGIC0");
+                    if (ol0pos != std::string::npos) {
+                        dst_name.replace(ol0pos, 7, "OLOGIC1");
+                        us0pos = src_name.find("_0");
+                        if (us0pos != std::string::npos)
+                            src_name.replace(us0pos, 2, "_1");
+                    }
+                }
+
+                NPNR_ASSERT_FALSE("unimplemented!");
+            }
+            if (boost::contains(tile_name, "IOI")) {
+                if (boost::contains(dst_name, "OCLKB") && boost::contains(src_name, "IOI_OCLKM_"))
+                    return; // missing, not sure if really a ppip?
+            }
+
+            out << tile_name << ".";
+            out << dst_name << ".";
+            out << src_name << std::endl;
+
+            if (boost::contains(tile_name, "IOI") && boost::starts_with(dst_name, "IOI_OCLK_")) {
+#if 0
+                dst_name.insert(dst_name.find("OCLK") + 4, 1, 'M');
+                orig_dst_name.insert(dst_name.find("OCLK") + 4, 1, 'M');
+
+                WireId w = ctx->getWireByNameStr(tile_name + "/" + orig_dst_name);
+                NPNR_ASSERT(w != WireId());
+                if (ctx->getBoundWireNet(w) == nullptr) {
+                    out << tile_name << ".";
+                    out << dst_name << ".";
+                    out << src_name << std::endl;
+                }
+#endif
+                NPNR_ASSERT_FALSE("unimplemented!");
+            }
+
+            last_was_blank = false;
+        }
+    };
+
+    // Get the set of input signals for a LUT-type cell
+    std::vector<IdString> get_inputs(CellInfo *cell)
+    {
+        IdString type = ctx->id(str_or_default(cell->attrs, id_X_ORIG_TYPE, ""));
+        if (type == id_LUT1)
+            return {id_I0};
+        else if (type == id_LUT2)
+            return {id_I0, id_I1};
+        else if (type == id_LUT3)
+            return {id_I0, id_I1, id_I2};
+        else if (type == id_LUT4)
+            return {id_I0, id_I1, id_I2, id_I3};
+        else if (type == id_LUT5)
+            return {id_I0, id_I1, id_I2, id_I3, id_I4};
+        else if (type == id_LUT6)
+            return {id_I0, id_I1, id_I2, id_I3, id_I4, id_I5};
+        else if (type == id_RAMD64E)
+            return {id_RADR0, id_RADR1, id_RADR2, id_RADR3, id_RADR4, id_RADR5};
+        else if (type == id_SRL16E)
+            return {id_A0, id_A1, id_A2, id_A3};
+        else if (type == id_SRLC32E)
+            return {ctx->id("A[0]"), ctx->id("A[1]"), ctx->id("A[2]"), ctx->id("A[3]"), ctx->id("A[4]")};
+        else if (type == id_RAMD32)
+            return {id_RADR0, id_RADR1, id_RADR2, id_RADR3, id_RADR4};
+        else
+            NPNR_ASSERT_FALSE("unsupported LUT-type cell");
+    }
+
+    // Process LUT initialisation
+    std::vector<bool> get_lut_init(CellInfo *lut6, CellInfo *lut5)
+    {
+        std::vector<bool> bits(64, false);
+
+        std::vector<IdString> phys_inputs;
+        for (int i = 1; i <= 6; i++)
+            phys_inputs.push_back(ctx->id("A" + std::to_string(i)));
+
+        for (int i = 0; i < 2; i++) {
+            CellInfo *lut = (i == 1) ? lut5 : lut6;
+            if (lut == nullptr)
+                continue;
+            auto lut_inputs = get_inputs(lut);
+            dict<int, std::vector<std::string>> phys_to_log;
+            dict<std::string, int> log_to_bit;
+            for (int j = 0; j < int(lut_inputs.size()); j++)
+                log_to_bit[lut_inputs[j].str(ctx)] = j;
+            for (int j = 0; j < 6; j++) {
+                // Get the LUT physical to logical mapping
+                phys_to_log[j];
+                if (!lut->attrs.count(ctx->idf("X_ORIG_PORT_%s", phys_inputs[j].c_str(ctx))))
+                    continue;
+                std::string orig = lut->attrs.at(ctx->idf("X_ORIG_PORT_%s", phys_inputs[j].c_str(ctx))).as_string();
+                boost::split(phys_to_log[j], orig, boost::is_any_of(" "));
+            }
+            int lbound = 0, ubound = 64;
+            // Fracturable LUTs
+            if (lut5 && lut6) {
+                lbound = (i == 1) ? 0 : 32;
+                ubound = (i == 1) ? 32 : 64;
+            }
+            Property init = get_or_default(lut->params, id_INIT, Property()).extract(0, 64);
+            for (int j = lbound; j < ubound; j++) {
+                int log_index = 0;
+                for (int k = 0; k < 6; k++) {
+                    if ((j & (1 << k)) == 0)
+                        continue;
+                    for (auto &p2l : phys_to_log[k])
+                        log_index |= (1 << log_to_bit[p2l]);
+                }
+                bits[j] = (init.str.at(log_index) == Property::S1);
+            }
+        }
+        return bits;
+    };
+
+    // Return the name for a half-logic-tile
+    std::string get_half_name(int half, bool is_m)
+    {
+        if (is_m)
+            return half ? "SLICEL_X1" : "SLICEM_X0";
+        else
+            return half ? "SLICEL_X1" : "SLICEL_X0";
+    }
+
+    std::string get_bel_name(BelId bel) { return uarch->bel_name_in_site(bel).str(ctx); }
+
+    void write_routing_bel(WireId dst_wire)
+    {
+        for (auto pip : ctx->getPipsUphill(dst_wire)) {
+            if (ctx->getBoundPipNet(pip) != nullptr) {
+                auto &pd = chip_pip_info(ctx->chip_info, pip);
+                const auto &extra_data = *reinterpret_cast<const XlnxPipExtraDataPOD *>(pd.extra_data.get());
+                std::string belname = IdString(extra_data.bel_name).str(ctx);
+                std::string pinname = IdString(extra_data.pip_config).str(ctx);
+                bool skip_pinname = false;
+                // Ignore modes with no associated bit (X-ray omission??)
+                if (belname == "WEMUX" && pinname == "WE")
+                    continue;
+
+                if (belname.substr(1) == "DI1MUX") {
+                    belname = "DI1MUX";
+                }
+
+                if (belname.substr(1) == "CY0") {
+                    if (pinname.substr(1) == "5")
+                        skip_pinname = true;
+                    else
+                        continue;
+                }
+
+                write_prefix();
+                out << belname;
+                if (!skip_pinname)
+                    out << "." << pinname;
+                out << std::endl;
+            }
+        }
+    }
+
+    // Process flipflops in a half-tile
+    void write_ffs_config(int tile, int half)
+    {
+        bool found_ff = false;
+        bool negedge_ff = false;
+        bool is_latch = false;
+        bool is_sync = false;
+        bool is_clkinv = false;
+        bool is_srused = false;
+        bool is_ceused = false;
+
+#define SET_CHECK(dst, src)                                                                                            \
+    do {                                                                                                               \
+        if (found_ff)                                                                                                  \
+            NPNR_ASSERT(dst == (src));                                                                                 \
+        else                                                                                                           \
+            dst = (src);                                                                                               \
+    } while (0)
+
+        std::string tname = uarch->tile_name(tile);
+
+        const auto &lts = uarch->tile_status.at(tile).lts;
+        if (!lts)
+            return;
+
+        push(tname);
+        push(get_half_name(half, boost::contains(tname, "CLBLM")));
+
+        for (int i = 0; i < 4; i++) {
+            CellInfo *ff1 = lts->cells[(half << 6) | (i << 4) | BEL_FF];
+            CellInfo *ff2 = lts->cells[(half << 6) | (i << 4) | BEL_FF2];
+            for (int j = 0; j < 2; j++) {
+                CellInfo *ff = (j == 1) ? ff2 : ff1;
+                if (ff == nullptr)
+                    continue;
+                push(get_bel_name(ff->bel));
+                bool zrst = false, zinit = false;
+                zinit = (int_or_default(ff->params, id_INIT, 0) != 1);
+                IdString srsig;
+                std::string type = str_or_default(ff->attrs, id_X_ORIG_TYPE, "");
+                if (type == "FDRE") {
+                    zrst = true;
+                    SET_CHECK(negedge_ff, false);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, true);
+                } else if (type == "FDRE_1") {
+                    zrst = true;
+                    SET_CHECK(negedge_ff, true);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, true);
+                } else if (type == "FDSE") {
+                    zrst = false;
+                    SET_CHECK(negedge_ff, false);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, true);
+                } else if (type == "FDSE_1") {
+                    zrst = false;
+                    SET_CHECK(negedge_ff, true);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, true);
+                } else if (type == "FDCE") {
+                    zrst = true;
+                    SET_CHECK(negedge_ff, false);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, false);
+                } else if (type == "FDCE_1") {
+                    zrst = true;
+                    SET_CHECK(negedge_ff, true);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, false);
+                } else if (type == "FDPE") {
+                    zrst = false;
+                    SET_CHECK(negedge_ff, false);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, false);
+                } else if (type == "FDPE_1") {
+                    zrst = false;
+                    SET_CHECK(negedge_ff, true);
+                    SET_CHECK(is_latch, false);
+                    SET_CHECK(is_sync, false);
+                } else {
+                    log_error("unsupported FF type: '%s'\n", type.c_str());
+                }
+
+                write_bit("ZINI", zinit);
+                write_bit("ZRST", zrst);
+
+                pop();
+                if (negedge_ff)
+                    SET_CHECK(is_clkinv, true);
+                else
+                    SET_CHECK(is_clkinv, int_or_default(ff->params, id_IS_C_INVERTED) == 1);
+
+                NetInfo *sr = ff->getPort(id_SR), *ce = ff->getPort(id_CE);
+
+                SET_CHECK(is_srused, sr != nullptr && sr->name != ctx->id("$PACKER_GND_NET"));
+                SET_CHECK(is_ceused, ce != nullptr && ce->name != ctx->id("$PACKER_VCC_NET"));
+
+                // Input mux
+                write_routing_bel(ctx->getBelPinWire(ff->bel, id_D));
+
+                found_ff = true;
+            }
+        }
+        write_bit("LATCH", is_latch);
+        write_bit("FFSYNC", is_sync);
+        write_bit("CLKINV", is_clkinv);
+        write_bit("NOCLKINV", !is_clkinv);
+        write_bit("SRUSEDMUX", is_srused);
+        write_bit("CEUSEDMUX", is_ceused);
+        pop(2);
+    }
+
+    // Get a named wire in the same site as a bel
+    WireId get_site_wire(BelId site_bel, std::string name)
+    {
+        IdStringList bel_name = ctx->getBelName(site_bel);
+        NPNR_ASSERT(bel_name.size() == 2);
+        IdString tile_name = bel_name[0];
+        const std::string &bel_name_str = bel_name[1].str(ctx);
+        size_t sep_pos = bel_name_str.find('.');
+        NPNR_ASSERT(sep_pos != std::string::npos);
+        std::string site_name = bel_name_str.substr(0, sep_pos);
+        IdString wire_name = ctx->idf("%s.%s", site_name.c_str(), name.c_str());
+        WireId wire = ctx->getWireByName(IdStringList::concat(tile_name, wire_name));
+        NPNR_ASSERT(wire != WireId());
+        return wire;
+    }
+
+    // Process LUTs and associated functionality in a half
+    void write_luts_config(int tile, int half)
+    {
+        bool wa7_used = false, wa8_used = false;
+
+        std::string tname = uarch->tile_name(tile);
+        bool is_mtile = boost::contains(tname, "CLBLM");
+        bool is_slicem = is_mtile && (half == 0);
+
+        const auto &lts = uarch->tile_status.at(tile).lts;
+        if (!lts)
+            return;
+
+        push(tname);
+        push(get_half_name(half, is_mtile));
+
+        BelId bel_in_half =
+                ctx->getBelByLocation(Loc(tile % ctx->chip_info->width, tile / ctx->chip_info->width, half << 6));
+
+        for (int i = 0; i < 4; i++) {
+            CellInfo *lut6 = lts->cells[(half << 6) | (i << 4) | BEL_6LUT];
+            CellInfo *lut5 = lts->cells[(half << 6) | (i << 4) | BEL_5LUT];
+            // Write LUT initialisation
+            if (lut6 != nullptr || lut5 != nullptr) {
+                std::string lutname = stringf("%cLUT", "ABCD"[i]);
+                push(lutname);
+                write_vector("INIT[63:0]", get_lut_init(lut6, lut5));
+
+                // Write LUT mode config
+                bool is_small = false, is_ram = false, is_srl = false;
+                for (int j = 0; j < 2; j++) {
+                    CellInfo *lut = (j == 1) ? lut5 : lut6;
+                    if (lut == nullptr)
+                        continue;
+                    std::string type = str_or_default(lut->attrs, id_X_ORIG_TYPE);
+                    if (type == "RAMD64E" || type == "RAMS64E") {
+                        is_ram = true;
+                    } else if (type == "RAMD32" || type == "RAMS32") {
+                        is_ram = true;
+                        is_small = true;
+                    } else if (type == "SRL16E") {
+                        is_srl = true;
+                        is_small = true;
+                    } else if (type == "SRLC32E") {
+                        is_srl = true;
+                    }
+                    wa7_used |= (lut->getPort(id_WA7) != nullptr);
+                    wa8_used |= (lut->getPort(id_WA8) != nullptr);
+                }
+                if (is_slicem && i != 3) {
+                    write_routing_bel(get_site_wire(bel_in_half, stringf("%cDI1MUX_OUT", "ABCD"[i])));
+                }
+                write_bit("SMALL", is_small);
+                write_bit("RAM", is_ram);
+                write_bit("SRL", is_srl);
+                pop();
+            }
+            write_routing_bel(get_site_wire(bel_in_half, stringf("%cMUX", "ABCD"[i])));
+        }
+        write_bit("WA7USED", wa7_used);
+        write_bit("WA8USED", wa8_used);
+        if (is_slicem)
+            write_routing_bel(get_site_wire(bel_in_half, "WEMUX_OUT"));
+
+        pop(2);
+    }
+
+    void write_carry_config(int tile, int half)
+    {
+        std::string tname = uarch->tile_name(tile);
+        bool is_mtile = boost::contains(tname, "CLBLM");
+
+        const auto &lts = uarch->tile_status.at(tile).lts;
+        if (!lts)
+            return;
+
+        CellInfo *carry = lts->cells[half << 6 | BEL_CARRY4];
+        if (carry == nullptr)
+            return;
+
+        push(tname);
+        push(get_half_name(half, is_mtile));
+
+        write_routing_bel(get_site_wire(carry->bel, "PRECYINIT_OUT"));
+        if (carry->getPort(id_CIN) != nullptr)
+            write_bit("PRECYINIT.CIN");
+        push("CARRY4");
+        for (char c : {'A', 'B', 'C', 'D'})
+            write_routing_bel(get_site_wire(carry->bel, stringf("%cCY0_OUT", c)));
+        pop(3);
+    }
+
+    void write_logic()
+    {
+        std::set<int> used_logic_tiles;
+        for (auto &cell : ctx->cells) {
+            if (uarch->is_logic_tile(cell.second->bel))
+                used_logic_tiles.insert(cell.second->bel.tile);
+        }
+        for (int tile : used_logic_tiles) {
+            write_luts_config(tile, 0);
+            write_luts_config(tile, 1);
+            write_ffs_config(tile, 0);
+            write_ffs_config(tile, 1);
+            write_carry_config(tile, 0);
+            write_carry_config(tile, 1);
+            blank();
+        }
+    }
+
+    void write_routing()
+    {
+        get_pseudo_pip_data();
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            out << stringf("# routing for net %s", ni->name.c_str(ctx)) << std::endl;
+            for (auto &w : ni->wires) {
+                if (w.second.pip != PipId())
+                    write_pip(w.second.pip, ni);
+            }
+            blank();
+        }
+    }
+
+    struct BankIoConfig
+    {
+        bool stepdown = false;
+        bool vref = false;
+        bool tmds_33 = false;
+        bool lvds_25 = false;
+        bool only_diff = false;
+    };
+
+    dict<int, BankIoConfig> ioconfig_by_hclk;
+
+    void write_io_config(CellInfo *pad)
+    {
+        NetInfo *pad_net = pad->getPort(id_PAD);
+        NPNR_ASSERT(pad_net != nullptr);
+        std::string iostandard = str_or_default(pad->attrs, id_IOSTANDARD, "LVCMOS33");
+        std::string pulltype = str_or_default(pad->attrs, id_PULLTYPE, "NONE");
+        std::string slew = str_or_default(pad->attrs, id_SLEW, "SLOW");
+
+        Loc ioLoc = uarch->rel_site_loc(uarch->get_bel_site(pad->bel));
+        bool is_output = false, is_input = false;
+        if (pad_net->driver.cell != nullptr)
+            is_output = true;
+        for (auto &usr : pad_net->users)
+            if (boost::contains(usr.cell->type.str(ctx), "INBUF"))
+                is_input = true;
+        std::string tile = uarch->tile_name(pad->bel.tile);
+        push(tile);
+
+        bool is_riob18 = boost::starts_with(tile, "RIOB18_");
+        bool is_sing = boost::contains(tile, "_SING_");
+        bool is_top_sing = pad->bel.tile < uarch->hclk_for_iob(pad->bel);
+        bool is_stepdown = false;
+        bool is_lvcmos = boost::starts_with(iostandard, "LVCMOS");
+        bool is_low_volt_lvcmos = iostandard == "LVCMOS12" || iostandard == "LVCMOS15" || iostandard == "LVCMOS18";
+
+        auto yLoc = is_sing ? (is_top_sing ? 1 : 0) : (1 - ioLoc.y);
+        push("IOB_Y" + std::to_string(yLoc));
+
+        bool has_diff_prefix = boost::starts_with(iostandard, "DIFF_");
+        bool is_tmds33 = iostandard == "TMDS_33";
+        bool is_lvds25 = iostandard == "LVDS_25";
+        bool is_lvds = boost::starts_with(iostandard, "LVDS");
+        bool only_diff = is_tmds33 || is_lvds;
+        bool is_diff = only_diff || has_diff_prefix;
+        if (has_diff_prefix)
+            iostandard.erase(0, 5);
+        bool is_sstl = iostandard == "SSTL12" || iostandard == "SSTL135" || iostandard == "SSTL15";
+
+        int hclk = uarch->hclk_for_iob(pad->bel);
+
+        if (only_diff)
+            ioconfig_by_hclk[hclk].only_diff = true;
+        if (is_tmds33)
+            ioconfig_by_hclk[hclk].tmds_33 = true;
+        if (is_lvds25)
+            ioconfig_by_hclk[hclk].lvds_25 = true;
+
+        if (is_output) {
+            // DRIVE
+            int default_drive = (is_riob18 && iostandard == "LVCMOS12") ? 8 : 12;
+            int drive = int_or_default(pad->attrs, id_DRIVE, default_drive);
+
+            if ((iostandard == "LVCMOS33" || iostandard == "LVTTL") && is_riob18)
+                log_error("high performance banks (RIOB18) do not support IO standard %s\n", iostandard.c_str());
+
+            if (iostandard == "SSTL135")
+                write_bit("SSTL135.DRIVE.I_FIXED");
+            else if (is_riob18) {
+                if ((iostandard == "LVCMOS18" || iostandard == "LVCMOS15"))
+                    write_bit("LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8");
+                else if (iostandard == "LVCMOS12")
+                    write_bit("LVCMOS12.DRIVE.I2_I4_I6_I8");
+                else if (iostandard == "LVDS")
+                    write_bit("LVDS.DRIVE.I_FIXED");
+                else if (is_sstl) {
+                    write_bit(iostandard + ".DRIVE.I_FIXED");
+                }
+            } else { // IOB33
+                if (iostandard == "TMDS_33" && yLoc == 0) {
+                    write_bit("TMDS_33.DRIVE.I_FIXED");
+                    write_bit("TMDS_33.OUT");
+                } else if (iostandard == "LVDS_25" && yLoc == 0) {
+                    write_bit("LVDS_25.DRIVE.I_FIXED");
+                    write_bit("LVDS_25.OUT");
+                } else if ((iostandard == "LVCMOS15" && drive == 16) || iostandard == "SSTL15")
+                    write_bit("LVCMOS15_SSTL15.DRIVE.I16_I_FIXED");
+                else if (iostandard == "LVCMOS18" && (drive == 12 || drive == 8))
+                    write_bit("LVCMOS18.DRIVE.I12_I8");
+                else if ((iostandard == "LVCMOS33" && drive == 16) || (iostandard == "LVTTL" && drive == 16))
+                    write_bit("LVCMOS33_LVTTL.DRIVE.I12_I16");
+                else if ((iostandard == "LVCMOS33" && (drive == 8 || drive == 12)) ||
+                         (iostandard == "LVTTL" && (drive == 8 || drive == 12)))
+                    write_bit("LVCMOS33_LVTTL.DRIVE.I12_I8");
+                else if ((iostandard == "LVCMOS33" && drive == 4) || (iostandard == "LVTTL" && drive == 4))
+                    write_bit("LVCMOS33_LVTTL.DRIVE.I4");
+                else if (drive == 8 && (iostandard == "LVCMOS12" || iostandard == "LVCMOS25"))
+                    write_bit("LVCMOS12_LVCMOS25.DRIVE.I8");
+                else if (drive == 4 &&
+                         (iostandard == "LVCMOS15" || iostandard == "LVCMOS18" || iostandard == "LVCMOS25"))
+                    write_bit("LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4");
+                else if (is_lvcmos || iostandard == "LVTTL")
+                    write_bit(iostandard + ".DRIVE.I" + std::to_string(drive));
+            }
+
+            // SSTL output used
+            if (is_riob18 && is_sstl)
+                write_bit(iostandard + ".IN_USE");
+
+            // SLEW
+            if (is_riob18 && slew == "SLOW") {
+                if (iostandard == "SSTL135")
+                    write_bit("SSTL135.SLEW.SLOW");
+                else if (iostandard == "SSTL15")
+                    write_bit("SSTL15.SLEW.SLOW");
+                else
+                    write_bit("LVCMOS12_LVCMOS15_LVCMOS18.SLEW.SLOW");
+            } else if (slew == "SLOW") {
+                if (iostandard != "LVDS_25" && iostandard != "TMDS_33")
+                    write_bit("LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW");
+            } else if (is_riob18)
+                write_bit(iostandard + ".SLEW.FAST");
+            else if (iostandard == "SSTL135" || iostandard == "SSTL15")
+                write_bit("SSTL135_SSTL15.SLEW.FAST");
+            else
+                write_bit("LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST");
+        }
+
+        if (is_input) {
+            if (!is_diff) {
+                if (iostandard == "LVCMOS33" || iostandard == "LVTTL" || iostandard == "LVCMOS25") {
+                    if (!is_riob18)
+                        write_bit("LVCMOS25_LVCMOS33_LVTTL.IN");
+                    else
+                        log_error("high performance banks (RIOB18) do not support IO standard %s\n",
+                                  iostandard.c_str());
+                }
+
+                if (is_sstl) {
+                    ioconfig_by_hclk[hclk].vref = true;
+                    if (!is_riob18)
+                        write_bit("SSTL135_SSTL15.IN");
+
+                    if (is_riob18) {
+                        write_bit("SSTL12_SSTL135_SSTL15.IN");
+                    }
+
+                    if (!is_riob18 && pad->attrs.count(id_IN_TERM))
+                        write_bit("IN_TERM." + pad->attrs.at(id_IN_TERM).as_string());
+                }
+
+                if (is_low_volt_lvcmos) {
+                    write_bit("LVCMOS12_LVCMOS15_LVCMOS18.IN");
+                }
+            } else /* is_diff */ {
+                if (is_riob18) {
+                    // vivado generates these bits only for Y0 of a diff pair
+                    if (yLoc == 0) {
+                        write_bit("LVDS_SSTL12_SSTL135_SSTL15.IN_DIFF");
+                        if (iostandard == "LVDS")
+                            write_bit("LVDS.IN_USE");
+                    }
+                } else {
+                    if (iostandard == "TDMS_33")
+                        write_bit("TDMS_33.IN_DIFF");
+                    else
+                        write_bit("LVDS_25_SSTL135_SSTL15.IN_DIFF");
+                }
+
+                if (pad->attrs.count(id_IN_TERM))
+                    write_bit("IN_TERM." + pad->attrs.at(id_IN_TERM).as_string());
+            }
+
+            // IN_ONLY
+            if (!is_output) {
+                if (is_riob18) {
+                    // vivado also sets this bit for DIFF_SSTL
+                    if (is_diff && (yLoc == 0))
+                        write_bit("LVDS.IN_ONLY");
+                    else
+                        write_bit("LVCMOS12_LVCMOS15_LVCMOS18_SSTL12_SSTL135_SSTL15.IN_ONLY");
+                } else
+                    write_bit("LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_"
+                              "ONLY");
+            }
+        }
+
+        if (!is_riob18 && (is_low_volt_lvcmos || is_sstl)) {
+            if (iostandard == "SSTL12") {
+                log_error("SSTL12 is only available on high performance banks.");
+            }
+            write_bit("LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN");
+            ioconfig_by_hclk[hclk].stepdown = true;
+            is_stepdown = true;
+        }
+
+        if (is_riob18 && (is_input || is_output) && (boost::contains(iostandard, "SSTL") || iostandard == "LVDS")) {
+            if (((yLoc == 0) && (iostandard == "LVDS")) || boost::contains(iostandard, "SSTL")) {
+                // TODO: I get bit conflicts with this, it seems to work anyway. Test more.
+                // write_bit("LVDS.IN_USE");
+            }
+        }
+
+        if (is_input && is_output && !is_diff && yLoc == 1) {
+            if (is_riob18 && boost::starts_with(iostandard, "SSTL"))
+                write_bit("SSTL12_SSTL135_SSTL15.IN");
+        }
+
+        write_bit("PULLTYPE." + pulltype);
+        pop(); // IOB_YN
+
+        BelId inv;
+
+        auto pad_bel_site = uarch->get_bel_site(pad->bel);
+
+        if (is_riob18)
+            inv = uarch->get_site_bel(pad_bel_site, ctx->id("IOB18S.O_ININV"));
+        else
+            inv = uarch->get_site_bel(pad_bel_site, ctx->id("IOB33S.O_ININV"));
+
+        if (inv != BelId() && ctx->getBoundBelCell(inv) != nullptr)
+            write_bit("OUT_DIFF");
+
+        if (is_stepdown && !is_sing)
+            write_bit("IOB_Y" + std::to_string(ioLoc.y) + ".LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN");
+
+        pop(); // tile
+    }
+
+    void write_iol_config(CellInfo *ci)
+    {
+        std::string tile = uarch->tile_name(ci->bel.tile);
+        push(tile);
+        bool is_sing = boost::contains(tile, "_SING_");
+        bool is_top_sing = ci->bel.tile < uarch->hclk_for_ioi(ci->bel.tile);
+
+        auto site_key = uarch->get_bel_site(ci->bel);
+        std::string site = uarch->get_site_name(site_key).str(ctx);
+        std::string sitetype = site.substr(0, site.find('_'));
+        Loc siteloc = uarch->rel_site_loc(site_key);
+        push(stringf("%s_Y%d", sitetype.c_str(), is_sing ? (is_top_sing ? 1 : 0) : (1 - siteloc.y)));
+
+        if (ci->type == id_ILOGICE3_IFF) {
+            write_bit("IDDR.IN_USE");
+            write_bit("IDDR_OR_ISERDES.IN_USE");
+            write_bit("ISERDES.MODE.MASTER");
+            write_bit("ISERDES.NUM_CE.N1");
+
+            // Switch IDELMUXE3 to include the IDELAY element, if we have an IDELAYE2 driving D
+            NetInfo *d = ci->getPort(id_D);
+            if (d == nullptr || d->driver.cell == nullptr)
+                log_error("%s '%s' has disconnected D input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            CellInfo *drv = d->driver.cell;
+            if (boost::contains(drv->type.str(ctx), "IDELAYE2"))
+                write_bit("IDELMUXE3.P0");
+            else
+                write_bit("IDELMUXE3.P1");
+
+            // clock edge
+            std::string edge = str_or_default(ci->params, id_DDR_CLK_EDGE, "OPPOSITE_EDGE");
+            if (edge == "SAME_EDGE")
+                write_bit("IFF.DDR_CLK_EDGE.SAME_EDGE");
+            else if (edge == "OPPOSITE_EDGE")
+                write_bit("IFF.DDR_CLK_EDGE.OPPOSITE_EDGE");
+            else
+                log_error("unsupported clock edge parameter for cell '%s' at %s: %s. Supported are: SAME_EDGE and "
+                          "OPPOSITE_EDGE",
+                          ci->name.c_str(ctx), site.c_str(), edge.c_str());
+
+            std::string srtype = str_or_default(ci->params, id_SRTYPE, "SYNC");
+            if (srtype == "SYNC")
+                write_bit("IFF.SRTYPE.SYNC");
+            else
+                write_bit("IFF.SRTYPE.ASYNC");
+
+            write_bit("IFF.ZINV_C", !bool_or_default(ci->params, id_IS_CLK_INVERTED, false));
+            write_bit("ZINV_D", !bool_or_default(ci->params, id_IS_D_INVERTED, false));
+
+            auto init = int_or_default(ci->params, id_INIT_Q1, 0);
+            if (init == 0)
+                write_bit("IFF.ZINIT_Q1");
+            init = int_or_default(ci->params, id_INIT_Q2, 0);
+            if (init == 0)
+                write_bit("IFF.ZINIT_Q2");
+
+            auto sr_name = str_or_default(ci->attrs, id_X_ORIG_PORT_SR, "R");
+            if (sr_name == "R") {
+                write_bit("IFF.ZSRVAL_Q1");
+                write_bit("IFF.ZSRVAL_Q2");
+            }
+        } else if (ci->type.in(id_OLOGICE2_OUTFF, id_OLOGICE3_OUTFF)) {
+            std::string edge = str_or_default(ci->params, id_DDR_CLK_EDGE, "OPPOSITE_EDGE");
+            if (edge == "SAME_EDGE")
+                write_bit("ODDR.DDR_CLK_EDGE.SAME_EDGE");
+
+            write_bit("ODDR_TDDR.IN_USE");
+            write_bit("OQUSED");
+            write_bit("OSERDES.DATA_RATE_OQ.DDR");
+            write_bit("OSERDES.DATA_RATE_TQ.BUF");
+
+            std::string srtype = str_or_default(ci->params, id_SRTYPE, "SYNC");
+            if (srtype == "SYNC")
+                write_bit("OSERDES.SRTYPE.SYNC");
+
+            for (std::string d : {"D1", "D2"})
+                write_bit("IS_" + d + "_INVERTED",
+                          bool_or_default(ci->params, ctx->id("IS_" + d + "_INVERTED"), false));
+
+            auto init = int_or_default(ci->params, id_INIT, 1);
+            if (init == 0)
+                write_bit("ZINIT_OQ");
+
+            write_bit("ODDR.SRUSED", ci->getPort(id_SR) != nullptr);
+            auto sr_name = str_or_default(ci->attrs, id_X_ORIG_PORT_SR, "R");
+            if (sr_name == "R")
+                write_bit("ZSRVAL_OQ");
+
+            auto clk_inv = bool_or_default(ci->params, id_IS_CLK_INVERTED);
+            if (!clk_inv)
+                write_bit("ZINV_CLK");
+        } else if (ci->type == id_OSERDESE2_OSERDESE2) {
+            write_bit("ODDR.DDR_CLK_EDGE.SAME_EDGE");
+            write_bit("ODDR.SRUSED");
+            write_bit("ODDR_TDDR.IN_USE");
+            write_bit("OQUSED", ci->getPort(id_OQ) != nullptr);
+            write_bit("ZINV_CLK", !bool_or_default(ci->params, id_IS_CLK_INVERTED, false));
+            for (std::string t : {"T1", "T2", "T3", "T4"})
+                write_bit("ZINV_" + t, (ci->getPort(ctx->id(t)) != nullptr || t == "T1") &&
+                                               !bool_or_default(ci->params, ctx->id("IS_" + t + "_INVERTED"), false));
+            for (std::string d : {"D1", "D2", "D3", "D4", "D5", "D6", "D7", "D8"})
+                write_bit("IS_" + d + "_INVERTED",
+                          bool_or_default(ci->params, ctx->id("IS_" + d + "_INVERTED"), false));
+            write_bit("ZINIT_OQ", !bool_or_default(ci->params, id_INIT_OQ, false));
+            write_bit("ZINIT_TQ", !bool_or_default(ci->params, id_INIT_TQ, false));
+            write_bit("ZSRVAL_OQ", !bool_or_default(ci->params, id_SRVAL_OQ, false));
+            write_bit("ZSRVAL_TQ", !bool_or_default(ci->params, id_SRVAL_TQ, false));
+
+            push("OSERDES");
+            write_bit("IN_USE");
+            std::string type = str_or_default(ci->params, id_DATA_RATE_OQ, "BUF");
+            write_bit(std::string("DATA_RATE_OQ.") + ((ci->getPort(id_OQ) != nullptr) ? type : "BUF"));
+            write_bit(std::string("DATA_RATE_TQ.") +
+                      ((ci->getPort(id_TQ) != nullptr) ? str_or_default(ci->params, id_DATA_RATE_TQ, "BUF") : "BUF"));
+            int width = int_or_default(ci->params, id_DATA_WIDTH, 8);
+#if 0
+            write_bit("DATA_WIDTH.W" + std::to_string(width));
+            if (type == "DDR" && (width == 6 || width == 8)) {
+                write_bit("DATA_WIDTH.DDR.W6_8");
+                write_bit("DATA_WIDTH.SDR.W2_4_5_6");
+            } else if (type == "SDR" && (width == 2 || width == 4 || width == 5 || width == 6)) {
+                write_bit("DATA_WIDTH.SDR.W2_4_5_6");
+            }
+#else
+            if (type == "DDR")
+                write_bit("DATA_WIDTH.DDR.W" + std::to_string(width));
+            else if (type == "SDR")
+                write_bit("DATA_WIDTH.SDR.W" + std::to_string(width));
+            else
+                write_bit("DATA_WIDTH.W" + std::to_string(width));
+#endif
+            write_bit("SRTYPE.SYNC");
+            write_bit("TSRTYPE.SYNC");
+            pop();
+        } else if (ci->type == id_ISERDESE2_ISERDESE2) {
+            std::string data_rate = str_or_default(ci->params, id_DATA_RATE);
+            write_bit("IDDR_OR_ISERDES.IN_USE");
+            if (data_rate == "DDR")
+                write_bit("IDDR.IN_USE");
+            write_bit("IFF.DDR_CLK_EDGE.OPPOSITE_EDGE");
+            write_bit("IFF.SRTYPE.SYNC");
+            for (int i = 1; i <= 4; i++) {
+                write_bit("IFF.ZINIT_Q" + std::to_string(i),
+                          !bool_or_default(ci->params, ctx->idf("INIT_Q%d", i), false));
+                write_bit("IFF.ZSRVAL_Q" + std::to_string(i),
+                          !bool_or_default(ci->params, ctx->idf("SRVAL_Q%d", i), false));
+            }
+            write_bit("IFF.ZINV_C", !bool_or_default(ci->params, id_IS_CLK_INVERTED, false));
+            write_bit("IFF.ZINV_OCLK", !bool_or_default(ci->params, id_IS_OCLK_INVERTED, false));
+
+            std::string iobdelay = str_or_default(ci->params, id_IOBDELAY, "NONE");
+            write_bit("IFFDELMUXE3.P0", (iobdelay == "IFD"));
+            write_bit("ZINV_D", !bool_or_default(ci->params, id_IS_D_INVERTED, false) && (iobdelay != "IFD"));
+
+            push("ISERDES");
+            write_bit("IN_USE");
+            int width = int_or_default(ci->params, id_DATA_WIDTH, 8);
+            std::string mode = str_or_default(ci->params, id_INTERFACE_TYPE, "NETWORKING");
+            std::string rate = str_or_default(ci->params, id_DATA_RATE, "DDR");
+            write_bit(mode + "." + rate + ".W" + std::to_string(width));
+            write_bit("MODE." + str_or_default(ci->params, id_SERDES_MODE, "MASTER"));
+            write_bit("NUM_CE.N" + std::to_string(int_or_default(ci->params, id_NUM_CE, 1)));
+            pop();
+        } else if (ci->type == id_IDELAYE2_IDELAYE2) {
+            write_bit("IN_USE");
+            write_bit("CINVCTRL_SEL", str_or_default(ci->params, id_CINVCTRL_SEL, "FALSE") == "TRUE");
+            write_bit("PIPE_SEL", str_or_default(ci->params, id_PIPE_SEL, "FALSE") == "TRUE");
+            write_bit("HIGH_PERFORMANCE_MODE", str_or_default(ci->params, id_HIGH_PERFORMANCE_MODE, "FALSE") == "TRUE");
+            write_bit("DELAY_SRC_" + str_or_default(ci->params, id_DELAY_SRC, "IDATAIN"));
+            write_bit("IDELAY_TYPE_" + str_or_default(ci->params, id_IDELAY_TYPE, "FIXED"));
+            write_int_vector("IDELAY_VALUE[4:0]", int_or_default(ci->params, id_IDELAY_VALUE, 0), 5, false);
+            write_int_vector("ZIDELAY_VALUE[4:0]", int_or_default(ci->params, id_IDELAY_VALUE, 0), 5, true);
+            write_bit("IS_DATAIN_INVERTED", bool_or_default(ci->params, id_IS_DATAIN_INVERTED, false));
+            write_bit("IS_IDATAIN_INVERTED", bool_or_default(ci->params, id_IS_IDATAIN_INVERTED, false));
+        } else if (ci->type == id_ODELAYE2_ODELAYE2) {
+            write_bit("IN_USE");
+            write_bit("CINVCTRL_SEL", str_or_default(ci->params, id_CINVCTRL_SEL, "FALSE") == "TRUE");
+            write_bit("HIGH_PERFORMANCE_MODE", str_or_default(ci->params, id_HIGH_PERFORMANCE_MODE, "FALSE") == "TRUE");
+            auto type = str_or_default(ci->params, id_ODELAY_TYPE, "FIXED");
+            if (type != "FIXED")
+                write_bit("ODELAY_TYPE_" + type);
+            write_int_vector("ODELAY_VALUE[4:0]", int_or_default(ci->params, id_ODELAY_VALUE, 0), 5, false);
+            write_int_vector("ZODELAY_VALUE[4:0]", int_or_default(ci->params, id_ODELAY_VALUE, 0), 5, true);
+            write_bit("ZINV_ODATAIN", !bool_or_default(ci->params, id_IS_ODATAIN_INVERTED, false));
+        } else {
+            NPNR_ASSERT_FALSE("unsupported IOLOGIC");
+        }
+        pop(2);
+    }
+
+    void write_io()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_PAD) {
+                write_io_config(ci);
+                blank();
+            } else if (ci->type.in(id_ILOGICE3_IFF, id_OLOGICE2_OUTFF, id_OLOGICE3_OUTFF, id_OSERDESE2_OSERDESE2,
+                                   id_ISERDESE2_ISERDESE2, id_IDELAYE2_IDELAYE2, id_ODELAYE2_ODELAYE2)) {
+                write_iol_config(ci);
+                blank();
+            }
+        }
+        for (auto &hclk : ioconfig_by_hclk) {
+            push(uarch->tile_name(hclk.first));
+            write_bit("STEPDOWN", hclk.second.stepdown);
+            write_bit("VREF.V_675_MV", hclk.second.vref);
+            write_bit("ONLY_DIFF_IN_USE", hclk.second.only_diff);
+            write_bit("TMDS_33_IN_USE", hclk.second.tmds_33);
+            write_bit("LVDS_25_IN_USE", hclk.second.lvds_25);
+            pop();
+        }
+    }
+
+    std::vector<std::string> used_wires_starting_with(int tile, const std::string &prefix, bool is_source)
+    {
+        std::vector<std::string> wires;
+        if (!pips_by_tile.count(tile))
+            return wires;
+        for (auto pip : pips_by_tile[tile]) {
+            auto &pd = chip_pip_info(ctx->chip_info, pip);
+            int wire_index = is_source ? pd.src_wire : pd.dst_wire;
+            std::string wire = IdString(chip_wire_info(ctx->chip_info, WireId(pip.tile, wire_index)).name).str(ctx);
+            if (boost::starts_with(wire, prefix))
+                wires.push_back(wire);
+        }
+        return wires;
+    }
+
+    void write_clocking()
+    {
+        std::string name, type;
+
+        std::set<std::string> all_gclk;
+        dict<int, std::set<std::string>> hclk_by_row;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_BUFGCTRL) {
+                push(uarch->tile_name(ci->bel.tile));
+                auto xy = uarch->rel_site_loc(uarch->get_bel_site(ci->bel));
+                push(stringf("BUFGCTRL.BUFGCTRL_X%dY%d", xy.x, xy.y));
+                write_bit("IN_USE");
+                write_bit("INIT_OUT", bool_or_default(ci->params, id_INIT_OUT));
+                write_bit("IS_IGNORE0_INVERTED", bool_or_default(ci->params, id_IS_IGNORE0_INVERTED));
+                write_bit("IS_IGNORE1_INVERTED", bool_or_default(ci->params, id_IS_IGNORE1_INVERTED));
+                write_bit("ZINV_CE0", !bool_or_default(ci->params, id_IS_CE0_INVERTED));
+                write_bit("ZINV_CE1", !bool_or_default(ci->params, id_IS_CE1_INVERTED));
+                write_bit("ZINV_S0", !bool_or_default(ci->params, id_IS_S0_INVERTED));
+                write_bit("ZINV_S1", !bool_or_default(ci->params, id_IS_S1_INVERTED));
+                pop(2);
+            } else if (ci->type == id_PLLE2_ADV_PLLE2_ADV) {
+                write_pll(ci);
+            }
+            blank();
+        }
+
+        for (int tile = 0; tile < ctx->chip_info->tile_insts.ssize(); tile++) {
+            std::string name = uarch->tile_name(tile);
+            std::string type = ctx->get_tile_type(tile).str(ctx);
+            push(name);
+            if (type == "HCLK_L" || type == "HCLK_R" || type == "HCLK_L_BOT_UTURN" || type == "HCLK_R_BOT_UTURN") {
+                auto used_sources = used_wires_starting_with(tile, "HCLK_CK_", true);
+                push("ENABLE_BUFFER");
+                for (auto s : used_sources) {
+                    if (boost::contains(s, "BUFHCLK")) {
+                        write_bit(s);
+                        hclk_by_row[tile / ctx->chip_info->width].insert(s.substr(s.find("BUFHCLK")));
+                    }
+                }
+                pop();
+            } else if (boost::starts_with(type, "CLK_HROW")) {
+                auto used_gclk = used_wires_starting_with(tile, "CLK_HROW_R_CK_GCLK", true);
+                auto used_ck_in = used_wires_starting_with(tile, "CLK_HROW_CK_IN", true);
+                for (auto s : used_gclk) {
+                    write_bit(s + "_ACTIVE");
+                    all_gclk.insert(s.substr(s.find("GCLK")));
+                }
+                for (auto s : used_ck_in) {
+                    if (boost::contains(s, "HROW_CK_INT"))
+                        continue;
+                    write_bit(s + "_ACTIVE");
+                }
+            } else if (boost::starts_with(type, "HCLK_CMT")) {
+                auto used_ccio = used_wires_starting_with(tile, "HCLK_CMT_CCIO", true);
+                for (auto s : used_ccio) {
+                    write_bit(s + "_ACTIVE");
+                    write_bit(s + "_USED");
+                }
+                auto used_hclk = used_wires_starting_with(tile, "HCLK_CMT_CK_", true);
+                for (auto s : used_hclk) {
+                    if (boost::contains(s, "BUFHCLK")) {
+                        write_bit(s + "_USED");
+                        hclk_by_row[tile / ctx->chip_info->width].insert(s.substr(s.find("BUFHCLK")));
+                    }
+                }
+            }
+            pop();
+            blank();
+        }
+
+        for (int tile = 0; tile < ctx->chip_info->tile_insts.ssize(); tile++) {
+            std::string name = uarch->tile_name(tile);
+            std::string type = ctx->get_tile_type(tile).str(ctx);
+            push(name);
+            if (type == "CLK_BUFG_REBUF") {
+                for (auto &gclk : all_gclk) {
+                    write_bit(gclk + "_ENABLE_ABOVE");
+                    write_bit(gclk + "_ENABLE_BELOW");
+                }
+            } else if (boost::starts_with(type, "HCLK_CMT")) {
+                for (auto &hclk : hclk_by_row[tile / ctx->chip_info->width]) {
+                    write_bit("HCLK_CMT_CK_" + hclk + "_USED");
+                }
+            }
+            pop();
+            blank();
+        }
+    }
+
+    void write_bram_width(CellInfo *ci, const std::string &name, bool is_36, bool is_y1)
+    {
+        int width = int_or_default(ci->params, ctx->id(name), 0);
+        if (width == 0)
+            return;
+        int actual_width = width;
+        if (is_36) {
+            if (width == 1)
+                actual_width = 1;
+            else
+                actual_width = width / 2;
+        }
+        if (((is_36 && width == 72) || (is_y1 && actual_width == 36)) && name == "READ_WIDTH_A") {
+            write_bit(name + "_18");
+        }
+        if (actual_width == 36) {
+            write_bit("SDP_" + name.substr(0, name.length() - 2) + "_36");
+            if (name.find("WRITE") == 0) {
+                write_bit(name.substr(0, name.size() - 1) + "A_18");
+                write_bit(name.substr(0, name.size() - 1) + "B_18");
+            } else if (name.find("READ") == 0) {
+                write_bit(name.substr(0, name.size() - 1) + "B_18");
+            }
+        } else {
+            write_bit(name + "_" + std::to_string(actual_width));
+        }
+    }
+
+    void write_bram_init(int half, CellInfo *ci, bool is_36)
+    {
+        for (std::string mode : {"", "P"}) {
+            for (int i = 0; i < (mode == "P" ? 8 : 64); i++) {
+                bool has_init = false;
+                std::vector<bool> init_data(256, false);
+                if (is_36) {
+                    for (int j = 0; j < 2; j++) {
+                        IdString param = ctx->idf("INIT%s_%02X", mode.c_str(), i * 2 + j);
+                        if (ci->params.count(param)) {
+                            auto &init0 = ci->params.at(param);
+                            has_init = true;
+                            for (int k = half; k < 256; k += 2) {
+                                if (k >= int(init0.str.size()))
+                                    break;
+                                init_data[j * 128 + (k / 2)] = init0.str[k] == Property::S1;
+                            }
+                        }
+                    }
+                } else {
+                    IdString param = ctx->idf("INIT%s_%02X", mode.c_str(), i);
+                    if (ci->params.count(param)) {
+                        auto &init = ci->params.at(param);
+                        has_init = true;
+                        for (int k = 0; k < 256; k++) {
+                            if (k >= int(init.str.size()))
+                                break;
+                            init_data[k] = init.str[k] == Property::S1;
+                        }
+                    }
+                }
+                if (has_init)
+                    write_vector(stringf("INIT%s_%02X[255:0]", mode.c_str(), i), init_data);
+            }
+        }
+    }
+
+    void write_bram_half(int tile, int half, CellInfo *ci)
+    {
+        push(uarch->tile_name(tile));
+        push("RAMB18_Y" + std::to_string(half));
+        if (ci != nullptr) {
+            bool is_36 = ci->type == id_RAMB36E1_RAMB36E1;
+            write_bit("IN_USE");
+            write_bram_width(ci, "READ_WIDTH_A", is_36, half == 1);
+            write_bram_width(ci, "READ_WIDTH_B", is_36, half == 1);
+            write_bram_width(ci, "WRITE_WIDTH_A", is_36, half == 1);
+            write_bram_width(ci, "WRITE_WIDTH_B", is_36, half == 1);
+            write_bit("DOA_REG", bool_or_default(ci->params, id_DOA_REG, false));
+            write_bit("DOB_REG", bool_or_default(ci->params, id_DOB_REG, false));
+            for (auto &invpin : invertible_pins[ctx->id(ci->attrs[id_X_ORIG_TYPE].as_string())])
+                write_bit("ZINV_" + invpin.str(ctx),
+                          !bool_or_default(ci->params, ctx->id("IS_" + invpin.str(ctx) + "_INVERTED"), false));
+            for (auto wrmode : {"WRITE_MODE_A", "WRITE_MODE_B"}) {
+                std::string mode = str_or_default(ci->params, ctx->id(wrmode), "WRITE_FIRST");
+                if (mode != "WRITE_FIRST")
+                    write_bit(std::string(wrmode) + "_" + mode);
+            }
+            write_vector("ZINIT_A[17:0]", std::vector<bool>(18, true));
+            write_vector("ZINIT_B[17:0]", std::vector<bool>(18, true));
+            write_vector("ZSRVAL_A[17:0]", std::vector<bool>(18, true));
+            write_vector("ZSRVAL_B[17:0]", std::vector<bool>(18, true));
+
+            write_bram_init(half, ci, is_36);
+        }
+        pop();
+        if (half == 0) {
+            auto used_rdaddrcasc = used_wires_starting_with(tile, "BRAM_CASCOUT_ADDRARDADDR", false);
+            auto used_wraddrcasc = used_wires_starting_with(tile, "BRAM_CASCOUT_ADDRBWRADDR", false);
+            write_bit("CASCOUT_ARD_ACTIVE", !used_rdaddrcasc.empty());
+            write_bit("CASCOUT_BWR_ACTIVE", !used_wraddrcasc.empty());
+        }
+        pop();
+    }
+
+    void write_bram()
+    {
+        for (int tile = 0; tile < ctx->chip_info->tile_insts.ssize(); tile++) {
+            IdString type = ctx->get_tile_type(tile);
+            if (type.in(id_BRAM_L, id_BRAM_R)) {
+                CellInfo *l = nullptr, *u = nullptr;
+                const auto &bts = uarch->tile_status[tile].bts;
+                if (bts) {
+                    if (bts->cells[BEL_RAM36] != nullptr) {
+                        l = bts->cells[BEL_RAM36];
+                        u = bts->cells[BEL_RAM36];
+                    } else {
+                        l = bts->cells[BEL_RAM18_L];
+                        u = bts->cells[BEL_RAM18_U];
+                    }
+                }
+                write_bram_half(tile, 0, l);
+                write_bram_half(tile, 1, u);
+                blank();
+            }
+        }
+    }
+
+    double float_or_default(CellInfo *ci, const std::string &name, double def)
+    {
+        IdString p = ctx->id(name);
+        if (!ci->params.count(p))
+            return def;
+        auto &prop = ci->params.at(p);
+        if (prop.is_string)
+            return std::stod(prop.as_string());
+        else
+            return prop.as_int64();
+    }
+
+    void write_pll_clkout(const std::string &name, CellInfo *ci)
+    {
+        // FIXME: variable duty cycle
+        int high = 1, low = 1, phasemux = 0, delaytime = 0, frac = 0;
+        bool no_count = false, edge = false;
+        double divide = float_or_default(ci, name + ((name == "CLKFBOUT") ? "_MULT" : "_DIVIDE"), 1);
+        double phase = float_or_default(ci, name + "_PHASE", 1);
+        if (divide <= 1) {
+            no_count = true;
+        } else {
+            high = floor(divide / 2);
+            low = int(floor(divide) - high);
+            if (high != low)
+                edge = true;
+            if (name == "CLKOUT1" || name == "CLKFBOUT")
+                frac = floor(divide * 8) - floor(divide) * 8;
+            int phase_eights = floor((phase / 360) * divide * 8);
+            phasemux = phase_eights % 8;
+            delaytime = phase_eights / 8;
+        }
+        bool used = false;
+        if (name == "DIVCLK" || name == "CLKFBOUT") {
+            used = true;
+        } else {
+            used = ci->getPort(ctx->id(name)) != nullptr;
+        }
+        if (name == "DIVCLK") {
+            write_int_vector("DIVCLK_DIVCLK_HIGH_TIME[5:0]", high, 6);
+            write_int_vector("DIVCLK_DIVCLK_LOW_TIME[5:0]", low, 6);
+            write_bit("DIVCLK_DIVCLK_EDGE[0]", edge);
+            write_bit("DIVCLK_DIVCLK_NO_COUNT[0]", no_count);
+        } else if (used) {
+            write_bit(name + "_CLKOUT1_OUTPUT_ENABLE[0]");
+            write_int_vector(name + "_CLKOUT1_HIGH_TIME[5:0]", high, 6);
+            write_int_vector(name + "_CLKOUT1_LOW_TIME[5:0]", low, 6);
+            write_int_vector(name + "_CLKOUT1_PHASE_MUX[2:0]", phasemux, 3);
+            write_bit(name + "_CLKOUT2_EDGE[0]", edge);
+            write_bit(name + "_CLKOUT2_NO_COUNT[0]", no_count);
+            write_int_vector(name + "_CLKOUT2_DELAY_TIME[5:0]", delaytime, 6);
+            if (frac != 0) {
+                write_bit(name + "_CLKOUT2_FRAC_EN[0]", edge);
+                write_int_vector(name + "_CLKOUT2_FRAC[2:0]", frac, 3);
+            }
+        }
+    }
+
+    void write_pll(CellInfo *ci)
+    {
+        push(uarch->tile_name(ci->bel.tile));
+        push("PLLE2_ADV");
+        write_bit("IN_USE");
+        // FIXME: should be INV not ZINV (XRay error?)
+        write_bit("ZINV_PWRDWN", bool_or_default(ci->params, id_IS_PWRDWN_INVERTED, false));
+        write_bit("ZINV_RST", bool_or_default(ci->params, id_IS_RST_INVERTED, false));
+        write_bit("INV_CLKINSEL", bool_or_default(ci->params, id_IS_CLKINSEL_INVERTED, false));
+        write_pll_clkout("DIVCLK", ci);
+        write_pll_clkout("CLKFBOUT", ci);
+        write_pll_clkout("CLKOUT0", ci);
+        write_pll_clkout("CLKOUT1", ci);
+        write_pll_clkout("CLKOUT2", ci);
+        write_pll_clkout("CLKOUT3", ci);
+        write_pll_clkout("CLKOUT4", ci);
+        write_pll_clkout("CLKOUT5", ci);
+
+        std::string comp = str_or_default(ci->params, id_COMPENSATION, "INTERNAL");
+        push("COMPENSATION");
+        if (comp == "INTERNAL") {
+            // write_bit("INTERNAL");
+            write_bit("Z_ZHOLD_OR_CLKIN_BUF");
+        } else {
+            NPNR_ASSERT_FALSE("unsupported compensation type");
+        }
+        pop();
+
+        // FIXME: should these be calculated somehow?
+        write_int_vector("FILTREG1_RESERVED[11:0]", 0x8, 12);
+        write_int_vector("LKTABLE[39:0]", 0xB5BE8FA401ULL, 40);
+        write_bit("LOCKREG3_RESERVED[0]");
+        write_int_vector("TABLE[9:0]", 0x3B4, 10);
+        pop(2);
+    }
+
+    void write_dsp_cell(CellInfo *ci)
+    {
+        auto tile_name = uarch->tile_name(ci->bel.tile);
+        auto tile_side = tile_name.at(4);
+        push(tile_name);
+        push("DSP48");
+        auto xy = uarch->rel_site_loc(uarch->get_bel_site(ci->bel));
+        auto dsp = stringf("DSP_%d", xy.y);
+        push(dsp);
+
+        auto write_bus_zinv = [&](std::string name, int width) {
+            for (int i = 0; i < width; i++) {
+                std::string b = stringf("[%d]", i);
+                bool inv = (int_or_default(ci->params, ctx->id("IS_" + name + "_INVERTED"), 0) >> i) & 0x1;
+                inv |= bool_or_default(ci->params, ctx->id("IS_" + name + b + "_INVERTED"), false);
+                write_bit("ZIS_" + name + "_INVERTED" + b, !inv);
+            }
+        };
+
+        // value 1 is equivalent to 2, according to UG479
+        // but in real life, Vivado sets AREG_0 is 0,
+        // no bit is 1, and AREG_2 is 2
+        auto areg = int_or_default(ci->params, ctx->id("AREG"), 1);
+        if (areg == 0 or areg == 2)
+            write_bit("AREG_" + std::to_string(areg));
+
+        auto ainput = str_or_default(ci->params, ctx->id("A_INPUT"), "DIRECT");
+        if (ainput == "CASCADE")
+            write_bit("A_INPUT[0]");
+
+        // value 1 is equivalent to 2, according to UG479
+        // but in real life, Vivado sets AREG_0 is 0,
+        // no bit is 1, and AREG_2 is 2
+        auto breg = int_or_default(ci->params, ctx->id("BREG"), 1);
+        if (breg == 0 or breg == 2)
+            write_bit("BREG_" + std::to_string(breg));
+
+        auto binput = str_or_default(ci->params, ctx->id("B_INPUT"), "DIRECT");
+        if (binput == "CASCADE")
+            write_bit("B_INPUT[0]");
+
+        auto use_dport = str_or_default(ci->params, ctx->id("USE_DPORT"), "FALSE");
+        if (use_dport == "TRUE")
+            write_bit("USE_DPORT[0]");
+
+        auto use_simd = str_or_default(ci->params, ctx->id("USE_SIMD"), "ONE48");
+        if (use_simd == "TWO24")
+            write_bit("USE_SIMD_FOUR12_TWO24");
+        if (use_simd == "FOUR12")
+            write_bit("USE_SIMD_FOUR12");
+
+        // PATTERN
+        auto pattern_str = str_or_default(ci->params, ctx->id("PATTERN"), "");
+        if (!boost::empty(pattern_str)) {
+            const size_t pattern_size = 48;
+            std::vector<bool> pattern_vector(pattern_size, true);
+            size_t i = 0;
+            for (auto it = pattern_str.crbegin(); it != pattern_str.crend() && i < pattern_size; ++i, ++it) {
+                pattern_vector[i] = *it == '1';
+            }
+            write_vector("PATTERN[47:0]", pattern_vector);
+        }
+
+        auto autoreset_patdet = str_or_default(ci->params, ctx->id("AUTORESET_PATDET"), "NO_RESET");
+        if (autoreset_patdet == "RESET_MATCH")
+            write_bit("AUTORESET_PATDET_RESET");
+        if (autoreset_patdet == "RESET_NOT_MATCH")
+            write_bit("AUTORESET_PATDET_RESET_NOT_MATCH");
+
+        // MASK
+        auto mask_str = str_or_default(ci->params, ctx->id("MASK"), "001111111111111111111111111111111111111111111111");
+        // Yosys gives us 48 bit, but prjxray only recognizes 46 bits
+        // The most significant two bits seem to be zero, so let us just truncate them
+        const size_t mask_size = 46;
+        std::vector<bool> mask_vector(mask_size, true);
+        size_t i = 0;
+        for (auto it = mask_str.crbegin(); it != mask_str.crend() && i < mask_size; ++i, ++it) {
+            mask_vector[i] = *it == '1';
+        }
+        write_vector("MASK[45:0]", mask_vector);
+
+        auto sel_mask = str_or_default(ci->params, ctx->id("SEL_MASK"), "MASK");
+        if (sel_mask == "C")
+            write_bit("SEL_MASK_C");
+        if (sel_mask == "ROUNDING_MODE1")
+            write_bit("SEL_MASK_ROUNDING_MODE1");
+        if (sel_mask == "ROUNDING_MODE2")
+            write_bit("SEL_MASK_ROUNDING_MODE2");
+
+        write_bit("ZADREG[0]", !bool_or_default(ci->params, ctx->id("ADREG"), true));
+        write_bit("ZALUMODEREG[0]", !bool_or_default(ci->params, ctx->id("ALUMODEREG")));
+        write_bit("ZAREG_2_ACASCREG_1", !bool_or_default(ci->params, ctx->id("ACASCREG")));
+        write_bit("ZBREG_2_BCASCREG_1", !bool_or_default(ci->params, ctx->id("BCASCREG")));
+        write_bit("ZCARRYINREG[0]", !bool_or_default(ci->params, ctx->id("CARRYINREG")));
+        write_bit("ZCARRYINSELREG[0]", !bool_or_default(ci->params, ctx->id("CARRYINSELREG")));
+        write_bit("ZCREG[0]", !bool_or_default(ci->params, ctx->id("CREG"), true));
+        write_bit("ZDREG[0]", !bool_or_default(ci->params, ctx->id("DREG"), true));
+        write_bit("ZINMODEREG[0]", !bool_or_default(ci->params, ctx->id("INMODEREG")));
+        write_bus_zinv("ALUMODE", 4);
+        write_bus_zinv("INMODE", 5);
+        write_bus_zinv("OPMODE", 7);
+        write_bit("ZMREG[0]", !bool_or_default(ci->params, ctx->id("MREG")));
+        write_bit("ZOPMODEREG[0]", !bool_or_default(ci->params, ctx->id("OPMODEREG")));
+        write_bit("ZPREG[0]", !bool_or_default(ci->params, ctx->id("PREG")));
+        write_bit("USE_DPORT[0]", str_or_default(ci->params, ctx->id("USE_DPORT"), "FALSE") == "TRUE");
+        write_bit("ZIS_CLK_INVERTED", !bool_or_default(ci->params, ctx->id("IS_CLK_INVERTED")));
+        write_bit("ZIS_CARRYIN_INVERTED", !bool_or_default(ci->params, ctx->id("IS_CARRYIN_INVERTED")));
+        pop(2);
+
+        auto write_const_pins = [&](std::string const_net_name) {
+            std::vector<std::string> pins;
+            const auto attr_name = "DSP_" + const_net_name + "_PINS";
+            const auto attr_value = str_or_default(ci->attrs, ctx->id(attr_name), "");
+            boost::split(pins, attr_value, boost::is_any_of(" "));
+            for (auto pin : pins) {
+                if (boost::empty(pin))
+                    continue;
+                auto pin_basename = pin;
+                boost::erase_all(pin_basename, "0123456789");
+                auto inv = bool_or_default(ci->params, ctx->id("IS_" + pin_basename + "_INVERTED"), 0);
+                auto net_name = inv ? (const_net_name == "GND" ? "VCC" : "GND") : const_net_name;
+                write_bit(stringf("%s_%s.DSP_%s_%c", dsp.c_str(), pin.c_str(), net_name.c_str(), tile_side));
+            }
+        };
+
+        write_const_pins("GND");
+        write_const_pins("VCC");
+
+        pop();
+    }
+
+    void write_ip()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (ci->type == id_DSP48E1_DSP48E1) {
+                write_dsp_cell(ci);
+                blank();
+            }
+        }
+    }
+
+    void write_fasm()
+    {
+        get_invertible_pins(ctx, invertible_pins);
+        write_logic();
+        write_io();
+        write_routing();
+        write_bram();
+        write_clocking();
+        write_ip();
+    }
+};
+
+} // namespace
+
+void XilinxImpl::write_fasm(const std::string &filename)
+{
+    std::ofstream out(filename);
+    if (!out)
+        log_error("failed to open file %s for writing (%s)\n", filename.c_str(), strerror(errno));
+
+    FasmBackend be(this->ctx, this, out);
+    be.write_fasm();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/gen/filters.py b/himbaechel/uarch/xilinx/gen/filters.py
new file mode 100644
index 0000000000..ba74546d17
--- /dev/null
+++ b/himbaechel/uarch/xilinx/gen/filters.py
@@ -0,0 +1,106 @@
+# Mapping rules from prjxray to nextpnr
+
+def get_bel_z_override(bel, default_z):
+    s = bel.site
+    t = s.tile
+    bt = bel.bel_type()
+    bn = bel.name()
+    if t.tile_type() == "BRAM_L" or t.tile_type() == "BRAM_R":
+        is_top18 = (s.primary.site_type() == "RAMB18E1")
+        if bt == "RAMBFIFO36E1_RAMBFIFO36E1":
+            return 0
+        elif bt == "RAMB36E1_RAMB36E1":
+            return 1
+        elif bt == "FIFO36E1_FIFO36E1":
+            return 2
+        elif bt == "RAMB18E1_RAMB18E1":
+            return (5 if is_top18 else 9)
+        elif bt == "FIFO18E1_FIFO18E1":
+            return 10
+    if s.site_type() == "SLICEL" or s.site_type() == "SLICEM":
+        is_upper_site = (s.rel_xy()[0] == 1)
+        subslices = "ABCD"
+        postfixes = ["6LUT", "5LUT", "FF", "5FF"]
+        for i, pf in enumerate(postfixes):
+            if len(bn) == len(pf) + 1 and bn[1:] == pf:
+                return (64 if is_upper_site else 0) | (subslices.index(bn[0]) << 4) | i
+        if bn == "F7AMUX":
+            return (0x47 if is_upper_site else 0x07)
+        elif bn == "F7BMUX":
+            return (0x67 if is_upper_site else 0x27)
+        elif bn == "F8MUX":
+            return (0x48 if is_upper_site else 0x08)
+        elif bn == "CARRY4":
+            return (0x4F if is_upper_site else 0x0F)
+        # Other bels (e.g. extra xc7 routing bels) can be ignored for nextpnr porpoises
+        return -1
+    return default_z
+
+def get_bel_type_override(bt):
+    if bt.endswith("6LUT") or bt == "LUT_OR_MEM6" or bt == "LUT6":
+        return "SLICE_LUTX"
+    elif bt.endswith("5LUT") or bt == "LUT_OR_MEM5" or bt == "LUT5":
+        return "SLICE_LUTX"
+    elif len(bt) == 4 and bt.endswith("FF2"):
+        return "SLICE_FFX"
+    elif len(bt) == 3 and bt.endswith("FF"):
+        return "SLICE_FFX"
+    elif bt == "FF_INIT" or bt == "REG_INIT":
+        return "SLICE_FFX"
+
+    iolParts = ["COMBUF_", "IDDR_", "IPFF_", "OPFF_", "OPTFF_", "TFF_"]
+    for p in iolParts:
+        if bt.startswith(p):
+            return "IOL_" + p.replace("_", "")
+    if bt.endswith("_VREF"):
+        return "IOB_VREF"
+    elif bt.endswith("_DIFFINBUF"):
+        return "IOB_DIFFINBUF"
+    elif bt.startswith("PSS_ALTO_CORE_PAD_"):
+        return "PSS_PAD"
+    elif bt.startswith("LAGUNA_RX_REG") or bt.startswith("LAGUNA_TX_REG"):
+        return "LAGUNA_REGX"
+    elif bt.startswith("BSCAN"):
+        return "BSCAN"
+    elif bt == "BUFGCTRL_BUFGCTRL":
+        return "BUFGCTRL"
+    elif bt == "RAMB18E2_U_RAMB18E2" or bt == "RAMB18E2_L_RAMB18E2":
+        return "RAMB18E2_RAMB18E2"
+    else:
+        return bt
+
+def include_pip(tile_type, p):
+    is_xc7_logic = (tile_type in ("CLBLL_L", "CLBLL_R", "CLBLM_L", "CLBLM_R"))
+    if p.is_route_thru() and p.src_wire().name().endswith("_CE_INT"):
+        return False
+    if p.is_route_thru() and is_xc7_logic:
+        return False
+    if p.is_route_thru() and "TFB" in p.dst_wire().name():
+        return False
+    if p.src_wire().name().startswith("CLK_BUFG_R_FBG_OUT"):
+        return False
+    if "CLK_HROW_CK_INT" in p.src_wire().name():
+        return False
+    if tile_type.startswith("HCLK_CMT") and "FREQ_REF" in p.dst_wire().name():
+        return False
+    if tile_type.startswith("CMT_TOP_L_LOWER"):
+        return False
+    if tile_type.startswith("CLK_HROW_TOP"):
+        if "CK_BUFG_CASCO" in p.dst_wire().name() and "CK_BUFG_CASCIN" in p.src_wire().name():
+            return False
+    if tile_type.startswith("HCLK_IOI"):
+        if "RCLK_BEFORE_DIV" in p.dst_wire().name() and "IMUX" in p.src_wire().name():
+            return False
+    if "IOI" in tile_type:
+        if "CLKB" in p.dst_wire().name() and "IMUX22" in p.src_wire().name():
+            return False
+        if "OCLKB" in p.dst_wire().name() and "IOI_OCLK_" in p.src_wire().name():
+            return False
+        if "OCLKM" in p.dst_wire().name() and "IMUX31" in p.src_wire().name():
+            return False
+    if "CMT_TOP_R" in tile_type:
+        if "PLLOUT_CLK_FREQ_BB_REBUFOUT" in p.dst_wire().name():
+            return False
+        if "MMCM_CLK_FREQ_BB" in p.dst_wire().name():
+            return False
+    return True
\ No newline at end of file
diff --git a/himbaechel/uarch/xilinx/gen/parse_sdf.py b/himbaechel/uarch/xilinx/gen/parse_sdf.py
new file mode 100644
index 0000000000..2eea49ecda
--- /dev/null
+++ b/himbaechel/uarch/xilinx/gen/parse_sdf.py
@@ -0,0 +1,134 @@
+"""
+Utilities for SDF file parsing to determine cell timings
+"""
+import sys
+
+
+class SDFData:
+    def __init__(self):
+        self.cells = {}
+
+class Delay:
+    def __init__(self, minv, typv, maxv):
+        self.minv = minv
+        self.typv = typv
+        self.maxv = maxv
+
+
+class IOPath:
+    def __init__(self, from_pin, to_pin, rising, falling):
+        self.from_pin = from_pin
+        self.to_pin = to_pin
+        self.rising = rising
+        self.falling = falling
+
+
+class SetupHoldCheck:
+    def __init__(self, pin, clock, setup, hold):
+        self.pin = pin
+        self.clock = clock
+        self.setup = setup
+        self.hold = hold
+
+
+class WidthCheck:
+    def __init__(self, clock, width):
+        self.clock = clock
+        self.width = width
+
+
+class Interconnect:
+    def __init__(self, from_net, to_net, rising, falling):
+        self.from_net = from_net
+        self.to_net = to_net
+        self.rising = rising
+        self.falling = falling
+
+
+class CellData:
+    def __init__(self, celltype, inst):
+        self.type = celltype
+        self.inst = inst
+        self.entries = []
+        self.interconnect = {}
+
+
+def parse_sexpr(stream):
+    content = []
+    buffer = ""
+    instr = False
+    while True:
+        c = stream.read(1)
+        assert c != "", "unexpected end of file"
+        if instr:
+            if c == '"':
+                instr = False
+            else:
+                buffer += c
+        else:
+            if c == '(':
+                content.append(parse_sexpr(stream))
+            elif c == ')':
+                if buffer != "":
+                    content.append(buffer)
+                return content
+            elif c.isspace():
+                if buffer != "":
+                    content.append(buffer)
+                buffer = ""
+            elif c == '"':
+                instr = True
+            else:
+                buffer += c
+
+
+def parse_sexpr_file(filename):
+    with open(filename, 'r') as f:
+        c = f.read(1)
+        while c != '(':
+            assert c == ' ' or c == '\n' or c == '\t'
+            c = f.read(1)
+        return parse_sexpr(f)
+
+
+def parse_delay(delay):
+    sp = [float(x) if x != '' else None for x in delay.split(":")]
+    assert len(sp) == 3
+    return Delay(sp[0], sp[1], sp[2])
+
+
+def parse_sdf_file(filename):
+    sdata = parse_sexpr_file(filename)
+    assert sdata[0] == "DELAYFILE"
+    sdf = SDFData()
+    for entry in sdata[1:]:
+        if entry[0] != "CELL":
+            continue
+        assert entry[1][0] == "CELLTYPE"
+        celltype = entry[1][1]
+        assert entry[2][0] == "INSTANCE"
+        if len(entry[2]) > 1:
+            inst = entry[2][1]
+        else:
+            inst = "top"
+        cell = CellData(celltype, inst)
+        for subentry in entry[3:]:
+            if subentry[0] == "DELAY":
+                assert subentry[1][0] == "ABSOLUTE"
+                for delay in subentry[1][1:]:
+                    if delay[0] == "IOPATH":
+                        cell.entries.append(
+                            IOPath(delay[1], delay[2], parse_delay(delay[3][0]), parse_delay(delay[4][0])))
+                    elif delay[0] == "INTERCONNECT":
+                        cell.interconnect[(delay[1], delay[2])] = Interconnect(delay[1], delay[2],
+                                                                               parse_delay(delay[3][0]),
+                                                                               parse_delay(delay[4][0]))
+            elif subentry[0] == "TIMINGCHECK":
+                for check in subentry[1:]:
+                    if check[0] == "SETUPHOLD":
+                        cell.entries.append(
+                            SetupHoldCheck(check[1], check[2], parse_delay(check[3][0]), parse_delay(check[4][0])))
+                    elif check[0] == "WIDTH":
+                        cell.entries.append(WidthCheck(check[1], parse_delay(check[2][0])))
+        sdf.cells[(celltype, inst)] = cell
+    return sdf
diff --git a/himbaechel/uarch/xilinx/gen/tileconn.py b/himbaechel/uarch/xilinx/gen/tileconn.py
new file mode 100644
index 0000000000..2b1c7d147c
--- /dev/null
+++ b/himbaechel/uarch/xilinx/gen/tileconn.py
@@ -0,0 +1,38 @@
+import json
+
+def apply_tileconn(f, d):
+    def merge_nodes(a, b):
+        for bwire in b.wires:
+            bwire.tile.wire_to_node[bwire.index] = a
+            a.wires.append(bwire)
+        b.wires = []
+
+    tj = json.load(f)
+    # Restructure to tiletype -> coord offset -> type -> wire_pairs
+    ttn = {}
+    for entry in tj:
+        tile0, tile1 = entry["tile_types"]
+        dx, dy = entry["grid_deltas"]
+        if tile0 not in ttn:
+            ttn[tile0] = {}
+        if (dx, dy) not in ttn[tile0]:
+            ttn[tile0][dx, dy] = {}
+        ttn[tile0][dx, dy][tile1] = entry["wire_pairs"]
+    for tile in d.tiles:
+        tt = tile.tile_type()
+        if tt not in ttn:
+            continue
+        # Search the neighborhood around a tile
+        for dxy, nd in sorted(ttn[tt].items()):
+            nx = tile.x + dxy[0]
+            ny = tile.y + dxy[1]
+            if (nx, ny) not in d.tiles_by_xy:
+                continue
+            ntile = d.tiles_by_xy[nx, ny]
+            ntt = ntile.tile_type()
+            if ntt not in nd:
+                continue
+            # Found a pair with connections
+            wc = nd[ntt]
+            for wirea, wireb in wc:
+                merge_nodes(tile.wire(wirea).node(), ntile.wire(wireb).node())
diff --git a/himbaechel/uarch/xilinx/gen/xilinx_device.py b/himbaechel/uarch/xilinx/gen/xilinx_device.py
new file mode 100644
index 0000000000..fc61ba89a4
--- /dev/null
+++ b/himbaechel/uarch/xilinx/gen/xilinx_device.py
@@ -0,0 +1,544 @@
+import json
+import os
+import re
+from enum import Enum
+from tileconn import apply_tileconn
+from parse_sdf import parse_sdf_file
+from dataclasses import dataclass
+from typing import Optional
+# Represents Xilinx device data from PrjXray etc
+
+@dataclass
+class WireData:
+    index: int
+    name: str
+    intent: str = ""
+    tied_value: Optional[int] = None
+    resistance: float = 0
+    capacitance: float = 0
+
+@dataclass
+class PIPData:
+    index: int
+    from_wire: int
+    to_wire: int
+    is_bidi: bool = False
+    is_route_thru: bool = False
+    is_buffered: bool = False
+    min_delay: float = 0
+    max_delay: float = 0
+    resistance: float = 0
+    capacitance: float = 0
+
+@dataclass
+class SiteWireData:
+    name: str
+    is_pin: bool = False
+
+@dataclass
+class SiteBELPinData:
+    name: str
+    pindir: str
+    site_wire_idx: int
+
+@dataclass
+class SiteBELData:
+    name: str
+    bel_type: str
+    bel_class: str
+    pins: list[SiteBELPinData]
+
+@dataclass
+class SitePIPData:
+    bel_idx: int
+    bel_input: str
+    from_wire_idx: int
+    to_wire_idx: int
+
+@dataclass
+class SitePinData:
+    name: str
+    pindir: str
+    site_wire_idx: int
+    prim_pin_name: str
+
+class SiteData:
+    def __init__(self, site_type):
+        self.site_type = site_type
+        self.wires = []
+        self.bels = []
+        self.pips = []
+        self.pins = []
+        self.variants = {}
+
+class TileSitePinData:
+    def __init__(self, wire_idx):
+        self.wire_idx = wire_idx
+        self.min_delay = 0
+        self.max_delay = 0
+        self.resistance = 0
+        self.capacitance = 0
+
+class TileData:
+    def __init__(self, tile_type):
+        self.tile_type = tile_type
+        self.wires = []
+        self.wires_by_name = {}
+        self.pips = []
+        self.sitepin_data = {} # (type, relxy, pin) -> TileSitePinData
+        self.cell_timing = None
+
+class PIP:
+    def __init__(self, tile, index):
+        self.tile = tile
+        self.index = index
+        self.data = tile.get_pip_data(index)
+    def src_wire(self):
+        return Wire(self.tile, self.data.from_wire)
+    def dst_wire(self):
+        return Wire(self.tile, self.data.to_wire)
+    def is_route_thru(self):
+        return self.data.is_route_thru
+    def is_bidi(self):
+        return self.data.is_bidi
+    def is_buffered(self):
+        return self.data.is_buffered
+    def min_delay(self):
+        return self.data.min_delay
+    def max_delay(self):
+        return self.data.max_delay
+    def resistance(self):
+        return self.data.resistance
+    def capacitance(self):
+        return self.data.capacitance
+
+class Wire:
+    def __init__(self, tile, index):
+        self.tile = tile
+        self.index = index
+        self.data = tile.get_wire_data(index)
+    def name(self):
+        return self.data.name
+    def intent(self):
+        return self.data.intent
+    def node(self):
+        if self.index not in self.tile.wire_to_node:
+            self.tile.wire_to_node[self.index] = Node(self.tile, [self])
+        return self.tile.wire_to_node[self.index]
+    def is_gnd(self):
+        return "GND_WIRE" in self.name()
+    def is_vcc(self):
+        return "VCC_WIRE" in self.name()
+    def resistance(self):
+        return self.data.resistance
+    def capacitance(self):
+        return self.data.capacitance
+
+class SiteWire:
+    def __init__(self, site, index):
+        self.site = site
+        self.index = index
+        self.data = self.site.get_wire_data(index)
+    def name(self):
+        return self.data.name
+
+class SiteBELPin:
+    def __init__(self, bel, name):
+        self.bel = bel
+        self.name = name
+        self.data = self.bel.data.pins[name]
+    def name(self):
+        return self.name
+    def dir(self):
+        return self.data.pindir
+    def site_wire(self):
+        return SiteWire(self.bel.site, self.data.site_wire_idx)
+
+class SiteBEL:
+    def __init__(self, site, index):
+        self.site = site
+        self.index = index
+        self.data = site.get_bel_data(index)
+    def name(self):
+        return self.data.name
+    def bel_type(self):
+        return self.data.bel_type
+    def bel_class(self):
+        return self.data.bel_class
+    def pins(self):
+        return (SiteBELPin(self, n) for n in self.data.pins.keys())
+
+class SitePIP:
+    def __init__(self, site, index):
+        self.site = site
+        self.index = index
+        self.data = site.get_pip_data(index)
+    def bel(self):
+        return SiteBEL(self.site, self.data.bel_idx)
+    def bel_input(self):
+        return self.data.bel_input
+    def src_wire(self):
+        return SiteWire(self.site, self.data.from_wire_idx)
+    def dst_wire(self):
+        return SiteWire(self.site, self.data.to_wire_idx)
+
+class SitePin:
+    def __init__(self, site, index):
+        self.site = site
+        self.index = index
+        self.data = site.data.pins[index]
+    def name(self):
+        return self.data.name
+    def dir(self):
+        return self.data.pindir
+    def site_wire(self):
+        return SiteWire(self.site, self.data.site_wire_idx)
+    def tile_wire(self):
+        return self.site.tile.site_pin_wire(self.site.primary.site_type(), self.site.rel_xy(), self.data.prim_pin_name)
+    def min_delay(self):
+        return self.site.tile.site_pin_timing(self.site.primary.site_type(), self.site.rel_xy(), self.data.prim_pin_name).min_delay
+    def max_delay(self):
+        return self.site.tile.site_pin_timing(self.site.primary.site_type(), self.site.rel_xy(), self.data.prim_pin_name).max_delay
+    def resistance(self):
+        return self.site.tile.site_pin_timing(self.site.primary.site_type(), self.site.rel_xy(), self.data.prim_pin_name).resistance
+    def capacitance(self):
+        return self.site.tile.site_pin_timing(self.site.primary.site_type(), self.site.rel_xy(), self.data.prim_pin_name).capacitance
+
+class Site:
+    def __init__(self, tile, name, index, grid_xy, data, primary=None):
+        self.tile = tile
+        self.name = name
+        self.index = index
+        self.prefix = name[0:name.rfind('_')]
+        self.grid_xy = grid_xy
+        self.data = data
+        self.primary = primary if primary is not None else self
+        self._rel_xy = None # filled later
+        self._variants = None #filled later
+    def get_bel_data(self, index):
+        return self.data.bels[index]
+    def get_wire_data(self, index):
+        return self.data.wires[index]
+    def get_pip_data(self, index):
+        return self.data.pips[index]
+    def site_type(self):
+        return self.data.site_type
+    def rel_xy(self):
+        if self._rel_xy is None:
+            base_x = 999999
+            base_y = 999999
+            for site in self.tile.sites():
+                if site.prefix != self.prefix:
+                    continue
+                base_x = min(base_x, site.grid_xy[0])
+                base_y = min(base_y, site.grid_xy[1])
+            self._rel_xy = (self.grid_xy[0] - base_x, self.grid_xy[1] - base_y)
+        return self._rel_xy
+    def bels(self):
+        return (SiteBEL(self, i) for i in range(len(self.data.bels)))
+    def wires(self):
+        return (SiteWire(self, i) for i in range(len(self.data.wires)))
+    def pips(self):
+        return (SitePIP(self, i) for i in range(len(self.data.pips)))
+    def pins(self):
+        return (SitePin(self, i) for i in range(len(self.data.pins)))
+    def pin(self, p):
+        for i in range(len(self.data.pins)):
+            if self.data.pins[i].name == p:
+                return SitePin(self, i)
+        return None
+    def available_variants(self):
+        # Make sure primary type is first
+        if self._variants is None:
+            self._variants = []
+            self._variants.append(self.site_type())
+            for var in sorted(self.data.variants.keys()):
+                if var != self.site_type():
+                    self._variants.append(var)
+        return self._variants
+    def variant(self, vtype):
+        vsite = Site(self.tile, self.name, self.index, self.grid_xy, self.data.variants[vtype], self)
+        return vsite
+    def rel_name(self):
+        x, y = self.rel_xy()
+        return f"{self.prefix}_X{x}Y{y}"
+
+class Tile:
+    def __init__(self, x, y, name, data, interconn_xy, site_insts):
+        self.x = x
+        self.y = y
+        self.name = name
+        self.data = data
+        self.interconn_xy = interconn_xy
+        self.site_insts = site_insts
+        self.wire_to_node = {}
+        self.node_autoidx = 0
+        self.used_wires = None
+    def get_pip_data(self, i):
+        return self.data.pips[i]
+    def get_wire_data(self, i):
+        return self.data.wires[i]
+    def tile_type(self):
+        return self.data.tile_type
+    def wires(self):
+        return (Wire(self, i) for i in range(len(self.data.wires)))
+    def wire(self, name):
+        return Wire(self, self.data.wires_by_name[name].index)
+    def pips(self):
+        return (PIP(self, i) for i in range(len(self.data.pips)))
+    def sites(self):
+        return self.site_insts
+    def site_pin_wire(self, sitetype, rel_xy, pin):
+        wire_idx = self.data.sitepin_data[(sitetype, rel_xy, pin)].wire_idx
+        return Wire(self, wire_idx) if wire_idx is not None else None
+    def site_pin_timing(self, sitetype, rel_xy, pin):
+        return self.data.sitepin_data[(sitetype, rel_xy, pin)]
+    def cell_timing(self):
+        return self.data.cell_timing
+    def used_wire_indices(self):
+        if self.used_wires is None:
+            self.used_wires = set()
+            for pip in self.pips():
+                self.used_wires.add(pip.src_wire().index)
+                self.used_wires.add(pip.dst_wire().index)
+            for site in self.sites():
+                for v in site.available_variants():
+                    variant = site.variant(v)
+                    for pin in variant.pins():
+                        if pin.tile_wire() is not None:
+                            self.used_wires.add(pin.tile_wire().index)
+        return self.used_wires
+    def split_name(self):
+        prefix, xy = self.name.rsplit("_", 1)
+        xy_m = re.match(r"X(\d+)Y(\d+)", xy)
+        return prefix, int(xy_m.group(1)), int(xy_m.group(2))
+
+class Node:
+    def __init__(self, tile, wires=[]):
+        self.tile = tile
+        self.index = tile.node_autoidx
+        tile.node_autoidx += 1
+        self.wires = wires
+    def unique_index(self):
+        return (self.tile.y << 48) | (self.tile.x << 32) | self.index
+    def is_vcc(self):
+        for wire in self.wires:
+            if wire.is_vcc():
+                return True
+        return False
+    def is_gnd(self):
+        for wire in self.wires:
+            if wire.is_gnd():
+                return True
+        return False
+
+class Package:
+    def __init__(self, name):
+        self.name = name
+        self.pin_map = {}
+
+class Device:
+    def __init__(self, name):
+        self.name = name
+        self.tiles = []
+        self.tiles_by_name = {}
+        self.tiles_by_xy = {}
+        self.sites_by_name = {}
+        self.width = 0
+        self.height = 0
+        self.packages = {}
+    def tile(self, name):
+        return self.tiles_by_name[name]
+    def site(self, name):
+        return self.sites_by_name[name]
+
+def import_device(fabricname, prjxray_root, metadata_root):
+    site_type_cache = {}
+    tile_type_cache = {}
+    tile_json_cache = {}
+    def parse_xy(xy):
+        xpos = xy.rfind("X")
+        ypos = xy.rfind("Y")
+        return int(xy[xpos+1:ypos]), int(xy[ypos+1:])
+
+    def get_site_type_data(sitetype):
+        if sitetype not in site_type_cache:
+            sd = SiteData(sitetype)
+            sp = metadata_root + "/site_type_" + sitetype + ".json"
+            if os.path.exists(sp):
+                with open(sp, "r") as jf:
+                    sj = json.load(jf)
+                for vtype, vdata in sorted(sj.items()): # Consider all site variants
+                    if vtype == sitetype:
+                        vd = sd # primary variant
+                    else:
+                        vd = SiteData(vtype)
+                    site_wire_by_name = {}
+                    def wire_index(name):
+                        if name not in site_wire_by_name:
+                            idx = len(vd.wires)
+                            vd.wires.append(SiteWireData(name=name))
+                            site_wire_by_name[name] = idx
+                        return site_wire_by_name[name]
+                    # Import bels
+                    bel_idx_by_name = {}
+                    for bel, beldata in sorted(vdata["bels"].items()):
+                        belpins = {}
+                        for pin, pindata in sorted(beldata["pins"].items()):
+                            belpins[pin] = SiteBELPinData(name=pin, pindir=pindata["dir"], site_wire_idx=wire_index(pindata["wire"]))
+                        bd = SiteBELData(name=bel, bel_type=beldata["type"], bel_class=beldata["class"], pins=belpins)
+                        bel_idx_by_name[bel] = len(vd.bels)
+                        vd.bels.append(bd)
+                    # Import pips
+                    for pipdata in vdata["pips"]:
+                        bel_idx = bel_idx_by_name[pipdata["bel"]]
+                        bel_data = vd.bels[bel_idx]
+                        vd.pips.append(SitePIPData(bel_idx=bel_idx_by_name[pipdata["bel"]], bel_input=pipdata["from_pin"],
+                            from_wire_idx=bel_data.pins[pipdata["from_pin"]].site_wire_idx,
+                            to_wire_idx=bel_data.pins[pipdata["to_pin"]].site_wire_idx))
+                    # Import pins
+                    for pin, pindata in sorted(vdata["pins"].items()):
+                        vd.pins.append(SitePinData(name=pin, pindir=pindata["dir"], site_wire_idx=wire_index(pindata["wire"]),
+                            prim_pin_name=pindata["primary"]))
+                    sd.variants[vtype] = vd
+            else:
+                sd.variants[sitetype] = sd
+            site_type_cache[sitetype] = sd
+        return site_type_cache[sitetype]
+
+    def read_tile_type_json(tiletype):
+        if tiletype not in tile_json_cache:
+            if not os.path.exists(prjxray_root + "/tile_type_" + tiletype + ".json"):
+                tile_json_cache[tiletype] = dict(wires={}, pips={}, sites=[])
+            else:
+                with open(prjxray_root + "/tile_type_" + tiletype + ".json", "r") as jf:
+                    tile_json_cache[tiletype] = json.load(jf)
+        return tile_json_cache[tiletype]
+
+    def get_tile_type_data(tiletype):
+        if tiletype not in tile_type_cache:
+            td = TileData(tiletype)
+            # Import wires and pips
+            tj = read_tile_type_json(tiletype)
+            for wire, wire_data in sorted(tj["wires"].items()):
+                wire_id = len(td.wires)
+                wd = WireData(index=wire_id, name=wire, tied_value=None) # FIXME: tied_value
+                wd.intent = get_wire_intent(tiletype, wire)
+                if wire_data is not None:
+                    if "res" in wire_data:
+                        wd.resistance = float(wire_data["res"])
+                    if "cap" in wire_data:
+                        wd.capacitance = float(wire_data["cap"])
+                td.wires.append(wd)
+                td.wires_by_name[wire] = wd
+            for pip, pipdata in sorted(tj["pips"].items()):
+                # FIXME: pip/wire delays
+                pip_id = len(td.pips)
+                pd = PIPData(index=pip_id,
+                    from_wire=td.wires_by_name[pipdata["src_wire"]].index, to_wire=td.wires_by_name[pipdata["dst_wire"]].index,
+                    is_bidi=(not bool(int(pipdata["is_directional"]))), is_route_thru=bool(int(pipdata["is_pseudo"])))
+                if "is_pass_transistor" in pipdata:
+                    pd.is_buffered = (not bool(int(pipdata["is_pass_transistor"])))
+                if "src_to_dst" in pipdata:
+                    s2d = pipdata["src_to_dst"]
+                    if "delay" in s2d and s2d["delay"] is not None:
+                        pd.min_delay = min(float(s2d["delay"][0]), float(s2d["delay"][1]))
+                        pd.max_delay = max(float(s2d["delay"][2]), float(s2d["delay"][3]))
+                    if "res" in s2d and s2d["res"] is not None:
+                        pd.resistance = float(s2d["res"])
+                    if "in_cap" in s2d and s2d["in_cap"] is not None:
+                        pd.capacitance = float(s2d["in_cap"])
+                td.pips.append(pd)
+            for sitedata in tj["sites"]:
+                rel_xy = parse_xy(sitedata["name"])
+                sitetype = sitedata["type"]
+                for sitepin, pindata in sorted(sitedata["site_pins"].items()):
+                    if pindata is None:
+                        tspd = TileSitePinData(None)
+                    else:
+                        pinwire = td.wires_by_name[pindata["wire"]].index
+                        tspd = TileSitePinData(pinwire)
+                        if "delay" in pindata:
+                            tspd.min_delay = min(float(pindata["delay"][0]), float(pindata["delay"][1]))
+                            tspd.max_delay = max(float(pindata["delay"][2]), float(pindata["delay"][3]))
+                        if "res" in pindata:
+                            tspd.resistance = float(pindata["res"])
+                        if "cap" in pindata:
+                            tspd.capacitance = float(pindata["cap"])
+                    td.sitepin_data[(sitetype, rel_xy, sitepin)] = tspd
+            if os.path.exists(prjxray_root + "/timings/" + tiletype + ".sdf"):
+                td.cell_timing = parse_sdf_file(prjxray_root + "/timings/" + tiletype + ".sdf")
+
+            tile_type_cache[tiletype] = td
+
+        return tile_type_cache[tiletype]
+
+    def get_wire_intent(tiletype, wirename):
+        if tiletype not in ij["tiles"]:
+            return "GENERIC"
+        if wirename not in ij["tiles"][tiletype]:
+            return "GENERIC"
+        return ij["intents"][str(ij["tiles"][tiletype][wirename])]
+
+    d = Device(fabricname)
+
+    # Load intent JSON
+    with open(metadata_root + "/wire_intents.json", "r") as ijf:
+        ij = json.load(ijf)
+    with open(prjxray_root + "/" + fabricname + "/tilegrid.json") as gf:
+        tgj = json.load(gf)
+    for tile, tiledata in sorted(tgj.items()):
+        x = int(tiledata["grid_x"])
+        y = int(tiledata["grid_y"])
+        d.width = max(d.width, x + 1)
+        d.height = max(d.height, y + 1)
+        tiletype = tiledata["type"]
+        t = Tile(x, y, tile, get_tile_type_data(tiletype), (-1, -1), [])
+        for idx, (site, sitetype) in enumerate(sorted(tiledata["sites"].items())):
+                si = Site(t, site, idx, parse_xy(site), get_site_type_data(sitetype))
+                t.site_insts.append(si)
+                d.sites_by_name[site] = si
+        d.tiles_by_name[tile] = t
+        d.tiles_by_xy[x, y] = t
+        d.tiles.append(t)
+
+    # Resolve interconnect tile coordinates
+    for t in d.tiles:
+        for delta in range(0, 30):
+            if t.interconn_xy != (-1, -1):
+                break # found, done
+            for direction in (-1, +1):
+                nxy = (t.x + direction * delta, t.y)
+                if nxy not in d.tiles_by_xy:
+                    continue
+                if d.tiles_by_xy[nxy].tile_type not in ("INT", "INT_L", "INT_R"):
+                    continue
+                t.interconn_xy = nxy
+                break
+    # Read package pins
+    for entry in os.scandir(prjxray_root):
+        if not entry.is_dir() or not entry.name.startswith(fabricname):
+            continue
+        device_postfix = entry.name[len(fabricname):]
+        if len(device_postfix) == 0:
+            continue
+        package_name = device_postfix.split("-")[0]
+        if package_name in d.packages:
+            continue # already seen in a different speed grade
+        with open(prjxray_root + "/" + entry.name + "/package_pins.csv") as ppf:
+            pkg = Package(name=package_name)
+            for line in ppf:
+                sl = line.strip().split(",")
+                if len(sl) < 3:
+                    continue
+                if sl[2] == "site":
+                    continue # header
+                pkg.pin_map[sl[0]] = sl[2]
+            d.packages[package_name] = pkg
+    with open(prjxray_root + "/" + fabricname + "/tileconn.json", "r") as tcf:
+        apply_tileconn(tcf, d)
+    return d
+
+if __name__ == '__main__':
+    import sys
+    import_device(*sys.argv[1:])
diff --git a/himbaechel/uarch/xilinx/gen/xilinx_gen.py b/himbaechel/uarch/xilinx/gen/xilinx_gen.py
new file mode 100644
index 0000000000..8eec7f56cd
--- /dev/null
+++ b/himbaechel/uarch/xilinx/gen/xilinx_gen.py
@@ -0,0 +1,371 @@
+from os import path
+import sys
+import argparse
+import xilinx_device
+import filters
+import struct
+sys.path.append(path.join(path.dirname(__file__), "../../.."))
+from himbaechel_dbgen.chip import *
+
+def lookup_port_type(t):
+    if t == "INPUT": return PinType.INPUT
+    elif t == "OUTPUT": return PinType.OUTPUT
+    elif t == "BIDIR": return PinType.INOUT
+    else: assert False
+
+def gen_bel_name(site, bel_name):
+    prim_st = site.primary.site_type()
+    if prim_st in ("IOB33M", "IOB33S", "IOB33", "IOB18M", "IOB18S", "IOB18"):
+        return f"{site.site_type()}.{bel_name}"
+    else:
+        return f"{bel_name}"
+
+@dataclass
+class PipClass(Enum):
+    TILE_ROUTING = 0
+    SITE_ENTRANCE = 1
+    SITE_EXIT = 2
+    SITE_INTERNAL = 3
+    LUT_PERMUTATION = 4
+    LUT_ROUTETHRU = 5
+    CONST_DRIVER = 6
+
+@dataclass
+class PipExtraData(BBAStruct):
+    site_key: int = -1
+    bel_name: IdString = field(default_factory=IdString)
+    pip_config: int = 0
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.site_key)
+        bba.u32(self.bel_name.index)
+        bba.u32(self.pip_config)
+
+@dataclass
+class BelExtraData(BBAStruct):
+    name_in_site: IdString
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name_in_site.index)
+
+@dataclass
+class SiteInst(BBAStruct):
+    name_prefix: IdString
+    site_x: int
+    site_y: int
+    rel_x: int
+    rel_y: int
+    int_x: int
+    int_y: int
+    variants: list[IdString] = field(default_factory=list)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_variants")
+        for i, variant in enumerate(self.variants):
+            bba.u32(variant.index)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name_prefix.index)
+        bba.u16(self.site_x)
+        bba.u16(self.site_y)
+        bba.u16(self.rel_x)
+        bba.u16(self.rel_y)
+        bba.u16(self.int_x)
+        bba.u16(self.int_y)
+        bba.slice(f"{context}_variants", len(self.variants))
+
+@dataclass
+class TileExtraData(BBAStruct):
+    name_prefix: IdString
+    tile_x: int
+    tile_y: int
+    sites: list[SiteInst] = field(default_factory=list)
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        for i, site in enumerate(self.sites):
+            site.serialise_lists(f"{context}_si{i}", bba)
+        bba.label(f"{context}_sites")
+        for i, site in enumerate(self.sites):
+            site.serialise(f"{context}_si{i}", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name_prefix.index)
+        bba.u16(self.tile_x)
+        bba.u16(self.tile_y)
+        bba.slice(f"{context}_sites", len(self.sites))
+
+def timing_pip_classs(pip: xilinx_device.PIP):
+    return f"{'buf' if pip.is_buffered() else 'sw'}_d{pip.max_delay()}_r{pip.resistance()}_c{pip.capacitance()}"
+
+seen_pip_timings = set()
+seen_node_timings = set()
+
+def import_tiletype(ch: Chip, tile: xilinx_device.Tile):
+    tile_type = tile.tile_type()
+    if tile.x == 0 and tile.y == 0:
+        assert tile_type == "NULL"
+        tile_type = "NULL_CORNER"
+    tt = ch.create_tile_type(tile_type)
+    # import tile wires
+    for wire in tile.wires():
+        nw = tt.create_wire(wire.name(), wire.intent())
+        nw.flags = -1 # not a site wire
+        if wire.is_gnd():
+            nw.const_value = ch.strs.id("GND")
+        if wire.is_vcc():
+            nw.const_value = ch.strs.id("VCC")
+    if tile_type == "NULL_CORNER":
+        # pseudo ground bels
+        tt.create_wire(f"GND", "GND", const_value="GND")
+        tt.create_wire(f"VCC", "VCC", const_value="VCC")
+
+        gnd = tt.create_bel(f"PSEUDO_GND", f"PSEUDO_GND", z=0)
+        gnd.site = -1
+        gnd.extra_data = BelExtraData(name_in_site=ch.strs.id("PSEUDO_GND"))
+        tt.add_bel_pin(gnd, "Y", "GND", PinType.OUTPUT)
+
+        vcc = tt.create_bel(f"PSEUDO_VCC", f"PSEUDO_VCC", z=1)
+        vcc.site = -1
+        vcc.extra_data = BelExtraData(name_in_site=ch.strs.id("PSEUDO_VCC"))
+        tt.add_bel_pin(vcc, "Y", "VCC", PinType.OUTPUT)
+    def add_pip(src_wire, dst_wire, pip_class=PipClass.TILE_ROUTING, timing="",
+        site_key=-1, bel_name="", pip_config=0):
+        np = tt.create_pip(src_wire, dst_wire, timing)
+        np.flags = pip_class.value
+        np.extra_data = PipExtraData(site_key=site_key, bel_name=ch.strs.id(bel_name),
+            pip_config=pip_config)
+
+    def lookup_site_wire(sw):
+        canon_name = f"{sw.site.rel_name()}.{sw.name()}"
+        if not tt.has_wire(canon_name):
+            nw = tt.create_wire(name=canon_name,
+                type="INTENT_SITE_GND" if sw.name() == "GND_WIRE" else "INTENT_SITE_WIRE")
+            nw.flags = sw.site.primary.index
+        return canon_name
+
+    def add_site_io_pip(pin):
+        pn = pin.name()
+        s = pin.site
+        site_key = (s.index << 8)
+        if pin.tile_wire() is None:
+            return None
+        # TODO: timing class
+        if pin.dir() in ("OUTPUT", "BIDIR"):
+            if s.primary.site_type() == "IPAD" and pn == "O":
+                return None
+            # if s.rel_xy()[0] == 0 and s.primary.site_type() == "SLICEL" and pin.site_wire().name() == "A":
+            #     # Add ground pip
+            #     # self.add_pseudo_pip(self.row_gnd_wire_index, self.sitewire_to_tilewire(pin.site_wire()),
+            #     #    pip_type=NextpnrPipType.CONST_DRIVER)
+            #     pass
+            add_pip(lookup_site_wire(pin.site_wire()), pin.tile_wire().name(),
+                pip_class=PipClass.SITE_EXIT, timing="SITE_NULL")
+        else:
+            if s.site_type() in ("SLICEL", "SLICEM"):
+                # Add permuation pseudo-pips for LUT inputs
+                swn = pin.site_wire().name()
+                if len(swn) == 2 and swn[0] in "ABCDEFGH" and swn[1] in "123456":
+                    i = int(swn[1])
+                    for j in range(1, 7):
+                        if (i == 6) != (j == 6):
+                            continue # don't allow permutation of input 6
+                        pip_config = ("ABCDEFGH".index(swn[0]) << 8) | ((j - 1) << 4) | (i - 1)
+                        if s.rel_xy()[0] == 1:
+                            pip_config |= (4 << 8)
+                        add_pip(s.pin(f"{swn[0]}{j}").tile_wire().name(), lookup_site_wire(pin.site_wire()),
+                            pip_class=PipClass.LUT_PERMUTATION,
+                            pip_config=pip_config,
+                            site_key=(s.index << 8),
+                            timing="SITE_NULL"
+                        )
+                    return
+            add_pip(pin.tile_wire().name(), lookup_site_wire(pin.site_wire()),
+                pip_class=PipClass.SITE_ENTRANCE, timing="SITE_NULL")
+
+    # TODO: ground/vcc
+    tile_wire_count = len(tt.wires)
+    for site in tile.sites():
+        seen_pins = set()
+        for variant_idx, variant in enumerate(site.available_variants()):
+            if variant in ("FIFO36E1", ): #unsupported atm
+                continue
+            sv = site.variant(variant)
+            variant_key = (site.index << 8) | (variant_idx & 0xFF)
+            # Import site bels
+            for bel in sv.bels():
+                z = filters.get_bel_z_override(bel, len(tt.bels))
+                # Overriden z of -1 means we skip this bel
+                if z == -1:
+                    continue
+                bel_name = gen_bel_name(sv, bel.name())
+                nb = tt.create_bel(name=f"{site.rel_name()}.{bel_name}", type=filters.get_bel_type_override(bel.bel_type()), z=z)
+                nb.site = variant_key
+                nb.extra_data = BelExtraData(name_in_site=ch.strs.id(bel_name))
+                if bel.bel_class() == "RBEL": nb.flags |= 2
+                # TODO: extra data (site etc)
+                for pin in bel.pins():
+                    tt.add_bel_pin(nb, pin.name, lookup_site_wire(pin.site_wire()), lookup_port_type(pin.dir()))
+            # Import site pins
+            for pin in sv.pins():
+                pin_key = (pin.name(), pin.site_wire().name())
+                if pin_key not in seen_pins:
+                    add_site_io_pip(pin)
+                    seen_pins.add(pin_key)
+            # Import site pips
+            for site_pip in sv.pips():
+                if "LUT" in site_pip.bel().bel_type():
+                    continue # ignore site LUT route-throughs
+                bel_name = site_pip.bel().name()
+                bel_pin = site_pip.bel_input()
+                if (bel_name == "ADI1MUX" and bel_pin == "BDI1") or \
+                    (bel_name == "BDI1MUX" and bel_pin == "DI") or \
+                    (bel_name == "CDI1MUX" and bel_pin == "DI") or \
+                    (bel_name.startswith("TFBUSED")) or \
+                    (bel_name == "OMUX"):
+                    continue
+                add_pip(lookup_site_wire(site_pip.src_wire()),
+                    lookup_site_wire(site_pip.dst_wire()),
+                    pip_class=PipClass.SITE_INTERNAL,
+                    site_key=variant_key,
+                    bel_name=bel_name,
+                    pip_config=ch.strs.id(bel_pin).index,
+                    timing="SITE_NULL"
+                )
+    # Import tile pips
+    for pip in tile.pips():
+        if not filters.include_pip(tile.tile_type(), pip):
+            continue
+        tcls = timing_pip_classs(pip)
+        if tcls not in seen_pip_timings:
+            ch.timing.set_pip_class(f"DEFAULT", tcls,
+                delay=TimingValue(int(pip.min_delay()*1000), int(pip.max_delay()*1000)), # ps
+                in_cap=TimingValue(int(pip.capacitance()*1000)), # fF
+                out_res=TimingValue(int(pip.resistance())), # mohm
+                is_buffered=pip.is_buffered())
+            seen_pip_timings.add(tcls)
+        add_pip(pip.src_wire().name(), pip.dst_wire().name(), pip_class=PipClass.TILE_ROUTING, timing=tcls,
+            pip_config=1 if pip.is_route_thru() else 0)
+        # TODO: extra data, route-through flag
+        if pip.is_bidi():
+            add_pip(pip.dst_wire().name(), pip.src_wire().name(), pip_class=PipClass.TILE_ROUTING, timing=tcls,
+                pip_config=1 if pip.is_route_thru() else 0)
+def main():
+    xlbase = path.join(path.dirname(path.realpath(__file__)), "..")
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--xray", help="Project X-Ray device database path for current family (e.g. ../prjxray-db/artix7)", type=str, required=True)
+    parser.add_argument("--metadata", help="nextpnr-xilinx site metadata root", type=str, default=path.join(xlbase, "meta", "artix7"))
+    parser.add_argument("--device", help="name of device to export", type=str, required=True)
+    parser.add_argument("--constids", help="name of nextpnr constids file to read", type=str, default=path.join(xlbase, "constids.inc"))
+    parser.add_argument("--bba", help="bba file to write", type=str, required=True)
+    args = parser.parse_args()
+
+    # Init database paths
+    metadata_root = args.metadata
+    xraydb_root = args.xray
+    if "xc7z" in args.device:
+        metadata_root = metadata_root.replace("artix7", "zynq7")
+        xraydb_root = xraydb_root.replace("artix7", "zynq7")
+    if "xc7k" in args.device:
+        metadata_root = metadata_root.replace("artix7", "kintex7")
+        xraydb_root = xraydb_root.replace("artix7", "kintex7")
+    if "xc7s" in args.device:
+        metadata_root = metadata_root.replace("artix7", "spartan7")
+        xraydb_root = xraydb_root.replace("artix7", "spartan7")
+    # Load prjxray device data
+    d = xilinx_device.import_device(args.device, xraydb_root, metadata_root)
+    # Init constant ids
+    ch = Chip("xilinx", args.device, d.width, d.height)
+    ch.strs.read_constids(path.join(path.dirname(__file__), args.constids))
+    ch.set_speed_grades(["DEFAULT", ]) # TODO: figure out how speed grades are supposed to work in prjxray
+    # Import tile types
+    for tile in d.tiles:
+        tile_type = tile.tile_type()
+        if tile.x == 0 and tile.y == 0:
+            assert tile_type == "NULL"
+            # location for pseudo gnd/vcc bels
+            tile_type = "NULL_CORNER"
+        if tile_type not in ch.tile_type_idx:
+            import_tiletype(ch, tile)
+        ti = ch.set_tile_type(tile.x, tile.y, tile_type)
+        prefix, tx, ty = tile.split_name()
+        ti.extra_data = TileExtraData(ch.strs.id(prefix), tx, ty)
+        for site in tile.sites():
+            ti.extra_data.sites.append(SiteInst(
+                name_prefix=ch.strs.id(site.prefix),
+                site_x=site.grid_xy[0], site_y=site.grid_xy[1],
+                rel_x=site.rel_xy()[0], rel_y=site.rel_xy()[1],
+                int_x=tile.interconn_xy[0], int_y=tile.interconn_xy[1],
+                variants=[ch.strs.id(v) for v in site.available_variants()]
+            ))
+    # Import nodes
+    seen_nodes = set()
+    tt_used_wires = {}
+    print("Processing nodes...")
+    for row in range(d.height):
+        # TODO: GND and VCC row connectivity...
+        for col in range(d.width):
+            t = d.tiles_by_xy[col, row]
+            for w in t.wires():
+                n = w.node()
+                uid = n.unique_index()
+                if uid in seen_nodes:
+                    continue
+                if len(n.wires) > 1:
+                    node_wires = []
+                    node_cap = 0
+                    node_res = 0
+                    # Add interconnect tiles first for better delay estimates in nextpnr
+                    for j in range(2):
+                        for w in n.wires:
+                            if (w.tile.tile_type() in ("INT", "INT_L", "INT_R")) != (j == 0):
+                                continue
+                            if w.tile.tile_type() not in tt_used_wires:
+                                tt_used_wires[w.tile.tile_type()] = w.tile.used_wire_indices()
+                            node_cap += int(w.capacitance() * 1000)
+                            node_res += int(w.resistance())
+                            # prune wires from nodes that just pass through a tile without connecting to
+                            # bels/pips, because nextpnr doesn't care about these
+                            if w.index not in tt_used_wires[w.tile.tile_type()]:
+                                continue
+                            node_wires.append(NodeWire(w.tile.x, w.tile.y, w.index))
+                    if len(node_wires) > 1:
+                        timing_class = f"node_c{node_cap}_c{node_res}"
+                        ch.add_node(node_wires, timing_class=timing_class)
+                        if timing_class not in seen_node_timings:
+                            ch.timing.set_node_class("DEFAULT", timing_class, delay=TimingValue(0), cap=TimingValue(node_cap), res=TimingValue(node_res))
+                            seen_node_timings.add(timing_class)
+                    del node_wires
+                seen_nodes.add(uid)
+    # Stub timing class
+    ch.timing.set_pip_class("DEFAULT", "SITE_NULL", delay=TimingValue(20))
+    # Stub bel timings
+    lut = ch.timing.add_cell_variant("DEFAULT", "SLICE_LUTX")
+    for i in range(1, 6+1):
+        lut.add_comb_arc(f"A{i}", "O6", TimingValue(100, 125))
+        if i <= 5: lut.add_comb_arc(f"A{i}", "O5", TimingValue(120, 150))
+    for i in range(1, 8+1):
+        lut.add_setup_hold("CLK", f"WA{i}", ClockEdge.RISING, TimingValue(100, 500), TimingValue(100, 200))
+    lut.add_setup_hold("CLK", "WE", ClockEdge.RISING, TimingValue(100, 600), TimingValue(100, 100))
+    lut.add_setup_hold("CLK", "DI1", ClockEdge.RISING, TimingValue(100, 100), TimingValue(100, 100))
+    ff = ch.timing.add_cell_variant("DEFAULT", "SLICE_FFX")
+    ff.add_setup_hold("CK", "CE", ClockEdge.RISING, TimingValue(100, 100), TimingValue(0, 0))
+    ff.add_setup_hold("CK", "SR", ClockEdge.RISING, TimingValue(100, 100), TimingValue(0, 0))
+    ff.add_setup_hold("CK", "D", ClockEdge.RISING, TimingValue(100, 100), TimingValue(200, 200))
+    ff.add_clock_out("CK", "Q", ClockEdge.RISING, TimingValue(300, 350))
+    # Import package pins
+    for package_name, package in sorted(d.packages.items(), key=lambda x:x[0]):
+        pkg = ch.create_package(package_name)
+        for pin, site in sorted(package.pin_map.items(), key=lambda x:x[0]):
+            site_data = d.sites_by_name[site]
+            bel_name = gen_bel_name(site_data, "PAD")
+            tile_type = ch.tile_type_at(site_data.tile.x, site_data.tile.y)
+            pkg.create_pad(pin, f"X{site_data.tile.x}Y{site_data.tile.y}",
+            f"{site_data.rel_name()}.{bel_name}",
+            "", 0) # TODO: bank
+    ch.write_bba(args.bba)
+
+if __name__ == '__main__':
+    main()
diff --git a/himbaechel/uarch/xilinx/meta b/himbaechel/uarch/xilinx/meta
new file mode 160000
index 0000000000..57de921663
--- /dev/null
+++ b/himbaechel/uarch/xilinx/meta
@@ -0,0 +1 @@
+Subproject commit 57de9216639b0670949664cfdc61b2679064eb7b
diff --git a/himbaechel/uarch/xilinx/pack.cc b/himbaechel/uarch/xilinx/pack.cc
new file mode 100644
index 0000000000..a40ccbd387
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack.cc
@@ -0,0 +1,750 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "pack.h"
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// Process the contents of packed_cells
+void XilinxPacker::flush_cells()
+{
+    for (auto pcell : packed_cells) {
+        for (auto &port : ctx->cells[pcell]->ports) {
+            ctx->cells[pcell]->disconnectPort(port.first);
+        }
+        ctx->cells.erase(pcell);
+    }
+    packed_cells.clear();
+}
+
+void XilinxPacker::xform_cell(const dict<IdString, XFormRule> &rules, CellInfo *ci)
+{
+    auto &rule = rules.at(ci->type);
+    ci->attrs[id_X_ORIG_TYPE] = ci->type.str(ctx);
+    ci->type = rule.new_type;
+    std::vector<IdString> orig_port_names;
+    for (auto &port : ci->ports)
+        orig_port_names.push_back(port.first);
+
+    for (auto pname : orig_port_names) {
+        if (rule.port_multixform.count(pname)) {
+            auto old_port = ci->ports.at(pname);
+            ci->disconnectPort(pname);
+            ci->ports.erase(pname);
+            for (auto new_name : rule.port_multixform.at(pname)) {
+                ci->ports[new_name].name = new_name;
+                ci->ports[new_name].type = old_port.type;
+                ci->connectPort(new_name, old_port.net);
+                ci->attrs[ctx->id("X_ORIG_PORT_" + new_name.str(ctx))] = pname.str(ctx);
+            }
+        } else {
+            IdString new_name;
+            if (rule.port_xform.count(pname)) {
+                new_name = rule.port_xform.at(pname);
+            } else {
+                std::string stripped_name;
+                for (auto c : pname.str(ctx))
+                    if (c != '[' && c != ']')
+                        stripped_name += c;
+                new_name = ctx->id(stripped_name);
+            }
+            if (new_name != pname) {
+                ci->renamePort(pname, new_name);
+            }
+            ci->attrs[ctx->id("X_ORIG_PORT_" + new_name.str(ctx))] = pname.str(ctx);
+        }
+    }
+
+    std::vector<IdString> xform_params;
+    for (auto &param : ci->params)
+        if (rule.param_xform.count(param.first))
+            xform_params.push_back(param.first);
+    for (auto param : xform_params)
+        ci->params[rule.param_xform.at(param)] = ci->params[param];
+
+    for (auto &attr : rule.set_attrs)
+        ci->attrs[attr.first] = attr.second;
+
+    for (auto &param : rule.set_params)
+        ci->params[param.first] = param.second;
+}
+
+void XilinxPacker::generic_xform(const dict<IdString, XFormRule> &rules, bool print_summary)
+{
+    std::map<std::string, int> cell_count;
+    std::map<std::string, int> new_types;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (rules.count(ci->type)) {
+            cell_count[ci->type.str(ctx)]++;
+            xform_cell(rules, ci);
+            new_types[ci->type.str(ctx)]++;
+        }
+    }
+    if (print_summary) {
+        for (auto &nt : new_types) {
+            log_info("    Created %d %s cells from:\n", nt.second, nt.first.c_str());
+            for (auto &cc : cell_count) {
+                if (rules.at(ctx->id(cc.first)).new_type != ctx->id(nt.first))
+                    continue;
+                log_info("        %6dx %s\n", cc.second, cc.first.c_str());
+            }
+        }
+    }
+}
+
+CellInfo *XilinxPacker::feed_through_lut(NetInfo *net, const std::vector<PortRef> &feed_users)
+{
+    NetInfo *feedthru_net = ctx->createNet(ctx->idf("%s$legal%d", net->name.c_str(ctx), ++autoidx));
+
+    CellInfo *lut = create_lut(stringf("%s$LUT%d", net->name.c_str(ctx), ++autoidx), {net}, feedthru_net, Property(2));
+
+    for (auto &usr : feed_users) {
+        usr.cell->disconnectPort(usr.port);
+        usr.cell->connectPort(usr.port, feedthru_net);
+    }
+
+    return lut;
+}
+
+CellInfo *XilinxPacker::feed_through_muxf(NetInfo *net, IdString type, const std::vector<PortRef> &feed_users)
+{
+    NetInfo *feedthru_net = ctx->createNet(ctx->idf("%s$legal$%d", net->name.c_str(ctx), ++autoidx));
+    CellInfo *mux = create_cell(type, ctx->idf("%s$MUX$%d", net->name.c_str(ctx), ++autoidx));
+    mux->connectPort(id_I0, net);
+    mux->connectPort(id_O, feedthru_net);
+    mux->connectPort(id_S, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+
+    for (auto &usr : feed_users) {
+        usr.cell->disconnectPort(usr.port);
+        usr.cell->connectPort(usr.port, feedthru_net);
+    }
+
+    return mux;
+}
+
+IdString XilinxPacker::int_name(IdString base, const std::string &postfix, bool is_hierarchy)
+{
+    return ctx->id(base.str(ctx) + (is_hierarchy ? "$subcell$" : "$intcell$") + postfix);
+}
+
+NetInfo *XilinxPacker::create_internal_net(IdString base, const std::string &postfix, bool is_hierarchy)
+{
+    IdString name = ctx->id(base.str(ctx) + (is_hierarchy ? "$subnet$" : "$intnet$") + postfix);
+    return ctx->createNet(name);
+}
+
+void XilinxPacker::pack_luts()
+{
+    log_info("Packing LUTs..\n");
+
+    dict<IdString, XFormRule> lut_rules;
+    for (int k = 1; k <= 6; k++) {
+        IdString lut = ctx->id("LUT" + std::to_string(k));
+        lut_rules[lut].new_type = id_SLICE_LUTX;
+        for (int i = 0; i < k; i++)
+            lut_rules[lut].port_xform[ctx->id("I" + std::to_string(i))] = ctx->id("A" + std::to_string(i + 1));
+        lut_rules[lut].port_xform[id_O] = id_O6;
+    }
+    lut_rules[id_LUT6_2] = XFormRule(lut_rules[id_LUT6]);
+    generic_xform(lut_rules, true);
+}
+
+void XilinxPacker::pack_ffs()
+{
+    log_info("Packing flipflops..\n");
+
+    dict<IdString, XFormRule> ff_rules;
+    ff_rules[id_FDCE].new_type = id_SLICE_FFX;
+    ff_rules[id_FDCE].port_xform[id_C] = id_CK;
+    ff_rules[id_FDCE].port_xform[id_CLR] = id_SR;
+    // ff_rules[id_FDCE].param_xform[id_IS_CLR_INVERTED] = id_IS_SR_INVERTED;
+
+    ff_rules[id_FDPE].new_type = id_SLICE_FFX;
+    ff_rules[id_FDPE].port_xform[id_C] = id_CK;
+    ff_rules[id_FDPE].port_xform[id_PRE] = id_SR;
+    // ff_rules[id_FDPE].param_xform[id_IS_PRE_INVERTED] = id_IS_SR_INVERTED;
+
+    ff_rules[id_FDRE].new_type = id_SLICE_FFX;
+    ff_rules[id_FDRE].port_xform[id_C] = id_CK;
+    ff_rules[id_FDRE].port_xform[id_R] = id_SR;
+    ff_rules[id_FDRE].set_attrs.emplace_back(id_X_FFSYNC, "1");
+    // ff_rules[id_FDRE].param_xform[id_IS_R_INVERTED] = id_IS_SR_INVERTED;
+
+    ff_rules[id_FDSE].new_type = id_SLICE_FFX;
+    ff_rules[id_FDSE].port_xform[id_C] = id_CK;
+    ff_rules[id_FDSE].port_xform[id_S] = id_SR;
+    ff_rules[id_FDSE].set_attrs.emplace_back(id_X_FFSYNC, "1");
+    // ff_rules[id_FDSE].param_xform[id_IS_S_INVERTED] = id_IS_SR_INVERTED;
+
+    ff_rules[id_FDCE_1] = XFormRule(ff_rules[id_FDCE]);
+    ff_rules[id_FDCE_1].set_params.emplace_back(id_IS_C_INVERTED, 1);
+
+    ff_rules[id_FDPE_1] = XFormRule(ff_rules[id_FDPE]);
+    ff_rules[id_FDPE_1].set_params.emplace_back(id_IS_C_INVERTED, 1);
+
+    ff_rules[id_FDRE_1] = XFormRule(ff_rules[id_FDRE]);
+    ff_rules[id_FDRE_1].set_params.emplace_back(id_IS_C_INVERTED, 1);
+
+    ff_rules[id_FDSE_1] = XFormRule(ff_rules[id_FDSE]);
+    ff_rules[id_FDSE_1].set_params.emplace_back(id_IS_C_INVERTED, 1);
+
+    generic_xform(ff_rules, true);
+}
+
+void XilinxPacker::pack_lutffs()
+{
+    int pairs = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->cluster != ClusterId() || !ci->constr_children.empty())
+            continue;
+        if (ci->type != id_SLICE_FFX)
+            continue;
+        NetInfo *d = ci->getPort(id_D);
+        if (d->driver.cell == nullptr || d->driver.cell->type != id_SLICE_LUTX || d->driver.port != id_O6)
+            continue;
+        CellInfo *lut = d->driver.cell;
+        if (lut->cluster != ClusterId() || !lut->constr_children.empty())
+            continue;
+        lut->constr_children.push_back(ci);
+        lut->cluster = lut->name;
+        ci->cluster = lut->name;
+        ci->constr_x = 0;
+        ci->constr_y = 0;
+        ci->constr_z = (BEL_FF - BEL_6LUT);
+        ++pairs;
+    }
+    log_info("Constrained %d LUTFF pairs.\n", pairs);
+}
+
+bool XilinxPacker::is_constrained(const CellInfo *cell) { return cell->cluster != ClusterId(); }
+
+void XilinxPacker::legalise_muxf_tree(CellInfo *curr, std::vector<CellInfo *> &mux_roots)
+{
+    if (curr->type.str(ctx).substr(0, 3) == "LUT")
+        return;
+    for (IdString p : {id_I0, id_I1}) {
+        NetInfo *pn = curr->getPort(p);
+        if (pn == nullptr || pn->driver.cell == nullptr)
+            continue;
+        if (curr->type == id_MUXF7) {
+            if (pn->driver.cell->type.str(ctx).substr(0, 3) != "LUT" || is_constrained(pn->driver.cell)) {
+                PortRef pr;
+                pr.cell = curr;
+                pr.port = p;
+                feed_through_lut(pn, {pr});
+                continue;
+            }
+        } else {
+            IdString next_type;
+            if (curr->type == id_MUXF9)
+                next_type = id_MUXF8;
+            else if (curr->type == id_MUXF8)
+                next_type = id_MUXF7;
+            else
+                NPNR_ASSERT_FALSE("bad mux type");
+            if (pn->driver.cell->type != next_type || is_constrained(pn->driver.cell) ||
+                bool_or_default(pn->driver.cell->attrs, id_MUX_TREE_ROOT)) {
+                PortRef pr;
+                pr.cell = curr;
+                pr.port = p;
+                feed_through_muxf(pn, next_type, {pr});
+                continue;
+            }
+        }
+        legalise_muxf_tree(pn->driver.cell, mux_roots);
+    }
+}
+
+void XilinxPacker::constrain_muxf_tree(CellInfo *curr, CellInfo *base, int zoffset)
+{
+
+    if (curr->type == id_SLICE_LUTX && (curr->constr_abs_z || curr->cluster != ClusterId()))
+        return;
+
+    int base_z = 0;
+    if (base->type == id_MUXF7)
+        base_z = BEL_F7MUX;
+    else if (base->type == id_MUXF8)
+        base_z = BEL_F8MUX;
+    else if (base->type == id_MUXF9)
+        base_z = BEL_F9MUX;
+    else if (base->constr_abs_z)
+        base_z = base->constr_z;
+    else
+        NPNR_ASSERT_FALSE("unexpected mux base type");
+    int curr_z = zoffset * 16;
+    int input_spacing = 0;
+    if (curr->type == id_MUXF7) {
+        curr_z += BEL_F7MUX;
+        input_spacing = 1;
+    } else if (curr->type == id_MUXF8) {
+        curr_z += BEL_F8MUX;
+        input_spacing = 2;
+    } else if (curr->type == id_MUXF9) {
+        curr_z += BEL_F9MUX;
+        input_spacing = 4;
+    } else
+        curr_z += BEL_6LUT;
+    if (curr != base) {
+        curr->constr_x = 0;
+        curr->constr_y = 0;
+        curr->constr_z = curr_z - base_z;
+        curr->constr_abs_z = false;
+        curr->cluster = base->name;
+        base->constr_children.push_back(curr);
+    }
+    if (curr->type.in(id_MUXF7, id_MUXF8, id_MUXF9)) {
+        NetInfo *i0 = curr->getPort(id_I0), *i1 = curr->getPort(id_I1);
+        if (i0 != nullptr && i0->driver.cell != nullptr)
+            constrain_muxf_tree(i0->driver.cell, base, zoffset + input_spacing);
+        if (i1 != nullptr && i1->driver.cell != nullptr)
+            constrain_muxf_tree(i1->driver.cell, base, zoffset);
+    }
+}
+
+void XilinxPacker::pack_muxfs()
+{
+    log_info("Packing MUX[789]s..\n");
+    std::vector<CellInfo *> mux_roots;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        ci->attrs.erase(id_MUX_TREE_ROOT);
+        if (ci->type == id_MUXF9) {
+            log_error("MUXF9 is not supported on xc7!\n");
+        } else if (ci->type == id_MUXF8) {
+            NetInfo *o = ci->getPort(id_O);
+            if (o == nullptr || o->users.entries() != 1 || (*o->users.begin()).cell->type != id_MUXF9 ||
+                is_constrained((*o->users.begin()).cell) || (*o->users.begin()).port == id_S)
+                mux_roots.push_back(ci);
+        } else if (ci->type == id_MUXF7) {
+            NetInfo *o = ci->getPort(id_O);
+            if (o == nullptr || o->users.entries() != 1 || (*o->users.begin()).cell->type != id_MUXF8 ||
+                is_constrained((*o->users.begin()).cell) || (*o->users.begin()).port == id_S)
+                mux_roots.push_back(ci);
+        }
+    }
+    for (auto root : mux_roots)
+        root->attrs[id_MUX_TREE_ROOT] = 1;
+    for (auto root : mux_roots)
+        legalise_muxf_tree(root, mux_roots);
+    for (auto root : mux_roots) {
+        root->cluster = root->name;
+        constrain_muxf_tree(root, root, 0);
+    }
+}
+
+void XilinxPacker::finalise_muxfs()
+{
+    dict<IdString, XFormRule> muxf_rules;
+    muxf_rules[id_MUXF9].new_type = id_F9MUX;
+    muxf_rules[id_MUXF9].port_xform[id_I0] = id_0;
+    muxf_rules[id_MUXF9].port_xform[id_I1] = id_1;
+    muxf_rules[id_MUXF9].port_xform[id_S] = id_S0;
+    muxf_rules[id_MUXF9].port_xform[id_O] = id_OUT;
+    muxf_rules[id_MUXF8].new_type = id_SELMUX2_1;
+    muxf_rules[id_MUXF8].port_xform = muxf_rules[id_MUXF9].port_xform;
+    muxf_rules[id_MUXF7].new_type = id_SELMUX2_1;
+    muxf_rules[id_MUXF7].port_xform = muxf_rules[id_MUXF9].port_xform;
+    generic_xform(muxf_rules, true);
+}
+
+void XilinxPacker::pack_srls()
+{
+    dict<IdString, XFormRule> srl_rules;
+    srl_rules[id_SRL16E].new_type = id_SLICE_LUTX;
+    srl_rules[id_SRL16E].port_xform[id_CLK] = id_CLK;
+    srl_rules[id_SRL16E].port_xform[id_CE] = id_WE;
+    srl_rules[id_SRL16E].port_xform[id_D] = id_DI2;
+    srl_rules[id_SRL16E].port_xform[id_Q] = id_O6;
+    srl_rules[id_SRL16E].set_attrs.emplace_back(id_X_LUT_AS_SRL, "1");
+
+    srl_rules[id_SRLC32E].new_type = id_SLICE_LUTX;
+    srl_rules[id_SRLC32E].port_xform[id_CLK] = id_CLK;
+    srl_rules[id_SRLC32E].port_xform[id_CE] = id_WE;
+    srl_rules[id_SRLC32E].port_xform[id_D] = id_DI1;
+    srl_rules[id_SRLC32E].port_xform[id_Q] = id_O6;
+    srl_rules[id_SRLC32E].set_attrs.emplace_back(id_X_LUT_AS_SRL, "1");
+    // FIXME: Q31 support
+    generic_xform(srl_rules, true);
+    // Fixup SRL inputs
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_SLICE_LUTX)
+            continue;
+        std::string orig_type = str_or_default(ci->attrs, id_X_ORIG_TYPE);
+        if (orig_type == "SRL16E") {
+            for (int i = 3; i >= 0; i--) {
+                ci->renamePort(ctx->id("A" + std::to_string(i)), ctx->id("A" + std::to_string(i + 2)));
+            }
+            for (auto tp : {id_A1, id_A6}) {
+                ci->ports[tp].name = tp;
+                ci->ports[tp].type = PORT_IN;
+                ci->connectPort(tp, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            }
+        } else if (orig_type == "SRLC32E") {
+            for (int i = 4; i >= 0; i--) {
+                ci->renamePort(ctx->id("A" + std::to_string(i)), ctx->id("A" + std::to_string(i + 2)));
+            }
+            for (auto tp : {id_A1}) {
+                ci->ports[tp].name = tp;
+                ci->ports[tp].type = PORT_IN;
+                ci->connectPort(tp, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            }
+        }
+    }
+}
+
+void XilinxPacker::pack_constants()
+{
+    log_info("Packing constants..\n");
+    if (tied_pins.empty())
+        get_tied_pins(ctx, tied_pins);
+    if (invertible_pins.empty())
+        get_invertible_pins(ctx, invertible_pins);
+    if (!ctx->cells.count(ctx->id("$PACKER_GND_DRV"))) {
+        CellInfo *gnd_cell = ctx->createCell(ctx->id("$PACKER_GND_DRV"), id_PSEUDO_GND);
+        gnd_cell->addOutput(id_Y);
+        NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
+        gnd_net->constant_value = id_GND;
+        gnd_cell->connectPort(id_Y, gnd_net);
+
+        CellInfo *vcc_cell = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), id_PSEUDO_VCC);
+        vcc_cell->addOutput(id_Y);
+        NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
+        vcc_net->constant_value = id_VCC;
+        vcc_cell->connectPort(id_Y, vcc_net);
+    }
+    NetInfo *gnd = ctx->nets[ctx->id("$PACKER_GND_NET")].get(), *vcc = ctx->nets[ctx->id("$PACKER_VCC_NET")].get();
+
+    std::vector<IdString> dead_nets;
+
+    std::vector<std::tuple<CellInfo *, IdString, bool>> const_ports;
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (!tied_pins.count(ci->type))
+            continue;
+        auto &tp = tied_pins.at(ci->type);
+        for (auto port : tp) {
+            if (cell.second->ports.count(port.first) && cell.second->ports.at(port.first).net != nullptr &&
+                cell.second->ports.at(port.first).net->driver.cell != nullptr)
+                continue;
+            const_ports.emplace_back(ci, port.first, port.second);
+        }
+    }
+
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
+            IdString drv_cell = ni->driver.cell->name;
+            for (auto &usr : ni->users) {
+                const_ports.emplace_back(usr.cell, usr.port, false);
+                usr.cell->ports.at(usr.port).net = nullptr;
+            }
+            dead_nets.push_back(net.first);
+            ctx->cells.erase(drv_cell);
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
+            IdString drv_cell = ni->driver.cell->name;
+            for (auto &usr : ni->users) {
+                const_ports.emplace_back(usr.cell, usr.port, true);
+                usr.cell->ports.at(usr.port).net = nullptr;
+            }
+            dead_nets.push_back(net.first);
+            ctx->cells.erase(drv_cell);
+        }
+    }
+
+    for (auto port : const_ports) {
+        CellInfo *ci;
+        IdString pname;
+        bool cval;
+        std::tie(ci, pname, cval) = port;
+
+        if (!ci->ports.count(pname)) {
+            ci->addInput(pname);
+        }
+        if (ci->ports.at(pname).net != nullptr) {
+            // Case where a port with a default tie value is previously connected to an undriven net
+            NPNR_ASSERT(ci->ports.at(pname).net->driver.cell == nullptr);
+            ci->disconnectPort(pname);
+        }
+
+        if (!cval && invertible_pins.count(ci->type) && invertible_pins.at(ci->type).count(pname)) {
+            // Invertible pins connected to zero are optimised to a connection to Vcc (which is easier to route)
+            // and an inversion
+            ci->params[ctx->idf("IS_%s_INVERTED", pname.c_str(ctx))] = Property(1);
+            cval = true;
+        }
+
+        ci->connectPort(pname, cval ? vcc : gnd);
+    }
+
+    for (auto dn : dead_nets) {
+        ctx->nets.erase(dn);
+    }
+}
+
+void XilinxPacker::rename_net(IdString old, IdString newname)
+{
+    std::unique_ptr<NetInfo> ni;
+    std::swap(ni, ctx->nets[old]);
+    ctx->nets.erase(old);
+    ni->name = newname;
+    ctx->nets[newname] = std::move(ni);
+}
+
+void XilinxPacker::tie_port(CellInfo *ci, const std::string &port, bool value, bool inv)
+{
+    IdString p = ctx->id(port);
+    if (!ci->ports.count(p)) {
+        ci->addInput(p);
+    }
+    if (value || inv)
+        ci->connectPort(p, ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get());
+    else
+        ci->connectPort(p, ctx->nets.at(ctx->id("$PACKER_GND_NET")).get());
+    if (!value && inv)
+        ci->params[ctx->idf("IS_%s_INVERTED", port.c_str())] = Property(1);
+}
+
+void XC7Packer::pack_bram()
+{
+    log_info("Packing BRAM..\n");
+
+    // Rules for normal TDP BRAM
+    dict<IdString, XFormRule> bram_rules;
+    bram_rules[id_RAMB18E1].new_type = id_RAMB18E1_RAMB18E1;
+    bram_rules[id_RAMB18E1].port_multixform[ctx->id("WEA[0]")] = {id_WEA0, id_WEA1};
+    bram_rules[id_RAMB18E1].port_multixform[ctx->id("WEA[1]")] = {id_WEA2, id_WEA3};
+    bram_rules[id_RAMB36E1].new_type = id_RAMB36E1_RAMB36E1;
+
+    // Some ports have upper/lower bel pins in 36-bit mode
+    std::vector<std::pair<IdString, std::vector<std::string>>> ul_pins;
+    get_bram36_ul_pins(ctx, ul_pins);
+    for (auto &ul : ul_pins) {
+        for (auto &bp : ul.second)
+            bram_rules[id_RAMB36E1].port_multixform[ul.first].push_back(ctx->id(bp));
+    }
+    bram_rules[id_RAMB36E1].port_multixform[ctx->id("ADDRARDADDR[15]")].push_back(id_ADDRARDADDRL15);
+    bram_rules[id_RAMB36E1].port_multixform[ctx->id("ADDRBWRADDR[15]")].push_back(id_ADDRBWRADDRL15);
+
+    // Special rules for SDP rules, relating to WE connectivity
+    dict<IdString, XFormRule> sdp_bram_rules = bram_rules;
+    for (int i = 0; i < 4; i++) {
+        // Connects to two WEBWE bel pins
+        sdp_bram_rules[id_RAMB18E1].port_multixform[ctx->idf("WEBWE[%d]", i)].push_back(ctx->idf("WEBWE%d", i * 2));
+        sdp_bram_rules[id_RAMB18E1].port_multixform[ctx->idf("WEBWE[%d]", i)].push_back(ctx->idf("WEBWE%d", i * 2 + 1));
+        // Not used in SDP mode
+        sdp_bram_rules[id_RAMB18E1].port_multixform[ctx->idf("WEA[%d]", i)] = {};
+    }
+
+    for (int i = 0; i < 8; i++) {
+        sdp_bram_rules[id_RAMB36E1].port_multixform[ctx->idf("WEBWE[%d]", i)].clear();
+        // Connects to two WEBWE bel pins
+        sdp_bram_rules[id_RAMB36E1].port_multixform[ctx->idf("WEBWE[%d]", i)].push_back(ctx->idf("WEBWEL%d", i));
+        sdp_bram_rules[id_RAMB36E1].port_multixform[ctx->idf("WEBWE[%d]", i)].push_back(ctx->idf("WEBWEU%d", i));
+        // Not used in SDP mode
+        sdp_bram_rules[id_RAMB36E1].port_multixform[ctx->idf("WEA[%d]", i)] = {};
+    }
+
+    // 72-bit BRAMs: drop upper bits of WEB in TDP mode
+    for (int i = 4; i < 8; i++)
+        bram_rules[id_RAMB36E1].port_multixform[ctx->idf("WEBWE[%d]", i)] = {};
+
+    // Process SDP BRAM first
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if ((ci->type == id_RAMB18E1 && int_or_default(ci->params, ctx->id("WRITE_WIDTH_B"), 0) == 36) ||
+            (ci->type == id_RAMB36E1 && int_or_default(ci->params, ctx->id("WRITE_WIDTH_B"), 0) == 72))
+            xform_cell(sdp_bram_rules, ci);
+    }
+
+    // Rewrite byte enables according to data width
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type.in(id_RAMB18E1, id_RAMB36E1)) {
+            for (char port : {'A', 'B'}) {
+                int write_width = int_or_default(ci->params, ctx->idf("WRITE_WIDTH_%c", port), 18);
+                int we_width;
+                if (ci->type == id_RAMB36E1)
+                    we_width = 4;
+                else
+                    we_width = (port == 'B') ? 4 : 2;
+                if (write_width >= (9 * we_width))
+                    continue;
+                int used_we_width = std::max(write_width / 9, 1);
+                for (int i = used_we_width; i < we_width; i++) {
+                    NetInfo *low_we = ci->getPort(ctx->id(std::string(port == 'B' ? "WEBWE[" : "WEA[") +
+                                                          std::to_string(i % used_we_width) + "]"));
+                    IdString curr_we = ctx->id(std::string(port == 'B' ? "WEBWE[" : "WEA[") + std::to_string(i) + "]");
+                    if (!ci->ports.count(curr_we)) {
+                        ci->ports[curr_we].type = PORT_IN;
+                        ci->ports[curr_we].name = curr_we;
+                    }
+                    ci->disconnectPort(curr_we);
+                    ci->connectPort(curr_we, low_we);
+                }
+            }
+        }
+    }
+
+    generic_xform(bram_rules, false);
+
+    // These pins have no logical mapping, so must be tied after transformation
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_RAMB18E1_RAMB18E1) {
+            int wwa = int_or_default(ci->params, id_WRITE_WIDTH_A, 0);
+            for (int i = ((wwa == 0) ? 0 : 2); i < 4; i++) {
+                IdString port = ctx->idf("WEA%d", i);
+                if (!ci->ports.count(port)) {
+                    ci->ports[port].name = port;
+                    ci->ports[port].type = PORT_IN;
+                    ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                }
+            }
+            int wwb = int_or_default(ci->params, id_WRITE_WIDTH_B, 0);
+            if (wwb != 36) {
+                for (int i = 4; i < 8; i++) {
+                    IdString port = ctx->id("WEBWE" + std::to_string(i));
+                    if (!ci->ports.count(port)) {
+                        ci->ports[port].name = port;
+                        ci->ports[port].type = PORT_IN;
+                        ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                    }
+                }
+            }
+            for (auto p : {id_ADDRATIEHIGH0, id_ADDRATIEHIGH1, id_ADDRBTIEHIGH0, id_ADDRBTIEHIGH1}) {
+                if (!ci->ports.count(p)) {
+                    ci->ports[p].name = p;
+                    ci->ports[p].type = PORT_IN;
+                } else {
+                    ci->disconnectPort(p);
+                }
+                ci->connectPort(p, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            }
+        } else if (ci->type == id_RAMB36E1_RAMB36E1) {
+            for (auto p : {id_ADDRARDADDRL15, id_ADDRBWRADDRL15}) {
+                if (!ci->ports.count(p)) {
+                    ci->ports[p].name = p;
+                    ci->ports[p].type = PORT_IN;
+                } else {
+                    ci->disconnectPort(p);
+                }
+                ci->connectPort(p, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            }
+            if (int_or_default(ci->params, id_WRITE_WIDTH_A, 0) == 1) {
+                ci->disconnectPort(id_DIADI1);
+                ci->connectPort(id_DIADI1, ci->getPort(id_DIADI0));
+                ci->attrs[id_X_ORIG_PORT_DIADI1] = std::string("DIADI[0]");
+                ci->disconnectPort(id_DIPADIP0);
+                ci->disconnectPort(id_DIPADIP1);
+            }
+            if (int_or_default(ci->params, id_WRITE_WIDTH_B, 0) == 1) {
+                ci->disconnectPort(id_DIBDI1);
+                ci->connectPort(id_DIBDI1, ci->getPort(id_DIBDI0));
+                ci->attrs[id_X_ORIG_PORT_DIBDI1] = std::string("DIBDI[0]");
+                ci->disconnectPort(id_DIPBDIP0);
+                ci->disconnectPort(id_DIPBDIP1);
+            }
+            if (int_or_default(ci->params, id_WRITE_WIDTH_B, 0) != 72) {
+                for (std::string s : {"L", "U"}) {
+                    for (int i = 4; i < 8; i++) {
+                        IdString port = ctx->idf("WEBWE%s%d", s.c_str(), i);
+                        if (!ci->ports.count(port)) {
+                            ci->ports[port].name = port;
+                            ci->ports[port].type = PORT_IN;
+                            ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                        }
+                    }
+                }
+            } else {
+                // Tie WEA low
+                for (std::string s : {"L", "U"}) {
+                    for (int i = 0; i < 4; i++) {
+                        IdString port = ctx->idf("WEA%s%d", s.c_str(), i);
+                        if (!ci->ports.count(port)) {
+                            ci->ports[port].name = port;
+                            ci->ports[port].type = PORT_IN;
+                            ci->connectPort(port, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                        }
+                    }
+                }
+            }
+        }
+    }
+}
+
+void XilinxPacker::pack_inverters()
+{
+    // FIXME: fold where possible
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_INV) {
+            ci->params[id_INIT] = Property(1, 2);
+            ci->renamePort(id_I, id_I0);
+            ci->type = id_LUT1;
+        }
+    }
+}
+
+void XilinxImpl::pack()
+{
+    const ArchArgs &args = ctx->args;
+    if (args.options.count("xdc")) {
+        parse_xdc(args.options.at("xdc"));
+    }
+
+    XC7Packer packer(ctx, this);
+    packer.pack_constants();
+    packer.pack_inverters();
+    packer.pack_io();
+    packer.prepare_clocking();
+    packer.pack_constants();
+    // packer.pack_iologic();
+    // packer.pack_idelayctrl();
+    packer.pack_clocking();
+    packer.pack_muxfs();
+    packer.pack_carries();
+    packer.pack_srls();
+    packer.pack_luts();
+    packer.pack_dram();
+    packer.pack_bram();
+    // packer.pack_dsps();
+    packer.pack_ffs();
+    packer.finalise_muxfs();
+    packer.pack_lutffs();
+}
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/pack.h b/himbaechel/uarch/xilinx/pack.h
new file mode 100644
index 0000000000..130949581e
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack.h
@@ -0,0 +1,218 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-23  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pins.h"
+#include "xilinx.h"
+
+#ifndef HB_XILINX_PACK_H
+#define HB_XILINX_PACK_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct XilinxPacker
+{
+    Context *ctx;
+    XilinxImpl *uarch;
+
+    XilinxPacker(Context *ctx, XilinxImpl *uarch) : ctx(ctx), uarch(uarch){};
+
+    // Generic cell transformation
+    // Given cell name map and port map
+    // If port name is not found in port map; it will be copied as-is but stripping []
+    struct XFormRule
+    {
+        IdString new_type;
+        dict<IdString, IdString> port_xform;
+        dict<IdString, std::vector<IdString>> port_multixform;
+        dict<IdString, IdString> param_xform;
+        std::vector<std::pair<IdString, std::string>> set_attrs;
+        std::vector<std::pair<IdString, Property>> set_params;
+    };
+
+    // Distributed RAM control set
+    struct DRAMControlSet
+    {
+        std::vector<NetInfo *> wa;
+        NetInfo *wclk, *we;
+        bool wclk_inv;
+        IdString memtype;
+
+        bool operator==(const DRAMControlSet &other) const
+        {
+            return wa == other.wa && wclk == other.wclk && we == other.we && wclk_inv == other.wclk_inv &&
+                   memtype == other.memtype;
+        }
+        bool operator!=(const DRAMControlSet &other) const
+        {
+            return wa != other.wa || wclk != other.wclk || we != other.we || wclk_inv != other.wclk_inv ||
+                   memtype != other.memtype;
+        }
+        unsigned int hash() const
+        {
+            unsigned seed = 0;
+            seed = mkhash(seed, wa.size());
+            for (auto abit : wa)
+                seed = mkhash(seed, (abit == nullptr ? IdString() : abit->name).hash());
+            seed = mkhash(seed, (wclk == nullptr ? IdString() : wclk->name).hash());
+            seed = mkhash(seed, (we == nullptr ? IdString() : we->name).hash());
+            seed = mkhash(seed, wclk_inv);
+            seed = mkhash(seed, memtype.hash());
+            return seed;
+        }
+    };
+
+    struct DRAMType
+    {
+        int abits;
+        int dbits;
+        int rports;
+    };
+
+    struct CarryGroup
+    {
+        std::vector<CellInfo *> muxcys;
+        std::vector<CellInfo *> xorcys;
+    };
+
+    pool<IdString> packed_cells;
+
+    // General helper functions
+    void flush_cells();
+
+    void xform_cell(const dict<IdString, XFormRule> &rules, CellInfo *ci);
+    void generic_xform(const dict<IdString, XFormRule> &rules, bool print_summary = false);
+
+    CellInfo *feed_through_lut(NetInfo *net, const std::vector<PortRef> &feed_users);
+    CellInfo *feed_through_muxf(NetInfo *net, IdString type, const std::vector<PortRef> &feed_users);
+
+    IdString int_name(IdString base, const std::string &postfix, bool is_hierarchy = true);
+    NetInfo *create_internal_net(IdString base, const std::string &postfix, bool is_hierarchy = true);
+    void rename_net(IdString old, IdString newname);
+
+    void tie_port(CellInfo *ci, const std::string &port, bool value, bool inv = false);
+
+    // LUTs & FFs
+    void pack_inverters();
+    void pack_luts();
+    void pack_ffs();
+    void pack_lutffs();
+
+    bool is_constrained(const CellInfo *cell);
+    void pack_muxfs();
+    void finalise_muxfs();
+    void legalise_muxf_tree(CellInfo *curr, std::vector<CellInfo *> &mux_roots);
+    void constrain_muxf_tree(CellInfo *curr, CellInfo *base, int zoffset);
+    void create_muxf_tree(CellInfo *base, const std::string &name_base, const std::vector<NetInfo *> &data,
+                          const std::vector<NetInfo *> &select, NetInfo *out, int zoffset);
+
+    void pack_srls();
+
+    void split_carry4s();
+
+    // DistRAM
+    dict<IdString, XFormRule> dram_rules, dram32_6_rules, dram32_5_rules;
+    CellInfo *create_dram_lut(const std::string &name, CellInfo *base, const DRAMControlSet &ctrlset,
+                              std::vector<NetInfo *> address, NetInfo *di, NetInfo *dout, int z);
+    CellInfo *create_dram32_lut(const std::string &name, CellInfo *base, const DRAMControlSet &ctrlset,
+                                std::vector<NetInfo *> address, NetInfo *di, NetInfo *dout, bool o5, int z);
+    void pack_dram();
+
+    // Constant pins
+    dict<IdString, dict<IdString, bool>> tied_pins;
+    dict<IdString, pool<IdString>> invertible_pins;
+    void pack_constants();
+
+    // IO
+    dict<IdString, pool<IdString>> toplevel_ports;
+    NetInfo *invert_net(NetInfo *toinv);
+    CellInfo *insert_obuf(IdString name, IdString type, NetInfo *i, NetInfo *o, NetInfo *tri = nullptr);
+    CellInfo *insert_outinv(IdString name, NetInfo *i, NetInfo *o);
+    std::pair<CellInfo *, PortRef> insert_pad_and_buf(CellInfo *npnr_io);
+    CellInfo *create_iobuf(CellInfo *npnr_io, IdString &top_port);
+
+    // Clocking
+    BelId find_bel_with_short_route(WireId source, IdString beltype, IdString belpin);
+    void try_preplace(CellInfo *cell, IdString port);
+    void preplace_unique(CellInfo *cell);
+
+    // Cell creating
+    CellInfo *create_cell(IdString type, IdString name);
+    CellInfo *create_lut(const std::string &name, const std::vector<NetInfo *> &inputs, NetInfo *output,
+                         const Property &init);
+
+    int autoidx = 0;
+};
+
+struct XC7Packer : public XilinxPacker
+{
+    XC7Packer(Context *ctx, XilinxImpl *uarch) : XilinxPacker(ctx, uarch){};
+
+    // Carries
+    bool has_illegal_fanout(NetInfo *carry);
+    void pack_carries();
+
+    // IO
+    CellInfo *insert_ibuf(IdString name, IdString type, NetInfo *i, NetInfo *o);
+    CellInfo *insert_diffibuf(IdString name, IdString type, const std::array<NetInfo *, 2> &i, NetInfo *o);
+
+    void decompose_iob(CellInfo *xil_iob, bool is_hr, const std::string &iostandard);
+    void pack_io();
+
+    // IOLOGIC
+    dict<IdString, XFormRule> hp_iol_rules, hd_iol_rules, ioctrl_rules;
+    void fold_inverter(CellInfo *cell, std::string port);
+    std::string get_ologic_site(const std::string &io_bel);
+    std::string get_ilogic_site(const std::string &io_bel);
+    std::string get_ioctrl_site(const std::string &io_bel);
+    std::string get_odelay_site(const std::string &io_bel);
+    std::string get_idelay_site(const std::string &io_bel);
+    // Call before packing constants
+    void prepare_iologic();
+
+    void pack_iologic();
+    void pack_idelayctrl();
+
+    // Clocking
+    void prepare_clocking();
+    void pack_plls();
+    void pack_gbs();
+    void pack_clocking();
+
+    // BRAM
+    void pack_bram();
+
+    // DSP
+    void pack_dsps();
+
+  private:
+    void walk_dsp(CellInfo *root, CellInfo *ci, int constr_z);
+    void check_valid_pad(CellInfo *ci, std::string type);
+};
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/uarch/xilinx/pack_carry.cc b/himbaechel/uarch/xilinx/pack_carry.cc
new file mode 100644
index 0000000000..5382f3de41
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack_carry.cc
@@ -0,0 +1,405 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pack.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool XC7Packer::has_illegal_fanout(NetInfo *carry)
+{
+    // FIXME: sometimes we can feed out of the chain
+    if (carry->users.entries() > 2)
+        return true;
+    CellInfo *muxcy = nullptr, *xorcy = nullptr;
+    for (auto &usr : carry->users) {
+        if (usr.cell->type == id_MUXCY) {
+            if (muxcy != nullptr)
+                return true;
+            else if (usr.port != id_CI)
+                return true;
+            else
+                muxcy = usr.cell;
+        } else if (usr.cell->type == id_XORCY) {
+            if (xorcy != nullptr)
+                return true;
+            else if (usr.port != id_CI)
+                return true;
+            else
+                xorcy = usr.cell;
+        } else {
+            return true;
+        }
+    }
+    if (muxcy && xorcy) {
+        NetInfo *muxcy_s = muxcy->getPort(id_S);
+        NetInfo *xorcy_li = xorcy->getPort(id_LI);
+        if (muxcy_s != xorcy_li)
+            return true;
+    }
+    return false;
+}
+
+void XilinxPacker::split_carry4s()
+{
+    std::vector<CellInfo *> carry4s;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_CARRY4)
+            continue;
+        carry4s.push_back(ci);
+    }
+    for (CellInfo *ci : carry4s) {
+        NetInfo *cin = ci->getPort(id_CI);
+        if (cin == nullptr || cin->name == ctx->id("$PACKER_GND_NET")) {
+            cin = ci->getPort(id_CYINIT);
+        }
+        ci->disconnectPort(id_CI);
+        ci->disconnectPort(id_CYINIT);
+
+        for (int i = 0; i < 4; i++) {
+            CellInfo *xorcy = create_cell(id_XORCY, ctx->idf("%s$split$xorcy%d", ci->name.c_str(ctx), i));
+            CellInfo *muxcy = create_cell(id_MUXCY, ctx->idf("%s$split$muxcy%d", ci->name.c_str(ctx), i));
+            muxcy->connectPort(id_CI, cin);
+            xorcy->connectPort(id_CI, cin);
+            ci->movePortTo(ctx->idf("DI[%d]", i), muxcy, id_DI);
+            muxcy->connectPort(id_S, ci->getPort(ctx->id("S[" + std::to_string(i) + "]")));
+            ci->movePortTo(ctx->idf("S[%d]", i), xorcy, id_LI);
+            ci->movePortTo(ctx->idf("O[%d]", i), xorcy, id_O);
+            NetInfo *co = ci->getPort(ctx->idf("CO[%d]", i));
+            ci->disconnectPort(ctx->idf("CO[%d]", i));
+            if (!co)
+                co = create_internal_net(ci->name, stringf("$split$co%d", i), false);
+            muxcy->connectPort(id_O, co);
+            cin = co;
+        }
+        packed_cells.insert(ci->name);
+    }
+    flush_cells();
+}
+
+void XC7Packer::pack_carries()
+{
+    log_info("Packing carries..\n");
+    split_carry4s();
+    std::vector<CellInfo *> root_muxcys;
+    // Find MUXCYs
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_MUXCY)
+            continue;
+        NetInfo *ci_net = ci->getPort(id_CI);
+        if (!ci_net || !ci_net->driver.cell || ci_net->driver.cell->type != id_MUXCY || has_illegal_fanout(ci_net)) {
+            root_muxcys.push_back(ci);
+        }
+    }
+
+    // Create chains from root MUXCYs
+    pool<IdString> processed_muxcys;
+    std::vector<CarryGroup> groups;
+    int muxcy_count = 0, xorcy_count = 0;
+    for (auto root : root_muxcys) {
+        CarryGroup group;
+
+        CellInfo *muxcy = root;
+        NetInfo *mux_ci = nullptr;
+        while (true) {
+
+            group.muxcys.push_back(muxcy);
+            ++muxcy_count;
+            mux_ci = muxcy->getPort(id_CI);
+            NetInfo *mux_s = muxcy->getPort(id_S);
+            group.xorcys.push_back(nullptr);
+            if (mux_s != nullptr) {
+                for (auto &user : mux_s->users) {
+                    if (user.cell->type == id_XORCY && user.port == id_LI) {
+                        CellInfo *xorcy = user.cell;
+                        NetInfo *xor_ci = xorcy->getPort(id_CI);
+                        if (xor_ci == mux_ci) {
+                            group.xorcys.back() = xorcy;
+                            ++xorcy_count;
+                            break;
+                        }
+                    }
+                }
+            }
+
+            mux_ci = muxcy->getPort(id_O);
+            if (mux_ci == nullptr)
+                break;
+            if (has_illegal_fanout(mux_ci))
+                break;
+            muxcy = nullptr;
+            for (auto &user : mux_ci->users) {
+                if (user.cell->type == id_MUXCY) {
+                    muxcy = user.cell;
+                    break;
+                }
+            }
+            if (muxcy == nullptr)
+                break;
+        }
+        if (mux_ci != nullptr) {
+            if (mux_ci->users.entries() == 1 && (*mux_ci->users.begin()).cell->type == id_XORCY &&
+                (*mux_ci->users.begin()).port == id_CI) {
+                // Trailing XORCY at end, can pack into chain.
+                CellInfo *xorcy = (*mux_ci->users.begin()).cell;
+                CellInfo *dummy_muxcy = create_cell(id_MUXCY, ctx->idf("%s$legal_muxcy$", xorcy->name.c_str(ctx)));
+                dummy_muxcy->connectPort(id_CI, mux_ci);
+                dummy_muxcy->connectPort(id_S, xorcy->getPort(id_LI));
+                group.muxcys.push_back(dummy_muxcy);
+                group.xorcys.push_back(xorcy);
+            } else if (mux_ci->users.entries() > 0) {
+                // Users other than a MUXCY
+                // Feed out with a zero-driving LUT and a XORCY
+                // (creating a zero-driver using Vcc and an inverter for now...)
+                CellInfo *zero_lut = create_lut(mux_ci->name.str(ctx) + "$feed$zero",
+                                                {ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get()}, nullptr, Property(1));
+                CellInfo *feed_xorcy = create_cell(id_XORCY, ctx->id(mux_ci->name.str(ctx) + "$feed$xor"));
+                CellInfo *dummy_muxcy = create_cell(id_MUXCY, ctx->id(mux_ci->name.str(ctx) + "$feed$muxcy"));
+
+                CellInfo *last_muxcy = mux_ci->driver.cell;
+
+                last_muxcy->disconnectPort(id_O);
+
+                zero_lut->connectPorts(id_O, feed_xorcy, id_LI);
+                zero_lut->connectPorts(id_O, dummy_muxcy, id_S);
+                last_muxcy->connectPorts(id_O, feed_xorcy, id_CI);
+                last_muxcy->connectPorts(id_O, dummy_muxcy, id_CI);
+
+                feed_xorcy->connectPort(id_O, mux_ci);
+
+                group.muxcys.push_back(dummy_muxcy);
+                group.xorcys.push_back(feed_xorcy);
+            }
+        }
+
+        groups.push_back(group);
+    }
+    flush_cells();
+
+    log_info("   Grouped %d MUXCYs and %d XORCYs into %d chains.\n", muxcy_count, xorcy_count, int(root_muxcys.size()));
+
+    // N.B. LUT6 is not a valid type here, as CARRY requires dual outputs
+    pool<IdString> lut_types{id_LUT1, id_LUT2, id_LUT3, id_LUT4, id_LUT5};
+
+    pool<IdString> folded_nets;
+
+    for (auto &grp : groups) {
+        std::vector<CellInfo *> carry4s;
+        for (int i = 0; i < int(grp.muxcys.size()); i++) {
+            int z = i % 4;
+            CellInfo *muxcy = grp.muxcys.at(i), *xorcy = grp.xorcys.at(i);
+            if (z == 0)
+                carry4s.push_back(create_cell(id_CARRY4, ctx->idf("%s$PACKED_CARRY4$", muxcy->name.c_str(ctx))));
+            CellInfo *c4 = carry4s.back();
+            CellInfo *root = carry4s.front();
+            if (i == 0) {
+                // Constrain initial CARRY4, forcing it to the CARRY4 of a logic tile
+                c4->cluster = c4->name;
+                c4->constr_abs_z = true;
+                c4->constr_z = BEL_CARRY4;
+            } else if (z == 0) {
+                // Constrain relative to the root carry4
+                c4->cluster = root->name;
+                root->constr_children.push_back(c4);
+                c4->constr_x = 0;
+                // Looks no CARRY4 on the tile of which grid_y is a multiple of 26. Skip them
+                c4->constr_y = -(i / 4 + i / (4 * 25));
+                c4->constr_abs_z = true;
+                c4->constr_z = BEL_CARRY4;
+            }
+            // Fold CI->CO connections into the CARRY4, except for those external ones every 8 units
+            if (z == 0 && i == 0) {
+                muxcy->movePortTo(id_CI, c4, id_CYINIT);
+            } else if (z == 0 && i > 0) {
+                muxcy->movePortTo(id_CI, c4, id_CI);
+            } else {
+                NetInfo *muxcy_ci = muxcy->getPort(id_CI);
+                if (muxcy_ci)
+                    folded_nets.insert(muxcy_ci->name);
+                muxcy->disconnectPort(id_CI);
+            }
+            if (z == 3) {
+                muxcy->movePortTo(id_O, c4, ctx->id("CO[3]"));
+            } else {
+                NetInfo *muxcy_o = muxcy->getPort(id_O);
+                if (muxcy_o)
+                    folded_nets.insert(muxcy_o->name);
+                muxcy->disconnectPort(id_O);
+            }
+            // Replace connections into the MUXCY with external CARRY4 ports
+            muxcy->movePortTo(id_S, c4, ctx->idf("S[%d]", z));
+            muxcy->movePortTo(id_DI, c4, ctx->idf("DI[%d]", z));
+            packed_cells.insert(muxcy->name);
+            // Fold MUXCY->XORCY into the CARRY4, if there is a XORCY
+            if (xorcy) {
+                // Replace XORCY output with external CARRY4 output
+                xorcy->movePortTo(id_O, c4, ctx->idf("O[%d]", z));
+                // Disconnect internal XORCY connectivity
+                xorcy->disconnectPort(id_LI);
+                xorcy->disconnectPort(id_DI);
+                packed_cells.insert(xorcy->name);
+            }
+            // Check legality of LUTs driving CARRY4, making them legal if they aren't already
+            NetInfo *c4_s = c4->getPort(ctx->idf("S[%d]", z));
+            NetInfo *c4_di = c4->getPort(ctx->idf("DI[%d]", z));
+            // Keep track of the total LUT input count; cannot exceed five or the LUTs cannot be packed together
+            pool<IdString> unique_lut_inputs;
+            int s_inputs = 0, d_inputs = 0;
+            // Check that S and DI are validy and unqiuely driven by LUTs
+            // FIXME: in multiple fanout cases, cell duplication will probably be cheaper
+            // than feed-throughs
+            CellInfo *s_lut = nullptr, *di_lut = nullptr;
+            if (c4_s) {
+                if (c4_s->users.entries() == 1 && c4_s->driver.cell != nullptr &&
+                    lut_types.count(c4_s->driver.cell->type)) {
+                    s_lut = c4_s->driver.cell;
+                    for (int j = 0; j < 5; j++) {
+                        NetInfo *ix = s_lut->getPort(ctx->idf("I%d", j));
+                        if (ix) {
+                            unique_lut_inputs.insert(ix->name);
+                            s_inputs++;
+                        }
+                    }
+                }
+            }
+            if (c4_di) {
+                if (c4_di->users.entries() == 1 && c4_di->driver.cell != nullptr &&
+                    lut_types.count(c4_di->driver.cell->type)) {
+                    di_lut = c4_di->driver.cell;
+                    for (int j = 0; j < 5; j++) {
+                        NetInfo *ix = di_lut->getPort(ctx->idf("I%d", j));
+                        if (ix) {
+                            unique_lut_inputs.insert(ix->name);
+                            d_inputs++;
+                        }
+                    }
+                }
+            }
+            int lut_inp_count = int(unique_lut_inputs.size());
+            if (!s_lut)
+                ++lut_inp_count; // for feedthrough
+            if (!di_lut)
+                ++lut_inp_count; // for feedthrough
+            if (lut_inp_count > 5) {
+                // Must use feedthrough for at least one LUT
+                di_lut = nullptr;
+                if (s_inputs > 4)
+                    s_lut = nullptr;
+            }
+            // If LUTs are nullptr, that means we need a feedthrough lut
+            if (!s_lut && c4_s) {
+                PortRef pr;
+                pr.cell = c4;
+                pr.port = ctx->idf("S[%d]", z);
+                auto s_feed = feed_through_lut(c4_s, {pr});
+                s_lut = s_feed;
+            }
+            if (!di_lut && c4_di) {
+                PortRef pr;
+                pr.cell = c4;
+                pr.port = ctx->idf("DI[%d]", z);
+                auto di_feed = feed_through_lut(c4_di, {pr});
+                di_lut = di_feed;
+            }
+            // Constrain LUTs relative to root CARRY4
+            if (s_lut) {
+                root->constr_children.push_back(s_lut);
+                s_lut->cluster = root->name;
+                s_lut->constr_x = 0;
+                s_lut->constr_y = -(i / 4 + i / (4 * 25));
+                s_lut->constr_abs_z = true;
+                s_lut->constr_z = (z << 4 | BEL_6LUT);
+            }
+            if (di_lut) {
+                root->constr_children.push_back(di_lut);
+                di_lut->cluster = root->name;
+                di_lut->constr_x = 0;
+                di_lut->constr_y = -(i / 4 + i / (4 * 25));
+                di_lut->constr_abs_z = true;
+                di_lut->constr_z = (z << 4 | BEL_5LUT);
+            }
+        }
+    }
+    flush_cells();
+
+    for (auto net : folded_nets)
+        ctx->nets.erase(net);
+
+    // XORCYs and MUXCYs not part of any chain (and therefore not packed into a CARRY4) must now be blasted
+    // to boring soft logic (LUT2 or LUT3 - these will become SLICE_LUTXs later in the flow.)
+    int remaining_muxcy = 0, remaining_xorcy = 0;
+    for (auto &cell : ctx->cells) {
+        if (cell.second->type == id_MUXCY)
+            ++remaining_muxcy;
+        else if (cell.second->type == id_XORCY)
+            ++remaining_xorcy;
+    }
+    dict<IdString, XFormRule> softlogic_rules;
+    softlogic_rules[id_MUXCY].new_type = id_LUT3;
+    softlogic_rules[id_MUXCY].port_xform[id_DI] = id_I0;
+    softlogic_rules[id_MUXCY].port_xform[id_CI] = id_I1;
+    softlogic_rules[id_MUXCY].port_xform[id_S] = id_I2;
+    // DI 1010 1010
+    // CI 1100 1100
+    //  S 1111 0000
+    //  O 1100 1010
+    softlogic_rules[id_MUXCY].set_params.emplace_back(id_INIT, Property(0xCA));
+
+    softlogic_rules[id_XORCY].new_type = id_LUT2;
+    softlogic_rules[id_XORCY].port_xform[id_CI] = id_I0;
+    softlogic_rules[id_XORCY].port_xform[id_LI] = id_I1;
+    // CI 1100
+    // LI 1010
+    //  O 0110
+    softlogic_rules[id_XORCY].set_params.emplace_back(id_INIT, Property(0x6));
+
+    generic_xform(softlogic_rules, false);
+    log_info("   Blasted %d non-chain MUXCYs and %d non-chain XORCYs to soft logic\n", remaining_muxcy,
+             remaining_xorcy);
+
+    // Finally, use generic_xform to remove the [] from bus ports; and set up the logical-physical mapping for
+    // RapidWright
+    dict<IdString, XFormRule> c4_rules;
+    c4_rules[id_CARRY4].new_type = id_CARRY4;
+    c4_rules[id_CARRY4].port_xform[id_CI] = id_CIN;
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_CARRY4)
+            continue;
+        xform_cell(c4_rules, ci);
+    }
+}
+
+NEXTPNR_NAMESPACE_END
\ No newline at end of file
diff --git a/himbaechel/uarch/xilinx/pack_clocking.cc b/himbaechel/uarch/xilinx/pack_clocking.cc
new file mode 100644
index 0000000000..eb743f22eb
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack_clocking.cc
@@ -0,0 +1,350 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pack.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+BelId XilinxPacker::find_bel_with_short_route(WireId source, IdString beltype, IdString belpin)
+{
+    if (source == WireId())
+        return BelId();
+    const size_t max_visit = 50000; // effort/runtime tradeoff
+    pool<WireId> visited;
+    std::queue<WireId> visit;
+    visit.push(source);
+    while (!visit.empty() && visited.size() < max_visit) {
+        WireId cursor = visit.front();
+        visit.pop();
+        for (auto bp : ctx->getWireBelPins(cursor))
+            if (bp.pin == belpin && ctx->getBelType(bp.bel) == beltype && ctx->checkBelAvail(bp.bel))
+                return bp.bel;
+        for (auto pip : ctx->getPipsDownhill(cursor)) {
+            WireId dst = ctx->getPipDstWire(pip);
+            if (visited.count(dst))
+                continue;
+            visit.push(dst);
+            visited.insert(dst);
+        }
+    }
+    return BelId();
+}
+
+void XilinxPacker::try_preplace(CellInfo *cell, IdString port)
+{
+    if (cell->attrs.count(id_BEL) || cell->bel != BelId())
+        return;
+    NetInfo *n = cell->getPort(port);
+    if (n == nullptr || n->driver.cell == nullptr)
+        return;
+    CellInfo *drv = n->driver.cell;
+    BelId drv_bel = drv->bel;
+    if (drv_bel == BelId())
+        return;
+    WireId drv_wire = ctx->getBelPinWire(drv_bel, n->driver.port);
+    if (drv_wire == WireId())
+        return;
+    BelId tgt = find_bel_with_short_route(drv_wire, cell->type, port);
+    if (tgt != BelId()) {
+        ctx->bindBel(tgt, cell, STRENGTH_LOCKED);
+        log_info("    Constrained %s '%s' to bel '%s' based on dedicated routing\n", cell->type.c_str(ctx),
+                 ctx->nameOf(cell), ctx->nameOfBel(tgt));
+    }
+}
+
+void XilinxPacker::preplace_unique(CellInfo *cell)
+{
+    if (cell->attrs.count(id_BEL) || cell->bel != BelId())
+        return;
+    for (auto bel : ctx->getBels()) {
+        if (ctx->checkBelAvail(bel) && ctx->getBelType(bel) == cell->type) {
+            ctx->bindBel(bel, cell, STRENGTH_LOCKED);
+            return;
+        }
+    }
+}
+
+void XC7Packer::prepare_clocking()
+{
+    log_info("Preparing clocking...\n");
+    dict<IdString, IdString> upgrade;
+    upgrade[id_MMCME2_BASE] = id_MMCME2_ADV;
+    upgrade[id_PLLE2_BASE] = id_PLLE2_ADV;
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (upgrade.count(ci->type)) {
+            IdString new_type = upgrade.at(ci->type);
+            ci->type = new_type;
+        } else if (ci->type == id_BUFG) {
+            ci->type = id_BUFGCTRL;
+            ci->renamePort(id_I, id_I0);
+            tie_port(ci, "CE0", true, true);
+            tie_port(ci, "S0", true, true);
+            tie_port(ci, "S1", false, true);
+            tie_port(ci, "IGNORE0", true, true);
+        } else if (ci->type == id_BUFGCE) {
+            ci->type = id_BUFGCTRL;
+            ci->renamePort(id_I, id_I0);
+            ci->renamePort(id_CE, id_CE0);
+            tie_port(ci, "S0", true, true);
+            tie_port(ci, "S1", false, true);
+            tie_port(ci, "IGNORE0", true, true);
+        }
+    }
+}
+
+void XC7Packer::pack_plls()
+{
+    log_info("Packing PLLs...\n");
+
+    auto set_default = [](CellInfo *ci, IdString param, const Property &value) {
+        if (!ci->params.count(param))
+            ci->params[param] = value;
+    };
+
+    dict<IdString, XFormRule> pll_rules;
+    pll_rules[id_MMCME2_ADV].new_type = id_MMCME2_ADV_MMCME2_ADV;
+    pll_rules[id_PLLE2_ADV].new_type = id_PLLE2_ADV_PLLE2_ADV;
+    generic_xform(pll_rules);
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        // Preplace PLLs to make use of dedicated/short routing paths
+        if (ci->type.in(id_MMCM_MMCM_TOP, id_PLL_PLL_TOP))
+            try_preplace(ci, id_CLKIN1);
+        if (ci->type == id_MMCM_MMCM_TOP) {
+            // Fixup parameters
+            for (int i = 1; i <= 2; i++)
+                set_default(ci, ctx->idf("CLKIN%d_PERIOD", i), Property("0.0"));
+            for (int i = 0; i <= 6; i++) {
+                set_default(ci, ctx->idf("CLKOUT%d_CASCADE", i), Property("FALSE"));
+                set_default(ci, ctx->idf("CLKOUT%d_DIVIDE", i), Property(1));
+                set_default(ci, ctx->idf("CLKOUT%d_DUTY_CYCLE", i), Property("0.5"));
+                set_default(ci, ctx->idf("CLKOUT%d_PHASE", i), Property(0));
+                set_default(ci, ctx->idf("CLKOUT%d_USE_FINE_PS", i), Property("FALSE"));
+            }
+            set_default(ci, id_COMPENSATION, Property("INTERNAL"));
+
+            // Fixup routing
+            if (str_or_default(ci->params, id_COMPENSATION, "INTERNAL") == "INTERNAL") {
+                ci->disconnectPort(id_CLKFBIN);
+                ci->connectPort(id_CLKFBIN, ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get());
+            }
+        }
+    }
+}
+
+void XC7Packer::pack_gbs()
+{
+    log_info("Packing global buffers...\n");
+    dict<IdString, XFormRule> gb_rules;
+    gb_rules[id_BUFGCTRL].new_type = id_BUFGCTRL;
+    gb_rules[id_BUFGCTRL].new_type = id_BUFGCTRL;
+
+    generic_xform(gb_rules);
+
+    // Make sure prerequisites are set up first
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_PS7_PS7)
+            preplace_unique(ci);
+        if (ci->type.in(id_PSEUDO_GND, id_PSEUDO_VCC))
+            preplace_unique(ci);
+    }
+
+    // Preplace global buffers to make use of dedicated/short routing
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_BUFGCTRL)
+            try_preplace(ci, id_I0);
+        if (ci->type == id_BUFG_BUFG)
+            try_preplace(ci, id_I);
+    }
+}
+
+void XC7Packer::pack_clocking()
+{
+    pack_plls();
+    pack_gbs();
+}
+
+void XilinxImpl::route_clocks()
+{
+    log_info("Routing global clocks...\n");
+    // Special pass for faster routing of global clock psuedo-net
+    for (auto &net : ctx->nets) {
+        NetInfo *clk_net = net.second.get();
+        if (!clk_net->driver.cell)
+            continue;
+
+        // check if we have a global clock net, skip otherwise
+        bool is_global = false;
+        if ((clk_net->driver.cell->type.in(id_BUFGCTRL, id_BUFCE_BUFG_PS, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV)) &&
+            clk_net->driver.port == id_O)
+            is_global = true;
+        else if (clk_net->driver.cell->type == id_PLLE2_ADV_PLLE2_ADV && clk_net->users.entries() == 1 &&
+                 ((*clk_net->users.begin()).cell->type.in(id_BUFGCTRL, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV)))
+            is_global = true;
+        else if (clk_net->users.entries() == 1 && (*clk_net->users.begin()).cell->type == id_PLLE2_ADV_PLLE2_ADV &&
+                 (*clk_net->users.begin()).port == id_CLKIN1)
+            is_global = true;
+        if (!is_global)
+            continue;
+
+        log_info("    routing clock '%s'\n", clk_net->name.c_str(ctx));
+        ctx->bindWire(ctx->getNetinfoSourceWire(clk_net), clk_net, STRENGTH_LOCKED);
+
+        for (auto &usr : clk_net->users) {
+            std::queue<WireId> visit;
+            dict<WireId, PipId> backtrace;
+            WireId dest = WireId();
+
+            auto sink_wire = ctx->getNetinfoSinkWire(clk_net, usr, 0);
+            if (ctx->debug) {
+                auto sink_wire_name = "(uninitialized)";
+                if (sink_wire != WireId())
+                    sink_wire_name = ctx->nameOfWire(sink_wire);
+                log_info("        routing arc to %s.%s (wire %s):\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
+                         sink_wire_name);
+            }
+
+            visit.push(sink_wire);
+            while (!visit.empty()) {
+                WireId curr = visit.front();
+                visit.pop();
+                if (ctx->getBoundWireNet(curr) == clk_net) {
+                    dest = curr;
+                    break;
+                }
+                for (auto uh : ctx->getPipsUphill(curr)) {
+                    if (!ctx->checkPipAvail(uh))
+                        continue;
+                    WireId src = ctx->getPipSrcWire(uh);
+                    if (backtrace.count(src))
+                        continue;
+                    IdString intent = ctx->getWireType(src);
+                    if (intent.in(id_NODE_DOUBLE, id_NODE_HLONG, id_NODE_HQUAD, id_NODE_VLONG, id_NODE_VQUAD,
+                                  id_NODE_SINGLE, id_NODE_CLE_OUTPUT, id_NODE_OPTDELAY, id_BENTQUAD, id_DOUBLE,
+                                  id_HLONG, id_HQUAD, id_OPTDELAY, id_SINGLE, id_VLONG, id_VLONG12, id_VQUAD,
+                                  id_PINBOUNCE))
+                        continue;
+                    if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != clk_net)
+                        continue;
+                    backtrace[src] = uh;
+                    visit.push(src);
+                }
+            }
+            if (dest == WireId()) {
+                log_info("            failed to find a route using dedicated resources.\n");
+                if (clk_net->users.entries() == 1 && (*clk_net->users.begin()).cell->type == id_PLLE2_ADV_PLLE2_ADV &&
+                    (*clk_net->users.begin()).port == id_CLKIN1) {
+                    // Due to some missing pips, currently special case more lenient solution
+                    std::queue<WireId> empty;
+                    std::swap(visit, empty);
+                    backtrace.clear();
+                    visit.push(sink_wire);
+                    while (!visit.empty()) {
+                        WireId curr = visit.front();
+                        visit.pop();
+                        if (ctx->getBoundWireNet(curr) == clk_net) {
+                            dest = curr;
+                            break;
+                        }
+                        for (auto uh : ctx->getPipsUphill(curr)) {
+                            if (!ctx->checkPipAvail(uh))
+                                continue;
+                            WireId src = ctx->getPipSrcWire(uh);
+                            if (backtrace.count(src))
+                                continue;
+                            if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != clk_net)
+                                continue;
+                            backtrace[src] = uh;
+                            visit.push(src);
+                        }
+                    }
+                    if (dest == WireId())
+                        continue;
+                } else {
+                    continue;
+                }
+            }
+            while (backtrace.count(dest)) {
+                auto uh = backtrace[dest];
+                dest = ctx->getPipDstWire(uh);
+                if (ctx->getBoundWireNet(dest) == clk_net) {
+                    NPNR_ASSERT(clk_net->wires.at(dest).pip == uh);
+                    break;
+                }
+                if (ctx->debug)
+                    log_info("            bind pip %s --> %s\n", ctx->nameOfPip(uh), ctx->nameOfWire(dest));
+                ctx->bindPip(uh, clk_net, STRENGTH_LOCKED);
+            }
+        }
+    }
+#if 0
+    for (auto& net : nets) {
+        NetInfo *ni = net.second.get();
+        for (auto &usr : ni->users) {
+            if (usr.cell->type != id_BUFGCTRL || usr.port != id_I0)
+                continue;
+            WireId dst = getCtx()->getNetinfoSinkWire(ni, usr, 0);
+            std::queue<WireId> visit;
+            visit.push(dst);
+            int i = 0;
+            while(!visit.empty() && i < 5000) {
+                WireId curr = visit.front();
+                visit.pop();
+                log("  %s\n", nameOfWire(curr));
+                for (auto pip : getPipsUphill(curr)) {
+                    auto &pd = locInfo(pip).pip_data[pip.index];
+                    log_info("    p %s sr %s (t %d s %d sv %d)\n", nameOfPip(pip), nameOfWire(getPipSrcWire(pip)), pd.flags, pd.site, pd.site_variant);
+                    if (!checkPipAvail(pip)) {
+                        log("      p unavail\n");
+                        continue;
+                    }
+                    WireId src = getPipSrcWire(pip);
+                    if (!checkWireAvail(src)) {
+                        log("      w unavail (%s)\n", nameOf(getBoundWireNet(src)));
+                        continue;
+                    }
+                    log_info("     p %s s %s\n", nameOfPip(pip), nameOfWire(src));
+                    visit.push(src);
+                }
+                ++i;
+            }
+        }
+    }
+#endif
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/pack_dram.cc b/himbaechel/uarch/xilinx/pack_dram.cc
new file mode 100644
index 0000000000..00f9d40869
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack_dram.cc
@@ -0,0 +1,477 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pack.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+CellInfo *XilinxPacker::create_dram_lut(const std::string &name, CellInfo *base, const DRAMControlSet &ctrlset,
+                                        std::vector<NetInfo *> address, NetInfo *di, NetInfo *dout, int z)
+{
+    CellInfo *dram_lut = create_cell(id_RAMD64E, ctx->id(name));
+    for (int i = 0; i < int(address.size()); i++)
+        dram_lut->connectPort(ctx->idf("RADR%d", i), address[i]);
+    dram_lut->connectPort(id_I, di);
+    dram_lut->connectPort(id_O, dout);
+    dram_lut->connectPort(id_CLK, ctrlset.wclk);
+    dram_lut->connectPort(id_WE, ctrlset.we);
+    for (int i = 0; i < int(ctrlset.wa.size()); i++)
+        dram_lut->connectPort(ctx->idf("WADR%d", i), ctrlset.wa[i]);
+    dram_lut->params[id_IS_WCLK_INVERTED] = ctrlset.wclk_inv ? 1 : 0;
+
+    xform_cell(dram_rules, dram_lut);
+
+    dram_lut->constr_abs_z = true;
+    dram_lut->constr_z = (z << 4) | BEL_6LUT;
+    if (base != nullptr) {
+        dram_lut->cluster = base->name;
+        dram_lut->constr_x = 0;
+        dram_lut->constr_y = 0;
+        base->constr_children.push_back(dram_lut);
+    }
+    if (base == nullptr) {
+        dram_lut->cluster = dram_lut->name;
+    }
+    return dram_lut;
+}
+
+CellInfo *XilinxPacker::create_dram32_lut(const std::string &name, CellInfo *base, const DRAMControlSet &ctrlset,
+                                          std::vector<NetInfo *> address, NetInfo *di, NetInfo *dout, bool o5, int z)
+{
+    CellInfo *dram_lut = create_cell(id_RAMD32, ctx->id(name));
+    for (int i = 0; i < int(address.size()); i++)
+        dram_lut->connectPort(ctx->idf("RADR%d", i), address[i]);
+    dram_lut->connectPort(id_I, di);
+    dram_lut->connectPort(id_O, dout);
+    dram_lut->connectPort(id_CLK, ctrlset.wclk);
+    dram_lut->connectPort(id_WE, ctrlset.we);
+    for (int i = 0; i < int(ctrlset.wa.size()); i++)
+        dram_lut->connectPort(ctx->idf("WADR%d", i), ctrlset.wa[i]);
+    dram_lut->params[id_IS_WCLK_INVERTED] = ctrlset.wclk_inv ? 1 : 0;
+
+    xform_cell(o5 ? dram32_5_rules : dram32_6_rules, dram_lut);
+
+    dram_lut->constr_abs_z = true;
+    dram_lut->constr_z = (z << 4) | (o5 ? BEL_5LUT : BEL_6LUT);
+    if (base != nullptr) {
+        dram_lut->cluster = base->name;
+        dram_lut->constr_x = 0;
+        dram_lut->constr_y = 0;
+        base->constr_children.push_back(dram_lut);
+    }
+    if (base == nullptr) {
+        dram_lut->cluster = dram_lut->name;
+    }
+    return dram_lut;
+}
+
+void XilinxPacker::create_muxf_tree(CellInfo *base, const std::string &name_base, const std::vector<NetInfo *> &data,
+                                    const std::vector<NetInfo *> &select, NetInfo *out, int zoffset)
+{
+    int levels = 0;
+    if (data.size() <= 2)
+        levels = 1;
+    else if (data.size() <= 4)
+        levels = 2;
+    else if (data.size() <= 8)
+        levels = 3;
+    else
+        NPNR_ASSERT_FALSE("muxf tree too large");
+    NPNR_ASSERT(int(select.size()) == levels);
+    std::vector<std::vector<NetInfo *>> int_data;
+    CellInfo *mux_root = nullptr;
+    int_data.push_back(data);
+    for (int i = 0; i < levels; i++) {
+        IdString mux_type;
+        if (i == 0)
+            mux_type = id_MUXF7;
+        else if (i == 1)
+            mux_type = id_MUXF8;
+        else if (i == 2)
+            mux_type = id_MUXF9;
+        else
+            NPNR_ASSERT_FALSE("unknown muxf type");
+        int_data.emplace_back();
+        auto &last = int_data.at(int_data.size() - 2);
+        for (int j = 0; j < int(last.size()) / 2; j++) {
+            NetInfo *output =
+                    (i == (levels - 1))
+                            ? out
+                            : create_internal_net(base->name, stringf("%s_muxq_%d_%d", name_base.c_str(), i, j), false);
+            int_data.back().push_back(output);
+            auto mux = create_cell(mux_type,
+                                   int_name(base->name, stringf("%s_muxf_%d_%d", name_base.c_str(), i, j), false));
+            mux->connectPort(id_I0, last.at(j * 2));
+            mux->connectPort(id_I1, last.at(j * 2 + 1));
+            mux->connectPort(id_S, select.at(i));
+            mux->connectPort(id_O, output);
+            if (i == (levels - 1))
+                mux_root = mux;
+        }
+    }
+    constrain_muxf_tree(mux_root, base, zoffset);
+}
+
+void XilinxPacker::pack_dram()
+{
+
+    log_info("Packing DRAM..\n");
+
+    dict<DRAMControlSet, std::vector<CellInfo *>> dram_groups;
+    dict<IdString, DRAMType> dram_types;
+
+    dram_types[id_RAM32X1S] = {5, 1, 0};
+    dram_types[id_RAM32X1D] = {5, 1, 1};
+    dram_types[id_RAM64X1S] = {6, 1, 0};
+    dram_types[id_RAM64X1D] = {6, 1, 1};
+    dram_types[id_RAM128X1S] = {7, 1, 0};
+    dram_types[id_RAM128X1D] = {7, 1, 1};
+    dram_types[id_RAM256X1S] = {8, 1, 0};
+    dram_types[id_RAM256X1D] = {8, 1, 1};
+    dram_types[id_RAM512X1S] = {9, 1, 0};
+    dram_types[id_RAM512X1D] = {9, 1, 1};
+
+    // Transform from RAMD64E UNISIM to SLICE_LUTX bel
+    dram_rules[id_RAMD64E].new_type = id_SLICE_LUTX;
+    dram_rules[id_RAMD64E].param_xform[id_IS_CLK_INVERTED] = id_IS_WCLK_INVERTED;
+    dram_rules[id_RAMD64E].set_attrs.emplace_back(id_X_LUT_AS_DRAM, "1");
+    for (int i = 0; i < 6; i++)
+        dram_rules[id_RAMD64E].port_xform[ctx->idf("RADR%d", i)] = ctx->idf("A%d", i + 1);
+    for (int i = 0; i < 8; i++)
+        dram_rules[id_RAMD64E].port_xform[ctx->idf("WADR%d", i)] = ctx->idf("WA%d", i + 1);
+    dram_rules[id_RAMD64E].port_xform[id_I] = id_DI1;
+    dram_rules[id_RAMD64E].port_xform[id_O] = id_O6;
+
+    // Rules for upper and lower RAMD32E
+    dram32_6_rules[id_RAMD32].new_type = id_SLICE_LUTX;
+    dram32_6_rules[id_RAMD32].param_xform[id_IS_CLK_INVERTED] = id_IS_WCLK_INVERTED;
+    dram32_6_rules[id_RAMD32].set_attrs.emplace_back(id_X_LUT_AS_DRAM, "1");
+    for (int i = 0; i < 5; i++)
+        dram32_6_rules[id_RAMD32].port_xform[ctx->idf("RADR%d", i)] = ctx->idf("A%d", i + 1);
+    for (int i = 0; i < 5; i++)
+        dram32_6_rules[id_RAMD32].port_xform[ctx->idf("WADR%d", i)] = ctx->idf("WA%d", i + 1);
+    dram32_6_rules[id_RAMD32].port_xform[id_I] = id_DI2;
+    dram32_6_rules[id_RAMD32].port_xform[id_O] = id_O6;
+
+    dram32_5_rules = dram32_6_rules;
+    dram32_5_rules[id_RAMD32].port_xform[id_I] = id_DI1;
+    dram32_5_rules[id_RAMD32].port_xform[id_O] = id_O5;
+
+    // Optimise DRAM with tied-low inputs, to more efficiently routeable tied-high inputs
+    int inverted_ports = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        auto dt_iter = dram_types.find(ci->type);
+        if (dt_iter == dram_types.end())
+            continue;
+        auto &dt = dt_iter->second;
+        for (int i = 0; i < std::min(dt.abits, 6); i++) {
+            IdString aport = ctx->idf(dt.abits <= 6 ? "A%d" : "A[%d]", i);
+            if (!ci->ports.count(aport))
+                continue;
+            NetInfo *anet = ci->getPort(aport);
+            if (anet == nullptr || anet->name != ctx->id("$PACKER_GND_NET"))
+                continue;
+            IdString raport;
+            if (dt.rports >= 1) {
+                NPNR_ASSERT(dt.rports == 1); // FIXME
+                raport = ctx->idf(dt.abits <= 6 ? "DPRA%d" : "DPRA[%d]", i);
+                NetInfo *ranet = ci->getPort(raport);
+                if (ranet == nullptr || ranet->name != ctx->id("$PACKER_GND_NET"))
+                    continue;
+            }
+            ci->disconnectPort(aport);
+            if (raport != IdString())
+                ci->disconnectPort(raport);
+            ci->connectPort(aport, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            if (raport != IdString())
+                ci->connectPort(raport, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
+            ++inverted_ports;
+            if (ci->params.count(id_INIT)) {
+                Property &init = ci->params[id_INIT];
+                for (int j = 0; j < int(init.str.size()); j++) {
+                    if (j & (1 << i))
+                        init.str[j] = init.str[j & ~(1 << i)];
+                }
+                init.update_intval();
+            }
+        }
+    }
+    log_info("   Transformed %d tied-low DRAM address inputs to be tied-high\n", inverted_ports);
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        auto dt_iter = dram_types.find(ci->type);
+        if (dt_iter == dram_types.end())
+            continue;
+        auto &dt = dt_iter->second;
+        DRAMControlSet dcs;
+        for (int i = 0; i < dt.abits; i++)
+            dcs.wa.push_back(ci->getPort(ctx->idf(dt.abits <= 6 ? "A%d" : "A[%d]", i)));
+        dcs.wclk = ci->getPort(id_WCLK);
+        dcs.we = ci->getPort(id_WE);
+        dcs.wclk_inv = bool_or_default(ci->params, id_IS_WCLK_INVERTED);
+        dcs.memtype = ci->type;
+        dram_groups[dcs].push_back(ci);
+    }
+
+    int height = /*ctx->xc7 ? 4 : 8*/ 4;
+    // Grouped DRAM
+    for (auto &group : dram_groups) {
+        auto &cs = group.first;
+        if (cs.memtype == id_RAM64X1D) {
+            int z = height - 1;
+            CellInfo *base = nullptr;
+            for (auto cell : group.second) {
+                NPNR_ASSERT(cell->type == id_RAM64X1D); // FIXME
+
+                int z_size = 0;
+                if (cell->getPort(id_SPO) != nullptr)
+                    z_size++;
+                if (cell->getPort(id_DPO) != nullptr)
+                    z_size++;
+
+                if (z == (height - 1) || (z - z_size + 1) < 0) {
+                    z = (height - 1);
+                    // Topmost cell is the write address input
+                    std::vector<NetInfo *> address(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
+                    base = create_dram_lut(cell->name.str(ctx) + "/ADDR", nullptr, cs, address, nullptr, nullptr, z);
+                    z--;
+                }
+
+                NetInfo *dpo = cell->getPort(id_DPO);
+                NetInfo *spo = cell->getPort(id_SPO);
+                cell->disconnectPort(id_DPO);
+                cell->disconnectPort(id_SPO);
+
+                NetInfo *di = cell->getPort(id_D);
+                if (spo != nullptr) {
+                    if (z == (height - 2)) {
+                        // Can fold DPO into address buffer
+                        base->connectPort(id_O6, spo);
+                        base->connectPort(id_DI1, di);
+                        if (cell->params.count(id_INIT))
+                            base->params[id_INIT] = cell->params[id_INIT];
+                    } else {
+                        std::vector<NetInfo *> address(cs.wa.begin(),
+                                                       cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
+                        CellInfo *dpr = create_dram_lut(cell->name.str(ctx) + "/SP", base, cs, address, di, spo, z);
+                        if (cell->params.count(id_INIT))
+                            dpr->params[id_INIT] = cell->params[id_INIT];
+                        z--;
+                    }
+                }
+
+                if (dpo != nullptr) {
+                    std::vector<NetInfo *> address;
+                    for (int i = 0; i < 6; i++)
+                        address.push_back(cell->getPort(ctx->id("DPRA" + std::to_string(i))));
+                    CellInfo *dpr = create_dram_lut(cell->name.str(ctx) + "/DP", base, cs, address, di, dpo, z);
+                    if (cell->params.count(id_INIT))
+                        dpr->params[id_INIT] = cell->params[id_INIT];
+                    z--;
+                }
+
+                packed_cells.insert(cell->name);
+            }
+        } else if (cs.memtype == id_RAM32X1D) {
+            int z = (height - 1);
+            CellInfo *base = nullptr;
+            for (auto cell : group.second) {
+                NPNR_ASSERT(cell->type == id_RAM32X1D);
+
+                int z_size = 0;
+                if (cell->getPort(id_SPO) != nullptr)
+                    z_size++;
+                if (cell->getPort(id_DPO) != nullptr)
+                    z_size++;
+
+                if (z == (height - 1) || (z - z_size + 1) < 0) {
+                    z = (height - 1);
+                    // Topmost cell is the write address input
+                    std::vector<NetInfo *> address(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 5));
+                    address.push_back(ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                    base = create_dram_lut(cell->name.str(ctx) + "/ADDR", nullptr, cs, address, nullptr, nullptr, z);
+                    z--;
+                }
+
+                NetInfo *dpo = cell->getPort(id_DPO);
+                NetInfo *spo = cell->getPort(id_SPO);
+                cell->disconnectPort(id_DPO);
+                cell->disconnectPort(id_SPO);
+
+                NetInfo *di = cell->getPort(id_D);
+                if (spo != nullptr) {
+                    if (z == (height - 2)) {
+                        // Can fold DPO into address buffer
+                        base->connectPort(id_O6, spo);
+                        base->connectPort(id_DI1, di);
+                        if (cell->params.count(id_INIT))
+                            base->params[id_INIT] = cell->params[id_INIT];
+                    } else {
+                        std::vector<NetInfo *> address(cs.wa.begin(),
+                                                       cs.wa.begin() + std::min<size_t>(cs.wa.size(), 5));
+                        address.push_back(ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                        CellInfo *dpr = create_dram_lut(cell->name.str(ctx) + "/SP", base, cs, address, di, spo, z);
+                        if (cell->params.count(id_INIT))
+                            dpr->params[id_INIT] = cell->params[id_INIT];
+                        z--;
+                    }
+                }
+
+                if (dpo != nullptr) {
+                    std::vector<NetInfo *> address;
+                    for (int i = 0; i < 5; i++)
+                        address.push_back(cell->getPort(ctx->idf("DPRA%d", i)));
+                    address.push_back(ctx->nets[ctx->id("$PACKER_GND_NET")].get());
+                    CellInfo *dpr = create_dram_lut(cell->name.str(ctx) + "/DP", base, cs, address, di, dpo, z);
+                    if (cell->params.count(id_INIT))
+                        dpr->params[id_INIT] = cell->params[id_INIT];
+                    z--;
+                }
+
+                packed_cells.insert(cell->name);
+            }
+        } else if (cs.memtype.in(id_RAM128X1D, id_RAM256X1D)) {
+            // Split these cells into write and read ports and associated mux tree
+            bool m256 = cs.memtype == id_RAM256X1D;
+            for (CellInfo *ci : group.second) {
+                auto init = get_or_default(ci->params, id_INIT, Property(0, m256 ? 256 : 128));
+                std::vector<NetInfo *> spo_pre, dpo_pre;
+                int z = (height - 1);
+
+                NetInfo *dpo = ci->getPort(id_DPO);
+                NetInfo *spo = ci->getPort(id_SPO);
+                ci->disconnectPort(id_DPO);
+                ci->disconnectPort(id_SPO);
+
+                // Low 6 bits of address - connect directly to RAM cells
+                std::vector<NetInfo *> addressw_64(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
+                // Upper bits of address - feed decode muxes
+                std::vector<NetInfo *> addressw_high(cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6), cs.wa.end());
+                CellInfo *base = nullptr;
+                // Combined write address/SPO read cells
+                for (int i = 0; i < (m256 ? 4 : 2); i++) {
+                    NetInfo *spo_i = create_internal_net(ci->name, stringf("SPO_%d", i), false);
+                    CellInfo *spr = create_dram_lut(ci->name.str(ctx) + "/ADDR" + std::to_string(i), base, cs,
+                                                    addressw_64, ci->getPort(id_D), spo_i, z);
+                    if (base == nullptr)
+                        base = spr;
+                    spo_pre.push_back(spo_i);
+                    spr->params[id_INIT] = init.extract(i * 64, 64);
+                    z--;
+                }
+                // Decode mux tree using MUXF[78]
+                create_muxf_tree(base, "SPO", spo_pre, addressw_high, spo, m256 ? 4 : 2);
+
+                std::vector<NetInfo *> addressr_64, addressr_high;
+                for (int i = 0; i < (m256 ? 8 : 7); i++) {
+                    (i >= 6 ? addressr_high : addressr_64)
+                            .push_back(ci->getPort(ctx->id("DPRA[" + std::to_string(i) + "]")));
+                }
+                // Read-only port cells
+                for (int i = 0; i < (m256 ? 4 : 2); i++) {
+                    NetInfo *dpo_i = create_internal_net(ci->name, stringf("DPO_%d", i), false);
+                    CellInfo *dpr = create_dram_lut(ci->name.str(ctx) + "/DPR" + std::to_string(i), base, cs,
+                                                    addressr_64, ci->getPort(id_D), dpo_i, z);
+                    dpo_pre.push_back(dpo_i);
+                    dpr->params[id_INIT] = init.extract(i * 64, 64);
+                    z--;
+                }
+                // Decode mux tree using MUXF[78]
+                create_muxf_tree(base, "DPO", dpo_pre, addressr_high, dpo, 0);
+
+                packed_cells.insert(ci->name);
+            }
+        }
+    }
+    // Whole-SLICE DRAM
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type.in(id_RAM64M, id_RAM32M)) {
+            bool is_64 = (cell.second->type == id_RAM64M);
+            int abits = is_64 ? 6 : 5;
+            int dbits = is_64 ? 1 : 2;
+            DRAMControlSet dcs;
+            for (int i = 0; i < abits; i++)
+                dcs.wa.push_back(ci->getPort(ctx->idf("ADDRD[%d]", i)));
+            dcs.wclk = ci->getPort(id_WCLK);
+            dcs.we = ci->getPort(id_WE);
+            dcs.wclk_inv = bool_or_default(ci->params, id_IS_WCLK_INVERTED);
+            CellInfo *base = nullptr;
+            int zoffset = /*ctx->xc7 ? 0 : 4*/ 0;
+            for (int i = 0; i < 4; i++) {
+                std::vector<NetInfo *> address;
+                for (int j = 0; j < abits; j++) {
+                    address.push_back(ci->getPort(ctx->idf("ADDR%c[%d]", 'A' + i, j)));
+                }
+                if (is_64) {
+                    NetInfo *di = ci->getPort(ctx->idf("DI%c", 'A' + i));
+                    NetInfo *dout = ci->getPort(ctx->idf("DO%c", 'A' + i));
+                    ci->disconnectPort(ctx->idf("DI%c", 'A' + i));
+                    ci->disconnectPort(ctx->idf("DO%c", 'A' + i));
+                    CellInfo *dram = create_dram_lut(stringf("%s/DPR%d", ctx->nameOf(ci), i), base, dcs, address, di,
+                                                     dout, zoffset + i);
+                    if (base == nullptr)
+                        base = dram;
+                    if (ci->params.count(ctx->idf("INIT%c", 'A' + i)))
+                        dram->params[id_INIT] = ci->params[ctx->idf("INIT%c", 'A' + i)];
+                } else {
+                    for (int j = 0; j < dbits; j++) {
+                        NetInfo *di = ci->getPort(ctx->idf("DI%c[%d]", 'A' + i, j));
+                        NetInfo *dout = ci->getPort(ctx->idf("DO%c[%d]", 'A' + i, j));
+                        ci->disconnectPort(ctx->idf("DI%c[%d]", 'A' + i, j));
+                        ci->disconnectPort(ctx->idf("DO%c[%d]", 'A' + i, j));
+                        CellInfo *dram = create_dram32_lut(stringf("%s/DPR%d_%d", ctx->nameOf(ci), i, j), base, dcs,
+                                                           address, di, dout, (j == 0), zoffset + i);
+                        if (base == nullptr)
+                            base = dram;
+                        if (ci->params.count(ctx->idf("INIT%c", 'A' + i))) {
+                            auto orig_init = ci->params.at(ctx->idf("INIT%c", 'A' + i)).extract(0, 64).as_bits();
+                            std::string init;
+                            for (int k = 0; k < 32; k++) {
+                                init.push_back(orig_init.at(k * 2 + j));
+                            }
+                            dram->params[id_INIT] = Property::from_string(init);
+                        }
+                    }
+                }
+            }
+            packed_cells.insert(ci->name);
+        }
+    }
+
+    flush_cells();
+}
+
+NEXTPNR_NAMESPACE_END
\ No newline at end of file
diff --git a/himbaechel/uarch/xilinx/pack_io.cc b/himbaechel/uarch/xilinx/pack_io.cc
new file mode 100644
index 0000000000..5bebbb9ccd
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack_io.cc
@@ -0,0 +1,497 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-23  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/algorithm/string.hpp>
+#include <queue>
+#include <unordered_set>
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "pack.h"
+#include "pins.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+CellInfo *XilinxPacker::insert_obuf(IdString name, IdString type, NetInfo *i, NetInfo *o, NetInfo *tri)
+{
+    auto obuf = create_cell(type, name);
+    obuf->connectPort(id_I, i);
+    obuf->connectPort(id_T, tri);
+    obuf->connectPort(id_O, o);
+    return obuf;
+}
+
+CellInfo *XilinxPacker::insert_outinv(IdString name, NetInfo *i, NetInfo *o)
+{
+    auto inv = create_cell(id_INV, name);
+    inv->connectPort(id_I, i);
+    inv->connectPort(id_O, o);
+    return inv;
+}
+
+CellInfo *XC7Packer::insert_ibuf(IdString name, IdString type, NetInfo *i, NetInfo *o)
+{
+    auto inbuf = create_cell(type, name);
+    inbuf->connectPort(id_I, i);
+    inbuf->connectPort(id_O, o);
+    return inbuf;
+}
+
+CellInfo *XC7Packer::insert_diffibuf(IdString name, IdString type, const std::array<NetInfo *, 2> &i, NetInfo *o)
+{
+    auto inbuf = create_cell(type, name);
+    inbuf->connectPort(id_I, i[0]);
+    inbuf->connectPort(id_IB, i[1]);
+    inbuf->connectPort(id_O, o);
+    return inbuf;
+}
+
+NetInfo *XilinxPacker::invert_net(NetInfo *toinv)
+{
+    if (toinv == nullptr)
+        return nullptr;
+    // If net is driven by an inverter, don't double-invert, which could cause problems with timing
+    // and IOLOGIC packing
+    if (toinv->driver.cell != nullptr && toinv->driver.cell->type == id_LUT1 &&
+        int_or_default(toinv->driver.cell->params, id_INIT, 0) == 1) {
+        NetInfo *preinv = toinv->driver.cell->getPort(id_I0);
+        // If only one user, also sweep the inversion LUT to avoid packing issues
+        if (toinv->users.entries() == 1) {
+            packed_cells.insert(toinv->driver.cell->name);
+            toinv->driver.cell->disconnectPort(id_I0);
+            toinv->driver.cell->disconnectPort(id_O);
+        }
+        return preinv;
+    } else {
+        NetInfo *inv = ctx->createNet(ctx->idf("%s$inverted%d", toinv->name.c_str(ctx), autoidx++));
+        create_lut(inv->name.str(ctx) + "$lut", {toinv}, inv, Property(1));
+        return inv;
+    }
+}
+
+std::pair<CellInfo *, PortRef> XilinxPacker::insert_pad_and_buf(CellInfo *npnr_io)
+{
+    // Given a nextpnr IO buffer, create a PAD instance and insert an IO buffer if one isn't already present
+    std::pair<CellInfo *, PortRef> result;
+    std::unique_ptr<CellInfo> pad_cell = std::make_unique<CellInfo>(ctx, npnr_io->name, id_PAD);
+    pad_cell->addInout(id_PAD);
+    // Copy IO attributes to pad
+    for (auto &attr : npnr_io->attrs)
+        pad_cell->attrs[attr.first] = attr.second;
+    NetInfo *ionet = nullptr;
+    PortRef iobuf;
+    iobuf.cell = nullptr;
+    if (npnr_io->type == ctx->id("$nextpnr_obuf") || npnr_io->type == ctx->id("$nextpnr_iobuf")) {
+        ionet = npnr_io->getPort(id_I);
+        if (ionet != nullptr && ionet->driver.cell != nullptr)
+            if (toplevel_ports.count(ionet->driver.cell->type) &&
+                toplevel_ports.at(ionet->driver.cell->type).count(ionet->driver.port)) {
+                if (ionet->users.entries() > 1)
+                    log_error("IO buffer '%s' is connected to more than a single top level IO pin.\n",
+                              ionet->driver.cell->name.c_str(ctx));
+                iobuf = ionet->driver;
+            }
+        pad_cell->attrs[id_X_IO_DIR] = std::string(npnr_io->type == ctx->id("$nextpnr_obuf") ? "OUT" : "INOUT");
+    }
+    if (npnr_io->type == ctx->id("$nextpnr_ibuf") || npnr_io->type == ctx->id("$nextpnr_iobuf")) {
+        ionet = npnr_io->getPort(id_O);
+        if (ionet != nullptr)
+            for (auto &usr : ionet->users)
+                if (toplevel_ports.count(usr.cell->type) && toplevel_ports.at(usr.cell->type).count(usr.port)) {
+                    if (ionet->users.entries() > 1)
+                        log_error("IO buffer '%s' is connected to more than a single top level IO pin.\n",
+                                  usr.cell->name.c_str(ctx));
+                    iobuf = usr;
+                }
+        pad_cell->attrs[id_X_IO_DIR] = std::string(npnr_io->type == ctx->id("$nextpnr_ibuf") ? "IN" : "INOUT");
+    }
+
+    if (!iobuf.cell) {
+        // No IO buffer, need to create one
+        log_error(
+                "   IO port '%s' is missing an IO buffer, do you need to remove -noiopad from your Yosys arguments?\n",
+                npnr_io->name.c_str(ctx));
+    } else {
+        log_info("    IO port '%s' driven by %s '%s'\n", npnr_io->name.c_str(ctx), iobuf.cell->type.c_str(ctx),
+                 iobuf.cell->name.c_str(ctx));
+    }
+
+    NPNR_ASSERT(ionet != nullptr);
+
+    for (auto &port : npnr_io->ports)
+        npnr_io->disconnectPort(port.first);
+
+    pad_cell->connectPort(id_PAD, ionet);
+    if (iobuf.cell->ports.at(iobuf.port).net != ionet) {
+        iobuf.cell->disconnectPort(iobuf.port);
+        iobuf.cell->connectPort(iobuf.port, ionet);
+    }
+
+    result.first = pad_cell.get();
+    result.second = iobuf;
+    // delete the npnr io and then add the pad, to avoid a name conflict
+    for (auto &port : npnr_io->ports) {
+        npnr_io->disconnectPort(port.first);
+    }
+    ctx->cells.erase(npnr_io->name);
+
+    ctx->cells[result.first->name] = std::move(pad_cell);
+
+    return result;
+}
+
+void XC7Packer::decompose_iob(CellInfo *xil_iob, bool is_hr, const std::string &iostandard)
+{
+    bool is_se_ibuf = xil_iob->type.in(id_IBUF, id_IBUF_IBUFDISABLE, id_IBUF_INTERMDISABLE);
+    bool is_se_iobuf = xil_iob->type.in(id_IOBUF, id_IOBUF_DCIEN, id_IOBUF_INTERMDISABLE);
+    bool is_se_obuf = xil_iob->type.in(id_OBUF, id_OBUFT);
+
+    auto pad_site = [&](NetInfo *n) {
+        for (auto user : n->users)
+            if (user.cell->type == id_PAD)
+                return uarch->get_bel_site(ctx->getBelByNameStr(user.cell->attrs[id_BEL].as_string()));
+        NPNR_ASSERT_FALSE(("can't find PAD for net " + n->name.str(ctx)).c_str());
+    };
+
+    if (is_se_ibuf || is_se_iobuf) {
+        log_info("Generating input buffer for '%s'\n", xil_iob->name.c_str(ctx));
+        NetInfo *pad_net = xil_iob->getPort(is_se_iobuf ? id_IO : id_I);
+        NPNR_ASSERT(pad_net != nullptr);
+        auto site = pad_site(pad_net);
+        if (!is_se_iobuf)
+            xil_iob->disconnectPort(id_I);
+
+        NetInfo *top_out = xil_iob->getPort(id_O);
+        xil_iob->disconnectPort(id_O);
+
+        IdString ibuf_type = id_IBUF;
+        if (xil_iob->type.in(id_IBUF_IBUFDISABLE, id_IOBUF_DCIEN))
+            ibuf_type = id_IBUF_IBUFDISABLE;
+        if (xil_iob->type.in(id_IBUF_INTERMDISABLE, id_IOBUF_INTERMDISABLE))
+            ibuf_type = id_IBUF_INTERMDISABLE;
+
+        CellInfo *inbuf = insert_ibuf(int_name(xil_iob->name, "IBUF", is_se_iobuf), ibuf_type, pad_net, top_out);
+        std::string tile = ctx->get_tile_type(site.tile).str(ctx);
+        if (boost::starts_with(tile, "RIOB18"))
+            ctx->bindBel(uarch->get_site_bel(site, ctx->id("IOB18.INBUF_DCIEN")), inbuf, STRENGTH_LOCKED);
+        else
+            ctx->bindBel(uarch->get_site_bel(site, ctx->id("IOB33.INBUF_EN")), inbuf, STRENGTH_LOCKED);
+        xil_iob->movePortTo(id_IBUFDISABLE, inbuf, id_IBUFDISABLE);
+        xil_iob->movePortTo(id_INTERMDISABLE, inbuf, id_INTERMDISABLE);
+    }
+
+    if (is_se_obuf || is_se_iobuf) {
+        log_info("Generating output buffer for '%s'\n", xil_iob->name.c_str(ctx));
+        NetInfo *pad_net = xil_iob->getPort(is_se_iobuf ? id_IO : id_O);
+        NPNR_ASSERT(pad_net != nullptr);
+        auto site = pad_site(pad_net);
+        xil_iob->disconnectPort(is_se_iobuf ? id_IO : id_O);
+        bool has_dci = xil_iob->type == id_IOBUF_DCIEN;
+        CellInfo *obuf = insert_obuf(
+                int_name(xil_iob->name, (is_se_iobuf || xil_iob->type == id_OBUFT) ? "OBUFT" : "OBUF", !is_se_obuf),
+                is_se_iobuf ? (has_dci ? id_OBUFT_DCIEN : id_OBUFT) : xil_iob->type, xil_iob->getPort(id_I), pad_net,
+                xil_iob->getPort(id_T));
+        std::string tile = ctx->get_tile_type(site.tile).str(ctx);
+        if (boost::starts_with(tile, "RIOB18"))
+            ctx->bindBel(uarch->get_site_bel(site, ctx->id("IOB18.OUTBUF_DCIEN")), obuf, STRENGTH_LOCKED);
+        else
+            ctx->bindBel(uarch->get_site_bel(site, ctx->id("IOB33.OUTBUF")), obuf, STRENGTH_LOCKED);
+        xil_iob->movePortTo(id_DCITERMDISABLE, obuf, id_DCITERMDISABLE);
+    }
+
+    bool is_diff_ibuf = xil_iob->type.in(id_IBUFDS, id_IBUFDS_INTERMDISABLE, id_IBUFDS);
+    bool is_diff_iobuf = xil_iob->type.in(id_IOBUFDS, id_IOBUFDS_DCIEN);
+    bool is_diff_out_iobuf =
+            xil_iob->type.in(id_IOBUFDS_DIFF_OUT, id_IOBUFDS_DIFF_OUT_DCIEN, id_IOBUFDS_DIFF_OUT_INTERMDISABLE);
+    bool is_diff_obuf = xil_iob->type.in(id_OBUFDS, id_OBUFTDS);
+
+    if (is_diff_ibuf || is_diff_iobuf) {
+        NetInfo *pad_p_net = xil_iob->getPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IO : id_I);
+        NPNR_ASSERT(pad_p_net != nullptr);
+        auto site_p = pad_site(pad_p_net);
+        NetInfo *pad_n_net = xil_iob->getPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IOB : id_IB);
+        NPNR_ASSERT(pad_n_net != nullptr);
+        std::string tile_p = ctx->get_tile_type(site_p.tile).str(ctx);
+        bool is_riob18 = boost::starts_with(tile_p, "RIOB18");
+
+        if (!is_diff_iobuf && !is_diff_out_iobuf) {
+            xil_iob->disconnectPort(id_I);
+            xil_iob->disconnectPort(id_IB);
+        }
+
+        NetInfo *top_out = xil_iob->getPort(id_O);
+        xil_iob->disconnectPort(id_O);
+
+        IdString ibuf_type = id_IBUFDS;
+        CellInfo *inbuf = insert_diffibuf(int_name(xil_iob->name, "IBUF", is_se_iobuf), ibuf_type,
+                                          {pad_p_net, pad_n_net}, top_out);
+        if (is_riob18) {
+            ctx->bindBel(uarch->get_site_bel(site_p, ctx->id("IOB18M.INBUF_DCIEN")), inbuf, STRENGTH_LOCKED);
+            inbuf->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB18M");
+        } else {
+            ctx->bindBel(uarch->get_site_bel(site_p, ctx->id("IOB33M.INBUF_EN")), inbuf, STRENGTH_LOCKED);
+            inbuf->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB33M");
+        }
+    }
+
+    if (is_diff_obuf || is_diff_out_iobuf || is_diff_iobuf) {
+        // FIXME: true diff outputs
+        NetInfo *pad_p_net = xil_iob->getPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IO : id_O);
+        NPNR_ASSERT(pad_p_net != nullptr);
+        auto site_p = pad_site(pad_p_net);
+        NetInfo *pad_n_net = xil_iob->getPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IOB : id_OB);
+        NPNR_ASSERT(pad_n_net != nullptr);
+        auto site_n = pad_site(pad_n_net);
+        std::string tile_p = ctx->get_tile_type(site_p.tile).str(ctx);
+        bool is_riob18 = boost::starts_with(tile_p, "RIOB18");
+
+        xil_iob->disconnectPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IO : id_O);
+        xil_iob->disconnectPort((is_diff_iobuf || is_diff_out_iobuf) ? id_IOB : id_OB);
+
+        NetInfo *inv_i = create_internal_net(xil_iob->name, is_diff_obuf ? "I_B" : "OBUFTDS$subnet$I_B");
+        CellInfo *inv = insert_outinv(int_name(xil_iob->name, is_diff_obuf ? "INV" : "OBUFTDS$subcell$INV"),
+                                      xil_iob->getPort(id_I), inv_i);
+        if (is_riob18) {
+            ctx->bindBel(uarch->get_site_bel(site_n, ctx->id("IOB18S.O_ININV")), inv, STRENGTH_LOCKED);
+            inv->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB18S");
+        } else {
+            ctx->bindBel(uarch->get_site_bel(site_n, ctx->id("IOB33S.O_ININV")), inv, STRENGTH_LOCKED);
+            inv->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB33S");
+        }
+
+        bool has_dci = xil_iob->type.in(id_IOBUFDS_DCIEN, id_IOBUFDSE3);
+
+        CellInfo *obuf_p = insert_obuf(int_name(xil_iob->name, is_diff_obuf ? "P" : "OBUFTDS$subcell$P"),
+                                       (is_diff_iobuf || is_diff_out_iobuf || (xil_iob->type == id_OBUFTDS))
+                                               ? (has_dci ? id_OBUFT_DCIEN : id_OBUFT)
+                                               : id_OBUF,
+                                       xil_iob->getPort(id_I), pad_p_net, xil_iob->getPort(id_T));
+
+        if (is_riob18) {
+            ctx->bindBel(uarch->get_site_bel(site_p, ctx->id("IOB18M.OUTBUF_DCIEN")), obuf_p, STRENGTH_LOCKED);
+            obuf_p->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB18M");
+        } else {
+            ctx->bindBel(uarch->get_site_bel(site_p, ctx->id("IOB33M.OUTBUF")), obuf_p, STRENGTH_LOCKED);
+            obuf_p->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB33M");
+        }
+        obuf_p->connectPort(id_DCITERMDISABLE, xil_iob->getPort(id_DCITERMDISABLE));
+
+        CellInfo *obuf_n = insert_obuf(int_name(xil_iob->name, is_diff_obuf ? "N" : "OBUFTDS$subcell$N"),
+                                       (is_diff_iobuf || is_diff_out_iobuf || (xil_iob->type == id_OBUFTDS))
+                                               ? (has_dci ? id_OBUFT_DCIEN : id_OBUFT)
+                                               : id_OBUF,
+                                       inv_i, pad_n_net, xil_iob->getPort(id_T));
+
+        if (is_riob18) {
+            ctx->bindBel(uarch->get_site_bel(site_n, ctx->id("IOB18S.OUTBUF_DCIEN")), obuf_n, STRENGTH_LOCKED);
+            obuf_n->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB18S");
+        } else {
+            ctx->bindBel(uarch->get_site_bel(site_n, ctx->id("IOB33S.OUTBUF")), obuf_n, STRENGTH_LOCKED);
+            obuf_n->attrs[id_X_IOB_SITE_TYPE] = std::string("IOB33S");
+        }
+        obuf_n->connectPort(id_DCITERMDISABLE, xil_iob->getPort(id_DCITERMDISABLE));
+
+        xil_iob->disconnectPort(id_DCITERMDISABLE);
+    }
+}
+
+void XC7Packer::pack_io()
+{
+    log_info("Inserting IO buffers..\n");
+
+    get_top_level_pins(ctx, toplevel_ports);
+    // Insert PAD cells on top level IO, and IO buffers where one doesn't exist already
+    std::vector<CellInfo *> npnr_io;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf") ||
+            ci->type == ctx->id("$nextpnr_obuf"))
+            npnr_io.push_back(ci);
+    }
+    std::vector<std::pair<CellInfo *, PortRef>> pad_and_buf;
+    for (auto ci : npnr_io) {
+        pad_and_buf.push_back(insert_pad_and_buf(ci));
+    }
+    flush_cells();
+    pool<BelId> used_io_bels;
+    int unconstr_io_count = 0;
+    for (auto &iob : pad_and_buf) {
+        CellInfo *pad = iob.first;
+        // Process location constraints
+        if (pad->attrs.count(id_PACKAGE_PIN)) {
+            pad->attrs[id_LOC] = pad->attrs.at(id_PACKAGE_PIN);
+        }
+        if (pad->attrs.count(id_LOC)) {
+            std::string loc = pad->attrs.at(id_LOC).to_string();
+            BelId bel = ctx->get_package_pin_bel(ctx->id(loc));
+            if (bel == BelId())
+                log_error("Unable to constrain IO '%s', device does not have a pin named '%s'\n", pad->name.c_str(ctx),
+                          loc.c_str());
+            log_info("    Constraining '%s' to pad '%s'\n", pad->name.c_str(ctx), ctx->nameOfBel(bel));
+            pad->attrs[id_BEL] = std::string(ctx->nameOfBel(bel));
+        }
+        if (pad->attrs.count(id_BEL)) {
+            used_io_bels.insert(ctx->getBelByNameStr(pad->attrs.at(id_BEL).as_string()));
+        } else {
+            ++unconstr_io_count;
+        }
+    }
+    // Constrain unconstrained IO
+    for (auto &iob : pad_and_buf) {
+        CellInfo *pad = iob.first;
+        if (!pad->attrs.count(id_BEL)) {
+            log_error("FIXME: unconstrained IO not supported (pad %s)\n", ctx->nameOf(pad));
+            ;
+        }
+    }
+    // Decompose macro IO primitives to smaller primitives that map logically to the actual IO Bels
+    for (auto &iob : pad_and_buf) {
+        if (packed_cells.count(iob.second.cell->name))
+            continue;
+        decompose_iob(iob.second.cell, true, str_or_default(iob.first->attrs, id_IOSTANDARD, ""));
+        packed_cells.insert(iob.second.cell->name);
+    }
+    flush_cells();
+
+    dict<IdString, XFormRule> hriobuf_rules, hpiobuf_rules;
+    hriobuf_rules[id_OBUF].new_type = id_IOB33_OUTBUF;
+    hriobuf_rules[id_OBUF].port_xform[id_I] = id_IN;
+    hriobuf_rules[id_OBUF].port_xform[id_O] = id_OUT;
+    hriobuf_rules[id_OBUF].port_xform[id_T] = id_TRI;
+    hriobuf_rules[id_OBUFT] = XFormRule(hriobuf_rules[id_OBUF]);
+
+    hriobuf_rules[id_IBUF].new_type = id_IOB33_INBUF_EN;
+    hriobuf_rules[id_IBUF].port_xform[id_I] = id_PAD;
+    hriobuf_rules[id_IBUF].port_xform[id_O] = id_OUT;
+    hriobuf_rules[id_IBUF_INTERMDISABLE] = XFormRule(hriobuf_rules[id_IBUF]);
+    hriobuf_rules[id_IBUF_IBUFDISABLE] = XFormRule(hriobuf_rules[id_IBUF]);
+    hriobuf_rules[id_IBUFDS_INTERMDISABLE_INT] = XFormRule(hriobuf_rules[id_IBUF]);
+    hriobuf_rules[id_IBUFDS_INTERMDISABLE_INT].port_xform[id_IB] = id_DIFFI_IN;
+    hriobuf_rules[id_IBUFDS] = XFormRule(hriobuf_rules[id_IBUF]);
+    hriobuf_rules[id_IBUFDS].port_xform[id_IB] = id_DIFFI_IN;
+
+    hpiobuf_rules[id_OBUF].new_type = id_IOB18_OUTBUF_DCIEN;
+    hpiobuf_rules[id_OBUF].port_xform[id_I] = id_IN;
+    hpiobuf_rules[id_OBUF].port_xform[id_O] = id_OUT;
+    hpiobuf_rules[id_OBUF].port_xform[id_T] = id_TRI;
+    hpiobuf_rules[id_OBUFT] = XFormRule(hpiobuf_rules[id_OBUF]);
+
+    hpiobuf_rules[id_IBUF].new_type = id_IOB18_INBUF_DCIEN;
+    hpiobuf_rules[id_IBUF].port_xform[id_I] = id_PAD;
+    hpiobuf_rules[id_IBUF].port_xform[id_O] = id_OUT;
+    hpiobuf_rules[id_IBUF_INTERMDISABLE] = XFormRule(hpiobuf_rules[id_IBUF]);
+    hpiobuf_rules[id_IBUF_IBUFDISABLE] = XFormRule(hpiobuf_rules[id_IBUF]);
+    hriobuf_rules[id_IBUFDS_INTERMDISABLE_INT] = XFormRule(hriobuf_rules[id_IBUF]);
+    hpiobuf_rules[id_IBUFDS_INTERMDISABLE_INT].port_xform[id_IB] = id_DIFFI_IN;
+    hpiobuf_rules[id_IBUFDS] = XFormRule(hpiobuf_rules[id_IBUF]);
+    hpiobuf_rules[id_IBUFDS].port_xform[id_IB] = id_DIFFI_IN;
+
+    // Special xform for OBUFx and IBUFx.
+    dict<IdString, XFormRule> rules;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (!ci->attrs.count(id_BEL) && ci->bel == BelId())
+            continue;
+        std::string belname =
+                ci->attrs.count(id_BEL) ? ci->attrs[id_BEL].as_string() : std::string(ctx->nameOfBel(ci->bel));
+        size_t pos = belname.find(".");
+        if (belname.substr(pos + 1, 5) == "IOB18")
+            rules = hpiobuf_rules;
+        else if (belname.substr(pos + 1, 5) == "IOB33")
+            rules = hriobuf_rules;
+        else
+            log_error("Unexpected IOBUF BEL %s\n", belname.c_str());
+        if (rules.count(ci->type)) {
+            xform_cell(rules, ci);
+        }
+    }
+
+    dict<IdString, XFormRule> hrio_rules;
+    hrio_rules[id_PAD].new_type = id_PAD;
+
+    hrio_rules[id_INV].new_type = id_INVERTER;
+    hrio_rules[id_INV].port_xform[id_I] = id_IN;
+    hrio_rules[id_INV].port_xform[id_O] = id_OUT;
+
+    hrio_rules[id_PS7].new_type = id_PS7_PS7;
+
+    generic_xform(hrio_rules, true);
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        std::string type = ci->type.str(ctx);
+        if (!boost::starts_with(type, "IOB33") && !boost::starts_with(type, "IOB18"))
+            continue;
+        if (!ci->attrs.count(id_X_IOB_SITE_TYPE))
+            continue;
+        type.replace(0, 5, ci->attrs.at(id_X_IOB_SITE_TYPE).as_string());
+        ci->type = ctx->id(type);
+    }
+
+    // check all PAD cells for IOSTANDARD/DRIVE
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        std::string type = ci->type.str(ctx);
+        if (type != "PAD")
+            continue;
+        check_valid_pad(ci, type);
+    }
+}
+
+void XC7Packer::check_valid_pad(CellInfo *ci, std::string type)
+{
+    auto iostandard_id = id_IOSTANDARD;
+    auto iostandard_attr = ci->attrs.find(iostandard_id);
+    if (iostandard_attr == ci->attrs.end())
+        log_error("port %s has no IOSTANDARD property", ci->name.c_str(ctx));
+
+    auto iostandard = iostandard_attr->second.as_string();
+    if (!boost::starts_with(iostandard, "LVTTL") && !boost::starts_with(iostandard, "LVCMOS"))
+        return;
+
+    auto drive_attr = ci->attrs.find(id_DRIVE);
+    // no drive strength attribute: use default
+    if (drive_attr == ci->attrs.end())
+        return;
+    auto drive = drive_attr->second.as_int64();
+
+    bool is_iob33 = boost::starts_with(type, "IOB33");
+    if (is_iob33) {
+        if (drive == 4 || drive == 8 || drive == 12)
+            return;
+        if (iostandard != "LVCMOS12" && drive == 16)
+            return;
+        if ((iostandard == "LVCMOS18" || iostandard == "LVTTL") && drive == 24)
+            return;
+    } else { // IOB18
+        if (drive == 2 || drive == 4 || drive == 6 || drive == 8)
+            return;
+        if (iostandard != "LVCMOS12" && (drive == 12 || drive == 16))
+            return;
+    }
+
+    log_error("unsupported DRIVE strength property %s for port %s", drive_attr->second.c_str(), ci->name.c_str(ctx));
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/pins.cc b/himbaechel/uarch/xilinx/pins.cc
new file mode 100644
index 0000000000..14c70b03c7
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pins.cc
@@ -0,0 +1,480 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <set>
+
+#include "nextpnr.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void get_invertible_pins(Context *ctx, dict<IdString, pool<IdString>> &invertible_pins)
+{
+    // List of pins that have an IS_x_INVERTED attributed, so we can optimise tie-zero to tie-one for these pins
+    // See scripts/invertible_pins.py
+
+    // Common and xcup
+    invertible_pins[id_BUFGCTRL].insert(id_CE0);
+    invertible_pins[id_BUFGCTRL].insert(id_CE1);
+    invertible_pins[id_BUFGCTRL].insert(id_S0);
+    invertible_pins[id_BUFGCTRL].insert(id_S1);
+    invertible_pins[id_BUFGCTRL].insert(id_IGNORE0);
+    invertible_pins[id_BUFGCTRL].insert(id_IGNORE1);
+    invertible_pins[id_BUFHCE].insert(id_CE);
+    invertible_pins[id_FDRE].insert(id_C);
+    invertible_pins[id_FDSE].insert(id_C);
+    invertible_pins[id_FDCE].insert(id_C);
+    invertible_pins[id_FDPE].insert(id_C);
+
+    invertible_pins[id_SRL16E].insert(id_CLK);
+    invertible_pins[id_SRLC32E].insert(id_CLK);
+    invertible_pins[id_BUFGCE].insert(id_CE);
+    invertible_pins[id_BUFGCE].insert(id_I);
+    invertible_pins[id_BUFGCE_DIV].insert(id_CE);
+    invertible_pins[id_BUFGCE_DIV].insert(id_CLR);
+    invertible_pins[id_BUFGCE_DIV].insert(id_I);
+    invertible_pins[id_CFGLUT5].insert(id_CLK);
+    invertible_pins[id_FIFO18E2].insert(id_RDCLK);
+    invertible_pins[id_FIFO18E2].insert(id_RDEN);
+    invertible_pins[id_FIFO18E2].insert(id_RSTREG);
+    invertible_pins[id_FIFO18E2].insert(id_RST);
+    invertible_pins[id_FIFO18E2].insert(id_WRCLK);
+    invertible_pins[id_FIFO18E2].insert(id_WREN);
+    invertible_pins[id_FIFO36E2].insert(id_RDCLK);
+    invertible_pins[id_FIFO36E2].insert(id_RDEN);
+    invertible_pins[id_FIFO36E2].insert(id_RSTREG);
+    invertible_pins[id_FIFO36E2].insert(id_RST);
+    invertible_pins[id_FIFO36E2].insert(id_WRCLK);
+    invertible_pins[id_FIFO36E2].insert(id_WREN);
+    invertible_pins[id_HARD_SYNC].insert(id_CLK);
+    invertible_pins[id_IDDRE1].insert(id_CB);
+    invertible_pins[id_IDDRE1].insert(id_C);
+
+    invertible_pins[id_LDCE].insert(id_CLR);
+    invertible_pins[id_LDCE].insert(id_G);
+    invertible_pins[id_LDPE].insert(id_G);
+    invertible_pins[id_LDPE].insert(id_PRE);
+    invertible_pins[id_ODDRE1].insert(id_C);
+    // invertible_pins[id_ODDRE1].insert(id_D1);
+    // invertible_pins[id_ODDRE1].insert(id_D2);
+
+    invertible_pins[id_OR2L].insert(id_SRI);
+
+    // invertible_pins[id_OSERDESE3].insert(id_RST);
+    invertible_pins[id_RAM128X1D].insert(id_WCLK);
+    invertible_pins[id_RAM128X1S].insert(id_WCLK);
+    invertible_pins[id_RAM256X1D].insert(id_WCLK);
+    invertible_pins[id_RAM256X1S].insert(id_WCLK);
+    invertible_pins[id_RAM32M].insert(id_WCLK);
+    invertible_pins[id_RAM32M16].insert(id_WCLK);
+    invertible_pins[id_RAM32X1D].insert(id_WCLK);
+    invertible_pins[id_RAM32X1S].insert(id_WCLK);
+    invertible_pins[id_RAM32X2S].insert(id_WCLK);
+    invertible_pins[id_RAM512X1S].insert(id_WCLK);
+    invertible_pins[id_RAM64M].insert(id_WCLK);
+    invertible_pins[id_RAM64M8].insert(id_WCLK);
+    invertible_pins[id_RAM64X1D].insert(id_WCLK);
+    invertible_pins[id_RAM64X1S].insert(id_WCLK);
+    invertible_pins[id_RAM64X8SW].insert(id_WCLK);
+
+    invertible_pins[id_SYSMONE1].insert(id_CONVSTCLK);
+    invertible_pins[id_SYSMONE1].insert(id_DCLK);
+
+    // xc7
+    invertible_pins[id_RAMB18E1].insert(id_CLKARDCLK);
+    invertible_pins[id_RAMB18E1].insert(id_CLKBWRCLK);
+    invertible_pins[id_RAMB18E1].insert(id_ENARDEN);
+    invertible_pins[id_RAMB18E1].insert(id_ENBWREN);
+    invertible_pins[id_RAMB18E1].insert(id_RSTRAMARSTRAM);
+    invertible_pins[id_RAMB18E1].insert(id_RSTRAMB);
+    invertible_pins[id_RAMB18E1].insert(id_RSTREGARSTREG);
+    invertible_pins[id_RAMB18E1].insert(id_RSTREGB);
+    invertible_pins[id_RAMB36E1].insert(id_CLKARDCLK);
+    invertible_pins[id_RAMB36E1].insert(id_CLKBWRCLK);
+    invertible_pins[id_RAMB36E1].insert(id_ENARDEN);
+    invertible_pins[id_RAMB36E1].insert(id_ENBWREN);
+    invertible_pins[id_RAMB36E1].insert(id_RSTRAMARSTRAM);
+    invertible_pins[id_RAMB36E1].insert(id_RSTRAMB);
+    invertible_pins[id_RAMB36E1].insert(id_RSTREGARSTREG);
+    invertible_pins[id_RAMB36E1].insert(id_RSTREGB);
+    invertible_pins[id_BUFMRCE].insert(id_CE);
+    for (int i = 0; i < 4; i++)
+        invertible_pins[id_DSP48E1].insert(ctx->idf("ALUMODE[%d]", i));
+    invertible_pins[id_DSP48E1].insert(id_CARRYIN);
+    for (int i = 0; i < 5; i++)
+        invertible_pins[id_DSP48E1].insert(ctx->idf("INMODE[%d]", i));
+    for (int i = 0; i < 7; i++)
+        invertible_pins[id_DSP48E1].insert(ctx->idf("OPMODE[%d]", i));
+    invertible_pins[id_FIFO18E1].insert(id_RDCLK);
+    invertible_pins[id_FIFO18E1].insert(id_RDEN);
+    invertible_pins[id_FIFO18E1].insert(id_RSTREG);
+    invertible_pins[id_FIFO18E1].insert(id_RST);
+    invertible_pins[id_FIFO18E1].insert(id_WRCLK);
+    invertible_pins[id_FIFO18E1].insert(id_WREN);
+    invertible_pins[id_FIFO36E1].insert(id_RDCLK);
+    invertible_pins[id_FIFO36E1].insert(id_RDEN);
+    invertible_pins[id_FIFO36E1].insert(id_RSTREG);
+    invertible_pins[id_FIFO36E1].insert(id_RST);
+    invertible_pins[id_FIFO36E1].insert(id_WRCLK);
+    invertible_pins[id_FIFO36E1].insert(id_WREN);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_CLKRSVD0);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_CLKRSVD1);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_CPLLLOCKDETCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_DMONITORCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_DRPCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_GTGREFCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_RXUSRCLK2);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_RXUSRCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_SIGVALIDCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_TXPHDLYTSTCLK);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_TXUSRCLK2);
+    invertible_pins[id_GTHE2_CHANNEL].insert(id_TXUSRCLK);
+    invertible_pins[id_GTHE2_COMMON].insert(id_DRPCLK);
+    invertible_pins[id_GTHE2_COMMON].insert(id_GTGREFCLK);
+    invertible_pins[id_GTHE2_COMMON].insert(id_QPLLLOCKDETCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_CLKRSVD0);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_CLKRSVD1);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_DMONITORCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_DRPCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_RXUSRCLK2);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_RXUSRCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_SIGVALIDCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_TXPHDLYTSTCLK);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_TXUSRCLK2);
+    invertible_pins[id_GTPE2_CHANNEL].insert(id_TXUSRCLK);
+    invertible_pins[id_GTPE2_COMMON].insert(id_DRPCLK);
+    invertible_pins[id_GTPE2_COMMON].insert(id_GTGREFCLK0);
+    invertible_pins[id_GTPE2_COMMON].insert(id_GTGREFCLK1);
+    invertible_pins[id_GTPE2_COMMON].insert(id_PLL0LOCKDETCLK);
+    invertible_pins[id_GTPE2_COMMON].insert(id_PLL1LOCKDETCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_CPLLLOCKDETCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_DRPCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_GTGREFCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_RXUSRCLK2);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_RXUSRCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_TXPHDLYTSTCLK);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_TXUSRCLK2);
+    invertible_pins[id_GTXE2_CHANNEL].insert(id_TXUSRCLK);
+    invertible_pins[id_GTXE2_COMMON].insert(id_DRPCLK);
+    invertible_pins[id_GTXE2_COMMON].insert(id_GTGREFCLK);
+    invertible_pins[id_GTXE2_COMMON].insert(id_QPLLLOCKDETCLK);
+    invertible_pins[id_IDDR].insert(id_C);
+    // invertible_pins[id_IDDR].insert(id_D);
+    invertible_pins[id_IDDR_2CLK].insert(id_CB);
+    invertible_pins[id_IDDR_2CLK].insert(id_C);
+    // invertible_pins[id_IDDR_2CLK].insert(id_D);
+    invertible_pins[id_IDELAYE2].insert(id_C);
+    invertible_pins[id_IDELAYE2].insert(id_IDATAIN);
+    invertible_pins[id_ODELAYE2].insert(id_C);
+    invertible_pins[id_ODELAYE2].insert(id_ODATAIN);
+    invertible_pins[id_ISERDESE2].insert(id_CLKB);
+    invertible_pins[id_ISERDESE2].insert(id_CLKDIVP);
+    invertible_pins[id_ISERDESE2].insert(id_CLKDIV);
+    invertible_pins[id_ISERDESE2].insert(id_CLK);
+    // invertible_pins[id_ISERDESE2].insert(id_D);
+    invertible_pins[id_ISERDESE2].insert(id_OCLKB);
+    invertible_pins[id_ISERDESE2].insert(id_OCLK);
+    // invertible_pins[id_LDCE].insert(id_CLR);
+    invertible_pins[id_LDCE].insert(id_G);
+    invertible_pins[id_LDPE].insert(id_G);
+    // invertible_pins[id_LDPE].insert(id_PRE);
+    invertible_pins[id_MMCME2_ADV].insert(id_CLKINSEL);
+    invertible_pins[id_MMCME2_ADV].insert(id_PSEN);
+    invertible_pins[id_MMCME2_ADV].insert(id_PSINCDEC);
+    invertible_pins[id_MMCME2_ADV].insert(id_PWRDWN);
+    invertible_pins[id_MMCME2_ADV].insert(id_RST);
+    invertible_pins[id_IDDR].insert(id_CK);
+    invertible_pins[id_ODDR].insert(id_CK);
+    invertible_pins[id_ODDR].insert(id_D1);
+    invertible_pins[id_ODDR].insert(id_D2);
+    invertible_pins[id_ODELAYE2].insert(id_C);
+    // invertible_pins[id_ODELAYE2].insert(id_ODATAIN);
+    invertible_pins[id_OSERDESE2].insert(id_CLKDIV);
+    invertible_pins[id_OSERDESE2].insert(id_CLK);
+    // invertible_pins[id_OSERDESE2].insert(id_D1);
+    // invertible_pins[id_OSERDESE2].insert(id_D2);
+    // invertible_pins[id_OSERDESE2].insert(id_D3);
+    // invertible_pins[id_OSERDESE2].insert(id_D4);
+    // invertible_pins[id_OSERDESE2].insert(id_D5);
+    // invertible_pins[id_OSERDESE2].insert(id_D6);
+    // invertible_pins[id_OSERDESE2].insert(id_D7);
+    // invertible_pins[id_OSERDESE2].insert(id_D8);
+    invertible_pins[id_OSERDESE2].insert(id_T1);
+    invertible_pins[id_OSERDESE2].insert(id_T2);
+    invertible_pins[id_OSERDESE2].insert(id_T3);
+    invertible_pins[id_OSERDESE2].insert(id_T4);
+    invertible_pins[id_PHASER_IN].insert(id_RST);
+    invertible_pins[id_PHASER_IN_PHY].insert(id_RST);
+    invertible_pins[id_PHASER_OUT].insert(id_RST);
+    invertible_pins[id_PHASER_OUT_PHY].insert(id_RST);
+    invertible_pins[id_PHASER_REF].insert(id_RST);
+    invertible_pins[id_PHASER_REF].insert(id_PWRDWN);
+    invertible_pins[id_PLLE2_ADV].insert(id_CLKINSEL);
+    invertible_pins[id_PLLE2_ADV].insert(id_PWRDWN);
+    invertible_pins[id_PLLE2_ADV].insert(id_RST);
+    invertible_pins[id_XADC].insert(id_CONVSTCLK);
+    invertible_pins[id_XADC].insert(id_DCLK);
+}
+
+void get_tied_pins(Context *ctx, dict<IdString, dict<IdString, bool>> &tied_pins)
+{
+    // List of pins that are tied to a fixed value when unused.
+    // This doesn't include the PS8, due to the large number of tied-zero pins that are implied by the
+    // list of Bel pins and dealt with as a special case in arch_place.cc
+
+    for (IdString ram : {id_RAMB18E2, id_RAMB36E2}) {
+        // based on UG573 p37
+        for (char port : {'A', 'B'}) {
+            tied_pins[ram][ctx->id(std::string("ADDREN") + port)] = true;
+            tied_pins[ram][ctx->id(std::string("CASDIMUX") + port)] = false;
+            tied_pins[ram][ctx->id(std::string("CASDOMUX") + port)] = false;
+            if (ram == id_RAMB18E2) {
+                tied_pins[ram][ctx->id(std::string("CASDOMUXEN_") + port)] = true;
+                tied_pins[ram][ctx->id(std::string("CASOREGIMUXEN_") + port)] = true;
+            }
+
+            tied_pins[ram][ctx->id(std::string("CASOREGIMUX") + port)] = false;
+        }
+
+        int wea_width = (ram == id_RAMB18E2 ? 2 : 4);
+        int web_width = 4;
+
+        for (int i = 0; i < wea_width; i++)
+            tied_pins[ram][ctx->id(std::string("WEA[") + std::to_string(i) + "]")] = true;
+        for (int i = 0; i < web_width; i++)
+            tied_pins[ram][ctx->id(std::string("WEBWE[") + std::to_string(i) + "]")] = true;
+
+        tied_pins[ram][id_CLKARDCLK] = false;
+        tied_pins[ram][id_CLKBWRCLK] = false;
+        tied_pins[ram][id_ENARDEN] = false;
+        tied_pins[ram][id_ENBWREN] = false;
+        tied_pins[ram][id_REGCEAREGCE] = true;
+        tied_pins[ram][id_REGCEB] = true;
+
+        tied_pins[ram][id_RSTRAMARSTRAM] = false;
+        tied_pins[ram][id_RSTRAMB] = false;
+        tied_pins[ram][id_RSTREGARSTREG] = false;
+        tied_pins[ram][id_RSTREGB] = false;
+        tied_pins[ram][id_SLEEP] = false;
+
+        if (ram == id_RAMB36E2) {
+            tied_pins[ram][id_INJECTSBITERR] = false;
+            tied_pins[ram][id_INJECTDBITERR] = false;
+            tied_pins[ram][id_ECCPIPECE] = true;
+        }
+    }
+
+    for (IdString ram : {id_RAMB18E1, id_RAMB36E1}) {
+        // based on UG573 p37
+
+        int wea_width = (ram == id_RAMB18E1 ? 2 : 4);
+        int web_width = 4;
+
+        for (int i = 0; i < wea_width; i++)
+            tied_pins[ram][ctx->id(std::string("WEA[") + std::to_string(i) + "]")] = true;
+        for (int i = 0; i < web_width; i++)
+            tied_pins[ram][ctx->id(std::string("WEBWE[") + std::to_string(i) + "]")] = true;
+
+        tied_pins[ram][id_CLKARDCLK] = false;
+        tied_pins[ram][id_CLKBWRCLK] = false;
+        tied_pins[ram][id_ENARDEN] = false;
+        tied_pins[ram][id_ENBWREN] = false;
+        tied_pins[ram][id_REGCEAREGCE] = true;
+        tied_pins[ram][id_REGCEB] = true;
+
+        tied_pins[ram][id_RSTRAMARSTRAM] = false;
+        tied_pins[ram][id_RSTRAMB] = false;
+        tied_pins[ram][id_RSTREGARSTREG] = false;
+        tied_pins[ram][id_RSTREGB] = false;
+    }
+
+    // BUFGCTRL (by experiment)
+    for (int i = 0; i < 2; i++) {
+        tied_pins[id_BUFGCTRL][ctx->id("S" + std::to_string(i))] = false;
+        tied_pins[id_BUFGCTRL][ctx->id("IGNORE" + std::to_string(i))] = false;
+        tied_pins[id_BUFGCTRL][ctx->id("CE" + std::to_string(i))] = false;
+    }
+
+    // IO logic primitives
+    tied_pins[id_IDDRE1][id_R] = false;
+    tied_pins[id_ODDRE1][id_SR] = false;
+
+    tied_pins[id_OSERDESE2][id_RST] = false;
+    for (int i = 1; i <= 8; i++)
+        tied_pins[id_OSERDESE2][ctx->id("D" + std::to_string(i))] = false;
+    for (int i = 1; i <= 4; i++)
+        tied_pins[id_OSERDESE2][ctx->id("T" + std::to_string(i))] = false;
+    tied_pins[id_OSERDESE2][id_OCE] = true;
+    tied_pins[id_OSERDESE2][id_TCE] = true;
+
+    tied_pins[id_IDELAYE2][id_REGRST] = false;
+    tied_pins[id_IDELAYE2][id_LDPIPEEN] = false;
+    tied_pins[id_IDELAYE2][id_CINVCTRL] = false;
+
+    // IO primitives
+    tied_pins[id_IOBUFDSE3][id_DCITERMDISABLE] = false;
+    tied_pins[id_IOBUFDSE3][ctx->id("OSC_EN[0]")] = false;
+    tied_pins[id_IOBUFDSE3][ctx->id("OSC_EN[1]")] = false;
+    for (int i = 0; i < 4; i++)
+        tied_pins[id_IOBUFDSE3][ctx->id("OSC[" + std::to_string(i) + "]")] = false;
+
+    // PLL
+    tied_pins[id_PLLE2_ADV][id_CLKFBIN] = false;
+    tied_pins[id_PLLE2_ADV][id_CLKIN1] = false;
+    tied_pins[id_PLLE2_ADV][id_CLKIN2] = false;
+    tied_pins[id_PLLE2_ADV][id_CLKINSEL] = true;
+    for (int i = 0; i < 7; i++)
+        tied_pins[id_PLLE2_ADV][ctx->id("DADDR[" + std::to_string(i) + "]")] = false;
+    tied_pins[id_PLLE2_ADV][id_DCLK] = false;
+    tied_pins[id_PLLE2_ADV][id_DEN] = false;
+    for (int i = 0; i < 16; i++)
+        tied_pins[id_PLLE2_ADV][ctx->id("DI[" + std::to_string(i) + "]")] = false;
+    tied_pins[id_PLLE2_ADV][id_DWE] = false;
+    tied_pins[id_PLLE2_ADV][id_PWRDWN] = false;
+    tied_pins[id_PLLE2_ADV][id_RST] = false;
+
+    // Misc clock buffers
+    tied_pins[id_BUFGCE_DIV][id_CE] = true;
+    tied_pins[id_BUFGCE_DIV][id_CLR] = false;
+    tied_pins[id_BUFGCE][id_CE] = true;
+
+    tied_pins[id_DSP48E1][id_CLK] = false;
+    tied_pins[id_DSP48E1][id_RSTA] = false;
+    tied_pins[id_DSP48E1][id_RSTALLCARRYIN] = false;
+    tied_pins[id_DSP48E1][id_RSTALUMODE] = false;
+    tied_pins[id_DSP48E1][id_RSTB] = false;
+    tied_pins[id_DSP48E1][id_RSTC] = false;
+    tied_pins[id_DSP48E1][id_RSTCTRL] = false;
+    tied_pins[id_DSP48E1][id_RSTD] = false;
+    tied_pins[id_DSP48E1][id_RSTINMODE] = false;
+    tied_pins[id_DSP48E1][id_RSTM] = false;
+    tied_pins[id_DSP48E1][id_RSTP] = false;
+
+    tied_pins[id_DSP48E1][id_CARRYIN] = false;
+
+    tied_pins[id_DSP48E1][id_CEA1] = false;
+    tied_pins[id_DSP48E1][id_CEA2] = false;
+    tied_pins[id_DSP48E1][id_CEAD] = false;
+    tied_pins[id_DSP48E1][id_CEALUMODE] = false;
+    tied_pins[id_DSP48E1][id_CEB1] = false;
+    tied_pins[id_DSP48E1][id_CEB2] = false;
+    tied_pins[id_DSP48E1][id_CEC] = false;
+    tied_pins[id_DSP48E1][id_CECARRYIN] = false;
+    tied_pins[id_DSP48E1][id_CECTRL] = false;
+    tied_pins[id_DSP48E1][id_CED] = false;
+    tied_pins[id_DSP48E1][id_CEINMODE] = false;
+    tied_pins[id_DSP48E1][id_CEM] = false;
+    tied_pins[id_DSP48E1][id_CEP] = false;
+    for (int i = 0; i < 30; i++)
+        tied_pins[id_DSP48E1][ctx->id("A[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 18; i++)
+        tied_pins[id_DSP48E1][ctx->id("B[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 48; i++)
+        tied_pins[id_DSP48E1][ctx->id("C[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 25; i++)
+        tied_pins[id_DSP48E1][ctx->id("D[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 4; i++)
+        tied_pins[id_DSP48E1][ctx->id("ALUMODE[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 3; i++)
+        tied_pins[id_DSP48E1][ctx->id("CARRYINSEL[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 5; i++)
+        tied_pins[id_DSP48E1][ctx->id("INMODE[" + std::to_string(i) + "]")] = false;
+    for (int i = 0; i < 7; i++)
+        tied_pins[id_DSP48E1][ctx->id("OPMODE[" + std::to_string(i) + "]")] = false;
+}
+
+// Get a list of logical pins that have both L and U bel pins that need
+// to be connected for a 36-bit BRAM
+void get_bram36_ul_pins(Context *ctx, std::vector<std::pair<IdString, std::vector<std::string>>> &ul_pins)
+{
+    BelId spec_bel;
+    for (auto bel : ctx->getBels()) {
+        if (ctx->getBelType(bel) == id_RAMB36E1_RAMB36E1) {
+            spec_bel = bel;
+            break;
+        }
+    }
+    NPNR_ASSERT(spec_bel != BelId());
+    pool<std::string> belpins;
+    for (auto &bp : ctx->getBelPins(spec_bel))
+        if (ctx->getBelPinType(spec_bel, bp) == PORT_IN)
+            belpins.insert(bp.str(ctx));
+    for (auto &bp : belpins) {
+        std::string bus_suffix = "";
+        std::string root_name = bp;
+        if (std::isdigit(bp.back())) {
+            auto root_end = bp.find_last_not_of("0123456789");
+            bus_suffix = bp.substr(root_end + 1);
+            root_name = bp.substr(0, root_end + 1);
+        }
+        if (root_name.back() != 'L')
+            continue;
+        std::string base_name = root_name.substr(0, root_name.length() - 1);
+        std::string complement = base_name + "U" + bus_suffix;
+        if (!belpins.count(complement))
+            continue;
+        std::string logical_name = bus_suffix.empty() ? base_name : (base_name + "[" + bus_suffix + "]");
+        ul_pins.emplace_back(ctx->id(logical_name), std::vector<std::string>{bp, complement});
+    }
+}
+
+// Gets a list of pins that are to be directly connected to a top level IO pin (only)
+void get_top_level_pins(Context *ctx, dict<IdString, pool<IdString>> &toplevel_pins)
+{
+    toplevel_pins[id_IBUF] = {id_I};
+    toplevel_pins[id_IBUF_ANALOG] = {id_I};
+    toplevel_pins[id_IBUF_IBUFDISABLE] = {id_I};
+    toplevel_pins[id_IBUF_INTERMDISABLE] = {id_I};
+    toplevel_pins[id_IBUFE3] = {id_I};
+
+    toplevel_pins[id_IBUFDS] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_DIFF_OUT] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_DIFF_OUT_IBUFDISABLE] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_DIFF_OUT_INTERMDISABLE] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_GTE3] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_GTE4] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDS_INTERMDISABLE] = {id_I, id_IB};
+    toplevel_pins[id_IBUFDSE3] = {id_I, id_IB};
+
+    toplevel_pins[id_IOBUF] = {id_IO};
+    toplevel_pins[id_IOBUF_DCIEN] = {id_IO};
+    toplevel_pins[id_IOBUF_INTERMDISABLE] = {id_IO};
+    toplevel_pins[id_IOBUFE3] = {id_IO};
+
+    toplevel_pins[id_IOBUFDS] = {id_IO, id_IOB};
+    toplevel_pins[id_IOBUFDS_DCIEN] = {id_IO, id_IOB};
+    toplevel_pins[id_IOBUFDS_DIFF_OUT] = {id_IO, id_IOB};
+    toplevel_pins[id_IOBUFDS_DIFF_OUT_DCIEN] = {id_IO, id_IOB};
+    toplevel_pins[id_IOBUFDS_DIFF_OUT_INTERMDISABLE] = {id_IO, id_IOB};
+    toplevel_pins[id_IOBUFDSE3] = {id_IO, id_IOB};
+
+    toplevel_pins[id_OBUF] = {id_O};
+    toplevel_pins[id_OBUFT] = {id_O};
+
+    toplevel_pins[id_OBUFDS] = {id_O, id_OB};
+    toplevel_pins[id_OBUFDS_GTE3] = {id_O, id_OB};
+    toplevel_pins[id_OBUFDS_GTE3_ADV] = {id_O, id_OB};
+    toplevel_pins[id_OBUFDS_GTE4] = {id_O, id_OB};
+    toplevel_pins[id_OBUFDS_GTE4_ADV] = {id_O, id_OB};
+    toplevel_pins[id_OBUFTDS] = {id_O, id_OB};
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/pins.h b/himbaechel/uarch/xilinx/pins.h
new file mode 100644
index 0000000000..e1a7bed5d9
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pins.h
@@ -0,0 +1,34 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  Myrtle Shah <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HB_XILINX_PINS_H
+#define HB_XILINX_PINS_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void get_invertible_pins(Context *ctx, dict<IdString, pool<IdString>> &invertible_pins);
+void get_tied_pins(Context *ctx, dict<IdString, dict<IdString, bool>> &tied_pins);
+void get_bram36_ul_pins(Context *ctx, std::vector<std::pair<IdString, std::vector<std::string>>> &ul_pins);
+void get_top_level_pins(Context *ctx, dict<IdString, pool<IdString>> &toplevel_pins);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
\ No newline at end of file
diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
new file mode 100644
index 0000000000..499a623ae1
--- /dev/null
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -0,0 +1,200 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <fstream>
+#include <regex>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "xilinx.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void XilinxImpl::parse_xdc(const std::string &filename)
+{
+    std::ifstream in(filename);
+    if (!in)
+        log_error("failed to open XDC file '%s'\n", filename.c_str());
+    std::string line;
+    std::string linebuf;
+    int lineno = 0;
+
+    auto isempty = [](const std::string &str) {
+        return std::all_of(str.begin(), str.end(), [](char c) { return std::isspace(c); });
+    };
+    auto strip_quotes = [](const std::string &str) {
+        if (str.at(0) == '"') {
+            NPNR_ASSERT(str.back() == '"');
+            return str.substr(1, str.size() - 2);
+        } else if (str.at(0) == '{') {
+            NPNR_ASSERT(str.back() == '}');
+            return str.substr(1, str.size() - 2);
+        } else {
+            return str;
+        }
+    };
+    auto split_to_args = [](const std::string &str, bool group_brackets) {
+        std::vector<std::string> split_args;
+        std::string buffer;
+        auto flush = [&]() {
+            if (!buffer.empty())
+                split_args.push_back(buffer);
+            buffer.clear();
+        };
+        int brcount = 0;
+        for (char c : str) {
+            if ((c == '[' || c == '{') && group_brackets) {
+                ++brcount;
+            }
+            if ((c == ']' || c == '}') && group_brackets) {
+                --brcount;
+                buffer += c;
+                if (brcount == 0)
+                    flush();
+                continue;
+            }
+            if (std::isspace(c)) {
+                if (brcount == 0) {
+                    flush();
+                    continue;
+                }
+            }
+            buffer += c;
+        }
+        flush();
+        return split_args;
+    };
+
+    auto get_cells = [&](std::string str) {
+        std::vector<CellInfo *> tgt_cells;
+        if (str.empty() || str.front() != '[')
+            log_error("failed to parse target (on line %d)\n", lineno);
+        str = str.substr(1, str.size() - 2);
+        auto split = split_to_args(str, false);
+        if (split.size() < 1)
+            log_error("failed to parse target (on line %d)\n", lineno);
+        if (split.front() != "get_ports")
+            log_error("targets other than 'get_ports' are not supported (on line %d)\n", lineno);
+        if (split.size() < 2)
+            log_error("failed to parse target (on line %d)\n", lineno);
+        IdString cellname = ctx->id(strip_quotes(split.at(1)));
+        if (ctx->cells.count(cellname))
+            tgt_cells.push_back(ctx->cells.at(cellname).get());
+        return tgt_cells;
+    };
+
+    auto get_nets = [&](std::string str) {
+        std::vector<NetInfo *> tgt_nets;
+        if (str.empty() || str.front() != '[')
+            log_error("failed to parse target (on line %d)\n", lineno);
+        str = str.substr(1, str.size() - 2);
+        auto split = split_to_args(str, false);
+        if (split.size() < 1)
+            log_error("failed to parse target (on line %d)\n", lineno);
+        if (split.front() != "get_ports" && split.front() != "get_nets")
+            log_error("targets other than 'get_ports' or 'get_nets' are not supported (on line %d)\n", lineno);
+        if (split.size() < 2)
+            log_error("failed to parse target (on line %d)\n", lineno);
+        IdString netname = ctx->id(split.at(1));
+        NetInfo *maybe_net = ctx->getNetByAlias(netname);
+        if (maybe_net != nullptr)
+            tgt_nets.push_back(maybe_net);
+        return tgt_nets;
+    };
+
+    while (std::getline(in, line)) {
+        ++lineno;
+        // Trim comments, from # until end of the line
+        size_t cstart = line.find('#');
+        if (cstart != std::string::npos)
+            line = line.substr(0, cstart);
+        if (isempty(line))
+            continue;
+
+        std::vector<std::string> arguments = split_to_args(line, true);
+        if (arguments.empty())
+            continue;
+        std::string &cmd = arguments.front();
+        if (cmd == "set_property") {
+            std::vector<std::pair<std::string, std::string>> arg_pairs;
+            if (arguments.size() != 4)
+                log_error("expected four arguments to 'set_property' (on line %d)\n", lineno);
+            else if (arguments.at(1) == "-dict") {
+                std::vector<std::string> dict_args = split_to_args(strip_quotes(arguments.at(2)), false);
+                if ((dict_args.size() % 2) != 0)
+                    log_error("expected an even number of argument for dictionary (on line %d)\n", lineno);
+                arg_pairs.reserve(dict_args.size() / 2);
+                for (int cursor = 0; cursor + 1 < int(dict_args.size()); cursor += 2) {
+                    arg_pairs.emplace_back(std::move(dict_args.at(cursor)), std::move(dict_args.at(cursor + 1)));
+                }
+            } else
+                arg_pairs.emplace_back(std::move(arguments.at(1)), std::move(arguments.at(2)));
+            if (arguments.at(1) == "INTERNAL_VREF")
+                continue;
+            if (arguments.at(3).size() > 2 && arguments.at(3) == "[current_design]") {
+                log_warning("[current_design] isn't supported, ignoring (on line %d)\n", lineno);
+                continue;
+            }
+            std::vector<CellInfo *> dest = get_cells(arguments.at(3));
+            for (auto c : dest)
+                for (const auto &pair : arg_pairs)
+                    c->attrs[ctx->id(pair.first)] = std::string(pair.second);
+        } else if (cmd == "create_clock") {
+            double period = 0;
+            bool got_period = false;
+            int cursor = 1;
+            for (cursor = 1; cursor < int(arguments.size()); cursor++) {
+                std::string opt = arguments.at(cursor);
+                if (opt == "-add")
+                    ;
+                else if (opt == "-name" || opt == "-waveform")
+                    cursor++;
+                else if (opt == "-period") {
+                    cursor++;
+                    period = std::stod(arguments.at(cursor));
+                    got_period = true;
+                } else
+                    break;
+            }
+            if (!got_period)
+                log_error("found create_clock without period (on line %d)", lineno);
+            std::vector<NetInfo *> dest = get_nets(arguments.at(cursor));
+            for (auto n : dest) {
+                n->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint);
+                n->clkconstr->period = DelayPair(ctx->getDelayFromNS(period));
+                n->clkconstr->high = DelayPair(ctx->getDelayFromNS(period / 2));
+                n->clkconstr->low = DelayPair(ctx->getDelayFromNS(period / 2));
+            }
+        } else {
+            log_info("ignoring unsupported XDC command '%s' (on line %d)\n", cmd.c_str(), lineno);
+        }
+    }
+    if (!isempty(linebuf))
+        log_error("unexpected end of XDC file\n");
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc
new file mode 100644
index 0000000000..f5ff8b5a59
--- /dev/null
+++ b/himbaechel/uarch/xilinx/xilinx.cc
@@ -0,0 +1,557 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <queue>
+#include <regex>
+
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "placer_heap.h"
+#include "xilinx.h"
+
+#include "himbaechel_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+XilinxImpl::~XilinxImpl(){};
+
+void XilinxImpl::init_database(Arch *arch)
+{
+    const ArchArgs &args = arch->args;
+    init_uarch_constids(arch);
+    std::regex devicere = std::regex("(xc7[azkv]\\d+t)([a-z0-9]+)-(\\dL?)");
+    std::smatch match;
+    if (!std::regex_match(args.device, match, devicere)) {
+        log_error("Invalid device %s\n", args.device.c_str());
+    }
+    std::string die = match[1].str();
+    if (die == "xc7a35t")
+        die = "xc7a50t";
+    arch->load_chipdb(stringf("xilinx/chipdb-%s.bin", die.c_str()));
+    std::string package = match[2].str();
+    arch->set_package(package);
+    arch->set_speed_grade("DEFAULT");
+}
+
+void XilinxImpl::init(Context *ctx)
+{
+    h.init(ctx);
+    HimbaechelAPI::init(ctx);
+
+    tile_status.resize(ctx->chip_info->tile_insts.size());
+    for (int i = 0; i < ctx->chip_info->tile_insts.ssize(); i++) {
+        auto extra_data = tile_extra_data(i);
+        tile_status.at(i).site_variant.resize(extra_data->sites.ssize());
+    }
+}
+
+SiteIndex XilinxImpl::get_bel_site(BelId bel) const
+{
+    auto &bel_data = chip_bel_info(ctx->chip_info, bel);
+    auto site_key = BelSiteKey::unpack(bel_data.site);
+    return SiteIndex(bel.tile, site_key.site);
+}
+
+IdString XilinxImpl::get_site_name(SiteIndex site) const
+{
+    const auto &site_data = tile_extra_data(site.tile)->sites[site.site];
+    return ctx->idf("%s_X%dY%d", IdString(site_data.name_prefix).c_str(ctx), site_data.site_x, site_data.site_y);
+}
+
+BelId XilinxImpl::get_site_bel(SiteIndex site, IdString bel_name) const
+{
+    const auto &tile_data = chip_tile_info(ctx->chip_info, site.tile);
+    for (int32_t i = 0; i < tile_data.bels.ssize(); i++) {
+        const auto &bel_data = tile_data.bels[i];
+        if (BelSiteKey::unpack(bel_data.site).site != site.site)
+            continue;
+        if (reinterpret_cast<const XlnxBelExtraDataPOD *>(bel_data.extra_data.get())->name_in_site != bel_name.index)
+            continue;
+        return BelId(site.tile, i);
+    }
+    return BelId();
+}
+
+IdString XilinxImpl::bel_name_in_site(BelId bel) const
+{
+    const auto &bel_data = chip_bel_info(ctx->chip_info, bel);
+    return IdString(reinterpret_cast<const XlnxBelExtraDataPOD *>(bel_data.extra_data.get())->name_in_site);
+}
+
+IdStringList XilinxImpl::get_site_bel_name(BelId bel) const
+{
+    return IdStringList::concat(get_site_name(get_bel_site(bel)), bel_name_in_site(bel));
+}
+
+void XilinxImpl::notifyBelChange(BelId bel, CellInfo *cell)
+{
+    auto &ts = tile_status.at(bel.tile);
+    auto &bel_data = chip_bel_info(ctx->chip_info, bel);
+    auto site_key = BelSiteKey::unpack(bel_data.site);
+    // Update bound site variant for pip validity use later on
+    if (cell && cell->type != id_PAD && site_key.site >= 0 && site_key.site < int(ts.site_variant.size())) {
+        ts.site_variant.at(site_key.site) = site_key.site_variant;
+    }
+    if (is_logic_tile(bel))
+        update_logic_bel(bel, cell);
+    if (is_bram_tile(bel))
+        update_bram_bel(bel, cell);
+}
+
+void XilinxImpl::update_logic_bel(BelId bel, CellInfo *cell)
+{
+    int z = ctx->getBelLocation(bel).z;
+    NPNR_ASSERT(z < 128);
+    auto &tts = tile_status.at(bel.tile);
+    if (!tts.lts)
+        tts.lts = std::make_unique<LogicTileStatus>();
+    auto &ts = *(tts.lts);
+    auto tags = get_tags(cell), last_tags = get_tags(ts.cells[z]);
+    if ((z == ((3 << 4) | BEL_6LUT)) || (z == ((3 << 4) | BEL_5LUT))) {
+        if ((tags && tags->lut.is_memory) || (last_tags && last_tags->lut.is_memory)) {
+            // Special case - memory write port invalidates everything
+            for (int i = 0; i < 8; i++)
+                ts.eights[i].dirty = true;
+            // if (xc7)
+            ts.halfs[0].dirty = true; // WCLK and CLK0 shared
+        }
+    }
+    if ((((z & 0xF) == BEL_6LUT) || ((z & 0xF) == BEL_5LUT)) &&
+        ((tags && tags->lut.is_srl) || (last_tags && last_tags->lut.is_srl))) {
+        // SRLs invalidate everything due to write clock
+        for (int i = 0; i < 8; i++)
+            ts.eights[i].dirty = true;
+        // if (xc7)
+        ts.halfs[0].dirty = true; // WCLK and CLK0 shared
+    }
+
+    ts.cells[z] = cell;
+
+    // determine which sections to mark as dirty
+    switch (z & 0xF) {
+    case BEL_FF:
+    case BEL_FF2:
+        ts.halfs[(z >> 4) / 4].dirty = true;
+        if ((((z >> 4) / 4) == 0) /*&& xc7*/)
+            ts.eights[3].dirty = true;
+    /* fall-through */
+    case BEL_6LUT:
+    case BEL_5LUT:
+        ts.eights[z >> 4].dirty = true;
+        break;
+    case BEL_F7MUX:
+        ts.eights[z >> 4].dirty = true;
+        ts.eights[(z >> 4) + 1].dirty = true;
+        break;
+    case BEL_F8MUX:
+        ts.eights[(z >> 4) + 1].dirty = true;
+        ts.eights[(z >> 4) + 2].dirty = true;
+        break;
+    case BEL_CARRY4:
+        for (int i = ((z >> 4) / 4) * 4; i < (((z >> 4) / 4) + 1) * 4; i++)
+            ts.eights[i].dirty = true;
+        break;
+    }
+}
+
+void XilinxImpl::update_bram_bel(BelId bel, CellInfo *cell) {}
+
+bool XilinxImpl::is_pip_unavail(PipId pip) const
+{
+    const auto &pip_data = chip_pip_info(ctx->chip_info, pip);
+    const auto &extra_data = *reinterpret_cast<const XlnxPipExtraDataPOD *>(pip_data.extra_data.get());
+    unsigned pip_type = pip_data.flags;
+    if (pip_type == PIP_SITE_ENTRY) {
+        WireId dst = ctx->getPipDstWire(pip);
+        if (ctx->getWireType(dst) == id_INTENT_SITE_GND) {
+            const auto &lts = tile_status[dst.tile].lts;
+            if (lts && (lts->cells[BEL_5LUT] != nullptr || lts->cells[BEL_6LUT] != nullptr))
+                return true; // Ground driver only available if lowest 5LUT and 6LUT not used
+        }
+    } else if (pip_type == PIP_CONST_DRIVER) {
+        WireId dst = ctx->getPipDstWire(pip);
+        const auto &lts = tile_status[dst.tile].lts;
+        if (lts && (lts->cells[BEL_5LUT] != nullptr || lts->cells[BEL_6LUT] != nullptr))
+            return true; // Ground driver only available if lowest 5LUT and 6LUT not used
+    } else if (pip_type == PIP_SITE_INTERNAL) {
+        if (extra_data.bel_name == ID_TRIBUF)
+            return true;
+        auto site = BelSiteKey::unpack(extra_data.site_key);
+        // Check site variant of PIP matches configured site variant of tile
+        if (site.site >= 0 && site.site < int(tile_status[pip.tile].site_variant.size())) {
+            if (site.site_variant > 0 && site.site_variant != tile_status[pip.tile].site_variant.at(site.site))
+                return true;
+        }
+    } else if (pip_type == PIP_LUT_PERMUTATION) {
+        const auto &lts = tile_status[pip.tile].lts;
+        if (!lts)
+            return false;
+        int eight = (extra_data.pip_config >> 8) & 0xF;
+
+        if (((extra_data.pip_config >> 4) & 0xF) == (extra_data.pip_config & 0xF))
+            return false; // from==to, always valid
+
+        auto lut6 = get_tags(lts->cells[(eight << 4) | BEL_6LUT]);
+        if (lut6 && (lut6->lut.is_memory || lut6->lut.is_srl))
+            return true;
+        auto lut5 = get_tags(lts->cells[(eight << 4) | BEL_5LUT]);
+        if (lut5 && (lut5->lut.is_memory || lut5->lut.is_srl))
+            return true;
+    } else if (pip_type == PIP_LUT_ROUTETHRU) {
+        int eight = (extra_data.pip_config >> 8) & 0xF;
+        int dest = (extra_data.pip_config & 0x1);
+        if (eight == 0)
+            return true; // FIXME: conflict with ground
+        if (dest & 0x1)
+            return true; // FIXME: routethru to MUX
+        const auto &lts = tile_status[pip.tile].lts;
+        if (!lts)
+            return false;
+        const CellInfo *lut6 = lts->cells[(eight << 4) | BEL_6LUT];
+        if (lut6)
+            return true;
+        const CellInfo *lut5 = lts->cells[(eight << 4) | BEL_5LUT];
+        if (lut5)
+            return true;
+    }
+
+    return false;
+}
+
+void XilinxImpl::prePlace() { assign_cell_tags(); }
+
+void XilinxImpl::postPlace()
+{
+    fixup_placement();
+    ctx->assignArchInfo();
+}
+
+void XilinxImpl::configurePlacerHeap(PlacerHeapCfg &cfg)
+{
+    cfg.hpwl_scale_x = 2;
+    cfg.hpwl_scale_y = 1;
+    cfg.beta = 0.5;
+    cfg.placeAllAtOnce = true;
+}
+
+void XilinxImpl::preRoute()
+{
+    find_source_sink_locs();
+    route_clocks();
+}
+
+void XilinxImpl::postRoute()
+{
+    fixup_routing();
+    ctx->assignArchInfo();
+    const ArchArgs &args = ctx->args;
+    if (args.options.count("fasm")) {
+        write_fasm(args.options.at("fasm"));
+    }
+}
+
+IdString XilinxImpl::bel_tile_type(BelId bel) const
+{
+    return IdString(chip_tile_info(ctx->chip_info, bel.tile).type_name);
+}
+
+bool XilinxImpl::is_logic_tile(BelId bel) const
+{
+    return bel_tile_type(bel).in(id_CLEL_L, id_CLEL_R, id_CLEM, id_CLEM_R, id_CLBLL_L, id_CLBLL_R, id_CLBLM_L,
+                                 id_CLBLM_R);
+}
+bool XilinxImpl::is_bram_tile(BelId bel) const { return bel_tile_type(bel).in(id_BRAM, id_BRAM_L, id_BRAM_R); }
+
+const XlnxTileInstExtraDataPOD *XilinxImpl::tile_extra_data(int tile) const
+{
+    return reinterpret_cast<const XlnxTileInstExtraDataPOD *>(ctx->chip_info->tile_insts[tile].extra_data.get());
+}
+
+std::string XilinxImpl::tile_name(int tile) const
+{
+    const auto &data = *tile_extra_data(tile);
+    return stringf("%s_X%dY%d", IdString(data.name_prefix).c_str(ctx), data.tile_x, data.tile_y);
+}
+
+Loc XilinxImpl::rel_site_loc(SiteIndex site) const
+{
+    const auto &site_data = tile_extra_data(site.tile)->sites[site.site];
+    return Loc(site_data.rel_x, site_data.rel_y, 0);
+}
+
+int XilinxImpl::hclk_for_iob(BelId pad) const
+{
+    std::string tile_type = bel_tile_type(pad).str(ctx);
+    int ioi = pad.tile;
+    if (boost::starts_with(tile_type, "LIOB"))
+        ioi += 1;
+    else if (boost::starts_with(tile_type, "RIOB"))
+        ioi -= 1;
+    else
+        NPNR_ASSERT_FALSE("unknown IOB side");
+    return hclk_for_ioi(ioi);
+}
+
+int XilinxImpl::hclk_for_ioi(int tile) const
+{
+    WireId ioclk0;
+    auto &td = chip_tile_info(ctx->chip_info, tile);
+    for (int i = 0; i < td.wires.ssize(); i++) {
+        std::string name = IdString(td.wires[i].name).str(ctx);
+        if (name == "IOI_IOCLK0" || name == "IOI_SING_IOCLK0") {
+            ioclk0 = ctx->normalise_wire(tile, i);
+            break;
+        }
+    }
+    NPNR_ASSERT(ioclk0 != WireId());
+    for (auto uh : ctx->getPipsUphill(ioclk0))
+        return uh.tile;
+    NPNR_ASSERT_FALSE("failed to find HCLK pips");
+}
+
+void XilinxImpl::assign_cell_tags()
+{
+    cell_tags.resize(ctx->cells.size());
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        auto &ct = cell_tags.at(ci->flat_index);
+        if (ci->type == id_SLICE_LUTX) {
+            ct.lut.input_count = 0;
+            for (IdString a : {id_A1, id_A2, id_A3, id_A4, id_A5, id_A6}) {
+                NetInfo *pn = ci->getPort(a);
+                if (pn != nullptr)
+                    ct.lut.input_sigs[ct.lut.input_count++] = pn;
+            }
+            ct.lut.output_count = 0;
+            for (IdString o : {id_O6, id_O5}) {
+                NetInfo *pn = ci->getPort(o);
+                if (pn != nullptr)
+                    ct.lut.output_sigs[ct.lut.output_count++] = pn;
+            }
+            for (int i = ct.lut.output_count; i < 2; i++)
+                ct.lut.output_sigs[i] = nullptr;
+            ct.lut.di1_net = ci->getPort(id_DI1);
+            ct.lut.di2_net = ci->getPort(id_DI2);
+            ct.lut.wclk = ci->getPort(id_CLK);
+            ct.lut.memory_group = 0; // fixme
+            ct.lut.is_srl = ci->attrs.count(id_X_LUT_AS_SRL);
+            ct.lut.is_memory = ci->attrs.count(id_X_LUT_AS_DRAM);
+            ct.lut.only_drives_carry = false;
+            if (ci->cluster != ClusterId() && ct.lut.output_count > 0 && ct.lut.output_sigs[0] != nullptr &&
+                ct.lut.output_sigs[0]->users.entries() == 1 &&
+                (*ct.lut.output_sigs[0]->users.begin()).cell->type == id_CARRY4)
+                ct.lut.only_drives_carry = true;
+
+            const IdString addr_msb_sigs[] = {id_WA7, id_WA8, id_WA9};
+            for (int i = 0; i < 3; i++)
+                ct.lut.address_msb[i] = ci->getPort(addr_msb_sigs[i]);
+
+        } else if (ci->type == id_SLICE_FFX) {
+            ct.ff.d = ci->getPort(id_D);
+            ct.ff.clk = ci->getPort(id_CK);
+            ct.ff.ce = ci->getPort(id_CE);
+            ct.ff.sr = ci->getPort(id_SR);
+            ct.ff.is_clkinv = bool_or_default(ci->params, id_IS_CLK_INVERTED, false);
+            ct.ff.is_srinv = bool_or_default(ci->params, id_IS_R_INVERTED, false) ||
+                             bool_or_default(ci->params, id_IS_S_INVERTED, false) ||
+                             bool_or_default(ci->params, id_IS_CLR_INVERTED, false) ||
+                             bool_or_default(ci->params, id_IS_PRE_INVERTED, false);
+            ct.ff.is_latch = ci->attrs.count(id_X_FF_AS_LATCH);
+            ct.ff.ffsync = ci->attrs.count(id_X_FFSYNC);
+        } else if (ci->type.in(id_F7MUX, id_F8MUX, id_F9MUX, id_SELMUX2_1)) {
+            ct.mux.sel = ci->getPort(id_S0);
+            ct.mux.out = ci->getPort(id_OUT);
+        } else if (ci->type == id_CARRY4) {
+            for (int i = 0; i < 4; i++) {
+                ct.carry.out_sigs[i] = ci->getPort(ctx->idf("O%d", i));
+                ct.carry.cout_sigs[i] = ci->getPort(ctx->idf("CO%d", i));
+                ct.carry.x_sigs[i] = nullptr;
+            }
+            ct.carry.x_sigs[0] = ci->getPort(id_CYINIT);
+        }
+    }
+}
+
+bool XilinxImpl::is_general_routing(WireId wire) const
+{
+    IdString intent = ctx->getWireType(wire);
+    return !intent.in(id_INTENT_DEFAULT, id_NODE_DEDICATED, id_NODE_OPTDELAY, id_NODE_OUTPUT, id_NODE_INT_INTERFACE,
+                      id_PINFEED, id_INPUT, id_PADOUTPUT, id_PADINPUT, id_IOBINPUT, id_IOBOUTPUT, id_GENERIC,
+                      id_IOBIN2OUT, id_INTENT_SITE_WIRE, id_INTENT_SITE_GND);
+}
+
+void XilinxImpl::find_source_sink_locs()
+{
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        for (auto &usr : ni->users) {
+            BelId bel = usr.cell->bel;
+            if (bel == BelId() || is_logic_tile(bel))
+                continue; // don't need to do this for logic bels, which are always next to their INT
+            WireId sink = ctx->getNetinfoSinkWire(ni, usr, 0);
+            if (sink == WireId() || sink_locs.count(sink))
+                continue;
+            std::queue<WireId> visit;
+            dict<WireId, WireId> backtrace;
+            int iter = 0;
+            // as this is a best-effort optimisation to slightly improve routing,
+            // don't spend too long with a nice low iteration limit
+            const int iter_max = 500;
+            visit.push(sink);
+            while (!visit.empty() && iter < iter_max) {
+                ++iter;
+                WireId cursor = visit.front();
+                visit.pop();
+                if (is_general_routing(cursor)) {
+                    Loc loc(0, 0, 0);
+                    tile_xy(ctx->chip_info, cursor.tile, loc.x, loc.y);
+                    sink_locs[sink] = loc;
+
+                    while (backtrace.count(cursor)) {
+                        cursor = backtrace.at(cursor);
+                        if (!sink_locs.count(cursor)) {
+                            sink_locs[cursor] = loc;
+                        }
+                    }
+
+                    break;
+                }
+                for (auto pip : ctx->getPipsUphill(cursor)) {
+                    WireId src = ctx->getPipSrcWire(pip);
+                    if (!backtrace.count(src)) {
+                        backtrace[src] = cursor;
+                        visit.push(src);
+                    }
+                }
+            }
+        }
+        auto &drv = ni->driver;
+        if (drv.cell != nullptr) {
+            BelId bel = drv.cell->bel;
+            if (bel == BelId() || is_logic_tile(bel))
+                continue; // don't need to do this for logic bels, which are always next to their INT
+            WireId source = ctx->getNetinfoSourceWire(ni);
+            if (source == WireId() || source_locs.count(source))
+                continue;
+            std::queue<WireId> visit;
+            dict<WireId, WireId> backtrace;
+            int iter = 0;
+            // as this is a best-effort optimisation to slightly improve routing,
+            // don't spend too long with a nice low iteration limit
+            const int iter_max = 500;
+            visit.push(source);
+            while (!visit.empty() && iter < iter_max) {
+                ++iter;
+                WireId cursor = visit.front();
+                visit.pop();
+                if (is_general_routing(cursor)) {
+                    Loc loc(0, 0, 0);
+                    tile_xy(ctx->chip_info, cursor.tile, loc.x, loc.y);
+                    source_locs[source] = loc;
+
+                    while (backtrace.count(cursor)) {
+                        cursor = backtrace.at(cursor);
+                        if (!source_locs.count(cursor)) {
+                            source_locs[cursor] = loc;
+                        }
+                    }
+
+                    break;
+                }
+                for (auto pip : ctx->getPipsDownhill(cursor)) {
+                    WireId dst = ctx->getPipDstWire(pip);
+                    if (!backtrace.count(dst)) {
+                        backtrace[dst] = cursor;
+                        visit.push(dst);
+                    }
+                }
+            }
+        }
+    }
+}
+
+delay_t XilinxImpl::estimateDelay(WireId src, WireId dst) const
+{
+    int sx, sy, dx, dy;
+    tile_xy(ctx->chip_info, src.tile, sx, sy);
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    auto fnd_src = source_locs.find(src);
+    if (fnd_src != source_locs.end()) {
+        sx = fnd_src->second.x;
+        sy = fnd_src->second.y;
+    }
+    auto fnd_snk = sink_locs.find(dst);
+    if (fnd_snk != sink_locs.end()) {
+        dx = fnd_snk->second.x;
+        dy = fnd_snk->second.y;
+    }
+    // TODO: improve sophistication here based on old nextpnr-xilinx code
+    return 800 + 50 * (std::abs(dy - sy) + std::abs(dx - sx));
+}
+
+BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const
+{
+    int x0, y0, x1, y1;
+    auto expand = [&](int x, int y) {
+        x0 = std::min(x0, x);
+        x1 = std::max(x1, x);
+        y0 = std::min(y0, y);
+        y1 = std::max(y1, y);
+    };
+
+    tile_xy(ctx->chip_info, src.tile, x0, y0);
+    x1 = x0;
+    y1 = y0;
+
+    int dx, dy;
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    expand(dx, dy);
+
+    auto fnd_src = source_locs.find(src);
+    if (fnd_src != source_locs.end()) {
+        expand(fnd_src->second.x, fnd_src->second.y);
+    }
+    auto fnd_snk = sink_locs.find(dst);
+    if (fnd_snk != sink_locs.end()) {
+        expand(fnd_snk->second.x, fnd_snk->second.y);
+    }
+    return {x0 - 2, y0 - 2, x1 + 2, y1 + 2};
+}
+
+namespace {
+struct XilinxArch : HimbaechelArch
+{
+    XilinxArch() : HimbaechelArch("xilinx"){};
+    bool match_device(const std::string &device) override { return device.size() > 3 && device.substr(0, 3) == "xc7"; }
+    std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<XilinxImpl>();
+    }
+} xilinxArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/xilinx.h b/himbaechel/uarch/xilinx/xilinx.h
new file mode 100644
index 0000000000..1a87c78a52
--- /dev/null
+++ b/himbaechel/uarch/xilinx/xilinx.h
@@ -0,0 +1,180 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_XILINX_H
+#define HIMBAECHEL_XILINX_H
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "himbaechel_helpers.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct XilinxCellTags
+{
+    union
+    {
+        struct
+        {
+            bool is_memory, is_srl;
+            int input_count, output_count;
+            int memory_group;
+            bool only_drives_carry;
+            NetInfo *input_sigs[6], *output_sigs[2];
+            NetInfo *address_msb[3];
+            NetInfo *di1_net, *di2_net, *wclk;
+        } lut;
+        struct
+        {
+            bool is_latch, is_clkinv, is_srinv, ffsync;
+            bool is_paired;
+            NetInfo *clk, *sr, *ce, *d;
+        } ff;
+        struct
+        {
+            NetInfo *out_sigs[8], *cout_sigs[8], *x_sigs[8];
+        } carry;
+        struct
+        {
+            NetInfo *sel, *out;
+        } mux;
+    };
+};
+
+struct SiteIndex
+{
+    SiteIndex() : tile(-1), site(-1){};
+    SiteIndex(int32_t tile, int32_t site) : tile(tile), site(site){};
+
+    int32_t tile;
+    int32_t site;
+    bool operator==(const SiteIndex &other) const { return tile == other.tile && site == other.site; }
+    bool operator!=(const SiteIndex &other) const { return tile != other.tile || site != other.site; }
+    unsigned hash() const { return mkhash(tile, site); }
+};
+
+struct XilinxImpl : HimbaechelAPI
+{
+
+    struct LogicTileStatus
+    {
+        // z -> cell
+        CellInfo *cells[128];
+
+        // Eight-tile valid and dirty status
+        struct EigthTileStatus
+        {
+            mutable bool valid = true, dirty = true;
+        } eights[8];
+        struct HalfTileStatus
+        {
+            mutable bool valid = true, dirty = true;
+        } halfs[8];
+    };
+
+    struct BRAMTileStatus
+    {
+        CellInfo *cells[12] = {nullptr};
+    };
+
+    struct TileStatus
+    {
+        std::unique_ptr<LogicTileStatus> lts;
+        std::unique_ptr<BRAMTileStatus> bts;
+        std::vector<int> site_variant;
+    };
+
+    ~XilinxImpl();
+    void init_database(Arch *arch) override;
+
+    void init(Context *ctx) override;
+
+    // Bels
+    void notifyBelChange(BelId bel, CellInfo *cell) override;
+    void update_logic_bel(BelId bel, CellInfo *cell);
+    void update_bram_bel(BelId bel, CellInfo *cell);
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
+    bool xc7_logic_tile_valid(IdString tileType, const LogicTileStatus &lts) const;
+
+    // Pips
+    bool is_pip_unavail(PipId pip) const;
+    bool checkPipAvail(PipId pip) const override { return !is_pip_unavail(pip); }
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override { return !is_pip_unavail(pip); }
+
+    // Flow management
+    void parse_xdc(const std::string &filename);
+    void pack() override;
+    void prePlace() override;
+    void preRoute() override;
+    void postPlace() override;
+    void postRoute() override;
+    void write_fasm(const std::string &filename);
+
+    void configurePlacerHeap(PlacerHeapCfg &cfg) override;
+
+    void fixup_placement();
+    void fixup_routing();
+    void route_clocks();
+
+    // Misc utility functions
+    const XlnxTileInstExtraDataPOD *tile_extra_data(int tile) const;
+    IdString bel_tile_type(BelId bel) const;
+    bool is_logic_tile(BelId bel) const;
+    bool is_bram_tile(BelId bel) const;
+
+    SiteIndex get_bel_site(BelId bel) const;
+    Loc rel_site_loc(SiteIndex site) const;
+    IdString get_site_name(SiteIndex site) const;
+    IdString bel_name_in_site(BelId bel) const;
+    IdStringList get_site_bel_name(BelId bel) const;
+    BelId get_site_bel(SiteIndex site, IdString bel_name) const;
+
+    int hclk_for_iob(BelId pad) const;
+    int hclk_for_ioi(int tile) const;
+
+    std::string tile_name(int tile) const;
+
+    std::vector<XilinxCellTags> cell_tags;
+    const XilinxCellTags *get_tags(const CellInfo *cell) const
+    {
+        return cell ? &cell_tags.at(cell->flat_index) : nullptr;
+    }
+
+    std::vector<TileStatus> tile_status;
+
+    // Improved delay predictions where sites are located far from their associated interconnect
+    dict<WireId, Loc> source_locs, sink_locs;
+    bool is_general_routing(WireId wire) const;
+    void find_source_sink_locs();
+
+    delay_t estimateDelay(WireId src, WireId dst) const override;
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
+
+  private:
+    HimbaechelHelpers h;
+    void assign_cell_tags();
+};
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/uarch/xilinx/xilinx_place.cc b/himbaechel/uarch/xilinx/xilinx_place.cc
new file mode 100644
index 0000000000..d39b94d026
--- /dev/null
+++ b/himbaechel/uarch/xilinx/xilinx_place.cc
@@ -0,0 +1,640 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019-2023  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <regex>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "xilinx.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// #define DEBUG_VALIDITY
+#ifdef DEBUG_VALIDITY
+#define DBG() log_info("invalid: %s %d\n", __FILE__, __LINE__)
+#else
+#define DBG()
+#endif
+
+bool XilinxImpl::xc7_logic_tile_valid(IdString tile_type, const LogicTileStatus &lts) const
+{
+    bool is_slicem = (tile_type == id_CLBLM_L) || (tile_type == id_CLBLM_R);
+    bool tile_is_memory = false;
+    if (lts.cells[(3 << 4) | BEL_6LUT] != nullptr && get_tags(lts.cells[(3 << 4) | BEL_6LUT])->lut.is_memory)
+        tile_is_memory = true;
+    bool small_memory = false;
+    if (lts.cells[(3 << 4) | BEL_5LUT] != nullptr && get_tags(lts.cells[(3 << 4) | BEL_5LUT])->lut.is_memory)
+        small_memory = true;
+    NetInfo *wclk = nullptr;
+    // Check eight-tiles (mostly LUT-related validity)
+    for (int i = 0; i < 8; i++) {
+        if (lts.eights[i].dirty) {
+            lts.eights[i].dirty = false;
+            lts.eights[i].valid = false;
+
+            auto lut6 = get_tags(lts.cells[(i << 4) | BEL_6LUT]);
+            auto lut5 = get_tags(lts.cells[(i << 4) | BEL_5LUT]);
+
+            // Check 6LUT
+            if (lut6) {
+                if (!is_slicem && (lut6->lut.is_memory || lut6->lut.is_srl)) {
+                    DBG();
+                    return false;
+                } // Memory and SRLs only valid in SLICEMs
+                if (lut6->lut.is_srl && (i >= 4)) {
+                    DBG();
+                    return false;
+                }
+                if (lut6->lut.is_memory || lut6->lut.is_srl) {
+                    if (wclk == nullptr)
+                        wclk = lut6->lut.wclk;
+                    else if (lut6->lut.wclk != wclk) {
+                        DBG();
+                        return false;
+                    }
+                }
+                if (lut5) {
+                    // Can't mix memory and non-memory
+                    if (lut6->lut.is_memory != lut5->lut.is_memory || lut6->lut.is_srl != lut5->lut.is_srl) {
+                        DBG();
+                        return false;
+                    }
+                    // If all 6 inputs or 2 outputs are used, 5LUT can't also be present
+                    if (lut6->lut.input_count == 6 || lut6->lut.output_count == 2) {
+                        DBG();
+                        return false;
+                    }
+                    // If more than 5 total inputs are used, need to check number of shared input
+                    if ((lut6->lut.input_count + lut5->lut.input_count) > 5) {
+                        int shared = 0, need_shared = (lut6->lut.input_count + lut5->lut.input_count - 5);
+                        for (int j = 0; j < lut6->lut.input_count; j++) {
+                            for (int k = 0; k < lut5->lut.input_count; k++) {
+                                if (lut6->lut.input_sigs[j] == lut5->lut.input_sigs[k])
+                                    shared++;
+                                if (shared >= need_shared)
+                                    break;
+                            }
+                        }
+                        if (shared < need_shared) {
+                            DBG();
+                            return false;
+                        }
+                    }
+                }
+            }
+            if (lut5 != nullptr) {
+                if (!is_slicem && (lut5->lut.is_memory || lut5->lut.is_srl)) {
+                    DBG();
+                    return false; // Memory and SRLs only valid in SLICEMs
+                }
+                if (lut5->lut.is_srl) {
+                    if (wclk == nullptr)
+                        wclk = lut5->lut.wclk;
+                    else if (lut5->lut.wclk != wclk) {
+                        DBG();
+                        return false;
+                    }
+                }
+                // 5LUT can use at most 5 inputs and 1 output
+                if (lut5->lut.input_count > 5 || lut5->lut.output_count == 2) {
+                    DBG();
+                    return false; // Memory and SRLs only valid in SLICEMs
+                }
+            }
+
+            // Check (over)usage ofX inputs
+            NetInfo *x_net = nullptr;
+            if (lut6) {
+                x_net = lut6->lut.di2_net;
+            }
+
+            CellInfo *mux_cell = nullptr;
+            // Eights A, C, E, G: F7MUX uses X input
+            if (i == 0 || i == 2 || i == 4 || i == 6)
+                mux_cell = lts.cells[i << 4 | BEL_F7MUX];
+            // Eights B, F: F8MUX uses X input
+            if (i == 1 || i == 5)
+                mux_cell = lts.cells[(i - 1) << 4 | BEL_F8MUX];
+            auto mux = get_tags(mux_cell);
+            if (mux) {
+                if (x_net)
+                    x_net = mux->mux.sel;
+                else if (x_net != mux->mux.sel) {
+                    DBG();
+                    return false; // Memory and SRLs only valid in SLICEMs
+                }
+            }
+
+            CellInfo *out_fmux_cell = nullptr;
+            // Subslices A, C: F7MUX connects to F7F8 out
+            if (i == 0 || i == 2 || i == 4 || i == 6)
+                out_fmux_cell = lts.cells[(i << 4) | BEL_F7MUX];
+            // Subslices B: F8MUX connects to F7F8 out
+            if (i == 1 || i == 5)
+                out_fmux_cell = lts.cells[(i - 1) << 4 | BEL_F8MUX];
+
+            auto carry4 = get_tags(lts.cells[((i / 4) << 6) | BEL_CARRY4]);
+
+            if (carry4 != nullptr && carry4->carry.x_sigs[i % 4] != nullptr) {
+                if (x_net == nullptr)
+                    x_net = carry4->carry.x_sigs[i % 4];
+                else if (x_net != carry4->carry.x_sigs[i % 4]) {
+                    DBG();
+                    return false;
+                }
+            }
+
+            // FF1 might use X, if it isn't driven directly
+            auto ff1 = get_tags(lts.cells[i << 4 | BEL_FF]);
+            if (ff1 != nullptr && ff1->ff.d != nullptr && ff1->ff.d->driver.cell != nullptr) {
+                auto &drv = ff1->ff.d->driver;
+                if ((drv.cell == lts.cells[(i << 4) | BEL_6LUT] && drv.port != id_MC31) ||
+                    drv.cell == lts.cells[(i << 4) | BEL_5LUT] || drv.cell == out_fmux_cell) {
+                    // Direct, OK
+                } else {
+                    // Indirect, must use X input
+                    if (x_net == nullptr)
+                        x_net = ff1->ff.d;
+                    else if (x_net != ff1->ff.d) {
+                        DBG();
+                        return false;
+                    }
+                }
+            }
+
+            // FF2 might use X, if it isn't driven directly
+            auto ff2 = get_tags(lts.cells[i << 4 | BEL_FF2]);
+            if (ff2 != nullptr && ff2->ff.d != nullptr && ff2->ff.d->driver.cell != nullptr) {
+                auto &drv = ff2->ff.d->driver;
+                if (drv.cell == lts.cells[(i << 4) | BEL_5LUT]) {
+                    // Direct, OK
+                } else {
+                    // Indirect, must use X input
+                    if (x_net == nullptr)
+                        x_net = ff2->ff.d;
+                    else if (x_net != ff2->ff.d) {
+#ifdef DEBUG_VALIDITY
+                        log_info("%s %s %s %s %s\n", nameOf(lut6), nameOf(ff1), nameOf(lut5), nameOf(ff2),
+                                 nameOf(drv.cell));
+#endif
+                        DBG();
+                        return false;
+                    }
+                }
+            }
+
+            // collision with top address bits
+            if (tile_is_memory && !small_memory) {
+                auto top_lut = get_tags(lts.cells[(3 << 4) | BEL_6LUT]);
+                if (top_lut) {
+                    if ((i == 2) && x_net != top_lut->lut.address_msb[0]) {
+                        DBG();
+                        return false;
+                    }
+                    if ((i == 1) && x_net != top_lut->lut.address_msb[1]) {
+                        DBG();
+                        return false;
+                    }
+                }
+            }
+
+            bool mux_output_used = false;
+            NetInfo *out5 = nullptr;
+            if (lut6 != nullptr && lut6->lut.output_count == 2)
+                out5 = lut6->lut.output_sigs[1];
+            else if (lut5 != nullptr && !lut5->lut.only_drives_carry)
+                out5 = lut5->lut.output_sigs[0];
+            if (out5 != nullptr && (out5->users.entries() > 1 ||
+                                    ((ff1 == nullptr || out5 != ff1->ff.d) && (ff2 == nullptr || out5 != ff2->ff.d)))) {
+                mux_output_used = true;
+            }
+
+            if (carry4 != nullptr && carry4->carry.out_sigs[i % 4] != nullptr) {
+                // FIXME: direct connections to FF
+                if (mux_output_used) {
+                    DBG();
+                    return false; // Memory and SRLs only valid in SLICEMs
+                }
+                mux_output_used = true;
+            }
+            if (out_fmux_cell != nullptr) {
+                auto out_fmux = get_tags(out_fmux_cell);
+                NetInfo *f7f8 = out_fmux->mux.out;
+                if (f7f8 != nullptr && (f7f8->users.entries() > 1 || ((ff1 == nullptr || f7f8 != ff1->ff.d)))) {
+                    if (mux_output_used) {
+                        DBG();
+                        return false; // Memory and SRLs only valid in SLICEMs
+                    }
+                    mux_output_used = true;
+                }
+            }
+            if (ff2 != nullptr) {
+                if (mux_output_used) {
+                    DBG();
+                    return false; // Memory and SRLs only valid in SLICEMs
+                }
+                mux_output_used = true;
+            }
+
+            lts.eights[i].valid = true;
+        } else if (!lts.eights[i].valid) {
+            DBG();
+            return false;
+        }
+    }
+    // Check half-tiles
+    for (int i = 0; i < 2; i++) {
+        if (lts.halfs[i].dirty) {
+            lts.halfs[i].valid = false;
+            bool found_ff[2] = {false, false};
+            if (i == 0 && wclk == nullptr) {
+                // Need to check wclk too
+                for (int z = 4 * i; z < 4 * (i + 1); z++) {
+                    for (int k = 0; k < 2; k++) {
+                        auto lut = get_tags(lts.cells[z << 4 | (BEL_6LUT + k)]);
+                        if (!lut)
+                            continue;
+                        if (!lut->lut.is_memory && !lut->lut.is_srl)
+                            continue;
+                        if (lut->lut.wclk != nullptr) {
+                            wclk = lut->lut.wclk;
+                            break;
+                        }
+                    }
+                }
+            }
+            NetInfo *clk = nullptr, *sr = nullptr, *ce = nullptr;
+            bool clkinv = false, srinv = false, islatch = false, ffsync = false;
+            for (int z = 4 * i; z < 4 * (i + 1); z++) {
+                for (int k = 0; k < 2; k++) {
+                    auto ff = get_tags(lts.cells[z << 4 | (BEL_FF + k)]);
+                    if (ff == nullptr)
+                        continue;
+                    if (ff->ff.is_latch && k == 1) {
+                        DBG();
+                        return false;
+                    }
+                    if (found_ff[0] || found_ff[1]) {
+                        if (ff->ff.clk != clk) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.sr != sr) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.ce != ce) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.is_clkinv != clkinv) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.is_srinv != srinv) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.is_latch != islatch) {
+                            DBG();
+                            return false;
+                        }
+                        if (ff->ff.ffsync != ffsync) {
+                            DBG();
+                            return false;
+                        }
+                    } else {
+                        clk = ff->ff.clk;
+                        if (i == 0 && wclk != nullptr && clk != wclk) {
+                            DBG();
+                            return false;
+                        }
+                        sr = ff->ff.sr;
+                        ce = ff->ff.ce;
+                        clkinv = ff->ff.is_clkinv;
+                        srinv = ff->ff.is_srinv;
+                        islatch = ff->ff.is_latch;
+                        ffsync = ff->ff.ffsync;
+                    }
+                    found_ff[k] = true;
+                }
+            }
+            lts.halfs[i].valid = true;
+        } else if (!lts.halfs[i].valid) {
+            DBG();
+            return false;
+        }
+    }
+    return true;
+}
+
+bool XilinxImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
+{
+    if (is_logic_tile(bel)) {
+        if (!tile_status.at(bel.tile).lts)
+            return true;
+        return xc7_logic_tile_valid(bel_tile_type(bel), *tile_status.at(bel.tile).lts);
+    } else if (is_bram_tile(bel)) {
+        const auto &bts = tile_status.at(bel.tile).bts;
+        if (!bts)
+            return true;
+        auto onehot = [&](CellInfo *a, CellInfo *b, CellInfo *c) {
+            return (((a != nullptr) ? 1 : 0) + ((b != nullptr) ? 1 : 0) + ((c != nullptr) ? 1 : 0)) <= 1;
+        };
+        // Only one type of BRAM cell at any given location
+        if (!onehot(bts->cells[BEL_RAMFIFO36], bts->cells[BEL_RAM36], bts->cells[BEL_FIFO36])) {
+            DBG();
+            return false;
+        }
+        if (!onehot(bts->cells[BEL_RAMFIFO18_L], bts->cells[BEL_RAM18_L], bts->cells[BEL_FIFO18_L])) {
+            DBG();
+            return false;
+        }
+        // 18-bit BRAMs cannot be used whilst 36-bit is used
+        if (bts->cells[BEL_RAMFIFO36] || bts->cells[BEL_RAM36] || bts->cells[BEL_FIFO36]) {
+            for (int i = 4; i < 12; i++)
+                if (bts->cells[i]) {
+                    DBG();
+                    return false;
+                }
+        }
+    }
+    return true;
+}
+
+void XilinxImpl::fixup_placement()
+{
+    log_info("Running post-placement legalisation...\n");
+    for (auto &ts : tile_status) {
+        if (!ts.lts)
+            continue;
+        auto &lt = *(ts.lts);
+        for (int z = 0; z < 8; z++) {
+            // Fixup LUT connectivity - applies whenever a LUT5 is used
+            CellInfo *lut5 = lt.cells[z << 4 | BEL_5LUT];
+            if (!lut5)
+                continue;
+            auto l5_tags = get_tags(lut5);
+            dict<IdString, std::vector<int>> lut5Inputs, lut6Inputs;
+            for (int i = 0; i < l5_tags->lut.input_count; i++)
+                if (l5_tags->lut.input_sigs[i])
+                    lut5Inputs[l5_tags->lut.input_sigs[i]->name].push_back(i);
+            CellInfo *lut6 = lt.cells[z << 4 | BEL_6LUT];
+            if (lut6) {
+                auto l6_tags = get_tags(lut6);
+                for (int i = 0; i < l6_tags->lut.input_count; i++)
+                    if (l6_tags->lut.input_sigs[i])
+                        lut6Inputs[l6_tags->lut.input_sigs[i]->name].push_back(i);
+            }
+            if (l5_tags->lut.is_memory || l5_tags->lut.is_srl) {
+                if (lut6) {
+                    if (!lut6->ports.count(id_A6)) {
+                        lut6->addInput(id_A6);
+                    }
+                    lut6->connectPort(id_A6, ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get());
+                }
+                continue;
+            }
+            std::set<IdString> uniqueInputs;
+            for (auto i5 : lut5Inputs)
+                uniqueInputs.insert(i5.first);
+            for (auto i6 : lut6Inputs)
+                uniqueInputs.insert(i6.first);
+            // Disconnect LUT inputs, and re-connect them to not overlap
+            IdString ports[6] = {id_A1, id_A2, id_A3, id_A4, id_A5, id_A6};
+            for (auto p : ports) {
+                lut5->disconnectPort(p);
+                lut5->attrs.erase(ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx)));
+                if (lut6) {
+                    lut6->attrs.erase(ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx)));
+                    lut6->disconnectPort(p);
+                }
+            }
+            int index = 0;
+            for (auto i : uniqueInputs) {
+                if (lut5Inputs.count(i)) {
+                    if (!lut5->ports.count(ports[index])) {
+                        lut5->ports[ports[index]].name = ports[index];
+                        lut5->ports[ports[index]].type = PORT_IN;
+                    }
+                    lut5->connectPort(ports[index], ctx->nets.at(i).get());
+                    lut5->attrs[ctx->idf("X_ORIG_PORT_%s", ports[index].c_str(ctx))] = std::string("");
+                    bool first = true;
+                    for (auto inp : lut5Inputs[i]) {
+                        lut5->attrs[ctx->idf("X_ORIG_PORT_%s", ports[index].c_str(ctx))].str +=
+                                (first ? "I" : " I") + std::to_string(inp);
+                        first = false;
+                    }
+                }
+                if (lut6 && lut6Inputs.count(i)) {
+                    if (!lut6->ports.count(ports[index])) {
+                        lut6->ports[ports[index]].name = ports[index];
+                        lut6->ports[ports[index]].type = PORT_IN;
+                    }
+                    lut6->connectPort(ports[index], ctx->nets.at(i).get());
+
+                    lut6->attrs[ctx->idf("X_ORIG_PORT_%s", ports[index].c_str(ctx))] = std::string("");
+                    bool first = true;
+                    for (auto inp : lut6Inputs[i]) {
+                        lut6->attrs[ctx->idf("X_ORIG_PORT_%s", ports[index].c_str(ctx))].str +=
+                                (first ? "I" : " I") + std::to_string(inp);
+                        first = false;
+                    }
+                }
+                ++index;
+            }
+            lut5->renamePort(id_O6, id_O5);
+            lut5->attrs.erase(id_X_ORIG_PORT_O6);
+            lut5->attrs[id_X_ORIG_PORT_O5] = std::string("O");
+
+            if (lut6) {
+                if (!lut6->ports.count(id_A6)) {
+                    lut6->addInput(id_A6);
+                }
+                lut6->connectPort(id_A6, ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get());
+            }
+        }
+    }
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_PS7_PS7) {
+            log_info("Tieing unused PS7 inputs to constants...\n");
+            for (IdString pname : ctx->getBelPins(ci->bel)) {
+                if (ci->ports.count(pname) && ci->ports.at(pname).net != nullptr &&
+                    ci->ports.at(pname).net->driver.cell != nullptr)
+                    continue;
+                if (ctx->getBelPinType(ci->bel, pname) != PORT_IN)
+                    continue;
+                std::string name = pname.str(ctx);
+                if (name.find("_PAD_") != std::string::npos)
+                    continue;
+                if (boost::starts_with(name, "TEST") || boost::starts_with(name, "DEBUGSELECT") ||
+                    boost::starts_with(name, "MIO") || boost::starts_with(name, "DDR"))
+                    continue;
+                bool constval = false;
+                ci->ports[pname].name = pname;
+                ci->ports[pname].type = PORT_IN;
+                if (ci->ports[pname].net != nullptr) {
+                    ci->disconnectPort(pname);
+                    ci->attrs.erase(ctx->idf("X_ORIG_PORT_", name.c_str()));
+                }
+                ci->connectPort(pname,
+                                ctx->nets.at(constval ? ctx->id("$PACKER_VCC_NET") : ctx->id("$PACKER_GND_NET")).get());
+            }
+        }
+    }
+}
+
+void XilinxImpl::fixup_routing()
+{
+    log_info("Running post-routing legalisation...\n");
+    /*
+     * Convert LUT permutation into correct physical connections (i.e. effectively eliminating the permutation pips),
+     * then specifying the permutation as a new physical-to-logical mapping using X_ORIG_PORT. This keeps RapidWright
+     * and Vivado happy, preserving the original logical netlist
+     */
+    dict<int, std::vector<int>> used_perm_pips; // tile -> [extra_data] for LUT perm pips
+
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        for (auto &wire : ni->wires) {
+            PipId pip = wire.second.pip;
+            if (pip == PipId())
+                continue;
+            auto &pd = chip_pip_info(ctx->chip_info, pip);
+            if (pd.flags != PIP_LUT_PERMUTATION)
+                continue;
+            const auto &extra_data = *reinterpret_cast<const XlnxPipExtraDataPOD *>(pd.extra_data.get());
+            used_perm_pips[pip.tile].push_back(extra_data.pip_config);
+        }
+    }
+
+    for (size_t ti = 0; ti < tile_status.size(); ti++) {
+        if (!used_perm_pips.count(int(ti)))
+            continue;
+        auto &ts = tile_status.at(ti);
+        if (!ts.lts)
+            continue;
+
+        auto &lt = *ts.lts;
+        for (int z = 0; z < 8; z++) {
+            CellInfo *lut5 = lt.cells[z << 4 | BEL_5LUT];
+            CellInfo *lut6 = lt.cells[z << 4 | BEL_6LUT];
+            if (lut5 == nullptr && lut6 == nullptr)
+                continue;
+            auto &pp = used_perm_pips.at(ti);
+            // from -> to
+            dict<IdString, std::vector<IdString>> new_connections;
+            IdString ports[6] = {id_A1, id_A2, id_A3, id_A4, id_A5, id_A6};
+            for (auto pip : pp) {
+                if (((pip >> 8) & 0xF) != z)
+                    continue;
+                new_connections[ports[(pip >> 4) & 0xF]].push_back(ports[pip & 0xF]);
+            }
+            dict<IdString, NetInfo *> orig_nets;
+            dict<IdString, std::string> orig_ports_l6, orig_ports_l5;
+            for (int i = 0; i < 6; i++) {
+                NetInfo *l6net = lut6 ? lut6->getPort(ports[i]) : nullptr;
+                NetInfo *l5net = lut5 ? lut5->getPort(ports[i]) : nullptr;
+                orig_nets[ports[i]] = (l6net ? l6net : l5net);
+                if (lut6)
+                    orig_ports_l6[ports[i]] =
+                            str_or_default(lut6->attrs, ctx->idf("X_ORIG_PORT_%s", ports[i].c_str(ctx)));
+                if (lut5)
+                    orig_ports_l5[ports[i]] =
+                            str_or_default(lut5->attrs, ctx->idf("X_ORIG_PORT_%s", ports[i].c_str(ctx)));
+            }
+            for (auto &nc : new_connections) {
+                if (lut6)
+                    lut6->disconnectPort(nc.first);
+                if (lut5)
+                    lut5->disconnectPort(nc.first);
+                for (auto &dst : nc.second) {
+                    if (lut6)
+                        lut6->disconnectPort(dst);
+                    if (lut5)
+                        lut5->disconnectPort(dst);
+                }
+            }
+            for (int i = 0; i < 6; i++) {
+                if (lut6)
+                    lut6->attrs.erase(ctx->idf("X_ORIG_PORT_%s", ports[i].c_str(ctx)));
+                if (lut5)
+                    lut5->attrs.erase(ctx->idf("X_ORIG_PORT_%s", ports[i].c_str(ctx)));
+            }
+            for (int i = 0; i < 6; i++) {
+                auto p = ports[i];
+                if (!new_connections.count(p) || new_connections.at(p).empty())
+                    continue;
+                if (lut6) {
+                    if (!lut6->ports.count(p)) {
+                        lut6->addInput(p);
+                    }
+                    lut6->connectPort(p, orig_nets[new_connections.at(p).front()]);
+                    lut6->attrs[ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx))] = std::string("");
+                    auto &orig_attr = lut6->attrs[ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx))].str;
+                    bool first = true;
+                    for (auto &nc : new_connections.at(p)) {
+                        orig_attr += orig_ports_l6[nc] + (first ? "" : " ");
+                        first = false;
+                    }
+                    if (orig_attr.empty())
+                        lut6->attrs.erase(ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx)));
+                }
+                if (lut5) {
+                    if (!lut5->ports.count(p)) {
+                        lut5->addInput(p);
+                    }
+                    lut5->connectPort(p, orig_nets[new_connections.at(p).front()]);
+                    lut5->attrs[ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx))] = std::string("");
+                    auto &orig_attr = lut5->attrs[ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx))].str;
+                    bool first = true;
+                    for (auto &nc : new_connections.at(p)) {
+                        orig_attr += orig_ports_l5[nc] + (first ? "" : " ");
+                        first = false;
+                    }
+                    if (orig_attr.empty())
+                        lut5->attrs.erase(ctx->idf("X_ORIG_PORT_%s", p.c_str(ctx)));
+                }
+            }
+        }
+    }
+
+    /*
+     * Legalise route through OSERDESE3s
+     */
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_OSERDESE3) {
+            if (ci->getPort(id_T_OUT) != nullptr)
+                continue;
+            ci->params[id_OSERDES_T_BYPASS] = std::string("TRUE");
+        }
+    }
+}
+
+NEXTPNR_NAMESPACE_END

From e2a887ef0d9e82ad598488d0381c64a593832c8c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Nov 2023 09:09:59 +0100
Subject: [PATCH 518/712] himbaechel: Switch default back to router1 for now

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/arch.cc                                  | 2 +-
 himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 44b79b620a..1270934e02 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -318,7 +318,7 @@ const std::string Arch::defaultPlacer = "heap";
 
 const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
 
-const std::string Arch::defaultRouter = "router2";
+const std::string Arch::defaultRouter = "router1";
 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
 
 void Arch::set_fast_pip_delays(bool fast_mode)
diff --git a/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
index 96f61b7a77..c51bffccaa 100755
--- a/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
+++ b/himbaechel/uarch/xilinx/examples/arty-a35/blinky.sh
@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
 set -ex
 yosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top top; write_json blinky.json" blinky.v
-nextpnr-himbaechel --device xc7a35tcsg324-1 -o xdc=arty.xdc --json blinky.json -o fasm=blinky.fasm
+nextpnr-himbaechel --device xc7a35tcsg324-1 -o xdc=arty.xdc --json blinky.json -o fasm=blinky.fasm --router router2
 ../bitgen_xray.sh xc7a35tcsg324-1 blinky.fasm blinky.bit

From 55635cf2cda7af3a301da33293cc0094e7d540a6 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 17 Nov 2023 09:14:19 +0100
Subject: [PATCH 519/712] Update README

Signed-off-by: gatecat <gatecat@ds0.me>
---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index ca0ef1e50b..ee6fa81980 100644
--- a/README.md
+++ b/README.md
@@ -37,6 +37,7 @@ of the selected architecture:
 - CMake 3.3 or later
 - Modern C++14 compiler (`clang-format` required for development)
 - Python 3.5 or later, including development libraries (`python3-dev` for Ubuntu)
+  - Python 3.9 or later is required for `nextpnr-himbaechel`
   - on Windows make sure to install same version as supported by [vcpkg](https://github.com/Microsoft/vcpkg/blob/master/ports/python3/CONTROL)
 - Boost libraries (`libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-iostreams-dev libboost-dev` or `libboost-all-dev` for Ubuntu)
 - Eigen3 (`libeigen3-dev` for Ubuntu) is required to build the analytic placer

From 6683fd4ada386e56c24585a428a6138a9eb2b10a Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 22 Nov 2023 16:30:49 +0100
Subject: [PATCH 520/712] himbaechel: Fix when more then 32k unique node shapes

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/himbaechel_dbgen/chip.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 26741a3162..4af1c98e34 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -706,6 +706,12 @@ def set_speed_grades(self, speed_grades: list):
         self.timing.set_speed_grades(speed_grades)
         return self.timing
     def add_node(self, wires: list[NodeWire], timing_class=""):
+        # encode a 0..65535 unsigned value into -32768..32767 signed value so struct.pack doesn't complain
+        # (we use the same field as signed and unsigned in different modes)
+        def _twos(x):
+            if x & 0x8000:
+                x = x - 0x10000
+            return x
         # add a node - joining between multiple tile wires into a single connection (from nextpnr's point of view)
         # all the tile wires must exist, and the tile types must be set, first
         x0 = wires[0].x
@@ -739,7 +745,7 @@ def add_node(self, wires: list[NodeWire], timing_class=""):
                 # so we re-use the structure to store the index of the node shape, instead
                 assert inst.shape.wire_to_node[3*wire_idx+0] == MODE_TILE_WIRE, "attempting to add wire to multiple nodes!"
                 inst.shape.wire_to_node[3*wire_idx+0] = MODE_IS_ROOT
-                inst.shape.wire_to_node[3*wire_idx+1] = (shape_idx & 0xFFFF)
+                inst.shape.wire_to_node[3*wire_idx+1] = _twos(shape_idx & 0xFFFF)
                 inst.shape.wire_to_node[3*wire_idx+2] = ((shape_idx >> 16) & 0xFFFF)
             else:
                 # back-reference to the root of the node

From 7814f44883615ff33a6e9b4951908f8212d38ba0 Mon Sep 17 00:00:00 2001
From: Balint Cristian <cristian.balint@gmail.com>
Date: Sat, 18 Nov 2023 00:27:54 +0200
Subject: [PATCH 521/712] Fix abstract class implementation for
 fpga_interchange

Signed-off-by: Balint Cristian <cristian.balint@gmail.com>
---
 fpga_interchange/arch.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index caabe6a3ae..e125d86c53 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -500,6 +500,8 @@ struct Arch : ArchAPI<ArchRanges>
 
     WireId getConflictingWireWire(WireId wire) const final { return wire; }
 
+    IdString getWireConstantValue(WireId wire) const final { return {}; }
+
     NetInfo *getConflictingWireNet(WireId wire) const final
     {
         NPNR_ASSERT(wire != WireId());

From de3d5be8f00bc67cc48ee969b2dc242549f3740b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 22 Nov 2023 16:13:30 +0100
Subject: [PATCH 522/712] python: Remove deprecated use of Py_SetProgramName

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/pybindings.cc | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index cea9a8be67..137c3e36ba 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -300,22 +300,14 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
     arch_wrap_python(m);
 }
 
-#ifdef MAIN_EXECUTABLE
-static wchar_t *program;
-#endif
-
 void (*python_sighandler)(int) = nullptr;
 
 void init_python(const char *executable)
 {
 #ifdef MAIN_EXECUTABLE
-    program = Py_DecodeLocale(executable, NULL);
-    if (program == NULL) {
-        fprintf(stderr, "Fatal error: cannot decode executable filename\n");
-        exit(1);
-    }
-    Py_SetProgramName(program);
-    py::initialize_interpreter();
+    static const char* python_argv[1];
+    python_argv[0] = executable;
+    py::initialize_interpreter(true, 1, python_argv);
     py::module::import(TOSTRING(MODULE_NAME));
     PyRun_SimpleString("from " TOSTRING(MODULE_NAME) " import *");
     python_sighandler = signal(SIGINT, SIG_DFL);
@@ -326,7 +318,6 @@ void deinit_python()
 {
 #ifdef MAIN_EXECUTABLE
     py::finalize_interpreter();
-    PyMem_RawFree(program);
 #endif
 }
 

From 0b8a93eed5e278dc1901d02bd584d88b5a51002e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 22 Nov 2023 19:50:17 +0100
Subject: [PATCH 523/712] fix compile warning

---
 gui/line_editor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gui/line_editor.cc b/gui/line_editor.cc
index ee6a2f9c32..dd7b51afa3 100644
--- a/gui/line_editor.cc
+++ b/gui/line_editor.cc
@@ -118,7 +118,7 @@ void LineEditor::clearHistory()
 void LineEditor::autocomplete()
 {
     QString line = text();
-    const std::list<std::string> &suggestions = pyinterpreter_suggest(line.toStdString());
+    const std::list<std::string> suggestions = pyinterpreter_suggest(line.toStdString());
     if (suggestions.size() == 1) {
         line = suggestions.back().c_str();
     } else {

From 1ec8e411d7b81316adf5a1297463ad5b9badb305 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 22 Nov 2023 19:51:28 +0100
Subject: [PATCH 524/712] set render bound box, so grid is displayed

---
 gui/fpgaviewwidget.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index 692eb27beb..c06482c9ab 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -572,6 +572,10 @@ void FPGAViewWidget::renderLines(void)
         for (float i = 0.0f; i < 1.0f * ctx_->getGridDimY() + 1; i += 1.0f) {
             PolyLine(0.0f, i, 1.0f * ctx_->getGridDimX(), i).build(rendererData_->gfxGrid);
         }
+        rendererData_->bbGlobal.setX0(-1.0f);
+        rendererData_->bbGlobal.setY0(-1.0f);
+        rendererData_->bbGlobal.setX1(1.0f * (ctx_->getGridDimX()+1));
+        rendererData_->bbGlobal.setY1(1.0f * (ctx_->getGridDimY()+1));
         rendererData_->gfxGrid.last_render++;
     }
     if (highlightedOrSelectedChanged) {

From ec60542ffda95bb040ab08792a82ae5a14be344e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 23 Nov 2023 08:59:23 +0100
Subject: [PATCH 525/712] create wiremap for himbaechel arch

---
 gui/designwidget.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index fb9086ddce..bc101d805a 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -328,6 +328,13 @@ void DesignWidget::newContext(Context *ctx)
                 WireInfo wi = ctx->wire_info(wire);
                 wireMap[std::pair<int, int>(wi.x, wi.y)].push_back(wire);
             }
+#endif
+#ifdef ARCH_HIMBAECHEL
+            for (const auto &wire : ctx->getWires()) {
+                Loc loc;
+                tile_xy(ctx->chip_info, wire.tile, loc.x, loc.y);
+                wireMap[std::pair<int, int>(loc.x, loc.y)].push_back(wire);
+            }
 #endif
             auto wireGetter = [](Context *ctx, WireId id) { return ctx->getWireName(id); };
             getTreeByElementType(ElementType::WIRE)

From e3f4578b3b331fb1b971b07376eef2b058a3e6d9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 23 Nov 2023 09:02:56 +0100
Subject: [PATCH 526/712] CRLF -> LF eol

---
 gui/basewindow.cc                  | 1094 +++++++-------
 gui/basewindow.h                   |  284 ++--
 gui/designwidget.cc                | 2144 ++++++++++++++--------------
 gui/designwidget.h                 |  276 ++--
 gui/ecp5/mainwindow.cc             |  332 ++---
 gui/ecp5/mainwindow.h              |  110 +-
 gui/fpga_interchange/mainwindow.cc |  100 +-
 gui/fpga_interchange/mainwindow.h  |   92 +-
 gui/generic/mainwindow.cc          |  104 +-
 gui/generic/mainwindow.h           |   90 +-
 gui/gowin/mainwindow.cc            |  206 +--
 gui/gowin/mainwindow.h             |  114 +-
 gui/ice40/mainwindow.cc            |  364 ++---
 gui/ice40/mainwindow.h             |  118 +-
 gui/pythontab.cc                   |  238 +--
 gui/pythontab.h                    |  128 +-
 16 files changed, 2897 insertions(+), 2897 deletions(-)

diff --git a/gui/basewindow.cc b/gui/basewindow.cc
index 4ea88a138a..b42b3c6237 100644
--- a/gui/basewindow.cc
+++ b/gui/basewindow.cc
@@ -1,547 +1,547 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *  Copyright (C) 2018  Serge Bazanski <q3k@q3k.org>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include <QAction>
-#include <QCoreApplication>
-#include <QFileDialog>
-#include <QGridLayout>
-#include <QIcon>
-#include <QImageWriter>
-#include <QInputDialog>
-#include <QMessageBox>
-#include <QSplitter>
-#include <fstream>
-#include "designwidget.h"
-#include "fpgaviewwidget.h"
-#include "json_frontend.h"
-#include "jsonwrite.h"
-#include "log.h"
-#include "mainwindow.h"
-#include "pythontab.h"
-#include "version.h"
-
-static void initBasenameResource() { Q_INIT_RESOURCE(base); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-BaseMainWindow::BaseMainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : QMainWindow(parent), handler(handler), ctx(std::move(context)), timing_driven(false)
-{
-    initBasenameResource();
-    qRegisterMetaType<std::string>();
-
-    log_streams.clear();
-
-    setObjectName("BaseMainWindow");
-    resize(1024, 768);
-
-    task = new TaskManager();
-
-    // Create and deploy widgets on main screen
-    QWidget *centralWidget = new QWidget(this);
-    QGridLayout *gridLayout = new QGridLayout(centralWidget);
-    gridLayout->setSpacing(6);
-    gridLayout->setContentsMargins(11, 11, 11, 11);
-
-    QSplitter *splitter_h = new QSplitter(Qt::Horizontal, centralWidget);
-    QSplitter *splitter_v = new QSplitter(Qt::Vertical, splitter_h);
-    splitter_h->addWidget(splitter_v);
-
-    gridLayout->addWidget(splitter_h, 0, 0, 1, 1);
-
-    setCentralWidget(centralWidget);
-
-    designview = new DesignWidget();
-    designview->setMinimumWidth(300);
-    splitter_h->addWidget(designview);
-
-    tabWidget = new QTabWidget();
-
-    console = new PythonTab();
-    tabWidget->addTab(console, "Console");
-
-    centralTabWidget = new QTabWidget();
-    centralTabWidget->setTabsClosable(true);
-
-    fpgaView = new FPGAViewWidget();
-    centralTabWidget->addTab(fpgaView, "Device");
-    centralTabWidget->tabBar()->setTabButton(0, QTabBar::RightSide, 0);
-    centralTabWidget->tabBar()->setTabButton(0, QTabBar::LeftSide, 0);
-
-    splitter_v->addWidget(centralTabWidget);
-    splitter_v->addWidget(tabWidget);
-
-    // Connect Worker
-    connect(task, &TaskManager::log, this, &BaseMainWindow::writeInfo);
-    connect(task, &TaskManager::pack_finished, this, &BaseMainWindow::pack_finished);
-    connect(task, &TaskManager::place_finished, this, &BaseMainWindow::place_finished);
-    connect(task, &TaskManager::route_finished, this, &BaseMainWindow::route_finished);
-    connect(task, &TaskManager::taskCanceled, this, &BaseMainWindow::taskCanceled);
-    connect(task, &TaskManager::taskStarted, this, &BaseMainWindow::taskStarted);
-    connect(task, &TaskManager::taskPaused, this, &BaseMainWindow::taskPaused);
-
-    // Events for context change
-    connect(this, &BaseMainWindow::contextChanged, task, &TaskManager::contextChanged);
-    connect(this, &BaseMainWindow::contextChanged, console, &PythonTab::newContext);
-    connect(this, &BaseMainWindow::contextChanged, fpgaView, &FPGAViewWidget::newContext);
-    connect(this, &BaseMainWindow::contextChanged, designview, &DesignWidget::newContext);
-
-    // Catch close tab events
-    connect(centralTabWidget, &QTabWidget::tabCloseRequested, this, &BaseMainWindow::closeTab);
-
-    // Propagate events from design view to device view
-    connect(designview, &DesignWidget::selected, fpgaView, &FPGAViewWidget::onSelectedArchItem);
-    connect(designview, &DesignWidget::zoomSelected, fpgaView, &FPGAViewWidget::zoomSelected);
-    connect(designview, &DesignWidget::highlight, fpgaView, &FPGAViewWidget::onHighlightGroupChanged);
-    connect(designview, &DesignWidget::hover, fpgaView, &FPGAViewWidget::onHoverItemChanged);
-
-    // Click event on device view
-    connect(fpgaView, &FPGAViewWidget::clickedBel, designview, &DesignWidget::onClickedBel);
-    connect(fpgaView, &FPGAViewWidget::clickedWire, designview, &DesignWidget::onClickedWire);
-    connect(fpgaView, &FPGAViewWidget::clickedPip, designview, &DesignWidget::onClickedPip);
-
-    // Update tree event
-    connect(this, &BaseMainWindow::updateTreeView, designview, &DesignWidget::updateTree);
-
-    createMenusAndBars();
-}
-
-BaseMainWindow::~BaseMainWindow() { delete task; }
-
-void BaseMainWindow::closeTab(int index) { delete centralTabWidget->widget(index); }
-
-void BaseMainWindow::writeInfo(std::string text) { console->info(text); }
-
-void BaseMainWindow::about()
-{
-    QString msg;
-    QTextStream out(&msg);
-    out << "nextpnr-" << NPNR_STRINGIFY_MACRO(ARCHNAME) << "\n";
-    out << "Version " << GIT_DESCRIBE_STR;
-    QMessageBox::information(this, "About nextpnr", msg);
-}
-
-void BaseMainWindow::createMenusAndBars()
-{
-    // File menu / project toolbar actions
-    QAction *actionExit = new QAction("Exit", this);
-    actionExit->setIcon(QIcon(":/icons/resources/exit.png"));
-    actionExit->setShortcuts(QKeySequence::Quit);
-    actionExit->setStatusTip("Exit the application");
-    connect(actionExit, &QAction::triggered, this, &BaseMainWindow::close);
-
-    // Help menu actions
-    QAction *actionAbout = new QAction("About", this);
-    connect(actionAbout, &QAction::triggered, this, &BaseMainWindow::about);
-
-    // Gile menu options
-    actionNew = new QAction("New", this);
-    actionNew->setIcon(QIcon(":/icons/resources/new.png"));
-    actionNew->setShortcuts(QKeySequence::New);
-    actionNew->setStatusTip("New project");
-    connect(actionNew, &QAction::triggered, this, &BaseMainWindow::new_proj);
-
-    actionLoadJSON = new QAction("Open JSON", this);
-    actionLoadJSON->setIcon(QIcon(":/icons/resources/open_json.png"));
-    actionLoadJSON->setStatusTip("Open an existing JSON file");
-    actionLoadJSON->setEnabled(true);
-    connect(actionLoadJSON, &QAction::triggered, this, &BaseMainWindow::open_json);
-
-    actionSaveJSON = new QAction("Save JSON", this);
-    actionSaveJSON->setIcon(QIcon(":/icons/resources/save_json.png"));
-    actionSaveJSON->setStatusTip("Write to JSON file");
-    actionSaveJSON->setEnabled(true);
-    connect(actionSaveJSON, &QAction::triggered, this, &BaseMainWindow::save_json);
-
-    // Design menu options
-    actionPack = new QAction("Pack", this);
-    actionPack->setIcon(QIcon(":/icons/resources/pack.png"));
-    actionPack->setStatusTip("Pack current design");
-    actionPack->setEnabled(false);
-    connect(actionPack, &QAction::triggered, task, &TaskManager::pack);
-
-    actionPlace = new QAction("Place", this);
-    actionPlace->setIcon(QIcon(":/icons/resources/place.png"));
-    actionPlace->setStatusTip("Place current design");
-    actionPlace->setEnabled(false);
-    connect(actionPlace, &QAction::triggered, this, &BaseMainWindow::place);
-
-    actionRoute = new QAction("Route", this);
-    actionRoute->setIcon(QIcon(":/icons/resources/route.png"));
-    actionRoute->setStatusTip("Route current design");
-    actionRoute->setEnabled(false);
-    connect(actionRoute, &QAction::triggered, task, &TaskManager::route);
-
-    actionExecutePy = new QAction("Execute Python", this);
-    actionExecutePy->setIcon(QIcon(":/icons/resources/py.png"));
-    actionExecutePy->setStatusTip("Execute Python script");
-    actionExecutePy->setEnabled(true);
-    connect(actionExecutePy, &QAction::triggered, this, &BaseMainWindow::execute_python);
-
-    // Worker control toolbar actions
-    actionPlay = new QAction("Play", this);
-    actionPlay->setIcon(QIcon(":/icons/resources/control_play.png"));
-    actionPlay->setStatusTip("Continue running task");
-    actionPlay->setEnabled(false);
-    connect(actionPlay, &QAction::triggered, task, &TaskManager::continue_thread);
-
-    actionPause = new QAction("Pause", this);
-    actionPause->setIcon(QIcon(":/icons/resources/control_pause.png"));
-    actionPause->setStatusTip("Pause running task");
-    actionPause->setEnabled(false);
-    connect(actionPause, &QAction::triggered, task, &TaskManager::pause_thread);
-
-    actionStop = new QAction("Stop", this);
-    actionStop->setIcon(QIcon(":/icons/resources/control_stop.png"));
-    actionStop->setStatusTip("Stop running task");
-    actionStop->setEnabled(false);
-    connect(actionStop, &QAction::triggered, task, &TaskManager::terminate_thread);
-
-    // Device view control toolbar actions
-    QAction *actionZoomIn = new QAction("Zoom In", this);
-    actionZoomIn->setIcon(QIcon(":/icons/resources/zoom_in.png"));
-    connect(actionZoomIn, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomIn);
-
-    QAction *actionZoomOut = new QAction("Zoom Out", this);
-    actionZoomOut->setIcon(QIcon(":/icons/resources/zoom_out.png"));
-    connect(actionZoomOut, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomOut);
-
-    QAction *actionZoomSelected = new QAction("Zoom Selected", this);
-    actionZoomSelected->setIcon(QIcon(":/icons/resources/shape_handles.png"));
-    connect(actionZoomSelected, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomSelected);
-
-    QAction *actionZoomOutbound = new QAction("Zoom Outbound", this);
-    actionZoomOutbound->setIcon(QIcon(":/icons/resources/shape_square.png"));
-    connect(actionZoomOutbound, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomOutbound);
-
-    actionDisplayBel = new QAction("Enable/Disable Bels", this);
-    actionDisplayBel->setIcon(QIcon(":/icons/resources/bel.png"));
-    actionDisplayBel->setCheckable(true);
-    actionDisplayBel->setChecked(true);
-    connect(actionDisplayBel, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
-
-    actionDisplayWire = new QAction("Enable/Disable Wires", this);
-    actionDisplayWire->setIcon(QIcon(":/icons/resources/wire.png"));
-    actionDisplayWire->setCheckable(true);
-    actionDisplayWire->setChecked(true);
-    connect(actionDisplayWire, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
-
-    actionDisplayPip = new QAction("Enable/Disable Pips", this);
-    actionDisplayPip->setIcon(QIcon(":/icons/resources/pip.png"));
-    actionDisplayPip->setCheckable(true);
-#ifdef ARCH_ECP5
-    actionDisplayPip->setChecked(false);
-#else
-    actionDisplayPip->setChecked(true);
-#endif
-    connect(actionDisplayPip, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
-
-    actionDisplayGroups = new QAction("Enable/Disable Groups", this);
-    actionDisplayGroups->setIcon(QIcon(":/icons/resources/group.png"));
-    actionDisplayGroups->setCheckable(true);
-    actionDisplayGroups->setChecked(true);
-    connect(actionDisplayGroups, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
-
-    actionScreenshot = new QAction("Screenshot", this);
-    actionScreenshot->setIcon(QIcon(":/icons/resources/camera.png"));
-    actionScreenshot->setStatusTip("Taking a screenshot");
-    connect(actionScreenshot, &QAction::triggered, this, &BaseMainWindow::screenshot);
-
-    actionMovie = new QAction("Recording", this);
-    actionMovie->setIcon(QIcon(":/icons/resources/film.png"));
-    actionMovie->setStatusTip("Saving a movie");
-    actionMovie->setCheckable(true);
-    actionMovie->setChecked(false);
-    connect(actionMovie, &QAction::triggered, this, &BaseMainWindow::saveMovie);
-
-    actionSaveSVG = new QAction("Save SVG", this);
-    actionSaveSVG->setIcon(QIcon(":/icons/resources/save_svg.png"));
-    actionSaveSVG->setStatusTip("Saving a SVG");
-    connect(actionSaveSVG, &QAction::triggered, this, &BaseMainWindow::saveSVG);
-
-    // set initial state
-    fpgaView->enableDisableDecals(actionDisplayBel->isChecked(), actionDisplayWire->isChecked(),
-                                  actionDisplayPip->isChecked(), actionDisplayGroups->isChecked());
-
-    // Add main menu
-    menuBar = new QMenuBar();
-    menuBar->setGeometry(QRect(0, 0, 1024, 27));
-    setMenuBar(menuBar);
-    QMenu *menuFile = new QMenu("&File", menuBar);
-    QMenu *menuHelp = new QMenu("&Help", menuBar);
-    menuDesign = new QMenu("&Design", menuBar);
-    menuBar->addAction(menuFile->menuAction());
-    menuBar->addAction(menuDesign->menuAction());
-    menuBar->addAction(menuHelp->menuAction());
-
-    // Add File menu actions
-    menuFile->addAction(actionNew);
-    menuFile->addAction(actionLoadJSON);
-    menuFile->addAction(actionSaveJSON);
-    menuFile->addSeparator();
-    menuFile->addAction(actionExit);
-
-    // Add Design menu actions
-    menuDesign->addAction(actionPack);
-    menuDesign->addAction(actionPlace);
-    menuDesign->addAction(actionRoute);
-    menuDesign->addSeparator();
-    menuDesign->addAction(actionExecutePy);
-
-    // Add Help menu actions
-    menuHelp->addAction(actionAbout);
-
-    // Main action bar
-    mainActionBar = new QToolBar("Main");
-    addToolBar(Qt::TopToolBarArea, mainActionBar);
-    mainActionBar->addAction(actionNew);
-    mainActionBar->addAction(actionLoadJSON);
-    mainActionBar->addAction(actionSaveJSON);
-    mainActionBar->addSeparator();
-    mainActionBar->addAction(actionPack);
-    mainActionBar->addAction(actionPlace);
-    mainActionBar->addAction(actionRoute);
-    mainActionBar->addAction(actionExecutePy);
-
-    // Add worker control toolbar
-    QToolBar *workerControlToolBar = new QToolBar("Worker");
-    addToolBar(Qt::TopToolBarArea, workerControlToolBar);
-    workerControlToolBar->addAction(actionPlay);
-    workerControlToolBar->addAction(actionPause);
-    workerControlToolBar->addAction(actionStop);
-
-    // Add device view control toolbar
-    QToolBar *deviceViewToolBar = new QToolBar("Device");
-    addToolBar(Qt::TopToolBarArea, deviceViewToolBar);
-    deviceViewToolBar->addAction(actionZoomIn);
-    deviceViewToolBar->addAction(actionZoomOut);
-    deviceViewToolBar->addAction(actionZoomSelected);
-    deviceViewToolBar->addAction(actionZoomOutbound);
-    deviceViewToolBar->addSeparator();
-    deviceViewToolBar->addAction(actionDisplayBel);
-    deviceViewToolBar->addAction(actionDisplayWire);
-    deviceViewToolBar->addAction(actionDisplayPip);
-    deviceViewToolBar->addAction(actionDisplayGroups);
-    deviceViewToolBar->addSeparator();
-    deviceViewToolBar->addAction(actionScreenshot);
-    deviceViewToolBar->addAction(actionMovie);
-    deviceViewToolBar->addAction(actionSaveSVG);
-
-    // Add status bar with progress bar
-    statusBar = new QStatusBar();
-    progressBar = new QProgressBar(statusBar);
-    progressBar->setAlignment(Qt::AlignRight);
-    progressBar->setMaximumSize(180, 19);
-    statusBar->addPermanentWidget(progressBar);
-    progressBar->setValue(0);
-    progressBar->setEnabled(false);
-    setStatusBar(statusBar);
-}
-
-void BaseMainWindow::enableDisableDecals()
-{
-    fpgaView->enableDisableDecals(actionDisplayBel->isChecked(), actionDisplayWire->isChecked(),
-                                  actionDisplayPip->isChecked(), actionDisplayGroups->isChecked());
-    ctx->refreshUi();
-}
-
-void BaseMainWindow::open_json()
-{
-    QString fileName = QFileDialog::getOpenFileName(this, QString("Open JSON"), QString(), QString("*.json"));
-    if (!fileName.isEmpty()) {
-        disableActions();
-        if (ctx->settings.find(ctx->id("synth")) == ctx->settings.end()) {
-            ArchArgs chipArgs = ctx->getArchArgs();
-            ctx = std::unique_ptr<Context>(new Context(chipArgs));
-            Q_EMIT contextChanged(ctx.get());
-        }
-        handler->load_json(ctx.get(), fileName.toStdString());
-        Q_EMIT updateTreeView();
-        log("Loading design successful.\n");
-        updateActions();
-    }
-}
-
-void BaseMainWindow::save_json()
-{
-    QString fileName = QFileDialog::getSaveFileName(this, QString("Save JSON"), QString(), QString("*.json"));
-    if (!fileName.isEmpty()) {
-        std::string fn = fileName.toStdString();
-        std::ofstream f(fn);
-        if (write_json_file(f, fn, ctx.get()))
-            log("Saving JSON successful.\n");
-        else
-            log("Saving JSON failed.\n");
-    }
-}
-
-void BaseMainWindow::screenshot()
-{
-    QString fileName = QFileDialog::getSaveFileName(this, QString("Save screenshot"), QString(), QString("*.png"));
-    if (!fileName.isEmpty()) {
-        QImage image = fpgaView->grabFramebuffer();
-        if (!fileName.endsWith(".png"))
-            fileName += ".png";
-        QImageWriter imageWriter(fileName, "png");
-        if (imageWriter.write(image))
-            log("Saving screenshot successful.\n");
-        else
-            log("Saving screenshot failed.\n");
-    }
-}
-
-void BaseMainWindow::saveMovie()
-{
-    if (actionMovie->isChecked()) {
-        QString dir = QFileDialog::getExistingDirectory(this, tr("Select Movie Directory"), QDir::currentPath(),
-                                                        QFileDialog::ShowDirsOnly | QFileDialog::DontResolveSymlinks);
-        if (!dir.isEmpty()) {
-            bool ok;
-            int frames =
-                    QInputDialog::getInt(this, "Recording", tr("Frames to skip (1 frame = 50ms):"), 5, 0, 1000, 1, &ok);
-            if (ok) {
-                QMessageBox::StandardButton reply =
-                        QMessageBox::question(this, "Recording", "Skip identical frames ?",
-                                              QMessageBox::Yes | QMessageBox::No, QMessageBox::Yes);
-                fpgaView->movieStart(dir, frames, (reply == QMessageBox::Yes));
-            } else
-                actionMovie->setChecked(false);
-        } else
-            actionMovie->setChecked(false);
-    } else {
-        fpgaView->movieStop();
-    }
-}
-
-void BaseMainWindow::saveSVG()
-{
-    QString fileName = QFileDialog::getSaveFileName(this, QString("Save SVG"), QString(), QString("*.svg"));
-    if (!fileName.isEmpty()) {
-        if (!fileName.endsWith(".svg"))
-            fileName += ".svg";
-        bool ok;
-        QString options =
-                QInputDialog::getText(this, "Save SVG", tr("Save options:"), QLineEdit::Normal, "scale=500", &ok);
-        if (ok) {
-            try {
-                ctx->writeSVG(fileName.toStdString(), options.toStdString());
-                log("Saving SVG successful.\n");
-            } catch (const log_execution_error_exception &ex) {
-                log("Saving SVG failed.\n");
-            }
-        }
-    }
-}
-
-void BaseMainWindow::pack_finished(bool status)
-{
-    disableActions();
-    if (status) {
-        log("Packing design successful.\n");
-        Q_EMIT updateTreeView();
-        updateActions();
-    } else {
-        log("Packing design failed.\n");
-    }
-}
-
-void BaseMainWindow::place_finished(bool status)
-{
-    disableActions();
-    if (status) {
-        log("Placing design successful.\n");
-        Q_EMIT updateTreeView();
-        updateActions();
-    } else {
-        log("Placing design failed.\n");
-    }
-}
-void BaseMainWindow::route_finished(bool status)
-{
-    disableActions();
-    if (status) {
-        log("Routing design successful.\n");
-        Q_EMIT updateTreeView();
-        updateActions();
-    } else
-        log("Routing design failed.\n");
-}
-
-void BaseMainWindow::taskCanceled()
-{
-    log("CANCELED\n");
-    disableActions();
-}
-
-void BaseMainWindow::taskStarted()
-{
-    disableActions();
-    actionPause->setEnabled(true);
-    actionStop->setEnabled(true);
-}
-
-void BaseMainWindow::taskPaused()
-{
-    disableActions();
-    actionPlay->setEnabled(true);
-    actionStop->setEnabled(true);
-}
-
-void BaseMainWindow::place() { Q_EMIT task->place(timing_driven); }
-
-void BaseMainWindow::disableActions()
-{
-    actionLoadJSON->setEnabled(true);
-    actionPack->setEnabled(false);
-    actionPlace->setEnabled(false);
-    actionRoute->setEnabled(false);
-
-    actionExecutePy->setEnabled(true);
-
-    actionPlay->setEnabled(false);
-    actionPause->setEnabled(false);
-    actionStop->setEnabled(false);
-
-    onDisableActions();
-}
-
-void BaseMainWindow::updateActions()
-{
-    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
-        actionPack->setEnabled(true);
-    else if (ctx->settings.find(ctx->id("place")) == ctx->settings.end()) {
-        actionPlace->setEnabled(true);
-    } else if (ctx->settings.find(ctx->id("route")) == ctx->settings.end())
-        actionRoute->setEnabled(true);
-
-    onUpdateActions();
-}
-
-void BaseMainWindow::execute_python()
-{
-    QString fileName = QFileDialog::getOpenFileName(this, QString("Execute Python"), QString(), QString("*.py"));
-    if (!fileName.isEmpty()) {
-        console->execute_python(fileName.toStdString());
-    }
-}
-
-void BaseMainWindow::notifyChangeContext() { Q_EMIT contextChanged(ctx.get()); }
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *  Copyright (C) 2018  Serge Bazanski <q3k@q3k.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <QAction>
+#include <QCoreApplication>
+#include <QFileDialog>
+#include <QGridLayout>
+#include <QIcon>
+#include <QImageWriter>
+#include <QInputDialog>
+#include <QMessageBox>
+#include <QSplitter>
+#include <fstream>
+#include "designwidget.h"
+#include "fpgaviewwidget.h"
+#include "json_frontend.h"
+#include "jsonwrite.h"
+#include "log.h"
+#include "mainwindow.h"
+#include "pythontab.h"
+#include "version.h"
+
+static void initBasenameResource() { Q_INIT_RESOURCE(base); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+BaseMainWindow::BaseMainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : QMainWindow(parent), handler(handler), ctx(std::move(context)), timing_driven(false)
+{
+    initBasenameResource();
+    qRegisterMetaType<std::string>();
+
+    log_streams.clear();
+
+    setObjectName("BaseMainWindow");
+    resize(1024, 768);
+
+    task = new TaskManager();
+
+    // Create and deploy widgets on main screen
+    QWidget *centralWidget = new QWidget(this);
+    QGridLayout *gridLayout = new QGridLayout(centralWidget);
+    gridLayout->setSpacing(6);
+    gridLayout->setContentsMargins(11, 11, 11, 11);
+
+    QSplitter *splitter_h = new QSplitter(Qt::Horizontal, centralWidget);
+    QSplitter *splitter_v = new QSplitter(Qt::Vertical, splitter_h);
+    splitter_h->addWidget(splitter_v);
+
+    gridLayout->addWidget(splitter_h, 0, 0, 1, 1);
+
+    setCentralWidget(centralWidget);
+
+    designview = new DesignWidget();
+    designview->setMinimumWidth(300);
+    splitter_h->addWidget(designview);
+
+    tabWidget = new QTabWidget();
+
+    console = new PythonTab();
+    tabWidget->addTab(console, "Console");
+
+    centralTabWidget = new QTabWidget();
+    centralTabWidget->setTabsClosable(true);
+
+    fpgaView = new FPGAViewWidget();
+    centralTabWidget->addTab(fpgaView, "Device");
+    centralTabWidget->tabBar()->setTabButton(0, QTabBar::RightSide, 0);
+    centralTabWidget->tabBar()->setTabButton(0, QTabBar::LeftSide, 0);
+
+    splitter_v->addWidget(centralTabWidget);
+    splitter_v->addWidget(tabWidget);
+
+    // Connect Worker
+    connect(task, &TaskManager::log, this, &BaseMainWindow::writeInfo);
+    connect(task, &TaskManager::pack_finished, this, &BaseMainWindow::pack_finished);
+    connect(task, &TaskManager::place_finished, this, &BaseMainWindow::place_finished);
+    connect(task, &TaskManager::route_finished, this, &BaseMainWindow::route_finished);
+    connect(task, &TaskManager::taskCanceled, this, &BaseMainWindow::taskCanceled);
+    connect(task, &TaskManager::taskStarted, this, &BaseMainWindow::taskStarted);
+    connect(task, &TaskManager::taskPaused, this, &BaseMainWindow::taskPaused);
+
+    // Events for context change
+    connect(this, &BaseMainWindow::contextChanged, task, &TaskManager::contextChanged);
+    connect(this, &BaseMainWindow::contextChanged, console, &PythonTab::newContext);
+    connect(this, &BaseMainWindow::contextChanged, fpgaView, &FPGAViewWidget::newContext);
+    connect(this, &BaseMainWindow::contextChanged, designview, &DesignWidget::newContext);
+
+    // Catch close tab events
+    connect(centralTabWidget, &QTabWidget::tabCloseRequested, this, &BaseMainWindow::closeTab);
+
+    // Propagate events from design view to device view
+    connect(designview, &DesignWidget::selected, fpgaView, &FPGAViewWidget::onSelectedArchItem);
+    connect(designview, &DesignWidget::zoomSelected, fpgaView, &FPGAViewWidget::zoomSelected);
+    connect(designview, &DesignWidget::highlight, fpgaView, &FPGAViewWidget::onHighlightGroupChanged);
+    connect(designview, &DesignWidget::hover, fpgaView, &FPGAViewWidget::onHoverItemChanged);
+
+    // Click event on device view
+    connect(fpgaView, &FPGAViewWidget::clickedBel, designview, &DesignWidget::onClickedBel);
+    connect(fpgaView, &FPGAViewWidget::clickedWire, designview, &DesignWidget::onClickedWire);
+    connect(fpgaView, &FPGAViewWidget::clickedPip, designview, &DesignWidget::onClickedPip);
+
+    // Update tree event
+    connect(this, &BaseMainWindow::updateTreeView, designview, &DesignWidget::updateTree);
+
+    createMenusAndBars();
+}
+
+BaseMainWindow::~BaseMainWindow() { delete task; }
+
+void BaseMainWindow::closeTab(int index) { delete centralTabWidget->widget(index); }
+
+void BaseMainWindow::writeInfo(std::string text) { console->info(text); }
+
+void BaseMainWindow::about()
+{
+    QString msg;
+    QTextStream out(&msg);
+    out << "nextpnr-" << NPNR_STRINGIFY_MACRO(ARCHNAME) << "\n";
+    out << "Version " << GIT_DESCRIBE_STR;
+    QMessageBox::information(this, "About nextpnr", msg);
+}
+
+void BaseMainWindow::createMenusAndBars()
+{
+    // File menu / project toolbar actions
+    QAction *actionExit = new QAction("Exit", this);
+    actionExit->setIcon(QIcon(":/icons/resources/exit.png"));
+    actionExit->setShortcuts(QKeySequence::Quit);
+    actionExit->setStatusTip("Exit the application");
+    connect(actionExit, &QAction::triggered, this, &BaseMainWindow::close);
+
+    // Help menu actions
+    QAction *actionAbout = new QAction("About", this);
+    connect(actionAbout, &QAction::triggered, this, &BaseMainWindow::about);
+
+    // Gile menu options
+    actionNew = new QAction("New", this);
+    actionNew->setIcon(QIcon(":/icons/resources/new.png"));
+    actionNew->setShortcuts(QKeySequence::New);
+    actionNew->setStatusTip("New project");
+    connect(actionNew, &QAction::triggered, this, &BaseMainWindow::new_proj);
+
+    actionLoadJSON = new QAction("Open JSON", this);
+    actionLoadJSON->setIcon(QIcon(":/icons/resources/open_json.png"));
+    actionLoadJSON->setStatusTip("Open an existing JSON file");
+    actionLoadJSON->setEnabled(true);
+    connect(actionLoadJSON, &QAction::triggered, this, &BaseMainWindow::open_json);
+
+    actionSaveJSON = new QAction("Save JSON", this);
+    actionSaveJSON->setIcon(QIcon(":/icons/resources/save_json.png"));
+    actionSaveJSON->setStatusTip("Write to JSON file");
+    actionSaveJSON->setEnabled(true);
+    connect(actionSaveJSON, &QAction::triggered, this, &BaseMainWindow::save_json);
+
+    // Design menu options
+    actionPack = new QAction("Pack", this);
+    actionPack->setIcon(QIcon(":/icons/resources/pack.png"));
+    actionPack->setStatusTip("Pack current design");
+    actionPack->setEnabled(false);
+    connect(actionPack, &QAction::triggered, task, &TaskManager::pack);
+
+    actionPlace = new QAction("Place", this);
+    actionPlace->setIcon(QIcon(":/icons/resources/place.png"));
+    actionPlace->setStatusTip("Place current design");
+    actionPlace->setEnabled(false);
+    connect(actionPlace, &QAction::triggered, this, &BaseMainWindow::place);
+
+    actionRoute = new QAction("Route", this);
+    actionRoute->setIcon(QIcon(":/icons/resources/route.png"));
+    actionRoute->setStatusTip("Route current design");
+    actionRoute->setEnabled(false);
+    connect(actionRoute, &QAction::triggered, task, &TaskManager::route);
+
+    actionExecutePy = new QAction("Execute Python", this);
+    actionExecutePy->setIcon(QIcon(":/icons/resources/py.png"));
+    actionExecutePy->setStatusTip("Execute Python script");
+    actionExecutePy->setEnabled(true);
+    connect(actionExecutePy, &QAction::triggered, this, &BaseMainWindow::execute_python);
+
+    // Worker control toolbar actions
+    actionPlay = new QAction("Play", this);
+    actionPlay->setIcon(QIcon(":/icons/resources/control_play.png"));
+    actionPlay->setStatusTip("Continue running task");
+    actionPlay->setEnabled(false);
+    connect(actionPlay, &QAction::triggered, task, &TaskManager::continue_thread);
+
+    actionPause = new QAction("Pause", this);
+    actionPause->setIcon(QIcon(":/icons/resources/control_pause.png"));
+    actionPause->setStatusTip("Pause running task");
+    actionPause->setEnabled(false);
+    connect(actionPause, &QAction::triggered, task, &TaskManager::pause_thread);
+
+    actionStop = new QAction("Stop", this);
+    actionStop->setIcon(QIcon(":/icons/resources/control_stop.png"));
+    actionStop->setStatusTip("Stop running task");
+    actionStop->setEnabled(false);
+    connect(actionStop, &QAction::triggered, task, &TaskManager::terminate_thread);
+
+    // Device view control toolbar actions
+    QAction *actionZoomIn = new QAction("Zoom In", this);
+    actionZoomIn->setIcon(QIcon(":/icons/resources/zoom_in.png"));
+    connect(actionZoomIn, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomIn);
+
+    QAction *actionZoomOut = new QAction("Zoom Out", this);
+    actionZoomOut->setIcon(QIcon(":/icons/resources/zoom_out.png"));
+    connect(actionZoomOut, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomOut);
+
+    QAction *actionZoomSelected = new QAction("Zoom Selected", this);
+    actionZoomSelected->setIcon(QIcon(":/icons/resources/shape_handles.png"));
+    connect(actionZoomSelected, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomSelected);
+
+    QAction *actionZoomOutbound = new QAction("Zoom Outbound", this);
+    actionZoomOutbound->setIcon(QIcon(":/icons/resources/shape_square.png"));
+    connect(actionZoomOutbound, &QAction::triggered, fpgaView, &FPGAViewWidget::zoomOutbound);
+
+    actionDisplayBel = new QAction("Enable/Disable Bels", this);
+    actionDisplayBel->setIcon(QIcon(":/icons/resources/bel.png"));
+    actionDisplayBel->setCheckable(true);
+    actionDisplayBel->setChecked(true);
+    connect(actionDisplayBel, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
+
+    actionDisplayWire = new QAction("Enable/Disable Wires", this);
+    actionDisplayWire->setIcon(QIcon(":/icons/resources/wire.png"));
+    actionDisplayWire->setCheckable(true);
+    actionDisplayWire->setChecked(true);
+    connect(actionDisplayWire, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
+
+    actionDisplayPip = new QAction("Enable/Disable Pips", this);
+    actionDisplayPip->setIcon(QIcon(":/icons/resources/pip.png"));
+    actionDisplayPip->setCheckable(true);
+#ifdef ARCH_ECP5
+    actionDisplayPip->setChecked(false);
+#else
+    actionDisplayPip->setChecked(true);
+#endif
+    connect(actionDisplayPip, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
+
+    actionDisplayGroups = new QAction("Enable/Disable Groups", this);
+    actionDisplayGroups->setIcon(QIcon(":/icons/resources/group.png"));
+    actionDisplayGroups->setCheckable(true);
+    actionDisplayGroups->setChecked(true);
+    connect(actionDisplayGroups, &QAction::triggered, this, &BaseMainWindow::enableDisableDecals);
+
+    actionScreenshot = new QAction("Screenshot", this);
+    actionScreenshot->setIcon(QIcon(":/icons/resources/camera.png"));
+    actionScreenshot->setStatusTip("Taking a screenshot");
+    connect(actionScreenshot, &QAction::triggered, this, &BaseMainWindow::screenshot);
+
+    actionMovie = new QAction("Recording", this);
+    actionMovie->setIcon(QIcon(":/icons/resources/film.png"));
+    actionMovie->setStatusTip("Saving a movie");
+    actionMovie->setCheckable(true);
+    actionMovie->setChecked(false);
+    connect(actionMovie, &QAction::triggered, this, &BaseMainWindow::saveMovie);
+
+    actionSaveSVG = new QAction("Save SVG", this);
+    actionSaveSVG->setIcon(QIcon(":/icons/resources/save_svg.png"));
+    actionSaveSVG->setStatusTip("Saving a SVG");
+    connect(actionSaveSVG, &QAction::triggered, this, &BaseMainWindow::saveSVG);
+
+    // set initial state
+    fpgaView->enableDisableDecals(actionDisplayBel->isChecked(), actionDisplayWire->isChecked(),
+                                  actionDisplayPip->isChecked(), actionDisplayGroups->isChecked());
+
+    // Add main menu
+    menuBar = new QMenuBar();
+    menuBar->setGeometry(QRect(0, 0, 1024, 27));
+    setMenuBar(menuBar);
+    QMenu *menuFile = new QMenu("&File", menuBar);
+    QMenu *menuHelp = new QMenu("&Help", menuBar);
+    menuDesign = new QMenu("&Design", menuBar);
+    menuBar->addAction(menuFile->menuAction());
+    menuBar->addAction(menuDesign->menuAction());
+    menuBar->addAction(menuHelp->menuAction());
+
+    // Add File menu actions
+    menuFile->addAction(actionNew);
+    menuFile->addAction(actionLoadJSON);
+    menuFile->addAction(actionSaveJSON);
+    menuFile->addSeparator();
+    menuFile->addAction(actionExit);
+
+    // Add Design menu actions
+    menuDesign->addAction(actionPack);
+    menuDesign->addAction(actionPlace);
+    menuDesign->addAction(actionRoute);
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionExecutePy);
+
+    // Add Help menu actions
+    menuHelp->addAction(actionAbout);
+
+    // Main action bar
+    mainActionBar = new QToolBar("Main");
+    addToolBar(Qt::TopToolBarArea, mainActionBar);
+    mainActionBar->addAction(actionNew);
+    mainActionBar->addAction(actionLoadJSON);
+    mainActionBar->addAction(actionSaveJSON);
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionPack);
+    mainActionBar->addAction(actionPlace);
+    mainActionBar->addAction(actionRoute);
+    mainActionBar->addAction(actionExecutePy);
+
+    // Add worker control toolbar
+    QToolBar *workerControlToolBar = new QToolBar("Worker");
+    addToolBar(Qt::TopToolBarArea, workerControlToolBar);
+    workerControlToolBar->addAction(actionPlay);
+    workerControlToolBar->addAction(actionPause);
+    workerControlToolBar->addAction(actionStop);
+
+    // Add device view control toolbar
+    QToolBar *deviceViewToolBar = new QToolBar("Device");
+    addToolBar(Qt::TopToolBarArea, deviceViewToolBar);
+    deviceViewToolBar->addAction(actionZoomIn);
+    deviceViewToolBar->addAction(actionZoomOut);
+    deviceViewToolBar->addAction(actionZoomSelected);
+    deviceViewToolBar->addAction(actionZoomOutbound);
+    deviceViewToolBar->addSeparator();
+    deviceViewToolBar->addAction(actionDisplayBel);
+    deviceViewToolBar->addAction(actionDisplayWire);
+    deviceViewToolBar->addAction(actionDisplayPip);
+    deviceViewToolBar->addAction(actionDisplayGroups);
+    deviceViewToolBar->addSeparator();
+    deviceViewToolBar->addAction(actionScreenshot);
+    deviceViewToolBar->addAction(actionMovie);
+    deviceViewToolBar->addAction(actionSaveSVG);
+
+    // Add status bar with progress bar
+    statusBar = new QStatusBar();
+    progressBar = new QProgressBar(statusBar);
+    progressBar->setAlignment(Qt::AlignRight);
+    progressBar->setMaximumSize(180, 19);
+    statusBar->addPermanentWidget(progressBar);
+    progressBar->setValue(0);
+    progressBar->setEnabled(false);
+    setStatusBar(statusBar);
+}
+
+void BaseMainWindow::enableDisableDecals()
+{
+    fpgaView->enableDisableDecals(actionDisplayBel->isChecked(), actionDisplayWire->isChecked(),
+                                  actionDisplayPip->isChecked(), actionDisplayGroups->isChecked());
+    ctx->refreshUi();
+}
+
+void BaseMainWindow::open_json()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open JSON"), QString(), QString("*.json"));
+    if (!fileName.isEmpty()) {
+        disableActions();
+        if (ctx->settings.find(ctx->id("synth")) == ctx->settings.end()) {
+            ArchArgs chipArgs = ctx->getArchArgs();
+            ctx = std::unique_ptr<Context>(new Context(chipArgs));
+            Q_EMIT contextChanged(ctx.get());
+        }
+        handler->load_json(ctx.get(), fileName.toStdString());
+        Q_EMIT updateTreeView();
+        log("Loading design successful.\n");
+        updateActions();
+    }
+}
+
+void BaseMainWindow::save_json()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save JSON"), QString(), QString("*.json"));
+    if (!fileName.isEmpty()) {
+        std::string fn = fileName.toStdString();
+        std::ofstream f(fn);
+        if (write_json_file(f, fn, ctx.get()))
+            log("Saving JSON successful.\n");
+        else
+            log("Saving JSON failed.\n");
+    }
+}
+
+void BaseMainWindow::screenshot()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save screenshot"), QString(), QString("*.png"));
+    if (!fileName.isEmpty()) {
+        QImage image = fpgaView->grabFramebuffer();
+        if (!fileName.endsWith(".png"))
+            fileName += ".png";
+        QImageWriter imageWriter(fileName, "png");
+        if (imageWriter.write(image))
+            log("Saving screenshot successful.\n");
+        else
+            log("Saving screenshot failed.\n");
+    }
+}
+
+void BaseMainWindow::saveMovie()
+{
+    if (actionMovie->isChecked()) {
+        QString dir = QFileDialog::getExistingDirectory(this, tr("Select Movie Directory"), QDir::currentPath(),
+                                                        QFileDialog::ShowDirsOnly | QFileDialog::DontResolveSymlinks);
+        if (!dir.isEmpty()) {
+            bool ok;
+            int frames =
+                    QInputDialog::getInt(this, "Recording", tr("Frames to skip (1 frame = 50ms):"), 5, 0, 1000, 1, &ok);
+            if (ok) {
+                QMessageBox::StandardButton reply =
+                        QMessageBox::question(this, "Recording", "Skip identical frames ?",
+                                              QMessageBox::Yes | QMessageBox::No, QMessageBox::Yes);
+                fpgaView->movieStart(dir, frames, (reply == QMessageBox::Yes));
+            } else
+                actionMovie->setChecked(false);
+        } else
+            actionMovie->setChecked(false);
+    } else {
+        fpgaView->movieStop();
+    }
+}
+
+void BaseMainWindow::saveSVG()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save SVG"), QString(), QString("*.svg"));
+    if (!fileName.isEmpty()) {
+        if (!fileName.endsWith(".svg"))
+            fileName += ".svg";
+        bool ok;
+        QString options =
+                QInputDialog::getText(this, "Save SVG", tr("Save options:"), QLineEdit::Normal, "scale=500", &ok);
+        if (ok) {
+            try {
+                ctx->writeSVG(fileName.toStdString(), options.toStdString());
+                log("Saving SVG successful.\n");
+            } catch (const log_execution_error_exception &ex) {
+                log("Saving SVG failed.\n");
+            }
+        }
+    }
+}
+
+void BaseMainWindow::pack_finished(bool status)
+{
+    disableActions();
+    if (status) {
+        log("Packing design successful.\n");
+        Q_EMIT updateTreeView();
+        updateActions();
+    } else {
+        log("Packing design failed.\n");
+    }
+}
+
+void BaseMainWindow::place_finished(bool status)
+{
+    disableActions();
+    if (status) {
+        log("Placing design successful.\n");
+        Q_EMIT updateTreeView();
+        updateActions();
+    } else {
+        log("Placing design failed.\n");
+    }
+}
+void BaseMainWindow::route_finished(bool status)
+{
+    disableActions();
+    if (status) {
+        log("Routing design successful.\n");
+        Q_EMIT updateTreeView();
+        updateActions();
+    } else
+        log("Routing design failed.\n");
+}
+
+void BaseMainWindow::taskCanceled()
+{
+    log("CANCELED\n");
+    disableActions();
+}
+
+void BaseMainWindow::taskStarted()
+{
+    disableActions();
+    actionPause->setEnabled(true);
+    actionStop->setEnabled(true);
+}
+
+void BaseMainWindow::taskPaused()
+{
+    disableActions();
+    actionPlay->setEnabled(true);
+    actionStop->setEnabled(true);
+}
+
+void BaseMainWindow::place() { Q_EMIT task->place(timing_driven); }
+
+void BaseMainWindow::disableActions()
+{
+    actionLoadJSON->setEnabled(true);
+    actionPack->setEnabled(false);
+    actionPlace->setEnabled(false);
+    actionRoute->setEnabled(false);
+
+    actionExecutePy->setEnabled(true);
+
+    actionPlay->setEnabled(false);
+    actionPause->setEnabled(false);
+    actionStop->setEnabled(false);
+
+    onDisableActions();
+}
+
+void BaseMainWindow::updateActions()
+{
+    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
+        actionPack->setEnabled(true);
+    else if (ctx->settings.find(ctx->id("place")) == ctx->settings.end()) {
+        actionPlace->setEnabled(true);
+    } else if (ctx->settings.find(ctx->id("route")) == ctx->settings.end())
+        actionRoute->setEnabled(true);
+
+    onUpdateActions();
+}
+
+void BaseMainWindow::execute_python()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Execute Python"), QString(), QString("*.py"));
+    if (!fileName.isEmpty()) {
+        console->execute_python(fileName.toStdString());
+    }
+}
+
+void BaseMainWindow::notifyChangeContext() { Q_EMIT contextChanged(ctx.get()); }
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/basewindow.h b/gui/basewindow.h
index 053bb8e6e6..00b8f45cb1 100644
--- a/gui/basewindow.h
+++ b/gui/basewindow.h
@@ -1,142 +1,142 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef BASEMAINWINDOW_H
-#define BASEMAINWINDOW_H
-
-#include "command.h"
-#include "nextpnr.h"
-#include "worker.h"
-
-#include <QMainWindow>
-#include <QMenu>
-#include <QMenuBar>
-#include <QProgressBar>
-#include <QStatusBar>
-#include <QTabWidget>
-#include <QToolBar>
-
-Q_DECLARE_METATYPE(std::string)
-Q_DECLARE_METATYPE(NEXTPNR_NAMESPACE_PREFIX DecalXY)
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class PythonTab;
-class DesignWidget;
-class FPGAViewWidget;
-
-class BaseMainWindow : public QMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit BaseMainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~BaseMainWindow();
-    Context *getContext() { return ctx.get(); }
-    void updateActions();
-
-    void notifyChangeContext();
-
-  protected:
-    void createMenusAndBars();
-    void disableActions();
-    void enableDisableDecals();
-
-    virtual void onDisableActions(){};
-    virtual void onUpdateActions(){};
-
-  protected Q_SLOTS:
-    void writeInfo(std::string text);
-    void closeTab(int index);
-
-    virtual void new_proj() = 0;
-
-    void open_json();
-    void save_json();
-    void place();
-
-    void execute_python();
-
-    void pack_finished(bool status);
-    void place_finished(bool status);
-    void route_finished(bool status);
-
-    void taskCanceled();
-    void taskStarted();
-    void taskPaused();
-
-    void screenshot();
-    void saveMovie();
-    void saveSVG();
-
-    void about();
-
-  Q_SIGNALS:
-    void contextChanged(Context *ctx);
-    void updateTreeView();
-
-  protected:
-    // state variables
-    CommandHandler *handler;
-    std::unique_ptr<Context> ctx;
-    TaskManager *task;
-    bool timing_driven;
-    std::string currentProj;
-
-    // main widgets
-    QTabWidget *tabWidget;
-    QTabWidget *centralTabWidget;
-    PythonTab *console;
-    DesignWidget *designview;
-    FPGAViewWidget *fpgaView;
-
-    // Menus, bars and actions
-    QMenuBar *menuBar;
-    QMenu *menuDesign;
-    QStatusBar *statusBar;
-    QToolBar *mainActionBar;
-    QProgressBar *progressBar;
-
-    QAction *actionNew;
-    QAction *actionLoadJSON;
-    QAction *actionSaveJSON;
-
-    QAction *actionPack;
-    QAction *actionPlace;
-    QAction *actionRoute;
-
-    QAction *actionExecutePy;
-
-    QAction *actionPlay;
-    QAction *actionPause;
-    QAction *actionStop;
-
-    QAction *actionDisplayBel;
-    QAction *actionDisplayWire;
-    QAction *actionDisplayPip;
-    QAction *actionDisplayGroups;
-
-    QAction *actionScreenshot;
-    QAction *actionMovie;
-    QAction *actionSaveSVG;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // BASEMAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef BASEMAINWINDOW_H
+#define BASEMAINWINDOW_H
+
+#include "command.h"
+#include "nextpnr.h"
+#include "worker.h"
+
+#include <QMainWindow>
+#include <QMenu>
+#include <QMenuBar>
+#include <QProgressBar>
+#include <QStatusBar>
+#include <QTabWidget>
+#include <QToolBar>
+
+Q_DECLARE_METATYPE(std::string)
+Q_DECLARE_METATYPE(NEXTPNR_NAMESPACE_PREFIX DecalXY)
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class PythonTab;
+class DesignWidget;
+class FPGAViewWidget;
+
+class BaseMainWindow : public QMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit BaseMainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~BaseMainWindow();
+    Context *getContext() { return ctx.get(); }
+    void updateActions();
+
+    void notifyChangeContext();
+
+  protected:
+    void createMenusAndBars();
+    void disableActions();
+    void enableDisableDecals();
+
+    virtual void onDisableActions(){};
+    virtual void onUpdateActions(){};
+
+  protected Q_SLOTS:
+    void writeInfo(std::string text);
+    void closeTab(int index);
+
+    virtual void new_proj() = 0;
+
+    void open_json();
+    void save_json();
+    void place();
+
+    void execute_python();
+
+    void pack_finished(bool status);
+    void place_finished(bool status);
+    void route_finished(bool status);
+
+    void taskCanceled();
+    void taskStarted();
+    void taskPaused();
+
+    void screenshot();
+    void saveMovie();
+    void saveSVG();
+
+    void about();
+
+  Q_SIGNALS:
+    void contextChanged(Context *ctx);
+    void updateTreeView();
+
+  protected:
+    // state variables
+    CommandHandler *handler;
+    std::unique_ptr<Context> ctx;
+    TaskManager *task;
+    bool timing_driven;
+    std::string currentProj;
+
+    // main widgets
+    QTabWidget *tabWidget;
+    QTabWidget *centralTabWidget;
+    PythonTab *console;
+    DesignWidget *designview;
+    FPGAViewWidget *fpgaView;
+
+    // Menus, bars and actions
+    QMenuBar *menuBar;
+    QMenu *menuDesign;
+    QStatusBar *statusBar;
+    QToolBar *mainActionBar;
+    QProgressBar *progressBar;
+
+    QAction *actionNew;
+    QAction *actionLoadJSON;
+    QAction *actionSaveJSON;
+
+    QAction *actionPack;
+    QAction *actionPlace;
+    QAction *actionRoute;
+
+    QAction *actionExecutePy;
+
+    QAction *actionPlay;
+    QAction *actionPause;
+    QAction *actionStop;
+
+    QAction *actionDisplayBel;
+    QAction *actionDisplayWire;
+    QAction *actionDisplayPip;
+    QAction *actionDisplayGroups;
+
+    QAction *actionScreenshot;
+    QAction *actionMovie;
+    QAction *actionSaveSVG;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // BASEMAINWINDOW_H
diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index bc101d805a..b7c16d45eb 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -1,1072 +1,1072 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *  Copyright (C) 2018  Serge Bazanski <q3k@q3k.org>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "designwidget.h"
-#include <QAction>
-#include <QApplication>
-#include <QGridLayout>
-#include <QLineEdit>
-#include <QMenu>
-#include <QSplitter>
-#include <QToolBar>
-#include <QTreeWidgetItem>
-#include "fpgaviewwidget.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-TreeView::TreeView(QWidget *parent) : QTreeView(parent) {}
-
-TreeView::~TreeView() {}
-
-void TreeView::mouseMoveEvent(QMouseEvent *event)
-{
-    QModelIndex index = indexAt(event->pos());
-    if (index != current) {
-        current = index;
-        Q_EMIT hoverIndexChanged(index);
-    }
-    QTreeView::mouseMoveEvent(event);
-}
-
-void TreeView::leaveEvent(QEvent *event) { Q_EMIT hoverIndexChanged(QModelIndex()); }
-
-DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr)
-{
-    tabWidget = new QTabWidget();
-
-    // Add tree view
-    for (int i = 0; i < 6; i++) {
-        treeView[i] = new TreeView();
-        treeModel[i] = new TreeModel::Model();
-        treeView[i]->setModel(treeModel[i]);
-        treeView[i]->setContextMenuPolicy(Qt::CustomContextMenu);
-        treeView[i]->setSelectionMode(QAbstractItemView::ExtendedSelection);
-        treeView[i]->viewport()->setMouseTracking(true);
-        selectionModel[i] = nullptr;
-    }
-
-    tabWidget->addTab(treeView[0], "Bels");
-    tabWidget->addTab(treeView[1], "Wires");
-    tabWidget->addTab(treeView[2], "Pips");
-    tabWidget->addTab(treeView[3], "Cells");
-    tabWidget->addTab(treeView[4], "Nets");
-    tabWidget->addTab(treeView[5], "Groups");
-
-    // Add property view
-    variantManager = new QtVariantPropertyManager(this);
-    readOnlyManager = new QtVariantPropertyManager(this);
-    groupManager = new QtGroupPropertyManager(this);
-    variantFactory = new QtVariantEditorFactory(this);
-    propertyEditor = new QtTreePropertyBrowser(this);
-    propertyEditor->setFactoryForManager(variantManager, variantFactory);
-    propertyEditor->setPropertiesWithoutValueMarked(true);
-    propertyEditor->show();
-    propertyEditor->treeWidget()->setContextMenuPolicy(Qt::CustomContextMenu);
-    propertyEditor->treeWidget()->setSelectionMode(QAbstractItemView::ExtendedSelection);
-    propertyEditor->treeWidget()->viewport()->setMouseTracking(true);
-
-    searchEdit = new QLineEdit();
-    searchEdit->setClearButtonEnabled(true);
-    searchEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition);
-    searchEdit->setPlaceholderText("Search...");
-    connect(searchEdit, &QLineEdit::returnPressed, this, &DesignWidget::onSearchInserted);
-
-    actionFirst = new QAction("", this);
-    actionFirst->setIcon(QIcon(":/icons/resources/resultset_first.png"));
-    actionFirst->setEnabled(false);
-    connect(actionFirst, &QAction::triggered, this, [this] {
-        history_ignore = true;
-        history_index = 0;
-        auto h = history.at(history_index);
-        if (tabWidget->currentIndex() != h.first) {
-            selectionModel[tabWidget->currentIndex()]->clearSelection();
-            tabWidget->setCurrentIndex(h.first);
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
-        } else {
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
-        }
-        updateButtons();
-    });
-
-    actionPrev = new QAction("", this);
-    actionPrev->setIcon(QIcon(":/icons/resources/resultset_previous.png"));
-    actionPrev->setEnabled(false);
-    connect(actionPrev, &QAction::triggered, this, [this] {
-        history_ignore = true;
-        history_index--;
-        auto h = history.at(history_index);
-        if (tabWidget->currentIndex() != h.first) {
-            selectionModel[tabWidget->currentIndex()]->clearSelection();
-            tabWidget->setCurrentIndex(h.first);
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
-        } else {
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
-        }
-        updateButtons();
-    });
-
-    actionNext = new QAction("", this);
-    actionNext->setIcon(QIcon(":/icons/resources/resultset_next.png"));
-    actionNext->setEnabled(false);
-    connect(actionNext, &QAction::triggered, this, [this] {
-        history_ignore = true;
-        history_index++;
-        auto h = history.at(history_index);
-        if (tabWidget->currentIndex() != h.first) {
-            selectionModel[tabWidget->currentIndex()]->clearSelection();
-            tabWidget->setCurrentIndex(h.first);
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
-        } else {
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
-        }
-        updateButtons();
-    });
-
-    actionLast = new QAction("", this);
-    actionLast->setIcon(QIcon(":/icons/resources/resultset_last.png"));
-    actionLast->setEnabled(false);
-    connect(actionLast, &QAction::triggered, this, [this] {
-        history_ignore = true;
-        history_index = int(history.size() - 1);
-        auto h = history.at(history_index);
-        if (tabWidget->currentIndex() != h.first) {
-            selectionModel[tabWidget->currentIndex()]->clearSelection();
-            tabWidget->setCurrentIndex(h.first);
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
-        } else {
-            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
-        }
-        updateButtons();
-    });
-
-    actionClear = new QAction("", this);
-    actionClear->setIcon(QIcon(":/icons/resources/cross.png"));
-    actionClear->setEnabled(true);
-    connect(actionClear, &QAction::triggered, this, [this] {
-        history_index = -1;
-        history.clear();
-        int num = tabWidget->currentIndex();
-        if (selectionModel[num]->selectedIndexes().size() > 0) {
-            QModelIndex index = selectionModel[num]->selectedIndexes().at(0);
-            if (index.isValid()) {
-                ElementType type = treeModel[num]->nodeFromIndex(index)->type();
-                if (type != ElementType::NONE)
-                    addToHistory(num, index);
-            }
-        }
-        updateButtons();
-    });
-
-    QToolBar *toolbar = new QToolBar();
-    toolbar->addAction(actionFirst);
-    toolbar->addAction(actionPrev);
-    toolbar->addAction(actionNext);
-    toolbar->addAction(actionLast);
-    toolbar->addAction(actionClear);
-
-    QWidget *topWidget = new QWidget();
-    QVBoxLayout *vbox1 = new QVBoxLayout();
-    topWidget->setLayout(vbox1);
-    vbox1->setSpacing(5);
-    vbox1->setContentsMargins(0, 0, 0, 0);
-    vbox1->addWidget(searchEdit);
-    vbox1->addWidget(tabWidget);
-
-    QWidget *toolbarWidget = new QWidget();
-    QHBoxLayout *hbox = new QHBoxLayout;
-    hbox->setAlignment(Qt::AlignCenter);
-    toolbarWidget->setLayout(hbox);
-    hbox->setSpacing(0);
-    hbox->setContentsMargins(0, 0, 0, 0);
-    hbox->addWidget(toolbar);
-
-    QWidget *btmWidget = new QWidget();
-
-    QVBoxLayout *vbox2 = new QVBoxLayout();
-    btmWidget->setLayout(vbox2);
-    vbox2->setSpacing(0);
-    vbox2->setContentsMargins(0, 0, 0, 0);
-    vbox2->addWidget(toolbarWidget);
-    vbox2->addWidget(propertyEditor);
-
-    QSplitter *splitter = new QSplitter(Qt::Vertical);
-    splitter->addWidget(topWidget);
-    splitter->addWidget(btmWidget);
-
-    QGridLayout *mainLayout = new QGridLayout();
-    mainLayout->setSpacing(0);
-    mainLayout->setContentsMargins(0, 0, 0, 0);
-    mainLayout->addWidget(splitter);
-    setLayout(mainLayout);
-
-    // Connection
-    connect(propertyEditor->treeWidget(), &QTreeWidget::customContextMenuRequested, this,
-            &DesignWidget::prepareMenuProperty);
-    connect(propertyEditor->treeWidget(), &QTreeWidget::itemDoubleClicked, this, &DesignWidget::onItemDoubleClicked);
-    connect(propertyEditor, &QtTreePropertyBrowser::hoverPropertyChanged, this, &DesignWidget::onHoverPropertyChanged);
-
-    for (int num = 0; num < 6; num++) {
-        connect(treeView[num], &TreeView::customContextMenuRequested,
-                [this, num](const QPoint &pos) { prepareMenuTree(num, pos); });
-        connect(treeView[num], &TreeView::doubleClicked, [this](const QModelIndex &index) { onDoubleClicked(index); });
-        connect(treeView[num], &TreeView::hoverIndexChanged,
-                [this, num](QModelIndex index) { onHoverIndexChanged(num, index); });
-        selectionModel[num] = treeView[num]->selectionModel();
-        connect(selectionModel[num], &QItemSelectionModel::selectionChanged,
-                [this, num](const QItemSelection &selected, const QItemSelection &deselected) {
-                    onSelectionChanged(num, selected, deselected);
-                });
-    }
-
-    history_index = -1;
-    history_ignore = false;
-
-    highlightColors[0] = QColor("#6495ed");
-    highlightColors[1] = QColor("#7fffd4");
-    highlightColors[2] = QColor("#98fb98");
-    highlightColors[3] = QColor("#ffd700");
-    highlightColors[4] = QColor("#cd5c5c");
-    highlightColors[5] = QColor("#fa8072");
-    highlightColors[6] = QColor("#ff69b4");
-    highlightColors[7] = QColor("#da70d6");
-}
-
-DesignWidget::~DesignWidget() {}
-
-void DesignWidget::updateButtons()
-{
-    int count = int(history.size());
-    actionFirst->setEnabled(history_index > 0);
-    actionPrev->setEnabled(history_index > 0);
-    actionNext->setEnabled(history_index < (count - 1));
-    actionLast->setEnabled(history_index < (count - 1));
-}
-
-void DesignWidget::addToHistory(int tab, QModelIndex item)
-{
-    if (!history_ignore) {
-        int count = int(history.size());
-        for (int i = count - 1; i > history_index; i--)
-            history.pop_back();
-        history.push_back(std::make_pair(tab, item));
-        history_index++;
-    }
-    history_ignore = false;
-    updateButtons();
-}
-
-void DesignWidget::newContext(Context *ctx)
-{
-    if (!ctx)
-        return;
-
-    highlightSelected.clear();
-    history_ignore = false;
-    history_index = -1;
-    history.clear();
-    updateButtons();
-
-    highlightSelected.clear();
-    this->ctx = ctx;
-    {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        {
-            TreeModel::ElementXYRoot<BelId>::ElementMap belMap;
-            for (const auto &bel : ctx->getBels()) {
-                auto loc = ctx->getBelLocation(bel);
-                belMap[std::pair<int, int>(loc.x, loc.y)].push_back(bel);
-            }
-            auto belGetter = [](Context *ctx, BelId id) { return ctx->getBelName(id); };
-
-            getTreeByElementType(ElementType::BEL)
-                    ->loadData(ctx,
-                               std::unique_ptr<TreeModel::ElementXYRoot<BelId>>(
-                                       new TreeModel::ElementXYRoot<BelId>(ctx, belMap, belGetter, ElementType::BEL)));
-        }
-
-        {
-            TreeModel::ElementXYRoot<WireId>::ElementMap wireMap;
-#ifdef ARCH_ICE40
-            for (int i = 0; i < int(ctx->chip_info->wire_data.size()); i++) {
-                const auto wire = &ctx->chip_info->wire_data[i];
-                WireId wireid;
-                wireid.index = i;
-                wireMap[std::pair<int, int>(wire->x, wire->y)].push_back(wireid);
-            }
-#endif
-#ifdef ARCH_ECP5
-            for (const auto &wire : ctx->getWires()) {
-                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
-            }
-#endif
-#ifdef ARCH_MACHXO2
-            for (const auto &wire : ctx->getWires()) {
-                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
-            }
-#endif
-#ifdef ARCH_GOWIN
-            for (const auto &wire : ctx->getWires()) {
-                WireInfo wi = ctx->wire_info(wire);
-                wireMap[std::pair<int, int>(wi.x, wi.y)].push_back(wire);
-            }
-#endif
-#ifdef ARCH_HIMBAECHEL
-            for (const auto &wire : ctx->getWires()) {
-                Loc loc;
-                tile_xy(ctx->chip_info, wire.tile, loc.x, loc.y);
-                wireMap[std::pair<int, int>(loc.x, loc.y)].push_back(wire);
-            }
-#endif
-            auto wireGetter = [](Context *ctx, WireId id) { return ctx->getWireName(id); };
-            getTreeByElementType(ElementType::WIRE)
-                    ->loadData(ctx,
-                               std::unique_ptr<TreeModel::ElementXYRoot<WireId>>(new TreeModel::ElementXYRoot<WireId>(
-                                       ctx, wireMap, wireGetter, ElementType::WIRE)));
-        }
-
-        {
-            TreeModel::ElementXYRoot<PipId>::ElementMap pipMap;
-            for (const auto &pip : ctx->getPips()) {
-                auto loc = ctx->getPipLocation(pip);
-                pipMap[std::pair<int, int>(loc.x, loc.y)].push_back(pip);
-            }
-            auto pipGetter = [](Context *ctx, PipId id) { return ctx->getPipName(id); };
-
-            getTreeByElementType(ElementType::PIP)
-                    ->loadData(ctx,
-                               std::unique_ptr<TreeModel::ElementXYRoot<PipId>>(
-                                       new TreeModel::ElementXYRoot<PipId>(ctx, pipMap, pipGetter, ElementType::PIP)));
-        }
-
-        getTreeByElementType(ElementType::CELL)
-                ->loadData(ctx, std::unique_ptr<TreeModel::IdList>(new TreeModel::IdList(ElementType::CELL)));
-        getTreeByElementType(ElementType::NET)
-                ->loadData(ctx, std::unique_ptr<TreeModel::IdList>(new TreeModel::IdList(ElementType::NET)));
-    }
-    updateTree();
-}
-
-void DesignWidget::updateTree()
-{
-    clearProperties();
-
-    QMap<TreeModel::Item *, int>::iterator i = highlightSelected.begin();
-    while (i != highlightSelected.end()) {
-        QMap<TreeModel::Item *, int>::iterator prev = i;
-        ++i;
-        if (prev.key()->type() == ElementType::NET && ctx->nets.find(prev.key()->id()[0]) == ctx->nets.end()) {
-            highlightSelected.erase(prev);
-        }
-        if (prev.key()->type() == ElementType::CELL && ctx->cells.find(prev.key()->id()[0]) == ctx->cells.end()) {
-            highlightSelected.erase(prev);
-        }
-    }
-
-    {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        std::vector<IdStringList> cells;
-        for (auto &pair : ctx->cells) {
-            cells.push_back(IdStringList(pair.first));
-        }
-        std::vector<IdStringList> nets;
-        for (auto &pair : ctx->nets) {
-            nets.push_back(IdStringList(pair.first));
-        }
-
-        getTreeByElementType(ElementType::CELL)->updateElements(cells);
-        getTreeByElementType(ElementType::NET)->updateElements(nets);
-    }
-}
-QtProperty *DesignWidget::addTopLevelProperty(const QString &id)
-{
-    QtProperty *topItem = groupManager->addProperty(id);
-    propertyToId[topItem] = id;
-    idToProperty[id] = topItem;
-    topItem->setSelectable(false);
-    propertyEditor->addProperty(topItem);
-    return topItem;
-}
-
-void DesignWidget::clearProperties()
-{
-    QMap<QtProperty *, QString>::ConstIterator itProp = propertyToId.constBegin();
-    while (itProp != propertyToId.constEnd()) {
-        delete itProp.key();
-        itProp++;
-    }
-    propertyToId.clear();
-    idToProperty.clear();
-}
-
-QString DesignWidget::getElementTypeName(ElementType type)
-{
-    if (type == ElementType::NONE)
-        return "";
-    if (type == ElementType::BEL)
-        return "BEL";
-    if (type == ElementType::WIRE)
-        return "WIRE";
-    if (type == ElementType::PIP)
-        return "PIP";
-    if (type == ElementType::NET)
-        return "NET";
-    if (type == ElementType::CELL)
-        return "CELL";
-    return "";
-}
-ElementType DesignWidget::getElementTypeByName(QString type)
-{
-    if (type == "BEL")
-        return ElementType::BEL;
-    if (type == "WIRE")
-        return ElementType::WIRE;
-    if (type == "PIP")
-        return ElementType::PIP;
-    if (type == "NET")
-        return ElementType::NET;
-    if (type == "CELL")
-        return ElementType::CELL;
-    return ElementType::NONE;
-}
-
-TreeModel::Model *DesignWidget::getTreeByElementType(ElementType type)
-{
-    if (type == ElementType::NONE)
-        return nullptr;
-    if (type == ElementType::BEL)
-        return treeModel[0];
-    if (type == ElementType::WIRE)
-        return treeModel[1];
-    if (type == ElementType::PIP)
-        return treeModel[2];
-    if (type == ElementType::CELL)
-        return treeModel[3];
-    if (type == ElementType::NET)
-        return treeModel[4];
-    return nullptr;
-}
-int DesignWidget::getIndexByElementType(ElementType type)
-{
-    if (type == ElementType::NONE)
-        return -1;
-    if (type == ElementType::BEL)
-        return 0;
-    if (type == ElementType::WIRE)
-        return 1;
-    if (type == ElementType::PIP)
-        return 2;
-    if (type == ElementType::CELL)
-        return 3;
-    if (type == ElementType::NET)
-        return 4;
-    if (type == ElementType::GROUP)
-        return 5;
-    return -1;
-}
-void DesignWidget::addProperty(QtProperty *topItem, int propertyType, const QString &name, QVariant value,
-                               const ElementType &type)
-{
-    QtVariantProperty *item = readOnlyManager->addProperty(propertyType, name);
-    item->setValue(value);
-    item->setPropertyId(getElementTypeName(type));
-    item->setSelectable(type != ElementType::NONE);
-    topItem->addSubProperty(item);
-}
-
-QtProperty *DesignWidget::addSubGroup(QtProperty *topItem, const QString &name)
-{
-    QtProperty *item = groupManager->addProperty(name);
-    item->setSelectable(false);
-    topItem->addSubProperty(item);
-    return item;
-}
-
-void DesignWidget::clearAllSelectionModels()
-{
-    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++)
-        selectionModel[i]->clearSelection();
-}
-
-void DesignWidget::onClickedBel(BelId bel, bool keep)
-{
-    boost::optional<TreeModel::Item *> item;
-    {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        item = getTreeByElementType(ElementType::BEL)->nodeForId(ctx->getBelName(bel));
-        if (!item)
-            return;
-
-        Q_EMIT selected(getDecals(ElementType::BEL, ctx->getBelName(bel)), keep);
-    }
-    int index = getIndexByElementType(ElementType::BEL);
-    if (!keep)
-        clearAllSelectionModels();
-    if (tabWidget->currentIndex() != index) {
-        tabWidget->setCurrentIndex(index);
-    }
-    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::BEL)->indexFromNode(*item),
-                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
-}
-
-void DesignWidget::onClickedWire(WireId wire, bool keep)
-{
-    boost::optional<TreeModel::Item *> item;
-    {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        item = getTreeByElementType(ElementType::WIRE)->nodeForId(ctx->getWireName(wire));
-        if (!item)
-            return;
-
-        Q_EMIT selected(getDecals(ElementType::WIRE, ctx->getWireName(wire)), keep);
-    }
-    int index = getIndexByElementType(ElementType::WIRE);
-    if (!keep)
-        clearAllSelectionModels();
-    if (tabWidget->currentIndex() != index)
-        tabWidget->setCurrentIndex(index);
-    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::WIRE)->indexFromNode(*item),
-                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
-}
-
-void DesignWidget::onClickedPip(PipId pip, bool keep)
-{
-    boost::optional<TreeModel::Item *> item;
-    {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        item = getTreeByElementType(ElementType::PIP)->nodeForId(ctx->getPipName(pip));
-        if (!item)
-            return;
-
-        Q_EMIT selected(getDecals(ElementType::PIP, ctx->getPipName(pip)), keep);
-    }
-
-    int index = getIndexByElementType(ElementType::PIP);
-    if (!keep)
-        clearAllSelectionModels();
-    if (tabWidget->currentIndex() != index)
-        tabWidget->setCurrentIndex(index);
-    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::PIP)->indexFromNode(*item),
-                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
-}
-
-void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QItemSelection &)
-{
-    int num_selected = 0;
-    std::vector<DecalXY> decals;
-    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++) {
-        num_selected += selectionModel[i]->selectedIndexes().size();
-        for (auto index : selectionModel[i]->selectedIndexes()) {
-            TreeModel::Item *item = treeModel[i]->nodeFromIndex(index);
-            std::vector<DecalXY> d = getDecals(item->type(), item->id());
-            std::move(d.begin(), d.end(), std::back_inserter(decals));
-        }
-    }
-
-    // Keep other tree seleciton only if Control is pressed
-    if (num_selected > 1 && QApplication::keyboardModifiers().testFlag(Qt::ControlModifier) == true) {
-        Q_EMIT selected(decals, false);
-        return;
-    }
-
-    // For deselect and multiple select just send all
-    if (selectionModel[num]->selectedIndexes().size() != 1) {
-        Q_EMIT selected(decals, false);
-        return;
-    }
-
-    QModelIndex index = selectionModel[num]->selectedIndexes().at(0);
-    if (!index.isValid())
-        return;
-    TreeModel::Item *clickItem = treeModel[num]->nodeFromIndex(index);
-
-    ElementType type = clickItem->type();
-    if (type == ElementType::NONE)
-        return;
-
-    // Clear other tab selections
-    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++)
-        if (i != num)
-            selectionModel[i]->clearSelection();
-
-    addToHistory(num, index);
-
-    clearProperties();
-
-    IdStringList c = clickItem->id();
-    Q_EMIT selected(getDecals(type, c), false);
-
-    if (type == ElementType::BEL) {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        BelId bel = ctx->getBelByName(c);
-        QtProperty *topItem = addTopLevelProperty("Bel");
-
-        addProperty(topItem, QVariant::String, "Name", ctx->nameOfBel(bel));
-        addProperty(topItem, QVariant::String, "Type", ctx->getBelType(bel).c_str(ctx));
-        addProperty(topItem, QVariant::Bool, "Available", ctx->checkBelAvail(bel));
-        addProperty(topItem, QVariant::String, "Bound Cell", ctx->nameOf(ctx->getBoundBelCell(bel)), ElementType::CELL);
-        addProperty(topItem, QVariant::String, "Conflicting Cell", ctx->nameOf(ctx->getConflictingBelCell(bel)),
-                    ElementType::CELL);
-
-        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
-        for (auto &item : ctx->getBelAttrs(bel)) {
-            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
-        }
-
-        QtProperty *belpinsItem = addSubGroup(topItem, "Ports");
-        for (const auto &item : ctx->getBelPins(bel)) {
-            QtProperty *portInfoItem = addSubGroup(belpinsItem, item.c_str(ctx));
-            addProperty(portInfoItem, QVariant::String, "Name", item.c_str(ctx));
-            addProperty(portInfoItem, QVariant::Int, "Type", int(ctx->getBelPinType(bel, item)));
-            WireId wire = ctx->getBelPinWire(bel, item);
-            addProperty(portInfoItem, QVariant::String, "Wire", ctx->nameOfWire(wire), ElementType::WIRE);
-        }
-    } else if (type == ElementType::WIRE) {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        WireId wire = ctx->getWireByName(c);
-        QtProperty *topItem = addTopLevelProperty("Wire");
-
-        addProperty(topItem, QVariant::String, "Name", ctx->nameOfWire(wire));
-        addProperty(topItem, QVariant::String, "Type", ctx->getWireType(wire).c_str(ctx));
-        addProperty(topItem, QVariant::Bool, "Available", ctx->checkWireAvail(wire));
-        addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundWireNet(wire)), ElementType::NET);
-        addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingWireWire(wire)),
-                    ElementType::WIRE);
-        addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingWireNet(wire)),
-                    ElementType::NET);
-
-        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
-        for (auto &item : ctx->getWireAttrs(wire)) {
-            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
-        }
-
-        DelayQuad delay = ctx->getWireDelay(wire);
-
-        QtProperty *delayItem = addSubGroup(topItem, "Delay");
-        addProperty(delayItem, QVariant::Double, "Min Rise", delay.minRiseDelay());
-        addProperty(delayItem, QVariant::Double, "Max Rise", delay.maxRiseDelay());
-        addProperty(delayItem, QVariant::Double, "Min Fall", delay.minFallDelay());
-        addProperty(delayItem, QVariant::Double, "Max Fall", delay.maxFallDelay());
-
-        QtProperty *belpinsItem = addSubGroup(topItem, "BelPins");
-        for (const auto &item : ctx->getWireBelPins(wire)) {
-            QString belname = "";
-            if (item.bel != BelId())
-                belname = ctx->nameOfBel(item.bel);
-            QString pinname = item.pin.c_str(ctx);
-
-            QtProperty *dhItem = addSubGroup(belpinsItem, belname + "-" + pinname);
-            addProperty(dhItem, QVariant::String, "Bel", belname, ElementType::BEL);
-            addProperty(dhItem, QVariant::String, "PortPin", pinname);
-        }
-
-        int counter = 0;
-        QtProperty *pipsDownItem = addSubGroup(topItem, "Pips Downhill");
-        for (const auto &item : ctx->getPipsDownhill(wire)) {
-            addProperty(pipsDownItem, QVariant::String, "", ctx->nameOfPip(item), ElementType::PIP);
-            counter++;
-            if (counter == 50) {
-                addProperty(pipsDownItem, QVariant::String, "Warning", "Too many items...", ElementType::NONE);
-                break;
-            }
-        }
-
-        counter = 0;
-        QtProperty *pipsUpItem = addSubGroup(topItem, "Pips Uphill");
-        for (const auto &item : ctx->getPipsUphill(wire)) {
-            addProperty(pipsUpItem, QVariant::String, "", ctx->nameOfPip(item), ElementType::PIP);
-            counter++;
-            if (counter == 50) {
-                addProperty(pipsUpItem, QVariant::String, "Warning", "Too many items...", ElementType::NONE);
-                break;
-            }
-        }
-    } else if (type == ElementType::PIP) {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        PipId pip = ctx->getPipByName(c);
-        QtProperty *topItem = addTopLevelProperty("Pip");
-
-        addProperty(topItem, QVariant::String, "Name", ctx->nameOfPip(pip));
-        addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
-        addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
-        addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
-        if (ctx->getConflictingPipWire(pip) != WireId()) {
-            addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingPipWire(pip)),
-                        ElementType::WIRE);
-        } else {
-            addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
-        }
-        addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
-                    ElementType::NET);
-        addProperty(topItem, QVariant::String, "Src Wire", ctx->nameOfWire(ctx->getPipSrcWire(pip)), ElementType::WIRE);
-        addProperty(topItem, QVariant::String, "Dest Wire", ctx->nameOfWire(ctx->getPipDstWire(pip)),
-                    ElementType::WIRE);
-
-        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
-        for (auto &item : ctx->getPipAttrs(pip)) {
-            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
-        }
-
-        DelayQuad delay = ctx->getPipDelay(pip);
-
-        QtProperty *delayItem = addSubGroup(topItem, "Delay");
-        addProperty(delayItem, QVariant::Double, "Min Rise", delay.minRiseDelay());
-        addProperty(delayItem, QVariant::Double, "Max Rise", delay.maxRiseDelay());
-        addProperty(delayItem, QVariant::Double, "Min Fall", delay.minFallDelay());
-        addProperty(delayItem, QVariant::Double, "Max Fall", delay.maxFallDelay());
-    } else if (type == ElementType::NET) {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        NetInfo *net = ctx->nets.at(c[0]).get();
-
-        QtProperty *topItem = addTopLevelProperty("Net");
-
-        addProperty(topItem, QVariant::String, "Name", net->name.c_str(ctx));
-
-        QtProperty *driverItem = addSubGroup(topItem, "Driver");
-        addProperty(driverItem, QVariant::String, "Port", net->driver.port.c_str(ctx));
-        if (net->driver.cell)
-            addProperty(driverItem, QVariant::String, "Cell", net->driver.cell->name.c_str(ctx), ElementType::CELL);
-        else
-            addProperty(driverItem, QVariant::String, "Cell", "", ElementType::CELL);
-
-        QtProperty *usersItem = addSubGroup(topItem, "Users");
-        for (auto &item : net->users) {
-            QtProperty *portItem = addSubGroup(usersItem, item.port.c_str(ctx));
-
-            addProperty(portItem, QVariant::String, "Port", item.port.c_str(ctx));
-            if (item.cell)
-                addProperty(portItem, QVariant::String, "Cell", item.cell->name.c_str(ctx), ElementType::CELL);
-            else
-                addProperty(portItem, QVariant::String, "Cell", "", ElementType::CELL);
-        }
-
-        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
-        for (auto &item : net->attrs) {
-            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx),
-                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
-        }
-
-        QtProperty *wiresItem = addSubGroup(topItem, "Wires");
-        for (auto &item : net->wires) {
-            auto name = ctx->nameOfWire(item.first);
-
-            QtProperty *wireItem = addSubGroup(wiresItem, name);
-            addProperty(wireItem, QVariant::String, "Wire", name, ElementType::WIRE);
-
-            if (item.second.pip != PipId())
-                addProperty(wireItem, QVariant::String, "Pip", ctx->nameOfPip(item.second.pip), ElementType::PIP);
-            else
-                addProperty(wireItem, QVariant::String, "Pip", "", ElementType::PIP);
-
-            addProperty(wireItem, QVariant::Int, "Strength", (int)item.second.strength);
-        }
-
-    } else if (type == ElementType::CELL) {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        CellInfo *cell = ctx->cells.at(c[0]).get();
-
-        QtProperty *topItem = addTopLevelProperty("Cell");
-
-        addProperty(topItem, QVariant::String, "Name", cell->name.c_str(ctx));
-        addProperty(topItem, QVariant::String, "Type", cell->type.c_str(ctx));
-        if (cell->bel != BelId())
-            addProperty(topItem, QVariant::String, "Bel", ctx->nameOfBel(cell->bel), ElementType::BEL);
-        else
-            addProperty(topItem, QVariant::String, "Bel", "", ElementType::BEL);
-        addProperty(topItem, QVariant::Int, "Bel strength", int(cell->belStrength));
-
-        QtProperty *cellPortsItem = addSubGroup(topItem, "Ports");
-        for (auto &item : cell->ports) {
-            PortInfo p = item.second;
-
-            QtProperty *portInfoItem = addSubGroup(cellPortsItem, p.name.c_str(ctx));
-            addProperty(portInfoItem, QVariant::String, "Name", p.name.c_str(ctx));
-            addProperty(portInfoItem, QVariant::Int, "Type", int(p.type));
-            if (p.net)
-                addProperty(portInfoItem, QVariant::String, "Net", p.net->name.c_str(ctx), ElementType::NET);
-            else
-                addProperty(portInfoItem, QVariant::String, "Net", "", ElementType::NET);
-        }
-
-        QtProperty *cellAttrItem = addSubGroup(topItem, "Attributes");
-        for (auto &item : cell->attrs) {
-            addProperty(cellAttrItem, QVariant::String, item.first.c_str(ctx),
-                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
-        }
-
-        QtProperty *cellParamsItem = addSubGroup(topItem, "Parameters");
-        for (auto &item : cell->params) {
-            addProperty(cellParamsItem, QVariant::String, item.first.c_str(ctx),
-                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
-        }
-    }
-}
-
-std::vector<DecalXY> DesignWidget::getDecals(ElementType type, IdStringList value)
-{
-    std::vector<DecalXY> decals;
-    switch (type) {
-    case ElementType::BEL: {
-        BelId bel = ctx->getBelByName(value);
-        if (bel != BelId()) {
-            decals.push_back(ctx->getBelDecal(bel));
-        }
-    } break;
-    case ElementType::WIRE: {
-        WireId wire = ctx->getWireByName(value);
-        if (wire != WireId()) {
-            decals.push_back(ctx->getWireDecal(wire));
-        }
-    } break;
-    case ElementType::PIP: {
-        PipId pip = ctx->getPipByName(value);
-        if (pip != PipId()) {
-            decals.push_back(ctx->getPipDecal(pip));
-        }
-    } break;
-    case ElementType::NET: {
-        NetInfo *net = ctx->nets.at(value[0]).get();
-        for (auto &item : net->wires) {
-            decals.push_back(ctx->getWireDecal(item.first));
-            if (item.second.pip != PipId()) {
-                decals.push_back(ctx->getPipDecal(item.second.pip));
-            }
-        }
-    } break;
-    case ElementType::CELL: {
-        CellInfo *cell = ctx->cells.at(value[0]).get();
-        if (cell->bel != BelId()) {
-            decals.push_back(ctx->getBelDecal(cell->bel));
-        }
-    } break;
-    default:
-        break;
-    }
-    return decals;
-}
-
-void DesignWidget::updateHighlightGroup(QList<TreeModel::Item *> items, int group)
-{
-    const bool shouldClear = items.size() == 1;
-    for (auto item : items) {
-        if (highlightSelected.contains(item)) {
-            if (shouldClear && highlightSelected[item] == group) {
-                highlightSelected.remove(item);
-            } else
-                highlightSelected[item] = group;
-        } else
-            highlightSelected.insert(item, group);
-    }
-    std::vector<DecalXY> decals[8];
-
-    for (auto it : highlightSelected.toStdMap()) {
-        std::vector<DecalXY> d = getDecals(it.first->type(), it.first->id());
-        std::move(d.begin(), d.end(), std::back_inserter(decals[it.second]));
-    }
-    for (int i = 0; i < 8; i++)
-        Q_EMIT highlight(decals[i], i);
-}
-
-void DesignWidget::prepareMenuProperty(const QPoint &pos)
-{
-    QTreeWidget *tree = propertyEditor->treeWidget();
-    QList<TreeModel::Item *> items;
-    for (auto itemContextMenu : tree->selectedItems()) {
-        QtBrowserItem *browserItem = propertyEditor->itemToBrowserItem(itemContextMenu);
-        if (!browserItem)
-            continue;
-        QtProperty *selectedProperty = browserItem->property();
-        ElementType type = getElementTypeByName(selectedProperty->propertyId());
-        if (type == ElementType::NONE)
-            continue;
-        IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
-        auto node = getTreeByElementType(type)->nodeForId(value);
-        if (!node)
-            continue;
-        items.append(*node);
-    }
-    int selectedIndex = -1;
-    if (items.size() == 1) {
-        TreeModel::Item *item = items.at(0);
-        if (highlightSelected.contains(item))
-            selectedIndex = highlightSelected[item];
-    }
-
-    QMenu menu(this);
-    QAction *selectAction = new QAction("&Select", this);
-    connect(selectAction, &QAction::triggered, this, [this, items] {
-        std::vector<DecalXY> decals;
-        for (auto clickItem : items) {
-            std::vector<DecalXY> d = getDecals(clickItem->type(), clickItem->id());
-            std::move(d.begin(), d.end(), std::back_inserter(decals));
-        }
-        Q_EMIT selected(decals, false);
-    });
-    menu.addAction(selectAction);
-
-    QMenu *subMenu = menu.addMenu("Highlight");
-    QActionGroup *group = new QActionGroup(this);
-    group->setExclusive(true);
-    for (int i = 0; i < 8; i++) {
-        QPixmap pixmap(32, 32);
-        pixmap.fill(QColor(highlightColors[i]));
-        QAction *action = new QAction(QIcon(pixmap), ("Group " + std::to_string(i)).c_str(), this);
-        action->setCheckable(true);
-        subMenu->addAction(action);
-        group->addAction(action);
-        if (selectedIndex == i)
-            action->setChecked(true);
-        connect(action, &QAction::triggered, this, [this, i, items] { updateHighlightGroup(items, i); });
-    }
-    menu.exec(tree->mapToGlobal(pos));
-}
-
-void DesignWidget::prepareMenuTree(int num, const QPoint &pos)
-{
-    int selectedIndex = -1;
-
-    if (selectionModel[num]->selectedIndexes().size() == 0)
-        return;
-
-    QList<TreeModel::Item *> items;
-    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++) {
-        for (auto index : selectionModel[i]->selectedIndexes()) {
-            TreeModel::Item *item = treeModel[i]->nodeFromIndex(index);
-            items.append(item);
-        }
-    }
-    if (items.size() == 1) {
-        TreeModel::Item *item = items.at(0);
-        if (highlightSelected.contains(item))
-            selectedIndex = highlightSelected[item];
-    }
-    QMenu menu(this);
-    QMenu *subMenu = menu.addMenu("Highlight");
-    QActionGroup *group = new QActionGroup(this);
-    group->setExclusive(true);
-    for (int i = 0; i < 8; i++) {
-        QPixmap pixmap(32, 32);
-        pixmap.fill(QColor(highlightColors[i]));
-        QAction *action = new QAction(QIcon(pixmap), ("Group " + std::to_string(i)).c_str(), this);
-        action->setCheckable(true);
-        subMenu->addAction(action);
-        group->addAction(action);
-        if (selectedIndex == i)
-            action->setChecked(true);
-        connect(action, &QAction::triggered, this, [this, i, items] { updateHighlightGroup(items, i); });
-    }
-    menu.exec(treeView[num]->mapToGlobal(pos));
-}
-
-void DesignWidget::onItemDoubleClicked(QTreeWidgetItem *item, int column)
-{
-    QtProperty *selectedProperty = propertyEditor->itemToBrowserItem(item)->property();
-    ElementType type = getElementTypeByName(selectedProperty->propertyId());
-    if (type == ElementType::NONE)
-        return;
-
-    IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
-    auto it = getTreeByElementType(type)->nodeForId(value);
-    if (it) {
-        int num = getIndexByElementType(type);
-        clearAllSelectionModels();
-        if (tabWidget->currentIndex() != num)
-            tabWidget->setCurrentIndex(num);
-        selectionModel[num]->setCurrentIndex(getTreeByElementType(type)->indexFromNode(*it),
-                                             QItemSelectionModel::ClearAndSelect);
-    }
-}
-
-void DesignWidget::onDoubleClicked(const QModelIndex &index) { Q_EMIT zoomSelected(); }
-
-void DesignWidget::onSearchInserted()
-{
-    if (currentSearch == searchEdit->text() && currentIndexTab == tabWidget->currentIndex()) {
-        currentIndex++;
-        if (currentIndex >= currentSearchIndexes.size())
-            currentIndex = 0;
-    } else {
-        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
-        std::lock_guard<std::mutex> lock(ctx->mutex);
-
-        currentSearch = searchEdit->text();
-        currentSearchIndexes = treeModel[tabWidget->currentIndex()]->search(searchEdit->text());
-        currentIndex = 0;
-        currentIndexTab = tabWidget->currentIndex();
-    }
-    if (currentSearchIndexes.size() > 0 && currentIndex < currentSearchIndexes.size())
-        selectionModel[tabWidget->currentIndex()]->setCurrentIndex(currentSearchIndexes.at(currentIndex),
-                                                                   QItemSelectionModel::ClearAndSelect);
-}
-
-void DesignWidget::onHoverIndexChanged(int num, QModelIndex index)
-{
-    if (index.isValid()) {
-        TreeModel::Item *item = treeModel[num]->nodeFromIndex(index);
-        if (item->type() != ElementType::NONE) {
-            std::vector<DecalXY> decals = getDecals(item->type(), item->id());
-            if (decals.size() > 0)
-                Q_EMIT hover(decals.at(0));
-            return;
-        }
-    }
-    Q_EMIT hover(DecalXY());
-}
-
-void DesignWidget::onHoverPropertyChanged(QtBrowserItem *item)
-{
-    if (item != nullptr) {
-        QtProperty *selectedProperty = item->property();
-        ElementType type = getElementTypeByName(selectedProperty->propertyId());
-        if (type != ElementType::NONE) {
-            IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
-            if (value != IdStringList()) {
-                auto node = getTreeByElementType(type)->nodeForId(value);
-                if (node) {
-                    std::vector<DecalXY> decals = getDecals((*node)->type(), (*node)->id());
-                    if (decals.size() > 0)
-                        Q_EMIT hover(decals.at(0));
-                    return;
-                }
-            }
-        }
-    }
-    Q_EMIT hover(DecalXY());
-}
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *  Copyright (C) 2018  Serge Bazanski <q3k@q3k.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "designwidget.h"
+#include <QAction>
+#include <QApplication>
+#include <QGridLayout>
+#include <QLineEdit>
+#include <QMenu>
+#include <QSplitter>
+#include <QToolBar>
+#include <QTreeWidgetItem>
+#include "fpgaviewwidget.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+TreeView::TreeView(QWidget *parent) : QTreeView(parent) {}
+
+TreeView::~TreeView() {}
+
+void TreeView::mouseMoveEvent(QMouseEvent *event)
+{
+    QModelIndex index = indexAt(event->pos());
+    if (index != current) {
+        current = index;
+        Q_EMIT hoverIndexChanged(index);
+    }
+    QTreeView::mouseMoveEvent(event);
+}
+
+void TreeView::leaveEvent(QEvent *event) { Q_EMIT hoverIndexChanged(QModelIndex()); }
+
+DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr)
+{
+    tabWidget = new QTabWidget();
+
+    // Add tree view
+    for (int i = 0; i < 6; i++) {
+        treeView[i] = new TreeView();
+        treeModel[i] = new TreeModel::Model();
+        treeView[i]->setModel(treeModel[i]);
+        treeView[i]->setContextMenuPolicy(Qt::CustomContextMenu);
+        treeView[i]->setSelectionMode(QAbstractItemView::ExtendedSelection);
+        treeView[i]->viewport()->setMouseTracking(true);
+        selectionModel[i] = nullptr;
+    }
+
+    tabWidget->addTab(treeView[0], "Bels");
+    tabWidget->addTab(treeView[1], "Wires");
+    tabWidget->addTab(treeView[2], "Pips");
+    tabWidget->addTab(treeView[3], "Cells");
+    tabWidget->addTab(treeView[4], "Nets");
+    tabWidget->addTab(treeView[5], "Groups");
+
+    // Add property view
+    variantManager = new QtVariantPropertyManager(this);
+    readOnlyManager = new QtVariantPropertyManager(this);
+    groupManager = new QtGroupPropertyManager(this);
+    variantFactory = new QtVariantEditorFactory(this);
+    propertyEditor = new QtTreePropertyBrowser(this);
+    propertyEditor->setFactoryForManager(variantManager, variantFactory);
+    propertyEditor->setPropertiesWithoutValueMarked(true);
+    propertyEditor->show();
+    propertyEditor->treeWidget()->setContextMenuPolicy(Qt::CustomContextMenu);
+    propertyEditor->treeWidget()->setSelectionMode(QAbstractItemView::ExtendedSelection);
+    propertyEditor->treeWidget()->viewport()->setMouseTracking(true);
+
+    searchEdit = new QLineEdit();
+    searchEdit->setClearButtonEnabled(true);
+    searchEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition);
+    searchEdit->setPlaceholderText("Search...");
+    connect(searchEdit, &QLineEdit::returnPressed, this, &DesignWidget::onSearchInserted);
+
+    actionFirst = new QAction("", this);
+    actionFirst->setIcon(QIcon(":/icons/resources/resultset_first.png"));
+    actionFirst->setEnabled(false);
+    connect(actionFirst, &QAction::triggered, this, [this] {
+        history_ignore = true;
+        history_index = 0;
+        auto h = history.at(history_index);
+        if (tabWidget->currentIndex() != h.first) {
+            selectionModel[tabWidget->currentIndex()]->clearSelection();
+            tabWidget->setCurrentIndex(h.first);
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
+        } else {
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
+        }
+        updateButtons();
+    });
+
+    actionPrev = new QAction("", this);
+    actionPrev->setIcon(QIcon(":/icons/resources/resultset_previous.png"));
+    actionPrev->setEnabled(false);
+    connect(actionPrev, &QAction::triggered, this, [this] {
+        history_ignore = true;
+        history_index--;
+        auto h = history.at(history_index);
+        if (tabWidget->currentIndex() != h.first) {
+            selectionModel[tabWidget->currentIndex()]->clearSelection();
+            tabWidget->setCurrentIndex(h.first);
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
+        } else {
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
+        }
+        updateButtons();
+    });
+
+    actionNext = new QAction("", this);
+    actionNext->setIcon(QIcon(":/icons/resources/resultset_next.png"));
+    actionNext->setEnabled(false);
+    connect(actionNext, &QAction::triggered, this, [this] {
+        history_ignore = true;
+        history_index++;
+        auto h = history.at(history_index);
+        if (tabWidget->currentIndex() != h.first) {
+            selectionModel[tabWidget->currentIndex()]->clearSelection();
+            tabWidget->setCurrentIndex(h.first);
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
+        } else {
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
+        }
+        updateButtons();
+    });
+
+    actionLast = new QAction("", this);
+    actionLast->setIcon(QIcon(":/icons/resources/resultset_last.png"));
+    actionLast->setEnabled(false);
+    connect(actionLast, &QAction::triggered, this, [this] {
+        history_ignore = true;
+        history_index = int(history.size() - 1);
+        auto h = history.at(history_index);
+        if (tabWidget->currentIndex() != h.first) {
+            selectionModel[tabWidget->currentIndex()]->clearSelection();
+            tabWidget->setCurrentIndex(h.first);
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::Select);
+        } else {
+            selectionModel[h.first]->setCurrentIndex(h.second, QItemSelectionModel::ClearAndSelect);
+        }
+        updateButtons();
+    });
+
+    actionClear = new QAction("", this);
+    actionClear->setIcon(QIcon(":/icons/resources/cross.png"));
+    actionClear->setEnabled(true);
+    connect(actionClear, &QAction::triggered, this, [this] {
+        history_index = -1;
+        history.clear();
+        int num = tabWidget->currentIndex();
+        if (selectionModel[num]->selectedIndexes().size() > 0) {
+            QModelIndex index = selectionModel[num]->selectedIndexes().at(0);
+            if (index.isValid()) {
+                ElementType type = treeModel[num]->nodeFromIndex(index)->type();
+                if (type != ElementType::NONE)
+                    addToHistory(num, index);
+            }
+        }
+        updateButtons();
+    });
+
+    QToolBar *toolbar = new QToolBar();
+    toolbar->addAction(actionFirst);
+    toolbar->addAction(actionPrev);
+    toolbar->addAction(actionNext);
+    toolbar->addAction(actionLast);
+    toolbar->addAction(actionClear);
+
+    QWidget *topWidget = new QWidget();
+    QVBoxLayout *vbox1 = new QVBoxLayout();
+    topWidget->setLayout(vbox1);
+    vbox1->setSpacing(5);
+    vbox1->setContentsMargins(0, 0, 0, 0);
+    vbox1->addWidget(searchEdit);
+    vbox1->addWidget(tabWidget);
+
+    QWidget *toolbarWidget = new QWidget();
+    QHBoxLayout *hbox = new QHBoxLayout;
+    hbox->setAlignment(Qt::AlignCenter);
+    toolbarWidget->setLayout(hbox);
+    hbox->setSpacing(0);
+    hbox->setContentsMargins(0, 0, 0, 0);
+    hbox->addWidget(toolbar);
+
+    QWidget *btmWidget = new QWidget();
+
+    QVBoxLayout *vbox2 = new QVBoxLayout();
+    btmWidget->setLayout(vbox2);
+    vbox2->setSpacing(0);
+    vbox2->setContentsMargins(0, 0, 0, 0);
+    vbox2->addWidget(toolbarWidget);
+    vbox2->addWidget(propertyEditor);
+
+    QSplitter *splitter = new QSplitter(Qt::Vertical);
+    splitter->addWidget(topWidget);
+    splitter->addWidget(btmWidget);
+
+    QGridLayout *mainLayout = new QGridLayout();
+    mainLayout->setSpacing(0);
+    mainLayout->setContentsMargins(0, 0, 0, 0);
+    mainLayout->addWidget(splitter);
+    setLayout(mainLayout);
+
+    // Connection
+    connect(propertyEditor->treeWidget(), &QTreeWidget::customContextMenuRequested, this,
+            &DesignWidget::prepareMenuProperty);
+    connect(propertyEditor->treeWidget(), &QTreeWidget::itemDoubleClicked, this, &DesignWidget::onItemDoubleClicked);
+    connect(propertyEditor, &QtTreePropertyBrowser::hoverPropertyChanged, this, &DesignWidget::onHoverPropertyChanged);
+
+    for (int num = 0; num < 6; num++) {
+        connect(treeView[num], &TreeView::customContextMenuRequested,
+                [this, num](const QPoint &pos) { prepareMenuTree(num, pos); });
+        connect(treeView[num], &TreeView::doubleClicked, [this](const QModelIndex &index) { onDoubleClicked(index); });
+        connect(treeView[num], &TreeView::hoverIndexChanged,
+                [this, num](QModelIndex index) { onHoverIndexChanged(num, index); });
+        selectionModel[num] = treeView[num]->selectionModel();
+        connect(selectionModel[num], &QItemSelectionModel::selectionChanged,
+                [this, num](const QItemSelection &selected, const QItemSelection &deselected) {
+                    onSelectionChanged(num, selected, deselected);
+                });
+    }
+
+    history_index = -1;
+    history_ignore = false;
+
+    highlightColors[0] = QColor("#6495ed");
+    highlightColors[1] = QColor("#7fffd4");
+    highlightColors[2] = QColor("#98fb98");
+    highlightColors[3] = QColor("#ffd700");
+    highlightColors[4] = QColor("#cd5c5c");
+    highlightColors[5] = QColor("#fa8072");
+    highlightColors[6] = QColor("#ff69b4");
+    highlightColors[7] = QColor("#da70d6");
+}
+
+DesignWidget::~DesignWidget() {}
+
+void DesignWidget::updateButtons()
+{
+    int count = int(history.size());
+    actionFirst->setEnabled(history_index > 0);
+    actionPrev->setEnabled(history_index > 0);
+    actionNext->setEnabled(history_index < (count - 1));
+    actionLast->setEnabled(history_index < (count - 1));
+}
+
+void DesignWidget::addToHistory(int tab, QModelIndex item)
+{
+    if (!history_ignore) {
+        int count = int(history.size());
+        for (int i = count - 1; i > history_index; i--)
+            history.pop_back();
+        history.push_back(std::make_pair(tab, item));
+        history_index++;
+    }
+    history_ignore = false;
+    updateButtons();
+}
+
+void DesignWidget::newContext(Context *ctx)
+{
+    if (!ctx)
+        return;
+
+    highlightSelected.clear();
+    history_ignore = false;
+    history_index = -1;
+    history.clear();
+    updateButtons();
+
+    highlightSelected.clear();
+    this->ctx = ctx;
+    {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        {
+            TreeModel::ElementXYRoot<BelId>::ElementMap belMap;
+            for (const auto &bel : ctx->getBels()) {
+                auto loc = ctx->getBelLocation(bel);
+                belMap[std::pair<int, int>(loc.x, loc.y)].push_back(bel);
+            }
+            auto belGetter = [](Context *ctx, BelId id) { return ctx->getBelName(id); };
+
+            getTreeByElementType(ElementType::BEL)
+                    ->loadData(ctx,
+                               std::unique_ptr<TreeModel::ElementXYRoot<BelId>>(
+                                       new TreeModel::ElementXYRoot<BelId>(ctx, belMap, belGetter, ElementType::BEL)));
+        }
+
+        {
+            TreeModel::ElementXYRoot<WireId>::ElementMap wireMap;
+#ifdef ARCH_ICE40
+            for (int i = 0; i < int(ctx->chip_info->wire_data.size()); i++) {
+                const auto wire = &ctx->chip_info->wire_data[i];
+                WireId wireid;
+                wireid.index = i;
+                wireMap[std::pair<int, int>(wire->x, wire->y)].push_back(wireid);
+            }
+#endif
+#ifdef ARCH_ECP5
+            for (const auto &wire : ctx->getWires()) {
+                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
+            }
+#endif
+#ifdef ARCH_MACHXO2
+            for (const auto &wire : ctx->getWires()) {
+                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
+            }
+#endif
+#ifdef ARCH_GOWIN
+            for (const auto &wire : ctx->getWires()) {
+                WireInfo wi = ctx->wire_info(wire);
+                wireMap[std::pair<int, int>(wi.x, wi.y)].push_back(wire);
+            }
+#endif
+#ifdef ARCH_HIMBAECHEL
+            for (const auto &wire : ctx->getWires()) {
+                Loc loc;
+                tile_xy(ctx->chip_info, wire.tile, loc.x, loc.y);
+                wireMap[std::pair<int, int>(loc.x, loc.y)].push_back(wire);
+            }
+#endif
+            auto wireGetter = [](Context *ctx, WireId id) { return ctx->getWireName(id); };
+            getTreeByElementType(ElementType::WIRE)
+                    ->loadData(ctx,
+                               std::unique_ptr<TreeModel::ElementXYRoot<WireId>>(new TreeModel::ElementXYRoot<WireId>(
+                                       ctx, wireMap, wireGetter, ElementType::WIRE)));
+        }
+
+        {
+            TreeModel::ElementXYRoot<PipId>::ElementMap pipMap;
+            for (const auto &pip : ctx->getPips()) {
+                auto loc = ctx->getPipLocation(pip);
+                pipMap[std::pair<int, int>(loc.x, loc.y)].push_back(pip);
+            }
+            auto pipGetter = [](Context *ctx, PipId id) { return ctx->getPipName(id); };
+
+            getTreeByElementType(ElementType::PIP)
+                    ->loadData(ctx,
+                               std::unique_ptr<TreeModel::ElementXYRoot<PipId>>(
+                                       new TreeModel::ElementXYRoot<PipId>(ctx, pipMap, pipGetter, ElementType::PIP)));
+        }
+
+        getTreeByElementType(ElementType::CELL)
+                ->loadData(ctx, std::unique_ptr<TreeModel::IdList>(new TreeModel::IdList(ElementType::CELL)));
+        getTreeByElementType(ElementType::NET)
+                ->loadData(ctx, std::unique_ptr<TreeModel::IdList>(new TreeModel::IdList(ElementType::NET)));
+    }
+    updateTree();
+}
+
+void DesignWidget::updateTree()
+{
+    clearProperties();
+
+    QMap<TreeModel::Item *, int>::iterator i = highlightSelected.begin();
+    while (i != highlightSelected.end()) {
+        QMap<TreeModel::Item *, int>::iterator prev = i;
+        ++i;
+        if (prev.key()->type() == ElementType::NET && ctx->nets.find(prev.key()->id()[0]) == ctx->nets.end()) {
+            highlightSelected.erase(prev);
+        }
+        if (prev.key()->type() == ElementType::CELL && ctx->cells.find(prev.key()->id()[0]) == ctx->cells.end()) {
+            highlightSelected.erase(prev);
+        }
+    }
+
+    {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        std::vector<IdStringList> cells;
+        for (auto &pair : ctx->cells) {
+            cells.push_back(IdStringList(pair.first));
+        }
+        std::vector<IdStringList> nets;
+        for (auto &pair : ctx->nets) {
+            nets.push_back(IdStringList(pair.first));
+        }
+
+        getTreeByElementType(ElementType::CELL)->updateElements(cells);
+        getTreeByElementType(ElementType::NET)->updateElements(nets);
+    }
+}
+QtProperty *DesignWidget::addTopLevelProperty(const QString &id)
+{
+    QtProperty *topItem = groupManager->addProperty(id);
+    propertyToId[topItem] = id;
+    idToProperty[id] = topItem;
+    topItem->setSelectable(false);
+    propertyEditor->addProperty(topItem);
+    return topItem;
+}
+
+void DesignWidget::clearProperties()
+{
+    QMap<QtProperty *, QString>::ConstIterator itProp = propertyToId.constBegin();
+    while (itProp != propertyToId.constEnd()) {
+        delete itProp.key();
+        itProp++;
+    }
+    propertyToId.clear();
+    idToProperty.clear();
+}
+
+QString DesignWidget::getElementTypeName(ElementType type)
+{
+    if (type == ElementType::NONE)
+        return "";
+    if (type == ElementType::BEL)
+        return "BEL";
+    if (type == ElementType::WIRE)
+        return "WIRE";
+    if (type == ElementType::PIP)
+        return "PIP";
+    if (type == ElementType::NET)
+        return "NET";
+    if (type == ElementType::CELL)
+        return "CELL";
+    return "";
+}
+ElementType DesignWidget::getElementTypeByName(QString type)
+{
+    if (type == "BEL")
+        return ElementType::BEL;
+    if (type == "WIRE")
+        return ElementType::WIRE;
+    if (type == "PIP")
+        return ElementType::PIP;
+    if (type == "NET")
+        return ElementType::NET;
+    if (type == "CELL")
+        return ElementType::CELL;
+    return ElementType::NONE;
+}
+
+TreeModel::Model *DesignWidget::getTreeByElementType(ElementType type)
+{
+    if (type == ElementType::NONE)
+        return nullptr;
+    if (type == ElementType::BEL)
+        return treeModel[0];
+    if (type == ElementType::WIRE)
+        return treeModel[1];
+    if (type == ElementType::PIP)
+        return treeModel[2];
+    if (type == ElementType::CELL)
+        return treeModel[3];
+    if (type == ElementType::NET)
+        return treeModel[4];
+    return nullptr;
+}
+int DesignWidget::getIndexByElementType(ElementType type)
+{
+    if (type == ElementType::NONE)
+        return -1;
+    if (type == ElementType::BEL)
+        return 0;
+    if (type == ElementType::WIRE)
+        return 1;
+    if (type == ElementType::PIP)
+        return 2;
+    if (type == ElementType::CELL)
+        return 3;
+    if (type == ElementType::NET)
+        return 4;
+    if (type == ElementType::GROUP)
+        return 5;
+    return -1;
+}
+void DesignWidget::addProperty(QtProperty *topItem, int propertyType, const QString &name, QVariant value,
+                               const ElementType &type)
+{
+    QtVariantProperty *item = readOnlyManager->addProperty(propertyType, name);
+    item->setValue(value);
+    item->setPropertyId(getElementTypeName(type));
+    item->setSelectable(type != ElementType::NONE);
+    topItem->addSubProperty(item);
+}
+
+QtProperty *DesignWidget::addSubGroup(QtProperty *topItem, const QString &name)
+{
+    QtProperty *item = groupManager->addProperty(name);
+    item->setSelectable(false);
+    topItem->addSubProperty(item);
+    return item;
+}
+
+void DesignWidget::clearAllSelectionModels()
+{
+    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++)
+        selectionModel[i]->clearSelection();
+}
+
+void DesignWidget::onClickedBel(BelId bel, bool keep)
+{
+    boost::optional<TreeModel::Item *> item;
+    {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        item = getTreeByElementType(ElementType::BEL)->nodeForId(ctx->getBelName(bel));
+        if (!item)
+            return;
+
+        Q_EMIT selected(getDecals(ElementType::BEL, ctx->getBelName(bel)), keep);
+    }
+    int index = getIndexByElementType(ElementType::BEL);
+    if (!keep)
+        clearAllSelectionModels();
+    if (tabWidget->currentIndex() != index) {
+        tabWidget->setCurrentIndex(index);
+    }
+    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::BEL)->indexFromNode(*item),
+                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
+}
+
+void DesignWidget::onClickedWire(WireId wire, bool keep)
+{
+    boost::optional<TreeModel::Item *> item;
+    {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        item = getTreeByElementType(ElementType::WIRE)->nodeForId(ctx->getWireName(wire));
+        if (!item)
+            return;
+
+        Q_EMIT selected(getDecals(ElementType::WIRE, ctx->getWireName(wire)), keep);
+    }
+    int index = getIndexByElementType(ElementType::WIRE);
+    if (!keep)
+        clearAllSelectionModels();
+    if (tabWidget->currentIndex() != index)
+        tabWidget->setCurrentIndex(index);
+    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::WIRE)->indexFromNode(*item),
+                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
+}
+
+void DesignWidget::onClickedPip(PipId pip, bool keep)
+{
+    boost::optional<TreeModel::Item *> item;
+    {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        item = getTreeByElementType(ElementType::PIP)->nodeForId(ctx->getPipName(pip));
+        if (!item)
+            return;
+
+        Q_EMIT selected(getDecals(ElementType::PIP, ctx->getPipName(pip)), keep);
+    }
+
+    int index = getIndexByElementType(ElementType::PIP);
+    if (!keep)
+        clearAllSelectionModels();
+    if (tabWidget->currentIndex() != index)
+        tabWidget->setCurrentIndex(index);
+    selectionModel[index]->setCurrentIndex(getTreeByElementType(ElementType::PIP)->indexFromNode(*item),
+                                           keep ? QItemSelectionModel::Select : QItemSelectionModel::ClearAndSelect);
+}
+
+void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QItemSelection &)
+{
+    int num_selected = 0;
+    std::vector<DecalXY> decals;
+    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++) {
+        num_selected += selectionModel[i]->selectedIndexes().size();
+        for (auto index : selectionModel[i]->selectedIndexes()) {
+            TreeModel::Item *item = treeModel[i]->nodeFromIndex(index);
+            std::vector<DecalXY> d = getDecals(item->type(), item->id());
+            std::move(d.begin(), d.end(), std::back_inserter(decals));
+        }
+    }
+
+    // Keep other tree seleciton only if Control is pressed
+    if (num_selected > 1 && QApplication::keyboardModifiers().testFlag(Qt::ControlModifier) == true) {
+        Q_EMIT selected(decals, false);
+        return;
+    }
+
+    // For deselect and multiple select just send all
+    if (selectionModel[num]->selectedIndexes().size() != 1) {
+        Q_EMIT selected(decals, false);
+        return;
+    }
+
+    QModelIndex index = selectionModel[num]->selectedIndexes().at(0);
+    if (!index.isValid())
+        return;
+    TreeModel::Item *clickItem = treeModel[num]->nodeFromIndex(index);
+
+    ElementType type = clickItem->type();
+    if (type == ElementType::NONE)
+        return;
+
+    // Clear other tab selections
+    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++)
+        if (i != num)
+            selectionModel[i]->clearSelection();
+
+    addToHistory(num, index);
+
+    clearProperties();
+
+    IdStringList c = clickItem->id();
+    Q_EMIT selected(getDecals(type, c), false);
+
+    if (type == ElementType::BEL) {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        BelId bel = ctx->getBelByName(c);
+        QtProperty *topItem = addTopLevelProperty("Bel");
+
+        addProperty(topItem, QVariant::String, "Name", ctx->nameOfBel(bel));
+        addProperty(topItem, QVariant::String, "Type", ctx->getBelType(bel).c_str(ctx));
+        addProperty(topItem, QVariant::Bool, "Available", ctx->checkBelAvail(bel));
+        addProperty(topItem, QVariant::String, "Bound Cell", ctx->nameOf(ctx->getBoundBelCell(bel)), ElementType::CELL);
+        addProperty(topItem, QVariant::String, "Conflicting Cell", ctx->nameOf(ctx->getConflictingBelCell(bel)),
+                    ElementType::CELL);
+
+        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
+        for (auto &item : ctx->getBelAttrs(bel)) {
+            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
+        }
+
+        QtProperty *belpinsItem = addSubGroup(topItem, "Ports");
+        for (const auto &item : ctx->getBelPins(bel)) {
+            QtProperty *portInfoItem = addSubGroup(belpinsItem, item.c_str(ctx));
+            addProperty(portInfoItem, QVariant::String, "Name", item.c_str(ctx));
+            addProperty(portInfoItem, QVariant::Int, "Type", int(ctx->getBelPinType(bel, item)));
+            WireId wire = ctx->getBelPinWire(bel, item);
+            addProperty(portInfoItem, QVariant::String, "Wire", ctx->nameOfWire(wire), ElementType::WIRE);
+        }
+    } else if (type == ElementType::WIRE) {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        WireId wire = ctx->getWireByName(c);
+        QtProperty *topItem = addTopLevelProperty("Wire");
+
+        addProperty(topItem, QVariant::String, "Name", ctx->nameOfWire(wire));
+        addProperty(topItem, QVariant::String, "Type", ctx->getWireType(wire).c_str(ctx));
+        addProperty(topItem, QVariant::Bool, "Available", ctx->checkWireAvail(wire));
+        addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundWireNet(wire)), ElementType::NET);
+        addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingWireWire(wire)),
+                    ElementType::WIRE);
+        addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingWireNet(wire)),
+                    ElementType::NET);
+
+        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
+        for (auto &item : ctx->getWireAttrs(wire)) {
+            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
+        }
+
+        DelayQuad delay = ctx->getWireDelay(wire);
+
+        QtProperty *delayItem = addSubGroup(topItem, "Delay");
+        addProperty(delayItem, QVariant::Double, "Min Rise", delay.minRiseDelay());
+        addProperty(delayItem, QVariant::Double, "Max Rise", delay.maxRiseDelay());
+        addProperty(delayItem, QVariant::Double, "Min Fall", delay.minFallDelay());
+        addProperty(delayItem, QVariant::Double, "Max Fall", delay.maxFallDelay());
+
+        QtProperty *belpinsItem = addSubGroup(topItem, "BelPins");
+        for (const auto &item : ctx->getWireBelPins(wire)) {
+            QString belname = "";
+            if (item.bel != BelId())
+                belname = ctx->nameOfBel(item.bel);
+            QString pinname = item.pin.c_str(ctx);
+
+            QtProperty *dhItem = addSubGroup(belpinsItem, belname + "-" + pinname);
+            addProperty(dhItem, QVariant::String, "Bel", belname, ElementType::BEL);
+            addProperty(dhItem, QVariant::String, "PortPin", pinname);
+        }
+
+        int counter = 0;
+        QtProperty *pipsDownItem = addSubGroup(topItem, "Pips Downhill");
+        for (const auto &item : ctx->getPipsDownhill(wire)) {
+            addProperty(pipsDownItem, QVariant::String, "", ctx->nameOfPip(item), ElementType::PIP);
+            counter++;
+            if (counter == 50) {
+                addProperty(pipsDownItem, QVariant::String, "Warning", "Too many items...", ElementType::NONE);
+                break;
+            }
+        }
+
+        counter = 0;
+        QtProperty *pipsUpItem = addSubGroup(topItem, "Pips Uphill");
+        for (const auto &item : ctx->getPipsUphill(wire)) {
+            addProperty(pipsUpItem, QVariant::String, "", ctx->nameOfPip(item), ElementType::PIP);
+            counter++;
+            if (counter == 50) {
+                addProperty(pipsUpItem, QVariant::String, "Warning", "Too many items...", ElementType::NONE);
+                break;
+            }
+        }
+    } else if (type == ElementType::PIP) {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        PipId pip = ctx->getPipByName(c);
+        QtProperty *topItem = addTopLevelProperty("Pip");
+
+        addProperty(topItem, QVariant::String, "Name", ctx->nameOfPip(pip));
+        addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
+        addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
+        addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
+        if (ctx->getConflictingPipWire(pip) != WireId()) {
+            addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingPipWire(pip)),
+                        ElementType::WIRE);
+        } else {
+            addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
+        }
+        addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
+                    ElementType::NET);
+        addProperty(topItem, QVariant::String, "Src Wire", ctx->nameOfWire(ctx->getPipSrcWire(pip)), ElementType::WIRE);
+        addProperty(topItem, QVariant::String, "Dest Wire", ctx->nameOfWire(ctx->getPipDstWire(pip)),
+                    ElementType::WIRE);
+
+        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
+        for (auto &item : ctx->getPipAttrs(pip)) {
+            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx), item.second.c_str());
+        }
+
+        DelayQuad delay = ctx->getPipDelay(pip);
+
+        QtProperty *delayItem = addSubGroup(topItem, "Delay");
+        addProperty(delayItem, QVariant::Double, "Min Rise", delay.minRiseDelay());
+        addProperty(delayItem, QVariant::Double, "Max Rise", delay.maxRiseDelay());
+        addProperty(delayItem, QVariant::Double, "Min Fall", delay.minFallDelay());
+        addProperty(delayItem, QVariant::Double, "Max Fall", delay.maxFallDelay());
+    } else if (type == ElementType::NET) {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        NetInfo *net = ctx->nets.at(c[0]).get();
+
+        QtProperty *topItem = addTopLevelProperty("Net");
+
+        addProperty(topItem, QVariant::String, "Name", net->name.c_str(ctx));
+
+        QtProperty *driverItem = addSubGroup(topItem, "Driver");
+        addProperty(driverItem, QVariant::String, "Port", net->driver.port.c_str(ctx));
+        if (net->driver.cell)
+            addProperty(driverItem, QVariant::String, "Cell", net->driver.cell->name.c_str(ctx), ElementType::CELL);
+        else
+            addProperty(driverItem, QVariant::String, "Cell", "", ElementType::CELL);
+
+        QtProperty *usersItem = addSubGroup(topItem, "Users");
+        for (auto &item : net->users) {
+            QtProperty *portItem = addSubGroup(usersItem, item.port.c_str(ctx));
+
+            addProperty(portItem, QVariant::String, "Port", item.port.c_str(ctx));
+            if (item.cell)
+                addProperty(portItem, QVariant::String, "Cell", item.cell->name.c_str(ctx), ElementType::CELL);
+            else
+                addProperty(portItem, QVariant::String, "Cell", "", ElementType::CELL);
+        }
+
+        QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
+        for (auto &item : net->attrs) {
+            addProperty(attrsItem, QVariant::String, item.first.c_str(ctx),
+                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
+        }
+
+        QtProperty *wiresItem = addSubGroup(topItem, "Wires");
+        for (auto &item : net->wires) {
+            auto name = ctx->nameOfWire(item.first);
+
+            QtProperty *wireItem = addSubGroup(wiresItem, name);
+            addProperty(wireItem, QVariant::String, "Wire", name, ElementType::WIRE);
+
+            if (item.second.pip != PipId())
+                addProperty(wireItem, QVariant::String, "Pip", ctx->nameOfPip(item.second.pip), ElementType::PIP);
+            else
+                addProperty(wireItem, QVariant::String, "Pip", "", ElementType::PIP);
+
+            addProperty(wireItem, QVariant::Int, "Strength", (int)item.second.strength);
+        }
+
+    } else if (type == ElementType::CELL) {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        CellInfo *cell = ctx->cells.at(c[0]).get();
+
+        QtProperty *topItem = addTopLevelProperty("Cell");
+
+        addProperty(topItem, QVariant::String, "Name", cell->name.c_str(ctx));
+        addProperty(topItem, QVariant::String, "Type", cell->type.c_str(ctx));
+        if (cell->bel != BelId())
+            addProperty(topItem, QVariant::String, "Bel", ctx->nameOfBel(cell->bel), ElementType::BEL);
+        else
+            addProperty(topItem, QVariant::String, "Bel", "", ElementType::BEL);
+        addProperty(topItem, QVariant::Int, "Bel strength", int(cell->belStrength));
+
+        QtProperty *cellPortsItem = addSubGroup(topItem, "Ports");
+        for (auto &item : cell->ports) {
+            PortInfo p = item.second;
+
+            QtProperty *portInfoItem = addSubGroup(cellPortsItem, p.name.c_str(ctx));
+            addProperty(portInfoItem, QVariant::String, "Name", p.name.c_str(ctx));
+            addProperty(portInfoItem, QVariant::Int, "Type", int(p.type));
+            if (p.net)
+                addProperty(portInfoItem, QVariant::String, "Net", p.net->name.c_str(ctx), ElementType::NET);
+            else
+                addProperty(portInfoItem, QVariant::String, "Net", "", ElementType::NET);
+        }
+
+        QtProperty *cellAttrItem = addSubGroup(topItem, "Attributes");
+        for (auto &item : cell->attrs) {
+            addProperty(cellAttrItem, QVariant::String, item.first.c_str(ctx),
+                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
+        }
+
+        QtProperty *cellParamsItem = addSubGroup(topItem, "Parameters");
+        for (auto &item : cell->params) {
+            addProperty(cellParamsItem, QVariant::String, item.first.c_str(ctx),
+                        item.second.is_string ? item.second.as_string().c_str() : item.second.to_string().c_str());
+        }
+    }
+}
+
+std::vector<DecalXY> DesignWidget::getDecals(ElementType type, IdStringList value)
+{
+    std::vector<DecalXY> decals;
+    switch (type) {
+    case ElementType::BEL: {
+        BelId bel = ctx->getBelByName(value);
+        if (bel != BelId()) {
+            decals.push_back(ctx->getBelDecal(bel));
+        }
+    } break;
+    case ElementType::WIRE: {
+        WireId wire = ctx->getWireByName(value);
+        if (wire != WireId()) {
+            decals.push_back(ctx->getWireDecal(wire));
+        }
+    } break;
+    case ElementType::PIP: {
+        PipId pip = ctx->getPipByName(value);
+        if (pip != PipId()) {
+            decals.push_back(ctx->getPipDecal(pip));
+        }
+    } break;
+    case ElementType::NET: {
+        NetInfo *net = ctx->nets.at(value[0]).get();
+        for (auto &item : net->wires) {
+            decals.push_back(ctx->getWireDecal(item.first));
+            if (item.second.pip != PipId()) {
+                decals.push_back(ctx->getPipDecal(item.second.pip));
+            }
+        }
+    } break;
+    case ElementType::CELL: {
+        CellInfo *cell = ctx->cells.at(value[0]).get();
+        if (cell->bel != BelId()) {
+            decals.push_back(ctx->getBelDecal(cell->bel));
+        }
+    } break;
+    default:
+        break;
+    }
+    return decals;
+}
+
+void DesignWidget::updateHighlightGroup(QList<TreeModel::Item *> items, int group)
+{
+    const bool shouldClear = items.size() == 1;
+    for (auto item : items) {
+        if (highlightSelected.contains(item)) {
+            if (shouldClear && highlightSelected[item] == group) {
+                highlightSelected.remove(item);
+            } else
+                highlightSelected[item] = group;
+        } else
+            highlightSelected.insert(item, group);
+    }
+    std::vector<DecalXY> decals[8];
+
+    for (auto it : highlightSelected.toStdMap()) {
+        std::vector<DecalXY> d = getDecals(it.first->type(), it.first->id());
+        std::move(d.begin(), d.end(), std::back_inserter(decals[it.second]));
+    }
+    for (int i = 0; i < 8; i++)
+        Q_EMIT highlight(decals[i], i);
+}
+
+void DesignWidget::prepareMenuProperty(const QPoint &pos)
+{
+    QTreeWidget *tree = propertyEditor->treeWidget();
+    QList<TreeModel::Item *> items;
+    for (auto itemContextMenu : tree->selectedItems()) {
+        QtBrowserItem *browserItem = propertyEditor->itemToBrowserItem(itemContextMenu);
+        if (!browserItem)
+            continue;
+        QtProperty *selectedProperty = browserItem->property();
+        ElementType type = getElementTypeByName(selectedProperty->propertyId());
+        if (type == ElementType::NONE)
+            continue;
+        IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
+        auto node = getTreeByElementType(type)->nodeForId(value);
+        if (!node)
+            continue;
+        items.append(*node);
+    }
+    int selectedIndex = -1;
+    if (items.size() == 1) {
+        TreeModel::Item *item = items.at(0);
+        if (highlightSelected.contains(item))
+            selectedIndex = highlightSelected[item];
+    }
+
+    QMenu menu(this);
+    QAction *selectAction = new QAction("&Select", this);
+    connect(selectAction, &QAction::triggered, this, [this, items] {
+        std::vector<DecalXY> decals;
+        for (auto clickItem : items) {
+            std::vector<DecalXY> d = getDecals(clickItem->type(), clickItem->id());
+            std::move(d.begin(), d.end(), std::back_inserter(decals));
+        }
+        Q_EMIT selected(decals, false);
+    });
+    menu.addAction(selectAction);
+
+    QMenu *subMenu = menu.addMenu("Highlight");
+    QActionGroup *group = new QActionGroup(this);
+    group->setExclusive(true);
+    for (int i = 0; i < 8; i++) {
+        QPixmap pixmap(32, 32);
+        pixmap.fill(QColor(highlightColors[i]));
+        QAction *action = new QAction(QIcon(pixmap), ("Group " + std::to_string(i)).c_str(), this);
+        action->setCheckable(true);
+        subMenu->addAction(action);
+        group->addAction(action);
+        if (selectedIndex == i)
+            action->setChecked(true);
+        connect(action, &QAction::triggered, this, [this, i, items] { updateHighlightGroup(items, i); });
+    }
+    menu.exec(tree->mapToGlobal(pos));
+}
+
+void DesignWidget::prepareMenuTree(int num, const QPoint &pos)
+{
+    int selectedIndex = -1;
+
+    if (selectionModel[num]->selectedIndexes().size() == 0)
+        return;
+
+    QList<TreeModel::Item *> items;
+    for (int i = 0; i <= getIndexByElementType(ElementType::GROUP); i++) {
+        for (auto index : selectionModel[i]->selectedIndexes()) {
+            TreeModel::Item *item = treeModel[i]->nodeFromIndex(index);
+            items.append(item);
+        }
+    }
+    if (items.size() == 1) {
+        TreeModel::Item *item = items.at(0);
+        if (highlightSelected.contains(item))
+            selectedIndex = highlightSelected[item];
+    }
+    QMenu menu(this);
+    QMenu *subMenu = menu.addMenu("Highlight");
+    QActionGroup *group = new QActionGroup(this);
+    group->setExclusive(true);
+    for (int i = 0; i < 8; i++) {
+        QPixmap pixmap(32, 32);
+        pixmap.fill(QColor(highlightColors[i]));
+        QAction *action = new QAction(QIcon(pixmap), ("Group " + std::to_string(i)).c_str(), this);
+        action->setCheckable(true);
+        subMenu->addAction(action);
+        group->addAction(action);
+        if (selectedIndex == i)
+            action->setChecked(true);
+        connect(action, &QAction::triggered, this, [this, i, items] { updateHighlightGroup(items, i); });
+    }
+    menu.exec(treeView[num]->mapToGlobal(pos));
+}
+
+void DesignWidget::onItemDoubleClicked(QTreeWidgetItem *item, int column)
+{
+    QtProperty *selectedProperty = propertyEditor->itemToBrowserItem(item)->property();
+    ElementType type = getElementTypeByName(selectedProperty->propertyId());
+    if (type == ElementType::NONE)
+        return;
+
+    IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
+    auto it = getTreeByElementType(type)->nodeForId(value);
+    if (it) {
+        int num = getIndexByElementType(type);
+        clearAllSelectionModels();
+        if (tabWidget->currentIndex() != num)
+            tabWidget->setCurrentIndex(num);
+        selectionModel[num]->setCurrentIndex(getTreeByElementType(type)->indexFromNode(*it),
+                                             QItemSelectionModel::ClearAndSelect);
+    }
+}
+
+void DesignWidget::onDoubleClicked(const QModelIndex &index) { Q_EMIT zoomSelected(); }
+
+void DesignWidget::onSearchInserted()
+{
+    if (currentSearch == searchEdit->text() && currentIndexTab == tabWidget->currentIndex()) {
+        currentIndex++;
+        if (currentIndex >= currentSearchIndexes.size())
+            currentIndex = 0;
+    } else {
+        std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
+        std::lock_guard<std::mutex> lock(ctx->mutex);
+
+        currentSearch = searchEdit->text();
+        currentSearchIndexes = treeModel[tabWidget->currentIndex()]->search(searchEdit->text());
+        currentIndex = 0;
+        currentIndexTab = tabWidget->currentIndex();
+    }
+    if (currentSearchIndexes.size() > 0 && currentIndex < currentSearchIndexes.size())
+        selectionModel[tabWidget->currentIndex()]->setCurrentIndex(currentSearchIndexes.at(currentIndex),
+                                                                   QItemSelectionModel::ClearAndSelect);
+}
+
+void DesignWidget::onHoverIndexChanged(int num, QModelIndex index)
+{
+    if (index.isValid()) {
+        TreeModel::Item *item = treeModel[num]->nodeFromIndex(index);
+        if (item->type() != ElementType::NONE) {
+            std::vector<DecalXY> decals = getDecals(item->type(), item->id());
+            if (decals.size() > 0)
+                Q_EMIT hover(decals.at(0));
+            return;
+        }
+    }
+    Q_EMIT hover(DecalXY());
+}
+
+void DesignWidget::onHoverPropertyChanged(QtBrowserItem *item)
+{
+    if (item != nullptr) {
+        QtProperty *selectedProperty = item->property();
+        ElementType type = getElementTypeByName(selectedProperty->propertyId());
+        if (type != ElementType::NONE) {
+            IdStringList value = IdStringList::parse(ctx, selectedProperty->valueText().toStdString());
+            if (value != IdStringList()) {
+                auto node = getTreeByElementType(type)->nodeForId(value);
+                if (node) {
+                    std::vector<DecalXY> decals = getDecals((*node)->type(), (*node)->id());
+                    if (decals.size() > 0)
+                        Q_EMIT hover(decals.at(0));
+                    return;
+                }
+            }
+        }
+    }
+    Q_EMIT hover(DecalXY());
+}
+NEXTPNR_NAMESPACE_END
diff --git a/gui/designwidget.h b/gui/designwidget.h
index 5efe2b42bb..7d59669e37 100644
--- a/gui/designwidget.h
+++ b/gui/designwidget.h
@@ -1,138 +1,138 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef DESIGNWIDGET_H
-#define DESIGNWIDGET_H
-
-#include <QMouseEvent>
-#include <QTabWidget>
-#include <QTreeView>
-#include <QVariant>
-#include "nextpnr.h"
-#include "qtgroupboxpropertybrowser.h"
-#include "qtpropertymanager.h"
-#include "qttreepropertybrowser.h"
-#include "qtvariantproperty.h"
-#include "treemodel.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class TreeView : public QTreeView
-{
-    Q_OBJECT
-
-  public:
-    explicit TreeView(QWidget *parent = 0);
-    ~TreeView();
-    void mouseMoveEvent(QMouseEvent *event) override;
-    void leaveEvent(QEvent *event) override;
-
-  Q_SIGNALS:
-    void hoverIndexChanged(QModelIndex index);
-
-  private:
-    QModelIndex current;
-};
-
-class DesignWidget : public QWidget
-{
-    Q_OBJECT
-
-  public:
-    explicit DesignWidget(QWidget *parent = 0);
-    ~DesignWidget();
-
-  private:
-    void clearProperties();
-    QtProperty *addTopLevelProperty(const QString &id);
-    QtProperty *addSubGroup(QtProperty *topItem, const QString &name);
-    void addProperty(QtProperty *topItem, int propertyType, const QString &name, QVariant value,
-                     const ElementType &type = ElementType::NONE);
-    QString getElementTypeName(ElementType type);
-    ElementType getElementTypeByName(QString type);
-    TreeModel::Model *getTreeByElementType(ElementType type);
-    int getIndexByElementType(ElementType type);
-    int getElementIndex(ElementType type);
-    void updateButtons();
-    void addToHistory(int tab, QModelIndex item);
-    std::vector<DecalXY> getDecals(ElementType type, IdStringList value);
-    void updateHighlightGroup(QList<TreeModel::Item *> item, int group);
-    void clearAllSelectionModels();
-  Q_SIGNALS:
-    void selected(std::vector<DecalXY> decal, bool keep);
-    void highlight(std::vector<DecalXY> decal, int group);
-    void hover(DecalXY decal);
-    void zoomSelected();
-
-  private Q_SLOTS:
-    void prepareMenuProperty(const QPoint &pos);
-    void prepareMenuTree(int num, const QPoint &pos);
-    void onSelectionChanged(int num, const QItemSelection &selected, const QItemSelection &deselected);
-    void onItemDoubleClicked(QTreeWidgetItem *item, int column);
-    void onDoubleClicked(const QModelIndex &index);
-    void onSearchInserted();
-    void onHoverIndexChanged(int num, QModelIndex index);
-    void onHoverPropertyChanged(QtBrowserItem *item);
-  public Q_SLOTS:
-    void newContext(Context *ctx);
-    void updateTree();
-    void onClickedBel(BelId bel, bool keep);
-    void onClickedWire(WireId wire, bool keep);
-    void onClickedPip(PipId pip, bool keep);
-
-  private:
-    Context *ctx;
-
-    QTabWidget *tabWidget;
-
-    TreeView *treeView[6];
-    QItemSelectionModel *selectionModel[6];
-    TreeModel::Model *treeModel[6];
-    QLineEdit *searchEdit;
-    QtVariantPropertyManager *variantManager;
-    QtVariantPropertyManager *readOnlyManager;
-    QtGroupPropertyManager *groupManager;
-    QtVariantEditorFactory *variantFactory;
-    QtTreePropertyBrowser *propertyEditor;
-
-    QMap<QtProperty *, QString> propertyToId;
-    QMap<QString, QtProperty *> idToProperty;
-
-    std::vector<std::pair<int, QModelIndex>> history;
-    int history_index;
-    bool history_ignore;
-
-    QAction *actionFirst;
-    QAction *actionPrev;
-    QAction *actionNext;
-    QAction *actionLast;
-    QAction *actionClear;
-
-    QColor highlightColors[8];
-    QMap<TreeModel::Item *, int> highlightSelected;
-
-    QString currentSearch;
-    QList<QModelIndex> currentSearchIndexes;
-    int currentIndex;
-    int currentIndexTab;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // DESIGNWIDGET_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef DESIGNWIDGET_H
+#define DESIGNWIDGET_H
+
+#include <QMouseEvent>
+#include <QTabWidget>
+#include <QTreeView>
+#include <QVariant>
+#include "nextpnr.h"
+#include "qtgroupboxpropertybrowser.h"
+#include "qtpropertymanager.h"
+#include "qttreepropertybrowser.h"
+#include "qtvariantproperty.h"
+#include "treemodel.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class TreeView : public QTreeView
+{
+    Q_OBJECT
+
+  public:
+    explicit TreeView(QWidget *parent = 0);
+    ~TreeView();
+    void mouseMoveEvent(QMouseEvent *event) override;
+    void leaveEvent(QEvent *event) override;
+
+  Q_SIGNALS:
+    void hoverIndexChanged(QModelIndex index);
+
+  private:
+    QModelIndex current;
+};
+
+class DesignWidget : public QWidget
+{
+    Q_OBJECT
+
+  public:
+    explicit DesignWidget(QWidget *parent = 0);
+    ~DesignWidget();
+
+  private:
+    void clearProperties();
+    QtProperty *addTopLevelProperty(const QString &id);
+    QtProperty *addSubGroup(QtProperty *topItem, const QString &name);
+    void addProperty(QtProperty *topItem, int propertyType, const QString &name, QVariant value,
+                     const ElementType &type = ElementType::NONE);
+    QString getElementTypeName(ElementType type);
+    ElementType getElementTypeByName(QString type);
+    TreeModel::Model *getTreeByElementType(ElementType type);
+    int getIndexByElementType(ElementType type);
+    int getElementIndex(ElementType type);
+    void updateButtons();
+    void addToHistory(int tab, QModelIndex item);
+    std::vector<DecalXY> getDecals(ElementType type, IdStringList value);
+    void updateHighlightGroup(QList<TreeModel::Item *> item, int group);
+    void clearAllSelectionModels();
+  Q_SIGNALS:
+    void selected(std::vector<DecalXY> decal, bool keep);
+    void highlight(std::vector<DecalXY> decal, int group);
+    void hover(DecalXY decal);
+    void zoomSelected();
+
+  private Q_SLOTS:
+    void prepareMenuProperty(const QPoint &pos);
+    void prepareMenuTree(int num, const QPoint &pos);
+    void onSelectionChanged(int num, const QItemSelection &selected, const QItemSelection &deselected);
+    void onItemDoubleClicked(QTreeWidgetItem *item, int column);
+    void onDoubleClicked(const QModelIndex &index);
+    void onSearchInserted();
+    void onHoverIndexChanged(int num, QModelIndex index);
+    void onHoverPropertyChanged(QtBrowserItem *item);
+  public Q_SLOTS:
+    void newContext(Context *ctx);
+    void updateTree();
+    void onClickedBel(BelId bel, bool keep);
+    void onClickedWire(WireId wire, bool keep);
+    void onClickedPip(PipId pip, bool keep);
+
+  private:
+    Context *ctx;
+
+    QTabWidget *tabWidget;
+
+    TreeView *treeView[6];
+    QItemSelectionModel *selectionModel[6];
+    TreeModel::Model *treeModel[6];
+    QLineEdit *searchEdit;
+    QtVariantPropertyManager *variantManager;
+    QtVariantPropertyManager *readOnlyManager;
+    QtGroupPropertyManager *groupManager;
+    QtVariantEditorFactory *variantFactory;
+    QtTreePropertyBrowser *propertyEditor;
+
+    QMap<QtProperty *, QString> propertyToId;
+    QMap<QString, QtProperty *> idToProperty;
+
+    std::vector<std::pair<int, QModelIndex>> history;
+    int history_index;
+    bool history_ignore;
+
+    QAction *actionFirst;
+    QAction *actionPrev;
+    QAction *actionNext;
+    QAction *actionLast;
+    QAction *actionClear;
+
+    QColor highlightColors[8];
+    QMap<TreeModel::Item *, int> highlightSelected;
+
+    QString currentSearch;
+    QList<QModelIndex> currentSearchIndexes;
+    int currentIndex;
+    int currentIndexTab;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // DESIGNWIDGET_H
diff --git a/gui/ecp5/mainwindow.cc b/gui/ecp5/mainwindow.cc
index 73d4a9891b..fa44426b0d 100644
--- a/gui/ecp5/mainwindow.cc
+++ b/gui/ecp5/mainwindow.cc
@@ -1,166 +1,166 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "mainwindow.h"
-#include <fstream>
-#include "bitstream.h"
-#include "log.h"
-
-#include <QFileDialog>
-#include <QInputDialog>
-#include <QLineEdit>
-
-static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : BaseMainWindow(std::move(context), handler, parent)
-{
-    initMainResource();
-
-    std::string title = "nextpnr-ecp5 - [EMPTY]";
-    setWindowTitle(title.c_str());
-
-    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
-
-    createMenu();
-}
-
-MainWindow::~MainWindow() {}
-
-void MainWindow::newContext(Context *ctx)
-{
-    std::string title = "nextpnr-ecp5 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
-    setWindowTitle(title.c_str());
-}
-
-void MainWindow::createMenu()
-{
-    // Add arch specific actions
-    actionLoadLPF = new QAction("Open LPF", this);
-    actionLoadLPF->setIcon(QIcon(":/icons/resources/open_lpf.png"));
-    actionLoadLPF->setStatusTip("Open LPF file");
-    actionLoadLPF->setEnabled(false);
-    connect(actionLoadLPF, &QAction::triggered, this, &MainWindow::open_lpf);
-
-    actionSaveConfig = new QAction("Save Bitstream", this);
-    actionSaveConfig->setIcon(QIcon(":/icons/resources/save_config.png"));
-    actionSaveConfig->setStatusTip("Save Bitstream config file");
-    actionSaveConfig->setEnabled(false);
-    connect(actionSaveConfig, &QAction::triggered, this, &MainWindow::save_config);
-
-    // Add actions in menus
-    mainActionBar->addSeparator();
-    mainActionBar->addAction(actionLoadLPF);
-    mainActionBar->addAction(actionSaveConfig);
-
-    menuDesign->addSeparator();
-    menuDesign->addAction(actionLoadLPF);
-    menuDesign->addAction(actionSaveConfig);
-}
-
-void MainWindow::new_proj()
-{
-    QMap<QString, int> arch;
-    if (Arch::is_available(ArchArgs::LFE5U_25F))
-        arch.insert("Lattice ECP5 LFE5U-25F", ArchArgs::LFE5U_25F);
-    if (Arch::is_available(ArchArgs::LFE5U_45F))
-        arch.insert("Lattice ECP5 LFE5U-45F", ArchArgs::LFE5U_45F);
-    if (Arch::is_available(ArchArgs::LFE5U_85F))
-        arch.insert("Lattice ECP5 LFE5U-85F", ArchArgs::LFE5U_85F);
-    if (Arch::is_available(ArchArgs::LFE5UM_25F))
-        arch.insert("Lattice ECP5 LFE5UM-25F", ArchArgs::LFE5UM_25F);
-    if (Arch::is_available(ArchArgs::LFE5UM_45F))
-        arch.insert("Lattice ECP5 LFE5UM-45F", ArchArgs::LFE5UM_45F);
-    if (Arch::is_available(ArchArgs::LFE5UM_85F))
-        arch.insert("Lattice ECP5 LFE5UM-85F", ArchArgs::LFE5UM_85F);
-    if (Arch::is_available(ArchArgs::LFE5UM5G_25F))
-        arch.insert("Lattice ECP5 LFE5UM5G-25F", ArchArgs::LFE5UM5G_25F);
-    if (Arch::is_available(ArchArgs::LFE5UM5G_45F))
-        arch.insert("Lattice ECP5 LFE5UM5G-45F", ArchArgs::LFE5UM5G_45F);
-    if (Arch::is_available(ArchArgs::LFE5UM5G_85F))
-        arch.insert("Lattice ECP5 LFE5UM5G-85F", ArchArgs::LFE5UM5G_85F);
-
-    bool ok;
-    QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
-    if (ok && !item.isEmpty()) {
-        ArchArgs chipArgs;
-        chipArgs.type = (ArchArgs::ArchArgsTypes)arch.value(item);
-
-        QStringList packages;
-        for (auto package : Arch::get_supported_packages(chipArgs.type))
-            packages.append(QLatin1String(package.data(), package.size()));
-        QString package = QInputDialog::getItem(this, "Select package", "Package:", packages, 0, false, &ok);
-
-        if (ok && !item.isEmpty()) {
-            handler->clear();
-            currentProj = "";
-            disableActions();
-            chipArgs.package = package.toStdString().c_str();
-            ctx = std::unique_ptr<Context>(new Context(chipArgs));
-            actionLoadJSON->setEnabled(true);
-
-            Q_EMIT contextChanged(ctx.get());
-        }
-    }
-}
-
-void MainWindow::open_lpf()
-{
-    QString fileName = QFileDialog::getOpenFileName(this, QString("Open LPF"), QString(), QString("*.lpf"));
-    if (!fileName.isEmpty()) {
-        std::ifstream in(fileName.toStdString());
-        if (ctx->apply_lpf(fileName.toStdString(), in)) {
-            log("Loading LPF successful.\n");
-            actionPack->setEnabled(true);
-            actionLoadLPF->setEnabled(false);
-        } else {
-            actionLoadLPF->setEnabled(true);
-            log("Loading LPF failed.\n");
-        }
-    }
-}
-
-void MainWindow::save_config()
-{
-    QString fileName = QFileDialog::getSaveFileName(this, QString("Save Bitstream"), QString(), QString("*.config"));
-    if (!fileName.isEmpty()) {
-        std::string fn = fileName.toStdString();
-        disableActions();
-        write_bitstream(ctx.get(), "", fileName.toStdString());
-        log("Saving Bitstream successful.\n");
-    }
-}
-
-void MainWindow::onDisableActions()
-{
-    actionLoadLPF->setEnabled(false);
-    actionSaveConfig->setEnabled(false);
-}
-
-void MainWindow::onUpdateActions()
-{
-    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
-        actionLoadLPF->setEnabled(true);
-    if (ctx->settings.find(ctx->id("route")) != ctx->settings.end())
-        actionSaveConfig->setEnabled(true);
-}
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+#include <fstream>
+#include "bitstream.h"
+#include "log.h"
+
+#include <QFileDialog>
+#include <QInputDialog>
+#include <QLineEdit>
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+
+    std::string title = "nextpnr-ecp5 - [EMPTY]";
+    setWindowTitle(title.c_str());
+
+    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
+
+    createMenu();
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-ecp5 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::createMenu()
+{
+    // Add arch specific actions
+    actionLoadLPF = new QAction("Open LPF", this);
+    actionLoadLPF->setIcon(QIcon(":/icons/resources/open_lpf.png"));
+    actionLoadLPF->setStatusTip("Open LPF file");
+    actionLoadLPF->setEnabled(false);
+    connect(actionLoadLPF, &QAction::triggered, this, &MainWindow::open_lpf);
+
+    actionSaveConfig = new QAction("Save Bitstream", this);
+    actionSaveConfig->setIcon(QIcon(":/icons/resources/save_config.png"));
+    actionSaveConfig->setStatusTip("Save Bitstream config file");
+    actionSaveConfig->setEnabled(false);
+    connect(actionSaveConfig, &QAction::triggered, this, &MainWindow::save_config);
+
+    // Add actions in menus
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionLoadLPF);
+    mainActionBar->addAction(actionSaveConfig);
+
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionLoadLPF);
+    menuDesign->addAction(actionSaveConfig);
+}
+
+void MainWindow::new_proj()
+{
+    QMap<QString, int> arch;
+    if (Arch::is_available(ArchArgs::LFE5U_25F))
+        arch.insert("Lattice ECP5 LFE5U-25F", ArchArgs::LFE5U_25F);
+    if (Arch::is_available(ArchArgs::LFE5U_45F))
+        arch.insert("Lattice ECP5 LFE5U-45F", ArchArgs::LFE5U_45F);
+    if (Arch::is_available(ArchArgs::LFE5U_85F))
+        arch.insert("Lattice ECP5 LFE5U-85F", ArchArgs::LFE5U_85F);
+    if (Arch::is_available(ArchArgs::LFE5UM_25F))
+        arch.insert("Lattice ECP5 LFE5UM-25F", ArchArgs::LFE5UM_25F);
+    if (Arch::is_available(ArchArgs::LFE5UM_45F))
+        arch.insert("Lattice ECP5 LFE5UM-45F", ArchArgs::LFE5UM_45F);
+    if (Arch::is_available(ArchArgs::LFE5UM_85F))
+        arch.insert("Lattice ECP5 LFE5UM-85F", ArchArgs::LFE5UM_85F);
+    if (Arch::is_available(ArchArgs::LFE5UM5G_25F))
+        arch.insert("Lattice ECP5 LFE5UM5G-25F", ArchArgs::LFE5UM5G_25F);
+    if (Arch::is_available(ArchArgs::LFE5UM5G_45F))
+        arch.insert("Lattice ECP5 LFE5UM5G-45F", ArchArgs::LFE5UM5G_45F);
+    if (Arch::is_available(ArchArgs::LFE5UM5G_85F))
+        arch.insert("Lattice ECP5 LFE5UM5G-85F", ArchArgs::LFE5UM5G_85F);
+
+    bool ok;
+    QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
+    if (ok && !item.isEmpty()) {
+        ArchArgs chipArgs;
+        chipArgs.type = (ArchArgs::ArchArgsTypes)arch.value(item);
+
+        QStringList packages;
+        for (auto package : Arch::get_supported_packages(chipArgs.type))
+            packages.append(QLatin1String(package.data(), package.size()));
+        QString package = QInputDialog::getItem(this, "Select package", "Package:", packages, 0, false, &ok);
+
+        if (ok && !item.isEmpty()) {
+            handler->clear();
+            currentProj = "";
+            disableActions();
+            chipArgs.package = package.toStdString().c_str();
+            ctx = std::unique_ptr<Context>(new Context(chipArgs));
+            actionLoadJSON->setEnabled(true);
+
+            Q_EMIT contextChanged(ctx.get());
+        }
+    }
+}
+
+void MainWindow::open_lpf()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open LPF"), QString(), QString("*.lpf"));
+    if (!fileName.isEmpty()) {
+        std::ifstream in(fileName.toStdString());
+        if (ctx->apply_lpf(fileName.toStdString(), in)) {
+            log("Loading LPF successful.\n");
+            actionPack->setEnabled(true);
+            actionLoadLPF->setEnabled(false);
+        } else {
+            actionLoadLPF->setEnabled(true);
+            log("Loading LPF failed.\n");
+        }
+    }
+}
+
+void MainWindow::save_config()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save Bitstream"), QString(), QString("*.config"));
+    if (!fileName.isEmpty()) {
+        std::string fn = fileName.toStdString();
+        disableActions();
+        write_bitstream(ctx.get(), "", fileName.toStdString());
+        log("Saving Bitstream successful.\n");
+    }
+}
+
+void MainWindow::onDisableActions()
+{
+    actionLoadLPF->setEnabled(false);
+    actionSaveConfig->setEnabled(false);
+}
+
+void MainWindow::onUpdateActions()
+{
+    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
+        actionLoadLPF->setEnabled(true);
+    if (ctx->settings.find(ctx->id("route")) != ctx->settings.end())
+        actionSaveConfig->setEnabled(true);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/ecp5/mainwindow.h b/gui/ecp5/mainwindow.h
index 17c694b8a3..20d72c6854 100644
--- a/gui/ecp5/mainwindow.h
+++ b/gui/ecp5/mainwindow.h
@@ -1,55 +1,55 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include "../basewindow.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class MainWindow : public BaseMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~MainWindow();
-
-  public:
-    void createMenu();
-
-  protected:
-    void onDisableActions() override;
-    void onUpdateActions() override;
-
-  protected Q_SLOTS:
-    void new_proj() override;
-    void newContext(Context *ctx);
-    void open_lpf();
-    void save_config();
-
-  private:
-    QAction *actionLoadLPF;
-    QAction *actionSaveConfig;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // MAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected:
+    void onDisableActions() override;
+    void onUpdateActions() override;
+
+  protected Q_SLOTS:
+    void new_proj() override;
+    void newContext(Context *ctx);
+    void open_lpf();
+    void save_config();
+
+  private:
+    QAction *actionLoadLPF;
+    QAction *actionSaveConfig;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/fpga_interchange/mainwindow.cc b/gui/fpga_interchange/mainwindow.cc
index 3483f6c775..c3fba6c392 100644
--- a/gui/fpga_interchange/mainwindow.cc
+++ b/gui/fpga_interchange/mainwindow.cc
@@ -1,50 +1,50 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "mainwindow.h"
-
-#include <QMessageBox>
-#include <cstdlib>
-
-static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : BaseMainWindow(std::move(context), handler, parent)
-{
-    initMainResource();
-    QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-generic");
-    std::exit(1);
-}
-
-MainWindow::~MainWindow() {}
-
-void MainWindow::newContext(Context *ctx)
-{
-    std::string title = "nextpnr-generic - " + ctx->getChipName();
-    setWindowTitle(title.c_str());
-}
-
-void MainWindow::createMenu() {}
-
-void MainWindow::new_proj() {}
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *  Copyright (C) 2021  Symbiflow Authors
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+
+#include <QMessageBox>
+#include <cstdlib>
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+    QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-generic");
+    std::exit(1);
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-generic - " + ctx->getChipName();
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::createMenu() {}
+
+void MainWindow::new_proj() {}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/fpga_interchange/mainwindow.h b/gui/fpga_interchange/mainwindow.h
index 2875cb74b9..9c199c7dc3 100644
--- a/gui/fpga_interchange/mainwindow.h
+++ b/gui/fpga_interchange/mainwindow.h
@@ -1,46 +1,46 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include "../basewindow.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class MainWindow : public BaseMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~MainWindow();
-
-  public:
-    void createMenu();
-
-  protected Q_SLOTS:
-    void new_proj() override;
-    void newContext(Context *ctx);
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // MAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *  Copyright (C) 2021  Symbiflow Authors
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected Q_SLOTS:
+    void new_proj() override;
+    void newContext(Context *ctx);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc
index 54fe6f3e1e..de459a561c 100644
--- a/gui/generic/mainwindow.cc
+++ b/gui/generic/mainwindow.cc
@@ -1,52 +1,52 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "mainwindow.h"
-
-#include <QMessageBox>
-#include <cstdlib>
-
-static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : BaseMainWindow(std::move(context), handler, parent)
-{
-    initMainResource();
-}
-
-MainWindow::~MainWindow() {}
-
-void MainWindow::newContext(Context *ctx)
-{
-    std::string title = "nextpnr-generic - " + ctx->getChipName();
-    setWindowTitle(title.c_str());
-}
-
-void MainWindow::createMenu() {}
-
-void MainWindow::new_proj()
-{
-    QMessageBox::critical(0, "Error",
-                          "Creating a new project not supported in Viaduct mode, please re-start from command line.");
-    std::exit(1);
-}
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+
+#include <QMessageBox>
+#include <cstdlib>
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-generic - " + ctx->getChipName();
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::createMenu() {}
+
+void MainWindow::new_proj()
+{
+    QMessageBox::critical(0, "Error",
+                          "Creating a new project not supported in Viaduct mode, please re-start from command line.");
+    std::exit(1);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/generic/mainwindow.h b/gui/generic/mainwindow.h
index 1e39b63f63..7cdb238b06 100644
--- a/gui/generic/mainwindow.h
+++ b/gui/generic/mainwindow.h
@@ -1,45 +1,45 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include "../basewindow.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class MainWindow : public BaseMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~MainWindow();
-
-  public:
-    void createMenu();
-
-  protected Q_SLOTS:
-    void new_proj() override;
-    void newContext(Context *ctx);
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // MAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected Q_SLOTS:
+    void new_proj() override;
+    void newContext(Context *ctx);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/gowin/mainwindow.cc b/gui/gowin/mainwindow.cc
index c7ba44ab60..195a083d5d 100644
--- a/gui/gowin/mainwindow.cc
+++ b/gui/gowin/mainwindow.cc
@@ -1,103 +1,103 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "mainwindow.h"
-
-#include <QFileDialog>
-#include <QMessageBox>
-#include <cstdlib>
-
-#include "cst.h"
-
-static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : BaseMainWindow(std::move(context), handler, parent)
-{
-    initMainResource();
-    std::string title = "nextpnr-gowin - [EMPTY]";
-    setWindowTitle(title.c_str());
-    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
-    createMenu();
-}
-
-MainWindow::~MainWindow() {}
-
-void MainWindow::newContext(Context *ctx)
-{
-    std::string title = "nextpnr-gowin - " + ctx->getChipName();
-    setWindowTitle(title.c_str());
-}
-
-void MainWindow::load_cst(std::string filename)
-{
-    disableActions();
-    std::ifstream f(filename);
-    if (read_cst(ctx.get(), f)) {
-        log("Loading CST successful.\n");
-        actionPack->setEnabled(true);
-    } else {
-        actionLoadCST->setEnabled(true);
-        log("Loading CST failed.\n");
-    }
-}
-
-void MainWindow::createMenu()
-{
-    actionLoadCST = new QAction("Open CST", this);
-    actionLoadCST->setIcon(QIcon(":/icons/resources/open_cst.png"));
-    actionLoadCST->setStatusTip("Open CST file");
-    actionLoadCST->setEnabled(false);
-    connect(actionLoadCST, &QAction::triggered, this, &MainWindow::open_cst);
-
-    // Add actions in menus
-    mainActionBar->addSeparator();
-    mainActionBar->addAction(actionLoadCST);
-
-    menuDesign->addSeparator();
-    menuDesign->addAction(actionLoadCST);
-}
-
-void MainWindow::new_proj() {}
-
-void MainWindow::open_cst()
-{
-    QString fileName = QFileDialog::getOpenFileName(this, QString("Open CST"), QString(), QString("*.cst"));
-    if (!fileName.isEmpty()) {
-        load_cst(fileName.toStdString());
-    }
-}
-
-void MainWindow::onDisableActions() { actionLoadCST->setEnabled(false); }
-
-void MainWindow::onUpdateActions()
-{
-    if (ctx->settings.find(ctx->id("synth")) != ctx->settings.end()) {
-        actionLoadCST->setEnabled(true);
-    }
-    if (ctx->settings.find(ctx->id("cst")) != ctx->settings.end()) {
-        actionLoadCST->setEnabled(false);
-    }
-    if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
-        actionLoadCST->setEnabled(false);
-    }
-}
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+
+#include <QFileDialog>
+#include <QMessageBox>
+#include <cstdlib>
+
+#include "cst.h"
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+    std::string title = "nextpnr-gowin - [EMPTY]";
+    setWindowTitle(title.c_str());
+    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
+    createMenu();
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-gowin - " + ctx->getChipName();
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::load_cst(std::string filename)
+{
+    disableActions();
+    std::ifstream f(filename);
+    if (read_cst(ctx.get(), f)) {
+        log("Loading CST successful.\n");
+        actionPack->setEnabled(true);
+    } else {
+        actionLoadCST->setEnabled(true);
+        log("Loading CST failed.\n");
+    }
+}
+
+void MainWindow::createMenu()
+{
+    actionLoadCST = new QAction("Open CST", this);
+    actionLoadCST->setIcon(QIcon(":/icons/resources/open_cst.png"));
+    actionLoadCST->setStatusTip("Open CST file");
+    actionLoadCST->setEnabled(false);
+    connect(actionLoadCST, &QAction::triggered, this, &MainWindow::open_cst);
+
+    // Add actions in menus
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionLoadCST);
+
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionLoadCST);
+}
+
+void MainWindow::new_proj() {}
+
+void MainWindow::open_cst()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open CST"), QString(), QString("*.cst"));
+    if (!fileName.isEmpty()) {
+        load_cst(fileName.toStdString());
+    }
+}
+
+void MainWindow::onDisableActions() { actionLoadCST->setEnabled(false); }
+
+void MainWindow::onUpdateActions()
+{
+    if (ctx->settings.find(ctx->id("synth")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(true);
+    }
+    if (ctx->settings.find(ctx->id("cst")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(false);
+    }
+    if (ctx->settings.find(ctx->id("pack")) != ctx->settings.end()) {
+        actionLoadCST->setEnabled(false);
+    }
+}
+NEXTPNR_NAMESPACE_END
diff --git a/gui/gowin/mainwindow.h b/gui/gowin/mainwindow.h
index 0d65ed1c01..4ca901a6ab 100644
--- a/gui/gowin/mainwindow.h
+++ b/gui/gowin/mainwindow.h
@@ -1,57 +1,57 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include "../basewindow.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class MainWindow : public BaseMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~MainWindow();
-
-  public:
-    void createMenu();
-
-  protected:
-    void onDisableActions() override;
-    void onUpdateActions() override;
-
-    void load_cst(std::string filename);
-
-  protected Q_SLOTS:
-    void new_proj() override;
-
-    void open_cst();
-
-    void newContext(Context *ctx);
-
-  private:
-    QAction *actionLoadCST;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // MAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected:
+    void onDisableActions() override;
+    void onUpdateActions() override;
+
+    void load_cst(std::string filename);
+
+  protected Q_SLOTS:
+    void new_proj() override;
+
+    void open_cst();
+
+    void newContext(Context *ctx);
+
+  private:
+    QAction *actionLoadCST;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/ice40/mainwindow.cc b/gui/ice40/mainwindow.cc
index 54d3b50bf3..955e58a4fc 100644
--- a/gui/ice40/mainwindow.cc
+++ b/gui/ice40/mainwindow.cc
@@ -1,182 +1,182 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "mainwindow.h"
-#include <QAction>
-#include <QFileDialog>
-#include <QFileInfo>
-#include <QIcon>
-#include <QInputDialog>
-#include <QLineEdit>
-#include <fstream>
-#include "bitstream.h"
-#include "design_utils.h"
-#include "log.h"
-#include "pcf.h"
-
-static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
-
-NEXTPNR_NAMESPACE_BEGIN
-
-MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
-        : BaseMainWindow(std::move(context), handler, parent)
-{
-    initMainResource();
-
-    std::string title = "nextpnr-ice40 - [EMPTY]";
-    setWindowTitle(title.c_str());
-
-    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
-
-    createMenu();
-}
-
-MainWindow::~MainWindow() {}
-
-void MainWindow::createMenu()
-{
-    // Add arch specific actions
-    actionLoadPCF = new QAction("Open PCF", this);
-    actionLoadPCF->setIcon(QIcon(":/icons/resources/open_pcf.png"));
-    actionLoadPCF->setStatusTip("Open PCF file");
-    actionLoadPCF->setEnabled(false);
-    connect(actionLoadPCF, &QAction::triggered, this, &MainWindow::open_pcf);
-
-    actionSaveAsc = new QAction("Save ASC", this);
-    actionSaveAsc->setIcon(QIcon(":/icons/resources/save_asc.png"));
-    actionSaveAsc->setStatusTip("Save ASC file");
-    actionSaveAsc->setEnabled(false);
-    connect(actionSaveAsc, &QAction::triggered, this, &MainWindow::save_asc);
-
-    // Add actions in menus
-    mainActionBar->addSeparator();
-    mainActionBar->addAction(actionLoadPCF);
-    mainActionBar->addAction(actionSaveAsc);
-
-    menuDesign->addSeparator();
-    menuDesign->addAction(actionLoadPCF);
-    menuDesign->addAction(actionSaveAsc);
-}
-
-void MainWindow::new_proj()
-{
-    QMap<QString, int> arch;
-    if (Arch::is_available(ArchArgs::LP384))
-        arch.insert("Lattice iCE40LP384", ArchArgs::LP384);
-    if (Arch::is_available(ArchArgs::LP1K))
-        arch.insert("Lattice iCE40LP1K", ArchArgs::LP1K);
-    if (Arch::is_available(ArchArgs::HX1K))
-        arch.insert("Lattice iCE40HX1K", ArchArgs::HX1K);
-    if (Arch::is_available(ArchArgs::U1K))
-        arch.insert("Lattice iCE5LP1K", ArchArgs::U1K);
-    if (Arch::is_available(ArchArgs::U2K))
-        arch.insert("Lattice iCE5LP2K", ArchArgs::U2K);
-    if (Arch::is_available(ArchArgs::U4K))
-        arch.insert("Lattice iCE5LP4K", ArchArgs::U4K);
-    if (Arch::is_available(ArchArgs::UP3K))
-        arch.insert("Lattice iCE40UP3K", ArchArgs::UP3K);
-    if (Arch::is_available(ArchArgs::UP5K))
-        arch.insert("Lattice iCE40UP5K", ArchArgs::UP5K);
-    if (Arch::is_available(ArchArgs::LP4K))
-        arch.insert("Lattice iCE40LP4K", ArchArgs::LP4K);
-    if (Arch::is_available(ArchArgs::LP8K))
-        arch.insert("Lattice iCE40LP8K", ArchArgs::LP8K);
-    if (Arch::is_available(ArchArgs::HX4K))
-        arch.insert("Lattice iCE40HX4K", ArchArgs::HX4K);
-    if (Arch::is_available(ArchArgs::HX8K))
-        arch.insert("Lattice iCE40HX8K", ArchArgs::HX8K);
-
-    bool ok;
-    QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
-    if (ok && !item.isEmpty()) {
-        ArchArgs chipArgs;
-        chipArgs.type = (ArchArgs::ArchArgsTypes)arch.value(item);
-
-        QStringList packages;
-        for (auto package : Arch::get_supported_packages(chipArgs.type))
-            packages.append(QLatin1String(package.data(), package.size()));
-        QString package = QInputDialog::getItem(this, "Select package", "Package:", packages, 0, false, &ok);
-
-        if (ok && !item.isEmpty()) {
-            handler->clear();
-            currentProj = "";
-            disableActions();
-            chipArgs.package = package.toStdString().c_str();
-            ctx = std::unique_ptr<Context>(new Context(chipArgs));
-            actionLoadJSON->setEnabled(true);
-
-            Q_EMIT contextChanged(ctx.get());
-        }
-    }
-}
-
-void MainWindow::load_pcf(std::string filename)
-{
-    disableActions();
-    std::ifstream f(filename);
-    if (apply_pcf(ctx.get(), filename, f)) {
-        log("Loading PCF successful.\n");
-        actionPack->setEnabled(true);
-    } else {
-        actionLoadPCF->setEnabled(true);
-        log("Loading PCF failed.\n");
-    }
-}
-
-void MainWindow::newContext(Context *ctx)
-{
-    std::string title = "nextpnr-ice40 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
-    setWindowTitle(title.c_str());
-}
-
-void MainWindow::open_pcf()
-{
-    QString fileName = QFileDialog::getOpenFileName(this, QString("Open PCF"), QString(), QString("*.pcf"));
-    if (!fileName.isEmpty()) {
-        load_pcf(fileName.toStdString());
-    }
-}
-
-void MainWindow::save_asc()
-{
-    QString fileName = QFileDialog::getSaveFileName(this, QString("Save ASC"), QString(), QString("*.asc"));
-    if (!fileName.isEmpty()) {
-        std::string fn = fileName.toStdString();
-        disableActions();
-        std::ofstream f(fn);
-        write_asc(ctx.get(), f);
-        log("Saving ASC successful.\n");
-    }
-}
-
-void MainWindow::onDisableActions()
-{
-    actionLoadPCF->setEnabled(false);
-    actionSaveAsc->setEnabled(false);
-}
-
-void MainWindow::onUpdateActions()
-{
-    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
-        actionLoadPCF->setEnabled(true);
-    if (ctx->settings.find(ctx->id("route")) != ctx->settings.end())
-        actionSaveAsc->setEnabled(true);
-}
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "mainwindow.h"
+#include <QAction>
+#include <QFileDialog>
+#include <QFileInfo>
+#include <QIcon>
+#include <QInputDialog>
+#include <QLineEdit>
+#include <fstream>
+#include "bitstream.h"
+#include "design_utils.h"
+#include "log.h"
+#include "pcf.h"
+
+static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
+
+NEXTPNR_NAMESPACE_BEGIN
+
+MainWindow::MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent)
+        : BaseMainWindow(std::move(context), handler, parent)
+{
+    initMainResource();
+
+    std::string title = "nextpnr-ice40 - [EMPTY]";
+    setWindowTitle(title.c_str());
+
+    connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
+
+    createMenu();
+}
+
+MainWindow::~MainWindow() {}
+
+void MainWindow::createMenu()
+{
+    // Add arch specific actions
+    actionLoadPCF = new QAction("Open PCF", this);
+    actionLoadPCF->setIcon(QIcon(":/icons/resources/open_pcf.png"));
+    actionLoadPCF->setStatusTip("Open PCF file");
+    actionLoadPCF->setEnabled(false);
+    connect(actionLoadPCF, &QAction::triggered, this, &MainWindow::open_pcf);
+
+    actionSaveAsc = new QAction("Save ASC", this);
+    actionSaveAsc->setIcon(QIcon(":/icons/resources/save_asc.png"));
+    actionSaveAsc->setStatusTip("Save ASC file");
+    actionSaveAsc->setEnabled(false);
+    connect(actionSaveAsc, &QAction::triggered, this, &MainWindow::save_asc);
+
+    // Add actions in menus
+    mainActionBar->addSeparator();
+    mainActionBar->addAction(actionLoadPCF);
+    mainActionBar->addAction(actionSaveAsc);
+
+    menuDesign->addSeparator();
+    menuDesign->addAction(actionLoadPCF);
+    menuDesign->addAction(actionSaveAsc);
+}
+
+void MainWindow::new_proj()
+{
+    QMap<QString, int> arch;
+    if (Arch::is_available(ArchArgs::LP384))
+        arch.insert("Lattice iCE40LP384", ArchArgs::LP384);
+    if (Arch::is_available(ArchArgs::LP1K))
+        arch.insert("Lattice iCE40LP1K", ArchArgs::LP1K);
+    if (Arch::is_available(ArchArgs::HX1K))
+        arch.insert("Lattice iCE40HX1K", ArchArgs::HX1K);
+    if (Arch::is_available(ArchArgs::U1K))
+        arch.insert("Lattice iCE5LP1K", ArchArgs::U1K);
+    if (Arch::is_available(ArchArgs::U2K))
+        arch.insert("Lattice iCE5LP2K", ArchArgs::U2K);
+    if (Arch::is_available(ArchArgs::U4K))
+        arch.insert("Lattice iCE5LP4K", ArchArgs::U4K);
+    if (Arch::is_available(ArchArgs::UP3K))
+        arch.insert("Lattice iCE40UP3K", ArchArgs::UP3K);
+    if (Arch::is_available(ArchArgs::UP5K))
+        arch.insert("Lattice iCE40UP5K", ArchArgs::UP5K);
+    if (Arch::is_available(ArchArgs::LP4K))
+        arch.insert("Lattice iCE40LP4K", ArchArgs::LP4K);
+    if (Arch::is_available(ArchArgs::LP8K))
+        arch.insert("Lattice iCE40LP8K", ArchArgs::LP8K);
+    if (Arch::is_available(ArchArgs::HX4K))
+        arch.insert("Lattice iCE40HX4K", ArchArgs::HX4K);
+    if (Arch::is_available(ArchArgs::HX8K))
+        arch.insert("Lattice iCE40HX8K", ArchArgs::HX8K);
+
+    bool ok;
+    QString item = QInputDialog::getItem(this, "Select new context", "Chip:", arch.keys(), 0, false, &ok);
+    if (ok && !item.isEmpty()) {
+        ArchArgs chipArgs;
+        chipArgs.type = (ArchArgs::ArchArgsTypes)arch.value(item);
+
+        QStringList packages;
+        for (auto package : Arch::get_supported_packages(chipArgs.type))
+            packages.append(QLatin1String(package.data(), package.size()));
+        QString package = QInputDialog::getItem(this, "Select package", "Package:", packages, 0, false, &ok);
+
+        if (ok && !item.isEmpty()) {
+            handler->clear();
+            currentProj = "";
+            disableActions();
+            chipArgs.package = package.toStdString().c_str();
+            ctx = std::unique_ptr<Context>(new Context(chipArgs));
+            actionLoadJSON->setEnabled(true);
+
+            Q_EMIT contextChanged(ctx.get());
+        }
+    }
+}
+
+void MainWindow::load_pcf(std::string filename)
+{
+    disableActions();
+    std::ifstream f(filename);
+    if (apply_pcf(ctx.get(), filename, f)) {
+        log("Loading PCF successful.\n");
+        actionPack->setEnabled(true);
+    } else {
+        actionLoadPCF->setEnabled(true);
+        log("Loading PCF failed.\n");
+    }
+}
+
+void MainWindow::newContext(Context *ctx)
+{
+    std::string title = "nextpnr-ice40 - " + ctx->getChipName() + " ( " + ctx->archArgs().package + " )";
+    setWindowTitle(title.c_str());
+}
+
+void MainWindow::open_pcf()
+{
+    QString fileName = QFileDialog::getOpenFileName(this, QString("Open PCF"), QString(), QString("*.pcf"));
+    if (!fileName.isEmpty()) {
+        load_pcf(fileName.toStdString());
+    }
+}
+
+void MainWindow::save_asc()
+{
+    QString fileName = QFileDialog::getSaveFileName(this, QString("Save ASC"), QString(), QString("*.asc"));
+    if (!fileName.isEmpty()) {
+        std::string fn = fileName.toStdString();
+        disableActions();
+        std::ofstream f(fn);
+        write_asc(ctx.get(), f);
+        log("Saving ASC successful.\n");
+    }
+}
+
+void MainWindow::onDisableActions()
+{
+    actionLoadPCF->setEnabled(false);
+    actionSaveAsc->setEnabled(false);
+}
+
+void MainWindow::onUpdateActions()
+{
+    if (ctx->settings.find(ctx->id("pack")) == ctx->settings.end())
+        actionLoadPCF->setEnabled(true);
+    if (ctx->settings.find(ctx->id("route")) != ctx->settings.end())
+        actionSaveAsc->setEnabled(true);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/ice40/mainwindow.h b/gui/ice40/mainwindow.h
index 16069e2df1..ee5946a3d5 100644
--- a/gui/ice40/mainwindow.h
+++ b/gui/ice40/mainwindow.h
@@ -1,59 +1,59 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef MAINWINDOW_H
-#define MAINWINDOW_H
-
-#include "../basewindow.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class MainWindow : public BaseMainWindow
-{
-    Q_OBJECT
-
-  public:
-    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
-    virtual ~MainWindow();
-
-  public:
-    void createMenu();
-
-  protected:
-    void load_pcf(std::string filename);
-
-    void onDisableActions() override;
-    void onUpdateActions() override;
-
-  protected Q_SLOTS:
-    void new_proj() override;
-
-    void open_pcf();
-    void save_asc();
-
-    void newContext(Context *ctx);
-
-  private:
-    QAction *actionLoadPCF;
-    QAction *actionSaveAsc;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // MAINWINDOW_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef MAINWINDOW_H
+#define MAINWINDOW_H
+
+#include "../basewindow.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class MainWindow : public BaseMainWindow
+{
+    Q_OBJECT
+
+  public:
+    explicit MainWindow(std::unique_ptr<Context> context, CommandHandler *handler, QWidget *parent = 0);
+    virtual ~MainWindow();
+
+  public:
+    void createMenu();
+
+  protected:
+    void load_pcf(std::string filename);
+
+    void onDisableActions() override;
+    void onUpdateActions() override;
+
+  protected Q_SLOTS:
+    void new_proj() override;
+
+    void open_pcf();
+    void save_asc();
+
+    void newContext(Context *ctx);
+
+  private:
+    QAction *actionLoadPCF;
+    QAction *actionSaveAsc;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // MAINWINDOW_H
diff --git a/gui/pythontab.cc b/gui/pythontab.cc
index c1008d07d4..36eab4716c 100644
--- a/gui/pythontab.cc
+++ b/gui/pythontab.cc
@@ -1,119 +1,119 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "pythontab.h"
-#include <QGridLayout>
-#include "pybindings.h"
-#include "pyinterpreter.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-const QString PythonTab::PROMPT = ">>> ";
-const QString PythonTab::MULTILINE_PROMPT = "... ";
-
-PythonTab::PythonTab(QWidget *parent) : QWidget(parent), initialized(false)
-{
-    QFont f("unexistent");
-    f.setStyleHint(QFont::Monospace);
-
-    // Add text area for Python output and input line
-    console = new PythonConsole();
-    console->setMinimumHeight(100);
-    console->setReadOnly(true);
-    console->setTextInteractionFlags(Qt::TextSelectableByMouse | Qt::TextSelectableByKeyboard);
-    console->setFont(f);
-
-    console->setContextMenuPolicy(Qt::CustomContextMenu);
-    QAction *clearAction = new QAction("Clear &buffer", this);
-    clearAction->setStatusTip("Clears display buffer");
-    connect(clearAction, &QAction::triggered, this, &PythonTab::clearBuffer);
-    contextMenu = console->createStandardContextMenu();
-    contextMenu->addSeparator();
-    contextMenu->addAction(clearAction);
-    connect(console, &PythonConsole::customContextMenuRequested, this, &PythonTab::showContextMenu);
-
-    lineEdit = new LineEditor(&parseHelper);
-    lineEdit->setMinimumHeight(30);
-    lineEdit->setMaximumHeight(30);
-    lineEdit->setFont(f);
-    lineEdit->setPlaceholderText(PythonTab::PROMPT);
-    connect(lineEdit, &LineEditor::textLineInserted, this, &PythonTab::editLineReturnPressed);
-
-    QGridLayout *mainLayout = new QGridLayout();
-    mainLayout->addWidget(console, 0, 0);
-    mainLayout->addWidget(lineEdit, 1, 0);
-    setLayout(mainLayout);
-
-    parseHelper.subscribe(console);
-
-    prompt = PythonTab::PROMPT;
-}
-
-PythonTab::~PythonTab()
-{
-    if (initialized) {
-        pyinterpreter_finalize();
-        deinit_python();
-    }
-}
-
-void PythonTab::editLineReturnPressed(QString text)
-{
-    console->displayString(prompt + text + "\n");
-
-    parseHelper.process(text.toStdString());
-
-    if (parseHelper.buffered())
-        prompt = PythonTab::MULTILINE_PROMPT;
-    else
-        prompt = PythonTab::PROMPT;
-
-    lineEdit->setPlaceholderText(prompt);
-}
-
-void PythonTab::newContext(Context *ctx)
-{
-    if (initialized) {
-        pyinterpreter_finalize();
-        deinit_python();
-    }
-    console->clear();
-
-    pyinterpreter_preinit();
-    init_python("nextpnr");
-    pyinterpreter_initialize();
-    pyinterpreter_aquire();
-    python_export_global("ctx", ctx);
-    pyinterpreter_release();
-
-    initialized = true;
-
-    QString version = QString("Python %1 on %2\n").arg(Py_GetVersion(), Py_GetPlatform());
-    console->displayString(version);
-}
-
-void PythonTab::showContextMenu(const QPoint &pt) { contextMenu->exec(mapToGlobal(pt)); }
-
-void PythonTab::clearBuffer() { console->clear(); }
-
-void PythonTab::info(std::string str) { console->displayString(str.c_str()); }
-
-void PythonTab::execute_python(std::string filename) { console->execute_python(filename); }
-
-NEXTPNR_NAMESPACE_END
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "pythontab.h"
+#include <QGridLayout>
+#include "pybindings.h"
+#include "pyinterpreter.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const QString PythonTab::PROMPT = ">>> ";
+const QString PythonTab::MULTILINE_PROMPT = "... ";
+
+PythonTab::PythonTab(QWidget *parent) : QWidget(parent), initialized(false)
+{
+    QFont f("unexistent");
+    f.setStyleHint(QFont::Monospace);
+
+    // Add text area for Python output and input line
+    console = new PythonConsole();
+    console->setMinimumHeight(100);
+    console->setReadOnly(true);
+    console->setTextInteractionFlags(Qt::TextSelectableByMouse | Qt::TextSelectableByKeyboard);
+    console->setFont(f);
+
+    console->setContextMenuPolicy(Qt::CustomContextMenu);
+    QAction *clearAction = new QAction("Clear &buffer", this);
+    clearAction->setStatusTip("Clears display buffer");
+    connect(clearAction, &QAction::triggered, this, &PythonTab::clearBuffer);
+    contextMenu = console->createStandardContextMenu();
+    contextMenu->addSeparator();
+    contextMenu->addAction(clearAction);
+    connect(console, &PythonConsole::customContextMenuRequested, this, &PythonTab::showContextMenu);
+
+    lineEdit = new LineEditor(&parseHelper);
+    lineEdit->setMinimumHeight(30);
+    lineEdit->setMaximumHeight(30);
+    lineEdit->setFont(f);
+    lineEdit->setPlaceholderText(PythonTab::PROMPT);
+    connect(lineEdit, &LineEditor::textLineInserted, this, &PythonTab::editLineReturnPressed);
+
+    QGridLayout *mainLayout = new QGridLayout();
+    mainLayout->addWidget(console, 0, 0);
+    mainLayout->addWidget(lineEdit, 1, 0);
+    setLayout(mainLayout);
+
+    parseHelper.subscribe(console);
+
+    prompt = PythonTab::PROMPT;
+}
+
+PythonTab::~PythonTab()
+{
+    if (initialized) {
+        pyinterpreter_finalize();
+        deinit_python();
+    }
+}
+
+void PythonTab::editLineReturnPressed(QString text)
+{
+    console->displayString(prompt + text + "\n");
+
+    parseHelper.process(text.toStdString());
+
+    if (parseHelper.buffered())
+        prompt = PythonTab::MULTILINE_PROMPT;
+    else
+        prompt = PythonTab::PROMPT;
+
+    lineEdit->setPlaceholderText(prompt);
+}
+
+void PythonTab::newContext(Context *ctx)
+{
+    if (initialized) {
+        pyinterpreter_finalize();
+        deinit_python();
+    }
+    console->clear();
+
+    pyinterpreter_preinit();
+    init_python("nextpnr");
+    pyinterpreter_initialize();
+    pyinterpreter_aquire();
+    python_export_global("ctx", ctx);
+    pyinterpreter_release();
+
+    initialized = true;
+
+    QString version = QString("Python %1 on %2\n").arg(Py_GetVersion(), Py_GetPlatform());
+    console->displayString(version);
+}
+
+void PythonTab::showContextMenu(const QPoint &pt) { contextMenu->exec(mapToGlobal(pt)); }
+
+void PythonTab::clearBuffer() { console->clear(); }
+
+void PythonTab::info(std::string str) { console->displayString(str.c_str()); }
+
+void PythonTab::execute_python(std::string filename) { console->execute_python(filename); }
+
+NEXTPNR_NAMESPACE_END
diff --git a/gui/pythontab.h b/gui/pythontab.h
index 0ab9b94e2c..1ee2dc5e45 100644
--- a/gui/pythontab.h
+++ b/gui/pythontab.h
@@ -1,64 +1,64 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef PYTHONTAB_H
-#define PYTHONTAB_H
-
-#include <QLineEdit>
-#include <QMenu>
-#include <QPlainTextEdit>
-#include "ParseHelper.h"
-#include "line_editor.h"
-#include "nextpnr.h"
-#include "pyconsole.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-class PythonTab : public QWidget
-{
-    Q_OBJECT
-
-  public:
-    explicit PythonTab(QWidget *parent = 0);
-    ~PythonTab();
-
-  private Q_SLOTS:
-    void showContextMenu(const QPoint &pt);
-    void editLineReturnPressed(QString text);
-  public Q_SLOTS:
-    void newContext(Context *ctx);
-    void info(std::string str);
-    void clearBuffer();
-    void execute_python(std::string filename);
-
-  private:
-    PythonConsole *console;
-    LineEditor *lineEdit;
-    QMenu *contextMenu;
-    bool initialized;
-    ParseHelper parseHelper;
-    QString prompt;
-
-    static const QString PROMPT;
-    static const QString MULTILINE_PROMPT;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif // PYTHONTAB_H
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef PYTHONTAB_H
+#define PYTHONTAB_H
+
+#include <QLineEdit>
+#include <QMenu>
+#include <QPlainTextEdit>
+#include "ParseHelper.h"
+#include "line_editor.h"
+#include "nextpnr.h"
+#include "pyconsole.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+class PythonTab : public QWidget
+{
+    Q_OBJECT
+
+  public:
+    explicit PythonTab(QWidget *parent = 0);
+    ~PythonTab();
+
+  private Q_SLOTS:
+    void showContextMenu(const QPoint &pt);
+    void editLineReturnPressed(QString text);
+  public Q_SLOTS:
+    void newContext(Context *ctx);
+    void info(std::string str);
+    void clearBuffer();
+    void execute_python(std::string filename);
+
+  private:
+    PythonConsole *console;
+    LineEditor *lineEdit;
+    QMenu *contextMenu;
+    bool initialized;
+    ParseHelper parseHelper;
+    QString prompt;
+
+    static const QString PROMPT;
+    static const QString MULTILINE_PROMPT;
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif // PYTHONTAB_H

From f2c280feda3ea0c54de96cbea31304ce0cb32b40 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 3 Oct 2023 21:11:40 +1000
Subject: [PATCH 527/712] gowin: Himbaechel. Initial BSRAM support

Only pROM/pROMX9 for now

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      | 23 +++++++
 himbaechel/uarch/gowin/gowin.cc          |  6 ++
 himbaechel/uarch/gowin/gowin.h           |  5 ++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 50 ++++++++++++++-
 himbaechel/uarch/gowin/pack.cc           | 80 +++++++++++++++++++++++-
 5 files changed, 160 insertions(+), 4 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 57938b0a4f..df333f718a 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -885,6 +885,27 @@ X(DIC)
 X(DID)
 X(WRE)
 
+// BSRAM
+X(BSRAM_SUBTYPE)
+X(BIT_WIDTH)
+X(ROM)
+X(SP)
+X(SPX9)
+X(pROM)
+X(pROMX9)
+X(BSRAM)
+X(OCE)
+X(OCEA)
+X(OCEB)
+X(CEA)
+X(CEB)
+X(RESETA)
+X(RESETB)
+X(WREA)
+X(WREB)
+X(CLKA)
+X(CLKB)
+
 // IOB types
 X(IBUF)
 X(OBUF)
@@ -1064,6 +1085,8 @@ X(BOTTOM_IO_PORT_A)
 X(BOTTOM_IO_PORT_B)
 X(IOLOGIC_DUMMY)
 
+// 
+
 // wire types
 X(GLOBAL_CLK)
 X(TILE_CLK)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index ed2c3fcc29..920d86facf 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -266,6 +266,9 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
     if (type_is_iologic(cell_type)) {
         return id_IOLOGIC;
     }
+    if (type_is_bsram(cell_type)) {
+        return id_BSRAM;
+    }
     if (cell_type == id_GOWIN_GND) {
         return id_GND;
     }
@@ -293,6 +296,9 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
     if (bel_type == id_IOLOGIC) {
         return type_is_iologic(cell_type);
     }
+    if (bel_type == id_BSRAM) {
+        return type_is_bsram(cell_type);
+    }
     if (bel_type == id_GND) {
         return cell_type == id_GOWIN_GND;
     }
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index f92049a5a5..842bf34d41 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -39,6 +39,10 @@ inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
 
+// Return true if a cell is a SSRAM
+inline bool type_is_bsram(IdString cell_type) { return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM); }
+inline bool is_bsram(const CellInfo *cell) { return type_is_bsram(cell->type); }
+
 // ==========================================
 // extra data in the chip db
 // ==========================================
@@ -89,6 +93,7 @@ enum
     OSER16_Z = 73,
 
     BUFG_Z = 74, // : 81 reserve just in case
+    BSRAM_Z = 100,
 
     OSC_Z = 274,
     PLL_Z = 275,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index be507f384e..f5373644c1 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -33,6 +33,7 @@
 OSER16_Z   = 73
 
 BUFG_Z  = 74 # : 81 reserve just in case
+BSRAM_Z = 100
 
 OSC_Z   = 274
 PLL_Z   = 275
@@ -561,9 +562,49 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
         tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
         tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
 
-    tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
-    tt.add_bel_pin(ff, f"CE",  "CE2", PinType.INPUT)
-    tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
+    tt.add_bel_pin(ff, "CLK", "CLK2", PinType.INPUT)
+    tt.add_bel_pin(ff, "CE",  "CE2", PinType.INPUT)
+    tt.add_bel_pin(ff, "WRE", "LSR2", PinType.INPUT)
+    return tt
+
+# BSRAM
+_bsram_inputs = {'CLK', 'OCE', 'CE', 'RESET', 'WRE'}
+def create_bsram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
+    typename = "BSRAM"
+    tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
+    tt = chip.create_tile_type(tiletype)
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
+    portmap = db.grid[y][x].bels['BSRAM'].portmap
+    bsram = tt.create_bel("BSRAM", "BSRAM", z = BSRAM_Z)
+
+    def add_port_wire(tt, bel, name, wire_type = "BSRAM_I", port_type = PinType.INPUT):
+        wire = portmap[name]
+        if not tt.has_wire(wire):
+            if name.startswith('CLK'):
+                tt.create_wire(wire, "TILE_CLK")
+            else:
+                tt.create_wire(wire, wire_type)
+        tt.add_bel_pin(bel, name, wire, port_type)
+
+    for sfx in {'', 'A', 'B'}:
+        for inp in _bsram_inputs:
+            add_port_wire(tt, bsram, f"{inp}{sfx}")
+        for idx in range(3):
+            add_port_wire(tt, bsram, f"BLKSEL{sfx}{idx}")
+        for idx in range(14):
+            add_port_wire(tt, bsram, f"AD{sfx}{idx}")
+        for idx in range(18):
+            add_port_wire(tt, bsram, f"DI{sfx}{idx}")
+            add_port_wire(tt, bsram, f"DO{sfx}{idx}", "BSRAM_O", PinType.OUTPUT)
+        if not sfx:
+            for idx in range(18, 36):
+                add_port_wire(tt, bsram, f"DI{idx}")
+                add_port_wire(tt, bsram, f"DO{idx}", "BSRAM_O", PinType.OUTPUT)
+
+    tdesc.tiletype = tiletype
     return tt
 
 # PLL main tile
@@ -687,6 +728,7 @@ def main():
     io_tiletypes = db.tile_types['I']
     ssram_tiletypes = db.tile_types['M']
     pll_tiletypes = db.tile_types['P']
+    bsram_tiletypes = db.tile_types['B']
 
     # Setup tile grid
     for x in range(X):
@@ -704,6 +746,8 @@ def main():
                 create_tiletype(create_io_tiletype, ch, db, x, y, ttyp)
             elif ttyp in pll_tiletypes:
                 create_tiletype(create_pll_tiletype, ch, db, x, y, ttyp)
+            elif ttyp in bsram_tiletypes:
+                create_tiletype(create_bsram_tiletype, ch, db, x, y, ttyp)
             else:
                 create_tiletype(create_null_tiletype, ch, db, x, y, ttyp)
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 621c7fff8f..78799401ea 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1191,7 +1191,6 @@ struct GowinPacker
     // ===================================
     // SSRAM cluster
     // ===================================
-    // create ALU filler block
     std::unique_ptr<CellInfo> ssram_make_lut(Context *ctx, CellInfo *ci, int index)
     {
         IdString name_id = ctx->idf("%s_LUT%d", ci->name.c_str(ctx), index);
@@ -1273,6 +1272,82 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // Block RAM
+    // ===================================
+    void pack_ROM(CellInfo *ci)
+    {
+        // use block 111
+        ci->setParam(ctx->id("BLK_SEL"), Property(7, 32));
+        if (ci->type == id_pROM) {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
+        } else {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+        }
+
+        NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+        NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+        for (int i = 0; i < 3; ++i) {
+            IdString port = ctx->idf("BLKSEL%d", i);
+            ci->addInput(port);
+            ci->connectPort(port, vcc_net);
+            port = ctx->idf("BLKSELB%d", i);
+            ci->addInput(port);
+            ci->connectPort(port, vcc_net);
+        }
+        // use port B
+        ci->renamePort(id_CLK, id_CLKB);
+        ci->renamePort(id_OCE, id_OCEB);
+        ci->renamePort(id_CE, id_CEB);
+        ci->renamePort(id_RESET, id_RESETB);
+        ci->addInput(id_WRE);
+        ci->connectPort(id_WRE, vss_net);
+        ci->addInput(id_WREB);
+        ci->connectPort(id_WREB, vss_net);
+
+        if (!ci->params.count(id_BIT_WIDTH)) {
+            ci->setParam(id_BIT_WIDTH, Property(32, 32));
+        }
+        int bit_width = ci->params[id_BIT_WIDTH].as_int64();
+        if (bit_width == 32 || bit_width == 36) {
+            log_error("Bit width %d is not supported\n", bit_width);
+        }
+        for (int i = 0; i < 14; ++i) {
+            ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADB%d", i));
+        }
+        int out_num = (bit_width == 9 || bit_width == 18) ? 36 : 32;
+        for (int i = 0, j = 18; i < out_num; ++i, ++j) {
+            if (((i + 1) % 9) == 0 && bit_width == 16) {
+                ++j;
+            }
+            ci->renamePort(ctx->idf("DO[%d]", i), ctx->idf("DO%d", j % 36));
+        }
+    }
+
+    void pack_bsram(void)
+    {
+        log_info("Pack BSRAMs...\n");
+
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+
+            if (is_bsram(ci)) {
+                if (ctx->verbose) {
+                    log_info(" pack %s\n", ci->type.c_str(ctx));
+                }
+                switch (ci->type.hash()) {
+                case ID_pROM: /* fallthrough */
+                case ID_pROMX9:
+                    pack_ROM(ci);
+                    ci->type = id_ROM;
+                    break;
+                default:
+                    log_error("Unsupported BSRAM type '%s'\n", ci->type.c_str(ctx));
+                }
+            }
+        }
+    }
+
     // ===================================
     // Global set/reset
     // ===================================
@@ -1397,6 +1472,9 @@ struct GowinPacker
         pack_ram16sdp4();
         ctx->check();
 
+        pack_bsram();
+        ctx->check();
+
         pack_buffered_nets();
 
         ctx->fixupHierarchy();

From 90d4863dd43cdeeefec3848e35f0d87ce43100f9 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 20 Nov 2023 12:27:56 +1000
Subject: [PATCH 528/712] gowin: Himbaechel. Add GW1NZ-1 BSRAM.

The following primitives are implemented for the GW1NZ-1 chip:

* pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9   - read only memory - (bitwidth: 9, 18, 36).
* SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
* DPB      - dual port        - (bitwidth: 16).
* DPX9B    - dual port        - (bitwidth: 18).
* SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9     - single port      - (bitwidth: 9, 18, 36).

Also:
 - The creation of databases for GW1NS-2 has been removed - this was not
   planned to be supported in Himbaechel from the very beginning and
   even examples were not created in apicula for this chip due to the
   lack of boards with it on sale.
 - It is temporarily prohibited to connect DFFs and LUTs into clusters
   because for some reason this prevents the creation of images on lower
   chips (placer cannot find the placement), although without these
   clusters the images are quite working. Requires further research.
 - Added creation of ALU with mode 0 - addition. Such an element is not
   generated by Yosys, but it is a favorite vendor element and its
   support here greatly simplifies the compilation of vendor netlists.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/CMakeLists.txt    |   2 +-
 himbaechel/uarch/gowin/constids.inc      |   9 +
 himbaechel/uarch/gowin/gowin.h           |   6 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |   2 +-
 himbaechel/uarch/gowin/gowin_utils.h     |   3 +
 himbaechel/uarch/gowin/pack.cc           | 203 +++++++++++++++++++++--
 6 files changed, 205 insertions(+), 20 deletions(-)

diff --git a/himbaechel/uarch/gowin/CMakeLists.txt b/himbaechel/uarch/gowin/CMakeLists.txt
index 99eba6332a..c45628be97 100644
--- a/himbaechel/uarch/gowin/CMakeLists.txt
+++ b/himbaechel/uarch/gowin/CMakeLists.txt
@@ -3,7 +3,7 @@ cmake_minimum_required(VERSION 3.5)
 project(himbaechel-gowin-chipdb NONE)
 
 find_package(Python3 3.5 REQUIRED COMPONENTS Interpreter)
-set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1NS-2 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
+set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C)
 set(HIMBAECHEL_GOWIN_DEVICES "" CACHE STRING
     "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
 if(HIMBAECHEL_GOWIN_DEVICES STREQUAL "all")
diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index df333f718a..178e625b7e 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -685,6 +685,7 @@ X(IOBIS)
 X(IOBJS)
 
 // long wires
+X(LONGWIRE)
 X(BUFS)
 X(BUFS0)
 X(BUFS1)
@@ -888,9 +889,17 @@ X(WRE)
 // BSRAM
 X(BSRAM_SUBTYPE)
 X(BIT_WIDTH)
+X(BIT_WIDTH_0)
+X(BIT_WIDTH_1)
 X(ROM)
+X(DP)
+X(DPB)
+X(DPX9B)
 X(SP)
 X(SPX9)
+X(SDP)
+X(SDPB)
+X(SDPX9B)
 X(pROM)
 X(pROMX9)
 X(BSRAM)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 842bf34d41..3e8a3ec6fc 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -40,7 +40,11 @@ inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
 
 // Return true if a cell is a SSRAM
-inline bool type_is_bsram(IdString cell_type) { return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM); }
+inline bool type_is_bsram(IdString cell_type)
+{
+    return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM, id_SDP, id_SDPB, id_SDPX9B, id_DP, id_DPB,
+                        id_DPX9B);
+}
 inline bool is_bsram(const CellInfo *cell) { return type_is_bsram(cell->type); }
 
 // ==========================================
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index f5373644c1..533928b3ea 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -728,7 +728,7 @@ def main():
     io_tiletypes = db.tile_types['I']
     ssram_tiletypes = db.tile_types['M']
     pll_tiletypes = db.tile_types['P']
-    bsram_tiletypes = db.tile_types['B']
+    bsram_tiletypes = db.tile_types.get('B', set())
 
     # Setup tile grid
     for x in range(X):
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index b88e9b7ac8..3dbb701079 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -35,6 +35,9 @@ struct GowinUtils
     bool have_bottom_io_cnds(void);
     IdString get_bottom_io_wire_a_net(int8_t condition);
     IdString get_bottom_io_wire_b_net(int8_t condition);
+
+    // wires
+    inline bool is_wire_type_default(IdString wire_type) { return wire_type == IdString(); }
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 78799401ea..b3080793f9 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1023,6 +1023,8 @@ struct GowinPacker
             return cin_ci;
         }
         // CIN from logic
+        cin_ci->addInput(id_I0);
+        cin_ci->connectPort(id_I0, ctx->nets.at(ctx->id("$PACKER_GND")).get());
         cin_ci->addInput(id_I1);
         cin_ci->addInput(id_I3);
         cin_ci->connectPort(id_I1, cin_net);
@@ -1113,6 +1115,12 @@ struct GowinPacker
                         ci->constr_x = alu_chain_len / 6;
                         ci->constr_y = 0;
                         ci->constr_z = alu_chain_len % 6;
+                        // XXX mode 0 - ADD
+                        if (ci->params[id_ALU_MODE].as_int64() == 0) {
+                            ci->renamePort(id_I3, id_I2);
+                            ci->renamePort(id_I0, id_I3);
+                            ci->renamePort(id_I2, id_I0);
+                        }
                         // XXX I2 is pin C which must be set to 1 for all ALU modes except MUL
                         // we use only mode 2 ADDSUB so create and connect this pin
                         ci->addInput(id_I2);
@@ -1184,7 +1192,7 @@ struct GowinPacker
                                          {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
                                          {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
 
-        int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
+        int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 0);
         log_info("Constrained %d LUTFF pairs.\n", lutffs);
     }
 
@@ -1275,9 +1283,20 @@ struct GowinPacker
     // ===================================
     // Block RAM
     // ===================================
+    void bsram_rename_ports(CellInfo *ci, int bit_width, char const *from, char const *to, int offset = 0)
+    {
+        int num = (bit_width == 9 || bit_width == 18 || bit_width == 36) ? 36 : 32;
+        for (int i = 0, j = offset; i < num; ++i, ++j) {
+            if (((i + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) {
+                ++j;
+            }
+            ci->renamePort(ctx->idf(from, i), ctx->idf(to, offset ? j % 36 : j));
+        }
+    }
+
     void pack_ROM(CellInfo *ci)
     {
-        // use block 111
+        // XXX use block 111
         ci->setParam(ctx->id("BLK_SEL"), Property(7, 32));
         if (ci->type == id_pROM) {
             ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
@@ -1295,11 +1314,7 @@ struct GowinPacker
             ci->addInput(port);
             ci->connectPort(port, vcc_net);
         }
-        // use port B
-        ci->renamePort(id_CLK, id_CLKB);
-        ci->renamePort(id_OCE, id_OCEB);
-        ci->renamePort(id_CE, id_CEB);
-        ci->renamePort(id_RESET, id_RESETB);
+
         ci->addInput(id_WRE);
         ci->connectPort(id_WRE, vss_net);
         ci->addInput(id_WREB);
@@ -1308,20 +1323,158 @@ struct GowinPacker
         if (!ci->params.count(id_BIT_WIDTH)) {
             ci->setParam(id_BIT_WIDTH, Property(32, 32));
         }
+
         int bit_width = ci->params[id_BIT_WIDTH].as_int64();
         if (bit_width == 32 || bit_width == 36) {
-            log_error("Bit width %d is not supported\n", bit_width);
+            ci->copyPortTo(id_CLK, ci, id_CLKB);
+            ci->copyPortTo(id_CE, ci, id_CEB);
+            ci->copyPortTo(id_OCE, ci, id_OCEB);
+            ci->copyPortTo(id_RESET, ci, id_RESETB);
+
+            for (int i = 0; i < 14; ++i) {
+                ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
+                ci->copyPortTo(ctx->idf("ADA%d", i), ci, ctx->idf("ADB%d", i));
+            }
+            bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
+        } else {
+            // use port B
+            ci->renamePort(id_CLK, id_CLKB);
+            ci->renamePort(id_OCE, id_OCEB);
+            ci->renamePort(id_CE, id_CEB);
+            ci->renamePort(id_RESET, id_RESETB);
+
+            ci->addInput(id_CEA);
+            ci->connectPort(id_CEA, vss_net);
+            for (int i = 0; i < 14; ++i) {
+                ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADB%d", i));
+            }
+            bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d", 18);
+        }
+    }
+
+    void pack_SDPB(CellInfo *ci)
+    {
+        if (ci->type == id_SDPB) {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
+        } else {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
         }
+
+        NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+        NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+
         for (int i = 0; i < 14; ++i) {
-            ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADB%d", i));
+            ci->renamePort(ctx->idf("ADA[%d]", i), ctx->idf("ADA%d", i));
+            ci->renamePort(ctx->idf("ADB[%d]", i), ctx->idf("ADB%d", i));
         }
-        int out_num = (bit_width == 9 || bit_width == 18) ? 36 : 32;
-        for (int i = 0, j = 18; i < out_num; ++i, ++j) {
-            if (((i + 1) % 9) == 0 && bit_width == 16) {
-                ++j;
+
+        for (int i = 0; i < 3; ++i) {
+            ci->renamePort(ctx->idf("BLKSELA[%d]", i), ctx->idf("BLKSELA%d", i));
+            ci->renamePort(ctx->idf("BLKSELB[%d]", i), ctx->idf("BLKSELB%d", i));
+        }
+
+        ci->copyPortTo(id_OCE, ci, id_OCEB);
+
+        // Port A
+        ci->addInput(id_WRE);
+        ci->connectPort(id_WRE, vcc_net);
+
+        if (!ci->params.count(id_BIT_WIDTH_0)) {
+            ci->setParam(id_BIT_WIDTH_0, Property(32, 32));
+        }
+
+        int bit_width = ci->params[id_BIT_WIDTH_0].as_int64();
+        bsram_rename_ports(ci, bit_width, "DI[%d]", "DI%d");
+
+        // Port B
+        ci->addInput(id_WREB);
+        if (!ci->params.count(id_BIT_WIDTH_1)) {
+            ci->setParam(id_BIT_WIDTH_1, Property(32, 32));
+        }
+        bit_width = ci->params[id_BIT_WIDTH_1].as_int64();
+        if (bit_width == 32 || bit_width == 36) {
+            ci->connectPort(id_WREB, vcc_net);
+            bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
+        } else {
+            ci->connectPort(id_WREB, vss_net);
+            bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d", 18);
+        }
+    }
+
+    void pack_DPB(CellInfo *ci)
+    {
+        if (ci->type == id_DPB) {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
+        } else {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+        }
+
+        for (int i = 0; i < 14; ++i) {
+            ci->renamePort(ctx->idf("ADA[%d]", i), ctx->idf("ADA%d", i));
+            ci->renamePort(ctx->idf("ADB[%d]", i), ctx->idf("ADB%d", i));
+        }
+
+        for (int i = 0; i < 3; ++i) {
+            ci->renamePort(ctx->idf("BLKSELA[%d]", i), ctx->idf("BLKSELA%d", i));
+            ci->renamePort(ctx->idf("BLKSELB[%d]", i), ctx->idf("BLKSELB%d", i));
+        }
+
+        if (!ci->params.count(id_BIT_WIDTH_0)) {
+            ci->setParam(id_BIT_WIDTH_0, Property(16, 32));
+        }
+        int bit_width = ci->params[id_BIT_WIDTH_0].as_int64();
+        if (bit_width == 32 || bit_width == 36) {
+            log_error("Bit width %d is not supported\n", bit_width);
+        }
+        bsram_rename_ports(ci, bit_width, "DIA[%d]", "DIA%d");
+        bsram_rename_ports(ci, bit_width, "DOA[%d]", "DOA%d");
+
+        if (!ci->params.count(id_BIT_WIDTH_1)) {
+            ci->setParam(id_BIT_WIDTH_1, Property(16, 32));
+        }
+        bit_width = ci->params[id_BIT_WIDTH_1].as_int64();
+        if (bit_width == 32 || bit_width == 36) {
+            log_error("Bit width %d is not supported\n", bit_width);
+        }
+        bsram_rename_ports(ci, bit_width, "DIB[%d]", "DIB%d");
+        bsram_rename_ports(ci, bit_width, "DOB[%d]", "DOB%d");
+    }
+
+    void pack_SP(CellInfo *ci)
+    {
+        if (ci->type == id_SP) {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
+        } else {
+            ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+        }
+
+        NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+        for (int i = 0; i < 3; ++i) {
+            ci->renamePort(ctx->idf("BLKSEL[%d]", i), ctx->idf("BLKSEL%d", i));
+            ci->copyPortTo(ctx->idf("BLKSEL%d", i), ci, ctx->idf("BLKSELB%d", i));
+        }
+
+        if (!ci->params.count(id_BIT_WIDTH)) {
+            ci->setParam(id_BIT_WIDTH, Property(32, 32));
+        }
+        int bit_width = ci->params[id_BIT_WIDTH].as_int64();
+        for (int i = 0; i < 14; ++i) {
+            ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("AD%d", i));
+            if (bit_width == 32 || bit_width == 36) {
+                ci->copyPortTo(ctx->idf("AD%d", i), ci, ctx->idf("ADB%d", i));
             }
-            ci->renamePort(ctx->idf("DO[%d]", i), ctx->idf("DO%d", j % 36));
         }
+        if (bit_width == 32 || bit_width == 36) {
+            ci->copyPortTo(id_CLK, ci, id_CLKB);
+            ci->copyPortTo(id_OCE, ci, id_OCEB);
+            ci->copyPortTo(id_CE, ci, id_CEB);
+            ci->copyPortTo(id_RESET, ci, id_RESETB);
+            ci->copyPortTo(id_WRE, ci, id_WREB);
+            ci->disconnectPort(ctx->id("ADB4"));
+            ci->connectPort(ctx->id("ADB4"), vcc_net);
+        }
+        bsram_rename_ports(ci, bit_width, "DI[%d]", "DI%d");
+        bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
     }
 
     void pack_bsram(void)
@@ -1336,11 +1489,26 @@ struct GowinPacker
                     log_info(" pack %s\n", ci->type.c_str(ctx));
                 }
                 switch (ci->type.hash()) {
-                case ID_pROM: /* fallthrough */
-                case ID_pROMX9:
+                case ID_pROMX9: /* fallthrough */
+                case ID_pROM:
                     pack_ROM(ci);
                     ci->type = id_ROM;
                     break;
+                case ID_SDPX9B: /* fallthrough */
+                case ID_SDPB:
+                    pack_SDPB(ci);
+                    ci->type = id_SDP;
+                    break;
+                case ID_DPX9B: /* fallthrough */
+                case ID_DPB:
+                    pack_DPB(ci);
+                    ci->type = id_DP;
+                    break;
+                case ID_SPX9: /* fallthrough */
+                case ID_SP:
+                    pack_SP(ci);
+                    ci->type = id_SP;
+                    break;
                 default:
                     log_error("Unsupported BSRAM type '%s'\n", ci->type.c_str(ctx));
                 }
@@ -1463,7 +1631,8 @@ struct GowinPacker
         pack_alus();
         ctx->check();
 
-        constrain_lutffs();
+        // XXX Leads to the impossibility of placement on lower models.
+        // constrain_lutffs();
         ctx->check();
 
         pack_pll();

From c13b34f20e7b8cdcd8b2cfa06e0f3c9446a2066d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 26 Nov 2023 20:51:16 +1000
Subject: [PATCH 529/712] gowin: Himbaechel. Add BSRAM for all chips.

    The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   4 +
 himbaechel/uarch/gowin/gowin.h           |   5 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  15 ++-
 himbaechel/uarch/gowin/gowin_utils.cc    |  13 ++
 himbaechel/uarch/gowin/gowin_utils.h     |   6 +
 himbaechel/uarch/gowin/pack.cc           | 145 +++++++++++++++++------
 6 files changed, 149 insertions(+), 39 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 178e625b7e..70f0d9896b 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1022,6 +1022,9 @@ X(CLKOUTP)
 X(CLKOUTD)
 X(CLKOUTD3)
 X(LOCK)
+X(AD)
+X(DI)
+X(DO)
 
 // PLL parameters
 X(CLKOUTPS)
@@ -1133,3 +1136,4 @@ X(HCLK_OUT3)
 X(BUFG)
 X(CLOCK)
 
+
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 3e8a3ec6fc..79fc4ea7cc 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -39,7 +39,7 @@ inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
 inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
 
-// Return true if a cell is a SSRAM
+// Return true if a cell is a BSRAM
 inline bool type_is_bsram(IdString cell_type)
 {
     return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM, id_SDP, id_SDPB, id_SDPX9B, id_DP, id_DPB,
@@ -70,8 +70,11 @@ NPNR_PACKED_STRUCT(struct Bottom_io_POD {
 });
 
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
+    int32_t chip_flags;
     Bottom_io_POD bottom_io;
     RelSlice<IdString> diff_io_types;
+    // chip flags
+    static constexpr int32_t HAS_SP32 = 0;
 });
 
 } // namespace
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 533928b3ea..413801f4da 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -14,6 +14,9 @@
 # Bel flags
 BEL_FLAG_SIMPLE_IO = 0x100
 
+# Chip flags
+CHIP_HAS_SP32 = 0x1
+
 # Z of the bels
 # sync with C++ part!
 LUT0_Z  = 0       # z(DFFx) = z(LUTx) + 1
@@ -86,6 +89,7 @@ def serialise(self, context: str, bba: BBAWriter):
 @dataclass
 class ChipExtraData(BBAStruct):
     strs: StringPool
+    flags: int
     bottom_io: BottomIO
     diff_io_types: list[IdString] = field(default_factory = list)
 
@@ -105,6 +109,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
             bba.u32(diff_io_type.index)
 
     def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.flags)
         self.bottom_io.serialise(f"{context}_bottom_io", bba)
         bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
 
@@ -691,8 +696,8 @@ def ioloc_to_tile_bel(ioloc):
             pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
 
 # Extra chip data
-def create_extra_data(chip: Chip, db: chipdb):
-    chip.extra_data = ChipExtraData(chip.strs, None)
+def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
+    chip.extra_data = ChipExtraData(chip.strs, chip_flags, None)
     chip.extra_data.create_bottom_io()
     for net_a, net_b in db.bottom_io[2]:
         chip.extra_data.add_bottom_io_cnd(net_a, net_b)
@@ -710,6 +715,10 @@ def main():
     with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
         db = pickle.load(f)
 
+    chip_flags = 0;
+    if device not in {"GW1NS-4", "GW1N-9"}:
+        chip_flags &= CHIP_HAS_SP32;
+
     X = db.cols;
     Y = db.rows;
 
@@ -753,7 +762,7 @@ def main():
 
     # Create nodes between tiles
     create_nodes(ch, db)
-    create_extra_data(ch, db)
+    create_extra_data(ch, db, chip_flags)
     ch.write_bba(args.output)
 if __name__ == '__main__':
     main()
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 16b39d474f..e19c64c884 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -91,4 +91,17 @@ IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
     const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
     return IdString(extra->bottom_io.conditions[condition].wire_b_net);
 }
+
+bool GowinUtils::have_SP32(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
+}
+
+std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
+{
+    NPNR_ASSERT(!ctx->cells.count(name));
+    return std::make_unique<CellInfo>(ctx, name, type);
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 3dbb701079..5d2c6571df 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -38,6 +38,12 @@ struct GowinUtils
 
     // wires
     inline bool is_wire_type_default(IdString wire_type) { return wire_type == IdString(); }
+
+    // chip dependent
+    bool have_SP32(void);
+
+    // make cell but do not include it in the list of chip cells.
+    std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index b3080793f9..5b0cc18383 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -118,7 +118,7 @@ struct GowinPacker
                     log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
                               ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
                 for (const auto &attr : ci.attrs) {
-                    i->driver.cell->attrs[attr.first] = attr.second;
+                    i->driver.cell->setAttr(attr.first, attr.second);
                 }
             }
             NetInfo *o = ci.getPort(id_O);
@@ -128,7 +128,7 @@ struct GowinPacker
                         log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
                                   ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
                     for (const auto &attr : ci.attrs) {
-                        usr.cell->attrs[attr.first] = attr.second;
+                        usr.cell->setAttr(attr.first, attr.second);
                     }
                     // network/port attributes that can be set in the
                     // restriction file and that need to be transferred to real
@@ -150,7 +150,7 @@ struct GowinPacker
                     log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
                               ctx->nameOf(io->driver.cell), ctx->nameOf(io->driver.port));
                 for (const auto &attr : ci.attrs) {
-                    io->driver.cell->attrs[attr.first] = attr.second;
+                    io->driver.cell->setAttr(attr.first, attr.second);
                 }
             }
             ci.disconnectPort(id_I);
@@ -1011,13 +1011,13 @@ struct GowinPacker
         cin_ci->connectPort(id_COUT, cout_net);
 
         if (cin_net->name == ctx->id("$PACKER_GND")) {
-            cin_ci->params[id_ALU_MODE] = std::string("C2L");
+            cin_ci->setParam(id_ALU_MODE, std::string("C2L"));
             cin_ci->addInput(id_I2);
             cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             return cin_ci;
         }
         if (cin_net->name == ctx->id("$PACKER_VCC")) {
-            cin_ci->params[id_ALU_MODE] = std::string("ONE2C");
+            cin_ci->setParam(id_ALU_MODE, std::string("ONE2C"));
             cin_ci->addInput(id_I2);
             cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
             return cin_ci;
@@ -1031,7 +1031,7 @@ struct GowinPacker
         cin_ci->connectPort(id_I3, cin_net);
         cin_ci->addInput(id_I2);
         cin_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
-        cin_ci->params[id_ALU_MODE] = std::string("0"); // ADD
+        cin_ci->setParam(id_ALU_MODE, std::string("0")); // ADD
         return cin_ci;
     }
 
@@ -1054,7 +1054,7 @@ struct GowinPacker
         cout_ci->addInput(id_I2);
         cout_ci->connectPort(id_I2, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
 
-        cout_ci->params[id_ALU_MODE] = std::string("C2L");
+        cout_ci->setParam(id_ALU_MODE, std::string("C2L"));
         return cout_ci;
     }
 
@@ -1065,7 +1065,7 @@ struct GowinPacker
         IdString name_id = ctx->id(name);
 
         auto dummy_ci = std::make_unique<CellInfo>(ctx, name_id, id_ALU);
-        dummy_ci->params[id_ALU_MODE] = std::string("C2L");
+        dummy_ci->setParam(id_ALU_MODE, std::string("C2L"));
         return dummy_ci;
     }
 
@@ -1116,7 +1116,7 @@ struct GowinPacker
                         ci->constr_y = 0;
                         ci->constr_z = alu_chain_len % 6;
                         // XXX mode 0 - ADD
-                        if (ci->params[id_ALU_MODE].as_int64() == 0) {
+                        if (ci->params.at(id_ALU_MODE).as_int64() == 0) {
                             ci->renamePort(id_I3, id_I2);
                             ci->renamePort(id_I0, id_I3);
                             ci->renamePort(id_I2, id_I0);
@@ -1210,9 +1210,9 @@ struct GowinPacker
         }
         IdString init_name = ctx->idf("INIT_%d", index);
         if (ci->params.count(init_name)) {
-            lut_ci->params[id_INIT] = ci->params.at(init_name);
+            lut_ci->setParam(id_INIT, ci->params.at(init_name));
         } else {
-            lut_ci->params[id_INIT] = std::string("1111111111111111");
+            lut_ci->setParam(id_INIT, std::string("1111111111111111"));
         }
         return lut_ci;
     }
@@ -1296,12 +1296,14 @@ struct GowinPacker
 
     void pack_ROM(CellInfo *ci)
     {
+        int default_bw = 32;
         // XXX use block 111
         ci->setParam(ctx->id("BLK_SEL"), Property(7, 32));
         if (ci->type == id_pROM) {
             ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
         } else {
             ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+            default_bw = 36;
         }
 
         NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
@@ -1321,10 +1323,10 @@ struct GowinPacker
         ci->connectPort(id_WREB, vss_net);
 
         if (!ci->params.count(id_BIT_WIDTH)) {
-            ci->setParam(id_BIT_WIDTH, Property(32, 32));
+            ci->setParam(id_BIT_WIDTH, Property(default_bw, 32));
         }
 
-        int bit_width = ci->params[id_BIT_WIDTH].as_int64();
+        int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
         if (bit_width == 32 || bit_width == 36) {
             ci->copyPortTo(id_CLK, ci, id_CLKB);
             ci->copyPortTo(id_CE, ci, id_CEB);
@@ -1354,10 +1356,12 @@ struct GowinPacker
 
     void pack_SDPB(CellInfo *ci)
     {
+        int default_bw = 32;
         if (ci->type == id_SDPB) {
             ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
         } else {
             ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+            default_bw = 36;
         }
 
         NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
@@ -1380,18 +1384,18 @@ struct GowinPacker
         ci->connectPort(id_WRE, vcc_net);
 
         if (!ci->params.count(id_BIT_WIDTH_0)) {
-            ci->setParam(id_BIT_WIDTH_0, Property(32, 32));
+            ci->setParam(id_BIT_WIDTH_0, Property(default_bw, 32));
         }
 
-        int bit_width = ci->params[id_BIT_WIDTH_0].as_int64();
+        int bit_width = ci->params.at(id_BIT_WIDTH_0).as_int64();
         bsram_rename_ports(ci, bit_width, "DI[%d]", "DI%d");
 
         // Port B
         ci->addInput(id_WREB);
         if (!ci->params.count(id_BIT_WIDTH_1)) {
-            ci->setParam(id_BIT_WIDTH_1, Property(32, 32));
+            ci->setParam(id_BIT_WIDTH_1, Property(default_bw, 32));
         }
-        bit_width = ci->params[id_BIT_WIDTH_1].as_int64();
+        bit_width = ci->params.at(id_BIT_WIDTH_1).as_int64();
         if (bit_width == 32 || bit_width == 36) {
             ci->connectPort(id_WREB, vcc_net);
             bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
@@ -1403,10 +1407,12 @@ struct GowinPacker
 
     void pack_DPB(CellInfo *ci)
     {
+        int default_bw = 16;
         if (ci->type == id_DPB) {
             ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
         } else {
             ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+            default_bw = 18;
         }
 
         for (int i = 0; i < 14; ++i) {
@@ -1420,44 +1426,109 @@ struct GowinPacker
         }
 
         if (!ci->params.count(id_BIT_WIDTH_0)) {
-            ci->setParam(id_BIT_WIDTH_0, Property(16, 32));
-        }
-        int bit_width = ci->params[id_BIT_WIDTH_0].as_int64();
-        if (bit_width == 32 || bit_width == 36) {
-            log_error("Bit width %d is not supported\n", bit_width);
+            ci->setParam(id_BIT_WIDTH_0, Property(default_bw, 32));
         }
+        int bit_width = ci->params.at(id_BIT_WIDTH_0).as_int64();
         bsram_rename_ports(ci, bit_width, "DIA[%d]", "DIA%d");
         bsram_rename_ports(ci, bit_width, "DOA[%d]", "DOA%d");
 
         if (!ci->params.count(id_BIT_WIDTH_1)) {
-            ci->setParam(id_BIT_WIDTH_1, Property(16, 32));
-        }
-        bit_width = ci->params[id_BIT_WIDTH_1].as_int64();
-        if (bit_width == 32 || bit_width == 36) {
-            log_error("Bit width %d is not supported\n", bit_width);
+            ci->setParam(id_BIT_WIDTH_1, Property(default_bw, 32));
         }
+        bit_width = ci->params.at(id_BIT_WIDTH_1).as_int64();
         bsram_rename_ports(ci, bit_width, "DIB[%d]", "DIB%d");
         bsram_rename_ports(ci, bit_width, "DOB[%d]", "DOB%d");
     }
 
-    void pack_SP(CellInfo *ci)
+    void divide_sp(CellInfo *ci, std::vector<std::unique_ptr<CellInfo>> &new_cells)
+    {
+        int bw = ci->params.at(id_BIT_WIDTH).as_int64();
+        NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+        NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+
+        IdString cell_type = id_SP;
+        if (bw == 36) {
+            cell_type = id_SPX9;
+        }
+        IdString name = ctx->idf("%s_AUX", ctx->nameOf(ci));
+
+        auto sp_cell = gwu.create_cell(name, cell_type);
+        CellInfo *sp = sp_cell.get();
+
+        ci->copyPortTo(id_CLK, sp, id_CLK);
+        ci->copyPortTo(id_OCE, sp, id_OCE);
+        ci->copyPortTo(id_CE, sp, id_CE);
+        ci->copyPortTo(id_RESET, sp, id_RESET);
+        ci->copyPortTo(id_WRE, sp, id_WRE);
+
+        // XXX Separate "byte enable" port
+        ci->movePortTo(ctx->id("AD[2]"), sp, ctx->id("AD0"));
+        ci->movePortTo(ctx->id("AD[3]"), sp, ctx->id("AD1"));
+        ci->connectPort(ctx->id("AD[2]"), vss_net);
+        ci->connectPort(ctx->id("AD[3]"), vss_net);
+
+        sp->addInput(ctx->id("AD2"));
+        sp->connectPort(ctx->id("AD2"), vss_net);
+        sp->addInput(ctx->id("AD3"));
+        sp->connectPort(ctx->id("AD3"), vss_net);
+
+        ci->disconnectPort(ctx->id("AD[4]"));
+        ci->connectPort(ctx->id("AD[4]"), vss_net);
+        sp->addInput(ctx->id("AD4"));
+        sp->connectPort(ctx->id("AD4"), vcc_net);
+
+        ci->copyPortBusTo(id_AD, 5, true, sp, id_AD, 5, false, 14 - 5 + 1);
+
+        sp->params = ci->params;
+        sp->setAttr(id_BSRAM_SUBTYPE, ci->attrs.at(id_BSRAM_SUBTYPE));
+
+        if (bw == 32) {
+            ci->setParam(id_BIT_WIDTH, Property(16, 32));
+            sp->setParam(id_BIT_WIDTH, Property(16, 32));
+            ci->movePortBusTo(id_DI, 16, true, sp, id_DI, 0, false, 16);
+            ci->movePortBusTo(id_DO, 16, true, sp, id_DO, 0, false, 16);
+        } else {
+            ci->setParam(id_BIT_WIDTH, Property(18, 32));
+            sp->setParam(id_BIT_WIDTH, Property(18, 32));
+            ci->movePortBusTo(id_DI, 18, true, sp, id_DI, 0, false, 18);
+            ci->movePortBusTo(id_DO, 18, true, sp, id_DO, 0, false, 18);
+        }
+        ci->copyPortBusTo(ctx->id("BLKSEL"), 0, true, sp, ctx->id("BLKSEL"), 0, false, 3);
+
+        new_cells.push_back(std::move(sp_cell));
+    }
+
+    void pack_SP(CellInfo *ci, std::vector<std::unique_ptr<CellInfo>> &new_cells)
     {
+        int default_bw = 32;
         if (ci->type == id_SP) {
             ci->setAttr(id_BSRAM_SUBTYPE, Property(""));
         } else {
             ci->setAttr(id_BSRAM_SUBTYPE, Property("X9"));
+            default_bw = 36;
+        }
+        if (!ci->params.count(id_BIT_WIDTH)) {
+            ci->setParam(id_BIT_WIDTH, Property(default_bw, 32));
+        }
+
+        int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
+        // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
+        // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
+        // SP/SPX9s, which occupy two BSRAMs.
+        // So divide it here
+        if ((bit_width == 32 || bit_width == 36) && !gwu.have_SP32()) {
+            divide_sp(ci, new_cells);
+            bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
         }
 
         NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
         for (int i = 0; i < 3; ++i) {
             ci->renamePort(ctx->idf("BLKSEL[%d]", i), ctx->idf("BLKSEL%d", i));
-            ci->copyPortTo(ctx->idf("BLKSEL%d", i), ci, ctx->idf("BLKSELB%d", i));
+            if (bit_width == 32 || bit_width == 36) {
+                ci->copyPortTo(ctx->idf("BLKSEL%d", i), ci, ctx->idf("BLKSELB%d", i));
+            }
         }
 
-        if (!ci->params.count(id_BIT_WIDTH)) {
-            ci->setParam(id_BIT_WIDTH, Property(32, 32));
-        }
-        int bit_width = ci->params[id_BIT_WIDTH].as_int64();
         for (int i = 0; i < 14; ++i) {
             ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("AD%d", i));
             if (bit_width == 32 || bit_width == 36) {
@@ -1479,11 +1550,11 @@ struct GowinPacker
 
     void pack_bsram(void)
     {
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
         log_info("Pack BSRAMs...\n");
 
         for (auto &cell : ctx->cells) {
             auto ci = cell.second.get();
-
             if (is_bsram(ci)) {
                 if (ctx->verbose) {
                     log_info(" pack %s\n", ci->type.c_str(ctx));
@@ -1506,7 +1577,7 @@ struct GowinPacker
                     break;
                 case ID_SPX9: /* fallthrough */
                 case ID_SP:
-                    pack_SP(ci);
+                    pack_SP(ci, new_cells);
                     ci->type = id_SP;
                     break;
                 default:
@@ -1514,6 +1585,10 @@ struct GowinPacker
                 }
             }
         }
+
+        for (auto &cell : new_cells) {
+            ctx->cells[cell->name] = std::move(cell);
+        }
     }
 
     // ===================================

From 6d9322457ec075bb8302d6100f6867ca8eaf6387 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sun, 26 Nov 2023 15:54:16 +0100
Subject: [PATCH 530/712] static: Reduce stddev of initial solution

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index ef60e47bcb..ffdd9b52e6 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -282,8 +282,8 @@ class StaticPlacer
         float m = std::sqrt(-2.f * std::log(u1));
         float z0 = m * std::cos(2.f * pi * u2);
         float z1 = m * std::sin(2.f * pi * u2);
-        float x = (width / 2.f) + (width / 50.f) * z0;
-        float y = (height / 2.f) + (height / 50.f) * z1;
+        float x = (width / 2.f) + (width / 250.f) * z0;
+        float y = (height / 2.f) + (height / 250.f) * z1;
         x = std::min<float>(width - 1.f, std::max<float>(x, 0));
         y = std::min<float>(height - 1.f, std::max<float>(y, 0));
         return RealPair(x, y);
@@ -527,8 +527,6 @@ class StaticPlacer
         for (int idx = 0; idx < int(ccells.size()); idx++) {
             auto &mc = mcells.at(idx);
             auto &g = groups.at(mc.group);
-            // scale width and height to be at least one bin (local density smoothing from the eplace paper)
-            // TODO: should we really do this every iteration?
             auto loc = mc.pos;
             auto size = mc.rect;
 
@@ -923,7 +921,7 @@ class StaticPlacer
         steplen = get_steplen();
         log_info("iter=%d steplen=%f a=%f\n", iter, steplen, nesterov_a);
         float a_next = (1.0f + std::sqrt(4.0f * nesterov_a * nesterov_a + 1)) / 2.0f;
-        // Update positions according to trivial gradient descent (let's leave Nesterov's for later...)
+        // Update positions using Nesterov's
         for (auto &cell : mcells) {
             if (cell.is_fixed || cell.is_dark)
                 continue;

From b4ca68c8ef221e6ba27fd19230a6027452e69e86 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Dec 2023 11:10:52 +0100
Subject: [PATCH 531/712] Add ability to override Cluster methods in Himbaechel

---
 himbaechel/arch.h            | 15 ++++++++++++++-
 himbaechel/himbaechel_api.cc | 16 ++++++++++++++++
 himbaechel/himbaechel_api.h  |  7 +++++++
 3 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 5590ef9929..548d6764d2 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -684,7 +684,20 @@ struct Arch : BaseArch<ArchRanges>
 
     // ------------------------------------------------
 
-    // clusters: BaseArch; for now
+    // Cluster methods
+    CellInfo *getClusterRootCell(ClusterId cluster) const override { return uarch->getClusterRootCell(cluster); }
+
+    BoundingBox getClusterBounds(ClusterId cluster) const override { return uarch->getClusterBounds(cluster); }
+
+    Loc getClusterOffset(const CellInfo *cell) const override { return uarch->getClusterOffset(cell); }
+
+    bool isClusterStrict(const CellInfo *cell) const override { return uarch->isClusterStrict(cell); }
+
+    bool getClusterPlacement(ClusterId cluster, BelId root_bel,
+                             std::vector<std::pair<CellInfo *, BelId>> &placement) const override
+    {
+        return uarch->getClusterPlacement(cluster, root_bel, placement);
+    }
     // ------------------------------------------------
 
     bool pack() override;
diff --git a/himbaechel/himbaechel_api.cc b/himbaechel/himbaechel_api.cc
index 2a04a99a45..0efe5c6f14 100644
--- a/himbaechel/himbaechel_api.cc
+++ b/himbaechel/himbaechel_api.cc
@@ -69,6 +69,22 @@ BoundingBox HimbaechelAPI::getRouteBoundingBox(WireId src, WireId dst) const
     return bb;
 }
 
+CellInfo *HimbaechelAPI::getClusterRootCell(ClusterId cluster) const
+{
+    return ctx->BaseArch::getClusterRootCell(cluster);
+}
+BoundingBox HimbaechelAPI::getClusterBounds(ClusterId cluster) const
+{
+    return ctx->BaseArch::getClusterBounds(cluster);
+}
+Loc HimbaechelAPI::getClusterOffset(const CellInfo *cell) const { return ctx->BaseArch::getClusterOffset(cell); }
+bool HimbaechelAPI::isClusterStrict(const CellInfo *cell) const { return ctx->BaseArch::isClusterStrict(cell); }
+bool HimbaechelAPI::getClusterPlacement(ClusterId cluster, BelId root_bel,
+                                        std::vector<std::pair<CellInfo *, BelId>> &placement) const
+{
+    return ctx->BaseArch::getClusterPlacement(cluster, root_bel, placement);
+}
+
 HimbaechelArch *HimbaechelArch::list_head;
 HimbaechelArch::HimbaechelArch(const std::string &name) : name(name)
 {
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index eaf1a5ed84..d68caea83f 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -95,6 +95,13 @@ struct HimbaechelAPI
     // Cell->bel pin mapping
     virtual bool map_cell_bel_pins(CellInfo *cell) const { return false; }
 
+    // Cluster
+    virtual CellInfo *getClusterRootCell(ClusterId cluster) const;
+    virtual BoundingBox getClusterBounds(ClusterId cluster) const;
+    virtual Loc getClusterOffset(const CellInfo *cell) const;
+    virtual bool isClusterStrict(const CellInfo *cell) const;
+    virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
+                                     std::vector<std::pair<CellInfo *, BelId>> &placement) const;
     // --- Flow hooks ---
     virtual void pack(){}; // replaces the pack function
     // Called before and after main placement and routing

From d1083fd348e1aaa6ec0cfafdad6e5947b50fb6de Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Sat, 9 Dec 2023 04:12:33 +0000
Subject: [PATCH 532/712] static/ice40: bug fixes for ultraplus

---
 common/place/placer_static.cc |  4 ++--
 common/place/placer_static.h  |  3 ++-
 ice40/arch.cc                 | 18 ++++++++++++++----
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index ffdd9b52e6..d3cb4863d5 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -1267,7 +1267,7 @@ class StaticPlacer
                 penalty *= 1.025;
             if (!legalised_ip) {
                 float ip_overlap = 0;
-                for (int i = 2; i < int(groups.size()); i++)
+                for (int i = cfg.logic_groups; i < int(groups.size()); i++)
                     ip_overlap = std::max(ip_overlap, groups.at(i).overlap);
                 if (ip_overlap < 0.15) {
                     legalise_step(true);
@@ -1275,7 +1275,7 @@ class StaticPlacer
                 }
             } else {
                 float logic_overlap = 0;
-                for (int i = 0; i < 2; i++)
+                for (int i = 0; i < cfg.logic_groups; i++)
                     logic_overlap = std::max(logic_overlap, groups.at(i).overlap);
                 if (logic_overlap < 0.1) {
                     legalise_step(false);
diff --git a/common/place/placer_static.h b/common/place/placer_static.h
index adce1f41ef..ac43920d52 100644
--- a/common/place/placer_static.h
+++ b/common/place/placer_static.h
@@ -61,8 +61,9 @@ struct PlacerStaticCfg
     // estimate = c + mx*dx + my * dy
     delay_t timing_c = 100, timing_mx = 100, timing_my = 100;
     // groups of cells that should be placed together.
-    // group 0 must be LUTs and group 1 must be FFs, further groups for BRAM/DSP/misc
+    // groups < logic_groups are logic like LUTs and FFs, further groups for BRAM/DSP/misc
     std::vector<StaticCellGroupCfg> cell_groups;
+    int logic_groups = 2;
 };
 
 extern bool placer_static(Context *ctx, PlacerStaticCfg cfg);
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 77261327ed..6f58cbbdeb 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -653,6 +653,7 @@ bool Arch::place()
             return false;
     } else if (placer == "static") {
         PlacerStaticCfg cfg(getCtx());
+        cfg.logic_groups = 1;
         {
             cfg.cell_groups.emplace_back();
             auto &comb = cfg.cell_groups.back();
@@ -671,6 +672,15 @@ bool Arch::place()
             comb.spacer_rect = StaticRect(1.0f, 2.0f);
         }
 
+        {
+            cfg.cell_groups.emplace_back();
+            auto& comb = cfg.cell_groups.back();
+            comb.name = getCtx()->id("DSP");
+            comb.cell_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);
+            comb.bel_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);
+            comb.spacer_rect = StaticRect(0.9f, 5.0f);
+        }
+
         {
             cfg.cell_groups.emplace_back();
             auto &comb = cfg.cell_groups.back();
@@ -684,9 +694,9 @@ bool Arch::place()
             cfg.cell_groups.emplace_back();
             auto &comb = cfg.cell_groups.back();
             comb.name = getCtx()->id("WARMBOOT");
-            comb.cell_area[id_SB_WARMBOOT] = StaticRect(1.0f, 1.0f);
-            comb.bel_area[id_SB_WARMBOOT] = StaticRect(1.0f, 1.0f);
-            comb.spacer_rect = StaticRect(1.0f, 1.0f);
+            comb.cell_area[id_SB_WARMBOOT] = StaticRect(0.5f, 1.0f);
+            comb.bel_area[id_SB_WARMBOOT] = StaticRect(0.5f, 1.0f);
+            comb.spacer_rect = StaticRect(0.5f, 1.0f);
         }
 
         {
@@ -695,7 +705,7 @@ bool Arch::place()
             comb.name = getCtx()->id("IO");
             comb.cell_area[id_SB_IO] = StaticRect(0.5f, 0.5f);
             comb.bel_area[id_SB_IO] = StaticRect(0.5f, 0.5f);
-            comb.spacer_rect = StaticRect(1.0f, 1.0f);
+            comb.spacer_rect = StaticRect(0.5f, 0.5f);
         }
         if (!placer_static(getCtx(), cfg))
             return false;

From 535709a9a933c2343247c7f204d3ed707308bf47 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 8 Dec 2023 16:07:17 +0100
Subject: [PATCH 533/712] placer1: Fix various bitrot

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/place_common.cc | 156 +++++++++++++++++++----------------
 common/place/place_common.h  |   3 -
 common/place/placer1.cc      |  92 ++++++++-------------
 3 files changed, 118 insertions(+), 133 deletions(-)

diff --git a/common/place/place_common.cc b/common/place/place_common.cc
index 8218b9fedf..c044e7e749 100644
--- a/common/place/place_common.cc
+++ b/common/place/place_common.cc
@@ -19,6 +19,7 @@
 
 #include "place_common.h"
 #include <cmath>
+#include "fast_bels.h"
 #include "log.h"
 #include "util.h"
 
@@ -102,77 +103,6 @@ wirelen_t get_cell_metric_at_bel(const Context *ctx, CellInfo *cell, BelId bel,
     return wirelen;
 }
 
-// Placing a single cell
-bool place_single_cell(Context *ctx, CellInfo *cell, bool require_legality)
-{
-    bool all_placed = false;
-    int iters = 25;
-    while (!all_placed) {
-        BelId best_bel = BelId();
-        wirelen_t best_wirelen = std::numeric_limits<wirelen_t>::max(),
-                  best_ripup_wirelen = std::numeric_limits<wirelen_t>::max();
-        CellInfo *ripup_target = nullptr;
-        BelId ripup_bel = BelId();
-        if (cell->bel != BelId()) {
-            ctx->unbindBel(cell->bel);
-        }
-        IdString targetType = cell->type;
-        for (auto bel : ctx->getBels()) {
-            if (ctx->isValidBelForCellType(targetType, bel)) {
-                if (ctx->checkBelAvail(bel)) {
-                    wirelen_t wirelen = get_cell_metric_at_bel(ctx, cell, bel, MetricType::COST);
-                    if (iters >= 4)
-                        wirelen += ctx->rng(25);
-                    if (wirelen <= best_wirelen) {
-                        best_wirelen = wirelen;
-                        best_bel = bel;
-                    }
-                } else {
-                    wirelen_t wirelen = get_cell_metric_at_bel(ctx, cell, bel, MetricType::COST);
-                    if (iters >= 4)
-                        wirelen += ctx->rng(25);
-                    if (wirelen <= best_ripup_wirelen) {
-                        CellInfo *curr_cell = ctx->getBoundBelCell(bel);
-                        if (curr_cell->belStrength < STRENGTH_STRONG) {
-                            best_ripup_wirelen = wirelen;
-                            ripup_bel = bel;
-                            ripup_target = curr_cell;
-                        }
-                    }
-                }
-            }
-        }
-        if (best_bel == BelId()) {
-            if (iters == 0) {
-                log_error("failed to place cell '%s' of type '%s' (ripup iteration limit exceeded)\n",
-                          cell->name.c_str(ctx), cell->type.c_str(ctx));
-            }
-            if (ripup_bel == BelId()) {
-                log_error("failed to place cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx));
-            }
-            --iters;
-            ctx->unbindBel(ripup_target->bel);
-            best_bel = ripup_bel;
-        } else {
-            ripup_target = nullptr;
-            all_placed = true;
-        }
-        ctx->bindBel(best_bel, cell, STRENGTH_WEAK);
-        if (require_legality && !ctx->isBelLocationValid(best_bel)) {
-            ctx->unbindBel(best_bel);
-            if (ripup_target != nullptr) {
-                ctx->bindBel(best_bel, ripup_target, STRENGTH_WEAK);
-            }
-            all_placed = false;
-            continue;
-        }
-        if (ctx->verbose)
-            log_info("   placed single cell '%s' at '%s'\n", cell->name.c_str(ctx), ctx->nameOfBel(best_bel));
-        cell = ripup_target;
-    }
-    return true;
-}
-
 class ConstraintLegaliseWorker
 {
   private:
@@ -180,6 +110,7 @@ class ConstraintLegaliseWorker
     std::set<IdString> rippedCells;
     dict<IdString, Loc> oldLocations;
     dict<ClusterId, std::vector<CellInfo *>> cluster2cells;
+    FastBels fast_bels;
 
     class IncreasingDiameterSearch
     {
@@ -376,8 +307,87 @@ class ConstraintLegaliseWorker
     // Check if constraints are currently satisfied on a cell and its children
     bool constraints_satisfied(const CellInfo *cell) { return get_constraints_distance(ctx, cell) == 0; }
 
+    // Placing a single cell
+    bool place_single_cell(CellInfo *cell)
+    {
+        int diameter = 1;
+        while (cell) {
+            CellInfo *ripup_target = nullptr;
+            if (cell->bel != BelId()) {
+                ctx->unbindBel(cell->bel);
+            }
+            FastBels::FastBelsData *bel_data;
+            fast_bels.getBelsForCellType(cell->type, &bel_data);
+
+            int iter = 0;
+            BelId best_bel = BelId();
+            wirelen_t best_metric = std::numeric_limits<wirelen_t>::max();
+
+            while (true) {
+                ++iter;
+                if (iter >= (5 * diameter)) {
+                    iter = 0;
+                    if (diameter < std::max(ctx->getGridDimX(), ctx->getGridDimY()))
+                        ++diameter;
+                    if (best_bel != BelId())
+                        break;
+                }
+                auto old_loc = oldLocations.at(cell->name);
+                int nx = old_loc.x - (diameter / 2) + ctx->rng(diameter),
+                    ny = old_loc.y - (diameter / 2) + ctx->rng(diameter);
+                if (nx < 0 || nx >= int(bel_data->size()))
+                    continue;
+                if (ny < 0 || ny >= int(bel_data->at(nx).size()))
+                    continue;
+                const auto &fb = bel_data->at(nx).at(ny);
+                if (fb.size() == 0)
+                    continue;
+                BelId bel = fb.at(ctx->rng(int(fb.size())));
+                if (cell->region && cell->region->constr_bels && !cell->region->bels.count(bel))
+                    continue;
+                if (!ctx->isValidBelForCellType(cell->type, bel))
+                    continue;
+                ripup_target = ctx->getBoundBelCell(bel);
+                if (ripup_target != nullptr) {
+                    if (ripup_target->belStrength > STRENGTH_STRONG || ripup_target->cluster != ClusterId())
+                        continue;
+                    ctx->unbindBel(bel);
+                } else if (!ctx->checkBelAvail(bel)) {
+                    continue;
+                }
+                ctx->bindBel(bel, cell, STRENGTH_WEAK);
+                if (!ctx->isBelLocationValid(bel)) {
+                    ctx->unbindBel(bel);
+                    if (ripup_target)
+                        ctx->bindBel(bel, ripup_target, STRENGTH_WEAK);
+                    continue;
+                }
+                wirelen_t new_metric = get_cell_metric(ctx, cell, MetricType::COST);
+                if (ripup_target)
+                    new_metric *= 5;
+                if (new_metric < best_metric) {
+                    best_bel = bel;
+                    best_metric = new_metric;
+                }
+                ctx->unbindBel(bel);
+                if (ripup_target)
+                    ctx->bindBel(bel, ripup_target, STRENGTH_WEAK);
+            }
+
+            // Back annotate location
+            ripup_target = ctx->getBoundBelCell(best_bel);
+            if (ripup_target)
+                ctx->unbindBel(best_bel);
+            ctx->bindBel(best_bel, cell, STRENGTH_WEAK);
+
+            cell->attrs[ctx->id("BEL")] = ctx->getBelName(cell->bel).str(ctx);
+            cell = ripup_target;
+        }
+        return true;
+    }
+
   public:
-    ConstraintLegaliseWorker(Context *ctx) : ctx(ctx)
+    ConstraintLegaliseWorker(Context *ctx) : ctx(ctx), fast_bels(ctx, /*check_bel_available=*/false, 0)
     {
         for (auto &cell : ctx->cells) {
             if (cell.second->cluster != ClusterId())
@@ -429,7 +439,7 @@ class ConstraintLegaliseWorker
         if (print_stats("legalising chains") == 0)
             return 0;
         for (auto rippedCell : rippedCells) {
-            bool res = place_single_cell(ctx, ctx->cells.at(rippedCell).get(), true);
+            bool res = place_single_cell(ctx->cells.at(rippedCell).get());
             if (!res) {
                 log_error("failed to place cell '%s' after relative constraint legalisation\n", rippedCell.c_str(ctx));
                 return -1;
diff --git a/common/place/place_common.h b/common/place/place_common.h
index 5e5cbee3b3..5179de4208 100644
--- a/common/place/place_common.h
+++ b/common/place/place_common.h
@@ -41,9 +41,6 @@ wirelen_t get_cell_metric(const Context *ctx, const CellInfo *cell, MetricType t
 // Return the wirelength of all nets connected to a cell, when the cell is at a given bel
 wirelen_t get_cell_metric_at_bel(const Context *ctx, CellInfo *cell, BelId bel, MetricType type);
 
-// Place a single cell in the lowest wirelength Bel available, optionally requiring validity check
-bool place_single_cell(Context *ctx, CellInfo *cell, bool require_legality);
-
 // Modify a design s.t. all relative placement constraints are satisfied
 bool legalise_relative_constraints(Context *ctx);
 
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index 4ecf3a7707..057f0106cd 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -416,73 +416,51 @@ class SAPlacer
     }
 
   private:
+    std::vector<BelId> all_bels;
     // Initial random placement
     void place_initial(CellInfo *cell)
     {
-        bool all_placed = false;
-        int iters = 25;
-        while (!all_placed) {
-            BelId best_bel = BelId();
-            uint64_t best_score = std::numeric_limits<uint64_t>::max(),
-                     best_ripup_score = std::numeric_limits<uint64_t>::max();
+        while (cell) {
             CellInfo *ripup_target = nullptr;
-            BelId ripup_bel = BelId();
             if (cell->bel != BelId()) {
                 ctx->unbindBel(cell->bel);
             }
-            IdString targetType = cell->type;
-
-            auto proc_bel = [&](BelId bel) {
-                if (ctx->isValidBelForCellType(targetType, bel)) {
-                    if (ctx->checkBelAvail(bel)) {
-                        uint64_t score = ctx->rng64();
-                        if (score <= best_score) {
-                            best_score = score;
-                            best_bel = bel;
-                        }
-                    } else {
-                        uint64_t score = ctx->rng64();
-                        CellInfo *bound_cell = ctx->getBoundBelCell(bel);
-                        if (score <= best_ripup_score && bound_cell->belStrength < STRENGTH_STRONG) {
-                            best_ripup_score = score;
-                            ripup_target = bound_cell;
-                            ripup_bel = bel;
-                        }
-                    }
-                }
-            };
-
-            if (cell->region != nullptr && cell->region->constr_bels) {
-                for (auto bel : cell->region->bels) {
-                    proc_bel(bel);
-                }
-            } else {
-                for (auto bel : ctx->getBels()) {
-                    proc_bel(bel);
-                }
-            }
-
-            if (best_bel == BelId()) {
-                if (iters == 0 || ripup_bel == BelId())
-                    log_error("failed to place cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx));
-                --iters;
-                ctx->unbindBel(ripup_target->bel);
-                best_bel = ripup_bel;
-            } else {
-                ripup_target = nullptr;
-                all_placed = true;
-            }
-            ctx->bindBel(best_bel, cell, STRENGTH_WEAK);
-
-            if (!ctx->isBelLocationValid(best_bel)) {
-                ctx->unbindBel(best_bel);
+            FastBels::FastBelsData *bel_data;
+            auto type_cnt = fast_bels.getBelsForCellType(cell->type, &bel_data);
+
+            while (true) {
+                int nx = ctx->rng(max_x + 1), ny = ctx->rng(max_y + 1);
+                if (cfg.minBelsForGridPick >= 0 && type_cnt < cfg.minBelsForGridPick)
+                    nx = ny = 0;
+                if (nx >= int(bel_data->size()))
+                    continue;
+                if (ny >= int(bel_data->at(nx).size()))
+                    continue;
+                const auto &fb = bel_data->at(nx).at(ny);
+                if (fb.size() == 0)
+                    continue;
+                BelId bel = fb.at(ctx->rng(int(fb.size())));
+                if (cell->region && cell->region->constr_bels && !cell->region->bels.count(bel))
+                    continue;
+                if (!ctx->isValidBelForCellType(cell->type, bel))
+                    continue;
+                ripup_target = ctx->getBoundBelCell(bel);
                 if (ripup_target != nullptr) {
-                    ctx->bindBel(best_bel, ripup_target, STRENGTH_WEAK);
+                    if (ripup_target->belStrength > STRENGTH_STRONG)
+                        continue;
+                    ctx->unbindBel(bel);
+                } else if (!ctx->checkBelAvail(bel)) {
+                    continue;
                 }
-                all_placed = false;
-                continue;
+                ctx->bindBel(bel, cell, STRENGTH_WEAK);
+                if (!ctx->isBelLocationValid(bel)) {
+                    ctx->unbindBel(bel);
+                    if (ripup_target)
+                        ctx->bindBel(bel, ripup_target, STRENGTH_WEAK);
+                    continue;
+                }
+                break;
             }
-
             // Back annotate location
             cell->attrs[ctx->id("BEL")] = ctx->getBelName(cell->bel).str(ctx);
             cell = ripup_target;

From 56587859d3596c4a42d5f28ae51898ee09cea2c1 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 18 Dec 2023 12:18:22 +0000
Subject: [PATCH 534/712] nexus: Improve error reporting for illegal carry
 chains

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/pack.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index d5c7147e67..dad3722a3b 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1318,8 +1318,14 @@ struct NexusPacker
             CellInfo *ci = cell.second.get();
             if (ci->type != id_CCU2)
                 continue;
-            if (ci->getPort(id_CIN) != nullptr)
+            NetInfo *cin = ci->getPort(id_CIN);
+            if (cin) {
+                if (cin->driver.cell && cin->driver.cell->type != id_CCU2) {
+                    log_error("CCU2 '%s' CIN net '%s' driven by non-CCU2 cell '%s'.\n",
+                        ctx->nameOf(ci), ctx->nameOf(cin), ctx->nameOf(cin->driver.cell));
+                }
                 continue;
+            }
             roots.push_back(ci);
         }
         for (CellInfo *root : roots) {

From 41914876ef641eff9c9c46f9e87e655f666197d7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 23 Dec 2023 11:05:50 +0100
Subject: [PATCH 535/712] .gitignore for nextpnr-himbaechel

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 7051a9c0f4..d5a21ea1c7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@
 /nextpnr-fpga_interchange*
 /nextpnr-gowin*
 /nextpnr-machxo2*
+/nextpnr-himbaechel*
 .cache
 cmake-build-*/
 Makefile

From 4a4025192a4d832f7636225c5a26912975c96f21 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 26 Dec 2023 09:54:34 +0100
Subject: [PATCH 536/712] run clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/pybindings.cc | 2 +-
 common/route/router2.cc     | 6 ++++--
 ecp5/pack.cc                | 3 ++-
 gowin/pack.cc               | 6 +++---
 gui/fpgaviewwidget.cc       | 4 ++--
 ice40/arch.cc               | 2 +-
 nexus/pack.cc               | 4 ++--
 7 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index 137c3e36ba..db233c1c9c 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -305,7 +305,7 @@ void (*python_sighandler)(int) = nullptr;
 void init_python(const char *executable)
 {
 #ifdef MAIN_EXECUTABLE
-    static const char* python_argv[1];
+    static const char *python_argv[1];
     python_argv[0] = executable;
     py::initialize_interpreter(true, 1, python_argv);
     py::module::import(TOSTRING(MODULE_NAME));
diff --git a/common/route/router2.cc b/common/route/router2.cc
index d592dcb8da..8dcec6e91c 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -781,8 +781,10 @@ struct Router2
                         WireScore next_score;
                         next_score.delay = curr.score.delay + cfg.get_base_cost(ctx, next, uh, crit_weight);
                         next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
-                        next_score.togo_cost =
-                                const_mode ? 0 : cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
+                        next_score.togo_cost = const_mode
+                                                       ? 0
+                                                       : cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire,
+                                                                                             true, crit_weight);
                         if (was_visited_bwd(next_idx, next_score.delay)) {
                             // Don't expand the same node twice.
                             continue;
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 69d7ccf8df..7d7c044c92 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -240,7 +240,8 @@ class Ecp5Packer
                     ci->disconnectPort(id_M);
                     ci->ports.erase(id_M);
                 }
-                if (di && di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
+                if (di && di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB &&
+                    di->driver.port == id_F) {
                     CellInfo *comb = di->driver.cell;
                     if (comb->cluster != ClusterId()) {
                         // Special procedure where the comb cell is part of an existing macro
diff --git a/gowin/pack.cc b/gowin/pack.cc
index d89992cc42..951f94f3a0 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -19,9 +19,9 @@
  */
 
 #include <algorithm>
+#include <cinttypes>
 #include <iostream>
 #include <iterator>
-#include <cinttypes>
 #include "cells.h"
 #include "design_utils.h"
 #include "log.h"
@@ -673,8 +673,8 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                 uc_init &= (1LL << uc_init_len) - 1;
 
                 if (ctx->verbose)
-                    log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc), it_param->second.intval,
-                             uc_init);
+                    log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc),
+                             it_param->second.intval, uc_init);
 
                 it_param->second = Property(uc_init, uc_init_len);
                 uc->ports[user.port].net = nullptr;
diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index c06482c9ab..24f953384a 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -574,8 +574,8 @@ void FPGAViewWidget::renderLines(void)
         }
         rendererData_->bbGlobal.setX0(-1.0f);
         rendererData_->bbGlobal.setY0(-1.0f);
-        rendererData_->bbGlobal.setX1(1.0f * (ctx_->getGridDimX()+1));
-        rendererData_->bbGlobal.setY1(1.0f * (ctx_->getGridDimY()+1));
+        rendererData_->bbGlobal.setX1(1.0f * (ctx_->getGridDimX() + 1));
+        rendererData_->bbGlobal.setY1(1.0f * (ctx_->getGridDimY() + 1));
         rendererData_->gfxGrid.last_render++;
     }
     if (highlightedOrSelectedChanged) {
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 6f58cbbdeb..030849a5c9 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -674,7 +674,7 @@ bool Arch::place()
 
         {
             cfg.cell_groups.emplace_back();
-            auto& comb = cfg.cell_groups.back();
+            auto &comb = cfg.cell_groups.back();
             comb.name = getCtx()->id("DSP");
             comb.cell_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);
             comb.bel_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);
diff --git a/nexus/pack.cc b/nexus/pack.cc
index dad3722a3b..9991d49de8 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1321,8 +1321,8 @@ struct NexusPacker
             NetInfo *cin = ci->getPort(id_CIN);
             if (cin) {
                 if (cin->driver.cell && cin->driver.cell->type != id_CCU2) {
-                    log_error("CCU2 '%s' CIN net '%s' driven by non-CCU2 cell '%s'.\n",
-                        ctx->nameOf(ci), ctx->nameOf(cin), ctx->nameOf(cin->driver.cell));
+                    log_error("CCU2 '%s' CIN net '%s' driven by non-CCU2 cell '%s'.\n", ctx->nameOf(ci),
+                              ctx->nameOf(cin), ctx->nameOf(cin->driver.cell));
                 }
                 continue;
             }

From d2297b1ba004855b2ed316ac9305b395303d0dff Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 8 Dec 2023 17:36:48 +0000
Subject: [PATCH 537/712] Add Rust FFI bindings

---
 .gitmodules                       |   3 +
 3rdparty/corrosion                |   1 +
 CMakeLists.txt                    |  19 +-
 ice40/arch.cc                     |   7 +
 rust/Cargo.toml                   |   6 +
 rust/example_printnets/Cargo.toml |  14 +
 rust/example_printnets/src/lib.rs |  12 +
 rust/nextpnr/Cargo.toml           |  14 +
 rust/nextpnr/src/lib.rs           | 581 ++++++++++++++++++++++++++++++
 rust/rust.cc                      | 323 +++++++++++++++++
 rust/rust.h                       |  34 ++
 11 files changed, 1013 insertions(+), 1 deletion(-)
 create mode 160000 3rdparty/corrosion
 create mode 100644 rust/Cargo.toml
 create mode 100644 rust/example_printnets/Cargo.toml
 create mode 100644 rust/example_printnets/src/lib.rs
 create mode 100644 rust/nextpnr/Cargo.toml
 create mode 100644 rust/nextpnr/src/lib.rs
 create mode 100644 rust/rust.cc
 create mode 100644 rust/rust.h

diff --git a/.gitmodules b/.gitmodules
index fde861f7ff..c03206a37f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,6 @@
 [submodule "himbaechel/uarch/xilinx/meta"]
 	path = himbaechel/uarch/xilinx/meta
 	url = https://github.com/gatecat/nextpnr-xilinx-meta
+[submodule "3rdparty/corrosion"]
+	path = 3rdparty/corrosion
+	url = https://github.com/corrosion-rs/corrosion
diff --git a/3rdparty/corrosion b/3rdparty/corrosion
new file mode 160000
index 0000000000..be76480232
--- /dev/null
+++ b/3rdparty/corrosion
@@ -0,0 +1 @@
+Subproject commit be76480232216a64f65e3b1d9794d68cbac6c690
diff --git a/CMakeLists.txt b/CMakeLists.txt
index adef332fb9..2a2886e8c5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -29,6 +29,13 @@ option(EXTERNAL_CHIPDB "Create build with pre-built chipdb binaries" OFF)
 option(WERROR "pass -Werror to compiler (used for CI)" OFF)
 option(PROFILER "Link against libprofiler" OFF)
 option(USE_IPO "Compile nextpnr with IPO" ON)
+option(USE_RUST "Enable Rust bindings" OFF)
+
+if (USE_RUST)
+    add_subdirectory(3rdparty/corrosion)
+    corrosion_import_crate(MANIFEST_PATH rust/Cargo.toml PROFILE "release" IMPORTED_CRATES RUST_CRATES)
+    aux_source_directory(rust RUST_FILES)
+endif()
 
 if (USE_IPO)
     if (ipo_supported)
@@ -249,7 +256,10 @@ aux_source_directory(3rdparty/json11 EXT_JSON11_FILES)
 aux_source_directory(3rdparty/oourafft EXT_OOURAFFT_FILES)
 aux_source_directory(frontend/ FRONTEND_FILES)
 
+aux_source_directory(rust/ RUST_FILES)
+
 set(COMMON_FILES ${KERNEL_SRC_FILES} ${PLACE_SRC_FILES} ${ROUTE_SRC_FILES} ${EXT_JSON11_FILES} ${EXT_OOURAFFT_FILES} ${JSON_PARSER_FILES} ${FRONTEND_FILES})
+
 if( NOT CMAKE_BUILD_TYPE )
     set(CMAKE_BUILD_TYPE Release)
 endif()
@@ -337,7 +347,7 @@ foreach (family ${ARCH})
         endforeach()
 
         # Include family-specific source files to all family targets and set defines appropriately
-        target_include_directories(${target} PRIVATE ${family}/ ${CMAKE_CURRENT_BINARY_DIR}/generated/)
+        target_include_directories(${target} PRIVATE ${family}/ ${CMAKE_CURRENT_BINARY_DIR}/generated/ rust/)
         target_compile_definitions(${target} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family} ARCH_${ufamily} ARCHNAME=${family})
         target_link_libraries(${target} LINK_PUBLIC ${Boost_LIBRARIES} ${link_param})
         if (NOT MSVC)
@@ -360,6 +370,13 @@ foreach (family ${ARCH})
                 endif()
             endif()
         endif()
+        if (USE_RUST)
+            target_sources(${target} PRIVATE ${RUST_FILES})
+            target_compile_definitions(${target} PRIVATE USE_RUST)
+            foreach(crate ${RUST_CRATES})
+                target_link_libraries(${target} PRIVATE ${crate})
+            endforeach(crate)
+        endif()
     endforeach (target)
 endforeach (family)
 
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 030849a5c9..1f8577fd67 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -30,6 +30,7 @@
 #include "placer_static.h"
 #include "router1.h"
 #include "router2.h"
+#include "rust.h"
 #include "timing_opt.h"
 #include "util.h"
 NEXTPNR_NAMESPACE_BEGIN
@@ -642,6 +643,12 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 bool Arch::place()
 {
+#ifdef USE_RUST
+    log_info("Calling Rust\n");
+    example_printnets(getCtx());
+    log_info("Returned from Rust\n");
+#endif
+
     std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
diff --git a/rust/Cargo.toml b/rust/Cargo.toml
new file mode 100644
index 0000000000..edf09dfe2c
--- /dev/null
+++ b/rust/Cargo.toml
@@ -0,0 +1,6 @@
+[workspace]
+
+members = [
+    "nextpnr",
+    "example_printnets",
+]
diff --git a/rust/example_printnets/Cargo.toml b/rust/example_printnets/Cargo.toml
new file mode 100644
index 0000000000..bc516be78b
--- /dev/null
+++ b/rust/example_printnets/Cargo.toml
@@ -0,0 +1,14 @@
+[package]
+name = "example_printnets"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[lib]
+name = "example_printnets"
+path = "src/lib.rs"
+crate-type = ["staticlib"]
+
+[dependencies]
+nextpnr = { path = "../nextpnr" }
diff --git a/rust/example_printnets/src/lib.rs b/rust/example_printnets/src/lib.rs
new file mode 100644
index 0000000000..7a21af50e8
--- /dev/null
+++ b/rust/example_printnets/src/lib.rs
@@ -0,0 +1,12 @@
+use nextpnr::{Context, Nets};
+
+#[no_mangle]
+pub extern "C" fn rust_example_printnets(ctx: &mut Context) {
+    let nets = Nets::new(ctx);
+    let nets_vec = nets.to_vec();
+
+    println!("Nets in design:");
+    for (&name, _net) in nets_vec {
+        println!("  {}", ctx.name_of(name).to_str().unwrap());
+    }
+}
diff --git a/rust/nextpnr/Cargo.toml b/rust/nextpnr/Cargo.toml
new file mode 100644
index 0000000000..aa0fb488df
--- /dev/null
+++ b/rust/nextpnr/Cargo.toml
@@ -0,0 +1,14 @@
+[package]
+name = "nextpnr"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[lib]
+name = "nextpnr"
+path = "src/lib.rs"
+crate-type = ["rlib"]
+
+[dependencies]
+libc = "0.2"
diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
new file mode 100644
index 0000000000..f0231f7b37
--- /dev/null
+++ b/rust/nextpnr/src/lib.rs
@@ -0,0 +1,581 @@
+use core::slice;
+use std::{collections::HashMap, ffi::CStr, marker::PhantomData, sync::Mutex};
+
+use libc::c_char;
+
+#[derive(Clone, Copy)]
+#[repr(C)]
+pub enum PlaceStrength {
+    None = 0,
+    Weak = 1,
+    Strong = 2,
+    Placer = 3,
+    Fixed = 4,
+    Locked = 5,
+    User = 6,
+}
+
+#[repr(C)]
+pub struct CellInfo {
+    private: [u8; 0],
+}
+
+impl CellInfo {
+    pub fn location(&self) -> Loc {
+        unsafe { npnr_cellinfo_get_location(self) }
+    }
+}
+
+#[repr(C)]
+pub struct NetInfo {
+    private: [u8; 0],
+}
+
+impl NetInfo {
+    pub fn driver(&mut self) -> *mut PortRef {
+        unsafe { npnr_netinfo_driver(self) }
+    }
+
+    pub fn is_global(&self) -> bool {
+        unsafe { npnr_netinfo_is_global(self) }
+    }
+
+    pub fn index(&self) -> NetIndex {
+        unsafe { npnr_netinfo_udata(self) }
+    }
+}
+
+#[repr(transparent)]
+#[derive(Clone, Copy, PartialEq, Eq, Hash)]
+pub struct NetIndex(i32);
+
+impl NetIndex {
+    pub fn into_inner(self) -> i32 {
+        self.0
+    }
+}
+
+#[repr(C)]
+pub struct PortRef {
+    private: [u8; 0],
+}
+
+impl PortRef {
+    pub fn cell(&self) -> Option<&CellInfo> {
+        // SAFETY: handing out &s is safe when we have &self.
+        unsafe { npnr_portref_cell(self).as_ref() }
+    }
+
+    pub fn cell_mut(&mut self) -> Option<&mut CellInfo> {
+        // SAFETY: handing out &mut is safe when we have &mut self
+        // as getting multiple &mut CellInfo would require multiple &mut PortRef.
+        unsafe { npnr_portref_cell(self).as_mut() }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct IdString(libc::c_int);
+
+/// A type representing a bel name.
+#[derive(Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
+pub struct BelId(u64);
+
+impl BelId {
+    /// Return a sentinel value that represents an invalid bel.
+    pub fn null() -> Self {
+        // SAFETY: BelId() has no safety requirements.
+        unsafe { npnr_belid_null() }
+    }
+
+    /// Check if this bel is invalid.
+    pub fn is_null(self) -> bool {
+        self == Self::null()
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct PipId(u64);
+
+impl PipId {
+    pub fn null() -> Self {
+        unsafe { npnr_pipid_null() }
+    }
+}
+
+#[derive(Clone, Copy, PartialOrd, Ord, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct WireId(u64);
+
+impl WireId {
+    /// Return a sentinel value that represents an invalid wire.
+    pub fn null() -> Self {
+        // SAFETY: WireId() has no safety requirements.
+        unsafe { npnr_wireid_null() }
+    }
+
+    /// Check if this wire is invalid.
+    pub fn is_null(self) -> bool {
+        self == Self::null()
+    }
+}
+
+#[repr(C)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
+pub struct Loc {
+    pub x: libc::c_int,
+    pub y: libc::c_int,
+    pub z: libc::c_int,
+}
+
+impl From<(i32, i32)> for Loc {
+    fn from(pos: (i32, i32)) -> Self {
+        Self {
+            x: pos.0,
+            y: pos.1,
+            z: 0,
+        }
+    }
+}
+
+#[repr(C)]
+pub struct Context {
+    _private: [u8; 0],
+}
+
+impl Context {
+    /// Get grid X dimension. All bels and pips must have X coordinates in the range `0 .. getGridDimX()-1` (inclusive).
+    pub fn grid_dim_x(&self) -> i32 {
+        unsafe { npnr_context_get_grid_dim_x(self) }
+    }
+
+    /// Get grid Y dimension. All bels and pips must have Y coordinates in the range `0 .. getGridDimY()-1` (inclusive).
+    pub fn grid_dim_y(&self) -> i32 {
+        unsafe { npnr_context_get_grid_dim_y(self) }
+    }
+
+    /// Bind a given bel to a given cell with the given strength.
+    pub fn bind_bel(&mut self, bel: BelId, cell: *mut CellInfo, strength: PlaceStrength) {
+        unsafe { npnr_context_bind_bel(self, bel, cell, strength) }
+    }
+
+    /// Unbind a bel.
+    pub fn unbind_bel(&mut self, bel: BelId) {
+        unsafe { npnr_context_unbind_bel(self, bel) }
+    }
+
+    /// Returns true if the bel is available. A bel can be unavailable because it is bound, or because it is exclusive to some other resource that is bound.
+    pub fn check_bel_avail(&self, bel: BelId) -> bool {
+        unsafe { npnr_context_check_bel_avail(self, bel) }
+    }
+
+    /// Bind a wire to a net. This method must be used when binding a wire that is driven by a bel pin. Use bindPip() when binding a wire that is driven by a pip.
+    pub fn bind_wire(&mut self, wire: WireId, net: *mut NetInfo, strength: PlaceStrength) {
+        unsafe { npnr_context_bind_wire(self, wire, net, strength) }
+    }
+
+    /// Unbind a wire. For wires that are driven by a pip, this will also unbind the driving pip.
+    pub fn unbind_wire(&mut self, wire: WireId) {
+        unsafe { npnr_context_unbind_wire(self, wire) }
+    }
+
+    /// Bid a pip to a net. This also bind the destination wire of that pip.
+    pub fn bind_pip(&mut self, pip: PipId, net: *mut NetInfo, strength: PlaceStrength) {
+        unsafe { npnr_context_bind_pip(self, pip, net, strength) }
+    }
+
+    /// Unbind a pip and the wire driven by that pip.
+    pub fn unbind_pip(&mut self, pip: PipId) {
+        unsafe { npnr_context_unbind_pip(self, pip) }
+    }
+
+    /// Get the source wire for a pip.
+    pub fn pip_src_wire(&self, pip: PipId) -> WireId {
+        unsafe { npnr_context_get_pip_src_wire(self, pip) }
+    }
+
+    /// Get the destination wire for a pip.
+    pub fn pip_dst_wire(&self, pip: PipId) -> WireId {
+        unsafe { npnr_context_get_pip_dst_wire(self, pip) }
+    }
+
+    // TODO: Should this be a Duration? Does that even make sense?
+    pub fn estimate_delay(&self, src: WireId, dst: WireId) -> f32 {
+        unsafe { npnr_context_estimate_delay(self, src, dst) }
+    }
+
+    pub fn pip_delay(&self, pip: PipId) -> f32 {
+        unsafe { npnr_context_get_pip_delay(self, pip) }
+    }
+
+    pub fn wire_delay(&self, wire: WireId) -> f32 {
+        unsafe { npnr_context_get_wire_delay(self, wire) }
+    }
+
+    pub fn delay_epsilon(&self) -> f32 {
+        unsafe { npnr_context_delay_epsilon(self) }
+    }
+
+    pub fn source_wire(&self, net: *const NetInfo) -> WireId {
+        unsafe { npnr_context_get_netinfo_source_wire(self, net) }
+    }
+
+    pub fn sink_wires(&self, net: *const NetInfo, sink: *const PortRef) -> Vec<WireId> {
+        let mut v = Vec::new();
+        let mut n = 0;
+        loop {
+            let wire = unsafe { npnr_context_get_netinfo_sink_wire(self, net, sink, n) };
+            if wire.is_null() {
+                break;
+            }
+            n += 1;
+            v.push(wire);
+        }
+        v
+    }
+
+    pub fn wires_leaking(&self) -> &[WireId] {
+        let mut wires = std::ptr::null_mut();
+        let len = unsafe { npnr_context_get_wires_leak(self, &mut wires as *mut *mut WireId) };
+        unsafe { std::slice::from_raw_parts(wires, len as usize) }
+    }
+
+    pub fn pips_leaking(&self) -> &[PipId] {
+        let mut pips = std::ptr::null_mut();
+        let len = unsafe { npnr_context_get_pips_leak(self, &mut pips as *mut *mut PipId) };
+        unsafe { std::slice::from_raw_parts(pips, len as usize) }
+    }
+
+    pub fn get_downhill_pips(&self, wire: WireId) -> DownhillPipsIter {
+        let iter = unsafe { npnr_context_get_pips_downhill(self, wire) };
+        DownhillPipsIter {
+            iter,
+            phantom_data: Default::default(),
+        }
+    }
+
+    pub fn get_uphill_pips(&self, wire: WireId) -> UphillPipsIter {
+        let iter = unsafe { npnr_context_get_pips_uphill(self, wire) };
+        UphillPipsIter {
+            iter,
+            phantom_data: Default::default(),
+        }
+    }
+
+    pub fn pip_location(&self, pip: PipId) -> Loc {
+        unsafe { npnr_context_get_pip_location(self, pip) }
+    }
+
+    pub fn pip_direction(&self, pip: PipId) -> Loc {
+        unsafe { npnr_context_get_pip_direction(self, pip) }
+    }
+
+    pub fn pip_avail_for_net(&self, pip: PipId, net: *mut NetInfo) -> bool {
+        unsafe { npnr_context_check_pip_avail_for_net(self, pip, net) }
+    }
+
+    pub fn check(&self) {
+        unsafe { npnr_context_check(self) }
+    }
+
+    pub fn debug(&self) -> bool {
+        unsafe { npnr_context_debug(self) }
+    }
+
+    pub fn id(&self, s: &str) -> IdString {
+        let s = std::ffi::CString::new(s).unwrap();
+        unsafe { npnr_context_id(self, s.as_ptr()) }
+    }
+
+    pub fn name_of(&self, s: IdString) -> &CStr {
+        unsafe { CStr::from_ptr(npnr_context_name_of(self, s)) }
+    }
+
+    pub fn name_of_pip(&self, pip: PipId) -> &CStr {
+        unsafe { CStr::from_ptr(npnr_context_name_of_pip(self, pip)) }
+    }
+
+    pub fn name_of_wire(&self, wire: WireId) -> &CStr {
+        static MUTEX: Mutex<()> = Mutex::new(());
+        let _lock = MUTEX.lock().unwrap();
+        unsafe { CStr::from_ptr(npnr_context_name_of_wire(self, wire)) }
+    }
+
+    pub fn verbose(&self) -> bool {
+        unsafe { npnr_context_verbose(self) }
+    }
+}
+
+extern "C" {
+    pub fn npnr_log_info(format: *const c_char);
+    pub fn npnr_log_error(format: *const c_char);
+
+    fn npnr_belid_null() -> BelId;
+    fn npnr_wireid_null() -> WireId;
+    fn npnr_pipid_null() -> PipId;
+
+    fn npnr_context_get_grid_dim_x(ctx: *const Context) -> libc::c_int;
+    fn npnr_context_get_grid_dim_y(ctx: *const Context) -> libc::c_int;
+    fn npnr_context_bind_bel(
+        ctx: *mut Context,
+        bel: BelId,
+        cell: *mut CellInfo,
+        strength: PlaceStrength,
+    );
+    fn npnr_context_unbind_bel(ctx: *mut Context, bel: BelId);
+    fn npnr_context_check_bel_avail(ctx: *const Context, bel: BelId) -> bool;
+    fn npnr_context_bind_wire(
+        ctx: *mut Context,
+        wire: WireId,
+        net: *mut NetInfo,
+        strength: PlaceStrength,
+    );
+    fn npnr_context_unbind_wire(ctx: *mut Context, wire: WireId);
+    fn npnr_context_bind_pip(
+        ctx: *mut Context,
+        pip: PipId,
+        net: *mut NetInfo,
+        strength: PlaceStrength,
+    );
+    fn npnr_context_unbind_pip(ctx: *mut Context, pip: PipId);
+    fn npnr_context_get_pip_src_wire(ctx: *const Context, pip: PipId) -> WireId;
+    fn npnr_context_get_pip_dst_wire(ctx: *const Context, pip: PipId) -> WireId;
+    fn npnr_context_estimate_delay(ctx: *const Context, src: WireId, dst: WireId) -> f32;
+    fn npnr_context_delay_epsilon(ctx: *const Context) -> f32;
+    fn npnr_context_get_pip_delay(ctx: *const Context, pip: PipId) -> f32;
+    fn npnr_context_get_wire_delay(ctx: *const Context, wire: WireId) -> f32;
+    fn npnr_context_get_wires_leak(ctx: *const Context, wires: *mut *mut WireId) -> u64;
+    fn npnr_context_get_pips_leak(ctx: *const Context, pips: *mut *mut PipId) -> u64;
+    fn npnr_context_get_pip_location(ctx: *const Context, pip: PipId) -> Loc;
+    fn npnr_context_get_pip_direction(ctx: *const Context, pip: PipId) -> Loc;
+    fn npnr_context_check_pip_avail_for_net(
+        ctx: *const Context,
+        pip: PipId,
+        net: *const NetInfo,
+    ) -> bool;
+
+    fn npnr_context_check(ctx: *const Context);
+    fn npnr_context_debug(ctx: *const Context) -> bool;
+    fn npnr_context_id(ctx: *const Context, s: *const c_char) -> IdString;
+    fn npnr_context_name_of(ctx: *const Context, s: IdString) -> *const libc::c_char;
+    fn npnr_context_name_of_pip(ctx: *const Context, pip: PipId) -> *const libc::c_char;
+    fn npnr_context_name_of_wire(ctx: *const Context, wire: WireId) -> *const libc::c_char;
+    fn npnr_context_verbose(ctx: *const Context) -> bool;
+
+    fn npnr_context_get_netinfo_source_wire(ctx: *const Context, net: *const NetInfo) -> WireId;
+    fn npnr_context_get_netinfo_sink_wire(
+        ctx: *const Context,
+        net: *const NetInfo,
+        sink: *const PortRef,
+        n: u32,
+    ) -> WireId;
+
+    fn npnr_context_nets_leak(
+        ctx: *const Context,
+        names: *mut *mut libc::c_int,
+        nets: *mut *mut *mut NetInfo,
+    ) -> u32;
+    fn npnr_context_get_pips_downhill(ctx: *const Context, wire: WireId) -> *mut RawDownhillIter;
+    fn npnr_delete_downhill_iter(iter: *mut RawDownhillIter);
+    fn npnr_context_get_pips_uphill(ctx: *const Context, wire: WireId) -> *mut RawUphillIter;
+    fn npnr_delete_uphill_iter(iter: *mut RawUphillIter);
+
+    fn npnr_netinfo_driver(net: *mut NetInfo) -> *mut PortRef;
+    fn npnr_netinfo_users_leak(net: *mut NetInfo, users: *mut *mut *mut PortRef) -> u32;
+    fn npnr_netinfo_is_global(net: *const NetInfo) -> bool;
+    fn npnr_netinfo_udata(net: *const NetInfo) -> NetIndex;
+    fn npnr_netinfo_udata_set(net: *mut NetInfo, value: NetIndex);
+
+    fn npnr_portref_cell(port: *const PortRef) -> *mut CellInfo;
+    fn npnr_cellinfo_get_location(info: *const CellInfo) -> Loc;
+
+    fn npnr_inc_downhill_iter(iter: *mut RawDownhillIter);
+    fn npnr_deref_downhill_iter(iter: *mut RawDownhillIter) -> PipId;
+    fn npnr_is_downhill_iter_done(iter: *mut RawDownhillIter) -> bool;
+    fn npnr_inc_uphill_iter(iter: *mut RawUphillIter);
+    fn npnr_deref_uphill_iter(iter: *mut RawUphillIter) -> PipId;
+    fn npnr_is_uphill_iter_done(iter: *mut RawUphillIter) -> bool;
+}
+
+/// Store for the nets of a context.
+pub struct Nets<'a> {
+    nets: HashMap<IdString, *mut NetInfo>,
+    users: HashMap<IdString, &'a [&'a mut PortRef]>,
+    index_to_net: Vec<IdString>,
+    net_to_index: HashMap<*mut NetInfo, i32>,
+    _data: PhantomData<&'a Context>,
+}
+
+unsafe impl Send for Nets<'_> {}
+unsafe impl Sync for Nets<'_> {}
+
+impl<'a> Nets<'a> {
+    /// Create a new store for the nets of a context.
+    ///
+    /// Note that this leaks memory created by nextpnr; the intention is this is called once.
+    pub fn new(ctx: &'a Context) -> Nets<'a> {
+        let mut names: *mut libc::c_int = std::ptr::null_mut();
+        let mut nets_ptr: *mut *mut NetInfo = std::ptr::null_mut();
+        let size = unsafe {
+            npnr_context_nets_leak(
+                ctx,
+                &mut names as *mut *mut libc::c_int,
+                &mut nets_ptr as *mut *mut *mut NetInfo,
+            )
+        };
+        let mut nets = HashMap::new();
+        let mut users = HashMap::new();
+        let mut index_to_net = Vec::new();
+        let mut net_to_index = HashMap::new();
+        for i in 0..size {
+            let name = unsafe { IdString(*names.add(i as usize)) };
+            let net = unsafe { *nets_ptr.add(i as usize) };
+            let mut users_ptr = std::ptr::null_mut();
+            // SAFETY: net is not null because it's a &mut, and users is only written to.
+            // Leaking memory is the most convenient FFI I could think of.
+            let len =
+                unsafe { npnr_netinfo_users_leak(net, &mut users_ptr as *mut *mut *mut PortRef) };
+            let users_slice =
+                unsafe { slice::from_raw_parts(users_ptr as *mut &mut PortRef, len as usize) };
+            nets.insert(name, net);
+            users.insert(name, users_slice);
+            let index = index_to_net.len() as i32;
+            index_to_net.push(name);
+            net_to_index.insert(net, index);
+            unsafe {
+                npnr_netinfo_udata_set(net, NetIndex(index));
+            }
+        }
+        // Note: the contents of `names` and `nets_ptr` are now lost.
+        Self {
+            nets,
+            users,
+            index_to_net,
+            net_to_index,
+            _data: PhantomData,
+        }
+    }
+
+    /// Find net users given a net's name.
+    pub fn users_by_name(&self, net: IdString) -> Option<&&[&mut PortRef]> {
+        self.users.get(&net)
+    }
+
+    /// Return the number of nets in the store.
+    pub fn len(&self) -> usize {
+        self.nets.len()
+    }
+
+    pub fn name_from_index(&self, index: NetIndex) -> IdString {
+        self.index_to_net[index.0 as usize]
+    }
+
+    pub fn net_from_index(&self, index: NetIndex) -> *mut NetInfo {
+        *self.nets.get(&self.name_from_index(index)).unwrap()
+    }
+
+    pub fn to_vec(&self) -> Vec<(&IdString, &*mut NetInfo)> {
+        let mut v = Vec::new();
+        v.extend(self.nets.iter());
+        v.sort_by_key(|(name, _net)| name.0);
+        v
+    }
+}
+
+pub struct NetSinkWireIter<'a> {
+    ctx: &'a Context,
+    net: *const NetInfo,
+    sink: *const PortRef,
+    n: u32,
+}
+
+impl<'a> Iterator for NetSinkWireIter<'a> {
+    type Item = WireId;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        let item =
+            unsafe { npnr_context_get_netinfo_sink_wire(self.ctx, self.net, self.sink, self.n) };
+        if item.is_null() {
+            return None;
+        }
+        self.n += 1;
+        Some(item)
+    }
+}
+
+#[repr(C)]
+struct RawDownhillIter {
+    content: [u8; 0],
+}
+
+pub struct DownhillPipsIter<'a> {
+    iter: *mut RawDownhillIter,
+    phantom_data: std::marker::PhantomData<&'a PipId>,
+}
+
+impl<'a> Iterator for DownhillPipsIter<'a> {
+    type Item = PipId;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        if unsafe { npnr_is_downhill_iter_done(self.iter) } {
+            None
+        } else {
+            let pip = unsafe { npnr_deref_downhill_iter(self.iter) };
+            unsafe { npnr_inc_downhill_iter(self.iter) };
+            Some(pip)
+        }
+    }
+}
+
+impl<'a> Drop for DownhillPipsIter<'a> {
+    fn drop(&mut self) {
+        unsafe { npnr_delete_downhill_iter(self.iter) };
+    }
+}
+
+#[repr(C)]
+struct RawUphillIter {
+    content: [u8; 0],
+}
+
+pub struct UphillPipsIter<'a> {
+    iter: *mut RawUphillIter,
+    phantom_data: std::marker::PhantomData<&'a PipId>,
+}
+
+impl<'a> Iterator for UphillPipsIter<'a> {
+    type Item = PipId;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        if unsafe { npnr_is_uphill_iter_done(self.iter) } {
+            None
+        } else {
+            let pip = unsafe { npnr_deref_uphill_iter(self.iter) };
+            unsafe { npnr_inc_uphill_iter(self.iter) };
+            Some(pip)
+        }
+    }
+}
+
+impl<'a> Drop for UphillPipsIter<'a> {
+    fn drop(&mut self) {
+        unsafe { npnr_delete_uphill_iter(self.iter) };
+    }
+}
+
+macro_rules! log_info {
+    ($($t:tt)*) => {
+        let s = std::ffi::CString::new(format!($($t)*)).unwrap();
+        unsafe { crate::npnr::npnr_log_info(s.as_ptr()); }
+    };
+}
+
+macro_rules! log_error {
+    ($($t:tt)*) => {
+        let s = std::ffi::CString::new(format!($($t)*)).unwrap();
+        unsafe { crate::npnr::npnr_log_error(s.as_ptr()); }
+    };
+}
+
diff --git a/rust/rust.cc b/rust/rust.cc
new file mode 100644
index 0000000000..33970f279d
--- /dev/null
+++ b/rust/rust.cc
@@ -0,0 +1,323 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022  Lofty <lofty@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+
+namespace {
+    USING_NEXTPNR_NAMESPACE;
+
+    template<typename T>
+    uint64_t wrap(T thing) {
+        static_assert(sizeof(T) <= 8, "T is too big for FFI");
+        uint64_t b = 0;
+        memcpy(&b, &thing, sizeof(T));
+        return b;
+    }
+
+    BelId unwrap_bel(uint64_t bel) {
+        static_assert(sizeof(BelId) <= 8, "T is too big for FFI");
+        auto b = BelId();
+        memcpy(&b, &bel, sizeof(BelId));
+        return b;
+    }
+
+    PipId unwrap_pip(uint64_t pip) {
+        static_assert(sizeof(PipId) <= 8, "T is too big for FFI");
+        auto p = PipId();
+        memcpy(&p, &pip, sizeof(PipId));
+        return p;
+    }
+
+    WireId unwrap_wire(uint64_t wire) {
+        static_assert(sizeof(WireId) <= 8, "T is too big for FFI");
+        auto w = WireId();
+        memcpy(&w, &wire, sizeof(WireId));
+        return w;
+    }
+}
+
+using DownhillIter = decltype(Context(ArchArgs()).getPipsDownhill(WireId()).begin());
+
+struct DownhillIterWrapper {
+    DownhillIter current;
+    DownhillIter end;
+
+    DownhillIterWrapper(DownhillIter begin, DownhillIter end) : current(begin), end(end) {}
+};
+using UphillIter = decltype(Context(ArchArgs()).getPipsUphill(WireId()).begin());
+
+struct UphillIterWrapper {
+    UphillIter current;
+    UphillIter end;
+
+    UphillIterWrapper(UphillIter begin, UphillIter end) : current(begin), end(end) {}
+};
+
+extern "C" {
+    USING_NEXTPNR_NAMESPACE;
+
+    /*
+        DONE:
+        ctx->bindPip
+        ctx->bindWire
+        ctx->check
+        ctx->debug
+        ctx->estimateDelay
+        ctx->getDelayEpsilon
+        ctx->getPipDstWire
+        ctx->getPipSrcWire
+        ctx->getGridDimX
+        ctx->getGridDimY
+        ctx->id
+        ctx->nameOf
+        ctx->unbindWire
+        ctx->verbose
+
+        UNNECESSARY:
+        ctx->getDelayNS - all FFI calls go through it anyway.
+
+        TODO:
+        ctx->checkPipAvail
+        ctx->checkPipAvailForNet
+        ctx->checkWireAvail
+        ctx->getBelPinType
+        ctx->getBoundPipNet
+        ctx->getBoundWireNet
+        ctx->getNetinfoSinkWire
+        ctx->getNetinfoSinkWires
+        ctx->getNetinfoSourceWire
+        ctx->getPipDelay
+        ctx->getPipLocation
+        ctx->getPipsDownhill
+        ctx->getPipsUphill
+        ctx->getRouteBoundingBox
+        ctx->getWireBelPins
+        ctx->getWireDelay
+        ctx->getWires
+        ctx->getWireType
+        ctx->nameOfPip
+        ctx->nameOfWire
+        ctx->nets
+        ctx->nets.at
+        ctx->nets.size
+        ctx->rng64
+        ctx->setting<bool>
+        ctx->setting<float>
+        ctx->setting<int>
+        ctx->sorted_shuffle
+    */
+
+    void npnr_log_info(const char *const format) { log_info("%s", format); }
+    void npnr_log_error(const char *const format) { log_error("%s", format); }
+
+    uint64_t npnr_belid_null() { return wrap(BelId()); }
+    uint64_t npnr_wireid_null() { return wrap(WireId()); }
+    uint64_t npnr_pipid_null() { return wrap(PipId()); }
+
+    int npnr_context_get_grid_dim_x(const Context *const ctx) { return ctx->getGridDimX(); }
+    int npnr_context_get_grid_dim_y(const Context *const ctx) { return ctx->getGridDimY(); }
+    void npnr_context_bind_bel(Context *ctx, uint64_t bel, CellInfo* cell, PlaceStrength strength) { return ctx->bindBel(unwrap_bel(bel), cell, strength); }
+    void npnr_context_unbind_bel(Context *ctx, uint64_t bel) { return ctx->unbindBel(unwrap_bel(bel)); }
+    bool npnr_context_check_bel_avail(Context *const ctx, uint64_t bel) { return ctx->checkBelAvail(unwrap_bel(bel)); }
+    void npnr_context_bind_wire(Context *ctx, uint64_t wire, NetInfo* net, PlaceStrength strength) { ctx->bindWire(unwrap_wire(wire), net, strength); }
+    void npnr_context_unbind_wire(Context *ctx, uint64_t wire) { ctx->unbindWire(unwrap_wire(wire)); }
+    void npnr_context_bind_pip(Context *ctx, uint64_t pip, NetInfo* net, PlaceStrength strength) { ctx->bindPip(unwrap_pip(pip), net, strength); }
+    void npnr_context_unbind_pip(Context *ctx, uint64_t pip) { ctx->unbindPip(unwrap_pip(pip)); }
+    uint64_t npnr_context_get_pip_src_wire(const Context *const ctx, uint64_t pip) { return wrap(ctx->getPipSrcWire(unwrap_pip(pip))); }
+    uint64_t npnr_context_get_pip_dst_wire(const Context *const ctx, uint64_t pip) { return wrap(ctx->getPipDstWire(unwrap_pip(pip))); }
+    float npnr_context_estimate_delay(const Context *const ctx, uint64_t src, uint64_t dst) { return ctx->getDelayNS(ctx->estimateDelay(unwrap_wire(src), unwrap_wire(dst))); }
+    float npnr_context_get_pip_delay(const Context *const ctx, uint64_t pip) { return ctx->getDelayNS(ctx->getPipDelay(unwrap_pip(pip)).maxDelay()); }
+    float npnr_context_get_wire_delay(const Context *const ctx, uint64_t wire) { return ctx->getDelayNS(ctx->getWireDelay(unwrap_wire(wire)).maxDelay()); }
+    float npnr_context_delay_epsilon(const Context *const ctx) { return ctx->getDelayNS(ctx->getDelayEpsilon()); }
+    Loc npnr_context_get_pip_location(const Context *const ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
+    bool npnr_context_check_pip_avail_for_net(const Context *const ctx, uint64_t pip, NetInfo *net) { return ctx->checkPipAvailForNet(unwrap_pip(pip), net); }
+
+    // This method's in C++ temporarily, while I figure out some better way of getting a pip iterator.
+    Loc npnr_context_get_pip_direction(const Context *const ctx, uint64_t _pip) {
+        auto pip = unwrap_pip(_pip);
+        auto src_loc = Loc{};
+        auto dst_loc = Loc{};
+
+        auto uh_pips = 0;
+        for (auto uh : ctx->getPipsUphill(ctx->getPipSrcWire(pip))) {
+            auto loc = ctx->getPipLocation(uh);
+            src_loc.x += loc.x;
+            src_loc.y += loc.y;
+            uh_pips++;
+        }
+        if (uh_pips > 1) {
+            src_loc.x /= uh_pips;
+            src_loc.y /= uh_pips;
+        }
+
+        auto dh_pips = 0;
+        for (auto dh : ctx->getPipsDownhill(ctx->getPipDstWire(pip))) {
+            auto loc = ctx->getPipLocation(dh);
+            dst_loc.x += loc.x;
+            dst_loc.y += loc.y;
+            dh_pips++;
+        }
+        if (dh_pips > 1) {
+            dst_loc.x /= dh_pips;
+            dst_loc.y /= dh_pips;
+        }
+
+        dst_loc.x -= src_loc.x;
+        dst_loc.y -= src_loc.y;
+        return dst_loc;
+    }
+
+    uint64_t npnr_context_get_pips_leak(const Context *const ctx, PipId **pips) {
+        auto pip_vec = std::vector<PipId>{};
+        for (auto pip : ctx->getPips()) {
+            pip_vec.push_back(pip);
+        }
+        pip_vec.shrink_to_fit();
+        auto size = pip_vec.size();
+        *pips = pip_vec.data();
+        auto dummy = std::vector<PipId>{};
+        // Yes, by memcpying over `pip_vec` we leak memory.
+        std::memcpy(&pip_vec, &dummy, sizeof(dummy));
+        return size;
+    }
+
+    uint64_t npnr_context_get_wires_leak(const Context *const ctx, WireId **wires) {
+        auto wire_vec = std::vector<WireId>{};
+        for (auto wire : ctx->getWires()) {
+            wire_vec.push_back(wire);
+        }
+        wire_vec.shrink_to_fit();
+        auto size = wire_vec.size();
+        *wires = wire_vec.data();
+        auto dummy = std::vector<WireId>{};
+        // Yes, by memcpying over `wire_vec` we leak memory.
+        std::memcpy(&wire_vec, &dummy, sizeof(dummy));
+        return size;
+    }
+
+    void npnr_context_check(const Context *const ctx) { ctx->check(); }
+    bool npnr_context_debug(const Context *const ctx) { return ctx->debug; }
+    int npnr_context_id(const Context *const ctx, const char *const str) { return ctx->id(str).hash(); }
+    const char *npnr_context_name_of(const Context *const ctx, IdString str) { return ctx->nameOf(str); }
+    const char *npnr_context_name_of_pip(const Context *const ctx, uint64_t pip) { return ctx->nameOfPip(unwrap_pip(pip)); }
+    const char *npnr_context_name_of_wire(const Context *const ctx, uint64_t wire) { return ctx->nameOfWire(unwrap_wire(wire)); }
+    bool npnr_context_verbose(const Context *const ctx) { return ctx->verbose; }
+
+    uint64_t npnr_context_get_netinfo_source_wire(const Context *const ctx, const NetInfo *const net) { return wrap(ctx->getNetinfoSourceWire(net)); }
+    uint64_t npnr_context_get_netinfo_sink_wire(const Context *const ctx, const NetInfo *const net, const PortRef *const sink, uint32_t n) { return wrap(ctx->getNetinfoSinkWire(net, *sink, n)); }
+
+    uint32_t npnr_context_nets_leak(const Context *const ctx, int **names, NetInfo ***nets) {
+        auto name_vec = std::vector<int>{};
+        auto nets_vec = std::vector<NetInfo*>{};
+        for (auto& item : ctx->nets) {
+            name_vec.push_back(item.first.hash());
+            nets_vec.push_back(item.second.get());
+        }
+        name_vec.shrink_to_fit();
+        nets_vec.shrink_to_fit();
+        auto size = name_vec.size();
+        *names = name_vec.data();
+        *nets = nets_vec.data();
+        // Yes, by memcpying over `name_vec` and `nets_vec` we leak memory.
+        auto dummy1 = std::vector<int>{};
+        auto dummy2 = std::vector<NetInfo*>{};
+        std::memcpy(&name_vec, &dummy1, sizeof(dummy1));
+        std::memcpy(&nets_vec, &dummy2, sizeof(dummy2));
+        return size;
+    }
+
+    DownhillIterWrapper *npnr_context_get_pips_downhill(Context *ctx, uint64_t wire_id) {
+        auto wire = unwrap_wire(wire_id);
+        auto range = ctx->getPipsDownhill(wire);
+        return new DownhillIterWrapper(range.begin(), range.end());
+    }
+    void npnr_delete_downhill_iter(DownhillIterWrapper *iter) {
+        delete iter;
+    }
+    UphillIterWrapper *npnr_context_get_pips_uphill(Context *ctx, uint64_t wire_id) {
+        auto wire = unwrap_wire(wire_id);
+        auto range = ctx->getPipsUphill(wire);
+        return new UphillIterWrapper(range.begin(), range.end());
+    }
+    void npnr_delete_uphill_iter(UphillIterWrapper *iter) {
+        delete iter;
+    }
+
+    PortRef* npnr_netinfo_driver(NetInfo *const net) {
+        if (net == nullptr) {
+            return nullptr;
+        }
+        return &net->driver;
+    }
+
+    uint32_t npnr_netinfo_users_leak(NetInfo *const net, PortRef ***users) {
+        auto x = std::vector<PortRef*>{};
+        for (auto& item : net->users) {
+            x.push_back(&item);
+        }
+        x.shrink_to_fit();
+        *users = x.data();
+        auto size = x.size();
+        // Yes, by memcpying over `x` we leak memory.
+        auto dummy = std::vector<PortRef*>{};
+        std::memcpy(&x, &dummy, sizeof(dummy));
+        return size;
+    }
+
+#ifdef ARCH_ECP5
+    bool npnr_netinfo_is_global(NetInfo *const net) { return net->is_global; }
+#else
+    bool npnr_netinfo_is_global(NetInfo *const net) { return false; }
+#endif
+
+    int32_t npnr_netinfo_udata(NetInfo *const net) { return net->udata; }
+    void npnr_netinfo_udata_set(NetInfo *const net, int32_t value) { net->udata = value; }
+
+    CellInfo* npnr_portref_cell(const PortRef *const port) { return port->cell; }
+    Loc npnr_cellinfo_get_location(const CellInfo *const info) { return info->getLocation(); }
+
+    void npnr_inc_downhill_iter(DownhillIterWrapper *iter) {
+        ++iter->current;
+    }
+    uint64_t npnr_deref_downhill_iter(DownhillIterWrapper *iter) {
+        return wrap(*iter->current);
+    }
+    bool npnr_is_downhill_iter_done(DownhillIterWrapper *iter) {
+        return !(iter->current != iter->end);
+    }
+    void npnr_inc_uphill_iter(UphillIterWrapper *iter) {
+        ++iter->current;
+    }
+    uint64_t npnr_deref_uphill_iter(UphillIterWrapper *iter) {
+        return wrap(*iter->current);
+    }
+    bool npnr_is_uphill_iter_done(UphillIterWrapper *iter) {
+        return !(iter->current != iter->end);
+    }
+
+    void rust_example_printnets(Context *ctx);
+}
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void example_printnets(Context *ctx) {
+    rust_example_printnets(ctx);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/rust/rust.h b/rust/rust.h
new file mode 100644
index 0000000000..4830503fa2
--- /dev/null
+++ b/rust/rust.h
@@ -0,0 +1,34 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2022  Lofty <lofty@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef RUST_H
+#define RUST_H
+
+#ifdef USE_RUST
+
+#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
+void example_printnets(Context* ctx);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
+
+#endif // RUST_H

From 1dbd81067ab32214507d8dd732eee01a29143005 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 20 Dec 2023 11:54:10 +0000
Subject: [PATCH 538/712] first round of review fixes

---
 CMakeLists.txt          |   1 -
 rust/nextpnr/src/lib.rs |  67 ++++++++++---
 rust/rust.cc            | 216 ++++++++++++----------------------------
 3 files changed, 116 insertions(+), 168 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 2a2886e8c5..d24a5d5fe7 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -34,7 +34,6 @@ option(USE_RUST "Enable Rust bindings" OFF)
 if (USE_RUST)
     add_subdirectory(3rdparty/corrosion)
     corrosion_import_crate(MANIFEST_PATH rust/Cargo.toml PROFILE "release" IMPORTED_CRATES RUST_CRATES)
-    aux_source_directory(rust RUST_FILES)
 endif()
 
 if (USE_IPO)
diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index f0231f7b37..05f4721fe8 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -157,7 +157,10 @@ impl Context {
     }
 
     /// Bind a given bel to a given cell with the given strength.
-    pub fn bind_bel(&mut self, bel: BelId, cell: *mut CellInfo, strength: PlaceStrength) {
+    ///
+    /// # Safety
+    /// `cell` must be valid and not null.
+    pub unsafe fn bind_bel(&mut self, bel: BelId, cell: *mut CellInfo, strength: PlaceStrength) {
         unsafe { npnr_context_bind_bel(self, bel, cell, strength) }
     }
 
@@ -172,7 +175,10 @@ impl Context {
     }
 
     /// Bind a wire to a net. This method must be used when binding a wire that is driven by a bel pin. Use bindPip() when binding a wire that is driven by a pip.
-    pub fn bind_wire(&mut self, wire: WireId, net: *mut NetInfo, strength: PlaceStrength) {
+    ///
+    /// # Safety
+    /// `net` must be valid and not null.
+    pub unsafe fn bind_wire(&mut self, wire: WireId, net: *mut NetInfo, strength: PlaceStrength) {
         unsafe { npnr_context_bind_wire(self, wire, net, strength) }
     }
 
@@ -181,8 +187,11 @@ impl Context {
         unsafe { npnr_context_unbind_wire(self, wire) }
     }
 
-    /// Bid a pip to a net. This also bind the destination wire of that pip.
-    pub fn bind_pip(&mut self, pip: PipId, net: *mut NetInfo, strength: PlaceStrength) {
+    /// Bind a pip to a net. This also binds the destination wire of that pip.
+    ///
+    /// # Safety
+    /// `net` must be valid and not null.
+    pub unsafe fn bind_pip(&mut self, pip: PipId, net: *mut NetInfo, strength: PlaceStrength) {
         unsafe { npnr_context_bind_pip(self, pip, net, strength) }
     }
 
@@ -218,11 +227,15 @@ impl Context {
         unsafe { npnr_context_delay_epsilon(self) }
     }
 
-    pub fn source_wire(&self, net: *const NetInfo) -> WireId {
+    /// # Safety
+    /// `net` must be valid and not null.
+    pub unsafe fn source_wire(&self, net: *const NetInfo) -> WireId {
         unsafe { npnr_context_get_netinfo_source_wire(self, net) }
     }
 
-    pub fn sink_wires(&self, net: *const NetInfo, sink: *const PortRef) -> Vec<WireId> {
+    /// # Safety
+    /// `net` and `sink` must be valid and not null.
+    pub unsafe fn sink_wires(&self, net: *const NetInfo, sink: *const PortRef) -> Vec<WireId> {
         let mut v = Vec::new();
         let mut n = 0;
         loop {
@@ -269,10 +282,39 @@ impl Context {
     }
 
     pub fn pip_direction(&self, pip: PipId) -> Loc {
-        unsafe { npnr_context_get_pip_direction(self, pip) }
+        let mut src = Loc{x: 0, y: 0, z: 0};
+        let mut dst = Loc{x: 0, y: 0, z: 0};
+
+        let mut pips = 0;
+        for pip in self.get_uphill_pips(self.pip_src_wire(pip)) {
+            let loc = self.pip_location(pip);
+            src.x += loc.x;
+            src.y += loc.y;
+            pips += 1;
+        }
+        if pips != 0 {
+            src.x /= pips;
+            src.y /= pips;
+        }
+
+        let mut pips = 0;
+        for pip in self.get_downhill_pips(self.pip_dst_wire(pip)) {
+            let loc = self.pip_location(pip);
+            dst.x += loc.x;
+            dst.y += loc.y;
+            pips += 1;
+        }
+        if pips != 0 {
+            dst.x /= pips;
+            dst.y /= pips;
+        }
+
+        Loc{x: dst.x - src.x, y: dst.y - src.y, z: 0}
     }
 
-    pub fn pip_avail_for_net(&self, pip: PipId, net: *mut NetInfo) -> bool {
+    /// # Safety
+    /// `net` must be valid and not null.
+    pub unsafe fn pip_avail_for_net(&self, pip: PipId, net: *mut NetInfo) -> bool {
         unsafe { npnr_context_check_pip_avail_for_net(self, pip, net) }
     }
 
@@ -349,7 +391,6 @@ extern "C" {
     fn npnr_context_get_wires_leak(ctx: *const Context, wires: *mut *mut WireId) -> u64;
     fn npnr_context_get_pips_leak(ctx: *const Context, pips: *mut *mut PipId) -> u64;
     fn npnr_context_get_pip_location(ctx: *const Context, pip: PipId) -> Loc;
-    fn npnr_context_get_pip_direction(ctx: *const Context, pip: PipId) -> Loc;
     fn npnr_context_check_pip_avail_for_net(
         ctx: *const Context,
         pip: PipId,
@@ -404,7 +445,6 @@ pub struct Nets<'a> {
     nets: HashMap<IdString, *mut NetInfo>,
     users: HashMap<IdString, &'a [&'a mut PortRef]>,
     index_to_net: Vec<IdString>,
-    net_to_index: HashMap<*mut NetInfo, i32>,
     _data: PhantomData<&'a Context>,
 }
 
@@ -428,7 +468,6 @@ impl<'a> Nets<'a> {
         let mut nets = HashMap::new();
         let mut users = HashMap::new();
         let mut index_to_net = Vec::new();
-        let mut net_to_index = HashMap::new();
         for i in 0..size {
             let name = unsafe { IdString(*names.add(i as usize)) };
             let net = unsafe { *nets_ptr.add(i as usize) };
@@ -443,7 +482,6 @@ impl<'a> Nets<'a> {
             users.insert(name, users_slice);
             let index = index_to_net.len() as i32;
             index_to_net.push(name);
-            net_to_index.insert(net, index);
             unsafe {
                 npnr_netinfo_udata_set(net, NetIndex(index));
             }
@@ -453,7 +491,6 @@ impl<'a> Nets<'a> {
             nets,
             users,
             index_to_net,
-            net_to_index,
             _data: PhantomData,
         }
     }
@@ -468,6 +505,10 @@ impl<'a> Nets<'a> {
         self.nets.len()
     }
 
+    pub fn is_empty(&self) -> bool {
+        self.nets.len() == 0
+    }
+
     pub fn name_from_index(&self, index: NetIndex) -> IdString {
         self.index_to_net[index.0 as usize]
     }
diff --git a/rust/rust.cc b/rust/rust.cc
index 33970f279d..41866124d2 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -72,173 +72,81 @@ struct UphillIterWrapper {
 extern "C" {
     USING_NEXTPNR_NAMESPACE;
 
-    /*
-        DONE:
-        ctx->bindPip
-        ctx->bindWire
-        ctx->check
-        ctx->debug
-        ctx->estimateDelay
-        ctx->getDelayEpsilon
-        ctx->getPipDstWire
-        ctx->getPipSrcWire
-        ctx->getGridDimX
-        ctx->getGridDimY
-        ctx->id
-        ctx->nameOf
-        ctx->unbindWire
-        ctx->verbose
-
-        UNNECESSARY:
-        ctx->getDelayNS - all FFI calls go through it anyway.
-
-        TODO:
-        ctx->checkPipAvail
-        ctx->checkPipAvailForNet
-        ctx->checkWireAvail
-        ctx->getBelPinType
-        ctx->getBoundPipNet
-        ctx->getBoundWireNet
-        ctx->getNetinfoSinkWire
-        ctx->getNetinfoSinkWires
-        ctx->getNetinfoSourceWire
-        ctx->getPipDelay
-        ctx->getPipLocation
-        ctx->getPipsDownhill
-        ctx->getPipsUphill
-        ctx->getRouteBoundingBox
-        ctx->getWireBelPins
-        ctx->getWireDelay
-        ctx->getWires
-        ctx->getWireType
-        ctx->nameOfPip
-        ctx->nameOfWire
-        ctx->nets
-        ctx->nets.at
-        ctx->nets.size
-        ctx->rng64
-        ctx->setting<bool>
-        ctx->setting<float>
-        ctx->setting<int>
-        ctx->sorted_shuffle
-    */
-
-    void npnr_log_info(const char *const format) { log_info("%s", format); }
-    void npnr_log_error(const char *const format) { log_error("%s", format); }
+    void npnr_log_info(const char *string) { log_info("%s", string); }
+    void npnr_log_error(const char *string) { log_error("%s", string); }
 
     uint64_t npnr_belid_null() { return wrap(BelId()); }
     uint64_t npnr_wireid_null() { return wrap(WireId()); }
     uint64_t npnr_pipid_null() { return wrap(PipId()); }
 
-    int npnr_context_get_grid_dim_x(const Context *const ctx) { return ctx->getGridDimX(); }
-    int npnr_context_get_grid_dim_y(const Context *const ctx) { return ctx->getGridDimY(); }
+    int npnr_context_get_grid_dim_x(const Context *ctx) { return ctx->getGridDimX(); }
+    int npnr_context_get_grid_dim_y(const Context *ctx) { return ctx->getGridDimY(); }
     void npnr_context_bind_bel(Context *ctx, uint64_t bel, CellInfo* cell, PlaceStrength strength) { return ctx->bindBel(unwrap_bel(bel), cell, strength); }
     void npnr_context_unbind_bel(Context *ctx, uint64_t bel) { return ctx->unbindBel(unwrap_bel(bel)); }
-    bool npnr_context_check_bel_avail(Context *const ctx, uint64_t bel) { return ctx->checkBelAvail(unwrap_bel(bel)); }
+    bool npnr_context_check_bel_avail(Context *ctx, uint64_t bel) { return ctx->checkBelAvail(unwrap_bel(bel)); }
     void npnr_context_bind_wire(Context *ctx, uint64_t wire, NetInfo* net, PlaceStrength strength) { ctx->bindWire(unwrap_wire(wire), net, strength); }
     void npnr_context_unbind_wire(Context *ctx, uint64_t wire) { ctx->unbindWire(unwrap_wire(wire)); }
     void npnr_context_bind_pip(Context *ctx, uint64_t pip, NetInfo* net, PlaceStrength strength) { ctx->bindPip(unwrap_pip(pip), net, strength); }
     void npnr_context_unbind_pip(Context *ctx, uint64_t pip) { ctx->unbindPip(unwrap_pip(pip)); }
-    uint64_t npnr_context_get_pip_src_wire(const Context *const ctx, uint64_t pip) { return wrap(ctx->getPipSrcWire(unwrap_pip(pip))); }
-    uint64_t npnr_context_get_pip_dst_wire(const Context *const ctx, uint64_t pip) { return wrap(ctx->getPipDstWire(unwrap_pip(pip))); }
-    float npnr_context_estimate_delay(const Context *const ctx, uint64_t src, uint64_t dst) { return ctx->getDelayNS(ctx->estimateDelay(unwrap_wire(src), unwrap_wire(dst))); }
-    float npnr_context_get_pip_delay(const Context *const ctx, uint64_t pip) { return ctx->getDelayNS(ctx->getPipDelay(unwrap_pip(pip)).maxDelay()); }
-    float npnr_context_get_wire_delay(const Context *const ctx, uint64_t wire) { return ctx->getDelayNS(ctx->getWireDelay(unwrap_wire(wire)).maxDelay()); }
-    float npnr_context_delay_epsilon(const Context *const ctx) { return ctx->getDelayNS(ctx->getDelayEpsilon()); }
-    Loc npnr_context_get_pip_location(const Context *const ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
-    bool npnr_context_check_pip_avail_for_net(const Context *const ctx, uint64_t pip, NetInfo *net) { return ctx->checkPipAvailForNet(unwrap_pip(pip), net); }
-
-    // This method's in C++ temporarily, while I figure out some better way of getting a pip iterator.
-    Loc npnr_context_get_pip_direction(const Context *const ctx, uint64_t _pip) {
-        auto pip = unwrap_pip(_pip);
-        auto src_loc = Loc{};
-        auto dst_loc = Loc{};
-
-        auto uh_pips = 0;
-        for (auto uh : ctx->getPipsUphill(ctx->getPipSrcWire(pip))) {
-            auto loc = ctx->getPipLocation(uh);
-            src_loc.x += loc.x;
-            src_loc.y += loc.y;
-            uh_pips++;
-        }
-        if (uh_pips > 1) {
-            src_loc.x /= uh_pips;
-            src_loc.y /= uh_pips;
-        }
-
-        auto dh_pips = 0;
-        for (auto dh : ctx->getPipsDownhill(ctx->getPipDstWire(pip))) {
-            auto loc = ctx->getPipLocation(dh);
-            dst_loc.x += loc.x;
-            dst_loc.y += loc.y;
-            dh_pips++;
-        }
-        if (dh_pips > 1) {
-            dst_loc.x /= dh_pips;
-            dst_loc.y /= dh_pips;
-        }
-
-        dst_loc.x -= src_loc.x;
-        dst_loc.y -= src_loc.y;
-        return dst_loc;
-    }
-
-    uint64_t npnr_context_get_pips_leak(const Context *const ctx, PipId **pips) {
-        auto pip_vec = std::vector<PipId>{};
-        for (auto pip : ctx->getPips()) {
-            pip_vec.push_back(pip);
-        }
-        pip_vec.shrink_to_fit();
-        auto size = pip_vec.size();
-        *pips = pip_vec.data();
-        auto dummy = std::vector<PipId>{};
-        // Yes, by memcpying over `pip_vec` we leak memory.
-        std::memcpy(&pip_vec, &dummy, sizeof(dummy));
+    uint64_t npnr_context_get_pip_src_wire(const Context *ctx, uint64_t pip) { return wrap(ctx->getPipSrcWire(unwrap_pip(pip))); }
+    uint64_t npnr_context_get_pip_dst_wire(const Context *ctx, uint64_t pip) { return wrap(ctx->getPipDstWire(unwrap_pip(pip))); }
+    float npnr_context_estimate_delay(const Context *ctx, uint64_t src, uint64_t dst) { return ctx->getDelayNS(ctx->estimateDelay(unwrap_wire(src), unwrap_wire(dst))); }
+    float npnr_context_get_pip_delay(const Context *ctx, uint64_t pip) { return ctx->getDelayNS(ctx->getPipDelay(unwrap_pip(pip)).maxDelay()); }
+    float npnr_context_get_wire_delay(const Context *ctx, uint64_t wire) { return ctx->getDelayNS(ctx->getWireDelay(unwrap_wire(wire)).maxDelay()); }
+    float npnr_context_delay_epsilon(const Context *ctx) { return ctx->getDelayNS(ctx->getDelayEpsilon()); }
+    Loc npnr_context_get_pip_location(const Context *ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
+    bool npnr_context_check_pip_avail_for_net(const Context *ctx, uint64_t pip, NetInfo *net) { return ctx->checkPipAvailForNet(unwrap_pip(pip), net); }
+
+    uint64_t npnr_context_get_pips_leak(const Context *ctx, uint64_t **pips) {
+        auto size = size_t{};
+        for (auto _pip : ctx->getPips())
+            size++;
+        auto *pip_vec = new std::vector<uint64_t>{};
+        pip_vec->reserve(size);
+        for (auto pip : ctx->getPips())
+            pip_vec->push_back(wrap(pip));
+        *pips = pip_vec->data();
+        // Yes, by never deleting pip_vec, we leak memory.
         return size;
     }
 
-    uint64_t npnr_context_get_wires_leak(const Context *const ctx, WireId **wires) {
-        auto wire_vec = std::vector<WireId>{};
-        for (auto wire : ctx->getWires()) {
-            wire_vec.push_back(wire);
-        }
-        wire_vec.shrink_to_fit();
-        auto size = wire_vec.size();
-        *wires = wire_vec.data();
-        auto dummy = std::vector<WireId>{};
-        // Yes, by memcpying over `wire_vec` we leak memory.
-        std::memcpy(&wire_vec, &dummy, sizeof(dummy));
+    uint64_t npnr_context_get_wires_leak(const Context *ctx, uint64_t **wires) {
+        auto size = size_t{};
+        for (auto _wire : ctx->getWires())
+            size++;
+        auto *wire_vec = new std::vector<uint64_t>{};
+        wire_vec->reserve(size);
+        for (auto wire : ctx->getWires())
+            wire_vec->push_back(wrap(wire));
+        *wires = wire_vec->data();
+        // Yes, by never deleting wire_vec, we leak memory.
         return size;
     }
 
-    void npnr_context_check(const Context *const ctx) { ctx->check(); }
-    bool npnr_context_debug(const Context *const ctx) { return ctx->debug; }
-    int npnr_context_id(const Context *const ctx, const char *const str) { return ctx->id(str).hash(); }
-    const char *npnr_context_name_of(const Context *const ctx, IdString str) { return ctx->nameOf(str); }
-    const char *npnr_context_name_of_pip(const Context *const ctx, uint64_t pip) { return ctx->nameOfPip(unwrap_pip(pip)); }
-    const char *npnr_context_name_of_wire(const Context *const ctx, uint64_t wire) { return ctx->nameOfWire(unwrap_wire(wire)); }
-    bool npnr_context_verbose(const Context *const ctx) { return ctx->verbose; }
+    void npnr_context_check(const Context *ctx) { ctx->check(); }
+    bool npnr_context_debug(const Context *ctx) { return ctx->debug; }
+    int npnr_context_id(const Context *ctx, const char *str) { return ctx->id(str).hash(); }
+    const char *npnr_context_name_of(const Context *ctx, IdString str) { return ctx->nameOf(str); }
+    const char *npnr_context_name_of_pip(const Context *ctx, uint64_t pip) { return ctx->nameOfPip(unwrap_pip(pip)); }
+    const char *npnr_context_name_of_wire(const Context *ctx, uint64_t wire) { return ctx->nameOfWire(unwrap_wire(wire)); }
+    bool npnr_context_verbose(const Context *ctx) { return ctx->verbose; }
 
-    uint64_t npnr_context_get_netinfo_source_wire(const Context *const ctx, const NetInfo *const net) { return wrap(ctx->getNetinfoSourceWire(net)); }
-    uint64_t npnr_context_get_netinfo_sink_wire(const Context *const ctx, const NetInfo *const net, const PortRef *const sink, uint32_t n) { return wrap(ctx->getNetinfoSinkWire(net, *sink, n)); }
+    uint64_t npnr_context_get_netinfo_source_wire(const Context *ctx, const NetInfo *net) { return wrap(ctx->getNetinfoSourceWire(net)); }
+    uint64_t npnr_context_get_netinfo_sink_wire(const Context *ctx, const NetInfo *net, const PortRef *sink, uint32_t n) { return wrap(ctx->getNetinfoSinkWire(net, *sink, n)); }
 
-    uint32_t npnr_context_nets_leak(const Context *const ctx, int **names, NetInfo ***nets) {
-        auto name_vec = std::vector<int>{};
-        auto nets_vec = std::vector<NetInfo*>{};
+    uint32_t npnr_context_nets_leak(const Context *ctx, int **names, NetInfo ***nets) {
+        auto size = ctx->nets.size();
+        auto *name_vec = new std::vector<int>{};
+        auto *nets_vec = new std::vector<NetInfo*>{};
+        name_vec->reserve(size);
+        nets_vec->reserve(size);
         for (auto& item : ctx->nets) {
-            name_vec.push_back(item.first.hash());
-            nets_vec.push_back(item.second.get());
+            name_vec->push_back(item.first.hash());
+            nets_vec->push_back(item.second.get());
         }
-        name_vec.shrink_to_fit();
-        nets_vec.shrink_to_fit();
-        auto size = name_vec.size();
-        *names = name_vec.data();
-        *nets = nets_vec.data();
-        // Yes, by memcpying over `name_vec` and `nets_vec` we leak memory.
-        auto dummy1 = std::vector<int>{};
-        auto dummy2 = std::vector<NetInfo*>{};
-        std::memcpy(&name_vec, &dummy1, sizeof(dummy1));
-        std::memcpy(&nets_vec, &dummy2, sizeof(dummy2));
+        *names = name_vec->data();
+        *nets = nets_vec->data();
+        // Yes, by never deleting `name_vec` and `nets_vec` we leak memory.
         return size;
     }
 
@@ -259,14 +167,14 @@ extern "C" {
         delete iter;
     }
 
-    PortRef* npnr_netinfo_driver(NetInfo *const net) {
+    PortRef* npnr_netinfo_driver(NetInfo *net) {
         if (net == nullptr) {
             return nullptr;
         }
         return &net->driver;
     }
 
-    uint32_t npnr_netinfo_users_leak(NetInfo *const net, PortRef ***users) {
+    uint32_t npnr_netinfo_users_leak(NetInfo *net, PortRef ***users) {
         auto x = std::vector<PortRef*>{};
         for (auto& item : net->users) {
             x.push_back(&item);
@@ -281,16 +189,16 @@ extern "C" {
     }
 
 #ifdef ARCH_ECP5
-    bool npnr_netinfo_is_global(NetInfo *const net) { return net->is_global; }
+    bool npnr_netinfo_is_global(NetInfo *net) { return net->is_global; }
 #else
-    bool npnr_netinfo_is_global(NetInfo *const net) { return false; }
+    bool npnr_netinfo_is_global(NetInfo *net) { return false; }
 #endif
 
-    int32_t npnr_netinfo_udata(NetInfo *const net) { return net->udata; }
-    void npnr_netinfo_udata_set(NetInfo *const net, int32_t value) { net->udata = value; }
+    int32_t npnr_netinfo_udata(NetInfo *net) { return net->udata; }
+    void npnr_netinfo_udata_set(NetInfo *net, int32_t value) { net->udata = value; }
 
-    CellInfo* npnr_portref_cell(const PortRef *const port) { return port->cell; }
-    Loc npnr_cellinfo_get_location(const CellInfo *const info) { return info->getLocation(); }
+    CellInfo* npnr_portref_cell(const PortRef *port) { return port->cell; }
+    Loc npnr_cellinfo_get_location(const CellInfo *info) { return info->getLocation(); }
 
     void npnr_inc_downhill_iter(DownhillIterWrapper *iter) {
         ++iter->current;

From 49d505831dd63cdaaa00a3b0fb262bffb8b2c97a Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Sun, 31 Dec 2023 09:49:56 +0000
Subject: [PATCH 539/712] second round of review fixes

---
 rust/rust.cc | 54 +++++++++++++++++++++++++---------------------------
 1 file changed, 26 insertions(+), 28 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 41866124d2..89c6055e5a 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -101,11 +101,12 @@ extern "C" {
         auto size = size_t{};
         for (auto _pip : ctx->getPips())
             size++;
-        auto *pip_vec = new std::vector<uint64_t>{};
-        pip_vec->reserve(size);
-        for (auto pip : ctx->getPips())
-            pip_vec->push_back(wrap(pip));
-        *pips = pip_vec->data();
+        *pips = new uint64_t[size];
+        auto idx = 0;
+        for (auto pip : ctx->getPips()) {
+            *pips[idx] = wrap(pip);
+            idx++;
+        }
         // Yes, by never deleting pip_vec, we leak memory.
         return size;
     }
@@ -114,12 +115,13 @@ extern "C" {
         auto size = size_t{};
         for (auto _wire : ctx->getWires())
             size++;
-        auto *wire_vec = new std::vector<uint64_t>{};
-        wire_vec->reserve(size);
-        for (auto wire : ctx->getWires())
-            wire_vec->push_back(wrap(wire));
-        *wires = wire_vec->data();
-        // Yes, by never deleting wire_vec, we leak memory.
+        *wires = new uint64_t[size];
+        auto idx = 0;
+        for (auto wire : ctx->getWires()) {
+            *wires[idx] = wrap(wire);
+            idx++;
+        }
+        // Yes, by never deleting wires, we leak memory.
         return size;
     }
 
@@ -136,17 +138,15 @@ extern "C" {
 
     uint32_t npnr_context_nets_leak(const Context *ctx, int **names, NetInfo ***nets) {
         auto size = ctx->nets.size();
-        auto *name_vec = new std::vector<int>{};
-        auto *nets_vec = new std::vector<NetInfo*>{};
-        name_vec->reserve(size);
-        nets_vec->reserve(size);
+        *names = new int[size];
+        *nets = new NetInfo*[size];
+        auto idx = 0;
         for (auto& item : ctx->nets) {
-            name_vec->push_back(item.first.hash());
-            nets_vec->push_back(item.second.get());
+            *names[idx] = item.first.hash();
+            *nets[idx] = item.second.get();
+            idx++;
         }
-        *names = name_vec->data();
-        *nets = nets_vec->data();
-        // Yes, by never deleting `name_vec` and `nets_vec` we leak memory.
+        // Yes, by never deleting `names` and `nets` we leak memory.
         return size;
     }
 
@@ -175,16 +175,14 @@ extern "C" {
     }
 
     uint32_t npnr_netinfo_users_leak(NetInfo *net, PortRef ***users) {
-        auto x = std::vector<PortRef*>{};
+        auto size = net->users.entries();
+        *users = new PortRef*[size];
+        auto idx = 0;
         for (auto& item : net->users) {
-            x.push_back(&item);
+            *users[idx] = &item;
+            idx++;
         }
-        x.shrink_to_fit();
-        *users = x.data();
-        auto size = x.size();
-        // Yes, by memcpying over `x` we leak memory.
-        auto dummy = std::vector<PortRef*>{};
-        std::memcpy(&x, &dummy, sizeof(dummy));
+        // Yes, by not freeing `users`, we leak memory.
         return size;
     }
 

From 1bbcc5f2c4b83c07997509eedb95410387edc2da Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 2 Jan 2024 20:15:42 +0000
Subject: [PATCH 540/712] (broken) third round of review fixes

---
 common/kernel/pybindings.cc | 4 ++++
 ice40/arch.cc               | 6 ------
 rust/rust.cc                | 2 +-
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index db233c1c9c..8cf8e4248d 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -25,6 +25,7 @@
 #include "json_frontend.h"
 #include "log.h"
 #include "nextpnr.h"
+#include "rust.h"
 
 #include <fstream>
 #include <memory>
@@ -248,6 +249,9 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
 
     m.def("parse_json", parse_json_shim);
     m.def("load_design", load_design_shim, py::return_value_policy::take_ownership);
+#ifdef USE_RUST
+    m.def("example_printnets", example_printnets);
+#endif
 
     auto region_cls = py::class_<ContextualWrapper<Region &>>(m, "Region");
     readwrite_wrapper<Region &, decltype(&Region::name), &Region::name, conv_to_str<IdString>,
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 1f8577fd67..a77dd611ac 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -643,12 +643,6 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 bool Arch::place()
 {
-#ifdef USE_RUST
-    log_info("Calling Rust\n");
-    example_printnets(getCtx());
-    log_info("Returned from Rust\n");
-#endif
-
     std::string placer = str_or_default(settings, id_placer, defaultPlacer);
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
diff --git a/rust/rust.cc b/rust/rust.cc
index 89c6055e5a..9f1c6bf10a 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -142,7 +142,7 @@ extern "C" {
         *nets = new NetInfo*[size];
         auto idx = 0;
         for (auto& item : ctx->nets) {
-            *names[idx] = item.first.hash();
+            *names[idx] = item.first.index;
             *nets[idx] = item.second.get();
             idx++;
         }

From e12ab86c75e62b4c51dc838a3470d87ec29e575c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 3 Jan 2024 11:01:23 +0100
Subject: [PATCH 541/712] rust: Fix segfault

Signed-off-by: gatecat <gatecat@ds0.me>
---
 rust/rust.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 9f1c6bf10a..4a1da958d2 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -104,7 +104,7 @@ extern "C" {
         *pips = new uint64_t[size];
         auto idx = 0;
         for (auto pip : ctx->getPips()) {
-            *pips[idx] = wrap(pip);
+            (*pips)[idx] = wrap(pip);
             idx++;
         }
         // Yes, by never deleting pip_vec, we leak memory.
@@ -118,7 +118,7 @@ extern "C" {
         *wires = new uint64_t[size];
         auto idx = 0;
         for (auto wire : ctx->getWires()) {
-            *wires[idx] = wrap(wire);
+            (*wires)[idx] = wrap(wire);
             idx++;
         }
         // Yes, by never deleting wires, we leak memory.
@@ -142,8 +142,8 @@ extern "C" {
         *nets = new NetInfo*[size];
         auto idx = 0;
         for (auto& item : ctx->nets) {
-            *names[idx] = item.first.index;
-            *nets[idx] = item.second.get();
+            (*names)[idx] = item.first.index;
+            (*nets)[idx] = item.second.get();
             idx++;
         }
         // Yes, by never deleting `names` and `nets` we leak memory.
@@ -179,7 +179,7 @@ extern "C" {
         *users = new PortRef*[size];
         auto idx = 0;
         for (auto& item : net->users) {
-            *users[idx] = &item;
+            (*users)[idx] = &item;
             idx++;
         }
         // Yes, by not freeing `users`, we leak memory.

From 50d43742ce47f6039dba2db97d3821798d7172d9 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 3 Jan 2024 12:55:46 +0000
Subject: [PATCH 542/712] rust: silence warnings

---
 rust/rust.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 4a1da958d2..25aa63e138 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -22,6 +22,9 @@
 namespace {
     USING_NEXTPNR_NAMESPACE;
 
+    // `memcpy` is used here to avoid strict-aliasing problems, but GCC dislikes it.
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wclass-memaccess"
     template<typename T>
     uint64_t wrap(T thing) {
         static_assert(sizeof(T) <= 8, "T is too big for FFI");
@@ -50,6 +53,7 @@ namespace {
         memcpy(&w, &wire, sizeof(WireId));
         return w;
     }
+#pragma GCC diagnostic pop
 }
 
 using DownhillIter = decltype(Context(ArchArgs()).getPipsDownhill(WireId()).begin());
@@ -99,8 +103,10 @@ extern "C" {
 
     uint64_t npnr_context_get_pips_leak(const Context *ctx, uint64_t **pips) {
         auto size = size_t{};
-        for (auto _pip : ctx->getPips())
+        for (auto _pip : ctx->getPips()) {
+            NPNR_UNUSED(_pip);
             size++;
+        }
         *pips = new uint64_t[size];
         auto idx = 0;
         for (auto pip : ctx->getPips()) {
@@ -113,8 +119,10 @@ extern "C" {
 
     uint64_t npnr_context_get_wires_leak(const Context *ctx, uint64_t **wires) {
         auto size = size_t{};
-        for (auto _wire : ctx->getWires())
+        for (auto _wire : ctx->getWires()) {
+            NPNR_UNUSED(_wire);
             size++;
+        }
         *wires = new uint64_t[size];
         auto idx = 0;
         for (auto wire : ctx->getWires()) {

From 7fd80c5a927ae8cdaa9102dedd953ba937a4a1f4 Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:02:59 +0000
Subject: [PATCH 543/712] common/kernel: Fixed unused parameters and spurious
 `;` warnings in some of the headers

---
 common/kernel/base_arch.h     | 54 +++++++++++++++++------------------
 common/kernel/command.h       |  8 +++---
 common/kernel/idstringlist.h  |  8 +++---
 common/kernel/nextpnr_types.h | 44 ++++++++++++++--------------
 common/kernel/pycontainers.h  | 10 +++----
 common/kernel/pywrappers.h    | 10 +++----
 common/place/timing_opt.h     |  2 +-
 7 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 94f88af700..fa852a7ce1 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -143,8 +143,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
 
     // Basic config
     virtual IdString archId() const override { return this->id(NPNR_STRINGIFY(ARCHNAME)); }
-    virtual IdString archArgsToId(typename R::ArchArgsT args) const override { return IdString(); }
-    virtual int getTilePipDimZ(int x, int y) const override { return 1; }
+    virtual IdString archArgsToId(typename R::ArchArgsT /*args*/) const override { return IdString(); }
+    virtual int getTilePipDimZ(int /*x*/, int /*y*/) const override { return 1; }
     virtual char getNameDelimiter() const override { return ' '; }
 
     // Bel methods
@@ -170,9 +170,9 @@ template <typename R> struct BaseArch : ArchAPI<R>
         this->refreshUiBel(bel);
     }
 
-    virtual bool getBelHidden(BelId bel) const override { return false; }
+    virtual bool getBelHidden(BelId /*bel*/) const override { return false; }
 
-    virtual bool getBelGlobalBuf(BelId bel) const override { return false; }
+    virtual bool getBelGlobalBuf(BelId /*bel*/) const override { return false; }
     virtual bool checkBelAvail(BelId bel) const override { return getBoundBelCell(bel) == nullptr; };
     virtual CellInfo *getBoundBelCell(BelId bel) const override
     {
@@ -180,18 +180,18 @@ template <typename R> struct BaseArch : ArchAPI<R>
         return fnd == base_bel2cell.end() ? nullptr : fnd->second;
     }
     virtual CellInfo *getConflictingBelCell(BelId bel) const override { return getBoundBelCell(bel); }
-    virtual typename R::BelAttrsRangeT getBelAttrs(BelId bel) const override
+    virtual typename R::BelAttrsRangeT getBelAttrs(BelId /*bel*/) const override
     {
         return empty_if_possible<typename R::BelAttrsRangeT>();
     }
 
-    virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override
+    virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo * /*cell_info*/, IdString pin) const override
     {
         return return_if_match<std::array<IdString, 1>, typename R::CellBelPinRangeT>({pin});
     }
 
     // Wire methods
-    virtual IdString getWireType(WireId wire) const override { return IdString(); }
+    virtual IdString getWireType(WireId /*wire*/) const override { return IdString(); }
     virtual typename R::WireAttrsRangeT getWireAttrs(WireId) const override
     {
         return empty_if_possible<typename R::WireAttrsRangeT>();
@@ -237,10 +237,10 @@ template <typename R> struct BaseArch : ArchAPI<R>
     }
     virtual WireId getConflictingWireWire(WireId wire) const override { return wire; };
     virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); }
-    virtual IdString getWireConstantValue(WireId wire) const override { return {}; }
+    virtual IdString getWireConstantValue(WireId /*wire*/) const override { return {}; }
 
     // Pip methods
-    virtual IdString getPipType(PipId pip) const override { return IdString(); }
+    virtual IdString getPipType(PipId /*pip*/) const override { return IdString(); }
     virtual typename R::PipAttrsRangeT getPipAttrs(PipId) const override
     {
         return empty_if_possible<typename R::PipAttrsRangeT>();
@@ -285,60 +285,60 @@ template <typename R> struct BaseArch : ArchAPI<R>
         auto fnd = base_pip2net.find(pip);
         return fnd == base_pip2net.end() ? nullptr : fnd->second;
     }
-    virtual WireId getConflictingPipWire(PipId pip) const override { return WireId(); }
+    virtual WireId getConflictingPipWire(PipId /*pip*/) const override { return WireId(); }
     virtual NetInfo *getConflictingPipNet(PipId pip) const override { return getBoundPipNet(pip); }
 
     // Group methods
-    virtual GroupId getGroupByName(IdStringList name) const override { return GroupId(); };
-    virtual IdStringList getGroupName(GroupId group) const override { return IdStringList(); };
+    virtual GroupId getGroupByName(IdStringList /*name*/) const override { return GroupId(); };
+    virtual IdStringList getGroupName(GroupId /*group*/) const override { return IdStringList(); };
     virtual typename R::AllGroupsRangeT getGroups() const override
     {
         return empty_if_possible<typename R::AllGroupsRangeT>();
     }
     // Default implementation of these assumes no groups so never called
-    virtual typename R::GroupBelsRangeT getGroupBels(GroupId group) const override
+    virtual typename R::GroupBelsRangeT getGroupBels(GroupId /*group*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     };
-    virtual typename R::GroupWiresRangeT getGroupWires(GroupId group) const override
+    virtual typename R::GroupWiresRangeT getGroupWires(GroupId /*group*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     };
-    virtual typename R::GroupPipsRangeT getGroupPips(GroupId group) const override
+    virtual typename R::GroupPipsRangeT getGroupPips(GroupId /*group*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     };
-    virtual typename R::GroupGroupsRangeT getGroupGroups(GroupId group) const override
+    virtual typename R::GroupGroupsRangeT getGroupGroups(GroupId /*group*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     };
 
     // Delay methods
-    virtual bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const override
+    virtual bool getArcDelayOverride(const NetInfo * /*net_info*/, const PortRef &/*sink*/, DelayQuad &/*delay*/) const override
     {
         return false;
     }
 
     // Decal methods
-    virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId decal) const override
+    virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId /*decal*/) const override
     {
         return empty_if_possible<typename R::DecalGfxRangeT>();
     };
-    virtual DecalXY getBelDecal(BelId bel) const override { return DecalXY(); }
-    virtual DecalXY getWireDecal(WireId wire) const override { return DecalXY(); }
-    virtual DecalXY getPipDecal(PipId pip) const override { return DecalXY(); }
-    virtual DecalXY getGroupDecal(GroupId group) const override { return DecalXY(); }
+    virtual DecalXY getBelDecal(BelId /*bel*/) const override { return DecalXY(); }
+    virtual DecalXY getWireDecal(WireId /*wire*/) const override { return DecalXY(); }
+    virtual DecalXY getPipDecal(PipId /*pip*/) const override { return DecalXY(); }
+    virtual DecalXY getGroupDecal(GroupId /*group*/) const override { return DecalXY(); }
 
     // Cell timing methods
-    virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override
+    virtual bool getCellDelay(const CellInfo * /*cell*/, IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override
     {
         return false;
     }
-    virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override
+    virtual TimingPortClass getPortTimingClass(const CellInfo * /*cell*/, IdString /*port*/, int &/*clockInfoCount*/) const override
     {
         return TMG_IGNORE;
     }
-    virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override
+    virtual TimingClockingInfo getPortClockingInfo(const CellInfo * /*cell*/, IdString /*port*/, int /*index*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     }
@@ -358,7 +358,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
     {
         return getBelBucketByName(cell_type);
     };
-    virtual bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override { return true; }
+    virtual bool isBelLocationValid(BelId /*bel*/, bool /*explain_invalid*/ = false) const override { return true; }
     virtual typename R::CellTypeRangeT getCellTypes() const override
     {
         NPNR_ASSERT(cell_types_initialised);
@@ -400,7 +400,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
                                          [](const BaseClusterInfo *c) { return Loc(c->constr_x, c->constr_y, 0); });
     }
 
-    virtual bool isClusterStrict(const CellInfo *cell) const override { return true; }
+    virtual bool isClusterStrict(const CellInfo * /*cell*/) const override { return true; }
 
     virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
                                      std::vector<std::pair<CellInfo *, BelId>> &placement) const override
diff --git a/common/kernel/command.h b/common/kernel/command.h
index 8e0e886d73..5f173e5590 100644
--- a/common/kernel/command.h
+++ b/common/kernel/command.h
@@ -34,7 +34,7 @@ class CommandHandler
 {
   public:
     CommandHandler(int argc, char **argv);
-    virtual ~CommandHandler(){};
+    virtual ~CommandHandler() { }
 
     int exec();
     void load_json(Context *ctx, std::string filename);
@@ -45,9 +45,9 @@ class CommandHandler
     virtual void setupArchContext(Context *ctx) = 0;
     virtual std::unique_ptr<Context> createContext(dict<std::string, Property> &values) = 0;
     virtual po::options_description getArchOptions() = 0;
-    virtual void validate(){};
-    virtual void customAfterLoad(Context *ctx){};
-    virtual void customBitstream(Context *ctx){};
+    virtual void validate() { }
+    virtual void customAfterLoad(Context * /*ctx*/) { }
+    virtual void customBitstream(Context * /*ctx*/) { }
     void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2);
 
   private:
diff --git a/common/kernel/idstringlist.h b/common/kernel/idstringlist.h
index 5e462d0e8d..b8e37966fe 100644
--- a/common/kernel/idstringlist.h
+++ b/common/kernel/idstringlist.h
@@ -35,10 +35,10 @@ struct IdStringList
 {
     SSOArray<IdString, 4> ids;
 
-    IdStringList() : ids(1, IdString()){};
-    explicit IdStringList(size_t n) : ids(n, IdString()){};
-    explicit IdStringList(IdString id) : ids(1, id){};
-    template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list){};
+    IdStringList() : ids(1, IdString()) { }
+    explicit IdStringList(size_t n) : ids(n, IdString()) { }
+    explicit IdStringList(IdString id) : ids(1, id) { }
+    template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list) { }
 
     static IdStringList parse(Context *ctx, const std::string &str);
     void build_str(const Context *ctx, std::string &str) const;
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 4c9dba600a..5a239ca17d 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -81,10 +81,10 @@ struct PortRef
 struct DelayPair
 {
     DelayPair(){};
-    explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay){};
-    DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay){};
-    delay_t minDelay() const { return min_delay; };
-    delay_t maxDelay() const { return max_delay; };
+    explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) { }
+    DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) { }
+    delay_t minDelay() const { return min_delay; }
+    delay_t maxDelay() const { return max_delay; }
     delay_t min_delay, max_delay;
     DelayPair operator+(const DelayPair &other) const
     {
@@ -100,21 +100,21 @@ struct DelayPair
 struct DelayQuad
 {
     DelayPair rise, fall;
-    DelayQuad(){};
-    explicit DelayQuad(delay_t delay) : rise(delay), fall(delay){};
-    DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay){};
-    DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall){};
+    DelayQuad() { }
+    explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) { }
+    DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) { }
+    DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) { }
     DelayQuad(delay_t min_rise, delay_t max_rise, delay_t min_fall, delay_t max_fall)
-            : rise(min_rise, max_rise), fall(min_fall, max_fall){};
+            : rise(min_rise, max_rise), fall(min_fall, max_fall) { }
 
-    delay_t minRiseDelay() const { return rise.minDelay(); };
-    delay_t maxRiseDelay() const { return rise.maxDelay(); };
-    delay_t minFallDelay() const { return fall.minDelay(); };
-    delay_t maxFallDelay() const { return fall.maxDelay(); };
-    delay_t minDelay() const { return std::min<delay_t>(rise.minDelay(), fall.minDelay()); };
-    delay_t maxDelay() const { return std::max<delay_t>(rise.maxDelay(), fall.maxDelay()); };
+    delay_t minRiseDelay() const { return rise.minDelay(); }
+    delay_t maxRiseDelay() const { return rise.maxDelay(); }
+    delay_t minFallDelay() const { return fall.minDelay(); }
+    delay_t maxFallDelay() const { return fall.maxDelay(); }
+    delay_t minDelay() const { return std::min<delay_t>(rise.minDelay(), fall.minDelay()); }
+    delay_t maxDelay() const { return std::max<delay_t>(rise.maxDelay(), fall.maxDelay()); }
 
-    DelayPair delayPair() const { return DelayPair(minDelay(), maxDelay()); };
+    DelayPair delayPair() const { return DelayPair(minDelay(), maxDelay()); }
 
     DelayQuad operator+(const DelayQuad &other) const { return {rise + other.rise, fall + other.fall}; }
     DelayQuad operator-(const DelayQuad &other) const { return {rise - other.rise, fall - other.fall}; }
@@ -124,7 +124,7 @@ struct ClockConstraint;
 
 struct NetInfo : ArchNetInfo
 {
-    explicit NetInfo(IdString name) : name(name){};
+    explicit NetInfo(IdString name) : name(name) { }
     IdString name, hierpath;
     int32_t udata = 0;
 
@@ -203,14 +203,14 @@ struct PseudoCell
 
 struct RegionPlug : PseudoCell
 {
-    RegionPlug(Loc loc) : loc(loc){}; // 'loc' is a notional location for the placer only
+    RegionPlug(Loc loc) : loc(loc) { } // 'loc' is a notional location for the placer only
     Loc getLocation() const override { return loc; }
     WireId getPortWire(IdString port) const override { return port_wires.at(port); }
 
     // TODO: partial reconfiguration region timing
-    bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const override { return false; }
-    TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const override { return TMG_IGNORE; }
-    TimingClockingInfo getPortClockingInfo(IdString port, int index) const override { return TimingClockingInfo{}; }
+    bool getDelay(IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override { return false; }
+    TimingPortClass getPortTimingClass(IdString /*port*/, int &/*clockInfoCount*/) const override { return TMG_IGNORE; }
+    TimingClockingInfo getPortClockingInfo(IdString /*port*/, int /*index*/) const override { return TimingClockingInfo{}; }
 
     dict<IdString, WireId> port_wires;
     Loc loc;
@@ -218,7 +218,7 @@ struct RegionPlug : PseudoCell
 
 struct CellInfo : ArchCellInfo
 {
-    CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type){};
+    CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type) { }
     Context *ctx = nullptr;
 
     IdString name, type, hierpath;
diff --git a/common/kernel/pycontainers.h b/common/kernel/pycontainers.h
index ff49c34cbf..626849ceea 100644
--- a/common/kernel/pycontainers.h
+++ b/common/kernel/pycontainers.h
@@ -290,7 +290,7 @@ template <typename T1, typename T2> struct pair_wrapper
             x.second = val.cast<T2>();
     }
 
-    static int len(T &x) { return 2; }
+    static int len(T &/*x*/) { return 2; }
 
     static iter_pair<T &, int> iter(T &x) { return iter_pair<T &, int>(boost::ref(x), 0); };
 
@@ -348,7 +348,7 @@ template <typename T1, typename T2, typename value_conv> struct map_pair_wrapper
                                                                                                        x.base.first));
     }
 
-    static int len(wrapped_pair &x) { return 2; }
+    static int len(wrapped_pair &/*x*/) { return 2; }
 
     static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
     {
@@ -469,14 +469,14 @@ template <typename T1, typename T2> struct map_pair_wrapper_uptr
 
     static py::object get(wrapped_pair &x, int i)
     {
-        if ((i >= 2) || (i < 0))
+        if (i >= 2 || i < 0)
             KeyError();
-        return (i == 1) ? py::cast(PythonConversion::ContextualWrapper<V &>(x.ctx, *x.base.second.get()))
+        return i == 1 ? py::cast(PythonConversion::ContextualWrapper<V &>(x.ctx, *x.base.second.get()))
                         : py::cast(PythonConversion::string_converter<decltype(x.base.first)>().to_str(x.ctx,
                                                                                                        x.base.first));
     }
 
-    static int len(wrapped_pair &x) { return 2; }
+    static int len(wrapped_pair &/*x*/) { return 2; }
 
     static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
     {
diff --git a/common/kernel/pywrappers.h b/common/kernel/pywrappers.h
index 60ef65be7c..69b9419786 100644
--- a/common/kernel/pywrappers.h
+++ b/common/kernel/pywrappers.h
@@ -35,9 +35,9 @@ template <typename T> struct ContextualWrapper
     Context *ctx;
     T base;
 
-    inline ContextualWrapper(Context *c, T x) : ctx(c), base(x){};
+    inline ContextualWrapper(Context *c, T x) : ctx(c), base(x) { }
 
-    inline operator T() { return base; };
+    inline operator T() { return base; }
     typedef T base_type;
 };
 
@@ -83,7 +83,7 @@ class bad_wrap
 // Action options
 template <typename T> struct pass_through
 {
-    inline T operator()(Context *ctx, T x) { return x; }
+    inline T operator()(Context * /*ctx*/, T x) { return x; }
 
     using ret_type = T;
     using arg_type = T;
@@ -99,7 +99,7 @@ template <typename T> struct wrap_context
 
 template <typename T> struct unwrap_context
 {
-    inline T operator()(Context *ctx, ContextualWrapper<T> x) { return x.base; }
+    inline T operator()(Context * /*ctx*/, ContextualWrapper<T> x) { return x.base; }
 
     using ret_type = T;
     using arg_type = ContextualWrapper<T>;
@@ -136,7 +136,7 @@ template <typename T> struct deref_and_wrap
 
 template <typename T> struct addr_and_unwrap
 {
-    inline T *operator()(Context *ctx, ContextualWrapper<T &> x) { return &(x.base); }
+    inline T *operator()(Context * /*ctx*/, ContextualWrapper<T &> x) { return &(x.base); }
 
     using arg_type = ContextualWrapper<T &>;
     using ret_type = T *;
diff --git a/common/place/timing_opt.h b/common/place/timing_opt.h
index 8f8bc7092f..e5d0fd3864 100644
--- a/common/place/timing_opt.h
+++ b/common/place/timing_opt.h
@@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct TimingOptCfg
 {
-    TimingOptCfg(Context *ctx) {}
+    TimingOptCfg(Context * /*ctx*/) { }
 
     // The timing optimiser will *only* optimise cells of these types
     // Normally these would only be logic cells (or tiles if applicable), the algorithm makes little sense

From cb4db2d368049a1b7cef0f1a6efc6efc62717e1b Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:03:16 +0000
Subject: [PATCH 544/712] ice40: Fixed unused parameters and spurious `;`
 warnings in some of the headers

---
 ice40/arch_pybindings.h |  2 +-
 ice40/cells.h           | 42 ++++++++++++++++++++---------------------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/ice40/arch_pybindings.h b/ice40/arch_pybindings.h
index 032d42fe49..6796ca3695 100644
--- a/ice40/arch_pybindings.h
+++ b/ice40/arch_pybindings.h
@@ -78,7 +78,7 @@ template <> struct string_converter<PipId>
 
 template <> struct string_converter<BelPin>
 {
-    BelPin from_str(Context *ctx, std::string name)
+    BelPin from_str(Context * /*ctx*/, std::string /*name*/)
     {
         NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
     }
diff --git a/ice40/cells.h b/ice40/cells.h
index 8aed649de3..56c8bd052c 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -30,61 +30,61 @@ NEXTPNR_NAMESPACE_BEGIN
 std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::string name = "");
 
 // Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LUT4; }
+inline bool is_lut(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_LUT4; }
 
 // Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
+inline bool is_ff(const BaseCtx * /*ctx*/, const CellInfo *cell)
 {
     return cell->type.in(id_SB_DFF, id_SB_DFFE, id_SB_DFFSR, id_SB_DFFR, id_SB_DFFSS, id_SB_DFFS, id_SB_DFFESR,
                          id_SB_DFFER, id_SB_DFFESS, id_SB_DFFES, id_SB_DFFN, id_SB_DFFNE, id_SB_DFFNSR, id_SB_DFFNR,
                          id_SB_DFFNSS, id_SB_DFFNS, id_SB_DFFNESR, id_SB_DFFNER, id_SB_DFFNESS, id_SB_DFFNES);
 }
 
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_CARRY; }
+inline bool is_carry(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_CARRY; }
 
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_ICESTORM_LC; }
+inline bool is_lc(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_ICESTORM_LC; }
 
 // Return true if a cell is a SB_IO
-inline bool is_sb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_IO; }
+inline bool is_sb_io(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_IO; }
 
 // Return true if a cell is a SB_GB_IO
-inline bool is_sb_gb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_GB_IO; }
+inline bool is_sb_gb_io(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_GB_IO; }
 
 // Return true if a cell is a global buffer
-inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_GB; }
+inline bool is_gbuf(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_GB; }
 
 // Return true if a cell is a RAM
-inline bool is_ram(const BaseCtx *ctx, const CellInfo *cell)
+inline bool is_ram(const BaseCtx * /*ctx*/, const CellInfo *cell)
 {
     return cell->type.in(id_SB_RAM40_4K, id_SB_RAM40_4KNR, id_SB_RAM40_4KNW, id_SB_RAM40_4KNRNW);
 }
 
-inline bool is_sb_lfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LFOSC; }
+inline bool is_sb_lfosc(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_LFOSC; }
 
-inline bool is_sb_hfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_HFOSC; }
+inline bool is_sb_hfosc(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_HFOSC; }
 
-inline bool is_sb_spram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_SPRAM256KA; }
+inline bool is_sb_spram(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_SPRAM256KA; }
 
-inline bool is_sb_mac16(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_MAC16; }
+inline bool is_sb_mac16(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_MAC16; }
 
-inline bool is_sb_rgba_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_RGBA_DRV; }
+inline bool is_sb_rgba_drv(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_RGBA_DRV; }
 
-inline bool is_sb_rgb_drv(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_RGB_DRV; }
+inline bool is_sb_rgb_drv(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_RGB_DRV; }
 
-inline bool is_sb_led_drv_cur(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LED_DRV_CUR; }
+inline bool is_sb_led_drv_cur(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_LED_DRV_CUR; }
 
-inline bool is_sb_ledda_ip(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LEDDA_IP; }
+inline bool is_sb_ledda_ip(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_LEDDA_IP; }
 
-inline bool is_sb_i2c(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_I2C; }
+inline bool is_sb_i2c(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_I2C; }
 
-inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_SPI; }
+inline bool is_sb_spi(const BaseCtx * /*ctx*/, const CellInfo *cell) { return cell->type == id_SB_SPI; }
 
-inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell)
+inline bool is_sb_pll40(const BaseCtx * /*ctx*/, const CellInfo *cell)
 {
     return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_CORE, id_SB_PLL40_2F_CORE);
 }
 
-inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
+inline bool is_sb_pll40_pad(const BaseCtx * /*ctx*/, const CellInfo *cell)
 {
     return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD) ||
            (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_PAD" ||
@@ -92,7 +92,7 @@ inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
                                               cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD"));
 }
 
-inline bool is_sb_pll40_dual(const BaseCtx *ctx, const CellInfo *cell)
+inline bool is_sb_pll40_dual(const BaseCtx * /*ctx*/, const CellInfo *cell)
 {
     return cell->type.in(id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_2F_CORE) ||
            (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" ||

From e9c69ac00ca6493d1dab89c4bfe786fa9879fabe Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:03:28 +0000
Subject: [PATCH 545/712] gui: Fixed unused parameters and spurious `;`
 warnings in one of the headers

---
 gui/treemodel.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gui/treemodel.h b/gui/treemodel.h
index 79e6e3f7ab..915258a6f3 100644
--- a/gui/treemodel.h
+++ b/gui/treemodel.h
@@ -71,7 +71,7 @@ class Item
         if (parent_ != nullptr) {
             parent_->addChild(this);
         }
-    };
+    }
 
     // Number of children.
     int count() const { return children_.count(); }
@@ -102,9 +102,9 @@ class Item
     virtual bool canFetchMore() const { return false; }
     virtual void fetchMore() {}
 
-    virtual boost::optional<Item *> getById(IdStringList id) { return boost::none; }
-    virtual void search(QList<Item *> &results, QString text, int limit) {}
-    virtual void updateElements(Context *ctx, std::vector<IdStringList> elements) {}
+    virtual boost::optional<Item *> getById(IdStringList /*id*/) { return boost::none; }
+    virtual void search(QList<Item *> &/*results*/, QString /*text*/, int /*limit*/) { }
+    virtual void updateElements(Context * /*ctx*/, std::vector<IdStringList> /*elements*/) { }
 
     virtual ~Item()
     {
@@ -147,7 +147,7 @@ class IdList : public Item
   public:
     // Create an IdList at given parent that will contain elements of
     // the given type.
-    IdList(ElementType type) : Item("root", nullptr), child_type_(type) {}
+    IdList(ElementType type) : Item("root", nullptr), child_type_(type) { }
 
     // Split a name into alpha/non-alpha parts, which is then used for sorting
     // of children.

From 7d0c4eaf1b83480695cee9206dce19b539cb3f12 Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:04:29 +0000
Subject: [PATCH 546/712] rust: Reworked `npnr_context_get_wires_leak()` using
 std::accumulate() and fixed an accidental copy problem

---
 rust/rust.cc | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 25aa63e138..d7032b742b 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -16,6 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <numeric>
 #include "log.h"
 #include "nextpnr.h"
 
@@ -117,15 +118,15 @@ extern "C" {
         return size;
     }
 
-    uint64_t npnr_context_get_wires_leak(const Context *ctx, uint64_t **wires) {
-        auto size = size_t{};
-        for (auto _wire : ctx->getWires()) {
-            NPNR_UNUSED(_wire);
-            size++;
-        }
+    uint64_t npnr_context_get_wires_leak(const Context *const ctx, uint64_t **const wires) {
+        const auto ctx_wires{ctx->getWires()};
+        const auto size{
+            std::accumulate(ctx_wires.begin(), ctx_wires.end(), /*initial value*/ size_t{},
+                [](size_t value, const auto &/*wire*/) { return value + 1U; }
+        )};
         *wires = new uint64_t[size];
         auto idx = 0;
-        for (auto wire : ctx->getWires()) {
+        for (const auto &wire : ctx_wires) {
             (*wires)[idx] = wrap(wire);
             idx++;
         }

From cfeb588d32a2ede30903037c1b064c8abda5c42b Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:04:43 +0000
Subject: [PATCH 547/712] rust: Reworked `npnr_context_get_pips_leak()` using
 std::accumulate() and fixed an accidental copy problem

---
 rust/rust.cc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index d7032b742b..23286a6854 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -102,15 +102,15 @@ extern "C" {
     Loc npnr_context_get_pip_location(const Context *ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
     bool npnr_context_check_pip_avail_for_net(const Context *ctx, uint64_t pip, NetInfo *net) { return ctx->checkPipAvailForNet(unwrap_pip(pip), net); }
 
-    uint64_t npnr_context_get_pips_leak(const Context *ctx, uint64_t **pips) {
-        auto size = size_t{};
-        for (auto _pip : ctx->getPips()) {
-            NPNR_UNUSED(_pip);
-            size++;
-        }
+    uint64_t npnr_context_get_pips_leak(const Context *const ctx, uint64_t **const pips) {
+        const auto ctx_pips{ctx->getPips()};
+        const auto size{
+            std::accumulate(ctx_pips.begin(), ctx_pips.end(), /*initial value*/ size_t{},
+                [](size_t value, const auto &/*pip*/) { return value + 1U; }
+        )};
         *pips = new uint64_t[size];
         auto idx = 0;
-        for (auto pip : ctx->getPips()) {
+        for (const auto &pip : ctx_pips) {
             (*pips)[idx] = wrap(pip);
             idx++;
         }

From 3e46fbc655421f1d40d0984d701925e81937402d Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:07:22 +0000
Subject: [PATCH 548/712] rust: Reworked the unwrap helpers by effectively
 hiding the crime of memcpy()'ing into a non-POD type from the compiler There
 is still the possibility that this can explode horribly, but the result
 should be the same codegen and fixes the warning

This also makes the helpers `inline` so they'll usually be compiled out for a nice speed boost
---
 rust/rust.cc | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 23286a6854..279884d07e 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -16,6 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <array>
 #include <numeric>
 #include "log.h"
 #include "nextpnr.h"
@@ -33,28 +34,30 @@ namespace {
         memcpy(&b, &thing, sizeof(T));
         return b;
     }
+#pragma GCC diagnostic pop
 
-    BelId unwrap_bel(uint64_t bel) {
-        static_assert(sizeof(BelId) <= 8, "T is too big for FFI");
-        auto b = BelId();
-        memcpy(&b, &bel, sizeof(BelId));
-        return b;
+    template<typename T> static inline T unwrap(const std::array<uint8_t, 8> &value) noexcept {
+        static_assert(sizeof(T) <= 8, "T is too big for FFI");
+        T result{};
+        memcpy(&result, value.data(), sizeof(result));
+        return result;
     }
 
-    PipId unwrap_pip(uint64_t pip) {
-        static_assert(sizeof(PipId) <= 8, "T is too big for FFI");
-        auto p = PipId();
-        memcpy(&p, &pip, sizeof(PipId));
-        return p;
+    template<typename T> static inline T unwrap(const uint64_t value) noexcept {
+        std::array<uint8_t, 8> data{};
+        static_assert(sizeof(value) >= data.size(), "uint64_t is not an appropriate size");
+        memcpy(data.data(), &value, data.size());
+        return unwrap<T>(data);
     }
 
-    WireId unwrap_wire(uint64_t wire) {
-        static_assert(sizeof(WireId) <= 8, "T is too big for FFI");
-        auto w = WireId();
-        memcpy(&w, &wire, sizeof(WireId));
-        return w;
-    }
-#pragma GCC diagnostic pop
+    static inline BelId unwrap_bel(const uint64_t bel) noexcept
+        { return unwrap<BelId>(bel); }
+
+    static inline PipId unwrap_pip(const uint64_t pip) noexcept
+        { return unwrap<PipId>(pip); }
+
+    static inline WireId unwrap_wire(const uint64_t wire) noexcept
+        { return unwrap<WireId>(wire); }
 }
 
 using DownhillIter = decltype(Context(ArchArgs()).getPipsDownhill(WireId()).begin());

From cb269b46d63d680b936c55e965dc0bb4e4f13677 Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:07:53 +0000
Subject: [PATCH 549/712] rust: Made the wrap helper `inline` and fixed an
 accidental copy error

---
 rust/rust.cc | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 279884d07e..cb486233f2 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -24,17 +24,12 @@
 namespace {
     USING_NEXTPNR_NAMESPACE;
 
-    // `memcpy` is used here to avoid strict-aliasing problems, but GCC dislikes it.
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wclass-memaccess"
-    template<typename T>
-    uint64_t wrap(T thing) {
+    template<typename T> static inline uint64_t wrap(const T &thing) noexcept {
         static_assert(sizeof(T) <= 8, "T is too big for FFI");
         uint64_t b = 0;
         memcpy(&b, &thing, sizeof(T));
         return b;
     }
-#pragma GCC diagnostic pop
 
     template<typename T> static inline T unwrap(const std::array<uint8_t, 8> &value) noexcept {
         static_assert(sizeof(T) <= 8, "T is too big for FFI");

From 6a9ad61051e6beb63d201afc7d3e63de62e0cebf Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Wed, 3 Jan 2024 15:08:48 +0000
Subject: [PATCH 550/712] rust: Fixed an unused parameter warning

---
 rust/rust.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index cb486233f2..f747d401a9 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -196,7 +196,7 @@ extern "C" {
 #ifdef ARCH_ECP5
     bool npnr_netinfo_is_global(NetInfo *net) { return net->is_global; }
 #else
-    bool npnr_netinfo_is_global(NetInfo *net) { return false; }
+    bool npnr_netinfo_is_global(NetInfo * /*net*/) { return false; }
 #endif
 
     int32_t npnr_netinfo_udata(NetInfo *net) { return net->udata; }

From 5013392841aa3488f6b87a554782b38498081edc Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 4 Jan 2024 16:42:53 +0100
Subject: [PATCH 551/712] Add trivially copyable invariant for ID types

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/nextpnr_types.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/common/kernel/nextpnr_types.cc b/common/kernel/nextpnr_types.cc
index 6da37763bf..d867ed0e61 100644
--- a/common/kernel/nextpnr_types.cc
+++ b/common/kernel/nextpnr_types.cc
@@ -23,8 +23,15 @@
 
 #include "nextpnr_namespaces.h"
 
+#include <type_traits>
+
 NEXTPNR_NAMESPACE_BEGIN
 
+// Invariant: architecture ID types must all be trivially copyable
+static_assert(std::is_trivially_copyable<BelId>::value == true);
+static_assert(std::is_trivially_copyable<WireId>::value == true);
+static_assert(std::is_trivially_copyable<PipId>::value == true);
+
 void CellInfo::addInput(IdString name)
 {
     ports[name].name = name;

From d867019dcb0d9b428b8cec1572fdf6caa267e665 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 3 Jan 2024 13:19:42 +0000
Subject: [PATCH 552/712] upgrade to C++17

---
 CMakeLists.txt          |  2 +-
 common/kernel/hashlib.h | 35 ++++++++++++++++++++++++++++++-----
 2 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index d24a5d5fe7..5b4604a4a5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -141,7 +141,7 @@ foreach(item ${ARCH})
     endif()
 endforeach()
 
-set(CMAKE_CXX_STANDARD 14)
+set(CMAKE_CXX_STANDARD 17)
 if (MSVC)
     set(CMAKE_CONFIGURATION_TYPES "Debug;Release" CACHE STRING "" FORCE)
     set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /D_DEBUG /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996")
diff --git a/common/kernel/hashlib.h b/common/kernel/hashlib.h
index 008a581e53..884fcdcccf 100644
--- a/common/kernel/hashlib.h
+++ b/common/kernel/hashlib.h
@@ -367,7 +367,7 @@ template <typename K, typename T, typename OPS> class dict
     using mapped_type = T;
     using value_type = std::pair<K, T>;
 
-    class const_iterator : public std::iterator<std::forward_iterator_tag, std::pair<K, T>>
+    class const_iterator
     {
         friend class dict;
 
@@ -377,6 +377,11 @@ template <typename K, typename T, typename OPS> class dict
         const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) {}
 
       public:
+        using iterator_category = std::forward_iterator_tag;
+        using value_type = std::pair<K, T>;
+        using difference_type = std::ptrdiff_t;
+        using pointer = std::pair<K, T>*;
+        using reference = std::pair<K, T>&;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -395,7 +400,7 @@ template <typename K, typename T, typename OPS> class dict
         const std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }
     };
 
-    class iterator : public std::iterator<std::forward_iterator_tag, std::pair<K, T>>
+    class iterator
     {
         friend class dict;
 
@@ -405,6 +410,11 @@ template <typename K, typename T, typename OPS> class dict
         iterator(dict *ptr, int index) : ptr(ptr), index(index) {}
 
       public:
+        using iterator_category = std::forward_iterator_tag;
+        using value_type = std::pair<K, T>;
+        using difference_type = std::ptrdiff_t;
+        using pointer = std::pair<K, T>*;
+        using reference = std::pair<K, T>&;
         iterator() {}
         iterator operator++()
         {
@@ -808,7 +818,7 @@ template <typename K, typename OPS> class pool
     }
 
   public:
-    class const_iterator : public std::iterator<std::forward_iterator_tag, K>
+    class const_iterator
     {
         friend class pool;
 
@@ -818,6 +828,11 @@ template <typename K, typename OPS> class pool
         const_iterator(const pool *ptr, int index) : ptr(ptr), index(index) {}
 
       public:
+        using iterator_category = std::forward_iterator_tag;
+        using value_type = K;
+        using difference_type = std::ptrdiff_t;
+        using pointer = K*;
+        using reference = K&;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -830,7 +845,7 @@ template <typename K, typename OPS> class pool
         const K *operator->() const { return &ptr->entries[index].udata; }
     };
 
-    class iterator : public std::iterator<std::forward_iterator_tag, K>
+    class iterator
     {
         friend class pool;
 
@@ -840,6 +855,11 @@ template <typename K, typename OPS> class pool
         iterator(pool *ptr, int index) : ptr(ptr), index(index) {}
 
       public:
+        using iterator_category = std::forward_iterator_tag;
+        using value_type = K;
+        using difference_type = std::ptrdiff_t;
+        using pointer = K*;
+        using reference = K&;
         iterator() {}
         iterator operator++()
         {
@@ -1035,7 +1055,7 @@ template <typename K, int offset, typename OPS> class idict
     pool<K, OPS> database;
 
   public:
-    class const_iterator : public std::iterator<std::forward_iterator_tag, K>
+    class const_iterator
     {
         friend class idict;
 
@@ -1045,6 +1065,11 @@ template <typename K, int offset, typename OPS> class idict
         const_iterator(const idict &container, int index) : container(container), index(index) {}
 
       public:
+        using iterator_category = std::forward_iterator_tag;
+        using value_type = K;
+        using difference_type = std::ptrdiff_t;
+        using pointer = K*;
+        using reference = K&;
         const_iterator() {}
         const_iterator operator++()
         {

From 2c8ad5fa1dcf61a94b73f24ff64120f3cbbf2880 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 3 Jan 2024 13:29:49 +0000
Subject: [PATCH 553/712] Fix a renamed Qt item

---
 gui/fpgaviewwidget.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index 24f953384a..3787536f30 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -721,7 +721,7 @@ void FPGAViewWidget::mousePressEvent(QMouseEvent *event)
     bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier);
     bool ctrl = QApplication::keyboardModifiers().testFlag(Qt::ControlModifier);
     bool btn_right = event->buttons() & Qt::RightButton;
-    bool btn_mid = event->buttons() & Qt::MidButton;
+    bool btn_mid = event->buttons() & Qt::MiddleButton;
     bool btn_left = event->buttons() & Qt::LeftButton;
 
     if (btn_right || btn_mid || (btn_left && shift)) {
@@ -761,7 +761,7 @@ void FPGAViewWidget::mouseMoveEvent(QMouseEvent *event)
 
     bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier);
     bool btn_right = event->buttons() & Qt::RightButton;
-    bool btn_mid = event->buttons() & Qt::MidButton;
+    bool btn_mid = event->buttons() & Qt::MiddleButton;
     bool btn_left = event->buttons() & Qt::LeftButton;
 
     if (btn_right || btn_mid || (btn_left && shift)) {

From d557e3e35f17af77e2c7f7ad233f37703104acc7 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 4 Jan 2024 16:08:15 +0000
Subject: [PATCH 554/712] hashlib: constify const_iterators

---
 common/kernel/hashlib.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/common/kernel/hashlib.h b/common/kernel/hashlib.h
index 884fcdcccf..8ddfa0f85f 100644
--- a/common/kernel/hashlib.h
+++ b/common/kernel/hashlib.h
@@ -380,8 +380,8 @@ template <typename K, typename T, typename OPS> class dict
         using iterator_category = std::forward_iterator_tag;
         using value_type = std::pair<K, T>;
         using difference_type = std::ptrdiff_t;
-        using pointer = std::pair<K, T>*;
-        using reference = std::pair<K, T>&;
+        using pointer = const std::pair<K, T>*;
+        using reference = const std::pair<K, T>&;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -831,8 +831,8 @@ template <typename K, typename OPS> class pool
         using iterator_category = std::forward_iterator_tag;
         using value_type = K;
         using difference_type = std::ptrdiff_t;
-        using pointer = K*;
-        using reference = K&;
+        using pointer = const K*;
+        using reference = const K&;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -1068,8 +1068,8 @@ template <typename K, int offset, typename OPS> class idict
         using iterator_category = std::forward_iterator_tag;
         using value_type = K;
         using difference_type = std::ptrdiff_t;
-        using pointer = K*;
-        using reference = K&;
+        using pointer = const K*;
+        using reference = const K&;
         const_iterator() {}
         const_iterator operator++()
         {

From 257fbe549d0ed916a1a553bdfa8b7ff8c56b118d Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Fri, 5 Jan 2024 19:13:48 +0000
Subject: [PATCH 555/712] readme: update build prerequisites

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index ee6fa81980..9fee3b15c0 100644
--- a/README.md
+++ b/README.md
@@ -34,8 +34,8 @@ Prerequisites
 The following packages need to be installed for building nextpnr, independent
 of the selected architecture:
 
-- CMake 3.3 or later
-- Modern C++14 compiler (`clang-format` required for development)
+- CMake 3.13 or later
+- Modern C++17 compiler (`clang-format` required for development)
 - Python 3.5 or later, including development libraries (`python3-dev` for Ubuntu)
   - Python 3.9 or later is required for `nextpnr-himbaechel`
   - on Windows make sure to install same version as supported by [vcpkg](https://github.com/Microsoft/vcpkg/blob/master/ports/python3/CONTROL)

From d00fdc8f7a20fe0e34911bb0cecb42a876738712 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 11 Jan 2024 15:48:47 +0100
Subject: [PATCH 556/712] frontend: Ignore $scopeinfo

Signed-off-by: gatecat <gatecat@ds0.me>
---
 frontend/frontend_base.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index a2ac219c45..a96a396efb 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -447,10 +447,13 @@ template <typename FrontendType> struct GenericFrontend
     // Import a leaf cell - (white|black)box
     void import_leaf_cell(HierModuleState &m, const std::string &name, const cell_dat_t &cd)
     {
+        auto cell_type = impl.get_cell_type(cd);
+        if (cell_type == "$scopeinfo")
+            return;
         IdString inst_name = unique_name(m.prefix, name, false);
         ctx->hierarchy[m.path].leaf_cells_by_gname[inst_name] = ctx->id(name);
         ctx->hierarchy[m.path].leaf_cells[ctx->id(name)] = inst_name;
-        CellInfo *ci = ctx->createCell(inst_name, ctx->id(impl.get_cell_type(cd)));
+        CellInfo *ci = ctx->createCell(inst_name, ctx->id(cell_type));
         ci->hierpath = m.path;
         // Import port directions
         dict<IdString, PortType> port_dirs;

From 2afb1f632e3069c140c1a7619031e9bda20d2002 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 12 Jan 2024 10:09:28 +0100
Subject: [PATCH 557/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/base_arch.h     |  15 +-
 common/kernel/command.h       |   8 +-
 common/kernel/hashlib.h       |  20 +-
 common/kernel/idstringlist.h  |   8 +-
 common/kernel/nextpnr_types.h |  34 ++--
 common/kernel/pycontainers.h  |  10 +-
 common/kernel/pywrappers.h    |   2 +-
 common/place/timing_opt.h     |   2 +-
 gui/treemodel.h               |   6 +-
 rust/rust.cc                  | 352 ++++++++++++++++++----------------
 rust/rust.h                   |   2 +-
 11 files changed, 246 insertions(+), 213 deletions(-)

diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index fa852a7ce1..5aa655a5cc 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -185,7 +185,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
         return empty_if_possible<typename R::BelAttrsRangeT>();
     }
 
-    virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo * /*cell_info*/, IdString pin) const override
+    virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo * /*cell_info*/,
+                                                              IdString pin) const override
     {
         return return_if_match<std::array<IdString, 1>, typename R::CellBelPinRangeT>({pin});
     }
@@ -314,7 +315,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
     };
 
     // Delay methods
-    virtual bool getArcDelayOverride(const NetInfo * /*net_info*/, const PortRef &/*sink*/, DelayQuad &/*delay*/) const override
+    virtual bool getArcDelayOverride(const NetInfo * /*net_info*/, const PortRef & /*sink*/,
+                                     DelayQuad & /*delay*/) const override
     {
         return false;
     }
@@ -330,15 +332,18 @@ template <typename R> struct BaseArch : ArchAPI<R>
     virtual DecalXY getGroupDecal(GroupId /*group*/) const override { return DecalXY(); }
 
     // Cell timing methods
-    virtual bool getCellDelay(const CellInfo * /*cell*/, IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override
+    virtual bool getCellDelay(const CellInfo * /*cell*/, IdString /*fromPort*/, IdString /*toPort*/,
+                              DelayQuad & /*delay*/) const override
     {
         return false;
     }
-    virtual TimingPortClass getPortTimingClass(const CellInfo * /*cell*/, IdString /*port*/, int &/*clockInfoCount*/) const override
+    virtual TimingPortClass getPortTimingClass(const CellInfo * /*cell*/, IdString /*port*/,
+                                               int & /*clockInfoCount*/) const override
     {
         return TMG_IGNORE;
     }
-    virtual TimingClockingInfo getPortClockingInfo(const CellInfo * /*cell*/, IdString /*port*/, int /*index*/) const override
+    virtual TimingClockingInfo getPortClockingInfo(const CellInfo * /*cell*/, IdString /*port*/,
+                                                   int /*index*/) const override
     {
         NPNR_ASSERT_FALSE("unreachable");
     }
diff --git a/common/kernel/command.h b/common/kernel/command.h
index 5f173e5590..d4a34e892a 100644
--- a/common/kernel/command.h
+++ b/common/kernel/command.h
@@ -34,7 +34,7 @@ class CommandHandler
 {
   public:
     CommandHandler(int argc, char **argv);
-    virtual ~CommandHandler() { }
+    virtual ~CommandHandler() {}
 
     int exec();
     void load_json(Context *ctx, std::string filename);
@@ -45,9 +45,9 @@ class CommandHandler
     virtual void setupArchContext(Context *ctx) = 0;
     virtual std::unique_ptr<Context> createContext(dict<std::string, Property> &values) = 0;
     virtual po::options_description getArchOptions() = 0;
-    virtual void validate() { }
-    virtual void customAfterLoad(Context * /*ctx*/) { }
-    virtual void customBitstream(Context * /*ctx*/) { }
+    virtual void validate() {}
+    virtual void customAfterLoad(Context * /*ctx*/) {}
+    virtual void customBitstream(Context * /*ctx*/) {}
     void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2);
 
   private:
diff --git a/common/kernel/hashlib.h b/common/kernel/hashlib.h
index 8ddfa0f85f..10bc04d3ae 100644
--- a/common/kernel/hashlib.h
+++ b/common/kernel/hashlib.h
@@ -380,8 +380,8 @@ template <typename K, typename T, typename OPS> class dict
         using iterator_category = std::forward_iterator_tag;
         using value_type = std::pair<K, T>;
         using difference_type = std::ptrdiff_t;
-        using pointer = const std::pair<K, T>*;
-        using reference = const std::pair<K, T>&;
+        using pointer = const std::pair<K, T> *;
+        using reference = const std::pair<K, T> &;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -413,8 +413,8 @@ template <typename K, typename T, typename OPS> class dict
         using iterator_category = std::forward_iterator_tag;
         using value_type = std::pair<K, T>;
         using difference_type = std::ptrdiff_t;
-        using pointer = std::pair<K, T>*;
-        using reference = std::pair<K, T>&;
+        using pointer = std::pair<K, T> *;
+        using reference = std::pair<K, T> &;
         iterator() {}
         iterator operator++()
         {
@@ -831,8 +831,8 @@ template <typename K, typename OPS> class pool
         using iterator_category = std::forward_iterator_tag;
         using value_type = K;
         using difference_type = std::ptrdiff_t;
-        using pointer = const K*;
-        using reference = const K&;
+        using pointer = const K *;
+        using reference = const K &;
         const_iterator() {}
         const_iterator operator++()
         {
@@ -858,8 +858,8 @@ template <typename K, typename OPS> class pool
         using iterator_category = std::forward_iterator_tag;
         using value_type = K;
         using difference_type = std::ptrdiff_t;
-        using pointer = K*;
-        using reference = K&;
+        using pointer = K *;
+        using reference = K &;
         iterator() {}
         iterator operator++()
         {
@@ -1068,8 +1068,8 @@ template <typename K, int offset, typename OPS> class idict
         using iterator_category = std::forward_iterator_tag;
         using value_type = K;
         using difference_type = std::ptrdiff_t;
-        using pointer = const K*;
-        using reference = const K&;
+        using pointer = const K *;
+        using reference = const K &;
         const_iterator() {}
         const_iterator operator++()
         {
diff --git a/common/kernel/idstringlist.h b/common/kernel/idstringlist.h
index b8e37966fe..436e6ff039 100644
--- a/common/kernel/idstringlist.h
+++ b/common/kernel/idstringlist.h
@@ -35,10 +35,10 @@ struct IdStringList
 {
     SSOArray<IdString, 4> ids;
 
-    IdStringList() : ids(1, IdString()) { }
-    explicit IdStringList(size_t n) : ids(n, IdString()) { }
-    explicit IdStringList(IdString id) : ids(1, id) { }
-    template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list) { }
+    IdStringList() : ids(1, IdString()) {}
+    explicit IdStringList(size_t n) : ids(n, IdString()) {}
+    explicit IdStringList(IdString id) : ids(1, id) {}
+    template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list) {}
 
     static IdStringList parse(Context *ctx, const std::string &str);
     void build_str(const Context *ctx, std::string &str) const;
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 5a239ca17d..163ad2f266 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -81,8 +81,8 @@ struct PortRef
 struct DelayPair
 {
     DelayPair(){};
-    explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) { }
-    DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) { }
+    explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) {}
+    DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) {}
     delay_t minDelay() const { return min_delay; }
     delay_t maxDelay() const { return max_delay; }
     delay_t min_delay, max_delay;
@@ -100,12 +100,14 @@ struct DelayPair
 struct DelayQuad
 {
     DelayPair rise, fall;
-    DelayQuad() { }
-    explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) { }
-    DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) { }
-    DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) { }
+    DelayQuad() {}
+    explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) {}
+    DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) {}
+    DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) {}
     DelayQuad(delay_t min_rise, delay_t max_rise, delay_t min_fall, delay_t max_fall)
-            : rise(min_rise, max_rise), fall(min_fall, max_fall) { }
+            : rise(min_rise, max_rise), fall(min_fall, max_fall)
+    {
+    }
 
     delay_t minRiseDelay() const { return rise.minDelay(); }
     delay_t maxRiseDelay() const { return rise.maxDelay(); }
@@ -124,7 +126,7 @@ struct ClockConstraint;
 
 struct NetInfo : ArchNetInfo
 {
-    explicit NetInfo(IdString name) : name(name) { }
+    explicit NetInfo(IdString name) : name(name) {}
     IdString name, hierpath;
     int32_t udata = 0;
 
@@ -203,14 +205,20 @@ struct PseudoCell
 
 struct RegionPlug : PseudoCell
 {
-    RegionPlug(Loc loc) : loc(loc) { } // 'loc' is a notional location for the placer only
+    RegionPlug(Loc loc) : loc(loc) {} // 'loc' is a notional location for the placer only
     Loc getLocation() const override { return loc; }
     WireId getPortWire(IdString port) const override { return port_wires.at(port); }
 
     // TODO: partial reconfiguration region timing
-    bool getDelay(IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override { return false; }
-    TimingPortClass getPortTimingClass(IdString /*port*/, int &/*clockInfoCount*/) const override { return TMG_IGNORE; }
-    TimingClockingInfo getPortClockingInfo(IdString /*port*/, int /*index*/) const override { return TimingClockingInfo{}; }
+    bool getDelay(IdString /*fromPort*/, IdString /*toPort*/, DelayQuad & /*delay*/) const override { return false; }
+    TimingPortClass getPortTimingClass(IdString /*port*/, int & /*clockInfoCount*/) const override
+    {
+        return TMG_IGNORE;
+    }
+    TimingClockingInfo getPortClockingInfo(IdString /*port*/, int /*index*/) const override
+    {
+        return TimingClockingInfo{};
+    }
 
     dict<IdString, WireId> port_wires;
     Loc loc;
@@ -218,7 +226,7 @@ struct RegionPlug : PseudoCell
 
 struct CellInfo : ArchCellInfo
 {
-    CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type) { }
+    CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type) {}
     Context *ctx = nullptr;
 
     IdString name, type, hierpath;
diff --git a/common/kernel/pycontainers.h b/common/kernel/pycontainers.h
index 626849ceea..d79508b969 100644
--- a/common/kernel/pycontainers.h
+++ b/common/kernel/pycontainers.h
@@ -290,7 +290,7 @@ template <typename T1, typename T2> struct pair_wrapper
             x.second = val.cast<T2>();
     }
 
-    static int len(T &/*x*/) { return 2; }
+    static int len(T & /*x*/) { return 2; }
 
     static iter_pair<T &, int> iter(T &x) { return iter_pair<T &, int>(boost::ref(x), 0); };
 
@@ -348,7 +348,7 @@ template <typename T1, typename T2, typename value_conv> struct map_pair_wrapper
                                                                                                        x.base.first));
     }
 
-    static int len(wrapped_pair &/*x*/) { return 2; }
+    static int len(wrapped_pair & /*x*/) { return 2; }
 
     static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
     {
@@ -472,11 +472,11 @@ template <typename T1, typename T2> struct map_pair_wrapper_uptr
         if (i >= 2 || i < 0)
             KeyError();
         return i == 1 ? py::cast(PythonConversion::ContextualWrapper<V &>(x.ctx, *x.base.second.get()))
-                        : py::cast(PythonConversion::string_converter<decltype(x.base.first)>().to_str(x.ctx,
-                                                                                                       x.base.first));
+                      : py::cast(PythonConversion::string_converter<decltype(x.base.first)>().to_str(x.ctx,
+                                                                                                     x.base.first));
     }
 
-    static int len(wrapped_pair &/*x*/) { return 2; }
+    static int len(wrapped_pair & /*x*/) { return 2; }
 
     static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
     {
diff --git a/common/kernel/pywrappers.h b/common/kernel/pywrappers.h
index 69b9419786..e6499fb697 100644
--- a/common/kernel/pywrappers.h
+++ b/common/kernel/pywrappers.h
@@ -35,7 +35,7 @@ template <typename T> struct ContextualWrapper
     Context *ctx;
     T base;
 
-    inline ContextualWrapper(Context *c, T x) : ctx(c), base(x) { }
+    inline ContextualWrapper(Context *c, T x) : ctx(c), base(x) {}
 
     inline operator T() { return base; }
     typedef T base_type;
diff --git a/common/place/timing_opt.h b/common/place/timing_opt.h
index e5d0fd3864..18c946c0db 100644
--- a/common/place/timing_opt.h
+++ b/common/place/timing_opt.h
@@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct TimingOptCfg
 {
-    TimingOptCfg(Context * /*ctx*/) { }
+    TimingOptCfg(Context * /*ctx*/) {}
 
     // The timing optimiser will *only* optimise cells of these types
     // Normally these would only be logic cells (or tiles if applicable), the algorithm makes little sense
diff --git a/gui/treemodel.h b/gui/treemodel.h
index 915258a6f3..84cdc16587 100644
--- a/gui/treemodel.h
+++ b/gui/treemodel.h
@@ -103,8 +103,8 @@ class Item
     virtual void fetchMore() {}
 
     virtual boost::optional<Item *> getById(IdStringList /*id*/) { return boost::none; }
-    virtual void search(QList<Item *> &/*results*/, QString /*text*/, int /*limit*/) { }
-    virtual void updateElements(Context * /*ctx*/, std::vector<IdStringList> /*elements*/) { }
+    virtual void search(QList<Item *> & /*results*/, QString /*text*/, int /*limit*/) {}
+    virtual void updateElements(Context * /*ctx*/, std::vector<IdStringList> /*elements*/) {}
 
     virtual ~Item()
     {
@@ -147,7 +147,7 @@ class IdList : public Item
   public:
     // Create an IdList at given parent that will contain elements of
     // the given type.
-    IdList(ElementType type) : Item("root", nullptr), child_type_(type) { }
+    IdList(ElementType type) : Item("root", nullptr), child_type_(type) {}
 
     // Split a name into alpha/non-alpha parts, which is then used for sorting
     // of children.
diff --git a/rust/rust.cc b/rust/rust.cc
index f747d401a9..19e1b6ffd3 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -22,42 +22,43 @@
 #include "nextpnr.h"
 
 namespace {
-    USING_NEXTPNR_NAMESPACE;
-
-    template<typename T> static inline uint64_t wrap(const T &thing) noexcept {
-        static_assert(sizeof(T) <= 8, "T is too big for FFI");
-        uint64_t b = 0;
-        memcpy(&b, &thing, sizeof(T));
-        return b;
-    }
+USING_NEXTPNR_NAMESPACE;
+
+template <typename T> static inline uint64_t wrap(const T &thing) noexcept
+{
+    static_assert(sizeof(T) <= 8, "T is too big for FFI");
+    uint64_t b = 0;
+    memcpy(&b, &thing, sizeof(T));
+    return b;
+}
 
-    template<typename T> static inline T unwrap(const std::array<uint8_t, 8> &value) noexcept {
-        static_assert(sizeof(T) <= 8, "T is too big for FFI");
-        T result{};
-        memcpy(&result, value.data(), sizeof(result));
-        return result;
-    }
+template <typename T> static inline T unwrap(const std::array<uint8_t, 8> &value) noexcept
+{
+    static_assert(sizeof(T) <= 8, "T is too big for FFI");
+    T result{};
+    memcpy(&result, value.data(), sizeof(result));
+    return result;
+}
 
-    template<typename T> static inline T unwrap(const uint64_t value) noexcept {
-        std::array<uint8_t, 8> data{};
-        static_assert(sizeof(value) >= data.size(), "uint64_t is not an appropriate size");
-        memcpy(data.data(), &value, data.size());
-        return unwrap<T>(data);
-    }
+template <typename T> static inline T unwrap(const uint64_t value) noexcept
+{
+    std::array<uint8_t, 8> data{};
+    static_assert(sizeof(value) >= data.size(), "uint64_t is not an appropriate size");
+    memcpy(data.data(), &value, data.size());
+    return unwrap<T>(data);
+}
 
-    static inline BelId unwrap_bel(const uint64_t bel) noexcept
-        { return unwrap<BelId>(bel); }
+static inline BelId unwrap_bel(const uint64_t bel) noexcept { return unwrap<BelId>(bel); }
 
-    static inline PipId unwrap_pip(const uint64_t pip) noexcept
-        { return unwrap<PipId>(pip); }
+static inline PipId unwrap_pip(const uint64_t pip) noexcept { return unwrap<PipId>(pip); }
 
-    static inline WireId unwrap_wire(const uint64_t wire) noexcept
-        { return unwrap<WireId>(wire); }
-}
+static inline WireId unwrap_wire(const uint64_t wire) noexcept { return unwrap<WireId>(wire); }
+} // namespace
 
 using DownhillIter = decltype(Context(ArchArgs()).getPipsDownhill(WireId()).begin());
 
-struct DownhillIterWrapper {
+struct DownhillIterWrapper
+{
     DownhillIter current;
     DownhillIter end;
 
@@ -65,7 +66,8 @@ struct DownhillIterWrapper {
 };
 using UphillIter = decltype(Context(ArchArgs()).getPipsUphill(WireId()).begin());
 
-struct UphillIterWrapper {
+struct UphillIterWrapper
+{
     UphillIter current;
     UphillIter end;
 
@@ -73,164 +75,182 @@ struct UphillIterWrapper {
 };
 
 extern "C" {
-    USING_NEXTPNR_NAMESPACE;
-
-    void npnr_log_info(const char *string) { log_info("%s", string); }
-    void npnr_log_error(const char *string) { log_error("%s", string); }
-
-    uint64_t npnr_belid_null() { return wrap(BelId()); }
-    uint64_t npnr_wireid_null() { return wrap(WireId()); }
-    uint64_t npnr_pipid_null() { return wrap(PipId()); }
-
-    int npnr_context_get_grid_dim_x(const Context *ctx) { return ctx->getGridDimX(); }
-    int npnr_context_get_grid_dim_y(const Context *ctx) { return ctx->getGridDimY(); }
-    void npnr_context_bind_bel(Context *ctx, uint64_t bel, CellInfo* cell, PlaceStrength strength) { return ctx->bindBel(unwrap_bel(bel), cell, strength); }
-    void npnr_context_unbind_bel(Context *ctx, uint64_t bel) { return ctx->unbindBel(unwrap_bel(bel)); }
-    bool npnr_context_check_bel_avail(Context *ctx, uint64_t bel) { return ctx->checkBelAvail(unwrap_bel(bel)); }
-    void npnr_context_bind_wire(Context *ctx, uint64_t wire, NetInfo* net, PlaceStrength strength) { ctx->bindWire(unwrap_wire(wire), net, strength); }
-    void npnr_context_unbind_wire(Context *ctx, uint64_t wire) { ctx->unbindWire(unwrap_wire(wire)); }
-    void npnr_context_bind_pip(Context *ctx, uint64_t pip, NetInfo* net, PlaceStrength strength) { ctx->bindPip(unwrap_pip(pip), net, strength); }
-    void npnr_context_unbind_pip(Context *ctx, uint64_t pip) { ctx->unbindPip(unwrap_pip(pip)); }
-    uint64_t npnr_context_get_pip_src_wire(const Context *ctx, uint64_t pip) { return wrap(ctx->getPipSrcWire(unwrap_pip(pip))); }
-    uint64_t npnr_context_get_pip_dst_wire(const Context *ctx, uint64_t pip) { return wrap(ctx->getPipDstWire(unwrap_pip(pip))); }
-    float npnr_context_estimate_delay(const Context *ctx, uint64_t src, uint64_t dst) { return ctx->getDelayNS(ctx->estimateDelay(unwrap_wire(src), unwrap_wire(dst))); }
-    float npnr_context_get_pip_delay(const Context *ctx, uint64_t pip) { return ctx->getDelayNS(ctx->getPipDelay(unwrap_pip(pip)).maxDelay()); }
-    float npnr_context_get_wire_delay(const Context *ctx, uint64_t wire) { return ctx->getDelayNS(ctx->getWireDelay(unwrap_wire(wire)).maxDelay()); }
-    float npnr_context_delay_epsilon(const Context *ctx) { return ctx->getDelayNS(ctx->getDelayEpsilon()); }
-    Loc npnr_context_get_pip_location(const Context *ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
-    bool npnr_context_check_pip_avail_for_net(const Context *ctx, uint64_t pip, NetInfo *net) { return ctx->checkPipAvailForNet(unwrap_pip(pip), net); }
-
-    uint64_t npnr_context_get_pips_leak(const Context *const ctx, uint64_t **const pips) {
-        const auto ctx_pips{ctx->getPips()};
-        const auto size{
-            std::accumulate(ctx_pips.begin(), ctx_pips.end(), /*initial value*/ size_t{},
-                [](size_t value, const auto &/*pip*/) { return value + 1U; }
-        )};
-        *pips = new uint64_t[size];
-        auto idx = 0;
-        for (const auto &pip : ctx_pips) {
-            (*pips)[idx] = wrap(pip);
-            idx++;
-        }
-        // Yes, by never deleting pip_vec, we leak memory.
-        return size;
-    }
+USING_NEXTPNR_NAMESPACE;
 
-    uint64_t npnr_context_get_wires_leak(const Context *const ctx, uint64_t **const wires) {
-        const auto ctx_wires{ctx->getWires()};
-        const auto size{
-            std::accumulate(ctx_wires.begin(), ctx_wires.end(), /*initial value*/ size_t{},
-                [](size_t value, const auto &/*wire*/) { return value + 1U; }
-        )};
-        *wires = new uint64_t[size];
-        auto idx = 0;
-        for (const auto &wire : ctx_wires) {
-            (*wires)[idx] = wrap(wire);
-            idx++;
-        }
-        // Yes, by never deleting wires, we leak memory.
-        return size;
-    }
+void npnr_log_info(const char *string) { log_info("%s", string); }
+void npnr_log_error(const char *string) { log_error("%s", string); }
 
-    void npnr_context_check(const Context *ctx) { ctx->check(); }
-    bool npnr_context_debug(const Context *ctx) { return ctx->debug; }
-    int npnr_context_id(const Context *ctx, const char *str) { return ctx->id(str).hash(); }
-    const char *npnr_context_name_of(const Context *ctx, IdString str) { return ctx->nameOf(str); }
-    const char *npnr_context_name_of_pip(const Context *ctx, uint64_t pip) { return ctx->nameOfPip(unwrap_pip(pip)); }
-    const char *npnr_context_name_of_wire(const Context *ctx, uint64_t wire) { return ctx->nameOfWire(unwrap_wire(wire)); }
-    bool npnr_context_verbose(const Context *ctx) { return ctx->verbose; }
-
-    uint64_t npnr_context_get_netinfo_source_wire(const Context *ctx, const NetInfo *net) { return wrap(ctx->getNetinfoSourceWire(net)); }
-    uint64_t npnr_context_get_netinfo_sink_wire(const Context *ctx, const NetInfo *net, const PortRef *sink, uint32_t n) { return wrap(ctx->getNetinfoSinkWire(net, *sink, n)); }
-
-    uint32_t npnr_context_nets_leak(const Context *ctx, int **names, NetInfo ***nets) {
-        auto size = ctx->nets.size();
-        *names = new int[size];
-        *nets = new NetInfo*[size];
-        auto idx = 0;
-        for (auto& item : ctx->nets) {
-            (*names)[idx] = item.first.index;
-            (*nets)[idx] = item.second.get();
-            idx++;
-        }
-        // Yes, by never deleting `names` and `nets` we leak memory.
-        return size;
-    }
+uint64_t npnr_belid_null() { return wrap(BelId()); }
+uint64_t npnr_wireid_null() { return wrap(WireId()); }
+uint64_t npnr_pipid_null() { return wrap(PipId()); }
 
-    DownhillIterWrapper *npnr_context_get_pips_downhill(Context *ctx, uint64_t wire_id) {
-        auto wire = unwrap_wire(wire_id);
-        auto range = ctx->getPipsDownhill(wire);
-        return new DownhillIterWrapper(range.begin(), range.end());
-    }
-    void npnr_delete_downhill_iter(DownhillIterWrapper *iter) {
-        delete iter;
+int npnr_context_get_grid_dim_x(const Context *ctx) { return ctx->getGridDimX(); }
+int npnr_context_get_grid_dim_y(const Context *ctx) { return ctx->getGridDimY(); }
+void npnr_context_bind_bel(Context *ctx, uint64_t bel, CellInfo *cell, PlaceStrength strength)
+{
+    return ctx->bindBel(unwrap_bel(bel), cell, strength);
+}
+void npnr_context_unbind_bel(Context *ctx, uint64_t bel) { return ctx->unbindBel(unwrap_bel(bel)); }
+bool npnr_context_check_bel_avail(Context *ctx, uint64_t bel) { return ctx->checkBelAvail(unwrap_bel(bel)); }
+void npnr_context_bind_wire(Context *ctx, uint64_t wire, NetInfo *net, PlaceStrength strength)
+{
+    ctx->bindWire(unwrap_wire(wire), net, strength);
+}
+void npnr_context_unbind_wire(Context *ctx, uint64_t wire) { ctx->unbindWire(unwrap_wire(wire)); }
+void npnr_context_bind_pip(Context *ctx, uint64_t pip, NetInfo *net, PlaceStrength strength)
+{
+    ctx->bindPip(unwrap_pip(pip), net, strength);
+}
+void npnr_context_unbind_pip(Context *ctx, uint64_t pip) { ctx->unbindPip(unwrap_pip(pip)); }
+uint64_t npnr_context_get_pip_src_wire(const Context *ctx, uint64_t pip)
+{
+    return wrap(ctx->getPipSrcWire(unwrap_pip(pip)));
+}
+uint64_t npnr_context_get_pip_dst_wire(const Context *ctx, uint64_t pip)
+{
+    return wrap(ctx->getPipDstWire(unwrap_pip(pip)));
+}
+float npnr_context_estimate_delay(const Context *ctx, uint64_t src, uint64_t dst)
+{
+    return ctx->getDelayNS(ctx->estimateDelay(unwrap_wire(src), unwrap_wire(dst)));
+}
+float npnr_context_get_pip_delay(const Context *ctx, uint64_t pip)
+{
+    return ctx->getDelayNS(ctx->getPipDelay(unwrap_pip(pip)).maxDelay());
+}
+float npnr_context_get_wire_delay(const Context *ctx, uint64_t wire)
+{
+    return ctx->getDelayNS(ctx->getWireDelay(unwrap_wire(wire)).maxDelay());
+}
+float npnr_context_delay_epsilon(const Context *ctx) { return ctx->getDelayNS(ctx->getDelayEpsilon()); }
+Loc npnr_context_get_pip_location(const Context *ctx, uint64_t pip) { return ctx->getPipLocation(unwrap_pip(pip)); }
+bool npnr_context_check_pip_avail_for_net(const Context *ctx, uint64_t pip, NetInfo *net)
+{
+    return ctx->checkPipAvailForNet(unwrap_pip(pip), net);
+}
+
+uint64_t npnr_context_get_pips_leak(const Context *const ctx, uint64_t **const pips)
+{
+    const auto ctx_pips{ctx->getPips()};
+    const auto size{std::accumulate(ctx_pips.begin(), ctx_pips.end(), /*initial value*/ size_t{},
+                                    [](size_t value, const auto & /*pip*/) { return value + 1U; })};
+    *pips = new uint64_t[size];
+    auto idx = 0;
+    for (const auto &pip : ctx_pips) {
+        (*pips)[idx] = wrap(pip);
+        idx++;
     }
-    UphillIterWrapper *npnr_context_get_pips_uphill(Context *ctx, uint64_t wire_id) {
-        auto wire = unwrap_wire(wire_id);
-        auto range = ctx->getPipsUphill(wire);
-        return new UphillIterWrapper(range.begin(), range.end());
+    // Yes, by never deleting pip_vec, we leak memory.
+    return size;
+}
+
+uint64_t npnr_context_get_wires_leak(const Context *const ctx, uint64_t **const wires)
+{
+    const auto ctx_wires{ctx->getWires()};
+    const auto size{std::accumulate(ctx_wires.begin(), ctx_wires.end(), /*initial value*/ size_t{},
+                                    [](size_t value, const auto & /*wire*/) { return value + 1U; })};
+    *wires = new uint64_t[size];
+    auto idx = 0;
+    for (const auto &wire : ctx_wires) {
+        (*wires)[idx] = wrap(wire);
+        idx++;
     }
-    void npnr_delete_uphill_iter(UphillIterWrapper *iter) {
-        delete iter;
+    // Yes, by never deleting wires, we leak memory.
+    return size;
+}
+
+void npnr_context_check(const Context *ctx) { ctx->check(); }
+bool npnr_context_debug(const Context *ctx) { return ctx->debug; }
+int npnr_context_id(const Context *ctx, const char *str) { return ctx->id(str).hash(); }
+const char *npnr_context_name_of(const Context *ctx, IdString str) { return ctx->nameOf(str); }
+const char *npnr_context_name_of_pip(const Context *ctx, uint64_t pip) { return ctx->nameOfPip(unwrap_pip(pip)); }
+const char *npnr_context_name_of_wire(const Context *ctx, uint64_t wire) { return ctx->nameOfWire(unwrap_wire(wire)); }
+bool npnr_context_verbose(const Context *ctx) { return ctx->verbose; }
+
+uint64_t npnr_context_get_netinfo_source_wire(const Context *ctx, const NetInfo *net)
+{
+    return wrap(ctx->getNetinfoSourceWire(net));
+}
+uint64_t npnr_context_get_netinfo_sink_wire(const Context *ctx, const NetInfo *net, const PortRef *sink, uint32_t n)
+{
+    return wrap(ctx->getNetinfoSinkWire(net, *sink, n));
+}
+
+uint32_t npnr_context_nets_leak(const Context *ctx, int **names, NetInfo ***nets)
+{
+    auto size = ctx->nets.size();
+    *names = new int[size];
+    *nets = new NetInfo *[size];
+    auto idx = 0;
+    for (auto &item : ctx->nets) {
+        (*names)[idx] = item.first.index;
+        (*nets)[idx] = item.second.get();
+        idx++;
     }
+    // Yes, by never deleting `names` and `nets` we leak memory.
+    return size;
+}
 
-    PortRef* npnr_netinfo_driver(NetInfo *net) {
-        if (net == nullptr) {
-            return nullptr;
-        }
-        return &net->driver;
+DownhillIterWrapper *npnr_context_get_pips_downhill(Context *ctx, uint64_t wire_id)
+{
+    auto wire = unwrap_wire(wire_id);
+    auto range = ctx->getPipsDownhill(wire);
+    return new DownhillIterWrapper(range.begin(), range.end());
+}
+void npnr_delete_downhill_iter(DownhillIterWrapper *iter) { delete iter; }
+UphillIterWrapper *npnr_context_get_pips_uphill(Context *ctx, uint64_t wire_id)
+{
+    auto wire = unwrap_wire(wire_id);
+    auto range = ctx->getPipsUphill(wire);
+    return new UphillIterWrapper(range.begin(), range.end());
+}
+void npnr_delete_uphill_iter(UphillIterWrapper *iter) { delete iter; }
+
+PortRef *npnr_netinfo_driver(NetInfo *net)
+{
+    if (net == nullptr) {
+        return nullptr;
     }
+    return &net->driver;
+}
 
-    uint32_t npnr_netinfo_users_leak(NetInfo *net, PortRef ***users) {
-        auto size = net->users.entries();
-        *users = new PortRef*[size];
-        auto idx = 0;
-        for (auto& item : net->users) {
-            (*users)[idx] = &item;
-            idx++;
-        }
-        // Yes, by not freeing `users`, we leak memory.
-        return size;
+uint32_t npnr_netinfo_users_leak(NetInfo *net, PortRef ***users)
+{
+    auto size = net->users.entries();
+    *users = new PortRef *[size];
+    auto idx = 0;
+    for (auto &item : net->users) {
+        (*users)[idx] = &item;
+        idx++;
     }
+    // Yes, by not freeing `users`, we leak memory.
+    return size;
+}
 
 #ifdef ARCH_ECP5
-    bool npnr_netinfo_is_global(NetInfo *net) { return net->is_global; }
+bool npnr_netinfo_is_global(NetInfo *net) { return net->is_global; }
 #else
-    bool npnr_netinfo_is_global(NetInfo * /*net*/) { return false; }
+bool npnr_netinfo_is_global(NetInfo * /*net*/) { return false; }
 #endif
 
-    int32_t npnr_netinfo_udata(NetInfo *net) { return net->udata; }
-    void npnr_netinfo_udata_set(NetInfo *net, int32_t value) { net->udata = value; }
+int32_t npnr_netinfo_udata(NetInfo *net) { return net->udata; }
+void npnr_netinfo_udata_set(NetInfo *net, int32_t value) { net->udata = value; }
 
-    CellInfo* npnr_portref_cell(const PortRef *port) { return port->cell; }
-    Loc npnr_cellinfo_get_location(const CellInfo *info) { return info->getLocation(); }
+CellInfo *npnr_portref_cell(const PortRef *port) { return port->cell; }
+Loc npnr_cellinfo_get_location(const CellInfo *info) { return info->getLocation(); }
 
-    void npnr_inc_downhill_iter(DownhillIterWrapper *iter) {
-        ++iter->current;
-    }
-    uint64_t npnr_deref_downhill_iter(DownhillIterWrapper *iter) {
-        return wrap(*iter->current);
-    }
-    bool npnr_is_downhill_iter_done(DownhillIterWrapper *iter) {
-        return !(iter->current != iter->end);
-    }
-    void npnr_inc_uphill_iter(UphillIterWrapper *iter) {
-        ++iter->current;
-    }
-    uint64_t npnr_deref_uphill_iter(UphillIterWrapper *iter) {
-        return wrap(*iter->current);
-    }
-    bool npnr_is_uphill_iter_done(UphillIterWrapper *iter) {
-        return !(iter->current != iter->end);
-    }
+void npnr_inc_downhill_iter(DownhillIterWrapper *iter) { ++iter->current; }
+uint64_t npnr_deref_downhill_iter(DownhillIterWrapper *iter) { return wrap(*iter->current); }
+bool npnr_is_downhill_iter_done(DownhillIterWrapper *iter) { return !(iter->current != iter->end); }
+void npnr_inc_uphill_iter(UphillIterWrapper *iter) { ++iter->current; }
+uint64_t npnr_deref_uphill_iter(UphillIterWrapper *iter) { return wrap(*iter->current); }
+bool npnr_is_uphill_iter_done(UphillIterWrapper *iter) { return !(iter->current != iter->end); }
 
-    void rust_example_printnets(Context *ctx);
+void rust_example_printnets(Context *ctx);
 }
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void example_printnets(Context *ctx) {
-    rust_example_printnets(ctx);
-}
+void example_printnets(Context *ctx) { rust_example_printnets(ctx); }
 
 NEXTPNR_NAMESPACE_END
diff --git a/rust/rust.h b/rust/rust.h
index 4830503fa2..2ca2ffe02a 100644
--- a/rust/rust.h
+++ b/rust/rust.h
@@ -25,7 +25,7 @@
 #include "nextpnr.h"
 NEXTPNR_NAMESPACE_BEGIN
 
-void example_printnets(Context* ctx);
+void example_printnets(Context *ctx);
 
 NEXTPNR_NAMESPACE_END
 

From f12e76479ca04910cd11a55415e85227de17c783 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 01:50:09 +0000
Subject: [PATCH 558/712] rust: add mutex for arch manipulation

---
 rust/nextpnr/src/lib.rs | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index 05f4721fe8..9ee7d0314a 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -140,6 +140,9 @@ impl From<(i32, i32)> for Loc {
     }
 }
 
+static RINGBUFFER_MUTEX: Mutex<()> = Mutex::new(());
+static ARCH_MUTEX: Mutex<()> = Mutex::new(());
+
 #[repr(C)]
 pub struct Context {
     _private: [u8; 0],
@@ -157,15 +160,14 @@ impl Context {
     }
 
     /// Bind a given bel to a given cell with the given strength.
-    ///
-    /// # Safety
-    /// `cell` must be valid and not null.
-    pub unsafe fn bind_bel(&mut self, bel: BelId, cell: *mut CellInfo, strength: PlaceStrength) {
+    pub fn bind_bel(&mut self, bel: BelId, cell: &mut CellInfo, strength: PlaceStrength) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_bind_bel(self, bel, cell, strength) }
     }
 
     /// Unbind a bel.
     pub fn unbind_bel(&mut self, bel: BelId) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_unbind_bel(self, bel) }
     }
 
@@ -175,28 +177,26 @@ impl Context {
     }
 
     /// Bind a wire to a net. This method must be used when binding a wire that is driven by a bel pin. Use bindPip() when binding a wire that is driven by a pip.
-    ///
-    /// # Safety
-    /// `net` must be valid and not null.
-    pub unsafe fn bind_wire(&mut self, wire: WireId, net: *mut NetInfo, strength: PlaceStrength) {
+    pub fn bind_wire(&mut self, wire: WireId, net: &mut NetInfo, strength: PlaceStrength) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_bind_wire(self, wire, net, strength) }
     }
 
     /// Unbind a wire. For wires that are driven by a pip, this will also unbind the driving pip.
     pub fn unbind_wire(&mut self, wire: WireId) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_unbind_wire(self, wire) }
     }
 
     /// Bind a pip to a net. This also binds the destination wire of that pip.
-    ///
-    /// # Safety
-    /// `net` must be valid and not null.
-    pub unsafe fn bind_pip(&mut self, pip: PipId, net: *mut NetInfo, strength: PlaceStrength) {
+    pub fn bind_pip(&mut self, pip: PipId, net: &mut NetInfo, strength: PlaceStrength) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_bind_pip(self, pip, net, strength) }
     }
 
     /// Unbind a pip and the wire driven by that pip.
     pub fn unbind_pip(&mut self, pip: PipId) {
+        let _lock = ARCH_MUTEX.lock().unwrap();
         unsafe { npnr_context_unbind_pip(self, pip) }
     }
 
@@ -332,16 +332,17 @@ impl Context {
     }
 
     pub fn name_of(&self, s: IdString) -> &CStr {
+        let _lock = RINGBUFFER_MUTEX.lock().unwrap();
         unsafe { CStr::from_ptr(npnr_context_name_of(self, s)) }
     }
 
     pub fn name_of_pip(&self, pip: PipId) -> &CStr {
+        let _lock = RINGBUFFER_MUTEX.lock().unwrap();
         unsafe { CStr::from_ptr(npnr_context_name_of_pip(self, pip)) }
     }
 
     pub fn name_of_wire(&self, wire: WireId) -> &CStr {
-        static MUTEX: Mutex<()> = Mutex::new(());
-        let _lock = MUTEX.lock().unwrap();
+        let _lock = RINGBUFFER_MUTEX.lock().unwrap();
         unsafe { CStr::from_ptr(npnr_context_name_of_wire(self, wire)) }
     }
 

From c5fc34f11acfed9ee36b9158b19804b10dfb2202 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 01:52:29 +0000
Subject: [PATCH 559/712] rust: slight cleanup

---
 rust/rust.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index 19e1b6ffd3..3d0276cd7b 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -129,7 +129,7 @@ bool npnr_context_check_pip_avail_for_net(const Context *ctx, uint64_t pip, NetI
     return ctx->checkPipAvailForNet(unwrap_pip(pip), net);
 }
 
-uint64_t npnr_context_get_pips_leak(const Context *const ctx, uint64_t **const pips)
+uint64_t npnr_context_get_pips_leak(const Context *ctx, uint64_t **const pips)
 {
     const auto ctx_pips{ctx->getPips()};
     const auto size{std::accumulate(ctx_pips.begin(), ctx_pips.end(), /*initial value*/ size_t{},
@@ -144,7 +144,7 @@ uint64_t npnr_context_get_pips_leak(const Context *const ctx, uint64_t **const p
     return size;
 }
 
-uint64_t npnr_context_get_wires_leak(const Context *const ctx, uint64_t **const wires)
+uint64_t npnr_context_get_wires_leak(const Context *ctx, uint64_t **const wires)
 {
     const auto ctx_wires{ctx->getWires()};
     const auto size{std::accumulate(ctx_wires.begin(), ctx_wires.end(), /*initial value*/ size_t{},

From c8e1cbc5f27d12b697646443a7debc84f148200e Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 01:55:50 +0000
Subject: [PATCH 560/712] rust: transform pointers to references where possible

---
 rust/nextpnr/src/lib.rs | 165 +++++++++++++++++++---------------------
 rust/rust.cc            |   2 +-
 2 files changed, 78 insertions(+), 89 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index 9ee7d0314a..a025c13fdf 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -32,7 +32,7 @@ pub struct NetInfo {
 }
 
 impl NetInfo {
-    pub fn driver(&mut self) -> *mut PortRef {
+    pub fn driver(&mut self) -> &mut PortRef {
         unsafe { npnr_netinfo_driver(self) }
     }
 
@@ -61,15 +61,10 @@ pub struct PortRef {
 }
 
 impl PortRef {
-    pub fn cell(&self) -> Option<&CellInfo> {
-        // SAFETY: handing out &s is safe when we have &self.
-        unsafe { npnr_portref_cell(self).as_ref() }
-    }
-
     pub fn cell_mut(&mut self) -> Option<&mut CellInfo> {
         // SAFETY: handing out &mut is safe when we have &mut self
         // as getting multiple &mut CellInfo would require multiple &mut PortRef.
-        unsafe { npnr_portref_cell(self).as_mut() }
+        unsafe { npnr_portref_cell(self) }
     }
 }
 
@@ -227,15 +222,11 @@ impl Context {
         unsafe { npnr_context_delay_epsilon(self) }
     }
 
-    /// # Safety
-    /// `net` must be valid and not null.
-    pub unsafe fn source_wire(&self, net: *const NetInfo) -> WireId {
+    pub fn source_wire(&self, net: &NetInfo) -> WireId {
         unsafe { npnr_context_get_netinfo_source_wire(self, net) }
     }
 
-    /// # Safety
-    /// `net` and `sink` must be valid and not null.
-    pub unsafe fn sink_wires(&self, net: *const NetInfo, sink: *const PortRef) -> Vec<WireId> {
+    pub fn sink_wires(&self, net: &NetInfo, sink: &PortRef) -> Vec<WireId> {
         let mut v = Vec::new();
         let mut n = 0;
         loop {
@@ -312,9 +303,7 @@ impl Context {
         Loc{x: dst.x - src.x, y: dst.y - src.y, z: 0}
     }
 
-    /// # Safety
-    /// `net` must be valid and not null.
-    pub unsafe fn pip_avail_for_net(&self, pip: PipId, net: *mut NetInfo) -> bool {
+    pub fn pip_avail_for_net(&self, pip: PipId, net: &mut NetInfo) -> bool {
         unsafe { npnr_context_check_pip_avail_for_net(self, pip, net) }
     }
 
@@ -359,92 +348,92 @@ extern "C" {
     fn npnr_wireid_null() -> WireId;
     fn npnr_pipid_null() -> PipId;
 
-    fn npnr_context_get_grid_dim_x(ctx: *const Context) -> libc::c_int;
-    fn npnr_context_get_grid_dim_y(ctx: *const Context) -> libc::c_int;
+    fn npnr_context_get_grid_dim_x(ctx: &Context) -> libc::c_int;
+    fn npnr_context_get_grid_dim_y(ctx: &Context) -> libc::c_int;
     fn npnr_context_bind_bel(
-        ctx: *mut Context,
+        ctx: &mut Context,
         bel: BelId,
-        cell: *mut CellInfo,
+        cell: &mut CellInfo,
         strength: PlaceStrength,
     );
-    fn npnr_context_unbind_bel(ctx: *mut Context, bel: BelId);
-    fn npnr_context_check_bel_avail(ctx: *const Context, bel: BelId) -> bool;
+    fn npnr_context_unbind_bel(ctx: &mut Context, bel: BelId);
+    fn npnr_context_check_bel_avail(ctx: &Context, bel: BelId) -> bool;
     fn npnr_context_bind_wire(
-        ctx: *mut Context,
+        ctx: &mut Context,
         wire: WireId,
-        net: *mut NetInfo,
+        net: &mut NetInfo,
         strength: PlaceStrength,
     );
-    fn npnr_context_unbind_wire(ctx: *mut Context, wire: WireId);
+    fn npnr_context_unbind_wire(ctx: &mut Context, wire: WireId);
     fn npnr_context_bind_pip(
-        ctx: *mut Context,
+        ctx: &mut Context,
         pip: PipId,
-        net: *mut NetInfo,
+        net: &mut NetInfo,
         strength: PlaceStrength,
     );
-    fn npnr_context_unbind_pip(ctx: *mut Context, pip: PipId);
-    fn npnr_context_get_pip_src_wire(ctx: *const Context, pip: PipId) -> WireId;
-    fn npnr_context_get_pip_dst_wire(ctx: *const Context, pip: PipId) -> WireId;
-    fn npnr_context_estimate_delay(ctx: *const Context, src: WireId, dst: WireId) -> f32;
-    fn npnr_context_delay_epsilon(ctx: *const Context) -> f32;
-    fn npnr_context_get_pip_delay(ctx: *const Context, pip: PipId) -> f32;
-    fn npnr_context_get_wire_delay(ctx: *const Context, wire: WireId) -> f32;
-    fn npnr_context_get_wires_leak(ctx: *const Context, wires: *mut *mut WireId) -> u64;
-    fn npnr_context_get_pips_leak(ctx: *const Context, pips: *mut *mut PipId) -> u64;
-    fn npnr_context_get_pip_location(ctx: *const Context, pip: PipId) -> Loc;
+    fn npnr_context_unbind_pip(ctx: &mut Context, pip: PipId);
+    fn npnr_context_get_pip_src_wire(ctx: &Context, pip: PipId) -> WireId;
+    fn npnr_context_get_pip_dst_wire(ctx: &Context, pip: PipId) -> WireId;
+    fn npnr_context_estimate_delay(ctx: &Context, src: WireId, dst: WireId) -> f32;
+    fn npnr_context_delay_epsilon(ctx: &Context) -> f32;
+    fn npnr_context_get_pip_delay(ctx: &Context, pip: PipId) -> f32;
+    fn npnr_context_get_wire_delay(ctx: &Context, wire: WireId) -> f32;
+    fn npnr_context_get_wires_leak(ctx: &Context, wires: *mut *mut WireId) -> u64;
+    fn npnr_context_get_pips_leak(ctx: &Context, pips: *mut *mut PipId) -> u64;
+    fn npnr_context_get_pip_location(ctx: &Context, pip: PipId) -> Loc;
     fn npnr_context_check_pip_avail_for_net(
-        ctx: *const Context,
+        ctx: &Context,
         pip: PipId,
-        net: *const NetInfo,
+        net: &NetInfo,
     ) -> bool;
 
-    fn npnr_context_check(ctx: *const Context);
-    fn npnr_context_debug(ctx: *const Context) -> bool;
-    fn npnr_context_id(ctx: *const Context, s: *const c_char) -> IdString;
-    fn npnr_context_name_of(ctx: *const Context, s: IdString) -> *const libc::c_char;
-    fn npnr_context_name_of_pip(ctx: *const Context, pip: PipId) -> *const libc::c_char;
-    fn npnr_context_name_of_wire(ctx: *const Context, wire: WireId) -> *const libc::c_char;
-    fn npnr_context_verbose(ctx: *const Context) -> bool;
+    fn npnr_context_check(ctx: &Context);
+    fn npnr_context_debug(ctx: &Context) -> bool;
+    fn npnr_context_id(ctx: &Context, s: *const c_char) -> IdString;
+    fn npnr_context_name_of(ctx: &Context, s: IdString) -> &libc::c_char;
+    fn npnr_context_name_of_pip(ctx: &Context, pip: PipId) -> &libc::c_char;
+    fn npnr_context_name_of_wire(ctx: &Context, wire: WireId) -> &libc::c_char;
+    fn npnr_context_verbose(ctx: &Context) -> bool;
 
-    fn npnr_context_get_netinfo_source_wire(ctx: *const Context, net: *const NetInfo) -> WireId;
+    fn npnr_context_get_netinfo_source_wire(ctx: &Context, net: &NetInfo) -> WireId;
     fn npnr_context_get_netinfo_sink_wire(
-        ctx: *const Context,
-        net: *const NetInfo,
-        sink: *const PortRef,
+        ctx: &Context,
+        net: &NetInfo,
+        sink: &PortRef,
         n: u32,
     ) -> WireId;
 
     fn npnr_context_nets_leak(
-        ctx: *const Context,
+        ctx: &Context,
         names: *mut *mut libc::c_int,
         nets: *mut *mut *mut NetInfo,
     ) -> u32;
-    fn npnr_context_get_pips_downhill(ctx: *const Context, wire: WireId) -> *mut RawDownhillIter;
-    fn npnr_delete_downhill_iter(iter: *mut RawDownhillIter);
-    fn npnr_context_get_pips_uphill(ctx: *const Context, wire: WireId) -> *mut RawUphillIter;
-    fn npnr_delete_uphill_iter(iter: *mut RawUphillIter);
-
-    fn npnr_netinfo_driver(net: *mut NetInfo) -> *mut PortRef;
-    fn npnr_netinfo_users_leak(net: *mut NetInfo, users: *mut *mut *mut PortRef) -> u32;
-    fn npnr_netinfo_is_global(net: *const NetInfo) -> bool;
-    fn npnr_netinfo_udata(net: *const NetInfo) -> NetIndex;
-    fn npnr_netinfo_udata_set(net: *mut NetInfo, value: NetIndex);
-
-    fn npnr_portref_cell(port: *const PortRef) -> *mut CellInfo;
-    fn npnr_cellinfo_get_location(info: *const CellInfo) -> Loc;
-
-    fn npnr_inc_downhill_iter(iter: *mut RawDownhillIter);
-    fn npnr_deref_downhill_iter(iter: *mut RawDownhillIter) -> PipId;
-    fn npnr_is_downhill_iter_done(iter: *mut RawDownhillIter) -> bool;
-    fn npnr_inc_uphill_iter(iter: *mut RawUphillIter);
-    fn npnr_deref_uphill_iter(iter: *mut RawUphillIter) -> PipId;
-    fn npnr_is_uphill_iter_done(iter: *mut RawUphillIter) -> bool;
+    fn npnr_context_get_pips_downhill(ctx: &Context, wire: WireId) -> &mut RawDownhillIter;
+    fn npnr_delete_downhill_iter(iter: &mut RawDownhillIter);
+    fn npnr_context_get_pips_uphill(ctx: &Context, wire: WireId) -> &mut RawUphillIter;
+    fn npnr_delete_uphill_iter(iter: &mut RawUphillIter);
+
+    fn npnr_netinfo_driver(net: &mut NetInfo) -> &mut PortRef;
+    fn npnr_netinfo_users_leak(net: &NetInfo, users: *mut *mut *const PortRef) -> u32;
+    fn npnr_netinfo_is_global(net: &NetInfo) -> bool;
+    fn npnr_netinfo_udata(net: &NetInfo) -> NetIndex;
+    fn npnr_netinfo_udata_set(net: &mut NetInfo, value: NetIndex);
+
+    fn npnr_portref_cell(port: &mut PortRef) -> Option<&mut CellInfo>;
+    fn npnr_cellinfo_get_location(info: &CellInfo) -> Loc;
+
+    fn npnr_inc_downhill_iter(iter: &mut RawDownhillIter);
+    fn npnr_deref_downhill_iter(iter: &mut RawDownhillIter) -> PipId;
+    fn npnr_is_downhill_iter_done(iter: &mut RawDownhillIter) -> bool;
+    fn npnr_inc_uphill_iter(iter: &mut RawUphillIter);
+    fn npnr_deref_uphill_iter(iter: &mut RawUphillIter) -> PipId;
+    fn npnr_is_uphill_iter_done(iter: &mut RawUphillIter) -> bool;
 }
 
 /// Store for the nets of a context.
 pub struct Nets<'a> {
-    nets: HashMap<IdString, *mut NetInfo>,
-    users: HashMap<IdString, &'a [&'a mut PortRef]>,
+    nets: HashMap<IdString, &'a mut NetInfo>,
+    users: HashMap<IdString, &'a [&'a PortRef]>,
     index_to_net: Vec<IdString>,
     _data: PhantomData<&'a Context>,
 }
@@ -471,21 +460,21 @@ impl<'a> Nets<'a> {
         let mut index_to_net = Vec::new();
         for i in 0..size {
             let name = unsafe { IdString(*names.add(i as usize)) };
-            let net = unsafe { *nets_ptr.add(i as usize) };
+            let net = unsafe { &mut **nets_ptr.add(i as usize) };
             let mut users_ptr = std::ptr::null_mut();
             // SAFETY: net is not null because it's a &mut, and users is only written to.
             // Leaking memory is the most convenient FFI I could think of.
             let len =
-                unsafe { npnr_netinfo_users_leak(net, &mut users_ptr as *mut *mut *mut PortRef) };
+                unsafe { npnr_netinfo_users_leak(net, &mut users_ptr as *mut *mut *const PortRef) };
             let users_slice =
-                unsafe { slice::from_raw_parts(users_ptr as *mut &mut PortRef, len as usize) };
-            nets.insert(name, net);
-            users.insert(name, users_slice);
+                unsafe { slice::from_raw_parts(users_ptr as *mut &PortRef, len as usize) };
             let index = index_to_net.len() as i32;
             index_to_net.push(name);
             unsafe {
                 npnr_netinfo_udata_set(net, NetIndex(index));
             }
+            nets.insert(name, net);
+            users.insert(name, users_slice);
         }
         // Note: the contents of `names` and `nets_ptr` are now lost.
         Self {
@@ -497,7 +486,7 @@ impl<'a> Nets<'a> {
     }
 
     /// Find net users given a net's name.
-    pub fn users_by_name(&self, net: IdString) -> Option<&&[&mut PortRef]> {
+    pub fn users_by_name(&self, net: IdString) -> Option<&&[&PortRef]> {
         self.users.get(&net)
     }
 
@@ -514,11 +503,11 @@ impl<'a> Nets<'a> {
         self.index_to_net[index.0 as usize]
     }
 
-    pub fn net_from_index(&self, index: NetIndex) -> *mut NetInfo {
-        *self.nets.get(&self.name_from_index(index)).unwrap()
+    pub fn net_from_index(&self, index: NetIndex) -> &NetInfo {
+        self.nets.get(&self.name_from_index(index)).unwrap()
     }
 
-    pub fn to_vec(&self) -> Vec<(&IdString, &*mut NetInfo)> {
+    pub fn to_vec(&self) -> Vec<(&IdString, &&mut NetInfo)> {
         let mut v = Vec::new();
         v.extend(self.nets.iter());
         v.sort_by_key(|(name, _net)| name.0);
@@ -528,8 +517,8 @@ impl<'a> Nets<'a> {
 
 pub struct NetSinkWireIter<'a> {
     ctx: &'a Context,
-    net: *const NetInfo,
-    sink: *const PortRef,
+    net: &'a NetInfo,
+    sink: &'a PortRef,
     n: u32,
 }
 
@@ -553,8 +542,8 @@ struct RawDownhillIter {
 }
 
 pub struct DownhillPipsIter<'a> {
-    iter: *mut RawDownhillIter,
-    phantom_data: std::marker::PhantomData<&'a PipId>,
+    iter: &'a mut RawDownhillIter,
+    phantom_data: PhantomData<&'a PipId>,
 }
 
 impl<'a> Iterator for DownhillPipsIter<'a> {
@@ -583,8 +572,8 @@ struct RawUphillIter {
 }
 
 pub struct UphillPipsIter<'a> {
-    iter: *mut RawUphillIter,
-    phantom_data: std::marker::PhantomData<&'a PipId>,
+    iter: &'a mut RawUphillIter,
+    phantom_data: PhantomData<&'a PipId>,
 }
 
 impl<'a> Iterator for UphillPipsIter<'a> {
diff --git a/rust/rust.cc b/rust/rust.cc
index 3d0276cd7b..d0ec0efc2b 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -214,7 +214,7 @@ PortRef *npnr_netinfo_driver(NetInfo *net)
     return &net->driver;
 }
 
-uint32_t npnr_netinfo_users_leak(NetInfo *net, PortRef ***users)
+uint32_t npnr_netinfo_users_leak(const NetInfo *net, const PortRef ***users)
 {
     auto size = net->users.entries();
     *users = new PortRef *[size];

From 6e4e81429c1aaa41bc414f2bfe2285150ed4f3c4 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 01:56:18 +0000
Subject: [PATCH 561/712] rust: nets isn't send/sync

---
 rust/nextpnr/src/lib.rs | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index a025c13fdf..898a150fd7 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -438,9 +438,6 @@ pub struct Nets<'a> {
     _data: PhantomData<&'a Context>,
 }
 
-unsafe impl Send for Nets<'_> {}
-unsafe impl Sync for Nets<'_> {}
-
 impl<'a> Nets<'a> {
     /// Create a new store for the nets of a context.
     ///

From d0e01661a5b7615b1e5bd55a072f45e430d26611 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 02:01:04 +0000
Subject: [PATCH 562/712] rust: fix build error

---
 rust/rust.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust/rust.cc b/rust/rust.cc
index d0ec0efc2b..b59e18717c 100644
--- a/rust/rust.cc
+++ b/rust/rust.cc
@@ -217,7 +217,7 @@ PortRef *npnr_netinfo_driver(NetInfo *net)
 uint32_t npnr_netinfo_users_leak(const NetInfo *net, const PortRef ***users)
 {
     auto size = net->users.entries();
-    *users = new PortRef *[size];
+    *users = new const PortRef *[size];
     auto idx = 0;
     for (auto &item : net->users) {
         (*users)[idx] = &item;

From dfd651a1325a4bc47d414db50dbccbb84ead85af Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 02:57:23 +0000
Subject: [PATCH 563/712] rust: fix some calls that got wrongly replaced

---
 rust/nextpnr/src/lib.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index 898a150fd7..85c1cf6d81 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -390,9 +390,9 @@ extern "C" {
     fn npnr_context_check(ctx: &Context);
     fn npnr_context_debug(ctx: &Context) -> bool;
     fn npnr_context_id(ctx: &Context, s: *const c_char) -> IdString;
-    fn npnr_context_name_of(ctx: &Context, s: IdString) -> &libc::c_char;
-    fn npnr_context_name_of_pip(ctx: &Context, pip: PipId) -> &libc::c_char;
-    fn npnr_context_name_of_wire(ctx: &Context, wire: WireId) -> &libc::c_char;
+    fn npnr_context_name_of(ctx: &Context, s: IdString) -> *const libc::c_char;
+    fn npnr_context_name_of_pip(ctx: &Context, pip: PipId) -> *const libc::c_char;
+    fn npnr_context_name_of_wire(ctx: &Context, wire: WireId) -> *const libc::c_char;
     fn npnr_context_verbose(ctx: &Context) -> bool;
 
     fn npnr_context_get_netinfo_source_wire(ctx: &Context, net: &NetInfo) -> WireId;

From 14a09061a5ebe16f4beba39f34ce79f2484b5801 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 16 Jan 2024 02:57:47 +0000
Subject: [PATCH 564/712] rust: rework portref_cell

---
 rust/nextpnr/src/lib.rs | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index 85c1cf6d81..b3386ebc6f 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -61,9 +61,8 @@ pub struct PortRef {
 }
 
 impl PortRef {
-    pub fn cell_mut(&mut self) -> Option<&mut CellInfo> {
-        // SAFETY: handing out &mut is safe when we have &mut self
-        // as getting multiple &mut CellInfo would require multiple &mut PortRef.
+    pub fn cell(&self) -> Option<&CellInfo> {
+        // SAFETY: handing out &s is safe when we have &self.
         unsafe { npnr_portref_cell(self) }
     }
 }
@@ -419,7 +418,7 @@ extern "C" {
     fn npnr_netinfo_udata(net: &NetInfo) -> NetIndex;
     fn npnr_netinfo_udata_set(net: &mut NetInfo, value: NetIndex);
 
-    fn npnr_portref_cell(port: &mut PortRef) -> Option<&mut CellInfo>;
+    fn npnr_portref_cell(port: &PortRef) -> Option<&CellInfo>;
     fn npnr_cellinfo_get_location(info: &CellInfo) -> Loc;
 
     fn npnr_inc_downhill_iter(iter: &mut RawDownhillIter);

From a0e360fd9f3c73f36d42e4b8450c339858a8de47 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 17 Jan 2024 12:25:00 +0000
Subject: [PATCH 565/712] rust: convert netinfo_driver to Option

---
 rust/nextpnr/src/lib.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rust/nextpnr/src/lib.rs b/rust/nextpnr/src/lib.rs
index b3386ebc6f..66a96ee15f 100644
--- a/rust/nextpnr/src/lib.rs
+++ b/rust/nextpnr/src/lib.rs
@@ -32,7 +32,7 @@ pub struct NetInfo {
 }
 
 impl NetInfo {
-    pub fn driver(&mut self) -> &mut PortRef {
+    pub fn driver(&mut self) -> Option<&mut PortRef> {
         unsafe { npnr_netinfo_driver(self) }
     }
 
@@ -412,7 +412,7 @@ extern "C" {
     fn npnr_context_get_pips_uphill(ctx: &Context, wire: WireId) -> &mut RawUphillIter;
     fn npnr_delete_uphill_iter(iter: &mut RawUphillIter);
 
-    fn npnr_netinfo_driver(net: &mut NetInfo) -> &mut PortRef;
+    fn npnr_netinfo_driver(net: &mut NetInfo) -> Option<&mut PortRef>;
     fn npnr_netinfo_users_leak(net: &NetInfo, users: *mut *mut *const PortRef) -> u32;
     fn npnr_netinfo_is_global(net: &NetInfo) -> bool;
     fn npnr_netinfo_udata(net: &NetInfo) -> NetIndex;

From 4220ce100776381fcaed4ceb2efed722e7ddf474 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 18 Jan 2024 15:34:40 +0100
Subject: [PATCH 566/712] gui: Remove const on max_elems_

Signed-off-by: gatecat <gatecat@ds0.me>
---
 gui/quadtree.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gui/quadtree.h b/gui/quadtree.h
index d28e4e8f79..f240f34589 100644
--- a/gui/quadtree.h
+++ b/gui/quadtree.h
@@ -116,7 +116,7 @@ template <typename CoordinateT, typename ElementT> class QuadTreeNode
     BoundingBox bound_;
     // How many elements should be contained in this node until it splits into
     // sub-nodes.
-    const size_t max_elems_;
+    size_t max_elems_;
     // Four sub-nodes or nullptr if it hasn't split yet.
     std::unique_ptr<QuadTreeNode<CoordinateT, ElementT>[]> children_ = nullptr;
     // Coordinates of the split.

From 8968c84ce650bfb02a69faa74ed99c62a7ac0954 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 23 Jan 2024 12:16:14 +0100
Subject: [PATCH 567/712] Increase the set of PnR-excluded cells

Signed-off-by: gatecat <gatecat@ds0.me>
---
 frontend/frontend_base.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index a96a396efb..bdc8a896c8 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -448,7 +448,7 @@ template <typename FrontendType> struct GenericFrontend
     void import_leaf_cell(HierModuleState &m, const std::string &name, const cell_dat_t &cd)
     {
         auto cell_type = impl.get_cell_type(cd);
-        if (cell_type == "$scopeinfo")
+        if (cell_type == "$scopeinfo" || cell_type == "$print" || cell_type == "$check")
             return;
         IdString inst_name = unique_name(m.prefix, name, false);
         ctx->hierarchy[m.path].leaf_cells_by_gname[inst_name] = ctx->id(name);

From 97f5c3ca2ca5936eab832f595520bbd3c85a6e42 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Sat, 20 Jan 2024 14:58:03 +0100
Subject: [PATCH 568/712] Add documentation for Himbaechel Gowin uarch

---
 README.md | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 9fee3b15c0..8f3070f183 100644
--- a/README.md
+++ b/README.md
@@ -118,29 +118,33 @@ sudo make install
 
 Nexus support is currently experimental, and has only been tested with engineering sample silicon.
 
-### nextpnr-gowin
+### nextpnr-generic
 
-For Gowin support, install [Project Apicula](https://github.com/YosysHQ/apicula). If a virtualenv is used, the path to `gowin_bba` needs to be provided as follows:
+The generic target allows running placement and routing for arbitrary custom architectures.
 
 ```
-cmake . -DARCH=gowin -DGOWIN_BBA_EXECUTABLE=path
+cmake . -DARCH=generic
 make -j$(nproc)
 sudo make install
 ```
 
- - Examples of the Gowin flow for a range of boards can be found in the [Project Apicula Examples](https://github.com/YosysHQ/apicula/tree/master/examples).
+An example of how to use the generic flow is in [generic/examples](generic/examples). See also the [Generic Architecture docs](docs/generic.md).
 
-### nextpnr-generic
+### nextpnr-himbaechel
 
-The generic target allows running placement and routing for arbitrary custom architectures.
+The himbaechel target allows running placement and routing for larger architectures that share a common structure.
+
+#### gowin
+
+For Gowin support, install [Project Apicula](https://github.com/YosysHQ/apicula)
 
 ```
-cmake . -DARCH=generic
+cmake . -DARCH="himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="all"
 make -j$(nproc)
 sudo make install
 ```
 
-An example of how to use the generic flow is in [generic/examples](generic/examples). See also the [Generic Architecture docs](docs/generic.md).
+ - Examples of the Gowin flow for a range of boards can be found in the [Project Apicula Examples](https://github.com/YosysHQ/apicula/tree/master/examples).
 
 ### GUI
 

From 91b0c4f90a71cb18413e1ffa1129184c8ecad67d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 23 Jan 2024 14:50:36 +1000
Subject: [PATCH 569/712] gowin: Himbaechel. Deal with SP BSRAM ports.

The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.

Also:
  * All PIPs for clock spines are made inaccessible to the common router
    - in general, using these routes for signals that have not been
    processed by a special globals router is fraught with effects that
    are difficult to detect.
  * The INV primitive has been added purely to speed up development -
    this primitive is not generated by Yosys, but is almost always
    present in vendor output files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc  |  3 ++
 himbaechel/uarch/gowin/globals.cc    |  4 ++-
 himbaechel/uarch/gowin/gowin.cc      |  6 ++++
 himbaechel/uarch/gowin/gowin_utils.h | 15 ++++++++++
 himbaechel/uarch/gowin/pack.cc       | 42 ++++++++++++++++++++++++++++
 5 files changed, 69 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 70f0d9896b..f357783c72 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -934,6 +934,9 @@ X(GSR)
 X(GSR0)
 X(GSRI)
 
+// inverter
+X(INV)
+
 // Oscillators
 X(OSC)
 X(OSCZ)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index c818f762a3..0489a9e00c 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -40,6 +40,8 @@ struct GowinGlobalRouter
 
     GowinGlobalRouter(Context *ctx) : ctx(ctx) { gwu.init(ctx); };
 
+    bool checkPipAvail(PipId pip) const { return gwu.is_global_pip(pip) || ctx->checkPipAvail(pip); };
+
     // allow io->global, global->global and global->tile clock
     bool global_pip_filter(PipId pip) const
     {
@@ -91,7 +93,7 @@ struct GowinGlobalRouter
             // Search uphill pips
             for (PipId pip : ctx->getPipsUphill(cursor)) {
                 // Skip pip if unavailable, and not because it's already used for this net
-                if (!ctx->checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net) {
+                if (!checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net) {
                     continue;
                 }
                 WireId prev = ctx->getPipSrcWire(pip);
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 920d86facf..cae8f1ab88 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -38,6 +38,9 @@ struct GowinImpl : HimbaechelAPI
 
     bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
 
+    // wires
+    bool checkPipAvail(PipId pip) const override;
+
   private:
     HimbaechelHelpers h;
     GowinUtils gwu;
@@ -154,6 +157,9 @@ void GowinImpl::init(Context *ctx)
     }
 }
 
+// We do not allow the use of global wires that bypass a special router.
+bool GowinImpl::checkPipAvail(PipId pip) const { return !gwu.is_global_pip(pip); }
+
 void GowinImpl::pack()
 {
     if (ctx->settings.count(ctx->id("cst.filename"))) {
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 5d2c6571df..d93c602974 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -38,6 +38,21 @@ struct GowinUtils
 
     // wires
     inline bool is_wire_type_default(IdString wire_type) { return wire_type == IdString(); }
+    // If wire is an important part of the global network (like SPINExx)
+    inline bool is_global_wire(WireId wire) const
+    {
+        return ctx->getWireName(wire)[1].in(
+                id_SPINE0, id_SPINE1, id_SPINE2, id_SPINE3, id_SPINE4, id_SPINE5, id_SPINE6, id_SPINE7, id_SPINE8,
+                id_SPINE9, id_SPINE10, id_SPINE11, id_SPINE12, id_SPINE13, id_SPINE14, id_SPINE15, id_SPINE16,
+                id_SPINE17, id_SPINE18, id_SPINE19, id_SPINE20, id_SPINE21, id_SPINE22, id_SPINE23, id_SPINE24,
+                id_SPINE25, id_SPINE26, id_SPINE27, id_SPINE28, id_SPINE29, id_SPINE30, id_SPINE31);
+    }
+
+    // pips
+    inline bool is_global_pip(PipId pip) const
+    {
+        return is_global_wire(ctx->getPipSrcWire(pip)) || is_global_wire(ctx->getPipDstWire(pip));
+    }
 
     // chip dependent
     bool have_SP32(void);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 5b0cc18383..5a2867dedb 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1294,6 +1294,24 @@ struct GowinPacker
         }
     }
 
+    // If the memory is controlled by the CE, then it is logical for the OCE to
+    // also respond to this signal, unless the OCE is controlled separately.
+    void bsram_handle_sp_oce(CellInfo *ci, IdString ce_pin, IdString oce_pin)
+    {
+        const NetInfo *net = ci->getPort(oce_pin);
+        NPNR_ASSERT(ci->getPort(ce_pin) != nullptr);
+        if (net == nullptr || net->name == ctx->id("$PACKER_VCC") || net->name == ctx->id("$PACKER_GND")) {
+            if (net != nullptr) {
+                ci->disconnectPort(oce_pin);
+            }
+            ci->copyPortTo(ce_pin, ci, oce_pin);
+        }
+        if (ctx->verbose) {
+            log_info("%s: %s = %s = %s\n", ctx->nameOf(ci), ce_pin.c_str(ctx), oce_pin.c_str(ctx),
+                     ctx->nameOf(ci->getPort(oce_pin)));
+        }
+    }
+
     void pack_ROM(CellInfo *ci)
     {
         int default_bw = 32;
@@ -1512,6 +1530,8 @@ struct GowinPacker
         }
 
         int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
+        bsram_handle_sp_oce(ci, id_CE, id_OCE);
+
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.
@@ -1623,6 +1643,25 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // Replace INV with LUT
+    // ===================================
+    void pack_inv(void)
+    {
+        log_info("Pack INV..\n");
+
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+
+            if (ci.type == id_INV) {
+                ci.type = id_LUT4;
+                ci.renamePort(id_O, id_F);
+                ci.renamePort(id_I, id_I3); // use D - it's simple for INIT
+                ci.params[id_INIT] = Property(0x00ff);
+            }
+        }
+    }
+
     // ===================================
     // PLL
     // ===================================
@@ -1700,6 +1739,9 @@ struct GowinPacker
         pack_gsr();
         ctx->check();
 
+        pack_inv();
+        ctx->check();
+
         pack_wideluts();
         ctx->check();
 

From 73b7de74a5769095acb96eb6c6333ffe161452f2 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 23 Jan 2024 21:57:23 +1000
Subject: [PATCH 570/712] gowin: Himbaechel. Fix the style.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 0489a9e00c..229f2908df 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -40,7 +40,7 @@ struct GowinGlobalRouter
 
     GowinGlobalRouter(Context *ctx) : ctx(ctx) { gwu.init(ctx); };
 
-    bool checkPipAvail(PipId pip) const { return gwu.is_global_pip(pip) || ctx->checkPipAvail(pip); };
+    bool global_pip_available(PipId pip) const { return gwu.is_global_pip(pip) || ctx->checkPipAvail(pip); };
 
     // allow io->global, global->global and global->tile clock
     bool global_pip_filter(PipId pip) const
@@ -93,7 +93,7 @@ struct GowinGlobalRouter
             // Search uphill pips
             for (PipId pip : ctx->getPipsUphill(cursor)) {
                 // Skip pip if unavailable, and not because it's already used for this net
-                if (!checkPipAvail(pip) && ctx->getBoundPipNet(pip) != net) {
+                if (!global_pip_available(pip) && ctx->getBoundPipNet(pip) != net) {
                     continue;
                 }
                 WireId prev = ctx->getPipSrcWire(pip);

From 9dcd0eff16ee5cd16ca7e065b513636320b46733 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 24 Jan 2024 15:36:37 +0100
Subject: [PATCH 571/712] static: Add a basic threadpool

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 121 ++++++++++++++++++++++++++++++----
 1 file changed, 108 insertions(+), 13 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index d3cb4863d5..a7a0004f95 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -40,6 +40,14 @@
 
 #include "fftsg.h"
 
+#ifndef NEXTPNR_DISABLE_THREADS
+#include <atomic>
+#include <condition_variable>
+#include <mutex>
+#include <thread>
+
+#endif
+
 NEXTPNR_NAMESPACE_BEGIN
 
 using namespace StaticUtil;
@@ -140,6 +148,93 @@ struct PlacerNet
     int hpwl() { return (b1.x - b0.x) + (b1.y - b0.y); }
 };
 
+#ifdef NEXTPNR_DISABLE_THREADS
+struct ThreadPool
+{
+    ThreadPool(int){};
+
+    void run(int N, std::function<void(int)> func)
+    {
+        for (int i = 0; i < N; i++)
+            func(i);
+    };
+};
+#else
+struct ThreadPool
+{
+    ThreadPool(int thread_count)
+    {
+        done.resize(thread_count, false);
+        for (int i = 0; i < thread_count; i++) {
+            threads.emplace_back([this, i]() { this->worker(i); });
+        }
+    }
+    std::vector<std::thread> threads;
+    std::condition_variable cv_start, cv_done;
+    std::mutex mutex;
+
+    bool work_available = false;
+    bool shutdown = false;
+    std::vector<bool> done;
+    std::function<void(int)> work;
+    int work_count;
+
+    ~ThreadPool()
+    {
+        {
+            std::lock_guard lk(mutex);
+            shutdown = true;
+        }
+        cv_start.notify_all();
+        for (auto &t : threads)
+            t.join();
+    }
+
+    void run(int N, std::function<void(int)> func)
+    {
+        {
+            std::lock_guard lk(mutex);
+            work = func;
+            work_count = N;
+            work_available = true;
+            std::fill(done.begin(), done.end(), false);
+        }
+        cv_start.notify_all();
+        {
+            std::unique_lock lk(mutex);
+            cv_done.wait(lk, [this] { return std::all_of(done.begin(), done.end(), [](bool x) { return x; }); });
+            work_available = false;
+        }
+    }
+
+    void worker(int idx)
+    {
+        while (true) {
+            std::unique_lock lk(mutex);
+            cv_start.wait(lk, [this, idx] { return (work_available && !done.at(idx)) || shutdown; });
+            if (shutdown) {
+                lk.unlock();
+                break;
+            } else if (work_available && !done.at(idx)) {
+                int work_per_thread = (work_count + int(threads.size()) - 1) / threads.size();
+                int begin = work_per_thread * idx;
+                int end = std::min(work_count, work_per_thread * (idx + 1));
+                lk.unlock();
+
+                for (int j = begin; j < end; j++) {
+                    work(j);
+                }
+
+                lk.lock();
+                done.at(idx) = true;
+                lk.unlock();
+                cv_done.notify_one();
+            }
+        }
+    }
+};
+#endif
+
 class StaticPlacer
 {
     Context *ctx;
@@ -154,6 +249,7 @@ class StaticPlacer
 
     FastBels fast_bels;
     TimingAnalyser tmg;
+    ThreadPool pool;
 
     int width, height;
     int iter = 0;
@@ -626,12 +722,14 @@ class StaticPlacer
 
     RealPair wl_coeff{0.5f, 0.5f};
 
-    void update_nets(Axis axis, bool ref)
+    void update_nets(bool ref)
     {
         static constexpr float min_wirelen_force = -300.f;
-        for (auto &net : nets) {
+        pool.run(2 * nets.size(), [&](int i) {
+            auto &net = nets.at(i / 2);
+            auto axis = (i % 2) ? Axis::Y : Axis::X;
             if (net.skip)
-                continue;
+                return;
             net.min_exp.at(axis) = 0;
             net.x_min_exp.at(axis) = 0;
             net.max_exp.at(axis) = 0;
@@ -665,7 +763,7 @@ class StaticPlacer
             }
             net.wa_wl.at(axis) =
                     (net.x_max_exp.at(axis) / net.max_exp.at(axis)) - (net.x_min_exp.at(axis) / net.min_exp.at(axis));
-        }
+        });
     }
 
     float wirelen_grad(CellInfo *cell, Axis axis, bool ref)
@@ -709,13 +807,11 @@ class StaticPlacer
     void update_gradients(bool ref = true, bool set_prev = true, bool init_penalty = false)
     {
         // TODO: skip non-group cells more efficiently?
-        for (int group = 0; group < int(groups.size()); group++) {
+        pool.run(groups.size(), [&](int group) {
             compute_density(group, ref);
             run_fft(group);
-        }
-        for (auto axis : {Axis::X, Axis::Y}) {
-            update_nets(axis, ref);
-        }
+        });
+        update_nets(ref);
         // First loop: back up gradients if required; set to zero; and compute density gradient
         for (auto &cell : mcells) {
             auto &g = groups.at(cell.group);
@@ -966,9 +1062,7 @@ class StaticPlacer
         log_info("Strict legalising %d cells...\n", int(to_legalise.size()));
         float pre_hpwl = system_hpwl();
         legalise_placement_strict(true);
-        for (auto axis : {Axis::X, Axis::Y}) {
-            update_nets(axis, true);
-        }
+        update_nets(true);
         float post_hpwl = system_hpwl();
         log_info("HPWL after legalise: %f (delta: %f)\n", post_hpwl, post_hpwl - pre_hpwl);
     }
@@ -1244,7 +1338,8 @@ class StaticPlacer
     }
 
   public:
-    StaticPlacer(Context *ctx, PlacerStaticCfg cfg) : ctx(ctx), cfg(cfg), fast_bels(ctx, true, 8), tmg(ctx)
+    StaticPlacer(Context *ctx, PlacerStaticCfg cfg)
+            : ctx(ctx), cfg(cfg), fast_bels(ctx, true, 8), tmg(ctx), pool(ctx->setting<int>("threads", 8))
     {
         groups.resize(cfg.cell_groups.size());
     };

From e7192cd37554639babde2b6cc6b58d2e56f7357f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 26 Jan 2024 17:57:22 +0100
Subject: [PATCH 572/712] static: Fix ifdefs

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index a7a0004f95..4d10f0732f 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -40,7 +40,7 @@
 
 #include "fftsg.h"
 
-#ifndef NEXTPNR_DISABLE_THREADS
+#ifndef NPNR_DISABLE_THREADS
 #include <atomic>
 #include <condition_variable>
 #include <mutex>
@@ -148,7 +148,7 @@ struct PlacerNet
     int hpwl() { return (b1.x - b0.x) + (b1.y - b0.y); }
 };
 
-#ifdef NEXTPNR_DISABLE_THREADS
+#ifdef NPNR_DISABLE_THREADS
 struct ThreadPool
 {
     ThreadPool(int){};

From 325985e055ec53a54fd8fef5fe396ee53230bd9a Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 27 Jan 2024 22:26:45 +1000
Subject: [PATCH 573/712] gowin: Himbaechel. SPX9 BSRAM BUGFIX.

This type setting is not needed here - the packer distinguishes memory
features by the X9 attribute, which will be correct anyway.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 5a2867dedb..ccddef2d46 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1465,9 +1465,6 @@ struct GowinPacker
         NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
 
         IdString cell_type = id_SP;
-        if (bw == 36) {
-            cell_type = id_SPX9;
-        }
         IdString name = ctx->idf("%s_AUX", ctx->nameOf(ci));
 
         auto sp_cell = gwu.create_cell(name, cell_type);

From a65ddff8ba2e4748c2a12bcd653629c3f4226c8a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Jan 2024 09:45:04 +0100
Subject: [PATCH 574/712] Update workflows

---
 .github/workflows/arch_ci.yml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index 63f7e4fa86..cc4bc44eb9 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -20,11 +20,11 @@ jobs:
       MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
       APYCULA_REVISION: 0.8.2a1
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         submodules: recursive
 
-    - uses: actions/setup-python@v4
+    - uses: actions/setup-python@v5
       with:
         python-version: '3.10'
     - name: Install
@@ -33,7 +33,7 @@ jobs:
         sudo apt-get install git make cmake libboost-all-dev python3-dev pypy3 libeigen3-dev tcl-dev lzma-dev libftdi-dev clang bison flex swig qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools iverilog
 
     - name: Cache yosys installation
-      uses: actions/cache@v3
+      uses: actions/cache@v4
       id: cache-yosys
       with:
         path: .yosys
@@ -46,7 +46,7 @@ jobs:
       if: steps.cache-yosys.outputs.cache-hit != 'true'
 
     - name: Cache icestorm installation
-      uses: actions/cache@v3
+      uses: actions/cache@v4
       id: cache-icestorm
       with:
         path: .icestorm
@@ -60,7 +60,7 @@ jobs:
       if: matrix.arch == 'ice40' && steps.cache-icestorm.outputs.cache-hit != 'true'
 
     - name: Cache trellis installation
-      uses: actions/cache@v3
+      uses: actions/cache@v4
       id: cache-trellis
       with:
         path: .trellis
@@ -74,7 +74,7 @@ jobs:
       if: (matrix.arch == 'ecp5' || matrix.arch == 'machxo2') && steps.cache-trellis.outputs.cache-hit != 'true'
 
     - name: Cache prjoxide installation
-      uses: actions/cache@v3
+      uses: actions/cache@v4
       id: cache-prjoxide
       with:
         path: .prjoxide

From b05cb86291c837e739962080378d68da123f0009 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 29 Jan 2024 09:40:34 +1000
Subject: [PATCH 575/712] gowin: Himbaechel. Global router BUGFIX.

Ignore networks without users.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 229f2908df..b13d4386b8 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -186,9 +186,6 @@ struct GowinGlobalRouter
                 break;
             }
         }
-        if (!routed) {
-            ctx->unbindWire(src);
-        }
         return routed;
     }
 
@@ -280,7 +277,10 @@ struct GowinGlobalRouter
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
-            if (drv == nullptr) {
+            if (drv == nullptr || ni->users.empty()) {
+                if (ctx->verbose) {
+                    log_info("skip empty or driverless net:%s\n", ctx->nameOf(ni));
+                }
                 continue;
             }
             if (driver_is_buf(ni->driver)) {
@@ -294,7 +294,10 @@ struct GowinGlobalRouter
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
-            if (drv == nullptr) {
+            if (drv == nullptr || ni->users.empty()) {
+                if (ctx->verbose) {
+                    log_info("skip empty or driverless net:%s\n", ctx->nameOf(ni));
+                }
                 continue;
             }
             if (driver_is_clksrc(ni->driver)) {

From 4eeb56c0e0c3d98afdf6224c9b25adca169d4363 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 31 Jan 2024 16:04:31 +1000
Subject: [PATCH 576/712] gowin: Himbaechel. Improve global router.

* Don't stop at the first bad "arc", but use the global network to the
  maximum.
* Report partial/full use of global wires for the network.
* In case of complete routing failure, releasing the source - this is
  actually a BUGFIX.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 38 ++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 11 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index b13d4386b8..0520c57220 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -71,7 +71,7 @@ struct GowinGlobalRouter
     template <typename Tfilt>
     bool backwards_bfs_route(NetInfo *net, WireId src, WireId dst, int iter_limit, bool strict, Tfilt pip_filter)
     {
-        // log_info("%s:%s->%s\n", net->name.c_str(ctx), ctx->nameOfWire(src), ctx->nameOfWire(dst));
+        // log_info("route arc %s:%s->%s\n", net->name.c_str(ctx), ctx->nameOfWire(src), ctx->nameOfWire(dst));
         // Queue of wires to visit
         std::queue<WireId> visit;
         // Wire -> upstream pip
@@ -141,7 +141,7 @@ struct GowinGlobalRouter
             // Bind pips until we hit already-bound routing
             for (PipId pip : pips) {
                 WireId dst = ctx->getPipDstWire(pip);
-                // log_info("%s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(dst));
+                // log_info("bind pip %s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(dst));
                 if (ctx->getBoundWireNet(dst) == net) {
                     break;
                 }
@@ -160,7 +160,14 @@ struct GowinGlobalRouter
         }
     }
 
-    bool route_direct_net(NetInfo *net)
+    enum RouteResult
+    {
+        NOT_ROUTED = 0,
+        ROUTED_PARTIALLY,
+        ROUTED_ALL
+    };
+
+    RouteResult route_direct_net(NetInfo *net)
     {
         // Lookup source and destination wires
         WireId src = ctx->getNetinfoSourceWire(net);
@@ -172,20 +179,24 @@ struct GowinGlobalRouter
             ctx->bindWire(src, net, STRENGTH_LOCKED);
         }
 
-        bool routed = false;
+        RouteResult routed = NOT_ROUTED;
         for (auto usr : net->users.enumerate()) {
             WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
             if (dst == WireId()) {
                 log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
                           ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
             }
-            routed = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
-            });
-            if (!routed) {
-                break;
+            if (backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                    return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
+                })) {
+                routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
+            } else {
+                routed = routed == NOT_ROUTED ? routed : ROUTED_PARTIALLY;
             }
         }
+        if (routed == NOT_ROUTED) {
+            ctx->unbindWire(src);
+        }
         return routed;
     }
 
@@ -229,8 +240,10 @@ struct GowinGlobalRouter
 
     void route_clk_net(NetInfo *net)
     {
-        if (route_direct_net(net)) {
-            log_info("    routed net '%s' using global resources\n", ctx->nameOf(net));
+        RouteResult res = route_direct_net(net);
+        if (res) {
+            log_info("    routed net '%s' using global resources %s\n", ctx->nameOf(net),
+                     res == ROUTED_ALL ? "completely" : "partially");
         }
     }
 
@@ -301,6 +314,9 @@ struct GowinGlobalRouter
                 continue;
             }
             if (driver_is_clksrc(ni->driver)) {
+                if (ctx->verbose) {
+                    log_info("route clock net '%s'\n", ctx->nameOf(ni));
+                }
                 route_clk_net(ni);
                 continue;
             }

From 833cb86b51d88a1a918a5e4b9a7d09b434a05288 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 6 Feb 2024 10:45:38 +1000
Subject: [PATCH 577/712] gowin: Himbaechel. Edit message text.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 0520c57220..881b036f5b 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -242,8 +242,8 @@ struct GowinGlobalRouter
     {
         RouteResult res = route_direct_net(net);
         if (res) {
-            log_info("    routed net '%s' using global resources %s\n", ctx->nameOf(net),
-                     res == ROUTED_ALL ? "completely" : "partially");
+            log_info("    routed net '%s' using global resources %s.\n", ctx->nameOf(net),
+                     res == ROUTED_ALL ? "only" : "partially");
         }
     }
 

From cc273c125775c07c612d1e1e8f39bc5d3370332c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 30 Jan 2024 11:13:07 +1000
Subject: [PATCH 578/712] gowin: Himbaechel. Handle SDP OCE

Semi-dual port BSRAM (in Gowin terminology) has the same feature as
Single Port - the CE and OCE signals must be synchronized.

Such a sin has not yet been noticed for Dual Port.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ccddef2d46..1045c76c11 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1395,6 +1395,7 @@ struct GowinPacker
             ci->renamePort(ctx->idf("BLKSELB[%d]", i), ctx->idf("BLKSELB%d", i));
         }
 
+        bsram_handle_sp_oce(ci, id_CEB, id_OCE);
         ci->copyPortTo(id_OCE, ci, id_OCEB);
 
         // Port A

From 255633c9f34742a6819cf74df53e0a4eb5b7ef74 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 9 Feb 2024 07:57:53 +0100
Subject: [PATCH 579/712] static: First pass at timing-driven placement

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 37 ++++++++++++++++++++++++++++++++++-
 ecp5/arch.cc                  |  3 +++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 4d10f0732f..7346821bba 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -795,7 +795,19 @@ class StaticPlacer
                          wl_coeff.at(axis) * pd.max_exp.at(axis) * x_max_sum) /
                         (max_sum * max_sum);
             }
-            gradient += (d_min - d_max);
+            float crit = 0.0;
+            if (cfg.timing_driven) {
+                if (port.second.type == PORT_IN) {
+                    crit = tmg.get_criticality(CellPortKey(cell->name, port.first));
+                } else if (port.second.type == PORT_OUT) {
+                    if (ni && ni->users.entries() < 5) {
+                        for (auto usr : ni->users)
+                            crit = std::max(crit, tmg.get_criticality(CellPortKey(usr)));
+                    }
+                }
+            }
+            float weight = 1.0 + 5 * std::pow(crit, 2);
+            gradient += weight * (d_min - d_max);
         }
 
         return gradient;
@@ -975,6 +987,7 @@ class StaticPlacer
                 initial_steplength *= 10;
             }
         }
+        update_timing();
     }
 
     RealPair clamp_loc(RealPair loc)
@@ -1034,6 +1047,26 @@ class StaticPlacer
         update_gradients(true);
         log_info("   system potential: %f hpwl: %f\n", system_potential(), system_hpwl());
         compute_overlap();
+        if ((iter % 5) == 0)
+            update_timing();
+    }
+
+    void update_timing()
+    {
+        if (!cfg.timing_driven)
+            return;
+        for (auto &net : nets) {
+            NetInfo *ni = net.ni;
+            if (ni->driver.cell == nullptr)
+                continue;
+            RealPair drv_loc = cell_loc(ni->driver.cell, false);
+            for (auto usr : ni->users.enumerate()) {
+                RealPair usr_loc = cell_loc(usr.value.cell, false);
+                delay_t est_delay = cfg.timing_c + cfg.timing_mx * std::abs(drv_loc.x - usr_loc.x) + cfg.timing_my * std::abs(drv_loc.y - usr_loc.y);
+                tmg.set_route_delay(CellPortKey(usr.value), DelayPair(est_delay));
+            }
+        }
+        tmg.run(false);
     }
 
     void legalise_step(bool dsp_bram)
@@ -1342,6 +1375,8 @@ class StaticPlacer
             : ctx(ctx), cfg(cfg), fast_bels(ctx, true, 8), tmg(ctx), pool(ctx->setting<int>("threads", 8))
     {
         groups.resize(cfg.cell_groups.size());
+        tmg.setup_only = true;
+        tmg.setup();
     };
     void place()
     {
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 8bf5db9194..54b070ea4d 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -627,6 +627,9 @@ void configure_static(Arch *arch, PlacerStaticCfg &cfg)
         comb.bel_area[id_MULT18X18D] = StaticRect(2.0f, 1.0f);
         comb.spacer_rect = StaticRect(2.0f, 1.0f);
     }
+    cfg.timing_c = (120 - 22 * arch->args.speed) * 6;
+    cfg.timing_mx = (120 - 22 * arch->args.speed);
+    cfg.timing_my = (120 - 22 * arch->args.speed);
 }
 } // namespace
 

From aa26ba7ea1024dde73f537dcae5cf1c01c4d3ea5 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 20 Feb 2024 10:25:35 +0100
Subject: [PATCH 580/712] static: Improve singleton handling

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 7346821bba..9b3d855643 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -408,7 +408,17 @@ class StaticPlacer
             StaticRect rect;
             // Mismatched group case
             if (!lookup_group(ci->type, cell_group, rect)) {
-                // TODO: what is the best thing to do here? singletons/odd cells we can probably mostly randomly place
+                for (auto bel : ctx->getBels()) {
+                    if (ctx->isValidBelForCellType(ci->type, bel) && ctx->checkBelAvail(bel)) {
+                        ctx->bindBel(bel, ci, STRENGTH_STRONG);
+                        if (!ctx->isBelLocationValid(bel)) {
+                            ctx->unbindBel(bel);
+                        } else {
+                            log_info("    placed potpourri cell '%s' at bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
+                            break;
+                        }
+                    }
+                }
                 continue;
             }
             if (ci->cluster != ClusterId()) {

From 05ed9308d6ea1167b570af3f97a90ffb3aed1d59 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 20 Feb 2024 10:44:00 +0100
Subject: [PATCH 581/712] ecp5: Improve router performance on slower speed
 grades

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ecp5/arch.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 54b070ea4d..3a8540274e 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -501,7 +501,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
 
     int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
 
-    return (120 - 22 * args.speed) *
+    return (80 - 9 * args.speed) *
            (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
@@ -579,11 +579,11 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
 
     int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
 
-    return (120 - 22 * args.speed) *
-           (3 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
+    return (80 - 9 * args.speed) *
+           (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
 }
 
-delay_t Arch::getRipupDelayPenalty() const { return 400; }
+delay_t Arch::getRipupDelayPenalty() const { return 550 - 50 * args.speed; }
 
 // -----------------------------------------------------------------------
 

From 4981ebb69836048fbde8a6bb1700cc6cd5a5af89 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 11 Feb 2024 10:52:05 +1000
Subject: [PATCH 582/712] gowin: Himbaechel. Improve the global router

A small improvement - do not waste time analyzing already processed
networks in the previous step (and possibly steps).

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 881b036f5b..86c3c63c6b 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -286,12 +286,14 @@ struct GowinGlobalRouter
     void run(void)
     {
         log_info("Routing globals...\n");
+
+        std::vector<IdString> routed_nets;
         // buffered nets first
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
             if (drv == nullptr || ni->users.empty()) {
-                if (ctx->verbose) {
+                if (ctx->debug) {
                     log_info("skip empty or driverless net:%s\n", ctx->nameOf(ni));
                 }
                 continue;
@@ -301,14 +303,21 @@ struct GowinGlobalRouter
                     log_info("route buffered net '%s'\n", ctx->nameOf(ni));
                 }
                 route_buffered_net(ni);
+                routed_nets.push_back(net.first);
                 continue;
             }
         }
         for (auto &net : ctx->nets) {
+            if (std::find(routed_nets.begin(), routed_nets.end(), net.first) != routed_nets.end()) {
+                if (ctx->debug) {
+                    log_info("skip already routed net:%s\n", net.first.c_str(ctx));
+                }
+                continue;
+            }
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
             if (drv == nullptr || ni->users.empty()) {
-                if (ctx->verbose) {
+                if (ctx->debug) {
                     log_info("skip empty or driverless net:%s\n", ctx->nameOf(ni));
                 }
                 continue;

From 4e8436a1fc6904b3d66dafaa20e15082470fc41c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 9 Feb 2024 17:44:57 +1000
Subject: [PATCH 583/712] gowin: Himbaechel. Allow to combine IOLOGIC.

Corrects the situation when it is impossible to use IOBUF with two
IOLOGIC elements at the same time - input and output.

Addresses https://github.com/YosysHQ/nextpnr/issues/1275

This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and
output IOLOGIC plus checking for compatibility of the cells located
there.

At the moment, this check is simple and allows only the combination of
DDR and DDRC primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  3 +-
 himbaechel/uarch/gowin/gowin.cc          | 17 +++++---
 himbaechel/uarch/gowin/gowin.h           | 21 ++++++----
 himbaechel/uarch/gowin/gowin_arch_gen.py | 31 +++++++-------
 himbaechel/uarch/gowin/gowin_utils.cc    |  5 ++-
 himbaechel/uarch/gowin/pack.cc           | 51 ++++++++++++++++++++----
 6 files changed, 91 insertions(+), 37 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index f357783c72..7b888ee88d 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -797,7 +797,8 @@ X(IDES8)
 X(IDES10)
 X(IVIDEO)
 X(IDES16)
-X(IOLOGIC)
+X(IOLOGICI)
+X(IOLOGICO)
 X(IOLOGICA)
 X(IOLOGICB)
 X(IOLOGIC_TYPE)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index cae8f1ab88..0b80fd5007 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -200,7 +200,8 @@ void GowinImpl::postRoute()
 
     for (auto &cell : ctx->cells) {
         auto ci = cell.second.get();
-        if (ci->type == id_IOLOGIC || (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
+        if (ci->type.in(id_IOLOGICI, id_IOLOGICO) ||
+            ((is_iologici(ci) || is_iologico(ci)) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
             if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
                 // mark FCLK<-HCLK connections
                 const NetInfo *h_net = ci->getPort(id_FCLK);
@@ -269,8 +270,11 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
     if (type_is_ssram(cell_type)) {
         return id_RAM16SDP4;
     }
-    if (type_is_iologic(cell_type)) {
-        return id_IOLOGIC;
+    if (type_is_iologici(cell_type)) {
+        return id_IOLOGICI;
+    }
+    if (type_is_iologico(cell_type)) {
+        return id_IOLOGICO;
     }
     if (type_is_bsram(cell_type)) {
         return id_BSRAM;
@@ -299,8 +303,11 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
     if (bel_type == id_RAM16SDP4) {
         return type_is_ssram(cell_type);
     }
-    if (bel_type == id_IOLOGIC) {
-        return type_is_iologic(cell_type);
+    if (bel_type == id_IOLOGICI) {
+        return type_is_iologici(cell_type);
+    }
+    if (bel_type == id_IOLOGICO) {
+        return type_is_iologico(cell_type);
     }
     if (bel_type == id_BSRAM) {
         return type_is_bsram(cell_type);
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 79fc4ea7cc..715f54e682 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -28,12 +28,19 @@ inline bool type_is_diffio(IdString cell_type)
 }
 inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type); }
 
-inline bool type_is_iologic(IdString cell_type)
+// IOLOGIC input and output separately
+
+inline bool type_is_iologico(IdString cell_type)
+{
+    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO);
+}
+inline bool is_iologico(const CellInfo *cell) { return type_is_iologico(cell->type); }
+
+inline bool type_is_iologici(IdString cell_type)
 {
-    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO, id_IDDR, id_IDDRC, id_IDES4,
-                        id_IDES8, id_IDES10, id_IVIDEO);
+    return cell_type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO);
 }
-inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type); }
+inline bool is_iologici(const CellInfo *cell) { return type_is_iologici(cell->type); }
 
 // Return true if a cell is a SSRAM
 inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
@@ -96,10 +103,10 @@ enum
     IOBB_Z = 51, // +IOBC...IOBL
 
     IOLOGICA_Z = 70,
-    IDES16_Z = 72,
-    OSER16_Z = 73,
+    IDES16_Z = 74,
+    OSER16_Z = 75,
 
-    BUFG_Z = 74, // : 81 reserve just in case
+    BUFG_Z = 76, // : 81 reserve just in case
     BSRAM_Z = 100,
 
     OSC_Z = 274,
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 413801f4da..2f96ee550e 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -32,10 +32,10 @@
 IOBB_Z  = 51
 
 IOLOGICA_Z = 70
-IDES16_Z   = 72
-OSER16_Z   = 73
+IDES16_Z   = 74
+OSER16_Z   = 75
 
-BUFG_Z  = 74 # : 81 reserve just in case
+BUFG_Z  = 76 # : 81 reserve just in case
 BSRAM_Z = 100
 
 OSC_Z   = 274
@@ -438,19 +438,20 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
     for idx, name in {(IOLOGICA_Z, 'IOLOGICA'), (IOLOGICA_Z + 1, 'IOLOGICB')}:
         if name not in db.grid[y][x].bels:
             continue
-        iol = tt.create_bel(name, "IOLOGIC", z = idx)
-        for port, wire in db.grid[y][x].bels[name].portmap.items():
-            if port == 'FCLK': # XXX compatibility
-                wire = f'FCLK{name[-1]}'
-            if not tt.has_wire(wire):
-                if port in {'CLK', 'PCLK'}:
-                    tt.create_wire(wire, "TILE_CLK")
+        for off, io_type in {(0, 'O'), (2, 'I')}:
+            iol = tt.create_bel(f"{name}{io_type}", f"IOLOGIC{io_type}", z = idx + off)
+            for port, wire in db.grid[y][x].bels[name].portmap.items():
+                if port == 'FCLK': # XXX compatibility
+                    wire = f'FCLK{name[-1]}'
+                if not tt.has_wire(wire):
+                    if port in {'CLK', 'PCLK'}:
+                        tt.create_wire(wire, "TILE_CLK")
+                    else:
+                        tt.create_wire(wire, "IOL_PORT")
+                if port in {'Q', 'Q0', 'Q1', 'Q2', 'Q3', 'Q4', 'Q5', 'Q6', 'Q7', 'Q8', 'Q9', 'DF', 'LAG', 'LEAD'}:
+                    tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
                 else:
-                    tt.create_wire(wire, "IOL_PORT")
-            if port in {'Q', 'Q0', 'Q1', 'Q2', 'Q3', 'Q4', 'Q5', 'Q6', 'Q7', 'Q8', 'Q9', 'DF', 'LAG', 'LEAD'}:
-                tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
-            else:
-                tt.add_bel_pin(iol, port, wire, PinType.INPUT)
+                    tt.add_bel_pin(iol, port, wire, PinType.INPUT)
     tdesc.tiletype = tiletype
     return tt
 
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index e19c64c884..4aec5e5045 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -52,14 +52,15 @@ bool GowinUtils::is_simple_io_bel(BelId bel)
 
 Loc GowinUtils::get_pair_iologic_bel(Loc loc)
 {
-    loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
+    int const z[] = {1, 0, 3, 2};
+    loc.z = BelZ::IOLOGICA_Z + z[(loc.z - BelZ::IOLOGICA_Z)];
     return loc;
 }
 
 BelId GowinUtils::get_io_bel_from_iologic(BelId bel)
 {
     Loc loc = ctx->getBelLocation(bel);
-    loc.z = BelZ::IOBA_Z + loc.z - BelZ::IOLOGICA_Z;
+    loc.z = BelZ::IOBA_Z + ((loc.z - BelZ::IOLOGICA_Z) & 1);
     return ctx->getBelByLocation(loc);
 }
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 1045c76c11..8133e46a4d 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -347,7 +347,7 @@ struct GowinPacker
         }
     }
 
-    BelId get_iologic_bel(CellInfo *iob)
+    BelId get_iologico_bel(CellInfo *iob)
     {
         NPNR_ASSERT(iob->bel != BelId());
         Loc loc = ctx->getBelLocation(iob->bel);
@@ -355,6 +355,14 @@ struct GowinPacker
         return ctx->getBelByLocation(loc);
     }
 
+    BelId get_iologici_bel(CellInfo *iob)
+    {
+        NPNR_ASSERT(iob->bel != BelId());
+        Loc loc = ctx->getBelLocation(iob->bel);
+        loc.z = loc.z - BelZ::IOBA_Z + BelZ::IOLOGICA_Z + 2;
+        return ctx->getBelByLocation(loc);
+    }
+
     void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
     {
         if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4) || diff) {
@@ -367,6 +375,26 @@ struct GowinPacker
         }
     }
 
+    // While we require an exact match of the type, in the future the criteria
+    // may be relaxed and there will be a comparison of the control networks
+    // used.
+    bool are_iologic_compatible(CellInfo *ci_0, CellInfo *ci_1)
+    {
+        switch (ci_0->type.hash()) {
+        case ID_ODDR:
+            return ci_1->type == id_IDDR;
+        case ID_ODDRC:
+            return ci_1->type == id_IDDRC;
+        case ID_IDDR:
+            return ci_1->type == id_ODDR;
+        case ID_IDDRC:
+            return ci_1->type == id_ODDRC;
+        default:
+            return false;
+        }
+        return false;
+    }
+
     void pack_bi_output_iol(CellInfo &ci, std::vector<IdString> &nets_to_remove)
     {
         // These primitives have an additional pin to control the tri-state iob - Q1.
@@ -377,7 +405,16 @@ struct GowinPacker
         NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
         BelId iob_bel = out_iob->bel;
 
-        BelId l_bel = get_iologic_bel(out_iob);
+        BelId l_bel = get_iologico_bel(out_iob);
+        // check compatible Input and Output iologic if any
+        BelId in_l_bel = get_iologici_bel(out_iob);
+        if (in_l_bel != BelId() && !ctx->checkBelAvail(in_l_bel)) {
+            CellInfo *in_iologic_ci = ctx->getBoundBelCell(in_l_bel);
+            if (!are_iologic_compatible(&ci, in_iologic_ci)) {
+                log_error("IOLOGIC %s at %s cannot coexist with %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel),
+                          ctx->nameOf(in_iologic_ci));
+            }
+        }
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
@@ -434,7 +471,7 @@ struct GowinPacker
         NPNR_ASSERT(out_iob != nullptr && out_iob->bel != BelId());
         BelId iob_bel = out_iob->bel;
 
-        BelId l_bel = get_iologic_bel(out_iob);
+        BelId l_bel = get_iologico_bel(out_iob);
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
@@ -554,7 +591,7 @@ struct GowinPacker
         NPNR_ASSERT(in_iob != nullptr && in_iob->bel != BelId());
         BelId iob_bel = in_iob->bel;
 
-        BelId l_bel = get_iologic_bel(in_iob);
+        BelId l_bel = get_iologici_bel(in_iob);
         if (l_bel == BelId()) {
             log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
         }
@@ -605,7 +642,7 @@ struct GowinPacker
 
         for (auto &cell : ctx->cells) {
             CellInfo &ci = *cell.second;
-            if (!is_iologic(&ci)) {
+            if (!(is_iologici(&ci) || is_iologico(&ci))) {
                 continue;
             }
             if (ctx->debug) {
@@ -704,7 +741,7 @@ struct GowinPacker
         aux->setParam(ctx->id("UPDATE"), Property("SAME"));
 
         // make cell in the next location
-        ctx->createCell(main_name, id_IOLOGIC);
+        ctx->createCell(main_name, id_IOLOGICO);
         aux = ctx->cells.at(main_name).get();
 
         aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
@@ -777,7 +814,7 @@ struct GowinPacker
         ci.copyPortTo(id_CALIB, aux, id_CALIB);
 
         // make cell in the next location
-        ctx->createCell(main_name, id_IOLOGIC);
+        ctx->createCell(main_name, id_IOLOGICI);
         aux = ctx->cells.at(main_name).get();
 
         aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));

From ff96fc5af1d220b5e84a4ddfb3d8634a4d8d56ef Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 10 Feb 2024 14:16:52 +1000
Subject: [PATCH 584/712] gowin: Himbaechel. Fix IDES16/OSER16

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc | 1 +
 himbaechel/uarch/gowin/gowin.cc     | 2 +-
 himbaechel/uarch/gowin/pack.cc      | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 7b888ee88d..db7ae20b23 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -797,6 +797,7 @@ X(IDES8)
 X(IDES10)
 X(IVIDEO)
 X(IDES16)
+X(IOLOGIC)
 X(IOLOGICI)
 X(IOLOGICO)
 X(IOLOGICA)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 0b80fd5007..97940def27 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -200,7 +200,7 @@ void GowinImpl::postRoute()
 
     for (auto &cell : ctx->cells) {
         auto ci = cell.second.get();
-        if (ci->type.in(id_IOLOGICI, id_IOLOGICO) ||
+        if (ci->type.in(id_IOLOGICI, id_IOLOGICO, id_IOLOGIC) ||
             ((is_iologici(ci) || is_iologico(ci)) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
             if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
                 // mark FCLK<-HCLK connections
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 8133e46a4d..3560488289 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -741,7 +741,7 @@ struct GowinPacker
         aux->setParam(ctx->id("UPDATE"), Property("SAME"));
 
         // make cell in the next location
-        ctx->createCell(main_name, id_IOLOGICO);
+        ctx->createCell(main_name, id_IOLOGIC);
         aux = ctx->cells.at(main_name).get();
 
         aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));
@@ -814,7 +814,7 @@ struct GowinPacker
         ci.copyPortTo(id_CALIB, aux, id_CALIB);
 
         // make cell in the next location
-        ctx->createCell(main_name, id_IOLOGICI);
+        ctx->createCell(main_name, id_IOLOGIC);
         aux = ctx->cells.at(main_name).get();
 
         aux->setAttr(ctx->id("MAIN_CELL"), Property(main_name.str(ctx)));

From 210e0fa33b7502a1bb15dfcd3e5382aa2e4bcc0d Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 18 Mar 2024 22:08:52 +1000
Subject: [PATCH 585/712] gowin: Add support for DSP primitives.

For the following primitives:
  - PADD9
  - PADD18
  - MULT9X9
  - MULT18X18
  - MULT36X36
  - MULTALU18X18
  - MULTALU36X18
  - MULTADDALU18X18
  - ALU54D
packing and processing of fixed wires between macro and between DSP
blocks is implemented.
Clusters of DSP and macro blocks are processed using custom placement of
cluster elements.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  42 +
 himbaechel/uarch/gowin/globals.cc        |  13 +-
 himbaechel/uarch/gowin/gowin.cc          | 263 ++++++-
 himbaechel/uarch/gowin/gowin.h           |  57 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py | 291 ++++++-
 himbaechel/uarch/gowin/gowin_utils.cc    | 120 +++
 himbaechel/uarch/gowin/gowin_utils.h     |  24 +
 himbaechel/uarch/gowin/pack.cc           | 945 ++++++++++++++++++++++-
 8 files changed, 1725 insertions(+), 30 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index db7ae20b23..b356872075 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -917,6 +917,48 @@ X(WREB)
 X(CLKA)
 X(CLKB)
 
+// DSP
+X(ALU54D)
+X(MULTADDALU18X18)
+X(MULTALU18X18)
+X(MULTALU36X18)
+X(MULT36X36)
+X(MULT18X18)
+X(MULT9X9)
+X(PADD18)
+X(PADD9)
+X(ASIGN)
+X(BSIGN)
+X(ASIGN0)
+X(BSIGN0)
+X(ASIGN1)
+X(BSIGN1)
+X(ASEL)
+X(ASEL0)
+X(ASEL1)
+X(BSEL)
+X(BSEL0)
+X(BSEL1)
+X(SOA_REG)
+X(DSIGN)
+X(ACCLOAD)
+X(ACCLOAD0)
+X(ACCLOAD1)
+X(NET_ACCLOAD)
+X(ALUSEL0)
+X(ALUSEL1)
+X(ALUSEL2)
+X(ALUSEL3)
+X(ALUSEL4)
+X(ALUSEL5)
+X(ALUSEL6)
+X(USE_CASCADE_OUT)
+X(USE_CASCADE_IN)
+X(LAST_IN_CHAIN)
+X(MULTALU18X18_MODE)
+X(MULTADDALU18X18_MODE)
+X(MULTALU36X18_MODE)
+
 // IOB types
 X(IBUF)
 X(OBUF)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 86c3c63c6b..2504f8ccef 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -215,6 +215,7 @@ struct GowinGlobalRouter
         }
         ctx->bindWire(src, net, STRENGTH_LOCKED);
 
+        RouteResult routed = NOT_ROUTED;
         for (auto usr : net->users.enumerate()) {
             WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
             if (dst == WireId()) {
@@ -222,8 +223,16 @@ struct GowinGlobalRouter
                           ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
             }
             // log_info(" usr wire: %s\n", ctx->nameOfWire(dst));
-            backwards_bfs_route(net, src, dst, 1000000, true,
-                                [&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
+            if (backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                    return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
+                })) {
+                routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
+            } else {
+                routed = routed == NOT_ROUTED ? routed : ROUTED_PARTIALLY;
+            }
+        }
+        if (routed == NOT_ROUTED) {
+            ctx->unbindWire(src);
         }
 
         // b) route net before buf from whatever to the buf input
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 97940def27..1fc3e5747d 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -32,6 +32,7 @@ struct GowinImpl : HimbaechelAPI
     void postRoute() override;
 
     bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
+    void notifyBelChange(BelId bel, CellInfo *cell) override;
 
     // Bel bucket functions
     IdString getBelBucketForCellType(IdString cell_type) const override;
@@ -41,6 +42,11 @@ struct GowinImpl : HimbaechelAPI
     // wires
     bool checkPipAvail(PipId pip) const override;
 
+    // Cluster
+    bool isClusterStrict(const CellInfo *cell) const { return true; }
+    bool getClusterPlacement(ClusterId cluster, BelId root_bel,
+                             std::vector<std::pair<CellInfo *, BelId>> &placement) const;
+
   private:
     HimbaechelHelpers h;
     GowinUtils gwu;
@@ -53,15 +59,37 @@ struct GowinImpl : HimbaechelAPI
     // Validity checking
     struct GowinCellInfo
     {
+        // slice info
         const NetInfo *lut_f = nullptr;
         const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
         const NetInfo *alu_sum = nullptr;
+        // dsp info
+        const NetInfo *dsp_asign = nullptr, *dsp_bsign = nullptr, *dsp_asel = nullptr, *dsp_bsel = nullptr,
+                      *dsp_ce = nullptr, *dsp_clk = nullptr, *dsp_reset = nullptr;
+        bool dsp_soa_reg;
     };
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
 
+    // dsp control nets
+    // Each DSP and each macro has a small set of control wires that are
+    // allocated to internal primitives as needed. It is assumed that most
+    // primitives use the same signals for CE, CLK and especially RESET, so
+    // these wires are few and need to be controlled.
+    struct dsp_net_counters
+    {
+        dict<IdString, int> ce;
+        dict<IdString, int> clk;
+        dict<IdString, int> reset;
+    };
+    dict<BelId, dsp_net_counters> dsp_net_cnt;
+    dict<BelId, CellInfo *> dsp_bel2cell; // Remember the connection with cells
+                                          // since this information is already lost during unbinding
+    void adjust_dsp_pin_mapping(void);
+
     // bel placement validation
     bool slice_valid(int x, int y, int z) const;
+    bool dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const;
 };
 
 struct GowinArch : HimbaechelArch
@@ -175,6 +203,59 @@ void GowinImpl::pack()
     gowin_pack(ctx);
 }
 
+// One DSP macro, in a rough approximation, consists of 5 large operating
+// blocks (pre-adders, multipliers and alu), at almost every input (blocks
+// usually have two of them) you can turn on registers, in addition, there are
+// registers on a dedicated operand shift line between DSP and registers at
+// the outputs. As we see, the number of registers is large, but the DSP has
+// only four inputs for each of the CE, CLK and RESET signals, and here we tell
+// gowin_pack which version of each signal is used by which block.
+// We also indicate to the router which Bel's pin to use.
+void GowinImpl::adjust_dsp_pin_mapping(void)
+{
+    for (auto b2c : dsp_bel2cell) {
+        BelId bel = b2c.first;
+        Loc loc = ctx->getBelLocation(bel);
+        CellInfo *ci = b2c.second;
+        const auto dsp_data = fast_cell_info.at(ci->flat_index);
+
+        auto set_cell_bel_pin = [&](dict<IdString, int> nets, IdString pin, IdString net_name, const char *fmt,
+                                    const char *fmt_double = nullptr) {
+            int i = 0;
+            for (auto net_cnt : nets) {
+                if (net_cnt.first == net_name) {
+                    break;
+                }
+                ++i;
+            }
+            ci->cell_bel_pins.at(pin).clear();
+            if (fmt_double == nullptr) {
+                ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt, i));
+            } else {
+                ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt_double, i, 0));
+                ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt_double, i, 1));
+            }
+            ci->setAttr(pin, i);
+        };
+
+        if (dsp_data.dsp_reset != nullptr) {
+            BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, BelZ::DSP_Z));
+            set_cell_bel_pin(dsp_net_cnt.at(dsp).reset, id_RESET, dsp_data.dsp_reset->name, "RESET%d",
+                             ci->type == id_MULT36X36 ? "RESET%d%d" : nullptr);
+        }
+        if (dsp_data.dsp_ce != nullptr) {
+            BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, gwu.get_dsp_macro(loc.z)));
+            set_cell_bel_pin(dsp_net_cnt.at(dsp).ce, id_CE, dsp_data.dsp_ce->name, "CE%d",
+                             ci->type == id_MULT36X36 ? "CE%d%d" : nullptr);
+        }
+        if (dsp_data.dsp_clk != nullptr) {
+            BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, gwu.get_dsp_macro(loc.z)));
+            set_cell_bel_pin(dsp_net_cnt.at(dsp).clk, id_CLK, dsp_data.dsp_clk->name, "CLK%d",
+                             ci->type == id_MULT36X36 ? "CLK%d%d" : nullptr);
+        }
+    }
+}
+
 void GowinImpl::prePlace() { assign_cell_info(); }
 void GowinImpl::postPlace()
 {
@@ -190,6 +271,9 @@ void GowinImpl::postPlace()
         }
         log_break();
     }
+
+    // adjust cell pin to bel pin mapping for DSP cells (CE, CLK and RESET pins)
+    adjust_dsp_pin_mapping();
 }
 
 void GowinImpl::preRoute() { gowin_route_globals(ctx); }
@@ -238,10 +322,10 @@ void GowinImpl::postRoute()
 bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
 {
     Loc l = ctx->getBelLocation(bel);
+    IdString bel_type = ctx->getBelType(bel);
     if (!ctx->getBoundBelCell(bel)) {
         return true;
     }
-    IdString bel_type = ctx->getBelType(bel);
     switch (bel_type.hash()) {
     case ID_LUT4: /* fall-through */
     case ID_DFF:
@@ -251,6 +335,16 @@ bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
     case ID_RAM16SDP4:
         // only slices 4 and 5 are critical for RAM
         return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
+    case ID_PADD9:           /* fall-through */
+    case ID_PADD18:          /* fall-through */
+    case ID_MULT9X9:         /* fall-through */
+    case ID_MULT18X18:       /* fall-through */
+    case ID_MULTADDALU18X18: /* fall-through */
+    case ID_MULTALU18X18:    /* fall-through */
+    case ID_MULTALU36X18:    /* fall-through */
+    case ID_MULT36X36:       /* fall-through */
+    case ID_ALU54D:
+        return dsp_valid(l, bel_type, explain_invalid);
     }
     return true;
 }
@@ -290,6 +384,10 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
 
 bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
 {
+    if (cell_type == id_DUMMY_CELL) {
+        return true;
+    }
+
     IdString bel_type = ctx->getBelType(bel);
     if (bel_type == id_IOB) {
         return cell_type.in(id_IBUF, id_OBUF);
@@ -347,6 +445,23 @@ void GowinImpl::assign_cell_info()
             fc.alu_sum = ci->getPort(id_SUM);
             continue;
         }
+        auto get_net = [&](IdString port_id) {
+            NetInfo *ni = ci->getPort(port_id);
+            if (ni != nullptr && ni->driver.cell == nullptr) {
+                ni = nullptr;
+            }
+            return ni;
+        };
+        if (is_dsp(ci)) {
+            fc.dsp_reset = get_net(id_RESET);
+            fc.dsp_clk = get_net(id_CLK);
+            fc.dsp_ce = get_net(id_CE);
+            fc.dsp_asign = get_net(id_ASIGN);
+            fc.dsp_bsign = get_net(id_BSIGN);
+            fc.dsp_asel = get_net(id_ASEL);
+            fc.dsp_bsel = get_net(id_BSEL);
+            fc.dsp_soa_reg = ci->params.count(id_SOA_REG) && ci->params.at(id_SOA_REG).as_int64() == 1;
+        }
     }
 }
 
@@ -367,6 +482,59 @@ inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
 }
 
 // placement validation
+bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
+{
+    const CellInfo *dsp = ctx->getBoundBelCell(ctx->getBelByLocation(l));
+    const auto &dsp_data = fast_cell_info.at(dsp->flat_index);
+    // check for shift out register - there is only one for macro
+    if (dsp_data.dsp_soa_reg) {
+        if (l.z == BelZ::MULT18X18_0_1_Z || l.z == BelZ::MULT18X18_1_1_Z || l.z == BelZ::MULT9X9_0_0_Z ||
+            l.z == BelZ::MULT9X9_0_1_Z || l.z == BelZ::MULT9X9_1_0_Z || l.z == BelZ::MULT9X9_1_1_Z) {
+            if (explain_invalid) {
+                log_nonfatal_error(
+                        "It is not possible to place the DSP so that the SOA register is on the macro boundary.\n");
+            }
+            return false;
+        }
+    }
+
+    if (bel_type.in(id_MULT9X9, id_PADD9)) {
+        int pair_z = gwu.get_dsp_paired_9(l.z);
+        const CellInfo *adj_dsp9 = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(l.x, l.y, pair_z)));
+        if (adj_dsp9 != nullptr) {
+            const auto &adj_dsp9_data = fast_cell_info.at(adj_dsp9->flat_index);
+            if ((dsp_data.dsp_asign != adj_dsp9_data.dsp_asign) || (dsp_data.dsp_bsign != adj_dsp9_data.dsp_bsign) ||
+                (dsp_data.dsp_asel != adj_dsp9_data.dsp_asel) || (dsp_data.dsp_bsel != adj_dsp9_data.dsp_bsel) ||
+                (dsp_data.dsp_reset != adj_dsp9_data.dsp_reset) || (dsp_data.dsp_ce != adj_dsp9_data.dsp_ce) ||
+                (dsp_data.dsp_clk != adj_dsp9_data.dsp_clk)) {
+                if (explain_invalid) {
+                    log_nonfatal_error("For 9bit primitives the control signals must be same.\n");
+                }
+                return false;
+            }
+        }
+    }
+    // check for control nets "overflow"
+    BelId dsp_bel = ctx->getBelByLocation(Loc(l.x, l.y, BelZ::DSP_Z));
+    if (dsp_net_cnt.at(dsp_bel).reset.size() > 4) {
+        if (explain_invalid) {
+            log_nonfatal_error("More than 4 different networks for RESET signals in one DSP are not allowed.\n");
+        }
+        return false;
+    }
+    BelId dsp_macro_bel = ctx->getBelByLocation(Loc(l.x, l.y, gwu.get_dsp_macro(l.z)));
+    if (dsp_net_cnt.count(dsp_macro_bel)) {
+        if (dsp_net_cnt.at(dsp_macro_bel).ce.size() > 4 || dsp_net_cnt.at(dsp_macro_bel).clk.size() > 4) {
+            if (explain_invalid) {
+                log_nonfatal_error(
+                        "More than 4 different networks for CE or CLK signals in one DSP macro are not allowed.\n");
+            }
+            return false;
+        }
+    }
+    return true;
+}
+
 bool GowinImpl::slice_valid(int x, int y, int z) const
 {
     const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
@@ -433,6 +601,99 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     return true;
 }
 
+// Cluster
+bool GowinImpl::getClusterPlacement(ClusterId cluster, BelId root_bel,
+                                    std::vector<std::pair<CellInfo *, BelId>> &placement) const
+{
+    CellInfo *root_ci = getClusterRootCell(cluster);
+    if (!root_ci->type.in(id_PADD9, id_MULT9X9, id_PADD18, id_MULT18X18, id_MULTALU18X18, id_MULTALU36X18,
+                          id_MULTADDALU18X18, id_ALU54D)) {
+        return HimbaechelAPI::getClusterPlacement(cluster, root_bel, placement);
+    }
+
+    NPNR_ASSERT(root_bel != BelId());
+    if (!isValidBelForCellType(root_ci->type, root_bel)) {
+        return false;
+    }
+
+    IdString bel_type = ctx->getBelType(root_bel);
+    // non-chain DSP
+    if (root_ci->constr_children.size() == 1 && bel_type.in(id_PADD9, id_MULT9X9)) {
+        return HimbaechelAPI::getClusterPlacement(cluster, root_bel, placement);
+    }
+
+    placement.clear();
+    Loc root_loc = ctx->getBelLocation(root_bel);
+    placement.emplace_back(root_ci, root_bel);
+
+    Loc mult_loc = root_loc;
+    for (auto child : root_ci->constr_children) {
+        Loc child_loc;
+        child_loc.y = root_loc.y;
+        if (child->type == id_DUMMY_CELL) {
+            child_loc.x = mult_loc.x + child->constr_x;
+            child_loc.z = mult_loc.z + child->constr_z;
+        } else {
+            child_loc = gwu.get_dsp_next_in_chain(mult_loc, child->type);
+            mult_loc = child_loc;
+        }
+
+        BelId child_bel = ctx->getBelByLocation(child_loc);
+        if (child_bel == BelId() || !isValidBelForCellType(child->type, child_bel))
+            return false;
+        placement.emplace_back(child, child_bel);
+    }
+    return true;
+}
+
+void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
+{
+    if (cell != nullptr && !is_dsp(cell)) {
+        return;
+    }
+    if (cell == nullptr && dsp_bel2cell.count(bel) == 0) {
+        return;
+    }
+
+    // trace DSP control networks
+    IdString cell_type = id_DUMMY_CELL;
+    if (cell != nullptr) {
+        cell_type = cell->type;
+    }
+    Loc loc = ctx->getBelLocation(bel);
+    Loc l = loc;
+    l.z = gwu.get_dsp(loc.z);
+    BelId dsp = ctx->getBelByLocation(l);
+    l.z = gwu.get_dsp_macro(loc.z);
+    BelId dsp_macro = ctx->getBelByLocation(l);
+
+    if (cell) {
+        const auto &dsp_cell_data = fast_cell_info.at(cell->flat_index);
+        if (dsp_cell_data.dsp_reset != nullptr) {
+            dsp_net_cnt[dsp].reset[dsp_cell_data.dsp_reset->name]++;
+        }
+        if (dsp_cell_data.dsp_ce != nullptr) {
+            dsp_net_cnt[dsp_macro].ce[dsp_cell_data.dsp_ce->name]++;
+        }
+        if (dsp_cell_data.dsp_clk != nullptr) {
+            dsp_net_cnt[dsp_macro].clk[dsp_cell_data.dsp_clk->name]++;
+        }
+        dsp_bel2cell[bel] = cell;
+    } else {
+        const auto &dsp_cell_data = fast_cell_info.at(dsp_bel2cell.at(bel)->flat_index);
+        if (dsp_cell_data.dsp_reset != nullptr) {
+            dsp_net_cnt.at(dsp).reset.at(dsp_cell_data.dsp_reset->name)--;
+        }
+        if (dsp_cell_data.dsp_ce != nullptr) {
+            dsp_net_cnt.at(dsp_macro).ce.at(dsp_cell_data.dsp_ce->name)--;
+        }
+        if (dsp_cell_data.dsp_clk != nullptr) {
+            dsp_net_cnt.at(dsp_macro).clk.at(dsp_cell_data.dsp_clk->name)--;
+        }
+        dsp_bel2cell.erase(bel);
+    }
+}
+
 } // namespace
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 715f54e682..aa3dcd083e 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -54,6 +54,14 @@ inline bool type_is_bsram(IdString cell_type)
 }
 inline bool is_bsram(const CellInfo *cell) { return type_is_bsram(cell->type); }
 
+// Return true if a cell is a DSP
+inline bool type_is_dsp(IdString cell_type)
+{
+    return cell_type.in(id_PADD9, id_PADD18, id_MULT9X9, id_MULT18X18, id_MULT36X36, id_ALU54D, id_MULTALU18X18,
+                        id_MULTALU36X18, id_MULTADDALU18X18);
+}
+inline bool is_dsp(const CellInfo *cell) { return type_is_dsp(cell->type); }
+
 // ==========================================
 // extra data in the chip db
 // ==========================================
@@ -113,7 +121,54 @@ enum
     PLL_Z = 275,
     GSR_Z = 276,
     VCC_Z = 277,
-    VSS_Z = 278
+    VSS_Z = 278,
+
+    // The two least significant bits encode Z for 9-bit adders and
+    // multipliers, if they are equal to 0, then we get Z of their common
+    // 18-bit equivalent.
+    DSP_Z = 509, // DSP
+
+    DSP_0_Z = 511, // DSP macro 0
+    PADD18_0_0_Z = 512,
+    PADD9_0_0_Z = 512 + 1,
+    PADD9_0_1_Z = 512 + 2,
+    PADD18_0_1_Z = 516,
+    PADD9_0_2_Z = 516 + 1,
+    PADD9_0_3_Z = 516 + 2,
+
+    MULT18X18_0_0_Z = 520,
+    MULT9X9_0_0_Z = 520 + 1,
+    MULT9X9_0_1_Z = 520 + 2,
+    MULT18X18_0_1_Z = 524,
+    MULT9X9_0_2_Z = 524 + 1,
+    MULT9X9_0_3_Z = 524 + 2,
+
+    ALU54D_0_Z = 524 + 3,
+    MULTALU18X18_0_Z = 528,
+    MULTALU36X18_0_Z = 528 + 1,
+    MULTADDALU18X18_0_Z = 528 + 2,
+
+    MULT36X36_Z = 528 + 3,
+
+    DSP_1_Z = 543, // DSP macro 1
+    PADD18_1_0_Z = 544,
+    PADD9_1_0_Z = 544 + 1,
+    PADD9_1_1_Z = 544 + 2,
+    PADD18_1_1_Z = 548,
+    PADD9_1_2_Z = 548 + 1,
+    PADD9_1_3_Z = 548 + 2,
+
+    MULT18X18_1_0_Z = 552,
+    MULT9X9_1_0_Z = 552 + 1,
+    MULT9X9_1_1_Z = 552 + 2,
+    MULT18X18_1_1_Z = 556,
+    MULT9X9_1_2_Z = 556 + 1,
+    MULT9X9_1_3_Z = 556 + 2,
+
+    ALU54D_1_Z = 556 + 3,
+    MULTALU18X18_1_Z = 560,
+    MULTALU36X18_1_Z = 560 + 1,
+    MULTADDALU18X18_1_Z = 560 + 2
 };
 }
 
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 2f96ee550e..3ba94c525a 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -44,6 +44,50 @@
 VCC_Z   = 277
 GND_Z   = 278
 
+DSP_Z          = 509
+
+DSP_0_Z        = 511 # DSP macro 0
+PADD18_0_0_Z   = 512
+PADD9_0_0_Z    = 512 + 1
+PADD9_0_1_Z    = 512 + 2
+PADD18_0_1_Z   = 516
+PADD9_0_2_Z    = 516 + 1
+PADD9_0_3_Z    = 516 + 2
+
+MULT18X18_0_0_Z  = 520
+MULT9X9_0_0_Z    = 520 + 1
+MULT9X9_0_1_Z    = 520 + 2
+MULT18X18_0_1_Z  = 524
+MULT9X9_0_2_Z    = 524 + 1
+MULT9X9_0_3_Z    = 524 + 2
+
+ALU54D_0_Z       = 524 + 3
+MULTALU18X18_0_Z = 528
+MULTALU36X18_0_Z = 528 + 1
+MULTADDALU18X18_0_Z = 528 + 2
+
+MULT36X36_Z    = 528 + 3
+
+DSP_1_Z        = 543 # DSP macro 1
+PADD18_1_0_Z   = 544
+PADD9_1_0_Z    = 544 + 1
+PADD9_1_1_Z    = 544 + 2
+PADD18_1_1_Z   = 548
+PADD9_1_2_Z    = 548 + 1
+PADD9_1_3_Z    = 548 + 2
+
+MULT18X18_1_0_Z  = 552
+MULT9X9_1_0_Z    = 552 + 1
+MULT9X9_1_1_Z    = 552 + 2
+MULT18X18_1_1_Z  = 556
+MULT9X9_1_2_Z    = 556 + 1
+MULT9X9_1_3_Z    = 556 + 2
+
+ALU54D_1_Z       = 556 + 3
+MULTALU18X18_1_Z = 560
+MULTALU36X18_1_Z = 560 + 1
+MULTADDALU18X18_1_Z = 560 + 2
+
 # =======================================
 # Chipdb additional info
 # =======================================
@@ -363,6 +407,15 @@ def find_or_make_dup():
     create_switch_matrix(tt, db, x, y)
     chip.set_tile_type(x, y, tdesc.tiletype)
 
+def add_port_wire(tt, bel, portmap, name, wire_type, port_type):
+    wire = portmap[name]
+    if not tt.has_wire(wire):
+        if name.startswith('CLK'):
+            tt.create_wire(wire, "TILE_CLK")
+        else:
+            tt.create_wire(wire, wire_type)
+    tt.add_bel_pin(bel, name, wire, port_type)
+
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "NULL"
     tiletype = f"{typename}_{ttyp}"
@@ -586,29 +639,234 @@ def create_bsram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
     portmap = db.grid[y][x].bels['BSRAM'].portmap
     bsram = tt.create_bel("BSRAM", "BSRAM", z = BSRAM_Z)
 
-    def add_port_wire(tt, bel, name, wire_type = "BSRAM_I", port_type = PinType.INPUT):
-        wire = portmap[name]
-        if not tt.has_wire(wire):
-            if name.startswith('CLK'):
-                tt.create_wire(wire, "TILE_CLK")
-            else:
-                tt.create_wire(wire, wire_type)
-        tt.add_bel_pin(bel, name, wire, port_type)
 
     for sfx in {'', 'A', 'B'}:
         for inp in _bsram_inputs:
-            add_port_wire(tt, bsram, f"{inp}{sfx}")
+            add_port_wire(tt, bsram, portmap, f"{inp}{sfx}", "BSRAM_I", PinType.INPUT)
         for idx in range(3):
-            add_port_wire(tt, bsram, f"BLKSEL{sfx}{idx}")
+            add_port_wire(tt, bsram, portmap, f"BLKSEL{sfx}{idx}", "BSRAM_I", PinType.INPUT)
         for idx in range(14):
-            add_port_wire(tt, bsram, f"AD{sfx}{idx}")
+            add_port_wire(tt, bsram, portmap, f"AD{sfx}{idx}", "BSRAM_I", PinType.INPUT)
         for idx in range(18):
-            add_port_wire(tt, bsram, f"DI{sfx}{idx}")
-            add_port_wire(tt, bsram, f"DO{sfx}{idx}", "BSRAM_O", PinType.OUTPUT)
+            add_port_wire(tt, bsram, portmap, f"DI{sfx}{idx}", "BSRAM_I", PinType.INPUT)
+            add_port_wire(tt, bsram, portmap, f"DO{sfx}{idx}", "BSRAM_O", PinType.OUTPUT)
         if not sfx:
             for idx in range(18, 36):
-                add_port_wire(tt, bsram, f"DI{idx}")
-                add_port_wire(tt, bsram, f"DO{idx}", "BSRAM_O", PinType.OUTPUT)
+                add_port_wire(tt, bsram, portmap, f"DI{idx}", "BSRAM_I", PinType.INPUT)
+                add_port_wire(tt, bsram, portmap, f"DO{idx}", "BSRAM_O", PinType.OUTPUT)
+
+    tdesc.tiletype = tiletype
+    return tt
+
+# DSP
+_mult_inputs = {'ASEL', 'BSEL', 'ASIGN', 'BSIGN'}
+def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
+    typename = "DSP"
+    tiletype = f"{typename}_{ttyp}"
+    if tdesc.sfx != 0:
+        tiletype += f"_{tdesc.sfx}"
+    tt = chip.create_tile_type(tiletype)
+    tt.extra_data = TileExtraData(chip.strs.id(typename))
+
+    # create big DSP
+    belname = f'DSP'
+    portmap = db.grid[y][x].bels[belname].portmap
+    dsp = tt.create_bel(belname, "DSP", DSP_Z)
+    dsp.flags = BEL_FLAG_HIDDEN
+
+    # create DSP macros
+    for idx in range(2):
+        belname = f'DSP{idx}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "DSP", eval(f'DSP_{idx}_Z'))
+        dsp.flags = BEL_FLAG_HIDDEN
+
+    # create pre-adders
+    for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
+        belname = f'PADD9{mac}{idx}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "PADD9", eval(f'PADD9_{mac}_{idx}_Z'))
+
+        add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
+        for sfx in {'A', 'B'}:
+            for inp in range(9):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(9):
+            add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        add_port_wire(tt, dsp, portmap, "ASEL", "DSP_I", PinType.INPUT)
+        for outp in range(9):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
+        belname = f'PADD18{mac}{idx}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "PADD18", eval(f'PADD18_{mac}_{idx}_Z'))
+
+        add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
+        for sfx in {'A', 'B'}:
+            for inp in range(18):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(18):
+            add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        add_port_wire(tt, dsp, portmap, "ASEL", "DSP_I", PinType.INPUT)
+        for outp in range(18):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # create multipliers
+    # mult 9x9
+    for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
+        belname = f'MULT9X9{mac}{idx}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "MULT9X9", eval(f'MULT9X9_{mac}_{idx}_Z'))
+
+        for sfx in {'A', 'B'}:
+            for inp in range(9):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        for inp in _mult_inputs:
+            add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(18):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # mult 18x18
+    for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
+        belname = f'MULT18X18{mac}{idx}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "MULT18X18", eval(f'MULT18X18_{mac}_{idx}_Z'))
+
+        for sfx in {'A', 'B'}:
+            for inp in range(18):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        for inp in _mult_inputs:
+            add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(36):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # mult 36x36
+    belname = 'MULT36X36'
+    portmap = db.grid[y][x].bels[belname].portmap
+    dsp = tt.create_bel(belname, "MULT36X36", MULT36X36_Z)
+
+    for i in range(2):
+        for sfx in {'A', 'B'}:
+            for inp in range(36):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}{i}", "DSP_I", PinType.INPUT)
+        for inp in {'ASIGN', 'BSIGN'}:
+            add_port_wire(tt, dsp, portmap, f"{inp}{i}", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}{i}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}{i}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}{i}", "DSP_I", PinType.INPUT)
+    for outp in range(72):
+        add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # create alus
+    for mac in range(2):
+        belname = f'ALU54D{mac}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "ALU54D", eval(f'ALU54D_{mac}_Z'))
+
+        for sfx in {'A', 'B'}:
+            for inp in range(54):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        for inp in {'ASIGN', 'BSIGN'}:
+            add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+            if inp < 2:
+                add_port_wire(tt, dsp, portmap, f"ACCLOAD{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(54):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # create multalus
+    # MULTALU18X18
+    for mac in range(2):
+        belname = f'MULTALU18X18{mac}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "MULTALU18X18", eval(f'MULTALU18X18_{mac}_Z'))
+
+        for i in range(2):
+            for sfx in {'ASIGN', 'BSIGN'}:
+                add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
+            for sfx in {'A', 'B'}:
+                for inp in range(18):
+                    add_port_wire(tt, dsp, portmap, f"{sfx}{inp}{i}", "DSP_I", PinType.INPUT)
+        for sfx in {'C', 'D'}:
+            for inp in range(54):
+                add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
+        add_port_wire(tt, dsp, portmap, "DSIGN", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+            if inp < 2:
+                add_port_wire(tt, dsp, portmap, f"ACCLOAD{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(54):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # MULTALU36X18
+    for mac in range(2):
+        belname = f'MULTALU36X18{mac}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "MULTALU36X18", eval(f'MULTALU36X18_{mac}_Z'))
+
+        for i in range(2):
+            for sfx in {'ASIGN', 'BSIGN'}:
+                add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
+            for inp in range(18):
+                add_port_wire(tt, dsp, portmap, f"A{inp}{i}", "DSP_I", PinType.INPUT)
+        for inp in range(7):
+            add_port_wire(tt, dsp, portmap, f"ALUSEL{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(36):
+            add_port_wire(tt, dsp, portmap, f"B{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(54):
+            add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(54):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
+
+    # MULTADDALU18X18
+    for mac in range(2):
+        belname = f'MULTADDALU18X18{mac}'
+        portmap = db.grid[y][x].bels[belname].portmap
+        dsp = tt.create_bel(belname, "MULTADDALU18X18", eval(f'MULTADDALU18X18_{mac}_Z'))
+
+        for i in range(2):
+            for sfx in {'ASIGN', 'BSIGN', 'ASEL', 'BSEL'}:
+                add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
+            for inp in range(18):
+                add_port_wire(tt, dsp, portmap, f"A{inp}{i}", "DSP_I", PinType.INPUT)
+                add_port_wire(tt, dsp, portmap, f"B{inp}{i}", "DSP_I", PinType.INPUT)
+        for inp in range(7):
+            add_port_wire(tt, dsp, portmap, f"ALUSEL{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(54):
+            add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
+        for inp in range(4):
+            add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
+            add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
+        for outp in range(54):
+            add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
 
     tdesc.tiletype = tiletype
     return tt
@@ -739,6 +997,7 @@ def main():
     ssram_tiletypes = db.tile_types['M']
     pll_tiletypes = db.tile_types['P']
     bsram_tiletypes = db.tile_types.get('B', set())
+    dsp_tiletypes = db.tile_types.get('D', set())
 
     # Setup tile grid
     for x in range(X):
@@ -758,6 +1017,8 @@ def main():
                 create_tiletype(create_pll_tiletype, ch, db, x, y, ttyp)
             elif ttyp in bsram_tiletypes:
                 create_tiletype(create_bsram_tiletype, ch, db, x, y, ttyp)
+            elif ttyp in dsp_tiletypes:
+                create_tiletype(create_dsp_tiletype, ch, db, x, y, ttyp)
             else:
                 create_tiletype(create_null_tiletype, ch, db, x, y, ttyp)
 
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 4aec5e5045..df255527a1 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -105,4 +105,124 @@ std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
     return std::make_unique<CellInfo>(ctx, name, type);
 }
 
+// DSP
+Loc GowinUtils::get_dsp_next_9_in_chain(Loc from) const
+{
+    Loc res;
+    res.y = from.y;
+    if (get_dsp_18_idx(from.z) == 0) {
+        res.x = from.x;
+        res.z = from.z + 4;
+        return res;
+    }
+    if (get_dsp_macro_num(from.z)) {
+        // next DSP
+        res.x = from.x + 9;
+        res.z = from.z & (~0x24);
+    } else {
+        // next macro
+        res.x = from.x;
+        res.z = get_dsp_next_macro(from.z) & (~4);
+    }
+    return res;
+}
+
+Loc GowinUtils::get_dsp_next_macro_in_chain(Loc from) const
+{
+    Loc res;
+    res.y = from.y;
+    if (get_dsp_macro_num(from.z)) {
+        // next DSP
+        res.x = from.x + 9;
+        res.z = from.z & (~0x20);
+    } else {
+        // next macro
+        res.x = from.x;
+        res.z = get_dsp_next_macro(from.z);
+    }
+    return res;
+}
+
+Loc GowinUtils::get_dsp_next_in_chain(Loc from, IdString dsp_type) const
+{
+    if (dsp_type.in(id_PADD9, id_PADD18, id_MULT9X9, id_MULT18X18)) {
+        return get_dsp_next_9_in_chain(from);
+    }
+    if (dsp_type.in(id_ALU54D, id_MULTALU18X18, id_MULTALU36X18, id_MULTADDALU18X18)) {
+        return get_dsp_next_macro_in_chain(from);
+    }
+    NPNR_ASSERT_FALSE("Unknown DSP cell type.");
+}
+
+CellInfo *GowinUtils::dsp_bus_src(const CellInfo *ci, const char *bus_prefix, int wire_num) const
+{
+    bool connected_to_const = false; // and disconnected too
+    CellInfo *connected_to_cell = nullptr;
+
+    for (int i = 0; i < wire_num; ++i) {
+        const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
+        if (connected_to_cell == nullptr) {
+            if (net == nullptr || net->driver.cell == nullptr || net->name == ctx->id("$PACKER_VCC") ||
+                net->name == ctx->id("$PACKER_GND")) {
+                connected_to_const = true;
+                continue;
+            } else {
+                if (connected_to_const) {
+                    log_error("The %s cell %s bus is connected simultaneously to constants and to another DSP.\n",
+                              ctx->nameOf(ci), bus_prefix);
+                }
+            }
+        }
+        if (net == nullptr || !is_dsp(net->driver.cell)) {
+            log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
+        }
+        if (connected_to_cell != nullptr && net->driver.cell != connected_to_cell) {
+            log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
+                      ctx->nameOf(connected_to_cell), ctx->nameOf(net->driver.cell));
+        }
+        connected_to_cell = net->driver.cell;
+    }
+    if (connected_to_const) {
+        return nullptr;
+    }
+    return connected_to_cell;
+}
+
+CellInfo *GowinUtils::dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, int wire_num) const
+{
+    bool disconnected = false; // and disconnected too
+    CellInfo *connected_to_cell = nullptr;
+
+    for (int i = 0; i < wire_num; ++i) {
+        const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
+        if (connected_to_cell == nullptr) {
+            if (net == nullptr || net->users.entries() == 0) {
+                disconnected = true;
+                continue;
+            } else {
+                if (disconnected) {
+                    log_error("The %s cell %s bus is partially disconnected.\n", ctx->nameOf(ci), bus_prefix);
+                }
+            }
+        }
+        if (net->users.entries() > 1) {
+            log_error("Net %s has >1 users.\n", ctx->nameOf(net));
+        }
+
+        CellInfo *dst = (*net->users.begin()).cell;
+        if (net == nullptr || !is_dsp(dst)) {
+            log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
+        }
+        if (connected_to_cell != nullptr && dst != connected_to_cell) {
+            log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
+                      ctx->nameOf(connected_to_cell), ctx->nameOf(dst));
+        }
+        connected_to_cell = dst;
+    }
+    if (disconnected) {
+        return nullptr;
+    }
+    return connected_to_cell;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index d93c602974..ea466b1124 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -31,6 +31,30 @@ struct GowinUtils
     Loc get_pair_iologic_bel(Loc loc);
     BelId get_io_bel_from_iologic(BelId bel);
 
+    // DSP
+    inline int get_dsp_18_z(int z) const { return z & (~3); }
+    inline int get_dsp_9_idx(int z) const { return z & 3; }
+    inline int get_dsp_18_idx(int z) const { return z & 4; }
+    inline int get_dsp_paired_9(int z) const { return (3 - get_dsp_9_idx(z)) | (z & (~3)); }
+    inline int get_dsp_mult_from_padd(int padd_z) const { return padd_z + 8; }
+    inline int get_dsp_padd_from_mult(int mult_z) const { return mult_z - 8; }
+    inline int get_dsp_next_macro(int z) const { return z + 32; }
+    inline int get_dsp(int z) const { return BelZ::DSP_Z; }
+    inline int get_dsp_macro(int z) const { return (z & 0x20) + BelZ::DSP_0_Z; }
+    inline int get_dsp_macro_num(int z) const { return (z & 0x20) >> 5; }
+    Loc get_dsp_next_9_in_chain(Loc from) const;
+    Loc get_dsp_next_macro_in_chain(Loc from) const;
+    Loc get_dsp_next_in_chain(Loc from, IdString dsp_type) const;
+
+    // check bus.
+    // This is necessary to find the head in the DSP chain - these buses are
+    // not switched in the hardware, but in software you can leave them
+    // unconnected or connect them to VCC or VSS, which is the same - as I
+    // already said, they are hard-wired and we are only discovering the fact
+    // that they are not connected to another DSP in the chain.
+    CellInfo *dsp_bus_src(const CellInfo *ci, const char *bus_prefix, int wire_num) const;
+    CellInfo *dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, int wire_num) const;
+
     bool is_diff_io_supported(IdString type);
     bool have_bottom_io_cnds(void);
     IdString get_bottom_io_wire_a_net(int8_t condition);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 3560488289..ad85fce17c 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -508,13 +508,13 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
-    IdString create_aux_iologic_name(IdString main_name, int idx = 0)
+    IdString create_aux_name(IdString main_name, int idx = 0)
     {
         std::string sfx("");
         if (idx) {
             sfx = std::to_string(idx);
         }
-        return ctx->id(main_name.str(ctx) + std::string("_aux") + sfx);
+        return ctx->id(main_name.str(ctx) + std::string("_aux$") + sfx);
     }
 
     BelId get_aux_iologic_bel(const CellInfo &ci)
@@ -529,7 +529,7 @@ struct GowinPacker
         if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
             return nullptr;
         }
-        IdString aux_name = create_aux_iologic_name(ci.name, idx);
+        IdString aux_name = create_aux_name(ci.name, idx);
         BelId bel = get_aux_iologic_bel(ci);
         BelId io_bel = gwu.get_io_bel_from_iologic(bel);
         if (!ctx->checkBelAvail(io_bel)) {
@@ -720,9 +720,9 @@ struct GowinPacker
 
         // to simplify packaging, the parts of the OSER16 are presented as IOLOGIC cells
         // and one of these aux cells is declared as main
-        IdString main_name = create_aux_iologic_name(ci.name);
+        IdString main_name = create_aux_name(ci.name);
 
-        IdString aux_name = create_aux_iologic_name(ci.name, 1);
+        IdString aux_name = create_aux_name(ci.name, 1);
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
         CellInfo *aux = ctx->cells.at(aux_name).get();
 
@@ -794,9 +794,9 @@ struct GowinPacker
 
         // to simplify packaging, the parts of the IDES16 are presented as IOLOGIC cells
         // and one of these aux cells is declared as main
-        IdString main_name = create_aux_iologic_name(ci.name);
+        IdString main_name = create_aux_name(ci.name);
 
-        IdString aux_name = create_aux_iologic_name(ci.name, 1);
+        IdString aux_name = create_aux_name(ci.name, 1);
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
         CellInfo *aux = ctx->cells.at(aux_name).get();
 
@@ -1646,12 +1646,932 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // DSP
+    // ===================================
+    void pass_net_type(CellInfo *ci, IdString port)
+    {
+        const NetInfo *net = ci->getPort(port);
+        std::string connected_net = "NET";
+        if (net != nullptr) {
+            if (net->name == ctx->id("$PACKER_VCC")) {
+                connected_net = "VCC";
+            } else if (net->name == ctx->id("$PACKER_GND")) {
+                connected_net = "GND";
+            }
+            ci->setAttr(ctx->idf("NET_%s", port.c_str(ctx)), connected_net);
+        } else {
+            ci->setAttr(ctx->idf("NET_%s", port.c_str(ctx)), std::string(""));
+        }
+    }
+
+    void pack_dsp(void)
+    {
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+        log_info("Pack DSP...\n");
+
+        std::vector<CellInfo *> dsp_heads;
+
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            if (is_dsp(ci)) {
+                if (ctx->verbose) {
+                    log_info(" pack %s %s\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+                }
+                switch (ci->type.hash()) {
+                case ID_PADD9: {
+                    pass_net_type(ci, id_ASEL);
+                    for (int i = 0; i < 9; ++i) {
+                        ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d", i));
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    for (int i = 0; i < 9; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // ADD_SUB wire
+                    IdString add_sub_net = ctx->id("$PACKER_GND");
+                    if (ci->params.count(ctx->id("ADD_SUB"))) {
+                        if (ci->params.at(ctx->id("ADD_SUB")).as_int64() == 1) {
+                            add_sub_net = ctx->id("$PACKER_VCC");
+                        }
+                    }
+                    ci->addInput(ctx->id("ADDSUB"));
+                    ci->connectPort(ctx->id("ADDSUB"), ctx->nets.at(add_sub_net).get());
+
+                    // PADD does not have outputs to the outside of the DSP -
+                    // it is always connected to the inputs of the multiplier;
+                    // to emulate a separate PADD primitive, we use
+                    // multiplication by input C, equal to 1. We can switch the
+                    // multiplier to multiplication mode by C in gowin_pack,
+                    // but we will have to generate the value 1 at input C
+                    // here.
+                    ci->addInput(ctx->id("C0"));
+                    ci->connectPort(ctx->id("C0"), ctx->nets.at(ctx->id("$PACKER_VCC")).get());
+                    for (int i = 1; i < 9; ++i) {
+                        ci->addInput(ctx->idf("C%d", i));
+                        ci->connectPort(ctx->idf("C%d", i), ctx->nets.at(ctx->id("$PACKER_GND")).get());
+                    }
+                    // mark mult9x9 as used by making cluster
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_y = 0;
+
+                    IdString mult_name = create_aux_name(ci->name);
+                    std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                    new_cells.push_back(std::move(mult_cell));
+                    CellInfo *mult_ci = new_cells.back().get();
+
+                    mult_ci->cluster = ci->name;
+                    mult_ci->constr_x = 0;
+                    mult_ci->constr_y = 0;
+                    mult_ci->constr_z = gwu.get_dsp_mult_from_padd(0);
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "SI", 9) == nullptr && gwu.dsp_bus_dst(ci, "SBO", 9) == nullptr) {
+                        for (int i = 0; i < 9; ++i) {
+                            ci->disconnectPort(ctx->idf("SI[%d]", i));
+                            ci->disconnectPort(ctx->idf("SBO[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_PADD18: {
+                    pass_net_type(ci, id_ASEL);
+                    for (int i = 0; i < 18; ++i) {
+                        ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d", i));
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    for (int i = 0; i < 18; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // ADD_SUB wire
+                    IdString add_sub_net = ctx->id("$PACKER_GND");
+                    if (ci->params.count(ctx->id("ADD_SUB"))) {
+                        if (ci->params.at(ctx->id("ADD_SUB")).as_int64() == 1) {
+                            add_sub_net = ctx->id("$PACKER_VCC");
+                        }
+                    }
+                    ci->addInput(ctx->id("ADDSUB"));
+                    ci->connectPort(ctx->id("ADDSUB"), ctx->nets.at(add_sub_net).get());
+
+                    // XXX form C as 1
+                    ci->addInput(ctx->id("C0"));
+                    ci->connectPort(ctx->id("C0"), ctx->nets.at(ctx->id("$PACKER_VCC")).get());
+                    for (int i = 1; i < 18; ++i) {
+                        ci->addInput(ctx->idf("C%d", i));
+                        ci->connectPort(ctx->idf("C%d", i), ctx->nets.at(ctx->id("$PACKER_GND")).get());
+                    }
+                    //
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 2; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::PADD18_0_0_Z + i;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::PADD18_0_0_Z + i;
+                    }
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "SI", 18) == nullptr && gwu.dsp_bus_dst(ci, "SBO", 18) == nullptr) {
+                        for (int i = 0; i < 18; ++i) {
+                            ci->disconnectPort(ctx->idf("SI[%d]", i));
+                            ci->disconnectPort(ctx->idf("SBO[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULT9X9: {
+                    pass_net_type(ci, id_ASEL);
+                    pass_net_type(ci, id_BSEL);
+                    for (int i = 0; i < 9; ++i) {
+                        ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d", i));
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    for (int i = 0; i < 18; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+                    // add padd9 as a child
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    IdString padd_name = create_aux_name(ci->name);
+                    std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                    new_cells.push_back(std::move(padd_cell));
+                    CellInfo *padd_ci = new_cells.back().get();
+
+                    padd_ci->cluster = ci->name;
+                    padd_ci->constr_abs_z = false;
+                    padd_ci->constr_x = 0;
+                    padd_ci->constr_y = 0;
+                    padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULT9X9_0_0_Z;
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "SIA", 9) == nullptr && gwu.dsp_bus_src(ci, "SIB", 9) == nullptr) {
+                        for (int i = 0; i < 9; ++i) {
+                            ci->disconnectPort(ctx->idf("SIA[%d]", i));
+                            ci->disconnectPort(ctx->idf("SIB[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULT18X18: {
+                    pass_net_type(ci, id_ASEL);
+                    pass_net_type(ci, id_BSEL);
+                    for (int i = 0; i < 18; ++i) {
+                        ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d", i));
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    for (int i = 0; i < 36; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 2; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULT18X18_0_0_Z + i;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::MULT18X18_0_0_Z + i;
+                    }
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "SIA", 18) == nullptr && gwu.dsp_bus_src(ci, "SIB", 18) == nullptr) {
+                        for (int i = 0; i < 18; ++i) {
+                            ci->disconnectPort(ctx->idf("SIA[%d]", i));
+                            ci->disconnectPort(ctx->idf("SIB[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_ALU54D: {
+                    pass_net_type(ci, id_ACCLOAD);
+                    for (int i = 0; i < 54; ++i) {
+                        ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d", i));
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    // ACCLOAD - It looks like these wires are always connected to each other.
+                    ci->cell_bel_pins.at(id_ACCLOAD).clear();
+                    ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ACCLOAD0);
+                    ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ACCLOAD1);
+
+                    for (int i = 0; i < 54; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 4; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::ALU54D_0_Z + 4 * (i / 2) + (i % 2);
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::ALU54D_0_Z + 4 * (i / 2) + (i % 2);
+                    }
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "CASI", 55) == nullptr) {
+                        for (int i = 0; i < 55; ++i) {
+                            ci->disconnectPort(ctx->idf("CASI[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULTALU18X18: {
+                    // Ports C and D conflict so we need to know the operating mode here.
+                    if (ci->params.count(id_MULTALU18X18_MODE) == 0) {
+                        ci->setParam(id_MULTALU18X18_MODE, 0);
+                    }
+                    int multalu18x18_mode = ci->params.at(id_MULTALU18X18_MODE).as_int64();
+                    NPNR_ASSERT_MSG(multalu18x18_mode >= 0 && multalu18x18_mode <= 2,
+                                    "MULTALU18X18_MODE is not in {0, 1, 2}");
+                    NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+
+                    for (int i = 0; i < 54; ++i) {
+                        if (i < 18) {
+                            if (multalu18x18_mode != 2) {
+                                ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d1", i));
+                                ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d1", i));
+                            } else {
+                                ci->renamePort(ctx->idf("A[%d]", i), ctx->idf("A%d0", i));
+                                ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d0", i));
+                            }
+                        }
+                        switch (multalu18x18_mode) {
+                        case 0:
+                            ci->renamePort(ctx->idf("C[%d]", i), ctx->idf("C%d", i));
+                            ci->disconnectPort(ctx->idf("D[%d]", i));
+                            break;
+                        case 1:
+                            ci->disconnectPort(ctx->idf("C[%d]", i));
+                            ci->disconnectPort(ctx->idf("D[%d]", i));
+                            break;
+                        case 2:
+                            ci->disconnectPort(ctx->idf("C[%d]", i));
+                            ci->renamePort(ctx->idf("D[%d]", i), ctx->idf("D%d", i));
+                            break;
+                        default:
+                            break;
+                        }
+                    }
+                    if (multalu18x18_mode != 2) {
+                        ci->renamePort(id_ASIGN, id_ASIGN1);
+                        ci->renamePort(id_BSIGN, id_BSIGN1);
+                        ci->addInput(id_ASIGN0);
+                        ci->addInput(id_BSIGN0);
+                        ci->connectPort(id_ASIGN0, vss_net);
+                        ci->connectPort(id_BSIGN0, vss_net);
+                        ci->disconnectPort(id_DSIGN);
+                    } else { // BSIGN0 and DSIGN are the same wire
+                        ci->renamePort(id_ASIGN, id_ASIGN0);
+                        ci->addInput(id_ASIGN1);
+                        ci->connectPort(id_ASIGN1, vss_net);
+                        ci->renamePort(id_BSIGN, id_BSIGN0);
+                    }
+
+                    // ACCLOAD - It looks like these wires are always connected to each other.
+                    pass_net_type(ci, id_ACCLOAD);
+                    ci->cell_bel_pins.at(id_ACCLOAD).clear();
+                    ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ACCLOAD0);
+                    ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ACCLOAD1);
+
+                    for (int i = 0; i < 54; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 2; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU18X18_0_Z + i;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::MULTALU18X18_0_Z + i;
+                    }
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "CASI", 55) == nullptr) {
+                        for (int i = 0; i < 55; ++i) {
+                            ci->disconnectPort(ctx->idf("CASI[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULTALU36X18: {
+                    if (ci->params.count(id_MULTALU18X18_MODE) == 0) {
+                        ci->setParam(id_MULTALU18X18_MODE, 0);
+                    }
+                    int multalu36x18_mode = ci->params.at(id_MULTALU36X18_MODE).as_int64();
+                    NPNR_ASSERT_MSG(multalu36x18_mode >= 0 && multalu36x18_mode <= 2,
+                                    "MULTALU36X18_MODE is not in {0, 1, 2}");
+                    NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+
+                    for (int i = 0; i < 36; ++i) {
+                        if (i < 18) {
+                            ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).clear();
+                            ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).push_back(ctx->idf("A%d0", i));
+                            ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).push_back(ctx->idf("A%d1", i));
+                        }
+                        ci->renamePort(ctx->idf("B[%d]", i), ctx->idf("B%d", i));
+                    }
+                    for (int i = 0; i < 54; ++i) {
+                        switch (multalu36x18_mode) {
+                        case 0:
+                            ci->renamePort(ctx->idf("C[%d]", i), ctx->idf("C%d", i));
+                            break;
+                        case 1: /* fallthrough */
+                        case 2:
+                            ci->disconnectPort(ctx->idf("C[%d]", i));
+                            break;
+                        default:
+                            break;
+                        }
+                    }
+
+                    // both A have sign bit
+                    // only MSB part of B has sign bit
+                    ci->cell_bel_pins.at(id_ASIGN).clear();
+                    ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN0);
+                    ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN1);
+                    ci->renamePort(id_BSIGN, id_BSIGN1);
+                    ci->addInput(id_BSIGN0);
+                    ci->connectPort(id_BSIGN0, vss_net);
+
+                    pass_net_type(ci, id_ACCLOAD);
+                    if (multalu36x18_mode == 1) {
+                        if (ci->attrs.at(id_NET_ACCLOAD).as_string() == "GND" ||
+                            ci->attrs.at(id_NET_ACCLOAD).as_string() == "VCC") {
+                            ci->disconnectPort(id_ACCLOAD);
+                        } else {
+                            ci->addInput(id_ALUSEL4);
+                            ci->addInput(id_ALUSEL6);
+                            ci->cell_bel_pins.at(id_ACCLOAD).clear();
+                            ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ALUSEL4);
+                            ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ALUSEL6);
+                        }
+                    } else {
+                        ci->disconnectPort(id_ACCLOAD);
+                    }
+
+                    for (int i = 0; i < 54; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 2; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU36X18_0_Z + i;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::MULTALU36X18_0_Z + i;
+                    }
+
+                    // DSP head?
+                    if (gwu.dsp_bus_src(ci, "CASI", 55) == nullptr) {
+                        for (int i = 0; i < 55; ++i) {
+                            ci->disconnectPort(ctx->idf("CASI[%d]", i));
+                        }
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULTADDALU18X18: {
+                    if (ci->params.count(id_MULTADDALU18X18_MODE) == 0) {
+                        ci->setParam(id_MULTADDALU18X18_MODE, 0);
+                    }
+                    int multaddalu18x18_mode = ci->params.at(id_MULTADDALU18X18_MODE).as_int64();
+                    NPNR_ASSERT_MSG(multaddalu18x18_mode >= 0 && multaddalu18x18_mode <= 2,
+                                    "MULTADDALU18X18_MODE is not in {0, 1, 2}");
+                    for (int i = 0; i < 54; ++i) {
+                        if (i < 18) {
+                            ci->renamePort(ctx->idf("A0[%d]", i), ctx->idf("A%d0", i));
+                            ci->renamePort(ctx->idf("B0[%d]", i), ctx->idf("B%d0", i));
+                            ci->renamePort(ctx->idf("A1[%d]", i), ctx->idf("A%d1", i));
+                            ci->renamePort(ctx->idf("B1[%d]", i), ctx->idf("B%d1", i));
+                        }
+                        if (multaddalu18x18_mode == 0) {
+                            ci->renamePort(ctx->idf("C[%d]", i), ctx->idf("C%d", i));
+                        } else {
+                            ci->disconnectPort(ctx->idf("C[%d]", i));
+                        }
+                    }
+                    for (int i = 0; i < 2; ++i) {
+                        ci->renamePort(ctx->idf("ASIGN[%d]", i), ctx->idf("ASIGN%d", i));
+                        ci->renamePort(ctx->idf("BSIGN[%d]", i), ctx->idf("BSIGN%d", i));
+                        ci->renamePort(ctx->idf("ASEL[%d]", i), ctx->idf("ASEL%d", i));
+                        ci->renamePort(ctx->idf("BSEL[%d]", i), ctx->idf("BSEL%d", i));
+                    }
+
+                    pass_net_type(ci, id_ASEL0);
+                    pass_net_type(ci, id_ASEL1);
+                    pass_net_type(ci, id_BSEL0);
+                    pass_net_type(ci, id_BSEL1);
+                    pass_net_type(ci, id_ACCLOAD);
+                    if (multaddalu18x18_mode == 1) {
+                        if (ci->attrs.at(id_NET_ACCLOAD).as_string() == "GND" ||
+                            ci->attrs.at(id_NET_ACCLOAD).as_string() == "VCC") {
+                            ci->disconnectPort(id_ACCLOAD);
+                        } else {
+                            ci->addInput(id_ALUSEL4);
+                            ci->addInput(id_ALUSEL6);
+                            ci->cell_bel_pins.at(id_ACCLOAD).clear();
+                            ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ALUSEL4);
+                            ci->cell_bel_pins.at(id_ACCLOAD).push_back(id_ALUSEL6);
+                        }
+                    } else {
+                        ci->disconnectPort(id_ACCLOAD);
+                    }
+
+                    for (int i = 0; i < 54; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 2; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTADDALU18X18_0_Z + i;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = BelZ::MULT9X9_0_0_Z - BelZ::MULTADDALU18X18_0_Z + i;
+                    }
+
+                    // DSP head? This primitive has the ability to form chains using both SO[AB] -> SI[AB] and
+                    // CASO->CASI
+                    bool cas_head = false;
+                    if (gwu.dsp_bus_src(ci, "CASI", 55) == nullptr) {
+                        for (int i = 0; i < 55; ++i) {
+                            ci->disconnectPort(ctx->idf("CASI[%d]", i));
+                        }
+                        cas_head = true;
+                    }
+                    bool so_head = false;
+                    if (gwu.dsp_bus_src(ci, "SIA", 18) == nullptr && gwu.dsp_bus_src(ci, "SIB", 18) == nullptr) {
+                        for (int i = 0; i < 18; ++i) {
+                            ci->disconnectPort(ctx->idf("SIA[%d]", i));
+                            ci->disconnectPort(ctx->idf("SIB[%d]", i));
+                        }
+                        so_head = true;
+                    }
+                    if (cas_head && so_head) {
+                        dsp_heads.push_back(ci);
+                        if (ctx->verbose) {
+                            log_info(" found a DSP head: %s\n", ctx->nameOf(ci));
+                        }
+                    }
+                } break;
+                case ID_MULT36X36: {
+                    for (int i = 0; i < 36; ++i) {
+                        ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).clear();
+                        ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).push_back(ctx->idf("A%d0", i));
+                        ci->cell_bel_pins.at(ctx->idf("A[%d]", i)).push_back(ctx->idf("A%d1", i));
+                        ci->cell_bel_pins.at(ctx->idf("B[%d]", i)).clear();
+                        ci->cell_bel_pins.at(ctx->idf("B[%d]", i)).push_back(ctx->idf("B%d0", i));
+                        ci->cell_bel_pins.at(ctx->idf("B[%d]", i)).push_back(ctx->idf("B%d1", i));
+                    }
+                    ci->cell_bel_pins.at(id_ASIGN).clear();
+                    ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN0);
+                    ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN1);
+                    ci->cell_bel_pins.at(id_BSIGN).clear();
+                    ci->cell_bel_pins.at(id_BSIGN).push_back(id_BSIGN0);
+                    ci->cell_bel_pins.at(id_BSIGN).push_back(id_BSIGN1);
+
+                    for (int i = 0; i < 72; ++i) {
+                        ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+                    }
+
+                    // add padd9s and mult9s as a children
+                    ci->cluster = ci->name;
+                    ci->constr_abs_z = false;
+                    ci->constr_x = 0;
+                    ci->constr_y = 0;
+                    ci->constr_z = 0;
+                    ci->constr_children.clear();
+
+                    for (int i = 0; i < 8; ++i) {
+                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(padd_cell));
+                        CellInfo *padd_ci = new_cells.back().get();
+
+                        static int padd_z[] = {BelZ::PADD9_0_0_Z, BelZ::PADD9_0_2_Z, BelZ::PADD9_1_0_Z,
+                                               BelZ::PADD9_1_2_Z};
+                        padd_ci->cluster = ci->name;
+                        padd_ci->constr_abs_z = false;
+                        padd_ci->constr_x = 0;
+                        padd_ci->constr_y = 0;
+                        padd_ci->constr_z = padd_z[i / 2] - BelZ::MULT36X36_Z + i % 2;
+
+                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
+                        new_cells.push_back(std::move(mult_cell));
+                        CellInfo *mult_ci = new_cells.back().get();
+
+                        static int mult_z[] = {BelZ::MULT9X9_0_0_Z, BelZ::MULT9X9_0_2_Z, BelZ::MULT9X9_1_0_Z,
+                                               BelZ::MULT9X9_1_2_Z};
+                        mult_ci->cluster = ci->name;
+                        mult_ci->constr_abs_z = false;
+                        mult_ci->constr_x = 0;
+                        mult_ci->constr_y = 0;
+                        mult_ci->constr_z = mult_z[i / 2] - BelZ::MULT36X36_Z + i % 2;
+                    }
+                } break;
+                default:
+                    log_error("Unsupported DSP type '%s'\n", ci->type.c_str(ctx));
+                }
+            }
+        }
+
+        // add new cells
+        for (auto &cell : new_cells) {
+            if (cell->cluster != ClusterId()) {
+                IdString cluster_root = cell->cluster;
+                IdString cell_name = cell->name;
+                ctx->cells[cell_name] = std::move(cell);
+                ctx->cells.at(cluster_root).get()->constr_children.push_back(ctx->cells.at(cell_name).get());
+            } else {
+                ctx->cells[cell->name] = std::move(cell);
+            }
+        }
+
+        // DSP chains
+        for (CellInfo *head : dsp_heads) {
+            if (ctx->verbose) {
+                log_info("Process a DSP head: %s\n", ctx->nameOf(head));
+            }
+            switch (head->type.hash()) {
+            case ID_PADD9: /* fallthrough */
+            case ID_PADD18: {
+                int wire_num = 9;
+                if (head->type == id_PADD18) {
+                    wire_num = 18;
+                }
+
+                CellInfo *cur_dsp = head;
+                while (1) {
+                    CellInfo *next_dsp_a = gwu.dsp_bus_dst(cur_dsp, "SO", wire_num);
+                    CellInfo *next_dsp_b = gwu.dsp_bus_src(cur_dsp, "SBI", wire_num);
+                    if (next_dsp_a != nullptr && next_dsp_b != nullptr && next_dsp_a != next_dsp_b) {
+                        log_error("%s is the next for two different DSPs (%s and %s) in the chain.",
+                                  ctx->nameOf(cur_dsp), ctx->nameOf(next_dsp_a), ctx->nameOf(next_dsp_b));
+                    }
+                    if (next_dsp_a == nullptr && next_dsp_b == nullptr) {
+                        // End of chain
+                        cur_dsp->setAttr(id_LAST_IN_CHAIN, 1);
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("SO[%d]", i));
+                            cur_dsp->disconnectPort(ctx->idf("SBI[%d]", i));
+                        }
+                        break;
+                    }
+
+                    next_dsp_a = next_dsp_a != nullptr ? next_dsp_a : next_dsp_b;
+                    for (int i = 0; i < wire_num; ++i) {
+                        cur_dsp->disconnectPort(ctx->idf("SO[%d]", i));
+                        cur_dsp->disconnectPort(ctx->idf("SBI[%d]", i));
+                        next_dsp_a->disconnectPort(ctx->idf("SI[%d]", i));
+                        next_dsp_a->disconnectPort(ctx->idf("SBO[%d]", i));
+                    }
+                    cur_dsp = next_dsp_a;
+                    if (ctx->verbose) {
+                        log_info("  add %s to the chain.\n", ctx->nameOf(cur_dsp));
+                    }
+                    if (head->cluster == ClusterId()) {
+                        head->cluster = head->name;
+                    }
+                    cur_dsp->cluster = head->name;
+                    head->constr_children.push_back(cur_dsp);
+                    for (auto child : cur_dsp->constr_children) {
+                        child->cluster = head->name;
+                        head->constr_children.push_back(child);
+                    }
+                    cur_dsp->constr_children.clear();
+                }
+            } break;
+            case ID_MULT9X9: /* fallthrough */
+            case ID_MULT18X18: {
+                int wire_num = 9;
+                if (head->type == id_MULT18X18) {
+                    wire_num = 18;
+                }
+
+                CellInfo *cur_dsp = head;
+                while (1) {
+                    CellInfo *next_dsp_a = gwu.dsp_bus_dst(cur_dsp, "SOA", wire_num);
+                    CellInfo *next_dsp_b = gwu.dsp_bus_dst(cur_dsp, "SOB", wire_num);
+                    if (next_dsp_a != nullptr && next_dsp_b != nullptr && next_dsp_a != next_dsp_b) {
+                        log_error("%s is the source for two different DSPs (%s and %s) in the chain.",
+                                  ctx->nameOf(cur_dsp), ctx->nameOf(next_dsp_a), ctx->nameOf(next_dsp_b));
+                    }
+                    if (next_dsp_a == nullptr && next_dsp_b == nullptr) {
+                        // End of chain
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("SOA[%d]", i));
+                            cur_dsp->disconnectPort(ctx->idf("SOB[%d]", i));
+                        }
+                        break;
+                    }
+
+                    next_dsp_a = next_dsp_a != nullptr ? next_dsp_a : next_dsp_b;
+                    for (int i = 0; i < wire_num; ++i) {
+                        cur_dsp->disconnectPort(ctx->idf("SOA[%d]", i));
+                        cur_dsp->disconnectPort(ctx->idf("SOB[%d]", i));
+                        next_dsp_a->disconnectPort(ctx->idf("SIA[%d]", i));
+                        next_dsp_a->disconnectPort(ctx->idf("SIB[%d]", i));
+                    }
+                    cur_dsp = next_dsp_a;
+                    if (ctx->verbose) {
+                        log_info("  add %s to the chain.\n", ctx->nameOf(cur_dsp));
+                    }
+                    if (head->cluster == ClusterId()) {
+                        head->cluster = head->name;
+                    }
+                    cur_dsp->cluster = head->name;
+                    head->constr_children.push_back(cur_dsp);
+                    for (auto child : cur_dsp->constr_children) {
+                        child->cluster = head->name;
+                        head->constr_children.push_back(child);
+                    }
+                    cur_dsp->constr_children.clear();
+                }
+            } break;
+            case ID_MULTALU18X18: /* fallthrough */
+            case ID_MULTALU36X18: /* fallthrough */
+            case ID_ALU54D: {
+                int wire_num = 55;
+                CellInfo *cur_dsp = head;
+                while (1) {
+                    CellInfo *next_dsp_a = gwu.dsp_bus_dst(cur_dsp, "CASO", wire_num);
+                    if (next_dsp_a == nullptr) {
+                        // End of chain
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("CASO[%d]", i));
+                        }
+                        break;
+                    }
+                    for (int i = 0; i < wire_num; ++i) {
+                        cur_dsp->disconnectPort(ctx->idf("CASO[%d]", i));
+                        next_dsp_a->disconnectPort(ctx->idf("CASI[%d]", i));
+                    }
+                    cur_dsp->setAttr(id_USE_CASCADE_OUT, 1);
+                    cur_dsp = next_dsp_a;
+                    cur_dsp->setAttr(id_USE_CASCADE_IN, 1);
+                    if (ctx->verbose) {
+                        log_info("  add %s to the chain.\n", ctx->nameOf(cur_dsp));
+                    }
+                    if (head->cluster == ClusterId()) {
+                        head->cluster = head->name;
+                    }
+                    cur_dsp->cluster = head->name;
+                    head->constr_children.push_back(cur_dsp);
+                    for (auto child : cur_dsp->constr_children) {
+                        child->cluster = head->name;
+                        head->constr_children.push_back(child);
+                    }
+                    cur_dsp->constr_children.clear();
+                }
+            } break;
+            case ID_MULTADDALU18X18: {
+                // This primitive has the ability to form chains using both SO[AB] -> SI[AB] and CASO->CASI
+                CellInfo *cur_dsp = head;
+                while (1) {
+                    bool end_of_cas_chain = false;
+                    int wire_num = 55;
+                    CellInfo *next_dsp_a = gwu.dsp_bus_dst(cur_dsp, "CASO", wire_num);
+                    if (next_dsp_a == nullptr) {
+                        // End of CASO chain
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("CASO[%d]", i));
+                        }
+                        end_of_cas_chain = true;
+                    } else {
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("CASO[%d]", i));
+                            next_dsp_a->disconnectPort(ctx->idf("CASI[%d]", i));
+                        }
+                    }
+
+                    bool end_of_so_chain = false;
+                    wire_num = 18;
+                    CellInfo *next_so_dsp_a = gwu.dsp_bus_dst(cur_dsp, "SOA", wire_num);
+                    CellInfo *next_so_dsp_b = gwu.dsp_bus_dst(cur_dsp, "SOB", wire_num);
+                    if (next_so_dsp_a != nullptr && next_so_dsp_b != nullptr && next_so_dsp_a != next_so_dsp_b) {
+                        log_error("%s is the source for two different DSPs (%s and %s) in the chain.",
+                                  ctx->nameOf(cur_dsp), ctx->nameOf(next_so_dsp_a), ctx->nameOf(next_so_dsp_b));
+                    }
+                    if (next_so_dsp_a == nullptr && next_so_dsp_b == nullptr) {
+                        // End of SO chain
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("SOA[%d]", i));
+                            cur_dsp->disconnectPort(ctx->idf("SOB[%d]", i));
+                        }
+                        end_of_so_chain = true;
+                    } else {
+                        next_so_dsp_a = next_so_dsp_a != nullptr ? next_so_dsp_a : next_so_dsp_b;
+                        for (int i = 0; i < wire_num; ++i) {
+                            cur_dsp->disconnectPort(ctx->idf("SOA[%d]", i));
+                            cur_dsp->disconnectPort(ctx->idf("SOB[%d]", i));
+                            next_so_dsp_a->disconnectPort(ctx->idf("SIA[%d]", i));
+                            next_so_dsp_a->disconnectPort(ctx->idf("SIB[%d]", i));
+                        }
+                    }
+                    if (end_of_cas_chain && end_of_so_chain) {
+                        break;
+                    }
+
+                    // to next
+                    if (!end_of_cas_chain) {
+                        cur_dsp->setAttr(id_USE_CASCADE_OUT, 1);
+                    }
+                    cur_dsp = next_dsp_a != nullptr ? next_dsp_a : next_so_dsp_a;
+                    if (!end_of_cas_chain) {
+                        cur_dsp->setAttr(id_USE_CASCADE_IN, 1);
+                    }
+                    if (ctx->verbose) {
+                        log_info("  add %s to the chain. End of the SO chain:%d, end of the CAS chain:%d\n",
+                                 ctx->nameOf(cur_dsp), end_of_so_chain, end_of_cas_chain);
+                    }
+                    if (head->cluster == ClusterId()) {
+                        head->cluster = head->name;
+                    }
+                    cur_dsp->cluster = head->name;
+                    head->constr_children.push_back(cur_dsp);
+                    for (auto child : cur_dsp->constr_children) {
+                        child->cluster = head->name;
+                        head->constr_children.push_back(child);
+                    }
+                    cur_dsp->constr_children.clear();
+                }
+            } break;
+            }
+        }
+    }
+
     // ===================================
     // Global set/reset
     // ===================================
     void pack_gsr(void)
     {
-        log_info("Pack GSR..\n");
+        log_info("Pack GSR...\n");
 
         bool user_gsr = false;
         for (auto &cell : ctx->cells) {
@@ -1683,7 +2603,7 @@ struct GowinPacker
     // ===================================
     void pack_inv(void)
     {
-        log_info("Pack INV..\n");
+        log_info("Pack INV...\n");
 
         for (auto &cell : ctx->cells) {
             auto &ci = *cell.second;
@@ -1702,7 +2622,7 @@ struct GowinPacker
     // ===================================
     void pack_pll(void)
     {
-        log_info("Pack PLL..\n");
+        log_info("Pack PLL...\n");
 
         for (auto &cell : ctx->cells) {
             auto &ci = *cell.second;
@@ -1728,7 +2648,7 @@ struct GowinPacker
     // =========================================
     void pack_buffered_nets()
     {
-        log_info("Pack buffered nets..\n");
+        log_info("Pack buffered nets...\n");
 
         for (auto &net : ctx->nets) {
             auto &ni = *net.second;
@@ -1796,6 +2716,9 @@ struct GowinPacker
         pack_bsram();
         ctx->check();
 
+        pack_dsp();
+        ctx->check();
+
         pack_buffered_nets();
 
         ctx->fixupHierarchy();

From 5ecb669a41e835ad6166aff3ccf86ff0f1a4f061 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 19 Mar 2024 08:06:17 +1000
Subject: [PATCH 586/712] gowin: BUGFIX fix typo

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 1fc3e5747d..751f1865b0 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -114,7 +114,7 @@ void GowinImpl::init_database(Arch *arch)
     } else {
         bool GW2 = args.device.rfind("GW2A", 0) == 0;
         if (GW2) {
-            log_error("For the GW2A series you need to specify -vopt family=GW2A-18 or -vopt family=GW2A-18C\n");
+            log_error("For the GW2A series you need to specify --vopt family=GW2A-18 or --vopt family=GW2A-18C\n");
         } else {
             std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
             std::smatch match;
@@ -123,7 +123,7 @@ void GowinImpl::init_database(Arch *arch)
             }
             family = stringf("GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
             if (family.rfind("GW1N-9", 0) == 0) {
-                log_error("For the GW1N-9 series you need to specify -vopt family=GW1N-9 or -vopt family=GW1N-9C\n");
+                log_error("For the GW1N-9 series you need to specify --vopt family=GW1N-9 or --vopt family=GW1N-9C\n");
             }
         }
     }

From 693058abb7a4bce2ff0c73ba60a79ada8c764196 Mon Sep 17 00:00:00 2001
From: Andrew Bell <andrew.bell.ia@gmail.com>
Date: Tue, 19 Mar 2024 14:25:07 -0400
Subject: [PATCH 587/712] Eliminate gcc13 warnings.

---
 3rdparty/json11/json11.cpp      | 16 ++++++++--------
 common/place/parallel_refine.cc |  2 --
 common/place/placer1.cc         |  2 --
 common/place/placer_static.cc   |  6 ------
 4 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/3rdparty/json11/json11.cpp b/3rdparty/json11/json11.cpp
index faa6cf645d..a0fcf866cc 100644
--- a/3rdparty/json11/json11.cpp
+++ b/3rdparty/json11/json11.cpp
@@ -152,7 +152,7 @@ class Value : public JsonValue {
 
     // Constructors
     explicit Value(const T &value) : m_value(value) {}
-    explicit Value(T &&value)      : m_value(move(value)) {}
+    explicit Value(T &&value)      : m_value(std::move(value)) {}
 
     // Get type tag
     Json::Type type() const override {
@@ -199,7 +199,7 @@ class JsonString final : public Value<Json::STRING, string> {
     const string &string_value() const override { return m_value; }
 public:
     explicit JsonString(const string &value) : Value(value) {}
-    explicit JsonString(string &&value)      : Value(move(value)) {}
+    explicit JsonString(string &&value)      : Value(std::move(value)) {}
 };
 
 class JsonArray final : public Value<Json::ARRAY, Json::array> {
@@ -207,7 +207,7 @@ class JsonArray final : public Value<Json::ARRAY, Json::array> {
     const Json & operator[](size_t i) const override;
 public:
     explicit JsonArray(const Json::array &value) : Value(value) {}
-    explicit JsonArray(Json::array &&value)      : Value(move(value)) {}
+    explicit JsonArray(Json::array &&value)      : Value(std::move(value)) {}
 };
 
 class JsonObject final : public Value<Json::OBJECT, Json::object> {
@@ -215,7 +215,7 @@ class JsonObject final : public Value<Json::OBJECT, Json::object> {
     const Json & operator[](const string &key) const override;
 public:
     explicit JsonObject(const Json::object &value) : Value(value) {}
-    explicit JsonObject(Json::object &&value)      : Value(move(value)) {}
+    explicit JsonObject(Json::object &&value)      : Value(std::move(value)) {}
 };
 
 class JsonNull final : public Value<Json::NUL, NullStruct> {
@@ -257,12 +257,12 @@ Json::Json(double value)               : m_ptr(make_shared<JsonDouble>(value)) {
 Json::Json(int value)                  : m_ptr(make_shared<JsonInt>(value)) {}
 Json::Json(bool value)                 : m_ptr(value ? statics().t : statics().f) {}
 Json::Json(const string &value)        : m_ptr(make_shared<JsonString>(value)) {}
-Json::Json(string &&value)             : m_ptr(make_shared<JsonString>(move(value))) {}
+Json::Json(string &&value)             : m_ptr(make_shared<JsonString>(std::move(value))) {}
 Json::Json(const char * value)         : m_ptr(make_shared<JsonString>(value)) {}
 Json::Json(const Json::array &values)  : m_ptr(make_shared<JsonArray>(values)) {}
-Json::Json(Json::array &&values)       : m_ptr(make_shared<JsonArray>(move(values))) {}
+Json::Json(Json::array &&values)       : m_ptr(make_shared<JsonArray>(std::move(values))) {}
 Json::Json(const Json::object &values) : m_ptr(make_shared<JsonObject>(values)) {}
-Json::Json(Json::object &&values)      : m_ptr(make_shared<JsonObject>(move(values))) {}
+Json::Json(Json::object &&values)      : m_ptr(make_shared<JsonObject>(std::move(values))) {}
 
 /* * * * * * * * * * * * * * * * * * * *
  * Accessors
@@ -360,7 +360,7 @@ struct JsonParser final {
      * Mark this parse as failed.
      */
     Json fail(string &&msg) {
-        return fail(move(msg), Json());
+        return fail(std::move(msg), Json());
     }
 
     template <typename T>
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index da8ed4fc15..dab45eba92 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -177,7 +177,6 @@ struct ThreadState : DetailPlacerThreadState
     {
         IdString targetType = cell->type;
         Loc curr_loc = ctx->getBelLocation(cell->bel);
-        int count = 0;
 
         int dx = g.radius, dy = g.radius;
         if (cell->region != nullptr && cell->region->constr_bels) {
@@ -217,7 +216,6 @@ struct ThreadState : DetailPlacerThreadState
             }
             if (!cell->testRegion(bel))
                 continue;
-            count++;
             return bel;
         }
     }
diff --git a/common/place/placer1.cc b/common/place/placer1.cc
index 057f0106cd..b2009e08bd 100644
--- a/common/place/placer1.cc
+++ b/common/place/placer1.cc
@@ -732,7 +732,6 @@ class SAPlacer
     {
         IdString targetType = cell->type;
         Loc curr_loc = ctx->getBelLocation(cell->bel);
-        int count = 0;
 
         int dx = diameter, dy = diameter;
         if (cell->region != nullptr && cell->region->constr_bels) {
@@ -772,7 +771,6 @@ class SAPlacer
                 continue;
             if (locked_bels.find(bel) != locked_bels.end())
                 continue;
-            count++;
             return bel;
         }
     }
diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 9b3d855643..56e460329b 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -917,7 +917,6 @@ class StaticPlacer
     {
         float coord_dist = 0;
         float grad_dist = 0;
-        int n = 0;
         for (auto &cell : mcells) {
             coord_dist += (cell.ref_pos.x - cell.last_ref_pos.x) * (cell.ref_pos.x - cell.last_ref_pos.x);
             coord_dist += (cell.ref_pos.y - cell.last_ref_pos.y) * (cell.ref_pos.y - cell.last_ref_pos.y);
@@ -925,8 +924,6 @@ class StaticPlacer
                     (cell.ref_total_grad.x - cell.last_total_grad.x) * (cell.ref_total_grad.x - cell.last_total_grad.x);
             grad_dist +=
                     (cell.ref_total_grad.y - cell.last_total_grad.y) * (cell.ref_total_grad.y - cell.last_total_grad.y);
-            // keep track of N separately, because we might exclude some cells
-            ++n;
         }
         coord_dist = std::sqrt(coord_dist / (2 * float(mcells.size())));
         grad_dist = std::sqrt(grad_dist / (2 * float(mcells.size())));
@@ -1155,7 +1152,6 @@ class StaticPlacer
             int radius = 0;
             int iter = 0;
             int iter_at_radius = 0;
-            int total_iters_for_cell = 0;
             bool placed = false;
             BelId bestBel;
             int best_inp_len = std::numeric_limits<int>::max();
@@ -1374,8 +1370,6 @@ class StaticPlacer
                         break;
                     }
                 }
-
-                total_iters_for_cell++;
             }
         }
     }

From b4da57598eaac912bbf3fa30462da7b511c940ea Mon Sep 17 00:00:00 2001
From: Andrew Bell <andrew.bell.ia@gmail.com>
Date: Wed, 20 Mar 2024 08:52:40 -0400
Subject: [PATCH 588/712] One more warning.

---
 common/place/placer_heap.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 1ed7142692..b701c65f40 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -1543,12 +1543,10 @@ class HeAPPlacer
         {
             cut_cells.clear();
             auto &cal = cells_at_location;
-            int total_cells = 0, total_bels = 0;
+            int total_cells = 0;
             for (int x = r.x0; x <= r.x1; x++) {
                 for (int y = r.y0; y <= r.y1; y++) {
                     std::copy(cal.at(x).at(y).begin(), cal.at(x).at(y).end(), std::back_inserter(cut_cells));
-                    for (size_t t = 0; t < buckets.size(); t++)
-                        total_bels += bels_at(x, y, t);
                 }
             }
             for (auto &cell : cut_cells) {

From 7f9f75c0d30cc11694aa793b568c0098fb0db1de Mon Sep 17 00:00:00 2001
From: Jason Thorpe <thorpej@me.com>
Date: Sat, 2 Mar 2024 18:54:11 -0800
Subject: [PATCH 589/712] Tweak the FreeBSD version of proc_self_dirname() to
 work on NetBSD and use it.

Resolves issue #1298.
---
 common/kernel/command.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 087af5b3a6..ae14ceacfa 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -61,7 +61,7 @@
 #include <unistd.h>
 #endif
 
-#ifdef __FreeBSD__
+#if defined(__FreeBSD__) || defined(__NetBSD__)
 #include <sys/sysctl.h>
 #endif
 
@@ -90,10 +90,14 @@ std::string proc_self_dirname()
         buflen--;
     return std::string(path, buflen);
 }
-#elif defined(__FreeBSD__)
+#elif defined(__FreeBSD__) || defined(__NetBSD__)
 std::string proc_self_dirname()
 {
+#ifdef __NetBSD__
+    int mib[4] = {CTL_KERN, KERN_PROC_ARGS, getpid(), KERN_PROC_PATHNAME};
+#else
     int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1};
+#endif
     size_t buflen;
     char *buffer;
     std::string path;

From 465cbfaf194e92fc42232c2c6b7dea71d87dba20 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 29 Feb 2024 08:45:13 +0100
Subject: [PATCH 590/712] Add share to .gitignore

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index d5a21ea1c7..087c35ac5e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -29,6 +29,7 @@ a.out
 *.il
 /generic/examples/blinky.png
 build/
+share/
 *.asc
 *.bin
 /Testing/*

From 75af8ccfd2083a9fb93b728f0bc70ad6c1a03b16 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 29 Feb 2024 08:48:04 +0100
Subject: [PATCH 591/712] gui: user more reliable locking

---
 gui/fpgaviewwidget.h | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/gui/fpgaviewwidget.h b/gui/fpgaviewwidget.h
index 3a2402291e..b5d7e11f3f 100644
--- a/gui/fpgaviewwidget.h
+++ b/gui/fpgaviewwidget.h
@@ -60,17 +60,12 @@ class PeriodicRunner : public QThread
     void run(void) override
     {
         for (;;) {
-            mutex_.lock();
+            QMutexLocker locker(&mutex_);
             condition_.wait(&mutex_);
-
             if (abort_) {
-                mutex_.unlock();
                 return;
             }
-
             target_();
-
-            mutex_.unlock();
         }
     }
 
@@ -78,11 +73,11 @@ class PeriodicRunner : public QThread
 
     ~PeriodicRunner()
     {
-        mutex_.lock();
-        abort_ = true;
-        condition_.wakeOne();
-        mutex_.unlock();
-
+        {
+            QMutexLocker locker(&mutex_);
+            abort_ = true;
+            condition_.wakeOne();
+        }
         wait();
     }
 

From ac725465a9a1e22c1b3627e9a860381a306f28ab Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 29 Feb 2024 08:48:19 +0100
Subject: [PATCH 592/712] gui: fix warning on closing application

---
 gui/lineshader.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gui/lineshader.h b/gui/lineshader.h
index 9d2524b3a7..784f35a82b 100644
--- a/gui/lineshader.h
+++ b/gui/lineshader.h
@@ -170,6 +170,7 @@ class LineShader
 
   public:
     LineShader(QObject *parent) : parent_(parent), program_(nullptr) {}
+    ~LineShader() { ((QOpenGLWidget*) parent_)->makeCurrent(); }
 
     static constexpr const char *vertexShaderSource_ =
             "#version 150\n"

From 1f25f2067a1fca9d7da0440ea80525ceffe1b297 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 29 Feb 2024 09:15:55 +0100
Subject: [PATCH 593/712] Make example more like other arch

---
 himbaechel/uarch/example/CMakeLists.txt      | 29 ++++++++++++++++++++
 himbaechel/uarch/example/example.cc          |  2 +-
 himbaechel/uarch/example/example_arch_gen.py |  2 +-
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/example/CMakeLists.txt b/himbaechel/uarch/example/CMakeLists.txt
index bc1c3b5953..046f01306a 100644
--- a/himbaechel/uarch/example/CMakeLists.txt
+++ b/himbaechel/uarch/example/CMakeLists.txt
@@ -1,2 +1,31 @@
 message(STATUS "Configuring Himbaechel-Example uarch")
+cmake_minimum_required(VERSION 3.5)
+project(himbaechel-example-chipdb NONE)
 
+set(ALL_HIMBAECHEL_EXAMPLE_DEVICES example)
+set(HIMBAECHEL_EXAMPLE_DEVICES "" CACHE STRING
+    "Include support for these Example devices (available: ${ALL_HIMBAECHEL_EXAMPLE_DEVICES})")
+message(STATUS "Enabled Himbaechel-Example devices: ${HIMBAECHEL_EXAMPLE_DEVICES}")
+
+set(chipdb_binaries)
+file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/example)
+foreach(device ${HIMBAECHEL_EXAMPLE_DEVICES})
+	set(device_bba ${CMAKE_BINARY_DIR}/share/himbaechel/example/chipdb-${device}.bba)
+	set(device_bin ${CMAKE_BINARY_DIR}/share/himbaechel/example/chipdb-${device}.bin)
+	add_custom_command(
+		OUTPUT ${device_bin}
+		COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/example_arch_gen.py ${device_bba}
+		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}.new
+        # atomically update
+        COMMAND ${CMAKE_COMMAND} -E rename ${device_bin}.new ${device_bin}
+		DEPENDS
+			bbasm
+			${CMAKE_CURRENT_SOURCE_DIR}/example_arch_gen.py
+			${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+		VERBATIM)
+	list(APPEND chipdb_binaries ${device_bin})
+endforeach()
+
+add_custom_target(chipdb-himbaechel-example ALL DEPENDS ${chipdb_binaries})
+install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/example/ DESTINATION share/nextpnr/himbaechel/example
+	    PATTERN "*.bba" EXCLUDE)
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index 4e8dff4a56..5172d5cf7f 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -40,7 +40,7 @@ struct ExampleImpl : HimbaechelAPI
     void init_database(Arch *arch) override
     {
         init_uarch_constids(arch);
-        arch->load_chipdb("example/example.bin");
+        arch->load_chipdb("example/chipdb-example.bin");
         arch->set_speed_grade("DEFAULT");
     }
 
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
index d4d0496bc5..cbfefd61ef 100644
--- a/himbaechel/uarch/example/example_arch_gen.py
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -170,7 +170,7 @@ def is_corner(x, y):
 
 def create_nodes(ch):
     for y in range(Y):
-        print(f"generating nodes for row {y}")
+        #print(f"generating nodes for row {y}")
         for x in range(X):
             if not is_corner(x, y):
                 # connect up actual neighbours

From 9bb46b98b474cacf3f21268e8962a7ecd6a2ec6d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 29 Feb 2024 10:33:44 +0100
Subject: [PATCH 594/712] update ci build script

---
 .github/ci/build_himbaechel.sh | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/.github/ci/build_himbaechel.sh b/.github/ci/build_himbaechel.sh
index 73db3b5700..62e133900e 100644
--- a/.github/ci/build_himbaechel.sh
+++ b/.github/ci/build_himbaechel.sh
@@ -7,13 +7,8 @@ function get_dependencies {
 function build_nextpnr {
     mkdir build
     pushd build
-    cmake .. -DARCH=himbaechel
-    make nextpnr-himbaechel bbasm -j`nproc`
-    # We'd ideally use pypy3 for speed (as works locally), but the version
-    # our CI Ubuntu provides doesn't like some of the typing stuff
-    python3 ../himbaechel/uarch/example/example_arch_gen.py ./example.bba
-    mkdir -p share/himbaechel/example
-    ./bba/bbasm --l ./example.bba share/himbaechel/example/example.bin
+    cmake .. -DARCH=himbaechel -DHIMBAECHEL_EXAMPLE_DEVICES=example
+    make nextpnr-himbaechel chipdb-himbaechel-example -j`nproc`
     popd
 }
 

From 6b7723e4c1be110a98f28c9ab7ad47bb1a61bb54 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 7 Apr 2024 21:47:23 +1000
Subject: [PATCH 595/712] Gowin. Add PLL pads.

If the CLKIN input of the PLL is connected to a special pin, then it
makes sense to try to place the PLL so that it uses a direct implicit
non-switched connection to this pin.

The transfer of information about pins for various purposes has been
implemented (clock input signal, feedback, etc), but so far only CLKIN
is used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  4 ++++
 himbaechel/uarch/gowin/gowin.h           |  6 ++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 25 ++++++++++++++++++++++++
 himbaechel/uarch/gowin/gowin_utils.cc    | 23 ++++++++++++++++++++--
 himbaechel/uarch/gowin/gowin_utils.h     |  5 ++++-
 himbaechel/uarch/gowin/pack.cc           | 22 +++++++++++++++++++++
 6 files changed, 82 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index b356872075..78ddb1fb44 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1140,6 +1140,10 @@ X(router)
 X(GOWIN_GND)
 X(GOWIN_VCC)
 X(PLL)
+X(CLKIN_T)
+X(CLKIN_C)
+X(FB_T)
+X(FB_C)
 X(BOTTOM_IO_PORT_A)
 X(BOTTOM_IO_PORT_B)
 X(IOLOGIC_DUMMY)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index aa3dcd083e..abff9031e3 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -65,6 +65,12 @@ inline bool is_dsp(const CellInfo *cell) { return type_is_dsp(cell->type); }
 // ==========================================
 // extra data in the chip db
 // ==========================================
+NPNR_PACKED_STRUCT(struct Pad_extra_data_POD {
+    int32_t pll_tile;
+    int32_t pll_bel;
+    int32_t pll_type;
+});
+
 NPNR_PACKED_STRUCT(struct Tile_extra_data_POD {
     int32_t class_id;
     int16_t io16_x_off;
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 3ba94c525a..2aab88f6d0 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -157,6 +157,20 @@ def serialise(self, context: str, bba: BBAWriter):
         self.bottom_io.serialise(f"{context}_bottom_io", bba)
         bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
 
+@dataclass
+class PadExtraData(BBAStruct):
+    # Which PLL does this pad belong to.
+    pll_tile: IdString
+    pll_bel:  IdString
+    pll_type: IdString
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.pll_tile.index)
+        bba.u32(self.pll_bel.index)
+        bba.u32(self.pll_type.index)
+
 # Unique features of the tiletype
 class TypeDesc:
     def __init__(self, dups, tiletype = '', extra_func = None, sfx = 0):
@@ -917,6 +931,15 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
     tdesc.tiletype = tiletype
     return tt
 
+# add Pll's bel to the pad
+def add_pll(chip: Chip, db: chipdb, pad: PadInfo, ioloc: str):
+    try:
+        if ioloc in db.pad_pll:
+            row, col, ttyp, bel_name = db.pad_pll[ioloc]
+            pad.extra_data = PadExtraData(chip.strs.id(f'X{col}Y{row}'), chip.strs.id(bel_name), chip.strs.id(ttyp))
+    except:
+        return
+
 # pinouts, packages...
 _tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
 def create_packages(chip: Chip, db: chipdb):
@@ -953,6 +976,8 @@ def ioloc_to_tile_bel(ioloc):
             pad_func = pad_func.rstrip('/')
             bank = int(db.pin_bank[io_loc])
             pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
+            # add PLL if any is connected
+            add_pll(chip, db, pad, io_loc)
 
 # Extra chip data
 def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index df255527a1..3aba699d67 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -30,9 +30,9 @@ Loc GowinUtils::get_tile_io16_offs(int x, int y)
 }
 
 // pin functions: GCLKT_4, SSPI_CS, READY etc
-IdStringList GowinUtils::get_pin_funcs(BelId bel)
+IdStringList GowinUtils::get_pin_funcs(BelId io_bel)
 {
-    IdStringList bel_name = ctx->getBelName(bel);
+    IdStringList bel_name = ctx->getBelName(io_bel);
 
     const PadInfoPOD *pins = ctx->package_info->pads.get();
     size_t len = ctx->package_info->pads.ssize();
@@ -45,6 +45,25 @@ IdStringList GowinUtils::get_pin_funcs(BelId bel)
     return IdStringList();
 }
 
+// PLL pads
+BelId GowinUtils::get_pll_bel(BelId io_bel, IdString type)
+{
+    IdStringList bel_name = ctx->getBelName(io_bel);
+
+    const PadInfoPOD *pins = ctx->package_info->pads.get();
+    size_t len = ctx->package_info->pads.ssize();
+    for (size_t i = 0; i < len; i++) {
+        const PadInfoPOD *pin = &pins[i];
+        if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
+            const Pad_extra_data_POD *extra = reinterpret_cast<const Pad_extra_data_POD *>(pin->extra_data.get());
+            if (extra != nullptr && IdString(extra->pll_type) == type) {
+                return ctx->getBelByName(IdStringList::concat(IdString(extra->pll_tile), IdString(extra->pll_bel)));
+            }
+        }
+    }
+    return BelId();
+}
+
 bool GowinUtils::is_simple_io_bel(BelId bel)
 {
     return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index ea466b1124..ce6b8d9fca 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -24,7 +24,10 @@ struct GowinUtils
     Loc get_tile_io16_offs(int x, int y);
 
     // pin functions: GCLKT_4, SSPI_CS, READY etc
-    IdStringList get_pin_funcs(BelId bel);
+    IdStringList get_pin_funcs(BelId io_bel);
+
+    // PLL pads (type - CLKIN, FeedBack, etc)
+    BelId get_pll_bel(BelId io_bel, IdString type);
 
     // Bels and pips
     bool is_simple_io_bel(BelId bel);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ad85fce17c..c28a9eea41 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -2624,6 +2624,8 @@ struct GowinPacker
     {
         log_info("Pack PLL...\n");
 
+        pool<BelId> used_pll_bels;
+
         for (auto &cell : ctx->cells) {
             auto &ci = *cell.second;
 
@@ -2639,6 +2641,26 @@ struct GowinPacker
                         ci.renamePort(ctx->idf("FDLY[%d]", i), ctx->idf("FDLY%d", i));
                     }
                 }
+                // If CLKIN is connected to a special pin, then it makes sense
+                // to try to place the PLL so that it uses a direct connection
+                // to this pin.
+                if (ci.bel == BelId()) {
+                    NetInfo *ni = ci.getPort(id_CLKIN);
+                    if (ni && ni->driver.cell) {
+                        BelId pll_bel = gwu.get_pll_bel(ni->driver.cell->bel, id_CLKIN_T);
+                        if (ctx->debug) {
+                            log_info("PLL clkin driver:%s at %s, PLL bel:%s\n", ctx->nameOf(ni->driver.cell),
+                                     ctx->getBelName(ni->driver.cell->bel).str(ctx).c_str(),
+                                     pll_bel != BelId() ? ctx->getBelName(pll_bel).str(ctx).c_str() : "NULL");
+                        }
+                        if (pll_bel != BelId() && used_pll_bels.count(pll_bel) == 0) {
+                            used_pll_bels.insert(pll_bel);
+                            ctx->bindBel(pll_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+                            ci.disconnectPort(id_CLKIN);
+                            ci.setParam(id_INSEL, std::string("CLKIN0"));
+                        }
+                    }
+                }
             }
         }
     }

From d3b53d8e1a36abe835a39847aaeb79e045062b8c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 8 Apr 2024 21:50:40 +1000
Subject: [PATCH 596/712] Gowin. PLL Pads. Fix the condition.

Do not search for pads if the signal source for the PLL is something
other than the IO pin - these are guaranteed to already be placed and
have a bound Bel.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index c28a9eea41..e20ac71225 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -2646,7 +2646,7 @@ struct GowinPacker
                 // to this pin.
                 if (ci.bel == BelId()) {
                     NetInfo *ni = ci.getPort(id_CLKIN);
-                    if (ni && ni->driver.cell) {
+                    if (ni && ni->driver.cell && ni->driver.cell->bel != BelId()) {
                         BelId pll_bel = gwu.get_pll_bel(ni->driver.cell->bel, id_CLKIN_T);
                         if (ctx->debug) {
                             log_info("PLL clkin driver:%s at %s, PLL bel:%s\n", ctx->nameOf(ni->driver.cell),

From 4d5c48ad834550e5821b42eada5085d339f79cd7 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 17 Apr 2024 14:52:34 +1000
Subject: [PATCH 597/712] Gowin. Fix DSP MULT36X36

When multiplying 36 bits by 36 bits using four 18x18 multipliers, the
sign bits of the higher 18-bit parts of the multipliers were correctly
switched, but what was incorrect was leaving the sign bits of the lower
parts of the multipliers uninitialized. They now connect to VSS.

Addresses https://github.com/YosysHQ/apicula/issues/242

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  5 +++++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 12 ++++++++++--
 himbaechel/uarch/gowin/pack.cc           | 10 ++++++++++
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 78ddb1fb44..77de2ee814 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -933,6 +933,11 @@ X(ASIGN0)
 X(BSIGN0)
 X(ASIGN1)
 X(BSIGN1)
+X(ZERO_SIGN)
+X(ZERO_ASIGN0)
+X(ZERO_BSIGN0)
+X(ZERO_ASIGN1)
+X(ZERO_BSIGN1)
 X(ASEL)
 X(ASEL0)
 X(ASEL1)
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 2aab88f6d0..e84e853bef 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -421,14 +421,17 @@ def find_or_make_dup():
     create_switch_matrix(tt, db, x, y)
     chip.set_tile_type(x, y, tdesc.tiletype)
 
-def add_port_wire(tt, bel, portmap, name, wire_type, port_type):
+def add_port_wire(tt, bel, portmap, name, wire_type, port_type, pin_name = None):
     wire = portmap[name]
     if not tt.has_wire(wire):
         if name.startswith('CLK'):
             tt.create_wire(wire, "TILE_CLK")
         else:
             tt.create_wire(wire, wire_type)
-    tt.add_bel_pin(bel, name, wire, port_type)
+    if pin_name:
+        tt.add_bel_pin(bel, pin_name, wire, port_type)
+    else:
+        tt.add_bel_pin(bel, name, wire, port_type)
 
 def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
     typename = "NULL"
@@ -776,6 +779,11 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
     portmap = db.grid[y][x].bels[belname].portmap
     dsp = tt.create_bel(belname, "MULT36X36", MULT36X36_Z)
 
+    # LSB 18x18 multipliers sign ports must be zero
+    add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN0')
+    add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN0')
+    add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1801'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN1')
+    add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1810'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN1')
     for i in range(2):
         for sfx in {'A', 'B'}:
             for inp in range(36):
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index e20ac71225..193892e2e7 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -2288,6 +2288,7 @@ struct GowinPacker
                         ci->cell_bel_pins.at(ctx->idf("B[%d]", i)).push_back(ctx->idf("B%d0", i));
                         ci->cell_bel_pins.at(ctx->idf("B[%d]", i)).push_back(ctx->idf("B%d1", i));
                     }
+                    // only MSB sign bits
                     ci->cell_bel_pins.at(id_ASIGN).clear();
                     ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN0);
                     ci->cell_bel_pins.at(id_ASIGN).push_back(id_ASIGN1);
@@ -2295,6 +2296,15 @@ struct GowinPacker
                     ci->cell_bel_pins.at(id_BSIGN).push_back(id_BSIGN0);
                     ci->cell_bel_pins.at(id_BSIGN).push_back(id_BSIGN1);
 
+                    // LSB sign bits = 0
+                    NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+                    ci->addInput(id_ZERO_SIGN);
+                    ci->cell_bel_pins[id_ZERO_SIGN].push_back(id_ZERO_ASIGN0);
+                    ci->cell_bel_pins.at(id_ZERO_SIGN).push_back(id_ZERO_BSIGN0);
+                    ci->cell_bel_pins.at(id_ZERO_SIGN).push_back(id_ZERO_BSIGN1);
+                    ci->cell_bel_pins.at(id_ZERO_SIGN).push_back(id_ZERO_ASIGN1);
+                    ci->connectPort(id_ZERO_SIGN, vss_net);
+
                     for (int i = 0; i < 72; ++i) {
                         ci->renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
                     }

From edcafcf085aa0ee65f1cf01dd5f33d877777f911 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 17 Apr 2024 08:23:17 +0200
Subject: [PATCH 598/712] Ignore compile artifacts in rust directory

---
 rust/.gitignore | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 rust/.gitignore

diff --git a/rust/.gitignore b/rust/.gitignore
new file mode 100644
index 0000000000..1e7caa9ea8
--- /dev/null
+++ b/rust/.gitignore
@@ -0,0 +1,2 @@
+Cargo.lock
+target/

From f085950383155a745cf2e3c0f28c468d01ff5fd7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Patrick=20Da=CC=88hne?= <pdaehne@gmail.com>
Date: Fri, 26 Apr 2024 15:34:12 +0200
Subject: [PATCH 599/712] Fixed header files for boost 1.85.0

---
 bba/main.cc              | 2 +-
 common/kernel/command.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/bba/main.cc b/bba/main.cc
index 70fc346088..82c4426b22 100644
--- a/bba/main.cc
+++ b/bba/main.cc
@@ -19,7 +19,7 @@
  */
 
 #include <assert.h>
-#include <boost/filesystem/convenience.hpp>
+#include <boost/filesystem/path.hpp>
 #include <boost/program_options.hpp>
 #include <iostream>
 #include <map>
diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index ae14ceacfa..44482946c6 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -29,7 +29,7 @@
 
 #include <boost/algorithm/string.hpp>
 #include <boost/algorithm/string/join.hpp>
-#include <boost/filesystem/convenience.hpp>
+#include <boost/filesystem/path.hpp>
 #include <boost/program_options.hpp>
 #include <fstream>
 #include <iostream>

From 7a00e76cb19561db620cab724ac8ce5a53b3e1e4 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 3 May 2024 09:36:09 +0200
Subject: [PATCH 600/712] static: Exclude dark nodes from steplength

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 56e460329b..65116eedcc 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -917,16 +917,20 @@ class StaticPlacer
     {
         float coord_dist = 0;
         float grad_dist = 0;
+        int n = 0;
         for (auto &cell : mcells) {
+            if (cell.is_fixed || cell.is_dark)
+                continue;
             coord_dist += (cell.ref_pos.x - cell.last_ref_pos.x) * (cell.ref_pos.x - cell.last_ref_pos.x);
             coord_dist += (cell.ref_pos.y - cell.last_ref_pos.y) * (cell.ref_pos.y - cell.last_ref_pos.y);
             grad_dist +=
                     (cell.ref_total_grad.x - cell.last_total_grad.x) * (cell.ref_total_grad.x - cell.last_total_grad.x);
             grad_dist +=
                     (cell.ref_total_grad.y - cell.last_total_grad.y) * (cell.ref_total_grad.y - cell.last_total_grad.y);
+            n++;
         }
-        coord_dist = std::sqrt(coord_dist / (2 * float(mcells.size())));
-        grad_dist = std::sqrt(grad_dist / (2 * float(mcells.size())));
+        coord_dist = std::sqrt(coord_dist / (2 * float(n)));
+        grad_dist = std::sqrt(grad_dist / (2 * float(n)));
         log_info("coord_dist: %f grad_dist: %f\n", coord_dist, grad_dist);
         return coord_dist / grad_dist;
         // return 0.1;
@@ -969,7 +973,7 @@ class StaticPlacer
             update_gradients(true, true, /* init_penalty */ true);
             // compute a "fake" previous position based on an arbitrary steplength and said gradients for nesterov
             for (auto &cell : mcells) {
-                if (cell.is_fixed)
+                if (cell.is_fixed || cell.is_dark)
                     continue;
                 // save current position in last_pos
                 cell.last_pos = cell.pos;
@@ -981,6 +985,8 @@ class StaticPlacer
             update_gradients(true);
             // Now we have the fake previous state in the current state
             for (auto &cell : mcells) {
+                if (cell.is_fixed || cell.is_dark)
+                    continue;
                 std::swap(cell.last_ref_pos, cell.ref_pos);
                 std::swap(cell.ref_total_grad, cell.last_total_grad);
                 std::swap(cell.ref_wl_grad, cell.last_wl_grad);

From 89e3b7d23d7fc403b35205540cf9ac9e8243c8eb Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 3 May 2024 09:39:24 +0200
Subject: [PATCH 601/712] static: Fix float overflow issue

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 65116eedcc..c9b5364c74 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -792,15 +792,15 @@ class StaticPlacer
             auto &pd = nd.ports.at(port.second.type == PORT_OUT ? (nd.ports.size() - 1) : port.second.user_idx.idx());
             // From Replace
             // TODO: check these derivatives on paper
-            float d_min = 0, d_max = 0;
+            double d_min = 0, d_max = 0;
             if (pd.has_min_exp(axis)) {
-                float min_sum = nd.min_exp.at(axis), x_min_sum = nd.x_min_exp.at(axis);
+                double min_sum = nd.min_exp.at(axis), x_min_sum = nd.x_min_exp.at(axis);
                 d_min = (min_sum * (pd.min_exp.at(axis) * (1.0f - wl_coeff.at(axis) * loc.at(axis))) +
                          wl_coeff.at(axis) * pd.min_exp.at(axis) * x_min_sum) /
                         (min_sum * min_sum);
             }
             if (pd.has_max_exp(axis)) {
-                float max_sum = nd.max_exp.at(axis), x_max_sum = nd.x_max_exp.at(axis);
+                double max_sum = nd.max_exp.at(axis), x_max_sum = nd.x_max_exp.at(axis);
                 d_max = (max_sum * (pd.max_exp.at(axis) * (1.0f + wl_coeff.at(axis) * loc.at(axis))) -
                          wl_coeff.at(axis) * pd.max_exp.at(axis) * x_max_sum) /
                         (max_sum * max_sum);

From 3f2451f8d78c88e299cb421539add41eadae17bf Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 3 May 2024 09:50:40 +0200
Subject: [PATCH 602/712] static: Guard density CSV dumps behind a flag

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/command.cc      | 7 +++++++
 common/place/placer_static.cc | 5 ++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 44482946c6..d6d451f525 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -389,6 +389,9 @@ po::options_description CommandHandler::getGeneralOptions()
                           "allow placer to attempt up to max(10000, total cells^2 / N) iterations to place a cell (int "
                           "N, default: 8, 0 for no timeout)");
 
+    general.add_options()("static-dump-density", "write density csv files during placer-static flow");
+
+
 #if !defined(NPNR_DISABLE_THREADS)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
 #endif
@@ -543,6 +546,10 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("router2-alt-weights"))
         ctx->settings[ctx->id("router2/alt-weights")] = true;
 
+    if (vm.count("static-dump-density"))
+        ctx->settings[ctx->id("static/dump_density")] = true;
+
+
     // Setting default values
     if (ctx->settings.find(ctx->id("target_freq")) == ctx->settings.end())
         ctx->settings[ctx->id("target_freq")] = std::to_string(12e6);
diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index c9b5364c74..0466902c4b 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -254,6 +254,7 @@ class StaticPlacer
     int width, height;
     int iter = 0;
     bool fft_debug = false;
+    bool dump_density = false;
 
     // legalisation queue
     std::priority_queue<std::pair<int, IdString>> to_legalise;
@@ -658,7 +659,8 @@ class StaticPlacer
             if (!overlap_str.empty())
                 overlap_str += ", ";
             overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap * 100);
-            g.conc_density.write_csv(stringf("out_conc_density_%d_%d.csv", iter, idx));
+            if (dump_density)
+                g.conc_density.write_csv(stringf("out_conc_density_%d_%d.csv", iter, idx));
         }
         log_info("overlap: %s\n", overlap_str.c_str());
     }
@@ -1387,6 +1389,7 @@ class StaticPlacer
         groups.resize(cfg.cell_groups.size());
         tmg.setup_only = true;
         tmg.setup();
+        dump_density = ctx->setting<bool>("static/dump_density", false);
     };
     void place()
     {

From 0dc4bcb20312db5676f87285d9244e7b34918b33 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 3 May 2024 11:52:59 +0200
Subject: [PATCH 603/712] Format utlilisation for larger FPGA as well

---
 common/kernel/design_utils.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/design_utils.cc b/common/kernel/design_utils.cc
index f52cc30485..cd7063cd34 100644
--- a/common/kernel/design_utils.cc
+++ b/common/kernel/design_utils.cc
@@ -44,7 +44,7 @@ void print_utilisation(const Context *ctx)
     for (auto type : available_types) {
         IdString type_id = type.first;
         int used_bels = get_or_default(used_types, type.first, 0);
-        log_info("\t%20s: %5d/%5d %5d%%\n", type_id.c_str(ctx), used_bels, type.second, 100 * used_bels / type.second);
+        log_info("\t%20s: %7d/%7d %5d%%\n", type_id.c_str(ctx), used_bels, type.second, 100 * used_bels / type.second);
     }
     log_break();
 }

From f99346ba61290ac184ca781023ad131430485f55 Mon Sep 17 00:00:00 2001
From: gmanricks <contact@lushaylabs.com>
Date: Sat, 20 Apr 2024 14:51:21 +0300
Subject: [PATCH 604/712] fix for windows path

---
 common/kernel/command.cc        |  2 +-
 himbaechel/arch.cc              |  9 ++++++++-
 himbaechel/uarch/gowin/gowin.cc | 12 +++++++++++-
 3 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index d6d451f525..dc178cd2a1 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -197,7 +197,7 @@ void init_share_dirname()
         npnr_share_dirname = proc_share_path;
         return;
     }
-    proc_share_path = proc_self_path + "..\\share\\";
+    proc_share_path = proc_self_path + "..\\share\\" + "nextpnr\\";
     if (check_file_exists(proc_share_path, true)) {
         npnr_share_dirname = proc_share_path;
         return;
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 1270934e02..0262548b95 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -61,8 +61,15 @@ void Arch::load_chipdb(const std::string &path)
     if (!args.chipdb_override.empty()) {
         db_path = args.chipdb_override;
     } else {
+        std::string separator;
+#if defined(_WIN32)
+        separator = "\\";
+#else
+        separator = "/";
+#endif
         db_path = proc_share_dirname();
-        db_path += "/himbaechel/";
+        db_path += "himbaechel";
+        db_path += separator;
         db_path += path;
     }
     try {
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 751f1865b0..fdac5ed17f 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -128,7 +128,17 @@ void GowinImpl::init_database(Arch *arch)
         }
     }
 
-    arch->load_chipdb(stringf("gowin/chipdb-%s.bin", family.c_str()));
+    char separator;
+#if defined(_WIN32)
+    separator = '\\';
+#else
+    separator = '/';
+#endif
+    arch->load_chipdb(stringf(
+        "gowin%cchipdb-%s.bin",
+        separator,
+        family.c_str()
+    ));
 
     // These fields go in the header of the output JSON file and can help
     // gowin_pack support different architectures

From eb0554319f8e6de58f21dad9ab122fa327208b4f Mon Sep 17 00:00:00 2001
From: gmanricks <contact@lushaylabs.com>
Date: Mon, 22 Apr 2024 00:12:43 +0300
Subject: [PATCH 605/712] use boost for windows path

---
 himbaechel/arch.cc              | 12 ++++--------
 himbaechel/uarch/gowin/gowin.cc | 12 +-----------
 2 files changed, 5 insertions(+), 19 deletions(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 0262548b95..3cbe2b1e93 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -22,6 +22,7 @@
 #include "chipdb.h"
 #include "log.h"
 #include "nextpnr.h"
+#include <boost/filesystem/convenience.hpp>
 
 #include "command.h"
 #include "placer1.h"
@@ -61,16 +62,11 @@ void Arch::load_chipdb(const std::string &path)
     if (!args.chipdb_override.empty()) {
         db_path = args.chipdb_override;
     } else {
-        std::string separator;
-#if defined(_WIN32)
-        separator = "\\";
-#else
-        separator = "/";
-#endif
         db_path = proc_share_dirname();
-        db_path += "himbaechel";
-        db_path += separator;
+        db_path += "himbaechel/";
         db_path += path;
+        boost::filesystem::path p(db_path);
+        db_path = p.make_preferred().string();
     }
     try {
         blob_file.open(db_path);
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index fdac5ed17f..751f1865b0 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -128,17 +128,7 @@ void GowinImpl::init_database(Arch *arch)
         }
     }
 
-    char separator;
-#if defined(_WIN32)
-    separator = '\\';
-#else
-    separator = '/';
-#endif
-    arch->load_chipdb(stringf(
-        "gowin%cchipdb-%s.bin",
-        separator,
-        family.c_str()
-    ));
+    arch->load_chipdb(stringf("gowin/chipdb-%s.bin", family.c_str()));
 
     // These fields go in the header of the output JSON file and can help
     // gowin_pack support different architectures

From 09703c7f352256d665833f8f65a5c373f0d850d2 Mon Sep 17 00:00:00 2001
From: gmanricks <contact@lushaylabs.com>
Date: Fri, 3 May 2024 13:14:34 +0300
Subject: [PATCH 606/712] update import to boost

---
 himbaechel/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 3cbe2b1e93..044b1a6c0f 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -22,7 +22,7 @@
 #include "chipdb.h"
 #include "log.h"
 #include "nextpnr.h"
-#include <boost/filesystem/convenience.hpp>
+#include <boost/filesystem/path.hpp>
 
 #include "command.h"
 #include "placer1.h"

From 423f1b7159e39bf6995c773042868422d8531e48 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 8 May 2024 09:53:28 +0200
Subject: [PATCH 607/712] static: Make bin stamping more consistent

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 0466902c4b..d47429c2e2 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -587,8 +587,8 @@ class StaticPlacer
             height = bin_h;
         }
 
-        double x0 = pos.x - (width / 2), x1 = pos.x + (width / 2);
-        double y0 = pos.y - (height / 2), y1 = pos.y + (height / 2);
+        double x0 = pos.x, x1 = pos.x + width;
+        double y0 = pos.y, y1 = pos.y + height;
         for (int y = int(y0 / bin_h); y <= int(y1 / bin_h); y++) {
             for (int x = int(x0 / bin_w); x <= int(x1 / bin_w); x++) {
                 int xb = std::max(0, std::min(x, m - 1));
@@ -1043,7 +1043,11 @@ class StaticPlacer
     {
         // TODO: update penalties; wirelength factor; etc
         steplen = get_steplen();
-        log_info("iter=%d steplen=%f a=%f\n", iter, steplen, nesterov_a);
+        std::string penalty_str = "";
+        for (auto p : dens_penalty) {
+            penalty_str += stringf("%s%.2f", penalty_str.empty() ? "" : ", ", p);
+        }
+        log_info("iter=%d steplen=%f a=%f penalty=[%s]\n", iter, steplen, nesterov_a, penalty_str.c_str());
         float a_next = (1.0f + std::sqrt(4.0f * nesterov_a * nesterov_a + 1)) / 2.0f;
         // Update positions using Nesterov's
         for (auto &cell : mcells) {

From 59a29e5f420a2d4ad598aa1ac81fa62cc96f138e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 May 2024 14:27:54 +0200
Subject: [PATCH 608/712] nexus: Use a toposort when preplacing clock
 primitives

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/pack.cc | 50 +++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/nexus/pack.cc b/nexus/pack.cc
index 9991d49de8..75ceb30959 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -916,19 +916,47 @@ struct NexusPacker
     {
         // Keep running until we reach a fixed point
         log_info("Placing globals...\n");
-        bool did_something = true;
-        while (did_something) {
-            did_something = false;
-            for (auto &cell : ctx->cells) {
-                CellInfo *ci = cell.second.get();
-                if (ci->type == id_OSC_CORE)
-                    did_something |= preplace_singleton(ci);
-                else if (ci->type == id_DCC)
-                    did_something |= preplace_prim(ci, id_CLKI, false);
-                else if (ci->type == id_PLL_CORE)
-                    did_something |= preplace_prim(ci, id_REFCK, false);
+        TopoSort<IdString> sorter;
+        auto is_glb_cell = [&](const CellInfo *cell) {
+            return cell->type.in(id_OSC_CORE, id_DCC, id_PLL_CORE, id_DCS);
+        };
+
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (is_glb_cell(ci)) {
+                sorter.node(ci->name);
+
+                auto do_pin = [&](IdString pin) {
+                    NetInfo *net = ci->getPort(pin);
+                    if (!net || !net->driver.cell || !is_glb_cell(net->driver.cell))
+                        return;
+                    sorter.edge(net->driver.cell->name, ci->name);
+                };
+
+                if (ci->type == id_PLL_CORE) {
+                    do_pin(id_REFCK);
+                } else if (ci->type == id_DCC) {
+                    do_pin(id_CLKI);
+                } else if (ci->type == id_DCS) {
+                    do_pin(id_CLK0);
+                    do_pin(id_CLK1);
+                }
             }
         }
+
+        sorter.sort();
+
+        for (IdString cell_name : sorter.sorted) {
+            CellInfo *ci = ctx->cells.at(cell_name).get();
+            if (ci->type == id_OSC_CORE)
+                preplace_singleton(ci);
+            else if (ci->type == id_DCC)
+                preplace_prim(ci, id_CLKI, false);
+            else if (ci->type == id_PLL_CORE)
+                preplace_prim(ci, id_REFCK, false);
+            else if (ci->type == id_DCS)
+                preplace_prim(ci, id_CLK0, false);
+        }
     }
 
     // Get a bus port name

From b7f91e57a0caf40dd23e3bada52c8595d53eb625 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 16 May 2024 14:42:09 +0200
Subject: [PATCH 609/712] Update cached Yosys in CI

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/workflows/arch_ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/arch_ci.yml b/.github/workflows/arch_ci.yml
index cc4bc44eb9..d428fc8027 100644
--- a/.github/workflows/arch_ci.yml
+++ b/.github/workflows/arch_ci.yml
@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
     env:
       DEPS_PATH: ${{ github.workspace }}/deps
-      YOSYS_REVISION: bd7ee79486d4e8788f36de8c25a3fb2df451d682
+      YOSYS_REVISION: 7045cf509e1d95cbc973746674cf2d7c73c02e50
       ICESTORM_REVISION: 9f66f9ce16941c6417813cb87653c735a78b53ae
       TRELLIS_REVISION: 36c615d1740473cc3574464c7f0bed44da20e5b6
       PRJOXIDE_REVISION: c3fb1526cf4a2165e15b74f4a994d153c7695fe4

From 61cc5259d9314c1d890365d9394a6e456aecd88f Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 12 Jun 2024 16:11:18 +0200
Subject: [PATCH 610/712] prefine: Add shared lock around bel availability
 checks

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/parallel_refine.cc | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index dab45eba92..2cf1996ba5 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -69,7 +69,13 @@ struct ThreadState : DetailPlacerThreadState
     {
         NPNR_ASSERT(moved_cells.empty());
         BelId old_bel = cell->bel;
-        CellInfo *bound = ctx->getBoundBelCell(new_bel);
+        CellInfo *bound = nullptr;
+        {
+            #if !defined(NPNR_DISABLE_THREADS)
+                std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+            #endif
+            bound = ctx->getBoundBelCell(new_bel);
+        }
         if (bound && (bound->belStrength > STRENGTH_STRONG || bound->cluster != ClusterId()))
             return false;
         if (!add_to_move(cell, old_bel, new_bel))
@@ -119,8 +125,13 @@ struct ThreadState : DetailPlacerThreadState
                 if (used_bels.count(db.second))
                     goto fail;
                 used_bels.insert(db.second);
-
-                CellInfo *bound = ctx->getBoundBelCell(db.second);
+                CellInfo *bound = nullptr;
+                {
+                    #if !defined(NPNR_DISABLE_THREADS)
+                        std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+                    #endif
+                    bound = ctx->getBoundBelCell(db.second);
+                }
                 if (bound) {
                     if (moved_cells.count(bound->name)) {
                         // Don't move a cell multiple times in the same go
@@ -146,8 +157,16 @@ struct ThreadState : DetailPlacerThreadState
                         if (!add_to_move(bound, bound->bel, old_bel))
                             goto fail;
                     }
-                } else if (!ctx->checkBelAvail(db.second)) {
-                    goto fail;
+                } else {
+                    bool avail = false;
+                    {
+                        #if !defined(NPNR_DISABLE_THREADS)
+                            std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+                        #endif
+                        avail = ctx->checkBelAvail(db.second);
+                    }
+                    if (!avail)
+                        goto fail;
                 }
             }
         }

From 945cf48c6cd1579c541ef1c26ced134ea6393bd9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 15 May 2024 09:07:38 +0200
Subject: [PATCH 611/712] static: Various convergence improvements for ECP5

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 184 +++++++++++++++++++++++-----------
 1 file changed, 126 insertions(+), 58 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index d47429c2e2..11e4b4ee84 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -56,6 +56,7 @@ namespace {
 
 struct PlacerGroup
 {
+    bool enabled = true;
     int total_bels = 0;
     double concrete_area = 0;
     double dark_area = 0;
@@ -70,6 +71,9 @@ struct PlacerGroup
     FFTArray density_fft;
     FFTArray electro_phi;
     FFTArray electro_fx, electro_fy;
+
+    double init_potential = 0;
+    double curr_potential = 0;
 };
 
 // Could be an actual concrete netlist cell; or just a spacer
@@ -301,7 +305,7 @@ class StaticPlacer
         dict<IdString, int> beltype2group;
         for (int i = 0; i < int(groups.size()); i++) {
             groups.at(i).loc_area.reset(width, height);
-            for (const auto &bel_type : cfg.cell_groups.at(i).cell_area)
+            for (const auto &bel_type : cfg.cell_groups.at(i).bel_area)
                 beltype2group[bel_type.first] = i;
         }
         for (auto bel : ctx->getBels()) {
@@ -409,14 +413,16 @@ class StaticPlacer
             StaticRect rect;
             // Mismatched group case
             if (!lookup_group(ci->type, cell_group, rect)) {
-                for (auto bel : ctx->getBels()) {
-                    if (ctx->isValidBelForCellType(ci->type, bel) && ctx->checkBelAvail(bel)) {
-                        ctx->bindBel(bel, ci, STRENGTH_STRONG);
-                        if (!ctx->isBelLocationValid(bel)) {
-                            ctx->unbindBel(bel);
-                        } else {
-                            log_info("    placed potpourri cell '%s' at bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
-                            break;
+                if (ci->bel == BelId()) {
+                    for (auto bel : ctx->getBels()) {
+                        if (ctx->isValidBelForCellType(ci->type, bel) && ctx->checkBelAvail(bel)) {
+                            ctx->bindBel(bel, ci, STRENGTH_STRONG);
+                            if (!ctx->isBelLocationValid(bel)) {
+                                ctx->unbindBel(bel);
+                            } else {
+                                log_info("    placed potpourri cell '%s' at bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
+                                break;
+                            }
                         }
                     }
                 }
@@ -506,26 +512,31 @@ class StaticPlacer
         }
     }
 
-    const double target_util = 0.8;
+    const double target_util = 0.7;
 
     void insert_dark()
     {
         log_info("⌁ inserting dark nodes...\n");
         for (int group = 0; group < int(groups.size()); group++) {
+            const auto &cg = cfg.cell_groups.at(group);
             auto &g = groups.at(group);
+            int dark_count = 0;
             for (auto tile : g.loc_area) {
                 if (tile.value > 0.5f)
                     continue;
                 StaticRect dark_area(1.0f, 1.0f - tile.value);
-                int cell_idx = add_cell(dark_area, group, RealPair(tile.x + 0.5f, tile.y + 0.5f), nullptr /*spacer*/);
+                int cell_idx = add_cell(dark_area, group, RealPair(tile.x, tile.y), nullptr /*spacer*/);
                 mcells.at(cell_idx).is_dark = true;
+                ++dark_count;
             }
+            log_info("⌁   group %s inserted a total of %d dark nodes\n", ctx->nameOf(cg.name), dark_count);
         }
     }
 
     void insert_spacer()
     {
         log_info("⌁ inserting spacers...\n");
+
         int inserted_spacers = 0;
         for (int group = 0; group < int(groups.size()); group++) {
             const auto &cg = cfg.cell_groups.at(group);
@@ -537,8 +548,13 @@ class StaticPlacer
             int spacer_count = (g.total_area * target_util - g.concrete_area) / cg.spacer_rect.area();
             if (spacer_count <= 0)
                 continue;
-            for (int i = 0; i < spacer_count; i++) {
-                add_cell(cg.spacer_rect, group, RealPair(ctx->rngf(width), ctx->rngf(height)), nullptr /*spacer*/);
+            while (inserted_spacers < spacer_count) {
+                int x = ctx->rng(width);
+                int y = ctx->rng(height);
+                // avoid placing spacers at locations with dark nodes
+                if (ctx->rngf(1.0) > g.loc_area.at(x, y))
+                    continue;
+                add_cell(cg.spacer_rect, group, RealPair(x + ctx->rngf(1.0), y + ctx->rngf(1.0)), nullptr /*spacer*/);
                 ++inserted_spacers;
             }
         }
@@ -556,7 +572,7 @@ class StaticPlacer
     {
         // TODO: a m x m grid follows the paper and makes the DCTs easier, but is it actually ideal for non-square
         // FPGAs?
-        m = 1 << int(std::ceil(std::log2(std::sqrt(mcells.size() / groups.size()))));
+        m = 1 << int(std::ceil(std::log2(std::max(width, height))));
         bin_w = double(width) / m;
         bin_h = double(height) / m;
 
@@ -591,18 +607,18 @@ class StaticPlacer
         double y0 = pos.y, y1 = pos.y + height;
         for (int y = int(y0 / bin_h); y <= int(y1 / bin_h); y++) {
             for (int x = int(x0 / bin_w); x <= int(x1 / bin_w); x++) {
-                int xb = std::max(0, std::min(x, m - 1));
-                int yb = std::max(0, std::min(y, m - 1));
+                if (x < 0 || x >= m || y < 0 || y >= m)
+                    continue;
                 double slither_w = 1.0, slither_h = 1.0;
-                if (yb == int(y0 / bin_h)) // y slithers
-                    slither_h = ((yb + 1) * bin_h) - y0;
-                else if (yb == int(y1 / bin_h))
-                    slither_h = (y1 - yb * bin_h);
-                if (xb == int(x0 / bin_w)) // x slithers
-                    slither_w = ((xb + 1) * bin_w) - x0;
-                else if (xb == int(x1 / bin_w))
-                    slither_w = (x1 - xb * bin_w);
-                func(xb, yb, scaled_density * slither_w * slither_h);
+                if (y == int(y0 / bin_h)) // y slithers
+                    slither_h = ((y + 1) * bin_h) - y0;
+                else if (y == int(y1 / bin_h))
+                    slither_h = (y1 - y * bin_h);
+                if (x == int(x0 / bin_w)) // x slithers
+                    slither_w = ((x + 1) * bin_w) - x0;
+                else if (x == int(x1 / bin_w))
+                    slither_w = (x1 - x * bin_w);
+                func(x, y, scaled_density * slither_w * slither_h);
             }
         }
     };
@@ -626,11 +642,10 @@ class StaticPlacer
         }
     }
 
-    void compute_overlap()
+    void compute_conc_density()
     {
-        // populate for concrete cells only
         for (auto &g : groups)
-            g.conc_density.reset(m, m, 0);
+            g.conc_density.reset(width, height, 0);
         for (int idx = 0; idx < int(ccells.size()); idx++) {
             auto &mc = mcells.at(idx);
             auto &g = groups.at(mc.group);
@@ -641,10 +656,18 @@ class StaticPlacer
                 for (int dx = 0; dx <= int(size.w); dx++) {
                     float h = (dy == int(size.h)) ? (size.h - int(size.h)) : 1;
                     float w = (dx == int(size.w)) ? (size.w - int(size.w)) : 1;
-                    g.conc_density.at(loc.x + dx, loc.y + dy) += w * h;
+                    if ((loc.x + dx) >= 0 && (loc.x + dx) < width && (loc.y + dy) >= 0 && (loc.y + dy) < height)
+                        g.conc_density.at(loc.x + dx, loc.y + dy) += w * h;
                 }
             }
         }
+    }
+
+    void compute_overlap()
+    {
+        // populate for concrete cells only
+        compute_conc_density();
+
         std::string overlap_str = "";
         for (int idx = 0; idx < int(groups.size()); idx++) {
             auto &g = groups.at(idx);
@@ -671,7 +694,7 @@ class StaticPlacer
         auto &g = groups.at(group);
         for (auto entry : g.density)
             g.density_fft.at(entry.x, entry.y) = entry.value;
-        if (fft_debug)
+        if (fft_debug || dump_density)
             g.density_fft.write_csv(stringf("out_bin_density_%d_%d.csv", iter, group));
         // Based on
         // https://github.com/ALIGN-analoglayout/ALIGN-public/blob/master/PlaceRouteHierFlow/EA_placer/FFT/fft.cpp
@@ -736,7 +759,7 @@ class StaticPlacer
 
     void update_nets(bool ref)
     {
-        static constexpr float min_wirelen_force = -300.f;
+        static constexpr float min_wirelen_force = -3000.f;
         pool.run(2 * nets.size(), [&](int i) {
             auto &net = nets.at(i / 2);
             auto axis = (i % 2) ? Axis::Y : Axis::X;
@@ -868,28 +891,17 @@ class StaticPlacer
         }
         if (init_penalty) {
             // set initial density penalty
-            dict<int, float> wirelen_sum;
-            dict<int, float> force_sum;
-            for (auto &cell : ctx->cells) {
-                CellInfo *ci = cell.second.get();
-                if (ci->udata == -1)
-                    continue;
-                auto &mc = mcells.at(ci->udata);
-                auto res1 = wirelen_sum.insert({mc.group, std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y)});
-                if (!res1.second)
-                    res1.first->second += std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y);
-                auto res2 = force_sum.insert({mc.group, std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y)});
-                if (!res2.second)
-                    res2.first->second += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
-            }
-            dens_penalty = std::vector<float>(wirelen_sum.size(), 0.0);
-            for (auto &item : wirelen_sum) {
-                auto group = item.first;
-                auto wirelen = item.second;
-                dens_penalty[group] = wirelen / force_sum.at(group);
-                log_info(" initial density penalty for %s: %f\n", cfg.cell_groups.at(group).name.c_str(ctx),
-                         dens_penalty[group]);
+            double wirelen_sum = 0, force_sum = 0;
+            for (int i = 0; i < int(ccells.size()); i++) {
+                auto mc = mcells.at(i);
+                wirelen_sum += std::abs(mc.ref_wl_grad.x) + std::abs(mc.ref_wl_grad.y);
+                force_sum += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
             }
+            const float eta = 1e-1;
+            float init_dens_penalty = eta * (wirelen_sum / force_sum); 
+            log_info("initial density penalty: %f\n", init_dens_penalty);
+            dens_penalty.resize(groups.size(), init_dens_penalty);
+            update_potentials(true); // set initial potential
         }
         // Third loop: compute total gradient, and precondition
         // TODO: ALM as well as simple penalty
@@ -953,17 +965,59 @@ class StaticPlacer
         return hpwl;
     }
 
-    float system_potential()
+    void update_potentials(bool init = false)
     {
-        float pot = 0;
+        for (auto &group : groups)
+            group.curr_potential = 0;
         for (auto &cell : mcells) {
             auto &g = groups.at(cell.group);
             iter_slithers(cell.ref_pos, cell.rect,
-                          [&](int x, int y, float area) { pot += g.electro_phi.at(x, y) * area; });
+                          [&](int x, int y, float area) { g.curr_potential += g.electro_phi.at(x, y) * area; });
         }
+        if (init) {
+            for (auto &group : groups)
+                group.init_potential = group.curr_potential;
+        }
+    }
+
+    float system_potential()
+    {
+        float pot = 0;
+        for (auto &group : groups)
+            pot += group.curr_potential;
         return pot;
     }
 
+    float penalty_beta = 2.0e3f;
+    float alpha_l = 1.05f, alpha_h = 1.06f;
+    double penalty_incr = alpha_h - 1;
+    void update_penalties() {
+        float pot_norm = 0;
+        // compute L2-norm of relative system potential
+        std::vector<float> rel_pot;
+        for (int g = 0; g < int(groups.size()); g++) {
+            auto &group = groups.at(g);
+            if (!group.enabled)
+               continue;
+            float phi_hat = group.curr_potential / group.init_potential;
+            rel_pot.push_back(phi_hat);
+            pot_norm += phi_hat * phi_hat;
+        }
+        pot_norm = sqrt(pot_norm);
+        log_info("pot_norm: %f\n", pot_norm);
+        // update penalty multiplier (ELFPlace equation 22)
+        double log_term = std::log(penalty_beta * pot_norm + 1);
+        penalty_incr = penalty_incr * ((log_term  / (log_term + 1)) * (alpha_h - alpha_l) + alpha_l);
+        // update density penalties (ELFPlace equation 21)
+        for (int g = 0; g < int(groups.size()); g++) {
+            if (!groups.at(g).enabled)
+                 continue;
+            float next_penalty = dens_penalty.at(g) + (penalty_incr * (rel_pot.at(g) / pot_norm));
+            dens_penalty.at(g) = next_penalty;
+        }
+    }
+
+
     void initialise()
     {
         float initial_steplength = 0.01f;
@@ -1016,6 +1070,7 @@ class StaticPlacer
         // Move the post-solve position of a chain towards be the weighted average of its constituents
         // The strength increases with iterations
         float alpha = std::min<float>(std::pow(1.002f, iter) - 1, 1.0f);
+        float dist = 0;
         for (int i = 0; i < int(macros.size()); i++) {
             auto &macro = macros.at(i);
             float total_area = 0;
@@ -1033,10 +1088,13 @@ class StaticPlacer
             for (int c : macro.conc_cells) {
                 auto &cc = ccells.at(c);
                 auto &mc = mcells.at(c);
+                auto last_pos = mc.pos;
                 mc.pos = mc.pos * (1 - alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
                 mc.ref_pos = mc.ref_pos * (1 - alpha) + (ref_pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha;
+                dist += std::sqrt(std::pow(last_pos.x - mc.pos.x, 2) + std::pow(last_pos.y - mc.pos.y, 2));
             }
         }
+        log_info("   update_chains distance %.2f\n", dist);
     }
 
     void step()
@@ -1064,9 +1122,10 @@ class StaticPlacer
         nesterov_a = a_next;
         update_chains();
         update_gradients(true);
+        update_potentials();
         log_info("   system potential: %f hpwl: %f\n", system_potential(), system_hpwl());
         compute_overlap();
-        if ((iter % 5) == 0)
+        if ((iter % 10) == 0)
             update_timing();
     }
 
@@ -1410,8 +1469,15 @@ class StaticPlacer
         bool legalised_ip = false;
         while (true) {
             step();
-            for (auto &penalty : dens_penalty)
-                penalty *= 1.025;
+            for (auto &p : dens_penalty)
+                if (p < 50.0)
+                    p *= 1.025;
+                else
+                    p += 1.0;
+            // wl_coeff.at(Axis::X) = std::max(0.005, 0.995 * wl_coeff.at(Axis::X));
+            // wl_coeff.at(Axis::Y) = std::max(0.005, 0.995 * wl_coeff.at(Axis::Y));
+
+            // update_penalties();
             if (!legalised_ip) {
                 float ip_overlap = 0;
                 for (int i = cfg.logic_groups; i < int(groups.size()); i++)
@@ -1419,6 +1485,8 @@ class StaticPlacer
                 if (ip_overlap < 0.15) {
                     legalise_step(true);
                     legalised_ip = true;
+                    for (int i = cfg.logic_groups; i < int(groups.size()); i++)
+                        groups.at(i).enabled = false;
                 }
             } else {
                 float logic_overlap = 0;

From c89037db49ff0597adc8734f68b04df7abc94d63 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 18 Jun 2024 13:53:42 +0200
Subject: [PATCH 612/712] static: Speedup with parallel wirelength gradient
 computation

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_static.cc | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 11e4b4ee84..c307b19c15 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -801,6 +801,8 @@ class StaticPlacer
         });
     }
 
+    std::vector<std::pair<CellInfo *, RealPair>> gathered_wirelen_grad;
+
     float wirelen_grad(CellInfo *cell, Axis axis, bool ref)
     {
         float gradient = 0;
@@ -878,16 +880,26 @@ class StaticPlacer
             // total gradient computed at the end
             (ref ? cell.ref_total_grad : cell.total_grad) = RealPair(0, 0);
         }
-        // Second loop: sum up wirelength gradients across concrete cell instances
-        for (auto &cell : ctx->cells) {
-            CellInfo *ci = cell.second.get();
-            if (ci->udata == -1)
-                continue;
-            auto &mc = mcells.at(ci->udata);
-            // TODO: exploit parallelism across axes
+        if (gathered_wirelen_grad.empty()) {
+            for (auto &cell : ctx->cells) {
+                CellInfo *ci = cell.second.get();
+                if (ci->udata == -1)
+                    continue;
+                gathered_wirelen_grad.emplace_back(ci, RealPair());
+            }
+        }
+        // Compute wirelength gradients for cells in parallel, this is a slow part
+        pool.run(gathered_wirelen_grad.size(), [&](int i) {
+            auto &entry = gathered_wirelen_grad.at(i);
+            CellInfo *ci = entry.first;
             float wl_gx = wirelen_grad(ci, Axis::X, ref);
             float wl_gy = wirelen_grad(ci, Axis::Y, ref);
-            (ref ? mc.ref_wl_grad : mc.wl_grad) += RealPair(wl_gx, wl_gy);
+            entry.second = RealPair(wl_gx, wl_gy);
+        });
+        // Second loop: sum up wirelength gradients across concrete cell instances
+        for (auto entry : gathered_wirelen_grad) {
+            auto &mc = mcells.at(entry.first->udata);
+            (ref ? mc.ref_wl_grad : mc.wl_grad) += entry.second;
         }
         if (init_penalty) {
             // set initial density penalty

From a29a17f8f24158b31a9272d55f48cd46d7db50fa Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 18 Jun 2024 13:54:12 +0200
Subject: [PATCH 613/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/command.cc         |  2 --
 common/place/parallel_refine.cc  | 18 +++++++++---------
 common/place/placer_static.cc    | 18 ++++++++++--------
 ecp5/bitstream.cc                |  2 +-
 ecp5/gfx.cc                      |  4 ++--
 generic/viaduct/fabulous/fasm.cc |  2 +-
 gui/lineshader.h                 |  2 +-
 himbaechel/arch.cc               |  2 +-
 8 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index dc178cd2a1..9b8f8616b7 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -391,7 +391,6 @@ po::options_description CommandHandler::getGeneralOptions()
 
     general.add_options()("static-dump-density", "write density csv files during placer-static flow");
 
-
 #if !defined(NPNR_DISABLE_THREADS)
     general.add_options()("parallel-refine", "use new experimental parallelised engine for placement refinement");
 #endif
@@ -549,7 +548,6 @@ void CommandHandler::setupContext(Context *ctx)
     if (vm.count("static-dump-density"))
         ctx->settings[ctx->id("static/dump_density")] = true;
 
-
     // Setting default values
     if (ctx->settings.find(ctx->id("target_freq")) == ctx->settings.end())
         ctx->settings[ctx->id("target_freq")] = std::to_string(12e6);
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index 2cf1996ba5..5712462965 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -71,9 +71,9 @@ struct ThreadState : DetailPlacerThreadState
         BelId old_bel = cell->bel;
         CellInfo *bound = nullptr;
         {
-            #if !defined(NPNR_DISABLE_THREADS)
-                std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-            #endif
+#if !defined(NPNR_DISABLE_THREADS)
+            std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
             bound = ctx->getBoundBelCell(new_bel);
         }
         if (bound && (bound->belStrength > STRENGTH_STRONG || bound->cluster != ClusterId()))
@@ -127,9 +127,9 @@ struct ThreadState : DetailPlacerThreadState
                 used_bels.insert(db.second);
                 CellInfo *bound = nullptr;
                 {
-                    #if !defined(NPNR_DISABLE_THREADS)
-                        std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-                    #endif
+#if !defined(NPNR_DISABLE_THREADS)
+                    std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
                     bound = ctx->getBoundBelCell(db.second);
                 }
                 if (bound) {
@@ -160,9 +160,9 @@ struct ThreadState : DetailPlacerThreadState
                 } else {
                     bool avail = false;
                     {
-                        #if !defined(NPNR_DISABLE_THREADS)
-                            std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
-                        #endif
+#if !defined(NPNR_DISABLE_THREADS)
+                        std::shared_lock<std::shared_timed_mutex> l(g.archapi_mutex);
+#endif
                         avail = ctx->checkBelAvail(db.second);
                     }
                     if (!avail)
diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index c307b19c15..e75ccfb8f1 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -420,7 +420,8 @@ class StaticPlacer
                             if (!ctx->isBelLocationValid(bel)) {
                                 ctx->unbindBel(bel);
                             } else {
-                                log_info("    placed potpourri cell '%s' at bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
+                                log_info("    placed potpourri cell '%s' at bel '%s'\n", ctx->nameOf(ci),
+                                         ctx->nameOfBel(bel));
                                 break;
                             }
                         }
@@ -910,7 +911,7 @@ class StaticPlacer
                 force_sum += std::abs(mc.ref_dens_grad.x) + std::abs(mc.ref_dens_grad.y);
             }
             const float eta = 1e-1;
-            float init_dens_penalty = eta * (wirelen_sum / force_sum); 
+            float init_dens_penalty = eta * (wirelen_sum / force_sum);
             log_info("initial density penalty: %f\n", init_dens_penalty);
             dens_penalty.resize(groups.size(), init_dens_penalty);
             update_potentials(true); // set initial potential
@@ -1003,14 +1004,15 @@ class StaticPlacer
     float penalty_beta = 2.0e3f;
     float alpha_l = 1.05f, alpha_h = 1.06f;
     double penalty_incr = alpha_h - 1;
-    void update_penalties() {
+    void update_penalties()
+    {
         float pot_norm = 0;
         // compute L2-norm of relative system potential
         std::vector<float> rel_pot;
         for (int g = 0; g < int(groups.size()); g++) {
             auto &group = groups.at(g);
             if (!group.enabled)
-               continue;
+                continue;
             float phi_hat = group.curr_potential / group.init_potential;
             rel_pot.push_back(phi_hat);
             pot_norm += phi_hat * phi_hat;
@@ -1019,17 +1021,16 @@ class StaticPlacer
         log_info("pot_norm: %f\n", pot_norm);
         // update penalty multiplier (ELFPlace equation 22)
         double log_term = std::log(penalty_beta * pot_norm + 1);
-        penalty_incr = penalty_incr * ((log_term  / (log_term + 1)) * (alpha_h - alpha_l) + alpha_l);
+        penalty_incr = penalty_incr * ((log_term / (log_term + 1)) * (alpha_h - alpha_l) + alpha_l);
         // update density penalties (ELFPlace equation 21)
         for (int g = 0; g < int(groups.size()); g++) {
             if (!groups.at(g).enabled)
-                 continue;
+                continue;
             float next_penalty = dens_penalty.at(g) + (penalty_incr * (rel_pot.at(g) / pot_norm));
             dens_penalty.at(g) = next_penalty;
         }
     }
 
-
     void initialise()
     {
         float initial_steplength = 0.01f;
@@ -1152,7 +1153,8 @@ class StaticPlacer
             RealPair drv_loc = cell_loc(ni->driver.cell, false);
             for (auto usr : ni->users.enumerate()) {
                 RealPair usr_loc = cell_loc(usr.value.cell, false);
-                delay_t est_delay = cfg.timing_c + cfg.timing_mx * std::abs(drv_loc.x - usr_loc.x) + cfg.timing_my * std::abs(drv_loc.y - usr_loc.y);
+                delay_t est_delay = cfg.timing_c + cfg.timing_mx * std::abs(drv_loc.x - usr_loc.x) +
+                                    cfg.timing_my * std::abs(drv_loc.y - usr_loc.y);
                 tmg.set_route_delay(CellPortKey(usr.value), DelayPair(est_delay));
             }
         }
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 8987fefb70..32f5bd3d6c 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -1548,7 +1548,7 @@ struct ECP5Bitgen
                     cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
             } else if (ci->type == id_DDRDLL) {
                 Loc loc = ctx->getBelLocation(ci->bel);
-                bool u = loc.y<15, r = loc.x> 15;
+                bool u = loc.y < 15, r = loc.x > 15;
                 std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
                 if ((ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
                      ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F) &&
diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc
index ae1de86a58..d4aff4925a 100644
--- a/ecp5/gfx.cc
+++ b/ecp5/gfx.cc
@@ -134,9 +134,9 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int
         }
         g.push_back(el);
     } else if (bel_type == id_DCCA) {
-        el.x1 = x + switchbox_x1 + (z)*0.025;
+        el.x1 = x + switchbox_x1 + (z) * 0.025;
         el.y1 = y + 0.14;
-        el.x2 = x + switchbox_x1 + (z)*0.025 + 0.020;
+        el.x2 = x + switchbox_x1 + (z) * 0.025 + 0.020;
         el.y2 = y + 0.18;
         g.push_back(el);
     } else if (bel_type.in(id_DP16KD, id_MULT18X18D, id_ALU54B)) {
diff --git a/generic/viaduct/fabulous/fasm.cc b/generic/viaduct/fabulous/fasm.cc
index 0ec6f02d58..0b8a82831e 100644
--- a/generic/viaduct/fabulous/fasm.cc
+++ b/generic/viaduct/fabulous/fasm.cc
@@ -136,7 +136,7 @@ struct FabFasmWriter
                     continue;
                 unsigned pip_data = pip_tags.at(pip.index).data;
                 unsigned from_pin = (pip_data >> 4) & 0xF;
-                unsigned to_pin = (pip_data)&0xF;
+                unsigned to_pin = (pip_data) & 0xF;
                 NPNR_ASSERT(to_pin == i);
                 phys_to_log[from_pin].push_back(i);
             }
diff --git a/gui/lineshader.h b/gui/lineshader.h
index 784f35a82b..9ebe3eb946 100644
--- a/gui/lineshader.h
+++ b/gui/lineshader.h
@@ -170,7 +170,7 @@ class LineShader
 
   public:
     LineShader(QObject *parent) : parent_(parent), program_(nullptr) {}
-    ~LineShader() { ((QOpenGLWidget*) parent_)->makeCurrent(); }
+    ~LineShader() { ((QOpenGLWidget *)parent_)->makeCurrent(); }
 
     static constexpr const char *vertexShaderSource_ =
             "#version 150\n"
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 044b1a6c0f..09d6d04b8f 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -18,11 +18,11 @@
  */
 
 #include "arch.h"
+#include <boost/filesystem/path.hpp>
 #include "archdefs.h"
 #include "chipdb.h"
 #include "log.h"
 #include "nextpnr.h"
-#include <boost/filesystem/path.hpp>
 
 #include "command.h"
 #include "placer1.h"

From 8f879182307ee3f33ecb681af25b347a6630baea Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 23 Jun 2024 20:26:50 +1000
Subject: [PATCH 614/712] Gowin. Add fix for Single Port BSRAM

Add description of BSRAM harness

In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements.

More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   2 +
 himbaechel/uarch/gowin/gowin.cc          |   1 +
 himbaechel/uarch/gowin/gowin.h           |   3 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  14 ++-
 himbaechel/uarch/gowin/gowin_utils.cc    |   6 ++
 himbaechel/uarch/gowin/gowin_utils.h     |   7 +-
 himbaechel/uarch/gowin/pack.cc           | 125 +++++++++++++++++++----
 7 files changed, 132 insertions(+), 26 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 77de2ee814..7bcf534aae 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -890,6 +890,8 @@ X(WRE)
 
 // BSRAM
 X(BSRAM_SUBTYPE)
+X(WRITE_MODE)
+X(READ_MODE)
 X(BIT_WIDTH)
 X(BIT_WIDTH_0)
 X(BIT_WIDTH_1)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 751f1865b0..5bb7bd2f96 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -259,6 +259,7 @@ void GowinImpl::adjust_dsp_pin_mapping(void)
 void GowinImpl::prePlace() { assign_cell_info(); }
 void GowinImpl::postPlace()
 {
+    gwu.have_SP32();
     if (ctx->debug) {
         log_info("================== Final Placement ===================\n");
         for (auto &cell : ctx->cells) {
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index abff9031e3..e2d34d5064 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -95,7 +95,8 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     Bottom_io_POD bottom_io;
     RelSlice<IdString> diff_io_types;
     // chip flags
-    static constexpr int32_t HAS_SP32 = 0;
+    static constexpr int32_t HAS_SP32 = 1;
+    static constexpr int32_t NEED_SP_FIX = 2;
 });
 
 } // namespace
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index e84e853bef..4dd2e77934 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -15,7 +15,8 @@
 BEL_FLAG_SIMPLE_IO = 0x100
 
 # Chip flags
-CHIP_HAS_SP32 = 0x1
+CHIP_HAS_SP32    = 0x1
+CHIP_NEED_SP_FIX = 0x2
 
 # Z of the bels
 # sync with C++ part!
@@ -1008,8 +1009,15 @@ def main():
         db = pickle.load(f)
 
     chip_flags = 0;
-    if device not in {"GW1NS-4", "GW1N-9"}:
-        chip_flags &= CHIP_HAS_SP32;
+    # XXX compatibility
+    if not hasattr(db, "chip_flags"):
+        if device not in {"GW1NS-4", "GW1N-9"}:
+            chip_flags |= CHIP_HAS_SP32;
+    else:
+        if "HAS_SP32" in db.chip_flags:
+            chip_flags |= CHIP_HAS_SP32;
+        if "NEED_SP_FIX" in db.chip_flags:
+            chip_flags |= CHIP_NEED_SP_FIX;
 
     X = db.cols;
     Y = db.rows;
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 3aba699d67..9443f6e6ab 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -118,6 +118,12 @@ bool GowinUtils::have_SP32(void)
     return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
 }
 
+bool GowinUtils::need_SP_fix(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::NEED_SP_FIX;
+}
+
 std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
 {
     NPNR_ASSERT(!ctx->cells.count(name));
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index ce6b8d9fca..632a4bfd46 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -34,6 +34,10 @@ struct GowinUtils
     Loc get_pair_iologic_bel(Loc loc);
     BelId get_io_bel_from_iologic(BelId bel);
 
+    // BSRAM
+    bool have_SP32(void);
+    bool need_SP_fix(void);
+
     // DSP
     inline int get_dsp_18_z(int z) const { return z & (~3); }
     inline int get_dsp_9_idx(int z) const { return z & 3; }
@@ -81,9 +85,6 @@ struct GowinUtils
         return is_global_wire(ctx->getPipSrcWire(pip)) || is_global_wire(ctx->getPipDstWire(pip));
     }
 
-    // chip dependent
-    bool have_SP32(void);
-
     // make cell but do not include it in the list of chip cells.
     std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
 };
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 193892e2e7..04a54eef45 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -508,13 +508,13 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
-    IdString create_aux_name(IdString main_name, int idx = 0)
+    IdString create_aux_name(IdString main_name, int idx = 0, const char *str_suffix = "_aux$")
     {
         std::string sfx("");
         if (idx) {
             sfx = std::to_string(idx);
         }
-        return ctx->id(main_name.str(ctx) + std::string("_aux$") + sfx);
+        return ctx->id(main_name.str(ctx) + std::string(str_suffix) + sfx);
     }
 
     BelId get_aux_iologic_bel(const CellInfo &ci)
@@ -1331,22 +1331,103 @@ struct GowinPacker
         }
     }
 
-    // If the memory is controlled by the CE, then it is logical for the OCE to
-    // also respond to this signal, unless the OCE is controlled separately.
-    void bsram_handle_sp_oce(CellInfo *ci, IdString ce_pin, IdString oce_pin)
+    // Analysis of the images generated by the IDE showed that some components
+    // are being added at the input and output of the BSRAM.  Two LUTs are
+    // added on the WRE and CE inputs (strangely, OCE is not affected), a pair
+    // of LUT-DFFs on each DO output, and one or two flipflops of different
+    // types in the auxiliary network.
+    // The semantics of these additions are unclear, but we can replicate this behavior.
+    //  Fix BSRAM in single port mode.
+    void bsram_fix_sp(CellInfo *ci, std::vector<std::unique_ptr<CellInfo>> &new_cells)
     {
-        const NetInfo *net = ci->getPort(oce_pin);
-        NPNR_ASSERT(ci->getPort(ce_pin) != nullptr);
-        if (net == nullptr || net->name == ctx->id("$PACKER_VCC") || net->name == ctx->id("$PACKER_GND")) {
+        int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
+
+        // create WRE LUT
+        auto wre_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
+        CellInfo *wre_lut = wre_lut_cell.get();
+        wre_lut->setParam(id_INIT, 0x8888);
+        ci->movePortTo(id_CE, wre_lut, id_I0);
+        ci->movePortTo(id_WRE, wre_lut, id_I1);
+        wre_lut->addOutput(id_F);
+        ci->connectPorts(id_WRE, wre_lut, id_F);
+
+        // create CE LUT
+        auto ce_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_lut$"), id_LUT4);
+        CellInfo *ce_lut = ce_lut_cell.get();
+        ce_lut->setParam(id_INIT, 0xeeee);
+        wre_lut->copyPortTo(id_I0, ce_lut, id_I0);
+        wre_lut->copyPortTo(id_I1, ce_lut, id_I1);
+        ce_lut->addOutput(id_F);
+        ci->connectPorts(id_CE, ce_lut, id_F);
+
+        // create ce reg
+        int write_mode = ci->params.at(id_WRITE_MODE).as_int64();
+        IdString dff_type = write_mode ? id_DFF : id_DFFR;
+        auto ce_pre_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pre_dff$"), dff_type);
+        CellInfo *ce_pre_dff = ce_pre_dff_cell.get();
+        ce_pre_dff->addInput(id_D);
+        ce_lut->copyPortTo(id_I0, ce_pre_dff, id_D);
+        ci->copyPortTo(id_CLK, ce_pre_dff, id_CLK);
+        if (dff_type == id_DFFR) {
+            wre_lut->copyPortTo(id_I1, ce_pre_dff, id_RESET);
+        }
+        ce_pre_dff->addOutput(id_Q);
+
+        // new ce src with Q pin (used by output pins, not by BSRAM itself)
+        CellInfo *new_ce_net_src = ce_pre_dff;
+
+        // add delay register in pipeline mode
+        int read_mode = ci->params.at(id_READ_MODE).as_int64();
+        if (read_mode) {
+            auto ce_pipe_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
+            new_cells.push_back(std::move(ce_pipe_dff_cell));
+            CellInfo *ce_pipe_dff = new_cells.back().get();
+            ce_pipe_dff->addInput(id_D);
+            new_ce_net_src->connectPorts(id_Q, ce_pipe_dff, id_D);
+            ci->copyPortTo(id_CLK, ce_pipe_dff, id_CLK);
+            ce_pipe_dff->addOutput(id_Q);
+            new_ce_net_src = ce_pipe_dff;
+        }
+
+        // used outputs of the BSRAM convert to cached
+        for (int i = 0; i < bit_width; ++i) {
+            IdString do_name = ctx->idf("DO[%d]", i);
+            const NetInfo *net = ci->getPort(do_name);
             if (net != nullptr) {
-                ci->disconnectPort(oce_pin);
+                if (net->users.empty()) {
+                    ci->disconnectPort(do_name);
+                    continue;
+                }
+                // create cache lut
+                auto cache_lut_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_lut$"), id_LUT4);
+                CellInfo *cache_lut = cache_lut_cell.get();
+                cache_lut->setParam(id_INIT, 0xcaca);
+                cache_lut->addInput(id_I0);
+                cache_lut->addInput(id_I1);
+                cache_lut->addInput(id_I2);
+                ci->movePortTo(do_name, cache_lut, id_F);
+                ci->connectPorts(do_name, cache_lut, id_I1);
+                new_ce_net_src->connectPorts(id_Q, cache_lut, id_I2);
+
+                // create cache DFF
+                auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), id_DFFE);
+                CellInfo *cache_dff = cache_dff_cell.get();
+                cache_dff->addInput(id_CE);
+                cache_dff->addInput(id_D);
+                ci->copyPortTo(id_CLK, cache_dff, id_CLK);
+                new_ce_net_src->connectPorts(id_Q, cache_dff, id_CE);
+                cache_lut->copyPortTo(id_I1, cache_dff, id_D);
+                cache_dff->addOutput(id_Q);
+                cache_dff->connectPorts(id_Q, cache_lut, id_I0);
+
+                new_cells.push_back(std::move(cache_lut_cell));
+                new_cells.push_back(std::move(cache_dff_cell));
             }
-            ci->copyPortTo(ce_pin, ci, oce_pin);
-        }
-        if (ctx->verbose) {
-            log_info("%s: %s = %s = %s\n", ctx->nameOf(ci), ce_pin.c_str(ctx), oce_pin.c_str(ctx),
-                     ctx->nameOf(ci->getPort(oce_pin)));
         }
+
+        new_cells.push_back(std::move(wre_lut_cell));
+        new_cells.push_back(std::move(ce_lut_cell));
+        new_cells.push_back(std::move(ce_pre_dff_cell));
     }
 
     void pack_ROM(CellInfo *ci)
@@ -1432,7 +1513,6 @@ struct GowinPacker
             ci->renamePort(ctx->idf("BLKSELB[%d]", i), ctx->idf("BLKSELB%d", i));
         }
 
-        bsram_handle_sp_oce(ci, id_CEB, id_OCE);
         ci->copyPortTo(id_OCE, ci, id_OCEB);
 
         // Port A
@@ -1565,7 +1645,14 @@ struct GowinPacker
         }
 
         int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
-        bsram_handle_sp_oce(ci, id_CE, id_OCE);
+
+        // XXX strange WRE<->CE relations
+        // Gowin IDE adds two LUTs to the WRE and CE signals. The logic is
+        // unclear, but without them effects occur. Perhaps this is a
+        // correction of some BSRAM defects.
+        if (gwu.need_SP_fix()) {
+            bsram_fix_sp(ci, new_cells);
+        }
 
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
@@ -2726,9 +2813,6 @@ struct GowinPacker
         pack_gsr();
         ctx->check();
 
-        pack_inv();
-        ctx->check();
-
         pack_wideluts();
         ctx->check();
 
@@ -2751,6 +2835,9 @@ struct GowinPacker
         pack_dsp();
         ctx->check();
 
+        pack_inv();
+        ctx->check();
+
         pack_buffered_nets();
 
         ctx->fixupHierarchy();

From 2e8280a9496e010f49d183fdac6a6164bd88798f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 25 Jun 2024 18:27:00 +1000
Subject: [PATCH 615/712] Gowin. Fix pipeline mode in BSRAM.

It seems that the internal registers on the BSRAM output pins in
READ_MODE=1'b1 (pipeline) mode do not function properly because in the
images generated by Gowin IDE an external register is added to each pin,
and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode .

This is observed on Tangnano9k and Tangnano20k boards.

Here we repeat this fix.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  1 +
 himbaechel/uarch/gowin/gowin.h           |  1 +
 himbaechel/uarch/gowin/gowin_arch_gen.py |  7 ++-
 himbaechel/uarch/gowin/gowin_utils.cc    |  6 ++
 himbaechel/uarch/gowin/gowin_utils.h     |  1 +
 himbaechel/uarch/gowin/pack.cc           | 75 ++++++++++++++++++++++++
 6 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 7bcf534aae..1add903340 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -892,6 +892,7 @@ X(WRE)
 X(BSRAM_SUBTYPE)
 X(WRITE_MODE)
 X(READ_MODE)
+X(RESET_MODE)
 X(BIT_WIDTH)
 X(BIT_WIDTH_0)
 X(BIT_WIDTH_1)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index e2d34d5064..728d6df21c 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -97,6 +97,7 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     // chip flags
     static constexpr int32_t HAS_SP32 = 1;
     static constexpr int32_t NEED_SP_FIX = 2;
+    static constexpr int32_t NEED_BSRAM_OUTREG_FIX = 4;
 });
 
 } // namespace
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 4dd2e77934..73a5ade1cb 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -15,8 +15,9 @@
 BEL_FLAG_SIMPLE_IO = 0x100
 
 # Chip flags
-CHIP_HAS_SP32    = 0x1
-CHIP_NEED_SP_FIX = 0x2
+CHIP_HAS_SP32             = 0x1
+CHIP_NEED_SP_FIX          = 0x2
+CHIP_NEED_BSRAM_OUTREG_FIX = 0x4
 
 # Z of the bels
 # sync with C++ part!
@@ -1018,6 +1019,8 @@ def main():
             chip_flags |= CHIP_HAS_SP32;
         if "NEED_SP_FIX" in db.chip_flags:
             chip_flags |= CHIP_NEED_SP_FIX;
+        if "NEED_BSRAM_OUTREG_FIX" in db.chip_flags:
+            chip_flags |= CHIP_NEED_BSRAM_OUTREG_FIX;
 
     X = db.cols;
     Y = db.rows;
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 9443f6e6ab..ac6153af1f 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -124,6 +124,12 @@ bool GowinUtils::need_SP_fix(void)
     return extra->chip_flags & Extra_chip_data_POD::NEED_SP_FIX;
 }
 
+bool GowinUtils::need_BSRAM_OUTREG_fix(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_OUTREG_FIX;
+}
+
 std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
 {
     NPNR_ASSERT(!ctx->cells.count(name));
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 632a4bfd46..c4d3e628dd 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -37,6 +37,7 @@ struct GowinUtils
     // BSRAM
     bool have_SP32(void);
     bool need_SP_fix(void);
+    bool need_BSRAM_OUTREG_fix(void);
 
     // DSP
     inline int get_dsp_18_z(int z) const { return z & (~3); }
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 04a54eef45..ee1ce9f200 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1331,6 +1331,73 @@ struct GowinPacker
         }
     }
 
+    // Some chips cannot, for some reason, use internal BSRAM registers to
+    // implement READ_MODE=1'b1 (pipeline) with a word width other than 32 or
+    // 36 bits.
+    // We work around this by adding an external DFF and using BSRAM
+    // as READ_MODE=1'b0 (bypass).
+    void bsram_fix_outreg(CellInfo *ci, std::vector<std::unique_ptr<CellInfo>> &new_cells)
+    {
+        int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
+        if (bit_width == 32 || bit_width == 36) {
+            return;
+        }
+        int read_mode = ci->params.at(id_READ_MODE).as_int64();
+        if (read_mode == 0) {
+            return;
+        }
+        NetInfo *ce_net = ci->getPort(id_CE);
+        NetInfo *oce_net = ci->getPort(id_OCE);
+        if (ce_net == nullptr || oce_net == nullptr) {
+            return;
+        }
+        if (ce_net->name == ctx->id("$PACKER_GND") || oce_net->name == ctx->id("$PACKER_GND")) {
+            return;
+        }
+
+        if (ctx->verbose) {
+            log_info("  apply the BSRAM OUTREG fix\n");
+        }
+        ci->setParam(id_READ_MODE, 0);
+        ci->disconnectPort(id_OCE);
+        ci->connectPort(id_OCE, ce_net);
+
+        NetInfo *reset_net = ci->getPort(id_RESET);
+        bool sync_reset = ci->params.at(id_RESET_MODE).as_string() == std::string("SYNC");
+        IdString dff_type = sync_reset ? id_DFFRE : id_DFFCE;
+        IdString reset_port = sync_reset ? id_RESET : id_CLEAR;
+
+        for (int i = 0; i < bit_width; ++i) {
+            IdString do_name = ctx->idf("DO[%d]", i);
+            const NetInfo *net = ci->getPort(do_name);
+            if (net != nullptr) {
+                if (net->users.empty()) {
+                    ci->disconnectPort(do_name);
+                    continue;
+                }
+
+                // create DFF
+                auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), dff_type);
+                CellInfo *cache_dff = cache_dff_cell.get();
+                cache_dff->addInput(id_CE);
+                cache_dff->connectPort(id_CE, oce_net);
+
+                cache_dff->addInput(reset_port);
+                cache_dff->connectPort(reset_port, reset_net);
+
+                ci->copyPortTo(id_CLK, cache_dff, id_CLK);
+
+                cache_dff->addOutput(id_Q);
+                ci->movePortTo(do_name, cache_dff, id_Q);
+
+                cache_dff->addInput(id_D);
+                ci->connectPorts(do_name, cache_dff, id_D);
+
+                new_cells.push_back(std::move(cache_dff_cell));
+            }
+        }
+    }
+
     // Analysis of the images generated by the IDE showed that some components
     // are being added at the input and output of the BSRAM.  Two LUTs are
     // added on the WRE and CE inputs (strangely, OCE is not affected), a pair
@@ -1342,6 +1409,9 @@ struct GowinPacker
     {
         int bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
 
+        if (ctx->verbose) {
+            log_info("  apply the SP fix\n");
+        }
         // create WRE LUT
         auto wre_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
         CellInfo *wre_lut = wre_lut_cell.get();
@@ -1654,6 +1724,11 @@ struct GowinPacker
             bsram_fix_sp(ci, new_cells);
         }
 
+        // Some chips have faulty output registers
+        if (gwu.need_BSRAM_OUTREG_fix()) {
+            bsram_fix_outreg(ci, new_cells);
+        }
+
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.

From 0639681b7328463e909cbca714ff9095476f186c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 28 Jun 2024 08:15:50 +1000
Subject: [PATCH 616/712] Gowin. Fix BSRAM block selection.

In the images generated by Gowin IDE, the signals for dynamic BSRAM
block selection (BLKSEL[2:0]) are not always connected directly to the
ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into
Clock Enable.  Apparently there are chips with an error in the operation
of these ports.

Here we make such a decoder instead of using ports directly.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  1 +
 himbaechel/uarch/gowin/gowin.h           |  1 +
 himbaechel/uarch/gowin/gowin_arch_gen.py |  7 ++-
 himbaechel/uarch/gowin/gowin_utils.cc    |  6 +++
 himbaechel/uarch/gowin/gowin_utils.h     |  1 +
 himbaechel/uarch/gowin/pack.cc           | 69 ++++++++++++++++++++++++
 6 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 1add903340..032de7ac65 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -889,6 +889,7 @@ X(DID)
 X(WRE)
 
 // BSRAM
+X(BLK_SEL)
 X(BSRAM_SUBTYPE)
 X(WRITE_MODE)
 X(READ_MODE)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 728d6df21c..c815fe0a2c 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -98,6 +98,7 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     static constexpr int32_t HAS_SP32 = 1;
     static constexpr int32_t NEED_SP_FIX = 2;
     static constexpr int32_t NEED_BSRAM_OUTREG_FIX = 4;
+    static constexpr int32_t NEED_BLKSEL_FIX = 8;
 });
 
 } // namespace
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 73a5ade1cb..cc19e3c09c 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -15,9 +15,10 @@
 BEL_FLAG_SIMPLE_IO = 0x100
 
 # Chip flags
-CHIP_HAS_SP32             = 0x1
-CHIP_NEED_SP_FIX          = 0x2
+CHIP_HAS_SP32              = 0x1
+CHIP_NEED_SP_FIX           = 0x2
 CHIP_NEED_BSRAM_OUTREG_FIX = 0x4
+CHIP_NEED_BLKSEL_FIX       = 0x8
 
 # Z of the bels
 # sync with C++ part!
@@ -1021,6 +1022,8 @@ def main():
             chip_flags |= CHIP_NEED_SP_FIX;
         if "NEED_BSRAM_OUTREG_FIX" in db.chip_flags:
             chip_flags |= CHIP_NEED_BSRAM_OUTREG_FIX;
+        if "NEED_BLKSEL_FIX" in db.chip_flags:
+            chip_flags |= CHIP_NEED_BLKSEL_FIX;
 
     X = db.cols;
     Y = db.rows;
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index ac6153af1f..603b6fc5b5 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -130,6 +130,12 @@ bool GowinUtils::need_BSRAM_OUTREG_fix(void)
     return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_OUTREG_FIX;
 }
 
+bool GowinUtils::need_BLKSEL_fix(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::NEED_BLKSEL_FIX;
+}
+
 std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
 {
     NPNR_ASSERT(!ctx->cells.count(name));
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index c4d3e628dd..65ae632e99 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -38,6 +38,7 @@ struct GowinUtils
     bool have_SP32(void);
     bool need_SP_fix(void);
     bool need_BSRAM_OUTREG_fix(void);
+    bool need_BLKSEL_fix(void);
 
     // DSP
     inline int get_dsp_18_z(int z) const { return z & (~3); }
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ee1ce9f200..b0975b3a3f 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1331,6 +1331,70 @@ struct GowinPacker
         }
     }
 
+    // We solve the BLKSEL problems that are observed on some chips by
+    // connecting the BLKSEL ports to constant networks so that this BSRAM will
+    // be selected, the actual selection is made by manipulating the Clock
+    // Enable pin using a LUT-based decoder.
+    void bsram_fix_blksel(CellInfo *ci, std::vector<std::unique_ptr<CellInfo>> &new_cells)
+    {
+        // is BSRAM enabled
+        NetInfo *ce_net = ci->getPort(id_CE);
+        if (ce_net == nullptr || ce_net->name == ctx->id("$PACKER_GND")) {
+            return;
+        }
+
+        // port name, BLK_SEL parameter for this port
+        std::vector<std::pair<IdString, int>> dyn_blksel;
+
+        int blk_sel_parameter = ci->params.at(id_BLK_SEL).as_int64();
+        for (int i = 0; i < 3; ++i) {
+            IdString pin_name = ctx->idf("BLKSEL[%d]", i);
+            NetInfo *net = ci->getPort(pin_name);
+            if (net == nullptr || net->name == ctx->id("$PACKER_GND") || net->name == ctx->id("$PACKER_VCC")) {
+                continue;
+            }
+            dyn_blksel.push_back(std::make_pair(pin_name, (blk_sel_parameter >> i) & 1));
+        }
+
+        if (dyn_blksel.empty()) {
+            return;
+        }
+
+        if (ctx->verbose) {
+            log_info("  apply the BSRAM BLKSEL fix\n");
+        }
+
+        // Make a decoder
+        auto lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_blksel_lut$"), id_LUT4);
+        CellInfo *lut = lut_cell.get();
+        lut->addInput(id_I3);
+        ci->movePortTo(id_CE, lut, id_I3);
+        lut->addOutput(id_F);
+        ci->connectPorts(id_CE, lut, id_F);
+
+        NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+        NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+
+        // Connected CE to I3 to make it easy to calculate the decoder
+        int init = 0x100; // CE == 0 -->  F = 0
+                          // CE == 1 -->  F = decoder result
+        int idx = 0;
+        for (auto &port : dyn_blksel) {
+            IdString lut_input_name = ctx->idf("I%d", idx);
+            ci->movePortTo(port.first, lut, lut_input_name);
+            if (port.second) {
+                init <<= (1 << idx);
+                ci->connectPort(port.first, vcc_net);
+            } else {
+                ci->connectPort(port.first, vss_net);
+            }
+            ++idx;
+        }
+        lut->setParam(id_INIT, init);
+
+        new_cells.push_back(std::move(lut_cell));
+    }
+
     // Some chips cannot, for some reason, use internal BSRAM registers to
     // implement READ_MODE=1'b1 (pipeline) with a word width other than 32 or
     // 36 bits.
@@ -1729,6 +1793,11 @@ struct GowinPacker
             bsram_fix_outreg(ci, new_cells);
         }
 
+        // Some chips have problems with BLKSEL ports
+        if (gwu.need_BLKSEL_fix()) {
+            bsram_fix_blksel(ci, new_cells);
+        }
+
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.

From ba293437e02e01e09936d029d80d78ad601fc4e7 Mon Sep 17 00:00:00 2001
From: TG <tarik.graba@telecom-paris.fr>
Date: Tue, 2 Jul 2024 15:15:20 +0200
Subject: [PATCH 617/712] ice40: Fix Python bindings for pip iterators

---
 ice40/arch_pybindings.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 09fcff3c95..a65ad0824d 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -81,8 +81,8 @@ void arch_wrap_python(py::module &m)
     readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
     readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
 
-    typedef const PipRange UphillPipRange;
-    typedef const PipRange DownhillPipRange;
+    typedef PipRange UphillPipRange;
+    typedef PipRange DownhillPipRange;
 
     typedef const std::vector<BelBucketId> &BelBucketRange;
     typedef const std::vector<BelId> &BelRangeForBelBucket;

From 7dd4a8c1d546c048b3b755d361820c865add7956 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 6 Jul 2024 19:14:43 +1000
Subject: [PATCH 618/712] Gowin. Implement power saving primitive

As the board on the GW1N-1 chip becomes a rarity, its replacement is the
Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism
for turning off power to important things such as OSC, PLL, etc.

Here we introduce a primitive that allows energy saving to be controlled
dynamically.

We also bring the names of some functions to uniformity.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  4 +++
 himbaechel/uarch/gowin/gowin.cc          |  2 +-
 himbaechel/uarch/gowin/gowin.h           |  2 ++
 himbaechel/uarch/gowin/gowin_arch_gen.py |  9 +++++
 himbaechel/uarch/gowin/gowin_utils.cc    | 10 ++++--
 himbaechel/uarch/gowin/gowin_utils.h     |  7 ++--
 himbaechel/uarch/gowin/pack.cc           | 42 ++++++++++++++++++++++--
 7 files changed, 69 insertions(+), 7 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 032de7ac65..c597a8cfdd 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -987,6 +987,10 @@ X(GSR)
 X(GSR0)
 X(GSRI)
 
+// power saving
+X(BANDGAP)
+X(BGEN)
+
 // inverter
 X(INV)
 
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 5bb7bd2f96..8942154b33 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -259,7 +259,7 @@ void GowinImpl::adjust_dsp_pin_mapping(void)
 void GowinImpl::prePlace() { assign_cell_info(); }
 void GowinImpl::postPlace()
 {
-    gwu.have_SP32();
+    gwu.has_SP32();
     if (ctx->debug) {
         log_info("================== Final Placement ===================\n");
         for (auto &cell : ctx->cells) {
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index c815fe0a2c..b2fc5f80ef 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -99,6 +99,7 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     static constexpr int32_t NEED_SP_FIX = 2;
     static constexpr int32_t NEED_BSRAM_OUTREG_FIX = 4;
     static constexpr int32_t NEED_BLKSEL_FIX = 8;
+    static constexpr int32_t HAS_BANDGAP = 16;
 });
 
 } // namespace
@@ -131,6 +132,7 @@ enum
     GSR_Z = 276,
     VCC_Z = 277,
     VSS_Z = 278,
+    BANDGAP_Z = 279,
 
     // The two least significant bits encode Z for 9-bit adders and
     // multipliers, if they are equal to 0, then we get Z of their common
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index cc19e3c09c..a6cffd358b 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -19,6 +19,7 @@
 CHIP_NEED_SP_FIX           = 0x2
 CHIP_NEED_BSRAM_OUTREG_FIX = 0x4
 CHIP_NEED_BLKSEL_FIX       = 0x8
+CHIP_HAS_BANDGAP           = 0x10
 
 # Z of the bels
 # sync with C++ part!
@@ -46,6 +47,7 @@
 GSR_Z   = 276
 VCC_Z   = 277
 GND_Z   = 278
+BANDGAP_Z = 279
 
 DSP_Z          = 509
 
@@ -338,6 +340,11 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
             tt.create_wire(wire, "GSRI")
             bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
             tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
+        elif func == 'bandgap':
+            wire = desc['wire']
+            tt.create_wire(wire, "BGEN")
+            bel = tt.create_bel("BANDGAP", "BANDGAP", z = BANDGAP_Z)
+            tt.add_bel_pin(bel, "BGEN", wire, PinType.INPUT)
         if func == 'io16':
             role = desc['role']
             if role == 'MAIN':
@@ -1024,6 +1031,8 @@ def main():
             chip_flags |= CHIP_NEED_BSRAM_OUTREG_FIX;
         if "NEED_BLKSEL_FIX" in db.chip_flags:
             chip_flags |= CHIP_NEED_BLKSEL_FIX;
+        if "HAS_BANDGAP" in db.chip_flags:
+            chip_flags |= CHIP_HAS_BANDGAP;
 
     X = db.cols;
     Y = db.rows;
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 603b6fc5b5..37cff7077c 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -94,7 +94,7 @@ bool GowinUtils::is_diff_io_supported(IdString type)
     return false;
 }
 
-bool GowinUtils::have_bottom_io_cnds(void)
+bool GowinUtils::has_bottom_io_cnds(void)
 {
     const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
     return extra->bottom_io.conditions.size() != 0;
@@ -112,7 +112,13 @@ IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
     return IdString(extra->bottom_io.conditions[condition].wire_b_net);
 }
 
-bool GowinUtils::have_SP32(void)
+bool GowinUtils::has_BANDGAP(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::HAS_BANDGAP;
+}
+
+bool GowinUtils::has_SP32(void)
 {
     const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
     return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 65ae632e99..7b76ea9aae 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -35,11 +35,14 @@ struct GowinUtils
     BelId get_io_bel_from_iologic(BelId bel);
 
     // BSRAM
-    bool have_SP32(void);
+    bool has_SP32(void);
     bool need_SP_fix(void);
     bool need_BSRAM_OUTREG_fix(void);
     bool need_BLKSEL_fix(void);
 
+    // Power saving
+    bool has_BANDGAP(void);
+
     // DSP
     inline int get_dsp_18_z(int z) const { return z & (~3); }
     inline int get_dsp_9_idx(int z) const { return z & 3; }
@@ -65,7 +68,7 @@ struct GowinUtils
     CellInfo *dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, int wire_num) const;
 
     bool is_diff_io_supported(IdString type);
-    bool have_bottom_io_cnds(void);
+    bool has_bottom_io_cnds(void);
     IdString get_bottom_io_wire_a_net(int8_t condition);
     IdString get_bottom_io_wire_b_net(int8_t condition);
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index b0975b3a3f..7fedad6e15 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -68,7 +68,7 @@ struct GowinPacker
 
     void config_bottom_row(CellInfo &ci, Loc loc, uint8_t cnd = Bottom_io_POD::NORMAL)
     {
-        if (!gwu.have_bottom_io_cnds()) {
+        if (!gwu.has_bottom_io_cnds()) {
             return;
         }
         if (!ci.type.in(id_OBUF, id_TBUF, id_IOBUF)) {
@@ -1802,7 +1802,7 @@ struct GowinPacker
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.
         // So divide it here
-        if ((bit_width == 32 || bit_width == 36) && !gwu.have_SP32()) {
+        if ((bit_width == 32 || bit_width == 36) && !gwu.has_SP32()) {
             divide_sp(ci, new_cells);
             bit_width = ci->params.at(id_BIT_WIDTH).as_int64();
         }
@@ -2839,6 +2839,41 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // Global power regulator
+    // ===================================
+    void pack_bandgap(void)
+    {
+        if (!gwu.has_BANDGAP()) {
+            return;
+        }
+        log_info("Pack BANDGAP...\n");
+
+        bool user_bandgap = false;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+
+            if (ci.type == id_BANDGAP) {
+                user_bandgap = true;
+                break;
+            }
+        }
+        if (!user_bandgap) {
+            // make default BANDGAP
+            auto bandgap_cell = std::make_unique<CellInfo>(ctx, id_BANDGAP, id_BANDGAP);
+            bandgap_cell->addInput(id_BGEN);
+            bandgap_cell->connectPort(id_BGEN, ctx->nets.at(ctx->id("$PACKER_VCC")).get());
+            ctx->cells[bandgap_cell->name] = std::move(bandgap_cell);
+        }
+        if (ctx->verbose) {
+            if (user_bandgap) {
+                log_info("Have user BANDGAP\n");
+            } else {
+                log_info("No user BANDGAP. Make one.\n");
+            }
+        }
+    }
+
     // ===================================
     // Replace INV with LUT
     // ===================================
@@ -2957,6 +2992,9 @@ struct GowinPacker
         pack_gsr();
         ctx->check();
 
+        pack_bandgap();
+        ctx->check();
+
         pack_wideluts();
         ctx->check();
 

From 6b5b21e1655d04ee1e7cf2f6c76545bc68026ed6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 17 Apr 2024 08:00:45 +0200
Subject: [PATCH 619/712] Enable user to override setupArchContext in
 Himbaechel arch

---
 himbaechel/himbaechel_api.h | 1 +
 himbaechel/main.cc          | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index d68caea83f..b1c50c5aa0 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -58,6 +58,7 @@ struct PlacerHeapCfg;
 struct HimbaechelAPI
 {
     virtual void init(Context *ctx);
+    virtual void setupArchContext() {}
     // If constids are being used, this is used to set them up early
     // then it is responsible for loading the db blob with arch->load_chipdb()
     virtual void init_database(Arch *arch) = 0;
diff --git a/himbaechel/main.cc b/himbaechel/main.cc
index 26686f8370..dccad722f9 100644
--- a/himbaechel/main.cc
+++ b/himbaechel/main.cc
@@ -33,7 +33,7 @@ class HimbaechelCommandHandler : public CommandHandler
     HimbaechelCommandHandler(int argc, char **argv);
     virtual ~HimbaechelCommandHandler(){};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override;
     void customBitstream(Context *ctx) override;
 
   protected:
@@ -58,6 +58,8 @@ po::options_description HimbaechelCommandHandler::getArchOptions()
     return specific;
 }
 
+void HimbaechelCommandHandler::setupArchContext(Context *ctx) { ctx->uarch->setupArchContext(); }
+
 void HimbaechelCommandHandler::customBitstream(Context *ctx) {}
 
 std::unique_ptr<Context> HimbaechelCommandHandler::createContext(dict<std::string, Property> &values)

From cecd6b3f4d2ff4a4931647db2337a7adcd144432 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 19 Apr 2024 12:07:15 +0200
Subject: [PATCH 620/712] Document context related calls in HimbaechelAPI

---
 himbaechel/himbaechel_api.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index b1c50c5aa0..21275cfb29 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -57,7 +57,9 @@ struct PlacerHeapCfg;
 
 struct HimbaechelAPI
 {
+    // Architecture specific context initialization
     virtual void init(Context *ctx);
+    // Called after context is initialized, but before any commands are executed
     virtual void setupArchContext() {}
     // If constids are being used, this is used to set them up early
     // then it is responsible for loading the db blob with arch->load_chipdb()

From 1871afe9b9970af8adc410b2715746c0bdeade50 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 4 Jul 2024 19:10:07 +1000
Subject: [PATCH 621/712] Gowin. Taking into account the features of ROM
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

For pROM(X9) primitives in images generated by Gowin IDE, there is an
interesting recommunication of inputs depending on the data bit depth.
For example, in some cases, a high logical level may be applied to the
Write Enable input, which, let’s say, is not entirely usual for Read
Only memory.

Here we will do similar manipulations.

In addition, several minor bug fixes are included:

 - Fixed bit numbering for non-X9 series primitives.
 - Fixed decoder generation for BLKSEL - do not assume unused inputs are
   connected to GND.
 - Use default values for BSRAM parameters - don't assume their
   mandatory presence.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 56 +++++++++++++++++++++++++++-------
 1 file changed, 45 insertions(+), 11 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 7fedad6e15..bc8f70fde4 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1,6 +1,7 @@
 #include "design_utils.h"
 #include "log.h"
 #include "nextpnr.h"
+#include "util.h"
 
 #define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
 #include "himbaechel_constids.h"
@@ -1324,7 +1325,7 @@ struct GowinPacker
     {
         int num = (bit_width == 9 || bit_width == 18 || bit_width == 36) ? 36 : 32;
         for (int i = 0, j = offset; i < num; ++i, ++j) {
-            if (((i + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) {
+            if (((j + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) {
                 ++j;
             }
             ci->renamePort(ctx->idf(from, i), ctx->idf(to, offset ? j % 36 : j));
@@ -1390,6 +1391,15 @@ struct GowinPacker
             }
             ++idx;
         }
+        switch (idx) {
+        case 1:
+            init |= init << 2; /* fallthrough */
+        case 2:
+            init |= init << 4;
+            break;
+        default:
+            break;
+        }
         lut->setParam(id_INIT, init);
 
         new_cells.push_back(std::move(lut_cell));
@@ -1406,7 +1416,7 @@ struct GowinPacker
         if (bit_width == 32 || bit_width == 36) {
             return;
         }
-        int read_mode = ci->params.at(id_READ_MODE).as_int64();
+        int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
         if (read_mode == 0) {
             return;
         }
@@ -1511,7 +1521,7 @@ struct GowinPacker
         CellInfo *new_ce_net_src = ce_pre_dff;
 
         // add delay register in pipeline mode
-        int read_mode = ci->params.at(id_READ_MODE).as_int64();
+        int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
         if (read_mode) {
             auto ce_pipe_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
             new_cells.push_back(std::move(ce_pipe_dff_cell));
@@ -1587,10 +1597,7 @@ struct GowinPacker
             ci->connectPort(port, vcc_net);
         }
 
-        ci->addInput(id_WRE);
-        ci->connectPort(id_WRE, vss_net);
         ci->addInput(id_WREB);
-        ci->connectPort(id_WREB, vss_net);
 
         if (!ci->params.count(id_BIT_WIDTH)) {
             ci->setParam(id_BIT_WIDTH, Property(default_bw, 32));
@@ -1602,10 +1609,19 @@ struct GowinPacker
             ci->copyPortTo(id_CE, ci, id_CEB);
             ci->copyPortTo(id_OCE, ci, id_OCEB);
             ci->copyPortTo(id_RESET, ci, id_RESETB);
+            ci->connectPort(id_WREB, vcc_net);
 
-            for (int i = 0; i < 14; ++i) {
-                ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
-                ci->copyPortTo(ctx->idf("ADA%d", i), ci, ctx->idf("ADB%d", i));
+            // disconnect lower address bits for ROM
+            static int rom_ignore_bits[] = {2, 4, 8, 16, 32};
+            static int romx9_ignore_bits[] = {9, 9, 9, 18, 36};
+            for (unsigned int i = 0; i < 14; ++i) {
+                if (i < sizeof(rom_ignore_bits) && ((ci->type == id_pROM && bit_width >= rom_ignore_bits[i]) ||
+                                                    (ci->type == id_pROMX9 && bit_width >= romx9_ignore_bits[i]))) {
+                    ci->disconnectPort(ctx->idf("AD[%d]", i));
+                } else {
+                    ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
+                    ci->copyPortTo(ctx->idf("ADA%d", i), ci, ctx->idf("ADB%d", i));
+                }
             }
             bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
         } else {
@@ -1614,9 +1630,18 @@ struct GowinPacker
             ci->renamePort(id_OCE, id_OCEB);
             ci->renamePort(id_CE, id_CEB);
             ci->renamePort(id_RESET, id_RESETB);
+            ci->connectPort(id_WREB, vss_net);
+
+            ci->addInput(id_CE);
+            ci->connectPort(id_CE, vcc_net);
+            ci->disconnectPort(id_OCEB);
 
-            ci->addInput(id_CEA);
-            ci->connectPort(id_CEA, vss_net);
+            int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
+            if (read_mode) {
+                ci->connectPort(id_OCEB, vcc_net);
+            } else {
+                ci->copyPortTo(id_CEB, ci, id_OCEB);
+            }
             for (int i = 0; i < 14; ++i) {
                 ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADB%d", i));
             }
@@ -1798,6 +1823,15 @@ struct GowinPacker
             bsram_fix_blksel(ci, new_cells);
         }
 
+        // XXX
+        NetInfo *oce_net = ci->getPort(id_OCE);
+        if (oce_net == nullptr || oce_net->name == ctx->id("$PACKER_VCC") || oce_net->name == ctx->id("$PACKER_GND")) {
+            if (oce_net != nullptr) {
+                ci->disconnectPort(id_OCE);
+                ci->copyPortTo(id_CE, ci, id_OCE);
+            }
+        }
+
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.

From eb099a9244857219ee33d627540dc5e2316893ae Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 9 Jul 2024 09:42:35 +1000
Subject: [PATCH 622/712] Gowin. Bugfix.

The statement in the Gowin documentation that in the reading mode
"READ_MODE=0" the output register is not used and the OCE signal is
ignored is not confirmed by practice - if the OCE was left unconnected
or connected to the constant network, then a change in output data was
observed even with CE=0, as well as the absence of such at CE=1.

Synchronizing CE and OCE helps and the memory works properly in complex
systems such as RISC-V emulation and i8080 emulation (with 32K RAM and
16K BSRAM based ROM), but there is no theoretical basis for this fix, so
it is a hack.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/pack.cc | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index bc8f70fde4..2faf1df0c1 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1612,11 +1612,11 @@ struct GowinPacker
             ci->connectPort(id_WREB, vcc_net);
 
             // disconnect lower address bits for ROM
-            static int rom_ignore_bits[] = {2, 4, 8, 16, 32};
-            static int romx9_ignore_bits[] = {9, 9, 9, 18, 36};
+            std::array rom_ignore_bits = {2, 4, 8, 16, 32};
+            std::array romx9_ignore_bits = {9, 9, 9, 18, 36};
             for (unsigned int i = 0; i < 14; ++i) {
-                if (i < sizeof(rom_ignore_bits) && ((ci->type == id_pROM && bit_width >= rom_ignore_bits[i]) ||
-                                                    (ci->type == id_pROMX9 && bit_width >= romx9_ignore_bits[i]))) {
+                if (i < size(rom_ignore_bits) && ((ci->type == id_pROM && bit_width >= rom_ignore_bits[i]) ||
+                                                  (ci->type == id_pROMX9 && bit_width >= romx9_ignore_bits[i]))) {
                     ci->disconnectPort(ctx->idf("AD[%d]", i));
                 } else {
                     ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
@@ -1823,13 +1823,19 @@ struct GowinPacker
             bsram_fix_blksel(ci, new_cells);
         }
 
-        // XXX
+        // The statement in the Gowin documentation that in the reading mode
+        // "READ_MODE=0" the output register is not used and the OCE signal is
+        // ignored is not confirmed by practice - if the OCE was left
+        // unconnected or connected to the constant network, then a change in
+        // output data was observed even with CE=0, as well as the absence of
+        // such at CE=1.
+        // Synchronizing CE and OCE helps but it's definitely a hack.
         NetInfo *oce_net = ci->getPort(id_OCE);
         if (oce_net == nullptr || oce_net->name == ctx->id("$PACKER_VCC") || oce_net->name == ctx->id("$PACKER_GND")) {
             if (oce_net != nullptr) {
                 ci->disconnectPort(id_OCE);
-                ci->copyPortTo(id_CE, ci, id_OCE);
             }
+            ci->copyPortTo(id_CE, ci, id_OCE);
         }
 
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:

From f17caa23795386c02dfdcc00f8ec582a757244b9 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 29 Jul 2024 16:19:04 +1000
Subject: [PATCH 623/712] Gowin. BUGFIX. Fix placement checks

It was not taken into account that there are only 6 ALUs per cell. As a
result, on complex designs where ALUs and LUT-based memory are involved
and there are many LUTs (like in the RISCV emulator), there were
sometimes false positives about placement conflicts.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 8942154b33..b9ca90707d 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -539,8 +539,10 @@ bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
 bool GowinImpl::slice_valid(int x, int y, int z) const
 {
     const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+    const bool lut_in_4_5 = lut && (z == 4 || z == 5);
     const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-    const CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z)));
+    // There are only 6 ALUs
+    const CellInfo *alu = (z < 6) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z))) : nullptr;
     const CellInfo *ramw =
             (z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
 
@@ -549,7 +551,7 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     }
 
     if (ramw) {
-        if (alu || ff || lut) {
+        if (alu || ff || lut_in_4_5) {
             return false;
         }
         return true;
@@ -560,7 +562,9 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
     const CellInfo *adj_lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z)));
     const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z + 1)));
-    const CellInfo *adj_alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)));
+    const CellInfo *adj_alu = adj_alu_z < (6 + BelZ::ALU0_Z)
+                                      ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)))
+                                      : nullptr;
 
     if ((alu && (adj_lut || (adj_ff && !adj_alu))) || ((lut || (ff && !alu)) && adj_alu)) {
         return false;

From 10a5a44b815f83bd980ceed47d4b17ef41aac7ca Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 14 Jul 2024 16:53:26 +1000
Subject: [PATCH 624/712] Gowin. Implement clock management primitives.

DQCE and DCS primitives are added.

DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.

DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.

Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.

Also:
  - minor edits to make the most of helper functions like connectPorts()
  - when creating bases, the corresponding constants are assigned to the
    VCC and GND wires, but for now huge nodes are used because, for an
    unknown reason, the constants mechanism makes large examples
    inoperable. So for now we remain on the nodes.

Compatible with older Apicula databases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   8 +-
 himbaechel/uarch/gowin/globals.cc        | 417 +++++++++++++++++------
 himbaechel/uarch/gowin/gowin.cc          |   5 +-
 himbaechel/uarch/gowin/gowin.h           |  12 +
 himbaechel/uarch/gowin/gowin_arch_gen.py | 111 +++++-
 himbaechel/uarch/gowin/gowin_utils.cc    |  22 ++
 himbaechel/uarch/gowin/gowin_utils.h     |   2 +
 himbaechel/uarch/gowin/pack.cc           |  90 ++++-
 8 files changed, 547 insertions(+), 120 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index c597a8cfdd..5aeac7489c 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1197,7 +1197,13 @@ X(HCLK_OUT2)
 X(HCLK_OUT3)
 
 // BUFG, clock buffers stuff
+X(CLKSEL)
 X(BUFG)
 X(CLOCK)
-
+X(DQCE)
+X(DCS)
+X(DCS_MODE)
+X(DQCE_PIP)
+X(DCS_USED)
+X(SELFORCE)
 
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 2504f8ccef..011e2f371f 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -49,9 +49,41 @@ struct GowinGlobalRouter
             return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
         };
 
-        IdString src_type = ctx->getWireType(ctx->getPipSrcWire(pip));
+        WireId src, dst;
+        src = ctx->getPipSrcWire(pip);
+        dst = ctx->getPipDstWire(pip);
+        IdString dst_name = ctx->getWireName(dst)[1];
+        bool not_dsc_pip = dst_name != id_CLKOUT;
+        IdString src_type = ctx->getWireType(src);
+        IdString dst_type = ctx->getWireType(dst);
+        bool src_valid = not_dsc_pip && src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
+        bool dst_valid = not_dsc_pip && dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
+
+        bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        if (ctx->debug && false /*&& res*/) {
+            log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
+                     ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
+                     src_type.c_str(ctx));
+            log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
+                     is_local(src_type), is_local(dst_type));
+        }
+        return res;
+    }
+
+    bool global_DCS_pip_filter(PipId pip) const
+    {
+        auto is_local = [&](IdString wire_type) {
+            return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
+        };
+
+        WireId src = ctx->getPipSrcWire(pip);
+        IdString src_type = ctx->getWireType(src);
+        IdString src_name = ctx->getWireName(src)[1];
+        bool src_is_spine = src_name.str(ctx).rfind("SPINE", 0) == 0;
         IdString dst_type = ctx->getWireType(ctx->getPipDstWire(pip));
-        bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
+        bool src_valid = ((!src_is_spine) && src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK)) ||
+                         src_name.in(id_SPINE6, id_SPINE7, id_SPINE14, id_SPINE15, id_SPINE22, id_SPINE23, id_SPINE30,
+                                     id_SPINE31);
         bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
 
         bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
@@ -71,7 +103,6 @@ struct GowinGlobalRouter
     template <typename Tfilt>
     bool backwards_bfs_route(NetInfo *net, WireId src, WireId dst, int iter_limit, bool strict, Tfilt pip_filter)
     {
-        // log_info("route arc %s:%s->%s\n", net->name.c_str(ctx), ctx->nameOfWire(src), ctx->nameOfWire(dst));
         // Queue of wires to visit
         std::queue<WireId> visit;
         // Wire -> upstream pip
@@ -134,14 +165,12 @@ struct GowinGlobalRouter
                 }
                 pips.push_back(pip);
                 cursor = ctx->getPipDstWire(pip);
-                // log_info(">> %s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(cursor));
             }
             // Reverse that list
             std::reverse(pips.begin(), pips.end());
             // Bind pips until we hit already-bound routing
             for (PipId pip : pips) {
                 WireId dst = ctx->getPipDstWire(pip);
-                // log_info("bind pip %s:%s\n", ctx->getPipName(pip).str(ctx).c_str(), ctx->nameOfWire(dst));
                 if (ctx->getBoundWireNet(dst) == net) {
                     break;
                 }
@@ -160,6 +189,43 @@ struct GowinGlobalRouter
         }
     }
 
+    bool driver_is_buf(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_BUFG, id_O); }
+    bool driver_is_dqce(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_DQCE, id_CLKOUT); }
+    bool driver_is_dcs(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_DCS, id_CLKOUT); }
+    bool driver_is_clksrc(const PortRef &driver)
+    {
+        // dedicated pins
+        if (CellTypePort(driver) == CellTypePort(id_IBUF, id_O)) {
+
+            NPNR_ASSERT(driver.cell->bel != BelId());
+            IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
+            for (size_t i = 0; i < pin_func.size(); ++i) {
+                if (ctx->debug) {
+                    log_info("bel:%s, pin func: %zu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
+                             pin_func[i].str(ctx).c_str());
+                }
+                if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
+                    if (ctx->debug) {
+                        log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
+                                 pin_func[i].c_str(ctx));
+                    }
+                    return true;
+                }
+            }
+        }
+        // PLL outputs
+        if (driver.cell->type.in(id_rPLL, id_PLLVR)) {
+            if (driver.port.in(id_CLKOUT, id_CLKOUTD, id_CLKOUTD3, id_CLKOUTP)) {
+                if (ctx->debug) {
+                    log_info("PLL out:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
+                             driver.port.c_str(ctx));
+                }
+                return true;
+            }
+        }
+        return false;
+    }
+
     enum RouteResult
     {
         NOT_ROUTED = 0,
@@ -167,72 +233,223 @@ struct GowinGlobalRouter
         ROUTED_ALL
     };
 
-    RouteResult route_direct_net(NetInfo *net)
+    RouteResult route_direct_net(NetInfo *net, WireId aux_src = WireId(), bool DCS_pip_only = false)
     {
-        // Lookup source and destination wires
-        WireId src = ctx->getNetinfoSourceWire(net);
-        if (src == WireId())
+        WireId src;
+        src = aux_src == WireId() ? ctx->getNetinfoSourceWire(net) : aux_src;
+        if (src == WireId()) {
             log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
                       ctx->nameOf(net->driver.port));
+        }
 
-        if (ctx->getBoundWireNet(src) != net) {
+        if (aux_src == WireId() && ctx->getBoundWireNet(src) != net) {
             ctx->bindWire(src, net, STRENGTH_LOCKED);
         }
 
         RouteResult routed = NOT_ROUTED;
-        for (auto usr : net->users.enumerate()) {
-            WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
+        for (auto usr : net->users) {
+            WireId dst = ctx->getNetinfoSinkWire(net, usr, 0);
             if (dst == WireId()) {
-                log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
-                          ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
+                log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net), ctx->nameOf(usr.cell),
+                          ctx->nameOf(usr.port));
             }
-            if (backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                    return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
-                })) {
+            bool bfs_res;
+            if (DCS_pip_only) {
+                bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                    return (is_relaxed_sink(usr) || global_DCS_pip_filter(pip));
+                });
+            } else {
+                bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                    return (is_relaxed_sink(usr) || global_pip_filter(pip));
+                });
+            }
+            if (bfs_res) {
                 routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
             } else {
                 routed = routed == NOT_ROUTED ? routed : ROUTED_PARTIALLY;
             }
         }
         if (routed == NOT_ROUTED) {
-            ctx->unbindWire(src);
+            if (aux_src == WireId()) {
+                ctx->unbindWire(src);
+            }
         }
         return routed;
     }
 
-    void route_buffered_net(NetInfo *net)
+    void route_dqce_net(NetInfo *net)
     {
-        // a) route net after buf using the buf input as source
-        CellInfo *buf_ci = net->driver.cell;
-        WireId src = ctx->getBelPinWire(buf_ci->bel, id_I);
+        // route net after dqce using source of CLKIN net
+        CellInfo *dqce_ci = net->driver.cell;
+
+        NetInfo *net_before_dqce = dqce_ci->getPort(id_CLKIN);
+        NPNR_ASSERT(net_before_dqce != nullptr);
+
+        PortRef driver = net_before_dqce->driver;
+        NPNR_ASSERT_MSG(driver_is_buf(driver) || driver_is_clksrc(driver),
+                        stringf("The input source for %s is not a clock.", ctx->nameOf(dqce_ci)).c_str());
+        WireId src;
+        // use BUF input if there is one
+        if (driver_is_buf(driver)) {
+            src = ctx->getBelPinWire(driver.cell->bel, id_I);
+        } else {
+            src = ctx->getBelPinWire(driver.cell->bel, driver.port);
+        }
 
-        NetInfo *net_before_buf = buf_ci->getPort(id_I);
-        NPNR_ASSERT(net_before_buf != nullptr);
+        RouteResult route_result = route_direct_net(net, src);
+        if (route_result == NOT_ROUTED) {
+            log_error("Can't route the %s network.\n", ctx->nameOf(net));
+        }
+        if (route_result == ROUTED_PARTIALLY) {
+            log_error("It was not possible to completely route the %s net using only global resources. This is not "
+                      "allowed for DQCE managed networks.\n",
+                      ctx->nameOf(net));
+        }
 
-        if (src == WireId()) {
-            log_error("Net '%s' has an invalid source port %s.%s\n", ctx->nameOf(net), ctx->nameOf(net->driver.cell),
-                      ctx->nameOf(net->driver.port));
+        // In networks controlled by DQCE, the source can only connect to the
+        // "spine" wires. Here we not only check this fact, but also find out
+        // how many and what kind of "spine" wires were used for network
+        // roaming.
+        for (PipId pip : ctx->getPipsDownhill(src)) {
+            if (ctx->getBoundPipNet(pip) == nullptr) {
+                continue;
+            }
+            WireId dst = ctx->getPipDstWire(pip);
+
+            BelId dqce_bel = gwu.get_dqce_bel(ctx->getWireName(dst)[1]);
+            NPNR_ASSERT(dqce_bel != BelId());
+
+            // One pseudo DQCE (either logical or custom, whatever you like)
+            // can be implemented as several hardware dqce - this is because
+            // each hardware dqce can control only one "spine", that is, a bus
+            // within one quadrant. Here we find suitable hardware dqces.
+            CellInfo *hw_dqce = ctx->getBoundBelCell(dqce_bel);
+            if (ctx->debug) {
+                log_info("  use %s spine and %s bel for '%s' hw cell.\n", ctx->nameOfWire(dst),
+                         ctx->nameOfBel(dqce_bel), ctx->nameOf(hw_dqce));
+            }
+
+            hw_dqce->setAttr(id_DQCE_PIP, Property(ctx->getPipName(pip).str(ctx)));
+            ctx->unbindPip(pip);
+            ctx->bindWire(dst, net, STRENGTH_LOCKED);
+
+            // The control network must connect the CE inputs of all hardware dqces.
+            dqce_ci->copyPortTo(id_CE, hw_dqce, id_CE);
         }
-        ctx->bindWire(src, net, STRENGTH_LOCKED);
+        net->driver.cell->disconnectPort(net->driver.port);
 
-        RouteResult routed = NOT_ROUTED;
-        for (auto usr : net->users.enumerate()) {
-            WireId dst = ctx->getNetinfoSinkWire(net, net->users.at(usr.index), 0);
-            if (dst == WireId()) {
-                log_error("Net '%s' has an invalid sink port %s.%s\n", ctx->nameOf(net),
-                          ctx->nameOf(net->users.at(usr.index).cell), ctx->nameOf(net->users.at(usr.index).port));
+        // remove the virtual DQCE
+        dqce_ci->disconnectPort(id_CLKIN);
+        dqce_ci->disconnectPort(id_CE);
+        ctx->cells.erase(dqce_ci->name);
+    }
+
+    void route_dcs_net(NetInfo *net)
+    {
+        // Since CLKOUT is responsible for only one quadrant, we will do
+        // routing not from it, but from any CLK0-3 input actually connected to
+        // the clock source.
+        CellInfo *dcs_ci = net->driver.cell;
+        NetInfo *net_before_dcs;
+        PortRef driver;
+        for (int i = 0; i < 4; ++i) {
+            net_before_dcs = dcs_ci->getPort(ctx->idf("CLK%d", i));
+            if (net_before_dcs == nullptr) {
+                continue;
             }
-            // log_info(" usr wire: %s\n", ctx->nameOfWire(dst));
-            if (backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                    return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
-                })) {
-                routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
+            driver = net_before_dcs->driver;
+            if (driver_is_buf(driver) || driver_is_clksrc(driver)) {
+                break;
+            }
+            net_before_dcs = nullptr;
+        }
+        NPNR_ASSERT_MSG(net_before_dcs != nullptr, stringf("No clock inputs for %s.", ctx->nameOf(dcs_ci)).c_str());
+
+        WireId src;
+        // use BUF input if there is one
+        if (driver_is_buf(driver)) {
+            src = ctx->getBelPinWire(driver.cell->bel, id_I);
+        } else {
+            src = ctx->getBelPinWire(driver.cell->bel, driver.port);
+        }
+
+        RouteResult route_result = route_direct_net(net, src, true);
+        if (route_result == NOT_ROUTED) {
+            log_error("Can't route the %s network.\n", ctx->nameOf(net));
+        }
+        if (route_result == ROUTED_PARTIALLY) {
+            log_error("It was not possible to completely route the %s net using only global resources. This is not "
+                      "allowed for DCS managed networks.\n",
+                      ctx->nameOf(net));
+        }
+
+        // In networks controlled by DCS, the source can only connect to the
+        // "spine" wires. Here we not only check this fact, but also find out
+        // how many and what kind of "spine" wires were used for network
+        // roaming.
+        for (PipId pip : ctx->getPipsDownhill(src)) {
+            if (ctx->getBoundPipNet(pip) == nullptr) {
+                continue;
+            }
+            WireId dst = ctx->getPipDstWire(pip);
+            BelId dcs_bel = gwu.get_dcs_bel(ctx->getWireName(dst)[1]);
+            NPNR_ASSERT(dcs_bel != BelId());
+
+            // One pseudo DCS (either logical or custom, whatever you like)
+            // can be implemented as several hardware dcs - this is because
+            // each hardware dcs can control only one "spine", that is, a bus
+            // within one quadrant. Here we find suitable hardware dcses.
+            CellInfo *hw_dcs = ctx->getBoundBelCell(dcs_bel);
+            if (ctx->debug) {
+                log_info("  use %s spine and %s bel for '%s' hw cell.\n", ctx->nameOfWire(dst), ctx->nameOfBel(dcs_bel),
+                         ctx->nameOf(hw_dcs));
+            }
+            if (dcs_ci->attrs.count(id_DCS_MODE) != 0) {
+                hw_dcs->setAttr(id_DCS_MODE, dcs_ci->attrs.at(id_DCS_MODE));
             } else {
-                routed = routed == NOT_ROUTED ? routed : ROUTED_PARTIALLY;
+                hw_dcs->setAttr(id_DCS_MODE, Property("RISING"));
             }
+
+            // Need to release the fake internal DCS PIP which is the only
+            // downhill pip for DCS inputs
+            PipId fake_pip = *ctx->getPipsDownhill(dst).begin();
+            WireId clkout_wire = ctx->getPipDstWire(fake_pip);
+            if (ctx->debug) {
+                log_info("fake pip:%s, CLKOUT src:%s\n", ctx->nameOfPip(fake_pip), ctx->nameOfWire(clkout_wire));
+            }
+            ctx->unbindPip(fake_pip);
+            ctx->bindWire(clkout_wire, net, STRENGTH_LOCKED);
+            ctx->unbindWire(dst);
+
+            // The input networks must bs same for all hardware dcs.
+            dcs_ci->copyPortTo(id_SELFORCE, hw_dcs, id_SELFORCE);
+            dcs_ci->copyPortBusTo(id_CLK, 0, false, hw_dcs, id_CLK, 0, false, 4);
+            dcs_ci->copyPortBusTo(id_CLKSEL, 0, true, hw_dcs, id_CLKSEL, 0, false, 4);
         }
-        if (routed == NOT_ROUTED) {
-            ctx->unbindWire(src);
+
+        // remove the virtual DCS
+        dcs_ci->disconnectPort(id_SELFORCE);
+        dcs_ci->disconnectPort(id_CLKOUT);
+        for (int i = 0; i < 4; ++i) {
+            dcs_ci->disconnectPort(ctx->idf("CLKSEL[%d]", i));
+            dcs_ci->disconnectPort(ctx->idf("CLK%d", i));
+        }
+        log_info("    '%s' net was routed.\n", ctx->nameOf(net));
+        ctx->cells.erase(dcs_ci->name);
+    }
+
+    void route_buffered_net(NetInfo *net)
+    {
+        // a) route net after buf using the buf input as source
+        CellInfo *buf_ci = net->driver.cell;
+        WireId src = ctx->getBelPinWire(buf_ci->bel, id_I);
+
+        NetInfo *net_before_buf = buf_ci->getPort(id_I);
+        NPNR_ASSERT(net_before_buf != nullptr);
+
+        RouteResult route_result = route_direct_net(net, src);
+        if (route_result == NOT_ROUTED || route_result == ROUTED_PARTIALLY) {
+            log_error("Can't route the %s net. It might be worth removing the BUFG buffer flag.\n", ctx->nameOf(net));
         }
 
         // b) route net before buf from whatever to the buf input
@@ -240,64 +457,30 @@ struct GowinGlobalRouter
         CellInfo *true_src_ci = net_before_buf->driver.cell;
         src = ctx->getBelPinWire(true_src_ci->bel, net_before_buf->driver.port);
         ctx->bindWire(src, net, STRENGTH_LOCKED);
-        ctx->unbindWire(dst);
         backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) { return true; });
         // remove net
         buf_ci->movePortTo(id_O, true_src_ci, net_before_buf->driver.port);
         net_before_buf->driver.cell = nullptr;
+
+        log_info("    '%s' net was routed.\n", ctx->nameOf(net));
     }
 
     void route_clk_net(NetInfo *net)
     {
-        RouteResult res = route_direct_net(net);
-        if (res) {
-            log_info("    routed net '%s' using global resources %s.\n", ctx->nameOf(net),
-                     res == ROUTED_ALL ? "only" : "partially");
+        RouteResult route_result = route_direct_net(net);
+        if (route_result != NOT_ROUTED) {
+            log_info("    '%s' net was routed  using global resources %s.\n", ctx->nameOf(net),
+                     route_result == ROUTED_ALL ? "only" : "partially");
         }
     }
 
-    bool driver_is_buf(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_BUFG, id_O); }
-
-    bool driver_is_clksrc(const PortRef &driver)
-    {
-        // dedicated pins
-        if (CellTypePort(driver) == CellTypePort(id_IBUF, id_O)) {
-
-            NPNR_ASSERT(driver.cell->bel != BelId());
-            IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
-            for (size_t i = 0; i < pin_func.size(); ++i) {
-                if (ctx->debug) {
-                    log_info("bel:%s, pin func: %zu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
-                             pin_func[i].str(ctx).c_str());
-                }
-                if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
-                    if (ctx->debug) {
-                        log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
-                                 pin_func[i].c_str(ctx));
-                    }
-                    return true;
-                }
-            }
-        }
-        // PLL outputs
-        if (driver.cell->type.in(id_rPLL, id_PLLVR)) {
-            if (driver.port.in(id_CLKOUT, id_CLKOUTD, id_CLKOUTD3, id_CLKOUTP)) {
-                if (ctx->debug) {
-                    log_info("PLL out:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
-                             driver.port.c_str(ctx));
-                }
-                return true;
-            }
-        }
-        return false;
-    }
-
     void run(void)
     {
         log_info("Routing globals...\n");
 
-        std::vector<IdString> routed_nets;
-        // buffered nets first
+        std::vector<IdString> dqce_nets, dcs_nets, buf_nets, clk_nets;
+
+        // Determining the priority of network routing
         for (auto &net : ctx->nets) {
             NetInfo *ni = net.second.get();
             CellInfo *drv = ni->driver.cell;
@@ -308,22 +491,59 @@ struct GowinGlobalRouter
                 continue;
             }
             if (driver_is_buf(ni->driver)) {
-                if (ctx->verbose) {
-                    log_info("route buffered net '%s'\n", ctx->nameOf(ni));
+                buf_nets.push_back(net.first);
+            } else {
+                if (driver_is_clksrc(ni->driver)) {
+                    clk_nets.push_back(net.first);
+                } else {
+                    if (driver_is_dqce(ni->driver)) {
+                        dqce_nets.push_back(net.first);
+                    } else {
+                        if (driver_is_dcs(ni->driver)) {
+                            dcs_nets.push_back(net.first);
+                        }
+                    }
                 }
-                route_buffered_net(ni);
-                routed_nets.push_back(net.first);
-                continue;
             }
         }
-        for (auto &net : ctx->nets) {
-            if (std::find(routed_nets.begin(), routed_nets.end(), net.first) != routed_nets.end()) {
+
+        // nets with DQCE
+        for (IdString net_name : dqce_nets) {
+            NetInfo *ni = ctx->nets.at(net_name).get();
+            if (ctx->verbose) {
+                log_info("route dqce net '%s'\n", ctx->nameOf(ni));
+            }
+            route_dqce_net(ni);
+        }
+
+        // nets with DCS
+        for (IdString net_name : dcs_nets) {
+            NetInfo *ni = ctx->nets.at(net_name).get();
+            if (ctx->verbose) {
+                log_info("route dcs net '%s'\n", ctx->nameOf(ni));
+            }
+            route_dcs_net(ni);
+        }
+
+        // buffered nets
+        for (IdString net_name : buf_nets) {
+            NetInfo *ni = ctx->nets.at(net_name).get();
+            CellInfo *drv = ni->driver.cell;
+            if (drv == nullptr || ni->users.empty()) {
                 if (ctx->debug) {
-                    log_info("skip already routed net:%s\n", net.first.c_str(ctx));
+                    log_info("skip empty or driverless net:%s\n", ctx->nameOf(ni));
                 }
                 continue;
             }
-            NetInfo *ni = net.second.get();
+            if (ctx->verbose) {
+                log_info("route buffered net '%s'\n", ctx->nameOf(ni));
+            }
+            route_buffered_net(ni);
+        }
+
+        // clock nets
+        for (IdString net_name : clk_nets) {
+            NetInfo *ni = ctx->nets.at(net_name).get();
             CellInfo *drv = ni->driver.cell;
             if (drv == nullptr || ni->users.empty()) {
                 if (ctx->debug) {
@@ -331,13 +551,10 @@ struct GowinGlobalRouter
                 }
                 continue;
             }
-            if (driver_is_clksrc(ni->driver)) {
-                if (ctx->verbose) {
-                    log_info("route clock net '%s'\n", ctx->nameOf(ni));
-                }
-                route_clk_net(ni);
-                continue;
+            if (ctx->verbose) {
+                log_info("route clock net '%s'\n", ctx->nameOf(ni));
             }
+            route_clk_net(ni);
         }
     }
 };
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index b9ca90707d..6ce7916c0a 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -186,7 +186,10 @@ void GowinImpl::init(Context *ctx)
 }
 
 // We do not allow the use of global wires that bypass a special router.
-bool GowinImpl::checkPipAvail(PipId pip) const { return !gwu.is_global_pip(pip); }
+bool GowinImpl::checkPipAvail(PipId pip) const
+{
+    return (ctx->getWireConstantValue(ctx->getPipSrcWire(pip)) != IdString()) || (!gwu.is_global_pip(pip));
+}
 
 void GowinImpl::pack()
 {
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index b2fc5f80ef..a9f247d891 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -90,10 +90,19 @@ NPNR_PACKED_STRUCT(struct Bottom_io_POD {
     RelSlice<Bottom_io_cnd_POD> conditions;
 });
 
+NPNR_PACKED_STRUCT(struct Spine_bel_POD {
+    int32_t spine;
+    int32_t bel_x;
+    int32_t bel_y;
+    int32_t bel_z;
+});
+
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     int32_t chip_flags;
     Bottom_io_POD bottom_io;
     RelSlice<IdString> diff_io_types;
+    RelSlice<Spine_bel_POD> dqce_bels;
+    RelSlice<Spine_bel_POD> dcs_bels;
     // chip flags
     static constexpr int32_t HAS_SP32 = 1;
     static constexpr int32_t NEED_SP_FIX = 2;
@@ -134,6 +143,9 @@ enum
     VSS_Z = 278,
     BANDGAP_Z = 279,
 
+    DQCE_Z = 280, // : 286 reserve for 6 DQCEs
+    DCS_Z = 286,  // : 287 reserve for 2 DCSs
+
     // The two least significant bits encode Z for 9-bit adders and
     // multipliers, if they are equal to 0, then we get Z of their common
     // 18-bit equivalent.
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index a6cffd358b..75fda033ef 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -49,6 +49,9 @@
 GND_Z   = 278
 BANDGAP_Z = 279
 
+DQCE_Z = 280 # : 286 reserve for 6 DQCEs
+DCS_Z  = 286 # : 287 reserve for 2 DCSs
+
 DSP_Z          = 509
 
 DSP_0_Z        = 511 # DSP macro 0
@@ -135,12 +138,30 @@ def serialise_lists(self, context: str, bba: BBAWriter):
     def serialise(self, context: str, bba: BBAWriter):
         bba.slice(f"{context}_conditions", len(self.conditions))
 
+# spine -> bel for different bels
+@dataclass
+class SpineBel(BBAStruct):
+    spine: IdString
+    bel_x: int
+    bel_y: int
+    bel_z: int
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.spine.index)
+        bba.u32(self.bel_x)
+        bba.u32(self.bel_y)
+        bba.u32(self.bel_z)
+
 @dataclass
 class ChipExtraData(BBAStruct):
     strs: StringPool
     flags: int
     bottom_io: BottomIO
     diff_io_types: list[IdString] = field(default_factory = list)
+    dqce_bels: list[SpineBel] = field(default_factory = list)
+    dcs_bels: list[SpineBel] = field(default_factory = list)
 
     def create_bottom_io(self):
         self.bottom_io = BottomIO()
@@ -151,16 +172,30 @@ def add_bottom_io_cnd(self, net_a: str, net_b: str):
     def add_diff_io_type(self, diff_type: str):
         self.diff_io_types.append(self.strs.id(diff_type))
 
+    def add_dqce_bel(self, spine: str, x: int, y: int, z: int):
+        self.dqce_bels.append(SpineBel(self.strs.id(spine), x, y, z))
+
+    def add_dcs_bel(self, spine: str, x: int, y: int, z: int):
+        self.dcs_bels.append(SpineBel(self.strs.id(spine), x, y, z))
+
     def serialise_lists(self, context: str, bba: BBAWriter):
         self.bottom_io.serialise_lists(f"{context}_bottom_io", bba)
         bba.label(f"{context}_diff_io_types")
         for i, diff_io_type in enumerate(self.diff_io_types):
             bba.u32(diff_io_type.index)
+        bba.label(f"{context}_dqce_bels")
+        for i, t in enumerate(self.dqce_bels):
+            t.serialise(f"{context}_dqce_bel{i}", bba)
+        bba.label(f"{context}_dcs_bels")
+        for i, t in enumerate(self.dcs_bels):
+            t.serialise(f"{context}_dcs_bel{i}", bba)
 
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.flags)
         self.bottom_io.serialise(f"{context}_bottom_io", bba)
         bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
+        bba.slice(f"{context}_dqce_bels", len(self.dqce_bels))
+        bba.slice(f"{context}_dcs_bels", len(self.dcs_bels))
 
 @dataclass
 class PadExtraData(BBAStruct):
@@ -296,7 +331,10 @@ def get_wire_type(name):
             tt.create_wire(dst, get_wire_type(dst))
         for src in srcs.keys():
             if not tt.has_wire(src):
-                tt.create_wire(src, get_wire_type(src))
+                if src in {"VSS", "VCC"}:
+                    tt.create_wire(src, get_wire_type(src), const_value = src)
+                else:
+                    tt.create_wire(src, get_wire_type(src))
             tt.create_pip(src, dst)
 
     # clock wires
@@ -320,6 +358,11 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
                 tt.create_wire(src, "HCLK")
             tt.create_pip(src, dst)
 
+# map spine -> dqce bel
+dqce_bels = {}
+# map spine -> dcs bel
+dcs_bels = {}
+
 def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.extra_func:
         return
@@ -328,7 +371,8 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
             osc_type = desc['type']
             portmap = db.grid[y][x].bels[osc_type].portmap
             for port, wire in portmap.items():
-                tt.create_wire(wire, port)
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire, port)
             bel = tt.create_bel(osc_type, osc_type, z = OSC_Z)
             for port, wire in portmap.items():
                 if 'OUT' in port:
@@ -337,15 +381,58 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                     tt.add_bel_pin(bel, port, wire, PinType.INPUT)
         elif func == 'gsr':
             wire = desc['wire']
-            tt.create_wire(wire, "GSRI")
+            if not tt.has_wire(wire):
+                tt.create_wire(wire)
             bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
             tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
         elif func == 'bandgap':
             wire = desc['wire']
-            tt.create_wire(wire, "BGEN")
+            if not tt.has_wire(wire):
+                tt.create_wire(wire)
             bel = tt.create_bel("BANDGAP", "BANDGAP", z = BANDGAP_Z)
             tt.add_bel_pin(bel, "BGEN", wire, PinType.INPUT)
-        if func == 'io16':
+        elif func == 'dqce':
+            for idx in range(6):
+                bel_z = DQCE_Z + idx
+                bel = tt.create_bel(f"DQCE{idx}", "DQCE", bel_z)
+                wire = desc[idx]['clkin']
+                dqce_bels[wire] = (x, y, bel_z)
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire, "GLOBAL_CLK")
+                tt.add_bel_pin(bel, "CLKIN", wire, PinType.INPUT)
+                tt.add_bel_pin(bel, "CLKOUT", wire, PinType.OUTPUT)
+                wire = desc[idx]['ce']
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire)
+                tt.add_bel_pin(bel, "CE", wire, PinType.INPUT)
+        elif func == 'dcs':
+            for idx in range(2):
+                if idx not in desc:
+                    continue
+                bel_z = DCS_Z + idx
+                bel = tt.create_bel(f"DCS{idx}", "DCS", bel_z)
+                wire = desc[idx]['clkout']
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire)
+                tt.add_bel_pin(bel, "CLKOUT", wire, PinType.OUTPUT)
+                clkout_wire = wire
+                for clk_idx, wire in enumerate(desc[idx]['clk']):
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "GLOBAL_CLK")
+                    tt.add_bel_pin(bel, f"CLK{clk_idx}", wire, PinType.INPUT)
+                    # This is a fake PIP that allows routing “through” this
+                    # primitive from the CLK input to the CLKOUT output.
+                    tt.create_pip(wire, clkout_wire)
+                    dcs_bels[wire] = (x, y, bel_z)
+                for i, wire in enumerate(desc[idx]['clksel']):
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire)
+                    tt.add_bel_pin(bel, f"CLKSEL{i}", wire, PinType.INPUT)
+                wire = desc[idx]['selforce']
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire)
+                tt.add_bel_pin(bel, "SELFORCE", wire, PinType.INPUT)
+        elif func == 'io16':
             role = desc['role']
             if role == 'MAIN':
                 y_off, x_off = desc['pair']
@@ -367,13 +454,13 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                         tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
                     else:
                         tt.add_bel_pin(bel, port, wire, PinType.INPUT)
-        if func == 'buf':
+        elif func == 'buf':
             for buf_type, wires in desc.items():
                 for i, wire in enumerate(wires):
                     if not tt.has_wire(wire):
                         tt.create_wire(wire, "TILE_CLK")
                     wire_out = f'{buf_type}{i}_O'
-                    tt.create_wire(wire_out, "TILE_CLK")
+                    tt.create_wire(wire_out, "BUFG_O")
                     # XXX make Z from buf_type
                     bel = tt.create_bel(f'{buf_type}{i}', buf_type, z = BUFG_Z + i)
                     bel.flags = BEL_FLAG_GLOBAL
@@ -464,11 +551,11 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, td
 
     if x == 0 and y == 0:
         # GND is the logic low level generator
-        tt.create_wire('VSS', 'GND')
+        tt.create_wire('VSS', 'GND', const_value = 'VSS')
         gnd = tt.create_bel('GND', 'GND', z = GND_Z)
         tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
         # VCC is the logic high level generator
-        tt.create_wire('VCC', 'VCC')
+        tt.create_wire('VCC', 'VCC', const_value = 'VCC')
         gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
         tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
 
@@ -1005,6 +1092,12 @@ def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
         chip.extra_data.add_bottom_io_cnd(net_a, net_b)
     for diff_type in db.diff_io_types:
         chip.extra_data.add_diff_io_type(diff_type)
+    # create spine->dqce bel map
+    for spine, bel in dqce_bels.items():
+        chip.extra_data.add_dqce_bel(spine, bel[0], bel[1], bel[2])
+    # create spine->dcs bel map
+    for spine, bel in dcs_bels.items():
+        chip.extra_data.add_dcs_bel(spine, bel[0], bel[1], bel[2])
 
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 37cff7077c..5bf398d9e3 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -64,6 +64,28 @@ BelId GowinUtils::get_pll_bel(BelId io_bel, IdString type)
     return BelId();
 }
 
+BelId GowinUtils::get_dqce_bel(IdString spine_name)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    for (auto &spine_bel : extra->dqce_bels) {
+        if (IdString(spine_bel.spine) == spine_name) {
+            return ctx->getBelByLocation(Loc(spine_bel.bel_x, spine_bel.bel_y, spine_bel.bel_z));
+        }
+    }
+    return BelId();
+}
+
+BelId GowinUtils::get_dcs_bel(IdString spine_name)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    for (auto &spine_bel : extra->dcs_bels) {
+        if (IdString(spine_bel.spine) == spine_name) {
+            return ctx->getBelByLocation(Loc(spine_bel.bel_x, spine_bel.bel_y, spine_bel.bel_z));
+        }
+    }
+    return BelId();
+}
+
 bool GowinUtils::is_simple_io_bel(BelId bel)
 {
     return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 7b76ea9aae..c280b271f7 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -33,6 +33,8 @@ struct GowinUtils
     bool is_simple_io_bel(BelId bel);
     Loc get_pair_iologic_bel(Loc loc);
     BelId get_io_bel_from_iologic(BelId bel);
+    BelId get_dqce_bel(IdString spine_name);
+    BelId get_dcs_bel(IdString spine_name);
 
     // BSRAM
     bool has_SP32(void);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 2faf1df0c1..c34a88cf95 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -165,9 +165,9 @@ struct GowinPacker
 
     BelId bind_io(CellInfo &ci)
     {
-        BelId bel = ctx->getBelByName(IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()));
+        BelId bel = ctx->getBelByNameStr(ci.attrs.at(id_BEL).as_string());
         if (bel == BelId()) {
-            log_error("No bel named %s\n", IdStringList::parse(ctx, ci.attrs.at(id_BEL).as_string()).str(ctx).c_str());
+            log_error("No bel named %s\n", ci.attrs.at(id_BEL).as_string().c_str());
         }
         if (!ctx->checkBelAvail(bel)) {
             log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
@@ -2999,18 +2999,83 @@ struct GowinPacker
             ctx->createCell(buf_name, id_BUFG);
             CellInfo *buf_ci = ctx->cells.at(buf_name).get();
             buf_ci->addInput(id_I);
-            NetInfo *buf_ni = ctx->createNet(ctx->idf("$PACKER_BUF_%s", net.first.c_str(ctx)));
-
-            if (ctx->verbose) {
-                log_info("Create buf '%s' with IN net '%s'\n", buf_name.c_str(ctx), buf_ni->name.c_str(ctx));
-            }
             // move driver
             CellInfo *driver_cell = ni.driver.cell;
             IdString driver_port = ni.driver.port;
 
             driver_cell->movePortTo(driver_port, buf_ci, id_O);
-            buf_ci->connectPort(id_I, buf_ni);
-            driver_cell->connectPort(driver_port, buf_ni);
+            buf_ci->connectPorts(id_I, driver_cell, driver_port);
+        }
+    }
+
+    // =========================================
+    // Create DQCEs
+    // =========================================
+    void pack_dqce()
+    {
+        // At the placement stage, nothing can be said definitively about DQCE,
+        // so we make user cells virtual but allocate all available bels by
+        // creating and placing cells - we will use some of them after, and
+        // delete the rest.
+        // We do this here because the decision about which physical DQCEs to
+        // use is made during routing, but some of the information (let’s say
+        // mapping cell pins -> bel pins) is filled in before routing.
+        bool grab_bels = false;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (ci.type == id_DQCE) {
+                ci.pseudo_cell = std::make_unique<RegionPlug>(Loc(0, 0, 0));
+                grab_bels = true;
+            }
+        }
+        if (grab_bels) {
+            for (int i = 0; i < 32; ++i) {
+                BelId dqce_bel = gwu.get_dqce_bel(ctx->idf("SPINE%d", i));
+                if (dqce_bel != BelId()) {
+                    IdString dqce_name = ctx->idf("$PACKER_DQCE_SPINE%d", i);
+                    CellInfo *dqce = ctx->createCell(dqce_name, id_DQCE);
+                    dqce->addInput(id_CE);
+                    ctx->bindBel(dqce_bel, dqce, STRENGTH_LOCKED);
+                }
+            }
+        }
+    }
+
+    // =========================================
+    // Create DCSs
+    // =========================================
+    void pack_dcs()
+    {
+        // At the placement stage, nothing can be said definitively about DCS,
+        // so we make user cells virtual but allocate all available bels by
+        // creating and placing cells - we will use some of them after, and
+        // delete the rest.
+        // We do this here because the decision about which physical DCEs to
+        // use is made during routing, but some of the information (let’s say
+        // mapping cell pins -> bel pins) is filled in before routing.
+        bool grab_bels = false;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (ci.type == id_DCS) {
+                ci.pseudo_cell = std::make_unique<RegionPlug>(Loc(0, 0, 0));
+                grab_bels = true;
+            }
+        }
+        if (grab_bels) {
+            for (int i = 0; i < 8; ++i) {
+                BelId dcs_bel = gwu.get_dcs_bel(ctx->idf("P%d%dA", 1 + (i % 4), 6 + (i >> 2)));
+                if (dcs_bel != BelId()) {
+                    IdString dcs_name = ctx->idf("$PACKER_DCS_SPINE%d", 8 * (i % 4) + 6 + (i >> 2));
+                    CellInfo *dcs = ctx->createCell(dcs_name, id_DCS);
+                    dcs->addInput(id_SELFORCE);
+                    for (int j = 0; j < 4; ++j) {
+                        dcs->addInput(ctx->idf("CLK%d", j));
+                        dcs->addInput(ctx->idf("CLKSEL%d", j));
+                    }
+                    dcs->addOutput(id_CLKOUT);
+                    ctx->bindBel(dcs_bel, dcs, STRENGTH_LOCKED);
+                }
+            }
         }
     }
 
@@ -3061,6 +3126,13 @@ struct GowinPacker
         ctx->check();
 
         pack_buffered_nets();
+        ctx->check();
+
+        pack_dqce();
+        ctx->check();
+
+        pack_dcs();
+        ctx->check();
 
         ctx->fixupHierarchy();
         ctx->check();

From 11d335c7cec7bc62781166926ca43ab645cc2604 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 14 Jul 2024 18:57:07 +1000
Subject: [PATCH 625/712] Gowin. Fix GW2A-18(c) DCS and DQCE

We filter out PIPs from these chips that bypass DCS.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc | 32 +++++++++++++++++
 himbaechel/uarch/gowin/globals.cc   | 53 +++++++++++++++++++++++++----
 2 files changed, 78 insertions(+), 7 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 5aeac7489c..4eb7badf25 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1085,6 +1085,38 @@ X(LOCK)
 X(AD)
 X(DI)
 X(DO)
+X(P16A)
+X(P16B)
+X(P16C)
+X(P16D)
+X(P17A)
+X(P17B)
+X(P17C)
+X(P17D)
+X(P26A)
+X(P26B)
+X(P26C)
+X(P26D)
+X(P27A)
+X(P27B)
+X(P27C)
+X(P27D)
+X(P36A)
+X(P36B)
+X(P36C)
+X(P36D)
+X(P37A)
+X(P37B)
+X(P37C)
+X(P37D)
+X(P46A)
+X(P46B)
+X(P46C)
+X(P46D)
+X(P47A)
+X(P47B)
+X(P47C)
+X(P47D)
 
 // PLL parameters
 X(CLKOUTPS)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 011e2f371f..48a45d26c4 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -48,7 +48,6 @@ struct GowinGlobalRouter
         auto is_local = [&](IdString wire_type) {
             return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
         };
-
         WireId src, dst;
         src = ctx->getPipSrcWire(pip);
         dst = ctx->getPipDstWire(pip);
@@ -70,6 +69,40 @@ struct GowinGlobalRouter
         return res;
     }
 
+    bool global_DQCE_pip_filter(PipId pip) const
+    {
+        auto is_local = [&](IdString wire_type) {
+            return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
+        };
+        auto is_dcs_input = [&](IdString wire_name) {
+            return wire_name.in(id_P16A, id_P16B, id_P16C, id_P16D, id_P17A, id_P17B, id_P17C, id_P17D, id_P26A,
+                                id_P26B, id_P26C, id_P26D, id_P27A, id_P27B, id_P27C, id_P27D, id_P36A, id_P36B,
+                                id_P36C, id_P36D, id_P37A, id_P37B, id_P37C, id_P37D, id_P46A, id_P46B, id_P46C,
+                                id_P46D, id_P47A, id_P47B, id_P47C, id_P47D);
+        };
+
+        WireId src, dst;
+        src = ctx->getPipSrcWire(pip);
+        dst = ctx->getPipDstWire(pip);
+        IdString src_name = ctx->getWireName(dst)[1];
+        IdString dst_name = ctx->getWireName(dst)[1];
+        bool not_dsc_pip = dst_name != id_CLKOUT && !is_dcs_input(src_name);
+        IdString src_type = ctx->getWireType(src);
+        IdString dst_type = ctx->getWireType(dst);
+        bool src_valid = not_dsc_pip && src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
+        bool dst_valid = not_dsc_pip && dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
+
+        bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        if (ctx->debug && false /*&& res*/) {
+            log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
+                     ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
+                     src_type.c_str(ctx));
+            log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
+                     is_local(src_type), is_local(dst_type));
+        }
+        return res;
+    }
+
     bool global_DCS_pip_filter(PipId pip) const
     {
         auto is_local = [&](IdString wire_type) {
@@ -233,7 +266,7 @@ struct GowinGlobalRouter
         ROUTED_ALL
     };
 
-    RouteResult route_direct_net(NetInfo *net, WireId aux_src = WireId(), bool DCS_pip_only = false)
+    RouteResult route_direct_net(NetInfo *net, WireId aux_src = WireId(), bool DCS_pips = false, bool DQCE_pips = false)
     {
         WireId src;
         src = aux_src == WireId() ? ctx->getNetinfoSourceWire(net) : aux_src;
@@ -254,14 +287,20 @@ struct GowinGlobalRouter
                           ctx->nameOf(usr.port));
             }
             bool bfs_res;
-            if (DCS_pip_only) {
+            if (DCS_pips) {
                 bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
                     return (is_relaxed_sink(usr) || global_DCS_pip_filter(pip));
                 });
             } else {
-                bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                    return (is_relaxed_sink(usr) || global_pip_filter(pip));
-                });
+                if (DQCE_pips) {
+                    bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                        return (is_relaxed_sink(usr) || global_DQCE_pip_filter(pip));
+                    });
+                } else {
+                    bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
+                        return (is_relaxed_sink(usr) || global_pip_filter(pip));
+                    });
+                }
             }
             if (bfs_res) {
                 routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
@@ -296,7 +335,7 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(net, src);
+        RouteResult route_result = route_direct_net(net, src, false, true);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }

From e9e7dce23d537d4318dfadcf2cd22310b9fdd11a Mon Sep 17 00:00:00 2001
From: Saviour Owolabi <42647840+Seyviour@users.noreply.github.com>
Date: Sat, 3 Aug 2024 14:57:22 +0100
Subject: [PATCH 626/712] Himbaechel Gowin: HCLK Support (#1340)

* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2

* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2

* Gowin Himbaechel: HCLK Bug fixes and corrections
---
 himbaechel/uarch/gowin/constids.inc      |  13 +
 himbaechel/uarch/gowin/cst.cc            |  58 ++++-
 himbaechel/uarch/gowin/globals.cc        |  10 +
 himbaechel/uarch/gowin/gowin.cc          | 302 ++++++++++++++++++++++-
 himbaechel/uarch/gowin/gowin.h           |  24 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  52 ++++
 himbaechel/uarch/gowin/gowin_utils.cc    | 142 +++++++++++
 himbaechel/uarch/gowin/gowin_utils.h     |  53 ++++
 himbaechel/uarch/gowin/pack.cc           |  98 ++++----
 9 files changed, 695 insertions(+), 57 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 4eb7badf25..fcadd941ef 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1239,3 +1239,16 @@ X(DQCE_PIP)
 X(DCS_USED)
 X(SELFORCE)
 
+//HCLK Bels
+X(CLKDIV)
+X(CLKDIV2)
+
+//HCLK Ports
+X(HCLKIN)
+X(RESETN)
+// X(CALIB)
+// X(CLKOUT)
+
+//HCLK Parameters
+X(DIV_MODE)
+X(GSREN)
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
index e4df3f6119..310e1406f2 100644
--- a/himbaechel/uarch/gowin/cst.cc
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -51,6 +51,27 @@ struct GowinCstReader
         return Loc(col - 1, row - 1, z);
     }
 
+    BelId getConstrainedHCLKBel(std::smatch match, int maxX, int maxY)
+    {
+        int idx = std::stoi(match[3]);
+        int bel_z = BelZ::CLKDIV_0_Z + 2 * idx;
+
+        std::string side = match[2].str();
+        bool lr = (side == "LEFT") || (side == "RIGHT");
+        int y_coord = (side == "BOTTOM") ? maxY - 1 : 0;
+        int x_coord = (side == "RIGHT") ? maxX - 1 : 0;
+
+        for (auto &bel : ctx->getBelsInBucket(ctx->getBelBucketForCellType(id_CLKDIV))) {
+            auto this_loc = ctx->getBelLocation(bel);
+            if (lr && this_loc.x == x_coord && this_loc.z == bel_z && this_loc.y != 0 &&
+                this_loc.y != maxY - 1) // left or right side
+                return bel;
+            else if (!lr && this_loc.y == y_coord && this_loc.z == bel_z) // top or bottom side
+                return bel;
+        }
+        return BelId();
+    }
+
     bool run(void)
     {
         pool<std::pair<IdString, IdStringList>> constrained_cells;
@@ -71,15 +92,19 @@ struct GowinCstReader
             std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
             std::regex inslocre =
                     std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
+            std::regex hclkre =
+                    std::regex("INS_LOC +\"([^\"]+)\" +(TOP|RIGHT|BOTTOM|LEFT)SIDE\\[([0,1])\\] *;*[\\s\\S]*");
             std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*[\\s\\S]*");
             std::smatch match, match_attr, match_pinloc;
             std::string line, pinline;
+            std::vector<IdStringList> constrained_clkdivs;
             enum
             {
                 ioloc,
                 ioport,
                 insloc,
-                clock
+                clock,
+                hclk
             } cst_type;
 
             while (!in.eof()) {
@@ -95,10 +120,14 @@ struct GowinCstReader
                             if (std::regex_match(line, match, inslocre)) {
                                 cst_type = insloc;
                             } else {
-                                if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
-                                    log_warning("Invalid constraint: %s\n", line.c_str());
+                                if (std::regex_match(line, match, hclkre)) {
+                                    cst_type = hclk;
+                                } else {
+                                    if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
+                                        log_warning("Invalid constraint: %s\n", line.c_str());
+                                    }
+                                    continue;
                                 }
-                                continue;
                             }
                         }
                     }
@@ -166,6 +195,27 @@ struct GowinCstReader
                         }
                     }
                 } break;
+                case hclk: {
+                    IdString cell_type = it->second->type;
+                    if (cell_type != id_CLKDIV) {
+                        log_error("Unsupported or invalid cell type %s for hclk\n", cell_type.c_str(ctx));
+                    }
+                    BelId hclk_bel = getConstrainedHCLKBel(match, ctx->getGridDimX(), ctx->getGridDimY());
+                    if (hclk_bel != BelId()) {
+                        auto hclk_bel_name = ctx->getBelName(hclk_bel);
+                        if (std::find(constrained_clkdivs.begin(), constrained_clkdivs.end(), hclk_bel_name) !=
+                            constrained_clkdivs.end()) {
+                            log_error("Only one CLKDIV can be placed at %sSIDE[%s]\n", match[2].str().c_str(),
+                                      match[3].str().c_str());
+                        }
+                        constrained_clkdivs.push_back(hclk_bel_name);
+                        it->second->setAttr(id_BEL, ctx->getBelName(hclk_bel).str(ctx));
+                        debug_cell(it->second->name, ctx->getBelName(hclk_bel));
+                    } else {
+                        log_error("No Bel of type CLKDIV found at constrained location %sSIDE[%s]\n",
+                                  match[2].str().c_str(), match[3].str().c_str());
+                    }
+                } break;
                 default: { // IO_PORT attr=value
                     std::string attr_val = match[2];
                     while (std::regex_match(attr_val, match_attr, port_attrre)) {
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 48a45d26c4..e510174b49 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -256,6 +256,16 @@ struct GowinGlobalRouter
                 return true;
             }
         }
+        // HCLK outputs
+        if (driver.cell->type.in(id_CLKDIV, id_CLKDIV2)) {
+            if (driver.port.in(id_CLKOUT)) {
+                if (ctx->debug) {
+                    log_info("%s out:%s:%s\n", driver.cell->type.c_str(ctx),
+                             ctx->getBelName(driver.cell->bel).str(ctx).c_str(), driver.port.c_str(ctx));
+                }
+                return true;
+            }
+        }
         return false;
     }
 
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 6ce7916c0a..7f4ae89aa8 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -71,6 +71,9 @@ struct GowinImpl : HimbaechelAPI
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
 
+    // Remember HCLK sections that have been reserved to route HCLK signals
+    std::set<BelId> routing_reserved_hclk_sections;
+
     // dsp control nets
     // Each DSP and each macro has a small set of control wires that are
     // allocated to internal primitives as needed. It is assumed that most
@@ -87,9 +90,14 @@ struct GowinImpl : HimbaechelAPI
                                           // since this information is already lost during unbinding
     void adjust_dsp_pin_mapping(void);
 
+    // Place explicityl constrained or implicitly constrained (by IOLOGIC) CLKDIV and CLKDIV2 cells
+    // to avoid routing conflicts and maximize utilization
+    void place_constrained_hclk_cells();
+
     // bel placement validation
     bool slice_valid(int x, int y, int z) const;
     bool dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const;
+    bool hclk_valid(BelId bel, IdString bel_type) const;
 };
 
 struct GowinArch : HimbaechelArch
@@ -259,7 +267,250 @@ void GowinImpl::adjust_dsp_pin_mapping(void)
     }
 }
 
-void GowinImpl::prePlace() { assign_cell_info(); }
+/*
+   Each HCLK section can serve one of three purposes:
+       1. A simple routing path to IOLOGIC FCLK
+       2. CLKDIV2
+       3. CLKDIV (only one section at any time)
+
+   Our task is to distribute HCLK signal providers to sections in a way that maximizes utilization while
+   enforcing user constraints on CLKDIV placement. We achieve this by solving two bipartite matchings:
+   - The first determines the best HCLK to place a CLKDIV within the established graph. This is then refined
+       to determine what section to assign the CLKDIV to based on what IOLOGIC it connects to
+   - The second determines which HCLK sections to use as CLKDIV2 or to reserve for routing.
+*/
+void GowinImpl::place_constrained_hclk_cells()
+{
+    log_info("Running custom HCLK placer...\n");
+    std::map<IdStringList, IdString> constrained_clkdivs;
+    std::map<BelId, std::set<std::pair<IdString, int>>> bel_cell_map;
+    std::vector<std::pair<IdString, int>> alias_cells;
+    std::map<std::pair<IdString, int>, BelId> final_placement;
+
+    std::set<IdString> seen_hclk_users;
+    for (auto &cell : ctx->cells) {
+        auto ci = cell.second.get();
+
+        if (is_clkdiv(ci) && ci->attrs.count(id_BEL)) {
+            BelId constrained_bel = ctx->getBelByName(IdStringList::parse(ctx, ci->attrs.at(id_BEL).as_string()));
+            NPNR_ASSERT(constrained_bel != BelId() && ctx->getBelType(constrained_bel) == id_CLKDIV);
+            auto hclk_id_loc = gwu.get_hclk_id(constrained_bel);
+            constrained_clkdivs[hclk_id_loc] = ci->name;
+        }
+
+        if ((seen_hclk_users.find(ci->name) != seen_hclk_users.end()))
+            continue;
+
+        if (((is_iologici(ci) || is_iologico(ci)) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
+            NetInfo *hclk_net = ci->getPort(id_FCLK);
+            if (hclk_net)
+                continue;
+            CellInfo *hclk_driver = hclk_net->driver.cell;
+            if (!hclk_driver)
+                continue;
+            if (chip.str(ctx) == "GW1N-9C" && hclk_driver->type != id_CLKDIV2) {
+                // CLKDIV doesn't seem to connect directly to FCLK on this device, and routing is guaranteed to succeed.
+                continue;
+            }
+
+            int alias_count = 0;
+            std::set<std::set<BelId>> seen_options;
+            for (auto user : hclk_net->users) {
+                std::vector<BelId> bel_candidates;
+                std::set<BelId> these_options;
+
+                if (!(user.port == id_FCLK && (is_iologici(user.cell) || is_iologico(user.cell)) &&
+                      !user.cell->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC)))
+                    continue;
+                if (seen_hclk_users.find(user.cell->name) != seen_hclk_users.end())
+                    continue;
+                seen_hclk_users.insert(user.cell->name);
+
+                if (ctx->debug) {
+                    log_info("Custom HCLK Placer: Found HCLK user: %s\n", user.cell->name.c_str(ctx));
+                }
+
+                gwu.find_connected_bels(user.cell, id_FCLK, id_CLKDIV2, id_CLKOUT, 16, bel_candidates);
+                these_options.insert(bel_candidates.begin(), bel_candidates.end());
+
+                if (seen_options.find(these_options) != seen_options.end())
+                    continue;
+                seen_options.insert(these_options);
+
+                // When an HCLK signal is routed to different (and disconnected) FCLKs, we treat each new
+                // HCLK-FCLK connection as a pseudo-HCLK cell since it must also be assigned an HCLK section
+                auto alias_index = std::pair<IdString, int>(hclk_driver->name, alias_count);
+                alias_cells.push_back(alias_index);
+                alias_count++;
+
+                for (auto option : these_options) {
+                    bel_cell_map[option].insert(alias_index);
+                }
+            }
+        }
+    }
+
+    // First matching. We use the upper CLKDIV2 as the ID for an HCLK
+    std::map<IdStringList, std::set<IdString>> clkdiv_graph;
+    for (auto bel_cell_candidates : bel_cell_map) {
+        auto bel = bel_cell_candidates.first;
+        auto hclk_id_loc = gwu.get_hclk_id(bel);
+        if (constrained_clkdivs.find(hclk_id_loc) != constrained_clkdivs.end()) {
+            continue;
+        }
+        for (auto candidate : bel_cell_candidates.second) {
+            auto ci = ctx->cells.at(candidate.first).get();
+            if ((ci->type != id_CLKDIV) || ci->attrs.count(id_BEL)) {
+                continue;
+            }
+            clkdiv_graph[hclk_id_loc].insert(candidate.first);
+        }
+    }
+
+    if (ctx->debug) {
+        log_info("<-----CUSTOM HCLK PLACER: Constrained CLKDIVs----->\n");
+        for (auto match_pair : constrained_clkdivs) {
+            log_info("%s cell <-----> CLKDIV at HCLK %s\n", match_pair.second.c_str(ctx), match_pair.second.c_str(ctx));
+        }
+        log("\n");
+    }
+
+    auto matching = gwu.find_maximum_bipartite_matching<IdStringList, IdString>(
+            clkdiv_graph); // these will serve as constraints
+    constrained_clkdivs.insert(matching.begin(), matching.end());
+
+    if (ctx->debug) {
+        log_info("<-----CUSTOM HCLK PLACER: First Matching(CLKDIV) Results----->\n");
+        for (auto match_pair : matching) {
+            log_info("%s cell <-----> CLKDIV at HCLK %s\n", match_pair.second.c_str(ctx), match_pair.second.c_str(ctx));
+        }
+        log("\n");
+    }
+
+    // Refine matching to HCLK section, based on what connections actually exist
+    std::map<IdString, std::pair<IdString, int>> true_clkdivs;
+    std::set<BelId> used_bels;
+    for (auto constr_pair : constrained_clkdivs) {
+        BelId option0 = ctx->getBelByName(constr_pair.first);
+        BelId option1 = gwu.get_other_hclk_clkdiv2(option0);
+
+        // On the GW1N-9 devices, only the lower CLKDIV can be fed by a CLKDIV2
+        std::vector<BelId> options = {option1, option0};
+        if (chip.str(ctx) == "GW1N-9C") {
+            auto ci = ctx->cells.at(constr_pair.second).get();
+            for (auto cluster_child_cell : ci->constr_children)
+                if (cluster_child_cell->type == id_CLKDIV2 && options.back() == option0) {
+                    options.pop_back();
+                    break;
+                }
+        }
+
+        bool placed = false;
+        for (auto option : options) {
+            if (placed || (used_bels.find(option) != used_bels.end()))
+                continue;
+            for (auto option_cell : bel_cell_map[option]) {
+                if ((option_cell.first != constr_pair.second) ||
+                    (true_clkdivs.find(option_cell.first) != true_clkdivs.end()))
+                    continue;
+                final_placement[option_cell] = option;
+                true_clkdivs[option_cell.first] = option_cell;
+                used_bels.insert(option);
+                placed = true;
+                break;
+            }
+        }
+        // This must be a constrained CLKDIV that either does not serve IOLOGIC Or
+        // does not have a direct (HCLK-FCLK) connection IOLOGIC it serves
+        // We create a new alias to represent this
+        if (!placed) {
+            auto new_alias = std::pair<IdString, int>(constr_pair.second, -1);
+            for (auto option : options)
+                bel_cell_map[option].insert(new_alias);
+            alias_cells.push_back(new_alias);
+            true_clkdivs[constr_pair.second] = new_alias;
+        }
+    }
+
+    // Second Matching for CLKDIV2 and routing reservation
+    std::map<IdStringList, std::set<std::pair<IdString, int>>> full_hclk_graph;
+    for (auto bel_cell_candidates : bel_cell_map) {
+        auto bel = bel_cell_candidates.first;
+        auto bel_name = ctx->getBelName(bel);
+        if (!used_bels.count(bel)) {
+            for (auto candidate : bel_cell_candidates.second) {
+                if (((candidate.second == -1) || (!true_clkdivs.count(candidate.first)) ||
+                     !(true_clkdivs[candidate.first] == candidate))) {
+                    full_hclk_graph[bel_name].insert(candidate);
+                }
+            }
+        }
+    }
+
+    auto full_matching = gwu.find_maximum_bipartite_matching(full_hclk_graph);
+    for (auto belname_cellalias : full_matching) {
+        auto bel = ctx->getBelByName(belname_cellalias.first);
+        NPNR_ASSERT(!used_bels.count(bel));
+        final_placement[belname_cellalias.second] = bel;
+    }
+
+    if (ctx->debug) {
+        log_info("<-----CUSTOM HCLK PLACER: Second Matching(CLKDIV2 and Routing) Results------>\n");
+        for (auto match_pair : full_matching) {
+            auto alias = match_pair.second;
+            auto bel = match_pair.first;
+            auto cell_type = ctx->cells.at(alias.first).get()->type;
+            log_info("%s cell %s Alias %d <-----> HCLK Section at %s\n", cell_type.c_str(ctx), alias.first.c_str(ctx),
+                     alias.second, bel.str(ctx).c_str());
+        }
+        log("\n");
+    }
+
+    for (auto cell_alias : alias_cells) {
+        auto ci = ctx->cells.at(cell_alias.first).get();
+
+        if (final_placement.find(cell_alias) == final_placement.end() && ctx->debug)
+            if (ci->type == id_CLKDIV2 || ci->type == id_CLKDIV)
+                log_info("Custom HCLK Placer: Unable to place HCLK cell %s; no BELs available to implement cell type "
+                         "%s\n",
+                         ci->name.c_str(ctx), ci->type.c_str(ctx));
+            else
+                log_info("Custom HCLK Placer: Unable to guarantee route for HCLK signal from %s to IOLOGIC\n",
+                         ci->name.c_str(ctx));
+
+        else {
+            auto placement = final_placement[cell_alias];
+            if (ctx->debug)
+                log_info("Custom HCLK Placer: Placing %s Alias %d at %s\n", cell_alias.first.c_str(ctx),
+                         cell_alias.second, ctx->nameOfBel(placement));
+            if (ci->type == id_CLKDIV2)
+                ctx->bindBel(placement, ci, STRENGTH_LOCKED);
+
+            else if ((ci->type == id_CLKDIV) && (true_clkdivs[cell_alias.first] == cell_alias)) {
+                NetInfo *in = ci->getPort(id_HCLKIN);
+                if (in && in->driver.cell->type == id_CLKDIV2) {
+                    ctx->bindBel(placement, in->driver.cell, STRENGTH_LOCKED);
+                }
+                auto clkdiv_bel = gwu.get_clkdiv_for_clkdiv2(placement);
+                ctx->bindBel(clkdiv_bel, ci, STRENGTH_LOCKED);
+            } else {
+                if (ctx->debug)
+                    log_info("Custom HCLK Placer: Reserving HCLK %s to route clock from %s\n",
+                             ctx->nameOfBel(placement), ci->name.c_str(ctx));
+                routing_reserved_hclk_sections.insert(placement);
+            }
+        }
+        if (ci->attrs.count(id_BEL))
+            ci->unsetAttr(id_BEL);
+    }
+}
+
+void GowinImpl::prePlace()
+{
+    place_constrained_hclk_cells();
+    assign_cell_info();
+}
+
 void GowinImpl::postPlace()
 {
     gwu.has_SP32();
@@ -349,6 +600,9 @@ bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
     case ID_MULT36X36:       /* fall-through */
     case ID_ALU54D:
         return dsp_valid(l, bel_type, explain_invalid);
+    case ID_CLKDIV2: /* fall-through */
+    case ID_CLKDIV:
+        return hclk_valid(bel, bel_type);
     }
     return true;
 }
@@ -608,6 +862,52 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
     }
     return true;
 }
+/*
+    Every HCLK section can be used in one of 3 ways:
+        1. As a simple routing path to IOLOGIC FCLK
+        2. As a CLKDIV2
+        3. As a CLKDIV (potentially fed by the CLKDIV2 in its section)
+
+    Here we validate that the placement of cells fits within these 3 use cases, while ensuring that
+    we enforce the constraint that only 1 CLKDIV can be used per HCLK (there is only 1 CLKDIV in each
+    HCLK but we pretend there are two because doing so makes it easier to enforce the real constraint
+    that HCLK signals don't crisscross between HCLK sections even after "transformation" by a CLKDIV
+    or CLKDIV2)
+*/
+bool GowinImpl::hclk_valid(BelId bel, IdString bel_type) const
+{
+    if (bel_type == id_CLKDIV2) {
+        if (routing_reserved_hclk_sections.count(bel))
+            return false;
+        auto clkdiv_cell = ctx->getBoundBelCell(gwu.get_clkdiv_for_clkdiv2(bel));
+        if (clkdiv_cell && ctx->getBoundBelCell(bel)->cluster != clkdiv_cell->name)
+            return false;
+        return true;
+    } else if (bel_type == id_CLKDIV) {
+        BelId clkdiv2_bel = gwu.get_clkdiv2_for_clkdiv(bel);
+        if (routing_reserved_hclk_sections.count(clkdiv2_bel)) {
+            return false;
+        }
+
+        auto other_clkdiv_cell = ctx->getBoundBelCell(gwu.get_other_hclk_clkdiv(bel));
+        if (other_clkdiv_cell)
+            return false;
+
+        auto clkdiv2_bel_cell = ctx->getBoundBelCell(clkdiv2_bel);
+        if (clkdiv2_bel_cell && clkdiv2_bel_cell->cluster != ctx->getBoundBelCell(bel)->name)
+            return false;
+
+        if (clkdiv2_bel_cell && chip.str(ctx) == "GW1N-9C") {
+            // On the GW1N(R)-9C, it appears that only the 'odd' CLKDIV2 is connected to CLKDIV
+            Loc loc = ctx->getBelLocation(bel);
+            if (loc.z == BelZ::CLKDIV_0_Z || loc.z == BelZ::CLKDIV_2_Z)
+                return false;
+        }
+
+        return true;
+    }
+    return false;
+}
 
 // Cluster
 bool GowinImpl::getClusterPlacement(ClusterId cluster, BelId root_bel,
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index a9f247d891..c14949d665 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -62,6 +62,17 @@ inline bool type_is_dsp(IdString cell_type)
 }
 inline bool is_dsp(const CellInfo *cell) { return type_is_dsp(cell->type); }
 
+// Return true if a cell is CLKDIV
+inline bool type_is_clkdiv(IdString cell_type) { return cell_type == id_CLKDIV; }
+inline bool is_clkdiv(const CellInfo *cell) { return type_is_clkdiv(cell->type); }
+
+// Return true if a cell is CLKDIV2
+inline bool type_is_clkdiv2(IdString cell_type) { return cell_type == id_CLKDIV2; }
+inline bool is_clkdiv2(const CellInfo *cell) { return type_is_clkdiv2(cell->type); }
+
+// Return true for HCLK Cells
+inline bool is_hclk(const CellInfo *cell) { return type_is_clkdiv2(cell->type) || type_is_clkdiv(cell->type); }
+
 // ==========================================
 // extra data in the chip db
 // ==========================================
@@ -191,7 +202,18 @@ enum
     ALU54D_1_Z = 556 + 3,
     MULTALU18X18_1_Z = 560,
     MULTALU36X18_1_Z = 560 + 1,
-    MULTADDALU18X18_1_Z = 560 + 2
+    MULTADDALU18X18_1_Z = 560 + 2,
+
+    // HCLK Bels
+    CLKDIV2_0_Z = 610,
+    CLKDIV2_1_Z = 611,
+    CLKDIV2_2_Z = 612,
+    CLKDIV2_3_Z = 613,
+
+    CLKDIV_0_Z = 620,
+    CLKDIV_1_Z = 621,
+    CLKDIV_2_Z = 622,
+    CLKDIV_3_Z = 623
 };
 }
 
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 75fda033ef..54d2e979e5 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -96,6 +96,17 @@
 MULTALU36X18_1_Z = 560 + 1
 MULTADDALU18X18_1_Z = 560 + 2
 
+CLKDIV2_0_Z = 610
+CLKDIV2_1_Z = 611
+CLKDIV2_2_Z = 612
+CLKDIV2_3_Z = 613
+
+
+CLKDIV_0_Z = 620
+CLKDIV_1_Z = 621
+CLKDIV_2_Z = 622
+CLKDIV_3_Z = 623
+
 # =======================================
 # Chipdb additional info
 # =======================================
@@ -357,6 +368,47 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
             if not tt.has_wire(src):
                 tt.create_wire(src, "HCLK")
             tt.create_pip(src, dst)
+    
+    hclk_bel_zs = {
+        "CLKDIV2_HCLK0_SECT0": CLKDIV2_0_Z,
+        "CLKDIV2_HCLK0_SECT1": CLKDIV2_1_Z,
+        "CLKDIV2_HCLK1_SECT0": CLKDIV2_2_Z,
+        "CLKDIV2_HCLK1_SECT1": CLKDIV2_3_Z,
+        "CLKDIV_HCLK0_SECT0": CLKDIV_0_Z,
+        "CLKDIV_HCLK0_SECT1": CLKDIV_1_Z,
+        "CLKDIV_HCLK1_SECT0": CLKDIV_2_Z,
+        "CLKDIV_HCLK1_SECT1": CLKDIV_3_Z
+    }
+   
+    for bel_name, bel_props in db.grid[y][x].bels.items():
+        if (bel_name not in hclk_bel_zs):
+            continue
+        this_portmap = bel_props.portmap
+
+        if bel_name.startswith("CLKDIV2_"):
+            bel_type = "CLKDIV2"
+        elif bel_name.startswith("CLKDIV_"):
+            bel_type = "CLKDIV"
+        this_bel = tt.create_bel(bel_name, bel_type, hclk_bel_zs[bel_name])
+
+        if (bel_name in ["CLKDIV_HCLK0_SECT1", "CLKDIV_HCLK1_SECT1"]): 
+            this_bel.flags |= BEL_FLAG_HIDDEN
+        if bel_type=="CLKDIV":
+            this_bel.flags |= BEL_FLAG_GLOBAL
+
+        known_pins = ["HCLKIN", "RESETN", "CLKOUT"]
+        if bel_type == "CLKDIV":
+            known_pins.append("CALIB")
+
+        for pin in this_portmap.keys():
+            assert pin in known_pins, f"Unknown pin {pin} for bel {this_bel}"
+            if pin in ["CALIB", "RESETN", "HCLKIN"]:
+                pin_direction = PinType.INPUT
+            elif pin in ["CLKOUT"]:
+                pin_direction = PinType.OUTPUT
+            wire_type = "HCLK_CTRL" if pin in ("CALIB", "RESETN") else "HCLK"
+            add_port_wire(tt, this_bel, this_portmap, pin, wire_type, pin_direction)
+
 
 # map spine -> dqce bel
 dqce_bels = {}
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 5bf398d9e3..0d6fb8b832 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -6,6 +6,7 @@
 #include "himbaechel_constids.h"
 #include "himbaechel_helpers.h"
 
+#include <queue>
 #include "gowin.h"
 #include "gowin_utils.h"
 
@@ -290,4 +291,145 @@ CellInfo *GowinUtils::dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, in
     return connected_to_cell;
 }
 
+// Use the upper CLKDIV as the id for a hclk section
+IdStringList GowinUtils::get_hclk_id(BelId hclk_bel) const
+{
+    IdString bel_type = ctx->getBelType(hclk_bel);
+    NPNR_ASSERT(hclk_bel != BelId() && bel_type.in(id_CLKDIV2, id_CLKDIV));
+    Loc id_loc = Loc(ctx->getBelLocation(hclk_bel));
+    if (bel_type == id_CLKDIV) {
+        return get_hclk_id(get_clkdiv2_for_clkdiv(hclk_bel));
+    } else if (id_loc.z == BelZ::CLKDIV2_0_Z || id_loc.z == BelZ::CLKDIV2_2_Z)
+        return ctx->getBelName(hclk_bel);
+    else
+        return ctx->getBelName(ctx->getBelByLocation(Loc(id_loc.x, id_loc.y, id_loc.z - 1)));
+    return IdStringList();
+}
+
+// Get the clkdiv in the same section as a clkdiv2
+BelId GowinUtils::get_clkdiv_for_clkdiv2(BelId clkdiv2_bel) const
+{
+    NPNR_ASSERT(clkdiv2_bel != BelId() && (ctx->getBelType(clkdiv2_bel) == id_CLKDIV2));
+    Loc clkdiv_loc = ctx->getBelLocation(clkdiv2_bel);
+    clkdiv_loc.z = BelZ::CLKDIV_0_Z + (clkdiv_loc.z - BelZ::CLKDIV2_0_Z);
+    return ctx->getBelByLocation(clkdiv_loc);
+}
+
+// Get the clkdiv2 in the same section as a clkdiv
+BelId GowinUtils::get_clkdiv2_for_clkdiv(BelId clkdiv_bel) const
+{
+    NPNR_ASSERT(clkdiv_bel != BelId() && (ctx->getBelType(clkdiv_bel) == id_CLKDIV));
+    Loc clkdiv_loc = ctx->getBelLocation(clkdiv_bel);
+    Loc clkdiv2_loc = Loc(clkdiv_loc.x, clkdiv_loc.y, BelZ::CLKDIV2_0_Z + (clkdiv_loc.z - BelZ::CLKDIV_0_Z));
+    return ctx->getBelByLocation(clkdiv2_loc);
+}
+
+// Get the clkdiv in the neighbouring section to a clkdiv
+BelId GowinUtils::get_other_hclk_clkdiv(BelId clkdiv_bel) const
+{
+    NPNR_ASSERT(clkdiv_bel != BelId() && (ctx->getBelType(clkdiv_bel) == id_CLKDIV));
+    Loc other_loc = Loc(ctx->getBelLocation(clkdiv_bel));
+    int dz = BelZ::CLKDIV_1_Z - BelZ::CLKDIV_0_Z;
+    if (other_loc.z == BelZ::CLKDIV_1_Z || other_loc.z == BelZ::CLKDIV_3_Z)
+        dz = -dz;
+    other_loc.z += dz;
+    return ctx->getBelByLocation(other_loc);
+}
+
+// Get the clkdiv2 in the neighbouring section to a clkdiv2
+BelId GowinUtils::get_other_hclk_clkdiv2(BelId clkdiv2_bel) const
+{
+    NPNR_ASSERT(clkdiv2_bel != BelId() && (ctx->getBelType(clkdiv2_bel) == id_CLKDIV2));
+    Loc other_loc = Loc(ctx->getBelLocation(clkdiv2_bel));
+    int dz = BelZ::CLKDIV2_1_Z - BelZ::CLKDIV2_0_Z;
+    if (other_loc.z == BelZ::CLKDIV2_1_Z || other_loc.z == BelZ::CLKDIV2_3_Z)
+        dz = -dz;
+    other_loc.z += dz;
+    return ctx->getBelByLocation(other_loc);
+}
+
+// Credit: https://cp-algorithms.com/graph/kuhn_maximum_bipartite_matching.html
+std::vector<int> GowinUtils::kuhn_find_maximum_bipartite_matching(int n, int k, std::vector<std::vector<int>> &g)
+{
+    std::vector<int> mt;
+    std::vector<bool> used(n);
+
+    auto try_kuhn = [&](int v, auto &try_kuhn_ref) -> bool {
+        if (used[v])
+            return false;
+        used[v] = true;
+        for (int to : g[v]) {
+            if (mt[to] == -1 || try_kuhn_ref(mt[to], try_kuhn_ref)) {
+                mt[to] = v;
+                return true;
+            }
+        }
+        return false;
+    };
+
+    mt.assign(k, -1);
+    for (int v = 0; v < n; ++v) {
+        used.assign(n, false);
+        try_kuhn(v, try_kuhn);
+    }
+
+    return mt;
+}
+
+// original implementation: nextpnr/machxo2/pack.cc
+// Using a BFS, search for bels of a given type either upstream or downstream of another cell
+void GowinUtils::find_connected_bels(const CellInfo *cell, IdString port, IdString dest_type, IdString dest_pin,
+                                     int iter_limit, std::vector<BelId> &candidates)
+{
+    int iter = 0;
+    std::queue<WireId> visit;
+    pool<WireId> seen_wires;
+    pool<BelId> seen_bels;
+
+    BelId bel = cell->bel;
+    if (bel == BelId())
+        return;
+    WireId start_wire = ctx->getBelPinWire(bel, port);
+    NPNR_ASSERT(start_wire != WireId());
+    PortType dir = ctx->getBelPinType(bel, port);
+
+    visit.push(start_wire);
+
+    while (!visit.empty() && (iter++ < iter_limit)) {
+        WireId cursor = visit.front();
+        visit.pop();
+        // Check to see if we have reached a valid bel pin
+        for (auto bp : ctx->getWireBelPins(cursor)) {
+            if (ctx->getBelType(bp.bel) != dest_type)
+                continue;
+            if (dest_pin != IdString() && bp.pin != dest_pin)
+                continue;
+            if (seen_bels.count(bp.bel))
+                continue;
+            seen_bels.insert(bp.bel);
+            candidates.push_back(bp.bel);
+        }
+        // Search in the appropriate direction up/downstream of the cursor
+        if (dir == PORT_OUT) {
+            for (PipId p : ctx->getPipsDownhill(cursor))
+                if (ctx->checkPipAvail(p)) {
+                    WireId dst = ctx->getPipDstWire(p);
+                    if (seen_wires.count(dst))
+                        continue;
+                    seen_wires.insert(dst);
+                    visit.push(dst);
+                }
+        } else {
+            for (PipId p : ctx->getPipsUphill(cursor))
+                if (ctx->checkPipAvail(p)) {
+                    WireId src = ctx->getPipSrcWire(p);
+                    if (seen_wires.count(src))
+                        continue;
+                    seen_wires.insert(src);
+                    visit.push(src);
+                }
+        }
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index c280b271f7..77b750820c 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -94,6 +94,59 @@ struct GowinUtils
 
     // make cell but do not include it in the list of chip cells.
     std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
+
+    // HCLK
+    BelId get_clkdiv_for_clkdiv2(BelId clkdiv2_bel) const;
+    BelId get_other_hclk_clkdiv2(BelId clkdiv2_bel) const;
+    BelId get_other_hclk_clkdiv(BelId clkdiv_bel) const;
+    BelId get_clkdiv2_for_clkdiv(BelId clkdiv_bel) const;
+    IdStringList get_hclk_id(BelId hclk_bel) const; // use the upper CLKDIV2 (CLKDIV2_0 orCLKDIV2_2) as an id
+
+    // Find Bels connected to a bound cell
+    void find_connected_bels(const CellInfo *cell, IdString port, IdString dest_type, IdString dest_pin, int iter_limit,
+                             std::vector<BelId> &candidates);
+
+    // Find a maximum bipartite matching
+    template <typename T1, typename T2> std::map<T1, T2> find_maximum_bipartite_matching(std::map<T1, std::set<T2>> &G)
+    {
+        std::map<int, T1> U;
+        std::map<int, T2> V;
+        std::map<T2, int> V_IDX;
+        std::vector<std::vector<int>> int_graph(G.size());
+
+        int u_idx = 0;
+        int v_idx = 0;
+
+        // Translate the input graph to an integer graph
+        for (auto row : G) {
+            U.insert(std::pair(u_idx, row.first));
+            for (auto v : row.second) {
+                if (V_IDX.find(v) == V_IDX.end()) {
+                    V_IDX[v] = v_idx;
+                    V[v_idx] = v;
+                    v_idx++;
+                }
+                int_graph[u_idx].push_back(V_IDX[v]);
+            }
+            u_idx++;
+        }
+
+        std::vector<int> int_matching = kuhn_find_maximum_bipartite_matching(u_idx, v_idx, int_graph);
+        std::map<T1, T2> ret_matching;
+
+        int m_idx = 0;
+        for (auto val : int_matching) {
+            if (val >= 0) { // elements that are not matched have a value of -1
+                ret_matching[U[val]] = V[m_idx];
+            }
+            m_idx++;
+        }
+
+        return ret_matching;
+    }
+
+    // Find a maximum matching in a bipartite graph, g
+    std::vector<int> kuhn_find_maximum_bipartite_matching(int n, int k, std::vector<std::vector<int>> &g);
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index c34a88cf95..ec1ef8f15e 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1,7 +1,6 @@
 #include "design_utils.h"
 #include "log.h"
 #include "nextpnr.h"
-#include "util.h"
 
 #define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
 #include "himbaechel_constids.h"
@@ -1325,7 +1324,7 @@ struct GowinPacker
     {
         int num = (bit_width == 9 || bit_width == 18 || bit_width == 36) ? 36 : 32;
         for (int i = 0, j = offset; i < num; ++i, ++j) {
-            if (((j + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) {
+            if (((i + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) {
                 ++j;
             }
             ci->renamePort(ctx->idf(from, i), ctx->idf(to, offset ? j % 36 : j));
@@ -1391,15 +1390,6 @@ struct GowinPacker
             }
             ++idx;
         }
-        switch (idx) {
-        case 1:
-            init |= init << 2; /* fallthrough */
-        case 2:
-            init |= init << 4;
-            break;
-        default:
-            break;
-        }
         lut->setParam(id_INIT, init);
 
         new_cells.push_back(std::move(lut_cell));
@@ -1416,7 +1406,7 @@ struct GowinPacker
         if (bit_width == 32 || bit_width == 36) {
             return;
         }
-        int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
+        int read_mode = ci->params.at(id_READ_MODE).as_int64();
         if (read_mode == 0) {
             return;
         }
@@ -1521,7 +1511,7 @@ struct GowinPacker
         CellInfo *new_ce_net_src = ce_pre_dff;
 
         // add delay register in pipeline mode
-        int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
+        int read_mode = ci->params.at(id_READ_MODE).as_int64();
         if (read_mode) {
             auto ce_pipe_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
             new_cells.push_back(std::move(ce_pipe_dff_cell));
@@ -1597,7 +1587,10 @@ struct GowinPacker
             ci->connectPort(port, vcc_net);
         }
 
+        ci->addInput(id_WRE);
+        ci->connectPort(id_WRE, vss_net);
         ci->addInput(id_WREB);
+        ci->connectPort(id_WREB, vss_net);
 
         if (!ci->params.count(id_BIT_WIDTH)) {
             ci->setParam(id_BIT_WIDTH, Property(default_bw, 32));
@@ -1609,19 +1602,10 @@ struct GowinPacker
             ci->copyPortTo(id_CE, ci, id_CEB);
             ci->copyPortTo(id_OCE, ci, id_OCEB);
             ci->copyPortTo(id_RESET, ci, id_RESETB);
-            ci->connectPort(id_WREB, vcc_net);
 
-            // disconnect lower address bits for ROM
-            std::array rom_ignore_bits = {2, 4, 8, 16, 32};
-            std::array romx9_ignore_bits = {9, 9, 9, 18, 36};
-            for (unsigned int i = 0; i < 14; ++i) {
-                if (i < size(rom_ignore_bits) && ((ci->type == id_pROM && bit_width >= rom_ignore_bits[i]) ||
-                                                  (ci->type == id_pROMX9 && bit_width >= romx9_ignore_bits[i]))) {
-                    ci->disconnectPort(ctx->idf("AD[%d]", i));
-                } else {
-                    ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
-                    ci->copyPortTo(ctx->idf("ADA%d", i), ci, ctx->idf("ADB%d", i));
-                }
+            for (int i = 0; i < 14; ++i) {
+                ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADA%d", i));
+                ci->copyPortTo(ctx->idf("ADA%d", i), ci, ctx->idf("ADB%d", i));
             }
             bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d");
         } else {
@@ -1630,18 +1614,9 @@ struct GowinPacker
             ci->renamePort(id_OCE, id_OCEB);
             ci->renamePort(id_CE, id_CEB);
             ci->renamePort(id_RESET, id_RESETB);
-            ci->connectPort(id_WREB, vss_net);
-
-            ci->addInput(id_CE);
-            ci->connectPort(id_CE, vcc_net);
-            ci->disconnectPort(id_OCEB);
 
-            int read_mode = int_or_default(ci->params, id_READ_MODE, 0);
-            if (read_mode) {
-                ci->connectPort(id_OCEB, vcc_net);
-            } else {
-                ci->copyPortTo(id_CEB, ci, id_OCEB);
-            }
+            ci->addInput(id_CEA);
+            ci->connectPort(id_CEA, vss_net);
             for (int i = 0; i < 14; ++i) {
                 ci->renamePort(ctx->idf("AD[%d]", i), ctx->idf("ADB%d", i));
             }
@@ -1823,21 +1798,6 @@ struct GowinPacker
             bsram_fix_blksel(ci, new_cells);
         }
 
-        // The statement in the Gowin documentation that in the reading mode
-        // "READ_MODE=0" the output register is not used and the OCE signal is
-        // ignored is not confirmed by practice - if the OCE was left
-        // unconnected or connected to the constant network, then a change in
-        // output data was observed even with CE=0, as well as the absence of
-        // such at CE=1.
-        // Synchronizing CE and OCE helps but it's definitely a hack.
-        NetInfo *oce_net = ci->getPort(id_OCE);
-        if (oce_net == nullptr || oce_net->name == ctx->id("$PACKER_VCC") || oce_net->name == ctx->id("$PACKER_GND")) {
-            if (oce_net != nullptr) {
-                ci->disconnectPort(id_OCE);
-            }
-            ci->copyPortTo(id_CE, ci, id_OCE);
-        }
-
         // XXX UG285-1.3.6_E Gowin BSRAM & SSRAM User Guide:
         // For GW1N-9/GW1NR-9/GW1NS-4 series, 32/36-bit SP/SPX9 is divided into two
         // SP/SPX9s, which occupy two BSRAMs.
@@ -2981,6 +2941,39 @@ struct GowinPacker
         }
     }
 
+    // ===================================
+    // HCLK -- CLKDIV and CLKDIV2 for now
+    // ===================================
+    void pack_hclk(void)
+    {
+        log_info("Pack HCLK cells...\n");
+
+        for (auto &cell : ctx->cells) {
+            auto ci = cell.second.get();
+            if (ci->type != id_CLKDIV)
+                continue;
+            NetInfo *hclk_in = ci->getPort(id_HCLKIN);
+            if (hclk_in) {
+                CellInfo *this_driver = hclk_in->driver.cell;
+                if (this_driver && this_driver->type == id_CLKDIV2) {
+                    NetInfo *out = this_driver->getPort(id_CLKOUT);
+                    if (out->users.entries() > 1) {
+                        // We could do as the IDE does sometimes and replicate the CLKDIV2 cell
+                        // as many times as we need. For now, we keep things simple
+                        log_error("CLKDIV2 that drives CLKDIV should drive no other cells\n");
+                    }
+                    ci->cluster = ci->name;
+                    this_driver->cluster = ci->name;
+                    ci->constr_children.push_back(this_driver);
+                    this_driver->constr_x = 0;
+                    this_driver->constr_y = 0;
+                    this_driver->constr_z = BelZ::CLKDIV2_0_Z - BelZ::CLKDIV_0_Z;
+                    this_driver->constr_abs_z = false;
+                }
+            }
+        }
+    }
+
     // =========================================
     // Create entry points to the clock system
     // =========================================
@@ -3097,6 +3090,9 @@ struct GowinPacker
         pack_gsr();
         ctx->check();
 
+        pack_hclk();
+        ctx->check();
+
         pack_bandgap();
         ctx->check();
 

From f199c3e576a3a796697e9e87f44242ae1489d2da Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Mon, 12 Aug 2024 16:29:26 +0200
Subject: [PATCH 627/712] Update shell.nix (#1347)

---
 shell.nix | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/shell.nix b/shell.nix
index 084e318092..7527783739 100644
--- a/shell.nix
+++ b/shell.nix
@@ -1,25 +1,8 @@
-{ pkgs ? import (fetchTarball https://github.com/NixOS/nixpkgs/archive/23.05.tar.gz) {} }:
+{ pkgs ? import (fetchTarball https://github.com/NixOS/nixpkgs/archive/24.05.tar.gz) {} }:
 
 let
   pythonPkgs = pkgs.python3Packages;
   boostPython = pkgs.boost.override { python = pythonPkgs.python; enablePython = true; };
-  vscode = pkgs.vscode-with-extensions.override {
-    vscodeExtensions = with pkgs.vscode-extensions; [
-      bbenoist.nix
-      ms-vscode.cpptools
-      ms-vscode.cmake-tools
-      twxs.cmake
-      usernamehw.errorlens
-      llvm-vs-code-extensions.vscode-clangd
-    ] ++ pkgs.vscode-utils.extensionsFromVscodeMarketplace [
-      {
-        name = "VerilogHDL";
-        publisher = "mshr-h";
-        version = "1.11.4";
-        sha256 = "sha256-4JY0eaN2IkwHv8u8X6ejDXk6vT1qB4vJjWdIy8b/jj4=";
-      }
-    ];
-  };
 in pkgs.mkShell {
   buildInputs = with pkgs; [
     cmake
@@ -37,7 +20,6 @@ in pkgs.mkShell {
     valgrind
     cling
     gdb
-    vscode
   ];
 
   shellHook = ''

From 0d5d32951c2f2100e436a4fbaf82d23e645ae4ff Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Mon, 12 Aug 2024 17:45:27 +0200
Subject: [PATCH 628/712] SDC parsing support (#1348)

* kernel: Add SDC file parser

* kernel: Add sdc as valid option

* kernel/sdc: Add error on EOF when fetching strings

* kernel/sdc: WIP command parsing for set_false_path

* kernel/sdc: Fully parse set_false_path

* kernel/sdc: Handle review comments
---
 common/kernel/command.cc |  15 ++
 common/kernel/context.h  |   4 +
 common/kernel/sdc.cc     | 446 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 465 insertions(+)
 create mode 100644 common/kernel/sdc.cc

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 9b8f8616b7..01c556b0e6 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -375,6 +375,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
     general.add_options()("timing-allow-fail", "allow timing to fail in design");
     general.add_options()("no-tmdriv", "disable timing-driven placement");
+    general.add_options()("sdc", po::value<std::string>(), "Generic timing constraints SDC file to load");
     general.add_options()("sdf", po::value<std::string>(), "SDF delay back-annotation file to write");
     general.add_options()("sdf-cvc", "enable tweaks for SDF file compatibility with the CVC simulator");
     general.add_options()("no-print-critical-path-source",
@@ -605,6 +606,13 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
                 std::ifstream f(filename);
                 if (!parse_json(f, filename, w.getContext()))
                     log_error("Loading design failed.\n");
+
+                if (vm.count("sdc")) {
+                    std::string sdc_filename = vm["sdc"].as<std::string>();
+                    std::ifstream sdc_stream(sdc_filename);
+                    ctx->read_sdc(sdc_stream);
+                }
+
                 customAfterLoad(w.getContext());
                 w.notifyChangeContext();
                 w.updateActions();
@@ -613,6 +621,7 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
         } catch (log_execution_error_exception) {
             // show error is handled by gui itself
         }
+
         w.show();
 
         return a.exec();
@@ -624,6 +633,12 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
         if (!parse_json(f, filename, ctx.get()))
             log_error("Loading design failed.\n");
 
+        if (vm.count("sdc")) {
+            std::string sdc_filename = vm["sdc"].as<std::string>();
+            std::ifstream sdc_stream(sdc_filename);
+            ctx->read_sdc(sdc_stream);
+        }
+
         customAfterLoad(ctx.get());
     }
 
diff --git a/common/kernel/context.h b/common/kernel/context.h
index 5543a2cf27..bd50e81791 100644
--- a/common/kernel/context.h
+++ b/common/kernel/context.h
@@ -105,6 +105,10 @@ struct Context : Arch, DeterministicRNG
     // provided by timing_log.cc
     void log_timing_results(TimingResult &result, bool print_histogram, bool print_fmax, bool print_path,
                             bool warn_on_failure);
+
+    // provided by sdc.cc
+    void read_sdc(std::istream &in);
+
     // --------------------------------------------------------------
 
     uint32_t checksum() const;
diff --git a/common/kernel/sdc.cc b/common/kernel/sdc.cc
new file mode 100644
index 0000000000..0fbfe69009
--- /dev/null
+++ b/common/kernel/sdc.cc
@@ -0,0 +1,446 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020  gatecat <gatecat@ds0.me>
+ *  Copyright (C) 2024  rowanG077 <goemansrowan@gmail.com>
+ *
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+
+#include <algorithm>
+#include <iterator>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct SdcEntity
+{
+    enum EntityType
+    {
+        ENTITY_CELL,
+        ENTITY_PORT,
+        ENTITY_NET,
+        ENTITY_PIN,
+    } type;
+    IdString name;
+    IdString pin; // for cell pins only
+
+    SdcEntity(EntityType type, IdString name) : type(type), name(name) {}
+    SdcEntity(EntityType type, IdString name, IdString pin) : type(type), name(name), pin(pin) {}
+
+    const std::string &to_string(Context *ctx) { return name.str(ctx); }
+
+    CellInfo *get_cell(Context *ctx) const
+    {
+        if (type != ENTITY_CELL)
+            return nullptr;
+        return ctx->cells.at(name).get();
+    }
+
+    PortInfo *get_port(Context *ctx) const
+    {
+        if (type != ENTITY_PORT)
+            return nullptr;
+        return &ctx->ports.at(name);
+    }
+
+    NetInfo *get_net(Context *ctx) const
+    {
+        if (type == ENTITY_PIN) {
+            CellInfo *cell = nullptr;
+            if (ctx->cells.count(name)) {
+                cell = ctx->cells.at(name).get();
+            } else {
+                return nullptr;
+            }
+            if (!cell->ports.count(pin))
+                return nullptr;
+            return cell->ports.at(pin).net;
+        } else if (type == ENTITY_NET) {
+            return ctx->nets.at(name).get();
+        } else {
+            return nullptr;
+        }
+    }
+};
+
+struct SdcValue
+{
+    SdcValue(const std::string &s) : is_string(true), str(s) {};
+    SdcValue(const std::vector<SdcEntity> &l) : is_string(false), list(l) {};
+
+    bool is_string;
+    std::string str;             // simple string value
+    std::vector<SdcEntity> list; // list of entities
+};
+
+struct SDCParser
+{
+    std::string buf;
+    int pos = 0;
+    int lineno = 1;
+    Context *ctx;
+
+    SDCParser(const std::string &buf, Context *ctx) : buf(buf), ctx(ctx) {};
+
+    inline bool eof() const { return pos == int(buf.size()); }
+
+    inline char peek() const { return buf.at(pos); }
+
+    inline char get()
+    {
+        char c = buf.at(pos++);
+        if (c == '\n')
+            ++lineno;
+        return c;
+    }
+
+    std::string get(int n)
+    {
+        std::string s = buf.substr(pos, n);
+        pos += n;
+        return s;
+    }
+
+    // If next char matches c, take it from the stream and return true
+    bool check_get(char c)
+    {
+        if (peek() == c) {
+            get();
+            return true;
+        } else {
+            return false;
+        }
+    }
+
+    // If next char matches any in chars, take it from the stream and return true
+    bool check_get_any(const std::string &chrs)
+    {
+        char c = peek();
+        if (chrs.find(c) != std::string::npos) {
+            get();
+            return true;
+        } else {
+            return false;
+        }
+    }
+
+    inline void skip_blank(bool nl = false)
+    {
+        while (!eof() && check_get_any(nl ? " \t\n\r" : " \t"))
+            ;
+    }
+
+    // Return true if end of line (or file)
+    inline bool skip_check_eol()
+    {
+        skip_blank(false);
+        if (eof())
+            return true;
+        char c = peek();
+        // Comments count as end of line
+        if (c == '#') {
+            get();
+            while (!eof() && peek() != '\n' && peek() != '\r')
+                get();
+            return true;
+        }
+        if (c == ';') {
+            // Forced end of line
+            get();
+            return true;
+        }
+        return (c == '\n' || c == '\r');
+    }
+
+    inline std::string get_str()
+    {
+        std::string s;
+        skip_blank(false);
+        if (eof())
+            return "";
+
+        bool in_quotes = false, in_braces = false, escaped = false;
+
+        char c = get();
+
+        if (c == '"')
+            in_quotes = true;
+        else if (c == '{')
+            in_braces = true;
+        else
+            s += c;
+
+        while (true) {
+            if (eof())
+                log_error("EOF while parsing string '%s'\n", s.c_str());
+
+            char c = peek();
+            if (!in_quotes && !in_braces && !escaped && (std::isblank(c) || c == ']')) {
+                break;
+            }
+            get();
+            if (escaped) {
+                s += c;
+                escaped = false;
+            } else if ((in_quotes && c == '"') || (in_braces && c == '}')) {
+                break;
+            } else if (c == '\\') {
+                escaped = true;
+            } else {
+                s += c;
+            }
+        }
+
+        return s;
+    }
+
+    SdcValue evaluate(const std::vector<SdcValue> &arguments)
+    {
+        NPNR_ASSERT(!arguments.empty());
+        auto &arg0 = arguments.at(0);
+        NPNR_ASSERT(arg0.is_string);
+        const std::string &cmd = arg0.str;
+        if (cmd == "get_ports")
+            return cmd_get_ports(arguments);
+        else if (cmd == "get_cells")
+            return cmd_get_cells(arguments);
+        else if (cmd == "get_nets")
+            return cmd_get_nets(arguments);
+        else if (cmd == "get_pins")
+            return cmd_get_pins(arguments);
+        else if (cmd == "create_clock")
+            return cmd_create_clock(arguments);
+        else if (cmd == "set_false_path")
+            return cmd_set_false_path(arguments);
+        else
+            log_error("Unsupported SDC command '%s'\n", cmd.c_str());
+    }
+
+    std::vector<SdcValue> get_arguments()
+    {
+        std::vector<SdcValue> args;
+        while (!skip_check_eol()) {
+            if (check_get('[')) {
+                // Start of a sub-expression
+                auto result = evaluate(get_arguments());
+                NPNR_ASSERT(check_get(']'));
+                args.push_back(result);
+            } else if (peek() == ']') {
+                break;
+            } else {
+                args.push_back(get_str());
+            }
+        }
+        skip_blank(true);
+        return args;
+    }
+
+    SdcValue cmd_get_nets(const std::vector<SdcValue> &arguments)
+    {
+        std::vector<SdcEntity> nets;
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (!arg.is_string)
+                log_error("get_nets expected string arguments (line %d)\n", lineno);
+            std::string s = arg.str;
+            if (s.at(0) == '-')
+                log_error("unsupported argument '%s' to get_nets (line %d)\n", s.c_str(), lineno);
+            IdString id = ctx->id(s);
+            if (ctx->nets.count(id) || ctx->net_aliases.count(id))
+                nets.emplace_back(SdcEntity::ENTITY_NET, ctx->net_aliases.count(id) ? ctx->net_aliases.at(id) : id);
+            else
+                log_warning("get_nets argument '%s' matched no objects.\n", s.c_str());
+        }
+        return nets;
+    }
+
+    SdcValue cmd_get_ports(const std::vector<SdcValue> &arguments)
+    {
+        std::vector<SdcEntity> ports;
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (!arg.is_string)
+                log_error("get_ports expected string arguments (line %d)\n", lineno);
+            std::string s = arg.str;
+            if (s.at(0) == '-')
+                log_error("unsupported argument '%s' to get_ports (line %d)\n", s.c_str(), lineno);
+            IdString id = ctx->id(s);
+            if (ctx->ports.count(id))
+                ports.emplace_back(SdcEntity::ENTITY_PORT, id);
+        }
+        return ports;
+    }
+
+    SdcValue cmd_get_cells(const std::vector<SdcValue> &arguments)
+    {
+        std::vector<SdcEntity> cells;
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (!arg.is_string)
+                log_error("get_cells expected string arguments (line %d)\n", lineno);
+            std::string s = arg.str;
+            if (s.at(0) == '-')
+                log_error("unsupported argument '%s' to get_cells (line %d)\n", s.c_str(), lineno);
+            IdString id = ctx->id(s);
+            if (ctx->cells.count(id))
+                cells.emplace_back(SdcEntity::ENTITY_CELL, id);
+        }
+        return cells;
+    }
+
+    SdcValue cmd_get_pins(const std::vector<SdcValue> &arguments)
+    {
+        std::vector<SdcEntity> pins;
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (!arg.is_string)
+                log_error("get_pins expected string arguments (line %d)\n", lineno);
+            std::string s = arg.str;
+            if (s.at(0) == '-')
+                log_error("unsupported argument '%s' to get_pins (line %d)\n", s.c_str(), lineno);
+            auto pos = s.rfind('/');
+            if (pos == std::string::npos)
+                log_error("expected / in cell pin name '%s' (line %d)\n", s.c_str(), lineno);
+            pins.emplace_back(SdcEntity::ENTITY_PIN, ctx->id(s.substr(0, pos)), ctx->id(s.substr(pos + 1)));
+            if (pins.back().get_net(ctx) == nullptr) {
+                log_warning("cell pin '%s' not found\n", s.c_str());
+                pins.pop_back();
+            }
+        }
+        return pins;
+    }
+
+    SdcValue cmd_create_clock(const std::vector<SdcValue> &arguments)
+    {
+        float period = 10;
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (arg.is_string) {
+                std::string s = arg.str;
+                if (s == "-period") {
+                    i++;
+                    auto &val = arguments.at(i);
+                    if (!val.is_string)
+                        log_error("expecting string argument to -period (line %d)\n", lineno);
+                    try {
+                        period = std::stof(val.str);
+                    } catch (std::exception &e) {
+                        log_error("invalid argument '%s' to -period (line %d)\n", val.str.c_str(), lineno);
+                    }
+                } else if (s == "-name") {
+                    i++;
+                } else {
+                    log_error("unsupported argument '%s' to create_clock\n", s.c_str());
+                }
+            } else {
+                for (const auto &ety : arg.list) {
+                    NetInfo *net = nullptr;
+                    if (ety.type == SdcEntity::ENTITY_PIN)
+                        net = ety.get_net(ctx);
+                    else if (ety.type == SdcEntity::ENTITY_NET)
+                        net = ctx->nets.at(ety.name).get();
+                    else if (ety.type == SdcEntity::ENTITY_PORT)
+                        net = ctx->ports.at(ety.name).net;
+                    else
+                        log_error("create_clock applies only to cells, cell pins, or IO ports (line %d)\n", lineno);
+
+                    ctx->addClock(net->name, 1000.0f / period);
+                }
+            }
+        }
+        return std::string{};
+    }
+
+    SdcValue cmd_set_false_path(const std::vector<SdcValue> &arguments)
+    {
+        NetInfo *from = nullptr;
+        NetInfo *to = nullptr;
+
+        for (int i = 1; i < int(arguments.size()); i++) {
+            auto &arg = arguments.at(i);
+            if (arg.is_string) {
+                std::string s = arg.str;
+
+                bool is_from = true;
+                if (s == "-to") {
+                    is_from = false;
+                } else if (s != "-from") {
+                    log_error("expecting either -to or -from to set_false_path(line %d)\n", lineno);
+                }
+
+                i++;
+                auto &val = arguments.at(i);
+                if (val.is_string) {
+                    log_error("expecting SdcValue argument to -from (line %d)\n", lineno);
+                }
+
+                if (val.list.size() != 1) {
+                    log_error("Expected a single SdcEntity as argument to -to/-from (line %d)\n", lineno);
+                }
+
+                auto &ety = val.list.at(0);
+
+                NetInfo *net = nullptr;
+                if (ety.type == SdcEntity::ENTITY_PIN)
+                    net = ety.get_net(ctx);
+                else if (ety.type == SdcEntity::ENTITY_NET)
+                    net = ctx->nets.at(ety.name).get();
+                else if (ety.type == SdcEntity::ENTITY_PORT)
+                    net = ctx->ports.at(ety.name).net;
+                else
+                    log_error("set_false_path applies only to nets, cell pins, or IO ports (line %d)\n", lineno);
+
+                if (is_from) {
+                    from = net;
+                } else {
+                    to = net;
+                }
+            }
+        }
+
+        if (from == nullptr) {
+            log_error("-from is required for set_false_path (line %d)\n", lineno);
+        } else if (to == nullptr) {
+            log_error("-to is required for set_false_path (line %d)\n", lineno);
+        }
+
+        log_warning("set_false_path from: %s, to: %s does not do anything(yet).\n", from->name.c_str(ctx),
+                    to->name.c_str(ctx));
+
+        return std::string{};
+    }
+
+    void operator()()
+    {
+        while (!eof()) {
+            skip_blank(true);
+            auto args = get_arguments();
+            if (args.empty())
+                continue;
+            evaluate(args);
+        }
+    }
+};
+
+void Context::read_sdc(std::istream &in)
+{
+    std::string buf(std::istreambuf_iterator<char>(in), {});
+    SDCParser(buf, getCtx())();
+}
+
+NEXTPNR_NAMESPACE_END

From fa55e938482cb98102bb724f4c088257b60e7f4e Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Mon, 19 Aug 2024 16:13:25 +0200
Subject: [PATCH 629/712] Himbaechel xilinx : Fix regex to parse Zynq device
 names

---
 himbaechel/uarch/xilinx/xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc
index f5ff8b5a59..db987f1c5f 100644
--- a/himbaechel/uarch/xilinx/xilinx.cc
+++ b/himbaechel/uarch/xilinx/xilinx.cc
@@ -43,8 +43,8 @@ void XilinxImpl::init_database(Arch *arch)
 {
     const ArchArgs &args = arch->args;
     init_uarch_constids(arch);
-    std::regex devicere = std::regex("(xc7[azkv]\\d+t)([a-z0-9]+)-(\\dL?)");
     std::smatch match;
+    std::regex devicere = std::regex("(xc7[azkv]\\d+t?)([a-z0-9]+)-(\\dL?)");
     if (!std::regex_match(args.device, match, devicere)) {
         log_error("Invalid device %s\n", args.device.c_str());
     }

From ccdc2f6f130f5341aae051bad46d417bc2b6b984 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Thu, 5 Oct 2023 07:18:10 +0100
Subject: [PATCH 630/712] himbaechel/gowin: add timing information

---
 himbaechel/himbaechel_dbgen/chip.py      |   2 +-
 himbaechel/uarch/gowin/gowin.cc          |   2 +
 himbaechel/uarch/gowin/gowin_arch_gen.py | 148 ++++++++++++++++++++++-
 3 files changed, 145 insertions(+), 7 deletions(-)

diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 4af1c98e34..19aa8914d6 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -654,7 +654,7 @@ def set_pip_class(self, grade: str, name: str, delay: TimingValue,
     def set_bel_pin_class(self, grade: str, name: str, delay: TimingValue,
             in_cap: Optional[TimingValue]=None, out_res: Optional[TimingValue]=None):
         # bel pin classes are shared with pip classes, but this alias adds a bit of extra clarity
-        set_pip_class(self, grade, name, delay, in_cap, out_res, is_buffered=True)
+        self.set_pip_class(grade, name, delay, in_cap, out_res, is_buffered=True)
 
     def set_node_class(self, grade: str, name: str,  delay: TimingValue,
             res: Optional[TimingValue]=None, cap: Optional[TimingValue]=None):
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 7f4ae89aa8..968d2ecafb 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -168,10 +168,12 @@ void GowinImpl::init(Context *ctx)
     if (std::regex_match(pn, match, speedre)) {
         package_idx = ctx->id(match[1]);
         spd = ctx->id(match[2]);
+        ctx->set_speed_grade(match[2]);
     } else {
         if (pn.length() > 2 && pn.compare(pn.length() - 2, 2, "ES")) {
             package_idx = ctx->id(pn.substr(pn.length() - 2));
             spd = ctx->id("ES");
+            ctx->set_speed_grade("ES");
         }
     }
 
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 54d2e979e5..b74bce0761 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -231,6 +231,11 @@ def __init__(self, dups, tiletype = '', extra_func = None, sfx = 0):
         self.sfx = sfx
 created_tiletypes = {}
 
+# get timing class by wire name
+def get_tm_class(db: chipdb, wire: str):
+    assert wire in db.wire_delay, f"Unknown timing class for {wire}"
+    return db.wire_delay[wire]
+
 # u-turn at the rim
 uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
 def uturn(db: chipdb, x: int, y: int, wire: str):
@@ -341,12 +346,14 @@ def get_wire_type(name):
         if not tt.has_wire(dst):
             tt.create_wire(dst, get_wire_type(dst))
         for src in srcs.keys():
+            if src not in db.wire_delay:
+                continue
             if not tt.has_wire(src):
                 if src in {"VSS", "VCC"}:
                     tt.create_wire(src, get_wire_type(src), const_value = src)
                 else:
                     tt.create_wire(src, get_wire_type(src))
-            tt.create_pip(src, dst)
+            tt.create_pip(src, dst, get_tm_class(db, src))
 
     # clock wires
     for dst, srcs in db.grid[y][x].pure_clock_pips.items():
@@ -355,7 +362,7 @@ def get_wire_type(name):
         for src in srcs.keys():
             if not tt.has_wire(src):
                 tt.create_wire(src, "GLOBAL_CLK")
-            tt.create_pip(src, dst)
+            tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.hclk_pips:
@@ -367,7 +374,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
         for src in srcs.keys():
             if not tt.has_wire(src):
                 tt.create_wire(src, "HCLK")
-            tt.create_pip(src, dst)
+            tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
     
     hclk_bel_zs = {
         "CLKDIV2_HCLK0_SECT0": CLKDIV2_0_Z,
@@ -687,7 +694,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
     # setup LUT wires
     for i in range(8):
         for inp_name in lut_inputs:
-            tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
+            tt.create_wire(f"{inp_name}{i}", "LUT_IN")
         tt.create_wire(f"F{i}", "LUT_OUT")
         # experimental. the wire is false - it is assumed that DFF is always
         # connected to the LUT's output F{i}, but we can place primitives
@@ -720,9 +727,9 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
         if i < 6:
             # FF data can come from LUT output, but we pretend that we can use
             # any LUT input
-            tt.create_pip(f"F{i}", f"XD{i}")
+            tt.create_pip(f"F{i}", f"XD{i}", get_tm_class(db, f"F{i}"))
             for inp_name in lut_inputs:
-                tt.create_pip(f"{inp_name}{i}", f"XD{i}")
+                tt.create_pip(f"{inp_name}{i}", f"XD{i}", get_tm_class(db, f"{inp_name}{i}"))
             # FF
             ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
             tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
@@ -1151,6 +1158,134 @@ def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
     for spine, bel in dcs_bels.items():
         chip.extra_data.add_dcs_bel(spine, bel[0], bel[1], bel[2])
 
+def create_timing_info(chip: Chip, db: chipdb.Device):
+    def group_to_timingvalue(group):
+        # if himbaechel ever recognises unateness, this should match that order.
+        ff = int(group[0] * 1000)
+        fr = int(group[1] * 1000)
+        rr = int(group[2] * 1000)
+        rf = int(group[3] * 1000)
+        return TimingValue(min(ff, fr, rf, rr), max(ff, fr, rf, rr))
+
+    speed_grades = []
+    for speed, _ in db.timing.items():
+        speed_grades.append(speed)
+
+    tmg = chip.set_speed_grades(speed_grades)
+    
+    print("device {}:".format(chip.name))
+    for speed, groups in db.timing.items():
+        for group, arc in groups.items():
+            if group == "lut":
+                lut = tmg.add_cell_variant(speed, "LUT4")
+                lut.add_comb_arc("I0", "F", group_to_timingvalue(arc["a_f"]))
+                lut.add_comb_arc("I1", "F", group_to_timingvalue(arc["b_f"]))
+                lut.add_comb_arc("I2", "F", group_to_timingvalue(arc["c_f"]))
+                lut.add_comb_arc("I3", "F", group_to_timingvalue(arc["d_f"]))
+                mux5 = tmg.add_cell_variant(speed, "MUX2_LUT5")
+                mux5.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
+                mux5.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
+                mux5.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
+                mux6 = tmg.add_cell_variant(speed, "MUX2_LUT6")
+                mux6.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
+                mux6.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
+                mux6.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
+                mux7 = tmg.add_cell_variant(speed, "MUX2_LUT7")
+                mux7.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
+                mux7.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
+                mux7.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
+                mux8 = tmg.add_cell_variant(speed, "MUX2_LUT8")
+                mux8.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
+                mux8.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
+                mux8.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
+            elif group == "alu":
+                alu = tmg.add_cell_variant(speed, "ALU")
+                alu.add_comb_arc("I0", "SUM", group_to_timingvalue(arc["a_f"]))
+                alu.add_comb_arc("I1", "SUM", group_to_timingvalue(arc["b_f"]))
+                alu.add_comb_arc("I3", "SUM", group_to_timingvalue(arc["d_f"]))
+                alu.add_comb_arc("CIN", "SUM", group_to_timingvalue(arc["fci_f0"]))
+                alu.add_comb_arc("I0", "COUT", group_to_timingvalue(arc["a0_fco"]))
+                alu.add_comb_arc("I1", "COUT", group_to_timingvalue(arc["b0_fco"]))
+                alu.add_comb_arc("I3", "COUT", group_to_timingvalue(arc["d0_fco"]))
+                alu.add_comb_arc("CIN", "COUT", group_to_timingvalue(arc["fci_fco"]))
+            elif group == "sram":
+                sram = tmg.add_cell_variant(speed, "RAM16SDP4")
+                for do in range(4):
+                    for rad in range(4):
+                        sram.add_comb_arc(f"RAD[{rad}]", f"DO[{do}]", group_to_timingvalue(arc[f"rad{rad}_do"]))
+                    sram.add_clock_out("CLK", f"DO[{do}]", ClockEdge.RISING, group_to_timingvalue(arc["clk_do"]))
+                for di in range(4):
+                    sram.add_setup_hold("CLK", f"DI[{di}", ClockEdge.RISING, group_to_timingvalue(arc["clk_di_set"]), group_to_timingvalue(arc["clk_di_hold"]))
+                sram.add_setup_hold("CLK", "WRE", ClockEdge.RISING, group_to_timingvalue(arc["clk_wre_set"]), group_to_timingvalue(arc["clk_wre_hold"]))
+                for wad in range(4):
+                    sram.add_setup_hold("CLK", f"WAD[{wad}]", ClockEdge.RISING, group_to_timingvalue(arc[f"clk_wad{wad}_set"]), group_to_timingvalue(arc[f"clk_wad{wad}_hold"]))
+            elif group == "dff":
+                for reset_type in ('', 'P', 'C', 'S', 'R'):
+                    for clock_enable in ('', 'E'):
+                        cell_name = "DFF{}{}".format(reset_type, clock_enable)
+                        dff = tmg.add_cell_variant(speed, cell_name)
+                        dff.add_setup_hold("CLK", "D", ClockEdge.RISING, group_to_timingvalue(arc["di_clksetpos"]), group_to_timingvalue(arc["di_clkholdpos"]))
+                        dff.add_setup_hold("CLK", "CE", ClockEdge.RISING, group_to_timingvalue(arc["ce_clksetpos"]), group_to_timingvalue(arc["ce_clkholdpos"]))
+                        dff.add_clock_out("CLK", "Q", ClockEdge.RISING, group_to_timingvalue(arc["clk_qpos"]))
+
+                        if reset_type in ('S', 'R'):
+                            port = "RESET" if reset_type == 'R' else "SET"
+                            dff.add_setup_hold("CLK", port, ClockEdge.RISING, group_to_timingvalue(arc["lsr_clksetpos_syn"]), group_to_timingvalue(arc["lsr_clkholdpos_syn"]))
+                        elif reset_type in ('P', 'C'):
+                            port = "CLEAR" if reset_type == 'C' else "PRESET"
+                            dff.add_setup_hold("CLK", port, ClockEdge.RISING, group_to_timingvalue(arc["lsr_clksetpos_asyn"]), group_to_timingvalue(arc["lsr_clkholdpos_asyn"]))
+                            dff.add_comb_arc(port, "Q", group_to_timingvalue(arc["lsr_q"]))
+
+                        cell_name = "DFFN{}{}".format(reset_type, clock_enable)
+                        dff = tmg.add_cell_variant(speed, cell_name)
+                        dff.add_setup_hold("CLK", "D", ClockEdge.FALLING, group_to_timingvalue(arc["di_clksetneg"]), group_to_timingvalue(arc["di_clkholdneg"]))
+                        dff.add_setup_hold("CLK", "CE", ClockEdge.FALLING, group_to_timingvalue(arc["ce_clksteneg"]), group_to_timingvalue(arc["ce_clkholdneg"])) # the DBs have a typo...
+                        dff.add_clock_out("CLK", "Q", ClockEdge.FALLING, group_to_timingvalue(arc["clk_qneg"]))
+
+                        if reset_type in ('S', 'R'):
+                            port = "RESET" if reset_type == 'R' else "SET"
+                            dff.add_setup_hold("CLK", port, ClockEdge.FALLING, group_to_timingvalue(arc["lsr_clksetneg_syn"]), group_to_timingvalue(arc["lsr_clkholdneg_syn"]))
+                        elif reset_type in ('P', 'C'):
+                            port = "CLEAR" if reset_type == 'C' else "PRESET"
+                            dff.add_setup_hold("CLK", port, ClockEdge.FALLING, group_to_timingvalue(arc["lsr_clksetneg_asyn"]), group_to_timingvalue(arc["lsr_clkholdneg_asyn"]))
+                            dff.add_comb_arc(port, "Q", group_to_timingvalue(arc["lsr_q"]))
+            elif group == "bram":
+                pass # TODO
+            elif group == "fanout":
+                pass # handled in "wire"
+            elif group == "glbsrc":
+                pass # TODO
+            elif group == "hclk":
+                pass # TODO
+            elif group == "iodelay":
+                pass # TODO
+            elif group == "wire":
+                # wires with delay and fanout delay
+                for name in ["X0", "X2", "X8"]:
+                    tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]), group_to_timingvalue(groups["fanout"][f"{name}Fan"]), TimingValue(round(1e6 / groups["fanout"][f"{name}FanNum"])))
+                # wires with delay but no fanout delay
+                for name in ["X0CTL", "X0CLK", "FX1"]:
+                    tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
+                # wires with presently-unknown delay
+                for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN", "GCLK_TAP", "GCLK_BRANCH"]:
+                    tmg.set_pip_class(speed, name, TimingValue())
+                # wires with fanout-only delay; used on cell output pips
+                for name, mapping in [("LUT_OUT", "FFan"), ("FF_OUT", "QFan"), ("OF", "OFFan")]:
+                    tmg.set_pip_class(speed, name, TimingValue(), group_to_timingvalue(groups["fanout"][mapping]), TimingValue(round(1e6 / groups["fanout"][f"{mapping}Num"])))
+
+        print("speed {}:".format(speed))
+        for group, arc in groups.items():
+            print("  group {}:".format(group))
+            for name, items in arc.items():
+                print("    name {}:".format(str(name)))
+                try:
+                    items[0]
+                    for item in items:
+                        print("      item {}".format(item))
+                except TypeError:
+                    print("      item {}".format(items))
+                    continue
+
 def main():
     parser = argparse.ArgumentParser(description='Make Gowin BBA')
     parser.add_argument('-d', '--device', required=True)
@@ -1226,6 +1361,7 @@ def main():
     # Create nodes between tiles
     create_nodes(ch, db)
     create_extra_data(ch, db, chip_flags)
+    create_timing_info(ch, db)
     ch.write_bba(args.output)
 if __name__ == '__main__':
     main()

From 01737a400c1f14315c58d0b11e1e9ae05fac9d49 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sun, 18 Aug 2024 07:43:07 +1000
Subject: [PATCH 631/712] Gowin. Add clock wires delays.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index b74bce0761..bfcbdb2cc3 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -362,7 +362,11 @@ def get_wire_type(name):
         for src in srcs.keys():
             if not tt.has_wire(src):
                 tt.create_wire(src, "GLOBAL_CLK")
-            tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
+            src_tm_class = get_tm_class(db, src)
+            if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}:
+                tt.create_pip(src, dst, src_tm_class, flags = PIP_FLAG_FIXED_DELAY)
+            else:
+                tt.create_pip(src, dst, src_tm_class)
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.hclk_pips:
@@ -1172,7 +1176,7 @@ def group_to_timingvalue(group):
         speed_grades.append(speed)
 
     tmg = chip.set_speed_grades(speed_grades)
-    
+
     print("device {}:".format(chip.name))
     for speed, groups in db.timing.items():
         for group, arc in groups.items():
@@ -1254,7 +1258,11 @@ def group_to_timingvalue(group):
             elif group == "fanout":
                 pass # handled in "wire"
             elif group == "glbsrc":
-                pass # TODO
+                # TODO
+                # no fanout delay for clock wires
+                for name in ["CENT_SPINE_PCLK", "SPINE_TAP_PCLK", "TAP_BRANCH_PCLK"]:
+                    tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
+                tmg.set_pip_class(speed, 'GCLK_BRANCH', group_to_timingvalue(arc['BRANCH_PCLK']))
             elif group == "hclk":
                 pass # TODO
             elif group == "iodelay":
@@ -1267,7 +1275,7 @@ def group_to_timingvalue(group):
                 for name in ["X0CTL", "X0CLK", "FX1"]:
                     tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
                 # wires with presently-unknown delay
-                for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN", "GCLK_TAP", "GCLK_BRANCH"]:
+                for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN"]:
                     tmg.set_pip_class(speed, name, TimingValue())
                 # wires with fanout-only delay; used on cell output pips
                 for name, mapping in [("LUT_OUT", "FFan"), ("FF_OUT", "QFan"), ("OF", "OFFan")]:

From 32e2d9223c5e554860ad8d98fb02f441a5615a2b Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 21 Aug 2024 20:22:07 +1000
Subject: [PATCH 632/712] Gowin. BUGFIX. Timing

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index bfcbdb2cc3..5f0e4ac2fd 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -364,8 +364,6 @@ def get_wire_type(name):
                 tt.create_wire(src, "GLOBAL_CLK")
             src_tm_class = get_tm_class(db, src)
             if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}:
-                tt.create_pip(src, dst, src_tm_class, flags = PIP_FLAG_FIXED_DELAY)
-            else:
                 tt.create_pip(src, dst, src_tm_class)
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
@@ -379,7 +377,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
             if not tt.has_wire(src):
                 tt.create_wire(src, "HCLK")
             tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
-    
+
     hclk_bel_zs = {
         "CLKDIV2_HCLK0_SECT0": CLKDIV2_0_Z,
         "CLKDIV2_HCLK0_SECT1": CLKDIV2_1_Z,
@@ -390,7 +388,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
         "CLKDIV_HCLK1_SECT0": CLKDIV_2_Z,
         "CLKDIV_HCLK1_SECT1": CLKDIV_3_Z
     }
-   
+
     for bel_name, bel_props in db.grid[y][x].bels.items():
         if (bel_name not in hclk_bel_zs):
             continue
@@ -402,7 +400,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
             bel_type = "CLKDIV"
         this_bel = tt.create_bel(bel_name, bel_type, hclk_bel_zs[bel_name])
 
-        if (bel_name in ["CLKDIV_HCLK0_SECT1", "CLKDIV_HCLK1_SECT1"]): 
+        if (bel_name in ["CLKDIV_HCLK0_SECT1", "CLKDIV_HCLK1_SECT1"]):
             this_bel.flags |= BEL_FLAG_HIDDEN
         if bel_type=="CLKDIV":
             this_bel.flags |= BEL_FLAG_GLOBAL

From 2dc712130cfd6e14f488b410add88d98f1aadc14 Mon Sep 17 00:00:00 2001
From: Christian Fibich <fibich@technikum-wien.at>
Date: Wed, 21 Aug 2024 12:36:23 +0200
Subject: [PATCH 633/712] allow LFD2NX devices to be specified with --device
 (#1353)

---
 nexus/arch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nexus/arch.cc b/nexus/arch.cc
index e6ff2e13f4..b66462537a 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -48,7 +48,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 Arch::Arch(ArchArgs args) : args(args)
 {
     // Parse device string
-    if (boost::starts_with(args.device, "LIFCL")) {
+    if (boost::starts_with(args.device, "LIFCL") || boost::starts_with(args.device, "LFD2NX")) {
         family = "LIFCL";
     } else {
         log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());

From 4cf7afedf7b11c461d8ff252552d051ee6d5a1c8 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 4 Sep 2024 20:55:35 +1000
Subject: [PATCH 634/712] Gowin. Implement the UserFlash primitive (#1357)

* Gowin. Implement the UserFlash primitive

Some Gowin chips have embedded flash memory accessible from the fabric.
Here we add primitives that allow access to this memory.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix cell creation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      | 37 ++++++++-
 himbaechel/uarch/gowin/gowin.h           | 12 ++-
 himbaechel/uarch/gowin/gowin_arch_gen.py | 16 +++-
 himbaechel/uarch/gowin/pack.cc           | 97 ++++++++++++++++++++++++
 4 files changed, 159 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index fcadd941ef..62a4036057 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1193,7 +1193,42 @@ X(BOTTOM_IO_PORT_A)
 X(BOTTOM_IO_PORT_B)
 X(IOLOGIC_DUMMY)
 
-// 
+// User Flash
+X(INUSEN)
+X(DIN)
+X(DOUT)
+X(XE)
+X(YE)
+X(SE)
+X(PROG)
+X(ERASE)
+X(NVSTR)
+X(XADR0)
+X(XADR1)
+X(XADR2)
+X(XADR3)
+X(XADR4)
+X(XADR5)
+X(XADR6)
+X(XADR7)
+X(XADR8)
+X(YADR)
+X(RA)
+X(CA)
+X(PA)
+X(MODE)
+X(SEQ)
+X(RMODE)
+X(WMODE)
+X(RBYTESEL)
+X(WBYTESEL)
+X(FLASH96K)
+X(FLASH256K)
+X(FLASH608K)
+X(FLASH128K)
+X(FLASH64K)
+X(FLASH64KZ)
+X(FLASH96KA)
 
 // wire types
 X(GLOBAL_CLK)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index c14949d665..81c825f4da 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -73,6 +73,14 @@ inline bool is_clkdiv2(const CellInfo *cell) { return type_is_clkdiv2(cell->type
 // Return true for HCLK Cells
 inline bool is_hclk(const CellInfo *cell) { return type_is_clkdiv2(cell->type) || type_is_clkdiv(cell->type); }
 
+// Return true if a cell is a UserFlash
+inline bool type_is_userflash(IdString cell_type)
+{
+    return cell_type.in(id_FLASH96K, id_FLASH256K, id_FLASH608K, id_FLASH128K, id_FLASH64K, id_FLASH64K, id_FLASH64KZ,
+                        id_FLASH96KA);
+}
+inline bool is_userflash(const CellInfo *cell) { return type_is_userflash(cell->type); }
+
 // ==========================================
 // extra data in the chip db
 // ==========================================
@@ -155,7 +163,9 @@ enum
     BANDGAP_Z = 279,
 
     DQCE_Z = 280, // : 286 reserve for 6 DQCEs
-    DCS_Z = 286,  // : 287 reserve for 2 DCSs
+    DCS_Z = 286,  // : 288 reserve for 2 DCSs
+
+    USERFLASH_Z = 288,
 
     // The two least significant bits encode Z for 9-bit adders and
     // multipliers, if they are equal to 0, then we get Z of their common
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 5f0e4ac2fd..5457fc621f 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -50,7 +50,9 @@
 BANDGAP_Z = 279
 
 DQCE_Z = 280 # : 286 reserve for 6 DQCEs
-DCS_Z  = 286 # : 287 reserve for 2 DCSs
+DCS_Z  = 286 # : 288 reserve for 2 DCSs
+
+USERFLASH_Z = 288
 
 DSP_Z          = 509
 
@@ -527,6 +529,18 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                     bel.flags = BEL_FLAG_GLOBAL
                     tt.add_bel_pin(bel, "I", wire, PinType.INPUT)
                     tt.add_bel_pin(bel, "O", wire_out, PinType.OUTPUT)
+        elif func == 'userflash':
+                bel = tt.create_bel("USERFLASH", desc['type'], USERFLASH_Z)
+                portmap = desc['ins']
+                for port, wire in portmap.items():
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "FLASH_IN")
+                    tt.add_bel_pin(bel, port, wire, PinType.INPUT)
+                portmap = desc['outs']
+                for port, wire in portmap.items():
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "FLASH_OUT")
+                    tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
 
 def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     has_extra_func = (y, x) in db.extra_func
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index ec1ef8f15e..b7b64a4813 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -3006,6 +3006,8 @@ struct GowinPacker
     // =========================================
     void pack_dqce()
     {
+        log_info("Pack DQCE cells...\n");
+
         // At the placement stage, nothing can be said definitively about DQCE,
         // so we make user cells virtual but allocate all available bels by
         // creating and placing cells - we will use some of them after, and
@@ -3039,6 +3041,8 @@ struct GowinPacker
     // =========================================
     void pack_dcs()
     {
+        log_info("Pack DCS cells...\n");
+
         // At the placement stage, nothing can be said definitively about DCS,
         // so we make user cells virtual but allocate all available bels by
         // creating and placing cells - we will use some of them after, and
@@ -3072,6 +3076,96 @@ struct GowinPacker
         }
     }
 
+    // =========================================
+    // Enable UserFlash
+    // =========================================
+    void pack_userflash()
+    {
+        log_info("Pack UserFlash cells...\n");
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (!is_userflash(&ci)) {
+                continue;
+            }
+
+            if (ci.type.in(id_FLASH96K, id_FLASH256K, id_FLASH608K)) {
+                // enable
+                ci.addInput(id_INUSEN);
+                ci.connectPort(id_INUSEN, ctx->nets.at(ctx->id("$PACKER_GND")).get());
+            }
+            // rename ports
+            for (int i = 0; i < 32; ++i) {
+                ci.renamePort(ctx->idf("DIN[%d]", i), ctx->idf("DIN%d", i));
+                ci.renamePort(ctx->idf("DOUT[%d]", i), ctx->idf("DOUT%d", i));
+            }
+            if (ci.type.in(id_FLASH96K)) {
+                for (int i = 0; i < 6; ++i) {
+                    ci.renamePort(ctx->idf("RA[%d]", i), ctx->idf("RA%d", i));
+                    ci.renamePort(ctx->idf("CA[%d]", i), ctx->idf("CA%d", i));
+                    ci.renamePort(ctx->idf("PA[%d]", i), ctx->idf("PA%d", i));
+                }
+                for (int i = 0; i < 2; ++i) {
+                    ci.renamePort(ctx->idf("MODE[%d]", i), ctx->idf("MODE%d", i));
+                    ci.renamePort(ctx->idf("SEQ[%d]", i), ctx->idf("SEQ%d", i));
+                    ci.renamePort(ctx->idf("RMODE[%d]", i), ctx->idf("RMODE%d", i));
+                    ci.renamePort(ctx->idf("WMODE[%d]", i), ctx->idf("WMODE%d", i));
+                    ci.renamePort(ctx->idf("RBYTESEL[%d]", i), ctx->idf("RBYTESEL%d", i));
+                    ci.renamePort(ctx->idf("WBYTESEL[%d]", i), ctx->idf("WBYTESEL%d", i));
+                }
+            } else {
+                for (int i = 0; i < 9; ++i) {
+                    ci.renamePort(ctx->idf("XADR[%d]", i), ctx->idf("XADR%d", i));
+                }
+                for (int i = 0; i < 6; ++i) {
+                    ci.renamePort(ctx->idf("YADR[%d]", i), ctx->idf("YADR%d", i));
+                }
+            }
+            // add invertor
+            int lut_idx = 0;
+            auto add_inv = [&](IdString port, PortType port_type) {
+                if (!port_used(&ci, port)) {
+                    return;
+                }
+
+                std::unique_ptr<CellInfo> lut_cell =
+                        gwu.create_cell(create_aux_name(ci.name, lut_idx, "_lut$"), id_LUT4);
+                new_cells.push_back(std::move(lut_cell));
+                CellInfo *lut = new_cells.back().get();
+                lut->addInput(id_I0);
+                lut->addOutput(id_F);
+                lut->setParam(id_INIT, 0x5555);
+                ++lut_idx;
+
+                if (port_type == PORT_IN) {
+                    ci.movePortTo(port, lut, id_I0);
+                    lut->connectPorts(id_F, &ci, port);
+                } else {
+                    ci.movePortTo(port, lut, id_F);
+                    ci.connectPorts(port, lut, id_I0);
+                }
+            };
+            for (auto pin : ci.ports) {
+                if (pin.second.type == PORT_OUT) {
+                    add_inv(pin.first, PORT_OUT);
+                } else {
+                    if (pin.first == id_INUSEN) {
+                        continue;
+                    }
+                    if (ci.type == id_FLASH608K && pin.first.in(id_XADR0, id_XADR1, id_XADR2, id_XADR3, id_XADR4,
+                                                                id_XADR5, id_XADR6, id_XADR7, id_XADR8)) {
+                        continue;
+                    }
+                    add_inv(pin.first, PORT_IN);
+                }
+            }
+        }
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+    }
+
     void run(void)
     {
         handle_constants();
@@ -3124,6 +3218,9 @@ struct GowinPacker
         pack_buffered_nets();
         ctx->check();
 
+        pack_userflash();
+        ctx->check();
+
         pack_dqce();
         ctx->check();
 

From 4d1de4532acf35bf4fdeea8bfcfb0e8b9ad3578c Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Fri, 6 Sep 2024 06:39:26 +1000
Subject: [PATCH 635/712] Gowin. BUGFIX. Create all Clock Pips. (#1358)

Some Clocks PIPS were not created due to a check for the presence of a
delay class, now all wires are attributed to the class so that there is
no longer any need for this check.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_arch_gen.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 5457fc621f..425d9171b1 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -365,8 +365,7 @@ def get_wire_type(name):
             if not tt.has_wire(src):
                 tt.create_wire(src, "GLOBAL_CLK")
             src_tm_class = get_tm_class(db, src)
-            if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}:
-                tt.create_pip(src, dst, src_tm_class)
+            tt.create_pip(src, dst, src_tm_class)
 
 def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.hclk_pips:

From 8d0f52fbf9b0bf4356ad342d8cc3b5fa6e423520 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Wed, 11 Sep 2024 08:23:46 +0200
Subject: [PATCH 636/712] timing: Move towards DelayPairs for timing reporting
 (#1359)

---
 common/kernel/nextpnr_types.h | 47 +++++++++++++++++++++++++++++------
 common/kernel/report.cc       | 25 +++++++++++++------
 common/kernel/timing.cc       | 22 +++++++++-------
 common/kernel/timing.h        | 18 ++++++--------
 common/kernel/timing_log.cc   | 40 ++++++++++++++++++-----------
 5 files changed, 102 insertions(+), 50 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 163ad2f266..ec1ac11101 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -80,7 +80,7 @@ struct PortRef
 // minimum and maximum delay
 struct DelayPair
 {
-    DelayPair(){};
+    DelayPair() : min_delay(0), max_delay(0) {};
     explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) {}
     DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) {}
     delay_t minDelay() const { return min_delay; }
@@ -94,13 +94,25 @@ struct DelayPair
     {
         return {min_delay - other.min_delay, max_delay - other.max_delay};
     }
+    DelayPair &operator+=(const DelayPair &rhs)
+    {
+        min_delay += rhs.min_delay;
+        max_delay += rhs.max_delay;
+        return *this;
+    }
+    DelayPair &operator-=(const DelayPair &rhs)
+    {
+        min_delay -= rhs.min_delay;
+        max_delay -= rhs.max_delay;
+        return *this;
+    }
 };
 
 // four-quadrant, min and max rise and fall delay
 struct DelayQuad
 {
     DelayPair rise, fall;
-    DelayQuad() {}
+    DelayQuad() : rise(0), fall(0) {}
     explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) {}
     DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) {}
     DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) {}
@@ -120,6 +132,19 @@ struct DelayQuad
 
     DelayQuad operator+(const DelayQuad &other) const { return {rise + other.rise, fall + other.fall}; }
     DelayQuad operator-(const DelayQuad &other) const { return {rise - other.rise, fall - other.fall}; }
+    DelayQuad &operator+=(const DelayQuad &rhs)
+    {
+        rise += rhs.rise;
+        fall += rhs.fall;
+        return *this;
+    }
+
+    DelayQuad &operator-=(const DelayQuad &rhs)
+    {
+        rise -= rhs.rise;
+        fall -= rhs.fall;
+        return *this;
+    }
 };
 
 struct ClockConstraint;
@@ -200,7 +225,7 @@ struct PseudoCell
     virtual bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const = 0;
     virtual TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const = 0;
     virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const = 0;
-    virtual ~PseudoCell(){};
+    virtual ~PseudoCell() {};
 };
 
 struct RegionPlug : PseudoCell
@@ -336,15 +361,18 @@ struct CriticalPath
         // To cell.port
         std::pair<IdString, IdString> to;
         // Segment delay
-        delay_t delay;
+        DelayPair delay;
     };
 
     // Clock pair
     ClockPair clock_pair;
     // Total path delay
-    delay_t delay;
-    // Period (max allowed delay)
-    delay_t period;
+    DelayPair delay;
+
+    // if delay.minDelay() < bound.minDelay() then this is a hold violation
+    // if delay.maxDelay() > bound.maxDelay() then this is a setup violation
+    DelayPair bound;
+
     // Individual path segments
     std::vector<Segment> segments;
 };
@@ -357,7 +385,7 @@ struct NetSinkTiming
     // Cell and port (the sink)
     std::pair<IdString, IdString> cell_port;
     // Delay
-    delay_t delay;
+    DelayPair delay;
 };
 
 struct TimingResult
@@ -379,6 +407,9 @@ struct TimingResult
 
     // Histogram of slack
     dict<int, unsigned> slack_histogram;
+
+    // TODO: Hold time violations
+    // dict<IdString, CriticalPath> hold_violations;
 };
 
 // Represents the contents of a non-leaf cell in a design
diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index 5fa51b6f59..917740b96c 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -73,11 +73,11 @@ static Json::array json_report_critical_paths(const Context *ctx)
                                         {"port", segment.to.second.c_str(ctx)},
                                         {"loc", Json::array({toLoc.x, toLoc.y})}});
 
-            auto segmentJson = Json::object({
-                    {"delay", ctx->getDelayNS(segment.delay)},
-                    {"from", fromJson},
-                    {"to", toJson},
-            });
+            auto minDelay = ctx->getDelayNS(segment.delay.minDelay());
+            auto maxDelay = ctx->getDelayNS(segment.delay.maxDelay());
+
+            auto segmentJson =
+                    Json::object({{"delay", Json::array({minDelay, maxDelay})}, {"from", fromJson}, {"to", toJson}});
 
             if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
                 segmentJson["type"] = "clk-to-q";
@@ -130,10 +130,13 @@ static Json::array json_report_detailed_net_timings(const Context *ctx)
 
         Json::array endpointsJson;
         for (const auto &sink_timing : it.second) {
+            auto minDelay = ctx->getDelayNS(sink_timing.delay.minDelay());
+            auto maxDelay = ctx->getDelayNS(sink_timing.delay.maxDelay());
+
             auto endpointJson = Json::object({{"cell", sink_timing.cell_port.first.c_str(ctx)},
                                               {"port", sink_timing.cell_port.second.c_str(ctx)},
                                               {"event", clock_event_name(ctx, sink_timing.clock_pair.end)},
-                                              {"delay", ctx->getDelayNS(sink_timing.delay)}});
+                                              {"delay", Json::array({minDelay, maxDelay})}});
             endpointsJson.push_back(endpointJson);
         }
 
@@ -191,7 +194,10 @@ Report JSON structure:
           },
           "type": <path segment type "clk-to-q", "source", "logic", "routing" or "setup">,
           "net": <net name (for routing only!)>,
-          "delay": <segment delay [ns]>,
+          "delay": [
+            <minimum segment delay [ns]>,
+            <maximum segment delay [ns]>,
+          ],
         }
         ...
       ]
@@ -209,7 +215,10 @@ Report JSON structure:
           "cell": <sink cell name>,
           "port": <sink cell port name>,
           "event": <destination clock event name>,
-          "delay": <delay [ns]>,
+          "delay": [
+            <minimum segment delay [ns]>,
+            <maximum segment delay [ns]>,
+          ],
         }
         ...
       ]
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7256ed1b18..105d20f906 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -502,6 +502,8 @@ void TimingAnalyser::identify_related_domains()
 
 void TimingAnalyser::reset_times()
 {
+    static const auto init_delay =
+            DelayPair(std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest());
     for (auto &port : ports) {
         auto do_reset = [&](dict<domain_id_t, ArrivReqTime> &times) {
             for (auto &t : times) {
@@ -758,7 +760,7 @@ void TimingAnalyser::build_detailed_net_timing_report()
                     sink_timing.clock_pair.end.clock = capture.clock;
                     sink_timing.clock_pair.end.edge = capture.edge;
                     sink_timing.cell_port = std::make_pair(pd.cell_port.cell, pd.cell_port.port);
-                    sink_timing.delay = arr.second.value.max_delay;
+                    sink_timing.delay = arr.second.value;
 
                     net_timings[net->name].push_back(sink_timing);
                 }
@@ -802,23 +804,25 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto &launch = domains.at(dp.key.launch).key;
     auto &capture = domains.at(dp.key.capture).key;
 
+    report.delay = DelayPair(0);
+
     report.clock_pair.start.clock = launch.clock;
     report.clock_pair.start.edge = launch.edge;
     report.clock_pair.end.clock = capture.clock;
     report.clock_pair.end.edge = capture.edge;
 
-    report.period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
+    report.bound = DelayPair(0, ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")));
     if (launch.edge != capture.edge) {
-        report.period = report.period / 2;
+        report.bound.max_delay = report.bound.max_delay / 2;
     }
 
     if (!launch.is_async() && ctx->nets.at(launch.clock)->clkconstr) {
         if (launch.edge == capture.edge) {
-            report.period = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
         } else if (capture.edge == RISING_EDGE) {
-            report.period = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
         } else if (capture.edge == FALLING_EDGE) {
-            report.period = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
         }
     }
 
@@ -895,13 +899,13 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
             seg_logic.type = CriticalPath::Segment::Type::LOGIC;
         }
 
-        seg_logic.delay = comb_delay.maxDelay();
+        seg_logic.delay = comb_delay.delayPair();
         seg_logic.from = std::make_pair(last_cell->name, last_port);
         seg_logic.to = std::make_pair(driver_cell->name, driver.port);
         seg_logic.net = IdString();
         report.segments.push_back(seg_logic);
 
-        auto net_delay = ctx->getNetinfoRouteDelay(net, sink);
+        auto net_delay = DelayPair(ctx->getNetinfoRouteDelay(net, sink));
 
         CriticalPath::Segment seg_route;
         seg_route.type = CriticalPath::Segment::Type::ROUTING;
@@ -919,7 +923,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto sinkClass = ctx->getPortTimingClass(crit_path.back().cell, crit_path.back().port, clockCount);
     if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
         auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back().cell, crit_path.back().port, 0);
-        delay_t setup = sinkClockInfo.setup.maxDelay();
+        auto setup = sinkClockInfo.setup;
 
         CriticalPath::Segment seg_logic;
         seg_logic.type = CriticalPath::Segment::Type::SETUP;
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 3dabe4f1d3..dae3ba27e1 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -27,8 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct CellPortKey
 {
-    CellPortKey(){};
-    CellPortKey(IdString cell, IdString port) : cell(cell), port(port){};
+    CellPortKey() {};
+    CellPortKey(IdString cell, IdString port) : cell(cell), port(port) {};
     explicit CellPortKey(const PortRef &pr)
     {
         NPNR_ASSERT(pr.cell != nullptr);
@@ -49,7 +49,7 @@ struct ClockDomainKey
 {
     IdString clock;
     ClockEdge edge;
-    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge){};
+    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge) {};
     // probably also need something here to deal with constraints
     inline bool is_async() const { return clock == IdString(); }
 
@@ -63,7 +63,7 @@ typedef int domain_id_t;
 struct ClockDomainPairKey
 {
     domain_id_t launch, capture;
-    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture){};
+    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture) {};
     inline bool operator==(const ClockDomainPairKey &other) const
     {
         return (launch == other.launch) && (capture == other.capture);
@@ -128,8 +128,6 @@ struct TimingAnalyser
     // get the N worst endpoints for a given domain pair
     std::vector<CellPortKey> get_worst_eps(domain_id_t domain_pair, int count);
 
-    const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
-
     // Set arrival/required times if more/less than the current value
     void set_arrival_time(CellPortKey target, domain_id_t domain, DelayPair arrival, int path_length,
                           CellPortKey prev = CellPortKey());
@@ -174,9 +172,9 @@ struct TimingAnalyser
         ClockEdge edge;
 
         CellArc(ArcType type, IdString other_port, DelayQuad value)
-                : type(type), other_port(other_port), value(value), edge(RISING_EDGE){};
+                : type(type), other_port(other_port), value(value), edge(RISING_EDGE) {};
         CellArc(ArcType type, IdString other_port, DelayQuad value, ClockEdge edge)
-                : type(type), other_port(other_port), value(value), edge(edge){};
+                : type(type), other_port(other_port), value(value), edge(edge) {};
     };
 
     // Timing data for every cell port
@@ -200,7 +198,7 @@ struct TimingAnalyser
 
     struct PerDomain
     {
-        PerDomain(ClockDomainKey key) : key(key){};
+        PerDomain(ClockDomainKey key) : key(key) {};
         ClockDomainKey key;
         // these are pairs (signal port; clock port)
         std::vector<std::pair<CellPortKey, IdString>> startpoints, endpoints;
@@ -208,7 +206,7 @@ struct TimingAnalyser
 
     struct PerDomainPair
     {
-        PerDomainPair(ClockDomainPairKey key) : key(key){};
+        PerDomainPair(ClockDomainPairKey key) : key(key) {};
         ClockDomainPairKey key;
         DelayPair period{0};
         delay_t worst_setup_slack, worst_hold_slack;
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 1bc1e1168a..24aac66589 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -68,7 +68,18 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
 
     // A helper function for reporting one critical path
     auto print_path_report = [ctx](const CriticalPath &path) {
-        delay_t total = 0, logic_total = 0, route_total = 0;
+        DelayPair total(0), logic_total(0), route_total(0);
+
+        // We print out the max delay since that's usually the interesting case
+        // But if we know this critical path has violated hold time we print the
+        // min delay instead
+        bool hold_violation = path.delay.minDelay() < path.bound.minDelay();
+        auto get_delay_ns = [hold_violation, ctx](const DelayPair &d) {
+            if (hold_violation) {
+                ctx->getDelayNS(d.minDelay());
+            }
+            return ctx->getDelayNS(d.maxDelay());
+        };
 
         log_info("curr total\n");
         for (const auto &segment : path.segments) {
@@ -83,10 +94,10 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
 
                 const std::string type_name = (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
 
-                log_info("%4.1f %4.1f  %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
-                         type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+                log_info("%4.1f %4.1f  %s %s.%s\n", get_delay_ns(segment.delay), get_delay_ns(total), type_name.c_str(),
+                         segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
-                route_total += segment.delay;
+                route_total = route_total + segment.delay;
 
                 const auto &driver = ctx->cells.at(segment.from.first);
                 const auto &sink = ctx->cells.at(segment.to.first);
@@ -94,9 +105,8 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto driver_loc = ctx->getBelLocation(driver->bel);
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
-                         ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
-                         sink_loc.y);
+                log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", get_delay_ns(segment.delay), get_delay_ns(total),
+                         segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
                 log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
 
                 const NetInfo *net = ctx->nets.at(segment.net).get();
@@ -134,7 +144,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 }
             }
         }
-        log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
+        log_info("%.1f ns logic, %.1f ns routing\n", get_delay_ns(logic_total), get_delay_ns(route_total));
     };
 
     // Single domain paths
@@ -223,7 +233,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
                 continue;
             }
 
-            delay_t path_delay = 0;
+            DelayPair path_delay(0);
             for (const auto &segment : report.segments) {
                 path_delay += segment.delay;
             }
@@ -232,13 +242,13 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             // result is negative then only the latter matters. Otherwise
             // the compensated path delay is taken.
             auto clock_delay = result.clock_delays.at(key);
-            path_delay -= clock_delay;
+            path_delay -= DelayPair(clock_delay);
 
             float fmax = std::numeric_limits<float>::infinity();
-            if (path_delay < 0) {
+            if (path_delay.maxDelay() < 0) {
                 fmax = 1e3f / ctx->getDelayNS(clock_delay);
-            } else if (path_delay > 0) {
-                fmax = 1e3f / ctx->getDelayNS(path_delay);
+            } else if (path_delay.maxDelay() > 0) {
+                fmax = 1e3f / ctx->getDelayNS(path_delay.maxDelay());
             }
 
             // Both clocks are related so they should have the same
@@ -306,12 +316,12 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     for (auto &report : result.xclock_paths) {
         const ClockEvent &a = report.clock_pair.start;
         const ClockEvent &b = report.clock_pair.end;
-        delay_t path_delay = 0;
+        DelayPair path_delay(0);
         for (const auto &segment : report.segments) {
             path_delay += segment.delay;
         }
         auto ev_a = clock_event_name(ctx, a, start_field_width), ev_b = clock_event_name(ctx, b, end_field_width);
-        log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
+        log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay.maxDelay()));
     }
     log_break();
 }

From ff7b8535bc78a1253b053ea5d7ce84065a39bcaf Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 11 Sep 2024 19:18:26 +1000
Subject: [PATCH 637/712] Gowin. Add DHCEN primitive. (#1349)

* Gowin. Add DHCEN primitive.

This primitive allows you to dynamically turn off and turn on the
networks of high-speed clocks.

This is done tracking the routes to the sinks and if the route passes
through a special HCLK MUX (this may be the input MUX or the output MUX,
as well as the interbank MUX), then the control signal of this MUX is
used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Change the DHCEN binding

Use the entire PIP instead of a wire - avoids normalisation and may also
be useful in the future when calculating clock stuff.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   4 +-
 himbaechel/uarch/gowin/globals.cc        | 133 +++++++++++++++++++----
 himbaechel/uarch/gowin/gowin.h           |  19 +++-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  50 ++++++++-
 himbaechel/uarch/gowin/gowin_utils.cc    |  16 +++
 himbaechel/uarch/gowin/gowin_utils.h     |   1 +
 himbaechel/uarch/gowin/pack.cc           |  33 ++++++
 7 files changed, 229 insertions(+), 27 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 62a4036057..e8e6874a6d 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1269,10 +1269,12 @@ X(BUFG)
 X(CLOCK)
 X(DQCE)
 X(DCS)
-X(DCS_MODE)
 X(DQCE_PIP)
+X(DHCEN_USED)
 X(DCS_USED)
 X(SELFORCE)
+X(DHCEN)
+X(DCS_MODE)
 
 //HCLK Bels
 X(CLKDIV)
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index e510174b49..4e1f8f7125 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -134,7 +134,8 @@ struct GowinGlobalRouter
 
     // Dedicated backwards BFS routing for global networks
     template <typename Tfilt>
-    bool backwards_bfs_route(NetInfo *net, WireId src, WireId dst, int iter_limit, bool strict, Tfilt pip_filter)
+    bool backwards_bfs_route(NetInfo *net, WireId src, WireId dst, int iter_limit, bool strict, Tfilt pip_filter,
+                             std::vector<PipId> *path = nullptr)
     {
         // Queue of wires to visit
         std::queue<WireId> visit;
@@ -208,6 +209,9 @@ struct GowinGlobalRouter
                     break;
                 }
                 ctx->bindPip(pip, net, STRENGTH_LOCKED);
+                if (path != nullptr) {
+                    path->push_back(pip);
+                }
             }
             return true;
         } else {
@@ -225,6 +229,7 @@ struct GowinGlobalRouter
     bool driver_is_buf(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_BUFG, id_O); }
     bool driver_is_dqce(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_DQCE, id_CLKOUT); }
     bool driver_is_dcs(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_DCS, id_CLKOUT); }
+    bool driver_is_dhcen(const PortRef &driver) { return CellTypePort(driver) == CellTypePort(id_DHCEN, id_CLKOUT); }
     bool driver_is_clksrc(const PortRef &driver)
     {
         // dedicated pins
@@ -276,7 +281,9 @@ struct GowinGlobalRouter
         ROUTED_ALL
     };
 
-    RouteResult route_direct_net(NetInfo *net, WireId aux_src = WireId(), bool DCS_pips = false, bool DQCE_pips = false)
+    template <typename Tfilter>
+    RouteResult route_direct_net(NetInfo *net, Tfilter pip_filter, WireId aux_src = WireId(),
+                                 std::vector<PipId> *path = nullptr)
     {
         WireId src;
         src = aux_src == WireId() ? ctx->getNetinfoSourceWire(net) : aux_src;
@@ -297,21 +304,9 @@ struct GowinGlobalRouter
                           ctx->nameOf(usr.port));
             }
             bool bfs_res;
-            if (DCS_pips) {
-                bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                    return (is_relaxed_sink(usr) || global_DCS_pip_filter(pip));
-                });
-            } else {
-                if (DQCE_pips) {
-                    bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                        return (is_relaxed_sink(usr) || global_DQCE_pip_filter(pip));
-                    });
-                } else {
-                    bfs_res = backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) {
-                        return (is_relaxed_sink(usr) || global_pip_filter(pip));
-                    });
-                }
-            }
+            bfs_res = backwards_bfs_route(
+                    net, src, dst, 1000000, false, [&](PipId pip) { return (is_relaxed_sink(usr) || pip_filter(pip)); },
+                    path);
             if (bfs_res) {
                 routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
             } else {
@@ -345,7 +340,8 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(net, src, false, true);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip) { return global_DQCE_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -422,7 +418,8 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(net, src, true);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip) { return global_DCS_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -487,6 +484,84 @@ struct GowinGlobalRouter
         ctx->cells.erase(dcs_ci->name);
     }
 
+    void route_dhcen_net(NetInfo *net)
+    {
+        // route net after dhcen source of CLKIN net
+        CellInfo *dhcen_ci = net->driver.cell;
+
+        NetInfo *net_before_dhcen = dhcen_ci->getPort(id_CLKIN);
+        NPNR_ASSERT(net_before_dhcen != nullptr);
+
+        PortRef driver = net_before_dhcen->driver;
+        NPNR_ASSERT_MSG(driver_is_buf(driver) || driver_is_clksrc(driver),
+                        stringf("The input source for %s is not a clock.", ctx->nameOf(dhcen_ci)).c_str());
+
+        IdString port;
+        // use BUF input if there is one
+        if (driver_is_buf(driver)) {
+            port = id_I;
+        } else {
+            port = driver.port;
+        }
+        WireId src = ctx->getBelPinWire(driver.cell->bel, port);
+
+        std::vector<PipId> path;
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip) { return global_pip_filter(pip); }, src, &path);
+        if (route_result == NOT_ROUTED) {
+            log_error("Can't route the %s network.\n", ctx->nameOf(net));
+        }
+        if (route_result == ROUTED_PARTIALLY) {
+            log_error("It was not possible to completely route the %s net using only global resources. This is not "
+                      "allowed for dhcen managed networks.\n",
+                      ctx->nameOf(net));
+        }
+
+        // In networks controlled by dhcen we disable/enable only HCLK - if
+        // there are ordinary cells among the sinks, then they are not affected
+        // by this primitive.
+        for (PipId pip : path) {
+            // move to upper level net
+            ctx->unbindPip(pip);
+            ctx->bindPip(pip, net_before_dhcen, STRENGTH_LOCKED);
+
+            WireId dst = ctx->getPipDstWire(pip);
+            IdString side;
+            BelId dhcen_bel = gwu.get_dhcen_bel(dst, side);
+            if (dhcen_bel == BelId()) {
+                continue;
+            }
+
+            // One pseudo dhcen can be implemented as several hardware dhcen.
+            // Here we find suitable hardware dhcens.
+            CellInfo *hw_dhcen = ctx->getBoundBelCell(dhcen_bel);
+            if (ctx->debug) {
+                log_info("  use %s wire and %s bel for '%s' hw cell.\n", ctx->nameOfWire(dst),
+                         ctx->nameOfBel(dhcen_bel), ctx->nameOf(hw_dhcen));
+            }
+
+            // The control network must connect the CE inputs of all hardware dhcens.
+            hw_dhcen->setAttr(id_DHCEN_USED, 1);
+            dhcen_ci->copyPortTo(id_CE, hw_dhcen, id_CE);
+        }
+
+        // connect all users to upper level net
+        std::vector<PortRef> users;
+        for (auto &cell_port : net->users) {
+            users.push_back(cell_port);
+        }
+        for (PortRef &user : users) {
+            user.cell->disconnectPort(user.port);
+            user.cell->connectPort(user.port, net_before_dhcen);
+        }
+
+        // remove the virtual dhcen
+        dhcen_ci->disconnectPort(id_CLKOUT);
+        dhcen_ci->disconnectPort(id_CLKIN);
+        dhcen_ci->disconnectPort(id_CE);
+        ctx->cells.erase(dhcen_ci->name);
+    }
+
     void route_buffered_net(NetInfo *net)
     {
         // a) route net after buf using the buf input as source
@@ -496,7 +571,8 @@ struct GowinGlobalRouter
         NetInfo *net_before_buf = buf_ci->getPort(id_I);
         NPNR_ASSERT(net_before_buf != nullptr);
 
-        RouteResult route_result = route_direct_net(net, src);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip) { return global_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED || route_result == ROUTED_PARTIALLY) {
             log_error("Can't route the %s net. It might be worth removing the BUFG buffer flag.\n", ctx->nameOf(net));
         }
@@ -516,7 +592,7 @@ struct GowinGlobalRouter
 
     void route_clk_net(NetInfo *net)
     {
-        RouteResult route_result = route_direct_net(net);
+        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); });
         if (route_result != NOT_ROUTED) {
             log_info("    '%s' net was routed  using global resources %s.\n", ctx->nameOf(net),
                      route_result == ROUTED_ALL ? "only" : "partially");
@@ -527,7 +603,7 @@ struct GowinGlobalRouter
     {
         log_info("Routing globals...\n");
 
-        std::vector<IdString> dqce_nets, dcs_nets, buf_nets, clk_nets;
+        std::vector<IdString> dhcen_nets, dqce_nets, dcs_nets, buf_nets, clk_nets;
 
         // Determining the priority of network routing
         for (auto &net : ctx->nets) {
@@ -550,12 +626,25 @@ struct GowinGlobalRouter
                     } else {
                         if (driver_is_dcs(ni->driver)) {
                             dcs_nets.push_back(net.first);
+                        } else {
+                            if (driver_is_dhcen(ni->driver)) {
+                                dhcen_nets.push_back(net.first);
+                            }
                         }
                     }
                 }
             }
         }
 
+        // nets with DHCEN
+        for (IdString net_name : dhcen_nets) {
+            NetInfo *ni = ctx->nets.at(net_name).get();
+            if (ctx->verbose) {
+                log_info("route dhcen net '%s'\n", ctx->nameOf(ni));
+            }
+            route_dhcen_net(ni);
+        }
+
         // nets with DQCE
         for (IdString net_name : dqce_nets) {
             NetInfo *ni = ctx->nets.at(net_name).get();
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 81c825f4da..deb70eecf9 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -116,12 +116,23 @@ NPNR_PACKED_STRUCT(struct Spine_bel_POD {
     int32_t bel_z;
 });
 
+NPNR_PACKED_STRUCT(struct Wire_bel_POD {
+    int32_t pip_xy;
+    int32_t pip_dst;
+    int32_t pip_src;
+    int32_t bel_x;
+    int32_t bel_y;
+    int32_t bel_z;
+    int32_t side;
+});
+
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     int32_t chip_flags;
     Bottom_io_POD bottom_io;
     RelSlice<IdString> diff_io_types;
     RelSlice<Spine_bel_POD> dqce_bels;
     RelSlice<Spine_bel_POD> dcs_bels;
+    RelSlice<Wire_bel_POD> dhcen_bels;
     // chip flags
     static constexpr int32_t HAS_SP32 = 1;
     static constexpr int32_t NEED_SP_FIX = 2;
@@ -162,10 +173,12 @@ enum
     VSS_Z = 278,
     BANDGAP_Z = 279,
 
-    DQCE_Z = 280, // : 286 reserve for 6 DQCEs
-    DCS_Z = 286,  // : 288 reserve for 2 DCSs
 
-    USERFLASH_Z = 288,
+    DQCE_Z = 280,  // : 286 reserve for 6 DQCEs
+    DCS_Z = 286,   // : 288 reserve for 2 DCSs
+    DHCEN_Z = 288, // : 298
+
+    USERFLASH_Z = 298,
 
     // The two least significant bits encode Z for 9-bit adders and
     // multipliers, if they are equal to 0, then we get Z of their common
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 425d9171b1..d8aa303eae 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -51,8 +51,10 @@
 
 DQCE_Z = 280 # : 286 reserve for 6 DQCEs
 DCS_Z  = 286 # : 288 reserve for 2 DCSs
+DHCEN_Z = 288 # : 298
+
+USERFLASH_Z = 298
 
-USERFLASH_Z = 288
 
 DSP_Z          = 509
 
@@ -167,6 +169,28 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.bel_y)
         bba.u32(self.bel_z)
 
+# wire -> bel for DHCEN bels
+@dataclass
+class WireBel(BBAStruct):
+    pip_xy: IdString
+    pip_dst: IdString
+    pip_src: IdString
+    bel_x: int
+    bel_y: int
+    bel_z: int
+    hclk_side: IdString
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.pip_xy.index)
+        bba.u32(self.pip_dst.index)
+        bba.u32(self.pip_src.index)
+        bba.u32(self.bel_x)
+        bba.u32(self.bel_y)
+        bba.u32(self.bel_z)
+        bba.u32(self.hclk_side.index)
+
 @dataclass
 class ChipExtraData(BBAStruct):
     strs: StringPool
@@ -175,6 +199,7 @@ class ChipExtraData(BBAStruct):
     diff_io_types: list[IdString] = field(default_factory = list)
     dqce_bels: list[SpineBel] = field(default_factory = list)
     dcs_bels: list[SpineBel] = field(default_factory = list)
+    dhcen_bels: list[WireBel] = field(default_factory = list)
 
     def create_bottom_io(self):
         self.bottom_io = BottomIO()
@@ -185,6 +210,9 @@ def add_bottom_io_cnd(self, net_a: str, net_b: str):
     def add_diff_io_type(self, diff_type: str):
         self.diff_io_types.append(self.strs.id(diff_type))
 
+    def add_dhcen_bel(self, pip_xy: str, pip_dst: str, pip_src, x: int, y: int, z: int, side: str):
+        self.dhcen_bels.append(WireBel(self.strs.id(pip_xy), self.strs.id(pip_dst), self.strs.id(pip_src), x, y, z, self.strs.id(side)))
+
     def add_dqce_bel(self, spine: str, x: int, y: int, z: int):
         self.dqce_bels.append(SpineBel(self.strs.id(spine), x, y, z))
 
@@ -202,6 +230,9 @@ def serialise_lists(self, context: str, bba: BBAWriter):
         bba.label(f"{context}_dcs_bels")
         for i, t in enumerate(self.dcs_bels):
             t.serialise(f"{context}_dcs_bel{i}", bba)
+        bba.label(f"{context}_dhcen_bels")
+        for i, t in enumerate(self.dhcen_bels):
+            t.serialise(f"{context}_dhcen_bel{i}", bba)
 
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.flags)
@@ -209,6 +240,7 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
         bba.slice(f"{context}_dqce_bels", len(self.dqce_bels))
         bba.slice(f"{context}_dcs_bels", len(self.dcs_bels))
+        bba.slice(f"{context}_dhcen_bels", len(self.dhcen_bels))
 
 @dataclass
 class PadExtraData(BBAStruct):
@@ -425,6 +457,9 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
 # map spine -> dcs bel
 dcs_bels = {}
 
+# map HCLKIN wire -> dhcen bel
+dhcen_bels = {}
+
 def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
     if (y, x) not in db.extra_func:
         return
@@ -453,6 +488,16 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                 tt.create_wire(wire)
             bel = tt.create_bel("BANDGAP", "BANDGAP", z = BANDGAP_Z)
             tt.add_bel_pin(bel, "BGEN", wire, PinType.INPUT)
+        elif func == 'dhcen':
+            for idx, dhcen in enumerate(desc):
+                wire = dhcen['ce']
+                if not tt.has_wire(wire):
+                    tt.create_wire(wire)
+                bel_z = DHCEN_Z + idx
+                bel = tt.create_bel(f"DHCEN{idx}", "DHCEN", z = bel_z)
+                tt.add_bel_pin(bel, "CE", wire, PinType.INPUT)
+                pip_xy, pip_dst, pip_src, side = dhcen['pip']
+                dhcen_bels[pip_xy, pip_dst, pip_src] = (x, y, bel_z, side)
         elif func == 'dqce':
             for idx in range(6):
                 bel_z = DQCE_Z + idx
@@ -1166,6 +1211,9 @@ def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
         chip.extra_data.add_bottom_io_cnd(net_a, net_b)
     for diff_type in db.diff_io_types:
         chip.extra_data.add_diff_io_type(diff_type)
+    # create hclk wire->dhcen bel map
+    for pip, bel in dhcen_bels.items():
+        chip.extra_data.add_dhcen_bel(pip[0], pip[1], pip[2], bel[0], bel[1], bel[2], bel[3])
     # create spine->dqce bel map
     for spine, bel in dqce_bels.items():
         chip.extra_data.add_dqce_bel(spine, bel[0], bel[1], bel[2])
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 0d6fb8b832..1e1c220822 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -87,6 +87,22 @@ BelId GowinUtils::get_dcs_bel(IdString spine_name)
     return BelId();
 }
 
+BelId GowinUtils::get_dhcen_bel(WireId hclkin_wire, IdString &side)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    for (auto &wire_bel : extra->dhcen_bels) {
+        IdString dst = IdString(wire_bel.pip_dst);
+        IdString src = IdString(wire_bel.pip_src);
+        IdStringList pip = IdStringList::concat(IdStringList::concat(IdString(wire_bel.pip_xy), dst), src);
+        WireId wire = ctx->getPipDstWire(ctx->getPipByName(pip));
+        if (wire == hclkin_wire) {
+            side = IdString(wire_bel.side);
+            return ctx->getBelByLocation(Loc(wire_bel.bel_x, wire_bel.bel_y, wire_bel.bel_z));
+        }
+    }
+    return BelId();
+}
+
 bool GowinUtils::is_simple_io_bel(BelId bel)
 {
     return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 77b750820c..f9276c10e9 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -35,6 +35,7 @@ struct GowinUtils
     BelId get_io_bel_from_iologic(BelId bel);
     BelId get_dqce_bel(IdString spine_name);
     BelId get_dcs_bel(IdString spine_name);
+    BelId get_dhcen_bel(WireId hclkin_wire, IdString &side);
 
     // BSRAM
     bool has_SP32(void);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index b7b64a4813..8d03b3a00a 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -3076,6 +3076,36 @@ struct GowinPacker
         }
     }
 
+    // =========================================
+    // Create DHCENs
+    // =========================================
+    void pack_dhcens()
+    {
+        // Allocate all available dhcen bels; we will find out which of them
+        // will actually be used during the routing process.
+        bool grab_bels = false;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (ci.type == id_DHCEN) {
+                ci.pseudo_cell = std::make_unique<RegionPlug>(Loc(0, 0, 0));
+                grab_bels = true;
+            }
+        }
+        if (grab_bels) {
+            // sane message if new primitives are used with old bases
+            auto buckets = ctx->getBelBuckets();
+            NPNR_ASSERT_MSG(std::find(buckets.begin(), buckets.end(), id_DHCEN) != buckets.end(), 
+                            "There are no DHCEN bels to use.");
+            int i = 0;
+            for (auto &bel : ctx->getBelsInBucket(ctx->getBelBucketForCellType(id_DHCEN))) {
+                IdString dhcen_name = ctx->idf("$PACKER_DHCEN_%d", ++i);
+                CellInfo *dhcen = ctx->createCell(dhcen_name, id_DHCEN);
+                dhcen->addInput(id_CE);
+                ctx->bindBel(bel, dhcen, STRENGTH_LOCKED);
+            }
+        }
+    }
+
     // =========================================
     // Enable UserFlash
     // =========================================
@@ -3218,6 +3248,9 @@ struct GowinPacker
         pack_buffered_nets();
         ctx->check();
 
+        pack_dhcens();
+        ctx->check();
+
         pack_userflash();
         ctx->check();
 

From 50bd8d09b07d8e62959ae299177310c2e7f9e4e9 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 12 Sep 2024 17:53:39 +1000
Subject: [PATCH 638/712] Gowin. Implement the EMCU primitive. (#1366)

* Gowin. Implement the EMCU primitive.

Add support for the GW1NSR-4C's embedded Cortex-M3 processor. Since it
uses flash in its own way, we disable additional flash processing for
this case.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix merge.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |   3 +
 himbaechel/uarch/gowin/gowin.h           |   7 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |  15 +++
 himbaechel/uarch/gowin/pack.cc           | 122 ++++++++++++++++++++++-
 4 files changed, 142 insertions(+), 5 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index e8e6874a6d..f15496b714 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1289,3 +1289,6 @@ X(RESETN)
 //HCLK Parameters
 X(DIV_MODE)
 X(GSREN)
+
+// EMCU
+X(EMCU)
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index deb70eecf9..1588b27b91 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -81,6 +81,10 @@ inline bool type_is_userflash(IdString cell_type)
 }
 inline bool is_userflash(const CellInfo *cell) { return type_is_userflash(cell->type); }
 
+// Return true if a cell is a EMCU
+inline bool type_is_emcu(IdString cell_type) { return cell_type == id_EMCU; }
+inline bool is_emcu(const CellInfo *cell) { return type_is_emcu(cell->type); }
+
 // ==========================================
 // extra data in the chip db
 // ==========================================
@@ -173,13 +177,14 @@ enum
     VSS_Z = 278,
     BANDGAP_Z = 279,
 
-
     DQCE_Z = 280,  // : 286 reserve for 6 DQCEs
     DCS_Z = 286,   // : 288 reserve for 2 DCSs
     DHCEN_Z = 288, // : 298
 
     USERFLASH_Z = 298,
 
+    EMCU_Z = 300,
+
     // The two least significant bits encode Z for 9-bit adders and
     // multipliers, if they are equal to 0, then we get Z of their common
     // 18-bit equivalent.
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index d8aa303eae..7daed96354 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -56,6 +56,8 @@
 USERFLASH_Z = 298
 
 
+EMCU_Z      = 300
+
 DSP_Z          = 509
 
 DSP_0_Z        = 511 # DSP macro 0
@@ -585,6 +587,19 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
                     if not tt.has_wire(wire):
                         tt.create_wire(wire, "FLASH_OUT")
                     tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
+        elif func == 'emcu':
+                bel = tt.create_bel("EMCU", "EMCU", EMCU_Z)
+                portmap = desc['ins']
+                for port, wire in portmap.items():
+                    print(port, wire)
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "EMCU_IN")
+                    tt.add_bel_pin(bel, port, wire, PinType.INPUT)
+                portmap = desc['outs']
+                for port, wire in portmap.items():
+                    if not tt.has_wire(wire):
+                        tt.create_wire(wire, "EMCU_OUT")
+                    tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
 
 def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     has_extra_func = (y, x) in db.extra_func
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 8d03b3a00a..78389d7fd7 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -3094,7 +3094,7 @@ struct GowinPacker
         if (grab_bels) {
             // sane message if new primitives are used with old bases
             auto buckets = ctx->getBelBuckets();
-            NPNR_ASSERT_MSG(std::find(buckets.begin(), buckets.end(), id_DHCEN) != buckets.end(), 
+            NPNR_ASSERT_MSG(std::find(buckets.begin(), buckets.end(), id_DHCEN) != buckets.end(),
                             "There are no DHCEN bels to use.");
             int i = 0;
             for (auto &bel : ctx->getBelsInBucket(ctx->getBelBucketForCellType(id_DHCEN))) {
@@ -3109,7 +3109,7 @@ struct GowinPacker
     // =========================================
     // Enable UserFlash
     // =========================================
-    void pack_userflash()
+    void pack_userflash(bool have_emcu)
     {
         log_info("Pack UserFlash cells...\n");
         std::vector<std::unique_ptr<CellInfo>> new_cells;
@@ -3152,6 +3152,11 @@ struct GowinPacker
                     ci.renamePort(ctx->idf("YADR[%d]", i), ctx->idf("YADR%d", i));
                 }
             }
+
+            if (have_emcu) {
+                continue;
+            }
+
             // add invertor
             int lut_idx = 0;
             auto add_inv = [&](IdString port, PortType port_type) {
@@ -3196,6 +3201,115 @@ struct GowinPacker
         }
     }
 
+    // =========================================
+    // Create EMCU
+    // =========================================
+    void pack_emcu_and_flash()
+    {
+        log_info("Pack EMCU and UserFlash cells...\n");
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        bool have_emcu = false;
+        for (auto &cell : ctx->cells) {
+            auto &ci = *cell.second;
+            if (!is_emcu(&ci)) {
+                continue;
+            }
+            have_emcu = true;
+
+            // rename ports
+            for (int i = 0; i < 2; ++i) {
+                ci.renamePort(ctx->idf("TARGFLASH0HTRANS[%d]", i), ctx->idf("TARGFLASH0HTRANS%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HTRANS[%d]", i), ctx->idf("TARGEXP0HTRANS%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0MEMATTR[%d]", i), ctx->idf("TARGEXP0MEMATTR%d", i));
+                // ins
+                ci.renamePort(ctx->idf("INITEXP0HTRANS[%d]", i), ctx->idf("INITEXP0HTRANS%d", i));
+                ci.renamePort(ctx->idf("INITEXP0MEMATTR[%d]", i), ctx->idf("INITEXP0MEMATTR%d", i));
+            }
+            for (int i = 0; i < 3; ++i) {
+                ci.renamePort(ctx->idf("TARGEXP0HSIZE[%d]", i), ctx->idf("TARGEXP0HSIZE%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HBURST[%d]", i), ctx->idf("TARGEXP0HBURST%d", i));
+                ci.renamePort(ctx->idf("APBTARGEXP2PPROT[%d]", i), ctx->idf("APBTARGEXP2PPROT%d", i));
+                // ins
+                ci.renamePort(ctx->idf("TARGEXP0HRUSER[%d]", i), ctx->idf("TARGEXP0HRUSER%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HSIZE[%d]", i), ctx->idf("INITEXP0HSIZE%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HBURST[%d]", i), ctx->idf("INITEXP0HBURST%d", i));
+            }
+            for (int i = 0; i < 4; ++i) {
+                ci.renamePort(ctx->idf("SRAM0WREN[%d]", i), ctx->idf("SRAM0WREN%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HPROT[%d]", i), ctx->idf("TARGEXP0HPROT%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HMASTER[%d]", i), ctx->idf("TARGEXP0HMASTER%d", i));
+                ci.renamePort(ctx->idf("APBTARGEXP2PSTRB[%d]", i), ctx->idf("APBTARGEXP2PSTRB%d", i));
+                ci.renamePort(ctx->idf("TPIUTRACEDATA[%d]", i), ctx->idf("TPIUTRACEDATA%d", i));
+                // ins
+                ci.renamePort(ctx->idf("INITEXP0HPROT[%d]", i), ctx->idf("INITEXP0HPROT%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HMASTER[%d]", i), ctx->idf("INITEXP0HMASTER%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HWUSER[%d]", i), ctx->idf("INITEXP0HWUSER%d", i));
+            }
+            for (int i = 0; i < 16; ++i) {
+                if (i < 13) {
+                    if (i < 12) {
+                        if (i < 5) {
+                            ci.renamePort(ctx->idf("GPINT[%d]", i), ctx->idf("GPINT%d", i));
+                        }
+                        ci.renamePort(ctx->idf("APBTARGEXP2PADDR[%d]", i), ctx->idf("APBTARGEXP2PADDR%d", i));
+                    }
+                    ci.renamePort(ctx->idf("SRAM0ADDR[%d]", i), ctx->idf("SRAM0ADDR%d", i));
+                }
+                ci.renamePort(ctx->idf("IOEXPOUTPUTO[%d]", i), ctx->idf("IOEXPOUTPUTO%d", i));
+                ci.renamePort(ctx->idf("IOEXPOUTPUTENO[%d]", i), ctx->idf("IOEXPOUTPUTENO%d", i));
+                // ins
+                ci.renamePort(ctx->idf("IOEXPINPUTI[%d]", i), ctx->idf("IOEXPINPUTI%d", i));
+            }
+            for (int i = 0; i < 32; ++i) {
+                if (i < 29) {
+                    ci.renamePort(ctx->idf("TARGFLASH0HADDR[%d]", i), ctx->idf("TARGFLASH0HADDR%d", i));
+                }
+                ci.renamePort(ctx->idf("SRAM0WDATA[%d]", i), ctx->idf("SRAM0WDATA%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HADDR[%d]", i), ctx->idf("TARGEXP0HADDR%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HWDATA[%d]", i), ctx->idf("TARGEXP0HWDATA%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HRDATA[%d]", i), ctx->idf("INITEXP0HRDATA%d", i));
+                ci.renamePort(ctx->idf("APBTARGEXP2PWDATA[%d]", i), ctx->idf("APBTARGEXP2PWDATA%d", i));
+                // ins
+                ci.renamePort(ctx->idf("SRAM0RDATA[%d]", i), ctx->idf("SRAM0RDATA%d", i));
+                ci.renamePort(ctx->idf("TARGEXP0HRDATA[%d]", i), ctx->idf("TARGEXP0HRDATA%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HADDR[%d]", i), ctx->idf("INITEXP0HADDR%d", i));
+                ci.renamePort(ctx->idf("INITEXP0HWDATA[%d]", i), ctx->idf("INITEXP0HWDATA%d", i));
+                ci.renamePort(ctx->idf("APBTARGEXP2PRDATA[%d]", i), ctx->idf("APBTARGEXP2PRDATA%d", i));
+            }
+            // The flash data bus is connected directly to the CPU so just disconnect these networks
+            // also other non-switched networks
+            ci.disconnectPort(ctx->id("DAPNTDOEN"));
+            ci.disconnectPort(ctx->id("DAPNTRST"));
+            ci.disconnectPort(ctx->id("DAPTDO"));
+            ci.disconnectPort(ctx->id("DAPTDI"));
+            ci.disconnectPort(ctx->id("TARGFLASH0HREADYMUX"));
+            ci.disconnectPort(ctx->id("TARGEXP0HAUSER"));
+            ci.disconnectPort(ctx->id("TARGFLASH0EXRESP"));
+            ci.disconnectPort(ctx->id("PORESETN"));
+            ci.disconnectPort(ctx->id("SYSRESETN"));
+            ci.disconnectPort(ctx->id("DAPSWDITMS"));
+            ci.disconnectPort(ctx->id("DAPSWCLKTCK"));
+            ci.disconnectPort(ctx->id("TPIUTRACECLK"));
+            for (int i = 0; i < 32; ++i) {
+                if (i < 4) {
+                    if (i < 3) {
+                        ci.disconnectPort(ctx->idf("TARGFLASH0HSIZE[%d]", i));
+                        ci.disconnectPort(ctx->idf("TARGFLASH0HBURST[%d]", i));
+                        ci.disconnectPort(ctx->idf("TARGFLASH0HRUSER[%d]", i));
+                        ci.disconnectPort(ctx->idf("INITEXP0HRUSER[%d]", i));
+                    }
+                    // ci.disconnectPort(ctx->idf("TARGFLASH0HPROT[%d]", i));
+                    ci.disconnectPort(ctx->idf("TARGEXP0HWUSER[%d]", i));
+                    ci.disconnectPort(ctx->idf("MTXREMAP[%d]", i));
+                }
+                // ins
+                ci.disconnectPort(ctx->idf("TARGFLASH0HRDATA[%d]", i));
+            }
+        }
+        pack_userflash(have_emcu);
+    }
+
     void run(void)
     {
         handle_constants();
@@ -3248,10 +3362,10 @@ struct GowinPacker
         pack_buffered_nets();
         ctx->check();
 
-        pack_dhcens();
+        pack_emcu_and_flash();
         ctx->check();
 
-        pack_userflash();
+        pack_dhcens();
         ctx->check();
 
         pack_dqce();

From 2627d4e0ad38ebc476af501ce8fff7f17f03d64f Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 12 Sep 2024 20:16:17 +0200
Subject: [PATCH 639/712] ecp5: Allow disabling of global promotion (#1367)

---
 ecp5/globals.cc | 5 +++--
 ecp5/main.cc    | 7 +++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 6c7ffba07d..921586f37c 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -48,7 +48,7 @@ static std::string get_quad_name(GlobalQuadrant quad)
 class Ecp5GlobalRouter
 {
   public:
-    Ecp5GlobalRouter(Context *ctx) : ctx(ctx){};
+    Ecp5GlobalRouter(Context *ctx) : ctx(ctx) {};
 
   private:
     bool is_clock_port(const PortRef &user)
@@ -512,11 +512,12 @@ class Ecp5GlobalRouter
   public:
     void promote_globals()
     {
+        bool disable_promotion = bool_or_default(ctx->settings, ctx->id("arch.no-promote-globals"));
         bool is_ooc = bool_or_default(ctx->settings, ctx->id("arch.ooc"));
         log_info("Promoting globals...\n");
         auto clocks = get_clocks();
         for (auto clock : clocks) {
-            bool is_noglobal = bool_or_default(clock->attrs, id_noglobal, false) ||
+            bool is_noglobal = disable_promotion || bool_or_default(clock->attrs, id_noglobal, false) ||
                                bool_or_default(clock->attrs, id_ECP5_IS_GLOBAL, false);
             if (is_noglobal)
                 continue;
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 6abea4a9f7..55754cd492 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -33,9 +33,9 @@ class ECP5CommandHandler : public CommandHandler
 {
   public:
     ECP5CommandHandler(int argc, char **argv);
-    virtual ~ECP5CommandHandler(){};
+    virtual ~ECP5CommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customAfterLoad(Context *ctx) override;
     void validate() override;
     void customBitstream(Context *ctx) override;
@@ -82,6 +82,7 @@ po::options_description ECP5CommandHandler::getArchOptions()
     specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
     specific.add_options()("lpf-allow-unconstrained", "don't require LPF file(s) to constrain all IO");
 
+    specific.add_options()("no-promote-globals", "disable all global promotion");
     specific.add_options()(
             "out-of-context",
             "disable IO buffer insertion and global promotion/routing, for building pre-routed blocks (experimental)");
@@ -253,6 +254,8 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext(dict<std::string, Pro
         ctx->settings[ctx->id(val.first)] = val.second;
     ctx->settings[ctx->id("arch.package")] = ctx->archArgs().package;
     ctx->settings[ctx->id("arch.speed")] = speedString(ctx->archArgs().speed);
+    if (vm.count("no-promote-globals"))
+        ctx->settings[ctx->id("arch.no-promote-globals")] = 1;
     if (vm.count("out-of-context"))
         ctx->settings[ctx->id("arch.ooc")] = 1;
     if (vm.count("disable-router-lutperm"))

From 6ca64526bb18ace8690872b09ca1251567c116de Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonas=20Th=C3=B6rnblad?= <jonas@tillitis.se>
Date: Tue, 17 Sep 2024 13:12:06 +0200
Subject: [PATCH 640/712] Fix handling of RNG seed

* Fix truncation of output seed value from 64 bits to 32 bits (int
  instead of uint64) when written to json file.

* Fix input seed value conversion when --seed option is used.

* Remove input seed value scrambling (use of rngseed()) when --seed
  or --randomize-seed option is used since the output seed value will
  be the scrambled value and not the seed that was actually supplied
  or generated.
---
 common/kernel/command.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 01c556b0e6..43eb491af2 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -343,7 +343,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("json", po::value<std::string>(), "JSON design file to ingest");
     general.add_options()("write", po::value<std::string>(), "JSON design file to write");
     general.add_options()("top", po::value<std::string>(), "name of top module");
-    general.add_options()("seed", po::value<int>(), "seed value for random number generator");
+    general.add_options()("seed", po::value<uint64_t>(), "seed value for random number generator");
     general.add_options()("randomize-seed,r", "randomize seed value for random number generator");
 
     general.add_options()(
@@ -447,7 +447,7 @@ void CommandHandler::setupContext(Context *ctx)
     }
 
     if (vm.count("seed")) {
-        ctx->rngseed(vm["seed"].as<int>());
+        ctx->rngstate = vm["seed"].as<uint64_t>();
     }
 
     if (vm.count("threads")) {
@@ -456,10 +456,10 @@ void CommandHandler::setupContext(Context *ctx)
 
     if (vm.count("randomize-seed")) {
         std::random_device randDev{};
-        std::uniform_int_distribution<int> distrib{1};
+        std::uniform_int_distribution<uint64_t> distrib{1};
         auto seed = distrib(randDev);
-        ctx->rngseed(seed);
-        log_info("Generated random seed: %d\n", seed);
+        ctx->rngstate = seed;
+        log_info("Generated random seed: %lu\n", seed);
     }
 
     if (vm.count("slack_redist_iter")) {
@@ -565,7 +565,7 @@ void CommandHandler::setupContext(Context *ctx)
 
     ctx->settings[ctx->id("arch.name")] = std::string(ctx->archId().c_str(ctx));
     ctx->settings[ctx->id("arch.type")] = std::string(ctx->archArgsToId(ctx->archArgs()).c_str(ctx));
-    ctx->settings[ctx->id("seed")] = ctx->rngstate;
+    ctx->settings[ctx->id("seed")] = Property(ctx->rngstate, 64);
 
     if (ctx->settings.find(ctx->id("placerHeap/alpha")) == ctx->settings.end())
         ctx->settings[ctx->id("placerHeap/alpha")] = std::to_string(0.1);

From 4b63b1115e01590e1ca5ac7a7f9c17811455387e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 20 Sep 2024 13:44:45 +0200
Subject: [PATCH 641/712] Bump tests submodule

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests b/tests
index 00c55a9eb9..d2d5b69dd3 160000
--- a/tests
+++ b/tests
@@ -1 +1 @@
-Subproject commit 00c55a9eb9ea2e062b51fe0d64741412b185d95d
+Subproject commit d2d5b69dd34b1a9a1e4e9466599ed18e9254fee9

From 2d542eb63a9283b4dceb05240b971cb8093c5517 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Fri, 6 Sep 2024 23:02:37 +0200
Subject: [PATCH 642/712] timing: Add hold time to bound of critical path
 report

---
 common/kernel/nextpnr_types.h | 26 ++++++++++++++++++++++++++
 common/kernel/timing.cc       | 21 +++++++++++++++++++--
 2 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index ec1ac11101..dd8eeecbc4 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -203,6 +203,32 @@ enum TimingPortClass
     TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
 };
 
+std::string tmgPortClass_to_str(TimingPortClass tmg_class)
+{
+    switch (tmg_class) {
+    case TMG_CLOCK_INPUT:
+        return "TMG_CLOCK_INPUT";
+    case TMG_GEN_CLOCK:
+        return "TMG_GEN_CLOCK";
+    case TMG_REGISTER_INPUT:
+        return "TMG_REGISTER_INPUT";
+    case TMG_REGISTER_OUTPUT:
+        return "TMG_REGISTER_OUTPUT";
+    case TMG_COMB_INPUT:
+        return "TMG_COMB_INPUT";
+    case TMG_COMB_OUTPUT:
+        return "TMG_COMB_OUTPUT";
+    case TMG_STARTPOINT:
+        return "TMG_STARTPOINT";
+    case TMG_ENDPOINT:
+        return "TMG_ENDPOINT";
+    case TMG_IGNORE:
+        return "TMG_IGNORE";
+    default:
+        return "TMG_BOOM";
+    }
+}
+
 enum ClockEdge
 {
     RISING_EDGE,
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 105d20f906..30faaf4685 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -826,16 +826,31 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     }
 
+    // Set hold time
+    auto cell = cell_info(endpoint);
+    auto &port = port_info(endpoint);
+    int port_clocks;
+    auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
+    if (portClass == TMG_REGISTER_INPUT) {
+        for (int i = 0; i < port_clocks; i++) {
+            auto info = ctx->getPortClockingInfo(cell, port.name, i);
+            if (!cell->ports.count(info.clock_port) || cell->ports.at(info.clock_port).net == nullptr)
+                continue;
+
+            report.bound.min_delay = info.hold.min_delay;
+            break;
+        }
+    }
+
     pool<std::pair<IdString, IdString>> visited;
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
     while (cursor != CellPortKey()) {
-        auto cell = cell_info(cursor);
-        auto &port = port_info(cursor);
 
         int port_clocks;
         auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
+        printf("%s.%s %s\n", cell->name.c_str(ctx), port.name.c_str(ctx), tmgPortClass_to_str(portClass));
 
         // combinational loop
         if (!visited.insert(std::make_pair(cell->name, port.name)).second)
@@ -848,6 +863,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
             break;
 
         cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
+        auto cell = cell_info(cursor);
+        auto &port = port_info(cursor);
     }
 
     auto crit_path = boost::adaptors::reverse(crit_path_rev);

From 44665a9c4d929a89d86038cc6dbc225f5f6be915 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Fri, 6 Sep 2024 23:23:04 +0200
Subject: [PATCH 643/712] timing: Allow critical path traversal for shortest
 paths

---
 common/kernel/nextpnr_types.h |  2 +-
 common/kernel/timing.cc       | 25 +++++++++++++++----------
 common/kernel/timing.h        |  4 +++-
 3 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index dd8eeecbc4..0da08865d1 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -203,7 +203,7 @@ enum TimingPortClass
     TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
 };
 
-std::string tmgPortClass_to_str(TimingPortClass tmg_class)
+static std::string tmgPortClass_to_str(TimingPortClass tmg_class)
 {
     switch (tmg_class) {
     case TMG_CLOCK_INPUT:
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 30faaf4685..17422cc010 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -796,7 +796,8 @@ std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair,
     return worst_eps;
 }
 
-CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
+CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint,
+                                                        bool longest_path)
 {
     CriticalPath report;
 
@@ -846,11 +847,18 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
-    while (cursor != CellPortKey()) {
+    auto next_cursor = [longest_path](ArrivReqTime &arrival) {
+        if (longest_path) {
+            return arrival.bwd_max;
+        }
+        return arrival.bwd_min;
+    };
 
+    while (cursor != CellPortKey()) {
+        auto cell = cell_info(cursor);
+        auto &port = port_info(cursor);
         int port_clocks;
         auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
-        printf("%s.%s %s\n", cell->name.c_str(ctx), port.name.c_str(ctx), tmgPortClass_to_str(portClass));
 
         // combinational loop
         if (!visited.insert(std::make_pair(cell->name, port.name)).second)
@@ -862,9 +870,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
 
-        cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
-        auto cell = cell_info(cursor);
-        auto &port = port_info(cursor);
+        cursor = next_cursor(ports.at(cursor).arrival.at(dp.key.launch));
     }
 
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
@@ -873,8 +879,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto &front_port = front.cell->ports.at(front.port);
     auto &front_driver = front_port.net->driver;
 
-    int port_clocks;
-    auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
+    portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
 
     const CellInfo *last_cell = front.cell;
     IdString last_port = front_driver.port;
@@ -997,7 +1002,7 @@ void TimingAnalyser::build_crit_path_reports()
             clock_fmax[launch.clock].achieved = Fmax;
             clock_fmax[launch.clock].constraint = target;
 
-            clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint.at(0));
+            clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint.at(0), true);
 
             empty_clocks.erase(launch.clock);
         }
@@ -1015,7 +1020,7 @@ void TimingAnalyser::build_crit_path_reports()
         if (worst_endpoint.empty())
             continue;
 
-        xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint.at(0)));
+        xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint.at(0), true));
     }
 
     auto cmp_crit_path = [&](const CriticalPath &ra, const CriticalPath &rb) {
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index dae3ba27e1..6ddd25c75f 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -119,7 +119,9 @@ struct TimingAnalyser
     void compute_criticality();
 
     void build_detailed_net_timing_report();
-    CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
+    // longest_path indicate whether to follow the longest or shortest path from endpoint to startpoint
+    // longest paths are interesting for setup violations and shortest paths are interesting for hold violations
+    CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint, bool longest_path);
     void build_crit_path_reports();
     void build_slack_histogram_report();
 

From c25da06d0351b6b07e356b6cae1aa57fde564408 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Wed, 11 Sep 2024 17:55:08 +0200
Subject: [PATCH 644/712] timing: Start identification of min_delay violations

---
 common/kernel/timing.cc | 115 ++++++++++++++++++++++++++++++++++++++--
 common/kernel/timing.h  |   2 +
 2 files changed, 112 insertions(+), 5 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 17422cc010..6d53594ad9 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -75,6 +75,7 @@ void TimingAnalyser::run(bool update_route_delays, bool update_net_timings, bool
     }
 
     if (update_crit_paths) {
+        get_min_delay_violations();
         build_crit_path_reports();
     }
 }
@@ -119,7 +120,9 @@ void TimingAnalyser::get_cell_delays()
                         continue;
                     pd.cell_arcs.emplace_back(CellArc::SETUP, info.clock_port, DelayQuad(info.setup, info.setup),
                                               info.edge);
-                    pd.cell_arcs.emplace_back(CellArc::HOLD, info.clock_port, DelayQuad(info.hold, info.hold),
+                    auto hold_factor = 1;
+                    auto hold_faked = DelayPair(hold_factor * info.hold.min_delay, hold_factor * info.hold.max_delay);
+                    pd.cell_arcs.emplace_back(CellArc::HOLD, info.clock_port, DelayQuad(hold_faked, hold_faked),
                                               info.edge);
                 }
             }
@@ -572,6 +575,8 @@ void TimingAnalyser::walk_forward()
                 for (auto &fanin : pd.cell_arcs) {
                     if (fanin.type == CellArc::CLK_TO_Q && fanin.other_port == sp.second) {
                         init_arrival = init_arrival + fanin.value.delayPair();
+                        // printf("walk_forward %s.%s: init_arrival to %d - %d\n", sp.first.cell.c_str(ctx),
+                        //        sp.first.port.c_str(ctx), init_arrival.min_delay, init_arrival.max_delay);
                         break;
                     }
                 }
@@ -591,16 +596,26 @@ void TimingAnalyser::walk_forward()
                     for (auto &usr : net->users) {
                         CellPortKey usr_key(usr);
                         auto &usr_pd = ports.at(usr_key);
-                        set_arrival_time(usr_key, arr.first, arr.second.value + usr_pd.route_delay,
-                                         arr.second.path_length, p);
+                        auto next_arr = arr.second.value + usr_pd.route_delay;
+                        printf("walk_forward: propagate routing from %s.%s to %s.%s, %d - %d\n", p.cell.c_str(ctx),
+                               p.port.c_str(ctx), usr_key.cell.c_str(ctx), usr_key.port.c_str(ctx), next_arr.min_delay,
+                               next_arr.max_delay);
+
+                        set_arrival_time(usr_key, arr.first, next_arr, arr.second.path_length, p);
                     }
             } else if (pd.type == PORT_IN) {
                 // Input port; propagate delay through cell, adding combinational delay
                 for (auto &fanout : pd.cell_arcs) {
                     if (fanout.type != CellArc::COMBINATIONAL)
                         continue;
-                    set_arrival_time(CellPortKey(p.cell, fanout.other_port), arr.first,
-                                     arr.second.value + fanout.value.delayPair(), arr.second.path_length + 1, p);
+
+                    auto next_arr = arr.second.value + fanout.value.delayPair();
+
+                    printf("walk_forward: propagate through cell from %s.%s to %s.%s, %d - %d\n", p.cell.c_str(ctx),
+                           p.port.c_str(ctx), p.cell.c_str(ctx), fanout.other_port.c_str(ctx), next_arr.min_delay,
+                           next_arr.max_delay);
+                    set_arrival_time(CellPortKey(p.cell, fanout.other_port), arr.first, next_arr,
+                                     arr.second.path_length + 1, p);
                 }
             }
         }
@@ -715,6 +730,13 @@ void TimingAnalyser::compute_slack()
                 pd.worst_hold_slack = std::min(pd.worst_hold_slack, pdp.second.hold_slack);
                 dp.worst_hold_slack = std::min(dp.worst_hold_slack, pdp.second.hold_slack);
             }
+            // printf("max arr: %d, min req: %d, c2c: %d, setup slack: %d\n", arr.value.maxDelay(),
+            // req.value.minDelay(),
+            //        clock_to_clock, pdp.second.setup_slack);
+            // if (!setup_only) {
+            //     printf("min arr: %d, max req: %d, c2c: %d, hold slack: %d\n", arr.value.minDelay(),
+            //            req.value.maxDelay(), clock_to_clock, pdp.second.hold_slack);
+            // }
         }
     }
 }
@@ -1083,6 +1105,89 @@ void TimingAnalyser::build_slack_histogram_report()
     }
 }
 
+std::string arc_typ_to_str(TimingAnalyser::CellArc::ArcType typ)
+{
+    switch (typ) {
+    case TimingAnalyser::CellArc::COMBINATIONAL:
+        return "COMBINATIONAL";
+    case TimingAnalyser::CellArc::SETUP:
+        return "SETUP";
+    case TimingAnalyser::CellArc::HOLD:
+        return "HOLD";
+    case TimingAnalyser::CellArc::CLK_TO_Q:
+        return "CLK_TO_Q";
+    case TimingAnalyser::CellArc::STARTPOINT:
+        return "STARTPOINT";
+    case TimingAnalyser::CellArc::ENDPOINT:
+        return "ENDPOINT";
+    default:
+        return "IMPOSSIBRU";
+    }
+}
+
+std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
+{
+    std::vector<CriticalPath> violations;
+
+    for (domain_id_t capture_id = 0; capture_id < domain_id_t(domains.size()); ++capture_id) {
+        const auto &capture = domains.at(capture_id);
+        const auto &capture_clock = capture.key.clock;
+
+        if (ctx->nets.count(capture_clock) == 0) {
+            continue;
+        }
+
+        NetInfo *clk_net = ctx->nets.at(capture_clock).get();
+        if (clk_net->clkconstr == nullptr) {
+            continue;
+        }
+
+        DelayPair period = clk_net->clkconstr->period;
+
+        printf("Clock %s.%s with period %f - %f\n", clk_net->driver.cell->name.c_str(ctx),
+               clk_net->driver.port.c_str(ctx), ctx->getDelayNS(period.minDelay()), ctx->getDelayNS(period.maxDelay()));
+
+        for (auto &sp : capture.endpoints) {
+            CellInfo *ci = cell_info(sp.first);
+            int clkInfoCount = 0;
+            TimingPortClass cls = ctx->getPortTimingClass(ci, sp.first.port, clkInfoCount);
+            if (cls != TMG_REGISTER_INPUT)
+                continue;
+
+            auto &port = ports.at(sp.first);
+
+            auto &req = port.required.at(capture_id);
+
+            for (auto &[launch_id, arr] : port.arrival) {
+                const auto &launch = domains.at(launch_id);
+                const auto &launch_clock = launch.key.clock;
+
+                auto clocks = std::make_pair(launch_clock, capture_clock);
+                auto related_clocks = clock_delays.count(clocks) != 0;
+
+                // Don't consider clocks without known relationships
+                if (launch_id != capture_id && !related_clocks) {
+                    continue;
+                }
+
+                delay_t clock_to_clock = 0;
+                if (related_clocks) {
+                    clock_to_clock = clock_delays.at(clocks);
+                }
+
+                auto hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
+
+                printf("endpoint: %s.%s, arr: %f - %f, req: %f - %f, hold slack: %f\n", sp.first.cell.c_str(ctx),
+                       sp.first.port.c_str(ctx), ctx->getDelayNS(arr.value.minDelay()),
+                       ctx->getDelayNS(arr.value.maxDelay()), ctx->getDelayNS(req.value.minDelay()),
+                       ctx->getDelayNS(req.value.maxDelay()), ctx->getDelayNS(hold_slack));
+            }
+        }
+    }
+
+    return violations;
+}
+
 domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
 {
     return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 6ddd25c75f..80b3079c7d 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -125,6 +125,8 @@ struct TimingAnalyser
     void build_crit_path_reports();
     void build_slack_histogram_report();
 
+    std::vector<CriticalPath> get_min_delay_violations();
+
     dict<domain_id_t, delay_t> max_delay_by_domain_pairs();
 
     // get the N worst endpoints for a given domain pair

From 7aeed52c065873d924711a0f6599a0ec8e49226d Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Wed, 11 Sep 2024 18:35:47 +0200
Subject: [PATCH 645/712] common: Add some convenience functions for
 development

---
 common/kernel/log.cc          |  4 +--
 common/kernel/nextpnr_types.h | 53 ++++++++++++++++++++++++++++++++---
 2 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/common/kernel/log.cc b/common/kernel/log.cc
index a0bdd64eb1..7bb7f6d748 100644
--- a/common/kernel/log.cc
+++ b/common/kernel/log.cc
@@ -135,7 +135,7 @@ void logv_nonfatal_error(const char *format, va_list ap)
     had_nonfatal_error = true;
 }
 
-void logv_error(const char *format, va_list ap)
+[[noreturn]] void logv_error(const char *format, va_list ap)
 {
     logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
 
@@ -180,7 +180,7 @@ void log_warning(const char *format, ...)
     va_end(ap);
 }
 
-void log_error(const char *format, ...)
+[[noreturn]] void log_error(const char *format, ...)
 {
     va_list ap;
     va_start(ap, format);
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 0da08865d1..23b319b9ed 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -30,6 +30,7 @@
 #include "archdefs.h"
 #include "hashlib.h"
 #include "indexed_store.h"
+#include "log.h"
 #include "nextpnr_base_types.h"
 #include "nextpnr_namespaces.h"
 #include "property.h"
@@ -180,6 +181,20 @@ enum PortType
     PORT_INOUT = 2
 };
 
+[[maybe_unused]] static const std::string portType_to_str(PortType typ)
+{
+    switch (typ) {
+    case PORT_IN:
+        return "PORT_IN";
+    case PORT_OUT:
+        return "PORT_OUT";
+    case PORT_INOUT:
+        return "PORT_INOUT";
+    default:
+        log_error("Impossible PortType");
+    }
+}
+
 struct PortInfo
 {
     IdString name;
@@ -203,7 +218,7 @@ enum TimingPortClass
     TMG_IGNORE,          // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
 };
 
-static std::string tmgPortClass_to_str(TimingPortClass tmg_class)
+[[maybe_unused]] static const std::string timingPortClass_to_str(TimingPortClass tmg_class)
 {
     switch (tmg_class) {
     case TMG_CLOCK_INPUT:
@@ -225,7 +240,7 @@ static std::string tmgPortClass_to_str(TimingPortClass tmg_class)
     case TMG_IGNORE:
         return "TMG_IGNORE";
     default:
-        return "TMG_BOOM";
+        log_error("Impossible TimingPortClass");
     }
 }
 
@@ -235,6 +250,18 @@ enum ClockEdge
     FALLING_EDGE
 };
 
+[[maybe_unused]] static const std::string clockEdge_to_str(ClockEdge edge)
+{
+    switch (edge) {
+    case RISING_EDGE:
+        return "RISING_EDGE";
+    case FALLING_EDGE:
+        return "FALLING_EDGE";
+    default:
+        log_error("Impossible ClockEdge");
+    }
+}
+
 struct TimingClockingInfo
 {
     IdString clock_port; // Port name of clock domain
@@ -378,6 +405,24 @@ struct CriticalPath
             SETUP     // Setup time in sink
         };
 
+        [[maybe_unused]] static const std::string type_to_str(Type typ)
+        {
+            switch (typ) {
+            case Type::CLK_TO_Q:
+                return "CLK_TO_Q";
+            case Type::SOURCE:
+                return "SOURCE";
+            case Type::LOGIC:
+                return "LOGIC";
+            case Type::ROUTING:
+                return "ROUTING";
+            case Type::SETUP:
+                return "SETUP";
+            default:
+                log_error("Impossible Segment::Type");
+            }
+        }
+
         // Type
         Type type;
         // Net name (routing only)
@@ -434,8 +479,8 @@ struct TimingResult
     // Histogram of slack
     dict<int, unsigned> slack_histogram;
 
-    // TODO: Hold time violations
-    // dict<IdString, CriticalPath> hold_violations;
+    // Min delay violations, only hold time for now
+    std::vector<CriticalPath> min_delay_violations;
 };
 
 // Represents the contents of a non-leaf cell in a design

From 82ea65d984e3c8fd51931d7c7a0e701c3dd19398 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Wed, 11 Sep 2024 18:36:23 +0200
Subject: [PATCH 646/712] timing: Report min delay violated in timing logger

---
 common/kernel/timing.cc     | 97 +++++++++++++++----------------------
 common/kernel/timing.h      |  2 +
 common/kernel/timing_log.cc | 15 +++++-
 3 files changed, 55 insertions(+), 59 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 6d53594ad9..bf3420bc37 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -25,7 +25,6 @@
 #include <deque>
 #include <map>
 #include <utility>
-#include "log.h"
 #include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -75,7 +74,6 @@ void TimingAnalyser::run(bool update_route_delays, bool update_net_timings, bool
     }
 
     if (update_crit_paths) {
-        get_min_delay_violations();
         build_crit_path_reports();
     }
 }
@@ -575,8 +573,6 @@ void TimingAnalyser::walk_forward()
                 for (auto &fanin : pd.cell_arcs) {
                     if (fanin.type == CellArc::CLK_TO_Q && fanin.other_port == sp.second) {
                         init_arrival = init_arrival + fanin.value.delayPair();
-                        // printf("walk_forward %s.%s: init_arrival to %d - %d\n", sp.first.cell.c_str(ctx),
-                        //        sp.first.port.c_str(ctx), init_arrival.min_delay, init_arrival.max_delay);
                         break;
                     }
                 }
@@ -597,10 +593,6 @@ void TimingAnalyser::walk_forward()
                         CellPortKey usr_key(usr);
                         auto &usr_pd = ports.at(usr_key);
                         auto next_arr = arr.second.value + usr_pd.route_delay;
-                        printf("walk_forward: propagate routing from %s.%s to %s.%s, %d - %d\n", p.cell.c_str(ctx),
-                               p.port.c_str(ctx), usr_key.cell.c_str(ctx), usr_key.port.c_str(ctx), next_arr.min_delay,
-                               next_arr.max_delay);
-
                         set_arrival_time(usr_key, arr.first, next_arr, arr.second.path_length, p);
                     }
             } else if (pd.type == PORT_IN) {
@@ -610,10 +602,6 @@ void TimingAnalyser::walk_forward()
                         continue;
 
                     auto next_arr = arr.second.value + fanout.value.delayPair();
-
-                    printf("walk_forward: propagate through cell from %s.%s to %s.%s, %d - %d\n", p.cell.c_str(ctx),
-                           p.port.c_str(ctx), p.cell.c_str(ctx), fanout.other_port.c_str(ctx), next_arr.min_delay,
-                           next_arr.max_delay);
                     set_arrival_time(CellPortKey(p.cell, fanout.other_port), arr.first, next_arr,
                                      arr.second.path_length + 1, p);
                 }
@@ -730,13 +718,6 @@ void TimingAnalyser::compute_slack()
                 pd.worst_hold_slack = std::min(pd.worst_hold_slack, pdp.second.hold_slack);
                 dp.worst_hold_slack = std::min(dp.worst_hold_slack, pdp.second.hold_slack);
             }
-            // printf("max arr: %d, min req: %d, c2c: %d, setup slack: %d\n", arr.value.maxDelay(),
-            // req.value.minDelay(),
-            //        clock_to_clock, pdp.second.setup_slack);
-            // if (!setup_only) {
-            //     printf("min arr: %d, max req: %d, c2c: %d, hold slack: %d\n", arr.value.minDelay(),
-            //            req.value.maxDelay(), clock_to_clock, pdp.second.hold_slack);
-            // }
         }
     }
 }
@@ -869,13 +850,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
-    auto next_cursor = [longest_path](ArrivReqTime &arrival) {
-        if (longest_path) {
-            return arrival.bwd_max;
-        }
-        return arrival.bwd_min;
-    };
-
     while (cursor != CellPortKey()) {
         auto cell = cell_info(cursor);
         auto &port = port_info(cursor);
@@ -892,7 +866,11 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (!ports.at(cursor).arrival.count(dp.key.launch))
             break;
 
-        cursor = next_cursor(ports.at(cursor).arrival.at(dp.key.launch));
+        if (longest_path) {
+            cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_max;
+        } else {
+            cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_min;
+        }
     }
 
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
@@ -989,6 +967,10 @@ void TimingAnalyser::build_crit_path_reports()
     auto &empty_clocks = result.empty_paths;
     auto &clock_delays_ctx = result.clock_delays;
 
+    if (!setup_only) {
+        result.min_delay_violations = get_min_delay_violations();
+    }
+
     auto delay_by_domain = max_delay_by_domain_pairs();
 
     for (int i = 0; i < int(domains.size()); i++) {
@@ -1105,26 +1087,6 @@ void TimingAnalyser::build_slack_histogram_report()
     }
 }
 
-std::string arc_typ_to_str(TimingAnalyser::CellArc::ArcType typ)
-{
-    switch (typ) {
-    case TimingAnalyser::CellArc::COMBINATIONAL:
-        return "COMBINATIONAL";
-    case TimingAnalyser::CellArc::SETUP:
-        return "SETUP";
-    case TimingAnalyser::CellArc::HOLD:
-        return "HOLD";
-    case TimingAnalyser::CellArc::CLK_TO_Q:
-        return "CLK_TO_Q";
-    case TimingAnalyser::CellArc::STARTPOINT:
-        return "STARTPOINT";
-    case TimingAnalyser::CellArc::ENDPOINT:
-        return "ENDPOINT";
-    default:
-        return "IMPOSSIBRU";
-    }
-}
-
 std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
 {
     std::vector<CriticalPath> violations;
@@ -1144,17 +1106,14 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
 
         DelayPair period = clk_net->clkconstr->period;
 
-        printf("Clock %s.%s with period %f - %f\n", clk_net->driver.cell->name.c_str(ctx),
-               clk_net->driver.port.c_str(ctx), ctx->getDelayNS(period.minDelay()), ctx->getDelayNS(period.maxDelay()));
-
-        for (auto &sp : capture.endpoints) {
-            CellInfo *ci = cell_info(sp.first);
+        for (auto &ep : capture.endpoints) {
+            CellInfo *ci = cell_info(ep.first);
             int clkInfoCount = 0;
-            TimingPortClass cls = ctx->getPortTimingClass(ci, sp.first.port, clkInfoCount);
+            TimingPortClass cls = ctx->getPortTimingClass(ci, ep.first.port, clkInfoCount);
             if (cls != TMG_REGISTER_INPUT)
                 continue;
 
-            auto &port = ports.at(sp.first);
+            auto &port = ports.at(ep.first);
 
             auto &req = port.required.at(capture_id);
 
@@ -1177,10 +1136,12 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
 
                 auto hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
 
-                printf("endpoint: %s.%s, arr: %f - %f, req: %f - %f, hold slack: %f\n", sp.first.cell.c_str(ctx),
-                       sp.first.port.c_str(ctx), ctx->getDelayNS(arr.value.minDelay()),
-                       ctx->getDelayNS(arr.value.maxDelay()), ctx->getDelayNS(req.value.minDelay()),
-                       ctx->getDelayNS(req.value.maxDelay()), ctx->getDelayNS(hold_slack));
+                auto violated = true;
+
+                if (violated) {
+                    const auto dom_pair_id = domain_pair_id(launch_id, capture_id);
+                    violations.emplace_back(build_critical_path_report(dom_pair_id, ep.first, false));
+                }
             }
         }
     }
@@ -1222,6 +1183,26 @@ void TimingAnalyser::copy_domains(const CellPortKey &from, const CellPortKey &to
     }
 }
 
+const std::string TimingAnalyser::arcType_to_str(CellArc::ArcType typ)
+{
+    switch (typ) {
+    case TimingAnalyser::CellArc::COMBINATIONAL:
+        return "COMBINATIONAL";
+    case TimingAnalyser::CellArc::SETUP:
+        return "SETUP";
+    case TimingAnalyser::CellArc::HOLD:
+        return "HOLD";
+    case TimingAnalyser::CellArc::CLK_TO_Q:
+        return "CLK_TO_Q";
+    case TimingAnalyser::CellArc::STARTPOINT:
+        return "STARTPOINT";
+    case TimingAnalyser::CellArc::ENDPOINT:
+        return "ENDPOINT";
+    default:
+        log_error("Impossible CellArc::ArcType\n");
+    }
+}
+
 CellInfo *TimingAnalyser::cell_info(const CellPortKey &key) { return ctx->cells.at(key.cell).get(); }
 
 PortInfo &TimingAnalyser::port_info(const CellPortKey &key) { return ctx->cells.at(key.cell)->ports.at(key.port); }
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 80b3079c7d..ac78be4b79 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -225,6 +225,8 @@ struct TimingAnalyser
 
     void copy_domains(const CellPortKey &from, const CellPortKey &to, bool backwards);
 
+    [[maybe_unused]] static const std::string arcType_to_str(CellArc::ArcType typ);
+
     dict<CellPortKey, PerPort> ports;
     dict<ClockDomainKey, domain_id_t> domain_to_id;
     dict<ClockDomainPairKey, domain_id_t> pair_to_id;
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 24aac66589..339c0b8622 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -168,7 +168,20 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
         log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
         print_path_report(report);
     }
-};
+
+    // Min delay violated paths
+    for (auto &report : result.min_delay_violations) {
+        log_break();
+        std::string start = clock_event_name(ctx, report.clock_pair.start);
+        std::string end = clock_event_name(ctx, report.clock_pair.end);
+        if (report.clock_pair.start == report.clock_pair.end) {
+            log_info("Hold time violations for clock '%s':\n", start.c_str());
+        } else {
+            log_info("Hold time violations for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+        }
+        print_path_report(report);
+    }
+}
 
 static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
 {

From 60ee682d5822b59425627868e3130379fdc8746c Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 12 Sep 2024 14:53:37 +0200
Subject: [PATCH 647/712] timing: Make hold violations an error

---
 common/kernel/timing_log.cc | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 339c0b8622..349f2ba8aa 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -19,6 +19,7 @@
  *
  */
 
+#include <algorithm>
 #include "log.h"
 #include "nextpnr.h"
 #include "util.h"
@@ -170,16 +171,23 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
     }
 
     // Min delay violated paths
-    for (auto &report : result.min_delay_violations) {
+    // Show maximum of 10
+    auto num_min_violations = result.min_delay_violations.size();
+    if (num_min_violations > 0) {
         log_break();
-        std::string start = clock_event_name(ctx, report.clock_pair.start);
-        std::string end = clock_event_name(ctx, report.clock_pair.end);
-        if (report.clock_pair.start == report.clock_pair.end) {
-            log_info("Hold time violations for clock '%s':\n", start.c_str());
-        } else {
-            log_info("Hold time violations for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+        log_info("Hold time violations:\n");
+        for (size_t i = 0; i < std::min((size_t)10, num_min_violations); ++i) {
+            auto &report = result.min_delay_violations.at(i);
+            log_break();
+            std::string start = clock_event_name(ctx, report.clock_pair.start);
+            std::string end = clock_event_name(ctx, report.clock_pair.end);
+            if (report.clock_pair.start == report.clock_pair.end) {
+                log_nonfatal_error("Hold time violations for clock '%s':\n", start.c_str());
+            } else {
+                log_nonfatal_error("Hold time violations for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+            }
+            print_path_report(report);
         }
-        print_path_report(report);
     }
 }
 

From fc3b2de8da560182a7fb16e6f35363322f00f2a6 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 12 Sep 2024 19:49:35 +0200
Subject: [PATCH 648/712] timing: Add clock skew to arrival and required time

---
 common/kernel/context.cc | 10 +++++-----
 common/kernel/timing.cc  | 37 ++++++++++++++++++++++++++++++-------
 common/kernel/timing.h   |  4 ++++
 3 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index b194675d4e..0e99c1b6f0 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -116,10 +116,10 @@ delay_t Context::predictArcDelay(const NetInfo *net_info, const PortRef &sink) c
 
 delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
 {
-#ifdef ARCH_ECP5
-    if (net_info->is_global)
-        return 0;
-#endif
+    // #ifdef ARCH_ECP5
+    //     if (net_info->is_global)
+    //         return 0;
+    // #endif
 
     if (net_info->wires.empty())
         return predictArcDelay(net_info, user_info);
@@ -417,7 +417,7 @@ void Context::check() const
 namespace {
 struct FixupHierarchyWorker
 {
-    FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
+    FixupHierarchyWorker(Context *ctx) : ctx(ctx) {};
     Context *ctx;
     void run()
     {
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index bf3420bc37..20b95d3c5e 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -174,10 +174,20 @@ void TimingAnalyser::get_route_delays()
         NetInfo *ni = net.second.get();
         if (ni->driver.cell == nullptr || ni->driver.cell->bel == BelId())
             continue;
+
+        if (clock_skew) {
+            printf("net %s has driver %s.%s\n", ni->name.c_str(ctx), ni->driver.cell->name.c_str(ctx),
+                   ni->driver.port.c_str(ctx));
+        }
         for (auto &usr : ni->users) {
             if (usr.cell->bel == BelId())
                 continue;
             ports.at(CellPortKey(usr)).route_delay = DelayPair(ctx->getNetinfoRouteDelay(ni, usr));
+
+            if (clock_skew) {
+                printf("\tuser %s.%s, delay: %f\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
+                       ctx->getDelayNS(ctx->getNetinfoRouteDelay(ni, usr)));
+            }
         }
     }
 }
@@ -567,12 +577,15 @@ void TimingAnalyser::walk_forward()
             auto &pd = ports.at(sp.first);
             DelayPair init_arrival(0);
             CellPortKey clock_key;
-            // TODO: clock routing delay, if analysis of that is enabled
             if (sp.second != IdString()) {
                 // clocked startpoints have a clock-to-out time
                 for (auto &fanin : pd.cell_arcs) {
                     if (fanin.type == CellArc::CLK_TO_Q && fanin.other_port == sp.second) {
-                        init_arrival = init_arrival + fanin.value.delayPair();
+                        init_arrival += fanin.value.delayPair();
+                        if (clock_skew) {
+                            auto clock_delay = ports.at(CellPortKey(sp.first.cell, fanin.other_port)).route_delay;
+                            init_arrival += clock_delay;
+                        }
                         break;
                     }
                 }
@@ -619,20 +632,28 @@ void TimingAnalyser::walk_backward()
         auto &dom = domains.at(dom_id);
         for (auto &ep : dom.endpoints) {
             auto &pd = ports.at(ep.first);
-            DelayPair init_setuphold(0);
+            DelayPair init_required(0);
             CellPortKey clock_key;
             // TODO: clock routing delay, if analysis of that is enabled
             if (ep.second != IdString()) {
                 // Add setup/hold time, if this endpoint is clocked
                 for (auto &fanin : pd.cell_arcs) {
-                    if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second)
-                        init_setuphold.min_delay -= fanin.value.maxDelay();
+                    printf("walk bwd %s.%s, fanin: %s, arctype: %s\n", ep.first.cell.c_str(ctx),
+                           ep.first.port.c_str(ctx), fanin.other_port.c_str(ctx), arcType_to_str(fanin.type).c_str());
+
+                    if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second) {
+                        if (clock_skew) {
+                            auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
+                            init_required += clock_delay;
+                        }
+                        init_required.min_delay -= fanin.value.maxDelay();
+                    }
                     if (fanin.type == CellArc::HOLD && fanin.other_port == ep.second)
-                        init_setuphold.max_delay -= fanin.value.maxDelay();
+                        init_required.max_delay -= fanin.value.maxDelay();
                 }
                 clock_key = CellPortKey(ep.first.cell, ep.second);
             }
-            set_required_time(ep.first, dom_id, init_setuphold, 1, clock_key);
+            set_required_time(ep.first, dom_id, init_required, 1, clock_key);
         }
     }
     // Walk backwards in topological order
@@ -1211,6 +1232,8 @@ void timing_analysis(Context *ctx, bool print_slack_histogram, bool print_fmax,
                      bool update_results)
 {
     TimingAnalyser tmg(ctx);
+    tmg.setup_only = false;
+    tmg.clock_skew = true;
     tmg.setup(ctx->detailed_timing_report, print_slack_histogram, print_path || print_fmax);
 
     auto &result = tmg.get_timing_result();
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index ac78be4b79..eea57700da 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -98,6 +98,10 @@ struct TimingAnalyser
 
     TimingResult &get_timing_result() { return result; }
 
+    // Enable analysis of clock skew between FFs.
+    // Only do this after legal placement
+    bool clock_skew = false;
+
     bool setup_only = false;
     bool have_loops = false;
     bool updated_domains = false;

From 86106cb49a3e5f65c5525051e7896369acc9efac Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Sat, 14 Sep 2024 00:15:24 +0200
Subject: [PATCH 649/712] timing: integrate c2c delays and cleanup code

---
 common/kernel/context.cc      |  10 +-
 common/kernel/nextpnr_types.h |  12 +-
 common/kernel/timing.cc       | 220 +++++++++++++++++++++-------------
 common/kernel/timing.h        |  18 +--
 common/kernel/timing_log.cc   |  22 ++--
 5 files changed, 169 insertions(+), 113 deletions(-)

diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index 0e99c1b6f0..b194675d4e 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -116,10 +116,10 @@ delay_t Context::predictArcDelay(const NetInfo *net_info, const PortRef &sink) c
 
 delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
 {
-    // #ifdef ARCH_ECP5
-    //     if (net_info->is_global)
-    //         return 0;
-    // #endif
+#ifdef ARCH_ECP5
+    if (net_info->is_global)
+        return 0;
+#endif
 
     if (net_info->wires.empty())
         return predictArcDelay(net_info, user_info);
@@ -417,7 +417,7 @@ void Context::check() const
 namespace {
 struct FixupHierarchyWorker
 {
-    FixupHierarchyWorker(Context *ctx) : ctx(ctx) {};
+    FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
     Context *ctx;
     void run()
     {
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 23b319b9ed..292508b233 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -81,7 +81,7 @@ struct PortRef
 // minimum and maximum delay
 struct DelayPair
 {
-    DelayPair() : min_delay(0), max_delay(0) {};
+    DelayPair() : min_delay(0), max_delay(0){};
     explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) {}
     DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) {}
     delay_t minDelay() const { return min_delay; }
@@ -278,7 +278,7 @@ struct PseudoCell
     virtual bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const = 0;
     virtual TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const = 0;
     virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const = 0;
-    virtual ~PseudoCell() {};
+    virtual ~PseudoCell(){};
 };
 
 struct RegionPlug : PseudoCell
@@ -398,16 +398,20 @@ struct CriticalPath
         // Segment type
         enum class Type
         {
+            CLK_SKEW, // Clock skew
             CLK_TO_Q, // Clock-to-Q delay
             SOURCE,   // Delayless source
             LOGIC,    // Combinational logic delay
             ROUTING,  // Routing delay
-            SETUP     // Setup time in sink
+            SETUP,    // Setup time in sink
+            HOLD      // Hold time in sink
         };
 
         [[maybe_unused]] static const std::string type_to_str(Type typ)
         {
             switch (typ) {
+            case Type::CLK_SKEW:
+                return "CLK_SKEW";
             case Type::CLK_TO_Q:
                 return "CLK_TO_Q";
             case Type::SOURCE:
@@ -418,6 +422,8 @@ struct CriticalPath
                 return "ROUTING";
             case Type::SETUP:
                 return "SETUP";
+            case Type::HOLD:
+                return "HOLD";
             default:
                 log_error("Impossible Segment::Type");
             }
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 20b95d3c5e..e9a7b02282 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -175,19 +175,10 @@ void TimingAnalyser::get_route_delays()
         if (ni->driver.cell == nullptr || ni->driver.cell->bel == BelId())
             continue;
 
-        if (clock_skew) {
-            printf("net %s has driver %s.%s\n", ni->name.c_str(ctx), ni->driver.cell->name.c_str(ctx),
-                   ni->driver.port.c_str(ctx));
-        }
         for (auto &usr : ni->users) {
             if (usr.cell->bel == BelId())
                 continue;
             ports.at(CellPortKey(usr)).route_delay = DelayPair(ctx->getNetinfoRouteDelay(ni, usr));
-
-            if (clock_skew) {
-                printf("\tuser %s.%s, delay: %f\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
-                       ctx->getDelayNS(ctx->getNetinfoRouteDelay(ni, usr)));
-            }
         }
     }
 }
@@ -582,9 +573,10 @@ void TimingAnalyser::walk_forward()
                 for (auto &fanin : pd.cell_arcs) {
                     if (fanin.type == CellArc::CLK_TO_Q && fanin.other_port == sp.second) {
                         init_arrival += fanin.value.delayPair();
-                        if (clock_skew) {
+                        // Include the clock delay if clock_skew analysis is enabled
+                        if (with_clock_skew) {
                             auto clock_delay = ports.at(CellPortKey(sp.first.cell, fanin.other_port)).route_delay;
-                            init_arrival += clock_delay;
+                            init_arrival += DelayPair(clock_delay.min_delay);
                         }
                         break;
                     }
@@ -638,13 +630,11 @@ void TimingAnalyser::walk_backward()
             if (ep.second != IdString()) {
                 // Add setup/hold time, if this endpoint is clocked
                 for (auto &fanin : pd.cell_arcs) {
-                    printf("walk bwd %s.%s, fanin: %s, arctype: %s\n", ep.first.cell.c_str(ctx),
-                           ep.first.port.c_str(ctx), fanin.other_port.c_str(ctx), arcType_to_str(fanin.type).c_str());
 
                     if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second) {
-                        if (clock_skew) {
+                        if (with_clock_skew) {
                             auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
-                            init_required += clock_delay;
+                            init_required -= DelayPair(clock_delay.min_delay);
                         }
                         init_required.min_delay -= fanin.value.maxDelay();
                     }
@@ -695,6 +685,9 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
                 auto dp = domain_pair_id(launch, capture);
 
                 delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
+                printf("%s -> %s, arr: %f, req: %f, delay: %f\n", domains.at(launch).key.clock.c_str(ctx),
+                       domains.at(capture).key.clock.c_str(ctx), ctx->getDelayNS(arr.second.value.maxDelay()),
+                       ctx->getDelayNS(req.second.value.minDelay()), ctx->getDelayNS(delay));
                 if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
                     domain_delay[dp] = delay;
             }
@@ -825,9 +818,9 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 {
     CriticalPath report;
 
-    auto &dp = domain_pairs.at(domain_pair);
-    auto &launch = domains.at(dp.key.launch).key;
-    auto &capture = domains.at(dp.key.capture).key;
+    const auto &dp = domain_pairs.at(domain_pair);
+    const auto &launch = domains.at(dp.key.launch).key;
+    const auto &capture = domains.at(dp.key.capture).key;
 
     report.delay = DelayPair(0);
 
@@ -851,27 +844,13 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     }
 
-    // Set hold time
-    auto cell = cell_info(endpoint);
-    auto &port = port_info(endpoint);
-    int port_clocks;
-    auto portClass = ctx->getPortTimingClass(cell, port.name, port_clocks);
-    if (portClass == TMG_REGISTER_INPUT) {
-        for (int i = 0; i < port_clocks; i++) {
-            auto info = ctx->getPortClockingInfo(cell, port.name, i);
-            if (!cell->ports.count(info.clock_port) || cell->ports.at(info.clock_port).net == nullptr)
-                continue;
-
-            report.bound.min_delay = info.hold.min_delay;
-            break;
-        }
-    }
-
+    // Walk the min or max path backwards to find a single crit path
     pool<std::pair<IdString, IdString>> visited;
     std::vector<PortRef> crit_path_rev;
     auto cursor = endpoint;
 
-    while (cursor != CellPortKey()) {
+    bool is_startpoint = false;
+    do {
         auto cell = cell_info(cursor);
         auto &port = port_info(cursor);
         int port_clocks;
@@ -881,7 +860,12 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (!visited.insert(std::make_pair(cell->name, port.name)).second)
             break;
 
-        if (portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN)
+        // We store the reversed critical path as all input ports that lead to
+        // the timing startpoint.
+        auto is_input = portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN;
+        is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT;
+
+        if (is_input || is_startpoint)
             crit_path_rev.emplace_back(PortRef{cell, port.name});
 
         if (!ports.at(cursor).arrival.count(dp.key.launch))
@@ -892,32 +876,99 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         } else {
             cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_min;
         }
-    }
+    } while (!is_startpoint);
 
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
 
-    auto &front = crit_path.front();
-    auto &front_port = front.cell->ports.at(front.port);
-    auto &front_driver = front_port.net->driver;
-
-    portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
-
-    const CellInfo *last_cell = front.cell;
-    IdString last_port = front_driver.port;
+    // Get timing and clocking info on the startpoint
+    const auto &sp = crit_path.front();
+    const auto &sp_cell = sp.cell;
+    const auto &sp_port = sp_cell->ports.at(sp.port);
+    int sp_clocks;
+    const auto sp_portClass = ctx->getPortTimingClass(sp_cell, sp_port.name, sp_clocks);
+    TimingClockingInfo sp_clk_info;
+    const NetInfo *sp_clk_net = nullptr;
+    bool register_start = sp_portClass == TMG_REGISTER_OUTPUT;
+
+    if (register_start) {
+        // If we don't find a clock we don't consider this startpoint to be registered.
+        register_start = sp_clocks > 0;
+        for (int i = 0; i < sp_clocks; i++) {
+            sp_clk_info = ctx->getPortClockingInfo(sp_cell, sp_port.name, i);
+            const auto clk_net = sp_cell->getPort(sp_clk_info.clock_port);
+            register_start = clk_net != nullptr && clk_net->name == launch.clock && sp_clk_info.edge == launch.edge;
+            if (register_start) {
+                sp_clk_net = clk_net;
+                break;
+            }
+        }
+    }
 
-    int clock_start = -1;
-    if (portClass == TMG_REGISTER_OUTPUT) {
-        for (int i = 0; i < port_clocks; i++) {
-            TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
-            const NetInfo *clknet = front_driver.cell->getPort(clockInfo.clock_port);
-            if (clknet != nullptr && clknet->name == launch.clock && clockInfo.edge == launch.edge) {
-                last_port = clockInfo.clock_port;
-                clock_start = i;
+    // Get timing and clocking info on the endpoint
+    const auto &ep = crit_path.back();
+    const auto &ep_cell = ep.cell;
+    const auto &ep_port = ep_cell->ports.at(ep.port);
+    int ep_clocks;
+    const auto ep_portClass = ctx->getPortTimingClass(ep_cell, ep_port.name, ep_clocks);
+    TimingClockingInfo ep_clk_info;
+    const NetInfo *ep_clk_net = nullptr;
+
+    bool register_end = ep_portClass == TMG_REGISTER_INPUT;
+
+    if (register_end) {
+        // If we don't find a clock we don't consider this startpoint to be registered.
+        register_end = ep_clocks > 0;
+        for (int i = 0; i < ep_clocks; i++) {
+            ep_clk_info = ctx->getPortClockingInfo(ep_cell, ep_port.name, i);
+            const auto clk_net = ep_cell->getPort(ep_clk_info.clock_port);
+
+            register_end = clk_net != nullptr && clk_net->name == capture.clock && ep_clk_info.edge == capture.edge;
+            if (register_end) {
+                ep_clk_net = clk_net;
                 break;
             }
         }
     }
 
+    auto clock_pair = std::make_pair(launch.clock, capture.clock);
+    auto related_clock = clock_delays.count(clock_pair) > 0;
+    auto same_clock = launch.clock == capture.clock;
+
+    delay_t skew = 0;
+    if (related_clock) {
+        skew -= clock_delays.at(clock_pair);
+    }
+
+    // Calculate clock skew only if start- and endpoint are registered
+    // and either the clock domains are the same or related clock
+    if (with_clock_skew && register_start && register_end && (same_clock || related_clock)) {
+
+        auto clock_delay_launch = ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
+        auto clock_delay_capture = ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
+
+        printf("delay launch: %f\n", ctx->getDelayNS(clock_delay_launch));
+        printf("delay capture: %f\n", ctx->getDelayNS(clock_delay_capture));
+        printf("clock to clock: %f\n", ctx->getDelayNS(skew));
+        skew += clock_delay_launch - clock_delay_capture;
+    }
+
+    if (skew != 0) {
+        CriticalPath::Segment seg_skew;
+        seg_skew.type = CriticalPath::Segment::Type::CLK_SKEW;
+        seg_skew.delay = DelayPair(skew);
+        seg_skew.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
+        seg_skew.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
+        if (same_clock) {
+            seg_skew.net = launch.clock;
+        } else {
+            seg_skew.net = IdString();
+        }
+        report.segments.push_back(seg_skew);
+    }
+
+    const CellInfo *prev_cell = sp_cell;
+    IdString prev_port = sp_port.name;
+
     for (auto sink : crit_path) {
         auto sink_cell = sink.cell;
         auto &port = sink_cell->ports.at(sink.port);
@@ -928,22 +979,20 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         CriticalPath::Segment seg_logic;
 
         DelayQuad comb_delay;
-        if (clock_start != -1) {
-            auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
-            comb_delay = clockInfo.clockToQ;
-            clock_start = -1;
+        if (is_startpoint && register_start) {
+            comb_delay = sp_clk_info.clockToQ;
             seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
-        } else if (last_port == driver.port) {
+        } else if (prev_port == driver.port) {
             // Case where we start with a STARTPOINT etc
             comb_delay = DelayQuad(0);
             seg_logic.type = CriticalPath::Segment::Type::SOURCE;
         } else {
-            ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
+            ctx->getCellDelay(driver_cell, prev_port, driver.port, comb_delay);
             seg_logic.type = CriticalPath::Segment::Type::LOGIC;
         }
 
         seg_logic.delay = comb_delay.delayPair();
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.from = std::make_pair(prev_cell->name, prev_port);
         seg_logic.to = std::make_pair(driver_cell->name, driver.port);
         seg_logic.net = IdString();
         report.segments.push_back(seg_logic);
@@ -958,23 +1007,29 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         seg_route.net = net->name;
         report.segments.push_back(seg_route);
 
-        last_cell = sink_cell;
-        last_port = sink.port;
+        prev_cell = sink_cell;
+        prev_port = sink.port;
+        is_startpoint = false;
     }
 
-    int clockCount = 0;
-    auto sinkClass = ctx->getPortTimingClass(crit_path.back().cell, crit_path.back().port, clockCount);
-    if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
-        auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back().cell, crit_path.back().port, 0);
-        auto setup = sinkClockInfo.setup;
-
+    // Add setup/hold time as final segment
+    // And add hold time as min bound
+    if (register_end) {
         CriticalPath::Segment seg_logic;
-        seg_logic.type = CriticalPath::Segment::Type::SETUP;
-        seg_logic.delay = setup;
-        seg_logic.from = std::make_pair(last_cell->name, last_port);
+        seg_logic.delay = DelayPair(0);
+        if (longest_path) {
+            seg_logic.type = CriticalPath::Segment::Type::SETUP;
+            seg_logic.delay += ep_clk_info.setup;
+        } else {
+            seg_logic.type = CriticalPath::Segment::Type::HOLD;
+            seg_logic.delay -= ep_clk_info.hold;
+        }
+        seg_logic.from = std::make_pair(prev_cell->name, prev_port);
         seg_logic.to = seg_logic.from;
         seg_logic.net = IdString();
         report.segments.push_back(seg_logic);
+
+        report.bound.min_delay = ep_clk_info.hold.min_delay;
     }
 
     return report;
@@ -1116,17 +1171,6 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
         const auto &capture = domains.at(capture_id);
         const auto &capture_clock = capture.key.clock;
 
-        if (ctx->nets.count(capture_clock) == 0) {
-            continue;
-        }
-
-        NetInfo *clk_net = ctx->nets.at(capture_clock).get();
-        if (clk_net->clkconstr == nullptr) {
-            continue;
-        }
-
-        DelayPair period = clk_net->clkconstr->period;
-
         for (auto &ep : capture.endpoints) {
             CellInfo *ci = cell_info(ep.first);
             int clkInfoCount = 0;
@@ -1143,7 +1187,7 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                 const auto &launch_clock = launch.key.clock;
 
                 auto clocks = std::make_pair(launch_clock, capture_clock);
-                auto related_clocks = clock_delays.count(clocks) != 0;
+                auto related_clocks = clock_delays.count(clocks) > 0;
 
                 // Don't consider clocks without known relationships
                 if (launch_id != capture_id && !related_clocks) {
@@ -1155,9 +1199,13 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                     clock_to_clock = clock_delays.at(clocks);
                 }
 
-                auto hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
+                auto hold_slack = arr.value.minDelay() + req.value.maxDelay() + clock_to_clock;
+                auto violated = hold_slack <= 0;
 
-                auto violated = true;
+                // printf("arr min: %f, req max: %f, c2c; %f, slack: %f, arr path len: %d, req path len: %d\n",
+                //        ctx->getDelayNS(arr.value.minDelay()), ctx->getDelayNS(req.value.maxDelay()),
+                //        ctx->getDelayNS(clock_to_clock), ctx->getDelayNS(hold_slack), arr.path_length,
+                //        req.path_length);
 
                 if (violated) {
                     const auto dom_pair_id = domain_pair_id(launch_id, capture_id);
@@ -1233,7 +1281,7 @@ void timing_analysis(Context *ctx, bool print_slack_histogram, bool print_fmax,
 {
     TimingAnalyser tmg(ctx);
     tmg.setup_only = false;
-    tmg.clock_skew = true;
+    tmg.with_clock_skew = false;
     tmg.setup(ctx->detailed_timing_report, print_slack_histogram, print_path || print_fmax);
 
     auto &result = tmg.get_timing_result();
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index eea57700da..fc60a5ee10 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -27,8 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct CellPortKey
 {
-    CellPortKey() {};
-    CellPortKey(IdString cell, IdString port) : cell(cell), port(port) {};
+    CellPortKey(){};
+    CellPortKey(IdString cell, IdString port) : cell(cell), port(port){};
     explicit CellPortKey(const PortRef &pr)
     {
         NPNR_ASSERT(pr.cell != nullptr);
@@ -49,7 +49,7 @@ struct ClockDomainKey
 {
     IdString clock;
     ClockEdge edge;
-    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge) {};
+    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge){};
     // probably also need something here to deal with constraints
     inline bool is_async() const { return clock == IdString(); }
 
@@ -63,7 +63,7 @@ typedef int domain_id_t;
 struct ClockDomainPairKey
 {
     domain_id_t launch, capture;
-    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture) {};
+    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture){};
     inline bool operator==(const ClockDomainPairKey &other) const
     {
         return (launch == other.launch) && (capture == other.capture);
@@ -100,7 +100,7 @@ struct TimingAnalyser
 
     // Enable analysis of clock skew between FFs.
     // Only do this after legal placement
-    bool clock_skew = false;
+    bool with_clock_skew = true;
 
     bool setup_only = false;
     bool have_loops = false;
@@ -180,9 +180,9 @@ struct TimingAnalyser
         ClockEdge edge;
 
         CellArc(ArcType type, IdString other_port, DelayQuad value)
-                : type(type), other_port(other_port), value(value), edge(RISING_EDGE) {};
+                : type(type), other_port(other_port), value(value), edge(RISING_EDGE){};
         CellArc(ArcType type, IdString other_port, DelayQuad value, ClockEdge edge)
-                : type(type), other_port(other_port), value(value), edge(edge) {};
+                : type(type), other_port(other_port), value(value), edge(edge){};
     };
 
     // Timing data for every cell port
@@ -206,7 +206,7 @@ struct TimingAnalyser
 
     struct PerDomain
     {
-        PerDomain(ClockDomainKey key) : key(key) {};
+        PerDomain(ClockDomainKey key) : key(key){};
         ClockDomainKey key;
         // these are pairs (signal port; clock port)
         std::vector<std::pair<CellPortKey, IdString>> startpoints, endpoints;
@@ -214,7 +214,7 @@ struct TimingAnalyser
 
     struct PerDomainPair
     {
-        PerDomainPair(ClockDomainPairKey key) : key(key) {};
+        PerDomainPair(ClockDomainPairKey key) : key(key){};
         ClockDomainPairKey key;
         DelayPair period{0};
         delay_t worst_setup_slack, worst_hold_slack;
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 349f2ba8aa..4de2fac772 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             return ctx->getDelayNS(d.maxDelay());
         };
 
-        log_info("curr total\n");
+        log_info(" curr  total type\n");
         for (const auto &segment : path.segments) {
 
             total += segment.delay;
@@ -90,14 +90,15 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
                 segment.type == CriticalPath::Segment::Type::SOURCE ||
                 segment.type == CriticalPath::Segment::Type::LOGIC ||
-                segment.type == CriticalPath::Segment::Type::SETUP) {
+                segment.type == CriticalPath::Segment::Type::SETUP ||
+                segment.type == CriticalPath::Segment::Type::HOLD) {
                 logic_total += segment.delay;
 
-                const std::string type_name = (segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
-
-                log_info("%4.1f %4.1f  %s %s.%s\n", get_delay_ns(segment.delay), get_delay_ns(total), type_name.c_str(),
-                         segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
-            } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
+                log_info("% 5.2f % 5.2f  %s %s.%s\n", get_delay_ns(segment.delay), get_delay_ns(total),
+                         CriticalPath::Segment::type_to_str(segment.type).c_str(), segment.to.first.c_str(ctx),
+                         segment.to.second.c_str(ctx));
+            } else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
+                       segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
                 route_total = route_total + segment.delay;
 
                 const auto &driver = ctx->cells.at(segment.from.first);
@@ -106,7 +107,8 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto driver_loc = ctx->getBelLocation(driver->bel);
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                log_info("%4.1f %4.1f    Net %s (%d,%d) -> (%d,%d)\n", get_delay_ns(segment.delay), get_delay_ns(total),
+                log_info("% 5.2f % 5.2f  %s Net %s (%d,%d) -> (%d,%d)\n", get_delay_ns(segment.delay),
+                         get_delay_ns(total), CriticalPath::Segment::type_to_str(segment.type).c_str(),
                          segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
                 log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
 
@@ -145,7 +147,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 }
             }
         }
-        log_info("%.1f ns logic, %.1f ns routing\n", get_delay_ns(logic_total), get_delay_ns(route_total));
+        log_info("%.2f ns logic, %.2f ns routing\n", get_delay_ns(logic_total), get_delay_ns(route_total));
     };
 
     // Single domain paths
@@ -175,7 +177,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
     auto num_min_violations = result.min_delay_violations.size();
     if (num_min_violations > 0) {
         log_break();
-        log_info("Hold time violations:\n");
+        log_info("Hold time/min time violation:\n");
         for (size_t i = 0; i < std::min((size_t)10, num_min_violations); ++i) {
             auto &report = result.min_delay_violations.at(i);
             log_break();

From 8e12dfc69378012fe2432716ecdecc41b21e8449 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 13:47:03 +0200
Subject: [PATCH 650/712] timing: cleanup clock2clock reporting timing: Add
 clock2clock delay as seperate         timing line item.

---
 common/kernel/nextpnr_types.h |  6 +--
 common/kernel/timing.cc       | 79 +++++++++++++++++++++--------------
 common/kernel/timing_log.cc   | 51 +++++++++++++---------
 3 files changed, 83 insertions(+), 53 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 292508b233..1f5b2fee1b 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -398,6 +398,7 @@ struct CriticalPath
         // Segment type
         enum class Type
         {
+            CLK2CLK,  // Clock to clock delay
             CLK_SKEW, // Clock skew
             CLK_TO_Q, // Clock-to-Q delay
             SOURCE,   // Delayless source
@@ -410,6 +411,8 @@ struct CriticalPath
         [[maybe_unused]] static const std::string type_to_str(Type typ)
         {
             switch (typ) {
+            case Type::CLK2CLK:
+                return "CLK2CLK";
             case Type::CLK_SKEW:
                 return "CLK_SKEW";
             case Type::CLK_TO_Q:
@@ -479,9 +482,6 @@ struct TimingResult
     // Detailed net timing data
     dict<IdString, std::vector<NetSinkTiming>> detailed_net_timings;
 
-    // clock to clock delays
-    dict<std::pair<IdString, IdString>, delay_t> clock_delays;
-
     // Histogram of slack
     dict<int, unsigned> slack_histogram;
 
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index e9a7b02282..6e9491ccb2 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -675,19 +675,31 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 {
     dict<domain_id_t, delay_t> domain_delay;
 
-    for (auto p : topological_order) {
-        auto &pd = ports.at(p);
-        for (auto &req : pd.required) {
-            auto &capture = req.first;
-            for (auto &arr : pd.arrival) {
-                auto &launch = arr.first;
+    for (domain_id_t capture_id = 0; capture_id < domain_id_t(domains.size()); ++capture_id) {
+        const auto &capture = domains.at(capture_id);
+        const auto &capture_clock = capture.key.clock;
+
+        for (auto &ep : capture.endpoints) {
+            auto &port = ports.at(ep.first);
+
+            auto &req = port.required.at(capture_id);
 
-                auto dp = domain_pair_id(launch, capture);
+            for (auto &[launch_id, arr] : port.arrival) {
+
+                // const auto &launch = domains.at(launch_id);
+                // const auto &launch_clock = launch.key.clock;
+
+                // auto clocks = std::make_pair(launch_clock, capture_clock);
+                // auto related_clocks = clock_delays.count(clocks) > 0;
+
+                // delay_t clock_to_clock = 0;
+                // if (related_clocks) {
+                //     clock_to_clock = clock_delays.at(clocks);
+                // }
+
+                auto dp = domain_pair_id(launch_id, capture_id);
+                auto delay = arr.value.maxDelay() - req.value.maxDelay();
 
-                delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
-                printf("%s -> %s, arr: %f, req: %f, delay: %f\n", domains.at(launch).key.clock.c_str(ctx),
-                       domains.at(capture).key.clock.c_str(ctx), ctx->getDelayNS(arr.second.value.maxDelay()),
-                       ctx->getDelayNS(req.second.value.minDelay()), ctx->getDelayNS(delay));
                 if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
                     domain_delay[dp] = delay;
             }
@@ -934,9 +946,17 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto related_clock = clock_delays.count(clock_pair) > 0;
     auto same_clock = launch.clock == capture.clock;
 
-    delay_t skew = 0;
     if (related_clock) {
-        skew -= clock_delays.at(clock_pair);
+        delay_t clock_delay = clock_delays.at(clock_pair);
+        if (clock_delay != 0) {
+            CriticalPath::Segment seg_c2c;
+            seg_c2c.type = CriticalPath::Segment::Type::CLK2CLK;
+            seg_c2c.delay = DelayPair(clock_delay);
+            seg_c2c.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
+            seg_c2c.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
+            seg_c2c.net = IdString();
+            report.segments.push_back(seg_c2c);
+        }
     }
 
     // Calculate clock skew only if start- and endpoint are registered
@@ -946,24 +966,24 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         auto clock_delay_launch = ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
         auto clock_delay_capture = ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
 
+        delay_t clock_skew = clock_delay_launch - clock_delay_capture;
         printf("delay launch: %f\n", ctx->getDelayNS(clock_delay_launch));
         printf("delay capture: %f\n", ctx->getDelayNS(clock_delay_capture));
-        printf("clock to clock: %f\n", ctx->getDelayNS(skew));
-        skew += clock_delay_launch - clock_delay_capture;
-    }
-
-    if (skew != 0) {
-        CriticalPath::Segment seg_skew;
-        seg_skew.type = CriticalPath::Segment::Type::CLK_SKEW;
-        seg_skew.delay = DelayPair(skew);
-        seg_skew.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
-        seg_skew.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
-        if (same_clock) {
-            seg_skew.net = launch.clock;
-        } else {
-            seg_skew.net = IdString();
+        printf("clock to clock: %f\n", ctx->getDelayNS(clock_skew));
+
+        if (clock_skew != 0) {
+            CriticalPath::Segment seg_skew;
+            seg_skew.type = CriticalPath::Segment::Type::CLK_SKEW;
+            seg_skew.delay = DelayPair(clock_skew);
+            seg_skew.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
+            seg_skew.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
+            if (same_clock) {
+                seg_skew.net = launch.clock;
+            } else {
+                seg_skew.net = IdString();
+            }
+            report.segments.push_back(seg_skew);
         }
-        report.segments.push_back(seg_skew);
     }
 
     const CellInfo *prev_cell = sp_cell;
@@ -1041,7 +1061,6 @@ void TimingAnalyser::build_crit_path_reports()
     auto &xclock_reports = result.xclock_paths;
     auto &clock_fmax = result.clock_fmax;
     auto &empty_clocks = result.empty_paths;
-    auto &clock_delays_ctx = result.clock_delays;
 
     if (!setup_only) {
         result.min_delay_violations = get_min_delay_violations();
@@ -1125,8 +1144,6 @@ void TimingAnalyser::build_crit_path_reports()
     };
 
     std::sort(xclock_reports.begin(), xclock_reports.end(), cmp_crit_path);
-
-    clock_delays_ctx = clock_delays;
 }
 
 void TimingAnalyser::build_slack_histogram_report()
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 4de2fac772..e6fdc935f9 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -61,9 +61,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
         source_entries.emplace_back(sourcelist.substr(prev, current - prev));
 
         // Iterate and print our source list at the correct indentation level
-        log_info("               Defined in:\n");
+        log_info("                        Defined in:\n");
         for (auto entry : source_entries) {
-            log_info("                 %s\n", entry.c_str());
+            log_info("                          %s\n", entry.c_str());
         }
     };
 
@@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             return ctx->getDelayNS(d.maxDelay());
         };
 
-        log_info(" curr  total type\n");
+        log_info("    type  curr  total\n");
         for (const auto &segment : path.segments) {
 
             total += segment.delay;
@@ -94,10 +94,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 segment.type == CriticalPath::Segment::Type::HOLD) {
                 logic_total += segment.delay;
 
-                log_info("% 5.2f % 5.2f  %s %s.%s\n", get_delay_ns(segment.delay), get_delay_ns(total),
-                         CriticalPath::Segment::type_to_str(segment.type).c_str(), segment.to.first.c_str(ctx),
+                log_info("%8s % 5.2f % 5.2f  %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
+                         get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
+                       segment.type == CriticalPath::Segment::Type::CLK2CLK ||
                        segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
                 route_total = route_total + segment.delay;
 
@@ -107,10 +108,12 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto driver_loc = ctx->getBelLocation(driver->bel);
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                log_info("% 5.2f % 5.2f  %s Net %s (%d,%d) -> (%d,%d)\n", get_delay_ns(segment.delay),
-                         get_delay_ns(total), CriticalPath::Segment::type_to_str(segment.type).c_str(),
-                         segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
-                log_info("               Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
+                log_info("%8s % 5.2f % 5.2f  Net %s (%d,%d) -> (%d,%d)\n",
+                         CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay),
+                         get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
+                         sink_loc.y);
+                log_info("                        Sink %s.%s\n", segment.to.first.c_str(ctx),
+                         segment.to.second.c_str(ctx));
 
                 const NetInfo *net = ctx->nets.at(segment.net).get();
 
@@ -227,14 +230,25 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     log_break();
 
     // Clock to clock delays for xpaths
-    dict<ClockPair, delay_t> xclock_delays;
+    dict<ClockPair, DelayPair> xclock_delays;
     for (auto &report : result.xclock_paths) {
         const auto &clock1_name = report.clock_pair.start.clock;
         const auto &clock2_name = report.clock_pair.end.clock;
 
-        const auto key = std::make_pair(clock1_name, clock2_name);
-        if (result.clock_delays.count(key)) {
-            xclock_delays[report.clock_pair] = result.clock_delays.at(key);
+        // Check if this path has a clock-2-clock delay
+        // clock-2-clock delays are always the first segment in the path
+        // But we walk the entire path anyway.
+        bool has_clock_to_clock = false;
+        DelayPair clock_delay = DelayPair(0);
+        for (const auto &seg : report.segments) {
+            if (seg.type == CriticalPath::Segment::Type::CLK2CLK) {
+                has_clock_to_clock = true;
+                clock_delay += seg.delay;
+            }
+        }
+
+        if (has_clock_to_clock) {
+            xclock_delays[report.clock_pair] = clock_delay;
         }
     }
 
@@ -252,7 +266,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             const auto &clock_b = report.clock_pair.end.clock;
 
             const auto key = std::make_pair(clock_a, clock_b);
-            if (!result.clock_delays.count(key)) {
+            if (!xclock_delays.count(report.clock_pair)) {
                 continue;
             }
 
@@ -264,12 +278,11 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             // Compensate path delay for clock-to-clock delay. If the
             // result is negative then only the latter matters. Otherwise
             // the compensated path delay is taken.
-            auto clock_delay = result.clock_delays.at(key);
-            path_delay -= DelayPair(clock_delay);
+            auto clock_delay = xclock_delays.at(report.clock_pair);
 
             float fmax = std::numeric_limits<float>::infinity();
             if (path_delay.maxDelay() < 0) {
-                fmax = 1e3f / ctx->getDelayNS(clock_delay);
+                fmax = 1e3f / ctx->getDelayNS(clock_delay.maxDelay());
             } else if (path_delay.maxDelay() > 0) {
                 fmax = 1e3f / ctx->getDelayNS(path_delay.maxDelay());
             }
@@ -308,12 +321,12 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     }
 
     // Report clock delays for xpaths
-    if (!result.clock_delays.empty()) {
+    if (!xclock_delays.empty()) {
         for (auto &pair : xclock_delays) {
             auto ev_a = clock_event_name(ctx, pair.first.start, max_width_xca);
             auto ev_b = clock_event_name(ctx, pair.first.end, max_width_xcb);
 
-            delay_t delay = pair.second;
+            delay_t delay = pair.second.maxDelay();
             if (pair.first.start.edge != pair.first.end.edge) {
                 delay /= 2;
             }

From 4488d42368f98dc6557f7a8071a31ee3e254a1e0 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 15:42:20 +0200
Subject: [PATCH 651/712] log: Remove bad usage of [[no_return]]

---
 common/kernel/log.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/kernel/log.cc b/common/kernel/log.cc
index 7bb7f6d748..a0bdd64eb1 100644
--- a/common/kernel/log.cc
+++ b/common/kernel/log.cc
@@ -135,7 +135,7 @@ void logv_nonfatal_error(const char *format, va_list ap)
     had_nonfatal_error = true;
 }
 
-[[noreturn]] void logv_error(const char *format, va_list ap)
+void logv_error(const char *format, va_list ap)
 {
     logv_prefixed("ERROR: ", format, ap, LogLevel::ERROR_MSG);
 
@@ -180,7 +180,7 @@ void log_warning(const char *format, ...)
     va_end(ap);
 }
 
-[[noreturn]] void log_error(const char *format, ...)
+void log_error(const char *format, ...)
 {
     va_list ap;
     va_start(ap, format);

From 3b7fec8c4ffd36344e6d8d6088e3ea24805a590b Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 15:50:27 +0200
Subject: [PATCH 652/712] report: Handle new segment types

---
 common/kernel/report.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index 917740b96c..7fe0bf74d9 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -79,7 +79,11 @@ static Json::array json_report_critical_paths(const Context *ctx)
             auto segmentJson =
                     Json::object({{"delay", Json::array({minDelay, maxDelay})}, {"from", fromJson}, {"to", toJson}});
 
-            if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
+            if (segment.type == CriticalPath::Segment::Type::CLK2CLK) {
+                segmentJson["type"] = "clk-to-clk";
+            } else if (segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
+                segmentJson["type"] = "clk-skew";
+            } else if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
                 segmentJson["type"] = "clk-to-q";
             } else if (segment.type == CriticalPath::Segment::Type::SOURCE) {
                 segmentJson["type"] = "source";

From eb0bf9ea9ca1861ed8919bf6ad6b654f96c0e0d9 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 16:08:00 +0200
Subject: [PATCH 653/712] report: Handle new segment types timing_log: Use
 common segment type strings

---
 common/kernel/nextpnr_types.h | 34 +++++++++++++++++-----------------
 common/kernel/report.cc       | 16 ++--------------
 common/kernel/timing.cc       |  2 +-
 common/kernel/timing_log.cc   | 18 +++++++++---------
 4 files changed, 29 insertions(+), 41 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 1f5b2fee1b..ff3b656fba 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -398,35 +398,35 @@ struct CriticalPath
         // Segment type
         enum class Type
         {
-            CLK2CLK,  // Clock to clock delay
-            CLK_SKEW, // Clock skew
-            CLK_TO_Q, // Clock-to-Q delay
-            SOURCE,   // Delayless source
-            LOGIC,    // Combinational logic delay
-            ROUTING,  // Routing delay
-            SETUP,    // Setup time in sink
-            HOLD      // Hold time in sink
+            CLK_TO_CLK, // Clock to clock delay
+            CLK_SKEW,   // Clock skew
+            CLK_TO_Q,   // Clock-to-Q delay
+            SOURCE,     // Delayless source
+            LOGIC,      // Combinational logic delay
+            ROUTING,    // Routing delay
+            SETUP,      // Setup time in sink
+            HOLD        // Hold time in sink
         };
 
         [[maybe_unused]] static const std::string type_to_str(Type typ)
         {
             switch (typ) {
-            case Type::CLK2CLK:
-                return "CLK2CLK";
+            case Type::CLK_TO_CLK:
+                return "clk-to-clk";
             case Type::CLK_SKEW:
-                return "CLK_SKEW";
+                return "clk-skew";
             case Type::CLK_TO_Q:
-                return "CLK_TO_Q";
+                return "clk-to-q";
             case Type::SOURCE:
-                return "SOURCE";
+                return "source";
             case Type::LOGIC:
-                return "LOGIC";
+                return "logic";
             case Type::ROUTING:
-                return "ROUTING";
+                return "routing";
             case Type::SETUP:
-                return "SETUP";
+                return "setup";
             case Type::HOLD:
-                return "HOLD";
+                return "hold";
             default:
                 log_error("Impossible Segment::Type");
             }
diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index 7fe0bf74d9..cd5b11722e 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -79,20 +79,8 @@ static Json::array json_report_critical_paths(const Context *ctx)
             auto segmentJson =
                     Json::object({{"delay", Json::array({minDelay, maxDelay})}, {"from", fromJson}, {"to", toJson}});
 
-            if (segment.type == CriticalPath::Segment::Type::CLK2CLK) {
-                segmentJson["type"] = "clk-to-clk";
-            } else if (segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
-                segmentJson["type"] = "clk-skew";
-            } else if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
-                segmentJson["type"] = "clk-to-q";
-            } else if (segment.type == CriticalPath::Segment::Type::SOURCE) {
-                segmentJson["type"] = "source";
-            } else if (segment.type == CriticalPath::Segment::Type::LOGIC) {
-                segmentJson["type"] = "logic";
-            } else if (segment.type == CriticalPath::Segment::Type::SETUP) {
-                segmentJson["type"] = "setup";
-            } else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
-                segmentJson["type"] = "routing";
+            segmentJson["type"] = CriticalPath::Segment::type_to_str(segment.type);
+            if (segment.type == CriticalPath::Segment::Type::ROUTING) {
                 segmentJson["net"] = segment.net.c_str(ctx);
             }
 
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 6e9491ccb2..957c4f5a14 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -950,7 +950,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         delay_t clock_delay = clock_delays.at(clock_pair);
         if (clock_delay != 0) {
             CriticalPath::Segment seg_c2c;
-            seg_c2c.type = CriticalPath::Segment::Type::CLK2CLK;
+            seg_c2c.type = CriticalPath::Segment::Type::CLK_TO_CLK;
             seg_c2c.delay = DelayPair(clock_delay);
             seg_c2c.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
             seg_c2c.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index e6fdc935f9..e21fcb3d43 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -61,9 +61,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
         source_entries.emplace_back(sourcelist.substr(prev, current - prev));
 
         // Iterate and print our source list at the correct indentation level
-        log_info("                        Defined in:\n");
+        log_info("                          Defined in:\n");
         for (auto entry : source_entries) {
-            log_info("                          %s\n", entry.c_str());
+            log_info("                            %s\n", entry.c_str());
         }
     };
 
@@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             return ctx->getDelayNS(d.maxDelay());
         };
 
-        log_info("    type  curr  total\n");
+        log_info("      type  curr  total\n");
         for (const auto &segment : path.segments) {
 
             total += segment.delay;
@@ -94,11 +94,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 segment.type == CriticalPath::Segment::Type::HOLD) {
                 logic_total += segment.delay;
 
-                log_info("%8s % 5.2f % 5.2f  %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
+                log_info("%10s % 5.2f % 5.2f  %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
                          get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
-                       segment.type == CriticalPath::Segment::Type::CLK2CLK ||
+                       segment.type == CriticalPath::Segment::Type::CLK_TO_CLK ||
                        segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
                 route_total = route_total + segment.delay;
 
@@ -108,11 +108,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto driver_loc = ctx->getBelLocation(driver->bel);
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                log_info("%8s % 5.2f % 5.2f  Net %s (%d,%d) -> (%d,%d)\n",
+                log_info("%10s % 5.2f % 5.2f  Net %s (%d,%d) -> (%d,%d)\n",
                          CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay),
                          get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
                          sink_loc.y);
-                log_info("                        Sink %s.%s\n", segment.to.first.c_str(ctx),
+                log_info("                          Sink %s.%s\n", segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
 
                 const NetInfo *net = ctx->nets.at(segment.net).get();
@@ -125,7 +125,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
 
                     auto driver_wire = ctx->getNetinfoSourceWire(net);
                     auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
-                    log_info("                 prediction: %f ns estimate: %f ns\n",
+                    log_info("                          prediction: %f ns estimate: %f ns\n",
                              ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
                              ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
                     auto cursor = sink_wire;
@@ -241,7 +241,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
         bool has_clock_to_clock = false;
         DelayPair clock_delay = DelayPair(0);
         for (const auto &seg : report.segments) {
-            if (seg.type == CriticalPath::Segment::Type::CLK2CLK) {
+            if (seg.type == CriticalPath::Segment::Type::CLK_TO_CLK) {
                 has_clock_to_clock = true;
                 clock_delay += seg.delay;
             }

From bca6f6394a887e46445fefe47ff62e490b35b33b Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 21:26:43 +0200
Subject: [PATCH 654/712] timing: Fix slack calculations timing: Fix
 max_delay_by_domain_pair function timing: Fix hold time check

---
 common/kernel/timing.cc     | 169 +++++++++++++++++++++---------------
 common/kernel/timing.h      |   6 ++
 common/kernel/timing_log.cc |   6 +-
 3 files changed, 108 insertions(+), 73 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 957c4f5a14..008eff504d 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -118,9 +118,7 @@ void TimingAnalyser::get_cell_delays()
                         continue;
                     pd.cell_arcs.emplace_back(CellArc::SETUP, info.clock_port, DelayQuad(info.setup, info.setup),
                                               info.edge);
-                    auto hold_factor = 1;
-                    auto hold_faked = DelayPair(hold_factor * info.hold.min_delay, hold_factor * info.hold.max_delay);
-                    pd.cell_arcs.emplace_back(CellArc::HOLD, info.clock_port, DelayQuad(hold_faked, hold_faked),
+                    pd.cell_arcs.emplace_back(CellArc::HOLD, info.clock_port, DelayQuad(info.hold, info.hold),
                                               info.edge);
                 }
             }
@@ -576,7 +574,9 @@ void TimingAnalyser::walk_forward()
                         // Include the clock delay if clock_skew analysis is enabled
                         if (with_clock_skew) {
                             auto clock_delay = ports.at(CellPortKey(sp.first.cell, fanin.other_port)).route_delay;
-                            init_arrival += DelayPair(clock_delay.min_delay);
+                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
+                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
+                            init_arrival += clock_delay;
                         }
                         break;
                     }
@@ -634,12 +634,14 @@ void TimingAnalyser::walk_backward()
                     if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second) {
                         if (with_clock_skew) {
                             auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
-                            init_required -= DelayPair(clock_delay.min_delay);
+                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
+                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
+                            init_required += clock_delay;
                         }
                         init_required.min_delay -= fanin.value.maxDelay();
                     }
                     if (fanin.type == CellArc::HOLD && fanin.other_port == ep.second)
-                        init_required.max_delay -= fanin.value.maxDelay();
+                        init_required.max_delay += fanin.value.maxDelay();
                 }
                 clock_key = CellPortKey(ep.first.cell, ep.second);
             }
@@ -677,31 +679,58 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 
     for (domain_id_t capture_id = 0; capture_id < domain_id_t(domains.size()); ++capture_id) {
         const auto &capture = domains.at(capture_id);
-        const auto &capture_clock = capture.key.clock;
 
         for (auto &ep : capture.endpoints) {
-            auto &port = ports.at(ep.first);
+            auto &ep_port = ports.at(ep.first);
 
-            auto &req = port.required.at(capture_id);
+            auto &req = ep_port.required.at(capture_id);
 
-            for (auto &[launch_id, arr] : port.arrival) {
+            for (auto &[launch_id, arr] : ep_port.arrival) {
+                const auto &launch = domains.at(capture_id);
 
-                // const auto &launch = domains.at(launch_id);
-                // const auto &launch_clock = launch.key.clock;
+                auto dp = domain_pair_id(launch_id, capture_id);
 
-                // auto clocks = std::make_pair(launch_clock, capture_clock);
-                // auto related_clocks = clock_delays.count(clocks) > 0;
+                auto clocks = std::make_pair(launch.key.clock, capture.key.clock);
+                auto same_clock = capture_id == launch_id;
+                auto related_clocks = clock_delays.count(clocks) > 0;
+                delay_t clock_to_clock = 0;
+                if (related_clocks) {
+                    clock_to_clock = clock_delays.at(clocks);
+                }
 
-                // delay_t clock_to_clock = 0;
-                // if (related_clocks) {
-                //     clock_to_clock = clock_delays.at(clocks);
-                // }
+                auto delay = arr.value.maxDelay() - req.value.minDelay() + clock_to_clock;
 
-                auto dp = domain_pair_id(launch_id, capture_id);
-                auto delay = arr.value.maxDelay() - req.value.maxDelay();
+                // If domains are unrelated or not the same clock we need to make sure
+                // to remove the clock delays from the arrival and required times
+                // because the delays have no common reference.
+                if (with_clock_skew && !same_clock && !related_clocks) {
+                    for (auto &fanin : ep_port.cell_arcs) {
+                        if (fanin.type == CellArc::SETUP) {
+                            auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
+                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
+                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
+                            delay += clock_delay.minDelay();
+                        }
+                    }
+
+                    // walk back to startpoint
+                    auto crit_path = walk_crit_path(domain_pair_id(launch_id, capture_id), ep.first, true);
+                    auto &sp = crit_path.back();
+                    auto &sp_port = ports.at(CellPortKey{sp.cell->name, sp.port});
+
+                    for (auto &fanin : sp_port.cell_arcs) {
+                        if (fanin.type == CellArc::CLK_TO_Q) {
+                            auto clock_delay = ports.at(CellPortKey(sp.cell->name, fanin.other_port)).route_delay;
+                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
+                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
+                            delay -= clock_delay.maxDelay();
+                        }
+                    }
+                }
 
-                if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
+                if (!domain_delay.count(dp) || domain_delay.at(dp) < delay) {
                     domain_delay[dp] = delay;
+                }
             }
         }
     }
@@ -825,36 +854,9 @@ std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair,
     return worst_eps;
 }
 
-CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint,
-                                                        bool longest_path)
+std::vector<PortRef> TimingAnalyser::walk_crit_path(domain_id_t domain_pair, CellPortKey endpoint, bool longest_path)
 {
-    CriticalPath report;
-
     const auto &dp = domain_pairs.at(domain_pair);
-    const auto &launch = domains.at(dp.key.launch).key;
-    const auto &capture = domains.at(dp.key.capture).key;
-
-    report.delay = DelayPair(0);
-
-    report.clock_pair.start.clock = launch.clock;
-    report.clock_pair.start.edge = launch.edge;
-    report.clock_pair.end.clock = capture.clock;
-    report.clock_pair.end.edge = capture.edge;
-
-    report.bound = DelayPair(0, ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")));
-    if (launch.edge != capture.edge) {
-        report.bound.max_delay = report.bound.max_delay / 2;
-    }
-
-    if (!launch.is_async() && ctx->nets.at(launch.clock)->clkconstr) {
-        if (launch.edge == capture.edge) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
-        } else if (capture.edge == RISING_EDGE) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
-        } else if (capture.edge == FALLING_EDGE) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
-        }
-    }
 
     // Walk the min or max path backwards to find a single crit path
     pool<std::pair<IdString, IdString>> visited;
@@ -890,6 +892,42 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     } while (!is_startpoint);
 
+    return crit_path_rev;
+}
+
+CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint,
+                                                        bool longest_path)
+{
+    CriticalPath report;
+
+    const auto &dp = domain_pairs.at(domain_pair);
+    const auto &launch = domains.at(dp.key.launch).key;
+    const auto &capture = domains.at(dp.key.capture).key;
+
+    report.delay = DelayPair(0);
+
+    report.clock_pair.start.clock = launch.clock;
+    report.clock_pair.start.edge = launch.edge;
+    report.clock_pair.end.clock = capture.clock;
+    report.clock_pair.end.edge = capture.edge;
+
+    report.bound = DelayPair(0, ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")));
+    if (launch.edge != capture.edge) {
+        report.bound.max_delay = report.bound.max_delay / 2;
+    }
+
+    if (!launch.is_async() && ctx->nets.at(launch.clock)->clkconstr) {
+        if (launch.edge == capture.edge) {
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
+        } else if (capture.edge == RISING_EDGE) {
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
+        } else if (capture.edge == FALLING_EDGE) {
+            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
+        }
+    }
+
+    // Walk the min or max path backwards to find a single crit path
+    auto crit_path_rev = walk_crit_path(domain_pair, endpoint, longest_path);
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
 
     // Get timing and clocking info on the startpoint
@@ -963,13 +1001,12 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     // and either the clock domains are the same or related clock
     if (with_clock_skew && register_start && register_end && (same_clock || related_clock)) {
 
-        auto clock_delay_launch = ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
-        auto clock_delay_capture = ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
+        auto clock_delay_launch =
+                clock_delay_fac * ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
+        auto clock_delay_capture =
+                clock_delay_fac * ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
 
         delay_t clock_skew = clock_delay_launch - clock_delay_capture;
-        printf("delay launch: %f\n", ctx->getDelayNS(clock_delay_launch));
-        printf("delay capture: %f\n", ctx->getDelayNS(clock_delay_capture));
-        printf("clock to clock: %f\n", ctx->getDelayNS(clock_skew));
 
         if (clock_skew != 0) {
             CriticalPath::Segment seg_skew;
@@ -989,6 +1026,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     const CellInfo *prev_cell = sp_cell;
     IdString prev_port = sp_port.name;
 
+    bool is_startpoint = true;
     for (auto sink : crit_path) {
         auto sink_cell = sink.cell;
         auto &port = sink_cell->ports.at(sink.port);
@@ -1188,16 +1226,16 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
         const auto &capture = domains.at(capture_id);
         const auto &capture_clock = capture.key.clock;
 
-        for (auto &ep : capture.endpoints) {
-            CellInfo *ci = cell_info(ep.first);
+        for (const auto &ep : capture.endpoints) {
+            const CellInfo *ci = cell_info(ep.first);
             int clkInfoCount = 0;
-            TimingPortClass cls = ctx->getPortTimingClass(ci, ep.first.port, clkInfoCount);
+            const TimingPortClass cls = ctx->getPortTimingClass(ci, ep.first.port, clkInfoCount);
             if (cls != TMG_REGISTER_INPUT)
                 continue;
 
-            auto &port = ports.at(ep.first);
+            const auto &port = ports.at(ep.first);
 
-            auto &req = port.required.at(capture_id);
+            const auto &req = port.required.at(capture_id);
 
             for (auto &[launch_id, arr] : port.arrival) {
                 const auto &launch = domains.at(launch_id);
@@ -1206,8 +1244,8 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                 auto clocks = std::make_pair(launch_clock, capture_clock);
                 auto related_clocks = clock_delays.count(clocks) > 0;
 
-                // Don't consider clocks without known relationships
-                if (launch_id != capture_id && !related_clocks) {
+                // Don't consider async paths and clocks without known relationships
+                if (launch_id == async_clock_id && launch_id != capture_id && !related_clocks) {
                     continue;
                 }
 
@@ -1216,14 +1254,9 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                     clock_to_clock = clock_delays.at(clocks);
                 }
 
-                auto hold_slack = arr.value.minDelay() + req.value.maxDelay() + clock_to_clock;
+                auto hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
                 auto violated = hold_slack <= 0;
 
-                // printf("arr min: %f, req max: %f, c2c; %f, slack: %f, arr path len: %d, req path len: %d\n",
-                //        ctx->getDelayNS(arr.value.minDelay()), ctx->getDelayNS(req.value.maxDelay()),
-                //        ctx->getDelayNS(clock_to_clock), ctx->getDelayNS(hold_slack), arr.path_length,
-                //        req.path_length);
-
                 if (violated) {
                     const auto dom_pair_id = domain_pair_id(launch_id, capture_id);
                     violations.emplace_back(build_critical_path_report(dom_pair_id, ep.first, false));
@@ -1298,7 +1331,7 @@ void timing_analysis(Context *ctx, bool print_slack_histogram, bool print_fmax,
 {
     TimingAnalyser tmg(ctx);
     tmg.setup_only = false;
-    tmg.with_clock_skew = false;
+    tmg.with_clock_skew = true;
     tmg.setup(ctx->detailed_timing_report, print_slack_histogram, print_path || print_fmax);
 
     auto &result = tmg.get_timing_result();
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index fc60a5ee10..9bba709ee8 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -101,6 +101,8 @@ struct TimingAnalyser
     // Enable analysis of clock skew between FFs.
     // Only do this after legal placement
     bool with_clock_skew = true;
+    // REMOVE ME once approved
+    delay_t clock_delay_fac = 100;
 
     bool setup_only = false;
     bool have_loops = false;
@@ -122,6 +124,10 @@ struct TimingAnalyser
     void compute_slack();
     void compute_criticality();
 
+    // Walk the endpoint back to a startpoint and get back the input ports walked
+    // and the startpoint.
+    std::vector<PortRef> walk_crit_path(domain_id_t domain_pair, CellPortKey endpoint, bool longest_path);
+
     void build_detailed_net_timing_report();
     // longest_path indicate whether to follow the longest or shortest path from endpoint to startpoint
     // longest paths are interesting for setup violations and shortest paths are interesting for hold violations
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index e21fcb3d43..c01b1159b4 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             return ctx->getDelayNS(d.maxDelay());
         };
 
-        log_info("      type  curr  total\n");
+        log_info("      type curr  total\n");
         for (const auto &segment : path.segments) {
 
             total += segment.delay;
@@ -232,9 +232,6 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     // Clock to clock delays for xpaths
     dict<ClockPair, DelayPair> xclock_delays;
     for (auto &report : result.xclock_paths) {
-        const auto &clock1_name = report.clock_pair.start.clock;
-        const auto &clock2_name = report.clock_pair.end.clock;
-
         // Check if this path has a clock-2-clock delay
         // clock-2-clock delays are always the first segment in the path
         // But we walk the entire path anyway.
@@ -265,7 +262,6 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             const auto &clock_a = report.clock_pair.start.clock;
             const auto &clock_b = report.clock_pair.end.clock;
 
-            const auto key = std::make_pair(clock_a, clock_b);
             if (!xclock_delays.count(report.clock_pair)) {
                 continue;
             }

From a7f79fd6811bab5199474c1506ac5eb633a1f71e Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Tue, 17 Sep 2024 22:14:13 +0200
Subject: [PATCH 655/712] timing: minor cleanup and stupid mistake fixups

---
 common/kernel/nextpnr_types.h |  6 +++---
 common/kernel/timing.cc       | 20 ++++++--------------
 common/kernel/timing_log.cc   | 12 ++++++------
 3 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index ff3b656fba..c806c1869f 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -447,11 +447,11 @@ struct CriticalPath
     // Clock pair
     ClockPair clock_pair;
     // Total path delay
+    // if sum < 0 this is a hold/min violation
+    // if delay.maxDelay() >= max_delay this is a setup/max violation
     DelayPair delay;
 
-    // if delay.minDelay() < bound.minDelay() then this is a hold violation
-    // if delay.maxDelay() > bound.maxDelay() then this is a setup violation
-    DelayPair bound;
+    delay_t max_delay;
 
     // Individual path segments
     std::vector<Segment> segments;
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 008eff504d..7504ead273 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -911,22 +911,21 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     report.clock_pair.end.clock = capture.clock;
     report.clock_pair.end.edge = capture.edge;
 
-    report.bound = DelayPair(0, ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")));
+    report.max_delay = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
     if (launch.edge != capture.edge) {
-        report.bound.max_delay = report.bound.max_delay / 2;
+        report.max_delay = report.max_delay / 2;
     }
 
     if (!launch.is_async() && ctx->nets.at(launch.clock)->clkconstr) {
         if (launch.edge == capture.edge) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
+            report.max_delay = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
         } else if (capture.edge == RISING_EDGE) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
+            report.max_delay = ctx->nets.at(launch.clock)->clkconstr->low.minDelay();
         } else if (capture.edge == FALLING_EDGE) {
-            report.bound.max_delay = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
+            report.max_delay = ctx->nets.at(launch.clock)->clkconstr->high.minDelay();
         }
     }
 
-    // Walk the min or max path backwards to find a single crit path
     auto crit_path_rev = walk_crit_path(domain_pair, endpoint, longest_path);
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
 
@@ -997,8 +996,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         }
     }
 
-    // Calculate clock skew only if start- and endpoint are registered
-    // and either the clock domains are the same or related clock
     if (with_clock_skew && register_start && register_end && (same_clock || related_clock)) {
 
         auto clock_delay_launch =
@@ -1070,8 +1067,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         is_startpoint = false;
     }
 
-    // Add setup/hold time as final segment
-    // And add hold time as min bound
     if (register_end) {
         CriticalPath::Segment seg_logic;
         seg_logic.delay = DelayPair(0);
@@ -1086,8 +1081,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         seg_logic.to = seg_logic.from;
         seg_logic.net = IdString();
         report.segments.push_back(seg_logic);
-
-        report.bound.min_delay = ep_clk_info.hold.min_delay;
     }
 
     return report;
@@ -1244,8 +1237,7 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                 auto clocks = std::make_pair(launch_clock, capture_clock);
                 auto related_clocks = clock_delays.count(clocks) > 0;
 
-                // Don't consider async paths and clocks without known relationships
-                if (launch_id == async_clock_id && launch_id != capture_id && !related_clocks) {
+                if (launch_id == async_clock_id || (launch_id != capture_id && !related_clocks)) {
                     continue;
                 }
 
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index c01b1159b4..77db543b91 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -74,9 +74,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
         // We print out the max delay since that's usually the interesting case
         // But if we know this critical path has violated hold time we print the
         // min delay instead
-        bool hold_violation = path.delay.minDelay() < path.bound.minDelay();
-        auto get_delay_ns = [hold_violation, ctx](const DelayPair &d) {
-            if (hold_violation) {
+        bool min_delay_violation = path.delay.minDelay() < 0;
+        auto get_delay_ns = [min_delay_violation, ctx](const DelayPair &d) {
+            if (min_delay_violation) {
                 ctx->getDelayNS(d.minDelay());
             }
             return ctx->getDelayNS(d.maxDelay());
@@ -180,16 +180,16 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
     auto num_min_violations = result.min_delay_violations.size();
     if (num_min_violations > 0) {
         log_break();
-        log_info("Hold time/min time violation:\n");
+        log_info("Hold time/min time violations:\n");
         for (size_t i = 0; i < std::min((size_t)10, num_min_violations); ++i) {
             auto &report = result.min_delay_violations.at(i);
             log_break();
             std::string start = clock_event_name(ctx, report.clock_pair.start);
             std::string end = clock_event_name(ctx, report.clock_pair.end);
             if (report.clock_pair.start == report.clock_pair.end) {
-                log_nonfatal_error("Hold time violations for clock '%s':\n", start.c_str());
+                log_nonfatal_error("Hold time violation for clock '%s':\n", start.c_str());
             } else {
-                log_nonfatal_error("Hold time violations for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+                log_nonfatal_error("Hold time violation for path '%s' -> '%s':\n", start.c_str(), end.c_str());
             }
             print_path_report(report);
         }

From 8ee2c5612cf41d8a94615c3f7316695b35270baa Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Wed, 18 Sep 2024 00:33:33 +0200
Subject: [PATCH 656/712] timing: Add safe zero check function for delay_t

---
 common/kernel/nextpnr_types.h | 10 ++++++++++
 common/kernel/timing.cc       |  4 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index c806c1869f..095329c772 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -78,6 +78,16 @@ struct PortRef
     IdString port;
 };
 
+// Zero checking which works regardless if delay_t is floating or integer
+inline bool is_zero_delay(delay_t delay)
+{
+    if constexpr (std::is_floating_point<delay_t>::value) {
+        return std::fpclassify(delay) == FP_ZERO;
+    } else {
+        return delay == 0;
+    }
+}
+
 // minimum and maximum delay
 struct DelayPair
 {
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7504ead273..ce4ef9a0b4 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -985,7 +985,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
     if (related_clock) {
         delay_t clock_delay = clock_delays.at(clock_pair);
-        if (clock_delay != 0) {
+        if (!is_zero_delay(clock_delay)) {
             CriticalPath::Segment seg_c2c;
             seg_c2c.type = CriticalPath::Segment::Type::CLK_TO_CLK;
             seg_c2c.delay = DelayPair(clock_delay);
@@ -1005,7 +1005,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
         delay_t clock_skew = clock_delay_launch - clock_delay_capture;
 
-        if (clock_skew != 0) {
+        if (!is_zero_delay(clock_skew)) {
             CriticalPath::Segment seg_skew;
             seg_skew.type = CriticalPath::Segment::Type::CLK_SKEW;
             seg_skew.delay = DelayPair(clock_skew);

From 5488cd994b03caae5b077fbfb74e2acf3cb90104 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 19 Sep 2024 15:24:45 +0200
Subject: [PATCH 657/712] router: Enable clock skew analysis during routing

---
 common/route/router1.cc | 2 ++
 common/route/router2.cc | 7 ++++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/route/router1.cc b/common/route/router1.cc
index a3ebdb60c1..510065f611 100644
--- a/common/route/router1.cc
+++ b/common/route/router1.cc
@@ -124,6 +124,8 @@ struct Router1
     Router1(Context *ctx, const Router1Cfg &cfg) : ctx(ctx), cfg(cfg), tmg(ctx)
     {
         timing_driven = ctx->setting<bool>("timing_driven");
+        tmg.setup_only = false;
+        tmg.with_clock_skew = true;
         tmg.setup();
         tmg.run();
     }
diff --git a/common/route/router2.cc b/common/route/router2.cc
index 8dcec6e91c..53596c24af 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -102,7 +102,12 @@ struct Router2
     Context *ctx;
     Router2Cfg cfg;
 
-    Router2(Context *ctx, const Router2Cfg &cfg) : ctx(ctx), cfg(cfg), tmg(ctx) { tmg.setup(); }
+    Router2(Context *ctx, const Router2Cfg &cfg) : ctx(ctx), cfg(cfg), tmg(ctx)
+    {
+        tmg.setup_only = false;
+        tmg.with_clock_skew = true;
+        tmg.setup();
+    }
 
     // Use 'udata' for fast net lookups and indexing
     std::vector<NetInfo *> nets_by_udata;

From 25d64b210532fa70d1dab20f2008f5307565be49 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 19 Sep 2024 17:23:41 +0200
Subject: [PATCH 658/712] timing_log: Fix logging indendation to match master
 timing: Disable clock_skew analysis by default

---
 common/kernel/timing.cc     | 13 +++++++------
 common/kernel/timing.h      |  4 ++--
 common/kernel/timing_log.cc | 12 ++++++------
 3 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index ce4ef9a0b4..7ca6c3d22c 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -715,7 +715,8 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
 
                     // walk back to startpoint
                     auto crit_path = walk_crit_path(domain_pair_id(launch_id, capture_id), ep.first, true);
-                    auto &sp = crit_path.back();
+                    auto first_inp = crit_path.back();
+                    const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver;
                     auto &sp_port = ports.at(CellPortKey{sp.cell->name, sp.port});
 
                     for (auto &fanin : sp_port.cell_arcs) {
@@ -877,9 +878,8 @@ std::vector<PortRef> TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel
         // We store the reversed critical path as all input ports that lead to
         // the timing startpoint.
         auto is_input = portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN;
-        is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT;
 
-        if (is_input || is_startpoint)
+        if (is_input)
             crit_path_rev.emplace_back(PortRef{cell, port.name});
 
         if (!ports.at(cursor).arrival.count(dp.key.launch))
@@ -890,6 +890,7 @@ std::vector<PortRef> TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel
         } else {
             cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_min;
         }
+        is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT;
     } while (!is_startpoint);
 
     return crit_path_rev;
@@ -930,7 +931,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     auto crit_path = boost::adaptors::reverse(crit_path_rev);
 
     // Get timing and clocking info on the startpoint
-    const auto &sp = crit_path.front();
+    auto first_inp = crit_path.front();
+    const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver;
     const auto &sp_cell = sp.cell;
     const auto &sp_port = sp_cell->ports.at(sp.port);
     int sp_clocks;
@@ -1037,8 +1039,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (is_startpoint && register_start) {
             comb_delay = sp_clk_info.clockToQ;
             seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
-        } else if (prev_port == driver.port) {
-            // Case where we start with a STARTPOINT etc
+        } else if (is_startpoint) {
             comb_delay = DelayQuad(0);
             seg_logic.type = CriticalPath::Segment::Type::SOURCE;
         } else {
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index 9bba709ee8..a6222a2ed0 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -99,8 +99,8 @@ struct TimingAnalyser
     TimingResult &get_timing_result() { return result; }
 
     // Enable analysis of clock skew between FFs.
-    // Only do this after legal placement
-    bool with_clock_skew = true;
+    bool with_clock_skew = false;
+
     // REMOVE ME once approved
     delay_t clock_delay_fac = 100;
 
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 77db543b91..825d209c6c 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -61,9 +61,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
         source_entries.emplace_back(sourcelist.substr(prev, current - prev));
 
         // Iterate and print our source list at the correct indentation level
-        log_info("                          Defined in:\n");
+        log_info("                         Defined in:\n");
         for (auto entry : source_entries) {
-            log_info("                            %s\n", entry.c_str());
+            log_info("                              %s\n", entry.c_str());
         }
     };
 
@@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             return ctx->getDelayNS(d.maxDelay());
         };
 
-        log_info("      type curr  total\n");
+        log_info("      type curr  total name\n");
         for (const auto &segment : path.segments) {
 
             total += segment.delay;
@@ -94,7 +94,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 segment.type == CriticalPath::Segment::Type::HOLD) {
                 logic_total += segment.delay;
 
-                log_info("%10s % 5.2f % 5.2f  %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
+                log_info("%10s % 5.2f % 5.2f Source %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
                          get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
@@ -108,11 +108,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto driver_loc = ctx->getBelLocation(driver->bel);
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
-                log_info("%10s % 5.2f % 5.2f  Net %s (%d,%d) -> (%d,%d)\n",
+                log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n",
                          CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay),
                          get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
                          sink_loc.y);
-                log_info("                          Sink %s.%s\n", segment.to.first.c_str(ctx),
+                log_info("                         Sink %s.%s\n", segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
 
                 const NetInfo *net = ctx->nets.at(segment.net).get();

From 0fce4b8f4ecb0f60e4bd268df06515c903c90bd7 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 19 Sep 2024 17:24:36 +0200
Subject: [PATCH 659/712] timing: lower clock_delay_fact to 1 to check if CI
 passes

---
 common/kernel/timing.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index a6222a2ed0..ce6859c764 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -102,7 +102,7 @@ struct TimingAnalyser
     bool with_clock_skew = false;
 
     // REMOVE ME once approved
-    delay_t clock_delay_fac = 100;
+    delay_t clock_delay_fac = 1;
 
     bool setup_only = false;
     bool have_loops = false;

From 098dcaedece720bdacab64909977d26cdb0479a8 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Thu, 19 Sep 2024 18:15:53 +0200
Subject: [PATCH 660/712] timing: remove the articial clock delay inflation

---
 common/kernel/timing.cc | 20 ++++----------------
 common/kernel/timing.h  |  3 ---
 2 files changed, 4 insertions(+), 19 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7ca6c3d22c..46a44fa40c 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -573,10 +573,7 @@ void TimingAnalyser::walk_forward()
                         init_arrival += fanin.value.delayPair();
                         // Include the clock delay if clock_skew analysis is enabled
                         if (with_clock_skew) {
-                            auto clock_delay = ports.at(CellPortKey(sp.first.cell, fanin.other_port)).route_delay;
-                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
-                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
-                            init_arrival += clock_delay;
+                            init_arrival += ports.at(CellPortKey(sp.first.cell, fanin.other_port)).route_delay;
                         }
                         break;
                     }
@@ -633,10 +630,7 @@ void TimingAnalyser::walk_backward()
 
                     if (fanin.type == CellArc::SETUP && fanin.other_port == ep.second) {
                         if (with_clock_skew) {
-                            auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
-                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
-                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
-                            init_required += clock_delay;
+                            init_required += ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
                         }
                         init_required.min_delay -= fanin.value.maxDelay();
                     }
@@ -707,8 +701,6 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
                     for (auto &fanin : ep_port.cell_arcs) {
                         if (fanin.type == CellArc::SETUP) {
                             auto clock_delay = ports.at(CellPortKey(ep.first.cell, fanin.other_port)).route_delay;
-                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
-                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
                             delay += clock_delay.minDelay();
                         }
                     }
@@ -722,8 +714,6 @@ dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
                     for (auto &fanin : sp_port.cell_arcs) {
                         if (fanin.type == CellArc::CLK_TO_Q) {
                             auto clock_delay = ports.at(CellPortKey(sp.cell->name, fanin.other_port)).route_delay;
-                            clock_delay.min_delay = clock_delay_fac * clock_delay.min_delay;
-                            clock_delay.max_delay = clock_delay_fac * clock_delay.max_delay;
                             delay -= clock_delay.maxDelay();
                         }
                     }
@@ -1000,10 +990,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
     if (with_clock_skew && register_start && register_end && (same_clock || related_clock)) {
 
-        auto clock_delay_launch =
-                clock_delay_fac * ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
-        auto clock_delay_capture =
-                clock_delay_fac * ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
+        auto clock_delay_launch = ctx->getNetinfoRouteDelay(sp_clk_net, PortRef{sp_cell, sp_clk_info.clock_port});
+        auto clock_delay_capture = ctx->getNetinfoRouteDelay(ep_clk_net, PortRef{ep_cell, ep_clk_info.clock_port});
 
         delay_t clock_skew = clock_delay_launch - clock_delay_capture;
 
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index ce6859c764..f82a1b6da6 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -101,9 +101,6 @@ struct TimingAnalyser
     // Enable analysis of clock skew between FFs.
     bool with_clock_skew = false;
 
-    // REMOVE ME once approved
-    delay_t clock_delay_fac = 1;
-
     bool setup_only = false;
     bool have_loops = false;
     bool updated_domains = false;

From 93e233dad9f686d2e21f0c29fb652653cac3dec9 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Fri, 20 Sep 2024 19:08:00 +0200
Subject: [PATCH 661/712] timing: Fix hold slack not matching reported path
 delay

---
 common/kernel/nextpnr_types.h |  8 ++---
 common/kernel/report.cc       | 15 ++++------
 common/kernel/timing.cc       | 47 +++++++++++++++++++++---------
 common/kernel/timing_log.cc   | 55 +++++++++++++++--------------------
 4 files changed, 65 insertions(+), 60 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index 095329c772..ebbdba0204 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -451,16 +451,14 @@ struct CriticalPath
         // To cell.port
         std::pair<IdString, IdString> to;
         // Segment delay
-        DelayPair delay;
+        delay_t delay;
     };
 
     // Clock pair
     ClockPair clock_pair;
-    // Total path delay
-    // if sum < 0 this is a hold/min violation
-    // if delay.maxDelay() >= max_delay this is a setup/max violation
-    DelayPair delay;
 
+    // if sum[segments.delay] < 0 this is a hold/min violation
+    // if sum[segments.delay] > max_delay this is a setup/max violation
     delay_t max_delay;
 
     // Individual path segments
diff --git a/common/kernel/report.cc b/common/kernel/report.cc
index cd5b11722e..d8c78881e0 100644
--- a/common/kernel/report.cc
+++ b/common/kernel/report.cc
@@ -73,11 +73,11 @@ static Json::array json_report_critical_paths(const Context *ctx)
                                         {"port", segment.to.second.c_str(ctx)},
                                         {"loc", Json::array({toLoc.x, toLoc.y})}});
 
-            auto minDelay = ctx->getDelayNS(segment.delay.minDelay());
-            auto maxDelay = ctx->getDelayNS(segment.delay.maxDelay());
-
-            auto segmentJson =
-                    Json::object({{"delay", Json::array({minDelay, maxDelay})}, {"from", fromJson}, {"to", toJson}});
+            auto segmentJson = Json::object({
+                    {"delay", ctx->getDelayNS(segment.delay)},
+                    {"from", fromJson},
+                    {"to", toJson},
+            });
 
             segmentJson["type"] = CriticalPath::Segment::type_to_str(segment.type);
             if (segment.type == CriticalPath::Segment::Type::ROUTING) {
@@ -186,10 +186,7 @@ Report JSON structure:
           },
           "type": <path segment type "clk-to-q", "source", "logic", "routing" or "setup">,
           "net": <net name (for routing only!)>,
-          "delay": [
-            <minimum segment delay [ns]>,
-            <maximum segment delay [ns]>,
-          ],
+          "delay": <segment delay [ns]>,
         }
         ...
       ]
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 46a44fa40c..ee1a55c2a9 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -895,8 +895,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
     const auto &launch = domains.at(dp.key.launch).key;
     const auto &capture = domains.at(dp.key.capture).key;
 
-    report.delay = DelayPair(0);
-
     report.clock_pair.start.clock = launch.clock;
     report.clock_pair.start.edge = launch.edge;
     report.clock_pair.end.clock = capture.clock;
@@ -980,7 +978,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (!is_zero_delay(clock_delay)) {
             CriticalPath::Segment seg_c2c;
             seg_c2c.type = CriticalPath::Segment::Type::CLK_TO_CLK;
-            seg_c2c.delay = DelayPair(clock_delay);
+            seg_c2c.delay = clock_delay;
             seg_c2c.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
             seg_c2c.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
             seg_c2c.net = IdString();
@@ -998,7 +996,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
         if (!is_zero_delay(clock_skew)) {
             CriticalPath::Segment seg_skew;
             seg_skew.type = CriticalPath::Segment::Type::CLK_SKEW;
-            seg_skew.delay = DelayPair(clock_skew);
+            seg_skew.delay = clock_skew;
             seg_skew.from = std::make_pair(sp_cell->name, sp_clk_info.clock_port);
             seg_skew.to = std::make_pair(ep_cell->name, ep_clk_info.clock_port);
             if (same_clock) {
@@ -1035,7 +1033,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
             seg_logic.type = CriticalPath::Segment::Type::LOGIC;
         }
 
-        seg_logic.delay = comb_delay.delayPair();
+        seg_logic.delay = longest_path ? comb_delay.maxDelay() : comb_delay.minDelay();
         seg_logic.from = std::make_pair(prev_cell->name, prev_port);
         seg_logic.to = std::make_pair(driver_cell->name, driver.port);
         seg_logic.net = IdString();
@@ -1045,7 +1043,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
         CriticalPath::Segment seg_route;
         seg_route.type = CriticalPath::Segment::Type::ROUTING;
-        seg_route.delay = net_delay;
+        seg_route.delay = longest_path ? net_delay.maxDelay() : net_delay.minDelay();
         seg_route.from = std::make_pair(driver_cell->name, driver.port);
         seg_route.to = std::make_pair(sink_cell->name, sink.port);
         seg_route.net = net->name;
@@ -1058,13 +1056,13 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
 
     if (register_end) {
         CriticalPath::Segment seg_logic;
-        seg_logic.delay = DelayPair(0);
+        seg_logic.delay = 0;
         if (longest_path) {
             seg_logic.type = CriticalPath::Segment::Type::SETUP;
-            seg_logic.delay += ep_clk_info.setup;
+            seg_logic.delay += ep_clk_info.setup.maxDelay();
         } else {
             seg_logic.type = CriticalPath::Segment::Type::HOLD;
-            seg_logic.delay -= ep_clk_info.hold;
+            seg_logic.delay -= ep_clk_info.hold.maxDelay();
         }
         seg_logic.from = std::make_pair(prev_cell->name, prev_port);
         seg_logic.to = seg_logic.from;
@@ -1222,6 +1220,7 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
             for (auto &[launch_id, arr] : port.arrival) {
                 const auto &launch = domains.at(launch_id);
                 const auto &launch_clock = launch.key.clock;
+                const auto dom_pair_id = domain_pair_id(launch_id, capture_id);
 
                 auto clocks = std::make_pair(launch_clock, capture_clock);
                 auto related_clocks = clock_delays.count(clocks) > 0;
@@ -1236,17 +1235,37 @@ std::vector<CriticalPath> TimingAnalyser::get_min_delay_violations()
                 }
 
                 auto hold_slack = arr.value.minDelay() - req.value.maxDelay() + clock_to_clock;
-                auto violated = hold_slack <= 0;
 
-                if (violated) {
-                    const auto dom_pair_id = domain_pair_id(launch_id, capture_id);
-                    violations.emplace_back(build_critical_path_report(dom_pair_id, ep.first, false));
+                if (hold_slack <= 0) {
+                    auto report = build_critical_path_report(dom_pair_id, ep.first, false);
+                    violations.emplace_back(report);
                 }
             }
         }
     }
 
-    return violations;
+    std::vector<std::pair<size_t, delay_t>> sum_indices;
+    sum_indices.reserve(violations.size());
+
+    for (size_t i = 0; i < violations.size(); ++i) {
+        delay_t delay = 0;
+        for (const auto &seg : violations[i].segments) {
+            delay += seg.delay;
+        }
+
+        sum_indices.emplace_back(i, delay);
+    }
+
+    std::sort(sum_indices.begin(), sum_indices.end(),
+              [](auto &left, auto &right) { return left.second < right.second; });
+
+    std::vector<CriticalPath> sorted_violations;
+    sorted_violations.reserve(violations.size());
+    for (const auto &pair : sum_indices) {
+        sorted_violations.push_back(std::move(violations[pair.first]));
+    }
+
+    return sorted_violations;
 }
 
 domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 825d209c6c..9db39e48a4 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -69,38 +69,29 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
 
     // A helper function for reporting one critical path
     auto print_path_report = [ctx](const CriticalPath &path) {
-        DelayPair total(0), logic_total(0), route_total(0);
-
-        // We print out the max delay since that's usually the interesting case
-        // But if we know this critical path has violated hold time we print the
-        // min delay instead
-        bool min_delay_violation = path.delay.minDelay() < 0;
-        auto get_delay_ns = [min_delay_violation, ctx](const DelayPair &d) {
-            if (min_delay_violation) {
-                ctx->getDelayNS(d.minDelay());
-            }
-            return ctx->getDelayNS(d.maxDelay());
-        };
+        delay_t total(0), logic_total(0), route_total(0);
 
         log_info("      type curr  total name\n");
         for (const auto &segment : path.segments) {
 
-            total += segment.delay;
+            delay_t delay = segment.delay;
+
+            total += delay;
 
             if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
                 segment.type == CriticalPath::Segment::Type::SOURCE ||
                 segment.type == CriticalPath::Segment::Type::LOGIC ||
                 segment.type == CriticalPath::Segment::Type::SETUP ||
                 segment.type == CriticalPath::Segment::Type::HOLD) {
-                logic_total += segment.delay;
+                logic_total += delay;
 
                 log_info("%10s % 5.2f % 5.2f Source %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(),
-                         get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx),
+                         ctx->getDelayNS(delay), ctx->getDelayNS(total), segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
             } else if (segment.type == CriticalPath::Segment::Type::ROUTING ||
                        segment.type == CriticalPath::Segment::Type::CLK_TO_CLK ||
                        segment.type == CriticalPath::Segment::Type::CLK_SKEW) {
-                route_total = route_total + segment.delay;
+                route_total = route_total + delay;
 
                 const auto &driver = ctx->cells.at(segment.from.first);
                 const auto &sink = ctx->cells.at(segment.to.first);
@@ -109,8 +100,8 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 auto sink_loc = ctx->getBelLocation(sink->bel);
 
                 log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n",
-                         CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay),
-                         get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
+                         CriticalPath::Segment::type_to_str(segment.type).c_str(), ctx->getDelayNS(delay),
+                         ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
                          sink_loc.y);
                 log_info("                         Sink %s.%s\n", segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
@@ -150,7 +141,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 }
             }
         }
-        log_info("%.2f ns logic, %.2f ns routing\n", get_delay_ns(logic_total), get_delay_ns(route_total));
+        log_info("%.2f ns logic, %.2f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
     };
 
     // Single domain paths
@@ -180,16 +171,16 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
     auto num_min_violations = result.min_delay_violations.size();
     if (num_min_violations > 0) {
         log_break();
-        log_info("Hold time/min time violations:\n");
+        log_info("%zu Hold/min time violations (showing 10 worst paths):\n", num_min_violations);
         for (size_t i = 0; i < std::min((size_t)10, num_min_violations); ++i) {
             auto &report = result.min_delay_violations.at(i);
             log_break();
             std::string start = clock_event_name(ctx, report.clock_pair.start);
             std::string end = clock_event_name(ctx, report.clock_pair.end);
             if (report.clock_pair.start == report.clock_pair.end) {
-                log_nonfatal_error("Hold time violation for clock '%s':\n", start.c_str());
+                log_nonfatal_error("Hold/min time violation for clock '%s':\n", start.c_str());
             } else {
-                log_nonfatal_error("Hold time violation for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+                log_nonfatal_error("Hold/min time violation for path '%s' -> '%s':\n", start.c_str(), end.c_str());
             }
             print_path_report(report);
         }
@@ -230,13 +221,13 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     log_break();
 
     // Clock to clock delays for xpaths
-    dict<ClockPair, DelayPair> xclock_delays;
+    dict<ClockPair, delay_t> xclock_delays;
     for (auto &report : result.xclock_paths) {
         // Check if this path has a clock-2-clock delay
         // clock-2-clock delays are always the first segment in the path
         // But we walk the entire path anyway.
         bool has_clock_to_clock = false;
-        DelayPair clock_delay = DelayPair(0);
+        delay_t clock_delay = 0;
         for (const auto &seg : report.segments) {
             if (seg.type == CriticalPath::Segment::Type::CLK_TO_CLK) {
                 has_clock_to_clock = true;
@@ -266,7 +257,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
                 continue;
             }
 
-            DelayPair path_delay(0);
+            delay_t path_delay = 0;
             for (const auto &segment : report.segments) {
                 path_delay += segment.delay;
             }
@@ -277,10 +268,10 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             auto clock_delay = xclock_delays.at(report.clock_pair);
 
             float fmax = std::numeric_limits<float>::infinity();
-            if (path_delay.maxDelay() < 0) {
-                fmax = 1e3f / ctx->getDelayNS(clock_delay.maxDelay());
-            } else if (path_delay.maxDelay() > 0) {
-                fmax = 1e3f / ctx->getDelayNS(path_delay.maxDelay());
+            if (path_delay < 0) {
+                fmax = 1e3f / ctx->getDelayNS(clock_delay);
+            } else if (path_delay > 0) {
+                fmax = 1e3f / ctx->getDelayNS(path_delay);
             }
 
             // Both clocks are related so they should have the same
@@ -322,7 +313,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             auto ev_a = clock_event_name(ctx, pair.first.start, max_width_xca);
             auto ev_b = clock_event_name(ctx, pair.first.end, max_width_xcb);
 
-            delay_t delay = pair.second.maxDelay();
+            delay_t delay = pair.second;
             if (pair.first.start.edge != pair.first.end.edge) {
                 delay /= 2;
             }
@@ -348,12 +339,12 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
     for (auto &report : result.xclock_paths) {
         const ClockEvent &a = report.clock_pair.start;
         const ClockEvent &b = report.clock_pair.end;
-        DelayPair path_delay(0);
+        delay_t path_delay = 0;
         for (const auto &segment : report.segments) {
             path_delay += segment.delay;
         }
         auto ev_a = clock_event_name(ctx, a, start_field_width), ev_b = clock_event_name(ctx, b, end_field_width);
-        log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay.maxDelay()));
+        log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
     }
     log_break();
 }

From 0af42f1218afe92d2605bb8180a75915a6bf8ed7 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Mon, 23 Sep 2024 16:14:40 +0200
Subject: [PATCH 662/712] common: Use `NPNR_ASSERT_FALSE` for unreachable case

---
 common/kernel/nextpnr_types.h | 9 ++++-----
 common/kernel/timing.cc       | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index ebbdba0204..e23cd16a35 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -30,7 +30,6 @@
 #include "archdefs.h"
 #include "hashlib.h"
 #include "indexed_store.h"
-#include "log.h"
 #include "nextpnr_base_types.h"
 #include "nextpnr_namespaces.h"
 #include "property.h"
@@ -201,7 +200,7 @@ enum PortType
     case PORT_INOUT:
         return "PORT_INOUT";
     default:
-        log_error("Impossible PortType");
+        NPNR_ASSERT_FALSE("Impossible PortType");
     }
 }
 
@@ -250,7 +249,7 @@ enum TimingPortClass
     case TMG_IGNORE:
         return "TMG_IGNORE";
     default:
-        log_error("Impossible TimingPortClass");
+        NPNR_ASSERT_FALSE("Impossible TimingPortClass");
     }
 }
 
@@ -268,7 +267,7 @@ enum ClockEdge
     case FALLING_EDGE:
         return "FALLING_EDGE";
     default:
-        log_error("Impossible ClockEdge");
+        NPNR_ASSERT_FALSE("Impossible ClockEdge");
     }
 }
 
@@ -438,7 +437,7 @@ struct CriticalPath
             case Type::HOLD:
                 return "hold";
             default:
-                log_error("Impossible Segment::Type");
+                NPNR_ASSERT_FALSE("Impossible Segment::Type");
             }
         }
 
diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index ee1a55c2a9..880cc50691 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -1318,7 +1318,7 @@ const std::string TimingAnalyser::arcType_to_str(CellArc::ArcType typ)
     case TimingAnalyser::CellArc::ENDPOINT:
         return "ENDPOINT";
     default:
-        log_error("Impossible CellArc::ArcType\n");
+        NPNR_ASSERT_FALSE("Impossible CellArc::ArcType\n");
     }
 }
 

From bbdf7aacb0296cff76e49f8975e5faa737d00252 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Mon, 23 Sep 2024 16:47:39 +0200
Subject: [PATCH 663/712] timing_log: warn on min time violation when timing
 fail is allowed

---
 common/kernel/timing_log.cc | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index 9db39e48a4..d0dd8986ba 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -169,6 +169,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
     // Min delay violated paths
     // Show maximum of 10
     auto num_min_violations = result.min_delay_violations.size();
+    bool allow_fail = bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false);
     if (num_min_violations > 0) {
         log_break();
         log_info("%zu Hold/min time violations (showing 10 worst paths):\n", num_min_violations);
@@ -177,11 +178,20 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
             log_break();
             std::string start = clock_event_name(ctx, report.clock_pair.start);
             std::string end = clock_event_name(ctx, report.clock_pair.end);
+
+            std::string message;
             if (report.clock_pair.start == report.clock_pair.end) {
-                log_nonfatal_error("Hold/min time violation for clock '%s':\n", start.c_str());
+                message = "Hold/min time violation for clock '" + start + "':\n";
+            } else {
+                message = "Hold/min time violation for path '" + start + "' -> '" + end + "':\n";
+            }
+
+            if (allow_fail) {
+                log_warning("%s", message.c_str());
             } else {
-                log_nonfatal_error("Hold/min time violation for path '%s' -> '%s':\n", start.c_str(), end.c_str());
+                log_nonfatal_error("%s", message.c_str());
             }
+
             print_path_report(report);
         }
     }
@@ -191,6 +201,8 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
 {
     log_break();
 
+    bool allow_fail = bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false);
+
     if (result.clock_paths.empty() && result.clock_paths.empty()) {
         log_info("No Fmax available; no interior timing paths found in design.\n");
         return;
@@ -211,7 +223,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
         if (!warn_on_failure || passed)
             log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(),
                      fmax, passed ? "PASS" : "FAIL", target);
-        else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+        else if (allow_fail)
             log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(),
                         fmax, passed ? "PASS" : "FAIL", target);
         else
@@ -296,8 +308,7 @@ static void log_fmax(Context *ctx, TimingResult &result, bool warn_on_failure)
             if (!warn_on_failure || passed)
                 log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(), fmax,
                          passed ? "PASS" : "FAIL", target);
-            else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
-                     bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
+            else if (allow_fail || bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
                 log_warning("Max frequency for  %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
                             fmax, passed ? "PASS" : "FAIL", target);
             else

From db0c99199e7bff7a23f46dc2fa2d8f0793ef6532 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Wed, 11 Sep 2024 18:57:12 +0200
Subject: [PATCH 664/712] Himbaechel xilinx : Add support of DSP packing for
 7-series

---
 himbaechel/uarch/xilinx/pack.cc         |   2 +-
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 165 ++++++++++++++++++++++++
 2 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 himbaechel/uarch/xilinx/pack_dsp_xc7.cc

diff --git a/himbaechel/uarch/xilinx/pack.cc b/himbaechel/uarch/xilinx/pack.cc
index a40ccbd387..a219fbf46c 100644
--- a/himbaechel/uarch/xilinx/pack.cc
+++ b/himbaechel/uarch/xilinx/pack.cc
@@ -742,7 +742,7 @@ void XilinxImpl::pack()
     packer.pack_luts();
     packer.pack_dram();
     packer.pack_bram();
-    // packer.pack_dsps();
+    packer.pack_dsps();
     packer.pack_ffs();
     packer.finalise_muxfs();
     packer.pack_lutffs();
diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
new file mode 100644
index 0000000000..9faffedd4e
--- /dev/null
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -0,0 +1,165 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2020  Myrtle Shah <gatecat@ds0.me>
+ *  Copyright (C) 2023  Hans Baier <hansfbaier@gmail.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include "pack.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
+{
+    CellInfo *cascaded_cell = nullptr;
+
+    auto check_illegal_fanout = [&] (NetInfo *ni, std::string port) {
+        if (ni->users.entries() > 1)
+            log_error("Port %s connected to net %s has more than one user", port.c_str(), ni->name.c_str(ctx));
+
+        PortRef& user = *ni->users.begin();
+        if (user.cell->type != id_DSP48E1_DSP48E1)
+            log_error("User %s of net %s is not a DSP block, but %s",
+                user.cell->name.c_str(ctx), ni->name.c_str(ctx), user.cell->type.c_str(ctx));
+    };
+
+    // see if any cascade outputs are connected
+    for (auto port : current_cell->ports) {
+        if (!boost::contains(port.first.str(ctx), "COUT")) continue;
+        NetInfo *cout_net = port.second.net;
+
+        if (cout_net == nullptr) continue;
+
+        check_illegal_fanout(cout_net, port.first.c_str(ctx));
+        PortRef& user = *cout_net->users.begin();
+        CellInfo *cout_cell = user.cell;
+        NPNR_ASSERT(cout_cell != nullptr);
+
+        if (cascaded_cell != nullptr && cout_cell != cascaded_cell)
+            log_error("the cascading outputs of DSP block %s are connected to different cells",
+                current_cell->name.c_str(ctx));
+
+        cascaded_cell = cout_cell;
+    }
+
+    if (cascaded_cell != nullptr) {
+        auto is_lower_bel = constr_z == BEL_LOWER_DSP;
+
+        cascaded_cell->cluster = root->name;
+        root->constr_children.push_back(cascaded_cell);
+        cascaded_cell->constr_x = 0;
+        // the connected cell has to be above the current cell,
+        // otherwise it cannot be routed, because the cascading ports
+        // are only connected to the DSP above
+        auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
+        cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
+        cascaded_cell->constr_z = constr_z;
+        cascaded_cell->constr_abs_z = true;
+
+        walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
+    }
+}
+
+void XC7Packer::pack_dsps()
+{
+    log_info("Packing DSPs..\n");
+
+    dict<IdString, XFormRule> dsp_rules;
+    dsp_rules[id_DSP48E1].new_type = id_DSP48E1_DSP48E1;
+    generic_xform(dsp_rules, true);
+
+    std::vector<CellInfo *> all_dsps;
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+
+        auto add_const_pin = [&](PortInfo& port, std::string& pins, std::string& pin_name, std::string net) {
+            if (port.net && port.net->name == ctx->id(net)) {
+                ci->disconnectPort(port.name);
+                pins += " " + pin_name;
+            }
+        };
+
+        if (ci->type == id_DSP48E1_DSP48E1) {
+            all_dsps.push_back(ci);
+            auto gnd_attr = ctx->id("DSP_GND_PINS");
+            auto vcc_attr = ctx->id("DSP_VCC_PINS");
+
+            auto gnd_pins = str_or_default(ci->attrs, gnd_attr, "");
+            auto vcc_pins = str_or_default(ci->attrs, vcc_attr, "");
+
+            for (auto &port : ci->ports) {
+                std::string n = port.first.str(ctx);
+
+                if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
+                    if (port.second.net == nullptr)
+                        continue;
+                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
+                        ci->disconnectPort(port.first);
+                }
+
+                // prjxray has extra bits for these ports to hardwire them to VCC/GND
+                // as these seem to be interal to the tile,
+                // this saves us from having to route those externally
+                if (boost::starts_with(n, "D") ||
+                    boost::starts_with(n, "RSTD") ||
+                    // TODO: these seem to be inverted for unknown reasons
+                    // boost::starts_with(n, "INMODE") ||
+                    // boost::starts_with(n, "ALUMODE2") ||
+                    // boost::starts_with(n, "ALUMODE3") ||
+                    boost::starts_with(n, "CARRYINSEL2") ||
+                    boost::starts_with(n, "CED") ||
+                    boost::starts_with(n, "CEAD") ||
+                    boost::starts_with(n, "CEINMODE") ||
+                    boost::starts_with(n, "CEALUMODE")) {
+                    add_const_pin(port.second, gnd_pins, n, "$PACKER_GND_NET");
+                    add_const_pin(port.second, vcc_pins, n, "$PACKER_VCC_NET");
+                }
+            }
+
+            ci->attrs[gnd_attr] = gnd_pins;
+            ci->attrs[vcc_attr] = vcc_pins;
+        }
+    }
+
+    std::vector<CellInfo *> dsp_roots;
+    for (auto ci : all_dsps) {
+        bool cascade_input_used = false;
+        for (auto port : ci->ports) {
+            if (!boost::contains(port.first.str(ctx), "CIN")) continue;
+            if (port.second.net != nullptr) {
+                cascade_input_used = true;
+                break;
+            }
+        }
+
+        if (!cascade_input_used) {
+            dsp_roots.push_back(ci);
+        }
+    }
+
+    for (auto root : dsp_roots) {
+        root->constr_abs_z = true;
+        root->constr_z = BEL_LOWER_DSP;
+        walk_dsp(root, root, BEL_UPPER_DSP);
+    }
+}
+
+NEXTPNR_NAMESPACE_END

From 04f5f80766bd20d8795e8191e08f6cdd803d341d Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Fri, 13 Sep 2024 13:58:46 +0200
Subject: [PATCH 665/712] Himbaechel xilinx : Add safety check in DSP packing
 for 7-series

---
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 9faffedd4e..4a5b73daec 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -45,7 +45,7 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
         if (!boost::contains(port.first.str(ctx), "COUT")) continue;
         NetInfo *cout_net = port.second.net;
 
-        if (cout_net == nullptr) continue;
+        if (cout_net == nullptr || cout_net->users.empty()) continue;
 
         check_illegal_fanout(cout_net, port.first.c_str(ctx));
         PortRef& user = *cout_net->users.begin();

From ad9a54cc69cdb60a4a44327c1fce739fe21cc4a4 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Fri, 13 Sep 2024 15:22:25 +0200
Subject: [PATCH 666/712] Himbaechel xilinx : More cascaded input ports for
 which routing is skipped

---
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 4a5b73daec..03878ff3de 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -108,12 +108,26 @@ void XC7Packer::pack_dsps()
             for (auto &port : ci->ports) {
                 std::string n = port.first.str(ctx);
 
+                // According to ug479 :
+                // These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.
                 if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
                     if (port.second.net == nullptr)
                         continue;
                     if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
                         ci->disconnectPort(port.first);
                 }
+                if (n == "CARRYCASCIN") {
+                    if (port.second.net == nullptr)
+                        continue;
+                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
+                        ci->disconnectPort(port.first);
+                }
+                if (n == "MULTSIGNIN") {
+                    if (port.second.net == nullptr)
+                        continue;
+                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
+                        ci->disconnectPort(port.first);
+                }
 
                 // prjxray has extra bits for these ports to hardwire them to VCC/GND
                 // as these seem to be interal to the tile,

From 9bea22ed1e0647638c93f5c306334bb392f17294 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 17 Sep 2024 16:11:48 +0200
Subject: [PATCH 667/712] Himbaechel xilinx : DSP packing : Fix identification
 of cascaded ports and share identification code

---
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 32 ++++++++++++-------------
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 03878ff3de..13bfc3c7b6 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -26,6 +26,17 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
+static bool is_cascade_input(const std::string& port_name)
+{
+    return boost::starts_with(port_name, "ACIN") || boost::starts_with(port_name, "BCIN") || boost::starts_with(port_name, "PCIN") ||
+           port_name == "CARRYCASCIN" || port_name == "MULTSIGNIN";
+}
+static bool is_cascade_output(const std::string& port_name)
+{
+    return boost::starts_with(port_name, "ACOUT") || boost::starts_with(port_name, "BCOUT") || boost::starts_with(port_name, "PCOUT") ||
+           port_name == "CARRYCASCOUT" || port_name == "MULTSIGNOUT";
+}
+
 void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
 {
     CellInfo *cascaded_cell = nullptr;
@@ -42,7 +53,7 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
 
     // see if any cascade outputs are connected
     for (auto port : current_cell->ports) {
-        if (!boost::contains(port.first.str(ctx), "COUT")) continue;
+        if (!is_cascade_output(port.first.str(ctx))) continue;
         NetInfo *cout_net = port.second.net;
 
         if (cout_net == nullptr || cout_net->users.empty()) continue;
@@ -108,21 +119,8 @@ void XC7Packer::pack_dsps()
             for (auto &port : ci->ports) {
                 std::string n = port.first.str(ctx);
 
-                // According to ug479 :
-                // These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.
-                if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
-                    if (port.second.net == nullptr)
-                        continue;
-                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
-                        ci->disconnectPort(port.first);
-                }
-                if (n == "CARRYCASCIN") {
-                    if (port.second.net == nullptr)
-                        continue;
-                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
-                        ci->disconnectPort(port.first);
-                }
-                if (n == "MULTSIGNIN") {
+                // Cascading inputs do not use routing resources, so disconnect them if constants
+                if (is_cascade_input(n)) {
                     if (port.second.net == nullptr)
                         continue;
                     if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
@@ -157,7 +155,7 @@ void XC7Packer::pack_dsps()
     for (auto ci : all_dsps) {
         bool cascade_input_used = false;
         for (auto port : ci->ports) {
-            if (!boost::contains(port.first.str(ctx), "CIN")) continue;
+            if (!is_cascade_input(port.first.str(ctx))) continue;
             if (port.second.net != nullptr) {
                 cascade_input_used = true;
                 break;

From a08229d6b60de562f81773519a1cabd92137bb33 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 17 Sep 2024 23:46:18 +0200
Subject: [PATCH 668/712] Placer : Clearer messages in warnings and errors

---
 common/place/placer_heap.cc | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index b701c65f40..92311c7917 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -301,17 +301,24 @@ class HeAPPlacer
             ++iter;
         }
 
-        // Apply saved solution
+        // Remove any previous binding
         for (auto &sc : solution) {
             CellInfo *cell = std::get<0>(sc);
             if (cell->bel != BelId())
                 ctx->unbindBel(cell->bel);
         }
+        // Apply saved solution
         for (auto &sc : solution) {
             CellInfo *cell;
             BelId bel;
             PlaceStrength strength;
             std::tie(cell, bel, strength) = sc;
+            // In case no bel was found, emit a warning instead of continuing to a crash
+            // This helps to investigate and to devise a workaround in user design
+            if (bel == BelId()) {
+                log_warning("No bel found to bind cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx));
+                continue;
+            }
             ctx->bindBel(bel, cell, strength);
         }
 
@@ -886,10 +893,10 @@ class HeAPPlacer
 
             while (!placed) {
                 if (cfg.cell_placement_timeout > 0 && total_iters_for_cell > cfg.cell_placement_timeout)
-                    log_error("Unable to find legal placement for cell '%s' after %d attempts, check constraints and "
+                    log_error("Unable to find legal placement for cell '%s' of type '%s' after %d attempts, check constraints and "
                               "utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of "
                               "attempts.\n",
-                              ctx->nameOf(ci), total_iters_for_cell);
+                              ctx->nameOf(ci), ci->type.c_str(ctx), total_iters_for_cell);
 
                 // Determine a search radius around the solver location (which increases over time) that is clamped to
                 // the region constraint for the cell (if applicable)

From 8a0e0625204bb83748722fab85a97b8074c53be9 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Thu, 19 Sep 2024 10:49:58 +0200
Subject: [PATCH 669/712] Himbaechel xilinx : DSP packing : Improve code
 efficiency

---
 himbaechel/uarch/xilinx/constids.inc    |  4 ++++
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 20 +++++++++++---------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/himbaechel/uarch/xilinx/constids.inc b/himbaechel/uarch/xilinx/constids.inc
index d4db03b2da..7e5024b3d1 100644
--- a/himbaechel/uarch/xilinx/constids.inc
+++ b/himbaechel/uarch/xilinx/constids.inc
@@ -288,6 +288,8 @@ X(BUFMRCE)
 X(C)
 X(CARRYIN)
 X(CARRY_TYPE)
+X(CARRYCASCIN)
+X(CARRYCASCOUT)
 X(CB)
 X(CDDCREQ)
 X(CE0)
@@ -531,6 +533,8 @@ X(MMCME3_ADV)
 X(MMCME3_BASE)
 X(MMCME4_ADV)
 X(MMCME4_BASIC)
+X(MULTSIGNIN)
+X(MULTSIGNOUT)
 X(MUXCY)
 X(MUXF7)
 X(MUXF8)
diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 13bfc3c7b6..f80be160eb 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -26,15 +26,17 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static bool is_cascade_input(const std::string& port_name)
+static bool is_cascade_input(const PortInfo& port, const Context *ctx)
 {
-    return boost::starts_with(port_name, "ACIN") || boost::starts_with(port_name, "BCIN") || boost::starts_with(port_name, "PCIN") ||
-           port_name == "CARRYCASCIN" || port_name == "MULTSIGNIN";
+    if(port.name == id_CARRYCASCIN || port.name == id_MULTSIGNIN) return true;
+		const std::string& str = port.name.c_str(ctx);
+    return boost::starts_with(str, "ACIN") || boost::starts_with(str, "BCIN") || boost::starts_with(str, "PCIN");
 }
-static bool is_cascade_output(const std::string& port_name)
+static bool is_cascade_output(const PortInfo& port, const Context *ctx)
 {
-    return boost::starts_with(port_name, "ACOUT") || boost::starts_with(port_name, "BCOUT") || boost::starts_with(port_name, "PCOUT") ||
-           port_name == "CARRYCASCOUT" || port_name == "MULTSIGNOUT";
+    if(port.name == id_CARRYCASCOUT || port.name == id_MULTSIGNOUT) return true;
+		const std::string& str = port.name.c_str(ctx);
+    return boost::starts_with(str, "ACOUT") || boost::starts_with(str, "BCOUT") || boost::starts_with(str, "PCOUT");
 }
 
 void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
@@ -53,7 +55,7 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
 
     // see if any cascade outputs are connected
     for (auto port : current_cell->ports) {
-        if (!is_cascade_output(port.first.str(ctx))) continue;
+        if (!is_cascade_output(port.second, ctx)) continue;
         NetInfo *cout_net = port.second.net;
 
         if (cout_net == nullptr || cout_net->users.empty()) continue;
@@ -120,7 +122,7 @@ void XC7Packer::pack_dsps()
                 std::string n = port.first.str(ctx);
 
                 // Cascading inputs do not use routing resources, so disconnect them if constants
-                if (is_cascade_input(n)) {
+                if (is_cascade_input(port.second, ctx)) {
                     if (port.second.net == nullptr)
                         continue;
                     if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
@@ -155,7 +157,7 @@ void XC7Packer::pack_dsps()
     for (auto ci : all_dsps) {
         bool cascade_input_used = false;
         for (auto port : ci->ports) {
-            if (!is_cascade_input(port.first.str(ctx))) continue;
+            if (!is_cascade_input(port.second, ctx)) continue;
             if (port.second.net != nullptr) {
                 cascade_input_used = true;
                 break;

From 81bf92a85585abec204113ca88dccf6f7426db2e Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Thu, 19 Sep 2024 10:54:55 +0200
Subject: [PATCH 670/712] Himbaechel xilinx : DSP packing : Disable clustering

---
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index f80be160eb..34a93ff849 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -81,6 +81,8 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
         // the connected cell has to be above the current cell,
         // otherwise it cannot be routed, because the cascading ports
         // are only connected to the DSP above
+        // FIXME The offset +/-5 applies to DSP tiles, not to DSP slices
+        //   So two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
         auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
         cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
         cascaded_cell->constr_z = constr_z;
@@ -169,11 +171,15 @@ void XC7Packer::pack_dsps()
         }
     }
 
+    // Creating placement clusters is currently disabled, because the current constraints
+    // on Y coordinates don't always correspond to placement possibilities, which makes placer crash
+    #if 0
     for (auto root : dsp_roots) {
         root->constr_abs_z = true;
         root->constr_z = BEL_LOWER_DSP;
         walk_dsp(root, root, BEL_UPPER_DSP);
     }
+    #endif
 }
 
 NEXTPNR_NAMESPACE_END

From 2031a067a0299d30e37562934e0ef1e4bc6c9967 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Thu, 19 Sep 2024 16:09:05 +0200
Subject: [PATCH 671/712] Himbaechel xilinx : More flexibility about types of
 DSP parameters

---
 common/kernel/util.h            | 45 +++++++++++++++++++++++++++++++++
 himbaechel/uarch/xilinx/fasm.cc | 30 ++++++++++------------
 2 files changed, 58 insertions(+), 17 deletions(-)

diff --git a/common/kernel/util.h b/common/kernel/util.h
index f04a956bd5..0223470aff 100644
--- a/common/kernel/util.h
+++ b/common/kernel/util.h
@@ -102,6 +102,51 @@ bool bool_or_default(const Container &ct, const KeyType &key, bool def = false)
     return bool(int_or_default(ct, key, int(def)));
 };
 
+// Get a bool from a map-style container, returning default if value is not found
+// Also tolerate string representation of boolean for interoperability purposes
+template <typename KeyType>
+bool boolstr_or_default(const dict<KeyType, Property> &ct, const KeyType &key, bool def = false)
+{
+    auto found = ct.find(key);
+    if (found == ct.end())
+        return def;
+    if (!found->second.is_string)
+        bool(found->second.as_int64());
+    const char* str = found->second.as_string().c_str();
+    if(!strcmp(str, "0") || !strcasecmp(str, "false"))
+        return false;
+    else if(!strcmp(str, "1") || !strcasecmp(str, "true"))
+        return true;
+    else
+        log_error("Expecting bool-compatible value but got '%s'.\n", found->second.as_string().c_str());
+    return false;
+};
+
+// Get a vector of bool from a map-style container, returning default if value is not found
+// Also tolerate string representation of vector for interoperability purposes
+template <typename KeyType>
+bool boolvec_populate(const dict<KeyType, Property> &ct, const KeyType &key, std::vector<bool>& vec)
+{
+    auto found = ct.find(key);
+    if (found == ct.end())
+        return false;
+    if (!found->second.is_string)
+    {
+        size_t val = found->second.as_int64();
+        for (size_t i = 0; i < vec.size(); ++i, val>>=1) {
+            vec[i] = (val & 0x1) != 0;
+        }
+    }
+    else {
+        const std::string& str = found->second.as_string();
+        size_t i = 0;
+        for (auto it = str.crbegin(); it != str.crend() && i < vec.size(); ++i, ++it) {
+            vec[i] = *it == '1';
+        }
+    }
+    return true;
+};
+
 // Get only value from a forward iterator begin/end pair.
 //
 // Generates assertion failure if std::distance(begin, end) != 1.
diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc
index 2c9dced7a0..f59a3fe469 100644
--- a/himbaechel/uarch/xilinx/fasm.cc
+++ b/himbaechel/uarch/xilinx/fasm.cc
@@ -1536,8 +1536,9 @@ struct FasmBackend
         if (binput == "CASCADE")
             write_bit("B_INPUT[0]");
 
-        auto use_dport = str_or_default(ci->params, ctx->id("USE_DPORT"), "FALSE");
-        if (use_dport == "TRUE")
+        // Tolerate both int and string types for interoperability purposes
+        auto use_dport = boolstr_or_default(ci->params, ctx->id("USE_DPORT"), false);
+        if (use_dport == true)
             write_bit("USE_DPORT[0]");
 
         auto use_simd = str_or_default(ci->params, ctx->id("USE_SIMD"), "ONE48");
@@ -1547,14 +1548,10 @@ struct FasmBackend
             write_bit("USE_SIMD_FOUR12");
 
         // PATTERN
-        auto pattern_str = str_or_default(ci->params, ctx->id("PATTERN"), "");
-        if (!boost::empty(pattern_str)) {
-            const size_t pattern_size = 48;
-            std::vector<bool> pattern_vector(pattern_size, true);
-            size_t i = 0;
-            for (auto it = pattern_str.crbegin(); it != pattern_str.crend() && i < pattern_size; ++i, ++it) {
-                pattern_vector[i] = *it == '1';
-            }
+        const size_t pattern_size = 48;
+        std::vector<bool> pattern_vector(pattern_size, false);
+        bool pattern_found = boolvec_populate(ci->params, ctx->id("PATTERN"), pattern_vector);
+        if (pattern_found) {
             write_vector("PATTERN[47:0]", pattern_vector);
         }
 
@@ -1565,16 +1562,15 @@ struct FasmBackend
             write_bit("AUTORESET_PATDET_RESET_NOT_MATCH");
 
         // MASK
-        auto mask_str = str_or_default(ci->params, ctx->id("MASK"), "001111111111111111111111111111111111111111111111");
         // Yosys gives us 48 bit, but prjxray only recognizes 46 bits
         // The most significant two bits seem to be zero, so let us just truncate them
-        const size_t mask_size = 46;
+        const size_t mask_size = 48;
         std::vector<bool> mask_vector(mask_size, true);
-        size_t i = 0;
-        for (auto it = mask_str.crbegin(); it != mask_str.crend() && i < mask_size; ++i, ++it) {
-            mask_vector[i] = *it == '1';
+        bool mask_found = boolvec_populate(ci->params, ctx->id("MASK"), mask_vector);
+        if (mask_found) {
+            mask_vector.resize(46);
+            write_vector("MASK[45:0]", mask_vector);
         }
-        write_vector("MASK[45:0]", mask_vector);
 
         auto sel_mask = str_or_default(ci->params, ctx->id("SEL_MASK"), "MASK");
         if (sel_mask == "C")
@@ -1599,7 +1595,7 @@ struct FasmBackend
         write_bit("ZMREG[0]", !bool_or_default(ci->params, ctx->id("MREG")));
         write_bit("ZOPMODEREG[0]", !bool_or_default(ci->params, ctx->id("OPMODEREG")));
         write_bit("ZPREG[0]", !bool_or_default(ci->params, ctx->id("PREG")));
-        write_bit("USE_DPORT[0]", str_or_default(ci->params, ctx->id("USE_DPORT"), "FALSE") == "TRUE");
+        write_bit("USE_DPORT[0]", boolstr_or_default(ci->params, ctx->id("USE_DPORT"), false));
         write_bit("ZIS_CLK_INVERTED", !bool_or_default(ci->params, ctx->id("IS_CLK_INVERTED")));
         write_bit("ZIS_CARRYIN_INVERTED", !bool_or_default(ci->params, ctx->id("IS_CARRYIN_INVERTED")));
         pop(2);

From 9da05b60012649f2a4e1425a8d3d46c58490f3e8 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 24 Sep 2024 10:01:29 +0200
Subject: [PATCH 672/712] Himbaechel xilinx : DSP packing : Emit a non-fatal
 error message

---
 himbaechel/uarch/xilinx/pack.h          |  2 +-
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 31 ++++++++++++++++++-------
 2 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/himbaechel/uarch/xilinx/pack.h b/himbaechel/uarch/xilinx/pack.h
index 130949581e..c0579419f3 100644
--- a/himbaechel/uarch/xilinx/pack.h
+++ b/himbaechel/uarch/xilinx/pack.h
@@ -210,7 +210,7 @@ struct XC7Packer : public XilinxPacker
     void pack_dsps();
 
   private:
-    void walk_dsp(CellInfo *root, CellInfo *ci, int constr_z);
+    unsigned walk_dsp(CellInfo *root, CellInfo *ci, int constr_z);
     void check_valid_pad(CellInfo *ci, std::string type);
 };
 
diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 34a93ff849..45f375e054 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -39,9 +39,11 @@ static bool is_cascade_output(const PortInfo& port, const Context *ctx)
     return boost::starts_with(str, "ACOUT") || boost::starts_with(str, "BCOUT") || boost::starts_with(str, "PCOUT");
 }
 
-void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
+// Return : the number of DSP marked as cascaded
+unsigned XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
 {
     CellInfo *cascaded_cell = nullptr;
+    unsigned num_casc = 0;
 
     auto check_illegal_fanout = [&] (NetInfo *ni, std::string port) {
         if (ni->users.entries() > 1)
@@ -75,21 +77,28 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
     if (cascaded_cell != nullptr) {
         auto is_lower_bel = constr_z == BEL_LOWER_DSP;
 
+        // Creating placement clusters is currently disabled, because the current constraints
+        // on Y coordinates don't always correspond to placement possibilities, which makes placer crash
+        // Explanation : the current offset +/-5 applies to DSP tiles, not to DSP slices
+        // But two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
+        #if 0
         cascaded_cell->cluster = root->name;
         root->constr_children.push_back(cascaded_cell);
         cascaded_cell->constr_x = 0;
         // the connected cell has to be above the current cell,
         // otherwise it cannot be routed, because the cascading ports
         // are only connected to the DSP above
-        // FIXME The offset +/-5 applies to DSP tiles, not to DSP slices
-        //   So two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
         auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
         cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
         cascaded_cell->constr_z = constr_z;
         cascaded_cell->constr_abs_z = true;
+        #endif
 
-        walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
+        num_casc += 1;
+        num_casc += walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
     }
+
+    return num_casc;
 }
 
 void XC7Packer::pack_dsps()
@@ -102,6 +111,7 @@ void XC7Packer::pack_dsps()
 
     std::vector<CellInfo *> all_dsps;
 
+    // Clean connections of DSPs
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
 
@@ -155,6 +165,7 @@ void XC7Packer::pack_dsps()
         }
     }
 
+    // Find the roots of cascaded DSP
     std::vector<CellInfo *> dsp_roots;
     for (auto ci : all_dsps) {
         bool cascade_input_used = false;
@@ -171,15 +182,17 @@ void XC7Packer::pack_dsps()
         }
     }
 
-    // Creating placement clusters is currently disabled, because the current constraints
-    // on Y coordinates don't always correspond to placement possibilities, which makes placer crash
-    #if 0
+    // Create clusters of cascaded DSPs
+    unsigned num_casc = 0;
     for (auto root : dsp_roots) {
         root->constr_abs_z = true;
         root->constr_z = BEL_LOWER_DSP;
-        walk_dsp(root, root, BEL_UPPER_DSP);
+        num_casc += walk_dsp(root, root, BEL_UPPER_DSP);
+    }
+    if(num_casc > 0) {
+       log_info("Found %u cascaded DSP from %u roots\n", num_casc, (unsigned)dsp_roots.size());
+       log_nonfatal_error("Cascaded DSP are currently not supported by the placer, the design will probably not be functional\n");
     }
-    #endif
 }
 
 NEXTPNR_NAMESPACE_END

From cd51a0c2fc9a7632f1920595dbf6f3df015104da Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 24 Sep 2024 10:02:47 +0200
Subject: [PATCH 673/712] Placer : Emit non-fatal error messages before ending
 the program

---
 common/place/placer_heap.cc | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 92311c7917..132da8b972 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -313,25 +313,31 @@ class HeAPPlacer
             BelId bel;
             PlaceStrength strength;
             std::tie(cell, bel, strength) = sc;
-            // In case no bel was found, emit a warning instead of continuing to a crash
-            // This helps to investigate and to devise a workaround in user design
-            if (bel == BelId()) {
-                log_warning("No bel found to bind cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx));
+            // Just skip unbound cells here, these errors are handled just after
+            if (bel == BelId())
                 continue;
-            }
             ctx->bindBel(bel, cell, strength);
         }
 
+				// Find and display all errors to help in finding the root cause of issues
+        unsigned num_errors = 0;
         for (auto &cell : ctx->cells) {
             if (cell.second->isPseudo())
                 continue;
-            if (cell.second->bel == BelId())
-                log_error("Found unbound cell %s\n", cell.first.c_str(ctx));
-            if (ctx->getBoundBelCell(cell.second->bel) != cell.second.get())
-                log_error("Found cell %s with mismatched binding\n", cell.first.c_str(ctx));
-            if (ctx->debug)
+            if (cell.second->bel == BelId()) {
+                log_nonfatal_error("Found unbound cell '%s' of type '%s'\n", cell.first.c_str(ctx), cell.second->type.c_str(ctx));
+                num_errors++;
+            }
+            else if (ctx->getBoundBelCell(cell.second->bel) != cell.second.get()) {
+                log_nonfatal_error("Found mismatched binding for '%s' or type '%s'\n", cell.first.c_str(ctx), cell.second->type.c_str(ctx));
+                num_errors++;
+            }
+            else if (ctx->debug)
                 log_info("AP soln: %s -> %s\n", cell.first.c_str(ctx), ctx->nameOfBel(cell.second->bel));
         }
+        if (num_errors > 0) {
+            log_error("Stopping the program after %u errors found\n", num_errors);
+        }
 
         bool any_bad_placements = false;
         for (auto bel : ctx->getBels()) {

From 437fb70ed364c94dcc040b58820b64fbf9164326 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 24 Sep 2024 11:52:31 +0200
Subject: [PATCH 674/712] Himbaechel xilinx : Fix packing of cascaded DSP

---
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 45f375e054..a97c92ccf3 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -77,22 +77,16 @@ unsigned XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_
     if (cascaded_cell != nullptr) {
         auto is_lower_bel = constr_z == BEL_LOWER_DSP;
 
-        // Creating placement clusters is currently disabled, because the current constraints
-        // on Y coordinates don't always correspond to placement possibilities, which makes placer crash
-        // Explanation : the current offset +/-5 applies to DSP tiles, not to DSP slices
-        // But two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
-        #if 0
         cascaded_cell->cluster = root->name;
         root->constr_children.push_back(cascaded_cell);
         cascaded_cell->constr_x = 0;
-        // the connected cell has to be above the current cell,
+        // The connected cell has to be above the current cell,
         // otherwise it cannot be routed, because the cascading ports
         // are only connected to the DSP above
         auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
         cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
         cascaded_cell->constr_z = constr_z;
         cascaded_cell->constr_abs_z = true;
-        #endif
 
         num_casc += 1;
         num_casc += walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
@@ -187,11 +181,14 @@ void XC7Packer::pack_dsps()
     for (auto root : dsp_roots) {
         root->constr_abs_z = true;
         root->constr_z = BEL_LOWER_DSP;
-        num_casc += walk_dsp(root, root, BEL_UPPER_DSP);
+        unsigned loc_casc = walk_dsp(root, root, BEL_UPPER_DSP);
+        if(loc_casc > 0) {
+            root->cluster = root->name;
+        }
+        num_casc += loc_casc;
     }
     if(num_casc > 0) {
        log_info("Found %u cascaded DSP from %u roots\n", num_casc, (unsigned)dsp_roots.size());
-       log_nonfatal_error("Cascaded DSP are currently not supported by the placer, the design will probably not be functional\n");
     }
 }
 

From c90d872e3586d8129b46638d96325990d5588c20 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 26 Sep 2024 15:56:20 +0200
Subject: [PATCH 675/712] xilinx: Filter out another missing pip type

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/gen/filters.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/himbaechel/uarch/xilinx/gen/filters.py b/himbaechel/uarch/xilinx/gen/filters.py
index ba74546d17..20b48ab77a 100644
--- a/himbaechel/uarch/xilinx/gen/filters.py
+++ b/himbaechel/uarch/xilinx/gen/filters.py
@@ -91,6 +91,8 @@ def include_pip(tile_type, p):
     if tile_type.startswith("HCLK_IOI"):
         if "RCLK_BEFORE_DIV" in p.dst_wire().name() and "IMUX" in p.src_wire().name():
             return False
+        if  p.dst_wire().name().endswith("_DMUX") and "I2IOCLK_TOP" in p.src_wire().name():
+            return False
     if "IOI" in tile_type:
         if "CLKB" in p.dst_wire().name() and "IMUX22" in p.src_wire().name():
             return False

From 118ecbc6b38956925e5cd69b5859a93fa34035ab Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 26 Sep 2024 15:58:16 +0200
Subject: [PATCH 676/712] xilinx: Remove unnecessary assert

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/fasm.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc
index f59a3fe469..8d31b6bdee 100644
--- a/himbaechel/uarch/xilinx/fasm.cc
+++ b/himbaechel/uarch/xilinx/fasm.cc
@@ -322,8 +322,6 @@ struct FasmBackend
                             src_name.replace(us0pos, 2, "_1");
                     }
                 }
-
-                NPNR_ASSERT_FALSE("unimplemented!");
             }
             if (boost::contains(tile_name, "IOI")) {
                 if (boost::contains(dst_name, "OCLKB") && boost::contains(src_name, "IOI_OCLKM_"))

From 7516b8950a146a7871901f7211f8fe92b7f65960 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 26 Sep 2024 17:30:36 +0200
Subject: [PATCH 677/712] xilinx: Few more stub timings

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/gen/xilinx_gen.py | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/himbaechel/uarch/xilinx/gen/xilinx_gen.py b/himbaechel/uarch/xilinx/gen/xilinx_gen.py
index 8eec7f56cd..3764ff55df 100644
--- a/himbaechel/uarch/xilinx/gen/xilinx_gen.py
+++ b/himbaechel/uarch/xilinx/gen/xilinx_gen.py
@@ -4,6 +4,7 @@
 import xilinx_device
 import filters
 import struct
+import parse_sdf
 sys.path.append(path.join(path.dirname(__file__), "../../.."))
 from himbaechel_dbgen.chip import *
 
@@ -251,6 +252,15 @@ def add_site_io_pip(pin):
         if pip.is_bidi():
             add_pip(pip.dst_wire().name(), pip.src_wire().name(), pip_class=PipClass.TILE_ROUTING, timing=tcls,
                 pip_config=1 if pip.is_route_thru() else 0)
+
+def import_sdf_timings(variant, sdfcell):
+    # TODO: anything other than comb
+    for entry in sdfcell.entries:
+        if isinstance(entry, parse_sdf.IOPath):
+            variant.add_comb_arc(entry.from_pin, entry.to_pin,
+                TimingValue(int(min(entry.rising.minv, entry.falling.minv)*1000),
+                    int(max(entry.rising.maxv, entry.falling.maxv)*1000)))
+
 def main():
     xlbase = path.join(path.dirname(path.realpath(__file__)), "..")
 
@@ -355,6 +365,14 @@ def main():
     ff.add_setup_hold("CK", "SR", ClockEdge.RISING, TimingValue(100, 100), TimingValue(0, 0))
     ff.add_setup_hold("CK", "D", ClockEdge.RISING, TimingValue(100, 100), TimingValue(200, 200))
     ff.add_clock_out("CK", "Q", ClockEdge.RISING, TimingValue(300, 350))
+
+    # Load SDF for carry and mux
+    slicem_sdf = parse_sdf.parse_sdf_file(path.join(xraydb_root, "timings", "slicem.sdf"))
+    mux = ch.timing.add_cell_variant("DEFAULT", "SELMUX2_1")
+    import_sdf_timings(mux, slicem_sdf.cells[("SELMUX2_1", "SLICEM/F7BMUX")])
+    carry = ch.timing.add_cell_variant("DEFAULT", "CARRY4")
+    import_sdf_timings(carry, slicem_sdf.cells[("CARRY4", "SLICEM")])
+
     # Import package pins
     for package_name, package in sorted(d.packages.items(), key=lambda x:x[0]):
         pkg = ch.create_package(package_name)

From e4dfd4e622e6954c298b1a1e4a3f2af69967381c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 26 Sep 2024 18:11:01 +0200
Subject: [PATCH 678/712] xilinx: Support single-port LUTRAM variants

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/pack_dram.cc    | 52 ++++++++++++++++++++++++-
 himbaechel/uarch/xilinx/xilinx_place.cc |  8 +---
 2 files changed, 53 insertions(+), 7 deletions(-)

diff --git a/himbaechel/uarch/xilinx/pack_dram.cc b/himbaechel/uarch/xilinx/pack_dram.cc
index 00f9d40869..34ed70f927 100644
--- a/himbaechel/uarch/xilinx/pack_dram.cc
+++ b/himbaechel/uarch/xilinx/pack_dram.cc
@@ -237,7 +237,7 @@ void XilinxPacker::pack_dram()
         auto &dt = dt_iter->second;
         DRAMControlSet dcs;
         for (int i = 0; i < dt.abits; i++)
-            dcs.wa.push_back(ci->getPort(ctx->idf(dt.abits <= 6 ? "A%d" : "A[%d]", i)));
+            dcs.wa.push_back(ci->getPort(ctx->idf((dt.abits <= 6 || ci->type == id_RAM128X1S) ? "A%d" : "A[%d]", i)));
         dcs.wclk = ci->getPort(id_WCLK);
         dcs.we = ci->getPort(id_WE);
         dcs.wclk_inv = bool_or_default(ci->params, id_IS_WCLK_INVERTED);
@@ -302,6 +302,26 @@ void XilinxPacker::pack_dram()
                     z--;
                 }
 
+                packed_cells.insert(cell->name);
+            }
+        } else if (cs.memtype == id_RAM64X1S) {
+            int z = height - 1;
+            CellInfo *base = nullptr;
+            for (auto cell : group.second) {
+                NPNR_ASSERT(cell->type == id_RAM64X1S); // FIXME
+
+                if (z == (height - 1) || (z - 1) < 0) {
+                    z = (height - 1);
+                    base = nullptr;
+                }
+
+                std::vector<NetInfo *> address(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
+                CellInfo *ram = create_dram_lut(cell->name.str(ctx) + "/ADDR", base, cs, address, cell->getPort(id_D), cell->getPort(id_O), z);
+                if (cell->params.count(id_INIT))
+                        ram->params[id_INIT] = cell->params[id_INIT];
+                if (base == nullptr)
+                    base = ram;
+                z--;
                 packed_cells.insert(cell->name);
             }
         } else if (cs.memtype == id_RAM32X1D) {
@@ -411,6 +431,36 @@ void XilinxPacker::pack_dram()
                 // Decode mux tree using MUXF[78]
                 create_muxf_tree(base, "DPO", dpo_pre, addressr_high, dpo, 0);
 
+                packed_cells.insert(ci->name);
+            }
+        } else if (cs.memtype.in(id_RAM128X1S, id_RAM256X1S)) {
+            bool m256 = cs.memtype == id_RAM256X1S;
+            for (CellInfo *ci : group.second) {
+                auto init = get_or_default(ci->params, id_INIT, Property(0, m256 ? 256 : 128));
+                std::vector<NetInfo *> o_pre;
+                int z = (height - 1);
+
+                NetInfo *o = ci->getPort(id_O);
+                ci->disconnectPort(id_O);
+
+                // Low 6 bits of address - connect directly to RAM cells
+                std::vector<NetInfo *> addressw_64(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
+                // Upper bits of address - feed decode muxes
+                std::vector<NetInfo *> addressw_high(cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6), cs.wa.end());
+                CellInfo *base = nullptr;
+                // Combined write address/SPO read cells
+                for (int i = 0; i < (m256 ? 4 : 2); i++) {
+                    NetInfo *spo_i = create_internal_net(ci->name, stringf("O_%d", i), false);
+                    CellInfo *spr = create_dram_lut(ci->name.str(ctx) + "/ADDR" + std::to_string(i), base, cs,
+                                                    addressw_64, ci->getPort(id_D), spo_i, z);
+                    if (base == nullptr)
+                        base = spr;
+                    o_pre.push_back(spo_i);
+                    spr->params[id_INIT] = init.extract(i * 64, 64);
+                    z--;
+                }
+                // Decode mux tree using MUXF[78]
+                create_muxf_tree(base, "O", o_pre, addressw_high, o, m256 ? 4 : 2);
                 packed_cells.insert(ci->name);
             }
         }
diff --git a/himbaechel/uarch/xilinx/xilinx_place.cc b/himbaechel/uarch/xilinx/xilinx_place.cc
index d39b94d026..cea618d2c5 100644
--- a/himbaechel/uarch/xilinx/xilinx_place.cc
+++ b/himbaechel/uarch/xilinx/xilinx_place.cc
@@ -141,11 +141,11 @@ bool XilinxImpl::xc7_logic_tile_valid(IdString tile_type, const LogicTileStatus
                 mux_cell = lts.cells[(i - 1) << 4 | BEL_F8MUX];
             auto mux = get_tags(mux_cell);
             if (mux) {
-                if (x_net)
+                if (!x_net)
                     x_net = mux->mux.sel;
                 else if (x_net != mux->mux.sel) {
                     DBG();
-                    return false; // Memory and SRLs only valid in SLICEMs
+                    return false; // conflict between existing X use and mux select
                 }
             }
 
@@ -197,10 +197,6 @@ bool XilinxImpl::xc7_logic_tile_valid(IdString tile_type, const LogicTileStatus
                     if (x_net == nullptr)
                         x_net = ff2->ff.d;
                     else if (x_net != ff2->ff.d) {
-#ifdef DEBUG_VALIDITY
-                        log_info("%s %s %s %s %s\n", nameOf(lut6), nameOf(ff1), nameOf(lut5), nameOf(ff2),
-                                 nameOf(drv.cell));
-#endif
                         DBG();
                         return false;
                     }

From 38e5faca85cb727dea1d27b372ba1649d308f28c Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 27 Sep 2024 16:07:38 +0200
Subject: [PATCH 679/712] xilinx: Fix workaround for unsupported xdc construct

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/xdc.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
index 499a623ae1..e6d76b599a 100644
--- a/himbaechel/uarch/xilinx/xdc.cc
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -151,9 +151,10 @@ void XilinxImpl::parse_xdc(const std::string &filename)
                 for (int cursor = 0; cursor + 1 < int(dict_args.size()); cursor += 2) {
                     arg_pairs.emplace_back(std::move(dict_args.at(cursor)), std::move(dict_args.at(cursor + 1)));
                 }
-            } else
+            } else {
                 arg_pairs.emplace_back(std::move(arguments.at(1)), std::move(arguments.at(2)));
-            if (arguments.at(1) == "INTERNAL_VREF")
+            }
+            if (arg_pairs.size() == 1 && arg_pairs.front().first == "INTERNAL_VREF") // get_iobanks not supported
                 continue;
             if (arguments.at(3).size() > 2 && arguments.at(3) == "[current_design]") {
                 log_warning("[current_design] isn't supported, ignoring (on line %d)\n", lineno);

From d3c0f945da28a6de9a741ede1c4019cc7ab2793a Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 27 Sep 2024 16:24:47 +0200
Subject: [PATCH 680/712] xilinx: Fix BRAM placement, clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/fasm.cc         |  2 +-
 himbaechel/uarch/xilinx/pack.h          |  4 +-
 himbaechel/uarch/xilinx/pack_dram.cc    |  5 ++-
 himbaechel/uarch/xilinx/pack_dsp_xc7.cc | 52 +++++++++++++------------
 himbaechel/uarch/xilinx/xilinx.cc       | 18 +++++++--
 himbaechel/uarch/xilinx/xilinx.h        |  4 +-
 6 files changed, 50 insertions(+), 35 deletions(-)

diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc
index 8d31b6bdee..ecd0930b83 100644
--- a/himbaechel/uarch/xilinx/fasm.cc
+++ b/himbaechel/uarch/xilinx/fasm.cc
@@ -48,7 +48,7 @@ struct FasmBackend
 
     dict<IdString, pool<IdString>> invertible_pins;
 
-    FasmBackend(Context *ctx, XilinxImpl *uarch, std::ostream &out) : ctx(ctx), uarch(uarch), out(out){};
+    FasmBackend(Context *ctx, XilinxImpl *uarch, std::ostream &out) : ctx(ctx), uarch(uarch), out(out) {};
 
     void push(const std::string &x) { fasm_ctx.push_back(x); }
 
diff --git a/himbaechel/uarch/xilinx/pack.h b/himbaechel/uarch/xilinx/pack.h
index c0579419f3..3042032939 100644
--- a/himbaechel/uarch/xilinx/pack.h
+++ b/himbaechel/uarch/xilinx/pack.h
@@ -39,7 +39,7 @@ struct XilinxPacker
     Context *ctx;
     XilinxImpl *uarch;
 
-    XilinxPacker(Context *ctx, XilinxImpl *uarch) : ctx(ctx), uarch(uarch){};
+    XilinxPacker(Context *ctx, XilinxImpl *uarch) : ctx(ctx), uarch(uarch) {};
 
     // Generic cell transformation
     // Given cell name map and port map
@@ -170,7 +170,7 @@ struct XilinxPacker
 
 struct XC7Packer : public XilinxPacker
 {
-    XC7Packer(Context *ctx, XilinxImpl *uarch) : XilinxPacker(ctx, uarch){};
+    XC7Packer(Context *ctx, XilinxImpl *uarch) : XilinxPacker(ctx, uarch) {};
 
     // Carries
     bool has_illegal_fanout(NetInfo *carry);
diff --git a/himbaechel/uarch/xilinx/pack_dram.cc b/himbaechel/uarch/xilinx/pack_dram.cc
index 34ed70f927..ec3df753f6 100644
--- a/himbaechel/uarch/xilinx/pack_dram.cc
+++ b/himbaechel/uarch/xilinx/pack_dram.cc
@@ -316,9 +316,10 @@ void XilinxPacker::pack_dram()
                 }
 
                 std::vector<NetInfo *> address(cs.wa.begin(), cs.wa.begin() + std::min<size_t>(cs.wa.size(), 6));
-                CellInfo *ram = create_dram_lut(cell->name.str(ctx) + "/ADDR", base, cs, address, cell->getPort(id_D), cell->getPort(id_O), z);
+                CellInfo *ram = create_dram_lut(cell->name.str(ctx) + "/ADDR", base, cs, address, cell->getPort(id_D),
+                                                cell->getPort(id_O), z);
                 if (cell->params.count(id_INIT))
-                        ram->params[id_INIT] = cell->params[id_INIT];
+                    ram->params[id_INIT] = cell->params[id_INIT];
                 if (base == nullptr)
                     base = ram;
                 z--;
diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index a97c92ccf3..1e5e276d6d 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -26,16 +26,18 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static bool is_cascade_input(const PortInfo& port, const Context *ctx)
+static bool is_cascade_input(const PortInfo &port, const Context *ctx)
 {
-    if(port.name == id_CARRYCASCIN || port.name == id_MULTSIGNIN) return true;
-		const std::string& str = port.name.c_str(ctx);
+    if (port.name == id_CARRYCASCIN || port.name == id_MULTSIGNIN)
+        return true;
+    const std::string &str = port.name.c_str(ctx);
     return boost::starts_with(str, "ACIN") || boost::starts_with(str, "BCIN") || boost::starts_with(str, "PCIN");
 }
-static bool is_cascade_output(const PortInfo& port, const Context *ctx)
+static bool is_cascade_output(const PortInfo &port, const Context *ctx)
 {
-    if(port.name == id_CARRYCASCOUT || port.name == id_MULTSIGNOUT) return true;
-		const std::string& str = port.name.c_str(ctx);
+    if (port.name == id_CARRYCASCOUT || port.name == id_MULTSIGNOUT)
+        return true;
+    const std::string &str = port.name.c_str(ctx);
     return boost::starts_with(str, "ACOUT") || boost::starts_with(str, "BCOUT") || boost::starts_with(str, "PCOUT");
 }
 
@@ -45,31 +47,33 @@ unsigned XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_
     CellInfo *cascaded_cell = nullptr;
     unsigned num_casc = 0;
 
-    auto check_illegal_fanout = [&] (NetInfo *ni, std::string port) {
+    auto check_illegal_fanout = [&](NetInfo *ni, std::string port) {
         if (ni->users.entries() > 1)
             log_error("Port %s connected to net %s has more than one user", port.c_str(), ni->name.c_str(ctx));
 
-        PortRef& user = *ni->users.begin();
+        PortRef &user = *ni->users.begin();
         if (user.cell->type != id_DSP48E1_DSP48E1)
-            log_error("User %s of net %s is not a DSP block, but %s",
-                user.cell->name.c_str(ctx), ni->name.c_str(ctx), user.cell->type.c_str(ctx));
+            log_error("User %s of net %s is not a DSP block, but %s", user.cell->name.c_str(ctx), ni->name.c_str(ctx),
+                      user.cell->type.c_str(ctx));
     };
 
     // see if any cascade outputs are connected
     for (auto port : current_cell->ports) {
-        if (!is_cascade_output(port.second, ctx)) continue;
+        if (!is_cascade_output(port.second, ctx))
+            continue;
         NetInfo *cout_net = port.second.net;
 
-        if (cout_net == nullptr || cout_net->users.empty()) continue;
+        if (cout_net == nullptr || cout_net->users.empty())
+            continue;
 
         check_illegal_fanout(cout_net, port.first.c_str(ctx));
-        PortRef& user = *cout_net->users.begin();
+        PortRef &user = *cout_net->users.begin();
         CellInfo *cout_cell = user.cell;
         NPNR_ASSERT(cout_cell != nullptr);
 
         if (cascaded_cell != nullptr && cout_cell != cascaded_cell)
             log_error("the cascading outputs of DSP block %s are connected to different cells",
-                current_cell->name.c_str(ctx));
+                      current_cell->name.c_str(ctx));
 
         cascaded_cell = cout_cell;
     }
@@ -109,7 +113,7 @@ void XC7Packer::pack_dsps()
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
 
-        auto add_const_pin = [&](PortInfo& port, std::string& pins, std::string& pin_name, std::string net) {
+        auto add_const_pin = [&](PortInfo &port, std::string &pins, std::string &pin_name, std::string net) {
             if (port.net && port.net->name == ctx->id(net)) {
                 ci->disconnectPort(port.name);
                 pins += " " + pin_name;
@@ -138,16 +142,13 @@ void XC7Packer::pack_dsps()
                 // prjxray has extra bits for these ports to hardwire them to VCC/GND
                 // as these seem to be interal to the tile,
                 // this saves us from having to route those externally
-                if (boost::starts_with(n, "D") ||
-                    boost::starts_with(n, "RSTD") ||
+                if (boost::starts_with(n, "D") || boost::starts_with(n, "RSTD") ||
                     // TODO: these seem to be inverted for unknown reasons
                     // boost::starts_with(n, "INMODE") ||
                     // boost::starts_with(n, "ALUMODE2") ||
                     // boost::starts_with(n, "ALUMODE3") ||
-                    boost::starts_with(n, "CARRYINSEL2") ||
-                    boost::starts_with(n, "CED") ||
-                    boost::starts_with(n, "CEAD") ||
-                    boost::starts_with(n, "CEINMODE") ||
+                    boost::starts_with(n, "CARRYINSEL2") || boost::starts_with(n, "CED") ||
+                    boost::starts_with(n, "CEAD") || boost::starts_with(n, "CEINMODE") ||
                     boost::starts_with(n, "CEALUMODE")) {
                     add_const_pin(port.second, gnd_pins, n, "$PACKER_GND_NET");
                     add_const_pin(port.second, vcc_pins, n, "$PACKER_VCC_NET");
@@ -164,7 +165,8 @@ void XC7Packer::pack_dsps()
     for (auto ci : all_dsps) {
         bool cascade_input_used = false;
         for (auto port : ci->ports) {
-            if (!is_cascade_input(port.second, ctx)) continue;
+            if (!is_cascade_input(port.second, ctx))
+                continue;
             if (port.second.net != nullptr) {
                 cascade_input_used = true;
                 break;
@@ -182,13 +184,13 @@ void XC7Packer::pack_dsps()
         root->constr_abs_z = true;
         root->constr_z = BEL_LOWER_DSP;
         unsigned loc_casc = walk_dsp(root, root, BEL_UPPER_DSP);
-        if(loc_casc > 0) {
+        if (loc_casc > 0) {
             root->cluster = root->name;
         }
         num_casc += loc_casc;
     }
-    if(num_casc > 0) {
-       log_info("Found %u cascaded DSP from %u roots\n", num_casc, (unsigned)dsp_roots.size());
+    if (num_casc > 0) {
+        log_info("Found %u cascaded DSP from %u roots\n", num_casc, (unsigned)dsp_roots.size());
     }
 }
 
diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc
index db987f1c5f..aed4d4b704 100644
--- a/himbaechel/uarch/xilinx/xilinx.cc
+++ b/himbaechel/uarch/xilinx/xilinx.cc
@@ -37,7 +37,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-XilinxImpl::~XilinxImpl(){};
+XilinxImpl::~XilinxImpl() {};
 
 void XilinxImpl::init_database(Arch *arch)
 {
@@ -178,7 +178,19 @@ void XilinxImpl::update_logic_bel(BelId bel, CellInfo *cell)
     }
 }
 
-void XilinxImpl::update_bram_bel(BelId bel, CellInfo *cell) {}
+void XilinxImpl::update_bram_bel(BelId bel, CellInfo *cell)
+{
+    IdString type = ctx->getBelType(bel);
+    if (!type.in(id_RAMBFIFO18E2_RAMBFIFO18E2, id_RAMBFIFO36E2_RAMBFIFO36E2, id_RAMB18E2_RAMB18E2, id_FIFO36E2_FIFO36E2,
+                 id_RAMBFIFO36E1_RAMBFIFO36E1, id_RAMB36E1_RAMB36E1, id_RAMB18E1_RAMB18E1))
+        return;
+    auto &tts = tile_status.at(bel.tile);
+    if (!tts.bts)
+        tts.bts = std::make_unique<BRAMTileStatus>();
+    int z = ctx->getBelLocation(bel).z;
+    NPNR_ASSERT(z >= 0 && z < 12);
+    tts.bts->cells[z] = cell;
+}
 
 bool XilinxImpl::is_pip_unavail(PipId pip) const
 {
@@ -545,7 +557,7 @@ BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const
 namespace {
 struct XilinxArch : HimbaechelArch
 {
-    XilinxArch() : HimbaechelArch("xilinx"){};
+    XilinxArch() : HimbaechelArch("xilinx") {};
     bool match_device(const std::string &device) override { return device.size() > 3 && device.substr(0, 3) == "xc7"; }
     std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
     {
diff --git a/himbaechel/uarch/xilinx/xilinx.h b/himbaechel/uarch/xilinx/xilinx.h
index 1a87c78a52..a7d3e6860b 100644
--- a/himbaechel/uarch/xilinx/xilinx.h
+++ b/himbaechel/uarch/xilinx/xilinx.h
@@ -63,8 +63,8 @@ struct XilinxCellTags
 
 struct SiteIndex
 {
-    SiteIndex() : tile(-1), site(-1){};
-    SiteIndex(int32_t tile, int32_t site) : tile(tile), site(site){};
+    SiteIndex() : tile(-1), site(-1) {};
+    SiteIndex(int32_t tile, int32_t site) : tile(tile), site(site) {};
 
     int32_t tile;
     int32_t site;

From 24fc33c01452cba93376ec6d0da006f64f0a4cc3 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 27 Sep 2024 17:09:15 +0200
Subject: [PATCH 681/712] xilinx: Basic I/ODDR support

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/fasm.cc    |   6 +-
 himbaechel/uarch/xilinx/pack.cc    |   2 +-
 himbaechel/uarch/xilinx/pack.h     |  10 +-
 himbaechel/uarch/xilinx/pack_io.cc | 180 +++++++++++++++++++++++++++++
 himbaechel/uarch/xilinx/xilinx.cc  |  10 ++
 himbaechel/uarch/xilinx/xilinx.h   |   1 +
 6 files changed, 199 insertions(+), 10 deletions(-)

diff --git a/himbaechel/uarch/xilinx/fasm.cc b/himbaechel/uarch/xilinx/fasm.cc
index ecd0930b83..9ca5e074ce 100644
--- a/himbaechel/uarch/xilinx/fasm.cc
+++ b/himbaechel/uarch/xilinx/fasm.cc
@@ -333,19 +333,17 @@ struct FasmBackend
             out << src_name << std::endl;
 
             if (boost::contains(tile_name, "IOI") && boost::starts_with(dst_name, "IOI_OCLK_")) {
-#if 0
                 dst_name.insert(dst_name.find("OCLK") + 4, 1, 'M');
                 orig_dst_name.insert(dst_name.find("OCLK") + 4, 1, 'M');
 
-                WireId w = ctx->getWireByNameStr(tile_name + "/" + orig_dst_name);
+                WireId w = uarch->lookup_wire(pip.tile, ctx->id(orig_dst_name));
+
                 NPNR_ASSERT(w != WireId());
                 if (ctx->getBoundWireNet(w) == nullptr) {
                     out << tile_name << ".";
                     out << dst_name << ".";
                     out << src_name << std::endl;
                 }
-#endif
-                NPNR_ASSERT_FALSE("unimplemented!");
             }
 
             last_was_blank = false;
diff --git a/himbaechel/uarch/xilinx/pack.cc b/himbaechel/uarch/xilinx/pack.cc
index a219fbf46c..1644e1882a 100644
--- a/himbaechel/uarch/xilinx/pack.cc
+++ b/himbaechel/uarch/xilinx/pack.cc
@@ -733,7 +733,7 @@ void XilinxImpl::pack()
     packer.pack_io();
     packer.prepare_clocking();
     packer.pack_constants();
-    // packer.pack_iologic();
+    packer.pack_iologic();
     // packer.pack_idelayctrl();
     packer.pack_clocking();
     packer.pack_muxfs();
diff --git a/himbaechel/uarch/xilinx/pack.h b/himbaechel/uarch/xilinx/pack.h
index 3042032939..008c758faa 100644
--- a/himbaechel/uarch/xilinx/pack.h
+++ b/himbaechel/uarch/xilinx/pack.h
@@ -186,11 +186,11 @@ struct XC7Packer : public XilinxPacker
     // IOLOGIC
     dict<IdString, XFormRule> hp_iol_rules, hd_iol_rules, ioctrl_rules;
     void fold_inverter(CellInfo *cell, std::string port);
-    std::string get_ologic_site(const std::string &io_bel);
-    std::string get_ilogic_site(const std::string &io_bel);
-    std::string get_ioctrl_site(const std::string &io_bel);
-    std::string get_odelay_site(const std::string &io_bel);
-    std::string get_idelay_site(const std::string &io_bel);
+    SiteIndex get_ologic_site(BelId io_bel);
+    SiteIndex get_ilogic_site(BelId io_bel);
+    SiteIndex get_ioctrl_site(BelId io_bel);
+    SiteIndex get_odelay_site(BelId io_bel);
+    SiteIndex get_idelay_site(BelId io_bel);
     // Call before packing constants
     void prepare_iologic();
 
diff --git a/himbaechel/uarch/xilinx/pack_io.cc b/himbaechel/uarch/xilinx/pack_io.cc
index 5bebbb9ccd..2419822b16 100644
--- a/himbaechel/uarch/xilinx/pack_io.cc
+++ b/himbaechel/uarch/xilinx/pack_io.cc
@@ -494,4 +494,184 @@ void XC7Packer::check_valid_pad(CellInfo *ci, std::string type)
     log_error("unsupported DRIVE strength property %s for port %s", drive_attr->second.c_str(), ci->name.c_str(ctx));
 }
 
+SiteIndex XC7Packer::get_ologic_site(BelId io_bel)
+{
+    BelId ibc_bel;
+    if (boost::contains(uarch->bel_name_in_site(io_bel).str(ctx), "IOB18"))
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB18.OUTBUF_DCIEN"));
+    else
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB33.OUTBUF"));
+    NPNR_ASSERT(ibc_bel != BelId());
+
+    std::queue<WireId> visit;
+    visit.push(ctx->getBelPinWire(ibc_bel, id_IN));
+
+    while (!visit.empty()) {
+        WireId cursor = visit.front();
+        visit.pop();
+        for (auto bp : ctx->getWireBelPins(cursor)) {
+            auto site = uarch->get_bel_site(bp.bel);
+            if (boost::starts_with(uarch->get_site_name(site).str(ctx), "OLOGIC"))
+                return site;
+        }
+        for (auto pip : ctx->getPipsUphill(cursor))
+            visit.push(ctx->getPipSrcWire(pip));
+    }
+    NPNR_ASSERT_FALSE("failed to find OLOGIC");
+}
+
+SiteIndex XC7Packer::get_ilogic_site(BelId io_bel)
+{
+    BelId ibc_bel;
+    if (boost::contains(uarch->bel_name_in_site(io_bel).str(ctx), "IOB18"))
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB18.INBUF_DCIEN"));
+    else
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB33.INBUF_EN"));
+
+    NPNR_ASSERT(ibc_bel != BelId());
+
+    std::queue<WireId> visit;
+    visit.push(ctx->getBelPinWire(ibc_bel, id_OUT));
+
+    while (!visit.empty()) {
+        WireId cursor = visit.front();
+        visit.pop();
+        for (auto bp : ctx->getWireBelPins(cursor)) {
+            auto site = uarch->get_bel_site(bp.bel);
+            if (boost::starts_with(uarch->get_site_name(site).str(ctx), "ILOGIC"))
+                return site;
+        }
+        for (auto pip : ctx->getPipsDownhill(cursor))
+            visit.push(ctx->getPipDstWire(pip));
+    }
+    NPNR_ASSERT_FALSE("failed to find ILOGIC");
+}
+
+
+void XC7Packer::fold_inverter(CellInfo *cell, std::string port)
+{
+    IdString p = ctx->id(port);
+    NetInfo *net = cell->getPort(p);
+    if (!net)
+        return;
+    CellInfo *drv = net->driver.cell;
+    if (!drv)
+        return;
+    if (drv->type == id_LUT1 && int_or_default(drv->params, id_INIT, 0) == 1) {
+        cell->disconnectPort(p);
+        NetInfo *preinv = drv->getPort(id_I0);
+        cell->connectPort(p, preinv);
+        cell->params[ctx->idf("IS_%s_INVERTED", port.c_str())] = 1;
+        if (net->users.empty())
+            packed_cells.insert(drv->name);
+    } else if (drv->type == id_INV) {
+        cell->disconnectPort(p);
+        NetInfo *preinv = drv->getPort(id_I);
+        cell->connectPort(p, preinv);
+        cell->params[ctx->idf("IS_%s_INVERTED", port.c_str())] = 1;
+        if (net->users.empty())
+            packed_cells.insert(drv->name);
+    }
+}
+
+void XC7Packer::pack_iologic()
+{
+    log_info("Packing IOLOGIC...\n");
+    dict<IdString, BelId> iodelay_to_io;
+    dict<IdString, XFormRule> iologic_rules;
+
+    // IDDR
+    iologic_rules[id_IDDR].new_type = id_ILOGICE3_IFF;
+    iologic_rules[id_IDDR].port_multixform[id_C] = {id_CK, id_CKB};
+    iologic_rules[id_IDDR].port_xform[id_S] = id_SR;
+    iologic_rules[id_IDDR].port_xform[id_R] = id_SR;
+
+    // Handles pseudo-diff output buffers without finding multiple sinks
+    auto find_p_outbuf = [&](NetInfo *net) {
+        CellInfo *outbuf = nullptr;
+        for (auto &usr : net->users) {
+            IdString type = usr.cell->type;
+            if (type.in(id_IOB33_OUTBUF, id_IOB33M_OUTBUF, id_IOB18_OUTBUF_DCIEN, id_IOB18M_OUTBUF_DCIEN)) {
+                if (outbuf != nullptr)
+                    return (CellInfo *)nullptr; // drives multiple outputs
+                outbuf = usr.cell;
+            } else if (type == id_ODELAYE2) {
+                auto dataout = usr.cell->ports.find(id_DATAOUT);
+                if (dataout != usr.cell->ports.end()) {
+                    for (auto &user : dataout->second.net->users) {
+                        IdString dataout_type = user.cell->type;
+                        if (dataout_type.in(id_IOB18_OUTBUF_DCIEN, id_IOB18M_OUTBUF_DCIEN)) {
+                            if (outbuf != nullptr)
+                                return (CellInfo *)nullptr; // drives multiple outputs
+                            outbuf = user.cell;
+                        }
+                    }
+                } else {
+                    if (outbuf != nullptr)
+                        return (CellInfo *)nullptr; // drives multiple outputs
+                }
+            }
+        }
+        return outbuf;
+    };
+
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_ODDR) {
+            NetInfo *q = ci->getPort(id_Q);
+            if (q == nullptr || q->users.empty())
+                log_error("%s '%s' has disconnected Q output\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            BelId io_bel;
+            CellInfo *ob = find_p_outbuf(q);
+            if (ob != nullptr)
+                io_bel = ob->bel;
+            else
+                log_error("%s '%s' has illegal fanout on Q output\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            SiteIndex ol_site = get_ologic_site(io_bel);
+
+            PortRef dest_port = *q->users.begin();
+            auto is_tristate = dest_port.port == id_TRI;
+
+            dict<IdString, XFormRule> oddr_rules;
+            if (boost::contains(uarch->get_site_name(ol_site).str(ctx), "IOB18"))
+                oddr_rules[id_ODDR].new_type = is_tristate ? id_OLOGICE2_TFF : id_OLOGICE2_OUTFF;
+            else
+                oddr_rules[id_ODDR].new_type = is_tristate ? id_OLOGICE3_TFF : id_OLOGICE3_OUTFF;
+            oddr_rules[id_ODDR].port_xform[id_C] = id_CK;
+            oddr_rules[id_ODDR].port_xform[id_S] = id_SR;
+            oddr_rules[id_ODDR].port_xform[id_R] = id_SR;
+            xform_cell(oddr_rules, ci);
+
+            BelId oddr_bel = uarch->get_site_bel(ol_site, is_tristate ? ctx->id("TFF") : ctx->id("OUTFF"));
+            NPNR_ASSERT(oddr_bel != BelId());
+            log_info("   binding output DDR cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(oddr_bel));
+            ctx->bindBel(oddr_bel, ci, STRENGTH_LOCKED);
+        } else if (ci->type == id_IDDR) {
+            fold_inverter(ci, "C");
+
+            BelId io_bel;
+            NetInfo *d = ci->getPort(id_D);
+            if (!d || !d->driver.cell)
+                log_error("%s '%s' has disconnected D input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            CellInfo *drv = d->driver.cell;
+            if (boost::contains(drv->type.str(ctx), "INBUF_EN") || boost::contains(drv->type.str(ctx), "INBUF_DCIEN"))
+                io_bel = drv->bel;
+            else
+                log_error("%s '%s' has D input connected to illegal cell type %s\n", ci->type.c_str(ctx),
+                          ctx->nameOf(ci), drv->type.c_str(ctx));
+
+            SiteIndex il_site = get_ilogic_site(io_bel);
+
+            BelId iddr_bel = uarch->get_site_bel(il_site, ctx->id("IFF"));
+            NPNR_ASSERT(iddr_bel != BelId());
+            log_info("   binding input DDR cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(iddr_bel));
+            ctx->bindBel(iddr_bel, ci, STRENGTH_LOCKED);
+        }
+    }
+
+    flush_cells();
+    generic_xform(iologic_rules, false);
+    flush_cells();
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc
index aed4d4b704..229c3e379f 100644
--- a/himbaechel/uarch/xilinx/xilinx.cc
+++ b/himbaechel/uarch/xilinx/xilinx.cc
@@ -107,6 +107,16 @@ IdStringList XilinxImpl::get_site_bel_name(BelId bel) const
     return IdStringList::concat(get_site_name(get_bel_site(bel)), bel_name_in_site(bel));
 }
 
+WireId XilinxImpl::lookup_wire(int tile, IdString wire_name) const
+{
+    const auto &tdata = chip_tile_info(ctx->chip_info, tile);
+    for (int wire = 0; wire < tdata.wires.ssize(); wire++) {
+        if (IdString(tdata.wires[wire].name) == wire_name)
+            return ctx->normalise_wire(tile, wire);
+    }
+    return WireId();
+}
+
 void XilinxImpl::notifyBelChange(BelId bel, CellInfo *cell)
 {
     auto &ts = tile_status.at(bel.tile);
diff --git a/himbaechel/uarch/xilinx/xilinx.h b/himbaechel/uarch/xilinx/xilinx.h
index a7d3e6860b..ac127ab98b 100644
--- a/himbaechel/uarch/xilinx/xilinx.h
+++ b/himbaechel/uarch/xilinx/xilinx.h
@@ -149,6 +149,7 @@ struct XilinxImpl : HimbaechelAPI
     IdString bel_name_in_site(BelId bel) const;
     IdStringList get_site_bel_name(BelId bel) const;
     BelId get_site_bel(SiteIndex site, IdString bel_name) const;
+    WireId lookup_wire(int tile, IdString wire_name) const;
 
     int hclk_for_iob(BelId pad) const;
     int hclk_for_ioi(int tile) const;

From 1967db170d23bc978d678912ec81c6814818983b Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Fri, 27 Sep 2024 17:37:46 +0200
Subject: [PATCH 682/712] xilinx: Support for complex IOLOGIC

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/uarch/xilinx/pack.cc    |   2 +-
 himbaechel/uarch/xilinx/pack_io.cc | 262 +++++++++++++++++++++++++++++
 himbaechel/uarch/xilinx/xilinx.h   |   4 +
 3 files changed, 267 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/xilinx/pack.cc b/himbaechel/uarch/xilinx/pack.cc
index 1644e1882a..0bf9bbb67c 100644
--- a/himbaechel/uarch/xilinx/pack.cc
+++ b/himbaechel/uarch/xilinx/pack.cc
@@ -734,7 +734,7 @@ void XilinxImpl::pack()
     packer.prepare_clocking();
     packer.pack_constants();
     packer.pack_iologic();
-    // packer.pack_idelayctrl();
+    packer.pack_idelayctrl();
     packer.pack_clocking();
     packer.pack_muxfs();
     packer.pack_carries();
diff --git a/himbaechel/uarch/xilinx/pack_io.cc b/himbaechel/uarch/xilinx/pack_io.cc
index 2419822b16..0c2af4027a 100644
--- a/himbaechel/uarch/xilinx/pack_io.cc
+++ b/himbaechel/uarch/xilinx/pack_io.cc
@@ -547,6 +547,72 @@ SiteIndex XC7Packer::get_ilogic_site(BelId io_bel)
     NPNR_ASSERT_FALSE("failed to find ILOGIC");
 }
 
+SiteIndex XC7Packer::get_idelay_site(BelId io_bel)
+{
+    BelId ibc_bel;
+    if (boost::contains(uarch->bel_name_in_site(io_bel).str(ctx), "IOB18"))
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB18.INBUF_DCIEN"));
+    else
+        ibc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB33.INBUF_EN"));
+
+    NPNR_ASSERT(ibc_bel != BelId());
+
+    std::queue<WireId> visit;
+    visit.push(ctx->getBelPinWire(ibc_bel, id_OUT));
+
+    while (!visit.empty()) {
+        WireId cursor = visit.front();
+        visit.pop();
+        for (auto bp : ctx->getWireBelPins(cursor)) {
+            auto site = uarch->get_bel_site(bp.bel);
+            if (boost::starts_with(uarch->get_site_name(site).str(ctx), "IDELAY"))
+                return site;
+        }
+        for (auto pip : ctx->getPipsDownhill(cursor))
+            visit.push(ctx->getPipDstWire(pip));
+    }
+    NPNR_ASSERT_FALSE("failed to find IDELAY");
+}
+
+SiteIndex XC7Packer::get_odelay_site(BelId io_bel)
+{
+    BelId obc_bel;
+    if (boost::contains(uarch->bel_name_in_site(io_bel).str(ctx), "IOB18"))
+        obc_bel = uarch->get_site_bel(uarch->get_bel_site(io_bel), ctx->id("IOB18.OUTBUF_DCIEN"));
+    else
+        log_error("BEL %s is located on a high range bank. High range banks do not have ODELAY\n",
+                  ctx->nameOfBel(io_bel));
+
+    std::queue<WireId> visit;
+    visit.push(ctx->getBelPinWire(obc_bel, id_IN));
+
+    while (!visit.empty()) {
+        WireId cursor = visit.front();
+        visit.pop();
+        for (auto bp : ctx->getWireBelPins(cursor)) {
+            auto site = uarch->get_bel_site(bp.bel);
+            if (boost::starts_with(uarch->get_site_name(site).str(ctx), "ODELAY"))
+                return site;
+        }
+        for (auto pip : ctx->getPipsUphill(cursor))
+            visit.push(ctx->getPipSrcWire(pip));
+    }
+    NPNR_ASSERT_FALSE("failed to find ODELAY");
+}
+
+SiteIndex XC7Packer::get_ioctrl_site(BelId io_bel)
+{
+    int hclk_tile = uarch->hclk_for_iob(io_bel);
+    const auto &extra_data = uarch->tile_extra_data(hclk_tile);
+
+    for (int site = 0; site < extra_data->sites.ssize(); site++) {
+        auto &site_data = extra_data->sites[site];
+        if (boost::starts_with(IdString(site_data.name_prefix).str(ctx), "IDELAYCTRL"))
+            return SiteIndex(hclk_tile, site);
+    }
+
+    NPNR_ASSERT_FALSE("failed to find IOCTRL");
+}
 
 void XC7Packer::fold_inverter(CellInfo *cell, std::string port)
 {
@@ -586,6 +652,14 @@ void XC7Packer::pack_iologic()
     iologic_rules[id_IDDR].port_xform[id_S] = id_SR;
     iologic_rules[id_IDDR].port_xform[id_R] = id_SR;
 
+    // SERDES
+    iologic_rules[id_ISERDESE2].new_type = id_ISERDESE2_ISERDESE2;
+    iologic_rules[id_OSERDESE2].new_type = id_OSERDESE2_OSERDESE2;
+
+    // DELAY
+    iologic_rules[id_IDELAYE2].new_type = id_IDELAYE2_IDELAYE2;
+    iologic_rules[id_ODELAYE2].new_type = id_ODELAYE2_ODELAYE2;
+
     // Handles pseudo-diff output buffers without finding multiple sinks
     auto find_p_outbuf = [&](NetInfo *net) {
         CellInfo *outbuf = nullptr;
@@ -615,6 +689,59 @@ void XC7Packer::pack_iologic()
         return outbuf;
     };
 
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_IDELAYE2) {
+            NetInfo *d = ci->getPort(id_IDATAIN);
+            if (!d || !d->driver.cell)
+                log_error("%s '%s' has disconnected IDATAIN input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            CellInfo *drv = d->driver.cell;
+            BelId io_bel;
+            if (boost::contains(drv->type.str(ctx), "INBUF_EN") || boost::contains(drv->type.str(ctx), "INBUF_DCIEN"))
+                io_bel = drv->bel;
+            else
+                log_error("%s '%s' has IDATAIN input connected to illegal cell type %s\n", ci->type.c_str(ctx),
+                          ctx->nameOf(ci), drv->type.c_str(ctx));
+            SiteIndex iol_site = get_idelay_site(io_bel);
+
+            BelId idelay_bel = uarch->get_site_bel(iol_site, id_IDELAYE2);
+            NPNR_ASSERT(idelay_bel != BelId());
+            log_info("   binding input delay cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(idelay_bel));
+            ctx->bindBel(idelay_bel, ci, STRENGTH_LOCKED);
+
+            ci->attrs[id_X_IO_BEL] = ctx->getBelName(io_bel).str(ctx);
+            iodelay_to_io[ci->name] = io_bel;
+        } else if (ci->type == id_ODELAYE2) {
+            NetInfo *dataout = ci->getPort(id_DATAOUT);
+            if (!dataout || dataout->users.empty())
+                log_error("%s '%s' has disconnected DATAOUT input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            BelId io_bel;
+            auto no_users = dataout->users.entries();
+            for (auto userport : dataout->users) {
+                CellInfo *user = userport.cell;
+                auto user_type = user->type.str(ctx);
+                // OBUFDS has the negative pin connected to an inverter
+                if (no_users == 2 && user_type == "INVERTER")
+                    continue;
+                if (boost::contains(user_type, "OUTBUF_EN") || boost::contains(user_type, "OUTBUF_DCIEN"))
+                    io_bel = user->bel;
+                else
+                    // TODO: support SIGNAL_PATTERN = CLOCK
+                    log_error("%s '%s' has DATAOUT connected to unsupported cell type %s\n", ci->type.c_str(ctx),
+                              ctx->nameOf(ci), user_type.c_str());
+            }
+            SiteIndex iol_site = get_odelay_site(io_bel);
+
+            BelId odelay_bel = uarch->get_site_bel(iol_site, id_ODELAYE2);
+            NPNR_ASSERT(odelay_bel != BelId());
+            log_info("   binding output delay cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(odelay_bel));
+            ctx->bindBel(odelay_bel, ci, STRENGTH_LOCKED);
+
+            ci->attrs[id_X_IO_BEL] = ctx->getBelName(io_bel).str(ctx);
+            iodelay_to_io[ci->name] = io_bel;
+        }
+    }
+
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
         if (ci->type == id_ODDR) {
@@ -646,6 +773,28 @@ void XC7Packer::pack_iologic()
             NPNR_ASSERT(oddr_bel != BelId());
             log_info("   binding output DDR cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(oddr_bel));
             ctx->bindBel(oddr_bel, ci, STRENGTH_LOCKED);
+        } else if (ci->type == id_OSERDESE2) {
+            NetInfo *q = ci->getPort(id_OQ);
+            NetInfo *ofb = ci->getPort(id_OFB);
+            bool q_disconnected = !q || q->users.empty();
+            bool ofb_disconnected = !ofb || ofb->users.empty();
+            if (q_disconnected && ofb_disconnected) {
+                log_error("%s '%s' has disconnected OQ/OFB output ports\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+            }
+            BelId io_bel;
+            CellInfo *ob = !q_disconnected ? find_p_outbuf(q) : find_p_outbuf(ofb);
+            if (ob != nullptr)
+                io_bel = ob->bel;
+            else
+                log_error("%s '%s' has illegal fanout on OQ or OFB output\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+
+            SiteIndex ol_site = get_ologic_site(io_bel);
+
+            BelId oserdes_bel = uarch->get_site_bel(ol_site, id_OSERDESE2);
+            NPNR_ASSERT(oserdes_bel != BelId());
+            log_info("   binding output SERDES cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(oserdes_bel));
+            ctx->bindBel(oserdes_bel, ci, STRENGTH_LOCKED);
+
         } else if (ci->type == id_IDDR) {
             fold_inverter(ci, "C");
 
@@ -656,6 +805,8 @@ void XC7Packer::pack_iologic()
             CellInfo *drv = d->driver.cell;
             if (boost::contains(drv->type.str(ctx), "INBUF_EN") || boost::contains(drv->type.str(ctx), "INBUF_DCIEN"))
                 io_bel = drv->bel;
+            else if (boost::contains(drv->type.str(ctx), "IDELAYE2") && d->driver.port == id_DATAOUT)
+                io_bel = iodelay_to_io.at(drv->name);
             else
                 log_error("%s '%s' has D input connected to illegal cell type %s\n", ci->type.c_str(ctx),
                           ctx->nameOf(ci), drv->type.c_str(ctx));
@@ -666,6 +817,45 @@ void XC7Packer::pack_iologic()
             NPNR_ASSERT(iddr_bel != BelId());
             log_info("   binding input DDR cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(iddr_bel));
             ctx->bindBel(iddr_bel, ci, STRENGTH_LOCKED);
+        } else if (ci->type == id_ISERDESE2) {
+            fold_inverter(ci, "CLKB");
+            fold_inverter(ci, "OCLKB");
+
+            std::string iobdelay = str_or_default(ci->params, id_IOBDELAY, "NONE");
+            BelId io_bel;
+
+            if (iobdelay == "IFD") {
+                NetInfo *d = ci->getPort(id_DDLY);
+                if (!d || !d->driver.cell)
+                    log_error("%s '%s' has disconnected DDLY input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+                CellInfo *drv = d->driver.cell;
+                if (boost::contains(drv->type.str(ctx), "IDELAYE2") && d->driver.port == id_DATAOUT)
+                    io_bel = iodelay_to_io.at(drv->name);
+                else
+                    log_error("%s '%s' has DDLY input connected to illegal cell type %s\n", ci->type.c_str(ctx),
+                              ctx->nameOf(ci), drv->type.c_str(ctx));
+            } else if (iobdelay == "NONE") {
+                NetInfo *d = ci->getPort(id_D);
+                if (!d || !d->driver.cell)
+                    log_error("%s '%s' has disconnected D input\n", ci->type.c_str(ctx), ctx->nameOf(ci));
+                CellInfo *drv = d->driver.cell;
+                if (boost::contains(drv->type.str(ctx), "INBUF_EN") ||
+                    boost::contains(drv->type.str(ctx), "INBUF_DCIEN"))
+                    io_bel = drv->bel;
+                else
+                    log_error("%s '%s' has D input connected to illegal cell type %s\n", ci->type.c_str(ctx),
+                              ctx->nameOf(ci), drv->type.c_str(ctx));
+            } else {
+                log_error("%s '%s' has unsupported IOBDELAY value '%s'\n", ci->type.c_str(ctx), ctx->nameOf(ci),
+                          iobdelay.c_str());
+            }
+
+            SiteIndex il_site = get_ilogic_site(io_bel);
+
+            BelId iserdes_bel = uarch->get_site_bel(il_site, id_ISERDESE2);
+            NPNR_ASSERT(iserdes_bel != BelId());
+            log_info("   binding input SERDES cell '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(iserdes_bel));
+            ctx->bindBel(iserdes_bel, ci, STRENGTH_LOCKED);
         }
     }
 
@@ -674,4 +864,76 @@ void XC7Packer::pack_iologic()
     flush_cells();
 }
 
+void XC7Packer::pack_idelayctrl()
+{
+    CellInfo *idelayctrl = nullptr;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id_IDELAYCTRL) {
+            if (idelayctrl)
+                log_error("Found more than one IDELAYCTRL cell!\n");
+            idelayctrl = ci;
+        }
+    }
+    if (!idelayctrl)
+        return;
+    std::set<SiteIndex> ioctrl_sites;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type.in(id_IDELAYE2_IDELAYE2, id_ODELAYE2_ODELAYE2)) {
+            if (ci->bel == BelId())
+                continue;
+            ioctrl_sites.insert(get_ioctrl_site(ctx->getBelByNameStr(ci->attrs.at(id_X_IO_BEL).as_string())));
+        }
+    }
+    if (ioctrl_sites.empty())
+        log_error("Found IDELAYCTRL but no I/ODELAYs\n");
+    NetInfo *rdy = idelayctrl->getPort(id_RDY);
+    idelayctrl->disconnectPort(id_RDY);
+    std::vector<NetInfo *> dup_rdys;
+    int i = 0;
+    for (auto site : ioctrl_sites) {
+        CellInfo *dup_idc =
+                create_cell(id_IDELAYCTRL, int_name(idelayctrl->name, "CTRL_DUP_" + std::to_string(i), false));
+        dup_idc->connectPort(id_REFCLK, idelayctrl->getPort(id_REFCLK));
+        dup_idc->connectPort(id_RST, idelayctrl->getPort(id_RST));
+        if (rdy) {
+            NetInfo *dup_rdy =
+                    (ioctrl_sites.size() == 1)
+                            ? rdy
+                            : create_internal_net(idelayctrl->name, "CTRL_DUP_" + std::to_string(i) + "_RDY", false);
+            dup_idc->connectPort(id_RDY, dup_rdy);
+            dup_rdys.push_back(dup_rdy);
+        }
+        BelId idc_bel = uarch->get_site_bel(site, id_IDELAYCTRL);
+        NPNR_ASSERT(idc_bel != BelId());
+        ctx->bindBel(idc_bel, dup_idc, STRENGTH_LOCKED);
+        ++i;
+    }
+    idelayctrl->disconnectPort(id_REFCLK);
+    idelayctrl->disconnectPort(id_RST);
+
+    if (rdy != nullptr) {
+        // AND together all the RDY signals
+        std::vector<NetInfo *> int_anded_rdy;
+        int_anded_rdy.push_back(dup_rdys.front());
+        for (size_t j = 1; j < dup_rdys.size(); j++) {
+            NetInfo *anded_net =
+                    (j == (dup_rdys.size() - 1))
+                            ? rdy
+                            : create_internal_net(idelayctrl->name, "ANDED_RDY_" + std::to_string(j), false);
+            create_lut(idelayctrl->name.str(ctx) + "/RDY_AND_LUT_" + std::to_string(j),
+                       {int_anded_rdy.at(j - 1), dup_rdys.at(j)}, anded_net, Property(8));
+            int_anded_rdy.push_back(anded_net);
+        }
+    }
+
+    packed_cells.insert(idelayctrl->name);
+    flush_cells();
+
+    ioctrl_rules[id_IDELAYCTRL].new_type = id_IDELAYCTRL_IDELAYCTRL;
+
+    generic_xform(ioctrl_rules);
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/xilinx/xilinx.h b/himbaechel/uarch/xilinx/xilinx.h
index ac127ab98b..5ff77855c8 100644
--- a/himbaechel/uarch/xilinx/xilinx.h
+++ b/himbaechel/uarch/xilinx/xilinx.h
@@ -70,6 +70,10 @@ struct SiteIndex
     int32_t site;
     bool operator==(const SiteIndex &other) const { return tile == other.tile && site == other.site; }
     bool operator!=(const SiteIndex &other) const { return tile != other.tile || site != other.site; }
+    bool operator<(const SiteIndex &other) const
+    {
+        return (tile < other.tile) || (tile == other.tile && site < other.site);
+    }
     unsigned hash() const { return mkhash(tile, site); }
 };
 

From fcdaf3f86cfdf6769e95ba138980cb5df2e3ee88 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 30 Sep 2024 11:32:41 +0200
Subject: [PATCH 683/712] Remove fpga_interchange

Signed-off-by: gatecat <gatecat@ds0.me>
---
 .github/ci/build_interchange.sh               |   64 -
 .github/workflows/interchange_ci.yml.disable  |  132 -
 .gitmodules                                   |    3 -
 3rdparty/fpga-interchange-schema              |    1 -
 CMakeLists.txt                                |    4 +-
 fpga_interchange/README.md                    |   78 -
 fpga_interchange/arch.cc                      | 2144 -----------------
 fpga_interchange/arch.h                       | 1196 ---------
 fpga_interchange/arch_iterators.h             |  497 ----
 fpga_interchange/arch_pack_clusters.cc        | 1076 ---------
 fpga_interchange/arch_pack_io.cc              |  356 ---
 fpga_interchange/arch_place_constr.cc         |  106 -
 fpga_interchange/arch_pybindings.cc           |   79 -
 fpga_interchange/arch_pybindings.h            |  110 -
 fpga_interchange/archdefs.h                   |  129 -
 fpga_interchange/cell_parameters.cc           |  222 --
 fpga_interchange/cell_parameters.h            |   54 -
 fpga_interchange/chipdb.h                     |  547 -----
 fpga_interchange/cost_map.cc                  |  400 ---
 fpga_interchange/cost_map.h                   |   67 -
 fpga_interchange/dedicated_interconnect.cc    |  902 -------
 fpga_interchange/dedicated_interconnect.h     |  124 -
 fpga_interchange/examples/README.md           |   76 -
 fpga_interchange/examples/boards.cmake        |   50 -
 .../examples/boards/CMakeLists.txt            |   49 -
 fpga_interchange/examples/chipdb.cmake        |  341 ---
 fpga_interchange/examples/chipdb_nexus.cmake  |  101 -
 fpga_interchange/examples/chipdb_xilinx.cmake |  138 --
 .../examples/devices/CMakeLists.txt           |   11 -
 .../examples/devices/LIFCL-17/CMakeLists.txt  |   13 -
 .../examples/devices/LIFCL-17/test_data.yaml  |    8 -
 .../examples/devices/LIFCL-40/CMakeLists.txt  |   13 -
 .../examples/devices/LIFCL-40/test_data.yaml  |    8 -
 .../examples/devices/xc7a100t/CMakeLists.txt  |   14 -
 .../examples/devices/xc7a100t/test_data.yaml  |   36 -
 .../examples/devices/xc7a200t/CMakeLists.txt  |   14 -
 .../examples/devices/xc7a200t/test_data.yaml  |   36 -
 .../examples/devices/xc7a35t/CMakeLists.txt   |   14 -
 .../examples/devices/xc7a35t/test_data.yaml   |   40 -
 .../examples/devices/xc7z010/CMakeLists.txt   |   14 -
 .../examples/devices/xc7z010/test_data.yaml   |   36 -
 fpga_interchange/examples/remap_nexus.v       |  180 --
 fpga_interchange/examples/remap_xilinx.v      |   11 -
 fpga_interchange/examples/tests.cmake         |  405 ----
 .../examples/tests/CMakeLists.txt             |   10 -
 .../examples/tests/const_wire/CMakeLists.txt  |    7 -
 .../examples/tests/const_wire/arty100t.xdc    |    9 -
 .../examples/tests/const_wire/arty35t.xdc     |    9 -
 .../examples/tests/const_wire/basys3.xdc      |    9 -
 .../examples/tests/const_wire/run.tcl         |   14 -
 .../examples/tests/const_wire/wire.v          |    8 -
 .../examples/tests/counter/CMakeLists.txt     |   19 -
 .../examples/tests/counter/arty100t.xdc       |   14 -
 .../examples/tests/counter/arty35t.xdc        |   14 -
 .../examples/tests/counter/basys3.xdc         |   14 -
 .../examples/tests/counter/counter.v          |   17 -
 .../examples/tests/counter/lifcl17.xdc        |   14 -
 .../examples/tests/counter/lifcl40evn.xdc     |   13 -
 .../examples/tests/counter/run_nexus.tcl      |   15 -
 .../examples/tests/counter/run_xilinx.tcl     |   15 -
 .../examples/tests/counter/zybo.xdc           |   14 -
 .../examples/tests/ff/CMakeLists.txt          |    8 -
 .../examples/tests/ff/arty100t.xdc            |    9 -
 .../examples/tests/ff/arty35t.xdc             |    9 -
 fpga_interchange/examples/tests/ff/basys3.xdc |    9 -
 fpga_interchange/examples/tests/ff/ff.v       |   11 -
 fpga_interchange/examples/tests/ff/run.tcl    |   14 -
 .../examples/tests/lut/CMakeLists.txt         |    8 -
 .../examples/tests/lut/arty100t.xdc           |    7 -
 .../examples/tests/lut/arty35t.xdc            |    7 -
 .../examples/tests/lut/basys3.xdc             |    7 -
 fpga_interchange/examples/tests/lut/lut.v     |    5 -
 fpga_interchange/examples/tests/lut/run.tcl   |   14 -
 .../examples/tests/lut_nexus/CMakeLists.txt   |   21 -
 .../examples/tests/lut_nexus/empty.xdc        |    0
 .../examples/tests/lut_nexus/lut.v            |    7 -
 .../examples/tests/lut_nexus/run.tcl          |   14 -
 .../examples/tests/lutram/CMakeLists.txt      |    8 -
 .../examples/tests/lutram/basys3.pcf          |   41 -
 .../examples/tests/lutram/basys3.xdc          |   80 -
 .../examples/tests/lutram/lutram.v            |   24 -
 .../examples/tests/lutram/run.tcl             |   17 -
 .../examples/tests/obuftds/CMakeLists.txt     |    7 -
 .../examples/tests/obuftds/basys3.xdc         |    9 -
 .../examples/tests/obuftds/obuftds.v          |   37 -
 .../examples/tests/obuftds/run.tcl            |   14 -
 .../examples/tests/ram/CMakeLists.txt         |    8 -
 .../examples/tests/ram/basys3.pcf             |   41 -
 .../examples/tests/ram/basys3.xdc             |   80 -
 fpga_interchange/examples/tests/ram/ram.v     |  134 --
 fpga_interchange/examples/tests/ram/run.tcl   |   17 -
 .../examples/tests/ram_nexus/CMakeLists.txt   |   10 -
 .../examples/tests/ram_nexus/lifcl40evn.xdc   |   57 -
 .../examples/tests/ram_nexus/ram_nexus.v      |  123 -
 .../examples/tests/ram_nexus/run_nexus.tcl    |   15 -
 .../examples/tests/wire/CMakeLists.txt        |   17 -
 .../examples/tests/wire/arty100t.xdc          |    5 -
 .../examples/tests/wire/arty35t.xdc           |    5 -
 .../examples/tests/wire/basys3.xdc            |    5 -
 .../examples/tests/wire/lifcl40evn.xdc        |    5 -
 .../examples/tests/wire/nexys_video.xdc       |    5 -
 fpga_interchange/examples/tests/wire/run.tcl  |   14 -
 .../examples/tests/wire/run_nexus.tcl         |   14 -
 fpga_interchange/examples/tests/wire/wire.v   |    5 -
 fpga_interchange/examples/tests/wire/zybo.xdc |    5 -
 fpga_interchange/family.cmake                 |   63 -
 fpga_interchange/flat_wire_map.h              |  121 -
 fpga_interchange/fpga_interchange.cpp         | 1153 ---------
 fpga_interchange/fpga_interchange.h           |   35 -
 fpga_interchange/globals.cc                   |  276 ---
 fpga_interchange/lookahead.capnp              |   61 -
 fpga_interchange/lookahead.cc                 | 1543 ------------
 fpga_interchange/lookahead.h                  |   98 -
 fpga_interchange/luts.cc                      |  554 -----
 fpga_interchange/luts.h                       |  139 --
 fpga_interchange/macros.cc                    |  180 --
 fpga_interchange/main.cc                      |  126 -
 fpga_interchange/pseudo_pip_model.cc          |  509 ----
 fpga_interchange/pseudo_pip_model.h           |  125 -
 fpga_interchange/sampler.cc                   |  174 --
 fpga_interchange/sampler.h                    |   69 -
 fpga_interchange/site_arch.cc                 |  489 ----
 fpga_interchange/site_arch.h                  |  810 -------
 fpga_interchange/site_arch.impl.h             |  327 ---
 fpga_interchange/site_lut_mapping_cache.cc    |  197 --
 fpga_interchange/site_lut_mapping_cache.h     |  179 --
 fpga_interchange/site_router.cc               | 1463 -----------
 fpga_interchange/site_router.h                |   58 -
 fpga_interchange/site_routing_cache.cc        |  209 --
 fpga_interchange/site_routing_cache.h         |  132 -
 fpga_interchange/site_routing_storage.h       |  161 --
 fpga_interchange/type_wire.cc                 |   82 -
 fpga_interchange/type_wire.h                  |   89 -
 fpga_interchange/xdc.cc                       |  230 --
 fpga_interchange/xdc.h                        |   41 -
 135 files changed, 2 insertions(+), 20757 deletions(-)
 delete mode 100755 .github/ci/build_interchange.sh
 delete mode 100644 .github/workflows/interchange_ci.yml.disable
 delete mode 160000 3rdparty/fpga-interchange-schema
 delete mode 100644 fpga_interchange/README.md
 delete mode 100644 fpga_interchange/arch.cc
 delete mode 100644 fpga_interchange/arch.h
 delete mode 100644 fpga_interchange/arch_iterators.h
 delete mode 100644 fpga_interchange/arch_pack_clusters.cc
 delete mode 100644 fpga_interchange/arch_pack_io.cc
 delete mode 100644 fpga_interchange/arch_place_constr.cc
 delete mode 100644 fpga_interchange/arch_pybindings.cc
 delete mode 100644 fpga_interchange/arch_pybindings.h
 delete mode 100644 fpga_interchange/archdefs.h
 delete mode 100644 fpga_interchange/cell_parameters.cc
 delete mode 100644 fpga_interchange/cell_parameters.h
 delete mode 100644 fpga_interchange/chipdb.h
 delete mode 100644 fpga_interchange/cost_map.cc
 delete mode 100644 fpga_interchange/cost_map.h
 delete mode 100644 fpga_interchange/dedicated_interconnect.cc
 delete mode 100644 fpga_interchange/dedicated_interconnect.h
 delete mode 100644 fpga_interchange/examples/README.md
 delete mode 100644 fpga_interchange/examples/boards.cmake
 delete mode 100644 fpga_interchange/examples/boards/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/chipdb.cmake
 delete mode 100644 fpga_interchange/examples/chipdb_nexus.cmake
 delete mode 100644 fpga_interchange/examples/chipdb_xilinx.cmake
 delete mode 100644 fpga_interchange/examples/devices/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/LIFCL-17/test_data.yaml
 delete mode 100644 fpga_interchange/examples/devices/LIFCL-40/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/LIFCL-40/test_data.yaml
 delete mode 100644 fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/xc7a100t/test_data.yaml
 delete mode 100644 fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/xc7a200t/test_data.yaml
 delete mode 100644 fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/xc7a35t/test_data.yaml
 delete mode 100644 fpga_interchange/examples/devices/xc7z010/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/devices/xc7z010/test_data.yaml
 delete mode 100644 fpga_interchange/examples/remap_nexus.v
 delete mode 100644 fpga_interchange/examples/remap_xilinx.v
 delete mode 100644 fpga_interchange/examples/tests.cmake
 delete mode 100644 fpga_interchange/examples/tests/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/const_wire/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/const_wire/arty100t.xdc
 delete mode 100644 fpga_interchange/examples/tests/const_wire/arty35t.xdc
 delete mode 100644 fpga_interchange/examples/tests/const_wire/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/const_wire/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/const_wire/wire.v
 delete mode 100644 fpga_interchange/examples/tests/counter/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/counter/arty100t.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/arty35t.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/counter.v
 delete mode 100644 fpga_interchange/examples/tests/counter/lifcl17.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/lifcl40evn.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/run_nexus.tcl
 delete mode 100644 fpga_interchange/examples/tests/counter/run_xilinx.tcl
 delete mode 100644 fpga_interchange/examples/tests/counter/zybo.xdc
 delete mode 100644 fpga_interchange/examples/tests/ff/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/ff/arty100t.xdc
 delete mode 100644 fpga_interchange/examples/tests/ff/arty35t.xdc
 delete mode 100644 fpga_interchange/examples/tests/ff/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/ff/ff.v
 delete mode 100644 fpga_interchange/examples/tests/ff/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/lut/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/lut/arty100t.xdc
 delete mode 100644 fpga_interchange/examples/tests/lut/arty35t.xdc
 delete mode 100644 fpga_interchange/examples/tests/lut/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/lut/lut.v
 delete mode 100644 fpga_interchange/examples/tests/lut/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/lut_nexus/empty.xdc
 delete mode 100644 fpga_interchange/examples/tests/lut_nexus/lut.v
 delete mode 100644 fpga_interchange/examples/tests/lut_nexus/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/lutram/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/lutram/basys3.pcf
 delete mode 100644 fpga_interchange/examples/tests/lutram/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/lutram/lutram.v
 delete mode 100644 fpga_interchange/examples/tests/lutram/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/obuftds/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/obuftds/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/obuftds/obuftds.v
 delete mode 100644 fpga_interchange/examples/tests/obuftds/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/ram/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/ram/basys3.pcf
 delete mode 100644 fpga_interchange/examples/tests/ram/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/ram/ram.v
 delete mode 100644 fpga_interchange/examples/tests/ram/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc
 delete mode 100644 fpga_interchange/examples/tests/ram_nexus/ram_nexus.v
 delete mode 100644 fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl
 delete mode 100644 fpga_interchange/examples/tests/wire/CMakeLists.txt
 delete mode 100644 fpga_interchange/examples/tests/wire/arty100t.xdc
 delete mode 100644 fpga_interchange/examples/tests/wire/arty35t.xdc
 delete mode 100644 fpga_interchange/examples/tests/wire/basys3.xdc
 delete mode 100644 fpga_interchange/examples/tests/wire/lifcl40evn.xdc
 delete mode 100644 fpga_interchange/examples/tests/wire/nexys_video.xdc
 delete mode 100644 fpga_interchange/examples/tests/wire/run.tcl
 delete mode 100644 fpga_interchange/examples/tests/wire/run_nexus.tcl
 delete mode 100644 fpga_interchange/examples/tests/wire/wire.v
 delete mode 100644 fpga_interchange/examples/tests/wire/zybo.xdc
 delete mode 100644 fpga_interchange/family.cmake
 delete mode 100644 fpga_interchange/flat_wire_map.h
 delete mode 100644 fpga_interchange/fpga_interchange.cpp
 delete mode 100644 fpga_interchange/fpga_interchange.h
 delete mode 100644 fpga_interchange/globals.cc
 delete mode 100644 fpga_interchange/lookahead.capnp
 delete mode 100644 fpga_interchange/lookahead.cc
 delete mode 100644 fpga_interchange/lookahead.h
 delete mode 100644 fpga_interchange/luts.cc
 delete mode 100644 fpga_interchange/luts.h
 delete mode 100644 fpga_interchange/macros.cc
 delete mode 100644 fpga_interchange/main.cc
 delete mode 100644 fpga_interchange/pseudo_pip_model.cc
 delete mode 100644 fpga_interchange/pseudo_pip_model.h
 delete mode 100644 fpga_interchange/sampler.cc
 delete mode 100644 fpga_interchange/sampler.h
 delete mode 100644 fpga_interchange/site_arch.cc
 delete mode 100644 fpga_interchange/site_arch.h
 delete mode 100644 fpga_interchange/site_arch.impl.h
 delete mode 100644 fpga_interchange/site_lut_mapping_cache.cc
 delete mode 100644 fpga_interchange/site_lut_mapping_cache.h
 delete mode 100644 fpga_interchange/site_router.cc
 delete mode 100644 fpga_interchange/site_router.h
 delete mode 100644 fpga_interchange/site_routing_cache.cc
 delete mode 100644 fpga_interchange/site_routing_cache.h
 delete mode 100644 fpga_interchange/site_routing_storage.h
 delete mode 100644 fpga_interchange/type_wire.cc
 delete mode 100644 fpga_interchange/type_wire.h
 delete mode 100644 fpga_interchange/xdc.cc
 delete mode 100644 fpga_interchange/xdc.h

diff --git a/.github/ci/build_interchange.sh b/.github/ci/build_interchange.sh
deleted file mode 100755
index 3976ce4ea5..0000000000
--- a/.github/ci/build_interchange.sh
+++ /dev/null
@@ -1,64 +0,0 @@
-#!/bin/bash
-
-# Install capnproto libraries
-function build_capnp {
-    curl -O https://capnproto.org/capnproto-c++-0.8.0.tar.gz
-    tar zxf capnproto-c++-0.8.0.tar.gz
-    pushd capnproto-c++-0.8.0
-    ./configure
-    make -j`nproc` check
-    sudo make install
-    popd
-
-    git clone https://github.com/capnproto/capnproto-java.git
-    pushd capnproto-java
-    make -j`nproc`
-    sudo make install
-    popd
-}
-
-# Install latest Yosys
-function build_yosys {
-    DESTDIR=`pwd`/.yosys
-    pushd yosys
-    make -j`nproc`
-    sudo make install DESTDIR=$DESTDIR
-    popd
-}
-
-
-function get_dependencies {
-    # Install python-fpga-interchange libraries
-    git clone -b ${PYTHON_INTERCHANGE_TAG} https://github.com/SymbiFlow/python-fpga-interchange.git ${PYTHON_INTERCHANGE_PATH}
-    pushd ${PYTHON_INTERCHANGE_PATH}
-    git submodule update --init --recursive
-    python3 -m pip install -r requirements.txt
-    popd
-
-    if [ ${DEVICE} == "LIFCL-17"  ] || [ ${DEVICE} == "LIFCL-40"  ]; then
-        # Install prjoxide
-        curl --proto '=https' -sSf https://sh.rustup.rs | sh -s -- -y
-        git clone --recursive https://github.com/gatecat/prjoxide.git
-        pushd prjoxide/libprjoxide
-        # TODO: use a tag instead of a commit, like python-fpga-interchange
-        git reset --hard ${PRJOXIDE_REVISION}
-        PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide --all-features
-        popd
-    else
-        # Install RapidWright
-        git clone https://github.com/Xilinx/RapidWright.git ${RAPIDWRIGHT_PATH}
-        pushd ${RAPIDWRIGHT_PATH}
-        ./gradlew updateJars --no-watch-fs
-        make compile
-        popd
-    fi
-}
-
-function build_nextpnr {
-    build_capnp
-    mkdir build
-    pushd build
-    cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH} -DWERROR=on
-    make nextpnr-fpga_interchange -j`nproc`
-    popd
-}
diff --git a/.github/workflows/interchange_ci.yml.disable b/.github/workflows/interchange_ci.yml.disable
deleted file mode 100644
index 27b19c5a54..0000000000
--- a/.github/workflows/interchange_ci.yml.disable
+++ /dev/null
@@ -1,132 +0,0 @@
-name: FPGA interchange CI tests
-
-on: [push, pull_request]
-
-jobs:
-  Build-yosys:
-    runs-on: ubuntu-latest
-    steps:
-
-    - uses: actions/checkout@v2
-      with:
-        submodules: recursive
-
-    - uses: actions/setup-python@v2
-
-    - name: Install
-      run: |
-        sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig locales libtinfo-dev
-
-    - name: ccache
-      uses: hendrikmuhs/ccache-action@v1
-
-    - name: Get yosys
-      run: |
-        git clone https://github.com/YosysHQ/yosys.git
-        cd yosys
-        echo "YOSYS_SHA=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-    - name: Cache yosys installation
-      uses: actions/cache@v2
-      id: cache-yosys
-      with:
-        path: .yosys
-        key: cache-yosys-${{ env.YOSYS_SHA }}
-
-    - name: Build yosys
-      run: |
-        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
-        source ./.github/ci/build_interchange.sh
-        build_yosys
-      if: steps.cache-yosys.outputs.cache-hit != 'true'
-
-  Build-nextpnr:
-    runs-on: ubuntu-latest
-    steps:
-
-    - uses: actions/checkout@v2
-      with:
-        submodules: recursive
-
-    - uses: actions/setup-python@v2
-
-    - name: Install
-      run: |
-        sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
-
-    - name: ccache
-      uses: hendrikmuhs/ccache-action@v1
-
-    - name: Execute build nextpnr
-      run: |
-        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
-        source ./.github/ci/build_interchange.sh
-        build_nextpnr
-
-  Run-Tests:
-    runs-on: ubuntu-latest
-    needs: [Build-yosys, Build-nextpnr]
-    strategy:
-      # Don't terminate jobs when one fails.  This is important when
-      # debugging CI failures.
-      fail-fast: false
-      matrix:
-        device: [xc7a35t, xc7a100t, xc7a200t, xc7z010, LIFCL-17, LIFCL-40]
-    steps:
-
-    - uses: actions/checkout@v2
-      with:
-        submodules: recursive
-
-    - uses: actions/setup-python@v2
-
-    - name: Install
-      run: |
-        sudo apt-get update
-        sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
-
-    - name: ccache
-      uses: hendrikmuhs/ccache-action@v1
-
-    - name: Get yosys
-      run: |
-        git clone https://github.com/YosysHQ/yosys.git
-        cd yosys
-        echo "YOSYS_SHA=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-    - name: Cache yosys installation
-      uses: actions/cache@v2
-      id: cache-yosys
-      with:
-        path: .yosys
-        key: cache-yosys-${{ env.YOSYS_SHA }}
-
-    - name: Build yosys
-      run: |
-        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
-        source ./.github/ci/build_interchange.sh
-        build_yosys
-      if: steps.cache-yosys.outputs.cache-hit != 'true'
-
-    - name: Execute build interchange script
-      env:
-        RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
-        PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.20
-        PRJOXIDE_REVISION: 318331f8b30c2e2a31cc41d51f104b671e180a8a
-        DEVICE: ${{ matrix.device }}
-      run: |
-        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
-        source ./.github/ci/build_interchange.sh
-        build_nextpnr && get_dependencies
-
-    - name: Run tests
-      env:
-        DEVICE: ${{ matrix.device }}
-      run: |
-        export PATH="$GITHUB_WORKSPACE/.yosys/usr/local/bin:$PATH"
-        which yosys
-        cd build
-        make all-$DEVICE-tests -j`nproc`
diff --git a/.gitmodules b/.gitmodules
index c03206a37f..7fec9e58bf 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,6 @@
 [submodule "tests"]
 	path = tests
 	url = https://github.com/YosysHQ/nextpnr-tests
-[submodule "fpga-interchange-schema"]
-	path = 3rdparty/fpga-interchange-schema
-	url = https://github.com/SymbiFlow/fpga-interchange-schema.git
 [submodule "himbaechel/uarch/xilinx/meta"]
 	path = himbaechel/uarch/xilinx/meta
 	url = https://github.com/gatecat/nextpnr-xilinx-meta
diff --git a/3rdparty/fpga-interchange-schema b/3rdparty/fpga-interchange-schema
deleted file mode 160000
index 6b29737886..0000000000
--- a/3rdparty/fpga-interchange-schema
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 6b2973788692be86c4a8b2cff1353e603e5857a3
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5b4604a4a5..9ae095e075 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -108,9 +108,9 @@ endif()
 set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
 
 # List of families to build
-set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2 mistral himbaechel)
+set(FAMILIES generic ice40 ecp5 nexus gowin machxo2 mistral himbaechel)
 set(STABLE_FAMILIES generic ice40 ecp5)
-set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2 mistral himbaechel)
+set(EXPERIMENTAL_FAMILIES nexus gowin machxo2 mistral himbaechel)
 
 set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
 set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
diff --git a/fpga_interchange/README.md b/fpga_interchange/README.md
deleted file mode 100644
index f5530c0e6a..0000000000
--- a/fpga_interchange/README.md
+++ /dev/null
@@ -1,78 +0,0 @@
-## FPGA interchange nextpnr architecture
-
-This nextpnr architecture is a meta architecture that in theory will implement
-any architecture that emits a complete FPGA interchange device database.
-
-### FPGA interchange
-
-The FPGA interchange is a set of file formats intended to describe any modern
-island based FPGA.  It consists of three primary file formats:
-
- - Device database
-   - This is a description of a particular FPGA fabric.  This description
-     includes placement locations, placement constraints and a complete
-     description of the routing fabric.
-   - This file will also include timing information once added.
-
- - Logical netlist
-   - This is the output of a synthesis tool.  This is equivalent to the
-     Yosys JSON format, EDIF, or eblif.
-   - As part of future nextpnr development, a frontend will be added that
-     takes this format as input.
-
- - Physical netlist
-   - This is the output of a place and route tool. It can describe a clustered
-     design, a partially or fully placed design, and a partially or fully
-     routed design.
-
-### Current development status
-
-This architecture implementation can be compiled in conjunction with a FPGA
-interchange device database, and the outputs from
-`fpga_interchange.nextpnr_emit`, which is part of the
-[python-fpga-interchange](https://github.com/SymbiFlow/python-fpga-interchange/)
-library.
-
-The current implementation is missing essential features for place and route.
-As these features are added, this implementation will become more useful.
-
- - [ ] Logical netlist macro expansion is not implemented, meaning that any
-       macro primitives are unplaceable.  Common macro primitives examples are
-       differential IO buffers (IBUFDS) and some LUT RAM (e.g. RAM64X1D).
- - [ ] Timing information is missing from the FPGA interchange device
-       database, so it is also currently missing from the FPGA interchange
-       architecture.  Once timing information is added to the device database
-
-#### Weaknesses of current implementation
-
-Initial development on the following features is started, but needs more
-refinement.
-
- - [ ] BEL validity checking is too expensive.  The majority of the runtime
-       is currently in the LUT rotation.  Profiling, optimization and
-       algorithm review is likely required to bring strict legalisation
-       runtimes into expected levels.
- - [ ] The router lookahead is disabled by default.  Without the lookahead,
-       router runtime is terrible.  However the current lookahead
-       implementation is slow to compute and memory intensive, hence why it is
-       disabled by default.
- - [ ] Pseudo pips (e.g. pips that consume BELs and or site resources) and
-       pseudo site pips (e.g. site pips that route through BELs) consume site
-       wires to indicate that they block some resources.  This covers many
-       validity check cases, but misses some.  In particular, when a pseudo
-       pip / pseudo site pip has an implication on the constraint system (e.g.
-       LUT on a LUT-RAM BEL), an edge may be allowed incorrectly, resulting
-       in an illegal design.
-
-### FPGA interchange fabrics
-
-Xilinx 7-series, UltraScale and UltraScale+ fabrics have a
-device database generator, via [RapidWright](https://github.com/Xilinx/RapidWright).
-
-A Lattice Nexus device database is being worked on, via
-[prjoxide](https://github.com/gatecat/prjoxide).
-
-### FPGA interchange build system
-
-Construction of chipdb's is currently integrated into nextpnr's CMake build
-system.  See fpga\_interchange/examples/README.md for more details.
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
deleted file mode 100644
index bf7e9ff108..0000000000
--- a/fpga_interchange/arch.cc
+++ /dev/null
@@ -1,2144 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018-19  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "arch.h"
-
-#include <algorithm>
-#include <boost/algorithm/string.hpp>
-#include <boost/range/adaptor/reversed.hpp>
-#include <boost/uuid/detail/sha1.hpp>
-#include <cmath>
-#include <cstring>
-#include <queue>
-#include <set>
-
-#include "constraints.impl.h"
-#include "fpga_interchange.h"
-#include "log.h"
-#include "nextpnr.h"
-#include "placer1.h"
-#include "placer_heap.h"
-#include "router1.h"
-#include "router2.h"
-#include "timing.h"
-#include "util.h"
-#include "xdc.h"
-
-// Include tcl.h late because it messed with defines and let them leave the
-// scope of the header.
-#include <tcl.h>
-
-// #define DEBUG_BINDING
-// #define USE_LOOKAHEAD
-// #define DEBUG_CELL_PIN_MAPPING
-
-// Define to enable some idempotent sanity checks for some important
-// operations prior to placement and routing.
-#define IDEMPOTENT_CHECK
-
-NEXTPNR_NAMESPACE_BEGIN
-struct SiteBelPair
-{
-    std::string site;
-    IdString bel;
-
-    SiteBelPair() {}
-    SiteBelPair(std::string site, IdString bel) : site(site), bel(bel) {}
-
-    bool operator==(const SiteBelPair &other) const { return site == other.site && bel == other.bel; }
-    unsigned int hash() const { return mkhash(std::hash<std::string>()(site), bel.hash()); }
-};
-
-static std::pair<std::string, std::string> split_identifier_name_dot(const std::string &name)
-{
-    size_t first_dot = name.find('.');
-    NPNR_ASSERT(first_dot != std::string::npos);
-    return std::make_pair(name.substr(0, first_dot), name.substr(first_dot + 1));
-};
-
-// -----------------------------------------------------------------------
-
-void IdString::initialize_arch(const BaseCtx *ctx) {}
-
-// -----------------------------------------------------------------------
-
-static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
-
-static std::string sha1_hash(const char *data, size_t size)
-{
-    boost::uuids::detail::sha1 hasher;
-    hasher.process_bytes(data, size);
-
-    // unsigned int[5]
-    boost::uuids::detail::sha1::digest_type digest;
-    hasher.get_digest(digest);
-
-    std::ostringstream buf;
-    for (int i = 0; i < 5; ++i)
-        buf << std::hex << std::setfill('0') << std::setw(8) << digest[i];
-
-    return buf.str();
-}
-
-Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
-{
-    try {
-        blob_file.open(args.chipdb);
-        if (args.chipdb.empty() || !blob_file.is_open())
-            log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
-        const char *blob = reinterpret_cast<const char *>(blob_file.data());
-
-        chipdb_hash = sha1_hash(blob, blob_file.size());
-        chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(blob));
-    } catch (...) {
-        log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
-    }
-
-    if (chip_info->version != kExpectedChipInfoVersion) {
-        log_error("Expected chipdb with version %d found version %d\n", kExpectedChipInfoVersion, chip_info->version);
-    }
-
-    // Read strings from constids into IdString database, checking that list
-    // is unique and matches expected constid value.
-    const RelSlice<RelPtr<char>> &constids = *chip_info->constids;
-    for (size_t i = 0; i < constids.size(); ++i) {
-        IdString::initialize_add(this, constids[i].get(), i + 1);
-    }
-
-    id_GND = id("GND");
-    id_VCC = id("VCC");
-
-    // Sanity check cell name ids.
-    const CellMapPOD &cell_map = *chip_info->cell_map;
-    int32_t first_cell_id = cell_map.cell_names[0];
-    for (int32_t i = 0; i < cell_map.cell_names.ssize(); ++i) {
-        log_assert(cell_map.cell_names[i] == i + first_cell_id);
-    }
-
-    io_port_types.emplace(this->id("$nextpnr_ibuf"));
-    io_port_types.emplace(this->id("$nextpnr_obuf"));
-    io_port_types.emplace(this->id("$nextpnr_iobuf"));
-    io_port_types.emplace(this->id("$nextpnr_inv"));
-
-    if (!this->args.package.empty()) {
-        IdString package = this->id(this->args.package);
-        package_index = -1;
-        for (size_t i = 0; i < chip_info->packages.size(); ++i) {
-            if (IdString(chip_info->packages[i].package) == package) {
-                NPNR_ASSERT(package_index == -1);
-                package_index = i;
-            }
-        }
-
-        if (package_index == -1) {
-            log_error("Could not find package '%s' in chipdb.\n", this->args.package.c_str());
-        }
-    } else {
-        // Default to first package.
-        NPNR_ASSERT(chip_info->packages.size() > 0);
-        if (chip_info->packages.size() == 1) {
-            IdString package_name(chip_info->packages[0].package);
-            this->args.package = package_name.str(this);
-            package_index = 0;
-        } else {
-            log_info(
-                    "Package must be specified (with --package arg) when multiple packages are available, packages:\n");
-            for (const auto &package : chip_info->packages) {
-                log_info(" - %s\n", IdString(package.package).c_str(this));
-            }
-            log_error("--package is required!\n");
-        }
-    }
-
-    pool<SiteBelPair> site_bel_pads;
-    for (const auto &package_pin : chip_info->packages[package_index].pins) {
-        IdString site(package_pin.site);
-        IdString bel(package_pin.bel);
-        site_bel_pads.emplace(SiteBelPair(site.str(this), bel));
-    }
-
-    for (BelId bel : getBels()) {
-        auto &bel_data = bel_info(chip_info, bel);
-        const SiteInstInfoPOD &site = get_site_inst(bel);
-        auto iter = site_bel_pads.find(SiteBelPair(site.site_name.get(), IdString(bel_data.name)));
-        if (iter != site_bel_pads.end()) {
-            pads.emplace(bel);
-        }
-    }
-
-    explain_constraints = false;
-
-    int tile_type_index = 0;
-    size_t max_tag_count = 0;
-
-    for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
-        max_tag_count = std::max(max_tag_count, tile_type.tags.size());
-
-        auto &type_definition = constraints.definitions[tile_type_index++];
-        for (const ConstraintTagPOD &tag : tile_type.tags) {
-            type_definition.emplace_back();
-            auto &definition = type_definition.back();
-            definition.prefix = IdString(tag.tag_prefix);
-            definition.default_state = IdString(tag.default_state);
-            NPNR_ASSERT(tag.states.size() < kMaxState);
-
-            definition.states.reserve(tag.states.size());
-            for (auto state : tag.states) {
-                definition.states.push_back(IdString(state));
-            }
-        }
-
-        // Logic BELs (e.g. placable BELs) should always appear first in the
-        // bel data list.
-        //
-        // When iterating over BELs this property is depended on to skip
-        // non-placable BELs (e.g. routing BELs and site ports).
-        bool in_logic_bels = true;
-        for (const BelInfoPOD &bel_info : tile_type.bel_data) {
-            if (in_logic_bels && bel_info.category != BEL_CATEGORY_LOGIC) {
-                in_logic_bels = false;
-            }
-
-            if (!in_logic_bels) {
-                NPNR_ASSERT(bel_info.category != BEL_CATEGORY_LOGIC);
-            }
-        }
-    }
-
-    // Initially LutElement vectors for each tile type.
-    tile_type_index = 0;
-    max_lut_cells = 0;
-    max_lut_pins = 0;
-    lut_elements.resize(chip_info->tile_types.size());
-    for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
-        std::vector<LutElement> &elements = lut_elements[tile_type_index++];
-        elements.reserve(tile_type.lut_elements.size());
-
-        int lut_cells_count = 0;
-        for (auto &lut_element : tile_type.lut_elements) {
-            elements.emplace_back();
-
-            LutElement &element = elements.back();
-            element.width = lut_element.width;
-            for (auto &lut_bel : lut_element.lut_bels) {
-                IdString name(lut_bel.name);
-                auto result = element.lut_bels.emplace(name, LutBel());
-                NPNR_ASSERT(result.second);
-                LutBel &lut = result.first->second;
-
-                lut.name = name;
-
-                lut.low_bit = lut_bel.low_bit;
-                lut.high_bit = lut_bel.high_bit;
-
-                lut.pins.reserve(lut_bel.pins.size());
-                for (size_t i = 0; i < lut_bel.pins.size(); ++i) {
-                    IdString pin(lut_bel.pins[i]);
-                    lut.pins.push_back(pin);
-                    lut.pin_to_index[pin] = i;
-                }
-
-                lut.output_pin = IdString(lut_bel.out_pin);
-                lut_cells_count++;
-
-                max_lut_pins = std::max((int)lut_bel.pins.size(), max_lut_pins);
-            }
-
-            element.compute_pin_order();
-        }
-
-        max_lut_cells = std::max(lut_cells_count, max_lut_cells);
-    }
-
-    // Map lut cell types to their LutCellPOD
-    wire_lut = nullptr;
-    for (const LutCellPOD &lut_cell : chip_info->cell_map->lut_cells) {
-        IdString cell_type(lut_cell.cell);
-        auto result = lut_cells.emplace(cell_type, &lut_cell);
-        NPNR_ASSERT(result.second);
-
-        if (lut_cell.input_pins.size() == 1) {
-            // Only really expecting 1 single input LUT type!
-            NPNR_ASSERT(wire_lut == nullptr);
-            wire_lut = &lut_cell;
-        }
-    }
-
-    raw_bin_constant = std::regex("[01]+", std::regex_constants::ECMAScript | std::regex_constants::optimize);
-    verilog_bin_constant =
-            std::regex("([0-9]+)'b([01]+)", std::regex_constants::ECMAScript | std::regex_constants::optimize);
-    verilog_hex_constant =
-            std::regex("([0-9]+)'h([0-9a-fA-F]+)", std::regex_constants::ECMAScript | std::regex_constants::optimize);
-
-    default_tags.resize(max_tag_count);
-}
-
-void Arch::init()
-{
-#ifdef USE_LOOKAHEAD
-    lookahead.init(getCtx(), getCtx());
-#endif
-    dedicated_interconnect.init(getCtx());
-    cell_parameters.init(getCtx());
-
-    for (size_t tile_type = 0; tile_type < chip_info->tile_types.size(); ++tile_type) {
-        pseudo_pip_data.init_tile_type(getCtx(), tile_type);
-    }
-
-    // Warn if there is no preferred constant net defined in the architecture
-    IdString const_net_name(getCtx()->chip_info->constants->best_constant_net);
-    if (const_net_name == IdString()) {
-        log_warning("The architecture does not specify preferred constant net. Using VCC as default.\n");
-    }
-}
-
-// -----------------------------------------------------------------------
-
-std::string Arch::getChipName() const { return chip_info->name.get(); }
-
-// -----------------------------------------------------------------------
-
-IdString Arch::archArgsToId(ArchArgs args) const { return IdString(); }
-
-// -----------------------------------------------------------------------
-
-void Arch::setup_byname() const
-{
-    by_name_mutex.lock();
-
-    if (tile_by_name.empty()) {
-        for (int i = 0; i < chip_info->tiles.ssize(); i++) {
-            tile_by_name[id(chip_info->tiles[i].name.get())] = i;
-        }
-    }
-
-    if (site_by_name.empty()) {
-        for (int i = 0; i < chip_info->tiles.ssize(); i++) {
-            auto &tile = chip_info->tiles[i];
-            auto &tile_type = chip_info->tile_types[tile.type];
-            for (size_t j = 0; j < tile_type.site_types.size(); j++) {
-                auto &site = chip_info->sites[tile.sites[j]];
-                site_by_name[id(site.name.get())] = std::make_pair(i, j);
-            }
-        }
-    }
-
-    by_name_mutex.unlock();
-}
-
-BelId Arch::getBelByName(IdStringList name) const
-{
-    BelId ret;
-    if (name.ids.size() != 2) {
-        return BelId();
-    }
-
-    setup_byname();
-
-    int tile, site;
-    std::tie(tile, site) = site_by_name.at(name.ids[0]);
-    auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
-    IdString belname = name.ids[1];
-    for (int i = 0; i < tile_info.bel_data.ssize(); i++) {
-        if (tile_info.bel_data[i].site == site && tile_info.bel_data[i].name == belname.index) {
-            ret.tile = tile;
-            ret.index = i;
-            break;
-        }
-    }
-
-    return ret;
-}
-
-BelRange Arch::getBelsByTile(int x, int y) const
-{
-    BelRange br;
-
-    br.b.cursor_tile = get_tile_index(x, y);
-    br.e.cursor_tile = br.b.cursor_tile;
-    br.b.cursor_index = 0;
-    br.e.cursor_index = chip_info->tile_types[chip_info->tiles[br.b.cursor_tile].type].bel_data.size();
-    br.b.chip = chip_info;
-    br.e.chip = chip_info;
-
-    if (br.b != br.e) {
-        ++br.e;
-    }
-    return br;
-}
-
-WireId Arch::getBelPinWire(BelId bel, IdString pin) const
-{
-    NPNR_ASSERT(bel != BelId());
-
-    int pin_index = get_bel_pin_index(bel, pin);
-
-    auto &bel_data = bel_info(chip_info, bel);
-    NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
-
-    const int32_t *wires = bel_data.wires.get();
-    int32_t wire_index = wires[pin_index];
-    if (wire_index < 0) {
-        // This BEL pin is not connected.
-        return WireId();
-    } else {
-        return canonical_wire(chip_info, bel.tile, wire_index);
-    }
-}
-
-PortType Arch::getBelPinType(BelId bel, IdString pin) const
-{
-    NPNR_ASSERT(bel != BelId());
-
-    int pin_index = get_bel_pin_index(bel, pin);
-    auto &bel_data = bel_info(chip_info, bel);
-    NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
-    const int32_t *types = bel_data.types.get();
-    return PortType(types[pin_index]);
-}
-
-// -----------------------------------------------------------------------
-
-WireId Arch::getWireByName(IdStringList name) const
-{
-    WireId ret;
-    if (name.ids.size() != 2) {
-        return WireId();
-    }
-
-    setup_byname();
-
-    auto iter = site_by_name.find(name.ids[0]);
-    if (iter != site_by_name.end()) {
-        int tile;
-        int site;
-        std::tie(tile, site) = iter->second;
-        auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
-        IdString wirename = name.ids[1];
-        for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
-            if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == wirename.index) {
-                ret.tile = tile;
-                ret.index = i;
-                break;
-            }
-        }
-    } else {
-        int tile = tile_by_name.at(name.ids[0]);
-        auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
-        IdString wirename = name.ids[1];
-        for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
-            if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == wirename.index) {
-                int32_t node = chip_info->tiles[tile].tile_wire_to_node[i];
-                if (node == -1) {
-                    // Not a nodal wire
-                    ret.tile = tile;
-                    ret.index = i;
-                } else {
-                    // Is a nodal wire, set tile to -1
-                    ret.tile = -1;
-                    ret.index = node;
-                }
-                break;
-            }
-        }
-    }
-
-    return ret;
-}
-
-IdString Arch::getWireType(WireId wire) const
-{
-    int tile = wire.tile, index = wire.index;
-    if (tile == -1) {
-        // Nodal wire
-        const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
-        tile = wr.tile;
-        index = wr.index;
-    }
-    auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
-    if (index >= w2t.ssize())
-        return IdString();
-    int wire_type = w2t[index];
-    if (wire_type == -1)
-        return IdString();
-    return IdString(chip_info->wire_types[wire_type].name);
-}
-
-bool Arch::is_site_wire(WireId wire) const
-{
-    if (wire.tile == -1)
-        return false;
-    const auto &tile_type = loc_info(chip_info, wire);
-    return tile_type.wire_data[wire.index].site != -1;
-}
-
-WireCategory Arch::get_wire_category(WireId wire) const
-{
-    int tile = wire.tile, index = wire.index;
-    if (tile == -1) {
-        // Nodal wire
-        const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
-        tile = wr.tile;
-        index = wr.index;
-    }
-    auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
-    if (index >= w2t.ssize())
-        return WIRE_CAT_GENERAL;
-    int wire_type = w2t[index];
-    if (wire_type == -1)
-        return WIRE_CAT_GENERAL;
-    return WireCategory(chip_info->wire_types[wire_type].category);
-}
-
-std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
-
-// -----------------------------------------------------------------------
-
-PipId Arch::getPipByName(IdStringList name) const
-{
-    // PIP name structure:
-    // Tile PIP: <tile name>/<source wire name>.<destination wire name>
-    // Site PIP: <site name>/<bel name>/<input bel pin name>
-    // Site pin: <site name>/<bel name>
-    // Psuedo site PIP: <site name>/<source wire name>.<destination wire name>
-
-    setup_byname();
-
-    if (name.ids.size() == 3) {
-        // This is a Site PIP.
-        IdString site_name = name.ids[0];
-        IdString belname = name.ids[1];
-        IdString pinname = name.ids[2];
-
-        int tile;
-        int site;
-        std::tie(tile, site) = site_by_name.at(site_name);
-        auto tile_type_idx = chip_info->tiles[tile].type;
-        auto &tile_info = chip_info->tile_types[tile_type_idx];
-
-        std::array<IdString, 2> ids{name.ids[0], belname};
-        BelId bel = getBelByName(IdStringList(ids));
-        NPNR_ASSERT(bel != BelId());
-
-        int pin_index = get_bel_pin_index(bel, pinname);
-        NPNR_ASSERT(pin_index >= 0);
-
-        for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
-            if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index &&
-                tile_info.pip_data[i].extra_data == pin_index) {
-
-                PipId ret;
-                ret.tile = tile;
-                ret.index = i;
-                return ret;
-            }
-        }
-    } else {
-        auto iter = site_by_name.find(name.ids[0]);
-        if (iter != site_by_name.end()) {
-            // This is either a site pin or a psuedo site pip.
-            // psuedo site pips are <site>/<src site wire>.<dst site wire>
-            // site pins are <site>/<bel>
-            int tile;
-            int site;
-            std::tie(tile, site) = iter->second;
-            auto tile_type_idx = chip_info->tiles[tile].type;
-            auto &tile_info = chip_info->tile_types[tile_type_idx];
-
-            std::string pip_second = name.ids[1].str(this);
-            auto split = pip_second.find('.');
-            if (split == std::string::npos) {
-                // This is a site pin!
-                BelId bel = getBelByName(name);
-                NPNR_ASSERT(bel != BelId());
-
-                for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
-                    if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == bel.index) {
-
-                        PipId ret;
-                        ret.tile = tile;
-                        ret.index = i;
-                        return ret;
-                    }
-                }
-            } else {
-                // This is a psuedo site pip!
-                IdString src_site_wire = id(pip_second.substr(0, split));
-                IdString dst_site_wire = id(pip_second.substr(split + 1));
-                int32_t src_index = -1;
-                int32_t dst_index = -1;
-
-                for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
-                    if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == src_site_wire.index) {
-                        src_index = i;
-                        if (dst_index != -1) {
-                            break;
-                        }
-                    }
-                    if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == dst_site_wire.index) {
-                        dst_index = i;
-                        if (src_index != -1) {
-                            break;
-                        }
-                    }
-                }
-
-                NPNR_ASSERT(src_index != -1);
-                NPNR_ASSERT(dst_index != -1);
-
-                for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
-                    if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].src_index == src_index &&
-                        tile_info.pip_data[i].dst_index == dst_index) {
-
-                        PipId ret;
-                        ret.tile = tile;
-                        ret.index = i;
-                        return ret;
-                    }
-                }
-            }
-        } else {
-            int tile = tile_by_name.at(name.ids[0]);
-            size_t tile_type_idx = chip_info->tiles[tile].type;
-            auto &tile_info = chip_info->tile_types[tile_type_idx];
-
-            std::string pip_second = name.ids[1].str(this);
-            auto spn = split_identifier_name_dot(pip_second);
-            auto src_wire_name = id(spn.first);
-            auto dst_wire_name = id(spn.second);
-
-            int32_t src_index = -1;
-            int32_t dst_index = -1;
-            for (int i = 0; i < tile_info.wire_data.ssize(); i++) {
-                if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == src_wire_name.index) {
-                    src_index = i;
-                    if (dst_index != -1) {
-                        break;
-                    }
-                }
-                if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == dst_wire_name.index) {
-                    dst_index = i;
-                    if (src_index != -1) {
-                        break;
-                    }
-                }
-            }
-
-            NPNR_ASSERT(src_index != -1);
-            NPNR_ASSERT(dst_index != -1);
-
-            for (int i = 0; i < tile_info.pip_data.ssize(); i++) {
-                if (tile_info.pip_data[i].src_index == src_index && tile_info.pip_data[i].dst_index == dst_index) {
-
-                    PipId ret;
-                    ret.tile = tile;
-                    ret.index = i;
-                    return ret;
-                }
-            }
-        }
-    }
-
-    return PipId();
-}
-
-IdStringList Arch::getPipName(PipId pip) const
-{
-    // PIP name structure:
-    // Tile PIP: <tile name>/<source wire name>.<destination wire name>
-    // Psuedo site PIP: <site name>/<input site wire>.<output site wire>
-    // Site PIP: <site name>/<bel name>/<input bel pin name>
-    // Site pin: <site name>/<bel name>
-    NPNR_ASSERT(pip != PipId());
-    auto &tile = chip_info->tiles[pip.tile];
-    auto &tile_type = loc_info(chip_info, pip);
-    auto &pip_info = tile_type.pip_data[pip.index];
-    if (pip_info.site != -1) {
-        // This is either a site pin or a site pip.
-        auto &site = get_site_inst(pip);
-        auto &bel = tile_type.bel_data[pip_info.bel];
-        IdString bel_name(bel.name);
-        if (bel.category == BEL_CATEGORY_LOGIC) {
-            // This is a psuedo pip
-            IdString src_wire_name = IdString(tile_type.wire_data[pip_info.src_index].name);
-            IdString dst_wire_name = IdString(tile_type.wire_data[pip_info.dst_index].name);
-            IdString pip = id(src_wire_name.str(this) + "." + dst_wire_name.str(this));
-            std::array<IdString, 2> ids{id(site.name.get()), pip};
-            return IdStringList(ids);
-
-        } else if (bel.category == BEL_CATEGORY_ROUTING) {
-            // This is a site pip.
-            IdString pin_name(bel.ports[pip_info.extra_data]);
-            std::array<IdString, 3> ids{id(site.name.get()), bel_name, pin_name};
-            return IdStringList(ids);
-        } else {
-            NPNR_ASSERT(bel.category == BEL_CATEGORY_SITE_PORT);
-            // This is a site pin, just the name of the BEL is a unique identifier.
-            std::array<IdString, 2> ids{id(site.name.get()), bel_name};
-            return IdStringList(ids);
-        }
-    } else {
-        // This is a tile pip.
-        IdString src_wire_name = IdString(tile_type.wire_data[pip_info.src_index].name);
-        IdString dst_wire_name = IdString(tile_type.wire_data[pip_info.dst_index].name);
-        IdString pip = id(src_wire_name.str(this) + "." + dst_wire_name.str(this));
-        std::array<IdString, 2> ids{id(std::string(tile.name.get())), pip};
-        return IdStringList(ids);
-    }
-}
-
-IdString Arch::getPipType(PipId pip) const { return id("PIP"); }
-
-std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const { return {}; }
-
-// -----------------------------------------------------------------------
-
-BelId Arch::getBelByLocation(Loc loc) const
-{
-    BelId bi;
-    if (loc.x >= chip_info->width || loc.y >= chip_info->height)
-        return BelId();
-    bi.tile = get_tile_index(loc);
-    auto &li = loc_info(chip_info, bi);
-
-    if (loc.z >= li.bel_data.ssize()) {
-        return BelId();
-    } else {
-        bi.index = loc.z;
-        return bi;
-    }
-}
-
-std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const { return {}; }
-
-// -----------------------------------------------------------------------
-
-BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
-{
-    int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
-    int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
-
-    int src_x, src_y;
-    get_tile_x_y(src_tile, &src_x, &src_y);
-
-    int x0 = src_x, x1 = src_x, y0 = src_y, y1 = src_y;
-
-    int dst_x, dst_y;
-    get_tile_x_y(dst_tile, &dst_x, &dst_y);
-
-    auto expand = [&](int x, int y) {
-        x0 = std::min(x0, x);
-        x1 = std::max(x1, x);
-        y0 = std::min(y0, y);
-        y1 = std::max(y1, y);
-    };
-
-    expand(dst_x, dst_y);
-
-    if (source_locs.count(src))
-        expand(source_locs.at(src).x, source_locs.at(src).y);
-
-    if (sink_locs.count(dst)) {
-        expand(sink_locs.at(dst).x, sink_locs.at(dst).y);
-    }
-
-    return {x0, y0, x1, y1};
-}
-
-// -----------------------------------------------------------------------
-
-bool Arch::pack()
-{
-    decode_lut_cells();
-    expand_macros();
-    merge_constant_nets();
-    pack_ports();
-    pack_default_conns();
-    pack_cluster();
-    return true;
-}
-
-static void prepare_for_placement(Context *ctx)
-{
-    ctx->remove_site_routing();
-
-    // Re-map BEL pins without constant pins
-    for (BelId bel : ctx->getBels()) {
-        CellInfo *cell = ctx->getBoundBelCell(bel);
-        if (cell != nullptr && cell->cell_mapping != -1) {
-            ctx->map_cell_pins(cell, cell->cell_mapping, /*bind_constants=*/false);
-        }
-    }
-}
-
-bool Arch::place()
-{
-    // Before placement, ripup placement specific bindings and unmask all cell
-    // pins.
-    getCtx()->check();
-    prepare_for_placement(getCtx());
-    getCtx()->check();
-#ifdef IDEMPOTENT_CHECK
-    prepare_for_placement(getCtx());
-    getCtx()->check();
-#endif
-
-    place_constraints();
-    place_globals();
-
-    std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
-    if (placer == "heap") {
-        PlacerHeapCfg cfg(getCtx());
-        cfg.criticalityExponent = 7;
-        cfg.alpha = 0.08;
-        cfg.beta = 0.4;
-        cfg.placeAllAtOnce = true;
-        cfg.hpwl_scale_x = 1;
-        cfg.hpwl_scale_y = 2;
-        cfg.spread_scale_x = 2;
-        cfg.spread_scale_y = 1;
-        cfg.solverTolerance = 0.6e-6;
-        if (!placer_heap(getCtx(), cfg))
-            return false;
-    } else if (placer == "sa") {
-        if (!placer1(getCtx(), Placer1Cfg(getCtx())))
-            return false;
-    } else {
-        log_error("FPGA interchange architecture does not support placer '%s'\n", placer.c_str());
-    }
-
-    getCtx()->attrs[getCtx()->id("step")] = std::string("place");
-    archInfoToAttributes();
-
-    // Print site LUT mapping caching stats
-    if (!getCtx()->arch_args.disable_lut_mapping_cache) {
-        log_info("Site LUT mapping cache stats:\n");
-        log_info("    miss ratio: %.1f%%\n", getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f);
-        log_info("    peak size : %zuMB (%zu items)\n", getCtx()->site_lut_mapping_cache.getSizeMB(),
-                 getCtx()->site_lut_mapping_cache.getCount());
-    }
-
-    getCtx()->check();
-
-    return true;
-}
-
-static void prepare_sites_for_routing(Context *ctx)
-{
-    // Reset site routing and remove masked cell pins from previous router run
-    // (if any).
-    ctx->remove_site_routing();
-
-    // Re-map BEL pins with constant pins
-    for (BelId bel : ctx->getBels()) {
-        CellInfo *cell = ctx->getBoundBelCell(bel);
-        if (cell != nullptr && cell->cell_mapping != -1) {
-            ctx->map_cell_pins(cell, cell->cell_mapping, /*bind_constants=*/true);
-        }
-    }
-
-    // Clear the site routing cache. This is because routing at this stage is done with the extra constraint of blocked
-    // pins to ensure a routeable pin choice.
-    ctx->site_routing_cache.clear();
-
-    // Clear the LUT mapping cache
-    ctx->site_lut_mapping_cache.clear();
-
-    // Have site router bind site routing (via bindPip and bindWire).
-    // This is important so that the pseudo pips are correctly blocked prior
-    // to handing the design to the generalized router algorithms.
-    for (auto &tile_pair : ctx->tileStatus) {
-        for (auto &site_router : tile_pair.second.sites) {
-            if (site_router.cells_in_site.empty()) {
-                continue;
-            }
-
-            site_router.bindSiteRouting(ctx);
-        }
-
-        tile_pair.second.pseudo_pip_model.prepare_for_routing(ctx, tile_pair.second.sites);
-    }
-
-    // Fixup LUT vcc pins.
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-
-    IdString const_net_name(ctx->chip_info->constants->best_constant_net);
-    NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
-
-    // FIXME: Use VCC if the architecture does not device the best constant
-    if (const_net_name == IdString()) {
-        const_net_name = vcc_net_name;
-    }
-
-    for (BelId bel : ctx->getBels()) {
-        CellInfo *cell = ctx->getBoundBelCell(bel);
-        if (cell == nullptr) {
-            continue;
-        }
-
-        for (const auto &it : cell->lut_cell.pin_connections) {
-            const auto &bel_pin = it.first;
-            const auto &conn = it.second;
-
-            // Connected to an active signal or unconnected
-            if (conn == LutCell::PinConnection::Signal || conn == LutCell::PinConnection::Unconnected) {
-                continue;
-            }
-
-            // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for
-            // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it
-            IdString cell_pin = ctx->idf("%s_PHYS", ctx->nameOf(bel_pin));
-
-            PortInfo port_info;
-            port_info.name = cell_pin;
-            port_info.type = PORT_IN;
-            port_info.net = nullptr;
-
-#ifdef DEBUG_LUT_MAPPING
-            if (ctx->verbose) {
-                log_info("%s must be tied to %s, tying now\n", ctx->nameOfWire(lut_pin_wire),
-                         LutCell::nameOfPinConnection(conn).c_str());
-            }
-#endif
-
-            IdString tie_net_name;
-            switch (conn) {
-            case LutCell::PinConnection::Vcc:
-                tie_net_name = vcc_net_name;
-                break;
-            case LutCell::PinConnection::Gnd:
-                tie_net_name = gnd_net_name;
-                break;
-            case LutCell::PinConnection::Const:
-                tie_net_name = const_net_name;
-                break;
-            default:
-                // Should never happen
-                NPNR_ASSERT_FALSE(
-                        stringf("Invalid LUT cell pin connection '%s'", LutCell::nameOfPinConnection(conn).c_str())
-                                .c_str());
-                break;
-            }
-
-            auto result = cell->ports.emplace(cell_pin, port_info);
-            if (result.second) {
-                cell->cell_bel_pins[cell_pin].push_back(bel_pin);
-                ctx->connectPort(tie_net_name, cell->name, cell_pin);
-                cell->const_ports.emplace(cell_pin);
-            } else {
-                NPNR_ASSERT(result.first->second.net == ctx->getNetByAlias(tie_net_name));
-                auto result2 = cell->cell_bel_pins.emplace(cell_pin, std::vector<IdString>({bel_pin}));
-                NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
-                NPNR_ASSERT(result2.first->second.size() == 1);
-            }
-        }
-    }
-}
-
-bool Arch::route()
-{
-    getCtx()->check();
-    prepare_sites_for_routing(getCtx());
-    getCtx()->check();
-#ifdef IDEMPOTENT_CHECK
-    prepare_sites_for_routing(getCtx());
-    getCtx()->check();
-#endif
-
-    std::string router = str_or_default(settings, id("router"), defaultRouter);
-
-    // Disallow site routing during general routing.  This is because
-    // "prepare_sites_for_routing" has already assigned routing for all sites
-    // in the design, and if the router wants to route-thru a site, it *MUST*
-    // use a pseudo-pip.
-    //
-    // It is not legal in the FPGA interchange to enter a site and not
-    // terminate at a BEL pin.
-    disallow_site_routing = true;
-
-    route_globals();
-
-    bool result;
-    if (router == "router1") {
-        result = router1(getCtx(), Router1Cfg(getCtx()));
-    } else if (router == "router2") {
-        router2(getCtx(), Router2Cfg(getCtx()));
-        result = true;
-    } else {
-        log_error("FPGA interchange architecture does not support router '%s'\n", router.c_str());
-    }
-
-    disallow_site_routing = false;
-
-    getCtx()->attrs[getCtx()->id("step")] = std::string("route");
-    archInfoToAttributes();
-
-    getCtx()->check();
-
-    // Now that routing is complete, unmask BEL pins.
-    unmask_bel_pins();
-
-    getCtx()->check();
-
-    return result;
-}
-
-// -----------------------------------------------------------------------
-
-std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const { return {}; }
-
-DecalXY Arch::getBelDecal(BelId bel) const
-{
-    DecalXY decalxy;
-    return decalxy;
-}
-
-DecalXY Arch::getWireDecal(WireId wire) const
-{
-    DecalXY decalxy;
-    return decalxy;
-}
-
-DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
-
-DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
-
-// -----------------------------------------------------------------------
-
-delay_t Arch::estimateDelay(WireId src, WireId dst) const
-{
-#ifdef USE_LOOKAHEAD
-    return lookahead.estimateDelay(getCtx(), src, dst);
-#else
-    // Note: Something is better than nothing when USE_LOOKAHEAD is not
-    // defined.
-    int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
-    int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
-
-    int src_x, src_y;
-    get_tile_x_y(src_tile, &src_x, &src_y);
-
-    int dst_x, dst_y;
-    get_tile_x_y(dst_tile, &dst_x, &dst_y);
-
-    delay_t base = 30 * std::min(std::abs(dst_x - src_x), 18) + 10 * std::max(std::abs(dst_x - src_x) - 18, 0) +
-                   60 * std::min(std::abs(dst_y - src_y), 6) + 20 * std::max(std::abs(dst_y - src_y) - 6, 0) + 300;
-
-    base = (base * 3) / 2;
-    return base;
-#endif
-}
-
-delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
-{
-    // FIXME: Implement when adding timing-driven place and route.
-    NPNR_UNUSED(src_pin);
-    NPNR_UNUSED(dst_pin);
-    int src_x, src_y;
-    get_tile_x_y(src_bel.tile, &src_x, &src_y);
-
-    int dst_x, dst_y;
-    get_tile_x_y(dst_bel.tile, &dst_x, &dst_y);
-
-    delay_t base = 30 * std::min(std::abs(dst_x - src_x), 18) + 10 * std::max(std::abs(dst_x - src_x) - 18, 0) +
-                   60 * std::min(std::abs(dst_y - src_y), 6) + 20 * std::max(std::abs(dst_y - src_y) - 6, 0) + 300;
-
-    base = (base * 3) / 2;
-    return base;
-}
-
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
-{
-    // FIXME: Implement when adding timing-driven place and route.
-    return false;
-}
-
-TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
-{
-    // FIXME: Implement when adding timing-driven place and route.
-    return TMG_IGNORE;
-}
-
-TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
-{
-    // FIXME: Implement when adding timing-driven place and route.
-    TimingClockingInfo info;
-    return info;
-}
-
-// -----------------------------------------------------------------------
-
-void Arch::read_logical_netlist(const std::string &filename)
-{
-    FpgaInterchange::read_logical_netlist(getCtx(), filename);
-}
-void Arch::write_physical_netlist(const std::string &filename) const
-{
-    FpgaInterchange::write_physical_netlist(getCtx(), filename);
-}
-
-void Arch::parse_xdc(const std::string &filename)
-{
-    TclInterp interp(getCtx());
-    auto result = Tcl_EvalFile(interp.interp, filename.c_str());
-    if (result != TCL_OK) {
-        log_error("Error in %s:%d => %s\n", filename.c_str(), Tcl_GetErrorLine(interp.interp),
-                  Tcl_GetStringResult(interp.interp));
-    }
-}
-
-std::string Arch::get_part() const
-{
-    // FIXME: Need a map between device / package / speed grade and part.
-    return chip_info->name.get() + args.package + "-1";
-}
-
-// -----------------------------------------------------------------------
-
-const std::string Arch::defaultPlacer = "heap";
-
-const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
-
-const std::string Arch::defaultRouter = "router2";
-const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
-
-void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
-{
-    cell->cell_mapping = mapping;
-    if (cell->lut_cell.pins.empty()) {
-        cell->cell_bel_pins.clear();
-        cell->masked_cell_bel_pins.clear();
-    } else {
-        std::vector<IdString> cell_pin_to_remove;
-        for (auto port_pair : cell->cell_bel_pins) {
-            if (!cell->lut_cell.lut_pins.count(port_pair.first)) {
-                cell_pin_to_remove.push_back(port_pair.first);
-            }
-        }
-
-        for (IdString cell_pin : cell_pin_to_remove) {
-            NPNR_ASSERT(cell->cell_bel_pins.erase(cell_pin));
-        }
-    }
-
-    for (IdString const_port : cell->const_ports) {
-        disconnectPort(cell->name, const_port);
-        NPNR_ASSERT(cell->ports.erase(const_port));
-    }
-
-    const CellBelMapPOD &cell_pin_map = chip_info->cell_map->cell_bel_map[mapping];
-
-    IdString gnd_net_name(chip_info->constants->gnd_net_name);
-    IdString vcc_net_name(chip_info->constants->vcc_net_name);
-
-    for (const auto &pin_map : cell_pin_map.common_pins) {
-        IdString cell_pin(pin_map.cell_pin);
-        IdString bel_pin(pin_map.bel_pin);
-
-        // Skip assigned LUT pins, as they are already mapped!
-        if (cell->lut_cell.lut_pins.count(cell_pin) && cell->cell_bel_pins.count(cell_pin)) {
-            continue;
-        }
-
-        if (cell_pin == id_GND) {
-            if (bind_constants) {
-                PortInfo port_info;
-                port_info.name = bel_pin;
-                port_info.type = PORT_IN;
-                port_info.net = nullptr;
-
-                auto result = cell->ports.emplace(bel_pin, port_info);
-                if (result.second) {
-                    cell->cell_bel_pins[bel_pin].push_back(bel_pin);
-                    connectPort(gnd_net_name, cell->name, bel_pin);
-                    cell->const_ports.emplace(bel_pin);
-                } else {
-                    NPNR_ASSERT(result.first->second.net == getNetByAlias(gnd_net_name));
-                    auto result2 = cell->cell_bel_pins.emplace(bel_pin, std::vector<IdString>({bel_pin}));
-                    NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
-                    NPNR_ASSERT(result2.first->second.size() == 1);
-                }
-            }
-            continue;
-        }
-
-        if (cell_pin == id_VCC) {
-            if (bind_constants) {
-                PortInfo port_info;
-                port_info.name = bel_pin;
-                port_info.type = PORT_IN;
-                port_info.net = nullptr;
-
-                auto result = cell->ports.emplace(bel_pin, port_info);
-                if (result.second) {
-                    cell->cell_bel_pins[bel_pin].push_back(bel_pin);
-                    connectPort(vcc_net_name, cell->name, bel_pin);
-                    cell->const_ports.emplace(bel_pin);
-                } else {
-                    NPNR_ASSERT(result.first->second.net == getNetByAlias(vcc_net_name));
-                    auto result2 = cell->cell_bel_pins.emplace(bel_pin, std::vector<IdString>({bel_pin}));
-                    NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
-                    NPNR_ASSERT(result2.first->second.size() == 1);
-                }
-            }
-            continue;
-        }
-
-        cell->cell_bel_pins[cell_pin].push_back(bel_pin);
-    }
-
-    for (const auto &parameter_pin_map : cell_pin_map.parameter_pins) {
-        IdString param_key(parameter_pin_map.key);
-        IdString param_value(parameter_pin_map.value);
-
-        auto iter = cell->params.find(param_key);
-        if (iter == cell->params.end()) {
-            continue;
-        }
-
-        if (!cell_parameters.compare_property(getCtx(), cell->type, param_key, iter->second, param_value)) {
-            continue;
-        }
-
-#ifdef DEBUG_CELL_PIN_MAPPING
-        log_info("parameter match on param_key %s\n", param_key.c_str(this));
-#endif
-
-        for (const auto &pin_map : parameter_pin_map.pins) {
-            IdString cell_pin(pin_map.cell_pin);
-            IdString bel_pin(pin_map.bel_pin);
-#ifdef DEBUG_CELL_PIN_MAPPING
-            log_info(" %s => %s\n", cell_pin.c_str(this), bel_pin.c_str(this));
-#endif
-
-            // Skip assigned LUT pins, as they are already mapped!
-            if (cell->lut_cell.lut_pins.count(cell_pin) && cell->cell_bel_pins.count(cell_pin)) {
-                continue;
-            }
-
-            if (cell_pin == id_GND) {
-                if (bind_constants) {
-                    PortInfo port_info;
-                    port_info.name = bel_pin;
-                    port_info.type = PORT_IN;
-                    port_info.net = nullptr;
-
-                    auto result = cell->ports.emplace(bel_pin, port_info);
-                    if (result.second) {
-                        cell->cell_bel_pins[bel_pin].push_back(bel_pin);
-                        connectPort(gnd_net_name, cell->name, bel_pin);
-                        cell->const_ports.emplace(bel_pin);
-                    } else {
-                        NPNR_ASSERT(result.first->second.net == getNetByAlias(gnd_net_name));
-                        auto result2 = cell->cell_bel_pins.emplace(bel_pin, std::vector<IdString>({bel_pin}));
-                        NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
-                        NPNR_ASSERT(result2.first->second.size() == 1);
-                    }
-                }
-                continue;
-            }
-
-            if (cell_pin == id_VCC) {
-                if (bind_constants) {
-                    PortInfo port_info;
-                    port_info.name = bel_pin;
-                    port_info.type = PORT_IN;
-                    port_info.net = nullptr;
-
-                    auto result = cell->ports.emplace(bel_pin, port_info);
-                    if (result.second) {
-                        cell->cell_bel_pins[bel_pin].push_back(bel_pin);
-                        connectPort(vcc_net_name, cell->name, bel_pin);
-                        cell->const_ports.emplace(bel_pin);
-                    } else {
-                        NPNR_ASSERT(result.first->second.net == getNetByAlias(vcc_net_name));
-                        auto result2 = cell->cell_bel_pins.emplace(bel_pin, std::vector<IdString>({bel_pin}));
-                        NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
-                        NPNR_ASSERT(result2.first->second.size() == 1);
-                    }
-                }
-                continue;
-            }
-
-            cell->cell_bel_pins[cell_pin].push_back(bel_pin);
-        }
-    }
-
-#ifdef DEBUG_CELL_PIN_MAPPING
-    log_info("Pin mapping for cell %s (type: %s)\n", cell->name.c_str(getCtx()), cell->type.c_str(getCtx()));
-    for (auto &pin_pair : cell->cell_bel_pins) {
-        log_info(" %s =>", pin_pair.first.c_str(getCtx()));
-        for (IdString bel_pin : pin_pair.second) {
-            log(" %s", bel_pin.c_str(getCtx()));
-        }
-        log("\n");
-    }
-#endif
-}
-
-void Arch::map_port_pins(BelId bel, CellInfo *cell) const
-{
-    IdStringRange pins = getBelPins(bel);
-    IdString pin = get_only_value(pins);
-
-    NPNR_ASSERT(cell->ports.size() == 1);
-    cell->cell_bel_pins[cell->ports.begin()->first].clear();
-    cell->cell_bel_pins[cell->ports.begin()->first].push_back(pin);
-}
-
-bool Arch::is_net_within_site(const NetInfo &net) const
-{
-    if (net.driver.cell == nullptr || net.driver.cell->bel == BelId()) {
-        return false;
-    }
-
-    BelId driver = net.driver.cell->bel;
-    int32_t site = bel_info(chip_info, driver).site;
-    NPNR_ASSERT(site >= 0);
-
-    for (const auto &user : net.users) {
-        if (user.cell == nullptr || user.cell->bel == BelId()) {
-            return false;
-        }
-        BelId user_bel = user.cell->bel;
-
-        if (user_bel.tile != driver.tile) {
-            return false;
-        }
-
-        if (bel_info(chip_info, user_bel).site != site) {
-            return false;
-        }
-    }
-
-    return true;
-}
-
-size_t Arch::get_cell_type_index(IdString cell_type) const
-{
-    const CellMapPOD &cell_map = *chip_info->cell_map;
-    int cell_offset = cell_type.index - cell_map.cell_names[0];
-    if ((cell_offset < 0 || cell_offset >= cell_map.cell_names.ssize())) {
-        log_error("Cell %s is not a placable element.\n", cell_type.c_str(this));
-    }
-    NPNR_ASSERT(cell_map.cell_names[cell_offset] == cell_type.index);
-
-    return cell_offset;
-}
-
-void Arch::merge_constant_nets()
-{
-    NetInfo *gnd_net = nullptr;
-    NetInfo *vcc_net = nullptr;
-
-    bool need_gnd_source = false;
-    bool need_vcc_source = false;
-
-    IdString gnd_net_name(chip_info->constants->gnd_net_name);
-    IdString gnd_cell_type(chip_info->constants->gnd_cell_name);
-    IdString gnd_cell_port(chip_info->constants->gnd_cell_port);
-
-    auto gnd_iter = nets.find(gnd_net_name);
-    if (gnd_iter != nets.end()) {
-        NPNR_ASSERT(gnd_iter->second->driver.cell != nullptr);
-        NPNR_ASSERT(gnd_iter->second->driver.cell->type == gnd_cell_type);
-        NPNR_ASSERT(gnd_iter->second->driver.port == gnd_cell_port);
-
-        gnd_net = gnd_iter->second.get();
-    } else {
-        gnd_net = createNet(gnd_net_name);
-        need_gnd_source = true;
-    }
-
-    IdString vcc_net_name(chip_info->constants->vcc_net_name);
-    IdString vcc_cell_type(chip_info->constants->vcc_cell_name);
-    IdString vcc_cell_port(chip_info->constants->vcc_cell_port);
-
-    auto vcc_iter = nets.find(vcc_net_name);
-    if (vcc_iter != nets.end()) {
-        NPNR_ASSERT(vcc_iter->second->driver.cell != nullptr);
-        NPNR_ASSERT(vcc_iter->second->driver.cell->type == vcc_cell_type);
-        NPNR_ASSERT(vcc_iter->second->driver.port == vcc_cell_port);
-
-        vcc_net = vcc_iter->second.get();
-    } else {
-        vcc_net = createNet(vcc_net_name);
-        need_vcc_source = true;
-    }
-
-    std::vector<IdString> other_gnd_nets;
-    std::vector<IdString> other_vcc_nets;
-
-    for (auto &net_pair : nets) {
-        if (net_pair.first == gnd_net_name) {
-            NPNR_ASSERT(net_pair.second.get() == gnd_net);
-            continue;
-        }
-
-        if (net_pair.first == vcc_net_name) {
-            NPNR_ASSERT(net_pair.second.get() == vcc_net);
-            continue;
-        }
-
-        NetInfo *net = net_pair.second.get();
-        if (net->driver.cell == nullptr) {
-            continue;
-        }
-
-        if (net->driver.cell->type == gnd_cell_type) {
-            NPNR_ASSERT(net->driver.port == gnd_cell_port);
-
-            other_gnd_nets.push_back(net_pair.first);
-
-            if (need_gnd_source) {
-                IdString driver_cell = net->driver.cell->name;
-                disconnectPort(driver_cell, gnd_cell_port);
-                connectPort(gnd_net_name, driver_cell, gnd_cell_port);
-                need_gnd_source = false;
-            }
-
-            NPNR_ASSERT(net->driver.port == gnd_cell_port);
-            indexed_store<PortRef> users_copy = net->users;
-            for (const PortRef &port_ref : users_copy) {
-                IdString cell = port_ref.cell->name;
-                disconnectPort(cell, port_ref.port);
-                connectPort(gnd_net_name, cell, port_ref.port);
-            }
-
-            continue;
-        }
-
-        if (net->driver.cell->type == vcc_cell_type) {
-            NPNR_ASSERT(net->driver.port == vcc_cell_port);
-
-            other_vcc_nets.push_back(net_pair.first);
-
-            if (need_vcc_source) {
-                IdString driver_cell = net->driver.cell->name;
-                disconnectPort(driver_cell, vcc_cell_port);
-                connectPort(vcc_net_name, driver_cell, vcc_cell_port);
-                need_vcc_source = false;
-            }
-
-            NPNR_ASSERT(net->driver.port == vcc_cell_port);
-            indexed_store<PortRef> users_copy = net->users;
-            for (const PortRef &port_ref : users_copy) {
-                IdString cell = port_ref.cell->name;
-                disconnectPort(cell, port_ref.port);
-                connectPort(vcc_net_name, cell, port_ref.port);
-            }
-        }
-    }
-
-    for (IdString other_gnd_net : other_gnd_nets) {
-        NetInfo *net = getNetByAlias(other_gnd_net);
-        NPNR_ASSERT(net->users.empty());
-        if (net->driver.cell) {
-            PortRef driver = net->driver;
-            IdString cell_to_remove = driver.cell->name;
-            disconnectPort(driver.cell->name, driver.port);
-            NPNR_ASSERT(cells.erase(cell_to_remove));
-        }
-    }
-
-    for (IdString other_vcc_net : other_vcc_nets) {
-        NetInfo *net = getNetByAlias(other_vcc_net);
-        NPNR_ASSERT(net->users.empty());
-        if (net->driver.cell) {
-            PortRef driver = net->driver;
-            IdString cell_to_remove = driver.cell->name;
-            disconnectPort(driver.cell->name, driver.port);
-            NPNR_ASSERT(cells.erase(cell_to_remove));
-        }
-    }
-
-    for (IdString other_gnd_net : other_gnd_nets) {
-        NPNR_ASSERT(nets.erase(other_gnd_net));
-        gnd_net->aliases.push_back(other_gnd_net);
-        net_aliases[other_gnd_net] = gnd_net_name;
-    }
-
-    for (IdString other_vcc_net : other_vcc_nets) {
-        NPNR_ASSERT(nets.erase(other_vcc_net));
-        vcc_net->aliases.push_back(other_vcc_net);
-        net_aliases[other_vcc_net] = vcc_net_name;
-    }
-
-    if (need_gnd_source) {
-        CellInfo *gnd_cell = createCell(gnd_cell_type, gnd_cell_type);
-        gnd_cell->addOutput(gnd_cell_port);
-        connectPort(gnd_net_name, gnd_cell_type, gnd_cell_port);
-    }
-
-    if (need_vcc_source) {
-        CellInfo *vcc_cell = createCell(vcc_cell_type, vcc_cell_type);
-        vcc_cell->addOutput(vcc_cell_port);
-        connectPort(vcc_net_name, vcc_cell_type, vcc_cell_port);
-    }
-}
-
-const std::vector<IdString> &Arch::getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const
-{
-    auto iter = cell_info->cell_bel_pins.find(pin);
-    if (iter == cell_info->cell_bel_pins.end()) {
-        return no_pins;
-    } else {
-        return iter->second;
-    }
-}
-
-void Arch::report_invalid_bel(BelId bel, CellInfo *cell) const
-{
-    int32_t mapping = bel_info(chip_info, bel).pin_map[get_cell_type_index(cell->type)];
-    NPNR_ASSERT(mapping < 0);
-    log_error("Cell %s (%s) cannot be placed at BEL %s (mapping %d)\n", cell->name.c_str(this), cell->type.c_str(this),
-              nameOfBel(bel), mapping);
-}
-
-void Arch::decode_lut_cells()
-{
-    for (auto &cell_pair : cells) {
-        CellInfo *cell = cell_pair.second.get();
-        auto iter = lut_cells.find(cell->type);
-        if (iter == lut_cells.end()) {
-            cell->lut_cell.pins.clear();
-            cell->lut_cell.equation.clear();
-            continue;
-        }
-
-        const LutCellPOD &lut_cell = *iter->second;
-
-        cell->lut_cell.pins.reserve(lut_cell.input_pins.size());
-        for (uint32_t pin : lut_cell.input_pins) {
-            cell->lut_cell.pins.push_back(IdString(pin));
-            cell->lut_cell.lut_pins.emplace(IdString(pin));
-        }
-
-        IdString equation_parameter(lut_cell.parameter);
-        const Property &equation = cell->params.at(equation_parameter);
-        cell->lut_cell.equation.resize(1 << cell->lut_cell.pins.size());
-
-        cell->lut_cell.equation = cell_parameters.parse_int_like(getCtx(), cell->type, equation_parameter, equation);
-    }
-}
-
-void Arch::remove_pip_pseudo_wires(PipId pip, NetInfo *net)
-{
-    WireId wire;
-    wire.tile = pip.tile;
-    const PipInfoPOD &pip_data = pip_info(chip_info, pip);
-    for (int32_t wire_index : pip_data.pseudo_cell_wires) {
-        NPNR_ASSERT(wire_index != -1);
-        wire.index = wire_index;
-
-        auto iter = wire_to_net.find(wire);
-        NPNR_ASSERT(iter != wire_to_net.end());
-        // This wire better already have been assigned to this net!
-        if (iter->second != net) {
-            if (iter->second == nullptr) {
-                log_error("Wire %s part of pseudo pip %s but net is null\n", nameOfWire(wire), nameOfPip(pip));
-            } else {
-                log_error("Wire %s part of pseudo pip %s but net is '%s' instead of net '%s'\n", nameOfWire(wire),
-                          nameOfPip(pip), iter->second->name.c_str(this), net->name.c_str(this));
-            }
-        }
-
-        auto wire_iter = net->wires.find(wire);
-        if (wire_iter != net->wires.end()) {
-#ifdef DEBUG_BINDING
-            if (getCtx()->verbose) {
-                log_info("Removing %s from net %s, but it's in net wires\n", nameOfWire(wire), net->name.c_str(this));
-            }
-#endif
-            // This wire is part of net->wires, make sure it has no pip,
-            // but leave it alone.  It will get cleaned up via
-            // unbindWire.
-        } else {
-            // This wire is not in net->wires, update wire_to_net.
-#ifdef DEBUG_BINDING
-            if (getCtx()->verbose) {
-                log_info("Removing %s from net %s in remove_pip_pseudo_wires\n", nameOfWire(wire),
-                         net->name.c_str(this));
-            }
-#endif
-            iter->second = nullptr;
-        }
-    }
-
-    if (pip_data.pseudo_cell_wires.size() > 0) {
-        get_tile_status(pip.tile).pseudo_pip_model.unbindPip(getCtx(), pip);
-    }
-}
-
-void Arch::assign_net_to_wire(WireId wire, NetInfo *net, const char *src, bool require_empty)
-{
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("Assigning wire %s to %s from %s\n", nameOfWire(wire), net->name.c_str(this), src);
-    }
-#endif
-    NPNR_ASSERT(net != nullptr);
-    auto result = wire_to_net.emplace(wire, net);
-    if (!result.second) {
-        // This wire was already in the map, make sure this assignment was
-        // legal.
-        if (require_empty) {
-            NPNR_ASSERT(result.first->second == nullptr);
-        } else {
-            NPNR_ASSERT(result.first->second == nullptr || result.first->second == net);
-        }
-        result.first->second = net;
-    }
-}
-
-void Arch::unassign_wire(WireId wire)
-{
-    NPNR_ASSERT(wire != WireId());
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("unassign_wire %s\n", nameOfWire(wire));
-    }
-#endif
-
-    auto iter = wire_to_net.find(wire);
-    NPNR_ASSERT(iter != wire_to_net.end());
-
-    NetInfo *net = iter->second;
-    NPNR_ASSERT(net != nullptr);
-
-    auto &net_wires = net->wires;
-    auto it = net_wires.find(wire);
-    NPNR_ASSERT(it != net_wires.end());
-
-    auto pip = it->second.pip;
-    if (pip != PipId()) {
-#ifdef DEBUG_BINDING
-        if (getCtx()->verbose) {
-            log_info("Removing pip %s because it was used to reach wire %s\n", nameOfPip(pip), nameOfWire(wire));
-        }
-#endif
-        auto pip_iter = pip_to_net.find(pip);
-        NPNR_ASSERT(pip_iter != pip_to_net.end());
-        NPNR_ASSERT(pip_iter->second == net);
-        pip_iter->second = nullptr;
-        remove_pip_pseudo_wires(pip, net);
-    }
-
-    net_wires.erase(it);
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("Removing %s from net %s in unassign_wire\n", nameOfWire(wire), net->name.c_str(this));
-    }
-#endif
-    iter->second = nullptr;
-}
-
-void Arch::unbindPip(PipId pip)
-{
-    NPNR_ASSERT(pip != PipId());
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("unbindPip %s\n", nameOfPip(pip));
-    }
-#endif
-
-    auto pip_iter = pip_to_net.find(pip);
-    NPNR_ASSERT(pip_iter != pip_to_net.end());
-    NetInfo *net = pip_iter->second;
-    NPNR_ASSERT(net != nullptr);
-
-    WireId dst = getPipDstWire(pip);
-    auto wire_iter = wire_to_net.find(dst);
-    NPNR_ASSERT(wire_iter != wire_to_net.end());
-    NPNR_ASSERT(wire_iter->second == net);
-
-    remove_pip_pseudo_wires(pip, net);
-
-    // Clear the net now.
-    pip_iter->second = nullptr;
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("Removing %s from net %s in unbindPip\n", nameOfWire(dst), net->name.c_str(this));
-    }
-#endif
-    wire_iter->second = nullptr;
-    NPNR_ASSERT(net->wires.erase(dst) == 1);
-
-    refreshUiPip(pip);
-    refreshUiWire(dst);
-}
-
-void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
-{
-    NPNR_ASSERT(pip != PipId());
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("bindPip %s (%d/%d) to net %s\n", nameOfPip(pip), pip.tile, pip.index, net->name.c_str(this));
-    }
-#endif
-    WireId dst = getPipDstWire(pip);
-    NPNR_ASSERT(dst != WireId());
-
-    {
-        // Pip should not already be assigned to anything.
-        auto result = pip_to_net.emplace(pip, net);
-        if (!result.second) {
-            NPNR_ASSERT(result.first->second == nullptr);
-            result.first->second = net;
-        }
-    }
-
-    assign_net_to_wire(dst, net, "bindPip", /*require_empty=*/true);
-    assign_pip_pseudo_wires(pip, net);
-
-    {
-        auto result = net->wires.emplace(dst, PipMap{pip, strength});
-        NPNR_ASSERT(result.second);
-    }
-
-    refreshUiPip(pip);
-    refreshUiWire(dst);
-}
-
-void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
-{
-    NPNR_ASSERT(wire != WireId());
-#ifdef DEBUG_BINDING
-    if (getCtx()->verbose) {
-        log_info("bindWire %s to net %s\n", nameOfWire(wire), net->name.c_str(this));
-    }
-#endif
-    assign_net_to_wire(wire, net, "bindWire", /*require_empty=*/true);
-    auto &pip_map = net->wires[wire];
-    pip_map.pip = PipId();
-    pip_map.strength = strength;
-    refreshUiWire(wire);
-}
-
-bool Arch::checkPipAvailForNet(PipId pip, const NetInfo *net) const
-{
-    NPNR_ASSERT(pip != PipId());
-    auto pip_iter = pip_to_net.find(pip);
-    if (pip_iter != pip_to_net.end() && pip_iter->second != nullptr) {
-        bool pip_blocked = false;
-        if (net == nullptr) {
-            pip_blocked = true;
-        } else {
-            if (net != pip_iter->second) {
-                pip_blocked = true;
-            }
-        }
-        if (pip_blocked) {
-#ifdef DEBUG_BINDING
-            if (getCtx()->verbose) {
-                log_info("Pip %s (%d/%d) is not available, tied to net %s\n", getCtx()->nameOfPip(pip), pip.tile,
-                         pip.index, pip_iter->second->name.c_str(getCtx()));
-            }
-#endif
-            NPNR_ASSERT(pip_iter->first == pip);
-            return false;
-        }
-    }
-
-    WireId src = getPipSrcWire(pip);
-    WireId dst = getPipDstWire(pip);
-
-    auto wire_iter = wire_to_net.find(dst);
-    if (wire_iter != wire_to_net.end()) {
-        NetInfo *wire_net = wire_iter->second;
-        if (wire_net != nullptr) {
-            auto net_iter = wire_net->wires.find(dst);
-            if (net_iter != wire_net->wires.end()) {
-                if (net == nullptr) {
-#ifdef DEBUG_BINDING
-                    if (getCtx()->verbose) {
-                        log_info("Pip %s (%d/%d) is not available, dst wire %s is tied to net %s\n",
-                                 getCtx()->nameOfPip(pip), pip.tile, pip.index, getCtx()->nameOfWire(dst),
-                                 wire_net->name.c_str(getCtx()));
-                    }
-#endif
-                    // dst is already driven in this net, do not allow!
-                    return false;
-                } else {
-#ifdef DEBUG_BINDING
-                    if (getCtx()->verbose && net_iter->second.pip != pip) {
-                        log_info("Pip %s (%d/%d) is not available, dst wire %s is tied to net %s\n",
-                                 getCtx()->nameOfPip(pip), pip.tile, pip.index, getCtx()->nameOfWire(dst),
-                                 wire_net->name.c_str(getCtx()));
-                    }
-#endif
-                    // This pip is available if this pip is already bound to
-                    // this.
-                    return net_iter->second.pip == pip;
-                }
-            }
-        }
-    }
-
-    // If this pip is a route-though, make sure all of the route-though are valid.
-    // A route-through is valid if:
-    //   - none of the pseudo-pip wires are bound to a net
-    //   - the pseudo pip wires are bound to the same net and there are no
-    //     lut elements in the tile type: this to prevent the router from choosing
-    //     a pseudo-pip on the same LUT and on a different input pin for the same net.
-    const TileTypeInfoPOD &tile_type = loc_info(chip_info, pip);
-    const PipInfoPOD &pip_data = tile_type.pip_data[pip.index];
-    WireId wire;
-    wire.tile = pip.tile;
-    for (int32_t wire_index : pip_data.pseudo_cell_wires) {
-        wire.index = wire_index;
-        NPNR_ASSERT(src != wire);
-        NPNR_ASSERT(dst != wire);
-
-        NetInfo *other_net = getConflictingWireNet(wire);
-        bool is_null_net = other_net == nullptr;
-        if (!is_null_net) {
-            bool is_same_net = other_net == net;
-            bool tile_has_luts = tile_type.lut_elements.size() > 0;
-            if (!is_same_net || tile_has_luts) {
-#ifdef DEBUG_BINDING
-                if (getCtx()->verbose)
-                    log_info("Pip %s is not available because wire %s is tied to a different net "
-                             "(other net: %s - orig net: %s) or the pseudo pip may traverses LUTs\n",
-                             getCtx()->nameOfPip(pip), getCtx()->nameOfWire(wire), other_net->name.c_str(getCtx()),
-                             net == nullptr ? "NULL net" : net->name.c_str(getCtx()));
-#endif
-                return false;
-            }
-        }
-    }
-
-    auto tile_status_iter = tileStatus.find(pip.tile);
-
-    if (pip_data.pseudo_cell_wires.size() > 0) {
-        // FIXME: This pseudo pip check is incomplete, because constraint
-        // failures will not be detected.  However the current FPGA
-        // interchange schema does not provide a cell type to place.
-        if (tile_status_iter != tileStatus.end() &&
-            !tile_status_iter->second.pseudo_pip_model.checkPipAvail(getCtx(), pip)) {
-            return false;
-        }
-    }
-
-    if (pip_data.site != -1 && net != nullptr) {
-        NPNR_ASSERT(net->driver.cell != nullptr);
-        NPNR_ASSERT(net->driver.cell->bel != BelId());
-
-        auto &src_wire_data = tile_type.wire_data[pip_data.src_index];
-        auto &dst_wire_data = tile_type.wire_data[pip_data.dst_index];
-
-        bool valid_pip = false;
-        if (pip.tile == net->driver.cell->bel.tile) {
-            if (tile_status_iter == tileStatus.end()) {
-                // there is no tile status and nothing blocks the validity of this PIP
-                valid_pip = true;
-            } else {
-                const BelInfoPOD &bel_data = tile_type.bel_data[net->driver.cell->bel.index];
-                const SiteRouter &site_router = get_site_status(tile_status_iter->second, bel_data);
-
-                const auto &pips = site_router.valid_pips;
-                auto result = std::find(pips.begin(), pips.end(), pip);
-                if (result != pips.end()) {
-                    valid_pip = true;
-                }
-            }
-        }
-
-        if (disallow_site_routing && !valid_pip) {
-            // For now, if driver is not part of this site, and
-            // disallow_site_routing is set, disallow the edge.
-            return false;
-        }
-
-        // FIXME: This check isn't perfect.  If a driver and sink are in the
-        // same site, it is possible for the router to route-thru the site
-        // ports without hitting a sink, which is not legal in the FPGA
-        // interchange.
-        if (!valid_pip) {
-            // See if one users can enter this site.
-            if (dst_wire_data.site == -1) {
-                // This is an output site port, but not for the driver net.
-                // Disallow.
-                NPNR_ASSERT(src_wire_data.site == pip_data.site);
-            } else {
-                // This might be a valid pip, scan users.
-                for (auto &user : net->users) {
-                    NPNR_ASSERT(user.cell != nullptr);
-                    if (user.cell->bel == BelId()) {
-                        continue;
-                    }
-
-                    auto &bel_data = bel_info(chip_info, user.cell->bel);
-                    if (bel_data.site == pip_data.site) {
-                        valid_pip = true;
-                        break;
-                    }
-                }
-            }
-        }
-
-        if (!valid_pip) {
-#ifdef DEBUG_BINDING
-            if (getCtx()->verbose) {
-                log_info("Pip %s is within a site and not available not right now\n", getCtx()->nameOfPip(pip));
-            }
-#endif
-            return false;
-        }
-    }
-
-    return true;
-}
-
-bool Arch::checkPipAvail(PipId pip) const { return checkPipAvailForNet(pip, nullptr); }
-
-std::string Arch::get_chipdb_hash() const { return chipdb_hash; }
-
-bool Arch::is_inverting(PipId pip) const
-{
-    auto &tile_type = loc_info(chip_info, pip);
-    auto &pip_info = tile_type.pip_data[pip.index];
-    if (pip_info.site == -1) {
-        // FIXME: Some routing pips are inverters, but this is missing from
-        // the chipdb.
-        return false;
-    }
-
-    auto &bel_data = tile_type.bel_data[pip_info.bel];
-
-    // Is a fixed inverter if the non_inverting_pin is another pin.
-    return bel_data.non_inverting_pin != pip_info.extra_data && bel_data.inverting_pin == pip_info.extra_data;
-}
-
-bool Arch::can_invert(PipId pip) const
-{
-    auto &tile_type = loc_info(chip_info, pip);
-    auto &pip_info = tile_type.pip_data[pip.index];
-    if (pip_info.site == -1) {
-        return false;
-    }
-
-    auto &bel_data = tile_type.bel_data[pip_info.bel];
-
-    // Can optionally invert if this pip is both the non_inverting_pin and
-    // inverting pin.
-    return bel_data.non_inverting_pin == pip_info.extra_data && bel_data.inverting_pin == pip_info.extra_data;
-}
-
-void Arch::mask_bel_pins_on_site_wire(NetInfo *net, WireId wire)
-{
-    std::vector<size_t> bel_pins_to_mask;
-    for (const PortRef &port_ref : net->users) {
-        if (port_ref.cell->bel == BelId()) {
-            continue;
-        }
-
-        NPNR_ASSERT(port_ref.cell != nullptr);
-        auto iter = port_ref.cell->cell_bel_pins.find(port_ref.port);
-        if (iter == port_ref.cell->cell_bel_pins.end()) {
-            continue;
-        }
-
-        std::vector<IdString> &cell_bel_pins = iter->second;
-        bel_pins_to_mask.clear();
-
-        for (size_t bel_pin_idx = 0; bel_pin_idx < cell_bel_pins.size(); ++bel_pin_idx) {
-            IdString bel_pin = cell_bel_pins.at(bel_pin_idx);
-            WireId bel_pin_wire = getBelPinWire(port_ref.cell->bel, bel_pin);
-            if (bel_pin_wire == wire) {
-                bel_pins_to_mask.push_back(bel_pin_idx);
-            }
-        }
-
-        if (!bel_pins_to_mask.empty()) {
-            std::vector<IdString> &masked_cell_bel_pins = port_ref.cell->masked_cell_bel_pins[port_ref.port];
-            // Remove in reverse order to preserve indicies.
-            for (auto riter = bel_pins_to_mask.rbegin(); riter != bel_pins_to_mask.rend(); ++riter) {
-                size_t bel_pin_idx = *riter;
-                masked_cell_bel_pins.push_back(cell_bel_pins.at(bel_pin_idx));
-                cell_bel_pins.erase(cell_bel_pins.begin() + bel_pin_idx);
-            }
-        }
-    }
-}
-
-void Arch::unmask_bel_pins()
-{
-    for (auto &cell_pair : cells) {
-        CellInfo *cell = cell_pair.second.get();
-        if (cell->masked_cell_bel_pins.empty()) {
-            continue;
-        }
-
-        for (auto &mask_pair : cell->masked_cell_bel_pins) {
-            IdString cell_port = mask_pair.first;
-            const std::vector<IdString> &bel_pins = mask_pair.second;
-            std::vector<IdString> &cell_bel_pins = cell->cell_bel_pins[cell_port];
-            cell_bel_pins.insert(cell_bel_pins.begin(), bel_pins.begin(), bel_pins.end());
-        }
-
-        cell->masked_cell_bel_pins.clear();
-    }
-}
-
-void Arch::remove_site_routing()
-{
-    pool<WireId> wires_to_unbind;
-    for (auto &net_pair : nets) {
-        for (auto &wire_pair : net_pair.second->wires) {
-            WireId wire = wire_pair.first;
-            if (wire_pair.second.strength != STRENGTH_PLACER) {
-                // Only looking for bound placer wires
-                continue;
-            }
-            wires_to_unbind.emplace(wire);
-        }
-    }
-
-    for (WireId wire : wires_to_unbind) {
-        unbindWire(wire);
-    }
-
-    unmask_bel_pins();
-
-    IdString id_NEXTPNR_INV = id("$nextpnr_inv");
-    IdString id_I = id("I");
-    std::vector<IdString> cells_to_remove;
-    for (auto &cell_pair : cells) {
-        CellInfo *cell = cell_pair.second.get();
-        if (cell->type != id_NEXTPNR_INV) {
-            continue;
-        }
-
-        disconnectPort(cell_pair.first, id_I);
-        cells_to_remove.push_back(cell_pair.first);
-        tileStatus.at(cell->bel.tile).boundcells[cell->bel.index] = nullptr;
-    }
-
-    for (IdString cell_name : cells_to_remove) {
-        NPNR_ASSERT(cells.erase(cell_name) == 1);
-    }
-}
-
-void Arch::explain_bel_status(BelId bel) const
-{
-    if (isBelLocationValid(bel)) {
-        log_info("BEL %s is valid!\n", nameOfBel(bel));
-        return;
-    }
-
-    auto iter = tileStatus.find(bel.tile);
-    NPNR_ASSERT(iter != tileStatus.end());
-    const TileStatus &tile_status = iter->second;
-    const CellInfo *cell = tile_status.boundcells[bel.index];
-    if (!dedicated_interconnect.isBelLocationValid(bel, cell)) {
-        dedicated_interconnect.explain_bel_status(bel, cell);
-        return;
-    }
-
-    if (io_port_types.count(cell->type)) {
-        return;
-    }
-
-    if (!is_cell_valid_constraints(cell, tile_status, /*explain_constraints=*/true)) {
-        return;
-    }
-
-    auto &bel_data = bel_info(chip_info, bel);
-    const SiteRouter &site = get_site_status(tile_status, bel_data);
-    NPNR_ASSERT(!site.checkSiteRouting(getCtx(), tile_status));
-    site.explain(getCtx());
-}
-
-DelayQuad Arch::getPipDelay(PipId pip) const
-{
-    // FIXME: Implement when adding timing-driven place and route.
-    const auto &pip_data = pip_info(chip_info, pip);
-
-    // Scale pseudo-pips by the number of wires they consume to make them
-    // more expensive than a single edge.  This approximation exists soley to
-    // make the non-timing driven solution avoid thinking that pseudo-pips
-    // are the same cost as regular pips.
-    return DelayQuad(100 * (1 + pip_data.pseudo_cell_wires.size()));
-}
-
-const DefaultCellConnsPOD *Arch::get_default_conns(IdString cell_type) const
-{
-    for (const auto &conn : chip_info->constants->default_conns) {
-        if (IdString(conn.cell_type) == cell_type)
-            return &conn;
-    }
-    return nullptr;
-}
-
-void Arch::pack_default_conns()
-{
-    IdString vcc_net_name(chip_info->constants->vcc_net_name);
-    IdString gnd_net_name(chip_info->constants->gnd_net_name);
-    Context *ctx = getCtx();
-
-    std::vector<IdString> dead_nets;
-
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        const DefaultCellConnsPOD *conns = get_default_conns(ci->type);
-        if (conns == nullptr)
-            continue;
-        for (const auto &pin : conns->pins) {
-            IdString pin_name(pin.pin_name);
-            // pin missing, create it
-            if (!ci->ports.count(pin_name))
-                ci->addInput(pin_name);
-            const NetInfo *net = ci->ports.at(pin_name).net;
-            if (net != nullptr) {
-                // pin is connected, and driven, nothing to do
-                if (net->driver.cell != nullptr)
-                    continue;
-                // pin is connected but undriven, disconnect the existing net
-                ctx->disconnectPort(ci->name, pin_name);
-                // remove net if it has no remaining users
-                if (net->users.empty())
-                    dead_nets.push_back(net->name);
-            }
-            if (pin.value == PIN_VALUE_GND)
-                ctx->connectPort(gnd_net_name, ci->name, pin_name);
-            else if (pin.value == PIN_VALUE_VCC)
-                ctx->connectPort(vcc_net_name, ci->name, pin_name);
-            else
-                NPNR_ASSERT(pin.value == PIN_VALUE_FLOAT);
-        }
-    }
-
-    // Remove any left-behind nets with no users and no drivers
-    for (auto net : dead_nets)
-        ctx->nets.erase(net);
-}
-
-// Instance constraint templates.
-template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
-template void Arch::ArchConstraints::unbindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
-template bool Arch::ArchConstraints::isValidBelForCellType(const Context *, uint32_t,
-                                                           const Arch::ArchConstraints::TagState *,
-                                                           const Arch::ConstraintRange, IdString, IdString, BelId,
-                                                           bool) const;
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
deleted file mode 100644
index e125d86c53..0000000000
--- a/fpga_interchange/arch.h
+++ /dev/null
@@ -1,1196 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018-19  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef FPGA_INTERCHANGE_ARCH_H
-#define FPGA_INTERCHANGE_ARCH_H
-
-#include <boost/iostreams/device/mapped_file.hpp>
-#include <iostream>
-#include <regex>
-
-#include "PhysicalNetlist.capnp.h"
-#include "arch_api.h"
-#include "constraints.h"
-#include "nextpnr_types.h"
-#include "relptr.h"
-
-#include "arch_iterators.h"
-#include "cell_parameters.h"
-#include "chipdb.h"
-#include "dedicated_interconnect.h"
-#include "lookahead.h"
-#include "pseudo_pip_model.h"
-#include "site_lut_mapping_cache.h"
-#include "site_router.h"
-#include "site_routing_cache.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct ArchArgs
-{
-    std::string chipdb;
-    std::string package;
-    bool rebuild_lookahead;
-    bool dont_write_lookahead;
-    bool disable_lut_mapping_cache;
-};
-
-struct ArchRanges
-{
-    using ArchArgsT = ArchArgs;
-    // Bels
-    using AllBelsRangeT = BelRange;
-    using TileBelsRangeT = BelRange;
-    using BelAttrsRangeT = std::vector<std::pair<IdString, std::string>>;
-    using BelPinsRangeT = IdStringRange;
-    using CellBelPinRangeT = const std::vector<IdString> &;
-    // Wires
-    using AllWiresRangeT = WireRange;
-    using DownhillPipRangeT = DownhillPipRange;
-    using UphillPipRangeT = UphillPipRange;
-    using WireBelPinRangeT = BelPinRange;
-    using WireAttrsRangeT = std::vector<std::pair<IdString, std::string>>;
-    // Pips
-    using AllPipsRangeT = AllPipRange;
-    using PipAttrsRangeT = std::vector<std::pair<IdString, std::string>>;
-    // Groups
-    using AllGroupsRangeT = std::vector<GroupId>;
-    using GroupBelsRangeT = std::vector<BelId>;
-    using GroupWiresRangeT = std::vector<WireId>;
-    using GroupPipsRangeT = std::vector<PipId>;
-    using GroupGroupsRangeT = std::vector<GroupId>;
-    // Decals
-    using DecalGfxRangeT = std::vector<GraphicElement>;
-    // Placement validity
-    using CellTypeRangeT = const IdStringRange;
-    using BelBucketRangeT = const BelBucketRange;
-    using BucketBelRangeT = FilteredBelRange;
-};
-
-static constexpr size_t kMaxState = 8;
-
-struct TileStatus
-{
-    std::vector<ExclusiveStateGroup<kMaxState>> tags;
-    std::vector<CellInfo *> boundcells;
-    std::vector<SiteRouter> sites;
-    PseudoPipModel pseudo_pip_model;
-};
-
-struct Cluster
-{
-    uint32_t index;
-    CellInfo *root;
-    std::vector<CellInfo *> cluster_nodes;
-    dict<IdString, IdString> cell_cluster_node_map;
-    dict<IdString, std::vector<std::pair<IdString, CellInfo *>>> cluster_node_cells;
-};
-
-struct Arch : ArchAPI<ArchRanges>
-{
-    boost::iostreams::mapped_file_source blob_file;
-    const ChipInfoPOD *chip_info;
-    int32_t package_index;
-
-    // Guard initialization of "by_name" maps if accessed from multiple
-    // threads on a "const Context *".
-    mutable std::mutex by_name_mutex;
-    mutable dict<IdString, int> tile_by_name;
-    mutable dict<IdString, std::pair<int, int>> site_by_name;
-
-    dict<WireId, NetInfo *> wire_to_net;
-    dict<PipId, NetInfo *> pip_to_net;
-
-    DedicatedInterconnect dedicated_interconnect;
-    dict<int32_t, TileStatus> tileStatus;
-    PseudoPipData pseudo_pip_data;
-
-    ArchArgs args;
-    Arch(ArchArgs args);
-    virtual ~Arch();
-    void init();
-
-    std::string getChipName() const final;
-
-    IdString archId() const final { return id(chip_info->name.get()); }
-    ArchArgs archArgs() const final { return args; }
-    IdString archArgsToId(ArchArgs args) const final;
-
-    // -------------------------------------------------
-
-    uint32_t get_tile_index(int x, int y) const { return (y * chip_info->width + x); }
-    uint32_t get_tile_index(Loc loc) const { return get_tile_index(loc.x, loc.y); }
-    template <typename TileIndex, typename CoordIndex>
-    void get_tile_x_y(TileIndex tile_index, CoordIndex *x, CoordIndex *y) const
-    {
-        *x = tile_index % chip_info->width;
-        *y = tile_index / chip_info->width;
-    }
-
-    template <typename TileIndex> void get_tile_loc(TileIndex tile_index, Loc *loc) const
-    {
-        get_tile_x_y(tile_index, &loc->x, &loc->y);
-    }
-
-    int getGridDimX() const final { return chip_info->width; }
-    int getGridDimY() const final { return chip_info->height; }
-    int getTileBelDimZ(int x, int y) const final
-    {
-        return chip_info->tile_types[chip_info->tiles[get_tile_index(x, y)].type].bel_data.size();
-    }
-    int getTilePipDimZ(int x, int y) const final
-    {
-        return chip_info->tile_types[chip_info->tiles[get_tile_index(x, y)].type].site_types.size();
-    }
-    char getNameDelimiter() const final { return '/'; }
-
-    std::string get_part() const;
-
-    // -------------------------------------------------
-
-    void setup_byname() const;
-
-    BelId getBelByName(IdStringList name) const final;
-
-    IdStringList getBelName(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-        const SiteInstInfoPOD &site = get_site_inst(bel);
-        std::array<IdString, 2> ids{id(site.name.get()), IdString(bel_info(chip_info, bel).name)};
-        return IdStringList(ids);
-    }
-
-    uint32_t getBelChecksum(BelId bel) const final { return bel.index; }
-
-    void map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants);
-    void map_port_pins(BelId bel, CellInfo *cell) const;
-
-    TileStatus &get_tile_status(int32_t tile)
-    {
-        auto result = tileStatus.emplace(tile, TileStatus());
-        if (result.second) {
-            auto &tile_type = chip_info->tile_types[chip_info->tiles[tile].type];
-            result.first->second.boundcells.resize(tile_type.bel_data.size(), nullptr);
-            result.first->second.tags.resize(default_tags.size());
-
-            result.first->second.sites.reserve(tile_type.site_types.size());
-            for (size_t i = 0; i < tile_type.site_types.size(); ++i) {
-                result.first->second.sites.push_back(SiteRouter(i));
-            }
-
-            result.first->second.pseudo_pip_model.init(getCtx(), tile);
-        }
-
-        return result.first->second;
-    }
-
-    const SiteRouter &get_site_status(const TileStatus &tile_status, const BelInfoPOD &bel_data) const
-    {
-        return tile_status.sites.at(bel_data.site);
-    }
-
-    SiteRouter &get_site_status(TileStatus &tile_status, const BelInfoPOD &bel_data)
-    {
-        return tile_status.sites.at(bel_data.site);
-    }
-
-    BelId get_vcc_bel() const
-    {
-        auto &constants = *chip_info->constants;
-        BelId bel;
-        bel.tile = constants.vcc_bel_tile;
-        bel.index = constants.vcc_bel_index;
-        return bel;
-    }
-
-    BelId get_gnd_bel() const
-    {
-        auto &constants = *chip_info->constants;
-        BelId bel;
-        bel.tile = constants.gnd_bel_tile;
-        bel.index = constants.gnd_bel_index;
-        return bel;
-    }
-
-    PhysicalNetlist::PhysNetlist::NetType get_net_type(NetInfo *net) const
-    {
-        NPNR_ASSERT(net != nullptr);
-        IdString gnd_cell_name(chip_info->constants->gnd_cell_name);
-        IdString gnd_cell_port(chip_info->constants->gnd_cell_port);
-
-        IdString vcc_cell_name(chip_info->constants->vcc_cell_name);
-        IdString vcc_cell_port(chip_info->constants->vcc_cell_port);
-        if (net->driver.cell->type == gnd_cell_name && net->driver.port == gnd_cell_port) {
-            return PhysicalNetlist::PhysNetlist::NetType::GND;
-        } else if (net->driver.cell->type == vcc_cell_name && net->driver.port == vcc_cell_port) {
-            return PhysicalNetlist::PhysNetlist::NetType::VCC;
-        } else {
-            return PhysicalNetlist::PhysNetlist::NetType::SIGNAL;
-        }
-    }
-
-    void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) final
-    {
-        NPNR_ASSERT(bel != BelId());
-
-        TileStatus &tile_status = get_tile_status(bel.tile);
-        NPNR_ASSERT(tile_status.boundcells[bel.index] == nullptr);
-
-        const auto &bel_data = bel_info(chip_info, bel);
-        NPNR_ASSERT(bel_data.category == BEL_CATEGORY_LOGIC);
-
-        if (io_port_types.count(cell->type) == 0) {
-            int32_t mapping = bel_info(chip_info, bel).pin_map[get_cell_type_index(cell->type)];
-            if (mapping < 0) {
-                report_invalid_bel(bel, cell);
-            }
-            NPNR_ASSERT(mapping >= 0);
-
-            if (cell->cell_mapping != mapping) {
-                map_cell_pins(cell, mapping, /*bind_constants=*/false);
-            }
-            constraints.bindBel(tile_status.tags.data(), get_cell_constraints(bel, cell->type));
-
-            // Clean previous cell placement in tile
-            if (cell->bel != BelId()) {
-                TileStatus &prev_tile_status = get_tile_status(cell->bel.tile);
-                NPNR_ASSERT(prev_tile_status.boundcells[cell->bel.index] != nullptr);
-
-                const auto &prev_bel_data = bel_info(chip_info, cell->bel);
-                NPNR_ASSERT(prev_bel_data.category == BEL_CATEGORY_LOGIC);
-
-                get_site_status(prev_tile_status, prev_bel_data).unbindBel(cell);
-                prev_tile_status.boundcells[cell->bel.index] = nullptr;
-
-                constraints.unbindBel(prev_tile_status.tags.data(), get_cell_constraints(cell->bel, cell->type));
-            }
-        } else {
-            map_port_pins(bel, cell);
-            // FIXME: Probably need to actually constraint io port cell/bel,
-            // but the current BBA emission doesn't support that.  This only
-            // really matters if the placer can choose IO port locations.
-        }
-
-        get_site_status(tile_status, bel_data).bindBel(cell);
-
-        tile_status.boundcells[bel.index] = cell;
-
-        cell->bel = bel;
-        cell->belStrength = strength;
-
-        refreshUiBel(bel);
-    }
-
-    void unbindBel(BelId bel) final
-    {
-        NPNR_ASSERT(bel != BelId());
-
-        TileStatus &tile_status = get_tile_status(bel.tile);
-        NPNR_ASSERT(tile_status.boundcells[bel.index] != nullptr);
-
-        CellInfo *cell = tile_status.boundcells[bel.index];
-        tile_status.boundcells[bel.index] = nullptr;
-
-        cell->bel = BelId();
-        cell->belStrength = STRENGTH_NONE;
-
-        // FIXME: Probably need to actually constraint io port cell/bel,
-        // but the current BBA emission doesn't support that.  This only
-        // really matters if the placer can choose IO port locations.
-        if (io_port_types.count(cell->type) == 0) {
-            constraints.unbindBel(tile_status.tags.data(), get_cell_constraints(bel, cell->type));
-        }
-
-        const auto &bel_data = bel_info(chip_info, bel);
-        get_site_status(tile_status, bel_data).unbindBel(cell);
-
-        refreshUiBel(bel);
-    }
-
-    bool checkBelAvail(BelId bel) const final
-    {
-        // FIXME: This could consult the constraint system to see if this BEL
-        // is blocked (e.g. site type is wrong).
-        return getBoundBelCell(bel) == nullptr;
-    }
-
-    CellInfo *getBoundBelCell(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-        auto iter = tileStatus.find(bel.tile);
-        if (iter == tileStatus.end()) {
-            return nullptr;
-        } else {
-            return iter->second.boundcells[bel.index];
-        }
-    }
-
-    CellInfo *getConflictingBelCell(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-        // FIXME: This could consult the constraint system to see why this BEL
-        // is blocked.
-        return getBoundBelCell(bel);
-    }
-
-    BelRange getBels() const final
-    {
-        BelRange range;
-        range.b.cursor_tile = 0;
-        range.b.cursor_index = -1;
-        range.b.chip = chip_info;
-        ++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
-        range.e.cursor_tile = chip_info->width * chip_info->height;
-        range.e.cursor_index = 0;
-        range.e.chip = chip_info;
-        return range;
-    }
-
-    Loc getBelLocation(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-        Loc loc;
-        get_tile_x_y(bel.tile, &loc.x, &loc.y);
-        loc.z = bel.index;
-        return loc;
-    }
-
-    BelId getBelByLocation(Loc loc) const final;
-    BelRange getBelsByTile(int x, int y) const final;
-
-    bool getBelGlobalBuf(BelId bel) const final
-    {
-        auto &bel_data = bel_info(chip_info, bel);
-        IdString bel_name(bel_data.name);
-
-        // Note: Check profiles and see if this should be something other than
-        // a linear scan.  Expectation is that for most arches, this will be
-        // fast enough.
-        for (int32_t global_bel : chip_info->cell_map->global_buffers) {
-            IdString global_bel_name(global_bel);
-            if (bel_name == global_bel_name) {
-                return true;
-            }
-        }
-
-        return false;
-    }
-
-    bool getBelHidden(BelId bel) const final { return bel_info(chip_info, bel).category != BEL_CATEGORY_LOGIC; }
-
-    IdString getBelType(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-        return IdString(bel_info(chip_info, bel).type);
-    }
-
-    std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const final;
-
-    int get_bel_pin_index(BelId bel, IdString pin) const
-    {
-        NPNR_ASSERT(bel != BelId());
-        int num_bel_wires = bel_info(chip_info, bel).num_bel_wires;
-        const int32_t *ports = bel_info(chip_info, bel).ports.get();
-        for (int i = 0; i < num_bel_wires; i++) {
-            if (ports[i] == pin.index) {
-                return i;
-            }
-        }
-
-        return -1;
-    }
-
-    WireId getBelPinWire(BelId bel, IdString pin) const final;
-    PortType getBelPinType(BelId bel, IdString pin) const final;
-
-    IdStringRange getBelPins(BelId bel) const final
-    {
-        NPNR_ASSERT(bel != BelId());
-
-        int num_bel_wires = bel_info(chip_info, bel).num_bel_wires;
-        const int32_t *ports = bel_info(chip_info, bel).ports.get();
-
-        IdStringRange str_range;
-        str_range.b.cursor = &ports[0];
-        str_range.e.cursor = &ports[num_bel_wires];
-
-        return str_range;
-    }
-
-    const std::vector<IdString> &getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const final;
-
-    // -------------------------------------------------
-
-    WireId getWireByName(IdStringList name) const final;
-
-    const TileWireInfoPOD &wire_info(WireId wire) const
-    {
-        if (wire.tile == -1) {
-            const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
-            return chip_info->tile_types[chip_info->tiles[wr.tile].type].wire_data[wr.index];
-        } else {
-            return loc_info(chip_info, wire).wire_data[wire.index];
-        }
-    }
-
-    IdStringList getWireName(WireId wire) const final
-    {
-        NPNR_ASSERT(wire != WireId());
-        if (wire.tile != -1) {
-            const auto &tile_type = loc_info(chip_info, wire);
-            if (tile_type.wire_data[wire.index].site != -1) {
-                const SiteInstInfoPOD &site = get_site_inst(wire);
-                std::array<IdString, 2> ids{id(site.name.get()), IdString(tile_type.wire_data[wire.index].name)};
-                return IdStringList(ids);
-            }
-        }
-
-        int32_t tile = wire.tile == -1 ? chip_info->nodes[wire.index].tile_wires[0].tile : wire.tile;
-        IdString tile_name = id(chip_info->tiles[tile].name.get());
-        std::array<IdString, 2> ids{tile_name, IdString(wire_info(wire).name)};
-        return IdStringList(ids);
-    }
-
-    IdString getWireType(WireId wire) const final;
-    std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const final;
-
-    uint32_t getWireChecksum(WireId wire) const final { return wire.index; }
-
-    void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) final;
-
-    void unbindWire(WireId wire) final
-    {
-        NPNR_ASSERT(wire != WireId());
-        unassign_wire(wire);
-        refreshUiWire(wire);
-    }
-
-    bool checkWireAvail(WireId wire) const final
-    {
-        NPNR_ASSERT(wire != WireId());
-        auto w2n = wire_to_net.find(wire);
-        return w2n == wire_to_net.end() || w2n->second == nullptr;
-    }
-
-    NetInfo *getBoundWireNet(WireId wire) const final
-    {
-        NPNR_ASSERT(wire != WireId());
-        auto w2n = wire_to_net.find(wire);
-        return w2n == wire_to_net.end() ? nullptr : w2n->second;
-    }
-
-    WireId getConflictingWireWire(WireId wire) const final { return wire; }
-
-    IdString getWireConstantValue(WireId wire) const final { return {}; }
-
-    NetInfo *getConflictingWireNet(WireId wire) const final
-    {
-        NPNR_ASSERT(wire != WireId());
-        auto w2n = wire_to_net.find(wire);
-        return w2n == wire_to_net.end() ? nullptr : w2n->second;
-    }
-
-    DelayQuad getWireDelay(WireId wire) const final { return DelayQuad(0); }
-
-    TileWireRange get_tile_wire_range(WireId wire) const
-    {
-        TileWireRange range;
-        range.b.chip = chip_info;
-        range.b.baseWire = wire;
-        range.b.cursor = -1;
-        ++range.b;
-
-        range.e.chip = chip_info;
-        range.e.baseWire = wire;
-        if (wire.tile == -1) {
-            range.e.cursor = chip_info->nodes[wire.index].tile_wires.size();
-        } else {
-            range.e.cursor = 1;
-        }
-        return range;
-    }
-
-    BelPinRange getWireBelPins(WireId wire) const final
-    {
-        BelPinRange range;
-        NPNR_ASSERT(wire != WireId());
-
-        TileWireRange twr = get_tile_wire_range(wire);
-        range.b.chip = chip_info;
-        range.b.twi = twr.b;
-        range.b.twi_end = twr.e;
-        range.b.cursor = -1;
-        ++range.b;
-
-        range.e.chip = chip_info;
-        range.e.twi = twr.e;
-        range.e.twi_end = twr.e;
-        range.e.cursor = 0;
-        return range;
-    }
-
-    WireRange getWires() const final
-    {
-        WireRange range;
-        range.b.chip = chip_info;
-        range.b.cursor_tile = -1;
-        range.b.cursor_index = 0;
-        range.e.chip = chip_info;
-        range.e.cursor_tile = chip_info->tiles.size();
-        range.e.cursor_index = 0;
-        return range;
-    }
-
-    bool is_site_wire(WireId wire) const;
-    WireCategory get_wire_category(WireId wire) const;
-
-    // -------------------------------------------------
-
-    PipId getPipByName(IdStringList name) const final;
-    IdStringList getPipName(PipId pip) const final;
-    IdString getPipType(PipId pip) const final;
-    std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const final;
-
-    void assign_net_to_wire(WireId wire, NetInfo *net, const char *src, bool require_empty);
-
-    void assign_pip_pseudo_wires(PipId pip, NetInfo *net)
-    {
-        NPNR_ASSERT(net != nullptr);
-        WireId wire;
-        wire.tile = pip.tile;
-        const PipInfoPOD &pip_data = pip_info(chip_info, pip);
-        for (int32_t wire_index : pip_data.pseudo_cell_wires) {
-            wire.index = wire_index;
-            if (getBoundWireNet(wire) != net)
-                assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true);
-        }
-
-        if (pip_data.pseudo_cell_wires.size() > 0) {
-            get_tile_status(pip.tile).pseudo_pip_model.bindPip(getCtx(), pip);
-        }
-    }
-
-    void remove_pip_pseudo_wires(PipId pip, NetInfo *net);
-
-    void unassign_wire(WireId wire);
-
-    void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) final;
-
-    void unbindPip(PipId pip) final;
-
-    bool checkPipAvail(PipId pip) const final;
-    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const final;
-
-    NetInfo *getBoundPipNet(PipId pip) const final
-    {
-        NPNR_ASSERT(pip != PipId());
-        auto p2n = pip_to_net.find(pip);
-        return p2n == pip_to_net.end() ? nullptr : p2n->second;
-    }
-
-    WireId getConflictingPipWire(PipId pip) const final
-    {
-        // FIXME: This doesn't account for pseudo pips.
-        return getPipDstWire(pip);
-    }
-
-    NetInfo *getConflictingPipNet(PipId pip) const final
-    {
-        // FIXME: This doesn't account for pseudo pips.
-        auto p2n = pip_to_net.find(pip);
-        return p2n == pip_to_net.end() ? nullptr : p2n->second;
-    }
-
-    AllPipRange getPips() const final
-    {
-        AllPipRange range;
-        range.b.cursor_tile = 0;
-        range.b.cursor_index = -1;
-        range.b.chip = chip_info;
-        ++range.b; //-1 and then ++ deals with the case of no wries in the first tile
-        range.e.cursor_tile = chip_info->width * chip_info->height;
-        range.e.cursor_index = 0;
-        range.e.chip = chip_info;
-        return range;
-    }
-
-    Loc getPipLocation(PipId pip) const final
-    {
-        Loc loc;
-        get_tile_loc(pip.tile, &loc);
-        loc.z = 0;
-        return loc;
-    }
-
-    uint32_t getPipChecksum(PipId pip) const final { return pip.index; }
-
-    WireId getPipSrcWire(PipId pip) const final NPNR_ALWAYS_INLINE
-    {
-        return canonical_wire(chip_info, pip.tile, loc_info(chip_info, pip).pip_data[pip.index].src_index);
-    }
-
-    WireId getPipDstWire(PipId pip) const final NPNR_ALWAYS_INLINE
-    {
-        return canonical_wire(chip_info, pip.tile, loc_info(chip_info, pip).pip_data[pip.index].dst_index);
-    }
-
-    DelayQuad getPipDelay(PipId pip) const final;
-
-    DownhillPipRange getPipsDownhill(WireId wire) const final
-    {
-        DownhillPipRange range;
-        NPNR_ASSERT(wire != WireId());
-        TileWireRange twr = get_tile_wire_range(wire);
-        range.b.chip = chip_info;
-        range.b.twi = twr.b;
-        range.b.twi_end = twr.e;
-        range.b.cursor = -1;
-        ++range.b;
-        range.e.chip = chip_info;
-        range.e.twi = twr.e;
-        range.e.twi_end = twr.e;
-        range.e.cursor = 0;
-        return range;
-    }
-
-    UphillPipRange getPipsUphill(WireId wire) const final
-    {
-        UphillPipRange range;
-        NPNR_ASSERT(wire != WireId());
-        TileWireRange twr = get_tile_wire_range(wire);
-        range.b.chip = chip_info;
-        range.b.twi = twr.b;
-        range.b.twi_end = twr.e;
-        range.b.cursor = -1;
-        ++range.b;
-        range.e.chip = chip_info;
-        range.e.twi = twr.e;
-        range.e.twi_end = twr.e;
-        range.e.cursor = 0;
-        return range;
-    }
-
-    // -------------------------------------------------
-
-    // FIXME: Use groups to get access to sites.
-    GroupId getGroupByName(IdStringList name) const final { return GroupId(); }
-    IdStringList getGroupName(GroupId group) const final { return IdStringList(); }
-    std::vector<GroupId> getGroups() const final { return {}; }
-    std::vector<BelId> getGroupBels(GroupId group) const final { return {}; }
-    std::vector<WireId> getGroupWires(GroupId group) const final { return {}; }
-    std::vector<PipId> getGroupPips(GroupId group) const final { return {}; }
-    std::vector<GroupId> getGroupGroups(GroupId group) const final { return {}; }
-
-    // -------------------------------------------------
-    delay_t estimateDelay(WireId src, WireId dst) const final;
-    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
-    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const final;
-    delay_t getDelayEpsilon() const final { return 20; }
-    delay_t getRipupDelayPenalty() const final { return 120; }
-    float getDelayNS(delay_t v) const final { return v * 0.001; }
-    delay_t getDelayFromNS(float ns) const final { return delay_t(ns * 1000); }
-    uint32_t getDelayChecksum(delay_t v) const final { return v; }
-
-    bool getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, DelayQuad &delay) const final
-    {
-        return false;
-    }
-
-    // -------------------------------------------------
-
-    void place_iobufs(WireId pad_wire, NetInfo *net,
-                      const dict<CellInfo *, IdString, hash_ptr_ops> &tightly_attached_bels,
-                      pool<CellInfo *, hash_ptr_ops> *placed_cells);
-
-    void pack_ports();
-
-    // Clusters
-    void pack_cluster();
-    void prepare_cluster(const ClusterPOD *cluster, uint32_t index);
-    void prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index);
-    dict<ClusterId, Cluster> clusters;
-
-    // User constraints
-    void place_constraints();
-
-    void decode_lut_cells();
-
-    const GlobalCellPOD *global_cell_info(IdString cell_type) const;
-    void place_globals();
-    void route_globals();
-
-    bool pack() final;
-    bool place() final;
-    bool route() final;
-    // -------------------------------------------------
-
-    std::vector<GraphicElement> getDecalGraphics(DecalId decal) const final;
-
-    DecalXY getBelDecal(BelId bel) const final;
-    DecalXY getWireDecal(WireId wire) const final;
-    DecalXY getPipDecal(PipId pip) const final;
-    DecalXY getGroupDecal(GroupId group) const final;
-
-    // -------------------------------------------------
-
-    // Get the delay through a cell from one port to another, returning false
-    // if no path exists. This only considers combinational delays, as required by the Arch API
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const;
-    // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
-    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
-    // Get the TimingClockingInfo of a port
-    TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
-
-    // -------------------------------------------------
-
-    const BelBucketRange getBelBuckets() const final
-    {
-        BelBucketRange bel_bucket_range;
-        bel_bucket_range.b.cursor.cursor = chip_info->bel_buckets.begin();
-        bel_bucket_range.e.cursor.cursor = chip_info->bel_buckets.end();
-        return bel_bucket_range;
-    }
-
-    BelBucketId getBelBucketForBel(BelId bel) const final
-    {
-        BelBucketId bel_bucket;
-        bel_bucket.name = IdString(bel_info(chip_info, bel).bel_bucket);
-        return bel_bucket;
-    }
-
-    const IdStringRange getCellTypes() const final
-    {
-        const CellMapPOD &cell_map = *chip_info->cell_map;
-
-        IdStringRange id_range;
-        id_range.b.cursor = cell_map.cell_names.begin();
-        id_range.e.cursor = cell_map.cell_names.end();
-
-        return id_range;
-    }
-
-    IdString getBelBucketName(BelBucketId bucket) const final { return bucket.name; }
-
-    BelBucketId getBelBucketByName(IdString name) const final
-    {
-        for (BelBucketId bel_bucket : getBelBuckets()) {
-            if (bel_bucket.name == name) {
-                return bel_bucket;
-            }
-        }
-
-        NPNR_ASSERT_FALSE("Failed to find BEL bucket for name.");
-        return BelBucketId();
-    }
-
-    size_t get_cell_type_index(IdString cell_type) const;
-
-    BelBucketId getBelBucketForCellType(IdString cell_type) const final
-    {
-        if (io_port_types.count(cell_type)) {
-            BelBucketId bucket;
-            bucket.name = id("IOPORTS");
-            return bucket;
-        }
-
-        BelBucketId bucket;
-        const CellMapPOD &cell_map = *chip_info->cell_map;
-        bucket.name = IdString(cell_map.cell_bel_buckets[get_cell_type_index(cell_type)]);
-        return bucket;
-    }
-
-    FilteredBelRange getBelsInBucket(BelBucketId bucket) const final
-    {
-        BelRange range = getBels();
-        FilteredBelRange filtered_range(range.begin(), range.end(),
-                                        [this, bucket](BelId bel) { return getBelBucketForBel(bel) == bucket; });
-
-        return filtered_range;
-    }
-
-    bool isValidBelForCellType(IdString cell_type, BelId bel) const final
-    {
-        if (io_port_types.count(cell_type)) {
-            return pads.count(bel) > 0;
-        }
-
-        const auto &bel_data = bel_info(chip_info, bel);
-        if (bel_data.category != BEL_CATEGORY_LOGIC) {
-            return false;
-        }
-
-        auto cell_type_index = get_cell_type_index(cell_type);
-        return bel_data.pin_map[cell_type_index] != -1;
-    }
-
-    bool is_cell_valid_constraints(const CellInfo *cell, const TileStatus &tile_status, bool explain) const
-    {
-        if (io_port_types.count(cell->type)) {
-            return true;
-        }
-
-        BelId bel = cell->bel;
-        NPNR_ASSERT(bel != BelId());
-
-        return constraints.isValidBelForCellType(getCtx(), get_constraint_prototype(bel), tile_status.tags.data(),
-                                                 get_cell_constraints(bel, cell->type),
-                                                 id(chip_info->tiles[bel.tile].name.get()), cell->name, bel, explain);
-    }
-
-    // Return true whether all Bels at a given location are valid
-    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const final
-    {
-        auto iter = tileStatus.find(bel.tile);
-        if (iter == tileStatus.end()) {
-            return true;
-        }
-        const TileStatus &tile_status = iter->second;
-        CellInfo *cell = tile_status.boundcells[bel.index];
-        auto &bel_data = bel_info(chip_info, bel);
-        auto &site_status = get_site_status(tile_status, bel_data);
-
-        if (cell != nullptr) {
-            if (!dedicated_interconnect.isBelLocationValid(bel, cell))
-                return false;
-
-            if (io_port_types.count(cell->type)) {
-                // FIXME: Probably need to actually constraint io port cell/bel,
-                // but the current BBA emission doesn't support that.  This only
-                // really matters if the placer can choose IO port locations.
-                return true;
-            }
-
-            if (!is_cell_valid_constraints(cell, tile_status, explain_constraints)) {
-                return false;
-            }
-
-            for (auto ci : site_status.cells_in_site) {
-                if (ci->cluster != ClusterId() && ci->cluster != cell->cluster &&
-                    cluster_info(chip_info, clusters.at(ci->cluster).index).disallow_other_cells)
-                    return false;
-
-                if (cell->cluster != ClusterId() && ci->cluster != cell->cluster &&
-                    cluster_info(chip_info, clusters.at(cell->cluster).index).disallow_other_cells)
-                    return false;
-            }
-        }
-
-        // Still check site status if cell is nullptr; as other bels in the site could be illegal (for example when
-        // dedicated paths can no longer be used after ripping up a cell)
-        bool routing_status = site_status.checkSiteRouting(getCtx(), tile_status);
-
-        return routing_status;
-    }
-
-    CellInfo *getClusterRootCell(ClusterId cluster) const override;
-    BoundingBox getClusterBounds(ClusterId cluster) const override;
-    Loc getClusterOffset(const CellInfo *cell) const override;
-    bool isClusterStrict(const CellInfo *cell) const override;
-    bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,
-                                  std::vector<std::pair<CellInfo *, BelId>> &) const;
-    bool macro_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,
-                                 std::vector<std::pair<CellInfo *, BelId>> &) const;
-    bool getClusterPlacement(ClusterId cluster, BelId root_bel,
-                             std::vector<std::pair<CellInfo *, BelId>> &placement) const override;
-
-    IdString get_bel_tiletype(BelId bel) const { return IdString(loc_info(chip_info, bel).name); }
-
-    dict<WireId, Loc> sink_locs, source_locs;
-    // -------------------------------------------------
-    void assignArchInfo() final {}
-
-    // -------------------------------------------------
-
-    static const std::string defaultPlacer;
-    static const std::vector<std::string> availablePlacers;
-
-    static const std::string defaultRouter;
-    static const std::vector<std::string> availableRouters;
-
-    // -------------------------------------------------
-    void read_logical_netlist(const std::string &filename);
-    void write_physical_netlist(const std::string &filename) const;
-    void parse_xdc(const std::string &filename);
-
-    pool<IdString> io_port_types;
-    pool<BelId> pads;
-
-    bool is_site_port(PipId pip) const
-    {
-        const PipInfoPOD &pip_data = pip_info(chip_info, pip);
-        if (pip_data.site == -1) {
-            return false;
-        }
-
-        BelId bel;
-        bel.tile = pip.tile;
-        bel.index = pip_data.bel;
-
-        const BelInfoPOD &bel_data = bel_info(chip_info, bel);
-
-        return bel_data.category == BEL_CATEGORY_SITE_PORT;
-    }
-
-    // Is the driver and all users of this net located within the same site?
-    //
-    // Returns false if any element of the net is not placed.
-    bool is_net_within_site(const NetInfo &net) const;
-
-    using ArchConstraints = Constraints<kMaxState>;
-    ArchConstraints constraints;
-    std::vector<ArchConstraints::TagState> default_tags;
-    bool explain_constraints;
-
-    struct StateRange
-    {
-        const int32_t *b;
-        const int32_t *e;
-
-        const int32_t *begin() const { return b; }
-        const int32_t *end() const { return e; }
-    };
-
-    struct Constraint : ArchConstraints::Constraint<StateRange>
-    {
-        const CellConstraintPOD *constraint;
-        Constraint(const CellConstraintPOD *constraint) : constraint(constraint) {}
-
-        size_t tag() const final { return constraint->tag; }
-
-        ArchConstraints::ConstraintType constraint_type() const final
-        {
-            return Constraints<kMaxState>::ConstraintType(constraint->constraint_type);
-        }
-
-        ArchConstraints::ConstraintStateType state() const final
-        {
-            NPNR_ASSERT(constraint_type() == Constraints<kMaxState>::CONSTRAINT_TAG_IMPLIES);
-            NPNR_ASSERT(constraint->states.size() == 1);
-            return constraint->states[0];
-        }
-
-        StateRange states() const final
-        {
-            StateRange range;
-            range.b = constraint->states.get();
-            range.e = range.b + constraint->states.size();
-
-            return range;
-        }
-    };
-
-    struct ConstraintIterator
-    {
-        const CellConstraintPOD *constraint;
-        ConstraintIterator() {}
-
-        ConstraintIterator operator++()
-        {
-            ++constraint;
-            return *this;
-        }
-
-        bool operator!=(const ConstraintIterator &other) const { return constraint != other.constraint; }
-
-        bool operator==(const ConstraintIterator &other) const { return constraint == other.constraint; }
-
-        Constraint operator*() const { return Constraint(constraint); }
-    };
-
-    struct ConstraintRange
-    {
-        ConstraintIterator b, e;
-
-        ConstraintIterator begin() const { return b; }
-        ConstraintIterator end() const { return e; }
-    };
-
-    uint32_t get_constraint_prototype(BelId bel) const { return chip_info->tiles[bel.tile].type; }
-
-    ConstraintRange get_cell_constraints(BelId bel, IdString cell_type) const
-    {
-        const auto &bel_data = bel_info(chip_info, bel);
-        NPNR_ASSERT(bel_data.category == BEL_CATEGORY_LOGIC);
-
-        int32_t mapping = bel_data.pin_map[get_cell_type_index(cell_type)];
-        NPNR_ASSERT(mapping >= 0);
-
-        auto &cell_bel_map = chip_info->cell_map->cell_bel_map[mapping];
-        ConstraintRange range;
-        range.b.constraint = cell_bel_map.constraints.get();
-        range.e.constraint = range.b.constraint + cell_bel_map.constraints.size();
-
-        return range;
-    }
-
-    const char *get_site_name(int32_t tile, size_t site) const
-    {
-        return site_inst_info(chip_info, tile, site).name.get();
-    }
-
-    const char *get_site_name(BelId bel) const
-    {
-        auto &bel_data = bel_info(chip_info, bel);
-        return get_site_name(bel.tile, bel_data.site);
-    }
-
-    const SiteInstInfoPOD &get_site_inst(BelId bel) const
-    {
-        auto &bel_data = bel_info(chip_info, bel);
-        return site_inst_info(chip_info, bel.tile, bel_data.site);
-    }
-
-    const SiteInstInfoPOD &get_site_inst(WireId wire) const
-    {
-        auto &wire_data = wire_info(wire);
-        NPNR_ASSERT(wire_data.site != -1);
-        return site_inst_info(chip_info, wire.tile, wire_data.site);
-    }
-
-    const SiteInstInfoPOD &get_site_inst(PipId pip) const
-    {
-        auto &pip_data = pip_info(chip_info, pip);
-        return site_inst_info(chip_info, pip.tile, pip_data.site);
-    }
-
-    // Is this bel synthetic (e.g. added during import process)?
-    //
-    // This is generally used for constant networks, but can also be used for
-    // static partitions.
-    bool is_bel_synthetic(BelId bel) const
-    {
-        const BelInfoPOD &bel_data = bel_info(chip_info, bel);
-
-        return bel_data.synthetic != 0;
-    }
-
-    // Is this pip synthetic (e.g. added during import process)?
-    //
-    // This is generally used for constant networks, but can also be used for
-    // static partitions.
-    bool is_pip_synthetic(PipId pip) const
-    {
-        auto &pip_data = pip_info(chip_info, pip);
-        if (pip_data.site == -1) {
-            return pip_data.extra_data == -1;
-        } else {
-            BelId bel;
-            bel.tile = pip.tile;
-            bel.index = pip_data.bel;
-            return is_bel_synthetic(bel);
-        }
-    }
-
-    bool is_same_site(WireId wire_a, WireId wire_b) const
-    {
-        if (wire_a.tile == -1) {
-            return false;
-        }
-
-        if (wire_a.tile != wire_b.tile) {
-            return false;
-        }
-
-        auto &wire_a_data = wire_info(wire_a);
-        auto &wire_b_data = wire_info(wire_b);
-
-        return wire_a_data.site == wire_b_data.site && wire_a_data.site != -1;
-    }
-
-    bool is_wire_in_site(WireId wire) const
-    {
-        if (wire.tile == -1) {
-            return false;
-        }
-
-        auto &wire_data = wire_info(wire);
-        return wire_data.site != -1;
-    }
-
-    // Does this pip always invert its signal?
-    bool is_inverting(PipId pip) const;
-
-    // Can this pip optional invert its signal?
-    bool can_invert(PipId pip) const;
-
-    void merge_constant_nets();
-    void report_invalid_bel(BelId bel, CellInfo *cell) const;
-
-    std::vector<IdString> no_pins;
-    IdString gnd_cell_pin;
-    IdString vcc_cell_pin;
-    std::vector<std::vector<LutElement>> lut_elements;
-    dict<IdString, const LutCellPOD *> lut_cells;
-
-    // Defines the max number of LUT cells in a site and LUT pins
-    // to allow a correct functioning of the site lut mapping cache
-    int max_lut_cells;
-    int max_lut_pins;
-
-    // Of the LUT cells, which is used for wires?
-    // Note: May be null in arch's without wire LUT types.  Assumption is
-    // that these arch's don't need wire LUT's because the LUT share is simple
-    // enough to avoid it.
-    const LutCellPOD *wire_lut;
-
-    std::regex raw_bin_constant;
-    std::regex verilog_bin_constant;
-    std::regex verilog_hex_constant;
-    void read_lut_equation(DynamicBitarray<> *equation, const Property &equation_parameter) const;
-
-    IdString id_GND;
-    IdString id_VCC;
-    Lookahead lookahead;
-    mutable RouteNodeStorage node_storage;
-    mutable SiteRoutingCache site_routing_cache;
-    mutable SiteLutMappingCache site_lut_mapping_cache;
-    bool disallow_site_routing;
-    CellParameters cell_parameters;
-
-    std::string chipdb_hash;
-    std::string get_chipdb_hash() const;
-
-    // Masking moves BEL pins from cell_bel_pins to masked_cell_bel_pins for
-    // the purposes routing.  The idea is that masked BEL pins are already
-    // handled during site routing, and they shouldn't be visible to the
-    // router.
-    void mask_bel_pins_on_site_wire(NetInfo *net, WireId wire);
-
-    // This removes pips and wires bound by the site router, and unmasks all
-    // BEL pins masked during site routing.
-    void remove_site_routing();
-
-    // This unmasks any BEL pins that were masked when site routing was bound.
-    void unmask_bel_pins();
-
-    void explain_bel_status(BelId bel) const;
-
-    const DefaultCellConnsPOD *get_default_conns(IdString cell_type) const;
-    void pack_default_conns();
-
-    dict<IdString, std::vector<CellInfo *>> macro_to_cells;
-    void expand_macros();
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* FPGA_INTERCHANGE_ARCH_H */
diff --git a/fpga_interchange/arch_iterators.h b/fpga_interchange/arch_iterators.h
deleted file mode 100644
index c59a7d1882..0000000000
--- a/fpga_interchange/arch_iterators.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef ARCH_ITERATORS_H
-#define ARCH_ITERATORS_H
-
-#include "chipdb.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct BelIterator
-{
-    const ChipInfoPOD *chip;
-    int cursor_index;
-    int cursor_tile;
-
-    BelIterator operator++()
-    {
-        cursor_index++;
-        while (cursor_tile < chip->tiles.ssize() && cursor_index >= tile_info(chip, cursor_tile).bel_data.ssize()) {
-            cursor_index = 0;
-            cursor_tile++;
-        }
-        return *this;
-    }
-    BelIterator operator++(int)
-    {
-        BelIterator prior(*this);
-        ++(*this);
-        return prior;
-    }
-
-    bool operator!=(const BelIterator &other) const
-    {
-        return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
-    }
-
-    bool operator==(const BelIterator &other) const
-    {
-        return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
-    }
-
-    BelId operator*() const
-    {
-        BelId ret;
-        ret.tile = cursor_tile;
-        ret.index = cursor_index;
-        return ret;
-    }
-};
-
-struct BelRange
-{
-    BelIterator b, e;
-    BelIterator begin() const { return b; }
-    BelIterator end() const { return e; }
-};
-
-struct FilteredBelIterator
-{
-    std::function<bool(BelId)> filter;
-    BelIterator b, e;
-
-    FilteredBelIterator operator++()
-    {
-        ++b;
-        while (b != e) {
-            if (filter(*b)) {
-                break;
-            }
-
-            ++b;
-        }
-        return *this;
-    }
-
-    bool operator!=(const FilteredBelIterator &other) const
-    {
-        NPNR_ASSERT(e == other.e);
-        return b != other.b;
-    }
-
-    bool operator==(const FilteredBelIterator &other) const
-    {
-        NPNR_ASSERT(e == other.e);
-        return b == other.b;
-    }
-
-    BelId operator*() const
-    {
-        BelId bel = *b;
-        NPNR_ASSERT(filter(bel));
-        return bel;
-    }
-};
-
-struct FilteredBelRange
-{
-    FilteredBelRange(BelIterator bel_b, BelIterator bel_e, std::function<bool(BelId)> filter)
-    {
-        b.filter = filter;
-        b.b = bel_b;
-        b.e = bel_e;
-
-        if (b.b != b.e && !filter(*b.b)) {
-            ++b;
-        }
-
-        e.b = bel_e;
-        e.e = bel_e;
-
-        if (b != e) {
-            NPNR_ASSERT(filter(*b.b));
-        }
-    }
-
-    FilteredBelIterator b, e;
-    FilteredBelIterator begin() const { return b; }
-    FilteredBelIterator end() const { return e; }
-};
-
-// -----------------------------------------------------------------------
-
-// Iterate over TileWires for a wire (will be more than one if nodal)
-struct TileWireIterator
-{
-    const ChipInfoPOD *chip;
-    WireId baseWire;
-    int cursor = -1;
-
-    void operator++() { cursor++; }
-
-    bool operator==(const TileWireIterator &other) const { return cursor == other.cursor; }
-    bool operator!=(const TileWireIterator &other) const { return cursor != other.cursor; }
-
-    // Returns a *denormalised* identifier always pointing to a tile wire rather than a node
-    WireId operator*() const
-    {
-        if (baseWire.tile == -1) {
-            WireId tw;
-            const auto &node_wire = chip->nodes[baseWire.index].tile_wires[cursor];
-            tw.tile = node_wire.tile;
-            tw.index = node_wire.index;
-            return tw;
-        } else {
-            return baseWire;
-        }
-    }
-};
-
-struct TileWireRange
-{
-    TileWireIterator b, e;
-    TileWireIterator begin() const { return b; }
-    TileWireIterator end() const { return e; }
-};
-
-NPNR_ALWAYS_INLINE inline WireId canonical_wire(const ChipInfoPOD *chip_info, int32_t tile, int32_t wire)
-{
-    WireId id;
-
-    if (wire >= chip_info->tiles[tile].tile_wire_to_node.ssize()) {
-        // Cannot be a nodal wire
-        id.tile = tile;
-        id.index = wire;
-    } else {
-        int32_t node = chip_info->tiles[tile].tile_wire_to_node[wire];
-        if (node == -1) {
-            // Not a nodal wire
-            id.tile = tile;
-            id.index = wire;
-        } else {
-            // Is a nodal wire, set tile to -1
-            id.tile = -1;
-            id.index = node;
-        }
-    }
-
-    return id;
-}
-
-// -----------------------------------------------------------------------
-
-struct WireIterator
-{
-    const ChipInfoPOD *chip;
-    int cursor_index = 0;
-    int cursor_tile = -1;
-
-    WireIterator operator++()
-    {
-        // Iterate over nodes first, then tile wires that aren't nodes
-        do {
-            cursor_index++;
-            if (cursor_tile == -1 && cursor_index >= chip->nodes.ssize()) {
-                cursor_tile = 0;
-                cursor_index = 0;
-            }
-            while (cursor_tile != -1 && cursor_tile < chip->tiles.ssize() &&
-                   cursor_index >= chip->tile_types[chip->tiles[cursor_tile].type].wire_data.ssize()) {
-                cursor_index = 0;
-                cursor_tile++;
-            }
-
-        } while ((cursor_tile != -1 && cursor_tile < chip->tiles.ssize() &&
-                  cursor_index < chip->tiles[cursor_tile].tile_wire_to_node.ssize() &&
-                  chip->tiles[cursor_tile].tile_wire_to_node[cursor_index] != -1));
-
-        return *this;
-    }
-    WireIterator operator++(int)
-    {
-        WireIterator prior(*this);
-        ++(*this);
-        return prior;
-    }
-
-    bool operator!=(const WireIterator &other) const
-    {
-        return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
-    }
-
-    bool operator==(const WireIterator &other) const
-    {
-        return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
-    }
-
-    WireId operator*() const
-    {
-        WireId ret;
-        ret.tile = cursor_tile;
-        ret.index = cursor_index;
-        return ret;
-    }
-};
-
-struct WireRange
-{
-    WireIterator b, e;
-    WireIterator begin() const { return b; }
-    WireIterator end() const { return e; }
-};
-
-// -----------------------------------------------------------------------
-struct AllPipIterator
-{
-    const ChipInfoPOD *chip;
-    int cursor_index;
-    int cursor_tile;
-
-    AllPipIterator operator++()
-    {
-        cursor_index++;
-        while (cursor_tile < chip->tiles.ssize() &&
-               cursor_index >= chip->tile_types[chip->tiles[cursor_tile].type].pip_data.ssize()) {
-            cursor_index = 0;
-            cursor_tile++;
-        }
-        return *this;
-    }
-    AllPipIterator operator++(int)
-    {
-        AllPipIterator prior(*this);
-        ++(*this);
-        return prior;
-    }
-
-    bool operator!=(const AllPipIterator &other) const
-    {
-        return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
-    }
-
-    bool operator==(const AllPipIterator &other) const
-    {
-        return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
-    }
-
-    PipId operator*() const
-    {
-        PipId ret;
-        ret.tile = cursor_tile;
-        ret.index = cursor_index;
-        return ret;
-    }
-};
-
-struct AllPipRange
-{
-    AllPipIterator b, e;
-    AllPipIterator begin() const { return b; }
-    AllPipIterator end() const { return e; }
-};
-
-// -----------------------------------------------------------------------
-
-struct UphillPipIterator
-{
-    const ChipInfoPOD *chip;
-    TileWireIterator twi, twi_end;
-    int cursor = -1;
-
-    void operator++()
-    {
-        cursor++;
-        while (true) {
-            if (!(twi != twi_end))
-                break;
-            WireId w = *twi;
-            auto &tile = chip->tile_types[chip->tiles[w.tile].type];
-            if (cursor < tile.wire_data[w.index].pips_uphill.ssize())
-                break;
-            ++twi;
-            cursor = 0;
-        }
-    }
-    bool operator!=(const UphillPipIterator &other) const { return twi != other.twi || cursor != other.cursor; }
-
-    PipId operator*() const
-    {
-        PipId ret;
-        WireId w = *twi;
-        ret.tile = w.tile;
-        ret.index = chip->tile_types[chip->tiles[w.tile].type].wire_data[w.index].pips_uphill[cursor];
-        return ret;
-    }
-};
-
-struct UphillPipRange
-{
-    UphillPipIterator b, e;
-    UphillPipIterator begin() const { return b; }
-    UphillPipIterator end() const { return e; }
-};
-
-struct DownhillPipIterator
-{
-    const ChipInfoPOD *chip;
-    TileWireIterator twi, twi_end;
-    int cursor = -1;
-
-    int32_t tile;
-    int32_t tile_type;
-    const RelSlice<int32_t> *pips_downhill = nullptr;
-
-    void operator++()
-    {
-        cursor++;
-        while (true) {
-            if (!(twi != twi_end))
-                break;
-
-            if (pips_downhill == nullptr) {
-                WireId w = *twi;
-                tile_type = chip->tiles[w.tile].type;
-                const TileTypeInfoPOD &type = chip->tile_types[tile_type];
-
-                tile = w.tile;
-                pips_downhill = &type.wire_data[w.index].pips_downhill;
-            }
-
-            if (cursor < pips_downhill->ssize())
-                break;
-
-            ++twi;
-            cursor = 0;
-            pips_downhill = nullptr;
-        }
-    }
-    bool operator!=(const DownhillPipIterator &other) const { return twi != other.twi || cursor != other.cursor; }
-
-    PipId operator*() const
-    {
-        PipId ret;
-        ret.tile = tile;
-        ret.index = (*pips_downhill)[cursor];
-        return ret;
-    }
-};
-
-struct DownhillPipRange
-{
-    DownhillPipIterator b, e;
-    DownhillPipIterator begin() const { return b; }
-    DownhillPipIterator end() const { return e; }
-};
-
-struct BelPinIterator
-{
-    const ChipInfoPOD *chip;
-    TileWireIterator twi, twi_end;
-    int cursor = -1;
-
-    void operator++()
-    {
-        cursor++;
-
-        while (twi != twi_end) {
-            WireId w = *twi;
-            auto &tile = tile_info(chip, w.tile);
-            if (cursor < tile.wire_data[w.index].bel_pins.ssize())
-                break;
-
-            ++twi;
-            cursor = 0;
-        }
-    }
-    bool operator!=(const BelPinIterator &other) const { return twi != other.twi || cursor != other.cursor; }
-
-    BelPin operator*() const
-    {
-        BelPin ret;
-        WireId w = *twi;
-        ret.bel.tile = w.tile;
-        ret.bel.index = tile_info(chip, w.tile).wire_data[w.index].bel_pins[cursor].bel_index;
-        ret.pin.index = tile_info(chip, w.tile).wire_data[w.index].bel_pins[cursor].port;
-        return ret;
-    }
-};
-
-struct BelPinRange
-{
-    BelPinIterator b, e;
-    BelPinIterator begin() const { return b; }
-    BelPinIterator end() const { return e; }
-};
-
-struct IdStringIterator : std::iterator<std::forward_iterator_tag,
-                                        /*T=*/IdString,
-                                        /*Distance=*/ptrdiff_t,
-                                        /*pointer=*/IdString *,
-                                        /*reference=*/IdString>
-{
-    const int32_t *cursor;
-
-    void operator++() { cursor += 1; }
-
-    bool operator!=(const IdStringIterator &other) const { return cursor != other.cursor; }
-
-    bool operator==(const IdStringIterator &other) const { return cursor == other.cursor; }
-
-    IdString operator*() const { return IdString(*cursor); }
-};
-
-struct IdStringRange
-{
-    IdStringIterator b, e;
-    IdStringIterator begin() const { return b; }
-    IdStringIterator end() const { return e; }
-};
-
-struct BelBucketIterator
-{
-    IdStringIterator cursor;
-
-    void operator++() { ++cursor; }
-
-    bool operator!=(const BelBucketIterator &other) const { return cursor != other.cursor; }
-
-    bool operator==(const BelBucketIterator &other) const { return cursor == other.cursor; }
-
-    BelBucketId operator*() const
-    {
-        BelBucketId bucket;
-        bucket.name = IdString(*cursor);
-        return bucket;
-    }
-};
-
-struct BelBucketRange
-{
-    BelBucketIterator b, e;
-    BelBucketIterator begin() const { return b; }
-    BelBucketIterator end() const { return e; }
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* ARCH_ITERATORS_H */
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc
deleted file mode 100644
index 0dc75192a8..0000000000
--- a/fpga_interchange/arch_pack_clusters.cc
+++ /dev/null
@@ -1,1076 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "arch.h"
-#include "design_utils.h"
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-#include <boost/algorithm/string.hpp>
-#include <queue>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace {
-enum ClusterWireNodeState
-{
-    IN_SINK_SITE = 0,
-    IN_ROUTING = 1,
-    IN_SOURCE_SITE = 2,
-    ONLY_IN_SOURCE_SITE = 3
-};
-
-enum ExpansionDirection
-{
-    CLUSTER_UPHILL_DIR = 0,
-    CLUSTER_DOWNHILL_DIR = 1,
-    CLUSTER_BOTH_DIR = 2
-};
-
-struct ClusterWireNode
-{
-    WireId wire;
-    ClusterWireNodeState state;
-    int depth;
-    bool only_down;
-};
-} // namespace
-
-static void handle_expansion_node(const Context *ctx, WireId prev_wire, PipId pip, ClusterWireNode curr_node,
-                                  std::vector<ClusterWireNode> &nodes_to_expand, pool<BelId> &bels,
-                                  ExpansionDirection direction)
-{
-    WireId wire;
-
-    if (direction == CLUSTER_UPHILL_DIR)
-        wire = ctx->getPipSrcWire(pip);
-    else
-        wire = ctx->getPipDstWire(pip);
-
-    if (wire == WireId())
-        return;
-
-    ClusterWireNode next_node;
-    next_node.wire = wire;
-    next_node.depth = curr_node.depth;
-
-    if (next_node.depth >= 2)
-        return;
-
-    auto const &wire_data = ctx->wire_info(wire);
-
-    bool expand_node = true;
-    if (ctx->is_site_port(pip)) {
-        switch (curr_node.state) {
-        case ONLY_IN_SOURCE_SITE:
-            expand_node = false;
-            break;
-        case IN_SOURCE_SITE:
-            NPNR_ASSERT(wire_data.site == -1);
-            next_node.state = IN_ROUTING;
-            break;
-        case IN_ROUTING:
-            NPNR_ASSERT(wire_data.site != -1);
-            next_node.state = IN_SINK_SITE;
-            break;
-        case IN_SINK_SITE:
-            expand_node = false;
-            break;
-        default:
-            // Unreachable!!!
-            NPNR_ASSERT(false);
-        }
-    } else {
-        if (curr_node.state == IN_ROUTING)
-            next_node.depth++;
-        next_node.state = curr_node.state;
-    }
-
-    if (expand_node)
-        nodes_to_expand.push_back(next_node);
-    else
-        return;
-
-    if (next_node.state == IN_SINK_SITE || next_node.state == ONLY_IN_SOURCE_SITE) {
-        for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
-            BelId bel = bel_pin.bel;
-            auto const &bel_data = bel_info(ctx->chip_info, bel);
-
-            if (bels.count(bel))
-                continue;
-
-            if (bel_data.category != BEL_CATEGORY_LOGIC)
-                return;
-
-            if (bel_data.synthetic)
-                return;
-
-            if (direction == CLUSTER_UPHILL_DIR) {
-                // Check that the BEL is indeed the one reached by backward exploration,
-                // by checking the previous visited wire.
-                for (IdString check_pin : ctx->getBelPins(bel)) {
-                    if (prev_wire == ctx->getBelPinWire(bel, check_pin)) {
-                        bels.insert(bel);
-                        break;
-                    }
-                }
-            } else {
-                bels.insert(bel);
-            }
-        }
-    }
-
-    return;
-}
-
-static pool<BelId> find_cluster_bels(const Context *ctx, WireId wire, ExpansionDirection direction,
-                                     bool out_of_site_expansion = false)
-{
-    std::vector<ClusterWireNode> nodes_to_expand;
-    pool<BelId> bels;
-
-    const auto &wire_data = ctx->wire_info(wire);
-    NPNR_ASSERT(wire_data.site != -1);
-
-    ClusterWireNode wire_node;
-    wire_node.wire = wire;
-    wire_node.state = IN_SOURCE_SITE;
-    if (!out_of_site_expansion)
-        wire_node.state = ONLY_IN_SOURCE_SITE;
-    wire_node.depth = 0;
-
-    nodes_to_expand.push_back(wire_node);
-
-    while (!nodes_to_expand.empty()) {
-        ClusterWireNode node_to_expand = nodes_to_expand.back();
-        WireId prev_wire = node_to_expand.wire;
-        nodes_to_expand.pop_back();
-
-        if (direction == CLUSTER_DOWNHILL_DIR) {
-            for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
-                if (ctx->is_pip_synthetic(pip))
-                    continue;
-
-                handle_expansion_node(ctx, prev_wire, pip, node_to_expand, nodes_to_expand, bels, direction);
-            }
-        } else {
-            NPNR_ASSERT(direction == CLUSTER_UPHILL_DIR);
-            for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
-                if (ctx->is_pip_synthetic(pip))
-                    continue;
-
-                handle_expansion_node(ctx, prev_wire, pip, node_to_expand, nodes_to_expand, bels, direction);
-            }
-        }
-    }
-
-    return bels;
-}
-
-CellInfo *Arch::getClusterRootCell(ClusterId cluster) const
-{
-    NPNR_ASSERT(cluster != ClusterId());
-    return clusters.at(cluster).root;
-}
-
-bool Arch::normal_cluster_placement(const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
-                                    CellInfo *root_cell, BelId root_bel,
-                                    std::vector<std::pair<CellInfo *, BelId>> &placement) const
-{
-    BelId next_bel;
-
-    // Place cluster
-    for (CellInfo *cluster_node : packed_cluster.cluster_nodes) {
-        if (cluster_node == root_cell) {
-            next_bel = root_bel;
-        } else {
-            // Find next chained cluster node
-            IdString next_bel_pin(cluster_data.chainable_ports[0].bel_source);
-            WireId next_bel_pin_wire = ctx->getBelPinWire(next_bel, next_bel_pin);
-            next_bel = BelId();
-            for (BelId bel :
-                 find_cluster_bels(ctx, next_bel_pin_wire, CLUSTER_DOWNHILL_DIR, /*out_of_site_expansion=*/true)) {
-                if (ctx->isValidBelForCellType(cluster_node->type, bel)) {
-                    next_bel = bel;
-                    break;
-                }
-            }
-
-            if (next_bel == BelId())
-                return false;
-        }
-
-        // Build a cell to bell mapping required to find BELs connected to the cluster ports.
-        dict<IdString, std::vector<IdString>> cell_bel_pins;
-
-        int32_t mapping = bel_info(chip_info, next_bel).pin_map[get_cell_type_index(cluster_node->type)];
-        NPNR_ASSERT(mapping >= 0);
-
-        const CellBelMapPOD &cell_pin_map = chip_info->cell_map->cell_bel_map[mapping];
-        for (const auto &pin_map : cell_pin_map.common_pins) {
-            IdString cell_pin(pin_map.cell_pin);
-            IdString bel_pin(pin_map.bel_pin);
-
-            cell_bel_pins[cell_pin].push_back(bel_pin);
-        }
-
-        placement.emplace_back(cluster_node, next_bel);
-
-        // Place cluster node cells at the same site
-        for (auto port_cell : packed_cluster.cluster_node_cells.at(cluster_node->name)) {
-            bool placed_cell = false;
-
-            IdString port = port_cell.first;
-            CellInfo *cell = port_cell.second;
-
-            NPNR_ASSERT(cell_bel_pins.count(port));
-
-            PortType port_type = cluster_node->ports.at(port).type;
-
-            if (port_type == PORT_INOUT)
-                continue;
-
-            for (auto &bel_pin : cell_bel_pins.at(port)) {
-                WireId bel_pin_wire = ctx->getBelPinWire(next_bel, bel_pin);
-
-                ExpansionDirection direction = port_type == PORT_IN ? CLUSTER_UPHILL_DIR : CLUSTER_DOWNHILL_DIR;
-                pool<BelId> cluster_bels =
-                        find_cluster_bels(ctx, bel_pin_wire, direction, (bool)cluster_data.out_of_site_clusters);
-
-                if (cluster_bels.size() == 0)
-                    continue;
-
-                for (BelId bel : cluster_bels) {
-                    if (ctx->isValidBelForCellType(cell->type, bel)) {
-                        placement.emplace_back(cell, bel);
-                        placed_cell = true;
-                        break;
-                    }
-                }
-
-                if (placed_cell)
-                    break;
-            }
-
-            if (!placed_cell)
-                return false;
-        }
-    }
-
-    return true;
-}
-
-static dict<int32_t, dict<IdString, BelId>> tileAndBelNameToBelIdCache;
-
-BelId check_and_return(int32_t tile, IdString name)
-{
-    if (tileAndBelNameToBelIdCache.count(tile) && tileAndBelNameToBelIdCache[tile].count(name))
-        return tileAndBelNameToBelIdCache[tile][name];
-    else
-        return BelId();
-}
-
-void add_to_cache(int32_t tile, IdString name, BelId t) { tileAndBelNameToBelIdCache[tile][name] = t; }
-
-bool find_site_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel, uint32_t &idx)
-{
-    bool found = false;
-    const auto &site_inst = ctx->get_site_inst(root_bel);
-    IdString site_type(site_inst.site_type);
-
-    if (ctx->debug) {
-        log_info("%s\n", ctx->get_site_name(root_bel));
-        log_info("Root_bel site_type: %s\n", site_type.c_str(ctx));
-        log_info("Allowed site_types:\n");
-    }
-    for (const auto &site : cluster.physical_placements) {
-        IdString name(site.site_type);
-        if (ctx->debug)
-            log_info("\t%s\n", name.c_str(ctx));
-
-        if (name == site_type) {
-            found = true;
-            break;
-        }
-        idx++;
-    }
-    return found;
-}
-
-bool find_placement_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel, uint32_t idx,
-                        uint32_t &placement_idx)
-{
-    bool found = false;
-    const auto &bel_data = bel_info(ctx->chip_info, root_bel);
-    IdString root_bel_name(bel_data.name);
-    if (ctx->debug) {
-        log_info("Root_bel name: %s\n", root_bel_name.c_str(ctx));
-        log_info("Allowed root_bels:\n");
-    }
-    for (const auto &place : cluster.physical_placements[idx].places) {
-        for (const auto bel : place.bels) {
-            IdString name(bel);
-            if (ctx->debug)
-                log_info("\t%s\n", name.c_str(ctx));
-
-            if (name == root_bel_name) {
-                found = true;
-                break;
-            }
-        }
-        if (found)
-            break;
-        placement_idx++;
-    }
-    return found;
-}
-
-dict<uint32_t, BelId> idx_bel_mapping(const Context *ctx, BelId root_bel, const ClusterPOD &cluster, uint32_t idx,
-                                      uint32_t placement_idx)
-{
-    dict<uint32_t, BelId> idx_bel_map;
-    auto root_bel_full_name = ctx->getBelName(root_bel);
-    uint32_t t_idx = 0;
-    if (ctx->debug)
-        log_info("Used bels:\n");
-    for (const auto &bel : cluster.physical_placements[idx].places[placement_idx].bels) {
-        IdString s_bel(bel);
-        BelId t = check_and_return(root_bel.tile, s_bel);
-        IdStringList cpy(root_bel_full_name.size());
-        if (t == BelId()) {
-            for (uint32_t j = 0; j < root_bel_full_name.size(); j++)
-                cpy.ids[j] = root_bel_full_name[j];
-            cpy.ids[root_bel_full_name.size() - 1] = s_bel;
-            t = ctx->getBelByName(cpy);
-            add_to_cache(root_bel.tile, s_bel, t);
-        }
-        if (ctx->debug) {
-            for (uint32_t j = 0; j < root_bel_full_name.size(); j++)
-                cpy.ids[j] = root_bel_full_name[j];
-            cpy.ids[1] = s_bel;
-            for (auto str : cpy)
-                log_info("\t%s\n", str.c_str(ctx));
-        }
-        idx_bel_map[t_idx] = t;
-        t_idx++;
-    }
-    return idx_bel_map;
-}
-
-bool Arch::macro_cluster_placement(const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
-                                   CellInfo *root_cell, BelId root_bel,
-                                   std::vector<std::pair<CellInfo *, BelId>> &placement) const
-{
-    // Check root_bel site_type
-    const auto &cluster = cluster_info(chip_info, packed_cluster.index);
-    uint32_t idx = 0;
-    if (!find_site_idx(ctx, cluster, root_bel, idx))
-        return false;
-
-    // Check if root_bel name
-    uint32_t placement_idx = 0;
-    if (!find_placement_idx(ctx, cluster, root_bel, idx, placement_idx))
-        return false;
-
-    // Map cells to bels
-    dict<uint32_t, BelId> idx_bel_map = idx_bel_mapping(ctx, root_bel, cluster, idx, placement_idx);
-
-    for (auto idx_bel : idx_bel_map) {
-        placement.emplace_back(packed_cluster.cluster_nodes[idx_bel.first], idx_bel.second);
-    }
-
-    return true;
-}
-
-bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
-                               std::vector<std::pair<CellInfo *, BelId>> &placement) const
-{
-    const Context *ctx = getCtx();
-    const Cluster &packed_cluster = clusters.at(cluster);
-
-    auto &cluster_data = cluster_info(chip_info, packed_cluster.index);
-
-    CellInfo *root_cell = getClusterRootCell(cluster);
-    if (!ctx->isValidBelForCellType(root_cell->type, root_bel))
-        return false;
-    if (!cluster_data.from_macro)
-        return normal_cluster_placement(ctx, packed_cluster, cluster_data, root_cell, root_bel, placement);
-    else {
-        bool temp = macro_cluster_placement(ctx, packed_cluster, cluster_data, root_cell, root_bel, placement);
-        return temp;
-    }
-}
-
-BoundingBox Arch::getClusterBounds(ClusterId cluster) const
-{
-    // TODO: Implement this
-    BoundingBox bounds(0, 0, 0, 0);
-    return bounds;
-}
-
-Loc Arch::getClusterOffset(const CellInfo *cell) const
-{
-    Loc offset;
-    CellInfo *root = getClusterRootCell(cell->cluster);
-
-    if (cell->bel != BelId() && root->bel != BelId()) {
-        Loc root_loc = getBelLocation(root->bel);
-        Loc cell_loc = getBelLocation(cell->bel);
-        offset.x = cell_loc.x - root_loc.x;
-        offset.y = cell_loc.y - root_loc.y;
-        offset.z = cell_loc.z - root_loc.z;
-    } else {
-        Cluster cluster = clusters.at(cell->cluster);
-        auto &cluster_data = cluster_info(chip_info, cluster.index);
-
-        if (cluster_data.chainable_ports.size() == 0)
-            return offset;
-
-        auto &chainable_port = cluster_data.chainable_ports[0];
-
-        IdString cluster_node = cluster.cell_cluster_node_map.at(cell->name);
-        CellInfo *cluster_node_cell = cells.at(cluster_node).get();
-
-        auto res = std::find(cluster.cluster_nodes.begin(), cluster.cluster_nodes.end(), cluster_node_cell);
-        NPNR_ASSERT(res != cluster.cluster_nodes.end());
-
-        auto distance = std::distance(cluster.cluster_nodes.begin(), res);
-
-        offset.x = chainable_port.avg_x_offset * distance;
-        offset.y = chainable_port.avg_y_offset * distance;
-    }
-
-    return offset;
-}
-
-bool Arch::isClusterStrict(const CellInfo *cell) const { return true; }
-
-static void dump_clusters(const ChipInfoPOD *chip_info, Context *ctx)
-{
-    for (size_t i = 0; i < chip_info->clusters.size(); ++i) {
-        const auto &cluster = chip_info->clusters[i];
-        IdString cluster_name(cluster.name);
-        log_info("Cluster '%s' loaded! Parameters:\n", cluster_name.c_str(ctx));
-
-        log_info("  - root cell types:\n");
-        for (auto cell : cluster.root_cell_types)
-            log_info("      - %s\n", IdString(cell).c_str(ctx));
-
-        for (auto chain_ports : cluster.chainable_ports)
-            log_info("  - chainable pair: source %s - sink %s\n", IdString(chain_ports.cell_source).c_str(ctx),
-                     IdString(chain_ports.cell_sink).c_str(ctx));
-
-        if (cluster.cluster_cells_map.size() != 0)
-            log_info("  - cell port maps:\n");
-        for (auto cluster_cell : cluster.cluster_cells_map) {
-            log_info("    - cell: %s - port: %s\n", IdString(cluster_cell.cell).c_str(ctx),
-                     IdString(cluster_cell.port).c_str(ctx));
-        }
-    }
-}
-
-static bool check_cluster_cells_compatibility(CellInfo *old_cell, CellInfo *new_cell, pool<IdString> &exclude_nets)
-{
-    NPNR_ASSERT(new_cell->type == old_cell->type);
-    for (auto &new_port_pair : new_cell->ports) {
-        PortInfo new_port_info = new_port_pair.second;
-        PortInfo old_port_info = old_cell->ports.at(new_port_pair.first);
-
-        if (exclude_nets.count(new_port_info.net->name))
-            continue;
-
-        if (new_port_info.type != PORT_IN)
-            continue;
-
-        if (new_port_info.net != old_port_info.net)
-            return false;
-    }
-
-    return true;
-}
-
-bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &domain,
-            Context *ctx)
-{
-    // Reduce X domain by removing values, which don't satisfy binary constraint with values from Y domain.
-    bool change = false;
-    std::vector<CellInfo *> remove_cell;
-    uint32_t counter = 0;
-    for (const auto &connection : cluster->connection_graph[x].connections) {
-        if (connection.target_idx == y)
-            break;
-        counter++;
-    }
-    for (const auto &x_cell : domain[x]) {
-        bool found = false;
-        for (const auto &y_cell : domain[y]) {
-            found = true;
-            for (const auto edge : cluster->connection_graph[x].connections[counter].edges) {
-                if (!x_cell->ports.count(IdString(edge.cell_pin)) ||
-                    !y_cell->ports.count(IdString(edge.other_cell_pin))) {
-                    found = false;
-                    break;
-                }
-                const auto x_net = x_cell->ports[IdString(edge.cell_pin)].net;
-                const auto y_net = y_cell->ports[IdString(edge.other_cell_pin)].net;
-
-                if (x_net != y_net) {
-                    found = false;
-                    break;
-                }
-                bool x_driver = x_net->driver.cell == x_cell;
-                bool y_driver = y_net->driver.cell == y_cell;
-                if ((edge.dir != 0 || !y_driver) && (edge.dir != 1 || !x_driver) &&
-                    (edge.dir != 2 || y_driver || x_driver)) {
-                    found = false;
-                    break;
-                }
-            }
-            if (found)
-                break;
-        }
-        if (!found)
-            remove_cell.push_back(x_cell);
-    }
-
-    for (const auto &cell : remove_cell) {
-        domain[x].erase(cell);
-        change = true;
-    }
-
-    return change;
-}
-
-void binary_constraint_check(const ClusterPOD *cluster, std::queue<std::pair<uint32_t, uint32_t>> &workqueue,
-                             dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx)
-{
-    while (!workqueue.empty()) {
-        std::pair<uint32_t, uint32_t> arc = workqueue.front();
-        workqueue.pop();
-        uint32_t x, y;
-        x = arc.first;
-        y = arc.second;
-        if (reduce(x, y, cluster, idx_to_cells, ctx)) {
-            for (const auto &node : cluster->connection_graph) {
-                if (node.idx != arc.first)
-                    for (const auto &connection : node.connections)
-                        if (connection.target_idx == arc.first)
-                            workqueue.push(std::pair<uint32_t, uint32_t>(node.idx, arc.first));
-            }
-        }
-    }
-}
-
-bool back_solver(const ClusterPOD *cluster, dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx)
-{
-    dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-    for (const auto &arc : idx_to_cells)
-        for (const auto &cell : arc.second)
-            possible_idx[cell].insert(arc.first);
-    std::queue<uint32_t> prep;
-    for (const auto &arc : idx_to_cells) {
-        if (arc.second.size() == 0)
-            return false;
-        if (arc.second.size() > 1) {
-            for (const auto &cell : arc.second) {
-                auto copy_idx_to_cells(idx_to_cells);
-                copy_idx_to_cells[arc.first].clear();
-                for (uint32_t idx : possible_idx[cell]) {
-                    copy_idx_to_cells[idx].erase(cell);
-                    prep.push(idx);
-                }
-                copy_idx_to_cells[arc.first].insert(cell);
-                std::queue<std::pair<uint32_t, uint32_t>> workqueue;
-                while (!prep.empty()) {
-                    uint32_t idx = prep.front();
-                    prep.pop();
-                    for (const auto &connection : cluster->connection_graph[idx].connections)
-                        if (arc.first != connection.target_idx)
-                            workqueue.push(std::pair<uint32_t, uint32_t>(arc.first, connection.target_idx));
-                }
-                binary_constraint_check(cluster, workqueue, copy_idx_to_cells, ctx);
-                if (back_solver(cluster, copy_idx_to_cells, ctx)) {
-                    idx_to_cells = std::move(copy_idx_to_cells);
-                    return true;
-                }
-            }
-        }
-    }
-    return true;
-}
-
-void Arch::prepare_macro_cluster(const ClusterPOD *cluster, uint32_t index)
-{
-    Context *ctx = getCtx();
-    IdString cluster_name(cluster->name);
-
-    pool<IdString> cluster_cell_types;
-    for (auto cell_type : cluster->root_cell_types)
-        cluster_cell_types.insert(IdString(cell_type));
-
-    // Find cluster roots for each macro only ones
-    dict<IdString, CellInfo *> roots;
-    for (auto &cell : cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->macro_parent == IdString())
-            continue;
-        if (ci->cluster != ClusterId())
-            continue;
-        if (!cluster_cell_types.count(ci->type))
-            continue;
-        if (roots.count(ci->macro_parent))
-            continue;
-        // Simple check based on cell type counting
-
-        dict<IdString, uint32_t> cells_in_macro, counter;
-        // cells_in_macro stores cell_types used in tested cluster and
-        // cell_types that are in macro_to_cells[ci->macro_parent]
-
-        pool<IdString> cell_types;
-        for (auto &cell_type : cluster->required_cells) {
-            cells_in_macro[IdString(cell_type.name)] = cell_type.count;
-            cell_types.insert(IdString(cell_type.name));
-        }
-
-        for (auto &node_cell : macro_to_cells[ci->macro_parent]) {
-            auto cell_type = node_cell->type;
-            counter[cell_type]++;
-            cell_types.insert(cell_type);
-        }
-        bool failed = false;
-        for (auto cell_type : cell_types) {
-            if (ctx->verbose && cells_in_macro.count(cell_type))
-                log_info("Required: %s %d\n", cell_type.c_str(ctx), cells_in_macro[cell_type]);
-            if (ctx->verbose && cells_in_macro.count(cell_type))
-                log_info("Have: %s %d\n", cell_type.c_str(ctx), counter[cell_type]);
-            if (!cells_in_macro.count(cell_type) || !counter.count(cell_type) ||
-                cells_in_macro[cell_type] != counter[cell_type])
-                failed = true;
-            if (failed && ctx->verbose)
-                log_info("Cell count stage failed, for sure not this cluster\n");
-            if (failed)
-                break;
-        }
-        if (failed) {
-            roots[ci->macro_parent] = nullptr;
-            continue;
-        }
-
-        // Arc consistency
-        dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> idx_to_cells;
-        // First singular constraints, like used cell type and used_cell ports
-        for (auto &cell : macro_to_cells[ci->macro_parent])
-            for (auto &node : cluster->connection_graph)
-                if (IdString(node.cell_type) == cell->type)
-                    if ((node.idx != 0 && cell->name != ci->name) || (node.idx == 0 && cell->name == ci->name)) {
-                        idx_to_cells[node.idx].insert(cell);
-                    }
-
-        for (auto &arc : idx_to_cells) {
-            std::vector<CellInfo *> remove_cell;
-            pool<IdString> used_ports;
-            for (const auto &port : cluster->connection_graph[arc.first].used_ports)
-                used_ports.insert(IdString(port.name));
-            for (const auto &cell : arc.second) {
-                uint32_t count = 0;
-                for (const auto &port : cell->ports) {
-                    if (!used_ports.count(port.first)) {
-                        remove_cell.push_back(cell);
-                        break;
-                    }
-                    count++;
-                }
-                if (count != used_ports.size()) {
-                    remove_cell.push_back(cell);
-                    break;
-                }
-            }
-            for (const auto &cell : remove_cell) {
-                arc.second.erase(cell);
-            }
-        }
-        if (ctx->debug) {
-            log_info("After mono constraints are applied\n");
-            dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-            for (const auto &arc : idx_to_cells)
-                for (const auto &cell : arc.second)
-                    possible_idx[cell].insert(arc.first);
-
-            for (const auto &arc : possible_idx) {
-                log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
-                for (const auto idx : arc.second)
-                    log_info("    - %d\n", idx);
-            }
-        }
-        // Solve for binary constraints
-        std::queue<std::pair<uint32_t, uint32_t>> workqueue;
-        for (const auto &arc : idx_to_cells)
-            for (const auto &connection : cluster->connection_graph[arc.first].connections)
-                workqueue.emplace(arc.first, connection.target_idx);
-
-        binary_constraint_check(cluster, workqueue, idx_to_cells, ctx);
-        for (const auto &arc : idx_to_cells) {
-            if (arc.second.size() == 0) {
-                if (ctx->debug)
-                    log_info("AC-3 failed\n");
-                failed = true;
-                break;
-            }
-        }
-        if (failed)
-            continue;
-
-        if (ctx->debug) {
-            log_info("After AC-3\n");
-            dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-            for (const auto &arc : idx_to_cells)
-                for (const auto &cell : arc.second)
-                    possible_idx[cell].insert(arc.first);
-
-            for (const auto &arc : possible_idx) {
-                log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
-                for (const auto idx : arc.second)
-                    log_info("    - %d\n", idx);
-            }
-        }
-
-        bool change = false;
-        std::queue<std::pair<uint32_t, CellInfo *>> removequeue;
-        // Keep assigning cells to indices that only map to single cell
-        // Remove this cell from other mappings and recheck binary constraints
-        // Fail if there is no cell for idx or cell has no idx assign
-        do {
-            change = false;
-            dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-            pool<uint32_t> changed_idxs;
-            for (const auto &arc : idx_to_cells) {
-                if (arc.second.size() == 0) {
-                    failed = true;
-                    break;
-                }
-                for (const auto &cell : arc.second)
-                    possible_idx[cell].insert(arc.first);
-            }
-            if (failed)
-                break;
-            for (auto &cell : macro_to_cells[ci->macro_parent])
-                if (possible_idx[cell].size() == 0) {
-                    failed = true;
-                    break;
-                }
-            if (failed)
-                break;
-            for (const auto &arc : idx_to_cells) {
-                if (arc.second.size() == 1)
-                    for (const auto &idx : possible_idx[*arc.second.begin()])
-                        if (idx != arc.first)
-                            removequeue.push(std::pair<uint32_t, CellInfo *>(idx, *arc.second.begin()));
-            }
-            while (!removequeue.empty()) {
-                auto t = removequeue.front();
-                removequeue.pop();
-                uint32_t idx = t.first;
-                CellInfo *cell = t.second;
-                idx_to_cells[idx].erase(cell);
-                change = true;
-                changed_idxs.insert(idx);
-            }
-            for (const uint32_t &idx : changed_idxs)
-                for (const auto &connection : cluster->connection_graph[idx].connections)
-                    workqueue.push(std::pair<uint32_t, uint32_t>(idx, connection.target_idx));
-
-            binary_constraint_check(cluster, workqueue, idx_to_cells, ctx);
-        } while (change);
-        if (failed) {
-            if (ctx->debug)
-                log_info("Single cell mapping failed\n");
-            continue;
-        }
-        if (ctx->debug) {
-            log_info("After mapping indices with single cell\n");
-            dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-            for (const auto &arc : idx_to_cells)
-                for (const auto &cell : arc.second)
-                    possible_idx[cell].insert(arc.first);
-
-            for (const auto &arc : possible_idx) {
-                log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
-                for (const auto idx : arc.second)
-                    log_info("    - %d\n", idx);
-            }
-        }
-        // At this point all indices that cloud only be mapped to single cell are mapped
-        // Next step is to run solver with backtracing to solve for other idx<->cell mappings
-        if (ctx->debug)
-            log_info("Back solver\n");
-        if (!back_solver(cluster, idx_to_cells, ctx)) {
-            if (ctx->debug)
-                log_info("Back solver failed\n");
-            continue;
-        }
-        if (ctx->debug) {
-            log_info("Final mapping after back solver\n");
-            dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
-            for (const auto &arc : idx_to_cells)
-                for (const auto &cell : arc.second)
-                    possible_idx[cell].insert(arc.first);
-
-            for (const auto &arc : possible_idx) {
-                log_info("Possible idx %s:\n", arc.first->name.c_str(ctx));
-                for (const auto idx : arc.second)
-                    log_info("    - %d\n", idx);
-            }
-        }
-        Cluster cluster_info;
-        cluster_info.root = ci;
-        cluster_info.index = index;
-        cluster_info.cluster_nodes.resize(idx_to_cells.size());
-        ci->cluster = ci->name;
-        for (auto &arc : idx_to_cells) {
-            CellInfo *sub_cell = arc.second.pop();
-            if (ctx->verbose)
-                log_info("%d %s - %s\n", arc.first, sub_cell->name.c_str(ctx), sub_cell->type.c_str(ctx));
-            sub_cell->cluster = ci->cluster;
-            cluster_info.cluster_nodes[arc.first] = sub_cell;
-        }
-        clusters.emplace(ci->cluster, cluster_info);
-    }
-}
-
-void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index)
-{
-    Context *ctx = getCtx();
-    IdString cluster_name(cluster->name);
-
-    pool<IdString> cluster_cell_types;
-    for (auto cell_type : cluster->root_cell_types)
-        cluster_cell_types.insert(IdString(cell_type));
-
-    // Find cluster roots
-    std::vector<CellInfo *> roots;
-    for (auto &cell : cells) {
-        CellInfo *ci = cell.second.get();
-        if (ci->macro_parent != IdString())
-            continue;
-
-        if (ci->cluster != ClusterId())
-            continue;
-
-        if (!cluster_cell_types.count(ci->type))
-            continue;
-
-        if (cluster->chainable_ports.size() == 0) {
-            ci->cluster.set(ctx, ci->name.str(ctx));
-            roots.push_back(ci);
-            continue;
-        }
-
-        // Only one type of dedicated interconnect is allowed.
-        auto chain_ports = cluster->chainable_ports[0];
-        IdString source_port(chain_ports.cell_source);
-        IdString sink_port(chain_ports.cell_sink);
-
-        PortRef driver = ci->ports[sink_port].net->driver;
-
-        if (driver.cell == nullptr || driver.port != source_port) {
-            // We hit a root cell
-            ci->cluster.set(ctx, ci->name.c_str(ctx));
-            roots.push_back(ci);
-
-            // Chained cells use dedicated connections, usually not exposed to the
-            // general interconnect resources. The port disconnection is required for
-            // sink ports which are connected to GND or VCC by default, which are not
-            // reachable due to the fixed dedicated interconnect.
-            // E.g.: The CI input of carry chains in 7series corresponds to the CIN bel port,
-            //       which can only be connected to the COUT output of the tile below.
-            ci->disconnectPort(sink_port);
-        }
-    }
-
-    dict<IdString, pool<IdString>> port_cell_maps;
-    for (auto cell_port_map : cluster->cluster_cells_map) {
-        IdString cell(cell_port_map.cell);
-        IdString port(cell_port_map.port);
-
-        pool<IdString> cells_pool({cell});
-
-        port_cell_maps.emplace(port, cells_pool).first->second.insert(cell);
-    }
-
-    // Generate unique clusters starting from each root
-    for (auto root : roots) {
-        Cluster cluster_info;
-        cluster_info.root = root;
-        cluster_info.index = index;
-
-        CellInfo *next_cluster_node = root;
-        if (ctx->verbose)
-            log_info("  - forming cluster starting from root cell: %s\n", next_cluster_node->name.c_str(ctx));
-
-        // counter to determine whether this cluster needs to exist
-        uint32_t count_cluster_cells = 0;
-        do {
-            std::vector<std::pair<IdString, CellInfo *>> cluster_cells;
-
-            // type -> cells map to verify compatibility of cells in the same cluster
-            dict<IdString, CellInfo *> cell_type_dict;
-            pool<IdString> exclude_nets;
-
-            count_cluster_cells++;
-
-            for (auto port : next_cluster_node->ports) {
-                if (!port_cell_maps.count(port.first))
-                    continue;
-
-                PortInfo port_info = port.second;
-
-                if (port_info.type == PORT_OUT) {
-                    exclude_nets.insert(port_info.net->name);
-                    auto &users = port_info.net->users;
-                    if (users.entries() != 1)
-                        continue;
-
-                    CellInfo *user_cell = (*users.begin()).cell;
-                    if (user_cell == nullptr)
-                        continue;
-
-                    if (!port_cell_maps.at(port.first).count(user_cell->type))
-                        continue;
-
-                    auto res = cell_type_dict.emplace(user_cell->type, user_cell);
-                    bool compatible = true;
-                    if (!res.second)
-                        // Check whether a cell of the same type has all the required nets compatible with
-                        // all other nets for the same type. If not, discard the cell.
-                        // An example is multiple FFs belonging to the same cluster, where one of them has a different
-                        // Set/Reset or CE net w.r.t. the others, making the cluster unplaceable.
-                        compatible = check_cluster_cells_compatibility(res.first->second, user_cell, exclude_nets);
-
-                    if (!compatible)
-                        continue;
-
-                    user_cell->cluster = root->cluster;
-                    cluster_cells.push_back(std::make_pair(port.first, user_cell));
-                    cluster_info.cell_cluster_node_map.emplace(user_cell->name, next_cluster_node->name);
-                    count_cluster_cells++;
-
-                    if (ctx->verbose)
-                        log_info("      - adding user cell: %s\n", user_cell->name.c_str(ctx));
-
-                } else if (port_info.type == PORT_IN) {
-                    auto &driver = port_info.net->driver;
-                    auto &users = port_info.net->users;
-                    if (users.entries() != 1)
-                        continue;
-
-                    CellInfo *driver_cell = driver.cell;
-                    if (driver_cell == nullptr)
-                        continue;
-
-                    if (!port_cell_maps.at(port.first).count(driver_cell->type))
-                        continue;
-
-                    driver_cell->cluster = root->cluster;
-                    cluster_cells.push_back(std::make_pair(port.first, driver_cell));
-                    cluster_info.cell_cluster_node_map.emplace(driver_cell->name, next_cluster_node->name);
-                    count_cluster_cells++;
-
-                    if (ctx->verbose)
-                        log_info("      - adding driver cell: %s\n", driver_cell->name.c_str(ctx));
-                }
-            }
-
-            cluster_info.cell_cluster_node_map.emplace(next_cluster_node->name, next_cluster_node->name);
-            cluster_info.cluster_nodes.push_back(next_cluster_node);
-            cluster_info.cluster_node_cells.emplace(next_cluster_node->name, cluster_cells);
-
-            if (cluster->chainable_ports.size() == 0)
-                break;
-
-            // Only one type of dedicated interconnect is allowed.
-            auto chain_ports = cluster->chainable_ports[0];
-            IdString source_port(chain_ports.cell_source);
-            IdString sink_port(chain_ports.cell_sink);
-
-            NetInfo *next_net = next_cluster_node->ports.at(source_port).net;
-
-            if (next_net == nullptr)
-                continue;
-
-            next_cluster_node = nullptr;
-            for (auto &user : next_net->users) {
-                CellInfo *user_cell = user.cell;
-
-                if (user_cell == nullptr)
-                    continue;
-
-                if (cluster_cell_types.count(user_cell->type)) {
-                    user_cell->cluster = root->cluster;
-                    next_cluster_node = user_cell;
-                    break;
-                }
-            }
-
-            if (next_cluster_node == nullptr)
-                break;
-
-        } while (true);
-
-        if (count_cluster_cells == 1 && cluster->chainable_ports.size() == 0) {
-            root->cluster = ClusterId();
-            continue;
-        }
-
-        clusters.emplace(root->cluster, cluster_info);
-    }
-}
-
-void Arch::pack_cluster()
-{
-    Context *ctx = getCtx();
-
-    if (ctx->verbose)
-        dump_clusters(chip_info, ctx);
-
-    for (uint32_t i = 0; i < chip_info->clusters.size(); ++i) {
-        if (!chip_info->clusters[i].from_macro) {
-            const auto &cluster = chip_info->clusters[i];
-
-            prepare_cluster(&cluster, i);
-        } else if (chip_info->clusters[i].physical_placements.size() > 0) {
-            const auto &cluster = chip_info->clusters[i];
-            if (ctx->verbose) {
-                log_info("%s\n", IdString(cluster.name).c_str(ctx));
-            }
-
-            prepare_macro_cluster(&cluster, i);
-        } else {
-            // No physical placement definitions found for given macro.
-            // Use default place and route algorithm as routes connectiong
-            // cells will use global routing
-            const auto &cluster = chip_info->clusters[i];
-            if (ctx->verbose)
-                log_info("Out of site cluster from macro: %s\n", IdString(cluster.name).c_str(ctx));
-        }
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/arch_pack_io.cc b/fpga_interchange/arch_pack_io.cc
deleted file mode 100644
index 3c7c566a08..0000000000
--- a/fpga_interchange/arch_pack_io.cc
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-#include <queue>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace {
-bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell, IdString cell_pin, bool downhill)
-{
-    std::queue<WireId> visit_queue;
-    pool<WireId> already_visited;
-    visit_queue.push(start_wire);
-    already_visited.insert(start_wire);
-    int iter = 0;
-    while (!visit_queue.empty() && iter++ < 1000) {
-        WireId next = visit_queue.front();
-        visit_queue.pop();
-        for (auto bp : arch->getWireBelPins(next)) {
-            if (!arch->isValidBelForCellType(cell->type, bp.bel))
-                continue;
-            if (!arch->checkBelAvail(bp.bel))
-                continue;
-            // We need to do a test placement to update the bel pin map
-            arch->bindBel(bp.bel, cell, STRENGTH_FIXED);
-            for (IdString bel_pin : arch->getBelPinsForCellPin(cell, cell_pin)) {
-                if (bel_pin == bp.pin)
-                    return true;
-            }
-            // Bel pin doesn't match
-            arch->unbindBel(bp.bel);
-        }
-        auto do_visit = [&](PipId pip) {
-            WireId dst = downhill ? arch->getPipDstWire(pip) : arch->getPipSrcWire(pip);
-            if (already_visited.count(dst))
-                return;
-            visit_queue.push(dst);
-            already_visited.insert(dst);
-        };
-        if (downhill) {
-            for (auto pip : arch->getPipsDownhill(next))
-                do_visit(pip);
-        } else {
-            for (auto pip : arch->getPipsUphill(next))
-                do_visit(pip);
-        }
-    }
-    return false;
-}
-} // namespace
-
-void Arch::place_iobufs(WireId pad_wire, NetInfo *net,
-                        const dict<CellInfo *, IdString, hash_ptr_ops> &tightly_attached_bels,
-                        pool<CellInfo *, hash_ptr_ops> *placed_cells)
-{
-    Context *ctx = getCtx();
-    for (auto cell_port : tightly_attached_bels) {
-        bool downhill = (cell_port.first->ports.at(cell_port.second).type != PORT_OUT);
-        if (cell_port.first->bel != BelId())
-            continue;
-        if (search_routing_for_placement(this, pad_wire, cell_port.first, cell_port.second, downhill)) {
-            if (ctx->verbose)
-                log_info("Placed IO cell %s:%s at %s.\n", ctx->nameOf(cell_port.first),
-                         ctx->nameOf(cell_port.first->type), ctx->nameOfBel(cell_port.first->bel));
-            placed_cells->insert(cell_port.first);
-        }
-    }
-
-    // Also try, on a best-effort basis, to preplace other cells in the macro based on downstream routing. This is
-    // needed for the split INBUF+IBUFCTRL arrangement in the UltraScale+, as just placing the INBUF will result in an
-    // unrouteable site and illegal placement.
-    std::queue<CellInfo *> place_queue;
-    for (auto pc : *placed_cells)
-        place_queue.push(pc);
-    while (!place_queue.empty()) {
-        CellInfo *cursor = place_queue.front();
-        place_queue.pop();
-        // Ignore cells not part of a macro
-        if (cursor->macro_parent == IdString())
-            continue;
-        for (auto &port : cursor->ports) {
-            // Only consider routing downstream from outputs for now
-            if (port.second.net == nullptr)
-                continue;
-            NetInfo *ni = port.second.net;
-            if (port.second.type == PORT_OUT) {
-                WireId src_wire = ctx->getNetinfoSourceWire(ni);
-                for (auto &usr : ni->users) {
-                    // Look for unplaced users in the same macro
-                    if (usr.cell->bel != BelId() || usr.cell->macro_parent != cursor->macro_parent)
-                        continue;
-                    // Try and place using dedicated routing
-                    if (search_routing_for_placement(this, src_wire, usr.cell, usr.port, true)) {
-                        // Successful
-                        placed_cells->insert(usr.cell);
-                        place_queue.push(usr.cell);
-                        if (ctx->verbose)
-                            log_info("Placed %s at %s based on dedicated IO macro routing.\n", ctx->nameOf(usr.cell),
-                                     ctx->nameOfBel(usr.cell->bel));
-                    }
-                }
-            } else {
-                auto &drv = ni->driver;
-                // Look for unplaced driver in the same macro
-                if (drv.cell->bel != BelId() || drv.cell->macro_parent != cursor->macro_parent)
-                    continue;
-                for (auto bel_pin : ctx->getBelPinsForCellPin(cursor, port.first)) {
-                    // Try and place using dedicated routing
-                    WireId dst_wire = ctx->getBelPinWire(cursor->bel, bel_pin);
-                    if (search_routing_for_placement(this, dst_wire, drv.cell, drv.port, false)) {
-                        // Successful
-                        placed_cells->insert(drv.cell);
-                        place_queue.push(drv.cell);
-                        if (ctx->verbose)
-                            log_info("Placed %s at %s based on dedicated IO macro routing.\n", ctx->nameOf(drv.cell),
-                                     ctx->nameOfBel(drv.cell->bel));
-                    }
-                }
-            }
-        }
-    }
-    // TODO: for even more complex cases, if any future devices hit them, we probably should do a full validity check of
-    // all placed cells here, and backtrack and try a different placement if the first one we choose isn't legal overall
-}
-
-void Arch::pack_ports()
-{
-    dict<IdString, const TileInstInfoPOD *> tile_type_prototypes;
-    for (size_t i = 0; i < chip_info->tiles.size(); ++i) {
-        const auto &tile = chip_info->tiles[i];
-        const auto &tile_type = chip_info->tile_types[tile.type];
-        IdString tile_type_name(tile_type.name);
-        tile_type_prototypes.emplace(tile_type_name, &tile);
-    }
-
-    // set(site_types) for package pins
-    pool<IdString> package_sites;
-    // Package pin -> (Site type -> BelId)
-    dict<IdString, std::vector<std::pair<IdString, BelId>>> package_pin_bels;
-    // Placed cells across all IO
-    pool<CellInfo *, hash_ptr_ops> all_placed_io;
-    for (const PackagePinPOD &package_pin : chip_info->packages[package_index].pins) {
-        IdString pin(package_pin.package_pin);
-        IdString bel(package_pin.bel);
-
-        IdString site(package_pin.site);
-        package_sites.emplace(site);
-
-        for (size_t i = 0; i < chip_info->tiles.size(); ++i) {
-            const auto &tile = chip_info->tiles[i];
-            pool<uint32_t> package_pin_sites;
-            for (size_t j = 0; j < tile.sites.size(); ++j) {
-                auto &site_data = chip_info->sites[tile.sites[j]];
-                if (site == id(site_data.site_name.get())) {
-                    package_pin_sites.emplace(j);
-                }
-            }
-
-            const auto &tile_type = chip_info->tile_types[tile.type];
-            for (size_t j = 0; j < tile_type.bel_data.size(); ++j) {
-                const BelInfoPOD &bel_data = tile_type.bel_data[j];
-                if (bel == IdString(bel_data.name) && package_pin_sites.count(bel_data.site)) {
-                    auto &site_data = chip_info->sites[tile.sites[bel_data.site]];
-                    IdString site_type(site_data.site_type);
-                    BelId bel;
-                    bel.tile = i;
-                    bel.index = j;
-                    package_pin_bels[pin].push_back(std::make_pair(site_type, bel));
-                }
-            }
-        }
-    }
-
-    // Determine for each package site type, which site types are possible.
-    pool<IdString> package_pin_site_types;
-    dict<IdString, pool<IdString>> possible_package_site_types;
-    for (const TileInstInfoPOD &tile : chip_info->tiles) {
-        for (size_t site_index : tile.sites) {
-            const SiteInstInfoPOD &site = chip_info->sites[site_index];
-            IdString site_name = getCtx()->id(site.site_name.get());
-            if (package_sites.count(site_name) == 1) {
-                possible_package_site_types[site_name].emplace(IdString(site.site_type));
-                package_pin_site_types.emplace(IdString(site.site_type));
-            }
-        }
-    }
-
-    // IO sites are usually pretty weird, so see if we can define some
-    // constraints between the port cell create by nextpnr and cells that are
-    // immediately attached to that port cell.
-    for (auto port_pair : port_cells) {
-        IdString port_name = port_pair.first;
-        CellInfo *port_cell = port_pair.second;
-        dict<CellInfo *, IdString, hash_ptr_ops> tightly_attached_bels;
-
-        for (auto port_pair : port_cell->ports) {
-            const PortInfo &port_info = port_pair.second;
-            const NetInfo *net = port_info.net;
-            if (net->driver.cell) {
-                tightly_attached_bels.emplace(net->driver.cell, net->driver.port);
-            }
-
-            for (const PortRef &port_ref : net->users) {
-                if (port_ref.cell) {
-                    tightly_attached_bels.emplace(port_ref.cell, port_ref.port);
-                }
-            }
-        }
-
-        if (getCtx()->verbose) {
-            log_info("Tightly attached BELs for port %s\n", port_name.c_str(getCtx()));
-            for (auto cell_port : tightly_attached_bels) {
-                log_info(" - %s : %s\n", cell_port.first->name.c_str(getCtx()), cell_port.first->type.c_str(getCtx()));
-            }
-        }
-
-        NPNR_ASSERT(tightly_attached_bels.erase(port_cell) == 1);
-        pool<IdString> cell_types_in_io_group;
-        for (auto cell_port : tightly_attached_bels) {
-            NPNR_ASSERT(port_cells.find(cell_port.first->name) == port_cells.end());
-            cell_types_in_io_group.emplace(cell_port.first->type);
-        }
-
-        // Get possible placement locations for tightly coupled BELs with
-        // port.
-        pool<IdString> possible_site_types;
-        for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
-            IdString tile_type_name(tile_type.name);
-            for (const BelInfoPOD &bel_info : tile_type.bel_data) {
-                if (bel_info.category != BEL_CATEGORY_LOGIC) {
-                    break;
-                }
-
-                for (IdString cell_type : cell_types_in_io_group) {
-                    size_t cell_type_index = get_cell_type_index(cell_type);
-                    if (bel_info.category == BEL_CATEGORY_LOGIC && bel_info.pin_map[cell_type_index] != -1) {
-                        auto *tile = tile_type_prototypes.at(tile_type_name);
-                        const SiteInstInfoPOD &site = chip_info->sites[tile->sites[bel_info.site]];
-
-                        IdString site_type(site.site_type);
-                        if (package_pin_site_types.count(site_type)) {
-                            possible_site_types.emplace(site_type);
-                        }
-                    }
-                }
-            }
-        }
-
-        if (possible_site_types.empty()) {
-            if (getCtx()->verbose)
-                log_info("Port '%s' has no possible site types, falling back to all types!\n",
-                         port_name.c_str(getCtx()));
-            possible_site_types = package_pin_site_types;
-        }
-
-        if (getCtx()->verbose) {
-            log_info("Possible site types for port %s\n", port_name.c_str(getCtx()));
-            for (IdString site_type : possible_site_types) {
-                log_info(" - %s\n", site_type.c_str(getCtx()));
-            }
-        }
-
-        auto iter = port_cell->attrs.find(id("PACKAGE_PIN"));
-        if (iter == port_cell->attrs.end()) {
-            iter = port_cell->attrs.find(id("LOC"));
-            if (iter == port_cell->attrs.end()) {
-                log_error("Port '%s' is missing PACKAGE_PIN or LOC property\n", port_cell->name.c_str(getCtx()));
-            }
-        }
-
-        // dict<IdString, dict<IdString, BelId>> package_pin_bels;
-        IdString package_pin_id = id(iter->second.as_string());
-        auto pin_iter = package_pin_bels.find(package_pin_id);
-        if (pin_iter == package_pin_bels.end()) {
-            log_error("Package pin '%s' not found in part %s\n", package_pin_id.c_str(getCtx()), get_part().c_str());
-        }
-        NPNR_ASSERT(pin_iter != package_pin_bels.end());
-
-        // Select the first BEL from package_bel_pins that is a legal site
-        // type.
-        //
-        // This is likely the most generic (versus specialized) site type.
-        BelId package_bel;
-        for (auto site_type_and_bel : pin_iter->second) {
-            IdString legal_site_type = site_type_and_bel.first;
-            BelId bel = site_type_and_bel.second;
-
-            if (possible_site_types.count(legal_site_type)) {
-                // FIXME: Need to handle case where a port can be in multiple
-                // modes, but only one of the modes works.
-                package_bel = bel;
-                break;
-            }
-        }
-
-        if (package_bel == BelId()) {
-            log_info("Failed to find BEL for package pin '%s' in any possible site types:\n",
-                     package_pin_id.c_str(getCtx()));
-            for (IdString site_type : possible_site_types) {
-                log_info(" - %s\n", site_type.c_str(getCtx()));
-            }
-            log_error("Failed to find BEL for package pin '%s'\n", package_pin_id.c_str(getCtx()));
-        }
-
-        if (getCtx()->verbose) {
-            log_info("Binding port %s to BEL %s\n", port_name.c_str(getCtx()), getCtx()->nameOfBel(package_bel));
-        }
-
-        pool<CellInfo *, hash_ptr_ops> placed_cells;
-        bindBel(package_bel, port_cell, STRENGTH_FIXED);
-        placed_cells.emplace(port_cell);
-
-        IdStringRange package_bel_pins = getBelPins(package_bel);
-        IdString pad_pin = get_only_value(package_bel_pins);
-
-        WireId pad_wire = getBelPinWire(package_bel, pad_pin);
-        place_iobufs(pad_wire, ports[port_pair.first].net, tightly_attached_bels, &placed_cells);
-
-        for (CellInfo *cell : placed_cells)
-            all_placed_io.insert(cell);
-    }
-
-    // Check at the end of IO placement, because differential pairs might need P and N sides to both be placed to be
-    // legal.
-    for (CellInfo *cell : all_placed_io) {
-        log_info("%s\n", getCtx()->nameOf(cell));
-        NPNR_ASSERT(cell->bel != BelId());
-        if (!isBelLocationValid(cell->bel)) {
-            explain_bel_status(cell->bel);
-            log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
-        }
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/arch_place_constr.cc b/fpga_interchange/arch_place_constr.cc
deleted file mode 100644
index 3af48656b5..0000000000
--- a/fpga_interchange/arch_place_constr.cc
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-void Arch::place_constraints()
-{
-    std::vector<std::pair<IdString, BelId>> constrained_cells;
-    for (auto &cell_pair : cells) {
-        CellInfo *cell = cell_pair.second.get();
-        auto loc_constr = cell->attrs.find(id("LOC"));
-        auto bel_constr = cell->attrs.find(id("BEL"));
-
-        if (loc_constr == cell->attrs.end() || bel_constr == cell->attrs.end())
-            continue;
-
-        IdString loc_name = id(loc_constr->second.as_string());
-        IdString bel_name = id(bel_constr->second.as_string());
-
-        BelId bel;
-        for (size_t i = 0; i < chip_info->tiles.size(); ++i) {
-            const auto &tile = chip_info->tiles[i];
-            bool site_found = false;
-            for (size_t j = 0; j < tile.sites.size(); ++j) {
-                auto &site_data = chip_info->sites[tile.sites[j]];
-                if (loc_name == id(site_data.site_name.get())) {
-                    site_found = true;
-                    break;
-                }
-            }
-
-            if (!site_found)
-                continue;
-
-            const auto &tile_type = chip_info->tile_types[tile.type];
-            bool bel_found = false;
-            for (size_t j = 0; j < tile_type.bel_data.size(); ++j) {
-                const BelInfoPOD &bel_data = tile_type.bel_data[j];
-                if (bel_name == IdString(bel_data.name)) {
-                    bel.tile = i;
-                    bel.index = j;
-                    bel_found = true;
-                    break;
-                }
-            }
-
-            if (bel_found)
-                break;
-            else
-                log_error("No bel found for user constraint \'%s/%s\' for cell \'%s\'\n", loc_name.c_str(getCtx()),
-                          bel_name.c_str(getCtx()), cell->name.c_str(getCtx()));
-        }
-
-        if (!isValidBelForCellType(cell->type, bel))
-            log_error("Bel \'%s\' is invalid for cell \'%s\' (%s)\n", nameOfBel(bel), cell->name.c_str(getCtx()),
-                      cell->type.c_str(getCtx()));
-
-        auto bound_cell = getBoundBelCell(bel);
-        if (bound_cell)
-            log_error("Cell \'%s\' cannot be bound to bel \'%s\' "
-                      "since it is already bound to cell \'%s\'\n",
-                      cell->name.c_str(getCtx()), nameOfBel(bel), bound_cell->name.c_str(getCtx()));
-
-        bindBel(bel, cell, STRENGTH_USER);
-
-        cell->attrs.erase(id("BEL"));
-        constrained_cells.emplace_back(cell->name, bel);
-    }
-
-    if (constrained_cells.empty())
-        return;
-
-    log_info("Cell placed via user constraints:\n");
-    for (auto cell_bel : constrained_cells) {
-        IdString cell_name = cell_bel.first;
-        BelId bel = cell_bel.second;
-
-        if (!isBelLocationValid(bel))
-            log_error("  - Bel \'%s\' is not valid for cell \'%s\'\n", nameOfBel(bel), cell_name.c_str(getCtx()));
-
-        log_info("  - %s placed at %s\n", cell_name.c_str(getCtx()), nameOfBel(cell_bel.second));
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/arch_pybindings.cc b/fpga_interchange/arch_pybindings.cc
deleted file mode 100644
index 1ccbaff79e..0000000000
--- a/fpga_interchange/arch_pybindings.cc
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2020  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef NO_PYTHON
-
-#include "arch_pybindings.h"
-#include "nextpnr.h"
-#include "pybindings.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-void arch_wrap_python(py::module &m)
-{
-    using namespace PythonConversion;
-    py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb);
-
-    py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
-
-    py::class_<WireId>(m, "WireId").def_readwrite("index", &WireId::index);
-
-    py::class_<PipId>(m, "PipId").def_readwrite("index", &PipId::index);
-
-    auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
-    auto ctx_cls = py::class_<Context, Arch>(m, "Context")
-                           .def("checksum", &Context::checksum)
-                           .def("pack", &Context::pack)
-                           .def("place", &Context::place)
-                           .def("route", &Context::route);
-
-    fn_wrapper_0a_v<Context, decltype(&Context::remove_site_routing), &Context::remove_site_routing>::def_wrap(
-            ctx_cls, "remove_site_routing");
-    fn_wrapper_1a_v<Context, decltype(&Context::explain_bel_status), &Context::explain_bel_status,
-                    conv_from_str<BelId>>::def_wrap(ctx_cls, "explain_bel_status");
-
-    typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap;
-    typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap;
-    typedef dict<IdString, IdString> AliasMap;
-    typedef dict<IdString, HierarchicalCell> HierarchyMap;
-
-    auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
-    readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
-    readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
-
-    typedef FilteredBelRange BelRangeForBelBucket;
-#include "arch_pybindings_shared.h"
-
-    WRAP_RANGE(m, BelBucket, conv_to_str<BelBucketId>);
-    WRAP_RANGE(m, Bel, conv_to_str<BelId>);
-    WRAP_RANGE(m, Wire, conv_to_str<WireId>);
-    WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
-    WRAP_RANGE(m, UphillPip, conv_to_str<PipId>);
-    WRAP_RANGE(m, DownhillPip, conv_to_str<PipId>);
-    WRAP_RANGE(m, BelPin, wrap_context<BelPin>);
-
-    WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
-    WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
-    WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
-}
-
-NEXTPNR_NAMESPACE_END
-
-#endif // NO_PYTHON
diff --git a/fpga_interchange/arch_pybindings.h b/fpga_interchange/arch_pybindings.h
deleted file mode 100644
index f571daa9e5..0000000000
--- a/fpga_interchange/arch_pybindings.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2020  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-#ifndef ARCH_PYBINDINGS_H
-#define ARCH_PYBINDINGS_H
-#ifndef NO_PYTHON
-
-#include "nextpnr.h"
-#include "pybindings.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace PythonConversion {
-
-template <> struct string_converter<BelId>
-{
-    BelId from_str(Context *ctx, std::string name) { return ctx->getBelByName(IdStringList::parse(ctx, name)); }
-
-    std::string to_str(Context *ctx, BelId id)
-    {
-        if (id == BelId())
-            throw bad_wrap();
-        return ctx->getBelName(id).str(ctx);
-    }
-};
-
-template <> struct string_converter<WireId>
-{
-    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
-
-    std::string to_str(Context *ctx, WireId id)
-    {
-        if (id == WireId())
-            throw bad_wrap();
-        return ctx->getWireName(id).str(ctx);
-    }
-};
-
-template <> struct string_converter<const WireId>
-{
-    WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(IdStringList::parse(ctx, name)); }
-
-    std::string to_str(Context *ctx, WireId id)
-    {
-        if (id == WireId())
-            throw bad_wrap();
-        return ctx->getWireName(id).str(ctx);
-    }
-};
-
-template <> struct string_converter<PipId>
-{
-    PipId from_str(Context *ctx, std::string name) { return ctx->getPipByName(IdStringList::parse(ctx, name)); }
-
-    std::string to_str(Context *ctx, PipId id)
-    {
-        if (id == PipId())
-            throw bad_wrap();
-        return ctx->getPipName(id).str(ctx);
-    }
-};
-
-template <> struct string_converter<BelBucketId>
-{
-    BelBucketId from_str(Context *ctx, std::string name) { return ctx->getBelBucketByName(ctx->id(name)); }
-
-    std::string to_str(Context *ctx, BelBucketId id)
-    {
-        if (id == BelBucketId())
-            throw bad_wrap();
-        return ctx->getBelBucketName(id).str(ctx);
-    }
-};
-
-template <> struct string_converter<BelPin>
-{
-    BelPin from_str(Context *ctx, std::string name)
-    {
-        NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
-    }
-
-    std::string to_str(Context *ctx, BelPin pin)
-    {
-        if (pin.bel == BelId())
-            throw bad_wrap();
-        return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
-    }
-};
-
-} // namespace PythonConversion
-
-NEXTPNR_NAMESPACE_END
-#endif
-#endif
diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h
deleted file mode 100644
index 4a196c2996..0000000000
--- a/fpga_interchange/archdefs.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef FPGA_INTERCHANGE_ARCHDEFS_H
-#define FPGA_INTERCHANGE_ARCHDEFS_H
-
-#include <cstdint>
-
-#include "hashlib.h"
-#include "luts.h"
-#include "nextpnr_namespaces.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-typedef int delay_t;
-
-// -----------------------------------------------------------------------
-
-struct BelId
-{
-    // Tile that contains this BEL.
-    int32_t tile = -1;
-    // Index into tile type BEL array.
-    // BEL indicies are the same for all tiles of the same type.
-    int32_t index = -1;
-
-    bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
-    bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
-    bool operator<(const BelId &other) const
-    {
-        return tile < other.tile || (tile == other.tile && index < other.index);
-    }
-    unsigned int hash() const { return mkhash(tile, index); }
-};
-
-struct WireId
-{
-    // Tile that contains this wire.
-    int32_t tile = -1;
-    int32_t index = -1;
-
-    bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
-    bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
-    bool operator<(const WireId &other) const
-    {
-        return tile < other.tile || (tile == other.tile && index < other.index);
-    }
-    unsigned int hash() const { return mkhash(tile, index); }
-};
-
-struct PipId
-{
-    int32_t tile = -1;
-    int32_t index = -1;
-
-    bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
-    bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
-    bool operator<(const PipId &other) const
-    {
-        return tile < other.tile || (tile == other.tile && index < other.index);
-    }
-    unsigned int hash() const { return mkhash(tile, index); }
-};
-
-struct GroupId
-{
-    bool operator==(const GroupId &other) const { return true; }
-    bool operator!=(const GroupId &other) const { return false; }
-    unsigned int hash() const { return 0; }
-};
-
-struct DecalId
-{
-    bool operator==(const DecalId &other) const { return true; }
-    bool operator!=(const DecalId &other) const { return false; }
-    unsigned int hash() const { return 0; }
-};
-
-struct BelBucketId
-{
-    IdString name;
-
-    bool operator==(const BelBucketId &other) const { return (name == other.name); }
-    bool operator!=(const BelBucketId &other) const { return (name != other.name); }
-    bool operator<(const BelBucketId &other) const { return name < other.name; }
-    unsigned int hash() const { return name.hash(); }
-};
-
-typedef IdString ClusterId;
-
-struct SiteExpansionLoop;
-
-struct ArchNetInfo
-{
-    virtual ~ArchNetInfo();
-
-    SiteExpansionLoop *loop = nullptr;
-};
-
-struct ArchCellInfo
-{
-    int32_t cell_mapping = -1;
-    dict<IdString, std::vector<IdString>> cell_bel_pins;
-    dict<IdString, std::vector<IdString>> masked_cell_bel_pins;
-    pool<IdString> const_ports;
-    IdString macro_parent = IdString();
-    LutCell lut_cell;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* FPGA_INTERCHANGE_ARCHDEFS_H */
diff --git a/fpga_interchange/cell_parameters.cc b/fpga_interchange/cell_parameters.cc
deleted file mode 100644
index e008fea89d..0000000000
--- a/fpga_interchange/cell_parameters.cc
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "cell_parameters.h"
-
-#include <limits>
-
-#include "DeviceResources.capnp.h"
-#include "context.h"
-#include "log.h"
-#include "nextpnr_assertions.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-CellParameters::CellParameters()
-        // 1'b0
-        : verilog_binary_re("([1-9][0-9]*)'b([01]+)$"),
-          // 8'hF
-          verilog_hex_re("([1-9][0-9]*)'h([0-9a-fA-F]+)$"),
-          // 0b10
-          c_binary_re("0b([01]+)$"),
-          // 0xF
-          c_hex_re("0x([0-9a-fA-F]+)$")
-{
-}
-
-void CellParameters::init(const Context *ctx)
-{
-    for (const CellParameterPOD &cell_parameter : ctx->chip_info->cell_map->cell_parameters) {
-        IdString cell_type(cell_parameter.cell_type);
-        IdString parameter(cell_parameter.parameter);
-        auto result = parameters.emplace(std::make_pair(cell_type, parameter), &cell_parameter);
-        NPNR_ASSERT(result.second);
-    }
-}
-
-static bool parse_int(const std::string &data, int64_t *result)
-{
-    NPNR_ASSERT(result != nullptr);
-    try {
-        *result = boost::lexical_cast<int64_t>(data);
-        return true;
-    } catch (boost::bad_lexical_cast &e) {
-        return false;
-    }
-}
-
-DynamicBitarray<> CellParameters::parse_int_like(const Context *ctx, IdString cell_type, IdString parameter,
-                                                 const Property &property) const
-{
-    const CellParameterPOD *definition = parameters.at(std::make_pair(cell_type, parameter));
-    DeviceResources::Device::ParameterFormat format;
-    format = static_cast<DeviceResources::Device::ParameterFormat>(definition->format);
-
-    DynamicBitarray<> result;
-    switch (format) {
-    case DeviceResources::Device::ParameterFormat::BOOLEAN:
-        result.resize(1);
-        if (property.is_string) {
-            if (property.as_string() == "TRUE" || property.as_string() == "1") {
-                result.set(0, true);
-            } else if (property.as_string() == "FALSE" || property.as_string() == "0") {
-                result.set(0, false);
-            } else {
-                log_error("Property value %s not expected for BOOLEAN type.\n", property.c_str());
-            }
-        } else {
-            if (property.intval == 1) {
-                result.set(0, true);
-            } else if (property.intval == 0) {
-                result.set(0, false);
-            } else {
-                log_error("Property value %lu not expected for BOOLEAN type.\n", property.intval);
-            }
-        }
-
-        return result;
-    case DeviceResources::Device::ParameterFormat::INTEGER:
-        if (property.is_string) {
-            char *endptr;
-            std::uintmax_t value = strtoumax(property.c_str(), &endptr, /*base=*/10);
-            if (endptr != (property.c_str() + property.size())) {
-                log_error("Property value %s not expected for INTEGER type.\n", property.c_str());
-            }
-
-            return DynamicBitarray<>::to_bitarray(value);
-        } else {
-            return DynamicBitarray<>::to_bitarray(property.intval);
-        }
-        break;
-    case DeviceResources::Device::ParameterFormat::VERILOG_BINARY:
-        if (property.is_string) {
-            std::smatch m;
-            if (!std::regex_match(property.as_string(), m, verilog_binary_re)) {
-                log_error("Property value %s not expected for VERILOG_BINARY type.\n", property.c_str());
-            }
-
-            int64_t width;
-            if (!parse_int(m[1], &width)) {
-                log_error("Failed to parse width from property value %s of type VERILOG_BINARY.\n", property.c_str());
-            }
-            if (width < 0) {
-                log_error("Expected width to be positive for property value %s\n", property.c_str());
-            }
-
-            return DynamicBitarray<>::parse_binary_bitstring(width, m[2]);
-        } else {
-            return DynamicBitarray<>::to_bitarray(property.intval);
-        }
-        break;
-    case DeviceResources::Device::ParameterFormat::VERILOG_HEX:
-        if (property.is_string) {
-            std::smatch m;
-            if (!std::regex_match(property.as_string(), m, verilog_hex_re)) {
-                log_error("Property value %s not expected for VERILOG_HEX type.\n", property.c_str());
-            }
-
-            int64_t width;
-            if (!parse_int(m[1], &width)) {
-                log_error("Failed to parse width from property value %s of type VERILOG_HEX.\n", property.c_str());
-            }
-            if (width < 0) {
-                log_error("Expected width to be positive for property value %s\n", property.c_str());
-            }
-
-            return DynamicBitarray<>::parse_hex_bitstring(width, m[2]);
-        } else {
-            return DynamicBitarray<>::to_bitarray(property.intval);
-        }
-        break;
-    case DeviceResources::Device::ParameterFormat::C_BINARY:
-        if (property.is_string) {
-            std::smatch m;
-            if (!std::regex_match(property.as_string(), m, c_binary_re)) {
-                log_error("Property value %s not expected for C_BINARY type.\n", property.c_str());
-            }
-
-            return DynamicBitarray<>::parse_binary_bitstring(/*width=*/-1, m[1]);
-        } else {
-            return DynamicBitarray<>::to_bitarray(property.intval);
-        }
-        break;
-    case DeviceResources::Device::ParameterFormat::C_HEX:
-        if (property.is_string) {
-            std::smatch m;
-            if (!std::regex_match(property.as_string(), m, c_hex_re)) {
-                log_error("Property value %s not expected for C_HEX type.\n", property.c_str());
-            }
-
-            return DynamicBitarray<>::parse_hex_bitstring(/*width=*/-1, m[1]);
-        } else {
-            return DynamicBitarray<>::to_bitarray(property.intval);
-        }
-        break;
-    default:
-        log_error("Format %d is not int-like\n", definition->format);
-    }
-
-    // Unreachable!
-    NPNR_ASSERT(false);
-}
-
-bool CellParameters::compare_property(const Context *ctx, IdString cell_type, IdString parameter,
-                                      const Property &property, IdString value_to_compare) const
-{
-    const CellParameterPOD *definition = parameters.at(std::make_pair(cell_type, parameter));
-    DeviceResources::Device::ParameterFormat format;
-    format = static_cast<DeviceResources::Device::ParameterFormat>(definition->format);
-
-    switch (format) {
-    case DeviceResources::Device::ParameterFormat::STRING:
-        return value_to_compare.c_str(ctx) == property.as_string();
-    case DeviceResources::Device::ParameterFormat::FLOATING_POINT:
-        // Note: Comparing floating point is pretty weird
-        log_warning("Doing direct comparisions on floating points values is pretty weird, double check this.  Cell "
-                    "type %s parameter %s\n",
-                    cell_type.c_str(ctx), parameter.c_str(ctx));
-        return value_to_compare.c_str(ctx) == property.as_string();
-    case DeviceResources::Device::ParameterFormat::BOOLEAN:
-    case DeviceResources::Device::ParameterFormat::INTEGER:
-    case DeviceResources::Device::ParameterFormat::VERILOG_BINARY:
-    case DeviceResources::Device::ParameterFormat::VERILOG_HEX:
-    case DeviceResources::Device::ParameterFormat::C_BINARY:
-    case DeviceResources::Device::ParameterFormat::C_HEX: {
-        if (property.is_string) {
-            // Given that string presentations should be equivalent if
-            // formatted consistently, this should work most and or all of
-            // the time.  If there are important exceptions, revisit this.
-            return property.as_string() == value_to_compare.c_str(ctx);
-        } else {
-            int64_t int_to_compare;
-            if (!parse_int(value_to_compare.c_str(ctx), &int_to_compare)) {
-                log_error("Comparision failed, to compare value %s is not int-like\n", value_to_compare.c_str(ctx));
-            }
-
-            return property.intval == int_to_compare;
-        }
-    }
-    }
-
-    // Unreachable!
-    NPNR_ASSERT(false);
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/cell_parameters.h b/fpga_interchange/cell_parameters.h
deleted file mode 100644
index d6d4ccec74..0000000000
--- a/fpga_interchange/cell_parameters.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef CELL_PARAMETERS_H
-#define CELL_PARAMETERS_H
-
-#include <regex>
-
-#include "chipdb.h"
-#include "dynamic_bitarray.h"
-#include "nextpnr_namespaces.h"
-#include "property.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-
-struct CellParameters
-{
-    CellParameters();
-    void init(const Context *ctx);
-    DynamicBitarray<> parse_int_like(const Context *ctx, IdString cell_type, IdString parameter,
-                                     const Property &property) const;
-    bool compare_property(const Context *ctx, IdString cell_type, IdString parameter, const Property &property,
-                          IdString value_to_compare) const;
-
-    dict<std::pair<IdString, IdString>, const CellParameterPOD *> parameters;
-
-    std::regex verilog_binary_re;
-    std::regex verilog_hex_re;
-    std::regex c_binary_re;
-    std::regex c_hex_re;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* CELL_PARAMETERS_H */
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h
deleted file mode 100644
index 7ef0914dec..0000000000
--- a/fpga_interchange/chipdb.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef CHIPDB_H
-#define CHIPDB_H
-
-#include "archdefs.h"
-#include "nextpnr_namespaces.h"
-#include "relptr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-/* !!! Everything in this section must be kept in sync !!!
- * !!! with fpga_interchange/chip_info.py              !!!
- *
- * When schema changes, bump version number in chip_info.py and
- * kExpectedChipInfoVersion
- */
-
-static constexpr int32_t kExpectedChipInfoVersion = 15;
-
-NPNR_PACKED_STRUCT(struct BelConnectedPinsPOD {
-    int32_t pin1;
-    int32_t pin2;
-});
-
-// Flattened site indexing.
-//
-// To enable flat BelId.z spaces, every tile and sites within that tile are
-// flattened.
-//
-// This has implications on BelId's, WireId's and PipId's.
-// The flattened site space works as follows:
-//  - Objects that belong to the tile are first.  BELs are always part of Sites,
-//    so no BEL objects are in this category.
-//  - All site alternative modes are exposed as a "full" site.
-//  - Each site appends it's BEL's, wires (site wires) and PIP's.
-//   - Sites add two types of pips.  Sites will add pip data first for site
-//     pips, and then for site pin edges.
-//     1. The first type is site pips, which connect site wires to other site
-//        wires.
-//     2. The second type is site pin edges, which connect site wires to tile
-//        wires (or vise-versa).
-
-NPNR_PACKED_STRUCT(struct BelInfoPOD {
-    int32_t name;       // bel name (in site) constid
-    int32_t type;       // Type name constid
-    int32_t bel_bucket; // BEL bucket constid.
-
-    int32_t num_bel_wires;
-    RelPtr<int32_t> ports; // port name constid
-    RelPtr<int32_t> types; // port type (IN/OUT/BIDIR)
-    RelPtr<int32_t> wires; // connected wire index in tile, or -1 if NA
-
-    int16_t site;
-    int16_t site_variant; // some sites have alternative types
-    int16_t category;
-    int8_t synthetic;
-    int8_t lut_element;
-
-    RelPtr<int32_t> pin_map; // Index into CellMapPOD::cell_bel_map
-
-    // If this BEL is a site routing BEL with inverting pins, these values
-    // will be [0, num_bel_wires).  If this BEL is either not a site routing
-    // BEL or this site routing has no inversion capabilities, then these will
-    // both be -1.
-    int8_t non_inverting_pin;
-    int8_t inverting_pin;
-
-    int16_t padding;
-
-    RelSlice<BelConnectedPinsPOD> connected_pins;
-});
-
-enum BELCategory
-{
-    // BEL is a logic element
-    BEL_CATEGORY_LOGIC = 0,
-    // BEL is a site routing mux
-    BEL_CATEGORY_ROUTING = 1,
-    // BEL is a site port, e.g. boundry between site and routing graph.
-    BEL_CATEGORY_SITE_PORT = 2
-};
-
-NPNR_PACKED_STRUCT(struct BelPortPOD {
-    int32_t bel_index;
-    int32_t port;
-});
-
-NPNR_PACKED_STRUCT(struct TileWireInfoPOD {
-    int32_t name; // wire name constid
-
-    // Pip index inside tile
-    RelSlice<int32_t> pips_uphill;
-
-    // Pip index inside tile
-    RelSlice<int32_t> pips_downhill;
-
-    // Bel index inside tile
-    RelSlice<BelPortPOD> bel_pins;
-
-    int16_t site;         // site index in tile
-    int16_t site_variant; // site variant index in tile
-});
-
-NPNR_PACKED_STRUCT(struct PipInfoPOD {
-    int32_t src_index, dst_index;
-    int16_t site;         // site index in tile
-    int16_t site_variant; // site variant index in tile
-    int16_t bel;          // BEL this pip belongs to if site pip.
-    int16_t extra_data;
-    RelSlice<int32_t> pseudo_cell_wires;
-});
-
-NPNR_PACKED_STRUCT(struct ConstraintTagPOD {
-    int32_t tag_prefix;       // constid
-    int32_t default_state;    // constid
-    RelSlice<int32_t> states; // constid
-});
-
-NPNR_PACKED_STRUCT(struct LutBelPOD {
-    uint32_t name;          // constid
-    RelSlice<int32_t> pins; // constid
-    uint32_t low_bit;
-    uint32_t high_bit;
-    int32_t out_pin; // constid
-});
-
-NPNR_PACKED_STRUCT(struct LutElementPOD {
-    int32_t width;
-    RelSlice<LutBelPOD> lut_bels;
-});
-
-NPNR_PACKED_STRUCT(struct TileTypeInfoPOD {
-    int32_t name; // Tile type constid
-
-    RelSlice<BelInfoPOD> bel_data;
-
-    RelSlice<TileWireInfoPOD> wire_data;
-
-    RelSlice<PipInfoPOD> pip_data;
-
-    RelSlice<ConstraintTagPOD> tags;
-
-    RelSlice<LutElementPOD> lut_elements;
-
-    RelSlice<int32_t> site_types; // constid
-});
-
-NPNR_PACKED_STRUCT(struct SiteInstInfoPOD {
-    RelPtr<char> name;
-    RelPtr<char> site_name;
-
-    // Which site type is this site instance?
-    // constid
-    int32_t site_type;
-});
-
-NPNR_PACKED_STRUCT(struct TileInstInfoPOD {
-    // Name of this tile.
-    RelPtr<char> name;
-
-    // Index into root.tile_types.
-    int32_t type;
-
-    // This array is root.tile_types[type].site_types.size() long.
-    // Index into root.sites
-    RelSlice<int32_t> sites;
-
-    // Number of tile wires; excluding any site-internal wires
-    // which come after general wires and are not stored here
-    // as they will never be nodal
-    // -1 if a tile-local wire; node index if nodal wire
-    RelSlice<int32_t> tile_wire_to_node;
-
-    // Index into wire_types
-    RelSlice<int16_t> tile_wire_to_type;
-});
-
-NPNR_PACKED_STRUCT(struct TileWireRefPOD {
-    int32_t tile;
-    int32_t index;
-});
-
-NPNR_PACKED_STRUCT(struct NodeInfoPOD { RelSlice<TileWireRefPOD> tile_wires; });
-
-NPNR_PACKED_STRUCT(struct CellBelPinPOD {
-    int32_t cell_pin; // constid
-    int32_t bel_pin;  // constid
-});
-
-NPNR_PACKED_STRUCT(struct ParameterPinsPOD {
-    int32_t key;   // constid
-    int32_t value; // constid
-    RelSlice<CellBelPinPOD> pins;
-});
-
-NPNR_PACKED_STRUCT(struct CellConstraintPOD {
-    int32_t tag;              // Tag index
-    int32_t constraint_type;  // Constraint::ConstraintType
-    RelSlice<int32_t> states; // State indicies
-});
-
-// Cell parameters metadata
-NPNR_PACKED_STRUCT(struct CellParameterPOD {
-    int32_t cell_type;     // constid
-    int32_t parameter;     // constid
-    int32_t format;        // ParameterFormat enum
-    int32_t default_value; // constid
-});
-
-NPNR_PACKED_STRUCT(struct CellBelMapPOD {
-    RelSlice<CellBelPinPOD> common_pins;
-    RelSlice<ParameterPinsPOD> parameter_pins;
-    RelSlice<CellConstraintPOD> constraints;
-});
-
-NPNR_PACKED_STRUCT(struct LutCellPOD {
-    int32_t cell;                 // constid
-    RelSlice<int32_t> input_pins; // constids
-    int32_t parameter;
-});
-
-NPNR_PACKED_STRUCT(struct CellMapPOD {
-    // Cell names supported in this arch.
-    RelSlice<int32_t> cell_names; // constids
-
-    // BEL names that are global buffers.
-    RelSlice<int32_t> global_buffers; // constids
-
-    // Name of BelBuckets.
-    RelSlice<int32_t> cell_bel_buckets; // constids
-
-    RelSlice<CellBelMapPOD> cell_bel_map;
-
-    RelSlice<LutCellPOD> lut_cells;
-    RelSlice<CellParameterPOD> cell_parameters;
-});
-
-NPNR_PACKED_STRUCT(struct PackagePinPOD {
-    int32_t package_pin; // constid
-    int32_t site;        // constid
-    int32_t bel;         // constid
-});
-
-NPNR_PACKED_STRUCT(struct PackagePOD {
-    int32_t package; // constid
-    RelSlice<PackagePinPOD> pins;
-});
-
-enum CellPinValue
-{
-    // leave floating
-    PIN_VALUE_FLOAT = 0,
-    // connect to ground
-    PIN_VALUE_GND = 1,
-    // connect to vcc
-    PIN_VALUE_VCC = 2,
-};
-
-NPNR_PACKED_STRUCT(struct DefaultCellConnPOD {
-    int32_t pin_name; // constid
-    int32_t value;    // CellPinValue
-});
-
-NPNR_PACKED_STRUCT(struct DefaultCellConnsPOD {
-    int32_t cell_type; // constid
-    RelSlice<DefaultCellConnPOD> pins;
-});
-
-NPNR_PACKED_STRUCT(struct ConstantsPOD {
-    // Cell type and port for the GND and VCC global source.
-    int32_t gnd_cell_name; // constid
-    int32_t gnd_cell_port; // constid
-
-    int32_t vcc_cell_name; // constid
-    int32_t vcc_cell_port; // constid
-
-    int32_t gnd_bel_tile;
-    int32_t gnd_bel_index;
-    int32_t gnd_bel_pin; // constid
-
-    int32_t vcc_bel_tile;
-    int32_t vcc_bel_index;
-    int32_t vcc_bel_pin; // constid
-
-    // Name to use for the global GND constant net
-    int32_t gnd_net_name; // constid
-
-    // Name to use for the global VCC constant net
-    int32_t vcc_net_name; // constid
-
-    // If a choice is available, which constant net should be used?
-    // Can be ''/0 if either constant net are equivilent.
-    int32_t best_constant_net; // constid
-
-    // Default cell pin connections
-    RelSlice<DefaultCellConnsPOD> default_conns;
-});
-
-enum WireCategory
-{
-    WIRE_CAT_GENERAL = 0,
-    WIRE_CAT_SPECIAL = 1,
-    WIRE_CAT_GLOBAL = 2,
-};
-
-NPNR_PACKED_STRUCT(struct WireTypePOD {
-    int32_t name;     // constid
-    int32_t category; // WireCategory
-});
-
-NPNR_PACKED_STRUCT(struct GlobalCellPinPOD {
-    int32_t name;     // constid
-    int16_t max_hops; // max routing hops to try
-    int8_t guide_placement;
-    int8_t force_routing;
-});
-
-NPNR_PACKED_STRUCT(struct GlobalCellPOD {
-    int32_t cell_type;
-    RelSlice<GlobalCellPinPOD> pins;
-});
-
-NPNR_PACKED_STRUCT(struct MacroParameterPOD {
-    int32_t key;   // constid
-    int32_t value; // constid
-});
-
-enum MacroParamRuleType
-{
-    PARAM_MAP_COPY = 0,  // copy parameter value
-    PARAM_MAP_SLICE = 1, // take a slice of bits
-    PARAM_MAP_TABLE = 2, // lookup strings in table
-};
-
-NPNR_PACKED_STRUCT(struct MacroParamMapRulePOD {
-    // name of parameter on parent primitive
-    int32_t prim_param; // constid
-    // name of instance to set parameter on
-    int32_t inst_name; // constid
-    // name of parameter on macro expansion instance
-    int32_t inst_param; // constid
-    // type of mapping to use to derive new value
-    int32_t rule_type; // MacroParamRuleType
-    // for slice mappings, the bits to collect
-    RelSlice<uint32_t> slice_bits;
-    // for table mappings, the lookup table to use
-    RelSlice<MacroParameterPOD> map_table;
-});
-
-NPNR_PACKED_STRUCT(struct MacroCellInstPOD {
-    int32_t name; // instance name constid
-    int32_t type; // instance type constid
-    // parameters to set on cell
-    RelSlice<MacroParameterPOD> parameters;
-});
-
-NPNR_PACKED_STRUCT(struct MacroPortInstPOD {
-    // name of the cell instance the port is on; or 0/'' for top level ports
-    int32_t instance;
-    // name of the port
-    int32_t port;
-    // direction of the port
-    int32_t dir;
-});
-
-NPNR_PACKED_STRUCT(struct MacroNetPOD {
-    // name of the net
-    int32_t name;
-    // ports on the net
-    RelSlice<MacroPortInstPOD> ports;
-});
-
-NPNR_PACKED_STRUCT(struct MacroPOD {
-    // macro name
-    int32_t name;
-    // cell instances inside macro
-    RelSlice<MacroCellInstPOD> cell_insts;
-    // nets inside macro
-    RelSlice<MacroNetPOD> nets;
-});
-
-NPNR_PACKED_STRUCT(struct MacroExpansionPOD {
-    // primitive name to match
-    int32_t prim_name;
-    // macro name to expand to
-    int32_t macro_name;
-    // list of parameters to (optionally) match
-    RelSlice<MacroParameterPOD> param_matches;
-    // how to derive parameters for expansion instances
-    RelSlice<MacroParamMapRulePOD> param_rules;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterCellPortPOD {
-    uint32_t cell;
-    uint32_t port;
-});
-
-NPNR_PACKED_STRUCT(struct ChainablePortPOD {
-    uint32_t cell_source;
-    uint32_t cell_sink;
-    uint32_t bel_source;
-    uint32_t bel_sink;
-    int16_t avg_x_offset;
-    int16_t avg_y_offset;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterRequiredCellPOD {
-    uint32_t name;
-    uint32_t count;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterUsedPortPOD { uint32_t name; });
-
-NPNR_PACKED_STRUCT(struct ClusterEdgePOD {
-    uint32_t dir;
-    uint32_t cell_pin;
-    uint32_t other_cell_pin;
-    uint32_t other_cell_type;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterConnectionsPOD {
-    uint32_t target_idx;
-    RelSlice<ClusterEdgePOD> edges;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterConnectionGraphPOD {
-    uint32_t idx;
-    uint32_t cell_type;
-    RelSlice<ClusterConnectionsPOD> connections;
-    RelSlice<ClusterUsedPortPOD> used_ports;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterPhysicalPlacementEntryPOD { RelSlice<uint32_t> bels; });
-
-NPNR_PACKED_STRUCT(struct ClusterPhysicalPlacementsPOD {
-    uint32_t site_type;
-    RelSlice<ClusterPhysicalPlacementEntryPOD> places;
-});
-
-NPNR_PACKED_STRUCT(struct ClusterPOD {
-    uint32_t name;
-    RelSlice<uint32_t> root_cell_types;
-    RelSlice<ChainablePortPOD> chainable_ports;
-    RelSlice<ClusterCellPortPOD> cluster_cells_map;
-    RelSlice<ClusterRequiredCellPOD> required_cells;
-    RelSlice<ClusterConnectionGraphPOD> connection_graph;
-    RelSlice<ClusterPhysicalPlacementsPOD> physical_placements;
-    uint32_t out_of_site_clusters;
-    uint32_t disallow_other_cells;
-    uint32_t from_macro;
-});
-
-NPNR_PACKED_STRUCT(struct ChipInfoPOD {
-    RelPtr<char> name;
-    RelPtr<char> generator;
-
-    int32_t version;
-    int32_t width, height;
-
-    RelSlice<TileTypeInfoPOD> tile_types;
-    RelSlice<SiteInstInfoPOD> sites;
-    RelSlice<TileInstInfoPOD> tiles;
-    RelSlice<NodeInfoPOD> nodes;
-    RelSlice<PackagePOD> packages;
-    RelSlice<WireTypePOD> wire_types;
-    RelSlice<GlobalCellPOD> global_cells;
-
-    // Macro related data
-    RelSlice<MacroPOD> macros;
-    RelSlice<MacroExpansionPOD> macro_rules;
-
-    RelSlice<ClusterPOD> clusters;
-
-    // BEL bucket constids.
-    RelSlice<int32_t> bel_buckets;
-
-    RelPtr<CellMapPOD> cell_map;
-    RelPtr<ConstantsPOD> constants;
-
-    // Constid string data.
-    RelPtr<RelSlice<RelPtr<char>>> constids;
-});
-
-/************************ End of chipdb section. ************************/
-
-inline const TileTypeInfoPOD &tile_info(const ChipInfoPOD *chip_info, int32_t tile)
-{
-    return chip_info->tile_types[chip_info->tiles[tile].type];
-}
-
-template <typename Id> const TileTypeInfoPOD &loc_info(const ChipInfoPOD *chip_info, Id &id)
-{
-    return chip_info->tile_types[chip_info->tiles[id.tile].type];
-}
-
-NPNR_ALWAYS_INLINE inline const BelInfoPOD &bel_info(const ChipInfoPOD *chip_info, BelId bel)
-{
-    NPNR_ASSERT(bel != BelId());
-    return loc_info(chip_info, bel).bel_data[bel.index];
-}
-
-inline const PipInfoPOD &pip_info(const ChipInfoPOD *chip_info, PipId pip)
-{
-    NPNR_ASSERT(pip != PipId());
-    return loc_info(chip_info, pip).pip_data[pip.index];
-}
-
-inline const SiteInstInfoPOD &site_inst_info(const ChipInfoPOD *chip_info, int32_t tile, int32_t site)
-{
-    return chip_info->sites[chip_info->tiles[tile].sites[site]];
-}
-
-inline const ClusterPOD &cluster_info(const ChipInfoPOD *chip_info, int32_t cluster)
-{
-    return chip_info->clusters[cluster];
-}
-
-enum SyntheticType
-{
-    NOT_SYNTH = 0,
-    SYNTH_SIGNAL = 1,
-    SYNTH_GND = 2,
-    SYNTH_VCC = 3,
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* CHIPDB_H */
diff --git a/fpga_interchange/cost_map.cc b/fpga_interchange/cost_map.cc
deleted file mode 100644
index 1062bfd6c9..0000000000
--- a/fpga_interchange/cost_map.cc
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "cost_map.h"
-
-#include "context.h"
-#include "log.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-///@brief Factor to adjust the penalty calculation for deltas outside the segment bounding box:
-//      factor < 1.0: penalty has less impact on the final returned delay
-//      factor > 1.0: penalty has more impact on the final returned delay
-static constexpr float PENALTY_FACTOR = 1.f;
-
-///@brief Minimum penalty cost that is added when penalizing a delta outside the segment bounding box.
-static constexpr delay_t PENALTY_MIN = 1;
-
-// also known as the L1 norm
-static int manhattan_distance(const std::pair<int32_t, int32_t> &a, const std::pair<int32_t, int32_t> &b)
-{
-    return std::abs(b.first - a.first) + std::abs(b.second - a.second);
-}
-
-static delay_t penalize(const delay_t &entry, int distance, delay_t penalty)
-{
-    penalty = std::max(penalty, PENALTY_MIN);
-    return entry + distance * penalty * PENALTY_FACTOR;
-}
-
-delay_t CostMap::get_delay(const Context *ctx, WireId src_wire, WireId dst_wire) const
-{
-    TypeWirePair type_pair;
-    type_pair.src = TypeWireId(ctx, src_wire);
-    type_pair.dst = TypeWireId(ctx, dst_wire);
-
-    int src_tile;
-    if (src_wire.tile == -1) {
-        src_tile = ctx->chip_info->nodes[src_wire.index].tile_wires[0].tile;
-    } else {
-        src_tile = src_wire.tile;
-    }
-
-    int32_t src_x, src_y;
-    ctx->get_tile_x_y(src_tile, &src_x, &src_y);
-
-    int dst_tile;
-    if (dst_wire.tile == -1) {
-        dst_tile = ctx->chip_info->nodes[dst_wire.index].tile_wires[0].tile;
-    } else {
-        dst_tile = dst_wire.tile;
-    }
-
-    int32_t dst_x, dst_y;
-    ctx->get_tile_x_y(dst_tile, &dst_x, &dst_y);
-
-    auto iter = cost_map_.find(type_pair);
-    if (iter == cost_map_.end()) {
-        auto &src_type = ctx->chip_info->tile_types[type_pair.src.type];
-        IdString src_tile_type(src_type.name);
-        IdString src_wire_name(src_type.wire_data[type_pair.src.index].name);
-
-        auto &dst_type = ctx->chip_info->tile_types[type_pair.dst.type];
-        IdString dst_tile_type(dst_type.name);
-        IdString dst_wire_name(dst_type.wire_data[type_pair.dst.index].name);
-
-#if 0
-        log_warning("Delay matrix is missing %s/%s -> %s/%s\n",
-                src_tile_type.c_str(ctx),
-                src_wire_name.c_str(ctx),
-                dst_tile_type.c_str(ctx),
-                dst_wire_name.c_str(ctx));
-#endif
-        return std::numeric_limits<delay_t>::max();
-    }
-
-    const auto &delay_matrix = iter->second;
-
-    int32_t off_x = delay_matrix.offset.first + (dst_x - src_x);
-    int32_t off_y = delay_matrix.offset.second + (dst_y - src_y);
-
-    int32_t x_dim = delay_matrix.data.shape()[0];
-    int32_t y_dim = delay_matrix.data.shape()[1];
-    NPNR_ASSERT(x_dim > 0);
-    NPNR_ASSERT(y_dim > 0);
-
-    // Bound closest_x/y to [0, dim)
-    int32_t closest_x = std::min(std::max(off_x, 0), x_dim - 1);
-    int32_t closest_y = std::min(std::max(off_y, 0), y_dim - 1);
-
-    // Get the cost entry from the cost map at the deltas values
-    auto cost = delay_matrix.data[closest_x][closest_y];
-    NPNR_ASSERT(cost >= 0);
-
-    // Get the base penalty corresponding to the current segment.
-    auto penalty = delay_matrix.penalty;
-
-    // Get the distance between the closest point in the bounding box and the original coordinates.
-    // Note that if the original coordinates are within the bounding box, the distance will be equal to zero.
-    auto distance = manhattan_distance(std::make_pair(off_x, off_y), std::make_pair(closest_x, closest_y));
-
-    // Return the penalized cost (no penalty is added if the coordinates are within the bounding box).
-    return penalize(cost, distance, penalty);
-}
-
-void CostMap::set_cost_map(const Context *ctx, const TypeWirePair &wire_pair,
-                           const dict<std::pair<int32_t, int32_t>, delay_t> &delays)
-{
-    CostMapEntry delay_matrix;
-
-    auto &offset = delay_matrix.offset;
-    offset.first = 0;
-    offset.second = 0;
-
-    int32_t max_x_offset = 0;
-    int32_t max_y_offset = 0;
-
-    for (const auto &delay_pair : delays) {
-        auto &dx_dy = delay_pair.first;
-        offset.first = std::max(-dx_dy.first, offset.first);
-        offset.second = std::max(-dx_dy.second, offset.second);
-        max_x_offset = std::max(dx_dy.first, max_x_offset);
-        max_y_offset = std::max(dx_dy.second, max_y_offset);
-    }
-
-    int32_t x_dim = offset.first + max_x_offset + 1;
-    int32_t y_dim = offset.second + max_y_offset + 1;
-
-    delay_matrix.data.resize(boost::extents[x_dim][y_dim]);
-
-    // Fill matrix with sentinel of -1 to know where the holes in the matrix
-    // are.
-    std::fill_n(delay_matrix.data.data(), delay_matrix.data.num_elements(), -1);
-
-    for (const auto &delay_pair : delays) {
-        auto &dx_dy = delay_pair.first;
-        int32_t off_x = dx_dy.first + offset.first;
-        int32_t off_y = dx_dy.second + offset.second;
-        NPNR_ASSERT(off_x >= 0);
-        NPNR_ASSERT(off_x < x_dim);
-        NPNR_ASSERT(off_y >= 0);
-        NPNR_ASSERT(off_y < y_dim);
-
-        delay_matrix.data[off_x][off_y] = delay_pair.second;
-    }
-
-    delay_matrix.penalty = get_penalty(delay_matrix.data);
-    fill_holes(ctx, wire_pair, delay_matrix.data, delay_matrix.penalty);
-
-    {
-        cost_map_mutex_.lock();
-        auto result = cost_map_.emplace(wire_pair, delay_matrix);
-        NPNR_ASSERT(result.second);
-        cost_map_mutex_.unlock();
-    }
-}
-
-static void assign_min_entry(delay_t *dst, const delay_t &src)
-{
-    if (src >= 0) {
-        if (*dst < 0) {
-            *dst = src;
-        } else if (src < *dst) {
-            *dst = src;
-        }
-    }
-}
-
-std::pair<delay_t, int> CostMap::get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
-                                                       const BoundingBox &bounds)
-{
-#ifdef DEBUG_FILL
-    log_info("Filling %d, %d within (%d, %d, %d, %d)\n", cx, cy, bounds.x0, bounds.y0, bounds.x1, bounds.y1);
-#endif
-
-    // spiral around (cx, cy) looking for a nearby entry
-    bool in_bounds = bounds.contains(cx, cy);
-    if (!in_bounds) {
-#ifdef DEBUG_FILL
-        log_info("Already out of bounds, return!\n");
-#endif
-        return std::make_pair(-1, 0);
-    }
-    int n = 0;
-    delay_t fill(matrix[cx][cy]);
-
-    while (in_bounds && (fill < 0)) {
-        n++;
-#ifdef DEBUG_FILL
-        log_info("At n = %d\n", n);
-#endif
-        in_bounds = false;
-        delay_t min_entry = -1;
-        for (int ox = -n; ox <= n; ox++) {
-            int x = cx + ox;
-            int oy = n - abs(ox);
-            int yp = cy + oy;
-            int yn = cy - oy;
-#ifdef DEBUG_FILL
-            log_info("Testing %d, %d\n", x, yp);
-#endif
-            if (bounds.contains(x, yp)) {
-                assign_min_entry(&min_entry, matrix[x][yp]);
-                in_bounds = true;
-#ifdef DEBUG_FILL
-                log_info("matrix[%d, %d] = %d, min_entry = %d\n", x, yp, matrix[x][yp], min_entry);
-#endif
-            }
-#ifdef DEBUG_FILL
-            log_info("Testing %d, %d\n", x, yn);
-#endif
-            if (bounds.contains(x, yn)) {
-                assign_min_entry(&min_entry, matrix[x][yn]);
-                in_bounds = true;
-#ifdef DEBUG_FILL
-                log_info("matrix[%d, %d] = %d, min_entry = %d\n", x, yn, matrix[x][yn], min_entry);
-#endif
-            }
-        }
-
-        if (fill < 0 && min_entry >= 0) {
-            fill = min_entry;
-        }
-    }
-
-    return std::make_pair(fill, n);
-}
-
-void CostMap::fill_holes(const Context *ctx, const TypeWirePair &type_pair, boost::multi_array<delay_t, 2> &matrix,
-                         delay_t delay_penalty)
-{
-    // find missing cost entries and fill them in by copying a nearby cost entry
-    std::vector<std::tuple<unsigned, unsigned, delay_t>> missing;
-    bool couldnt_fill = false;
-    auto shifted_bounds = BoundingBox(0, 0, matrix.shape()[0] - 1, matrix.shape()[1] - 1);
-    int max_fill = 0;
-    for (unsigned ix = 0; ix < matrix.shape()[0]; ix++) {
-        for (unsigned iy = 0; iy < matrix.shape()[1]; iy++) {
-            delay_t &cost_entry = matrix[ix][iy];
-            if (cost_entry < 0) {
-                // maximum search radius
-                delay_t filler;
-                int distance;
-                std::tie(filler, distance) = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds);
-                if (filler >= 0) {
-                    missing.push_back(std::make_tuple(ix, iy, penalize(filler, distance, delay_penalty)));
-                    max_fill = std::max(max_fill, distance);
-                } else {
-                    couldnt_fill = true;
-                }
-            }
-        }
-        if (couldnt_fill) {
-            // give up trying to fill an empty matrix
-            break;
-        }
-    }
-
-    if (!couldnt_fill && max_fill > 0) {
-        if (ctx->verbose) {
-            auto &src_type_data = ctx->chip_info->tile_types[type_pair.src.type];
-            IdString src_type(src_type_data.name);
-            IdString src_wire(src_type_data.wire_data[type_pair.src.index].name);
-
-            auto &dst_type_data = ctx->chip_info->tile_types[type_pair.dst.type];
-            IdString dst_type(dst_type_data.name);
-            IdString dst_wire(dst_type_data.wire_data[type_pair.dst.index].name);
-
-#ifdef DEBUG_FILL
-            log_info("At %s/%s -> %s/%s: max_fill = %d, delay_penalty = %d\n", src_type.c_str(ctx), src_wire.c_str(ctx),
-                     dst_type.c_str(ctx), dst_wire.c_str(ctx), max_fill, delay_penalty);
-#endif
-        }
-    }
-
-    // write back the missing entries
-    for (auto &xy_entry : missing) {
-        matrix[std::get<0>(xy_entry)][std::get<1>(xy_entry)] = std::get<2>(xy_entry);
-    }
-
-    if (couldnt_fill) {
-        auto &src_type_data = ctx->chip_info->tile_types[type_pair.src.type];
-        IdString src_type(src_type_data.name);
-        IdString src_wire(src_type_data.wire_data[type_pair.src.index].name);
-
-        auto &dst_type_data = ctx->chip_info->tile_types[type_pair.dst.type];
-        IdString dst_type(dst_type_data.name);
-        IdString dst_wire(dst_type_data.wire_data[type_pair.dst.index].name);
-
-        log_warning("Couldn't fill holes in the cost matrix %s/%s -> %s/%s %d x %d bounding box\n", src_type.c_str(ctx),
-                    src_wire.c_str(ctx), dst_type.c_str(ctx), dst_wire.c_str(ctx), shifted_bounds.x1,
-                    shifted_bounds.y1);
-        for (unsigned y = 0; y < matrix.shape()[1]; y++) {
-            for (unsigned x = 0; x < matrix.shape()[0]; x++) {
-                NPNR_ASSERT(matrix[x][y] >= 0);
-            }
-        }
-    }
-}
-
-delay_t CostMap::get_penalty(const boost::multi_array<delay_t, 2> &matrix) const
-{
-    delay_t min_delay = std::numeric_limits<delay_t>::max();
-    delay_t max_delay = std::numeric_limits<delay_t>::lowest();
-
-    std::pair<int32_t, int32_t> min_location(0, 0), max_location(0, 0);
-    for (unsigned ix = 0; ix < matrix.shape()[0]; ix++) {
-        for (unsigned iy = 0; iy < matrix.shape()[1]; iy++) {
-            const delay_t &cost_entry = matrix[ix][iy];
-            if (cost_entry >= 0) {
-                if (cost_entry < min_delay) {
-                    min_delay = cost_entry;
-                    min_location = std::make_pair(ix, iy);
-                }
-                if (cost_entry > max_delay) {
-                    max_delay = cost_entry;
-                    max_location = std::make_pair(ix, iy);
-                }
-            }
-        }
-    }
-
-    delay_t delay_penalty =
-            (max_delay - min_delay) / static_cast<float>(std::max(1, manhattan_distance(max_location, min_location)));
-
-    return delay_penalty;
-}
-
-void CostMap::from_reader(lookahead_storage::CostMap::Reader reader)
-{
-    for (auto cost_entry : reader.getCostMap()) {
-        TypeWirePair key(cost_entry.getKey());
-
-        auto result = cost_map_.emplace(key, CostMapEntry());
-        NPNR_ASSERT(result.second);
-
-        CostMapEntry &entry = result.first->second;
-        auto data = cost_entry.getData();
-        auto in_iter = data.begin();
-
-        entry.data.resize(boost::extents[cost_entry.getXDim()][cost_entry.getYDim()]);
-        if (entry.data.num_elements() != data.size()) {
-            log_error("entry.data.num_elements() %zu != data.size() %u", entry.data.num_elements(), data.size());
-        }
-
-        delay_t *out = entry.data.origin();
-        for (; in_iter != data.end(); ++in_iter, ++out) {
-            *out = *in_iter;
-        }
-
-        entry.penalty = cost_entry.getPenalty();
-
-        entry.offset.first = cost_entry.getXOffset();
-        entry.offset.second = cost_entry.getYOffset();
-    }
-}
-
-void CostMap::to_builder(lookahead_storage::CostMap::Builder builder) const
-{
-    auto cost_map = builder.initCostMap(cost_map_.size());
-    auto entry_iter = cost_map.begin();
-    auto in = cost_map_.begin();
-    for (; entry_iter != cost_map.end(); ++entry_iter, ++in) {
-        NPNR_ASSERT(in != cost_map_.end());
-
-        in->first.to_builder(entry_iter->getKey());
-        const CostMapEntry &entry = in->second;
-
-        auto data = entry_iter->initData(entry.data.num_elements());
-        const delay_t *data_in = entry.data.origin();
-        for (size_t i = 0; i < entry.data.num_elements(); ++i) {
-            data.set(i, data_in[i]);
-        }
-
-        entry_iter->setXDim(entry.data.shape()[0]);
-        entry_iter->setYDim(entry.data.shape()[1]);
-        entry_iter->setXOffset(entry.offset.first);
-        entry_iter->setYOffset(entry.offset.second);
-        entry_iter->setPenalty(entry.penalty);
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/cost_map.h b/fpga_interchange/cost_map.h
deleted file mode 100644
index dfde29f9b2..0000000000
--- a/fpga_interchange/cost_map.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef COST_MAP_H
-#define COST_MAP_H
-
-#include <boost/multi_array.hpp>
-#include <mutex>
-
-#include "lookahead.capnp.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-#include "type_wire.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-
-class CostMap
-{
-  public:
-    delay_t get_delay(const Context *ctx, WireId src, WireId dst) const;
-    void set_cost_map(const Context *ctx, const TypeWirePair &wire_pair,
-                      const dict<std::pair<int32_t, int32_t>, delay_t> &delays);
-
-    void from_reader(lookahead_storage::CostMap::Reader reader);
-    void to_builder(lookahead_storage::CostMap::Builder builder) const;
-
-  private:
-    struct CostMapEntry
-    {
-        boost::multi_array<delay_t, 2> data;
-        std::pair<int32_t, int32_t> offset;
-        delay_t penalty;
-    };
-
-    std::mutex cost_map_mutex_;
-    dict<TypeWirePair, CostMapEntry> cost_map_;
-
-    void fill_holes(const Context *ctx, const TypeWirePair &wire_pair, boost::multi_array<delay_t, 2> &matrix,
-                    delay_t delay_penality);
-
-    std::pair<delay_t, int> get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
-                                                  const BoundingBox &bounds);
-    delay_t get_penalty(const boost::multi_array<delay_t, 2> &matrix) const;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* COST_MAP_H */
diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc
deleted file mode 100644
index e4ce2b951e..0000000000
--- a/fpga_interchange/dedicated_interconnect.cc
+++ /dev/null
@@ -1,902 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-namespace {
-// All legal routes involved at most 2 sites, the source site and the sink
-// site.  The source site and sink sites may be the same, but that is not
-// dedicated routing, that is intra site routing.
-//
-// Dedicated routing must leave the sink site, traverse some routing and
-// terminate at another site.  Routing that "flys" over a site is expressed as
-// a psuedo-pip connected the relevant site pin wires, rather than traversing
-// the site.
-enum WireNodeState
-{
-    IN_SINK_SITE = 0,
-    IN_ROUTING = 1,
-    IN_SOURCE_SITE = 2
-};
-
-enum ExpansionDirection
-{
-    EXPAND_DOWNHILL = 0,
-    EXPAND_UPHILL = 1
-};
-
-struct WireNode
-{
-    WireId wire;
-    WireNodeState state;
-    int depth;
-};
-} // namespace
-
-// Maximum depth that a dedicate interconnect is considered.
-//
-// Routing networks with depth <= kMaxDepth is considers a dedicated
-// interconnect.
-constexpr int kMaxDepth = 6;
-
-static uint32_t get_num_pips(const Context *ctx, WireId wire, ExpansionDirection direction)
-{
-    uint32_t num_pips = 0;
-
-    if (direction == EXPAND_DOWNHILL) {
-        for (PipId pip : ctx->getPipsDownhill(wire)) {
-            auto &pip_data = pip_info(ctx->chip_info, pip);
-            if (pip_data.pseudo_cell_wires.size() > 0)
-                continue;
-
-            if (ctx->getPipDstWire(pip) == WireId())
-                continue;
-
-            if (ctx->is_pip_synthetic(pip))
-                continue;
-
-            if (ctx->is_site_port(pip))
-                continue;
-
-            num_pips++;
-        }
-    } else {
-        NPNR_ASSERT(direction == EXPAND_UPHILL);
-        for (PipId pip : ctx->getPipsUphill(wire)) {
-            auto &pip_data = pip_info(ctx->chip_info, pip);
-            if (pip_data.pseudo_cell_wires.size() > 0)
-                continue;
-
-            if (ctx->getPipSrcWire(pip) == WireId())
-                continue;
-
-            if (ctx->is_pip_synthetic(pip))
-                continue;
-
-            if (ctx->is_site_port(pip))
-                continue;
-
-            num_pips++;
-        }
-    }
-
-    return num_pips;
-}
-
-void DedicatedInterconnect::init(const Context *ctx)
-{
-    this->ctx = ctx;
-
-    if (ctx->debug) {
-        log_info("Finding dedicated interconnect!\n");
-    }
-
-    find_dedicated_interconnect();
-    if (ctx->debug) {
-        print_dedicated_interconnect();
-    }
-}
-
-bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, BelId dst_bel, IdString dst_bel_pin,
-                                          bool site_only) const
-{
-    std::vector<WireNode> nodes_to_expand;
-
-    WireId src_wire = ctx->getBelPinWire(src_bel, src_bel_pin);
-
-    const auto &src_wire_data = ctx->wire_info(src_wire);
-    NPNR_ASSERT(src_wire_data.site != -1);
-
-    WireId dst_wire = ctx->getBelPinWire(dst_bel, dst_bel_pin);
-
-    if (src_wire == dst_wire) {
-        return true;
-    }
-
-    const auto &dst_wire_data = ctx->wire_info(dst_wire);
-    NPNR_ASSERT(dst_wire_data.site != -1);
-
-    WireNode wire_node;
-    wire_node.wire = src_wire;
-    if (src_wire.tile == dst_wire.tile && src_wire_data.site == dst_wire_data.site)
-        wire_node.state = IN_SINK_SITE;
-    else
-        wire_node.state = IN_SOURCE_SITE;
-    wire_node.depth = 0;
-
-    nodes_to_expand.push_back(wire_node);
-
-    while (!nodes_to_expand.empty()) {
-        WireNode node_to_expand = nodes_to_expand.back();
-        nodes_to_expand.pop_back();
-
-        auto num_pips = get_num_pips(ctx, node_to_expand.wire, EXPAND_DOWNHILL);
-
-        // Usually, dedicated interconnects do not have more than one PIPs in the out-of-site
-        if (node_to_expand.depth > 1 && node_to_expand.state == IN_ROUTING && num_pips > 1) {
-            if (ctx->verbose)
-                log_info("Wire %s is on a non-dedicated path (number of pips %d)\n",
-                         ctx->nameOfWire(node_to_expand.wire), num_pips);
-            continue;
-        }
-
-        for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-
-            WireId wire = ctx->getPipDstWire(pip);
-            if (wire == WireId()) {
-                continue;
-            }
-
-            if (ctx->debug) {
-                log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
-            }
-
-            WireNode next_node;
-            next_node.wire = wire;
-            next_node.depth = node_to_expand.depth;
-
-            if (node_to_expand.depth > kMaxDepth) {
-                // Dedicated routing should reach sources by kMaxDepth (with
-                // tuning).
-                //
-                // FIXME: Consider removing kMaxDepth and use kMaxSources?
-                continue;
-            }
-
-            auto const &wire_data = ctx->wire_info(wire);
-
-            bool expand_node = true;
-            if (ctx->is_site_port(pip)) {
-                if (site_only) {
-                    // When routing site only, don't allow site ports.
-                    continue;
-                }
-
-                switch (node_to_expand.state) {
-                case IN_SOURCE_SITE:
-                    NPNR_ASSERT(wire_data.site == -1);
-                    next_node.state = IN_ROUTING;
-                    break;
-                case IN_ROUTING:
-                    NPNR_ASSERT(wire_data.site != -1);
-                    if (wire.tile == src_wire.tile && wire_data.site == src_wire_data.site) {
-                        // Dedicated routing won't have straight loops,
-                        // general routing looks like that.
-#ifdef DEBUG_EXPANSION
-                        log_info(" - Not dedicated site routing because loop!");
-#endif
-                        continue;
-                    }
-                    next_node.state = IN_SINK_SITE;
-                    break;
-                case IN_SINK_SITE:
-                    // Once entering a site, do not leave it again.
-                    // This path is not a legal route!
-                    expand_node = false;
-                    break;
-                default:
-                    // Unreachable!!!
-                    NPNR_ASSERT(false);
-                }
-            } else {
-                next_node.state = node_to_expand.state;
-                if (next_node.state == IN_ROUTING)
-                    next_node.depth++;
-            }
-
-            if (expand_node) {
-                nodes_to_expand.push_back(next_node);
-            } else {
-                continue;
-            }
-
-            if (next_node.state == IN_SINK_SITE) {
-                for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
-                    if (bel_pin.bel == dst_bel && bel_pin.pin == dst_bel_pin) {
-                        if (ctx->debug) {
-                            log_info("Valid dedicated interconnect from %s/%s to %s/%s\n", ctx->nameOfBel(src_bel),
-                                     src_bel_pin.c_str(ctx), ctx->nameOfBel(dst_bel), dst_bel_pin.c_str(ctx));
-                        }
-                        return true;
-                    }
-                }
-            }
-        }
-    }
-
-    return false;
-}
-
-bool DedicatedInterconnect::is_driver_on_net_valid(BelId driver_bel, const CellInfo *cell, IdString driver_port,
-                                                   NetInfo *net) const
-{
-    const auto &driver_bel_data = bel_info(ctx->chip_info, driver_bel);
-
-    TileTypeBelPin type_bel_pin;
-    type_bel_pin.tile_type = ctx->chip_info->tiles[driver_bel.tile].type;
-    type_bel_pin.bel_index = driver_bel.index;
-
-    Loc driver_loc = ctx->getBelLocation(driver_bel);
-
-    for (IdString driver_bel_pin : ctx->getBelPinsForCellPin(cell, driver_port)) {
-        type_bel_pin.bel_pin = driver_bel_pin;
-
-        auto iter = sources.find(type_bel_pin);
-        if (iter == sources.end()) {
-            // This BEL pin doesn't have a dedicate interconnect.
-            continue;
-        }
-
-        for (const PortRef &port_ref : net->users) {
-            NPNR_ASSERT(port_ref.cell != nullptr);
-
-            if (port_ref.cell->bel == BelId()) {
-                // FIXME: This should actually return "unknown!" because the
-                // sink is unplaced.  Once the sink is placed, this constraint
-                // can be evaluated.
-                if (ctx->debug) {
-                    log_info("BEL %s is not valid because sink cell %s/%s is not placed\n", ctx->nameOfBel(driver_bel),
-                             port_ref.cell->name.c_str(ctx), port_ref.port.c_str(ctx));
-                }
-                return false;
-            }
-
-            BelId sink_bel = port_ref.cell->bel;
-            const auto &sink_bel_data = bel_info(ctx->chip_info, sink_bel);
-            Loc sink_loc = ctx->getBelLocation(port_ref.cell->bel);
-
-            if (sink_bel.tile == driver_bel.tile && sink_bel_data.site == driver_bel_data.site) {
-                // This might site local routing.  See if it can be routed
-                for (IdString sink_bel_pin : ctx->getBelPinsForCellPin(port_ref.cell, port_ref.port)) {
-                    if (!check_routing(driver_bel, driver_bel_pin, sink_bel, sink_bel_pin, /*site_only=*/true)) {
-                        return false;
-                    }
-                }
-                continue;
-            }
-
-            DeltaTileTypeBelPin sink_type_bel_pin;
-            sink_type_bel_pin.delta_x = sink_loc.x - driver_loc.x;
-            sink_type_bel_pin.delta_y = sink_loc.y - driver_loc.y;
-            sink_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
-            sink_type_bel_pin.type_bel_pin.bel_index = sink_bel.index;
-
-            for (IdString sink_bel_pin : ctx->getBelPinsForCellPin(port_ref.cell, port_ref.port)) {
-                sink_type_bel_pin.type_bel_pin.bel_pin = sink_bel_pin;
-
-                // Do fast routing check to see if the pair of driver and sink
-                // every are valid.
-                if (iter->second.count(sink_type_bel_pin) == 0) {
-                    if (ctx->debug) {
-                        log_info("BEL %s is not valid because pin %s cannot reach %s/%s\n", ctx->nameOfBel(driver_bel),
-                                 driver_bel_pin.c_str(ctx), ctx->nameOfBel(sink_bel), sink_bel_pin.c_str(ctx));
-                    }
-                    return false;
-                }
-
-                // Do detailed routing check to ensure driver can reach sink.
-                //
-                // FIXME: This might be too slow, but it handles a case on
-                // SLICEL.COUT -> SLICEL.CIN has delta_y = {1, 2}, but the
-                // delta_y=2 case is rare.
-                if (!check_routing(driver_bel, driver_bel_pin, sink_bel, sink_bel_pin, /*site_only=*/false)) {
-                    if (ctx->debug) {
-                        log_info("BEL %s is not valid because pin %s cannot be reach %s/%s (via detailed check)\n",
-                                 ctx->nameOfBel(driver_bel), driver_bel_pin.c_str(ctx), ctx->nameOfBel(sink_bel),
-                                 sink_bel_pin.c_str(ctx));
-                    }
-                    return false;
-                }
-            }
-        }
-    }
-
-    return true;
-}
-
-bool DedicatedInterconnect::is_sink_on_net_valid(BelId bel, const CellInfo *cell, IdString port_name,
-                                                 NetInfo *net) const
-{
-    const auto &bel_data = bel_info(ctx->chip_info, bel);
-    Loc bel_loc = ctx->getBelLocation(bel);
-
-    BelId driver_bel = net->driver.cell->bel;
-
-    for (IdString bel_pin : ctx->getBelPinsForCellPin(cell, port_name)) {
-        TileTypeBelPin type_bel_pin;
-        type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
-        type_bel_pin.bel_index = bel.index;
-        type_bel_pin.bel_pin = bel_pin;
-
-        auto iter = sinks.find(type_bel_pin);
-        if (iter == sinks.end()) {
-            // This BEL pin doesn't have a dedicate interconnect.
-            continue;
-        }
-
-        if (driver_bel == BelId()) {
-            // FIXME: This should actually return "unknown!" because the
-            // driver is unplaced.  Once the driver is placed, this constraint
-            // can be evaluated.
-            if (ctx->debug) {
-                log_info("BEL %s is not valid because driver cell %s/%s is not placed\n", ctx->nameOfBel(bel),
-                         net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
-            }
-            return false;
-        }
-
-        const auto &driver_bel_data = bel_info(ctx->chip_info, driver_bel);
-
-        if (bel.tile == driver_bel.tile && bel_data.site == driver_bel_data.site) {
-            // This is a site local routing, even though this is a sink
-            // with a dedicated interconnect.
-            continue;
-        }
-
-        Loc driver_loc = ctx->getBelLocation(driver_bel);
-
-        DeltaTileTypeBelPin driver_type_bel_pin;
-        driver_type_bel_pin.delta_x = driver_loc.x - bel_loc.x;
-        driver_type_bel_pin.delta_y = driver_loc.y - bel_loc.y;
-        driver_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[driver_bel.tile].type;
-        driver_type_bel_pin.type_bel_pin.bel_index = driver_bel.index;
-        driver_type_bel_pin.type_bel_pin.bel_pin =
-                get_only_value(ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port));
-
-        // Do fast routing check to see if the pair of driver and sink
-        // every are valid.
-        if (iter->second.count(driver_type_bel_pin) == 0) {
-            if (ctx->debug) {
-                log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s\n", ctx->nameOfBel(bel),
-                         bel_pin.c_str(ctx), ctx->nameOfBel(driver_bel),
-                         driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
-            }
-            return false;
-        }
-
-        // Do detailed routing check to ensure driver can reach sink.
-        //
-        // FIXME: This might be too slow, but it handles a case on
-        // SLICEL.COUT -> SLICEL.CIN has delta_y = {1, 2}, but the
-        // delta_y=2 case is rare.
-        if (!check_routing(driver_bel, driver_type_bel_pin.type_bel_pin.bel_pin, bel, bel_pin, /*site_only=*/false)) {
-            if (ctx->debug) {
-                log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s (via detailed check)\n",
-                         ctx->nameOfBel(bel), bel_pin.c_str(ctx), ctx->nameOfBel(driver_bel),
-                         driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
-            }
-            return false;
-        }
-    }
-
-    return true;
-}
-
-bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo *cell) const
-{
-    NPNR_ASSERT(bel != BelId());
-
-    for (const auto &port_pair : cell->ports) {
-        IdString port_name = port_pair.first;
-        NetInfo *net = port_pair.second.net;
-        if (net == nullptr || net->driver.cell == nullptr) {
-            continue;
-        }
-
-        if (ctx->io_port_types.count(net->driver.cell->type)) {
-            continue;
-        }
-
-        // Only check sink BELs.
-        if (net->driver.cell == cell && net->driver.port == port_name) {
-            if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
-                return false;
-            }
-        } else {
-            if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
-                return false;
-            }
-        }
-    }
-
-    return true;
-}
-
-void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell) const
-{
-    NPNR_ASSERT(bel != BelId());
-
-    for (const auto &port_pair : cell->ports) {
-        IdString port_name = port_pair.first;
-        NetInfo *net = port_pair.second.net;
-        if (net == nullptr) {
-            continue;
-        }
-
-        // This net doesn't have a driver, probably not valid?
-        NPNR_ASSERT(net->driver.cell != nullptr);
-
-        if (ctx->io_port_types.count(net->driver.cell->type)) {
-            continue;
-        }
-
-        // Only check sink BELs.
-        if (net->driver.cell == cell && net->driver.port == port_name) {
-            if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
-                log_info("Driver %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
-                         net->name.c_str(ctx));
-            }
-        } else {
-            if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
-                log_info("Sink %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
-                         net->name.c_str(ctx));
-            }
-        }
-    }
-}
-
-void DedicatedInterconnect::print_dedicated_interconnect() const
-{
-    log_info("Found %zu sinks with dedicated interconnect\n", sinks.size());
-    log_info("Found %zu sources with dedicated interconnect\n", sources.size());
-    std::vector<TileTypeBelPin> sorted_keys;
-    for (const auto &sink_to_srcs : sinks) {
-        sorted_keys.push_back(sink_to_srcs.first);
-    }
-    for (const auto &src_to_sinks : sources) {
-        sorted_keys.push_back(src_to_sinks.first);
-    }
-    std::sort(sorted_keys.begin(), sorted_keys.end());
-
-    for (const auto &key : sorted_keys) {
-        auto iter = sinks.find(key);
-        if (iter != sinks.end()) {
-            auto dst = key;
-            for (const auto &src_delta : iter->second) {
-                auto src = src_delta.type_bel_pin;
-                auto delta_x = src_delta.delta_x;
-                auto delta_y = src_delta.delta_y;
-
-                const TileTypeInfoPOD &src_tile_type = ctx->chip_info->tile_types[src.tile_type];
-                const BelInfoPOD &src_bel_info = src_tile_type.bel_data[src.bel_index];
-                IdString src_site_type = IdString(src_tile_type.site_types[src_bel_info.site]);
-                IdString src_bel_pin = src.bel_pin;
-
-                const TileTypeInfoPOD &dst_tile_type = ctx->chip_info->tile_types[dst.tile_type];
-                const BelInfoPOD &dst_bel_info = dst_tile_type.bel_data[dst.bel_index];
-                IdString dst_site_type = IdString(dst_tile_type.site_types[dst_bel_info.site]);
-                IdString dst_bel_pin = dst.bel_pin;
-
-                log_info("%s.%s[%d]/%s/%s (%d, %d) -> %s.%s[%d]/%s/%s\n", IdString(src_tile_type.name).c_str(ctx),
-                         src_site_type.c_str(ctx), src_bel_info.site, IdString(src_bel_info.name).c_str(ctx),
-                         src_bel_pin.c_str(ctx), delta_x, delta_y, IdString(dst_tile_type.name).c_str(ctx),
-                         dst_site_type.c_str(ctx), dst_bel_info.site, IdString(dst_bel_info.name).c_str(ctx),
-                         dst_bel_pin.c_str(ctx));
-            }
-        } else {
-            auto src = key;
-            for (const auto &dst_delta : sources.at(key)) {
-                auto dst = dst_delta.type_bel_pin;
-                auto delta_x = dst_delta.delta_x;
-                auto delta_y = dst_delta.delta_y;
-
-                const TileTypeInfoPOD &src_tile_type = ctx->chip_info->tile_types[src.tile_type];
-                const BelInfoPOD &src_bel_info = src_tile_type.bel_data[src.bel_index];
-                IdString src_site_type = IdString(src_tile_type.site_types[src_bel_info.site]);
-                IdString src_bel_pin = src.bel_pin;
-
-                const TileTypeInfoPOD &dst_tile_type = ctx->chip_info->tile_types[dst.tile_type];
-                const BelInfoPOD &dst_bel_info = dst_tile_type.bel_data[dst.bel_index];
-                IdString dst_site_type = IdString(dst_tile_type.site_types[dst_bel_info.site]);
-                IdString dst_bel_pin = dst.bel_pin;
-
-                log_info("%s.%s[%d]/%s/%s -> %s.%s[%d]/%s/%s  (%d, %d)\n", IdString(src_tile_type.name).c_str(ctx),
-                         src_site_type.c_str(ctx), src_bel_info.site, IdString(src_bel_info.name).c_str(ctx),
-                         src_bel_pin.c_str(ctx), IdString(dst_tile_type.name).c_str(ctx), dst_site_type.c_str(ctx),
-                         dst_bel_info.site, IdString(dst_bel_info.name).c_str(ctx), dst_bel_pin.c_str(ctx), delta_x,
-                         delta_y);
-            }
-        }
-    }
-}
-
-void DedicatedInterconnect::find_dedicated_interconnect()
-{
-    for (BelId bel : ctx->getBels()) {
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-        if (bel_data.category != BEL_CATEGORY_LOGIC) {
-            continue;
-        }
-        if (bel_data.synthetic) {
-            continue;
-        }
-
-        for (int i = 0; i < bel_data.num_bel_wires; ++i) {
-            if (bel_data.types[i] != PORT_IN) {
-                continue;
-            }
-
-            WireId wire;
-            wire.tile = bel.tile;
-            wire.index = bel_data.wires[i];
-
-            expand_sink_bel(bel, IdString(bel_data.ports[i]), wire);
-        }
-    }
-
-    pool<TileTypeBelPin> seen_pins;
-    for (auto sink_pair : sinks) {
-        for (auto src : sink_pair.second) {
-            seen_pins.emplace(src.type_bel_pin);
-        }
-    }
-
-    for (BelId bel : ctx->getBels()) {
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-        if (bel_data.category != BEL_CATEGORY_LOGIC) {
-            continue;
-        }
-        if (bel_data.synthetic) {
-            continue;
-        }
-
-        for (int i = 0; i < bel_data.num_bel_wires; ++i) {
-            if (bel_data.types[i] != PORT_OUT || bel_data.wires[i] == -1) {
-                continue;
-            }
-
-            IdString bel_pin(bel_data.ports[i]);
-
-            TileTypeBelPin type_bel_pin;
-            type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
-            type_bel_pin.bel_index = bel.index;
-            type_bel_pin.bel_pin = bel_pin;
-
-            // Don't visit src pins already handled in the sink expansion!
-            if (seen_pins.count(type_bel_pin)) {
-                continue;
-            }
-
-            WireId wire;
-            wire.tile = bel.tile;
-            wire.index = bel_data.wires[i];
-
-            expand_source_bel(bel, bel_pin, wire);
-        }
-    }
-}
-
-void DedicatedInterconnect::expand_sink_bel(BelId sink_bel, IdString sink_pin, WireId sink_wire)
-{
-    NPNR_ASSERT(sink_bel != BelId());
-#ifdef DEBUG_EXPANSION
-    log_info("Expanding from %s/%s\n", ctx->nameOfBel(sink_bel), pin.c_str(ctx));
-#endif
-
-    std::vector<WireNode> nodes_to_expand;
-
-    const auto &sink_wire_data = ctx->wire_info(sink_wire);
-    NPNR_ASSERT(sink_wire_data.site != -1);
-
-    WireNode wire_node;
-    wire_node.wire = sink_wire;
-    wire_node.state = IN_SINK_SITE;
-    wire_node.depth = 0;
-
-    nodes_to_expand.push_back(wire_node);
-
-    Loc sink_loc = ctx->getBelLocation(sink_bel);
-    pool<DeltaTileTypeBelPin> srcs;
-
-    while (!nodes_to_expand.empty()) {
-        WireNode node_to_expand = nodes_to_expand.back();
-        nodes_to_expand.pop_back();
-
-        for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-
-            WireId wire = ctx->getPipSrcWire(pip);
-            if (wire == WireId()) {
-                continue;
-            }
-
-#ifdef DEBUG_EXPANSION
-            log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
-#endif
-
-            WireNode next_node;
-            next_node.wire = wire;
-            next_node.depth = node_to_expand.depth;
-
-            if (node_to_expand.depth > kMaxDepth) {
-                // Dedicated routing should reach sources by kMaxDepth (with
-                // tuning).
-                //
-                // FIXME: Consider removing kMaxDepth and use kMaxSources?
-#ifdef DEBUG_EXPANSION
-                log_info(" - Exceeded max depth!\n");
-#endif
-                return;
-            }
-
-            auto const &wire_data = ctx->wire_info(wire);
-
-            bool expand_node = true;
-            if (ctx->is_site_port(pip)) {
-                switch (node_to_expand.state) {
-                case IN_SINK_SITE:
-                    NPNR_ASSERT(wire_data.site == -1);
-                    next_node.state = IN_ROUTING;
-                    break;
-                case IN_ROUTING:
-                    NPNR_ASSERT(wire_data.site != -1);
-                    if (wire.tile == sink_wire.tile && wire_data.site == sink_wire_data.site) {
-                        // Dedicated routing won't have straight loops,
-                        // general routing looks like that.
-#ifdef DEBUG_EXPANSION
-                        log_info(" - Not dedicated site routing because loop!");
-#endif
-                        return;
-                    }
-                    next_node.state = IN_SOURCE_SITE;
-                    break;
-                case IN_SOURCE_SITE:
-                    // Once entering a site, do not leave it again.
-                    // This path is not a legal route!
-                    expand_node = false;
-                    break;
-                default:
-                    // Unreachable!!!
-                    NPNR_ASSERT(false);
-                }
-            } else {
-                next_node.state = node_to_expand.state;
-                if (next_node.state == IN_ROUTING)
-                    next_node.depth++;
-            }
-
-            if (expand_node) {
-                nodes_to_expand.push_back(next_node);
-            } else {
-                continue;
-            }
-
-            if (next_node.state == IN_SOURCE_SITE) {
-                for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
-                    BelId src_bel = bel_pin.bel;
-                    auto const &bel_data = bel_info(ctx->chip_info, src_bel);
-
-                    if (bel_data.category != BEL_CATEGORY_LOGIC) {
-                        continue;
-                    }
-                    if (bel_data.synthetic) {
-                        continue;
-                    }
-                    if (ctx->getBelPinType(bel_pin.bel, bel_pin.pin) != PORT_OUT) {
-                        continue;
-                    }
-
-#ifdef DEBUG_EXPANSION
-                    log_info(" - Reached %s/%s\n", ctx->nameOfBel(bel_pin.bel), bel_pin.pin.c_str(ctx));
-#endif
-
-                    Loc src_loc = ctx->getBelLocation(src_bel);
-
-                    DeltaTileTypeBelPin delta_type_bel_pin;
-                    delta_type_bel_pin.delta_x = src_loc.x - sink_loc.x;
-                    delta_type_bel_pin.delta_y = src_loc.y - sink_loc.y;
-                    delta_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[src_bel.tile].type;
-                    delta_type_bel_pin.type_bel_pin.bel_index = src_bel.index;
-                    delta_type_bel_pin.type_bel_pin.bel_pin = bel_pin.pin;
-                    srcs.emplace(delta_type_bel_pin);
-                }
-            }
-        }
-    }
-
-    TileTypeBelPin type_bel_pin;
-    type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
-    type_bel_pin.bel_index = sink_bel.index;
-    type_bel_pin.bel_pin = sink_pin;
-
-    auto result = sinks.emplace(type_bel_pin, srcs);
-    if (!result.second) {
-        // type_bel_pin was already present! Add any new sources from this
-        // sink type (if any);
-        for (auto src : srcs) {
-            result.first->second.emplace(src);
-        }
-    }
-}
-
-void DedicatedInterconnect::expand_source_bel(BelId src_bel, IdString src_pin, WireId src_wire)
-{
-    NPNR_ASSERT(src_bel != BelId());
-#ifdef DEBUG_EXPANSION
-    log_info("Expanding from %s/%s\n", ctx->nameOfBel(src_bel), src_pin.c_str(ctx));
-#endif
-
-    std::vector<WireNode> nodes_to_expand;
-
-    const auto &src_wire_data = ctx->wire_info(src_wire);
-    NPNR_ASSERT(src_wire_data.site != -1);
-
-    WireNode wire_node;
-    wire_node.wire = src_wire;
-    wire_node.state = IN_SOURCE_SITE;
-    wire_node.depth = 0;
-
-    nodes_to_expand.push_back(wire_node);
-
-    Loc src_loc = ctx->getBelLocation(src_bel);
-    pool<DeltaTileTypeBelPin> dsts;
-
-    while (!nodes_to_expand.empty()) {
-        WireNode node_to_expand = nodes_to_expand.back();
-        nodes_to_expand.pop_back();
-
-        for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-
-            WireId wire = ctx->getPipDstWire(pip);
-            if (wire == WireId()) {
-                continue;
-            }
-
-#ifdef DEBUG_EXPANSION
-            log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
-#endif
-
-            WireNode next_node;
-            next_node.wire = wire;
-            next_node.depth = node_to_expand.depth;
-
-            if (node_to_expand.depth > kMaxDepth) {
-                // Dedicated routing should reach sources by kMaxDepth (with
-                // tuning).
-                //
-                // FIXME: Consider removing kMaxDepth and use kMaxSources?
-#ifdef DEBUG_EXPANSION
-                log_info(" - Exceeded max depth!\n");
-#endif
-                return;
-            }
-
-            auto const &wire_data = ctx->wire_info(wire);
-
-            bool expand_node = true;
-            if (ctx->is_site_port(pip)) {
-                switch (node_to_expand.state) {
-                case IN_SOURCE_SITE:
-                    NPNR_ASSERT(wire_data.site == -1);
-                    next_node.state = IN_ROUTING;
-                    break;
-                case IN_ROUTING:
-                    NPNR_ASSERT(wire_data.site != -1);
-                    if (wire.tile == src_wire.tile && wire_data.site == src_wire_data.site) {
-                        // Dedicated routing won't have straight loops,
-                        // general routing looks like that.
-#ifdef DEBUG_EXPANSION
-                        log_info(" - Not dedicated site routing because loop!");
-#endif
-                        return;
-                    }
-                    next_node.state = IN_SINK_SITE;
-                    break;
-                case IN_SINK_SITE:
-                    // Once entering a site, do not leave it again.
-                    // This path is not a legal route!
-                    expand_node = false;
-                    break;
-                default:
-                    // Unreachable!!!
-                    NPNR_ASSERT(false);
-                }
-            } else {
-                next_node.state = node_to_expand.state;
-                if (next_node.state == IN_ROUTING)
-                    next_node.depth++;
-            }
-
-            if (expand_node) {
-                nodes_to_expand.push_back(next_node);
-            } else {
-                continue;
-            }
-
-            if (next_node.state == IN_SINK_SITE) {
-                for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
-                    BelId sink_bel = bel_pin.bel;
-                    auto const &bel_data = bel_info(ctx->chip_info, sink_bel);
-
-                    if (bel_data.category != BEL_CATEGORY_LOGIC) {
-                        continue;
-                    }
-                    if (bel_data.synthetic) {
-                        continue;
-                    }
-                    if (ctx->getBelPinType(bel_pin.bel, bel_pin.pin) != PORT_IN) {
-                        continue;
-                    }
-
-#ifdef DEBUG_EXPANSION
-                    log_info(" - Reached %s/%s\n", ctx->nameOfBel(bel_pin.bel), bel_pin.pin.c_str(ctx));
-#endif
-
-                    Loc sink_loc = ctx->getBelLocation(sink_bel);
-
-                    DeltaTileTypeBelPin delta_type_bel_pin;
-                    delta_type_bel_pin.delta_x = sink_loc.x - src_loc.x;
-                    delta_type_bel_pin.delta_y = sink_loc.y - src_loc.y;
-                    delta_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
-                    delta_type_bel_pin.type_bel_pin.bel_index = sink_bel.index;
-                    delta_type_bel_pin.type_bel_pin.bel_pin = bel_pin.pin;
-                    dsts.emplace(delta_type_bel_pin);
-                }
-            }
-        }
-    }
-
-    TileTypeBelPin type_bel_pin;
-    type_bel_pin.tile_type = ctx->chip_info->tiles[src_bel.tile].type;
-    type_bel_pin.bel_index = src_bel.index;
-    type_bel_pin.bel_pin = src_pin;
-
-    auto result = sources.emplace(type_bel_pin, dsts);
-    if (!result.second) {
-        // type_bel_pin was already present! Add any new sources from this
-        // sink type (if any);
-        for (auto dst : dsts) {
-            result.first->second.emplace(dst);
-        }
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/dedicated_interconnect.h b/fpga_interchange/dedicated_interconnect.h
deleted file mode 100644
index 085ced2646..0000000000
--- a/fpga_interchange/dedicated_interconnect.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef DEDICATED_INTERCONNECT_H
-#define DEDICATED_INTERCONNECT_H
-
-#include <boost/functional/hash.hpp>
-#include <cstdint>
-
-#include "archdefs.h"
-#include "hashlib.h"
-#include "idstring.h"
-#include "nextpnr_namespaces.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct TileTypeBelPin
-{
-    int32_t tile_type;
-    int32_t bel_index;
-    IdString bel_pin;
-
-    bool operator<(const TileTypeBelPin &other) const
-    {
-        if (tile_type >= other.tile_type) {
-            return false;
-        }
-
-        if (bel_index >= other.bel_index) {
-            return false;
-        }
-
-        return bel_pin < other.bel_pin;
-    }
-
-    bool operator==(const TileTypeBelPin &other) const
-    {
-        return tile_type == other.tile_type && bel_index == other.bel_index && bel_pin == other.bel_pin;
-    }
-    bool operator!=(const TileTypeBelPin &other) const
-    {
-        return tile_type != other.tile_type || bel_index != other.bel_index || bel_pin != other.bel_pin;
-    }
-    unsigned int hash() const { return mkhash(mkhash(tile_type, bel_index), bel_pin.hash()); }
-};
-
-struct DeltaTileTypeBelPin
-{
-    int32_t delta_x;
-    int32_t delta_y;
-    TileTypeBelPin type_bel_pin;
-
-    bool operator==(const DeltaTileTypeBelPin &other) const
-    {
-        return delta_x == other.delta_x && delta_y == other.delta_y && type_bel_pin == other.type_bel_pin;
-    }
-    bool operator!=(const DeltaTileTypeBelPin &other) const
-    {
-        return delta_x != other.delta_x || delta_y != other.delta_y || type_bel_pin != other.type_bel_pin;
-    }
-    unsigned int hash() const { return mkhash(mkhash(delta_x, delta_y), type_bel_pin.hash()); }
-};
-
-struct Context;
-
-// This class models dedicated interconnect present in the given fabric.
-//
-// Examples of dedicate interconnect:
-//  - IBUF.O -> ISERDES.I
-//  - IBUF.O -> IDELAY.I
-//  - CARRY4.CO[3] -> CARRY4.CIN
-//
-//  Note that CARRY4.CYINIT does not **require** dedicated interconnect, so
-//  it doesn't qualify.
-//
-//  This class discovers dedicated interconnect by examing the routing graph.
-//  This discovery make be expensive, and require caching to accelerate
-//  startup.
-struct DedicatedInterconnect
-{
-    const Context *ctx;
-
-    dict<TileTypeBelPin, pool<DeltaTileTypeBelPin>> sinks;
-    dict<TileTypeBelPin, pool<DeltaTileTypeBelPin>> sources;
-
-    void init(const Context *ctx);
-
-    // Is this BEL placed in a location that is valid based on dedicated
-    // interconnect?
-    //
-    // Note: Only BEL pin sinks are checked.
-    bool isBelLocationValid(BelId bel, const CellInfo *cell) const;
-    void explain_bel_status(BelId bel, const CellInfo *cell) const;
-
-    void find_dedicated_interconnect();
-    void print_dedicated_interconnect() const;
-    bool check_routing(BelId src_bel, IdString src_bel_pin, BelId dst_bel, IdString dst_bel_pin, bool site_only) const;
-    void expand_sink_bel(BelId bel, IdString pin, WireId wire);
-    void expand_source_bel(BelId bel, IdString pin, WireId wire);
-
-    bool is_driver_on_net_valid(BelId driver_bel, const CellInfo *cell, IdString driver_port, NetInfo *net) const;
-    bool is_sink_on_net_valid(BelId bel, const CellInfo *cell, IdString port_name, NetInfo *net) const;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* DEDICATED_INTERCONNECT_H */
diff --git a/fpga_interchange/examples/README.md b/fpga_interchange/examples/README.md
deleted file mode 100644
index 6c1da117bd..0000000000
--- a/fpga_interchange/examples/README.md
+++ /dev/null
@@ -1,76 +0,0 @@
-## FPGA interchange instructions
-
-These are instructions on how to get the dependencies, generate the FPGA interchange architecture build system and
-run some example designs.
-
-
-### Installing dependencies
-
-Install java and javac if not already installed:
-```
-# Or equivalent for your local system.
-sudo apt-get install openjdk-10-jdk
-```
-
-Install capnproto if not already installed. Version 0.8.0 is required.
-As stated in the [official instructions](https://capnproto.org/install.html), the version on the common package managers
-might not be up to date with the latest version, hence it is suggested to install
-from the archive or, in alternative, directly from the git repository.
-
-Install capnproto-java if not already installed:
-```
-git clone https://github.com/capnproto/capnproto-java.git
-cd capnproto-java
-make
-sudo make install
-```
-
-Install python-fpga-interchange if not already installed:
-```
-git clone https://github.com/SymbiFlow/python-fpga-interchange.git
-cd python-fpga-interchange.git
-#
-# Note: Recommend checking out a specific release, for example:
-#
-#   git checkout v0.0.5
-#
-# Release of python-fpga-interchange library does have to match nextpnr
-# implementation.
-python -m pip install -e .
-```
-
-Clone RapidWright, if not already cloned:
-```
-git clone https://github.com/Xilinx/RapidWright.git
-cd RapidWright
-make update_jars
-```
-
-### Build instructions
-
-Once dependencies are installed/cloned, configure the build system for the FPGA interchange.
-
-From the nextpnr root dir run:
-
-```
-mkdir build
-cd build
-cmake .. --DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=<RapidWright path> -DINTERCHANGE_SCHEMA_PATH=<fpga-interchange-schema path> -DPYTHON_INTERCHANGE_PATH=<python-fpga-interchange path>
-```
-
-To build the xc7a35t architecture, run:
-```
-make chipdb-xc7a35t-bin
-```
-
-To build the example designs run:
-```
-make test-fpga_interchange-wire_arty-dcp
-```
-
-The make targets for the example designs follow the same pattern: `test-fpga_interchange-<test_name>-<output>`, where `output` is the name of the intermediate step of the build which can be:
-
-- `json`: synthesis output
-- `netlist`: logical netlist
-- `phys`: physical netlist
-- `dcp`: design checkpoint
diff --git a/fpga_interchange/examples/boards.cmake b/fpga_interchange/examples/boards.cmake
deleted file mode 100644
index 3639080b7b..0000000000
--- a/fpga_interchange/examples/boards.cmake
+++ /dev/null
@@ -1,50 +0,0 @@
-function(add_board)
-    # ~~~
-    # add_board(
-    #    name <board name>
-    #    device_family <device family>
-    #    device <common device>
-    #    package <package>
-    # )
-    # ~~~
-    #
-    # Generates a board target containing information on the common device and package
-    # of the board.
-    #
-    # Arguments:
-    #   - name: name of the board. E.g. arty
-    #   - device_family: the name of the family this device belongs to.
-    #                    E.g. the xc7a35t device belongs to the xc7 family
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - package: one of the packages available for a given device. E.g. cpg236
-    #
-    # Targets generated:
-    #   - board-<name>
-
-    set(options)
-    set(oneValueArgs name device_family device package)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        add_board
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(name ${add_board_name})
-    set(device_family ${add_board_device_family})
-    set(device ${add_board_device})
-    set(package ${add_board_package})
-
-    add_custom_target(board-${name} DEPENDS device-${device})
-    set_target_properties(
-        board-${name}
-        PROPERTIES
-            DEVICE_FAMILY ${device_family}
-            DEVICE ${device}
-            PACKAGE ${package}
-    )
-endfunction()
diff --git a/fpga_interchange/examples/boards/CMakeLists.txt b/fpga_interchange/examples/boards/CMakeLists.txt
deleted file mode 100644
index ef4a97c5a0..0000000000
--- a/fpga_interchange/examples/boards/CMakeLists.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-add_board(
-    name arty35t
-    device_family xc7
-    device xc7a35t
-    package csg324
-)
-
-add_board(
-    name arty100t
-    device_family xc7
-    device xc7a100t
-    package csg324
-)
-
-add_board(
-    name nexys_video
-    device_family xc7
-    device xc7a200t
-    package sbg484
-)
-
-add_board(
-    name basys3
-    device_family xc7
-    device xc7a35t
-    package cpg236
-)
-
-add_board(
-    name zybo
-    device_family xc7
-    device xc7z010
-    package clg400
-)
-
-# This isn't a real board, all the real boards currently available use the LIFCL-40 but the LIFCL-17 speeds up runtime for testing
-add_board(
-    name lifcl17
-    device_family nexus
-    device LIFCL-17
-    package QFN72
-)
-
-add_board(
-    name lifcl40evn
-    device_family nexus
-    device LIFCL-40
-    package CABGA400
-)
diff --git a/fpga_interchange/examples/chipdb.cmake b/fpga_interchange/examples/chipdb.cmake
deleted file mode 100644
index e820124baa..0000000000
--- a/fpga_interchange/examples/chipdb.cmake
+++ /dev/null
@@ -1,341 +0,0 @@
-include(${family}/examples/chipdb_xilinx.cmake)
-include(${family}/examples/chipdb_nexus.cmake)
-
-function(create_patched_device_db)
-    # ~~~
-    # create_patched_device_db(
-    #    device <common device>
-    #    patch_name <patch_name>
-    #    patch_path <patch_path>
-    #    patch_format <patch_format>
-    #    patch_data <patch_data>
-    #    input_device <input device target>
-    #    output_target <output device target>
-    # )
-    # ~~~
-    #
-    # Generates a patched device database starting from an input device
-    #
-    # If output_target is specified, the variable named as the output_target
-    # parameter value is set to the generated output_device_file target.
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix.
-    #   - patch_name: name of the patch which determines the target name
-    #   - patch_path: patch_path argument for the fpga_interchange.patch call
-    #   - patch_format: patch_format argument for the fpga_interchange.patch call
-    #   - patch_data: path to the patch_data required for the fpga_interchange.patch call
-    #   - input_device: target for the device that needs to be patched
-    #   - output_target: variable name that will hold the output device target for the parent scope
-    #
-    # Targets generated:
-    #   - <patch_name>-<device>-device
-
-    set(options)
-    set(oneValueArgs device patch_name patch_path patch_format patch_data input_device output_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        create_patched_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${create_patched_device_db_device})
-    set(patch_name ${create_patched_device_db_patch_name})
-    set(patch_path ${create_patched_device_db_patch_path})
-    set(patch_format ${create_patched_device_db_patch_format})
-    set(patch_data ${create_patched_device_db_patch_data})
-    set(input_device ${create_patched_device_db_input_device})
-    set(output_target ${create_patched_device_db_output_target})
-
-    get_target_property(input_device_loc ${input_device} LOCATION)
-    set(output_device_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_${patch_name}.device)
-    add_custom_command(
-        OUTPUT ${output_device_file}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.patch
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema device
-                --patch_path ${patch_path}
-                --patch_format ${patch_format}
-                ${input_device_loc}
-                ${patch_data}
-                ${output_device_file}
-        DEPENDS
-            ${patch_data}
-            ${input_device}
-            ${input_device_loc}
-    )
-
-    add_custom_target(${patch_name}-${device}-device DEPENDS ${output_device_file})
-    set_property(TARGET ${patch_name}-${device}-device PROPERTY LOCATION ${output_device_file})
-
-    add_custom_target(${patch_name}-${device}-device-yaml
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.convert
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema device
-                --input_format capnp
-                --output_format yaml
-                ${output_device_file}
-                ${output_device_file}.yaml
-        DEPENDS ${output_device_file})
-
-    if (DEFINED output_target)
-        set(${output_target} ${patch_name}-${device}-device PARENT_SCOPE)
-    endif()
-endfunction()
-
-function(patch_device_with_prim_lib)
-    # ~~~
-    # patch_device_with_prim_lib(
-    #    device <common device>
-    #    yosys_script <yosys script>
-    #    input_device <input device target>
-    #    output_target <output device target>
-    # )
-    # ~~~
-    #
-    # Patches an input device with a primitive library from Yosys
-    #
-    # If output_target is specified, the variable named as the output_target
-    # parameter value is set to the generated output_device_file target.
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix.
-    #   - yosys_script: yosys script to produce cell library
-    #   - input_device: target for the device that needs to be patched
-    #   - output_target: variable name that will hold the output device target for the parent scope
-    #
-    # Targets generated:
-    #   - prims-<device>-device
-
-    set(options)
-    set(oneValueArgs device yosys_script input_device output_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        patch_device_with_prim_lib
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${patch_device_with_prim_lib_device})
-    set(yosys_script ${patch_device_with_prim_lib_yosys_script})
-    set(input_device ${patch_device_with_prim_lib_input_device})
-    set(output_target ${patch_device_with_prim_lib_output_target})
-
-    get_target_property(input_device_loc ${input_device} LOCATION)
-    set(output_device_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.device)
-    set(output_json_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.json)
-
-    add_custom_command(
-        OUTPUT ${output_json_file}
-        COMMAND
-            yosys -p '${yosys_script}\; write_json ${output_json_file}'
-    )
-
-    add_custom_command(
-        OUTPUT ${output_device_file}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.add_prim_lib
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                ${input_device_loc}
-                ${output_json_file}
-                ${output_device_file}
-        DEPENDS
-            ${input_device}
-            ${input_device_loc}
-            ${output_json_file}
-    )
-
-    add_custom_target(prims-${device}-device DEPENDS ${output_device_file})
-    set_property(TARGET prims-${device}-device PROPERTY LOCATION ${output_device_file})
-
-    if (DEFINED output_target)
-        set(${output_target} prims-${device}-device PARENT_SCOPE)
-    endif()
-endfunction()
-
-function(generate_chipdb)
-    # ~~~
-    # generate_chipdb(
-    #    family <family>
-    #    device <common device>
-    #    part <part>
-    #    device_target <device target>
-    #    device_config <device config>
-    #    test_package <test_package>
-    # )
-    # ~~~
-    #
-    # Generates a chipdb BBA file, starting from a device database.
-    #
-    # The chipdb binary file is directly generated to the
-    # <nextpnr-root>/build/fpga_interchange/chipdb/ directory.
-    #
-    # The package argument is only used to run the architecture check target.
-    #
-    # Arguments:
-    #   - family: nextpnr architecture family (e.g. fpga_interchange)
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - part: one among the parts available for a given device
-    #   - device_target: target for the device from which the chipdb is generated
-    #   - device_config: path to the device configYAML file
-    #       This file specifies some nextpnr specific data, such as BEL bucket
-    #       seeds and global BEL names.
-    #   - test_package: package among the ones available for the device. This is used for architecture
-    #                   testing only
-    #
-    # Targets generated:
-    #   - chipdb-${device}-bba
-    #   - chipdb-${device}-bin
-    #   - device-${device}
-    #
-    # The device-${device} target contains properties to get the interchange device as well
-    # as the binary chipdb
-
-    set(options)
-    set(oneValueArgs family device part device_target device_config test_package)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        generate_chipdb
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(family ${generate_chipdb_family})
-    set(device ${generate_chipdb_device})
-    set(part ${generate_chipdb_part})
-    set(device_target ${generate_chipdb_device_target})
-    set(device_config ${generate_chipdb_device_config})
-    set(test_package ${generate_chipdb_test_package})
-
-    get_target_property(device_loc ${device_target} LOCATION)
-    set(chipdb_bba ${CMAKE_CURRENT_BINARY_DIR}/chipdb.bba)
-    add_custom_command(
-        OUTPUT ${chipdb_bba}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.nextpnr_emit
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --output_dir ${CMAKE_CURRENT_BINARY_DIR}
-                --device_config ${device_config}
-                --device ${device_loc}
-        DEPENDS
-            ${device_config}
-            ${device_target}
-            ${device_loc}
-    )
-
-    add_custom_target(chipdb-${device}-bba DEPENDS ${chipdb_bba})
-
-    set(chipdb_bin ${chipdb_dir}/chipdb-${device}.bin)
-    add_custom_command(
-        OUTPUT ${chipdb_bin}
-        COMMAND
-            bbasm -l ${chipdb_bba} ${chipdb_bin}
-        DEPENDS
-            chipdb-${device}-bba
-            ${chipdb_bba}
-            bbasm
-    )
-
-    add_custom_target(chipdb-${device}-bin DEPENDS ${chipdb_bin})
-
-    # Setting device target properties
-    add_custom_target(device-${device})
-    set_target_properties(
-        device-${device}
-        PROPERTIES
-            DEVICE_LOC ${device_loc}
-            DEVICE_TARGET ${device_target}
-            CHIPDB_BIN_LOC ${chipdb_bin}
-            CHIPDB_BIN_TARGET chipdb-${device}-bin
-    )
-
-    # Generate architecture check target
-    add_custom_target(
-        chipdb-${device}-bin-check
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin}
-                --package ${test_package}
-                --test
-        DEPENDS
-            ${chipdb_bin}
-            chipdb-${device}-bin
-    )
-
-    add_custom_target(
-        chipdb-${device}-bin-check-verbose
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin}
-                --package ${test_package}
-                --test --verbose
-        DEPENDS
-            ${chipdb_bin}
-            chipdb-${device}-bin
-    )
-
-    add_custom_target(
-        chipdb-${device}-bin-check-verbose2
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin}
-                --package ${test_package}
-                --test --debug
-        DEPENDS
-            ${chipdb_bin}
-            chipdb-${device}-bin
-    )
-
-    add_custom_target(
-        chipdb-${device}-bin-check-debug
-        COMMAND gdb --args
-            $<TARGET_FILE:nextpnr-fpga_interchange>
-                --chipdb ${chipdb_bin}
-                --package ${test_package}
-                --test
-        DEPENDS
-            ${chipdb_bin}
-            chipdb-${device}-bin
-    )
-
-    add_custom_target(
-        chipdb-${device}-bin-check-test-data
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin}
-                --package ${test_package}
-                --run ${PROJECT_SOURCE_DIR}/python/check_arch_api.py
-        DEPENDS
-            ${chipdb_bin}
-            chipdb-${device}-bin
-            ${test_data_binary}
-        WORKING_DIRECTORY
-            ${CMAKE_CURRENT_SOURCE_DIR}
-    )
-
-    add_dependencies(all-${family}-archcheck-tests chipdb-${device}-bin-check-test-data chipdb-${device}-bin-check)
-
-    # All tests targets for this device are added to this target
-    add_custom_target(
-        all-${device}-tests
-        DEPENDS
-            chipdb-${device}-bin-check-test-data
-            chipdb-${device}-bin-check
-    )
-endfunction()
-
diff --git a/fpga_interchange/examples/chipdb_nexus.cmake b/fpga_interchange/examples/chipdb_nexus.cmake
deleted file mode 100644
index 4ea180c568..0000000000
--- a/fpga_interchange/examples/chipdb_nexus.cmake
+++ /dev/null
@@ -1,101 +0,0 @@
-function(create_prjoxide_device_db)
-    # ~~~
-    # create_prjoxide_device_db(
-    #    device <common device>
-    #    output_target <output device target>
-    # )
-    # ~~~
-    #
-    # Generates a device database from Project Oxide
-    #
-    # If output_target is specified, the output_target_name variable
-    # is set to the generated output_device_file target.
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. LIFCL-17
-    #   - output_target: variable name that will hold the output device target for the parent scope
-    #
-    # Targets generated:
-    #   - prjoxide-<device>-device
-    set(options)
-    set(oneValueArgs device output_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        create_prjoxide_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${create_prjoxide_device_db_device})
-    set(output_target ${create_prjoxide_device_db_output_target})
-    set(prjoxide_device_db ${CMAKE_CURRENT_BINARY_DIR}/${device}.device)
-    add_custom_command(
-        OUTPUT ${prjoxide_device_db}
-        COMMAND
-            ${PRJOXIDE_PREFIX}/bin/prjoxide
-            interchange-export
-            ${device}
-            ${prjoxide_device_db}
-        DEPENDS
-            ${PRJOXIDE_PREFIX}/bin/prjoxide
-    )
-
-    add_custom_target(prjoxide-${device}-device DEPENDS ${prjoxide_device_db})
-    set_property(TARGET prjoxide-${device}-device PROPERTY LOCATION ${prjoxide_device_db})
-
-    if (DEFINED output_target)
-        set(${output_target} prjoxide-${device}-device PARENT_SCOPE)
-    endif()
-
-endfunction()
-
-function(generate_nexus_device_db)
-    # ~~~
-    # generate_nexus_device_db(
-    #    device <common device>
-    #    device_target <variable name for device target>
-    # )
-    # ~~~
-    #
-    # Generates a chipdb BBA file, starting from a Project Oxide device database.
-    # Patches applied:
-    #   - primitive library from Yosys
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. LIFCL-17
-    #   - device_target: variable name that will hold the output device target for the parent scope
-    set(options)
-    set(oneValueArgs device device_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        generate_nexus_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${generate_nexus_device_db_device})
-    set(device_target ${generate_nexus_device_db_device_target})
-
-    create_prjoxide_device_db(
-        device ${device}
-        output_target prjoxide_device
-    )
-
-    # Add primitive library
-    patch_device_with_prim_lib(
-        device ${device}
-        yosys_script synth_nexus
-        input_device ${prjoxide_device}
-        output_target prjoxide_prims_device
-    )
-
-    if(DEFINED device_target)
-        set(${device_target} ${prjoxide_prims_device} PARENT_SCOPE)
-    endif()
-endfunction()
diff --git a/fpga_interchange/examples/chipdb_xilinx.cmake b/fpga_interchange/examples/chipdb_xilinx.cmake
deleted file mode 100644
index 62e6b9eda6..0000000000
--- a/fpga_interchange/examples/chipdb_xilinx.cmake
+++ /dev/null
@@ -1,138 +0,0 @@
-function(create_rapidwright_device_db)
-    # ~~~
-    # create_rapidwright_device_db(
-    #    device <common device>
-    #    part <part>
-    #    output_target <output device target>
-    # )
-    # ~~~
-    #
-    # Generates a device database from RapidWright
-    #
-    # If output_target is specified, the output_target_name variable
-    # is set to the generated output_device_file target.
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - part: one among the parts available for a given device
-    #   - output_target: variable name that will hold the output device target for the parent scope
-    #
-    # Targets generated:
-    #   - rapidwright-<device>-device
-
-    set(options)
-    set(oneValueArgs device part output_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        create_rapidwright_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${create_rapidwright_device_db_device})
-    set(part ${create_rapidwright_device_db_part})
-    set(output_target ${create_rapidwright_device_db_output_target})
-    set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
-    add_custom_command(
-        OUTPUT ${rapidwright_device_db}
-        COMMAND
-            RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
-            ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
-            com.xilinx.rapidwright.interchange.DeviceResourcesExample
-            ${part}
-        DEPENDS
-            ${INVOKE_RAPIDWRIGHT}
-    )
-
-    add_custom_target(rapidwright-${device}-device DEPENDS ${rapidwright_device_db})
-    set_property(TARGET rapidwright-${device}-device PROPERTY LOCATION ${rapidwright_device_db})
-
-    add_custom_target(rapidwright-${device}-device-yaml
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.convert
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema device
-                --input_format capnp
-                --output_format yaml
-                ${rapidwright_device_db}
-                ${rapidwright_device_db}.yaml
-        DEPENDS ${rapidwright_device_db})
-
-    if (DEFINED output_target)
-        set(${output_target} rapidwright-${device}-device PARENT_SCOPE)
-    endif()
-endfunction()
-
-
-function(generate_xc7_device_db)
-    # ~~~
-    # generate_xc7_device_db(
-    #    device <common device>
-    #    part <part>
-    #    device_target <variable name for device target>
-    # )
-    # ~~~
-    #
-    # Generates a chipdb BBA file, starting from a RapidWright device database which is then patched.
-    # Patches applied:
-    #   - constraints patch
-    #   - luts patch
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - part: one among the parts available for a given device
-    #   - device_target: variable name that will hold the output device target for the parent scope
-
-    set(options)
-    set(oneValueArgs device part device_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        create_rapidwright_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${create_rapidwright_device_db_device})
-    set(part ${create_rapidwright_device_db_part})
-    set(device_target ${create_rapidwright_device_db_device_target})
-
-    create_rapidwright_device_db(
-        device ${device}
-        part ${part}
-        output_target rapidwright_device
-    )
-
-    # Generate constraints patch
-    create_patched_device_db(
-        device ${device}
-        patch_name constraints
-        patch_path constraints
-        patch_format yaml
-        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
-        input_device ${rapidwright_device}
-        output_target constraints_device
-    )
-
-    # Generate lut constraints patch
-    create_patched_device_db(
-        device ${device}
-        patch_name constraints-luts
-        patch_path lutDefinitions
-        patch_format yaml
-        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
-        input_device ${constraints_device}
-        output_target constraints_luts_device
-    )
-
-    if(DEFINED device_target)
-        set(${device_target} ${constraints_luts_device} PARENT_SCOPE)
-    endif()
-endfunction()
diff --git a/fpga_interchange/examples/devices/CMakeLists.txt b/fpga_interchange/examples/devices/CMakeLists.txt
deleted file mode 100644
index 1cf8ad437b..0000000000
--- a/fpga_interchange/examples/devices/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# Artix-7 devices
-add_subdirectory(xc7a35t)
-add_subdirectory(xc7a100t)
-add_subdirectory(xc7a200t)
-
-# Zynq-7 devices
-add_subdirectory(xc7z010)
-
-# Nexus devices
-add_subdirectory(LIFCL-17)
-add_subdirectory(LIFCL-40)
diff --git a/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt b/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt
deleted file mode 100644
index 572ff200ea..0000000000
--- a/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-generate_nexus_device_db(
-    device LIFCL-17
-    device_target lifcl17_target
-)
-
-generate_chipdb(
-    family ${family}
-    device LIFCL-17
-    part LIFCL-17-7SG72C
-    device_target ${lifcl17_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/nexus_device_config.yaml
-    test_package QFN72
-)
diff --git a/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml b/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml
deleted file mode 100644
index c4787eba26..0000000000
--- a/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-pip_test:
-    - src_wire: R3C3_PLC.PLC/JDI0_SLICEA
-      dst_wire: R3C3/JF0
-bel_pin_test:
-    - bel: R7C3_PLC.PLC/SLICEA_LUT0
-      pin: D
-      wire: R7C3_PLC.PLC/JD0_SLICEA
-
diff --git a/fpga_interchange/examples/devices/LIFCL-40/CMakeLists.txt b/fpga_interchange/examples/devices/LIFCL-40/CMakeLists.txt
deleted file mode 100644
index d631011695..0000000000
--- a/fpga_interchange/examples/devices/LIFCL-40/CMakeLists.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-generate_nexus_device_db(
-    device LIFCL-40
-    device_target lifcl40_target
-)
-
-generate_chipdb(
-    family ${family}
-    device LIFCL-40
-    part LIFCL-40-9BG400C
-    device_target ${lifcl40_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/nexus_device_config.yaml
-    test_package CABGA400
-)
diff --git a/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml b/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml
deleted file mode 100644
index c4787eba26..0000000000
--- a/fpga_interchange/examples/devices/LIFCL-40/test_data.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-pip_test:
-    - src_wire: R3C3_PLC.PLC/JDI0_SLICEA
-      dst_wire: R3C3/JF0
-bel_pin_test:
-    - bel: R7C3_PLC.PLC/SLICEA_LUT0
-      pin: D
-      wire: R7C3_PLC.PLC/JD0_SLICEA
-
diff --git a/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt
deleted file mode 100644
index 955ee8ca0c..0000000000
--- a/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-generate_xc7_device_db(
-    device xc7a100t
-    part xc7a100tcsg324-1
-    device_target xc7a100t_target
-)
-
-generate_chipdb(
-    family ${family}
-    device xc7a100t
-    part xc7a100tcsg324-1
-    device_target ${xc7a100t_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
-    test_package csg324
-)
diff --git a/fpga_interchange/examples/devices/xc7a100t/test_data.yaml b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
deleted file mode 100644
index 268d180a27..0000000000
--- a/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-pip_test:
-    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
-      dst_wire: SLICE_X15Y93.SLICEL/D3
-pip_chain_test:
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
-        - INT_R_X3Y145/GND_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
-        - INT_R_X3Y145/VCC_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
-bel_pin_test:
-    - bel: SLICE_X15Y93.SLICEL/D6LUT
-      pin: A3
-      wire: SLICE_X15Y93.SLICEL/D3
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
-      pin: G
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
-      pin: P
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt
deleted file mode 100644
index b77d77bbbc..0000000000
--- a/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-generate_xc7_device_db(
-    device xc7a200t
-    part xc7a200tsbg484-1
-    device_target xc7a200t_target
-)
-
-generate_chipdb(
-    family ${family}
-    device xc7a200t
-    part xc7a200tsbg484-1
-    device_target ${xc7a200t_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
-    test_package sbg484
-)
diff --git a/fpga_interchange/examples/devices/xc7a200t/test_data.yaml b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
deleted file mode 100644
index 268d180a27..0000000000
--- a/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-pip_test:
-    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
-      dst_wire: SLICE_X15Y93.SLICEL/D3
-pip_chain_test:
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
-        - INT_R_X3Y145/GND_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
-        - INT_R_X3Y145/VCC_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
-bel_pin_test:
-    - bel: SLICE_X15Y93.SLICEL/D6LUT
-      pin: A3
-      wire: SLICE_X15Y93.SLICEL/D3
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
-      pin: G
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
-      pin: P
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
deleted file mode 100644
index 636440c451..0000000000
--- a/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-generate_xc7_device_db(
-    device xc7a35t
-    part xc7a35tcsg324-1
-    device_target xc7a35t_target
-)
-
-generate_chipdb(
-    family ${family}
-    device xc7a35t
-    part xc7a35tcsg324-1
-    device_target ${xc7a35t_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
-    test_package csg324
-)
diff --git a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
deleted file mode 100644
index 88c6fedaed..0000000000
--- a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
+++ /dev/null
@@ -1,40 +0,0 @@
-pip_test:
-    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
-      dst_wire: SLICE_X15Y93.SLICEL/D3
-pip_chain_test:
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
-        - INT_R_X3Y145/GND_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
-        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
-        - INT_R_X3Y145/VCC_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
-        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
-bel_pin_test:
-    - bel: SLICE_X15Y93.SLICEL/D6LUT
-      pin: A3
-      wire: SLICE_X15Y93.SLICEL/D3
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
-      pin: G
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
-      pin: P
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-    - bel: SLICE_X1Y19.SLICEL/SRUSEDGND
-      pin: "0"
-      wire: SLICE_X1Y19.SLICEL/SRUSEDGND_HARD0
-      type: PORT_OUT
diff --git a/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt b/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt
deleted file mode 100644
index ec6a772871..0000000000
--- a/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-generate_xc7_device_db(
-    device xc7z010
-    part xc7z010clg400-1
-    device_target xc7z010_target
-)
-
-generate_chipdb(
-    family ${family}
-    device xc7z010
-    part xc7z010clg400-1
-    device_target ${xc7z010_target}
-    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
-    test_package clg400
-)
diff --git a/fpga_interchange/examples/devices/xc7z010/test_data.yaml b/fpga_interchange/examples/devices/xc7z010/test_data.yaml
deleted file mode 100644
index dbc95845cb..0000000000
--- a/fpga_interchange/examples/devices/xc7z010/test_data.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-pip_test:
-    - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3
-      dst_wire: SLICE_X11Y69.SLICEL/D3
-pip_chain_test:
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE
-        - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0
-        - INT_L_X8Y69/GND_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE
-        - TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1
-        - INT_L_X8Y69/VCC_WIRE
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-        - $CONSTANTS_X0Y0/$VCC_NODE
-        - SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE
-        - SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1
-    - wires:
-        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-        - $CONSTANTS_X0Y0/$GND_NODE
-        - SLICE_X11Y69.SLICEL/$GND_SITE_WIRE
-        - SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0
-bel_pin_test:
-    - bel: SLICE_X14Y63.SLICEL/D6LUT
-      pin: A3
-      wire: SLICE_X14Y63.SLICEL/D3
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
-      pin: G
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
-    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
-      pin: P
-      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/remap_nexus.v b/fpga_interchange/examples/remap_nexus.v
deleted file mode 100644
index 861ce7794d..0000000000
--- a/fpga_interchange/examples/remap_nexus.v
+++ /dev/null
@@ -1,180 +0,0 @@
-// Inverter support is still a TODO
-module INV(input A, output Z);
-	LUT4 #(.INIT("0x5555")) _TECHMAP_REPLACE_ (.A(A), .B(1'b1), .C(1'b1), .D(1'b1), .Z(Z));
-endmodule
-
-module PDPSC16K (...);
-	parameter DATA_WIDTH_W = "X36";
-	parameter DATA_WIDTH_R = "X36";
-	parameter OUTREG = "BYPASSED";
-	parameter RESETMODE = "SYNC";
-	parameter GSR = "ENABLED";
-	parameter ECC = "DISABLED";
-	parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-	parameter CSDECODE_W = "000";
-	parameter CSDECODE_R = "000";
-	parameter ASYNC_RST_RELEASE = "SYNC";
-	parameter INIT_DATA = "STATIC";
-	input [35:0] DI;
-	input [13:0] ADW;
-	input [13:0] ADR;
-	input CLK;
-	input CER;
-	input CEW;
-	input [2:0] CSW;
-	input [2:0] CSR;
-	input RST;
-	output [35:0] DO;
-	output ONEBITERR;
-	output TWOBITERR;
-
-	// TODO: this should really be a macro or otherwise dealt with more automatically
-	PDPSC16K_MODE #(
-		.DATA_WIDTH_W(DATA_WIDTH_W),
-		.DATA_WIDTH_R(DATA_WIDTH_R),
-		.OUTREG(OUTREG),
-		.GSR(GSR),
-		.ECC(ECC),
-		.CSDECODE_W(CSDECODE_W),
-		.CSDECODE_R(CSDECODE_R),
-		.ASYNC_RST_RELEASE(ASYNC_RST_RELEASE),
-		.INITVAL_00(INITVAL_00),
-		.INITVAL_01(INITVAL_01),
-		.INITVAL_02(INITVAL_02),
-		.INITVAL_03(INITVAL_03),
-		.INITVAL_04(INITVAL_04),
-		.INITVAL_05(INITVAL_05),
-		.INITVAL_06(INITVAL_06),
-		.INITVAL_07(INITVAL_07),
-		.INITVAL_08(INITVAL_08),
-		.INITVAL_09(INITVAL_09),
-		.INITVAL_0A(INITVAL_0A),
-		.INITVAL_0B(INITVAL_0B),
-		.INITVAL_0C(INITVAL_0C),
-		.INITVAL_0D(INITVAL_0D),
-		.INITVAL_0E(INITVAL_0E),
-		.INITVAL_0F(INITVAL_0F),
-		.INITVAL_10(INITVAL_10),
-		.INITVAL_11(INITVAL_11),
-		.INITVAL_12(INITVAL_12),
-		.INITVAL_13(INITVAL_13),
-		.INITVAL_14(INITVAL_14),
-		.INITVAL_15(INITVAL_15),
-		.INITVAL_16(INITVAL_16),
-		.INITVAL_17(INITVAL_17),
-		.INITVAL_18(INITVAL_18),
-		.INITVAL_19(INITVAL_19),
-		.INITVAL_1A(INITVAL_1A),
-		.INITVAL_1B(INITVAL_1B),
-		.INITVAL_1C(INITVAL_1C),
-		.INITVAL_1D(INITVAL_1D),
-		.INITVAL_1E(INITVAL_1E),
-		.INITVAL_1F(INITVAL_1F),
-		.INITVAL_20(INITVAL_20),
-		.INITVAL_21(INITVAL_21),
-		.INITVAL_22(INITVAL_22),
-		.INITVAL_23(INITVAL_23),
-		.INITVAL_24(INITVAL_24),
-		.INITVAL_25(INITVAL_25),
-		.INITVAL_26(INITVAL_26),
-		.INITVAL_27(INITVAL_27),
-		.INITVAL_28(INITVAL_28),
-		.INITVAL_29(INITVAL_29),
-		.INITVAL_2A(INITVAL_2A),
-		.INITVAL_2B(INITVAL_2B),
-		.INITVAL_2C(INITVAL_2C),
-		.INITVAL_2D(INITVAL_2D),
-		.INITVAL_2E(INITVAL_2E),
-		.INITVAL_2F(INITVAL_2F),
-		.INITVAL_30(INITVAL_30),
-		.INITVAL_31(INITVAL_31),
-		.INITVAL_32(INITVAL_32),
-		.INITVAL_33(INITVAL_33),
-		.INITVAL_34(INITVAL_34),
-		.INITVAL_35(INITVAL_35),
-		.INITVAL_36(INITVAL_36),
-		.INITVAL_37(INITVAL_37),
-		.INITVAL_38(INITVAL_38),
-		.INITVAL_39(INITVAL_39),
-		.INITVAL_3A(INITVAL_3A),
-		.INITVAL_3B(INITVAL_3B),
-		.INITVAL_3C(INITVAL_3C),
-		.INITVAL_3D(INITVAL_3D),
-		.INITVAL_3E(INITVAL_3E),
-		.INITVAL_3F(INITVAL_3F),
-		.INIT_DATA(INIT_DATA)
-	) _TECHMAP_REPLACE_ (
-		.CLK(CLK), .CER(CER), .CEW(CEW), .RST(RST),
-		.CSW0(CSW[0]), .CSW1(CSW[1]), .CSW2(CSW[2]),
-		.CSR0(CSR[0]), .CSR1(CSR[1]), .CSR2(CSR[2]),
-		.DI0(DI[0]), .DI1(DI[1]), .DI2(DI[2]), .DI3(DI[3]), .DI4(DI[4]), .DI5(DI[5]), .DI6(DI[6]), .DI7(DI[7]), .DI8(DI[8]), .DI9(DI[9]), .DI10(DI[10]), .DI11(DI[11]), .DI12(DI[12]), .DI13(DI[13]), .DI14(DI[14]), .DI15(DI[15]), .DI16(DI[16]), .DI17(DI[17]), .DI18(DI[18]), .DI19(DI[19]), .DI20(DI[20]), .DI21(DI[21]), .DI22(DI[22]), .DI23(DI[23]), .DI24(DI[24]), .DI25(DI[25]), .DI26(DI[26]), .DI27(DI[27]), .DI28(DI[28]), .DI29(DI[29]), .DI30(DI[30]), .DI31(DI[31]), .DI32(DI[32]), .DI33(DI[33]), .DI34(DI[34]), .DI35(DI[35]),
-		.ADW0(ADW[0]), .ADW1(ADW[1]), .ADW2(ADW[2]), .ADW3(ADW[3]), .ADW4(ADW[4]), .ADW5(ADW[5]), .ADW6(ADW[6]), .ADW7(ADW[7]), .ADW8(ADW[8]), .ADW9(ADW[9]), .ADW10(ADW[10]), .ADW11(ADW[11]), .ADW12(ADW[12]), .ADW13(ADW[13]),
-		.ADR0(ADR[0]), .ADR1(ADR[1]), .ADR2(ADR[2]), .ADR3(ADR[3]), .ADR4(ADR[4]), .ADR5(ADR[5]), .ADR6(ADR[6]), .ADR7(ADR[7]), .ADR8(ADR[8]), .ADR9(ADR[9]), .ADR10(ADR[10]), .ADR11(ADR[11]), .ADR12(ADR[12]), .ADR13(ADR[13]),
-		.DO0(DO[0]), .DO1(DO[1]), .DO2(DO[2]), .DO3(DO[3]), .DO4(DO[4]), .DO5(DO[5]), .DO6(DO[6]), .DO7(DO[7]), .DO8(DO[8]), .DO9(DO[9]), .DO10(DO[10]), .DO11(DO[11]), .DO12(DO[12]), .DO13(DO[13]), .DO14(DO[14]), .DO15(DO[15]), .DO16(DO[16]), .DO17(DO[17]), .DO18(DO[18]), .DO19(DO[19]), .DO20(DO[20]), .DO21(DO[21]), .DO22(DO[22]), .DO23(DO[23]), .DO24(DO[24]), .DO25(DO[25]), .DO26(DO[26]), .DO27(DO[27]), .DO28(DO[28]), .DO29(DO[29]), .DO30(DO[30]), .DO31(DO[31]), .DO32(DO[32]), .DO33(DO[33]), .DO34(DO[34]), .DO35(DO[35]),
-		.ONEBITERR(ONEBITERR), .TWOBITERR(TWOBITERR),
-	);
-
-endmodule
diff --git a/fpga_interchange/examples/remap_xilinx.v b/fpga_interchange/examples/remap_xilinx.v
deleted file mode 100644
index 6dfc0b4aac..0000000000
--- a/fpga_interchange/examples/remap_xilinx.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module INV(input I, output O);
-
-LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
-
-endmodule
-
-module BUF(input I, output O);
-
-LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
-
-endmodule
diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake
deleted file mode 100644
index b568c5df7b..0000000000
--- a/fpga_interchange/examples/tests.cmake
+++ /dev/null
@@ -1,405 +0,0 @@
-function(add_interchange_test)
-    # ~~~
-    # add_interchange_test(
-    #    name <name>
-    #    family <family>
-    #    device <common device>
-    #    package <package>
-    #    tcl <tcl>
-    #    xdc <xdc>
-    #    sources <sources list>
-    #    [top <top name>]
-    #    [techmap <techmap file>]
-    #    [output_fasm]
-    #    [device_family <device family>]
-    # )
-    #
-    # Generates targets to run desired tests
-    #
-    # Arguments:
-    #   - name: test name. This must be unique and no other tests with the same
-    #           name should exist
-    #   - family: nextpnr architecture family (e.g. fpga_interchange)
-    #   - device_family: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - package: package among the ones available for the device
-    #   - tcl: tcl script used for synthesis
-    #   - xdc: constraints file used in the physical netlist generation step
-    #   - sources: list of HDL sources
-    #   - top (optional): name of the top level module.
-    #                     If not provided, "top" is assigned as top level module
-    #   - techmap (optional): techmap file used during synthesis
-    #   - output_fasm (optional): generates a fasm output
-    #   - device_family (optional): this information is used during FASM generation, therfore it is
-    #                               required only if the `output_fasm` option is enabled
-    #
-    # Targets generated:
-    #   - test-fpga_interchange-<name>-json     : synthesis output
-    #   - test-fpga_interchange-<name>-netlist  : interchange logical netlist
-    #   - test-fpga_interchange-<name>-phys     : interchange physical netlist
-    #   - test-fpga_interchange-<name>-dcp     : design checkpoint with RapidWright
-
-    set(options skip_dcp output_fasm)
-    set(oneValueArgs name family device package tcl xdc top techmap device_family)
-    set(multiValueArgs sources)
-
-    cmake_parse_arguments(
-        add_interchange_test
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(name ${add_interchange_test_name})
-    set(family ${add_interchange_test_family})
-    set(device ${add_interchange_test_device})
-    set(package ${add_interchange_test_package})
-    set(skip_dcp ${add_interchange_test_skip_dcp})
-    set(output_fasm ${add_interchange_test_output_fasm})
-    set(top ${add_interchange_test_top})
-    set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
-    set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
-    set(techmap ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_techmap})
-    set(device_family ${add_interchange_test_device_family})
-
-    set(sources)
-    foreach(source ${add_interchange_test_sources})
-        list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source})
-    endforeach()
-
-    if (NOT DEFINED top)
-        # Setting default top value
-        set(top "top")
-    endif()
-
-    # Synthesis
-    set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
-    set(synth_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.json.log)
-    add_custom_command(
-        OUTPUT ${synth_json}
-        COMMAND ${CMAKE_COMMAND} -E env
-            SOURCES="${sources}"
-            OUT_JSON=${synth_json}
-            TECHMAP=${techmap}
-            yosys -c ${tcl} -l ${synth_log}
-        DEPENDS ${sources} ${techmap} ${tcl}
-    )
-
-    add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
-
-    # Logical Netlist
-    get_property(device_target TARGET device-${device} PROPERTY DEVICE_TARGET)
-    get_property(device_loc TARGET device-${device} PROPERTY DEVICE_LOC)
-
-    set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist)
-    add_custom_command(
-        OUTPUT ${netlist}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.yosys_json
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --device ${device_loc}
-                --top ${top}
-                ${synth_json}
-                ${netlist}
-        DEPENDS
-            ${synth_json}
-            ${device_target}
-            ${device_loc}
-    )
-
-    add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist})
-
-    # Logical Netlist YAML
-    set(netlist_yaml ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist.yaml)
-    add_custom_command(
-        OUTPUT ${netlist_yaml}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.convert
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema logical
-                --input_format capnp
-                --output_format yaml
-                ${netlist}
-                ${netlist_yaml}
-        DEPENDS
-            ${netlist}
-    )
-
-    add_custom_target(test-${family}-${name}-netlist-yaml DEPENDS ${netlist_yaml})
-
-    # Physical Netlist
-    get_property(chipdb_bin_target TARGET device-${device} PROPERTY CHIPDB_BIN_TARGET)
-    get_property(chipdb_bin_loc TARGET device-${device} PROPERTY CHIPDB_BIN_LOC)
-
-    set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys)
-    set(phys_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.log)
-    add_custom_command(
-        OUTPUT ${phys}
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin_loc}
-                --xdc ${xdc}
-                --netlist ${netlist}
-                --phys ${phys}
-                --package ${package}
-                --log ${phys_log}
-        DEPENDS
-            nextpnr-fpga_interchange
-            ${netlist}
-            ${xdc}
-            ${chipdb_bin_target}
-            ${chipdb_bin_loc}
-    )
-
-    set(phys_verbose_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.verbose.log)
-    add_custom_target(
-        test-${family}-${name}-phys-verbose
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin_loc}
-                --xdc ${xdc}
-                --netlist ${netlist}
-                --phys ${phys}
-                --package ${package}
-                --verbose
-                --log ${phys_verbose_log}
-        DEPENDS
-            ${netlist}
-            ${xdc}
-            ${chipdb_bin_target}
-            ${chipdb_bin_loc}
-    )
-
-    add_custom_target(
-        test-${family}-${name}-phys-verbose2
-        COMMAND
-            nextpnr-fpga_interchange
-                --chipdb ${chipdb_bin_loc}
-                --xdc ${xdc}
-                --netlist ${netlist}
-                --phys ${phys}
-                --package ${package}
-                --debug
-        DEPENDS
-            ${netlist}
-            ${xdc}
-            ${chipdb_bin_target}
-            ${chipdb_bin_loc}
-    )
-
-    add_custom_target(
-        test-${family}-${name}-phys-debug
-        COMMAND gdb --args
-            $<TARGET_FILE:nextpnr-fpga_interchange>
-                --chipdb ${chipdb_bin_loc}
-                --xdc ${xdc}
-                --netlist ${netlist}
-                --phys ${phys}
-                --package ${package}
-        DEPENDS
-            ${netlist}
-            ${xdc}
-            ${chipdb_bin_target}
-            ${chipdb_bin_loc}
-    )
-
-    add_custom_target(
-        test-${family}-${name}-phys-valgrind
-        COMMAND
-            PYTHONMALLOC=malloc valgrind
-            $<TARGET_FILE:nextpnr-fpga_interchange>
-                --chipdb ${chipdb_bin_loc}
-                --xdc ${xdc}
-                --netlist ${netlist}
-                --phys ${phys}
-                --package ${package}
-        DEPENDS
-            ${netlist}
-            ${xdc}
-            ${chipdb_bin_target}
-            ${chipdb_bin_loc}
-    )
-
-    if(PROFILER)
-        add_custom_target(
-            test-${family}-${name}-phys-profile
-            COMMAND CPUPROFILE=${name}.prof
-                    $<TARGET_FILE:nextpnr-fpga_interchange>
-                    --chipdb ${chipdb_bin_loc}
-                    --xdc ${xdc}
-                    --netlist ${netlist}
-                    --phys ${phys}
-                    --package ${package}
-            DEPENDS
-                ${netlist}
-                ${xdc}
-                ${chipdb_bin_target}
-                ${chipdb_bin_loc}
-        )
-    endif()
-
-    add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
-
-    # Physical Netlist YAML
-    set(phys_yaml ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.yaml)
-    add_custom_command(
-        OUTPUT ${phys_yaml}
-        COMMAND
-            ${Python3_EXECUTABLE} -mfpga_interchange.convert
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema physical
-                --input_format capnp
-                --output_format yaml
-                ${phys}
-                ${phys_yaml}
-        DEPENDS
-            ${phys}
-    )
-
-    add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml})
-
-    set(last_target "")
-    if(skip_dcp)
-        set(last_target test-${family}-${name}-phys)
-    else()
-        set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
-        add_custom_command(
-            OUTPUT ${dcp}
-            COMMAND
-                RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
-                ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
-                com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
-                ${netlist} ${phys} ${xdc} ${dcp}
-            DEPENDS
-                ${INVOKE_RAPIDWRIGHT}
-                ${phys}
-                ${netlist}
-        )
-
-        add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
-        set(last_target test-${family}-${name}-dcp)
-    endif()
-
-    add_dependencies(all-${device}-tests ${last_target})
-    add_dependencies(all-${family}-tests ${last_target})
-
-    if(output_fasm)
-        if(NOT DEFINED device_family)
-            message(FATAL_ERROR "If FASM output is enabled, the device family must be provided as well!")
-        endif()
-
-        # Output FASM target
-        set(fasm ${CMAKE_CURRENT_BINARY_DIR}/${name}.fasm)
-        add_custom_command(
-            OUTPUT ${fasm}
-            COMMAND
-                ${Python3_EXECUTABLE} -mfpga_interchange.fasm_generator
-                    --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                    --family ${device_family}
-                    ${device_loc}
-                    ${netlist}
-                    ${phys}
-                    ${fasm}
-            DEPENDS
-                ${device_target}
-                ${netlist}
-                ${phys}
-        )
-
-        add_custom_target(test-${family}-${name}-fasm DEPENDS ${fasm} ${last_target})
-        add_dependencies(all-${device}-tests test-${family}-${name}-fasm)
-        add_dependencies(all-${family}-tests test-${family}-${name}-fasm)
-    endif()
-endfunction()
-
-function(add_interchange_group_test)
-    # ~~~
-    # add_interchange_group_test(
-    #    name <name>
-    #    family <family>
-    #    board_list <boards>
-    #    xdc_list <xdc>
-    #    tcl <tcl>
-    #    sources <sources list>
-    #    [top <top name>]
-    #    [techmap <techmap file>]
-    #    [skip_dcp]
-    # )
-    #
-    # Generates targets to run desired tests over multiple devices.
-    #
-    # Arguments:
-    #   - name: base test name. The real test name will be <name>_<board>
-    #   - family: nextpnr architecture family (e.g. fpga_interchange)
-    #   - board_list: list of boards, one for each test
-    #   - tcl: tcl script used for synthesis
-    #   - sources: list of HDL sources
-    #   - top (optional): name of the top level module.
-    #                     If not provided, "top" is assigned as top level module
-    #   - techmap (optional): techmap file used during synthesis
-    #
-    # This function internally calls add_interchange_test to generate the various tests.
-    #
-    # Note: it is assumed that there exists an XDC file for each board, with the following naming
-    #       convention: <board>.xdc
-
-    set(options output_fasm skip_dcp)
-    set(oneValueArgs name family tcl top techmap)
-    set(multiValueArgs sources board_list)
-
-    cmake_parse_arguments(
-        add_interchange_group_test
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(name ${add_interchange_group_test_name})
-    set(family ${add_interchange_group_test_family})
-    set(top ${add_interchange_group_test_top})
-    set(tcl ${add_interchange_group_test_tcl})
-    set(techmap ${add_interchange_group_test_techmap})
-    set(sources ${add_interchange_group_test_sources})
-    set(output_fasm ${add_interchange_group_test_output_fasm})
-    set(skip_dcp ${add_interchange_group_test_skip_dcp})
-
-    set(output_fasm_arg "")
-    if(output_fasm)
-        set(output_fasm_arg "output_fasm")
-    endif()
-
-    set(skip_dcp_arg "")
-    if(skip_dcp)
-        set(skip_dcp_arg "skip_dcp")
-    endif()
-
-    if (NOT DEFINED top)
-        # Setting default top value
-        set(top "top")
-    endif()
-
-    foreach(board ${add_interchange_group_test_board_list})
-        get_property(device_family TARGET board-${board} PROPERTY DEVICE_FAMILY)
-        get_property(device TARGET board-${board} PROPERTY DEVICE)
-        get_property(package TARGET board-${board} PROPERTY PACKAGE)
-
-        add_interchange_test(
-            name ${name}_${board}
-            family ${family}
-            device ${device}
-            device_family ${device_family}
-            package ${package}
-            tcl ${tcl}
-            xdc ${board}.xdc
-            sources ${sources}
-            top ${top}
-            techmap ${techmap}
-            ${output_fasm_arg}
-            ${skip_dcp_arg}
-        )
-    endforeach()
-endfunction()
diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt
deleted file mode 100644
index f8a52a4178..0000000000
--- a/fpga_interchange/examples/tests/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-add_subdirectory(wire)
-add_subdirectory(const_wire)
-add_subdirectory(counter)
-add_subdirectory(ram)
-add_subdirectory(ff)
-add_subdirectory(lut)
-add_subdirectory(lut_nexus)
-add_subdirectory(lutram)
-add_subdirectory(obuftds)
-add_subdirectory(ram_nexus)
diff --git a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt
deleted file mode 100644
index 3fff5fbbd3..0000000000
--- a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-add_interchange_group_test(
-    name const_wire
-    family ${family}
-    board_list basys3 arty35t arty100t
-    tcl run.tcl
-    sources wire.v
-)
diff --git a/fpga_interchange/examples/tests/const_wire/arty100t.xdc b/fpga_interchange/examples/tests/const_wire/arty100t.xdc
deleted file mode 100644
index a6e69de507..0000000000
--- a/fpga_interchange/examples/tests/const_wire/arty100t.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN H5  [get_ports o]
-set_property PACKAGE_PIN J5  [get_ports o2]
-set_property PACKAGE_PIN T9  [get_ports o3]
-set_property PACKAGE_PIN T10 [get_ports o4]
-
-set_property IOSTANDARD LVCMOS33 [get_ports o]
-set_property IOSTANDARD LVCMOS33 [get_ports o2]
-set_property IOSTANDARD LVCMOS33 [get_ports o3]
-set_property IOSTANDARD LVCMOS33 [get_ports o4]
diff --git a/fpga_interchange/examples/tests/const_wire/arty35t.xdc b/fpga_interchange/examples/tests/const_wire/arty35t.xdc
deleted file mode 100644
index a6e69de507..0000000000
--- a/fpga_interchange/examples/tests/const_wire/arty35t.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN H5  [get_ports o]
-set_property PACKAGE_PIN J5  [get_ports o2]
-set_property PACKAGE_PIN T9  [get_ports o3]
-set_property PACKAGE_PIN T10 [get_ports o4]
-
-set_property IOSTANDARD LVCMOS33 [get_ports o]
-set_property IOSTANDARD LVCMOS33 [get_ports o2]
-set_property IOSTANDARD LVCMOS33 [get_ports o3]
-set_property IOSTANDARD LVCMOS33 [get_ports o4]
diff --git a/fpga_interchange/examples/tests/const_wire/basys3.xdc b/fpga_interchange/examples/tests/const_wire/basys3.xdc
deleted file mode 100644
index f843558051..0000000000
--- a/fpga_interchange/examples/tests/const_wire/basys3.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN U16 [get_ports o]
-set_property PACKAGE_PIN E19 [get_ports o2]
-set_property PACKAGE_PIN U19 [get_ports o3]
-set_property PACKAGE_PIN V19 [get_ports o4]
-
-set_property IOSTANDARD LVCMOS33 [get_ports o]
-set_property IOSTANDARD LVCMOS33 [get_ports o2]
-set_property IOSTANDARD LVCMOS33 [get_ports o3]
-set_property IOSTANDARD LVCMOS33 [get_ports o4]
diff --git a/fpga_interchange/examples/tests/const_wire/run.tcl b/fpga_interchange/examples/tests/const_wire/run.tcl
deleted file mode 100644
index b8d0df721b..0000000000
--- a/fpga_interchange/examples/tests/const_wire/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/const_wire/wire.v b/fpga_interchange/examples/tests/const_wire/wire.v
deleted file mode 100644
index 5b1ab692a3..0000000000
--- a/fpga_interchange/examples/tests/const_wire/wire.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module top(output o, output o2, output o3, output o4);
-
-assign o = 1'b0;
-assign o2 = 1'b1;
-assign o3 = 1'b0;
-assign o4 = 1'b1;
-
-endmodule
diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt
deleted file mode 100644
index 2e0eefcca3..0000000000
--- a/fpga_interchange/examples/tests/counter/CMakeLists.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-add_interchange_group_test(
-    name counter
-    family ${family}
-    board_list basys3 arty35t arty100t zybo
-    tcl run_xilinx.tcl
-    sources counter.v
-    techmap ../../remap_xilinx.v
-    output_fasm
-)
-
-add_interchange_group_test(
-    name counter
-    family ${family}
-    board_list lifcl17 lifcl40evn
-    tcl run_nexus.tcl
-    sources counter.v
-    techmap ../../remap_nexus.v
-    skip_dcp
-)
diff --git a/fpga_interchange/examples/tests/counter/arty100t.xdc b/fpga_interchange/examples/tests/counter/arty100t.xdc
deleted file mode 100644
index c40df560b4..0000000000
--- a/fpga_interchange/examples/tests/counter/arty100t.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-## arty-100t board
-set_property PACKAGE_PIN E3  [get_ports clk]
-set_property PACKAGE_PIN D9  [get_ports rst]
-set_property PACKAGE_PIN H5  [get_ports io_led[4]]
-set_property PACKAGE_PIN J5  [get_ports io_led[5]]
-set_property PACKAGE_PIN T9  [get_ports io_led[6]]
-set_property PACKAGE_PIN T10 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/arty35t.xdc b/fpga_interchange/examples/tests/counter/arty35t.xdc
deleted file mode 100644
index 22c325ae78..0000000000
--- a/fpga_interchange/examples/tests/counter/arty35t.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-## arty-35t board
-set_property PACKAGE_PIN E3  [get_ports clk]
-set_property PACKAGE_PIN D9  [get_ports rst]
-set_property PACKAGE_PIN H5  [get_ports io_led[4]]
-set_property PACKAGE_PIN J5  [get_ports io_led[5]]
-set_property PACKAGE_PIN T9  [get_ports io_led[6]]
-set_property PACKAGE_PIN T10 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/basys3.xdc b/fpga_interchange/examples/tests/counter/basys3.xdc
deleted file mode 100644
index 09446b5ff4..0000000000
--- a/fpga_interchange/examples/tests/counter/basys3.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-## basys3 breakout board
-set_property PACKAGE_PIN W5 [get_ports clk]
-set_property PACKAGE_PIN V17 [get_ports rst]
-set_property PACKAGE_PIN U16 [get_ports io_led[4]]
-set_property PACKAGE_PIN E19 [get_ports io_led[5]]
-set_property PACKAGE_PIN U19 [get_ports io_led[6]]
-set_property PACKAGE_PIN V19 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v
deleted file mode 100644
index 4b3f343b62..0000000000
--- a/fpga_interchange/examples/tests/counter/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top(input clk, input rst, output [7:4] io_led);
-
-localparam SIZE = 32;
-
-reg [SIZE-1:0] counter = SIZE'b0;
-
-assign io_led = {counter[SIZE-1], counter[25:23]};
-
-always @(posedge clk)
-begin
-    if(rst)
-        counter <= SIZE'b0;
-    else
-        counter <= counter + 1;
-end
-
-endmodule
diff --git a/fpga_interchange/examples/tests/counter/lifcl17.xdc b/fpga_interchange/examples/tests/counter/lifcl17.xdc
deleted file mode 100644
index 2031964e3a..0000000000
--- a/fpga_interchange/examples/tests/counter/lifcl17.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-## lifcl17 pins for testing based on breakout board
-set_property PACKAGE_PIN 55 [get_ports clk]
-set_property PACKAGE_PIN 57 [get_ports rst]
-set_property PACKAGE_PIN 56 [get_ports io_led[4]]
-set_property PACKAGE_PIN 59 [get_ports io_led[5]]
-set_property PACKAGE_PIN 60 [get_ports io_led[6]]
-set_property PACKAGE_PIN 61 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/lifcl40evn.xdc b/fpga_interchange/examples/tests/counter/lifcl40evn.xdc
deleted file mode 100644
index 4f378aef50..0000000000
--- a/fpga_interchange/examples/tests/counter/lifcl40evn.xdc
+++ /dev/null
@@ -1,13 +0,0 @@
-set_property PACKAGE_PIN L13 [get_ports clk]
-set_property PACKAGE_PIN G19 [get_ports rst]
-set_property PACKAGE_PIN E17 [get_ports io_led[4]]
-set_property PACKAGE_PIN F13 [get_ports io_led[5]]
-set_property PACKAGE_PIN G13 [get_ports io_led[6]]
-set_property PACKAGE_PIN F14 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/run_nexus.tcl b/fpga_interchange/examples/tests/counter/run_nexus.tcl
deleted file mode 100644
index 8015057120..0000000000
--- a/fpga_interchange/examples/tests/counter/run_nexus.tcl
+++ /dev/null
@@ -1,15 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
-techmap -max_iter 1 -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
deleted file mode 100644
index c02cf93325..0000000000
--- a/fpga_interchange/examples/tests/counter/run_xilinx.tcl
+++ /dev/null
@@ -1,15 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nodsp
-techmap -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/counter/zybo.xdc b/fpga_interchange/examples/tests/counter/zybo.xdc
deleted file mode 100644
index e7764d527b..0000000000
--- a/fpga_interchange/examples/tests/counter/zybo.xdc
+++ /dev/null
@@ -1,14 +0,0 @@
-# zybo board
-set_property PACKAGE_PIN K17 [get_ports clk]
-set_property PACKAGE_PIN K18 [get_ports rst]
-set_property PACKAGE_PIN M14 [get_ports io_led[4]]
-set_property PACKAGE_PIN M15 [get_ports io_led[5]]
-set_property PACKAGE_PIN G14 [get_ports io_led[6]]
-set_property PACKAGE_PIN D18 [get_ports io_led[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/ff/CMakeLists.txt b/fpga_interchange/examples/tests/ff/CMakeLists.txt
deleted file mode 100644
index e119b7c3db..0000000000
--- a/fpga_interchange/examples/tests/ff/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-add_interchange_group_test(
-    name ff
-    family ${family}
-    board_list basys3 arty35t arty100t
-    tcl run.tcl
-    sources ff.v
-    output_fasm
-)
diff --git a/fpga_interchange/examples/tests/ff/arty100t.xdc b/fpga_interchange/examples/tests/ff/arty100t.xdc
deleted file mode 100644
index 29456f2a43..0000000000
--- a/fpga_interchange/examples/tests/ff/arty100t.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN E3 [get_ports clk]
-set_property PACKAGE_PIN A8 [get_ports d]
-set_property PACKAGE_PIN D9 [get_ports r]
-set_property PACKAGE_PIN H5 [get_ports q]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports d]
-set_property IOSTANDARD LVCMOS33 [get_ports r]
-set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/tests/ff/arty35t.xdc b/fpga_interchange/examples/tests/ff/arty35t.xdc
deleted file mode 100644
index 29456f2a43..0000000000
--- a/fpga_interchange/examples/tests/ff/arty35t.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN E3 [get_ports clk]
-set_property PACKAGE_PIN A8 [get_ports d]
-set_property PACKAGE_PIN D9 [get_ports r]
-set_property PACKAGE_PIN H5 [get_ports q]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports d]
-set_property IOSTANDARD LVCMOS33 [get_ports r]
-set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/tests/ff/basys3.xdc b/fpga_interchange/examples/tests/ff/basys3.xdc
deleted file mode 100644
index ef65112a25..0000000000
--- a/fpga_interchange/examples/tests/ff/basys3.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN W5 [get_ports clk]
-set_property PACKAGE_PIN U16 [get_ports d]
-set_property PACKAGE_PIN E19 [get_ports r]
-set_property PACKAGE_PIN U19 [get_ports q]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports d]
-set_property IOSTANDARD LVCMOS33 [get_ports r]
-set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/tests/ff/ff.v b/fpga_interchange/examples/tests/ff/ff.v
deleted file mode 100644
index 1c27104281..0000000000
--- a/fpga_interchange/examples/tests/ff/ff.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top(input clk, input d, input r, output reg q);
-
-always @(posedge clk)
-begin
-    if(r)
-        q <= 1'b0;
-    else
-        q <= d;
-end
-
-endmodule
diff --git a/fpga_interchange/examples/tests/ff/run.tcl b/fpga_interchange/examples/tests/ff/run.tcl
deleted file mode 100644
index b8d0df721b..0000000000
--- a/fpga_interchange/examples/tests/ff/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/lut/CMakeLists.txt b/fpga_interchange/examples/tests/lut/CMakeLists.txt
deleted file mode 100644
index 77a4b4da99..0000000000
--- a/fpga_interchange/examples/tests/lut/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-add_interchange_group_test(
-    name lut
-    family ${family}
-    board_list basys3 arty35t arty100t
-    tcl run.tcl
-    sources lut.v
-    output_fasm
-)
diff --git a/fpga_interchange/examples/tests/lut/arty100t.xdc b/fpga_interchange/examples/tests/lut/arty100t.xdc
deleted file mode 100644
index 1dba65740c..0000000000
--- a/fpga_interchange/examples/tests/lut/arty100t.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_property PACKAGE_PIN A8  [get_ports i0]
-set_property PACKAGE_PIN C11 [get_ports i1]
-set_property PACKAGE_PIN H5  [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i0]
-set_property IOSTANDARD LVCMOS33 [get_ports i1]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/lut/arty35t.xdc b/fpga_interchange/examples/tests/lut/arty35t.xdc
deleted file mode 100644
index 1dba65740c..0000000000
--- a/fpga_interchange/examples/tests/lut/arty35t.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_property PACKAGE_PIN A8  [get_ports i0]
-set_property PACKAGE_PIN C11 [get_ports i1]
-set_property PACKAGE_PIN H5  [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i0]
-set_property IOSTANDARD LVCMOS33 [get_ports i1]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/lut/basys3.xdc b/fpga_interchange/examples/tests/lut/basys3.xdc
deleted file mode 100644
index aef287eeb1..0000000000
--- a/fpga_interchange/examples/tests/lut/basys3.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_property PACKAGE_PIN V17 [get_ports i0]
-set_property PACKAGE_PIN V16 [get_ports i1]
-set_property PACKAGE_PIN U16 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i0]
-set_property IOSTANDARD LVCMOS33 [get_ports i1]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/lut/lut.v b/fpga_interchange/examples/tests/lut/lut.v
deleted file mode 100644
index ca18e665d7..0000000000
--- a/fpga_interchange/examples/tests/lut/lut.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module top(input i0, input i1, output o);
-
-assign o = i0 | i1;
-
-endmodule
diff --git a/fpga_interchange/examples/tests/lut/run.tcl b/fpga_interchange/examples/tests/lut/run.tcl
deleted file mode 100644
index b8d0df721b..0000000000
--- a/fpga_interchange/examples/tests/lut/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt b/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
deleted file mode 100644
index 7ca3634352..0000000000
--- a/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-add_interchange_test(
-    name lut_nexus
-    family ${family}
-    device LIFCL-17
-    package QFN72
-    tcl run.tcl
-    xdc empty.xdc
-    sources lut.v
-    skip_dcp
-)
-
-add_interchange_test(
-    name lut_nexus40
-    family ${family}
-    device LIFCL-40
-    package CABGA400
-    tcl run.tcl
-    xdc empty.xdc
-    sources lut.v
-    skip_dcp
-)
diff --git a/fpga_interchange/examples/tests/lut_nexus/empty.xdc b/fpga_interchange/examples/tests/lut_nexus/empty.xdc
deleted file mode 100644
index e69de29bb2..0000000000
diff --git a/fpga_interchange/examples/tests/lut_nexus/lut.v b/fpga_interchange/examples/tests/lut_nexus/lut.v
deleted file mode 100644
index 5913aff123..0000000000
--- a/fpga_interchange/examples/tests/lut_nexus/lut.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module top;
-	wire x, y;
-	(*keep*)
-	LUT4 lut_0(.A(x), .B(x), .C(x), .D(x), .Z(y));
-	(*keep*)
-	LUT4 lut_1(.A(y), .B(y), .C(y), .D(y), .Z(x));
-endmodule
\ No newline at end of file
diff --git a/fpga_interchange/examples/tests/lut_nexus/run.tcl b/fpga_interchange/examples/tests/lut_nexus/run.tcl
deleted file mode 100644
index 4aa56c138d..0000000000
--- a/fpga_interchange/examples/tests/lut_nexus/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_nexus -noccu2 -nobram -nolutram -nowidelut
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/lutram/CMakeLists.txt b/fpga_interchange/examples/tests/lutram/CMakeLists.txt
deleted file mode 100644
index 0d45e8f839..0000000000
--- a/fpga_interchange/examples/tests/lutram/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-add_interchange_group_test(
-    name lutram
-    family ${family}
-    board_list basys3
-    tcl run.tcl
-    sources lutram.v
-)
-
diff --git a/fpga_interchange/examples/tests/lutram/basys3.pcf b/fpga_interchange/examples/tests/lutram/basys3.pcf
deleted file mode 100644
index cb4191cc37..0000000000
--- a/fpga_interchange/examples/tests/lutram/basys3.pcf
+++ /dev/null
@@ -1,41 +0,0 @@
-# basys3 100 MHz CLK
-set_io clk W5
-
-set_io tx A18
-set_io rx B18
-#
-# in[0:15] correspond with SW0-SW15 on the basys3
-set_io sw[0] V17
-set_io sw[1] V16
-set_io sw[2] W16
-set_io sw[3] W17
-set_io sw[4] W15
-set_io sw[5] V15
-set_io sw[6] W14
-set_io sw[7] W13
-set_io sw[8] V2
-set_io sw[9] T3
-set_io sw[10] T2
-set_io sw[11] R3
-set_io sw[12] W2
-set_io sw[13] U1
-set_io sw[14] T1
-set_io sw[15] R2
-
-# out[0:15] correspond with LD0-LD15 on the basys3
-set_io led[0] U16
-set_io led[1] E19
-set_io led[2] U19
-set_io led[3] V19
-set_io led[4] W18
-set_io led[5] U15
-set_io led[6] U14
-set_io led[7] V14
-set_io led[8] V13
-set_io led[9] V3
-set_io led[10] W3
-set_io led[11] U3
-set_io led[12] P3
-set_io led[13] N3
-set_io led[14] P1
-set_io led[15] L1
diff --git a/fpga_interchange/examples/tests/lutram/basys3.xdc b/fpga_interchange/examples/tests/lutram/basys3.xdc
deleted file mode 100644
index 58e1859c13..0000000000
--- a/fpga_interchange/examples/tests/lutram/basys3.xdc
+++ /dev/null
@@ -1,80 +0,0 @@
-# basys3 100 MHz CLK
-set_property PACKAGE_PIN W5 [get_ports clk]
-
-set_property PACKAGE_PIN A18 [get_ports tx]
-set_property PACKAGE_PIN B18 [get_ports rx]
-#
-# in[0:15] correspond with SW0-SW15 on the basys3
-set_property PACKAGE_PIN V17 [get_ports sw[0]]
-set_property PACKAGE_PIN V16 [get_ports sw[1]]
-set_property PACKAGE_PIN W16 [get_ports sw[2]]
-set_property PACKAGE_PIN W17 [get_ports sw[3]]
-set_property PACKAGE_PIN W15 [get_ports sw[4]]
-set_property PACKAGE_PIN V15 [get_ports sw[5]]
-set_property PACKAGE_PIN W14 [get_ports sw[6]]
-set_property PACKAGE_PIN W13 [get_ports sw[7]]
-set_property PACKAGE_PIN V2  [get_ports sw[8]]
-set_property PACKAGE_PIN T3  [get_ports sw[9]]
-set_property PACKAGE_PIN T2  [get_ports sw[10]]
-set_property PACKAGE_PIN R3  [get_ports sw[11]]
-set_property PACKAGE_PIN W2  [get_ports sw[12]]
-set_property PACKAGE_PIN U1  [get_ports sw[13]]
-set_property PACKAGE_PIN T1  [get_ports sw[14]]
-set_property PACKAGE_PIN R2  [get_ports sw[15]]
-
-# out[0:15] correspond with LD0-LD15 on the basys3
-set_property PACKAGE_PIN U16 [get_ports led[0]]
-set_property PACKAGE_PIN E19 [get_ports led[1]]
-set_property PACKAGE_PIN U19 [get_ports led[2]]
-set_property PACKAGE_PIN V19 [get_ports led[3]]
-set_property PACKAGE_PIN W18 [get_ports led[4]]
-set_property PACKAGE_PIN U15 [get_ports led[5]]
-set_property PACKAGE_PIN U14 [get_ports led[6]]
-set_property PACKAGE_PIN V14 [get_ports led[7]]
-set_property PACKAGE_PIN V13 [get_ports led[8]]
-set_property PACKAGE_PIN V3  [get_ports led[9]]
-set_property PACKAGE_PIN W3  [get_ports led[10]]
-set_property PACKAGE_PIN U3  [get_ports led[11]]
-set_property PACKAGE_PIN P3  [get_ports led[12]]
-set_property PACKAGE_PIN N3  [get_ports led[13]]
-set_property PACKAGE_PIN P1  [get_ports led[14]]
-set_property PACKAGE_PIN L1  [get_ports led[15]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-
-set_property IOSTANDARD LVCMOS33 [get_ports tx]
-set_property IOSTANDARD LVCMOS33 [get_ports rx]
-#
-set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[8]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[9]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[10]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[11]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[12]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[13]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[14]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[15]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[15]]
diff --git a/fpga_interchange/examples/tests/lutram/lutram.v b/fpga_interchange/examples/tests/lutram/lutram.v
deleted file mode 100644
index f38197d474..0000000000
--- a/fpga_interchange/examples/tests/lutram/lutram.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module top (
-    input  wire clk,
-
-    input  wire rx,
-    output wire tx,
-
-    input  wire [15:0] sw,
-    output wire [15:0] led
-);
-    RAM128X1D #(
-        .INIT(128'hFFEEDDCCBBAA99887766554433221100)
-    ) ram_i (
-        .WCLK(clk),
-        .A(sw[6:0]),
-        .DPRA(sw[13:7]),
-        .WE(sw[14]),
-        .D(sw[15]),
-        .SPO(led[0]),
-        .DPO(led[1]),
-    );
-
-    assign led[15:2] = 14'b0;
-    assign tx = rx;
-endmodule
diff --git a/fpga_interchange/examples/tests/lutram/run.tcl b/fpga_interchange/examples/tests/lutram/run.tcl
deleted file mode 100644
index 79321139f3..0000000000
--- a/fpga_interchange/examples/tests/lutram/run.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-yosys -import
-
-foreach src $::env(SOURCES) {
-    read_verilog $src
-}
-
-synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
-techmap -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/obuftds/CMakeLists.txt b/fpga_interchange/examples/tests/obuftds/CMakeLists.txt
deleted file mode 100644
index 0313c9bb3c..0000000000
--- a/fpga_interchange/examples/tests/obuftds/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-add_interchange_group_test(
-    name obuftds
-    family ${family}
-    board_list basys3
-    tcl run.tcl
-    sources obuftds.v
-)
diff --git a/fpga_interchange/examples/tests/obuftds/basys3.xdc b/fpga_interchange/examples/tests/obuftds/basys3.xdc
deleted file mode 100644
index 4b77723367..0000000000
--- a/fpga_interchange/examples/tests/obuftds/basys3.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN V2 [get_ports sw[8] ]
-set_property PACKAGE_PIN T3 [get_ports sw[9] ]
-set_property PACKAGE_PIN T2 [get_ports sw[10]]
-set_property PACKAGE_PIN R3 [get_ports sw[11]]
-
-set_property PACKAGE_PIN U19 [get_ports diff_p[0]]
-set_property PACKAGE_PIN V19 [get_ports diff_n[0]]
-set_property PACKAGE_PIN V13 [get_ports diff_p[1]]
-set_property PACKAGE_PIN V14 [get_ports diff_n[1]]
diff --git a/fpga_interchange/examples/tests/obuftds/obuftds.v b/fpga_interchange/examples/tests/obuftds/obuftds.v
deleted file mode 100644
index d4e9a60394..0000000000
--- a/fpga_interchange/examples/tests/obuftds/obuftds.v
+++ /dev/null
@@ -1,37 +0,0 @@
-module top(
-  input  wire [11:8] sw,
-
-  output wire [1:0]  diff_p,
-  output wire [1:0]  diff_n
-);
-
-wire [1:0] buf_i;
-wire [1:0] buf_t;
-
-OBUFTDS # (
-  .IOSTANDARD("DIFF_SSTL135"),
-  .SLEW("FAST")
-) obuftds_0 (
-  .I(buf_i[0]),
-  .T(buf_t[0]),
-  .O(diff_p[0]),
-  .OB(diff_n[0])
-);
-
-OBUFTDS # (
-  .IOSTANDARD("DIFF_SSTL135"),
-  .SLEW("FAST")
-) obuftds_1 (
-  .I(buf_i[1]),
-  .T(buf_t[1]),
-  .O(diff_p[1]),
-  .OB(diff_n[1])
-);
-
-assign buf_i[0] = sw[ 8];
-assign buf_t[0] = sw[ 9];
-assign buf_i[1] = sw[10];
-assign buf_t[1] = sw[11];
-
-endmodule
-
diff --git a/fpga_interchange/examples/tests/obuftds/run.tcl b/fpga_interchange/examples/tests/obuftds/run.tcl
deleted file mode 100644
index b8d0df721b..0000000000
--- a/fpga_interchange/examples/tests/obuftds/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/ram/CMakeLists.txt b/fpga_interchange/examples/tests/ram/CMakeLists.txt
deleted file mode 100644
index 56db487011..0000000000
--- a/fpga_interchange/examples/tests/ram/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-add_interchange_group_test(
-    name ram
-    family ${family}
-    board_list basys3
-    tcl run.tcl
-    sources ram.v
-)
-
diff --git a/fpga_interchange/examples/tests/ram/basys3.pcf b/fpga_interchange/examples/tests/ram/basys3.pcf
deleted file mode 100644
index cb4191cc37..0000000000
--- a/fpga_interchange/examples/tests/ram/basys3.pcf
+++ /dev/null
@@ -1,41 +0,0 @@
-# basys3 100 MHz CLK
-set_io clk W5
-
-set_io tx A18
-set_io rx B18
-#
-# in[0:15] correspond with SW0-SW15 on the basys3
-set_io sw[0] V17
-set_io sw[1] V16
-set_io sw[2] W16
-set_io sw[3] W17
-set_io sw[4] W15
-set_io sw[5] V15
-set_io sw[6] W14
-set_io sw[7] W13
-set_io sw[8] V2
-set_io sw[9] T3
-set_io sw[10] T2
-set_io sw[11] R3
-set_io sw[12] W2
-set_io sw[13] U1
-set_io sw[14] T1
-set_io sw[15] R2
-
-# out[0:15] correspond with LD0-LD15 on the basys3
-set_io led[0] U16
-set_io led[1] E19
-set_io led[2] U19
-set_io led[3] V19
-set_io led[4] W18
-set_io led[5] U15
-set_io led[6] U14
-set_io led[7] V14
-set_io led[8] V13
-set_io led[9] V3
-set_io led[10] W3
-set_io led[11] U3
-set_io led[12] P3
-set_io led[13] N3
-set_io led[14] P1
-set_io led[15] L1
diff --git a/fpga_interchange/examples/tests/ram/basys3.xdc b/fpga_interchange/examples/tests/ram/basys3.xdc
deleted file mode 100644
index 58e1859c13..0000000000
--- a/fpga_interchange/examples/tests/ram/basys3.xdc
+++ /dev/null
@@ -1,80 +0,0 @@
-# basys3 100 MHz CLK
-set_property PACKAGE_PIN W5 [get_ports clk]
-
-set_property PACKAGE_PIN A18 [get_ports tx]
-set_property PACKAGE_PIN B18 [get_ports rx]
-#
-# in[0:15] correspond with SW0-SW15 on the basys3
-set_property PACKAGE_PIN V17 [get_ports sw[0]]
-set_property PACKAGE_PIN V16 [get_ports sw[1]]
-set_property PACKAGE_PIN W16 [get_ports sw[2]]
-set_property PACKAGE_PIN W17 [get_ports sw[3]]
-set_property PACKAGE_PIN W15 [get_ports sw[4]]
-set_property PACKAGE_PIN V15 [get_ports sw[5]]
-set_property PACKAGE_PIN W14 [get_ports sw[6]]
-set_property PACKAGE_PIN W13 [get_ports sw[7]]
-set_property PACKAGE_PIN V2  [get_ports sw[8]]
-set_property PACKAGE_PIN T3  [get_ports sw[9]]
-set_property PACKAGE_PIN T2  [get_ports sw[10]]
-set_property PACKAGE_PIN R3  [get_ports sw[11]]
-set_property PACKAGE_PIN W2  [get_ports sw[12]]
-set_property PACKAGE_PIN U1  [get_ports sw[13]]
-set_property PACKAGE_PIN T1  [get_ports sw[14]]
-set_property PACKAGE_PIN R2  [get_ports sw[15]]
-
-# out[0:15] correspond with LD0-LD15 on the basys3
-set_property PACKAGE_PIN U16 [get_ports led[0]]
-set_property PACKAGE_PIN E19 [get_ports led[1]]
-set_property PACKAGE_PIN U19 [get_ports led[2]]
-set_property PACKAGE_PIN V19 [get_ports led[3]]
-set_property PACKAGE_PIN W18 [get_ports led[4]]
-set_property PACKAGE_PIN U15 [get_ports led[5]]
-set_property PACKAGE_PIN U14 [get_ports led[6]]
-set_property PACKAGE_PIN V14 [get_ports led[7]]
-set_property PACKAGE_PIN V13 [get_ports led[8]]
-set_property PACKAGE_PIN V3  [get_ports led[9]]
-set_property PACKAGE_PIN W3  [get_ports led[10]]
-set_property PACKAGE_PIN U3  [get_ports led[11]]
-set_property PACKAGE_PIN P3  [get_ports led[12]]
-set_property PACKAGE_PIN N3  [get_ports led[13]]
-set_property PACKAGE_PIN P1  [get_ports led[14]]
-set_property PACKAGE_PIN L1  [get_ports led[15]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-
-set_property IOSTANDARD LVCMOS33 [get_ports tx]
-set_property IOSTANDARD LVCMOS33 [get_ports rx]
-#
-set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[8]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[9]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[10]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[11]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[12]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[13]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[14]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[15]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[15]]
diff --git a/fpga_interchange/examples/tests/ram/ram.v b/fpga_interchange/examples/tests/ram/ram.v
deleted file mode 100644
index aec5c4d150..0000000000
--- a/fpga_interchange/examples/tests/ram/ram.v
+++ /dev/null
@@ -1,134 +0,0 @@
-module ram0(
-    // Write port
-    input wrclk,
-    input [15:0] di,
-    input wren,
-    input [9:0] wraddr,
-    // Read port
-    input rdclk,
-    input rden,
-    input [9:0] rdaddr,
-    output reg [15:0] do);
-
-    (* ram_style = "block" *) reg [15:0] ram[0:1023];
-
-    initial begin
-        ram[0] = 16'b00000000_00000001;
-        ram[1] = 16'b10101010_10101010;
-        ram[2] = 16'b01010101_01010101;
-        ram[3] = 16'b11111111_11111111;
-        ram[4] = 16'b11110000_11110000;
-        ram[5] = 16'b00001111_00001111;
-        ram[6] = 16'b11001100_11001100;
-        ram[7] = 16'b00110011_00110011;
-        ram[8] = 16'b00000000_00000010;
-        ram[9] = 16'b00000000_00000100;
-    end
-
-    always @ (posedge wrclk) begin
-        if(wren == 1) begin
-            ram[wraddr] <= di;
-        end
-    end
-
-    always @ (posedge rdclk) begin
-        if(rden == 1) begin
-            do <= ram[rdaddr];
-        end
-    end
-
-endmodule
-
-module top (
-    input  wire clk,
-
-    input  wire rx,
-    output wire tx,
-
-    input  wire [15:0] sw,
-    output wire [15:0] led
-);
-    wire rden;
-    reg wren;
-    wire [9:0] rdaddr;
-    wire [9:0] wraddr;
-    wire [15:0] di;
-    wire [15:0] do;
-    ram0 ram(
-        .wrclk(clk),
-        .di(di),
-        .wren(wren),
-        .wraddr(wraddr),
-        .rdclk(clk),
-        .rden(rden),
-        .rdaddr(rdaddr),
-        .do(do)
-    );
-
-    reg [9:0] address_reg;
-    reg [15:0] data_reg;
-    reg [15:0] out_reg;
-
-    assign rdaddr = address_reg;
-    assign wraddr = address_reg;
-
-    // display_mode == 00 -> ram[address_reg]
-    // display_mode == 01 -> address_reg
-    // display_mode == 10 -> data_reg
-    wire [1:0] display_mode;
-
-    // input_mode == 00 -> in[9:0] -> address_reg
-    // input_mode == 01 -> in[7:0] -> data_reg[7:0]
-    // input_mode == 10 -> in[7:0] -> data_reg[15:8]
-    // input_mode == 11 -> data_reg -> ram[address_reg]
-    wire [1:0] input_mode;
-
-    // WE == 0 -> address_reg and data_reg unchanged.
-    // WE == 1 -> address_reg or data_reg is updated because on input_mode.
-    wire we;
-
-    assign display_mode[0] = sw[14];
-    assign display_mode[1] = sw[15];
-
-    assign input_mode[0] = sw[12];
-    assign input_mode[1] = sw[13];
-
-    assign we = sw[11];
-    assign led = out_reg;
-    assign di = data_reg;
-    assign rden = 1;
-
-    initial begin
-        address_reg = 10'b0;
-        data_reg = 16'b0;
-        out_reg = 16'b0;
-    end
-
-    always @ (posedge clk) begin
-        if(display_mode == 0) begin
-            out_reg <= do;
-        end else if(display_mode == 1) begin
-            out_reg <= address_reg;
-        end else if(display_mode == 2) begin
-            out_reg <= data_reg;
-        end
-
-        if(we == 1) begin
-            if(input_mode == 0) begin
-                address_reg <= sw[9:0];
-                wren <= 0;
-            end else if(input_mode == 1) begin
-                data_reg[7:0] <= sw[7:0];
-                wren <= 0;
-            end else if(input_mode == 2) begin
-                data_reg[15:8] <= sw[7:0];
-                wren <= 0;
-            end else if(input_mode == 3) begin
-                wren <= 1;
-            end
-        end
-    end
-
-    // Uart loopback
-    assign tx = rx;
-endmodule
diff --git a/fpga_interchange/examples/tests/ram/run.tcl b/fpga_interchange/examples/tests/ram/run.tcl
deleted file mode 100644
index 79321139f3..0000000000
--- a/fpga_interchange/examples/tests/ram/run.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-yosys -import
-
-foreach src $::env(SOURCES) {
-    read_verilog $src
-}
-
-synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
-techmap -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt b/fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt
deleted file mode 100644
index 49d976c53b..0000000000
--- a/fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-add_interchange_group_test(
-    name ram_nexus
-    family ${family}
-    board_list lifcl40evn
-    tcl run_nexus.tcl
-    sources ram_nexus.v
-    techmap ../../remap_nexus.v
-    skip_dcp
-)
-
diff --git a/fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc b/fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc
deleted file mode 100644
index 2fb0b3a28b..0000000000
--- a/fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-set_property PACKAGE_PIN L13 [get_ports clk]
-
-set_property PACKAGE_PIN E17 [get_ports led[0]]
-set_property PACKAGE_PIN F13 [get_ports led[1]]
-set_property PACKAGE_PIN G13 [get_ports led[2]]
-set_property PACKAGE_PIN F14 [get_ports led[3]]
-set_property PACKAGE_PIN L16 [get_ports led[4]]
-set_property PACKAGE_PIN L15 [get_ports led[5]]
-set_property PACKAGE_PIN L20 [get_ports led[6]]
-set_property PACKAGE_PIN L19 [get_ports led[7]]
-set_property PACKAGE_PIN R17 [get_ports led[8]]
-set_property PACKAGE_PIN R18 [get_ports led[9]]
-set_property PACKAGE_PIN U20 [get_ports led[10]]
-set_property PACKAGE_PIN T20 [get_ports led[11]]
-set_property PACKAGE_PIN W20 [get_ports led[12]]
-set_property PACKAGE_PIN V20 [get_ports led[13]]
-
-set_property PACKAGE_PIN G14 [get_ports pb0]
-set_property PACKAGE_PIN G15 [get_ports pb1]
-
-set_property PACKAGE_PIN N14 [get_ports sw[0]]
-set_property PACKAGE_PIN M14 [get_ports sw[1]]
-set_property PACKAGE_PIN M16 [get_ports sw[2]]
-set_property PACKAGE_PIN M15 [get_ports sw[3]]
-set_property PACKAGE_PIN N15 [get_ports sw[4]]
-set_property PACKAGE_PIN N16 [get_ports sw[5]]
-set_property PACKAGE_PIN M17 [get_ports sw[6]]
-set_property PACKAGE_PIN M18 [get_ports sw[7]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-
-set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
-set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
-
-set_property IOSTANDARD LVCMOS33 [get_ports pb0]
-set_property IOSTANDARD LVCMOS33 [get_ports pb1]
-
-set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
-set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
\ No newline at end of file
diff --git a/fpga_interchange/examples/tests/ram_nexus/ram_nexus.v b/fpga_interchange/examples/tests/ram_nexus/ram_nexus.v
deleted file mode 100644
index e91a64bc1d..0000000000
--- a/fpga_interchange/examples/tests/ram_nexus/ram_nexus.v
+++ /dev/null
@@ -1,123 +0,0 @@
-module ram0(
-    // Write port
-    input wrclk,
-    input [7:0] di,
-    input wren,
-    input [5:0] wraddr,
-    // Read port
-    input rdclk,
-    input rden,
-    input [5:0] rdaddr,
-    output reg [7:0] do);
-
-    (* syn_ramstyle = "block_ram" *) reg [7:0] ram[0:63];
-
-    initial begin
-        ram[0] = 8'b00000001;
-        ram[1] = 8'b10101010;
-        ram[2] = 8'b01010101;
-        ram[3] = 8'b11111111;
-        ram[4] = 8'b11110000;
-        ram[5] = 8'b00001111;
-        ram[6] = 8'b11001100;
-        ram[7] = 8'b00110011;
-        ram[8] = 8'b00000010;
-        ram[9] = 8'b00000100;
-    end
-
-    always @ (posedge wrclk) begin
-        if(wren == 1) begin
-            ram[wraddr] <= di;
-        end
-    end
-
-    always @ (posedge rdclk) begin
-        if(rden == 1) begin
-            do <= ram[rdaddr];
-        end
-    end
-
-endmodule
-
-module top (
-    input  wire clk,
-
-    input wire  pb0,
-    input wire  pb1,
-
-    input  wire [7:0] sw,
-    output wire [13:0] led
-);
-    wire bufclk;
-    DCC gbuf_i(.CLKI(clk), .CLKO(bufclk));
-
-
-    wire rden;
-    reg wren;
-    wire [5:0] rdaddr;
-    wire [5:0] wraddr;
-    wire [7:0] di;
-    wire [7:0] do;
-    ram0 ram(
-        .wrclk(bufclk),
-        .di(di),
-        .wren(wren),
-        .wraddr(wraddr),
-        .rdclk(bufclk),
-        .rden(rden),
-        .rdaddr(rdaddr),
-        .do(do)
-    );
-
-    reg [5:0] address_reg;
-    reg [7:0] data_reg;
-    reg [7:0] out_reg;
-
-    assign rdaddr = address_reg;
-    assign wraddr = address_reg;
-
-    // input_mode == 00 -> in[3:0] -> address_reg
-    // input_mode == 01 -> in[3:0] -> data_reg[3:0]
-    // input_mode == 10 -> in[3:0] -> data_reg[7:4]
-    // input_mode == 11 -> data_reg -> ram[address_reg]
-    wire [1:0] input_mode;
-
-    // WE == 0 -> address_reg and data_reg unchanged.
-    // WE == 1 -> address_reg or data_reg is updated because on input_mode.
-    wire we;
-
-    assign input_mode[0] = ~sw[6];
-    assign input_mode[1] = ~sw[7];
-
-    assign we = ~pb0;
-    assign led = ~{address_reg, out_reg};
-    assign di = data_reg;
-    assign rden = 1;
-
-    initial begin
-        wren = 1'b0;
-        address_reg = 10'b0;
-        data_reg = 16'b0;
-        out_reg = 16'b0;
-    end
-
-    always @ (posedge bufclk) begin
-        out_reg <= do;
-
-        if(we == 1) begin
-            if(input_mode == 0) begin
-                address_reg <= ~sw[5:0];
-                wren <= 0;
-            end else if(input_mode == 1) begin
-                data_reg[3:0] <= ~sw[3:0];
-                wren <= 0;
-            end else if(input_mode == 2) begin
-                data_reg[7:4] <= ~sw[3:0];
-                wren <= 0;
-            end else if(input_mode == 3) begin
-                wren <= 1;
-            end
-        end
-    end
-
-endmodule
diff --git a/fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl b/fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl
deleted file mode 100644
index 4ea5e28221..0000000000
--- a/fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl
+++ /dev/null
@@ -1,15 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_nexus -nolutram -nowidelut -noccu2 -nodsp
-techmap -max_iter 1 -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt
deleted file mode 100644
index 9caffcd190..0000000000
--- a/fpga_interchange/examples/tests/wire/CMakeLists.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-add_interchange_group_test(
-    name wire
-    family ${family}
-    board_list basys3 arty35t zybo arty100t nexys_video
-    tcl run.tcl
-    sources wire.v
-    output_fasm
-)
-
-add_interchange_group_test(
-    name wire
-    family ${family}
-    board_list lifcl40evn
-    tcl run_nexus.tcl
-    sources wire.v
-    skip_dcp
-)
diff --git a/fpga_interchange/examples/tests/wire/arty100t.xdc b/fpga_interchange/examples/tests/wire/arty100t.xdc
deleted file mode 100644
index 54c661c978..0000000000
--- a/fpga_interchange/examples/tests/wire/arty100t.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN A8 [get_ports i]
-set_property PACKAGE_PIN H5 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/arty35t.xdc b/fpga_interchange/examples/tests/wire/arty35t.xdc
deleted file mode 100644
index 54c661c978..0000000000
--- a/fpga_interchange/examples/tests/wire/arty35t.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN A8 [get_ports i]
-set_property PACKAGE_PIN H5 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/basys3.xdc b/fpga_interchange/examples/tests/wire/basys3.xdc
deleted file mode 100644
index 317d5accd2..0000000000
--- a/fpga_interchange/examples/tests/wire/basys3.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN V17 [get_ports i]
-set_property PACKAGE_PIN U16 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/lifcl40evn.xdc b/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
deleted file mode 100644
index c1a8748895..0000000000
--- a/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN G19 [get_ports i]
-set_property PACKAGE_PIN E17 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/nexys_video.xdc b/fpga_interchange/examples/tests/wire/nexys_video.xdc
deleted file mode 100644
index 326f77cb8c..0000000000
--- a/fpga_interchange/examples/tests/wire/nexys_video.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN E22 [get_ports i]
-set_property PACKAGE_PIN T14 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/run.tcl b/fpga_interchange/examples/tests/wire/run.tcl
deleted file mode 100644
index b8d0df721b..0000000000
--- a/fpga_interchange/examples/tests/wire/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/wire/run_nexus.tcl b/fpga_interchange/examples/tests/wire/run_nexus.tcl
deleted file mode 100644
index cddad3f814..0000000000
--- a/fpga_interchange/examples/tests/wire/run_nexus.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/wire/wire.v b/fpga_interchange/examples/tests/wire/wire.v
deleted file mode 100644
index 429d05ff28..0000000000
--- a/fpga_interchange/examples/tests/wire/wire.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module top(input i, output o);
-
-assign o = i;
-
-endmodule
diff --git a/fpga_interchange/examples/tests/wire/zybo.xdc b/fpga_interchange/examples/tests/wire/zybo.xdc
deleted file mode 100644
index 072c19d213..0000000000
--- a/fpga_interchange/examples/tests/wire/zybo.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN G15 [get_ports i]
-set_property PACKAGE_PIN M14 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/family.cmake b/fpga_interchange/family.cmake
deleted file mode 100644
index 863ab06e2b..0000000000
--- a/fpga_interchange/family.cmake
+++ /dev/null
@@ -1,63 +0,0 @@
-find_package(TCL)
-if(NOT ${TCL_FOUND})
-    message(FATAL_ERROR "Tcl is required for FPGA interchange Arch.")
-endif()
-
-find_package(ZLIB REQUIRED)
-
-set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
-set(INVOKE_RAPIDWRIGHT "${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh" CACHE PATH "Path to RapidWright invocation script")
-set(JAVA_HEAP_SPACE "-Xmx8g" CACHE STRING "Heap space reserved for Java")
-set(PRJOXIDE_PREFIX $ENV{HOME}/.cargo CACHE PATH "prjoxide install prefix")
-
-# FIXME: Make patch data available in the python package and remove this cached var
-set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
-set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir")
-
-add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
-
-include(${family}/examples/chipdb.cmake)
-include(${family}/examples/boards.cmake)
-include(${family}/examples/tests.cmake)
-
-set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
-file(MAKE_DIRECTORY ${chipdb_dir})
-
-add_custom_target(all-${family}-tests)
-add_custom_target(all-${family}-fasm)
-add_custom_target(all-${family}-archcheck-tests)
-add_subdirectory(${family}/examples/devices)
-add_subdirectory(${family}/examples/boards)
-add_subdirectory(${family}/examples/tests)
-
-set(PROTOS lookahead.capnp)
-set(CAPNP_SRCS)
-set(CAPNP_HDRS)
-find_package(CapnProto REQUIRED)
-foreach (proto ${PROTOS})
-    capnp_generate_cpp(CAPNP_SRC CAPNP_HDR fpga_interchange/${proto})
-    list(APPEND CAPNP_HDRS ${CAPNP_HDR})
-    list(APPEND CAPNP_SRCS ${CAPNP_SRC})
-endforeach()
-
-add_library(extra_capnp STATIC ${CAPNP_SRCS})
-target_link_libraries(extra_capnp PRIVATE CapnProto::capnp)
-
-target_include_directories(extra_capnp INTERFACE ${CMAKE_CURRENT_BINARY_DIR}/fpga_interchange)
-
-foreach (target ${family_targets})
-    target_include_directories(${target} PRIVATE ${TCL_INCLUDE_PATH})
-    target_link_libraries(${target} PRIVATE ${TCL_LIBRARY})
-    target_link_libraries(${target} PRIVATE fpga_interchange_capnp)
-    target_link_libraries(${target} PRIVATE extra_capnp)
-    target_link_libraries(${target} PRIVATE z)
-endforeach()
-
-if(BUILD_GUI)
-    target_link_libraries(gui_${family} fpga_interchange_capnp)
-    target_link_libraries(gui_${family} extra_capnp)
-    target_link_libraries(gui_${family} z)
-endif()
-if (BUILD_TESTS)
-    add_subdirectory(tests/${family}/site_router_tests)
-endif()
diff --git a/fpga_interchange/flat_wire_map.h b/fpga_interchange/flat_wire_map.h
deleted file mode 100644
index 71ecd0b611..0000000000
--- a/fpga_interchange/flat_wire_map.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef FLAT_WIRE_MAP_H_
-#define FLAT_WIRE_MAP_H_
-
-#include "context.h"
-#include "dynamic_bitarray.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-template <typename Value> class FlatTileWireMap
-{
-  public:
-    std::pair<Value *, bool> emplace(const Context *ctx, WireId wire, const Value &value)
-    {
-        if (values_.empty()) {
-            if (wire.tile == -1) {
-                resize(ctx->chip_info->nodes.size());
-            } else {
-                resize(loc_info(ctx->chip_info, wire).wire_data.size());
-            }
-        }
-
-        if (set_.get(wire.index)) {
-            return std::make_pair(&values_[wire.index], false);
-        } else {
-            values_[wire.index] = value;
-            set_.set(wire.index, true);
-            return std::make_pair(&values_[wire.index], true);
-        }
-    }
-
-    const Value &at(WireId wire) const
-    {
-        NPNR_ASSERT(!values_.empty());
-        NPNR_ASSERT(set_.get(wire.index));
-        return values_.at(wire.index);
-    }
-
-    void clear()
-    {
-        if (!values_.empty()) {
-            set_.fill(false);
-        }
-    }
-
-  private:
-    void resize(size_t count)
-    {
-        set_.resize(count);
-        set_.fill(false);
-        values_.resize(count);
-    }
-
-    DynamicBitarray<> set_;
-    std::vector<Value> values_;
-};
-
-template <typename Value> class FlatWireMap
-{
-  public:
-    FlatWireMap(const Context *ctx) : ctx_(ctx) { tiles_.resize(ctx->chip_info->tiles.size() + 1); }
-
-    std::pair<std::pair<WireId, Value *>, bool> emplace(WireId wire, const Value &value)
-    {
-        // Tile = -1 is for node wires.
-        size_t tile_index = wire.tile + 1;
-        auto &tile = tiles_.at(tile_index);
-
-        auto result = tile.emplace(ctx_, wire, value);
-        if (result.second) {
-            size_ += 1;
-        }
-        return std::make_pair(std::make_pair(wire, result.first), result.second);
-    }
-
-    const Value &at(WireId wire) const
-    {
-        const auto &tile = tiles_.at(wire.tile + 1);
-        return tile.at(wire);
-    }
-
-    size_t size() const { return size_; }
-
-    void clear()
-    {
-        for (auto &tile : tiles_) {
-            tile.clear();
-        }
-        size_ = 0;
-    }
-
-  private:
-    const Context *ctx_;
-    std::vector<FlatTileWireMap<Value>> tiles_;
-    size_t size_;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* FLAT_WIRE_MAP_H_ */
diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp
deleted file mode 100644
index 671b29f1c5..0000000000
--- a/fpga_interchange/fpga_interchange.cpp
+++ /dev/null
@@ -1,1153 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "fpga_interchange.h"
-#include <capnp/message.h>
-#include <sstream>
-#include <capnp/serialize.h>
-#include <kj/std/iostream.h>
-#include "PhysicalNetlist.capnp.h"
-#include "LogicalNetlist.capnp.h"
-#include "zlib.h"
-#include "frontend_base.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-static void write_message(::capnp::MallocMessageBuilder & message, const std::string &filename) {
-    kj::Array<capnp::word> words = messageToFlatArray(message);
-    kj::ArrayPtr<kj::byte> bytes = words.asBytes();
-
-    gzFile file = gzopen(filename.c_str(), "w");
-    NPNR_ASSERT(file != Z_NULL);
-
-    NPNR_ASSERT(gzwrite(file, &bytes[0], bytes.size()) == (int)bytes.size());
-    NPNR_ASSERT(gzclose(file) == Z_OK);
-}
-
-struct StringEnumerator {
-    std::vector<std::string> strings;
-    dict<std::string, size_t> string_to_index;
-
-    size_t get_index(const std::string &s) {
-        auto result = string_to_index.emplace(s, strings.size());
-        if(result.second) {
-            // This string was inserted, append.
-            strings.push_back(s);
-        }
-
-        return result.first->second;
-    }
-};
-
-static PhysicalNetlist::PhysNetlist::RouteBranch::Builder emit_branch(
-        const Context * ctx,
-        StringEnumerator * strings,
-        const dict<PipId, PlaceStrength> &pip_place_strength,
-        PipId pip,
-        PhysicalNetlist::PhysNetlist::RouteBranch::Builder branch) {
-    if(ctx->is_pip_synthetic(pip)) {
-        log_error("FPGA interchange should not emit synthetic pip %s\n", ctx->nameOfPip(pip));
-    }
-
-    const PipInfoPOD & pip_data = pip_info(ctx->chip_info, pip);
-    const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, pip);
-    const TileInstInfoPOD & tile = ctx->chip_info->tiles[pip.tile];
-
-    if(pip_data.site == -1) {
-        // This is a PIP
-        auto pip_obj = branch.getRouteSegment().initPip();
-        pip_obj.setTile(strings->get_index(tile.name.get()));
-
-        // FIXME: This might be broken for reverse bi-pips.  Re-visit this one.
-        //
-        // pip_data might need to mark that it is a reversed bi-pip, so the
-        // pip emission for the physical netlist would be:
-        //
-        //  wire0: dst_wire
-        //  wire1: src_wire
-        //  forward: false
-        //
-        IdString src_wire_name = IdString(tile_type.wire_data[pip_data.src_index].name);
-        IdString dst_wire_name = IdString(tile_type.wire_data[pip_data.dst_index].name);
-        pip_obj.setWire0(strings->get_index(src_wire_name.str(ctx)));
-        pip_obj.setWire1(strings->get_index(dst_wire_name.str(ctx)));
-        pip_obj.setForward(true);
-        pip_obj.setIsFixed(pip_place_strength.at(pip) >= STRENGTH_FIXED);
-
-        // If this is a pseudo PIP, get its name
-        if (pip_data.pseudo_cell_wires.size() != 0) {
-            for (int32_t wire_index : pip_data.pseudo_cell_wires) {
-                const TileWireInfoPOD &wire_data = tile_type.wire_data[wire_index];
-
-                if (wire_data.site == -1) {
-                    continue;
-                }
-
-                const SiteInstInfoPOD & site_data = site_inst_info(ctx->chip_info, pip.tile, wire_data.site);
-                std::string site_name = site_data.site_name.get();
-                int site_idx = strings->get_index(site_name);
-                pip_obj.setSite(site_idx);
-
-                // It is assumed that a pseudo PIP traverses one site only
-                break;
-            }
-        }
-
-        return branch;
-    } else {
-        BelId bel;
-        bel.tile = pip.tile;
-        bel.index = pip_data.bel;
-
-        const BelInfoPOD & bel_data = bel_info(ctx->chip_info, bel);
-
-        IdStringList bel_name = ctx->getBelName(bel);
-        NPNR_ASSERT(bel_name.size() == 2);
-        std::string site_and_type = bel_name[0].str(ctx);
-        auto pos = site_and_type.find_first_of('.');
-        NPNR_ASSERT(pos != std::string::npos);
-
-        std::string site_name = site_and_type.substr(0, pos);
-        int site_idx = strings->get_index(site_name);
-
-        if(bel_data.category == BEL_CATEGORY_LOGIC) {
-            // This is a psuedo site-pip.
-            auto in_bel_pin = branch.getRouteSegment().initBelPin();
-            WireId src_wire = ctx->getPipSrcWire(pip);
-            WireId dst_wire = ctx->getPipDstWire(pip);
-
-            NPNR_ASSERT(src_wire.index == bel_data.wires[pip_data.extra_data]);
-
-            IdString src_pin(bel_data.ports[pip_data.extra_data]);
-
-            IdString dst_pin;
-            for(IdString pin : ctx->getBelPins(bel)) {
-                if(ctx->getBelPinWire(bel, pin) == dst_wire) {
-                    NPNR_ASSERT(dst_pin == IdString());
-                    dst_pin = pin;
-                }
-            }
-
-            NPNR_ASSERT(src_pin != IdString());
-            NPNR_ASSERT(dst_pin != IdString());
-
-            int bel_idx = strings->get_index(bel_name[1].str(ctx));
-            in_bel_pin.setSite(site_idx);
-            in_bel_pin.setBel(bel_idx);
-            in_bel_pin.setPin(strings->get_index(src_pin.str(ctx)));
-
-            auto subbranch = branch.initBranches(1);
-            auto bel_pin_branch = subbranch[0];
-            auto out_bel_pin = bel_pin_branch.getRouteSegment().initBelPin();
-            out_bel_pin.setSite(site_idx);
-            out_bel_pin.setBel(bel_idx);
-            out_bel_pin.setPin(strings->get_index(dst_pin.str(ctx)));
-
-            return bel_pin_branch;
-        } else if(bel_data.category == BEL_CATEGORY_ROUTING) {
-            // This is a site-pip.
-            IdStringList pip_name = ctx->getPipName(pip);
-
-            auto site_pip = branch.getRouteSegment().initSitePIP();
-            site_pip.setSite(site_idx);
-            site_pip.setBel(strings->get_index(pip_name[1].str(ctx)));
-            site_pip.setPin(strings->get_index(pip_name[2].str(ctx)));
-            site_pip.setIsFixed(pip_place_strength.at(pip) >= STRENGTH_FIXED);
-
-            // FIXME: Mark inverter state.
-            // This is required for US/US+ inverters, because those inverters
-            // only have 1 input.
-
-            return branch;
-        } else {
-            NPNR_ASSERT(bel_data.category == BEL_CATEGORY_SITE_PORT);
-
-            // This is a site port.
-            const TileWireInfoPOD &tile_wire = tile_type.wire_data[pip_data.src_index];
-
-            int site_pin_idx = strings->get_index(bel_name[1].str(ctx));
-
-            if(tile_wire.site == -1) {
-                // This site port is routing -> site.
-                auto site_pin = branch.getRouteSegment().initSitePin();
-                site_pin.setSite(site_idx);
-                site_pin.setPin(site_pin_idx);
-
-                auto subbranch = branch.initBranches(1);
-                auto bel_pin_branch = subbranch[0];
-                auto bel_pin = bel_pin_branch.getRouteSegment().initBelPin();
-                bel_pin.setSite(site_idx);
-                bel_pin.setBel(site_pin_idx);
-                bel_pin.setPin(site_pin_idx);
-
-                return bel_pin_branch;
-            } else {
-                // This site port is site -> routing.
-                auto bel_pin = branch.getRouteSegment().initBelPin();
-                bel_pin.setSite(site_idx);
-                bel_pin.setBel(site_pin_idx);
-                bel_pin.setPin(site_pin_idx);
-
-                auto subbranch = branch.initBranches(1);
-                auto site_pin_branch = subbranch[0];
-                auto site_pin = site_pin_branch.getRouteSegment().initSitePin();
-                site_pin.setSite(site_idx);
-                site_pin.setPin(site_pin_idx);
-
-                return site_pin_branch;
-            }
-        }
-    }
-}
-
-
-static void init_bel_pin(
-        const Context * ctx,
-        StringEnumerator * strings,
-        const BelPin &bel_pin,
-        PhysicalNetlist::PhysNetlist::RouteBranch::Builder branch) {
-    if(ctx->is_bel_synthetic(bel_pin.bel)) {
-        log_error("FPGA interchange should not emit synthetic BEL pin %s/%s\n",
-                ctx->nameOfBel(bel_pin.bel), bel_pin.pin.c_str(ctx));
-    }
-
-    BelId bel = bel_pin.bel;
-    IdString pin_name = bel_pin.pin;
-
-    IdStringList bel_name = ctx->getBelName(bel);
-    NPNR_ASSERT(bel_name.size() == 2);
-    std::string site_and_type = bel_name[0].str(ctx);
-    auto pos = site_and_type.find_first_of('.');
-    NPNR_ASSERT(pos != std::string::npos);
-
-    std::string site_name = site_and_type.substr(0, pos);
-
-    const BelInfoPOD & bel_data = bel_info(ctx->chip_info, bel);
-    if(bel_data.category == BEL_CATEGORY_LOGIC) {
-        // This is a boring old logic BEL.
-        auto out_bel_pin = branch.getRouteSegment().initBelPin();
-
-        out_bel_pin.setSite(strings->get_index(site_name));
-        out_bel_pin.setBel(strings->get_index(bel_name[1].str(ctx)));
-        out_bel_pin.setPin(strings->get_index(pin_name.str(ctx)));
-    } else {
-        // This is a local site inverter.  This is represented with a
-        // $nextpnr_inv, and this BEL pin is the input to that inverter.
-        NPNR_ASSERT(bel_data.category == BEL_CATEGORY_ROUTING);
-        auto out_pip = branch.getRouteSegment().initSitePIP();
-
-        out_pip.setSite(strings->get_index(site_name));
-        out_pip.setBel(strings->get_index(bel_name[1].str(ctx)));
-        out_pip.setPin(strings->get_index(pin_name.str(ctx)));
-        out_pip.setIsInverting(true);
-    }
-}
-
-
-static void emit_net(
-        const Context * ctx,
-        StringEnumerator * strings,
-        const dict<WireId, std::vector<PipId>> &pip_downhill,
-        const dict<WireId, std::vector<BelPin>> &sinks,
-        pool<PipId> *pips,
-        const dict<PipId, PlaceStrength> &pip_place_strength,
-        WireId wire, PhysicalNetlist::PhysNetlist::RouteBranch::Builder branch) {
-    size_t number_branches = 0;
-
-    auto downhill_iter = pip_downhill.find(wire);
-    if(downhill_iter != pip_downhill.end()) {
-        number_branches += downhill_iter->second.size();
-    }
-
-    auto sink_iter = sinks.find(wire);
-    if(sink_iter != sinks.end()) {
-        number_branches += sink_iter->second.size();
-    }
-
-    size_t branch_index = 0;
-    auto branches = branch.initBranches(number_branches);
-
-    if(downhill_iter != pip_downhill.end()) {
-        const std::vector<PipId> & wire_pips = downhill_iter->second;
-        for(size_t i = 0; i < wire_pips.size(); ++i) {
-            PipId pip = wire_pips.at(i);
-            NPNR_ASSERT(pips->erase(pip) == 1);
-            PhysicalNetlist::PhysNetlist::RouteBranch::Builder leaf_branch = emit_branch(
-                ctx, strings, pip_place_strength, pip, branches[branch_index++]);
-
-            emit_net(ctx, strings, pip_downhill, sinks, pips,
-                    pip_place_strength,
-                    ctx->getPipDstWire(pip), leaf_branch);
-        }
-    }
-
-    if(sink_iter != sinks.end()) {
-        for(const auto bel_pin : sink_iter->second) {
-            auto leaf_branch = branches[branch_index++];
-            init_bel_pin(ctx, strings, bel_pin, leaf_branch);
-        }
-    }
-}
-
-// Given a site wire, find the source BEL pin.
-//
-// All site wires should have exactly 1 source BEL pin.
-//
-// FIXME: Consider making sure that wire_data.bel_pins[0] is always the
-// source BEL pin in the BBA generator.
-static BelPin find_source(const Context *ctx, WireId source_wire) {
-    if (source_wire.tile == -1) {
-        // Nodal wire, probably a constant, cannot have an associated bel pin
-        return BelPin();
-    }
-
-    const TileTypeInfoPOD & tile_type = loc_info(ctx->chip_info, source_wire);
-    const TileWireInfoPOD & wire_data = tile_type.wire_data[source_wire.index];
-
-    // Make sure this is a site wire, otherwise something odd is happening
-    // here.
-    if(wire_data.site == -1) {
-        return BelPin();
-    }
-
-    BelPin source_bel_pin;
-    for(const BelPin & bel_pin : ctx->getWireBelPins(source_wire)) {
-        if(ctx->getBelPinType(bel_pin.bel, bel_pin.pin) == PORT_OUT) {
-            // Synthetic BEL's (like connection to the VCC/GND network) are
-            // ignored here, because synthetic BEL's don't exists outside of
-            // the BBA.
-            if(ctx->is_bel_synthetic(bel_pin.bel)) {
-                continue;
-            }
-
-            NPNR_ASSERT(source_bel_pin.bel == BelId());
-            source_bel_pin = bel_pin;
-        }
-    }
-
-    NPNR_ASSERT(source_bel_pin.bel != BelId());
-    NPNR_ASSERT(source_bel_pin.pin != IdString());
-
-    return source_bel_pin;
-}
-
-// Initial a local signal source (usually VCC/GND).
-static PhysicalNetlist::PhysNetlist::RouteBranch::Builder init_local_source(
-        const Context *ctx,
-        StringEnumerator * strings,
-        PhysicalNetlist::PhysNetlist::RouteBranch::Builder source_branch,
-        PipId root,
-        const dict<PipId, PlaceStrength> &pip_place_strength,
-        WireId *root_wire) {
-    WireId source_wire = ctx->getPipSrcWire(root);
-    BelPin source_bel_pin = find_source(ctx, source_wire);
-    if(source_bel_pin.bel != BelId()) {
-        // This branch should first emit the BEL pin that is the source, followed
-        // by the pip that brings the source to the net.
-        init_bel_pin(ctx, strings, source_bel_pin, source_branch);
-
-        source_branch = source_branch.initBranches(1)[0];
-    }
-    *root_wire = ctx->getPipDstWire(root);
-    return emit_branch(ctx, strings, pip_place_strength, root, source_branch);
-}
-
-static void find_non_synthetic_edges(const Context * ctx, WireId root_wire,
-        const dict<WireId, std::vector<PipId>> &pip_downhill,
-        std::vector<PipId> *root_pips) {
-    std::vector<WireId> wires_to_expand;
-
-    wires_to_expand.push_back(root_wire);
-    while(!wires_to_expand.empty()) {
-        WireId wire = wires_to_expand.back();
-        wires_to_expand.pop_back();
-
-        auto downhill_iter = pip_downhill.find(wire);
-        if(downhill_iter == pip_downhill.end()) {
-            if(root_wire != wire) {
-                log_warning("Wire %s never entered the real fabric?\n",
-                        ctx->nameOfWire(wire));
-            }
-            continue;
-        }
-
-        for(PipId pip : pip_downhill.at(wire)) {
-            if(!ctx->is_pip_synthetic(pip)) {
-                // Stop following edges that are non-synthetic, they will be
-                // followed during emit_net
-                root_pips->push_back(pip);
-            } else {
-                // Continue to follow synthetic edges.
-                wires_to_expand.push_back(ctx->getPipDstWire(pip));
-            }
-        }
-    }
-}
-
-void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::string &filename) {
-    ::capnp::MallocMessageBuilder message;
-
-    PhysicalNetlist::PhysNetlist::Builder phys_netlist = message.initRoot<PhysicalNetlist::PhysNetlist>();
-
-    phys_netlist.setPart(ctx->get_part());
-
-    pool<IdString> placed_cells;
-    for(const auto & cell_pair : ctx->cells) {
-        const CellInfo & cell = *cell_pair.second;
-        if(cell.bel == BelId()) {
-            // This cell was not placed!
-            continue;
-        }
-        NPNR_ASSERT(cell_pair.first == cell.name);
-        NPNR_ASSERT(placed_cells.emplace(cell.name).second);
-    }
-
-    StringEnumerator strings;
-
-    IdString nextpnr_inv = ctx->id("$nextpnr_inv");
-
-    size_t number_placements = 0;
-    for(auto & cell_name : placed_cells) {
-        const CellInfo & cell = *ctx->cells.at(cell_name);
-
-        if(cell.type == nextpnr_inv) {
-            continue;
-        }
-
-        if(cell.bel == BelId()) {
-            continue;
-        }
-
-        if(!ctx->isBelLocationValid(cell.bel)) {
-            log_error("Cell '%s' is placed at BEL '%s', but this location is currently invalid.  Not writing physical netlist.\n",
-                    cell.name.c_str(ctx), ctx->nameOfBel(cell.bel));
-        }
-
-        if(ctx->is_bel_synthetic(cell.bel)) {
-            continue;
-        }
-
-        number_placements += 1;
-    }
-
-    std::vector<IdString> ports;
-
-    dict<std::string, std::string> sites;
-    auto placements = phys_netlist.initPlacements(number_placements);
-    auto placement_iter = placements.begin();
-
-    for(auto & cell_name : placed_cells) {
-        const CellInfo & cell = *ctx->cells.at(cell_name);
-
-        if(cell.type == nextpnr_inv) {
-            continue;
-        }
-
-        if(cell.bel == BelId()) {
-            continue;
-        }
-
-        NPNR_ASSERT(ctx->isBelLocationValid(cell.bel));
-
-        if(ctx->is_bel_synthetic(cell.bel)) {
-            continue;
-        }
-
-        IdStringList bel_name = ctx->getBelName(cell.bel);
-        NPNR_ASSERT(bel_name.size() == 2);
-        std::string site_and_type = bel_name[0].str(ctx);
-        auto pos = site_and_type.find_first_of('.');
-        NPNR_ASSERT(pos != std::string::npos);
-
-        std::string site_name = site_and_type.substr(0, pos);
-        std::string site_type = site_and_type.substr(pos + 1);
-
-        auto result = sites.emplace(site_name, site_type);
-        if(!result.second) {
-            NPNR_ASSERT(result.first->second == site_type);
-        }
-
-        auto placement = *placement_iter++;
-
-        placement.setCellName(strings.get_index(cell.name.str(ctx)));
-        if(ctx->io_port_types.count(cell.type)) {
-            // Always mark IO ports as type <PORT>.
-            placement.setType(strings.get_index("<PORT>"));
-            ports.push_back(cell.name);
-        } else {
-            placement.setType(strings.get_index(cell.type.str(ctx)));
-        }
-        placement.setSite(strings.get_index(site_name));
-
-        size_t bel_index = strings.get_index(bel_name[1].str(ctx));
-        placement.setBel(bel_index);
-        placement.setIsBelFixed(cell.belStrength >= STRENGTH_FIXED);
-        placement.setIsSiteFixed(cell.belStrength >= STRENGTH_FIXED);
-
-        if(!ctx->io_port_types.count(cell.type)) {
-            // Don't emit pin map for ports.
-            size_t pin_count = 0;
-            for(const auto & pin : cell.cell_bel_pins) {
-                if(cell.const_ports.count(pin.first)) {
-                    continue;
-                }
-                pin_count += pin.second.size();
-            }
-
-            auto pins = placement.initPinMap(pin_count);
-            auto pin_iter = pins.begin();
-
-            for(const auto & cell_to_bel_pins : cell.cell_bel_pins) {
-                if(cell.const_ports.count(cell_to_bel_pins.first)) {
-                    continue;
-                }
-
-                std::string cell_pin = cell_to_bel_pins.first.str(ctx);
-                size_t cell_pin_index = strings.get_index(cell_pin);
-
-                for(const auto & bel_pin : cell_to_bel_pins.second) {
-                    auto pin_output = *pin_iter++;
-                    pin_output.setCellPin(cell_pin_index);
-                    pin_output.setBel(bel_index);
-                    pin_output.setBelPin(strings.get_index(bel_pin.str(ctx)));
-                }
-            }
-        }
-    }
-
-    auto phys_cells = phys_netlist.initPhysCells(ports.size());
-    auto phys_cells_iter = phys_cells.begin();
-    for(IdString port : ports) {
-        auto phys_cell = *phys_cells_iter++;
-        phys_cell.setCellName(strings.get_index(port.str(ctx)));
-        phys_cell.setPhysType(PhysicalNetlist::PhysNetlist::PhysCellType::PORT);
-    }
-
-    int nets_to_remove = 0;
-    for(auto & net_pair : ctx->nets) {
-        auto &net = *net_pair.second;
-
-        // Remove disconnected nets that do not have any users
-        auto net_name = std::string(net.name.c_str(ctx));
-        if (net.users.empty() && net_name.rfind("$frontend$", 0) == 0)
-            nets_to_remove++;
-    }
-
-    auto nets = phys_netlist.initPhysNets(ctx->nets.size() - nets_to_remove);
-    auto net_iter = nets.begin();
-    for(auto & net_pair : ctx->nets) {
-        auto &net = *net_pair.second;
-
-        auto net_name = std::string(net.name.c_str(ctx));
-        if (net.users.empty() && net_name.rfind("$frontend$", 0) == 0)
-            continue;
-
-        const CellInfo *driver_cell = net.driver.cell;
-
-        auto net_out = *net_iter++;
-
-        // Handle GND and VCC nets.
-        if(driver_cell != nullptr && driver_cell->bel == ctx->get_gnd_bel()) {
-            IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-            net_out.setName(strings.get_index(gnd_net_name.str(ctx)));
-            net_out.setType(PhysicalNetlist::PhysNetlist::NetType::GND);
-        } else if(driver_cell != nullptr && driver_cell->bel == ctx->get_vcc_bel()) {
-            IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-            net_out.setName(strings.get_index(vcc_net_name.str(ctx)));
-            net_out.setType(PhysicalNetlist::PhysNetlist::NetType::VCC);
-        } else {
-            net_out.setName(strings.get_index(net.name.str(ctx)));
-        }
-
-        dict<WireId, BelPin> root_wires;
-        dict<WireId, std::vector<PipId>> pip_downhill;
-        pool<PipId> pips;
-
-        if (driver_cell != nullptr && driver_cell->bel != BelId() && ctx->isBelLocationValid(driver_cell->bel)) {
-            for(IdString bel_pin_name : driver_cell->cell_bel_pins.at(net.driver.port)) {
-                BelPin driver_bel_pin;
-                driver_bel_pin.bel = driver_cell->bel;
-                driver_bel_pin.pin = bel_pin_name;
-
-                WireId driver_wire = ctx->getBelPinWire(driver_bel_pin.bel, bel_pin_name);
-                if(driver_wire != WireId()) {
-                    root_wires[driver_wire] = driver_bel_pin;
-                }
-            }
-        }
-
-        dict<WireId, std::vector<BelPin>> sinks;
-        for(const auto &port_ref : net.users) {
-            if(port_ref.cell != nullptr && port_ref.cell->bel != BelId() && ctx->isBelLocationValid(port_ref.cell->bel)) {
-                auto pin_iter = port_ref.cell->cell_bel_pins.find(port_ref.port);
-                if(pin_iter == port_ref.cell->cell_bel_pins.end()) {
-                    log_warning("Cell %s port %s on net %s is legal, but has no BEL pins?\n",
-                            port_ref.cell->name.c_str(ctx),
-                            port_ref.port.c_str(ctx),
-                            net.name.c_str(ctx));
-                    continue;
-                }
-
-                for(IdString bel_pin_name : pin_iter->second) {
-                    BelPin sink_bel_pin;
-                    sink_bel_pin.bel = port_ref.cell->bel;
-                    sink_bel_pin.pin = bel_pin_name;
-
-                    WireId sink_wire = ctx->getBelPinWire(sink_bel_pin.bel, bel_pin_name);
-                    if(sink_wire != WireId()) {
-                        sinks[sink_wire].push_back(sink_bel_pin);
-                    }
-                }
-            }
-        }
-
-        dict<PipId, PlaceStrength> pip_place_strength;
-
-        for(auto &wire_pair : net.wires) {
-            WireId downhill_wire = wire_pair.first;
-            PipId pip = wire_pair.second.pip;
-            PlaceStrength strength = wire_pair.second.strength;
-            pip_place_strength[pip] = strength;
-            if(pip != PipId()) {
-                pips.emplace(pip);
-
-                WireId uphill_wire = ctx->getPipSrcWire(pip);
-                NPNR_ASSERT(downhill_wire != uphill_wire);
-                pip_downhill[uphill_wire].push_back(pip);
-            } else {
-                // This is a root wire.
-                NPNR_ASSERT(root_wires.count(downhill_wire));
-            }
-        }
-
-        std::vector<PipId> root_pips;
-        std::vector<WireId> roots_to_remove;
-
-        for(const auto & root_pair : root_wires) {
-            WireId root_wire = root_pair.first;
-            BelPin src_bel_pin = root_pair.second;
-
-            if(!ctx->is_bel_synthetic(src_bel_pin.bel)) {
-                continue;
-            }
-
-            roots_to_remove.push_back(root_wire);
-            find_non_synthetic_edges(ctx, root_wire, pip_downhill, &root_pips);
-        }
-
-        // Remove wires that have a synthetic root.
-        for(WireId wire : roots_to_remove) {
-            NPNR_ASSERT(root_wires.erase(wire) == 1);
-        }
-
-        auto sources = net_out.initSources(root_wires.size() + root_pips.size());
-        auto source_iter = sources.begin();
-
-        for(const auto & root_pair : root_wires) {
-            WireId root_wire = root_pair.first;
-            BelPin src_bel_pin = root_pair.second;
-
-            PhysicalNetlist::PhysNetlist::RouteBranch::Builder source_branch = *source_iter++;
-            init_bel_pin(ctx, &strings, src_bel_pin, source_branch);
-
-            emit_net(ctx, &strings, pip_downhill, sinks, &pips, pip_place_strength, root_wire, source_branch);
-        }
-
-        for(const PipId root : root_pips) {
-            PhysicalNetlist::PhysNetlist::RouteBranch::Builder source_branch = *source_iter++;
-
-            NPNR_ASSERT(pips.erase(root) == 1);
-            WireId root_wire;
-            source_branch = init_local_source(ctx, &strings, source_branch, root, pip_place_strength, &root_wire);
-            emit_net(ctx, &strings, pip_downhill, sinks, &pips, pip_place_strength, root_wire, source_branch);
-        }
-
-        // Any pips that were not part of a tree starting from the source are
-        // stubs.
-        size_t real_pips = 0;
-        for(PipId pip : pips) {
-            if(ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-            real_pips += 1;
-        }
-        auto stubs = net_out.initStubs(real_pips);
-        auto stub_iter = stubs.begin();
-        for(PipId pip : pips) {
-            if(ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-            emit_branch(ctx, &strings, pip_place_strength, pip, *stub_iter++);
-        }
-    }
-
-    auto site_instances = phys_netlist.initSiteInsts(sites.size());
-    auto site_inst_iter = site_instances.begin();
-    auto site_iter = sites.begin();
-    while(site_iter != sites.end()) {
-        NPNR_ASSERT(site_inst_iter != site_instances.end());
-
-        auto site_instance = *site_inst_iter;
-        site_instance.setSite(strings.get_index(site_iter->first));
-        site_instance.setType(strings.get_index(site_iter->second));
-
-        ++site_inst_iter;
-        ++site_iter;
-    }
-
-    auto str_list = phys_netlist.initStrList(strings.strings.size());
-    for(size_t i = 0; i < strings.strings.size(); ++i) {
-        str_list.set(i, strings.strings[i]);
-    }
-
-    write_message(message, filename);
-}
-
-struct LogicalNetlistImpl;
-
-size_t get_port_width(LogicalNetlist::Netlist::Port::Reader port) {
-    if(port.isBit()) {
-        return 1;
-    } else {
-        auto bus = port.getBus();
-        if(bus.getBusStart() < bus.getBusEnd()) {
-            return bus.getBusEnd() - bus.getBusStart() + 1;
-        } else {
-            return bus.getBusStart() - bus.getBusEnd() + 1;
-        }
-    }
-}
-
-struct PortKey {
-    PortKey(int32_t inst_idx, uint32_t port_idx) : inst_idx(inst_idx), port_idx(port_idx) {}
-    int32_t inst_idx;
-    uint32_t port_idx;
-
-    bool operator == (const PortKey &other) const {
-        return inst_idx == other.inst_idx && port_idx == other.port_idx;
-    }
-    unsigned int hash() const {
-        return mkhash(inst_idx, port_idx);
-    }
-};
-
-struct ModuleReader {
-    const LogicalNetlistImpl *root;
-
-    bool is_top;
-    LogicalNetlist::Netlist::CellInstance::Reader cell_inst;
-    LogicalNetlist::Netlist::Cell::Reader cell;
-    LogicalNetlist::Netlist::CellDeclaration::Reader cell_decl;
-
-    dict<int32_t, LogicalNetlist::Netlist::Net::Reader> net_indicies;
-    dict<int32_t, std::string> disconnected_nets;
-    dict<PortKey, std::vector<int32_t>> connections;
-
-    ModuleReader(const LogicalNetlistImpl *root,
-            LogicalNetlist::Netlist::CellInstance::Reader cell_inst, bool is_top);
-
-    size_t translate_port_index(LogicalNetlist::Netlist::PortInstance::Reader port_inst) const;
-};
-
-struct PortReader {
-    const ModuleReader * module;
-    size_t port_idx;
-};
-
-struct CellReader {
-    const ModuleReader * module;
-    size_t inst_idx;
-};
-
-struct NetReader {
-    NetReader(const ModuleReader * module, size_t net_idx) : module(module), net_idx(net_idx) {
-        scratch.resize(1);
-        scratch[0] = net_idx;
-    }
-
-    const ModuleReader * module;
-    size_t net_idx;
-    LogicalNetlist::Netlist::PropertyMap::Reader property_map;
-    std::vector<int32_t> scratch;
-};
-
-struct LogicalNetlistImpl
-{
-    LogicalNetlist::Netlist::Reader root;
-    std::vector<std::string> strings;
-
-    typedef const ModuleReader ModuleDataType;
-    typedef const PortReader& ModulePortDataType;
-    typedef const CellReader& CellDataType;
-    typedef const NetReader& NetnameDataType;
-    typedef const std::vector<int32_t>& BitVectorDataType;
-
-    LogicalNetlistImpl(LogicalNetlist::Netlist::Reader root) : root(root) {
-        strings.reserve(root.getStrList().size());
-        for(auto s : root.getStrList()) {
-            strings.push_back(s);
-        }
-    }
-
-    template <typename TFunc> void foreach_module(TFunc Func) const
-    {
-        auto top = root.getTopInst();
-        ModuleReader top_module(this, top, /*is_top=*/true);
-        Func(strings.at(top.getName()), top_module);
-    }
-
-    template <typename TFunc> void foreach_port(const ModuleReader &mod, TFunc Func) const
-    {
-        for(auto port_idx : mod.cell_decl.getPorts()) {
-            PortReader port_reader;
-            port_reader.module = &mod;
-            port_reader.port_idx = port_idx;
-            auto port = root.getPortList()[port_idx];
-            Func(strings.at(port.getName()), port_reader);
-        }
-    }
-
-    template <typename TFunc> void foreach_cell(const ModuleReader &mod, TFunc Func) const
-    {
-        for (auto cell_inst_idx : mod.cell.getInsts()) {
-            auto cell_inst = root.getInstList()[cell_inst_idx];
-            CellReader cell_reader;
-            cell_reader.module = &mod;
-            cell_reader.inst_idx = cell_inst_idx;
-            Func(strings.at(cell_inst.getName()), cell_reader);
-        }
-    }
-
-    template <typename TFunc> void foreach_netname(const ModuleReader &mod, TFunc Func) const
-    {
-        for(auto net_pair : mod.net_indicies) {
-            NetReader net_reader(&mod, net_pair.first);
-            auto net = net_pair.second;
-            net_reader.property_map = net.getPropMap();
-            Func(strings.at(net.getName()), net_reader);
-        }
-
-        for(auto net_pair : mod.disconnected_nets) {
-            NetReader net_reader(&mod, net_pair.first);
-            Func(net_pair.second, net_reader);
-        }
-    }
-
-    PortType get_port_type_for_direction(LogicalNetlist::Netlist::Direction dir) const {
-        if(dir == LogicalNetlist::Netlist::Direction::INPUT) {
-            return PORT_IN;
-        } else if (dir == LogicalNetlist::Netlist::Direction::INOUT) {
-            return PORT_INOUT;
-        } else if (dir == LogicalNetlist::Netlist::Direction::OUTPUT) {
-            return PORT_OUT;
-        } else {
-            NPNR_ASSERT_FALSE("invalid logical netlist port direction");
-        }
-    }
-
-    PortType get_port_dir(const PortReader &port_reader) const {
-        auto port = root.getPortList()[port_reader.port_idx];
-        auto dir = port.getDir();
-        return get_port_type_for_direction(dir);
-    }
-
-    const std::string &get_cell_type(const CellReader &cell) const {
-        auto cell_inst = root.getInstList()[cell.inst_idx];
-        auto cell_def = root.getCellList()[cell_inst.getCell()];
-        auto cell_decl = root.getCellDecls()[cell_def.getIndex()];
-        return strings.at(cell_decl.getName());
-    }
-
-
-    template <typename TFunc> void foreach_port_dir(const CellReader &cell, TFunc Func) const {
-        auto cell_inst = root.getInstList()[cell.inst_idx];
-        auto cell_def = root.getCellList()[cell_inst.getCell()];
-        auto cell_decl = root.getCellDecls()[cell_def.getIndex()];
-
-        for(auto port_idx : cell_decl.getPorts()) {
-            auto port = root.getPortList()[port_idx];
-            Func(strings.at(port.getName()), get_port_type_for_direction(port.getDir()));
-        }
-    }
-
-    template <typename TFunc> void foreach_prop_map(LogicalNetlist::Netlist::PropertyMap::Reader prop_map, TFunc Func) const {
-        for(auto prop : prop_map.getEntries()) {
-            if(prop.isTextValue()) {
-                Func(strings.at(prop.getKey()), Property(strings.at(prop.getTextValue())));
-            } else if(prop.isIntValue()) {
-                Func(strings.at(prop.getKey()), Property(prop.getIntValue()));
-            } else {
-                NPNR_ASSERT(prop.isBoolValue());
-                Func(strings.at(prop.getKey()), Property(prop.getBoolValue()));
-            }
-        }
-    }
-
-    template <typename TFunc> void foreach_attr(const ModuleReader &mod, TFunc Func) const {
-        if(mod.is_top) {
-            // Emit attribute "top" for top instance.
-            Func("top", Property(1));
-        }
-
-        auto cell_def = root.getCellList()[mod.cell_inst.getCell()];
-        auto cell_decl = root.getCellDecls()[cell_def.getIndex()];
-        foreach_prop_map(cell_decl.getPropMap(), Func);
-    }
-
-    template <typename TFunc> void foreach_attr(const CellReader &cell, TFunc Func) const {
-        auto cell_inst = root.getInstList()[cell.inst_idx];
-        foreach_prop_map(cell_inst.getPropMap(), Func);
-    }
-
-    template <typename TFunc> void foreach_attr(const PortReader &port_reader, TFunc Func) const {
-        auto port = root.getPortList()[port_reader.port_idx];
-        foreach_prop_map(port.getPropMap(), Func);
-    }
-
-    template <typename TFunc> void foreach_attr(const NetReader &net_reader, TFunc Func) const {
-        foreach_prop_map(net_reader.property_map, Func);
-    }
-
-    template <typename TFunc> void foreach_param(const CellReader &cell_reader, TFunc Func) const
-    {
-        auto cell_inst = root.getInstList()[cell_reader.inst_idx];
-        foreach_prop_map(cell_inst.getPropMap(), Func);
-    }
-
-    template <typename TFunc> void foreach_setting(const ModuleReader &obj, TFunc Func) const
-    {
-        foreach_prop_map(root.getPropMap(), Func);
-    }
-
-    template <typename TFunc> void foreach_port_conn(const CellReader &cell, TFunc Func) const
-    {
-        auto cell_inst = root.getInstList()[cell.inst_idx];
-        auto cell_def = root.getCellList()[cell_inst.getCell()];
-        auto cell_decl = root.getCellDecls()[cell_def.getIndex()];
-
-        for(auto port_idx : cell_decl.getPorts()) {
-            auto port = root.getPortList()[port_idx];
-            PortKey port_key(cell.inst_idx, port_idx);
-            const std::vector<int32_t> &connections = cell.module->connections.at(port_key);
-            Func(strings.at(port.getName()), connections);
-        }
-    }
-
-    int get_array_offset(const NetReader &port_reader) const
-    {
-        return 0;
-    }
-
-    bool is_array_upto(const NetReader &port_reader) const {
-        return false;
-    }
-
-    int get_array_offset(const PortReader &port_reader) const
-    {
-        auto port = root.getPortList()[port_reader.port_idx];
-        if(port.isBus()) {
-            auto bus = port.getBus();
-            return std::min(bus.getBusStart(), bus.getBusEnd());
-        } else {
-            return 0;
-        }
-    }
-
-    bool is_array_upto(const PortReader &port_reader) const {
-        auto port = root.getPortList()[port_reader.port_idx];
-        if(port.isBus()) {
-            auto bus = port.getBus();
-            return bus.getBusStart() < bus.getBusEnd();
-        } else {
-            return false;
-        }
-    }
-
-    const std::vector<int32_t> &get_port_bits(const PortReader &port_reader) const {
-        PortKey port_key(-1, port_reader.port_idx);
-        return port_reader.module->connections.at(port_key);
-    }
-
-    const std::vector<int32_t> &get_net_bits(const NetReader &net) const {
-        return net.scratch;
-    }
-
-    int get_vector_length(const std::vector<int32_t> &bits) const { return int(bits.size()); }
-
-    bool is_vector_bit_constant(const std::vector<int32_t> &bits, int i) const
-    {
-        // Note: This appears weird, but is correct.  This is because VCC/GND
-        // nets are not handled in frontend_base for FPGA interchange.
-        return false;
-    }
-
-    char get_vector_bit_constval(const std::vector<int32_t>&bits, int i) const
-    {
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-
-    int get_vector_bit_signal(const std::vector<int32_t>&bits, int i) const
-    {
-        return bits.at(i);
-    }
-};
-
-ModuleReader::ModuleReader(const LogicalNetlistImpl *root,
-            LogicalNetlist::Netlist::CellInstance::Reader cell_inst, bool is_top) :
-            root(root), is_top(is_top), cell_inst(cell_inst) {
-    cell = root->root.getCellList()[cell_inst.getCell()];
-    cell_decl = root->root.getCellDecls()[cell.getIndex()];
-
-    // Auto-assign all ports to a net index, and then re-assign based on the
-    // nets.
-    int net_idx = 2;
-
-    auto ports = root->root.getPortList();
-    for(auto port_idx : cell_decl.getPorts()) {
-        auto port = ports[port_idx];
-        size_t port_width = get_port_width(port);
-
-        PortKey port_key(-1, port_idx);
-        auto result = connections.emplace(port_key, std::vector<int32_t>());
-        NPNR_ASSERT(result.second);
-
-        std::vector<int32_t> & port_connections = result.first->second;
-        port_connections.resize(port_width);
-        for(size_t i = 0; i < port_width; ++i) {
-            port_connections[i] = net_idx++;
-        }
-    }
-
-    for(auto inst_idx : cell.getInsts()) {
-        auto inst = root->root.getInstList()[inst_idx];
-        auto inst_cell = root->root.getCellList()[inst.getCell()];
-        auto inst_cell_decl = root->root.getCellDecls()[inst_cell.getIndex()];
-
-        auto inst_ports = inst_cell_decl.getPorts();
-        for(auto inst_port_idx : inst_ports) {
-            PortKey port_key(inst_idx, inst_port_idx);
-            auto result = connections.emplace(port_key, std::vector<int32_t>());
-            NPNR_ASSERT(result.second);
-
-            auto inst_port = ports[inst_port_idx];
-            size_t port_width = get_port_width(inst_port);
-
-            std::vector<int32_t> & port_connections = result.first->second;
-            port_connections.resize(port_width);
-            for(size_t i = 0; i < port_width; ++i) {
-                port_connections[i] = net_idx++;
-            }
-        }
-    }
-
-    auto nets = cell.getNets();
-    for(size_t i = 0; i < nets.size(); ++i, ++net_idx) {
-        auto net = nets[i];
-        net_indicies[net_idx] = net;
-
-        for(auto port_inst : net.getPortInsts()) {
-            int32_t inst_idx = -1;
-            if(port_inst.isInst()) {
-                inst_idx = port_inst.getInst();
-            }
-
-            PortKey port_key(inst_idx, port_inst.getPort());
-            std::vector<int32_t> & port_connections = connections.at(port_key);
-
-            size_t port_idx = translate_port_index(port_inst);
-            port_connections.at(port_idx) = net_idx;
-        }
-    }
-
-    for(const auto & port_connections : connections) {
-        for(size_t i = 0; i < port_connections.second.size(); ++i) {
-            int32_t net_idx = port_connections.second[i];
-
-            auto iter = net_indicies.find(net_idx);
-            if(iter == net_indicies.end()) {
-                PortKey port_key = port_connections.first;
-                auto port = ports[port_key.port_idx];
-
-                // Disconnected outputs should be marked, so to be ignored when
-                // writing the physical netlist.
-                // Skipping these nets lets the basic frontend to assign a default
-                // name that starts with $frontend$.
-                if (port.getDir() == LogicalNetlist::Netlist::Direction::OUTPUT)
-                    continue;
-
-                disconnected_nets[net_idx] = stringf("%s.%d", root->strings.at(port.getName()).c_str(), i);
-            }
-        }
-    }
-}
-
-void FpgaInterchange::read_logical_netlist(Context * ctx, const std::string &filename) {
-    gzFile file = gzopen(filename.c_str(), "r");
-    NPNR_ASSERT(file != Z_NULL);
-
-    std::vector<uint8_t> output_data;
-    output_data.resize(4096);
-    std::stringstream sstream(std::ios_base::in | std::ios_base::out | std::ios_base::binary);
-    while(true) {
-        int ret = gzread(file, output_data.data(), output_data.size());
-        NPNR_ASSERT(ret >= 0);
-        if(ret > 0) {
-            sstream.write((const char*)output_data.data(), ret);
-            NPNR_ASSERT(sstream);
-        } else {
-            NPNR_ASSERT(ret == 0);
-            int error;
-            gzerror(file, &error);
-            NPNR_ASSERT(error == Z_OK);
-            break;
-        }
-    }
-
-    NPNR_ASSERT(gzclose(file) == Z_OK);
-
-    sstream.seekg(0);
-    kj::std::StdInputStream istream(sstream);
-    capnp::ReaderOptions reader_options;
-    reader_options.traversalLimitInWords = 32llu*1024llu*1024llu*1024llu;
-    capnp::InputStreamMessageReader message_reader(istream, reader_options);
-
-    LogicalNetlist::Netlist::Reader netlist = message_reader.getRoot<LogicalNetlist::Netlist>();
-    LogicalNetlistImpl netlist_reader(netlist);
-
-    GenericFrontend<LogicalNetlistImpl>(ctx, netlist_reader, /*split_io=*/false)();
-}
-
-size_t ModuleReader::translate_port_index(LogicalNetlist::Netlist::PortInstance::Reader port_inst) const {
-    LogicalNetlist::Netlist::Port::Reader port = root->root.getPortList()[port_inst.getPort()];
-    if(port_inst.getBusIdx().isSingleBit()) {
-        NPNR_ASSERT(port.isBit());
-        return 0;
-    } else {
-        NPNR_ASSERT(port.isBus());
-        uint32_t idx = port_inst.getBusIdx().getIdx();
-        size_t width = get_port_width(port);
-        NPNR_ASSERT(idx < width);
-        return width - 1 - idx;
-    }
-}
-
-NEXTPNR_NAMESPACE_END
-
diff --git a/fpga_interchange/fpga_interchange.h b/fpga_interchange/fpga_interchange.h
deleted file mode 100644
index 239b0e96f1..0000000000
--- a/fpga_interchange/fpga_interchange.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  The SymbiFlow Authors.
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef PHYSICAL_NETLIST_WRITER_H
-#define PHYSICAL_NETLIST_WRITER_H
-
-#include "nextpnr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct FpgaInterchange
-{
-    static void read_logical_netlist(Context *ctx, const std::string &filename);
-    static void write_physical_netlist(const Context *ctx, const std::string &filename);
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif
diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc
deleted file mode 100644
index eaff30e08f..0000000000
--- a/fpga_interchange/globals.cc
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-#include <queue>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace {
-
-struct GlobalVist
-{
-    PipId downhill = PipId();
-    int total_hops = 0;
-    int global_hops = 0;
-    bool operator<(const GlobalVist &other) const
-    {
-        return (total_hops < other.total_hops) ||
-               ((total_hops == other.total_hops) && (global_hops > other.global_hops));
-    }
-};
-
-// This is our main global routing implementation. It is used both to actually route globals; and also to discover if
-// global buffers have available short routes from their source for auto-placement
-static int route_global_arc(Context *ctx, NetInfo *net, store_index<PortRef> usr_idx, size_t phys_port_idx,
-                            int max_hops, bool dry_run)
-{
-    auto &usr = net->users.at(usr_idx);
-    WireId src = ctx->getNetinfoSourceWire(net);
-    WireId dest = ctx->getNetinfoSinkWire(net, usr, phys_port_idx);
-    if (dest == WireId()) {
-        if (dry_run)
-            return -1;
-        else
-            log_error("Arc %d.%d (%s.%s) of net %s has no sink wire!\n", usr_idx.idx(), int(phys_port_idx),
-                      ctx->nameOf(usr.cell), ctx->nameOf(usr.port), ctx->nameOf(net));
-    }
-    // Consider any existing routing put in place by the site router, etc
-    int start_hops = 0;
-    while (net->wires.count(dest) && dest != src) {
-        dest = ctx->getPipSrcWire(net->wires.at(dest).pip);
-        ++start_hops;
-    }
-    // The main BFS implementation
-    // Currently this is a backwards-BFS from sink to source (or pre-existing routing) that avoids general routing. It
-    // currently aims for minimum hops as a primary goal and maximum global resource usage as a secondary goal. More
-    // advanced heuristics will likely be needed for more complex situation
-    WireId startpoint;
-    GlobalVist best_visit;
-    std::queue<WireId> visit_queue;
-    dict<WireId, GlobalVist> visits;
-
-    visit_queue.push(dest);
-    visits[dest].downhill = PipId();
-    visits[dest].total_hops = start_hops;
-
-    while (!visit_queue.empty()) {
-        WireId cursor = visit_queue.front();
-        visit_queue.pop();
-        auto curr_visit = visits.at(cursor);
-        // We're now at least one layer deeper than a valid visit, any further exploration is futile
-        if (startpoint != WireId() && curr_visit.total_hops > best_visit.total_hops)
-            break;
-        // Valid end of routing
-        if ((cursor == src) || (ctx->getBoundWireNet(cursor) == net)) {
-            if (startpoint == WireId() || curr_visit < best_visit) {
-                startpoint = cursor;
-                best_visit = curr_visit;
-            }
-        }
-        // Explore uphill
-        for (auto pip : ctx->getPipsUphill(cursor)) {
-            if (!dry_run && !ctx->checkPipAvailForNet(pip, net))
-                continue;
-            WireId pip_src = ctx->getPipSrcWire(pip);
-            if (!dry_run && !ctx->checkWireAvail(pip_src) && ctx->getBoundWireNet(pip_src) != net)
-                continue;
-            auto cat = ctx->get_wire_category(pip_src);
-            if (!ctx->is_site_wire(pip_src) && cat == WIRE_CAT_GENERAL)
-                continue; // never allow general routing
-            GlobalVist next_visit;
-            next_visit.downhill = pip;
-            next_visit.total_hops = curr_visit.total_hops + 1;
-            if (max_hops != -1 && next_visit.total_hops > max_hops)
-                continue;
-            next_visit.global_hops = curr_visit.global_hops + ((cat == WIRE_CAT_GLOBAL) ? 1 : 0);
-            auto fnd_src = visits.find(pip_src);
-            if (fnd_src == visits.end() || next_visit < fnd_src->second) {
-                visit_queue.push(pip_src);
-                visits[pip_src] = next_visit;
-            }
-        }
-    }
-
-    if (startpoint == WireId())
-        return -1;
-    if (!dry_run) {
-        if (ctx->getBoundWireNet(startpoint) == nullptr)
-            ctx->bindWire(startpoint, net, STRENGTH_LOCKED);
-
-        WireId cursor = startpoint;
-        std::vector<PipId> pips;
-        // Create a list of pips on the routed path
-        while (true) {
-            PipId pip = visits.at(cursor).downhill;
-            if (pip == PipId())
-                break;
-            pips.push_back(pip);
-            cursor = ctx->getPipDstWire(pip);
-        }
-        // Reverse that list
-        std::reverse(pips.begin(), pips.end());
-        // Bind pips until we hit already-bound routing
-        for (PipId pip : pips) {
-            WireId dst = ctx->getPipDstWire(pip);
-            if (ctx->getBoundWireNet(dst) == net)
-                break;
-            ctx->bindPip(pip, net, STRENGTH_LOCKED);
-        }
-    }
-    return visits.at(startpoint).total_hops;
-}
-}; // namespace
-
-const GlobalCellPOD *Arch::global_cell_info(IdString cell_type) const
-{
-    for (const auto &glb_cell : chip_info->global_cells)
-        if (IdString(glb_cell.cell_type) == cell_type)
-            return &glb_cell;
-
-    return nullptr;
-}
-
-void Arch::place_globals()
-{
-    log_info("Placing globals...\n");
-
-    Context *ctx = getCtx();
-    IdString gnd_net_name(chip_info->constants->gnd_net_name);
-    IdString vcc_net_name(chip_info->constants->vcc_net_name);
-
-    // TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed
-    // before the GBs it drives
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        const GlobalCellPOD *glb_cell = global_cell_info(ci->type);
-        if (glb_cell == nullptr)
-            continue;
-        // Ignore if already placed
-        if (ci->bel != BelId())
-            continue;
-
-        for (const auto &pin : glb_cell->pins) {
-            if (!pin.guide_placement)
-                continue;
-
-            IdString pin_name(pin.name);
-            if (!ci->ports.count(pin_name))
-                continue;
-            auto &port = ci->ports.at(pin_name);
-
-            // only input ports currently used for placement guidance
-            if (port.type != PORT_IN)
-                continue;
-
-            NetInfo *net = port.net;
-            if (net == nullptr || net->name == gnd_net_name || net->name == vcc_net_name)
-                continue;
-            // Ignore if there is no driver; or the driver is not placed
-            if (net->driver.cell == nullptr || net->driver.cell->bel == BelId())
-                continue;
-
-            // TODO: substantial performance improvements are probably possible, although of questionable benefit given
-            // the low number of globals in a typical device...
-            BelId best_bel;
-            int shortest_distance = std::numeric_limits<int>::max();
-
-            for (auto bel : getBels()) {
-                int distance;
-                if (!isValidBelForCellType(ci->type, bel))
-                    continue;
-                if (!checkBelAvail(bel))
-                    continue;
-                // Provisionally place
-                bindBel(bel, ci, STRENGTH_WEAK);
-                if (!isBelLocationValid(bel))
-                    goto fail;
-                // Check distance
-                distance = route_global_arc(ctx, net, port.user_idx, 0, pin.max_hops, true);
-                if (distance != -1 && distance < shortest_distance) {
-                    best_bel = bel;
-                    shortest_distance = distance;
-                }
-            fail:
-                unbindBel(bel);
-            }
-
-            if (best_bel != BelId()) {
-                bindBel(best_bel, ci, STRENGTH_LOCKED);
-                log_info("    placed %s:%s at %s\n", ctx->nameOf(ci), ctx->nameOf(ci->type), ctx->nameOfBel(best_bel));
-                break;
-            }
-        }
-    }
-}
-
-void Arch::route_globals()
-{
-    log_info("Routing globals...\n");
-
-    Context *ctx = getCtx();
-    IdString gnd_net_name(chip_info->constants->gnd_net_name);
-    IdString vcc_net_name(chip_info->constants->vcc_net_name);
-
-    for (auto &cell : ctx->cells) {
-        CellInfo *ci = cell.second.get();
-        const GlobalCellPOD *glb_cell = global_cell_info(ci->type);
-        if (glb_cell == nullptr)
-            continue;
-        for (const auto &pin : glb_cell->pins) {
-            IdString pin_name(pin.name);
-            if (!ci->ports.count(pin_name))
-                continue;
-            auto &port = ci->ports.at(pin_name);
-
-            // TOOD: routing of input ports, too
-            // output ports are generally the first priority though
-            if (port.type != PORT_OUT)
-                continue;
-
-            NetInfo *net = port.net;
-            if (net == nullptr || net->name == gnd_net_name || net->name == vcc_net_name)
-                continue;
-
-            int total_sinks = 0;
-            int global_sinks = 0;
-
-            for (auto usr : net->users.enumerate()) {
-                for (size_t j = 0; j < ctx->getNetinfoSinkWireCount(net, usr.value); j++) {
-                    int result = route_global_arc(ctx, net, usr.index, j, pin.max_hops, false);
-                    ++total_sinks;
-                    if (result != -1)
-                        ++global_sinks;
-                    if ((result == -1) && pin.force_routing)
-                        log_error("Failed to route arc %d.%d (%s.%s) of net %s using dedicated global routing!\n",
-                                  usr.index.idx(), int(j), ctx->nameOf(usr.value.cell), ctx->nameOf(usr.value.port),
-                                  ctx->nameOf(net));
-                }
-            }
-
-            log_info("    routed %d/%d sinks of net %s using dedicated routing.\n", global_sinks, total_sinks,
-                     ctx->nameOf(net));
-        }
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/lookahead.capnp b/fpga_interchange/lookahead.capnp
deleted file mode 100644
index e69c165d87..0000000000
--- a/fpga_interchange/lookahead.capnp
+++ /dev/null
@@ -1,61 +0,0 @@
-@0x97c69817483d9dea;
-
-using Cxx = import "/capnp/c++.capnp";
-$Cxx.namespace("lookahead_storage");
-
-using DelayType = Int32;
-
-struct TypeWireId {
-    type  @0: Int32;
-    index @1: Int32;
-}
-
-struct TypeWirePair {
-    src @0 : TypeWireId;
-    dst @1 : TypeWireId;
-}
-
-struct InputSiteWireCost {
-    routeTo @0 : TypeWireId;
-    cost    @1 : DelayType;
-}
-
-struct InputSiteWireCostMap {
-    key   @0 : TypeWireId;
-    value @1 : List(InputSiteWireCost);
-}
-
-struct OutputSiteWireCostMap {
-    key               @0 : TypeWireId;
-    cheapestRouteFrom @1 : TypeWireId;
-    cost              @2 : DelayType;
-}
-
-struct SiteToSiteCostMap {
-    key  @0 : TypeWirePair;
-    cost @1 : DelayType;
-}
-
-struct CostMapEntry {
-    key     @0 : TypeWirePair;
-    data    @1 : List(DelayType);
-    xDim    @2 : UInt32;
-    yDim    @3 : UInt32;
-    xOffset @4 : UInt32;
-    yOffset @5 : UInt32;
-    penalty @6 : DelayType;
-}
-
-struct CostMap {
-    costMap @0 : List(CostMapEntry);
-}
-
-struct Lookahead {
-
-    chipdbHash      @0 : Text;
-    inputSiteWires  @1 : List(InputSiteWireCostMap);
-    outputSiteWires @2 : List(OutputSiteWireCostMap);
-    siteToSiteCost  @3 : List(SiteToSiteCostMap);
-    costMap         @4 : CostMap;
-}
-
diff --git a/fpga_interchange/lookahead.cc b/fpga_interchange/lookahead.cc
deleted file mode 100644
index f1cb13e1c4..0000000000
--- a/fpga_interchange/lookahead.cc
+++ /dev/null
@@ -1,1543 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "lookahead.h"
-
-#include <boost/filesystem.hpp>
-#include <boost/safe_numerics/safe_integer.hpp>
-#include <capnp/message.h>
-#include <capnp/serialize.h>
-#include <kj/filesystem.h>
-#include <kj/std/iostream.h>
-#include <queue>
-#include <sstream>
-#include <zlib.h>
-
-#include "context.h"
-#include "flat_wire_map.h"
-#include "log.h"
-#include "sampler.h"
-#include "scope_lock.h"
-
-#if defined(NEXTPNR_USE_TBB)
-#include <tbb/parallel_for_each.h>
-#endif
-
-NEXTPNR_NAMESPACE_BEGIN
-
-static constexpr size_t kNumberSamples = 4;
-static constexpr int32_t kMaxExploreDist = 20;
-
-// Initial only explore with a depth of this.
-static constexpr int32_t kInitialExploreDepth = 30;
-
-struct RoutingNode
-{
-    WireId wire_to_expand;
-    delay_t cost;
-    int32_t depth;
-
-    bool operator<(const RoutingNode &other) const { return cost < other.cost; }
-};
-
-struct PipAndCost
-{
-    PipId upstream_pip;
-    delay_t cost_from_src;
-    int32_t depth;
-};
-
-static void expand_input(const Context *ctx, WireId input_wire, dict<TypeWireId, delay_t> *input_costs)
-{
-    pool<WireId> seen;
-    std::priority_queue<RoutingNode> to_expand;
-
-    RoutingNode initial;
-    initial.cost = 0;
-    initial.wire_to_expand = input_wire;
-
-    to_expand.push(initial);
-
-    while (!to_expand.empty()) {
-        RoutingNode node = to_expand.top();
-        to_expand.pop();
-
-        auto result = seen.emplace(node.wire_to_expand);
-        if (!result.second) {
-            // We've already done an expansion at this wire.
-            continue;
-        }
-
-        for (PipId pip : ctx->getPipsUphill(node.wire_to_expand)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-            WireId new_wire = ctx->getPipSrcWire(pip);
-            if (new_wire == WireId()) {
-                continue;
-            }
-
-            RoutingNode next_node;
-            next_node.wire_to_expand = new_wire;
-            next_node.cost = node.cost + ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(new_wire).maxDelay();
-
-            if (ctx->is_site_port(pip)) {
-                // Done with expansion, record the path if cheaper.
-                // Only the first path to each wire will be the cheapest.
-
-                // Get local tile wire at pip dest. Using getPipSrcWire may
-                // return a node wire, which is not correct here.
-                TypeWireId route_to;
-                route_to.type = ctx->chip_info->tiles[pip.tile].type;
-                route_to.index = loc_info(ctx->chip_info, pip).pip_data[pip.index].src_index;
-                if (route_to.index >= 0) {
-                    auto result = input_costs->emplace(route_to, next_node.cost);
-                    if (!result.second && result.first->second > next_node.cost) {
-                        result.first->second = next_node.cost;
-                    }
-                }
-            } else {
-                to_expand.push(next_node);
-            }
-        }
-    }
-}
-
-static void update_site_to_site_costs(const Context *ctx, WireId first_wire, const dict<WireId, PipAndCost> &best_path,
-                                      dict<TypeWirePair, delay_t> *site_to_site_cost)
-{
-    for (auto &best_pair : best_path) {
-        WireId last_wire = best_pair.first;
-        TypeWirePair pair;
-        pair.dst = TypeWireId(ctx, last_wire);
-
-        PipAndCost pip_and_cost = best_pair.second;
-        delay_t cost_from_src = pip_and_cost.cost_from_src;
-
-        WireId cursor;
-        do {
-            cursor = ctx->getPipSrcWire(pip_and_cost.upstream_pip);
-
-            pair.src = TypeWireId(ctx, cursor);
-
-            delay_t cost = cost_from_src;
-
-            // Only use the delta cost from cursor to last_wire, not the full
-            // cost from first_wire to last_wire.
-            if (cursor != first_wire) {
-                pip_and_cost = best_path.at(cursor);
-                cost -= pip_and_cost.cost_from_src;
-            }
-
-            NPNR_ASSERT(cost >= 0);
-
-            auto cost_result = site_to_site_cost->emplace(pair, cost);
-            if (!cost_result.second) {
-                // Update point to point cost if cheaper.
-                if (cost_result.first->second > cost) {
-                    cost_result.first->second = cost;
-                }
-            }
-        } while (cursor != first_wire);
-    }
-}
-
-static void expand_output(const Context *ctx, WireId output_wire, Lookahead::OutputSiteWireCost *output_cost,
-                          dict<TypeWirePair, delay_t> *site_to_site_cost)
-{
-    pool<WireId> seen;
-    std::priority_queue<RoutingNode> to_expand;
-
-    RoutingNode initial;
-    initial.cost = 0;
-    initial.wire_to_expand = output_wire;
-
-    to_expand.push(initial);
-
-    dict<WireId, PipAndCost> best_path;
-
-    while (!to_expand.empty()) {
-        RoutingNode node = to_expand.top();
-        to_expand.pop();
-
-        auto result = seen.emplace(node.wire_to_expand);
-        if (!result.second) {
-            // We've already done an expansion at this wire.
-            continue;
-        }
-
-        for (PipId pip : ctx->getPipsDownhill(node.wire_to_expand)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-            WireId new_wire = ctx->getPipDstWire(pip);
-            if (new_wire == WireId()) {
-                continue;
-            }
-
-            RoutingNode next_node;
-            next_node.wire_to_expand = new_wire;
-            next_node.cost = node.cost + ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(new_wire).maxDelay();
-
-            if (ctx->is_site_port(pip)) {
-                // Done with expansion, record the path if cheaper.
-
-                // Get local tile wire at pip dest. Using getPipDstWire may
-                // return a node wire, which is not correct here.
-                TypeWireId route_from;
-                route_from.type = ctx->chip_info->tiles[pip.tile].type;
-                route_from.index = loc_info(ctx->chip_info, pip).pip_data[pip.index].dst_index;
-                if (route_from.index != -1 && output_cost != nullptr && next_node.cost < output_cost->cost) {
-                    output_cost->cost = next_node.cost;
-                    output_cost->cheapest_route_from = route_from;
-                }
-            } else {
-                to_expand.push(next_node);
-
-                auto result = best_path.emplace(new_wire, PipAndCost());
-                PipAndCost &pip_and_cost = result.first->second;
-                if (result.second || pip_and_cost.cost_from_src > next_node.cost) {
-                    pip_and_cost.upstream_pip = pip;
-                    pip_and_cost.cost_from_src = next_node.cost;
-                }
-            }
-        }
-    }
-
-    update_site_to_site_costs(ctx, output_wire, best_path, site_to_site_cost);
-}
-
-static void expand_input_type(const Context *ctx, DeterministicRNG *rng, const Sampler &tiles_of_type,
-                              TypeWireId input_wire, std::vector<Lookahead::InputSiteWireCost> *input_costs)
-{
-    dict<TypeWireId, delay_t> input_costs_map;
-    for (size_t region = 0; region < tiles_of_type.number_of_regions(); ++region) {
-        size_t tile = tiles_of_type.get_sample_from_region(region, [rng]() -> int32_t { return rng->rng(); });
-
-        NPNR_ASSERT(ctx->chip_info->tiles[tile].type == input_wire.type);
-        WireId wire = canonical_wire(ctx->chip_info, tile, input_wire.index);
-
-        expand_input(ctx, wire, &input_costs_map);
-    }
-
-    input_costs->clear();
-    input_costs->reserve(input_costs_map.size());
-    for (const auto &input_pair : input_costs_map) {
-        input_costs->emplace_back();
-        auto &input_cost = input_costs->back();
-        input_cost.route_to = input_pair.first;
-        input_cost.cost = input_pair.second;
-    }
-}
-
-struct DelayStorage
-{
-    dict<TypeWirePair, dict<std::pair<int32_t, int32_t>, delay_t>> storage;
-    int32_t max_explore_depth;
-};
-
-static bool has_multiple_inputs(const Context *ctx, WireId wire)
-{
-    size_t pip_count = 0;
-    for (PipId pip : ctx->getPipsUphill(wire)) {
-        (void)pip;
-        pip_count += 1;
-    }
-
-    return pip_count > 1;
-}
-
-static void update_results(const Context *ctx, const FlatWireMap<PipAndCost> &best_path, WireId src_wire,
-                           WireId sink_wire, DelayStorage *storage)
-{
-    TypeWireId src_wire_type(ctx, src_wire);
-
-    int src_tile;
-    if (src_wire.tile == -1) {
-        src_tile = ctx->chip_info->nodes[src_wire.index].tile_wires[0].tile;
-    } else {
-        src_tile = src_wire.tile;
-    }
-
-    int32_t src_x, src_y;
-    ctx->get_tile_x_y(src_tile, &src_x, &src_y);
-
-    TypeWirePair wire_pair;
-    wire_pair.src = src_wire_type;
-
-    // The first couple wires from the site pip are usually boring, don't record
-    // them.
-    bool out_of_infeed = false;
-
-    // Starting from end of result, walk backwards and record the path into
-    // the delay storage.
-    WireId cursor = sink_wire;
-    pool<WireId> seen;
-    while (cursor != src_wire) {
-        // No loops allowed in routing!
-        auto result = seen.emplace(cursor);
-        NPNR_ASSERT(result.second);
-
-        if (!out_of_infeed && has_multiple_inputs(ctx, cursor)) {
-            out_of_infeed = true;
-        }
-
-        TypeWireId dst_wire_type(ctx, cursor);
-        wire_pair.dst = dst_wire_type;
-
-        int dst_tile;
-        if (cursor.tile == -1) {
-            dst_tile = ctx->chip_info->nodes[cursor.index].tile_wires[0].tile;
-        } else {
-            dst_tile = cursor.tile;
-        }
-        int32_t dst_x;
-        int32_t dst_y;
-        ctx->get_tile_x_y(dst_tile, &dst_x, &dst_y);
-
-        std::pair<int32_t, int32_t> dx_dy;
-        dx_dy.first = dst_x - src_x;
-        dx_dy.second = dst_y - src_y;
-
-        const PipAndCost &pip_and_cost = best_path.at(cursor);
-        if (out_of_infeed) {
-            auto &delta_data = storage->storage[wire_pair];
-            auto result2 = delta_data.emplace(dx_dy, pip_and_cost.cost_from_src);
-            if (!result2.second) {
-                if (result2.first->second > pip_and_cost.cost_from_src) {
-                    result2.first->second = pip_and_cost.cost_from_src;
-                }
-            }
-        }
-
-        cursor = ctx->getPipSrcWire(pip_and_cost.upstream_pip);
-    }
-}
-
-static void expand_routing_graph_from_wire(const Context *ctx, WireId first_wire, FlatWireMap<PipAndCost> *best_path,
-                                           DelayStorage *storage)
-{
-    pool<WireId> seen;
-    std::priority_queue<RoutingNode> to_expand;
-
-    int src_tile;
-    if (first_wire.tile == -1) {
-        src_tile = ctx->chip_info->nodes[first_wire.index].tile_wires[0].tile;
-    } else {
-        src_tile = first_wire.tile;
-    }
-
-    int32_t src_x, src_y;
-    ctx->get_tile_x_y(src_tile, &src_x, &src_y);
-
-    RoutingNode initial;
-    initial.cost = 0;
-    initial.wire_to_expand = first_wire;
-    initial.depth = 0;
-
-    to_expand.push(initial);
-
-    best_path->clear();
-    size_t skip_count = 0;
-
-    while (!to_expand.empty()) {
-        RoutingNode node = to_expand.top();
-        to_expand.pop();
-
-        auto result = seen.emplace(node.wire_to_expand);
-        if (!result.second) {
-            // We've already done an expansion at this wire.
-            skip_count += 1;
-            continue;
-        }
-
-        bool has_site_pip = false;
-        for (PipId pip : ctx->getPipsDownhill(node.wire_to_expand)) {
-            if (ctx->is_pip_synthetic(pip)) {
-                continue;
-            }
-
-            // Don't expand edges that are site pips, but do record how we
-            // got to the pip before the site pip!
-            if (ctx->is_site_port(pip)) {
-                has_site_pip = true;
-                continue;
-            }
-
-            WireId new_wire = ctx->getPipDstWire(pip);
-            if (new_wire == WireId()) {
-                continue;
-            }
-
-            RoutingNode next_node;
-            next_node.wire_to_expand = new_wire;
-            next_node.cost = node.cost + ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(new_wire).maxDelay();
-            next_node.depth = node.depth + 1;
-
-            // Record best path.
-            PipAndCost pip_and_cost;
-            pip_and_cost.upstream_pip = pip;
-            pip_and_cost.cost_from_src = next_node.cost;
-            pip_and_cost.depth = next_node.depth;
-            auto result = best_path->emplace(new_wire, pip_and_cost);
-            bool is_best_path = true;
-            if (!result.second) {
-                if (result.first.second->cost_from_src > next_node.cost) {
-                    result.first.second->cost_from_src = next_node.cost;
-                    result.first.second->upstream_pip = pip;
-                    result.first.second->depth = next_node.depth;
-                } else {
-                    is_best_path = false;
-                }
-            }
-
-            Loc dst = ctx->getPipLocation(pip);
-            int32_t dst_x = dst.x;
-            int32_t dst_y = dst.y;
-            if (is_best_path && std::abs(dst_x - src_x) < kMaxExploreDist &&
-                std::abs(dst_y - src_y) < kMaxExploreDist && next_node.depth < storage->max_explore_depth) {
-                to_expand.push(next_node);
-            }
-        }
-
-        if (has_site_pip) {
-            update_results(ctx, *best_path, first_wire, node.wire_to_expand, storage);
-        }
-    }
-}
-
-static bool has_multiple_outputs(const Context *ctx, WireId wire)
-{
-    size_t pip_count = 0;
-    for (PipId pip : ctx->getPipsDownhill(wire)) {
-        (void)pip;
-        pip_count += 1;
-    }
-
-    return pip_count > 1;
-}
-
-static void expand_routing_graph(const Context *ctx, DeterministicRNG *rng, const Sampler &tiles_of_type,
-                                 TypeWireId wire_type, pool<TypeWireSet> *types_explored, DelayStorage *storage,
-                                 pool<TypeWireId> *types_deferred, FlatWireMap<PipAndCost> *best_path)
-{
-    pool<TypeWireSet> new_types_explored;
-
-    for (size_t region = 0; region < tiles_of_type.number_of_regions(); ++region) {
-        size_t tile = tiles_of_type.get_sample_from_region(region, [rng]() -> int32_t { return rng->rng(); });
-
-        NPNR_ASSERT(ctx->chip_info->tiles[tile].type == wire_type.type);
-
-        WireId wire = canonical_wire(ctx->chip_info, tile, wire_type.index);
-        TypeWireSet wire_set(ctx, wire);
-
-        if (!has_multiple_outputs(ctx, wire)) {
-            types_deferred->emplace(wire_type);
-            continue;
-        }
-
-        new_types_explored.emplace(wire_set);
-
-        expand_routing_graph_from_wire(ctx, wire, best_path, storage);
-    }
-
-    for (const TypeWireSet &new_wire_set : new_types_explored) {
-        types_explored->emplace(new_wire_set);
-    }
-}
-
-static WireId follow_pip_chain(const Context *ctx, WireId wire, delay_t *delay_out)
-{
-    delay_t delay = 0;
-    WireId cursor = wire;
-    while (true) {
-        WireId next;
-        size_t pip_count = 0;
-        delay_t next_delay = delay;
-        for (PipId pip : ctx->getPipsDownhill(cursor)) {
-            pip_count += 1;
-            next = ctx->getPipDstWire(pip);
-            next_delay += ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(next).maxDelay();
-        }
-
-        if (pip_count > 1) {
-            *delay_out = delay;
-            return cursor;
-        }
-
-        if (next == WireId()) {
-            return WireId();
-        }
-
-        delay = next_delay;
-
-        cursor = next;
-    }
-
-    // Unreachable?
-    NPNR_ASSERT(false);
-}
-
-static WireId follow_pip_chain_target(const Context *ctx, WireId wire, WireId target, delay_t *delay_out)
-{
-    delay_t delay = 0;
-    WireId cursor = wire;
-    while (cursor != target) {
-        WireId next;
-        size_t pip_count = 0;
-        delay_t next_delay = delay;
-        for (PipId pip : ctx->getPipsDownhill(cursor)) {
-            pip_count += 1;
-            next = ctx->getPipDstWire(pip);
-            next_delay += ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(next).maxDelay();
-        }
-
-        if (pip_count > 1) {
-            *delay_out = delay;
-            return cursor;
-        }
-
-        if (next == WireId()) {
-            return WireId();
-        }
-
-        delay = next_delay;
-
-        cursor = next;
-    }
-
-    *delay_out = delay;
-    return cursor;
-}
-
-static WireId follow_pip_chain_up(const Context *ctx, WireId wire, delay_t *delay_out)
-{
-    delay_t delay = 0;
-    WireId cursor = wire;
-    while (true) {
-        WireId next;
-        size_t pip_count = 0;
-        delay_t next_delay = delay;
-        for (PipId pip : ctx->getPipsUphill(cursor)) {
-            pip_count += 1;
-            next = ctx->getPipSrcWire(pip);
-            next_delay += ctx->getPipDelay(pip).maxDelay() + ctx->getWireDelay(next).maxDelay();
-        }
-
-        if (pip_count > 1) {
-            *delay_out = delay;
-            return cursor;
-        }
-
-        if (next == WireId()) {
-            return WireId();
-        }
-
-        delay = next_delay;
-
-        cursor = next;
-    }
-
-    // Unreachable?
-    NPNR_ASSERT(false);
-}
-
-static void expand_deferred_routing_graph(const Context *ctx, DeterministicRNG *rng, const Sampler &tiles_of_type,
-                                          TypeWireId wire_type, pool<TypeWireSet> *types_explored,
-                                          DelayStorage *storage, FlatWireMap<PipAndCost> *best_path)
-{
-    pool<TypeWireSet> new_types_explored;
-
-    for (size_t region = 0; region < tiles_of_type.number_of_regions(); ++region) {
-        size_t tile = tiles_of_type.get_sample_from_region(region, [rng]() -> int32_t { return rng->rng(); });
-
-        NPNR_ASSERT(ctx->chip_info->tiles[tile].type == wire_type.type);
-
-        WireId wire = canonical_wire(ctx->chip_info, tile, wire_type.index);
-        TypeWireSet wire_set(ctx, wire);
-        if (types_explored->count(wire_set)) {
-            // Check if this wire set has been expanded.
-            continue;
-        }
-
-        delay_t delay;
-        WireId routing_wire = follow_pip_chain(ctx, wire, &delay);
-
-        // This wire doesn't go anywhere!
-        if (routing_wire == WireId()) {
-            continue;
-        }
-
-        TypeWireSet routing_wire_set(ctx, routing_wire);
-        if (types_explored->count(routing_wire_set)) {
-            continue;
-        }
-
-        new_types_explored.emplace(wire_set);
-        expand_routing_graph_from_wire(ctx, wire, best_path, storage);
-    }
-
-    for (const TypeWireSet &new_wire_set : new_types_explored) {
-        types_explored->emplace(new_wire_set);
-    }
-}
-
-static void expand_output_type(const Context *ctx, DeterministicRNG *rng, const Sampler &tiles_of_type,
-                               TypeWireId output_wire, Lookahead::OutputSiteWireCost *output_cost,
-                               dict<TypeWirePair, delay_t> *site_to_site_cost)
-{
-    for (size_t region = 0; region < tiles_of_type.number_of_regions(); ++region) {
-        size_t tile = tiles_of_type.get_sample_from_region(region, [rng]() -> int32_t { return rng->rng(); });
-
-        NPNR_ASSERT(ctx->chip_info->tiles[tile].type == output_wire.type);
-        WireId wire = canonical_wire(ctx->chip_info, tile, output_wire.index);
-
-        expand_output(ctx, wire, output_cost, site_to_site_cost);
-    }
-}
-
-static constexpr bool kWriteLookaheadCsv = false;
-
-void write_lookahead_csv(const Context *ctx, const DelayStorage &all_tiles_storage)
-{
-    FILE *lookahead_data = fopen("lookahead.csv", "w");
-    NPNR_ASSERT(lookahead_data != nullptr);
-    fprintf(lookahead_data, "src_type,src_wire,dest_type,dest_wire,delta_x,delta_y,delay\n");
-    for (const auto &type_pair : all_tiles_storage.storage) {
-        auto &src_wire_type = type_pair.first.src;
-        auto &src_type_data = ctx->chip_info->tile_types[src_wire_type.type];
-        IdString src_type(src_type_data.name);
-        IdString src_wire(src_type_data.wire_data[src_wire_type.index].name);
-
-        auto &dst_wire_type = type_pair.first.dst;
-        auto &dst_type_data = ctx->chip_info->tile_types[dst_wire_type.type];
-        IdString dst_type(dst_type_data.name);
-        IdString dst_wire(dst_type_data.wire_data[dst_wire_type.index].name);
-
-        for (const auto &delta_pair : type_pair.second) {
-            fprintf(lookahead_data, "%s,%s,%s,%s,%d,%d,%d\n", src_type.c_str(ctx), src_wire.c_str(ctx),
-                    dst_type.c_str(ctx), dst_wire.c_str(ctx), delta_pair.first.first, delta_pair.first.second,
-                    delta_pair.second);
-        }
-    }
-
-    fclose(lookahead_data);
-}
-
-// Storage for tile type expansion for lookahead.
-struct ExpandLocals
-{
-    virtual ~ExpandLocals() {}
-    const std::vector<Sampler> *tiles_of_type;
-    DeterministicRNG *rng;
-    FlatWireMap<PipAndCost> *best_path;
-    DelayStorage *storage;
-    pool<TypeWireSet> *explored;
-    pool<TypeWireId> *deferred;
-
-    virtual void lock() {}
-    virtual void unlock() {}
-    virtual void copy_back(int32_t tile_type) {}
-};
-
-// Do tile type expansion for 1 tile.
-static void expand_tile_type(const Context *ctx, int32_t tile_type, ExpandLocals *locals)
-{
-    auto &type_data = ctx->chip_info->tile_types[tile_type];
-    if (ctx->verbose) {
-        ScopeLock<ExpandLocals> lock(locals);
-        log_info("Expanding all wires in type %s\n", IdString(type_data.name).c_str(ctx));
-    }
-
-    auto &tile_sampler = (*locals->tiles_of_type)[tile_type];
-    for (size_t wire_index = 0; wire_index < type_data.wire_data.size(); ++wire_index) {
-        auto &wire_data = type_data.wire_data[wire_index];
-        if (wire_data.site != -1) {
-            // Skip site wires
-            continue;
-        }
-
-        if (ctx->debug) {
-            ScopeLock<ExpandLocals> lock(locals);
-            log_info("Expanding wire %s in type %s (%d/%zu, seen %zu types, deferred %zu types)\n",
-                     IdString(wire_data.name).c_str(ctx), IdString(type_data.name).c_str(ctx), tile_type,
-                     ctx->chip_info->tile_types.size(), locals->explored->size(), locals->deferred->size());
-        }
-
-        TypeWireId wire;
-        wire.type = tile_type;
-        wire.index = wire_index;
-
-        expand_routing_graph(ctx, locals->rng, tile_sampler, wire, locals->explored, locals->storage, locals->deferred,
-                             locals->best_path);
-    }
-
-    locals->copy_back(tile_type);
-}
-
-// Function that does all tile expansions serially.
-static void expand_tile_type_serial(const Context *ctx, const std::vector<int32_t> &tile_types,
-                                    const std::vector<Sampler> &tiles_of_type, DeterministicRNG *rng,
-                                    FlatWireMap<PipAndCost> *best_path, DelayStorage *storage,
-                                    pool<TypeWireSet> *explored, pool<TypeWireId> *deferred, pool<int32_t> *tiles_left)
-{
-
-    for (int32_t tile_type : tile_types) {
-        ExpandLocals locals;
-
-        locals.tiles_of_type = &tiles_of_type;
-        locals.rng = rng;
-        locals.best_path = best_path;
-        locals.storage = storage;
-        locals.explored = explored;
-        expand_tile_type(ctx, tile_type, &locals);
-
-        NPNR_ASSERT(tiles_left->erase(tile_type) == 1);
-    }
-
-    NPNR_ASSERT(tiles_left->empty());
-}
-
-// Additional storage for doing tile type expansion in parallel.
-struct TbbExpandLocals : public ExpandLocals
-{
-    const Context *ctx;
-    std::mutex *all_costs_mutex;
-
-    DelayStorage *all_tiles_storage;
-    pool<TypeWireSet> *types_explored;
-    pool<TypeWireId> *types_deferred;
-    pool<int32_t> *tiles_left;
-
-    void lock() override { all_costs_mutex->lock(); }
-
-    void unlock() override { all_costs_mutex->unlock(); }
-
-    void copy_back(int32_t tile_type) override
-    {
-        ScopeLock<TbbExpandLocals> locker(this);
-
-        auto &type_data = ctx->chip_info->tile_types[tile_type];
-
-        // Copy per tile data by to over all data structures.
-        if (ctx->verbose) {
-            log_info("Expanded all wires in type %s, merging data back\n", IdString(type_data.name).c_str(ctx));
-            log_info("Testing %zu wires, saw %zu types, deferred %zu types\n", type_data.wire_data.size(),
-                     explored->size(), deferred->size());
-        }
-
-        // Copy cheapest explored paths back to all_tiles_storage.
-        for (const auto &type_pair : storage->storage) {
-            auto &type_pair_data = all_tiles_storage->storage[type_pair.first];
-            for (const auto &delta_pair : type_pair.second) {
-                // See if this dx/dy already has data.
-                auto result = type_pair_data.emplace(delta_pair.first, delta_pair.second);
-                if (!result.second) {
-                    // This was already in the map, check if this new result is
-                    // better
-                    if (delta_pair.second < result.first->second) {
-                        result.first->second = delta_pair.second;
-                    }
-                }
-            }
-        }
-
-        // Update explored and deferred sets.
-        for (auto &key : *explored) {
-            types_explored->emplace(key);
-        }
-        for (auto &key : *deferred) {
-            types_deferred->emplace(key);
-        }
-
-        NPNR_ASSERT(tiles_left->erase(tile_type));
-
-        if (ctx->verbose) {
-            log_info("Done merging data from type %s, %zu tiles left\n", IdString(type_data.name).c_str(ctx),
-                     tiles_left->size());
-        }
-    }
-};
-
-// Wrapper method used if running expansion in parallel.
-//
-// expand_tile_type is invoked using thread local data, and then afterwards
-// the data is joined with the global data.
-static void expand_tile_type_parallel(const Context *ctx, int32_t tile_type, const std::vector<Sampler> &tiles_of_type,
-                                      DeterministicRNG *rng, std::mutex *all_costs_mutex,
-                                      DelayStorage *all_tiles_storage, pool<TypeWireSet> *types_explored,
-                                      pool<TypeWireId> *types_deferred, pool<int32_t> *tiles_left)
-{
-    TbbExpandLocals locals;
-
-    DeterministicRNG rng_copy = *rng;
-    FlatWireMap<PipAndCost> best_path(ctx);
-    pool<TypeWireSet> explored;
-    pool<TypeWireId> deferred;
-    DelayStorage storage;
-    storage.max_explore_depth = all_tiles_storage->max_explore_depth;
-
-    locals.tiles_of_type = &tiles_of_type;
-    locals.rng = &rng_copy;
-    locals.best_path = &best_path;
-    locals.storage = &storage;
-    locals.explored = &explored;
-    locals.deferred = &deferred;
-
-    locals.ctx = ctx;
-    locals.all_costs_mutex = all_costs_mutex;
-    locals.all_tiles_storage = all_tiles_storage;
-    locals.types_explored = types_explored;
-    locals.types_deferred = types_deferred;
-    locals.tiles_left = tiles_left;
-
-    expand_tile_type(ctx, tile_type, &locals);
-}
-
-void Lookahead::build_lookahead(const Context *ctx, DeterministicRNG *rng)
-{
-    auto start = std::chrono::high_resolution_clock::now();
-
-    if (ctx->verbose) {
-        log_info("Building lookahead, first gathering input and output site wires\n");
-    }
-
-    pool<TypeWireId> input_site_ports;
-    for (BelId bel : ctx->getBels()) {
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-
-        for (IdString pin : ctx->getBelPins(bel)) {
-            WireId pin_wire = ctx->getBelPinWire(bel, pin);
-            if (pin_wire == WireId()) {
-                continue;
-            }
-
-            PortType type = ctx->getBelPinType(bel, pin);
-
-            if (type == PORT_IN && bel_data.category == BEL_CATEGORY_LOGIC) {
-                input_site_wires.emplace(TypeWireId(ctx, pin_wire), std::vector<InputSiteWireCost>());
-            } else if (type == PORT_OUT && bel_data.category == BEL_CATEGORY_LOGIC) {
-                output_site_wires.emplace(TypeWireId(ctx, pin_wire), OutputSiteWireCost());
-            } else if (type == PORT_OUT && bel_data.category == BEL_CATEGORY_SITE_PORT) {
-                input_site_ports.emplace(TypeWireId(ctx, pin_wire));
-            }
-        }
-    }
-
-    if (ctx->verbose) {
-        log_info("Have %zu input and %zu output site wire types. Creating tile type samplers\n",
-                 input_site_wires.size(), output_site_wires.size());
-    }
-
-    std::vector<Sampler> tiles_of_type;
-    tiles_of_type.resize(ctx->chip_info->tile_types.ssize());
-
-    std::vector<size_t> indicies;
-    std::vector<std::pair<int32_t, int32_t>> xys;
-    indicies.reserve(ctx->chip_info->tiles.size());
-    xys.reserve(ctx->chip_info->tiles.size());
-
-    for (int32_t tile_type = 0; tile_type < ctx->chip_info->tile_types.ssize(); ++tile_type) {
-        indicies.clear();
-        xys.clear();
-
-        for (size_t tile = 0; tile < ctx->chip_info->tiles.size(); ++tile) {
-            if (ctx->chip_info->tiles[tile].type != tile_type) {
-                continue;
-            }
-
-            std::pair<size_t, size_t> xy;
-            ctx->get_tile_x_y(tile, &xy.first, &xy.second);
-
-            indicies.push_back(tile);
-            xys.push_back(xy);
-        }
-
-        auto &tile_sampler = tiles_of_type[tile_type];
-        tile_sampler.divide_samples(kNumberSamples, xys);
-
-        // Remap Sampler::indicies from 0 to number of tiles of type to
-        // absolute tile indicies.
-        for (size_t i = 0; i < indicies.size(); ++i) {
-            tile_sampler.indicies[i] = indicies[tile_sampler.indicies[i]];
-        }
-    }
-
-    if (ctx->verbose) {
-        log_info("Expanding input site wires\n");
-    }
-
-    // Expand backwards from each input site wire to find the cheapest
-    // non-site wire.
-    for (auto &input_pair : input_site_wires) {
-        expand_input_type(ctx, rng, tiles_of_type[input_pair.first.type], input_pair.first, &input_pair.second);
-    }
-
-    if (ctx->verbose) {
-        log_info("Expanding output site wires\n");
-    }
-
-    // Expand forward from each output site wire to find the cheapest
-    // non-site wire.
-    for (auto &output_pair : output_site_wires) {
-        output_pair.second.cost = std::numeric_limits<delay_t>::max();
-        expand_output_type(ctx, rng, tiles_of_type[output_pair.first.type], output_pair.first, &output_pair.second,
-                           &site_to_site_cost);
-    }
-    for (TypeWireId input_site_port : input_site_ports) {
-        expand_output_type(ctx, rng, tiles_of_type[input_site_port.type], input_site_port, nullptr, &site_to_site_cost);
-    }
-
-    if (ctx->verbose) {
-        log_info("Expanding all wire types\n");
-    }
-
-    DelayStorage all_tiles_storage;
-    all_tiles_storage.max_explore_depth = kInitialExploreDepth;
-
-    // These are wire types that have been explored.
-    pool<TypeWireSet> types_explored;
-
-    // These are wire types that have been deferred because they are trival
-    // copies of another wire type.  These can be cheaply computed after the
-    // graph has been explored.
-    pool<TypeWireId> types_deferred;
-
-    std::vector<int32_t> tile_types;
-    pool<int32_t> tiles_left;
-    tile_types.reserve(ctx->chip_info->tile_types.size());
-    for (int32_t tile_type = 0; tile_type < ctx->chip_info->tile_types.ssize(); ++tile_type) {
-        tile_types.push_back(tile_type);
-        tiles_left.emplace(tile_type);
-    }
-
-    FlatWireMap<PipAndCost> best_path(ctx);
-
-    // Walk each tile type, and expand all non-site wires in the tile.
-    // Wires that are nodes will expand as if the node type is the first node
-    // in the wire.
-    //
-    // Wires that only have 1 output pip are deferred until the next loop,
-    // because generally those wires will get explored via another wire.
-    // The deferred will be expanded if this assumption doesn't hold.
-    bool expand_serially = true;
-#if defined(NEXTPNR_USE_TBB) // Run parallely
-    {
-        std::mutex all_costs_mutex;
-
-        expand_serially = false;
-        tbb::parallel_for_each(tile_types, [&](int32_t tile_type) {
-            expand_tile_type_parallel(ctx, tile_type, tiles_of_type, rng, &all_costs_mutex, &all_tiles_storage,
-                                      &types_explored, &types_deferred, &tiles_left);
-        });
-    }
-#else
-    // Supress warning that expand_tile_type_parallel if not running in
-    // parallel.
-    (void)expand_tile_type_parallel;
-#endif
-    if (expand_serially) {
-        expand_tile_type_serial(ctx, tile_types, tiles_of_type, rng, &best_path, &all_tiles_storage, &types_explored,
-                                &types_deferred, &tiles_left);
-    }
-
-    // Check to see if deferred wire types were expanded.  If they were not
-    // expanded, expand them now.  If they were expanded, copy_types is
-    // populated with the wire types that can just copy the relevant data from
-    // another wire type.
-    for (TypeWireId wire_type : types_deferred) {
-        auto &type_data = ctx->chip_info->tile_types[wire_type.type];
-        auto &tile_sampler = tiles_of_type[wire_type.type];
-        auto &wire_data = type_data.wire_data[wire_type.index];
-
-        if (ctx->verbose) {
-            log_info("Expanding deferred wire %s in type %s (seen %zu types)\n", IdString(wire_data.name).c_str(ctx),
-                     IdString(type_data.name).c_str(ctx), types_explored.size());
-        }
-
-        expand_deferred_routing_graph(ctx, rng, tile_sampler, wire_type, &types_explored, &all_tiles_storage,
-                                      &best_path);
-    }
-
-    auto end = std::chrono::high_resolution_clock::now();
-    if (ctx->verbose) {
-        log_info("Done with expansion, dt %02fs\n", std::chrono::duration<float>(end - start).count());
-    }
-
-    if (kWriteLookaheadCsv) {
-        write_lookahead_csv(ctx, all_tiles_storage);
-        end = std::chrono::high_resolution_clock::now();
-        if (ctx->verbose) {
-            log_info("Done writing data to disk, dt %02fs\n", std::chrono::duration<float>(end - start).count());
-        }
-    }
-
-#if defined(NEXTPNR_USE_TBB) // Run parallely
-    tbb::parallel_for_each(all_tiles_storage.storage,
-                           [&](const std::pair<TypeWirePair, dict<std::pair<int32_t, int32_t>, delay_t>> &type_pair) {
-#else
-    for (const auto &type_pair : all_tiles_storage.storage) {
-#endif
-                               cost_map.set_cost_map(ctx, type_pair.first, type_pair.second);
-#if defined(NEXTPNR_USE_TBB) // Run parallely
-                           });
-#else
-    }
-#endif
-
-    end = std::chrono::high_resolution_clock::now();
-    if (ctx->verbose) {
-        log_info("build_lookahead time %.02fs\n", std::chrono::duration<float>(end - start).count());
-    }
-}
-
-constexpr static bool kUseGzipForLookahead = false;
-
-static void write_message(::capnp::MallocMessageBuilder &message, const std::string &filename)
-{
-    kj::Array<capnp::word> words = messageToFlatArray(message);
-    kj::ArrayPtr<kj::byte> bytes = words.asBytes();
-
-    boost::filesystem::path temp = boost::filesystem::unique_path();
-    log_info("Writing tempfile to %s\n", temp.c_str());
-
-    if (kUseGzipForLookahead) {
-        gzFile file = gzopen(temp.c_str(), "w");
-        NPNR_ASSERT(file != Z_NULL);
-
-        size_t bytes_written = 0;
-        int result;
-        while (bytes_written < bytes.size()) {
-            size_t bytes_remaining = bytes.size() - bytes_written;
-            size_t bytes_to_write = bytes_remaining;
-            if (bytes_to_write >= std::numeric_limits<int>::max()) {
-                bytes_to_write = std::numeric_limits<int>::max();
-            }
-            result = gzwrite(file, &bytes[0] + bytes_written, bytes_to_write);
-            if (result < 0) {
-                break;
-            }
-
-            bytes_written += result;
-        }
-
-        int error;
-        std::string error_str;
-        if (result < 0) {
-            error_str.assign(gzerror(file, &error));
-        }
-        NPNR_ASSERT(gzclose(file) == Z_OK);
-        if (bytes_written != bytes.size()) {
-            // Remove failed writes before reporting error.
-            boost::filesystem::remove(temp);
-        }
-
-        if (result < 0) {
-            log_error("Failed to write lookahead, error from gzip %s\n", error_str.c_str());
-        } else {
-            if (bytes_written != bytes.size()) {
-                log_error("Failed to write lookahead, wrote %d bytes, had %zu bytes\n", result, bytes.size());
-            } else {
-                // Written, move file into place
-                boost::filesystem::rename(temp, filename);
-            }
-        }
-    } else {
-        {
-            kj::Own<kj::Filesystem> fs = kj::newDiskFilesystem();
-
-            auto path = kj::Path::parse(temp);
-            auto file = fs->getCurrent().openFile(path, kj::WriteMode::CREATE);
-            file->writeAll(bytes);
-        }
-
-        boost::filesystem::rename(temp, filename);
-    }
-}
-
-bool Lookahead::read_lookahead(const std::string &chipdb_hash, const std::string &filename)
-{
-    capnp::ReaderOptions reader_options;
-    reader_options.traversalLimitInWords = 32llu * 1024llu * 1024llu * 1024llu;
-
-    if (kUseGzipForLookahead) {
-        gzFile file = gzopen(filename.c_str(), "r");
-        if (file == Z_NULL) {
-            return false;
-        }
-
-        std::vector<uint8_t> output_data;
-        output_data.resize(4096);
-        std::stringstream sstream(std::ios_base::in | std::ios_base::out | std::ios_base::binary);
-        while (true) {
-            int ret = gzread(file, output_data.data(), output_data.size());
-            NPNR_ASSERT(ret >= 0);
-            if (ret > 0) {
-                sstream.write((const char *)output_data.data(), ret);
-                NPNR_ASSERT(sstream);
-            } else {
-                NPNR_ASSERT(ret == 0);
-                int error;
-                gzerror(file, &error);
-                NPNR_ASSERT(error == Z_OK);
-                break;
-            }
-        }
-
-        NPNR_ASSERT(gzclose(file) == Z_OK);
-
-        sstream.seekg(0);
-        kj::std::StdInputStream istream(sstream);
-        capnp::InputStreamMessageReader message_reader(istream, reader_options);
-
-        lookahead_storage::Lookahead::Reader lookahead = message_reader.getRoot<lookahead_storage::Lookahead>();
-        return from_reader(chipdb_hash, lookahead);
-    } else {
-        boost::iostreams::mapped_file_source file;
-        try {
-            file.open(filename.c_str());
-        } catch (std::ios_base::failure &fail) {
-            return false;
-        }
-
-        if (!file.is_open()) {
-            return false;
-        }
-
-        const char *data = reinterpret_cast<const char *>(file.data());
-        const kj::ArrayPtr<const ::capnp::word> words =
-                kj::arrayPtr(reinterpret_cast<const ::capnp::word *>(data), file.size() / sizeof(::capnp::word));
-        ::capnp::FlatArrayMessageReader reader(words, reader_options);
-        lookahead_storage::Lookahead::Reader lookahead = reader.getRoot<lookahead_storage::Lookahead>();
-        return from_reader(chipdb_hash, lookahead);
-    }
-}
-
-void Lookahead::write_lookahead(const std::string &chipdb_hash, const std::string &file) const
-{
-    ::capnp::MallocMessageBuilder message;
-
-    lookahead_storage::Lookahead::Builder lookahead = message.initRoot<lookahead_storage::Lookahead>();
-    to_builder(chipdb_hash, lookahead);
-    write_message(message, file);
-}
-
-void Lookahead::init(const Context *ctx, DeterministicRNG *rng)
-{
-    std::string lookahead_filename;
-    if (kUseGzipForLookahead) {
-        lookahead_filename = ctx->args.chipdb + ".lookahead.tgz";
-    } else {
-        lookahead_filename = ctx->args.chipdb + ".lookahead";
-    }
-
-    std::string chipdb_hash = ctx->get_chipdb_hash();
-
-    if (ctx->args.rebuild_lookahead || !read_lookahead(chipdb_hash, lookahead_filename)) {
-        build_lookahead(ctx, rng);
-        if (!ctx->args.dont_write_lookahead) {
-            write_lookahead(chipdb_hash, lookahead_filename);
-        }
-    }
-}
-
-static bool safe_add_i32(int32_t a, int32_t b, int32_t *out)
-{
-#if defined(__GNUG__) || defined(__clang__)
-    // GCC and clang have had __builtin_add_overflow for a while.
-    return !__builtin_add_overflow(a, b, out);
-#else
-    // MSVC and other don't have an intrinsic.  Emit some more code.
-    bool safe_to_add;
-    if (b < 0) {
-        safe_to_add = a >= std::numeric_limits<int32_t>::min() - b;
-    } else {
-        safe_to_add = a <= std::numeric_limits<int32_t>::max() - b;
-    }
-    if (!safe_to_add) {
-        return false;
-    }
-    *out = a + b;
-    return true;
-#endif
-}
-
-static void saturating_incr(int32_t *acc, int32_t value)
-{
-    if (!safe_add_i32(*acc, value, acc)) {
-        if (value > 0) {
-            *acc = std::numeric_limits<int32_t>::max();
-        } else {
-            *acc = std::numeric_limits<int32_t>::min();
-        }
-    }
-}
-
-#define DEBUG_LOOKUP
-
-delay_t Lookahead::estimateDelay(const Context *ctx, WireId src, WireId dst) const
-{
-#ifdef DEBUG_LOOKUP
-    if (ctx->debug) {
-        log_info("Looking up %s to %s\n", ctx->nameOfWire(src), ctx->nameOfWire(dst));
-    }
-#endif
-    delay_t delay = 0;
-
-    // Follow chain down, chasing wires with only 1 pip.  Stop if dst is
-    // reached.
-    WireId orig_src = src;
-    src = follow_pip_chain_target(ctx, src, dst, &delay);
-    NPNR_ASSERT(delay >= 0);
-    if (src == WireId()) {
-        // This src wire is a dead end, tell router to avoid it!
-#ifdef DEBUG_LOOKUP
-        if (ctx->debug) {
-            log_info("Source %s is a dead end!\n", ctx->nameOfWire(orig_src));
-        }
-#endif
-        return std::numeric_limits<delay_t>::max();
-    }
-
-#ifdef DEBUG_LOOKUP
-    if (ctx->debug && src != orig_src) {
-        log_info("Moving src from %s to %s, delay = %d\n", ctx->nameOfWire(orig_src), ctx->nameOfWire(src), delay);
-    }
-#endif
-
-    if (src == dst) {
-        // Reached target already, done!
-        return delay;
-    }
-
-    if (ctx->is_same_site(src, dst)) {
-        // Check for site to site direct path.
-        TypeWirePair pair;
-
-        TypeWireId src_type(ctx, src);
-        pair.src = src_type;
-
-        TypeWireId dst_type(ctx, dst);
-        pair.dst = dst_type;
-
-        auto iter = site_to_site_cost.find(pair);
-        if (iter != site_to_site_cost.end()) {
-            NPNR_ASSERT(iter->second >= 0);
-            saturating_incr(&delay, iter->second);
-#ifdef DEBUG_LOOKUP
-            if (ctx->debug) {
-                log_info("Found site to site direct path %s -> %s = %d\n", ctx->nameOfWire(src), ctx->nameOfWire(dst),
-                         delay);
-            }
-#endif
-            return delay;
-        }
-    }
-
-    // At this point we know that the routing interconnect is needed, or
-    // the pair is unreachable.
-    orig_src = src;
-    TypeWireId src_type(ctx, src);
-
-    // Find the first routing wire from the src_type.
-    auto src_iter = output_site_wires.find(src_type);
-    if (src_iter != output_site_wires.end()) {
-        NPNR_ASSERT(src_iter->second.cost >= 0);
-        saturating_incr(&delay, src_iter->second.cost);
-        src_type = src_iter->second.cheapest_route_from;
-
-        src = canonical_wire(ctx->chip_info, src.tile, src_type.index);
-#ifdef DEBUG_LOOKUP
-        if (ctx->debug) {
-            log_info("Moving src from %s to %s, delay = %d\n", ctx->nameOfWire(orig_src), ctx->nameOfWire(src), delay);
-        }
-#endif
-    }
-
-    // Make sure that the new wire is in the routing graph.
-    if (ctx->is_wire_in_site(src)) {
-#ifdef DEBUG_LOOKUP
-        // We've already tested for direct site to site routing, if src cannot
-        // reach outside of the routing network, this path is impossible.
-        if (ctx->debug) {
-            log_warning("Failed to reach routing network for src %s, got to %s\n", ctx->nameOfWire(orig_src),
-                        ctx->nameOfWire(src));
-        }
-#endif
-        return std::numeric_limits<delay_t>::max();
-    }
-
-    if (src == dst) {
-        // Reached target already, done!
-        return delay;
-    }
-
-    // Find the first routing wire that reaches dst_type.
-    WireId orig_dst = dst;
-    TypeWireId dst_type(ctx, dst);
-
-    auto dst_iter = input_site_wires.find(dst_type);
-    if (dst_iter == input_site_wires.end()) {
-        // dst_type isn't an input site wire, just add point to point delay.
-        auto &dst_data = ctx->wire_info(dst);
-        if (dst_data.site != -1) {
-#ifdef DEBUG_LOOKUP
-            // We've already tested for direct site to site routing, if dst cannot
-            // be reached from the routing network, this path is impossible.
-            if (ctx->debug) {
-                log_warning("Failed to reach routing network for dst %s, got to %s\n", ctx->nameOfWire(orig_dst),
-                            ctx->nameOfWire(dst));
-            }
-#endif
-            return std::numeric_limits<delay_t>::max();
-        }
-
-        // Follow chain up
-        WireId orig_dst = dst;
-        (void)orig_dst;
-
-        delay_t chain_delay;
-        dst = follow_pip_chain_up(ctx, dst, &chain_delay);
-        NPNR_ASSERT(chain_delay >= 0);
-        saturating_incr(&delay, chain_delay);
-#ifdef DEBUG_LOOKUP
-        if (ctx->debug && dst != orig_dst) {
-            log_info("Moving dst from %s to %s, delay = %d\n", ctx->nameOfWire(orig_dst), ctx->nameOfWire(dst), delay);
-        }
-#endif
-
-        if (src == dst) {
-            // Reached target already, done!
-            return delay;
-        }
-
-        // Both src and dst are in the routing graph, lookup approx cost to go
-        // from src to dst.
-        int32_t delay_from_map = cost_map.get_delay(ctx, src, dst);
-        NPNR_ASSERT(delay_from_map >= 0);
-        saturating_incr(&delay, delay_from_map);
-
-#ifdef DEBUG_LOOKUP
-        if (ctx->debug) {
-            log_info("Final delay = %d\n", delay);
-        }
-#endif
-
-        return delay;
-    } else {
-        // dst_type is an input site wire, try each possible routing path.
-        delay_t base_delay = delay;
-        delay_t cheapest_path = std::numeric_limits<delay_t>::max();
-
-        for (const InputSiteWireCost &input_cost : dst_iter->second) {
-            dst = orig_dst;
-            delay = base_delay;
-
-            NPNR_ASSERT(input_cost.cost >= 0);
-            saturating_incr(&delay, input_cost.cost);
-            dst_type = input_cost.route_to;
-
-            NPNR_ASSERT(dst_type.index != -1);
-            dst = canonical_wire(ctx->chip_info, dst.tile, dst_type.index);
-            NPNR_ASSERT(dst != WireId());
-
-#ifdef DEBUG_LOOKUP
-            if (ctx->debug) {
-                log_info("Moving dst from %s to %s, delay = %d\n", ctx->nameOfWire(orig_dst), ctx->nameOfWire(dst),
-                         delay);
-            }
-#endif
-
-            if (dst == src) {
-#ifdef DEBUG_LOOKUP
-                if (ctx->debug) {
-                    log_info("Possible delay = %d\n", delay);
-                }
-#endif
-                // Reached target already, done!
-                cheapest_path = std::min(delay, cheapest_path);
-                continue;
-            }
-
-            auto &dst_data = ctx->wire_info(dst);
-            if (dst_data.site != -1) {
-#ifdef DEBUG_LOOKUP
-                // We've already tested for direct site to site routing, if dst cannot
-                // be reached from the routing network, this path is impossible.
-                if (ctx->debug) {
-                    log_warning("Failed to reach routing network for dst %s, got to %s\n", ctx->nameOfWire(orig_dst),
-                                ctx->nameOfWire(dst));
-                }
-#endif
-                continue;
-            }
-
-            // Follow chain up
-            WireId orig_dst = dst;
-            (void)orig_dst;
-
-            delay_t chain_delay;
-            dst = follow_pip_chain_up(ctx, dst, &chain_delay);
-            NPNR_ASSERT(chain_delay >= 0);
-            saturating_incr(&delay, chain_delay);
-#ifdef DEBUG_LOOKUP
-            if (ctx->debug && dst != orig_dst) {
-                log_info("Moving dst from %s to %s, delay = %d\n", ctx->nameOfWire(orig_dst), ctx->nameOfWire(dst),
-                         delay);
-            }
-#endif
-
-            if (dst == WireId()) {
-                // This dst wire is a dead end, don't examine it!
-#ifdef DEBUG_LOOKUP
-                if (ctx->debug) {
-                    log_info("Dest %s is a dead end!\n", ctx->nameOfWire(dst));
-                }
-#endif
-                continue;
-            }
-
-            if (src == dst) {
-#ifdef DEBUG_LOOKUP
-                if (ctx->debug) {
-                    log_info("Possible delay = %d\n", delay);
-                }
-#endif
-                // Reached target already, done!
-                cheapest_path = std::min(delay, cheapest_path);
-                continue;
-            }
-
-            // Both src and dst are in the routing graph, lookup approx cost to go
-            // from src to dst.
-            int32_t delay_from_map = cost_map.get_delay(ctx, src, dst);
-            NPNR_ASSERT(delay_from_map >= 0);
-            saturating_incr(&delay, delay_from_map);
-            cheapest_path = std::min(delay, cheapest_path);
-#ifdef DEBUG_LOOKUP
-            if (ctx->debug) {
-                log_info("Possible delay = %d\n", delay);
-            }
-#endif
-        }
-
-#ifdef DEBUG_LOOKUP
-        if (ctx->debug) {
-            log_info("Final delay = %d\n", delay);
-        }
-#endif
-
-        return cheapest_path;
-    }
-}
-
-bool Lookahead::from_reader(const std::string &chipdb_hash, lookahead_storage::Lookahead::Reader reader)
-{
-    std::string expected_hash = reader.getChipdbHash();
-    if (chipdb_hash != expected_hash) {
-        return false;
-    }
-
-    input_site_wires.clear();
-    output_site_wires.clear();
-    site_to_site_cost.clear();
-
-    for (auto input_reader : reader.getInputSiteWires()) {
-        TypeWireId key(input_reader.getKey());
-
-        auto result = input_site_wires.emplace(key, std::vector<InputSiteWireCost>());
-        NPNR_ASSERT(result.second);
-        std::vector<InputSiteWireCost> &costs = result.first->second;
-        auto value = input_reader.getValue();
-        costs.reserve(value.size());
-        for (auto cost : value) {
-            costs.emplace_back(InputSiteWireCost{TypeWireId(cost.getRouteTo()), cost.getCost()});
-        }
-    }
-
-    for (auto output_reader : reader.getOutputSiteWires()) {
-        TypeWireId key(output_reader.getKey());
-
-        auto result = output_site_wires.emplace(
-                key, OutputSiteWireCost{TypeWireId(output_reader.getCheapestRouteFrom()), output_reader.getCost()});
-        NPNR_ASSERT(result.second);
-    }
-
-    for (auto site_to_site_reader : reader.getSiteToSiteCost()) {
-        TypeWirePair key(site_to_site_reader.getKey());
-        auto result = site_to_site_cost.emplace(key, site_to_site_reader.getCost());
-        NPNR_ASSERT(result.second);
-    }
-
-    cost_map.from_reader(reader.getCostMap());
-
-    return true;
-}
-
-void Lookahead::to_builder(const std::string &chipdb_hash, lookahead_storage::Lookahead::Builder builder) const
-{
-    builder.setChipdbHash(chipdb_hash);
-
-    auto input_out = builder.initInputSiteWires(input_site_wires.size());
-    auto in = input_site_wires.begin();
-    for (auto out = input_out.begin(); out != input_out.end(); ++out, ++in) {
-        NPNR_ASSERT(in != input_site_wires.end());
-
-        const TypeWireId &key = in->first;
-        key.to_builder(out->getKey());
-
-        const std::vector<InputSiteWireCost> &costs = in->second;
-        auto value = out->initValue(costs.size());
-
-        auto value_in = costs.begin();
-        for (auto value_out = value.begin(); value_out != value.end(); ++value_out, ++value_in) {
-            value_in->route_to.to_builder(value_out->getRouteTo());
-            value_out->setCost(value_in->cost);
-        }
-    }
-
-    auto output_out = builder.initOutputSiteWires(output_site_wires.size());
-    auto out = output_site_wires.begin();
-    for (auto out2 = output_out.begin(); out2 != output_out.end(); ++out, ++out2) {
-        NPNR_ASSERT(out != output_site_wires.end());
-
-        const TypeWireId &key = out->first;
-        key.to_builder(out2->getKey());
-
-        const TypeWireId &cheapest_route_from = out->second.cheapest_route_from;
-        cheapest_route_from.to_builder(out2->getCheapestRouteFrom());
-
-        out2->setCost(out->second.cost);
-    }
-
-    auto site_out = builder.initSiteToSiteCost(site_to_site_cost.size());
-    auto site = site_to_site_cost.begin();
-    for (auto out2 = site_out.begin(); out2 != site_out.end(); ++out2, ++site) {
-        NPNR_ASSERT(site != site_to_site_cost.end());
-
-        const TypeWirePair &key = site->first;
-        key.to_builder(out2->getKey());
-        out2->setCost(site->second);
-    }
-
-    cost_map.to_builder(builder.getCostMap());
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/lookahead.h b/fpga_interchange/lookahead.h
deleted file mode 100644
index 9655e13e1b..0000000000
--- a/fpga_interchange/lookahead.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef LOOKAHEAD_H
-#define LOOKAHEAD_H
-
-#include <algorithm>
-#include <vector>
-
-#include "cost_map.h"
-#include "deterministic_rng.h"
-#include "lookahead.capnp.h"
-#include "nextpnr_namespaces.h"
-#include "type_wire.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-// Lookahead is a routing graph generic lookahead builder and evaluator.
-//
-// The lookahead data model is structured into 3 parts:
-//  - Output site wires to routing network cost
-//  - Routing network point to point cost
-//  - Routing network cost to input site wires
-//
-//  If the lookahead is invoked from a routing wire to a routing wire, only
-//  the point to point cost is used.
-//
-//  If the lookahead is invoked from an output site wire to a routing wire,
-//  the point to point cost is computed using the cheapest output routing wire
-//  from the current site wire and then returned cost is the sum of the output
-//  cost plus the point to point routing network cost.
-//
-//  If the lookahead is invoked from a routing wire to an input site wire,
-//  then the cost is the point to point routing cost to the cheapest input
-//  routing wire plus the input routing cost.
-//
-//  If the lookahead is invoked from an output site wire to an input site wire,
-//  then cost is the sum of each of the 3 parts.
-struct Lookahead
-{
-    void init(const Context *, DeterministicRNG *rng);
-    void build_lookahead(const Context *, DeterministicRNG *rng);
-
-    bool read_lookahead(const std::string &chipdb_hash, const std::string &file);
-    void write_lookahead(const std::string &chipdb_hash, const std::string &file) const;
-    bool from_reader(const std::string &chipdb_hash, lookahead_storage::Lookahead::Reader reader);
-    void to_builder(const std::string &chipdb_hash, lookahead_storage::Lookahead::Builder builder) const;
-
-    delay_t estimateDelay(const Context *, WireId src, WireId dst) const;
-
-    struct InputSiteWireCost
-    {
-        // This wire is the cheapest non-site wire that leads to this site
-        // wire.
-        TypeWireId route_to;
-
-        // This is the cost from the cheapest_route_to wire to the site wire in
-        // question.
-        delay_t cost;
-    };
-
-    struct OutputSiteWireCost
-    {
-        // This wire is the cheapest non-site wire that is reachable from
-        // this site wire.
-        TypeWireId cheapest_route_from;
-
-        // This is the cost from the site wire in question to
-        // cheapest_route_from wire.
-        delay_t cost;
-    };
-
-    dict<TypeWireId, std::vector<InputSiteWireCost>> input_site_wires;
-    dict<TypeWireId, OutputSiteWireCost> output_site_wires;
-    dict<TypeWirePair, delay_t> site_to_site_cost;
-    CostMap cost_map;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* LOOKAHEAD_H */
diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
deleted file mode 100644
index 009b601e72..0000000000
--- a/fpga_interchange/luts.cc
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "luts.h"
-
-#include "log.h"
-#include "nextpnr.h"
-
-#include "site_lut_mapping_cache.h"
-
-// #define DEBUG_LUT_ROTATION
-
-NEXTPNR_NAMESPACE_BEGIN
-
-bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel &lut_bel,
-                                   const DynamicBitarray<> &old_equation, const std::vector<int32_t> &pin_map,
-                                   uint32_t used_pins)
-{
-    // pin_map maps pin indicies from the old pin to the new pin.
-    // So a reversal of a LUT4 would have a pin map of:
-    // pin_map[0] = 3;
-    // pin_map[1] = 2;
-    // pin_map[2] = 1;
-    // pin_map[3] = 0;
-
-    size_t bel_width = 1 << lut_bel.pins.size();
-    for (size_t bel_address = 0; bel_address < bel_width; ++bel_address) {
-        bool address_reachable = true;
-        size_t cell_address = 0;
-        for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) {
-            // This address line is 0, so don't translate this bit to the cell
-            // address.
-            if ((bel_address & (1 << bel_pin_idx)) == 0) {
-                if ((used_pins & (1 << bel_pin_idx)) == 0) {
-                    address_reachable = false;
-                    break;
-                }
-
-                continue;
-            }
-
-            auto cell_pin_idx = pin_map[bel_pin_idx];
-
-            // Is this BEL pin used for this cell?
-            if (cell_pin_idx < 0) {
-                // This BEL pin is not used for the LUT cell, skip
-                continue;
-            }
-
-            cell_address |= (1 << cell_pin_idx);
-        }
-
-        if (!address_reachable) {
-            continue;
-        }
-
-        bel_address += lut_bel.low_bit;
-        if (old_equation.get(cell_address)) {
-            if ((*result)[bel_address] == LL_Zero) {
-                // Output equation has a conflict!
-                return false;
-            }
-
-            (*result)[bel_address] = LL_One;
-        } else {
-            if ((*result)[bel_address] == LL_One) {
-                // Output equation has a conflict!
-                return false;
-            }
-            (*result)[bel_address] = LL_Zero;
-        }
-    }
-
-    return true;
-}
-
-static constexpr bool kCheckOutputEquation = true;
-
-struct LutPin
-{
-    struct LutPinUser
-    {
-        size_t cell_idx;
-        size_t cell_pin_idx;
-    };
-
-    const NetInfo *net = nullptr;
-    std::vector<LutPinUser> users;
-
-    int32_t min_pin = -1;
-    int32_t max_pin = -1;
-
-    void add_user(const LutBel &lut_bel, size_t cell_idx, size_t cell_pin_idx)
-    {
-        if (min_pin < 0) {
-            min_pin = lut_bel.min_pin;
-            max_pin = lut_bel.max_pin;
-        }
-
-        min_pin = std::max(min_pin, lut_bel.min_pin);
-        max_pin = std::min(max_pin, lut_bel.max_pin);
-
-        users.emplace_back();
-        users.back().cell_idx = cell_idx;
-        users.back().cell_pin_idx = cell_pin_idx;
-    }
-
-    bool operator<(const LutPin &other) const { return max_pin < other.max_pin; }
-};
-
-const std::string LutCell::nameOfPinConnection(LutCell::PinConnection conn)
-{
-    switch (conn) {
-    case PinConnection::Unconnected:
-        return std::string("unconnected");
-    case PinConnection::Gnd:
-        return std::string("Gnd");
-    case PinConnection::Vcc:
-        return std::string("Vcc");
-    case PinConnection::Const:
-        return std::string("Const");
-    case PinConnection::Signal:
-        return std::string("Signal");
-    default:
-        // Should never happen
-        NPNR_ASSERT_FALSE("Invalid value of LutCell::PinConnection");
-        return std::string();
-    }
-}
-
-uint32_t LutMapper::check_wires(const Context *ctx) const
-{
-    // Unlike the 3 argument version of check_wires, this version needs to
-    // calculate following data based on current cell pin mapping, etc:
-    //
-    //  - Index map from bel pins to cell pins, -1 for unmapped
-    //  - Mask of used pins
-    //  - Vector of unused LUT BELs.
-
-    uint32_t used_pins = 0;
-
-    std::vector<std::vector<int32_t>> bel_to_cell_pin_remaps;
-    std::vector<const LutBel *> lut_bels;
-    bel_to_cell_pin_remaps.resize(cells.size());
-    lut_bels.resize(cells.size());
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        const CellInfo *cell = cells[cell_idx];
-
-        auto &bel_data = bel_info(ctx->chip_info, cell->bel);
-        IdString bel_name(bel_data.name);
-        auto &lut_bel = element.lut_bels.at(bel_name);
-        lut_bels[cell_idx] = &lut_bel;
-
-        bel_to_cell_pin_remaps[cell_idx].resize(lut_bel.pins.size(), -1);
-
-        for (size_t pin_idx = 0; pin_idx < cell->lut_cell.pins.size(); ++pin_idx) {
-            IdString lut_cell_pin = cell->lut_cell.pins[pin_idx];
-            const std::vector<IdString> bel_pins = cell->cell_bel_pins.at(lut_cell_pin);
-            NPNR_ASSERT(bel_pins.size() == 1);
-
-            size_t bel_pin_idx = lut_bel.pin_to_index.at(bel_pins[0]);
-            bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] = pin_idx;
-            used_pins |= (1 << bel_pin_idx);
-        }
-    }
-
-    pool<const LutBel *, hash_ptr_ops> blocked_luts;
-    return check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, &blocked_luts);
-}
-
-uint32_t LutMapper::check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps,
-                                const std::vector<const LutBel *> &lut_bels, uint32_t used_pins,
-                                pool<const LutBel *, hash_ptr_ops> *blocked_luts) const
-{
-    std::vector<const LutBel *> unused_luts;
-    for (auto &lut_bel_pair : element.lut_bels) {
-        if (std::find(lut_bels.begin(), lut_bels.end(), &lut_bel_pair.second) == lut_bels.end()) {
-            unused_luts.push_back(&lut_bel_pair.second);
-            blocked_luts->emplace(&lut_bel_pair.second);
-        }
-    }
-
-    uint32_t pin_mask = 0;
-
-    DynamicBitarray<> wire_equation;
-    wire_equation.resize(2);
-    wire_equation.set(0, false);
-    wire_equation.set(1, true);
-
-    std::vector<int32_t> wire_bel_to_cell_pin_map;
-    std::vector<LogicLevel> equation_result;
-    for (int32_t pin_idx = 0; pin_idx < (int32_t)element.pins.size(); ++pin_idx) {
-        if (used_pins & (1 << pin_idx)) {
-            // This pin is already used, so it cannot be used for a wire.
-            continue;
-        }
-
-        bool valid_pin_for_wire = false;
-        bool invalid_pin_for_wire = false;
-
-        for (const LutBel *lut_bel : unused_luts) {
-            if (pin_idx < lut_bel->min_pin) {
-                continue;
-            }
-
-            if (pin_idx > lut_bel->max_pin) {
-                continue;
-            }
-
-            wire_bel_to_cell_pin_map.clear();
-            wire_bel_to_cell_pin_map.resize(lut_bel->pins.size(), -1);
-            wire_bel_to_cell_pin_map[lut_bel->pin_to_index.at(element.pins[pin_idx])] = 0;
-
-            equation_result.clear();
-            equation_result.resize(element.width, LL_DontCare);
-
-            uint32_t used_pins_with_wire = used_pins | (1 << pin_idx);
-
-            for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-                const CellInfo *cell = cells[cell_idx];
-                auto &lut_bel_for_cell = *lut_bels[cell_idx];
-                if (!rotate_and_merge_lut_equation(&equation_result, lut_bel_for_cell, cell->lut_cell.equation,
-                                                   bel_to_cell_pin_remaps[cell_idx], used_pins_with_wire)) {
-                    invalid_pin_for_wire = true;
-                    break;
-                }
-            }
-
-            if (invalid_pin_for_wire) {
-                break;
-            }
-
-            if (rotate_and_merge_lut_equation(&equation_result, *lut_bel, wire_equation, wire_bel_to_cell_pin_map,
-                                              used_pins_with_wire)) {
-                valid_pin_for_wire = true;
-                blocked_luts->erase(lut_bel);
-            }
-        }
-
-        bool good_for_wire = valid_pin_for_wire && !invalid_pin_for_wire;
-        if (!good_for_wire) {
-            pin_mask |= (1 << pin_idx);
-        }
-    }
-
-    return pin_mask;
-}
-
-bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping,
-                           pool<const LutBel *, hash_ptr_ops> *blocked_luts)
-{
-    dict<NetInfo *, LutPin, hash_ptr_ops> lut_pin_map;
-    std::vector<const LutBel *> lut_bels;
-    lut_bels.resize(cells.size());
-
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        const CellInfo *cell = cells[cell_idx];
-#ifdef DEBUG_LUT_ROTATION
-        log_info("Mapping %s %s eq = %s at %s\n", cell->type.c_str(ctx), cell->name.c_str(ctx),
-                 cell->params.at(ctx->id("INIT")).c_str(), ctx->nameOfBel(cell->bel));
-#endif
-
-        auto &bel_data = bel_info(ctx->chip_info, cell->bel);
-        IdString bel_name(bel_data.name);
-        auto &lut_bel = element.lut_bels.at(bel_name);
-        lut_bels[cell_idx] = &lut_bel;
-
-        for (size_t pin_idx = 0; pin_idx < cell->lut_cell.pins.size(); ++pin_idx) {
-            IdString lut_pin_name = cell->lut_cell.pins[pin_idx];
-            const PortInfo &port_info = cell->ports.at(lut_pin_name);
-            NPNR_ASSERT(port_info.net != nullptr);
-
-            auto result = lut_pin_map.emplace(port_info.net, LutPin());
-            LutPin &lut_pin = result.first->second;
-            lut_pin.net = port_info.net;
-            lut_pin.add_user(lut_bel, cell_idx, pin_idx);
-        }
-    }
-
-    if (lut_pin_map.size() > element.pins.size()) {
-        // Trival conflict, more nets entering element than pins are
-        // available!
-#ifdef DEBUG_LUT_ROTATION
-        log_info("Trival failure %zu > %zu, %zu %zu\n", lut_pin_map.size(), element.pins.size(), element.width,
-                 element.lut_bels.size());
-#endif
-        return false;
-    }
-
-    std::vector<LutPin> lut_pins;
-    lut_pins.reserve(lut_pin_map.size());
-    for (auto lut_pin_pair : lut_pin_map) {
-        lut_pins.push_back(std::move(lut_pin_pair.second));
-    }
-    lut_pin_map.clear();
-    std::sort(lut_pins.begin(), lut_pins.end());
-
-    std::vector<std::vector<size_t>> cell_to_bel_pin_remaps;
-    std::vector<std::vector<int32_t>> bel_to_cell_pin_remaps;
-    cell_to_bel_pin_remaps.resize(cells.size());
-    bel_to_cell_pin_remaps.resize(cells.size());
-    for (size_t i = 0; i < cells.size(); ++i) {
-        cell_to_bel_pin_remaps[i].resize(cells[i]->lut_cell.pins.size());
-        bel_to_cell_pin_remaps[i].resize(lut_bels[i]->pins.size(), -1);
-    }
-
-    uint32_t used_pins = 0;
-    size_t idx = 0;
-    std::vector<IdString> net_pins(lut_pins.size());
-    for (auto &lut_pin : lut_pins) {
-        size_t net_idx = idx++;
-        used_pins |= (1 << net_idx);
-
-        for (auto cell_pin_idx : lut_pin.users) {
-            size_t cell_idx = cell_pin_idx.cell_idx;
-            size_t pin_idx = cell_pin_idx.cell_pin_idx;
-            IdString bel_pin = lut_bels[cell_idx]->pins[net_idx];
-#ifdef DEBUG_LUT_ROTATION
-            log_info("%s %s %s => %s (%s)\n", cells[cell_idx]->type.c_str(ctx), cells[cell_idx]->name.c_str(ctx),
-                     cells[cell_idx]->lut_cell.pins[pin_idx].c_str(ctx), bel_pin.c_str(ctx),
-                     lut_pin.net->name.c_str(ctx));
-#endif
-            if (net_pins[net_idx] == IdString()) {
-                net_pins[net_idx] = bel_pin;
-            } else {
-                NPNR_ASSERT(net_pins[net_idx] == bel_pin);
-            }
-
-            cell_to_bel_pin_remaps[cell_idx][pin_idx] = net_idx;
-            bel_to_cell_pin_remaps[cell_idx][net_idx] = pin_idx;
-        }
-    }
-
-    // Try to see if the equations are mergable!
-    std::vector<LogicLevel> equation_result;
-    equation_result.resize(element.width, LL_DontCare);
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        const CellInfo *cell = cells[cell_idx];
-        auto &lut_bel = *lut_bels[cell_idx];
-        if (!rotate_and_merge_lut_equation(&equation_result, lut_bel, cell->lut_cell.equation,
-                                           bel_to_cell_pin_remaps[cell_idx], used_pins)) {
-#ifdef DEBUG_LUT_ROTATION
-            log_info("Failed to find a solution!\n");
-            for (auto *cell : cells) {
-                log_info("%s %s : %s\b\n", cell->type.c_str(ctx), cell->name.c_str(ctx),
-                         cell->params.at(ctx->id("INIT")).c_str());
-            }
-#endif
-            return false;
-        }
-    }
-
-#ifdef DEBUG_LUT_ROTATION
-    log_info("Found a solution!\n");
-#endif
-
-    // Sanity check final equation to make sure no assumptions are violated.
-    if (kCheckOutputEquation) {
-        for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-            CellInfo *cell = cells[cell_idx];
-            auto &lut_bel = *lut_bels[cell_idx];
-
-            dict<IdString, IdString> cell_to_bel_map;
-            for (size_t pin_idx = 0; pin_idx < cell->lut_cell.pins.size(); ++pin_idx) {
-                size_t bel_pin_idx = cell_to_bel_pin_remaps[cell_idx][pin_idx];
-                NPNR_ASSERT(bel_pin_idx < lut_bel.pins.size());
-                cell_to_bel_map[cell->lut_cell.pins[pin_idx]] = lut_bel.pins[bel_pin_idx];
-            }
-
-            check_equation(cell->lut_cell, cell_to_bel_map, lut_bel, equation_result, used_pins);
-        }
-    }
-
-    // Not all LUT inputs are used
-    uint32_t pin_mask = 0;
-    if (cells.size() != element.lut_bels.size()) {
-        pin_mask = check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, blocked_luts);
-    }
-
-#if defined(DEBUG_LUT_ROTATION)
-    log_info("Cell bindings:\n");
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        CellInfo *cell = cells[cell_idx];
-        log_info(" - %s => %s\n", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx));
-    }
-#endif
-
-    // Fill in the LUT mapping result
-
-    // Push new cell -> BEL pin maps out to cells now that equations have been
-    // verified!
-    lut_mapping->cells.reserve(cells.size());
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        CellInfo *cellInfo = cells[cell_idx];
-        auto &lutBel = *lut_bels[cell_idx];
-
-        // Add the cell data
-        SiteLutMappingResult::Cell cell;
-        cell.belIndex = cellInfo->bel.index;
-
-        // Cell to BEL pin map
-        for (size_t pin_idx = 0; pin_idx < cellInfo->lut_cell.pins.size(); ++pin_idx) {
-            IdString cellPin = cellInfo->lut_cell.pins[pin_idx];
-            IdString belPin = lutBel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]];
-            cell.belPins[cellPin] = belPin;
-        }
-
-        cell.lutCell.pin_connections.clear();
-
-        // All LUT inputs used
-        if (cells.size() == element.lut_bels.size()) {
-            for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) {
-                if ((used_pins & (1 << bel_pin_idx)) == 0) {
-                    NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Const);
-                } else {
-                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
-                }
-            }
-        }
-        // Only some LUT inputs used
-        else {
-            for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) {
-                if ((pin_mask & (1 << bel_pin_idx)) != 0) {
-                    NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    auto pin = lutBel.pins.at(bel_pin_idx);
-                    cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Const);
-                } else {
-                    cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
-                }
-            }
-        }
-
-#if defined(DEBUG_LUT_ROTATION)
-        log_info("Pin connections for LUT cell %s:\n", cellInfo->name.c_str(ctx));
-        for (const auto &it : cell.lutCell.pin_connections) {
-            log_info(" - %s : %s\n", it.first.c_str(ctx), LutCell::nameOfPinConnection(it.second).c_str());
-        }
-#endif
-
-        lut_mapping->cells.push_back(cell);
-    }
-
-    return true;
-}
-
-void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cell_to_bel_map, const LutBel &lut_bel,
-                    const std::vector<LogicLevel> &equation, uint32_t used_pins)
-{
-    std::vector<int8_t> pin_map;
-    pin_map.resize(lut_bel.pins.size(), -1);
-
-    NPNR_ASSERT(lut_cell.pins.size() < (size_t)std::numeric_limits<decltype(pin_map)::value_type>::max());
-
-    for (size_t cell_pin_idx = 0; cell_pin_idx < lut_cell.pins.size(); ++cell_pin_idx) {
-        IdString cell_pin = lut_cell.pins[cell_pin_idx];
-        IdString bel_pin = cell_to_bel_map.at(cell_pin);
-        size_t bel_pin_idx = lut_bel.pin_to_index.at(bel_pin);
-
-        pin_map[bel_pin_idx] = cell_pin_idx;
-    }
-
-    // Iterate over all BEL addresses in the LUT, and ensure that the original
-    // LUT equation is respected.
-    size_t bel_width = 1 << lut_bel.pins.size();
-    NPNR_ASSERT(lut_bel.low_bit + bel_width == lut_bel.high_bit + 1);
-    for (size_t bel_address = 0; bel_address < bel_width; ++bel_address) {
-        LogicLevel level = equation[bel_address + lut_bel.low_bit];
-
-        bool address_reachable = true;
-        size_t cell_address = 0;
-        for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) {
-            // This address line is 0, so don't translate this bit to the cell
-            // address.
-            if ((bel_address & (1 << bel_pin_idx)) == 0) {
-                // This pin is unused, so the line will be tied high, this
-                // address is unreachable.
-                if ((used_pins & (1 << bel_pin_idx)) == 0) {
-                    address_reachable = false;
-                    break;
-                }
-                continue;
-            }
-
-            auto cell_pin_idx = pin_map[bel_pin_idx];
-
-            // Is this BEL pin used for this cell?
-            if (cell_pin_idx < 0) {
-                // This BEL pin is not used for the LUT cell, skip
-                continue;
-            }
-
-            cell_address |= (1 << cell_pin_idx);
-        }
-
-        if (!address_reachable) {
-            continue;
-        }
-
-        if (lut_cell.equation.get(cell_address)) {
-            NPNR_ASSERT(level == LL_One);
-        } else {
-            NPNR_ASSERT(level == LL_Zero);
-        }
-    }
-}
-
-void LutElement::compute_pin_order()
-{
-    pins.clear();
-    pin_to_index.clear();
-
-    for (auto &lut_bel_pair : lut_bels) {
-        auto &lut_bel = lut_bel_pair.second;
-
-        for (size_t pin_idx = 0; pin_idx < lut_bel.pins.size(); ++pin_idx) {
-            IdString pin = lut_bel.pins[pin_idx];
-            auto result = pin_to_index.emplace(pin, pin_idx);
-            if (!result.second) {
-                // Not sure when this isn't true, but check it for now!
-                NPNR_ASSERT(result.first->second == pin_idx);
-            }
-        }
-    }
-
-    pins.resize(pin_to_index.size());
-    for (auto &pin_pair : pin_to_index) {
-        pins.at(pin_pair.second) = pin_pair.first;
-    }
-
-    for (auto &lut_bel_pair : lut_bels) {
-        auto &lut_bel = lut_bel_pair.second;
-        lut_bel.min_pin = pin_to_index.at(lut_bel.pins.front());
-        lut_bel.max_pin = pin_to_index.at(lut_bel.pins.back());
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h
deleted file mode 100644
index 892f457c19..0000000000
--- a/fpga_interchange/luts.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef LUTS_H
-#define LUTS_H
-
-#include "idstring.h"
-#include "nextpnr_namespaces.h"
-
-#include "dynamic_bitarray.h"
-#include "hashlib.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct CellInfo;
-struct Context;
-
-struct SiteLutMappingResult;
-
-enum LogicLevel
-{
-    LL_Zero,
-    LL_One,
-    LL_DontCare
-};
-
-struct LutCell
-{
-    enum class PinConnection
-    {
-        Unconnected,
-        Gnd,
-        Vcc,
-        Const,
-        Signal
-    };
-
-    // LUT cell pins for equation, LSB first.
-    std::vector<IdString> pins;
-    pool<IdString> lut_pins;
-    dict<IdString, PinConnection> pin_connections;
-    DynamicBitarray<> equation;
-
-    static const std::string nameOfPinConnection(PinConnection conn);
-};
-
-struct LutBel
-{
-    IdString name;
-
-    // LUT BEL pins to LUT array index.
-    std::vector<IdString> pins;
-    dict<IdString, size_t> pin_to_index;
-
-    IdString output_pin;
-
-    // What part of the LUT equation does this LUT output use?
-    // This assumes contiguous LUT bits.
-    uint32_t low_bit;
-    uint32_t high_bit;
-
-    int32_t min_pin;
-    int32_t max_pin;
-};
-
-struct SiteLutMapping
-{
-    struct LutCellMapping
-    {
-        LutCell lut_cell;
-    };
-};
-
-// Work forward from cell definition and cell -> bel pin map and check that
-// equation is valid.
-void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cell_to_bel_map, const LutBel &lut_bel,
-                    const std::vector<LogicLevel> &equation, uint32_t used_pins);
-
-struct LutElement
-{
-    size_t width;
-    dict<IdString, LutBel> lut_bels;
-
-    void compute_pin_order();
-
-    std::vector<IdString> pins;
-    dict<IdString, size_t> pin_to_index;
-};
-
-struct LutMapper
-{
-    LutMapper(const LutElement &element) : element(element) {}
-    const LutElement &element;
-
-    std::vector<CellInfo *> cells;
-
-    bool remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping,
-                    pool<const LutBel *, hash_ptr_ops> *blocked_luts);
-
-    // Determine which wires given the current mapping must be tied to the
-    // default constant.
-    //
-    // Returns a bit mask, 1 meaning it must be tied.   Otherwise means that
-    // the pin is free to be a signal.
-    uint32_t check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps,
-                         const std::vector<const LutBel *> &lut_bels, uint32_t used_pins,
-                         pool<const LutBel *, hash_ptr_ops> *blocked_luts) const;
-
-    // Version of check_wires that uses current state of cells based on pin
-    // mapping in cells variable.
-    uint32_t check_wires(const Context *ctx) const;
-};
-
-// Rotate and merge a LUT equation into an array of levels.
-//
-// If a conflict arises, return false and result is in an indeterminate state.
-bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel &lut_bel,
-                                   const DynamicBitarray<> &old_equation, const std::vector<size_t> &pin_map,
-                                   uint32_t used_pins);
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* LUTS_H */
diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc
deleted file mode 100644
index cc67833aba..0000000000
--- a/fpga_interchange/macros.cc
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "design_utils.h"
-#include "log.h"
-#include "nextpnr.h"
-#include "util.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-static const MacroPOD *lookup_macro(const ChipInfoPOD *chip, IdString cell_type)
-{
-    for (const auto &macro : chip->macros) {
-        if (IdString(macro.name) == cell_type)
-            return &macro;
-    }
-    return nullptr;
-}
-
-static const MacroExpansionPOD *lookup_macro_rules(const ChipInfoPOD *chip, IdString cell_type)
-{
-    for (const auto &rule : chip->macro_rules) {
-        if (IdString(rule.prim_name) == cell_type)
-            return &rule;
-    }
-    return nullptr;
-}
-
-static IdString derived_name(Context *ctx, IdString base_name, IdString suffix)
-{
-    return ctx->idf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx));
-}
-
-void Arch::expand_macros()
-{
-    log_info("Expand macros\n");
-    // Make up a list of cells, so we don't have modify-while-iterating issues
-    Context *ctx = getCtx();
-    std::vector<CellInfo *> cells;
-    for (auto &cell : ctx->cells)
-        cells.push_back(cell.second.get());
-
-    std::vector<CellInfo *> next_cells;
-
-    bool first_iter = false;
-    do {
-        // Expand cells
-        for (auto cell : cells) {
-            // TODO: consult exception map
-            const MacroExpansionPOD *exp = lookup_macro_rules(chip_info, cell->type);
-
-            // Block infinite expansion loop due to a macro being expanded in the same primitive.
-            // E.g.: OBUFTDS expands into the following cells, with an infinite loop being generated:
-            //          - 2 OBUFTDS
-            //          - 1 INV
-            if (exp && first_iter)
-                continue;
-
-            const MacroPOD *macro = lookup_macro(chip_info, exp ? IdString(exp->macro_name) : cell->type);
-            if (macro == nullptr)
-                continue;
-
-            // Get the ultimate root of this macro expansion
-            IdString parent = (cell->macro_parent == IdString()) ? cell->name : cell->macro_parent;
-            // Create child instances
-            for (const auto &inst : macro->cell_insts) {
-                CellInfo *inst_cell =
-                        ctx->createCell(derived_name(ctx, cell->name, IdString(inst.name)), IdString(inst.type));
-                for (const auto &param : inst.parameters) {
-                    inst_cell->params[IdString(param.key)] = IdString(param.value).str(ctx);
-                }
-                inst_cell->macro_parent = parent;
-                next_cells.push_back(inst_cell);
-            }
-            // Create and connect nets
-            for (const auto &net_data : macro->nets) {
-                NetInfo *net = nullptr;
-                // If there is a top level port, use that as the net
-                for (const auto &net_port : net_data.ports) {
-                    if (net_port.instance != 0)
-                        continue;
-                    // TODO: case of multiple top level ports on the same net?
-                    NPNR_ASSERT(net == nullptr);
-                    // Use the corresponding pre-expansion port net
-                    net = cell->getPort(IdString(net_port.port));
-                    // Disconnect the original port pre-expansion
-                    cell->disconnectPort(IdString(net_port.port));
-                }
-                // If not on a top level port, create a new net
-                if (net == nullptr)
-                    net = ctx->createNet(derived_name(ctx, cell->name, IdString(net_data.name)));
-                // Create and connect instance ports
-                for (const auto &net_port : net_data.ports) {
-                    if (net_port.instance == 0)
-                        continue;
-                    IdString port_name(net_port.port);
-                    CellInfo *inst_cell =
-                            ctx->cells.at(derived_name(ctx, cell->name, IdString(net_port.instance))).get();
-                    inst_cell->ports[port_name].name = port_name;
-                    inst_cell->ports[port_name].type = PortType(net_port.dir);
-                    inst_cell->connectPort(port_name, net);
-                }
-            }
-
-            if (exp != nullptr) {
-                // Convert parameters, according to the exception rules
-                for (const auto &param_rule : exp->param_rules) {
-                    IdString prim_param(param_rule.prim_param);
-                    if (!cell->params.count(prim_param))
-                        continue;
-                    const auto &prim_param_val = cell->params.at(prim_param);
-                    IdString inst_name = derived_name(ctx, cell->name, IdString(param_rule.inst_name));
-                    CellInfo *inst_cell = ctx->cells.at(inst_name).get();
-                    IdString inst_param(param_rule.inst_param);
-                    if (param_rule.rule_type == PARAM_MAP_COPY) {
-                        inst_cell->params[inst_param] = prim_param_val;
-                    } else if (param_rule.rule_type == PARAM_MAP_SLICE) {
-                        auto prim_bits = cell_parameters.parse_int_like(ctx, cell->type, prim_param, prim_param_val);
-                        Property value(0, param_rule.slice_bits.ssize());
-                        for (int i = 0; i < param_rule.slice_bits.ssize(); i++) {
-                            size_t bit = param_rule.slice_bits[i];
-                            if (bit >= prim_bits.size())
-                                continue;
-                            value.str.at(i) = prim_bits.get(bit) ? Property::S1 : Property::S0;
-                        }
-                        inst_cell->params[inst_param] = value;
-                    } else if (param_rule.rule_type == PARAM_MAP_TABLE) {
-                        const std::string &prim_str = prim_param_val.as_string();
-                        IdString prim_id = ctx->id(prim_str);
-                        for (auto &tbl_entry : param_rule.map_table) {
-                            if (IdString(tbl_entry.key) == prim_id) {
-                                inst_cell->params[inst_param] = IdString(tbl_entry.value).str(ctx);
-                                break;
-                            }
-                        }
-                        if (!inst_cell->params.count(inst_param))
-                            log_error("Unsupported value '%s' for property '%s' of cell %s:%s\n", prim_str.c_str(),
-                                      ctx->nameOf(prim_param), ctx->nameOf(cell), ctx->nameOf(cell->type));
-                    }
-                }
-            }
-
-            // Remove the now-expanded cell, but first make sure we don't leave behind any dangling references
-            for (const auto &port : cell->ports)
-                if (port.second.net != nullptr)
-                    log_error("Macro expansion of %s:%s left dangling port %s.", ctx->nameOf(cell),
-                              ctx->nameOf(cell->type), ctx->nameOf(port.first));
-            ctx->cells.erase(cell->name);
-        }
-
-        // Iterate until no more expansions are possible
-        // The next iteration only needs to look at cells created in this iteration
-        std::swap(next_cells, cells);
-        next_cells.clear();
-
-        first_iter = true;
-    } while (!cells.empty());
-    // Do this at the end, otherwise we might add cells that are later destroyed
-    for (auto &cell : ctx->cells)
-        macro_to_cells[cell.second->macro_parent].push_back(cell.second.get());
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/main.cc b/fpga_interchange/main.cc
deleted file mode 100644
index 5423c17d93..0000000000
--- a/fpga_interchange/main.cc
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2018  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifdef MAIN_EXECUTABLE
-
-#include <chrono>
-#include <fstream>
-
-#include "command.h"
-#include "design_utils.h"
-#include "jsonwrite.h"
-#include "log.h"
-#include "timing.h"
-
-USING_NEXTPNR_NAMESPACE
-
-class FpgaInterchangeCommandHandler : public CommandHandler
-{
-  public:
-    FpgaInterchangeCommandHandler(int argc, char **argv);
-    virtual ~FpgaInterchangeCommandHandler(){};
-    std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
-    void customBitstream(Context *ctx) override;
-    void customAfterLoad(Context *ctx) override;
-
-  protected:
-    po::options_description getArchOptions() override;
-};
-
-FpgaInterchangeCommandHandler::FpgaInterchangeCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
-
-po::options_description FpgaInterchangeCommandHandler::getArchOptions()
-{
-    po::options_description specific("Architecture specific options");
-    specific.add_options()("chipdb", po::value<std::string>(), "name of chip database binary");
-    specific.add_options()("xdc", po::value<std::vector<std::string>>(), "XDC-style constraints file to read");
-    specific.add_options()("netlist", po::value<std::string>(), "FPGA interchange logical netlist to read");
-    specific.add_options()("phys", po::value<std::string>(), "FPGA interchange Physical netlist to write");
-    specific.add_options()("package", po::value<std::string>(), "Package to use");
-    specific.add_options()("rebuild-lookahead", "Ignore lookahead cache and rebuild");
-    specific.add_options()("dont-write-lookahead", "Don't write the lookahead file");
-    specific.add_options()("disable-lut-mapping-cache", "Disable caching of LUT mapping solutions in site router");
-
-    return specific;
-}
-
-void FpgaInterchangeCommandHandler::customBitstream(Context *ctx)
-{
-    if (vm.count("phys")) {
-        std::string filename = vm["phys"].as<std::string>();
-        ctx->write_physical_netlist(filename);
-    }
-}
-
-std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(dict<std::string, Property> &values)
-{
-    auto start = std::chrono::high_resolution_clock::now();
-
-    ArchArgs chipArgs;
-    chipArgs.rebuild_lookahead = vm.count("rebuild_lookahead") != 0;
-    chipArgs.dont_write_lookahead = vm.count("dont_write_lookahead") != 0;
-    chipArgs.disable_lut_mapping_cache = vm.count("disable-lut-mapping-cache") != 0;
-
-    if (!vm.count("chipdb")) {
-        log_error("chip database binary must be provided\n");
-    }
-    chipArgs.chipdb = vm["chipdb"].as<std::string>();
-    if (vm.count("package")) {
-        chipArgs.package = vm["package"].as<std::string>();
-    }
-
-    auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
-
-    if (vm.count("verbose")) {
-        ctx->verbose = true;
-    }
-    if (vm.count("debug")) {
-        ctx->verbose = true;
-        ctx->debug = true;
-    }
-
-    ctx->init();
-
-    if (vm.count("netlist")) {
-        ctx->read_logical_netlist(vm["netlist"].as<std::string>());
-    }
-
-    if (vm.count("xdc")) {
-        for (auto &x : vm["xdc"].as<std::vector<std::string>>()) {
-            ctx->parse_xdc(x);
-        }
-    }
-
-    auto end = std::chrono::high_resolution_clock::now();
-    log_info("createContext time %.02fs\n", std::chrono::duration<float>(end - start).count());
-
-    return ctx;
-}
-
-void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx) {}
-
-int main(int argc, char *argv[])
-{
-    FpgaInterchangeCommandHandler handler(argc, argv);
-    return handler.exec();
-}
-
-#endif
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc
deleted file mode 100644
index 0b76736922..0000000000
--- a/fpga_interchange/pseudo_pip_model.cc
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "pseudo_pip_model.h"
-
-#include "context.h"
-
-// #define DEBUG_PSEUDO_PIP
-
-NEXTPNR_NAMESPACE_BEGIN
-
-void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type)
-{
-    if (max_pseudo_pip_for_tile_type.count(tile_type)) {
-        return;
-    }
-
-    const TileTypeInfoPOD &type_data = ctx->chip_info->tile_types[tile_type];
-    int32_t max_pseudo_pip_index = -1;
-    for (int32_t pip_idx = 0; pip_idx < type_data.pip_data.ssize(); ++pip_idx) {
-        const PipInfoPOD &pip_data = type_data.pip_data[pip_idx];
-        if (pip_data.pseudo_cell_wires.size() == 0) {
-            continue;
-        }
-
-        if (pip_idx > max_pseudo_pip_index) {
-            max_pseudo_pip_index = pip_idx;
-        }
-
-        pool<size_t> sites;
-        std::vector<PseudoPipBel> pseudo_pip_bels;
-        for (int32_t wire_index : pip_data.pseudo_cell_wires) {
-            const TileWireInfoPOD &wire_data = type_data.wire_data[wire_index];
-            if (wire_data.site == -1) {
-                continue;
-            }
-
-            // Only use primary site types for psuedo pips
-            //
-            // Note: This assumption may be too restrictive.  If so, then
-            // need to update database generators to provide
-            // pseudo_cell_wires for each site type, not just the primary.
-            if (wire_data.site_variant != -1) {
-                continue;
-            }
-
-            sites.emplace(wire_data.site);
-
-            for (const BelPortPOD &bel_pin : wire_data.bel_pins) {
-                const BelInfoPOD &bel_data = type_data.bel_data[bel_pin.bel_index];
-                if (bel_data.synthetic != NOT_SYNTH) {
-                    // Ignore synthetic BELs
-                    continue;
-                }
-
-                if (bel_data.category != BEL_CATEGORY_LOGIC) {
-                    // Ignore site ports and site routing
-                    continue;
-                }
-
-                int32_t bel_pin_idx = -1;
-                for (int32_t i = 0; i < bel_data.num_bel_wires; ++i) {
-                    if (bel_data.ports[i] == bel_pin.port) {
-                        bel_pin_idx = i;
-                        break;
-                    }
-                }
-
-                NPNR_ASSERT(bel_pin_idx != -1);
-                if (bel_data.types[bel_pin_idx] != PORT_OUT) {
-                    // Only care about output ports.  Input ports may not be
-                    // part of the pseudo pip.
-                    continue;
-                }
-
-                PseudoPipBel bel;
-                bel.bel_index = bel_pin.bel_index;
-                bel.output_bel_pin = bel_pin_idx;
-                pseudo_pip_bels.push_back(bel);
-            }
-        }
-
-        std::pair<int32_t, int32_t> key{tile_type, pip_idx};
-        std::vector<size_t> &sites_for_pseudo_pip = possibles_sites_for_pip[key];
-        sites_for_pseudo_pip.clear();
-        sites_for_pseudo_pip.insert(sites_for_pseudo_pip.begin(), sites.begin(), sites.end());
-        std::sort(sites_for_pseudo_pip.begin(), sites_for_pseudo_pip.end());
-
-        // Initialize "logic_bels_for_pip" for every site that this pseudo pip
-        // appears.  This means that if there are no pseudo_pip_bels, those
-        // vectors will be empty.
-        for (int32_t site : sites_for_pseudo_pip) {
-            logic_bels_for_pip[LogicBelKey{tile_type, pip_idx, site}].clear();
-        }
-
-        if (!pseudo_pip_bels.empty()) {
-            pool<int32_t> pseudo_cell_wires;
-            pseudo_cell_wires.insert(pip_data.pseudo_cell_wires.begin(), pip_data.pseudo_cell_wires.end());
-
-            // For each BEL, find the input bel pin used, and attach it to
-            // the vector for that site.
-            //
-            // Note: Intentially copying the bel for mutation, and then
-            // pushing onto vector.
-            for (PseudoPipBel bel : pseudo_pip_bels) {
-                const BelInfoPOD &bel_data = type_data.bel_data[bel.bel_index];
-                int32_t site = bel_data.site;
-
-                int32_t input_bel_pin = -1;
-                int32_t output_bel_pin = -1;
-                for (int32_t i = 0; i < bel_data.num_bel_wires; ++i) {
-                    if (!pseudo_cell_wires.count(bel_data.wires[i])) {
-                        continue;
-                    }
-
-                    if (bel_data.types[i] == PORT_OUT) {
-                        NPNR_ASSERT(output_bel_pin == -1);
-                        output_bel_pin = i;
-                    }
-
-                    if (bel_data.types[i] == PORT_IN && input_bel_pin == -1) {
-                        // Take first input BEL pin
-                        //
-                        // FIXME: This heuristic feels fragile.
-                        // This data oaught come from the database.
-                        input_bel_pin = i;
-                    }
-                }
-
-                NPNR_ASSERT(output_bel_pin == bel.output_bel_pin);
-                bel.input_bel_pin = input_bel_pin;
-
-                logic_bels_for_pip[LogicBelKey{tile_type, pip_idx, site}].push_back(bel);
-            }
-        }
-    }
-
-    max_pseudo_pip_for_tile_type[tile_type] = max_pseudo_pip_index;
-}
-
-const std::vector<size_t> &PseudoPipData::get_possible_sites_for_pip(const Context *ctx, PipId pip) const
-{
-    int32_t tile_type = ctx->chip_info->tiles[pip.tile].type;
-    return possibles_sites_for_pip.at(std::make_pair(tile_type, pip.index));
-}
-
-size_t PseudoPipData::get_max_pseudo_pip(int32_t tile_type) const { return max_pseudo_pip_for_tile_type.at(tile_type); }
-
-const std::vector<PseudoPipBel> &PseudoPipData::get_logic_bels_for_pip(const Context *ctx, int32_t site,
-                                                                       PipId pip) const
-{
-    int32_t tile_type = ctx->chip_info->tiles[pip.tile].type;
-    return logic_bels_for_pip.at(LogicBelKey{tile_type, pip.index, site});
-}
-
-void PseudoPipModel::init(Context *ctx, int32_t tile_idx)
-{
-    int32_t tile_type = ctx->chip_info->tiles[tile_idx].type;
-
-    this->tile = tile_idx;
-
-    allowed_pseudo_pips.resize(ctx->pseudo_pip_data.get_max_pseudo_pip(tile_type) + 1);
-    allowed_pseudo_pips.fill(true);
-}
-
-void PseudoPipModel::prepare_for_routing(const Context *ctx, const std::vector<SiteRouter> &sites)
-{
-    // First determine which sites have placed cells, these sites are consider
-    // active.
-    pool<size_t> active_sites;
-    for (size_t site = 0; site < sites.size(); ++site) {
-        if (!sites[site].cells_in_site.empty()) {
-            active_sites.emplace(site);
-        }
-    }
-
-    // Assign each pseudo pip in this tile a site, which is either the active
-    // site (if the site / alt site is in use) or the first site that pseudo
-    // pip appears in.
-    int32_t tile_type = ctx->chip_info->tiles[tile].type;
-    const TileTypeInfoPOD &type_data = ctx->chip_info->tile_types[tile_type];
-
-    pseudo_pip_sites.clear();
-    site_to_pseudo_pips.clear();
-
-    for (size_t pip_idx = 0; pip_idx < type_data.pip_data.size(); ++pip_idx) {
-        const PipInfoPOD &pip_data = type_data.pip_data[pip_idx];
-        if (pip_data.pseudo_cell_wires.size() == 0) {
-            continue;
-        }
-
-        PipId pip;
-        pip.tile = tile;
-        pip.index = pip_idx;
-        const std::vector<size_t> &sites = ctx->pseudo_pip_data.get_possible_sites_for_pip(ctx, pip);
-
-        int32_t site_for_pip = -1;
-        for (size_t possible_site : sites) {
-            if (active_sites.count(possible_site)) {
-                site_for_pip = possible_site;
-                break;
-            }
-        }
-
-        if (site_for_pip < 0) {
-            site_for_pip = sites.at(0);
-        }
-
-        pseudo_pip_sites[pip_idx] = site_for_pip;
-        site_to_pseudo_pips[site_for_pip].push_back(pip_idx);
-    }
-
-    for (auto &site_pair : site_to_pseudo_pips) {
-        update_site(ctx, site_pair.first);
-    }
-}
-
-bool PseudoPipModel::checkPipAvail(const Context *ctx, PipId pip) const
-{
-    bool allowed = allowed_pseudo_pips.get(pip.index);
-    if (!allowed) {
-#ifdef DEBUG_PSEUDO_PIP
-        if (ctx->verbose) {
-            log_info("Pseudo pip %s not allowed\n", ctx->nameOfPip(pip));
-        }
-#endif
-    }
-
-    return allowed;
-}
-
-void PseudoPipModel::bindPip(const Context *ctx, PipId pip)
-{
-    // If pseudo_pip_sites is empty, then prepare_for_routing was never
-    // invoked.  This is likely because PseudoPipModel was constructed during
-    // routing.
-    if (pseudo_pip_sites.empty()) {
-        prepare_for_routing(ctx, ctx->tileStatus.at(tile).sites);
-    }
-
-    // Do not allow pseudo pips to be bound if they are not allowed!
-    NPNR_ASSERT(allowed_pseudo_pips.get(pip.index));
-
-    // Mark that this pseudo pip is active.
-    auto result = active_pseudo_pips.emplace(pip.index);
-    NPNR_ASSERT(result.second);
-
-    // Update the site this pseudo pip is within.
-    size_t site = pseudo_pip_sites.at(pip.index);
-    update_site(ctx, site);
-}
-
-void PseudoPipModel::unbindPip(const Context *ctx, PipId pip)
-{
-    // It should not be possible for unbindPip to be invoked with
-    // pseudo_pip_sites being empty.
-    NPNR_ASSERT(!pseudo_pip_sites.empty());
-
-    NPNR_ASSERT(active_pseudo_pips.erase(pip.index));
-
-    // Remove the site this pseudo pip is within.
-    size_t site = pseudo_pip_sites.at(pip.index);
-    update_site(ctx, site);
-}
-
-void PseudoPipModel::update_site(const Context *ctx, size_t site)
-{
-    // update_site consists of several steps:
-    //
-    //  - Find all BELs within the site used by pseudo pips.
-    //  - Trivially marking other pseudo pips as unavailable if it requires
-    //    logic BELs used by active pseudo pips (or bound by cells).
-    //  - Determine if remaining pseudo pips can be legally placed.  This
-    //    generally consists of:
-    //     - Checking LUT element
-    //     - FIXME: Checking constraints (when metadata is available)
-
-    const std::vector<int32_t> pseudo_pips_for_site = site_to_pseudo_pips.at(site);
-
-    std::vector<int32_t> &unused_pseudo_pips = scratch;
-    unused_pseudo_pips.clear();
-    unused_pseudo_pips.reserve(pseudo_pips_for_site.size());
-
-    dict<int32_t, PseudoPipBel> used_bels;
-    for (int32_t pseudo_pip : pseudo_pips_for_site) {
-        if (!active_pseudo_pips.count(pseudo_pip)) {
-            unused_pseudo_pips.push_back(pseudo_pip);
-            continue;
-        }
-
-        PipId pip;
-        pip.tile = tile;
-        pip.index = pseudo_pip;
-        for (const PseudoPipBel &bel : ctx->pseudo_pip_data.get_logic_bels_for_pip(ctx, site, pip)) {
-            used_bels.emplace(bel.bel_index, bel);
-        }
-    }
-
-    if (unused_pseudo_pips.empty()) {
-        return;
-    }
-
-    int32_t tile_type = ctx->chip_info->tiles[tile].type;
-    const TileTypeInfoPOD &type_data = ctx->chip_info->tile_types[tile_type];
-
-    // This section builds up LUT mapping logic to determine which LUT wires
-    // are availble and which are not.
-    const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(tile_type);
-    std::vector<LutMapper> lut_mappers;
-    lut_mappers.reserve(lut_elements.size());
-    for (size_t i = 0; i < lut_elements.size(); ++i) {
-        lut_mappers.push_back(LutMapper(lut_elements[i]));
-    }
-
-    const TileStatus &tile_status = ctx->tileStatus.at(tile);
-    for (CellInfo *cell : tile_status.sites[site].cells_in_site) {
-        if (cell->lut_cell.pins.empty()) {
-            continue;
-        }
-
-        BelId bel = cell->bel;
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-        if (bel_data.lut_element != -1) {
-            lut_mappers[bel_data.lut_element].cells.push_back(cell);
-        }
-    }
-
-    std::vector<CellInfo> lut_thru_cells;
-    lut_thru_cells.reserve(tile_status.sites[site].lut_thrus.size());
-    for (auto input_bel_pin : tile_status.sites[site].lut_thrus) {
-        if (ctx->wire_lut == nullptr)
-            break;
-
-        BelId bel;
-        bel.index = input_bel_pin.second;
-        bel.tile = tile;
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-
-        NPNR_ASSERT(bel_data.lut_element != -1);
-
-        lut_thru_cells.emplace_back(nullptr, IdString(), IdString(ctx->wire_lut->cell));
-        CellInfo &cell = lut_thru_cells.back();
-
-        cell.bel = bel;
-
-        NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
-        cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));
-
-        cell.lut_cell.equation.resize(2);
-        cell.lut_cell.equation.set(0, false);
-        cell.lut_cell.equation.set(1, true);
-
-        cell.cell_bel_pins[IdString(ctx->wire_lut->input_pins[0])].push_back(input_bel_pin.first);
-
-        lut_mappers[bel_data.lut_element].cells.push_back(&cell);
-    }
-
-    std::vector<CellInfo> lut_cells;
-    lut_cells.reserve(used_bels.size());
-    for (const auto &bel_pair : used_bels) {
-        const PseudoPipBel &bel = bel_pair.second;
-        const BelInfoPOD &bel_data = type_data.bel_data[bel.bel_index];
-
-        // This used BEL isn't a LUT, skip it!
-        if (bel_data.lut_element == -1) {
-            continue;
-        }
-
-        lut_cells.emplace_back(nullptr, IdString(), ctx->wire_lut ? IdString(ctx->wire_lut->cell) : IdString());
-        CellInfo &cell = lut_cells.back();
-
-        cell.bel.tile = tile;
-        cell.bel.index = bel_pair.first;
-
-        if (ctx->wire_lut == nullptr)
-            continue;
-
-        NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1);
-        cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0]));
-
-        if (bel.input_bel_pin == -1) {
-            // FIXME: currently assume that LUT route-throughs with no input pins are GND drivers as this is all we need
-            // for Nexus/Xilinx where Vcc is readily available and cheap This won't be true for other arches
-            cell.lut_cell.equation.resize(2);
-            cell.lut_cell.equation.set(0, false);
-            cell.lut_cell.equation.set(1, false);
-        } else {
-            cell.lut_cell.equation.resize(2);
-            cell.lut_cell.equation.set(0, false);
-            cell.lut_cell.equation.set(1, true);
-
-            // Map LUT input to input wire used by pseudo pip.
-            IdString input_bel_pin(bel_data.ports[bel.input_bel_pin]);
-            cell.cell_bel_pins[IdString(ctx->wire_lut->input_pins[0])].push_back(input_bel_pin);
-        }
-
-        lut_mappers[bel_data.lut_element].cells.push_back(&cell);
-    }
-
-    std::vector<uint32_t> lut_wires_unavailable;
-    lut_wires_unavailable.reserve(lut_elements.size());
-    for (LutMapper &lut_mapper : lut_mappers) {
-        lut_wires_unavailable.push_back(lut_mapper.check_wires(ctx));
-    }
-
-    // For unused pseudo pips, see if the BEL used is idle.
-    for (int32_t pseudo_pip : unused_pseudo_pips) {
-        PipId pip;
-        pip.tile = tile;
-        pip.index = pseudo_pip;
-
-        bool blocked_by_bel = false;
-        const std::vector<PseudoPipBel> &bels = ctx->pseudo_pip_data.get_logic_bels_for_pip(ctx, site, pip);
-        for (const PseudoPipBel &bel : bels) {
-            if (tile_status.boundcells[bel.bel_index] != nullptr) {
-                blocked_by_bel = true;
-
-#ifdef DEBUG_PSEUDO_PIP
-                if (ctx->verbose) {
-                    BelId abel;
-                    abel.tile = tile;
-                    abel.index = bel.bel_index;
-                    log_info("Pseudo pip %s is block by a bound BEL %s\n", ctx->nameOfPip(pip), ctx->nameOfBel(abel));
-                }
-#endif
-                break;
-            }
-
-            if (used_bels.count(bel.bel_index)) {
-#ifdef DEBUG_PSEUDO_PIP
-                if (ctx->verbose) {
-                    log_info("Pseudo pip %s is block by another pseudo pip\n", ctx->nameOfPip(pip));
-                }
-#endif
-                blocked_by_bel = true;
-                break;
-            }
-        }
-
-        bool blocked_by_lut_eq = false;
-
-        // See if any BELs are part of a LUT element.  If so, see if using
-        // that pseudo pip violates the LUT element equation.
-        for (const PseudoPipBel &bel : bels) {
-            const BelInfoPOD &bel_data = type_data.bel_data[bel.bel_index];
-            if (bel_data.lut_element == -1) {
-                continue;
-            }
-
-            // FIXME: Check if the pseudo cell satifies the constraint system.
-            // Will become important for LUT-RAM/SRL testing.
-
-            // FIXME: This lookup is static, consider moving to PseudoPipBel?
-            IdString bel_name(bel_data.name);
-            if (bel.input_bel_pin == -1) {
-                // No input bel pin (e.g. LUT as constant driver) - check that *any* input is available, i.e. there is
-                // some room in the LUT equation still
-                size_t pin_count = lut_elements.at(bel_data.lut_element).lut_bels.at(bel_name).pins.size();
-                uint32_t pin_mask = (1 << uint32_t(pin_count)) - 1;
-                uint32_t blocked_inputs = lut_wires_unavailable.at(bel_data.lut_element);
-                if ((blocked_inputs & pin_mask) == pin_mask) {
-                    blocked_by_lut_eq = true;
-                    break;
-                }
-            } else {
-                IdString input_bel_pin(bel_data.ports[bel.input_bel_pin]);
-                size_t pin_idx =
-                        lut_elements.at(bel_data.lut_element).lut_bels.at(bel_name).pin_to_index.at(input_bel_pin);
-
-                uint32_t blocked_inputs = lut_wires_unavailable.at(bel_data.lut_element);
-                if ((blocked_inputs & (1 << pin_idx)) != 0) {
-                    blocked_by_lut_eq = true;
-                    break;
-                }
-            }
-        }
-
-#ifdef DEBUG_PSEUDO_PIP
-        if (blocked_by_lut_eq && ctx->verbose) {
-            log_info("Pseudo pip %s is blocked by invalid LUT equation\n", ctx->nameOfPip(pip));
-        }
-#endif
-
-        // Pseudo pip should be allowed, mark as such.
-        //
-        // FIXME: Handle non-LUT constraint cases, as needed.
-        bool allow_pip = !blocked_by_lut_eq && !blocked_by_bel;
-        allowed_pseudo_pips.set(pseudo_pip, allow_pip);
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/pseudo_pip_model.h b/fpga_interchange/pseudo_pip_model.h
deleted file mode 100644
index b0e28059d5..0000000000
--- a/fpga_interchange/pseudo_pip_model.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef PSEUDO_PIP_MODEL_H
-#define PSEUDO_PIP_MODEL_H
-
-#include <tuple>
-
-#include "dynamic_bitarray.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-#include "site_router.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct PseudoPipBel
-{
-    // Which BEL in the tile does the pseudo pip use?
-    int32_t bel_index;
-
-    // What is the index of the input BEL pin that the pseudo pip used?
-    //
-    // NOTE: This is **not** the name of the pin.
-    int32_t input_bel_pin;
-
-    // What is the index of the output BEL pin that the pseudo pip used?
-    //
-    // NOTE: This is **not** the name of the pin.
-    int32_t output_bel_pin;
-};
-
-struct LogicBelKey
-{
-    int32_t tile_type;
-    int32_t pip_index;
-    int32_t site;
-
-    std::tuple<int32_t, int32_t, int32_t> make_tuple() const { return std::make_tuple(tile_type, pip_index, site); }
-
-    bool operator==(const LogicBelKey &other) const { return make_tuple() == other.make_tuple(); }
-
-    bool operator<(const LogicBelKey &other) const { return make_tuple() < other.make_tuple(); }
-
-    unsigned int hash() const { return mkhash(mkhash(tile_type, pip_index), site); }
-};
-
-// Storage for tile type generic pseudo pip data and lookup.
-struct PseudoPipData
-{
-    // Initial data for specified tile type, if not already initialized.
-    void init_tile_type(const Context *ctx, int32_t tile_type);
-
-    // Get the highest PipId::index found in a specified tile type.
-    size_t get_max_pseudo_pip(int32_t tile_type) const;
-
-    // Get the list of possible sites that a pseudo pip might be used in.
-    const std::vector<size_t> &get_possible_sites_for_pip(const Context *ctx, PipId pip) const;
-
-    // Get list of BELs the pseudo pip uses, and how it routes through them.
-    //
-    // This does **not** include site ports or site pips.
-    const std::vector<PseudoPipBel> &get_logic_bels_for_pip(const Context *ctx, int32_t site, PipId pip) const;
-
-    dict<int32_t, size_t> max_pseudo_pip_for_tile_type;
-    dict<std::pair<int32_t, int32_t>, std::vector<size_t>> possibles_sites_for_pip;
-    dict<LogicBelKey, std::vector<PseudoPipBel>> logic_bels_for_pip;
-};
-
-// Tile instance fast pseudo pip lookup.
-struct PseudoPipModel
-{
-    int32_t tile;
-    DynamicBitarray<> allowed_pseudo_pips;
-    dict<int32_t, size_t> pseudo_pip_sites;
-    dict<size_t, std::vector<int32_t>> site_to_pseudo_pips;
-    pool<int32_t> active_pseudo_pips;
-    std::vector<int32_t> scratch;
-
-    // Call when a tile is initialized.
-    void init(Context *ctx, int32_t tile);
-
-    // Call after placement but before routing to update which pseudo pips are
-    // legal.  This call is important to ensure that checkPipAvail returns the
-    // correct value.
-    //
-    // If the tile has no placed elements, then prepare_for_routing does not
-    // need to be called after init.
-    void prepare_for_routing(const Context *ctx, const std::vector<SiteRouter> &sites);
-
-    // Returns true if the pseudo pip is allowed given current site placements
-    // and other pseudo pips.
-    bool checkPipAvail(const Context *ctx, PipId pip) const;
-
-    // Enables a pseudo pip in the model.  May cause other pseudo pips to
-    // become unavailable.
-    void bindPip(const Context *ctx, PipId pip);
-
-    // Removes a pseudo pip from the model.  May cause other pseudo pips to
-    // become available.
-    void unbindPip(const Context *ctx, PipId pip);
-
-    // Internal method to update pseudo pips marked as part of a site.
-    void update_site(const Context *ctx, size_t site);
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* PSEUDO_PIP_MODEL_H */
diff --git a/fpga_interchange/sampler.cc b/fpga_interchange/sampler.cc
deleted file mode 100644
index 0868867e47..0000000000
--- a/fpga_interchange/sampler.cc
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "sampler.h"
-#include <algorithm>
-#include <cmath>
-#include <stdexcept>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-static size_t partition_x(std::vector<size_t>::iterator begin, std::vector<size_t>::iterator end,
-                          const std::vector<std::pair<int32_t, int32_t>> &samples)
-{
-    if (std::distance(begin, end) == 0) {
-        return 0;
-    }
-
-    // Find the median x value.
-    std::vector<int32_t> xs;
-    xs.reserve(std::distance(begin, end));
-
-    for (auto iter = begin; iter != end; ++iter) {
-        xs.push_back(samples[*iter].first);
-    }
-
-    std::sort(xs.begin(), xs.end());
-    xs.erase(std::unique(xs.begin(), xs.end()), xs.end());
-
-    // Partion on the median x value (e.g. 50% of samples on one side and
-    // 50% of samples on the other side).
-    int32_t x_div = xs[(xs.size() - 1) / 2];
-
-    auto split = std::partition(begin, end,
-                                [x_div, &samples](size_t index) -> bool { return samples[index].first <= x_div; });
-
-    return std::distance(begin, split);
-}
-
-/* Don't both splitting when the partition has less than kMinSplit. */
-static constexpr ptrdiff_t kMinSplit = 20;
-
-static size_t partition_y(std::vector<size_t>::iterator begin, std::vector<size_t>::iterator end,
-                          const std::vector<std::pair<int32_t, int32_t>> &samples)
-{
-    if (std::distance(begin, end) == 0) {
-        return 0;
-    }
-
-    std::vector<int32_t> ys;
-    ys.reserve(std::distance(begin, end));
-
-    for (auto iter = begin; iter != end; ++iter) {
-        ys.push_back(samples[*iter].second);
-    }
-
-    std::sort(ys.begin(), ys.end());
-    ys.erase(std::unique(ys.begin(), ys.end()), ys.end());
-
-    int32_t y_div = ys[(ys.size() - 1) / 2];
-
-    auto split = std::partition(begin, end,
-                                [y_div, &samples](size_t index) -> bool { return samples[index].second <= y_div; });
-
-    return std::distance(begin, split);
-}
-
-static void add_split(std::vector<size_t> *splits, size_t new_split)
-{
-    if (splits->back() < new_split) {
-        splits->push_back(new_split);
-    } else if (splits->back() != new_split) {
-        throw std::runtime_error("Split is not consectutive!");
-    }
-}
-
-void Sampler::divide_samples(size_t target_sample_count, const std::vector<std::pair<int32_t, int32_t>> &samples)
-{
-    // Initialize indicies lookup and make 1 split with entire sample range.
-    indicies.resize(samples.size());
-    for (size_t i = 0; i < samples.size(); ++i) {
-        indicies[i] = i;
-    }
-
-    splits.reserve(2);
-    splits.push_back(0);
-    splits.push_back(samples.size());
-
-    size_t divisions = std::ceil(std::sqrt(target_sample_count) / 2.);
-    if (divisions == 0) {
-        throw std::runtime_error("Math failure, unreachable!");
-    }
-
-    if (divisions > samples.size()) {
-        // Handle cases where there are few samples.
-        return;
-    }
-
-    // Recursively split samples first 50% / 50% in x direction, and then
-    // 50% / 50% in y direction.  Repeat until the bucket is smaller than
-    // kMinSplit or the samples have been divided `divisions` times.
-    std::vector<size_t> new_splits;
-    for (size_t division_count = 0; division_count < divisions; ++division_count) {
-        new_splits.clear();
-        new_splits.push_back(0);
-        for (size_t i = 0; i < splits.size() - 1; ++i) {
-            size_t split_begin = splits.at(i);
-            size_t split_end = splits.at(i + 1);
-            if (split_end > indicies.size()) {
-                throw std::runtime_error("split_end is not valid!");
-            }
-            if (split_begin >= split_end) {
-                throw std::runtime_error("Invalid split from earlier pass!");
-            }
-
-            std::vector<size_t>::iterator begin = indicies.begin() + split_begin;
-            std::vector<size_t>::iterator end = indicies.begin() + split_end;
-
-            if (std::distance(begin, end) < kMinSplit) {
-                add_split(&new_splits, split_begin);
-                continue;
-            }
-
-            // Try to split samples 50/50 in x direction.
-            size_t split = partition_x(begin, end, samples);
-            // Try to split samples 50/50 in y direction after the x split.
-            size_t split_y1 = partition_y(begin, begin + split, samples);
-            size_t split_y2 = partition_y(begin + split, end, samples);
-
-            // Because the y2 split starts at split, add it here.
-            split_y2 += split;
-
-            add_split(&new_splits, split_begin);
-            add_split(&new_splits, split_begin + split_y1);
-            add_split(&new_splits, split_begin + split);
-            add_split(&new_splits, split_begin + split_y2);
-        }
-
-        add_split(&new_splits, samples.size());
-
-        if (new_splits.front() != 0) {
-            throw std::runtime_error("Split must start at 0");
-        }
-        if (new_splits.back() != samples.size()) {
-            throw std::runtime_error("Split must end at last element");
-        }
-
-        for (size_t i = 0; i < new_splits.size() - 1; ++i) {
-            if (new_splits[i] >= new_splits[i + 1]) {
-                throw std::runtime_error("Split indicies must be increasing");
-            }
-        }
-
-        std::swap(splits, new_splits);
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/sampler.h b/fpga_interchange/sampler.h
deleted file mode 100644
index e8475d45bc..0000000000
--- a/fpga_interchange/sampler.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SAMPLER_H_
-#define SAMPLER_H_
-
-#include <cstdint>
-#include <functional>
-#include <stdexcept>
-#include <vector>
-
-#include "nextpnr_namespaces.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-// Given a set of coordinates, generates random samples that are geometric
-// distributed.
-struct Sampler
-{
-
-    void divide_samples(size_t target_sample_count, const std::vector<std::pair<int32_t, int32_t>> &samples);
-
-    size_t number_of_regions() const { return splits.size() - 1; }
-
-    size_t get_sample_from_region(size_t region, std::function<int32_t()> rng) const
-    {
-        if (region >= (splits.size() - 1)) {
-            throw std::runtime_error("region out of range");
-        }
-        size_t split_begin = splits[region];
-        size_t split_end = splits[region + 1];
-        if (split_begin == split_end) {
-            throw std::runtime_error("Splits should never be empty!");
-        }
-
-        // Pick a random element from that region.
-        return indicies[split_begin + (rng() % (split_end - split_begin))];
-    }
-
-    size_t get_sample(std::function<int32_t()> rng) const
-    {
-        size_t region = rng() % number_of_regions();
-        return get_sample_from_region(region, rng);
-    }
-
-    std::vector<size_t> indicies;
-    std::vector<size_t> splits;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SAMPLER_H_ */
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
deleted file mode 100644
index d0a5c48c2e..0000000000
--- a/fpga_interchange/site_arch.cc
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "site_arch.h"
-#include "site_arch.impl.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-SiteInformation::SiteInformation(const Context *ctx, int32_t tile, int32_t site,
-                                 const pool<CellInfo *, hash_ptr_ops> &cells_in_site)
-        : ctx(ctx), tile(tile), tile_type(ctx->chip_info->tiles[tile].type), site(site), cells_in_site(cells_in_site)
-{
-}
-
-bool SiteArch::bindPip(const SitePip &pip, SiteNetInfo *net)
-{
-    SiteWire src = getPipSrcWire(pip);
-    SiteWire dst = getPipDstWire(pip);
-
-    if (!bindWire(src, net)) {
-        return false;
-    }
-    if (!bindWire(dst, net)) {
-        unbindWire(src);
-        return false;
-    }
-
-    auto result = net->wires.emplace(dst, SitePipMap{pip, 1});
-    if (!result.second) {
-        if (result.first->second.pip != pip) {
-            // Pip conflict!
-            if (debug()) {
-                log_info("Pip conflict binding pip %s to wire %s, conflicts with pip %s\n", nameOfPip(pip),
-                         nameOfWire(dst), nameOfPip(result.first->second.pip));
-            }
-
-            unbindWire(src);
-            unbindWire(dst);
-            return false;
-        }
-
-        result.first->second.count += 1;
-    }
-
-    if (debug()) {
-        log_info("Bound pip %s to wire %s\n", nameOfPip(pip), nameOfWire(dst));
-    }
-
-    return true;
-}
-
-void SiteArch::unbindPip(const SitePip &pip)
-{
-    SiteWire src = getPipSrcWire(pip);
-    SiteWire dst = getPipDstWire(pip);
-
-    if (debug()) {
-        log_info("Unbinding pip %s from wire %s\n", nameOfPip(pip), nameOfWire(dst));
-    }
-
-    SiteNetInfo *src_net = unbindWire(src);
-    SiteNetInfo *dst_net = unbindWire(dst);
-    NPNR_ASSERT(src_net == dst_net);
-    auto iter = dst_net->wires.find(dst);
-    NPNR_ASSERT(iter != dst_net->wires.end());
-    NPNR_ASSERT(iter->second.count >= 1);
-    iter->second.count -= 1;
-
-    if (iter->second.count == 0) {
-        dst_net->wires.erase(iter);
-    }
-}
-
-void SiteArch::archcheck()
-{
-    for (SiteWire wire : getWires()) {
-        for (SitePip pip : getPipsDownhill(wire)) {
-            SiteWire wire2 = getPipSrcWire(pip);
-            log_assert(wire == wire2);
-        }
-
-        for (SitePip pip : getPipsUphill(wire)) {
-            SiteWire wire2 = getPipDstWire(pip);
-            log_assert(wire == wire2);
-        }
-    }
-}
-
-SiteArch::SiteArch(const SiteInformation *site_info)
-        : ctx(site_info->ctx), site_info(site_info), blocking_net(site_info->ctx->id("$nextpnr_blocked_net"))
-{
-    // Build list of input and output site ports
-    //
-    // FIXME: This doesn't need to be computed over and over, move to
-    // arch/chip db.
-    const TileTypeInfoPOD &tile_type = loc_info(&site_info->chip_info(), *site_info);
-    PipId pip;
-    pip.tile = site_info->tile;
-    for (size_t pip_index = 0; pip_index < tile_type.pip_data.size(); ++pip_index) {
-        if (tile_type.pip_data[pip_index].site != site_info->site) {
-            continue;
-        }
-
-        pip.index = pip_index;
-
-        if (!site_info->is_site_port(pip)) {
-            continue;
-        }
-
-        WireId src_wire = ctx->getPipSrcWire(pip);
-        if (site_info->is_wire_in_site(src_wire)) {
-            output_site_ports.push_back(pip);
-        } else {
-            input_site_ports.push_back(pip);
-        }
-    }
-
-    // Create list of out of site sources and sinks.
-    bool have_vcc_pins = false;
-    bool have_gnd_pins = false;
-
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-
-    IdString const_net_name(ctx->chip_info->constants->best_constant_net);
-    NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
-
-    // FIXME: Use VCC if the architecture does not device the best constant
-    if (const_net_name == IdString()) {
-        const_net_name = vcc_net_name;
-    }
-
-    for (CellInfo *cell : site_info->cells_in_site) {
-        for (const auto &pin_pair : cell->cell_bel_pins) {
-            if (!cell->ports.count(pin_pair.first))
-                continue;
-            const PortInfo &port = cell->ports.at(pin_pair.first);
-            if (port.net != nullptr) {
-                nets.emplace(port.net, SiteNetInfo{port.net});
-            }
-        }
-
-        for (const auto &conn : cell->lut_cell.pin_connections) {
-            if (conn.second == LutCell::PinConnection::Vcc) {
-                have_vcc_pins = true;
-            } else if (conn.second == LutCell::PinConnection::Gnd) {
-                have_gnd_pins = true;
-            } else if (conn.second == LutCell::PinConnection::Const) {
-                if (const_net_name == vcc_net_name) {
-                    have_vcc_pins = true;
-                } else if (const_net_name == gnd_net_name) {
-                    have_gnd_pins = true;
-                }
-            }
-        }
-    }
-
-    for (auto &net_pair : nets) {
-        NetInfo *net = net_pair.first;
-        SiteNetInfo &net_info = net_pair.second;
-
-        // All nets require drivers
-        if (net->driver.cell == nullptr)
-            continue;
-
-        bool net_driven_out_of_site = false;
-        if (net->driver.cell->bel == BelId()) {
-            // The driver of this site hasn't been placed, so treat it as
-            // out of site.
-            out_of_site_sources.push_back(SiteWire::make(site_info, PORT_OUT, net));
-            net_info.driver = out_of_site_sources.back();
-            net_driven_out_of_site = true;
-        } else {
-            if (!site_info->is_bel_in_site(net->driver.cell->bel)) {
-
-                // The driver of this site has been placed, it is an out
-                // of site source.
-                out_of_site_sources.push_back(SiteWire::make(site_info, PORT_OUT, net));
-                // out_of_site_sources.back().wire = ctx->getNetinfoSourceWire(net);
-                net_info.driver = out_of_site_sources.back();
-
-                net_driven_out_of_site = true;
-            } else {
-                net_info.driver = SiteWire::make(site_info, ctx->getNetinfoSourceWire(net));
-            }
-        }
-
-        if (net_driven_out_of_site) {
-            // Because this net is driven from a source out of the site,
-            // no out of site sink is required.
-            continue;
-        }
-
-        // Examine net to determine if it has any users not in this site.
-        bool net_used_out_of_site = false;
-        for (const PortRef &user : net->users) {
-            NPNR_ASSERT(user.cell != nullptr);
-
-            if (user.cell->bel == BelId()) {
-                // Because this net has a user that has not been placed,
-                // and this net is being driven from this site, make sure
-                // this net can be routed from this site.
-                net_used_out_of_site = true;
-                break;
-            }
-
-            if (!site_info->is_bel_in_site(user.cell->bel)) {
-                net_used_out_of_site = true;
-                break;
-            }
-        }
-
-        if (net_used_out_of_site) {
-            out_of_site_sinks.push_back(SiteWire::make(site_info, PORT_IN, net));
-            net_info.users.emplace(out_of_site_sinks.back());
-        }
-    }
-
-    // At this point all nets have a driver SiteWire, but user SiteWire's
-    // within the site are not present.  Add them now.
-    for (auto &net_pair : nets) {
-        NetInfo *net = net_pair.first;
-        SiteNetInfo &net_info = net_pair.second;
-
-        for (const PortRef &user : net->users) {
-            if (!site_info->is_bel_in_site(user.cell->bel)) {
-                // Only care about BELs within the site at this point.
-                continue;
-            }
-
-            for (IdString bel_pin : ctx->getBelPinsForCellPin(user.cell, user.port)) {
-                SiteWire wire = getBelPinWire(user.cell->bel, bel_pin);
-                // Don't add users that are trivially routable!
-                if (wire != net_info.driver) {
-#ifdef DEBUG_SITE_ARCH
-                    if (ctx->debug) {
-                        log_info("Add user %s because it isn't driver %s\n", nameOfWire(wire),
-                                 nameOfWire(net_info.driver));
-                    }
-#endif
-                    net_info.users.emplace(wire);
-                }
-            }
-        }
-    }
-
-    NetInfo *vcc_net = ctx->nets.at(vcc_net_name).get();
-    auto vcc_iter = nets.find(vcc_net);
-    if (vcc_iter == nets.end() && have_vcc_pins) {
-        // VCC net isn't present, add it.
-        SiteNetInfo net_info;
-        net_info.net = vcc_net;
-        net_info.driver.type = SiteWire::OUT_OF_SITE_SOURCE;
-        net_info.driver.net = vcc_net;
-        auto result = nets.emplace(vcc_net, net_info);
-        NPNR_ASSERT(result.second);
-        vcc_iter = result.first;
-    }
-
-    NetInfo *gnd_net = ctx->nets.at(gnd_net_name).get();
-    auto gnd_iter = nets.find(gnd_net);
-    if (gnd_iter == nets.end() && have_gnd_pins) {
-        // GND net isn't present, add it.
-        SiteNetInfo net_info;
-        net_info.net = gnd_net;
-        net_info.driver.type = SiteWire::OUT_OF_SITE_SOURCE;
-        net_info.driver.net = gnd_net;
-        auto result = nets.emplace(gnd_net, net_info);
-        NPNR_ASSERT(result.second);
-        gnd_iter = result.first;
-    }
-
-    for (CellInfo *cell : site_info->cells_in_site) {
-        for (const auto &it : cell->lut_cell.pin_connections) {
-            const auto &pin = it.first;
-            const auto &conn = it.second;
-
-            if (conn == LutCell::PinConnection::Unconnected || conn == LutCell::PinConnection::Signal) {
-                continue;
-            }
-
-            if (conn == LutCell::PinConnection::Vcc) {
-                SiteWire wire = getBelPinWire(cell->bel, pin);
-                vcc_iter->second.users.emplace(wire);
-            } else if (conn == LutCell::PinConnection::Gnd) {
-                SiteWire wire = getBelPinWire(cell->bel, pin);
-                gnd_iter->second.users.emplace(wire);
-            } else if (conn == LutCell::PinConnection::Const) {
-                SiteWire wire = getBelPinWire(cell->bel, pin);
-                if (const_net_name == vcc_net_name) {
-                    vcc_iter->second.users.emplace(wire);
-                }
-                if (const_net_name == gnd_net_name) {
-                    gnd_iter->second.users.emplace(wire);
-                }
-            }
-
-#ifdef DEBUG_LUT_MAPPING
-            if (ctx->verbose) {
-                log_info("Tying %s.%s to %s\n", cell->name.c_str(ctx), pin.c_str(ctx),
-                         LutCell::nameOfPinConnection(conn).c_str());
-            }
-#endif
-        }
-    }
-
-    for (auto &net_pair : nets) {
-        if (net_pair.first->driver.cell == nullptr)
-            continue;
-        SiteNetInfo *net_info = &net_pair.second;
-        auto result = wire_to_nets.emplace(net_info->driver, SiteNetMap{net_info, 1});
-        // By this point, trivial congestion at sources should already by
-        // avoided, and there should be no duplicates in the
-        // driver/users data.
-        NPNR_ASSERT(result.second);
-
-        for (const auto &user : net_info->users) {
-            result = wire_to_nets.emplace(user, SiteNetMap{net_info, 1});
-            NPNR_ASSERT(result.second);
-        }
-    }
-
-    blocking_site_net.net = &blocking_net;
-}
-
-const char *SiteArch::nameOfWire(const SiteWire &wire) const
-{
-    switch (wire.type) {
-    case SiteWire::SITE_WIRE:
-        return ctx->nameOfWire(wire.wire);
-    case SiteWire::SITE_PORT_SINK:
-        return ctx->nameOfWire(wire.wire);
-    case SiteWire::SITE_PORT_SOURCE:
-        return ctx->nameOfWire(wire.wire);
-    case SiteWire::OUT_OF_SITE_SOURCE: {
-        std::string &str = ctx->log_strs.next();
-        str = stringf("Out of site source for net %s", wire.net->name.c_str(ctx));
-        return str.c_str();
-    }
-    case SiteWire::OUT_OF_SITE_SINK: {
-        std::string &str = ctx->log_strs.next();
-        str = stringf("Out of sink source for net %s", wire.net->name.c_str(ctx));
-        return str.c_str();
-    }
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-const char *SiteArch::nameOfPip(const SitePip &pip) const
-{
-    switch (pip.type) {
-    case SitePip::SITE_PIP:
-        return ctx->nameOfPip(pip.pip);
-    case SitePip::SITE_PORT:
-        return ctx->nameOfPip(pip.pip);
-    case SitePip::SOURCE_TO_SITE_PORT: {
-        std::string &str = ctx->log_strs.next();
-        str = stringf("Out of site source for net %s => %s", pip.wire.net->name.c_str(ctx),
-                      ctx->nameOfWire(ctx->getPipSrcWire(pip.pip)));
-        return str.c_str();
-    }
-    case SitePip::SITE_PORT_TO_SINK: {
-        std::string &str = ctx->log_strs.next();
-        str = stringf("%s => Out of site sink for net %s", ctx->nameOfWire(ctx->getPipDstWire(pip.pip)),
-                      pip.wire.net->name.c_str(ctx));
-        return str.c_str();
-    }
-    case SitePip::SITE_PORT_TO_SITE_PORT: {
-        std::string &str = ctx->log_strs.next();
-        str = stringf("%s => %s", ctx->nameOfWire(ctx->getPipSrcWire(pip.pip)),
-                      ctx->nameOfWire(ctx->getPipDstWire(pip.other_pip)));
-        return str.c_str();
-    }
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-const char *SiteArch::nameOfNet(const SiteNetInfo *net) const { return net->net->name.c_str(ctx); }
-
-bool SiteArch::debug() const { return ctx->debug; }
-
-SitePipUphillRange::SitePipUphillRange(const SiteArch *site_arch, SiteWire site_wire)
-        : site_arch(site_arch), site_wire(site_wire)
-{
-    switch (site_wire.type) {
-    case SiteWire::SITE_WIRE:
-        pip_range = site_arch->ctx->getPipsUphill(site_wire.wire);
-        break;
-    case SiteWire::OUT_OF_SITE_SOURCE:
-        // No normal pips!
-        break;
-    case SiteWire::OUT_OF_SITE_SINK:
-        // No normal pips!
-        break;
-    case SiteWire::SITE_PORT_SINK:
-        // No normal pips!
-        break;
-    case SiteWire::SITE_PORT_SOURCE:
-        // No normal pips!
-        break;
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-SitePip SitePipUphillIterator::operator*() const
-{
-    switch (state) {
-    case NORMAL_PIPS:
-        return SitePip::make(site_arch->site_info, *iter);
-    case PORT_SRC_TO_PORT_SINK:
-        return SitePip::make(site_arch->site_info, site_arch->output_site_ports.at(cursor), site_wire.pip);
-    case OUT_OF_SITE_SOURCES:
-        return SitePip::make(site_arch->site_info, site_arch->out_of_site_sources.at(cursor), site_wire.pip);
-    case OUT_OF_SITE_SINK_TO_PORT_SINK:
-        return SitePip::make(site_arch->site_info, site_arch->output_site_ports.at(cursor), site_wire);
-    case SITE_PORT:
-        return SitePip::make(site_arch->site_info, site_wire.pip);
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-SiteWire SiteWireIterator::operator*() const
-{
-    WireId wire;
-    PipId pip;
-    SiteWire site_wire;
-    switch (state) {
-    case NORMAL_WIRES:
-        wire.tile = site_arch->site_info->tile;
-        wire.index = cursor;
-        return SiteWire::make(site_arch->site_info, wire);
-    case INPUT_SITE_PORTS:
-        pip = site_arch->input_site_ports.at(cursor);
-        site_wire = SiteWire::make_site_port(site_arch->site_info, pip, /*dst_wire=*/false);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SOURCE);
-        return site_wire;
-    case OUTPUT_SITE_PORTS:
-        pip = site_arch->output_site_ports.at(cursor);
-        site_wire = SiteWire::make_site_port(site_arch->site_info, pip, /*dst_wire=*/true);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SINK);
-        return site_wire;
-    case OUT_OF_SITE_SOURCES:
-        return site_arch->out_of_site_sources.at(cursor);
-    case OUT_OF_SITE_SINKS:
-        return site_arch->out_of_site_sinks.at(cursor);
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-SiteWireIterator SiteWireRange::begin() const
-{
-    SiteWireIterator b;
-
-    b.state = SiteWireIterator::BEGIN;
-    b.site_arch = site_arch;
-    b.tile_type = &loc_info(&site_arch->site_info->chip_info(), *site_arch->site_info);
-
-    ++b;
-    return b;
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/site_arch.h b/fpga_interchange/site_arch.h
deleted file mode 100644
index 81c0b96c37..0000000000
--- a/fpga_interchange/site_arch.h
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_ARCH_H
-#define SITE_ARCH_H
-
-#include <cstdint>
-#include <vector>
-
-#include "PhysicalNetlist.capnp.h"
-#include "arch_iterators.h"
-#include "chipdb.h"
-#include "hashlib.h"
-#include "log.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-
-struct SiteInformation
-{
-    const Context *ctx;
-
-    const int32_t tile;
-    const int32_t tile_type;
-    const int32_t site;
-    const pool<CellInfo *, hash_ptr_ops> &cells_in_site;
-
-    SiteInformation(const Context *ctx, int32_t tile, int32_t site,
-                    const pool<CellInfo *, hash_ptr_ops> &cells_in_site);
-
-    inline const ChipInfoPOD &chip_info() const NPNR_ALWAYS_INLINE;
-
-    inline bool is_wire_in_site(WireId wire) const NPNR_ALWAYS_INLINE;
-
-    inline bool is_bel_in_site(BelId bel) const NPNR_ALWAYS_INLINE;
-
-    inline bool is_pip_part_of_site(PipId pip) const NPNR_ALWAYS_INLINE;
-
-    inline bool is_site_port(PipId pip) const NPNR_ALWAYS_INLINE;
-};
-
-// Site routing needs a modification of the routing graph.  Within the site,
-// the arch can be consulted for edges.  However the rest of the routing graph
-// needs to be reduced for analysis purposes.  Wires within the site are
-// SITE_WIRE's.  4 additional nodes are introduced to model out of site
-// routing:
-//  - OUT_OF_SITE_SOURCE / OUT_OF_SITE_SINK
-//   - These represent net sources and sinks that are only reachable via the
-//     routing graph (e.g. outside of the site).
-//  - SITE_PORT_SOURCE / SITE_PORT_SINK
-//   - These represent the routing resources connected to other side of site
-//     ports.
-//
-//  The non-site wire graph is connected like:
-//
-// ┌─────────────────┐                          ┌────────────────────┐
-// │                 │                          │                    │
-// │ OUT_OF_SITE_SRC │                          │  OUT_OF_SITE_SINK  │◄────┐
-// │                 │                          │                    │     │
-// └┬────────────────┘                          └────────────────────┘     │
-//  │                                                                      │
-//  │                ┌─────────────────────────────────────────────────────┤
-//  │                │                                                     │
-//  │                │                                                     │
-//  │                │                                                     │
-//  │                │                                                     │
-//  │                ▼                                                     │
-//  │      ┌─────────────────┐   ┌─────────────┐       ┌────────────────┐  │
-//  │      │                 │   │             │       │                │  │
-//  └─────►│  SITE_PORT_SRC  ├──►│    Site     ├──────►│ SITE_PORT_SINK ├──┘
-//         │                 │   │             │       │                │
-//         └─────────────────┘   └─────────────┘       └────────────────┘
-//
-struct SiteWire
-{
-    enum Type
-    {
-        // This wire is just a plain site wire.
-        SITE_WIRE = 0,
-        // This wire is a source that is from outside of the site.
-        OUT_OF_SITE_SOURCE = 1,
-        // This wire is a sink that is from outside of the site.
-        OUT_OF_SITE_SINK = 2,
-        // This wire is the routing graph wire on the dst side of a site port.
-        SITE_PORT_SINK = 3,
-        // This wire is the routing graph wire on the src side of a site port.
-        SITE_PORT_SOURCE = 4,
-        NUMBER_SITE_WIRE_TYPES = 5,
-    };
-
-    static inline SiteWire make(const SiteInformation *site_info, WireId site_wire) NPNR_ALWAYS_INLINE;
-
-    static SiteWire make(const SiteInformation *site_info, PortType port_type, NetInfo *net) NPNR_ALWAYS_INLINE
-    {
-        SiteWire out;
-        if (port_type == PORT_OUT) {
-            out.type = OUT_OF_SITE_SOURCE;
-            out.net = net;
-        } else {
-            out.type = OUT_OF_SITE_SINK;
-            out.net = net;
-        }
-        return out;
-    }
-
-    static inline SiteWire make_site_port(const SiteInformation *site_info, PipId pip, bool dst_wire);
-
-    bool operator==(const SiteWire &other) const
-    {
-        return wire == other.wire && type == other.type && pip == other.pip && net == other.net;
-    }
-    bool operator!=(const SiteWire &other) const
-    {
-        return wire != other.wire || type != other.type || pip != other.pip || net != other.net;
-    }
-    bool operator<(const SiteWire &other) const
-    {
-        return std::make_tuple(type, wire, pip, net) < std::make_tuple(other.type, other.wire, other.pip, other.net);
-    }
-
-    Type type = NUMBER_SITE_WIRE_TYPES;
-    WireId wire;
-    PipId pip;
-    NetInfo *net = nullptr;
-    unsigned int hash() const { return mkhash(mkhash(int(type), wire.hash()), mkhash(pip.hash(), uintptr_t(net))); }
-};
-
-struct SitePip
-{
-    enum Type
-    {
-        // This is a plain regular site pip.
-        SITE_PIP = 0,
-        // This pip is a site port, and connects a SITE_WIRE to a SITE_PORT_SINK/SITE_PORT_SRC
-        SITE_PORT = 1,
-        // This pip connects a OUT_OF_SITE_SOURCE to a SITE_PORT_SRC
-        SOURCE_TO_SITE_PORT = 2,
-        // This pip connects a SITE_PORT_SINK to a OUT_OF_SITE_SINK
-        SITE_PORT_TO_SINK = 3,
-        // This pip connects a SITE_PORT_SINK to a SITE_PORT_SRC.
-        SITE_PORT_TO_SITE_PORT = 4,
-        INVALID_TYPE = 5,
-    };
-
-    static inline SitePip make(const SiteInformation *site_info, PipId pip);
-
-    static SitePip make(const SiteInformation *site_info, SiteWire src, PipId dst)
-    {
-        NPNR_ASSERT(src.type == SiteWire::OUT_OF_SITE_SOURCE);
-
-        SitePip out;
-        out.type = SOURCE_TO_SITE_PORT;
-        out.pip = dst;
-        out.wire = src;
-
-        return out;
-    }
-
-    static SitePip make(const SiteInformation *site_info, PipId src, SiteWire dst)
-    {
-        NPNR_ASSERT(dst.type == SiteWire::OUT_OF_SITE_SINK);
-
-        SitePip out;
-        out.type = SITE_PORT_TO_SINK;
-        out.pip = src;
-        out.wire = dst;
-
-        return out;
-    }
-
-    static SitePip make(const SiteInformation *site_info, PipId src_pip, PipId dst_pip)
-    {
-        SitePip out;
-        out.type = SITE_PORT_TO_SITE_PORT;
-        out.pip = src_pip;
-        out.other_pip = dst_pip;
-
-        return out;
-    }
-
-    Type type = INVALID_TYPE;
-    // For SITE_PORT_TO_SITE_PORT connections, pip is the site -> routing pip.
-    PipId pip;
-    SiteWire wire;
-    // For SITE_PORT_TO_SITE_PORT connections, other_pip is the routing ->
-    // site pip.
-    PipId other_pip;
-
-    bool operator==(const SitePip &other) const
-    {
-        return type == other.type && pip == other.pip && wire == other.wire && other_pip == other.other_pip;
-    }
-    bool operator!=(const SitePip &other) const
-    {
-        return type != other.type || pip != other.pip || wire != other.wire || other_pip != other.other_pip;
-    }
-    unsigned int hash() const { return mkhash(mkhash(int(type), pip.hash()), mkhash(wire.hash(), other_pip.hash())); }
-};
-
-struct SitePipDownhillRange;
-struct SitePipUphillRange;
-struct SiteWireRange;
-struct SiteNetInfo;
-
-struct SitePipMap
-{
-    SitePip pip;
-    size_t count;
-};
-
-struct SiteNetMap
-{
-    SiteNetInfo *net;
-    size_t count;
-};
-
-struct SiteNetInfo
-{
-    NetInfo *net;
-    SiteWire driver;
-    pool<SiteWire> users;
-
-    dict<SiteWire, SitePipMap> wires;
-};
-
-struct SiteArch
-{
-    const Context *const ctx;
-    const SiteInformation *const site_info;
-
-    dict<NetInfo *, SiteNetInfo, hash_ptr_ops> nets;
-    dict<SiteWire, SiteNetMap> wire_to_nets;
-
-    NetInfo blocking_net;
-    SiteNetInfo blocking_site_net;
-
-    std::vector<PipId> input_site_ports;
-    std::vector<PipId> output_site_ports;
-
-    std::vector<SiteWire> out_of_site_sources;
-    std::vector<SiteWire> out_of_site_sinks;
-
-    // A site port that is present in this dictionary is blocked for all those nets except any in the attached pool
-    dict<PipId, pool<NetInfo *, hash_ptr_ops>> blocked_site_ports;
-
-    SiteArch(const SiteInformation *site_info);
-
-    inline SiteWire getPipSrcWire(const SitePip &site_pip) const NPNR_ALWAYS_INLINE;
-    inline SiteWire getPipDstWire(const SitePip &site_pip) const NPNR_ALWAYS_INLINE;
-
-    // Does this site pip always invert its signal?
-    inline bool isInverting(const SitePip &site_pip) const NPNR_ALWAYS_INLINE;
-
-    // Can this site pip optional invert its signal?
-    inline bool canInvert(const SitePip &site_pip) const NPNR_ALWAYS_INLINE;
-
-    // For a site port, returns the preferred constant net type.
-    //
-    // If no preference, then NetType is SIGNAL.
-    inline PhysicalNetlist::PhysNetlist::NetType prefered_constant_net_type(const SitePip &site_pip) const;
-
-    inline SitePipDownhillRange getPipsDownhill(const SiteWire &site_wire) const NPNR_ALWAYS_INLINE;
-    inline SitePipUphillRange getPipsUphill(const SiteWire &site_wire) const NPNR_ALWAYS_INLINE;
-    SiteWireRange getWires() const;
-
-    inline SiteWire getBelPinWire(BelId bel, IdString pin) const NPNR_ALWAYS_INLINE;
-    inline PortType getBelPinType(BelId bel, IdString pin) const NPNR_ALWAYS_INLINE;
-
-    const char *nameOfWire(const SiteWire &wire) const;
-    const char *nameOfPip(const SitePip &pip) const;
-    const char *nameOfNet(const SiteNetInfo *net) const;
-
-    bool debug() const;
-
-    bool bindWire(const SiteWire &wire, SiteNetInfo *net)
-    {
-        auto result = wire_to_nets.emplace(wire, SiteNetMap{net, 1});
-        if (result.first->second.net != net) {
-            if (debug()) {
-                log_info("Net conflict binding wire %s to net %s, conflicts with net %s\n", nameOfWire(wire),
-                         nameOfNet(net), nameOfNet(result.first->second.net));
-            }
-            return false;
-        }
-
-        if (!result.second) {
-            result.first->second.count += 1;
-        }
-
-        return true;
-    }
-
-    SiteNetInfo *unbindWire(const SiteWire &wire)
-    {
-        auto iter = wire_to_nets.find(wire);
-        NPNR_ASSERT(iter != wire_to_nets.end());
-        NPNR_ASSERT(iter->second.count >= 1);
-        SiteNetInfo *net = iter->second.net;
-        iter->second.count -= 1;
-
-        if (iter->second.count == 0) {
-            wire_to_nets.erase(iter);
-        }
-
-        return net;
-    }
-
-    bool bindPip(const SitePip &pip, SiteNetInfo *net);
-    void unbindPip(const SitePip &pip);
-
-    void archcheck();
-
-    bool is_pip_synthetic(const SitePip &pip) const NPNR_ALWAYS_INLINE;
-    SyntheticType pip_synthetic_type(const SitePip &pip) const NPNR_ALWAYS_INLINE;
-};
-
-struct SitePipDownhillIterator
-{
-    enum DownhillIteratorState
-    {
-        // Initial state
-        BEGIN = 0,
-        // Iterating over normal pips.
-        NORMAL_PIPS = 1,
-        // Iterating off all site port sources.
-        PORT_SINK_TO_PORT_SRC = 2,
-        // Iterating over out of site sinks.
-        OUT_OF_SITE_SINKS = 3,
-        // Iterating off all site port sources.
-        OUT_OF_SITE_SOURCE_TO_PORT_SRC = 4,
-        SITE_PORT = 5,
-        END = 6,
-        NUMBER_STATES = 7,
-    };
-
-    DownhillIteratorState state = BEGIN;
-    const SiteArch *site_arch;
-    SiteWire site_wire;
-    const RelSlice<int32_t> *pips_downhill;
-    size_t cursor;
-
-    bool advance_in_state() NPNR_ALWAYS_INLINE
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_PIPS:
-            ++cursor;
-            return (cursor < pips_downhill->size());
-        case PORT_SINK_TO_PORT_SRC:
-            ++cursor;
-            return (cursor < site_arch->input_site_ports.size());
-        case OUT_OF_SITE_SINKS:
-            ++cursor;
-            return (cursor < site_arch->out_of_site_sinks.size());
-        case OUT_OF_SITE_SOURCE_TO_PORT_SRC:
-            ++cursor;
-            return (cursor < site_arch->input_site_ports.size());
-        case SITE_PORT:
-            ++cursor;
-            return false;
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    bool check_first() const NPNR_ALWAYS_INLINE
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_PIPS:
-            return (cursor < pips_downhill->size());
-        case PORT_SINK_TO_PORT_SRC:
-            return (cursor < site_arch->input_site_ports.size());
-        case OUT_OF_SITE_SINKS:
-            return (cursor < site_arch->out_of_site_sinks.size());
-        case OUT_OF_SITE_SOURCE_TO_PORT_SRC:
-            return (cursor < site_arch->input_site_ports.size());
-        case SITE_PORT:
-            return true;
-        case END:
-            return true;
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    const std::array<std::array<DownhillIteratorState, NUMBER_STATES>, SiteWire::NUMBER_SITE_WIRE_TYPES>
-    get_state_table() const
-    {
-        std::array<std::array<DownhillIteratorState, NUMBER_STATES>, SiteWire::NUMBER_SITE_WIRE_TYPES> state_table;
-        for (size_t j = 0; j < SiteWire::NUMBER_SITE_WIRE_TYPES; ++j) {
-            for (size_t i = 0; i < NUMBER_STATES; ++i) {
-                state_table[j][i] = NUMBER_STATES;
-            }
-        }
-
-        state_table[SiteWire::SITE_WIRE][BEGIN] = NORMAL_PIPS;
-        state_table[SiteWire::SITE_WIRE][NORMAL_PIPS] = END;
-
-        state_table[SiteWire::OUT_OF_SITE_SOURCE][BEGIN] = OUT_OF_SITE_SOURCE_TO_PORT_SRC;
-        state_table[SiteWire::OUT_OF_SITE_SOURCE][OUT_OF_SITE_SOURCE_TO_PORT_SRC] = END;
-
-        state_table[SiteWire::OUT_OF_SITE_SINK][BEGIN] = END;
-
-        state_table[SiteWire::SITE_PORT_SINK][BEGIN] = PORT_SINK_TO_PORT_SRC;
-        state_table[SiteWire::SITE_PORT_SINK][PORT_SINK_TO_PORT_SRC] = OUT_OF_SITE_SINKS;
-        state_table[SiteWire::SITE_PORT_SINK][OUT_OF_SITE_SINKS] = END;
-
-        state_table[SiteWire::SITE_PORT_SOURCE][BEGIN] = SITE_PORT;
-        state_table[SiteWire::SITE_PORT_SOURCE][SITE_PORT] = END;
-
-        return state_table;
-    }
-
-    void advance_state() NPNR_ALWAYS_INLINE
-    {
-        state = get_state_table().at(site_wire.type).at(state);
-        cursor = 0;
-        NPNR_ASSERT(state >= BEGIN && state <= END);
-    }
-
-    void operator++() NPNR_ALWAYS_INLINE
-    {
-        NPNR_ASSERT(state != END);
-        while (state != END) {
-            if (advance_in_state()) {
-                break;
-            } else {
-                advance_state();
-                if (check_first()) {
-                    break;
-                }
-            }
-        }
-    }
-
-    bool operator!=(const SitePipDownhillIterator &other) const
-    {
-        return state != other.state || cursor != other.cursor;
-    }
-
-    inline SitePip operator*() const NPNR_ALWAYS_INLINE;
-};
-
-struct SitePipDownhillRange
-{
-    const SiteArch *site_arch;
-    SiteWire site_wire;
-
-    SitePipDownhillRange(const SiteArch *site_arch, const SiteWire &site_wire)
-            : site_arch(site_arch), site_wire(site_wire)
-    {
-    }
-
-    inline const RelSlice<int32_t> *init_pip_range() const NPNR_ALWAYS_INLINE;
-
-    inline SitePipDownhillIterator begin() const NPNR_ALWAYS_INLINE;
-
-    SitePipDownhillIterator end() const NPNR_ALWAYS_INLINE
-    {
-        SitePipDownhillIterator e;
-        e.state = SitePipDownhillIterator::END;
-        e.cursor = 0;
-
-        return e;
-    }
-};
-
-struct SitePipUphillIterator
-{
-    enum UphillIteratorState
-    {
-        // Initial state
-        BEGIN = 0,
-        // Iterating over normal pips.
-        NORMAL_PIPS = 1,
-        // Iterating off all site port sources.
-        PORT_SRC_TO_PORT_SINK = 2,
-        // Iterating over out of site sinks.
-        OUT_OF_SITE_SOURCES = 3,
-        // Iterating off all site port sources.
-        OUT_OF_SITE_SINK_TO_PORT_SINK = 4,
-        SITE_PORT = 5,
-        END = 6,
-        NUMBER_STATES = 7,
-    };
-
-    UphillIteratorState state = BEGIN;
-    const SiteArch *site_arch;
-    SiteWire site_wire;
-    size_t cursor;
-    UphillPipIterator iter;
-    UphillPipIterator uphill_end;
-
-    bool advance_in_state()
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_PIPS:
-            while (iter != uphill_end) {
-                ++iter;
-                if (!(iter != uphill_end)) {
-                    break;
-                }
-            }
-
-            return false;
-        case PORT_SRC_TO_PORT_SINK:
-            ++cursor;
-            return (cursor < site_arch->output_site_ports.size());
-        case OUT_OF_SITE_SOURCES:
-            ++cursor;
-            return (cursor < site_arch->out_of_site_sources.size());
-        case OUT_OF_SITE_SINK_TO_PORT_SINK:
-            ++cursor;
-            return (cursor < site_arch->output_site_ports.size());
-        case SITE_PORT:
-            ++cursor;
-            return false;
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    bool check_first() const
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_PIPS:
-            if (!(iter != uphill_end)) {
-                return false;
-            } else {
-                return true;
-            }
-        case PORT_SRC_TO_PORT_SINK:
-            return (cursor < site_arch->output_site_ports.size());
-        case OUT_OF_SITE_SOURCES:
-            return (cursor < site_arch->out_of_site_sources.size());
-        case OUT_OF_SITE_SINK_TO_PORT_SINK:
-            return (cursor < site_arch->output_site_ports.size());
-        case SITE_PORT:
-            return true;
-        case END:
-            return true;
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    const std::array<std::array<UphillIteratorState, NUMBER_STATES>, SiteWire::NUMBER_SITE_WIRE_TYPES>
-    get_state_table() const
-    {
-        std::array<std::array<UphillIteratorState, NUMBER_STATES>, SiteWire::NUMBER_SITE_WIRE_TYPES> state_table;
-        for (size_t j = 0; j < SiteWire::NUMBER_SITE_WIRE_TYPES; ++j) {
-            for (size_t i = 0; i < NUMBER_STATES; ++i) {
-                state_table[j][i] = NUMBER_STATES;
-            }
-        }
-
-        state_table[SiteWire::SITE_WIRE][BEGIN] = NORMAL_PIPS;
-        state_table[SiteWire::SITE_WIRE][NORMAL_PIPS] = END;
-
-        state_table[SiteWire::OUT_OF_SITE_SOURCE][BEGIN] = END;
-
-        state_table[SiteWire::OUT_OF_SITE_SINK][BEGIN] = OUT_OF_SITE_SINK_TO_PORT_SINK;
-        state_table[SiteWire::OUT_OF_SITE_SINK][OUT_OF_SITE_SINK_TO_PORT_SINK] = END;
-
-        state_table[SiteWire::SITE_PORT_SINK][BEGIN] = SITE_PORT;
-        state_table[SiteWire::SITE_PORT_SINK][SITE_PORT] = END;
-
-        state_table[SiteWire::SITE_PORT_SOURCE][BEGIN] = PORT_SRC_TO_PORT_SINK;
-        state_table[SiteWire::SITE_PORT_SOURCE][PORT_SRC_TO_PORT_SINK] = OUT_OF_SITE_SOURCES;
-        state_table[SiteWire::SITE_PORT_SOURCE][OUT_OF_SITE_SOURCES] = END;
-
-        return state_table;
-    }
-
-    void advance_state()
-    {
-        state = get_state_table().at(site_wire.type).at(state);
-        cursor = 0;
-        NPNR_ASSERT(state >= BEGIN && state <= END);
-    }
-
-    void operator++()
-    {
-        NPNR_ASSERT(state != END);
-        while (state != END) {
-            if (advance_in_state()) {
-                break;
-            } else {
-                advance_state();
-                if (check_first()) {
-                    break;
-                }
-            }
-        }
-    }
-
-    bool operator!=(const SitePipUphillIterator &other) const
-    {
-        return state != other.state || cursor != other.cursor || iter != other.iter;
-    }
-
-    SitePip operator*() const;
-};
-
-struct SitePipUphillRange
-{
-    const SiteArch *site_arch;
-    SiteWire site_wire;
-    UphillPipRange pip_range;
-
-    SitePipUphillRange(const SiteArch *site_arch, SiteWire site_wire);
-
-    SitePipUphillIterator begin() const
-    {
-        SitePipUphillIterator b;
-        b.state = SitePipUphillIterator::BEGIN;
-        b.site_arch = site_arch;
-        b.site_wire = site_wire;
-        b.cursor = 0;
-        b.iter = pip_range.b;
-        b.uphill_end = pip_range.e;
-
-        ++b;
-
-        return b;
-    }
-
-    SitePipUphillIterator end() const
-    {
-        SitePipUphillIterator e;
-        e.state = SitePipUphillIterator::END;
-        e.site_arch = site_arch;
-        e.site_wire = site_wire;
-        e.cursor = 0;
-        e.iter = pip_range.e;
-        e.uphill_end = pip_range.e;
-
-        return e;
-    }
-};
-
-inline SitePipDownhillRange SiteArch::getPipsDownhill(const SiteWire &site_wire) const
-{
-    return SitePipDownhillRange(this, site_wire);
-}
-
-inline SitePipUphillRange SiteArch::getPipsUphill(const SiteWire &site_wire) const
-{
-    return SitePipUphillRange(this, site_wire);
-}
-
-struct SiteWireIterator
-{
-    enum SiteWireIteratorState
-    {
-        // Initial state
-        BEGIN = 0,
-        NORMAL_WIRES = 1,
-        INPUT_SITE_PORTS = 2,
-        OUTPUT_SITE_PORTS = 3,
-        OUT_OF_SITE_SOURCES = 4,
-        OUT_OF_SITE_SINKS = 5,
-        END = 6,
-    };
-
-    SiteWireIteratorState state = BEGIN;
-    const SiteArch *site_arch;
-    const TileTypeInfoPOD *tile_type;
-    size_t cursor = 0;
-
-    bool advance_in_state()
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_WIRES:
-            while (true) {
-                ++cursor;
-                if (cursor >= tile_type->wire_data.size()) {
-                    return false;
-                }
-                if (tile_type->wire_data[cursor].site == site_arch->site_info->site) {
-                    return true;
-                }
-            }
-        case INPUT_SITE_PORTS:
-            ++cursor;
-            return (cursor < site_arch->input_site_ports.size());
-        case OUTPUT_SITE_PORTS:
-            ++cursor;
-            return (cursor < site_arch->output_site_ports.size());
-        case OUT_OF_SITE_SOURCES:
-            ++cursor;
-            return (cursor < site_arch->out_of_site_sources.size());
-        case OUT_OF_SITE_SINKS:
-            ++cursor;
-            return (cursor < site_arch->out_of_site_sinks.size());
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    // See if initial value in state is good.
-    bool check_first() const
-    {
-        switch (state) {
-        case BEGIN:
-            return false;
-        case NORMAL_WIRES:
-            if (cursor >= tile_type->wire_data.size()) {
-                return false;
-            }
-            return tile_type->wire_data[cursor].site == site_arch->site_info->site;
-        case INPUT_SITE_PORTS:
-            return (cursor < site_arch->input_site_ports.size());
-        case OUTPUT_SITE_PORTS:
-            return (cursor < site_arch->output_site_ports.size());
-        case OUT_OF_SITE_SOURCES:
-            return (cursor < site_arch->out_of_site_sources.size());
-        case OUT_OF_SITE_SINKS:
-            return (cursor < site_arch->out_of_site_sinks.size());
-        case END:
-            return true;
-        default:
-            // Unreachable!
-            NPNR_ASSERT(false);
-        }
-    }
-
-    void advance_state()
-    {
-        NPNR_ASSERT(state >= BEGIN && state < END);
-        state = static_cast<SiteWireIteratorState>(state + 1);
-        cursor = 0;
-        NPNR_ASSERT(state >= BEGIN && state <= END);
-    }
-
-    void operator++()
-    {
-        NPNR_ASSERT(state != END);
-        while (state != END) {
-            if (advance_in_state()) {
-                break;
-            } else {
-                advance_state();
-                if (check_first()) {
-                    break;
-                }
-            }
-        }
-    }
-
-    bool operator!=(const SiteWireIterator &other) const { return state != other.state || cursor != other.cursor; }
-
-    SiteWire operator*() const;
-};
-
-struct SiteWireRange
-{
-    const SiteArch *site_arch;
-    SiteWireRange(const SiteArch *site_arch) : site_arch(site_arch) {}
-    SiteWireIterator begin() const;
-
-    SiteWireIterator end() const
-    {
-        SiteWireIterator e;
-
-        e.state = SiteWireIterator::END;
-
-        return e;
-    }
-};
-
-inline SiteWireRange SiteArch::getWires() const { return SiteWireRange(this); }
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_ARCH_H */
diff --git a/fpga_interchange/site_arch.impl.h b/fpga_interchange/site_arch.impl.h
deleted file mode 100644
index 88df6c0f89..0000000000
--- a/fpga_interchange/site_arch.impl.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_ARCH_IMPL_H
-#define SITE_ARCH_IMPL_H
-
-#include "context.h"
-#include "site_arch.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-inline const ChipInfoPOD &SiteInformation::chip_info() const { return *ctx->chip_info; }
-
-inline bool SiteInformation::is_wire_in_site(WireId wire) const
-{
-    if (wire.tile != tile) {
-        return false;
-    }
-
-    return ctx->wire_info(wire).site == site;
-}
-
-inline bool SiteInformation::is_bel_in_site(BelId bel) const
-{
-    if (bel.tile != tile) {
-        return false;
-    }
-
-    return bel_info(ctx->chip_info, bel).site == site;
-}
-
-inline bool SiteInformation::is_pip_part_of_site(PipId pip) const
-{
-    if (pip.tile != tile) {
-        return false;
-    }
-
-    const auto &tile_type_data = ctx->chip_info->tile_types[tile_type];
-    const auto &pip_data = tile_type_data.pip_data[pip.index];
-    return pip_data.site == site;
-}
-
-inline bool SiteInformation::is_site_port(PipId pip) const
-{
-    const auto &tile_type_data = ctx->chip_info->tile_types[tile_type];
-    const auto &pip_data = tile_type_data.pip_data[pip.index];
-    if (pip_data.site == -1) {
-        return false;
-    }
-    auto &bel_data = tile_type_data.bel_data[pip_data.bel];
-    return bel_data.category == BEL_CATEGORY_SITE_PORT;
-}
-
-inline SiteWire SiteWire::make(const SiteInformation *site_info, WireId site_wire)
-{
-    NPNR_ASSERT(site_info->is_wire_in_site(site_wire));
-    SiteWire out;
-    out.type = SITE_WIRE;
-    out.wire = site_wire;
-    return out;
-}
-
-inline SiteWire SiteWire::make_site_port(const SiteInformation *site_info, PipId pip, bool dst_wire)
-{
-    const auto &tile_type_data = site_info->chip_info().tile_types[site_info->tile_type];
-    const auto &pip_data = tile_type_data.pip_data[pip.index];
-
-    // This pip should definitely be part of this site
-    NPNR_ASSERT(pip_data.site == site_info->site);
-
-    SiteWire out;
-
-    const auto &src_data = tile_type_data.wire_data[pip_data.src_index];
-    const auto &dst_data = tile_type_data.wire_data[pip_data.dst_index];
-
-    if (dst_wire) {
-        if (src_data.site == site_info->site) {
-            NPNR_ASSERT(dst_data.site == -1);
-            out.type = SITE_PORT_SINK;
-            out.pip = pip;
-            out.wire = canonical_wire(&site_info->chip_info(), pip.tile, pip_data.dst_index);
-        } else {
-            NPNR_ASSERT(src_data.site == -1);
-            NPNR_ASSERT(dst_data.site == site_info->site);
-            out.type = SITE_WIRE;
-            out.wire.tile = pip.tile;
-            out.wire.index = pip_data.dst_index;
-        }
-    } else {
-        if (src_data.site == site_info->site) {
-            NPNR_ASSERT(dst_data.site == -1);
-            out.type = SITE_WIRE;
-            out.wire.tile = pip.tile;
-            out.wire.index = pip_data.src_index;
-        } else {
-            NPNR_ASSERT(src_data.site == -1);
-            NPNR_ASSERT(dst_data.site == site_info->site);
-            out.type = SITE_PORT_SOURCE;
-            out.pip = pip;
-            out.wire = canonical_wire(&site_info->chip_info(), pip.tile, pip_data.src_index);
-        }
-    }
-
-    return out;
-}
-
-inline SitePip SitePip::make(const SiteInformation *site_info, PipId pip)
-{
-    SitePip out;
-    out.pip = pip;
-
-    if (site_info->is_site_port(pip)) {
-        out.type = SITE_PORT;
-    } else {
-        out.type = SITE_PIP;
-    }
-    return out;
-}
-
-inline SiteWire SiteArch::getPipSrcWire(const SitePip &site_pip) const
-{
-    SiteWire site_wire;
-    switch (site_pip.type) {
-    case SitePip::Type::SITE_PIP:
-        return SiteWire::make(site_info, ctx->getPipSrcWire(site_pip.pip));
-    case SitePip::Type::SITE_PORT:
-        return SiteWire::make_site_port(site_info, site_pip.pip, /*dst_wire=*/false);
-    case SitePip::Type::SOURCE_TO_SITE_PORT:
-        NPNR_ASSERT(site_pip.wire.type == SiteWire::OUT_OF_SITE_SOURCE);
-        return site_pip.wire;
-    case SitePip::Type::SITE_PORT_TO_SINK:
-        site_wire = SiteWire::make_site_port(site_info, site_pip.pip, /*dst_wire=*/true);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SINK);
-        return site_wire;
-    case SitePip::Type::SITE_PORT_TO_SITE_PORT:
-        site_wire = SiteWire::make_site_port(site_info, site_pip.pip, /*dst_wire=*/true);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SINK);
-        return site_wire;
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-inline SiteWire SiteArch::getPipDstWire(const SitePip &site_pip) const
-{
-    switch (site_pip.type) {
-    case SitePip::Type::SITE_PIP:
-        return SiteWire::make(site_info, ctx->getPipDstWire(site_pip.pip));
-    case SitePip::Type::SITE_PORT:
-        return SiteWire::make_site_port(site_info, site_pip.pip, /*dst_wire=*/true);
-    case SitePip::Type::SOURCE_TO_SITE_PORT: {
-        SiteWire site_wire = SiteWire::make_site_port(site_info, site_pip.pip, /*dst_wire=*/false);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SOURCE);
-        return site_wire;
-    }
-    case SitePip::Type::SITE_PORT_TO_SINK:
-        NPNR_ASSERT(site_pip.wire.type == SiteWire::OUT_OF_SITE_SINK);
-        return site_pip.wire;
-    case SitePip::Type::SITE_PORT_TO_SITE_PORT: {
-        SiteWire site_wire = SiteWire::make_site_port(site_info, site_pip.other_pip, /*dst_wire=*/false);
-        NPNR_ASSERT(site_wire.type == SiteWire::SITE_PORT_SOURCE);
-        return site_wire;
-    }
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-inline bool SiteArch::is_pip_synthetic(const SitePip &pip) const
-{
-    if (pip.type != SitePip::SITE_PORT) {
-        // This isn't a site port, so its valid!
-        return false;
-    }
-
-    auto &tile_type = ctx->chip_info->tile_types[site_info->tile_type];
-    auto &pip_data = tile_type.pip_data[pip.pip.index];
-    if (pip_data.site == -1) {
-        return pip_data.extra_data == -1;
-    } else {
-        auto &bel_data = tile_type.bel_data[pip_data.bel];
-        return bel_data.synthetic != 0;
-    }
-}
-
-inline SyntheticType SiteArch::pip_synthetic_type(const SitePip &pip) const
-{
-    if (pip.type != SitePip::SITE_PORT) {
-        // This isn't a site port, so its valid!
-        return NOT_SYNTH;
-    }
-
-    auto &tile_type = ctx->chip_info->tile_types[site_info->tile_type];
-    auto &pip_data = tile_type.pip_data[pip.pip.index];
-    NPNR_ASSERT(pip_data.site != -1);
-    auto &bel_data = tile_type.bel_data[pip_data.bel];
-    return SyntheticType(bel_data.synthetic);
-}
-
-inline SitePip SitePipDownhillIterator::operator*() const
-{
-    switch (state) {
-    case NORMAL_PIPS: {
-        PipId pip;
-        pip.tile = site_arch->site_info->tile;
-        pip.index = (*pips_downhill)[cursor];
-        return SitePip::make(site_arch->site_info, pip);
-    }
-    case PORT_SINK_TO_PORT_SRC:
-        return SitePip::make(site_arch->site_info, site_wire.pip, site_arch->input_site_ports.at(cursor));
-    case OUT_OF_SITE_SINKS:
-        return SitePip::make(site_arch->site_info, site_wire.pip, site_arch->out_of_site_sinks.at(cursor));
-    case OUT_OF_SITE_SOURCE_TO_PORT_SRC:
-        return SitePip::make(site_arch->site_info, site_wire, site_arch->input_site_ports.at(cursor));
-    case SITE_PORT:
-        return SitePip::make(site_arch->site_info, site_wire.pip);
-    default:
-        // Unreachable!
-        NPNR_ASSERT(false);
-    }
-}
-
-inline const RelSlice<int32_t> *SitePipDownhillRange::init_pip_range() const
-{
-    NPNR_ASSERT(site_wire.type == SiteWire::SITE_WIRE);
-    NPNR_ASSERT(site_wire.wire.tile == site_arch->site_info->tile);
-    return &site_arch->ctx->chip_info->tile_types[site_arch->site_info->tile_type]
-                    .wire_data[site_wire.wire.index]
-                    .pips_downhill;
-}
-
-inline SitePipDownhillIterator SitePipDownhillRange::begin() const
-{
-    SitePipDownhillIterator b;
-    b.state = SitePipDownhillIterator::BEGIN;
-    b.site_arch = site_arch;
-    b.site_wire = site_wire;
-    b.cursor = 0;
-    if (site_wire.type == SiteWire::SITE_WIRE) {
-        b.pips_downhill = init_pip_range();
-    }
-
-    ++b;
-
-    return b;
-}
-
-inline bool SiteArch::isInverting(const SitePip &site_pip) const
-{
-    if (site_pip.type != SitePip::SITE_PIP) {
-        return false;
-    }
-
-    auto &tile_type = ctx->chip_info->tile_types[site_info->tile_type];
-    auto &pip_data = tile_type.pip_data[site_pip.pip.index];
-    NPNR_ASSERT(pip_data.site != -1);
-    auto &bel_data = tile_type.bel_data[pip_data.bel];
-
-    // Is a fixed inverter if the non_inverting_pin is another pin.
-    return bel_data.non_inverting_pin != pip_data.extra_data && bel_data.inverting_pin == pip_data.extra_data;
-}
-
-inline bool SiteArch::canInvert(const SitePip &site_pip) const
-{
-    if (site_pip.type != SitePip::SITE_PIP) {
-        return false;
-    }
-
-    auto &tile_type = ctx->chip_info->tile_types[site_info->tile_type];
-    auto &pip_data = tile_type.pip_data[site_pip.pip.index];
-    NPNR_ASSERT(pip_data.site != -1);
-    auto &bel_data = tile_type.bel_data[pip_data.bel];
-
-    // Can optionally invert if this pip is both the non_inverting_pin and
-    // inverting pin.
-    return bel_data.non_inverting_pin == pip_data.extra_data && bel_data.inverting_pin == pip_data.extra_data;
-}
-
-inline PhysicalNetlist::PhysNetlist::NetType SiteArch::prefered_constant_net_type(const SitePip &site_pip) const
-{
-    // FIXME: Implement site port overrides from chipdb once available.
-    IdString prefered_constant_net(ctx->chip_info->constants->best_constant_net);
-    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-
-    if (prefered_constant_net == IdString()) {
-        return PhysicalNetlist::PhysNetlist::NetType::SIGNAL;
-    } else if (prefered_constant_net == gnd_net_name) {
-        return PhysicalNetlist::PhysNetlist::NetType::GND;
-    } else if (prefered_constant_net == vcc_net_name) {
-        return PhysicalNetlist::PhysNetlist::NetType::VCC;
-    } else {
-        log_error("prefered_constant_net %s is not the GND (%s) or VCC(%s) net?\n", prefered_constant_net.c_str(ctx),
-                  gnd_net_name.c_str(ctx), vcc_net_name.c_str(ctx));
-    }
-}
-
-inline SiteWire SiteArch::getBelPinWire(BelId bel, IdString pin) const
-{
-    WireId wire = ctx->getBelPinWire(bel, pin);
-    return SiteWire::make(site_info, wire);
-}
-
-inline PortType SiteArch::getBelPinType(BelId bel, IdString pin) const { return ctx->getBelPinType(bel, pin); }
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_ARCH_H */
diff --git a/fpga_interchange/site_lut_mapping_cache.cc b/fpga_interchange/site_lut_mapping_cache.cc
deleted file mode 100644
index 82832ed9e8..0000000000
--- a/fpga_interchange/site_lut_mapping_cache.cc
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "site_lut_mapping_cache.h"
-#include "nextpnr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-// ============================================================================
-
-SiteLutMappingKey SiteLutMappingKey::create(const SiteInformation &siteInfo)
-{
-    const Context *ctx = siteInfo.ctx;
-
-    // Look for LUT cells in the site
-    std::vector<CellInfo *> lutCells;
-    lutCells.reserve(siteInfo.cells_in_site.size());
-
-    for (CellInfo *cellInfo : siteInfo.cells_in_site) {
-
-        // Not a LUT cell
-        if (cellInfo->lut_cell.pins.empty()) {
-            continue;
-        }
-
-        // Not bound to a LUT BEL
-        BelId bel = cellInfo->bel;
-        const auto &bel_data = bel_info(ctx->chip_info, bel);
-        if (bel_data.lut_element == -1) {
-            continue;
-        }
-
-        lutCells.push_back(cellInfo);
-    }
-
-    // Sort cells by BEL indices to maintain always the same order
-    std::sort(lutCells.begin(), lutCells.end(),
-              [](const CellInfo *a, const CellInfo *b) { return a->bel.index > b->bel.index; });
-
-    // Initialize the key
-    SiteLutMappingKey key;
-    key.tileType = siteInfo.tile_type;
-    key.siteType = ctx->chip_info->sites[siteInfo.site].site_type;
-    key.numCells = 0;
-    key.cells.resize(ctx->max_lut_cells);
-
-    // Get bound nets. Store localized (to the LUT cluster) net indices only
-    // to get always the same key for the same LUT port configuration even
-    // when the actual global net names are different.
-    dict<IdString, int32_t> netMap;
-    for (CellInfo *cellInfo : lutCells) {
-
-        NPNR_ASSERT(key.numCells < key.cells.size());
-        auto &cell = key.cells[key.numCells++];
-
-        cell.type = cellInfo->type;
-        cell.belIndex = cellInfo->bel.index;
-
-        cell.conns.resize(ctx->max_lut_pins, 0);
-
-        size_t portId = 0;
-        for (const auto &port : cellInfo->ports) {
-            const auto &portInfo = port.second;
-
-            // Consider only LUT inputs
-            if (portInfo.type != PORT_IN) {
-                continue;
-            }
-
-            // Assign net id if any
-            int32_t netId = 0;
-            if (portInfo.net != nullptr) {
-                auto netInfo = portInfo.net;
-
-                auto it = netMap.find(netInfo->name);
-                if (it != netMap.end()) {
-                    netId = it->second;
-                } else {
-                    netId = (int32_t)netMap.size() + 1;
-                    netMap[netInfo->name] = netId;
-                }
-            }
-
-            NPNR_ASSERT(portId < cell.conns.size());
-            cell.conns[portId++] = netId;
-        }
-    }
-
-    // Compute hash
-    key.computeHash();
-
-    return key;
-}
-
-// ============================================================================
-
-bool SiteLutMappingResult::apply(const SiteInformation &siteInfo)
-{
-
-    Context *ctx = const_cast<Context *>(siteInfo.ctx);
-    TileStatus &tileStatus = ctx->get_tile_status(siteInfo.tile);
-
-    for (auto &cell : cells) {
-
-        // Get the bound cell
-        CellInfo *cellInfo = tileStatus.boundcells[cell.belIndex];
-        NPNR_ASSERT(cellInfo);
-
-        // Double check BEL binding
-        NPNR_ASSERT(cellInfo->bel.tile == siteInfo.tile);
-        NPNR_ASSERT(cellInfo->bel.index == cell.belIndex);
-
-        // Cell <-> BEL pin map
-        size_t numPins = cellInfo->lut_cell.pins.size();
-        for (size_t pinIdx = 0; pinIdx < numPins; ++pinIdx) {
-            const IdString &cellPin = cellInfo->lut_cell.pins[pinIdx];
-            auto &belPins = cellInfo->cell_bel_pins[cellPin];
-
-            // There is only one pin
-            belPins.resize(1);
-            belPins[0] = cell.belPins[cellPin];
-        }
-
-        // LUT data
-        // FIXME: Is there any other info that is being updated than pin_connections ?
-        cellInfo->lut_cell.pin_connections = std::move(cell.lutCell.pin_connections);
-    }
-
-    return true;
-}
-
-size_t SiteLutMappingResult::getSizeInBytes() const
-{
-
-    size_t size = 0;
-
-    size += sizeof(SiteLutMappingResult);
-    size += blockedWires.size() * sizeof(std::pair<IdString, IdString>);
-
-    for (const auto &cell : cells) {
-        size += sizeof(Cell);
-        size += cell.belPins.size() * sizeof(decltype(cell.belPins)::value_type);
-    }
-
-    return size;
-}
-
-// ============================================================================
-
-void SiteLutMappingCache::add(const SiteLutMappingKey &key, const SiteLutMappingResult &result)
-{
-    cache_[key] = result;
-}
-
-bool SiteLutMappingCache::get(const SiteLutMappingKey &key, SiteLutMappingResult *result)
-{
-    if (cache_.count(key) == 0) {
-        numMisses++;
-        return false;
-    }
-
-    numHits++;
-    *result = cache_[key];
-    return true;
-}
-
-void SiteLutMappingCache::clear()
-{
-    cache_.clear();
-    clearStats();
-}
-
-void SiteLutMappingCache::clearStats()
-{
-    numHits = 0;
-    numMisses = 0;
-}
-
-// ============================================================================
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/site_lut_mapping_cache.h b/fpga_interchange/site_lut_mapping_cache.h
deleted file mode 100644
index 31e7e5e124..0000000000
--- a/fpga_interchange/site_lut_mapping_cache.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_LUT_MAPPING_CACHE_H
-#define SITE_LUT_MAPPING_CACHE_H
-
-#include "idstring.h"
-#include "nextpnr_namespaces.h"
-#include "site_arch.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-// Key structure used in site LUT mapping cache
-struct SiteLutMappingKey
-{
-    // LUT Cell data
-    struct Cell
-    {
-        IdString type;    // Cell type
-        int32_t belIndex; // Bound BEL index
-
-        // Port to net assignments. These are local net ids generated during
-        // key creation. This is to abstract connections from actual design
-        // net names. the Id 0 means unconnected.
-        std::vector<int32_t> conns;
-
-        bool operator==(const Cell &other) const
-        {
-            return (type == other.type) && (belIndex == other.belIndex) && (conns == other.conns);
-        }
-
-        bool operator!=(const Cell &other) const
-        {
-            return (type != other.type) || (belIndex != other.belIndex) || (conns != other.conns);
-        }
-    };
-
-    int32_t tileType;        // Tile type
-    int32_t siteType;        // Site type in that tile type
-    size_t numCells;         // LUT cell count
-    std::vector<Cell> cells; // LUT cell data
-
-    unsigned int hash_; // Precomputed hash
-
-    // Creates a key from the given site state
-    static SiteLutMappingKey create(const SiteInformation &siteInfo);
-
-    // Returns size in bytes of the key
-    size_t getSizeInBytes() const { return sizeof(SiteLutMappingKey); }
-
-    // Precomputes hash of the key and stores it within
-    void computeHash()
-    {
-        hash_ = mkhash(0, tileType);
-        hash_ = mkhash(hash_, siteType);
-        hash_ = mkhash(hash_, numCells);
-        for (size_t j = 0; j < numCells; ++j) {
-            const auto &cell = cells[j];
-            hash_ = mkhash(hash_, cell.type.index);
-            hash_ = mkhash(hash_, cell.belIndex);
-            for (size_t i = 0; i < cell.conns.size(); ++i) {
-                hash_ = mkhash(hash_, cell.conns[i]);
-            }
-        }
-    }
-
-    // Compares cell data of this and other key
-    bool compareCells(const SiteLutMappingKey &other) const
-    {
-        if (numCells != other.numCells) {
-            return false;
-        }
-
-        for (size_t i = 0; i < numCells; ++i) {
-            if (cells[i] != other.cells[i]) {
-                return false;
-            }
-        }
-        return true;
-    }
-
-    bool operator==(const SiteLutMappingKey &other) const
-    {
-        return (hash_ == other.hash_) && (tileType == other.tileType) && (siteType == other.siteType) &&
-               compareCells(other);
-    }
-
-    bool operator!=(const SiteLutMappingKey &other) const
-    {
-        return (hash_ != other.hash_) || (tileType != other.tileType) || (siteType != other.siteType) ||
-               !compareCells(other);
-    }
-
-    unsigned int hash() const { return hash_; }
-};
-
-// Site LUT mapping result data
-struct SiteLutMappingResult
-{
-
-    // LUT cell data
-    struct Cell
-    {
-        int32_t belIndex;                 // BEL in tile index
-        LutCell lutCell;                  // LUT mapping data
-        dict<IdString, IdString> belPins; // Cell to BEL pin mapping
-    };
-
-    bool isValid;            // Validity flag
-    std::vector<Cell> cells; // Cell data
-
-    pool<std::pair<IdString, IdString>> blockedWires; // Set of blocked wires
-
-    // Applies the mapping result to the site
-    bool apply(const SiteInformation &siteInfo);
-
-    // Returns size in bytes
-    size_t getSizeInBytes() const;
-};
-
-// Site LUT mapping cache object
-class SiteLutMappingCache
-{
-  public:
-    // Adds an entry to the cache
-    void add(const SiteLutMappingKey &key, const SiteLutMappingResult &result);
-    // Retrieves an entry from the cache. Returns false if not found
-    bool get(const SiteLutMappingKey &key, SiteLutMappingResult *result);
-
-    // Clears the cache
-    void clear();
-    // Clears statistics counters of the cache
-    void clearStats();
-
-    // Return get() miss ratio
-    float getMissRatio() const { return (float)numMisses / (float)(numHits + numMisses); }
-
-    // Returns count of entries in the cache
-    size_t getCount() const { return cache_.size(); }
-
-    // Returns size of the cache rounded upwards to full MBs.
-    size_t getSizeMB() const
-    {
-        size_t size = 0;
-        for (const auto &it : cache_) {
-            size += it.first.getSizeInBytes();
-            size += it.second.getSizeInBytes();
-        }
-
-        const size_t MB = 1024L * 1024L;
-        return (size + MB - 1) / MB; // Round up to megabytes
-    }
-
-  private:
-    dict<SiteLutMappingKey, SiteLutMappingResult> cache_; // The cache
-
-    size_t numHits = 0;   // Hit count
-    size_t numMisses = 0; // Miss count
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_LUT_MAPPING_CACHE_H */
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
deleted file mode 100644
index 4e3d460a26..0000000000
--- a/fpga_interchange/site_router.cc
+++ /dev/null
@@ -1,1463 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "nextpnr.h"
-
-#include "design_utils.h"
-#include "dynamic_bitarray.h"
-#include "log.h"
-#include "site_routing_cache.h"
-
-#include "site_arch.h"
-#include "site_arch.impl.h"
-
-#include <queue>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-bool verbose_site_router(const Context *ctx) { return ctx->debug; }
-
-bool verbose_site_router(const SiteArch *ctx) { return verbose_site_router(ctx->ctx); }
-
-void SiteRouter::bindBel(CellInfo *cell)
-{
-    auto result = cells_in_site.emplace(cell);
-    NPNR_ASSERT(result.second);
-
-    dirty = true;
-}
-
-void SiteRouter::unbindBel(CellInfo *cell)
-{
-    NPNR_ASSERT(cells_in_site.erase(cell) == 1);
-
-    dirty = true;
-}
-
-bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
-{
-    // Propagate from BEL pins to first wire, checking for trivial routing
-    // conflicts.
-    dict<WireId, NetInfo *> wires;
-
-    for (CellInfo *cell : site_info->cells_in_site) {
-        BelId bel = cell->bel;
-        for (const auto &pin_pair : cell->cell_bel_pins) {
-            if (!cell->ports.count(pin_pair.first))
-                continue;
-            const PortInfo &port = cell->ports.at(pin_pair.first);
-
-            if (port.net == nullptr)
-                continue;
-
-            for (IdString bel_pin_name : pin_pair.second) {
-                BelPin bel_pin;
-                bel_pin.bel = bel;
-                bel_pin.pin = bel_pin_name;
-
-                WireId wire = ctx->getBelPinWire(bel_pin.bel, bel_pin.pin);
-                auto result = wires.emplace(wire, port.net);
-                if (!result.second) {
-                    // This wire is already in use, make sure the net bound is
-                    // the same net, otherwise there is a trivial net
-                    // conflict.
-                    const NetInfo *other_net = result.first->second;
-                    if (other_net != port.net) {
-                        // We have a direct net conflict at the BEL pin,
-                        // immediately short circuit the site routing check.
-                        if (verbose_site_router(ctx)) {
-                            log_info("Direct net conflict detected for cell %s:%s at bel %s, net %s != %s\n",
-                                     cell->name.c_str(ctx), cell->type.c_str(ctx), ctx->nameOfBel(cell->bel),
-                                     port.net->name.c_str(ctx), other_net->name.c_str(ctx));
-                        }
-
-                        return false;
-                    }
-                }
-            }
-        }
-    }
-
-    return true;
-}
-
-static bool is_invalid_site_port(const SiteArch *ctx, const SiteNetInfo *net, const SitePip &pip)
-{
-    // Blocked ports
-    auto fnd_rsv = ctx->blocked_site_ports.find(pip.pip);
-    if (fnd_rsv != ctx->blocked_site_ports.end() && !fnd_rsv->second.count(net->net))
-        return true;
-    // Synthetic pips
-    SyntheticType type = ctx->pip_synthetic_type(pip);
-    PhysicalNetlist::PhysNetlist::NetType net_type = ctx->ctx->get_net_type(net->net);
-    bool is_invalid = false;
-    if (type == SYNTH_GND) {
-        is_invalid = net_type != PhysicalNetlist::PhysNetlist::NetType::GND;
-    } else if (type == SYNTH_VCC) {
-        is_invalid = net_type != PhysicalNetlist::PhysNetlist::NetType::VCC;
-    }
-
-    return is_invalid;
-}
-
-struct SiteExpansionLoop
-{
-    RouteNodeStorage *const node_storage;
-
-    SiteExpansionLoop(RouteNodeStorage *node_storage) : node_storage(node_storage)
-    {
-        NPNR_ASSERT(node_storage != nullptr);
-    }
-
-    void clear()
-    {
-        node_storage->free_nodes(used_nodes);
-        used_nodes.clear();
-        solution.clear();
-        net_driver = SiteWire();
-    }
-
-    virtual ~SiteExpansionLoop() { node_storage->free_nodes(used_nodes); }
-
-    // Storage for nodes
-    std::vector<size_t> used_nodes;
-
-    bool expand_result;
-    SiteWire net_driver;
-    pool<SiteWire> net_users;
-
-    SiteRoutingSolution solution;
-
-    Node new_node(const SiteWire &wire, const SitePip &pip, const Node *parent)
-    {
-        Node node = node_storage->alloc_node();
-        used_nodes.push_back(node.get_index());
-
-        node->wire = wire;
-        node->pip = pip;
-        if (parent != nullptr) {
-            node->parent = (*parent).get_index();
-            node->flags = (*parent)->flags;
-            node->depth = (*parent)->depth + 1;
-        }
-
-        if (pip.type == SitePip::SITE_PORT) {
-            // Site ports should always have a parent!
-            NPNR_ASSERT(parent != nullptr);
-            if (wire.type == SiteWire::SITE_PORT_SINK) {
-                NPNR_ASSERT((*parent)->wire.type == SiteWire::SITE_WIRE);
-                NPNR_ASSERT(node->can_leave_site());
-                node->mark_left_site();
-                node->mark_left_site_after_entering();
-            } else if (wire.type == SiteWire::SITE_PORT_SOURCE) {
-                // This is a backward walk, so this is considered entering
-                // the site.
-                NPNR_ASSERT((*parent)->wire.type == SiteWire::SITE_WIRE);
-                NPNR_ASSERT(node->can_enter_site());
-                node->mark_entered_site();
-            } else {
-                // See if this is a forward or backward walk.
-                NPNR_ASSERT(wire.type == SiteWire::SITE_WIRE);
-                if ((*parent)->wire.type == SiteWire::SITE_PORT_SINK) {
-                    // This is a backward walk, so this is considered leaving
-                    // the site.
-                    NPNR_ASSERT(node->can_leave_site());
-                    node->mark_left_site();
-                    node->mark_left_site_after_entering();
-                } else {
-                    NPNR_ASSERT((*parent)->wire.type == SiteWire::SITE_PORT_SOURCE);
-                    NPNR_ASSERT(node->can_enter_site());
-                    node->mark_entered_site();
-                }
-            }
-        }
-
-        return node;
-    }
-
-    // Expand from wire specified, always downhill.
-    bool expand_net(const SiteArch *ctx, SiteRoutingCache *site_routing_cache, const SiteNetInfo *net,
-                    bool cache_disabled = false)
-    {
-        if (net->driver == net_driver && net->users == net_users) {
-            return expand_result;
-        }
-
-        clear();
-
-        net_driver = net->driver;
-        net_users = net->users;
-
-        if (!cache_disabled && site_routing_cache->get_solution(ctx, *net, &solution)) {
-            expand_result = true;
-            return expand_result;
-        }
-
-        if (verbose_site_router(ctx)) {
-            log_info("Expanding net %s from %s\n", ctx->nameOfNet(net), ctx->nameOfWire(net->driver));
-        }
-
-        auto node = new_node(net->driver, SitePip(), /*parent=*/nullptr);
-
-        pool<SiteWire> targets;
-        targets.insert(net->users.begin(), net->users.end());
-
-        if (verbose_site_router(ctx)) {
-            log_info("%zu targets:\n", targets.size());
-            for (auto &target : targets) {
-                log_info(" - %s\n", ctx->nameOfWire(target));
-            }
-        }
-
-        int32_t max_depth = 0;
-        int32_t max_depth_seen = 0;
-        std::vector<Node> nodes_to_expand;
-        nodes_to_expand.push_back(node);
-
-        std::vector<size_t> completed_routes;
-        while (!nodes_to_expand.empty()) {
-            Node parent_node = nodes_to_expand.back();
-            nodes_to_expand.pop_back();
-
-            max_depth_seen = std::max(max_depth_seen, parent_node->depth);
-
-            for (SitePip pip : ctx->getPipsDownhill(parent_node->wire)) {
-                if (is_invalid_site_port(ctx, net, pip)) {
-                    if (verbose_site_router(ctx)) {
-                        log_info("Pip %s is not a valid site port for net %s, skipping\n", ctx->nameOfPip(pip),
-                                 ctx->nameOfNet(net));
-                    }
-                    continue;
-                }
-
-                SiteWire wire = ctx->getPipDstWire(pip);
-
-                if (pip.type == SitePip::SITE_PORT) {
-                    if (wire.type == SiteWire::SITE_PORT_SINK) {
-                        if (!parent_node->can_leave_site()) {
-                            // This path has already left the site once, don't leave it again!
-                            if (verbose_site_router(ctx)) {
-                                log_info("%s is not a valid PIP for this path because it has already left the site\n",
-                                         ctx->nameOfPip(pip));
-                            }
-                            continue;
-                        }
-                    } else {
-                        NPNR_ASSERT(parent_node->wire.type == SiteWire::SITE_PORT_SOURCE);
-
-                        if (!parent_node->can_enter_site()) {
-                            // This path has already entered the site once,
-                            // don't enter it again!
-                            if (verbose_site_router(ctx)) {
-                                log_info(
-                                        "%s is not a valid PIP for this path because it has already entered the site\n",
-                                        ctx->nameOfPip(pip));
-                            }
-                            continue;
-                        }
-                    }
-                }
-
-                auto wire_iter = ctx->wire_to_nets.find(wire);
-                if (wire_iter != ctx->wire_to_nets.end() && wire_iter->second.net != net) {
-                    if (verbose_site_router(ctx)) {
-                        log_info("Wire %s is already tied to net %s, not exploring for net %s\n", ctx->nameOfWire(wire),
-                                 ctx->nameOfNet(wire_iter->second.net), ctx->nameOfNet(net));
-                    }
-                    continue;
-                }
-
-                auto node = new_node(wire, pip, &parent_node);
-
-                if (!node->is_valid_node()) {
-                    if (verbose_site_router(ctx)) {
-                        log_info(
-                                "%s is not a valid PIP for this path because it has left the site after entering it.\n",
-                                ctx->nameOfPip(pip));
-                    }
-                    continue;
-                }
-
-                if (targets.count(wire)) {
-                    completed_routes.push_back(node.get_index());
-                    max_depth = std::max(max_depth, node->depth);
-                }
-
-                nodes_to_expand.push_back(node);
-            }
-        }
-
-        // Make sure expansion reached all targets, otherwise this site is
-        // already unroutable!
-        solution.clear();
-        solution.store_solution(ctx, node_storage, net->driver, completed_routes);
-        bool verify = solution.verify(ctx, *net);
-
-        if (!verify)
-            return false;
-
-        for (size_t route : completed_routes) {
-            SiteWire wire = node_storage->get_node(route)->wire;
-            targets.erase(wire);
-        }
-
-        if (!cache_disabled && targets.empty()) {
-            site_routing_cache->add_solutions(ctx, *net, solution);
-        }
-
-        // Return nodes back to the storage system.
-        node_storage->free_nodes(used_nodes);
-        used_nodes.clear();
-
-        expand_result = targets.empty();
-        return expand_result;
-    }
-
-    size_t num_solutions() const { return solution.num_solutions(); }
-
-    const SiteWire &solution_sink(size_t idx) const { return solution.solution_sink(idx); }
-    std::vector<SitePip>::const_iterator solution_begin(size_t idx) const { return solution.solution_begin(idx); }
-
-    std::vector<SitePip>::const_iterator solution_end(size_t idx) const { return solution.solution_end(idx); }
-    bool solution_inverted(size_t idx) const { return solution.solution_inverted(idx); }
-    bool solution_can_invert(size_t idx) const { return solution.solution_can_invert(idx); }
-};
-
-void print_current_state(const SiteArch *site_arch)
-{
-    const Context *ctx = site_arch->ctx;
-    auto &cells_in_site = site_arch->site_info->cells_in_site;
-    const CellInfo *cell = *cells_in_site.begin();
-    BelId bel = cell->bel;
-    const auto &bel_data = bel_info(ctx->chip_info, bel);
-    const auto &site_inst = site_inst_info(ctx->chip_info, bel.tile, bel_data.site);
-
-    log_info("Site %s\n", site_inst.name.get());
-
-    log_info(" Cells in site:\n");
-    for (CellInfo *cell : cells_in_site) {
-        log_info("  - %s (%s) => %s\n", cell->name.c_str(ctx), cell->type.c_str(ctx), ctx->nameOfBel(cell->bel));
-    }
-
-    log_info(" Nets in site:\n");
-    for (auto &net_pair : site_arch->nets) {
-        auto *net = net_pair.first;
-        log_info("  - %s, pins in site:\n", net->name.c_str(ctx));
-        if (net->driver.cell && cells_in_site.count(net->driver.cell)) {
-            log_info("    - %s/%s (%s)\n", net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx),
-                     net->driver.cell->type.c_str(ctx));
-        }
-
-        for (const auto user : net->users) {
-            if (user.cell && cells_in_site.count(user.cell)) {
-                log_info("    - %s/%s (%s)\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
-                         user.cell->type.c_str(ctx));
-            }
-        }
-    }
-
-    log_info(" Consumed wires:\n");
-    for (auto &wire_pair : site_arch->wire_to_nets) {
-        const SiteWire &site_wire = wire_pair.first;
-        if (site_wire.type != SiteWire::SITE_WIRE) {
-            continue;
-        }
-        WireId wire = site_wire.wire;
-        const NetInfo *net = wire_pair.second.net->net;
-        log_info("  - %s is bound to %s\n", ctx->nameOfWire(wire), net->name.c_str(ctx));
-    }
-}
-
-struct PossibleSolutions
-{
-    bool tested = false;
-    SiteNetInfo *net = nullptr;
-    std::vector<SitePip>::const_iterator pips_begin;
-    std::vector<SitePip>::const_iterator pips_end;
-    bool inverted = false;
-    bool can_invert = false;
-    PhysicalNetlist::PhysNetlist::NetType prefered_constant_net_type = PhysicalNetlist::PhysNetlist::NetType::SIGNAL;
-};
-
-bool test_solution(SiteArch *ctx, SiteNetInfo *net, std::vector<SitePip>::const_iterator pips_begin,
-                   std::vector<SitePip>::const_iterator pips_end)
-{
-    bool valid = true;
-    std::vector<SitePip>::const_iterator good_pip_end = pips_begin;
-    std::vector<SitePip>::const_iterator iter = pips_begin;
-    SitePip pip;
-    while (iter != pips_end) {
-        pip = *iter;
-        if (!ctx->bindPip(pip, net)) {
-            valid = false;
-            break;
-        }
-
-        ++iter;
-        good_pip_end = iter;
-    }
-
-    // Unwind a bad solution
-    if (!valid) {
-        for (auto iter = pips_begin; iter != good_pip_end; ++iter) {
-            ctx->unbindPip(*iter);
-        }
-    } else {
-        NPNR_ASSERT(net->driver == ctx->getPipSrcWire(pip));
-    }
-
-    return valid;
-}
-
-void remove_solution(SiteArch *ctx, std::vector<SitePip>::const_iterator pips_begin,
-                     std::vector<SitePip>::const_iterator pips_end)
-{
-    for (auto iter = pips_begin; iter != pips_end; ++iter) {
-        ctx->unbindPip(*iter);
-    }
-}
-
-struct SolutionPreference
-{
-    const SiteArch *ctx;
-    const std::vector<PossibleSolutions> &solutions;
-
-    SolutionPreference(const SiteArch *ctx, const std::vector<PossibleSolutions> &solutions)
-            : ctx(ctx), solutions(solutions)
-    {
-    }
-
-    bool non_inverting_preference(const PossibleSolutions &lhs, const PossibleSolutions &rhs) const
-    {
-        // If the LHS is non-inverting and the RHS is inverting, then put the
-        // LHS first.
-        if (!lhs.inverted && rhs.inverted) {
-            return true;
-        }
-
-        // Better to have a path that can invert over a path that has no
-        // option to invert.
-        return (!lhs.can_invert) < (!rhs.can_invert);
-    }
-
-    bool inverting_preference(const PossibleSolutions &lhs, const PossibleSolutions &rhs) const
-    {
-        // If the LHS is inverting and the RHS is non-inverting, then put the
-        // LHS first (because this is the inverting preferred case).
-        if (lhs.inverted && !rhs.inverted) {
-            return true;
-        }
-
-        // Better to have a path that can invert over a path that has no
-        // option to invert.
-        return (!lhs.can_invert) < (!rhs.can_invert);
-    }
-
-    bool operator()(size_t lhs_solution_idx, size_t rhs_solution_idx) const
-    {
-        const PossibleSolutions &lhs = solutions.at(lhs_solution_idx);
-        const PossibleSolutions &rhs = solutions.at(rhs_solution_idx);
-
-        NPNR_ASSERT(lhs.net == rhs.net);
-
-        PhysicalNetlist::PhysNetlist::NetType net_type = ctx->ctx->get_net_type(lhs.net->net);
-        if (net_type == PhysicalNetlist::PhysNetlist::NetType::SIGNAL) {
-            return non_inverting_preference(lhs, rhs);
-        }
-
-        // All GND/VCC nets use out of site sources.  Local constant sources
-        // are still connected via synthetic edges to the global GND/VCC
-        // network.
-        NPNR_ASSERT(lhs.net->driver.type == SiteWire::OUT_OF_SITE_SOURCE);
-
-        bool lhs_match_preference = net_type == lhs.prefered_constant_net_type;
-        bool rhs_match_preference = net_type == rhs.prefered_constant_net_type;
-
-        if (lhs_match_preference && !rhs_match_preference) {
-            // Prefer solutions where the net type already matches the
-            // prefered constant type.
-            return true;
-        }
-
-        if (!lhs_match_preference && rhs_match_preference) {
-            // Prefer solutions where the net type already matches the
-            // prefered constant type. In this case the RHS is better, which
-            // means that RHS < LHS, hence false here.
-            return false;
-        }
-
-        NPNR_ASSERT(lhs_match_preference == rhs_match_preference);
-
-        if (!lhs_match_preference) {
-            // If the net type does not match the preference, then prefer
-            // inverted solutions.
-            return inverting_preference(lhs, rhs);
-        } else {
-            // If the net type does match the preference, then prefer
-            // non-inverted solutions.
-            return non_inverting_preference(lhs, rhs);
-        }
-    }
-};
-
-static bool find_solution_via_backtrack(SiteArch *ctx, std::vector<PossibleSolutions> *solutions,
-                                        std::vector<std::vector<size_t>> sinks_to_solutions,
-                                        const std::vector<SiteWire> &sinks, bool explain)
-{
-    std::vector<uint8_t> routed_sinks;
-    std::vector<size_t> solution_indicies;
-    routed_sinks.resize(sinks_to_solutions.size(), 0);
-    solution_indicies.resize(sinks_to_solutions.size(), 0);
-
-    // Scan solutions, and remove any solutions that are invalid immediately
-    //
-    // Note: This result cannot be cached because some solutions may be
-    // placement dependent.
-    for (size_t solution_idx = 0; solution_idx < solutions->size(); ++solution_idx) {
-        PossibleSolutions &solution = (*solutions)[solution_idx];
-        if (verbose_site_router(ctx) || explain) {
-            log_info("Testing solution %zu\n", solution_idx);
-        }
-        if (test_solution(ctx, solution.net, solution.pips_begin, solution.pips_end)) {
-            if (verbose_site_router(ctx) || explain) {
-                log_info("Solution %zu is good\n", solution_idx);
-            }
-            remove_solution(ctx, solution.pips_begin, solution.pips_end);
-        } else {
-            if (verbose_site_router(ctx) || explain) {
-                log_info("Solution %zu is not useable\n", solution_idx);
-            }
-            solution.tested = true;
-        }
-    }
-
-    // Sort sinks_to_solutions so that preferred solutions are tested earlier
-    // than less preferred solutions.
-    //
-    // See SolutionPreference implementation for details.
-    for (size_t sink_idx = 0; sink_idx < sinks_to_solutions.size(); ++sink_idx) {
-        std::vector<size_t> &solutions_for_sink = sinks_to_solutions.at(sink_idx);
-        std::stable_sort(solutions_for_sink.begin(), solutions_for_sink.end(), SolutionPreference(ctx, *solutions));
-
-        if (verbose_site_router(ctx) || explain) {
-            log_info("Solutions for sink %s (%zu)\n", ctx->nameOfWire(sinks.at(sink_idx)), sink_idx);
-            for (size_t solution_idx : solutions_for_sink) {
-                const PossibleSolutions &solution = solutions->at(solution_idx);
-                log_info("%zu: inverted = %d, can_invert = %d, tested = %d\n", solution_idx, solution.inverted,
-                         solution.can_invert, solution.tested);
-                for (auto iter = solution.pips_begin; iter != solution.pips_end; ++iter) {
-                    log_info(" - %s\n", ctx->nameOfPip(*iter));
-                }
-            }
-        }
-    }
-
-    // Sort solutions by the number of possible solutions first.  This allows
-    // the backtrack to avoid the wide searches first.
-
-    // First create a tuple vector of (sink_idx, number of valid solutions for sink).
-    std::vector<std::pair<size_t, size_t>> solution_order;
-    for (size_t sink_idx = 0; sink_idx < sinks_to_solutions.size(); ++sink_idx) {
-        size_t solution_count = 0;
-        for (size_t solution_idx : sinks_to_solutions[sink_idx]) {
-            if (!(*solutions)[solution_idx].tested) {
-                solution_count += 1;
-            }
-        }
-
-        if (solution_count == 0) {
-            if (verbose_site_router(ctx) || explain) {
-                log_info("Sink %s has no solution in site\n", ctx->nameOfWire(sinks.at(sink_idx)));
-            }
-            return false;
-        }
-
-        solution_order.emplace_back(sink_idx, solution_count);
-    }
-
-    // Actually sort so that sinks with fewer valid solutions are tested
-    // earlier.
-    std::sort(solution_order.begin(), solution_order.end(),
-              [](const std::pair<size_t, size_t> &a, const std::pair<size_t, size_t> &b) -> bool {
-                  return a.second < b.second;
-              });
-
-    std::vector<size_t> solution_stack;
-    solution_stack.reserve(sinks_to_solutions.size());
-
-    if (verbose_site_router(ctx)) {
-        log_info("Solving via backtrack with %zu solutions and %zu sinks\n", solutions->size(),
-                 sinks_to_solutions.size());
-    }
-
-    // Simple backtrack explorer:
-    //  - Apply the next solution at stack index.
-    //  - If solution is valid, push solution onto stack, and advance stack
-    //    index at solution 0.
-    //  - If solution is not valid, pop the stack.
-    //    - At this level of the stack, advance to the next solution.  If
-    //      there are not more solutions at this level, pop again.
-    //    - If stack is now empty, mark root solution as tested and invalid.
-    //      If root of stack has no more solutions, no solution is possible.
-    while (true) {
-        // Which sink is next to be tested?
-        size_t sink_idx = solution_order[solution_stack.size()].first;
-
-        size_t next_solution_to_test = solution_indicies[sink_idx];
-        if (verbose_site_router(ctx) || explain) {
-            log_info("next %zu : %zu (of %zu)\n", sink_idx, next_solution_to_test, sinks_to_solutions[sink_idx].size());
-        }
-        if (next_solution_to_test >= sinks_to_solutions[sink_idx].size()) {
-            // We have exausted all solutions at this level of the stack!
-            if (solution_stack.empty()) {
-                // Search is done, failed!!!
-                if (verbose_site_router(ctx) || explain) {
-                    log_info("No solution found via backtrack with %zu solutions and %zu sinks\n", solutions->size(),
-                             sinks_to_solutions.size());
-                }
-                return false;
-            } else {
-                // This level of the stack is completely tapped out, pop back
-                // to the next level up.
-                size_t sink_idx = solution_order[solution_stack.size() - 1].first;
-                size_t solution_idx = solution_stack.back();
-                if (verbose_site_router(ctx) || explain) {
-                    log_info("pop  %zu : %zu\n", sink_idx, solution_idx);
-                }
-                solution_stack.pop_back();
-
-                // Remove the now tested bad solution at the previous level of
-                // the stack.
-                auto &solution = solutions->at(solution_idx);
-                remove_solution(ctx, solution.pips_begin, solution.pips_end);
-
-                // Because we had to pop up the stack, advance the index at
-                // the level below us and start again.
-                solution_indicies[sink_idx] += 1;
-                continue;
-            }
-        }
-
-        size_t solution_idx = sinks_to_solutions[sink_idx].at(next_solution_to_test);
-        auto &solution = solutions->at(solution_idx);
-        if (solution.tested) {
-            // This solution was already determined to be no good, skip it.
-            if (verbose_site_router(ctx) || explain) {
-                log_info("skip %zu : %zu\n", sink_idx, solution_idx);
-            }
-            solution_indicies[sink_idx] += 1;
-            continue;
-        }
-
-        if (verbose_site_router(ctx) || explain) {
-            log_info("test %zu : %zu\n", sink_idx, solution_idx);
-        }
-
-        if (!test_solution(ctx, solution.net, solution.pips_begin, solution.pips_end)) {
-            // This solution was no good, try the next one at this level of
-            // the stack.
-            solution_indicies[sink_idx] += 1;
-        } else {
-            // This solution was good, push onto the stack.
-            if (verbose_site_router(ctx) || explain) {
-                log_info("push %zu : %zu\n", sink_idx, solution_idx);
-            }
-            solution_stack.push_back(solution_idx);
-            if (solution_stack.size() == sinks_to_solutions.size()) {
-                // Found a valid solution, done!
-                if (verbose_site_router(ctx)) {
-                    log_info("Solved via backtrack with %zu solutions and %zu sinks\n", solutions->size(),
-                             sinks_to_solutions.size());
-                }
-                return true;
-            } else {
-                // Because we pushing to a new level of stack, restart the
-                // search at this level.
-                sink_idx = solution_order[solution_stack.size()].first;
-                solution_indicies[sink_idx] = 0;
-            }
-        }
-    }
-
-    // Unreachable!!!
-    NPNR_ASSERT(false);
-}
-
-static bool route_site(SiteArch *ctx, SiteRoutingCache *site_routing_cache, RouteNodeStorage *node_storage,
-                       bool explain, bool cache_disabled = false)
-{
-    // Overview:
-    // - Starting from each site net source, expand the site routing graph
-    //   and record all reachable sinks.
-    //    - Note: This step is cachable and is being cached.  This cache
-    //      behaving well is critical to the performance of route_site.
-    // - Convert site expansion solutions into flat solution map.
-    // - Use backtrack algorithm to find conflict free solution to route site.
-    //
-    std::vector<SiteExpansionLoop *> expansions;
-    expansions.reserve(ctx->nets.size());
-
-    for (auto &net_pair : ctx->nets) {
-        if (net_pair.first->driver.cell == nullptr)
-            continue;
-        SiteNetInfo *net = &net_pair.second;
-
-        if (net->net->loop == nullptr) {
-            net->net->loop = new SiteExpansionLoop(node_storage);
-        }
-        expansions.push_back(net->net->loop);
-
-        SiteExpansionLoop *router = expansions.back();
-        if (!router->expand_net(ctx, site_routing_cache, net, cache_disabled)) {
-            if (verbose_site_router(ctx) || explain) {
-                log_info("Net %s expansion failed to reach all users, site is unroutable!\n", ctx->nameOfNet(net));
-            }
-
-            return false;
-        }
-    }
-
-    // Convert solutions into a flat solution set.
-
-    // Create a flat sink list and map.
-    std::vector<SiteWire> sinks;
-    dict<SiteWire, size_t> sink_map;
-    size_t number_solutions = 0;
-    for (const auto *expansion : expansions) {
-        number_solutions += expansion->num_solutions();
-        for (const SiteWire &unrouted_sink : expansion->net_users) {
-            auto result = sink_map.emplace(unrouted_sink, sink_map.size());
-            NPNR_ASSERT(result.second);
-            sinks.push_back(unrouted_sink);
-        }
-    }
-
-    if (sink_map.empty()) {
-        // All nets are trivially routed!
-        return true;
-    }
-
-    std::vector<PossibleSolutions> solutions;
-    solutions.reserve(number_solutions);
-
-    // Create a map from flat sink index to flat solution index.
-    std::vector<std::vector<size_t>> sinks_to_solutions;
-    sinks_to_solutions.resize(sink_map.size());
-
-    // Actually flatten solutions.
-    for (const auto *expansion : expansions) {
-        for (size_t idx = 0; idx < expansion->num_solutions(); ++idx) {
-            SiteWire wire = expansion->solution_sink(idx);
-            auto begin = expansion->solution_begin(idx);
-            auto end = expansion->solution_end(idx);
-            NPNR_ASSERT(begin != end);
-
-            size_t sink_idx = sink_map.at(wire);
-            sinks_to_solutions.at(sink_idx).push_back(solutions.size());
-
-            solutions.emplace_back();
-            auto &solution = solutions.back();
-            solution.net = ctx->wire_to_nets.at(wire).net;
-            solution.pips_begin = begin;
-            solution.pips_end = end;
-            solution.inverted = expansion->solution_inverted(idx);
-            solution.can_invert = expansion->solution_can_invert(idx);
-
-            for (auto iter = begin; iter != end; ++iter) {
-                const SitePip &site_pip = *iter;
-                NPNR_ASSERT(ctx->getPipDstWire(site_pip) == wire);
-                wire = ctx->getPipSrcWire(site_pip);
-
-                // If there is a input site port, mark on the solution what the
-                // prefered constant net type is for this site port.
-                if (site_pip.type == SitePip::SITE_PORT && wire.type == SiteWire::SITE_PORT_SOURCE) {
-                    solution.prefered_constant_net_type = ctx->prefered_constant_net_type(site_pip);
-                }
-            }
-
-            NPNR_ASSERT(expansion->net_driver == wire);
-        }
-    }
-
-    return find_solution_via_backtrack(ctx, &solutions, sinks_to_solutions, sinks, explain);
-}
-
-void check_routing(const SiteArch &site_arch)
-{
-    for (auto &net_pair : site_arch.nets) {
-        const NetInfo *net = net_pair.first;
-        if (net->driver.cell == nullptr)
-            continue;
-        const SiteNetInfo &net_info = net_pair.second;
-
-        for (const auto &user : net_info.users) {
-            NPNR_ASSERT(site_arch.wire_to_nets.at(user).net->net == net);
-            SiteWire cursor = user;
-            while (cursor != net_info.driver) {
-                auto iter = net_info.wires.find(cursor);
-                if (iter == net_info.wires.end()) {
-                    log_error("Wire %s has no pip, but didn't reach driver wire %s\n", site_arch.nameOfWire(cursor),
-                              site_arch.nameOfWire(net_info.driver));
-                }
-                const SitePip &site_pip = iter->second.pip;
-                cursor = site_arch.getPipSrcWire(site_pip);
-            }
-
-            NPNR_ASSERT(cursor == net_info.driver);
-            NPNR_ASSERT(site_arch.wire_to_nets.at(cursor).net->net == net);
-        }
-    }
-}
-
-static void apply_simple_routing(Context *ctx, const SiteArch &site_arch, NetInfo *net, const SiteNetInfo *site_net,
-                                 const SiteWire &user)
-{
-    SiteWire wire = user;
-    while (wire != site_net->driver) {
-        SitePip site_pip = site_net->wires.at(wire).pip;
-        NPNR_ASSERT(site_arch.getPipDstWire(site_pip) == wire);
-
-        if (site_pip.type == SitePip::SITE_PIP || site_pip.type == SitePip::SITE_PORT) {
-            NetInfo *bound_net = ctx->getBoundPipNet(site_pip.pip);
-            if (bound_net == nullptr) {
-                ctx->bindPip(site_pip.pip, net, STRENGTH_PLACER);
-            } else {
-                NPNR_ASSERT(bound_net == net);
-            }
-        }
-
-        wire = site_arch.getPipSrcWire(site_pip);
-    }
-}
-
-static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetInfo *net, const SiteNetInfo *site_net)
-{
-    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-    NetInfo *gnd_net = ctx->nets.at(gnd_net_name).get();
-
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-    NetInfo *vcc_net = ctx->nets.at(vcc_net_name).get();
-
-    // This function is designed to operate only on the gnd or vcc net, and
-    // assumes that the GND and VCC nets have been unified.
-    NPNR_ASSERT(net == vcc_net || net == gnd_net);
-
-    for (auto &user : site_net->users) {
-        bool is_path_inverting = false, path_can_invert = false;
-
-        SiteWire wire = user;
-        PipId inverting_pip;
-        PhysicalNetlist::PhysNetlist::NetType pref_const = PhysicalNetlist::PhysNetlist::NetType::SIGNAL;
-
-        while (wire != site_net->driver) {
-            SitePip pip = site_net->wires.at(wire).pip;
-            NPNR_ASSERT(site_arch.getPipDstWire(pip) == wire);
-
-            if (site_arch.isInverting(pip)) {
-                // FIXME: Should be able to handle the general case of
-                // multiple inverters, but that is harder (and annoying). Also
-                // most sites won't allow for a double inversion, so just
-                // disallow for now.
-                NPNR_ASSERT(!is_path_inverting);
-                is_path_inverting = true;
-                NPNR_ASSERT(pip.type == SitePip::SITE_PIP);
-                inverting_pip = pip.pip;
-            }
-
-            if (site_arch.canInvert(pip)) {
-                path_can_invert = true;
-                NPNR_ASSERT(pip.type == SitePip::SITE_PIP);
-                inverting_pip = pip.pip;
-            }
-
-            wire = site_arch.getPipSrcWire(pip);
-            pref_const = site_arch.prefered_constant_net_type(pip);
-        }
-
-        bool is_pref_const = true;
-        if (pref_const == PhysicalNetlist::PhysNetlist::NetType::VCC && net == gnd_net)
-            is_pref_const = false;
-        else if (pref_const == PhysicalNetlist::PhysNetlist::NetType::GND && net == vcc_net)
-            is_pref_const = false;
-
-        if (!is_path_inverting && (!path_can_invert || is_pref_const)) {
-            // This routing is boring, use base logic.
-            apply_simple_routing(ctx, site_arch, net, site_net, user);
-            continue;
-        }
-
-        NPNR_ASSERT(inverting_pip != PipId());
-
-        // This net is going to become two nets.
-        // The portion of the net prior to the inverter is going to be bound
-        // to the opposite net.  For example, if the original net was gnd_net,
-        // the portion prior to the inverter will not be the vcc_net.
-        //
-        // A new cell will be generated to sink the connection from the
-        // opposite net.
-        NetInfo *net_before_inverter;
-        if (net == gnd_net) {
-            net_before_inverter = vcc_net;
-        } else {
-            NPNR_ASSERT(net == vcc_net);
-            net_before_inverter = gnd_net;
-        }
-
-        // First find a name for the new cell
-        int count = 0;
-        CellInfo *new_cell = nullptr;
-        while (true) {
-            std::string new_cell_name = stringf("%s_%s.%d", net->name.c_str(ctx), site_arch.nameOfWire(user), count);
-            IdString new_cell_id = ctx->id(new_cell_name);
-            if (ctx->cells.count(new_cell_id)) {
-                count += 1;
-            } else {
-                new_cell = ctx->createCell(new_cell_id, ctx->id("$nextpnr_inv"));
-                break;
-            }
-        }
-
-        auto &tile_type = loc_info(ctx->chip_info, inverting_pip);
-        auto &pip_data = tile_type.pip_data[inverting_pip.index];
-        NPNR_ASSERT(pip_data.site != -1);
-        auto &bel_data = tile_type.bel_data[pip_data.bel];
-
-        BelId inverting_bel;
-        inverting_bel.tile = inverting_pip.tile;
-        inverting_bel.index = pip_data.bel;
-
-        IdString in_port(bel_data.ports[pip_data.extra_data]);
-        NPNR_ASSERT(bel_data.types[pip_data.extra_data] == PORT_IN);
-
-        IdString id_I = ctx->id("I");
-        new_cell->addInput(id_I);
-        new_cell->cell_bel_pins[id_I].push_back(in_port);
-
-        new_cell->bel = inverting_bel;
-        new_cell->belStrength = STRENGTH_PLACER;
-        ctx->tileStatus.at(inverting_bel.tile).boundcells[inverting_bel.index] = new_cell;
-
-        new_cell->connectPort(id_I, net_before_inverter);
-
-        // The original BEL pin is now routed, but only through the inverter.
-        // Because the cell/net model doesn't allow for multiple source pins
-        // and the fact that the portion of the net after the inverter is
-        // currently routed, all BEL pins on this site wire are going to be
-        // masked from the router.
-        NPNR_ASSERT(user.type == SiteWire::SITE_WIRE);
-        ctx->mask_bel_pins_on_site_wire(net, user.wire);
-
-        // Bind wires and pips to the two nets.
-        bool after_inverter = true;
-        wire = user;
-        while (wire != site_net->driver) {
-            SitePip site_pip = site_net->wires.at(wire).pip;
-            NPNR_ASSERT(site_arch.getPipDstWire(site_pip) == wire);
-
-            if (site_arch.isInverting(site_pip) || site_arch.canInvert(site_pip)) {
-                NPNR_ASSERT(after_inverter);
-                after_inverter = false;
-
-                // Because this wire is just after the inverter, bind it to
-                // the net without the pip, as this is a "source".
-                NPNR_ASSERT(wire.type == SiteWire::SITE_WIRE);
-                ctx->bindWire(wire.wire, net, STRENGTH_PLACER);
-            } else {
-                if (site_pip.type == SitePip::SITE_PIP || site_pip.type == SitePip::SITE_PORT) {
-                    if (after_inverter) {
-                        ctx->bindPip(site_pip.pip, net, STRENGTH_PLACER);
-                    } else {
-                        ctx->bindPip(site_pip.pip, net_before_inverter, STRENGTH_PLACER);
-                    }
-                }
-            }
-
-            wire = site_arch.getPipSrcWire(site_pip);
-        }
-    }
-}
-
-static void apply_routing(Context *ctx, const SiteArch &site_arch, pool<std::pair<IdString, int32_t>> &lut_thrus)
-{
-    IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
-    NetInfo *gnd_net = ctx->nets.at(gnd_net_name).get();
-
-    IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
-    NetInfo *vcc_net = ctx->nets.at(vcc_net_name).get();
-
-    for (auto &net_pair : site_arch.nets) {
-        NetInfo *net = net_pair.first;
-        const SiteNetInfo *site_net = &net_pair.second;
-
-        if (net == gnd_net || net == vcc_net) {
-            apply_constant_routing(ctx, site_arch, net, site_net);
-        } else {
-            // If the driver wire is a site wire, bind it.
-            if (site_net->driver.type == SiteWire::SITE_WIRE) {
-                WireId driver_wire = site_net->driver.wire;
-                if (ctx->getBoundWireNet(driver_wire) != net) {
-                    ctx->bindWire(driver_wire, net, STRENGTH_PLACER);
-                }
-            }
-
-            for (auto &wire_pair : site_net->wires) {
-                const SitePip &site_pip = wire_pair.second.pip;
-                if (site_pip.type != SitePip::SITE_PIP && site_pip.type != SitePip::SITE_PORT) {
-                    continue;
-                }
-
-                auto &pip_data = pip_info(ctx->chip_info, site_pip.pip);
-
-                BelId bel;
-                bel.tile = site_pip.pip.tile;
-                bel.index = pip_data.bel;
-                const auto &bel_data = bel_info(ctx->chip_info, bel);
-
-                // Detect and store LUT thrus for allowance check during routing
-                if (bel_data.lut_element != -1) {
-                    WireId src_wire = ctx->getPipSrcWire(site_pip.pip);
-
-                    for (BelPin bel_pin : ctx->getWireBelPins(src_wire)) {
-                        if (bel_pin.bel != bel)
-                            continue;
-
-                        lut_thrus.insert(std::make_pair(bel_pin.pin, bel_pin.bel.index));
-                        break;
-                    }
-                }
-
-                ctx->bindPip(site_pip.pip, net, STRENGTH_PLACER);
-            }
-        }
-    }
-}
-
-static bool map_luts_in_site(const SiteInformation &site_info, pool<std::pair<IdString, IdString>> *blocked_wires)
-{
-    const Context *ctx = site_info.ctx;
-    bool enable_cache = !ctx->arch_args.disable_lut_mapping_cache;
-
-    // Create a site LUT mapping key
-    SiteLutMappingKey key = SiteLutMappingKey::create(site_info);
-
-    // Get the solution from cache. If not found then compute it
-    SiteLutMappingResult lutMapping;
-    if (!enable_cache || !ctx->site_lut_mapping_cache.get(key, &lutMapping)) {
-
-        const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(site_info.tile_type);
-        std::vector<LutMapper> lut_mappers;
-        lut_mappers.reserve(lut_elements.size());
-        for (size_t i = 0; i < lut_elements.size(); ++i) {
-            lut_mappers.push_back(LutMapper(lut_elements[i]));
-        }
-
-        for (CellInfo *cell : site_info.cells_in_site) {
-            if (cell->lut_cell.pins.empty()) {
-                continue;
-            }
-
-            BelId bel = cell->bel;
-            const auto &bel_data = bel_info(ctx->chip_info, bel);
-            if (bel_data.lut_element != -1) {
-                lut_mappers[bel_data.lut_element].cells.push_back(cell);
-            }
-        }
-
-        bool res = true;
-
-        lutMapping.blockedWires.clear();
-        for (LutMapper lut_mapper : lut_mappers) {
-            if (lut_mapper.cells.empty()) {
-                continue;
-            }
-
-            pool<const LutBel *, hash_ptr_ops> blocked_luts;
-            if (!lut_mapper.remap_luts(ctx, &lutMapping, &blocked_luts)) {
-                res = false;
-                break;
-            }
-
-            for (const LutBel *lut_bel : blocked_luts) {
-                lutMapping.blockedWires.emplace(std::make_pair(lut_bel->name, lut_bel->output_pin));
-            }
-        }
-
-        lutMapping.isValid = res;
-
-        // Add the solution to the cache
-        if (enable_cache) {
-            ctx->site_lut_mapping_cache.add(key, lutMapping);
-        }
-    }
-
-    // Apply the solution if valid
-    if (lutMapping.isValid) {
-
-        lutMapping.apply(site_info);
-
-        blocked_wires->clear();
-        blocked_wires->insert(lutMapping.blockedWires.begin(), lutMapping.blockedWires.end());
-    }
-
-    return lutMapping.isValid;
-}
-
-// Block outputs of unavailable LUTs to prevent site router from using them.
-static void block_lut_outputs(SiteArch *site_arch, const pool<std::pair<IdString, IdString>> &blocked_wires)
-{
-    const Context *ctx = site_arch->site_info->ctx;
-    auto &tile_info = ctx->chip_info->tile_types[site_arch->site_info->tile_type];
-    for (const auto &bel_pin_pair : blocked_wires) {
-        IdString bel_name = bel_pin_pair.first;
-        IdString bel_pin = bel_pin_pair.second;
-
-        int32_t bel_index = -1;
-        for (int32_t i = 0; i < tile_info.bel_data.ssize(); i++) {
-            if (tile_info.bel_data[i].site == site_arch->site_info->site &&
-                tile_info.bel_data[i].name == bel_name.index) {
-                bel_index = i;
-                break;
-            }
-        }
-
-        NPNR_ASSERT(bel_index != -1);
-        BelId bel;
-        bel.tile = site_arch->site_info->tile;
-        bel.index = bel_index;
-
-        SiteWire lut_output_wire = site_arch->getBelPinWire(bel, bel_pin);
-        site_arch->bindWire(lut_output_wire, &site_arch->blocking_site_net);
-    }
-}
-
-// Block wires corresponding to dedicated interconnections that are not
-// exposed to the general interconnect.
-// These wires cannot be chosen for the first element in a BEL chain, as they
-// would result in an unroutability error.
-static void block_cluster_wires(SiteArch *site_arch)
-{
-    const Context *ctx = site_arch->site_info->ctx;
-    auto &cells_in_site = site_arch->site_info->cells_in_site;
-
-    for (auto &cell : cells_in_site) {
-        if (cell->cluster == ClusterId())
-            continue;
-
-        if (ctx->getClusterRootCell(cell->cluster) != cell)
-            continue;
-
-        Cluster cluster = ctx->clusters.at(cell->cluster);
-
-        uint32_t cluster_id = cluster.index;
-        auto &cluster_data = cluster_info(ctx->chip_info, cluster_id);
-
-        if (cluster_data.chainable_ports.size() == 0)
-            continue;
-
-        IdString cluster_chain_input(cluster_data.chainable_ports[0].cell_sink);
-
-        if (cluster_chain_input == IdString())
-            continue;
-
-        auto &cell_bel_pins = cell->cell_bel_pins.at(cluster_chain_input);
-        for (auto &bel_pin : cell_bel_pins) {
-            SiteWire bel_pin_wire = site_arch->getBelPinWire(cell->bel, bel_pin);
-            site_arch->bindWire(bel_pin_wire, &site_arch->blocking_site_net);
-        }
-    }
-}
-
-// Reserve site ports that are on dedicated rather than general interconnect
-static void reserve_site_ports(SiteArch *site_arch)
-{
-    const Context *ctx = site_arch->site_info->ctx;
-    site_arch->blocked_site_ports.clear();
-    for (PipId in_pip : site_arch->input_site_ports) {
-        pool<NetInfo *, hash_ptr_ops> dedicated_nets;
-        const int max_iters = 100;
-
-        std::queue<WireId> visit_queue;
-        pool<WireId> already_visited;
-        WireId src = ctx->getPipSrcWire(in_pip);
-        visit_queue.push(src);
-        already_visited.insert(src);
-
-        int iter = 0;
-        while (!visit_queue.empty() && iter++ < max_iters) {
-            WireId next = visit_queue.front();
-            visit_queue.pop();
-            for (auto bp : ctx->getWireBelPins(next)) {
-                // Bel pins could mean dedicated routes
-                CellInfo *bound = ctx->getBoundBelCell(bp.bel);
-                if (bound == nullptr)
-                    continue;
-                // Need to find the corresponding cell pin
-                for (auto &port : bound->ports) {
-                    if (port.second.net == nullptr)
-                        continue;
-                    for (auto bel_pin : ctx->getBelPinsForCellPin(bound, port.first)) {
-                        if (bel_pin == bp.pin)
-                            dedicated_nets.insert(port.second.net);
-                    }
-                }
-            }
-            for (auto pip : ctx->getPipsUphill(next)) {
-                WireId next_src = ctx->getPipSrcWire(pip);
-                if (already_visited.count(next_src))
-                    continue;
-                visit_queue.push(next_src);
-                already_visited.insert(next_src);
-            }
-        }
-        if (iter < max_iters) {
-            if (ctx->debug)
-                log_info("Blocking PIP %s\n", ctx->nameOfPip(in_pip));
-            // If we didn't search up to the iteration limit, assume this node is not reachable from general routing
-            site_arch->blocked_site_ports[in_pip] = dedicated_nets;
-        }
-    }
-}
-
-// Recursively visit downhill PIPs until a SITE_PORT_SINK is reached.
-// Marks all PIPs for all valid paths.
-static bool visit_downhill_pips(const SiteArch *site_arch, const SiteWire &site_wire, std::vector<PipId> &valid_pips)
-{
-    bool valid_path_exists = false;
-    for (SitePip site_pip : site_arch->getPipsDownhill(site_wire)) {
-        const SiteWire &dst_wire = site_arch->getPipDstWire(site_pip);
-        if (dst_wire.type == SiteWire::SITE_PORT_SINK) {
-            valid_pips.push_back(site_pip.pip);
-            return true;
-        }
-
-        bool path_ok = visit_downhill_pips(site_arch, dst_wire, valid_pips);
-        valid_path_exists |= path_ok;
-
-        if (path_ok) {
-            valid_pips.push_back(site_pip.pip);
-        }
-    }
-
-    return valid_path_exists;
-}
-
-// Checks all downhill PIPs starting from driver wires.
-// All valid PIPs are stored and returned in a vector.
-static void check_downhill_pips(Context *ctx, const SiteArch *site_arch, std::vector<PipId> &valid_pips)
-{
-    auto &cells_in_site = site_arch->site_info->cells_in_site;
-
-    for (auto &net_pair : site_arch->nets) {
-        NetInfo *net = net_pair.first;
-        const SiteNetInfo *site_net = &net_pair.second;
-
-        if (net->driver.cell && cells_in_site.count(net->driver.cell)) {
-            const SiteWire &site_wire = site_net->driver;
-
-            visit_downhill_pips(site_arch, site_wire, valid_pips);
-        }
-    }
-}
-
-bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_status) const
-{
-    // Overview:
-    //  - Make sure all cells in site satisfy the constraints.
-    //  - Ensure that the LUT equation elements in the site are legal
-    //  - Check that the site is routable.
-
-    // Because site routing checks are expensive, cache them.
-    // SiteRouter::bindBel/unbindBel should correctly invalid the cache by
-    // setting dirty=true.
-
-    if (!dirty) {
-        return site_ok;
-    }
-
-    dirty = false;
-
-    // Empty sites are trivially correct.
-    if (cells_in_site.size() == 0) {
-        site_ok = true;
-        return site_ok;
-    }
-
-    site_ok = false;
-
-    // Make sure all cells in this site belong!
-    auto iter = cells_in_site.begin();
-    NPNR_ASSERT((*iter)->bel != BelId());
-    auto tile = (*iter)->bel.tile;
-
-    if (verbose_site_router(ctx)) {
-        log_info("Checking site routing for site %s\n", ctx->get_site_name(tile, site));
-    }
-
-    for (CellInfo *cell : cells_in_site) {
-        // All cells in the site must be placed.
-        NPNR_ASSERT(cell->bel != BelId());
-
-        // Sanity check that all cells in this site are part of the same site.
-        NPNR_ASSERT(tile == cell->bel.tile);
-        NPNR_ASSERT(site == bel_info(ctx->chip_info, cell->bel).site);
-
-        // As a first pass make sure each assigned cell in site is valid by
-        // constraints.
-        if (!ctx->is_cell_valid_constraints(cell, tile_status, verbose_site_router(ctx))) {
-            if (verbose_site_router(ctx)) {
-                log_info("Sanity check failed, cell_type %s at %s has an invalid constraints, so site is not good\n",
-                         cell->type.c_str(ctx), ctx->nameOfBel(cell->bel));
-            }
-            site_ok = false;
-            return site_ok;
-        }
-    }
-
-    SiteInformation site_info(ctx, tile, site, cells_in_site);
-    pool<std::pair<IdString, IdString>> blocked_wires;
-    if (!map_luts_in_site(site_info, &blocked_wires)) {
-        site_ok = false;
-        return site_ok;
-    }
-
-    // Push from cell pins to the first WireId from each cell pin.
-    //
-    // If a site wire conflict occurs here, the site is trivially unroutable.
-    if (!check_initial_wires(ctx, &site_info)) {
-        site_ok = false;
-        return site_ok;
-    }
-
-    // Construct a model of the site routing that is suitable for routing
-    // algorithms.
-    SiteArch site_arch(&site_info);
-
-    // SiteArch::archcheck is a good sanity check on SiteArch and the chipdb,
-    // but isn't cheap, so disabled for now.
-    //
-    // site_arch.archcheck();
-
-    block_lut_outputs(&site_arch, blocked_wires);
-    block_cluster_wires(&site_arch);
-
-    // Do a detailed routing check to see if the site has at least 1 valid
-    // routing solution.
-    site_ok = route_site(&site_arch, &ctx->site_routing_cache, &ctx->node_storage, /*explain=*/false);
-    if (verbose_site_router(ctx)) {
-        if (site_ok) {
-            log_info("Site %s is routable\n", ctx->get_site_name(tile, site));
-        } else {
-            log_info("Site %s is not routable\n", ctx->get_site_name(tile, site));
-        }
-    }
-
-    if (site_ok) {
-        check_routing(site_arch);
-    }
-    return site_ok;
-}
-
-void SiteRouter::bindSiteRouting(Context *ctx)
-{
-    NPNR_ASSERT(!dirty);
-    NPNR_ASSERT(site_ok);
-
-    // Make sure all cells in this site belong!
-    auto iter = cells_in_site.begin();
-    NPNR_ASSERT((*iter)->bel != BelId());
-
-    auto tile = (*iter)->bel.tile;
-    auto &tile_type = loc_info(ctx->chip_info, (*iter)->bel);
-
-    // Unbind all bound site wires
-    WireId wire;
-    wire.tile = tile;
-    for (size_t wire_index = 0; wire_index < tile_type.wire_data.size(); ++wire_index) {
-        const TileWireInfoPOD &wire_data = tile_type.wire_data[wire_index];
-
-        if (wire_data.site != this->site) {
-            continue;
-        }
-
-        wire.index = wire_index;
-
-        NetInfo *net = ctx->getBoundWireNet(wire);
-        if (net == nullptr) {
-            continue;
-        }
-
-        auto &pip_map = net->wires.at(wire);
-        if (pip_map.strength <= STRENGTH_STRONG) {
-            ctx->unbindWire(wire);
-        }
-    }
-
-    SiteInformation site_info(ctx, tile, site, cells_in_site);
-    pool<std::pair<IdString, IdString>> blocked_wires;
-    NPNR_ASSERT(map_luts_in_site(site_info, &blocked_wires));
-
-    SiteArch site_arch(&site_info);
-    block_lut_outputs(&site_arch, blocked_wires);
-    block_cluster_wires(&site_arch);
-    reserve_site_ports(&site_arch);
-    NPNR_ASSERT(route_site(&site_arch, &ctx->site_routing_cache, &ctx->node_storage, /*explain=*/false,
-                           /*cache_disabled=*/true));
-
-    check_routing(site_arch);
-    apply_routing(ctx, site_arch, lut_thrus);
-
-    check_downhill_pips(ctx, &site_arch, valid_pips);
-    if (verbose_site_router(ctx)) {
-        print_current_state(&site_arch);
-    }
-}
-
-void SiteRouter::explain(const Context *ctx) const
-{
-    NPNR_ASSERT(!dirty);
-    if (site_ok) {
-        return;
-    }
-
-    // Make sure all cells in this site belong!
-    auto iter = cells_in_site.begin();
-    NPNR_ASSERT((*iter)->bel != BelId());
-
-    auto tile = (*iter)->bel.tile;
-
-    SiteInformation site_info(ctx, tile, site, cells_in_site);
-    SiteArch site_arch(&site_info);
-    bool route_status = route_site(&site_arch, &ctx->site_routing_cache, &ctx->node_storage, /*explain=*/true);
-    if (!route_status) {
-        print_current_state(&site_arch);
-    }
-}
-
-ArchNetInfo::~ArchNetInfo() { delete loop; }
-
-Arch::~Arch()
-{
-    for (auto &net_pair : nets) {
-        if (net_pair.second->loop) {
-            net_pair.second->loop->clear();
-        }
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/site_router.h b/fpga_interchange/site_router.h
deleted file mode 100644
index ad1cbf66be..0000000000
--- a/fpga_interchange/site_router.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_ROUTER_H
-#define SITE_ROUTER_H
-
-#include <cstdint>
-
-#include "hashlib.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-#include "site_arch.h"
-#include "site_routing_storage.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-struct TileStatus;
-
-struct SiteRouter
-{
-    SiteRouter(int16_t site) : site(site), dirty(false), site_ok(true) {}
-
-    pool<CellInfo *, hash_ptr_ops> cells_in_site;
-    std::vector<PipId> valid_pips;
-    pool<std::pair<IdString, int32_t>> lut_thrus;
-    const int16_t site;
-
-    mutable bool dirty;
-    mutable bool site_ok;
-
-    void bindBel(CellInfo *cell);
-    void unbindBel(CellInfo *cell);
-    bool checkSiteRouting(const Context *ctx, const TileStatus &tile_status) const;
-    void bindSiteRouting(Context *ctx);
-    void explain(const Context *ctx) const;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_ROUTER_H */
diff --git a/fpga_interchange/site_routing_cache.cc b/fpga_interchange/site_routing_cache.cc
deleted file mode 100644
index 82bbbf1bca..0000000000
--- a/fpga_interchange/site_routing_cache.cc
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "site_routing_cache.h"
-
-#include "context.h"
-#include "site_arch.impl.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-void SiteRoutingSolution::store_solution(const SiteArch *ctx, const RouteNodeStorage *node_storage,
-                                         const SiteWire &driver, std::vector<size_t> solutions)
-{
-    clear();
-
-    solution_sinks.reserve(solutions.size());
-    inverted.reserve(solutions.size());
-    can_invert.reserve(solutions.size());
-
-    for (size_t route : solutions) {
-        bool sol_inverted = false;
-        bool sol_can_invert = false;
-
-        SiteWire wire = node_storage->get_node(route)->wire;
-        solution_sinks.push_back(wire);
-
-        solution_offsets.push_back(solution_storage.size());
-        Node cursor = node_storage->get_node(route);
-        while (cursor.has_parent()) {
-            if (ctx->isInverting(cursor->pip) && !sol_can_invert) {
-                sol_inverted = !sol_inverted;
-            }
-            if (ctx->canInvert(cursor->pip)) {
-                sol_inverted = false;
-                sol_can_invert = true;
-            }
-
-            solution_storage.push_back(cursor->pip);
-            Node parent = cursor.parent();
-            NPNR_ASSERT(ctx->getPipDstWire(cursor->pip) == cursor->wire);
-            NPNR_ASSERT(ctx->getPipSrcWire(cursor->pip) == parent->wire);
-            cursor = parent;
-        }
-
-        inverted.push_back(sol_inverted);
-        can_invert.push_back(sol_can_invert);
-
-        NPNR_ASSERT(cursor->wire == driver);
-    }
-
-    solution_offsets.push_back(solution_storage.size());
-}
-
-bool SiteRoutingSolution::verify(const SiteArch *ctx, const SiteNetInfo &net)
-{
-    pool<SiteWire> seen_users;
-    for (size_t i = 0; i < num_solutions(); ++i) {
-        SiteWire cursor = solution_sink(i);
-        NPNR_ASSERT(net.users.count(cursor) == 1);
-        seen_users.emplace(cursor);
-
-        auto begin = solution_begin(i);
-        auto end = solution_end(i);
-
-        for (auto iter = begin; iter != end; ++iter) {
-            SitePip pip = *iter;
-            NPNR_ASSERT(ctx->getPipDstWire(pip) == cursor);
-            cursor = ctx->getPipSrcWire(pip);
-        }
-
-        NPNR_ASSERT(net.driver == cursor);
-    }
-
-    return seen_users.size() == net.users.size();
-}
-
-SiteRoutingKey SiteRoutingKey::make(const SiteArch *ctx, const SiteNetInfo &site_net)
-{
-    SiteRoutingKey out;
-
-    out.tile_type = ctx->site_info->tile_type;
-    out.site = ctx->site_info->site;
-
-    out.net_type = ctx->ctx->get_net_type(site_net.net);
-    out.driver_type = site_net.driver.type;
-    if (site_net.driver.type == SiteWire::SITE_WIRE) {
-        out.driver_index = site_net.driver.wire.index;
-    } else {
-        NPNR_ASSERT(site_net.driver.type == SiteWire::OUT_OF_SITE_SOURCE);
-        out.driver_index = -1;
-    }
-
-    out.user_types.reserve(site_net.users.size());
-    out.user_indicies.reserve(site_net.users.size());
-
-    std::vector<SiteWire> users;
-    users.reserve(site_net.users.size());
-    users.insert(users.begin(), site_net.users.begin(), site_net.users.end());
-
-    std::sort(users.begin(), users.end());
-
-    for (const SiteWire &user : users) {
-        out.user_types.push_back(user.type);
-
-        if (user.type == SiteWire::SITE_WIRE) {
-            out.user_indicies.push_back(user.wire.index);
-        } else {
-            NPNR_ASSERT(user.type == SiteWire::OUT_OF_SITE_SINK);
-            out.user_indicies.push_back(-1);
-        }
-    }
-
-    return out;
-}
-
-bool SiteRoutingCache::get_solution(const SiteArch *ctx, const SiteNetInfo &net, SiteRoutingSolution *solution) const
-{
-    SiteRoutingKey key = SiteRoutingKey::make(ctx, net);
-    auto iter = cache_.find(key);
-    if (iter == cache_.end()) {
-        return false;
-    }
-
-    *solution = iter->second;
-    const auto &tile_type_data = ctx->site_info->chip_info().tile_types[ctx->site_info->tile_type];
-
-    for (SiteWire &wire : solution->solution_sinks) {
-        switch (wire.type) {
-        case SiteWire::SITE_WIRE:
-            wire.wire.tile = ctx->site_info->tile;
-            break;
-        case SiteWire::OUT_OF_SITE_SOURCE:
-            wire.net = net.net;
-            break;
-        case SiteWire::OUT_OF_SITE_SINK:
-            wire.net = net.net;
-            break;
-        case SiteWire::SITE_PORT_SINK: {
-            const auto &pip_data = tile_type_data.pip_data[wire.pip.index];
-            wire.pip.tile = ctx->site_info->tile;
-            wire.wire = canonical_wire(&ctx->site_info->chip_info(), ctx->site_info->tile, pip_data.dst_index);
-            break;
-        }
-        case SiteWire::SITE_PORT_SOURCE: {
-            const auto &pip_data = tile_type_data.pip_data[wire.pip.index];
-            wire.pip.tile = ctx->site_info->tile;
-            wire.wire = canonical_wire(&ctx->site_info->chip_info(), ctx->site_info->tile, pip_data.src_index);
-            break;
-        }
-        default:
-            NPNR_ASSERT(false);
-        }
-    }
-
-    for (SitePip &pip : solution->solution_storage) {
-        pip.pip.tile = ctx->site_info->tile;
-        switch (pip.type) {
-        case SitePip::SITE_PIP:
-            // Done!
-            break;
-        case SitePip::SITE_PORT:
-            // Done!
-            break;
-        case SitePip::SOURCE_TO_SITE_PORT:
-            NPNR_ASSERT(pip.wire.type == SiteWire::OUT_OF_SITE_SOURCE);
-            pip.wire.net = net.net;
-            break;
-        case SitePip::SITE_PORT_TO_SINK:
-            NPNR_ASSERT(pip.wire.type == SiteWire::OUT_OF_SITE_SINK);
-            pip.wire.net = net.net;
-            break;
-        case SitePip::SITE_PORT_TO_SITE_PORT:
-            pip.other_pip.tile = ctx->site_info->tile;
-            break;
-        default:
-            NPNR_ASSERT(false);
-        }
-    }
-
-    return solution->verify(ctx, net);
-}
-
-void SiteRoutingCache::add_solutions(const SiteArch *ctx, const SiteNetInfo &net, const SiteRoutingSolution &solution)
-{
-    SiteRoutingKey key = SiteRoutingKey::make(ctx, net);
-
-    cache_[key] = solution;
-}
-
-void SiteRoutingCache::clear() { cache_.clear(); }
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/site_routing_cache.h b/fpga_interchange/site_routing_cache.h
deleted file mode 100644
index 5f5e7b7539..0000000000
--- a/fpga_interchange/site_routing_cache.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_ROUTING_CACHE_H
-#define SITE_ROUTING_CACHE_H
-
-#include "PhysicalNetlist.capnp.h"
-#include "nextpnr_namespaces.h"
-#include "site_arch.h"
-#include "site_routing_storage.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct SiteRoutingSolution
-{
-    void store_solution(const SiteArch *ctx, const RouteNodeStorage *node_storage, const SiteWire &driver,
-                        std::vector<size_t> solutions);
-    bool verify(const SiteArch *ctx, const SiteNetInfo &net);
-
-    void clear()
-    {
-        solution_offsets.clear();
-        solution_storage.clear();
-        solution_sinks.clear();
-        inverted.clear();
-        can_invert.clear();
-    }
-
-    size_t num_solutions() const { return solution_sinks.size(); }
-
-    const SiteWire &solution_sink(size_t solution) const { return solution_sinks.at(solution); }
-
-    std::vector<SitePip>::const_iterator solution_begin(size_t solution) const
-    {
-        NPNR_ASSERT(solution + 1 < solution_offsets.size());
-        return solution_storage.begin() + solution_offsets.at(solution);
-    }
-
-    std::vector<SitePip>::const_iterator solution_end(size_t solution) const
-    {
-        NPNR_ASSERT(solution + 1 < solution_offsets.size());
-        return solution_storage.begin() + solution_offsets.at(solution + 1);
-    }
-
-    bool solution_inverted(size_t solution) const { return inverted.at(solution) != 0; }
-
-    bool solution_can_invert(size_t solution) const { return can_invert.at(solution) != 0; }
-
-    std::vector<size_t> solution_offsets;
-    std::vector<SitePip> solution_storage;
-    std::vector<SiteWire> solution_sinks;
-    std::vector<uint8_t> inverted;
-    std::vector<uint8_t> can_invert;
-};
-
-struct SiteRoutingKey
-{
-    int32_t tile_type;
-    int32_t site;
-    // The net type matters for site routing. Legal routes for VCC/GND/SIGNAL
-    // nets are different.
-    PhysicalNetlist::PhysNetlist::NetType net_type;
-    SiteWire::Type driver_type;
-    int32_t driver_index;
-    std::vector<SiteWire::Type> user_types;
-    std::vector<int32_t> user_indicies;
-
-    bool operator==(const SiteRoutingKey &other) const
-    {
-        return tile_type == other.tile_type && site == other.site && net_type == other.net_type &&
-               driver_type == other.driver_type && driver_index == other.driver_index &&
-               user_types == other.user_types && user_indicies == other.user_indicies;
-    }
-    bool operator!=(const SiteRoutingKey &other) const
-    {
-        return tile_type != other.tile_type || site != other.site || net_type != other.net_type ||
-               driver_type != other.driver_type || driver_index != other.driver_index ||
-               user_types != other.user_types || user_indicies != other.user_indicies;
-    }
-
-    static SiteRoutingKey make(const SiteArch *ctx, const SiteNetInfo &site_net);
-
-    unsigned int hash() const
-    {
-        unsigned int seed = 0;
-        seed = mkhash(seed, tile_type);
-        seed = mkhash(seed, site);
-        seed = mkhash(seed, int(net_type));
-        seed = mkhash(seed, int(driver_type));
-        seed = mkhash(seed, driver_index);
-        seed = mkhash(seed, user_types.size());
-        for (auto t : user_types)
-            seed = mkhash(seed, int(t));
-        seed = mkhash(seed, user_indicies.size());
-        for (auto i : user_indicies)
-            seed = mkhash(seed, i);
-        return seed;
-    }
-};
-
-// Provides an LRU cache for site routing solutions.
-class SiteRoutingCache
-{
-  public:
-    bool get_solution(const SiteArch *ctx, const SiteNetInfo &net, SiteRoutingSolution *solution) const;
-    void add_solutions(const SiteArch *ctx, const SiteNetInfo &net, const SiteRoutingSolution &solution);
-    void clear();
-
-  private:
-    dict<SiteRoutingKey, SiteRoutingSolution> cache_;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_ROUTING_CACHE_H */
diff --git a/fpga_interchange/site_routing_storage.h b/fpga_interchange/site_routing_storage.h
deleted file mode 100644
index 2fbc246e27..0000000000
--- a/fpga_interchange/site_routing_storage.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef SITE_ROUTING_STORAGE
-#define SITE_ROUTING_STORAGE
-
-#include <limits>
-
-#include "nextpnr_namespaces.h"
-#include "site_arch.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct RouteNode
-{
-    void clear()
-    {
-        parent = std::numeric_limits<size_t>::max();
-        pip = SitePip();
-        wire = SiteWire();
-        flags = 0;
-        depth = 0;
-    }
-
-    enum Flags
-    {
-        // Has this path left the site?
-        LEFT_SITE = 0,
-        // Has this path entered the site?
-        ENTERED_SITE = 1,
-        // Has this path left the site after entering it?
-        // This node should be discarded as being part of an illegal path
-        // which allows entering and exiting a site, situation that needs
-        // to be handled with a tile PIP.
-        LEFT_SITE_AFTER_ENTERING = 2,
-    };
-
-    bool has_left_site() const { return (flags & (1 << LEFT_SITE)) != 0; }
-
-    bool has_left_site_after_entering() const { return (flags & (1 << LEFT_SITE_AFTER_ENTERING)) != 0; }
-
-    bool can_leave_site() const { return !has_left_site(); }
-
-    bool is_valid_node() const { return !has_left_site_after_entering(); }
-
-    void mark_left_site() { flags |= (1 << LEFT_SITE); }
-
-    void mark_left_site_after_entering() { flags |= (has_entered_site() << LEFT_SITE_AFTER_ENTERING); }
-
-    bool has_entered_site() const { return (flags & (1 << ENTERED_SITE)) != 0; }
-
-    bool can_enter_site() const { return !has_entered_site(); }
-
-    void mark_entered_site() { flags |= (1 << ENTERED_SITE); }
-
-    size_t parent;
-
-    SitePip pip;   // What pip was taken to reach this node.
-    SiteWire wire; // What wire is this routing node located at?
-    int32_t flags;
-    int32_t depth;
-};
-
-struct RouteNodeStorage;
-
-class Node
-{
-  public:
-    Node(RouteNodeStorage *storage, size_t idx) : storage_(storage), idx_(idx) {}
-
-    size_t get_index() const { return idx_; }
-
-    RouteNode &operator*();
-    const RouteNode &operator*() const;
-    RouteNode *operator->();
-    const RouteNode *operator->() const;
-    bool has_parent() const;
-    Node parent();
-
-  private:
-    RouteNodeStorage *storage_;
-    size_t idx_;
-};
-
-struct RouteNodeStorage
-{
-    // Free list of nodes.
-    std::vector<RouteNode> nodes;
-    std::vector<size_t> free_list;
-
-    // Either allocate a new node if no nodes are on the free list, or return
-    // an element from the free list.
-    Node alloc_node()
-    {
-        if (free_list.empty()) {
-            nodes.emplace_back();
-            nodes.back().clear();
-            return Node(this, nodes.size() - 1);
-        }
-
-        size_t idx = free_list.back();
-        free_list.pop_back();
-        nodes[idx].clear();
-
-        return Node(this, idx);
-    }
-
-    Node get_node(size_t idx)
-    {
-        NPNR_ASSERT(idx < nodes.size());
-        return Node(this, idx);
-    }
-
-    const Node get_node(size_t idx) const
-    {
-        NPNR_ASSERT(idx < nodes.size());
-        return Node(const_cast<RouteNodeStorage *>(this), idx);
-    }
-
-    // Return all node from the current owner to the free list.
-    void free_nodes(std::vector<size_t> &other_free_list)
-    {
-        free_list.insert(free_list.end(), other_free_list.begin(), other_free_list.end());
-    }
-};
-
-inline RouteNode &Node::operator*() { return storage_->nodes[idx_]; }
-inline const RouteNode &Node::operator*() const { return storage_->nodes[idx_]; }
-
-inline RouteNode *Node::operator->() { return &storage_->nodes[idx_]; }
-inline const RouteNode *Node::operator->() const { return &storage_->nodes[idx_]; }
-
-inline bool Node::has_parent() const { return storage_->nodes[idx_].parent < storage_->nodes.size(); }
-
-inline Node Node::parent()
-{
-    size_t parent_idx = storage_->nodes[idx_].parent;
-    NPNR_ASSERT(parent_idx < storage_->nodes.size());
-    return Node(storage_, parent_idx);
-}
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* SITE_ROUTING_STORAGE */
diff --git a/fpga_interchange/type_wire.cc b/fpga_interchange/type_wire.cc
deleted file mode 100644
index d1bdaed01d..0000000000
--- a/fpga_interchange/type_wire.cc
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "type_wire.h"
-#include "nextpnr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-TypeWireId::TypeWireId(const Context *ctx, WireId wire_inst)
-{
-    NPNR_ASSERT(wire_inst != WireId());
-
-    if (wire_inst.tile == -1) {
-        auto &tile_wire = ctx->chip_info->nodes[wire_inst.index].tile_wires[0];
-        type = ctx->chip_info->tiles[tile_wire.tile].type;
-        index = tile_wire.index;
-    } else {
-        type = ctx->chip_info->tiles[wire_inst.tile].type;
-        index = wire_inst.index;
-    }
-}
-
-TypeWireSet::TypeWireSet(const Context *ctx, WireId wire)
-{
-    if (wire.tile == -1) {
-        const auto &node_data = ctx->chip_info->nodes[wire.index];
-        wire_types_.reserve(node_data.tile_wires.size());
-        for (const auto &tile_wire : node_data.tile_wires) {
-            wire_types_.emplace_back();
-            wire_types_.back().type = ctx->chip_info->tiles[tile_wire.tile].type;
-            wire_types_.back().index = tile_wire.index;
-        }
-    } else {
-        TypeWireId wire_type(ctx, wire);
-        wire_types_.push_back(wire_type);
-    }
-
-    std::sort(wire_types_.begin(), wire_types_.end());
-
-    hash_ = wire_types_.size();
-    for (const auto &wire : wire_types_) {
-        hash_ = mkhash(hash_, wire.hash());
-    }
-}
-
-TypeWireId::TypeWireId(lookahead_storage::TypeWireId::Reader reader) : type(reader.getType()), index(reader.getIndex())
-{
-}
-void TypeWireId::to_builder(lookahead_storage::TypeWireId::Builder builder) const
-{
-    builder.setType(type);
-    builder.setIndex(index);
-}
-
-TypeWirePair::TypeWirePair(lookahead_storage::TypeWirePair::Reader reader) : src(reader.getSrc()), dst(reader.getDst())
-{
-}
-
-void TypeWirePair::to_builder(lookahead_storage::TypeWirePair::Builder builder) const
-{
-    src.to_builder(builder.getSrc());
-    dst.to_builder(builder.getDst());
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/type_wire.h b/fpga_interchange/type_wire.h
deleted file mode 100644
index a472bccc20..0000000000
--- a/fpga_interchange/type_wire.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef TYPE_WIRE_H
-#define TYPE_WIRE_H
-
-#include <algorithm>
-#include <vector>
-
-#include "hashlib.h"
-#include "nextpnr_namespaces.h"
-#include "nextpnr_types.h"
-
-#include "lookahead.capnp.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-
-struct TypeWireId
-{
-    TypeWireId() : type(-1), index(-1) {}
-    TypeWireId(const Context *ctx, WireId wire_inst);
-
-    explicit TypeWireId(lookahead_storage::TypeWireId::Reader reader);
-    void to_builder(lookahead_storage::TypeWireId::Builder builder) const;
-
-    bool operator==(const TypeWireId &other) const { return type == other.type && index == other.index; }
-    bool operator!=(const TypeWireId &other) const { return type != other.type || index != other.index; }
-    bool operator<(const TypeWireId &other) const
-    {
-        return type < other.type || (type == other.type && index < other.index);
-    }
-
-    unsigned int hash() const { return mkhash(type, index); }
-
-    int32_t type;
-    int32_t index;
-};
-
-struct TypeWirePair
-{
-    TypeWireId src;
-    TypeWireId dst;
-
-    TypeWirePair() = default;
-    explicit TypeWirePair(lookahead_storage::TypeWirePair::Reader reader);
-    void to_builder(lookahead_storage::TypeWirePair::Builder builder) const;
-
-    bool operator==(const TypeWirePair &other) const { return src == other.src && dst == other.dst; }
-    bool operator!=(const TypeWirePair &other) const { return src != other.src || dst != other.dst; }
-
-    unsigned int hash() const { return mkhash(src.hash(), dst.hash()); }
-};
-
-struct TypeWireSet
-{
-  public:
-    TypeWireSet(const Context *ctx, WireId wire);
-    unsigned int hash() const { return hash_; }
-
-    bool operator==(const TypeWireSet &other) const { return wire_types_ == other.wire_types_; }
-    bool operator!=(const TypeWireSet &other) const { return wire_types_ != other.wire_types_; }
-
-  private:
-    unsigned int hash_;
-    std::vector<TypeWireId> wire_types_;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif /* TYPE_WIRE_H */
diff --git a/fpga_interchange/xdc.cc b/fpga_interchange/xdc.cc
deleted file mode 100644
index 53a80b7da4..0000000000
--- a/fpga_interchange/xdc.cc
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2019  gatecat <gatecat@ds0.me>
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "xdc.h"
-
-#include <string>
-
-#include "context.h"
-#include "log.h"
-
-// Include tcl.h late because it messed with #define's and lets them leave the
-// scope of the header.
-#include <tcl.h>
-
-NEXTPNR_NAMESPACE_BEGIN
-
-static int obj_set_from_any(Tcl_Interp *interp, Tcl_Obj *objPtr) { return TCL_ERROR; }
-
-static void set_tcl_obj_string(Tcl_Obj *objPtr, const std::string &s)
-{
-    NPNR_ASSERT(objPtr->bytes == nullptr);
-    // Need to have space for the end null byte.
-    objPtr->bytes = Tcl_Alloc(s.size() + 1);
-
-    // Length is length of string, not including the end null byte.
-    objPtr->length = s.size();
-
-    std::copy(s.begin(), s.end(), objPtr->bytes);
-    objPtr->bytes[objPtr->length] = '\0';
-}
-
-static void port_update_string(Tcl_Obj *objPtr)
-{
-    const Context *ctx = static_cast<const Context *>(objPtr->internalRep.twoPtrValue.ptr1);
-    PortInfo *port_info = static_cast<PortInfo *>(objPtr->internalRep.twoPtrValue.ptr2);
-
-    std::string port_name = port_info->name.str(ctx);
-    set_tcl_obj_string(objPtr, port_name);
-}
-
-static void cell_update_string(Tcl_Obj *objPtr)
-{
-    const Context *ctx = static_cast<const Context *>(objPtr->internalRep.twoPtrValue.ptr1);
-    CellInfo *cell_info = static_cast<CellInfo *>(objPtr->internalRep.twoPtrValue.ptr2);
-
-    std::string cell_name = cell_info->name.str(ctx);
-    set_tcl_obj_string(objPtr, cell_name);
-}
-
-static void obj_dup(Tcl_Obj *srcPtr, Tcl_Obj *dupPtr)
-{
-    dupPtr->internalRep.twoPtrValue = srcPtr->internalRep.twoPtrValue;
-}
-
-static void obj_free(Tcl_Obj *objPtr) {}
-
-static void Tcl_SetStringResult(Tcl_Interp *interp, const std::string &s)
-{
-    char *copy = Tcl_Alloc(s.size() + 1);
-    std::copy(s.begin(), s.end(), copy);
-    copy[s.size()] = '\0';
-    Tcl_SetResult(interp, copy, TCL_DYNAMIC);
-}
-
-static Tcl_ObjType port_object = {
-        "port", obj_free, obj_dup, port_update_string, obj_set_from_any,
-};
-
-static Tcl_ObjType cell_object = {
-        "cell", obj_free, obj_dup, cell_update_string, obj_set_from_any,
-};
-
-static int get_ports(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-    const Context *ctx = static_cast<const Context *>(data);
-    if (objc == 1) {
-        // Return list of all ports.
-        Tcl_SetStringResult(interp, "Unimplemented");
-        return TCL_ERROR;
-    } else if (objc == 2) {
-        const char *arg0 = Tcl_GetString(objv[1]);
-        IdString port_name = ctx->id(arg0);
-
-        auto iter = ctx->ports.find(port_name);
-        if (iter == ctx->ports.end()) {
-            Tcl_SetStringResult(interp, "Could not find port " + port_name.str(ctx));
-            return TCL_ERROR;
-        }
-
-        Tcl_Obj *result = Tcl_NewObj();
-        result->typePtr = &port_object;
-        result->internalRep.twoPtrValue.ptr1 = (void *)(ctx);
-        result->internalRep.twoPtrValue.ptr2 = (void *)(&iter->second);
-
-        result->bytes = nullptr;
-        port_update_string(result);
-
-        Tcl_SetObjResult(interp, result);
-        return TCL_OK;
-    } else if (objc > 2) {
-        log_warning("get_ports options not implemented!\n");
-        return TCL_OK;
-    } else {
-        return TCL_ERROR;
-    }
-}
-
-static int get_cells(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-    const Context *ctx = static_cast<const Context *>(data);
-    if (objc == 1) {
-        // Return list of all ports.
-        Tcl_SetStringResult(interp, "Unimplemented");
-        return TCL_ERROR;
-    } else if (objc == 2) {
-        const char *arg0 = Tcl_GetString(objv[1]);
-        IdString cell_name = ctx->id(arg0);
-
-        auto iter = ctx->cells.find(cell_name);
-        if (iter == ctx->cells.end()) {
-            Tcl_SetStringResult(interp, "Could not find cell " + cell_name.str(ctx));
-            return TCL_ERROR;
-        }
-
-        Tcl_Obj *result = Tcl_NewObj();
-        result->typePtr = &cell_object;
-        result->internalRep.twoPtrValue.ptr1 = (void *)(ctx);
-        result->internalRep.twoPtrValue.ptr2 = (void *)(iter->second.get());
-
-        result->bytes = nullptr;
-        cell_update_string(result);
-
-        Tcl_SetObjResult(interp, result);
-        return TCL_OK;
-    } else if (objc > 2) {
-        log_warning("get_cells options not implemented!\n");
-        return TCL_OK;
-    } else {
-        return TCL_ERROR;
-    }
-}
-
-static int set_property(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-    // set_property <property> <value> <object>
-    if (objc != 4) {
-        Tcl_SetStringResult(interp, "Only simple 'set_property <property> <value> <object>' is supported");
-        return TCL_ERROR;
-    }
-
-    const char *property = Tcl_GetString(objv[1]);
-    const char *value = Tcl_GetString(objv[2]);
-    const Tcl_Obj *object = objv[3];
-
-    if (object->typePtr == &port_object) {
-        const Context *ctx = static_cast<const Context *>(object->internalRep.twoPtrValue.ptr1);
-        PortInfo *port_info = static_cast<PortInfo *>(object->internalRep.twoPtrValue.ptr2);
-        NPNR_ASSERT(port_info->net != nullptr);
-        CellInfo *cell = ctx->port_cells.at(port_info->name);
-
-        cell->attrs[ctx->id(property)] = Property(value);
-    } else if (object->typePtr == &cell_object) {
-        const Context *ctx = static_cast<const Context *>(object->internalRep.twoPtrValue.ptr1);
-        CellInfo *cell = static_cast<CellInfo *>(object->internalRep.twoPtrValue.ptr2);
-
-        cell->attrs[ctx->id(property)] = Property(value);
-    }
-
-    return TCL_OK;
-}
-
-static int not_implemented(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-    // TCL command that is not yet implemented
-    log_warning("%s command is not implemented!\n", Tcl_GetString(objv[0]));
-    return TCL_OK;
-}
-
-TclInterp::TclInterp(Context *ctx)
-{
-    interp = Tcl_CreateInterp();
-    NPNR_ASSERT(Tcl_Init(interp) == TCL_OK);
-
-    Tcl_RegisterObjType(&port_object);
-    Tcl_RegisterObjType(&cell_object);
-
-    NPNR_ASSERT(Tcl_Eval(interp, "rename unknown _original_unknown") == TCL_OK);
-    NPNR_ASSERT(Tcl_Eval(interp, "proc unknown args {\n"
-                                 "  set result [scan [lindex $args 0] \"%d\" value]\n"
-                                 "  if { $result == 1 && [llength $args] == 1 } {\n"
-                                 "    return \\[$value\\]\n"
-                                 "  } else {\n"
-                                 "    uplevel 1 [list _original_unknown {*}$args]\n"
-                                 "  }\n"
-                                 "}") == TCL_OK);
-    Tcl_CreateObjCommand(interp, "get_ports", get_ports, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "get_cells", get_cells, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "set_property", set_property, ctx, nullptr);
-
-    // Not implemented TCL commands
-    Tcl_CreateObjCommand(interp, "create_clock", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "get_clocks", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "get_iobanks", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "get_nets", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "get_pins", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "set_clock_groups", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "set_false_path", not_implemented, ctx, nullptr);
-    Tcl_CreateObjCommand(interp, "set_max_delay", not_implemented, ctx, nullptr);
-}
-
-TclInterp::~TclInterp() { Tcl_DeleteInterp(interp); }
-
-NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/xdc.h b/fpga_interchange/xdc.h
deleted file mode 100644
index bafd123506..0000000000
--- a/fpga_interchange/xdc.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  Symbiflow Authors
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#ifndef XDC_H
-#define XDC_H
-
-#include "nextpnr_namespaces.h"
-
-struct Tcl_Interp;
-
-NEXTPNR_NAMESPACE_BEGIN
-
-struct Context;
-
-struct TclInterp
-{
-    TclInterp(Context *ctx);
-    ~TclInterp();
-
-    Tcl_Interp *interp;
-};
-
-NEXTPNR_NAMESPACE_END
-
-#endif

From 9b51c6e337232bccde494f016b38d335aa38d4be Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Mon, 30 Sep 2024 14:51:33 +0200
Subject: [PATCH 684/712] clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/kernel/array2d.h                   |  6 ++---
 common/kernel/base_arch.h                 |  2 +-
 common/kernel/context.cc                  |  2 +-
 common/kernel/indexed_store.h             | 14 ++++++------
 common/kernel/nextpnr_base_types.h        |  6 ++---
 common/kernel/nextpnr_types.h             |  4 ++--
 common/kernel/pycontainers.h              |  4 ++--
 common/kernel/sso_array.h                 |  2 +-
 common/kernel/svg.cc                      |  2 +-
 common/kernel/timing.h                    | 16 ++++++-------
 common/kernel/util.h                      | 20 ++++++++--------
 common/place/detail_place_core.h          |  4 ++--
 common/place/parallel_refine.cc           |  4 ++--
 common/place/place_common.cc              |  6 ++---
 common/place/placer_heap.cc               | 17 +++++++-------
 common/place/placer_static.cc             |  4 ++--
 common/place/placer_static.h              |  4 ++--
 common/place/static_util.h                |  6 ++---
 common/place/timing_opt.cc                |  2 +-
 common/route/router2.cc                   |  2 +-
 ecp5/archdefs.h                           |  6 ++---
 ecp5/bitstream.cc                         |  2 +-
 ecp5/pack.cc                              |  2 +-
 frontend/json_frontend.cc                 |  2 +-
 generic/arch.h                            |  4 ++--
 generic/archdefs.h                        | 16 ++++++-------
 generic/main.cc                           |  4 ++--
 generic/viaduct/example/example.cc        |  4 ++--
 generic/viaduct/fabulous/fabric_parsing.h |  8 +++----
 generic/viaduct/fabulous/fabulous.cc      |  4 ++--
 generic/viaduct/fabulous/validity_check.h |  6 ++---
 generic/viaduct/okami/okami.cc            |  4 ++--
 generic/viaduct_api.h                     | 14 ++++++------
 generic/viaduct_helpers.h                 |  8 +++----
 gowin/main.cc                             |  4 ++--
 gui/basewindow.h                          |  4 ++--
 gui/quadtree.h                            | 28 +++++++++++------------
 himbaechel/arch.cc                        | 13 ++++-------
 himbaechel/arch.h                         | 12 +++++-----
 himbaechel/archdefs.h                     |  6 ++---
 himbaechel/himbaechel_api.h               | 16 ++++++-------
 himbaechel/himbaechel_helpers.h           |  8 +++----
 himbaechel/main.cc                        |  2 +-
 himbaechel/uarch/example/example.cc       |  4 ++--
 himbaechel/uarch/gowin/cst.cc             |  2 +-
 himbaechel/uarch/gowin/globals.cc         | 12 ++++------
 himbaechel/uarch/gowin/gowin.cc           |  4 ++--
 ice40/chains.cc                           |  2 +-
 ice40/main.cc                             |  2 +-
 machxo2/archdefs.h                        |  6 ++---
 machxo2/bitstream.cc                      |  2 +-
 machxo2/globals.cc                        |  2 +-
 machxo2/main.cc                           |  4 ++--
 machxo2/pack.cc                           |  2 +-
 mistral/arch.h                            | 10 ++++----
 mistral/archdefs.h                        |  4 ++--
 mistral/bitstream.cc                      |  2 +-
 mistral/globals.cc                        |  2 +-
 mistral/main.cc                           |  4 ++--
 mistral/pack.cc                           |  2 +-
 mistral/qsf.cc                            |  2 +-
 nexus/archdefs.h                          |  6 ++---
 nexus/global.cc                           |  2 +-
 nexus/main.cc                             |  4 ++--
 nexus/pdc.cc                              |  6 ++---
 nexus/post_place.cc                       |  2 +-
 66 files changed, 192 insertions(+), 200 deletions(-)

diff --git a/common/kernel/array2d.h b/common/kernel/array2d.h
index bb1a150db6..513dabae3f 100644
--- a/common/kernel/array2d.h
+++ b/common/kernel/array2d.h
@@ -35,7 +35,7 @@ NEXTPNR_NAMESPACE_BEGIN
 template <typename T> class array2d
 {
   public:
-    array2d() : m_width(0), m_height(0), m_size(0), data(nullptr){};
+    array2d() : m_width(0), m_height(0), m_size(0), data(nullptr) {};
     array2d(int width, int height) : m_width(width), m_height(height), m_size(width * height)
     {
         data = new T[m_width * m_height]();
@@ -88,7 +88,7 @@ template <typename T> class array2d
     ~array2d() { delete[] data; }
     struct entry
     {
-        entry(int x, int y, T &value) : x(x), y(y), value(value){};
+        entry(int x, int y, T &value) : x(x), y(y), value(value) {};
         int x, y;
         T &value;
     };
@@ -119,7 +119,7 @@ template <typename T> class array2d
         inline bool operator==(const iterator &other) const { return other.x == x && other.y == y; }
 
       private:
-        iterator(int x, int y, array2d<T> &base) : x(x), y(y), base(&base){};
+        iterator(int x, int y, array2d<T> &base) : x(x), y(y), base(&base) {};
         int x, y;
         array2d<T> *base;
         friend class array2d;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 5aa655a5cc..708636a0d1 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -443,7 +443,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
     }
 
     // Flow methods
-    virtual void assignArchInfo() override{};
+    virtual void assignArchInfo() override {};
 
     // --------------------------------------------------------------
     // These structures are used to provide default implementations of bel/wire/pip binding. Arches might want to
diff --git a/common/kernel/context.cc b/common/kernel/context.cc
index b194675d4e..b845365c46 100644
--- a/common/kernel/context.cc
+++ b/common/kernel/context.cc
@@ -417,7 +417,7 @@ void Context::check() const
 namespace {
 struct FixupHierarchyWorker
 {
-    FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
+    FixupHierarchyWorker(Context *ctx) : ctx(ctx) {};
     Context *ctx;
     void run()
     {
diff --git a/common/kernel/indexed_store.h b/common/kernel/indexed_store.h
index df607c13de..f15f66dbb5 100644
--- a/common/kernel/indexed_store.h
+++ b/common/kernel/indexed_store.h
@@ -34,7 +34,7 @@ template <typename T> struct store_index
 {
     int32_t m_index = -1;
     store_index() = default;
-    explicit store_index(int32_t index) : m_index(index){};
+    explicit store_index(int32_t index) : m_index(index) {};
     int32_t idx() const { return m_index; }
     void set(int32_t index) { m_index = index; }
     bool empty() const { return m_index == -1; }
@@ -64,7 +64,7 @@ template <typename T> class indexed_store
         friend class indexed_store<T>;
 
       public:
-        slot() : next_free(std::numeric_limits<int32_t>::max()), active(false){};
+        slot() : next_free(std::numeric_limits<int32_t>::max()), active(false) {};
         slot(slot &&other) : next_free(other.next_free), active(other.active)
         {
             if (active)
@@ -180,7 +180,7 @@ template <typename T> class indexed_store
         int32_t index = 0;
 
       public:
-        iterator(indexed_store *base, int32_t index) : base(base), index(index){};
+        iterator(indexed_store *base, int32_t index) : base(base), index(index) {};
         inline bool operator!=(const iterator &other) const { return other.index != index; }
         inline bool operator==(const iterator &other) const { return other.index == index; }
         inline iterator operator++()
@@ -217,7 +217,7 @@ template <typename T> class indexed_store
         int32_t index = 0;
 
       public:
-        const_iterator(const indexed_store *base, int32_t index) : base(base), index(index){};
+        const_iterator(const indexed_store *base, int32_t index) : base(base), index(index) {};
         inline bool operator!=(const const_iterator &other) const { return other.index != index; }
         inline bool operator==(const const_iterator &other) const { return other.index == index; }
         inline const_iterator operator++()
@@ -249,7 +249,7 @@ template <typename T> class indexed_store
 
     template <typename S> struct enumerated_item
     {
-        enumerated_item(int32_t index, T &value) : index(index), value(value){};
+        enumerated_item(int32_t index, T &value) : index(index), value(value) {};
         store_index<std::remove_cv_t<S>> index;
         S &value;
     };
@@ -260,7 +260,7 @@ template <typename T> class indexed_store
         It base;
 
       public:
-        enumerated_iterator(const It &base) : base(base){};
+        enumerated_iterator(const It &base) : base(base) {};
         inline bool operator!=(const enumerated_iterator<It, S> &other) const { return other.base != base; }
         inline bool operator==(const enumerated_iterator<It, S> &other) const { return other.base == base; }
         inline enumerated_iterator<It, S> operator++()
@@ -279,7 +279,7 @@ template <typename T> class indexed_store
 
     template <typename It, typename S> struct enumerated_range
     {
-        enumerated_range(const It &begin, const It &end) : m_begin(begin), m_end(end){};
+        enumerated_range(const It &begin, const It &end) : m_begin(begin), m_end(end) {};
         enumerated_iterator<It, S> m_begin, m_end;
         enumerated_iterator<It, S> begin() { return m_begin; }
         enumerated_iterator<It, S> end() { return m_end; }
diff --git a/common/kernel/nextpnr_base_types.h b/common/kernel/nextpnr_base_types.h
index 80a0e24ee1..ad5a295ca2 100644
--- a/common/kernel/nextpnr_base_types.h
+++ b/common/kernel/nextpnr_base_types.h
@@ -78,9 +78,9 @@ struct GraphicElement
 
     float x1 = 0, y1 = 0, x2 = 0, y2 = 0, z = 0;
     std::string text;
-    GraphicElement(){};
+    GraphicElement() {};
     GraphicElement(type_t type, style_t style, float x1, float y1, float x2, float y2, float z)
-            : type(type), style(style), x1(x1), y1(y1), x2(x2), y2(y2), z(z){};
+            : type(type), style(style), x1(x1), y1(y1), x2(x2), y2(y2), z(z) {};
 };
 
 struct Loc
@@ -100,7 +100,7 @@ struct BoundingBox
     int x0 = -1, y0 = -1, x1 = -1, y1 = -1;
 
     BoundingBox() {}
-    BoundingBox(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1){};
+    BoundingBox(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1) {};
 
     int distance(Loc loc) const
     {
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index e23cd16a35..fbe16daf7e 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -90,7 +90,7 @@ inline bool is_zero_delay(delay_t delay)
 // minimum and maximum delay
 struct DelayPair
 {
-    DelayPair() : min_delay(0), max_delay(0){};
+    DelayPair() : min_delay(0), max_delay(0) {};
     explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) {}
     DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) {}
     delay_t minDelay() const { return min_delay; }
@@ -287,7 +287,7 @@ struct PseudoCell
     virtual bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const = 0;
     virtual TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const = 0;
     virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const = 0;
-    virtual ~PseudoCell(){};
+    virtual ~PseudoCell() {};
 };
 
 struct RegionPlug : PseudoCell
diff --git a/common/kernel/pycontainers.h b/common/kernel/pycontainers.h
index d79508b969..175d2608d7 100644
--- a/common/kernel/pycontainers.h
+++ b/common/kernel/pycontainers.h
@@ -76,8 +76,8 @@ A pair that doesn't automatically become a tuple
 */
 template <typename Ta, typename Tb> struct iter_pair
 {
-    iter_pair(){};
-    iter_pair(const Ta &first, const Tb &second) : first(first), second(second){};
+    iter_pair() {};
+    iter_pair(const Ta &first, const Tb &second) : first(first), second(second) {};
     Ta first;
     Tb second;
 };
diff --git a/common/kernel/sso_array.h b/common/kernel/sso_array.h
index 80e7d1c1fd..f2b8dfded7 100644
--- a/common/kernel/sso_array.h
+++ b/common/kernel/sso_array.h
@@ -56,7 +56,7 @@ template <typename T, std::size_t N> class SSOArray
     const T *begin() const { return data(); }
     const T *end() const { return data() + m_size; }
 
-    SSOArray() : m_size(0){};
+    SSOArray() : m_size(0) {};
 
     SSOArray(std::size_t size, const T &init = T()) : m_size(size)
     {
diff --git a/common/kernel/svg.cc b/common/kernel/svg.cc
index c5e2ea36c9..4fef53b7e1 100644
--- a/common/kernel/svg.cc
+++ b/common/kernel/svg.cc
@@ -31,7 +31,7 @@ struct SVGWriter
     std::ostream &out;
     float scale = 500.0;
     bool hide_inactive = false;
-    SVGWriter(const Context *ctx, std::ostream &out) : ctx(ctx), out(out){};
+    SVGWriter(const Context *ctx, std::ostream &out) : ctx(ctx), out(out) {};
     const char *get_stroke_colour(GraphicElement::style_t style)
     {
         switch (style) {
diff --git a/common/kernel/timing.h b/common/kernel/timing.h
index f82a1b6da6..4fe42866b7 100644
--- a/common/kernel/timing.h
+++ b/common/kernel/timing.h
@@ -27,8 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct CellPortKey
 {
-    CellPortKey(){};
-    CellPortKey(IdString cell, IdString port) : cell(cell), port(port){};
+    CellPortKey() {};
+    CellPortKey(IdString cell, IdString port) : cell(cell), port(port) {};
     explicit CellPortKey(const PortRef &pr)
     {
         NPNR_ASSERT(pr.cell != nullptr);
@@ -49,7 +49,7 @@ struct ClockDomainKey
 {
     IdString clock;
     ClockEdge edge;
-    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge){};
+    ClockDomainKey(IdString clock_net, ClockEdge edge) : clock(clock_net), edge(edge) {};
     // probably also need something here to deal with constraints
     inline bool is_async() const { return clock == IdString(); }
 
@@ -63,7 +63,7 @@ typedef int domain_id_t;
 struct ClockDomainPairKey
 {
     domain_id_t launch, capture;
-    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture){};
+    ClockDomainPairKey(domain_id_t launch, domain_id_t capture) : launch(launch), capture(capture) {};
     inline bool operator==(const ClockDomainPairKey &other) const
     {
         return (launch == other.launch) && (capture == other.capture);
@@ -183,9 +183,9 @@ struct TimingAnalyser
         ClockEdge edge;
 
         CellArc(ArcType type, IdString other_port, DelayQuad value)
-                : type(type), other_port(other_port), value(value), edge(RISING_EDGE){};
+                : type(type), other_port(other_port), value(value), edge(RISING_EDGE) {};
         CellArc(ArcType type, IdString other_port, DelayQuad value, ClockEdge edge)
-                : type(type), other_port(other_port), value(value), edge(edge){};
+                : type(type), other_port(other_port), value(value), edge(edge) {};
     };
 
     // Timing data for every cell port
@@ -209,7 +209,7 @@ struct TimingAnalyser
 
     struct PerDomain
     {
-        PerDomain(ClockDomainKey key) : key(key){};
+        PerDomain(ClockDomainKey key) : key(key) {};
         ClockDomainKey key;
         // these are pairs (signal port; clock port)
         std::vector<std::pair<CellPortKey, IdString>> startpoints, endpoints;
@@ -217,7 +217,7 @@ struct TimingAnalyser
 
     struct PerDomainPair
     {
-        PerDomainPair(ClockDomainPairKey key) : key(key){};
+        PerDomainPair(ClockDomainPairKey key) : key(key) {};
         ClockDomainPairKey key;
         DelayPair period{0};
         delay_t worst_setup_slack, worst_hold_slack;
diff --git a/common/kernel/util.h b/common/kernel/util.h
index 0223470aff..2f7f80b1b5 100644
--- a/common/kernel/util.h
+++ b/common/kernel/util.h
@@ -112,10 +112,10 @@ bool boolstr_or_default(const dict<KeyType, Property> &ct, const KeyType &key, b
         return def;
     if (!found->second.is_string)
         bool(found->second.as_int64());
-    const char* str = found->second.as_string().c_str();
-    if(!strcmp(str, "0") || !strcasecmp(str, "false"))
+    const char *str = found->second.as_string().c_str();
+    if (!strcmp(str, "0") || !strcasecmp(str, "false"))
         return false;
-    else if(!strcmp(str, "1") || !strcasecmp(str, "true"))
+    else if (!strcmp(str, "1") || !strcasecmp(str, "true"))
         return true;
     else
         log_error("Expecting bool-compatible value but got '%s'.\n", found->second.as_string().c_str());
@@ -125,20 +125,18 @@ bool boolstr_or_default(const dict<KeyType, Property> &ct, const KeyType &key, b
 // Get a vector of bool from a map-style container, returning default if value is not found
 // Also tolerate string representation of vector for interoperability purposes
 template <typename KeyType>
-bool boolvec_populate(const dict<KeyType, Property> &ct, const KeyType &key, std::vector<bool>& vec)
+bool boolvec_populate(const dict<KeyType, Property> &ct, const KeyType &key, std::vector<bool> &vec)
 {
     auto found = ct.find(key);
     if (found == ct.end())
         return false;
-    if (!found->second.is_string)
-    {
+    if (!found->second.is_string) {
         size_t val = found->second.as_int64();
-        for (size_t i = 0; i < vec.size(); ++i, val>>=1) {
+        for (size_t i = 0; i < vec.size(); ++i, val >>= 1) {
             vec[i] = (val & 0x1) != 0;
         }
-    }
-    else {
-        const std::string& str = found->second.as_string();
+    } else {
+        const std::string &str = found->second.as_string();
         size_t i = 0;
         for (auto it = str.crbegin(); it != str.crend() && i < vec.size(); ++i, ++it) {
             vec[i] = *it == '1';
@@ -255,7 +253,7 @@ template <typename T, typename C = std::less<T>> struct TopoSort
 template <typename T> struct reversed_range_t
 {
     T &obj;
-    explicit reversed_range_t(T &obj) : obj(obj){};
+    explicit reversed_range_t(T &obj) : obj(obj) {};
     auto begin() { return obj.rbegin(); }
     auto end() { return obj.rend(); }
 };
diff --git a/common/place/detail_place_core.h b/common/place/detail_place_core.h
index aaca82f900..1d57001f44 100644
--- a/common/place/detail_place_core.h
+++ b/common/place/detail_place_core.h
@@ -85,7 +85,7 @@ struct NetBB
 struct DetailPlacerState
 {
     explicit DetailPlacerState(Context *ctx, DetailPlaceCfg &cfg)
-            : ctx(ctx), base_cfg(cfg), bels(ctx, false, 64), tmg(ctx){};
+            : ctx(ctx), base_cfg(cfg), bels(ctx, false, 64), tmg(ctx) {};
     Context *ctx;
     DetailPlaceCfg &base_cfg;
     FastBels bels;
@@ -196,7 +196,7 @@ struct DetailPlacerThreadState
     std::vector<std::pair<int, store_index<PortRef>>> timing_changed_arcs;
     std::vector<double> new_timing_costs;
 
-    DetailPlacerThreadState(Context *ctx, DetailPlacerState &g, int idx) : ctx(ctx), g(g), idx(idx){};
+    DetailPlacerThreadState(Context *ctx, DetailPlacerState &g, int idx) : ctx(ctx), g(g), idx(idx) {};
     void set_partition(const PlacePartition &part);
     void setup_initial_state();
     bool bounds_check(BelId bel);
diff --git a/common/place/parallel_refine.cc b/common/place/parallel_refine.cc
index 5712462965..24591ce100 100644
--- a/common/place/parallel_refine.cc
+++ b/common/place/parallel_refine.cc
@@ -37,7 +37,7 @@ namespace {
 
 struct GlobalState : DetailPlacerState
 {
-    explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : DetailPlacerState(ctx, this->cfg), cfg(cfg){};
+    explicit GlobalState(Context *ctx, ParallelRefineCfg cfg) : DetailPlacerState(ctx, this->cfg), cfg(cfg) {};
 
     dict<ClusterId, std::vector<CellInfo *>> cluster2cells;
 
@@ -49,7 +49,7 @@ struct GlobalState : DetailPlacerState
 
 struct ThreadState : DetailPlacerThreadState
 {
-    ThreadState(Context *ctx, GlobalState &g, int idx) : DetailPlacerThreadState(ctx, g, idx), g(g){};
+    ThreadState(Context *ctx, GlobalState &g, int idx) : DetailPlacerThreadState(ctx, g, idx), g(g) {};
     // Total made and accepted moved
     GlobalState &g;
     int n_move = 0, n_accept = 0;
diff --git a/common/place/place_common.cc b/common/place/place_common.cc
index c044e7e749..2ddbcb6015 100644
--- a/common/place/place_common.cc
+++ b/common/place/place_common.cc
@@ -115,9 +115,9 @@ class ConstraintLegaliseWorker
     class IncreasingDiameterSearch
     {
       public:
-        IncreasingDiameterSearch() : start(0), min(0), max(-1){};
-        IncreasingDiameterSearch(int x) : start(x), min(x), max(x){};
-        IncreasingDiameterSearch(int start, int min, int max) : start(start), min(min), max(max){};
+        IncreasingDiameterSearch() : start(0), min(0), max(-1) {};
+        IncreasingDiameterSearch(int x) : start(x), min(x), max(x) {};
+        IncreasingDiameterSearch(int start, int min, int max) : start(start), min(min), max(max) {};
         bool done() const { return (diameter > (max - min)); };
         int get() const
         {
diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index 132da8b972..b2ae6dbe84 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -319,20 +319,20 @@ class HeAPPlacer
             ctx->bindBel(bel, cell, strength);
         }
 
-				// Find and display all errors to help in finding the root cause of issues
+        // Find and display all errors to help in finding the root cause of issues
         unsigned num_errors = 0;
         for (auto &cell : ctx->cells) {
             if (cell.second->isPseudo())
                 continue;
             if (cell.second->bel == BelId()) {
-                log_nonfatal_error("Found unbound cell '%s' of type '%s'\n", cell.first.c_str(ctx), cell.second->type.c_str(ctx));
+                log_nonfatal_error("Found unbound cell '%s' of type '%s'\n", cell.first.c_str(ctx),
+                                   cell.second->type.c_str(ctx));
                 num_errors++;
-            }
-            else if (ctx->getBoundBelCell(cell.second->bel) != cell.second.get()) {
-                log_nonfatal_error("Found mismatched binding for '%s' or type '%s'\n", cell.first.c_str(ctx), cell.second->type.c_str(ctx));
+            } else if (ctx->getBoundBelCell(cell.second->bel) != cell.second.get()) {
+                log_nonfatal_error("Found mismatched binding for '%s' or type '%s'\n", cell.first.c_str(ctx),
+                                   cell.second->type.c_str(ctx));
                 num_errors++;
-            }
-            else if (ctx->debug)
+            } else if (ctx->debug)
                 log_info("AP soln: %s -> %s\n", cell.first.c_str(ctx), ctx->nameOfBel(cell.second->bel));
         }
         if (num_errors > 0) {
@@ -899,7 +899,8 @@ class HeAPPlacer
 
             while (!placed) {
                 if (cfg.cell_placement_timeout > 0 && total_iters_for_cell > cfg.cell_placement_timeout)
-                    log_error("Unable to find legal placement for cell '%s' of type '%s' after %d attempts, check constraints and "
+                    log_error("Unable to find legal placement for cell '%s' of type '%s' after %d attempts, check "
+                              "constraints and "
                               "utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of "
                               "attempts.\n",
                               ctx->nameOf(ci), ci->type.c_str(ctx), total_iters_for_cell);
diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index e75ccfb8f1..9b20af306d 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -105,7 +105,7 @@ struct ConcreteCell
 
 struct ClusterGroupKey
 {
-    ClusterGroupKey(int dx = 0, int dy = 0, int group = -1) : dx(dx), dy(dy), group(group){};
+    ClusterGroupKey(int dx = 0, int dy = 0, int group = -1) : dx(dx), dy(dy), group(group) {};
     bool operator==(const ClusterGroupKey &other) const
     {
         return dx == other.dx && dy == other.dy && group == other.group;
@@ -155,7 +155,7 @@ struct PlacerNet
 #ifdef NPNR_DISABLE_THREADS
 struct ThreadPool
 {
-    ThreadPool(int){};
+    ThreadPool(int) {};
 
     void run(int N, std::function<void(int)> func)
     {
diff --git a/common/place/placer_static.h b/common/place/placer_static.h
index ac43920d52..1f7097de6e 100644
--- a/common/place/placer_static.h
+++ b/common/place/placer_static.h
@@ -27,8 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct StaticRect
 {
-    StaticRect() : w(0), h(0){};
-    StaticRect(float w, float h) : w(w), h(h){};
+    StaticRect() : w(0), h(0) {};
+    StaticRect(float w, float h) : w(w), h(h) {};
     float w, h;
     float area() const { return w * h; }
 };
diff --git a/common/place/static_util.h b/common/place/static_util.h
index a3dc5c9368..bbaa3d9bb7 100644
--- a/common/place/static_util.h
+++ b/common/place/static_util.h
@@ -36,9 +36,9 @@ enum class Axis
 
 struct RealPair
 {
-    RealPair() : x(0), y(0){};
-    RealPair(float x, float y) : x(x), y(y){};
-    explicit RealPair(Loc l, float bias = 0.0f) : x(l.x + bias), y(l.y + bias){};
+    RealPair() : x(0), y(0) {};
+    RealPair(float x, float y) : x(x), y(y) {};
+    explicit RealPair(Loc l, float bias = 0.0f) : x(l.x + bias), y(l.y + bias) {};
     float x, y;
     RealPair &operator+=(const RealPair &other)
     {
diff --git a/common/place/timing_opt.cc b/common/place/timing_opt.cc
index f9246292d5..5d59b9c19d 100644
--- a/common/place/timing_opt.cc
+++ b/common/place/timing_opt.cc
@@ -40,7 +40,7 @@ NEXTPNR_NAMESPACE_BEGIN
 class TimingOptimiser
 {
   public:
-    TimingOptimiser(Context *ctx, TimingOptCfg cfg) : ctx(ctx), cfg(cfg), tmg(ctx){};
+    TimingOptimiser(Context *ctx, TimingOptCfg cfg) : ctx(ctx), cfg(cfg), tmg(ctx) {};
     bool optimise()
     {
         log_info("Running timing-driven placement optimisation...\n");
diff --git a/common/route/router2.cc b/common/route/router2.cc
index 53596c24af..a19046a67d 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -241,7 +241,7 @@ struct Router2
     {
 
         explicit QueuedWire(int wire = -1, WireScore score = WireScore{}, int randtag = 0)
-                : wire(wire), score(score), randtag(randtag){};
+                : wire(wire), score(score), randtag(randtag) {};
 
         int wire;
         WireScore score;
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index b7d892c538..95c369399c 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -55,9 +55,9 @@ NPNR_PACKED_STRUCT(struct LocationPOD { int16_t x, y; });
 struct Location
 {
     int16_t x = -1, y = -1;
-    Location() : x(-1), y(-1){};
-    Location(int16_t x, int16_t y) : x(x), y(y){};
-    Location(const LocationPOD &pod) : x(pod.x), y(pod.y){};
+    Location() : x(-1), y(-1) {};
+    Location(int16_t x, int16_t y) : x(x), y(y) {};
+    Location(const LocationPOD &pod) : x(pod.x), y(pod.y) {};
 
     bool operator==(const Location &other) const { return x == other.x && y == other.y; }
     bool operator!=(const Location &other) const { return x != other.x || y != other.y; }
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 32f5bd3d6c..31b5041d95 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -49,7 +49,7 @@ void config_empty_lfe5um5g_85f(ChipConfig &cc);
 namespace {
 struct ECP5Bitgen
 {
-    explicit ECP5Bitgen(Context *ctx) : ctx(ctx){};
+    explicit ECP5Bitgen(Context *ctx) : ctx(ctx) {};
     Context *ctx;
     ChipConfig cc;
     std::string get_trellis_wirename(Location loc, WireId wire)
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 7d7c044c92..ad6d9bf816 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -53,7 +53,7 @@ static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
 class Ecp5Packer
 {
   public:
-    Ecp5Packer(Context *ctx) : ctx(ctx){};
+    Ecp5Packer(Context *ctx) : ctx(ctx) {};
 
   private:
     // Process the contents of packed_cells and new_cells
diff --git a/frontend/json_frontend.cc b/frontend/json_frontend.cc
index f2fb3ac06f..6004ee17ce 100644
--- a/frontend/json_frontend.cc
+++ b/frontend/json_frontend.cc
@@ -32,7 +32,7 @@ using namespace json11;
 struct JsonFrontendImpl
 {
     // See specification in frontend_base.h
-    JsonFrontendImpl(Json &root) : root(root){};
+    JsonFrontendImpl(Json &root) : root(root) {};
     Json &root;
     typedef const Json &ModuleDataType;
     typedef const Json &ModulePortDataType;
diff --git a/generic/arch.h b/generic/arch.h
index f4977e1e19..1bf1f0b667 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -115,14 +115,14 @@ template <typename TId> struct linear_range
 {
     struct iterator
     {
-        explicit iterator(int32_t index) : index(index){};
+        explicit iterator(int32_t index) : index(index) {};
         int32_t index;
         bool operator==(const iterator &other) const { return index == other.index; }
         bool operator!=(const iterator &other) const { return index != other.index; }
         void operator++() { ++index; }
         TId operator*() const { return TId(index); }
     };
-    explicit linear_range(int32_t size) : size(size){};
+    explicit linear_range(int32_t size) : size(size) {};
     int32_t size;
     iterator begin() const { return iterator(0); }
     iterator end() const { return iterator(size); }
diff --git a/generic/archdefs.h b/generic/archdefs.h
index 374ddeb0fb..dd4377cce2 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -30,8 +30,8 @@ typedef float delay_t;
 
 struct BelId
 {
-    BelId() : index(-1){};
-    explicit BelId(int32_t index) : index(index){};
+    BelId() : index(-1) {};
+    explicit BelId(int32_t index) : index(index) {};
     int32_t index = -1;
 
     bool operator==(const BelId &other) const { return index == other.index; }
@@ -42,8 +42,8 @@ struct BelId
 
 struct WireId
 {
-    WireId() : index(-1){};
-    explicit WireId(int32_t index) : index(index){};
+    WireId() : index(-1) {};
+    explicit WireId(int32_t index) : index(index) {};
     int32_t index = -1;
 
     bool operator==(const WireId &other) const { return index == other.index; }
@@ -54,8 +54,8 @@ struct WireId
 
 struct PipId
 {
-    PipId() : index(-1){};
-    explicit PipId(int32_t index) : index(index){};
+    PipId() : index(-1) {};
+    explicit PipId(int32_t index) : index(index) {};
     int32_t index = -1;
 
     bool operator==(const PipId &other) const { return index == other.index; }
@@ -68,8 +68,8 @@ struct DecalId
 {
     IdStringList name;
     bool active = false;
-    DecalId() : name(), active(false){};
-    DecalId(IdStringList name, bool active) : name(name), active(active){};
+    DecalId() : name(), active(false) {};
+    DecalId(IdStringList name, bool active) : name(name), active(active) {};
     bool operator==(const DecalId &other) const { return name == other.name && active == other.active; }
     bool operator!=(const DecalId &other) const { return name != other.name || active != other.active; }
     unsigned int hash() const { return mkhash(name.hash(), active); }
diff --git a/generic/main.cc b/generic/main.cc
index 7aece56999..f1ce373ba6 100644
--- a/generic/main.cc
+++ b/generic/main.cc
@@ -31,9 +31,9 @@ class GenericCommandHandler : public CommandHandler
 {
   public:
     GenericCommandHandler(int argc, char **argv);
-    virtual ~GenericCommandHandler(){};
+    virtual ~GenericCommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customBitstream(Context *ctx) override;
 
   protected:
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
index 7de0404bb7..bf3a98d872 100644
--- a/generic/viaduct/example/example.cc
+++ b/generic/viaduct/example/example.cc
@@ -32,7 +32,7 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace {
 struct ExampleImpl : ViaductAPI
 {
-    ~ExampleImpl(){};
+    ~ExampleImpl() {};
     void init(Context *ctx) override
     {
         init_uarch_constids(ctx);
@@ -321,7 +321,7 @@ struct ExampleImpl : ViaductAPI
 
 struct ExampleArch : ViaductArch
 {
-    ExampleArch() : ViaductArch("example"){};
+    ExampleArch() : ViaductArch("example") {};
     std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
     {
         return std::make_unique<ExampleImpl>();
diff --git a/generic/viaduct/fabulous/fabric_parsing.h b/generic/viaduct/fabulous/fabric_parsing.h
index 841b246550..a66220f4ed 100644
--- a/generic/viaduct/fabulous/fabric_parsing.h
+++ b/generic/viaduct/fabulous/fabric_parsing.h
@@ -36,9 +36,9 @@ struct parser_view
 {
     char *m_ptr;
     size_t m_length;
-    parser_view() : m_ptr(nullptr), m_length(0){};
-    explicit parser_view(std::string &str) : m_ptr(&(str[0])), m_length(str.size()){};
-    parser_view(char *ptr, size_t length) : m_ptr(ptr), m_length(length){};
+    parser_view() : m_ptr(nullptr), m_length(0) {};
+    explicit parser_view(std::string &str) : m_ptr(&(str[0])), m_length(str.size()) {};
+    parser_view(char *ptr, size_t length) : m_ptr(ptr), m_length(length) {};
 
     static constexpr size_t npos = std::numeric_limits<size_t>::max();
     char operator[](size_t idx)
@@ -151,7 +151,7 @@ struct parser_view
 
 struct CsvParser
 {
-    explicit CsvParser(std::istream &in) : in(in){};
+    explicit CsvParser(std::istream &in) : in(in) {};
     std::istream &in;
     std::string buf;
     parser_view view;
diff --git a/generic/viaduct/fabulous/fabulous.cc b/generic/viaduct/fabulous/fabulous.cc
index ed528b0bb9..6160ff7282 100644
--- a/generic/viaduct/fabulous/fabulous.cc
+++ b/generic/viaduct/fabulous/fabulous.cc
@@ -55,7 +55,7 @@ struct FabulousImpl : ViaductAPI
         }
     }
 
-    ~FabulousImpl(){};
+    ~FabulousImpl() {};
     void init(Context *ctx) override
     {
         init_uarch_constids(ctx);
@@ -666,7 +666,7 @@ struct FabulousImpl : ViaductAPI
 
 struct FabulousArch : ViaductArch
 {
-    FabulousArch() : ViaductArch("fabulous"){};
+    FabulousArch() : ViaductArch("fabulous") {};
     std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
     {
         return std::make_unique<FabulousImpl>(args);
diff --git a/generic/viaduct/fabulous/validity_check.h b/generic/viaduct/fabulous/validity_check.h
index 1f21e07b58..bb74de59aa 100644
--- a/generic/viaduct/fabulous/validity_check.h
+++ b/generic/viaduct/fabulous/validity_check.h
@@ -33,8 +33,8 @@ NEXTPNR_NAMESPACE_BEGIN
 // validity checking code
 struct ControlSig
 {
-    ControlSig() : net(), invert(false){};
-    ControlSig(IdString net, bool invert) : net(net), invert(invert){};
+    ControlSig() : net(), invert(false) {};
+    ControlSig(IdString net, bool invert) : net(net), invert(invert) {};
     IdString net;
     bool invert;
     bool operator==(const ControlSig &other) const { return net == other.net && invert == other.invert; }
@@ -110,7 +110,7 @@ struct BlockTracker
     const FabricConfig &cfg;
     std::vector<BelFlags> bel_data;
 
-    BlockTracker(Context *ctx, const FabricConfig &cfg) : ctx(ctx), cfg(cfg){};
+    BlockTracker(Context *ctx, const FabricConfig &cfg) : ctx(ctx), cfg(cfg) {};
     void set_bel_type(BelId bel, BelFlags::BlockType block, BelFlags::FuncType func, uint8_t index);
     void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell);
     struct TileData
diff --git a/generic/viaduct/okami/okami.cc b/generic/viaduct/okami/okami.cc
index 4ff97cb336..12aa96a4be 100644
--- a/generic/viaduct/okami/okami.cc
+++ b/generic/viaduct/okami/okami.cc
@@ -33,7 +33,7 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace {
 struct OkamiImpl : ViaductAPI
 {
-    ~OkamiImpl(){};
+    ~OkamiImpl() {};
     void init(Context *ctx) override
     {
         init_uarch_constids(ctx);
@@ -534,7 +534,7 @@ struct OkamiImpl : ViaductAPI
 
 struct OkamiArch : ViaductArch
 {
-    OkamiArch() : ViaductArch("okami"){};
+    OkamiArch() : ViaductArch("okami") {};
     std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
     {
         return std::make_unique<OkamiImpl>();
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
index 6d6423b66e..03cf801e37 100644
--- a/generic/viaduct_api.h
+++ b/generic/viaduct_api.h
@@ -86,14 +86,14 @@ struct ViaductAPI
     virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const;
 
     // --- Flow hooks ---
-    virtual void pack(){}; // replaces the pack function
+    virtual void pack() {}; // replaces the pack function
     // Called before and after main placement and routing
-    virtual void prePlace(){};
-    virtual void postPlace(){};
-    virtual void preRoute(){};
-    virtual void postRoute(){};
+    virtual void prePlace() {};
+    virtual void postPlace() {};
+    virtual void preRoute() {};
+    virtual void postRoute() {};
 
-    virtual ~ViaductAPI(){};
+    virtual ~ViaductAPI() {};
 };
 
 struct ViaductArch
@@ -103,7 +103,7 @@ struct ViaductArch
 
     std::string name;
     ViaductArch(const std::string &name);
-    ~ViaductArch(){};
+    ~ViaductArch() {};
     virtual std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args) = 0;
 
     static std::string list();
diff --git a/generic/viaduct_helpers.h b/generic/viaduct_helpers.h
index 213995dba1..78fef4eab7 100644
--- a/generic/viaduct_helpers.h
+++ b/generic/viaduct_helpers.h
@@ -36,10 +36,10 @@ viaduct_helpers provides some features for building up arches using the viaduct
 // Used to configure various generic pack functions
 struct CellTypePort
 {
-    CellTypePort() : cell_type(), port(){};
-    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port){};
+    CellTypePort() : cell_type(), port() {};
+    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port) {};
     explicit CellTypePort(const PortRef &net_port)
-            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port){};
+            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port) {};
     inline bool operator==(const CellTypePort &other) const
     {
         return cell_type == other.cell_type && port == other.port;
@@ -54,7 +54,7 @@ struct CellTypePort
 
 struct ViaductHelpers
 {
-    ViaductHelpers(){};
+    ViaductHelpers() {};
     Context *ctx;
     void init(Context *ctx) { this->ctx = ctx; }
     // IdStringList components for x and y locations
diff --git a/gowin/main.cc b/gowin/main.cc
index 15b1914d86..13f16fa703 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -34,9 +34,9 @@ class GowinCommandHandler : public CommandHandler
 {
   public:
     GowinCommandHandler(int argc, char **argv);
-    virtual ~GowinCommandHandler(){};
+    virtual ~GowinCommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customAfterLoad(Context *ctx) override;
 
   protected:
diff --git a/gui/basewindow.h b/gui/basewindow.h
index 00b8f45cb1..5c11f9d2de 100644
--- a/gui/basewindow.h
+++ b/gui/basewindow.h
@@ -58,8 +58,8 @@ class BaseMainWindow : public QMainWindow
     void disableActions();
     void enableDisableDecals();
 
-    virtual void onDisableActions(){};
-    virtual void onUpdateActions(){};
+    virtual void onDisableActions() {};
+    virtual void onUpdateActions() {};
 
   protected Q_SLOTS:
     void writeInfo(std::string text);
diff --git a/gui/quadtree.h b/gui/quadtree.h
index f240f34589..267695351e 100644
--- a/gui/quadtree.h
+++ b/gui/quadtree.h
@@ -264,20 +264,20 @@ template <typename CoordinateT, typename ElementT> class QuadTreeNode
             splitx_ = (bound_.x1_ - bound_.x0_) / 2 + bound_.x0_;
             splity_ = (bound_.y1_ - bound_.y0_) / 2 + bound_.y0_;
             // Create the new children.
-            children_ = decltype(children_)(new QuadTreeNode<CoordinateT, ElementT>[4] {
-                // Note: not using [NW] = QuadTreeNode because that seems to
-                //       crash g++ 7.3.0.
-                /* NW */ QuadTreeNode<CoordinateT, ElementT>(BoundingBox(bound_.x0_, bound_.y0_, splitx_, splity_),
-                                                             depth_ + 1, max_elems_),
-                        /* NE */
-                        QuadTreeNode<CoordinateT, ElementT>(BoundingBox(splitx_, bound_.y0_, bound_.x1_, splity_),
-                                                            depth_ + 1, max_elems_),
-                        /* SW */
-                        QuadTreeNode<CoordinateT, ElementT>(BoundingBox(bound_.x0_, splity_, splitx_, bound_.y1_),
-                                                            depth_ + 1, max_elems_),
-                        /* SE */
-                        QuadTreeNode<CoordinateT, ElementT>(BoundingBox(splitx_, splity_, bound_.x1_, bound_.y1_),
-                                                            depth_ + 1, max_elems_),
+            children_ = decltype(children_)(new QuadTreeNode<CoordinateT, ElementT>[4]{
+                    // Note: not using [NW] = QuadTreeNode because that seems to
+                    //       crash g++ 7.3.0.
+                    /* NW */ QuadTreeNode<CoordinateT, ElementT>(BoundingBox(bound_.x0_, bound_.y0_, splitx_, splity_),
+                                                                 depth_ + 1, max_elems_),
+                    /* NE */
+                    QuadTreeNode<CoordinateT, ElementT>(BoundingBox(splitx_, bound_.y0_, bound_.x1_, splity_),
+                                                        depth_ + 1, max_elems_),
+                    /* SW */
+                    QuadTreeNode<CoordinateT, ElementT>(BoundingBox(bound_.x0_, splity_, splitx_, bound_.y1_),
+                                                        depth_ + 1, max_elems_),
+                    /* SE */
+                    QuadTreeNode<CoordinateT, ElementT>(BoundingBox(splitx_, splity_, bound_.x1_, bound_.y1_),
+                                                        depth_ + 1, max_elems_),
             });
             // Move all elements to where they belong.
             auto it = elems_.begin();
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 09d6d04b8f..de31415156 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -387,13 +387,12 @@ bool Arch::lookup_cell_delay(int type_idx, IdString from_port, IdString to_port,
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
-    int to_pin_idx = db_binary_search(
-            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, to_port.index);
+    int to_pin_idx = db_binary_search(ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, to_port.index);
     if (to_pin_idx == -1)
         return false;
     const auto &tp = ct.pins[to_pin_idx];
-    int arc_idx = db_binary_search(
-            tp.comb_arcs, [](const CellPinCombArcPOD &arc) { return arc.input; }, from_port.index);
+    int arc_idx =
+            db_binary_search(tp.comb_arcs, [](const CellPinCombArcPOD &arc) { return arc.input; }, from_port.index);
     if (arc_idx == -1)
         return false;
     delay = DelayQuad(tp.comb_arcs[arc_idx].delay.fast_min, tp.comb_arcs[arc_idx].delay.slow_max);
@@ -404,8 +403,7 @@ const RelSlice<CellPinRegArcPOD> *Arch::lookup_cell_seq_timings(int type_idx, Id
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
-    int pin_idx = db_binary_search(
-            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
+    int pin_idx = db_binary_search(ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
     if (pin_idx == -1)
         return nullptr;
     return &ct.pins[pin_idx].reg_arcs;
@@ -416,8 +414,7 @@ TimingPortClass Arch::lookup_port_tmg_type(int type_idx, IdString port, PortType
 
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
-    int pin_idx = db_binary_search(
-            ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
+    int pin_idx = db_binary_search(ct.pins, [](const CellPinTimingPOD &pd) { return pd.pin; }, port.index);
     if (pin_idx == -1)
         return (dir == PORT_OUT) ? TMG_IGNORE : TMG_COMB_INPUT;
     auto &pin = ct.pins[pin_idx];
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 548d6764d2..80765da356 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -178,7 +178,7 @@ struct TileWireIterator
     int cursor;
 
     TileWireIterator(const ChipInfoPOD *chip, WireId base, int node_shape, int cursor)
-            : chip(chip), base(base), node_shape(node_shape), cursor(cursor){};
+            : chip(chip), base(base), node_shape(node_shape), cursor(cursor) {};
 
     void operator++() { cursor++; }
     bool operator!=(const TileWireIterator &other) const { return cursor != other.cursor; }
@@ -210,7 +210,7 @@ struct TileWireRange
     };
 
     // is not nodal
-    explicit TileWireRange(WireId w) : b(nullptr, w, -1, 0), e(nullptr, w, -1, 1){};
+    explicit TileWireRange(WireId w) : b(nullptr, w, -1, 0), e(nullptr, w, -1, 1) {};
 
     TileWireIterator b, e;
     TileWireIterator begin() const { return b; }
@@ -223,7 +223,7 @@ struct WireIterator
     int cursor_tile = 0;
     int cursor_index = -1;
 
-    WireIterator(const ChipInfoPOD *chip, int tile, int index) : chip(chip), cursor_tile(tile), cursor_index(index){};
+    WireIterator(const ChipInfoPOD *chip, int tile, int index) : chip(chip), cursor_tile(tile), cursor_index(index) {};
 
     WireIterator operator++()
     {
@@ -287,7 +287,7 @@ template <RelSlice<int32_t> TileWireDataPOD::*ptr> struct UpdownhillPipIterator
     int cursor = -1;
 
     UpdownhillPipIterator(const ChipInfoPOD *chip, TileWireIterator twi, TileWireIterator twi_end, int cursor)
-            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor){};
+            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor) {};
 
     void operator++()
     {
@@ -339,7 +339,7 @@ struct BelPinIterator
     int cursor = -1;
 
     BelPinIterator(const ChipInfoPOD *chip, TileWireIterator twi, TileWireIterator twi_end, int cursor)
-            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor){};
+            : chip(chip), twi(twi), twi_end(twi_end), cursor(cursor) {};
 
     void operator++()
     {
@@ -418,7 +418,7 @@ struct Arch : BaseArch<ArchRanges>
 {
     ArchArgs args;
     Arch(ArchArgs args);
-    ~Arch(){};
+    ~Arch() {};
 
     void load_chipdb(const std::string &path);
     void set_speed_grade(const std::string &speed);
diff --git a/himbaechel/archdefs.h b/himbaechel/archdefs.h
index 14c4b11fdc..d4b8d62155 100644
--- a/himbaechel/archdefs.h
+++ b/himbaechel/archdefs.h
@@ -39,7 +39,7 @@ struct BelId
     int32_t index = -1;
 
     BelId() = default;
-    BelId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    BelId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
@@ -56,7 +56,7 @@ struct WireId
     int32_t index = -1;
 
     WireId() = default;
-    WireId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    WireId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
@@ -74,7 +74,7 @@ struct PipId
     int32_t index = -1;
 
     PipId() = default;
-    PipId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    PipId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index 21275cfb29..e795e4d5df 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -106,17 +106,17 @@ struct HimbaechelAPI
     virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
                                      std::vector<std::pair<CellInfo *, BelId>> &placement) const;
     // --- Flow hooks ---
-    virtual void pack(){}; // replaces the pack function
+    virtual void pack() {}; // replaces the pack function
     // Called before and after main placement and routing
-    virtual void prePlace(){};
-    virtual void postPlace(){};
-    virtual void preRoute(){};
-    virtual void postRoute(){};
+    virtual void prePlace() {};
+    virtual void postPlace() {};
+    virtual void preRoute() {};
+    virtual void postRoute() {};
 
     // For custom placer configuration
-    virtual void configurePlacerHeap(PlacerHeapCfg &cfg){};
+    virtual void configurePlacerHeap(PlacerHeapCfg &cfg) {};
 
-    virtual ~HimbaechelAPI(){};
+    virtual ~HimbaechelAPI() {};
 };
 
 struct HimbaechelArch
@@ -126,7 +126,7 @@ struct HimbaechelArch
 
     std::string name;
     HimbaechelArch(const std::string &name);
-    ~HimbaechelArch(){};
+    ~HimbaechelArch() {};
     virtual bool match_device(const std::string &device) = 0;
     virtual std::unique_ptr<HimbaechelAPI> create(const std::string &device,
                                                   const dict<std::string, std::string> &args) = 0;
diff --git a/himbaechel/himbaechel_helpers.h b/himbaechel/himbaechel_helpers.h
index 369f41dcf4..d622a41ced 100644
--- a/himbaechel/himbaechel_helpers.h
+++ b/himbaechel/himbaechel_helpers.h
@@ -36,10 +36,10 @@ himbaechel_helpers provides some features for building up arches using the himb
 // Used to configure various generic pack functions
 struct CellTypePort
 {
-    CellTypePort() : cell_type(), port(){};
-    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port){};
+    CellTypePort() : cell_type(), port() {};
+    CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port) {};
     explicit CellTypePort(const PortRef &net_port)
-            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port){};
+            : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port) {};
     inline bool operator==(const CellTypePort &other) const
     {
         return cell_type == other.cell_type && port == other.port;
@@ -54,7 +54,7 @@ struct CellTypePort
 
 struct HimbaechelHelpers
 {
-    HimbaechelHelpers(){};
+    HimbaechelHelpers() {};
     Context *ctx;
     void init(Context *ctx) { this->ctx = ctx; }
     // Common packing functions
diff --git a/himbaechel/main.cc b/himbaechel/main.cc
index dccad722f9..8e25f114fe 100644
--- a/himbaechel/main.cc
+++ b/himbaechel/main.cc
@@ -31,7 +31,7 @@ class HimbaechelCommandHandler : public CommandHandler
 {
   public:
     HimbaechelCommandHandler(int argc, char **argv);
-    virtual ~HimbaechelCommandHandler(){};
+    virtual ~HimbaechelCommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
     void setupArchContext(Context *ctx) override;
     void customBitstream(Context *ctx) override;
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index 5172d5cf7f..391a8ca441 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -36,7 +36,7 @@ struct ExampleImpl : HimbaechelAPI
 
     static constexpr int K = 4;
 
-    ~ExampleImpl(){};
+    ~ExampleImpl() {};
     void init_database(Arch *arch) override
     {
         init_uarch_constids(arch);
@@ -139,7 +139,7 @@ struct ExampleImpl : HimbaechelAPI
 
 struct ExampleArch : HimbaechelArch
 {
-    ExampleArch() : HimbaechelArch("example"){};
+    ExampleArch() : HimbaechelArch("example") {};
     bool match_device(const std::string &device) override { return device == "EXAMPLE"; }
     std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
     {
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
index 310e1406f2..a933cc19c6 100644
--- a/himbaechel/uarch/gowin/cst.cc
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -20,7 +20,7 @@ struct GowinCstReader
     Context *ctx;
     std::istream &in;
 
-    GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in){};
+    GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in) {};
 
     const PadInfoPOD *pinLookup(const PadInfoPOD *list, const size_t len, const IdString idx)
     {
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index 4e1f8f7125..aa5490a453 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -340,8 +340,7 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(
-                net, [&](PipId pip) { return global_DQCE_pip_filter(pip); }, src);
+        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_DQCE_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -418,8 +417,7 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(
-                net, [&](PipId pip) { return global_DCS_pip_filter(pip); }, src);
+        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_DCS_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -506,8 +504,7 @@ struct GowinGlobalRouter
         WireId src = ctx->getBelPinWire(driver.cell->bel, port);
 
         std::vector<PipId> path;
-        RouteResult route_result = route_direct_net(
-                net, [&](PipId pip) { return global_pip_filter(pip); }, src, &path);
+        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); }, src, &path);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -571,8 +568,7 @@ struct GowinGlobalRouter
         NetInfo *net_before_buf = buf_ci->getPort(id_I);
         NPNR_ASSERT(net_before_buf != nullptr);
 
-        RouteResult route_result = route_direct_net(
-                net, [&](PipId pip) { return global_pip_filter(pip); }, src);
+        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); }, src);
         if (route_result == NOT_ROUTED || route_result == ROUTED_PARTIALLY) {
             log_error("Can't route the %s net. It might be worth removing the BUFG buffer flag.\n", ctx->nameOf(net));
         }
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 968d2ecafb..1199ee45fe 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -21,7 +21,7 @@ namespace {
 struct GowinImpl : HimbaechelAPI
 {
 
-    ~GowinImpl(){};
+    ~GowinImpl() {};
     void init_database(Arch *arch) override;
     void init(Context *ctx) override;
 
@@ -102,7 +102,7 @@ struct GowinImpl : HimbaechelAPI
 
 struct GowinArch : HimbaechelArch
 {
-    GowinArch() : HimbaechelArch("gowin"){};
+    GowinArch() : HimbaechelArch("gowin") {};
 
     bool match_device(const std::string &device) override { return device.size() > 2 && device.substr(0, 2) == "GW"; }
 
diff --git a/ice40/chains.cc b/ice40/chains.cc
index 20edafaac4..f6e236a781 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -270,7 +270,7 @@ class ChainConstrainer
     }
 
   public:
-    ChainConstrainer(Context *ctx) : ctx(ctx){};
+    ChainConstrainer(Context *ctx) : ctx(ctx) {};
     void constrain_chains() { process_carries(); }
 };
 
diff --git a/ice40/main.cc b/ice40/main.cc
index 224b027577..f16ba83d67 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -34,7 +34,7 @@ class Ice40CommandHandler : public CommandHandler
 {
   public:
     Ice40CommandHandler(int argc, char **argv);
-    virtual ~Ice40CommandHandler(){};
+    virtual ~Ice40CommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
     void setupArchContext(Context *ctx) override;
     void validate() override;
diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
index 3a4ed21e95..e5e30ba96d 100644
--- a/machxo2/archdefs.h
+++ b/machxo2/archdefs.h
@@ -55,9 +55,9 @@ NPNR_PACKED_STRUCT(struct LocationPOD { int16_t x, y; });
 struct Location
 {
     int16_t x = -1, y = -1;
-    Location() : x(-1), y(-1){};
-    Location(int16_t x, int16_t y) : x(x), y(y){};
-    Location(const LocationPOD &pod) : x(pod.x), y(pod.y){};
+    Location() : x(-1), y(-1) {};
+    Location(int16_t x, int16_t y) : x(x), y(y) {};
+    Location(const LocationPOD &pod) : x(pod.x), y(pod.y) {};
 
     bool operator==(const Location &other) const { return x == other.x && y == other.y; }
     bool operator!=(const Location &other) const { return x != other.x || y != other.y; }
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index 6ad03541f0..c4b016c1ad 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -52,7 +52,7 @@ void config_empty_lcmxo3_9400(ChipConfig &cc);
 namespace {
 struct MachXO2Bitgen
 {
-    explicit MachXO2Bitgen(Context *ctx) : ctx(ctx){};
+    explicit MachXO2Bitgen(Context *ctx) : ctx(ctx) {};
     Context *ctx;
     ChipConfig cc;
     // Convert an absolute wire name to a relative Trellis one
diff --git a/machxo2/globals.cc b/machxo2/globals.cc
index bef4628d82..cabc9d5898 100644
--- a/machxo2/globals.cc
+++ b/machxo2/globals.cc
@@ -30,7 +30,7 @@ struct MachxoGlobalRouter
 {
     Context *ctx;
 
-    MachxoGlobalRouter(Context *ctx) : ctx(ctx){};
+    MachxoGlobalRouter(Context *ctx) : ctx(ctx) {};
 
     // When routing globals; we allow global->local for some tricky cases but never local->local
     bool global_pip_filter(PipId pip) const
diff --git a/machxo2/main.cc b/machxo2/main.cc
index ff72ace372..54a226da0b 100644
--- a/machxo2/main.cc
+++ b/machxo2/main.cc
@@ -33,9 +33,9 @@ class MachXO2CommandHandler : public CommandHandler
 {
   public:
     MachXO2CommandHandler(int argc, char **argv);
-    virtual ~MachXO2CommandHandler(){};
+    virtual ~MachXO2CommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customAfterLoad(Context *ctx) override;
     void customBitstream(Context *ctx) override;
 
diff --git a/machxo2/pack.cc b/machxo2/pack.cc
index 51c0dae1df..62f72ecbf6 100644
--- a/machxo2/pack.cc
+++ b/machxo2/pack.cc
@@ -38,7 +38,7 @@ static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
 class MachXO2Packer
 {
   public:
-    MachXO2Packer(Context *ctx) : ctx(ctx){};
+    MachXO2Packer(Context *ctx) : ctx(ctx) {};
 
   private:
     // Process the contents of packed_cells and new_cells
diff --git a/mistral/arch.h b/mistral/arch.h
index bc950566a8..f2de793d4e 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -133,7 +133,7 @@ struct UpDownhillPipIterator
     bool is_uphill;
 
     UpDownhillPipIterator(WireVecIterator base, WireId other_wire, bool is_uphill)
-            : base(base), other_wire(other_wire), is_uphill(is_uphill){};
+            : base(base), other_wire(other_wire), is_uphill(is_uphill) {};
 
     bool operator!=(const UpDownhillPipIterator &other) { return base != other.base; }
     UpDownhillPipIterator operator++()
@@ -155,7 +155,7 @@ struct UpDownhillPipRange
     UpDownhillPipIterator b, e;
 
     UpDownhillPipRange(const std::vector<WireId> &v, WireId other_wire, bool is_uphill)
-            : b(v.begin(), other_wire, is_uphill), e(v.end(), other_wire, is_uphill){};
+            : b(v.begin(), other_wire, is_uphill), e(v.end(), other_wire, is_uphill) {};
 
     UpDownhillPipIterator begin() const { return b; }
     UpDownhillPipIterator end() const { return e; }
@@ -170,7 +170,7 @@ struct AllPipIterator
     int uphill_idx;
 
     AllPipIterator(WireMapIterator base, WireMapIterator end, int uphill_idx)
-            : base(base), end(end), uphill_idx(uphill_idx){};
+            : base(base), end(end), uphill_idx(uphill_idx) {};
 
     bool operator!=(const AllPipIterator &other) { return base != other.base || uphill_idx != other.uphill_idx; }
     AllPipIterator operator++()
@@ -212,12 +212,12 @@ struct AllPipRange
 // This transforms a map to a range of keys, used as the wire iterator
 template <typename T> struct key_range
 {
-    key_range(const T &t) : b(t.begin()), e(t.end()){};
+    key_range(const T &t) : b(t.begin()), e(t.end()) {};
     typename T::const_iterator b, e;
 
     struct xformed_iterator : public T::const_iterator
     {
-        explicit xformed_iterator(typename T::const_iterator base) : T::const_iterator(base){};
+        explicit xformed_iterator(typename T::const_iterator base) : T::const_iterator(base) {};
         typename T::key_type operator*() { return this->T::const_iterator::operator*().first; }
     };
 
diff --git a/mistral/archdefs.h b/mistral/archdefs.h
index f4040398ad..b42f0e95e8 100644
--- a/mistral/archdefs.h
+++ b/mistral/archdefs.h
@@ -93,7 +93,7 @@ static constexpr auto invalid_rnode = std::numeric_limits<CycloneV::rnode_t>::ma
 struct WireId
 {
     WireId() = default;
-    explicit WireId(CycloneV::rnode_t node) : node(node){};
+    explicit WireId(CycloneV::rnode_t node) : node(node) {};
     CycloneV::rnode_t node = invalid_rnode;
 
     // Wires created by nextpnr have rnode type >= 128
@@ -112,7 +112,7 @@ struct WireId
 struct PipId
 {
     PipId() = default;
-    PipId(CycloneV::rnode_t src, CycloneV::rnode_t dst) : src(src), dst(dst){};
+    PipId(CycloneV::rnode_t src, CycloneV::rnode_t dst) : src(src), dst(dst) {};
     CycloneV::rnode_t src = invalid_rnode, dst = invalid_rnode;
 
     bool operator==(const PipId &other) const { return src == other.src && dst == other.dst; }
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index e326881071..b46a9f6b38 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -26,7 +26,7 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace {
 struct MistralBitgen
 {
-    MistralBitgen(Context *ctx) : ctx(ctx), cv(ctx->cyclonev){};
+    MistralBitgen(Context *ctx) : ctx(ctx), cv(ctx->cyclonev) {};
     Context *ctx;
     CycloneV *cv;
 
diff --git a/mistral/globals.cc b/mistral/globals.cc
index cb00b635ea..0d971335b2 100644
--- a/mistral/globals.cc
+++ b/mistral/globals.cc
@@ -66,7 +66,7 @@ struct MistralGlobalRouter
 {
     Context *ctx;
 
-    MistralGlobalRouter(Context *ctx) : ctx(ctx){};
+    MistralGlobalRouter(Context *ctx) : ctx(ctx) {};
 
     // When routing globals; we allow global->local for some tricky cases but never local->local
     bool global_pip_filter(PipId pip) const
diff --git a/mistral/main.cc b/mistral/main.cc
index 34bf759ee5..a2df7fd903 100644
--- a/mistral/main.cc
+++ b/mistral/main.cc
@@ -32,9 +32,9 @@ class MistralCommandHandler : public CommandHandler
 {
   public:
     MistralCommandHandler(int argc, char **argv);
-    virtual ~MistralCommandHandler(){};
+    virtual ~MistralCommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customBitstream(Context *ctx) override;
     void customAfterLoad(Context *ctx) override;
 
diff --git a/mistral/pack.cc b/mistral/pack.cc
index a298c5d6a4..5dae4034c0 100644
--- a/mistral/pack.cc
+++ b/mistral/pack.cc
@@ -26,7 +26,7 @@ NEXTPNR_NAMESPACE_BEGIN
 namespace {
 struct MistralPacker
 {
-    MistralPacker(Context *ctx) : ctx(ctx){};
+    MistralPacker(Context *ctx) : ctx(ctx) {};
     Context *ctx;
 
     NetInfo *gnd_net, *vcc_net;
diff --git a/mistral/qsf.cc b/mistral/qsf.cc
index 88f51b1bb0..ccf9a5ec02 100644
--- a/mistral/qsf.cc
+++ b/mistral/qsf.cc
@@ -78,7 +78,7 @@ struct QsfParser
     int lineno = 0;
     Context *ctx;
 
-    QsfParser(const std::string &buf, Context *ctx) : buf(buf), ctx(ctx){};
+    QsfParser(const std::string &buf, Context *ctx) : buf(buf), ctx(ctx) {};
 
     inline bool eof() const { return pos == int(buf.size()); }
 
diff --git a/nexus/archdefs.h b/nexus/archdefs.h
index f12206f031..4d09110594 100644
--- a/nexus/archdefs.h
+++ b/nexus/archdefs.h
@@ -52,7 +52,7 @@ struct BelId
     int32_t index = -1;
 
     BelId() = default;
-    inline BelId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    inline BelId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
@@ -71,7 +71,7 @@ struct WireId
     int32_t index = -1;
 
     WireId() = default;
-    inline WireId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    inline WireId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
@@ -89,7 +89,7 @@ struct PipId
     int32_t index = -1;
 
     PipId() = default;
-    inline PipId(int32_t tile, int32_t index) : tile(tile), index(index){};
+    inline PipId(int32_t tile, int32_t index) : tile(tile), index(index) {};
 
     bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
     bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
diff --git a/nexus/global.cc b/nexus/global.cc
index ec6f66a280..9b5fd9fd67 100644
--- a/nexus/global.cc
+++ b/nexus/global.cc
@@ -42,7 +42,7 @@ struct NexusGlobalRouter
 {
     Context *ctx;
 
-    NexusGlobalRouter(Context *ctx) : ctx(ctx){};
+    NexusGlobalRouter(Context *ctx) : ctx(ctx) {};
 
     // When routing globals; we allow global->local for some tricky cases but never local->local
     bool global_pip_filter(PipId pip) const
diff --git a/nexus/main.cc b/nexus/main.cc
index cfa06b745b..208b25d783 100644
--- a/nexus/main.cc
+++ b/nexus/main.cc
@@ -32,9 +32,9 @@ class NexusCommandHandler : public CommandHandler
 {
   public:
     NexusCommandHandler(int argc, char **argv);
-    virtual ~NexusCommandHandler(){};
+    virtual ~NexusCommandHandler() {};
     std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
-    void setupArchContext(Context *ctx) override{};
+    void setupArchContext(Context *ctx) override {};
     void customBitstream(Context *ctx) override;
     void customAfterLoad(Context *ctx) override;
 
diff --git a/nexus/pdc.cc b/nexus/pdc.cc
index af62215829..0ec50b7ec1 100644
--- a/nexus/pdc.cc
+++ b/nexus/pdc.cc
@@ -87,8 +87,8 @@ struct TCLEntity
 
 struct TCLValue
 {
-    TCLValue(const std::string &s) : is_string(true), str(s){};
-    TCLValue(const std::vector<TCLEntity> &l) : is_string(false), list(l){};
+    TCLValue(const std::string &s) : is_string(true), str(s) {};
+    TCLValue(const std::vector<TCLEntity> &l) : is_string(false), list(l) {};
 
     bool is_string;
     std::string str;             // simple string value
@@ -102,7 +102,7 @@ struct PDCParser
     int lineno = 1;
     Context *ctx;
 
-    PDCParser(const std::string &buf, Context *ctx) : buf(buf), ctx(ctx){};
+    PDCParser(const std::string &buf, Context *ctx) : buf(buf), ctx(ctx) {};
 
     inline bool eof() const { return pos == int(buf.size()); }
 
diff --git a/nexus/post_place.cc b/nexus/post_place.cc
index 289f82b254..8b615dd741 100644
--- a/nexus/post_place.cc
+++ b/nexus/post_place.cc
@@ -30,7 +30,7 @@ struct NexusPostPlaceOpt
     Context *ctx;
     TimingAnalyser tmg;
 
-    NexusPostPlaceOpt(Context *ctx) : ctx(ctx), tmg(ctx){};
+    NexusPostPlaceOpt(Context *ctx) : ctx(ctx), tmg(ctx) {};
 
     inline bool is_constrained(CellInfo *cell) { return cell->cluster != ClusterId(); }
 

From cc04882b172c76ff4b1216ae97030df6c7c8f457 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 10:04:49 +0200
Subject: [PATCH 685/712] BaseCtx : Fix crash in getNetByAlias()

---
 common/kernel/basectx.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/kernel/basectx.h b/common/kernel/basectx.h
index c8791a2b96..7ff1822829 100644
--- a/common/kernel/basectx.h
+++ b/common/kernel/basectx.h
@@ -213,7 +213,9 @@ struct BaseCtx
 
     NetInfo *getNetByAlias(IdString alias) const
     {
-        return nets.count(alias) ? nets.at(alias).get() : nets.at(net_aliases.at(alias)).get();
+        if(nets.count(alias) > 0) return nets.at(alias).get();
+        if(net_aliases.count(alias) == 0) return nullptr;
+        return nets.at(net_aliases.at(alias)).get();
     }
 
     // Intended to simplify Python API

From ff9ba9e090666edabf3bd2d3d5c44d3a6a23ae8d Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 11:11:21 +0200
Subject: [PATCH 686/712] Himbaechel Xilinx : More warning messages about
 unsupported things in XDC file

---
 himbaechel/uarch/xilinx/xdc.cc | 70 ++++++++++++++++++++++++++--------
 1 file changed, 54 insertions(+), 16 deletions(-)

diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
index e6d76b599a..1a16b9bdc9 100644
--- a/himbaechel/uarch/xilinx/xdc.cc
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -39,9 +39,11 @@ void XilinxImpl::parse_xdc(const std::string &filename)
     std::ifstream in(filename);
     if (!in)
         log_error("failed to open XDC file '%s'\n", filename.c_str());
+    log_info("Parsing XDC file...\n");
     std::string line;
     std::string linebuf;
     int lineno = 0;
+    unsigned num_errors = 0;
 
     auto isempty = [](const std::string &str) {
         return std::all_of(str.begin(), str.end(), [](char c) { return std::isspace(c); });
@@ -109,8 +111,10 @@ void XilinxImpl::parse_xdc(const std::string &filename)
 
     auto get_nets = [&](std::string str) {
         std::vector<NetInfo *> tgt_nets;
-        if (str.empty() || str.front() != '[')
-            log_error("failed to parse target (on line %d)\n", lineno);
+        if (str.empty())
+            return tgt_nets;
+        if (str.front() != '[' || str.back() != ']')
+            log_error("failed to parse target '%s' (on line %d)\n", str.c_str(), lineno);
         str = str.substr(1, str.size() - 2);
         auto split = split_to_args(str, false);
         if (split.size() < 1)
@@ -141,12 +145,18 @@ void XilinxImpl::parse_xdc(const std::string &filename)
         std::string &cmd = arguments.front();
         if (cmd == "set_property") {
             std::vector<std::pair<std::string, std::string>> arg_pairs;
-            if (arguments.size() != 4)
-                log_error("expected four arguments to 'set_property' (on line %d)\n", lineno);
+            if (arguments.size() != 4) {
+                log_nonfatal_error("expected at four arguments to 'set_property' (on line %d)\n", lineno);
+                num_errors++;
+                goto nextline;
+            }
             else if (arguments.at(1) == "-dict") {
                 std::vector<std::string> dict_args = split_to_args(strip_quotes(arguments.at(2)), false);
-                if ((dict_args.size() % 2) != 0)
-                    log_error("expected an even number of argument for dictionary (on line %d)\n", lineno);
+                if ((dict_args.size() % 2) != 0) {
+                    log_nonfatal_error("expected an even number of argument for dictionary (on line %d)\n", lineno);
+                    num_errors++;
+                    goto nextline;
+                }
                 arg_pairs.reserve(dict_args.size() / 2);
                 for (int cursor = 0; cursor + 1 < int(dict_args.size()); cursor += 2) {
                     arg_pairs.emplace_back(std::move(dict_args.at(cursor)), std::move(dict_args.at(cursor + 1)));
@@ -154,8 +164,11 @@ void XilinxImpl::parse_xdc(const std::string &filename)
             } else {
                 arg_pairs.emplace_back(std::move(arguments.at(1)), std::move(arguments.at(2)));
             }
-            if (arg_pairs.size() == 1 && arg_pairs.front().first == "INTERNAL_VREF") // get_iobanks not supported
+            // Warning : ug835 has lowercase example, so probably supporting lowercase too is needed
+            if (arg_pairs.size() == 1 && arg_pairs.front().first == "INTERNAL_VREF") { // get_iobanks not supported
+                log_warning("INTERNAL_VREF isn't supported, ignoring (on line %d)\n", lineno);
                 continue;
+            }
             if (arguments.at(3).size() > 2 && arguments.at(3) == "[current_design]") {
                 log_warning("[current_design] isn't supported, ignoring (on line %d)\n", lineno);
                 continue;
@@ -170,32 +183,57 @@ void XilinxImpl::parse_xdc(const std::string &filename)
             int cursor = 1;
             for (cursor = 1; cursor < int(arguments.size()); cursor++) {
                 std::string opt = arguments.at(cursor);
-                if (opt == "-add")
-                    ;
-                else if (opt == "-name" || opt == "-waveform")
+                if (opt == "-add") {
+                    log_warning("ignoring unsupported XDC option '%s' (on line %d)\n", opt.c_str(), lineno);
+                }
+                else if (opt == "-name" || opt == "-waveform") {
+                    log_warning("ignoring unsupported XDC option '%s' (on line %d)\n", opt.c_str(), lineno);
                     cursor++;
+                }
                 else if (opt == "-period") {
                     cursor++;
                     period = std::stod(arguments.at(cursor));
                     got_period = true;
-                } else
+                }
+                else
                     break;
             }
-            if (!got_period)
-                log_error("found create_clock without period (on line %d)", lineno);
+            if (!got_period) {
+                log_nonfatal_error("found create_clock without period (on line %d)\n", lineno);
+                num_errors++;
+                goto nextline;
+            }
+            if (cursor >= int(arguments.size())) {
+                log_warning("found create_clock without designated nets (on line %d)\n", lineno);
+                goto nextline;
+            }
             std::vector<NetInfo *> dest = get_nets(arguments.at(cursor));
             for (auto n : dest) {
+                if (ctx->debug)
+                    log_info("applying clock period constraint on net '%s' (on line %d)\n", n->name.c_str(ctx), lineno);
+                if (n->clkconstr.get() != nullptr) {
+                    log_nonfatal_error("found multiple clock constraints on net '%s' (on line %d)\n", n->name.c_str(ctx), lineno);
+                    num_errors++;
+                }
                 n->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint);
                 n->clkconstr->period = DelayPair(ctx->getDelayFromNS(period));
                 n->clkconstr->high = DelayPair(ctx->getDelayFromNS(period / 2));
                 n->clkconstr->low = DelayPair(ctx->getDelayFromNS(period / 2));
             }
         } else {
-            log_info("ignoring unsupported XDC command '%s' (on line %d)\n", cmd.c_str(), lineno);
+            log_warning("ignoring unsupported XDC command '%s' (on line %d)\n", cmd.c_str(), lineno);
         }
+
+        nextline:
+        ;  // Phony statement to have something legal after the label
+    }
+    if (!isempty(linebuf)) {
+        log_nonfatal_error("unexpected end of XDC file\n");
+        num_errors++;
+    }
+    if (num_errors > 0) {
+        log_error("Stopping the program after %u errors found in XDC file\n", num_errors);
     }
-    if (!isempty(linebuf))
-        log_error("unexpected end of XDC file\n");
 }
 
 NEXTPNR_NAMESPACE_END

From a9cc7f453df2129d8e2b1a24b1966b22552261f4 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 11:19:03 +0200
Subject: [PATCH 687/712] Himbaechel Xilinx : Support multiple nets per command

---
 himbaechel/uarch/xilinx/xdc.cc | 40 ++++++++++++++++++++++++++--------
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
index 1a16b9bdc9..eaa2c513ce 100644
--- a/himbaechel/uarch/xilinx/xdc.cc
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -143,10 +143,11 @@ void XilinxImpl::parse_xdc(const std::string &filename)
         if (arguments.empty())
             continue;
         std::string &cmd = arguments.front();
+
         if (cmd == "set_property") {
             std::vector<std::pair<std::string, std::string>> arg_pairs;
-            if (arguments.size() != 4) {
-                log_nonfatal_error("expected at four arguments to 'set_property' (on line %d)\n", lineno);
+            if (arguments.size() < 4) {
+                log_nonfatal_error("expected at least four arguments to 'set_property' (on line %d)\n", lineno);
                 num_errors++;
                 goto nextline;
             }
@@ -173,10 +174,26 @@ void XilinxImpl::parse_xdc(const std::string &filename)
                 log_warning("[current_design] isn't supported, ignoring (on line %d)\n", lineno);
                 continue;
             }
-            std::vector<CellInfo *> dest = get_cells(arguments.at(3));
-            for (auto c : dest)
-                for (const auto &pair : arg_pairs)
-                    c->attrs[ctx->id(pair.first)] = std::string(pair.second);
+            // All remaining arguments are supposed to designate cells
+            std::vector<CellInfo *> dest;
+            for (int cursor = 3; cursor < int(arguments.size()); cursor++) {
+                std::vector<CellInfo *> dest_loc = get_cells(arguments.at(cursor));
+                if (dest_loc.empty())
+                    log_warning("found set_property with no cells matching '%s' (on line %d)\n", arguments.at(cursor).c_str(), lineno);
+                dest.insert(dest.end(), dest_loc.begin(), dest_loc.end());
+            }
+            for (auto c : dest) {
+                for (const auto &pair : arg_pairs) {
+                    IdString id_prop = ctx->id(pair.first);
+                    if (ctx->debug)
+                        log_info("applying property '%s' = '%s' to cell '%s' (on line %d)\n", pair.first.c_str(), pair.second.c_str(), c->name.c_str(ctx), lineno);
+                    if(c->attrs.find(id_prop) != c->attrs.end()) {
+                        log_nonfatal_error("found multiple properties '%s' for cell '%s' (on line %d)\n", pair.first.c_str(), c->name.c_str(ctx), lineno);
+                        num_errors++;
+                    }
+                    c->attrs[id_prop] = std::string(pair.second);
+                }
+            }
         } else if (cmd == "create_clock") {
             double period = 0;
             bool got_period = false;
@@ -203,11 +220,16 @@ void XilinxImpl::parse_xdc(const std::string &filename)
                 num_errors++;
                 goto nextline;
             }
-            if (cursor >= int(arguments.size())) {
+            // All remaining arguments are supposed to designate ports/nets
+            std::vector<NetInfo *> dest;
+            if (cursor >= int(arguments.size()))
                 log_warning("found create_clock without designated nets (on line %d)\n", lineno);
-                goto nextline;
+            for ( ; cursor < (int)arguments.size(); cursor++) {
+                std::vector<NetInfo *> dest_loc = get_nets(arguments.at(cursor));
+                if (dest_loc.empty())
+                    log_warning("found create_clock with no nets matching '%s' (on line %d)\n", arguments.at(cursor).c_str(), lineno);
+                dest.insert(dest.end(), dest_loc.begin(), dest_loc.end());
             }
-            std::vector<NetInfo *> dest = get_nets(arguments.at(cursor));
             for (auto n : dest) {
                 if (ctx->debug)
                     log_info("applying clock period constraint on net '%s' (on line %d)\n", n->name.c_str(ctx), lineno);

From 3d00b97e0a9f8e8eb2bc22a4c3464eef547fc68d Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 11:20:57 +0200
Subject: [PATCH 688/712] Himbaechel Xilinx : Support get_nets with braces
 around net name in XDC commands

---
 himbaechel/uarch/xilinx/xdc.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
index eaa2c513ce..8ae2d1ac7f 100644
--- a/himbaechel/uarch/xilinx/xdc.cc
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -123,7 +123,10 @@ void XilinxImpl::parse_xdc(const std::string &filename)
             log_error("targets other than 'get_ports' or 'get_nets' are not supported (on line %d)\n", lineno);
         if (split.size() < 2)
             log_error("failed to parse target (on line %d)\n", lineno);
-        IdString netname = ctx->id(split.at(1));
+        str = strip_quotes(split.at(1));
+        if (str.empty())
+            return tgt_nets;
+        IdString netname = ctx->id(str);
         NetInfo *maybe_net = ctx->getNetByAlias(netname);
         if (maybe_net != nullptr)
             tgt_nets.push_back(maybe_net);

From 7f33329fe14b19316f716e39aca0b1059ba3cadd Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 11:23:33 +0200
Subject: [PATCH 689/712] Himbaechel Xilinx : XDC commands : Also search nets
 with lowercase for better interoperability with other synthesis tools and RTL
 languages

---
 himbaechel/uarch/xilinx/xdc.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/himbaechel/uarch/xilinx/xdc.cc b/himbaechel/uarch/xilinx/xdc.cc
index 8ae2d1ac7f..b0f41922a0 100644
--- a/himbaechel/uarch/xilinx/xdc.cc
+++ b/himbaechel/uarch/xilinx/xdc.cc
@@ -128,6 +128,14 @@ void XilinxImpl::parse_xdc(const std::string &filename)
             return tgt_nets;
         IdString netname = ctx->id(str);
         NetInfo *maybe_net = ctx->getNetByAlias(netname);
+        if (maybe_net != nullptr) {
+            tgt_nets.push_back(maybe_net);
+            return tgt_nets;
+        }
+        // Also test the lowercase variant, for better interoperability with synthesis tools
+        boost::algorithm::to_lower(str);
+        netname = ctx->id(str);
+        maybe_net = ctx->getNetByAlias(netname);
         if (maybe_net != nullptr)
             tgt_nets.push_back(maybe_net);
         return tgt_nets;

From b3b239289332395d4ea0a687b14faf841a499415 Mon Sep 17 00:00:00 2001
From: Adrien Prost-Boucle <adrien.prost-boucle@univ-grenoble-alpes.fr>
Date: Tue, 1 Oct 2024 14:20:19 +0200
Subject: [PATCH 690/712] clang-format on basectx.h

---
 common/kernel/basectx.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/common/kernel/basectx.h b/common/kernel/basectx.h
index 7ff1822829..3f021e82cc 100644
--- a/common/kernel/basectx.h
+++ b/common/kernel/basectx.h
@@ -213,8 +213,10 @@ struct BaseCtx
 
     NetInfo *getNetByAlias(IdString alias) const
     {
-        if(nets.count(alias) > 0) return nets.at(alias).get();
-        if(net_aliases.count(alias) == 0) return nullptr;
+        if (nets.count(alias) > 0)
+            return nets.at(alias).get();
+        if (net_aliases.count(alias) == 0)
+            return nullptr;
         return nets.at(net_aliases.at(alias)).get();
     }
 

From 268b32c341587aba99b4144e7793b58890004c89 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 22 May 2024 22:56:51 +0100
Subject: [PATCH 691/712] router2: additional heatmap data

---
 common/route/router2.cc                 | 59 ++++++++++++++++++++++---
 python/plot_congestion_by_coordinate.py | 27 +++++++++++
 python/plot_congestion_by_wiretype.py   | 56 +++++++++++++++++++++++
 3 files changed, 135 insertions(+), 7 deletions(-)
 create mode 100644 python/plot_congestion_by_coordinate.py
 create mode 100644 python/plot_congestion_by_wiretype.py

diff --git a/common/route/router2.cc b/common/route/router2.cc
index a19046a67d..5ae091eea4 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -1159,7 +1159,7 @@ struct Router2
         return success;
     }
 
-    void write_wiretype_heatmap(std::ostream &out)
+    void write_congestion_by_wiretype_heatmap(std::ostream &out)
     {
         dict<IdString, std::vector<int>> cong_by_type;
         size_t max_cong = 0;
@@ -1185,6 +1185,33 @@ struct Router2
         }
     }
 
+    void write_utilisation_by_wiretype_heatmap(std::ostream &out)
+    {
+        dict<IdString, int> util_by_type;
+        for (auto &wd : flat_wires) {
+            IdString type = ctx->getWireType(wd.w);
+            if (wd.curr_cong > 0)
+                util_by_type[type] += wd.curr_cong;
+        }
+        // Write csv
+        for (auto &u : util_by_type)
+            out << u.first.c_str(ctx) << "," << u.second << std::endl;
+    }
+
+    void write_congestion_by_coordinate_heatmap(std::ostream &out)
+    {
+        auto util_by_coord = std::vector<std::vector<int>>(ctx->getGridDimX() + 1, std::vector<int>(ctx->getGridDimY() + 1, 0));
+        for (auto &wd : flat_wires)
+            if (wd.curr_cong > 1)
+                util_by_coord[wd.x][wd.y] += wd.curr_cong;
+        // Write csv
+        for (auto &x : util_by_coord) {
+            for (auto y : x)
+                out << y << ",";
+            out << std::endl;
+        }
+    }
+
     int mid_x = 0, mid_y = 0;
 
     void partition_nets()
@@ -1444,12 +1471,30 @@ struct Router2
             update_congestion();
 
             if (!cfg.heatmap.empty()) {
-                std::string filename(cfg.heatmap + "_" + std::to_string(iter) + ".csv");
-                std::ofstream cong_map(filename);
-                if (!cong_map)
-                    log_error("Failed to open wiretype heatmap %s for writing.\n", filename.c_str());
-                write_wiretype_heatmap(cong_map);
-                log_info("        wrote wiretype heatmap to %s.\n", filename.c_str());
+                {
+                    std::string filename(cfg.heatmap + "_congestion_by_wiretype_" + std::to_string(iter) + ".csv");
+                    std::ofstream cong_map(filename);
+                    if (!cong_map)
+                        log_error("Failed to open congestion-by-wiretype heatmap %s for writing.\n", filename.c_str());
+                    write_congestion_by_wiretype_heatmap(cong_map);
+                    log_info("        wrote congestion-by-wiretype heatmap to %s.\n", filename.c_str());
+                }
+                {
+                    std::string filename(cfg.heatmap + "_utilisation_by_wiretype_" + std::to_string(iter) + ".csv");
+                    std::ofstream cong_map(filename);
+                    if (!cong_map)
+                        log_error("Failed to open utilisation-by-wiretype heatmap %s for writing.\n", filename.c_str());
+                    write_utilisation_by_wiretype_heatmap(cong_map);
+                    log_info("        wrote utilisation-by-wiretype heatmap to %s.\n", filename.c_str());
+                }
+                {
+                    std::string filename(cfg.heatmap + "_congestion_by_coordinate_" + std::to_string(iter) + ".csv");
+                    std::ofstream cong_map(filename);
+                    if (!cong_map)
+                        log_error("Failed to open congestion-by-coordinate heatmap %s for writing.\n", filename.c_str());
+                    write_congestion_by_coordinate_heatmap(cong_map);
+                    log_info("        wrote congestion-by-coordinate heatmap to %s.\n", filename.c_str());
+                }
             }
             int tmgfail = 0;
             if (timing_driven)
diff --git a/python/plot_congestion_by_coordinate.py b/python/plot_congestion_by_coordinate.py
new file mode 100644
index 0000000000..a9e7833d49
--- /dev/null
+++ b/python/plot_congestion_by_coordinate.py
@@ -0,0 +1,27 @@
+import csv
+import sys
+
+import matplotlib.pyplot as plt
+
+data = []
+
+file = 1
+try:
+    while True:
+        print("{}/heatmap_congestion_by_coordinate_{}.csv".format(sys.argv[1], file))
+        with open("{}/heatmap_congestion_by_coordinate_{}.csv".format(sys.argv[1], file)) as f:
+            file_data = []
+            reader = csv.reader(f, delimiter=',')
+            for row in reader:
+                file_data.append([float(x) for x in row if x != ''])
+            data.append(file_data)
+        file += 1
+except FileNotFoundError:
+    pass
+
+for i, file_data in enumerate(data):
+    plt.imshow(file_data, cmap="gray", aspect="equal")
+    plt.title("heatmap for iteration {}".format(i+1))
+    plt.tight_layout()
+    plt.savefig("{}/heatmap_congestion_by_coordinate_{:03}.png".format(sys.argv[1], i), dpi=300)
+    plt.clf()
diff --git a/python/plot_congestion_by_wiretype.py b/python/plot_congestion_by_wiretype.py
new file mode 100644
index 0000000000..6f44a1ab47
--- /dev/null
+++ b/python/plot_congestion_by_wiretype.py
@@ -0,0 +1,56 @@
+import csv
+import sys
+
+import matplotlib.pyplot as plt
+
+data = {}
+max_bars = {}
+
+file = 1
+try:
+    while True:
+        print("{}/heatmap_congestion_by_wiretype_{}.csv".format(sys.argv[1], file))
+        with open("{}/heatmap_congestion_by_wiretype_{}.csv".format(sys.argv[1], file)) as f:
+            reader = csv.reader(f, delimiter=',')
+            for row in [x for x in reader][1:]:
+                key = row[0]
+                values = [float(x) for x in row[1:] if x != '']
+                # Ignore wires without overuse
+                values[0] = 0
+                values[1] = 0
+                if key not in data:
+                    data[key] = []
+                    max_bars[key] = 0
+                data[key].append(values)
+                max_bars[key] = max(max_bars[key], len(values))
+            file += 1
+except FileNotFoundError:
+    pass
+finally:
+    file -= 1
+
+to_remove = []
+for key in data.keys():
+    if sum([sum(values) for values in data[key]]) == 0:
+        # Prune entries that never have any overuse to attempt to reduce visual clutter
+        to_remove.append(key)
+    else:
+        # Pad entries as needed
+        for values in data[key]:
+            while len(values) < max_bars[key]:
+                values.append(0)
+for key in to_remove:
+    del data[key]
+
+COLS = 2
+for i in range(file):
+    plt.suptitle("heatmap for iteration {}".format(i))
+    fig, axs = plt.subplots((len(data.keys())+(COLS-1))//COLS, COLS)
+    for j, key in enumerate(data.keys()):
+        if sum(data[key][i]) > 0:
+            axs[j//COLS, j%COLS].bar([x for x in range(len(data[key][i]))], data[key][i])
+            axs[j//COLS, j%COLS].set_title(key)
+        else:
+            axs[j//COLS, j%COLS].set_axis_off()
+    plt.savefig("{}/heatmap_congestion_by_wiretype_{:03}.png".format(sys.argv[1], i), dpi=300)
+    plt.close()

From 65cf6d8da78851a9a7939ce12a7ca996f2d3fe6e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Thu, 3 Oct 2024 06:36:36 +1000
Subject: [PATCH 692/712] Gowin. Fix the port check for connectivity. (#1376)

* Gowin. Fix the port check for connectivity.

What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks.

And the style edits - they get automatically when I make sure to run
clang-format10.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix the port check for connectivity.

What happens is that it's not enough to check for a network, we also
need to make sure that the network is functional: has src and sinks

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin_utils.h | 14 ++++++++++++++
 himbaechel/uarch/gowin/pack.cc       |  4 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index f9276c10e9..71f60f8c99 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -1,6 +1,7 @@
 #ifndef GOWIN_UTILS_H
 #define GOWIN_UTILS_H
 
+#include "design_utils.h"
 #include "idstringlist.h"
 #include "nextpnr_namespaces.h"
 #include "nextpnr_types.h"
@@ -37,6 +38,19 @@ struct GowinUtils
     BelId get_dcs_bel(IdString spine_name);
     BelId get_dhcen_bel(WireId hclkin_wire, IdString &side);
 
+    // ports
+    inline bool port_used(CellInfo *cell, IdString port_name)
+    {
+        if (!nextpnr_himbaechel::port_used(cell, port_name)) {
+            return false;
+        }
+        NetInfo *ni = cell->ports.at(port_name).net;
+        if (ni->driver.cell == nullptr) {
+            return false;
+        }
+        return ni->users.entries() != 0;
+    }
+
     // BSRAM
     bool has_SP32(void);
     bool need_SP_fix(void);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 78389d7fd7..f774bbc32b 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -454,7 +454,7 @@ struct GowinPacker
         }
 
         // if Q1 is connected then disconnect it too
-        if (port_used(&ci, tx_port)) {
+        if (gwu.port_used(&ci, tx_port)) {
             NPNR_ASSERT(out_iob == net_only_drives(ctx, ci.ports.at(tx_port).net, is_iob, id_OEN, true));
             nets_to_remove.push_back(ci.getPort(tx_port)->name);
             out_iob->disconnectPort(id_OEN);
@@ -3160,7 +3160,7 @@ struct GowinPacker
             // add invertor
             int lut_idx = 0;
             auto add_inv = [&](IdString port, PortType port_type) {
-                if (!port_used(&ci, port)) {
+                if (!gwu.port_used(&ci, port)) {
                     return;
                 }
 

From 75d2ce6a9274c16a3cd9c83179c2ba6c88c843a8 Mon Sep 17 00:00:00 2001
From: myrtle <gatecat@ds0.me>
Date: Wed, 2 Oct 2024 22:36:57 +0200
Subject: [PATCH 693/712] heap: Fix ripup criterea (#1378)

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/place/placer_heap.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc
index b2ae6dbe84..940d1d714d 100644
--- a/common/place/placer_heap.cc
+++ b/common/place/placer_heap.cc
@@ -890,7 +890,7 @@ class HeAPPlacer
             total_iters_noreset++;
             if (total_iters > int(solve_cells.size())) {
                 total_iters = 0;
-                ripup_radius = std::max(std::max(max_x, max_y), ripup_radius * 2);
+                ripup_radius = std::min(std::max(max_x, max_y), ripup_radius * 2);
             }
 
             if (total_iters_noreset > std::max(5000, 8 * int(ctx->cells.size()))) {
@@ -995,7 +995,7 @@ class HeAPPlacer
                             CellInfo *bound = ctx->getBoundBelCell(sz);
                             if (bound != nullptr) {
                                 // Only rip up cells without constraints
-                                if (bound->cluster != ClusterId())
+                                if (bound->cluster != ClusterId() || bound->belStrength > STRENGTH_WEAK)
                                     continue;
                                 ctx->unbindBel(bound->bel);
                             }

From 854549a5ab15889a32af265c8c09f1289d97414d Mon Sep 17 00:00:00 2001
From: myrtle <gatecat@ds0.me>
Date: Fri, 4 Oct 2024 08:07:13 +0200
Subject: [PATCH 694/712] ice40: Fix missing clock pin types (#1380)

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/cells.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/ice40/cells.cc b/ice40/cells.cc
index d304a68f75..419ee434ee 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -521,6 +521,10 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port)
         return port.port == id_CLK;
     if (is_sb_spram(ctx, port.cell) || port.cell->type == id_ICESTORM_SPRAM)
         return port.port == id_CLOCK;
+    if (is_sb_i2c(ctx, port.cell) || is_sb_spi(ctx, port.cell))
+        return port.port == id_SBCLKI;
+    if (is_sb_ledda_ip(ctx, port.cell))
+        return port.port == id_LEDDCLK;
     if (is_sb_io(ctx, port.cell))
         return port.port.in(id_INPUT_CLK, id_OUTPUT_CLK);
     return false;

From 0e5b1348e6619caef48e0696ffc19075e615c907 Mon Sep 17 00:00:00 2001
From: Rowan Goemans <goemansrowan@gmail.com>
Date: Fri, 4 Oct 2024 08:07:55 +0200
Subject: [PATCH 695/712] timing_log: Handle potentially missing net when
 reporting crit path (#1381)

---
 common/kernel/timing_log.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc
index d0dd8986ba..8e6a3f3c0e 100644
--- a/common/kernel/timing_log.cc
+++ b/common/kernel/timing_log.cc
@@ -106,6 +106,10 @@ static void log_crit_paths(const Context *ctx, TimingResult &result)
                 log_info("                         Sink %s.%s\n", segment.to.first.c_str(ctx),
                          segment.to.second.c_str(ctx));
 
+                // CLK_TO_CLK has no net and CLK_SKEW might have a net
+                if (ctx->nets.count(segment.net) == 0) {
+                    continue;
+                }
                 const NetInfo *net = ctx->nets.at(segment.net).get();
 
                 if (ctx->verbose) {

From d27993f0192df545a0796a361e00ad743ce91783 Mon Sep 17 00:00:00 2001
From: Meinhard Kissich <privat@meinhard-kissich.at>
Date: Tue, 8 Oct 2024 15:20:33 +0200
Subject: [PATCH 696/712] Placer: Fix static legalise radius (#1382)

---
 common/place/placer_static.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc
index 9b20af306d..50f6502224 100644
--- a/common/place/placer_static.cc
+++ b/common/place/placer_static.cc
@@ -1245,7 +1245,7 @@ class StaticPlacer
             total_iters_noreset++;
             if (total_iters > int(ccells.size())) {
                 total_iters = 0;
-                ripup_radius = std::max(std::max(width + 1, height + 1), ripup_radius * 2);
+                ripup_radius = std::min(std::max(width + 1, height + 1), ripup_radius * 2);
             }
 
             if (total_iters_noreset > std::max(5000, 8 * int(ctx->cells.size()))) {

From 028be1462a6faece10a39a9e3391cf51832b3cf1 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 9 Oct 2024 15:16:36 +0200
Subject: [PATCH 697/712] apicula: add support for magic sip pins (#1370)

* apicula: add support for magic sip pins

* fix nullptr check

* DDR fix by xiwang

* WIP support for setting the iostd

* add iostd
---
 common/kernel/relptr.h                   |  2 ++
 himbaechel/chipdb.h                      |  1 +
 himbaechel/himbaechel_dbgen/chip.py      |  9 +++++++
 himbaechel/uarch/gowin/cst.cc            | 30 ++++++++++++++++++++++++
 himbaechel/uarch/gowin/gowin.h           | 12 ++++++++++
 himbaechel/uarch/gowin/gowin_arch_gen.py | 21 +++++++++++++++++
 6 files changed, 75 insertions(+)

diff --git a/common/kernel/relptr.h b/common/kernel/relptr.h
index f0f45b7d03..4a98dd682b 100644
--- a/common/kernel/relptr.h
+++ b/common/kernel/relptr.h
@@ -33,6 +33,8 @@ template <typename T> struct RelPtr
 
     const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
 
+    bool is_null() const { return offset == 0; }
+
     const T &operator[](std::size_t index) const { return get()[index]; }
 
     const T &operator*() const { return *(get()); }
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 2ac7f60b42..17430ac4c2 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -138,6 +138,7 @@ NPNR_PACKED_STRUCT(struct PadInfoPOD {
 NPNR_PACKED_STRUCT(struct PackageInfoPOD {
     int32_t name;
     RelSlice<PadInfoPOD> pads;
+    RelPtr<uint8_t> extra_data;
 });
 
 NPNR_PACKED_STRUCT(struct TileInstPOD {
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 19aa8914d6..8650813d93 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -411,6 +411,7 @@ class PackageInfo(BBAStruct):
     strs: StringPool
     name: IdString
     pads: list[int] = field(default_factory=list)
+    extra_data: object = None
 
     def create_pad(self, package_pin: str, tile: str, bel: str, pad_function: str, pad_bank: int, flags: int = 0):
         pad = PadInfo(package_pin = self.strs.id(package_pin), tile = self.strs.id(tile), bel = self.strs.id(bel),
@@ -424,10 +425,18 @@ def serialise_lists(self, context: str, bba: BBAWriter):
         bba.label(f"{context}_pads")
         for i, pad in enumerate(self.pads):
             pad.serialise(f"{context}_pad{i}", bba)
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
 
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
         bba.slice(f"{context}_pads", len(self.pads))
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
 
 class TimingValue(BBAStruct):
     def __init__(self, fast_min=0, fast_max=None, slow_min=None, slow_max=None):
diff --git a/himbaechel/uarch/gowin/cst.cc b/himbaechel/uarch/gowin/cst.cc
index a933cc19c6..5229a4c2a5 100644
--- a/himbaechel/uarch/gowin/cst.cc
+++ b/himbaechel/uarch/gowin/cst.cc
@@ -240,8 +240,38 @@ struct GowinCstReader
     }
 };
 
+
+static void add_sip_constraints(Context *ctx, const Extra_package_data_POD *extra) {
+    for(auto cst : extra->cst) {
+        auto it = ctx->cells.find(IdString(cst.net));
+        if (it == ctx->cells.end()) {
+            log_info("Cell %s not found\n", IdString(cst.net).c_str(ctx));
+            continue;
+        }
+        Loc loc = Loc(cst.col, cst.row, cst.bel);
+        BelId bel = ctx->getBelByLocation(loc);
+        if (bel == BelId()) {
+            log_error("Pin not found.\n");
+        }
+        it->second->setAttr(IdString(ID_BEL), std::string(ctx->nameOfBel(bel)));
+
+        if(cst.iostd > 0) {
+            std::string attr = "&IO_TYPE=";
+            attr += IdString(cst.iostd).c_str(ctx);
+            boost::algorithm::to_upper(attr);
+            it->second->setAttr(ctx->id(attr), 1);
+        }
+    }
+}
+
 bool gowin_apply_constraints(Context *ctx, std::istream &in)
 {
+    // implicit constraints from SiP pins
+    if(!ctx->package_info->extra_data.is_null()) {
+        const Extra_package_data_POD *extra = reinterpret_cast<const Extra_package_data_POD *>(ctx->package_info->extra_data.get());
+        add_sip_constraints(ctx, extra);
+    }
+
     GowinCstReader reader(ctx, in);
     return reader.run();
 }
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 1588b27b91..001c1cfb07 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -130,6 +130,18 @@ NPNR_PACKED_STRUCT(struct Wire_bel_POD {
     int32_t side;
 });
 
+NPNR_PACKED_STRUCT(struct Constraint_POD {
+    int32_t net;
+    int32_t row;
+    int32_t col;
+    int32_t bel;
+    int32_t iostd;
+});
+
+NPNR_PACKED_STRUCT(struct Extra_package_data_POD {
+    RelSlice<Constraint_POD> cst;
+});
+
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     int32_t chip_flags;
     Bottom_io_POD bottom_io;
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 7daed96354..473efa21a9 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -244,6 +244,23 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.slice(f"{context}_dcs_bels", len(self.dcs_bels))
         bba.slice(f"{context}_dhcen_bels", len(self.dhcen_bels))
 
+@dataclass
+class PackageExtraData(BBAStruct):
+    strs: StringPool
+    cst: list
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_constraints")
+        for (net, row, col, bel, iostd) in self.cst:
+            bba.u32(self.strs.id(net).index)
+            bba.u32(row)
+            bba.u32(col)
+            bba.u32(ord(bel[0])-ord('A')+IOBA_Z)
+            bba.u32(self.strs.id(iostd).index if iostd else 0)
+
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.slice(f"{context}_constraints", len(self.cst))
+
 @dataclass
 class PadExtraData(BBAStruct):
     # Which PLL does this pad belong to.
@@ -1206,6 +1223,10 @@ def ioloc_to_tile_bel(ioloc):
             continue
         created_pkgs.add(partno)
         pkg = chip.create_package(partno)
+
+        if variant in db.sip_cst and pkgname in db.sip_cst[variant]:
+            pkg.extra_data = PackageExtraData(chip.strs, db.sip_cst[variant][pkgname])
+
         for pinno, pininfo in db.pinout[variant][pkgname].items():
             io_loc, cfgs = pininfo
             tile, bel = ioloc_to_tile_bel(io_loc)

From 7c459805f63c07c44f22e46fbd08734da2578db8 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 9 Oct 2024 15:21:10 +0200
Subject: [PATCH 698/712] himbaechel: Bump DB version for package extra_data
 addition

Signed-off-by: gatecat <gatecat@ds0.me>
---
 himbaechel/arch.cc                  | 2 +-
 himbaechel/himbaechel_dbgen/chip.py | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index de31415156..4152e7aee3 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -33,7 +33,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static constexpr int database_version = 3;
+static constexpr int database_version = 4;
 
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index 8650813d93..a5ee2b4272 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -831,7 +831,7 @@ def serialise(self, bba: BBAWriter):
 
         bba.label("chip_info")
         bba.u32(0x00ca7ca7) # magic
-        bba.u32(3) # version
+        bba.u32(4) # version
         bba.u32(self.width)
         bba.u32(self.height)
 

From cf42baa43b1ce31e20640eaaa631bc3d3710aad3 Mon Sep 17 00:00:00 2001
From: Meinhard Kissich <privat@meinhard-kissich.at>
Date: Wed, 9 Oct 2024 18:25:02 +0200
Subject: [PATCH 699/712] Fix RNG seed initialization (#1383)

---
 common/kernel/command.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 43eb491af2..9dc54afb0e 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -427,7 +427,7 @@ void script_terminate_handler()
 void CommandHandler::setupContext(Context *ctx)
 {
     if (ctx->settings.find(ctx->id("seed")) != ctx->settings.end())
-        ctx->rngstate = ctx->setting<uint64_t>("seed");
+        ctx->rngseed(ctx->setting<uint64_t>("seed"));
 
     if (vm.count("verbose")) {
         ctx->verbose = true;
@@ -447,7 +447,7 @@ void CommandHandler::setupContext(Context *ctx)
     }
 
     if (vm.count("seed")) {
-        ctx->rngstate = vm["seed"].as<uint64_t>();
+        ctx->rngseed(vm["seed"].as<uint64_t>());
     }
 
     if (vm.count("threads")) {

From f36a6571c1bac94729bbfc33784e3dd814421891 Mon Sep 17 00:00:00 2001
From: myrtle <gatecat@ds0.me>
Date: Tue, 22 Oct 2024 10:35:54 +0200
Subject: [PATCH 700/712] cmake: Use upstream BoostConfig.cmake instead of
 cmake's own (#1387)

Signed-off-by: gatecat <gatecat@ds0.me>
---
 CMakeLists.txt | 2 --
 1 file changed, 2 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 9ae095e075..40707d0ee6 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -55,8 +55,6 @@ else()
     set(BBASM_MODE "string")
 endif()
 
-set(Boost_NO_BOOST_CMAKE ON)
-
 find_package(Threads)
 if (Threads_FOUND)
     find_package(TBB QUIET)

From 9c2d96f86ed56b77c9c325041b67654f26308270 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 22 Oct 2024 20:49:44 +1000
Subject: [PATCH 701/712] Gowin. FFs placement. (#1386)

* Gowin. FFs placement.

* Allow clusters to be created from FFs and LUTs;

* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;

* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;

* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix aux name creation

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Use I3 for pass-trough LUTs

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.cc          | 113 +++++++++++++++++++----
 himbaechel/uarch/gowin/gowin_arch_gen.py |   9 +-
 himbaechel/uarch/gowin/gowin_utils.cc    |   6 ++
 himbaechel/uarch/gowin/gowin_utils.h     |   3 +
 himbaechel/uarch/gowin/pack.cc           |  74 +++++++--------
 5 files changed, 143 insertions(+), 62 deletions(-)

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 1199ee45fe..a09c9ea715 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -71,6 +71,9 @@ struct GowinImpl : HimbaechelAPI
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
 
+    // If there is an unused LUT adjacent to FF, use it
+    void create_passthrough_luts(void);
+
     // Remember HCLK sections that have been reserved to route HCLK signals
     std::set<BelId> routing_reserved_hclk_sections;
 
@@ -531,6 +534,7 @@ void GowinImpl::postPlace()
 
     // adjust cell pin to bel pin mapping for DSP cells (CE, CLK and RESET pins)
     adjust_dsp_pin_mapping();
+    create_passthrough_luts();
 }
 
 void GowinImpl::preRoute() { gowin_route_globals(ctx); }
@@ -590,8 +594,15 @@ bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
     case ID_ALU:
         return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
     case ID_RAM16SDP4:
-        // only slices 4 and 5 are critical for RAM
-        return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
+        return slice_valid(l.x, l.y, 0);
+    case ID_MUX2_LUT5:
+        return slice_valid(l.x, l.y, (l.z - BelZ::MUX20_Z) / 2);
+    case ID_MUX2_LUT6:
+        return slice_valid(l.x, l.y, (l.z - BelZ::MUX21_Z) / 2 + 1);
+    case ID_MUX2_LUT7:
+        return slice_valid(l.x, l.y, 3);
+    case ID_MUX2_LUT8:
+        return slice_valid(l.x, l.y, 7);
     case ID_PADD9:           /* fall-through */
     case ID_PADD18:          /* fall-through */
     case ID_MULT9X9:         /* fall-through */
@@ -725,6 +736,67 @@ void GowinImpl::assign_cell_info()
     }
 }
 
+// If there is an unused LUT next to the DFF, use its inputs for the D input
+void GowinImpl::create_passthrough_luts(void)
+{
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (is_dff(ci)) {
+            Loc loc = ctx->getBelLocation(ci->bel);
+            BelId lut_bel = ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z - 1));
+            CellInfo *lut = ctx->getBoundBelCell(lut_bel);
+            CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z / 2 + BelZ::ALU0_Z)));
+            const CellInfo *ramw = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BelZ::RAMW_Z)));
+
+            if (!(lut || alu || ramw)) {
+                if (ctx->debug) {
+                    log_info("Found an unused LUT:%s, ", ctx->nameOfBel(lut_bel));
+                }
+                // make LUT
+                auto lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_passthrough_lut$"), id_LUT4);
+                CellInfo *lut = lut_cell.get();
+                NetInfo *d_net = ci->getPort(id_D);
+                NPNR_ASSERT(d_net != nullptr);
+
+                if (d_net->name == ctx->id("$PACKER_GND") || d_net->name == ctx->id("$PACKER_VCC")) {
+                    if (ctx->debug) {
+                        log("make a constant %s.\n", d_net->name == ctx->id("$PACKER_VCC") ? "VCC" : "GND");
+                    }
+                    ci->disconnectPort(id_D);
+                    if (d_net->name == ctx->id("$PACKER_GND")) {
+                        lut->setParam(id_INIT, 0x0000);
+                    } else {
+                        lut->setParam(id_INIT, 0xffff);
+                    }
+                } else {
+                    if (ctx->debug) {
+                        log("make a pass-through.\n");
+                    }
+                    IdString lut_input = id_I3;
+                    int lut_init = 0xff00;
+
+                    lut->addInput(lut_input);
+                    lut->cell_bel_pins[lut_input].clear();
+                    lut->cell_bel_pins.at(lut_input).push_back(lut_input);
+                    ci->movePortTo(id_D, lut, lut_input);
+                    lut->setParam(id_INIT, lut_init);
+                }
+                lut->addOutput(id_F);
+                lut->cell_bel_pins[id_F].clear();
+                lut->cell_bel_pins.at(id_F).push_back(id_F);
+                ci->connectPorts(id_D, lut, id_F);
+
+                ctx->bindBel(lut_bel, lut, PlaceStrength::STRENGTH_LOCKED);
+                new_cells.push_back(std::move(lut_cell));
+            }
+        }
+    }
+    for (auto &cell : new_cells) {
+        ctx->cells[cell->name] = std::move(cell);
+    }
+}
+
 // DFFs must be same type or compatible
 inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
 {
@@ -798,22 +870,30 @@ bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
 bool GowinImpl::slice_valid(int x, int y, int z) const
 {
     const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
-    const bool lut_in_4_5 = lut && (z == 4 || z == 5);
     const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
     // There are only 6 ALUs
     const CellInfo *alu = (z < 6) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z))) : nullptr;
-    const CellInfo *ramw =
-            (z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
+    const CellInfo *ramw = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z)));
 
     if (alu && lut) {
         return false;
     }
 
     if (ramw) {
-        if (alu || ff || lut_in_4_5) {
+        // FFs in slices 4 and 5 are not allowed
+        if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, 4 * 2 + 1))) ||
+            ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, 5 * 2 + 1)))) {
             return false;
         }
-        return true;
+        // ALU/LUTs in slices 4, 5, 6, 7 are not allowed
+        for (int i = 4; i < 8; ++i) {
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, i * 2)))) {
+                return false;
+            }
+            if (i < 6 && ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, i + BelZ::ALU0_Z)))) {
+                return false;
+            }
+        }
     }
 
     // check for ALU/LUT in the adjacent cell
@@ -829,18 +909,19 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
         return false;
     }
 
-    // if there is DFF it must be connected to this LUT or ALU
     if (ff) {
+        static std::vector<int> mux_z = {BelZ::MUX20_Z,     BelZ::MUX21_Z,     BelZ::MUX20_Z + 4,  BelZ::MUX23_Z,
+                                         BelZ::MUX20_Z + 8, BelZ::MUX21_Z + 8, BelZ::MUX20_Z + 12, BelZ::MUX27_Z};
         const auto &ff_data = fast_cell_info.at(ff->flat_index);
-        if (lut) {
-            const auto &lut_data = fast_cell_info.at(lut->flat_index);
-            if (ff_data.ff_d != lut_data.lut_f) {
-                return false;
+        const NetInfo *src;
+        // check implcit LUT(ALU) -> FF connection
+        if (lut || alu) {
+            if (lut) {
+                src = fast_cell_info.at(lut->flat_index).lut_f;
+            } else {
+                src = fast_cell_info.at(alu->flat_index).alu_sum;
             }
-        }
-        if (alu) {
-            const auto &alu_data = fast_cell_info.at(alu->flat_index);
-            if (ff_data.ff_d != alu_data.alu_sum) {
+            if (ff_data.ff_d != src) {
                 return false;
             }
         }
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 473efa21a9..77a2739874 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -817,11 +817,12 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
             tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
         tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
         if i < 6:
-            # FF data can come from LUT output, but we pretend that we can use
-            # any LUT input
             tt.create_pip(f"F{i}", f"XD{i}", get_tm_class(db, f"F{i}"))
-            for inp_name in lut_inputs:
-                tt.create_pip(f"{inp_name}{i}", f"XD{i}", get_tm_class(db, f"{inp_name}{i}"))
+            # also experimental input for FF using SEL wire - this theory will
+            # allow to place unrelated LUT and FF next to each other
+            # don't create for now
+            #tt.create_pip(f"SEL{i}", f"XD{i}", get_tm_class(db, f"SEL{i}"))
+
             # FF
             ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
             tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 1e1c220822..ed3571a689 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -181,6 +181,12 @@ bool GowinUtils::need_BLKSEL_fix(void)
     return extra->chip_flags & Extra_chip_data_POD::NEED_BLKSEL_FIX;
 }
 
+IdString GowinUtils::create_aux_name(IdString main_name, int idx, const char *str_suffix)
+{
+    return idx ? ctx->idf("%s%s%d", main_name.c_str(ctx), str_suffix, idx)
+               : ctx->idf("%s%s", main_name.c_str(ctx), str_suffix);
+}
+
 std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
 {
     NPNR_ASSERT(!ctx->cells.count(name));
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 71f60f8c99..ff622804f4 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -107,6 +107,9 @@ struct GowinUtils
         return is_global_wire(ctx->getPipSrcWire(pip)) || is_global_wire(ctx->getPipDstWire(pip));
     }
 
+    // construct name
+    IdString create_aux_name(IdString main_name, int idx = 0, const char *str_suffix = "_aux$");
+
     // make cell but do not include it in the list of chip cells.
     std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index f774bbc32b..384c4bf9c9 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -508,15 +508,6 @@ struct GowinPacker
         make_iob_nets(*out_iob);
     }
 
-    IdString create_aux_name(IdString main_name, int idx = 0, const char *str_suffix = "_aux$")
-    {
-        std::string sfx("");
-        if (idx) {
-            sfx = std::to_string(idx);
-        }
-        return ctx->id(main_name.str(ctx) + std::string(str_suffix) + sfx);
-    }
-
     BelId get_aux_iologic_bel(const CellInfo &ci)
     {
         return ctx->getBelByLocation(gwu.get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
@@ -529,7 +520,7 @@ struct GowinPacker
         if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
             return nullptr;
         }
-        IdString aux_name = create_aux_name(ci.name, idx);
+        IdString aux_name = gwu.create_aux_name(ci.name, idx);
         BelId bel = get_aux_iologic_bel(ci);
         BelId io_bel = gwu.get_io_bel_from_iologic(bel);
         if (!ctx->checkBelAvail(io_bel)) {
@@ -720,9 +711,9 @@ struct GowinPacker
 
         // to simplify packaging, the parts of the OSER16 are presented as IOLOGIC cells
         // and one of these aux cells is declared as main
-        IdString main_name = create_aux_name(ci.name);
+        IdString main_name = gwu.create_aux_name(ci.name);
 
-        IdString aux_name = create_aux_name(ci.name, 1);
+        IdString aux_name = gwu.create_aux_name(ci.name, 1);
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
         CellInfo *aux = ctx->cells.at(aux_name).get();
 
@@ -794,9 +785,9 @@ struct GowinPacker
 
         // to simplify packaging, the parts of the IDES16 are presented as IOLOGIC cells
         // and one of these aux cells is declared as main
-        IdString main_name = create_aux_name(ci.name);
+        IdString main_name = gwu.create_aux_name(ci.name);
 
-        IdString aux_name = create_aux_name(ci.name, 1);
+        IdString aux_name = gwu.create_aux_name(ci.name, 1);
         ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
         CellInfo *aux = ctx->cells.at(aux_name).get();
 
@@ -1229,7 +1220,7 @@ struct GowinPacker
                                          {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
                                          {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
 
-        int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 0);
+        int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1, 1);
         log_info("Constrained %d LUTFF pairs.\n", lutffs);
     }
 
@@ -1365,7 +1356,7 @@ struct GowinPacker
         }
 
         // Make a decoder
-        auto lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_blksel_lut$"), id_LUT4);
+        auto lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_blksel_lut$"), id_LUT4);
         CellInfo *lut = lut_cell.get();
         lut->addInput(id_I3);
         ci->movePortTo(id_CE, lut, id_I3);
@@ -1441,7 +1432,7 @@ struct GowinPacker
                 }
 
                 // create DFF
-                auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), dff_type);
+                auto cache_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_dff$"), dff_type);
                 CellInfo *cache_dff = cache_dff_cell.get();
                 cache_dff->addInput(id_CE);
                 cache_dff->connectPort(id_CE, oce_net);
@@ -1477,7 +1468,7 @@ struct GowinPacker
             log_info("  apply the SP fix\n");
         }
         // create WRE LUT
-        auto wre_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
+        auto wre_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
         CellInfo *wre_lut = wre_lut_cell.get();
         wre_lut->setParam(id_INIT, 0x8888);
         ci->movePortTo(id_CE, wre_lut, id_I0);
@@ -1486,7 +1477,7 @@ struct GowinPacker
         ci->connectPorts(id_WRE, wre_lut, id_F);
 
         // create CE LUT
-        auto ce_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_lut$"), id_LUT4);
+        auto ce_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_lut$"), id_LUT4);
         CellInfo *ce_lut = ce_lut_cell.get();
         ce_lut->setParam(id_INIT, 0xeeee);
         wre_lut->copyPortTo(id_I0, ce_lut, id_I0);
@@ -1497,7 +1488,7 @@ struct GowinPacker
         // create ce reg
         int write_mode = ci->params.at(id_WRITE_MODE).as_int64();
         IdString dff_type = write_mode ? id_DFF : id_DFFR;
-        auto ce_pre_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pre_dff$"), dff_type);
+        auto ce_pre_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_pre_dff$"), dff_type);
         CellInfo *ce_pre_dff = ce_pre_dff_cell.get();
         ce_pre_dff->addInput(id_D);
         ce_lut->copyPortTo(id_I0, ce_pre_dff, id_D);
@@ -1513,7 +1504,7 @@ struct GowinPacker
         // add delay register in pipeline mode
         int read_mode = ci->params.at(id_READ_MODE).as_int64();
         if (read_mode) {
-            auto ce_pipe_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
+            auto ce_pipe_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
             new_cells.push_back(std::move(ce_pipe_dff_cell));
             CellInfo *ce_pipe_dff = new_cells.back().get();
             ce_pipe_dff->addInput(id_D);
@@ -1533,7 +1524,7 @@ struct GowinPacker
                     continue;
                 }
                 // create cache lut
-                auto cache_lut_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_lut$"), id_LUT4);
+                auto cache_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_lut$"), id_LUT4);
                 CellInfo *cache_lut = cache_lut_cell.get();
                 cache_lut->setParam(id_INIT, 0xcaca);
                 cache_lut->addInput(id_I0);
@@ -1544,7 +1535,7 @@ struct GowinPacker
                 new_ce_net_src->connectPorts(id_Q, cache_lut, id_I2);
 
                 // create cache DFF
-                auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), id_DFFE);
+                auto cache_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_dff$"), id_DFFE);
                 CellInfo *cache_dff = cache_dff_cell.get();
                 cache_dff->addInput(id_CE);
                 cache_dff->addInput(id_D);
@@ -1950,7 +1941,7 @@ struct GowinPacker
                     ci->constr_y = 0;
                     ci->constr_y = 0;
 
-                    IdString mult_name = create_aux_name(ci->name);
+                    IdString mult_name = gwu.create_aux_name(ci->name);
                     std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                     new_cells.push_back(std::move(mult_cell));
                     CellInfo *mult_ci = new_cells.back().get();
@@ -2009,7 +2000,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 2; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2020,7 +2011,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::PADD18_0_0_Z + i;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2061,7 +2052,7 @@ struct GowinPacker
                     ci->constr_z = 0;
                     ci->constr_children.clear();
 
-                    IdString padd_name = create_aux_name(ci->name);
+                    IdString padd_name = gwu.create_aux_name(ci->name);
                     std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                     new_cells.push_back(std::move(padd_cell));
                     CellInfo *padd_ci = new_cells.back().get();
@@ -2103,7 +2094,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 2; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2114,7 +2105,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULT18X18_0_0_Z + i;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2161,7 +2152,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 4; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2172,7 +2163,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::ALU54D_0_Z + 4 * (i / 2) + (i % 2);
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2266,7 +2257,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 2; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2277,7 +2268,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU18X18_0_Z + i;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2369,7 +2360,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 2; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2380,7 +2371,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU36X18_0_Z + i;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2463,7 +2454,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 2; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2474,7 +2465,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTADDALU18X18_0_Z + i;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -2549,7 +2540,7 @@ struct GowinPacker
                     ci->constr_children.clear();
 
                     for (int i = 0; i < 8; ++i) {
-                        IdString padd_name = create_aux_name(ci->name, i * 2);
+                        IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
                         std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(padd_cell));
                         CellInfo *padd_ci = new_cells.back().get();
@@ -2562,7 +2553,7 @@ struct GowinPacker
                         padd_ci->constr_y = 0;
                         padd_ci->constr_z = padd_z[i / 2] - BelZ::MULT36X36_Z + i % 2;
 
-                        IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
+                        IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
                         std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
                         new_cells.push_back(std::move(mult_cell));
                         CellInfo *mult_ci = new_cells.back().get();
@@ -3165,7 +3156,7 @@ struct GowinPacker
                 }
 
                 std::unique_ptr<CellInfo> lut_cell =
-                        gwu.create_cell(create_aux_name(ci.name, lut_idx, "_lut$"), id_LUT4);
+                        gwu.create_cell(gwu.create_aux_name(ci.name, lut_idx, "_lut$"), id_LUT4);
                 new_cells.push_back(std::move(lut_cell));
                 CellInfo *lut = new_cells.back().get();
                 lut->addInput(id_I0);
@@ -3340,8 +3331,7 @@ struct GowinPacker
         pack_alus();
         ctx->check();
 
-        // XXX Leads to the impossibility of placement on lower models.
-        // constrain_lutffs();
+        constrain_lutffs();
         ctx->check();
 
         pack_pll();

From 55035465aa8752155234f3d07a5dbfe88890c3e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Thu, 21 Nov 2024 15:13:22 +0100
Subject: [PATCH 702/712] Himbaechel GUI (#1295)

* Extend Himbaechel API with gfx drawing methods

* Add bel drawing in example uarch

* changed API and added tile wire id in db

* extend API so we can distinguish CLK wires

* added bit more wires

* less horrid way of handling gfx ids

* loop wire range

* removed not needed brackets

* bump database version to 5

* Removed not used GfxFlags
---
 himbaechel/arch.cc                           |  61 ++++++-
 himbaechel/arch.h                            |   9 +
 himbaechel/archdefs.h                        |  23 ++-
 himbaechel/chipdb.h                          |   1 +
 himbaechel/himbaechel_api.h                  |   9 +
 himbaechel/himbaechel_dbgen/chip.py          |  25 ++-
 himbaechel/himbaechel_gfxids.h               |  53 ++++++
 himbaechel/uarch/example/CMakeLists.txt      |   1 +
 himbaechel/uarch/example/constids.inc        |  26 ++-
 himbaechel/uarch/example/example.cc          | 179 +++++++++++++++++++
 himbaechel/uarch/example/example_arch_gen.py |   1 +
 himbaechel/uarch/example/gfxids.inc          | 123 +++++++++++++
 12 files changed, 506 insertions(+), 5 deletions(-)
 create mode 100644 himbaechel/himbaechel_gfxids.h
 create mode 100644 himbaechel/uarch/example/gfxids.inc

diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 4152e7aee3..9ae9225e00 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -33,7 +33,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static constexpr int database_version = 4;
+static constexpr int database_version = 5;
 
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
@@ -501,4 +501,63 @@ IdString Arch::get_tile_type(int tile) const
     return IdString(tile_data.type_name);
 }
 
+std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
+{
+    std::vector<GraphicElement> ret;
+    if (decal.type == DecalId::TYPE_BEL) {
+        BelId bel(decal.tile, decal.index);
+        GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+        uarch->drawBel(ret, style, getBelType(bel), getBelLocation(bel));
+    } else if (decal.type == DecalId::TYPE_WIRE) {
+        WireId w(decal.tile, decal.index);
+        for (WireId wire: get_tile_wire_range(w)) {
+            auto wire_type = getWireType(wire);
+            GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+            Loc loc;
+            tile_xy(chip_info, wire.tile, loc.x, loc.y);
+            int32_t tilewire = chip_wire_info(chip_info, wire).tile_wire;
+            uarch->drawWire(ret, style, loc, wire_type, tilewire, get_tile_type(wire.tile));
+        }
+    } else if (decal.type == DecalId::TYPE_PIP) {
+        PipId pip(decal.tile, decal.index);
+        WireId src_wire = getPipSrcWire(pip);
+        WireId dst_wire = getPipDstWire(pip);
+        Loc loc = getPipLocation(pip);
+        int32_t src_id = chip_wire_info(chip_info, src_wire).tile_wire;
+        int32_t dst_id = chip_wire_info(chip_info, dst_wire).tile_wire;
+        GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
+        uarch->drawPip(ret, style, loc, src_wire, getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire), dst_id);
+    }
+    return ret;
+}
+
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+    DecalXY decalxy;
+    decalxy.decal = DecalId(bel.tile, bel.index, DecalId::TYPE_BEL);
+    decalxy.decal.active = getBoundBelCell(bel) != nullptr;
+    return decalxy;
+}
+
+DecalXY Arch::getWireDecal(WireId wire) const
+{
+    DecalXY decalxy;
+    decalxy.decal = DecalId(wire.tile, wire.index, DecalId::TYPE_WIRE);
+    decalxy.decal.active = getBoundWireNet(wire) != nullptr;
+    return decalxy;
+}
+
+DecalXY Arch::getPipDecal(PipId pip) const
+{
+    DecalXY decalxy;
+    decalxy.decal = DecalId(pip.tile, pip.index, DecalId::TYPE_PIP);
+    decalxy.decal.active = getBoundPipNet(pip) != nullptr;
+    return decalxy;
+}
+
+DecalXY Arch::getGroupDecal(GroupId group) const
+{
+    return DecalXY();
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index 80765da356..c1076d5a56 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -698,6 +698,15 @@ struct Arch : BaseArch<ArchRanges>
     {
         return uarch->getClusterPlacement(cluster, root_bel, placement);
     }
+
+    // -------------------------------------------------
+    // Decal methods
+    std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
+    DecalXY getBelDecal(BelId bel) const override;
+    DecalXY getWireDecal(WireId wire) const override;
+    DecalXY getPipDecal(PipId pip) const override;
+    DecalXY getGroupDecal(GroupId group) const override;
+
     // ------------------------------------------------
 
     bool pack() override;
diff --git a/himbaechel/archdefs.h b/himbaechel/archdefs.h
index d4b8d62155..589dea9926 100644
--- a/himbaechel/archdefs.h
+++ b/himbaechel/archdefs.h
@@ -85,7 +85,28 @@ struct PipId
     unsigned int hash() const { return mkhash(tile, index); }
 };
 
-typedef IdString DecalId;
+struct DecalId
+{
+    int32_t tile = -1;
+    int32_t index = -1;
+    enum DecalType
+    {
+        TYPE_NONE,
+        TYPE_BEL,
+        TYPE_WIRE,
+        TYPE_PIP,
+        TYPE_GROUP
+    } type = TYPE_NONE;
+    bool active = false;
+
+    DecalId() = default;
+    DecalId(int32_t tile, int32_t index, DecalType type) : tile(tile), index(index), type(type) {};
+
+    bool operator==(const DecalId &other) const { return tile == other.tile && index == other.index && type == other.type; }
+    bool operator!=(const DecalId &other) const { return tile != other.tile || index != other.index || type != other.type; }
+    unsigned int hash() const { return mkhash(tile, mkhash(index, type)); }
+};
+
 typedef IdString GroupId;
 typedef IdString BelBucketId;
 typedef IdString ClusterId;
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 17430ac4c2..4f3241c781 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -62,6 +62,7 @@ NPNR_PACKED_STRUCT(struct BelPinRefPOD {
 NPNR_PACKED_STRUCT(struct TileWireDataPOD {
     int32_t name;
     int32_t wire_type;
+    int32_t tile_wire;
     int32_t const_value;
     int32_t flags;      // 32 bits of arbitrary data
     int32_t timing_idx; // used only when the wire is not part of a node, otherwise node idx applies
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index e795e4d5df..f432921738 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -105,6 +105,15 @@ struct HimbaechelAPI
     virtual bool isClusterStrict(const CellInfo *cell) const;
     virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
                                      std::vector<std::pair<CellInfo *, BelId>> &placement) const;
+
+    // Graphics
+    virtual void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) {};
+
+    virtual void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire, IdString tile_type) {};
+
+    virtual void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
+                WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id) {};
+
     // --- Flow hooks ---
     virtual void pack() {}; // replaces the pack function
     // Called before and after main placement and routing
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index a5ee2b4272..bedf0f28d4 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -144,6 +144,7 @@ class TileWireData:
     index: int
     name: IdString
     wire_type: IdString
+    gfx_wire_id: int
     const_value: IdString = field(default_factory=list)
     flags: int = 0
     timing_idx: int = -1
@@ -166,6 +167,7 @@ def serialise_lists(self, context: str, bba: BBAWriter):
     def serialise(self, context: str, bba: BBAWriter):
         bba.u32(self.name.index)
         bba.u32(self.wire_type.index)
+        bba.u32(self.gfx_wire_id)
         bba.u32(self.const_value.index)
         bba.u32(self.flags)
         bba.u32(self.timing_idx)
@@ -202,6 +204,7 @@ def serialise(self, context: str, bba: BBAWriter):
 @dataclass
 class TileType(BBAStruct):
     strs: StringPool
+    gfx_wire_ids: dict()
     tmg: "TimingPool"
     type_name: IdString
     bels: list[BelData] = field(default_factory=list)
@@ -229,9 +232,13 @@ def add_bel_pin(self, bel: BelData, pin: str, wire: str, dir: PinType):
 
     def create_wire(self, name: str, type: str="", const_value: str=""):
         # Create a new tile wire of a given name and type (optional) in the tile type
+        gfx_wire_id = 0
+        if name in self.gfx_wire_ids:
+            gfx_wire_id = self.gfx_wire_ids[name]
         wire = TileWireData(index=len(self.wires),
             name=self.strs.id(name),
             wire_type=self.strs.id(type),
+            gfx_wire_id=gfx_wire_id,
             const_value=self.strs.id(const_value))
         self._wire2idx[wire.name] = wire.index
         self.wires.append(wire)
@@ -700,8 +707,9 @@ def __init__(self, uarch: str, name: str, width: int, height: int):
         self.packages = []
         self.extra_data = None
         self.timing = TimingPool(self.strs)
+        self.gfx_wire_ids = dict()
     def create_tile_type(self, name: str):
-        tt = TileType(self.strs, self.timing, self.strs.id(name))
+        tt = TileType(self.strs, self.gfx_wire_ids, self.timing, self.strs.id(name))
         self.tile_type_idx[name] = len(self.tile_types)
         self.tile_types.append(tt)
         return tt
@@ -831,7 +839,7 @@ def serialise(self, bba: BBAWriter):
 
         bba.label("chip_info")
         bba.u32(0x00ca7ca7) # magic
-        bba.u32(4) # version
+        bba.u32(5) # version
         bba.u32(self.width)
         bba.u32(self.height)
 
@@ -866,3 +874,16 @@ def write_bba(self, filename):
             bba.ref('chip_info')
             self.serialise(bba)
             bba.pop()
+
+    def read_gfxids(self, filename):
+        idx = 1
+        with open(filename) as f:
+            for line in f:
+                l = line.strip()
+                if not l.startswith("X("):
+                    continue
+                l = l[2:]
+                assert l.endswith(")"), l
+                l = l[:-1].strip()
+                self.gfx_wire_ids[l] = idx
+                idx += 1
diff --git a/himbaechel/himbaechel_gfxids.h b/himbaechel/himbaechel_gfxids.h
new file mode 100644
index 0000000000..8d954bb3f3
--- /dev/null
+++ b/himbaechel/himbaechel_gfxids.h
@@ -0,0 +1,53 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_GFXIDS_H
+#define HIMBAECHEL_GFXIDS_H
+
+/*
+This enables use of 'gfxids' similar to a 'constids' in a HIMBAECHEL uarch.
+To use:
+    - create a 'gfxids.inc' file in your uarch folder containing one ID per line; inside X( )
+    - set the HIMBAECHEL_UARCH macro to uarch namespace
+    - set the HIMBAECHEL_GFXIDS macro to the path to this file relative to the generic arch base
+    - include this file
+*/
+
+#include "nextpnr_namespaces.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace HIMBAECHEL_UARCH {
+#ifndef Q_MOC_RUN
+enum GfxTileWireId
+{
+    GFX_WIRE_NONE
+#define X(t) , GFX_WIRE_##t
+#include HIMBAECHEL_GFXIDS
+#undef X
+    ,
+};
+#endif
+};
+
+NEXTPNR_NAMESPACE_END
+
+using namespace NEXTPNR_NAMESPACE_PREFIX HIMBAECHEL_UARCH;
+
+#endif
diff --git a/himbaechel/uarch/example/CMakeLists.txt b/himbaechel/uarch/example/CMakeLists.txt
index 046f01306a..26be2ea31b 100644
--- a/himbaechel/uarch/example/CMakeLists.txt
+++ b/himbaechel/uarch/example/CMakeLists.txt
@@ -22,6 +22,7 @@ foreach(device ${HIMBAECHEL_EXAMPLE_DEVICES})
 			bbasm
 			${CMAKE_CURRENT_SOURCE_DIR}/example_arch_gen.py
 			${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+			${CMAKE_CURRENT_SOURCE_DIR}/gfxids.inc
 		VERBATIM)
 	list(APPEND chipdb_binaries ${device_bin})
 endforeach()
diff --git a/himbaechel/uarch/example/constids.inc b/himbaechel/uarch/example/constids.inc
index 900577e46c..eca9b10827 100644
--- a/himbaechel/uarch/example/constids.inc
+++ b/himbaechel/uarch/example/constids.inc
@@ -13,7 +13,31 @@ X(IOB)
 X(PAD)
 X(INIT)
 
+X(BRAM_512X16)
+
 X(GND)
 X(GND_DRV)
 X(VCC)
-X(VCC_DRV)
\ No newline at end of file
+X(VCC_DRV)
+
+X(LUT_INPUT)
+X(FF_DATA)
+X(LUT_OUT)
+X(FF_OUT)
+X(TILE_CLK)
+
+X(RAM_IN)
+X(RAM_OUT)
+
+X(IO_I)
+X(IO_O)
+X(IO_T)
+X(IO_PAD)
+X(GCLK)
+
+X(CLK_ROUTE)
+
+X(LOGIC)
+X(BRAM)
+X(IO)
+X(NULL)
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index 391a8ca441..42b7608668 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -26,7 +26,10 @@
 
 #define GEN_INIT_CONSTIDS
 #define HIMBAECHEL_CONSTIDS "uarch/example/constids.inc"
+#define HIMBAECHEL_GFXIDS "uarch/example/gfxids.inc"
+#define HIMBAECHEL_UARCH example
 #include "himbaechel_constids.h"
+#include "himbaechel_gfxids.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -135,6 +138,182 @@ struct ExampleImpl : HimbaechelAPI
             return false;
         return true;
     }
+
+    void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override
+    {
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_BOX;
+        el.style = style;
+        switch (bel_type.index)
+        {
+            case id_LUT4.index :
+                el.x1 = loc.x + 0.15;
+                el.x2 = el.x1 + 0.25;
+                el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
+                el.y2 = el.y1 - 0.05;
+                g.push_back(el);
+                break;
+            case id_DFF.index :
+                el.x1 = loc.x + 0.55;
+                el.x2 = el.x1 + 0.25;
+                el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
+                el.y2 = el.y1 - 0.05;
+                g.push_back(el);
+                break;
+            case id_GND_DRV.index :
+            case id_VCC_DRV.index :
+            case id_IOB.index :
+                el.x1 = loc.x + 0.25;
+                el.x2 = el.x1 + 0.50;
+                el.y1 = loc.y + 0.80 - loc.z * 0.40;
+                el.y2 = el.y1 - 0.25;
+                g.push_back(el);
+                break;
+            case id_BRAM_512X16.index :
+                el.x1 = loc.x + 0.25;
+                el.x2 = el.x1 + 0.50;
+                el.y1 = loc.y + 0.80;
+                el.y2 = el.y1 - 0.60;
+                g.push_back(el);
+                break;
+        }
+    }
+
+    void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire, IdString tile_type)
+    {
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_LINE;
+        el.style = style;
+        int z;
+        switch(tile_type.index)
+        {
+            case id_LOGIC.index:
+                switch (wire_type.index)
+                {
+                    case id_LUT_INPUT.index:
+                        z = (tilewire - GFX_WIRE_L0_I0) / 4;
+                        el.x1 = loc.x + 0.10;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.85 - z * 0.1  - ((tilewire - GFX_WIRE_L0_I0) % 4 + 1) * 0.01;
+                        el.y2 = el.y1;
+                        g.push_back(el);
+                        break;
+                    case id_LUT_OUT.index:
+                        z = tilewire - GFX_WIRE_L0_O;
+                        el.x1 = loc.x + 0.40;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
+                        el.y2 = el.y1;
+                        g.push_back(el);
+                        break;
+                    case id_FF_DATA.index:
+                        z = tilewire - GFX_WIRE_L0_D;
+                        el.x1 = loc.x + 0.50;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
+                        el.y2 = el.y1;
+                        g.push_back(el);
+                        break;
+                    case id_FF_OUT.index:
+                        z = tilewire - GFX_WIRE_L0_Q;
+                        el.x1 = loc.x + 0.80;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
+                        el.y2 = el.y1;
+                        g.push_back(el);
+                        break;
+                    case id_TILE_CLK.index:
+                        for(int i=0;i<8; i++) {
+                            GraphicElement el;
+                            el.type = GraphicElement::TYPE_LINE;
+                            el.style = style;
+                            el.x1 = loc.x + 0.6;
+                            el.x2 = el.x1;
+                            el.y1 = loc.y + 0.85 - i * 0.1 - 0.05;
+                            el.y2 = el.y1 - 0.05;
+                            g.push_back(el);
+                        }
+                        break;
+                }
+                break;
+            case id_BRAM.index:
+                switch (wire_type.index)
+                {
+                    case id_RAM_IN.index:
+                        z = tilewire - GFX_WIRE_RAM_WA0;
+                        el.x1 = loc.x + 0.20;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.78 - z * 0.015;
+                        el.y2 = el.y1;
+                        g.push_back(el);
+                        break;
+                    case id_RAM_OUT.index:
+                        z = tilewire - GFX_WIRE_RAM_DO0;
+                        el.x1 = loc.x + 0.75;
+                        el.x2 = el.x1 + 0.05;
+                        el.y1 = loc.y + 0.78 - z * 0.015;
+                        el.y2 = el.y1;
+                        g.push_back(el);                    
+                        break;
+                    case id_TILE_CLK.index:
+                        el.x1 = loc.x + 0.6;
+                        el.x2 = el.x1;
+                        el.y1 = loc.y + 0.20;
+                        el.y2 = el.y1 - 0.05;
+                        g.push_back(el);
+                        break;
+                }
+                break;
+            case id_IO.index:
+                switch (wire_type.index)
+                {
+                    case id_IO_I.index:
+                        break;
+                    case id_IO_O.index:
+                        break;
+                    case id_IO_T.index:
+                        break;
+                    case id_IO_PAD.index:
+                        break;
+                    case id_TILE_CLK.index:
+                        break;
+                    case id_GCLK.index:
+                        break;
+                }
+                break;
+            case id_NULL.index:
+                switch (wire_type.index)
+                {
+                    case id_CLK_ROUTE.index:
+                        break;
+                    case id_GND.index:
+                        break;
+                    case id_VCC.index:
+                        break;
+                    case id_TILE_CLK.index:
+                        break;
+                }
+                break;
+        }
+    }
+
+    void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
+            WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id)
+    {
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_ARROW;
+        el.style = style;
+        int z;
+        if (src_type == id_LUT_OUT && dst_type == id_FF_DATA) {
+            z = src_id - GFX_WIRE_L0_O;
+            el.x1 = loc.x + 0.45;
+            el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
+            el.x2 = loc.x + 0.50;
+            el.y2 = el.y1;
+            g.push_back(el);
+
+        }
+    }
 };
 
 struct ExampleArch : HimbaechelArch
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
index cbfefd61ef..d36ae22e63 100644
--- a/himbaechel/uarch/example/example_arch_gen.py
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -237,6 +237,7 @@ def main():
     ch = Chip("example", "EX1", X, Y)
     # Init constant ids
     ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
+    ch.read_gfxids(path.join(path.dirname(__file__), "gfxids.inc")) 
     logic = create_logic_tiletype(ch)
     io = create_io_tiletype(ch)
     bram = create_bram_tiletype(ch)
diff --git a/himbaechel/uarch/example/gfxids.inc b/himbaechel/uarch/example/gfxids.inc
new file mode 100644
index 0000000000..567480821e
--- /dev/null
+++ b/himbaechel/uarch/example/gfxids.inc
@@ -0,0 +1,123 @@
+X(L0_O)
+X(L1_O)
+X(L2_O)
+X(L3_O)
+X(L4_O)
+X(L5_O)
+X(L6_O)
+X(L7_O)
+
+X(L0_I0)
+X(L0_I1)
+X(L0_I2)
+X(L0_I3)
+
+X(L1_I0)
+X(L1_I1)
+X(L1_I2)
+X(L1_I3)
+
+X(L2_I0)
+X(L2_I1)
+X(L2_I2)
+X(L2_I3)
+
+X(L3_I0)
+X(L3_I1)
+X(L3_I2)
+X(L3_I3)
+
+X(L4_I0)
+X(L4_I1)
+X(L4_I2)
+X(L4_I3)
+
+X(L5_I0)
+X(L5_I1)
+X(L5_I2)
+X(L5_I3)
+
+X(L6_I0)
+X(L6_I1)
+X(L6_I2)
+X(L6_I3)
+
+X(L7_I0)
+X(L7_I1)
+X(L7_I2)
+X(L7_I3)
+
+X(L0_D)
+X(L1_D)
+X(L2_D)
+X(L3_D)
+X(L4_D)
+X(L5_D)
+X(L6_D)
+X(L7_D)
+
+X(L0_Q)
+X(L1_Q)
+X(L2_Q)
+X(L3_Q)
+X(L4_Q)
+X(L5_Q)
+X(L6_Q)
+X(L7_Q)
+
+X(RAM_WA0)
+X(RAM_WA1)
+X(RAM_WA2)
+X(RAM_WA3)
+X(RAM_WA4)
+X(RAM_WA5)
+X(RAM_WA6)
+X(RAM_WA7)
+X(RAM_WA8)
+
+X(RAM_RA0)
+X(RAM_RA1)
+X(RAM_RA2)
+X(RAM_RA3)
+X(RAM_RA4)
+X(RAM_RA5)
+X(RAM_RA6)
+X(RAM_RA7)
+X(RAM_RA8)
+
+X(RAM_WE0)
+X(RAM_WE1)
+
+X(RAM_DI0)
+X(RAM_DI1)
+X(RAM_DI2)
+X(RAM_DI3)
+X(RAM_DI4)
+X(RAM_DI5)
+X(RAM_DI6)
+X(RAM_DI7)
+X(RAM_DI8)
+X(RAM_DI9)
+X(RAM_DI10)
+X(RAM_DI11)
+X(RAM_DI12)
+X(RAM_DI13)
+X(RAM_DI14)
+X(RAM_DI15)
+
+X(RAM_DO0)
+X(RAM_DO1)
+X(RAM_DO2)
+X(RAM_DO3)
+X(RAM_DO4)
+X(RAM_DO5)
+X(RAM_DO6)
+X(RAM_DO7)
+X(RAM_DO8)
+X(RAM_DO9)
+X(RAM_DO10)
+X(RAM_DO11)
+X(RAM_DO12)
+X(RAM_DO13)
+X(RAM_DO14)
+X(RAM_DO15)

From 0e69425794da7eccdedbd13bfd37898474fa5e59 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Tue, 26 Nov 2024 10:13:41 +0100
Subject: [PATCH 703/712] Add expandBoundingBox method to API (#1395)

* Add expandBoundingBox method to API

* Update API documentation
---
 common/kernel/arch_api.h     | 3 +++
 common/kernel/base_arch.h    | 8 ++++++++
 common/route/router2.cc      | 9 +--------
 docs/archapi.md              | 9 +++++++++
 himbaechel/arch.h            | 4 ++++
 himbaechel/himbaechel_api.cc | 5 +++++
 himbaechel/himbaechel_api.h  | 2 ++
 mistral/arch.h               | 4 ++++
 8 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/common/kernel/arch_api.h b/common/kernel/arch_api.h
index 88582adde7..4eb6f4dde5 100644
--- a/common/kernel/arch_api.h
+++ b/common/kernel/arch_api.h
@@ -147,6 +147,9 @@ template <typename R> struct ArchAPI : BaseCtx
     virtual bool isClusterStrict(const CellInfo *cell) const = 0;
     virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,
                                      std::vector<std::pair<CellInfo *, BelId>> &placement) const = 0;
+    // Routing methods
+    virtual void expandBoundingBox(BoundingBox &bb) const = 0;
+
     // Flow methods
     virtual bool pack() = 0;
     virtual bool place() = 0;
diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 708636a0d1..2929bcba98 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -442,6 +442,14 @@ template <typename R> struct BaseArch : ArchAPI<R>
         });
     }
 
+    // Routing methods
+    virtual void expandBoundingBox(BoundingBox &bb) const override {
+        bb.x0 = std::max(bb.x0 - 1, 0);
+        bb.y0 = std::max(bb.y0 - 1, 0);
+        bb.x1 = std::min(bb.x1 + 1, this->getGridDimX());
+        bb.y1 = std::min(bb.y1 + 1, this->getGridDimY());
+    }
+
     // Flow methods
     virtual void assignArchInfo() override {};
 
diff --git a/common/route/router2.cc b/common/route/router2.cc
index 5ae091eea4..148c405117 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -1013,14 +1013,7 @@ struct Router2
             ++net_data.fail_count;
             if ((net_data.fail_count % 3) == 0) {
                 // Every three times a net fails to route, expand the bounding box to increase the search space
-#ifndef ARCH_MISTRAL
-                // This patch seems to make thing worse for CycloneV, as it slows down the resolution of TD congestion,
-                // disable it
-                net_data.bb.x0 = std::max(net_data.bb.x0 - 1, 0);
-                net_data.bb.y0 = std::max(net_data.bb.y0 - 1, 0);
-                net_data.bb.x1 = std::min(net_data.bb.x1 + 1, ctx->getGridDimX());
-                net_data.bb.y1 = std::min(net_data.bb.y1 + 1, ctx->getGridDimY());
-#endif
+                ctx->expandBoundingBox(net_data.bb);
             }
         }
     }
diff --git a/docs/archapi.md b/docs/archapi.md
index 043f937b34..9918a895e7 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -765,3 +765,12 @@ Returns `true` if the cell **must** be placed according to the cluster; for exam
 Gets an exact placement of the cluster, with the root cell placed on or near `root_bel` (and always within the same tile). Returns false if no placement is viable, otherwise returns `true` and populates `placement` with a list of cells inside the cluster and bels they should be placed at.
 
 This approach of allowing architectures to define cluster placements enables easier handling of irregular fabrics than requiring strict and constant x, y and z offsets.
+
+Router Methods
+---------------
+
+### void expandBoundingBox(BoundingBox &bb) const
+
+As part of `router2` implementation, during congestion update, every third time a net fails to route, this method is executed to expand the bounding box to increase the search space.
+
+Default implementation expands by one tile in each direction.
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index c1076d5a56..ca965c8625 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -707,6 +707,10 @@ struct Arch : BaseArch<ArchRanges>
     DecalXY getPipDecal(PipId pip) const override;
     DecalXY getGroupDecal(GroupId group) const override;
 
+    // ------------------------------------------------
+    // Routing methods
+    void expandBoundingBox(BoundingBox &bb) const override { uarch->expandBoundingBox(bb); };
+
     // ------------------------------------------------
 
     bool pack() override;
diff --git a/himbaechel/himbaechel_api.cc b/himbaechel/himbaechel_api.cc
index 0efe5c6f14..23b2476987 100644
--- a/himbaechel/himbaechel_api.cc
+++ b/himbaechel/himbaechel_api.cc
@@ -85,6 +85,11 @@ bool HimbaechelAPI::getClusterPlacement(ClusterId cluster, BelId root_bel,
     return ctx->BaseArch::getClusterPlacement(cluster, root_bel, placement);
 }
 
+void HimbaechelAPI::expandBoundingBox(BoundingBox &bb) const
+{
+    ctx->BaseArch::expandBoundingBox(bb);
+}
+
 HimbaechelArch *HimbaechelArch::list_head;
 HimbaechelArch::HimbaechelArch(const std::string &name) : name(name)
 {
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index f432921738..fa75740139 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -114,6 +114,8 @@ struct HimbaechelAPI
     virtual void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
                 WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id) {};
 
+    // Routing methods
+    virtual void expandBoundingBox(BoundingBox &bb) const;
     // --- Flow hooks ---
     virtual void pack() {}; // replaces the pack function
     // Called before and after main placement and routing
diff --git a/mistral/arch.h b/mistral/arch.h
index f2de793d4e..10309bf019 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -450,6 +450,10 @@ struct Arch : BaseArch<ArchRanges>
     BelBucketId getBelBucketForCellType(IdString cell_type) const override;
     BelBucketId getBelBucketForBel(BelId bel) const override;
 
+    // -------------------------------------------------
+    // Expanding bounding box seems to make thing worse for CycloneV
+    // as it slows down the resolution of TD congestion, disabling it
+    void expandBoundingBox(BoundingBox &bb) const override {};
     // -------------------------------------------------
 
     void assignArchInfo() override;

From 2b8a23577659adc043696af967e8ae0b239cf4e6 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 27 Nov 2024 18:57:34 +1000
Subject: [PATCH 704/712] Gowin. Add Input Edge Monitor (#1396)

Add sampling part to IO blocks (input only). This edge detector will
allow to dynamically adjust DDR decoding window in the future.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc      |  13 ++
 himbaechel/uarch/gowin/gowin.cc          |   3 +-
 himbaechel/uarch/gowin/gowin.h           |   6 +-
 himbaechel/uarch/gowin/gowin_arch_gen.py |   2 +-
 himbaechel/uarch/gowin/pack.cc           | 149 ++++++++++++++++++++++-
 5 files changed, 164 insertions(+), 9 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index f15496b714..36d35c4d24 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -122,6 +122,7 @@ X(W800)
 X(W810)
 X(W820)
 X(W830)
+X(MCLK)
 X(CLK0)
 X(CLK1)
 X(CLK2)
@@ -761,6 +762,16 @@ X(LWO6)
 X(LWO7)
 
 // IOLOGIC
+X(IEM)
+X(WINSIZE)
+X(WINSIZE0)
+X(WINSIZE1)
+X(SMALL)
+X(MIDSMALL)
+X(MIDLARGE)
+X(LARGE)
+X(LAG)
+X(LEAD)
 X(TX)
 X(TX0)
 X(TX1)
@@ -797,6 +808,7 @@ X(IDES8)
 X(IDES10)
 X(IVIDEO)
 X(IDES16)
+X(IOLOGICI_EMPTY)
 X(IOLOGIC)
 X(IOLOGICI)
 X(IOLOGICO)
@@ -1289,6 +1301,7 @@ X(RESETN)
 //HCLK Parameters
 X(DIV_MODE)
 X(GSREN)
+X(LSREN)
 
 // EMCU
 X(EMCU)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index a09c9ea715..0611f2ae4f 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -306,7 +306,8 @@ void GowinImpl::place_constrained_hclk_cells()
         if ((seen_hclk_users.find(ci->name) != seen_hclk_users.end()))
             continue;
 
-        if (((is_iologici(ci) || is_iologico(ci)) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
+        if (((is_iologici(ci) || is_iologico(ci)) &&
+             !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_IOLOGICI_EMPTY))) {
             NetInfo *hclk_net = ci->getPort(id_FCLK);
             if (hclk_net)
                 continue;
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 001c1cfb07..2785fd5a64 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -38,7 +38,7 @@ inline bool is_iologico(const CellInfo *cell) { return type_is_iologico(cell->ty
 
 inline bool type_is_iologici(IdString cell_type)
 {
-    return cell_type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO);
+    return cell_type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO, id_IOLOGICI_EMPTY);
 }
 inline bool is_iologici(const CellInfo *cell) { return type_is_iologici(cell->type); }
 
@@ -138,9 +138,7 @@ NPNR_PACKED_STRUCT(struct Constraint_POD {
     int32_t iostd;
 });
 
-NPNR_PACKED_STRUCT(struct Extra_package_data_POD {
-    RelSlice<Constraint_POD> cst;
-});
+NPNR_PACKED_STRUCT(struct Extra_package_data_POD { RelSlice<Constraint_POD> cst; });
 
 NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     int32_t chip_flags;
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index 77a2739874..f95308d8a8 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -762,7 +762,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
                 if port == 'FCLK': # XXX compatibility
                     wire = f'FCLK{name[-1]}'
                 if not tt.has_wire(wire):
-                    if port in {'CLK', 'PCLK'}:
+                    if port in {'CLK', 'PCLK', 'MCLK'}:
                         tt.create_wire(wire, "TILE_CLK")
                     else:
                         tt.create_wire(wire, "IOL_PORT")
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 384c4bf9c9..1c45722af9 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -365,7 +365,7 @@ struct GowinPacker
 
     void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4) || diff) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4, id_IOLOGICI_EMPTY) || diff) {
             return;
         }
         BelId l_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOBA_Z + 1 - (iob_loc.z - BelZ::IOBA_Z)));
@@ -517,7 +517,7 @@ struct GowinPacker
 
     CellInfo *create_aux_iologic_cell(CellInfo &ci, IdString mode, bool io16 = false, int idx = 0)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4, id_IOLOGICI_EMPTY)) {
             return nullptr;
         }
         IdString aux_name = gwu.create_aux_name(ci.name, idx);
@@ -597,6 +597,9 @@ struct GowinPacker
         ctx->bindBel(l_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         std::string in_mode;
         switch (ci.type.hash()) {
+        case ID_IOLOGICI_EMPTY:
+            in_mode = "EMPTY";
+            break;
         case ID_IDDR:
         case ID_IDDRC:
             in_mode = "IDDRX1";
@@ -616,6 +619,10 @@ struct GowinPacker
         }
         ci.setParam(ctx->id("INMODE"), in_mode);
 
+        if (ci.type == id_IOLOGICI_EMPTY) {
+            return;
+        }
+
         // disconnect D input: it is wired internally
         nets_to_remove.push_back(ci.getPort(in_port)->name);
         in_iob->disconnectPort(id_O);
@@ -626,6 +633,139 @@ struct GowinPacker
         make_iob_nets(*in_iob);
     }
 
+    void pack_iem()
+    {
+        log_info("Pack Input Edge Monitors...\n");
+        std::vector<IdString> cells_to_remove;
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (ci.type != id_IEM) {
+                continue;
+            }
+            if (ctx->debug) {
+                log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+            }
+            // IEM is part of IOLOGIC but functions independently of the
+            // presence/absence of other IOLOGIC components. Therefore, we use
+            // the existing cell whenever possible.
+            const NetInfo *d_net = ci.ports.at(id_D).net;
+            CellInfo *in_iob = net_driven_by(ctx, d_net, is_iob, id_O);
+            NPNR_ASSERT(in_iob != nullptr && in_iob->bel != BelId());
+            BelId iob_bel = in_iob->bel;
+
+            BelId l_bel = get_iologici_bel(in_iob);
+            if (l_bel == BelId()) {
+                log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
+            }
+            CellInfo *iologic = nullptr;
+            for (auto &usr : d_net->users) {
+                if (is_iologici(usr.cell)) {
+                    if (ctx->debug) {
+                        log_info(" found IOLOGIC cell %s of type %s, use it.\n", ctx->nameOf(usr.cell),
+                                 usr.cell->type.c_str(ctx));
+                    }
+                    iologic = usr.cell;
+                    if (iologic->ports.count(id_CLK)) {
+                        NPNR_ASSERT(iologic->ports.at(id_CLK).net == ci.ports.at(id_CLK).net);
+                    } else {
+                        if (iologic->ports.count(id_PCLK)) {
+                            NPNR_ASSERT(iologic->ports.at(id_PCLK).net == ci.ports.at(id_CLK).net);
+                        }
+                        iologic->addInput(ctx->id("CLK"));
+                    }
+                    if (iologic->ports.count(id_RESET)) {
+                        NPNR_ASSERT(iologic->ports.at(id_RESET).net == ci.ports.at(id_RESET).net);
+                    } else {
+                        iologic->addInput(ctx->id("RESET"));
+                    }
+                    break;
+                }
+            }
+            if (iologic == nullptr) {
+                IdString iologic_name = gwu.create_aux_name(ci.name);
+                if (ctx->debug) {
+                    log_info(" create IOLOGIC cell %s.\n", iologic_name.c_str(ctx));
+                }
+                auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICI_EMPTY);
+                new_cells.push_back(std::move(iologic_cell));
+                iologic = new_cells.back().get();
+                ci.copyPortTo(id_D, iologic, id_D);
+                ci.copyPortTo(id_CLK, iologic, id_CLK);
+                ci.copyPortTo(id_RESET, iologic, id_RESET);
+            }
+            ci.movePortTo(id_MCLK, iologic, id_MCLK);
+            ci.movePortTo(id_LAG, iologic, id_LAG);
+            ci.movePortTo(id_LEAD, iologic, id_LEAD);
+
+            ci.disconnectPort(id_D);
+            ci.disconnectPort(id_CLK);
+            ci.disconnectPort(id_RESET);
+
+            // WINSIZE attribute defines routing to ports WINSIZE0/1
+            iologic->addInput(id_WINSIZE0);
+            iologic->addInput(id_WINSIZE1);
+            if (ci.params.count(id_WINSIZE) == 0) {
+                ci.setParam(id_WINSIZE, Property("SMALL"));
+            }
+
+            NetInfo *vcc_net = ctx->nets.at(ctx->id("$PACKER_VCC")).get();
+            NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
+            IdString winsize = ctx->id(ci.params.at(id_WINSIZE).as_string());
+            switch (winsize.hash()) {
+            case ID_SMALL:
+                iologic->connectPort(id_WINSIZE0, vss_net);
+                iologic->connectPort(id_WINSIZE1, vss_net);
+                break;
+            case ID_MIDSMALL:
+                iologic->connectPort(id_WINSIZE0, vcc_net);
+                iologic->connectPort(id_WINSIZE1, vss_net);
+                break;
+            case ID_MIDLARGE:
+                iologic->connectPort(id_WINSIZE0, vss_net);
+                iologic->connectPort(id_WINSIZE1, vcc_net);
+                break;
+            case ID_LARGE:
+                iologic->connectPort(id_WINSIZE0, vcc_net);
+                iologic->connectPort(id_WINSIZE1, vcc_net);
+                break;
+            default:
+                log_error("%s has incorrect WINSIZE:%s\n", ctx->nameOf(&ci), ci.params.at(id_WINSIZE).c_str());
+            }
+
+            if (ci.params.count(id_GSREN) != 0) {
+                if (iologic->params.count(id_GSREN) == 0) {
+                    iologic->setParam(id_GSREN, ci.params.at(id_GSREN));
+                } else {
+                    if (ci.params.at(id_GSREN) != iologic->params.at(id_GSREN)) {
+                        log_error("GSREN parameter values of %s and %s do not match.\n", ctx->nameOf(&ci),
+                                  ctx->nameOf(iologic));
+                    }
+                }
+            }
+            if (ci.params.count(id_LSREN) != 0) {
+                if (iologic->params.count(id_LSREN) == 0) {
+                    iologic->setParam(id_LSREN, ci.params.at(id_LSREN));
+                } else {
+                    if (ci.params.at(id_LSREN) != iologic->params.at(id_LSREN)) {
+                        log_error("LSREN parameter values of %s and %s do not match.\n", ctx->nameOf(&ci),
+                                  ctx->nameOf(iologic));
+                    }
+                }
+            }
+            cells_to_remove.push_back(ci.name);
+        }
+
+        for (auto cell : cells_to_remove) {
+            ctx->cells.erase(cell);
+        }
+
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+    }
+
     void pack_iologic()
     {
         log_info("Pack IO logic...\n");
@@ -649,7 +789,7 @@ struct GowinPacker
                 create_aux_iologic_cell(ci, ctx->id("OUTMODE"));
                 continue;
             }
-            if (ci.type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO)) {
+            if (ci.type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO, id_IOLOGICI_EMPTY)) {
                 pack_ides_iol(ci, nets_to_remove);
                 create_aux_iologic_cell(ci, ctx->id("INMODE"));
                 continue;
@@ -3310,6 +3450,9 @@ struct GowinPacker
         pack_diff_iobs();
         ctx->check();
 
+        pack_iem();
+        ctx->check();
+
         pack_iologic();
         ctx->check();
 

From 5eaa1b3f1f34595604aa5f919c0b00033509923f Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 30 Nov 2024 18:24:59 +1000
Subject: [PATCH 705/712] Gowin. Add IODELAY. (#1398)

* Gowin. Add IODELAY.

Input/Output delay (IODELAY) is programmable delay uint in IO block.

This delay line is enabled before/after the IO pad and allows the signal
to be delayed statically or dynamically during 0-127 stages each lasting
from 18 to 30 picoseconds depending on the chip family.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Replacing assertions with log_error.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc |   7 ++
 himbaechel/uarch/gowin/gowin.cc     |   2 +-
 himbaechel/uarch/gowin/gowin.h      |   2 +-
 himbaechel/uarch/gowin/pack.cc      | 170 +++++++++++++++++++++++++---
 4 files changed, 164 insertions(+), 17 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 36d35c4d24..6e294b8663 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -762,6 +762,12 @@ X(LWO6)
 X(LWO7)
 
 // IOLOGIC
+X(C_STATIC_DLY)
+X(IODELAY)
+X(SDTAP)
+X(SETN)
+X(VALUE)
+X(DF)
 X(IEM)
 X(WINSIZE)
 X(WINSIZE0)
@@ -809,6 +815,7 @@ X(IDES10)
 X(IVIDEO)
 X(IDES16)
 X(IOLOGICI_EMPTY)
+X(IOLOGICO_EMPTY)
 X(IOLOGIC)
 X(IOLOGICI)
 X(IOLOGICO)
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index 0611f2ae4f..e3a4225ff2 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -307,7 +307,7 @@ void GowinImpl::place_constrained_hclk_cells()
             continue;
 
         if (((is_iologici(ci) || is_iologico(ci)) &&
-             !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_IOLOGICI_EMPTY))) {
+             !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_IOLOGICI_EMPTY, id_IOLOGICO_EMPTY))) {
             NetInfo *hclk_net = ci->getPort(id_FCLK);
             if (hclk_net)
                 continue;
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 2785fd5a64..e2903e9982 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -32,7 +32,7 @@ inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type);
 
 inline bool type_is_iologico(IdString cell_type)
 {
-    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO);
+    return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO, id_IOLOGICO_EMPTY);
 }
 inline bool is_iologico(const CellInfo *cell) { return type_is_iologico(cell->type); }
 
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 1c45722af9..e820bd160b 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -365,7 +365,7 @@ struct GowinPacker
 
     void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4, id_IOLOGICI_EMPTY) || diff) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC, id_OSER4, id_IOLOGICI_EMPTY, id_IOLOGICO_EMPTY) || diff) {
             return;
         }
         BelId l_bel = ctx->getBelByLocation(Loc(iob_loc.x, iob_loc.y, BelZ::IOBA_Z + 1 - (iob_loc.z - BelZ::IOBA_Z)));
@@ -486,6 +486,9 @@ struct GowinPacker
         ctx->bindBel(l_bel, &ci, PlaceStrength::STRENGTH_LOCKED);
         std::string out_mode;
         switch (ci.type.hash()) {
+        case ID_IOLOGICO_EMPTY:
+            out_mode = "EMPTY";
+            break;
         case ID_OVIDEO:
             out_mode = "VIDEORX";
             break;
@@ -494,11 +497,14 @@ struct GowinPacker
             break;
         }
         ci.setParam(ctx->id("OUTMODE"), out_mode);
-
         // disconnect Q output: it is wired internally
         nets_to_remove.push_back(ci.getPort(out_port)->name);
         out_iob->disconnectPort(id_I);
         ci.disconnectPort(out_port);
+        if (ci.type == id_IOLOGICO_EMPTY) {
+            ci.movePortTo(id_D, out_iob, id_I);
+            return;
+        }
         set_daaj_nets(ci, iob_bel);
 
         Loc io_loc = ctx->getBelLocation(iob_bel);
@@ -517,7 +523,8 @@ struct GowinPacker
 
     CellInfo *create_aux_iologic_cell(CellInfo &ci, IdString mode, bool io16 = false, int idx = 0)
     {
-        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4, id_IOLOGICI_EMPTY)) {
+        if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4, id_IOLOGICI_EMPTY,
+                       id_IOLOGICO_EMPTY)) {
             return nullptr;
         }
         IdString aux_name = gwu.create_aux_name(ci.name, idx);
@@ -618,21 +625,148 @@ struct GowinPacker
             break;
         }
         ci.setParam(ctx->id("INMODE"), in_mode);
-
-        if (ci.type == id_IOLOGICI_EMPTY) {
-            return;
-        }
-
         // disconnect D input: it is wired internally
         nets_to_remove.push_back(ci.getPort(in_port)->name);
         in_iob->disconnectPort(id_O);
         ci.disconnectPort(in_port);
+        if (ci.type == id_IOLOGICI_EMPTY) {
+            ci.movePortTo(id_Q, in_iob, id_O);
+            return;
+        }
+
         set_daaj_nets(ci, iob_bel);
         reconnect_ides_outs(&ci);
 
         make_iob_nets(*in_iob);
     }
 
+    void pack_iodelay()
+    {
+        log_info("Pack IODELAY...\n");
+        std::vector<IdString> cells_to_remove;
+        std::vector<IdString> nets_to_remove;
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (ci.type != id_IODELAY) {
+                continue;
+            }
+            if (ctx->debug) {
+                log_info("pack %s of type %s.\n", ctx->nameOf(&ci), ci.type.c_str(ctx));
+            }
+            // There is only one delay line in the IO block, which can be either
+            // input or output.  Define which case we are dealing with.
+            bool is_idelay = false;
+            NetInfo *di_net = ci.ports.at(id_DI).net;
+            NetInfo *do_net = ci.ports.at(id_DO).net;
+            CellInfo *iob = net_driven_by(ctx, di_net, is_iob, id_O);
+            if (iob != nullptr) {
+                NPNR_ASSERT(iob->bel != BelId());
+                if (di_net->users.entries() != 1) {
+                    log_error("IODELAY %s should be the only sink in the %s network.\n", ctx->nameOf(&ci),
+                              ctx->nameOf(di_net));
+                }
+                is_idelay = true;
+            } else {
+                iob = net_only_drives(ctx, do_net, is_iob, id_I, true);
+                if (iob != nullptr) {
+                    NPNR_ASSERT(iob->bel != BelId());
+                } else {
+                    log_error("IODELAY %s is not connected to the pin.\n", ctx->nameOf(&ci));
+                }
+            }
+
+            BelId iob_bel = iob->bel;
+            BelId l_bel = get_iologici_bel(iob);
+            if (l_bel == BelId()) {
+                log_error("Can't place IOLOGIC %s at %s\n", ctx->nameOf(&ci), ctx->nameOfBel(iob_bel));
+            }
+
+            // find IOLOGIC connected or create dummy one
+            CellInfo *iologic = nullptr;
+            Property attr;
+            IdString dummy_iol_type;
+            if (is_idelay) {
+                attr = Property("IN");
+                dummy_iol_type = id_IOLOGICI_EMPTY;
+                for (auto &usr : do_net->users) {
+                    if (is_iologici(usr.cell)) {
+                        iologic = usr.cell;
+                        if (iologic->attrs.count(id_IODELAY) != 0) {
+                            log_error("Only one IODELAY allowed per IO block %s.\n", ctx->nameOfBel(iob->bel));
+                        }
+                        if (ctx->debug) {
+                            log_info(" found IOLOGIC cell %s of type %s, use it.\n", ctx->nameOf(iologic),
+                                     iologic->type.c_str(ctx));
+                        }
+                    }
+                }
+            } else {
+                attr = Property("OUT");
+                dummy_iol_type = id_IOLOGICO_EMPTY;
+                if (is_iologico(di_net->driver.cell)) {
+                    iologic = di_net->driver.cell;
+                    if (iologic->attrs.count(id_IODELAY) != 0) {
+                        log_error("Only one IODELAY allowed per IO block %s.\n", ctx->nameOfBel(iob->bel));
+                    }
+                    if (ctx->debug) {
+                        log_info(" found IOLOGIC cell %s of type %s, use it.\n", ctx->nameOf(iologic),
+                                 iologic->type.c_str(ctx));
+                    }
+                }
+            }
+
+            if (iologic == nullptr) {
+                IdString iologic_name = gwu.create_aux_name(ci.name);
+                if (ctx->debug) {
+                    log_info(" create IOLOGIC cell %s.\n", iologic_name.c_str(ctx));
+                }
+                auto iologic_cell = gwu.create_cell(iologic_name, dummy_iol_type);
+                new_cells.push_back(std::move(iologic_cell));
+                iologic = new_cells.back().get();
+                iologic->addInput(id_D);
+                iologic->addOutput(id_Q);
+                ci.movePortTo(id_DI, iologic, id_D);
+                ci.movePortTo(id_DO, iologic, id_Q);
+            } else {
+                if (is_idelay) {
+                    iob->disconnectPort(id_O);
+                    ci.disconnectPort(id_I);
+                    ci.movePortTo(id_DO, iob, id_O);
+                } else {
+                    IdString iol_out = di_net->driver.port;
+                    ci.disconnectPort(id_DI);
+                    iologic->disconnectPort(iol_out);
+                    ci.movePortTo(id_DO, iologic, iol_out);
+                }
+                nets_to_remove.push_back(di_net->name);
+            }
+
+            ci.movePortTo(id_SDTAP, iologic, id_SDTAP);
+            ci.movePortTo(id_SETN, iologic, id_SETN);
+            ci.movePortTo(id_VALUE, iologic, id_VALUE);
+            ci.movePortTo(id_DF, iologic, id_DF);
+
+            if (ci.params.count(id_C_STATIC_DLY)) {
+                iologic->setParam(id_C_STATIC_DLY, ci.params.at(id_C_STATIC_DLY));
+            }
+            iologic->setAttr(id_IODELAY, attr);
+            cells_to_remove.push_back(ci.name);
+        }
+        for (auto cell : cells_to_remove) {
+            ctx->cells.erase(cell);
+        }
+
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+
+        for (auto net : nets_to_remove) {
+            ctx->nets.erase(net);
+        }
+    }
+
     void pack_iem()
     {
         log_info("Pack Input Edge Monitors...\n");
@@ -784,7 +918,7 @@ struct GowinPacker
                 create_aux_iologic_cell(ci, ctx->id("OUTMODE"));
                 continue;
             }
-            if (ci.type.in(id_OVIDEO, id_OSER10)) {
+            if (ci.type.in(id_OVIDEO, id_OSER10, id_IOLOGICO_EMPTY)) {
                 pack_single_output_iol(ci, nets_to_remove);
                 create_aux_iologic_cell(ci, ctx->id("OUTMODE"));
                 continue;
@@ -2332,8 +2466,9 @@ struct GowinPacker
                         ci->setParam(id_MULTALU18X18_MODE, 0);
                     }
                     int multalu18x18_mode = ci->params.at(id_MULTALU18X18_MODE).as_int64();
-                    NPNR_ASSERT_MSG(multalu18x18_mode >= 0 && multalu18x18_mode <= 2,
-                                    "MULTALU18X18_MODE is not in {0, 1, 2}");
+                    if (multalu18x18_mode < 0 || multalu18x18_mode > 2) {
+                        log_error("%s MULTALU18X18_MODE is not in {0, 1, 2}.\n", ctx->nameOf(ci));
+                    }
                     NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
 
                     for (int i = 0; i < 54; ++i) {
@@ -2436,8 +2571,9 @@ struct GowinPacker
                         ci->setParam(id_MULTALU18X18_MODE, 0);
                     }
                     int multalu36x18_mode = ci->params.at(id_MULTALU36X18_MODE).as_int64();
-                    NPNR_ASSERT_MSG(multalu36x18_mode >= 0 && multalu36x18_mode <= 2,
-                                    "MULTALU36X18_MODE is not in {0, 1, 2}");
+                    if (multalu36x18_mode < 0 || multalu36x18_mode > 2) {
+                        log_error("%s MULTALU36X18_MODE is not in {0, 1, 2}.\n", ctx->nameOf(ci));
+                    }
                     NetInfo *vss_net = ctx->nets.at(ctx->id("$PACKER_GND")).get();
 
                     for (int i = 0; i < 36; ++i) {
@@ -2539,8 +2675,9 @@ struct GowinPacker
                         ci->setParam(id_MULTADDALU18X18_MODE, 0);
                     }
                     int multaddalu18x18_mode = ci->params.at(id_MULTADDALU18X18_MODE).as_int64();
-                    NPNR_ASSERT_MSG(multaddalu18x18_mode >= 0 && multaddalu18x18_mode <= 2,
-                                    "MULTADDALU18X18_MODE is not in {0, 1, 2}");
+                    if (multaddalu18x18_mode < 0 || multaddalu18x18_mode > 2) {
+                        log_error("%s MULTADDALU18X18_MODE is not in {0, 1, 2}.\n", ctx->nameOf(ci));
+                    }
                     for (int i = 0; i < 54; ++i) {
                         if (i < 18) {
                             ci->renamePort(ctx->idf("A0[%d]", i), ctx->idf("A%d0", i));
@@ -3450,6 +3587,9 @@ struct GowinPacker
         pack_diff_iobs();
         ctx->check();
 
+        pack_iodelay();
+        ctx->check();
+
         pack_iem();
         ctx->check();
 

From 5a807110de045e5d3c16d878072f54f9e69421f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Wed, 4 Dec 2024 09:00:05 +0100
Subject: [PATCH 706/712] Adding NanoXplore NG-Ultra support (#1397)

* ng-ultra: new architecture

* Implementation as in D2 deliverable

* Support for nxdesignsuite-24.0.0.0-20240429T102300

* Save memory by directly outputing json

* Add support for bidirectional IOs

* cleanup

* Create BFRs properly

* Add IOM insertion

* Cleanup

* Block certain pips depending of DDFR mode

* Add LUT bypass to improve routability

* Add bypass for CSC mode of GCK

* Fix IOM case

* Initial memory support

* Better RF/XRF handling

* fix

* RF placement and legalization

* Disconnect non available ports for NX_RAM

* cleanup

* Add RFB/RAM context support for latest release

* Remove ports that must not be used

* Proper port used only on RFB

* Add structure for clock sinks

* Use cell type where applicable

* Add clock sinks for other cell types

* Validation check fixes

* Commented too restrictive placement

* Added more crossbar wire type

* Hande IO termination input

* Fail early due to NX tools limitation for now

* Validations and fixes for RAM I/Os

* Fix for latest version of tools

* Use ctx->idf where applicable

* warn if RAM ports are not actually used

* Fix IOM packing

* Fix CY packing

* Change how constants are handled on CY

* Post placement optimization for CY

* Address comments for PR

* pack and export  GCK, WFG and PLL

* Cover more global routing cases

* Constraing to location if provided

* Place at LOC

* Pack and export DSP

* wip

* wip

* notes

* wip

* wip

* Validate DSPs

* DSP cascading

* Check mandatory parameters for DSP

* existing gck

* wip

* export all the rest for bitstream

* CDC packing

* add more sinks

* place FIFO

* map rest of FIFO ports

* enable pll by default

* cleanup

* Initial XLUT support

* Fix statistics

* Properly duplicate GCKs

* RRSTO and WRSTO are not used on XFIFO

* Fix for latest version of JSON format

* Implement GCK limitations

* cleanup

* cleanup

* Add more signals and use lowskew name

* cleanup code a bit

* Fix wfb

* detect cascaded GCKs

* Handle DFR

* Route dfr clock properly

* Cleanup

* Cleanup bitstream code

* Review issues addressed

* Move helper routines

* Expose private members for unit tests

* cleanup

* remove scale factor

* make all location helper arrays static

* Addressed review comments

* Support post-routing CSC and SCC

* Support NX_BFF

* Place CSS and SCC only on allowed locations

* Support latest Impulse

* ng_ultra: Expand bounding box further for left-edge IO

Signed-off-by: gatecat <gatecat@ds0.me>

* Export all IO parameters in bitstream

* Handle new CSV order or parameters and additional validation

* Add some more undocumented values for CSV

* Support for old and new CSV formats

* Initial DDFR support

* Display warning message once per file

* Address review issues

* Fix crash on memory access

* Make boundbox fit NG-Ultra internal design

* Update attributes after dff rewrite

* Implement basic NG-Ultra LUT-DFF unit tests

* Always use first seen xbar input

Signed-off-by: gatecat <gatecat@ds0.me>

* Simplified crossbar pip detection

* Change order to prevent issues with some unconnected constants

* Pack LUT and multiple DFF in stripe

* Place DFF chains

* Improve large DFF chains

* Rename to pack_dff_chains

* Better use XLUTs when possible

* pack output DFF together with XLUT

* option to disable XLUT optimiziations

* Make more optimizations optional

* fix to use pre-increment

* GCK for lowskew signals

* Bugfix for nets that are not part of lowskew network

* Fix bitstream export for PLL cell

* Remove separate route lowskew

* Allow WFG mode 2

* Merge inverter into GCK

* Add CSC per TILE when needed

* Improve reusage of existing cell for CSC

* Take preferred CSC

* Cleanup

* When in place CSC size not important

* Cleanup

* Reset and Load restriction

* make csc optimisation optional

* Proper count for IO resources

* Detect when there is no next cell for DSP chain

* Do not incorporate loops in XLUT

* Check if output exists

* Update copyright for delivery

* Make building NG-Ultra chip database optional, follow filename convention

* Ported drawing code to new API

* Update expandBoundingBox for NG-Ultra

* Copyright and license update

* Add README information

* cleanup and constids

* Using ctx->idf where applicable

* remove if_using_basecluster

* refactor extra data usage

* refactor to use create_cell_ptr only

* optimized getCSC

* optimize critical path a bit

* clangformat

* disable clangformat where applicable

---------

Signed-off-by: gatecat <gatecat@ds0.me>
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Co-authored-by: gatecat <gatecat@ds0.me>
---
 CMakeLists.txt                             |    1 +
 README.md                                  |   13 +
 himbaechel/family.cmake                    |    8 +-
 himbaechel/uarch/ng-ultra/CMakeLists.txt   |   38 +
 himbaechel/uarch/ng-ultra/bitstream.cc     |  705 +++
 himbaechel/uarch/ng-ultra/cells.cc         |   84 +
 himbaechel/uarch/ng-ultra/constids.inc     | 6026 ++++++++++++++++++++
 himbaechel/uarch/ng-ultra/csv.cc           |  304 +
 himbaechel/uarch/ng-ultra/extra_data.h     |  265 +
 himbaechel/uarch/ng-ultra/gen/arch_gen.py  |  726 +++
 himbaechel/uarch/ng-ultra/location_map.cc  |  569 ++
 himbaechel/uarch/ng-ultra/location_map.h   |   43 +
 himbaechel/uarch/ng-ultra/ng_ultra.cc      | 1069 ++++
 himbaechel/uarch/ng-ultra/ng_ultra.h       |  126 +
 himbaechel/uarch/ng-ultra/pack.cc          | 2738 +++++++++
 himbaechel/uarch/ng-ultra/pack.h           |  131 +
 himbaechel/uarch/ng-ultra/tests/lut_dff.cc |  161 +
 himbaechel/uarch/ng-ultra/tests/main.cc    |   32 +
 18 files changed, 13038 insertions(+), 1 deletion(-)
 create mode 100644 himbaechel/uarch/ng-ultra/CMakeLists.txt
 create mode 100644 himbaechel/uarch/ng-ultra/bitstream.cc
 create mode 100644 himbaechel/uarch/ng-ultra/cells.cc
 create mode 100644 himbaechel/uarch/ng-ultra/constids.inc
 create mode 100644 himbaechel/uarch/ng-ultra/csv.cc
 create mode 100644 himbaechel/uarch/ng-ultra/extra_data.h
 create mode 100644 himbaechel/uarch/ng-ultra/gen/arch_gen.py
 create mode 100644 himbaechel/uarch/ng-ultra/location_map.cc
 create mode 100644 himbaechel/uarch/ng-ultra/location_map.h
 create mode 100644 himbaechel/uarch/ng-ultra/ng_ultra.cc
 create mode 100644 himbaechel/uarch/ng-ultra/ng_ultra.h
 create mode 100644 himbaechel/uarch/ng-ultra/pack.cc
 create mode 100644 himbaechel/uarch/ng-ultra/pack.h
 create mode 100644 himbaechel/uarch/ng-ultra/tests/lut_dff.cc
 create mode 100644 himbaechel/uarch/ng-ultra/tests/main.cc

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 40707d0ee6..2ae0b681ce 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -334,6 +334,7 @@ foreach (family ${ARCH})
 
     if (BUILD_TESTS)
         set(family_targets ${family_targets} ${PROGRAM_PREFIX}nextpnr-${family}-test)
+        set(family_test_targets ${PROGRAM_PREFIX}nextpnr-${family}-test)
     endif()
 
     # Include the family-specific CMakeFile
diff --git a/README.md b/README.md
index 8f3070f183..a5db81a21c 100644
--- a/README.md
+++ b/README.md
@@ -9,6 +9,7 @@ Currently nextpnr supports:
  * Lattice ECP5 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
  * Lattice Nexus devices supported by [Project Oxide](https://github.com/gatecat/prjoxide)
  * Gowin LittleBee devices supported by [Project Apicula](https://github.com/YosysHQ/apicula)
+ * NanoXplore NG-Ultra devices supported by [Project Beyond](https://github.com/yosyshq-GmbH/prjbeyond-db)
  * *(experimental)* Cyclone V devices supported by [Mistral](https://github.com/Ravenslofty/mistral)
  * *(experimental)* Lattice MachXO2 devices supported by [Project Trellis](https://github.com/YosysHQ/prjtrellis)
  * *(experimental)* a "generic" back-end for user-defined architectures
@@ -146,6 +147,18 @@ sudo make install
 
  - Examples of the Gowin flow for a range of boards can be found in the [Project Apicula Examples](https://github.com/YosysHQ/apicula/tree/master/examples).
 
+#### ng-ultra
+
+For NanoXplore NG-Ultra support, clone [Project Beyond DB](https://github.com/yosyshq-GmbH/prjbeyond-db) repo
+
+```
+cmake . -DARCH="himbaechel" -DHIMBAECHEL_PRJBEYOND_DB=/path/to/prjbeyond-db -DHIMBAECHEL_NGULTRA_DEVICES=ng-ultra
+make -j$(nproc)
+sudo make install
+```
+
+*Please note that binary bitstream creation requires Impulse tool from NanoXplore.*
+
 ### GUI
 
 The nextpnr GUI is not built by default, to reduce the number of dependencies for a standard headless build. To enable it, add `-DBUILD_GUI=ON` to the CMake command line and ensure that Qt5 and OpenGL are available:
diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake
index 88a52b339a..5061124d00 100644
--- a/himbaechel/family.cmake
+++ b/himbaechel/family.cmake
@@ -1,8 +1,14 @@
-set(HIMBAECHEL_UARCHES "example;gowin;xilinx")
+set(HIMBAECHEL_UARCHES "example;gowin;xilinx;ng-ultra")
 foreach(uarch ${HIMBAECHEL_UARCHES})
 	add_subdirectory(${family}/uarch/${uarch})
     aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES)
     foreach(target ${family_targets})
         target_sources(${target} PRIVATE ${HM_UARCH_FILES})
     endforeach()
+    if (BUILD_TESTS)
+        foreach(target ${family_test_targets})
+            aux_source_directory(${family}/uarch/${uarch}/tests/ HM_UARCH_TEST_FILES)
+            target_sources(${target} PRIVATE ${HM_UARCH_TEST_FILES})
+        endforeach()
+    endif()
 endforeach(uarch)
diff --git a/himbaechel/uarch/ng-ultra/CMakeLists.txt b/himbaechel/uarch/ng-ultra/CMakeLists.txt
new file mode 100644
index 0000000000..f3ed2589af
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/CMakeLists.txt
@@ -0,0 +1,38 @@
+message(STATUS "Configuring Himbaechel-NG-ULTRA uarch")
+cmake_minimum_required(VERSION 3.5)
+project(himbaechel-ng-ultra-chipdb NONE)
+
+set(ALL_HIMBAECHEL_NGULTRA_DEVICES ng-ultra)
+set(HIMBAECHEL_NGULTRA_DEVICES "" CACHE STRING
+    "Include support for these NG-Ultra devices (available: ${ALL_HIMBAECHEL_NGULTRA_DEVICES})")
+message(STATUS "Enabled Himbaechel-NG-Ultra devices: ${HIMBAECHEL_NGULTRA_DEVICES}")
+set(HIMBAECHEL_PRJBEYOND_DB "" CACHE STRING
+    "Path to a Project Beyond database")
+
+set(chipdb_binaries)
+file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/ng-ultra)
+foreach(device ${HIMBAECHEL_NGULTRA_DEVICES})
+	if("${HIMBAECHEL_PRJBEYOND_DB}" STREQUAL "")
+		message(SEND_ERROR "HIMBAECHEL_PRJBEYOND_DB must be set to a prjbeyond database checkout")
+	endif()
+
+	set(device_bba ${CMAKE_BINARY_DIR}/share/himbaechel/ng-ultra/chipdb-${device}.bba)
+	set(device_bin ${CMAKE_BINARY_DIR}/share/himbaechel/ng-ultra/chipdb-${device}.bin)
+	string(TOUPPER ${device} upcase_device)
+	add_custom_command(
+		OUTPUT ${device_bin}
+		COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen/arch_gen.py --db ${HIMBAECHEL_PRJBEYOND_DB} --device ${upcase_device} --bba ${device_bba}
+		COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${device_bba} ${device_bin}.new
+        # atomically update
+        COMMAND ${CMAKE_COMMAND} -E rename ${device_bin}.new ${device_bin}
+		DEPENDS
+			bbasm
+			${CMAKE_CURRENT_SOURCE_DIR}/gen/arch_gen.py
+			${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+		VERBATIM)
+	list(APPEND chipdb_binaries ${device_bin})
+endforeach()
+
+add_custom_target(chipdb-himbaechel-ng-ultra ALL DEPENDS ${chipdb_binaries})
+install(DIRECTORY ${CMAKE_BINARY_DIR}/share/himbaechel/ng-ultra/ DESTINATION share/nextpnr/himbaechel/ng-ultra
+	    PATTERN "*.bba" EXCLUDE)
diff --git a/himbaechel/uarch/ng-ultra/bitstream.cc b/himbaechel/uarch/ng-ultra/bitstream.cc
new file mode 100644
index 0000000000..145218a353
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/bitstream.cc
@@ -0,0 +1,705 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <boost/range/adaptor/reversed.hpp>
+
+#include <fstream>
+#include <regex>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "ng_ultra.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct BitstreamJsonBackend
+{
+    Context *ctx;
+    NgUltraImpl *uarch;
+    std::ostream &out;
+    bool first_instance;
+
+    BitstreamJsonBackend(Context *ctx, NgUltraImpl *uarch, std::ostream &out) : ctx(ctx), uarch(uarch), out(out) {};
+
+    std::string get_string(std::string str)
+    {
+        std::string newstr = "\"";
+        for (char c : str) {
+            if (c == '\\')
+                newstr += c;
+            newstr += c;
+        }
+        return newstr + "\"";
+    }
+
+    std::string update_name(std::string tile, std::string name)
+    {
+        if (boost::starts_with(tile, "FENCE[")) {
+            char last = tile[tile.size() - 2];
+            switch (last) {
+            case 'T':
+            case 'B':
+            case 'U':
+            case 'L':
+                std::string loc = tile.substr(tile.find("[") + 1, tile.find("x") - tile.find("["));
+                boost::replace_all(name, "1x", loc);
+                return name;
+            }
+        }
+        if (boost::starts_with(tile, "TILE[") && boost::algorithm::contains(name, ".FE")) {
+            std::string last = name.substr(name.rfind('.') + 1);
+            if (last[0] == 'D') {
+                boost::replace_all(name, ".D", ".");
+                boost::replace_all(name, ".FE", ".DFF");
+                return name;
+            }
+            if (last == "L" || last == "R") {
+                boost::replace_all(name, ".FE", ".DFF");
+                return name;
+            }
+            if (last == "CK") {
+                boost::replace_all(name, ".FE", ".DFF");
+                return name;
+            }
+            if (last[0] == 'L') {
+                boost::replace_all(name, ".L", ".");
+                boost::replace_all(name, ".FE", ".LUT");
+                return name;
+            }
+            if (last[0] == 'P') {
+                boost::replace_all(name, ".PI", ".I");
+                boost::replace_all(name, ".FE", ".LUT");
+                return name;
+            }
+        }
+        return name;
+    }
+
+    void add_net(std::set<std::string> &nets, std::string src_tile, std::string src_name, std::string dst_tile,
+                 std::string dst_name, IdString src_type, IdString dst_type)
+    {
+        if (src_type.in(ctx->id("LUT_PERMUTATION_WIRE"), ctx->id("MUX_WIRE"), ctx->id("INTERCONNECT_INPUT")))
+            return;
+        if (boost::starts_with(src_type.c_str(ctx), "CROSSBAR_") && boost::ends_with(src_type.c_str(ctx), "INPUT_WIRE"))
+            return;
+        if (dst_type == ctx->id("MUX_WIRE"))
+            dst_name = dst_name.substr(0, dst_name.rfind('.'));
+        src_name = update_name(src_tile, src_name);
+        dst_name = update_name(dst_tile, dst_name);
+
+        nets.emplace(stringf("%s:%s->%s:%s", src_tile.c_str(), src_name.c_str(), dst_tile.c_str(), dst_name.c_str()));
+    }
+
+    std::string cleanup_name(std::string name)
+    {
+        std::replace(name.begin(), name.end(), '$', '_');
+        return name;
+    }
+
+    void write_nets()
+    {
+        out << "\t\"nets\": {\n";
+        bool first_net = true;
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            if (ni->wires.empty())
+                continue;
+            out << (first_net ? "" : ",\n");
+            first_net = false;
+            out << stringf("\t\t%s: [\n", get_string(cleanup_name(ni->name.c_str(ctx))).c_str());
+            std::set<std::string> nets;
+            for (auto &w : ni->wires) {
+                if (w.second.pip != PipId()) {
+                    PipId pip = w.second.pip;
+                    auto &pd = chip_pip_info(ctx->chip_info, pip);
+                    const auto &extra_data = *uarch->pip_extra_data(pip);
+                    WireId swire = ctx->getPipSrcWire(pip);
+                    IdString src = ctx->getWireName(swire)[1];
+                    IdString src_type = ctx->getWireType(swire);
+
+                    IdString src_orig = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
+                    IdString src_orig_type =
+                            IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].wire_type);
+
+                    WireId dwire = ctx->getPipDstWire(pip);
+                    IdString dst = ctx->getWireName(dwire)[1];
+                    IdString dst_type = ctx->getWireType(dwire);
+
+                    std::string s_tile_name = uarch->tile_name(swire.tile);
+                    std::string tile_name = uarch->tile_name(pip.tile);
+
+                    if (src_orig != src)
+                        add_net(nets, s_tile_name, src.c_str(ctx), tile_name, src_orig.c_str(ctx), src_type,
+                                src_orig_type);
+                    if (!extra_data.name ||
+                        (extra_data.type != PipExtra::PIP_EXTRA_BYPASS &&
+                         extra_data.type != PipExtra::PIP_EXTRA_VIRTUAL && extra_data.type != PipExtra::PIP_EXTRA_MUX))
+                        add_net(nets, tile_name, src_orig.c_str(ctx), tile_name, dst.c_str(ctx), src_orig_type,
+                                dst_type);
+                } else if (ni->wires.size() == 1) {
+                    IdString src = ctx->getWireName(w.first)[1];
+                    IdString src_type = ctx->getWireType(w.first);
+                    std::string s_tile_name = uarch->tile_name(w.first.tile);
+                    for (auto &u : ni->users) {
+                        std::string tile_name = uarch->tile_name(u.cell->bel.tile);
+                        IdString bel_name = ctx->getBelName(u.cell->bel)[1];
+                        add_net(nets, s_tile_name, src.c_str(ctx), tile_name,
+                                stringf("%s.%s", bel_name.c_str(ctx), u.port.c_str(ctx)), src_type, src_type);
+                    }
+                }
+            }
+            bool first = true;
+            for (auto &str : nets) {
+                out << (first ? "" : ",\n");
+                out << stringf("\t\t\t%s", get_string(str).c_str());
+                first = false;
+            }
+            out << "\n\t\t]";
+        }
+        out << "\n\t},\n";
+    }
+
+    template <typename KeyType>
+    std::string str_or_n_value(const dict<KeyType, Property> &ct, const KeyType &key, std::string def = "N")
+    {
+        auto found = ct.find(key);
+        if (found == ct.end())
+            return def;
+        else {
+            if (!found->second.is_string)
+                log_error("Expecting string value but got integer %d.\n", int(found->second.intval));
+            if (found->second.as_string().empty())
+                return def;
+            return found->second.as_string();
+        }
+    };
+
+    template <typename KeyType>
+    std::string str_or_n_value_lower(const dict<KeyType, Property> &ct, const KeyType &key, std::string def = "N")
+    {
+        auto found = ct.find(key);
+        if (found == ct.end())
+            return def;
+        else {
+            if (!found->second.is_string)
+                log_error("Expecting string value but got integer %d.\n", int(found->second.intval));
+            if (found->second.as_string().empty())
+                return def;
+            std::string tmp = found->second.as_string();
+            boost::algorithm::to_lower(tmp);
+            return tmp;
+        }
+    };
+
+    template <typename KeyType>
+    std::string extract_bits_or_default(const dict<KeyType, Property> &ct, const KeyType &key, int bits, int def = 0)
+    {
+        Property extr = get_or_default(ct, key, Property()).extract(0, bits);
+        std::string str = extr.str;
+        std::reverse(str.begin(), str.end());
+        return str;
+    };
+
+    std::vector<std::string> config;
+
+    void open_instance(CellInfo *cell, std::string rename = "")
+    {
+        out << stringf("%s", first_instance ? "" : ",\n");
+        first_instance = false;
+        out << stringf("\t\t%s: {\n",
+                       get_string(cleanup_name(rename.empty() ? cell->name.c_str(ctx) : rename.c_str())).c_str());
+        std::string tile_name = uarch->tile_name(cell->bel.tile);
+        IdString idx = ctx->getBelName(cell->bel)[1];
+        std::string belname = idx.c_str(ctx);
+        config.clear();
+        out << stringf("\t\t\t\"location\": %s,\n", get_string(tile_name + ":" + belname).c_str());
+        out << stringf("\t\t\t\"type\": %s", get_string(cell->type.c_str(ctx)).c_str());
+    }
+
+    void open_instance_fe(CellInfo *cell, std::string type, std::string replace, std::string postfix = "")
+    {
+        out << stringf("%s", first_instance ? "" : ",\n");
+        first_instance = false;
+        out << stringf("\t\t%s: {\n", get_string(cleanup_name(cell->name.c_str(ctx)) + postfix).c_str());
+        std::string tile_name = uarch->tile_name(cell->bel.tile);
+        IdString idx = ctx->getBelName(cell->bel)[1];
+        std::string belname = idx.c_str(ctx);
+        boost::replace_all(belname, ".FE", replace);
+        config.clear();
+        out << stringf("\t\t\t\"location\": %s,\n", get_string(tile_name + ":" + belname).c_str());
+        out << stringf("\t\t\t\"type\": %s", get_string(type).c_str());
+    }
+
+    inline void add_config(std::string name, int val)
+    {
+        config.push_back(stringf("\t\t\t\t%s:%d", get_string(name).c_str(), val));
+    }
+
+    inline void add_config(std::string name, bool val)
+    {
+        config.push_back(stringf("\t\t\t\t%s:%s", get_string(name).c_str(), val ? "true" : "false"));
+    }
+
+    inline void add_config(std::string name, std::string val)
+    {
+        config.push_back(stringf("\t\t\t\t%s:%s", get_string(name).c_str(), get_string(val).c_str()));
+    }
+
+    void close_instance()
+    {
+        bool first = true;
+        if (!config.empty())
+            out << ",\n\t\t\t\"config\": {\n";
+        for (auto &str : config) {
+            out << (first ? "" : ",\n");
+            out << str.c_str();
+            first = false;
+        }
+        if (!config.empty())
+            out << "\n\t\t\t}";
+        out << "\n\t\t}";
+        config.clear();
+    }
+
+    void write_iop(CellInfo *cell)
+    {
+        open_instance(cell, str_or_default(cell->params, id_iobname, ""));
+        add_config("location", str_or_default(cell->params, id_location, ""));
+        add_config("differential", str_or_n_value_lower(cell->params, id_differential, "false"));
+        add_config("slewRate", str_or_default(cell->params, id_slewRate, "Medium"));
+        add_config("turbo", str_or_n_value_lower(cell->params, id_turbo, "false"));
+        add_config("weakTermination", str_or_n_value(cell->params, id_weakTermination, "PullUp"));
+        add_config("inputDelayLine", str_or_default(cell->params, id_inputDelayLine, "0"));
+        add_config("outputDelayLine", str_or_default(cell->params, id_outputDelayLine, "0"));
+        add_config("inputSignalSlope", str_or_default(cell->params, id_inputSignalSlope, "0"));
+        add_config("outputCapacity", str_or_default(cell->params, id_outputCapacity, "0"));
+        add_config("standard", str_or_default(cell->params, id_standard, "LVCMOS"));
+        add_config("drive", str_or_default(cell->params, id_drive, "2mA"));
+        add_config("inputDelayOn", str_or_n_value_lower(cell->params, id_inputDelayOn, "false"));
+        add_config("outputDelayOn", str_or_n_value_lower(cell->params, id_outputDelayOn, "false"));
+        add_config("dynDrive", str_or_n_value_lower(cell->params, id_dynDrive, "false"));
+        add_config("dynInput", str_or_n_value_lower(cell->params, id_dynInput, "false"));
+        add_config("dynTerm", str_or_n_value_lower(cell->params, id_dynTerm, "false"));
+        if (cell->type.in(id_OTP, id_ITP, id_IOTP)) {
+            add_config("termination", str_or_n_value(cell->params, id_termination, "0"));
+            add_config("terminationReference", str_or_n_value(cell->params, id_terminationReference, "VT"));
+        }
+        close_instance();
+        std::string tile_name = uarch->tile_name(cell->bel.tile);
+        std::string bank = tile_name.substr(0, tile_name.rfind(':'));
+        if (uarch->bank_voltage.count(bank) == 0) {
+            if (bank == "IOB0" || bank == "IOB1" || bank == "IOB6" || bank == "IOB7")
+                uarch->bank_voltage[bank] = "3.3V";
+            else
+                uarch->bank_voltage[bank] = "1.8V";
+        }
+    }
+
+    void write_ddfr(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
+        add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
+        add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
+        add_config("iobname", str_or_default(cell->params, id_iobname, ""));
+        add_config("path", int_or_default(cell->params, id_path, 0));
+        close_instance();
+    }
+
+    void write_dfr(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("data_inv", bool_or_default(cell->params, id_data_inv, false));
+        add_config("dff_edge", bool_or_default(cell->params, id_dff_edge, false));
+        add_config("dff_init", bool_or_default(cell->params, id_dff_init, false));
+        add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
+        add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
+        add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
+        add_config("mode", int_or_default(cell->params, id_mode, 3));
+        add_config("iobname", str_or_default(cell->params, id_iobname, ""));
+        close_instance();
+    }
+
+    void write_bfr(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("mode", int_or_default(cell->params, id_mode, 2));
+        add_config("iobname", str_or_default(cell->params, id_iobname, ""));
+        if (cell->params.count(id_data_inv)) {
+            add_config("data_inv", bool_or_default(cell->params, id_data_inv, false));
+        }
+        close_instance();
+    }
+
+    void write_cy(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("add_carry", int_or_default(cell->params, id_add_carry, 0));
+        add_config("shifter", bool_or_default(cell->params, id_shifter, false));
+        close_instance();
+    }
+
+    void write_fe(CellInfo *cell)
+    {
+        if (bool_or_default(cell->params, id_lut_used)) {
+            open_instance_fe(cell, "LUT", ".LUT");
+            add_config("lut_table", extract_bits_or_default(cell->params, id_lut_table, 16));
+            close_instance();
+        }
+        if (bool_or_default(cell->params, id_dff_used)) {
+            std::string subtype = str_or_default(cell->params, id_type, "DFF");
+            open_instance_fe(cell, subtype, ".DFF", "_D");
+            if (subtype == "DFF") {
+                add_config("dff_ctxt", std::to_string(int_or_default(cell->params, id_dff_ctxt, 0)));
+                add_config("dff_edge", bool_or_default(cell->params, id_dff_edge, false));
+                add_config("dff_init", bool_or_default(cell->params, id_dff_init, false));
+                add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
+                add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
+                add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
+            }
+            close_instance();
+        }
+    }
+
+    void write_xlut(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("lut_table", extract_bits_or_default(cell->params, id_lut_table, 16));
+        close_instance();
+    }
+
+    void write_iom(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("pads_path", str_or_default(cell->params, id_pads_path, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"));
+        close_instance();
+    }
+
+    void write_gck(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("inv_in", bool_or_default(cell->params, id_inv_in, false));
+        add_config("inv_out", bool_or_default(cell->params, id_inv_out, false));
+        add_config("std_mode", str_or_default(cell->params, id_std_mode, "BYPASS"));
+        close_instance();
+    }
+
+    void write_wfb(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("delay_on", bool_or_default(cell->params, id_delay_on, false));
+        add_config("delay", int_or_default(cell->params, id_delay, 0));
+        add_config("wfg_edge", bool_or_default(cell->params, id_wfg_edge, false));
+        close_instance();
+    }
+
+    void write_wfg(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("mode", int_or_default(cell->params, id_mode, 0));
+        add_config("delay_on", bool_or_default(cell->params, id_delay_on, false));
+        add_config("delay", int_or_default(cell->params, id_delay, 0));
+        add_config("wfg_edge", bool_or_default(cell->params, id_wfg_edge, false));
+        add_config("pattern", extract_bits_or_default(cell->params, id_pattern, 16));
+        add_config("pattern_end", int_or_default(cell->params, id_pattern_end, 0));
+        add_config("div_ratio", int_or_default(cell->params, id_div_ratio, 0));
+        add_config("div_phase", bool_or_default(cell->params, id_div_phase, false));
+        add_config("reset_on_pll_lock_n", bool_or_default(cell->params, id_reset_on_pll_lock_n, false));
+        add_config("reset_on_pll_locka_n", bool_or_default(cell->params, id_reset_on_pll_locka_n, false));
+        add_config("reset_on_cal_lock_n", bool_or_default(cell->params, id_reset_on_cal_lock_n, false));
+        close_instance();
+    }
+
+    void write_pll(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("clk_outdiv1", extract_bits_or_default(cell->params, id_clk_outdiv1, 3));
+        add_config("clk_outdiv2", extract_bits_or_default(cell->params, id_clk_outdiv2, 3));
+        add_config("clk_outdiv3", extract_bits_or_default(cell->params, id_clk_outdiv3, 3));
+        add_config("clk_outdiv4", extract_bits_or_default(cell->params, id_clk_outdiv4, 3));
+        add_config("clk_outdivd1", extract_bits_or_default(cell->params, id_clk_outdivd1, 4));
+        add_config("clk_outdivd2", extract_bits_or_default(cell->params, id_clk_outdivd2, 4));
+        add_config("clk_outdivd3", extract_bits_or_default(cell->params, id_clk_outdivd3, 4));
+        add_config("clk_outdivd4", extract_bits_or_default(cell->params, id_clk_outdivd4, 4));
+        add_config("clk_outdivd5", extract_bits_or_default(cell->params, id_clk_outdivd5, 4));
+        add_config("use_cal", bool_or_default(cell->params, id_use_cal, false));
+        add_config("clk_cal_sel", extract_bits_or_default(cell->params, id_clk_cal_sel, 2));
+        add_config("pll_odf", extract_bits_or_default(cell->params, id_pll_odf, 2));
+        add_config("pll_lpf_res", extract_bits_or_default(cell->params, id_pll_lpf_res, 4));
+        add_config("pll_lpf_cap", extract_bits_or_default(cell->params, id_pll_lpf_cap, 4));
+        add_config("cal_div", extract_bits_or_default(cell->params, id_cal_div, 4));
+        add_config("cal_delay", extract_bits_or_default(cell->params, id_cal_delay, 6));
+        add_config("use_pll", bool_or_default(cell->params, id_use_pll, true));
+        add_config("ref_intdiv", extract_bits_or_default(cell->params, id_ref_intdiv, 5));
+        add_config("ref_osc_on", bool_or_default(cell->params, id_ref_osc_on, false));
+        add_config("pll_cpump", extract_bits_or_default(cell->params, id_pll_cpump, 4));
+        add_config("pll_lock", extract_bits_or_default(cell->params, id_pll_lock, 4));
+        add_config("ext_fbk_on", bool_or_default(cell->params, id_ext_fbk_on, false));
+        add_config("fbk_intdiv", extract_bits_or_default(cell->params, id_fbk_intdiv, 7));
+        add_config("fbk_delay_on", bool_or_default(cell->params, id_fbk_delay_on, false));
+        add_config("fbk_delay", extract_bits_or_default(cell->params, id_fbk_delay, 6));
+        close_instance();
+    }
+
+    void write_rfb(CellInfo *cell)
+    {
+        open_instance(cell);
+        std::string context = str_or_default(cell->params, id_mem_ctxt, "");
+        if (!context.empty())
+            add_config("mem_ctxt", context);
+        add_config("wck_edge", bool_or_default(cell->params, id_wck_edge, false));
+        close_instance();
+    }
+
+    void write_ram(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("mcka_edge", bool_or_default(cell->params, id_mcka_edge, false));
+        add_config("mckb_edge", bool_or_default(cell->params, id_mckb_edge, false));
+        add_config("pcka_edge", bool_or_default(cell->params, id_pcka_edge, false));
+        add_config("pckb_edge", bool_or_default(cell->params, id_pckb_edge, false));
+        add_config("raw_config0", extract_bits_or_default(cell->params, id_raw_config0, 4));
+        add_config("raw_config1", extract_bits_or_default(cell->params, id_raw_config1, 16));
+        std::string context = str_or_default(cell->params, id_mem_ctxt, "");
+        if (!context.empty())
+            add_config("mem_ctxt", context);
+        close_instance();
+    }
+
+    void write_dsp(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("raw_config0", extract_bits_or_default(cell->params, id_raw_config0, 27));
+        add_config("raw_config1", extract_bits_or_default(cell->params, id_raw_config1, 24));
+        add_config("raw_config2", extract_bits_or_default(cell->params, id_raw_config2, 14));
+        add_config("raw_config3", extract_bits_or_default(cell->params, id_raw_config3, 3));
+        close_instance();
+    }
+
+    void write_cdc(CellInfo *cell)
+    {
+        open_instance(cell);
+        if (cell->type.in(id_DDE, id_TDE, id_CDC, id_XCDC)) {
+            add_config("ck0_edge", bool_or_default(cell->params, id_ck0_edge, false));
+            add_config("ck1_edge", bool_or_default(cell->params, id_ck1_edge, false));
+            add_config("ack_sel", bool_or_default(cell->params, id_ack_sel, false));
+            add_config("bck_sel", bool_or_default(cell->params, id_bck_sel, false));
+            add_config("use_adest_arst", bool_or_default(cell->params, id_use_adest_arst, false));
+            add_config("use_bdest_arst", bool_or_default(cell->params, id_use_bdest_arst, false));
+            if (cell->type != id_DDE) {
+                add_config("use_asrc_arst", bool_or_default(cell->params, id_use_asrc_arst, false));
+                add_config("use_bsrc_arst", bool_or_default(cell->params, id_use_bsrc_arst, false));
+            }
+            if (cell->type == id_XCDC) {
+                add_config("cck_sel", bool_or_default(cell->params, id_cck_sel, false));
+                add_config("dck_sel", bool_or_default(cell->params, id_dck_sel, false));
+                add_config("use_csrc_arst", bool_or_default(cell->params, id_use_csrc_arst, false));
+                add_config("use_dsrc_arst", bool_or_default(cell->params, id_use_dsrc_arst, false));
+                add_config("use_cdest_arst", bool_or_default(cell->params, id_use_cdest_arst, false));
+                add_config("use_ddest_arst", bool_or_default(cell->params, id_use_ddest_arst, false));
+                add_config("link_BA", bool_or_default(cell->params, id_link_BA, false));
+                add_config("link_CB", bool_or_default(cell->params, id_link_CB, false));
+                add_config("link_DC", bool_or_default(cell->params, id_link_DC, false));
+            }
+        }
+        close_instance();
+    }
+
+    void write_fifo(CellInfo *cell)
+    {
+        open_instance(cell);
+        add_config("rck_edge", bool_or_default(cell->params, id_rck_edge, false));
+        add_config("wck_edge", bool_or_default(cell->params, id_wck_edge, false));
+        if (cell->type != id_FIFO) {
+            add_config("use_read_arst", bool_or_default(cell->params, id_use_read_arst, false));
+            add_config("use_write_arst", bool_or_default(cell->params, id_use_write_arst, false));
+        }
+        add_config("read_addr_inv", extract_bits_or_default(cell->params, id_read_addr_inv, 7));
+        close_instance();
+    }
+
+    void write_interconnections()
+    {
+        for (auto &net : ctx->nets) {
+            NetInfo *ni = net.second.get();
+            if (ni->wires.size() == 0)
+                continue;
+            std::vector<std::string> nets;
+            for (auto &w : ni->wires) {
+                if (w.second.pip != PipId()) {
+                    PipId pip = w.second.pip;
+                    const auto &extra_data = *uarch->pip_extra_data(w.second.pip);
+                    if (!extra_data.name || extra_data.type != PipExtra::PIP_EXTRA_INTERCONNECT)
+                        continue;
+                    auto &pd = chip_pip_info(ctx->chip_info, pip);
+                    IdString src = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
+                    std::string tile_name = uarch->tile_name(pip.tile);
+                    std::string src_name = src.c_str(ctx);
+                    std::string type = "OTC";
+                    if (src_name.find("UI1x") != std::string::npos)
+                        type = "ITC";
+                    if (boost::starts_with(src_name, "SO1."))
+                        type = "OTS";
+                    if (boost::starts_with(src_name, "SI1."))
+                        type = "ITS";
+                    src_name = update_name(tile_name, src_name);
+                    src_name = src_name.substr(0, src_name.size() - 2);
+
+                    std::string name = cleanup_name(std::string(ni->name.c_str(ctx)) + "_" + src_name.substr(4));
+                    out << stringf(",\n\t\t%s: {\n", get_string(name).c_str());
+                    out << stringf("\t\t\t\"location\": %s,\n", get_string(tile_name + ":" + src_name).c_str());
+                    out << stringf("\t\t\t\"type\": %s\n\t\t}", get_string(type).c_str());
+                }
+            }
+        }
+    }
+
+    void write_instances()
+    {
+        out << "\t\"instances\": {\n";
+        first_instance = true;
+        for (auto &cell : ctx->cells) {
+            switch (cell.second->type.index) {
+            case id_BEYOND_FE.index:
+                write_fe(cell.second.get());
+                break;
+            case id_IOP.index:
+            case id_IP.index:
+            case id_OP.index:
+            case id_IOTP.index:
+            case id_ITP.index:
+            case id_OTP.index:
+                write_iop(cell.second.get());
+                break;
+            case id_CY.index:
+                write_cy(cell.second.get());
+                break;
+            case id_WFB.index:
+                write_wfb(cell.second.get());
+                break;
+            case id_WFG.index:
+                write_wfg(cell.second.get());
+                break;
+            case id_GCK.index:
+                write_gck(cell.second.get());
+                break;
+            case id_IOM.index:
+                write_iom(cell.second.get());
+                break;
+            case id_BFR.index:
+                write_bfr(cell.second.get());
+                break;
+            case id_DDFR.index:
+                write_ddfr(cell.second.get());
+                break;
+            case id_DFR.index:
+                write_dfr(cell.second.get());
+                break;
+            case id_RAM.index:
+                write_ram(cell.second.get());
+                break;
+            case id_RF.index:
+            case id_RFSP.index:
+            case id_XHRF.index:
+            case id_XWRF.index:
+            case id_XPRF.index:
+                write_rfb(cell.second.get());
+                break;
+            case id_XLUT.index:
+                write_xlut(cell.second.get());
+                break;
+            case id_FIFO.index:   // mode 0
+            case id_XHFIFO.index: // mode 1
+            case id_XWFIFO.index:
+                write_fifo(cell.second.get());
+                break;         // mode 2
+            case id_DDE.index: // mode 0
+            case id_TDE.index: // mode 1
+            case id_CDC.index: // mode 2
+            case id_BGC.index: // mode 3
+            case id_GBC.index: // mode 4
+            case id_XCDC.index:
+                write_cdc(cell.second.get());
+                break; // mode 5
+            case id_DSP.index:
+                write_dsp(cell.second.get());
+                break;
+            case id_PLL.index:
+                write_pll(cell.second.get());
+                break;
+            // case id_CRX.index:
+            // case id_CTX.index:
+            // case id_PMA.index:
+            // case id_Service.index:
+            // case id_SOCIF.index:
+            default:
+                log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx),
+                          cell.second->type.c_str(ctx));
+            }
+        }
+        write_interconnections();
+        out << "\n\t},\n";
+    }
+
+    void write_setup()
+    {
+        out << "\t\"setup\": {\n";
+        out << "\t\t\"variant\": \"NG-ULTRA\",\n";
+        out << "\t\t\"iobanks\": {\n";
+        bool first = true;
+        for (auto &bank : uarch->bank_voltage) {
+            out << (first ? "" : ",\n");
+            out << stringf("\t\t\t%s:%s", get_string(bank.first).c_str(), get_string(bank.second).c_str());
+            first = false;
+        }
+        out << "\n\t\t}\n\t}\n";
+    }
+
+    void write_json()
+    {
+        out << "{\n";
+        write_nets();
+        write_instances();
+        write_setup();
+        out << "}\n";
+    }
+};
+
+} // namespace
+
+void NgUltraImpl::write_bitstream_json(const std::string &filename)
+{
+    std::ofstream out(filename);
+    if (!out)
+        log_error("failed to open file %s for writing (%s)\n", filename.c_str(), strerror(errno));
+
+    BitstreamJsonBackend be(ctx, this, out);
+    be.write_json();
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/cells.cc b/himbaechel/uarch/ng-ultra/cells.cc
new file mode 100644
index 0000000000..322dacb03f
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/cells.cc
@@ -0,0 +1,84 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+#include "pack.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+CellInfo *NgUltraPacker::create_cell_ptr(IdString type, IdString name)
+{
+    CellInfo *cell = ctx->createCell(name, type);
+
+    auto add_port = [&](const IdString id, PortType dir) {
+        cell->ports[id].name = id;
+        cell->ports[id].type = dir;
+    };
+    if (type == id_BEYOND_FE) {
+        add_port(id_I1, PORT_IN);
+        add_port(id_I2, PORT_IN);
+        add_port(id_I3, PORT_IN);
+        add_port(id_I4, PORT_IN);
+        add_port(id_LO, PORT_OUT);
+        add_port(id_DI, PORT_IN);
+        add_port(id_L, PORT_IN);
+        add_port(id_CK, PORT_IN);
+        add_port(id_R, PORT_IN);
+        add_port(id_DO, PORT_OUT);
+    } else if (type == id_BFR) {
+        add_port(id_I, PORT_IN);
+        add_port(id_O, PORT_OUT);
+    } else if (type == id_DFR) {
+        add_port(id_I, PORT_IN);
+        add_port(id_O, PORT_OUT);
+        add_port(id_L, PORT_IN);
+        add_port(id_CK, PORT_IN);
+        add_port(id_R, PORT_IN);
+    } else if (type == id_DDFR) {
+        add_port(id_I, PORT_IN);
+        add_port(id_O, PORT_OUT);
+        add_port(id_L, PORT_IN);
+        add_port(id_CK, PORT_IN);
+        add_port(id_R, PORT_IN);
+        add_port(id_I2, PORT_IN);
+        add_port(id_O2, PORT_OUT);
+        add_port(id_CKF, PORT_IN);
+    } else if (type == id_IOM) {
+        add_port(id_P17RI, PORT_IN);
+        add_port(id_CKO1, PORT_OUT);
+        add_port(id_P19RI, PORT_IN);
+        add_port(id_CKO2, PORT_OUT);
+    } else if (type == id_WFB) {
+        add_port(id_ZI, PORT_IN);
+        add_port(id_ZO, PORT_OUT);
+    } else if (type == id_GCK) {
+        add_port(id_SI1, PORT_IN);
+        add_port(id_SI2, PORT_IN);
+        add_port(id_CMD, PORT_IN);
+        add_port(id_SO, PORT_OUT);
+    } else {
+        log_error("Trying to create unknown cell type %s\n", type.c_str(ctx));
+    }
+    return cell;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/constids.inc b/himbaechel/uarch/ng-ultra/constids.inc
new file mode 100644
index 0000000000..c091c71050
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/constids.inc
@@ -0,0 +1,6026 @@
+// autogenerated items
+// BEYOND_FE
+X(BEYOND_FE)
+X(CK)
+X(DC)
+X(DI)
+X(DJ)
+X(DK)
+X(DO)
+X(DP)
+X(DS)
+X(I1)
+X(I2)
+X(I3)
+X(I4)
+X(L)
+X(LD)
+X(LJ)
+X(LK)
+X(LO)
+X(LX)
+X(R)
+
+// BFF
+X(BFF)
+X(C)
+X(I)
+X(J)
+X(K)
+X(O)
+X(P)
+X(S)
+
+// BFR
+X(BFR)
+//X(I)
+//X(O)
+
+// BGC
+X(BGC)
+X(AI1)
+X(AI2)
+X(AI3)
+X(AI4)
+X(AI5)
+X(AI6)
+X(AO1)
+X(AO2)
+X(AO3)
+X(AO4)
+X(AO5)
+X(AO6)
+X(BI1)
+X(BI2)
+X(BI3)
+X(BI4)
+X(BI5)
+X(BI6)
+X(BO1)
+X(BO2)
+X(BO3)
+X(BO4)
+X(BO5)
+X(BO6)
+
+// CDC
+X(CDC)
+X(ADRSTI)
+X(ADRSTO)
+//X(AI1)
+//X(AI2)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+//X(AO1)
+//X(AO2)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+X(ASRSTI)
+X(ASRSTO)
+X(BDRSTI)
+X(BDRSTO)
+//X(BI1)
+//X(BI2)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+//X(BO1)
+//X(BO2)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+X(BSRSTI)
+X(BSRSTO)
+X(CK1)
+X(CK2)
+
+// CRX
+X(CRX)
+X(ALIGN_E_I)
+X(ALIGN_O)
+X(ALIGN_S_I)
+X(BUF_R_I)
+X(BUSY_O)
+X(CH_A_O1)
+X(CH_A_O2)
+X(CH_A_O3)
+X(CH_A_O4)
+X(CH_A_O5)
+X(CH_A_O6)
+X(CH_A_O7)
+X(CH_A_O8)
+X(CH_COM_O1)
+X(CH_COM_O2)
+X(CH_COM_O3)
+X(CH_COM_O4)
+X(CH_COM_O5)
+X(CH_COM_O6)
+X(CH_COM_O7)
+X(CH_COM_O8)
+X(CH_F_O1)
+X(CH_F_O2)
+X(CH_F_O3)
+X(CH_F_O4)
+X(CH_F_O5)
+X(CH_F_O6)
+X(CH_F_O7)
+X(CH_F_O8)
+X(CH_K_O1)
+X(CH_K_O2)
+X(CH_K_O3)
+X(CH_K_O4)
+X(CH_K_O5)
+X(CH_K_O6)
+X(CH_K_O7)
+X(CH_K_O8)
+X(DATA_O1)
+X(DATA_O10)
+X(DATA_O11)
+X(DATA_O12)
+X(DATA_O13)
+X(DATA_O14)
+X(DATA_O15)
+X(DATA_O16)
+X(DATA_O17)
+X(DATA_O18)
+X(DATA_O19)
+X(DATA_O2)
+X(DATA_O20)
+X(DATA_O21)
+X(DATA_O22)
+X(DATA_O23)
+X(DATA_O24)
+X(DATA_O25)
+X(DATA_O26)
+X(DATA_O27)
+X(DATA_O28)
+X(DATA_O29)
+X(DATA_O3)
+X(DATA_O30)
+X(DATA_O31)
+X(DATA_O32)
+X(DATA_O33)
+X(DATA_O34)
+X(DATA_O35)
+X(DATA_O36)
+X(DATA_O37)
+X(DATA_O38)
+X(DATA_O39)
+X(DATA_O4)
+X(DATA_O40)
+X(DATA_O41)
+X(DATA_O42)
+X(DATA_O43)
+X(DATA_O44)
+X(DATA_O45)
+X(DATA_O46)
+X(DATA_O47)
+X(DATA_O48)
+X(DATA_O49)
+X(DATA_O5)
+X(DATA_O50)
+X(DATA_O51)
+X(DATA_O52)
+X(DATA_O53)
+X(DATA_O54)
+X(DATA_O55)
+X(DATA_O56)
+X(DATA_O57)
+X(DATA_O58)
+X(DATA_O59)
+X(DATA_O6)
+X(DATA_O60)
+X(DATA_O61)
+X(DATA_O62)
+X(DATA_O63)
+X(DATA_O64)
+X(DATA_O7)
+X(DATA_O8)
+X(DATA_O9)
+X(DBG_S_I1)
+X(DBG_S_I2)
+X(DBG_S_I3)
+X(DEC_E_I)
+X(DSCR_E_I)
+X(D_ERR_O1)
+X(D_ERR_O2)
+X(D_ERR_O3)
+X(D_ERR_O4)
+X(D_ERR_O5)
+X(D_ERR_O6)
+X(D_ERR_O7)
+X(D_ERR_O8)
+X(LINK)
+X(LL_FLOCK_O)
+X(LL_SLOCK_O)
+X(LOS_O)
+X(MEYE_RST_I)
+X(NIT_O1)
+X(NIT_O2)
+X(NIT_O3)
+X(NIT_O4)
+X(NIT_O5)
+X(NIT_O6)
+X(NIT_O7)
+X(NIT_O8)
+X(OVS_BS_I1)
+X(OVS_BS_I2)
+X(PLL_LOCKT_O)
+X(PLL_LOCK_O)
+X(PMA_RSTN_I)
+X(PWDN_N_I)
+X(REP_E_I)
+X(RST_N_I)
+X(TST_O1)
+X(TST_O2)
+X(TST_O3)
+X(TST_O4)
+X(TST_O5)
+X(TST_O6)
+X(TST_O7)
+X(TST_O8)
+X(VREALIGN_O)
+
+// CSC
+X(CSC)
+//X(C)
+//X(I)
+//X(J)
+//X(K)
+//X(O)
+//X(P)
+//X(S)
+
+// CTX
+X(CTX)
+//X(BUSY_O)
+X(CH_K_I1)
+X(CH_K_I2)
+X(CH_K_I3)
+X(CH_K_I4)
+X(CH_K_I5)
+X(CH_K_I6)
+X(CH_K_I7)
+X(CH_K_I8)
+X(CLK_E_I)
+X(CLK_O)
+X(DATA_I1)
+X(DATA_I10)
+X(DATA_I11)
+X(DATA_I12)
+X(DATA_I13)
+X(DATA_I14)
+X(DATA_I15)
+X(DATA_I16)
+X(DATA_I17)
+X(DATA_I18)
+X(DATA_I19)
+X(DATA_I2)
+X(DATA_I20)
+X(DATA_I21)
+X(DATA_I22)
+X(DATA_I23)
+X(DATA_I24)
+X(DATA_I25)
+X(DATA_I26)
+X(DATA_I27)
+X(DATA_I28)
+X(DATA_I29)
+X(DATA_I3)
+X(DATA_I30)
+X(DATA_I31)
+X(DATA_I32)
+X(DATA_I33)
+X(DATA_I34)
+X(DATA_I35)
+X(DATA_I36)
+X(DATA_I37)
+X(DATA_I38)
+X(DATA_I39)
+X(DATA_I4)
+X(DATA_I40)
+X(DATA_I41)
+X(DATA_I42)
+X(DATA_I43)
+X(DATA_I44)
+X(DATA_I45)
+X(DATA_I46)
+X(DATA_I47)
+X(DATA_I48)
+X(DATA_I49)
+X(DATA_I5)
+X(DATA_I50)
+X(DATA_I51)
+X(DATA_I52)
+X(DATA_I53)
+X(DATA_I54)
+X(DATA_I55)
+X(DATA_I56)
+X(DATA_I57)
+X(DATA_I58)
+X(DATA_I59)
+X(DATA_I6)
+X(DATA_I60)
+X(DATA_I61)
+X(DATA_I62)
+X(DATA_I63)
+X(DATA_I64)
+X(DATA_I7)
+X(DATA_I8)
+X(DATA_I9)
+X(ENC_E_I1)
+X(ENC_E_I2)
+X(ENC_E_I3)
+X(ENC_E_I4)
+X(ENC_E_I5)
+X(ENC_E_I6)
+X(ENC_E_I7)
+X(ENC_E_I8)
+X(EOF_I1)
+X(EOF_I2)
+X(EOF_I3)
+X(EOF_I4)
+X(EOF_I5)
+X(EOF_I6)
+X(EOF_I7)
+X(EOF_I8)
+X(EOMF_I1)
+X(EOMF_I2)
+X(EOMF_I3)
+X(EOMF_I4)
+X(EOMF_I5)
+X(EOMF_I6)
+X(EOMF_I7)
+X(EOMF_I8)
+X(INV_K_O)
+//X(LINK)
+//X(PWDN_N_I)
+//X(REP_E_I)
+//X(RST_N_I)
+X(SCR_E_I1)
+X(SCR_E_I2)
+X(SCR_E_I3)
+X(SCR_E_I4)
+X(SCR_E_I5)
+X(SCR_E_I6)
+X(SCR_E_I7)
+X(SCR_E_I8)
+
+// CY
+X(CY)
+X(A1)
+X(A2)
+X(A3)
+X(A4)
+X(B1)
+X(B2)
+X(B3)
+X(B4)
+X(CI)
+X(CO)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+X(O1)
+X(O2)
+X(O3)
+X(O4)
+X(S1)
+X(S2)
+X(S3)
+X(S4)
+
+// DDE
+X(DDE)
+//X(ADRSTI)
+//X(ADRSTO)
+//X(AI1)
+//X(AI2)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+//X(AO1)
+//X(AO2)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+//X(BDRSTI)
+//X(BDRSTO)
+//X(BI1)
+//X(BI2)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+//X(BO1)
+//X(BO2)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+//X(CK1)
+//X(CK2)
+
+// DDFR
+X(DDFR)
+//X(CK)
+X(CKF)
+//X(I)
+//X(I2)
+//X(L)
+//X(O)
+//X(O2)
+//X(R)
+
+// DFF
+X(DFF)
+//X(C)
+//X(CK)
+//X(I)
+//X(J)
+//X(K)
+//X(L)
+//X(O)
+//X(P)
+//X(R)
+//X(S)
+
+// DFR
+X(DFR)
+//X(CK)
+//X(I)
+//X(L)
+//X(O)
+//X(R)
+
+// DSP
+X(DSP)
+//X(A1)
+X(A10)
+X(A11)
+X(A12)
+X(A13)
+X(A14)
+X(A15)
+X(A16)
+X(A17)
+X(A18)
+X(A19)
+//X(A2)
+X(A20)
+X(A21)
+X(A22)
+X(A23)
+X(A24)
+//X(A3)
+//X(A4)
+X(A5)
+X(A6)
+X(A7)
+X(A8)
+X(A9)
+//X(B1)
+X(B10)
+X(B11)
+X(B12)
+X(B13)
+X(B14)
+X(B15)
+X(B16)
+X(B17)
+X(B18)
+//X(B2)
+//X(B3)
+//X(B4)
+X(B5)
+X(B6)
+X(B7)
+X(B8)
+X(B9)
+X(C1)
+X(C10)
+X(C11)
+X(C12)
+X(C13)
+X(C14)
+X(C15)
+X(C16)
+X(C17)
+X(C18)
+X(C19)
+X(C2)
+X(C20)
+X(C21)
+X(C22)
+X(C23)
+X(C24)
+X(C25)
+X(C26)
+X(C27)
+X(C28)
+X(C29)
+X(C3)
+X(C30)
+X(C31)
+X(C32)
+X(C33)
+X(C34)
+X(C35)
+X(C36)
+X(C4)
+X(C5)
+X(C6)
+X(C7)
+X(C8)
+X(C9)
+X(CAI1)
+X(CAI10)
+X(CAI11)
+X(CAI12)
+X(CAI13)
+X(CAI14)
+X(CAI15)
+X(CAI16)
+X(CAI17)
+X(CAI18)
+X(CAI19)
+X(CAI2)
+X(CAI20)
+X(CAI21)
+X(CAI22)
+X(CAI23)
+X(CAI24)
+X(CAI3)
+X(CAI4)
+X(CAI5)
+X(CAI6)
+X(CAI7)
+X(CAI8)
+X(CAI9)
+X(CAO1)
+X(CAO10)
+X(CAO11)
+X(CAO12)
+X(CAO13)
+X(CAO14)
+X(CAO15)
+X(CAO16)
+X(CAO17)
+X(CAO18)
+X(CAO19)
+X(CAO2)
+X(CAO20)
+X(CAO21)
+X(CAO22)
+X(CAO23)
+X(CAO24)
+X(CAO3)
+X(CAO4)
+X(CAO5)
+X(CAO6)
+X(CAO7)
+X(CAO8)
+X(CAO9)
+X(CBI1)
+X(CBI10)
+X(CBI11)
+X(CBI12)
+X(CBI13)
+X(CBI14)
+X(CBI15)
+X(CBI16)
+X(CBI17)
+X(CBI18)
+X(CBI2)
+X(CBI3)
+X(CBI4)
+X(CBI5)
+X(CBI6)
+X(CBI7)
+X(CBI8)
+X(CBI9)
+X(CBO1)
+X(CBO10)
+X(CBO11)
+X(CBO12)
+X(CBO13)
+X(CBO14)
+X(CBO15)
+X(CBO16)
+X(CBO17)
+X(CBO18)
+X(CBO2)
+X(CBO3)
+X(CBO4)
+X(CBO5)
+X(CBO6)
+X(CBO7)
+X(CBO8)
+X(CBO9)
+X(CCI)
+X(CCO)
+//X(CI)
+//X(CK)
+X(CO43)
+X(CO57)
+X(CZI1)
+X(CZI10)
+X(CZI11)
+X(CZI12)
+X(CZI13)
+X(CZI14)
+X(CZI15)
+X(CZI16)
+X(CZI17)
+X(CZI18)
+X(CZI19)
+X(CZI2)
+X(CZI20)
+X(CZI21)
+X(CZI22)
+X(CZI23)
+X(CZI24)
+X(CZI25)
+X(CZI26)
+X(CZI27)
+X(CZI28)
+X(CZI29)
+X(CZI3)
+X(CZI30)
+X(CZI31)
+X(CZI32)
+X(CZI33)
+X(CZI34)
+X(CZI35)
+X(CZI36)
+X(CZI37)
+X(CZI38)
+X(CZI39)
+X(CZI4)
+X(CZI40)
+X(CZI41)
+X(CZI42)
+X(CZI43)
+X(CZI44)
+X(CZI45)
+X(CZI46)
+X(CZI47)
+X(CZI48)
+X(CZI49)
+X(CZI5)
+X(CZI50)
+X(CZI51)
+X(CZI52)
+X(CZI53)
+X(CZI54)
+X(CZI55)
+X(CZI56)
+X(CZI6)
+X(CZI7)
+X(CZI8)
+X(CZI9)
+X(CZO1)
+X(CZO10)
+X(CZO11)
+X(CZO12)
+X(CZO13)
+X(CZO14)
+X(CZO15)
+X(CZO16)
+X(CZO17)
+X(CZO18)
+X(CZO19)
+X(CZO2)
+X(CZO20)
+X(CZO21)
+X(CZO22)
+X(CZO23)
+X(CZO24)
+X(CZO25)
+X(CZO26)
+X(CZO27)
+X(CZO28)
+X(CZO29)
+X(CZO3)
+X(CZO30)
+X(CZO31)
+X(CZO32)
+X(CZO33)
+X(CZO34)
+X(CZO35)
+X(CZO36)
+X(CZO37)
+X(CZO38)
+X(CZO39)
+X(CZO4)
+X(CZO40)
+X(CZO41)
+X(CZO42)
+X(CZO43)
+X(CZO44)
+X(CZO45)
+X(CZO46)
+X(CZO47)
+X(CZO48)
+X(CZO49)
+X(CZO5)
+X(CZO50)
+X(CZO51)
+X(CZO52)
+X(CZO53)
+X(CZO54)
+X(CZO55)
+X(CZO56)
+X(CZO6)
+X(CZO7)
+X(CZO8)
+X(CZO9)
+X(D1)
+X(D10)
+X(D11)
+X(D12)
+X(D13)
+X(D14)
+X(D15)
+X(D16)
+X(D17)
+X(D18)
+X(D2)
+X(D3)
+X(D4)
+X(D5)
+X(D6)
+X(D7)
+X(D8)
+X(D9)
+X(OVF)
+//X(R)
+X(RESERVED)
+X(RZ)
+X(WE)
+X(WEZ)
+X(Z1)
+X(Z10)
+X(Z11)
+X(Z12)
+X(Z13)
+X(Z14)
+X(Z15)
+X(Z16)
+X(Z17)
+X(Z18)
+X(Z19)
+X(Z2)
+X(Z20)
+X(Z21)
+X(Z22)
+X(Z23)
+X(Z24)
+X(Z25)
+X(Z26)
+X(Z27)
+X(Z28)
+X(Z29)
+X(Z3)
+X(Z30)
+X(Z31)
+X(Z32)
+X(Z33)
+X(Z34)
+X(Z35)
+X(Z36)
+X(Z37)
+X(Z38)
+X(Z39)
+X(Z4)
+X(Z40)
+X(Z41)
+X(Z42)
+X(Z43)
+X(Z44)
+X(Z45)
+X(Z46)
+X(Z47)
+X(Z48)
+X(Z49)
+X(Z5)
+X(Z50)
+X(Z51)
+X(Z52)
+X(Z53)
+X(Z54)
+X(Z55)
+X(Z56)
+X(Z6)
+X(Z7)
+X(Z8)
+X(Z9)
+
+// FCI
+X(FCI)
+//X(I)
+//X(O)
+
+// FCO
+X(FCO)
+//X(I)
+//X(O)
+
+// FIFO
+X(FIFO)
+//X(I1)
+X(I10)
+X(I11)
+X(I12)
+X(I13)
+X(I14)
+X(I15)
+X(I16)
+X(I17)
+X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+X(I5)
+X(I6)
+X(I7)
+X(I8)
+X(I9)
+//X(O1)
+X(O10)
+X(O11)
+X(O12)
+X(O13)
+X(O14)
+X(O15)
+X(O16)
+X(O17)
+X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+X(O5)
+X(O6)
+X(O7)
+X(O8)
+X(O9)
+X(RAI1)
+X(RAI2)
+X(RAI3)
+X(RAI4)
+X(RAI5)
+X(RAI6)
+X(RAO1)
+X(RAO2)
+X(RAO3)
+X(RAO4)
+X(RAO5)
+X(RAO6)
+X(RCK)
+X(REQ)
+X(RRSTI1)
+X(RRSTI2)
+X(RRSTO)
+X(WAI1)
+X(WAI2)
+X(WAI3)
+X(WAI4)
+X(WAI5)
+X(WAI6)
+X(WAO1)
+X(WAO2)
+X(WAO3)
+X(WAO4)
+X(WAO5)
+X(WAO6)
+X(WCK)
+//X(WE)
+X(WEA)
+X(WEQ)
+X(WRSTI1)
+X(WRSTI2)
+X(WRSTO)
+X(WRSTI)
+X(RRSTI)
+
+// GBC
+X(GBC)
+//X(AI1)
+//X(AI2)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+//X(AO1)
+//X(AO2)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+//X(BI1)
+//X(BI2)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+//X(BO1)
+//X(BO2)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+
+// GCI
+X(GCI)
+//X(I)
+//X(O)
+
+// GCK
+X(GCK)
+X(CMD)
+X(SI1)
+X(SI2)
+X(SO)
+
+// GEA
+X(GEA)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+X(I19)
+//X(I2)
+X(I20)
+X(I21)
+X(I22)
+X(I23)
+X(I24)
+X(I25)
+X(I26)
+X(I27)
+X(I28)
+X(I29)
+//X(I3)
+X(I30)
+X(I31)
+X(I32)
+X(I33)
+X(I34)
+X(I35)
+X(I36)
+X(I37)
+X(I38)
+X(I39)
+//X(I4)
+X(I40)
+X(I41)
+X(I42)
+X(I43)
+X(I44)
+X(I45)
+X(I46)
+X(I47)
+X(I48)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+
+// GEB
+X(GEB)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+
+// GSO
+X(GSO)
+//X(I)
+//X(O)
+
+// HEE
+X(HEE)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// HSS
+X(HSS)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// IOM
+X(IOM)
+X(AL1D)
+X(AL1T)
+X(AL2D)
+X(AL2T)
+X(AL3D)
+X(AL3T)
+X(ALCK1)
+X(ALCK2)
+X(ALCK3)
+X(CA1D1)
+X(CA1D2)
+X(CA1D3)
+X(CA1D4)
+X(CA1D5)
+X(CA1D6)
+X(CA1N1)
+X(CA1N2)
+X(CA1N3)
+X(CA1N4)
+X(CA1P1)
+X(CA1P2)
+X(CA1P3)
+X(CA1P4)
+X(CA1T1)
+X(CA1T2)
+X(CA1T3)
+X(CA1T4)
+X(CA2D1)
+X(CA2D2)
+X(CA2D3)
+X(CA2D4)
+X(CA2D5)
+X(CA2D6)
+X(CA2N1)
+X(CA2N2)
+X(CA2N3)
+X(CA2N4)
+X(CA2P1)
+X(CA2P2)
+X(CA2P3)
+X(CA2P4)
+X(CA2T1)
+X(CA2T2)
+X(CA2T3)
+X(CA2T4)
+X(CCK)
+X(CKO1)
+X(CKO2)
+X(DCL)
+X(DCRN)
+X(DQ1CI1)
+X(DQ1CI2)
+X(DQ1CI3)
+X(DQ1CI4)
+X(DQ1CI5)
+X(DQ1CI6)
+X(DQ1CI7)
+X(DQ1CI8)
+X(DQ2CI1)
+X(DQ2CI2)
+X(DQ2CI3)
+X(DQ2CI4)
+X(DQ2CI5)
+X(DQ2CI6)
+X(DQ2CI7)
+X(DQ2CI8)
+X(DQ3CI1)
+X(DQ3CI2)
+X(DQ3CI3)
+X(DQ3CI4)
+X(DQ3CI5)
+X(DQ3CI6)
+X(DQ3CI7)
+X(DQ3CI8)
+X(DQS1CI1)
+X(DQS1CI2)
+X(DQS1CI3)
+X(DQS1CI4)
+X(DQS1CI5)
+X(DQS1CI6)
+X(DQS1CI7)
+X(DQS1CI8)
+X(DQS2CI1)
+X(DQS2CI2)
+X(DQS2CI3)
+X(DQS2CI4)
+X(DQS2CI5)
+X(DQS2CI6)
+X(DQS2CI7)
+X(DQS2CI8)
+X(DQS3CI1)
+X(DQS3CI2)
+X(DQS3CI3)
+X(DQS3CI4)
+X(DQS3CI5)
+X(DQS3CI6)
+X(DQS3CI7)
+X(DQS3CI8)
+X(DRA1)
+X(DRA2)
+X(DRA3)
+X(DRA4)
+X(DRCCSN)
+X(DRDPA1CSN)
+X(DRDPA2CSN)
+X(DRDPA3CSN)
+X(DRE)
+X(DRI1)
+X(DRI1CSN)
+X(DRI2)
+X(DRI2CSN)
+X(DRI3)
+X(DRI3CSN)
+X(DRI4)
+X(DRI5)
+X(DRI6)
+X(DRO1)
+X(DRO1CSN)
+X(DRO2)
+X(DRO2CSN)
+X(DRO3)
+X(DRO3CSN)
+X(DRO4)
+X(DRO5)
+X(DRO6)
+X(DRWDS)
+X(DRWEN)
+X(FA1)
+X(FA2)
+X(FA3)
+X(FA4)
+X(FA5)
+X(FA6)
+X(FCK1)
+X(FCK2)
+X(FDCK)
+X(FLD)
+X(FLG)
+X(FZ)
+X(LD1RN)
+X(LD2RN)
+X(LD3RN)
+X(LDSCK1)
+X(LDSCK2)
+X(LDSCK3)
+X(LE)
+X(P10CI1)
+X(P10CL)
+X(P10CO)
+X(P10CR)
+X(P10CTI)
+X(P10CTO)
+X(P10EI1)
+X(P10EI2)
+X(P10EI3)
+X(P10EI4)
+X(P10EI5)
+X(P10EI6)
+X(P10EI7)
+X(P10EI8)
+X(P10EL)
+X(P10EO)
+X(P10ER)
+X(P10RI)
+X(P10RL)
+X(P10RO1)
+X(P10RO2)
+X(P10RO3)
+X(P10RO4)
+X(P10RO5)
+X(P10RO6)
+X(P10RO7)
+X(P10RO8)
+X(P10RR)
+X(P11CI1)
+X(P11CL)
+X(P11CO)
+X(P11CR)
+X(P11CTI)
+X(P11CTO)
+X(P11EI1)
+X(P11EI2)
+X(P11EI3)
+X(P11EI4)
+X(P11EI5)
+X(P11EI6)
+X(P11EI7)
+X(P11EI8)
+X(P11EL)
+X(P11EO)
+X(P11ER)
+X(P11RI)
+X(P11RL)
+X(P11RO1)
+X(P11RO2)
+X(P11RO3)
+X(P11RO4)
+X(P11RO5)
+X(P11RO6)
+X(P11RO7)
+X(P11RO8)
+X(P11RR)
+X(P12CI1)
+X(P12CL)
+X(P12CO)
+X(P12CR)
+X(P12CTI)
+X(P12CTO)
+X(P12EI1)
+X(P12EI2)
+X(P12EI3)
+X(P12EI4)
+X(P12EI5)
+X(P12EI6)
+X(P12EI7)
+X(P12EI8)
+X(P12EL)
+X(P12EO)
+X(P12ER)
+X(P12RI)
+X(P12RL)
+X(P12RO1)
+X(P12RO2)
+X(P12RO3)
+X(P12RO4)
+X(P12RO5)
+X(P12RO6)
+X(P12RO7)
+X(P12RO8)
+X(P12RR)
+X(P13CI1)
+X(P13CL)
+X(P13CO)
+X(P13CR)
+X(P13CTI)
+X(P13CTO)
+X(P13EI1)
+X(P13EI2)
+X(P13EI3)
+X(P13EI4)
+X(P13EI5)
+X(P13EI6)
+X(P13EI7)
+X(P13EI8)
+X(P13EL)
+X(P13EO)
+X(P13ER)
+X(P13RI)
+X(P13RL)
+X(P13RO1)
+X(P13RO2)
+X(P13RO3)
+X(P13RO4)
+X(P13RO5)
+X(P13RO6)
+X(P13RO7)
+X(P13RO8)
+X(P13RR)
+X(P14CI1)
+X(P14CL)
+X(P14CO)
+X(P14CR)
+X(P14CTI)
+X(P14CTO)
+X(P14EI1)
+X(P14EI2)
+X(P14EI3)
+X(P14EI4)
+X(P14EI5)
+X(P14EI6)
+X(P14EI7)
+X(P14EI8)
+X(P14EL)
+X(P14EO)
+X(P14ER)
+X(P14RI)
+X(P14RL)
+X(P14RO1)
+X(P14RO2)
+X(P14RO3)
+X(P14RO4)
+X(P14RO5)
+X(P14RO6)
+X(P14RO7)
+X(P14RO8)
+X(P14RR)
+X(P15CI1)
+X(P15CL)
+X(P15CO)
+X(P15CR)
+X(P15CTI)
+X(P15CTO)
+X(P15EI1)
+X(P15EI2)
+X(P15EI3)
+X(P15EI4)
+X(P15EI5)
+X(P15EI6)
+X(P15EI7)
+X(P15EI8)
+X(P15EL)
+X(P15EO)
+X(P15ER)
+X(P15RI)
+X(P15RL)
+X(P15RO1)
+X(P15RO2)
+X(P15RO3)
+X(P15RO4)
+X(P15RO5)
+X(P15RO6)
+X(P15RO7)
+X(P15RO8)
+X(P15RR)
+X(P16CI1)
+X(P16CL)
+X(P16CO)
+X(P16CR)
+X(P16CTI)
+X(P16CTO)
+X(P16EI1)
+X(P16EI2)
+X(P16EI3)
+X(P16EI4)
+X(P16EI5)
+X(P16EI6)
+X(P16EI7)
+X(P16EI8)
+X(P16EL)
+X(P16EO)
+X(P16ER)
+X(P16RI)
+X(P16RL)
+X(P16RO1)
+X(P16RO2)
+X(P16RO3)
+X(P16RO4)
+X(P16RO5)
+X(P16RO6)
+X(P16RO7)
+X(P16RO8)
+X(P16RR)
+X(P17CI1)
+X(P17CL)
+X(P17CO)
+X(P17CR)
+X(P17CTI)
+X(P17CTO)
+X(P17EI1)
+X(P17EI2)
+X(P17EI3)
+X(P17EI4)
+X(P17EI5)
+X(P17EI6)
+X(P17EI7)
+X(P17EI8)
+X(P17EL)
+X(P17EO)
+X(P17ER)
+X(P17RI)
+X(P17RL)
+X(P17RO1)
+X(P17RO2)
+X(P17RO3)
+X(P17RO4)
+X(P17RO5)
+X(P17RO6)
+X(P17RO7)
+X(P17RO8)
+X(P17RR)
+X(P18CI1)
+X(P18CL)
+X(P18CO)
+X(P18CR)
+X(P18CTI)
+X(P18CTO)
+X(P18EI1)
+X(P18EI2)
+X(P18EI3)
+X(P18EI4)
+X(P18EI5)
+X(P18EI6)
+X(P18EI7)
+X(P18EI8)
+X(P18EL)
+X(P18EO)
+X(P18ER)
+X(P18RI)
+X(P18RL)
+X(P18RO1)
+X(P18RO2)
+X(P18RO3)
+X(P18RO4)
+X(P18RO5)
+X(P18RO6)
+X(P18RO7)
+X(P18RO8)
+X(P18RR)
+X(P19CI1)
+X(P19CL)
+X(P19CO)
+X(P19CR)
+X(P19CTI)
+X(P19CTO)
+X(P19EI1)
+X(P19EI2)
+X(P19EI3)
+X(P19EI4)
+X(P19EI5)
+X(P19EI6)
+X(P19EI7)
+X(P19EI8)
+X(P19EL)
+X(P19EO)
+X(P19ER)
+X(P19RI)
+X(P19RL)
+X(P19RO1)
+X(P19RO2)
+X(P19RO3)
+X(P19RO4)
+X(P19RO5)
+X(P19RO6)
+X(P19RO7)
+X(P19RO8)
+X(P19RR)
+X(P1CI1)
+X(P1CL)
+X(P1CO)
+X(P1CR)
+X(P1CTI)
+X(P1CTO)
+X(P1EI1)
+X(P1EI2)
+X(P1EI3)
+X(P1EI4)
+X(P1EI5)
+X(P1EI6)
+X(P1EI7)
+X(P1EI8)
+X(P1EL)
+X(P1EO)
+X(P1ER)
+X(P1RI)
+X(P1RL)
+X(P1RO1)
+X(P1RO2)
+X(P1RO3)
+X(P1RO4)
+X(P1RO5)
+X(P1RO6)
+X(P1RO7)
+X(P1RO8)
+X(P1RR)
+X(P20CI1)
+X(P20CL)
+X(P20CO)
+X(P20CR)
+X(P20CTI)
+X(P20CTO)
+X(P20EI1)
+X(P20EI2)
+X(P20EI3)
+X(P20EI4)
+X(P20EI5)
+X(P20EI6)
+X(P20EI7)
+X(P20EI8)
+X(P20EL)
+X(P20EO)
+X(P20ER)
+X(P20RI)
+X(P20RL)
+X(P20RO1)
+X(P20RO2)
+X(P20RO3)
+X(P20RO4)
+X(P20RO5)
+X(P20RO6)
+X(P20RO7)
+X(P20RO8)
+X(P20RR)
+X(P21CI1)
+X(P21CL)
+X(P21CO)
+X(P21CR)
+X(P21CTI)
+X(P21CTO)
+X(P21EI1)
+X(P21EI2)
+X(P21EI3)
+X(P21EI4)
+X(P21EI5)
+X(P21EI6)
+X(P21EI7)
+X(P21EI8)
+X(P21EL)
+X(P21EO)
+X(P21ER)
+X(P21RI)
+X(P21RL)
+X(P21RO1)
+X(P21RO2)
+X(P21RO3)
+X(P21RO4)
+X(P21RO5)
+X(P21RO6)
+X(P21RO7)
+X(P21RO8)
+X(P21RR)
+X(P22CI1)
+X(P22CL)
+X(P22CO)
+X(P22CR)
+X(P22CTI)
+X(P22CTO)
+X(P22EI1)
+X(P22EI2)
+X(P22EI3)
+X(P22EI4)
+X(P22EI5)
+X(P22EI6)
+X(P22EI7)
+X(P22EI8)
+X(P22EL)
+X(P22EO)
+X(P22ER)
+X(P22RI)
+X(P22RL)
+X(P22RO1)
+X(P22RO2)
+X(P22RO3)
+X(P22RO4)
+X(P22RO5)
+X(P22RO6)
+X(P22RO7)
+X(P22RO8)
+X(P22RR)
+X(P23CI1)
+X(P23CL)
+X(P23CO)
+X(P23CR)
+X(P23CTI)
+X(P23CTO)
+X(P23EI1)
+X(P23EI2)
+X(P23EI3)
+X(P23EI4)
+X(P23EI5)
+X(P23EI6)
+X(P23EI7)
+X(P23EI8)
+X(P23EL)
+X(P23EO)
+X(P23ER)
+X(P23RI)
+X(P23RL)
+X(P23RO1)
+X(P23RO2)
+X(P23RO3)
+X(P23RO4)
+X(P23RO5)
+X(P23RO6)
+X(P23RO7)
+X(P23RO8)
+X(P23RR)
+X(P24CI1)
+X(P24CL)
+X(P24CO)
+X(P24CR)
+X(P24CTI)
+X(P24CTO)
+X(P24EI1)
+X(P24EI2)
+X(P24EI3)
+X(P24EI4)
+X(P24EI5)
+X(P24EI6)
+X(P24EI7)
+X(P24EI8)
+X(P24EL)
+X(P24EO)
+X(P24ER)
+X(P24RI)
+X(P24RL)
+X(P24RO1)
+X(P24RO2)
+X(P24RO3)
+X(P24RO4)
+X(P24RO5)
+X(P24RO6)
+X(P24RO7)
+X(P24RO8)
+X(P24RR)
+X(P25CI1)
+X(P25CL)
+X(P25CO)
+X(P25CR)
+X(P25CTI)
+X(P25CTO)
+X(P25EI1)
+X(P25EI2)
+X(P25EI3)
+X(P25EI4)
+X(P25EI5)
+X(P25EI6)
+X(P25EI7)
+X(P25EI8)
+X(P25EL)
+X(P25EO)
+X(P25ER)
+X(P25RI)
+X(P25RL)
+X(P25RO1)
+X(P25RO2)
+X(P25RO3)
+X(P25RO4)
+X(P25RO5)
+X(P25RO6)
+X(P25RO7)
+X(P25RO8)
+X(P25RR)
+X(P26CI1)
+X(P26CL)
+X(P26CO)
+X(P26CR)
+X(P26CTI)
+X(P26CTO)
+X(P26EI1)
+X(P26EI2)
+X(P26EI3)
+X(P26EI4)
+X(P26EI5)
+X(P26EI6)
+X(P26EI7)
+X(P26EI8)
+X(P26EL)
+X(P26EO)
+X(P26ER)
+X(P26RI)
+X(P26RL)
+X(P26RO1)
+X(P26RO2)
+X(P26RO3)
+X(P26RO4)
+X(P26RO5)
+X(P26RO6)
+X(P26RO7)
+X(P26RO8)
+X(P26RR)
+X(P27CI1)
+X(P27CL)
+X(P27CO)
+X(P27CR)
+X(P27CTI)
+X(P27CTO)
+X(P27EI1)
+X(P27EI2)
+X(P27EI3)
+X(P27EI4)
+X(P27EI5)
+X(P27EI6)
+X(P27EI7)
+X(P27EI8)
+X(P27EL)
+X(P27EO)
+X(P27ER)
+X(P27RI)
+X(P27RL)
+X(P27RO1)
+X(P27RO2)
+X(P27RO3)
+X(P27RO4)
+X(P27RO5)
+X(P27RO6)
+X(P27RO7)
+X(P27RO8)
+X(P27RR)
+X(P28CI1)
+X(P28CL)
+X(P28CO)
+X(P28CR)
+X(P28CTI)
+X(P28CTO)
+X(P28EI1)
+X(P28EI2)
+X(P28EI3)
+X(P28EI4)
+X(P28EI5)
+X(P28EI6)
+X(P28EI7)
+X(P28EI8)
+X(P28EL)
+X(P28EO)
+X(P28ER)
+X(P28RI)
+X(P28RL)
+X(P28RO1)
+X(P28RO2)
+X(P28RO3)
+X(P28RO4)
+X(P28RO5)
+X(P28RO6)
+X(P28RO7)
+X(P28RO8)
+X(P28RR)
+X(P29CI1)
+X(P29CL)
+X(P29CO)
+X(P29CR)
+X(P29CTI)
+X(P29CTO)
+X(P29EI1)
+X(P29EI2)
+X(P29EI3)
+X(P29EI4)
+X(P29EI5)
+X(P29EI6)
+X(P29EI7)
+X(P29EI8)
+X(P29EL)
+X(P29EO)
+X(P29ER)
+X(P29RI)
+X(P29RL)
+X(P29RO1)
+X(P29RO2)
+X(P29RO3)
+X(P29RO4)
+X(P29RO5)
+X(P29RO6)
+X(P29RO7)
+X(P29RO8)
+X(P29RR)
+X(P2CI1)
+X(P2CL)
+X(P2CO)
+X(P2CR)
+X(P2CTI)
+X(P2CTO)
+X(P2EI1)
+X(P2EI2)
+X(P2EI3)
+X(P2EI4)
+X(P2EI5)
+X(P2EI6)
+X(P2EI7)
+X(P2EI8)
+X(P2EL)
+X(P2EO)
+X(P2ER)
+X(P2RI)
+X(P2RL)
+X(P2RO1)
+X(P2RO2)
+X(P2RO3)
+X(P2RO4)
+X(P2RO5)
+X(P2RO6)
+X(P2RO7)
+X(P2RO8)
+X(P2RR)
+X(P30CI1)
+X(P30CL)
+X(P30CO)
+X(P30CR)
+X(P30CTI)
+X(P30CTO)
+X(P30EI1)
+X(P30EI2)
+X(P30EI3)
+X(P30EI4)
+X(P30EI5)
+X(P30EI6)
+X(P30EI7)
+X(P30EI8)
+X(P30EL)
+X(P30EO)
+X(P30ER)
+X(P30RI)
+X(P30RL)
+X(P30RO1)
+X(P30RO2)
+X(P30RO3)
+X(P30RO4)
+X(P30RO5)
+X(P30RO6)
+X(P30RO7)
+X(P30RO8)
+X(P30RR)
+X(P31CI1)
+X(P31CL)
+X(P31CO)
+X(P31CR)
+X(P31CTI)
+X(P31CTO)
+X(P31EI1)
+X(P31EI2)
+X(P31EI3)
+X(P31EI4)
+X(P31EI5)
+X(P31EI6)
+X(P31EI7)
+X(P31EI8)
+X(P31EL)
+X(P31EO)
+X(P31ER)
+X(P31RI)
+X(P31RL)
+X(P31RO1)
+X(P31RO2)
+X(P31RO3)
+X(P31RO4)
+X(P31RO5)
+X(P31RO6)
+X(P31RO7)
+X(P31RO8)
+X(P31RR)
+X(P32CI1)
+X(P32CL)
+X(P32CO)
+X(P32CR)
+X(P32CTI)
+X(P32CTO)
+X(P32EI1)
+X(P32EI2)
+X(P32EI3)
+X(P32EI4)
+X(P32EI5)
+X(P32EI6)
+X(P32EI7)
+X(P32EI8)
+X(P32EL)
+X(P32EO)
+X(P32ER)
+X(P32RI)
+X(P32RL)
+X(P32RO1)
+X(P32RO2)
+X(P32RO3)
+X(P32RO4)
+X(P32RO5)
+X(P32RO6)
+X(P32RO7)
+X(P32RO8)
+X(P32RR)
+X(P33CI1)
+X(P33CL)
+X(P33CO)
+X(P33CR)
+X(P33CTI)
+X(P33CTO)
+X(P33EI1)
+X(P33EI2)
+X(P33EI3)
+X(P33EI4)
+X(P33EI5)
+X(P33EI6)
+X(P33EI7)
+X(P33EI8)
+X(P33EL)
+X(P33EO)
+X(P33ER)
+X(P33RI)
+X(P33RL)
+X(P33RO1)
+X(P33RO2)
+X(P33RO3)
+X(P33RO4)
+X(P33RO5)
+X(P33RO6)
+X(P33RO7)
+X(P33RO8)
+X(P33RR)
+X(P34CI1)
+X(P34CL)
+X(P34CO)
+X(P34CR)
+X(P34CTI)
+X(P34CTO)
+X(P34EI1)
+X(P34EI2)
+X(P34EI3)
+X(P34EI4)
+X(P34EI5)
+X(P34EI6)
+X(P34EI7)
+X(P34EI8)
+X(P34EL)
+X(P34EO)
+X(P34ER)
+X(P34RI)
+X(P34RL)
+X(P34RO1)
+X(P34RO2)
+X(P34RO3)
+X(P34RO4)
+X(P34RO5)
+X(P34RO6)
+X(P34RO7)
+X(P34RO8)
+X(P34RR)
+X(P3CI1)
+X(P3CL)
+X(P3CO)
+X(P3CR)
+X(P3CTI)
+X(P3CTO)
+X(P3EI1)
+X(P3EI2)
+X(P3EI3)
+X(P3EI4)
+X(P3EI5)
+X(P3EI6)
+X(P3EI7)
+X(P3EI8)
+X(P3EL)
+X(P3EO)
+X(P3ER)
+X(P3RI)
+X(P3RL)
+X(P3RO1)
+X(P3RO2)
+X(P3RO3)
+X(P3RO4)
+X(P3RO5)
+X(P3RO6)
+X(P3RO7)
+X(P3RO8)
+X(P3RR)
+X(P4CI1)
+X(P4CL)
+X(P4CO)
+X(P4CR)
+X(P4CTI)
+X(P4CTO)
+X(P4EI1)
+X(P4EI2)
+X(P4EI3)
+X(P4EI4)
+X(P4EI5)
+X(P4EI6)
+X(P4EI7)
+X(P4EI8)
+X(P4EL)
+X(P4EO)
+X(P4ER)
+X(P4RI)
+X(P4RL)
+X(P4RO1)
+X(P4RO2)
+X(P4RO3)
+X(P4RO4)
+X(P4RO5)
+X(P4RO6)
+X(P4RO7)
+X(P4RO8)
+X(P4RR)
+X(P5CI1)
+X(P5CL)
+X(P5CO)
+X(P5CR)
+X(P5CTI)
+X(P5CTO)
+X(P5EI1)
+X(P5EI2)
+X(P5EI3)
+X(P5EI4)
+X(P5EI5)
+X(P5EI6)
+X(P5EI7)
+X(P5EI8)
+X(P5EL)
+X(P5EO)
+X(P5ER)
+X(P5RI)
+X(P5RL)
+X(P5RO1)
+X(P5RO2)
+X(P5RO3)
+X(P5RO4)
+X(P5RO5)
+X(P5RO6)
+X(P5RO7)
+X(P5RO8)
+X(P5RR)
+X(P6CI1)
+X(P6CL)
+X(P6CO)
+X(P6CR)
+X(P6CTI)
+X(P6CTO)
+X(P6EI1)
+X(P6EI2)
+X(P6EI3)
+X(P6EI4)
+X(P6EI5)
+X(P6EI6)
+X(P6EI7)
+X(P6EI8)
+X(P6EL)
+X(P6EO)
+X(P6ER)
+X(P6RI)
+X(P6RL)
+X(P6RO1)
+X(P6RO2)
+X(P6RO3)
+X(P6RO4)
+X(P6RO5)
+X(P6RO6)
+X(P6RO7)
+X(P6RO8)
+X(P6RR)
+X(P7CI1)
+X(P7CL)
+X(P7CO)
+X(P7CR)
+X(P7CTI)
+X(P7CTO)
+X(P7EI1)
+X(P7EI2)
+X(P7EI3)
+X(P7EI4)
+X(P7EI5)
+X(P7EI6)
+X(P7EI7)
+X(P7EI8)
+X(P7EL)
+X(P7EO)
+X(P7ER)
+X(P7RI)
+X(P7RL)
+X(P7RO1)
+X(P7RO2)
+X(P7RO3)
+X(P7RO4)
+X(P7RO5)
+X(P7RO6)
+X(P7RO7)
+X(P7RO8)
+X(P7RR)
+X(P8CI1)
+X(P8CL)
+X(P8CO)
+X(P8CR)
+X(P8CTI)
+X(P8CTO)
+X(P8EI1)
+X(P8EI2)
+X(P8EI3)
+X(P8EI4)
+X(P8EI5)
+X(P8EI6)
+X(P8EI7)
+X(P8EI8)
+X(P8EL)
+X(P8EO)
+X(P8ER)
+X(P8RI)
+X(P8RL)
+X(P8RO1)
+X(P8RO2)
+X(P8RO3)
+X(P8RO4)
+X(P8RO5)
+X(P8RO6)
+X(P8RO7)
+X(P8RO8)
+X(P8RR)
+X(P9CI1)
+X(P9CL)
+X(P9CO)
+X(P9CR)
+X(P9CTI)
+X(P9CTO)
+X(P9EI1)
+X(P9EI2)
+X(P9EI3)
+X(P9EI4)
+X(P9EI5)
+X(P9EI6)
+X(P9EI7)
+X(P9EI8)
+X(P9EL)
+X(P9EO)
+X(P9ER)
+X(P9RI)
+X(P9RL)
+X(P9RO1)
+X(P9RO2)
+X(P9RO3)
+X(P9RO4)
+X(P9RO5)
+X(P9RO6)
+X(P9RO7)
+X(P9RO8)
+X(P9RR)
+X(SE)
+X(SWRX1CK)
+X(SWRX2CK)
+
+// IOP
+X(IOP)
+//X(C)
+//X(I)
+//X(O)
+
+// IOTP
+X(IOTP)
+//X(C)
+//X(I)
+X(IO)
+//X(O)
+X(T)
+
+// IP
+X(IP)
+//X(C)
+//X(O)
+
+// ITC
+X(ITC)
+//X(I)
+//X(O)
+
+// ITP
+X(ITP)
+//X(C)
+//X(IO)
+//X(O)
+//X(T)
+
+// ITS
+X(ITS)
+//X(I)
+//X(O)
+
+// LUT
+X(LUT)
+X(D)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(J)
+//X(K)
+//X(O)
+X(X)
+
+// MSM
+X(MSM)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I37)
+//X(I38)
+//X(I39)
+//X(I4)
+//X(I40)
+//X(I41)
+//X(I42)
+//X(I43)
+//X(I44)
+//X(I45)
+//X(I46)
+//X(I47)
+//X(I48)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+X(O19)
+//X(O2)
+X(O20)
+X(O21)
+X(O22)
+X(O23)
+X(O24)
+X(O25)
+X(O26)
+X(O27)
+X(O28)
+X(O29)
+//X(O3)
+X(O30)
+X(O31)
+X(O32)
+X(O33)
+X(O34)
+X(O35)
+X(O36)
+X(O37)
+X(O38)
+X(O39)
+//X(O4)
+X(O40)
+X(O41)
+X(O42)
+X(O43)
+X(O44)
+X(O45)
+X(O46)
+X(O47)
+X(O48)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// OP
+X(OP)
+//X(C)
+//X(I)
+
+// OTC
+X(OTC)
+//X(I)
+//X(O)
+
+// OTP
+X(OTP)
+//X(C)
+//X(I)
+//X(IO)
+//X(T)
+
+// OTS
+X(OTS)
+//X(I)
+//X(O)
+
+// PLL
+X(PLL)
+X(ARST_CAL)
+X(CAL1)
+X(CAL2)
+X(CAL3)
+X(CAL4)
+X(CAL5)
+X(CAL_LOCKED)
+X(CLK_CAL)
+X(CLK_CAL_DIV)
+X(CLK_DIV1)
+X(CLK_DIV2)
+X(CLK_DIV3)
+X(CLK_DIV4)
+X(CLK_DIVD1)
+X(CLK_DIVD2)
+X(CLK_DIVD3)
+X(CLK_DIVD4)
+X(CLK_DIVD5)
+X(EXT_CAL1)
+X(EXT_CAL2)
+X(EXT_CAL3)
+X(EXT_CAL4)
+X(EXT_CAL5)
+X(EXT_CAL_LOCKED)
+X(FBK)
+X(LDFO)
+X(OSC)
+X(PLL_LOCKED)
+X(PLL_LOCKEDA)
+//X(R)
+X(REF)
+X(REFO)
+X(VCO)
+X(scan_en_i)
+X(scan_in_i1)
+X(scan_in_i10)
+X(scan_in_i11)
+X(scan_in_i12)
+X(scan_in_i13)
+X(scan_in_i14)
+X(scan_in_i15)
+X(scan_in_i16)
+X(scan_in_i17)
+X(scan_in_i18)
+X(scan_in_i19)
+X(scan_in_i2)
+X(scan_in_i20)
+X(scan_in_i21)
+X(scan_in_i22)
+X(scan_in_i23)
+X(scan_in_i24)
+X(scan_in_i25)
+X(scan_in_i26)
+X(scan_in_i27)
+X(scan_in_i28)
+X(scan_in_i29)
+X(scan_in_i3)
+X(scan_in_i30)
+X(scan_in_i31)
+X(scan_in_i32)
+X(scan_in_i33)
+X(scan_in_i34)
+X(scan_in_i35)
+X(scan_in_i36)
+X(scan_in_i37)
+X(scan_in_i4)
+X(scan_in_i5)
+X(scan_in_i6)
+X(scan_in_i7)
+X(scan_in_i8)
+X(scan_in_i9)
+X(scan_out_o1)
+X(scan_out_o10)
+X(scan_out_o11)
+X(scan_out_o12)
+X(scan_out_o13)
+X(scan_out_o14)
+X(scan_out_o15)
+X(scan_out_o16)
+X(scan_out_o17)
+X(scan_out_o18)
+X(scan_out_o19)
+X(scan_out_o2)
+X(scan_out_o20)
+X(scan_out_o21)
+X(scan_out_o22)
+X(scan_out_o23)
+X(scan_out_o24)
+X(scan_out_o25)
+X(scan_out_o26)
+X(scan_out_o27)
+X(scan_out_o28)
+X(scan_out_o29)
+X(scan_out_o3)
+X(scan_out_o30)
+X(scan_out_o31)
+X(scan_out_o32)
+X(scan_out_o33)
+X(scan_out_o34)
+X(scan_out_o35)
+X(scan_out_o36)
+X(scan_out_o37)
+X(scan_out_o4)
+X(scan_out_o5)
+X(scan_out_o6)
+X(scan_out_o7)
+X(scan_out_o8)
+X(scan_out_o9)
+
+// PMA
+X(PMA)
+X(CAL_OUT_O)
+//X(CLK_O)
+X(CLK_RX_O)
+X(DBG_A_I)
+X(DBG_R_O)
+//X(DBG_S_I1)
+//X(DBG_S_I2)
+X(DC_ADD_I1)
+X(DC_ADD_I2)
+X(DC_ADD_I3)
+X(DC_ADD_I4)
+X(DC_CCSN_I)
+X(DC_E_I)
+X(DC_LCSN_I1)
+X(DC_LCSN_I2)
+X(DC_LCSN_I3)
+X(DC_LCSN_I4)
+X(DC_WDATAS_I)
+X(DC_WDATA_I1)
+X(DC_WDATA_I10)
+X(DC_WDATA_I11)
+X(DC_WDATA_I12)
+X(DC_WDATA_I2)
+X(DC_WDATA_I3)
+X(DC_WDATA_I4)
+X(DC_WDATA_I5)
+X(DC_WDATA_I6)
+X(DC_WDATA_I7)
+X(DC_WDATA_I8)
+X(DC_WDATA_I9)
+X(DC_WE_N_I)
+X(FB_LOCK_O)
+X(LINK_RX0)
+X(LINK_RX1)
+X(LINK_RX2)
+X(LINK_RX3)
+X(LINK_TX0)
+X(LINK_TX1)
+X(LINK_TX2)
+X(LINK_TX3)
+X(LL_O1)
+X(LL_O10)
+X(LL_O11)
+X(LL_O12)
+X(LL_O13)
+X(LL_O14)
+X(LL_O15)
+X(LL_O16)
+X(LL_O17)
+X(LL_O18)
+X(LL_O19)
+X(LL_O2)
+X(LL_O20)
+X(LL_O3)
+X(LL_O4)
+X(LL_O5)
+X(LL_O6)
+X(LL_O7)
+X(LL_O8)
+X(LL_O9)
+X(LOCKA_O)
+X(LOCK_O)
+X(PLL_RN_I)
+//X(PWDN_N_I)
+//X(RST_N_I)
+X(SCAN_I1)
+X(SCAN_I2)
+X(SCAN_I3)
+X(SCAN_I4)
+X(SCAN_I5)
+X(SCAN_I6)
+X(SCAN_I7)
+X(SCAN_I8)
+X(SCAN_O1)
+X(SCAN_O2)
+X(SCAN_O3)
+X(SCAN_O4)
+X(SCAN_O5)
+X(SCAN_O6)
+X(SCAN_O7)
+X(SCAN_O8)
+X(SE_I)
+X(calibrate)
+X(ckrefn)
+X(ckrefp)
+X(hssl_clock_i1)
+X(hssl_clock_i2)
+X(hssl_clock_i3)
+X(hssl_clock_i4)
+X(pll_ckref_in)
+X(pll_ckref_out)
+X(pma_pll_fbr_clk_ref_o)
+X(rx0n)
+X(rx0p)
+X(rx1n)
+X(rx1p)
+X(rx2n)
+X(rx2p)
+X(rx3n)
+X(rx3p)
+X(tx0n)
+X(tx0p)
+X(tx1n)
+X(tx1p)
+X(tx2n)
+X(tx2p)
+X(tx3n)
+X(tx3p)
+
+// RAM
+X(RAM)
+X(AA1)
+X(AA10)
+X(AA11)
+X(AA12)
+X(AA13)
+X(AA14)
+X(AA15)
+X(AA16)
+X(AA2)
+X(AA3)
+X(AA4)
+X(AA5)
+X(AA6)
+X(AA7)
+X(AA8)
+X(AA9)
+X(ACK)
+X(ACKC)
+X(ACKD)
+X(ACKR)
+X(ACOR)
+X(ACS)
+X(AERR)
+//X(AI1)
+X(AI10)
+X(AI11)
+X(AI12)
+X(AI13)
+X(AI14)
+X(AI15)
+X(AI16)
+X(AI17)
+X(AI18)
+X(AI19)
+//X(AI2)
+X(AI20)
+X(AI21)
+X(AI22)
+X(AI23)
+X(AI24)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+X(AI7)
+X(AI8)
+X(AI9)
+//X(AO1)
+X(AO10)
+X(AO11)
+X(AO12)
+X(AO13)
+X(AO14)
+X(AO15)
+X(AO16)
+X(AO17)
+X(AO18)
+X(AO19)
+//X(AO2)
+X(AO20)
+X(AO21)
+X(AO22)
+X(AO23)
+X(AO24)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+X(AO7)
+X(AO8)
+X(AO9)
+X(AR)
+X(AWE)
+X(BA1)
+X(BA10)
+X(BA11)
+X(BA12)
+X(BA13)
+X(BA14)
+X(BA15)
+X(BA16)
+X(BA2)
+X(BA3)
+X(BA4)
+X(BA5)
+X(BA6)
+X(BA7)
+X(BA8)
+X(BA9)
+X(BCK)
+X(BCKC)
+X(BCKD)
+X(BCKR)
+X(BCOR)
+X(BCS)
+X(BERR)
+//X(BI1)
+X(BI10)
+X(BI11)
+X(BI12)
+X(BI13)
+X(BI14)
+X(BI15)
+X(BI16)
+X(BI17)
+X(BI18)
+X(BI19)
+//X(BI2)
+X(BI20)
+X(BI21)
+X(BI22)
+X(BI23)
+X(BI24)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+X(BI7)
+X(BI8)
+X(BI9)
+//X(BO1)
+X(BO10)
+X(BO11)
+X(BO12)
+X(BO13)
+X(BO14)
+X(BO15)
+X(BO16)
+X(BO17)
+X(BO18)
+X(BO19)
+//X(BO2)
+X(BO20)
+X(BO21)
+X(BO22)
+X(BO23)
+X(BO24)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+X(BO7)
+X(BO8)
+X(BO9)
+X(BR)
+X(BWE)
+
+// RF
+X(RF)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+X(RA1)
+X(RA2)
+X(RA3)
+X(RA4)
+X(RA5)
+X(WA1)
+X(WA2)
+X(WA3)
+X(WA4)
+X(WA5)
+//X(WCK)
+//X(WE)
+//X(WEA)
+
+// RFSP
+X(RFSP)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RA1)
+//X(RA2)
+//X(RA3)
+//X(RA4)
+//X(RA5)
+//X(WA1)
+//X(WA2)
+//X(WA3)
+//X(WA4)
+//X(WA5)
+//X(WCK)
+//X(WE)
+//X(WEA)
+
+// SCC
+X(SCC)
+//X(C)
+//X(I)
+//X(J)
+//X(K)
+//X(O)
+//X(P)
+//X(S)
+
+// SCI
+X(SCI)
+//X(I)
+//X(O)
+
+// SCO
+X(SCO)
+//X(I)
+//X(O)
+
+// SEA
+X(SEA)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// SEB
+X(SEB)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// SIC
+X(SIC)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+
+// SLT
+X(SLT)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// SSA
+X(SSA)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+
+// SSB
+X(SSB)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+
+// SSI
+X(SSI)
+//X(I)
+//X(O)
+
+// TCI
+X(TCI)
+//X(I)
+//X(O)
+
+// TCO
+X(TCO)
+//X(I)
+//X(O)
+
+// TDE
+X(TDE)
+//X(ADRSTI)
+//X(ADRSTO)
+//X(AI1)
+//X(AI2)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+//X(AO1)
+//X(AO2)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+//X(ASRSTI)
+//X(ASRSTO)
+//X(BDRSTI)
+//X(BDRSTO)
+//X(BI1)
+//X(BI2)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+//X(BO1)
+//X(BO2)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+//X(BSRSTI)
+//X(BSRSTO)
+//X(CK1)
+//X(CK2)
+
+// TEA
+X(TEA)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// TEB
+X(TEB)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// TIA
+X(TIA)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// TIB
+X(TIB)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+
+// TLT
+X(TLT)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O37)
+//X(O38)
+//X(O39)
+//X(O4)
+//X(O40)
+//X(O41)
+//X(O42)
+//X(O43)
+//X(O44)
+//X(O45)
+//X(O46)
+//X(O47)
+//X(O48)
+X(O49)
+//X(O5)
+X(O50)
+X(O51)
+X(O52)
+X(O53)
+X(O54)
+X(O55)
+X(O56)
+X(O57)
+X(O58)
+X(O59)
+//X(O6)
+X(O60)
+X(O61)
+X(O62)
+X(O63)
+X(O64)
+X(O65)
+X(O66)
+X(O67)
+X(O68)
+X(O69)
+//X(O7)
+X(O70)
+X(O71)
+X(O72)
+X(O73)
+X(O74)
+X(O75)
+X(O76)
+X(O77)
+X(O78)
+X(O79)
+//X(O8)
+X(O80)
+X(O81)
+X(O82)
+X(O83)
+X(O84)
+X(O85)
+X(O86)
+//X(O9)
+
+// TSA
+X(TSA)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+
+// TSB
+X(TSB)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+
+// TSI
+X(TSI)
+//X(I)
+//X(O)
+
+// TSO
+X(TSO)
+//X(I)
+//X(O)
+
+// TSS
+X(TSS)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I37)
+//X(I38)
+//X(I39)
+//X(I4)
+//X(I40)
+//X(I41)
+//X(I42)
+//X(I43)
+//X(I44)
+//X(I45)
+//X(I46)
+//X(I47)
+//X(I48)
+X(I49)
+//X(I5)
+X(I50)
+X(I51)
+X(I52)
+X(I53)
+X(I54)
+X(I55)
+X(I56)
+X(I57)
+X(I58)
+X(I59)
+//X(I6)
+X(I60)
+X(I61)
+X(I62)
+X(I63)
+X(I64)
+X(I65)
+X(I66)
+X(I67)
+X(I68)
+X(I69)
+//X(I7)
+X(I70)
+X(I71)
+X(I72)
+X(I73)
+X(I74)
+X(I75)
+X(I76)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O2)
+//X(O3)
+//X(O4)
+
+// WFB
+X(WFB)
+X(ZI)
+X(ZO)
+
+// WFG
+X(WFG)
+//X(R)
+X(SI)
+//X(SO)
+//X(ZI)
+//X(ZO)
+
+// XCDC
+X(XCDC)
+//X(ADRSTI)
+//X(ADRSTO)
+//X(AI1)
+//X(AI2)
+//X(AI3)
+//X(AI4)
+//X(AI5)
+//X(AI6)
+//X(AO1)
+//X(AO2)
+//X(AO3)
+//X(AO4)
+//X(AO5)
+//X(AO6)
+//X(ASRSTI)
+//X(ASRSTO)
+//X(BDRSTI)
+//X(BDRSTO)
+//X(BI1)
+//X(BI2)
+//X(BI3)
+//X(BI4)
+//X(BI5)
+//X(BI6)
+//X(BO1)
+//X(BO2)
+//X(BO3)
+//X(BO4)
+//X(BO5)
+//X(BO6)
+//X(BSRSTI)
+//X(BSRSTO)
+X(CDRSTI)
+X(CDRSTO)
+X(CI1)
+X(CI2)
+X(CI3)
+X(CI4)
+X(CI5)
+X(CI6)
+//X(CK1)
+//X(CK2)
+X(CO1)
+X(CO2)
+X(CO3)
+X(CO4)
+X(CO5)
+X(CO6)
+X(CSRSTI)
+X(CSRSTO)
+X(DDRSTI)
+X(DDRSTO)
+X(DI1)
+X(DI2)
+X(DI3)
+X(DI4)
+X(DI5)
+X(DI6)
+X(DO1)
+X(DO2)
+X(DO3)
+X(DO4)
+X(DO5)
+X(DO6)
+X(DSRSTI)
+X(DSRSTO)
+
+// XFIFO
+X(XFIFO)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RAI1)
+//X(RAI2)
+//X(RAI3)
+//X(RAI4)
+//X(RAI5)
+//X(RAI6)
+X(RAI7)
+//X(RAO1)
+//X(RAO2)
+//X(RAO3)
+//X(RAO4)
+//X(RAO5)
+//X(RAO6)
+X(RAO7)
+X(RCK1)
+X(RCK2)
+X(REQ1)
+X(REQ2)
+//X(RRSTI1)
+//X(RRSTI2)
+X(RRSTI3)
+X(RRSTI4)
+//X(RRSTO)
+//X(WAI1)
+//X(WAI2)
+//X(WAI3)
+//X(WAI4)
+//X(WAI5)
+//X(WAI6)
+X(WAI7)
+//X(WAO1)
+//X(WAO2)
+//X(WAO3)
+//X(WAO4)
+//X(WAO5)
+//X(WAO6)
+X(WAO7)
+X(WCK1)
+X(WCK2)
+//X(WE)
+//X(WEA)
+X(WEQ1)
+X(WEQ2)
+//X(WRSTI1)
+//X(WRSTI2)
+X(WRSTI3)
+X(WRSTI4)
+//X(WRSTO)
+
+// XHFIFO
+X(XHFIFO)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RAI1)
+//X(RAI2)
+//X(RAI3)
+//X(RAI4)
+//X(RAI5)
+//X(RAI6)
+//X(RAI7)
+//X(RAO1)
+//X(RAO2)
+//X(RAO3)
+//X(RAO4)
+//X(RAO5)
+//X(RAO6)
+//X(RAO7)
+//X(RCK1)
+//X(RCK2)
+//X(REQ1)
+//X(REQ2)
+//X(RRSTI1)
+//X(RRSTI2)
+//X(RRSTI3)
+//X(RRSTI4)
+//X(WAI1)
+//X(WAI2)
+//X(WAI3)
+//X(WAI4)
+//X(WAI5)
+//X(WAI6)
+//X(WAI7)
+//X(WAO1)
+//X(WAO2)
+//X(WAO3)
+//X(WAO4)
+//X(WAO5)
+//X(WAO6)
+//X(WAO7)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+//X(WEQ1)
+//X(WEQ2)
+//X(WRSTI1)
+//X(WRSTI2)
+//X(WRSTI3)
+//X(WRSTI4)
+
+// XHRF
+X(XHRF)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O2)
+//X(O3)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RA1)
+//X(RA2)
+//X(RA3)
+//X(RA4)
+//X(RA5)
+X(RA6)
+//X(WA1)
+//X(WA2)
+//X(WA3)
+//X(WA4)
+//X(WA5)
+X(WA6)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+
+// XLUT
+X(XLUT)
+X(G1)
+X(G2)
+X(G3)
+X(G4)
+//X(I1)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(J)
+//X(O)
+
+// XPRF
+X(XPRF)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I2)
+//X(I3)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RA1)
+X(RA10)
+//X(RA2)
+//X(RA3)
+//X(RA4)
+//X(RA5)
+//X(RA6)
+X(RA7)
+X(RA8)
+X(RA9)
+//X(WA1)
+//X(WA2)
+//X(WA3)
+//X(WA4)
+//X(WA5)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+
+// XRF
+X(XRF)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RA1)
+//X(RA10)
+//X(RA2)
+//X(RA3)
+//X(RA4)
+//X(RA5)
+//X(RA6)
+//X(RA7)
+//X(RA8)
+//X(RA9)
+//X(WA1)
+//X(WA2)
+//X(WA3)
+//X(WA4)
+//X(WA5)
+//X(WA6)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+
+// XWFIFO
+X(XWFIFO)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RAI1)
+//X(RAI2)
+//X(RAI3)
+//X(RAI4)
+//X(RAI5)
+//X(RAI6)
+//X(RAO1)
+//X(RAO2)
+//X(RAO3)
+//X(RAO4)
+//X(RAO5)
+//X(RAO6)
+//X(RCK1)
+//X(RCK2)
+//X(REQ)
+//X(RRSTI1)
+//X(RRSTI2)
+//X(WAI1)
+//X(WAI2)
+//X(WAI3)
+//X(WAI4)
+//X(WAI5)
+//X(WAI6)
+//X(WAO1)
+//X(WAO2)
+//X(WAO3)
+//X(WAO4)
+//X(WAO5)
+//X(WAO6)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+//X(WEQ)
+//X(WRSTI1)
+//X(WRSTI2)
+
+// XWRF
+X(XWRF)
+//X(I1)
+//X(I10)
+//X(I11)
+//X(I12)
+//X(I13)
+//X(I14)
+//X(I15)
+//X(I16)
+//X(I17)
+//X(I18)
+//X(I19)
+//X(I2)
+//X(I20)
+//X(I21)
+//X(I22)
+//X(I23)
+//X(I24)
+//X(I25)
+//X(I26)
+//X(I27)
+//X(I28)
+//X(I29)
+//X(I3)
+//X(I30)
+//X(I31)
+//X(I32)
+//X(I33)
+//X(I34)
+//X(I35)
+//X(I36)
+//X(I4)
+//X(I5)
+//X(I6)
+//X(I7)
+//X(I8)
+//X(I9)
+//X(O1)
+//X(O10)
+//X(O11)
+//X(O12)
+//X(O13)
+//X(O14)
+//X(O15)
+//X(O16)
+//X(O17)
+//X(O18)
+//X(O19)
+//X(O2)
+//X(O20)
+//X(O21)
+//X(O22)
+//X(O23)
+//X(O24)
+//X(O25)
+//X(O26)
+//X(O27)
+//X(O28)
+//X(O29)
+//X(O3)
+//X(O30)
+//X(O31)
+//X(O32)
+//X(O33)
+//X(O34)
+//X(O35)
+//X(O36)
+//X(O4)
+//X(O5)
+//X(O6)
+//X(O7)
+//X(O8)
+//X(O9)
+//X(RA1)
+//X(RA2)
+//X(RA3)
+//X(RA4)
+//X(RA5)
+//X(WA1)
+//X(WA2)
+//X(WA3)
+//X(WA4)
+//X(WA5)
+//X(WCK1)
+//X(WCK2)
+//X(WE)
+//X(WEA)
+
+// end of autogenerated items
+
+// start of generated parameter list
+// NX_BD
+X(NX_BD)
+X(mode)
+
+// NX_BFF
+X(NX_BFF)
+
+// NX_BFR
+X(NX_BFR)
+X(data_inv)
+X(iobname)
+X(location)
+//X(mode)
+X(path)
+X(ring)
+
+// NX_CDC_L
+X(NX_CDC_L)
+X(ack_sel)
+X(bck_sel)
+X(cck_sel)
+X(ck0_edge)
+X(ck1_edge)
+X(dck_sel)
+X(gt0_bypass_reg1)
+X(gt0_bypass_reg2)
+X(gt1_bypass_reg1)
+X(gt1_bypass_reg2)
+X(link_BA)
+X(link_CB)
+X(link_DC)
+//X(mode)
+X(use_adest_arst)
+X(use_asrc_arst)
+X(use_bdest_arst)
+X(use_bsrc_arst)
+X(use_cdest_arst)
+X(use_csrc_arst)
+X(use_ddest_arst)
+X(use_dsrc_arst)
+
+// NX_CDC_L_2DFF
+X(NX_CDC_L_2DFF)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(gt0_bypass_reg1)
+//X(gt0_bypass_reg2)
+//X(gt1_bypass_reg1)
+//X(gt1_bypass_reg2)
+//X(use_adest_arst)
+//X(use_bdest_arst)
+
+// NX_CDC_L_3DFF
+X(NX_CDC_L_3DFF)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(gt0_bypass_reg1)
+//X(gt0_bypass_reg2)
+//X(gt1_bypass_reg1)
+//X(gt1_bypass_reg2)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+
+// NX_CDC_L_BIN2GRAY
+X(NX_CDC_L_BIN2GRAY)
+
+// NX_CDC_L_FULL
+X(NX_CDC_L_FULL)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(gt0_bypass_reg1)
+//X(gt0_bypass_reg2)
+//X(gt1_bypass_reg1)
+//X(gt1_bypass_reg2)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+
+// NX_CDC_U
+X(NX_CDC_U)
+//X(ack_sel)
+//X(bck_sel)
+//X(cck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(dck_sel)
+//X(link_BA)
+//X(link_CB)
+//X(link_DC)
+//X(mode)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+//X(use_cdest_arst)
+//X(use_csrc_arst)
+//X(use_ddest_arst)
+//X(use_dsrc_arst)
+
+// NX_CDC_U_2DFF
+X(NX_CDC_U_2DFF)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(use_adest_arst)
+//X(use_bdest_arst)
+
+// NX_CDC_U_3DFF
+X(NX_CDC_U_3DFF)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+
+// NX_CDC_U_BIN2GRAY
+X(NX_CDC_U_BIN2GRAY)
+
+// NX_CDC_U_FULL
+X(NX_CDC_U_FULL)
+//X(ack_sel)
+//X(bck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+
+// NX_CDC_U_GRAY2BIN
+X(NX_CDC_U_GRAY2BIN)
+
+// NX_CKS
+X(NX_CKS)
+X(ck_edge)
+
+// NX_CKS_U
+X(NX_CKS_U)
+
+// NX_CMUX_U
+X(NX_CMUX_U)
+
+// NX_CRX_L
+X(NX_CRX_L)
+//X(location)
+X(pcs_8b_dscr_sel)
+X(pcs_align_bypass)
+X(pcs_buffers_bypass)
+X(pcs_buffers_use_cdc)
+X(pcs_bypass_pma_cdc)
+X(pcs_bypass_usr_cdc)
+X(pcs_comma_mask)
+X(pcs_debug_en)
+X(pcs_dec_bypass)
+X(pcs_dscr_bypass)
+X(pcs_el_buff_diff_bef_comp)
+X(pcs_el_buff_max_comp)
+X(pcs_el_buff_only_one_skp)
+X(pcs_el_buff_skp_char_0)
+X(pcs_el_buff_skp_char_1)
+X(pcs_el_buff_skp_char_2)
+X(pcs_el_buff_skp_char_3)
+X(pcs_el_buff_skp_header_0)
+X(pcs_el_buff_skp_header_1)
+X(pcs_el_buff_skp_header_2)
+X(pcs_el_buff_skp_header_3)
+X(pcs_el_buff_skp_header_size)
+X(pcs_el_buff_skp_seq_size)
+X(pcs_el_buff_underflow_handle)
+X(pcs_fsm_sel)
+X(pcs_fsm_watchdog_en)
+X(pcs_loopback)
+X(pcs_m_comma_en)
+X(pcs_m_comma_val)
+X(pcs_nb_comma_bef_realign)
+X(pcs_p_comma_en)
+X(pcs_p_comma_val)
+X(pcs_polarity)
+X(pcs_protocol_size)
+X(pcs_replace_bypass)
+X(pcs_sync_supported)
+X(pma_cdr_cp)
+X(pma_clk_pos)
+X(pma_ctrl_term)
+X(pma_loopback)
+X(pma_pll_cpump_n)
+X(pma_pll_divf)
+X(pma_pll_divf_en_n)
+X(pma_pll_divm)
+X(pma_pll_divm_en_n)
+X(pma_pll_divn)
+X(pma_pll_divn_en_n)
+X(test)
+
+// NX_CRX_U
+X(NX_CRX_U)
+X(gearbox_en)
+X(gearbox_mode)
+//X(location)
+//X(pcs_8b_dscr_sel)
+//X(pcs_align_bypass)
+//X(pcs_buffers_bypass)
+//X(pcs_buffers_use_cdc)
+//X(pcs_bypass_pma_cdc)
+//X(pcs_bypass_usr_cdc)
+//X(pcs_comma_mask)
+//X(pcs_debug_en)
+//X(pcs_dec_bypass)
+//X(pcs_dscr_bypass)
+//X(pcs_el_buff_diff_bef_comp)
+//X(pcs_el_buff_max_comp)
+//X(pcs_el_buff_only_one_skp)
+//X(pcs_el_buff_skp_char_0)
+//X(pcs_el_buff_skp_char_1)
+//X(pcs_el_buff_skp_char_2)
+//X(pcs_el_buff_skp_char_3)
+//X(pcs_el_buff_skp_header_0)
+//X(pcs_el_buff_skp_header_1)
+//X(pcs_el_buff_skp_header_2)
+//X(pcs_el_buff_skp_header_3)
+//X(pcs_el_buff_skp_header_size)
+//X(pcs_el_buff_skp_seq_size)
+//X(pcs_fsm_sel)
+//X(pcs_fsm_watchdog_en)
+//X(pcs_loopback)
+//X(pcs_m_comma_en)
+//X(pcs_m_comma_val)
+//X(pcs_nb_comma_bef_realign)
+//X(pcs_p_comma_en)
+//X(pcs_p_comma_val)
+//X(pcs_polarity)
+//X(pcs_protocol_size)
+//X(pcs_replace_bypass)
+//X(pcs_sync_supported)
+//X(pma_cdr_cp)
+//X(pma_clk_pos)
+X(pma_coarse_ppm)
+//X(pma_ctrl_term)
+X(pma_dco_divl)
+X(pma_dco_divm)
+X(pma_dco_divn)
+X(pma_dco_reg_res)
+X(pma_dco_vref_sel)
+X(pma_fine_ppm)
+//X(pma_loopback)
+X(pma_m_eye_ppm)
+X(pma_peak_detect_cmd)
+X(pma_peak_detect_on)
+//X(pma_pll_cpump_n)
+//X(pma_pll_divf)
+//X(pma_pll_divf_en_n)
+//X(pma_pll_divm)
+//X(pma_pll_divm_en_n)
+//X(pma_pll_divn)
+//X(pma_pll_divn_en_n)
+
+// NX_CTX_L
+X(NX_CTX_L)
+//X(location)
+X(pcs_8b_scr_sel)
+//X(pcs_bypass_pma_cdc)
+//X(pcs_bypass_usr_cdc)
+X(pcs_enc_bypass)
+X(pcs_esistream_fsm_en)
+//X(pcs_loopback)
+//X(pcs_polarity)
+//X(pcs_protocol_size)
+//X(pcs_replace_bypass)
+X(pcs_scr_bypass)
+X(pcs_scr_init)
+//X(pcs_sync_supported)
+//X(pma_clk_pos)
+//X(pma_loopback)
+//X(test)
+
+// NX_CTX_U
+X(NX_CTX_U)
+//X(gearbox_en)
+//X(gearbox_mode)
+//X(location)
+//X(pcs_8b_scr_sel)
+//X(pcs_bypass_pma_cdc)
+//X(pcs_bypass_usr_cdc)
+//X(pcs_enc_bypass)
+//X(pcs_esistream_fsm_en)
+//X(pcs_loopback)
+//X(pcs_polarity)
+//X(pcs_protocol_size)
+//X(pcs_replace_bypass)
+//X(pcs_scr_bypass)
+//X(pcs_scr_init)
+//X(pcs_sync_supported)
+//X(pma_clk_pos)
+//X(pma_loopback)
+
+// NX_CY
+X(NX_CY)
+X(add_carry)
+X(shifter)
+
+// NX_DES
+X(NX_DES)
+X(data_size)
+X(differential)
+X(dpath_dynamic)
+X(drive)
+X(inputDelayLine)
+X(inputSignalSlope)
+//X(location)
+X(locked)
+X(standard)
+X(termination)
+X(terminationReference)
+X(turbo)
+X(weakTermination)
+
+// NX_DFF
+X(NX_DFF)
+X(dff_ctxt)
+X(dff_edge)
+X(dff_init)
+X(dff_load)
+X(dff_sync)
+X(dff_type)
+
+// NX_DFR
+X(NX_DFR)
+//X(data_inv)
+//X(dff_edge)
+//X(dff_init)
+//X(dff_load)
+//X(dff_sync)
+//X(dff_type)
+//X(iobname)
+//X(location)
+//X(mode)
+//X(path)
+//X(ring)
+
+// NX_DDFR_U
+X(NX_DDFR_U)
+
+// NX_DSP
+X(NX_DSP)
+X(raw_config0)
+X(raw_config1)
+X(raw_config2)
+X(raw_config3)
+X(std_mode)
+
+// NX_DSP_L
+X(NX_DSP_L)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_config2)
+//X(raw_config3)
+//X(std_mode)
+
+// NX_DSP_L_SPLIT
+X(NX_DSP_L_SPLIT)
+X(ALU_DYNAMIC_OP)
+X(ALU_MUX)
+X(ALU_OP)
+X(CO_SEL)
+X(ENABLE_PR_ALU_RST)
+X(ENABLE_PR_A_RST)
+X(ENABLE_PR_B_RST)
+X(ENABLE_PR_CI_RST)
+X(ENABLE_PR_CO_RST)
+X(ENABLE_PR_C_RST)
+X(ENABLE_PR_D_RST)
+X(ENABLE_PR_MULT_RST)
+X(ENABLE_PR_OV_RST)
+X(ENABLE_PR_P_RST)
+X(ENABLE_PR_X_RST)
+X(ENABLE_PR_Y_RST)
+X(ENABLE_PR_Z_RST)
+X(ENABLE_SATURATION)
+X(MUX_A)
+X(MUX_B)
+X(MUX_CI)
+X(MUX_P)
+X(MUX_X)
+X(MUX_Y)
+X(MUX_Z)
+X(PRE_ADDER_OP)
+X(PR_ALU_MUX)
+X(PR_A_CASCADE_MUX)
+X(PR_A_MUX)
+X(PR_B_CASCADE_MUX)
+X(PR_B_MUX)
+X(PR_CI_MUX)
+X(PR_CO_MUX)
+X(PR_C_MUX)
+X(PR_D_MUX)
+X(PR_MULT_MUX)
+X(PR_OV_MUX)
+X(PR_P_MUX)
+X(PR_X_MUX)
+X(PR_Y_MUX)
+X(PR_Z_MUX)
+X(SATURATION_RANK)
+X(SIGNED_MODE)
+X(Z_FEEDBACK_SHL12)
+
+// NX_DSP_L_WRAP
+X(NX_DSP_L_WRAP)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_config2)
+//X(raw_config3)
+//X(std_mode)
+
+// NX_DSP_SPLIT
+X(NX_DSP_SPLIT)
+//X(ALU_DYNAMIC_OP)
+//X(ALU_MUX)
+//X(ALU_OP)
+//X(CO_SEL)
+//X(ENABLE_PR_ALU_RST)
+//X(ENABLE_PR_A_RST)
+//X(ENABLE_PR_B_RST)
+//X(ENABLE_PR_CI_RST)
+//X(ENABLE_PR_CO_RST)
+//X(ENABLE_PR_C_RST)
+//X(ENABLE_PR_D_RST)
+//X(ENABLE_PR_MULT_RST)
+//X(ENABLE_PR_OV_RST)
+//X(ENABLE_PR_P_RST)
+//X(ENABLE_PR_X_RST)
+//X(ENABLE_PR_Y_RST)
+//X(ENABLE_PR_Z_RST)
+//X(ENABLE_SATURATION)
+//X(MUX_A)
+//X(MUX_B)
+//X(MUX_CI)
+//X(MUX_P)
+//X(MUX_X)
+//X(MUX_Y)
+//X(MUX_Z)
+//X(PRE_ADDER_OP)
+//X(PR_ALU_MUX)
+//X(PR_A_CASCADE_MUX)
+//X(PR_A_MUX)
+//X(PR_B_CASCADE_MUX)
+//X(PR_B_MUX)
+//X(PR_CI_MUX)
+//X(PR_CO_MUX)
+//X(PR_C_MUX)
+//X(PR_D_MUX)
+//X(PR_MULT_MUX)
+//X(PR_OV_MUX)
+//X(PR_P_MUX)
+//X(PR_X_MUX)
+//X(PR_Y_MUX)
+//X(PR_Z_MUX)
+//X(SATURATION_RANK)
+//X(SIGNED_MODE)
+//X(Z_FEEDBACK_SHL12)
+
+// NX_DSP_U
+X(NX_DSP_U)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_config2)
+//X(raw_config3)
+//X(std_mode)
+
+// NX_DSP_U_SPLIT
+X(NX_DSP_U_SPLIT)
+//X(ALU_DYNAMIC_OP)
+//X(ALU_OP)
+//X(ENABLE_PR_A_RST)
+//X(ENABLE_PR_B_RST)
+X(ENABLE_PR_CCO_RST)
+//X(ENABLE_PR_CI_RST)
+//X(ENABLE_PR_CO_RST)
+X(ENABLE_PR_CZ_RST)
+//X(ENABLE_PR_C_RST)
+//X(ENABLE_PR_D_RST)
+//X(ENABLE_PR_MULT_RST)
+//X(ENABLE_PR_OV_RST)
+//X(ENABLE_PR_P_RST)
+//X(ENABLE_PR_X_RST)
+//X(ENABLE_PR_Y_RST)
+//X(ENABLE_PR_Z_RST)
+//X(ENABLE_SATURATION)
+X(INV_RST)
+X(INV_RSTZ)
+X(INV_WE)
+X(INV_WEZ)
+//X(MUX_A)
+//X(MUX_B)
+X(MUX_CCI)
+X(MUX_CCO)
+//X(MUX_CI)
+X(MUX_CZ)
+//X(MUX_P)
+//X(MUX_X)
+//X(MUX_Y)
+//X(MUX_Z)
+//X(PRE_ADDER_OP)
+//X(PR_A_CASCADE_MUX)
+//X(PR_A_MUX)
+//X(PR_B_CASCADE_MUX)
+//X(PR_B_MUX)
+X(PR_CCO_MUX)
+//X(PR_CI_MUX)
+//X(PR_CO_MUX)
+X(PR_CZ_MUX)
+//X(PR_C_MUX)
+//X(PR_D_MUX)
+//X(PR_MULT_MUX)
+//X(PR_OV_MUX)
+//X(PR_P_MUX)
+X(PR_RSTZ_MUX)
+X(PR_RST_MUX)
+X(PR_WEZ_MUX)
+X(PR_WE_MUX)
+//X(PR_X_MUX)
+//X(PR_Y_MUX)
+//X(PR_Z_MUX)
+//X(SATURATION_RANK)
+//X(SIGNED_MODE)
+
+// NX_DSP_U_WRAP
+X(NX_DSP_U_WRAP)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_config2)
+//X(raw_config3)
+//X(std_mode)
+
+// NX_DSP_WRAP
+X(NX_DSP_WRAP)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_config2)
+//X(raw_config3)
+//X(std_mode)
+
+// NX_ECC
+X(NX_ECC)
+
+// NX_FIFO_DPREG
+X(NX_FIFO_DPREG)
+X(rck_edge)
+X(read_addr_inv)
+X(use_read_arst)
+X(use_write_arst)
+X(wck_edge)
+
+// NX_FIFO_U
+X(NX_FIFO_U)
+//X(mode)
+//X(rck_edge)
+//X(read_addr_inv)
+//X(use_read_arst)
+//X(use_write_arst)
+//X(wck_edge)
+
+// NX_GCK_U
+X(NX_GCK_U)
+X(inv_in)
+X(inv_out)
+//X(std_mode)
+
+// NX_HSSL_L_FULL
+X(NX_HSSL_L_FULL)
+X(cfg_main_i)
+X(cfg_rx0_i)
+X(cfg_rx1_i)
+X(cfg_rx2_i)
+X(cfg_rx3_i)
+X(cfg_rx4_i)
+X(cfg_rx5_i)
+X(cfg_tx0_i)
+X(cfg_tx1_i)
+X(cfg_tx2_i)
+X(cfg_tx3_i)
+X(cfg_tx4_i)
+X(cfg_tx5_i)
+//X(location)
+
+// NX_HSSL_U_FULL
+X(NX_HSSL_U_FULL)
+X(cfg_dyn_all_rx_pma_m_eye_coarse_ena_i)
+X(cfg_dyn_all_rx_pma_m_eye_dn_i)
+X(cfg_dyn_all_rx_pma_m_eye_fine_ena_i)
+X(cfg_dyn_all_rx_pma_m_eye_i)
+X(cfg_dyn_all_rx_pma_m_eye_step_i)
+X(cfg_dyn_all_rx_pma_m_eye_up_i)
+X(cfg_dyn_all_rx_pma_threshold_1)
+X(cfg_dyn_all_rx_pma_threshold_2)
+X(cfg_dyn_all_rx_pma_trim_locked_i)
+X(cfg_dyn_all_rx_pma_trim_mode_i)
+X(cfg_dyn_all_rx_pma_trim_unlocked_i)
+X(cfg_dyn_rx0_pma_ctle_cap_p_i)
+X(cfg_dyn_rx0_pma_ctle_res_p_i)
+X(cfg_dyn_rx0_pma_dfe_idac_tap1_n_i)
+X(cfg_dyn_rx0_pma_dfe_idac_tap2_n_i)
+X(cfg_dyn_rx0_pma_dfe_idac_tap3_n_i)
+X(cfg_dyn_rx0_pma_dfe_idac_tap4_n_i)
+X(cfg_dyn_rx0_pma_termination_cmd_i)
+X(cfg_dyn_rx1_pma_ctle_cap_p_i)
+X(cfg_dyn_rx1_pma_ctle_res_p_i)
+X(cfg_dyn_rx1_pma_dfe_idac_tap1_n_i)
+X(cfg_dyn_rx1_pma_dfe_idac_tap2_n_i)
+X(cfg_dyn_rx1_pma_dfe_idac_tap3_n_i)
+X(cfg_dyn_rx1_pma_dfe_idac_tap4_n_i)
+X(cfg_dyn_rx1_pma_termination_cmd_i)
+X(cfg_dyn_rx2_pma_ctle_cap_p_i)
+X(cfg_dyn_rx2_pma_ctle_res_p_i)
+X(cfg_dyn_rx2_pma_dfe_idac_tap1_n_i)
+X(cfg_dyn_rx2_pma_dfe_idac_tap2_n_i)
+X(cfg_dyn_rx2_pma_dfe_idac_tap3_n_i)
+X(cfg_dyn_rx2_pma_dfe_idac_tap4_n_i)
+X(cfg_dyn_rx2_pma_termination_cmd_i)
+X(cfg_dyn_rx3_pma_ctle_cap_p_i)
+X(cfg_dyn_rx3_pma_ctle_res_p_i)
+X(cfg_dyn_rx3_pma_dfe_idac_tap1_n_i)
+X(cfg_dyn_rx3_pma_dfe_idac_tap2_n_i)
+X(cfg_dyn_rx3_pma_dfe_idac_tap3_n_i)
+X(cfg_dyn_rx3_pma_dfe_idac_tap4_n_i)
+X(cfg_dyn_rx3_pma_termination_cmd_i)
+X(cfg_dyn_tx0_pma_main_en_i)
+X(cfg_dyn_tx0_pma_main_sign_i)
+X(cfg_dyn_tx0_pma_margin_input_i)
+X(cfg_dyn_tx0_pma_margin_sel_i)
+X(cfg_dyn_tx0_pma_post_en_i)
+X(cfg_dyn_tx0_pma_post_sel_i)
+X(cfg_dyn_tx0_pma_post_sign_i)
+X(cfg_dyn_tx0_pma_pre_en_i)
+X(cfg_dyn_tx0_pma_pre_sel_i)
+X(cfg_dyn_tx0_pma_pre_sign_i)
+X(cfg_dyn_tx1_pma_main_en_i)
+X(cfg_dyn_tx1_pma_main_sign_i)
+X(cfg_dyn_tx1_pma_margin_input_i)
+X(cfg_dyn_tx1_pma_margin_sel_i)
+X(cfg_dyn_tx1_pma_post_en_i)
+X(cfg_dyn_tx1_pma_post_sel_i)
+X(cfg_dyn_tx1_pma_post_sign_i)
+X(cfg_dyn_tx1_pma_pre_en_i)
+X(cfg_dyn_tx1_pma_pre_sel_i)
+X(cfg_dyn_tx1_pma_pre_sign_i)
+X(cfg_dyn_tx2_pma_main_en_i)
+X(cfg_dyn_tx2_pma_main_sign_i)
+X(cfg_dyn_tx2_pma_margin_input_i)
+X(cfg_dyn_tx2_pma_margin_sel_i)
+X(cfg_dyn_tx2_pma_post_en_i)
+X(cfg_dyn_tx2_pma_post_sel_i)
+X(cfg_dyn_tx2_pma_post_sign_i)
+X(cfg_dyn_tx2_pma_pre_en_i)
+X(cfg_dyn_tx2_pma_pre_sel_i)
+X(cfg_dyn_tx2_pma_pre_sign_i)
+X(cfg_dyn_tx3_pma_main_en_i)
+X(cfg_dyn_tx3_pma_main_sign_i)
+X(cfg_dyn_tx3_pma_margin_input_i)
+X(cfg_dyn_tx3_pma_margin_sel_i)
+X(cfg_dyn_tx3_pma_post_en_i)
+X(cfg_dyn_tx3_pma_post_sel_i)
+X(cfg_dyn_tx3_pma_post_sign_i)
+X(cfg_dyn_tx3_pma_pre_en_i)
+X(cfg_dyn_tx3_pma_pre_sel_i)
+X(cfg_dyn_tx3_pma_pre_sign_i)
+X(cfg_main_clk_to_fabric_div_en_i)
+X(cfg_main_clk_to_fabric_div_mode_i)
+X(cfg_main_clk_to_fabric_sel_i)
+X(cfg_main_rclk_to_fabric_sel_i)
+X(cfg_main_use_only_usr_clock_i)
+X(cfg_pcs_ovs_en_i)
+X(cfg_pcs_ovs_mode_i)
+X(cfg_pcs_pll_lock_ppm_i)
+X(cfg_pcs_word_len_i)
+X(cfg_pll_pma_ckref_ext_i)
+X(cfg_pll_pma_cpump_i)
+X(cfg_pll_pma_divl_i)
+X(cfg_pll_pma_divm_i)
+X(cfg_pll_pma_divn_i)
+X(cfg_pll_pma_gbx_en_i)
+X(cfg_pll_pma_int_data_len_i)
+X(cfg_pll_pma_lvds_en_i)
+X(cfg_pll_pma_lvds_mux_i)
+X(cfg_pll_pma_mux_ckref_i)
+X(cfg_rx0_gearbox_en_i)
+X(cfg_rx0_gearbox_mode_i)
+X(cfg_rx0_pcs_8b_dscr_sel_i)
+X(cfg_rx0_pcs_align_bypass_i)
+X(cfg_rx0_pcs_buffers_bypass_i)
+X(cfg_rx0_pcs_buffers_use_cdc_i)
+X(cfg_rx0_pcs_bypass_pma_cdc_i)
+X(cfg_rx0_pcs_bypass_usr_cdc_i)
+X(cfg_rx0_pcs_comma_mask_i)
+X(cfg_rx0_pcs_debug_en_i)
+X(cfg_rx0_pcs_dec_bypass_i)
+X(cfg_rx0_pcs_dscr_bypass_i)
+X(cfg_rx0_pcs_el_buff_diff_bef_comp_i)
+X(cfg_rx0_pcs_el_buff_max_comp_i)
+X(cfg_rx0_pcs_el_buff_only_one_skp_i)
+X(cfg_rx0_pcs_el_buff_skp_char_0_i)
+X(cfg_rx0_pcs_el_buff_skp_char_1_i)
+X(cfg_rx0_pcs_el_buff_skp_char_2_i)
+X(cfg_rx0_pcs_el_buff_skp_char_3_i)
+X(cfg_rx0_pcs_el_buff_skp_header_0_i)
+X(cfg_rx0_pcs_el_buff_skp_header_1_i)
+X(cfg_rx0_pcs_el_buff_skp_header_2_i)
+X(cfg_rx0_pcs_el_buff_skp_header_3_i)
+X(cfg_rx0_pcs_el_buff_skp_header_size_i)
+X(cfg_rx0_pcs_el_buff_skp_seq_size_i)
+X(cfg_rx0_pcs_fsm_sel_i)
+X(cfg_rx0_pcs_fsm_watchdog_en_i)
+X(cfg_rx0_pcs_loopback_i)
+X(cfg_rx0_pcs_m_comma_en_i)
+X(cfg_rx0_pcs_m_comma_val_i)
+X(cfg_rx0_pcs_nb_comma_bef_realign_i)
+X(cfg_rx0_pcs_p_comma_en_i)
+X(cfg_rx0_pcs_p_comma_val_i)
+X(cfg_rx0_pcs_polarity_i)
+X(cfg_rx0_pcs_protocol_size_i)
+X(cfg_rx0_pcs_replace_bypass_i)
+X(cfg_rx0_pcs_sync_supported_i)
+X(cfg_rx0_pma_cdr_cp_i)
+X(cfg_rx0_pma_clk_pos_i)
+X(cfg_rx0_pma_coarse_ppm_i)
+X(cfg_rx0_pma_ctrl_term_i)
+X(cfg_rx0_pma_dco_divl_i)
+X(cfg_rx0_pma_dco_divm_i)
+X(cfg_rx0_pma_dco_divn_i)
+X(cfg_rx0_pma_dco_reg_res_i)
+X(cfg_rx0_pma_dco_vref_sel_i)
+X(cfg_rx0_pma_fine_ppm_i)
+X(cfg_rx0_pma_loopback_i)
+X(cfg_rx0_pma_m_eye_ppm_i)
+X(cfg_rx0_pma_peak_detect_cmd_i)
+X(cfg_rx0_pma_peak_detect_on_i)
+X(cfg_rx0_pma_pll_cpump_n_i)
+X(cfg_rx0_pma_pll_divf_en_n_i)
+X(cfg_rx0_pma_pll_divf_i)
+X(cfg_rx0_pma_pll_divm_en_n_i)
+X(cfg_rx0_pma_pll_divm_i)
+X(cfg_rx0_pma_pll_divn_en_n_i)
+X(cfg_rx0_pma_pll_divn_i)
+X(cfg_rx1_gearbox_en_i)
+X(cfg_rx1_gearbox_mode_i)
+X(cfg_rx1_pcs_8b_dscr_sel_i)
+X(cfg_rx1_pcs_align_bypass_i)
+X(cfg_rx1_pcs_buffers_bypass_i)
+X(cfg_rx1_pcs_buffers_use_cdc_i)
+X(cfg_rx1_pcs_bypass_pma_cdc_i)
+X(cfg_rx1_pcs_bypass_usr_cdc_i)
+X(cfg_rx1_pcs_comma_mask_i)
+X(cfg_rx1_pcs_debug_en_i)
+X(cfg_rx1_pcs_dec_bypass_i)
+X(cfg_rx1_pcs_dscr_bypass_i)
+X(cfg_rx1_pcs_el_buff_diff_bef_comp_i)
+X(cfg_rx1_pcs_el_buff_max_comp_i)
+X(cfg_rx1_pcs_el_buff_only_one_skp_i)
+X(cfg_rx1_pcs_el_buff_skp_char_0_i)
+X(cfg_rx1_pcs_el_buff_skp_char_1_i)
+X(cfg_rx1_pcs_el_buff_skp_char_2_i)
+X(cfg_rx1_pcs_el_buff_skp_char_3_i)
+X(cfg_rx1_pcs_el_buff_skp_header_0_i)
+X(cfg_rx1_pcs_el_buff_skp_header_1_i)
+X(cfg_rx1_pcs_el_buff_skp_header_2_i)
+X(cfg_rx1_pcs_el_buff_skp_header_3_i)
+X(cfg_rx1_pcs_el_buff_skp_header_size_i)
+X(cfg_rx1_pcs_el_buff_skp_seq_size_i)
+X(cfg_rx1_pcs_fsm_sel_i)
+X(cfg_rx1_pcs_fsm_watchdog_en_i)
+X(cfg_rx1_pcs_loopback_i)
+X(cfg_rx1_pcs_m_comma_en_i)
+X(cfg_rx1_pcs_m_comma_val_i)
+X(cfg_rx1_pcs_nb_comma_bef_realign_i)
+X(cfg_rx1_pcs_p_comma_en_i)
+X(cfg_rx1_pcs_p_comma_val_i)
+X(cfg_rx1_pcs_polarity_i)
+X(cfg_rx1_pcs_protocol_size_i)
+X(cfg_rx1_pcs_replace_bypass_i)
+X(cfg_rx1_pcs_sync_supported_i)
+X(cfg_rx1_pma_cdr_cp_i)
+X(cfg_rx1_pma_clk_pos_i)
+X(cfg_rx1_pma_coarse_ppm_i)
+X(cfg_rx1_pma_ctrl_term_i)
+X(cfg_rx1_pma_dco_divl_i)
+X(cfg_rx1_pma_dco_divm_i)
+X(cfg_rx1_pma_dco_divn_i)
+X(cfg_rx1_pma_dco_reg_res_i)
+X(cfg_rx1_pma_dco_vref_sel_i)
+X(cfg_rx1_pma_fine_ppm_i)
+X(cfg_rx1_pma_loopback_i)
+X(cfg_rx1_pma_m_eye_ppm_i)
+X(cfg_rx1_pma_peak_detect_cmd_i)
+X(cfg_rx1_pma_peak_detect_on_i)
+X(cfg_rx1_pma_pll_cpump_n_i)
+X(cfg_rx1_pma_pll_divf_en_n_i)
+X(cfg_rx1_pma_pll_divf_i)
+X(cfg_rx1_pma_pll_divm_en_n_i)
+X(cfg_rx1_pma_pll_divm_i)
+X(cfg_rx1_pma_pll_divn_en_n_i)
+X(cfg_rx1_pma_pll_divn_i)
+X(cfg_rx2_gearbox_en_i)
+X(cfg_rx2_gearbox_mode_i)
+X(cfg_rx2_pcs_8b_dscr_sel_i)
+X(cfg_rx2_pcs_align_bypass_i)
+X(cfg_rx2_pcs_buffers_bypass_i)
+X(cfg_rx2_pcs_buffers_use_cdc_i)
+X(cfg_rx2_pcs_bypass_pma_cdc_i)
+X(cfg_rx2_pcs_bypass_usr_cdc_i)
+X(cfg_rx2_pcs_comma_mask_i)
+X(cfg_rx2_pcs_debug_en_i)
+X(cfg_rx2_pcs_dec_bypass_i)
+X(cfg_rx2_pcs_dscr_bypass_i)
+X(cfg_rx2_pcs_el_buff_diff_bef_comp_i)
+X(cfg_rx2_pcs_el_buff_max_comp_i)
+X(cfg_rx2_pcs_el_buff_only_one_skp_i)
+X(cfg_rx2_pcs_el_buff_skp_char_0_i)
+X(cfg_rx2_pcs_el_buff_skp_char_1_i)
+X(cfg_rx2_pcs_el_buff_skp_char_2_i)
+X(cfg_rx2_pcs_el_buff_skp_char_3_i)
+X(cfg_rx2_pcs_el_buff_skp_header_0_i)
+X(cfg_rx2_pcs_el_buff_skp_header_1_i)
+X(cfg_rx2_pcs_el_buff_skp_header_2_i)
+X(cfg_rx2_pcs_el_buff_skp_header_3_i)
+X(cfg_rx2_pcs_el_buff_skp_header_size_i)
+X(cfg_rx2_pcs_el_buff_skp_seq_size_i)
+X(cfg_rx2_pcs_fsm_sel_i)
+X(cfg_rx2_pcs_fsm_watchdog_en_i)
+X(cfg_rx2_pcs_loopback_i)
+X(cfg_rx2_pcs_m_comma_en_i)
+X(cfg_rx2_pcs_m_comma_val_i)
+X(cfg_rx2_pcs_nb_comma_bef_realign_i)
+X(cfg_rx2_pcs_p_comma_en_i)
+X(cfg_rx2_pcs_p_comma_val_i)
+X(cfg_rx2_pcs_polarity_i)
+X(cfg_rx2_pcs_protocol_size_i)
+X(cfg_rx2_pcs_replace_bypass_i)
+X(cfg_rx2_pcs_sync_supported_i)
+X(cfg_rx2_pma_cdr_cp_i)
+X(cfg_rx2_pma_clk_pos_i)
+X(cfg_rx2_pma_coarse_ppm_i)
+X(cfg_rx2_pma_ctrl_term_i)
+X(cfg_rx2_pma_dco_divl_i)
+X(cfg_rx2_pma_dco_divm_i)
+X(cfg_rx2_pma_dco_divn_i)
+X(cfg_rx2_pma_dco_reg_res_i)
+X(cfg_rx2_pma_dco_vref_sel_i)
+X(cfg_rx2_pma_fine_ppm_i)
+X(cfg_rx2_pma_loopback_i)
+X(cfg_rx2_pma_m_eye_ppm_i)
+X(cfg_rx2_pma_peak_detect_cmd_i)
+X(cfg_rx2_pma_peak_detect_on_i)
+X(cfg_rx2_pma_pll_cpump_n_i)
+X(cfg_rx2_pma_pll_divf_en_n_i)
+X(cfg_rx2_pma_pll_divf_i)
+X(cfg_rx2_pma_pll_divm_en_n_i)
+X(cfg_rx2_pma_pll_divm_i)
+X(cfg_rx2_pma_pll_divn_en_n_i)
+X(cfg_rx2_pma_pll_divn_i)
+X(cfg_rx3_gearbox_en_i)
+X(cfg_rx3_gearbox_mode_i)
+X(cfg_rx3_pcs_8b_dscr_sel_i)
+X(cfg_rx3_pcs_align_bypass_i)
+X(cfg_rx3_pcs_buffers_bypass_i)
+X(cfg_rx3_pcs_buffers_use_cdc_i)
+X(cfg_rx3_pcs_bypass_pma_cdc_i)
+X(cfg_rx3_pcs_bypass_usr_cdc_i)
+X(cfg_rx3_pcs_comma_mask_i)
+X(cfg_rx3_pcs_debug_en_i)
+X(cfg_rx3_pcs_dec_bypass_i)
+X(cfg_rx3_pcs_dscr_bypass_i)
+X(cfg_rx3_pcs_el_buff_diff_bef_comp_i)
+X(cfg_rx3_pcs_el_buff_max_comp_i)
+X(cfg_rx3_pcs_el_buff_only_one_skp_i)
+X(cfg_rx3_pcs_el_buff_skp_char_0_i)
+X(cfg_rx3_pcs_el_buff_skp_char_1_i)
+X(cfg_rx3_pcs_el_buff_skp_char_2_i)
+X(cfg_rx3_pcs_el_buff_skp_char_3_i)
+X(cfg_rx3_pcs_el_buff_skp_header_0_i)
+X(cfg_rx3_pcs_el_buff_skp_header_1_i)
+X(cfg_rx3_pcs_el_buff_skp_header_2_i)
+X(cfg_rx3_pcs_el_buff_skp_header_3_i)
+X(cfg_rx3_pcs_el_buff_skp_header_size_i)
+X(cfg_rx3_pcs_el_buff_skp_seq_size_i)
+X(cfg_rx3_pcs_fsm_sel_i)
+X(cfg_rx3_pcs_fsm_watchdog_en_i)
+X(cfg_rx3_pcs_loopback_i)
+X(cfg_rx3_pcs_m_comma_en_i)
+X(cfg_rx3_pcs_m_comma_val_i)
+X(cfg_rx3_pcs_nb_comma_bef_realign_i)
+X(cfg_rx3_pcs_p_comma_en_i)
+X(cfg_rx3_pcs_p_comma_val_i)
+X(cfg_rx3_pcs_polarity_i)
+X(cfg_rx3_pcs_protocol_size_i)
+X(cfg_rx3_pcs_replace_bypass_i)
+X(cfg_rx3_pcs_sync_supported_i)
+X(cfg_rx3_pma_cdr_cp_i)
+X(cfg_rx3_pma_clk_pos_i)
+X(cfg_rx3_pma_coarse_ppm_i)
+X(cfg_rx3_pma_ctrl_term_i)
+X(cfg_rx3_pma_dco_divl_i)
+X(cfg_rx3_pma_dco_divm_i)
+X(cfg_rx3_pma_dco_divn_i)
+X(cfg_rx3_pma_dco_reg_res_i)
+X(cfg_rx3_pma_dco_vref_sel_i)
+X(cfg_rx3_pma_fine_ppm_i)
+X(cfg_rx3_pma_loopback_i)
+X(cfg_rx3_pma_m_eye_ppm_i)
+X(cfg_rx3_pma_peak_detect_cmd_i)
+X(cfg_rx3_pma_peak_detect_on_i)
+X(cfg_rx3_pma_pll_cpump_n_i)
+X(cfg_rx3_pma_pll_divf_en_n_i)
+X(cfg_rx3_pma_pll_divf_i)
+X(cfg_rx3_pma_pll_divm_en_n_i)
+X(cfg_rx3_pma_pll_divm_i)
+X(cfg_rx3_pma_pll_divn_en_n_i)
+X(cfg_rx3_pma_pll_divn_i)
+X(cfg_test_mode_i)
+X(cfg_tx0_gearbox_en_i)
+X(cfg_tx0_gearbox_mode_i)
+X(cfg_tx0_pcs_8b_scr_sel_i)
+X(cfg_tx0_pcs_bypass_pma_cdc_i)
+X(cfg_tx0_pcs_bypass_usr_cdc_i)
+X(cfg_tx0_pcs_enc_bypass_i)
+X(cfg_tx0_pcs_esistream_fsm_en_i)
+X(cfg_tx0_pcs_loopback_i)
+X(cfg_tx0_pcs_polarity_i)
+X(cfg_tx0_pcs_protocol_size_i)
+X(cfg_tx0_pcs_replace_bypass_i)
+X(cfg_tx0_pcs_scr_bypass_i)
+X(cfg_tx0_pcs_scr_init_i)
+X(cfg_tx0_pcs_sync_supported_i)
+X(cfg_tx0_pma_clk_pos_i)
+X(cfg_tx0_pma_loopback_i)
+X(cfg_tx1_gearbox_en_i)
+X(cfg_tx1_gearbox_mode_i)
+X(cfg_tx1_pcs_8b_scr_sel_i)
+X(cfg_tx1_pcs_bypass_pma_cdc_i)
+X(cfg_tx1_pcs_bypass_usr_cdc_i)
+X(cfg_tx1_pcs_enc_bypass_i)
+X(cfg_tx1_pcs_esistream_fsm_en_i)
+X(cfg_tx1_pcs_loopback_i)
+X(cfg_tx1_pcs_polarity_i)
+X(cfg_tx1_pcs_protocol_size_i)
+X(cfg_tx1_pcs_replace_bypass_i)
+X(cfg_tx1_pcs_scr_bypass_i)
+X(cfg_tx1_pcs_scr_init_i)
+X(cfg_tx1_pcs_sync_supported_i)
+X(cfg_tx1_pma_clk_pos_i)
+X(cfg_tx1_pma_loopback_i)
+X(cfg_tx2_gearbox_en_i)
+X(cfg_tx2_gearbox_mode_i)
+X(cfg_tx2_pcs_8b_scr_sel_i)
+X(cfg_tx2_pcs_bypass_pma_cdc_i)
+X(cfg_tx2_pcs_bypass_usr_cdc_i)
+X(cfg_tx2_pcs_enc_bypass_i)
+X(cfg_tx2_pcs_esistream_fsm_en_i)
+X(cfg_tx2_pcs_loopback_i)
+X(cfg_tx2_pcs_polarity_i)
+X(cfg_tx2_pcs_protocol_size_i)
+X(cfg_tx2_pcs_replace_bypass_i)
+X(cfg_tx2_pcs_scr_bypass_i)
+X(cfg_tx2_pcs_scr_init_i)
+X(cfg_tx2_pcs_sync_supported_i)
+X(cfg_tx2_pma_clk_pos_i)
+X(cfg_tx2_pma_loopback_i)
+X(cfg_tx3_gearbox_en_i)
+X(cfg_tx3_gearbox_mode_i)
+X(cfg_tx3_pcs_8b_scr_sel_i)
+X(cfg_tx3_pcs_bypass_pma_cdc_i)
+X(cfg_tx3_pcs_bypass_usr_cdc_i)
+X(cfg_tx3_pcs_enc_bypass_i)
+X(cfg_tx3_pcs_esistream_fsm_en_i)
+X(cfg_tx3_pcs_loopback_i)
+X(cfg_tx3_pcs_polarity_i)
+X(cfg_tx3_pcs_protocol_size_i)
+X(cfg_tx3_pcs_replace_bypass_i)
+X(cfg_tx3_pcs_scr_bypass_i)
+X(cfg_tx3_pcs_scr_init_i)
+X(cfg_tx3_pcs_sync_supported_i)
+X(cfg_tx3_pma_clk_pos_i)
+X(cfg_tx3_pma_loopback_i)
+//X(location)
+X(rx_usrclk_use_pcs_clk_2)
+X(tx_usrclk_use_pcs_clk_2)
+
+// NX_IOB
+X(NX_IOB)
+//X(differential)
+//X(drive)
+X(dynDrive)
+X(dynInput)
+X(dynTerm)
+X(extra)
+//X(inputDelayLine)
+X(inputDelayOn)
+//X(inputSignalSlope)
+//X(location)
+//X(locked)
+X(outputCapacity)
+X(outputDelayLine)
+X(outputDelayOn)
+X(slewRate)
+//X(standard)
+//X(termination)
+//X(terminationReference)
+//X(turbo)
+//X(weakTermination)
+
+// NX_IOB_I
+X(NX_IOB_I)
+//X(differential)
+//X(drive)
+//X(dynDrive)
+//X(dynInput)
+//X(dynTerm)
+//X(extra)
+//X(inputDelayLine)
+//X(inputDelayOn)
+//X(inputSignalSlope)
+//X(location)
+//X(locked)
+//X(outputCapacity)
+//X(outputDelayLine)
+//X(outputDelayOn)
+//X(slewRate)
+//X(standard)
+//X(termination)
+//X(terminationReference)
+//X(turbo)
+//X(weakTermination)
+
+// NX_IOB_O
+X(NX_IOB_O)
+//X(differential)
+//X(drive)
+//X(dynDrive)
+//X(dynInput)
+//X(dynTerm)
+//X(extra)
+//X(inputDelayLine)
+//X(inputDelayOn)
+//X(inputSignalSlope)
+//X(location)
+//X(locked)
+//X(outputCapacity)
+//X(outputDelayLine)
+//X(outputDelayOn)
+//X(slewRate)
+//X(standard)
+//X(termination)
+//X(terminationReference)
+//X(turbo)
+//X(weakTermination)
+
+// NX_IOM
+X(NX_IOM)
+X(div_rx1)
+X(div_rx2)
+X(div_tx1)
+X(div_tx2)
+X(mode_io_cal)
+X(mode_side1)
+X(mode_side2)
+X(pads_dict)
+X(pads_path)
+X(sel_clk_out1)
+X(sel_clk_out2)
+X(sel_clkr_rx1)
+X(sel_clkr_rx2)
+X(sel_clkw_rx1)
+X(sel_clkw_rx2)
+
+// NX_IOM_BIN2GRP
+X(NX_IOM_BIN2GRP)
+
+// NX_IOM_CONTROL
+X(NX_IOM_CONTROL)
+//X(div_rx1)
+//X(div_rx2)
+//X(div_tx1)
+//X(div_tx2)
+X(inv_di_fclk1)
+X(inv_di_fclk2)
+X(latency1)
+X(latency2)
+//X(location)
+X(mode_cpath)
+X(mode_epath)
+//X(mode_io_cal)
+X(mode_rpath)
+//X(mode_side1)
+//X(mode_side2)
+X(mode_tpath)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+//X(sel_clkr_rx1)
+//X(sel_clkr_rx2)
+//X(sel_clkw_rx1)
+//X(sel_clkw_rx2)
+
+// NX_IOM_CONTROL_L
+X(NX_IOM_CONTROL_L)
+//X(div_rx1)
+//X(div_rx2)
+//X(div_tx1)
+//X(div_tx2)
+//X(inv_di_fclk1)
+//X(inv_di_fclk2)
+//X(latency1)
+//X(latency2)
+//X(location)
+//X(mode_cpath)
+//X(mode_epath)
+//X(mode_io_cal)
+//X(mode_rpath)
+//X(mode_side1)
+//X(mode_side2)
+//X(mode_tpath)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+//X(sel_clkr_rx1)
+//X(sel_clkr_rx2)
+//X(sel_clkw_rx1)
+//X(sel_clkw_rx2)
+
+// NX_IOM_CONTROL_M
+X(NX_IOM_CONTROL_M)
+//X(div_rx1)
+//X(div_rx2)
+//X(div_tx1)
+//X(div_tx2)
+//X(inv_di_fclk1)
+//X(inv_di_fclk2)
+//X(latency1)
+//X(latency2)
+//X(location)
+//X(mode_cpath)
+//X(mode_epath)
+//X(mode_io_cal)
+//X(mode_rpath)
+//X(mode_side1)
+//X(mode_side2)
+//X(mode_tpath)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+//X(sel_clkr_rx1)
+//X(sel_clkr_rx2)
+//X(sel_clkw_rx1)
+//X(sel_clkw_rx2)
+
+// NX_IOM_CONTROL_U
+X(NX_IOM_CONTROL_U)
+X(cal_delay1)
+X(cal_delay2)
+X(div1)
+X(div2)
+X(div3)
+X(div_swrx1)
+X(div_swrx2)
+X(inv_ld_sck1)
+X(inv_ld_sck2)
+X(inv_ld_sck3)
+X(link_ld_12)
+X(link_ld_23)
+//X(location)
+//X(mode_side1)
+//X(mode_side2)
+X(mode_side3)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+X(sel_dc_clk)
+X(sel_ld_fck1)
+X(sel_ld_fck2)
+X(sel_ld_fck3)
+X(sel_sw_fck1)
+X(sel_sw_fck2)
+X(use_dc)
+
+// NX_IOM_DRIVER
+X(NX_IOM_DRIVER)
+X(chained)
+X(cpath_edge)
+X(cpath_init)
+X(cpath_inv)
+X(cpath_load)
+X(cpath_mode)
+X(cpath_sync)
+X(epath_dynamic)
+X(epath_edge)
+X(epath_init)
+X(epath_load)
+X(epath_mode)
+X(epath_sync)
+//X(location)
+X(rpath_dynamic)
+X(rpath_edge)
+X(rpath_init)
+X(rpath_load)
+X(rpath_mode)
+X(rpath_sync)
+X(symbol)
+X(tpath_mode)
+X(variant)
+
+// NX_IOM_DRIVER_M
+X(NX_IOM_DRIVER_M)
+//X(chained)
+//X(cpath_edge)
+//X(cpath_init)
+//X(cpath_inv)
+//X(cpath_load)
+//X(cpath_mode)
+//X(cpath_sync)
+//X(epath_dynamic)
+//X(epath_edge)
+//X(epath_init)
+//X(epath_load)
+//X(epath_mode)
+//X(epath_sync)
+//X(location)
+//X(rpath_dynamic)
+//X(rpath_edge)
+//X(rpath_init)
+//X(rpath_load)
+//X(rpath_mode)
+//X(rpath_sync)
+//X(symbol)
+//X(tpath_mode)
+//X(variant)
+
+// NX_IOM_DRIVER_U
+X(NX_IOM_DRIVER_U)
+//X(chained)
+//X(cpath_edge)
+//X(cpath_init)
+//X(cpath_inv)
+//X(cpath_load)
+//X(cpath_mode)
+//X(cpath_sync)
+X(cpath_type)
+//X(epath_dynamic)
+//X(epath_edge)
+//X(epath_init)
+//X(epath_load)
+//X(epath_mode)
+//X(epath_sync)
+X(epath_type)
+//X(location)
+//X(rpath_dynamic)
+//X(rpath_edge)
+//X(rpath_init)
+//X(rpath_load)
+//X(rpath_mode)
+//X(rpath_sync)
+X(rpath_type)
+//X(symbol)
+//X(tpath_mode)
+
+// NX_IOM_L
+X(NX_IOM_L)
+//X(div_rx1)
+//X(div_rx2)
+//X(div_tx1)
+//X(div_tx2)
+//X(mode_io_cal)
+//X(mode_side1)
+//X(mode_side2)
+//X(pads_dict)
+//X(pads_path)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+//X(sel_clkr_rx1)
+//X(sel_clkr_rx2)
+//X(sel_clkw_rx1)
+//X(sel_clkw_rx2)
+
+// NX_IOM_SERDES
+X(NX_IOM_SERDES)
+//X(data_size)
+//X(location)
+
+// NX_IOM_SERDES_M
+X(NX_IOM_SERDES_M)
+//X(data_size)
+//X(location)
+
+// NX_IOM_SERDES_U
+X(NX_IOM_SERDES_U)
+//X(data_size)
+//X(location)
+
+// NX_IOM_U
+X(NX_IOM_U)
+//X(cal_delay1)
+//X(cal_delay2)
+//X(div1)
+//X(div2)
+//X(div3)
+//X(div_swrx1)
+//X(div_swrx2)
+//X(inv_ld_sck1)
+//X(inv_ld_sck2)
+//X(inv_ld_sck3)
+//X(link_ld_12)
+//X(link_ld_23)
+//X(mode_side1)
+//X(mode_side2)
+//X(mode_side3)
+//X(pads_dict)
+//X(pads_path)
+//X(sel_clk_out1)
+//X(sel_clk_out2)
+//X(sel_dc_clk)
+//X(sel_ld_fck1)
+//X(sel_ld_fck2)
+//X(sel_ld_fck3)
+//X(sel_sw_fck1)
+//X(sel_sw_fck2)
+//X(use_dc)
+
+// NX_LUT
+X(NX_LUT)
+X(lut_table)
+
+// NX_PLL
+X(NX_PLL)
+X(clk_outdiv1)
+X(clk_outdiv2)
+X(clk_outdiv3)
+X(ext_fbk_on)
+X(fbk_delay)
+X(fbk_delay_on)
+X(fbk_div_on)
+X(fbk_intdiv)
+//X(location)
+X(ref_div_on)
+X(vco_range)
+
+// NX_PLL_L
+X(NX_PLL_L)
+X(cfg_use_pll)
+X(clk_outdivo1)
+X(clk_outdivp1)
+X(clk_outdivp2)
+X(clk_outdivp3o2)
+//X(ext_fbk_on)
+//X(fbk_delay)
+//X(fbk_delay_on)
+//X(fbk_intdiv)
+//X(location)
+X(pll_cpump)
+X(ref_intdiv)
+X(ref_osc_on)
+X(wfg_sync_cal_lock)
+X(wfg_sync_pll_lock)
+
+// NX_PLL_U
+X(NX_PLL_U)
+X(cal_delay)
+X(cal_div)
+X(clk_cal_sel)
+//X(clk_outdiv1)
+//X(clk_outdiv2)
+//X(clk_outdiv3)
+X(clk_outdiv4)
+X(clk_outdivd1)
+X(clk_outdivd2)
+X(clk_outdivd3)
+X(clk_outdivd4)
+X(clk_outdivd5)
+//X(ext_fbk_on)
+//X(fbk_delay)
+//X(fbk_delay_on)
+//X(fbk_intdiv)
+//X(location)
+//X(pll_cpump)
+X(pll_lock)
+X(pll_lpf_cap)
+X(pll_lpf_res)
+X(pll_odf)
+//X(ref_intdiv)
+//X(ref_osc_on)
+X(use_cal)
+X(use_pll)
+
+// NX_PLL_U_WRAP
+X(NX_PLL_U_WRAP)
+//X(cal_delay)
+//X(cal_div)
+//X(clk_cal_sel)
+//X(clk_outdiv1)
+//X(clk_outdiv2)
+//X(clk_outdiv3)
+//X(clk_outdiv4)
+//X(clk_outdivd1)
+//X(clk_outdivd2)
+//X(clk_outdivd3)
+//X(clk_outdivd4)
+//X(clk_outdivd5)
+//X(ext_fbk_on)
+//X(fbk_delay)
+//X(fbk_delay_on)
+//X(fbk_intdiv)
+//X(location)
+//X(pll_cpump)
+//X(pll_lock)
+//X(pll_lpf_cap)
+//X(pll_lpf_res)
+//X(pll_odf)
+//X(ref_intdiv)
+//X(ref_osc_on)
+//X(use_cal)
+//X(use_pll)
+
+// NX_PMA_L
+X(NX_PMA_L)
+//X(location)
+X(main_clk_to_fabric_div_en)
+X(main_clk_to_fabric_div_mode)
+X(main_clk_to_fabric_sel)
+X(main_test)
+X(main_use_only_usr_clock)
+X(main_use_pcs_clk_2)
+X(pcs_ovs_mode)
+X(pcs_pll_lock_count)
+X(pcs_word_len)
+X(pll_pma_cpump_n)
+X(pll_pma_divf)
+X(pll_pma_divf_en_n)
+X(pll_pma_divm)
+X(pll_pma_divm_en_n)
+X(pll_pma_divn)
+X(pll_pma_divn_en_n)
+X(pll_pma_int_data_len)
+X(pll_pma_lvds_mux)
+X(pll_pma_mux_ckref)
+X(rx_pma_half_step)
+
+// NX_PMA_U
+X(NX_PMA_U)
+X(dyn_all_rx_pma_m_eye)
+X(dyn_all_rx_pma_m_eye_coarse_ena)
+X(dyn_all_rx_pma_m_eye_dn)
+X(dyn_all_rx_pma_m_eye_fine_ena)
+X(dyn_all_rx_pma_m_eye_step)
+X(dyn_all_rx_pma_m_eye_up)
+X(dyn_all_rx_pma_threshold_1)
+X(dyn_all_rx_pma_threshold_2)
+X(dyn_all_rx_pma_trim_locked)
+X(dyn_all_rx_pma_trim_mode)
+X(dyn_all_rx_pma_trim_unlocked)
+X(dyn_rx0_pma_ctle_cap_p)
+X(dyn_rx0_pma_ctle_res_p)
+X(dyn_rx0_pma_dfe_idac_tap1_n)
+X(dyn_rx0_pma_dfe_idac_tap2_n)
+X(dyn_rx0_pma_dfe_idac_tap3_n)
+X(dyn_rx0_pma_dfe_idac_tap4_n)
+X(dyn_rx0_pma_termination_cmd)
+X(dyn_rx1_pma_ctle_cap_p)
+X(dyn_rx1_pma_ctle_res_p)
+X(dyn_rx1_pma_dfe_idac_tap1_n)
+X(dyn_rx1_pma_dfe_idac_tap2_n)
+X(dyn_rx1_pma_dfe_idac_tap3_n)
+X(dyn_rx1_pma_dfe_idac_tap4_n)
+X(dyn_rx1_pma_termination_cmd)
+X(dyn_rx2_pma_ctle_cap_p)
+X(dyn_rx2_pma_ctle_res_p)
+X(dyn_rx2_pma_dfe_idac_tap1_n)
+X(dyn_rx2_pma_dfe_idac_tap2_n)
+X(dyn_rx2_pma_dfe_idac_tap3_n)
+X(dyn_rx2_pma_dfe_idac_tap4_n)
+X(dyn_rx2_pma_termination_cmd)
+X(dyn_rx3_pma_ctle_cap_p)
+X(dyn_rx3_pma_ctle_res_p)
+X(dyn_rx3_pma_dfe_idac_tap1_n)
+X(dyn_rx3_pma_dfe_idac_tap2_n)
+X(dyn_rx3_pma_dfe_idac_tap3_n)
+X(dyn_rx3_pma_dfe_idac_tap4_n)
+X(dyn_rx3_pma_termination_cmd)
+X(dyn_tx0_pma_main_en)
+X(dyn_tx0_pma_main_sign)
+X(dyn_tx0_pma_margin_input)
+X(dyn_tx0_pma_margin_sel)
+X(dyn_tx0_pma_post_en)
+X(dyn_tx0_pma_post_sel)
+X(dyn_tx0_pma_post_sign)
+X(dyn_tx0_pma_pre_en)
+X(dyn_tx0_pma_pre_sel)
+X(dyn_tx0_pma_pre_sign)
+X(dyn_tx1_pma_main_en)
+X(dyn_tx1_pma_main_sign)
+X(dyn_tx1_pma_margin_input)
+X(dyn_tx1_pma_margin_sel)
+X(dyn_tx1_pma_post_en)
+X(dyn_tx1_pma_post_sel)
+X(dyn_tx1_pma_post_sign)
+X(dyn_tx1_pma_pre_en)
+X(dyn_tx1_pma_pre_sel)
+X(dyn_tx1_pma_pre_sign)
+X(dyn_tx2_pma_main_en)
+X(dyn_tx2_pma_main_sign)
+X(dyn_tx2_pma_margin_input)
+X(dyn_tx2_pma_margin_sel)
+X(dyn_tx2_pma_post_en)
+X(dyn_tx2_pma_post_sel)
+X(dyn_tx2_pma_post_sign)
+X(dyn_tx2_pma_pre_en)
+X(dyn_tx2_pma_pre_sel)
+X(dyn_tx2_pma_pre_sign)
+X(dyn_tx3_pma_main_en)
+X(dyn_tx3_pma_main_sign)
+X(dyn_tx3_pma_margin_input)
+X(dyn_tx3_pma_margin_sel)
+X(dyn_tx3_pma_post_en)
+X(dyn_tx3_pma_post_sel)
+X(dyn_tx3_pma_post_sign)
+X(dyn_tx3_pma_pre_en)
+X(dyn_tx3_pma_pre_sel)
+X(dyn_tx3_pma_pre_sign)
+//X(location)
+//X(main_clk_to_fabric_div_en)
+//X(main_clk_to_fabric_div_mode)
+//X(main_clk_to_fabric_sel)
+X(main_rclk_to_fabric_sel)
+//X(main_use_only_usr_clock)
+X(pcs_ovs_en)
+//X(pcs_ovs_mode)
+X(pcs_pll_lock_ppm)
+//X(pcs_word_len)
+X(pll_pma_ckref_ext)
+X(pll_pma_cpump)
+X(pll_pma_divl)
+//X(pll_pma_divm)
+//X(pll_pma_divn)
+X(pll_pma_gbx_en)
+//X(pll_pma_int_data_len)
+X(pll_pma_lvds_en)
+//X(pll_pma_lvds_mux)
+//X(pll_pma_mux_ckref)
+//X(rx_usrclk_use_pcs_clk_2)
+X(test_mode)
+//X(tx_usrclk_use_pcs_clk_2)
+
+// NX_R5_L
+X(NX_R5_L)
+
+// NX_R5_L_WRAP
+X(NX_R5_L_WRAP)
+
+// NX_RAM
+X(NX_RAM)
+X(mcka_edge)
+X(mckb_edge)
+X(mem_ctxt)
+X(pcka_edge)
+X(pckb_edge)
+X(pipe_ia)
+X(pipe_ib)
+X(pipe_oa)
+X(pipe_ob)
+//X(raw_config0)
+//X(raw_config1)
+X(raw_l_enable)
+X(raw_l_extend)
+X(raw_u_enable)
+X(raw_u_extend)
+//X(std_mode)
+
+// NX_RAM_SLOWECC_1K_36_1r1w
+X(NX_RAM_SLOWECC_1K_36_1r1w)
+//X(mem_ctxt)
+
+// NX_RAM_WRAP
+X(NX_RAM_WRAP)
+//X(mcka_edge)
+//X(mckb_edge)
+//X(mem_ctxt)
+//X(pcka_edge)
+//X(pckb_edge)
+//X(pipe_ia)
+//X(pipe_ib)
+//X(pipe_oa)
+//X(pipe_ob)
+//X(raw_config0)
+//X(raw_config1)
+//X(raw_l_enable)
+//X(raw_l_extend)
+//X(raw_u_enable)
+//X(raw_u_extend)
+//X(std_mode)
+
+// NX_RB
+X(NX_RB)
+X(inputBypass)
+X(inputClk)
+X(inputContext)
+X(outputBypass)
+X(outputClk)
+X(outputContext)
+
+// NX_RB_WRAP
+X(NX_RB_WRAP)
+//X(inputBypass)
+//X(inputClk)
+//X(inputContext)
+//X(outputBypass)
+//X(outputClk)
+//X(outputContext)
+
+// NX_RFB
+X(NX_RFB)
+X(addr_mask)
+//X(mem_ctxt)
+//X(rck_edge)
+//X(wck_edge)
+X(we_mask)
+X(wea_mask)
+
+// NX_RFBDP_U_WRAP
+X(NX_RFBDP_U_WRAP)
+//X(mem_ctxt)
+//X(wck_edge)
+
+// NX_RFBSP_U_WRAP
+X(NX_RFBSP_U_WRAP)
+//X(mem_ctxt)
+//X(wck_edge)
+
+// NX_RFB_L
+X(NX_RFB_L)
+//X(mem_ctxt)
+//X(mode)
+//X(rck_edge)
+//X(wck_edge)
+
+// NX_RFB_L_WRAP
+X(NX_RFB_L_WRAP)
+//X(mem_ctxt)
+//X(mode)
+//X(rck_edge)
+//X(wck_edge)
+
+// NX_RFB_M
+X(NX_RFB_M)
+//X(mem_ctxt)
+//X(rck_edge)
+//X(wck_edge)
+
+// NX_RFB_U
+X(NX_RFB_U)
+//X(mem_ctxt)
+//X(mode)
+//X(wck_edge)
+
+// NX_RFB_WRAP
+X(NX_RFB_WRAP)
+//X(mem_ctxt)
+//X(rck_edge)
+//X(wck_edge)
+
+// NX_SER
+X(NX_SER)
+//X(data_size)
+//X(differential)
+//X(drive)
+//X(location)
+//X(locked)
+//X(outputCapacity)
+//X(outputDelayLine)
+//X(slewRate)
+X(spath_dynamic)
+//X(standard)
+
+// NX_SERDES
+X(NX_SERDES)
+X(cpath_registered)
+//X(data_size)
+//X(differential)
+//X(dpath_dynamic)
+//X(drive)
+//X(inputDelayLine)
+//X(inputSignalSlope)
+//X(location)
+//X(locked)
+//X(outputCapacity)
+//X(outputDelayLine)
+//X(slewRate)
+//X(spath_dynamic)
+//X(standard)
+//X(termination)
+//X(terminationReference)
+//X(turbo)
+//X(weakTermination)
+
+// NX_WFG
+X(NX_WFG)
+X(delay)
+X(delay_on)
+//X(location)
+//X(mode)
+X(pattern)
+X(pattern_end)
+X(wfg_edge)
+
+// NX_WFG_L
+X(NX_WFG_L)
+//X(delay)
+//X(delay_on)
+//X(location)
+//X(mode)
+//X(pattern)
+//X(pattern_end)
+//X(wfg_edge)
+
+// NX_WFG_U
+X(NX_WFG_U)
+//X(delay)
+//X(delay_on)
+X(div_phase)
+X(div_ratio)
+//X(location)
+//X(mode)
+//X(pattern)
+//X(pattern_end)
+X(reset_on_cal_lock_n)
+X(reset_on_pll_lock_n)
+X(reset_on_pll_locka_n)
+//X(wfg_edge)
+
+// NX_XCDC_U
+X(NX_XCDC_U)
+//X(ack_sel)
+//X(bck_sel)
+//X(cck_sel)
+//X(ck0_edge)
+//X(ck1_edge)
+//X(dck_sel)
+//X(link_BA)
+//X(link_CB)
+//X(link_DC)
+//X(use_adest_arst)
+//X(use_asrc_arst)
+//X(use_bdest_arst)
+//X(use_bsrc_arst)
+//X(use_cdest_arst)
+//X(use_csrc_arst)
+//X(use_ddest_arst)
+//X(use_dsrc_arst)
+
+// NX_XFIFO_32x36
+X(NX_XFIFO_32x36)
+//X(rck_edge)
+//X(read_addr_inv)
+//X(use_read_arst)
+//X(use_write_arst)
+//X(wck_edge)
+
+// NX_XFIFO_64x18
+X(NX_XFIFO_64x18)
+//X(rck_edge)
+//X(read_addr_inv)
+//X(use_read_arst)
+//X(use_write_arst)
+//X(wck_edge)
+
+// NX_XRFB_2R_1W
+X(NX_XRFB_2R_1W)
+//X(mem_ctxt)
+//X(wck_edge)
+
+// NX_XRFB_32x36
+X(NX_XRFB_32x36)
+//X(mem_ctxt)
+//X(wck_edge)
+
+// NX_XRFB_64x18
+X(NX_XRFB_64x18)
+//X(mem_ctxt)
+//X(wck_edge)
+
+// end of generated parameter list
+
+// IO location attribute
+X(LOC)
+
+X(lut_used)
+X(dff_used)
+
+X(type)
+
+// Timing
+X(BEYOND_FE_LUT)
+
+// csv 
+X(registered)
diff --git a/himbaechel/uarch/ng-ultra/csv.cc b/himbaechel/uarch/ng-ultra/csv.cc
new file mode 100644
index 0000000000..32e0861a6e
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/csv.cc
@@ -0,0 +1,304 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/algorithm/string.hpp>
+#include <fstream>
+#include <regex>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "ng_ultra.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void NgUltraImpl::parse_csv(const std::string &filename)
+{
+    std::ifstream in(filename);
+    if (!in)
+        log_error("failed to open CSV file '%s'\n", filename.c_str());
+    log_info("Parsing CSV file..\n");
+    std::string line;
+    std::string linebuf;
+    int lineno = 0;
+    enum uint8_t
+    {
+        IO_PADS = 0,
+        IO_BANKS,
+        IO_GCKS,
+        IO_ERROR
+    } line_type;
+
+    auto isempty = [](const std::string &str) {
+        return std::all_of(str.begin(), str.end(), [](char c) { return std::isspace(c); });
+    };
+    auto is_number = [](const std::string &str) {
+        return !str.empty() && std::all_of(str.begin(), str.end(), ::isdigit);
+    };
+    auto get_cells = [&](std::string str) {
+        std::vector<CellInfo *> tgt_cells;
+        IdString cellname = ctx->id(str);
+        if (ctx->cells.count(cellname))
+            tgt_cells.push_back(ctx->cells.at(cellname).get());
+        return tgt_cells;
+    };
+
+    line_type = IO_PADS;
+    pool<std::string> banks_used;
+    bool old_format = false;
+    while (std::getline(in, line)) {
+        ++lineno;
+        // Trim comments, from # until end of the line
+        size_t cstart = line.find('#');
+        if (cstart != std::string::npos)
+            line = line.substr(0, cstart);
+        if (isempty(line))
+            continue;
+
+        std::vector<std::string> arguments;
+        boost::split(arguments, line, boost::is_any_of(","));
+        if (arguments.empty())
+            continue;
+        switch (line_type) {
+        case IO_PADS: {
+            if (arguments.size() == 1 && arguments[0][0] == '!') {
+                line_type = IO_BANKS;
+                continue;
+            }
+            if (arguments.size() != 15)
+                log_error("number of parameters in line %d must be 15\n", lineno);
+
+            std::string arg_iobname = arguments.at(0);
+            std::string arg_location = arguments.at(1);
+            std::string arg_standard = arguments.at(2);
+            std::string arg_drive = arguments.at(3);
+            std::string arg_slewRate = arguments.at(4);
+            std::string arg_inputDelayLine = arguments.at(5);
+            std::string arg_outputDelayLine = arguments.at(6);
+            std::string arg_differential = arguments.at(7);
+            std::string arg_weakTermination = arguments.at(8);
+            std::string arg_termination = arguments.at(9);
+            std::string arg_terminationReference = arguments.at(10);
+            std::string arg_turbo = arguments.at(11);
+            std::string arg_inputSignalSlope = arguments.at(12);
+            std::string arg_outputCapacity = arguments.at(13);
+            std::string arg_registered = arguments.at(14);
+
+            // TODO: Remove this block
+            const std::vector<std::string> weak_values_check = {"None", "PullDown", "PullUp", "Keeper"};
+            auto it2 = std::find(std::begin(weak_values_check), std::end(weak_values_check), arguments.at(4));
+            if (it2 != std::end(weak_values_check)) {
+                if (!old_format) {
+                    log_warning("Old CSV format detected. Please update file.\n");
+                    old_format = true;
+                }
+                arg_weakTermination = arguments.at(4);
+                arg_slewRate = arguments.at(5);
+                arg_termination = arguments.at(6);
+                arg_inputDelayLine = arguments.at(7);
+                arg_outputDelayLine = arguments.at(8);
+                arg_differential = arguments.at(9);
+            }
+            // End of block
+
+            if (!(boost::starts_with(arg_location, "IOB") && boost::contains(arg_location, "_D")))
+                log_error("invalid location name '%s' must start with 'IOB' in line %d\n", arg_location.c_str(),
+                          lineno);
+
+            const std::vector<std::string> standard_values = {"LVDS", "LVCMOS", "SSTL", "HSTL"}; // , "POD"
+            auto it = std::find(std::begin(standard_values), std::end(standard_values), arg_standard);
+            if (it == std::end(standard_values))
+                log_error("unknown standard value '%s' in line %d\n", arg_standard.c_str(), lineno);
+
+            const std::vector<std::string> drive_values = {"2mA",  "4mA",   "8mA",      "16mA",
+                                                           "CatI", "CatII", "Undefined"}; // "6mA", "12mA",
+            it = std::find(std::begin(drive_values), std::end(drive_values), arg_drive);
+            if (it == std::end(drive_values))
+                log_error("unknown drive value '%s' in line %d\n", arg_drive.c_str(), lineno);
+
+            const std::vector<std::string> slew_values = {"Slow", "Medium", "Fast"};
+            it = std::find(std::begin(slew_values), std::end(slew_values), arg_slewRate);
+            if (it == std::end(slew_values))
+                log_error("unknown weak termination value '%s' in line %d\n", arg_slewRate.c_str(), lineno);
+
+            if (!is_number(arg_inputDelayLine)) {
+                log_error("input delay must be number, value '%s' in line %d\n", arg_inputDelayLine.c_str(), lineno);
+            } else {
+                int delay = std::stoi(arg_inputDelayLine);
+                if (delay < 0 || delay > 63)
+                    log_error("input delay value must be in range from 0 to 63 in line %d\n", lineno);
+            }
+            if (!is_number(arg_outputDelayLine)) {
+                log_error("output delay must be number, value '%s' in line %d\n", arg_outputDelayLine.c_str(), lineno);
+            } else {
+                int delay = std::stoi(arg_outputDelayLine);
+                if (delay < 0 || delay > 63)
+                    log_error("output delay value must be in range from 0 to 63 in line %d\n", lineno);
+            }
+
+            if (!arg_differential.empty() && arg_differential != "True" && arg_differential != "False")
+                log_error("differential must be boolean, value '%s' in line %d\n", arg_differential.c_str(), lineno);
+
+            const std::vector<std::string> weak_values = {"None", "PullDown", "PullUp", "Keeper"};
+            it = std::find(std::begin(weak_values), std::end(weak_values), arg_weakTermination);
+            if (it == std::end(weak_values))
+                log_error("unknown weak termination value '%s' in line %d\n", arg_weakTermination.c_str(), lineno);
+
+            if (!arg_termination.empty()) {
+                if (!is_number(arg_termination)) {
+                    log_error("termination must be string containing int, value '%s' in line %d\n",
+                              arg_termination.c_str(), lineno);
+                } else {
+                    int termination = std::stoi(arg_termination);
+                    if (termination < 30 || termination > 80)
+                        log_error("termination value must be in range from 30 to 80 in line %d\n", lineno);
+                }
+            }
+
+            const std::vector<std::string> termref_values = {"Floating", "VT"};
+            it = std::find(std::begin(termref_values), std::end(termref_values), arg_terminationReference);
+            if (it == std::end(termref_values))
+                log_error("unknown termination reference value '%s' in line %d\n", arg_terminationReference.c_str(),
+                          lineno);
+
+            if (!arg_turbo.empty() && arg_turbo != "True" && arg_turbo != "False")
+                log_error("turbo must be boolean, value '%s' in line %d\n", arg_turbo.c_str(), lineno);
+
+            if (!arg_inputSignalSlope.empty() && !is_number(arg_inputSignalSlope))
+                log_error("signal slope must be number, value '%s' in line %d\n", arg_inputSignalSlope.c_str(), lineno);
+            if (!arg_outputCapacity.empty() && !is_number(arg_outputCapacity))
+                log_error("output capacity must be number, value '%s' in line %d\n", arg_outputCapacity.c_str(),
+                          lineno);
+
+            const std::vector<std::string> registered_values = {"Auto", "I", "IC", "O", "OC", "IO", "IOC"};
+            it = std::find(std::begin(registered_values), std::end(registered_values), arg_registered);
+            if (it == std::end(registered_values))
+                log_error("unknown registered value '%s' in line %d\n", arg_registered.c_str(), lineno);
+
+            if (arg_standard == "LVDS" && arg_drive != "Undefined")
+                log_error("for port in line %d when standard is 'LVDS' drive must be 'Undefined'\n", lineno);
+            if (arg_standard == "LVCMOS" && !boost::ends_with(arg_drive, "mA"))
+                log_error("for port in line %d when standard is 'LVCMOS' drive current must be in mA\n", lineno);
+            if ((arg_standard == "SSTL" || arg_standard == "HSTL") && !boost::starts_with(arg_drive, "Cat"))
+                log_error("for port in line %d when standard is 'SSTL' or 'HSTL' drive current must be in 'CatI' or "
+                          "'CatII'\n",
+                          lineno);
+
+            if (arg_terminationReference == "Floating") {
+                if (!(arg_differential == "True" && arg_weakTermination == "None")) {
+                    log_error("for floating termination, differential myst be 'True' and weakTermination must be "
+                              "'None' in line %d\n",
+                              lineno);
+                }
+            }
+            std::vector<CellInfo *> dest = get_cells(arg_iobname);
+            for (auto c : dest) {
+                c->params[id_iobname] = arg_iobname;
+                c->params[id_location] = arg_location;
+                c->params[id_standard] = arg_standard;
+                c->params[id_drive] = arg_drive;
+                c->params[id_slewRate] = arg_slewRate;
+                c->params[id_inputDelayLine] = arg_inputDelayLine;
+                c->params[id_outputDelayLine] = arg_outputDelayLine;
+                c->params[id_inputDelayOn] = std::string((std::stoi(arg_inputDelayLine) != 0) ? "True" : "False");
+                c->params[id_outputDelayOn] = std::string((std::stoi(arg_outputDelayLine) != 0) ? "True" : "False");
+                c->params[id_differential] = arg_differential;
+                c->params[id_weakTermination] = arg_weakTermination;
+                if (!arg_termination.empty()) {
+                    c->params[id_termination] = arg_termination;
+                    c->params[id_terminationReference] = arg_terminationReference;
+                }
+                c->params[id_turbo] = arg_turbo;
+                c->params[id_inputSignalSlope] = arg_inputSignalSlope;
+                c->params[id_outputCapacity] = arg_outputCapacity;
+                c->params[id_registered] = arg_registered;
+            }
+            if (dest.size() == 0)
+                log_warning("Pad with name '%s' not found in netlist.\n", arg_iobname.c_str());
+
+            std::string bank_name = arg_location.substr(0, arg_location.find_first_of('_'));
+            banks_used.emplace(bank_name);
+        } break;
+        case IO_BANKS: {
+            if (arguments.size() == 1 && arguments[0][0] == '!') {
+                line_type = IO_GCKS;
+                continue;
+            }
+            if (arguments.size() != 3)
+                log_error("number of parameters in line %d must be 3\n", lineno);
+
+            if (!boost::starts_with(arguments.at(0), "IOB"))
+                log_error("wrong bank name '%s' in line %d\n", arguments.at(0).c_str(), lineno);
+
+            const char *voltages[] = {"1.2V", "1.5V", "1.8V", "2.5V", "3.3V"};
+            auto it = std::find(std::begin(voltages), std::end(voltages), arguments.at(1));
+            if (it == std::end(voltages))
+                log_error("unknown voltage level '%s' in line %d\n", arguments.at(1).c_str(), lineno);
+
+            const char *direct_io_voltages[] = {"1.8V", "2.5V", "3.3V"};
+            const char *complex_io_voltages[] = {"1.2V", "1.5V", "1.8V"};
+
+            int bank = std::stoi(arguments.at(0).substr(3));
+            switch (bank) {
+            // direct
+            case 0:
+            case 1:
+            case 6:
+            case 7: {
+                auto it = std::find(std::begin(direct_io_voltages), std::end(direct_io_voltages), arguments.at(1));
+                if (it == std::end(direct_io_voltages))
+                    log_error("unsupported voltage level '%s' for bank '%s'\n", arguments.at(1).c_str(),
+                              arguments.at(0).c_str());
+            } break;
+            // complex
+            default:
+                auto it = std::find(std::begin(complex_io_voltages), std::end(complex_io_voltages), arguments.at(1));
+                if (it == std::end(complex_io_voltages))
+                    log_error("unsupported voltage level '%s' for bank '%s'\n", arguments.at(1).c_str(),
+                              arguments.at(0).c_str());
+            }
+            bank_voltage[arguments.at(0)] = arguments.at(1);
+        } break;
+        case IO_GCKS: {
+            if (arguments.size() == 1 && arguments[0][0] == '!') {
+                line_type = IO_ERROR;
+                continue;
+            }
+            if (arguments.size() != 2)
+                log_error("number of parameters in line %d must be 2\n", lineno);
+        } break;
+        default:
+            log_error("switching to unknown block of data in line %d\n", lineno);
+        }
+    }
+    for (auto &bank_name : banks_used) {
+        if (bank_voltage.count(bank_name) == 0) {
+            log_error("IO for bank '%s' defined, but no bank configuration.\n", bank_name.c_str());
+        }
+    }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/extra_data.h b/himbaechel/uarch/ng-ultra/extra_data.h
new file mode 100644
index 0000000000..efd922feed
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/extra_data.h
@@ -0,0 +1,265 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef NGULTRA_EXTRA_DATA_H
+#define NGULTRA_EXTRA_DATA_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+NPNR_PACKED_STRUCT(struct NGUltraTileInstExtraDataPOD {
+    int32_t name;
+    uint8_t lobe;
+    uint8_t tile_type;
+    uint16_t dummy2;
+});
+
+NPNR_PACKED_STRUCT(struct NGUltraPipExtraDataPOD {
+    int32_t name;
+    uint16_t type;
+    uint8_t input;
+    uint8_t output;
+});
+
+NPNR_PACKED_STRUCT(struct NGUltraBelExtraDataPOD { int32_t flags; });
+
+struct GckConfig
+{
+    explicit GckConfig(BelId belid)
+    {
+        bel = belid;
+        si1 = IdString();
+        si2 = IdString();
+        used = false;
+    }
+    BelId bel;
+    IdString si1;
+    IdString si2;
+    bool used;
+};
+
+enum TILETypeZ
+{
+    BEL_LUT_Z = 0,
+    BEL_LUT_MAX_Z = 31,
+    BEL_CY_Z = 32,
+    BEL_XLUT_Z = BEL_CY_Z + 4,
+    BEL_RF_Z = BEL_XLUT_Z + 8,
+    BEL_XRF_Z = BEL_RF_Z + 2,
+    BEL_FIFO_Z = BEL_XRF_Z + 1,
+    BEL_XFIFO_Z = BEL_FIFO_Z + 2,
+    BEL_CDC_Z = BEL_XFIFO_Z + 1,
+    BEL_XCDC_Z = BEL_CDC_Z + 2
+};
+
+enum ClusterPlacement
+{
+    PLACE_CY_CHAIN = 1024,
+    PLACE_CY_FE1,
+    PLACE_CY_FE2,
+    PLACE_CY_FE3,
+    PLACE_CY_FE4,
+    PLACE_XLUT_FE1,
+    PLACE_XLUT_FE2,
+    PLACE_XLUT_FE3,
+    PLACE_XLUT_FE4,
+    PLACE_XRF_I1,
+    PLACE_XRF_I2,
+    PLACE_XRF_I3,
+    PLACE_XRF_I4,
+    PLACE_XRF_I5,
+    PLACE_XRF_I6,
+    PLACE_XRF_I7,
+    PLACE_XRF_I8,
+    PLACE_XRF_I9,
+    PLACE_XRF_I10,
+    PLACE_XRF_I11,
+    PLACE_XRF_I12,
+    PLACE_XRF_I13,
+    PLACE_XRF_I14,
+    PLACE_XRF_I15,
+    PLACE_XRF_I16,
+    PLACE_XRF_I17,
+    PLACE_XRF_I18,
+    PLACE_XRF_I19,
+    PLACE_XRF_I20,
+    PLACE_XRF_I21,
+    PLACE_XRF_I22,
+    PLACE_XRF_I23,
+    PLACE_XRF_I24,
+    PLACE_XRF_I25,
+    PLACE_XRF_I26,
+    PLACE_XRF_I27,
+    PLACE_XRF_I28,
+    PLACE_XRF_I29,
+    PLACE_XRF_I30,
+    PLACE_XRF_I31,
+    PLACE_XRF_I32,
+    PLACE_XRF_I33,
+    PLACE_XRF_I34,
+    PLACE_XRF_I35,
+    PLACE_XRF_I36,
+    PLACE_XRF_RA1,
+    PLACE_XRF_RA2,
+    PLACE_XRF_RA3,
+    PLACE_XRF_RA4,
+    PLACE_XRF_RA5,
+    PLACE_XRF_RA6,
+    PLACE_XRF_RA7,
+    PLACE_XRF_RA8,
+    PLACE_XRF_RA9,
+    PLACE_XRF_RA10,
+    PLACE_XRF_WA1,
+    PLACE_XRF_WA2,
+    PLACE_XRF_WA3,
+    PLACE_XRF_WA4,
+    PLACE_XRF_WA5,
+    PLACE_XRF_WA6,
+    PLACE_XRF_WE,
+    PLACE_XRF_WEA,
+    PLACE_DSP_CHAIN,
+    PLACE_CDC_AI1,
+    PLACE_CDC_AI2,
+    PLACE_CDC_AI3,
+    PLACE_CDC_AI4,
+    PLACE_CDC_AI5,
+    PLACE_CDC_AI6,
+    PLACE_CDC_BI1,
+    PLACE_CDC_BI2,
+    PLACE_CDC_BI3,
+    PLACE_CDC_BI4,
+    PLACE_CDC_BI5,
+    PLACE_CDC_BI6,
+    PLACE_CDC_ASRSTI,
+    PLACE_CDC_ADRSTI,
+    PLACE_CDC_BSRSTI,
+    PLACE_CDC_BDRSTI,
+    PLACE_CDC_CI1,
+    PLACE_CDC_CI2,
+    PLACE_CDC_CI3,
+    PLACE_CDC_CI4,
+    PLACE_CDC_CI5,
+    PLACE_CDC_CI6,
+    PLACE_CDC_DI1,
+    PLACE_CDC_DI2,
+    PLACE_CDC_DI3,
+    PLACE_CDC_DI4,
+    PLACE_CDC_DI5,
+    PLACE_CDC_DI6,
+    PLACE_CDC_CSRSTI,
+    PLACE_CDC_CDRSTI,
+    PLACE_CDC_DSRSTI,
+    PLACE_CDC_DDRSTI,
+    PLACE_FIFO_I1,
+    PLACE_FIFO_I2,
+    PLACE_FIFO_I3,
+    PLACE_FIFO_I4,
+    PLACE_FIFO_I5,
+    PLACE_FIFO_I6,
+    PLACE_FIFO_I7,
+    PLACE_FIFO_I8,
+    PLACE_FIFO_I9,
+    PLACE_FIFO_I10,
+    PLACE_FIFO_I11,
+    PLACE_FIFO_I12,
+    PLACE_FIFO_I13,
+    PLACE_FIFO_I14,
+    PLACE_FIFO_I15,
+    PLACE_FIFO_I16,
+    PLACE_FIFO_I17,
+    PLACE_FIFO_I18,
+    PLACE_FIFO_I19,
+    PLACE_FIFO_I20,
+    PLACE_FIFO_I21,
+    PLACE_FIFO_I22,
+    PLACE_FIFO_I23,
+    PLACE_FIFO_I24,
+    PLACE_FIFO_I25,
+    PLACE_FIFO_I26,
+    PLACE_FIFO_I27,
+    PLACE_FIFO_I28,
+    PLACE_FIFO_I29,
+    PLACE_FIFO_I30,
+    PLACE_FIFO_I31,
+    PLACE_FIFO_I32,
+    PLACE_FIFO_I33,
+    PLACE_FIFO_I34,
+    PLACE_FIFO_I35,
+    PLACE_FIFO_I36,
+    PLACE_FIFO_RAI1,
+    PLACE_FIFO_RAI2,
+    PLACE_FIFO_RAI3,
+    PLACE_FIFO_RAI4,
+    PLACE_FIFO_RAI5,
+    PLACE_FIFO_RAI6,
+    PLACE_FIFO_RAI7,
+    PLACE_FIFO_WAI1,
+    PLACE_FIFO_WAI2,
+    PLACE_FIFO_WAI3,
+    PLACE_FIFO_WAI4,
+    PLACE_FIFO_WAI5,
+    PLACE_FIFO_WAI6,
+    PLACE_FIFO_WAI7,
+    PLACE_FIFO_WE,
+    PLACE_FIFO_WEA,
+    PLACE_FIFO_WRSTI1,
+    PLACE_FIFO_RRSTI1,
+    PLACE_FIFO_WRSTI2,
+    PLACE_FIFO_RRSTI2,
+    PLACE_FIFO_WRSTI3,
+    PLACE_FIFO_RRSTI3,
+    PLACE_FIFO_WRSTI4,
+    PLACE_FIFO_RRSTI4,
+    PLACE_FIFO_WEQ1,
+    PLACE_FIFO_REQ1,
+    PLACE_FIFO_WEQ2,
+    PLACE_FIFO_REQ2,
+    PLACE_LUT_CHAIN,
+    PLACE_DFF_CHAIN,
+};
+
+enum PipExtra
+{
+    PIP_EXTRA_CROSSBAR = 1,
+    PIP_EXTRA_MUX = 2,
+    PIP_EXTRA_BYPASS = 3,
+    PIP_EXTRA_LUT_PERMUTATION = 4,
+    PIP_EXTRA_INTERCONNECT = 5,
+    PIP_EXTRA_VIRTUAL = 6,
+};
+
+enum BelExtra
+{
+    BEL_EXTRA_FE_CSC = 1,
+    BEL_EXTRA_FE_SCC = 2,
+};
+
+enum TileTypeExtra
+{
+    TILE_EXTRA_FABRIC = 0,
+    TILE_EXTRA_TUBE = 1,
+    TILE_EXTRA_SOC = 2,
+    TILE_EXTRA_RING = 3,
+    TILE_EXTRA_FENCE = 4
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/himbaechel/uarch/ng-ultra/gen/arch_gen.py b/himbaechel/uarch/ng-ultra/gen/arch_gen.py
new file mode 100644
index 0000000000..dc5e5aab61
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/gen/arch_gen.py
@@ -0,0 +1,726 @@
+#  nextpnr -- Next Generation Place and Route
+#
+#  Copyright (C) 2024  The Project Beyond Authors.
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+
+import json
+from os import path
+import sys
+import argparse
+import gzip
+
+# Configuration flags
+USE_LUT_PERMUTATION = True
+
+sys.path.append(path.join(path.dirname(__file__), "../../.."))
+from himbaechel_dbgen.chip import *
+
+@dataclass
+class TileExtraData(BBAStruct):
+    name: IdString
+    lobe: int = 0
+    tile_type: int = 0
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u8(self.lobe)
+        bba.u8(self.tile_type)
+        bba.u16(0) # dummy
+
+@dataclass
+class PipExtraData(BBAStruct):
+    name: IdString = field(default_factory=IdString)
+    data_type: int = 0
+    input: int = 0
+    output: int = 0
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u16(self.data_type)
+        bba.u8(self.input)
+        bba.u8(self.output)
+
+@dataclass
+class BelExtraData(BBAStruct):
+    flags: int = 0
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        pass
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.flags)
+ 
+PLL_Z = 0
+WFG_C_Z = 1
+WFG_R_Z = 11
+
+IOM_Z = 136
+
+RAM_Z = 0
+DSP1_Z = 1
+DSP2_Z = 2
+
+SOCIF_Z = 0
+SERVICE_Z = 1
+
+LUT_Z = 0
+CY_Z = 32
+XLUT_Z = CY_Z + 4
+RF_Z =  XLUT_Z + 8
+XRF_Z = RF_Z + 2
+FIFO_Z = XRF_Z + 1
+XFIFO_Z = FIFO_Z + 2
+CDC_Z = XFIFO_Z + 1
+XCDC_Z = CDC_Z + 2
+
+PIP_EXTRA_CROSSBAR = 1
+PIP_EXTRA_MUX = 2
+PIP_EXTRA_BYPASS = 3
+PIP_EXTRA_LUT_PERMUTATION = 4
+PIP_EXTRA_INTERCONNECT = 5
+PIP_EXTRA_VIRTUAL = 6
+
+BEL_EXTRA_FE_CSC = 1
+BEL_EXTRA_FE_SCC = 2
+
+TILE_EXTRA_FABRIC = 0
+TILE_EXTRA_TUBE = 1
+TILE_EXTRA_SOC = 2
+TILE_EXTRA_RING = 3
+TILE_EXTRA_FENCE = 4
+
+def bel_z(tile_type, bel_name, bel_type):
+    if tile_type.startswith("CKG"):
+        if (bel_type=="PLL"):
+            return PLL_Z
+        else:
+            if bel_name.startswith("WFG.WFG_C"):
+                return int(bel_name.replace("WFG.WFG_C","")) + WFG_C_Z -1
+            else:
+                return int(bel_name.replace("WFG.WFG_R","")) + WFG_R_Z -1
+    elif tile_type.startswith("HSSL"):
+        if bel_type=="PMA":
+            return 0
+        elif bel_type=="CRX":
+            return int(bel_name.split(".")[0][7:]) * 2 - 1
+        else:
+            return int(bel_name.split(".")[0][7:]) * 2
+    elif tile_type.startswith("IOB") and tile_type in ["IOB0","IOB1","IOB6","IOB7"]: #direct
+        sp = bel_name.split(".")
+        if bel_type=="IOP":
+            return int(sp[0][1:]) * 4
+        else:
+            return (int(sp[0][3:])-1) * 4 + (1 if sp[1][0]=='I' else 2 if sp[1][0]=='O' else 3)
+    elif tile_type.startswith("IOB"): # complex
+        sp = bel_name.split(".")
+        if bel_type=="IOTP":
+            return (int(sp[0][1:3]) *2 + (1 if sp[0][3]=='N' else 0)) * 4
+        elif bel_type=="IOM":
+            return IOM_Z
+        else:
+            return (int(sp[0][3:])-1) * 4 + (1 if sp[1][0]=='I' else 2 if sp[1][0]=='O' else 3)
+    elif tile_type == "CGB":
+        if bel_type=="RAM":
+            return RAM_Z
+        elif bel_name=="S2.DSP1":
+            return DSP1_Z
+        else:
+            return DSP2_Z
+    elif tile_type == "SOCBank":
+        if bel_type=="SOCIF":
+            return SOCIF_Z
+        else:
+            return SERVICE_Z
+    elif tile_type == "TILE":
+        sp = bel_name.split(".")
+        if bel_type=="BEYOND_FE":
+            return (int(sp[1][2:])-1) % 32
+        elif bel_type=="CY":
+            pos = int(sp[1][2:])-1
+            # in S1, S5 and S9 they are ordered other way arround
+            return ((pos % 4) if pos < 12 else 3 - (pos % 4)) + CY_Z
+        elif bel_type=="XLUT":
+            return (int(sp[1][4:])-1) % 8 + XLUT_Z
+        elif bel_type=="RF":
+            return (int(sp[1][2:])-1) + RF_Z
+        elif bel_type=="XRF":
+            return (int(sp[1][3:])-1) + XRF_Z
+        elif bel_type=="FIFO":
+            return (int(sp[1][4:])-1) + FIFO_Z
+        elif bel_type=="XFIFO":
+            return (int(sp[1][5:])-1) + XFIFO_Z
+        elif bel_type=="CDC":
+            return (int(sp[1][3:])-1) + CDC_Z
+        elif bel_type=="XCDC":
+            return (int(sp[1][4:])-1) + XCDC_Z
+        else:
+            raise Exception(f"Unknown bel type {bel_type}")
+    elif tile_type == "TUBE":
+        sp = bel_name.split(".")
+        return (int(sp[0][1:])-1)*20 + (int(sp[1][1:])-1)
+    else:
+        raise Exception(f"Unknown type {tile_type}")
+
+if USE_LUT_PERMUTATION:
+    # Note PI1-PI4 are not real inputs but will appear
+    # before actual BEL input to enable LUT permutation
+    lut_to_beyond_fe = {
+        "I1" : "PI1",
+        "I2" : "PI2",
+        "I3" : "PI3",
+        "I4" : "PI4",
+        "O"  : "LO",
+        "J"  : "LJ",
+        "K"  : "LK",
+        "D"  : "LD",
+        "X"  : "LX",
+    }
+else:
+    lut_to_beyond_fe = {
+        "I1" : "I1",
+        "I2" : "I2",
+        "I3" : "I3",
+        "I4" : "I4",
+        "O"  : "LO",
+        "J"  : "LJ",
+        "K"  : "LK",
+        "D"  : "LD",
+        "X"  : "LX",
+    }
+
+dff_to_beyond_fe = {
+    "I"  : "DI",
+    "O"  : "DO",
+    "L"  : "L",
+    "CK" : "CK",
+    "R"  : "R",
+    "J"  : "DJ",
+    "P"  : "DP",
+    "C"  : "DC",
+    "S"  : "DS",
+    "K"  : "DK",
+}
+
+def is_complex(tile_type):
+    return tile_type not in ["IOB0","IOB1","IOB6","IOB7"]
+
+def map_to_beyond(tile_type,bel_name,bel_type=None):
+    if not tile_type in ["TILE"]:
+        return (bel_name,bel_type)
+    s = bel_name.split(".")
+    if tile_type in ["TILE"]:
+        # BEYOND_FE
+        if not (s[1].startswith("LUT") or s[1].startswith("DFF")):
+            return (bel_name,bel_type)
+        if len(s)==3:
+            # BEL and PORT
+            if s[1].startswith("LUT"):
+                pin = lut_to_beyond_fe[s[2]]
+            else:
+                pin = dff_to_beyond_fe[s[2]]
+            if pin is None:
+                return (None,bel_type)
+            return (s[0]+".FE"+s[1][3:]+"."+pin, bel_type if type(bel_type) is int else "BEYOND_FE")
+        else:
+            # just BEL
+            return (s[0]+".FE"+s[1][3:], "BEYOND_FE")
+
+split_map = ["TILE", "CGB"]
+
+def split_tilegrid(tilegrid):
+    new_tilegrid = dict()
+    for k,v in tilegrid.items():
+        if v["type"] not in split_map:
+            new_tilegrid[k] = dict()
+            data = dict(v)
+            data["orig"] = data["type"]
+            data["x"]=data["x"]*4
+            data["y"]=data["y"]*4
+            new_tilegrid[k][0] = data
+        else:
+            new_tilegrid[k] = dict()
+            for i in range(4*4):
+                data = dict(v)
+                data["orig"] = data["type"]
+                data["type"] = data["type"]+"_"+str(i)
+                data["x"]=data["x"]*4 + i // 4
+                data["y"]=data["y"]*4 + i % 4
+                new_tilegrid[k][i] = data
+    return new_tilegrid
+
+def determine_subtile(tile,bel):
+    if tile=="TILE":
+        if bel.startswith("SYSTEM"):
+            s = 3
+        elif bel.startswith("RE") or bel.startswith("RS") or bel.startswith("RI"):
+            s = int(bel.split(".")[0][2:])-1
+        elif bel.startswith("S"):
+            s = int(bel.split(".")[0][1:])+3
+        else:
+            return 0
+        return s
+    elif tile=="CGB":
+        if bel.startswith("SYSTEM"):
+            s = 6
+        elif bel.startswith("RE"):
+            s = 8
+        elif bel.startswith("RS"):
+            s = int(bel.split(".")[0][2:])
+        elif bel.startswith("RI"):
+            s = 5
+        elif bel.startswith("S1"):
+            s = 0
+        elif bel.startswith("S2.DSP1"):
+            s = 7
+        else:
+            return 15
+        return s
+    else:
+        return 0
+
+def split_per_bels(bels):
+    new_bels = dict()
+    for k,v in bels.items():
+        if k not in split_map:
+            new_bels[k] = dict()
+            data = dict(v)
+            new_bels[k][0] = data
+        else:
+            new_bels[k] = dict()
+            for i in range(4*4):
+                new_bels[k][i] = dict()
+            for item,bel in v.items():
+                (item, bel) = map_to_beyond(k,item,bel)
+                if item is not None:
+                    num = determine_subtile(k,item)
+                    new_bels[k][num][item] = bel
+    return new_bels
+
+def lookup_port_type(t):
+    if t == "Input": return PinType.INPUT
+    elif t == "Output": return PinType.OUTPUT
+    elif t == "Bidir": return PinType.INOUT
+    else: assert False
+
+def create_pips(tt, tile_type, muxes, num, args):
+    file_path = path.join(args.db, args.device, tile_type + ".txt")
+    if not path.isfile(file_path):
+        return
+    with open(file_path) as f:
+        for item in f:
+            line = item.strip().split(" ")
+            name1,_ = map_to_beyond(tile_type,line[0])
+            name2,_ = map_to_beyond(tile_type,line[1])
+            if name1 is None or name2 is None:
+                continue
+            num1 = determine_subtile(tile_type,name1)
+            num2 = determine_subtile(tile_type,name2)
+
+            if name2 in muxes:
+                name2 = name2 + "." + line[2]
+            if num1==num and not tt.has_wire(name1):
+                tt.create_wire(name=name1, type=tile_type + "_WIRE")
+            if num2==num and not tt.has_wire(name2):
+                tt.create_wire(name=name2, type=tile_type + "_WIRE")
+            timing_class = line[3]
+            # Only create PIP if both ends are in same subtile
+            if num1==num and num2==num:
+                tt.create_pip(name1,name2,timing_class)
+
+def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes, args):
+    for tile_type,items in bels.items():
+        for num in items.keys():
+            if len(items)==1:
+                sub_type = tile_type
+            else:
+                sub_type = f"{tile_type}_{num}"
+            tt = ch.create_tile_type(sub_type)
+
+            def lookup_site_wire(canon_name):
+                if not tt.has_wire(canon_name):
+                    tt.create_wire(name=canon_name, type="BEL_PIN_WIRE")
+                return canon_name
+
+            # Create BELs inside tile
+            for name,bel in bels[tile_type][num].items():
+                nb = tt.create_bel(name, bel, z=bel_z(tile_type,name,bel))
+                # Create wires for each BEL port
+                for index in bel_pins[bel].keys():
+                    pin = bel_pins[bel][index]
+                    tt.add_bel_pin(nb, pin["name"], lookup_site_wire(f"{name}."+pin["name"]), lookup_port_type(pin["direction"]))
+                if (tile_type.startswith("TILE") and bel=="BEYOND_FE"):
+                    flag = 0
+                    fe_nxd = int(name[name.index(".")+3:])
+                    if (((fe_nxd-1) & 127) < 64):
+                        if ((fe_nxd-1)&31) < 16:
+                            if (fe_nxd & 1)==1:
+                                flag |= BEL_EXTRA_FE_SCC
+                        else:
+                            if (fe_nxd & 1)==0:
+                                flag |= BEL_EXTRA_FE_SCC
+
+                    if fe_nxd in (65, 80, 81, 96, 225,240,241,256, 321,336,337,352):
+                        flag |= BEL_EXTRA_FE_CSC
+                    nb.extra_data = BelExtraData(flag)
+
+                    # LUT drawers, LO already connected to LJ
+                    vi = tt.create_pip(f"{name}.LJ",f"{name}.LK","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    vi = tt.create_pip(f"{name}.LJ",f"{name}.LD","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    vi = tt.create_pip(f"{name}.LJ",f"{name}.LX","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    # DFF drawers, DO already connected to DJ
+                    vi = tt.create_pip(f"{name}.DJ",f"{name}.DP","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    vi = tt.create_pip(f"{name}.DJ",f"{name}.DC","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    vi = tt.create_pip(f"{name}.DJ",f"{name}.DS","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    vi = tt.create_pip(f"{name}.DJ",f"{name}.DK","Virtual")
+                    vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                    # DFF bypass
+                    by = tt.create_pip(f"{name}.DI",f"{name}.DO","BYPASS")
+                    by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
+                    # LUT bypass
+                    by = tt.create_pip(f"{name}.I1",f"{name}.LO","BYPASS")
+                    by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
+                elif (tile_type.startswith("TILE") and bel=="XLUT"):
+                    for out in ["G1","G2","G3","G4"]:
+                        vi = tt.create_pip(f"{name}.J",f"{name}.{out}","Virtual")
+                        vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
+                elif (tile_type.startswith("TILE") and bel=="CY"):
+                    # matrix of each input to each output combination
+                    # crossbar but use mux placeholder for convenience
+                    for inp in ["I1","I2","I3","I4"]:
+                        for out in ["O1","O2","O3","O4"]:
+                            pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP")
+                            pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1)
+
+                elif (tile_type.startswith("CKG") and bel=="WFG"):
+                    by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS")
+                    by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
+                elif (tile_type.startswith("TUBE") and bel=="GCK"):
+                    # 20 clock signals comming to 20 GCK, SI1 is bypass
+                    by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")
+                    by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
+                    # there are CMD signals that can be bypassed as well
+                    by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS")
+                    by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
+                
+
+            # Add LUT permutation
+            if USE_LUT_PERMUTATION and tile_type=="TILE":
+                for name,bel in bels[tile_type][num].items():
+                    if bel=="BEYOND_FE":
+                        for inp in ["PI1","PI2","PI3","PI4"]:
+                            tt.create_wire(name=f"{name}."+inp, type="LUT_PERMUTATION_WIRE")
+                            for out in ["I1","I2","I3","I4"]:
+                                pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"LUT_PERMUTATION")
+                                pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_LUT_PERMUTATION,int(inp[2:])-1,int(out[1:])-1)
+
+            # Create crossbars as multiple PIPs
+            for name,xb in crossbars[tile_type][num].items():
+                inputs = list()
+                outputs = list()
+                for index in bel_pins[xb].keys():
+                    pin = bel_pins[xb][index]
+                    tt.create_wire(name=f"{name}."+pin["name"], type="CROSSBAR_"+xb+"_INPUT_WIRE" if pin["direction"] == "Input" else "CROSSBAR_"+xb+"_OUTPUT_WIRE")
+                for index in bel_pins[xb].keys():
+                    pin = bel_pins[xb][index]
+                    if pin["direction"] == "Input":
+                        inputs.append(pin["name"])
+                    else:
+                        outputs.append(pin["name"])
+                for inp in inputs:
+                    for out in outputs:
+                        pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"CROSSBAR_"+xb)
+                        pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_CROSSBAR,int(inp[1:])-1,int(out[1:])-1)
+
+            # Interconnects are just PIPs with one I and one O
+            for name,xb in interconnects[tile_type][num].items():
+                for index in bel_pins[xb].keys():
+                    pin = bel_pins[xb][index]
+                    tt.create_wire(name=f"{name}."+pin["name"], type="INTERCONNECT_INPUT" if pin["direction"] == "Input" else "INTERCONNECT_OUTPUT")
+                inp = f"{name}."+bel_pins[xb]["I"]["name"]
+                out = f"{name}."+bel_pins[xb]["O"]["name"]
+                pd = tt.create_pip(inp,out,"INTERCONNECT")
+                pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_INTERCONNECT,0,0)
+
+            # Create MUXes as many to one connections
+            if tile_type in muxes:
+                for (name, n) in muxes[tile_type][num].items():
+                    for i in range(0,n+1):
+                        new_name = name + "." + str(i)
+                        if not tt.has_wire(new_name):
+                            tt.create_wire(name=new_name, type="MUX_WIRE")
+                        pd = tt.create_pip(new_name,name,"MUX_PIP")
+                        pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_MUX,i,0)
+
+            m = muxes[tile_type] if tile_type in muxes else dict()                
+            mux = muxes[tile_type][num] if num in m else dict()
+            create_pips(tt, tile_type, mux, num, args)
+
+def create_null(ch: Chip):
+    tt = ch.create_tile_type("NULL")
+
+def set_timings(ch, pip_timings, bel_timings):
+    speed = "DEFAULT"
+    tmg = ch.set_speed_grades([speed])
+    for k,v in pip_timings.items():
+        tmg.set_pip_class(grade=speed, name=k, delay=TimingValue(v[0]))
+        tmg.set_node_class(grade=speed, name=k, delay=TimingValue(v[0]))
+    tmg.set_pip_class(grade=speed, name="INTERCONNECT", delay=TimingValue(0))
+    tmg.set_pip_class(grade=speed, name="MUX_PIP", delay=TimingValue(0))
+    tmg.set_pip_class(grade=speed, name="MATRIX_PIP", delay=TimingValue(0))
+    tmg.set_pip_class(grade=speed, name="LUT_PERMUTATION", delay=TimingValue(0))
+    tmg.set_pip_class(grade=speed, name="BYPASS", delay=TimingValue(142))
+    for k,g in bel_timings.items():
+        primitive = ch.timing.add_cell_variant(speed, k)
+        for t,v in g.items():
+            if t=="IOPath":
+                for from_port,values in v.items():
+                    for to_port,data in values.items():
+                        primitive.add_comb_arc(from_port, to_port, TimingValue(data[0], data[1]))
+            elif t=="SetupHold":
+                for from_port,values in v.items():
+                    for to_port,data in values.items():
+                        primitive.add_setup_hold(from_port, to_port, ClockEdge.RISING, TimingValue(data[0]), TimingValue(data[1]))
+            elif t=="ClockOut":
+                for from_port,values in v.items():
+                    for to_port,data in values.items():
+                        primitive.add_clock_out(from_port, to_port, ClockEdge.RISING, TimingValue(data[0],data[1]))
+
+def get_pos(tilegrid,name,bel):
+    tile = tilegrid[name][0]["orig"]
+    num = determine_subtile(tile,bel)
+    item = tilegrid[name][num]
+    x = item["x"]
+    y = item["y"]
+    return (tile,num,x,y)
+
+
+global_connections = dict()
+def load_globals(args):
+    print("Load global connections...")
+    with gzip.open(path.join(args.db, args.device, "GLOBAL.txt.gz"),"rt") as f:
+        for item in f:
+            line = item.strip().split(" ")
+            tile_name = line[0].split(":")[0]
+            if tile_name not in global_connections:
+                global_connections[tile_name] = dict()
+            if line[0] not in global_connections[tile_name]:
+                global_connections[tile_name][line[0]] = list()
+            global_connections[tile_name][line[0]].append(line)
+
+def create_nodes(ch, tile_name, tilegrid, muxes, pip_timings):
+    if tile_name not in global_connections:
+        return
+    connections = global_connections[tile_name]
+    for key,val in connections.items():
+        name1 = key.split(":")
+        t1,_,x1,y1 = get_pos(tilegrid,name1[0],name1[1])
+        name1[1],_ = map_to_beyond(t1,name1[1])
+        if name1[1] is None:
+            continue
+        node = [NodeWire(x1, y1, name1[1])]
+        timing = None
+        timing_val = -1
+        for v in val:
+            name2 = v[1].split(":")
+            name2[1],_ = map_to_beyond(tilegrid[name2[0]][0]["orig"],name2[1])
+            t2,num,x2,y2 = get_pos(tilegrid,name2[0],name2[1])
+            if name2[1] is None:
+                continue
+            if pip_timings[v[3]][0] > timing_val:
+                timing_val = pip_timings[v[3]][0]
+                timing = v[3]
+            if t2 in muxes and num in muxes[t2] and name2[1] in muxes[t2][num]:
+                node.append(NodeWire(x2, y2, name2[1]+"."+v[2]))
+            else:
+                node.append(NodeWire(x2, y2, name2[1]))
+
+        ch.add_node(node,timing_class=timing)
+
+
+subtile_connections = dict()
+def create_nodes_subtiles(ch, tilegrid, name, tile_type, muxes, pip_timings, args):
+    if tile_type not in subtile_connections:
+        subtile_connections[tile_type] = dict()
+
+        file_path = path.join(args.db, args.device, tile_type + ".txt")
+        if not path.isfile(file_path):
+            return
+        with open(file_path) as f:
+            for item in f:
+                line = item.strip().split(" ")
+                name1 = line[0]
+                name2 = line[1]
+                name1,_ = map_to_beyond(tile_type,line[0])
+                name2,_ = map_to_beyond(tile_type,line[1])
+                if name1 is None or name2 is None:
+                    continue
+                num1 = determine_subtile(tile_type,name1)
+                num2 = determine_subtile(tile_type,name2)
+                # Only create WIRE if ends are NOT in same subtile
+                if num1!=num2:
+                    if name1 not in subtile_connections[tile_type] :
+                        subtile_connections[tile_type][name1] = list()
+                    subtile_connections[tile_type][name1].append([name1, name2, line[2], line[3]])
+
+    for name1,val in subtile_connections[tile_type].items():
+        _,_,x1,y1 = get_pos(tilegrid,name,name1)
+        node = [NodeWire(x1, y1, name1)]
+        timing_val = -1
+        timing = None
+        for v in val:
+            name2 = v[1]
+            t2,num,x2,y2 = get_pos(tilegrid,name,name2)
+            if pip_timings[v[3]][0] > timing_val:
+                timing_val = pip_timings[v[3]][0]
+                timing = v[3]
+            if t2 in muxes and num in muxes[t2] and name2 in muxes[t2][num]:
+                node.append(NodeWire(x2, y2, name2+"."+v[2]))
+            else:
+                node.append(NodeWire(x2, y2, name2))
+
+        ch.add_node(node,timing_class=timing)
+
+def import_package(ch, package, bels, tilegrid):
+    pkg = ch.create_package(package)
+    for name, data in tilegrid.items():
+        for key, item in data.items():
+            ty = item["orig"]
+            x = item["x"]
+            y = item["y"]
+            if ty.startswith("IOB"):
+                for bel,ty in bels[ty][key].items():
+                    # Support for native primitives
+                    if ty =="IOTP":
+                        pin = name+"_"+bel[:4]
+                    elif ty =="IOP":
+                        pin = name+"_"+bel[:3]
+                    else:
+                        continue
+                    pkg.create_pad(pin, f"X{x}Y{y}", bel, "", int(name[3:]))
+
+def main():
+    xlbase = path.join(path.dirname(path.realpath(__file__)), "..")
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--db", help="Project Beyond device database path (e.g. ../prjbeyond/database)", type=str, required=True)
+    parser.add_argument("--device", help="name of device to export", type=str, required=True)
+    parser.add_argument("--constids", help="name of nextpnr constids file to read", type=str, default=path.join(xlbase, "constids.inc"))
+    parser.add_argument("--bba", help="bba file to write", type=str, required=True)
+    args = parser.parse_args()
+
+    with open(path.join(args.db, "devices.json")) as f:
+        devices = json.load(f)
+
+    width = (devices["families"][args.device]["max_col"] + 1) * 4
+    height = (devices["families"][args.device]["max_row"] + 1) * 4
+    packages = devices["families"][args.device]["packages"]
+
+    ch = Chip("ng-ultra",args.device, width, height)
+    ch.strs.read_constids(path.join(path.dirname(__file__), "..", "constids.inc"))
+
+    # Data that is depending of location
+    with open(path.join(args.db, args.device, "tilegrid.json")) as f:
+        tilegrid = split_tilegrid(json.load(f))
+
+    with open(path.join(args.db, args.device, "bels.json")) as f:
+        bels = split_per_bels(json.load(f))
+
+    with open(path.join(args.db, args.device, "crossbars.json")) as f:
+        crossbars = split_per_bels(json.load(f))
+
+    with open(path.join(args.db, args.device, "interconnects.json")) as f:
+        interconnects = split_per_bels(json.load(f))
+
+    with open(path.join(args.db, args.device, "muxes.json")) as f:
+        muxes = split_per_bels(json.load(f))
+
+    # Data that is not related to position
+    with open(path.join(args.db, args.device, "bel_pins.json")) as f:
+        bel_pins = json.load(f)
+        bel_pins["IOP"]["IO"] = { "direction": "Bidir", "name": "IO" }
+        bel_pins["IOTP"]["IO"] = { "direction": "Bidir", "name": "IO" }
+
+    with open(path.join(args.db, args.device, "pip_timings.json")) as f:
+        pip_timings = json.load(f)
+
+    with open(path.join(args.db, args.device, "bel_timings.json")) as f:
+        bel_timings = json.load(f)
+
+    create_tile_types(ch, bels, bel_pins, crossbars, interconnects, muxes, args)
+    create_null(ch)
+    set_timings(ch, pip_timings, bel_timings)
+
+    for x in range(width):
+        for y in range(height):
+            ch.set_tile_type(x,y,"NULL")
+
+    load_globals(args)
+    for name, data in tilegrid.items():
+        for item in data.values():
+            ti = ch.set_tile_type(item["x"],item["y"],item["type"])
+            lobe = 0
+            if item["orig"] in ["TILE","CGB"]:
+                tmp = name.replace("TILE[","").replace("CGB[","").replace("]","")
+                x,y = tmp.split("x")
+                lobe = ((int(y)-1) // 12)*2 + (1 if int(x)>46 else 0) + 1
+            elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL"):
+                match item["orig"]:
+                    case "IOB0" | "IOB1":
+                        lobe = 5
+                    case "IOB6" | "IOB7":
+                        lobe = 6
+                    case "IOB8" | "IOB9" | "IOB10":
+                        lobe = 2
+                    case "IOB11" | "IOB12" | "IOB13":
+                        lobe = 1
+                    case "IOB2" | "IOB3" | "HSSL0" | "HSSL1" | "HSSL2" | "HSSL3":
+                        lobe = 7
+                    case "IOB4" | "IOB5" | "HSSL4" | "HSSL5" | "HSSL6" | "HSSL7":
+                        lobe = 8
+            tile_type = 0
+            if item["orig"] in ["TILE","CGB","MESH"]:
+                tile_type = TILE_EXTRA_FABRIC
+            elif item["orig"] in ["TUBE"]:
+                tile_type = TILE_EXTRA_TUBE
+            elif item["orig"] in ["SOCBank"]:
+                tile_type = TILE_EXTRA_SOC
+            elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL") or item["orig"].startswith("CKG"):
+                tile_type = TILE_EXTRA_RING
+            elif item["orig"].startswith("FENCE"):
+                tile_type = TILE_EXTRA_FENCE
+
+            ti.extra_data = TileExtraData(ch.strs.id(name),lobe, tile_type)
+
+    for name, data in tilegrid.items():
+        print(f"Generate nodes for {name}...")
+        create_nodes_subtiles(ch, tilegrid, name, data[0]["orig"], muxes, pip_timings, args)
+        create_nodes(ch, name, tilegrid, muxes, pip_timings)
+
+    for package in packages:
+        import_package(ch, package, bels, tilegrid)
+
+    ch.write_bba(args.bba)
+
+if __name__ == '__main__':
+    main()
diff --git a/himbaechel/uarch/ng-ultra/location_map.cc b/himbaechel/uarch/ng-ultra/location_map.cc
new file mode 100644
index 0000000000..c04c88888c
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/location_map.cc
@@ -0,0 +1,569 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "location_map.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+/* clang-format off */
+const Loc ng_ultra_place_cy_map[24] = {
+        { 0,  1,  0}, // S1 0 -> S2 0  CY24->CY1
+        { 0,  0, -1}, // S1 1 -> S1 0  CY23->CY24
+        { 0,  0, -1}, // S1 2 -> S1 1  CY22->CY23
+        { 0,  0, -1}, // S1 3 -> S1 2  CY21->CY22
+
+        {-1,  0, +3}, // S5 0 -> S1 1  CY20->CY21
+        { 0,  0, -1}, // S5 1 -> S5 0  CY19->CY20
+        { 0,  0, -1}, // S5 2 -> S5 1  CY18->CY19
+        { 0,  0, -1}, // S5 3 -> S5 2  CY17->CY18
+
+        {-1,  0, +3}, // S9 0 -> S5 1  CY16->CY17
+        { 0,  0, -1}, // S9 1 -> S9 0  CY15->CY16
+        { 0,  0, -1}, // S9 2 -> S9 1  CY14->CY15
+        { 0,  0, -1}, // S9 3 -> S9 2  CY13->CY14
+
+        { 0,  0, +1}, // S2 0 -> S2 1  CY1->CY2
+        { 0,  0, +1}, // S2 1 -> S2 2  CY2->CY3
+        { 0,  0, +1}, // S2 2 -> S2 3  CY3->CY4
+        { 1,  0, -3}, // S2 3 -> S6 0  CY4->CY5
+
+        { 0,  0, +1}, // S6 0 -> S6 1  CY5->CY6
+        { 0,  0, +1}, // S6 1 -> S6 2  CY6->CY7
+        { 0,  0, +1}, // S6 2 -> S6 3  CY7->CY8
+        { 1,  0, -3}, // S6 3 -> S10 0 CY8->CY9
+
+        { 0,  0, +1}, // S10 0 -> S10 1 CY9->CY10
+        { 0,  0, +1}, // S10 1 -> S10 2 CY10->CY11
+        { 0,  0, +1}, // S10 2 -> S10 3 CY11->CY12
+        { 0, -1,  0}, // S10 3 -> S9  3 CY12->CY13
+};
+
+const Loc ng_ultra_place_xrf[] = {
+        {-1, 0, 1},  // I/O1
+        {-1, 0, 2},  // I/O2
+        {-1, 0, 5},  // I/O3
+        {-1, 0, 6},  // I/O4
+        {-1, 0, 7},  // I/O5
+        {-1, 0, 9},  // I/O6
+        {-1, 0, 10}, // I/O7
+        {-1, 0, 13}, // I/O8
+        {-1, 0, 14}, // I/O9
+        {-1, 0, 15}, // I/O10
+        {-1, 0, 16}, // I/O11
+        {-1, 0, 17}, // I/O12
+        {-1, 0, 18}, // I/O13
+        {-1, 0, 21}, // I/O14
+        {-1, 0, 24}, // I/O15
+        {-1, 0, 25}, // I/O16
+        {-1, 0, 26}, // I/O17
+        {-1, 0, 29}, // I/O18
+
+        {+1, 0, 1},  // I/O19
+        {+1, 0, 2},  // I/O20
+        {+1, 0, 5},  // I/O21
+        {+1, 0, 6},  // I/O22
+        {+1, 0, 7},  // I/O23
+        {+1, 0, 9},  // I/O24
+        {+1, 0, 10}, // I/O25
+        {+1, 0, 13}, // I/O26
+        {+1, 0, 14}, // I/O27
+        {+1, 0, 15}, // I/O28
+        {+1, 0, 16}, // I/O29
+        {+1, 0, 17}, // I/O30
+        {+1, 0, 18}, // I/O31
+        {+1, 0, 21}, // I/O32
+        {+1, 0, 24}, // I/O33
+        {+1, 0, 25}, // I/O34
+        {+1, 0, 26}, // I/O35
+        {+1, 0, 29}, // I/O36
+
+        {-1, 0, 4},  // RA1
+        {-1, 0, 12}, // RA2
+        {-1, 0, 20}, // RA3
+        {-1, 0, 27}, // RA4
+        {-1, 0, 31}, // RA5
+
+        {+1, 0, 4},  // RA6
+        {+1, 0, 12}, // RA7
+        {+1, 0, 20}, // RA8
+        {+1, 0, 27}, // RA9
+        {+1, 0, 31}, // RA10
+
+        {-1, 0, 3},  // WA1
+        {-1, 0, 11}, // WA2
+        {-1, 0, 19}, // WA3
+        {-1, 0, 23}, // WA4
+        {-1, 0, 28}, // WA5
+
+        {+1, 0, 3}, // WA6
+
+        {-1, 0, 0}, // WE
+        {-1, 0, 8}, // WEA
+
+};
+
+const Loc ng_ultra_place_cdc1[] = {
+        {+1, 0, 1},  // AI1
+        {+1, 0, 2},  // AI2
+        {+1, 0, 9},  // AI3
+        {+1, 0, 17}, // AI4
+        {+1, 0, 18}, // AI5
+        {+1, 0, 25}, // AI6
+
+        {+1, 0, 3},  // BI1
+        {+1, 0, 10}, // BI2
+        {+1, 0, 11}, // BI3
+        {+1, 0, 19}, // BI4
+        {+1, 0, 26}, // BI5
+        {+1, 0, 27}, // BI6
+
+        { 0, 0, 22}, // ASRSTI
+        { 0, 0, 30}, // ADRSTI
+        {+1, 0, 24}, // BSRSTI
+        {+1, 0, 8},  // BDRSTI
+};
+
+const Loc ng_ultra_place_cdc2[] = {
+        {-1, 0, 4},  // AI1
+        {-1, 0, 5},  // AI2
+        {-1, 0, 12}, // AI3
+        {-1, 0, 20}, // AI4
+        {-1, 0, 21}, // AI5
+        {-1, 0, 28}, // AI6
+
+        {-1, 0, 6},  // BI1
+        {-1, 0, 13}, // BI2
+        {-1, 0, 14}, // BI3
+        {-1, 0, 22}, // BI4
+        {-1, 0, 29}, // BI5
+        {-1, 0, 30}, // BI6
+
+        { 0, 0, 22}, // ASRSTI
+        { 0, 0, 30}, // ADRSTI
+        {-1, 0, 23}, // BSRSTI
+        {-1, 0, 7},  // BDRSTI
+};
+
+const Loc ng_ultra_place_xcdc[] = {
+        { 0, 0, 1},  // AI1
+        { 0, 0, 2},  // AI2
+        { 0, 0, 9},  // AI3
+        { 0, 0, 17}, // AI4
+        { 0, 0, 18}, // AI5
+        { 0, 0, 25}, // AI6
+
+        { 0, 0, 4},  // BI1
+        { 0, 0, 5},  // BI2
+        { 0, 0, 12}, // BI3
+        { 0, 0, 20}, // BI4
+        { 0, 0, 21}, // BI5
+        { 0, 0, 28}, // BI6
+
+        {-1, 0, 22}, // ASRSTI
+        {-1, 0, 30}, // ADRSTI
+        {+1, 0, 22}, // BSRSTI
+        {+1, 0, 30}, // BDRSTI
+
+        { 0, 0, 3},  // CI1
+        { 0, 0, 10}, // CI2
+        { 0, 0, 11}, // CI3
+        { 0, 0, 19}, // CI4
+        { 0, 0, 26}, // CI5
+        { 0, 0, 27}, // CI6
+
+        { 0, 0, 6},  // DI1
+        { 0, 0, 13}, // DI2
+        { 0, 0, 14}, // DI3
+        { 0, 0, 22}, // DI4
+        { 0, 0, 29}, // DI5
+        { 0, 0, 30}, // DI6
+
+        { 0, 0, 24}, // CSRSTI
+        { 0, 0, 8},  // CDRSTI
+        { 0, 0, 23}, // DSRSTI
+        { 0, 0, 7},  // DDRSTI
+};
+
+const Loc ng_ultra_place_fifo1[] = {
+        {-1, 0, 1},  // I/O1
+        {-1, 0, 2},  // I/O2
+        {-1, 0, 5},  // I/O3
+        {-1, 0, 6},  // I/O4
+        {-1, 0, 7},  // I/O5
+        {-1, 0, 9},  // I/O6
+        {-1, 0, 10}, // I/O7
+        {-1, 0, 13}, // I/O8
+        {-1, 0, 14}, // I/O9
+        {-1, 0, 15}, // I/O10
+        {-1, 0, 16}, // I/O11
+        {-1, 0, 17}, // I/O12
+        {-1, 0, 18}, // I/O13
+        {-1, 0, 21}, // I/O14
+        {-1, 0, 24}, // I/O15
+        {-1, 0, 25}, // I/O16
+        {-1, 0, 26}, // I/O17
+        {-1, 0, 29}, // I/O18
+
+        { 0, 0, 0},  // I/O19
+        { 0, 0, 0},  // I/O20
+        { 0, 0, 0},  // I/O21
+        { 0, 0, 0},  // I/O22
+        { 0, 0, 0},  // I/O23
+        { 0, 0, 0},  // I/O24
+        { 0, 0, 0},  // I/O25
+        { 0, 0, 0},  // I/O26
+        { 0, 0, 0},  // I/O27
+        { 0, 0, 0},  // I/O28
+        { 0, 0, 0},  // I/O29
+        { 0, 0, 0},  // I/O30
+        { 0, 0, 0},  // I/O31
+        { 0, 0, 0},  // I/O32
+        { 0, 0, 0},  // I/O33
+        { 0, 0, 0},  // I/O34
+        { 0, 0, 0},  // I/O35
+        { 0, 0, 0},  // I/O36
+
+        { 0, 0, 3},  // RAI1/RAO1
+        { 0, 0, 10}, // RAI2/RAO2
+        { 0, 0, 11}, // RAI3/RAO3
+        { 0, 0, 19}, // RAI4/RAO4
+        { 0, 0, 26}, // RAI5/RAO5
+        { 0, 0, 27}, // RAI6/RAO6
+        { 0, 0, 0},  // RAI7/RAO7
+
+        { 0, 0, 1},  // WAI1/WAO1
+        { 0, 0, 2},  // WAI2/WAO2
+        { 0, 0, 9},  // WAI3/WAO3
+        { 0, 0, 17}, // WAI4/WAO4
+        { 0, 0, 18}, // WAI5/WAO5
+        { 0, 0, 25}, // WAI6/WAO6
+        { 0, 0, 0},  // WAI7/WAO7
+
+        {-1, 0, 0},  // WE
+        {-1, 0, 8},  // WEA
+
+        {-1, 0, 22}, // WRSTI1/WRSTO
+        {-1, 0, 30}, // RRSTI1/RRSTO
+        { 0, 0, 8},  // WRSTI2
+        { 0, 0, 24}, // RRSTI2
+        { 0, 0, 0},  // WRSTI3/WRSTO
+        { 0, 0, 0},  // RRSTI3/RRSTO
+        { 0, 0, 0},  // WRSTI4
+        { 0, 0, 0},  // RRSTI4
+
+        {-1, 0, 3}, // WEQ
+        {-1, 0, 4}, // REQ
+        // {-1, 0, 11}, WEQ
+        // {-1, 0, 12}, REQ
+        // {-1, 0, 19}, WEQ
+        // {-1, 0, 20}, REQ
+        // {-1, 0, 27}, WEQ
+        // {-1, 0, 28}, REQ
+        { 0, 0, 0}, // WEQ2
+        { 0, 0, 0}, // REQ2
+};
+
+const Loc ng_ultra_place_fifo2[] = {
+        {+1, 0, 1},  // I/O1
+        {+1, 0, 2},  // I/O2
+        {+1, 0, 5},  // I/O3
+        {+1, 0, 6},  // I/O4
+        {+1, 0, 7},  // I/O5
+        {+1, 0, 9},  // I/O6
+        {+1, 0, 10}, // I/O7
+        {+1, 0, 13}, // I/O8
+        {+1, 0, 14}, // I/O9
+        {+1, 0, 15}, // I/O10
+        {+1, 0, 16}, // I/O11
+        {+1, 0, 17}, // I/O12
+        {+1, 0, 18}, // I/O13
+        {+1, 0, 21}, // I/O14
+        {+1, 0, 24}, // I/O15
+        {+1, 0, 25}, // I/O16
+        {+1, 0, 26}, // I/O17
+        {+1, 0, 29}, // I/O18
+
+        { 0, 0, 0},  // I/O19
+        { 0, 0, 0},  // I/O20
+        { 0, 0, 0},  // I/O21
+        { 0, 0, 0},  // I/O22
+        { 0, 0, 0},  // I/O23
+        { 0, 0, 0},  // I/O24
+        { 0, 0, 0},  // I/O25
+        { 0, 0, 0},  // I/O26
+        { 0, 0, 0},  // I/O27
+        { 0, 0, 0},  // I/O28
+        { 0, 0, 0},  // I/O29
+        { 0, 0, 0},  // I/O30
+        { 0, 0, 0},  // I/O31
+        { 0, 0, 0},  // I/O32
+        { 0, 0, 0},  // I/O33
+        { 0, 0, 0},  // I/O34
+        { 0, 0, 0},  // I/O35
+        { 0, 0, 0},  // I/O36
+
+        { 0, 0, 6},  // RAI1/RAO1
+        { 0, 0, 13}, // RAI2/RAO2
+        { 0, 0, 14}, // RAI3/RAO3
+        { 0, 0, 22}, // RAI4/RAO4
+        { 0, 0, 29}, // RAI5/RAO5
+        { 0, 0, 30}, // RAI6/RAO6
+        { 0, 0, 0},  // RAI7/RAO7
+
+        { 0, 0, 4},  // WAI1/WAO1
+        { 0, 0, 5},  // WAI2/WAO2
+        { 0, 0, 12}, // WAI3/WAO3
+        { 0, 0, 20}, // WAI4/WAO4
+        { 0, 0, 21}, // WAI5/WAO5
+        { 0, 0, 28}, // WAI6/WAO6
+        { 0, 0, 0},  // WAI7/WAO7
+
+        {+1, 0, 0},  // WE
+        {+1, 0, 8},  // WEA
+
+        {+1, 0, 22}, // WRSTI1/WRSTO
+        {+1, 0, 30}, // RRSTI1/RRSTO
+        { 0, 0, 7},  // WRSTI2
+        { 0, 0, 23}, // RRSTI2
+        { 0, 0, 0},  // WRSTI3/WRSTO
+        { 0, 0, 0},  // RRSTI3/RRSTO
+        { 0, 0, 0},  // WRSTI4
+        { 0, 0, 0},  // RRSTI4
+
+        {+1, 0, 3}, // WEQ
+        {+1, 0, 4}, // REQ
+        // {+1, 0, 11}, WEQ
+        // {+1, 0, 12}, REQ
+        // {+1, 0, 19}, WEQ
+        // {+1, 0, 20}, REQ
+        // {+1, 0, 27}, WEQ
+        // {+1, 0, 28}, REQ
+        { 0, 0, 0}, // WEQ2
+        { 0, 0, 0}, // REQ2
+};
+
+const Loc ng_ultra_place_xfifo[] = {
+        {-1, 0, 1},  // I/O1
+        {-1, 0, 2},  // I/O2
+        {-1, 0, 5},  // I/O3
+        {-1, 0, 6},  // I/O4
+        {-1, 0, 7},  // I/O5
+        {-1, 0, 9},  // I/O6
+        {-1, 0, 10}, // I/O7
+        {-1, 0, 13}, // I/O8
+        {-1, 0, 14}, // I/O9
+        {-1, 0, 15}, // I/O10
+        {-1, 0, 16}, // I/O11
+        {-1, 0, 17}, // I/O12
+        {-1, 0, 18}, // I/O13
+        {-1, 0, 21}, // I/O14
+        {-1, 0, 24}, // I/O15
+        {-1, 0, 25}, // I/O16
+        {-1, 0, 26}, // I/O17
+        {-1, 0, 29}, // I/O18
+        {+1, 0, 1},  // I/O19
+        {+1, 0, 2},  // I/O20
+        {+1, 0, 5},  // I/O21
+        {+1, 0, 6},  // I/O22
+        {+1, 0, 7},  // I/O23
+        {+1, 0, 9},  // I/O24
+        {+1, 0, 10}, // I/O25
+        {+1, 0, 13}, // I/O26
+        {+1, 0, 14}, // I/O27
+        {+1, 0, 15}, // I/O28
+        {+1, 0, 16}, // I/O29
+        {+1, 0, 17}, // I/O30
+        {+1, 0, 18}, // I/O31
+        {+1, 0, 21}, // I/O32
+        {+1, 0, 24}, // I/O33
+        {+1, 0, 25}, // I/O34
+        {+1, 0, 26}, // I/O35
+        {+1, 0, 29}, // I/O36
+
+        { 0, 0, 3},  // RAI1/RAO1
+        { 0, 0, 10}, // RAI2/RAO2
+        { 0, 0, 11}, // RAI3/RAO3
+        { 0, 0, 19}, // RAI4/RAO4
+        { 0, 0, 26}, // RAI5/RAO5
+        { 0, 0, 27}, // RAI6/RAO6
+        { 0, 0, 6},  // RAI7/RAO7
+
+        { 0, 0, 1},  // WAI1/WAO1
+        { 0, 0, 2},  // WAI2/WAO2
+        { 0, 0, 9},  // WAI3/WAO3
+        { 0, 0, 17}, // WAI4/WAO4
+        { 0, 0, 18}, // WAI5/WAO5
+        { 0, 0, 25}, // WAI6/WAO6
+        { 0, 0, 4},  // WAI7/WAO7
+
+        {-1, 0, 0},  // WE
+        {-1, 0, 8},  // WEA
+
+        {-1, 0, 22}, // WRSTI1/WRSTO
+        {-1, 0, 30}, // RRSTI1/RRSTO
+        { 0, 0, 8},  // WRSTI2
+        { 0, 0, 24}, // RRSTI2
+        {+1, 0, 22}, // WRSTI3/WRSTO
+        {+1, 0, 30}, // RRSTI3/RRSTO
+        { 0, 0, 7},  // WRSTI4
+        { 0, 0, 23}, // RRSTI4
+
+        {-1, 0, 3}, // WEQ1
+        {-1, 0, 4}, // REQ1
+        // {-1, 0, 11}, WEQ1
+        // {-1, 0, 12}, REQ1
+        // {-1, 0, 19}, WEQ1
+        // {-1, 0, 20}, REQ1
+        // {-1, 0, 27}, WEQ1
+        // {-1, 0, 28}, REQ1
+        {+1, 0, 3}, // WEQ2
+        {+1, 0, 4}, // REQ2
+        // {+1, 0, 11}, WEQ2
+        // {+1, 0, 12}, REQ2
+        // {+1, 0, 19}, WEQ2
+        // {+1, 0, 20}, REQ2
+        // {+1, 0, 27}, WEQ2
+        // {+1, 0, 28}, REQ2
+};
+/* clang-format on */
+
+}; // namespace
+
+namespace ng_ultra {
+
+Loc getNextLocInDSPChain(const NgUltraImpl *impl, Loc loc)
+{
+    BelId bel = impl->ctx->getBelByLocation(loc);
+    if (impl->dsp_cascade.count(bel) == 0) {
+        loc.z = -1; // End of chain
+        return loc;
+    }
+    BelId dsp = impl->dsp_cascade.at(bel);
+    return impl->ctx->getBelLocation(dsp);
+}
+
+Loc getNextLocInCYChain(Loc loc)
+{
+    int section = (loc.x % 4 - 1 + 3 * (loc.y % 4)) * 4 + loc.z - BEL_CY_Z;
+    Loc result = ng_ultra_place_cy_map[section];
+    result.x += loc.x;
+    result.y += loc.y;
+    result.z += loc.z;
+    return result;
+}
+
+Loc getNextLocInLUTChain(Loc loc)
+{
+    Loc result = loc;
+    result.x = loc.x;
+    result.y = loc.y;
+    result.z = (loc.z + 8) % 32; // BEL_LUT_Z is 0
+    return result;
+}
+
+Loc getNextLocInDFFChain(Loc loc)
+{
+    Loc result = loc;
+    if (loc.z == 31) {
+        if ((loc.x & 3) == 3) {
+            result.z = -1; // End of chain
+            return result;
+        }
+        result.z = 0;
+        result.x++;
+        return result;
+    }
+    int z = loc.z + 8;
+    if (z > 31)
+        z++;
+    result.z = z % 32; // BEL_LUT_Z is 0
+    return result;
+}
+
+Loc getCYFE(Loc root, int pos)
+{
+    int p[] = {2 - 1, 25 - 1, 10 - 1, 17 - 1};
+    int cy = root.z - BEL_CY_Z;
+    Loc result;
+    result.x = root.x;
+    result.y = root.y;
+    result.z = p[pos] + cy * 2;
+    return result;
+}
+
+Loc getXLUTFE(Loc root, int pos)
+{
+    Loc result;
+    result.x = root.x;
+    result.y = root.y;
+    result.z = root.z - BEL_XLUT_Z + 8 * pos;
+    return result;
+}
+
+Loc getXRFFE(Loc root, int pos)
+{
+    Loc result = ng_ultra_place_xrf[pos];
+    if (root.z == BEL_XRF_Z) {
+        // XRF1
+        result.x += root.x;
+    } else {
+        // RF1 or RF2
+        result.x = root.x + ((root.z == BEL_RF_Z) ? -1 : +1);
+    }
+    result.y = root.y;
+    return result;
+}
+
+Loc getCDCFE(Loc root, int pos)
+{
+    Loc result;
+    if (root.z == BEL_CDC_Z) {
+        result = ng_ultra_place_cdc1[pos];
+    } else if (root.z == BEL_CDC_Z + 1) {
+        result = ng_ultra_place_cdc2[pos];
+    } else if (root.z == BEL_XCDC_Z) {
+        result = ng_ultra_place_xcdc[pos];
+    } else {
+        log_error("Trying to place CDC on wrong location.\n");
+    }
+    result.x += root.x;
+    result.y = root.y;
+    return result;
+}
+
+Loc getFIFOFE(Loc root, int pos)
+{
+    Loc result;
+    if (root.z == BEL_FIFO_Z) {
+        result = ng_ultra_place_fifo1[pos];
+    } else if (root.z == BEL_FIFO_Z + 1) {
+        result = ng_ultra_place_fifo2[pos];
+    } else if (root.z == BEL_XFIFO_Z) {
+        result = ng_ultra_place_xfifo[pos];
+    } else {
+        log_error("Trying to place CDC on wrong location.\n");
+    }
+    result.x += root.x;
+    result.y = root.y;
+    return result;
+}
+
+}; // namespace ng_ultra
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/location_map.h b/himbaechel/uarch/ng-ultra/location_map.h
new file mode 100644
index 0000000000..f856e72975
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/location_map.h
@@ -0,0 +1,43 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+#include "ng_ultra.h"
+
+#ifndef NG_ULTRA_LOCATION_MAP_H
+#define NG_ULTRA_LOCATION_MAP_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace ng_ultra {
+
+Loc getNextLocInDSPChain(const NgUltraImpl *impl, Loc loc);
+Loc getNextLocInCYChain(Loc loc);
+Loc getNextLocInLUTChain(Loc loc);
+Loc getNextLocInDFFChain(Loc loc);
+Loc getCYFE(Loc root, int pos);
+Loc getXLUTFE(Loc root, int pos);
+Loc getXRFFE(Loc root, int pos);
+Loc getCDCFE(Loc root, int pos);
+Loc getFIFOFE(Loc root, int pos);
+
+}; // namespace ng_ultra
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc
new file mode 100644
index 0000000000..f5932e71af
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc
@@ -0,0 +1,1069 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <boost/algorithm/string.hpp>
+#include <fstream>
+#include <queue>
+
+#include "design_utils.h"
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "placer_heap.h"
+#include "util.h"
+
+#include "himbaechel_helpers.h"
+
+#include "location_map.h"
+#include "ng_ultra.h"
+
+#define GEN_INIT_CONSTIDS
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+using namespace NEXTPNR_NAMESPACE_PREFIX ng_ultra;
+
+NEXTPNR_NAMESPACE_BEGIN
+
+NgUltraImpl::~NgUltraImpl() {};
+
+void NgUltraImpl::init_database(Arch *arch)
+{
+    init_uarch_constids(arch);
+    arch->load_chipdb("ng-ultra/chipdb-ng-ultra.bin");
+    arch->set_package("FF-1760");
+    arch->set_speed_grade("DEFAULT");
+}
+
+void NgUltraImpl::init(Context *ctx)
+{
+    HimbaechelAPI::init(ctx);
+    for (int i = 1; i <= 8; i++)
+        for (int j = 0; j < 20; j++)
+            gck_per_lobe[i].push_back(GckConfig(BelId()));
+    for (auto bel : ctx->getBels()) {
+        if (ctx->getBelType(bel) == id_IOM) {
+            std::set<IdString> ckg;
+            IdString bank = tile_name_id(bel.tile);
+            iom_bels.emplace(bank, bel);
+            WireId belpin = ctx->getBelPinWire(bel, id_CKO1);
+            for (auto dh : ctx->getPipsDownhill(belpin)) {
+                WireId pip_dst = ctx->getPipDstWire(dh);
+                for (const auto &item : ctx->getWireBelPins(pip_dst)) {
+                    if (boost::contains(ctx->nameOfBel(item.bel), "WFG_C")) {
+                        unused_wfg[item.bel] = tile_name_id(item.bel.tile);
+                    } else if (boost::contains(ctx->nameOfBel(item.bel), "PLL")) {
+                        ckg.emplace(tile_name_id(item.bel.tile));
+                        unused_pll[item.bel] = tile_name_id(item.bel.tile);
+                    }
+                }
+            }
+            std::pair<IdString, IdString> p;
+            p.first = *ckg.begin();
+            if (ckg.size() == 2)
+                p.second = *(ckg.begin()++);
+            bank_to_ckg[bank] = p;
+        } else if (ctx->getBelType(bel) == id_IOTP) {
+            if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) {
+                global_capable_bels.emplace(bel, id_P17RI);
+            } else if (ctx->getBelName(bel)[1] == ctx->id("D09P_CLK.IOTP")) {
+                global_capable_bels.emplace(bel, id_P19RI);
+            }
+        } else if (ctx->getBelType(bel) == id_GCK) {
+            std::string name = ctx->getBelName(bel)[1].c_str(ctx);
+            int lobe = std::stoi(name.substr(1, 1));
+            int num = std::stoi(name.substr(4, 2).c_str());
+            gck_per_lobe[lobe][num - 1] = GckConfig(bel);
+        }
+        locations.emplace(stringf("%s:%s", tile_name(bel.tile).c_str(), ctx->getBelName(bel)[1].c_str(ctx)), bel);
+        Loc loc = ctx->getBelLocation(bel);
+        tile_locations.emplace(tile_name(bel.tile).c_str(), Loc(loc.x & 0xfffe, loc.y & 0xfffe, 0));
+    }
+    for (auto bel : ctx->getBels()) {
+        if (ctx->getBelType(bel) == id_DSP) {
+            WireId cco = ctx->getBelPinWire(bel, id_CCO);
+            WireId cci;
+            for (auto dh : ctx->getPipsDownhill(cco)) {
+                cci = ctx->getPipDstWire(dh);
+            }
+            if (cci != WireId()) {
+                std::string loc = stringf("%s:%s", tile_name(cci.tile).c_str(), ctx->getWireName(cci)[1].c_str(ctx));
+                loc.erase(loc.find(".CCI"));
+                BelId dsp_bel = locations[loc];
+                dsp_cascade.emplace(dsp_bel, bel);
+            }
+        }
+    }
+}
+
+namespace {
+// Note: These are per Cell type not Bel type
+// Sinks
+const dict<IdString, pool<IdString>> fabric_lowskew_sinks = {
+        // TILE - DFF
+        {id_BEYOND_FE, {id_CK, id_L, id_R}},
+        // { id_DFF, { id_CK }},  // This is part of BEYOND_FE
+        // TILE - Register file
+        {id_RF, {id_WCK}},
+        {id_RFSP, {id_WCK}},
+        {id_XHRF, {id_WCK1, id_WCK2}},
+        {id_XWRF, {id_WCK1, id_WCK2}},
+        {id_XPRF, {id_WCK1, id_WCK2}},
+        // TILE - CDC
+        {id_CDC, {id_CK1, id_CK2}},
+        {id_DDE, {id_CK1, id_CK2}},
+        {id_TDE, {id_CK1, id_CK2}},
+        {id_XCDC, {id_CK1, id_CK2}},
+        // TILE - FIFO
+        {id_FIFO, {id_RCK, id_WCK}},
+        {id_XHFIFO, {id_RCK1, id_RCK2, id_WCK1, id_WCK2}},
+        {id_XWFIFO, {id_RCK1, id_RCK2, id_WCK1, id_WCK2}},
+        // CGB - RAM
+        {id_RAM, {id_ACK, id_BCK}},
+        // CGB - DSP
+        {id_DSP, {id_CK}},
+};
+
+const dict<IdString, pool<IdString>> ring_clock_sinks = {
+        // CKG
+        {id_PLL, {id_CLK_CAL, id_FBK, id_REF}},
+        {id_WFB, {id_ZI}},
+        {id_WFG, {id_ZI}}};
+
+const dict<IdString, pool<IdString>> ring_over_tile_clock_sinks = {
+        // IOB
+        {id_DFR, {id_CK}},
+        {id_DDFR, {id_CK, id_CKF}},
+};
+// IOB
+// { id_IOM, { id_ALCK1, id_ALCK2, id_ALCK3, id_CCK, id_FCK1, id_FCK2, id_FDCK,
+//             id_LDSCK1, id_LDSCK2, id_LDSCK3, id_SWRX1CK, id_SWRX2CK }},
+
+// HSSL
+// { id_CRX, { id_LINK }},
+// { id_CTX, { id_LINK }},
+// { id_PMA, { id_hssl_clock_i1, id_hssl_clock_i2, id_hssl_clock_i3, id_hssl_clock_i4 },
+
+const dict<IdString, pool<IdString>> tube_clock_sinks = {
+        // TUBE
+        {id_GCK, {id_SI1, id_SI2}},
+};
+// Sources
+// CKG
+const dict<IdString, pool<IdString>> ring_clock_source = {
+        {id_IOM, {id_CKO1, id_CKO2}},
+        {id_WFB, {id_ZO}},
+        {id_WFG, {id_ZO}},
+        {id_PLL,
+         {id_OSC, id_VCO, id_REFO, id_LDFO, id_CLK_DIV1, id_CLK_DIV2, id_CLK_DIV3, id_CLK_DIV4, id_CLK_DIVD1,
+          id_CLK_DIVD2, id_CLK_DIVD3, id_CLK_DIVD4, id_CLK_DIVD5, id_CLK_CAL_DIV}}};
+// TUBE
+const dict<IdString, pool<IdString>> tube_clock_source = {
+        {id_GCK, {id_SO}},
+};
+
+}; // namespace
+
+const dict<IdString, pool<IdString>> &NgUltraImpl::get_fabric_lowskew_sinks() { return fabric_lowskew_sinks; }
+
+bool NgUltraImpl::is_fabric_lowskew_sink(const PortRef &ref)
+{
+    return fabric_lowskew_sinks.count(ref.cell->type) && fabric_lowskew_sinks.at(ref.cell->type).count(ref.port);
+}
+
+bool NgUltraImpl::is_ring_clock_sink(const PortRef &ref)
+{
+    return ring_clock_sinks.count(ref.cell->type) && ring_clock_sinks.at(ref.cell->type).count(ref.port);
+}
+
+bool NgUltraImpl::is_ring_over_tile_clock_sink(const PortRef &ref)
+{
+    return ring_over_tile_clock_sinks.count(ref.cell->type) &&
+           ring_over_tile_clock_sinks.at(ref.cell->type).count(ref.port);
+}
+
+bool NgUltraImpl::is_tube_clock_sink(const PortRef &ref)
+{
+    return tube_clock_sinks.count(ref.cell->type) && tube_clock_sinks.at(ref.cell->type).count(ref.port);
+}
+
+bool NgUltraImpl::is_ring_clock_source(const PortRef &ref)
+{
+    return ring_clock_source.count(ref.cell->type) && ring_clock_source.at(ref.cell->type).count(ref.port);
+}
+
+bool NgUltraImpl::is_tube_clock_source(const PortRef &ref)
+{
+    return tube_clock_source.count(ref.cell->type) && tube_clock_source.at(ref.cell->type).count(ref.port);
+}
+
+const NGUltraTileInstExtraDataPOD *NgUltraImpl::tile_extra_data(int tile) const
+{
+    return reinterpret_cast<const NGUltraTileInstExtraDataPOD *>(ctx->chip_info->tile_insts[tile].extra_data.get());
+}
+
+const NGUltraPipExtraDataPOD *NgUltraImpl::pip_extra_data(PipId pip) const
+{
+    return reinterpret_cast<const NGUltraPipExtraDataPOD *>(chip_pip_info(ctx->chip_info, pip).extra_data.get());
+}
+
+const NGUltraBelExtraDataPOD *NgUltraImpl::bel_extra_data(BelId bel) const
+{
+    return reinterpret_cast<const NGUltraBelExtraDataPOD *>(chip_bel_info(ctx->chip_info, bel).extra_data.get());
+}
+
+IdString NgUltraImpl::tile_name_id(int tile) const
+{
+    const auto &data = *tile_extra_data(tile);
+    return IdString(data.name);
+}
+
+std::string NgUltraImpl::tile_name(int tile) const { return stringf("%s", tile_name_id(tile).c_str(ctx)); }
+
+int NgUltraImpl::tile_lobe(int tile) const
+{
+    const auto &data = *tile_extra_data(tile);
+    return data.lobe;
+}
+
+TileTypeExtra NgUltraImpl::tile_type(int tile) const
+{
+    const auto &data = *tile_extra_data(tile);
+    return (TileTypeExtra)data.tile_type;
+}
+
+bool NgUltraImpl::get_mux_data(BelId bel, IdString port, uint8_t *value)
+{
+    return get_mux_data(ctx->getBelPinWire(bel, port), value);
+}
+
+bool NgUltraImpl::get_mux_data(WireId wire, uint8_t *value)
+{
+    for (PipId pip : ctx->getPipsUphill(wire)) {
+        if (!ctx->getBoundPipNet(pip))
+            continue;
+        const auto &extra_data = *pip_extra_data(pip);
+        if (!extra_data.name)
+            continue;
+        if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
+            *value = extra_data.input;
+            return true;
+        }
+    }
+    return false;
+}
+
+bool NgUltraImpl::update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip)
+{
+    const auto &extra_data = *bel_extra_data(bel);
+    // Check if CSC mode only if FE is capable
+    if (extra_data.flags & BEL_EXTRA_FE_CSC) {
+        WireId dwire = ctx->getPipDstWire(dst_pip);
+        for (PipId pip : ctx->getPipsDownhill(dwire)) {
+            if (!ctx->getBoundPipNet(pip))
+                continue;
+            for (PipId pip2 : ctx->getPipsDownhill(ctx->getPipDstWire(pip))) {
+                if (!ctx->getBoundPipNet(pip2))
+                    continue;
+                IdString dst = ctx->getWireName(ctx->getPipDstWire(pip2))[1];
+                if (boost::ends_with(dst.c_str(ctx), ".DS")) {
+                    cell->setParam(id_type, Property("CSC"));
+                    return true;
+                }
+            }
+        }
+    }
+    return false;
+}
+
+bool NgUltraImpl::update_bff_to_scc(CellInfo *cell, BelId bel, PipId dst_pip)
+{
+    const auto &extra_data = *bel_extra_data(bel);
+    // Check if SCC mode only if FE is capable
+    if (extra_data.flags & BEL_EXTRA_FE_SCC) {
+        WireId dwire = ctx->getPipDstWire(dst_pip);
+        for (PipId pip : ctx->getPipsUphill(dwire)) {
+            if (!ctx->getBoundPipNet(pip))
+                continue;
+            for (PipId pip2 : ctx->getPipsUphill(ctx->getPipSrcWire(pip))) {
+                if (!ctx->getBoundPipNet(pip2))
+                    continue;
+                IdString dst = ctx->getWireName(ctx->getPipSrcWire(pip2))[1];
+                if (boost::starts_with(dst.c_str(ctx), "SYSTEM.ST1")) {
+                    cell->setParam(id_type, Property("SCC"));
+                    return true;
+                }
+            }
+        }
+    }
+    return false;
+}
+
+void NgUltraImpl::postRoute()
+{
+    ctx->assignArchInfo();
+    log_break();
+    log_info("Resources spent on routing:\n");
+    int bff_count = 0, csc_count = 0, scc_count = 0, lut_bypass = 0, fe_new = 0, wfg_bypass = 0, gck_bypass = 0;
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        for (auto &w : ni->wires) {
+            if (w.second.pip != PipId()) {
+                const auto &extra_data = *pip_extra_data(w.second.pip);
+                if (!extra_data.name)
+                    continue;
+                if (extra_data.type == PipExtra::PIP_EXTRA_BYPASS) {
+                    IdStringList id = ctx->getPipName(w.second.pip);
+                    BelId bel = ctx->getBelByName(IdStringList::concat(id[0], IdString(extra_data.name)));
+                    IdString type = ctx->getBelType(bel);
+                    if (!ctx->getBoundBelCell(bel)) {
+                        CellInfo *cell = ctx->createCell(ctx->id(ctx->nameOfBel(bel)), type);
+                        ctx->bindBel(bel, cell, PlaceStrength::STRENGTH_FIXED);
+                        if (type == id_BEYOND_FE)
+                            fe_new++;
+                    }
+                    CellInfo *cell = ctx->getBoundBelCell(bel);
+                    switch (type.index) {
+                    case id_BEYOND_FE.index:
+                        if (extra_data.input == 0) {
+                            // set bypass mode for DFF
+                            cell->setParam(id_type, Property("BFF"));
+                            cell->params[id_dff_used] = Property(1, 1);
+                            // Note: no conflict, CSC and SCC modes are never available on same position
+                            if (update_bff_to_csc(cell, bel, w.second.pip))
+                                csc_count++;
+                            else if (update_bff_to_scc(cell, bel, w.second.pip))
+                                scc_count++;
+                            else
+                                bff_count++;
+                        } else {
+                            lut_bypass++;
+                            cell->params[id_lut_used] = Property(1, 1);
+                            cell->params[id_lut_table] = Property(0xaaaa, 16);
+                        }
+                        break;
+                    case id_WFG.index:
+                        wfg_bypass++;
+                        cell->type = id_WFB;
+                        break;
+                    case id_GCK.index:
+                        gck_bypass++;
+                        cell->setParam(id_std_mode, extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
+                        break;
+                    default:
+                        log_error("Unmaped bel type '%s' for routing\n", type.c_str(ctx));
+                    }
+                }
+            }
+        }
+    }
+    if (bff_count)
+        log_info("    %6d DFFs used as BFF\n", bff_count);
+    if (csc_count)
+        log_info("    %6d DFFs used as CSC\n", csc_count);
+    if (scc_count)
+        log_info("    %6d DFFs used as SCC\n", scc_count);
+    if (lut_bypass)
+        log_info("    %6d LUTs used in bypass mode\n", lut_bypass);
+    if (fe_new)
+        log_info("    %6d newly allocated FEs\n", fe_new);
+    if (wfg_bypass)
+        log_info("    %6d WFGs used as WFB\n", wfg_bypass);
+    if (gck_bypass)
+        log_info("    %6d GCK\n", gck_bypass);
+
+    // Handle LUT permutation
+    for (auto &cell : ctx->cells) {
+        if (cell.second->type == id_BEYOND_FE) {
+            // if LUT part used
+            if (cell.second->params.count(id_lut_table) != 0) {
+                std::array<std::vector<unsigned>, 4> phys_to_log;
+                unsigned orig_init = int_or_default(cell.second->params, id_lut_table);
+                const std::array<IdString, 4> ports{id_I1, id_I2, id_I3, id_I4};
+                for (unsigned i = 0; i < 4; i++) {
+                    WireId pin_wire = ctx->getBelPinWire(cell.second->bel, ports[i]);
+                    for (PipId pip : ctx->getPipsUphill(pin_wire)) {
+                        if (!ctx->getBoundPipNet(pip))
+                            continue;
+                        const auto &extra_data = *pip_extra_data(pip);
+                        if (!extra_data.name)
+                            continue;
+                        if (extra_data.type == PipExtra::PIP_EXTRA_LUT_PERMUTATION) {
+                            NPNR_ASSERT(extra_data.output == i);
+                            phys_to_log[extra_data.input].push_back(i);
+                        }
+                    }
+                }
+                unsigned permuted_init = 0;
+                for (unsigned i = 0; i < 16; i++) {
+                    unsigned log_idx = 0;
+                    for (unsigned j = 0; j < 4; j++) {
+                        if ((i >> j) & 0x1) {
+                            for (auto log_pin : phys_to_log[j])
+                                log_idx |= (1 << log_pin);
+                        }
+                    }
+                    if ((orig_init >> log_idx) & 0x1)
+                        permuted_init |= (1 << i);
+                }
+                cell.second->params[id_lut_table] = Property(permuted_init, 16);
+            }
+        }
+    }
+
+    fixup_crossbars();
+
+    print_utilisation(ctx);
+    const ArchArgs &args = ctx->args;
+    if (args.options.count("bit")) {
+        write_bitstream_json(args.options.at("bit"));
+    }
+}
+
+void NgUltraImpl::configurePlacerHeap(PlacerHeapCfg &cfg)
+{
+    cfg.beta = 0.5;
+    cfg.placeAllAtOnce = true;
+}
+
+namespace {
+
+template <size_t N> bool check_assign_sig(std::array<const NetInfo *, N> &sig_set, const NetInfo *sig)
+{
+    if (sig == nullptr)
+        return true;
+    for (size_t i = 0; i < N; i++)
+        if (sig_set[i] == sig) {
+            return true;
+        } else if (sig_set[i] == nullptr) {
+            sig_set[i] = sig;
+            return true;
+        }
+    return false;
+};
+
+struct SectionFEWorker
+{
+    std::array<const NetInfo *, 2> clk{};    // from local system matrix
+    std::array<const NetInfo *, 2> reset{};  // from local system matrix
+    std::array<const NetInfo *, 2> load{};   // from local system matrix
+    std::array<const NetInfo *, 1> shared{}; // 1 from local system matrix
+    // Additional R and L can be used from RI network
+    bool run(const NgUltraImpl *impl, const Context *ctx, BelId bel, CellInfo *cell)
+    {
+        Loc loc = ctx->getBelLocation(bel);
+        for (uint8_t id = 0; id <= BEL_LUT_MAX_Z; id++) {
+            const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, id)));
+            if (ff == nullptr)
+                continue;
+            if (!check_assign_sig(reset, ff->getPort(id_R))) {
+                if (!check_assign_sig(shared, ff->getPort(id_R)))
+                    return false;
+            }
+            if (!check_assign_sig(load, ff->getPort(id_L))) {
+                if (!check_assign_sig(shared, ff->getPort(id_L)))
+                    return false;
+            }
+            if (!check_assign_sig(clk, ff->getPort(id_CK)))
+                return false;
+        }
+        const auto &extra_data = *impl->bel_extra_data(bel);
+        if (cell->params.count(id_type)) {
+            const std::string &type = cell->params[id_type].as_string();
+            if (type == "CSC" && (extra_data.flags & BEL_EXTRA_FE_CSC) == 0)
+                return false; // No CSC capability on FE
+            if (type == "SCC" && (extra_data.flags & BEL_EXTRA_FE_SCC) == 0)
+                return false; // No SCC capability on FE
+        }
+        if (extra_data.flags & BEL_EXTRA_FE_CSC)
+            return false;
+        return true;
+    }
+};
+
+}; // namespace
+
+bool NgUltraImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
+{
+    CellInfo *cell = ctx->getBoundBelCell(bel);
+    if (cell == nullptr) {
+        return true;
+    }
+    if (ctx->getBelType(bel) == id_BEYOND_FE) {
+        SectionFEWorker worker;
+        return worker.run(this, ctx, bel, cell);
+    } else if (ctx->getBelType(bel).in(id_RF, id_XRF)) {
+        Loc loc = ctx->getBelLocation(bel);
+        if (loc.z == BEL_XRF_Z) {
+            // If we used any of RFs we can not used XRF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_RF_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_RF_Z + 1))))
+                return false;
+            // If we used any FIFO we can not use XRF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z + 1))))
+                return false;
+            // If we used XFIFO we can not use XRF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XFIFO_Z))))
+                return false;
+        } else {
+            // If we used XRF we can not use individual RF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XRF_Z))))
+                return false;
+            // If we used XFIFO we can not use RF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XFIFO_Z))))
+                return false;
+            int index = loc.z - BEL_RF_Z;
+            // If we used coresponding FIFO we can not use RF
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z + index))))
+                return false;
+        }
+    } else if (ctx->getBelType(bel).in(id_FIFO, id_XFIFO)) {
+        Loc loc = ctx->getBelLocation(bel);
+        if (loc.z == BEL_XFIFO_Z) {
+            // If we used any of RFs we can not used XFIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_RF_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_RF_Z + 1))))
+                return false;
+            // If we used any FIFO we can not use XFIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z + 1))))
+                return false;
+            // If we used XFIFO we can not use XFIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XFIFO_Z))))
+                return false;
+            // If we used any CDC we can not use XFIFO
+            // NOTE: CDC1 is in S4 and CDC2 is S12
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x - 1, loc.y, BEL_CDC_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + 1, loc.y, BEL_CDC_Z + 1))))
+                return false;
+            // If we used XCDC we can not use XFIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XCDC_Z))))
+                return false;
+        } else {
+            // If we used XFIFO we can not use individual FIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XFIFO_Z))))
+                return false;
+            // If we used XRF we can not use FIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XRF_Z))))
+                return false;
+            // If we used XCDC we can not use FIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XCDC_Z))))
+                return false;
+            int index = loc.z - BEL_FIFO_Z;
+            // If we used coresponding RF we can not use FIFO
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_RF_Z + index))))
+                return false;
+            // If we used coresponding CDC we can not use FIFO
+            // NOTE: CDC1 is in S4 and CDC2 is S12
+            int rel = (index == 0) ? -1 : +1;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + rel, loc.y, BEL_CDC_Z + index))))
+                return false;
+        }
+    } else if (ctx->getBelType(bel).in(id_CDC, id_XCDC)) {
+        Loc loc = ctx->getBelLocation(bel);
+        if (loc.z == BEL_XCDC_Z) {
+            // If we used any of CDCs we can not used XCDC
+            // NOTE: CDC1 is in S4 and CDC2 is S12
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x - 1, loc.y, BEL_CDC_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + 1, loc.y, BEL_CDC_Z + 1))))
+                return false;
+            // If we used any FIFO we can not use XCDC
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z))))
+                return false;
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_FIFO_Z + 1))))
+                return false;
+            // If we used XFIFO we can not use XCDC
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BEL_XFIFO_Z))))
+                return false;
+        } else {
+            // NOTE: CDC1 is in S4 and CDC2 is S12 so we move calculation relative to S8
+            int index = loc.z - BEL_CDC_Z;
+            int fix = (index == 0) ? +1 : -1;
+            // If we used XCDC we can not use individual CDC
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + fix, loc.y, BEL_XCDC_Z))))
+                return false;
+            // If we used XFIFO we can not use CDC
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + fix, loc.y, BEL_XFIFO_Z))))
+                return false;
+            // If we used coresponding FIFO we can not use CDC
+            if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x + fix, loc.y, BEL_FIFO_Z + index))))
+                return false;
+        }
+    }
+    return true;
+}
+
+// Bel bucket functions
+IdString NgUltraImpl::getBelBucketForCellType(IdString cell_type) const
+{
+    if (cell_type.in(id_IOP, id_IP, id_OP, id_IOTP, id_ITP, id_OTP))
+        return ctx->idf("IOP/IOTP");
+    else if (cell_type.in(id_BFR, id_DFR, id_DDFR))
+        return ctx->idf("DFR/DDFR");
+    else if (cell_type.in(id_RF, id_RFSP))
+        return id_RF;
+    else if (cell_type.in(id_XHRF, id_XWRF, id_XPRF))
+        return id_XRF;
+    else if (cell_type.in(id_DDE, id_TDE, id_CDC, id_BGC, id_GBC))
+        return id_CDC;
+    else if (cell_type.in(id_XCDC))
+        return id_XCDC;
+    else if (cell_type.in(id_FIFO))
+        return id_FIFO;
+    else if (cell_type.in(id_XHFIFO, id_XWFIFO))
+        return id_XFIFO;
+    else if (cell_type.in(id_WFB, id_WFG))
+        return id_WFG;
+    else
+        return cell_type;
+}
+
+BelBucketId NgUltraImpl::getBelBucketForBel(BelId bel) const
+{
+    IdString bel_type = ctx->getBelType(bel);
+    if (bel_type.in(id_IOP, id_IOTP))
+        return ctx->idf("IOP/IOTP");
+    else if (bel_type.in(id_DFR, id_DDFR))
+        return ctx->idf("DFR/DDFR");
+    return bel_type;
+}
+
+bool NgUltraImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
+{
+    IdString bel_type = ctx->getBelType(bel);
+    if (bel_type == id_IOTP)
+        return cell_type.in(id_IOP, id_IP, id_OP, id_IOTP, id_ITP, id_OTP);
+    else if (bel_type == id_IOP)
+        return cell_type.in(id_IOP, id_IP, id_OP);
+    else if (bel_type == id_DDFR)
+        return cell_type.in(id_BFR, id_DFR, id_DDFR);
+    else if (bel_type == id_DFR)
+        return cell_type.in(id_BFR, id_DFR);
+    else if (bel_type == id_RF)
+        return cell_type.in(id_RF, id_RFSP);
+    else if (bel_type == id_XRF)
+        return cell_type.in(id_XHRF, id_XWRF, id_XPRF);
+    else if (bel_type == id_CDC)
+        return cell_type.in(id_DDE, id_TDE, id_CDC, id_BGC, id_GBC);
+    else if (bel_type == id_XCDC)
+        return cell_type.in(id_XCDC);
+    else if (bel_type == id_FIFO)
+        return cell_type.in(id_FIFO);
+    else if (bel_type == id_XFIFO)
+        return cell_type.in(id_XHFIFO, id_XWFIFO);
+    else if (bel_type == id_WFG)
+        return cell_type.in(id_WFB, id_WFG);
+    else
+        return (bel_type == cell_type);
+}
+
+bool NgUltraImpl::getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,
+                                    std::vector<std::pair<CellInfo *, BelId>> &placement) const
+{
+    Loc prev = root_loc;
+    for (auto child : cluster->constr_children) {
+        Loc child_loc;
+        switch (child->constr_z) {
+        case PLACE_CY_CHAIN:
+            child_loc = getNextLocInCYChain(prev);
+            prev = child_loc;
+            break;
+        case PLACE_LUT_CHAIN:
+            child_loc = getNextLocInLUTChain(prev);
+            prev = child_loc;
+            break;
+        case PLACE_DFF_CHAIN:
+            child_loc = getNextLocInDFFChain(prev);
+            prev = child_loc;
+            break;
+        case PLACE_CY_FE1 ... PLACE_CY_FE4:
+            child_loc = getCYFE(root_loc, child->constr_z - PLACE_CY_FE1);
+            break;
+        case PLACE_XLUT_FE1 ... PLACE_XLUT_FE4:
+            child_loc = getXLUTFE(root_loc, child->constr_z - PLACE_XLUT_FE1);
+            break;
+        case PLACE_XRF_I1 ... PLACE_XRF_WEA:
+            child_loc = getXRFFE(root_loc, child->constr_z - PLACE_XRF_I1);
+            break;
+        case PLACE_CDC_AI1 ... PLACE_CDC_DDRSTI:
+            child_loc = getCDCFE(root_loc, child->constr_z - PLACE_CDC_AI1);
+            break;
+        case PLACE_FIFO_I1 ... PLACE_FIFO_REQ2:
+            child_loc = getFIFOFE(root_loc, child->constr_z - PLACE_FIFO_I1);
+            break;
+        case PLACE_DSP_CHAIN:
+            child_loc = getNextLocInDSPChain(this, prev);
+            prev = child_loc;
+            break;
+        default:
+            child_loc.x = root_loc.x + child->constr_x;
+            child_loc.y = root_loc.y + child->constr_y;
+            child_loc.z = child->constr_abs_z ? child->constr_z : (root_loc.z + child->constr_z);
+        }
+        BelId child_bel = ctx->getBelByLocation(child_loc);
+        if (child_bel == BelId() || !this->isValidBelForCellType(child->type, child_bel))
+            return false;
+        placement.emplace_back(child, child_bel);
+        if (!getChildPlacement(child, child_loc, placement))
+            return false;
+    }
+    return true;
+}
+
+bool NgUltraImpl::getClusterPlacement(ClusterId cluster, BelId root_bel,
+                                      std::vector<std::pair<CellInfo *, BelId>> &placement) const
+{
+    CellInfo *root_cell = get_cluster_root(ctx, cluster);
+    placement.clear();
+    NPNR_ASSERT(root_bel != BelId());
+    Loc root_loc = ctx->getBelLocation(root_bel);
+    if (root_cell->constr_abs_z) {
+        // Coerce root to absolute z constraint
+        root_loc.z = root_cell->constr_z;
+        root_bel = ctx->getBelByLocation(root_loc);
+        if (root_bel == BelId() || !this->isValidBelForCellType(root_cell->type, root_bel))
+            return false;
+    }
+    placement.emplace_back(root_cell, root_bel);
+    return getChildPlacement(root_cell, root_loc, placement);
+}
+
+BoundingBox NgUltraImpl::getRouteBoundingBox(WireId src, WireId dst) const
+{
+    if ((tile_type(src.tile) != TILE_EXTRA_FABRIC || tile_type(dst.tile) != TILE_EXTRA_FABRIC)) {
+        return {0, 0, ctx->getGridDimX(), ctx->getGridDimY()};
+    }
+    int x0, y0, x1, y1;
+    auto expand = [&](int x, int y) {
+        x0 = std::min(x0, x);
+        x1 = std::max(x1, x);
+        y0 = std::min(y0, y);
+        y1 = std::max(y1, y);
+    };
+    tile_xy(ctx->chip_info, src.tile, x0, y0);
+    x1 = x0;
+    y1 = y0;
+    int dx, dy;
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    expand(dx, dy);
+    // Reach 7 MESH above and below (3 left and 3 right of TILE/CGB)
+    return {(x0 & 0xfffc) - 3 * 4, // 3 MESH on left
+            (y0 & 0xfffc) - 4,     // row above
+            (x1 & 0xfffc) + 4 * 4, // MESH bellow and 3 right
+            (y1 & 0xfffc) + 8};    // current and row bellow
+}
+
+void NgUltraImpl::expandBoundingBox(BoundingBox &bb) const
+{
+    // Updated numbers for NG-ULTRA only
+    // x0 and y0 substract 1 TILE
+    // x1 and y1 adds 1 TILE (and of one added)
+    bb.x0 = std::max((bb.x0 & 0xfffc) - 4, 0);
+    bb.y0 = std::max((bb.y0 & 0xfffc) - 4, 0);
+    bb.x1 = std::min((bb.x1 & 0xfffc) + 8, ctx->getGridDimX());
+    bb.y1 = std::min((bb.y1 & 0xfffc) + 8, ctx->getGridDimY());
+}
+
+delay_t NgUltraImpl::estimateDelay(WireId src, WireId dst) const
+{
+    int sx, sy, dx, dy;
+    tile_xy(ctx->chip_info, src.tile, sx, sy);
+    tile_xy(ctx->chip_info, dst.tile, dx, dy);
+    if (sx == dx && sy == dy) {
+        // Same sub tile
+        return 50;
+    } else if (((sx & 0xfffc) == (dx & 0xfffc)) && ((sy & 0xfffc) == (dy & 0xfffc))) {
+        // Same "TILE"
+        return 200;
+    }
+    return 500 + 100 * (std::abs(dy - sy) / 4 + std::abs(dx - sx) / 4);
+}
+
+delay_t NgUltraImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
+{
+    Loc src_loc = ctx->getBelLocation(src_bel), dst_loc = ctx->getBelLocation(dst_bel);
+    if (src_loc.x == dst_loc.x && src_loc.y == dst_loc.y) {
+        // Same sub tile
+        return 50;
+    } else if (((src_loc.x & 0xfffc) == (dst_loc.x & 0xfffc)) && ((src_loc.y & 0xfffc) == (dst_loc.y & 0xfffc))) {
+        // Same "TILE"
+        return 200;
+    }
+    return 500 + 100 * (std::abs(dst_loc.y - src_loc.y) / 4 + std::abs(dst_loc.x - src_loc.x) / 4);
+}
+
+void NgUltraImpl::fixup_crossbars()
+{
+
+    auto is_crossbar_pip = [&](PipId pip) {
+        const auto &extra_data = *pip_extra_data(pip);
+        return (extra_data.name && extra_data.type == PipExtra::PIP_EXTRA_CROSSBAR);
+    };
+
+    auto crossbar_key = [&](PipId pip) {
+        const auto &extra_data = *pip_extra_data(pip);
+        return std::make_pair(pip.tile, IdString(extra_data.name));
+    };
+
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        dict<WireId, std::vector<PipId>> downstream;
+        // build a map of wires to sinks
+        for (auto &w : ni->wires) {
+            if (w.second.pip != PipId()) {
+                downstream[ctx->getPipSrcWire(w.second.pip)].push_back(w.second.pip);
+            }
+        }
+        // the original drivers of crossbars
+        dict<std::pair<int, IdString>, WireId> crossbar_entries;
+        // traverse from the start forwards so we always reach closer wires first in the route tree
+        WireId src = ctx->getNetinfoSourceWire(ni);
+        if (src == WireId() || !downstream.count(src)) {
+            continue;
+        }
+        std::queue<WireId> visit;
+        visit.push(src);
+        while (!visit.empty()) {
+            WireId cursor = visit.front();
+            visit.pop();
+            if (!downstream.count(cursor))
+                continue;
+            for (auto pip : downstream.at(cursor)) {
+                WireId dst = ctx->getPipDstWire(pip);
+                if (is_crossbar_pip(pip)) {
+                    auto key = crossbar_key(pip);
+                    if (!crossbar_entries.count(key)) {
+                        crossbar_entries[key] = ctx->getPipSrcWire(pip);
+                    } else {
+                        WireId xbar_src = crossbar_entries.at(key);
+                        if (ctx->getPipSrcWire(pip) != xbar_src) {
+                            // rewrite to be driven by original entry
+                            ctx->unbindPip(pip);
+                            PipId found_pip = PipId();
+                            for (auto search_pip : ctx->getPipsUphill(dst)) {
+                                if (ctx->getPipSrcWire(search_pip) == xbar_src) {
+                                    found_pip = search_pip;
+                                    break;
+                                }
+                            }
+                            NPNR_ASSERT(found_pip != PipId());
+                            // rebind
+                            // log_info(" replacing crossbar pip %s with %s on %s\n", ctx->nameOfPip(pip),
+                            // ctx->nameOfPip(found_pip), ctx->nameOf(ni));
+                            ctx->bindPip(found_pip, ni, STRENGTH_STRONG);
+                        }
+                    }
+                }
+                visit.push(dst);
+            }
+            downstream.erase(cursor);
+        }
+        // check everything was visited by our BFS tree traversal
+        NPNR_ASSERT(downstream.empty());
+    }
+}
+
+void NgUltraImpl::drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc)
+{
+    GraphicElement el;
+    el.type = GraphicElement::TYPE_BOX;
+    el.style = style;
+    switch (bel_type.index) {
+    case id_BEYOND_FE.index:
+        el.x1 = loc.x + 0.15 + (loc.z % 8) * 0.1;
+        el.x2 = el.x1 + 0.05;
+        el.y1 = loc.y + 0.9 - (loc.z / 8) * 0.15;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_XLUT.index:
+        el.x1 = loc.x + 0.15 + ((loc.z - BEL_XLUT_Z) % 8) * 0.1;
+        el.x2 = el.x1 + 0.05;
+        el.y1 = loc.y + 0.9 - 4 * 0.15;
+        el.y2 = el.y1 - 0.1;
+        g.push_back(el);
+        break;
+    case id_CY.index:
+        el.x1 = loc.x + 0.15 + ((loc.z - BEL_CY_Z) % 4) * 0.2;
+        el.x2 = el.x1 + 0.15;
+        el.y1 = loc.y + 0.9 - 4 * 0.15;
+        el.y2 = el.y1 - 0.1;
+        g.push_back(el);
+        break;
+    case id_RF.index:
+        el.x1 = loc.x + 0.15 + ((loc.z - BEL_RF_Z) % 2) * 0.6;
+        el.x2 = el.x1 + 0.15;
+        el.y1 = loc.y + 0.9 - 4 * 0.15;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_XRF.index:
+        el.x1 = loc.x + 0.15 + 0.2;
+        el.x2 = el.x1 + 0.35;
+        el.y1 = loc.y + 0.9 - 4 * 0.15;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_CDC.index:
+        el.x1 = loc.x + 0.15 + ((loc.z - BEL_CDC_Z) % 2) * 0.6;
+        el.x2 = el.x1 + 0.15;
+        el.y1 = loc.y + 0.9 - 4 * 0.15 - 0.1;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_XCDC.index:
+        el.x1 = loc.x + 0.15 + 0.2;
+        el.x2 = el.x1 + 0.35;
+        el.y1 = loc.y + 0.9 - 4 * 0.15 - 0.1;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_FIFO.index:
+        el.x1 = loc.x + 0.15 + ((loc.z - BEL_FIFO_Z) % 2) * 0.6;
+        el.x2 = el.x1 + 0.15;
+        el.y1 = loc.y + 0.9 - 4 * 0.15 - 0.2;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_XFIFO.index:
+        el.x1 = loc.x + 0.15 + 0.2;
+        el.x2 = el.x1 + 0.35;
+        el.y1 = loc.y + 0.9 - 4 * 0.15 - 0.2;
+        el.y2 = el.y1 - 0.05;
+        g.push_back(el);
+        break;
+    case id_IOTP.index:
+        el.x1 = loc.x + 0.15 + loc.z / 4 * 0.11;
+        el.x2 = el.x1 + 0.06;
+        if (loc.y == 3) { // bottom
+            el.y1 = 0.1;
+            el.y2 = el.y1 + 0.2;
+        } else { // top
+            el.y1 = loc.y + 0.9;
+            el.y2 = el.y1 - 0.2;
+        }
+        g.push_back(el);
+        break;
+    case id_IOM.index:
+        el.x1 = loc.x + 0.15;
+        el.x2 = el.x1 + 33 * 0.11 + 0.06;
+        if (loc.y == 3) { // bottom
+            el.y1 = 0.4;
+            el.y2 = el.y1 + 0.2;
+        } else { // top
+            el.y1 = loc.y + 0.6;
+            el.y2 = el.y1 - 0.2;
+        }
+        g.push_back(el);
+        break;
+    case id_DDFR.index:
+        el.x1 = loc.x + 0.15 + loc.z / 4 * 0.11 + (loc.z % 4 - 1) * 0.02;
+        el.x2 = el.x1 + 0.015;
+        if (loc.y == 3) { // bottom
+            el.y1 = 0.7;
+            el.y2 = el.y1 + 0.1;
+        } else { // top
+            el.y1 = loc.y + 0.3;
+            el.y2 = el.y1 - 0.1;
+        }
+        g.push_back(el);
+        break;
+    case id_IOP.index:
+        if (loc.x == ctx->getGridDimX() - 4) { // right
+            el.x1 = ctx->getGridDimX() - 0.1;
+            el.x2 = el.x1 - 0.2;
+        } else { // left
+            el.x1 = loc.x + 0.1;
+            el.x2 = el.x1 + 0.2;
+        }
+        el.y1 = loc.y + 0.85 - loc.z / 4 * 0.11;
+        el.y2 = el.y1 - 0.06;
+        g.push_back(el);
+        break;
+    case id_DFR.index:
+        if (loc.x == ctx->getGridDimX() - 4) { // right
+            el.x1 = ctx->getGridDimX() - 0.4;
+            el.x2 = el.x1 - 0.1;
+        } else { // left
+            el.x1 = loc.x + 0.4;
+            el.x2 = el.x1 + 0.1;
+        }
+        el.y1 = loc.y + 0.85 - loc.z / 4 * 0.11 - (loc.z % 4 - 1) * 0.02 - 0.02;
+        el.y2 = el.y1 + 0.015;
+        g.push_back(el);
+        break;
+    case id_PLL.index:
+        el.x1 = loc.x + 0.1;
+        el.x2 = el.x1 + 0.8;
+        el.y1 = loc.y + 0.9;
+        el.y2 = el.y1 - 0.8;
+        g.push_back(el);
+        break;
+    case id_WFG.index:
+        el.x1 = loc.x + 1.1;
+        el.x2 = el.x1 + 0.8;
+        el.y1 = loc.y + 0.95 - (loc.z - 1) * 0.25 + 3;
+        el.y2 = el.y1 - 0.2;
+        g.push_back(el);
+        break;
+    case id_RAM.index:
+        el.x1 = loc.x + 0.2;
+        el.x2 = el.x1 + 3.6;
+        el.y1 = loc.y + 0.8;
+        el.y2 = el.y1 - 1.6;
+        g.push_back(el);
+        break;
+    case id_DSP.index:
+        el.x1 = (loc.x - 1) + 0.2;
+        el.x2 = el.x1 + 1.6;
+        el.y1 = loc.y + 0.8;
+        el.y2 = el.y1 - 1.6;
+        g.push_back(el);
+        break;
+    case id_GCK.index: {
+        int lobe = loc.z / 20;
+        el.x1 = (47 + (lobe % 2) * 3) * 4 + 0.1;
+        el.x2 = el.x1 + 0.8;
+        el.y1 = (ctx->getGridDimY() - 1 - (7 * 4 + 12 * 4 * (lobe >> 1))) + 0.95 - (loc.z % 20) * 0.25;
+        el.y2 = el.y1 - 0.2;
+        g.push_back(el);
+    } break;
+    default:
+        break;
+    }
+}
+
+struct NgUltraArch : HimbaechelArch
+{
+    NgUltraArch() : HimbaechelArch("ng-ultra") {};
+    bool match_device(const std::string &device) override { return device == "NG-ULTRA"; }
+    std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
+    {
+        return std::make_unique<NgUltraImpl>();
+    }
+} ngUltraArch;
+
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.h b/himbaechel/uarch/ng-ultra/ng_ultra.h
new file mode 100644
index 0000000000..0ced37b2af
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/ng_ultra.h
@@ -0,0 +1,126 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef HIMBAECHEL_NG_ULTRA_H
+#define HIMBAECHEL_NG_ULTRA_H
+#include <deque>
+
+#include "extra_data.h"
+#include "himbaechel_api.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+#include "himbaechel_helpers.h"
+
+#ifdef GTEST_API_
+#define TESTABLE_PRIVATE public
+#else
+#define TESTABLE_PRIVATE private
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct NgUltraImpl : HimbaechelAPI
+{
+    ~NgUltraImpl();
+    void init_database(Arch *arch) override;
+
+    void init(Context *ctx) override;
+
+    bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
+    IdString getBelBucketForCellType(IdString cell_type) const override;
+    bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
+    BelBucketId getBelBucketForBel(BelId bel) const override;
+
+    // Flow management
+    void pack() override;
+    void postPlace() override;
+    void postRoute() override;
+
+    void configurePlacerHeap(PlacerHeapCfg &cfg) override;
+
+    bool getClusterPlacement(ClusterId cluster, BelId root_bel,
+                             std::vector<std::pair<CellInfo *, BelId>> &placement) const override;
+    bool getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,
+                           std::vector<std::pair<CellInfo *, BelId>> &placement) const;
+
+    BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
+    delay_t estimateDelay(WireId src, WireId dst) const override;
+    delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
+
+    bool checkPipAvail(PipId pip) const override { return blocked_pips.count(pip) == 0; }
+    bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override { return checkPipAvail(pip); };
+
+    void expandBoundingBox(BoundingBox &bb) const override;
+
+    void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override;
+
+  public:
+    int tile_lobe(int tile) const;
+    TileTypeExtra tile_type(int tile) const;
+    IdString tile_name_id(int tile) const;
+    std::string tile_name(int tile) const;
+
+    const dict<IdString, pool<IdString>> &get_fabric_lowskew_sinks();
+    bool is_fabric_lowskew_sink(const PortRef &ref);
+    bool is_ring_clock_sink(const PortRef &ref);
+    bool is_ring_over_tile_clock_sink(const PortRef &ref);
+    bool is_tube_clock_sink(const PortRef &ref);
+
+    bool is_ring_clock_source(const PortRef &ref);
+    bool is_tube_clock_source(const PortRef &ref);
+
+    const NGUltraPipExtraDataPOD *pip_extra_data(PipId pip) const;
+    const NGUltraBelExtraDataPOD *bel_extra_data(BelId bel) const;
+
+    dict<IdString, BelId> iom_bels;
+    dict<std::string, std::string> bank_voltage;
+    dict<BelId, IdString> global_capable_bels;
+    dict<std::string, BelId> locations;
+    dict<std::string, Loc> tile_locations;
+    dict<int, std::vector<GckConfig>> gck_per_lobe;
+
+    pool<PipId> blocked_pips;
+    dict<IdString, std::pair<IdString, IdString>> bank_to_ckg;
+    dict<BelId, IdString> unused_wfg;
+    dict<BelId, IdString> unused_pll;
+    dict<BelId, BelId> dsp_cascade;
+
+    /* clang-format off */
+TESTABLE_PRIVATE:
+    void write_bitstream_json(const std::string &filename);
+    /* clang-format on */
+    void parse_csv(const std::string &filename);
+    void remove_constants();
+    bool update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip);
+    bool update_bff_to_scc(CellInfo *cell, BelId bel, PipId dst_pip);
+    void disable_beyond_fe_s_output(BelId bel);
+
+    void fixup_crossbars();
+
+    // Misc utility functions
+    bool get_mux_data(BelId bel, IdString port, uint8_t *value);
+    bool get_mux_data(WireId wire, uint8_t *value);
+
+    const NGUltraTileInstExtraDataPOD *tile_extra_data(int tile) const;
+};
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc
new file mode 100644
index 0000000000..182be6b2c0
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/pack.cc
@@ -0,0 +1,2738 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "pack.h"
+#include <algorithm>
+#include <boost/algorithm/string.hpp>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "extra_data.h"
+#include "log.h"
+#include "nextpnr.h"
+
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// Return true if a cell is a LUT
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_NX_LUT; }
+
+// Return true if a cell is a flipflop
+inline bool is_dff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type.in(id_NX_DFF, id_NX_BFF); }
+
+// Return true if a cell is a FE
+inline bool is_fe(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_BEYOND_FE; }
+
+// Return true if a cell is a DFR
+inline bool is_dfr(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_NX_DFR; }
+
+// Return true if a cell is a DDFR
+inline bool is_ddfr(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_NX_DDFR_U; }
+
+// Return true if a cell is a WFG/WFB
+inline bool is_wfg(const BaseCtx *ctx, const CellInfo *cell) { return cell->type.in(id_WFB, id_WFG); }
+
+// Return true if a cell is a GCK
+inline bool is_gck(const BaseCtx *ctx, const CellInfo *cell) { return cell->type.in(id_GCK, id_NX_GCK_U); }
+
+// Process the contents of packed_cells
+void NgUltraPacker::flush_cells()
+{
+    for (auto pcell : packed_cells) {
+        for (auto &port : ctx->cells[pcell]->ports) {
+            ctx->cells[pcell]->disconnectPort(port.first);
+        }
+        ctx->cells.erase(pcell);
+    }
+    packed_cells.clear();
+}
+
+void NgUltraPacker::pack_constants(void)
+{
+    log_info("Packing constants..\n");
+    // Replace constants with LUTs
+    const dict<IdString, Property> vcc_params = {
+            {id_lut_table, Property(0xFFFF, 16)}, {id_lut_used, Property(1, 1)}, {id_dff_used, Property(1, 1)}};
+    const dict<IdString, Property> gnd_params = {
+            {id_lut_table, Property(0x0000, 16)}, {id_lut_used, Property(1, 1)}, {id_dff_used, Property(1, 1)}};
+
+    h.replace_constants(CellTypePort(id_BEYOND_FE, id_LO), CellTypePort(id_BEYOND_FE, id_LO), vcc_params, gnd_params);
+}
+
+void NgUltraImpl::remove_constants()
+{
+    log_info("Removing constants..\n");
+    auto fnd_cell = ctx->cells.find(ctx->id("$PACKER_VCC_DRV"));
+    if (fnd_cell != ctx->cells.end()) {
+        auto fnd_net = ctx->nets.find(ctx->id("$PACKER_VCC"));
+        if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
+            BelId bel = (*fnd_cell).second.get()->bel;
+            if (bel != BelId())
+                ctx->unbindBel(bel);
+            ctx->cells.erase(fnd_cell);
+            ctx->nets.erase(fnd_net);
+            log_info("    Removed unused VCC cell\n");
+        }
+    }
+    fnd_cell = ctx->cells.find(ctx->id("$PACKER_GND_DRV"));
+    if (fnd_cell != ctx->cells.end()) {
+        auto fnd_net = ctx->nets.find(ctx->id("$PACKER_GND"));
+        if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
+            BelId bel = (*fnd_cell).second.get()->bel;
+            if (bel != BelId())
+                ctx->unbindBel(bel);
+            ctx->cells.erase(fnd_cell);
+            ctx->nets.erase(fnd_net);
+            log_info("    Removed unused GND cell\n");
+        }
+    }
+}
+
+void NgUltraPacker::update_lut_init()
+{
+    log_info("Update LUT init...\n");
+
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_LUT))
+            continue;
+        set_lut_input_if_constant(&ci, id_I1);
+        set_lut_input_if_constant(&ci, id_I2);
+        set_lut_input_if_constant(&ci, id_I3);
+        set_lut_input_if_constant(&ci, id_I4);
+        NetInfo *o = ci.getPort(id_O);
+        if (!o) {
+            // Remove those that do not output any value
+            log_warning("Removing LUT '%s' since output is not connected.\n", ci.name.c_str(ctx));
+            packed_cells.insert(ci.name);
+        }
+    }
+    flush_cells();
+}
+
+void NgUltraPacker::dff_rewrite(CellInfo *cell)
+{
+    if (int_or_default(cell->params, id_dff_init, 0) == 0) {
+        // Reset not used
+        cell->disconnectPort(id_R);
+    } else {
+        // Reset used
+        NetInfo *net = cell->getPort(id_R);
+        if (net) {
+            if (net->name == ctx->id("$PACKER_GND")) {
+                log_warning("Removing reset on '%s' since it is always 0.\n", cell->name.c_str(ctx));
+                cell->setParam(id_dff_init, Property(0, 1));
+                cell->disconnectPort(id_R);
+            } else if (net->name == ctx->id("$PACKER_VCC")) {
+                log_error("Invalid DFF configuration, reset on '%s' is always 1.\n", cell->name.c_str(ctx));
+            }
+        }
+    }
+
+    if (int_or_default(cell->params, id_dff_load, 0) == 0) {
+        // Load not used
+        cell->disconnectPort(id_L);
+    } else {
+        // Load used
+        NetInfo *net = cell->getPort(id_L);
+        if (net) {
+            if (net->name == ctx->id("$PACKER_VCC")) {
+                log_warning("Removing load enable on '%s' since it is always 1.\n", cell->name.c_str(ctx));
+                cell->setParam(id_dff_load, Property(0, 0));
+                cell->disconnectPort(id_L);
+            } else if (net->name == ctx->id("$PACKER_GND")) {
+                log_warning("Converting to self loop, since load enable on '%s' is always 0.\n", cell->name.c_str(ctx));
+                cell->setParam(id_dff_load, Property(0, 0));
+                cell->disconnectPort(id_L);
+                cell->disconnectPort(id_I);
+                NetInfo *out = cell->getPort(id_O);
+                cell->connectPort(id_I, out);
+            }
+        }
+    }
+}
+
+void NgUltraPacker::ddfr_rewrite(CellInfo *cell)
+{
+    // Reversed logic in comparison to DFF
+    if (int_or_default(cell->params, id_dff_load, 0) == 1) {
+        // Load not used
+        cell->disconnectPort(id_L);
+    } else {
+        // Load used
+        NetInfo *net = cell->getPort(id_L);
+        if (net) {
+            if (net->name == ctx->id("$PACKER_VCC")) {
+                log_warning("Removing load enable on '%s' since it is always 1.\n", cell->name.c_str(ctx));
+                cell->setParam(id_dff_load, Property(0, 0));
+                cell->disconnectPort(id_L);
+            }
+        }
+    }
+}
+
+void NgUltraPacker::update_dffs()
+{
+    log_info("Update DFFs...\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_DFF))
+            continue;
+        dff_rewrite(&ci);
+    }
+}
+
+int NgUltraPacker::make_init_with_const_input(int init, int input, bool value)
+{
+    int new_init = 0;
+    for (int i = 0; i < 16; i++) {
+        if (((i >> input) & 0x1) != value) {
+            int other_i = (i & (~(1 << input))) | (value << input);
+            if ((init >> other_i) & 0x1)
+                new_init |= (1 << i);
+        } else {
+            if ((init >> i) & 0x1)
+                new_init |= (1 << i);
+        }
+    }
+    return new_init;
+}
+
+void NgUltraPacker::set_lut_input_if_constant(CellInfo *cell, IdString input)
+{
+    NetInfo *net = cell->getPort(input);
+    if (!net)
+        return;
+    if (!net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")))
+        return;
+    bool value = net->name == ctx->id("$PACKER_VCC");
+    int index = std::string("1234").find(input.str(ctx));
+    int init = int_or_default(cell->params, id_lut_table);
+    int new_init = make_init_with_const_input(init, index, value);
+    cell->params[id_lut_table] = Property(new_init, 16);
+    cell->disconnectPort(input);
+}
+
+void NgUltraPacker::disconnect_if_gnd(CellInfo *cell, IdString input)
+{
+    NetInfo *net = cell->getPort(input);
+    if (!net)
+        return;
+    if (net->name.in(ctx->id("$PACKER_GND"))) {
+        cell->disconnectPort(input);
+    }
+}
+
+void NgUltraPacker::connect_gnd_if_unconnected(CellInfo *cell, IdString input, bool warn = true)
+{
+    NetInfo *net = cell->getPort(input);
+    if (net)
+        return;
+    if (!cell->ports.count(input))
+        cell->addInput(input);
+    auto fnd_net = ctx->nets.find(ctx->id("$PACKER_GND"));
+    if (fnd_net != ctx->nets.end()) {
+        cell->connectPort(input, fnd_net->second.get());
+        if (warn)
+            log_warning("Connected GND to mandatory port '%s' of cell '%s'(%s).\n", input.c_str(ctx),
+                        cell->name.c_str(ctx), cell->type.c_str(ctx));
+    }
+}
+
+void NgUltraPacker::lut_to_fe(CellInfo *lut, CellInfo *fe, bool no_dff, Property lut_table)
+{
+    fe->params[id_lut_table] = lut_table;
+    fe->params[id_lut_used] = Property(1, 1);
+    lut->movePortTo(id_I1, fe, id_I1);
+    lut->movePortTo(id_I2, fe, id_I2);
+    lut->movePortTo(id_I3, fe, id_I3);
+    lut->movePortTo(id_I4, fe, id_I4);
+    lut->movePortTo(id_O, fe, id_LO);
+    if (no_dff) {
+        fe->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
+    }
+}
+
+void NgUltraPacker::dff_to_fe(CellInfo *dff, CellInfo *fe, bool pass_thru_lut)
+{
+    if (pass_thru_lut) {
+        NetInfo *net = dff->getPort(id_I);
+        if (net && net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
+            // special case if driver is constant
+            fe->params[id_lut_table] = Property((net->name == ctx->id("$PACKER_GND")) ? 0x0000 : 0xffff, 16);
+            dff->disconnectPort(id_I);
+        } else {
+            // otherwise just passthru
+            fe->params[id_lut_table] = Property(0xaaaa, 16);
+            dff->movePortTo(id_I, fe, id_I1);
+        }
+        fe->params[id_lut_used] = Property(1, 1);
+    } else
+        dff->movePortTo(id_I, fe, id_DI);
+    fe->params[id_dff_used] = Property(1, 1);
+    dff->movePortTo(id_O, fe, id_DO);
+    if (dff->type == id_NX_BFF) {
+        fe->setParam(id_type, Property("BFF"));
+    } else {
+        fe->setParam(id_type, Property("DFF"));
+
+        dff->movePortTo(id_R, fe, id_R);
+        dff->movePortTo(id_CK, fe, id_CK);
+        dff->movePortTo(id_L, fe, id_L);
+
+        if (dff->params.count(id_dff_ctxt))
+            fe->setParam(id_dff_ctxt, dff->params[id_dff_ctxt]);
+        if (dff->params.count(id_dff_edge))
+            fe->setParam(id_dff_edge, dff->params[id_dff_edge]);
+        if (dff->params.count(id_dff_init))
+            fe->setParam(id_dff_init, dff->params[id_dff_init]);
+        if (dff->params.count(id_dff_load))
+            fe->setParam(id_dff_load, dff->params[id_dff_load]);
+        if (dff->params.count(id_dff_sync))
+            fe->setParam(id_dff_sync, dff->params[id_dff_sync]);
+        if (dff->params.count(id_dff_type))
+            fe->setParam(id_dff_type, dff->params[id_dff_type]);
+    }
+    if (pass_thru_lut) {
+        NetInfo *new_out = ctx->createNet(ctx->idf("%s$LO", dff->name.c_str(ctx)));
+        fe->connectPort(id_LO, new_out);
+        fe->connectPort(id_DI, new_out);
+    }
+}
+
+void NgUltraPacker::bind_attr_loc(CellInfo *cell, dict<IdString, Property> *attrs)
+{
+    if (attrs->count(id_LOC)) {
+        std::string name = attrs->at(id_LOC).as_string();
+        if (boost::starts_with(name, "TILE[")) {
+            boost::replace_all(name, ".DFF", ".FE");
+            boost::replace_all(name, ".LUT", ".FE");
+        }
+        if (!uarch->locations.count(name)) {
+            log_error("Unable to find location %s\n", name.c_str());
+        }
+        BelId bel = uarch->locations.at(name);
+        ctx->bindBel(bel, cell, PlaceStrength::STRENGTH_LOCKED);
+    }
+}
+
+void NgUltraPacker::pack_xluts(void)
+{
+    log_info("Pack XLUTs...\n");
+    int xlut_used = 0, lut_only = 0, lut_and_ff = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_LUT))
+            continue;
+        if (!ci.params.count(id_lut_table))
+            log_error("Cell '%s' missing lut_table\n", ci.name.c_str(ctx));
+
+        if (ci.cluster != ClusterId())
+            continue;
+        CellInfo *lut[4];
+        int inputs_used = 0;
+        int dff_parts_used = 0;
+        for (int i = 0; i < 4; i++) {
+            NetInfo *net = ci.getPort(ctx->idf("I%d", i + 1));
+            if (!net)
+                continue;
+            lut[i] = net_driven_by(ctx, net, is_lut, id_O);
+            if (lut[i] == cell.second.get())
+                continue;
+            if (lut[i]) {
+                if (net->users.entries() > 1)
+                    dff_parts_used++;
+                inputs_used++;
+            }
+        }
+        if (inputs_used != 4)
+            continue;
+        // we must have a route out for xlut output signal
+        if (dff_parts_used > 3)
+            continue;
+        ci.type = id_XLUT;
+        bind_attr_loc(&ci, &ci.attrs);
+        ci.cluster = ci.name;
+        xlut_used++;
+
+        NetInfo *o = ci.getPort(id_O);
+        CellInfo *orig_dff = o ? net_only_drives(ctx, o, is_dff, id_I, true) : nullptr;
+
+        for (int i = 0; i < 4; i++) {
+            ci.constr_children.push_back(lut[i]);
+            lut[i]->cluster = ci.cluster;
+            lut[i]->type = id_BEYOND_FE;
+            lut[i]->constr_z = PLACE_XLUT_FE1 + i;
+            lut[i]->renamePort(id_O, id_LO);
+            lut[i]->params[id_lut_used] = Property(1, 1);
+            NetInfo *net = lut[i]->getPort(id_LO);
+            if (net->users.entries() != 2) {
+                if (orig_dff && net->users.entries() == 1) {
+                    // we place DFF on XLUT output on unused DFF
+                    dff_to_fe(orig_dff, lut[i], false);
+                    packed_cells.insert(orig_dff->name);
+                    lut_and_ff++;
+                    orig_dff = nullptr;
+                } else {
+                    lut[i]->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
+                    lut_only++;
+                }
+            } else {
+                CellInfo *dff = (*net->users.begin()).cell;
+                if (dff->type != id_NX_DFF)
+                    dff = (*(++net->users.begin())).cell;
+                if (dff->type == id_NX_DFF) {
+                    dff_to_fe(dff, lut[i], false);
+                    packed_cells.insert(dff->name);
+                    lut_and_ff++;
+                } else {
+                    lut[i]->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
+                    lut_only++;
+                }
+            }
+        }
+    }
+    if (xlut_used)
+        log_info("    %6d XLUTs used\n", xlut_used);
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_dff_chains(void)
+{
+    log_info("Pack DFF chains...\n");
+    std::vector<std::pair<CellInfo *, std::vector<CellInfo *>>> dff_chain_start;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_DFF))
+            continue;
+        NetInfo *inp = ci.getPort(id_I);
+        if (!inp || (inp->driver.cell && inp->driver.cell->type.in(id_NX_DFF)))
+            continue;
+        int cnt = 0;
+        CellInfo *dff = &ci;
+        std::vector<CellInfo *> chain;
+        CellInfo *start_dff = &ci;
+        while (1) {
+            NetInfo *o = dff->getPort(id_O);
+            if (!o)
+                break;
+            if (o->users.entries() != 1)
+                break;
+            dff = (*o->users.begin()).cell;
+            if (dff->type == id_NX_DFF && (*o->users.begin()).port == id_I) {
+                if (cnt == 95) { // note that start_dff is also part of chain
+                    dff_chain_start.push_back(make_pair(start_dff, chain));
+                    cnt = 0;
+                    start_dff = dff;
+                    chain.clear();
+                } else {
+                    chain.push_back(dff);
+                    cnt++;
+                }
+            } else
+                break;
+        }
+        if (cnt)
+            dff_chain_start.push_back(make_pair(start_dff, chain));
+    }
+
+    int dff_only = 0, lut_and_ff = 0;
+    for (auto ch : dff_chain_start) {
+        CellInfo *dff = ch.first;
+        CellInfo *root = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", dff->name.c_str(ctx)));
+        root->cluster = root->name;
+        NetInfo *net = dff->getPort(id_I);
+        if (net && net->driver.cell->type == id_NX_LUT && net->users.entries() == 1) {
+            CellInfo *lut = net->driver.cell;
+            if (!lut->params.count(id_lut_table))
+                log_error("Cell '%s' missing lut_table\n", lut->name.c_str(ctx));
+            lut_to_fe(lut, root, false, lut->params[id_lut_table]);
+            packed_cells.insert(lut->name);
+            dff_to_fe(dff, root, false);
+            packed_cells.insert(dff->name);
+            ++lut_and_ff;
+        } else {
+            dff_to_fe(dff, root, true);
+            packed_cells.insert(dff->name);
+            ++dff_only;
+        }
+        for (auto dff : ch.second) {
+            CellInfo *new_cell = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", dff->name.c_str(ctx)));
+            dff_to_fe(dff, new_cell, true);
+            ++dff_only;
+            root->constr_children.push_back(new_cell);
+            new_cell->cluster = root->cluster;
+            new_cell->constr_z = PLACE_DFF_CHAIN;
+            packed_cells.insert(dff->name);
+        }
+    }
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_lut_multi_dffs(void)
+{
+    log_info("Pack LUT-multi DFFs...\n");
+
+    int dff_only = 0, lut_and_ff = 0, bff_only = 0;
+    ;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_LUT))
+            continue;
+        if (!ci.params.count(id_lut_table))
+            log_error("Cell '%s' missing lut_table\n", ci.name.c_str(ctx));
+
+        NetInfo *o = ci.getPort(id_O);
+        if (o) {
+            if (o->users.entries() < 2)
+                continue;
+
+            int cnt = 0;
+            for (auto u : o->users) {
+                if (u.cell->type == id_NX_DFF && u.cell->getPort(id_I) == o)
+                    cnt++;
+            }
+            if (cnt < 2)
+                continue;
+
+            CellInfo *root = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", ci.name.c_str(ctx)));
+            packed_cells.insert(ci.name);
+            bind_attr_loc(root, &ci.attrs);
+            lut_to_fe(&ci, root, false, ci.params[id_lut_table]);
+            root->cluster = root->name;
+
+            int max_use = (cnt == 4 && o->users.entries() == 4) ? 4 : 3;
+            bool use_bff = max_use != 4 && cnt >= 4;
+            int i = 0;
+            std::vector<PortRef> users;
+            for (auto u : o->users) {
+                if (u.cell->type == id_NX_DFF && u.cell->getPort(id_I) == o) {
+                    if (i == 0) {
+                        packed_cells.insert(u.cell->name);
+                        dff_to_fe(u.cell, root, false);
+                        ++lut_and_ff;
+                    } else if (i < max_use) {
+                        packed_cells.insert(u.cell->name);
+                        CellInfo *new_cell = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", u.cell->name.c_str(ctx)));
+                        dff_to_fe(u.cell, new_cell, false);
+                        root->constr_children.push_back(new_cell);
+                        new_cell->cluster = root->cluster;
+                        new_cell->constr_z = PLACE_LUT_CHAIN;
+                        ++dff_only;
+                    } else {
+                        use_bff = true;
+                        users.push_back(u);
+                        u.cell->disconnectPort(u.port);
+                    }
+                    i++;
+                } else {
+                    use_bff = true;
+                    users.push_back(u);
+                    u.cell->disconnectPort(u.port);
+                }
+            }
+            if (use_bff) {
+                CellInfo *new_cell = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$bff", ci.name.c_str(ctx)));
+                new_cell->params[id_dff_used] = Property(1, 1);
+                new_cell->setParam(id_type, Property("BFF"));
+                new_cell->connectPort(id_DI, o);
+                root->constr_children.push_back(new_cell);
+                new_cell->cluster = root->cluster;
+                new_cell->constr_z = PLACE_LUT_CHAIN;
+                bff_only++;
+                NetInfo *new_out = ctx->createNet(ctx->idf("%s$new", o->name.c_str(ctx)));
+                new_cell->connectPort(id_DO, new_out);
+                for (auto &user : users) {
+                    user.cell->connectPort(user.port, new_out);
+                }
+            }
+        }
+    }
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    if (bff_only)
+        log_info("    %6d FEs used as BFF only\n", bff_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_lut_dffs(void)
+{
+    log_info("Pack LUT-DFFs...\n");
+
+    int lut_only = 0, lut_and_ff = 0;
+    std::vector<CellInfo *> lut_list;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_LUT))
+            continue;
+        if (!ci.params.count(id_lut_table))
+            log_error("Cell '%s' missing lut_table\n", ci.name.c_str(ctx));
+        packed_cells.insert(ci.name);
+        lut_list.push_back(&ci);
+    }
+    for (auto ci : lut_list) {
+        CellInfo *packed = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", ci->name.c_str(ctx)));
+        bind_attr_loc(packed, &ci->attrs);
+
+        bool packed_dff = false;
+        NetInfo *o = ci->getPort(id_O);
+        if (o) {
+            CellInfo *dff = net_only_drives(ctx, o, is_dff, id_I, true);
+            if (dff) {
+                if (ctx->verbose)
+                    log_info("found attached dff %s\n", dff->name.c_str(ctx));
+                lut_to_fe(ci, packed, false, ci->params[id_lut_table]);
+                dff_to_fe(dff, packed, false);
+                ++lut_and_ff;
+                packed_cells.insert(dff->name);
+                if (ctx->verbose)
+                    log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
+                packed_dff = true;
+            }
+        }
+        if (!packed_dff) {
+            lut_to_fe(ci, packed, true, ci->params[id_lut_table]);
+            ++lut_only;
+        }
+    }
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_dffs(void)
+{
+    int dff_only = 0;
+    std::vector<CellInfo *> dff_list;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_DFF, id_NX_BFF))
+            continue;
+        packed_cells.insert(ci.name);
+        dff_list.push_back(&ci);
+    }
+    for (auto ci : dff_list) {
+        CellInfo *packed = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$fe", ci->name.c_str(ctx)));
+        dff_to_fe(ci, packed, true);
+        bind_attr_loc(packed, &ci->attrs);
+        ++dff_only;
+    }
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_iobs(void)
+{
+    log_info("Pack IOBs...\n");
+    // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+    for (auto &port : ctx->ports) {
+        if (!ctx->cells.count(port.first))
+            log_error("Port '%s' doesn't seem to have a corresponding top level IO\n", ctx->nameOf(port.first));
+        CellInfo *ci = ctx->cells.at(port.first).get();
+
+        PortRef top_port;
+        top_port.cell = nullptr;
+        bool is_npnr_iob = false;
+
+        if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
+            // Might have an input buffer connected to it
+            is_npnr_iob = true;
+            NetInfo *o = ci->getPort(id_O);
+            if (o == nullptr)
+                ;
+            else if (o->users.entries() > 1)
+                log_error("Top level pin '%s' has multiple input buffers\n", ctx->nameOf(port.first));
+            else if (o->users.entries() == 1)
+                top_port = *o->users.begin();
+        }
+        if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
+            // Might have an output buffer connected to it
+            is_npnr_iob = true;
+            NetInfo *i = ci->getPort(id_I);
+            if (i != nullptr && i->driver.cell != nullptr) {
+                if (top_port.cell != nullptr)
+                    log_error("Top level pin '%s' has multiple input/output buffers\n", ctx->nameOf(port.first));
+                top_port = i->driver;
+            }
+            // Edge case of a bidirectional buffer driving an output pin
+            if (i->users.entries() > 2) {
+                log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
+            } else if (i->users.entries() == 2) {
+                if (top_port.cell != nullptr)
+                    log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
+                for (auto &usr : i->users) {
+                    if (usr.cell->type == ctx->id("$nextpnr_obuf") || usr.cell->type == ctx->id("$nextpnr_iobuf"))
+                        continue;
+                    top_port = usr;
+                    break;
+                }
+            }
+        }
+        if (!is_npnr_iob)
+            log_error("Port '%s' doesn't seem to have a corresponding top level IO (internal cell type mismatch)\n",
+                      ctx->nameOf(port.first));
+
+        if (top_port.cell == nullptr) {
+            log_info("Trimming port '%s' as it is unused.\n", ctx->nameOf(port.first));
+        } else {
+            // Copy attributes to real IO buffer
+            for (auto &attrs : ci->attrs)
+                top_port.cell->attrs[attrs.first] = attrs.second;
+            for (auto &params : ci->params)
+                top_port.cell->params[params.first] = params.second;
+
+            // Make sure that top level net is set correctly
+            port.second.net = top_port.cell->ports.at(top_port.port).net;
+        }
+        // Now remove the nextpnr-inserted buffer
+        ci->disconnectPort(id_I);
+        ci->disconnectPort(id_O);
+        ctx->cells.erase(port.first);
+    }
+    std::vector<CellInfo *> to_update;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_IOB_I, id_NX_IOB_O, id_NX_IOB))
+            continue;
+        if (ci.params.count(id_location) == 0) {
+            log_error("Unconstrained IO:%s\n", ctx->nameOf(&ci));
+        }
+        std::string loc = ci.params.at(id_location).to_string();
+        BelId bel = ctx->get_package_pin_bel(ctx->id(loc));
+        if (bel == BelId())
+            log_error("Unable to constrain IO '%s', device does not have a pin named '%s'\n", ci.name.c_str(ctx),
+                      loc.c_str());
+        log_info("    Constraining '%s' to pad '%s'\n", ci.name.c_str(ctx), loc.c_str());
+        if (!ctx->checkBelAvail(bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
+                      ctx->nameOf(ctx->getBoundBelCell(bel)));
+        }
+
+        IdString new_type = id_IOP;
+        disconnect_if_gnd(&ci, id_T);
+        if (ci.getPort(id_T)) {
+            // In case T input is used must use different types
+            new_type = id_IOTP;
+            if (ci.type == id_NX_IOB_O)
+                new_type = id_OTP;
+            if (ci.type == id_NX_IOB_I)
+                new_type = id_ITP;
+        } else {
+            if (ci.type == id_NX_IOB_O)
+                new_type = id_OP;
+            if (ci.type == id_NX_IOB_I)
+                new_type = id_IP;
+        }
+        ci.type = new_type;
+        ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+        if (!ctx->isValidBelForCellType(new_type, bel))
+            log_error("Invalid type of IO for specified location %s %s.\n", new_type.c_str(ctx),
+                      ctx->getBelType(bel).c_str(ctx));
+        to_update.push_back(&ci);
+    }
+    int bfr_added = 0;
+    int dfr_added = 0;
+    int ddfr_added = 0;
+    for (auto cell : to_update) {
+        NetInfo *c_net = cell->getPort(id_C);
+        if (!c_net)
+            log_error("C input of IO primitive %s must be connected.\n", cell->name.c_str(ctx));
+        if (c_net->name == ctx->id("$PACKER_GND") && !cell->getPort(id_O)) {
+            log_warning("O port of IO primitive %s must be connected. Removing cell.\n", cell->name.c_str(ctx));
+            packed_cells.emplace(cell->name);
+            continue;
+        }
+        if (c_net->name == ctx->id("$PACKER_VCC") && !cell->getPort(id_I)) {
+            log_warning("I port of IO primitive %s must be connected. Removing cell.\n", cell->name.c_str(ctx));
+            packed_cells.emplace(cell->name);
+            continue;
+        }
+        if (!cell->getPort(id_I) && !cell->getPort(id_O)) {
+            log_warning("I or O port of IO primitive %s must be connected. Removing cell.\n", cell->name.c_str(ctx));
+            packed_cells.emplace(cell->name);
+            continue;
+        }
+
+        {
+            CellInfo *iod = net_driven_by(ctx, c_net, is_dfr, id_O);
+            if (iod && c_net->users.entries() != 1)
+                log_error("NX_DFR '%s' can only directly drive IOB.\n", iod->name.c_str(ctx));
+            if (!iod) {
+                iod = net_driven_by(ctx, c_net, is_ddfr, id_O);
+                if (iod && c_net->users.entries() != 1)
+                    log_error("NX_DDFR '%s' can only directly drive IOB.\n", iod->name.c_str(ctx));
+                if (!iod) {
+                    bfr_added++;
+                    iod = create_cell_ptr(id_BFR, ctx->idf("%s$iod_cd", cell->name.c_str(ctx)));
+                    NetInfo *new_out = ctx->createNet(ctx->idf("%s$O", iod->name.c_str(ctx)));
+                    iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                    cell->disconnectPort(id_C);
+                    if (c_net->name == ctx->id("$PACKER_GND"))
+                        iod->setParam(id_mode, Property(0, 2));
+                    else if (c_net->name == ctx->id("$PACKER_VCC"))
+                        iod->setParam(id_mode, Property(1, 2));
+                    else {
+                        iod->connectPort(id_I, c_net);
+                        iod->setParam(id_mode, Property(2, 2));
+                        iod->setParam(id_data_inv, Property(0, 1));
+                    }
+                    iod->connectPort(id_O, new_out);
+                    cell->connectPort(id_C, new_out);
+                } else {
+                    ddfr_added++;
+                    iod->type = id_DDFR;
+                    iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                    iod->setParam(id_path, Property(2, 2));
+                    ddfr_rewrite(iod);
+                    disconnect_unused(iod, id_O2);
+                    disconnect_if_gnd(iod, id_L);
+                    disconnect_if_gnd(iod, id_R);
+                }
+            } else {
+                dfr_added++;
+                iod->type = id_DFR;
+                iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                dff_rewrite(iod);
+            }
+            Loc cd_loc = cell->getLocation();
+            cd_loc.z += 3;
+            BelId bel = ctx->getBelByLocation(cd_loc);
+            ctx->bindBel(bel, iod, PlaceStrength::STRENGTH_LOCKED);
+        }
+        NetInfo *i_net = cell->getPort(id_I);
+        if (i_net) {
+            CellInfo *iod = net_driven_by(ctx, i_net, is_dfr, id_O);
+            if (iod && i_net->users.entries() != 1)
+                log_error("NX_DFR '%s' can only directly drive IOB.\n", iod->name.c_str(ctx));
+            if (!iod) {
+                iod = net_driven_by(ctx, i_net, is_ddfr, id_O);
+                if (iod && i_net->users.entries() != 1)
+                    log_error("NX_DDFR '%s' can only directly drive IOB.\n", iod->name.c_str(ctx));
+                if (!iod) {
+                    bfr_added++;
+                    iod = create_cell_ptr(id_BFR, ctx->idf("%s$iod_od", cell->name.c_str(ctx)));
+                    NetInfo *new_out = ctx->createNet(ctx->idf("%s$O", iod->name.c_str(ctx)));
+                    iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                    cell->disconnectPort(id_I);
+                    if (i_net->name == ctx->id("$PACKER_GND"))
+                        iod->setParam(id_mode, Property(0, 2));
+                    else if (i_net->name == ctx->id("$PACKER_VCC"))
+                        iod->setParam(id_mode, Property(1, 2));
+                    else {
+                        iod->connectPort(id_I, i_net);
+                        iod->setParam(id_mode, Property(2, 2));
+                        iod->setParam(id_data_inv, Property(0, 1));
+                    }
+                    iod->connectPort(id_O, new_out);
+                    cell->connectPort(id_I, new_out);
+                } else {
+                    ddfr_added++;
+                    iod->type = id_DDFR;
+                    iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                    iod->setParam(id_path, Property(0, 2));
+                    ddfr_rewrite(iod);
+                    disconnect_unused(iod, id_O2);
+                    disconnect_if_gnd(iod, id_L);
+                    disconnect_if_gnd(iod, id_R);
+                }
+            } else {
+                dfr_added++;
+                iod->type = id_DFR;
+                iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                dff_rewrite(iod);
+            }
+            Loc cd_loc = cell->getLocation();
+            cd_loc.z += 2;
+            BelId bel = ctx->getBelByLocation(cd_loc);
+            ctx->bindBel(bel, iod, PlaceStrength::STRENGTH_LOCKED);
+        }
+
+        NetInfo *o_net = cell->getPort(id_O);
+        if (o_net) {
+            CellInfo *iod = net_only_drives(ctx, o_net, is_dfr, id_I, true);
+            if (!(o_net->users.entries() == 1 && (*o_net->users.begin()).cell->type == id_NX_IOM_U)) {
+                bool bfr_mode = false;
+                bool ddfr_mode = false;
+                if (!iod) {
+                    iod = net_only_drives(ctx, o_net, is_ddfr, id_I, true);
+                    if (!iod) {
+                        bfr_added++;
+                        iod = create_cell_ptr(id_BFR, ctx->idf("%s$iod_id", cell->name.c_str(ctx)));
+                        NetInfo *new_in = ctx->createNet(ctx->idf("%s$I", iod->name.c_str(ctx)));
+                        iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                        cell->disconnectPort(id_O);
+                        iod->connectPort(id_O, o_net);
+                        iod->setParam(id_mode, Property(2, 2));
+                        iod->setParam(id_data_inv, Property(0, 1));
+                        iod->connectPort(id_I, new_in);
+                        cell->connectPort(id_O, new_in);
+                        bfr_mode = true;
+                    } else {
+                        ddfr_mode = true;
+                        ddfr_added++;
+                        iod->type = id_DDFR;
+                        iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                        iod->setParam(id_path, Property(1, 2));
+                        ddfr_rewrite(iod);
+                        disconnect_if_gnd(iod, id_I2);
+                        disconnect_if_gnd(iod, id_L);
+                        disconnect_if_gnd(iod, id_R);
+                    }
+                } else {
+                    dfr_added++;
+                    iod->type = id_DFR;
+                    iod->setParam(id_iobname, str_or_default(cell->params, id_iobname, ""));
+                    dff_rewrite(iod);
+                }
+                Loc cd_loc = cell->getLocation();
+                cd_loc.z += 1;
+                BelId bel = ctx->getBelByLocation(cd_loc);
+                ctx->bindBel(bel, iod, PlaceStrength::STRENGTH_LOCKED);
+
+                // Depending of DDFR mode we must use one of dedicated routes (ITCs)
+                if (!ddfr_mode && ctx->getBelType(bel) == id_DDFR) {
+                    WireId dwire = ctx->getBelPinWire(bel, id_O);
+                    for (PipId pip : ctx->getPipsDownhill(dwire)) {
+                        const auto &extra_data = *uarch->pip_extra_data(pip);
+                        if (!extra_data.name)
+                            continue;
+                        if (extra_data.type != PipExtra::PIP_EXTRA_MUX)
+                            continue;
+                        if (bfr_mode && extra_data.input == 2) {
+                            uarch->blocked_pips.emplace(pip);
+                        } else if (!bfr_mode && extra_data.input == 1) {
+                            uarch->blocked_pips.emplace(pip);
+                        }
+                    }
+                }
+            }
+        }
+    }
+    if (ddfr_added)
+        log_info("    %6d DDFRs used as DDFR\n", ddfr_added);
+    if (dfr_added)
+        log_info("    %6d DFRs/DDFRs used as DFR\n", dfr_added);
+    if (bfr_added)
+        log_info("    %6d DFRs/DDFRs used as BFR\n", bfr_added);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_ioms(void)
+{
+    log_info("Pack IOMs...\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_IOM_U))
+            continue;
+        ci.type = id_IOM;
+        IdString iob;
+        for (auto &port : ci.ports) {
+            if (port.second.type == PORT_IN && port.second.net != nullptr) {
+                if (port.second.net->name == ctx->id("$PACKER_GND"))
+                    ci.disconnectPort(port.first);
+                else if (port.second.net->driver.cell != nullptr &&
+                         port.second.net->driver.cell->type.in(id_IP, id_OP, id_IOP, id_ITP, id_OTP, id_IOTP)) {
+                    IdString loc = uarch->tile_name_id(port.second.net->driver.cell->bel.tile);
+                    if (iob != IdString() && loc != iob) {
+                        log_error("Unable to constrain IOM '%s', connection to multiple IO banks exist.\n",
+                                  ci.name.c_str(ctx));
+                    }
+                    iob = loc;
+                }
+            }
+        }
+        if (iob == IdString())
+            log_error("Unable to constrain IOM '%s', no connection to nearby IO banks found.\n", ci.name.c_str(ctx));
+        log_info("    Constraining '%s' to bank '%s'\n", ci.name.c_str(ctx), iob.c_str(ctx));
+        BelId bel = uarch->iom_bels[iob];
+        if (!ctx->checkBelAvail(bel)) {
+            log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci), ctx->nameOfBel(bel),
+                      ctx->nameOf(ctx->getBoundBelCell(bel)));
+        }
+        ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+    }
+}
+
+void NgUltraPacker::pack_cy_input_and_output(CellInfo *cy, IdString cluster, IdString in_port, IdString out_port,
+                                             int placer, int &lut_only, int &lut_and_ff, int &dff_only)
+{
+    CellInfo *fe = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$%s", cy->name.c_str(ctx), in_port.c_str(ctx)));
+    NetInfo *net = cy->getPort(in_port);
+    if (net) {
+        if (net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
+            fe->params[id_lut_table] = Property((net->name == ctx->id("$PACKER_GND")) ? 0x0000 : 0xffff, 16);
+            fe->params[id_lut_used] = Property(1, 1);
+            cy->disconnectPort(in_port);
+            NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", fe->name.c_str(ctx)));
+            fe->connectPort(id_LO, new_out);
+            cy->connectPort(in_port, new_out);
+        } else {
+            fe->params[id_lut_table] = Property(0xaaaa, 16);
+            fe->params[id_lut_used] = Property(1, 1);
+            cy->disconnectPort(in_port);
+            NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", fe->name.c_str(ctx)));
+            fe->connectPort(id_I1, net);
+            fe->connectPort(id_LO, new_out);
+            cy->connectPort(in_port, new_out);
+        }
+        lut_only++;
+    }
+    net = cy->getPort(out_port);
+    CellInfo *dff = net_only_drives(ctx, net, is_dff, id_I, true);
+    if (dff) {
+        if (ctx->verbose)
+            log_info("found attached dff %s\n", dff->name.c_str(ctx));
+        dff_to_fe(dff, fe, false);
+        packed_cells.insert(dff->name);
+        if (net) {
+            lut_only--;
+            lut_and_ff++;
+        } else
+            dff_only++;
+    } else {
+        fe->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
+    }
+    fe->cluster = cluster;
+    fe->constr_z = placer;
+    cy->constr_children.push_back(fe);
+}
+
+void NgUltraPacker::exchange_if_constant(CellInfo *cell, IdString input1, IdString input2)
+{
+    NetInfo *net1 = cell->getPort(input1);
+    NetInfo *net2 = cell->getPort(input2);
+    // GND on A
+    if (net1->name.in(ctx->id("$PACKER_GND"))) {
+        return;
+    }
+    // VCC on A -> exchange
+    // if GND on B and not on A -> exchange
+    if (net1->name.in(ctx->id("$PACKER_VCC")) || net2->name.in(ctx->id("$PACKER_GND"))) {
+        cell->disconnectPort(input1);
+        cell->disconnectPort(input2);
+        cell->connectPort(input1, net2);
+        cell->connectPort(input2, net1);
+    }
+}
+
+void NgUltraPacker::pack_cys(void)
+{
+    log_info("Packing carries..\n");
+    std::vector<CellInfo *> root_cys;
+    int lut_only = 0, lut_and_ff = 0, dff_only = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type != id_NX_CY)
+            continue;
+        bind_attr_loc(ci, &ci->attrs);
+        NetInfo *ci_net = ci->getPort(id_CI);
+        if (!ci_net || !ci_net->driver.cell || ci_net->driver.cell->type != id_NX_CY) {
+            root_cys.push_back(ci);
+        }
+        for (int i = 1; i <= 4; i++) {
+            connect_gnd_if_unconnected(ci, ctx->idf("A%d", i), false);
+            connect_gnd_if_unconnected(ci, ctx->idf("B%d", i), false);
+            exchange_if_constant(ci, ctx->idf("A%d", i), ctx->idf("B%d", i));
+        }
+        NetInfo *co_net = ci->getPort(id_CO);
+        if (!co_net) {
+            disconnect_unused(ci, id_CO);
+            // Disconnect unused ports on last CY in chain
+            // at least id_A1 and id_B1 will be connected
+            // Reverse direction, must stop if used, then
+            // rest is used as well
+            if (!ci->getPort(id_S4)) {
+                disconnect_unused(ci, id_S4);
+                disconnect_unused(ci, id_A4);
+                disconnect_unused(ci, id_B4);
+                if (!ci->getPort(id_S3)) {
+                    disconnect_unused(ci, id_S3);
+                    disconnect_unused(ci, id_A3);
+                    disconnect_unused(ci, id_B3);
+                    if (!ci->getPort(id_S2)) {
+                        disconnect_unused(ci, id_S2);
+                        disconnect_unused(ci, id_A2);
+                        disconnect_unused(ci, id_B2);
+                    };
+                }
+            }
+        }
+    }
+
+    std::vector<std::vector<CellInfo *>> groups;
+    for (auto root : root_cys) {
+        std::vector<CellInfo *> group;
+        CellInfo *cy = root;
+        group.push_back(cy);
+        while (true) {
+            NetInfo *co_net = cy->getPort(id_CO);
+            if (co_net && co_net->users.entries() > 0) {
+                cy = (*co_net->users.begin()).cell;
+                if (cy->type != id_NX_CY || co_net->users.entries() != 1) {
+                    log_warning("Cells %s CO output connected to:\n", group.back()->name.c_str(ctx));
+                    for (auto user : co_net->users)
+                        log_warning("\t%s of type %s\n", user.cell->name.c_str(ctx), user.cell->type.c_str(ctx));
+                    log_error("NX_CY can only be chained with one other NX_CY cell\n");
+                }
+                group.push_back(cy);
+            } else
+                break;
+        }
+        groups.push_back(group);
+    }
+
+    for (auto &grp : groups) {
+        CellInfo *root = grp.front();
+        root->type = id_CY;
+        root->cluster = root->name;
+        if (grp.size() > 24)
+            log_error("NX_CY chains are limited to contain 24 elements maximum.\n");
+
+        for (int i = 0; i < int(grp.size()); i++) {
+            CellInfo *cy = grp.at(i);
+            cy->type = id_CY;
+            if (i != 0) {
+                cy->cluster = root->name;
+                root->constr_children.push_back(cy);
+                cy->constr_z = PLACE_CY_CHAIN;
+            }
+            pack_cy_input_and_output(cy, root->name, id_B1, id_S1, PLACE_CY_FE1, lut_only, lut_and_ff, dff_only);
+            // Must check for B input otherwise we have bogus FEs
+            if (cy->getPort(id_B2))
+                pack_cy_input_and_output(cy, root->name, id_B2, id_S2, PLACE_CY_FE2, lut_only, lut_and_ff, dff_only);
+            if (cy->getPort(id_B3))
+                pack_cy_input_and_output(cy, root->name, id_B3, id_S3, PLACE_CY_FE3, lut_only, lut_and_ff, dff_only);
+            if (cy->getPort(id_B4))
+                pack_cy_input_and_output(cy, root->name, id_B4, id_S4, PLACE_CY_FE4, lut_only, lut_and_ff, dff_only);
+            NetInfo *net = cy->getPort(id_CI);
+            if (net) {
+                if (net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
+                    // Constant driver for CI is configuration
+                    cy->disconnectPort(id_CI);
+                } else {
+                    if (net->driver.cell && net->driver.cell->type != id_CY)
+                        log_error("CI must be constant or driven by CO in cell '%s'\n", cy->name.c_str(ctx));
+                }
+            }
+        }
+    }
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_xrf_input_and_output(CellInfo *xrf, IdString cluster, IdString in_port, IdString out_port,
+                                              ClusterPlacement placement, int &lut_only, int &lut_and_ff, int &dff_only)
+{
+    NetInfo *net = xrf->getPort(in_port);
+    NetInfo *net_out = nullptr;
+    if (out_port != IdString()) {
+        net_out = xrf->getPort(out_port);
+        if (net_out && net_out->users.entries() == 0) {
+            xrf->disconnectPort(out_port);
+            net_out = nullptr;
+        }
+    }
+    if (!net && !net_out)
+        return;
+    IdString name = in_port;
+    if (name == IdString())
+        name = out_port;
+    CellInfo *fe = create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$%s", xrf->name.c_str(ctx), name.c_str(ctx)));
+
+    if (net) {
+        if (net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
+            fe->params[id_lut_table] = Property((net->name == ctx->id("$PACKER_GND")) ? 0x0000 : 0xffff, 16);
+            fe->params[id_lut_used] = Property(1, 1);
+            xrf->disconnectPort(in_port);
+            NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", fe->name.c_str(ctx)));
+            fe->connectPort(id_LO, new_out);
+            xrf->connectPort(in_port, new_out);
+        } else {
+            CellInfo *lut = net_driven_by(ctx, net, is_lut, id_O);
+            if (lut && net->users.entries() == 1) {
+                if (!lut->params.count(id_lut_table))
+                    log_error("Cell '%s' missing lut_table\n", lut->name.c_str(ctx));
+                lut_to_fe(lut, fe, false, lut->params[id_lut_table]);
+                packed_cells.insert(lut->name);
+            } else {
+                fe->params[id_lut_table] = Property(0xaaaa, 16);
+                fe->params[id_lut_used] = Property(1, 1);
+                xrf->disconnectPort(in_port);
+                NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", fe->name.c_str(ctx)));
+                fe->connectPort(id_I1, net);
+                fe->connectPort(id_LO, new_out);
+                xrf->connectPort(in_port, new_out);
+            }
+        }
+        lut_only++;
+    }
+    if (net_out) {
+        CellInfo *dff = net_only_drives(ctx, net_out, is_dff, id_I, true);
+        if (dff) {
+            if (ctx->verbose)
+                log_info("found attached dff %s\n", dff->name.c_str(ctx));
+            dff_to_fe(dff, fe, false);
+            packed_cells.insert(dff->name);
+            if (net) {
+                lut_only--;
+                lut_and_ff++;
+            } else
+                dff_only++;
+        }
+    }
+    fe->cluster = cluster;
+    fe->constr_z = placement;
+    xrf->constr_children.push_back(fe);
+}
+
+void NgUltraPacker::disconnect_unused(CellInfo *cell, IdString port)
+{
+    NetInfo *net = cell->getPort(port);
+    if (net) {
+        // NanoXplore tools usually connects 0 to unused port, no need to warn
+        // Sometimes there is unused nets, so number of entries is zero
+        if (net->users.entries() != 0 && !net->name.in(ctx->id("$PACKER_GND")))
+            log_warning("Disconnected unused port '%s' from cell '%s'.\n", port.c_str(ctx), cell->name.c_str(ctx));
+        cell->disconnectPort(port);
+    }
+}
+
+void NgUltraPacker::pack_rfs(void)
+{
+    log_info("Packing RFs..\n");
+    int lut_only = 0, lut_and_ff = 0, dff_only = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_RFB_U))
+            continue;
+        int mode = int_or_default(ci.params, id_mode, 0);
+        switch (mode) {
+        case 0:
+            ci.type = id_RF;
+            break;
+        case 1:
+            ci.type = id_RFSP;
+            break;
+        case 2:
+            ci.type = id_XHRF;
+            break;
+        case 3:
+            ci.type = id_XWRF;
+            break;
+        case 4:
+            ci.type = id_XPRF;
+            break;
+        default:
+            log_error("Unknown mode %d for cell '%s'.\n", mode, ci.name.c_str(ctx));
+        }
+        ci.cluster = ci.name;
+        bind_attr_loc(&ci, &ci.attrs);
+
+        for (int i = 1; i <= 18; i++) {
+            connect_gnd_if_unconnected(&ci, ctx->idf("I%d", i));
+            pack_xrf_input_and_output(&ci, ci.name, ctx->idf("I%d", i), ctx->idf("O%d", i),
+                                      ClusterPlacement(PLACE_XRF_I1 + i - 1), lut_only, lut_and_ff, dff_only);
+        }
+        if (mode != 1) {
+            for (int i = 1; i <= 5; i++) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("RA%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("RA%d", i), IdString(),
+                                          ClusterPlacement(PLACE_XRF_RA1 + i - 1), lut_only, lut_and_ff, dff_only);
+            }
+        } else {
+            // SPREG mode does not use RA inputs
+            for (int i = 1; i <= 5; i++)
+                disconnect_unused(&ci, ctx->idf("RA%d", i));
+        }
+
+        if (mode == 2 || mode == 4) {
+            connect_gnd_if_unconnected(&ci, id_RA6);
+            pack_xrf_input_and_output(&ci, ci.name, id_RA6, IdString(), PLACE_XRF_RA6, lut_only, lut_and_ff, dff_only);
+        } else {
+            disconnect_unused(&ci, id_RA6);
+        }
+
+        if (mode == 4) {
+            for (int i = 7; i <= 10; i++) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("RA%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("RA%d", i), IdString(),
+                                          ClusterPlacement(PLACE_XRF_RA1 + i - 1), lut_only, lut_and_ff, dff_only);
+            }
+        } else {
+            for (int i = 7; i <= 10; i++)
+                disconnect_unused(&ci, ctx->idf("RA%d", i));
+        }
+
+        for (int i = 1; i <= 5; i++) {
+            connect_gnd_if_unconnected(&ci, ctx->idf("WA%d", i));
+            pack_xrf_input_and_output(&ci, ci.name, ctx->idf("WA%d", i), IdString(),
+                                      ClusterPlacement(PLACE_XRF_WA1 + i - 1), lut_only, lut_and_ff, dff_only);
+        }
+
+        if (mode == 2) {
+            connect_gnd_if_unconnected(&ci, id_WA6);
+            pack_xrf_input_and_output(&ci, ci.name, id_WA6, IdString(), PLACE_XRF_WA6, lut_only, lut_and_ff, dff_only);
+        } else {
+            disconnect_unused(&ci, id_WA6);
+        }
+
+        connect_gnd_if_unconnected(&ci, id_WE);
+        pack_xrf_input_and_output(&ci, ci.name, id_WE, IdString(), PLACE_XRF_WE, lut_only, lut_and_ff, dff_only);
+
+        disconnect_if_gnd(&ci, id_WEA);
+        pack_xrf_input_and_output(&ci, ci.name, id_WEA, IdString(), PLACE_XRF_WEA, lut_only, lut_and_ff, dff_only);
+
+        if (mode == 3) {
+            for (int i = 19; i <= 36; i++) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("I%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("I%d", i), ctx->idf("O%d", i),
+                                          ClusterPlacement(PLACE_XRF_I1 + i - 1), lut_only, lut_and_ff, dff_only);
+            }
+        } else if (mode == 4) {
+            for (int i = 19; i <= 36; i++) {
+                disconnect_unused(&ci, ctx->idf("I%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, IdString(), ctx->idf("O%d", i),
+                                          ClusterPlacement(PLACE_XRF_I1 + i - 1), lut_only, lut_and_ff, dff_only);
+            }
+        } else {
+            for (int i = 19; i <= 36; i++) {
+                disconnect_unused(&ci, ctx->idf("I%d", i));
+                disconnect_unused(&ci, ctx->idf("O%d", i));
+            }
+        }
+
+        if (mode > 1) {
+            // XRF
+            ci.ports[id_WCK1].name = id_WCK1;
+            ci.ports[id_WCK1].type = PORT_IN;
+            ci.ports[id_WCK2].name = id_WCK2;
+            ci.ports[id_WCK2].type = PORT_IN;
+            NetInfo *net = ci.getPort(id_WCK);
+            if (net) {
+                ci.disconnectPort(id_WCK);
+
+                ci.connectPort(id_WCK1, net);
+                ci.connectPort(id_WCK2, net);
+            }
+        }
+    }
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_cdcs(void)
+{
+    log_info("Packing CDCs..\n");
+    int lut_only = 0, lut_and_ff = 0, dff_only = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_CDC_U))
+            continue;
+        int mode = int_or_default(ci.params, id_mode, 0);
+        switch (mode) {
+        case 0:
+            ci.type = id_DDE;
+            break;
+        case 1:
+            ci.type = id_TDE;
+            break;
+        case 2:
+            ci.type = id_CDC;
+            break;
+        case 3:
+            ci.type = id_BGC;
+            break;
+        case 4:
+            ci.type = id_GBC;
+            break;
+        case 5:
+            ci.type = id_XCDC;
+            break;
+        default:
+            log_error("Unknown mode %d for cell '%s'.\n", mode, ci.name.c_str(ctx));
+        }
+        ci.cluster = ci.name;
+
+        // If unconnected, connect GND to inputs that are actually used as outputs
+        for (int i = 1; i <= 6; i++) {
+            if (ci.getPort(ctx->idf("AO%d", i))) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("AI%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("AI%d", i), ctx->idf("AO%d", i),
+                                          ClusterPlacement(PLACE_CDC_AI1 + i - 1), lut_only, lut_and_ff, dff_only);
+            } else
+                disconnect_unused(&ci, ctx->idf("AI%d", i));
+            if (ci.getPort(ctx->idf("BO%d", i))) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("BI%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("BI%d", i), ctx->idf("BO%d", i),
+                                          ClusterPlacement(PLACE_CDC_BI1 + i - 1), lut_only, lut_and_ff, dff_only);
+            } else
+                disconnect_unused(&ci, ctx->idf("BI%d", i));
+            if (ci.type.in(id_XCDC)) {
+                if (ci.getPort(ctx->idf("CO%d", i))) {
+                    connect_gnd_if_unconnected(&ci, ctx->idf("CI%d", i));
+                    pack_xrf_input_and_output(&ci, ci.name, ctx->idf("CI%d", i), ctx->idf("CO%d", i),
+                                              ClusterPlacement(PLACE_CDC_CI1 + i - 1), lut_only, lut_and_ff, dff_only);
+                } else
+                    disconnect_unused(&ci, ctx->idf("CI%d", i));
+                if (ci.getPort(ctx->idf("DO%d", i))) {
+                    connect_gnd_if_unconnected(&ci, ctx->idf("DI%d", i));
+                    pack_xrf_input_and_output(&ci, ci.name, ctx->idf("DI%d", i), ctx->idf("DO%d", i),
+                                              ClusterPlacement(PLACE_CDC_DI1 + i - 1), lut_only, lut_and_ff, dff_only);
+                } else
+                    disconnect_unused(&ci, ctx->idf("DI%d", i));
+            }
+        }
+
+        // Remove inputs and outputs that are not used for specific types
+        if (ci.type.in(id_BGC, id_GBC)) {
+            disconnect_unused(&ci, id_CK1);
+            disconnect_unused(&ci, id_CK2);
+            disconnect_unused(&ci, id_ADRSTI);
+            disconnect_unused(&ci, id_ADRSTO);
+            disconnect_unused(&ci, id_BDRSTI);
+            disconnect_unused(&ci, id_BDRSTO);
+        } else {
+            connect_gnd_if_unconnected(&ci, id_ADRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_ADRSTI, id_ADRSTO, PLACE_CDC_ADRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+            connect_gnd_if_unconnected(&ci, id_BDRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_BDRSTI, id_BDRSTO, PLACE_CDC_BDRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+        }
+        if (ci.type.in(id_BGC, id_GBC, id_DDE)) {
+            disconnect_unused(&ci, id_ASRSTI);
+            disconnect_unused(&ci, id_ASRSTO);
+            disconnect_unused(&ci, id_BSRSTI);
+            disconnect_unused(&ci, id_BSRSTO);
+        } else {
+            connect_gnd_if_unconnected(&ci, id_ASRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_ASRSTI, id_ASRSTO, PLACE_CDC_ASRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+            connect_gnd_if_unconnected(&ci, id_BSRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_BSRSTI, id_BSRSTO, PLACE_CDC_BSRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+        }
+
+        // Only XCDC is using these ports, remove from others if used
+        if (!ci.type.in(id_XCDC)) {
+            disconnect_unused(&ci, id_CDRSTI);
+            disconnect_unused(&ci, id_CDRSTO);
+            for (int i = 1; i <= 6; i++) {
+                disconnect_unused(&ci, ctx->idf("CI%d", i));
+                disconnect_unused(&ci, ctx->idf("CO%d", i));
+            }
+            disconnect_unused(&ci, id_CSRSTI);
+            disconnect_unused(&ci, id_CSRSTO);
+
+            disconnect_unused(&ci, id_DDRSTI);
+            disconnect_unused(&ci, id_DDRSTO);
+            for (int i = 1; i <= 6; i++) {
+                disconnect_unused(&ci, ctx->idf("DI%d", i));
+                disconnect_unused(&ci, ctx->idf("DO%d", i));
+            }
+            disconnect_unused(&ci, id_DSRSTI);
+            disconnect_unused(&ci, id_DSRSTO);
+        } else {
+            connect_gnd_if_unconnected(&ci, id_CDRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_CDRSTI, id_CDRSTO, PLACE_CDC_CDRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+            connect_gnd_if_unconnected(&ci, id_DDRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_DDRSTI, id_DDRSTO, PLACE_CDC_DDRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+            connect_gnd_if_unconnected(&ci, id_CSRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_CSRSTI, id_CSRSTO, PLACE_CDC_CSRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+            connect_gnd_if_unconnected(&ci, id_DSRSTI);
+            pack_xrf_input_and_output(&ci, ci.name, id_DSRSTI, id_DSRSTO, PLACE_CDC_DSRSTI, lut_only, lut_and_ff,
+                                      dff_only);
+        }
+    }
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::pack_fifos(void)
+{
+    log_info("Packing FIFOs..\n");
+    int lut_only = 0, lut_and_ff = 0, dff_only = 0;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_FIFO_U))
+            continue;
+        int mode = int_or_default(ci.params, id_mode, 0);
+        switch (mode) {
+        case 0:
+            ci.type = id_FIFO;
+            break;
+        case 1:
+            ci.type = id_XHFIFO;
+            break;
+        case 2:
+            ci.type = id_XWFIFO;
+            break;
+        default:
+            log_error("Unknown mode %d for cell '%s'.\n", mode, ci.name.c_str(ctx));
+        }
+        ci.cluster = ci.name;
+        bool use_write_arst = bool_or_default(ci.params, id_use_write_arst, false);
+        bool use_read_arst = bool_or_default(ci.params, id_use_read_arst, false);
+
+        int rsti = (ci.type == id_FIFO) ? 2 : 4;
+        for (int i = 1; i <= rsti; i++) {
+            IdString port = ctx->idf("WRSTI%d", i);
+            ci.ports[port].name = port;
+            ci.ports[port].type = PORT_IN;
+            port = ctx->idf("RRSTI%d", i);
+            ci.ports[port].name = port;
+            ci.ports[port].type = PORT_IN;
+        }
+
+        if (use_write_arst) {
+            IdString port = id_WRSTI;
+            connect_gnd_if_unconnected(&ci, port);
+            NetInfo *wrsti_net = ci.getPort(port);
+            ci.disconnectPort(port);
+            for (int i = 1; i <= rsti; i++)
+                ci.connectPort(ctx->idf("WRSTI%d", i), wrsti_net);
+            if (mode != 0)
+                disconnect_unused(&ci, id_WRSTO);
+            pack_xrf_input_and_output(&ci, ci.name, id_WRSTI1, id_WRSTO, PLACE_FIFO_WRSTI1, lut_only, lut_and_ff,
+                                      dff_only);
+            pack_xrf_input_and_output(&ci, ci.name, id_WRSTI2, IdString(), PLACE_FIFO_WRSTI2, lut_only, lut_and_ff,
+                                      dff_only);
+            if (mode != 0) {
+                pack_xrf_input_and_output(&ci, ci.name, id_WRSTI3, IdString(), PLACE_FIFO_WRSTI3, lut_only, lut_and_ff,
+                                          dff_only);
+                pack_xrf_input_and_output(&ci, ci.name, id_WRSTI4, IdString(), PLACE_FIFO_WRSTI4, lut_only, lut_and_ff,
+                                          dff_only);
+            }
+        } else {
+            disconnect_unused(&ci, id_WRSTI);
+        }
+        if (use_read_arst) {
+            IdString port = id_RRSTI;
+            connect_gnd_if_unconnected(&ci, port);
+            NetInfo *rrsti_net = ci.getPort(port);
+            ci.disconnectPort(port);
+            for (int i = 1; i <= rsti; i++)
+                ci.connectPort(ctx->idf("RRSTI%d", i), rrsti_net);
+            if (mode != 0)
+                disconnect_unused(&ci, id_RRSTO);
+            pack_xrf_input_and_output(&ci, ci.name, id_RRSTI1, id_RRSTO, PLACE_FIFO_RRSTI1, lut_only, lut_and_ff,
+                                      dff_only);
+            pack_xrf_input_and_output(&ci, ci.name, id_RRSTI2, IdString(), PLACE_FIFO_RRSTI2, lut_only, lut_and_ff,
+                                      dff_only);
+            if (mode != 0) {
+                pack_xrf_input_and_output(&ci, ci.name, id_RRSTI3, IdString(), PLACE_FIFO_RRSTI3, lut_only, lut_and_ff,
+                                          dff_only);
+                pack_xrf_input_and_output(&ci, ci.name, id_RRSTI4, IdString(), PLACE_FIFO_RRSTI4, lut_only, lut_and_ff,
+                                          dff_only);
+            }
+        } else {
+            disconnect_unused(&ci, id_RRSTI);
+        }
+
+        for (int i = 1; i <= 18; i++) {
+            connect_gnd_if_unconnected(&ci, ctx->idf("I%d", i));
+            pack_xrf_input_and_output(&ci, ci.name, ctx->idf("I%d", i), ctx->idf("O%d", i),
+                                      ClusterPlacement(PLACE_FIFO_I1 + i - 1), lut_only, lut_and_ff, dff_only);
+        }
+
+        if (mode == 0) {
+            for (int i = 19; i <= 36; i++) {
+                disconnect_unused(&ci, ctx->idf("I%d", i));
+                disconnect_unused(&ci, ctx->idf("O%d", i));
+            }
+        } else {
+            for (int i = 19; i <= 36; i++) {
+                connect_gnd_if_unconnected(&ci, ctx->idf("I%d", i));
+                pack_xrf_input_and_output(&ci, ci.name, ctx->idf("I%d", i), ctx->idf("O%d", i),
+                                          ClusterPlacement(PLACE_FIFO_I1 + i - 1), lut_only, lut_and_ff, dff_only);
+            }
+        }
+        for (int i = 1; i <= 6; i++) {
+            connect_gnd_if_unconnected(&ci, ctx->idf("RAI%d", i));
+            pack_xrf_input_and_output(&ci, ci.name, ctx->idf("RAI%d", i), ctx->idf("RAO%d", i),
+                                      ClusterPlacement(PLACE_FIFO_RAI1 + i - 1), lut_only, lut_and_ff, dff_only);
+
+            connect_gnd_if_unconnected(&ci, ctx->idf("WAI%d", i));
+            pack_xrf_input_and_output(&ci, ci.name, ctx->idf("WAI%d", i), ctx->idf("WAO%d", i),
+                                      ClusterPlacement(PLACE_FIFO_WAI1 + i - 1), lut_only, lut_and_ff, dff_only);
+        }
+
+        if (mode == 0) {
+            disconnect_unused(&ci, id_RAI7);
+            disconnect_unused(&ci, id_WAI7);
+        } else {
+            connect_gnd_if_unconnected(&ci, id_RAI7);
+            pack_xrf_input_and_output(&ci, ci.name, id_RAI7, id_RAO7, PLACE_FIFO_RAI7, lut_only, lut_and_ff, dff_only);
+
+            connect_gnd_if_unconnected(&ci, id_WAI7);
+            pack_xrf_input_and_output(&ci, ci.name, id_WAI7, id_WAO7, PLACE_FIFO_WAI7, lut_only, lut_and_ff, dff_only);
+        }
+
+        connect_gnd_if_unconnected(&ci, id_WE);
+        pack_xrf_input_and_output(&ci, ci.name, id_WE, IdString(), PLACE_FIFO_WE, lut_only, lut_and_ff, dff_only);
+
+        disconnect_if_gnd(&ci, id_WEA);
+        pack_xrf_input_and_output(&ci, ci.name, id_WEA, IdString(), PLACE_FIFO_WEA, lut_only, lut_and_ff, dff_only);
+
+        if (mode == 0) {
+            // FIFO
+            ci.renamePort(id_WEQ1, id_WEQ);
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ, PLACE_FIFO_WEQ1, lut_only, lut_and_ff,
+                                      dff_only);
+            disconnect_unused(&ci, id_WEQ2);
+
+            ci.renamePort(id_REQ1, id_REQ);
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_REQ, PLACE_FIFO_REQ1, lut_only, lut_and_ff,
+                                      dff_only);
+            disconnect_unused(&ci, id_REQ2);
+        } else {
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ1, PLACE_FIFO_WEQ1, lut_only, lut_and_ff,
+                                      dff_only);
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ2, PLACE_FIFO_WEQ2, lut_only, lut_and_ff,
+                                      dff_only);
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ1, PLACE_FIFO_REQ1, lut_only, lut_and_ff,
+                                      dff_only);
+            pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ2, PLACE_FIFO_REQ2, lut_only, lut_and_ff,
+                                      dff_only);
+
+            // XFIFO
+            ci.ports[id_WCK1].name = id_WCK1;
+            ci.ports[id_WCK1].type = PORT_IN;
+            ci.ports[id_WCK2].name = id_WCK2;
+            ci.ports[id_WCK2].type = PORT_IN;
+            ci.ports[id_RCK1].name = id_RCK1;
+            ci.ports[id_RCK1].type = PORT_IN;
+            ci.ports[id_RCK2].name = id_RCK2;
+            ci.ports[id_RCK2].type = PORT_IN;
+            NetInfo *net = ci.getPort(id_WCK);
+            if (net) {
+                ci.disconnectPort(id_WCK);
+
+                ci.connectPort(id_WCK1, net);
+                ci.connectPort(id_WCK2, net);
+            }
+            net = ci.getPort(id_RCK);
+            if (net) {
+                ci.disconnectPort(id_RCK);
+
+                ci.connectPort(id_RCK1, net);
+                ci.connectPort(id_RCK2, net);
+            }
+        }
+    }
+    if (lut_only)
+        log_info("    %6d FEs used as LUT only\n", lut_only);
+    if (lut_and_ff)
+        log_info("    %6d FEs used as LUT and DFF\n", lut_and_ff);
+    if (dff_only)
+        log_info("    %6d FEs used as DFF only\n", dff_only);
+    flush_cells();
+}
+
+void NgUltraPacker::insert_ioms()
+{
+    std::vector<IdString> pins_needing_iom;
+    for (auto &net : ctx->nets) {
+        NetInfo *ni = net.second.get();
+        // Skip undriven nets
+        if (ni->driver.cell == nullptr)
+            continue;
+        if (!ni->driver.cell->type.in(id_BFR)) {
+            continue;
+        }
+        Loc iotp_loc = ni->driver.cell->getLocation();
+        iotp_loc.z -= 1;
+        BelId bel = ctx->getBelByLocation(iotp_loc);
+        if (uarch->global_capable_bels.count(bel) == 0)
+            continue;
+        for (const auto &usr : ni->users) {
+            if (uarch->is_fabric_lowskew_sink(usr) || uarch->is_ring_clock_sink(usr) ||
+                uarch->is_tube_clock_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
+                pins_needing_iom.emplace_back(ni->name);
+                break;
+            }
+        }
+    }
+    // Sort clocks by max fanout
+    log_info("Inserting IOMs...\n");
+    int bfr_removed = 0;
+    for (size_t i = 0; i < pins_needing_iom.size(); i++) {
+        NetInfo *net = ctx->nets.at(pins_needing_iom.at(i)).get();
+        Loc iotp_loc = net->driver.cell->getLocation();
+        iotp_loc.z -= 1;
+        BelId iotp_bel = ctx->getBelByLocation(iotp_loc);
+
+        IdString iob = uarch->tile_name_id(iotp_bel.tile);
+        BelId bel = uarch->iom_bels[iob];
+
+        CellInfo *iom = nullptr;
+        IdString port = uarch->global_capable_bels.at(iotp_bel);
+        CellInfo *input_pad = ctx->getBoundBelCell(iotp_bel);
+        std::string iobname = str_or_default(input_pad->params, id_iobname, "");
+        if (!ctx->checkBelAvail(bel)) {
+            iom = ctx->getBoundBelCell(bel);
+            log_info("    Reusing IOM in bank '%s' for signal '%s'\n", iob.c_str(ctx), iobname.c_str());
+        } else {
+            iom = create_cell_ptr(id_IOM, ctx->idf("%s$iom", iob.c_str(ctx)));
+            log_info("    Adding IOM in bank '%s' for signal '%s'\n", iob.c_str(ctx), iobname.c_str());
+        }
+        if (iom->getPort(port)) {
+            log_error("Port '%s' of IOM cell '%s' is already used.\n", port.c_str(ctx), iom->name.c_str(ctx));
+        }
+        NetInfo *iom_to_clk = ctx->createNet(ctx->idf("%s$iom", net->name.c_str(ctx)));
+        for (const auto &usr : net->users) {
+            IdString port = usr.port;
+            usr.cell->disconnectPort(port);
+            usr.cell->connectPort(port, iom_to_clk);
+        }
+        iom->connectPort(port, input_pad->getPort(id_O));
+        iom->connectPort((port == id_P17RI) ? id_CKO1 : id_CKO2, iom_to_clk);
+        if (ctx->checkBelAvail(bel))
+            ctx->bindBel(bel, iom, PlaceStrength::STRENGTH_LOCKED);
+        CellInfo *bfr = net->driver.cell;
+        if (bfr->type == id_BFR && bfr->getPort(id_O)->users.empty()) {
+            bfr->disconnectPort(id_O);
+            bfr->disconnectPort(id_I);
+            bfr_removed++;
+            ctx->cells.erase(bfr->name);
+        }
+    }
+    if (bfr_removed)
+        log_info("    Removed %d unused BFR\n", bfr_removed);
+}
+
+void NgUltraPacker::insert_wfbs()
+{
+    log_info("Inserting WFBs...\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (ci.type.in(id_IOM)) {
+            insert_wfb(&ci, id_CKO1);
+            insert_wfb(&ci, id_CKO2);
+        } else if (ci.type.in(id_PLL)) {
+            insert_wfb(&ci, id_OSC);
+            insert_wfb(&ci, id_VCO);
+            insert_wfb(&ci, id_REFO);
+            insert_wfb(&ci, id_LDFO);
+            insert_wfb(&ci, id_CLK_DIV1);
+            insert_wfb(&ci, id_CLK_DIV2);
+            insert_wfb(&ci, id_CLK_DIV3);
+            insert_wfb(&ci, id_CLK_DIV4);
+            insert_wfb(&ci, id_CLK_DIVD1);
+            insert_wfb(&ci, id_CLK_DIVD2);
+            insert_wfb(&ci, id_CLK_DIVD3);
+            insert_wfb(&ci, id_CLK_DIVD4);
+            insert_wfb(&ci, id_CLK_DIVD5);
+            insert_wfb(&ci, id_CLK_CAL_DIV);
+        }
+    }
+}
+
+void NgUltraPacker::mandatory_param(CellInfo *cell, IdString param)
+{
+    if (!cell->params.count(param))
+        log_error("Mandatory parameter '%s' of cell '%s'(%s) is missing.\n", param.c_str(ctx), cell->name.c_str(ctx),
+                  cell->type.c_str(ctx));
+}
+
+int NgUltraPacker::memory_width(int config, bool ecc)
+{
+    if (ecc) {
+        if (config == 4)
+            return 18;
+        else
+            log_error("ECC mode only support width of 18.\n");
+    } else {
+        switch (config) {
+        case 0:
+            return 1; // NOECC_48kx1
+        case 1:
+            return 2; // NOECC_24kx2
+        case 2:
+            return 4; // NOECC_12kx4
+        case 3:
+            return 8; // NOECC_6kx8
+        case 4:
+            return 12; // NOECC_4kx12
+        case 5:
+            return 24; // NOECC_2kx24
+        case 6:
+            return 3; // NOECC_16kx3
+        case 7:
+            return 6; // NOECC_8kx6
+        }
+        log_error("Unknown memory configuration width config '%d'.\n", config);
+    }
+}
+
+int NgUltraPacker::memory_addr_bits(int config, bool ecc)
+{
+    if (ecc) {
+        if (config == 4)
+            return 11;
+        else
+            log_error("ECC mode only support width of 18.\n");
+    } else {
+        switch (config) {
+        case 0:
+            return 16; // NOECC_48kx1
+        case 1:
+            return 15; // NOECC_24kx2
+        case 2:
+            return 14; // NOECC_12kx4
+        case 3:
+            return 13; // NOECC_6kx8
+        case 4:
+            return 12; // NOECC_4kx12
+        case 5:
+            return 11; // NOECC_2kx24
+        case 6:
+            return 14; // NOECC_16kx3
+        case 7:
+            return 13; // NOECC_8kx6
+        }
+        log_error("Unknown memory configuration width config '%d'.\n", config);
+    }
+}
+
+void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
+{
+    NetInfo *net = cell->getPort(port);
+    if (!net)
+        return;
+
+    CellInfo *wfg = net_only_drives(ctx, net, is_wfg, id_ZI, true);
+    if (wfg)
+        return;
+    bool in_fabric = false;
+    bool in_ring = false;
+    for (const auto &usr : net->users) {
+        if (uarch->is_fabric_lowskew_sink(usr) || uarch->is_tube_clock_sink(usr) ||
+            uarch->is_ring_over_tile_clock_sink(usr))
+            in_fabric = true;
+        else
+            in_ring = true;
+    }
+    // If all in ring and none in fabric no need for WFB
+    if (in_ring && !in_fabric)
+        return;
+    log_info("    Inserting WFB for cell '%s' port '%s'\n", cell->name.c_str(ctx), port.c_str(ctx));
+    CellInfo *wfb = create_cell_ptr(id_WFB, ctx->idf("%s$%s", cell->name.c_str(ctx), port.c_str(ctx)));
+    if (in_ring && in_fabric) {
+        // If both in ring and in fabric create new signal
+        wfb->connectPort(id_ZI, net);
+        NetInfo *net_zo = ctx->createNet(ctx->idf("%s$ZO", net->name.c_str(ctx)));
+        wfb->connectPort(id_ZO, net_zo);
+        for (const auto &usr : net->users) {
+            if (uarch->is_fabric_lowskew_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
+                usr.cell->disconnectPort(usr.port);
+                usr.cell->connectPort(usr.port, net_zo);
+            }
+        }
+    } else {
+        // Only in fabric, reconnect wire directly to WFB
+        cell->disconnectPort(port);
+        wfb->connectPort(id_ZO, net);
+        NetInfo *new_out = ctx->createNet(ctx->idf("%s$%s", net->name.c_str(ctx), port.c_str(ctx)));
+        cell->connectPort(port, new_out);
+        wfb->connectPort(id_ZI, new_out);
+    }
+}
+
+void NgUltraPacker::constrain_location(CellInfo *cell)
+{
+    std::string location = str_or_default(cell->params, id_location, "");
+    if (!location.empty()) {
+        if (uarch->locations.count(location)) {
+            BelId bel = uarch->locations[location];
+            if (ctx->getBelType(bel) != cell->type) {
+                log_error("Location '%s' is wrong for bel type '%s'.\n", location.c_str(), cell->type.c_str(ctx));
+            }
+            if (ctx->checkBelAvail(bel)) {
+                log_info("    Constraining %s '%s' to '%s'\n", cell->type.c_str(ctx), cell->name.c_str(ctx),
+                         location.c_str());
+                ctx->bindBel(bel, cell, PlaceStrength::STRENGTH_LOCKED);
+            } else {
+                log_error("Bel at location '%s' is already used by other cell.\n", location.c_str());
+            }
+
+        } else {
+            log_error("Unknown location '%s' for cell '%s'.\n", location.c_str(), cell->name.c_str(ctx));
+        }
+    }
+}
+
+void NgUltraPacker::pack_plls(void)
+{
+    log_info("Packing PLLs..\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_PLL_U))
+            continue;
+        ci.type = id_PLL;
+        constrain_location(&ci);
+
+        disconnect_if_gnd(&ci, id_FBK);
+        disconnect_if_gnd(&ci, id_CLK_CAL);
+        disconnect_if_gnd(&ci, id_R);
+        disconnect_if_gnd(&ci, id_EXT_CAL1);
+        disconnect_if_gnd(&ci, id_EXT_CAL2);
+        disconnect_if_gnd(&ci, id_EXT_CAL3);
+        disconnect_if_gnd(&ci, id_EXT_CAL4);
+        disconnect_if_gnd(&ci, id_EXT_CAL5);
+        disconnect_if_gnd(&ci, id_EXT_CAL_LOCKED);
+        disconnect_if_gnd(&ci, id_ARST_CAL);
+    }
+}
+
+void NgUltraPacker::pack_wfgs(void)
+{
+    log_info("Packing WFGs..\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_WFG_U))
+            continue;
+        ci.type = id_WFG;
+        constrain_location(&ci);
+        int mode = int_or_default(ci.params, id_mode, 1);
+        if (mode == 0) { // WFB - bypass mode
+            ci.type = id_WFB;
+            // must not be used, zero is tollerated
+            disconnect_unused(&ci, id_SI);
+            disconnect_unused(&ci, id_SO);
+            disconnect_unused(&ci, id_R);
+        } else if (mode == 1) {
+            // Can be unused, if zero it is unused
+            disconnect_if_gnd(&ci, id_SI);
+            disconnect_if_gnd(&ci, id_R);
+        } else if (mode == 2) {
+            // Allow mode 2
+        } else {
+            log_error("Unknown mode %d for cell '%s'.\n", mode, ci.name.c_str(ctx));
+        }
+        NetInfo *zi = ci.getPort(id_ZI);
+        if (!zi || !zi->driver.cell)
+            log_error("WFG port ZI of '%s' must be driven.\n", ci.name.c_str(ctx));
+        NetInfo *zo = ci.getPort(id_ZO);
+        if (!zo || zo->users.entries() == 0)
+            log_error("WFG port ZO of '%s' must be connected.\n", ci.name.c_str(ctx));
+    }
+}
+
+void NgUltraPacker::pack_gcks(void)
+{
+    log_info("Packing GCKs..\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_GCK_U))
+            continue;
+        ci.type = id_GCK;
+        std::string mode = str_or_default(ci.params, id_std_mode, "BYPASS");
+        if (mode == "BYPASS") {
+            disconnect_unused(&ci, id_SI2);
+            disconnect_unused(&ci, id_CMD);
+        } else if (mode == "CSC") {
+            disconnect_unused(&ci, id_SI1);
+            disconnect_unused(&ci, id_SI2);
+        } else if (mode == "CKS") {
+            disconnect_unused(&ci, id_SI2);
+        } else if (mode == "MUX") {
+            // all used
+        } else
+            log_error("Unknown mode '%s' for cell '%s'.\n", mode.c_str(), ci.name.c_str(ctx));
+
+        if (net_driven_by(ctx, ci.getPort(id_SI1), is_gck, id_SO) ||
+            net_driven_by(ctx, ci.getPort(id_SI2), is_gck, id_SO) ||
+            net_driven_by(ctx, ci.getPort(id_CMD), is_gck, id_SO)) {
+            log_error("Cascaded GCKs are not allowed.\n");
+        }
+    }
+}
+
+void NgUltraPacker::pack_rams(void)
+{
+    log_info("Packing RAMs..\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_RAM))
+            continue;
+        ci.type = id_RAM;
+        bind_attr_loc(&ci, &ci.attrs);
+        // These ACKx and BCKx exists for NX_RAM, but are not available on NX_ULTRA
+        ci.disconnectPort(id_ACKC);
+        ci.disconnectPort(id_ACKD);
+        ci.disconnectPort(id_ACKR);
+        ci.disconnectPort(id_BCKC);
+        ci.disconnectPort(id_BCKD);
+        ci.disconnectPort(id_BCKR);
+        mandatory_param(&ci, id_raw_config0);
+        mandatory_param(&ci, id_raw_config1);
+        Property extr = ci.params[id_raw_config1].extract(0, 16);
+        std::vector<bool> bits = extr.as_bits();
+        // int ecc_mode = (bits[12] ? 1 : 0) | (bits[13] ? 2 : 0) | (bits[14] ? 4 : 0) | (bits[15] ? 8 : 0);
+        bool ecc = bits[12];
+        // int a_in_width = memory_width((bits[0] ? 1 : 0) | (bits[1] ? 2 : 0) | (bits[2] ? 4 : 0), ecc);
+        // int b_in_width = memory_width((bits[3] ? 1 : 0) | (bits[4] ? 2 : 0) | (bits[5] ? 4 : 0), ecc);
+        int a_out_width = memory_width((bits[6] ? 1 : 0) | (bits[7] ? 2 : 0) | (bits[8] ? 4 : 0), ecc);
+        int b_out_width = memory_width((bits[9] ? 1 : 0) | (bits[10] ? 2 : 0) | (bits[11] ? 4 : 0), ecc);
+
+        int a_addr = std::max(memory_addr_bits((bits[0] ? 1 : 0) | (bits[1] ? 2 : 0) | (bits[2] ? 4 : 0), ecc),
+                              memory_addr_bits((bits[6] ? 1 : 0) | (bits[7] ? 2 : 0) | (bits[8] ? 4 : 0), ecc));
+        int b_addr = std::max(memory_addr_bits((bits[3] ? 1 : 0) | (bits[4] ? 2 : 0) | (bits[5] ? 4 : 0), ecc),
+                              memory_addr_bits((bits[9] ? 1 : 0) | (bits[10] ? 2 : 0) | (bits[11] ? 4 : 0), ecc));
+
+        NetInfo *a_cs = ci.getPort(id_ACS);
+        if (!a_cs || a_cs->name.in(ctx->id("$PACKER_GND"))) {
+            // If there is no chip-select disconnect all
+            disconnect_unused(&ci, id_ACK);
+            for (int i = 0; i < 24; i++) {
+                disconnect_unused(&ci, ctx->idf("AI%d", i + 1));
+                disconnect_unused(&ci, ctx->idf("AO%d", i + 1));
+            }
+            for (int i = 0; i < 16; i++)
+                disconnect_unused(&ci, ctx->idf("AA%d", i + 1));
+        } else {
+            for (int i = a_out_width; i < 24; i++)
+                disconnect_unused(&ci, ctx->idf("AO%d", i + 1));
+            for (int i = a_addr; i < 16; i++)
+                disconnect_unused(&ci, ctx->idf("AA%d", i + 1));
+        }
+
+        NetInfo *b_cs = ci.getPort(id_BCS);
+        if (!b_cs || b_cs->name.in(ctx->id("$PACKER_GND"))) {
+            // If there is no chip-select disconnect all
+            disconnect_unused(&ci, id_BCK);
+            for (int i = 0; i < 24; i++) {
+                disconnect_unused(&ci, ctx->idf("BI%d", i + 1));
+                disconnect_unused(&ci, ctx->idf("BO%d", i + 1));
+            }
+            for (int i = 0; i < 16; i++)
+                disconnect_unused(&ci, ctx->idf("BA%d", i + 1));
+        } else {
+            for (int i = b_out_width; i < 24; i++)
+                disconnect_unused(&ci, ctx->idf("BO%d", i + 1));
+            for (int i = b_addr; i < 16; i++)
+                disconnect_unused(&ci, ctx->idf("BA%d", i + 1));
+        }
+
+        for (auto &p : ci.ports) {
+            if (p.second.type == PortType::PORT_IN)
+                disconnect_if_gnd(&ci, p.first);
+        }
+    }
+}
+
+void NgUltraPacker::dsp_same_driver(IdString port, CellInfo *cell, CellInfo **target)
+{
+    if (cell->getPort(port)) {
+        CellInfo *driver = cell->getPort(port)->driver.cell;
+        if (!driver->type.in(id_DSP, id_NX_DSP_U))
+            log_error("Port '%s' of '%s' can only be driven by DSP.\n", port.c_str(ctx), cell->name.c_str(ctx));
+        if (*target && *target != driver)
+            log_error("CAI1-24, CBI1-18, CZI1..56 and CCI must be from same DSP for '%s'.\n", cell->name.c_str(ctx));
+        *target = driver;
+    }
+}
+
+void NgUltraPacker::dsp_same_sink(IdString port, CellInfo *cell, CellInfo **target)
+{
+    if (cell->getPort(port)) {
+        if (cell->getPort(port)->users.entries() != 1)
+            log_error("Port '%s' of '%s' can only drive one DSP.\n", port.c_str(ctx), cell->name.c_str(ctx));
+        CellInfo *driver = (*cell->getPort(port)->users.begin()).cell;
+        if (!driver->type.in(id_DSP, id_NX_DSP_U))
+            log_error("Port '%s' of '%s' can only drive DSP.\n", port.c_str(ctx), cell->name.c_str(ctx));
+        if (*target && *target != driver)
+            log_error("CAI1-24, CBI1-18, CZI1..56 and CCI must be from same DSP for '%s'.\n", cell->name.c_str(ctx));
+        *target = driver;
+    }
+}
+
+void NgUltraPacker::pack_dsps(void)
+{
+    log_info("Packing DSPs..\n");
+    dict<IdString, CellInfo *> dsp_output;
+    std::vector<CellInfo *> root_dsps;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_NX_DSP_U))
+            continue;
+        ci.type = id_DSP;
+        bind_attr_loc(&ci, &ci.attrs);
+        mandatory_param(&ci, id_raw_config0);
+        mandatory_param(&ci, id_raw_config1);
+        mandatory_param(&ci, id_raw_config2);
+        mandatory_param(&ci, id_raw_config3);
+
+        for (auto &p : ci.ports) {
+            if (p.second.type == PortType::PORT_IN)
+                disconnect_if_gnd(&ci, p.first);
+        }
+
+        // CAI1-24, CBI1-18, CZI1..56 and CCI must be from same DSP
+        CellInfo *dsp = nullptr;
+        for (int i = 1; i <= 24; i++)
+            dsp_same_driver(ctx->idf("CAI%d", i), &ci, &dsp);
+        for (int i = 1; i <= 18; i++)
+            dsp_same_driver(ctx->idf("CBI%d", i), &ci, &dsp);
+        for (int i = 1; i <= 56; i++)
+            dsp_same_driver(ctx->idf("CZI%d", i), &ci, &dsp);
+        dsp_same_driver(id_CCI, &ci, &dsp);
+        if (!dsp)
+            root_dsps.push_back(&ci);
+
+        // CAO1-24, CBO1-18, CZO1..56 and CCO must go to same DSP
+        dsp = nullptr;
+        for (int i = 1; i <= 24; i++)
+            dsp_same_sink(ctx->idf("CAO%d", i), &ci, &dsp);
+        for (int i = 1; i <= 18; i++)
+            dsp_same_sink(ctx->idf("CBO%d", i), &ci, &dsp);
+        for (int i = 1; i <= 56; i++)
+            dsp_same_sink(ctx->idf("CZO%d", i), &ci, &dsp);
+        dsp_same_sink(id_CCO, &ci, &dsp);
+        if (dsp)
+            dsp_output.emplace(ci.name, dsp);
+    }
+    for (auto root : root_dsps) {
+        CellInfo *dsp = root;
+        if (dsp_output.count(dsp->name) == 0)
+            continue;
+        root->cluster = root->name;
+        while (true) {
+            if (dsp_output.count(dsp->name) == 0)
+                break;
+            dsp = dsp_output[dsp->name];
+            dsp->cluster = root->name;
+            root->constr_children.push_back(dsp);
+            dsp->constr_z = PLACE_DSP_CHAIN;
+        }
+    }
+}
+
+void NgUltraPacker::remove_not_used()
+{
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        for (auto &p : ci.ports) {
+            if (p.second.type == PortType::PORT_OUT) {
+                NetInfo *net = ci.getPort(p.first);
+                if (net && net->users.entries() == 0) {
+                    ci.disconnectPort(p.first);
+                }
+            }
+        }
+    }
+}
+
+void NgUltraImpl::pack()
+{
+    const ArchArgs &args = ctx->args;
+    if (args.options.count("csv")) {
+        parse_csv(args.options.at("csv"));
+    }
+
+    // Setup
+    NgUltraPacker packer(ctx, this);
+    packer.pack_constants();
+    packer.remove_not_used();
+    packer.update_lut_init();
+    packer.update_dffs();
+
+    // CGB
+    packer.pack_rams();
+    packer.pack_dsps();
+
+    // TILE
+    packer.pack_rfs();
+    packer.pack_cdcs();
+    packer.pack_fifos();
+    packer.pack_cys();
+    if (!args.options.count("no-xlut"))
+        packer.pack_xluts();
+    if (!args.options.count("no-lut-chains"))
+        packer.pack_lut_multi_dffs();
+    if (!args.options.count("no-dff-chains"))
+        packer.pack_dff_chains();
+    packer.pack_lut_dffs();
+    packer.pack_dffs();
+
+    // Tube
+    packer.pack_gcks();
+
+    // Ring
+    packer.pack_iobs();
+    packer.pack_ioms();
+    packer.pack_plls();
+    packer.pack_wfgs();
+    packer.insert_ioms();
+    packer.insert_wfbs();
+
+    packer.pre_place();
+}
+
+IdString NgUltraPacker::assign_wfg(IdString ckg, IdString ckg2, CellInfo *cell)
+{
+    for (auto &item : uarch->unused_wfg) {
+        BelId bel = item.first;
+        if (item.second == ckg || item.second == ckg2) {
+            IdString ckg = item.second;
+            uarch->unused_wfg.erase(bel);
+            log_info("    Using '%s:%s' for cell '%s'.\n", uarch->tile_name(bel.tile).c_str(),
+                     ctx->getBelName(bel)[1].c_str(ctx), cell->name.c_str(ctx));
+            ctx->bindBel(bel, cell, PlaceStrength::STRENGTH_LOCKED);
+            return ckg;
+        }
+    }
+    log_error("    No more available WFGs for cell '%s'.\n", cell->name.c_str(ctx));
+}
+
+void NgUltraPacker::extract_lowskew_signals(CellInfo *cell,
+                                            dict<IdString, dict<IdString, std::vector<PortRef>>> &lowskew_signals)
+{
+    IdString loc;
+    if (cell->bel != BelId())
+        loc = uarch->tile_name_id(cell->bel.tile);
+
+    PortRef ref;
+    ref.cell = cell;
+    auto &sinks = uarch->get_fabric_lowskew_sinks();
+    if (sinks.count(cell->type)) {
+        for (auto &port : sinks.at(cell->type)) {
+            NetInfo *clock = cell->getPort(port);
+            if (clock && !global_lowskew.count(clock->name)) {
+                ref.port = port;
+                lowskew_signals[loc][clock->name].push_back(ref);
+            }
+        }
+    }
+}
+
+void NgUltraPacker::pre_place(void)
+{
+    log_info("Pre-placing PLLs..\n");
+
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_PLL))
+            continue;
+        // Remove from list those that are used
+        if (ci.bel != BelId()) {
+            uarch->unused_pll.erase(ci.bel);
+        }
+    }
+    // First process those on dedicated clock pins
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_PLL) || ci.bel != BelId())
+            continue;
+
+        NetInfo *ref = ci.getPort(id_REF);
+        if (ref && ref->driver.cell && ref->driver.cell->type == id_IOM) {
+            IdString bank = uarch->tile_name_id(ref->driver.cell->bel.tile);
+            // bool found = false;
+            for (auto &item : uarch->unused_pll) {
+                BelId bel = item.first;
+                std::pair<IdString, IdString> &ckgs = uarch->bank_to_ckg[bank];
+                if (item.second == ckgs.first || item.second == ckgs.second) {
+                    uarch->unused_pll.erase(bel);
+                    log_info("    Using PLL in '%s' for cell '%s'.\n", uarch->tile_name(bel.tile).c_str(),
+                             ci.name.c_str(ctx));
+                    ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+                    // found = true;
+                    break;
+                }
+            }
+        }
+    }
+    // If PLL use any other pin, location is not relevant, so we pick available
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_PLL) || ci.bel != BelId())
+            continue;
+        if (uarch->unused_pll.empty())
+            log_error("    No more available PLLs for driving '%s'.\n", ci.name.c_str(ctx));
+        BelId bel = uarch->unused_pll.begin()->first;
+        uarch->unused_pll.erase(bel);
+        log_info("    Using PLL in '%s' for cell '%s'.\n", uarch->tile_name(bel.tile).c_str(), ci.name.c_str(ctx));
+        ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_LOCKED);
+    }
+
+    log_info("Pre-placing WFB/WFGs..\n");
+
+    std::vector<CellInfo *> root_wfgs;
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_WFG, id_WFB))
+            continue;
+        NetInfo *zi = ci.getPort(id_ZI);
+        if (!zi || !zi->driver.cell || !zi->driver.cell->type.in(id_WFG, id_WFB))
+            root_wfgs.push_back(&ci);
+    }
+
+    std::vector<std::vector<CellInfo *>> groups;
+    for (auto root : root_wfgs) {
+        std::vector<CellInfo *> group;
+        CellInfo *wfg = root;
+        group.push_back(wfg);
+        while (true) {
+            NetInfo *zo_net = wfg->getPort(id_ZO);
+            if (zo_net && zo_net->users.entries() > 0) {
+                wfg = (*zo_net->users.begin()).cell;
+                if (wfg->type.in(id_WFG, id_WFB)) {
+                    if (zo_net->users.entries() != 1)
+                        log_error("WFG can only be chained with one other WFG cell\n");
+                    group.push_back(wfg);
+                } else
+                    break;
+            } else
+                break;
+        }
+        groups.push_back(group);
+    }
+
+    // First pre-place those depending of PLL
+    for (auto &grp : groups) {
+        CellInfo *root = grp.front();
+        NetInfo *zi = root->getPort(id_ZI);
+        if (zi->driver.cell->type.in(id_PLL)) {
+            IdString ckg = uarch->tile_name_id(zi->driver.cell->bel.tile);
+            assign_wfg(ckg, IdString(), root);
+            for (int i = 1; i < int(grp.size()); i++) {
+                assign_wfg(ckg, IdString(), grp.at(i));
+            }
+        }
+    }
+    // Then those that depend on IOM
+    for (auto &grp : groups) {
+        CellInfo *root = grp.front();
+        NetInfo *zi = root->getPort(id_ZI);
+        if (zi->driver.cell->type.in(id_IOM)) {
+            IdString bank = uarch->tile_name_id(zi->driver.cell->bel.tile);
+            std::pair<IdString, IdString> &ckgs = uarch->bank_to_ckg[bank];
+            IdString ckg = assign_wfg(ckgs.first, ckgs.second, root);
+            for (int i = 1; i < int(grp.size()); i++) {
+                assign_wfg(ckg, IdString(), grp.at(i));
+            }
+        }
+    }
+    for (auto &grp : groups) {
+        CellInfo *root = grp.front();
+        if (root->bel != BelId())
+            continue;
+        // Assign first available
+        BelId bel = uarch->unused_pll.begin()->first;
+        IdString ckg = uarch->unused_pll.begin()->second;
+        uarch->unused_pll.erase(bel);
+        for (int i = 1; i < int(grp.size()); i++) {
+            assign_wfg(ckg, IdString(), grp.at(i));
+        }
+    }
+
+    dict<IdString, dict<IdString, std::vector<PortRef>>> lowskew_signals;
+    for (auto &cell : ctx->cells)
+        extract_lowskew_signals(cell.second.get(), lowskew_signals);
+
+    log_info("Adding GCK for lowskew signals..\n");
+    for (auto &n : lowskew_signals[IdString()]) {
+        NetInfo *net = ctx->nets.at(n.first).get();
+        if (net->driver.cell->type.in(id_BFR, id_DFR, id_DDFR)) {
+            CellInfo *bfr = net->driver.cell;
+            CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$csc", bfr->name.c_str(ctx)));
+            gck_cell->params[id_std_mode] = Property("CSC");
+            NetInfo *new_out = ctx->createNet(ctx->idf("%s$bfr", bfr->name.c_str(ctx)));
+            NetInfo *old = bfr->getPort(id_O);
+            bfr->disconnectPort(id_O);
+            gck_cell->connectPort(id_SO, old);
+            gck_cell->connectPort(id_CMD, new_out);
+            bfr->connectPort(id_O, new_out);
+            log_info("    Create GCK '%s' for signal '%s'\n", gck_cell->name.c_str(ctx), n.first.c_str(ctx));
+        }
+        if (net->driver.cell->type.in(id_BEYOND_FE)) {
+            CellInfo *fe = net->driver.cell;
+            if (!fe->params.count(id_lut_table))
+                continue;
+            if (fe->params.count(id_dff_used))
+                continue;
+            if (fe->params[id_lut_table] != Property(0x5555, 16))
+                continue;
+            if (!fe->getPort(id_I1))
+                continue;
+            CellInfo *bfr = fe->getPort(id_I1)->driver.cell;
+            if (bfr->type.in(id_BFR, id_DFR, id_DDFR)) {
+                CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$csc", bfr->name.c_str(ctx)));
+                gck_cell->params[id_std_mode] = Property("CSC");
+                gck_cell->params[id_inv_out] = Property(true);
+                NetInfo *old_out = fe->getPort(id_LO);
+                NetInfo *old_in = fe->getPort(id_I1);
+                fe->disconnectPort(id_LO);
+                fe->disconnectPort(id_I1);
+                gck_cell->connectPort(id_SO, old_out);
+                gck_cell->connectPort(id_CMD, old_in);
+                packed_cells.insert(fe->name);
+                log_info("    Create GCK '%s' for signal '%s'\n", gck_cell->name.c_str(ctx), n.first.c_str(ctx));
+            }
+        }
+    }
+    flush_cells();
+}
+
+void NgUltraImpl::disable_beyond_fe_s_output(BelId bel)
+{
+    WireId dwire = ctx->getBelPinWire(bel, id_DO);
+    for (PipId pip : ctx->getPipsDownhill(dwire)) {
+        for (PipId pip2 : ctx->getPipsDownhill(ctx->getPipDstWire(pip))) {
+            IdString dst = ctx->getWireName(ctx->getPipDstWire(pip2))[1];
+            if (boost::ends_with(dst.c_str(ctx), ".DS")) {
+                blocked_pips.emplace(pip2);
+                return;
+            }
+        }
+    }
+}
+
+void NgUltraImpl::postPlace()
+{
+    log_break();
+    log_info("Limiting routing...\n");
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (ci.type == id_BEYOND_FE) {
+            const auto &extra_data = *bel_extra_data(ci.bel);
+            // Check if CSC mode only if FE is capable
+            if ((extra_data.flags & BEL_EXTRA_FE_CSC)) {
+                if (str_or_default(ci.params, id_type, "") == "CSC")
+                    continue;
+                // Disable routing to S output if CSC is not used
+                disable_beyond_fe_s_output(ci.bel);
+            }
+        } else if (ci.type == id_CY) {
+            // In case A input is actually used, but it is connectd to GND
+            // it is considered that signal is comming from RI1 crossbar.
+            // We need to prevent router to use that crossbar output for
+            // any other signal.
+            for (int i = 1; i <= 4; i++) {
+                IdString port = ctx->idf("A%d", i);
+                NetInfo *net = ci.getPort(port);
+                if (!net)
+                    continue;
+                if (net->name.in(ctx->id("$PACKER_GND"))) {
+                    WireId dwire = ctx->getBelPinWire(ci.bel, port);
+                    for (PipId pip : ctx->getPipsUphill(dwire)) {
+                        WireId src = ctx->getPipSrcWire(pip);
+                        const std::string src_name = ctx->getWireName(src)[1].str(ctx);
+                        if (boost::starts_with(src_name, "RI1")) {
+                            for (PipId pip2 : ctx->getPipsDownhill(src)) {
+                                blocked_pips.emplace(pip2);
+                            }
+                        }
+                    }
+                    ci.disconnectPort(port); // Disconnect A
+                }
+            }
+        }
+    }
+    remove_constants();
+
+    const ArchArgs &args = ctx->args;
+    NgUltraPacker packer(ctx, this);
+    log_break();
+    log_info("Running post-placement ...\n");
+    packer.duplicate_gck();
+    packer.insert_bypass_gck();
+    if (!args.options.count("no-csc-insertion"))
+        packer.insert_csc();
+    log_break();
+    ctx->assignArchInfo();
+}
+
+BelId NgUltraPacker::getCSC(Loc l, int row)
+{
+    const int z_loc[] = {0, 15, 16, 31};
+    for (int j = 0; j < 3; j++) {
+        for (int i = 0; i < 4; i++) {
+            BelId bel = ctx->getBelByLocation(Loc(l.x + j + 1, l.y + j % 2 + 2, z_loc[i]));
+            if (!ctx->getBoundBelCell(bel) && (row == 0 || row == (i + 1)))
+                return bel;
+        }
+    }
+    return BelId();
+}
+
+void NgUltraPacker::insert_csc()
+{
+    dict<IdString, dict<IdString, std::vector<PortRef>>> local_system_matrix;
+    log_info("Inserting CSCs...\n");
+    int insert_new_csc = 0, change_to_csc = 0;
+    for (auto &cell : ctx->cells) {
+        auto ci = cell.second.get();
+        if (ci->bel != BelId()) {
+            if (uarch->tile_type(ci->bel.tile) == TILE_EXTRA_FABRIC) {
+                extract_lowskew_signals(ci, local_system_matrix);
+            }
+        }
+    }
+    for (auto &lsm : local_system_matrix) {
+        std::string name = lsm.first.c_str(ctx);
+        Loc loc = uarch->tile_locations[name];
+        std::vector<std::pair<int, IdString>> fanout;
+        for (auto &n : lsm.second) {
+            fanout.push_back(std::make_pair(n.second.size(), n.first));
+        }
+        std::sort(fanout.begin(), fanout.end(), std::greater<std::pair<int, IdString>>());
+        int available_csc = 12;
+        for (std::size_t i = 0; i < std::min<std::size_t>(fanout.size(), available_csc); i++) {
+            auto &n = fanout.at(i);
+
+            NetInfo *net = ctx->nets.at(n.second).get();
+            CellInfo *cell = net->driver.cell;
+            if (uarch->tile_name(cell->bel.tile) == lsm.first.c_str(ctx) && !cell->params.count(id_dff_used) &&
+                cell->cluster == ClusterId()) {
+                BelId newbel = getCSC(loc, 0);
+                if (newbel == BelId())
+                    break;
+
+                ctx->unbindBel(cell->bel);
+                cell->disconnectPort(id_LO);
+                NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", cell->name.c_str(ctx)));
+                cell->params[id_CSC] = Property(Property::State::S1);
+                cell->params[id_type] = Property("CSC");
+                cell->params[id_dff_used] = Property(1, 1);
+                cell->connectPort(id_LO, new_out);
+                cell->connectPort(id_DI, new_out);
+
+                cell->connectPort(id_DO, net);
+                ctx->bindBel(newbel, cell, PlaceStrength::STRENGTH_LOCKED);
+                change_to_csc++;
+                continue;
+            }
+            Loc cell_loc = ctx->getBelLocation(cell->bel);
+            BelId newbel = getCSC(loc, (cell_loc.y & 3) + 1); // Take CSC from pefered row
+            if (newbel == BelId())
+                newbel = getCSC(loc, 0); // Try getting any other CSC
+            if (newbel == BelId())
+                break;
+            if (lsm.second[n.second].size() < 4)
+                break;
+
+            CellInfo *fe =
+                    create_cell_ptr(id_BEYOND_FE, ctx->idf("%s$%s$csc", net->name.c_str(ctx), lsm.first.c_str(ctx)));
+            NetInfo *new_out = ctx->createNet(ctx->idf("%s$o", fe->name.c_str(ctx)));
+            fe->params[id_lut_table] = Property(0xaaaa, 16);
+            fe->params[id_lut_used] = Property(1, 1);
+            fe->params[id_CSC] = Property(Property::State::S1);
+            fe->params[id_type] = Property("CSC");
+            fe->params[id_dff_used] = Property(1, 1);
+            fe->connectPort(id_I1, net);
+            fe->connectPort(id_DO, new_out);
+            insert_new_csc++;
+
+            for (auto &conn : lsm.second[n.second])
+                conn.cell->disconnectPort(conn.port);
+            for (auto &conn : lsm.second[n.second])
+                conn.cell->connectPort(conn.port, new_out);
+
+            ctx->bindBel(newbel, fe, PlaceStrength::STRENGTH_LOCKED);
+        }
+    }
+    if (insert_new_csc)
+        log_info("    %6d FEs inserted as CSC\n", insert_new_csc);
+    if (change_to_csc)
+        log_info("    %6d FEs converted to CSC\n", change_to_csc);
+}
+BelId NgUltraPacker::get_available_gck(int lobe, NetInfo *si1, NetInfo *si2)
+{
+    auto &gcks = uarch->gck_per_lobe[lobe];
+    for (int i = 0; i < 20; i++) {
+        auto &g = gcks.at(i);
+        if (g.used)
+            continue;
+        if (si1 && g.si1 != IdString() && g.si1 != si1->name)
+            continue;
+        if (si2 && g.si2 != IdString() && g.si2 != si2->name)
+            continue;
+        if (si1)
+            g.si1 = si1->name;
+        if (si2)
+            g.si2 = si2->name;
+        g.used = true;
+        if (i % 2 == 0) {
+            // next GCK share inputs in reverse order
+            if (si2)
+                gcks.at(i + 1).si1 = si2->name;
+            if (si1)
+                gcks.at(i + 1).si2 = si1->name;
+        }
+        return g.bel;
+    }
+    log_error("No GCK left to promote lowskew signal.\n");
+    return BelId();
+}
+
+void NgUltraPacker::duplicate_gck()
+{
+    // Unbind all GCKs that are inserted
+    for (auto &cell : ctx->cells) {
+        CellInfo &ci = *cell.second;
+        if (!ci.type.in(id_GCK))
+            continue;
+        ctx->unbindBel(ci.bel);
+    }
+
+    log_info("Duplicating existing GCKs...\n");
+    for (auto &net : ctx->nets) {
+        NetInfo *glb_net = net.second.get();
+        if (!glb_net->driver.cell)
+            continue;
+
+        if (!uarch->is_tube_clock_source(glb_net->driver))
+            continue;
+
+        log_info("    Lowskew signal '%s'\n", glb_net->name.c_str(ctx));
+        dict<int, std::vector<PortRef>> connections;
+        for (const auto &usr : glb_net->users) {
+            if (uarch->is_fabric_lowskew_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
+                if (usr.cell->bel == BelId()) {
+                    log_error("Cell '%s' not placed\n", usr.cell->name.c_str(ctx));
+                }
+                int lobe = uarch->tile_lobe(usr.cell->bel.tile);
+                if (lobe > 0) {
+                    connections[lobe].push_back(usr);
+                    usr.cell->disconnectPort(usr.port);
+                }
+            }
+        }
+        int cnt = 0;
+        CellInfo *driver = glb_net->driver.cell;
+        NetInfo *si1 = driver->getPort(id_SI1);
+        NetInfo *si2 = driver->getPort(id_SI2);
+        NetInfo *cmd = driver->getPort(id_CMD);
+        for (auto &conn : connections) {
+            BelId bel = get_available_gck(conn.first, si1, si2);
+            CellInfo *gck_cell = nullptr;
+            if (cnt == 0) {
+                gck_cell = driver;
+                log_info("        Assign GCK '%s' to lobe %d\n", gck_cell->name.c_str(ctx), conn.first);
+            } else {
+                gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$gck_%d", driver->name.c_str(ctx), conn.first));
+                log_info("        Create GCK '%s' for lobe %d\n", gck_cell->name.c_str(ctx), conn.first);
+                for (auto &params : driver->params)
+                    gck_cell->params[params.first] = params.second;
+                if (si1)
+                    gck_cell->connectPort(id_SI1, si1);
+                if (si2)
+                    gck_cell->connectPort(id_SI2, si2);
+                if (cmd)
+                    gck_cell->connectPort(id_CMD, cmd);
+            }
+            gck_cell->disconnectPort(id_SO);
+            NetInfo *new_clk = ctx->createNet(ctx->id(gck_cell->name.str(ctx)));
+            gck_cell->connectPort(id_SO, new_clk);
+            for (const auto &usr : conn.second) {
+                CellInfo *cell = usr.cell;
+                IdString port = usr.port;
+                cell->connectPort(port, new_clk);
+            }
+            global_lowskew.emplace(new_clk->name);
+            ctx->bindBel(bel, gck_cell, PlaceStrength::STRENGTH_LOCKED);
+            cnt++;
+        }
+    }
+}
+
+void NgUltraPacker::insert_bypass_gck()
+{
+    log_info("Inserting bypass GCKs...\n");
+    for (auto &net : ctx->nets) {
+        NetInfo *glb_net = net.second.get();
+        if (!glb_net->driver.cell)
+            continue;
+
+        if (!uarch->is_ring_clock_source(glb_net->driver))
+            continue;
+
+        log_info("    Lowskew signal '%s'\n", glb_net->name.c_str(ctx));
+        dict<int, std::vector<PortRef>> connections;
+        for (const auto &usr : glb_net->users) {
+            if (uarch->is_fabric_lowskew_sink(usr) || uarch->is_ring_over_tile_clock_sink(usr)) {
+                if (usr.cell->bel == BelId()) {
+                    log_error("Cell '%s' not placed\n", usr.cell->name.c_str(ctx));
+                }
+                int lobe = uarch->tile_lobe(usr.cell->bel.tile);
+                if (lobe > 0) {
+                    connections[lobe].push_back(usr);
+                    usr.cell->disconnectPort(usr.port);
+                }
+            }
+        }
+        for (auto &conn : connections) {
+            BelId bel = get_available_gck(conn.first, glb_net, nullptr);
+
+            log_info("        Create GCK for lobe %d\n", conn.first);
+            CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$gck_%d", glb_net->name.c_str(ctx), conn.first));
+            gck_cell->params[id_std_mode] = Property("BYPASS");
+            gck_cell->connectPort(id_SI1, glb_net);
+            NetInfo *new_clk = ctx->createNet(ctx->id(gck_cell->name.str(ctx)));
+            gck_cell->connectPort(id_SO, new_clk);
+            for (const auto &usr : conn.second) {
+                CellInfo *cell = usr.cell;
+                IdString port = usr.port;
+                cell->connectPort(port, new_clk);
+            }
+            global_lowskew.emplace(new_clk->name);
+            ctx->bindBel(bel, gck_cell, PlaceStrength::STRENGTH_LOCKED);
+        }
+    }
+}
+NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/uarch/ng-ultra/pack.h b/himbaechel/uarch/ng-ultra/pack.h
new file mode 100644
index 0000000000..09a99fa20d
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/pack.h
@@ -0,0 +1,131 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <boost/optional.hpp>
+#include <iterator>
+#include <queue>
+#include <unordered_set>
+#include "chain_utils.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "ng_ultra.h"
+
+#ifndef NG_ULTRA_PACK_H
+#define NG_ULTRA_PACK_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
+struct NgUltraPacker
+{
+    NgUltraPacker(Context *ctx, NgUltraImpl *uarch) : ctx(ctx), uarch(uarch) { h.init(ctx); };
+
+    void remove_not_used();
+    // Constants
+    void pack_constants();
+    void remove_constants();
+
+    // LUTs & FFs
+    void update_lut_init();
+    void update_dffs();
+    void pack_xluts();
+    void pack_lut_multi_dffs();
+    void pack_dff_chains();
+    void pack_lut_dffs();
+    void pack_dffs();
+    void pack_cys();
+    void pack_rfs();
+    void pack_cdcs();
+    void pack_fifos();
+
+    void pack_rams();
+    void pack_dsps();
+
+    // IO
+    void pack_iobs();
+    void pack_ioms();
+
+    void pack_gcks();
+    void pack_plls();
+    void pack_wfgs();
+    void pre_place();
+
+    void insert_ioms();
+    void insert_wfbs();
+
+    // Post placement
+    void duplicate_gck();
+    void insert_bypass_gck();
+    void insert_csc();
+
+    /* clang-format off */
+TESTABLE_PRIVATE:
+    void set_lut_input_if_constant(CellInfo *cell, IdString input);
+    /* clang-format on */
+    void lut_to_fe(CellInfo *lut, CellInfo *fe, bool no_dff, Property lut_table);
+    void dff_to_fe(CellInfo *dff, CellInfo *fe, bool pass_thru_lut);
+    void dff_rewrite(CellInfo *cell);
+    void ddfr_rewrite(CellInfo *cell);
+
+    void exchange_if_constant(CellInfo *cell, IdString input1, IdString input2);
+    void pack_cy_input_and_output(CellInfo *cy, IdString cluster, IdString in_port, IdString out_port, int placer,
+                                  int &lut_only, int &lut_and_ff, int &dff_only);
+
+    void pack_xrf_input_and_output(CellInfo *cy, IdString cluster, IdString in_port, IdString out_port,
+                                   ClusterPlacement placement, int &lut_only, int &lut_and_ff, int &dff_only);
+
+    void connect_gnd_if_unconnected(CellInfo *cell, IdString input, bool warn);
+    void disconnect_if_gnd(CellInfo *cell, IdString input);
+
+    void insert_wfb(CellInfo *cell, IdString port);
+
+    void mandatory_param(CellInfo *cell, IdString param);
+    void disconnect_unused(CellInfo *cell, IdString port);
+    void bind_attr_loc(CellInfo *cell, dict<IdString, Property> *attrs);
+    BelId get_available_gck(int lobe, NetInfo *si1, NetInfo *si2);
+    BelId getCSC(Loc l, int row);
+    // General helper functions
+    void flush_cells();
+
+    IdString assign_wfg(IdString ckg, IdString ckg2, CellInfo *cell);
+    void dsp_same_driver(IdString port, CellInfo *cell, CellInfo **target);
+    void dsp_same_sink(IdString port, CellInfo *cell, CellInfo **target);
+
+    int make_init_with_const_input(int init, int input, bool value);
+
+    int memory_width(int config, bool ecc);
+    int memory_addr_bits(int config, bool ecc);
+
+    void constrain_location(CellInfo *cell);
+    void extract_lowskew_signals(CellInfo *cell, dict<IdString, dict<IdString, std::vector<PortRef>>> &lowskew_signals);
+    // Cell creating
+    CellInfo *create_cell_ptr(IdString type, IdString name);
+
+    Context *ctx;
+    NgUltraImpl *uarch;
+
+    pool<IdString> packed_cells;
+    pool<IdString> global_lowskew;
+
+    HimbaechelHelpers h;
+};
+
+NEXTPNR_NAMESPACE_END
+#endif
diff --git a/himbaechel/uarch/ng-ultra/tests/lut_dff.cc b/himbaechel/uarch/ng-ultra/tests/lut_dff.cc
new file mode 100644
index 0000000000..87cce6fffc
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/tests/lut_dff.cc
@@ -0,0 +1,161 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <vector>
+#include "command.h"
+#include "gtest/gtest.h"
+#include "nextpnr.h"
+#include "uarch/ng-ultra/ng_ultra.h"
+#include "uarch/ng-ultra/pack.h"
+#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
+#include "himbaechel_constids.h"
+
+USING_NEXTPNR_NAMESPACE
+
+class NGUltraLutDffTest : public ::testing::Test
+{
+  protected:
+    virtual void SetUp()
+    {
+        init_share_dirname();
+        chipArgs.device = "NG-ULTRA";
+        ctx = new Context(chipArgs);
+        ctx->uarch->init(ctx);
+        ctx->late_init();
+        impl = (NgUltraImpl *)(ctx->uarch.get());
+    }
+
+    virtual void TearDown() { delete ctx; }
+
+    int const_autoidx = 0;
+    NetInfo *add_constant_driver(const char *name, char constval)
+    {
+        IdString cell_name = ctx->idf("%s%s%d", name, (constval == '1' ? "$VCC$" : "$GND$"), const_autoidx++);
+        CellInfo *cc = ctx->createCell(cell_name, ctx->id(constval == '1' ? "VCC" : "GND"));
+        cc->ports[ctx->id("Y")].name = ctx->id("Y");
+        cc->ports[ctx->id("Y")].type = PORT_OUT;
+        NetInfo *net = ctx->createNet(cell_name);
+        cc->connectPort(ctx->id("Y"), net);
+        return net;
+    }
+
+    void add_port(CellInfo *cell, const std::string &name, PortType dir)
+    {
+        IdString id = ctx->id(name);
+        cell->ports[id].name = id;
+        cell->ports[id].type = dir;
+    };
+
+    int evaluate_lut(int I1, int I2, int I3, int I4, int lut_table)
+    {
+        int S1 = I4 ? (lut_table >> 8) & 0xff : lut_table & 0xff;
+        int S2 = I3 ? (S1 >> 4 & 0xf) : S1 & 0xf;
+        int S3 = I2 ? (S2 >> 2 & 0x3) : S2 & 0x3;
+        int O = I1 ? (S3 >> 1 & 0x1) : S3 & 0x1;
+        return O;
+    }
+
+    ArchArgs chipArgs;
+    Context *ctx;
+    NgUltraImpl *impl;
+};
+
+TEST_F(NGUltraLutDffTest, pack_constants)
+{
+    NgUltraPacker packer(ctx, impl);
+    packer.pack_constants();
+    ASSERT_EQ(ctx->cells.size(), 2LU);
+}
+
+TEST_F(NGUltraLutDffTest, remove_constants)
+{
+    NgUltraPacker packer(ctx, impl);
+    packer.pack_constants();
+    impl->remove_constants();
+    ASSERT_EQ(ctx->cells.size(), 0LU);
+}
+
+TEST_F(NGUltraLutDffTest, remove_unused_gnd)
+{
+    NgUltraPacker packer(ctx, impl);
+    CellInfo *cell = ctx->createCell(ctx->id("TEST"), id_NX_LUT);
+    add_port(cell, "I1", PORT_IN);
+    add_port(cell, "I2", PORT_IN);
+    add_port(cell, "I3", PORT_IN);
+    add_port(cell, "I4", PORT_IN);
+    cell->connectPort(id_I1, add_constant_driver("TEST", '1'));
+    cell->connectPort(id_I2, add_constant_driver("TEST", '1'));
+    cell->connectPort(id_I3, add_constant_driver("TEST", '1'));
+
+    ASSERT_EQ(ctx->cells.size(), 4LU);
+    packer.pack_constants();
+    ASSERT_EQ(ctx->cells.size(), 3LU);
+    impl->remove_constants();
+    ASSERT_EQ(ctx->cells.size(), 2LU);
+    ASSERT_EQ(ctx->cells.find(ctx->id("$PACKER_GND_DRV")), ctx->cells.end());
+    ASSERT_NE(ctx->cells.find(ctx->id("$PACKER_VCC_DRV")), ctx->cells.end());
+    ASSERT_EQ(ctx->nets.find(ctx->id("$PACKER_GND")), ctx->nets.end());
+    ASSERT_NE(ctx->nets.find(ctx->id("$PACKER_VCC")), ctx->nets.end());
+}
+
+TEST_F(NGUltraLutDffTest, remove_unused_vcc)
+{
+    NgUltraPacker packer(ctx, impl);
+    CellInfo *cell = ctx->createCell(ctx->id("TEST"), id_NX_LUT);
+    add_port(cell, "I1", PORT_IN);
+    add_port(cell, "I2", PORT_IN);
+    add_port(cell, "I3", PORT_IN);
+    add_port(cell, "I4", PORT_IN);
+    cell->connectPort(id_I1, add_constant_driver("TEST", '0'));
+    cell->connectPort(id_I2, add_constant_driver("TEST", '0'));
+    cell->connectPort(id_I3, add_constant_driver("TEST", '0'));
+
+    ASSERT_EQ(ctx->cells.size(), 4LU);
+    packer.pack_constants();
+    ASSERT_EQ(ctx->cells.size(), 3LU);
+    impl->remove_constants();
+    ASSERT_EQ(ctx->cells.size(), 2LU);
+    ASSERT_NE(ctx->cells.find(ctx->id("$PACKER_GND_DRV")), ctx->cells.end());
+    ASSERT_EQ(ctx->cells.find(ctx->id("$PACKER_VCC_DRV")), ctx->cells.end());
+    ASSERT_NE(ctx->nets.find(ctx->id("$PACKER_GND")), ctx->nets.end());
+    ASSERT_EQ(ctx->nets.find(ctx->id("$PACKER_VCC")), ctx->nets.end());
+}
+
+TEST_F(NGUltraLutDffTest, make_init_with_const_input)
+{
+    NgUltraPacker packer(ctx, impl);
+    for (int lut_table = 0; lut_table < 0x10000; lut_table++) {
+        for (int lut = 0; lut < 16; lut++) {
+            int I4 = (lut & 8) ? 1 : 0;
+            int I3 = (lut & 4) ? 1 : 0;
+            int I2 = (lut & 2) ? 1 : 0;
+            int I1 = (lut & 1) ? 1 : 0;
+
+            int tab1 = packer.make_init_with_const_input(lut_table, 0, I1);
+            int tab2 = packer.make_init_with_const_input(tab1, 1, I2);
+            int tab3 = packer.make_init_with_const_input(tab2, 2, I3);
+            int tab4 = packer.make_init_with_const_input(tab3, 3, I4);
+
+            ASSERT_EQ(evaluate_lut(I1, I2, I3, I4, lut_table), evaluate_lut(I1, I2, I3, I4, tab1));
+            ASSERT_EQ(evaluate_lut(I1, I2, I3, I4, lut_table), evaluate_lut(I1, I2, I3, I4, tab2));
+            ASSERT_EQ(evaluate_lut(I1, I2, I3, I4, lut_table), evaluate_lut(I1, I2, I3, I4, tab3));
+            ASSERT_EQ(evaluate_lut(I1, I2, I3, I4, lut_table), evaluate_lut(I1, I2, I3, I4, tab4));
+        }
+    }
+}
diff --git a/himbaechel/uarch/ng-ultra/tests/main.cc b/himbaechel/uarch/ng-ultra/tests/main.cc
new file mode 100644
index 0000000000..92e027f29f
--- /dev/null
+++ b/himbaechel/uarch/ng-ultra/tests/main.cc
@@ -0,0 +1,32 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2024  The Project Beyond Authors.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <vector>
+#include "gtest/gtest.h"
+#include "log.h"
+
+USING_NEXTPNR_NAMESPACE
+
+int main(int argc, char **argv)
+{
+    // TODO: Remove for delivery, useful while checking tests
+    log_streams.push_back(std::make_pair(&std::cerr, LogLevel::LOG_MSG));
+    ::testing::InitGoogleTest(&argc, argv);
+    return RUN_ALL_TESTS();
+}

From d810aac8676b9b4af0f4a1145bcfe9ac2a0b102e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Thu, 5 Dec 2024 13:59:33 +0100
Subject: [PATCH 707/712] Add GroupId related calls to Himbaechel API (#1399)

* Add GroupId related calls to Himbaechel API

* Example uarch using new API features

* Update drawGroup to propagate only GroupId
---
 common/kernel/base_arch.h                    |   3 +-
 himbaechel/arch.cc                           |  39 ++-
 himbaechel/arch.h                            |  74 +++++
 himbaechel/archdefs.h                        |  28 +-
 himbaechel/chipdb.h                          |  12 +
 himbaechel/himbaechel_api.cc                 |   5 +-
 himbaechel/himbaechel_api.h                  |   9 +-
 himbaechel/himbaechel_dbgen/chip.py          |  71 ++++-
 himbaechel/himbaechel_gfxids.h               |   2 +-
 himbaechel/uarch/example/constids.inc        |   2 +
 himbaechel/uarch/example/example.cc          | 289 ++++++++++---------
 himbaechel/uarch/example/example_arch_gen.py |   2 +
 12 files changed, 377 insertions(+), 159 deletions(-)

diff --git a/common/kernel/base_arch.h b/common/kernel/base_arch.h
index 2929bcba98..96f1d804c8 100644
--- a/common/kernel/base_arch.h
+++ b/common/kernel/base_arch.h
@@ -443,7 +443,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
     }
 
     // Routing methods
-    virtual void expandBoundingBox(BoundingBox &bb) const override {
+    virtual void expandBoundingBox(BoundingBox &bb) const override
+    {
         bb.x0 = std::max(bb.x0 - 1, 0);
         bb.y0 = std::max(bb.y0 - 1, 0);
         bb.x1 = std::min(bb.x1 + 1, this->getGridDimX());
diff --git a/himbaechel/arch.cc b/himbaechel/arch.cc
index 9ae9225e00..dccf285e29 100644
--- a/himbaechel/arch.cc
+++ b/himbaechel/arch.cc
@@ -33,7 +33,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static constexpr int database_version = 5;
+static constexpr int database_version = 6;
 
 static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
 
@@ -307,6 +307,23 @@ IdStringList Arch::getPipName(PipId pip) const
 
 IdString Arch::getPipType(PipId pip) const { return IdString(); }
 
+GroupId Arch::getGroupByName(IdStringList name) const
+{
+    NPNR_ASSERT(name.size() == 2);
+    int tile = tile_name2idx.at(name[0]);
+    const auto &tdata = chip_tile_info(chip_info, tile);
+    for (int group = 0; group < tdata.groups.ssize(); group++) {
+        if (IdString(tdata.groups[group].name) == name[1])
+            return GroupId(tile, group);
+    }
+    return GroupId();
+}
+
+IdStringList Arch::getGroupName(GroupId group) const
+{
+    return IdStringList::concat(tile_name.at(group.tile), IdString(chip_group_info(chip_info, group).name));
+}
+
 std::string Arch::getChipName() const { return chip_info->name.get(); }
 
 IdString Arch::archArgsToId(ArchArgs args) const
@@ -504,15 +521,21 @@ IdString Arch::get_tile_type(int tile) const
 std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
 {
     std::vector<GraphicElement> ret;
-    if (decal.type == DecalId::TYPE_BEL) {
+    if (decal.type == DecalId::TYPE_GROUP) {
+        GroupId group(decal.tile, decal.index);
+        Loc loc;
+        tile_xy(chip_info, decal.tile, loc.x, loc.y);
+        uarch->drawGroup(ret, group, loc);
+    } else if (decal.type == DecalId::TYPE_BEL) {
         BelId bel(decal.tile, decal.index);
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
         uarch->drawBel(ret, style, getBelType(bel), getBelLocation(bel));
     } else if (decal.type == DecalId::TYPE_WIRE) {
         WireId w(decal.tile, decal.index);
-        for (WireId wire: get_tile_wire_range(w)) {
+        for (WireId wire : get_tile_wire_range(w)) {
             auto wire_type = getWireType(wire);
-            GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+            GraphicElement::style_t style =
+                    decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
             Loc loc;
             tile_xy(chip_info, wire.tile, loc.x, loc.y);
             int32_t tilewire = chip_wire_info(chip_info, wire).tile_wire;
@@ -526,7 +549,8 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         int32_t src_id = chip_wire_info(chip_info, src_wire).tile_wire;
         int32_t dst_id = chip_wire_info(chip_info, dst_wire).tile_wire;
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
-        uarch->drawPip(ret, style, loc, src_wire, getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire), dst_id);
+        uarch->drawPip(ret, style, loc, src_wire, getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire),
+                       dst_id);
     }
     return ret;
 }
@@ -557,7 +581,10 @@ DecalXY Arch::getPipDecal(PipId pip) const
 
 DecalXY Arch::getGroupDecal(GroupId group) const
 {
-    return DecalXY();
+    DecalXY decalxy;
+    decalxy.decal = DecalId(group.tile, group.index, DecalId::TYPE_GROUP);
+    decalxy.decal.active = true;
+    return decalxy;
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/himbaechel/arch.h b/himbaechel/arch.h
index ca965c8625..29f5cb8d50 100644
--- a/himbaechel/arch.h
+++ b/himbaechel/arch.h
@@ -49,6 +49,10 @@ inline const PipDataPOD &chip_pip_info(const ChipInfoPOD *chip, PipId pip)
 {
     return chip_tile_info(chip, pip.tile).pips[pip.index];
 }
+inline const GroupDataPOD &chip_group_info(const ChipInfoPOD *chip, GroupId group)
+{
+    return chip_tile_info(chip, group.tile).groups[group.index];
+}
 inline const TileRoutingShapePOD &chip_tile_shape(const ChipInfoPOD *chip, int tile)
 {
     return chip->tile_shapes[chip->tile_insts[tile].shape];
@@ -332,6 +336,41 @@ template <RelSlice<int32_t> TileWireDataPOD::*ptr> struct UpDownhillPipRange
 
 // -----------------------------------------------------------------------
 
+template <typename Tid, RelSlice<int32_t> GroupDataPOD::*ptr> struct GroupObjIterator
+{
+    const GroupDataPOD &group;
+    int tile = -1;
+    int cursor = -1;
+
+    GroupObjIterator(const GroupDataPOD &group, int tile, int cursor) : group(group), tile(tile), cursor(cursor) {};
+
+    void operator++() { cursor++; }
+
+    bool operator!=(const GroupObjIterator<Tid, ptr> &other) const
+    {
+        return tile != other.tile || cursor != other.cursor;
+    }
+
+    bool operator==(const GroupObjIterator<Tid, ptr> &other) const
+    {
+        return tile == other.tile && cursor == other.cursor;
+    }
+
+    Tid operator*() const { return Tid(tile, (group.*ptr)[cursor]); }
+};
+
+template <typename Tid, RelSlice<int32_t> GroupDataPOD::*ptr> struct GroupObjRange
+{
+    using iterator = GroupObjIterator<Tid, ptr>;
+    GroupObjRange(const GroupDataPOD &group, int tile) : b(group, tile, 0), e(group, tile, (group.*ptr).ssize()) {}
+
+    iterator b, e;
+    iterator begin() const { return b; }
+    iterator end() const { return e; }
+};
+
+// -----------------------------------------------------------------------
+
 struct BelPinIterator
 {
     const ChipInfoPOD *chip;
@@ -393,10 +432,16 @@ struct ArchArgs
 
 typedef TileObjRange<BelId, BelDataPOD, &TileTypePOD::bels> BelRange;
 typedef TileObjRange<PipId, PipDataPOD, &TileTypePOD::pips> AllPipRange;
+typedef TileObjRange<GroupId, GroupDataPOD, &TileTypePOD::groups> GroupRange;
 
 typedef UpDownhillPipRange<&TileWireDataPOD::pips_uphill> UphillPipRange;
 typedef UpDownhillPipRange<&TileWireDataPOD::pips_downhill> DownhillPipRange;
 
+typedef GroupObjRange<BelId, &GroupDataPOD::group_bels> GroupBelRange;
+typedef GroupObjRange<WireId, &GroupDataPOD::group_wires> GroupWireRange;
+typedef GroupObjRange<PipId, &GroupDataPOD::group_pips> GroupPipRange;
+typedef GroupObjRange<GroupId, &GroupDataPOD::group_groups> GroupGroupRange;
+
 struct ArchRanges : BaseArchRanges
 {
     using ArchArgsT = ArchArgs;
@@ -412,6 +457,12 @@ struct ArchRanges : BaseArchRanges
     using WireBelPinRangeT = BelPinRange;
     // Pips
     using AllPipsRangeT = AllPipRange;
+    // Groups
+    using AllGroupsRangeT = GroupRange;
+    using GroupBelsRangeT = GroupBelRange;
+    using GroupWiresRangeT = GroupWireRange;
+    using GroupPipsRangeT = GroupPipRange;
+    using GroupGroupsRangeT = GroupGroupRange;
 };
 
 struct Arch : BaseArch<ArchRanges>
@@ -699,6 +750,29 @@ struct Arch : BaseArch<ArchRanges>
         return uarch->getClusterPlacement(cluster, root_bel, placement);
     }
 
+    // -------------------------------------------------
+    // Group methods
+    GroupId getGroupByName(IdStringList name) const override;
+    IdStringList getGroupName(GroupId group) const override;
+    GroupRange getGroups() const override { return GroupRange(chip_info); }
+    IdString getGroupType(GroupId group) const { return IdString(chip_group_info(chip_info, group).group_type); }
+    GroupBelRange getGroupBels(GroupId group) const override
+    {
+        return GroupBelRange(chip_group_info(chip_info, group), group.tile);
+    }
+    GroupWireRange getGroupWires(GroupId group) const override
+    {
+        return GroupWireRange(chip_group_info(chip_info, group), group.tile);
+    }
+    GroupPipRange getGroupPips(GroupId group) const override
+    {
+        return GroupPipRange(chip_group_info(chip_info, group), group.tile);
+    }
+    GroupGroupRange getGroupGroups(GroupId group) const override
+    {
+        return GroupGroupRange(chip_group_info(chip_info, group), group.tile);
+    }
+
     // -------------------------------------------------
     // Decal methods
     std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
diff --git a/himbaechel/archdefs.h b/himbaechel/archdefs.h
index 589dea9926..13318bbef0 100644
--- a/himbaechel/archdefs.h
+++ b/himbaechel/archdefs.h
@@ -102,12 +102,34 @@ struct DecalId
     DecalId() = default;
     DecalId(int32_t tile, int32_t index, DecalType type) : tile(tile), index(index), type(type) {};
 
-    bool operator==(const DecalId &other) const { return tile == other.tile && index == other.index && type == other.type; }
-    bool operator!=(const DecalId &other) const { return tile != other.tile || index != other.index || type != other.type; }
+    bool operator==(const DecalId &other) const
+    {
+        return tile == other.tile && index == other.index && type == other.type;
+    }
+    bool operator!=(const DecalId &other) const
+    {
+        return tile != other.tile || index != other.index || type != other.type;
+    }
     unsigned int hash() const { return mkhash(tile, mkhash(index, type)); }
 };
 
-typedef IdString GroupId;
+struct GroupId
+{
+    int32_t tile = -1;
+    int32_t index = -1;
+
+    GroupId() = default;
+    GroupId(int32_t tile, int32_t index) : tile(tile), index(index) {};
+
+    bool operator==(const GroupId &other) const { return tile == other.tile && index == other.index; }
+    bool operator!=(const GroupId &other) const { return tile != other.tile || index != other.index; }
+    bool operator<(const GroupId &other) const
+    {
+        return tile < other.tile || (tile == other.tile && index < other.index);
+    }
+    unsigned int hash() const { return mkhash(tile, index); }
+};
+
 typedef IdString BelBucketId;
 typedef IdString ClusterId;
 
diff --git a/himbaechel/chipdb.h b/himbaechel/chipdb.h
index 4f3241c781..099a1112c7 100644
--- a/himbaechel/chipdb.h
+++ b/himbaechel/chipdb.h
@@ -93,11 +93,23 @@ NPNR_PACKED_STRUCT(struct NodeShapePOD {
     int32_t timing_idx;
 });
 
+NPNR_PACKED_STRUCT(struct GroupDataPOD {
+    int32_t name;
+    int32_t group_type;
+    RelSlice<int32_t> group_bels;
+    RelSlice<int32_t> group_wires;
+    RelSlice<int32_t> group_pips;
+    RelSlice<int32_t> group_groups;
+
+    RelPtr<uint8_t> extra_data;
+});
+
 NPNR_PACKED_STRUCT(struct TileTypePOD {
     int32_t type_name;
     RelSlice<BelDataPOD> bels;
     RelSlice<TileWireDataPOD> wires;
     RelSlice<PipDataPOD> pips;
+    RelSlice<GroupDataPOD> groups;
     RelPtr<uint8_t> extra_data;
 });
 
diff --git a/himbaechel/himbaechel_api.cc b/himbaechel/himbaechel_api.cc
index 23b2476987..717d1879e6 100644
--- a/himbaechel/himbaechel_api.cc
+++ b/himbaechel/himbaechel_api.cc
@@ -85,10 +85,7 @@ bool HimbaechelAPI::getClusterPlacement(ClusterId cluster, BelId root_bel,
     return ctx->BaseArch::getClusterPlacement(cluster, root_bel, placement);
 }
 
-void HimbaechelAPI::expandBoundingBox(BoundingBox &bb) const
-{
-    ctx->BaseArch::expandBoundingBox(bb);
-}
+void HimbaechelAPI::expandBoundingBox(BoundingBox &bb) const { ctx->BaseArch::expandBoundingBox(bb); }
 
 HimbaechelArch *HimbaechelArch::list_head;
 HimbaechelArch::HimbaechelArch(const std::string &name) : name(name)
diff --git a/himbaechel/himbaechel_api.h b/himbaechel/himbaechel_api.h
index fa75740139..4f6f210130 100644
--- a/himbaechel/himbaechel_api.h
+++ b/himbaechel/himbaechel_api.h
@@ -109,10 +109,13 @@ struct HimbaechelAPI
     // Graphics
     virtual void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) {};
 
-    virtual void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire, IdString tile_type) {};
+    virtual void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type,
+                          int32_t tilewire, IdString tile_type) {};
 
-    virtual void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
-                WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id) {};
+    virtual void drawPip(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, WireId src,
+                         IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id) {};
+
+    virtual void drawGroup(std::vector<GraphicElement> &g, GroupId group, Loc loc) {};
 
     // Routing methods
     virtual void expandBoundingBox(BoundingBox &bb) const;
diff --git a/himbaechel/himbaechel_dbgen/chip.py b/himbaechel/himbaechel_dbgen/chip.py
index bedf0f28d4..6f7a3086d3 100644
--- a/himbaechel/himbaechel_dbgen/chip.py
+++ b/himbaechel/himbaechel_dbgen/chip.py
@@ -202,6 +202,47 @@ def serialise(self, context: str, bba: BBAWriter):
         else:
             bba.u32(0)
 @dataclass
+class GroupData(BBAStruct):
+    index: int
+    name: IdString
+    group_type: IdString = field(default_factory=IdString)
+    group_bels: list[int] = field(default_factory=list)
+    group_wires: list[int] = field(default_factory=list)
+    group_pips: list[int] = field(default_factory=list)
+    group_groups: list[int] = field(default_factory=list)
+    extra_data: object = None
+
+    def serialise_lists(self, context: str, bba: BBAWriter):
+        bba.label(f"{context}_group_bels")
+        for idx in self.group_bels:
+            bba.u32(idx)
+        bba.label(f"{context}_group_wires")
+        for idx in self.group_wires:
+            bba.u32(idx)
+        bba.label(f"{context}_group_pips")
+        for idx in self.group_pips:
+            bba.u32(idx)
+        bba.label(f"{context}_group_groups")
+        for idx in self.group_groups:
+            bba.u32(idx)
+        # extra data (optional)
+        if self.extra_data is not None:
+            self.extra_data.serialise_lists(f"{context}_extra_data", bba)
+            bba.label(f"{context}_extra_data")
+            self.extra_data.serialise(f"{context}_extra_data", bba)
+    def serialise(self, context: str, bba: BBAWriter):
+        bba.u32(self.name.index)
+        bba.u32(self.group_type.index)
+        bba.slice(f"{context}_group_bels", len(self.group_bels))
+        bba.slice(f"{context}_group_wires", len(self.group_wires))
+        bba.slice(f"{context}_group_pips", len(self.group_pips))
+        bba.slice(f"{context}_group_groups", len(self.group_groups))
+        if self.extra_data is not None:
+            bba.ref(f"{context}_extra_data")
+        else:
+            bba.u32(0)
+
+@dataclass
 class TileType(BBAStruct):
     strs: StringPool
     gfx_wire_ids: dict()
@@ -210,8 +251,10 @@ class TileType(BBAStruct):
     bels: list[BelData] = field(default_factory=list)
     pips: list[PipData] = field(default_factory=list)
     wires: list[TileWireData] = field(default_factory=list)
+    groups: list[GroupData] = field(default_factory=list)
 
     _wire2idx: dict[IdString, int] = field(default_factory=dict)
+    _group2idx: dict[IdString, int] = field(default_factory=dict)
 
     extra_data: object = None
 
@@ -253,6 +296,26 @@ def create_pip(self, src: str, dst: str, timing_class: str=""):
         self.wires[dst_idx].pips_uphill.append(pip.index)
         self.pips.append(pip)
         return pip
+    def create_group(self, name: str, type: str):
+        # Create a new group of a given name and type in the tile type
+        group = GroupData(index=len(self.groups),
+            name=self.strs.id(name),
+            group_type=self.strs.id(type))
+        self._group2idx[group.name] = group.index
+        self.groups.append(group)
+        return group
+    def add_bel_to_group(self, bel: BelData, group: str):
+        group_idx = self._group2idx[self.strs.id(group)]
+        self.groups[group_idx].group_bels.append(bel.index)
+    def add_wire_to_group(self, wire: TileWireData, group: str):
+        group_idx = self._group2idx[self.strs.id(group)]
+        self.groups[group_idx].group_wires.append(wire.index)
+    def add_pip_to_group(self, pip: PipData, group: str):
+        group_idx = self._group2idx[self.strs.id(group)]
+        self.groups[group_idx].group_pips.append(pip.index)
+    def add_group_to_group(self, sub_group: GroupData, group: str):
+        group_idx = self._group2idx[self.strs.id(group)]
+        self.groups[group_idx].group_groups.append(sub_group.index)
     def has_wire(self, wire: str):
         # Check if a wire has already been created
         return self.strs.id(wire) in self._wire2idx
@@ -267,6 +330,8 @@ def serialise_lists(self, context: str, bba: BBAWriter):
             wire.serialise_lists(f"{context}_wire{i}", bba)
         for i, pip in enumerate(self.pips):
             pip.serialise_lists(f"{context}_pip{i}", bba)
+        for i, group in enumerate(self.groups):
+            group.serialise_lists(f"{context}_group{i}", bba)
         # lists of members
         bba.label(f"{context}_bels")
         for i, bel in enumerate(self.bels):
@@ -277,6 +342,9 @@ def serialise_lists(self, context: str, bba: BBAWriter):
         bba.label(f"{context}_pips")
         for i, pip in enumerate(self.pips):
             pip.serialise(f"{context}_pip{i}", bba)
+        bba.label(f"{context}_groups")
+        for i, group in enumerate(self.groups):
+            group.serialise(f"{context}_group{i}", bba)
         # extra data (optional)
         if self.extra_data is not None:
             self.extra_data.serialise_lists(f"{context}_extra_data", bba)
@@ -287,6 +355,7 @@ def serialise(self, context: str, bba: BBAWriter):
         bba.slice(f"{context}_bels", len(self.bels))
         bba.slice(f"{context}_wires", len(self.wires))
         bba.slice(f"{context}_pips", len(self.pips))
+        bba.slice(f"{context}_groups", len(self.groups))
         if self.extra_data is not None:
             bba.ref(f"{context}_extra_data")
         else:
@@ -839,7 +908,7 @@ def serialise(self, bba: BBAWriter):
 
         bba.label("chip_info")
         bba.u32(0x00ca7ca7) # magic
-        bba.u32(5) # version
+        bba.u32(6) # version
         bba.u32(self.width)
         bba.u32(self.height)
 
diff --git a/himbaechel/himbaechel_gfxids.h b/himbaechel/himbaechel_gfxids.h
index 8d954bb3f3..78bbabc3cf 100644
--- a/himbaechel/himbaechel_gfxids.h
+++ b/himbaechel/himbaechel_gfxids.h
@@ -44,7 +44,7 @@ enum GfxTileWireId
     ,
 };
 #endif
-};
+}; // namespace HIMBAECHEL_UARCH
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/himbaechel/uarch/example/constids.inc b/himbaechel/uarch/example/constids.inc
index eca9b10827..4e16ad5918 100644
--- a/himbaechel/uarch/example/constids.inc
+++ b/himbaechel/uarch/example/constids.inc
@@ -41,3 +41,5 @@ X(LOGIC)
 X(BRAM)
 X(IO)
 X(NULL)
+
+X(SWITCHBOX)
diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc
index 42b7608668..cfb2a0b933 100644
--- a/himbaechel/uarch/example/example.cc
+++ b/himbaechel/uarch/example/example.cc
@@ -139,166 +139,176 @@ struct ExampleImpl : HimbaechelAPI
         return true;
     }
 
+    void drawGroup(std::vector<GraphicElement> &g, GroupId group, Loc loc) override
+    {
+        IdString group_type = ctx->getGroupType(group);
+        if (group_type == id_SWITCHBOX) {
+            GraphicElement el;
+            el.type = GraphicElement::TYPE_BOX;
+            el.style = GraphicElement::STYLE_FRAME;
+
+            el.x1 = loc.x + 0.1;
+            el.x2 = el.x1 + 0.4;
+            el.y1 = loc.y + 0.1;
+            el.y2 = el.y1 + 0.8;
+            g.push_back(el);
+        }
+    }
     void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override
     {
         GraphicElement el;
         el.type = GraphicElement::TYPE_BOX;
         el.style = style;
-        switch (bel_type.index)
-        {
-            case id_LUT4.index :
-                el.x1 = loc.x + 0.15;
-                el.x2 = el.x1 + 0.25;
-                el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
-                el.y2 = el.y1 - 0.05;
-                g.push_back(el);
-                break;
-            case id_DFF.index :
-                el.x1 = loc.x + 0.55;
-                el.x2 = el.x1 + 0.25;
-                el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
-                el.y2 = el.y1 - 0.05;
-                g.push_back(el);
-                break;
-            case id_GND_DRV.index :
-            case id_VCC_DRV.index :
-            case id_IOB.index :
-                el.x1 = loc.x + 0.25;
-                el.x2 = el.x1 + 0.50;
-                el.y1 = loc.y + 0.80 - loc.z * 0.40;
-                el.y2 = el.y1 - 0.25;
-                g.push_back(el);
-                break;
-            case id_BRAM_512X16.index :
-                el.x1 = loc.x + 0.25;
-                el.x2 = el.x1 + 0.50;
-                el.y1 = loc.y + 0.80;
-                el.y2 = el.y1 - 0.60;
-                g.push_back(el);
-                break;
+        switch (bel_type.index) {
+        case id_LUT4.index:
+            el.x1 = loc.x + 0.55;
+            el.x2 = el.x1 + 0.15;
+            el.y1 = loc.y + 0.90 - (loc.z / 2) * 0.1;
+            el.y2 = el.y1 - 0.05;
+            g.push_back(el);
+            break;
+        case id_DFF.index:
+            el.x1 = loc.x + 0.75;
+            el.x2 = el.x1 + 0.15;
+            el.y1 = loc.y + 0.90 - (loc.z / 2) * 0.1;
+            el.y2 = el.y1 - 0.05;
+            g.push_back(el);
+            break;
+        case id_GND_DRV.index:
+        case id_VCC_DRV.index:
+        case id_IOB.index:
+            el.x1 = loc.x + 0.55;
+            el.x2 = el.x1 + 0.35;
+            el.y1 = loc.y + 0.90 - loc.z * 0.40;
+            el.y2 = el.y1 - 0.25;
+            g.push_back(el);
+            break;
+        case id_BRAM_512X16.index:
+            el.x1 = loc.x + 0.55;
+            el.x2 = el.x1 + 0.35;
+            el.y1 = loc.y + 0.90;
+            el.y2 = el.y1 - 0.60;
+            g.push_back(el);
+            break;
         }
     }
 
-    void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire, IdString tile_type)
+    void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type,
+                  int32_t tilewire, IdString tile_type)
     {
         GraphicElement el;
         el.type = GraphicElement::TYPE_LINE;
         el.style = style;
         int z;
-        switch(tile_type.index)
-        {
-            case id_LOGIC.index:
-                switch (wire_type.index)
-                {
-                    case id_LUT_INPUT.index:
-                        z = (tilewire - GFX_WIRE_L0_I0) / 4;
-                        el.x1 = loc.x + 0.10;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.85 - z * 0.1  - ((tilewire - GFX_WIRE_L0_I0) % 4 + 1) * 0.01;
-                        el.y2 = el.y1;
-                        g.push_back(el);
-                        break;
-                    case id_LUT_OUT.index:
-                        z = tilewire - GFX_WIRE_L0_O;
-                        el.x1 = loc.x + 0.40;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
-                        el.y2 = el.y1;
-                        g.push_back(el);
-                        break;
-                    case id_FF_DATA.index:
-                        z = tilewire - GFX_WIRE_L0_D;
-                        el.x1 = loc.x + 0.50;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
-                        el.y2 = el.y1;
-                        g.push_back(el);
-                        break;
-                    case id_FF_OUT.index:
-                        z = tilewire - GFX_WIRE_L0_Q;
-                        el.x1 = loc.x + 0.80;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
-                        el.y2 = el.y1;
-                        g.push_back(el);
-                        break;
-                    case id_TILE_CLK.index:
-                        for(int i=0;i<8; i++) {
-                            GraphicElement el;
-                            el.type = GraphicElement::TYPE_LINE;
-                            el.style = style;
-                            el.x1 = loc.x + 0.6;
-                            el.x2 = el.x1;
-                            el.y1 = loc.y + 0.85 - i * 0.1 - 0.05;
-                            el.y2 = el.y1 - 0.05;
-                            g.push_back(el);
-                        }
-                        break;
-                }
+        switch (tile_type.index) {
+        case id_LOGIC.index:
+            switch (wire_type.index) {
+            case id_LUT_INPUT.index:
+                z = (tilewire - GFX_WIRE_L0_I0) / 4;
+                el.x1 = loc.x + 0.54;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.1 - ((tilewire - GFX_WIRE_L0_I0) % 4 + 1) * 0.01;
+                el.y2 = el.y1;
+                g.push_back(el);
                 break;
-            case id_BRAM.index:
-                switch (wire_type.index)
-                {
-                    case id_RAM_IN.index:
-                        z = tilewire - GFX_WIRE_RAM_WA0;
-                        el.x1 = loc.x + 0.20;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.78 - z * 0.015;
-                        el.y2 = el.y1;
-                        g.push_back(el);
-                        break;
-                    case id_RAM_OUT.index:
-                        z = tilewire - GFX_WIRE_RAM_DO0;
-                        el.x1 = loc.x + 0.75;
-                        el.x2 = el.x1 + 0.05;
-                        el.y1 = loc.y + 0.78 - z * 0.015;
-                        el.y2 = el.y1;
-                        g.push_back(el);                    
-                        break;
-                    case id_TILE_CLK.index:
-                        el.x1 = loc.x + 0.6;
-                        el.x2 = el.x1;
-                        el.y1 = loc.y + 0.20;
-                        el.y2 = el.y1 - 0.05;
-                        g.push_back(el);
-                        break;
-                }
+            case id_LUT_OUT.index:
+                z = tilewire - GFX_WIRE_L0_O;
+                el.x1 = loc.x + 0.70;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.1 - 0.025;
+                el.y2 = el.y1;
+                g.push_back(el);
                 break;
-            case id_IO.index:
-                switch (wire_type.index)
-                {
-                    case id_IO_I.index:
-                        break;
-                    case id_IO_O.index:
-                        break;
-                    case id_IO_T.index:
-                        break;
-                    case id_IO_PAD.index:
-                        break;
-                    case id_TILE_CLK.index:
-                        break;
-                    case id_GCLK.index:
-                        break;
-                }
+            case id_FF_DATA.index:
+                z = tilewire - GFX_WIRE_L0_D;
+                el.x1 = loc.x + 0.74;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.1 - 0.025;
+                el.y2 = el.y1;
+                g.push_back(el);
                 break;
-            case id_NULL.index:
-                switch (wire_type.index)
-                {
-                    case id_CLK_ROUTE.index:
-                        break;
-                    case id_GND.index:
-                        break;
-                    case id_VCC.index:
-                        break;
-                    case id_TILE_CLK.index:
-                        break;
+            case id_FF_OUT.index:
+                z = tilewire - GFX_WIRE_L0_Q;
+                el.x1 = loc.x + 0.90;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.1 - 0.025;
+                el.y2 = el.y1;
+                g.push_back(el);
+                break;
+            case id_TILE_CLK.index:
+                for (int i = 0; i < 8; i++) {
+                    GraphicElement el;
+                    el.type = GraphicElement::TYPE_LINE;
+                    el.style = style;
+                    el.x1 = loc.x + 0.6;
+                    el.x2 = el.x1;
+                    el.y1 = loc.y + 0.90 - i * 0.1 - 0.05;
+                    el.y2 = el.y1 - 0.05;
+                    g.push_back(el);
                 }
                 break;
+            }
+            break;
+        case id_BRAM.index:
+            switch (wire_type.index) {
+            case id_RAM_IN.index:
+                z = tilewire - GFX_WIRE_RAM_WA0;
+                el.x1 = loc.x + 0.54;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.015 - 0.025;
+                el.y2 = el.y1;
+                g.push_back(el);
+                break;
+            case id_RAM_OUT.index:
+                z = tilewire - GFX_WIRE_RAM_DO0;
+                el.x1 = loc.x + 0.90;
+                el.x2 = el.x1 + 0.01;
+                el.y1 = loc.y + 0.90 - z * 0.015 - 0.025;
+                el.y2 = el.y1;
+                g.push_back(el);
+                break;
+            case id_TILE_CLK.index:
+                el.x1 = loc.x + 0.60;
+                el.x2 = el.x1;
+                el.y1 = loc.y + 0.30;
+                el.y2 = el.y1 - 0.025;
+                g.push_back(el);
+                break;
+            }
+            break;
+        case id_IO.index:
+            switch (wire_type.index) {
+            case id_IO_I.index:
+                break;
+            case id_IO_O.index:
+                break;
+            case id_IO_T.index:
+                break;
+            case id_IO_PAD.index:
+                break;
+            case id_TILE_CLK.index:
+                break;
+            case id_GCLK.index:
+                break;
+            }
+            break;
+        case id_NULL.index:
+            switch (wire_type.index) {
+            case id_CLK_ROUTE.index:
+                break;
+            case id_GND.index:
+                break;
+            case id_VCC.index:
+                break;
+            case id_TILE_CLK.index:
+                break;
+            }
+            break;
         }
     }
 
-    void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
-            WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id)
+    void drawPip(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, WireId src, IdString src_type,
+                 int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id)
     {
         GraphicElement el;
         el.type = GraphicElement::TYPE_ARROW;
@@ -311,7 +321,6 @@ struct ExampleImpl : HimbaechelAPI
             el.x2 = loc.x + 0.50;
             el.y2 = el.y1;
             g.push_back(el);
-
         }
     }
 };
diff --git a/himbaechel/uarch/example/example_arch_gen.py b/himbaechel/uarch/example/example_arch_gen.py
index d36ae22e63..ec7a1187cd 100644
--- a/himbaechel/uarch/example/example_arch_gen.py
+++ b/himbaechel/uarch/example/example_arch_gen.py
@@ -62,6 +62,8 @@ def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
     tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
     tt.create_pip(f"CLK_PREV", f"CLK")
 
+    tt.create_group("SWITCHBOX", "SWITCHBOX")
+
 def create_logic_tiletype(chip: Chip):
     tt = chip.create_tile_type("LOGIC")
     # setup wires

From f01465f6280e2eae2459819597fda0fc2f46b703 Mon Sep 17 00:00:00 2001
From: Tarik Graba <tarikgraba@users.noreply.github.com>
Date: Tue, 17 Dec 2024 11:30:39 +0100
Subject: [PATCH 708/712] Add attributes to the hierarchical cells (#1405)

* Adds attributes to the hierarchical cells

* python: add binding for hierarchical cells attributes

* frontend/base: import hierarchical cells attributes
---
 common/kernel/nextpnr_types.h | 2 ++
 common/kernel/pybindings.cc   | 3 +++
 frontend/frontend_base.h      | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index fbe16daf7e..5ee030b17b 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -519,6 +519,8 @@ struct HierarchicalCell
     dict<IdString, HierarchicalPort> ports;
     // Name inside cell instance -> global name
     dict<IdString, IdString> hier_cells;
+    // Cell attributes
+    dict<IdString, Property> attrs;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/kernel/pybindings.cc b/common/kernel/pybindings.cc
index 8cf8e4248d..737bccd59a 100644
--- a/common/kernel/pybindings.cc
+++ b/common/kernel/pybindings.cc
@@ -283,6 +283,9 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
                      wrap_context<IdIdMap &>>::def_wrap(hierarchy_cls, "nets");
     readonly_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::hier_cells), &HierarchicalCell::hier_cells,
                      wrap_context<IdIdMap &>>::def_wrap(hierarchy_cls, "hier_cells");
+    readonly_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::attrs), &HierarchicalCell::attrs,
+                     wrap_context<AttrMap &>>::def_wrap(hierarchy_cls, "attrs");
+
     WRAP_MAP(m, AttrMap, conv_to_str<Property>, "AttrMap");
     WRAP_MAP(m, PortMap, wrap_context<PortInfo &>, "PortMap");
     WRAP_MAP(m, IdIdMap, conv_to_str<IdString>, "IdIdMap");
diff --git a/frontend/frontend_base.h b/frontend/frontend_base.h
index bdc8a896c8..cd26349f1b 100644
--- a/frontend/frontend_base.h
+++ b/frontend/frontend_base.h
@@ -535,6 +535,9 @@ template <typename FrontendType> struct GenericFrontend
         // Do the submodule import
         auto type = impl.get_cell_type(cd);
         import_module(submod, name, type, mod_refs.at(type));
+        // Add current cell attributes to the imported module
+        impl.foreach_attr( cd, [&](const std::string &name, const Property &value)
+              { ctx->hierarchy[submod.path].attrs[ctx->id(name)] = value; } );
     }
 
     // Import the cells section of a module

From 3d350c21c5a2dd38f68a0eacb59522a797322607 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Tue, 31 Dec 2024 19:31:03 +1000
Subject: [PATCH 709/712] Gowin. BUGFIX. Global clock routing. (#1410)

Adds additional restrictions on the first PIP after the clock source -
only connections to SPINEs are allowed. This allowed to correct the
behaviour of DQCEs since the latter can only disable/enable SPINEs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/globals.cc | 58 ++++++++++++++++++++-----------
 1 file changed, 38 insertions(+), 20 deletions(-)

diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
index aa5490a453..3a91752c6e 100644
--- a/himbaechel/uarch/gowin/globals.cc
+++ b/himbaechel/uarch/gowin/globals.cc
@@ -43,7 +43,7 @@ struct GowinGlobalRouter
     bool global_pip_available(PipId pip) const { return gwu.is_global_pip(pip) || ctx->checkPipAvail(pip); };
 
     // allow io->global, global->global and global->tile clock
-    bool global_pip_filter(PipId pip) const
+    bool global_pip_filter(PipId pip, WireId src_wire) const
     {
         auto is_local = [&](IdString wire_type) {
             return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
@@ -58,7 +58,13 @@ struct GowinGlobalRouter
         bool src_valid = not_dsc_pip && src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
         bool dst_valid = not_dsc_pip && dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
 
-        bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        bool res;
+        if (src == src_wire && (!src_type.in(id_IO, id_HCLK))) {
+            bool dst_is_spine = dst_name.str(ctx).rfind("SPINE", 0) == 0;
+            res = src_valid && dst_is_spine;
+        } else {
+            res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+        }
         if (ctx->debug && false /*&& res*/) {
             log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
                      ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
@@ -69,7 +75,7 @@ struct GowinGlobalRouter
         return res;
     }
 
-    bool global_DQCE_pip_filter(PipId pip) const
+    bool global_DQCE_pip_filter(PipId pip, WireId src_wire) const
     {
         auto is_local = [&](IdString wire_type) {
             return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
@@ -92,18 +98,25 @@ struct GowinGlobalRouter
         bool src_valid = not_dsc_pip && src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O, id_HCLK);
         bool dst_valid = not_dsc_pip && dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I, id_HCLK);
 
-        bool res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
-        if (ctx->debug && false /*&& res*/) {
-            log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
-                     ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
-                     src_type.c_str(ctx));
-            log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
-                     is_local(src_type), is_local(dst_type));
+        // If DQCE is used, then the source can only connect to SPINEs as only they can be switched off/on.
+        bool res;
+        if (src == src_wire) {
+            bool dst_is_spine = dst_name.str(ctx).rfind("SPINE", 0) == 0;
+            res = src_valid && dst_is_spine;
+        } else {
+            res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
+            if (ctx->debug && false /*res*/) {
+                log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
+                         ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
+                         src_type.c_str(ctx));
+                log_info("res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d\n", res, src_valid, dst_valid,
+                         is_local(src_type), is_local(dst_type));
+            }
         }
         return res;
     }
 
-    bool global_DCS_pip_filter(PipId pip) const
+    bool global_DCS_pip_filter(PipId pip, WireId src_wire) const
     {
         auto is_local = [&](IdString wire_type) {
             return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
@@ -171,7 +184,7 @@ struct GowinGlobalRouter
                     continue;
                 }
                 // Apply our custom pip filter
-                if (!pip_filter(pip)) {
+                if (!pip_filter(pip, src)) {
                     continue;
                 }
                 // Add to the queue
@@ -305,8 +318,8 @@ struct GowinGlobalRouter
             }
             bool bfs_res;
             bfs_res = backwards_bfs_route(
-                    net, src, dst, 1000000, false, [&](PipId pip) { return (is_relaxed_sink(usr) || pip_filter(pip)); },
-                    path);
+                    net, src, dst, 1000000, false,
+                    [&](PipId pip, WireId src_wire) { return (is_relaxed_sink(usr) || pip_filter(pip, src)); }, path);
             if (bfs_res) {
                 routed = routed == ROUTED_PARTIALLY ? routed : ROUTED_ALL;
             } else {
@@ -340,7 +353,8 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_DQCE_pip_filter(pip); }, src);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip, WireId src_wire) { return global_DQCE_pip_filter(pip, src); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -417,7 +431,8 @@ struct GowinGlobalRouter
             src = ctx->getBelPinWire(driver.cell->bel, driver.port);
         }
 
-        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_DCS_pip_filter(pip); }, src);
+        RouteResult route_result =
+                route_direct_net(net, [&](PipId pip, WireId src_wire) { return global_DCS_pip_filter(pip, src); }, src);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -504,7 +519,8 @@ struct GowinGlobalRouter
         WireId src = ctx->getBelPinWire(driver.cell->bel, port);
 
         std::vector<PipId> path;
-        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); }, src, &path);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip, WireId src_wire) { return global_pip_filter(pip, src); }, src, &path);
         if (route_result == NOT_ROUTED) {
             log_error("Can't route the %s network.\n", ctx->nameOf(net));
         }
@@ -568,7 +584,8 @@ struct GowinGlobalRouter
         NetInfo *net_before_buf = buf_ci->getPort(id_I);
         NPNR_ASSERT(net_before_buf != nullptr);
 
-        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); }, src);
+        RouteResult route_result = route_direct_net(
+                net, [&](PipId pip, WireId src_wire) { return global_pip_filter(pip, src_wire); }, src);
         if (route_result == NOT_ROUTED || route_result == ROUTED_PARTIALLY) {
             log_error("Can't route the %s net. It might be worth removing the BUFG buffer flag.\n", ctx->nameOf(net));
         }
@@ -578,7 +595,7 @@ struct GowinGlobalRouter
         CellInfo *true_src_ci = net_before_buf->driver.cell;
         src = ctx->getBelPinWire(true_src_ci->bel, net_before_buf->driver.port);
         ctx->bindWire(src, net, STRENGTH_LOCKED);
-        backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip) { return true; });
+        backwards_bfs_route(net, src, dst, 1000000, false, [&](PipId pip, WireId src_wire) { return true; });
         // remove net
         buf_ci->movePortTo(id_O, true_src_ci, net_before_buf->driver.port);
         net_before_buf->driver.cell = nullptr;
@@ -588,7 +605,8 @@ struct GowinGlobalRouter
 
     void route_clk_net(NetInfo *net)
     {
-        RouteResult route_result = route_direct_net(net, [&](PipId pip) { return global_pip_filter(pip); });
+        RouteResult route_result =
+                route_direct_net(net, [&](PipId pip, WireId src_wire) { return global_pip_filter(pip, src_wire); });
         if (route_result != NOT_ROUTED) {
             log_info("    '%s' net was routed  using global resources %s.\n", ctx->nameOf(net),
                      route_result == ROUTED_ALL ? "only" : "partially");

From 0345b6e803bef9bf63eb6a862f96b3b1dded857a Mon Sep 17 00:00:00 2001
From: Aritz Erkiaga <38228836+aerkiaga@users.noreply.github.com>
Date: Wed, 1 Jan 2025 13:05:54 +0100
Subject: [PATCH 710/712] Fix gowin ALU SUB mode ports (#1407)

---
 himbaechel/uarch/gowin/pack.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index e820bd160b..21f9c2ea2a 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -1423,6 +1423,12 @@ struct GowinPacker
                             ci->renamePort(id_I0, id_I3);
                             ci->renamePort(id_I2, id_I0);
                         }
+                        // XXX mode 1 - SUB
+                        else if (ci->params.at(id_ALU_MODE).as_int64() == 1) {
+                            ci->renamePort(id_I3, id_I2);
+                            ci->renamePort(id_I1, id_I3);
+                            ci->renamePort(id_I2, id_I1);
+                        }
                         // XXX I2 is pin C which must be set to 1 for all ALU modes except MUL
                         // we use only mode 2 ADDSUB so create and connect this pin
                         ci->addInput(id_I2);

From c565e364bc3fcf48db0ecb2c2891c9939fae5603 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 1 Jan 2025 22:11:57 +1000
Subject: [PATCH 711/712] Gowin. Add the ability to place registers in IOB
 (#1403)

* Gowin. Add the ability to place registers in IOB

IO blocks have registers: for input, for output and for OutputEnable
signal - IREG, OREG and TREG respectively.

Each of the registers has one implicit non-switched wire, which one
depends on the type of register (IREG has a Q wire, OREG has a D wire).
Although the registers can be activated independently of each other they
share the CLK, ClockEnable and LocalSetReset wires and this places
restrictions on the possible combinations of register types in a single
IO.

Register placement in IO blocks is enabled by specifying the command
line keys --vopt ireg_in_iob, --vopt oreg_in_iob, or --vopt ioreg_in_iob.

It should be noted that specifying these keys leads to attempts to place
registers in IO blocks, but no errors are generated in case of failure.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Registers in IO

Check for unconnected ports.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. IO regs. Verbose warnings.

If an attempt to place an FF in an IO block fails, issue a warning
detailing the reason for the failure, whether it is a register type
conflict, a network requirement violation, or a control signal conflict.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. BUGFIX. Fix FFs compatibility.

Flipflops with a fixed ClockEnable input cannot coexist with flipflops
with a variable one.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. FFs in IO.  Changing diagnostic messages.

Placement modes are still specified by the command line keys
ireg_in_iob/oreg_in_iob/ioreg_in_iob, but also introduces more granular
control in the form of attributes at I/O ports:

  (* NOIOBFF *) - registers are never placed in this IO,

  (* IOBFF *) - registers must be placed in this IO, in case of failure
  a warning (not an error) with the reason for nonplacement is issued,

  _attribute_absence_ - no diagnostics will be issued: managed to place - good, failed - not bad either.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Registers in IO.

Change the logic for handling command line keys and attributes -
attributes allow routines to be placed in IO regardless of global mode.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Registers in IO. Fix style.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/constids.inc |  21 ++
 himbaechel/uarch/gowin/gowin.cc     |  15 +-
 himbaechel/uarch/gowin/gowin.h      |   4 +
 himbaechel/uarch/gowin/pack.cc      | 363 +++++++++++++++++++++++++++-
 4 files changed, 393 insertions(+), 10 deletions(-)

diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc
index 6e294b8663..88c98fb9dc 100644
--- a/himbaechel/uarch/gowin/constids.inc
+++ b/himbaechel/uarch/gowin/constids.inc
@@ -1312,3 +1312,24 @@ X(LSREN)
 
 // EMCU
 X(EMCU)
+
+// Register placement options
+X(IREG_IN_IOB)
+X(OREG_IN_IOB)
+X(IOREG_IN_IOB)
+X(HAS_REG)
+X(IREG_TYPE)
+X(OREG_TYPE)
+X(TREG_TYPE)
+X(IREG_CLK_NET)
+X(IREG_CE_NET)
+X(IREG_LSR_NET)
+X(OREG_CLK_NET)
+X(OREG_CE_NET)
+X(OREG_LSR_NET)
+X(TREG_CLK_NET)
+X(TREG_CE_NET)
+X(TREG_LSR_NET)
+X(NOIOBFF)
+X(IOBFF)
+
diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
index e3a4225ff2..2afbadebb8 100644
--- a/himbaechel/uarch/gowin/gowin.cc
+++ b/himbaechel/uarch/gowin/gowin.cc
@@ -196,6 +196,17 @@ void GowinImpl::init(Context *ctx)
     if (args.options.count("cst")) {
         ctx->settings[ctx->id("cst.filename")] = args.options.at("cst");
     }
+
+    // place registers in IO blocks
+    if (args.options.count("ireg_in_iob")) {
+        ctx->settings[id_IREG_IN_IOB] = Property(1);
+    }
+    if (args.options.count("oreg_in_iob")) {
+        ctx->settings[id_OREG_IN_IOB] = Property(1);
+    }
+    if (args.options.count("ioreg_in_iob")) {
+        ctx->settings[id_IOREG_IN_IOB] = Property(1);
+    }
 }
 
 // We do not allow the use of global wires that bypass a special router.
@@ -811,7 +822,9 @@ inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
             (ff->type == id_DFFNRE && adj_ff->type != id_DFFNSE) ||
             (ff->type == id_DFFNP && adj_ff->type != id_DFFNC) || (ff->type == id_DFFNC && adj_ff->type != id_DFFNP) ||
             (ff->type == id_DFFNPE && adj_ff->type != id_DFFNCE) ||
-            (ff->type == id_DFFNCE && adj_ff->type != id_DFFNPE));
+            (ff->type == id_DFFNCE && adj_ff->type != id_DFFNPE) || (ff->type == id_DFF && adj_ff->type != id_DFF) ||
+            (ff->type == id_DFFE && adj_ff->type != id_DFFE) || (ff->type == id_DFFN && adj_ff->type != id_DFFN) ||
+            (ff->type == id_DFFNE && adj_ff->type != id_DFFNE));
 }
 
 // placement validation
diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index e2903e9982..05bfaa30c7 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -21,6 +21,10 @@ inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
 inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
 inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
 
+// io
+inline bool type_is_io(IdString cell_type) { return cell_type.in(id_IBUF, id_OBUF, id_IOBUF, id_TBUF); }
+inline bool is_io(const CellInfo *cell) { return type_is_io(cell->type); }
+
 inline bool type_is_diffio(IdString cell_type)
 {
     return cell_type.in(id_ELVDS_IOBUF, id_ELVDS_IBUF, id_ELVDS_TBUF, id_ELVDS_OBUF, id_TLVDS_IOBUF, id_TLVDS_IBUF,
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 21f9c2ea2a..7a82f8591d 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -184,8 +184,9 @@ struct GowinPacker
 
         for (auto &cell : ctx->cells) {
             CellInfo &ci = *cell.second;
-            if (!ci.type.in(id_IBUF, id_OBUF, id_TBUF, id_IOBUF))
+            if (!is_io(&ci)) {
                 continue;
+            }
             if (ci.attrs.count(id_BEL) == 0) {
                 log_error("Unconstrained IO:%s\n", ctx->nameOf(&ci));
             }
@@ -204,10 +205,7 @@ struct GowinPacker
     // ===================================
     // Differential IO
     // ===================================
-    static bool is_iob(const Context *ctx, CellInfo *cell)
-    {
-        return (cell->type.in(id_IBUF, id_OBUF, id_TBUF, id_IOBUF));
-    }
+    static bool is_iob(const Context *ctx, CellInfo *cell) { return is_io(cell); }
 
     std::pair<CellInfo *, CellInfo *> get_pn_cells(const CellInfo &ci)
     {
@@ -352,7 +350,13 @@ struct GowinPacker
         NPNR_ASSERT(iob->bel != BelId());
         Loc loc = ctx->getBelLocation(iob->bel);
         loc.z = loc.z - BelZ::IOBA_Z + BelZ::IOLOGICA_Z;
-        return ctx->getBelByLocation(loc);
+        BelId bel = ctx->getBelByLocation(loc);
+        if (bel != BelId()) {
+            if (ctx->getBelType(bel) == id_IOLOGICO) {
+                return bel;
+            }
+        }
+        return BelId();
     }
 
     BelId get_iologici_bel(CellInfo *iob)
@@ -360,7 +364,13 @@ struct GowinPacker
         NPNR_ASSERT(iob->bel != BelId());
         Loc loc = ctx->getBelLocation(iob->bel);
         loc.z = loc.z - BelZ::IOBA_Z + BelZ::IOLOGICA_Z + 2;
-        return ctx->getBelByLocation(loc);
+        BelId bel = ctx->getBelByLocation(loc);
+        if (bel != BelId()) {
+            if (ctx->getBelType(bel) == id_IOLOGICI) {
+                return bel;
+            }
+        }
+        return BelId();
     }
 
     void check_iologic_placement(CellInfo &ci, Loc iob_loc, int diff /* 1 - diff */)
@@ -502,7 +512,9 @@ struct GowinPacker
         out_iob->disconnectPort(id_I);
         ci.disconnectPort(out_port);
         if (ci.type == id_IOLOGICO_EMPTY) {
-            ci.movePortTo(id_D, out_iob, id_I);
+            if (ci.attrs.count(id_HAS_REG) == 0) {
+                ci.movePortTo(id_D, out_iob, id_I);
+            }
             return;
         }
         set_daaj_nets(ci, iob_bel);
@@ -630,7 +642,9 @@ struct GowinPacker
         in_iob->disconnectPort(id_O);
         ci.disconnectPort(in_port);
         if (ci.type == id_IOLOGICI_EMPTY) {
-            ci.movePortTo(id_Q, in_iob, id_O);
+            if (ci.attrs.count(id_HAS_REG) == 0) {
+                ci.movePortTo(id_Q, in_iob, id_O);
+            }
             return;
         }
 
@@ -640,6 +654,334 @@ struct GowinPacker
         make_iob_nets(*in_iob);
     }
 
+    static bool is_ff(const Context *ctx, CellInfo *cell) { return is_dff(cell); }
+
+    static bool incompatible_ffs(IdString type_a, IdString type_b)
+    {
+        return type_a != type_b &&
+               ((type_a == id_DFFS && type_b != id_DFFR) || (type_a == id_DFFR && type_b != id_DFFS) ||
+                (type_a == id_DFFSE && type_b != id_DFFRE) || (type_a == id_DFFRE && type_b != id_DFFSE) ||
+                (type_a == id_DFFP && type_b != id_DFFC) || (type_a == id_DFFC && type_b != id_DFFP) ||
+                (type_a == id_DFFPE && type_b != id_DFFCE) || (type_a == id_DFFCE && type_b != id_DFFPE) ||
+                (type_a == id_DFFNS && type_b != id_DFFNR) || (type_a == id_DFFNR && type_b != id_DFFNS) ||
+                (type_a == id_DFFNSE && type_b != id_DFFNRE) || (type_a == id_DFFNRE && type_b != id_DFFNSE) ||
+                (type_a == id_DFFNP && type_b != id_DFFNC) || (type_a == id_DFFNC && type_b != id_DFFNP) ||
+                (type_a == id_DFFNPE && type_b != id_DFFNCE) || (type_a == id_DFFNCE && type_b != id_DFFNPE) ||
+                (type_a == id_DFF && type_b != id_DFF) || (type_a == id_DFFN && type_b != id_DFFN) ||
+                (type_a == id_DFFE && type_b != id_DFFE) || (type_a == id_DFFNE && type_b != id_DFFNE));
+    }
+
+    void pack_io_regs()
+    {
+        log_info("Pack FFs into IO cells...\n");
+        std::vector<IdString> cells_to_remove;
+        std::vector<IdString> nets_to_remove;
+        std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+        for (auto &cell : ctx->cells) {
+            CellInfo &ci = *cell.second;
+            if (!is_io(&ci)) {
+                continue;
+            }
+            if (ci.attrs.count(id_NOIOBFF)) {
+                if (ctx->debug) {
+                    log_info(" NOIOBFF attribute at %s. Skipping FF placement.\n", ctx->nameOf(&ci));
+                }
+                continue;
+            }
+
+            // In the case of placing multiple registers in the IO it should be
+            // noted that the CLK, ClockEnable and LocalSetReset nets must
+            // match.
+            const NetInfo *clk_net = nullptr;
+            const NetInfo *ce_net = nullptr;
+            const NetInfo *lsr_net = nullptr;
+            IdString reg_type;
+
+            // input reg in IO
+            CellInfo *iologic_i = nullptr;
+            if ((ci.type == id_IBUF && (ctx->settings.count(id_IREG_IN_IOB) || ci.attrs.count(id_IOBFF))) ||
+                (ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF)))) {
+
+                if (ci.getPort(id_O) == nullptr) {
+                    continue;
+                }
+                // OBUF O -> D FF
+                CellInfo *ff = net_only_drives(ctx, ci.ports.at(id_O).net, is_ff, id_D);
+                if (ff == nullptr) {
+                    if (ci.attrs.count(id_IOBFF)) {
+                        log_warning("Port O of %s is not connected to FF.\n", ctx->nameOf(&ci));
+                    }
+                    continue;
+                }
+                if (ci.ports.at(id_O).net->users.entries() != 1) {
+                    if (ci.attrs.count(id_IOBFF)) {
+                        log_warning("Port O of %s is the driver of %s multi-sink network.\n", ctx->nameOf(&ci),
+                                    ctx->nameOf(ci.ports.at(id_O).net));
+                    }
+                    continue;
+                }
+                BelId l_bel = get_iologici_bel(&ci);
+                if (l_bel == BelId()) {
+                    continue;
+                }
+                if (ctx->debug) {
+                    log_info(" trying %s ff as Input Register of %s IO\n", ctx->nameOf(ff), ctx->nameOf(&ci));
+                }
+
+                clk_net = ff->getPort(id_CLK);
+                ce_net = ff->getPort(id_CE);
+                for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+                    lsr_net = ff->getPort(port);
+                    if (lsr_net != nullptr) {
+                        break;
+                    }
+                }
+                reg_type = ff->type;
+
+                // create IOLOGIC cell for flipflop
+                IdString iologic_name = gwu.create_aux_name(ci.name, 0, "_iobff$");
+                auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICI_EMPTY);
+                new_cells.push_back(std::move(iologic_cell));
+                iologic_i = new_cells.back().get();
+
+                // move ports
+                for (auto &port : ff->ports) {
+                    IdString port_name = port.first;
+                    ff->movePortTo(port_name, iologic_i, port_name != id_Q ? port_name : id_Q4);
+                }
+                if (ctx->verbose) {
+                    log_info("  place FF %s into IBUF %s, make iologic_i %s\n", ctx->nameOf(ff), ctx->nameOf(&ci),
+                             ctx->nameOf(iologic_i));
+                }
+                iologic_i->setAttr(id_HAS_REG, 1);
+                iologic_i->setAttr(id_IREG_TYPE, ff->type.str(ctx));
+                cells_to_remove.push_back(ff->name);
+            }
+
+            // output reg in IO
+            CellInfo *iologic_o = nullptr;
+            if ((ci.type == id_OBUF && (ctx->settings.count(id_OREG_IN_IOB) || ci.attrs.count(id_IOBFF))) ||
+                (ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF)))) {
+                do {
+                    if (ci.getPort(id_I) == nullptr) {
+                        break;
+                    }
+                    // OBUF I <- Q FF
+                    CellInfo *ff = net_driven_by(ctx, ci.ports.at(id_I).net, is_ff, id_Q);
+                    if (ff == nullptr) {
+                        if (ci.attrs.count(id_IOBFF)) {
+                            log_warning("Port I of %s is not connected to FF.\n", ctx->nameOf(&ci));
+                        }
+                    } else {
+                        if (ci.ports.at(id_I).net->users.entries() != 1) {
+                            if (ci.attrs.count(id_IOBFF)) {
+                                log_warning("Port I of %s is not the only sink on the %s network.\n", ctx->nameOf(&ci),
+                                            ctx->nameOf(ci.ports.at(id_I).net));
+                            }
+                            break;
+                        }
+                        BelId l_bel = get_iologico_bel(&ci);
+                        if (l_bel == BelId()) {
+                            break;
+                        }
+
+                        const NetInfo *this_clk_net = ff->getPort(id_CLK);
+                        const NetInfo *this_ce_net = ff->getPort(id_CE);
+                        const NetInfo *this_lsr_net;
+                        for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+                            this_lsr_net = ff->getPort(port);
+                            if (this_lsr_net != nullptr) {
+                                break;
+                            }
+                        }
+                        // The IOBUF may already have registers placed
+                        if (ci.type == id_IOBUF) {
+                            if (iologic_i != nullptr) {
+                                if (incompatible_ffs(ff->type, reg_type)) {
+                                    if (ci.attrs.count(id_IOBFF)) {
+                                        log_warning("OREG type conflict:%s:%s vs %s IREG:%s\n", ctx->nameOf(ff),
+                                                    ff->type.c_str(ctx), ctx->nameOf(&ci), reg_type.c_str(ctx));
+                                    }
+                                    break;
+                                } else {
+                                    if (clk_net != this_clk_net || ce_net != this_ce_net || lsr_net != this_lsr_net) {
+                                        if (clk_net != this_clk_net) {
+                                            if (ci.attrs.count(id_IOBFF)) {
+                                                log_warning("Conflicting OREG CLK nets at %s:'%s' vs '%s'\n",
+                                                            ctx->nameOf(&ci), ctx->nameOf(clk_net),
+                                                            ctx->nameOf(this_clk_net));
+                                            }
+                                        }
+                                        if (ce_net != this_ce_net) {
+                                            if (ci.attrs.count(id_IOBFF)) {
+                                                log_warning("Conflicting OREG CE nets at %s:'%s' vs '%s'\n",
+                                                            ctx->nameOf(&ci), ctx->nameOf(ce_net),
+                                                            ctx->nameOf(this_ce_net));
+                                            }
+                                        }
+                                        if (lsr_net != this_lsr_net) {
+                                            if (ci.attrs.count(id_IOBFF)) {
+                                                log_warning("Conflicting OREG LSR nets at %s:'%s' vs '%s'\n",
+                                                            ctx->nameOf(&ci), ctx->nameOf(lsr_net),
+                                                            ctx->nameOf(this_lsr_net));
+                                            }
+                                        }
+                                        break;
+                                    }
+                                }
+                            } else {
+                                clk_net = this_clk_net;
+                                ce_net = this_ce_net;
+                                lsr_net = this_lsr_net;
+                                reg_type = ff->type;
+                            }
+                        }
+
+                        // create IOLOGIC cell for flipflop
+                        IdString iologic_name = gwu.create_aux_name(ci.name, 1, "_iobff$");
+                        auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICO_EMPTY);
+                        new_cells.push_back(std::move(iologic_cell));
+                        iologic_o = new_cells.back().get();
+
+                        // move ports
+                        for (auto &port : ff->ports) {
+                            IdString port_name = port.first;
+                            ff->movePortTo(port_name, iologic_o, port_name != id_D ? port_name : id_D0);
+                        }
+                        if (ctx->verbose) {
+                            log_info("  place FF %s into OBUF %s, make iologic_o %s\n", ctx->nameOf(ff),
+                                     ctx->nameOf(&ci), ctx->nameOf(iologic_o));
+                        }
+                        iologic_o->setAttr(id_HAS_REG, 1);
+                        iologic_o->setAttr(id_OREG_TYPE, ff->type.str(ctx));
+                        cells_to_remove.push_back(ff->name);
+                    }
+                    break;
+                } while (false);
+            }
+
+            // output enable reg in IO
+            if (ci.type == id_IOBUF && (ctx->settings.count(id_IOREG_IN_IOB) || ci.attrs.count(id_IOBFF))) {
+                do {
+                    if (ci.getPort(id_OEN) == nullptr) {
+                        break;
+                    }
+                    // IOBUF OEN <- Q FF
+                    CellInfo *ff = net_driven_by(ctx, ci.ports.at(id_OEN).net, is_ff, id_Q);
+                    if (ff != nullptr) {
+                        if (ci.ports.at(id_OEN).net->users.entries() != 1) {
+                            if (ci.attrs.count(id_IOBFF)) {
+                                log_warning("Port OEN of %s is not the only sink on the %s network.\n",
+                                            ctx->nameOf(&ci), ctx->nameOf(ci.ports.at(id_OEN).net));
+                            }
+                            break;
+                        }
+                        BelId l_bel = get_iologico_bel(&ci);
+                        if (l_bel == BelId()) {
+                            break;
+                        }
+                        if (ctx->debug) {
+                            log_info(" trying %s ff as Output Enable Register of %s IO\n", ctx->nameOf(ff),
+                                     ctx->nameOf(&ci));
+                        }
+
+                        const NetInfo *this_clk_net = ff->getPort(id_CLK);
+                        const NetInfo *this_ce_net = ff->getPort(id_CE);
+                        const NetInfo *this_lsr_net;
+                        for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+                            this_lsr_net = ff->getPort(port);
+                            if (this_lsr_net != nullptr) {
+                                break;
+                            }
+                        }
+
+                        // The IOBUF may already have registers placed
+                        if (iologic_i != nullptr || iologic_o != nullptr) {
+                            if (iologic_o == nullptr) {
+                                iologic_o = iologic_i;
+                            }
+                            if (incompatible_ffs(ff->type, reg_type)) {
+                                if (ci.attrs.count(id_IOBFF)) {
+                                    log_warning("TREG type conflict:%s:%s vs %s IREG/OREG:%s\n", ctx->nameOf(ff),
+                                                ff->type.c_str(ctx), ctx->nameOf(&ci), reg_type.c_str(ctx));
+                                }
+                                break;
+                            } else {
+                                if (clk_net != this_clk_net || ce_net != this_ce_net || lsr_net != this_lsr_net) {
+                                    if (clk_net != this_clk_net) {
+                                        if (ci.attrs.count(id_IOBFF)) {
+                                            log_warning("Conflicting TREG CLK nets at %s:'%s' vs '%s'\n",
+                                                        ctx->nameOf(&ci), ctx->nameOf(clk_net),
+                                                        ctx->nameOf(this_clk_net));
+                                        }
+                                    }
+                                    if (ce_net != this_ce_net) {
+                                        if (ci.attrs.count(id_IOBFF)) {
+                                            log_warning("Conflicting TREG CE nets at %s:'%s' vs '%s'\n",
+                                                        ctx->nameOf(&ci), ctx->nameOf(ce_net),
+                                                        ctx->nameOf(this_ce_net));
+                                        }
+                                    }
+                                    if (lsr_net != this_lsr_net) {
+                                        if (ci.attrs.count(id_IOBFF)) {
+                                            log_warning("Conflicting TREG LSR nets at %s:'%s' vs '%s'\n",
+                                                        ctx->nameOf(&ci), ctx->nameOf(lsr_net),
+                                                        ctx->nameOf(this_lsr_net));
+                                        }
+                                    }
+                                    break;
+                                }
+                            }
+                        }
+
+                        if (iologic_o == nullptr) {
+                            // create IOLOGIC cell for flipflop
+                            IdString iologic_name = gwu.create_aux_name(ci.name, 2, "_iobff$");
+                            auto iologic_cell = gwu.create_cell(iologic_name, id_IOLOGICO_EMPTY);
+                            new_cells.push_back(std::move(iologic_cell));
+                            iologic_o = new_cells.back().get();
+                        }
+
+                        // move ports
+                        for (auto &port : ff->ports) {
+                            IdString port_name = port.first;
+                            if (port_name == id_Q) {
+                                continue;
+                            }
+                            ff->movePortTo(port_name, iologic_o, port_name != id_D ? port_name : id_TX);
+                        }
+
+                        nets_to_remove.push_back(ci.getPort(id_OEN)->name);
+                        ci.disconnectPort(id_OEN);
+                        ff->disconnectPort(id_Q);
+
+                        if (ctx->verbose) {
+                            log_info("  place FF %s into IOBUF %s, make iologic_o %s\n", ctx->nameOf(ff),
+                                     ctx->nameOf(&ci), ctx->nameOf(iologic_o));
+                        }
+                        iologic_o->setAttr(id_HAS_REG, 1);
+                        iologic_o->setAttr(id_TREG_TYPE, ff->type.str(ctx));
+                        cells_to_remove.push_back(ff->name);
+                    }
+                    break;
+                } while (false);
+            }
+        }
+
+        for (auto cell : cells_to_remove) {
+            ctx->cells.erase(cell);
+        }
+
+        for (auto &ncell : new_cells) {
+            ctx->cells[ncell->name] = std::move(ncell);
+        }
+
+        for (auto net : nets_to_remove) {
+            ctx->nets.erase(net);
+        }
+    }
+
     void pack_iodelay()
     {
         log_info("Pack IODELAY...\n");
@@ -3593,6 +3935,9 @@ struct GowinPacker
         pack_diff_iobs();
         ctx->check();
 
+        pack_io_regs();
+        ctx->check();
+
         pack_iodelay();
         ctx->check();
 

From 55bd7608089bd5b9efd0866744f491a99a2ba330 Mon Sep 17 00:00:00 2001
From: myrtle <gatecat@ds0.me>
Date: Thu, 2 Jan 2025 11:08:42 +0100
Subject: [PATCH 712/712] ice40: Don't constrain multiple
 potentially-incompatible FFs to same tile (#1413)

Signed-off-by: gatecat <gatecat@ds0.me>
---
 ice40/pack.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/ice40/pack.cc b/ice40/pack.cc
index f8944685f8..0a51332db2 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -1619,6 +1619,7 @@ void pack_plls(Context *ctx)
                 bool found_lut = false;
                 bool all_luts = true;
                 bool found_carry = false;
+                bool found_ff = false;
                 unsigned int lut_count = 0;
                 for (const auto &user : port.net->users) {
                     NPNR_ASSERT(user.cell != nullptr);
@@ -1626,6 +1627,10 @@ void pack_plls(Context *ctx)
                         if (bool_or_default(user.cell->params, id_CARRY_ENABLE, false)) {
                             found_carry = true;
                             all_luts = false;
+                        } else if (bool_or_default(user.cell->params, id_DFF_ENABLE, false)) {
+                            found_lut = true;
+                            found_ff = true;
+                            lut_count++;
                         } else {
                             found_lut = true;
                             lut_count++;
@@ -1635,9 +1640,9 @@ void pack_plls(Context *ctx)
                     }
                 }
 
-                if (found_lut && all_luts && lut_count < 8) {
+                if (found_lut && all_luts && (!found_ff || lut_count == 1) && lut_count < 8) {
                     // Every user is a LUT, carry on now.
-                } else if (found_lut && !all_luts && !found_carry && lut_count < 8) {
+                } else if (found_lut && !all_luts && !found_carry && !found_ff && lut_count < 8) {
                     // Strategy: create a pass-through LUT, move all non-LUT users behind it.
                     log_info("  LUT strategy for %s: move non-LUT users to new LUT\n", port.name.c_str(ctx));
                     auto pt = spliceLUT(ctx, packed.get(), port.name, true);